2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_rect.h>
44 #include <linux/dma_remapping.h>
46 /* Primary plane formats supported by all gen */
47 #define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_XRGB8888, \
53 /* Primary plane formats for gen <= 3 */
54 static const uint32_t intel_primary_formats_gen2
[] = {
55 COMMON_PRIMARY_FORMATS
,
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t intel_primary_formats_gen4
[] = {
62 COMMON_PRIMARY_FORMATS
, \
65 DRM_FORMAT_XRGB2101010
,
66 DRM_FORMAT_ARGB2101010
,
67 DRM_FORMAT_XBGR2101010
,
68 DRM_FORMAT_ABGR2101010
,
72 static const uint32_t intel_cursor_formats
[] = {
76 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
77 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
79 static void intel_increase_pllclock(struct drm_device
*dev
,
81 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
83 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
84 struct intel_crtc_config
*pipe_config
);
85 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
86 struct intel_crtc_config
*pipe_config
);
88 static int intel_set_mode(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
89 int x
, int y
, struct drm_framebuffer
*old_fb
);
90 static int intel_framebuffer_init(struct drm_device
*dev
,
91 struct intel_framebuffer
*ifb
,
92 struct drm_mode_fb_cmd2
*mode_cmd
,
93 struct drm_i915_gem_object
*obj
);
94 static void intel_dp_set_m_n(struct intel_crtc
*crtc
);
95 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
);
96 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
);
97 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
98 struct intel_link_m_n
*m_n
);
99 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
);
100 static void haswell_set_pipeconf(struct drm_crtc
*crtc
);
101 static void intel_set_pipe_csc(struct drm_crtc
*crtc
);
102 static void vlv_prepare_pll(struct intel_crtc
*crtc
);
110 int p2_slow
, p2_fast
;
113 typedef struct intel_limit intel_limit_t
;
115 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
120 intel_pch_rawclk(struct drm_device
*dev
)
122 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
124 WARN_ON(!HAS_PCH_SPLIT(dev
));
126 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
129 static inline u32
/* units of 100MHz */
130 intel_fdi_link_freq(struct drm_device
*dev
)
133 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
134 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
139 static const intel_limit_t intel_limits_i8xx_dac
= {
140 .dot
= { .min
= 25000, .max
= 350000 },
141 .vco
= { .min
= 908000, .max
= 1512000 },
142 .n
= { .min
= 2, .max
= 16 },
143 .m
= { .min
= 96, .max
= 140 },
144 .m1
= { .min
= 18, .max
= 26 },
145 .m2
= { .min
= 6, .max
= 16 },
146 .p
= { .min
= 4, .max
= 128 },
147 .p1
= { .min
= 2, .max
= 33 },
148 .p2
= { .dot_limit
= 165000,
149 .p2_slow
= 4, .p2_fast
= 2 },
152 static const intel_limit_t intel_limits_i8xx_dvo
= {
153 .dot
= { .min
= 25000, .max
= 350000 },
154 .vco
= { .min
= 908000, .max
= 1512000 },
155 .n
= { .min
= 2, .max
= 16 },
156 .m
= { .min
= 96, .max
= 140 },
157 .m1
= { .min
= 18, .max
= 26 },
158 .m2
= { .min
= 6, .max
= 16 },
159 .p
= { .min
= 4, .max
= 128 },
160 .p1
= { .min
= 2, .max
= 33 },
161 .p2
= { .dot_limit
= 165000,
162 .p2_slow
= 4, .p2_fast
= 4 },
165 static const intel_limit_t intel_limits_i8xx_lvds
= {
166 .dot
= { .min
= 25000, .max
= 350000 },
167 .vco
= { .min
= 908000, .max
= 1512000 },
168 .n
= { .min
= 2, .max
= 16 },
169 .m
= { .min
= 96, .max
= 140 },
170 .m1
= { .min
= 18, .max
= 26 },
171 .m2
= { .min
= 6, .max
= 16 },
172 .p
= { .min
= 4, .max
= 128 },
173 .p1
= { .min
= 1, .max
= 6 },
174 .p2
= { .dot_limit
= 165000,
175 .p2_slow
= 14, .p2_fast
= 7 },
178 static const intel_limit_t intel_limits_i9xx_sdvo
= {
179 .dot
= { .min
= 20000, .max
= 400000 },
180 .vco
= { .min
= 1400000, .max
= 2800000 },
181 .n
= { .min
= 1, .max
= 6 },
182 .m
= { .min
= 70, .max
= 120 },
183 .m1
= { .min
= 8, .max
= 18 },
184 .m2
= { .min
= 3, .max
= 7 },
185 .p
= { .min
= 5, .max
= 80 },
186 .p1
= { .min
= 1, .max
= 8 },
187 .p2
= { .dot_limit
= 200000,
188 .p2_slow
= 10, .p2_fast
= 5 },
191 static const intel_limit_t intel_limits_i9xx_lvds
= {
192 .dot
= { .min
= 20000, .max
= 400000 },
193 .vco
= { .min
= 1400000, .max
= 2800000 },
194 .n
= { .min
= 1, .max
= 6 },
195 .m
= { .min
= 70, .max
= 120 },
196 .m1
= { .min
= 8, .max
= 18 },
197 .m2
= { .min
= 3, .max
= 7 },
198 .p
= { .min
= 7, .max
= 98 },
199 .p1
= { .min
= 1, .max
= 8 },
200 .p2
= { .dot_limit
= 112000,
201 .p2_slow
= 14, .p2_fast
= 7 },
205 static const intel_limit_t intel_limits_g4x_sdvo
= {
206 .dot
= { .min
= 25000, .max
= 270000 },
207 .vco
= { .min
= 1750000, .max
= 3500000},
208 .n
= { .min
= 1, .max
= 4 },
209 .m
= { .min
= 104, .max
= 138 },
210 .m1
= { .min
= 17, .max
= 23 },
211 .m2
= { .min
= 5, .max
= 11 },
212 .p
= { .min
= 10, .max
= 30 },
213 .p1
= { .min
= 1, .max
= 3},
214 .p2
= { .dot_limit
= 270000,
220 static const intel_limit_t intel_limits_g4x_hdmi
= {
221 .dot
= { .min
= 22000, .max
= 400000 },
222 .vco
= { .min
= 1750000, .max
= 3500000},
223 .n
= { .min
= 1, .max
= 4 },
224 .m
= { .min
= 104, .max
= 138 },
225 .m1
= { .min
= 16, .max
= 23 },
226 .m2
= { .min
= 5, .max
= 11 },
227 .p
= { .min
= 5, .max
= 80 },
228 .p1
= { .min
= 1, .max
= 8},
229 .p2
= { .dot_limit
= 165000,
230 .p2_slow
= 10, .p2_fast
= 5 },
233 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
234 .dot
= { .min
= 20000, .max
= 115000 },
235 .vco
= { .min
= 1750000, .max
= 3500000 },
236 .n
= { .min
= 1, .max
= 3 },
237 .m
= { .min
= 104, .max
= 138 },
238 .m1
= { .min
= 17, .max
= 23 },
239 .m2
= { .min
= 5, .max
= 11 },
240 .p
= { .min
= 28, .max
= 112 },
241 .p1
= { .min
= 2, .max
= 8 },
242 .p2
= { .dot_limit
= 0,
243 .p2_slow
= 14, .p2_fast
= 14
247 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
248 .dot
= { .min
= 80000, .max
= 224000 },
249 .vco
= { .min
= 1750000, .max
= 3500000 },
250 .n
= { .min
= 1, .max
= 3 },
251 .m
= { .min
= 104, .max
= 138 },
252 .m1
= { .min
= 17, .max
= 23 },
253 .m2
= { .min
= 5, .max
= 11 },
254 .p
= { .min
= 14, .max
= 42 },
255 .p1
= { .min
= 2, .max
= 6 },
256 .p2
= { .dot_limit
= 0,
257 .p2_slow
= 7, .p2_fast
= 7
261 static const intel_limit_t intel_limits_pineview_sdvo
= {
262 .dot
= { .min
= 20000, .max
= 400000},
263 .vco
= { .min
= 1700000, .max
= 3500000 },
264 /* Pineview's Ncounter is a ring counter */
265 .n
= { .min
= 3, .max
= 6 },
266 .m
= { .min
= 2, .max
= 256 },
267 /* Pineview only has one combined m divider, which we treat as m2. */
268 .m1
= { .min
= 0, .max
= 0 },
269 .m2
= { .min
= 0, .max
= 254 },
270 .p
= { .min
= 5, .max
= 80 },
271 .p1
= { .min
= 1, .max
= 8 },
272 .p2
= { .dot_limit
= 200000,
273 .p2_slow
= 10, .p2_fast
= 5 },
276 static const intel_limit_t intel_limits_pineview_lvds
= {
277 .dot
= { .min
= 20000, .max
= 400000 },
278 .vco
= { .min
= 1700000, .max
= 3500000 },
279 .n
= { .min
= 3, .max
= 6 },
280 .m
= { .min
= 2, .max
= 256 },
281 .m1
= { .min
= 0, .max
= 0 },
282 .m2
= { .min
= 0, .max
= 254 },
283 .p
= { .min
= 7, .max
= 112 },
284 .p1
= { .min
= 1, .max
= 8 },
285 .p2
= { .dot_limit
= 112000,
286 .p2_slow
= 14, .p2_fast
= 14 },
289 /* Ironlake / Sandybridge
291 * We calculate clock using (register_value + 2) for N/M1/M2, so here
292 * the range value for them is (actual_value - 2).
294 static const intel_limit_t intel_limits_ironlake_dac
= {
295 .dot
= { .min
= 25000, .max
= 350000 },
296 .vco
= { .min
= 1760000, .max
= 3510000 },
297 .n
= { .min
= 1, .max
= 5 },
298 .m
= { .min
= 79, .max
= 127 },
299 .m1
= { .min
= 12, .max
= 22 },
300 .m2
= { .min
= 5, .max
= 9 },
301 .p
= { .min
= 5, .max
= 80 },
302 .p1
= { .min
= 1, .max
= 8 },
303 .p2
= { .dot_limit
= 225000,
304 .p2_slow
= 10, .p2_fast
= 5 },
307 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
308 .dot
= { .min
= 25000, .max
= 350000 },
309 .vco
= { .min
= 1760000, .max
= 3510000 },
310 .n
= { .min
= 1, .max
= 3 },
311 .m
= { .min
= 79, .max
= 118 },
312 .m1
= { .min
= 12, .max
= 22 },
313 .m2
= { .min
= 5, .max
= 9 },
314 .p
= { .min
= 28, .max
= 112 },
315 .p1
= { .min
= 2, .max
= 8 },
316 .p2
= { .dot_limit
= 225000,
317 .p2_slow
= 14, .p2_fast
= 14 },
320 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
321 .dot
= { .min
= 25000, .max
= 350000 },
322 .vco
= { .min
= 1760000, .max
= 3510000 },
323 .n
= { .min
= 1, .max
= 3 },
324 .m
= { .min
= 79, .max
= 127 },
325 .m1
= { .min
= 12, .max
= 22 },
326 .m2
= { .min
= 5, .max
= 9 },
327 .p
= { .min
= 14, .max
= 56 },
328 .p1
= { .min
= 2, .max
= 8 },
329 .p2
= { .dot_limit
= 225000,
330 .p2_slow
= 7, .p2_fast
= 7 },
333 /* LVDS 100mhz refclk limits. */
334 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
335 .dot
= { .min
= 25000, .max
= 350000 },
336 .vco
= { .min
= 1760000, .max
= 3510000 },
337 .n
= { .min
= 1, .max
= 2 },
338 .m
= { .min
= 79, .max
= 126 },
339 .m1
= { .min
= 12, .max
= 22 },
340 .m2
= { .min
= 5, .max
= 9 },
341 .p
= { .min
= 28, .max
= 112 },
342 .p1
= { .min
= 2, .max
= 8 },
343 .p2
= { .dot_limit
= 225000,
344 .p2_slow
= 14, .p2_fast
= 14 },
347 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
348 .dot
= { .min
= 25000, .max
= 350000 },
349 .vco
= { .min
= 1760000, .max
= 3510000 },
350 .n
= { .min
= 1, .max
= 3 },
351 .m
= { .min
= 79, .max
= 126 },
352 .m1
= { .min
= 12, .max
= 22 },
353 .m2
= { .min
= 5, .max
= 9 },
354 .p
= { .min
= 14, .max
= 42 },
355 .p1
= { .min
= 2, .max
= 6 },
356 .p2
= { .dot_limit
= 225000,
357 .p2_slow
= 7, .p2_fast
= 7 },
360 static const intel_limit_t intel_limits_vlv
= {
362 * These are the data rate limits (measured in fast clocks)
363 * since those are the strictest limits we have. The fast
364 * clock and actual rate limits are more relaxed, so checking
365 * them would make no difference.
367 .dot
= { .min
= 25000 * 5, .max
= 270000 * 5 },
368 .vco
= { .min
= 4000000, .max
= 6000000 },
369 .n
= { .min
= 1, .max
= 7 },
370 .m1
= { .min
= 2, .max
= 3 },
371 .m2
= { .min
= 11, .max
= 156 },
372 .p1
= { .min
= 2, .max
= 3 },
373 .p2
= { .p2_slow
= 2, .p2_fast
= 20 }, /* slow=min, fast=max */
376 static const intel_limit_t intel_limits_chv
= {
378 * These are the data rate limits (measured in fast clocks)
379 * since those are the strictest limits we have. The fast
380 * clock and actual rate limits are more relaxed, so checking
381 * them would make no difference.
383 .dot
= { .min
= 25000 * 5, .max
= 540000 * 5},
384 .vco
= { .min
= 4860000, .max
= 6700000 },
385 .n
= { .min
= 1, .max
= 1 },
386 .m1
= { .min
= 2, .max
= 2 },
387 .m2
= { .min
= 24 << 22, .max
= 175 << 22 },
388 .p1
= { .min
= 2, .max
= 4 },
389 .p2
= { .p2_slow
= 1, .p2_fast
= 14 },
392 static void vlv_clock(int refclk
, intel_clock_t
*clock
)
394 clock
->m
= clock
->m1
* clock
->m2
;
395 clock
->p
= clock
->p1
* clock
->p2
;
396 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
398 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
399 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
403 * Returns whether any output on the specified pipe is of the specified type
405 static bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
407 struct drm_device
*dev
= crtc
->dev
;
408 struct intel_encoder
*encoder
;
410 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
411 if (encoder
->type
== type
)
417 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
,
420 struct drm_device
*dev
= crtc
->dev
;
421 const intel_limit_t
*limit
;
423 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
424 if (intel_is_dual_link_lvds(dev
)) {
425 if (refclk
== 100000)
426 limit
= &intel_limits_ironlake_dual_lvds_100m
;
428 limit
= &intel_limits_ironlake_dual_lvds
;
430 if (refclk
== 100000)
431 limit
= &intel_limits_ironlake_single_lvds_100m
;
433 limit
= &intel_limits_ironlake_single_lvds
;
436 limit
= &intel_limits_ironlake_dac
;
441 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
443 struct drm_device
*dev
= crtc
->dev
;
444 const intel_limit_t
*limit
;
446 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
447 if (intel_is_dual_link_lvds(dev
))
448 limit
= &intel_limits_g4x_dual_channel_lvds
;
450 limit
= &intel_limits_g4x_single_channel_lvds
;
451 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
452 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
453 limit
= &intel_limits_g4x_hdmi
;
454 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
455 limit
= &intel_limits_g4x_sdvo
;
456 } else /* The option is for other outputs */
457 limit
= &intel_limits_i9xx_sdvo
;
462 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
, int refclk
)
464 struct drm_device
*dev
= crtc
->dev
;
465 const intel_limit_t
*limit
;
467 if (HAS_PCH_SPLIT(dev
))
468 limit
= intel_ironlake_limit(crtc
, refclk
);
469 else if (IS_G4X(dev
)) {
470 limit
= intel_g4x_limit(crtc
);
471 } else if (IS_PINEVIEW(dev
)) {
472 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
473 limit
= &intel_limits_pineview_lvds
;
475 limit
= &intel_limits_pineview_sdvo
;
476 } else if (IS_CHERRYVIEW(dev
)) {
477 limit
= &intel_limits_chv
;
478 } else if (IS_VALLEYVIEW(dev
)) {
479 limit
= &intel_limits_vlv
;
480 } else if (!IS_GEN2(dev
)) {
481 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
482 limit
= &intel_limits_i9xx_lvds
;
484 limit
= &intel_limits_i9xx_sdvo
;
486 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
487 limit
= &intel_limits_i8xx_lvds
;
488 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
))
489 limit
= &intel_limits_i8xx_dvo
;
491 limit
= &intel_limits_i8xx_dac
;
496 /* m1 is reserved as 0 in Pineview, n is a ring counter */
497 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
499 clock
->m
= clock
->m2
+ 2;
500 clock
->p
= clock
->p1
* clock
->p2
;
501 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
503 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
504 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
507 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
509 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
512 static void i9xx_clock(int refclk
, intel_clock_t
*clock
)
514 clock
->m
= i9xx_dpll_compute_m(clock
);
515 clock
->p
= clock
->p1
* clock
->p2
;
516 if (WARN_ON(clock
->n
+ 2 == 0 || clock
->p
== 0))
518 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
+ 2);
519 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
522 static void chv_clock(int refclk
, intel_clock_t
*clock
)
524 clock
->m
= clock
->m1
* clock
->m2
;
525 clock
->p
= clock
->p1
* clock
->p2
;
526 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
528 clock
->vco
= DIV_ROUND_CLOSEST_ULL((uint64_t)refclk
* clock
->m
,
530 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
533 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
535 * Returns whether the given set of divisors are valid for a given refclk with
536 * the given connectors.
539 static bool intel_PLL_is_valid(struct drm_device
*dev
,
540 const intel_limit_t
*limit
,
541 const intel_clock_t
*clock
)
543 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
544 INTELPllInvalid("n out of range\n");
545 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
546 INTELPllInvalid("p1 out of range\n");
547 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
548 INTELPllInvalid("m2 out of range\n");
549 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
550 INTELPllInvalid("m1 out of range\n");
552 if (!IS_PINEVIEW(dev
) && !IS_VALLEYVIEW(dev
))
553 if (clock
->m1
<= clock
->m2
)
554 INTELPllInvalid("m1 <= m2\n");
556 if (!IS_VALLEYVIEW(dev
)) {
557 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
558 INTELPllInvalid("p out of range\n");
559 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
560 INTELPllInvalid("m out of range\n");
563 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
564 INTELPllInvalid("vco out of range\n");
565 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
566 * connector, etc., rather than just a single range.
568 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
569 INTELPllInvalid("dot out of range\n");
575 i9xx_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
576 int target
, int refclk
, intel_clock_t
*match_clock
,
577 intel_clock_t
*best_clock
)
579 struct drm_device
*dev
= crtc
->dev
;
583 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
585 * For LVDS just rely on its current settings for dual-channel.
586 * We haven't figured out how to reliably set up different
587 * single/dual channel state, if we even can.
589 if (intel_is_dual_link_lvds(dev
))
590 clock
.p2
= limit
->p2
.p2_fast
;
592 clock
.p2
= limit
->p2
.p2_slow
;
594 if (target
< limit
->p2
.dot_limit
)
595 clock
.p2
= limit
->p2
.p2_slow
;
597 clock
.p2
= limit
->p2
.p2_fast
;
600 memset(best_clock
, 0, sizeof(*best_clock
));
602 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
604 for (clock
.m2
= limit
->m2
.min
;
605 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
606 if (clock
.m2
>= clock
.m1
)
608 for (clock
.n
= limit
->n
.min
;
609 clock
.n
<= limit
->n
.max
; clock
.n
++) {
610 for (clock
.p1
= limit
->p1
.min
;
611 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
614 i9xx_clock(refclk
, &clock
);
615 if (!intel_PLL_is_valid(dev
, limit
,
619 clock
.p
!= match_clock
->p
)
622 this_err
= abs(clock
.dot
- target
);
623 if (this_err
< err
) {
632 return (err
!= target
);
636 pnv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
637 int target
, int refclk
, intel_clock_t
*match_clock
,
638 intel_clock_t
*best_clock
)
640 struct drm_device
*dev
= crtc
->dev
;
644 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
646 * For LVDS just rely on its current settings for dual-channel.
647 * We haven't figured out how to reliably set up different
648 * single/dual channel state, if we even can.
650 if (intel_is_dual_link_lvds(dev
))
651 clock
.p2
= limit
->p2
.p2_fast
;
653 clock
.p2
= limit
->p2
.p2_slow
;
655 if (target
< limit
->p2
.dot_limit
)
656 clock
.p2
= limit
->p2
.p2_slow
;
658 clock
.p2
= limit
->p2
.p2_fast
;
661 memset(best_clock
, 0, sizeof(*best_clock
));
663 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
665 for (clock
.m2
= limit
->m2
.min
;
666 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
667 for (clock
.n
= limit
->n
.min
;
668 clock
.n
<= limit
->n
.max
; clock
.n
++) {
669 for (clock
.p1
= limit
->p1
.min
;
670 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
673 pineview_clock(refclk
, &clock
);
674 if (!intel_PLL_is_valid(dev
, limit
,
678 clock
.p
!= match_clock
->p
)
681 this_err
= abs(clock
.dot
- target
);
682 if (this_err
< err
) {
691 return (err
!= target
);
695 g4x_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
696 int target
, int refclk
, intel_clock_t
*match_clock
,
697 intel_clock_t
*best_clock
)
699 struct drm_device
*dev
= crtc
->dev
;
703 /* approximately equals target * 0.00585 */
704 int err_most
= (target
>> 8) + (target
>> 9);
707 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
708 if (intel_is_dual_link_lvds(dev
))
709 clock
.p2
= limit
->p2
.p2_fast
;
711 clock
.p2
= limit
->p2
.p2_slow
;
713 if (target
< limit
->p2
.dot_limit
)
714 clock
.p2
= limit
->p2
.p2_slow
;
716 clock
.p2
= limit
->p2
.p2_fast
;
719 memset(best_clock
, 0, sizeof(*best_clock
));
720 max_n
= limit
->n
.max
;
721 /* based on hardware requirement, prefer smaller n to precision */
722 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
723 /* based on hardware requirement, prefere larger m1,m2 */
724 for (clock
.m1
= limit
->m1
.max
;
725 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
726 for (clock
.m2
= limit
->m2
.max
;
727 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
728 for (clock
.p1
= limit
->p1
.max
;
729 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
732 i9xx_clock(refclk
, &clock
);
733 if (!intel_PLL_is_valid(dev
, limit
,
737 this_err
= abs(clock
.dot
- target
);
738 if (this_err
< err_most
) {
752 vlv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
753 int target
, int refclk
, intel_clock_t
*match_clock
,
754 intel_clock_t
*best_clock
)
756 struct drm_device
*dev
= crtc
->dev
;
758 unsigned int bestppm
= 1000000;
759 /* min update 19.2 MHz */
760 int max_n
= min(limit
->n
.max
, refclk
/ 19200);
763 target
*= 5; /* fast clock */
765 memset(best_clock
, 0, sizeof(*best_clock
));
767 /* based on hardware requirement, prefer smaller n to precision */
768 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
769 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
770 for (clock
.p2
= limit
->p2
.p2_fast
; clock
.p2
>= limit
->p2
.p2_slow
;
771 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
772 clock
.p
= clock
.p1
* clock
.p2
;
773 /* based on hardware requirement, prefer bigger m1,m2 values */
774 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
775 unsigned int ppm
, diff
;
777 clock
.m2
= DIV_ROUND_CLOSEST(target
* clock
.p
* clock
.n
,
780 vlv_clock(refclk
, &clock
);
782 if (!intel_PLL_is_valid(dev
, limit
,
786 diff
= abs(clock
.dot
- target
);
787 ppm
= div_u64(1000000ULL * diff
, target
);
789 if (ppm
< 100 && clock
.p
> best_clock
->p
) {
795 if (bestppm
>= 10 && ppm
< bestppm
- 10) {
809 chv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
810 int target
, int refclk
, intel_clock_t
*match_clock
,
811 intel_clock_t
*best_clock
)
813 struct drm_device
*dev
= crtc
->dev
;
818 memset(best_clock
, 0, sizeof(*best_clock
));
821 * Based on hardware doc, the n always set to 1, and m1 always
822 * set to 2. If requires to support 200Mhz refclk, we need to
823 * revisit this because n may not 1 anymore.
825 clock
.n
= 1, clock
.m1
= 2;
826 target
*= 5; /* fast clock */
828 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
829 for (clock
.p2
= limit
->p2
.p2_fast
;
830 clock
.p2
>= limit
->p2
.p2_slow
;
831 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
833 clock
.p
= clock
.p1
* clock
.p2
;
835 m2
= DIV_ROUND_CLOSEST_ULL(((uint64_t)target
* clock
.p
*
836 clock
.n
) << 22, refclk
* clock
.m1
);
838 if (m2
> INT_MAX
/clock
.m1
)
843 chv_clock(refclk
, &clock
);
845 if (!intel_PLL_is_valid(dev
, limit
, &clock
))
848 /* based on hardware requirement, prefer bigger p
850 if (clock
.p
> best_clock
->p
) {
860 bool intel_crtc_active(struct drm_crtc
*crtc
)
862 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
864 /* Be paranoid as we can arrive here with only partial
865 * state retrieved from the hardware during setup.
867 * We can ditch the adjusted_mode.crtc_clock check as soon
868 * as Haswell has gained clock readout/fastboot support.
870 * We can ditch the crtc->primary->fb check as soon as we can
871 * properly reconstruct framebuffers.
873 return intel_crtc
->active
&& crtc
->primary
->fb
&&
874 intel_crtc
->config
.adjusted_mode
.crtc_clock
;
877 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
880 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
881 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
883 return intel_crtc
->config
.cpu_transcoder
;
886 static void g4x_wait_for_vblank(struct drm_device
*dev
, int pipe
)
888 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
889 u32 frame
, frame_reg
= PIPE_FRMCOUNT_GM45(pipe
);
891 frame
= I915_READ(frame_reg
);
893 if (wait_for(I915_READ_NOTRACE(frame_reg
) != frame
, 50))
894 WARN(1, "vblank wait timed out\n");
898 * intel_wait_for_vblank - wait for vblank on a given pipe
900 * @pipe: pipe to wait for
902 * Wait for vblank to occur on a given pipe. Needed for various bits of
905 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
907 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
908 int pipestat_reg
= PIPESTAT(pipe
);
910 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
911 g4x_wait_for_vblank(dev
, pipe
);
915 /* Clear existing vblank status. Note this will clear any other
916 * sticky status fields as well.
918 * This races with i915_driver_irq_handler() with the result
919 * that either function could miss a vblank event. Here it is not
920 * fatal, as we will either wait upon the next vblank interrupt or
921 * timeout. Generally speaking intel_wait_for_vblank() is only
922 * called during modeset at which time the GPU should be idle and
923 * should *not* be performing page flips and thus not waiting on
925 * Currently, the result of us stealing a vblank from the irq
926 * handler is that a single frame will be skipped during swapbuffers.
928 I915_WRITE(pipestat_reg
,
929 I915_READ(pipestat_reg
) | PIPE_VBLANK_INTERRUPT_STATUS
);
931 /* Wait for vblank interrupt bit to set */
932 if (wait_for(I915_READ(pipestat_reg
) &
933 PIPE_VBLANK_INTERRUPT_STATUS
,
935 DRM_DEBUG_KMS("vblank wait timed out\n");
938 static bool pipe_dsl_stopped(struct drm_device
*dev
, enum pipe pipe
)
940 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
941 u32 reg
= PIPEDSL(pipe
);
946 line_mask
= DSL_LINEMASK_GEN2
;
948 line_mask
= DSL_LINEMASK_GEN3
;
950 line1
= I915_READ(reg
) & line_mask
;
952 line2
= I915_READ(reg
) & line_mask
;
954 return line1
== line2
;
958 * intel_wait_for_pipe_off - wait for pipe to turn off
960 * @pipe: pipe to wait for
962 * After disabling a pipe, we can't wait for vblank in the usual way,
963 * spinning on the vblank interrupt status bit, since we won't actually
964 * see an interrupt when the pipe is disabled.
967 * wait for the pipe register state bit to turn off
970 * wait for the display line value to settle (it usually
971 * ends up stopping at the start of the next frame).
974 void intel_wait_for_pipe_off(struct drm_device
*dev
, int pipe
)
976 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
977 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
980 if (INTEL_INFO(dev
)->gen
>= 4) {
981 int reg
= PIPECONF(cpu_transcoder
);
983 /* Wait for the Pipe State to go off */
984 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
986 WARN(1, "pipe_off wait timed out\n");
988 /* Wait for the display line to settle */
989 if (wait_for(pipe_dsl_stopped(dev
, pipe
), 100))
990 WARN(1, "pipe_off wait timed out\n");
995 * ibx_digital_port_connected - is the specified port connected?
996 * @dev_priv: i915 private structure
997 * @port: the port to test
999 * Returns true if @port is connected, false otherwise.
1001 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
1002 struct intel_digital_port
*port
)
1006 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1007 switch (port
->port
) {
1009 bit
= SDE_PORTB_HOTPLUG
;
1012 bit
= SDE_PORTC_HOTPLUG
;
1015 bit
= SDE_PORTD_HOTPLUG
;
1021 switch (port
->port
) {
1023 bit
= SDE_PORTB_HOTPLUG_CPT
;
1026 bit
= SDE_PORTC_HOTPLUG_CPT
;
1029 bit
= SDE_PORTD_HOTPLUG_CPT
;
1036 return I915_READ(SDEISR
) & bit
;
1039 static const char *state_string(bool enabled
)
1041 return enabled
? "on" : "off";
1044 /* Only for pre-ILK configs */
1045 void assert_pll(struct drm_i915_private
*dev_priv
,
1046 enum pipe pipe
, bool state
)
1053 val
= I915_READ(reg
);
1054 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1055 WARN(cur_state
!= state
,
1056 "PLL state assertion failure (expected %s, current %s)\n",
1057 state_string(state
), state_string(cur_state
));
1060 /* XXX: the dsi pll is shared between MIPI DSI ports */
1061 static void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
1066 mutex_lock(&dev_priv
->dpio_lock
);
1067 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
1068 mutex_unlock(&dev_priv
->dpio_lock
);
1070 cur_state
= val
& DSI_PLL_VCO_EN
;
1071 WARN(cur_state
!= state
,
1072 "DSI PLL state assertion failure (expected %s, current %s)\n",
1073 state_string(state
), state_string(cur_state
));
1075 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1076 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1078 struct intel_shared_dpll
*
1079 intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
)
1081 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1083 if (crtc
->config
.shared_dpll
< 0)
1086 return &dev_priv
->shared_dplls
[crtc
->config
.shared_dpll
];
1090 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
1091 struct intel_shared_dpll
*pll
,
1095 struct intel_dpll_hw_state hw_state
;
1097 if (HAS_PCH_LPT(dev_priv
->dev
)) {
1098 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1103 "asserting DPLL %s with no DPLL\n", state_string(state
)))
1106 cur_state
= pll
->get_hw_state(dev_priv
, pll
, &hw_state
);
1107 WARN(cur_state
!= state
,
1108 "%s assertion failure (expected %s, current %s)\n",
1109 pll
->name
, state_string(state
), state_string(cur_state
));
1112 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1113 enum pipe pipe
, bool state
)
1118 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1121 if (HAS_DDI(dev_priv
->dev
)) {
1122 /* DDI does not have a specific FDI_TX register */
1123 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1124 val
= I915_READ(reg
);
1125 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1127 reg
= FDI_TX_CTL(pipe
);
1128 val
= I915_READ(reg
);
1129 cur_state
= !!(val
& FDI_TX_ENABLE
);
1131 WARN(cur_state
!= state
,
1132 "FDI TX state assertion failure (expected %s, current %s)\n",
1133 state_string(state
), state_string(cur_state
));
1135 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1136 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1138 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1139 enum pipe pipe
, bool state
)
1145 reg
= FDI_RX_CTL(pipe
);
1146 val
= I915_READ(reg
);
1147 cur_state
= !!(val
& FDI_RX_ENABLE
);
1148 WARN(cur_state
!= state
,
1149 "FDI RX state assertion failure (expected %s, current %s)\n",
1150 state_string(state
), state_string(cur_state
));
1152 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1153 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1155 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1161 /* ILK FDI PLL is always enabled */
1162 if (INTEL_INFO(dev_priv
->dev
)->gen
== 5)
1165 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1166 if (HAS_DDI(dev_priv
->dev
))
1169 reg
= FDI_TX_CTL(pipe
);
1170 val
= I915_READ(reg
);
1171 WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1174 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1175 enum pipe pipe
, bool state
)
1181 reg
= FDI_RX_CTL(pipe
);
1182 val
= I915_READ(reg
);
1183 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1184 WARN(cur_state
!= state
,
1185 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1186 state_string(state
), state_string(cur_state
));
1189 static void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1192 int pp_reg
, lvds_reg
;
1194 enum pipe panel_pipe
= PIPE_A
;
1197 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
1198 pp_reg
= PCH_PP_CONTROL
;
1199 lvds_reg
= PCH_LVDS
;
1201 pp_reg
= PP_CONTROL
;
1205 val
= I915_READ(pp_reg
);
1206 if (!(val
& PANEL_POWER_ON
) ||
1207 ((val
& PANEL_UNLOCK_REGS
) == PANEL_UNLOCK_REGS
))
1210 if (I915_READ(lvds_reg
) & LVDS_PIPEB_SELECT
)
1211 panel_pipe
= PIPE_B
;
1213 WARN(panel_pipe
== pipe
&& locked
,
1214 "panel assertion failure, pipe %c regs locked\n",
1218 static void assert_cursor(struct drm_i915_private
*dev_priv
,
1219 enum pipe pipe
, bool state
)
1221 struct drm_device
*dev
= dev_priv
->dev
;
1224 if (IS_845G(dev
) || IS_I865G(dev
))
1225 cur_state
= I915_READ(_CURACNTR
) & CURSOR_ENABLE
;
1227 cur_state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
1229 WARN(cur_state
!= state
,
1230 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1231 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1233 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1234 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1236 void assert_pipe(struct drm_i915_private
*dev_priv
,
1237 enum pipe pipe
, bool state
)
1242 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1245 /* if we need the pipe A quirk it must be always on */
1246 if (pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
1249 if (!intel_display_power_enabled(dev_priv
,
1250 POWER_DOMAIN_TRANSCODER(cpu_transcoder
))) {
1253 reg
= PIPECONF(cpu_transcoder
);
1254 val
= I915_READ(reg
);
1255 cur_state
= !!(val
& PIPECONF_ENABLE
);
1258 WARN(cur_state
!= state
,
1259 "pipe %c assertion failure (expected %s, current %s)\n",
1260 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1263 static void assert_plane(struct drm_i915_private
*dev_priv
,
1264 enum plane plane
, bool state
)
1270 reg
= DSPCNTR(plane
);
1271 val
= I915_READ(reg
);
1272 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1273 WARN(cur_state
!= state
,
1274 "plane %c assertion failure (expected %s, current %s)\n",
1275 plane_name(plane
), state_string(state
), state_string(cur_state
));
1278 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1279 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1281 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1284 struct drm_device
*dev
= dev_priv
->dev
;
1289 /* Primary planes are fixed to pipes on gen4+ */
1290 if (INTEL_INFO(dev
)->gen
>= 4) {
1291 reg
= DSPCNTR(pipe
);
1292 val
= I915_READ(reg
);
1293 WARN(val
& DISPLAY_PLANE_ENABLE
,
1294 "plane %c assertion failure, should be disabled but not\n",
1299 /* Need to check both planes against the pipe */
1302 val
= I915_READ(reg
);
1303 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1304 DISPPLANE_SEL_PIPE_SHIFT
;
1305 WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1306 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1307 plane_name(i
), pipe_name(pipe
));
1311 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1314 struct drm_device
*dev
= dev_priv
->dev
;
1318 if (IS_VALLEYVIEW(dev
)) {
1319 for_each_sprite(pipe
, sprite
) {
1320 reg
= SPCNTR(pipe
, sprite
);
1321 val
= I915_READ(reg
);
1322 WARN(val
& SP_ENABLE
,
1323 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1324 sprite_name(pipe
, sprite
), pipe_name(pipe
));
1326 } else if (INTEL_INFO(dev
)->gen
>= 7) {
1328 val
= I915_READ(reg
);
1329 WARN(val
& SPRITE_ENABLE
,
1330 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1331 plane_name(pipe
), pipe_name(pipe
));
1332 } else if (INTEL_INFO(dev
)->gen
>= 5) {
1333 reg
= DVSCNTR(pipe
);
1334 val
= I915_READ(reg
);
1335 WARN(val
& DVS_ENABLE
,
1336 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1337 plane_name(pipe
), pipe_name(pipe
));
1341 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1346 WARN_ON(!(HAS_PCH_IBX(dev_priv
->dev
) || HAS_PCH_CPT(dev_priv
->dev
)));
1348 val
= I915_READ(PCH_DREF_CONTROL
);
1349 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1350 DREF_SUPERSPREAD_SOURCE_MASK
));
1351 WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1354 static void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1361 reg
= PCH_TRANSCONF(pipe
);
1362 val
= I915_READ(reg
);
1363 enabled
= !!(val
& TRANS_ENABLE
);
1365 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1369 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1370 enum pipe pipe
, u32 port_sel
, u32 val
)
1372 if ((val
& DP_PORT_EN
) == 0)
1375 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1376 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1377 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1378 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1380 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1381 if ((val
& DP_PIPE_MASK_CHV
) != DP_PIPE_SELECT_CHV(pipe
))
1384 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1390 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1391 enum pipe pipe
, u32 val
)
1393 if ((val
& SDVO_ENABLE
) == 0)
1396 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1397 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1399 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1400 if ((val
& SDVO_PIPE_SEL_MASK_CHV
) != SDVO_PIPE_SEL_CHV(pipe
))
1403 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1409 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1410 enum pipe pipe
, u32 val
)
1412 if ((val
& LVDS_PORT_EN
) == 0)
1415 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1416 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1419 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1425 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1426 enum pipe pipe
, u32 val
)
1428 if ((val
& ADPA_DAC_ENABLE
) == 0)
1430 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1431 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1434 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1440 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1441 enum pipe pipe
, int reg
, u32 port_sel
)
1443 u32 val
= I915_READ(reg
);
1444 WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1445 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1446 reg
, pipe_name(pipe
));
1448 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1449 && (val
& DP_PIPEB_SELECT
),
1450 "IBX PCH dp port still using transcoder B\n");
1453 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1454 enum pipe pipe
, int reg
)
1456 u32 val
= I915_READ(reg
);
1457 WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1458 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1459 reg
, pipe_name(pipe
));
1461 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_ENABLE
) == 0
1462 && (val
& SDVO_PIPE_B_SELECT
),
1463 "IBX PCH hdmi port still using transcoder B\n");
1466 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1472 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1473 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1474 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1477 val
= I915_READ(reg
);
1478 WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1479 "PCH VGA enabled on transcoder %c, should be disabled\n",
1483 val
= I915_READ(reg
);
1484 WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1485 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1488 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1489 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1490 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1493 static void intel_init_dpio(struct drm_device
*dev
)
1495 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1497 if (!IS_VALLEYVIEW(dev
))
1501 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1502 * CHV x1 PHY (DP/HDMI D)
1503 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1505 if (IS_CHERRYVIEW(dev
)) {
1506 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO_2
;
1507 DPIO_PHY_IOSF_PORT(DPIO_PHY1
) = IOSF_PORT_DPIO
;
1509 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO
;
1513 static void intel_reset_dpio(struct drm_device
*dev
)
1515 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1517 if (IS_CHERRYVIEW(dev
)) {
1521 for (phy
= DPIO_PHY0
; phy
< I915_NUM_PHYS_VLV
; phy
++) {
1522 /* Poll for phypwrgood signal */
1523 if (wait_for(I915_READ(DISPLAY_PHY_STATUS
) &
1524 PHY_POWERGOOD(phy
), 1))
1525 DRM_ERROR("Display PHY %d is not power up\n", phy
);
1528 * Deassert common lane reset for PHY.
1530 * This should only be done on init and resume from S3
1531 * with both PLLs disabled, or we risk losing DPIO and
1532 * PLL synchronization.
1534 val
= I915_READ(DISPLAY_PHY_CONTROL
);
1535 I915_WRITE(DISPLAY_PHY_CONTROL
,
1536 PHY_COM_LANE_RESET_DEASSERT(phy
, val
));
1541 static void vlv_enable_pll(struct intel_crtc
*crtc
)
1543 struct drm_device
*dev
= crtc
->base
.dev
;
1544 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1545 int reg
= DPLL(crtc
->pipe
);
1546 u32 dpll
= crtc
->config
.dpll_hw_state
.dpll
;
1548 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1550 /* No really, not for ILK+ */
1551 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
));
1553 /* PLL is protected by panel, make sure we can write it */
1554 if (IS_MOBILE(dev_priv
->dev
) && !IS_I830(dev_priv
->dev
))
1555 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1557 I915_WRITE(reg
, dpll
);
1561 if (wait_for(((I915_READ(reg
) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1562 DRM_ERROR("DPLL %d failed to lock\n", crtc
->pipe
);
1564 I915_WRITE(DPLL_MD(crtc
->pipe
), crtc
->config
.dpll_hw_state
.dpll_md
);
1565 POSTING_READ(DPLL_MD(crtc
->pipe
));
1567 /* We do this three times for luck */
1568 I915_WRITE(reg
, dpll
);
1570 udelay(150); /* wait for warmup */
1571 I915_WRITE(reg
, dpll
);
1573 udelay(150); /* wait for warmup */
1574 I915_WRITE(reg
, dpll
);
1576 udelay(150); /* wait for warmup */
1579 static void chv_enable_pll(struct intel_crtc
*crtc
)
1581 struct drm_device
*dev
= crtc
->base
.dev
;
1582 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1583 int pipe
= crtc
->pipe
;
1584 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1587 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1589 BUG_ON(!IS_CHERRYVIEW(dev_priv
->dev
));
1591 mutex_lock(&dev_priv
->dpio_lock
);
1593 /* Enable back the 10bit clock to display controller */
1594 tmp
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1595 tmp
|= DPIO_DCLKP_EN
;
1596 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), tmp
);
1599 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1604 I915_WRITE(DPLL(pipe
), crtc
->config
.dpll_hw_state
.dpll
);
1606 /* Check PLL is locked */
1607 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1608 DRM_ERROR("PLL %d failed to lock\n", pipe
);
1610 /* not sure when this should be written */
1611 I915_WRITE(DPLL_MD(pipe
), crtc
->config
.dpll_hw_state
.dpll_md
);
1612 POSTING_READ(DPLL_MD(pipe
));
1614 mutex_unlock(&dev_priv
->dpio_lock
);
1617 static void i9xx_enable_pll(struct intel_crtc
*crtc
)
1619 struct drm_device
*dev
= crtc
->base
.dev
;
1620 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1621 int reg
= DPLL(crtc
->pipe
);
1622 u32 dpll
= crtc
->config
.dpll_hw_state
.dpll
;
1624 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1626 /* No really, not for ILK+ */
1627 BUG_ON(INTEL_INFO(dev
)->gen
>= 5);
1629 /* PLL is protected by panel, make sure we can write it */
1630 if (IS_MOBILE(dev
) && !IS_I830(dev
))
1631 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1633 I915_WRITE(reg
, dpll
);
1635 /* Wait for the clocks to stabilize. */
1639 if (INTEL_INFO(dev
)->gen
>= 4) {
1640 I915_WRITE(DPLL_MD(crtc
->pipe
),
1641 crtc
->config
.dpll_hw_state
.dpll_md
);
1643 /* The pixel multiplier can only be updated once the
1644 * DPLL is enabled and the clocks are stable.
1646 * So write it again.
1648 I915_WRITE(reg
, dpll
);
1651 /* We do this three times for luck */
1652 I915_WRITE(reg
, dpll
);
1654 udelay(150); /* wait for warmup */
1655 I915_WRITE(reg
, dpll
);
1657 udelay(150); /* wait for warmup */
1658 I915_WRITE(reg
, dpll
);
1660 udelay(150); /* wait for warmup */
1664 * i9xx_disable_pll - disable a PLL
1665 * @dev_priv: i915 private structure
1666 * @pipe: pipe PLL to disable
1668 * Disable the PLL for @pipe, making sure the pipe is off first.
1670 * Note! This is for pre-ILK only.
1672 static void i9xx_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1674 /* Don't disable pipe A or pipe A PLLs if needed */
1675 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1678 /* Make sure the pipe isn't still relying on us */
1679 assert_pipe_disabled(dev_priv
, pipe
);
1681 I915_WRITE(DPLL(pipe
), 0);
1682 POSTING_READ(DPLL(pipe
));
1685 static void vlv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1689 /* Make sure the pipe isn't still relying on us */
1690 assert_pipe_disabled(dev_priv
, pipe
);
1693 * Leave integrated clock source and reference clock enabled for pipe B.
1694 * The latter is needed for VGA hotplug / manual detection.
1697 val
= DPLL_INTEGRATED_CRI_CLK_VLV
| DPLL_REFA_CLK_ENABLE_VLV
;
1698 I915_WRITE(DPLL(pipe
), val
);
1699 POSTING_READ(DPLL(pipe
));
1703 static void chv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1705 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1708 /* Make sure the pipe isn't still relying on us */
1709 assert_pipe_disabled(dev_priv
, pipe
);
1711 /* Set PLL en = 0 */
1712 val
= DPLL_SSC_REF_CLOCK_CHV
;
1714 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1715 I915_WRITE(DPLL(pipe
), val
);
1716 POSTING_READ(DPLL(pipe
));
1718 mutex_lock(&dev_priv
->dpio_lock
);
1720 /* Disable 10bit clock to display controller */
1721 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1722 val
&= ~DPIO_DCLKP_EN
;
1723 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), val
);
1725 /* disable left/right clock distribution */
1726 if (pipe
!= PIPE_B
) {
1727 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
1728 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
1729 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
1731 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
1732 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
1733 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
1736 mutex_unlock(&dev_priv
->dpio_lock
);
1739 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1740 struct intel_digital_port
*dport
)
1745 switch (dport
->port
) {
1747 port_mask
= DPLL_PORTB_READY_MASK
;
1751 port_mask
= DPLL_PORTC_READY_MASK
;
1755 port_mask
= DPLL_PORTD_READY_MASK
;
1756 dpll_reg
= DPIO_PHY_STATUS
;
1762 if (wait_for((I915_READ(dpll_reg
) & port_mask
) == 0, 1000))
1763 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1764 port_name(dport
->port
), I915_READ(dpll_reg
));
1767 static void intel_prepare_shared_dpll(struct intel_crtc
*crtc
)
1769 struct drm_device
*dev
= crtc
->base
.dev
;
1770 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1771 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1773 if (WARN_ON(pll
== NULL
))
1776 WARN_ON(!pll
->refcount
);
1777 if (pll
->active
== 0) {
1778 DRM_DEBUG_DRIVER("setting up %s\n", pll
->name
);
1780 assert_shared_dpll_disabled(dev_priv
, pll
);
1782 pll
->mode_set(dev_priv
, pll
);
1787 * intel_enable_shared_dpll - enable PCH PLL
1788 * @dev_priv: i915 private structure
1789 * @pipe: pipe PLL to enable
1791 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1792 * drives the transcoder clock.
1794 static void intel_enable_shared_dpll(struct intel_crtc
*crtc
)
1796 struct drm_device
*dev
= crtc
->base
.dev
;
1797 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1798 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1800 if (WARN_ON(pll
== NULL
))
1803 if (WARN_ON(pll
->refcount
== 0))
1806 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1807 pll
->name
, pll
->active
, pll
->on
,
1808 crtc
->base
.base
.id
);
1810 if (pll
->active
++) {
1812 assert_shared_dpll_enabled(dev_priv
, pll
);
1817 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
1819 DRM_DEBUG_KMS("enabling %s\n", pll
->name
);
1820 pll
->enable(dev_priv
, pll
);
1824 void intel_disable_shared_dpll(struct intel_crtc
*crtc
)
1826 struct drm_device
*dev
= crtc
->base
.dev
;
1827 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1828 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1830 /* PCH only available on ILK+ */
1831 BUG_ON(INTEL_INFO(dev
)->gen
< 5);
1832 if (WARN_ON(pll
== NULL
))
1835 if (WARN_ON(pll
->refcount
== 0))
1838 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1839 pll
->name
, pll
->active
, pll
->on
,
1840 crtc
->base
.base
.id
);
1842 if (WARN_ON(pll
->active
== 0)) {
1843 assert_shared_dpll_disabled(dev_priv
, pll
);
1847 assert_shared_dpll_enabled(dev_priv
, pll
);
1852 DRM_DEBUG_KMS("disabling %s\n", pll
->name
);
1853 pll
->disable(dev_priv
, pll
);
1856 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
1859 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1862 struct drm_device
*dev
= dev_priv
->dev
;
1863 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1864 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1865 uint32_t reg
, val
, pipeconf_val
;
1867 /* PCH only available on ILK+ */
1868 BUG_ON(INTEL_INFO(dev
)->gen
< 5);
1870 /* Make sure PCH DPLL is enabled */
1871 assert_shared_dpll_enabled(dev_priv
,
1872 intel_crtc_to_shared_dpll(intel_crtc
));
1874 /* FDI must be feeding us bits for PCH ports */
1875 assert_fdi_tx_enabled(dev_priv
, pipe
);
1876 assert_fdi_rx_enabled(dev_priv
, pipe
);
1878 if (HAS_PCH_CPT(dev
)) {
1879 /* Workaround: Set the timing override bit before enabling the
1880 * pch transcoder. */
1881 reg
= TRANS_CHICKEN2(pipe
);
1882 val
= I915_READ(reg
);
1883 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1884 I915_WRITE(reg
, val
);
1887 reg
= PCH_TRANSCONF(pipe
);
1888 val
= I915_READ(reg
);
1889 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1891 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1893 * make the BPC in transcoder be consistent with
1894 * that in pipeconf reg.
1896 val
&= ~PIPECONF_BPC_MASK
;
1897 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1900 val
&= ~TRANS_INTERLACE_MASK
;
1901 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1902 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1903 intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
))
1904 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1906 val
|= TRANS_INTERLACED
;
1908 val
|= TRANS_PROGRESSIVE
;
1910 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1911 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1912 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
1915 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1916 enum transcoder cpu_transcoder
)
1918 u32 val
, pipeconf_val
;
1920 /* PCH only available on ILK+ */
1921 BUG_ON(INTEL_INFO(dev_priv
->dev
)->gen
< 5);
1923 /* FDI must be feeding us bits for PCH ports */
1924 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1925 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
1927 /* Workaround: set timing override bit. */
1928 val
= I915_READ(_TRANSA_CHICKEN2
);
1929 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1930 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1933 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1935 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1936 PIPECONF_INTERLACED_ILK
)
1937 val
|= TRANS_INTERLACED
;
1939 val
|= TRANS_PROGRESSIVE
;
1941 I915_WRITE(LPT_TRANSCONF
, val
);
1942 if (wait_for(I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
, 100))
1943 DRM_ERROR("Failed to enable PCH transcoder\n");
1946 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1949 struct drm_device
*dev
= dev_priv
->dev
;
1952 /* FDI relies on the transcoder */
1953 assert_fdi_tx_disabled(dev_priv
, pipe
);
1954 assert_fdi_rx_disabled(dev_priv
, pipe
);
1956 /* Ports must be off as well */
1957 assert_pch_ports_disabled(dev_priv
, pipe
);
1959 reg
= PCH_TRANSCONF(pipe
);
1960 val
= I915_READ(reg
);
1961 val
&= ~TRANS_ENABLE
;
1962 I915_WRITE(reg
, val
);
1963 /* wait for PCH transcoder off, transcoder state */
1964 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1965 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
1967 if (!HAS_PCH_IBX(dev
)) {
1968 /* Workaround: Clear the timing override chicken bit again. */
1969 reg
= TRANS_CHICKEN2(pipe
);
1970 val
= I915_READ(reg
);
1971 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1972 I915_WRITE(reg
, val
);
1976 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1980 val
= I915_READ(LPT_TRANSCONF
);
1981 val
&= ~TRANS_ENABLE
;
1982 I915_WRITE(LPT_TRANSCONF
, val
);
1983 /* wait for PCH transcoder off, transcoder state */
1984 if (wait_for((I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
) == 0, 50))
1985 DRM_ERROR("Failed to disable PCH transcoder\n");
1987 /* Workaround: clear timing override bit. */
1988 val
= I915_READ(_TRANSA_CHICKEN2
);
1989 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1990 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1994 * intel_enable_pipe - enable a pipe, asserting requirements
1995 * @crtc: crtc responsible for the pipe
1997 * Enable @crtc's pipe, making sure that various hardware specific requirements
1998 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2000 static void intel_enable_pipe(struct intel_crtc
*crtc
)
2002 struct drm_device
*dev
= crtc
->base
.dev
;
2003 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2004 enum pipe pipe
= crtc
->pipe
;
2005 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
2007 enum pipe pch_transcoder
;
2011 assert_planes_disabled(dev_priv
, pipe
);
2012 assert_cursor_disabled(dev_priv
, pipe
);
2013 assert_sprites_disabled(dev_priv
, pipe
);
2015 if (HAS_PCH_LPT(dev_priv
->dev
))
2016 pch_transcoder
= TRANSCODER_A
;
2018 pch_transcoder
= pipe
;
2021 * A pipe without a PLL won't actually be able to drive bits from
2022 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2025 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
2026 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DSI
))
2027 assert_dsi_pll_enabled(dev_priv
);
2029 assert_pll_enabled(dev_priv
, pipe
);
2031 if (crtc
->config
.has_pch_encoder
) {
2032 /* if driving the PCH, we need FDI enabled */
2033 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
2034 assert_fdi_tx_pll_enabled(dev_priv
,
2035 (enum pipe
) cpu_transcoder
);
2037 /* FIXME: assert CPU port conditions for SNB+ */
2040 reg
= PIPECONF(cpu_transcoder
);
2041 val
= I915_READ(reg
);
2042 if (val
& PIPECONF_ENABLE
) {
2043 WARN_ON(!(pipe
== PIPE_A
&&
2044 dev_priv
->quirks
& QUIRK_PIPEA_FORCE
));
2048 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
2053 * intel_disable_pipe - disable a pipe, asserting requirements
2054 * @dev_priv: i915 private structure
2055 * @pipe: pipe to disable
2057 * Disable @pipe, making sure that various hardware specific requirements
2058 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
2060 * @pipe should be %PIPE_A or %PIPE_B.
2062 * Will wait until the pipe has shut down before returning.
2064 static void intel_disable_pipe(struct drm_i915_private
*dev_priv
,
2067 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
2073 * Make sure planes won't keep trying to pump pixels to us,
2074 * or we might hang the display.
2076 assert_planes_disabled(dev_priv
, pipe
);
2077 assert_cursor_disabled(dev_priv
, pipe
);
2078 assert_sprites_disabled(dev_priv
, pipe
);
2080 /* Don't disable pipe A or pipe A PLLs if needed */
2081 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
2084 reg
= PIPECONF(cpu_transcoder
);
2085 val
= I915_READ(reg
);
2086 if ((val
& PIPECONF_ENABLE
) == 0)
2089 I915_WRITE(reg
, val
& ~PIPECONF_ENABLE
);
2090 intel_wait_for_pipe_off(dev_priv
->dev
, pipe
);
2094 * Plane regs are double buffered, going from enabled->disabled needs a
2095 * trigger in order to latch. The display address reg provides this.
2097 void intel_flush_primary_plane(struct drm_i915_private
*dev_priv
,
2100 struct drm_device
*dev
= dev_priv
->dev
;
2101 u32 reg
= INTEL_INFO(dev
)->gen
>= 4 ? DSPSURF(plane
) : DSPADDR(plane
);
2103 I915_WRITE(reg
, I915_READ(reg
));
2108 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2109 * @dev_priv: i915 private structure
2110 * @plane: plane to enable
2111 * @pipe: pipe being fed
2113 * Enable @plane on @pipe, making sure that @pipe is running first.
2115 static void intel_enable_primary_hw_plane(struct drm_i915_private
*dev_priv
,
2116 enum plane plane
, enum pipe pipe
)
2118 struct drm_device
*dev
= dev_priv
->dev
;
2119 struct intel_crtc
*intel_crtc
=
2120 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
2124 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2125 assert_pipe_enabled(dev_priv
, pipe
);
2127 if (intel_crtc
->primary_enabled
)
2130 intel_crtc
->primary_enabled
= true;
2132 reg
= DSPCNTR(plane
);
2133 val
= I915_READ(reg
);
2134 WARN_ON(val
& DISPLAY_PLANE_ENABLE
);
2136 I915_WRITE(reg
, val
| DISPLAY_PLANE_ENABLE
);
2137 intel_flush_primary_plane(dev_priv
, plane
);
2140 * BDW signals flip done immediately if the plane
2141 * is disabled, even if the plane enable is already
2142 * armed to occur at the next vblank :(
2144 if (IS_BROADWELL(dev
))
2145 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2149 * intel_disable_primary_hw_plane - disable the primary hardware plane
2150 * @dev_priv: i915 private structure
2151 * @plane: plane to disable
2152 * @pipe: pipe consuming the data
2154 * Disable @plane; should be an independent operation.
2156 static void intel_disable_primary_hw_plane(struct drm_i915_private
*dev_priv
,
2157 enum plane plane
, enum pipe pipe
)
2159 struct intel_crtc
*intel_crtc
=
2160 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
2164 if (!intel_crtc
->primary_enabled
)
2167 intel_crtc
->primary_enabled
= false;
2169 reg
= DSPCNTR(plane
);
2170 val
= I915_READ(reg
);
2171 WARN_ON((val
& DISPLAY_PLANE_ENABLE
) == 0);
2173 I915_WRITE(reg
, val
& ~DISPLAY_PLANE_ENABLE
);
2174 intel_flush_primary_plane(dev_priv
, plane
);
2177 static bool need_vtd_wa(struct drm_device
*dev
)
2179 #ifdef CONFIG_INTEL_IOMMU
2180 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
2186 static int intel_align_height(struct drm_device
*dev
, int height
, bool tiled
)
2190 tile_height
= tiled
? (IS_GEN2(dev
) ? 16 : 8) : 1;
2191 return ALIGN(height
, tile_height
);
2195 intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
2196 struct drm_i915_gem_object
*obj
,
2197 struct intel_engine_cs
*pipelined
)
2199 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2203 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2205 switch (obj
->tiling_mode
) {
2206 case I915_TILING_NONE
:
2207 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
2208 alignment
= 128 * 1024;
2209 else if (INTEL_INFO(dev
)->gen
>= 4)
2210 alignment
= 4 * 1024;
2212 alignment
= 64 * 1024;
2215 /* pin() will align the object as required by fence */
2219 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2225 /* Note that the w/a also requires 64 PTE of padding following the
2226 * bo. We currently fill all unused PTE with the shadow page and so
2227 * we should always have valid PTE following the scanout preventing
2230 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
2231 alignment
= 256 * 1024;
2233 dev_priv
->mm
.interruptible
= false;
2234 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
);
2236 goto err_interruptible
;
2238 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2239 * fence, whereas 965+ only requires a fence if using
2240 * framebuffer compression. For simplicity, we always install
2241 * a fence as the cost is not that onerous.
2243 ret
= i915_gem_object_get_fence(obj
);
2247 i915_gem_object_pin_fence(obj
);
2249 dev_priv
->mm
.interruptible
= true;
2253 i915_gem_object_unpin_from_display_plane(obj
);
2255 dev_priv
->mm
.interruptible
= true;
2259 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
)
2261 WARN_ON(!mutex_is_locked(&obj
->base
.dev
->struct_mutex
));
2263 i915_gem_object_unpin_fence(obj
);
2264 i915_gem_object_unpin_from_display_plane(obj
);
2267 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2268 * is assumed to be a power-of-two. */
2269 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
2270 unsigned int tiling_mode
,
2274 if (tiling_mode
!= I915_TILING_NONE
) {
2275 unsigned int tile_rows
, tiles
;
2280 tiles
= *x
/ (512/cpp
);
2283 return tile_rows
* pitch
* 8 + tiles
* 4096;
2285 unsigned int offset
;
2287 offset
= *y
* pitch
+ *x
* cpp
;
2289 *x
= (offset
& 4095) / cpp
;
2290 return offset
& -4096;
2294 int intel_format_to_fourcc(int format
)
2297 case DISPPLANE_8BPP
:
2298 return DRM_FORMAT_C8
;
2299 case DISPPLANE_BGRX555
:
2300 return DRM_FORMAT_XRGB1555
;
2301 case DISPPLANE_BGRX565
:
2302 return DRM_FORMAT_RGB565
;
2304 case DISPPLANE_BGRX888
:
2305 return DRM_FORMAT_XRGB8888
;
2306 case DISPPLANE_RGBX888
:
2307 return DRM_FORMAT_XBGR8888
;
2308 case DISPPLANE_BGRX101010
:
2309 return DRM_FORMAT_XRGB2101010
;
2310 case DISPPLANE_RGBX101010
:
2311 return DRM_FORMAT_XBGR2101010
;
2315 static bool intel_alloc_plane_obj(struct intel_crtc
*crtc
,
2316 struct intel_plane_config
*plane_config
)
2318 struct drm_device
*dev
= crtc
->base
.dev
;
2319 struct drm_i915_gem_object
*obj
= NULL
;
2320 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
2321 u32 base
= plane_config
->base
;
2323 if (plane_config
->size
== 0)
2326 obj
= i915_gem_object_create_stolen_for_preallocated(dev
, base
, base
,
2327 plane_config
->size
);
2331 if (plane_config
->tiled
) {
2332 obj
->tiling_mode
= I915_TILING_X
;
2333 obj
->stride
= crtc
->base
.primary
->fb
->pitches
[0];
2336 mode_cmd
.pixel_format
= crtc
->base
.primary
->fb
->pixel_format
;
2337 mode_cmd
.width
= crtc
->base
.primary
->fb
->width
;
2338 mode_cmd
.height
= crtc
->base
.primary
->fb
->height
;
2339 mode_cmd
.pitches
[0] = crtc
->base
.primary
->fb
->pitches
[0];
2341 mutex_lock(&dev
->struct_mutex
);
2343 if (intel_framebuffer_init(dev
, to_intel_framebuffer(crtc
->base
.primary
->fb
),
2345 DRM_DEBUG_KMS("intel fb init failed\n");
2349 obj
->frontbuffer_bits
= INTEL_FRONTBUFFER_PRIMARY(crtc
->pipe
);
2350 mutex_unlock(&dev
->struct_mutex
);
2352 DRM_DEBUG_KMS("plane fb obj %p\n", obj
);
2356 drm_gem_object_unreference(&obj
->base
);
2357 mutex_unlock(&dev
->struct_mutex
);
2361 static void intel_find_plane_obj(struct intel_crtc
*intel_crtc
,
2362 struct intel_plane_config
*plane_config
)
2364 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2366 struct intel_crtc
*i
;
2367 struct drm_i915_gem_object
*obj
;
2369 if (!intel_crtc
->base
.primary
->fb
)
2372 if (intel_alloc_plane_obj(intel_crtc
, plane_config
))
2375 kfree(intel_crtc
->base
.primary
->fb
);
2376 intel_crtc
->base
.primary
->fb
= NULL
;
2379 * Failed to alloc the obj, check to see if we should share
2380 * an fb with another CRTC instead
2382 for_each_crtc(dev
, c
) {
2383 i
= to_intel_crtc(c
);
2385 if (c
== &intel_crtc
->base
)
2391 obj
= intel_fb_obj(c
->primary
->fb
);
2395 if (i915_gem_obj_ggtt_offset(obj
) == plane_config
->base
) {
2396 drm_framebuffer_reference(c
->primary
->fb
);
2397 intel_crtc
->base
.primary
->fb
= c
->primary
->fb
;
2398 obj
->frontbuffer_bits
|= INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
);
2404 static void i9xx_update_primary_plane(struct drm_crtc
*crtc
,
2405 struct drm_framebuffer
*fb
,
2408 struct drm_device
*dev
= crtc
->dev
;
2409 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2410 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2411 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2412 int plane
= intel_crtc
->plane
;
2413 unsigned long linear_offset
;
2417 reg
= DSPCNTR(plane
);
2418 dspcntr
= I915_READ(reg
);
2419 /* Mask out pixel format bits in case we change it */
2420 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2421 switch (fb
->pixel_format
) {
2423 dspcntr
|= DISPPLANE_8BPP
;
2425 case DRM_FORMAT_XRGB1555
:
2426 case DRM_FORMAT_ARGB1555
:
2427 dspcntr
|= DISPPLANE_BGRX555
;
2429 case DRM_FORMAT_RGB565
:
2430 dspcntr
|= DISPPLANE_BGRX565
;
2432 case DRM_FORMAT_XRGB8888
:
2433 case DRM_FORMAT_ARGB8888
:
2434 dspcntr
|= DISPPLANE_BGRX888
;
2436 case DRM_FORMAT_XBGR8888
:
2437 case DRM_FORMAT_ABGR8888
:
2438 dspcntr
|= DISPPLANE_RGBX888
;
2440 case DRM_FORMAT_XRGB2101010
:
2441 case DRM_FORMAT_ARGB2101010
:
2442 dspcntr
|= DISPPLANE_BGRX101010
;
2444 case DRM_FORMAT_XBGR2101010
:
2445 case DRM_FORMAT_ABGR2101010
:
2446 dspcntr
|= DISPPLANE_RGBX101010
;
2452 if (INTEL_INFO(dev
)->gen
>= 4) {
2453 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2454 dspcntr
|= DISPPLANE_TILED
;
2456 dspcntr
&= ~DISPPLANE_TILED
;
2460 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2462 I915_WRITE(reg
, dspcntr
);
2464 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2466 if (INTEL_INFO(dev
)->gen
>= 4) {
2467 intel_crtc
->dspaddr_offset
=
2468 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2469 fb
->bits_per_pixel
/ 8,
2471 linear_offset
-= intel_crtc
->dspaddr_offset
;
2473 intel_crtc
->dspaddr_offset
= linear_offset
;
2476 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2477 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2479 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2480 if (INTEL_INFO(dev
)->gen
>= 4) {
2481 I915_WRITE(DSPSURF(plane
),
2482 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2483 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2484 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2486 I915_WRITE(DSPADDR(plane
), i915_gem_obj_ggtt_offset(obj
) + linear_offset
);
2490 static void ironlake_update_primary_plane(struct drm_crtc
*crtc
,
2491 struct drm_framebuffer
*fb
,
2494 struct drm_device
*dev
= crtc
->dev
;
2495 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2496 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2497 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2498 int plane
= intel_crtc
->plane
;
2499 unsigned long linear_offset
;
2503 reg
= DSPCNTR(plane
);
2504 dspcntr
= I915_READ(reg
);
2505 /* Mask out pixel format bits in case we change it */
2506 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2507 switch (fb
->pixel_format
) {
2509 dspcntr
|= DISPPLANE_8BPP
;
2511 case DRM_FORMAT_RGB565
:
2512 dspcntr
|= DISPPLANE_BGRX565
;
2514 case DRM_FORMAT_XRGB8888
:
2515 case DRM_FORMAT_ARGB8888
:
2516 dspcntr
|= DISPPLANE_BGRX888
;
2518 case DRM_FORMAT_XBGR8888
:
2519 case DRM_FORMAT_ABGR8888
:
2520 dspcntr
|= DISPPLANE_RGBX888
;
2522 case DRM_FORMAT_XRGB2101010
:
2523 case DRM_FORMAT_ARGB2101010
:
2524 dspcntr
|= DISPPLANE_BGRX101010
;
2526 case DRM_FORMAT_XBGR2101010
:
2527 case DRM_FORMAT_ABGR2101010
:
2528 dspcntr
|= DISPPLANE_RGBX101010
;
2534 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2535 dspcntr
|= DISPPLANE_TILED
;
2537 dspcntr
&= ~DISPPLANE_TILED
;
2539 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2540 dspcntr
&= ~DISPPLANE_TRICKLE_FEED_DISABLE
;
2542 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2544 I915_WRITE(reg
, dspcntr
);
2546 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2547 intel_crtc
->dspaddr_offset
=
2548 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2549 fb
->bits_per_pixel
/ 8,
2551 linear_offset
-= intel_crtc
->dspaddr_offset
;
2553 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2554 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2556 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2557 I915_WRITE(DSPSURF(plane
),
2558 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2559 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2560 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2562 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2563 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2568 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2570 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2571 int x
, int y
, enum mode_set_atomic state
)
2573 struct drm_device
*dev
= crtc
->dev
;
2574 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2576 if (dev_priv
->display
.disable_fbc
)
2577 dev_priv
->display
.disable_fbc(dev
);
2578 intel_increase_pllclock(dev
, to_intel_crtc(crtc
)->pipe
);
2580 dev_priv
->display
.update_primary_plane(crtc
, fb
, x
, y
);
2585 void intel_display_handle_reset(struct drm_device
*dev
)
2587 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2588 struct drm_crtc
*crtc
;
2591 * Flips in the rings have been nuked by the reset,
2592 * so complete all pending flips so that user space
2593 * will get its events and not get stuck.
2595 * Also update the base address of all primary
2596 * planes to the the last fb to make sure we're
2597 * showing the correct fb after a reset.
2599 * Need to make two loops over the crtcs so that we
2600 * don't try to grab a crtc mutex before the
2601 * pending_flip_queue really got woken up.
2604 for_each_crtc(dev
, crtc
) {
2605 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2606 enum plane plane
= intel_crtc
->plane
;
2608 intel_prepare_page_flip(dev
, plane
);
2609 intel_finish_page_flip_plane(dev
, plane
);
2612 for_each_crtc(dev
, crtc
) {
2613 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2615 drm_modeset_lock(&crtc
->mutex
, NULL
);
2617 * FIXME: Once we have proper support for primary planes (and
2618 * disabling them without disabling the entire crtc) allow again
2619 * a NULL crtc->primary->fb.
2621 if (intel_crtc
->active
&& crtc
->primary
->fb
)
2622 dev_priv
->display
.update_primary_plane(crtc
,
2626 drm_modeset_unlock(&crtc
->mutex
);
2631 intel_finish_fb(struct drm_framebuffer
*old_fb
)
2633 struct drm_i915_gem_object
*obj
= intel_fb_obj(old_fb
);
2634 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2635 bool was_interruptible
= dev_priv
->mm
.interruptible
;
2638 /* Big Hammer, we also need to ensure that any pending
2639 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2640 * current scanout is retired before unpinning the old
2643 * This should only fail upon a hung GPU, in which case we
2644 * can safely continue.
2646 dev_priv
->mm
.interruptible
= false;
2647 ret
= i915_gem_object_finish_gpu(obj
);
2648 dev_priv
->mm
.interruptible
= was_interruptible
;
2653 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
2655 struct drm_device
*dev
= crtc
->dev
;
2656 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2657 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2658 unsigned long flags
;
2661 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
2662 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
2665 spin_lock_irqsave(&dev
->event_lock
, flags
);
2666 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
2667 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2673 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2674 struct drm_framebuffer
*fb
)
2676 struct drm_device
*dev
= crtc
->dev
;
2677 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2678 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2679 enum pipe pipe
= intel_crtc
->pipe
;
2680 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
2681 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2682 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(old_fb
);
2685 if (intel_crtc_has_pending_flip(crtc
)) {
2686 DRM_ERROR("pipe is still busy with an old pageflip\n");
2692 DRM_ERROR("No FB bound\n");
2696 if (intel_crtc
->plane
> INTEL_INFO(dev
)->num_pipes
) {
2697 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2698 plane_name(intel_crtc
->plane
),
2699 INTEL_INFO(dev
)->num_pipes
);
2703 mutex_lock(&dev
->struct_mutex
);
2704 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, NULL
);
2706 i915_gem_track_fb(old_obj
, obj
,
2707 INTEL_FRONTBUFFER_PRIMARY(pipe
));
2708 mutex_unlock(&dev
->struct_mutex
);
2710 DRM_ERROR("pin & fence failed\n");
2715 * Update pipe size and adjust fitter if needed: the reason for this is
2716 * that in compute_mode_changes we check the native mode (not the pfit
2717 * mode) to see if we can flip rather than do a full mode set. In the
2718 * fastboot case, we'll flip, but if we don't update the pipesrc and
2719 * pfit state, we'll end up with a big fb scanned out into the wrong
2722 * To fix this properly, we need to hoist the checks up into
2723 * compute_mode_changes (or above), check the actual pfit state and
2724 * whether the platform allows pfit disable with pipe active, and only
2725 * then update the pipesrc and pfit state, even on the flip path.
2727 if (i915
.fastboot
) {
2728 const struct drm_display_mode
*adjusted_mode
=
2729 &intel_crtc
->config
.adjusted_mode
;
2731 I915_WRITE(PIPESRC(intel_crtc
->pipe
),
2732 ((adjusted_mode
->crtc_hdisplay
- 1) << 16) |
2733 (adjusted_mode
->crtc_vdisplay
- 1));
2734 if (!intel_crtc
->config
.pch_pfit
.enabled
&&
2735 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) ||
2736 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
2737 I915_WRITE(PF_CTL(intel_crtc
->pipe
), 0);
2738 I915_WRITE(PF_WIN_POS(intel_crtc
->pipe
), 0);
2739 I915_WRITE(PF_WIN_SZ(intel_crtc
->pipe
), 0);
2741 intel_crtc
->config
.pipe_src_w
= adjusted_mode
->crtc_hdisplay
;
2742 intel_crtc
->config
.pipe_src_h
= adjusted_mode
->crtc_vdisplay
;
2745 dev_priv
->display
.update_primary_plane(crtc
, fb
, x
, y
);
2747 if (intel_crtc
->active
)
2748 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
2750 crtc
->primary
->fb
= fb
;
2755 if (intel_crtc
->active
&& old_fb
!= fb
)
2756 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2757 mutex_lock(&dev
->struct_mutex
);
2758 intel_unpin_fb_obj(old_obj
);
2759 mutex_unlock(&dev
->struct_mutex
);
2762 mutex_lock(&dev
->struct_mutex
);
2763 intel_update_fbc(dev
);
2764 mutex_unlock(&dev
->struct_mutex
);
2769 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
2771 struct drm_device
*dev
= crtc
->dev
;
2772 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2773 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2774 int pipe
= intel_crtc
->pipe
;
2777 /* enable normal train */
2778 reg
= FDI_TX_CTL(pipe
);
2779 temp
= I915_READ(reg
);
2780 if (IS_IVYBRIDGE(dev
)) {
2781 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2782 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2784 temp
&= ~FDI_LINK_TRAIN_NONE
;
2785 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2787 I915_WRITE(reg
, temp
);
2789 reg
= FDI_RX_CTL(pipe
);
2790 temp
= I915_READ(reg
);
2791 if (HAS_PCH_CPT(dev
)) {
2792 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2793 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2795 temp
&= ~FDI_LINK_TRAIN_NONE
;
2796 temp
|= FDI_LINK_TRAIN_NONE
;
2798 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2800 /* wait one idle pattern time */
2804 /* IVB wants error correction enabled */
2805 if (IS_IVYBRIDGE(dev
))
2806 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
2807 FDI_FE_ERRC_ENABLE
);
2810 static bool pipe_has_enabled_pch(struct intel_crtc
*crtc
)
2812 return crtc
->base
.enabled
&& crtc
->active
&&
2813 crtc
->config
.has_pch_encoder
;
2816 static void ivb_modeset_global_resources(struct drm_device
*dev
)
2818 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2819 struct intel_crtc
*pipe_B_crtc
=
2820 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
2821 struct intel_crtc
*pipe_C_crtc
=
2822 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]);
2826 * When everything is off disable fdi C so that we could enable fdi B
2827 * with all lanes. Note that we don't care about enabled pipes without
2828 * an enabled pch encoder.
2830 if (!pipe_has_enabled_pch(pipe_B_crtc
) &&
2831 !pipe_has_enabled_pch(pipe_C_crtc
)) {
2832 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
2833 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
2835 temp
= I915_READ(SOUTH_CHICKEN1
);
2836 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
2837 DRM_DEBUG_KMS("disabling fdi C rx\n");
2838 I915_WRITE(SOUTH_CHICKEN1
, temp
);
2842 /* The FDI link training functions for ILK/Ibexpeak. */
2843 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
2845 struct drm_device
*dev
= crtc
->dev
;
2846 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2847 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2848 int pipe
= intel_crtc
->pipe
;
2849 u32 reg
, temp
, tries
;
2851 /* FDI needs bits from pipe first */
2852 assert_pipe_enabled(dev_priv
, pipe
);
2854 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2856 reg
= FDI_RX_IMR(pipe
);
2857 temp
= I915_READ(reg
);
2858 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2859 temp
&= ~FDI_RX_BIT_LOCK
;
2860 I915_WRITE(reg
, temp
);
2864 /* enable CPU FDI TX and PCH FDI RX */
2865 reg
= FDI_TX_CTL(pipe
);
2866 temp
= I915_READ(reg
);
2867 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2868 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2869 temp
&= ~FDI_LINK_TRAIN_NONE
;
2870 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2871 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2873 reg
= FDI_RX_CTL(pipe
);
2874 temp
= I915_READ(reg
);
2875 temp
&= ~FDI_LINK_TRAIN_NONE
;
2876 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2877 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2882 /* Ironlake workaround, enable clock pointer after FDI enable*/
2883 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2884 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
2885 FDI_RX_PHASE_SYNC_POINTER_EN
);
2887 reg
= FDI_RX_IIR(pipe
);
2888 for (tries
= 0; tries
< 5; tries
++) {
2889 temp
= I915_READ(reg
);
2890 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2892 if ((temp
& FDI_RX_BIT_LOCK
)) {
2893 DRM_DEBUG_KMS("FDI train 1 done.\n");
2894 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2899 DRM_ERROR("FDI train 1 fail!\n");
2902 reg
= FDI_TX_CTL(pipe
);
2903 temp
= I915_READ(reg
);
2904 temp
&= ~FDI_LINK_TRAIN_NONE
;
2905 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2906 I915_WRITE(reg
, temp
);
2908 reg
= FDI_RX_CTL(pipe
);
2909 temp
= I915_READ(reg
);
2910 temp
&= ~FDI_LINK_TRAIN_NONE
;
2911 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2912 I915_WRITE(reg
, temp
);
2917 reg
= FDI_RX_IIR(pipe
);
2918 for (tries
= 0; tries
< 5; tries
++) {
2919 temp
= I915_READ(reg
);
2920 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2922 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2923 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2924 DRM_DEBUG_KMS("FDI train 2 done.\n");
2929 DRM_ERROR("FDI train 2 fail!\n");
2931 DRM_DEBUG_KMS("FDI train done\n");
2935 static const int snb_b_fdi_train_param
[] = {
2936 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
2937 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
2938 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
2939 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
2942 /* The FDI link training functions for SNB/Cougarpoint. */
2943 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
2945 struct drm_device
*dev
= crtc
->dev
;
2946 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2947 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2948 int pipe
= intel_crtc
->pipe
;
2949 u32 reg
, temp
, i
, retry
;
2951 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2953 reg
= FDI_RX_IMR(pipe
);
2954 temp
= I915_READ(reg
);
2955 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2956 temp
&= ~FDI_RX_BIT_LOCK
;
2957 I915_WRITE(reg
, temp
);
2962 /* enable CPU FDI TX and PCH FDI RX */
2963 reg
= FDI_TX_CTL(pipe
);
2964 temp
= I915_READ(reg
);
2965 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2966 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2967 temp
&= ~FDI_LINK_TRAIN_NONE
;
2968 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2969 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2971 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2972 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2974 I915_WRITE(FDI_RX_MISC(pipe
),
2975 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2977 reg
= FDI_RX_CTL(pipe
);
2978 temp
= I915_READ(reg
);
2979 if (HAS_PCH_CPT(dev
)) {
2980 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2981 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2983 temp
&= ~FDI_LINK_TRAIN_NONE
;
2984 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2986 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2991 for (i
= 0; i
< 4; i
++) {
2992 reg
= FDI_TX_CTL(pipe
);
2993 temp
= I915_READ(reg
);
2994 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2995 temp
|= snb_b_fdi_train_param
[i
];
2996 I915_WRITE(reg
, temp
);
3001 for (retry
= 0; retry
< 5; retry
++) {
3002 reg
= FDI_RX_IIR(pipe
);
3003 temp
= I915_READ(reg
);
3004 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3005 if (temp
& FDI_RX_BIT_LOCK
) {
3006 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3007 DRM_DEBUG_KMS("FDI train 1 done.\n");
3016 DRM_ERROR("FDI train 1 fail!\n");
3019 reg
= FDI_TX_CTL(pipe
);
3020 temp
= I915_READ(reg
);
3021 temp
&= ~FDI_LINK_TRAIN_NONE
;
3022 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3024 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3026 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3028 I915_WRITE(reg
, temp
);
3030 reg
= FDI_RX_CTL(pipe
);
3031 temp
= I915_READ(reg
);
3032 if (HAS_PCH_CPT(dev
)) {
3033 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3034 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3036 temp
&= ~FDI_LINK_TRAIN_NONE
;
3037 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3039 I915_WRITE(reg
, temp
);
3044 for (i
= 0; i
< 4; i
++) {
3045 reg
= FDI_TX_CTL(pipe
);
3046 temp
= I915_READ(reg
);
3047 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3048 temp
|= snb_b_fdi_train_param
[i
];
3049 I915_WRITE(reg
, temp
);
3054 for (retry
= 0; retry
< 5; retry
++) {
3055 reg
= FDI_RX_IIR(pipe
);
3056 temp
= I915_READ(reg
);
3057 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3058 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3059 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3060 DRM_DEBUG_KMS("FDI train 2 done.\n");
3069 DRM_ERROR("FDI train 2 fail!\n");
3071 DRM_DEBUG_KMS("FDI train done.\n");
3074 /* Manual link training for Ivy Bridge A0 parts */
3075 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
3077 struct drm_device
*dev
= crtc
->dev
;
3078 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3079 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3080 int pipe
= intel_crtc
->pipe
;
3081 u32 reg
, temp
, i
, j
;
3083 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3085 reg
= FDI_RX_IMR(pipe
);
3086 temp
= I915_READ(reg
);
3087 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3088 temp
&= ~FDI_RX_BIT_LOCK
;
3089 I915_WRITE(reg
, temp
);
3094 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3095 I915_READ(FDI_RX_IIR(pipe
)));
3097 /* Try each vswing and preemphasis setting twice before moving on */
3098 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
3099 /* disable first in case we need to retry */
3100 reg
= FDI_TX_CTL(pipe
);
3101 temp
= I915_READ(reg
);
3102 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
3103 temp
&= ~FDI_TX_ENABLE
;
3104 I915_WRITE(reg
, temp
);
3106 reg
= FDI_RX_CTL(pipe
);
3107 temp
= I915_READ(reg
);
3108 temp
&= ~FDI_LINK_TRAIN_AUTO
;
3109 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3110 temp
&= ~FDI_RX_ENABLE
;
3111 I915_WRITE(reg
, temp
);
3113 /* enable CPU FDI TX and PCH FDI RX */
3114 reg
= FDI_TX_CTL(pipe
);
3115 temp
= I915_READ(reg
);
3116 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3117 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
3118 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
3119 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3120 temp
|= snb_b_fdi_train_param
[j
/2];
3121 temp
|= FDI_COMPOSITE_SYNC
;
3122 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3124 I915_WRITE(FDI_RX_MISC(pipe
),
3125 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3127 reg
= FDI_RX_CTL(pipe
);
3128 temp
= I915_READ(reg
);
3129 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3130 temp
|= FDI_COMPOSITE_SYNC
;
3131 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3134 udelay(1); /* should be 0.5us */
3136 for (i
= 0; i
< 4; i
++) {
3137 reg
= FDI_RX_IIR(pipe
);
3138 temp
= I915_READ(reg
);
3139 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3141 if (temp
& FDI_RX_BIT_LOCK
||
3142 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
3143 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3144 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3148 udelay(1); /* should be 0.5us */
3151 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
3156 reg
= FDI_TX_CTL(pipe
);
3157 temp
= I915_READ(reg
);
3158 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3159 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
3160 I915_WRITE(reg
, temp
);
3162 reg
= FDI_RX_CTL(pipe
);
3163 temp
= I915_READ(reg
);
3164 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3165 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3166 I915_WRITE(reg
, temp
);
3169 udelay(2); /* should be 1.5us */
3171 for (i
= 0; i
< 4; i
++) {
3172 reg
= FDI_RX_IIR(pipe
);
3173 temp
= I915_READ(reg
);
3174 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3176 if (temp
& FDI_RX_SYMBOL_LOCK
||
3177 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
3178 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3179 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3183 udelay(2); /* should be 1.5us */
3186 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
3190 DRM_DEBUG_KMS("FDI train done.\n");
3193 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
3195 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3196 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3197 int pipe
= intel_crtc
->pipe
;
3201 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3202 reg
= FDI_RX_CTL(pipe
);
3203 temp
= I915_READ(reg
);
3204 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
3205 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
3206 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3207 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
3212 /* Switch from Rawclk to PCDclk */
3213 temp
= I915_READ(reg
);
3214 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
3219 /* Enable CPU FDI TX PLL, always on for Ironlake */
3220 reg
= FDI_TX_CTL(pipe
);
3221 temp
= I915_READ(reg
);
3222 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
3223 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
3230 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
3232 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3233 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3234 int pipe
= intel_crtc
->pipe
;
3237 /* Switch from PCDclk to Rawclk */
3238 reg
= FDI_RX_CTL(pipe
);
3239 temp
= I915_READ(reg
);
3240 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
3242 /* Disable CPU FDI TX PLL */
3243 reg
= FDI_TX_CTL(pipe
);
3244 temp
= I915_READ(reg
);
3245 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
3250 reg
= FDI_RX_CTL(pipe
);
3251 temp
= I915_READ(reg
);
3252 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
3254 /* Wait for the clocks to turn off. */
3259 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
3261 struct drm_device
*dev
= crtc
->dev
;
3262 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3263 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3264 int pipe
= intel_crtc
->pipe
;
3267 /* disable CPU FDI tx and PCH FDI rx */
3268 reg
= FDI_TX_CTL(pipe
);
3269 temp
= I915_READ(reg
);
3270 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
3273 reg
= FDI_RX_CTL(pipe
);
3274 temp
= I915_READ(reg
);
3275 temp
&= ~(0x7 << 16);
3276 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3277 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
3282 /* Ironlake workaround, disable clock pointer after downing FDI */
3283 if (HAS_PCH_IBX(dev
))
3284 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3286 /* still set train pattern 1 */
3287 reg
= FDI_TX_CTL(pipe
);
3288 temp
= I915_READ(reg
);
3289 temp
&= ~FDI_LINK_TRAIN_NONE
;
3290 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3291 I915_WRITE(reg
, temp
);
3293 reg
= FDI_RX_CTL(pipe
);
3294 temp
= I915_READ(reg
);
3295 if (HAS_PCH_CPT(dev
)) {
3296 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3297 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3299 temp
&= ~FDI_LINK_TRAIN_NONE
;
3300 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3302 /* BPC in FDI rx is consistent with that in PIPECONF */
3303 temp
&= ~(0x07 << 16);
3304 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3305 I915_WRITE(reg
, temp
);
3311 bool intel_has_pending_fb_unpin(struct drm_device
*dev
)
3313 struct intel_crtc
*crtc
;
3315 /* Note that we don't need to be called with mode_config.lock here
3316 * as our list of CRTC objects is static for the lifetime of the
3317 * device and so cannot disappear as we iterate. Similarly, we can
3318 * happily treat the predicates as racy, atomic checks as userspace
3319 * cannot claim and pin a new fb without at least acquring the
3320 * struct_mutex and so serialising with us.
3322 for_each_intel_crtc(dev
, crtc
) {
3323 if (atomic_read(&crtc
->unpin_work_count
) == 0)
3326 if (crtc
->unpin_work
)
3327 intel_wait_for_vblank(dev
, crtc
->pipe
);
3335 void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
3337 struct drm_device
*dev
= crtc
->dev
;
3338 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3340 if (crtc
->primary
->fb
== NULL
)
3343 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
3345 WARN_ON(wait_event_timeout(dev_priv
->pending_flip_queue
,
3346 !intel_crtc_has_pending_flip(crtc
),
3349 mutex_lock(&dev
->struct_mutex
);
3350 intel_finish_fb(crtc
->primary
->fb
);
3351 mutex_unlock(&dev
->struct_mutex
);
3354 /* Program iCLKIP clock to the desired frequency */
3355 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
3357 struct drm_device
*dev
= crtc
->dev
;
3358 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3359 int clock
= to_intel_crtc(crtc
)->config
.adjusted_mode
.crtc_clock
;
3360 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
3363 mutex_lock(&dev_priv
->dpio_lock
);
3365 /* It is necessary to ungate the pixclk gate prior to programming
3366 * the divisors, and gate it back when it is done.
3368 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
3370 /* Disable SSCCTL */
3371 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
3372 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
3376 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3377 if (clock
== 20000) {
3382 /* The iCLK virtual clock root frequency is in MHz,
3383 * but the adjusted_mode->crtc_clock in in KHz. To get the
3384 * divisors, it is necessary to divide one by another, so we
3385 * convert the virtual clock precision to KHz here for higher
3388 u32 iclk_virtual_root_freq
= 172800 * 1000;
3389 u32 iclk_pi_range
= 64;
3390 u32 desired_divisor
, msb_divisor_value
, pi_value
;
3392 desired_divisor
= (iclk_virtual_root_freq
/ clock
);
3393 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
3394 pi_value
= desired_divisor
% iclk_pi_range
;
3397 divsel
= msb_divisor_value
- 2;
3398 phaseinc
= pi_value
;
3401 /* This should not happen with any sane values */
3402 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
3403 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
3404 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
3405 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
3407 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3414 /* Program SSCDIVINTPHASE6 */
3415 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
3416 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
3417 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
3418 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
3419 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
3420 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
3421 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
3422 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
3424 /* Program SSCAUXDIV */
3425 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
3426 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3427 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
3428 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
3430 /* Enable modulator and associated divider */
3431 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
3432 temp
&= ~SBI_SSCCTL_DISABLE
;
3433 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
3435 /* Wait for initialization time */
3438 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
3440 mutex_unlock(&dev_priv
->dpio_lock
);
3443 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
3444 enum pipe pch_transcoder
)
3446 struct drm_device
*dev
= crtc
->base
.dev
;
3447 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3448 enum transcoder cpu_transcoder
= crtc
->config
.cpu_transcoder
;
3450 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
3451 I915_READ(HTOTAL(cpu_transcoder
)));
3452 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
3453 I915_READ(HBLANK(cpu_transcoder
)));
3454 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
3455 I915_READ(HSYNC(cpu_transcoder
)));
3457 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
3458 I915_READ(VTOTAL(cpu_transcoder
)));
3459 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
3460 I915_READ(VBLANK(cpu_transcoder
)));
3461 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
3462 I915_READ(VSYNC(cpu_transcoder
)));
3463 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
3464 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
3467 static void cpt_enable_fdi_bc_bifurcation(struct drm_device
*dev
)
3469 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3472 temp
= I915_READ(SOUTH_CHICKEN1
);
3473 if (temp
& FDI_BC_BIFURCATION_SELECT
)
3476 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
3477 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
3479 temp
|= FDI_BC_BIFURCATION_SELECT
;
3480 DRM_DEBUG_KMS("enabling fdi C rx\n");
3481 I915_WRITE(SOUTH_CHICKEN1
, temp
);
3482 POSTING_READ(SOUTH_CHICKEN1
);
3485 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
3487 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3488 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3490 switch (intel_crtc
->pipe
) {
3494 if (intel_crtc
->config
.fdi_lanes
> 2)
3495 WARN_ON(I915_READ(SOUTH_CHICKEN1
) & FDI_BC_BIFURCATION_SELECT
);
3497 cpt_enable_fdi_bc_bifurcation(dev
);
3501 cpt_enable_fdi_bc_bifurcation(dev
);
3510 * Enable PCH resources required for PCH ports:
3512 * - FDI training & RX/TX
3513 * - update transcoder timings
3514 * - DP transcoding bits
3517 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
3519 struct drm_device
*dev
= crtc
->dev
;
3520 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3521 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3522 int pipe
= intel_crtc
->pipe
;
3525 assert_pch_transcoder_disabled(dev_priv
, pipe
);
3527 if (IS_IVYBRIDGE(dev
))
3528 ivybridge_update_fdi_bc_bifurcation(intel_crtc
);
3530 /* Write the TU size bits before fdi link training, so that error
3531 * detection works. */
3532 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
3533 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
3535 /* For PCH output, training FDI link */
3536 dev_priv
->display
.fdi_link_train(crtc
);
3538 /* We need to program the right clock selection before writing the pixel
3539 * mutliplier into the DPLL. */
3540 if (HAS_PCH_CPT(dev
)) {
3543 temp
= I915_READ(PCH_DPLL_SEL
);
3544 temp
|= TRANS_DPLL_ENABLE(pipe
);
3545 sel
= TRANS_DPLLB_SEL(pipe
);
3546 if (intel_crtc
->config
.shared_dpll
== DPLL_ID_PCH_PLL_B
)
3550 I915_WRITE(PCH_DPLL_SEL
, temp
);
3553 /* XXX: pch pll's can be enabled any time before we enable the PCH
3554 * transcoder, and we actually should do this to not upset any PCH
3555 * transcoder that already use the clock when we share it.
3557 * Note that enable_shared_dpll tries to do the right thing, but
3558 * get_shared_dpll unconditionally resets the pll - we need that to have
3559 * the right LVDS enable sequence. */
3560 intel_enable_shared_dpll(intel_crtc
);
3562 /* set transcoder timing, panel must allow it */
3563 assert_panel_unlocked(dev_priv
, pipe
);
3564 ironlake_pch_transcoder_set_timings(intel_crtc
, pipe
);
3566 intel_fdi_normal_train(crtc
);
3568 /* For PCH DP, enable TRANS_DP_CTL */
3569 if (HAS_PCH_CPT(dev
) &&
3570 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
3571 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3572 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
3573 reg
= TRANS_DP_CTL(pipe
);
3574 temp
= I915_READ(reg
);
3575 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
3576 TRANS_DP_SYNC_MASK
|
3578 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
3579 TRANS_DP_ENH_FRAMING
);
3580 temp
|= bpc
<< 9; /* same format but at 11:9 */
3582 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
3583 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
3584 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
3585 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
3587 switch (intel_trans_dp_port_sel(crtc
)) {
3589 temp
|= TRANS_DP_PORT_SEL_B
;
3592 temp
|= TRANS_DP_PORT_SEL_C
;
3595 temp
|= TRANS_DP_PORT_SEL_D
;
3601 I915_WRITE(reg
, temp
);
3604 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
3607 static void lpt_pch_enable(struct drm_crtc
*crtc
)
3609 struct drm_device
*dev
= crtc
->dev
;
3610 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3611 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3612 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
3614 assert_pch_transcoder_disabled(dev_priv
, TRANSCODER_A
);
3616 lpt_program_iclkip(crtc
);
3618 /* Set transcoder timing. */
3619 ironlake_pch_transcoder_set_timings(intel_crtc
, PIPE_A
);
3621 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
3624 void intel_put_shared_dpll(struct intel_crtc
*crtc
)
3626 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3631 if (pll
->refcount
== 0) {
3632 WARN(1, "bad %s refcount\n", pll
->name
);
3636 if (--pll
->refcount
== 0) {
3638 WARN_ON(pll
->active
);
3641 crtc
->config
.shared_dpll
= DPLL_ID_PRIVATE
;
3644 struct intel_shared_dpll
*intel_get_shared_dpll(struct intel_crtc
*crtc
)
3646 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
3647 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3648 enum intel_dpll_id i
;
3651 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3652 crtc
->base
.base
.id
, pll
->name
);
3653 intel_put_shared_dpll(crtc
);
3656 if (HAS_PCH_IBX(dev_priv
->dev
)) {
3657 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3658 i
= (enum intel_dpll_id
) crtc
->pipe
;
3659 pll
= &dev_priv
->shared_dplls
[i
];
3661 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3662 crtc
->base
.base
.id
, pll
->name
);
3664 WARN_ON(pll
->refcount
);
3669 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3670 pll
= &dev_priv
->shared_dplls
[i
];
3672 /* Only want to check enabled timings first */
3673 if (pll
->refcount
== 0)
3676 if (memcmp(&crtc
->config
.dpll_hw_state
, &pll
->hw_state
,
3677 sizeof(pll
->hw_state
)) == 0) {
3678 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3680 pll
->name
, pll
->refcount
, pll
->active
);
3686 /* Ok no matching timings, maybe there's a free one? */
3687 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3688 pll
= &dev_priv
->shared_dplls
[i
];
3689 if (pll
->refcount
== 0) {
3690 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3691 crtc
->base
.base
.id
, pll
->name
);
3699 if (pll
->refcount
== 0)
3700 pll
->hw_state
= crtc
->config
.dpll_hw_state
;
3702 crtc
->config
.shared_dpll
= i
;
3703 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll
->name
,
3704 pipe_name(crtc
->pipe
));
3711 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
3713 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3714 int dslreg
= PIPEDSL(pipe
);
3717 temp
= I915_READ(dslreg
);
3719 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
3720 if (wait_for(I915_READ(dslreg
) != temp
, 5))
3721 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
3725 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
3727 struct drm_device
*dev
= crtc
->base
.dev
;
3728 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3729 int pipe
= crtc
->pipe
;
3731 if (crtc
->config
.pch_pfit
.enabled
) {
3732 /* Force use of hard-coded filter coefficients
3733 * as some pre-programmed values are broken,
3736 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
3737 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
3738 PF_PIPE_SEL_IVB(pipe
));
3740 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
3741 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
.pch_pfit
.pos
);
3742 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
.pch_pfit
.size
);
3746 static void intel_enable_planes(struct drm_crtc
*crtc
)
3748 struct drm_device
*dev
= crtc
->dev
;
3749 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
3750 struct drm_plane
*plane
;
3751 struct intel_plane
*intel_plane
;
3753 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
3754 intel_plane
= to_intel_plane(plane
);
3755 if (intel_plane
->pipe
== pipe
)
3756 intel_plane_restore(&intel_plane
->base
);
3760 static void intel_disable_planes(struct drm_crtc
*crtc
)
3762 struct drm_device
*dev
= crtc
->dev
;
3763 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
3764 struct drm_plane
*plane
;
3765 struct intel_plane
*intel_plane
;
3767 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
3768 intel_plane
= to_intel_plane(plane
);
3769 if (intel_plane
->pipe
== pipe
)
3770 intel_plane_disable(&intel_plane
->base
);
3774 void hsw_enable_ips(struct intel_crtc
*crtc
)
3776 struct drm_device
*dev
= crtc
->base
.dev
;
3777 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3779 if (!crtc
->config
.ips_enabled
)
3782 /* We can only enable IPS after we enable a plane and wait for a vblank */
3783 intel_wait_for_vblank(dev
, crtc
->pipe
);
3785 assert_plane_enabled(dev_priv
, crtc
->plane
);
3786 if (IS_BROADWELL(dev
)) {
3787 mutex_lock(&dev_priv
->rps
.hw_lock
);
3788 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0xc0000000));
3789 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3790 /* Quoting Art Runyan: "its not safe to expect any particular
3791 * value in IPS_CTL bit 31 after enabling IPS through the
3792 * mailbox." Moreover, the mailbox may return a bogus state,
3793 * so we need to just enable it and continue on.
3796 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
3797 /* The bit only becomes 1 in the next vblank, so this wait here
3798 * is essentially intel_wait_for_vblank. If we don't have this
3799 * and don't wait for vblanks until the end of crtc_enable, then
3800 * the HW state readout code will complain that the expected
3801 * IPS_CTL value is not the one we read. */
3802 if (wait_for(I915_READ_NOTRACE(IPS_CTL
) & IPS_ENABLE
, 50))
3803 DRM_ERROR("Timed out waiting for IPS enable\n");
3807 void hsw_disable_ips(struct intel_crtc
*crtc
)
3809 struct drm_device
*dev
= crtc
->base
.dev
;
3810 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3812 if (!crtc
->config
.ips_enabled
)
3815 assert_plane_enabled(dev_priv
, crtc
->plane
);
3816 if (IS_BROADWELL(dev
)) {
3817 mutex_lock(&dev_priv
->rps
.hw_lock
);
3818 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0));
3819 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3820 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3821 if (wait_for((I915_READ(IPS_CTL
) & IPS_ENABLE
) == 0, 42))
3822 DRM_ERROR("Timed out waiting for IPS disable\n");
3824 I915_WRITE(IPS_CTL
, 0);
3825 POSTING_READ(IPS_CTL
);
3828 /* We need to wait for a vblank before we can disable the plane. */
3829 intel_wait_for_vblank(dev
, crtc
->pipe
);
3832 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3833 static void intel_crtc_load_lut(struct drm_crtc
*crtc
)
3835 struct drm_device
*dev
= crtc
->dev
;
3836 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3837 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3838 enum pipe pipe
= intel_crtc
->pipe
;
3839 int palreg
= PALETTE(pipe
);
3841 bool reenable_ips
= false;
3843 /* The clocks have to be on to load the palette. */
3844 if (!crtc
->enabled
|| !intel_crtc
->active
)
3847 if (!HAS_PCH_SPLIT(dev_priv
->dev
)) {
3848 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
))
3849 assert_dsi_pll_enabled(dev_priv
);
3851 assert_pll_enabled(dev_priv
, pipe
);
3854 /* use legacy palette for Ironlake */
3855 if (HAS_PCH_SPLIT(dev
))
3856 palreg
= LGC_PALETTE(pipe
);
3858 /* Workaround : Do not read or write the pipe palette/gamma data while
3859 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3861 if (IS_HASWELL(dev
) && intel_crtc
->config
.ips_enabled
&&
3862 ((I915_READ(GAMMA_MODE(pipe
)) & GAMMA_MODE_MODE_MASK
) ==
3863 GAMMA_MODE_MODE_SPLIT
)) {
3864 hsw_disable_ips(intel_crtc
);
3865 reenable_ips
= true;
3868 for (i
= 0; i
< 256; i
++) {
3869 I915_WRITE(palreg
+ 4 * i
,
3870 (intel_crtc
->lut_r
[i
] << 16) |
3871 (intel_crtc
->lut_g
[i
] << 8) |
3872 intel_crtc
->lut_b
[i
]);
3876 hsw_enable_ips(intel_crtc
);
3879 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
3881 if (!enable
&& intel_crtc
->overlay
) {
3882 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3883 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3885 mutex_lock(&dev
->struct_mutex
);
3886 dev_priv
->mm
.interruptible
= false;
3887 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
3888 dev_priv
->mm
.interruptible
= true;
3889 mutex_unlock(&dev
->struct_mutex
);
3892 /* Let userspace switch the overlay on again. In most cases userspace
3893 * has to recompute where to put it anyway.
3897 static void intel_crtc_enable_planes(struct drm_crtc
*crtc
)
3899 struct drm_device
*dev
= crtc
->dev
;
3900 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3901 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3902 int pipe
= intel_crtc
->pipe
;
3903 int plane
= intel_crtc
->plane
;
3905 drm_vblank_on(dev
, pipe
);
3907 intel_enable_primary_hw_plane(dev_priv
, plane
, pipe
);
3908 intel_enable_planes(crtc
);
3909 intel_crtc_update_cursor(crtc
, true);
3910 intel_crtc_dpms_overlay(intel_crtc
, true);
3912 hsw_enable_ips(intel_crtc
);
3914 mutex_lock(&dev
->struct_mutex
);
3915 intel_update_fbc(dev
);
3916 mutex_unlock(&dev
->struct_mutex
);
3919 * FIXME: Once we grow proper nuclear flip support out of this we need
3920 * to compute the mask of flip planes precisely. For the time being
3921 * consider this a flip from a NULL plane.
3923 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
3926 static void intel_crtc_disable_planes(struct drm_crtc
*crtc
)
3928 struct drm_device
*dev
= crtc
->dev
;
3929 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3930 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3931 int pipe
= intel_crtc
->pipe
;
3932 int plane
= intel_crtc
->plane
;
3934 intel_crtc_wait_for_pending_flips(crtc
);
3936 if (dev_priv
->fbc
.plane
== plane
)
3937 intel_disable_fbc(dev
);
3939 hsw_disable_ips(intel_crtc
);
3941 intel_crtc_dpms_overlay(intel_crtc
, false);
3942 intel_crtc_update_cursor(crtc
, false);
3943 intel_disable_planes(crtc
);
3944 intel_disable_primary_hw_plane(dev_priv
, plane
, pipe
);
3947 * FIXME: Once we grow proper nuclear flip support out of this we need
3948 * to compute the mask of flip planes precisely. For the time being
3949 * consider this a flip to a NULL plane.
3951 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
3953 drm_vblank_off(dev
, pipe
);
3956 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
3958 struct drm_device
*dev
= crtc
->dev
;
3959 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3960 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3961 struct intel_encoder
*encoder
;
3962 int pipe
= intel_crtc
->pipe
;
3963 enum plane plane
= intel_crtc
->plane
;
3965 WARN_ON(!crtc
->enabled
);
3967 if (intel_crtc
->active
)
3970 if (intel_crtc
->config
.has_pch_encoder
)
3971 intel_prepare_shared_dpll(intel_crtc
);
3973 if (intel_crtc
->config
.has_dp_encoder
)
3974 intel_dp_set_m_n(intel_crtc
);
3976 intel_set_pipe_timings(intel_crtc
);
3978 if (intel_crtc
->config
.has_pch_encoder
) {
3979 intel_cpu_transcoder_set_m_n(intel_crtc
,
3980 &intel_crtc
->config
.fdi_m_n
);
3983 ironlake_set_pipeconf(crtc
);
3985 /* Set up the display plane register */
3986 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
);
3987 POSTING_READ(DSPCNTR(plane
));
3989 dev_priv
->display
.update_primary_plane(crtc
, crtc
->primary
->fb
,
3992 intel_crtc
->active
= true;
3994 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
3995 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
3997 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3998 if (encoder
->pre_enable
)
3999 encoder
->pre_enable(encoder
);
4001 if (intel_crtc
->config
.has_pch_encoder
) {
4002 /* Note: FDI PLL enabling _must_ be done before we enable the
4003 * cpu pipes, hence this is separate from all the other fdi/pch
4005 ironlake_fdi_pll_enable(intel_crtc
);
4007 assert_fdi_tx_disabled(dev_priv
, pipe
);
4008 assert_fdi_rx_disabled(dev_priv
, pipe
);
4011 ironlake_pfit_enable(intel_crtc
);
4014 * On ILK+ LUT must be loaded before the pipe is running but with
4017 intel_crtc_load_lut(crtc
);
4019 intel_update_watermarks(crtc
);
4020 intel_enable_pipe(intel_crtc
);
4022 if (intel_crtc
->config
.has_pch_encoder
)
4023 ironlake_pch_enable(crtc
);
4025 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4026 encoder
->enable(encoder
);
4028 if (HAS_PCH_CPT(dev
))
4029 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
4031 intel_crtc_enable_planes(crtc
);
4034 /* IPS only exists on ULT machines and is tied to pipe A. */
4035 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
4037 return HAS_IPS(crtc
->base
.dev
) && crtc
->pipe
== PIPE_A
;
4041 * This implements the workaround described in the "notes" section of the mode
4042 * set sequence documentation. When going from no pipes or single pipe to
4043 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4044 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4046 static void haswell_mode_set_planes_workaround(struct intel_crtc
*crtc
)
4048 struct drm_device
*dev
= crtc
->base
.dev
;
4049 struct intel_crtc
*crtc_it
, *other_active_crtc
= NULL
;
4051 /* We want to get the other_active_crtc only if there's only 1 other
4053 for_each_intel_crtc(dev
, crtc_it
) {
4054 if (!crtc_it
->active
|| crtc_it
== crtc
)
4057 if (other_active_crtc
)
4060 other_active_crtc
= crtc_it
;
4062 if (!other_active_crtc
)
4065 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
4066 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
4069 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
4071 struct drm_device
*dev
= crtc
->dev
;
4072 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4073 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4074 struct intel_encoder
*encoder
;
4075 int pipe
= intel_crtc
->pipe
;
4076 enum plane plane
= intel_crtc
->plane
;
4078 WARN_ON(!crtc
->enabled
);
4080 if (intel_crtc
->active
)
4083 if (intel_crtc_to_shared_dpll(intel_crtc
))
4084 intel_enable_shared_dpll(intel_crtc
);
4086 if (intel_crtc
->config
.has_dp_encoder
)
4087 intel_dp_set_m_n(intel_crtc
);
4089 intel_set_pipe_timings(intel_crtc
);
4091 if (intel_crtc
->config
.has_pch_encoder
) {
4092 intel_cpu_transcoder_set_m_n(intel_crtc
,
4093 &intel_crtc
->config
.fdi_m_n
);
4096 haswell_set_pipeconf(crtc
);
4098 intel_set_pipe_csc(crtc
);
4100 /* Set up the display plane register */
4101 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
| DISPPLANE_PIPE_CSC_ENABLE
);
4102 POSTING_READ(DSPCNTR(plane
));
4104 dev_priv
->display
.update_primary_plane(crtc
, crtc
->primary
->fb
,
4107 intel_crtc
->active
= true;
4109 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
4110 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4111 if (encoder
->pre_enable
)
4112 encoder
->pre_enable(encoder
);
4114 if (intel_crtc
->config
.has_pch_encoder
) {
4115 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
4116 dev_priv
->display
.fdi_link_train(crtc
);
4119 intel_ddi_enable_pipe_clock(intel_crtc
);
4121 ironlake_pfit_enable(intel_crtc
);
4124 * On ILK+ LUT must be loaded before the pipe is running but with
4127 intel_crtc_load_lut(crtc
);
4129 intel_ddi_set_pipe_settings(crtc
);
4130 intel_ddi_enable_transcoder_func(crtc
);
4132 intel_update_watermarks(crtc
);
4133 intel_enable_pipe(intel_crtc
);
4135 if (intel_crtc
->config
.has_pch_encoder
)
4136 lpt_pch_enable(crtc
);
4138 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4139 encoder
->enable(encoder
);
4140 intel_opregion_notify_encoder(encoder
, true);
4143 /* If we change the relative order between pipe/planes enabling, we need
4144 * to change the workaround. */
4145 haswell_mode_set_planes_workaround(intel_crtc
);
4146 intel_crtc_enable_planes(crtc
);
4149 static void ironlake_pfit_disable(struct intel_crtc
*crtc
)
4151 struct drm_device
*dev
= crtc
->base
.dev
;
4152 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4153 int pipe
= crtc
->pipe
;
4155 /* To avoid upsetting the power well on haswell only disable the pfit if
4156 * it's in use. The hw state code will make sure we get this right. */
4157 if (crtc
->config
.pch_pfit
.enabled
) {
4158 I915_WRITE(PF_CTL(pipe
), 0);
4159 I915_WRITE(PF_WIN_POS(pipe
), 0);
4160 I915_WRITE(PF_WIN_SZ(pipe
), 0);
4164 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
4166 struct drm_device
*dev
= crtc
->dev
;
4167 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4168 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4169 struct intel_encoder
*encoder
;
4170 int pipe
= intel_crtc
->pipe
;
4173 if (!intel_crtc
->active
)
4176 intel_crtc_disable_planes(crtc
);
4178 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4179 encoder
->disable(encoder
);
4181 if (intel_crtc
->config
.has_pch_encoder
)
4182 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, false);
4184 intel_disable_pipe(dev_priv
, pipe
);
4186 ironlake_pfit_disable(intel_crtc
);
4188 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4189 if (encoder
->post_disable
)
4190 encoder
->post_disable(encoder
);
4192 if (intel_crtc
->config
.has_pch_encoder
) {
4193 ironlake_fdi_disable(crtc
);
4195 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
4196 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
4198 if (HAS_PCH_CPT(dev
)) {
4199 /* disable TRANS_DP_CTL */
4200 reg
= TRANS_DP_CTL(pipe
);
4201 temp
= I915_READ(reg
);
4202 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
4203 TRANS_DP_PORT_SEL_MASK
);
4204 temp
|= TRANS_DP_PORT_SEL_NONE
;
4205 I915_WRITE(reg
, temp
);
4207 /* disable DPLL_SEL */
4208 temp
= I915_READ(PCH_DPLL_SEL
);
4209 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
4210 I915_WRITE(PCH_DPLL_SEL
, temp
);
4213 /* disable PCH DPLL */
4214 intel_disable_shared_dpll(intel_crtc
);
4216 ironlake_fdi_pll_disable(intel_crtc
);
4219 intel_crtc
->active
= false;
4220 intel_update_watermarks(crtc
);
4222 mutex_lock(&dev
->struct_mutex
);
4223 intel_update_fbc(dev
);
4224 mutex_unlock(&dev
->struct_mutex
);
4227 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
4229 struct drm_device
*dev
= crtc
->dev
;
4230 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4231 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4232 struct intel_encoder
*encoder
;
4233 int pipe
= intel_crtc
->pipe
;
4234 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
4236 if (!intel_crtc
->active
)
4239 intel_crtc_disable_planes(crtc
);
4241 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4242 intel_opregion_notify_encoder(encoder
, false);
4243 encoder
->disable(encoder
);
4246 if (intel_crtc
->config
.has_pch_encoder
)
4247 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, false);
4248 intel_disable_pipe(dev_priv
, pipe
);
4250 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
4252 ironlake_pfit_disable(intel_crtc
);
4254 intel_ddi_disable_pipe_clock(intel_crtc
);
4256 if (intel_crtc
->config
.has_pch_encoder
) {
4257 lpt_disable_pch_transcoder(dev_priv
);
4258 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
4259 intel_ddi_fdi_disable(crtc
);
4262 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4263 if (encoder
->post_disable
)
4264 encoder
->post_disable(encoder
);
4266 intel_crtc
->active
= false;
4267 intel_update_watermarks(crtc
);
4269 mutex_lock(&dev
->struct_mutex
);
4270 intel_update_fbc(dev
);
4271 mutex_unlock(&dev
->struct_mutex
);
4273 if (intel_crtc_to_shared_dpll(intel_crtc
))
4274 intel_disable_shared_dpll(intel_crtc
);
4277 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
4279 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4280 intel_put_shared_dpll(intel_crtc
);
4284 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
4286 struct drm_device
*dev
= crtc
->base
.dev
;
4287 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4288 struct intel_crtc_config
*pipe_config
= &crtc
->config
;
4290 if (!crtc
->config
.gmch_pfit
.control
)
4294 * The panel fitter should only be adjusted whilst the pipe is disabled,
4295 * according to register description and PRM.
4297 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
4298 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
4300 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
4301 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
4303 /* Border color in case we don't scale up to the full screen. Black by
4304 * default, change to something else for debugging. */
4305 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
4308 #define for_each_power_domain(domain, mask) \
4309 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4310 if ((1 << (domain)) & (mask))
4312 enum intel_display_power_domain
4313 intel_display_port_power_domain(struct intel_encoder
*intel_encoder
)
4315 struct drm_device
*dev
= intel_encoder
->base
.dev
;
4316 struct intel_digital_port
*intel_dig_port
;
4318 switch (intel_encoder
->type
) {
4319 case INTEL_OUTPUT_UNKNOWN
:
4320 /* Only DDI platforms should ever use this output type */
4321 WARN_ON_ONCE(!HAS_DDI(dev
));
4322 case INTEL_OUTPUT_DISPLAYPORT
:
4323 case INTEL_OUTPUT_HDMI
:
4324 case INTEL_OUTPUT_EDP
:
4325 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
4326 switch (intel_dig_port
->port
) {
4328 return POWER_DOMAIN_PORT_DDI_A_4_LANES
;
4330 return POWER_DOMAIN_PORT_DDI_B_4_LANES
;
4332 return POWER_DOMAIN_PORT_DDI_C_4_LANES
;
4334 return POWER_DOMAIN_PORT_DDI_D_4_LANES
;
4337 return POWER_DOMAIN_PORT_OTHER
;
4339 case INTEL_OUTPUT_ANALOG
:
4340 return POWER_DOMAIN_PORT_CRT
;
4341 case INTEL_OUTPUT_DSI
:
4342 return POWER_DOMAIN_PORT_DSI
;
4344 return POWER_DOMAIN_PORT_OTHER
;
4348 static unsigned long get_crtc_power_domains(struct drm_crtc
*crtc
)
4350 struct drm_device
*dev
= crtc
->dev
;
4351 struct intel_encoder
*intel_encoder
;
4352 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4353 enum pipe pipe
= intel_crtc
->pipe
;
4355 enum transcoder transcoder
;
4357 transcoder
= intel_pipe_to_cpu_transcoder(dev
->dev_private
, pipe
);
4359 mask
= BIT(POWER_DOMAIN_PIPE(pipe
));
4360 mask
|= BIT(POWER_DOMAIN_TRANSCODER(transcoder
));
4361 if (intel_crtc
->config
.pch_pfit
.enabled
||
4362 intel_crtc
->config
.pch_pfit
.force_thru
)
4363 mask
|= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe
));
4365 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
4366 mask
|= BIT(intel_display_port_power_domain(intel_encoder
));
4371 void intel_display_set_init_power(struct drm_i915_private
*dev_priv
,
4374 if (dev_priv
->power_domains
.init_power_on
== enable
)
4378 intel_display_power_get(dev_priv
, POWER_DOMAIN_INIT
);
4380 intel_display_power_put(dev_priv
, POWER_DOMAIN_INIT
);
4382 dev_priv
->power_domains
.init_power_on
= enable
;
4385 static void modeset_update_crtc_power_domains(struct drm_device
*dev
)
4387 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4388 unsigned long pipe_domains
[I915_MAX_PIPES
] = { 0, };
4389 struct intel_crtc
*crtc
;
4392 * First get all needed power domains, then put all unneeded, to avoid
4393 * any unnecessary toggling of the power wells.
4395 for_each_intel_crtc(dev
, crtc
) {
4396 enum intel_display_power_domain domain
;
4398 if (!crtc
->base
.enabled
)
4401 pipe_domains
[crtc
->pipe
] = get_crtc_power_domains(&crtc
->base
);
4403 for_each_power_domain(domain
, pipe_domains
[crtc
->pipe
])
4404 intel_display_power_get(dev_priv
, domain
);
4407 for_each_intel_crtc(dev
, crtc
) {
4408 enum intel_display_power_domain domain
;
4410 for_each_power_domain(domain
, crtc
->enabled_power_domains
)
4411 intel_display_power_put(dev_priv
, domain
);
4413 crtc
->enabled_power_domains
= pipe_domains
[crtc
->pipe
];
4416 intel_display_set_init_power(dev_priv
, false);
4419 /* returns HPLL frequency in kHz */
4420 static int valleyview_get_vco(struct drm_i915_private
*dev_priv
)
4422 int hpll_freq
, vco_freq
[] = { 800, 1600, 2000, 2400 };
4424 /* Obtain SKU information */
4425 mutex_lock(&dev_priv
->dpio_lock
);
4426 hpll_freq
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
) &
4427 CCK_FUSE_HPLL_FREQ_MASK
;
4428 mutex_unlock(&dev_priv
->dpio_lock
);
4430 return vco_freq
[hpll_freq
] * 1000;
4433 static void vlv_update_cdclk(struct drm_device
*dev
)
4435 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4437 dev_priv
->vlv_cdclk_freq
= dev_priv
->display
.get_display_clock_speed(dev
);
4438 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz",
4439 dev_priv
->vlv_cdclk_freq
);
4442 * Program the gmbus_freq based on the cdclk frequency.
4443 * BSpec erroneously claims we should aim for 4MHz, but
4444 * in fact 1MHz is the correct frequency.
4446 I915_WRITE(GMBUSFREQ_VLV
, dev_priv
->vlv_cdclk_freq
);
4449 /* Adjust CDclk dividers to allow high res or save power if possible */
4450 static void valleyview_set_cdclk(struct drm_device
*dev
, int cdclk
)
4452 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4455 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
) != dev_priv
->vlv_cdclk_freq
);
4457 if (cdclk
>= 320000) /* jump to highest voltage for 400MHz too */
4459 else if (cdclk
== 266667)
4464 mutex_lock(&dev_priv
->rps
.hw_lock
);
4465 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
4466 val
&= ~DSPFREQGUAR_MASK
;
4467 val
|= (cmd
<< DSPFREQGUAR_SHIFT
);
4468 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
4469 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
4470 DSPFREQSTAT_MASK
) == (cmd
<< DSPFREQSTAT_SHIFT
),
4472 DRM_ERROR("timed out waiting for CDclk change\n");
4474 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4476 if (cdclk
== 400000) {
4479 vco
= valleyview_get_vco(dev_priv
);
4480 divider
= DIV_ROUND_CLOSEST(vco
<< 1, cdclk
) - 1;
4482 mutex_lock(&dev_priv
->dpio_lock
);
4483 /* adjust cdclk divider */
4484 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
4485 val
&= ~DISPLAY_FREQUENCY_VALUES
;
4487 vlv_cck_write(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
, val
);
4489 if (wait_for((vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
) &
4490 DISPLAY_FREQUENCY_STATUS
) == (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
4492 DRM_ERROR("timed out waiting for CDclk change\n");
4493 mutex_unlock(&dev_priv
->dpio_lock
);
4496 mutex_lock(&dev_priv
->dpio_lock
);
4497 /* adjust self-refresh exit latency value */
4498 val
= vlv_bunit_read(dev_priv
, BUNIT_REG_BISOC
);
4502 * For high bandwidth configs, we set a higher latency in the bunit
4503 * so that the core display fetch happens in time to avoid underruns.
4505 if (cdclk
== 400000)
4506 val
|= 4500 / 250; /* 4.5 usec */
4508 val
|= 3000 / 250; /* 3.0 usec */
4509 vlv_bunit_write(dev_priv
, BUNIT_REG_BISOC
, val
);
4510 mutex_unlock(&dev_priv
->dpio_lock
);
4512 vlv_update_cdclk(dev
);
4515 static int valleyview_calc_cdclk(struct drm_i915_private
*dev_priv
,
4518 int vco
= valleyview_get_vco(dev_priv
);
4519 int freq_320
= (vco
<< 1) % 320000 != 0 ? 333333 : 320000;
4522 * Really only a few cases to deal with, as only 4 CDclks are supported:
4525 * 320/333MHz (depends on HPLL freq)
4527 * So we check to see whether we're above 90% of the lower bin and
4530 * We seem to get an unstable or solid color picture at 200MHz.
4531 * Not sure what's wrong. For now use 200MHz only when all pipes
4534 if (max_pixclk
> freq_320
*9/10)
4536 else if (max_pixclk
> 266667*9/10)
4538 else if (max_pixclk
> 0)
4544 /* compute the max pixel clock for new configuration */
4545 static int intel_mode_max_pixclk(struct drm_i915_private
*dev_priv
)
4547 struct drm_device
*dev
= dev_priv
->dev
;
4548 struct intel_crtc
*intel_crtc
;
4551 for_each_intel_crtc(dev
, intel_crtc
) {
4552 if (intel_crtc
->new_enabled
)
4553 max_pixclk
= max(max_pixclk
,
4554 intel_crtc
->new_config
->adjusted_mode
.crtc_clock
);
4560 static void valleyview_modeset_global_pipes(struct drm_device
*dev
,
4561 unsigned *prepare_pipes
)
4563 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4564 struct intel_crtc
*intel_crtc
;
4565 int max_pixclk
= intel_mode_max_pixclk(dev_priv
);
4567 if (valleyview_calc_cdclk(dev_priv
, max_pixclk
) ==
4568 dev_priv
->vlv_cdclk_freq
)
4571 /* disable/enable all currently active pipes while we change cdclk */
4572 for_each_intel_crtc(dev
, intel_crtc
)
4573 if (intel_crtc
->base
.enabled
)
4574 *prepare_pipes
|= (1 << intel_crtc
->pipe
);
4577 static void valleyview_modeset_global_resources(struct drm_device
*dev
)
4579 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4580 int max_pixclk
= intel_mode_max_pixclk(dev_priv
);
4581 int req_cdclk
= valleyview_calc_cdclk(dev_priv
, max_pixclk
);
4583 if (req_cdclk
!= dev_priv
->vlv_cdclk_freq
)
4584 valleyview_set_cdclk(dev
, req_cdclk
);
4585 modeset_update_crtc_power_domains(dev
);
4588 static void valleyview_crtc_enable(struct drm_crtc
*crtc
)
4590 struct drm_device
*dev
= crtc
->dev
;
4591 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4592 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4593 struct intel_encoder
*encoder
;
4594 int pipe
= intel_crtc
->pipe
;
4595 int plane
= intel_crtc
->plane
;
4599 WARN_ON(!crtc
->enabled
);
4601 if (intel_crtc
->active
)
4604 is_dsi
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
);
4606 if (!is_dsi
&& !IS_CHERRYVIEW(dev
))
4607 vlv_prepare_pll(intel_crtc
);
4609 /* Set up the display plane register */
4610 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
4612 if (intel_crtc
->config
.has_dp_encoder
)
4613 intel_dp_set_m_n(intel_crtc
);
4615 intel_set_pipe_timings(intel_crtc
);
4617 /* pipesrc and dspsize control the size that is scaled from,
4618 * which should always be the user's requested size.
4620 I915_WRITE(DSPSIZE(plane
),
4621 ((intel_crtc
->config
.pipe_src_h
- 1) << 16) |
4622 (intel_crtc
->config
.pipe_src_w
- 1));
4623 I915_WRITE(DSPPOS(plane
), 0);
4625 i9xx_set_pipeconf(intel_crtc
);
4627 I915_WRITE(DSPCNTR(plane
), dspcntr
);
4628 POSTING_READ(DSPCNTR(plane
));
4630 dev_priv
->display
.update_primary_plane(crtc
, crtc
->primary
->fb
,
4633 intel_crtc
->active
= true;
4635 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
4637 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4638 if (encoder
->pre_pll_enable
)
4639 encoder
->pre_pll_enable(encoder
);
4642 if (IS_CHERRYVIEW(dev
))
4643 chv_enable_pll(intel_crtc
);
4645 vlv_enable_pll(intel_crtc
);
4648 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4649 if (encoder
->pre_enable
)
4650 encoder
->pre_enable(encoder
);
4652 i9xx_pfit_enable(intel_crtc
);
4654 intel_crtc_load_lut(crtc
);
4656 intel_update_watermarks(crtc
);
4657 intel_enable_pipe(intel_crtc
);
4659 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4660 encoder
->enable(encoder
);
4662 intel_crtc_enable_planes(crtc
);
4664 /* Underruns don't raise interrupts, so check manually. */
4665 i9xx_check_fifo_underruns(dev
);
4668 static void i9xx_set_pll_dividers(struct intel_crtc
*crtc
)
4670 struct drm_device
*dev
= crtc
->base
.dev
;
4671 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4673 I915_WRITE(FP0(crtc
->pipe
), crtc
->config
.dpll_hw_state
.fp0
);
4674 I915_WRITE(FP1(crtc
->pipe
), crtc
->config
.dpll_hw_state
.fp1
);
4677 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
4679 struct drm_device
*dev
= crtc
->dev
;
4680 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4681 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4682 struct intel_encoder
*encoder
;
4683 int pipe
= intel_crtc
->pipe
;
4684 int plane
= intel_crtc
->plane
;
4687 WARN_ON(!crtc
->enabled
);
4689 if (intel_crtc
->active
)
4692 i9xx_set_pll_dividers(intel_crtc
);
4694 /* Set up the display plane register */
4695 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
4698 dspcntr
&= ~DISPPLANE_SEL_PIPE_MASK
;
4700 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
4702 if (intel_crtc
->config
.has_dp_encoder
)
4703 intel_dp_set_m_n(intel_crtc
);
4705 intel_set_pipe_timings(intel_crtc
);
4707 /* pipesrc and dspsize control the size that is scaled from,
4708 * which should always be the user's requested size.
4710 I915_WRITE(DSPSIZE(plane
),
4711 ((intel_crtc
->config
.pipe_src_h
- 1) << 16) |
4712 (intel_crtc
->config
.pipe_src_w
- 1));
4713 I915_WRITE(DSPPOS(plane
), 0);
4715 i9xx_set_pipeconf(intel_crtc
);
4717 I915_WRITE(DSPCNTR(plane
), dspcntr
);
4718 POSTING_READ(DSPCNTR(plane
));
4720 dev_priv
->display
.update_primary_plane(crtc
, crtc
->primary
->fb
,
4723 intel_crtc
->active
= true;
4726 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
4728 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4729 if (encoder
->pre_enable
)
4730 encoder
->pre_enable(encoder
);
4732 i9xx_enable_pll(intel_crtc
);
4734 i9xx_pfit_enable(intel_crtc
);
4736 intel_crtc_load_lut(crtc
);
4738 intel_update_watermarks(crtc
);
4739 intel_enable_pipe(intel_crtc
);
4741 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4742 encoder
->enable(encoder
);
4744 intel_crtc_enable_planes(crtc
);
4747 * Gen2 reports pipe underruns whenever all planes are disabled.
4748 * So don't enable underrun reporting before at least some planes
4750 * FIXME: Need to fix the logic to work when we turn off all planes
4751 * but leave the pipe running.
4754 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
4756 /* Underruns don't raise interrupts, so check manually. */
4757 i9xx_check_fifo_underruns(dev
);
4760 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
4762 struct drm_device
*dev
= crtc
->base
.dev
;
4763 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4765 if (!crtc
->config
.gmch_pfit
.control
)
4768 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
4770 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4771 I915_READ(PFIT_CONTROL
));
4772 I915_WRITE(PFIT_CONTROL
, 0);
4775 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
4777 struct drm_device
*dev
= crtc
->dev
;
4778 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4779 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4780 struct intel_encoder
*encoder
;
4781 int pipe
= intel_crtc
->pipe
;
4783 if (!intel_crtc
->active
)
4787 * Gen2 reports pipe underruns whenever all planes are disabled.
4788 * So diasble underrun reporting before all the planes get disabled.
4789 * FIXME: Need to fix the logic to work when we turn off all planes
4790 * but leave the pipe running.
4793 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, false);
4796 * Vblank time updates from the shadow to live plane control register
4797 * are blocked if the memory self-refresh mode is active at that
4798 * moment. So to make sure the plane gets truly disabled, disable
4799 * first the self-refresh mode. The self-refresh enable bit in turn
4800 * will be checked/applied by the HW only at the next frame start
4801 * event which is after the vblank start event, so we need to have a
4802 * wait-for-vblank between disabling the plane and the pipe.
4804 intel_set_memory_cxsr(dev_priv
, false);
4805 intel_crtc_disable_planes(crtc
);
4807 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4808 encoder
->disable(encoder
);
4811 * On gen2 planes are double buffered but the pipe isn't, so we must
4812 * wait for planes to fully turn off before disabling the pipe.
4813 * We also need to wait on all gmch platforms because of the
4814 * self-refresh mode constraint explained above.
4816 intel_wait_for_vblank(dev
, pipe
);
4818 intel_disable_pipe(dev_priv
, pipe
);
4820 i9xx_pfit_disable(intel_crtc
);
4822 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4823 if (encoder
->post_disable
)
4824 encoder
->post_disable(encoder
);
4826 if (!intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
)) {
4827 if (IS_CHERRYVIEW(dev
))
4828 chv_disable_pll(dev_priv
, pipe
);
4829 else if (IS_VALLEYVIEW(dev
))
4830 vlv_disable_pll(dev_priv
, pipe
);
4832 i9xx_disable_pll(dev_priv
, pipe
);
4836 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, false);
4838 intel_crtc
->active
= false;
4839 intel_update_watermarks(crtc
);
4841 mutex_lock(&dev
->struct_mutex
);
4842 intel_update_fbc(dev
);
4843 mutex_unlock(&dev
->struct_mutex
);
4846 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
4850 static void intel_crtc_update_sarea(struct drm_crtc
*crtc
,
4853 struct drm_device
*dev
= crtc
->dev
;
4854 struct drm_i915_master_private
*master_priv
;
4855 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4856 int pipe
= intel_crtc
->pipe
;
4858 if (!dev
->primary
->master
)
4861 master_priv
= dev
->primary
->master
->driver_priv
;
4862 if (!master_priv
->sarea_priv
)
4867 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
4868 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
4871 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
4872 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
4875 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe
));
4881 * Sets the power management mode of the pipe and plane.
4883 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
4885 struct drm_device
*dev
= crtc
->dev
;
4886 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4887 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4888 struct intel_encoder
*intel_encoder
;
4889 enum intel_display_power_domain domain
;
4890 unsigned long domains
;
4891 bool enable
= false;
4893 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
4894 enable
|= intel_encoder
->connectors_active
;
4897 if (!intel_crtc
->active
) {
4899 * FIXME: DDI plls and relevant code isn't converted
4900 * yet, so do runtime PM for DPMS only for all other
4901 * platforms for now.
4903 if (!HAS_DDI(dev
)) {
4904 domains
= get_crtc_power_domains(crtc
);
4905 for_each_power_domain(domain
, domains
)
4906 intel_display_power_get(dev_priv
, domain
);
4907 intel_crtc
->enabled_power_domains
= domains
;
4910 dev_priv
->display
.crtc_enable(crtc
);
4913 if (intel_crtc
->active
) {
4914 dev_priv
->display
.crtc_disable(crtc
);
4916 if (!HAS_DDI(dev
)) {
4917 domains
= intel_crtc
->enabled_power_domains
;
4918 for_each_power_domain(domain
, domains
)
4919 intel_display_power_put(dev_priv
, domain
);
4920 intel_crtc
->enabled_power_domains
= 0;
4925 intel_crtc_update_sarea(crtc
, enable
);
4928 static void intel_crtc_disable(struct drm_crtc
*crtc
)
4930 struct drm_device
*dev
= crtc
->dev
;
4931 struct drm_connector
*connector
;
4932 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4933 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(crtc
->primary
->fb
);
4934 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
4936 /* crtc should still be enabled when we disable it. */
4937 WARN_ON(!crtc
->enabled
);
4939 dev_priv
->display
.crtc_disable(crtc
);
4940 intel_crtc_update_sarea(crtc
, false);
4941 dev_priv
->display
.off(crtc
);
4943 assert_plane_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->plane
);
4944 assert_cursor_disabled(dev_priv
, pipe
);
4945 assert_pipe_disabled(dev
->dev_private
, pipe
);
4947 if (crtc
->primary
->fb
) {
4948 mutex_lock(&dev
->struct_mutex
);
4949 intel_unpin_fb_obj(old_obj
);
4950 i915_gem_track_fb(old_obj
, NULL
,
4951 INTEL_FRONTBUFFER_PRIMARY(pipe
));
4952 mutex_unlock(&dev
->struct_mutex
);
4953 crtc
->primary
->fb
= NULL
;
4956 /* Update computed state. */
4957 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
4958 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
4961 if (connector
->encoder
->crtc
!= crtc
)
4964 connector
->dpms
= DRM_MODE_DPMS_OFF
;
4965 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
4969 void intel_encoder_destroy(struct drm_encoder
*encoder
)
4971 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
4973 drm_encoder_cleanup(encoder
);
4974 kfree(intel_encoder
);
4977 /* Simple dpms helper for encoders with just one connector, no cloning and only
4978 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4979 * state of the entire output pipe. */
4980 static void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
4982 if (mode
== DRM_MODE_DPMS_ON
) {
4983 encoder
->connectors_active
= true;
4985 intel_crtc_update_dpms(encoder
->base
.crtc
);
4987 encoder
->connectors_active
= false;
4989 intel_crtc_update_dpms(encoder
->base
.crtc
);
4993 /* Cross check the actual hw state with our own modeset state tracking (and it's
4994 * internal consistency). */
4995 static void intel_connector_check_state(struct intel_connector
*connector
)
4997 if (connector
->get_hw_state(connector
)) {
4998 struct intel_encoder
*encoder
= connector
->encoder
;
4999 struct drm_crtc
*crtc
;
5000 bool encoder_enabled
;
5003 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5004 connector
->base
.base
.id
,
5005 connector
->base
.name
);
5007 WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
5008 "wrong connector dpms state\n");
5009 WARN(connector
->base
.encoder
!= &encoder
->base
,
5010 "active connector not linked to encoder\n");
5011 WARN(!encoder
->connectors_active
,
5012 "encoder->connectors_active not set\n");
5014 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
5015 WARN(!encoder_enabled
, "encoder not enabled\n");
5016 if (WARN_ON(!encoder
->base
.crtc
))
5019 crtc
= encoder
->base
.crtc
;
5021 WARN(!crtc
->enabled
, "crtc not enabled\n");
5022 WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
5023 WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
5024 "encoder active on the wrong pipe\n");
5028 /* Even simpler default implementation, if there's really no special case to
5030 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
5032 /* All the simple cases only support two dpms states. */
5033 if (mode
!= DRM_MODE_DPMS_ON
)
5034 mode
= DRM_MODE_DPMS_OFF
;
5036 if (mode
== connector
->dpms
)
5039 connector
->dpms
= mode
;
5041 /* Only need to change hw state when actually enabled */
5042 if (connector
->encoder
)
5043 intel_encoder_dpms(to_intel_encoder(connector
->encoder
), mode
);
5045 intel_modeset_check_state(connector
->dev
);
5048 /* Simple connector->get_hw_state implementation for encoders that support only
5049 * one connector and no cloning and hence the encoder state determines the state
5050 * of the connector. */
5051 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
5054 struct intel_encoder
*encoder
= connector
->encoder
;
5056 return encoder
->get_hw_state(encoder
, &pipe
);
5059 static bool ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
5060 struct intel_crtc_config
*pipe_config
)
5062 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5063 struct intel_crtc
*pipe_B_crtc
=
5064 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
5066 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5067 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5068 if (pipe_config
->fdi_lanes
> 4) {
5069 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5070 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5074 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
5075 if (pipe_config
->fdi_lanes
> 2) {
5076 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5077 pipe_config
->fdi_lanes
);
5084 if (INTEL_INFO(dev
)->num_pipes
== 2)
5087 /* Ivybridge 3 pipe is really complicated */
5092 if (dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]->enabled
&&
5093 pipe_config
->fdi_lanes
> 2) {
5094 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5095 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5100 if (!pipe_has_enabled_pch(pipe_B_crtc
) ||
5101 pipe_B_crtc
->config
.fdi_lanes
<= 2) {
5102 if (pipe_config
->fdi_lanes
> 2) {
5103 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5104 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5108 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5118 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
5119 struct intel_crtc_config
*pipe_config
)
5121 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5122 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
5123 int lane
, link_bw
, fdi_dotclock
;
5124 bool setup_ok
, needs_recompute
= false;
5127 /* FDI is a binary signal running at ~2.7GHz, encoding
5128 * each output octet as 10 bits. The actual frequency
5129 * is stored as a divider into a 100MHz clock, and the
5130 * mode pixel clock is stored in units of 1KHz.
5131 * Hence the bw of each lane in terms of the mode signal
5134 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
5136 fdi_dotclock
= adjusted_mode
->crtc_clock
;
5138 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
5139 pipe_config
->pipe_bpp
);
5141 pipe_config
->fdi_lanes
= lane
;
5143 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
5144 link_bw
, &pipe_config
->fdi_m_n
);
5146 setup_ok
= ironlake_check_fdi_lanes(intel_crtc
->base
.dev
,
5147 intel_crtc
->pipe
, pipe_config
);
5148 if (!setup_ok
&& pipe_config
->pipe_bpp
> 6*3) {
5149 pipe_config
->pipe_bpp
-= 2*3;
5150 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5151 pipe_config
->pipe_bpp
);
5152 needs_recompute
= true;
5153 pipe_config
->bw_constrained
= true;
5158 if (needs_recompute
)
5161 return setup_ok
? 0 : -EINVAL
;
5164 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
5165 struct intel_crtc_config
*pipe_config
)
5167 pipe_config
->ips_enabled
= i915
.enable_ips
&&
5168 hsw_crtc_supports_ips(crtc
) &&
5169 pipe_config
->pipe_bpp
<= 24;
5172 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
5173 struct intel_crtc_config
*pipe_config
)
5175 struct drm_device
*dev
= crtc
->base
.dev
;
5176 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
5178 /* FIXME should check pixel clock limits on all platforms */
5179 if (INTEL_INFO(dev
)->gen
< 4) {
5180 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5182 dev_priv
->display
.get_display_clock_speed(dev
);
5185 * Enable pixel doubling when the dot clock
5186 * is > 90% of the (display) core speed.
5188 * GDG double wide on either pipe,
5189 * otherwise pipe A only.
5191 if ((crtc
->pipe
== PIPE_A
|| IS_I915G(dev
)) &&
5192 adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10) {
5194 pipe_config
->double_wide
= true;
5197 if (adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10)
5202 * Pipe horizontal size must be even in:
5204 * - LVDS dual channel mode
5205 * - Double wide pipe
5207 if ((intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
5208 intel_is_dual_link_lvds(dev
)) || pipe_config
->double_wide
)
5209 pipe_config
->pipe_src_w
&= ~1;
5211 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5212 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5214 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
5215 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
5218 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) && pipe_config
->pipe_bpp
> 10*3) {
5219 pipe_config
->pipe_bpp
= 10*3; /* 12bpc is gen5+ */
5220 } else if (INTEL_INFO(dev
)->gen
<= 4 && pipe_config
->pipe_bpp
> 8*3) {
5221 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5223 pipe_config
->pipe_bpp
= 8*3;
5227 hsw_compute_ips_config(crtc
, pipe_config
);
5230 * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the
5231 * old clock survives for now.
5233 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
) || HAS_DDI(dev
))
5234 pipe_config
->shared_dpll
= crtc
->config
.shared_dpll
;
5236 if (pipe_config
->has_pch_encoder
)
5237 return ironlake_fdi_compute_config(crtc
, pipe_config
);
5242 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
5244 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5245 int vco
= valleyview_get_vco(dev_priv
);
5249 mutex_lock(&dev_priv
->dpio_lock
);
5250 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
5251 mutex_unlock(&dev_priv
->dpio_lock
);
5253 divider
= val
& DISPLAY_FREQUENCY_VALUES
;
5255 WARN((val
& DISPLAY_FREQUENCY_STATUS
) !=
5256 (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
5257 "cdclk change in progress\n");
5259 return DIV_ROUND_CLOSEST(vco
<< 1, divider
+ 1);
5262 static int i945_get_display_clock_speed(struct drm_device
*dev
)
5267 static int i915_get_display_clock_speed(struct drm_device
*dev
)
5272 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
5277 static int pnv_get_display_clock_speed(struct drm_device
*dev
)
5281 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
5283 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
5284 case GC_DISPLAY_CLOCK_267_MHZ_PNV
:
5286 case GC_DISPLAY_CLOCK_333_MHZ_PNV
:
5288 case GC_DISPLAY_CLOCK_444_MHZ_PNV
:
5290 case GC_DISPLAY_CLOCK_200_MHZ_PNV
:
5293 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc
);
5294 case GC_DISPLAY_CLOCK_133_MHZ_PNV
:
5296 case GC_DISPLAY_CLOCK_167_MHZ_PNV
:
5301 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
5305 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
5307 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
5310 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
5311 case GC_DISPLAY_CLOCK_333_MHZ
:
5314 case GC_DISPLAY_CLOCK_190_200_MHZ
:
5320 static int i865_get_display_clock_speed(struct drm_device
*dev
)
5325 static int i855_get_display_clock_speed(struct drm_device
*dev
)
5328 /* Assume that the hardware is in the high speed state. This
5329 * should be the default.
5331 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
5332 case GC_CLOCK_133_200
:
5333 case GC_CLOCK_100_200
:
5335 case GC_CLOCK_166_250
:
5337 case GC_CLOCK_100_133
:
5341 /* Shouldn't happen */
5345 static int i830_get_display_clock_speed(struct drm_device
*dev
)
5351 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
5353 while (*num
> DATA_LINK_M_N_MASK
||
5354 *den
> DATA_LINK_M_N_MASK
) {
5360 static void compute_m_n(unsigned int m
, unsigned int n
,
5361 uint32_t *ret_m
, uint32_t *ret_n
)
5363 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
5364 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
5365 intel_reduce_m_n_ratio(ret_m
, ret_n
);
5369 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
5370 int pixel_clock
, int link_clock
,
5371 struct intel_link_m_n
*m_n
)
5375 compute_m_n(bits_per_pixel
* pixel_clock
,
5376 link_clock
* nlanes
* 8,
5377 &m_n
->gmch_m
, &m_n
->gmch_n
);
5379 compute_m_n(pixel_clock
, link_clock
,
5380 &m_n
->link_m
, &m_n
->link_n
);
5383 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
5385 if (i915
.panel_use_ssc
>= 0)
5386 return i915
.panel_use_ssc
!= 0;
5387 return dev_priv
->vbt
.lvds_use_ssc
5388 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
5391 static int i9xx_get_refclk(struct drm_crtc
*crtc
, int num_connectors
)
5393 struct drm_device
*dev
= crtc
->dev
;
5394 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5397 if (IS_VALLEYVIEW(dev
)) {
5399 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
5400 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
5401 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
5402 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
5403 } else if (!IS_GEN2(dev
)) {
5412 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
5414 return (1 << dpll
->n
) << 16 | dpll
->m2
;
5417 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
5419 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
5422 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
5423 intel_clock_t
*reduced_clock
)
5425 struct drm_device
*dev
= crtc
->base
.dev
;
5428 if (IS_PINEVIEW(dev
)) {
5429 fp
= pnv_dpll_compute_fp(&crtc
->config
.dpll
);
5431 fp2
= pnv_dpll_compute_fp(reduced_clock
);
5433 fp
= i9xx_dpll_compute_fp(&crtc
->config
.dpll
);
5435 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
5438 crtc
->config
.dpll_hw_state
.fp0
= fp
;
5440 crtc
->lowfreq_avail
= false;
5441 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
5442 reduced_clock
&& i915
.powersave
) {
5443 crtc
->config
.dpll_hw_state
.fp1
= fp2
;
5444 crtc
->lowfreq_avail
= true;
5446 crtc
->config
.dpll_hw_state
.fp1
= fp
;
5450 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
5456 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5457 * and set it to a reasonable value instead.
5459 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
5460 reg_val
&= 0xffffff00;
5461 reg_val
|= 0x00000030;
5462 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
5464 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
5465 reg_val
&= 0x8cffffff;
5466 reg_val
= 0x8c000000;
5467 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
5469 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
5470 reg_val
&= 0xffffff00;
5471 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
5473 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
5474 reg_val
&= 0x00ffffff;
5475 reg_val
|= 0xb0000000;
5476 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
5479 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
5480 struct intel_link_m_n
*m_n
)
5482 struct drm_device
*dev
= crtc
->base
.dev
;
5483 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5484 int pipe
= crtc
->pipe
;
5486 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5487 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
5488 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
5489 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
5492 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
5493 struct intel_link_m_n
*m_n
)
5495 struct drm_device
*dev
= crtc
->base
.dev
;
5496 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5497 int pipe
= crtc
->pipe
;
5498 enum transcoder transcoder
= crtc
->config
.cpu_transcoder
;
5500 if (INTEL_INFO(dev
)->gen
>= 5) {
5501 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5502 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
5503 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
5504 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
5506 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5507 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
5508 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
5509 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
5513 static void intel_dp_set_m_n(struct intel_crtc
*crtc
)
5515 if (crtc
->config
.has_pch_encoder
)
5516 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
5518 intel_cpu_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
5521 static void vlv_update_pll(struct intel_crtc
*crtc
)
5526 * Enable DPIO clock input. We should never disable the reference
5527 * clock for pipe B, since VGA hotplug / manual detection depends
5530 dpll
= DPLL_EXT_BUFFER_ENABLE_VLV
| DPLL_REFA_CLK_ENABLE_VLV
|
5531 DPLL_VGA_MODE_DIS
| DPLL_INTEGRATED_CLOCK_VLV
;
5532 /* We should never disable this, set it here for state tracking */
5533 if (crtc
->pipe
== PIPE_B
)
5534 dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
5535 dpll
|= DPLL_VCO_ENABLE
;
5536 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
5538 dpll_md
= (crtc
->config
.pixel_multiplier
- 1)
5539 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
5540 crtc
->config
.dpll_hw_state
.dpll_md
= dpll_md
;
5543 static void vlv_prepare_pll(struct intel_crtc
*crtc
)
5545 struct drm_device
*dev
= crtc
->base
.dev
;
5546 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5547 int pipe
= crtc
->pipe
;
5549 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
5550 u32 coreclk
, reg_val
;
5552 mutex_lock(&dev_priv
->dpio_lock
);
5554 bestn
= crtc
->config
.dpll
.n
;
5555 bestm1
= crtc
->config
.dpll
.m1
;
5556 bestm2
= crtc
->config
.dpll
.m2
;
5557 bestp1
= crtc
->config
.dpll
.p1
;
5558 bestp2
= crtc
->config
.dpll
.p2
;
5560 /* See eDP HDMI DPIO driver vbios notes doc */
5562 /* PLL B needs special handling */
5564 vlv_pllb_recal_opamp(dev_priv
, pipe
);
5566 /* Set up Tx target for periodic Rcomp update */
5567 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9_BCAST
, 0x0100000f);
5569 /* Disable target IRef on PLL */
5570 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW8(pipe
));
5571 reg_val
&= 0x00ffffff;
5572 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW8(pipe
), reg_val
);
5574 /* Disable fast lock */
5575 vlv_dpio_write(dev_priv
, pipe
, VLV_CMN_DW0
, 0x610);
5577 /* Set idtafcrecal before PLL is enabled */
5578 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
5579 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
5580 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
5581 mdiv
|= (1 << DPIO_K_SHIFT
);
5584 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5585 * but we don't support that).
5586 * Note: don't use the DAC post divider as it seems unstable.
5588 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
5589 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
5591 mdiv
|= DPIO_ENABLE_CALIBRATION
;
5592 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
5594 /* Set HBR and RBR LPF coefficients */
5595 if (crtc
->config
.port_clock
== 162000 ||
5596 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_ANALOG
) ||
5597 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
))
5598 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
5601 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
5604 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
) ||
5605 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
)) {
5606 /* Use SSC source */
5608 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5611 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5613 } else { /* HDMI or VGA */
5614 /* Use bend source */
5616 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5619 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5623 coreclk
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW7(pipe
));
5624 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
5625 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
) ||
5626 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
))
5627 coreclk
|= 0x01000000;
5628 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW7(pipe
), coreclk
);
5630 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW11(pipe
), 0x87871000);
5631 mutex_unlock(&dev_priv
->dpio_lock
);
5634 static void chv_update_pll(struct intel_crtc
*crtc
)
5636 struct drm_device
*dev
= crtc
->base
.dev
;
5637 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5638 int pipe
= crtc
->pipe
;
5639 int dpll_reg
= DPLL(crtc
->pipe
);
5640 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
5641 u32 loopfilter
, intcoeff
;
5642 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
, bestm2_frac
;
5645 crtc
->config
.dpll_hw_state
.dpll
= DPLL_SSC_REF_CLOCK_CHV
|
5646 DPLL_REFA_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
|
5649 crtc
->config
.dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
5651 crtc
->config
.dpll_hw_state
.dpll_md
=
5652 (crtc
->config
.pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
5654 bestn
= crtc
->config
.dpll
.n
;
5655 bestm2_frac
= crtc
->config
.dpll
.m2
& 0x3fffff;
5656 bestm1
= crtc
->config
.dpll
.m1
;
5657 bestm2
= crtc
->config
.dpll
.m2
>> 22;
5658 bestp1
= crtc
->config
.dpll
.p1
;
5659 bestp2
= crtc
->config
.dpll
.p2
;
5662 * Enable Refclk and SSC
5664 I915_WRITE(dpll_reg
,
5665 crtc
->config
.dpll_hw_state
.dpll
& ~DPLL_VCO_ENABLE
);
5667 mutex_lock(&dev_priv
->dpio_lock
);
5669 /* p1 and p2 divider */
5670 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW13(port
),
5671 5 << DPIO_CHV_S1_DIV_SHIFT
|
5672 bestp1
<< DPIO_CHV_P1_DIV_SHIFT
|
5673 bestp2
<< DPIO_CHV_P2_DIV_SHIFT
|
5674 1 << DPIO_CHV_K_DIV_SHIFT
);
5676 /* Feedback post-divider - m2 */
5677 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW0(port
), bestm2
);
5679 /* Feedback refclk divider - n and m1 */
5680 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW1(port
),
5681 DPIO_CHV_M1_DIV_BY_2
|
5682 1 << DPIO_CHV_N_DIV_SHIFT
);
5684 /* M2 fraction division */
5685 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW2(port
), bestm2_frac
);
5687 /* M2 fraction division enable */
5688 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW3(port
),
5689 DPIO_CHV_FRAC_DIV_EN
|
5690 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT
));
5693 refclk
= i9xx_get_refclk(&crtc
->base
, 0);
5694 loopfilter
= 5 << DPIO_CHV_PROP_COEFF_SHIFT
|
5695 2 << DPIO_CHV_GAIN_CTRL_SHIFT
;
5696 if (refclk
== 100000)
5698 else if (refclk
== 38400)
5702 loopfilter
|= intcoeff
<< DPIO_CHV_INT_COEFF_SHIFT
;
5703 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW6(port
), loopfilter
);
5706 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
),
5707 vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
)) |
5710 mutex_unlock(&dev_priv
->dpio_lock
);
5713 static void i9xx_update_pll(struct intel_crtc
*crtc
,
5714 intel_clock_t
*reduced_clock
,
5717 struct drm_device
*dev
= crtc
->base
.dev
;
5718 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5721 struct dpll
*clock
= &crtc
->config
.dpll
;
5723 i9xx_update_pll_dividers(crtc
, reduced_clock
);
5725 is_sdvo
= intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_SDVO
) ||
5726 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
);
5728 dpll
= DPLL_VGA_MODE_DIS
;
5730 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
))
5731 dpll
|= DPLLB_MODE_LVDS
;
5733 dpll
|= DPLLB_MODE_DAC_SERIAL
;
5735 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
5736 dpll
|= (crtc
->config
.pixel_multiplier
- 1)
5737 << SDVO_MULTIPLIER_SHIFT_HIRES
;
5741 dpll
|= DPLL_SDVO_HIGH_SPEED
;
5743 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
))
5744 dpll
|= DPLL_SDVO_HIGH_SPEED
;
5746 /* compute bitmask from p1 value */
5747 if (IS_PINEVIEW(dev
))
5748 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
5750 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5751 if (IS_G4X(dev
) && reduced_clock
)
5752 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
5754 switch (clock
->p2
) {
5756 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
5759 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
5762 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
5765 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
5768 if (INTEL_INFO(dev
)->gen
>= 4)
5769 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
5771 if (crtc
->config
.sdvo_tv_clock
)
5772 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
5773 else if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
5774 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
5775 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
5777 dpll
|= PLL_REF_INPUT_DREFCLK
;
5779 dpll
|= DPLL_VCO_ENABLE
;
5780 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
5782 if (INTEL_INFO(dev
)->gen
>= 4) {
5783 u32 dpll_md
= (crtc
->config
.pixel_multiplier
- 1)
5784 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
5785 crtc
->config
.dpll_hw_state
.dpll_md
= dpll_md
;
5789 static void i8xx_update_pll(struct intel_crtc
*crtc
,
5790 intel_clock_t
*reduced_clock
,
5793 struct drm_device
*dev
= crtc
->base
.dev
;
5794 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5796 struct dpll
*clock
= &crtc
->config
.dpll
;
5798 i9xx_update_pll_dividers(crtc
, reduced_clock
);
5800 dpll
= DPLL_VGA_MODE_DIS
;
5802 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
)) {
5803 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5806 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
5808 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5810 dpll
|= PLL_P2_DIVIDE_BY_4
;
5813 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DVO
))
5814 dpll
|= DPLL_DVO_2X_MODE
;
5816 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
5817 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
5818 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
5820 dpll
|= PLL_REF_INPUT_DREFCLK
;
5822 dpll
|= DPLL_VCO_ENABLE
;
5823 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
5826 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
5828 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5829 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5830 enum pipe pipe
= intel_crtc
->pipe
;
5831 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
5832 struct drm_display_mode
*adjusted_mode
=
5833 &intel_crtc
->config
.adjusted_mode
;
5834 uint32_t crtc_vtotal
, crtc_vblank_end
;
5837 /* We need to be careful not to changed the adjusted mode, for otherwise
5838 * the hw state checker will get angry at the mismatch. */
5839 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
5840 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
5842 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
5843 /* the chip adds 2 halflines automatically */
5845 crtc_vblank_end
-= 1;
5847 if (intel_pipe_has_type(&intel_crtc
->base
, INTEL_OUTPUT_SDVO
))
5848 vsyncshift
= (adjusted_mode
->crtc_htotal
- 1) / 2;
5850 vsyncshift
= adjusted_mode
->crtc_hsync_start
-
5851 adjusted_mode
->crtc_htotal
/ 2;
5853 vsyncshift
+= adjusted_mode
->crtc_htotal
;
5856 if (INTEL_INFO(dev
)->gen
> 3)
5857 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
5859 I915_WRITE(HTOTAL(cpu_transcoder
),
5860 (adjusted_mode
->crtc_hdisplay
- 1) |
5861 ((adjusted_mode
->crtc_htotal
- 1) << 16));
5862 I915_WRITE(HBLANK(cpu_transcoder
),
5863 (adjusted_mode
->crtc_hblank_start
- 1) |
5864 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
5865 I915_WRITE(HSYNC(cpu_transcoder
),
5866 (adjusted_mode
->crtc_hsync_start
- 1) |
5867 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
5869 I915_WRITE(VTOTAL(cpu_transcoder
),
5870 (adjusted_mode
->crtc_vdisplay
- 1) |
5871 ((crtc_vtotal
- 1) << 16));
5872 I915_WRITE(VBLANK(cpu_transcoder
),
5873 (adjusted_mode
->crtc_vblank_start
- 1) |
5874 ((crtc_vblank_end
- 1) << 16));
5875 I915_WRITE(VSYNC(cpu_transcoder
),
5876 (adjusted_mode
->crtc_vsync_start
- 1) |
5877 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
5879 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5880 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5881 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5883 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
5884 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
5885 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
5887 /* pipesrc controls the size that is scaled from, which should
5888 * always be the user's requested size.
5890 I915_WRITE(PIPESRC(pipe
),
5891 ((intel_crtc
->config
.pipe_src_w
- 1) << 16) |
5892 (intel_crtc
->config
.pipe_src_h
- 1));
5895 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
5896 struct intel_crtc_config
*pipe_config
)
5898 struct drm_device
*dev
= crtc
->base
.dev
;
5899 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5900 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
5903 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
5904 pipe_config
->adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
5905 pipe_config
->adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
5906 tmp
= I915_READ(HBLANK(cpu_transcoder
));
5907 pipe_config
->adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
5908 pipe_config
->adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
5909 tmp
= I915_READ(HSYNC(cpu_transcoder
));
5910 pipe_config
->adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
5911 pipe_config
->adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
5913 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
5914 pipe_config
->adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
5915 pipe_config
->adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
5916 tmp
= I915_READ(VBLANK(cpu_transcoder
));
5917 pipe_config
->adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
5918 pipe_config
->adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
5919 tmp
= I915_READ(VSYNC(cpu_transcoder
));
5920 pipe_config
->adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
5921 pipe_config
->adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
5923 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
5924 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
5925 pipe_config
->adjusted_mode
.crtc_vtotal
+= 1;
5926 pipe_config
->adjusted_mode
.crtc_vblank_end
+= 1;
5929 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
5930 pipe_config
->pipe_src_h
= (tmp
& 0xffff) + 1;
5931 pipe_config
->pipe_src_w
= ((tmp
>> 16) & 0xffff) + 1;
5933 pipe_config
->requested_mode
.vdisplay
= pipe_config
->pipe_src_h
;
5934 pipe_config
->requested_mode
.hdisplay
= pipe_config
->pipe_src_w
;
5937 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
5938 struct intel_crtc_config
*pipe_config
)
5940 mode
->hdisplay
= pipe_config
->adjusted_mode
.crtc_hdisplay
;
5941 mode
->htotal
= pipe_config
->adjusted_mode
.crtc_htotal
;
5942 mode
->hsync_start
= pipe_config
->adjusted_mode
.crtc_hsync_start
;
5943 mode
->hsync_end
= pipe_config
->adjusted_mode
.crtc_hsync_end
;
5945 mode
->vdisplay
= pipe_config
->adjusted_mode
.crtc_vdisplay
;
5946 mode
->vtotal
= pipe_config
->adjusted_mode
.crtc_vtotal
;
5947 mode
->vsync_start
= pipe_config
->adjusted_mode
.crtc_vsync_start
;
5948 mode
->vsync_end
= pipe_config
->adjusted_mode
.crtc_vsync_end
;
5950 mode
->flags
= pipe_config
->adjusted_mode
.flags
;
5952 mode
->clock
= pipe_config
->adjusted_mode
.crtc_clock
;
5953 mode
->flags
|= pipe_config
->adjusted_mode
.flags
;
5956 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
5958 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5959 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5964 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
5965 I915_READ(PIPECONF(intel_crtc
->pipe
)) & PIPECONF_ENABLE
)
5966 pipeconf
|= PIPECONF_ENABLE
;
5968 if (intel_crtc
->config
.double_wide
)
5969 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
5971 /* only g4x and later have fancy bpc/dither controls */
5972 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
5973 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5974 if (intel_crtc
->config
.dither
&& intel_crtc
->config
.pipe_bpp
!= 30)
5975 pipeconf
|= PIPECONF_DITHER_EN
|
5976 PIPECONF_DITHER_TYPE_SP
;
5978 switch (intel_crtc
->config
.pipe_bpp
) {
5980 pipeconf
|= PIPECONF_6BPC
;
5983 pipeconf
|= PIPECONF_8BPC
;
5986 pipeconf
|= PIPECONF_10BPC
;
5989 /* Case prevented by intel_choose_pipe_bpp_dither. */
5994 if (HAS_PIPE_CXSR(dev
)) {
5995 if (intel_crtc
->lowfreq_avail
) {
5996 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5997 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
5999 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6003 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
6004 if (INTEL_INFO(dev
)->gen
< 4 ||
6005 intel_pipe_has_type(&intel_crtc
->base
, INTEL_OUTPUT_SDVO
))
6006 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
6008 pipeconf
|= PIPECONF_INTERLACE_W_SYNC_SHIFT
;
6010 pipeconf
|= PIPECONF_PROGRESSIVE
;
6012 if (IS_VALLEYVIEW(dev
) && intel_crtc
->config
.limited_color_range
)
6013 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
6015 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
6016 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
6019 static int i9xx_crtc_mode_set(struct drm_crtc
*crtc
,
6021 struct drm_framebuffer
*fb
)
6023 struct drm_device
*dev
= crtc
->dev
;
6024 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6025 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6026 int refclk
, num_connectors
= 0;
6027 intel_clock_t clock
, reduced_clock
;
6028 bool ok
, has_reduced_clock
= false;
6029 bool is_lvds
= false, is_dsi
= false;
6030 struct intel_encoder
*encoder
;
6031 const intel_limit_t
*limit
;
6033 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
6034 switch (encoder
->type
) {
6035 case INTEL_OUTPUT_LVDS
:
6038 case INTEL_OUTPUT_DSI
:
6049 if (!intel_crtc
->config
.clock_set
) {
6050 refclk
= i9xx_get_refclk(crtc
, num_connectors
);
6053 * Returns a set of divisors for the desired target clock with
6054 * the given refclk, or FALSE. The returned values represent
6055 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6058 limit
= intel_limit(crtc
, refclk
);
6059 ok
= dev_priv
->display
.find_dpll(limit
, crtc
,
6060 intel_crtc
->config
.port_clock
,
6061 refclk
, NULL
, &clock
);
6063 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6067 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
6069 * Ensure we match the reduced clock's P to the target
6070 * clock. If the clocks don't match, we can't switch
6071 * the display clock by using the FP0/FP1. In such case
6072 * we will disable the LVDS downclock feature.
6075 dev_priv
->display
.find_dpll(limit
, crtc
,
6076 dev_priv
->lvds_downclock
,
6080 /* Compat-code for transition, will disappear. */
6081 intel_crtc
->config
.dpll
.n
= clock
.n
;
6082 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
6083 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
6084 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
6085 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
6089 i8xx_update_pll(intel_crtc
,
6090 has_reduced_clock
? &reduced_clock
: NULL
,
6092 } else if (IS_CHERRYVIEW(dev
)) {
6093 chv_update_pll(intel_crtc
);
6094 } else if (IS_VALLEYVIEW(dev
)) {
6095 vlv_update_pll(intel_crtc
);
6097 i9xx_update_pll(intel_crtc
,
6098 has_reduced_clock
? &reduced_clock
: NULL
,
6105 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
6106 struct intel_crtc_config
*pipe_config
)
6108 struct drm_device
*dev
= crtc
->base
.dev
;
6109 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6112 if (INTEL_INFO(dev
)->gen
<= 3 && (IS_I830(dev
) || !IS_MOBILE(dev
)))
6115 tmp
= I915_READ(PFIT_CONTROL
);
6116 if (!(tmp
& PFIT_ENABLE
))
6119 /* Check whether the pfit is attached to our pipe. */
6120 if (INTEL_INFO(dev
)->gen
< 4) {
6121 if (crtc
->pipe
!= PIPE_B
)
6124 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
6128 pipe_config
->gmch_pfit
.control
= tmp
;
6129 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
6130 if (INTEL_INFO(dev
)->gen
< 5)
6131 pipe_config
->gmch_pfit
.lvds_border_bits
=
6132 I915_READ(LVDS
) & LVDS_BORDER_ENABLE
;
6135 static void vlv_crtc_clock_get(struct intel_crtc
*crtc
,
6136 struct intel_crtc_config
*pipe_config
)
6138 struct drm_device
*dev
= crtc
->base
.dev
;
6139 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6140 int pipe
= pipe_config
->cpu_transcoder
;
6141 intel_clock_t clock
;
6143 int refclk
= 100000;
6145 mutex_lock(&dev_priv
->dpio_lock
);
6146 mdiv
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW3(pipe
));
6147 mutex_unlock(&dev_priv
->dpio_lock
);
6149 clock
.m1
= (mdiv
>> DPIO_M1DIV_SHIFT
) & 7;
6150 clock
.m2
= mdiv
& DPIO_M2DIV_MASK
;
6151 clock
.n
= (mdiv
>> DPIO_N_SHIFT
) & 0xf;
6152 clock
.p1
= (mdiv
>> DPIO_P1_SHIFT
) & 7;
6153 clock
.p2
= (mdiv
>> DPIO_P2_SHIFT
) & 0x1f;
6155 vlv_clock(refclk
, &clock
);
6157 /* clock.dot is the fast clock */
6158 pipe_config
->port_clock
= clock
.dot
/ 5;
6161 static void i9xx_get_plane_config(struct intel_crtc
*crtc
,
6162 struct intel_plane_config
*plane_config
)
6164 struct drm_device
*dev
= crtc
->base
.dev
;
6165 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6166 u32 val
, base
, offset
;
6167 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
6168 int fourcc
, pixel_format
;
6171 crtc
->base
.primary
->fb
= kzalloc(sizeof(struct intel_framebuffer
), GFP_KERNEL
);
6172 if (!crtc
->base
.primary
->fb
) {
6173 DRM_DEBUG_KMS("failed to alloc fb\n");
6177 val
= I915_READ(DSPCNTR(plane
));
6179 if (INTEL_INFO(dev
)->gen
>= 4)
6180 if (val
& DISPPLANE_TILED
)
6181 plane_config
->tiled
= true;
6183 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
6184 fourcc
= intel_format_to_fourcc(pixel_format
);
6185 crtc
->base
.primary
->fb
->pixel_format
= fourcc
;
6186 crtc
->base
.primary
->fb
->bits_per_pixel
=
6187 drm_format_plane_cpp(fourcc
, 0) * 8;
6189 if (INTEL_INFO(dev
)->gen
>= 4) {
6190 if (plane_config
->tiled
)
6191 offset
= I915_READ(DSPTILEOFF(plane
));
6193 offset
= I915_READ(DSPLINOFF(plane
));
6194 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
6196 base
= I915_READ(DSPADDR(plane
));
6198 plane_config
->base
= base
;
6200 val
= I915_READ(PIPESRC(pipe
));
6201 crtc
->base
.primary
->fb
->width
= ((val
>> 16) & 0xfff) + 1;
6202 crtc
->base
.primary
->fb
->height
= ((val
>> 0) & 0xfff) + 1;
6204 val
= I915_READ(DSPSTRIDE(pipe
));
6205 crtc
->base
.primary
->fb
->pitches
[0] = val
& 0xffffff80;
6207 aligned_height
= intel_align_height(dev
, crtc
->base
.primary
->fb
->height
,
6208 plane_config
->tiled
);
6210 plane_config
->size
= PAGE_ALIGN(crtc
->base
.primary
->fb
->pitches
[0] *
6213 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6214 pipe
, plane
, crtc
->base
.primary
->fb
->width
,
6215 crtc
->base
.primary
->fb
->height
,
6216 crtc
->base
.primary
->fb
->bits_per_pixel
, base
,
6217 crtc
->base
.primary
->fb
->pitches
[0],
6218 plane_config
->size
);
6222 static void chv_crtc_clock_get(struct intel_crtc
*crtc
,
6223 struct intel_crtc_config
*pipe_config
)
6225 struct drm_device
*dev
= crtc
->base
.dev
;
6226 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6227 int pipe
= pipe_config
->cpu_transcoder
;
6228 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
6229 intel_clock_t clock
;
6230 u32 cmn_dw13
, pll_dw0
, pll_dw1
, pll_dw2
;
6231 int refclk
= 100000;
6233 mutex_lock(&dev_priv
->dpio_lock
);
6234 cmn_dw13
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW13(port
));
6235 pll_dw0
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW0(port
));
6236 pll_dw1
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW1(port
));
6237 pll_dw2
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW2(port
));
6238 mutex_unlock(&dev_priv
->dpio_lock
);
6240 clock
.m1
= (pll_dw1
& 0x7) == DPIO_CHV_M1_DIV_BY_2
? 2 : 0;
6241 clock
.m2
= ((pll_dw0
& 0xff) << 22) | (pll_dw2
& 0x3fffff);
6242 clock
.n
= (pll_dw1
>> DPIO_CHV_N_DIV_SHIFT
) & 0xf;
6243 clock
.p1
= (cmn_dw13
>> DPIO_CHV_P1_DIV_SHIFT
) & 0x7;
6244 clock
.p2
= (cmn_dw13
>> DPIO_CHV_P2_DIV_SHIFT
) & 0x1f;
6246 chv_clock(refclk
, &clock
);
6248 /* clock.dot is the fast clock */
6249 pipe_config
->port_clock
= clock
.dot
/ 5;
6252 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
6253 struct intel_crtc_config
*pipe_config
)
6255 struct drm_device
*dev
= crtc
->base
.dev
;
6256 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6259 if (!intel_display_power_enabled(dev_priv
,
6260 POWER_DOMAIN_PIPE(crtc
->pipe
)))
6263 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
6264 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
6266 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
6267 if (!(tmp
& PIPECONF_ENABLE
))
6270 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
6271 switch (tmp
& PIPECONF_BPC_MASK
) {
6273 pipe_config
->pipe_bpp
= 18;
6276 pipe_config
->pipe_bpp
= 24;
6278 case PIPECONF_10BPC
:
6279 pipe_config
->pipe_bpp
= 30;
6286 if (IS_VALLEYVIEW(dev
) && (tmp
& PIPECONF_COLOR_RANGE_SELECT
))
6287 pipe_config
->limited_color_range
= true;
6289 if (INTEL_INFO(dev
)->gen
< 4)
6290 pipe_config
->double_wide
= tmp
& PIPECONF_DOUBLE_WIDE
;
6292 intel_get_pipe_timings(crtc
, pipe_config
);
6294 i9xx_get_pfit_config(crtc
, pipe_config
);
6296 if (INTEL_INFO(dev
)->gen
>= 4) {
6297 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
6298 pipe_config
->pixel_multiplier
=
6299 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
6300 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
6301 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
6302 } else if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
6303 tmp
= I915_READ(DPLL(crtc
->pipe
));
6304 pipe_config
->pixel_multiplier
=
6305 ((tmp
& SDVO_MULTIPLIER_MASK
)
6306 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
6308 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6309 * port and will be fixed up in the encoder->get_config
6311 pipe_config
->pixel_multiplier
= 1;
6313 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
6314 if (!IS_VALLEYVIEW(dev
)) {
6315 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
6316 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
6318 /* Mask out read-only status bits. */
6319 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
6320 DPLL_PORTC_READY_MASK
|
6321 DPLL_PORTB_READY_MASK
);
6324 if (IS_CHERRYVIEW(dev
))
6325 chv_crtc_clock_get(crtc
, pipe_config
);
6326 else if (IS_VALLEYVIEW(dev
))
6327 vlv_crtc_clock_get(crtc
, pipe_config
);
6329 i9xx_crtc_clock_get(crtc
, pipe_config
);
6334 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
6336 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6337 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
6338 struct intel_encoder
*encoder
;
6340 bool has_lvds
= false;
6341 bool has_cpu_edp
= false;
6342 bool has_panel
= false;
6343 bool has_ck505
= false;
6344 bool can_ssc
= false;
6346 /* We need to take the global config into account */
6347 list_for_each_entry(encoder
, &mode_config
->encoder_list
,
6349 switch (encoder
->type
) {
6350 case INTEL_OUTPUT_LVDS
:
6354 case INTEL_OUTPUT_EDP
:
6356 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
6362 if (HAS_PCH_IBX(dev
)) {
6363 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
6364 can_ssc
= has_ck505
;
6370 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6371 has_panel
, has_lvds
, has_ck505
);
6373 /* Ironlake: try to setup display ref clock before DPLL
6374 * enabling. This is only under driver's control after
6375 * PCH B stepping, previous chipset stepping should be
6376 * ignoring this setting.
6378 val
= I915_READ(PCH_DREF_CONTROL
);
6380 /* As we must carefully and slowly disable/enable each source in turn,
6381 * compute the final state we want first and check if we need to
6382 * make any changes at all.
6385 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
6387 final
|= DREF_NONSPREAD_CK505_ENABLE
;
6389 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
6391 final
&= ~DREF_SSC_SOURCE_MASK
;
6392 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
6393 final
&= ~DREF_SSC1_ENABLE
;
6396 final
|= DREF_SSC_SOURCE_ENABLE
;
6398 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
6399 final
|= DREF_SSC1_ENABLE
;
6402 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
6403 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
6405 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
6407 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6409 final
|= DREF_SSC_SOURCE_DISABLE
;
6410 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6416 /* Always enable nonspread source */
6417 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
6420 val
|= DREF_NONSPREAD_CK505_ENABLE
;
6422 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
6425 val
&= ~DREF_SSC_SOURCE_MASK
;
6426 val
|= DREF_SSC_SOURCE_ENABLE
;
6428 /* SSC must be turned on before enabling the CPU output */
6429 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
6430 DRM_DEBUG_KMS("Using SSC on panel\n");
6431 val
|= DREF_SSC1_ENABLE
;
6433 val
&= ~DREF_SSC1_ENABLE
;
6435 /* Get SSC going before enabling the outputs */
6436 I915_WRITE(PCH_DREF_CONTROL
, val
);
6437 POSTING_READ(PCH_DREF_CONTROL
);
6440 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
6442 /* Enable CPU source on CPU attached eDP */
6444 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
6445 DRM_DEBUG_KMS("Using SSC on eDP\n");
6446 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
6448 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
6450 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6452 I915_WRITE(PCH_DREF_CONTROL
, val
);
6453 POSTING_READ(PCH_DREF_CONTROL
);
6456 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6458 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
6460 /* Turn off CPU output */
6461 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6463 I915_WRITE(PCH_DREF_CONTROL
, val
);
6464 POSTING_READ(PCH_DREF_CONTROL
);
6467 /* Turn off the SSC source */
6468 val
&= ~DREF_SSC_SOURCE_MASK
;
6469 val
|= DREF_SSC_SOURCE_DISABLE
;
6472 val
&= ~DREF_SSC1_ENABLE
;
6474 I915_WRITE(PCH_DREF_CONTROL
, val
);
6475 POSTING_READ(PCH_DREF_CONTROL
);
6479 BUG_ON(val
!= final
);
6482 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
6486 tmp
= I915_READ(SOUTH_CHICKEN2
);
6487 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
6488 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
6490 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
6491 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
6492 DRM_ERROR("FDI mPHY reset assert timeout\n");
6494 tmp
= I915_READ(SOUTH_CHICKEN2
);
6495 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
6496 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
6498 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
6499 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
6500 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6503 /* WaMPhyProgramming:hsw */
6504 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
6508 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
6509 tmp
&= ~(0xFF << 24);
6510 tmp
|= (0x12 << 24);
6511 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
6513 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
6515 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
6517 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
6519 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
6521 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
6522 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
6523 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
6525 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
6526 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
6527 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
6529 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
6532 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
6534 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
6537 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
6539 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
6542 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
6544 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
6547 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
6549 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
6550 tmp
&= ~(0xFF << 16);
6551 tmp
|= (0x1C << 16);
6552 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
6554 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
6555 tmp
&= ~(0xFF << 16);
6556 tmp
|= (0x1C << 16);
6557 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
6559 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
6561 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
6563 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
6565 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
6567 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
6568 tmp
&= ~(0xF << 28);
6570 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
6572 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
6573 tmp
&= ~(0xF << 28);
6575 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
6578 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6579 * Programming" based on the parameters passed:
6580 * - Sequence to enable CLKOUT_DP
6581 * - Sequence to enable CLKOUT_DP without spread
6582 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6584 static void lpt_enable_clkout_dp(struct drm_device
*dev
, bool with_spread
,
6587 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6590 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
6592 if (WARN(dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
&&
6593 with_fdi
, "LP PCH doesn't have FDI\n"))
6596 mutex_lock(&dev_priv
->dpio_lock
);
6598 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
6599 tmp
&= ~SBI_SSCCTL_DISABLE
;
6600 tmp
|= SBI_SSCCTL_PATHALT
;
6601 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
6606 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
6607 tmp
&= ~SBI_SSCCTL_PATHALT
;
6608 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
6611 lpt_reset_fdi_mphy(dev_priv
);
6612 lpt_program_fdi_mphy(dev_priv
);
6616 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
6617 SBI_GEN0
: SBI_DBUFF0
;
6618 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
6619 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
6620 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
6622 mutex_unlock(&dev_priv
->dpio_lock
);
6625 /* Sequence to disable CLKOUT_DP */
6626 static void lpt_disable_clkout_dp(struct drm_device
*dev
)
6628 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6631 mutex_lock(&dev_priv
->dpio_lock
);
6633 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
6634 SBI_GEN0
: SBI_DBUFF0
;
6635 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
6636 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
6637 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
6639 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
6640 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
6641 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
6642 tmp
|= SBI_SSCCTL_PATHALT
;
6643 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
6646 tmp
|= SBI_SSCCTL_DISABLE
;
6647 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
6650 mutex_unlock(&dev_priv
->dpio_lock
);
6653 static void lpt_init_pch_refclk(struct drm_device
*dev
)
6655 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
6656 struct intel_encoder
*encoder
;
6657 bool has_vga
= false;
6659 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
) {
6660 switch (encoder
->type
) {
6661 case INTEL_OUTPUT_ANALOG
:
6668 lpt_enable_clkout_dp(dev
, true, true);
6670 lpt_disable_clkout_dp(dev
);
6674 * Initialize reference clocks when the driver loads
6676 void intel_init_pch_refclk(struct drm_device
*dev
)
6678 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
6679 ironlake_init_pch_refclk(dev
);
6680 else if (HAS_PCH_LPT(dev
))
6681 lpt_init_pch_refclk(dev
);
6684 static int ironlake_get_refclk(struct drm_crtc
*crtc
)
6686 struct drm_device
*dev
= crtc
->dev
;
6687 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6688 struct intel_encoder
*encoder
;
6689 int num_connectors
= 0;
6690 bool is_lvds
= false;
6692 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
6693 switch (encoder
->type
) {
6694 case INTEL_OUTPUT_LVDS
:
6701 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
6702 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6703 dev_priv
->vbt
.lvds_ssc_freq
);
6704 return dev_priv
->vbt
.lvds_ssc_freq
;
6710 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
6712 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
6713 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6714 int pipe
= intel_crtc
->pipe
;
6719 switch (intel_crtc
->config
.pipe_bpp
) {
6721 val
|= PIPECONF_6BPC
;
6724 val
|= PIPECONF_8BPC
;
6727 val
|= PIPECONF_10BPC
;
6730 val
|= PIPECONF_12BPC
;
6733 /* Case prevented by intel_choose_pipe_bpp_dither. */
6737 if (intel_crtc
->config
.dither
)
6738 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
6740 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
6741 val
|= PIPECONF_INTERLACED_ILK
;
6743 val
|= PIPECONF_PROGRESSIVE
;
6745 if (intel_crtc
->config
.limited_color_range
)
6746 val
|= PIPECONF_COLOR_RANGE_SELECT
;
6748 I915_WRITE(PIPECONF(pipe
), val
);
6749 POSTING_READ(PIPECONF(pipe
));
6753 * Set up the pipe CSC unit.
6755 * Currently only full range RGB to limited range RGB conversion
6756 * is supported, but eventually this should handle various
6757 * RGB<->YCbCr scenarios as well.
6759 static void intel_set_pipe_csc(struct drm_crtc
*crtc
)
6761 struct drm_device
*dev
= crtc
->dev
;
6762 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6763 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6764 int pipe
= intel_crtc
->pipe
;
6765 uint16_t coeff
= 0x7800; /* 1.0 */
6768 * TODO: Check what kind of values actually come out of the pipe
6769 * with these coeff/postoff values and adjust to get the best
6770 * accuracy. Perhaps we even need to take the bpc value into
6774 if (intel_crtc
->config
.limited_color_range
)
6775 coeff
= ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6778 * GY/GU and RY/RU should be the other way around according
6779 * to BSpec, but reality doesn't agree. Just set them up in
6780 * a way that results in the correct picture.
6782 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeff
<< 16);
6783 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), 0);
6785 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeff
);
6786 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), 0);
6788 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), 0);
6789 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeff
<< 16);
6791 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
6792 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
6793 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
6795 if (INTEL_INFO(dev
)->gen
> 6) {
6796 uint16_t postoff
= 0;
6798 if (intel_crtc
->config
.limited_color_range
)
6799 postoff
= (16 * (1 << 12) / 255) & 0x1fff;
6801 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
6802 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
6803 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
6805 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
6807 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
6809 if (intel_crtc
->config
.limited_color_range
)
6810 mode
|= CSC_BLACK_SCREEN_OFFSET
;
6812 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
6816 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
6818 struct drm_device
*dev
= crtc
->dev
;
6819 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6820 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6821 enum pipe pipe
= intel_crtc
->pipe
;
6822 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
6827 if (IS_HASWELL(dev
) && intel_crtc
->config
.dither
)
6828 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
6830 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
6831 val
|= PIPECONF_INTERLACED_ILK
;
6833 val
|= PIPECONF_PROGRESSIVE
;
6835 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
6836 POSTING_READ(PIPECONF(cpu_transcoder
));
6838 I915_WRITE(GAMMA_MODE(intel_crtc
->pipe
), GAMMA_MODE_MODE_8BIT
);
6839 POSTING_READ(GAMMA_MODE(intel_crtc
->pipe
));
6841 if (IS_BROADWELL(dev
)) {
6844 switch (intel_crtc
->config
.pipe_bpp
) {
6846 val
|= PIPEMISC_DITHER_6_BPC
;
6849 val
|= PIPEMISC_DITHER_8_BPC
;
6852 val
|= PIPEMISC_DITHER_10_BPC
;
6855 val
|= PIPEMISC_DITHER_12_BPC
;
6858 /* Case prevented by pipe_config_set_bpp. */
6862 if (intel_crtc
->config
.dither
)
6863 val
|= PIPEMISC_DITHER_ENABLE
| PIPEMISC_DITHER_TYPE_SP
;
6865 I915_WRITE(PIPEMISC(pipe
), val
);
6869 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
6870 intel_clock_t
*clock
,
6871 bool *has_reduced_clock
,
6872 intel_clock_t
*reduced_clock
)
6874 struct drm_device
*dev
= crtc
->dev
;
6875 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6876 struct intel_encoder
*intel_encoder
;
6878 const intel_limit_t
*limit
;
6879 bool ret
, is_lvds
= false;
6881 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
6882 switch (intel_encoder
->type
) {
6883 case INTEL_OUTPUT_LVDS
:
6889 refclk
= ironlake_get_refclk(crtc
);
6892 * Returns a set of divisors for the desired target clock with the given
6893 * refclk, or FALSE. The returned values represent the clock equation:
6894 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6896 limit
= intel_limit(crtc
, refclk
);
6897 ret
= dev_priv
->display
.find_dpll(limit
, crtc
,
6898 to_intel_crtc(crtc
)->config
.port_clock
,
6899 refclk
, NULL
, clock
);
6903 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
6905 * Ensure we match the reduced clock's P to the target clock.
6906 * If the clocks don't match, we can't switch the display clock
6907 * by using the FP0/FP1. In such case we will disable the LVDS
6908 * downclock feature.
6910 *has_reduced_clock
=
6911 dev_priv
->display
.find_dpll(limit
, crtc
,
6912 dev_priv
->lvds_downclock
,
6920 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
6923 * Account for spread spectrum to avoid
6924 * oversubscribing the link. Max center spread
6925 * is 2.5%; use 5% for safety's sake.
6927 u32 bps
= target_clock
* bpp
* 21 / 20;
6928 return DIV_ROUND_UP(bps
, link_bw
* 8);
6931 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
6933 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
6936 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
6938 intel_clock_t
*reduced_clock
, u32
*fp2
)
6940 struct drm_crtc
*crtc
= &intel_crtc
->base
;
6941 struct drm_device
*dev
= crtc
->dev
;
6942 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6943 struct intel_encoder
*intel_encoder
;
6945 int factor
, num_connectors
= 0;
6946 bool is_lvds
= false, is_sdvo
= false;
6948 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
6949 switch (intel_encoder
->type
) {
6950 case INTEL_OUTPUT_LVDS
:
6953 case INTEL_OUTPUT_SDVO
:
6954 case INTEL_OUTPUT_HDMI
:
6962 /* Enable autotuning of the PLL clock (if permissible) */
6965 if ((intel_panel_use_ssc(dev_priv
) &&
6966 dev_priv
->vbt
.lvds_ssc_freq
== 100000) ||
6967 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
6969 } else if (intel_crtc
->config
.sdvo_tv_clock
)
6972 if (ironlake_needs_fb_cb_tune(&intel_crtc
->config
.dpll
, factor
))
6975 if (fp2
&& (reduced_clock
->m
< factor
* reduced_clock
->n
))
6981 dpll
|= DPLLB_MODE_LVDS
;
6983 dpll
|= DPLLB_MODE_DAC_SERIAL
;
6985 dpll
|= (intel_crtc
->config
.pixel_multiplier
- 1)
6986 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
6989 dpll
|= DPLL_SDVO_HIGH_SPEED
;
6990 if (intel_crtc
->config
.has_dp_encoder
)
6991 dpll
|= DPLL_SDVO_HIGH_SPEED
;
6993 /* compute bitmask from p1 value */
6994 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
6996 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
6998 switch (intel_crtc
->config
.dpll
.p2
) {
7000 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
7003 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
7006 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
7009 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
7013 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
7014 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7016 dpll
|= PLL_REF_INPUT_DREFCLK
;
7018 return dpll
| DPLL_VCO_ENABLE
;
7021 static int ironlake_crtc_mode_set(struct drm_crtc
*crtc
,
7023 struct drm_framebuffer
*fb
)
7025 struct drm_device
*dev
= crtc
->dev
;
7026 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7027 int num_connectors
= 0;
7028 intel_clock_t clock
, reduced_clock
;
7029 u32 dpll
= 0, fp
= 0, fp2
= 0;
7030 bool ok
, has_reduced_clock
= false;
7031 bool is_lvds
= false;
7032 struct intel_encoder
*encoder
;
7033 struct intel_shared_dpll
*pll
;
7035 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
7036 switch (encoder
->type
) {
7037 case INTEL_OUTPUT_LVDS
:
7045 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
7046 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
7048 ok
= ironlake_compute_clocks(crtc
, &clock
,
7049 &has_reduced_clock
, &reduced_clock
);
7050 if (!ok
&& !intel_crtc
->config
.clock_set
) {
7051 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7054 /* Compat-code for transition, will disappear. */
7055 if (!intel_crtc
->config
.clock_set
) {
7056 intel_crtc
->config
.dpll
.n
= clock
.n
;
7057 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
7058 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
7059 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
7060 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
7063 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7064 if (intel_crtc
->config
.has_pch_encoder
) {
7065 fp
= i9xx_dpll_compute_fp(&intel_crtc
->config
.dpll
);
7066 if (has_reduced_clock
)
7067 fp2
= i9xx_dpll_compute_fp(&reduced_clock
);
7069 dpll
= ironlake_compute_dpll(intel_crtc
,
7070 &fp
, &reduced_clock
,
7071 has_reduced_clock
? &fp2
: NULL
);
7073 intel_crtc
->config
.dpll_hw_state
.dpll
= dpll
;
7074 intel_crtc
->config
.dpll_hw_state
.fp0
= fp
;
7075 if (has_reduced_clock
)
7076 intel_crtc
->config
.dpll_hw_state
.fp1
= fp2
;
7078 intel_crtc
->config
.dpll_hw_state
.fp1
= fp
;
7080 pll
= intel_get_shared_dpll(intel_crtc
);
7082 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7083 pipe_name(intel_crtc
->pipe
));
7087 intel_put_shared_dpll(intel_crtc
);
7089 if (is_lvds
&& has_reduced_clock
&& i915
.powersave
)
7090 intel_crtc
->lowfreq_avail
= true;
7092 intel_crtc
->lowfreq_avail
= false;
7097 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
7098 struct intel_link_m_n
*m_n
)
7100 struct drm_device
*dev
= crtc
->base
.dev
;
7101 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7102 enum pipe pipe
= crtc
->pipe
;
7104 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
7105 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
7106 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
7108 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
7109 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
7110 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7113 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
7114 enum transcoder transcoder
,
7115 struct intel_link_m_n
*m_n
)
7117 struct drm_device
*dev
= crtc
->base
.dev
;
7118 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7119 enum pipe pipe
= crtc
->pipe
;
7121 if (INTEL_INFO(dev
)->gen
>= 5) {
7122 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
7123 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
7124 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
7126 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
7127 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
7128 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7130 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
7131 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
7132 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
7134 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
7135 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
7136 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7140 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
7141 struct intel_crtc_config
*pipe_config
)
7143 if (crtc
->config
.has_pch_encoder
)
7144 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
7146 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
7147 &pipe_config
->dp_m_n
);
7150 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
7151 struct intel_crtc_config
*pipe_config
)
7153 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
7154 &pipe_config
->fdi_m_n
);
7157 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
7158 struct intel_crtc_config
*pipe_config
)
7160 struct drm_device
*dev
= crtc
->base
.dev
;
7161 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7164 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
7166 if (tmp
& PF_ENABLE
) {
7167 pipe_config
->pch_pfit
.enabled
= true;
7168 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
7169 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
7171 /* We currently do not free assignements of panel fitters on
7172 * ivb/hsw (since we don't use the higher upscaling modes which
7173 * differentiates them) so just WARN about this case for now. */
7175 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
7176 PF_PIPE_SEL_IVB(crtc
->pipe
));
7181 static void ironlake_get_plane_config(struct intel_crtc
*crtc
,
7182 struct intel_plane_config
*plane_config
)
7184 struct drm_device
*dev
= crtc
->base
.dev
;
7185 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7186 u32 val
, base
, offset
;
7187 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
7188 int fourcc
, pixel_format
;
7191 crtc
->base
.primary
->fb
= kzalloc(sizeof(struct intel_framebuffer
), GFP_KERNEL
);
7192 if (!crtc
->base
.primary
->fb
) {
7193 DRM_DEBUG_KMS("failed to alloc fb\n");
7197 val
= I915_READ(DSPCNTR(plane
));
7199 if (INTEL_INFO(dev
)->gen
>= 4)
7200 if (val
& DISPPLANE_TILED
)
7201 plane_config
->tiled
= true;
7203 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
7204 fourcc
= intel_format_to_fourcc(pixel_format
);
7205 crtc
->base
.primary
->fb
->pixel_format
= fourcc
;
7206 crtc
->base
.primary
->fb
->bits_per_pixel
=
7207 drm_format_plane_cpp(fourcc
, 0) * 8;
7209 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
7210 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
7211 offset
= I915_READ(DSPOFFSET(plane
));
7213 if (plane_config
->tiled
)
7214 offset
= I915_READ(DSPTILEOFF(plane
));
7216 offset
= I915_READ(DSPLINOFF(plane
));
7218 plane_config
->base
= base
;
7220 val
= I915_READ(PIPESRC(pipe
));
7221 crtc
->base
.primary
->fb
->width
= ((val
>> 16) & 0xfff) + 1;
7222 crtc
->base
.primary
->fb
->height
= ((val
>> 0) & 0xfff) + 1;
7224 val
= I915_READ(DSPSTRIDE(pipe
));
7225 crtc
->base
.primary
->fb
->pitches
[0] = val
& 0xffffff80;
7227 aligned_height
= intel_align_height(dev
, crtc
->base
.primary
->fb
->height
,
7228 plane_config
->tiled
);
7230 plane_config
->size
= PAGE_ALIGN(crtc
->base
.primary
->fb
->pitches
[0] *
7233 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7234 pipe
, plane
, crtc
->base
.primary
->fb
->width
,
7235 crtc
->base
.primary
->fb
->height
,
7236 crtc
->base
.primary
->fb
->bits_per_pixel
, base
,
7237 crtc
->base
.primary
->fb
->pitches
[0],
7238 plane_config
->size
);
7241 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
7242 struct intel_crtc_config
*pipe_config
)
7244 struct drm_device
*dev
= crtc
->base
.dev
;
7245 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7248 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
7249 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
7251 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
7252 if (!(tmp
& PIPECONF_ENABLE
))
7255 switch (tmp
& PIPECONF_BPC_MASK
) {
7257 pipe_config
->pipe_bpp
= 18;
7260 pipe_config
->pipe_bpp
= 24;
7262 case PIPECONF_10BPC
:
7263 pipe_config
->pipe_bpp
= 30;
7265 case PIPECONF_12BPC
:
7266 pipe_config
->pipe_bpp
= 36;
7272 if (tmp
& PIPECONF_COLOR_RANGE_SELECT
)
7273 pipe_config
->limited_color_range
= true;
7275 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
7276 struct intel_shared_dpll
*pll
;
7278 pipe_config
->has_pch_encoder
= true;
7280 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
7281 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
7282 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
7284 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
7286 if (HAS_PCH_IBX(dev_priv
->dev
)) {
7287 pipe_config
->shared_dpll
=
7288 (enum intel_dpll_id
) crtc
->pipe
;
7290 tmp
= I915_READ(PCH_DPLL_SEL
);
7291 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
7292 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_B
;
7294 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_A
;
7297 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
7299 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
7300 &pipe_config
->dpll_hw_state
));
7302 tmp
= pipe_config
->dpll_hw_state
.dpll
;
7303 pipe_config
->pixel_multiplier
=
7304 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
7305 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
7307 ironlake_pch_clock_get(crtc
, pipe_config
);
7309 pipe_config
->pixel_multiplier
= 1;
7312 intel_get_pipe_timings(crtc
, pipe_config
);
7314 ironlake_get_pfit_config(crtc
, pipe_config
);
7319 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
7321 struct drm_device
*dev
= dev_priv
->dev
;
7322 struct intel_crtc
*crtc
;
7324 for_each_intel_crtc(dev
, crtc
)
7325 WARN(crtc
->active
, "CRTC for pipe %c enabled\n",
7326 pipe_name(crtc
->pipe
));
7328 WARN(I915_READ(HSW_PWR_WELL_DRIVER
), "Power well on\n");
7329 WARN(I915_READ(SPLL_CTL
) & SPLL_PLL_ENABLE
, "SPLL enabled\n");
7330 WARN(I915_READ(WRPLL_CTL1
) & WRPLL_PLL_ENABLE
, "WRPLL1 enabled\n");
7331 WARN(I915_READ(WRPLL_CTL2
) & WRPLL_PLL_ENABLE
, "WRPLL2 enabled\n");
7332 WARN(I915_READ(PCH_PP_STATUS
) & PP_ON
, "Panel power on\n");
7333 WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
7334 "CPU PWM1 enabled\n");
7335 WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
7336 "CPU PWM2 enabled\n");
7337 WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
7338 "PCH PWM1 enabled\n");
7339 WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
7340 "Utility pin enabled\n");
7341 WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
7344 * In theory we can still leave IRQs enabled, as long as only the HPD
7345 * interrupts remain enabled. We used to check for that, but since it's
7346 * gen-specific and since we only disable LCPLL after we fully disable
7347 * the interrupts, the check below should be enough.
7349 WARN(!dev_priv
->pm
.irqs_disabled
, "IRQs enabled\n");
7352 static uint32_t hsw_read_dcomp(struct drm_i915_private
*dev_priv
)
7354 struct drm_device
*dev
= dev_priv
->dev
;
7356 if (IS_HASWELL(dev
))
7357 return I915_READ(D_COMP_HSW
);
7359 return I915_READ(D_COMP_BDW
);
7362 static void hsw_write_dcomp(struct drm_i915_private
*dev_priv
, uint32_t val
)
7364 struct drm_device
*dev
= dev_priv
->dev
;
7366 if (IS_HASWELL(dev
)) {
7367 mutex_lock(&dev_priv
->rps
.hw_lock
);
7368 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
,
7370 DRM_ERROR("Failed to write to D_COMP\n");
7371 mutex_unlock(&dev_priv
->rps
.hw_lock
);
7373 I915_WRITE(D_COMP_BDW
, val
);
7374 POSTING_READ(D_COMP_BDW
);
7379 * This function implements pieces of two sequences from BSpec:
7380 * - Sequence for display software to disable LCPLL
7381 * - Sequence for display software to allow package C8+
7382 * The steps implemented here are just the steps that actually touch the LCPLL
7383 * register. Callers should take care of disabling all the display engine
7384 * functions, doing the mode unset, fixing interrupts, etc.
7386 static void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
7387 bool switch_to_fclk
, bool allow_power_down
)
7391 assert_can_disable_lcpll(dev_priv
);
7393 val
= I915_READ(LCPLL_CTL
);
7395 if (switch_to_fclk
) {
7396 val
|= LCPLL_CD_SOURCE_FCLK
;
7397 I915_WRITE(LCPLL_CTL
, val
);
7399 if (wait_for_atomic_us(I915_READ(LCPLL_CTL
) &
7400 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
7401 DRM_ERROR("Switching to FCLK failed\n");
7403 val
= I915_READ(LCPLL_CTL
);
7406 val
|= LCPLL_PLL_DISABLE
;
7407 I915_WRITE(LCPLL_CTL
, val
);
7408 POSTING_READ(LCPLL_CTL
);
7410 if (wait_for((I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
) == 0, 1))
7411 DRM_ERROR("LCPLL still locked\n");
7413 val
= hsw_read_dcomp(dev_priv
);
7414 val
|= D_COMP_COMP_DISABLE
;
7415 hsw_write_dcomp(dev_priv
, val
);
7418 if (wait_for((hsw_read_dcomp(dev_priv
) & D_COMP_RCOMP_IN_PROGRESS
) == 0,
7420 DRM_ERROR("D_COMP RCOMP still in progress\n");
7422 if (allow_power_down
) {
7423 val
= I915_READ(LCPLL_CTL
);
7424 val
|= LCPLL_POWER_DOWN_ALLOW
;
7425 I915_WRITE(LCPLL_CTL
, val
);
7426 POSTING_READ(LCPLL_CTL
);
7431 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7434 static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
7437 unsigned long irqflags
;
7439 val
= I915_READ(LCPLL_CTL
);
7441 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
7442 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
7446 * Make sure we're not on PC8 state before disabling PC8, otherwise
7447 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7449 * The other problem is that hsw_restore_lcpll() is called as part of
7450 * the runtime PM resume sequence, so we can't just call
7451 * gen6_gt_force_wake_get() because that function calls
7452 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7453 * while we are on the resume sequence. So to solve this problem we have
7454 * to call special forcewake code that doesn't touch runtime PM and
7455 * doesn't enable the forcewake delayed work.
7457 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
7458 if (dev_priv
->uncore
.forcewake_count
++ == 0)
7459 dev_priv
->uncore
.funcs
.force_wake_get(dev_priv
, FORCEWAKE_ALL
);
7460 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
7462 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
7463 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
7464 I915_WRITE(LCPLL_CTL
, val
);
7465 POSTING_READ(LCPLL_CTL
);
7468 val
= hsw_read_dcomp(dev_priv
);
7469 val
|= D_COMP_COMP_FORCE
;
7470 val
&= ~D_COMP_COMP_DISABLE
;
7471 hsw_write_dcomp(dev_priv
, val
);
7473 val
= I915_READ(LCPLL_CTL
);
7474 val
&= ~LCPLL_PLL_DISABLE
;
7475 I915_WRITE(LCPLL_CTL
, val
);
7477 if (wait_for(I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
, 5))
7478 DRM_ERROR("LCPLL not locked yet\n");
7480 if (val
& LCPLL_CD_SOURCE_FCLK
) {
7481 val
= I915_READ(LCPLL_CTL
);
7482 val
&= ~LCPLL_CD_SOURCE_FCLK
;
7483 I915_WRITE(LCPLL_CTL
, val
);
7485 if (wait_for_atomic_us((I915_READ(LCPLL_CTL
) &
7486 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
7487 DRM_ERROR("Switching back to LCPLL failed\n");
7490 /* See the big comment above. */
7491 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
7492 if (--dev_priv
->uncore
.forcewake_count
== 0)
7493 dev_priv
->uncore
.funcs
.force_wake_put(dev_priv
, FORCEWAKE_ALL
);
7494 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
7498 * Package states C8 and deeper are really deep PC states that can only be
7499 * reached when all the devices on the system allow it, so even if the graphics
7500 * device allows PC8+, it doesn't mean the system will actually get to these
7501 * states. Our driver only allows PC8+ when going into runtime PM.
7503 * The requirements for PC8+ are that all the outputs are disabled, the power
7504 * well is disabled and most interrupts are disabled, and these are also
7505 * requirements for runtime PM. When these conditions are met, we manually do
7506 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7507 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7510 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7511 * the state of some registers, so when we come back from PC8+ we need to
7512 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7513 * need to take care of the registers kept by RC6. Notice that this happens even
7514 * if we don't put the device in PCI D3 state (which is what currently happens
7515 * because of the runtime PM support).
7517 * For more, read "Display Sequences for Package C8" on the hardware
7520 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
)
7522 struct drm_device
*dev
= dev_priv
->dev
;
7525 DRM_DEBUG_KMS("Enabling package C8+\n");
7527 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
7528 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
7529 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
7530 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
7533 lpt_disable_clkout_dp(dev
);
7534 hsw_disable_lcpll(dev_priv
, true, true);
7537 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
)
7539 struct drm_device
*dev
= dev_priv
->dev
;
7542 DRM_DEBUG_KMS("Disabling package C8+\n");
7544 hsw_restore_lcpll(dev_priv
);
7545 lpt_init_pch_refclk(dev
);
7547 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
7548 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
7549 val
|= PCH_LP_PARTITION_LEVEL_DISABLE
;
7550 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
7553 intel_prepare_ddi(dev
);
7556 static void snb_modeset_global_resources(struct drm_device
*dev
)
7558 modeset_update_crtc_power_domains(dev
);
7561 static void haswell_modeset_global_resources(struct drm_device
*dev
)
7563 modeset_update_crtc_power_domains(dev
);
7566 static int haswell_crtc_mode_set(struct drm_crtc
*crtc
,
7568 struct drm_framebuffer
*fb
)
7570 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7572 if (!intel_ddi_pll_select(intel_crtc
))
7575 intel_crtc
->lowfreq_avail
= false;
7580 static void haswell_get_ddi_port_state(struct intel_crtc
*crtc
,
7581 struct intel_crtc_config
*pipe_config
)
7583 struct drm_device
*dev
= crtc
->base
.dev
;
7584 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7585 struct intel_shared_dpll
*pll
;
7589 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
7591 port
= (tmp
& TRANS_DDI_PORT_MASK
) >> TRANS_DDI_PORT_SHIFT
;
7593 pipe_config
->ddi_pll_sel
= I915_READ(PORT_CLK_SEL(port
));
7595 switch (pipe_config
->ddi_pll_sel
) {
7596 case PORT_CLK_SEL_WRPLL1
:
7597 pipe_config
->shared_dpll
= DPLL_ID_WRPLL1
;
7599 case PORT_CLK_SEL_WRPLL2
:
7600 pipe_config
->shared_dpll
= DPLL_ID_WRPLL2
;
7604 if (pipe_config
->shared_dpll
>= 0) {
7605 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
7607 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
7608 &pipe_config
->dpll_hw_state
));
7612 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7613 * DDI E. So just check whether this pipe is wired to DDI E and whether
7614 * the PCH transcoder is on.
7616 if ((port
== PORT_E
) && I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
7617 pipe_config
->has_pch_encoder
= true;
7619 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
7620 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
7621 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
7623 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
7627 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
7628 struct intel_crtc_config
*pipe_config
)
7630 struct drm_device
*dev
= crtc
->base
.dev
;
7631 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7632 enum intel_display_power_domain pfit_domain
;
7635 if (!intel_display_power_enabled(dev_priv
,
7636 POWER_DOMAIN_PIPE(crtc
->pipe
)))
7639 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
7640 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
7642 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
7643 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
7644 enum pipe trans_edp_pipe
;
7645 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
7647 WARN(1, "unknown pipe linked to edp transcoder\n");
7648 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
7649 case TRANS_DDI_EDP_INPUT_A_ON
:
7650 trans_edp_pipe
= PIPE_A
;
7652 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
7653 trans_edp_pipe
= PIPE_B
;
7655 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
7656 trans_edp_pipe
= PIPE_C
;
7660 if (trans_edp_pipe
== crtc
->pipe
)
7661 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
7664 if (!intel_display_power_enabled(dev_priv
,
7665 POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
)))
7668 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
7669 if (!(tmp
& PIPECONF_ENABLE
))
7672 haswell_get_ddi_port_state(crtc
, pipe_config
);
7674 intel_get_pipe_timings(crtc
, pipe_config
);
7676 pfit_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
7677 if (intel_display_power_enabled(dev_priv
, pfit_domain
))
7678 ironlake_get_pfit_config(crtc
, pipe_config
);
7680 if (IS_HASWELL(dev
))
7681 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
7682 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
7684 pipe_config
->pixel_multiplier
= 1;
7692 } hdmi_audio_clock
[] = {
7693 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175
},
7694 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200
}, /* default per bspec */
7695 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000
},
7696 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027
},
7697 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000
},
7698 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054
},
7699 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176
},
7700 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250
},
7701 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352
},
7702 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500
},
7705 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7706 static u32
audio_config_hdmi_pixel_clock(struct drm_display_mode
*mode
)
7710 for (i
= 0; i
< ARRAY_SIZE(hdmi_audio_clock
); i
++) {
7711 if (mode
->clock
== hdmi_audio_clock
[i
].clock
)
7715 if (i
== ARRAY_SIZE(hdmi_audio_clock
)) {
7716 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode
->clock
);
7720 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7721 hdmi_audio_clock
[i
].clock
,
7722 hdmi_audio_clock
[i
].config
);
7724 return hdmi_audio_clock
[i
].config
;
7727 static bool intel_eld_uptodate(struct drm_connector
*connector
,
7728 int reg_eldv
, uint32_t bits_eldv
,
7729 int reg_elda
, uint32_t bits_elda
,
7732 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
7733 uint8_t *eld
= connector
->eld
;
7736 i
= I915_READ(reg_eldv
);
7745 i
= I915_READ(reg_elda
);
7747 I915_WRITE(reg_elda
, i
);
7749 for (i
= 0; i
< eld
[2]; i
++)
7750 if (I915_READ(reg_edid
) != *((uint32_t *)eld
+ i
))
7756 static void g4x_write_eld(struct drm_connector
*connector
,
7757 struct drm_crtc
*crtc
,
7758 struct drm_display_mode
*mode
)
7760 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
7761 uint8_t *eld
= connector
->eld
;
7766 i
= I915_READ(G4X_AUD_VID_DID
);
7768 if (i
== INTEL_AUDIO_DEVBLC
|| i
== INTEL_AUDIO_DEVCL
)
7769 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
7771 eldv
= G4X_ELDV_DEVCTG
;
7773 if (intel_eld_uptodate(connector
,
7774 G4X_AUD_CNTL_ST
, eldv
,
7775 G4X_AUD_CNTL_ST
, G4X_ELD_ADDR
,
7776 G4X_HDMIW_HDMIEDID
))
7779 i
= I915_READ(G4X_AUD_CNTL_ST
);
7780 i
&= ~(eldv
| G4X_ELD_ADDR
);
7781 len
= (i
>> 9) & 0x1f; /* ELD buffer size */
7782 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
7787 len
= min_t(uint8_t, eld
[2], len
);
7788 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
7789 for (i
= 0; i
< len
; i
++)
7790 I915_WRITE(G4X_HDMIW_HDMIEDID
, *((uint32_t *)eld
+ i
));
7792 i
= I915_READ(G4X_AUD_CNTL_ST
);
7794 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
7797 static void haswell_write_eld(struct drm_connector
*connector
,
7798 struct drm_crtc
*crtc
,
7799 struct drm_display_mode
*mode
)
7801 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
7802 uint8_t *eld
= connector
->eld
;
7806 int pipe
= to_intel_crtc(crtc
)->pipe
;
7809 int hdmiw_hdmiedid
= HSW_AUD_EDID_DATA(pipe
);
7810 int aud_cntl_st
= HSW_AUD_DIP_ELD_CTRL(pipe
);
7811 int aud_config
= HSW_AUD_CFG(pipe
);
7812 int aud_cntrl_st2
= HSW_AUD_PIN_ELD_CP_VLD
;
7814 /* Audio output enable */
7815 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7816 tmp
= I915_READ(aud_cntrl_st2
);
7817 tmp
|= (AUDIO_OUTPUT_ENABLE_A
<< (pipe
* 4));
7818 I915_WRITE(aud_cntrl_st2
, tmp
);
7819 POSTING_READ(aud_cntrl_st2
);
7821 assert_pipe_disabled(dev_priv
, to_intel_crtc(crtc
)->pipe
);
7823 /* Set ELD valid state */
7824 tmp
= I915_READ(aud_cntrl_st2
);
7825 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp
);
7826 tmp
|= (AUDIO_ELD_VALID_A
<< (pipe
* 4));
7827 I915_WRITE(aud_cntrl_st2
, tmp
);
7828 tmp
= I915_READ(aud_cntrl_st2
);
7829 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp
);
7831 /* Enable HDMI mode */
7832 tmp
= I915_READ(aud_config
);
7833 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp
);
7834 /* clear N_programing_enable and N_value_index */
7835 tmp
&= ~(AUD_CONFIG_N_VALUE_INDEX
| AUD_CONFIG_N_PROG_ENABLE
);
7836 I915_WRITE(aud_config
, tmp
);
7838 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
7840 eldv
= AUDIO_ELD_VALID_A
<< (pipe
* 4);
7842 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
7843 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7844 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7845 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
7847 I915_WRITE(aud_config
, audio_config_hdmi_pixel_clock(mode
));
7850 if (intel_eld_uptodate(connector
,
7851 aud_cntrl_st2
, eldv
,
7852 aud_cntl_st
, IBX_ELD_ADDRESS
,
7856 i
= I915_READ(aud_cntrl_st2
);
7858 I915_WRITE(aud_cntrl_st2
, i
);
7863 i
= I915_READ(aud_cntl_st
);
7864 i
&= ~IBX_ELD_ADDRESS
;
7865 I915_WRITE(aud_cntl_st
, i
);
7866 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
7867 DRM_DEBUG_DRIVER("port num:%d\n", i
);
7869 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
7870 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
7871 for (i
= 0; i
< len
; i
++)
7872 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
7874 i
= I915_READ(aud_cntrl_st2
);
7876 I915_WRITE(aud_cntrl_st2
, i
);
7880 static void ironlake_write_eld(struct drm_connector
*connector
,
7881 struct drm_crtc
*crtc
,
7882 struct drm_display_mode
*mode
)
7884 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
7885 uint8_t *eld
= connector
->eld
;
7893 int pipe
= to_intel_crtc(crtc
)->pipe
;
7895 if (HAS_PCH_IBX(connector
->dev
)) {
7896 hdmiw_hdmiedid
= IBX_HDMIW_HDMIEDID(pipe
);
7897 aud_config
= IBX_AUD_CFG(pipe
);
7898 aud_cntl_st
= IBX_AUD_CNTL_ST(pipe
);
7899 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
7900 } else if (IS_VALLEYVIEW(connector
->dev
)) {
7901 hdmiw_hdmiedid
= VLV_HDMIW_HDMIEDID(pipe
);
7902 aud_config
= VLV_AUD_CFG(pipe
);
7903 aud_cntl_st
= VLV_AUD_CNTL_ST(pipe
);
7904 aud_cntrl_st2
= VLV_AUD_CNTL_ST2
;
7906 hdmiw_hdmiedid
= CPT_HDMIW_HDMIEDID(pipe
);
7907 aud_config
= CPT_AUD_CFG(pipe
);
7908 aud_cntl_st
= CPT_AUD_CNTL_ST(pipe
);
7909 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
7912 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
7914 if (IS_VALLEYVIEW(connector
->dev
)) {
7915 struct intel_encoder
*intel_encoder
;
7916 struct intel_digital_port
*intel_dig_port
;
7918 intel_encoder
= intel_attached_encoder(connector
);
7919 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
7920 i
= intel_dig_port
->port
;
7922 i
= I915_READ(aud_cntl_st
);
7923 i
= (i
>> 29) & DIP_PORT_SEL_MASK
;
7924 /* DIP_Port_Select, 0x1 = PortB */
7928 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7929 /* operate blindly on all ports */
7930 eldv
= IBX_ELD_VALIDB
;
7931 eldv
|= IBX_ELD_VALIDB
<< 4;
7932 eldv
|= IBX_ELD_VALIDB
<< 8;
7934 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i
));
7935 eldv
= IBX_ELD_VALIDB
<< ((i
- 1) * 4);
7938 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
7939 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7940 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7941 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
7943 I915_WRITE(aud_config
, audio_config_hdmi_pixel_clock(mode
));
7946 if (intel_eld_uptodate(connector
,
7947 aud_cntrl_st2
, eldv
,
7948 aud_cntl_st
, IBX_ELD_ADDRESS
,
7952 i
= I915_READ(aud_cntrl_st2
);
7954 I915_WRITE(aud_cntrl_st2
, i
);
7959 i
= I915_READ(aud_cntl_st
);
7960 i
&= ~IBX_ELD_ADDRESS
;
7961 I915_WRITE(aud_cntl_st
, i
);
7963 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
7964 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
7965 for (i
= 0; i
< len
; i
++)
7966 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
7968 i
= I915_READ(aud_cntrl_st2
);
7970 I915_WRITE(aud_cntrl_st2
, i
);
7973 void intel_write_eld(struct drm_encoder
*encoder
,
7974 struct drm_display_mode
*mode
)
7976 struct drm_crtc
*crtc
= encoder
->crtc
;
7977 struct drm_connector
*connector
;
7978 struct drm_device
*dev
= encoder
->dev
;
7979 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7981 connector
= drm_select_eld(encoder
, mode
);
7985 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7988 connector
->encoder
->base
.id
,
7989 connector
->encoder
->name
);
7991 connector
->eld
[6] = drm_av_sync_delay(connector
, mode
) / 2;
7993 if (dev_priv
->display
.write_eld
)
7994 dev_priv
->display
.write_eld(connector
, crtc
, mode
);
7997 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
7999 struct drm_device
*dev
= crtc
->dev
;
8000 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8001 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8004 if (base
!= intel_crtc
->cursor_base
) {
8005 /* On these chipsets we can only modify the base whilst
8006 * the cursor is disabled.
8008 if (intel_crtc
->cursor_cntl
) {
8009 I915_WRITE(_CURACNTR
, 0);
8010 POSTING_READ(_CURACNTR
);
8011 intel_crtc
->cursor_cntl
= 0;
8014 I915_WRITE(_CURABASE
, base
);
8015 POSTING_READ(_CURABASE
);
8018 /* XXX width must be 64, stride 256 => 0x00 << 28 */
8021 cntl
= (CURSOR_ENABLE
|
8022 CURSOR_GAMMA_ENABLE
|
8023 CURSOR_FORMAT_ARGB
);
8024 if (intel_crtc
->cursor_cntl
!= cntl
) {
8025 I915_WRITE(_CURACNTR
, cntl
);
8026 POSTING_READ(_CURACNTR
);
8027 intel_crtc
->cursor_cntl
= cntl
;
8031 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
8033 struct drm_device
*dev
= crtc
->dev
;
8034 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8035 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8036 int pipe
= intel_crtc
->pipe
;
8041 cntl
= MCURSOR_GAMMA_ENABLE
;
8042 switch (intel_crtc
->cursor_width
) {
8044 cntl
|= CURSOR_MODE_64_ARGB_AX
;
8047 cntl
|= CURSOR_MODE_128_ARGB_AX
;
8050 cntl
|= CURSOR_MODE_256_ARGB_AX
;
8056 cntl
|= pipe
<< 28; /* Connect to correct pipe */
8058 if (intel_crtc
->cursor_cntl
!= cntl
) {
8059 I915_WRITE(CURCNTR(pipe
), cntl
);
8060 POSTING_READ(CURCNTR(pipe
));
8061 intel_crtc
->cursor_cntl
= cntl
;
8064 /* and commit changes on next vblank */
8065 I915_WRITE(CURBASE(pipe
), base
);
8066 POSTING_READ(CURBASE(pipe
));
8069 static void ivb_update_cursor(struct drm_crtc
*crtc
, u32 base
)
8071 struct drm_device
*dev
= crtc
->dev
;
8072 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8073 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8074 int pipe
= intel_crtc
->pipe
;
8079 cntl
= MCURSOR_GAMMA_ENABLE
;
8080 switch (intel_crtc
->cursor_width
) {
8082 cntl
|= CURSOR_MODE_64_ARGB_AX
;
8085 cntl
|= CURSOR_MODE_128_ARGB_AX
;
8088 cntl
|= CURSOR_MODE_256_ARGB_AX
;
8095 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
8096 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
8098 if (intel_crtc
->cursor_cntl
!= cntl
) {
8099 I915_WRITE(CURCNTR(pipe
), cntl
);
8100 POSTING_READ(CURCNTR(pipe
));
8101 intel_crtc
->cursor_cntl
= cntl
;
8104 /* and commit changes on next vblank */
8105 I915_WRITE(CURBASE(pipe
), base
);
8106 POSTING_READ(CURBASE(pipe
));
8109 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8110 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
8113 struct drm_device
*dev
= crtc
->dev
;
8114 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8115 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8116 int pipe
= intel_crtc
->pipe
;
8117 int x
= crtc
->cursor_x
;
8118 int y
= crtc
->cursor_y
;
8119 u32 base
= 0, pos
= 0;
8122 base
= intel_crtc
->cursor_addr
;
8124 if (x
>= intel_crtc
->config
.pipe_src_w
)
8127 if (y
>= intel_crtc
->config
.pipe_src_h
)
8131 if (x
+ intel_crtc
->cursor_width
<= 0)
8134 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
8137 pos
|= x
<< CURSOR_X_SHIFT
;
8140 if (y
+ intel_crtc
->cursor_height
<= 0)
8143 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
8146 pos
|= y
<< CURSOR_Y_SHIFT
;
8148 if (base
== 0 && intel_crtc
->cursor_base
== 0)
8151 I915_WRITE(CURPOS(pipe
), pos
);
8153 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
) || IS_BROADWELL(dev
))
8154 ivb_update_cursor(crtc
, base
);
8155 else if (IS_845G(dev
) || IS_I865G(dev
))
8156 i845_update_cursor(crtc
, base
);
8158 i9xx_update_cursor(crtc
, base
);
8159 intel_crtc
->cursor_base
= base
;
8163 * intel_crtc_cursor_set_obj - Set cursor to specified GEM object
8165 * Note that the object's reference will be consumed if the update fails. If
8166 * the update succeeds, the reference of the old object (if any) will be
8169 static int intel_crtc_cursor_set_obj(struct drm_crtc
*crtc
,
8170 struct drm_i915_gem_object
*obj
,
8171 uint32_t width
, uint32_t height
)
8173 struct drm_device
*dev
= crtc
->dev
;
8174 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8175 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8176 enum pipe pipe
= intel_crtc
->pipe
;
8181 /* if we want to turn off the cursor ignore width and height */
8183 DRM_DEBUG_KMS("cursor off\n");
8186 mutex_lock(&dev
->struct_mutex
);
8190 /* Check for which cursor types we support */
8191 if (!((width
== 64 && height
== 64) ||
8192 (width
== 128 && height
== 128 && !IS_GEN2(dev
)) ||
8193 (width
== 256 && height
== 256 && !IS_GEN2(dev
)))) {
8194 DRM_DEBUG("Cursor dimension not supported\n");
8198 if (obj
->base
.size
< width
* height
* 4) {
8199 DRM_DEBUG_KMS("buffer is too small\n");
8204 /* we only need to pin inside GTT if cursor is non-phy */
8205 mutex_lock(&dev
->struct_mutex
);
8206 if (!INTEL_INFO(dev
)->cursor_needs_physical
) {
8209 if (obj
->tiling_mode
) {
8210 DRM_DEBUG_KMS("cursor cannot be tiled\n");
8215 /* Note that the w/a also requires 2 PTE of padding following
8216 * the bo. We currently fill all unused PTE with the shadow
8217 * page and so we should always have valid PTE following the
8218 * cursor preventing the VT-d warning.
8221 if (need_vtd_wa(dev
))
8222 alignment
= 64*1024;
8224 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, NULL
);
8226 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8230 ret
= i915_gem_object_put_fence(obj
);
8232 DRM_DEBUG_KMS("failed to release fence for cursor");
8236 addr
= i915_gem_obj_ggtt_offset(obj
);
8238 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
8239 ret
= i915_gem_object_attach_phys(obj
, align
);
8241 DRM_DEBUG_KMS("failed to attach phys object\n");
8244 addr
= obj
->phys_handle
->busaddr
;
8248 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
8251 if (intel_crtc
->cursor_bo
) {
8252 if (!INTEL_INFO(dev
)->cursor_needs_physical
)
8253 i915_gem_object_unpin_from_display_plane(intel_crtc
->cursor_bo
);
8256 i915_gem_track_fb(intel_crtc
->cursor_bo
, obj
,
8257 INTEL_FRONTBUFFER_CURSOR(pipe
));
8258 mutex_unlock(&dev
->struct_mutex
);
8260 old_width
= intel_crtc
->cursor_width
;
8262 intel_crtc
->cursor_addr
= addr
;
8263 intel_crtc
->cursor_bo
= obj
;
8264 intel_crtc
->cursor_width
= width
;
8265 intel_crtc
->cursor_height
= height
;
8267 if (intel_crtc
->active
) {
8268 if (old_width
!= width
)
8269 intel_update_watermarks(crtc
);
8270 intel_crtc_update_cursor(crtc
, intel_crtc
->cursor_bo
!= NULL
);
8273 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_CURSOR(pipe
));
8277 i915_gem_object_unpin_from_display_plane(obj
);
8279 mutex_unlock(&dev
->struct_mutex
);
8281 drm_gem_object_unreference_unlocked(&obj
->base
);
8285 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
8286 u16
*blue
, uint32_t start
, uint32_t size
)
8288 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
8289 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8291 for (i
= start
; i
< end
; i
++) {
8292 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
8293 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
8294 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
8297 intel_crtc_load_lut(crtc
);
8300 /* VESA 640x480x72Hz mode to set on the pipe */
8301 static struct drm_display_mode load_detect_mode
= {
8302 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
8303 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
8306 struct drm_framebuffer
*
8307 __intel_framebuffer_create(struct drm_device
*dev
,
8308 struct drm_mode_fb_cmd2
*mode_cmd
,
8309 struct drm_i915_gem_object
*obj
)
8311 struct intel_framebuffer
*intel_fb
;
8314 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
8316 drm_gem_object_unreference_unlocked(&obj
->base
);
8317 return ERR_PTR(-ENOMEM
);
8320 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
8324 return &intel_fb
->base
;
8326 drm_gem_object_unreference_unlocked(&obj
->base
);
8329 return ERR_PTR(ret
);
8332 static struct drm_framebuffer
*
8333 intel_framebuffer_create(struct drm_device
*dev
,
8334 struct drm_mode_fb_cmd2
*mode_cmd
,
8335 struct drm_i915_gem_object
*obj
)
8337 struct drm_framebuffer
*fb
;
8340 ret
= i915_mutex_lock_interruptible(dev
);
8342 return ERR_PTR(ret
);
8343 fb
= __intel_framebuffer_create(dev
, mode_cmd
, obj
);
8344 mutex_unlock(&dev
->struct_mutex
);
8350 intel_framebuffer_pitch_for_width(int width
, int bpp
)
8352 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
8353 return ALIGN(pitch
, 64);
8357 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
8359 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
8360 return PAGE_ALIGN(pitch
* mode
->vdisplay
);
8363 static struct drm_framebuffer
*
8364 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
8365 struct drm_display_mode
*mode
,
8368 struct drm_i915_gem_object
*obj
;
8369 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
8371 obj
= i915_gem_alloc_object(dev
,
8372 intel_framebuffer_size_for_mode(mode
, bpp
));
8374 return ERR_PTR(-ENOMEM
);
8376 mode_cmd
.width
= mode
->hdisplay
;
8377 mode_cmd
.height
= mode
->vdisplay
;
8378 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
8380 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
8382 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
8385 static struct drm_framebuffer
*
8386 mode_fits_in_fbdev(struct drm_device
*dev
,
8387 struct drm_display_mode
*mode
)
8389 #ifdef CONFIG_DRM_I915_FBDEV
8390 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8391 struct drm_i915_gem_object
*obj
;
8392 struct drm_framebuffer
*fb
;
8394 if (!dev_priv
->fbdev
)
8397 if (!dev_priv
->fbdev
->fb
)
8400 obj
= dev_priv
->fbdev
->fb
->obj
;
8403 fb
= &dev_priv
->fbdev
->fb
->base
;
8404 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
8405 fb
->bits_per_pixel
))
8408 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
8417 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
8418 struct drm_display_mode
*mode
,
8419 struct intel_load_detect_pipe
*old
,
8420 struct drm_modeset_acquire_ctx
*ctx
)
8422 struct intel_crtc
*intel_crtc
;
8423 struct intel_encoder
*intel_encoder
=
8424 intel_attached_encoder(connector
);
8425 struct drm_crtc
*possible_crtc
;
8426 struct drm_encoder
*encoder
= &intel_encoder
->base
;
8427 struct drm_crtc
*crtc
= NULL
;
8428 struct drm_device
*dev
= encoder
->dev
;
8429 struct drm_framebuffer
*fb
;
8430 struct drm_mode_config
*config
= &dev
->mode_config
;
8433 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8434 connector
->base
.id
, connector
->name
,
8435 encoder
->base
.id
, encoder
->name
);
8437 drm_modeset_acquire_init(ctx
, 0);
8440 ret
= drm_modeset_lock(&config
->connection_mutex
, ctx
);
8445 * Algorithm gets a little messy:
8447 * - if the connector already has an assigned crtc, use it (but make
8448 * sure it's on first)
8450 * - try to find the first unused crtc that can drive this connector,
8451 * and use that if we find one
8454 /* See if we already have a CRTC for this connector */
8455 if (encoder
->crtc
) {
8456 crtc
= encoder
->crtc
;
8458 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
8462 old
->dpms_mode
= connector
->dpms
;
8463 old
->load_detect_temp
= false;
8465 /* Make sure the crtc and connector are running */
8466 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
8467 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
8472 /* Find an unused one (if possible) */
8473 for_each_crtc(dev
, possible_crtc
) {
8475 if (!(encoder
->possible_crtcs
& (1 << i
)))
8477 if (!possible_crtc
->enabled
) {
8478 crtc
= possible_crtc
;
8484 * If we didn't find an unused CRTC, don't use any.
8487 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8491 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
8494 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
8495 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
8497 intel_crtc
= to_intel_crtc(crtc
);
8498 intel_crtc
->new_enabled
= true;
8499 intel_crtc
->new_config
= &intel_crtc
->config
;
8500 old
->dpms_mode
= connector
->dpms
;
8501 old
->load_detect_temp
= true;
8502 old
->release_fb
= NULL
;
8505 mode
= &load_detect_mode
;
8507 /* We need a framebuffer large enough to accommodate all accesses
8508 * that the plane may generate whilst we perform load detection.
8509 * We can not rely on the fbcon either being present (we get called
8510 * during its initialisation to detect all boot displays, or it may
8511 * not even exist) or that it is large enough to satisfy the
8514 fb
= mode_fits_in_fbdev(dev
, mode
);
8516 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8517 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
8518 old
->release_fb
= fb
;
8520 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8522 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8526 if (intel_set_mode(crtc
, mode
, 0, 0, fb
)) {
8527 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8528 if (old
->release_fb
)
8529 old
->release_fb
->funcs
->destroy(old
->release_fb
);
8533 /* let the connector get through one full cycle before testing */
8534 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
8538 intel_crtc
->new_enabled
= crtc
->enabled
;
8539 if (intel_crtc
->new_enabled
)
8540 intel_crtc
->new_config
= &intel_crtc
->config
;
8542 intel_crtc
->new_config
= NULL
;
8544 if (ret
== -EDEADLK
) {
8545 drm_modeset_backoff(ctx
);
8549 drm_modeset_drop_locks(ctx
);
8550 drm_modeset_acquire_fini(ctx
);
8555 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
8556 struct intel_load_detect_pipe
*old
,
8557 struct drm_modeset_acquire_ctx
*ctx
)
8559 struct intel_encoder
*intel_encoder
=
8560 intel_attached_encoder(connector
);
8561 struct drm_encoder
*encoder
= &intel_encoder
->base
;
8562 struct drm_crtc
*crtc
= encoder
->crtc
;
8563 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8565 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8566 connector
->base
.id
, connector
->name
,
8567 encoder
->base
.id
, encoder
->name
);
8569 if (old
->load_detect_temp
) {
8570 to_intel_connector(connector
)->new_encoder
= NULL
;
8571 intel_encoder
->new_crtc
= NULL
;
8572 intel_crtc
->new_enabled
= false;
8573 intel_crtc
->new_config
= NULL
;
8574 intel_set_mode(crtc
, NULL
, 0, 0, NULL
);
8576 if (old
->release_fb
) {
8577 drm_framebuffer_unregister_private(old
->release_fb
);
8578 drm_framebuffer_unreference(old
->release_fb
);
8585 /* Switch crtc and encoder back off if necessary */
8586 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
8587 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
8590 drm_modeset_drop_locks(ctx
);
8591 drm_modeset_acquire_fini(ctx
);
8594 static int i9xx_pll_refclk(struct drm_device
*dev
,
8595 const struct intel_crtc_config
*pipe_config
)
8597 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8598 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
8600 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
8601 return dev_priv
->vbt
.lvds_ssc_freq
;
8602 else if (HAS_PCH_SPLIT(dev
))
8604 else if (!IS_GEN2(dev
))
8610 /* Returns the clock of the currently programmed mode of the given pipe. */
8611 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
8612 struct intel_crtc_config
*pipe_config
)
8614 struct drm_device
*dev
= crtc
->base
.dev
;
8615 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8616 int pipe
= pipe_config
->cpu_transcoder
;
8617 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
8619 intel_clock_t clock
;
8620 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
8622 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
8623 fp
= pipe_config
->dpll_hw_state
.fp0
;
8625 fp
= pipe_config
->dpll_hw_state
.fp1
;
8627 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
8628 if (IS_PINEVIEW(dev
)) {
8629 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
8630 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
8632 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
8633 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
8636 if (!IS_GEN2(dev
)) {
8637 if (IS_PINEVIEW(dev
))
8638 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
8639 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
8641 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
8642 DPLL_FPA01_P1_POST_DIV_SHIFT
);
8644 switch (dpll
& DPLL_MODE_MASK
) {
8645 case DPLLB_MODE_DAC_SERIAL
:
8646 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
8649 case DPLLB_MODE_LVDS
:
8650 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
8654 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8655 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
8659 if (IS_PINEVIEW(dev
))
8660 pineview_clock(refclk
, &clock
);
8662 i9xx_clock(refclk
, &clock
);
8664 u32 lvds
= IS_I830(dev
) ? 0 : I915_READ(LVDS
);
8665 bool is_lvds
= (pipe
== 1) && (lvds
& LVDS_PORT_EN
);
8668 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
8669 DPLL_FPA01_P1_POST_DIV_SHIFT
);
8671 if (lvds
& LVDS_CLKB_POWER_UP
)
8676 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
8679 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
8680 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
8682 if (dpll
& PLL_P2_DIVIDE_BY_4
)
8688 i9xx_clock(refclk
, &clock
);
8692 * This value includes pixel_multiplier. We will use
8693 * port_clock to compute adjusted_mode.crtc_clock in the
8694 * encoder's get_config() function.
8696 pipe_config
->port_clock
= clock
.dot
;
8699 int intel_dotclock_calculate(int link_freq
,
8700 const struct intel_link_m_n
*m_n
)
8703 * The calculation for the data clock is:
8704 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8705 * But we want to avoid losing precison if possible, so:
8706 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8708 * and the link clock is simpler:
8709 * link_clock = (m * link_clock) / n
8715 return div_u64((u64
)m_n
->link_m
* link_freq
, m_n
->link_n
);
8718 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
8719 struct intel_crtc_config
*pipe_config
)
8721 struct drm_device
*dev
= crtc
->base
.dev
;
8723 /* read out port_clock from the DPLL */
8724 i9xx_crtc_clock_get(crtc
, pipe_config
);
8727 * This value does not include pixel_multiplier.
8728 * We will check that port_clock and adjusted_mode.crtc_clock
8729 * agree once we know their relationship in the encoder's
8730 * get_config() function.
8732 pipe_config
->adjusted_mode
.crtc_clock
=
8733 intel_dotclock_calculate(intel_fdi_link_freq(dev
) * 10000,
8734 &pipe_config
->fdi_m_n
);
8737 /** Returns the currently programmed mode of the given pipe. */
8738 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
8739 struct drm_crtc
*crtc
)
8741 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8742 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8743 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
8744 struct drm_display_mode
*mode
;
8745 struct intel_crtc_config pipe_config
;
8746 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
8747 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
8748 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
8749 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
8750 enum pipe pipe
= intel_crtc
->pipe
;
8752 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
8757 * Construct a pipe_config sufficient for getting the clock info
8758 * back out of crtc_clock_get.
8760 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8761 * to use a real value here instead.
8763 pipe_config
.cpu_transcoder
= (enum transcoder
) pipe
;
8764 pipe_config
.pixel_multiplier
= 1;
8765 pipe_config
.dpll_hw_state
.dpll
= I915_READ(DPLL(pipe
));
8766 pipe_config
.dpll_hw_state
.fp0
= I915_READ(FP0(pipe
));
8767 pipe_config
.dpll_hw_state
.fp1
= I915_READ(FP1(pipe
));
8768 i9xx_crtc_clock_get(intel_crtc
, &pipe_config
);
8770 mode
->clock
= pipe_config
.port_clock
/ pipe_config
.pixel_multiplier
;
8771 mode
->hdisplay
= (htot
& 0xffff) + 1;
8772 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
8773 mode
->hsync_start
= (hsync
& 0xffff) + 1;
8774 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
8775 mode
->vdisplay
= (vtot
& 0xffff) + 1;
8776 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
8777 mode
->vsync_start
= (vsync
& 0xffff) + 1;
8778 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
8780 drm_mode_set_name(mode
);
8785 static void intel_increase_pllclock(struct drm_device
*dev
,
8788 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8789 int dpll_reg
= DPLL(pipe
);
8792 if (HAS_PCH_SPLIT(dev
))
8795 if (!dev_priv
->lvds_downclock_avail
)
8798 dpll
= I915_READ(dpll_reg
);
8799 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
8800 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8802 assert_panel_unlocked(dev_priv
, pipe
);
8804 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
8805 I915_WRITE(dpll_reg
, dpll
);
8806 intel_wait_for_vblank(dev
, pipe
);
8808 dpll
= I915_READ(dpll_reg
);
8809 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
8810 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8814 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
8816 struct drm_device
*dev
= crtc
->dev
;
8817 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8818 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8820 if (HAS_PCH_SPLIT(dev
))
8823 if (!dev_priv
->lvds_downclock_avail
)
8827 * Since this is called by a timer, we should never get here in
8830 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
8831 int pipe
= intel_crtc
->pipe
;
8832 int dpll_reg
= DPLL(pipe
);
8835 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8837 assert_panel_unlocked(dev_priv
, pipe
);
8839 dpll
= I915_READ(dpll_reg
);
8840 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
8841 I915_WRITE(dpll_reg
, dpll
);
8842 intel_wait_for_vblank(dev
, pipe
);
8843 dpll
= I915_READ(dpll_reg
);
8844 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
8845 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8850 void intel_mark_busy(struct drm_device
*dev
)
8852 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8854 if (dev_priv
->mm
.busy
)
8857 intel_runtime_pm_get(dev_priv
);
8858 i915_update_gfx_val(dev_priv
);
8859 dev_priv
->mm
.busy
= true;
8862 void intel_mark_idle(struct drm_device
*dev
)
8864 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8865 struct drm_crtc
*crtc
;
8867 if (!dev_priv
->mm
.busy
)
8870 dev_priv
->mm
.busy
= false;
8872 if (!i915
.powersave
)
8875 for_each_crtc(dev
, crtc
) {
8876 if (!crtc
->primary
->fb
)
8879 intel_decrease_pllclock(crtc
);
8882 if (INTEL_INFO(dev
)->gen
>= 6)
8883 gen6_rps_idle(dev
->dev_private
);
8886 intel_runtime_pm_put(dev_priv
);
8891 * intel_mark_fb_busy - mark given planes as busy
8893 * @frontbuffer_bits: bits for the affected planes
8894 * @ring: optional ring for asynchronous commands
8896 * This function gets called every time the screen contents change. It can be
8897 * used to keep e.g. the update rate at the nominal refresh rate with DRRS.
8899 static void intel_mark_fb_busy(struct drm_device
*dev
,
8900 unsigned frontbuffer_bits
,
8901 struct intel_engine_cs
*ring
)
8905 if (!i915
.powersave
)
8908 for_each_pipe(pipe
) {
8909 if (!(frontbuffer_bits
& INTEL_FRONTBUFFER_ALL_MASK(pipe
)))
8912 intel_increase_pllclock(dev
, pipe
);
8913 if (ring
&& intel_fbc_enabled(dev
))
8914 ring
->fbc_dirty
= true;
8919 * intel_fb_obj_invalidate - invalidate frontbuffer object
8920 * @obj: GEM object to invalidate
8921 * @ring: set for asynchronous rendering
8923 * This function gets called every time rendering on the given object starts and
8924 * frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must
8925 * be invalidated. If @ring is non-NULL any subsequent invalidation will be delayed
8926 * until the rendering completes or a flip on this frontbuffer plane is
8929 void intel_fb_obj_invalidate(struct drm_i915_gem_object
*obj
,
8930 struct intel_engine_cs
*ring
)
8932 struct drm_device
*dev
= obj
->base
.dev
;
8933 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8935 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
8937 if (!obj
->frontbuffer_bits
)
8941 mutex_lock(&dev_priv
->fb_tracking
.lock
);
8942 dev_priv
->fb_tracking
.busy_bits
8943 |= obj
->frontbuffer_bits
;
8944 dev_priv
->fb_tracking
.flip_bits
8945 &= ~obj
->frontbuffer_bits
;
8946 mutex_unlock(&dev_priv
->fb_tracking
.lock
);
8949 intel_mark_fb_busy(dev
, obj
->frontbuffer_bits
, ring
);
8951 intel_edp_psr_exit(dev
);
8955 * intel_frontbuffer_flush - flush frontbuffer
8957 * @frontbuffer_bits: frontbuffer plane tracking bits
8959 * This function gets called every time rendering on the given planes has
8960 * completed and frontbuffer caching can be started again. Flushes will get
8961 * delayed if they're blocked by some oustanding asynchronous rendering.
8963 * Can be called without any locks held.
8965 void intel_frontbuffer_flush(struct drm_device
*dev
,
8966 unsigned frontbuffer_bits
)
8968 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8970 /* Delay flushing when rings are still busy.*/
8971 mutex_lock(&dev_priv
->fb_tracking
.lock
);
8972 frontbuffer_bits
&= ~dev_priv
->fb_tracking
.busy_bits
;
8973 mutex_unlock(&dev_priv
->fb_tracking
.lock
);
8975 intel_mark_fb_busy(dev
, frontbuffer_bits
, NULL
);
8977 intel_edp_psr_exit(dev
);
8981 * intel_fb_obj_flush - flush frontbuffer object
8982 * @obj: GEM object to flush
8983 * @retire: set when retiring asynchronous rendering
8985 * This function gets called every time rendering on the given object has
8986 * completed and frontbuffer caching can be started again. If @retire is true
8987 * then any delayed flushes will be unblocked.
8989 void intel_fb_obj_flush(struct drm_i915_gem_object
*obj
,
8992 struct drm_device
*dev
= obj
->base
.dev
;
8993 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8994 unsigned frontbuffer_bits
;
8996 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
8998 if (!obj
->frontbuffer_bits
)
9001 frontbuffer_bits
= obj
->frontbuffer_bits
;
9004 mutex_lock(&dev_priv
->fb_tracking
.lock
);
9005 /* Filter out new bits since rendering started. */
9006 frontbuffer_bits
&= dev_priv
->fb_tracking
.busy_bits
;
9008 dev_priv
->fb_tracking
.busy_bits
&= ~frontbuffer_bits
;
9009 mutex_unlock(&dev_priv
->fb_tracking
.lock
);
9012 intel_frontbuffer_flush(dev
, frontbuffer_bits
);
9016 * intel_frontbuffer_flip_prepare - prepare asnychronous frontbuffer flip
9018 * @frontbuffer_bits: frontbuffer plane tracking bits
9020 * This function gets called after scheduling a flip on @obj. The actual
9021 * frontbuffer flushing will be delayed until completion is signalled with
9022 * intel_frontbuffer_flip_complete. If an invalidate happens in between this
9023 * flush will be cancelled.
9025 * Can be called without any locks held.
9027 void intel_frontbuffer_flip_prepare(struct drm_device
*dev
,
9028 unsigned frontbuffer_bits
)
9030 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9032 mutex_lock(&dev_priv
->fb_tracking
.lock
);
9033 dev_priv
->fb_tracking
.flip_bits
9034 |= frontbuffer_bits
;
9035 mutex_unlock(&dev_priv
->fb_tracking
.lock
);
9039 * intel_frontbuffer_flip_complete - complete asynchronous frontbuffer flush
9041 * @frontbuffer_bits: frontbuffer plane tracking bits
9043 * This function gets called after the flip has been latched and will complete
9044 * on the next vblank. It will execute the fush if it hasn't been cancalled yet.
9046 * Can be called without any locks held.
9048 void intel_frontbuffer_flip_complete(struct drm_device
*dev
,
9049 unsigned frontbuffer_bits
)
9051 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9053 mutex_lock(&dev_priv
->fb_tracking
.lock
);
9054 /* Mask any cancelled flips. */
9055 frontbuffer_bits
&= dev_priv
->fb_tracking
.flip_bits
;
9056 dev_priv
->fb_tracking
.flip_bits
&= ~frontbuffer_bits
;
9057 mutex_unlock(&dev_priv
->fb_tracking
.lock
);
9059 intel_frontbuffer_flush(dev
, frontbuffer_bits
);
9062 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
9064 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9065 struct drm_device
*dev
= crtc
->dev
;
9066 struct intel_unpin_work
*work
;
9067 unsigned long flags
;
9069 spin_lock_irqsave(&dev
->event_lock
, flags
);
9070 work
= intel_crtc
->unpin_work
;
9071 intel_crtc
->unpin_work
= NULL
;
9072 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9075 cancel_work_sync(&work
->work
);
9079 drm_crtc_cleanup(crtc
);
9084 static void intel_unpin_work_fn(struct work_struct
*__work
)
9086 struct intel_unpin_work
*work
=
9087 container_of(__work
, struct intel_unpin_work
, work
);
9088 struct drm_device
*dev
= work
->crtc
->dev
;
9089 enum pipe pipe
= to_intel_crtc(work
->crtc
)->pipe
;
9091 mutex_lock(&dev
->struct_mutex
);
9092 intel_unpin_fb_obj(work
->old_fb_obj
);
9093 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
9094 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
9096 intel_update_fbc(dev
);
9097 mutex_unlock(&dev
->struct_mutex
);
9099 intel_frontbuffer_flip_complete(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
9101 BUG_ON(atomic_read(&to_intel_crtc(work
->crtc
)->unpin_work_count
) == 0);
9102 atomic_dec(&to_intel_crtc(work
->crtc
)->unpin_work_count
);
9107 static void do_intel_finish_page_flip(struct drm_device
*dev
,
9108 struct drm_crtc
*crtc
)
9110 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9111 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9112 struct intel_unpin_work
*work
;
9113 unsigned long flags
;
9115 /* Ignore early vblank irqs */
9116 if (intel_crtc
== NULL
)
9119 spin_lock_irqsave(&dev
->event_lock
, flags
);
9120 work
= intel_crtc
->unpin_work
;
9122 /* Ensure we don't miss a work->pending update ... */
9125 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
9126 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9130 /* and that the unpin work is consistent wrt ->pending. */
9133 intel_crtc
->unpin_work
= NULL
;
9136 drm_send_vblank_event(dev
, intel_crtc
->pipe
, work
->event
);
9138 drm_crtc_vblank_put(crtc
);
9140 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9142 wake_up_all(&dev_priv
->pending_flip_queue
);
9144 queue_work(dev_priv
->wq
, &work
->work
);
9146 trace_i915_flip_complete(intel_crtc
->plane
, work
->pending_flip_obj
);
9149 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
9151 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9152 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
9154 do_intel_finish_page_flip(dev
, crtc
);
9157 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
9159 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9160 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
9162 do_intel_finish_page_flip(dev
, crtc
);
9165 /* Is 'a' after or equal to 'b'? */
9166 static bool g4x_flip_count_after_eq(u32 a
, u32 b
)
9168 return !((a
- b
) & 0x80000000);
9171 static bool page_flip_finished(struct intel_crtc
*crtc
)
9173 struct drm_device
*dev
= crtc
->base
.dev
;
9174 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9177 * The relevant registers doen't exist on pre-ctg.
9178 * As the flip done interrupt doesn't trigger for mmio
9179 * flips on gmch platforms, a flip count check isn't
9180 * really needed there. But since ctg has the registers,
9181 * include it in the check anyway.
9183 if (INTEL_INFO(dev
)->gen
< 5 && !IS_G4X(dev
))
9187 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9188 * used the same base address. In that case the mmio flip might
9189 * have completed, but the CS hasn't even executed the flip yet.
9191 * A flip count check isn't enough as the CS might have updated
9192 * the base address just after start of vblank, but before we
9193 * managed to process the interrupt. This means we'd complete the
9196 * Combining both checks should get us a good enough result. It may
9197 * still happen that the CS flip has been executed, but has not
9198 * yet actually completed. But in case the base address is the same
9199 * anyway, we don't really care.
9201 return (I915_READ(DSPSURFLIVE(crtc
->plane
)) & ~0xfff) ==
9202 crtc
->unpin_work
->gtt_offset
&&
9203 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc
->pipe
)),
9204 crtc
->unpin_work
->flip_count
);
9207 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
9209 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9210 struct intel_crtc
*intel_crtc
=
9211 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
9212 unsigned long flags
;
9214 /* NB: An MMIO update of the plane base pointer will also
9215 * generate a page-flip completion irq, i.e. every modeset
9216 * is also accompanied by a spurious intel_prepare_page_flip().
9218 spin_lock_irqsave(&dev
->event_lock
, flags
);
9219 if (intel_crtc
->unpin_work
&& page_flip_finished(intel_crtc
))
9220 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
9221 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9224 static inline void intel_mark_page_flip_active(struct intel_crtc
*intel_crtc
)
9226 /* Ensure that the work item is consistent when activating it ... */
9228 atomic_set(&intel_crtc
->unpin_work
->pending
, INTEL_FLIP_PENDING
);
9229 /* and that it is marked active as soon as the irq could fire. */
9233 static int intel_gen2_queue_flip(struct drm_device
*dev
,
9234 struct drm_crtc
*crtc
,
9235 struct drm_framebuffer
*fb
,
9236 struct drm_i915_gem_object
*obj
,
9237 struct intel_engine_cs
*ring
,
9240 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9244 ret
= intel_ring_begin(ring
, 6);
9248 /* Can't queue multiple flips, so wait for the previous
9249 * one to finish before executing the next.
9251 if (intel_crtc
->plane
)
9252 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
9254 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
9255 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
9256 intel_ring_emit(ring
, MI_NOOP
);
9257 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9258 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9259 intel_ring_emit(ring
, fb
->pitches
[0]);
9260 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9261 intel_ring_emit(ring
, 0); /* aux display base address, unused */
9263 intel_mark_page_flip_active(intel_crtc
);
9264 __intel_ring_advance(ring
);
9268 static int intel_gen3_queue_flip(struct drm_device
*dev
,
9269 struct drm_crtc
*crtc
,
9270 struct drm_framebuffer
*fb
,
9271 struct drm_i915_gem_object
*obj
,
9272 struct intel_engine_cs
*ring
,
9275 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9279 ret
= intel_ring_begin(ring
, 6);
9283 if (intel_crtc
->plane
)
9284 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
9286 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
9287 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
9288 intel_ring_emit(ring
, MI_NOOP
);
9289 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
9290 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9291 intel_ring_emit(ring
, fb
->pitches
[0]);
9292 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9293 intel_ring_emit(ring
, MI_NOOP
);
9295 intel_mark_page_flip_active(intel_crtc
);
9296 __intel_ring_advance(ring
);
9300 static int intel_gen4_queue_flip(struct drm_device
*dev
,
9301 struct drm_crtc
*crtc
,
9302 struct drm_framebuffer
*fb
,
9303 struct drm_i915_gem_object
*obj
,
9304 struct intel_engine_cs
*ring
,
9307 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9308 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9309 uint32_t pf
, pipesrc
;
9312 ret
= intel_ring_begin(ring
, 4);
9316 /* i965+ uses the linear or tiled offsets from the
9317 * Display Registers (which do not change across a page-flip)
9318 * so we need only reprogram the base address.
9320 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9321 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9322 intel_ring_emit(ring
, fb
->pitches
[0]);
9323 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
|
9326 /* XXX Enabling the panel-fitter across page-flip is so far
9327 * untested on non-native modes, so ignore it for now.
9328 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9331 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
9332 intel_ring_emit(ring
, pf
| pipesrc
);
9334 intel_mark_page_flip_active(intel_crtc
);
9335 __intel_ring_advance(ring
);
9339 static int intel_gen6_queue_flip(struct drm_device
*dev
,
9340 struct drm_crtc
*crtc
,
9341 struct drm_framebuffer
*fb
,
9342 struct drm_i915_gem_object
*obj
,
9343 struct intel_engine_cs
*ring
,
9346 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9347 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9348 uint32_t pf
, pipesrc
;
9351 ret
= intel_ring_begin(ring
, 4);
9355 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9356 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9357 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
9358 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9360 /* Contrary to the suggestions in the documentation,
9361 * "Enable Panel Fitter" does not seem to be required when page
9362 * flipping with a non-native mode, and worse causes a normal
9364 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9367 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
9368 intel_ring_emit(ring
, pf
| pipesrc
);
9370 intel_mark_page_flip_active(intel_crtc
);
9371 __intel_ring_advance(ring
);
9375 static int intel_gen7_queue_flip(struct drm_device
*dev
,
9376 struct drm_crtc
*crtc
,
9377 struct drm_framebuffer
*fb
,
9378 struct drm_i915_gem_object
*obj
,
9379 struct intel_engine_cs
*ring
,
9382 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9383 uint32_t plane_bit
= 0;
9386 switch (intel_crtc
->plane
) {
9388 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
9391 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
9394 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
9397 WARN_ONCE(1, "unknown plane in flip command\n");
9402 if (ring
->id
== RCS
) {
9405 * On Gen 8, SRM is now taking an extra dword to accommodate
9406 * 48bits addresses, and we need a NOOP for the batch size to
9414 * BSpec MI_DISPLAY_FLIP for IVB:
9415 * "The full packet must be contained within the same cache line."
9417 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9418 * cacheline, if we ever start emitting more commands before
9419 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9420 * then do the cacheline alignment, and finally emit the
9423 ret
= intel_ring_cacheline_align(ring
);
9427 ret
= intel_ring_begin(ring
, len
);
9431 /* Unmask the flip-done completion message. Note that the bspec says that
9432 * we should do this for both the BCS and RCS, and that we must not unmask
9433 * more than one flip event at any time (or ensure that one flip message
9434 * can be sent by waiting for flip-done prior to queueing new flips).
9435 * Experimentation says that BCS works despite DERRMR masking all
9436 * flip-done completion events and that unmasking all planes at once
9437 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9438 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9440 if (ring
->id
== RCS
) {
9441 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
9442 intel_ring_emit(ring
, DERRMR
);
9443 intel_ring_emit(ring
, ~(DERRMR_PIPEA_PRI_FLIP_DONE
|
9444 DERRMR_PIPEB_PRI_FLIP_DONE
|
9445 DERRMR_PIPEC_PRI_FLIP_DONE
));
9447 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM_GEN8(1) |
9448 MI_SRM_LRM_GLOBAL_GTT
);
9450 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM(1) |
9451 MI_SRM_LRM_GLOBAL_GTT
);
9452 intel_ring_emit(ring
, DERRMR
);
9453 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
+ 256);
9455 intel_ring_emit(ring
, 0);
9456 intel_ring_emit(ring
, MI_NOOP
);
9460 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
9461 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
9462 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9463 intel_ring_emit(ring
, (MI_NOOP
));
9465 intel_mark_page_flip_active(intel_crtc
);
9466 __intel_ring_advance(ring
);
9470 static bool use_mmio_flip(struct intel_engine_cs
*ring
,
9471 struct drm_i915_gem_object
*obj
)
9474 * This is not being used for older platforms, because
9475 * non-availability of flip done interrupt forces us to use
9476 * CS flips. Older platforms derive flip done using some clever
9477 * tricks involving the flip_pending status bits and vblank irqs.
9478 * So using MMIO flips there would disrupt this mechanism.
9484 if (INTEL_INFO(ring
->dev
)->gen
< 5)
9487 if (i915
.use_mmio_flip
< 0)
9489 else if (i915
.use_mmio_flip
> 0)
9492 return ring
!= obj
->ring
;
9495 static void intel_do_mmio_flip(struct intel_crtc
*intel_crtc
)
9497 struct drm_device
*dev
= intel_crtc
->base
.dev
;
9498 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9499 struct intel_framebuffer
*intel_fb
=
9500 to_intel_framebuffer(intel_crtc
->base
.primary
->fb
);
9501 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
9505 intel_mark_page_flip_active(intel_crtc
);
9507 reg
= DSPCNTR(intel_crtc
->plane
);
9508 dspcntr
= I915_READ(reg
);
9510 if (INTEL_INFO(dev
)->gen
>= 4) {
9511 if (obj
->tiling_mode
!= I915_TILING_NONE
)
9512 dspcntr
|= DISPPLANE_TILED
;
9514 dspcntr
&= ~DISPPLANE_TILED
;
9516 I915_WRITE(reg
, dspcntr
);
9518 I915_WRITE(DSPSURF(intel_crtc
->plane
),
9519 intel_crtc
->unpin_work
->gtt_offset
);
9520 POSTING_READ(DSPSURF(intel_crtc
->plane
));
9523 static int intel_postpone_flip(struct drm_i915_gem_object
*obj
)
9525 struct intel_engine_cs
*ring
;
9528 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
9530 if (!obj
->last_write_seqno
)
9535 if (i915_seqno_passed(ring
->get_seqno(ring
, true),
9536 obj
->last_write_seqno
))
9539 ret
= i915_gem_check_olr(ring
, obj
->last_write_seqno
);
9543 if (WARN_ON(!ring
->irq_get(ring
)))
9549 void intel_notify_mmio_flip(struct intel_engine_cs
*ring
)
9551 struct drm_i915_private
*dev_priv
= to_i915(ring
->dev
);
9552 struct intel_crtc
*intel_crtc
;
9553 unsigned long irq_flags
;
9556 seqno
= ring
->get_seqno(ring
, false);
9558 spin_lock_irqsave(&dev_priv
->mmio_flip_lock
, irq_flags
);
9559 for_each_intel_crtc(ring
->dev
, intel_crtc
) {
9560 struct intel_mmio_flip
*mmio_flip
;
9562 mmio_flip
= &intel_crtc
->mmio_flip
;
9563 if (mmio_flip
->seqno
== 0)
9566 if (ring
->id
!= mmio_flip
->ring_id
)
9569 if (i915_seqno_passed(seqno
, mmio_flip
->seqno
)) {
9570 intel_do_mmio_flip(intel_crtc
);
9571 mmio_flip
->seqno
= 0;
9572 ring
->irq_put(ring
);
9575 spin_unlock_irqrestore(&dev_priv
->mmio_flip_lock
, irq_flags
);
9578 static int intel_queue_mmio_flip(struct drm_device
*dev
,
9579 struct drm_crtc
*crtc
,
9580 struct drm_framebuffer
*fb
,
9581 struct drm_i915_gem_object
*obj
,
9582 struct intel_engine_cs
*ring
,
9585 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9586 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9587 unsigned long irq_flags
;
9590 if (WARN_ON(intel_crtc
->mmio_flip
.seqno
))
9593 ret
= intel_postpone_flip(obj
);
9597 intel_do_mmio_flip(intel_crtc
);
9601 spin_lock_irqsave(&dev_priv
->mmio_flip_lock
, irq_flags
);
9602 intel_crtc
->mmio_flip
.seqno
= obj
->last_write_seqno
;
9603 intel_crtc
->mmio_flip
.ring_id
= obj
->ring
->id
;
9604 spin_unlock_irqrestore(&dev_priv
->mmio_flip_lock
, irq_flags
);
9607 * Double check to catch cases where irq fired before
9608 * mmio flip data was ready
9610 intel_notify_mmio_flip(obj
->ring
);
9614 static int intel_default_queue_flip(struct drm_device
*dev
,
9615 struct drm_crtc
*crtc
,
9616 struct drm_framebuffer
*fb
,
9617 struct drm_i915_gem_object
*obj
,
9618 struct intel_engine_cs
*ring
,
9624 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
9625 struct drm_framebuffer
*fb
,
9626 struct drm_pending_vblank_event
*event
,
9627 uint32_t page_flip_flags
)
9629 struct drm_device
*dev
= crtc
->dev
;
9630 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9631 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
9632 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
9633 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9634 enum pipe pipe
= intel_crtc
->pipe
;
9635 struct intel_unpin_work
*work
;
9636 struct intel_engine_cs
*ring
;
9637 unsigned long flags
;
9641 * drm_mode_page_flip_ioctl() should already catch this, but double
9642 * check to be safe. In the future we may enable pageflipping from
9643 * a disabled primary plane.
9645 if (WARN_ON(intel_fb_obj(old_fb
) == NULL
))
9648 /* Can't change pixel format via MI display flips. */
9649 if (fb
->pixel_format
!= crtc
->primary
->fb
->pixel_format
)
9653 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9654 * Note that pitch changes could also affect these register.
9656 if (INTEL_INFO(dev
)->gen
> 3 &&
9657 (fb
->offsets
[0] != crtc
->primary
->fb
->offsets
[0] ||
9658 fb
->pitches
[0] != crtc
->primary
->fb
->pitches
[0]))
9661 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
9664 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
9668 work
->event
= event
;
9670 work
->old_fb_obj
= intel_fb_obj(old_fb
);
9671 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
9673 ret
= drm_crtc_vblank_get(crtc
);
9677 /* We borrow the event spin lock for protecting unpin_work */
9678 spin_lock_irqsave(&dev
->event_lock
, flags
);
9679 if (intel_crtc
->unpin_work
) {
9680 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9682 drm_crtc_vblank_put(crtc
);
9684 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9687 intel_crtc
->unpin_work
= work
;
9688 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9690 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
9691 flush_workqueue(dev_priv
->wq
);
9693 ret
= i915_mutex_lock_interruptible(dev
);
9697 /* Reference the objects for the scheduled work. */
9698 drm_gem_object_reference(&work
->old_fb_obj
->base
);
9699 drm_gem_object_reference(&obj
->base
);
9701 crtc
->primary
->fb
= fb
;
9703 work
->pending_flip_obj
= obj
;
9705 work
->enable_stall_check
= true;
9707 atomic_inc(&intel_crtc
->unpin_work_count
);
9708 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
9710 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
9711 work
->flip_count
= I915_READ(PIPE_FLIPCOUNT_GM45(pipe
)) + 1;
9713 if (IS_VALLEYVIEW(dev
)) {
9714 ring
= &dev_priv
->ring
[BCS
];
9715 if (obj
->tiling_mode
!= work
->old_fb_obj
->tiling_mode
)
9716 /* vlv: DISPLAY_FLIP fails to change tiling */
9718 } else if (IS_IVYBRIDGE(dev
)) {
9719 ring
= &dev_priv
->ring
[BCS
];
9720 } else if (INTEL_INFO(dev
)->gen
>= 7) {
9722 if (ring
== NULL
|| ring
->id
!= RCS
)
9723 ring
= &dev_priv
->ring
[BCS
];
9725 ring
= &dev_priv
->ring
[RCS
];
9728 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
9730 goto cleanup_pending
;
9733 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
;
9735 if (use_mmio_flip(ring
, obj
))
9736 ret
= intel_queue_mmio_flip(dev
, crtc
, fb
, obj
, ring
,
9739 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
, ring
,
9744 i915_gem_track_fb(work
->old_fb_obj
, obj
,
9745 INTEL_FRONTBUFFER_PRIMARY(pipe
));
9747 intel_disable_fbc(dev
);
9748 intel_frontbuffer_flip_prepare(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
9749 mutex_unlock(&dev
->struct_mutex
);
9751 trace_i915_flip_request(intel_crtc
->plane
, obj
);
9756 intel_unpin_fb_obj(obj
);
9758 atomic_dec(&intel_crtc
->unpin_work_count
);
9759 crtc
->primary
->fb
= old_fb
;
9760 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
9761 drm_gem_object_unreference(&obj
->base
);
9762 mutex_unlock(&dev
->struct_mutex
);
9765 spin_lock_irqsave(&dev
->event_lock
, flags
);
9766 intel_crtc
->unpin_work
= NULL
;
9767 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9769 drm_crtc_vblank_put(crtc
);
9775 intel_crtc_wait_for_pending_flips(crtc
);
9776 ret
= intel_pipe_set_base(crtc
, crtc
->x
, crtc
->y
, fb
);
9777 if (ret
== 0 && event
)
9778 drm_send_vblank_event(dev
, pipe
, event
);
9783 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
9784 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
9785 .load_lut
= intel_crtc_load_lut
,
9789 * intel_modeset_update_staged_output_state
9791 * Updates the staged output configuration state, e.g. after we've read out the
9794 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
9796 struct intel_crtc
*crtc
;
9797 struct intel_encoder
*encoder
;
9798 struct intel_connector
*connector
;
9800 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9802 connector
->new_encoder
=
9803 to_intel_encoder(connector
->base
.encoder
);
9806 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9809 to_intel_crtc(encoder
->base
.crtc
);
9812 for_each_intel_crtc(dev
, crtc
) {
9813 crtc
->new_enabled
= crtc
->base
.enabled
;
9815 if (crtc
->new_enabled
)
9816 crtc
->new_config
= &crtc
->config
;
9818 crtc
->new_config
= NULL
;
9823 * intel_modeset_commit_output_state
9825 * This function copies the stage display pipe configuration to the real one.
9827 static void intel_modeset_commit_output_state(struct drm_device
*dev
)
9829 struct intel_crtc
*crtc
;
9830 struct intel_encoder
*encoder
;
9831 struct intel_connector
*connector
;
9833 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9835 connector
->base
.encoder
= &connector
->new_encoder
->base
;
9838 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9840 encoder
->base
.crtc
= &encoder
->new_crtc
->base
;
9843 for_each_intel_crtc(dev
, crtc
) {
9844 crtc
->base
.enabled
= crtc
->new_enabled
;
9849 connected_sink_compute_bpp(struct intel_connector
*connector
,
9850 struct intel_crtc_config
*pipe_config
)
9852 int bpp
= pipe_config
->pipe_bpp
;
9854 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9855 connector
->base
.base
.id
,
9856 connector
->base
.name
);
9858 /* Don't use an invalid EDID bpc value */
9859 if (connector
->base
.display_info
.bpc
&&
9860 connector
->base
.display_info
.bpc
* 3 < bpp
) {
9861 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9862 bpp
, connector
->base
.display_info
.bpc
*3);
9863 pipe_config
->pipe_bpp
= connector
->base
.display_info
.bpc
*3;
9866 /* Clamp bpp to 8 on screens without EDID 1.4 */
9867 if (connector
->base
.display_info
.bpc
== 0 && bpp
> 24) {
9868 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9870 pipe_config
->pipe_bpp
= 24;
9875 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
9876 struct drm_framebuffer
*fb
,
9877 struct intel_crtc_config
*pipe_config
)
9879 struct drm_device
*dev
= crtc
->base
.dev
;
9880 struct intel_connector
*connector
;
9883 switch (fb
->pixel_format
) {
9885 bpp
= 8*3; /* since we go through a colormap */
9887 case DRM_FORMAT_XRGB1555
:
9888 case DRM_FORMAT_ARGB1555
:
9889 /* checked in intel_framebuffer_init already */
9890 if (WARN_ON(INTEL_INFO(dev
)->gen
> 3))
9892 case DRM_FORMAT_RGB565
:
9893 bpp
= 6*3; /* min is 18bpp */
9895 case DRM_FORMAT_XBGR8888
:
9896 case DRM_FORMAT_ABGR8888
:
9897 /* checked in intel_framebuffer_init already */
9898 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
9900 case DRM_FORMAT_XRGB8888
:
9901 case DRM_FORMAT_ARGB8888
:
9904 case DRM_FORMAT_XRGB2101010
:
9905 case DRM_FORMAT_ARGB2101010
:
9906 case DRM_FORMAT_XBGR2101010
:
9907 case DRM_FORMAT_ABGR2101010
:
9908 /* checked in intel_framebuffer_init already */
9909 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
9913 /* TODO: gen4+ supports 16 bpc floating point, too. */
9915 DRM_DEBUG_KMS("unsupported depth\n");
9919 pipe_config
->pipe_bpp
= bpp
;
9921 /* Clamp display bpp to EDID value */
9922 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9924 if (!connector
->new_encoder
||
9925 connector
->new_encoder
->new_crtc
!= crtc
)
9928 connected_sink_compute_bpp(connector
, pipe_config
);
9934 static void intel_dump_crtc_timings(const struct drm_display_mode
*mode
)
9936 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9937 "type: 0x%x flags: 0x%x\n",
9939 mode
->crtc_hdisplay
, mode
->crtc_hsync_start
,
9940 mode
->crtc_hsync_end
, mode
->crtc_htotal
,
9941 mode
->crtc_vdisplay
, mode
->crtc_vsync_start
,
9942 mode
->crtc_vsync_end
, mode
->crtc_vtotal
, mode
->type
, mode
->flags
);
9945 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
9946 struct intel_crtc_config
*pipe_config
,
9947 const char *context
)
9949 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc
->base
.base
.id
,
9950 context
, pipe_name(crtc
->pipe
));
9952 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config
->cpu_transcoder
));
9953 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9954 pipe_config
->pipe_bpp
, pipe_config
->dither
);
9955 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9956 pipe_config
->has_pch_encoder
,
9957 pipe_config
->fdi_lanes
,
9958 pipe_config
->fdi_m_n
.gmch_m
, pipe_config
->fdi_m_n
.gmch_n
,
9959 pipe_config
->fdi_m_n
.link_m
, pipe_config
->fdi_m_n
.link_n
,
9960 pipe_config
->fdi_m_n
.tu
);
9961 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9962 pipe_config
->has_dp_encoder
,
9963 pipe_config
->dp_m_n
.gmch_m
, pipe_config
->dp_m_n
.gmch_n
,
9964 pipe_config
->dp_m_n
.link_m
, pipe_config
->dp_m_n
.link_n
,
9965 pipe_config
->dp_m_n
.tu
);
9966 DRM_DEBUG_KMS("requested mode:\n");
9967 drm_mode_debug_printmodeline(&pipe_config
->requested_mode
);
9968 DRM_DEBUG_KMS("adjusted mode:\n");
9969 drm_mode_debug_printmodeline(&pipe_config
->adjusted_mode
);
9970 intel_dump_crtc_timings(&pipe_config
->adjusted_mode
);
9971 DRM_DEBUG_KMS("port clock: %d\n", pipe_config
->port_clock
);
9972 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9973 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
9974 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9975 pipe_config
->gmch_pfit
.control
,
9976 pipe_config
->gmch_pfit
.pgm_ratios
,
9977 pipe_config
->gmch_pfit
.lvds_border_bits
);
9978 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9979 pipe_config
->pch_pfit
.pos
,
9980 pipe_config
->pch_pfit
.size
,
9981 pipe_config
->pch_pfit
.enabled
? "enabled" : "disabled");
9982 DRM_DEBUG_KMS("ips: %i\n", pipe_config
->ips_enabled
);
9983 DRM_DEBUG_KMS("double wide: %i\n", pipe_config
->double_wide
);
9986 static bool encoders_cloneable(const struct intel_encoder
*a
,
9987 const struct intel_encoder
*b
)
9989 /* masks could be asymmetric, so check both ways */
9990 return a
== b
|| (a
->cloneable
& (1 << b
->type
) &&
9991 b
->cloneable
& (1 << a
->type
));
9994 static bool check_single_encoder_cloning(struct intel_crtc
*crtc
,
9995 struct intel_encoder
*encoder
)
9997 struct drm_device
*dev
= crtc
->base
.dev
;
9998 struct intel_encoder
*source_encoder
;
10000 list_for_each_entry(source_encoder
,
10001 &dev
->mode_config
.encoder_list
, base
.head
) {
10002 if (source_encoder
->new_crtc
!= crtc
)
10005 if (!encoders_cloneable(encoder
, source_encoder
))
10012 static bool check_encoder_cloning(struct intel_crtc
*crtc
)
10014 struct drm_device
*dev
= crtc
->base
.dev
;
10015 struct intel_encoder
*encoder
;
10017 list_for_each_entry(encoder
,
10018 &dev
->mode_config
.encoder_list
, base
.head
) {
10019 if (encoder
->new_crtc
!= crtc
)
10022 if (!check_single_encoder_cloning(crtc
, encoder
))
10029 static struct intel_crtc_config
*
10030 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
10031 struct drm_framebuffer
*fb
,
10032 struct drm_display_mode
*mode
)
10034 struct drm_device
*dev
= crtc
->dev
;
10035 struct intel_encoder
*encoder
;
10036 struct intel_crtc_config
*pipe_config
;
10037 int plane_bpp
, ret
= -EINVAL
;
10040 if (!check_encoder_cloning(to_intel_crtc(crtc
))) {
10041 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10042 return ERR_PTR(-EINVAL
);
10045 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
10047 return ERR_PTR(-ENOMEM
);
10049 drm_mode_copy(&pipe_config
->adjusted_mode
, mode
);
10050 drm_mode_copy(&pipe_config
->requested_mode
, mode
);
10052 pipe_config
->cpu_transcoder
=
10053 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
10054 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
10057 * Sanitize sync polarity flags based on requested ones. If neither
10058 * positive or negative polarity is requested, treat this as meaning
10059 * negative polarity.
10061 if (!(pipe_config
->adjusted_mode
.flags
&
10062 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
10063 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
10065 if (!(pipe_config
->adjusted_mode
.flags
&
10066 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
10067 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
10069 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10070 * plane pixel format and any sink constraints into account. Returns the
10071 * source plane bpp so that dithering can be selected on mismatches
10072 * after encoders and crtc also have had their say. */
10073 plane_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
10079 * Determine the real pipe dimensions. Note that stereo modes can
10080 * increase the actual pipe size due to the frame doubling and
10081 * insertion of additional space for blanks between the frame. This
10082 * is stored in the crtc timings. We use the requested mode to do this
10083 * computation to clearly distinguish it from the adjusted mode, which
10084 * can be changed by the connectors in the below retry loop.
10086 drm_mode_set_crtcinfo(&pipe_config
->requested_mode
, CRTC_STEREO_DOUBLE
);
10087 pipe_config
->pipe_src_w
= pipe_config
->requested_mode
.crtc_hdisplay
;
10088 pipe_config
->pipe_src_h
= pipe_config
->requested_mode
.crtc_vdisplay
;
10091 /* Ensure the port clock defaults are reset when retrying. */
10092 pipe_config
->port_clock
= 0;
10093 pipe_config
->pixel_multiplier
= 1;
10095 /* Fill in default crtc timings, allow encoders to overwrite them. */
10096 drm_mode_set_crtcinfo(&pipe_config
->adjusted_mode
, CRTC_STEREO_DOUBLE
);
10098 /* Pass our mode to the connectors and the CRTC to give them a chance to
10099 * adjust it according to limitations or connector properties, and also
10100 * a chance to reject the mode entirely.
10102 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
10105 if (&encoder
->new_crtc
->base
!= crtc
)
10108 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
10109 DRM_DEBUG_KMS("Encoder config failure\n");
10114 /* Set default port clock if not overwritten by the encoder. Needs to be
10115 * done afterwards in case the encoder adjusts the mode. */
10116 if (!pipe_config
->port_clock
)
10117 pipe_config
->port_clock
= pipe_config
->adjusted_mode
.crtc_clock
10118 * pipe_config
->pixel_multiplier
;
10120 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
10122 DRM_DEBUG_KMS("CRTC fixup failed\n");
10126 if (ret
== RETRY
) {
10127 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
10132 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10134 goto encoder_retry
;
10137 pipe_config
->dither
= pipe_config
->pipe_bpp
!= plane_bpp
;
10138 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10139 plane_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
10141 return pipe_config
;
10143 kfree(pipe_config
);
10144 return ERR_PTR(ret
);
10147 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10148 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10150 intel_modeset_affected_pipes(struct drm_crtc
*crtc
, unsigned *modeset_pipes
,
10151 unsigned *prepare_pipes
, unsigned *disable_pipes
)
10153 struct intel_crtc
*intel_crtc
;
10154 struct drm_device
*dev
= crtc
->dev
;
10155 struct intel_encoder
*encoder
;
10156 struct intel_connector
*connector
;
10157 struct drm_crtc
*tmp_crtc
;
10159 *disable_pipes
= *modeset_pipes
= *prepare_pipes
= 0;
10161 /* Check which crtcs have changed outputs connected to them, these need
10162 * to be part of the prepare_pipes mask. We don't (yet) support global
10163 * modeset across multiple crtcs, so modeset_pipes will only have one
10164 * bit set at most. */
10165 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10167 if (connector
->base
.encoder
== &connector
->new_encoder
->base
)
10170 if (connector
->base
.encoder
) {
10171 tmp_crtc
= connector
->base
.encoder
->crtc
;
10173 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
10176 if (connector
->new_encoder
)
10178 1 << connector
->new_encoder
->new_crtc
->pipe
;
10181 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
10183 if (encoder
->base
.crtc
== &encoder
->new_crtc
->base
)
10186 if (encoder
->base
.crtc
) {
10187 tmp_crtc
= encoder
->base
.crtc
;
10189 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
10192 if (encoder
->new_crtc
)
10193 *prepare_pipes
|= 1 << encoder
->new_crtc
->pipe
;
10196 /* Check for pipes that will be enabled/disabled ... */
10197 for_each_intel_crtc(dev
, intel_crtc
) {
10198 if (intel_crtc
->base
.enabled
== intel_crtc
->new_enabled
)
10201 if (!intel_crtc
->new_enabled
)
10202 *disable_pipes
|= 1 << intel_crtc
->pipe
;
10204 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
10208 /* set_mode is also used to update properties on life display pipes. */
10209 intel_crtc
= to_intel_crtc(crtc
);
10210 if (intel_crtc
->new_enabled
)
10211 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
10214 * For simplicity do a full modeset on any pipe where the output routing
10215 * changed. We could be more clever, but that would require us to be
10216 * more careful with calling the relevant encoder->mode_set functions.
10218 if (*prepare_pipes
)
10219 *modeset_pipes
= *prepare_pipes
;
10221 /* ... and mask these out. */
10222 *modeset_pipes
&= ~(*disable_pipes
);
10223 *prepare_pipes
&= ~(*disable_pipes
);
10226 * HACK: We don't (yet) fully support global modesets. intel_set_config
10227 * obies this rule, but the modeset restore mode of
10228 * intel_modeset_setup_hw_state does not.
10230 *modeset_pipes
&= 1 << intel_crtc
->pipe
;
10231 *prepare_pipes
&= 1 << intel_crtc
->pipe
;
10233 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10234 *modeset_pipes
, *prepare_pipes
, *disable_pipes
);
10237 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
10239 struct drm_encoder
*encoder
;
10240 struct drm_device
*dev
= crtc
->dev
;
10242 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
10243 if (encoder
->crtc
== crtc
)
10250 intel_modeset_update_state(struct drm_device
*dev
, unsigned prepare_pipes
)
10252 struct intel_encoder
*intel_encoder
;
10253 struct intel_crtc
*intel_crtc
;
10254 struct drm_connector
*connector
;
10256 list_for_each_entry(intel_encoder
, &dev
->mode_config
.encoder_list
,
10258 if (!intel_encoder
->base
.crtc
)
10261 intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
10263 if (prepare_pipes
& (1 << intel_crtc
->pipe
))
10264 intel_encoder
->connectors_active
= false;
10267 intel_modeset_commit_output_state(dev
);
10269 /* Double check state. */
10270 for_each_intel_crtc(dev
, intel_crtc
) {
10271 WARN_ON(intel_crtc
->base
.enabled
!= intel_crtc_in_use(&intel_crtc
->base
));
10272 WARN_ON(intel_crtc
->new_config
&&
10273 intel_crtc
->new_config
!= &intel_crtc
->config
);
10274 WARN_ON(intel_crtc
->base
.enabled
!= !!intel_crtc
->new_config
);
10277 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
10278 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
10281 intel_crtc
= to_intel_crtc(connector
->encoder
->crtc
);
10283 if (prepare_pipes
& (1 << intel_crtc
->pipe
)) {
10284 struct drm_property
*dpms_property
=
10285 dev
->mode_config
.dpms_property
;
10287 connector
->dpms
= DRM_MODE_DPMS_ON
;
10288 drm_object_property_set_value(&connector
->base
,
10292 intel_encoder
= to_intel_encoder(connector
->encoder
);
10293 intel_encoder
->connectors_active
= true;
10299 static bool intel_fuzzy_clock_check(int clock1
, int clock2
)
10303 if (clock1
== clock2
)
10306 if (!clock1
|| !clock2
)
10309 diff
= abs(clock1
- clock2
);
10311 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
10317 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10318 list_for_each_entry((intel_crtc), \
10319 &(dev)->mode_config.crtc_list, \
10321 if (mask & (1 <<(intel_crtc)->pipe))
10324 intel_pipe_config_compare(struct drm_device
*dev
,
10325 struct intel_crtc_config
*current_config
,
10326 struct intel_crtc_config
*pipe_config
)
10328 #define PIPE_CONF_CHECK_X(name) \
10329 if (current_config->name != pipe_config->name) { \
10330 DRM_ERROR("mismatch in " #name " " \
10331 "(expected 0x%08x, found 0x%08x)\n", \
10332 current_config->name, \
10333 pipe_config->name); \
10337 #define PIPE_CONF_CHECK_I(name) \
10338 if (current_config->name != pipe_config->name) { \
10339 DRM_ERROR("mismatch in " #name " " \
10340 "(expected %i, found %i)\n", \
10341 current_config->name, \
10342 pipe_config->name); \
10346 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10347 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10348 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10349 "(expected %i, found %i)\n", \
10350 current_config->name & (mask), \
10351 pipe_config->name & (mask)); \
10355 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10356 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10357 DRM_ERROR("mismatch in " #name " " \
10358 "(expected %i, found %i)\n", \
10359 current_config->name, \
10360 pipe_config->name); \
10364 #define PIPE_CONF_QUIRK(quirk) \
10365 ((current_config->quirks | pipe_config->quirks) & (quirk))
10367 PIPE_CONF_CHECK_I(cpu_transcoder
);
10369 PIPE_CONF_CHECK_I(has_pch_encoder
);
10370 PIPE_CONF_CHECK_I(fdi_lanes
);
10371 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_m
);
10372 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_n
);
10373 PIPE_CONF_CHECK_I(fdi_m_n
.link_m
);
10374 PIPE_CONF_CHECK_I(fdi_m_n
.link_n
);
10375 PIPE_CONF_CHECK_I(fdi_m_n
.tu
);
10377 PIPE_CONF_CHECK_I(has_dp_encoder
);
10378 PIPE_CONF_CHECK_I(dp_m_n
.gmch_m
);
10379 PIPE_CONF_CHECK_I(dp_m_n
.gmch_n
);
10380 PIPE_CONF_CHECK_I(dp_m_n
.link_m
);
10381 PIPE_CONF_CHECK_I(dp_m_n
.link_n
);
10382 PIPE_CONF_CHECK_I(dp_m_n
.tu
);
10384 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hdisplay
);
10385 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_htotal
);
10386 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_start
);
10387 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_end
);
10388 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_start
);
10389 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_end
);
10391 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vdisplay
);
10392 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vtotal
);
10393 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_start
);
10394 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_end
);
10395 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_start
);
10396 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_end
);
10398 PIPE_CONF_CHECK_I(pixel_multiplier
);
10399 PIPE_CONF_CHECK_I(has_hdmi_sink
);
10400 if ((INTEL_INFO(dev
)->gen
< 8 && !IS_HASWELL(dev
)) ||
10401 IS_VALLEYVIEW(dev
))
10402 PIPE_CONF_CHECK_I(limited_color_range
);
10404 PIPE_CONF_CHECK_I(has_audio
);
10406 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10407 DRM_MODE_FLAG_INTERLACE
);
10409 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
10410 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10411 DRM_MODE_FLAG_PHSYNC
);
10412 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10413 DRM_MODE_FLAG_NHSYNC
);
10414 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10415 DRM_MODE_FLAG_PVSYNC
);
10416 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10417 DRM_MODE_FLAG_NVSYNC
);
10420 PIPE_CONF_CHECK_I(pipe_src_w
);
10421 PIPE_CONF_CHECK_I(pipe_src_h
);
10424 * FIXME: BIOS likes to set up a cloned config with lvds+external
10425 * screen. Since we don't yet re-compute the pipe config when moving
10426 * just the lvds port away to another pipe the sw tracking won't match.
10428 * Proper atomic modesets with recomputed global state will fix this.
10429 * Until then just don't check gmch state for inherited modes.
10431 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE
)) {
10432 PIPE_CONF_CHECK_I(gmch_pfit
.control
);
10433 /* pfit ratios are autocomputed by the hw on gen4+ */
10434 if (INTEL_INFO(dev
)->gen
< 4)
10435 PIPE_CONF_CHECK_I(gmch_pfit
.pgm_ratios
);
10436 PIPE_CONF_CHECK_I(gmch_pfit
.lvds_border_bits
);
10439 PIPE_CONF_CHECK_I(pch_pfit
.enabled
);
10440 if (current_config
->pch_pfit
.enabled
) {
10441 PIPE_CONF_CHECK_I(pch_pfit
.pos
);
10442 PIPE_CONF_CHECK_I(pch_pfit
.size
);
10445 /* BDW+ don't expose a synchronous way to read the state */
10446 if (IS_HASWELL(dev
))
10447 PIPE_CONF_CHECK_I(ips_enabled
);
10449 PIPE_CONF_CHECK_I(double_wide
);
10451 PIPE_CONF_CHECK_X(ddi_pll_sel
);
10453 PIPE_CONF_CHECK_I(shared_dpll
);
10454 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
10455 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
10456 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
10457 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
10458 PIPE_CONF_CHECK_X(dpll_hw_state
.wrpll
);
10460 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5)
10461 PIPE_CONF_CHECK_I(pipe_bpp
);
10463 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode
.crtc_clock
);
10464 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
10466 #undef PIPE_CONF_CHECK_X
10467 #undef PIPE_CONF_CHECK_I
10468 #undef PIPE_CONF_CHECK_FLAGS
10469 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10470 #undef PIPE_CONF_QUIRK
10476 check_connector_state(struct drm_device
*dev
)
10478 struct intel_connector
*connector
;
10480 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10482 /* This also checks the encoder/connector hw state with the
10483 * ->get_hw_state callbacks. */
10484 intel_connector_check_state(connector
);
10486 WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
10487 "connector's staged encoder doesn't match current encoder\n");
10492 check_encoder_state(struct drm_device
*dev
)
10494 struct intel_encoder
*encoder
;
10495 struct intel_connector
*connector
;
10497 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
10499 bool enabled
= false;
10500 bool active
= false;
10501 enum pipe pipe
, tracked_pipe
;
10503 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10504 encoder
->base
.base
.id
,
10505 encoder
->base
.name
);
10507 WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
10508 "encoder's stage crtc doesn't match current crtc\n");
10509 WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
10510 "encoder's active_connectors set, but no crtc\n");
10512 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10514 if (connector
->base
.encoder
!= &encoder
->base
)
10517 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
10520 WARN(!!encoder
->base
.crtc
!= enabled
,
10521 "encoder's enabled state mismatch "
10522 "(expected %i, found %i)\n",
10523 !!encoder
->base
.crtc
, enabled
);
10524 WARN(active
&& !encoder
->base
.crtc
,
10525 "active encoder with no crtc\n");
10527 WARN(encoder
->connectors_active
!= active
,
10528 "encoder's computed active state doesn't match tracked active state "
10529 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
10531 active
= encoder
->get_hw_state(encoder
, &pipe
);
10532 WARN(active
!= encoder
->connectors_active
,
10533 "encoder's hw state doesn't match sw tracking "
10534 "(expected %i, found %i)\n",
10535 encoder
->connectors_active
, active
);
10537 if (!encoder
->base
.crtc
)
10540 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
10541 WARN(active
&& pipe
!= tracked_pipe
,
10542 "active encoder's pipe doesn't match"
10543 "(expected %i, found %i)\n",
10544 tracked_pipe
, pipe
);
10550 check_crtc_state(struct drm_device
*dev
)
10552 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10553 struct intel_crtc
*crtc
;
10554 struct intel_encoder
*encoder
;
10555 struct intel_crtc_config pipe_config
;
10557 for_each_intel_crtc(dev
, crtc
) {
10558 bool enabled
= false;
10559 bool active
= false;
10561 memset(&pipe_config
, 0, sizeof(pipe_config
));
10563 DRM_DEBUG_KMS("[CRTC:%d]\n",
10564 crtc
->base
.base
.id
);
10566 WARN(crtc
->active
&& !crtc
->base
.enabled
,
10567 "active crtc, but not enabled in sw tracking\n");
10569 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
10571 if (encoder
->base
.crtc
!= &crtc
->base
)
10574 if (encoder
->connectors_active
)
10578 WARN(active
!= crtc
->active
,
10579 "crtc's computed active state doesn't match tracked active state "
10580 "(expected %i, found %i)\n", active
, crtc
->active
);
10581 WARN(enabled
!= crtc
->base
.enabled
,
10582 "crtc's computed enabled state doesn't match tracked enabled state "
10583 "(expected %i, found %i)\n", enabled
, crtc
->base
.enabled
);
10585 active
= dev_priv
->display
.get_pipe_config(crtc
,
10588 /* hw state is inconsistent with the pipe A quirk */
10589 if (crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
10590 active
= crtc
->active
;
10592 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
10595 if (encoder
->base
.crtc
!= &crtc
->base
)
10597 if (encoder
->get_hw_state(encoder
, &pipe
))
10598 encoder
->get_config(encoder
, &pipe_config
);
10601 WARN(crtc
->active
!= active
,
10602 "crtc active state doesn't match with hw state "
10603 "(expected %i, found %i)\n", crtc
->active
, active
);
10606 !intel_pipe_config_compare(dev
, &crtc
->config
, &pipe_config
)) {
10607 WARN(1, "pipe state doesn't match!\n");
10608 intel_dump_pipe_config(crtc
, &pipe_config
,
10610 intel_dump_pipe_config(crtc
, &crtc
->config
,
10617 check_shared_dpll_state(struct drm_device
*dev
)
10619 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10620 struct intel_crtc
*crtc
;
10621 struct intel_dpll_hw_state dpll_hw_state
;
10624 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
10625 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
10626 int enabled_crtcs
= 0, active_crtcs
= 0;
10629 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
10631 DRM_DEBUG_KMS("%s\n", pll
->name
);
10633 active
= pll
->get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
10635 WARN(pll
->active
> pll
->refcount
,
10636 "more active pll users than references: %i vs %i\n",
10637 pll
->active
, pll
->refcount
);
10638 WARN(pll
->active
&& !pll
->on
,
10639 "pll in active use but not on in sw tracking\n");
10640 WARN(pll
->on
&& !pll
->active
,
10641 "pll in on but not on in use in sw tracking\n");
10642 WARN(pll
->on
!= active
,
10643 "pll on state mismatch (expected %i, found %i)\n",
10646 for_each_intel_crtc(dev
, crtc
) {
10647 if (crtc
->base
.enabled
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
10649 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
10652 WARN(pll
->active
!= active_crtcs
,
10653 "pll active crtcs mismatch (expected %i, found %i)\n",
10654 pll
->active
, active_crtcs
);
10655 WARN(pll
->refcount
!= enabled_crtcs
,
10656 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10657 pll
->refcount
, enabled_crtcs
);
10659 WARN(pll
->on
&& memcmp(&pll
->hw_state
, &dpll_hw_state
,
10660 sizeof(dpll_hw_state
)),
10661 "pll hw state mismatch\n");
10666 intel_modeset_check_state(struct drm_device
*dev
)
10668 check_connector_state(dev
);
10669 check_encoder_state(dev
);
10670 check_crtc_state(dev
);
10671 check_shared_dpll_state(dev
);
10674 void ironlake_check_encoder_dotclock(const struct intel_crtc_config
*pipe_config
,
10678 * FDI already provided one idea for the dotclock.
10679 * Yell if the encoder disagrees.
10681 WARN(!intel_fuzzy_clock_check(pipe_config
->adjusted_mode
.crtc_clock
, dotclock
),
10682 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10683 pipe_config
->adjusted_mode
.crtc_clock
, dotclock
);
10686 static void update_scanline_offset(struct intel_crtc
*crtc
)
10688 struct drm_device
*dev
= crtc
->base
.dev
;
10691 * The scanline counter increments at the leading edge of hsync.
10693 * On most platforms it starts counting from vtotal-1 on the
10694 * first active line. That means the scanline counter value is
10695 * always one less than what we would expect. Ie. just after
10696 * start of vblank, which also occurs at start of hsync (on the
10697 * last active line), the scanline counter will read vblank_start-1.
10699 * On gen2 the scanline counter starts counting from 1 instead
10700 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10701 * to keep the value positive), instead of adding one.
10703 * On HSW+ the behaviour of the scanline counter depends on the output
10704 * type. For DP ports it behaves like most other platforms, but on HDMI
10705 * there's an extra 1 line difference. So we need to add two instead of
10706 * one to the value.
10708 if (IS_GEN2(dev
)) {
10709 const struct drm_display_mode
*mode
= &crtc
->config
.adjusted_mode
;
10712 vtotal
= mode
->crtc_vtotal
;
10713 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
10716 crtc
->scanline_offset
= vtotal
- 1;
10717 } else if (HAS_DDI(dev
) &&
10718 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
)) {
10719 crtc
->scanline_offset
= 2;
10721 crtc
->scanline_offset
= 1;
10724 static int __intel_set_mode(struct drm_crtc
*crtc
,
10725 struct drm_display_mode
*mode
,
10726 int x
, int y
, struct drm_framebuffer
*fb
)
10728 struct drm_device
*dev
= crtc
->dev
;
10729 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10730 struct drm_display_mode
*saved_mode
;
10731 struct intel_crtc_config
*pipe_config
= NULL
;
10732 struct intel_crtc
*intel_crtc
;
10733 unsigned disable_pipes
, prepare_pipes
, modeset_pipes
;
10736 saved_mode
= kmalloc(sizeof(*saved_mode
), GFP_KERNEL
);
10740 intel_modeset_affected_pipes(crtc
, &modeset_pipes
,
10741 &prepare_pipes
, &disable_pipes
);
10743 *saved_mode
= crtc
->mode
;
10745 /* Hack: Because we don't (yet) support global modeset on multiple
10746 * crtcs, we don't keep track of the new mode for more than one crtc.
10747 * Hence simply check whether any bit is set in modeset_pipes in all the
10748 * pieces of code that are not yet converted to deal with mutliple crtcs
10749 * changing their mode at the same time. */
10750 if (modeset_pipes
) {
10751 pipe_config
= intel_modeset_pipe_config(crtc
, fb
, mode
);
10752 if (IS_ERR(pipe_config
)) {
10753 ret
= PTR_ERR(pipe_config
);
10754 pipe_config
= NULL
;
10758 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,
10760 to_intel_crtc(crtc
)->new_config
= pipe_config
;
10764 * See if the config requires any additional preparation, e.g.
10765 * to adjust global state with pipes off. We need to do this
10766 * here so we can get the modeset_pipe updated config for the new
10767 * mode set on this crtc. For other crtcs we need to use the
10768 * adjusted_mode bits in the crtc directly.
10770 if (IS_VALLEYVIEW(dev
)) {
10771 valleyview_modeset_global_pipes(dev
, &prepare_pipes
);
10773 /* may have added more to prepare_pipes than we should */
10774 prepare_pipes
&= ~disable_pipes
;
10777 for_each_intel_crtc_masked(dev
, disable_pipes
, intel_crtc
)
10778 intel_crtc_disable(&intel_crtc
->base
);
10780 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
10781 if (intel_crtc
->base
.enabled
)
10782 dev_priv
->display
.crtc_disable(&intel_crtc
->base
);
10785 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10786 * to set it here already despite that we pass it down the callchain.
10788 if (modeset_pipes
) {
10789 crtc
->mode
= *mode
;
10790 /* mode_set/enable/disable functions rely on a correct pipe
10792 to_intel_crtc(crtc
)->config
= *pipe_config
;
10793 to_intel_crtc(crtc
)->new_config
= &to_intel_crtc(crtc
)->config
;
10796 * Calculate and store various constants which
10797 * are later needed by vblank and swap-completion
10798 * timestamping. They are derived from true hwmode.
10800 drm_calc_timestamping_constants(crtc
,
10801 &pipe_config
->adjusted_mode
);
10804 /* Only after disabling all output pipelines that will be changed can we
10805 * update the the output configuration. */
10806 intel_modeset_update_state(dev
, prepare_pipes
);
10808 if (dev_priv
->display
.modeset_global_resources
)
10809 dev_priv
->display
.modeset_global_resources(dev
);
10811 /* Set up the DPLL and any encoders state that needs to adjust or depend
10814 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
10815 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
10816 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(old_fb
);
10817 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
10819 mutex_lock(&dev
->struct_mutex
);
10820 ret
= intel_pin_and_fence_fb_obj(dev
,
10824 DRM_ERROR("pin & fence failed\n");
10825 mutex_unlock(&dev
->struct_mutex
);
10829 intel_unpin_fb_obj(old_obj
);
10830 i915_gem_track_fb(old_obj
, obj
,
10831 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
));
10832 mutex_unlock(&dev
->struct_mutex
);
10834 crtc
->primary
->fb
= fb
;
10838 ret
= dev_priv
->display
.crtc_mode_set(&intel_crtc
->base
,
10844 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10845 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
10846 update_scanline_offset(intel_crtc
);
10848 dev_priv
->display
.crtc_enable(&intel_crtc
->base
);
10851 /* FIXME: add subpixel order */
10853 if (ret
&& crtc
->enabled
)
10854 crtc
->mode
= *saved_mode
;
10857 kfree(pipe_config
);
10862 static int intel_set_mode(struct drm_crtc
*crtc
,
10863 struct drm_display_mode
*mode
,
10864 int x
, int y
, struct drm_framebuffer
*fb
)
10868 ret
= __intel_set_mode(crtc
, mode
, x
, y
, fb
);
10871 intel_modeset_check_state(crtc
->dev
);
10876 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
10878 intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
, crtc
->primary
->fb
);
10881 #undef for_each_intel_crtc_masked
10883 static void intel_set_config_free(struct intel_set_config
*config
)
10888 kfree(config
->save_connector_encoders
);
10889 kfree(config
->save_encoder_crtcs
);
10890 kfree(config
->save_crtc_enabled
);
10894 static int intel_set_config_save_state(struct drm_device
*dev
,
10895 struct intel_set_config
*config
)
10897 struct drm_crtc
*crtc
;
10898 struct drm_encoder
*encoder
;
10899 struct drm_connector
*connector
;
10902 config
->save_crtc_enabled
=
10903 kcalloc(dev
->mode_config
.num_crtc
,
10904 sizeof(bool), GFP_KERNEL
);
10905 if (!config
->save_crtc_enabled
)
10908 config
->save_encoder_crtcs
=
10909 kcalloc(dev
->mode_config
.num_encoder
,
10910 sizeof(struct drm_crtc
*), GFP_KERNEL
);
10911 if (!config
->save_encoder_crtcs
)
10914 config
->save_connector_encoders
=
10915 kcalloc(dev
->mode_config
.num_connector
,
10916 sizeof(struct drm_encoder
*), GFP_KERNEL
);
10917 if (!config
->save_connector_encoders
)
10920 /* Copy data. Note that driver private data is not affected.
10921 * Should anything bad happen only the expected state is
10922 * restored, not the drivers personal bookkeeping.
10925 for_each_crtc(dev
, crtc
) {
10926 config
->save_crtc_enabled
[count
++] = crtc
->enabled
;
10930 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
10931 config
->save_encoder_crtcs
[count
++] = encoder
->crtc
;
10935 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
10936 config
->save_connector_encoders
[count
++] = connector
->encoder
;
10942 static void intel_set_config_restore_state(struct drm_device
*dev
,
10943 struct intel_set_config
*config
)
10945 struct intel_crtc
*crtc
;
10946 struct intel_encoder
*encoder
;
10947 struct intel_connector
*connector
;
10951 for_each_intel_crtc(dev
, crtc
) {
10952 crtc
->new_enabled
= config
->save_crtc_enabled
[count
++];
10954 if (crtc
->new_enabled
)
10955 crtc
->new_config
= &crtc
->config
;
10957 crtc
->new_config
= NULL
;
10961 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
10962 encoder
->new_crtc
=
10963 to_intel_crtc(config
->save_encoder_crtcs
[count
++]);
10967 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
10968 connector
->new_encoder
=
10969 to_intel_encoder(config
->save_connector_encoders
[count
++]);
10974 is_crtc_connector_off(struct drm_mode_set
*set
)
10978 if (set
->num_connectors
== 0)
10981 if (WARN_ON(set
->connectors
== NULL
))
10984 for (i
= 0; i
< set
->num_connectors
; i
++)
10985 if (set
->connectors
[i
]->encoder
&&
10986 set
->connectors
[i
]->encoder
->crtc
== set
->crtc
&&
10987 set
->connectors
[i
]->dpms
!= DRM_MODE_DPMS_ON
)
10994 intel_set_config_compute_mode_changes(struct drm_mode_set
*set
,
10995 struct intel_set_config
*config
)
10998 /* We should be able to check here if the fb has the same properties
10999 * and then just flip_or_move it */
11000 if (is_crtc_connector_off(set
)) {
11001 config
->mode_changed
= true;
11002 } else if (set
->crtc
->primary
->fb
!= set
->fb
) {
11004 * If we have no fb, we can only flip as long as the crtc is
11005 * active, otherwise we need a full mode set. The crtc may
11006 * be active if we've only disabled the primary plane, or
11007 * in fastboot situations.
11009 if (set
->crtc
->primary
->fb
== NULL
) {
11010 struct intel_crtc
*intel_crtc
=
11011 to_intel_crtc(set
->crtc
);
11013 if (intel_crtc
->active
) {
11014 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11015 config
->fb_changed
= true;
11017 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11018 config
->mode_changed
= true;
11020 } else if (set
->fb
== NULL
) {
11021 config
->mode_changed
= true;
11022 } else if (set
->fb
->pixel_format
!=
11023 set
->crtc
->primary
->fb
->pixel_format
) {
11024 config
->mode_changed
= true;
11026 config
->fb_changed
= true;
11030 if (set
->fb
&& (set
->x
!= set
->crtc
->x
|| set
->y
!= set
->crtc
->y
))
11031 config
->fb_changed
= true;
11033 if (set
->mode
&& !drm_mode_equal(set
->mode
, &set
->crtc
->mode
)) {
11034 DRM_DEBUG_KMS("modes are different, full mode set\n");
11035 drm_mode_debug_printmodeline(&set
->crtc
->mode
);
11036 drm_mode_debug_printmodeline(set
->mode
);
11037 config
->mode_changed
= true;
11040 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11041 set
->crtc
->base
.id
, config
->mode_changed
, config
->fb_changed
);
11045 intel_modeset_stage_output_state(struct drm_device
*dev
,
11046 struct drm_mode_set
*set
,
11047 struct intel_set_config
*config
)
11049 struct intel_connector
*connector
;
11050 struct intel_encoder
*encoder
;
11051 struct intel_crtc
*crtc
;
11054 /* The upper layers ensure that we either disable a crtc or have a list
11055 * of connectors. For paranoia, double-check this. */
11056 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
11057 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
11059 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11061 /* Otherwise traverse passed in connector list and get encoders
11063 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
11064 if (set
->connectors
[ro
] == &connector
->base
) {
11065 connector
->new_encoder
= connector
->encoder
;
11070 /* If we disable the crtc, disable all its connectors. Also, if
11071 * the connector is on the changing crtc but not on the new
11072 * connector list, disable it. */
11073 if ((!set
->fb
|| ro
== set
->num_connectors
) &&
11074 connector
->base
.encoder
&&
11075 connector
->base
.encoder
->crtc
== set
->crtc
) {
11076 connector
->new_encoder
= NULL
;
11078 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11079 connector
->base
.base
.id
,
11080 connector
->base
.name
);
11084 if (&connector
->new_encoder
->base
!= connector
->base
.encoder
) {
11085 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11086 config
->mode_changed
= true;
11089 /* connector->new_encoder is now updated for all connectors. */
11091 /* Update crtc of enabled connectors. */
11092 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11094 struct drm_crtc
*new_crtc
;
11096 if (!connector
->new_encoder
)
11099 new_crtc
= connector
->new_encoder
->base
.crtc
;
11101 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
11102 if (set
->connectors
[ro
] == &connector
->base
)
11103 new_crtc
= set
->crtc
;
11106 /* Make sure the new CRTC will work with the encoder */
11107 if (!drm_encoder_crtc_ok(&connector
->new_encoder
->base
,
11111 connector
->encoder
->new_crtc
= to_intel_crtc(new_crtc
);
11113 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11114 connector
->base
.base
.id
,
11115 connector
->base
.name
,
11116 new_crtc
->base
.id
);
11119 /* Check for any encoders that needs to be disabled. */
11120 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
11122 int num_connectors
= 0;
11123 list_for_each_entry(connector
,
11124 &dev
->mode_config
.connector_list
,
11126 if (connector
->new_encoder
== encoder
) {
11127 WARN_ON(!connector
->new_encoder
->new_crtc
);
11132 if (num_connectors
== 0)
11133 encoder
->new_crtc
= NULL
;
11134 else if (num_connectors
> 1)
11137 /* Only now check for crtc changes so we don't miss encoders
11138 * that will be disabled. */
11139 if (&encoder
->new_crtc
->base
!= encoder
->base
.crtc
) {
11140 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11141 config
->mode_changed
= true;
11144 /* Now we've also updated encoder->new_crtc for all encoders. */
11146 for_each_intel_crtc(dev
, crtc
) {
11147 crtc
->new_enabled
= false;
11149 list_for_each_entry(encoder
,
11150 &dev
->mode_config
.encoder_list
,
11152 if (encoder
->new_crtc
== crtc
) {
11153 crtc
->new_enabled
= true;
11158 if (crtc
->new_enabled
!= crtc
->base
.enabled
) {
11159 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11160 crtc
->new_enabled
? "en" : "dis");
11161 config
->mode_changed
= true;
11164 if (crtc
->new_enabled
)
11165 crtc
->new_config
= &crtc
->config
;
11167 crtc
->new_config
= NULL
;
11173 static void disable_crtc_nofb(struct intel_crtc
*crtc
)
11175 struct drm_device
*dev
= crtc
->base
.dev
;
11176 struct intel_encoder
*encoder
;
11177 struct intel_connector
*connector
;
11179 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11180 pipe_name(crtc
->pipe
));
11182 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
11183 if (connector
->new_encoder
&&
11184 connector
->new_encoder
->new_crtc
== crtc
)
11185 connector
->new_encoder
= NULL
;
11188 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
11189 if (encoder
->new_crtc
== crtc
)
11190 encoder
->new_crtc
= NULL
;
11193 crtc
->new_enabled
= false;
11194 crtc
->new_config
= NULL
;
11197 static int intel_crtc_set_config(struct drm_mode_set
*set
)
11199 struct drm_device
*dev
;
11200 struct drm_mode_set save_set
;
11201 struct intel_set_config
*config
;
11205 BUG_ON(!set
->crtc
);
11206 BUG_ON(!set
->crtc
->helper_private
);
11208 /* Enforce sane interface api - has been abused by the fb helper. */
11209 BUG_ON(!set
->mode
&& set
->fb
);
11210 BUG_ON(set
->fb
&& set
->num_connectors
== 0);
11213 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11214 set
->crtc
->base
.id
, set
->fb
->base
.id
,
11215 (int)set
->num_connectors
, set
->x
, set
->y
);
11217 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
11220 dev
= set
->crtc
->dev
;
11223 config
= kzalloc(sizeof(*config
), GFP_KERNEL
);
11227 ret
= intel_set_config_save_state(dev
, config
);
11231 save_set
.crtc
= set
->crtc
;
11232 save_set
.mode
= &set
->crtc
->mode
;
11233 save_set
.x
= set
->crtc
->x
;
11234 save_set
.y
= set
->crtc
->y
;
11235 save_set
.fb
= set
->crtc
->primary
->fb
;
11237 /* Compute whether we need a full modeset, only an fb base update or no
11238 * change at all. In the future we might also check whether only the
11239 * mode changed, e.g. for LVDS where we only change the panel fitter in
11241 intel_set_config_compute_mode_changes(set
, config
);
11243 ret
= intel_modeset_stage_output_state(dev
, set
, config
);
11247 if (config
->mode_changed
) {
11248 ret
= intel_set_mode(set
->crtc
, set
->mode
,
11249 set
->x
, set
->y
, set
->fb
);
11250 } else if (config
->fb_changed
) {
11251 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11252 struct intel_crtc
*intel_crtc
= to_intel_crtc(set
->crtc
);
11254 intel_crtc_wait_for_pending_flips(set
->crtc
);
11256 ret
= intel_pipe_set_base(set
->crtc
,
11257 set
->x
, set
->y
, set
->fb
);
11260 * We need to make sure the primary plane is re-enabled if it
11261 * has previously been turned off.
11263 if (!intel_crtc
->primary_enabled
&& ret
== 0) {
11264 WARN_ON(!intel_crtc
->active
);
11265 intel_enable_primary_hw_plane(dev_priv
, intel_crtc
->plane
,
11270 * In the fastboot case this may be our only check of the
11271 * state after boot. It would be better to only do it on
11272 * the first update, but we don't have a nice way of doing that
11273 * (and really, set_config isn't used much for high freq page
11274 * flipping, so increasing its cost here shouldn't be a big
11277 if (i915
.fastboot
&& ret
== 0)
11278 intel_modeset_check_state(set
->crtc
->dev
);
11282 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11283 set
->crtc
->base
.id
, ret
);
11285 intel_set_config_restore_state(dev
, config
);
11288 * HACK: if the pipe was on, but we didn't have a framebuffer,
11289 * force the pipe off to avoid oopsing in the modeset code
11290 * due to fb==NULL. This should only happen during boot since
11291 * we don't yet reconstruct the FB from the hardware state.
11293 if (to_intel_crtc(save_set
.crtc
)->new_enabled
&& !save_set
.fb
)
11294 disable_crtc_nofb(to_intel_crtc(save_set
.crtc
));
11296 /* Try to restore the config */
11297 if (config
->mode_changed
&&
11298 intel_set_mode(save_set
.crtc
, save_set
.mode
,
11299 save_set
.x
, save_set
.y
, save_set
.fb
))
11300 DRM_ERROR("failed to restore config after modeset failure\n");
11304 intel_set_config_free(config
);
11308 static const struct drm_crtc_funcs intel_crtc_funcs
= {
11309 .gamma_set
= intel_crtc_gamma_set
,
11310 .set_config
= intel_crtc_set_config
,
11311 .destroy
= intel_crtc_destroy
,
11312 .page_flip
= intel_crtc_page_flip
,
11315 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private
*dev_priv
,
11316 struct intel_shared_dpll
*pll
,
11317 struct intel_dpll_hw_state
*hw_state
)
11321 if (!intel_display_power_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
11324 val
= I915_READ(PCH_DPLL(pll
->id
));
11325 hw_state
->dpll
= val
;
11326 hw_state
->fp0
= I915_READ(PCH_FP0(pll
->id
));
11327 hw_state
->fp1
= I915_READ(PCH_FP1(pll
->id
));
11329 return val
& DPLL_VCO_ENABLE
;
11332 static void ibx_pch_dpll_mode_set(struct drm_i915_private
*dev_priv
,
11333 struct intel_shared_dpll
*pll
)
11335 I915_WRITE(PCH_FP0(pll
->id
), pll
->hw_state
.fp0
);
11336 I915_WRITE(PCH_FP1(pll
->id
), pll
->hw_state
.fp1
);
11339 static void ibx_pch_dpll_enable(struct drm_i915_private
*dev_priv
,
11340 struct intel_shared_dpll
*pll
)
11342 /* PCH refclock must be enabled first */
11343 ibx_assert_pch_refclk_enabled(dev_priv
);
11345 I915_WRITE(PCH_DPLL(pll
->id
), pll
->hw_state
.dpll
);
11347 /* Wait for the clocks to stabilize. */
11348 POSTING_READ(PCH_DPLL(pll
->id
));
11351 /* The pixel multiplier can only be updated once the
11352 * DPLL is enabled and the clocks are stable.
11354 * So write it again.
11356 I915_WRITE(PCH_DPLL(pll
->id
), pll
->hw_state
.dpll
);
11357 POSTING_READ(PCH_DPLL(pll
->id
));
11361 static void ibx_pch_dpll_disable(struct drm_i915_private
*dev_priv
,
11362 struct intel_shared_dpll
*pll
)
11364 struct drm_device
*dev
= dev_priv
->dev
;
11365 struct intel_crtc
*crtc
;
11367 /* Make sure no transcoder isn't still depending on us. */
11368 for_each_intel_crtc(dev
, crtc
) {
11369 if (intel_crtc_to_shared_dpll(crtc
) == pll
)
11370 assert_pch_transcoder_disabled(dev_priv
, crtc
->pipe
);
11373 I915_WRITE(PCH_DPLL(pll
->id
), 0);
11374 POSTING_READ(PCH_DPLL(pll
->id
));
11378 static char *ibx_pch_dpll_names
[] = {
11383 static void ibx_pch_dpll_init(struct drm_device
*dev
)
11385 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11388 dev_priv
->num_shared_dpll
= 2;
11390 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
11391 dev_priv
->shared_dplls
[i
].id
= i
;
11392 dev_priv
->shared_dplls
[i
].name
= ibx_pch_dpll_names
[i
];
11393 dev_priv
->shared_dplls
[i
].mode_set
= ibx_pch_dpll_mode_set
;
11394 dev_priv
->shared_dplls
[i
].enable
= ibx_pch_dpll_enable
;
11395 dev_priv
->shared_dplls
[i
].disable
= ibx_pch_dpll_disable
;
11396 dev_priv
->shared_dplls
[i
].get_hw_state
=
11397 ibx_pch_dpll_get_hw_state
;
11401 static void intel_shared_dpll_init(struct drm_device
*dev
)
11403 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11406 intel_ddi_pll_init(dev
);
11407 else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
11408 ibx_pch_dpll_init(dev
);
11410 dev_priv
->num_shared_dpll
= 0;
11412 BUG_ON(dev_priv
->num_shared_dpll
> I915_NUM_PLLS
);
11416 intel_primary_plane_disable(struct drm_plane
*plane
)
11418 struct drm_device
*dev
= plane
->dev
;
11419 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11420 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
11421 struct intel_crtc
*intel_crtc
;
11426 BUG_ON(!plane
->crtc
);
11428 intel_crtc
= to_intel_crtc(plane
->crtc
);
11431 * Even though we checked plane->fb above, it's still possible that
11432 * the primary plane has been implicitly disabled because the crtc
11433 * coordinates given weren't visible, or because we detected
11434 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11435 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11436 * In either case, we need to unpin the FB and let the fb pointer get
11437 * updated, but otherwise we don't need to touch the hardware.
11439 if (!intel_crtc
->primary_enabled
)
11440 goto disable_unpin
;
11442 intel_crtc_wait_for_pending_flips(plane
->crtc
);
11443 intel_disable_primary_hw_plane(dev_priv
, intel_plane
->plane
,
11444 intel_plane
->pipe
);
11446 mutex_lock(&dev
->struct_mutex
);
11447 i915_gem_track_fb(intel_fb_obj(plane
->fb
), NULL
,
11448 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
));
11449 intel_unpin_fb_obj(intel_fb_obj(plane
->fb
));
11450 mutex_unlock(&dev
->struct_mutex
);
11457 intel_primary_plane_setplane(struct drm_plane
*plane
, struct drm_crtc
*crtc
,
11458 struct drm_framebuffer
*fb
, int crtc_x
, int crtc_y
,
11459 unsigned int crtc_w
, unsigned int crtc_h
,
11460 uint32_t src_x
, uint32_t src_y
,
11461 uint32_t src_w
, uint32_t src_h
)
11463 struct drm_device
*dev
= crtc
->dev
;
11464 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11465 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11466 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
11467 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
11468 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(plane
->fb
);
11469 struct drm_rect dest
= {
11470 /* integer pixels */
11473 .x2
= crtc_x
+ crtc_w
,
11474 .y2
= crtc_y
+ crtc_h
,
11476 struct drm_rect src
= {
11477 /* 16.16 fixed point */
11480 .x2
= src_x
+ src_w
,
11481 .y2
= src_y
+ src_h
,
11483 const struct drm_rect clip
= {
11484 /* integer pixels */
11485 .x2
= intel_crtc
->active
? intel_crtc
->config
.pipe_src_w
: 0,
11486 .y2
= intel_crtc
->active
? intel_crtc
->config
.pipe_src_h
: 0,
11491 ret
= drm_plane_helper_check_update(plane
, crtc
, fb
,
11492 &src
, &dest
, &clip
,
11493 DRM_PLANE_HELPER_NO_SCALING
,
11494 DRM_PLANE_HELPER_NO_SCALING
,
11495 false, true, &visible
);
11501 * If the CRTC isn't enabled, we're just pinning the framebuffer,
11502 * updating the fb pointer, and returning without touching the
11503 * hardware. This allows us to later do a drmModeSetCrtc with fb=-1 to
11504 * turn on the display with all planes setup as desired.
11506 if (!crtc
->enabled
) {
11507 mutex_lock(&dev
->struct_mutex
);
11510 * If we already called setplane while the crtc was disabled,
11511 * we may have an fb pinned; unpin it.
11514 intel_unpin_fb_obj(old_obj
);
11516 i915_gem_track_fb(old_obj
, obj
,
11517 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
));
11519 /* Pin and return without programming hardware */
11520 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, NULL
);
11521 mutex_unlock(&dev
->struct_mutex
);
11526 intel_crtc_wait_for_pending_flips(crtc
);
11529 * If clipping results in a non-visible primary plane, we'll disable
11530 * the primary plane. Note that this is a bit different than what
11531 * happens if userspace explicitly disables the plane by passing fb=0
11532 * because plane->fb still gets set and pinned.
11535 mutex_lock(&dev
->struct_mutex
);
11538 * Try to pin the new fb first so that we can bail out if we
11541 if (plane
->fb
!= fb
) {
11542 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, NULL
);
11544 mutex_unlock(&dev
->struct_mutex
);
11549 i915_gem_track_fb(old_obj
, obj
,
11550 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
));
11552 if (intel_crtc
->primary_enabled
)
11553 intel_disable_primary_hw_plane(dev_priv
,
11554 intel_plane
->plane
,
11555 intel_plane
->pipe
);
11558 if (plane
->fb
!= fb
)
11560 intel_unpin_fb_obj(old_obj
);
11562 mutex_unlock(&dev
->struct_mutex
);
11567 ret
= intel_pipe_set_base(crtc
, src
.x1
, src
.y1
, fb
);
11571 if (!intel_crtc
->primary_enabled
)
11572 intel_enable_primary_hw_plane(dev_priv
, intel_crtc
->plane
,
11578 /* Common destruction function for both primary and cursor planes */
11579 static void intel_plane_destroy(struct drm_plane
*plane
)
11581 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
11582 drm_plane_cleanup(plane
);
11583 kfree(intel_plane
);
11586 static const struct drm_plane_funcs intel_primary_plane_funcs
= {
11587 .update_plane
= intel_primary_plane_setplane
,
11588 .disable_plane
= intel_primary_plane_disable
,
11589 .destroy
= intel_plane_destroy
,
11592 static struct drm_plane
*intel_primary_plane_create(struct drm_device
*dev
,
11595 struct intel_plane
*primary
;
11596 const uint32_t *intel_primary_formats
;
11599 primary
= kzalloc(sizeof(*primary
), GFP_KERNEL
);
11600 if (primary
== NULL
)
11603 primary
->can_scale
= false;
11604 primary
->max_downscale
= 1;
11605 primary
->pipe
= pipe
;
11606 primary
->plane
= pipe
;
11607 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4)
11608 primary
->plane
= !pipe
;
11610 if (INTEL_INFO(dev
)->gen
<= 3) {
11611 intel_primary_formats
= intel_primary_formats_gen2
;
11612 num_formats
= ARRAY_SIZE(intel_primary_formats_gen2
);
11614 intel_primary_formats
= intel_primary_formats_gen4
;
11615 num_formats
= ARRAY_SIZE(intel_primary_formats_gen4
);
11618 drm_universal_plane_init(dev
, &primary
->base
, 0,
11619 &intel_primary_plane_funcs
,
11620 intel_primary_formats
, num_formats
,
11621 DRM_PLANE_TYPE_PRIMARY
);
11622 return &primary
->base
;
11626 intel_cursor_plane_disable(struct drm_plane
*plane
)
11631 BUG_ON(!plane
->crtc
);
11633 return intel_crtc_cursor_set_obj(plane
->crtc
, NULL
, 0, 0);
11637 intel_cursor_plane_update(struct drm_plane
*plane
, struct drm_crtc
*crtc
,
11638 struct drm_framebuffer
*fb
, int crtc_x
, int crtc_y
,
11639 unsigned int crtc_w
, unsigned int crtc_h
,
11640 uint32_t src_x
, uint32_t src_y
,
11641 uint32_t src_w
, uint32_t src_h
)
11643 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11644 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
11645 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
11646 struct drm_rect dest
= {
11647 /* integer pixels */
11650 .x2
= crtc_x
+ crtc_w
,
11651 .y2
= crtc_y
+ crtc_h
,
11653 struct drm_rect src
= {
11654 /* 16.16 fixed point */
11657 .x2
= src_x
+ src_w
,
11658 .y2
= src_y
+ src_h
,
11660 const struct drm_rect clip
= {
11661 /* integer pixels */
11662 .x2
= intel_crtc
->config
.pipe_src_w
,
11663 .y2
= intel_crtc
->config
.pipe_src_h
,
11668 ret
= drm_plane_helper_check_update(plane
, crtc
, fb
,
11669 &src
, &dest
, &clip
,
11670 DRM_PLANE_HELPER_NO_SCALING
,
11671 DRM_PLANE_HELPER_NO_SCALING
,
11672 true, true, &visible
);
11676 crtc
->cursor_x
= crtc_x
;
11677 crtc
->cursor_y
= crtc_y
;
11678 if (fb
!= crtc
->cursor
->fb
) {
11679 return intel_crtc_cursor_set_obj(crtc
, obj
, crtc_w
, crtc_h
);
11681 intel_crtc_update_cursor(crtc
, visible
);
11685 static const struct drm_plane_funcs intel_cursor_plane_funcs
= {
11686 .update_plane
= intel_cursor_plane_update
,
11687 .disable_plane
= intel_cursor_plane_disable
,
11688 .destroy
= intel_plane_destroy
,
11691 static struct drm_plane
*intel_cursor_plane_create(struct drm_device
*dev
,
11694 struct intel_plane
*cursor
;
11696 cursor
= kzalloc(sizeof(*cursor
), GFP_KERNEL
);
11697 if (cursor
== NULL
)
11700 cursor
->can_scale
= false;
11701 cursor
->max_downscale
= 1;
11702 cursor
->pipe
= pipe
;
11703 cursor
->plane
= pipe
;
11705 drm_universal_plane_init(dev
, &cursor
->base
, 0,
11706 &intel_cursor_plane_funcs
,
11707 intel_cursor_formats
,
11708 ARRAY_SIZE(intel_cursor_formats
),
11709 DRM_PLANE_TYPE_CURSOR
);
11710 return &cursor
->base
;
11713 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
11715 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11716 struct intel_crtc
*intel_crtc
;
11717 struct drm_plane
*primary
= NULL
;
11718 struct drm_plane
*cursor
= NULL
;
11721 intel_crtc
= kzalloc(sizeof(*intel_crtc
), GFP_KERNEL
);
11722 if (intel_crtc
== NULL
)
11725 primary
= intel_primary_plane_create(dev
, pipe
);
11729 cursor
= intel_cursor_plane_create(dev
, pipe
);
11733 ret
= drm_crtc_init_with_planes(dev
, &intel_crtc
->base
, primary
,
11734 cursor
, &intel_crtc_funcs
);
11738 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
11739 for (i
= 0; i
< 256; i
++) {
11740 intel_crtc
->lut_r
[i
] = i
;
11741 intel_crtc
->lut_g
[i
] = i
;
11742 intel_crtc
->lut_b
[i
] = i
;
11746 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
11747 * is hooked to pipe B. Hence we want plane A feeding pipe B.
11749 intel_crtc
->pipe
= pipe
;
11750 intel_crtc
->plane
= pipe
;
11751 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4) {
11752 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
11753 intel_crtc
->plane
= !pipe
;
11756 intel_crtc
->cursor_base
= ~0;
11757 intel_crtc
->cursor_cntl
= ~0;
11759 init_waitqueue_head(&intel_crtc
->vbl_wait
);
11761 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
11762 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
11763 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
11764 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
11766 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
11768 WARN_ON(drm_crtc_index(&intel_crtc
->base
) != intel_crtc
->pipe
);
11773 drm_plane_cleanup(primary
);
11775 drm_plane_cleanup(cursor
);
11779 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
)
11781 struct drm_encoder
*encoder
= connector
->base
.encoder
;
11782 struct drm_device
*dev
= connector
->base
.dev
;
11784 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
11787 return INVALID_PIPE
;
11789 return to_intel_crtc(encoder
->crtc
)->pipe
;
11792 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
11793 struct drm_file
*file
)
11795 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
11796 struct drm_mode_object
*drmmode_obj
;
11797 struct intel_crtc
*crtc
;
11799 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
11802 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
11803 DRM_MODE_OBJECT_CRTC
);
11805 if (!drmmode_obj
) {
11806 DRM_ERROR("no such CRTC id\n");
11810 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
11811 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
11816 static int intel_encoder_clones(struct intel_encoder
*encoder
)
11818 struct drm_device
*dev
= encoder
->base
.dev
;
11819 struct intel_encoder
*source_encoder
;
11820 int index_mask
= 0;
11823 list_for_each_entry(source_encoder
,
11824 &dev
->mode_config
.encoder_list
, base
.head
) {
11825 if (encoders_cloneable(encoder
, source_encoder
))
11826 index_mask
|= (1 << entry
);
11834 static bool has_edp_a(struct drm_device
*dev
)
11836 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11838 if (!IS_MOBILE(dev
))
11841 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
11844 if (IS_GEN5(dev
) && (I915_READ(FUSE_STRAP
) & ILK_eDP_A_DISABLE
))
11850 const char *intel_output_name(int output
)
11852 static const char *names
[] = {
11853 [INTEL_OUTPUT_UNUSED
] = "Unused",
11854 [INTEL_OUTPUT_ANALOG
] = "Analog",
11855 [INTEL_OUTPUT_DVO
] = "DVO",
11856 [INTEL_OUTPUT_SDVO
] = "SDVO",
11857 [INTEL_OUTPUT_LVDS
] = "LVDS",
11858 [INTEL_OUTPUT_TVOUT
] = "TV",
11859 [INTEL_OUTPUT_HDMI
] = "HDMI",
11860 [INTEL_OUTPUT_DISPLAYPORT
] = "DisplayPort",
11861 [INTEL_OUTPUT_EDP
] = "eDP",
11862 [INTEL_OUTPUT_DSI
] = "DSI",
11863 [INTEL_OUTPUT_UNKNOWN
] = "Unknown",
11866 if (output
< 0 || output
>= ARRAY_SIZE(names
) || !names
[output
])
11869 return names
[output
];
11872 static bool intel_crt_present(struct drm_device
*dev
)
11874 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11879 if (IS_CHERRYVIEW(dev
))
11882 if (IS_VALLEYVIEW(dev
) && !dev_priv
->vbt
.int_crt_support
)
11888 static void intel_setup_outputs(struct drm_device
*dev
)
11890 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11891 struct intel_encoder
*encoder
;
11892 bool dpd_is_edp
= false;
11894 intel_lvds_init(dev
);
11896 if (intel_crt_present(dev
))
11897 intel_crt_init(dev
);
11899 if (HAS_DDI(dev
)) {
11902 /* Haswell uses DDI functions to detect digital outputs */
11903 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
11904 /* DDI A only supports eDP */
11906 intel_ddi_init(dev
, PORT_A
);
11908 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
11910 found
= I915_READ(SFUSE_STRAP
);
11912 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
11913 intel_ddi_init(dev
, PORT_B
);
11914 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
11915 intel_ddi_init(dev
, PORT_C
);
11916 if (found
& SFUSE_STRAP_DDID_DETECTED
)
11917 intel_ddi_init(dev
, PORT_D
);
11918 } else if (HAS_PCH_SPLIT(dev
)) {
11920 dpd_is_edp
= intel_dp_is_edp(dev
, PORT_D
);
11922 if (has_edp_a(dev
))
11923 intel_dp_init(dev
, DP_A
, PORT_A
);
11925 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
11926 /* PCH SDVOB multiplex with HDMIB */
11927 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
11929 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
11930 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
11931 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
11934 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
11935 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
11937 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
11938 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
11940 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
11941 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
11943 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
11944 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
11945 } else if (IS_VALLEYVIEW(dev
)) {
11946 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIB
) & SDVO_DETECTED
) {
11947 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIB
,
11949 if (I915_READ(VLV_DISPLAY_BASE
+ DP_B
) & DP_DETECTED
)
11950 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_B
, PORT_B
);
11953 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIC
) & SDVO_DETECTED
) {
11954 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIC
,
11956 if (I915_READ(VLV_DISPLAY_BASE
+ DP_C
) & DP_DETECTED
)
11957 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_C
, PORT_C
);
11960 if (IS_CHERRYVIEW(dev
)) {
11961 if (I915_READ(VLV_DISPLAY_BASE
+ CHV_HDMID
) & SDVO_DETECTED
) {
11962 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ CHV_HDMID
,
11964 if (I915_READ(VLV_DISPLAY_BASE
+ DP_D
) & DP_DETECTED
)
11965 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_D
, PORT_D
);
11969 intel_dsi_init(dev
);
11970 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
11971 bool found
= false;
11973 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
11974 DRM_DEBUG_KMS("probing SDVOB\n");
11975 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, true);
11976 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
11977 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
11978 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
11981 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
))
11982 intel_dp_init(dev
, DP_B
, PORT_B
);
11985 /* Before G4X SDVOC doesn't have its own detect register */
11987 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
11988 DRM_DEBUG_KMS("probing SDVOC\n");
11989 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, false);
11992 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
11994 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
11995 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
11996 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
11998 if (SUPPORTS_INTEGRATED_DP(dev
))
11999 intel_dp_init(dev
, DP_C
, PORT_C
);
12002 if (SUPPORTS_INTEGRATED_DP(dev
) &&
12003 (I915_READ(DP_D
) & DP_DETECTED
))
12004 intel_dp_init(dev
, DP_D
, PORT_D
);
12005 } else if (IS_GEN2(dev
))
12006 intel_dvo_init(dev
);
12008 if (SUPPORTS_TV(dev
))
12009 intel_tv_init(dev
);
12011 intel_edp_psr_init(dev
);
12013 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
12014 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
12015 encoder
->base
.possible_clones
=
12016 intel_encoder_clones(encoder
);
12019 intel_init_pch_refclk(dev
);
12021 drm_helper_move_panel_connectors_to_head(dev
);
12024 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
12026 struct drm_device
*dev
= fb
->dev
;
12027 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
12029 drm_framebuffer_cleanup(fb
);
12030 mutex_lock(&dev
->struct_mutex
);
12031 WARN_ON(!intel_fb
->obj
->framebuffer_references
--);
12032 drm_gem_object_unreference(&intel_fb
->obj
->base
);
12033 mutex_unlock(&dev
->struct_mutex
);
12037 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
12038 struct drm_file
*file
,
12039 unsigned int *handle
)
12041 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
12042 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
12044 return drm_gem_handle_create(file
, &obj
->base
, handle
);
12047 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
12048 .destroy
= intel_user_framebuffer_destroy
,
12049 .create_handle
= intel_user_framebuffer_create_handle
,
12052 static int intel_framebuffer_init(struct drm_device
*dev
,
12053 struct intel_framebuffer
*intel_fb
,
12054 struct drm_mode_fb_cmd2
*mode_cmd
,
12055 struct drm_i915_gem_object
*obj
)
12057 int aligned_height
;
12061 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
12063 if (obj
->tiling_mode
== I915_TILING_Y
) {
12064 DRM_DEBUG("hardware does not support tiling Y\n");
12068 if (mode_cmd
->pitches
[0] & 63) {
12069 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12070 mode_cmd
->pitches
[0]);
12074 if (INTEL_INFO(dev
)->gen
>= 5 && !IS_VALLEYVIEW(dev
)) {
12075 pitch_limit
= 32*1024;
12076 } else if (INTEL_INFO(dev
)->gen
>= 4) {
12077 if (obj
->tiling_mode
)
12078 pitch_limit
= 16*1024;
12080 pitch_limit
= 32*1024;
12081 } else if (INTEL_INFO(dev
)->gen
>= 3) {
12082 if (obj
->tiling_mode
)
12083 pitch_limit
= 8*1024;
12085 pitch_limit
= 16*1024;
12087 /* XXX DSPC is limited to 4k tiled */
12088 pitch_limit
= 8*1024;
12090 if (mode_cmd
->pitches
[0] > pitch_limit
) {
12091 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12092 obj
->tiling_mode
? "tiled" : "linear",
12093 mode_cmd
->pitches
[0], pitch_limit
);
12097 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
12098 mode_cmd
->pitches
[0] != obj
->stride
) {
12099 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12100 mode_cmd
->pitches
[0], obj
->stride
);
12104 /* Reject formats not supported by any plane early. */
12105 switch (mode_cmd
->pixel_format
) {
12106 case DRM_FORMAT_C8
:
12107 case DRM_FORMAT_RGB565
:
12108 case DRM_FORMAT_XRGB8888
:
12109 case DRM_FORMAT_ARGB8888
:
12111 case DRM_FORMAT_XRGB1555
:
12112 case DRM_FORMAT_ARGB1555
:
12113 if (INTEL_INFO(dev
)->gen
> 3) {
12114 DRM_DEBUG("unsupported pixel format: %s\n",
12115 drm_get_format_name(mode_cmd
->pixel_format
));
12119 case DRM_FORMAT_XBGR8888
:
12120 case DRM_FORMAT_ABGR8888
:
12121 case DRM_FORMAT_XRGB2101010
:
12122 case DRM_FORMAT_ARGB2101010
:
12123 case DRM_FORMAT_XBGR2101010
:
12124 case DRM_FORMAT_ABGR2101010
:
12125 if (INTEL_INFO(dev
)->gen
< 4) {
12126 DRM_DEBUG("unsupported pixel format: %s\n",
12127 drm_get_format_name(mode_cmd
->pixel_format
));
12131 case DRM_FORMAT_YUYV
:
12132 case DRM_FORMAT_UYVY
:
12133 case DRM_FORMAT_YVYU
:
12134 case DRM_FORMAT_VYUY
:
12135 if (INTEL_INFO(dev
)->gen
< 5) {
12136 DRM_DEBUG("unsupported pixel format: %s\n",
12137 drm_get_format_name(mode_cmd
->pixel_format
));
12142 DRM_DEBUG("unsupported pixel format: %s\n",
12143 drm_get_format_name(mode_cmd
->pixel_format
));
12147 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12148 if (mode_cmd
->offsets
[0] != 0)
12151 aligned_height
= intel_align_height(dev
, mode_cmd
->height
,
12153 /* FIXME drm helper for size checks (especially planar formats)? */
12154 if (obj
->base
.size
< aligned_height
* mode_cmd
->pitches
[0])
12157 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
12158 intel_fb
->obj
= obj
;
12159 intel_fb
->obj
->framebuffer_references
++;
12161 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
12163 DRM_ERROR("framebuffer init failed %d\n", ret
);
12170 static struct drm_framebuffer
*
12171 intel_user_framebuffer_create(struct drm_device
*dev
,
12172 struct drm_file
*filp
,
12173 struct drm_mode_fb_cmd2
*mode_cmd
)
12175 struct drm_i915_gem_object
*obj
;
12177 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
12178 mode_cmd
->handles
[0]));
12179 if (&obj
->base
== NULL
)
12180 return ERR_PTR(-ENOENT
);
12182 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
12185 #ifndef CONFIG_DRM_I915_FBDEV
12186 static inline void intel_fbdev_output_poll_changed(struct drm_device
*dev
)
12191 static const struct drm_mode_config_funcs intel_mode_funcs
= {
12192 .fb_create
= intel_user_framebuffer_create
,
12193 .output_poll_changed
= intel_fbdev_output_poll_changed
,
12196 /* Set up chip specific display functions */
12197 static void intel_init_display(struct drm_device
*dev
)
12199 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12201 if (HAS_PCH_SPLIT(dev
) || IS_G4X(dev
))
12202 dev_priv
->display
.find_dpll
= g4x_find_best_dpll
;
12203 else if (IS_CHERRYVIEW(dev
))
12204 dev_priv
->display
.find_dpll
= chv_find_best_dpll
;
12205 else if (IS_VALLEYVIEW(dev
))
12206 dev_priv
->display
.find_dpll
= vlv_find_best_dpll
;
12207 else if (IS_PINEVIEW(dev
))
12208 dev_priv
->display
.find_dpll
= pnv_find_best_dpll
;
12210 dev_priv
->display
.find_dpll
= i9xx_find_best_dpll
;
12212 if (HAS_DDI(dev
)) {
12213 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
12214 dev_priv
->display
.get_plane_config
= ironlake_get_plane_config
;
12215 dev_priv
->display
.crtc_mode_set
= haswell_crtc_mode_set
;
12216 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
12217 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
12218 dev_priv
->display
.off
= ironlake_crtc_off
;
12219 dev_priv
->display
.update_primary_plane
=
12220 ironlake_update_primary_plane
;
12221 } else if (HAS_PCH_SPLIT(dev
)) {
12222 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
12223 dev_priv
->display
.get_plane_config
= ironlake_get_plane_config
;
12224 dev_priv
->display
.crtc_mode_set
= ironlake_crtc_mode_set
;
12225 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
12226 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
12227 dev_priv
->display
.off
= ironlake_crtc_off
;
12228 dev_priv
->display
.update_primary_plane
=
12229 ironlake_update_primary_plane
;
12230 } else if (IS_VALLEYVIEW(dev
)) {
12231 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
12232 dev_priv
->display
.get_plane_config
= i9xx_get_plane_config
;
12233 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
12234 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
12235 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
12236 dev_priv
->display
.off
= i9xx_crtc_off
;
12237 dev_priv
->display
.update_primary_plane
=
12238 i9xx_update_primary_plane
;
12240 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
12241 dev_priv
->display
.get_plane_config
= i9xx_get_plane_config
;
12242 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
12243 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
12244 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
12245 dev_priv
->display
.off
= i9xx_crtc_off
;
12246 dev_priv
->display
.update_primary_plane
=
12247 i9xx_update_primary_plane
;
12250 /* Returns the core display clock speed */
12251 if (IS_VALLEYVIEW(dev
))
12252 dev_priv
->display
.get_display_clock_speed
=
12253 valleyview_get_display_clock_speed
;
12254 else if (IS_I945G(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
12255 dev_priv
->display
.get_display_clock_speed
=
12256 i945_get_display_clock_speed
;
12257 else if (IS_I915G(dev
))
12258 dev_priv
->display
.get_display_clock_speed
=
12259 i915_get_display_clock_speed
;
12260 else if (IS_I945GM(dev
) || IS_845G(dev
))
12261 dev_priv
->display
.get_display_clock_speed
=
12262 i9xx_misc_get_display_clock_speed
;
12263 else if (IS_PINEVIEW(dev
))
12264 dev_priv
->display
.get_display_clock_speed
=
12265 pnv_get_display_clock_speed
;
12266 else if (IS_I915GM(dev
))
12267 dev_priv
->display
.get_display_clock_speed
=
12268 i915gm_get_display_clock_speed
;
12269 else if (IS_I865G(dev
))
12270 dev_priv
->display
.get_display_clock_speed
=
12271 i865_get_display_clock_speed
;
12272 else if (IS_I85X(dev
))
12273 dev_priv
->display
.get_display_clock_speed
=
12274 i855_get_display_clock_speed
;
12275 else /* 852, 830 */
12276 dev_priv
->display
.get_display_clock_speed
=
12277 i830_get_display_clock_speed
;
12279 if (HAS_PCH_SPLIT(dev
)) {
12280 if (IS_GEN5(dev
)) {
12281 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
12282 dev_priv
->display
.write_eld
= ironlake_write_eld
;
12283 } else if (IS_GEN6(dev
)) {
12284 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
12285 dev_priv
->display
.write_eld
= ironlake_write_eld
;
12286 dev_priv
->display
.modeset_global_resources
=
12287 snb_modeset_global_resources
;
12288 } else if (IS_IVYBRIDGE(dev
)) {
12289 /* FIXME: detect B0+ stepping and use auto training */
12290 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
12291 dev_priv
->display
.write_eld
= ironlake_write_eld
;
12292 dev_priv
->display
.modeset_global_resources
=
12293 ivb_modeset_global_resources
;
12294 } else if (IS_HASWELL(dev
) || IS_GEN8(dev
)) {
12295 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
12296 dev_priv
->display
.write_eld
= haswell_write_eld
;
12297 dev_priv
->display
.modeset_global_resources
=
12298 haswell_modeset_global_resources
;
12300 } else if (IS_G4X(dev
)) {
12301 dev_priv
->display
.write_eld
= g4x_write_eld
;
12302 } else if (IS_VALLEYVIEW(dev
)) {
12303 dev_priv
->display
.modeset_global_resources
=
12304 valleyview_modeset_global_resources
;
12305 dev_priv
->display
.write_eld
= ironlake_write_eld
;
12308 /* Default just returns -ENODEV to indicate unsupported */
12309 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
12311 switch (INTEL_INFO(dev
)->gen
) {
12313 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
12317 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
12322 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
12326 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
12329 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12330 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
12334 intel_panel_init_backlight_funcs(dev
);
12338 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12339 * resume, or other times. This quirk makes sure that's the case for
12340 * affected systems.
12342 static void quirk_pipea_force(struct drm_device
*dev
)
12344 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12346 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
12347 DRM_INFO("applying pipe a force quirk\n");
12351 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12353 static void quirk_ssc_force_disable(struct drm_device
*dev
)
12355 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12356 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
12357 DRM_INFO("applying lvds SSC disable quirk\n");
12361 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12364 static void quirk_invert_brightness(struct drm_device
*dev
)
12366 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12367 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
12368 DRM_INFO("applying inverted panel brightness quirk\n");
12371 struct intel_quirk
{
12373 int subsystem_vendor
;
12374 int subsystem_device
;
12375 void (*hook
)(struct drm_device
*dev
);
12378 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12379 struct intel_dmi_quirk
{
12380 void (*hook
)(struct drm_device
*dev
);
12381 const struct dmi_system_id (*dmi_id_list
)[];
12384 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
12386 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
12390 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
12392 .dmi_id_list
= &(const struct dmi_system_id
[]) {
12394 .callback
= intel_dmi_reverse_brightness
,
12395 .ident
= "NCR Corporation",
12396 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
12397 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
12400 { } /* terminating entry */
12402 .hook
= quirk_invert_brightness
,
12406 static struct intel_quirk intel_quirks
[] = {
12407 /* HP Mini needs pipe A force quirk (LP: #322104) */
12408 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
12410 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12411 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
12413 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12414 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
12416 /* Lenovo U160 cannot use SSC on LVDS */
12417 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
12419 /* Sony Vaio Y cannot use SSC on LVDS */
12420 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
12422 /* Acer Aspire 5734Z must invert backlight brightness */
12423 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
12425 /* Acer/eMachines G725 */
12426 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
12428 /* Acer/eMachines e725 */
12429 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
12431 /* Acer/Packard Bell NCL20 */
12432 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
12434 /* Acer Aspire 4736Z */
12435 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
12437 /* Acer Aspire 5336 */
12438 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness
},
12441 static void intel_init_quirks(struct drm_device
*dev
)
12443 struct pci_dev
*d
= dev
->pdev
;
12446 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
12447 struct intel_quirk
*q
= &intel_quirks
[i
];
12449 if (d
->device
== q
->device
&&
12450 (d
->subsystem_vendor
== q
->subsystem_vendor
||
12451 q
->subsystem_vendor
== PCI_ANY_ID
) &&
12452 (d
->subsystem_device
== q
->subsystem_device
||
12453 q
->subsystem_device
== PCI_ANY_ID
))
12456 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
12457 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
12458 intel_dmi_quirks
[i
].hook(dev
);
12462 /* Disable the VGA plane that we never use */
12463 static void i915_disable_vga(struct drm_device
*dev
)
12465 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12467 u32 vga_reg
= i915_vgacntrl_reg(dev
);
12469 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12470 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
12471 outb(SR01
, VGA_SR_INDEX
);
12472 sr1
= inb(VGA_SR_DATA
);
12473 outb(sr1
| 1<<5, VGA_SR_DATA
);
12474 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
12477 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
12478 POSTING_READ(vga_reg
);
12481 void intel_modeset_init_hw(struct drm_device
*dev
)
12483 intel_prepare_ddi(dev
);
12485 if (IS_VALLEYVIEW(dev
))
12486 vlv_update_cdclk(dev
);
12488 intel_init_clock_gating(dev
);
12490 intel_reset_dpio(dev
);
12492 intel_enable_gt_powersave(dev
);
12495 void intel_modeset_suspend_hw(struct drm_device
*dev
)
12497 intel_suspend_hw(dev
);
12500 void intel_modeset_init(struct drm_device
*dev
)
12502 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12505 struct intel_crtc
*crtc
;
12507 drm_mode_config_init(dev
);
12509 dev
->mode_config
.min_width
= 0;
12510 dev
->mode_config
.min_height
= 0;
12512 dev
->mode_config
.preferred_depth
= 24;
12513 dev
->mode_config
.prefer_shadow
= 1;
12515 dev
->mode_config
.funcs
= &intel_mode_funcs
;
12517 intel_init_quirks(dev
);
12519 intel_init_pm(dev
);
12521 if (INTEL_INFO(dev
)->num_pipes
== 0)
12524 intel_init_display(dev
);
12526 if (IS_GEN2(dev
)) {
12527 dev
->mode_config
.max_width
= 2048;
12528 dev
->mode_config
.max_height
= 2048;
12529 } else if (IS_GEN3(dev
)) {
12530 dev
->mode_config
.max_width
= 4096;
12531 dev
->mode_config
.max_height
= 4096;
12533 dev
->mode_config
.max_width
= 8192;
12534 dev
->mode_config
.max_height
= 8192;
12537 if (IS_GEN2(dev
)) {
12538 dev
->mode_config
.cursor_width
= GEN2_CURSOR_WIDTH
;
12539 dev
->mode_config
.cursor_height
= GEN2_CURSOR_HEIGHT
;
12541 dev
->mode_config
.cursor_width
= MAX_CURSOR_WIDTH
;
12542 dev
->mode_config
.cursor_height
= MAX_CURSOR_HEIGHT
;
12545 dev
->mode_config
.fb_base
= dev_priv
->gtt
.mappable_base
;
12547 DRM_DEBUG_KMS("%d display pipe%s available.\n",
12548 INTEL_INFO(dev
)->num_pipes
,
12549 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
12551 for_each_pipe(pipe
) {
12552 intel_crtc_init(dev
, pipe
);
12553 for_each_sprite(pipe
, sprite
) {
12554 ret
= intel_plane_init(dev
, pipe
, sprite
);
12556 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12557 pipe_name(pipe
), sprite_name(pipe
, sprite
), ret
);
12561 intel_init_dpio(dev
);
12562 intel_reset_dpio(dev
);
12564 intel_shared_dpll_init(dev
);
12566 /* Just disable it once at startup */
12567 i915_disable_vga(dev
);
12568 intel_setup_outputs(dev
);
12570 /* Just in case the BIOS is doing something questionable. */
12571 intel_disable_fbc(dev
);
12573 drm_modeset_lock_all(dev
);
12574 intel_modeset_setup_hw_state(dev
, false);
12575 drm_modeset_unlock_all(dev
);
12577 for_each_intel_crtc(dev
, crtc
) {
12582 * Note that reserving the BIOS fb up front prevents us
12583 * from stuffing other stolen allocations like the ring
12584 * on top. This prevents some ugliness at boot time, and
12585 * can even allow for smooth boot transitions if the BIOS
12586 * fb is large enough for the active pipe configuration.
12588 if (dev_priv
->display
.get_plane_config
) {
12589 dev_priv
->display
.get_plane_config(crtc
,
12590 &crtc
->plane_config
);
12592 * If the fb is shared between multiple heads, we'll
12593 * just get the first one.
12595 intel_find_plane_obj(crtc
, &crtc
->plane_config
);
12600 static void intel_enable_pipe_a(struct drm_device
*dev
)
12602 struct intel_connector
*connector
;
12603 struct drm_connector
*crt
= NULL
;
12604 struct intel_load_detect_pipe load_detect_temp
;
12605 struct drm_modeset_acquire_ctx ctx
;
12607 /* We can't just switch on the pipe A, we need to set things up with a
12608 * proper mode and output configuration. As a gross hack, enable pipe A
12609 * by enabling the load detect pipe once. */
12610 list_for_each_entry(connector
,
12611 &dev
->mode_config
.connector_list
,
12613 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
12614 crt
= &connector
->base
;
12622 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
, &ctx
))
12623 intel_release_load_detect_pipe(crt
, &load_detect_temp
, &ctx
);
12629 intel_check_plane_mapping(struct intel_crtc
*crtc
)
12631 struct drm_device
*dev
= crtc
->base
.dev
;
12632 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12635 if (INTEL_INFO(dev
)->num_pipes
== 1)
12638 reg
= DSPCNTR(!crtc
->plane
);
12639 val
= I915_READ(reg
);
12641 if ((val
& DISPLAY_PLANE_ENABLE
) &&
12642 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
12648 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
12650 struct drm_device
*dev
= crtc
->base
.dev
;
12651 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12654 /* Clear any frame start delays used for debugging left by the BIOS */
12655 reg
= PIPECONF(crtc
->config
.cpu_transcoder
);
12656 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
12658 /* restore vblank interrupts to correct state */
12660 drm_vblank_on(dev
, crtc
->pipe
);
12662 drm_vblank_off(dev
, crtc
->pipe
);
12664 /* We need to sanitize the plane -> pipe mapping first because this will
12665 * disable the crtc (and hence change the state) if it is wrong. Note
12666 * that gen4+ has a fixed plane -> pipe mapping. */
12667 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
12668 struct intel_connector
*connector
;
12671 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
12672 crtc
->base
.base
.id
);
12674 /* Pipe has the wrong plane attached and the plane is active.
12675 * Temporarily change the plane mapping and disable everything
12677 plane
= crtc
->plane
;
12678 crtc
->plane
= !plane
;
12679 dev_priv
->display
.crtc_disable(&crtc
->base
);
12680 crtc
->plane
= plane
;
12682 /* ... and break all links. */
12683 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
12685 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
12688 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
12689 connector
->base
.encoder
= NULL
;
12691 /* multiple connectors may have the same encoder:
12692 * handle them and break crtc link separately */
12693 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
12695 if (connector
->encoder
->base
.crtc
== &crtc
->base
) {
12696 connector
->encoder
->base
.crtc
= NULL
;
12697 connector
->encoder
->connectors_active
= false;
12700 WARN_ON(crtc
->active
);
12701 crtc
->base
.enabled
= false;
12704 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
12705 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
12706 /* BIOS forgot to enable pipe A, this mostly happens after
12707 * resume. Force-enable the pipe to fix this, the update_dpms
12708 * call below we restore the pipe to the right state, but leave
12709 * the required bits on. */
12710 intel_enable_pipe_a(dev
);
12713 /* Adjust the state of the output pipe according to whether we
12714 * have active connectors/encoders. */
12715 intel_crtc_update_dpms(&crtc
->base
);
12717 if (crtc
->active
!= crtc
->base
.enabled
) {
12718 struct intel_encoder
*encoder
;
12720 /* This can happen either due to bugs in the get_hw_state
12721 * functions or because the pipe is force-enabled due to the
12723 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
12724 crtc
->base
.base
.id
,
12725 crtc
->base
.enabled
? "enabled" : "disabled",
12726 crtc
->active
? "enabled" : "disabled");
12728 crtc
->base
.enabled
= crtc
->active
;
12730 /* Because we only establish the connector -> encoder ->
12731 * crtc links if something is active, this means the
12732 * crtc is now deactivated. Break the links. connector
12733 * -> encoder links are only establish when things are
12734 * actually up, hence no need to break them. */
12735 WARN_ON(crtc
->active
);
12737 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
12738 WARN_ON(encoder
->connectors_active
);
12739 encoder
->base
.crtc
= NULL
;
12743 if (crtc
->active
|| IS_VALLEYVIEW(dev
) || INTEL_INFO(dev
)->gen
< 5) {
12745 * We start out with underrun reporting disabled to avoid races.
12746 * For correct bookkeeping mark this on active crtcs.
12748 * Also on gmch platforms we dont have any hardware bits to
12749 * disable the underrun reporting. Which means we need to start
12750 * out with underrun reporting disabled also on inactive pipes,
12751 * since otherwise we'll complain about the garbage we read when
12752 * e.g. coming up after runtime pm.
12754 * No protection against concurrent access is required - at
12755 * worst a fifo underrun happens which also sets this to false.
12757 crtc
->cpu_fifo_underrun_disabled
= true;
12758 crtc
->pch_fifo_underrun_disabled
= true;
12760 update_scanline_offset(crtc
);
12764 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
12766 struct intel_connector
*connector
;
12767 struct drm_device
*dev
= encoder
->base
.dev
;
12769 /* We need to check both for a crtc link (meaning that the
12770 * encoder is active and trying to read from a pipe) and the
12771 * pipe itself being active. */
12772 bool has_active_crtc
= encoder
->base
.crtc
&&
12773 to_intel_crtc(encoder
->base
.crtc
)->active
;
12775 if (encoder
->connectors_active
&& !has_active_crtc
) {
12776 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
12777 encoder
->base
.base
.id
,
12778 encoder
->base
.name
);
12780 /* Connector is active, but has no active pipe. This is
12781 * fallout from our resume register restoring. Disable
12782 * the encoder manually again. */
12783 if (encoder
->base
.crtc
) {
12784 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
12785 encoder
->base
.base
.id
,
12786 encoder
->base
.name
);
12787 encoder
->disable(encoder
);
12789 encoder
->base
.crtc
= NULL
;
12790 encoder
->connectors_active
= false;
12792 /* Inconsistent output/port/pipe state happens presumably due to
12793 * a bug in one of the get_hw_state functions. Or someplace else
12794 * in our code, like the register restore mess on resume. Clamp
12795 * things to off as a safer default. */
12796 list_for_each_entry(connector
,
12797 &dev
->mode_config
.connector_list
,
12799 if (connector
->encoder
!= encoder
)
12801 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
12802 connector
->base
.encoder
= NULL
;
12805 /* Enabled encoders without active connectors will be fixed in
12806 * the crtc fixup. */
12809 void i915_redisable_vga_power_on(struct drm_device
*dev
)
12811 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12812 u32 vga_reg
= i915_vgacntrl_reg(dev
);
12814 if (!(I915_READ(vga_reg
) & VGA_DISP_DISABLE
)) {
12815 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
12816 i915_disable_vga(dev
);
12820 void i915_redisable_vga(struct drm_device
*dev
)
12822 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12824 /* This function can be called both from intel_modeset_setup_hw_state or
12825 * at a very early point in our resume sequence, where the power well
12826 * structures are not yet restored. Since this function is at a very
12827 * paranoid "someone might have enabled VGA while we were not looking"
12828 * level, just check if the power well is enabled instead of trying to
12829 * follow the "don't touch the power well if we don't need it" policy
12830 * the rest of the driver uses. */
12831 if (!intel_display_power_enabled(dev_priv
, POWER_DOMAIN_VGA
))
12834 i915_redisable_vga_power_on(dev
);
12837 static bool primary_get_hw_state(struct intel_crtc
*crtc
)
12839 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
12844 return I915_READ(DSPCNTR(crtc
->plane
)) & DISPLAY_PLANE_ENABLE
;
12847 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
12849 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12851 struct intel_crtc
*crtc
;
12852 struct intel_encoder
*encoder
;
12853 struct intel_connector
*connector
;
12856 for_each_intel_crtc(dev
, crtc
) {
12857 memset(&crtc
->config
, 0, sizeof(crtc
->config
));
12859 crtc
->config
.quirks
|= PIPE_CONFIG_QUIRK_INHERITED_MODE
;
12861 crtc
->active
= dev_priv
->display
.get_pipe_config(crtc
,
12864 crtc
->base
.enabled
= crtc
->active
;
12865 crtc
->primary_enabled
= primary_get_hw_state(crtc
);
12867 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
12868 crtc
->base
.base
.id
,
12869 crtc
->active
? "enabled" : "disabled");
12872 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
12873 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
12875 pll
->on
= pll
->get_hw_state(dev_priv
, pll
, &pll
->hw_state
);
12877 for_each_intel_crtc(dev
, crtc
) {
12878 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
12881 pll
->refcount
= pll
->active
;
12883 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
12884 pll
->name
, pll
->refcount
, pll
->on
);
12887 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
12890 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
12894 if (encoder
->get_hw_state(encoder
, &pipe
)) {
12895 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
12896 encoder
->base
.crtc
= &crtc
->base
;
12897 encoder
->get_config(encoder
, &crtc
->config
);
12899 encoder
->base
.crtc
= NULL
;
12902 encoder
->connectors_active
= false;
12903 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
12904 encoder
->base
.base
.id
,
12905 encoder
->base
.name
,
12906 encoder
->base
.crtc
? "enabled" : "disabled",
12910 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
12912 if (connector
->get_hw_state(connector
)) {
12913 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
12914 connector
->encoder
->connectors_active
= true;
12915 connector
->base
.encoder
= &connector
->encoder
->base
;
12917 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
12918 connector
->base
.encoder
= NULL
;
12920 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
12921 connector
->base
.base
.id
,
12922 connector
->base
.name
,
12923 connector
->base
.encoder
? "enabled" : "disabled");
12927 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
12928 * and i915 state tracking structures. */
12929 void intel_modeset_setup_hw_state(struct drm_device
*dev
,
12930 bool force_restore
)
12932 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12934 struct intel_crtc
*crtc
;
12935 struct intel_encoder
*encoder
;
12938 intel_modeset_readout_hw_state(dev
);
12941 * Now that we have the config, copy it to each CRTC struct
12942 * Note that this could go away if we move to using crtc_config
12943 * checking everywhere.
12945 for_each_intel_crtc(dev
, crtc
) {
12946 if (crtc
->active
&& i915
.fastboot
) {
12947 intel_mode_from_pipe_config(&crtc
->base
.mode
, &crtc
->config
);
12948 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
12949 crtc
->base
.base
.id
);
12950 drm_mode_debug_printmodeline(&crtc
->base
.mode
);
12954 /* HW state is read out, now we need to sanitize this mess. */
12955 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
12957 intel_sanitize_encoder(encoder
);
12960 for_each_pipe(pipe
) {
12961 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
12962 intel_sanitize_crtc(crtc
);
12963 intel_dump_pipe_config(crtc
, &crtc
->config
, "[setup_hw_state]");
12966 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
12967 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
12969 if (!pll
->on
|| pll
->active
)
12972 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll
->name
);
12974 pll
->disable(dev_priv
, pll
);
12978 if (HAS_PCH_SPLIT(dev
))
12979 ilk_wm_get_hw_state(dev
);
12981 if (force_restore
) {
12982 i915_redisable_vga(dev
);
12985 * We need to use raw interfaces for restoring state to avoid
12986 * checking (bogus) intermediate states.
12988 for_each_pipe(pipe
) {
12989 struct drm_crtc
*crtc
=
12990 dev_priv
->pipe_to_crtc_mapping
[pipe
];
12992 __intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
,
12993 crtc
->primary
->fb
);
12996 intel_modeset_update_staged_output_state(dev
);
12999 intel_modeset_check_state(dev
);
13002 void intel_modeset_gem_init(struct drm_device
*dev
)
13004 struct drm_crtc
*c
;
13005 struct drm_i915_gem_object
*obj
;
13007 mutex_lock(&dev
->struct_mutex
);
13008 intel_init_gt_powersave(dev
);
13009 mutex_unlock(&dev
->struct_mutex
);
13011 intel_modeset_init_hw(dev
);
13013 intel_setup_overlay(dev
);
13016 * Make sure any fbs we allocated at startup are properly
13017 * pinned & fenced. When we do the allocation it's too early
13020 mutex_lock(&dev
->struct_mutex
);
13021 for_each_crtc(dev
, c
) {
13022 obj
= intel_fb_obj(c
->primary
->fb
);
13026 if (intel_pin_and_fence_fb_obj(dev
, obj
, NULL
)) {
13027 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13028 to_intel_crtc(c
)->pipe
);
13029 drm_framebuffer_unreference(c
->primary
->fb
);
13030 c
->primary
->fb
= NULL
;
13033 mutex_unlock(&dev
->struct_mutex
);
13036 void intel_connector_unregister(struct intel_connector
*intel_connector
)
13038 struct drm_connector
*connector
= &intel_connector
->base
;
13040 intel_panel_destroy_backlight(connector
);
13041 drm_sysfs_connector_remove(connector
);
13044 void intel_modeset_cleanup(struct drm_device
*dev
)
13046 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13047 struct drm_connector
*connector
;
13050 * Interrupts and polling as the first thing to avoid creating havoc.
13051 * Too much stuff here (turning of rps, connectors, ...) would
13052 * experience fancy races otherwise.
13054 drm_irq_uninstall(dev
);
13055 cancel_work_sync(&dev_priv
->hotplug_work
);
13057 * Due to the hpd irq storm handling the hotplug work can re-arm the
13058 * poll handlers. Hence disable polling after hpd handling is shut down.
13060 drm_kms_helper_poll_fini(dev
);
13062 mutex_lock(&dev
->struct_mutex
);
13064 intel_unregister_dsm_handler();
13066 intel_disable_fbc(dev
);
13068 intel_disable_gt_powersave(dev
);
13070 ironlake_teardown_rc6(dev
);
13072 mutex_unlock(&dev
->struct_mutex
);
13074 /* flush any delayed tasks or pending work */
13075 flush_scheduled_work();
13077 /* destroy the backlight and sysfs files before encoders/connectors */
13078 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
13079 struct intel_connector
*intel_connector
;
13081 intel_connector
= to_intel_connector(connector
);
13082 intel_connector
->unregister(intel_connector
);
13085 drm_mode_config_cleanup(dev
);
13087 intel_cleanup_overlay(dev
);
13089 mutex_lock(&dev
->struct_mutex
);
13090 intel_cleanup_gt_powersave(dev
);
13091 mutex_unlock(&dev
->struct_mutex
);
13095 * Return which encoder is currently attached for connector.
13097 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
13099 return &intel_attached_encoder(connector
)->base
;
13102 void intel_connector_attach_encoder(struct intel_connector
*connector
,
13103 struct intel_encoder
*encoder
)
13105 connector
->encoder
= encoder
;
13106 drm_mode_connector_attach_encoder(&connector
->base
,
13111 * set vga decode state - true == enable VGA decode
13113 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
13115 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13116 unsigned reg
= INTEL_INFO(dev
)->gen
>= 6 ? SNB_GMCH_CTRL
: INTEL_GMCH_CTRL
;
13119 if (pci_read_config_word(dev_priv
->bridge_dev
, reg
, &gmch_ctrl
)) {
13120 DRM_ERROR("failed to read control word\n");
13124 if (!!(gmch_ctrl
& INTEL_GMCH_VGA_DISABLE
) == !state
)
13128 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
13130 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
13132 if (pci_write_config_word(dev_priv
->bridge_dev
, reg
, gmch_ctrl
)) {
13133 DRM_ERROR("failed to write control word\n");
13140 struct intel_display_error_state
{
13142 u32 power_well_driver
;
13144 int num_transcoders
;
13146 struct intel_cursor_error_state
{
13151 } cursor
[I915_MAX_PIPES
];
13153 struct intel_pipe_error_state
{
13154 bool power_domain_on
;
13157 } pipe
[I915_MAX_PIPES
];
13159 struct intel_plane_error_state
{
13167 } plane
[I915_MAX_PIPES
];
13169 struct intel_transcoder_error_state
{
13170 bool power_domain_on
;
13171 enum transcoder cpu_transcoder
;
13184 struct intel_display_error_state
*
13185 intel_display_capture_error_state(struct drm_device
*dev
)
13187 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13188 struct intel_display_error_state
*error
;
13189 int transcoders
[] = {
13197 if (INTEL_INFO(dev
)->num_pipes
== 0)
13200 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
13204 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
13205 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_DRIVER
);
13208 error
->pipe
[i
].power_domain_on
=
13209 intel_display_power_enabled_unlocked(dev_priv
,
13210 POWER_DOMAIN_PIPE(i
));
13211 if (!error
->pipe
[i
].power_domain_on
)
13214 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
13215 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
13216 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
13218 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
13219 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
13220 if (INTEL_INFO(dev
)->gen
<= 3) {
13221 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
13222 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
13224 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
13225 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
13226 if (INTEL_INFO(dev
)->gen
>= 4) {
13227 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
13228 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
13231 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
13233 if (!HAS_PCH_SPLIT(dev
))
13234 error
->pipe
[i
].stat
= I915_READ(PIPESTAT(i
));
13237 error
->num_transcoders
= INTEL_INFO(dev
)->num_pipes
;
13238 if (HAS_DDI(dev_priv
->dev
))
13239 error
->num_transcoders
++; /* Account for eDP. */
13241 for (i
= 0; i
< error
->num_transcoders
; i
++) {
13242 enum transcoder cpu_transcoder
= transcoders
[i
];
13244 error
->transcoder
[i
].power_domain_on
=
13245 intel_display_power_enabled_unlocked(dev_priv
,
13246 POWER_DOMAIN_TRANSCODER(cpu_transcoder
));
13247 if (!error
->transcoder
[i
].power_domain_on
)
13250 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
13252 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
13253 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
13254 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
13255 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
13256 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
13257 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
13258 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
13264 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13267 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
13268 struct drm_device
*dev
,
13269 struct intel_display_error_state
*error
)
13276 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
13277 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
13278 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
13279 error
->power_well_driver
);
13281 err_printf(m
, "Pipe [%d]:\n", i
);
13282 err_printf(m
, " Power: %s\n",
13283 error
->pipe
[i
].power_domain_on
? "on" : "off");
13284 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
13285 err_printf(m
, " STAT: %08x\n", error
->pipe
[i
].stat
);
13287 err_printf(m
, "Plane [%d]:\n", i
);
13288 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
13289 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
13290 if (INTEL_INFO(dev
)->gen
<= 3) {
13291 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
13292 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
13294 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
13295 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
13296 if (INTEL_INFO(dev
)->gen
>= 4) {
13297 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
13298 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
13301 err_printf(m
, "Cursor [%d]:\n", i
);
13302 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
13303 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
13304 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
13307 for (i
= 0; i
< error
->num_transcoders
; i
++) {
13308 err_printf(m
, "CPU transcoder: %c\n",
13309 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
13310 err_printf(m
, " Power: %s\n",
13311 error
->transcoder
[i
].power_domain_on
? "on" : "off");
13312 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
13313 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
13314 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
13315 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
13316 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
13317 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
13318 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);