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drm/i915: Simplify the way BC bifurcation state consistency is kept
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic_helper.h>
41 #include <drm/drm_dp_helper.h>
42 #include <drm/drm_crtc_helper.h>
43 #include <drm/drm_plane_helper.h>
44 #include <drm/drm_rect.h>
45 #include <linux/dma_remapping.h>
46
47 /* Primary plane formats supported by all gen */
48 #define COMMON_PRIMARY_FORMATS \
49 DRM_FORMAT_C8, \
50 DRM_FORMAT_RGB565, \
51 DRM_FORMAT_XRGB8888, \
52 DRM_FORMAT_ARGB8888
53
54 /* Primary plane formats for gen <= 3 */
55 static const uint32_t intel_primary_formats_gen2[] = {
56 COMMON_PRIMARY_FORMATS,
57 DRM_FORMAT_XRGB1555,
58 DRM_FORMAT_ARGB1555,
59 };
60
61 /* Primary plane formats for gen >= 4 */
62 static const uint32_t intel_primary_formats_gen4[] = {
63 COMMON_PRIMARY_FORMATS, \
64 DRM_FORMAT_XBGR8888,
65 DRM_FORMAT_ABGR8888,
66 DRM_FORMAT_XRGB2101010,
67 DRM_FORMAT_ARGB2101010,
68 DRM_FORMAT_XBGR2101010,
69 DRM_FORMAT_ABGR2101010,
70 };
71
72 /* Cursor formats */
73 static const uint32_t intel_cursor_formats[] = {
74 DRM_FORMAT_ARGB8888,
75 };
76
77 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
78
79 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
80 struct intel_crtc_state *pipe_config);
81 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
82 struct intel_crtc_state *pipe_config);
83
84 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
85 int x, int y, struct drm_framebuffer *old_fb);
86 static int intel_framebuffer_init(struct drm_device *dev,
87 struct intel_framebuffer *ifb,
88 struct drm_mode_fb_cmd2 *mode_cmd,
89 struct drm_i915_gem_object *obj);
90 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
91 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
92 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
93 struct intel_link_m_n *m_n,
94 struct intel_link_m_n *m2_n2);
95 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
96 static void haswell_set_pipeconf(struct drm_crtc *crtc);
97 static void intel_set_pipe_csc(struct drm_crtc *crtc);
98 static void vlv_prepare_pll(struct intel_crtc *crtc,
99 const struct intel_crtc_state *pipe_config);
100 static void chv_prepare_pll(struct intel_crtc *crtc,
101 const struct intel_crtc_state *pipe_config);
102 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
103 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
104
105 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
106 {
107 if (!connector->mst_port)
108 return connector->encoder;
109 else
110 return &connector->mst_port->mst_encoders[pipe]->base;
111 }
112
113 typedef struct {
114 int min, max;
115 } intel_range_t;
116
117 typedef struct {
118 int dot_limit;
119 int p2_slow, p2_fast;
120 } intel_p2_t;
121
122 typedef struct intel_limit intel_limit_t;
123 struct intel_limit {
124 intel_range_t dot, vco, n, m, m1, m2, p, p1;
125 intel_p2_t p2;
126 };
127
128 int
129 intel_pch_rawclk(struct drm_device *dev)
130 {
131 struct drm_i915_private *dev_priv = dev->dev_private;
132
133 WARN_ON(!HAS_PCH_SPLIT(dev));
134
135 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
136 }
137
138 static inline u32 /* units of 100MHz */
139 intel_fdi_link_freq(struct drm_device *dev)
140 {
141 if (IS_GEN5(dev)) {
142 struct drm_i915_private *dev_priv = dev->dev_private;
143 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
144 } else
145 return 27;
146 }
147
148 static const intel_limit_t intel_limits_i8xx_dac = {
149 .dot = { .min = 25000, .max = 350000 },
150 .vco = { .min = 908000, .max = 1512000 },
151 .n = { .min = 2, .max = 16 },
152 .m = { .min = 96, .max = 140 },
153 .m1 = { .min = 18, .max = 26 },
154 .m2 = { .min = 6, .max = 16 },
155 .p = { .min = 4, .max = 128 },
156 .p1 = { .min = 2, .max = 33 },
157 .p2 = { .dot_limit = 165000,
158 .p2_slow = 4, .p2_fast = 2 },
159 };
160
161 static const intel_limit_t intel_limits_i8xx_dvo = {
162 .dot = { .min = 25000, .max = 350000 },
163 .vco = { .min = 908000, .max = 1512000 },
164 .n = { .min = 2, .max = 16 },
165 .m = { .min = 96, .max = 140 },
166 .m1 = { .min = 18, .max = 26 },
167 .m2 = { .min = 6, .max = 16 },
168 .p = { .min = 4, .max = 128 },
169 .p1 = { .min = 2, .max = 33 },
170 .p2 = { .dot_limit = 165000,
171 .p2_slow = 4, .p2_fast = 4 },
172 };
173
174 static const intel_limit_t intel_limits_i8xx_lvds = {
175 .dot = { .min = 25000, .max = 350000 },
176 .vco = { .min = 908000, .max = 1512000 },
177 .n = { .min = 2, .max = 16 },
178 .m = { .min = 96, .max = 140 },
179 .m1 = { .min = 18, .max = 26 },
180 .m2 = { .min = 6, .max = 16 },
181 .p = { .min = 4, .max = 128 },
182 .p1 = { .min = 1, .max = 6 },
183 .p2 = { .dot_limit = 165000,
184 .p2_slow = 14, .p2_fast = 7 },
185 };
186
187 static const intel_limit_t intel_limits_i9xx_sdvo = {
188 .dot = { .min = 20000, .max = 400000 },
189 .vco = { .min = 1400000, .max = 2800000 },
190 .n = { .min = 1, .max = 6 },
191 .m = { .min = 70, .max = 120 },
192 .m1 = { .min = 8, .max = 18 },
193 .m2 = { .min = 3, .max = 7 },
194 .p = { .min = 5, .max = 80 },
195 .p1 = { .min = 1, .max = 8 },
196 .p2 = { .dot_limit = 200000,
197 .p2_slow = 10, .p2_fast = 5 },
198 };
199
200 static const intel_limit_t intel_limits_i9xx_lvds = {
201 .dot = { .min = 20000, .max = 400000 },
202 .vco = { .min = 1400000, .max = 2800000 },
203 .n = { .min = 1, .max = 6 },
204 .m = { .min = 70, .max = 120 },
205 .m1 = { .min = 8, .max = 18 },
206 .m2 = { .min = 3, .max = 7 },
207 .p = { .min = 7, .max = 98 },
208 .p1 = { .min = 1, .max = 8 },
209 .p2 = { .dot_limit = 112000,
210 .p2_slow = 14, .p2_fast = 7 },
211 };
212
213
214 static const intel_limit_t intel_limits_g4x_sdvo = {
215 .dot = { .min = 25000, .max = 270000 },
216 .vco = { .min = 1750000, .max = 3500000},
217 .n = { .min = 1, .max = 4 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 10, .max = 30 },
222 .p1 = { .min = 1, .max = 3},
223 .p2 = { .dot_limit = 270000,
224 .p2_slow = 10,
225 .p2_fast = 10
226 },
227 };
228
229 static const intel_limit_t intel_limits_g4x_hdmi = {
230 .dot = { .min = 22000, .max = 400000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 4 },
233 .m = { .min = 104, .max = 138 },
234 .m1 = { .min = 16, .max = 23 },
235 .m2 = { .min = 5, .max = 11 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8},
238 .p2 = { .dot_limit = 165000,
239 .p2_slow = 10, .p2_fast = 5 },
240 };
241
242 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
243 .dot = { .min = 20000, .max = 115000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 14, .p2_fast = 14
253 },
254 };
255
256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
257 .dot = { .min = 80000, .max = 224000 },
258 .vco = { .min = 1750000, .max = 3500000 },
259 .n = { .min = 1, .max = 3 },
260 .m = { .min = 104, .max = 138 },
261 .m1 = { .min = 17, .max = 23 },
262 .m2 = { .min = 5, .max = 11 },
263 .p = { .min = 14, .max = 42 },
264 .p1 = { .min = 2, .max = 6 },
265 .p2 = { .dot_limit = 0,
266 .p2_slow = 7, .p2_fast = 7
267 },
268 };
269
270 static const intel_limit_t intel_limits_pineview_sdvo = {
271 .dot = { .min = 20000, .max = 400000},
272 .vco = { .min = 1700000, .max = 3500000 },
273 /* Pineview's Ncounter is a ring counter */
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 /* Pineview only has one combined m divider, which we treat as m2. */
277 .m1 = { .min = 0, .max = 0 },
278 .m2 = { .min = 0, .max = 254 },
279 .p = { .min = 5, .max = 80 },
280 .p1 = { .min = 1, .max = 8 },
281 .p2 = { .dot_limit = 200000,
282 .p2_slow = 10, .p2_fast = 5 },
283 };
284
285 static const intel_limit_t intel_limits_pineview_lvds = {
286 .dot = { .min = 20000, .max = 400000 },
287 .vco = { .min = 1700000, .max = 3500000 },
288 .n = { .min = 3, .max = 6 },
289 .m = { .min = 2, .max = 256 },
290 .m1 = { .min = 0, .max = 0 },
291 .m2 = { .min = 0, .max = 254 },
292 .p = { .min = 7, .max = 112 },
293 .p1 = { .min = 1, .max = 8 },
294 .p2 = { .dot_limit = 112000,
295 .p2_slow = 14, .p2_fast = 14 },
296 };
297
298 /* Ironlake / Sandybridge
299 *
300 * We calculate clock using (register_value + 2) for N/M1/M2, so here
301 * the range value for them is (actual_value - 2).
302 */
303 static const intel_limit_t intel_limits_ironlake_dac = {
304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 5 },
307 .m = { .min = 79, .max = 127 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 5, .max = 80 },
311 .p1 = { .min = 1, .max = 8 },
312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 10, .p2_fast = 5 },
314 };
315
316 static const intel_limit_t intel_limits_ironlake_single_lvds = {
317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 3 },
320 .m = { .min = 79, .max = 118 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2, .max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
327 };
328
329 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
330 .dot = { .min = 25000, .max = 350000 },
331 .vco = { .min = 1760000, .max = 3510000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 79, .max = 127 },
334 .m1 = { .min = 12, .max = 22 },
335 .m2 = { .min = 5, .max = 9 },
336 .p = { .min = 14, .max = 56 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 225000,
339 .p2_slow = 7, .p2_fast = 7 },
340 };
341
342 /* LVDS 100mhz refclk limits. */
343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000 },
346 .n = { .min = 1, .max = 2 },
347 .m = { .min = 79, .max = 126 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 28, .max = 112 },
351 .p1 = { .min = 2, .max = 8 },
352 .p2 = { .dot_limit = 225000,
353 .p2_slow = 14, .p2_fast = 14 },
354 };
355
356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
357 .dot = { .min = 25000, .max = 350000 },
358 .vco = { .min = 1760000, .max = 3510000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 79, .max = 126 },
361 .m1 = { .min = 12, .max = 22 },
362 .m2 = { .min = 5, .max = 9 },
363 .p = { .min = 14, .max = 42 },
364 .p1 = { .min = 2, .max = 6 },
365 .p2 = { .dot_limit = 225000,
366 .p2_slow = 7, .p2_fast = 7 },
367 };
368
369 static const intel_limit_t intel_limits_vlv = {
370 /*
371 * These are the data rate limits (measured in fast clocks)
372 * since those are the strictest limits we have. The fast
373 * clock and actual rate limits are more relaxed, so checking
374 * them would make no difference.
375 */
376 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m1 = { .min = 2, .max = 3 },
380 .m2 = { .min = 11, .max = 156 },
381 .p1 = { .min = 2, .max = 3 },
382 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
383 };
384
385 static const intel_limit_t intel_limits_chv = {
386 /*
387 * These are the data rate limits (measured in fast clocks)
388 * since those are the strictest limits we have. The fast
389 * clock and actual rate limits are more relaxed, so checking
390 * them would make no difference.
391 */
392 .dot = { .min = 25000 * 5, .max = 540000 * 5},
393 .vco = { .min = 4800000, .max = 6480000 },
394 .n = { .min = 1, .max = 1 },
395 .m1 = { .min = 2, .max = 2 },
396 .m2 = { .min = 24 << 22, .max = 175 << 22 },
397 .p1 = { .min = 2, .max = 4 },
398 .p2 = { .p2_slow = 1, .p2_fast = 14 },
399 };
400
401 static void vlv_clock(int refclk, intel_clock_t *clock)
402 {
403 clock->m = clock->m1 * clock->m2;
404 clock->p = clock->p1 * clock->p2;
405 if (WARN_ON(clock->n == 0 || clock->p == 0))
406 return;
407 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
408 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
409 }
410
411 /**
412 * Returns whether any output on the specified pipe is of the specified type
413 */
414 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
415 {
416 struct drm_device *dev = crtc->base.dev;
417 struct intel_encoder *encoder;
418
419 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
420 if (encoder->type == type)
421 return true;
422
423 return false;
424 }
425
426 /**
427 * Returns whether any output on the specified pipe will have the specified
428 * type after a staged modeset is complete, i.e., the same as
429 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
430 * encoder->crtc.
431 */
432 static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
433 {
434 struct drm_device *dev = crtc->base.dev;
435 struct intel_encoder *encoder;
436
437 for_each_intel_encoder(dev, encoder)
438 if (encoder->new_crtc == crtc && encoder->type == type)
439 return true;
440
441 return false;
442 }
443
444 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
445 int refclk)
446 {
447 struct drm_device *dev = crtc->base.dev;
448 const intel_limit_t *limit;
449
450 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
451 if (intel_is_dual_link_lvds(dev)) {
452 if (refclk == 100000)
453 limit = &intel_limits_ironlake_dual_lvds_100m;
454 else
455 limit = &intel_limits_ironlake_dual_lvds;
456 } else {
457 if (refclk == 100000)
458 limit = &intel_limits_ironlake_single_lvds_100m;
459 else
460 limit = &intel_limits_ironlake_single_lvds;
461 }
462 } else
463 limit = &intel_limits_ironlake_dac;
464
465 return limit;
466 }
467
468 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
469 {
470 struct drm_device *dev = crtc->base.dev;
471 const intel_limit_t *limit;
472
473 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
474 if (intel_is_dual_link_lvds(dev))
475 limit = &intel_limits_g4x_dual_channel_lvds;
476 else
477 limit = &intel_limits_g4x_single_channel_lvds;
478 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
479 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
480 limit = &intel_limits_g4x_hdmi;
481 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
482 limit = &intel_limits_g4x_sdvo;
483 } else /* The option is for other outputs */
484 limit = &intel_limits_i9xx_sdvo;
485
486 return limit;
487 }
488
489 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
490 {
491 struct drm_device *dev = crtc->base.dev;
492 const intel_limit_t *limit;
493
494 if (HAS_PCH_SPLIT(dev))
495 limit = intel_ironlake_limit(crtc, refclk);
496 else if (IS_G4X(dev)) {
497 limit = intel_g4x_limit(crtc);
498 } else if (IS_PINEVIEW(dev)) {
499 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
500 limit = &intel_limits_pineview_lvds;
501 else
502 limit = &intel_limits_pineview_sdvo;
503 } else if (IS_CHERRYVIEW(dev)) {
504 limit = &intel_limits_chv;
505 } else if (IS_VALLEYVIEW(dev)) {
506 limit = &intel_limits_vlv;
507 } else if (!IS_GEN2(dev)) {
508 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
509 limit = &intel_limits_i9xx_lvds;
510 else
511 limit = &intel_limits_i9xx_sdvo;
512 } else {
513 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
514 limit = &intel_limits_i8xx_lvds;
515 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
516 limit = &intel_limits_i8xx_dvo;
517 else
518 limit = &intel_limits_i8xx_dac;
519 }
520 return limit;
521 }
522
523 /* m1 is reserved as 0 in Pineview, n is a ring counter */
524 static void pineview_clock(int refclk, intel_clock_t *clock)
525 {
526 clock->m = clock->m2 + 2;
527 clock->p = clock->p1 * clock->p2;
528 if (WARN_ON(clock->n == 0 || clock->p == 0))
529 return;
530 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
531 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
532 }
533
534 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
535 {
536 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
537 }
538
539 static void i9xx_clock(int refclk, intel_clock_t *clock)
540 {
541 clock->m = i9xx_dpll_compute_m(clock);
542 clock->p = clock->p1 * clock->p2;
543 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
544 return;
545 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
546 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
547 }
548
549 static void chv_clock(int refclk, intel_clock_t *clock)
550 {
551 clock->m = clock->m1 * clock->m2;
552 clock->p = clock->p1 * clock->p2;
553 if (WARN_ON(clock->n == 0 || clock->p == 0))
554 return;
555 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
556 clock->n << 22);
557 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
558 }
559
560 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
561 /**
562 * Returns whether the given set of divisors are valid for a given refclk with
563 * the given connectors.
564 */
565
566 static bool intel_PLL_is_valid(struct drm_device *dev,
567 const intel_limit_t *limit,
568 const intel_clock_t *clock)
569 {
570 if (clock->n < limit->n.min || limit->n.max < clock->n)
571 INTELPllInvalid("n out of range\n");
572 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
573 INTELPllInvalid("p1 out of range\n");
574 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
575 INTELPllInvalid("m2 out of range\n");
576 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
577 INTELPllInvalid("m1 out of range\n");
578
579 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
580 if (clock->m1 <= clock->m2)
581 INTELPllInvalid("m1 <= m2\n");
582
583 if (!IS_VALLEYVIEW(dev)) {
584 if (clock->p < limit->p.min || limit->p.max < clock->p)
585 INTELPllInvalid("p out of range\n");
586 if (clock->m < limit->m.min || limit->m.max < clock->m)
587 INTELPllInvalid("m out of range\n");
588 }
589
590 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
591 INTELPllInvalid("vco out of range\n");
592 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
593 * connector, etc., rather than just a single range.
594 */
595 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
596 INTELPllInvalid("dot out of range\n");
597
598 return true;
599 }
600
601 static bool
602 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
603 int target, int refclk, intel_clock_t *match_clock,
604 intel_clock_t *best_clock)
605 {
606 struct drm_device *dev = crtc->base.dev;
607 intel_clock_t clock;
608 int err = target;
609
610 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
611 /*
612 * For LVDS just rely on its current settings for dual-channel.
613 * We haven't figured out how to reliably set up different
614 * single/dual channel state, if we even can.
615 */
616 if (intel_is_dual_link_lvds(dev))
617 clock.p2 = limit->p2.p2_fast;
618 else
619 clock.p2 = limit->p2.p2_slow;
620 } else {
621 if (target < limit->p2.dot_limit)
622 clock.p2 = limit->p2.p2_slow;
623 else
624 clock.p2 = limit->p2.p2_fast;
625 }
626
627 memset(best_clock, 0, sizeof(*best_clock));
628
629 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
630 clock.m1++) {
631 for (clock.m2 = limit->m2.min;
632 clock.m2 <= limit->m2.max; clock.m2++) {
633 if (clock.m2 >= clock.m1)
634 break;
635 for (clock.n = limit->n.min;
636 clock.n <= limit->n.max; clock.n++) {
637 for (clock.p1 = limit->p1.min;
638 clock.p1 <= limit->p1.max; clock.p1++) {
639 int this_err;
640
641 i9xx_clock(refclk, &clock);
642 if (!intel_PLL_is_valid(dev, limit,
643 &clock))
644 continue;
645 if (match_clock &&
646 clock.p != match_clock->p)
647 continue;
648
649 this_err = abs(clock.dot - target);
650 if (this_err < err) {
651 *best_clock = clock;
652 err = this_err;
653 }
654 }
655 }
656 }
657 }
658
659 return (err != target);
660 }
661
662 static bool
663 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
664 int target, int refclk, intel_clock_t *match_clock,
665 intel_clock_t *best_clock)
666 {
667 struct drm_device *dev = crtc->base.dev;
668 intel_clock_t clock;
669 int err = target;
670
671 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
672 /*
673 * For LVDS just rely on its current settings for dual-channel.
674 * We haven't figured out how to reliably set up different
675 * single/dual channel state, if we even can.
676 */
677 if (intel_is_dual_link_lvds(dev))
678 clock.p2 = limit->p2.p2_fast;
679 else
680 clock.p2 = limit->p2.p2_slow;
681 } else {
682 if (target < limit->p2.dot_limit)
683 clock.p2 = limit->p2.p2_slow;
684 else
685 clock.p2 = limit->p2.p2_fast;
686 }
687
688 memset(best_clock, 0, sizeof(*best_clock));
689
690 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
691 clock.m1++) {
692 for (clock.m2 = limit->m2.min;
693 clock.m2 <= limit->m2.max; clock.m2++) {
694 for (clock.n = limit->n.min;
695 clock.n <= limit->n.max; clock.n++) {
696 for (clock.p1 = limit->p1.min;
697 clock.p1 <= limit->p1.max; clock.p1++) {
698 int this_err;
699
700 pineview_clock(refclk, &clock);
701 if (!intel_PLL_is_valid(dev, limit,
702 &clock))
703 continue;
704 if (match_clock &&
705 clock.p != match_clock->p)
706 continue;
707
708 this_err = abs(clock.dot - target);
709 if (this_err < err) {
710 *best_clock = clock;
711 err = this_err;
712 }
713 }
714 }
715 }
716 }
717
718 return (err != target);
719 }
720
721 static bool
722 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
723 int target, int refclk, intel_clock_t *match_clock,
724 intel_clock_t *best_clock)
725 {
726 struct drm_device *dev = crtc->base.dev;
727 intel_clock_t clock;
728 int max_n;
729 bool found;
730 /* approximately equals target * 0.00585 */
731 int err_most = (target >> 8) + (target >> 9);
732 found = false;
733
734 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
735 if (intel_is_dual_link_lvds(dev))
736 clock.p2 = limit->p2.p2_fast;
737 else
738 clock.p2 = limit->p2.p2_slow;
739 } else {
740 if (target < limit->p2.dot_limit)
741 clock.p2 = limit->p2.p2_slow;
742 else
743 clock.p2 = limit->p2.p2_fast;
744 }
745
746 memset(best_clock, 0, sizeof(*best_clock));
747 max_n = limit->n.max;
748 /* based on hardware requirement, prefer smaller n to precision */
749 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
750 /* based on hardware requirement, prefere larger m1,m2 */
751 for (clock.m1 = limit->m1.max;
752 clock.m1 >= limit->m1.min; clock.m1--) {
753 for (clock.m2 = limit->m2.max;
754 clock.m2 >= limit->m2.min; clock.m2--) {
755 for (clock.p1 = limit->p1.max;
756 clock.p1 >= limit->p1.min; clock.p1--) {
757 int this_err;
758
759 i9xx_clock(refclk, &clock);
760 if (!intel_PLL_is_valid(dev, limit,
761 &clock))
762 continue;
763
764 this_err = abs(clock.dot - target);
765 if (this_err < err_most) {
766 *best_clock = clock;
767 err_most = this_err;
768 max_n = clock.n;
769 found = true;
770 }
771 }
772 }
773 }
774 }
775 return found;
776 }
777
778 static bool
779 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
780 int target, int refclk, intel_clock_t *match_clock,
781 intel_clock_t *best_clock)
782 {
783 struct drm_device *dev = crtc->base.dev;
784 intel_clock_t clock;
785 unsigned int bestppm = 1000000;
786 /* min update 19.2 MHz */
787 int max_n = min(limit->n.max, refclk / 19200);
788 bool found = false;
789
790 target *= 5; /* fast clock */
791
792 memset(best_clock, 0, sizeof(*best_clock));
793
794 /* based on hardware requirement, prefer smaller n to precision */
795 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
796 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
797 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
798 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
799 clock.p = clock.p1 * clock.p2;
800 /* based on hardware requirement, prefer bigger m1,m2 values */
801 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
802 unsigned int ppm, diff;
803
804 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
805 refclk * clock.m1);
806
807 vlv_clock(refclk, &clock);
808
809 if (!intel_PLL_is_valid(dev, limit,
810 &clock))
811 continue;
812
813 diff = abs(clock.dot - target);
814 ppm = div_u64(1000000ULL * diff, target);
815
816 if (ppm < 100 && clock.p > best_clock->p) {
817 bestppm = 0;
818 *best_clock = clock;
819 found = true;
820 }
821
822 if (bestppm >= 10 && ppm < bestppm - 10) {
823 bestppm = ppm;
824 *best_clock = clock;
825 found = true;
826 }
827 }
828 }
829 }
830 }
831
832 return found;
833 }
834
835 static bool
836 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
837 int target, int refclk, intel_clock_t *match_clock,
838 intel_clock_t *best_clock)
839 {
840 struct drm_device *dev = crtc->base.dev;
841 intel_clock_t clock;
842 uint64_t m2;
843 int found = false;
844
845 memset(best_clock, 0, sizeof(*best_clock));
846
847 /*
848 * Based on hardware doc, the n always set to 1, and m1 always
849 * set to 2. If requires to support 200Mhz refclk, we need to
850 * revisit this because n may not 1 anymore.
851 */
852 clock.n = 1, clock.m1 = 2;
853 target *= 5; /* fast clock */
854
855 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
856 for (clock.p2 = limit->p2.p2_fast;
857 clock.p2 >= limit->p2.p2_slow;
858 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
859
860 clock.p = clock.p1 * clock.p2;
861
862 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
863 clock.n) << 22, refclk * clock.m1);
864
865 if (m2 > INT_MAX/clock.m1)
866 continue;
867
868 clock.m2 = m2;
869
870 chv_clock(refclk, &clock);
871
872 if (!intel_PLL_is_valid(dev, limit, &clock))
873 continue;
874
875 /* based on hardware requirement, prefer bigger p
876 */
877 if (clock.p > best_clock->p) {
878 *best_clock = clock;
879 found = true;
880 }
881 }
882 }
883
884 return found;
885 }
886
887 bool intel_crtc_active(struct drm_crtc *crtc)
888 {
889 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
890
891 /* Be paranoid as we can arrive here with only partial
892 * state retrieved from the hardware during setup.
893 *
894 * We can ditch the adjusted_mode.crtc_clock check as soon
895 * as Haswell has gained clock readout/fastboot support.
896 *
897 * We can ditch the crtc->primary->fb check as soon as we can
898 * properly reconstruct framebuffers.
899 *
900 * FIXME: The intel_crtc->active here should be switched to
901 * crtc->state->active once we have proper CRTC states wired up
902 * for atomic.
903 */
904 return intel_crtc->active && crtc->primary->state->fb &&
905 intel_crtc->config->base.adjusted_mode.crtc_clock;
906 }
907
908 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
909 enum pipe pipe)
910 {
911 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
912 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
913
914 return intel_crtc->config->cpu_transcoder;
915 }
916
917 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
918 {
919 struct drm_i915_private *dev_priv = dev->dev_private;
920 u32 reg = PIPEDSL(pipe);
921 u32 line1, line2;
922 u32 line_mask;
923
924 if (IS_GEN2(dev))
925 line_mask = DSL_LINEMASK_GEN2;
926 else
927 line_mask = DSL_LINEMASK_GEN3;
928
929 line1 = I915_READ(reg) & line_mask;
930 mdelay(5);
931 line2 = I915_READ(reg) & line_mask;
932
933 return line1 == line2;
934 }
935
936 /*
937 * intel_wait_for_pipe_off - wait for pipe to turn off
938 * @crtc: crtc whose pipe to wait for
939 *
940 * After disabling a pipe, we can't wait for vblank in the usual way,
941 * spinning on the vblank interrupt status bit, since we won't actually
942 * see an interrupt when the pipe is disabled.
943 *
944 * On Gen4 and above:
945 * wait for the pipe register state bit to turn off
946 *
947 * Otherwise:
948 * wait for the display line value to settle (it usually
949 * ends up stopping at the start of the next frame).
950 *
951 */
952 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
953 {
954 struct drm_device *dev = crtc->base.dev;
955 struct drm_i915_private *dev_priv = dev->dev_private;
956 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
957 enum pipe pipe = crtc->pipe;
958
959 if (INTEL_INFO(dev)->gen >= 4) {
960 int reg = PIPECONF(cpu_transcoder);
961
962 /* Wait for the Pipe State to go off */
963 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
964 100))
965 WARN(1, "pipe_off wait timed out\n");
966 } else {
967 /* Wait for the display line to settle */
968 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
969 WARN(1, "pipe_off wait timed out\n");
970 }
971 }
972
973 /*
974 * ibx_digital_port_connected - is the specified port connected?
975 * @dev_priv: i915 private structure
976 * @port: the port to test
977 *
978 * Returns true if @port is connected, false otherwise.
979 */
980 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
981 struct intel_digital_port *port)
982 {
983 u32 bit;
984
985 if (HAS_PCH_IBX(dev_priv->dev)) {
986 switch (port->port) {
987 case PORT_B:
988 bit = SDE_PORTB_HOTPLUG;
989 break;
990 case PORT_C:
991 bit = SDE_PORTC_HOTPLUG;
992 break;
993 case PORT_D:
994 bit = SDE_PORTD_HOTPLUG;
995 break;
996 default:
997 return true;
998 }
999 } else {
1000 switch (port->port) {
1001 case PORT_B:
1002 bit = SDE_PORTB_HOTPLUG_CPT;
1003 break;
1004 case PORT_C:
1005 bit = SDE_PORTC_HOTPLUG_CPT;
1006 break;
1007 case PORT_D:
1008 bit = SDE_PORTD_HOTPLUG_CPT;
1009 break;
1010 default:
1011 return true;
1012 }
1013 }
1014
1015 return I915_READ(SDEISR) & bit;
1016 }
1017
1018 static const char *state_string(bool enabled)
1019 {
1020 return enabled ? "on" : "off";
1021 }
1022
1023 /* Only for pre-ILK configs */
1024 void assert_pll(struct drm_i915_private *dev_priv,
1025 enum pipe pipe, bool state)
1026 {
1027 int reg;
1028 u32 val;
1029 bool cur_state;
1030
1031 reg = DPLL(pipe);
1032 val = I915_READ(reg);
1033 cur_state = !!(val & DPLL_VCO_ENABLE);
1034 I915_STATE_WARN(cur_state != state,
1035 "PLL state assertion failure (expected %s, current %s)\n",
1036 state_string(state), state_string(cur_state));
1037 }
1038
1039 /* XXX: the dsi pll is shared between MIPI DSI ports */
1040 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1041 {
1042 u32 val;
1043 bool cur_state;
1044
1045 mutex_lock(&dev_priv->dpio_lock);
1046 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1047 mutex_unlock(&dev_priv->dpio_lock);
1048
1049 cur_state = val & DSI_PLL_VCO_EN;
1050 I915_STATE_WARN(cur_state != state,
1051 "DSI PLL state assertion failure (expected %s, current %s)\n",
1052 state_string(state), state_string(cur_state));
1053 }
1054 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1055 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1056
1057 struct intel_shared_dpll *
1058 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1059 {
1060 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1061
1062 if (crtc->config->shared_dpll < 0)
1063 return NULL;
1064
1065 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1066 }
1067
1068 /* For ILK+ */
1069 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1070 struct intel_shared_dpll *pll,
1071 bool state)
1072 {
1073 bool cur_state;
1074 struct intel_dpll_hw_state hw_state;
1075
1076 if (WARN (!pll,
1077 "asserting DPLL %s with no DPLL\n", state_string(state)))
1078 return;
1079
1080 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1081 I915_STATE_WARN(cur_state != state,
1082 "%s assertion failure (expected %s, current %s)\n",
1083 pll->name, state_string(state), state_string(cur_state));
1084 }
1085
1086 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1087 enum pipe pipe, bool state)
1088 {
1089 int reg;
1090 u32 val;
1091 bool cur_state;
1092 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1093 pipe);
1094
1095 if (HAS_DDI(dev_priv->dev)) {
1096 /* DDI does not have a specific FDI_TX register */
1097 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1098 val = I915_READ(reg);
1099 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1100 } else {
1101 reg = FDI_TX_CTL(pipe);
1102 val = I915_READ(reg);
1103 cur_state = !!(val & FDI_TX_ENABLE);
1104 }
1105 I915_STATE_WARN(cur_state != state,
1106 "FDI TX state assertion failure (expected %s, current %s)\n",
1107 state_string(state), state_string(cur_state));
1108 }
1109 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1110 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1111
1112 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1113 enum pipe pipe, bool state)
1114 {
1115 int reg;
1116 u32 val;
1117 bool cur_state;
1118
1119 reg = FDI_RX_CTL(pipe);
1120 val = I915_READ(reg);
1121 cur_state = !!(val & FDI_RX_ENABLE);
1122 I915_STATE_WARN(cur_state != state,
1123 "FDI RX state assertion failure (expected %s, current %s)\n",
1124 state_string(state), state_string(cur_state));
1125 }
1126 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1127 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1128
1129 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1130 enum pipe pipe)
1131 {
1132 int reg;
1133 u32 val;
1134
1135 /* ILK FDI PLL is always enabled */
1136 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1137 return;
1138
1139 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1140 if (HAS_DDI(dev_priv->dev))
1141 return;
1142
1143 reg = FDI_TX_CTL(pipe);
1144 val = I915_READ(reg);
1145 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1146 }
1147
1148 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1149 enum pipe pipe, bool state)
1150 {
1151 int reg;
1152 u32 val;
1153 bool cur_state;
1154
1155 reg = FDI_RX_CTL(pipe);
1156 val = I915_READ(reg);
1157 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1158 I915_STATE_WARN(cur_state != state,
1159 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1160 state_string(state), state_string(cur_state));
1161 }
1162
1163 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1164 enum pipe pipe)
1165 {
1166 struct drm_device *dev = dev_priv->dev;
1167 int pp_reg;
1168 u32 val;
1169 enum pipe panel_pipe = PIPE_A;
1170 bool locked = true;
1171
1172 if (WARN_ON(HAS_DDI(dev)))
1173 return;
1174
1175 if (HAS_PCH_SPLIT(dev)) {
1176 u32 port_sel;
1177
1178 pp_reg = PCH_PP_CONTROL;
1179 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1180
1181 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1182 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1183 panel_pipe = PIPE_B;
1184 /* XXX: else fix for eDP */
1185 } else if (IS_VALLEYVIEW(dev)) {
1186 /* presumably write lock depends on pipe, not port select */
1187 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1188 panel_pipe = pipe;
1189 } else {
1190 pp_reg = PP_CONTROL;
1191 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1192 panel_pipe = PIPE_B;
1193 }
1194
1195 val = I915_READ(pp_reg);
1196 if (!(val & PANEL_POWER_ON) ||
1197 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1198 locked = false;
1199
1200 I915_STATE_WARN(panel_pipe == pipe && locked,
1201 "panel assertion failure, pipe %c regs locked\n",
1202 pipe_name(pipe));
1203 }
1204
1205 static void assert_cursor(struct drm_i915_private *dev_priv,
1206 enum pipe pipe, bool state)
1207 {
1208 struct drm_device *dev = dev_priv->dev;
1209 bool cur_state;
1210
1211 if (IS_845G(dev) || IS_I865G(dev))
1212 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1213 else
1214 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1215
1216 I915_STATE_WARN(cur_state != state,
1217 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1218 pipe_name(pipe), state_string(state), state_string(cur_state));
1219 }
1220 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1221 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1222
1223 void assert_pipe(struct drm_i915_private *dev_priv,
1224 enum pipe pipe, bool state)
1225 {
1226 int reg;
1227 u32 val;
1228 bool cur_state;
1229 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1230 pipe);
1231
1232 /* if we need the pipe quirk it must be always on */
1233 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1234 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1235 state = true;
1236
1237 if (!intel_display_power_is_enabled(dev_priv,
1238 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1239 cur_state = false;
1240 } else {
1241 reg = PIPECONF(cpu_transcoder);
1242 val = I915_READ(reg);
1243 cur_state = !!(val & PIPECONF_ENABLE);
1244 }
1245
1246 I915_STATE_WARN(cur_state != state,
1247 "pipe %c assertion failure (expected %s, current %s)\n",
1248 pipe_name(pipe), state_string(state), state_string(cur_state));
1249 }
1250
1251 static void assert_plane(struct drm_i915_private *dev_priv,
1252 enum plane plane, bool state)
1253 {
1254 int reg;
1255 u32 val;
1256 bool cur_state;
1257
1258 reg = DSPCNTR(plane);
1259 val = I915_READ(reg);
1260 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1261 I915_STATE_WARN(cur_state != state,
1262 "plane %c assertion failure (expected %s, current %s)\n",
1263 plane_name(plane), state_string(state), state_string(cur_state));
1264 }
1265
1266 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1267 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1268
1269 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1270 enum pipe pipe)
1271 {
1272 struct drm_device *dev = dev_priv->dev;
1273 int reg, i;
1274 u32 val;
1275 int cur_pipe;
1276
1277 /* Primary planes are fixed to pipes on gen4+ */
1278 if (INTEL_INFO(dev)->gen >= 4) {
1279 reg = DSPCNTR(pipe);
1280 val = I915_READ(reg);
1281 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1282 "plane %c assertion failure, should be disabled but not\n",
1283 plane_name(pipe));
1284 return;
1285 }
1286
1287 /* Need to check both planes against the pipe */
1288 for_each_pipe(dev_priv, i) {
1289 reg = DSPCNTR(i);
1290 val = I915_READ(reg);
1291 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1292 DISPPLANE_SEL_PIPE_SHIFT;
1293 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1294 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1295 plane_name(i), pipe_name(pipe));
1296 }
1297 }
1298
1299 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1300 enum pipe pipe)
1301 {
1302 struct drm_device *dev = dev_priv->dev;
1303 int reg, sprite;
1304 u32 val;
1305
1306 if (INTEL_INFO(dev)->gen >= 9) {
1307 for_each_sprite(dev_priv, pipe, sprite) {
1308 val = I915_READ(PLANE_CTL(pipe, sprite));
1309 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1310 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1311 sprite, pipe_name(pipe));
1312 }
1313 } else if (IS_VALLEYVIEW(dev)) {
1314 for_each_sprite(dev_priv, pipe, sprite) {
1315 reg = SPCNTR(pipe, sprite);
1316 val = I915_READ(reg);
1317 I915_STATE_WARN(val & SP_ENABLE,
1318 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1319 sprite_name(pipe, sprite), pipe_name(pipe));
1320 }
1321 } else if (INTEL_INFO(dev)->gen >= 7) {
1322 reg = SPRCTL(pipe);
1323 val = I915_READ(reg);
1324 I915_STATE_WARN(val & SPRITE_ENABLE,
1325 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1326 plane_name(pipe), pipe_name(pipe));
1327 } else if (INTEL_INFO(dev)->gen >= 5) {
1328 reg = DVSCNTR(pipe);
1329 val = I915_READ(reg);
1330 I915_STATE_WARN(val & DVS_ENABLE,
1331 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1332 plane_name(pipe), pipe_name(pipe));
1333 }
1334 }
1335
1336 static void assert_vblank_disabled(struct drm_crtc *crtc)
1337 {
1338 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1339 drm_crtc_vblank_put(crtc);
1340 }
1341
1342 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1343 {
1344 u32 val;
1345 bool enabled;
1346
1347 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1348
1349 val = I915_READ(PCH_DREF_CONTROL);
1350 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1351 DREF_SUPERSPREAD_SOURCE_MASK));
1352 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1353 }
1354
1355 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1356 enum pipe pipe)
1357 {
1358 int reg;
1359 u32 val;
1360 bool enabled;
1361
1362 reg = PCH_TRANSCONF(pipe);
1363 val = I915_READ(reg);
1364 enabled = !!(val & TRANS_ENABLE);
1365 I915_STATE_WARN(enabled,
1366 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1367 pipe_name(pipe));
1368 }
1369
1370 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1371 enum pipe pipe, u32 port_sel, u32 val)
1372 {
1373 if ((val & DP_PORT_EN) == 0)
1374 return false;
1375
1376 if (HAS_PCH_CPT(dev_priv->dev)) {
1377 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1378 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1379 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1380 return false;
1381 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1382 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1383 return false;
1384 } else {
1385 if ((val & DP_PIPE_MASK) != (pipe << 30))
1386 return false;
1387 }
1388 return true;
1389 }
1390
1391 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1392 enum pipe pipe, u32 val)
1393 {
1394 if ((val & SDVO_ENABLE) == 0)
1395 return false;
1396
1397 if (HAS_PCH_CPT(dev_priv->dev)) {
1398 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1399 return false;
1400 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1401 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1402 return false;
1403 } else {
1404 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1405 return false;
1406 }
1407 return true;
1408 }
1409
1410 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1411 enum pipe pipe, u32 val)
1412 {
1413 if ((val & LVDS_PORT_EN) == 0)
1414 return false;
1415
1416 if (HAS_PCH_CPT(dev_priv->dev)) {
1417 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1418 return false;
1419 } else {
1420 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1421 return false;
1422 }
1423 return true;
1424 }
1425
1426 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1427 enum pipe pipe, u32 val)
1428 {
1429 if ((val & ADPA_DAC_ENABLE) == 0)
1430 return false;
1431 if (HAS_PCH_CPT(dev_priv->dev)) {
1432 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1433 return false;
1434 } else {
1435 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1436 return false;
1437 }
1438 return true;
1439 }
1440
1441 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1442 enum pipe pipe, int reg, u32 port_sel)
1443 {
1444 u32 val = I915_READ(reg);
1445 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1446 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1447 reg, pipe_name(pipe));
1448
1449 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1450 && (val & DP_PIPEB_SELECT),
1451 "IBX PCH dp port still using transcoder B\n");
1452 }
1453
1454 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1455 enum pipe pipe, int reg)
1456 {
1457 u32 val = I915_READ(reg);
1458 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1459 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1460 reg, pipe_name(pipe));
1461
1462 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1463 && (val & SDVO_PIPE_B_SELECT),
1464 "IBX PCH hdmi port still using transcoder B\n");
1465 }
1466
1467 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1468 enum pipe pipe)
1469 {
1470 int reg;
1471 u32 val;
1472
1473 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1474 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1475 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1476
1477 reg = PCH_ADPA;
1478 val = I915_READ(reg);
1479 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1480 "PCH VGA enabled on transcoder %c, should be disabled\n",
1481 pipe_name(pipe));
1482
1483 reg = PCH_LVDS;
1484 val = I915_READ(reg);
1485 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1486 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1487 pipe_name(pipe));
1488
1489 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1490 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1491 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1492 }
1493
1494 static void intel_init_dpio(struct drm_device *dev)
1495 {
1496 struct drm_i915_private *dev_priv = dev->dev_private;
1497
1498 if (!IS_VALLEYVIEW(dev))
1499 return;
1500
1501 /*
1502 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1503 * CHV x1 PHY (DP/HDMI D)
1504 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1505 */
1506 if (IS_CHERRYVIEW(dev)) {
1507 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1508 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1509 } else {
1510 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1511 }
1512 }
1513
1514 static void vlv_enable_pll(struct intel_crtc *crtc,
1515 const struct intel_crtc_state *pipe_config)
1516 {
1517 struct drm_device *dev = crtc->base.dev;
1518 struct drm_i915_private *dev_priv = dev->dev_private;
1519 int reg = DPLL(crtc->pipe);
1520 u32 dpll = pipe_config->dpll_hw_state.dpll;
1521
1522 assert_pipe_disabled(dev_priv, crtc->pipe);
1523
1524 /* No really, not for ILK+ */
1525 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1526
1527 /* PLL is protected by panel, make sure we can write it */
1528 if (IS_MOBILE(dev_priv->dev))
1529 assert_panel_unlocked(dev_priv, crtc->pipe);
1530
1531 I915_WRITE(reg, dpll);
1532 POSTING_READ(reg);
1533 udelay(150);
1534
1535 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1536 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1537
1538 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1539 POSTING_READ(DPLL_MD(crtc->pipe));
1540
1541 /* We do this three times for luck */
1542 I915_WRITE(reg, dpll);
1543 POSTING_READ(reg);
1544 udelay(150); /* wait for warmup */
1545 I915_WRITE(reg, dpll);
1546 POSTING_READ(reg);
1547 udelay(150); /* wait for warmup */
1548 I915_WRITE(reg, dpll);
1549 POSTING_READ(reg);
1550 udelay(150); /* wait for warmup */
1551 }
1552
1553 static void chv_enable_pll(struct intel_crtc *crtc,
1554 const struct intel_crtc_state *pipe_config)
1555 {
1556 struct drm_device *dev = crtc->base.dev;
1557 struct drm_i915_private *dev_priv = dev->dev_private;
1558 int pipe = crtc->pipe;
1559 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1560 u32 tmp;
1561
1562 assert_pipe_disabled(dev_priv, crtc->pipe);
1563
1564 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1565
1566 mutex_lock(&dev_priv->dpio_lock);
1567
1568 /* Enable back the 10bit clock to display controller */
1569 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1570 tmp |= DPIO_DCLKP_EN;
1571 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1572
1573 /*
1574 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1575 */
1576 udelay(1);
1577
1578 /* Enable PLL */
1579 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1580
1581 /* Check PLL is locked */
1582 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1583 DRM_ERROR("PLL %d failed to lock\n", pipe);
1584
1585 /* not sure when this should be written */
1586 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1587 POSTING_READ(DPLL_MD(pipe));
1588
1589 mutex_unlock(&dev_priv->dpio_lock);
1590 }
1591
1592 static int intel_num_dvo_pipes(struct drm_device *dev)
1593 {
1594 struct intel_crtc *crtc;
1595 int count = 0;
1596
1597 for_each_intel_crtc(dev, crtc)
1598 count += crtc->active &&
1599 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1600
1601 return count;
1602 }
1603
1604 static void i9xx_enable_pll(struct intel_crtc *crtc)
1605 {
1606 struct drm_device *dev = crtc->base.dev;
1607 struct drm_i915_private *dev_priv = dev->dev_private;
1608 int reg = DPLL(crtc->pipe);
1609 u32 dpll = crtc->config->dpll_hw_state.dpll;
1610
1611 assert_pipe_disabled(dev_priv, crtc->pipe);
1612
1613 /* No really, not for ILK+ */
1614 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1615
1616 /* PLL is protected by panel, make sure we can write it */
1617 if (IS_MOBILE(dev) && !IS_I830(dev))
1618 assert_panel_unlocked(dev_priv, crtc->pipe);
1619
1620 /* Enable DVO 2x clock on both PLLs if necessary */
1621 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1622 /*
1623 * It appears to be important that we don't enable this
1624 * for the current pipe before otherwise configuring the
1625 * PLL. No idea how this should be handled if multiple
1626 * DVO outputs are enabled simultaneosly.
1627 */
1628 dpll |= DPLL_DVO_2X_MODE;
1629 I915_WRITE(DPLL(!crtc->pipe),
1630 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1631 }
1632
1633 /* Wait for the clocks to stabilize. */
1634 POSTING_READ(reg);
1635 udelay(150);
1636
1637 if (INTEL_INFO(dev)->gen >= 4) {
1638 I915_WRITE(DPLL_MD(crtc->pipe),
1639 crtc->config->dpll_hw_state.dpll_md);
1640 } else {
1641 /* The pixel multiplier can only be updated once the
1642 * DPLL is enabled and the clocks are stable.
1643 *
1644 * So write it again.
1645 */
1646 I915_WRITE(reg, dpll);
1647 }
1648
1649 /* We do this three times for luck */
1650 I915_WRITE(reg, dpll);
1651 POSTING_READ(reg);
1652 udelay(150); /* wait for warmup */
1653 I915_WRITE(reg, dpll);
1654 POSTING_READ(reg);
1655 udelay(150); /* wait for warmup */
1656 I915_WRITE(reg, dpll);
1657 POSTING_READ(reg);
1658 udelay(150); /* wait for warmup */
1659 }
1660
1661 /**
1662 * i9xx_disable_pll - disable a PLL
1663 * @dev_priv: i915 private structure
1664 * @pipe: pipe PLL to disable
1665 *
1666 * Disable the PLL for @pipe, making sure the pipe is off first.
1667 *
1668 * Note! This is for pre-ILK only.
1669 */
1670 static void i9xx_disable_pll(struct intel_crtc *crtc)
1671 {
1672 struct drm_device *dev = crtc->base.dev;
1673 struct drm_i915_private *dev_priv = dev->dev_private;
1674 enum pipe pipe = crtc->pipe;
1675
1676 /* Disable DVO 2x clock on both PLLs if necessary */
1677 if (IS_I830(dev) &&
1678 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1679 intel_num_dvo_pipes(dev) == 1) {
1680 I915_WRITE(DPLL(PIPE_B),
1681 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1682 I915_WRITE(DPLL(PIPE_A),
1683 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1684 }
1685
1686 /* Don't disable pipe or pipe PLLs if needed */
1687 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1688 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1689 return;
1690
1691 /* Make sure the pipe isn't still relying on us */
1692 assert_pipe_disabled(dev_priv, pipe);
1693
1694 I915_WRITE(DPLL(pipe), 0);
1695 POSTING_READ(DPLL(pipe));
1696 }
1697
1698 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1699 {
1700 u32 val = 0;
1701
1702 /* Make sure the pipe isn't still relying on us */
1703 assert_pipe_disabled(dev_priv, pipe);
1704
1705 /*
1706 * Leave integrated clock source and reference clock enabled for pipe B.
1707 * The latter is needed for VGA hotplug / manual detection.
1708 */
1709 if (pipe == PIPE_B)
1710 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1711 I915_WRITE(DPLL(pipe), val);
1712 POSTING_READ(DPLL(pipe));
1713
1714 }
1715
1716 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1717 {
1718 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1719 u32 val;
1720
1721 /* Make sure the pipe isn't still relying on us */
1722 assert_pipe_disabled(dev_priv, pipe);
1723
1724 /* Set PLL en = 0 */
1725 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1726 if (pipe != PIPE_A)
1727 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1728 I915_WRITE(DPLL(pipe), val);
1729 POSTING_READ(DPLL(pipe));
1730
1731 mutex_lock(&dev_priv->dpio_lock);
1732
1733 /* Disable 10bit clock to display controller */
1734 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1735 val &= ~DPIO_DCLKP_EN;
1736 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1737
1738 /* disable left/right clock distribution */
1739 if (pipe != PIPE_B) {
1740 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1741 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1742 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1743 } else {
1744 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1745 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1746 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1747 }
1748
1749 mutex_unlock(&dev_priv->dpio_lock);
1750 }
1751
1752 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1753 struct intel_digital_port *dport)
1754 {
1755 u32 port_mask;
1756 int dpll_reg;
1757
1758 switch (dport->port) {
1759 case PORT_B:
1760 port_mask = DPLL_PORTB_READY_MASK;
1761 dpll_reg = DPLL(0);
1762 break;
1763 case PORT_C:
1764 port_mask = DPLL_PORTC_READY_MASK;
1765 dpll_reg = DPLL(0);
1766 break;
1767 case PORT_D:
1768 port_mask = DPLL_PORTD_READY_MASK;
1769 dpll_reg = DPIO_PHY_STATUS;
1770 break;
1771 default:
1772 BUG();
1773 }
1774
1775 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1776 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1777 port_name(dport->port), I915_READ(dpll_reg));
1778 }
1779
1780 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1781 {
1782 struct drm_device *dev = crtc->base.dev;
1783 struct drm_i915_private *dev_priv = dev->dev_private;
1784 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1785
1786 if (WARN_ON(pll == NULL))
1787 return;
1788
1789 WARN_ON(!pll->config.crtc_mask);
1790 if (pll->active == 0) {
1791 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1792 WARN_ON(pll->on);
1793 assert_shared_dpll_disabled(dev_priv, pll);
1794
1795 pll->mode_set(dev_priv, pll);
1796 }
1797 }
1798
1799 /**
1800 * intel_enable_shared_dpll - enable PCH PLL
1801 * @dev_priv: i915 private structure
1802 * @pipe: pipe PLL to enable
1803 *
1804 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1805 * drives the transcoder clock.
1806 */
1807 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1808 {
1809 struct drm_device *dev = crtc->base.dev;
1810 struct drm_i915_private *dev_priv = dev->dev_private;
1811 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1812
1813 if (WARN_ON(pll == NULL))
1814 return;
1815
1816 if (WARN_ON(pll->config.crtc_mask == 0))
1817 return;
1818
1819 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1820 pll->name, pll->active, pll->on,
1821 crtc->base.base.id);
1822
1823 if (pll->active++) {
1824 WARN_ON(!pll->on);
1825 assert_shared_dpll_enabled(dev_priv, pll);
1826 return;
1827 }
1828 WARN_ON(pll->on);
1829
1830 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1831
1832 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1833 pll->enable(dev_priv, pll);
1834 pll->on = true;
1835 }
1836
1837 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1838 {
1839 struct drm_device *dev = crtc->base.dev;
1840 struct drm_i915_private *dev_priv = dev->dev_private;
1841 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1842
1843 /* PCH only available on ILK+ */
1844 BUG_ON(INTEL_INFO(dev)->gen < 5);
1845 if (WARN_ON(pll == NULL))
1846 return;
1847
1848 if (WARN_ON(pll->config.crtc_mask == 0))
1849 return;
1850
1851 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1852 pll->name, pll->active, pll->on,
1853 crtc->base.base.id);
1854
1855 if (WARN_ON(pll->active == 0)) {
1856 assert_shared_dpll_disabled(dev_priv, pll);
1857 return;
1858 }
1859
1860 assert_shared_dpll_enabled(dev_priv, pll);
1861 WARN_ON(!pll->on);
1862 if (--pll->active)
1863 return;
1864
1865 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1866 pll->disable(dev_priv, pll);
1867 pll->on = false;
1868
1869 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1870 }
1871
1872 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1873 enum pipe pipe)
1874 {
1875 struct drm_device *dev = dev_priv->dev;
1876 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1877 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1878 uint32_t reg, val, pipeconf_val;
1879
1880 /* PCH only available on ILK+ */
1881 BUG_ON(!HAS_PCH_SPLIT(dev));
1882
1883 /* Make sure PCH DPLL is enabled */
1884 assert_shared_dpll_enabled(dev_priv,
1885 intel_crtc_to_shared_dpll(intel_crtc));
1886
1887 /* FDI must be feeding us bits for PCH ports */
1888 assert_fdi_tx_enabled(dev_priv, pipe);
1889 assert_fdi_rx_enabled(dev_priv, pipe);
1890
1891 if (HAS_PCH_CPT(dev)) {
1892 /* Workaround: Set the timing override bit before enabling the
1893 * pch transcoder. */
1894 reg = TRANS_CHICKEN2(pipe);
1895 val = I915_READ(reg);
1896 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1897 I915_WRITE(reg, val);
1898 }
1899
1900 reg = PCH_TRANSCONF(pipe);
1901 val = I915_READ(reg);
1902 pipeconf_val = I915_READ(PIPECONF(pipe));
1903
1904 if (HAS_PCH_IBX(dev_priv->dev)) {
1905 /*
1906 * make the BPC in transcoder be consistent with
1907 * that in pipeconf reg.
1908 */
1909 val &= ~PIPECONF_BPC_MASK;
1910 val |= pipeconf_val & PIPECONF_BPC_MASK;
1911 }
1912
1913 val &= ~TRANS_INTERLACE_MASK;
1914 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1915 if (HAS_PCH_IBX(dev_priv->dev) &&
1916 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1917 val |= TRANS_LEGACY_INTERLACED_ILK;
1918 else
1919 val |= TRANS_INTERLACED;
1920 else
1921 val |= TRANS_PROGRESSIVE;
1922
1923 I915_WRITE(reg, val | TRANS_ENABLE);
1924 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1925 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1926 }
1927
1928 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1929 enum transcoder cpu_transcoder)
1930 {
1931 u32 val, pipeconf_val;
1932
1933 /* PCH only available on ILK+ */
1934 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1935
1936 /* FDI must be feeding us bits for PCH ports */
1937 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1938 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1939
1940 /* Workaround: set timing override bit. */
1941 val = I915_READ(_TRANSA_CHICKEN2);
1942 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1943 I915_WRITE(_TRANSA_CHICKEN2, val);
1944
1945 val = TRANS_ENABLE;
1946 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1947
1948 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1949 PIPECONF_INTERLACED_ILK)
1950 val |= TRANS_INTERLACED;
1951 else
1952 val |= TRANS_PROGRESSIVE;
1953
1954 I915_WRITE(LPT_TRANSCONF, val);
1955 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1956 DRM_ERROR("Failed to enable PCH transcoder\n");
1957 }
1958
1959 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1960 enum pipe pipe)
1961 {
1962 struct drm_device *dev = dev_priv->dev;
1963 uint32_t reg, val;
1964
1965 /* FDI relies on the transcoder */
1966 assert_fdi_tx_disabled(dev_priv, pipe);
1967 assert_fdi_rx_disabled(dev_priv, pipe);
1968
1969 /* Ports must be off as well */
1970 assert_pch_ports_disabled(dev_priv, pipe);
1971
1972 reg = PCH_TRANSCONF(pipe);
1973 val = I915_READ(reg);
1974 val &= ~TRANS_ENABLE;
1975 I915_WRITE(reg, val);
1976 /* wait for PCH transcoder off, transcoder state */
1977 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1978 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1979
1980 if (!HAS_PCH_IBX(dev)) {
1981 /* Workaround: Clear the timing override chicken bit again. */
1982 reg = TRANS_CHICKEN2(pipe);
1983 val = I915_READ(reg);
1984 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1985 I915_WRITE(reg, val);
1986 }
1987 }
1988
1989 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1990 {
1991 u32 val;
1992
1993 val = I915_READ(LPT_TRANSCONF);
1994 val &= ~TRANS_ENABLE;
1995 I915_WRITE(LPT_TRANSCONF, val);
1996 /* wait for PCH transcoder off, transcoder state */
1997 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1998 DRM_ERROR("Failed to disable PCH transcoder\n");
1999
2000 /* Workaround: clear timing override bit. */
2001 val = I915_READ(_TRANSA_CHICKEN2);
2002 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2003 I915_WRITE(_TRANSA_CHICKEN2, val);
2004 }
2005
2006 /**
2007 * intel_enable_pipe - enable a pipe, asserting requirements
2008 * @crtc: crtc responsible for the pipe
2009 *
2010 * Enable @crtc's pipe, making sure that various hardware specific requirements
2011 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2012 */
2013 static void intel_enable_pipe(struct intel_crtc *crtc)
2014 {
2015 struct drm_device *dev = crtc->base.dev;
2016 struct drm_i915_private *dev_priv = dev->dev_private;
2017 enum pipe pipe = crtc->pipe;
2018 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2019 pipe);
2020 enum pipe pch_transcoder;
2021 int reg;
2022 u32 val;
2023
2024 assert_planes_disabled(dev_priv, pipe);
2025 assert_cursor_disabled(dev_priv, pipe);
2026 assert_sprites_disabled(dev_priv, pipe);
2027
2028 if (HAS_PCH_LPT(dev_priv->dev))
2029 pch_transcoder = TRANSCODER_A;
2030 else
2031 pch_transcoder = pipe;
2032
2033 /*
2034 * A pipe without a PLL won't actually be able to drive bits from
2035 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2036 * need the check.
2037 */
2038 if (!HAS_PCH_SPLIT(dev_priv->dev))
2039 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2040 assert_dsi_pll_enabled(dev_priv);
2041 else
2042 assert_pll_enabled(dev_priv, pipe);
2043 else {
2044 if (crtc->config->has_pch_encoder) {
2045 /* if driving the PCH, we need FDI enabled */
2046 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2047 assert_fdi_tx_pll_enabled(dev_priv,
2048 (enum pipe) cpu_transcoder);
2049 }
2050 /* FIXME: assert CPU port conditions for SNB+ */
2051 }
2052
2053 reg = PIPECONF(cpu_transcoder);
2054 val = I915_READ(reg);
2055 if (val & PIPECONF_ENABLE) {
2056 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2057 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2058 return;
2059 }
2060
2061 I915_WRITE(reg, val | PIPECONF_ENABLE);
2062 POSTING_READ(reg);
2063 }
2064
2065 /**
2066 * intel_disable_pipe - disable a pipe, asserting requirements
2067 * @crtc: crtc whose pipes is to be disabled
2068 *
2069 * Disable the pipe of @crtc, making sure that various hardware
2070 * specific requirements are met, if applicable, e.g. plane
2071 * disabled, panel fitter off, etc.
2072 *
2073 * Will wait until the pipe has shut down before returning.
2074 */
2075 static void intel_disable_pipe(struct intel_crtc *crtc)
2076 {
2077 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2078 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2079 enum pipe pipe = crtc->pipe;
2080 int reg;
2081 u32 val;
2082
2083 /*
2084 * Make sure planes won't keep trying to pump pixels to us,
2085 * or we might hang the display.
2086 */
2087 assert_planes_disabled(dev_priv, pipe);
2088 assert_cursor_disabled(dev_priv, pipe);
2089 assert_sprites_disabled(dev_priv, pipe);
2090
2091 reg = PIPECONF(cpu_transcoder);
2092 val = I915_READ(reg);
2093 if ((val & PIPECONF_ENABLE) == 0)
2094 return;
2095
2096 /*
2097 * Double wide has implications for planes
2098 * so best keep it disabled when not needed.
2099 */
2100 if (crtc->config->double_wide)
2101 val &= ~PIPECONF_DOUBLE_WIDE;
2102
2103 /* Don't disable pipe or pipe PLLs if needed */
2104 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2105 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2106 val &= ~PIPECONF_ENABLE;
2107
2108 I915_WRITE(reg, val);
2109 if ((val & PIPECONF_ENABLE) == 0)
2110 intel_wait_for_pipe_off(crtc);
2111 }
2112
2113 /*
2114 * Plane regs are double buffered, going from enabled->disabled needs a
2115 * trigger in order to latch. The display address reg provides this.
2116 */
2117 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2118 enum plane plane)
2119 {
2120 struct drm_device *dev = dev_priv->dev;
2121 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2122
2123 I915_WRITE(reg, I915_READ(reg));
2124 POSTING_READ(reg);
2125 }
2126
2127 /**
2128 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2129 * @plane: plane to be enabled
2130 * @crtc: crtc for the plane
2131 *
2132 * Enable @plane on @crtc, making sure that the pipe is running first.
2133 */
2134 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2135 struct drm_crtc *crtc)
2136 {
2137 struct drm_device *dev = plane->dev;
2138 struct drm_i915_private *dev_priv = dev->dev_private;
2139 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2140
2141 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2142 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2143
2144 if (intel_crtc->primary_enabled)
2145 return;
2146
2147 intel_crtc->primary_enabled = true;
2148
2149 dev_priv->display.update_primary_plane(crtc, plane->fb,
2150 crtc->x, crtc->y);
2151
2152 /*
2153 * BDW signals flip done immediately if the plane
2154 * is disabled, even if the plane enable is already
2155 * armed to occur at the next vblank :(
2156 */
2157 if (IS_BROADWELL(dev))
2158 intel_wait_for_vblank(dev, intel_crtc->pipe);
2159 }
2160
2161 /**
2162 * intel_disable_primary_hw_plane - disable the primary hardware plane
2163 * @plane: plane to be disabled
2164 * @crtc: crtc for the plane
2165 *
2166 * Disable @plane on @crtc, making sure that the pipe is running first.
2167 */
2168 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2169 struct drm_crtc *crtc)
2170 {
2171 struct drm_device *dev = plane->dev;
2172 struct drm_i915_private *dev_priv = dev->dev_private;
2173 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2174
2175 if (WARN_ON(!intel_crtc->active))
2176 return;
2177
2178 if (!intel_crtc->primary_enabled)
2179 return;
2180
2181 intel_crtc->primary_enabled = false;
2182
2183 dev_priv->display.update_primary_plane(crtc, plane->fb,
2184 crtc->x, crtc->y);
2185 }
2186
2187 static bool need_vtd_wa(struct drm_device *dev)
2188 {
2189 #ifdef CONFIG_INTEL_IOMMU
2190 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2191 return true;
2192 #endif
2193 return false;
2194 }
2195
2196 int
2197 intel_fb_align_height(struct drm_device *dev, int height,
2198 uint32_t pixel_format,
2199 uint64_t fb_format_modifier)
2200 {
2201 int tile_height;
2202 uint32_t bits_per_pixel;
2203
2204 switch (fb_format_modifier) {
2205 case DRM_FORMAT_MOD_NONE:
2206 tile_height = 1;
2207 break;
2208 case I915_FORMAT_MOD_X_TILED:
2209 tile_height = IS_GEN2(dev) ? 16 : 8;
2210 break;
2211 case I915_FORMAT_MOD_Y_TILED:
2212 tile_height = 32;
2213 break;
2214 case I915_FORMAT_MOD_Yf_TILED:
2215 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2216 switch (bits_per_pixel) {
2217 default:
2218 case 8:
2219 tile_height = 64;
2220 break;
2221 case 16:
2222 case 32:
2223 tile_height = 32;
2224 break;
2225 case 64:
2226 tile_height = 16;
2227 break;
2228 case 128:
2229 WARN_ONCE(1,
2230 "128-bit pixels are not supported for display!");
2231 tile_height = 16;
2232 break;
2233 }
2234 break;
2235 default:
2236 MISSING_CASE(fb_format_modifier);
2237 tile_height = 1;
2238 break;
2239 }
2240
2241 return ALIGN(height, tile_height);
2242 }
2243
2244 int
2245 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2246 struct drm_framebuffer *fb,
2247 struct intel_engine_cs *pipelined)
2248 {
2249 struct drm_device *dev = fb->dev;
2250 struct drm_i915_private *dev_priv = dev->dev_private;
2251 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2252 u32 alignment;
2253 int ret;
2254
2255 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2256
2257 switch (fb->modifier[0]) {
2258 case DRM_FORMAT_MOD_NONE:
2259 if (INTEL_INFO(dev)->gen >= 9)
2260 alignment = 256 * 1024;
2261 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2262 alignment = 128 * 1024;
2263 else if (INTEL_INFO(dev)->gen >= 4)
2264 alignment = 4 * 1024;
2265 else
2266 alignment = 64 * 1024;
2267 break;
2268 case I915_FORMAT_MOD_X_TILED:
2269 if (INTEL_INFO(dev)->gen >= 9)
2270 alignment = 256 * 1024;
2271 else {
2272 /* pin() will align the object as required by fence */
2273 alignment = 0;
2274 }
2275 break;
2276 case I915_FORMAT_MOD_Y_TILED:
2277 case I915_FORMAT_MOD_Yf_TILED:
2278 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2279 "Y tiling bo slipped through, driver bug!\n"))
2280 return -EINVAL;
2281 alignment = 1 * 1024 * 1024;
2282 break;
2283 default:
2284 MISSING_CASE(fb->modifier[0]);
2285 return -EINVAL;
2286 }
2287
2288 /* Note that the w/a also requires 64 PTE of padding following the
2289 * bo. We currently fill all unused PTE with the shadow page and so
2290 * we should always have valid PTE following the scanout preventing
2291 * the VT-d warning.
2292 */
2293 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2294 alignment = 256 * 1024;
2295
2296 /*
2297 * Global gtt pte registers are special registers which actually forward
2298 * writes to a chunk of system memory. Which means that there is no risk
2299 * that the register values disappear as soon as we call
2300 * intel_runtime_pm_put(), so it is correct to wrap only the
2301 * pin/unpin/fence and not more.
2302 */
2303 intel_runtime_pm_get(dev_priv);
2304
2305 dev_priv->mm.interruptible = false;
2306 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2307 if (ret)
2308 goto err_interruptible;
2309
2310 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2311 * fence, whereas 965+ only requires a fence if using
2312 * framebuffer compression. For simplicity, we always install
2313 * a fence as the cost is not that onerous.
2314 */
2315 ret = i915_gem_object_get_fence(obj);
2316 if (ret)
2317 goto err_unpin;
2318
2319 i915_gem_object_pin_fence(obj);
2320
2321 dev_priv->mm.interruptible = true;
2322 intel_runtime_pm_put(dev_priv);
2323 return 0;
2324
2325 err_unpin:
2326 i915_gem_object_unpin_from_display_plane(obj);
2327 err_interruptible:
2328 dev_priv->mm.interruptible = true;
2329 intel_runtime_pm_put(dev_priv);
2330 return ret;
2331 }
2332
2333 static void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2334 {
2335 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2336
2337 i915_gem_object_unpin_fence(obj);
2338 i915_gem_object_unpin_from_display_plane(obj);
2339 }
2340
2341 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2342 * is assumed to be a power-of-two. */
2343 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2344 unsigned int tiling_mode,
2345 unsigned int cpp,
2346 unsigned int pitch)
2347 {
2348 if (tiling_mode != I915_TILING_NONE) {
2349 unsigned int tile_rows, tiles;
2350
2351 tile_rows = *y / 8;
2352 *y %= 8;
2353
2354 tiles = *x / (512/cpp);
2355 *x %= 512/cpp;
2356
2357 return tile_rows * pitch * 8 + tiles * 4096;
2358 } else {
2359 unsigned int offset;
2360
2361 offset = *y * pitch + *x * cpp;
2362 *y = 0;
2363 *x = (offset & 4095) / cpp;
2364 return offset & -4096;
2365 }
2366 }
2367
2368 static int i9xx_format_to_fourcc(int format)
2369 {
2370 switch (format) {
2371 case DISPPLANE_8BPP:
2372 return DRM_FORMAT_C8;
2373 case DISPPLANE_BGRX555:
2374 return DRM_FORMAT_XRGB1555;
2375 case DISPPLANE_BGRX565:
2376 return DRM_FORMAT_RGB565;
2377 default:
2378 case DISPPLANE_BGRX888:
2379 return DRM_FORMAT_XRGB8888;
2380 case DISPPLANE_RGBX888:
2381 return DRM_FORMAT_XBGR8888;
2382 case DISPPLANE_BGRX101010:
2383 return DRM_FORMAT_XRGB2101010;
2384 case DISPPLANE_RGBX101010:
2385 return DRM_FORMAT_XBGR2101010;
2386 }
2387 }
2388
2389 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2390 {
2391 switch (format) {
2392 case PLANE_CTL_FORMAT_RGB_565:
2393 return DRM_FORMAT_RGB565;
2394 default:
2395 case PLANE_CTL_FORMAT_XRGB_8888:
2396 if (rgb_order) {
2397 if (alpha)
2398 return DRM_FORMAT_ABGR8888;
2399 else
2400 return DRM_FORMAT_XBGR8888;
2401 } else {
2402 if (alpha)
2403 return DRM_FORMAT_ARGB8888;
2404 else
2405 return DRM_FORMAT_XRGB8888;
2406 }
2407 case PLANE_CTL_FORMAT_XRGB_2101010:
2408 if (rgb_order)
2409 return DRM_FORMAT_XBGR2101010;
2410 else
2411 return DRM_FORMAT_XRGB2101010;
2412 }
2413 }
2414
2415 static bool
2416 intel_alloc_plane_obj(struct intel_crtc *crtc,
2417 struct intel_initial_plane_config *plane_config)
2418 {
2419 struct drm_device *dev = crtc->base.dev;
2420 struct drm_i915_gem_object *obj = NULL;
2421 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2422 struct drm_framebuffer *fb = &plane_config->fb->base;
2423 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2424 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2425 PAGE_SIZE);
2426
2427 size_aligned -= base_aligned;
2428
2429 if (plane_config->size == 0)
2430 return false;
2431
2432 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2433 base_aligned,
2434 base_aligned,
2435 size_aligned);
2436 if (!obj)
2437 return false;
2438
2439 obj->tiling_mode = plane_config->tiling;
2440 if (obj->tiling_mode == I915_TILING_X)
2441 obj->stride = fb->pitches[0];
2442
2443 mode_cmd.pixel_format = fb->pixel_format;
2444 mode_cmd.width = fb->width;
2445 mode_cmd.height = fb->height;
2446 mode_cmd.pitches[0] = fb->pitches[0];
2447 mode_cmd.modifier[0] = fb->modifier[0];
2448 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2449
2450 mutex_lock(&dev->struct_mutex);
2451
2452 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2453 &mode_cmd, obj)) {
2454 DRM_DEBUG_KMS("intel fb init failed\n");
2455 goto out_unref_obj;
2456 }
2457
2458 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2459 mutex_unlock(&dev->struct_mutex);
2460
2461 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2462 return true;
2463
2464 out_unref_obj:
2465 drm_gem_object_unreference(&obj->base);
2466 mutex_unlock(&dev->struct_mutex);
2467 return false;
2468 }
2469
2470 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2471 static void
2472 update_state_fb(struct drm_plane *plane)
2473 {
2474 if (plane->fb == plane->state->fb)
2475 return;
2476
2477 if (plane->state->fb)
2478 drm_framebuffer_unreference(plane->state->fb);
2479 plane->state->fb = plane->fb;
2480 if (plane->state->fb)
2481 drm_framebuffer_reference(plane->state->fb);
2482 }
2483
2484 static void
2485 intel_find_plane_obj(struct intel_crtc *intel_crtc,
2486 struct intel_initial_plane_config *plane_config)
2487 {
2488 struct drm_device *dev = intel_crtc->base.dev;
2489 struct drm_i915_private *dev_priv = dev->dev_private;
2490 struct drm_crtc *c;
2491 struct intel_crtc *i;
2492 struct drm_i915_gem_object *obj;
2493
2494 if (!plane_config->fb)
2495 return;
2496
2497 if (intel_alloc_plane_obj(intel_crtc, plane_config)) {
2498 struct drm_plane *primary = intel_crtc->base.primary;
2499
2500 primary->fb = &plane_config->fb->base;
2501 primary->state->crtc = &intel_crtc->base;
2502 update_state_fb(primary);
2503
2504 return;
2505 }
2506
2507 kfree(plane_config->fb);
2508
2509 /*
2510 * Failed to alloc the obj, check to see if we should share
2511 * an fb with another CRTC instead
2512 */
2513 for_each_crtc(dev, c) {
2514 i = to_intel_crtc(c);
2515
2516 if (c == &intel_crtc->base)
2517 continue;
2518
2519 if (!i->active)
2520 continue;
2521
2522 obj = intel_fb_obj(c->primary->fb);
2523 if (obj == NULL)
2524 continue;
2525
2526 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2527 struct drm_plane *primary = intel_crtc->base.primary;
2528
2529 if (obj->tiling_mode != I915_TILING_NONE)
2530 dev_priv->preserve_bios_swizzle = true;
2531
2532 drm_framebuffer_reference(c->primary->fb);
2533 primary->fb = c->primary->fb;
2534 primary->state->crtc = &intel_crtc->base;
2535 update_state_fb(intel_crtc->base.primary);
2536 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2537 break;
2538 }
2539 }
2540
2541 }
2542
2543 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2544 struct drm_framebuffer *fb,
2545 int x, int y)
2546 {
2547 struct drm_device *dev = crtc->dev;
2548 struct drm_i915_private *dev_priv = dev->dev_private;
2549 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2550 struct drm_i915_gem_object *obj;
2551 int plane = intel_crtc->plane;
2552 unsigned long linear_offset;
2553 u32 dspcntr;
2554 u32 reg = DSPCNTR(plane);
2555 int pixel_size;
2556
2557 if (!intel_crtc->primary_enabled) {
2558 I915_WRITE(reg, 0);
2559 if (INTEL_INFO(dev)->gen >= 4)
2560 I915_WRITE(DSPSURF(plane), 0);
2561 else
2562 I915_WRITE(DSPADDR(plane), 0);
2563 POSTING_READ(reg);
2564 return;
2565 }
2566
2567 obj = intel_fb_obj(fb);
2568 if (WARN_ON(obj == NULL))
2569 return;
2570
2571 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2572
2573 dspcntr = DISPPLANE_GAMMA_ENABLE;
2574
2575 dspcntr |= DISPLAY_PLANE_ENABLE;
2576
2577 if (INTEL_INFO(dev)->gen < 4) {
2578 if (intel_crtc->pipe == PIPE_B)
2579 dspcntr |= DISPPLANE_SEL_PIPE_B;
2580
2581 /* pipesrc and dspsize control the size that is scaled from,
2582 * which should always be the user's requested size.
2583 */
2584 I915_WRITE(DSPSIZE(plane),
2585 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2586 (intel_crtc->config->pipe_src_w - 1));
2587 I915_WRITE(DSPPOS(plane), 0);
2588 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2589 I915_WRITE(PRIMSIZE(plane),
2590 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2591 (intel_crtc->config->pipe_src_w - 1));
2592 I915_WRITE(PRIMPOS(plane), 0);
2593 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2594 }
2595
2596 switch (fb->pixel_format) {
2597 case DRM_FORMAT_C8:
2598 dspcntr |= DISPPLANE_8BPP;
2599 break;
2600 case DRM_FORMAT_XRGB1555:
2601 case DRM_FORMAT_ARGB1555:
2602 dspcntr |= DISPPLANE_BGRX555;
2603 break;
2604 case DRM_FORMAT_RGB565:
2605 dspcntr |= DISPPLANE_BGRX565;
2606 break;
2607 case DRM_FORMAT_XRGB8888:
2608 case DRM_FORMAT_ARGB8888:
2609 dspcntr |= DISPPLANE_BGRX888;
2610 break;
2611 case DRM_FORMAT_XBGR8888:
2612 case DRM_FORMAT_ABGR8888:
2613 dspcntr |= DISPPLANE_RGBX888;
2614 break;
2615 case DRM_FORMAT_XRGB2101010:
2616 case DRM_FORMAT_ARGB2101010:
2617 dspcntr |= DISPPLANE_BGRX101010;
2618 break;
2619 case DRM_FORMAT_XBGR2101010:
2620 case DRM_FORMAT_ABGR2101010:
2621 dspcntr |= DISPPLANE_RGBX101010;
2622 break;
2623 default:
2624 BUG();
2625 }
2626
2627 if (INTEL_INFO(dev)->gen >= 4 &&
2628 obj->tiling_mode != I915_TILING_NONE)
2629 dspcntr |= DISPPLANE_TILED;
2630
2631 if (IS_G4X(dev))
2632 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2633
2634 linear_offset = y * fb->pitches[0] + x * pixel_size;
2635
2636 if (INTEL_INFO(dev)->gen >= 4) {
2637 intel_crtc->dspaddr_offset =
2638 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2639 pixel_size,
2640 fb->pitches[0]);
2641 linear_offset -= intel_crtc->dspaddr_offset;
2642 } else {
2643 intel_crtc->dspaddr_offset = linear_offset;
2644 }
2645
2646 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2647 dspcntr |= DISPPLANE_ROTATE_180;
2648
2649 x += (intel_crtc->config->pipe_src_w - 1);
2650 y += (intel_crtc->config->pipe_src_h - 1);
2651
2652 /* Finding the last pixel of the last line of the display
2653 data and adding to linear_offset*/
2654 linear_offset +=
2655 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2656 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2657 }
2658
2659 I915_WRITE(reg, dspcntr);
2660
2661 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2662 if (INTEL_INFO(dev)->gen >= 4) {
2663 I915_WRITE(DSPSURF(plane),
2664 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2665 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2666 I915_WRITE(DSPLINOFF(plane), linear_offset);
2667 } else
2668 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2669 POSTING_READ(reg);
2670 }
2671
2672 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2673 struct drm_framebuffer *fb,
2674 int x, int y)
2675 {
2676 struct drm_device *dev = crtc->dev;
2677 struct drm_i915_private *dev_priv = dev->dev_private;
2678 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2679 struct drm_i915_gem_object *obj;
2680 int plane = intel_crtc->plane;
2681 unsigned long linear_offset;
2682 u32 dspcntr;
2683 u32 reg = DSPCNTR(plane);
2684 int pixel_size;
2685
2686 if (!intel_crtc->primary_enabled) {
2687 I915_WRITE(reg, 0);
2688 I915_WRITE(DSPSURF(plane), 0);
2689 POSTING_READ(reg);
2690 return;
2691 }
2692
2693 obj = intel_fb_obj(fb);
2694 if (WARN_ON(obj == NULL))
2695 return;
2696
2697 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2698
2699 dspcntr = DISPPLANE_GAMMA_ENABLE;
2700
2701 dspcntr |= DISPLAY_PLANE_ENABLE;
2702
2703 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2704 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2705
2706 switch (fb->pixel_format) {
2707 case DRM_FORMAT_C8:
2708 dspcntr |= DISPPLANE_8BPP;
2709 break;
2710 case DRM_FORMAT_RGB565:
2711 dspcntr |= DISPPLANE_BGRX565;
2712 break;
2713 case DRM_FORMAT_XRGB8888:
2714 case DRM_FORMAT_ARGB8888:
2715 dspcntr |= DISPPLANE_BGRX888;
2716 break;
2717 case DRM_FORMAT_XBGR8888:
2718 case DRM_FORMAT_ABGR8888:
2719 dspcntr |= DISPPLANE_RGBX888;
2720 break;
2721 case DRM_FORMAT_XRGB2101010:
2722 case DRM_FORMAT_ARGB2101010:
2723 dspcntr |= DISPPLANE_BGRX101010;
2724 break;
2725 case DRM_FORMAT_XBGR2101010:
2726 case DRM_FORMAT_ABGR2101010:
2727 dspcntr |= DISPPLANE_RGBX101010;
2728 break;
2729 default:
2730 BUG();
2731 }
2732
2733 if (obj->tiling_mode != I915_TILING_NONE)
2734 dspcntr |= DISPPLANE_TILED;
2735
2736 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2737 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2738
2739 linear_offset = y * fb->pitches[0] + x * pixel_size;
2740 intel_crtc->dspaddr_offset =
2741 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2742 pixel_size,
2743 fb->pitches[0]);
2744 linear_offset -= intel_crtc->dspaddr_offset;
2745 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2746 dspcntr |= DISPPLANE_ROTATE_180;
2747
2748 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2749 x += (intel_crtc->config->pipe_src_w - 1);
2750 y += (intel_crtc->config->pipe_src_h - 1);
2751
2752 /* Finding the last pixel of the last line of the display
2753 data and adding to linear_offset*/
2754 linear_offset +=
2755 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2756 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2757 }
2758 }
2759
2760 I915_WRITE(reg, dspcntr);
2761
2762 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2763 I915_WRITE(DSPSURF(plane),
2764 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2765 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2766 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2767 } else {
2768 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2769 I915_WRITE(DSPLINOFF(plane), linear_offset);
2770 }
2771 POSTING_READ(reg);
2772 }
2773
2774 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2775 uint32_t pixel_format)
2776 {
2777 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2778
2779 /*
2780 * The stride is either expressed as a multiple of 64 bytes
2781 * chunks for linear buffers or in number of tiles for tiled
2782 * buffers.
2783 */
2784 switch (fb_modifier) {
2785 case DRM_FORMAT_MOD_NONE:
2786 return 64;
2787 case I915_FORMAT_MOD_X_TILED:
2788 if (INTEL_INFO(dev)->gen == 2)
2789 return 128;
2790 return 512;
2791 case I915_FORMAT_MOD_Y_TILED:
2792 /* No need to check for old gens and Y tiling since this is
2793 * about the display engine and those will be blocked before
2794 * we get here.
2795 */
2796 return 128;
2797 case I915_FORMAT_MOD_Yf_TILED:
2798 if (bits_per_pixel == 8)
2799 return 64;
2800 else
2801 return 128;
2802 default:
2803 MISSING_CASE(fb_modifier);
2804 return 64;
2805 }
2806 }
2807
2808 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2809 struct drm_framebuffer *fb,
2810 int x, int y)
2811 {
2812 struct drm_device *dev = crtc->dev;
2813 struct drm_i915_private *dev_priv = dev->dev_private;
2814 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2815 struct drm_i915_gem_object *obj;
2816 int pipe = intel_crtc->pipe;
2817 u32 plane_ctl, stride_div;
2818
2819 if (!intel_crtc->primary_enabled) {
2820 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2821 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2822 POSTING_READ(PLANE_CTL(pipe, 0));
2823 return;
2824 }
2825
2826 plane_ctl = PLANE_CTL_ENABLE |
2827 PLANE_CTL_PIPE_GAMMA_ENABLE |
2828 PLANE_CTL_PIPE_CSC_ENABLE;
2829
2830 switch (fb->pixel_format) {
2831 case DRM_FORMAT_RGB565:
2832 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2833 break;
2834 case DRM_FORMAT_XRGB8888:
2835 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2836 break;
2837 case DRM_FORMAT_ARGB8888:
2838 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2839 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2840 break;
2841 case DRM_FORMAT_XBGR8888:
2842 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2843 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2844 break;
2845 case DRM_FORMAT_ABGR8888:
2846 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2847 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2848 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2849 break;
2850 case DRM_FORMAT_XRGB2101010:
2851 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2852 break;
2853 case DRM_FORMAT_XBGR2101010:
2854 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2855 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2856 break;
2857 default:
2858 BUG();
2859 }
2860
2861 switch (fb->modifier[0]) {
2862 case DRM_FORMAT_MOD_NONE:
2863 break;
2864 case I915_FORMAT_MOD_X_TILED:
2865 plane_ctl |= PLANE_CTL_TILED_X;
2866 break;
2867 case I915_FORMAT_MOD_Y_TILED:
2868 plane_ctl |= PLANE_CTL_TILED_Y;
2869 break;
2870 case I915_FORMAT_MOD_Yf_TILED:
2871 plane_ctl |= PLANE_CTL_TILED_YF;
2872 break;
2873 default:
2874 MISSING_CASE(fb->modifier[0]);
2875 }
2876
2877 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2878 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180))
2879 plane_ctl |= PLANE_CTL_ROTATE_180;
2880
2881 obj = intel_fb_obj(fb);
2882 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
2883 fb->pixel_format);
2884
2885 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2886
2887 I915_WRITE(PLANE_POS(pipe, 0), 0);
2888 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2889 I915_WRITE(PLANE_SIZE(pipe, 0),
2890 (intel_crtc->config->pipe_src_h - 1) << 16 |
2891 (intel_crtc->config->pipe_src_w - 1));
2892 I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
2893 I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2894
2895 POSTING_READ(PLANE_SURF(pipe, 0));
2896 }
2897
2898 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2899 static int
2900 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2901 int x, int y, enum mode_set_atomic state)
2902 {
2903 struct drm_device *dev = crtc->dev;
2904 struct drm_i915_private *dev_priv = dev->dev_private;
2905
2906 if (dev_priv->display.disable_fbc)
2907 dev_priv->display.disable_fbc(dev);
2908
2909 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2910
2911 return 0;
2912 }
2913
2914 static void intel_complete_page_flips(struct drm_device *dev)
2915 {
2916 struct drm_crtc *crtc;
2917
2918 for_each_crtc(dev, crtc) {
2919 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2920 enum plane plane = intel_crtc->plane;
2921
2922 intel_prepare_page_flip(dev, plane);
2923 intel_finish_page_flip_plane(dev, plane);
2924 }
2925 }
2926
2927 static void intel_update_primary_planes(struct drm_device *dev)
2928 {
2929 struct drm_i915_private *dev_priv = dev->dev_private;
2930 struct drm_crtc *crtc;
2931
2932 for_each_crtc(dev, crtc) {
2933 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2934
2935 drm_modeset_lock(&crtc->mutex, NULL);
2936 /*
2937 * FIXME: Once we have proper support for primary planes (and
2938 * disabling them without disabling the entire crtc) allow again
2939 * a NULL crtc->primary->fb.
2940 */
2941 if (intel_crtc->active && crtc->primary->fb)
2942 dev_priv->display.update_primary_plane(crtc,
2943 crtc->primary->fb,
2944 crtc->x,
2945 crtc->y);
2946 drm_modeset_unlock(&crtc->mutex);
2947 }
2948 }
2949
2950 void intel_prepare_reset(struct drm_device *dev)
2951 {
2952 struct drm_i915_private *dev_priv = to_i915(dev);
2953 struct intel_crtc *crtc;
2954
2955 /* no reset support for gen2 */
2956 if (IS_GEN2(dev))
2957 return;
2958
2959 /* reset doesn't touch the display */
2960 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
2961 return;
2962
2963 drm_modeset_lock_all(dev);
2964
2965 /*
2966 * Disabling the crtcs gracefully seems nicer. Also the
2967 * g33 docs say we should at least disable all the planes.
2968 */
2969 for_each_intel_crtc(dev, crtc) {
2970 if (crtc->active)
2971 dev_priv->display.crtc_disable(&crtc->base);
2972 }
2973 }
2974
2975 void intel_finish_reset(struct drm_device *dev)
2976 {
2977 struct drm_i915_private *dev_priv = to_i915(dev);
2978
2979 /*
2980 * Flips in the rings will be nuked by the reset,
2981 * so complete all pending flips so that user space
2982 * will get its events and not get stuck.
2983 */
2984 intel_complete_page_flips(dev);
2985
2986 /* no reset support for gen2 */
2987 if (IS_GEN2(dev))
2988 return;
2989
2990 /* reset doesn't touch the display */
2991 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
2992 /*
2993 * Flips in the rings have been nuked by the reset,
2994 * so update the base address of all primary
2995 * planes to the the last fb to make sure we're
2996 * showing the correct fb after a reset.
2997 */
2998 intel_update_primary_planes(dev);
2999 return;
3000 }
3001
3002 /*
3003 * The display has been reset as well,
3004 * so need a full re-initialization.
3005 */
3006 intel_runtime_pm_disable_interrupts(dev_priv);
3007 intel_runtime_pm_enable_interrupts(dev_priv);
3008
3009 intel_modeset_init_hw(dev);
3010
3011 spin_lock_irq(&dev_priv->irq_lock);
3012 if (dev_priv->display.hpd_irq_setup)
3013 dev_priv->display.hpd_irq_setup(dev);
3014 spin_unlock_irq(&dev_priv->irq_lock);
3015
3016 intel_modeset_setup_hw_state(dev, true);
3017
3018 intel_hpd_init(dev_priv);
3019
3020 drm_modeset_unlock_all(dev);
3021 }
3022
3023 static int
3024 intel_finish_fb(struct drm_framebuffer *old_fb)
3025 {
3026 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3027 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3028 bool was_interruptible = dev_priv->mm.interruptible;
3029 int ret;
3030
3031 /* Big Hammer, we also need to ensure that any pending
3032 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3033 * current scanout is retired before unpinning the old
3034 * framebuffer.
3035 *
3036 * This should only fail upon a hung GPU, in which case we
3037 * can safely continue.
3038 */
3039 dev_priv->mm.interruptible = false;
3040 ret = i915_gem_object_finish_gpu(obj);
3041 dev_priv->mm.interruptible = was_interruptible;
3042
3043 return ret;
3044 }
3045
3046 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3047 {
3048 struct drm_device *dev = crtc->dev;
3049 struct drm_i915_private *dev_priv = dev->dev_private;
3050 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3051 bool pending;
3052
3053 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3054 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3055 return false;
3056
3057 spin_lock_irq(&dev->event_lock);
3058 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3059 spin_unlock_irq(&dev->event_lock);
3060
3061 return pending;
3062 }
3063
3064 static void intel_update_pipe_size(struct intel_crtc *crtc)
3065 {
3066 struct drm_device *dev = crtc->base.dev;
3067 struct drm_i915_private *dev_priv = dev->dev_private;
3068 const struct drm_display_mode *adjusted_mode;
3069
3070 if (!i915.fastboot)
3071 return;
3072
3073 /*
3074 * Update pipe size and adjust fitter if needed: the reason for this is
3075 * that in compute_mode_changes we check the native mode (not the pfit
3076 * mode) to see if we can flip rather than do a full mode set. In the
3077 * fastboot case, we'll flip, but if we don't update the pipesrc and
3078 * pfit state, we'll end up with a big fb scanned out into the wrong
3079 * sized surface.
3080 *
3081 * To fix this properly, we need to hoist the checks up into
3082 * compute_mode_changes (or above), check the actual pfit state and
3083 * whether the platform allows pfit disable with pipe active, and only
3084 * then update the pipesrc and pfit state, even on the flip path.
3085 */
3086
3087 adjusted_mode = &crtc->config->base.adjusted_mode;
3088
3089 I915_WRITE(PIPESRC(crtc->pipe),
3090 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3091 (adjusted_mode->crtc_vdisplay - 1));
3092 if (!crtc->config->pch_pfit.enabled &&
3093 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3094 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3095 I915_WRITE(PF_CTL(crtc->pipe), 0);
3096 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3097 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3098 }
3099 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3100 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3101 }
3102
3103 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3104 {
3105 struct drm_device *dev = crtc->dev;
3106 struct drm_i915_private *dev_priv = dev->dev_private;
3107 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3108 int pipe = intel_crtc->pipe;
3109 u32 reg, temp;
3110
3111 /* enable normal train */
3112 reg = FDI_TX_CTL(pipe);
3113 temp = I915_READ(reg);
3114 if (IS_IVYBRIDGE(dev)) {
3115 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3116 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3117 } else {
3118 temp &= ~FDI_LINK_TRAIN_NONE;
3119 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3120 }
3121 I915_WRITE(reg, temp);
3122
3123 reg = FDI_RX_CTL(pipe);
3124 temp = I915_READ(reg);
3125 if (HAS_PCH_CPT(dev)) {
3126 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3127 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3128 } else {
3129 temp &= ~FDI_LINK_TRAIN_NONE;
3130 temp |= FDI_LINK_TRAIN_NONE;
3131 }
3132 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3133
3134 /* wait one idle pattern time */
3135 POSTING_READ(reg);
3136 udelay(1000);
3137
3138 /* IVB wants error correction enabled */
3139 if (IS_IVYBRIDGE(dev))
3140 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3141 FDI_FE_ERRC_ENABLE);
3142 }
3143
3144 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
3145 {
3146 return crtc->base.state->enable && crtc->active &&
3147 crtc->config->has_pch_encoder;
3148 }
3149
3150 /* The FDI link training functions for ILK/Ibexpeak. */
3151 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3152 {
3153 struct drm_device *dev = crtc->dev;
3154 struct drm_i915_private *dev_priv = dev->dev_private;
3155 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3156 int pipe = intel_crtc->pipe;
3157 u32 reg, temp, tries;
3158
3159 /* FDI needs bits from pipe first */
3160 assert_pipe_enabled(dev_priv, pipe);
3161
3162 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3163 for train result */
3164 reg = FDI_RX_IMR(pipe);
3165 temp = I915_READ(reg);
3166 temp &= ~FDI_RX_SYMBOL_LOCK;
3167 temp &= ~FDI_RX_BIT_LOCK;
3168 I915_WRITE(reg, temp);
3169 I915_READ(reg);
3170 udelay(150);
3171
3172 /* enable CPU FDI TX and PCH FDI RX */
3173 reg = FDI_TX_CTL(pipe);
3174 temp = I915_READ(reg);
3175 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3176 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3177 temp &= ~FDI_LINK_TRAIN_NONE;
3178 temp |= FDI_LINK_TRAIN_PATTERN_1;
3179 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3180
3181 reg = FDI_RX_CTL(pipe);
3182 temp = I915_READ(reg);
3183 temp &= ~FDI_LINK_TRAIN_NONE;
3184 temp |= FDI_LINK_TRAIN_PATTERN_1;
3185 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3186
3187 POSTING_READ(reg);
3188 udelay(150);
3189
3190 /* Ironlake workaround, enable clock pointer after FDI enable*/
3191 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3192 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3193 FDI_RX_PHASE_SYNC_POINTER_EN);
3194
3195 reg = FDI_RX_IIR(pipe);
3196 for (tries = 0; tries < 5; tries++) {
3197 temp = I915_READ(reg);
3198 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3199
3200 if ((temp & FDI_RX_BIT_LOCK)) {
3201 DRM_DEBUG_KMS("FDI train 1 done.\n");
3202 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3203 break;
3204 }
3205 }
3206 if (tries == 5)
3207 DRM_ERROR("FDI train 1 fail!\n");
3208
3209 /* Train 2 */
3210 reg = FDI_TX_CTL(pipe);
3211 temp = I915_READ(reg);
3212 temp &= ~FDI_LINK_TRAIN_NONE;
3213 temp |= FDI_LINK_TRAIN_PATTERN_2;
3214 I915_WRITE(reg, temp);
3215
3216 reg = FDI_RX_CTL(pipe);
3217 temp = I915_READ(reg);
3218 temp &= ~FDI_LINK_TRAIN_NONE;
3219 temp |= FDI_LINK_TRAIN_PATTERN_2;
3220 I915_WRITE(reg, temp);
3221
3222 POSTING_READ(reg);
3223 udelay(150);
3224
3225 reg = FDI_RX_IIR(pipe);
3226 for (tries = 0; tries < 5; tries++) {
3227 temp = I915_READ(reg);
3228 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3229
3230 if (temp & FDI_RX_SYMBOL_LOCK) {
3231 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3232 DRM_DEBUG_KMS("FDI train 2 done.\n");
3233 break;
3234 }
3235 }
3236 if (tries == 5)
3237 DRM_ERROR("FDI train 2 fail!\n");
3238
3239 DRM_DEBUG_KMS("FDI train done\n");
3240
3241 }
3242
3243 static const int snb_b_fdi_train_param[] = {
3244 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3245 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3246 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3247 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3248 };
3249
3250 /* The FDI link training functions for SNB/Cougarpoint. */
3251 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3252 {
3253 struct drm_device *dev = crtc->dev;
3254 struct drm_i915_private *dev_priv = dev->dev_private;
3255 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3256 int pipe = intel_crtc->pipe;
3257 u32 reg, temp, i, retry;
3258
3259 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3260 for train result */
3261 reg = FDI_RX_IMR(pipe);
3262 temp = I915_READ(reg);
3263 temp &= ~FDI_RX_SYMBOL_LOCK;
3264 temp &= ~FDI_RX_BIT_LOCK;
3265 I915_WRITE(reg, temp);
3266
3267 POSTING_READ(reg);
3268 udelay(150);
3269
3270 /* enable CPU FDI TX and PCH FDI RX */
3271 reg = FDI_TX_CTL(pipe);
3272 temp = I915_READ(reg);
3273 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3274 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3275 temp &= ~FDI_LINK_TRAIN_NONE;
3276 temp |= FDI_LINK_TRAIN_PATTERN_1;
3277 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3278 /* SNB-B */
3279 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3280 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3281
3282 I915_WRITE(FDI_RX_MISC(pipe),
3283 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3284
3285 reg = FDI_RX_CTL(pipe);
3286 temp = I915_READ(reg);
3287 if (HAS_PCH_CPT(dev)) {
3288 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3289 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3290 } else {
3291 temp &= ~FDI_LINK_TRAIN_NONE;
3292 temp |= FDI_LINK_TRAIN_PATTERN_1;
3293 }
3294 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3295
3296 POSTING_READ(reg);
3297 udelay(150);
3298
3299 for (i = 0; i < 4; i++) {
3300 reg = FDI_TX_CTL(pipe);
3301 temp = I915_READ(reg);
3302 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3303 temp |= snb_b_fdi_train_param[i];
3304 I915_WRITE(reg, temp);
3305
3306 POSTING_READ(reg);
3307 udelay(500);
3308
3309 for (retry = 0; retry < 5; retry++) {
3310 reg = FDI_RX_IIR(pipe);
3311 temp = I915_READ(reg);
3312 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3313 if (temp & FDI_RX_BIT_LOCK) {
3314 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3315 DRM_DEBUG_KMS("FDI train 1 done.\n");
3316 break;
3317 }
3318 udelay(50);
3319 }
3320 if (retry < 5)
3321 break;
3322 }
3323 if (i == 4)
3324 DRM_ERROR("FDI train 1 fail!\n");
3325
3326 /* Train 2 */
3327 reg = FDI_TX_CTL(pipe);
3328 temp = I915_READ(reg);
3329 temp &= ~FDI_LINK_TRAIN_NONE;
3330 temp |= FDI_LINK_TRAIN_PATTERN_2;
3331 if (IS_GEN6(dev)) {
3332 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3333 /* SNB-B */
3334 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3335 }
3336 I915_WRITE(reg, temp);
3337
3338 reg = FDI_RX_CTL(pipe);
3339 temp = I915_READ(reg);
3340 if (HAS_PCH_CPT(dev)) {
3341 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3342 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3343 } else {
3344 temp &= ~FDI_LINK_TRAIN_NONE;
3345 temp |= FDI_LINK_TRAIN_PATTERN_2;
3346 }
3347 I915_WRITE(reg, temp);
3348
3349 POSTING_READ(reg);
3350 udelay(150);
3351
3352 for (i = 0; i < 4; i++) {
3353 reg = FDI_TX_CTL(pipe);
3354 temp = I915_READ(reg);
3355 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3356 temp |= snb_b_fdi_train_param[i];
3357 I915_WRITE(reg, temp);
3358
3359 POSTING_READ(reg);
3360 udelay(500);
3361
3362 for (retry = 0; retry < 5; retry++) {
3363 reg = FDI_RX_IIR(pipe);
3364 temp = I915_READ(reg);
3365 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3366 if (temp & FDI_RX_SYMBOL_LOCK) {
3367 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3368 DRM_DEBUG_KMS("FDI train 2 done.\n");
3369 break;
3370 }
3371 udelay(50);
3372 }
3373 if (retry < 5)
3374 break;
3375 }
3376 if (i == 4)
3377 DRM_ERROR("FDI train 2 fail!\n");
3378
3379 DRM_DEBUG_KMS("FDI train done.\n");
3380 }
3381
3382 /* Manual link training for Ivy Bridge A0 parts */
3383 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3384 {
3385 struct drm_device *dev = crtc->dev;
3386 struct drm_i915_private *dev_priv = dev->dev_private;
3387 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3388 int pipe = intel_crtc->pipe;
3389 u32 reg, temp, i, j;
3390
3391 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3392 for train result */
3393 reg = FDI_RX_IMR(pipe);
3394 temp = I915_READ(reg);
3395 temp &= ~FDI_RX_SYMBOL_LOCK;
3396 temp &= ~FDI_RX_BIT_LOCK;
3397 I915_WRITE(reg, temp);
3398
3399 POSTING_READ(reg);
3400 udelay(150);
3401
3402 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3403 I915_READ(FDI_RX_IIR(pipe)));
3404
3405 /* Try each vswing and preemphasis setting twice before moving on */
3406 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3407 /* disable first in case we need to retry */
3408 reg = FDI_TX_CTL(pipe);
3409 temp = I915_READ(reg);
3410 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3411 temp &= ~FDI_TX_ENABLE;
3412 I915_WRITE(reg, temp);
3413
3414 reg = FDI_RX_CTL(pipe);
3415 temp = I915_READ(reg);
3416 temp &= ~FDI_LINK_TRAIN_AUTO;
3417 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3418 temp &= ~FDI_RX_ENABLE;
3419 I915_WRITE(reg, temp);
3420
3421 /* enable CPU FDI TX and PCH FDI RX */
3422 reg = FDI_TX_CTL(pipe);
3423 temp = I915_READ(reg);
3424 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3425 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3426 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3427 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3428 temp |= snb_b_fdi_train_param[j/2];
3429 temp |= FDI_COMPOSITE_SYNC;
3430 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3431
3432 I915_WRITE(FDI_RX_MISC(pipe),
3433 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3434
3435 reg = FDI_RX_CTL(pipe);
3436 temp = I915_READ(reg);
3437 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3438 temp |= FDI_COMPOSITE_SYNC;
3439 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3440
3441 POSTING_READ(reg);
3442 udelay(1); /* should be 0.5us */
3443
3444 for (i = 0; i < 4; i++) {
3445 reg = FDI_RX_IIR(pipe);
3446 temp = I915_READ(reg);
3447 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3448
3449 if (temp & FDI_RX_BIT_LOCK ||
3450 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3451 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3452 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3453 i);
3454 break;
3455 }
3456 udelay(1); /* should be 0.5us */
3457 }
3458 if (i == 4) {
3459 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3460 continue;
3461 }
3462
3463 /* Train 2 */
3464 reg = FDI_TX_CTL(pipe);
3465 temp = I915_READ(reg);
3466 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3467 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3468 I915_WRITE(reg, temp);
3469
3470 reg = FDI_RX_CTL(pipe);
3471 temp = I915_READ(reg);
3472 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3473 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3474 I915_WRITE(reg, temp);
3475
3476 POSTING_READ(reg);
3477 udelay(2); /* should be 1.5us */
3478
3479 for (i = 0; i < 4; i++) {
3480 reg = FDI_RX_IIR(pipe);
3481 temp = I915_READ(reg);
3482 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3483
3484 if (temp & FDI_RX_SYMBOL_LOCK ||
3485 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3486 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3487 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3488 i);
3489 goto train_done;
3490 }
3491 udelay(2); /* should be 1.5us */
3492 }
3493 if (i == 4)
3494 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3495 }
3496
3497 train_done:
3498 DRM_DEBUG_KMS("FDI train done.\n");
3499 }
3500
3501 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3502 {
3503 struct drm_device *dev = intel_crtc->base.dev;
3504 struct drm_i915_private *dev_priv = dev->dev_private;
3505 int pipe = intel_crtc->pipe;
3506 u32 reg, temp;
3507
3508
3509 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3510 reg = FDI_RX_CTL(pipe);
3511 temp = I915_READ(reg);
3512 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3513 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3514 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3515 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3516
3517 POSTING_READ(reg);
3518 udelay(200);
3519
3520 /* Switch from Rawclk to PCDclk */
3521 temp = I915_READ(reg);
3522 I915_WRITE(reg, temp | FDI_PCDCLK);
3523
3524 POSTING_READ(reg);
3525 udelay(200);
3526
3527 /* Enable CPU FDI TX PLL, always on for Ironlake */
3528 reg = FDI_TX_CTL(pipe);
3529 temp = I915_READ(reg);
3530 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3531 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3532
3533 POSTING_READ(reg);
3534 udelay(100);
3535 }
3536 }
3537
3538 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3539 {
3540 struct drm_device *dev = intel_crtc->base.dev;
3541 struct drm_i915_private *dev_priv = dev->dev_private;
3542 int pipe = intel_crtc->pipe;
3543 u32 reg, temp;
3544
3545 /* Switch from PCDclk to Rawclk */
3546 reg = FDI_RX_CTL(pipe);
3547 temp = I915_READ(reg);
3548 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3549
3550 /* Disable CPU FDI TX PLL */
3551 reg = FDI_TX_CTL(pipe);
3552 temp = I915_READ(reg);
3553 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3554
3555 POSTING_READ(reg);
3556 udelay(100);
3557
3558 reg = FDI_RX_CTL(pipe);
3559 temp = I915_READ(reg);
3560 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3561
3562 /* Wait for the clocks to turn off. */
3563 POSTING_READ(reg);
3564 udelay(100);
3565 }
3566
3567 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3568 {
3569 struct drm_device *dev = crtc->dev;
3570 struct drm_i915_private *dev_priv = dev->dev_private;
3571 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3572 int pipe = intel_crtc->pipe;
3573 u32 reg, temp;
3574
3575 /* disable CPU FDI tx and PCH FDI rx */
3576 reg = FDI_TX_CTL(pipe);
3577 temp = I915_READ(reg);
3578 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3579 POSTING_READ(reg);
3580
3581 reg = FDI_RX_CTL(pipe);
3582 temp = I915_READ(reg);
3583 temp &= ~(0x7 << 16);
3584 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3585 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3586
3587 POSTING_READ(reg);
3588 udelay(100);
3589
3590 /* Ironlake workaround, disable clock pointer after downing FDI */
3591 if (HAS_PCH_IBX(dev))
3592 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3593
3594 /* still set train pattern 1 */
3595 reg = FDI_TX_CTL(pipe);
3596 temp = I915_READ(reg);
3597 temp &= ~FDI_LINK_TRAIN_NONE;
3598 temp |= FDI_LINK_TRAIN_PATTERN_1;
3599 I915_WRITE(reg, temp);
3600
3601 reg = FDI_RX_CTL(pipe);
3602 temp = I915_READ(reg);
3603 if (HAS_PCH_CPT(dev)) {
3604 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3605 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3606 } else {
3607 temp &= ~FDI_LINK_TRAIN_NONE;
3608 temp |= FDI_LINK_TRAIN_PATTERN_1;
3609 }
3610 /* BPC in FDI rx is consistent with that in PIPECONF */
3611 temp &= ~(0x07 << 16);
3612 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3613 I915_WRITE(reg, temp);
3614
3615 POSTING_READ(reg);
3616 udelay(100);
3617 }
3618
3619 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3620 {
3621 struct intel_crtc *crtc;
3622
3623 /* Note that we don't need to be called with mode_config.lock here
3624 * as our list of CRTC objects is static for the lifetime of the
3625 * device and so cannot disappear as we iterate. Similarly, we can
3626 * happily treat the predicates as racy, atomic checks as userspace
3627 * cannot claim and pin a new fb without at least acquring the
3628 * struct_mutex and so serialising with us.
3629 */
3630 for_each_intel_crtc(dev, crtc) {
3631 if (atomic_read(&crtc->unpin_work_count) == 0)
3632 continue;
3633
3634 if (crtc->unpin_work)
3635 intel_wait_for_vblank(dev, crtc->pipe);
3636
3637 return true;
3638 }
3639
3640 return false;
3641 }
3642
3643 static void page_flip_completed(struct intel_crtc *intel_crtc)
3644 {
3645 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3646 struct intel_unpin_work *work = intel_crtc->unpin_work;
3647
3648 /* ensure that the unpin work is consistent wrt ->pending. */
3649 smp_rmb();
3650 intel_crtc->unpin_work = NULL;
3651
3652 if (work->event)
3653 drm_send_vblank_event(intel_crtc->base.dev,
3654 intel_crtc->pipe,
3655 work->event);
3656
3657 drm_crtc_vblank_put(&intel_crtc->base);
3658
3659 wake_up_all(&dev_priv->pending_flip_queue);
3660 queue_work(dev_priv->wq, &work->work);
3661
3662 trace_i915_flip_complete(intel_crtc->plane,
3663 work->pending_flip_obj);
3664 }
3665
3666 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3667 {
3668 struct drm_device *dev = crtc->dev;
3669 struct drm_i915_private *dev_priv = dev->dev_private;
3670
3671 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3672 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3673 !intel_crtc_has_pending_flip(crtc),
3674 60*HZ) == 0)) {
3675 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3676
3677 spin_lock_irq(&dev->event_lock);
3678 if (intel_crtc->unpin_work) {
3679 WARN_ONCE(1, "Removing stuck page flip\n");
3680 page_flip_completed(intel_crtc);
3681 }
3682 spin_unlock_irq(&dev->event_lock);
3683 }
3684
3685 if (crtc->primary->fb) {
3686 mutex_lock(&dev->struct_mutex);
3687 intel_finish_fb(crtc->primary->fb);
3688 mutex_unlock(&dev->struct_mutex);
3689 }
3690 }
3691
3692 /* Program iCLKIP clock to the desired frequency */
3693 static void lpt_program_iclkip(struct drm_crtc *crtc)
3694 {
3695 struct drm_device *dev = crtc->dev;
3696 struct drm_i915_private *dev_priv = dev->dev_private;
3697 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3698 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3699 u32 temp;
3700
3701 mutex_lock(&dev_priv->dpio_lock);
3702
3703 /* It is necessary to ungate the pixclk gate prior to programming
3704 * the divisors, and gate it back when it is done.
3705 */
3706 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3707
3708 /* Disable SSCCTL */
3709 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3710 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3711 SBI_SSCCTL_DISABLE,
3712 SBI_ICLK);
3713
3714 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3715 if (clock == 20000) {
3716 auxdiv = 1;
3717 divsel = 0x41;
3718 phaseinc = 0x20;
3719 } else {
3720 /* The iCLK virtual clock root frequency is in MHz,
3721 * but the adjusted_mode->crtc_clock in in KHz. To get the
3722 * divisors, it is necessary to divide one by another, so we
3723 * convert the virtual clock precision to KHz here for higher
3724 * precision.
3725 */
3726 u32 iclk_virtual_root_freq = 172800 * 1000;
3727 u32 iclk_pi_range = 64;
3728 u32 desired_divisor, msb_divisor_value, pi_value;
3729
3730 desired_divisor = (iclk_virtual_root_freq / clock);
3731 msb_divisor_value = desired_divisor / iclk_pi_range;
3732 pi_value = desired_divisor % iclk_pi_range;
3733
3734 auxdiv = 0;
3735 divsel = msb_divisor_value - 2;
3736 phaseinc = pi_value;
3737 }
3738
3739 /* This should not happen with any sane values */
3740 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3741 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3742 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3743 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3744
3745 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3746 clock,
3747 auxdiv,
3748 divsel,
3749 phasedir,
3750 phaseinc);
3751
3752 /* Program SSCDIVINTPHASE6 */
3753 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3754 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3755 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3756 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3757 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3758 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3759 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3760 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3761
3762 /* Program SSCAUXDIV */
3763 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3764 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3765 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3766 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3767
3768 /* Enable modulator and associated divider */
3769 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3770 temp &= ~SBI_SSCCTL_DISABLE;
3771 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3772
3773 /* Wait for initialization time */
3774 udelay(24);
3775
3776 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3777
3778 mutex_unlock(&dev_priv->dpio_lock);
3779 }
3780
3781 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3782 enum pipe pch_transcoder)
3783 {
3784 struct drm_device *dev = crtc->base.dev;
3785 struct drm_i915_private *dev_priv = dev->dev_private;
3786 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3787
3788 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3789 I915_READ(HTOTAL(cpu_transcoder)));
3790 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3791 I915_READ(HBLANK(cpu_transcoder)));
3792 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3793 I915_READ(HSYNC(cpu_transcoder)));
3794
3795 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3796 I915_READ(VTOTAL(cpu_transcoder)));
3797 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3798 I915_READ(VBLANK(cpu_transcoder)));
3799 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3800 I915_READ(VSYNC(cpu_transcoder)));
3801 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3802 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3803 }
3804
3805 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
3806 {
3807 struct drm_i915_private *dev_priv = dev->dev_private;
3808 uint32_t temp;
3809
3810 temp = I915_READ(SOUTH_CHICKEN1);
3811 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
3812 return;
3813
3814 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3815 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3816
3817 temp &= ~FDI_BC_BIFURCATION_SELECT;
3818 if (enable)
3819 temp |= FDI_BC_BIFURCATION_SELECT;
3820
3821 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
3822 I915_WRITE(SOUTH_CHICKEN1, temp);
3823 POSTING_READ(SOUTH_CHICKEN1);
3824 }
3825
3826 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3827 {
3828 struct drm_device *dev = intel_crtc->base.dev;
3829
3830 switch (intel_crtc->pipe) {
3831 case PIPE_A:
3832 break;
3833 case PIPE_B:
3834 if (intel_crtc->config->fdi_lanes > 2)
3835 cpt_set_fdi_bc_bifurcation(dev, false);
3836 else
3837 cpt_set_fdi_bc_bifurcation(dev, true);
3838
3839 break;
3840 case PIPE_C:
3841 cpt_set_fdi_bc_bifurcation(dev, true);
3842
3843 break;
3844 default:
3845 BUG();
3846 }
3847 }
3848
3849 /*
3850 * Enable PCH resources required for PCH ports:
3851 * - PCH PLLs
3852 * - FDI training & RX/TX
3853 * - update transcoder timings
3854 * - DP transcoding bits
3855 * - transcoder
3856 */
3857 static void ironlake_pch_enable(struct drm_crtc *crtc)
3858 {
3859 struct drm_device *dev = crtc->dev;
3860 struct drm_i915_private *dev_priv = dev->dev_private;
3861 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3862 int pipe = intel_crtc->pipe;
3863 u32 reg, temp;
3864
3865 assert_pch_transcoder_disabled(dev_priv, pipe);
3866
3867 if (IS_IVYBRIDGE(dev))
3868 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3869
3870 /* Write the TU size bits before fdi link training, so that error
3871 * detection works. */
3872 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3873 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3874
3875 /* For PCH output, training FDI link */
3876 dev_priv->display.fdi_link_train(crtc);
3877
3878 /* We need to program the right clock selection before writing the pixel
3879 * mutliplier into the DPLL. */
3880 if (HAS_PCH_CPT(dev)) {
3881 u32 sel;
3882
3883 temp = I915_READ(PCH_DPLL_SEL);
3884 temp |= TRANS_DPLL_ENABLE(pipe);
3885 sel = TRANS_DPLLB_SEL(pipe);
3886 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
3887 temp |= sel;
3888 else
3889 temp &= ~sel;
3890 I915_WRITE(PCH_DPLL_SEL, temp);
3891 }
3892
3893 /* XXX: pch pll's can be enabled any time before we enable the PCH
3894 * transcoder, and we actually should do this to not upset any PCH
3895 * transcoder that already use the clock when we share it.
3896 *
3897 * Note that enable_shared_dpll tries to do the right thing, but
3898 * get_shared_dpll unconditionally resets the pll - we need that to have
3899 * the right LVDS enable sequence. */
3900 intel_enable_shared_dpll(intel_crtc);
3901
3902 /* set transcoder timing, panel must allow it */
3903 assert_panel_unlocked(dev_priv, pipe);
3904 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3905
3906 intel_fdi_normal_train(crtc);
3907
3908 /* For PCH DP, enable TRANS_DP_CTL */
3909 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
3910 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3911 reg = TRANS_DP_CTL(pipe);
3912 temp = I915_READ(reg);
3913 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3914 TRANS_DP_SYNC_MASK |
3915 TRANS_DP_BPC_MASK);
3916 temp |= (TRANS_DP_OUTPUT_ENABLE |
3917 TRANS_DP_ENH_FRAMING);
3918 temp |= bpc << 9; /* same format but at 11:9 */
3919
3920 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3921 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3922 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3923 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3924
3925 switch (intel_trans_dp_port_sel(crtc)) {
3926 case PCH_DP_B:
3927 temp |= TRANS_DP_PORT_SEL_B;
3928 break;
3929 case PCH_DP_C:
3930 temp |= TRANS_DP_PORT_SEL_C;
3931 break;
3932 case PCH_DP_D:
3933 temp |= TRANS_DP_PORT_SEL_D;
3934 break;
3935 default:
3936 BUG();
3937 }
3938
3939 I915_WRITE(reg, temp);
3940 }
3941
3942 ironlake_enable_pch_transcoder(dev_priv, pipe);
3943 }
3944
3945 static void lpt_pch_enable(struct drm_crtc *crtc)
3946 {
3947 struct drm_device *dev = crtc->dev;
3948 struct drm_i915_private *dev_priv = dev->dev_private;
3949 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3950 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
3951
3952 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3953
3954 lpt_program_iclkip(crtc);
3955
3956 /* Set transcoder timing. */
3957 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3958
3959 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3960 }
3961
3962 void intel_put_shared_dpll(struct intel_crtc *crtc)
3963 {
3964 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3965
3966 if (pll == NULL)
3967 return;
3968
3969 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
3970 WARN(1, "bad %s crtc mask\n", pll->name);
3971 return;
3972 }
3973
3974 pll->config.crtc_mask &= ~(1 << crtc->pipe);
3975 if (pll->config.crtc_mask == 0) {
3976 WARN_ON(pll->on);
3977 WARN_ON(pll->active);
3978 }
3979
3980 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
3981 }
3982
3983 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
3984 struct intel_crtc_state *crtc_state)
3985 {
3986 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3987 struct intel_shared_dpll *pll;
3988 enum intel_dpll_id i;
3989
3990 if (HAS_PCH_IBX(dev_priv->dev)) {
3991 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3992 i = (enum intel_dpll_id) crtc->pipe;
3993 pll = &dev_priv->shared_dplls[i];
3994
3995 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3996 crtc->base.base.id, pll->name);
3997
3998 WARN_ON(pll->new_config->crtc_mask);
3999
4000 goto found;
4001 }
4002
4003 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4004 pll = &dev_priv->shared_dplls[i];
4005
4006 /* Only want to check enabled timings first */
4007 if (pll->new_config->crtc_mask == 0)
4008 continue;
4009
4010 if (memcmp(&crtc_state->dpll_hw_state,
4011 &pll->new_config->hw_state,
4012 sizeof(pll->new_config->hw_state)) == 0) {
4013 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4014 crtc->base.base.id, pll->name,
4015 pll->new_config->crtc_mask,
4016 pll->active);
4017 goto found;
4018 }
4019 }
4020
4021 /* Ok no matching timings, maybe there's a free one? */
4022 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4023 pll = &dev_priv->shared_dplls[i];
4024 if (pll->new_config->crtc_mask == 0) {
4025 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4026 crtc->base.base.id, pll->name);
4027 goto found;
4028 }
4029 }
4030
4031 return NULL;
4032
4033 found:
4034 if (pll->new_config->crtc_mask == 0)
4035 pll->new_config->hw_state = crtc_state->dpll_hw_state;
4036
4037 crtc_state->shared_dpll = i;
4038 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4039 pipe_name(crtc->pipe));
4040
4041 pll->new_config->crtc_mask |= 1 << crtc->pipe;
4042
4043 return pll;
4044 }
4045
4046 /**
4047 * intel_shared_dpll_start_config - start a new PLL staged config
4048 * @dev_priv: DRM device
4049 * @clear_pipes: mask of pipes that will have their PLLs freed
4050 *
4051 * Starts a new PLL staged config, copying the current config but
4052 * releasing the references of pipes specified in clear_pipes.
4053 */
4054 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4055 unsigned clear_pipes)
4056 {
4057 struct intel_shared_dpll *pll;
4058 enum intel_dpll_id i;
4059
4060 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4061 pll = &dev_priv->shared_dplls[i];
4062
4063 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4064 GFP_KERNEL);
4065 if (!pll->new_config)
4066 goto cleanup;
4067
4068 pll->new_config->crtc_mask &= ~clear_pipes;
4069 }
4070
4071 return 0;
4072
4073 cleanup:
4074 while (--i >= 0) {
4075 pll = &dev_priv->shared_dplls[i];
4076 kfree(pll->new_config);
4077 pll->new_config = NULL;
4078 }
4079
4080 return -ENOMEM;
4081 }
4082
4083 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4084 {
4085 struct intel_shared_dpll *pll;
4086 enum intel_dpll_id i;
4087
4088 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4089 pll = &dev_priv->shared_dplls[i];
4090
4091 WARN_ON(pll->new_config == &pll->config);
4092
4093 pll->config = *pll->new_config;
4094 kfree(pll->new_config);
4095 pll->new_config = NULL;
4096 }
4097 }
4098
4099 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4100 {
4101 struct intel_shared_dpll *pll;
4102 enum intel_dpll_id i;
4103
4104 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4105 pll = &dev_priv->shared_dplls[i];
4106
4107 WARN_ON(pll->new_config == &pll->config);
4108
4109 kfree(pll->new_config);
4110 pll->new_config = NULL;
4111 }
4112 }
4113
4114 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4115 {
4116 struct drm_i915_private *dev_priv = dev->dev_private;
4117 int dslreg = PIPEDSL(pipe);
4118 u32 temp;
4119
4120 temp = I915_READ(dslreg);
4121 udelay(500);
4122 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4123 if (wait_for(I915_READ(dslreg) != temp, 5))
4124 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4125 }
4126 }
4127
4128 static void skylake_pfit_enable(struct intel_crtc *crtc)
4129 {
4130 struct drm_device *dev = crtc->base.dev;
4131 struct drm_i915_private *dev_priv = dev->dev_private;
4132 int pipe = crtc->pipe;
4133
4134 if (crtc->config->pch_pfit.enabled) {
4135 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
4136 I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4137 I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4138 }
4139 }
4140
4141 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4142 {
4143 struct drm_device *dev = crtc->base.dev;
4144 struct drm_i915_private *dev_priv = dev->dev_private;
4145 int pipe = crtc->pipe;
4146
4147 if (crtc->config->pch_pfit.enabled) {
4148 /* Force use of hard-coded filter coefficients
4149 * as some pre-programmed values are broken,
4150 * e.g. x201.
4151 */
4152 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4153 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4154 PF_PIPE_SEL_IVB(pipe));
4155 else
4156 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4157 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4158 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4159 }
4160 }
4161
4162 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4163 {
4164 struct drm_device *dev = crtc->dev;
4165 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4166 struct drm_plane *plane;
4167 struct intel_plane *intel_plane;
4168
4169 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4170 intel_plane = to_intel_plane(plane);
4171 if (intel_plane->pipe == pipe)
4172 intel_plane_restore(&intel_plane->base);
4173 }
4174 }
4175
4176 /*
4177 * Disable a plane internally without actually modifying the plane's state.
4178 * This will allow us to easily restore the plane later by just reprogramming
4179 * its state.
4180 */
4181 static void disable_plane_internal(struct drm_plane *plane)
4182 {
4183 struct intel_plane *intel_plane = to_intel_plane(plane);
4184 struct drm_plane_state *state =
4185 plane->funcs->atomic_duplicate_state(plane);
4186 struct intel_plane_state *intel_state = to_intel_plane_state(state);
4187
4188 intel_state->visible = false;
4189 intel_plane->commit_plane(plane, intel_state);
4190
4191 intel_plane_destroy_state(plane, state);
4192 }
4193
4194 static void intel_disable_sprite_planes(struct drm_crtc *crtc)
4195 {
4196 struct drm_device *dev = crtc->dev;
4197 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4198 struct drm_plane *plane;
4199 struct intel_plane *intel_plane;
4200
4201 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4202 intel_plane = to_intel_plane(plane);
4203 if (plane->fb && intel_plane->pipe == pipe)
4204 disable_plane_internal(plane);
4205 }
4206 }
4207
4208 void hsw_enable_ips(struct intel_crtc *crtc)
4209 {
4210 struct drm_device *dev = crtc->base.dev;
4211 struct drm_i915_private *dev_priv = dev->dev_private;
4212
4213 if (!crtc->config->ips_enabled)
4214 return;
4215
4216 /* We can only enable IPS after we enable a plane and wait for a vblank */
4217 intel_wait_for_vblank(dev, crtc->pipe);
4218
4219 assert_plane_enabled(dev_priv, crtc->plane);
4220 if (IS_BROADWELL(dev)) {
4221 mutex_lock(&dev_priv->rps.hw_lock);
4222 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4223 mutex_unlock(&dev_priv->rps.hw_lock);
4224 /* Quoting Art Runyan: "its not safe to expect any particular
4225 * value in IPS_CTL bit 31 after enabling IPS through the
4226 * mailbox." Moreover, the mailbox may return a bogus state,
4227 * so we need to just enable it and continue on.
4228 */
4229 } else {
4230 I915_WRITE(IPS_CTL, IPS_ENABLE);
4231 /* The bit only becomes 1 in the next vblank, so this wait here
4232 * is essentially intel_wait_for_vblank. If we don't have this
4233 * and don't wait for vblanks until the end of crtc_enable, then
4234 * the HW state readout code will complain that the expected
4235 * IPS_CTL value is not the one we read. */
4236 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4237 DRM_ERROR("Timed out waiting for IPS enable\n");
4238 }
4239 }
4240
4241 void hsw_disable_ips(struct intel_crtc *crtc)
4242 {
4243 struct drm_device *dev = crtc->base.dev;
4244 struct drm_i915_private *dev_priv = dev->dev_private;
4245
4246 if (!crtc->config->ips_enabled)
4247 return;
4248
4249 assert_plane_enabled(dev_priv, crtc->plane);
4250 if (IS_BROADWELL(dev)) {
4251 mutex_lock(&dev_priv->rps.hw_lock);
4252 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4253 mutex_unlock(&dev_priv->rps.hw_lock);
4254 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4255 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4256 DRM_ERROR("Timed out waiting for IPS disable\n");
4257 } else {
4258 I915_WRITE(IPS_CTL, 0);
4259 POSTING_READ(IPS_CTL);
4260 }
4261
4262 /* We need to wait for a vblank before we can disable the plane. */
4263 intel_wait_for_vblank(dev, crtc->pipe);
4264 }
4265
4266 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4267 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4268 {
4269 struct drm_device *dev = crtc->dev;
4270 struct drm_i915_private *dev_priv = dev->dev_private;
4271 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4272 enum pipe pipe = intel_crtc->pipe;
4273 int palreg = PALETTE(pipe);
4274 int i;
4275 bool reenable_ips = false;
4276
4277 /* The clocks have to be on to load the palette. */
4278 if (!crtc->state->enable || !intel_crtc->active)
4279 return;
4280
4281 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4282 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4283 assert_dsi_pll_enabled(dev_priv);
4284 else
4285 assert_pll_enabled(dev_priv, pipe);
4286 }
4287
4288 /* use legacy palette for Ironlake */
4289 if (!HAS_GMCH_DISPLAY(dev))
4290 palreg = LGC_PALETTE(pipe);
4291
4292 /* Workaround : Do not read or write the pipe palette/gamma data while
4293 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4294 */
4295 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4296 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4297 GAMMA_MODE_MODE_SPLIT)) {
4298 hsw_disable_ips(intel_crtc);
4299 reenable_ips = true;
4300 }
4301
4302 for (i = 0; i < 256; i++) {
4303 I915_WRITE(palreg + 4 * i,
4304 (intel_crtc->lut_r[i] << 16) |
4305 (intel_crtc->lut_g[i] << 8) |
4306 intel_crtc->lut_b[i]);
4307 }
4308
4309 if (reenable_ips)
4310 hsw_enable_ips(intel_crtc);
4311 }
4312
4313 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4314 {
4315 if (!enable && intel_crtc->overlay) {
4316 struct drm_device *dev = intel_crtc->base.dev;
4317 struct drm_i915_private *dev_priv = dev->dev_private;
4318
4319 mutex_lock(&dev->struct_mutex);
4320 dev_priv->mm.interruptible = false;
4321 (void) intel_overlay_switch_off(intel_crtc->overlay);
4322 dev_priv->mm.interruptible = true;
4323 mutex_unlock(&dev->struct_mutex);
4324 }
4325
4326 /* Let userspace switch the overlay on again. In most cases userspace
4327 * has to recompute where to put it anyway.
4328 */
4329 }
4330
4331 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4332 {
4333 struct drm_device *dev = crtc->dev;
4334 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4335 int pipe = intel_crtc->pipe;
4336
4337 intel_enable_primary_hw_plane(crtc->primary, crtc);
4338 intel_enable_sprite_planes(crtc);
4339 intel_crtc_update_cursor(crtc, true);
4340 intel_crtc_dpms_overlay(intel_crtc, true);
4341
4342 hsw_enable_ips(intel_crtc);
4343
4344 mutex_lock(&dev->struct_mutex);
4345 intel_fbc_update(dev);
4346 mutex_unlock(&dev->struct_mutex);
4347
4348 /*
4349 * FIXME: Once we grow proper nuclear flip support out of this we need
4350 * to compute the mask of flip planes precisely. For the time being
4351 * consider this a flip from a NULL plane.
4352 */
4353 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4354 }
4355
4356 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4357 {
4358 struct drm_device *dev = crtc->dev;
4359 struct drm_i915_private *dev_priv = dev->dev_private;
4360 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4361 int pipe = intel_crtc->pipe;
4362
4363 intel_crtc_wait_for_pending_flips(crtc);
4364
4365 if (dev_priv->fbc.crtc == intel_crtc)
4366 intel_fbc_disable(dev);
4367
4368 hsw_disable_ips(intel_crtc);
4369
4370 intel_crtc_dpms_overlay(intel_crtc, false);
4371 intel_crtc_update_cursor(crtc, false);
4372 intel_disable_sprite_planes(crtc);
4373 intel_disable_primary_hw_plane(crtc->primary, crtc);
4374
4375 /*
4376 * FIXME: Once we grow proper nuclear flip support out of this we need
4377 * to compute the mask of flip planes precisely. For the time being
4378 * consider this a flip to a NULL plane.
4379 */
4380 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4381 }
4382
4383 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4384 {
4385 struct drm_device *dev = crtc->dev;
4386 struct drm_i915_private *dev_priv = dev->dev_private;
4387 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4388 struct intel_encoder *encoder;
4389 int pipe = intel_crtc->pipe;
4390
4391 WARN_ON(!crtc->state->enable);
4392
4393 if (intel_crtc->active)
4394 return;
4395
4396 if (intel_crtc->config->has_pch_encoder)
4397 intel_prepare_shared_dpll(intel_crtc);
4398
4399 if (intel_crtc->config->has_dp_encoder)
4400 intel_dp_set_m_n(intel_crtc, M1_N1);
4401
4402 intel_set_pipe_timings(intel_crtc);
4403
4404 if (intel_crtc->config->has_pch_encoder) {
4405 intel_cpu_transcoder_set_m_n(intel_crtc,
4406 &intel_crtc->config->fdi_m_n, NULL);
4407 }
4408
4409 ironlake_set_pipeconf(crtc);
4410
4411 intel_crtc->active = true;
4412
4413 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4414 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4415
4416 for_each_encoder_on_crtc(dev, crtc, encoder)
4417 if (encoder->pre_enable)
4418 encoder->pre_enable(encoder);
4419
4420 if (intel_crtc->config->has_pch_encoder) {
4421 /* Note: FDI PLL enabling _must_ be done before we enable the
4422 * cpu pipes, hence this is separate from all the other fdi/pch
4423 * enabling. */
4424 ironlake_fdi_pll_enable(intel_crtc);
4425 } else {
4426 assert_fdi_tx_disabled(dev_priv, pipe);
4427 assert_fdi_rx_disabled(dev_priv, pipe);
4428 }
4429
4430 ironlake_pfit_enable(intel_crtc);
4431
4432 /*
4433 * On ILK+ LUT must be loaded before the pipe is running but with
4434 * clocks enabled
4435 */
4436 intel_crtc_load_lut(crtc);
4437
4438 intel_update_watermarks(crtc);
4439 intel_enable_pipe(intel_crtc);
4440
4441 if (intel_crtc->config->has_pch_encoder)
4442 ironlake_pch_enable(crtc);
4443
4444 assert_vblank_disabled(crtc);
4445 drm_crtc_vblank_on(crtc);
4446
4447 for_each_encoder_on_crtc(dev, crtc, encoder)
4448 encoder->enable(encoder);
4449
4450 if (HAS_PCH_CPT(dev))
4451 cpt_verify_modeset(dev, intel_crtc->pipe);
4452
4453 intel_crtc_enable_planes(crtc);
4454 }
4455
4456 /* IPS only exists on ULT machines and is tied to pipe A. */
4457 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4458 {
4459 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4460 }
4461
4462 /*
4463 * This implements the workaround described in the "notes" section of the mode
4464 * set sequence documentation. When going from no pipes or single pipe to
4465 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4466 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4467 */
4468 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4469 {
4470 struct drm_device *dev = crtc->base.dev;
4471 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4472
4473 /* We want to get the other_active_crtc only if there's only 1 other
4474 * active crtc. */
4475 for_each_intel_crtc(dev, crtc_it) {
4476 if (!crtc_it->active || crtc_it == crtc)
4477 continue;
4478
4479 if (other_active_crtc)
4480 return;
4481
4482 other_active_crtc = crtc_it;
4483 }
4484 if (!other_active_crtc)
4485 return;
4486
4487 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4488 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4489 }
4490
4491 static void haswell_crtc_enable(struct drm_crtc *crtc)
4492 {
4493 struct drm_device *dev = crtc->dev;
4494 struct drm_i915_private *dev_priv = dev->dev_private;
4495 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4496 struct intel_encoder *encoder;
4497 int pipe = intel_crtc->pipe;
4498
4499 WARN_ON(!crtc->state->enable);
4500
4501 if (intel_crtc->active)
4502 return;
4503
4504 if (intel_crtc_to_shared_dpll(intel_crtc))
4505 intel_enable_shared_dpll(intel_crtc);
4506
4507 if (intel_crtc->config->has_dp_encoder)
4508 intel_dp_set_m_n(intel_crtc, M1_N1);
4509
4510 intel_set_pipe_timings(intel_crtc);
4511
4512 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4513 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4514 intel_crtc->config->pixel_multiplier - 1);
4515 }
4516
4517 if (intel_crtc->config->has_pch_encoder) {
4518 intel_cpu_transcoder_set_m_n(intel_crtc,
4519 &intel_crtc->config->fdi_m_n, NULL);
4520 }
4521
4522 haswell_set_pipeconf(crtc);
4523
4524 intel_set_pipe_csc(crtc);
4525
4526 intel_crtc->active = true;
4527
4528 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4529 for_each_encoder_on_crtc(dev, crtc, encoder)
4530 if (encoder->pre_enable)
4531 encoder->pre_enable(encoder);
4532
4533 if (intel_crtc->config->has_pch_encoder) {
4534 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4535 true);
4536 dev_priv->display.fdi_link_train(crtc);
4537 }
4538
4539 intel_ddi_enable_pipe_clock(intel_crtc);
4540
4541 if (IS_SKYLAKE(dev))
4542 skylake_pfit_enable(intel_crtc);
4543 else
4544 ironlake_pfit_enable(intel_crtc);
4545
4546 /*
4547 * On ILK+ LUT must be loaded before the pipe is running but with
4548 * clocks enabled
4549 */
4550 intel_crtc_load_lut(crtc);
4551
4552 intel_ddi_set_pipe_settings(crtc);
4553 intel_ddi_enable_transcoder_func(crtc);
4554
4555 intel_update_watermarks(crtc);
4556 intel_enable_pipe(intel_crtc);
4557
4558 if (intel_crtc->config->has_pch_encoder)
4559 lpt_pch_enable(crtc);
4560
4561 if (intel_crtc->config->dp_encoder_is_mst)
4562 intel_ddi_set_vc_payload_alloc(crtc, true);
4563
4564 assert_vblank_disabled(crtc);
4565 drm_crtc_vblank_on(crtc);
4566
4567 for_each_encoder_on_crtc(dev, crtc, encoder) {
4568 encoder->enable(encoder);
4569 intel_opregion_notify_encoder(encoder, true);
4570 }
4571
4572 /* If we change the relative order between pipe/planes enabling, we need
4573 * to change the workaround. */
4574 haswell_mode_set_planes_workaround(intel_crtc);
4575 intel_crtc_enable_planes(crtc);
4576 }
4577
4578 static void skylake_pfit_disable(struct intel_crtc *crtc)
4579 {
4580 struct drm_device *dev = crtc->base.dev;
4581 struct drm_i915_private *dev_priv = dev->dev_private;
4582 int pipe = crtc->pipe;
4583
4584 /* To avoid upsetting the power well on haswell only disable the pfit if
4585 * it's in use. The hw state code will make sure we get this right. */
4586 if (crtc->config->pch_pfit.enabled) {
4587 I915_WRITE(PS_CTL(pipe), 0);
4588 I915_WRITE(PS_WIN_POS(pipe), 0);
4589 I915_WRITE(PS_WIN_SZ(pipe), 0);
4590 }
4591 }
4592
4593 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4594 {
4595 struct drm_device *dev = crtc->base.dev;
4596 struct drm_i915_private *dev_priv = dev->dev_private;
4597 int pipe = crtc->pipe;
4598
4599 /* To avoid upsetting the power well on haswell only disable the pfit if
4600 * it's in use. The hw state code will make sure we get this right. */
4601 if (crtc->config->pch_pfit.enabled) {
4602 I915_WRITE(PF_CTL(pipe), 0);
4603 I915_WRITE(PF_WIN_POS(pipe), 0);
4604 I915_WRITE(PF_WIN_SZ(pipe), 0);
4605 }
4606 }
4607
4608 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4609 {
4610 struct drm_device *dev = crtc->dev;
4611 struct drm_i915_private *dev_priv = dev->dev_private;
4612 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4613 struct intel_encoder *encoder;
4614 int pipe = intel_crtc->pipe;
4615 u32 reg, temp;
4616
4617 if (!intel_crtc->active)
4618 return;
4619
4620 intel_crtc_disable_planes(crtc);
4621
4622 for_each_encoder_on_crtc(dev, crtc, encoder)
4623 encoder->disable(encoder);
4624
4625 drm_crtc_vblank_off(crtc);
4626 assert_vblank_disabled(crtc);
4627
4628 if (intel_crtc->config->has_pch_encoder)
4629 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4630
4631 intel_disable_pipe(intel_crtc);
4632
4633 ironlake_pfit_disable(intel_crtc);
4634
4635 for_each_encoder_on_crtc(dev, crtc, encoder)
4636 if (encoder->post_disable)
4637 encoder->post_disable(encoder);
4638
4639 if (intel_crtc->config->has_pch_encoder) {
4640 ironlake_fdi_disable(crtc);
4641
4642 ironlake_disable_pch_transcoder(dev_priv, pipe);
4643
4644 if (HAS_PCH_CPT(dev)) {
4645 /* disable TRANS_DP_CTL */
4646 reg = TRANS_DP_CTL(pipe);
4647 temp = I915_READ(reg);
4648 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4649 TRANS_DP_PORT_SEL_MASK);
4650 temp |= TRANS_DP_PORT_SEL_NONE;
4651 I915_WRITE(reg, temp);
4652
4653 /* disable DPLL_SEL */
4654 temp = I915_READ(PCH_DPLL_SEL);
4655 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4656 I915_WRITE(PCH_DPLL_SEL, temp);
4657 }
4658
4659 /* disable PCH DPLL */
4660 intel_disable_shared_dpll(intel_crtc);
4661
4662 ironlake_fdi_pll_disable(intel_crtc);
4663 }
4664
4665 intel_crtc->active = false;
4666 intel_update_watermarks(crtc);
4667
4668 mutex_lock(&dev->struct_mutex);
4669 intel_fbc_update(dev);
4670 mutex_unlock(&dev->struct_mutex);
4671 }
4672
4673 static void haswell_crtc_disable(struct drm_crtc *crtc)
4674 {
4675 struct drm_device *dev = crtc->dev;
4676 struct drm_i915_private *dev_priv = dev->dev_private;
4677 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4678 struct intel_encoder *encoder;
4679 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4680
4681 if (!intel_crtc->active)
4682 return;
4683
4684 intel_crtc_disable_planes(crtc);
4685
4686 for_each_encoder_on_crtc(dev, crtc, encoder) {
4687 intel_opregion_notify_encoder(encoder, false);
4688 encoder->disable(encoder);
4689 }
4690
4691 drm_crtc_vblank_off(crtc);
4692 assert_vblank_disabled(crtc);
4693
4694 if (intel_crtc->config->has_pch_encoder)
4695 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4696 false);
4697 intel_disable_pipe(intel_crtc);
4698
4699 if (intel_crtc->config->dp_encoder_is_mst)
4700 intel_ddi_set_vc_payload_alloc(crtc, false);
4701
4702 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4703
4704 if (IS_SKYLAKE(dev))
4705 skylake_pfit_disable(intel_crtc);
4706 else
4707 ironlake_pfit_disable(intel_crtc);
4708
4709 intel_ddi_disable_pipe_clock(intel_crtc);
4710
4711 if (intel_crtc->config->has_pch_encoder) {
4712 lpt_disable_pch_transcoder(dev_priv);
4713 intel_ddi_fdi_disable(crtc);
4714 }
4715
4716 for_each_encoder_on_crtc(dev, crtc, encoder)
4717 if (encoder->post_disable)
4718 encoder->post_disable(encoder);
4719
4720 intel_crtc->active = false;
4721 intel_update_watermarks(crtc);
4722
4723 mutex_lock(&dev->struct_mutex);
4724 intel_fbc_update(dev);
4725 mutex_unlock(&dev->struct_mutex);
4726
4727 if (intel_crtc_to_shared_dpll(intel_crtc))
4728 intel_disable_shared_dpll(intel_crtc);
4729 }
4730
4731 static void ironlake_crtc_off(struct drm_crtc *crtc)
4732 {
4733 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4734 intel_put_shared_dpll(intel_crtc);
4735 }
4736
4737
4738 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4739 {
4740 struct drm_device *dev = crtc->base.dev;
4741 struct drm_i915_private *dev_priv = dev->dev_private;
4742 struct intel_crtc_state *pipe_config = crtc->config;
4743
4744 if (!pipe_config->gmch_pfit.control)
4745 return;
4746
4747 /*
4748 * The panel fitter should only be adjusted whilst the pipe is disabled,
4749 * according to register description and PRM.
4750 */
4751 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4752 assert_pipe_disabled(dev_priv, crtc->pipe);
4753
4754 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4755 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4756
4757 /* Border color in case we don't scale up to the full screen. Black by
4758 * default, change to something else for debugging. */
4759 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4760 }
4761
4762 static enum intel_display_power_domain port_to_power_domain(enum port port)
4763 {
4764 switch (port) {
4765 case PORT_A:
4766 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4767 case PORT_B:
4768 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4769 case PORT_C:
4770 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4771 case PORT_D:
4772 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4773 default:
4774 WARN_ON_ONCE(1);
4775 return POWER_DOMAIN_PORT_OTHER;
4776 }
4777 }
4778
4779 #define for_each_power_domain(domain, mask) \
4780 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4781 if ((1 << (domain)) & (mask))
4782
4783 enum intel_display_power_domain
4784 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4785 {
4786 struct drm_device *dev = intel_encoder->base.dev;
4787 struct intel_digital_port *intel_dig_port;
4788
4789 switch (intel_encoder->type) {
4790 case INTEL_OUTPUT_UNKNOWN:
4791 /* Only DDI platforms should ever use this output type */
4792 WARN_ON_ONCE(!HAS_DDI(dev));
4793 case INTEL_OUTPUT_DISPLAYPORT:
4794 case INTEL_OUTPUT_HDMI:
4795 case INTEL_OUTPUT_EDP:
4796 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4797 return port_to_power_domain(intel_dig_port->port);
4798 case INTEL_OUTPUT_DP_MST:
4799 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4800 return port_to_power_domain(intel_dig_port->port);
4801 case INTEL_OUTPUT_ANALOG:
4802 return POWER_DOMAIN_PORT_CRT;
4803 case INTEL_OUTPUT_DSI:
4804 return POWER_DOMAIN_PORT_DSI;
4805 default:
4806 return POWER_DOMAIN_PORT_OTHER;
4807 }
4808 }
4809
4810 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4811 {
4812 struct drm_device *dev = crtc->dev;
4813 struct intel_encoder *intel_encoder;
4814 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4815 enum pipe pipe = intel_crtc->pipe;
4816 unsigned long mask;
4817 enum transcoder transcoder;
4818
4819 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4820
4821 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4822 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4823 if (intel_crtc->config->pch_pfit.enabled ||
4824 intel_crtc->config->pch_pfit.force_thru)
4825 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4826
4827 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4828 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4829
4830 return mask;
4831 }
4832
4833 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4834 {
4835 struct drm_i915_private *dev_priv = dev->dev_private;
4836 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4837 struct intel_crtc *crtc;
4838
4839 /*
4840 * First get all needed power domains, then put all unneeded, to avoid
4841 * any unnecessary toggling of the power wells.
4842 */
4843 for_each_intel_crtc(dev, crtc) {
4844 enum intel_display_power_domain domain;
4845
4846 if (!crtc->base.state->enable)
4847 continue;
4848
4849 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4850
4851 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4852 intel_display_power_get(dev_priv, domain);
4853 }
4854
4855 if (dev_priv->display.modeset_global_resources)
4856 dev_priv->display.modeset_global_resources(dev);
4857
4858 for_each_intel_crtc(dev, crtc) {
4859 enum intel_display_power_domain domain;
4860
4861 for_each_power_domain(domain, crtc->enabled_power_domains)
4862 intel_display_power_put(dev_priv, domain);
4863
4864 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4865 }
4866
4867 intel_display_set_init_power(dev_priv, false);
4868 }
4869
4870 /* returns HPLL frequency in kHz */
4871 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4872 {
4873 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4874
4875 /* Obtain SKU information */
4876 mutex_lock(&dev_priv->dpio_lock);
4877 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4878 CCK_FUSE_HPLL_FREQ_MASK;
4879 mutex_unlock(&dev_priv->dpio_lock);
4880
4881 return vco_freq[hpll_freq] * 1000;
4882 }
4883
4884 static void vlv_update_cdclk(struct drm_device *dev)
4885 {
4886 struct drm_i915_private *dev_priv = dev->dev_private;
4887
4888 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4889 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4890 dev_priv->vlv_cdclk_freq);
4891
4892 /*
4893 * Program the gmbus_freq based on the cdclk frequency.
4894 * BSpec erroneously claims we should aim for 4MHz, but
4895 * in fact 1MHz is the correct frequency.
4896 */
4897 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
4898 }
4899
4900 /* Adjust CDclk dividers to allow high res or save power if possible */
4901 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4902 {
4903 struct drm_i915_private *dev_priv = dev->dev_private;
4904 u32 val, cmd;
4905
4906 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4907
4908 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4909 cmd = 2;
4910 else if (cdclk == 266667)
4911 cmd = 1;
4912 else
4913 cmd = 0;
4914
4915 mutex_lock(&dev_priv->rps.hw_lock);
4916 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4917 val &= ~DSPFREQGUAR_MASK;
4918 val |= (cmd << DSPFREQGUAR_SHIFT);
4919 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4920 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4921 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4922 50)) {
4923 DRM_ERROR("timed out waiting for CDclk change\n");
4924 }
4925 mutex_unlock(&dev_priv->rps.hw_lock);
4926
4927 if (cdclk == 400000) {
4928 u32 divider;
4929
4930 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
4931
4932 mutex_lock(&dev_priv->dpio_lock);
4933 /* adjust cdclk divider */
4934 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4935 val &= ~DISPLAY_FREQUENCY_VALUES;
4936 val |= divider;
4937 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4938
4939 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4940 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4941 50))
4942 DRM_ERROR("timed out waiting for CDclk change\n");
4943 mutex_unlock(&dev_priv->dpio_lock);
4944 }
4945
4946 mutex_lock(&dev_priv->dpio_lock);
4947 /* adjust self-refresh exit latency value */
4948 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4949 val &= ~0x7f;
4950
4951 /*
4952 * For high bandwidth configs, we set a higher latency in the bunit
4953 * so that the core display fetch happens in time to avoid underruns.
4954 */
4955 if (cdclk == 400000)
4956 val |= 4500 / 250; /* 4.5 usec */
4957 else
4958 val |= 3000 / 250; /* 3.0 usec */
4959 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4960 mutex_unlock(&dev_priv->dpio_lock);
4961
4962 vlv_update_cdclk(dev);
4963 }
4964
4965 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4966 {
4967 struct drm_i915_private *dev_priv = dev->dev_private;
4968 u32 val, cmd;
4969
4970 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4971
4972 switch (cdclk) {
4973 case 333333:
4974 case 320000:
4975 case 266667:
4976 case 200000:
4977 break;
4978 default:
4979 MISSING_CASE(cdclk);
4980 return;
4981 }
4982
4983 /*
4984 * Specs are full of misinformation, but testing on actual
4985 * hardware has shown that we just need to write the desired
4986 * CCK divider into the Punit register.
4987 */
4988 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
4989
4990 mutex_lock(&dev_priv->rps.hw_lock);
4991 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4992 val &= ~DSPFREQGUAR_MASK_CHV;
4993 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4994 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4995 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4996 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4997 50)) {
4998 DRM_ERROR("timed out waiting for CDclk change\n");
4999 }
5000 mutex_unlock(&dev_priv->rps.hw_lock);
5001
5002 vlv_update_cdclk(dev);
5003 }
5004
5005 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5006 int max_pixclk)
5007 {
5008 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5009 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5010
5011 /*
5012 * Really only a few cases to deal with, as only 4 CDclks are supported:
5013 * 200MHz
5014 * 267MHz
5015 * 320/333MHz (depends on HPLL freq)
5016 * 400MHz (VLV only)
5017 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5018 * of the lower bin and adjust if needed.
5019 *
5020 * We seem to get an unstable or solid color picture at 200MHz.
5021 * Not sure what's wrong. For now use 200MHz only when all pipes
5022 * are off.
5023 */
5024 if (!IS_CHERRYVIEW(dev_priv) &&
5025 max_pixclk > freq_320*limit/100)
5026 return 400000;
5027 else if (max_pixclk > 266667*limit/100)
5028 return freq_320;
5029 else if (max_pixclk > 0)
5030 return 266667;
5031 else
5032 return 200000;
5033 }
5034
5035 /* compute the max pixel clock for new configuration */
5036 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
5037 {
5038 struct drm_device *dev = dev_priv->dev;
5039 struct intel_crtc *intel_crtc;
5040 int max_pixclk = 0;
5041
5042 for_each_intel_crtc(dev, intel_crtc) {
5043 if (intel_crtc->new_enabled)
5044 max_pixclk = max(max_pixclk,
5045 intel_crtc->new_config->base.adjusted_mode.crtc_clock);
5046 }
5047
5048 return max_pixclk;
5049 }
5050
5051 static void valleyview_modeset_global_pipes(struct drm_device *dev,
5052 unsigned *prepare_pipes)
5053 {
5054 struct drm_i915_private *dev_priv = dev->dev_private;
5055 struct intel_crtc *intel_crtc;
5056 int max_pixclk = intel_mode_max_pixclk(dev_priv);
5057
5058 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
5059 dev_priv->vlv_cdclk_freq)
5060 return;
5061
5062 /* disable/enable all currently active pipes while we change cdclk */
5063 for_each_intel_crtc(dev, intel_crtc)
5064 if (intel_crtc->base.state->enable)
5065 *prepare_pipes |= (1 << intel_crtc->pipe);
5066 }
5067
5068 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5069 {
5070 unsigned int credits, default_credits;
5071
5072 if (IS_CHERRYVIEW(dev_priv))
5073 default_credits = PFI_CREDIT(12);
5074 else
5075 default_credits = PFI_CREDIT(8);
5076
5077 if (DIV_ROUND_CLOSEST(dev_priv->vlv_cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5078 /* CHV suggested value is 31 or 63 */
5079 if (IS_CHERRYVIEW(dev_priv))
5080 credits = PFI_CREDIT_31;
5081 else
5082 credits = PFI_CREDIT(15);
5083 } else {
5084 credits = default_credits;
5085 }
5086
5087 /*
5088 * WA - write default credits before re-programming
5089 * FIXME: should we also set the resend bit here?
5090 */
5091 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5092 default_credits);
5093
5094 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5095 credits | PFI_CREDIT_RESEND);
5096
5097 /*
5098 * FIXME is this guaranteed to clear
5099 * immediately or should we poll for it?
5100 */
5101 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5102 }
5103
5104 static void valleyview_modeset_global_resources(struct drm_device *dev)
5105 {
5106 struct drm_i915_private *dev_priv = dev->dev_private;
5107 int max_pixclk = intel_mode_max_pixclk(dev_priv);
5108 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5109
5110 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
5111 /*
5112 * FIXME: We can end up here with all power domains off, yet
5113 * with a CDCLK frequency other than the minimum. To account
5114 * for this take the PIPE-A power domain, which covers the HW
5115 * blocks needed for the following programming. This can be
5116 * removed once it's guaranteed that we get here either with
5117 * the minimum CDCLK set, or the required power domains
5118 * enabled.
5119 */
5120 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5121
5122 if (IS_CHERRYVIEW(dev))
5123 cherryview_set_cdclk(dev, req_cdclk);
5124 else
5125 valleyview_set_cdclk(dev, req_cdclk);
5126
5127 vlv_program_pfi_credits(dev_priv);
5128
5129 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5130 }
5131 }
5132
5133 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5134 {
5135 struct drm_device *dev = crtc->dev;
5136 struct drm_i915_private *dev_priv = to_i915(dev);
5137 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5138 struct intel_encoder *encoder;
5139 int pipe = intel_crtc->pipe;
5140 bool is_dsi;
5141
5142 WARN_ON(!crtc->state->enable);
5143
5144 if (intel_crtc->active)
5145 return;
5146
5147 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5148
5149 if (!is_dsi) {
5150 if (IS_CHERRYVIEW(dev))
5151 chv_prepare_pll(intel_crtc, intel_crtc->config);
5152 else
5153 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5154 }
5155
5156 if (intel_crtc->config->has_dp_encoder)
5157 intel_dp_set_m_n(intel_crtc, M1_N1);
5158
5159 intel_set_pipe_timings(intel_crtc);
5160
5161 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5162 struct drm_i915_private *dev_priv = dev->dev_private;
5163
5164 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5165 I915_WRITE(CHV_CANVAS(pipe), 0);
5166 }
5167
5168 i9xx_set_pipeconf(intel_crtc);
5169
5170 intel_crtc->active = true;
5171
5172 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5173
5174 for_each_encoder_on_crtc(dev, crtc, encoder)
5175 if (encoder->pre_pll_enable)
5176 encoder->pre_pll_enable(encoder);
5177
5178 if (!is_dsi) {
5179 if (IS_CHERRYVIEW(dev))
5180 chv_enable_pll(intel_crtc, intel_crtc->config);
5181 else
5182 vlv_enable_pll(intel_crtc, intel_crtc->config);
5183 }
5184
5185 for_each_encoder_on_crtc(dev, crtc, encoder)
5186 if (encoder->pre_enable)
5187 encoder->pre_enable(encoder);
5188
5189 i9xx_pfit_enable(intel_crtc);
5190
5191 intel_crtc_load_lut(crtc);
5192
5193 intel_update_watermarks(crtc);
5194 intel_enable_pipe(intel_crtc);
5195
5196 assert_vblank_disabled(crtc);
5197 drm_crtc_vblank_on(crtc);
5198
5199 for_each_encoder_on_crtc(dev, crtc, encoder)
5200 encoder->enable(encoder);
5201
5202 intel_crtc_enable_planes(crtc);
5203
5204 /* Underruns don't raise interrupts, so check manually. */
5205 i9xx_check_fifo_underruns(dev_priv);
5206 }
5207
5208 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5209 {
5210 struct drm_device *dev = crtc->base.dev;
5211 struct drm_i915_private *dev_priv = dev->dev_private;
5212
5213 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5214 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5215 }
5216
5217 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5218 {
5219 struct drm_device *dev = crtc->dev;
5220 struct drm_i915_private *dev_priv = to_i915(dev);
5221 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5222 struct intel_encoder *encoder;
5223 int pipe = intel_crtc->pipe;
5224
5225 WARN_ON(!crtc->state->enable);
5226
5227 if (intel_crtc->active)
5228 return;
5229
5230 i9xx_set_pll_dividers(intel_crtc);
5231
5232 if (intel_crtc->config->has_dp_encoder)
5233 intel_dp_set_m_n(intel_crtc, M1_N1);
5234
5235 intel_set_pipe_timings(intel_crtc);
5236
5237 i9xx_set_pipeconf(intel_crtc);
5238
5239 intel_crtc->active = true;
5240
5241 if (!IS_GEN2(dev))
5242 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5243
5244 for_each_encoder_on_crtc(dev, crtc, encoder)
5245 if (encoder->pre_enable)
5246 encoder->pre_enable(encoder);
5247
5248 i9xx_enable_pll(intel_crtc);
5249
5250 i9xx_pfit_enable(intel_crtc);
5251
5252 intel_crtc_load_lut(crtc);
5253
5254 intel_update_watermarks(crtc);
5255 intel_enable_pipe(intel_crtc);
5256
5257 assert_vblank_disabled(crtc);
5258 drm_crtc_vblank_on(crtc);
5259
5260 for_each_encoder_on_crtc(dev, crtc, encoder)
5261 encoder->enable(encoder);
5262
5263 intel_crtc_enable_planes(crtc);
5264
5265 /*
5266 * Gen2 reports pipe underruns whenever all planes are disabled.
5267 * So don't enable underrun reporting before at least some planes
5268 * are enabled.
5269 * FIXME: Need to fix the logic to work when we turn off all planes
5270 * but leave the pipe running.
5271 */
5272 if (IS_GEN2(dev))
5273 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5274
5275 /* Underruns don't raise interrupts, so check manually. */
5276 i9xx_check_fifo_underruns(dev_priv);
5277 }
5278
5279 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5280 {
5281 struct drm_device *dev = crtc->base.dev;
5282 struct drm_i915_private *dev_priv = dev->dev_private;
5283
5284 if (!crtc->config->gmch_pfit.control)
5285 return;
5286
5287 assert_pipe_disabled(dev_priv, crtc->pipe);
5288
5289 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5290 I915_READ(PFIT_CONTROL));
5291 I915_WRITE(PFIT_CONTROL, 0);
5292 }
5293
5294 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5295 {
5296 struct drm_device *dev = crtc->dev;
5297 struct drm_i915_private *dev_priv = dev->dev_private;
5298 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5299 struct intel_encoder *encoder;
5300 int pipe = intel_crtc->pipe;
5301
5302 if (!intel_crtc->active)
5303 return;
5304
5305 /*
5306 * Gen2 reports pipe underruns whenever all planes are disabled.
5307 * So diasble underrun reporting before all the planes get disabled.
5308 * FIXME: Need to fix the logic to work when we turn off all planes
5309 * but leave the pipe running.
5310 */
5311 if (IS_GEN2(dev))
5312 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5313
5314 /*
5315 * Vblank time updates from the shadow to live plane control register
5316 * are blocked if the memory self-refresh mode is active at that
5317 * moment. So to make sure the plane gets truly disabled, disable
5318 * first the self-refresh mode. The self-refresh enable bit in turn
5319 * will be checked/applied by the HW only at the next frame start
5320 * event which is after the vblank start event, so we need to have a
5321 * wait-for-vblank between disabling the plane and the pipe.
5322 */
5323 intel_set_memory_cxsr(dev_priv, false);
5324 intel_crtc_disable_planes(crtc);
5325
5326 /*
5327 * On gen2 planes are double buffered but the pipe isn't, so we must
5328 * wait for planes to fully turn off before disabling the pipe.
5329 * We also need to wait on all gmch platforms because of the
5330 * self-refresh mode constraint explained above.
5331 */
5332 intel_wait_for_vblank(dev, pipe);
5333
5334 for_each_encoder_on_crtc(dev, crtc, encoder)
5335 encoder->disable(encoder);
5336
5337 drm_crtc_vblank_off(crtc);
5338 assert_vblank_disabled(crtc);
5339
5340 intel_disable_pipe(intel_crtc);
5341
5342 i9xx_pfit_disable(intel_crtc);
5343
5344 for_each_encoder_on_crtc(dev, crtc, encoder)
5345 if (encoder->post_disable)
5346 encoder->post_disable(encoder);
5347
5348 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5349 if (IS_CHERRYVIEW(dev))
5350 chv_disable_pll(dev_priv, pipe);
5351 else if (IS_VALLEYVIEW(dev))
5352 vlv_disable_pll(dev_priv, pipe);
5353 else
5354 i9xx_disable_pll(intel_crtc);
5355 }
5356
5357 if (!IS_GEN2(dev))
5358 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5359
5360 intel_crtc->active = false;
5361 intel_update_watermarks(crtc);
5362
5363 mutex_lock(&dev->struct_mutex);
5364 intel_fbc_update(dev);
5365 mutex_unlock(&dev->struct_mutex);
5366 }
5367
5368 static void i9xx_crtc_off(struct drm_crtc *crtc)
5369 {
5370 }
5371
5372 /* Master function to enable/disable CRTC and corresponding power wells */
5373 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5374 {
5375 struct drm_device *dev = crtc->dev;
5376 struct drm_i915_private *dev_priv = dev->dev_private;
5377 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5378 enum intel_display_power_domain domain;
5379 unsigned long domains;
5380
5381 if (enable) {
5382 if (!intel_crtc->active) {
5383 domains = get_crtc_power_domains(crtc);
5384 for_each_power_domain(domain, domains)
5385 intel_display_power_get(dev_priv, domain);
5386 intel_crtc->enabled_power_domains = domains;
5387
5388 dev_priv->display.crtc_enable(crtc);
5389 }
5390 } else {
5391 if (intel_crtc->active) {
5392 dev_priv->display.crtc_disable(crtc);
5393
5394 domains = intel_crtc->enabled_power_domains;
5395 for_each_power_domain(domain, domains)
5396 intel_display_power_put(dev_priv, domain);
5397 intel_crtc->enabled_power_domains = 0;
5398 }
5399 }
5400 }
5401
5402 /**
5403 * Sets the power management mode of the pipe and plane.
5404 */
5405 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5406 {
5407 struct drm_device *dev = crtc->dev;
5408 struct intel_encoder *intel_encoder;
5409 bool enable = false;
5410
5411 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5412 enable |= intel_encoder->connectors_active;
5413
5414 intel_crtc_control(crtc, enable);
5415 }
5416
5417 static void intel_crtc_disable(struct drm_crtc *crtc)
5418 {
5419 struct drm_device *dev = crtc->dev;
5420 struct drm_connector *connector;
5421 struct drm_i915_private *dev_priv = dev->dev_private;
5422
5423 /* crtc should still be enabled when we disable it. */
5424 WARN_ON(!crtc->state->enable);
5425
5426 dev_priv->display.crtc_disable(crtc);
5427 dev_priv->display.off(crtc);
5428
5429 crtc->primary->funcs->disable_plane(crtc->primary);
5430
5431 /* Update computed state. */
5432 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5433 if (!connector->encoder || !connector->encoder->crtc)
5434 continue;
5435
5436 if (connector->encoder->crtc != crtc)
5437 continue;
5438
5439 connector->dpms = DRM_MODE_DPMS_OFF;
5440 to_intel_encoder(connector->encoder)->connectors_active = false;
5441 }
5442 }
5443
5444 void intel_encoder_destroy(struct drm_encoder *encoder)
5445 {
5446 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5447
5448 drm_encoder_cleanup(encoder);
5449 kfree(intel_encoder);
5450 }
5451
5452 /* Simple dpms helper for encoders with just one connector, no cloning and only
5453 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5454 * state of the entire output pipe. */
5455 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5456 {
5457 if (mode == DRM_MODE_DPMS_ON) {
5458 encoder->connectors_active = true;
5459
5460 intel_crtc_update_dpms(encoder->base.crtc);
5461 } else {
5462 encoder->connectors_active = false;
5463
5464 intel_crtc_update_dpms(encoder->base.crtc);
5465 }
5466 }
5467
5468 /* Cross check the actual hw state with our own modeset state tracking (and it's
5469 * internal consistency). */
5470 static void intel_connector_check_state(struct intel_connector *connector)
5471 {
5472 if (connector->get_hw_state(connector)) {
5473 struct intel_encoder *encoder = connector->encoder;
5474 struct drm_crtc *crtc;
5475 bool encoder_enabled;
5476 enum pipe pipe;
5477
5478 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5479 connector->base.base.id,
5480 connector->base.name);
5481
5482 /* there is no real hw state for MST connectors */
5483 if (connector->mst_port)
5484 return;
5485
5486 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5487 "wrong connector dpms state\n");
5488 I915_STATE_WARN(connector->base.encoder != &encoder->base,
5489 "active connector not linked to encoder\n");
5490
5491 if (encoder) {
5492 I915_STATE_WARN(!encoder->connectors_active,
5493 "encoder->connectors_active not set\n");
5494
5495 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5496 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
5497 if (I915_STATE_WARN_ON(!encoder->base.crtc))
5498 return;
5499
5500 crtc = encoder->base.crtc;
5501
5502 I915_STATE_WARN(!crtc->state->enable,
5503 "crtc not enabled\n");
5504 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5505 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
5506 "encoder active on the wrong pipe\n");
5507 }
5508 }
5509 }
5510
5511 /* Even simpler default implementation, if there's really no special case to
5512 * consider. */
5513 void intel_connector_dpms(struct drm_connector *connector, int mode)
5514 {
5515 /* All the simple cases only support two dpms states. */
5516 if (mode != DRM_MODE_DPMS_ON)
5517 mode = DRM_MODE_DPMS_OFF;
5518
5519 if (mode == connector->dpms)
5520 return;
5521
5522 connector->dpms = mode;
5523
5524 /* Only need to change hw state when actually enabled */
5525 if (connector->encoder)
5526 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5527
5528 intel_modeset_check_state(connector->dev);
5529 }
5530
5531 /* Simple connector->get_hw_state implementation for encoders that support only
5532 * one connector and no cloning and hence the encoder state determines the state
5533 * of the connector. */
5534 bool intel_connector_get_hw_state(struct intel_connector *connector)
5535 {
5536 enum pipe pipe = 0;
5537 struct intel_encoder *encoder = connector->encoder;
5538
5539 return encoder->get_hw_state(encoder, &pipe);
5540 }
5541
5542 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5543 struct intel_crtc_state *pipe_config)
5544 {
5545 struct drm_i915_private *dev_priv = dev->dev_private;
5546 struct intel_crtc *pipe_B_crtc =
5547 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5548
5549 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5550 pipe_name(pipe), pipe_config->fdi_lanes);
5551 if (pipe_config->fdi_lanes > 4) {
5552 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5553 pipe_name(pipe), pipe_config->fdi_lanes);
5554 return false;
5555 }
5556
5557 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5558 if (pipe_config->fdi_lanes > 2) {
5559 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5560 pipe_config->fdi_lanes);
5561 return false;
5562 } else {
5563 return true;
5564 }
5565 }
5566
5567 if (INTEL_INFO(dev)->num_pipes == 2)
5568 return true;
5569
5570 /* Ivybridge 3 pipe is really complicated */
5571 switch (pipe) {
5572 case PIPE_A:
5573 return true;
5574 case PIPE_B:
5575 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5576 pipe_config->fdi_lanes > 2) {
5577 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5578 pipe_name(pipe), pipe_config->fdi_lanes);
5579 return false;
5580 }
5581 return true;
5582 case PIPE_C:
5583 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5584 pipe_B_crtc->config->fdi_lanes <= 2) {
5585 if (pipe_config->fdi_lanes > 2) {
5586 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5587 pipe_name(pipe), pipe_config->fdi_lanes);
5588 return false;
5589 }
5590 } else {
5591 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5592 return false;
5593 }
5594 return true;
5595 default:
5596 BUG();
5597 }
5598 }
5599
5600 #define RETRY 1
5601 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5602 struct intel_crtc_state *pipe_config)
5603 {
5604 struct drm_device *dev = intel_crtc->base.dev;
5605 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5606 int lane, link_bw, fdi_dotclock;
5607 bool setup_ok, needs_recompute = false;
5608
5609 retry:
5610 /* FDI is a binary signal running at ~2.7GHz, encoding
5611 * each output octet as 10 bits. The actual frequency
5612 * is stored as a divider into a 100MHz clock, and the
5613 * mode pixel clock is stored in units of 1KHz.
5614 * Hence the bw of each lane in terms of the mode signal
5615 * is:
5616 */
5617 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5618
5619 fdi_dotclock = adjusted_mode->crtc_clock;
5620
5621 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5622 pipe_config->pipe_bpp);
5623
5624 pipe_config->fdi_lanes = lane;
5625
5626 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5627 link_bw, &pipe_config->fdi_m_n);
5628
5629 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5630 intel_crtc->pipe, pipe_config);
5631 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5632 pipe_config->pipe_bpp -= 2*3;
5633 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5634 pipe_config->pipe_bpp);
5635 needs_recompute = true;
5636 pipe_config->bw_constrained = true;
5637
5638 goto retry;
5639 }
5640
5641 if (needs_recompute)
5642 return RETRY;
5643
5644 return setup_ok ? 0 : -EINVAL;
5645 }
5646
5647 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5648 struct intel_crtc_state *pipe_config)
5649 {
5650 pipe_config->ips_enabled = i915.enable_ips &&
5651 hsw_crtc_supports_ips(crtc) &&
5652 pipe_config->pipe_bpp <= 24;
5653 }
5654
5655 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5656 struct intel_crtc_state *pipe_config)
5657 {
5658 struct drm_device *dev = crtc->base.dev;
5659 struct drm_i915_private *dev_priv = dev->dev_private;
5660 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5661
5662 /* FIXME should check pixel clock limits on all platforms */
5663 if (INTEL_INFO(dev)->gen < 4) {
5664 int clock_limit =
5665 dev_priv->display.get_display_clock_speed(dev);
5666
5667 /*
5668 * Enable pixel doubling when the dot clock
5669 * is > 90% of the (display) core speed.
5670 *
5671 * GDG double wide on either pipe,
5672 * otherwise pipe A only.
5673 */
5674 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5675 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5676 clock_limit *= 2;
5677 pipe_config->double_wide = true;
5678 }
5679
5680 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5681 return -EINVAL;
5682 }
5683
5684 /*
5685 * Pipe horizontal size must be even in:
5686 * - DVO ganged mode
5687 * - LVDS dual channel mode
5688 * - Double wide pipe
5689 */
5690 if ((intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5691 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5692 pipe_config->pipe_src_w &= ~1;
5693
5694 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5695 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5696 */
5697 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5698 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5699 return -EINVAL;
5700
5701 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5702 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5703 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5704 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5705 * for lvds. */
5706 pipe_config->pipe_bpp = 8*3;
5707 }
5708
5709 if (HAS_IPS(dev))
5710 hsw_compute_ips_config(crtc, pipe_config);
5711
5712 if (pipe_config->has_pch_encoder)
5713 return ironlake_fdi_compute_config(crtc, pipe_config);
5714
5715 return 0;
5716 }
5717
5718 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5719 {
5720 struct drm_i915_private *dev_priv = dev->dev_private;
5721 u32 val;
5722 int divider;
5723
5724 if (dev_priv->hpll_freq == 0)
5725 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5726
5727 mutex_lock(&dev_priv->dpio_lock);
5728 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5729 mutex_unlock(&dev_priv->dpio_lock);
5730
5731 divider = val & DISPLAY_FREQUENCY_VALUES;
5732
5733 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5734 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5735 "cdclk change in progress\n");
5736
5737 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
5738 }
5739
5740 static int i945_get_display_clock_speed(struct drm_device *dev)
5741 {
5742 return 400000;
5743 }
5744
5745 static int i915_get_display_clock_speed(struct drm_device *dev)
5746 {
5747 return 333000;
5748 }
5749
5750 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5751 {
5752 return 200000;
5753 }
5754
5755 static int pnv_get_display_clock_speed(struct drm_device *dev)
5756 {
5757 u16 gcfgc = 0;
5758
5759 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5760
5761 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5762 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5763 return 267000;
5764 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5765 return 333000;
5766 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5767 return 444000;
5768 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5769 return 200000;
5770 default:
5771 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5772 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5773 return 133000;
5774 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5775 return 167000;
5776 }
5777 }
5778
5779 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5780 {
5781 u16 gcfgc = 0;
5782
5783 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5784
5785 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5786 return 133000;
5787 else {
5788 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5789 case GC_DISPLAY_CLOCK_333_MHZ:
5790 return 333000;
5791 default:
5792 case GC_DISPLAY_CLOCK_190_200_MHZ:
5793 return 190000;
5794 }
5795 }
5796 }
5797
5798 static int i865_get_display_clock_speed(struct drm_device *dev)
5799 {
5800 return 266000;
5801 }
5802
5803 static int i855_get_display_clock_speed(struct drm_device *dev)
5804 {
5805 u16 hpllcc = 0;
5806 /* Assume that the hardware is in the high speed state. This
5807 * should be the default.
5808 */
5809 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5810 case GC_CLOCK_133_200:
5811 case GC_CLOCK_100_200:
5812 return 200000;
5813 case GC_CLOCK_166_250:
5814 return 250000;
5815 case GC_CLOCK_100_133:
5816 return 133000;
5817 }
5818
5819 /* Shouldn't happen */
5820 return 0;
5821 }
5822
5823 static int i830_get_display_clock_speed(struct drm_device *dev)
5824 {
5825 return 133000;
5826 }
5827
5828 static void
5829 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5830 {
5831 while (*num > DATA_LINK_M_N_MASK ||
5832 *den > DATA_LINK_M_N_MASK) {
5833 *num >>= 1;
5834 *den >>= 1;
5835 }
5836 }
5837
5838 static void compute_m_n(unsigned int m, unsigned int n,
5839 uint32_t *ret_m, uint32_t *ret_n)
5840 {
5841 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5842 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5843 intel_reduce_m_n_ratio(ret_m, ret_n);
5844 }
5845
5846 void
5847 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5848 int pixel_clock, int link_clock,
5849 struct intel_link_m_n *m_n)
5850 {
5851 m_n->tu = 64;
5852
5853 compute_m_n(bits_per_pixel * pixel_clock,
5854 link_clock * nlanes * 8,
5855 &m_n->gmch_m, &m_n->gmch_n);
5856
5857 compute_m_n(pixel_clock, link_clock,
5858 &m_n->link_m, &m_n->link_n);
5859 }
5860
5861 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5862 {
5863 if (i915.panel_use_ssc >= 0)
5864 return i915.panel_use_ssc != 0;
5865 return dev_priv->vbt.lvds_use_ssc
5866 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5867 }
5868
5869 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5870 {
5871 struct drm_device *dev = crtc->base.dev;
5872 struct drm_i915_private *dev_priv = dev->dev_private;
5873 int refclk;
5874
5875 if (IS_VALLEYVIEW(dev)) {
5876 refclk = 100000;
5877 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5878 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5879 refclk = dev_priv->vbt.lvds_ssc_freq;
5880 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5881 } else if (!IS_GEN2(dev)) {
5882 refclk = 96000;
5883 } else {
5884 refclk = 48000;
5885 }
5886
5887 return refclk;
5888 }
5889
5890 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5891 {
5892 return (1 << dpll->n) << 16 | dpll->m2;
5893 }
5894
5895 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5896 {
5897 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5898 }
5899
5900 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5901 struct intel_crtc_state *crtc_state,
5902 intel_clock_t *reduced_clock)
5903 {
5904 struct drm_device *dev = crtc->base.dev;
5905 u32 fp, fp2 = 0;
5906
5907 if (IS_PINEVIEW(dev)) {
5908 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
5909 if (reduced_clock)
5910 fp2 = pnv_dpll_compute_fp(reduced_clock);
5911 } else {
5912 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
5913 if (reduced_clock)
5914 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5915 }
5916
5917 crtc_state->dpll_hw_state.fp0 = fp;
5918
5919 crtc->lowfreq_avail = false;
5920 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5921 reduced_clock && i915.powersave) {
5922 crtc_state->dpll_hw_state.fp1 = fp2;
5923 crtc->lowfreq_avail = true;
5924 } else {
5925 crtc_state->dpll_hw_state.fp1 = fp;
5926 }
5927 }
5928
5929 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5930 pipe)
5931 {
5932 u32 reg_val;
5933
5934 /*
5935 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5936 * and set it to a reasonable value instead.
5937 */
5938 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5939 reg_val &= 0xffffff00;
5940 reg_val |= 0x00000030;
5941 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5942
5943 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5944 reg_val &= 0x8cffffff;
5945 reg_val = 0x8c000000;
5946 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5947
5948 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5949 reg_val &= 0xffffff00;
5950 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5951
5952 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5953 reg_val &= 0x00ffffff;
5954 reg_val |= 0xb0000000;
5955 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5956 }
5957
5958 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5959 struct intel_link_m_n *m_n)
5960 {
5961 struct drm_device *dev = crtc->base.dev;
5962 struct drm_i915_private *dev_priv = dev->dev_private;
5963 int pipe = crtc->pipe;
5964
5965 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5966 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5967 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5968 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5969 }
5970
5971 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5972 struct intel_link_m_n *m_n,
5973 struct intel_link_m_n *m2_n2)
5974 {
5975 struct drm_device *dev = crtc->base.dev;
5976 struct drm_i915_private *dev_priv = dev->dev_private;
5977 int pipe = crtc->pipe;
5978 enum transcoder transcoder = crtc->config->cpu_transcoder;
5979
5980 if (INTEL_INFO(dev)->gen >= 5) {
5981 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5982 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5983 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5984 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5985 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5986 * for gen < 8) and if DRRS is supported (to make sure the
5987 * registers are not unnecessarily accessed).
5988 */
5989 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
5990 crtc->config->has_drrs) {
5991 I915_WRITE(PIPE_DATA_M2(transcoder),
5992 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5993 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5994 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5995 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5996 }
5997 } else {
5998 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5999 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6000 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6001 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6002 }
6003 }
6004
6005 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6006 {
6007 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6008
6009 if (m_n == M1_N1) {
6010 dp_m_n = &crtc->config->dp_m_n;
6011 dp_m2_n2 = &crtc->config->dp_m2_n2;
6012 } else if (m_n == M2_N2) {
6013
6014 /*
6015 * M2_N2 registers are not supported. Hence m2_n2 divider value
6016 * needs to be programmed into M1_N1.
6017 */
6018 dp_m_n = &crtc->config->dp_m2_n2;
6019 } else {
6020 DRM_ERROR("Unsupported divider value\n");
6021 return;
6022 }
6023
6024 if (crtc->config->has_pch_encoder)
6025 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6026 else
6027 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6028 }
6029
6030 static void vlv_update_pll(struct intel_crtc *crtc,
6031 struct intel_crtc_state *pipe_config)
6032 {
6033 u32 dpll, dpll_md;
6034
6035 /*
6036 * Enable DPIO clock input. We should never disable the reference
6037 * clock for pipe B, since VGA hotplug / manual detection depends
6038 * on it.
6039 */
6040 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6041 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6042 /* We should never disable this, set it here for state tracking */
6043 if (crtc->pipe == PIPE_B)
6044 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6045 dpll |= DPLL_VCO_ENABLE;
6046 pipe_config->dpll_hw_state.dpll = dpll;
6047
6048 dpll_md = (pipe_config->pixel_multiplier - 1)
6049 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6050 pipe_config->dpll_hw_state.dpll_md = dpll_md;
6051 }
6052
6053 static void vlv_prepare_pll(struct intel_crtc *crtc,
6054 const struct intel_crtc_state *pipe_config)
6055 {
6056 struct drm_device *dev = crtc->base.dev;
6057 struct drm_i915_private *dev_priv = dev->dev_private;
6058 int pipe = crtc->pipe;
6059 u32 mdiv;
6060 u32 bestn, bestm1, bestm2, bestp1, bestp2;
6061 u32 coreclk, reg_val;
6062
6063 mutex_lock(&dev_priv->dpio_lock);
6064
6065 bestn = pipe_config->dpll.n;
6066 bestm1 = pipe_config->dpll.m1;
6067 bestm2 = pipe_config->dpll.m2;
6068 bestp1 = pipe_config->dpll.p1;
6069 bestp2 = pipe_config->dpll.p2;
6070
6071 /* See eDP HDMI DPIO driver vbios notes doc */
6072
6073 /* PLL B needs special handling */
6074 if (pipe == PIPE_B)
6075 vlv_pllb_recal_opamp(dev_priv, pipe);
6076
6077 /* Set up Tx target for periodic Rcomp update */
6078 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6079
6080 /* Disable target IRef on PLL */
6081 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6082 reg_val &= 0x00ffffff;
6083 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6084
6085 /* Disable fast lock */
6086 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6087
6088 /* Set idtafcrecal before PLL is enabled */
6089 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6090 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6091 mdiv |= ((bestn << DPIO_N_SHIFT));
6092 mdiv |= (1 << DPIO_K_SHIFT);
6093
6094 /*
6095 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6096 * but we don't support that).
6097 * Note: don't use the DAC post divider as it seems unstable.
6098 */
6099 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6100 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6101
6102 mdiv |= DPIO_ENABLE_CALIBRATION;
6103 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6104
6105 /* Set HBR and RBR LPF coefficients */
6106 if (pipe_config->port_clock == 162000 ||
6107 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6108 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
6109 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6110 0x009f0003);
6111 else
6112 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6113 0x00d0000f);
6114
6115 if (pipe_config->has_dp_encoder) {
6116 /* Use SSC source */
6117 if (pipe == PIPE_A)
6118 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6119 0x0df40000);
6120 else
6121 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6122 0x0df70000);
6123 } else { /* HDMI or VGA */
6124 /* Use bend source */
6125 if (pipe == PIPE_A)
6126 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6127 0x0df70000);
6128 else
6129 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6130 0x0df40000);
6131 }
6132
6133 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6134 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6135 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6136 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
6137 coreclk |= 0x01000000;
6138 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6139
6140 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6141 mutex_unlock(&dev_priv->dpio_lock);
6142 }
6143
6144 static void chv_update_pll(struct intel_crtc *crtc,
6145 struct intel_crtc_state *pipe_config)
6146 {
6147 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
6148 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6149 DPLL_VCO_ENABLE;
6150 if (crtc->pipe != PIPE_A)
6151 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6152
6153 pipe_config->dpll_hw_state.dpll_md =
6154 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6155 }
6156
6157 static void chv_prepare_pll(struct intel_crtc *crtc,
6158 const struct intel_crtc_state *pipe_config)
6159 {
6160 struct drm_device *dev = crtc->base.dev;
6161 struct drm_i915_private *dev_priv = dev->dev_private;
6162 int pipe = crtc->pipe;
6163 int dpll_reg = DPLL(crtc->pipe);
6164 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6165 u32 loopfilter, tribuf_calcntr;
6166 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6167 u32 dpio_val;
6168 int vco;
6169
6170 bestn = pipe_config->dpll.n;
6171 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6172 bestm1 = pipe_config->dpll.m1;
6173 bestm2 = pipe_config->dpll.m2 >> 22;
6174 bestp1 = pipe_config->dpll.p1;
6175 bestp2 = pipe_config->dpll.p2;
6176 vco = pipe_config->dpll.vco;
6177 dpio_val = 0;
6178 loopfilter = 0;
6179
6180 /*
6181 * Enable Refclk and SSC
6182 */
6183 I915_WRITE(dpll_reg,
6184 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6185
6186 mutex_lock(&dev_priv->dpio_lock);
6187
6188 /* p1 and p2 divider */
6189 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6190 5 << DPIO_CHV_S1_DIV_SHIFT |
6191 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6192 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6193 1 << DPIO_CHV_K_DIV_SHIFT);
6194
6195 /* Feedback post-divider - m2 */
6196 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6197
6198 /* Feedback refclk divider - n and m1 */
6199 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6200 DPIO_CHV_M1_DIV_BY_2 |
6201 1 << DPIO_CHV_N_DIV_SHIFT);
6202
6203 /* M2 fraction division */
6204 if (bestm2_frac)
6205 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6206
6207 /* M2 fraction division enable */
6208 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6209 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6210 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6211 if (bestm2_frac)
6212 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6213 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6214
6215 /* Program digital lock detect threshold */
6216 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6217 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6218 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6219 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6220 if (!bestm2_frac)
6221 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6222 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6223
6224 /* Loop filter */
6225 if (vco == 5400000) {
6226 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6227 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6228 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6229 tribuf_calcntr = 0x9;
6230 } else if (vco <= 6200000) {
6231 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6232 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6233 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6234 tribuf_calcntr = 0x9;
6235 } else if (vco <= 6480000) {
6236 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6237 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6238 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6239 tribuf_calcntr = 0x8;
6240 } else {
6241 /* Not supported. Apply the same limits as in the max case */
6242 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6243 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6244 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6245 tribuf_calcntr = 0;
6246 }
6247 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6248
6249 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(pipe));
6250 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6251 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6252 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6253
6254 /* AFC Recal */
6255 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6256 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6257 DPIO_AFC_RECAL);
6258
6259 mutex_unlock(&dev_priv->dpio_lock);
6260 }
6261
6262 /**
6263 * vlv_force_pll_on - forcibly enable just the PLL
6264 * @dev_priv: i915 private structure
6265 * @pipe: pipe PLL to enable
6266 * @dpll: PLL configuration
6267 *
6268 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6269 * in cases where we need the PLL enabled even when @pipe is not going to
6270 * be enabled.
6271 */
6272 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6273 const struct dpll *dpll)
6274 {
6275 struct intel_crtc *crtc =
6276 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6277 struct intel_crtc_state pipe_config = {
6278 .pixel_multiplier = 1,
6279 .dpll = *dpll,
6280 };
6281
6282 if (IS_CHERRYVIEW(dev)) {
6283 chv_update_pll(crtc, &pipe_config);
6284 chv_prepare_pll(crtc, &pipe_config);
6285 chv_enable_pll(crtc, &pipe_config);
6286 } else {
6287 vlv_update_pll(crtc, &pipe_config);
6288 vlv_prepare_pll(crtc, &pipe_config);
6289 vlv_enable_pll(crtc, &pipe_config);
6290 }
6291 }
6292
6293 /**
6294 * vlv_force_pll_off - forcibly disable just the PLL
6295 * @dev_priv: i915 private structure
6296 * @pipe: pipe PLL to disable
6297 *
6298 * Disable the PLL for @pipe. To be used in cases where we need
6299 * the PLL enabled even when @pipe is not going to be enabled.
6300 */
6301 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6302 {
6303 if (IS_CHERRYVIEW(dev))
6304 chv_disable_pll(to_i915(dev), pipe);
6305 else
6306 vlv_disable_pll(to_i915(dev), pipe);
6307 }
6308
6309 static void i9xx_update_pll(struct intel_crtc *crtc,
6310 struct intel_crtc_state *crtc_state,
6311 intel_clock_t *reduced_clock,
6312 int num_connectors)
6313 {
6314 struct drm_device *dev = crtc->base.dev;
6315 struct drm_i915_private *dev_priv = dev->dev_private;
6316 u32 dpll;
6317 bool is_sdvo;
6318 struct dpll *clock = &crtc_state->dpll;
6319
6320 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6321
6322 is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6323 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6324
6325 dpll = DPLL_VGA_MODE_DIS;
6326
6327 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6328 dpll |= DPLLB_MODE_LVDS;
6329 else
6330 dpll |= DPLLB_MODE_DAC_SERIAL;
6331
6332 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6333 dpll |= (crtc_state->pixel_multiplier - 1)
6334 << SDVO_MULTIPLIER_SHIFT_HIRES;
6335 }
6336
6337 if (is_sdvo)
6338 dpll |= DPLL_SDVO_HIGH_SPEED;
6339
6340 if (crtc_state->has_dp_encoder)
6341 dpll |= DPLL_SDVO_HIGH_SPEED;
6342
6343 /* compute bitmask from p1 value */
6344 if (IS_PINEVIEW(dev))
6345 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6346 else {
6347 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6348 if (IS_G4X(dev) && reduced_clock)
6349 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6350 }
6351 switch (clock->p2) {
6352 case 5:
6353 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6354 break;
6355 case 7:
6356 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6357 break;
6358 case 10:
6359 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6360 break;
6361 case 14:
6362 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6363 break;
6364 }
6365 if (INTEL_INFO(dev)->gen >= 4)
6366 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6367
6368 if (crtc_state->sdvo_tv_clock)
6369 dpll |= PLL_REF_INPUT_TVCLKINBC;
6370 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6371 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6372 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6373 else
6374 dpll |= PLL_REF_INPUT_DREFCLK;
6375
6376 dpll |= DPLL_VCO_ENABLE;
6377 crtc_state->dpll_hw_state.dpll = dpll;
6378
6379 if (INTEL_INFO(dev)->gen >= 4) {
6380 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6381 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6382 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6383 }
6384 }
6385
6386 static void i8xx_update_pll(struct intel_crtc *crtc,
6387 struct intel_crtc_state *crtc_state,
6388 intel_clock_t *reduced_clock,
6389 int num_connectors)
6390 {
6391 struct drm_device *dev = crtc->base.dev;
6392 struct drm_i915_private *dev_priv = dev->dev_private;
6393 u32 dpll;
6394 struct dpll *clock = &crtc_state->dpll;
6395
6396 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6397
6398 dpll = DPLL_VGA_MODE_DIS;
6399
6400 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6401 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6402 } else {
6403 if (clock->p1 == 2)
6404 dpll |= PLL_P1_DIVIDE_BY_TWO;
6405 else
6406 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6407 if (clock->p2 == 4)
6408 dpll |= PLL_P2_DIVIDE_BY_4;
6409 }
6410
6411 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6412 dpll |= DPLL_DVO_2X_MODE;
6413
6414 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6415 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6416 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6417 else
6418 dpll |= PLL_REF_INPUT_DREFCLK;
6419
6420 dpll |= DPLL_VCO_ENABLE;
6421 crtc_state->dpll_hw_state.dpll = dpll;
6422 }
6423
6424 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6425 {
6426 struct drm_device *dev = intel_crtc->base.dev;
6427 struct drm_i915_private *dev_priv = dev->dev_private;
6428 enum pipe pipe = intel_crtc->pipe;
6429 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6430 struct drm_display_mode *adjusted_mode =
6431 &intel_crtc->config->base.adjusted_mode;
6432 uint32_t crtc_vtotal, crtc_vblank_end;
6433 int vsyncshift = 0;
6434
6435 /* We need to be careful not to changed the adjusted mode, for otherwise
6436 * the hw state checker will get angry at the mismatch. */
6437 crtc_vtotal = adjusted_mode->crtc_vtotal;
6438 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6439
6440 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6441 /* the chip adds 2 halflines automatically */
6442 crtc_vtotal -= 1;
6443 crtc_vblank_end -= 1;
6444
6445 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6446 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6447 else
6448 vsyncshift = adjusted_mode->crtc_hsync_start -
6449 adjusted_mode->crtc_htotal / 2;
6450 if (vsyncshift < 0)
6451 vsyncshift += adjusted_mode->crtc_htotal;
6452 }
6453
6454 if (INTEL_INFO(dev)->gen > 3)
6455 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6456
6457 I915_WRITE(HTOTAL(cpu_transcoder),
6458 (adjusted_mode->crtc_hdisplay - 1) |
6459 ((adjusted_mode->crtc_htotal - 1) << 16));
6460 I915_WRITE(HBLANK(cpu_transcoder),
6461 (adjusted_mode->crtc_hblank_start - 1) |
6462 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6463 I915_WRITE(HSYNC(cpu_transcoder),
6464 (adjusted_mode->crtc_hsync_start - 1) |
6465 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6466
6467 I915_WRITE(VTOTAL(cpu_transcoder),
6468 (adjusted_mode->crtc_vdisplay - 1) |
6469 ((crtc_vtotal - 1) << 16));
6470 I915_WRITE(VBLANK(cpu_transcoder),
6471 (adjusted_mode->crtc_vblank_start - 1) |
6472 ((crtc_vblank_end - 1) << 16));
6473 I915_WRITE(VSYNC(cpu_transcoder),
6474 (adjusted_mode->crtc_vsync_start - 1) |
6475 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6476
6477 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6478 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6479 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6480 * bits. */
6481 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6482 (pipe == PIPE_B || pipe == PIPE_C))
6483 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6484
6485 /* pipesrc controls the size that is scaled from, which should
6486 * always be the user's requested size.
6487 */
6488 I915_WRITE(PIPESRC(pipe),
6489 ((intel_crtc->config->pipe_src_w - 1) << 16) |
6490 (intel_crtc->config->pipe_src_h - 1));
6491 }
6492
6493 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6494 struct intel_crtc_state *pipe_config)
6495 {
6496 struct drm_device *dev = crtc->base.dev;
6497 struct drm_i915_private *dev_priv = dev->dev_private;
6498 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6499 uint32_t tmp;
6500
6501 tmp = I915_READ(HTOTAL(cpu_transcoder));
6502 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6503 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6504 tmp = I915_READ(HBLANK(cpu_transcoder));
6505 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6506 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6507 tmp = I915_READ(HSYNC(cpu_transcoder));
6508 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6509 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6510
6511 tmp = I915_READ(VTOTAL(cpu_transcoder));
6512 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6513 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6514 tmp = I915_READ(VBLANK(cpu_transcoder));
6515 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6516 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6517 tmp = I915_READ(VSYNC(cpu_transcoder));
6518 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6519 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6520
6521 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6522 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6523 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6524 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6525 }
6526
6527 tmp = I915_READ(PIPESRC(crtc->pipe));
6528 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6529 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6530
6531 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6532 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
6533 }
6534
6535 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6536 struct intel_crtc_state *pipe_config)
6537 {
6538 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6539 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6540 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
6541 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
6542
6543 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
6544 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
6545 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
6546 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
6547
6548 mode->flags = pipe_config->base.adjusted_mode.flags;
6549
6550 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
6551 mode->flags |= pipe_config->base.adjusted_mode.flags;
6552 }
6553
6554 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6555 {
6556 struct drm_device *dev = intel_crtc->base.dev;
6557 struct drm_i915_private *dev_priv = dev->dev_private;
6558 uint32_t pipeconf;
6559
6560 pipeconf = 0;
6561
6562 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6563 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6564 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6565
6566 if (intel_crtc->config->double_wide)
6567 pipeconf |= PIPECONF_DOUBLE_WIDE;
6568
6569 /* only g4x and later have fancy bpc/dither controls */
6570 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6571 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6572 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
6573 pipeconf |= PIPECONF_DITHER_EN |
6574 PIPECONF_DITHER_TYPE_SP;
6575
6576 switch (intel_crtc->config->pipe_bpp) {
6577 case 18:
6578 pipeconf |= PIPECONF_6BPC;
6579 break;
6580 case 24:
6581 pipeconf |= PIPECONF_8BPC;
6582 break;
6583 case 30:
6584 pipeconf |= PIPECONF_10BPC;
6585 break;
6586 default:
6587 /* Case prevented by intel_choose_pipe_bpp_dither. */
6588 BUG();
6589 }
6590 }
6591
6592 if (HAS_PIPE_CXSR(dev)) {
6593 if (intel_crtc->lowfreq_avail) {
6594 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6595 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6596 } else {
6597 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6598 }
6599 }
6600
6601 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6602 if (INTEL_INFO(dev)->gen < 4 ||
6603 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6604 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6605 else
6606 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6607 } else
6608 pipeconf |= PIPECONF_PROGRESSIVE;
6609
6610 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
6611 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6612
6613 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6614 POSTING_READ(PIPECONF(intel_crtc->pipe));
6615 }
6616
6617 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
6618 struct intel_crtc_state *crtc_state)
6619 {
6620 struct drm_device *dev = crtc->base.dev;
6621 struct drm_i915_private *dev_priv = dev->dev_private;
6622 int refclk, num_connectors = 0;
6623 intel_clock_t clock, reduced_clock;
6624 bool ok, has_reduced_clock = false;
6625 bool is_lvds = false, is_dsi = false;
6626 struct intel_encoder *encoder;
6627 const intel_limit_t *limit;
6628
6629 for_each_intel_encoder(dev, encoder) {
6630 if (encoder->new_crtc != crtc)
6631 continue;
6632
6633 switch (encoder->type) {
6634 case INTEL_OUTPUT_LVDS:
6635 is_lvds = true;
6636 break;
6637 case INTEL_OUTPUT_DSI:
6638 is_dsi = true;
6639 break;
6640 default:
6641 break;
6642 }
6643
6644 num_connectors++;
6645 }
6646
6647 if (is_dsi)
6648 return 0;
6649
6650 if (!crtc_state->clock_set) {
6651 refclk = i9xx_get_refclk(crtc, num_connectors);
6652
6653 /*
6654 * Returns a set of divisors for the desired target clock with
6655 * the given refclk, or FALSE. The returned values represent
6656 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6657 * 2) / p1 / p2.
6658 */
6659 limit = intel_limit(crtc, refclk);
6660 ok = dev_priv->display.find_dpll(limit, crtc,
6661 crtc_state->port_clock,
6662 refclk, NULL, &clock);
6663 if (!ok) {
6664 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6665 return -EINVAL;
6666 }
6667
6668 if (is_lvds && dev_priv->lvds_downclock_avail) {
6669 /*
6670 * Ensure we match the reduced clock's P to the target
6671 * clock. If the clocks don't match, we can't switch
6672 * the display clock by using the FP0/FP1. In such case
6673 * we will disable the LVDS downclock feature.
6674 */
6675 has_reduced_clock =
6676 dev_priv->display.find_dpll(limit, crtc,
6677 dev_priv->lvds_downclock,
6678 refclk, &clock,
6679 &reduced_clock);
6680 }
6681 /* Compat-code for transition, will disappear. */
6682 crtc_state->dpll.n = clock.n;
6683 crtc_state->dpll.m1 = clock.m1;
6684 crtc_state->dpll.m2 = clock.m2;
6685 crtc_state->dpll.p1 = clock.p1;
6686 crtc_state->dpll.p2 = clock.p2;
6687 }
6688
6689 if (IS_GEN2(dev)) {
6690 i8xx_update_pll(crtc, crtc_state,
6691 has_reduced_clock ? &reduced_clock : NULL,
6692 num_connectors);
6693 } else if (IS_CHERRYVIEW(dev)) {
6694 chv_update_pll(crtc, crtc_state);
6695 } else if (IS_VALLEYVIEW(dev)) {
6696 vlv_update_pll(crtc, crtc_state);
6697 } else {
6698 i9xx_update_pll(crtc, crtc_state,
6699 has_reduced_clock ? &reduced_clock : NULL,
6700 num_connectors);
6701 }
6702
6703 return 0;
6704 }
6705
6706 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6707 struct intel_crtc_state *pipe_config)
6708 {
6709 struct drm_device *dev = crtc->base.dev;
6710 struct drm_i915_private *dev_priv = dev->dev_private;
6711 uint32_t tmp;
6712
6713 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6714 return;
6715
6716 tmp = I915_READ(PFIT_CONTROL);
6717 if (!(tmp & PFIT_ENABLE))
6718 return;
6719
6720 /* Check whether the pfit is attached to our pipe. */
6721 if (INTEL_INFO(dev)->gen < 4) {
6722 if (crtc->pipe != PIPE_B)
6723 return;
6724 } else {
6725 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6726 return;
6727 }
6728
6729 pipe_config->gmch_pfit.control = tmp;
6730 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6731 if (INTEL_INFO(dev)->gen < 5)
6732 pipe_config->gmch_pfit.lvds_border_bits =
6733 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6734 }
6735
6736 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6737 struct intel_crtc_state *pipe_config)
6738 {
6739 struct drm_device *dev = crtc->base.dev;
6740 struct drm_i915_private *dev_priv = dev->dev_private;
6741 int pipe = pipe_config->cpu_transcoder;
6742 intel_clock_t clock;
6743 u32 mdiv;
6744 int refclk = 100000;
6745
6746 /* In case of MIPI DPLL will not even be used */
6747 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6748 return;
6749
6750 mutex_lock(&dev_priv->dpio_lock);
6751 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6752 mutex_unlock(&dev_priv->dpio_lock);
6753
6754 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6755 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6756 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6757 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6758 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6759
6760 vlv_clock(refclk, &clock);
6761
6762 /* clock.dot is the fast clock */
6763 pipe_config->port_clock = clock.dot / 5;
6764 }
6765
6766 static void
6767 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
6768 struct intel_initial_plane_config *plane_config)
6769 {
6770 struct drm_device *dev = crtc->base.dev;
6771 struct drm_i915_private *dev_priv = dev->dev_private;
6772 u32 val, base, offset;
6773 int pipe = crtc->pipe, plane = crtc->plane;
6774 int fourcc, pixel_format;
6775 int aligned_height;
6776 struct drm_framebuffer *fb;
6777 struct intel_framebuffer *intel_fb;
6778
6779 val = I915_READ(DSPCNTR(plane));
6780 if (!(val & DISPLAY_PLANE_ENABLE))
6781 return;
6782
6783 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6784 if (!intel_fb) {
6785 DRM_DEBUG_KMS("failed to alloc fb\n");
6786 return;
6787 }
6788
6789 fb = &intel_fb->base;
6790
6791 if (INTEL_INFO(dev)->gen >= 4) {
6792 if (val & DISPPLANE_TILED) {
6793 plane_config->tiling = I915_TILING_X;
6794 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
6795 }
6796 }
6797
6798 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6799 fourcc = i9xx_format_to_fourcc(pixel_format);
6800 fb->pixel_format = fourcc;
6801 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
6802
6803 if (INTEL_INFO(dev)->gen >= 4) {
6804 if (plane_config->tiling)
6805 offset = I915_READ(DSPTILEOFF(plane));
6806 else
6807 offset = I915_READ(DSPLINOFF(plane));
6808 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6809 } else {
6810 base = I915_READ(DSPADDR(plane));
6811 }
6812 plane_config->base = base;
6813
6814 val = I915_READ(PIPESRC(pipe));
6815 fb->width = ((val >> 16) & 0xfff) + 1;
6816 fb->height = ((val >> 0) & 0xfff) + 1;
6817
6818 val = I915_READ(DSPSTRIDE(pipe));
6819 fb->pitches[0] = val & 0xffffffc0;
6820
6821 aligned_height = intel_fb_align_height(dev, fb->height,
6822 fb->pixel_format,
6823 fb->modifier[0]);
6824
6825 plane_config->size = fb->pitches[0] * aligned_height;
6826
6827 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6828 pipe_name(pipe), plane, fb->width, fb->height,
6829 fb->bits_per_pixel, base, fb->pitches[0],
6830 plane_config->size);
6831
6832 plane_config->fb = intel_fb;
6833 }
6834
6835 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6836 struct intel_crtc_state *pipe_config)
6837 {
6838 struct drm_device *dev = crtc->base.dev;
6839 struct drm_i915_private *dev_priv = dev->dev_private;
6840 int pipe = pipe_config->cpu_transcoder;
6841 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6842 intel_clock_t clock;
6843 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6844 int refclk = 100000;
6845
6846 mutex_lock(&dev_priv->dpio_lock);
6847 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6848 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6849 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6850 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6851 mutex_unlock(&dev_priv->dpio_lock);
6852
6853 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6854 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6855 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6856 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6857 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6858
6859 chv_clock(refclk, &clock);
6860
6861 /* clock.dot is the fast clock */
6862 pipe_config->port_clock = clock.dot / 5;
6863 }
6864
6865 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6866 struct intel_crtc_state *pipe_config)
6867 {
6868 struct drm_device *dev = crtc->base.dev;
6869 struct drm_i915_private *dev_priv = dev->dev_private;
6870 uint32_t tmp;
6871
6872 if (!intel_display_power_is_enabled(dev_priv,
6873 POWER_DOMAIN_PIPE(crtc->pipe)))
6874 return false;
6875
6876 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6877 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6878
6879 tmp = I915_READ(PIPECONF(crtc->pipe));
6880 if (!(tmp & PIPECONF_ENABLE))
6881 return false;
6882
6883 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6884 switch (tmp & PIPECONF_BPC_MASK) {
6885 case PIPECONF_6BPC:
6886 pipe_config->pipe_bpp = 18;
6887 break;
6888 case PIPECONF_8BPC:
6889 pipe_config->pipe_bpp = 24;
6890 break;
6891 case PIPECONF_10BPC:
6892 pipe_config->pipe_bpp = 30;
6893 break;
6894 default:
6895 break;
6896 }
6897 }
6898
6899 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6900 pipe_config->limited_color_range = true;
6901
6902 if (INTEL_INFO(dev)->gen < 4)
6903 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6904
6905 intel_get_pipe_timings(crtc, pipe_config);
6906
6907 i9xx_get_pfit_config(crtc, pipe_config);
6908
6909 if (INTEL_INFO(dev)->gen >= 4) {
6910 tmp = I915_READ(DPLL_MD(crtc->pipe));
6911 pipe_config->pixel_multiplier =
6912 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6913 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6914 pipe_config->dpll_hw_state.dpll_md = tmp;
6915 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6916 tmp = I915_READ(DPLL(crtc->pipe));
6917 pipe_config->pixel_multiplier =
6918 ((tmp & SDVO_MULTIPLIER_MASK)
6919 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6920 } else {
6921 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6922 * port and will be fixed up in the encoder->get_config
6923 * function. */
6924 pipe_config->pixel_multiplier = 1;
6925 }
6926 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6927 if (!IS_VALLEYVIEW(dev)) {
6928 /*
6929 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6930 * on 830. Filter it out here so that we don't
6931 * report errors due to that.
6932 */
6933 if (IS_I830(dev))
6934 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6935
6936 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6937 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6938 } else {
6939 /* Mask out read-only status bits. */
6940 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6941 DPLL_PORTC_READY_MASK |
6942 DPLL_PORTB_READY_MASK);
6943 }
6944
6945 if (IS_CHERRYVIEW(dev))
6946 chv_crtc_clock_get(crtc, pipe_config);
6947 else if (IS_VALLEYVIEW(dev))
6948 vlv_crtc_clock_get(crtc, pipe_config);
6949 else
6950 i9xx_crtc_clock_get(crtc, pipe_config);
6951
6952 return true;
6953 }
6954
6955 static void ironlake_init_pch_refclk(struct drm_device *dev)
6956 {
6957 struct drm_i915_private *dev_priv = dev->dev_private;
6958 struct intel_encoder *encoder;
6959 u32 val, final;
6960 bool has_lvds = false;
6961 bool has_cpu_edp = false;
6962 bool has_panel = false;
6963 bool has_ck505 = false;
6964 bool can_ssc = false;
6965
6966 /* We need to take the global config into account */
6967 for_each_intel_encoder(dev, encoder) {
6968 switch (encoder->type) {
6969 case INTEL_OUTPUT_LVDS:
6970 has_panel = true;
6971 has_lvds = true;
6972 break;
6973 case INTEL_OUTPUT_EDP:
6974 has_panel = true;
6975 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6976 has_cpu_edp = true;
6977 break;
6978 default:
6979 break;
6980 }
6981 }
6982
6983 if (HAS_PCH_IBX(dev)) {
6984 has_ck505 = dev_priv->vbt.display_clock_mode;
6985 can_ssc = has_ck505;
6986 } else {
6987 has_ck505 = false;
6988 can_ssc = true;
6989 }
6990
6991 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6992 has_panel, has_lvds, has_ck505);
6993
6994 /* Ironlake: try to setup display ref clock before DPLL
6995 * enabling. This is only under driver's control after
6996 * PCH B stepping, previous chipset stepping should be
6997 * ignoring this setting.
6998 */
6999 val = I915_READ(PCH_DREF_CONTROL);
7000
7001 /* As we must carefully and slowly disable/enable each source in turn,
7002 * compute the final state we want first and check if we need to
7003 * make any changes at all.
7004 */
7005 final = val;
7006 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7007 if (has_ck505)
7008 final |= DREF_NONSPREAD_CK505_ENABLE;
7009 else
7010 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7011
7012 final &= ~DREF_SSC_SOURCE_MASK;
7013 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7014 final &= ~DREF_SSC1_ENABLE;
7015
7016 if (has_panel) {
7017 final |= DREF_SSC_SOURCE_ENABLE;
7018
7019 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7020 final |= DREF_SSC1_ENABLE;
7021
7022 if (has_cpu_edp) {
7023 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7024 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7025 else
7026 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7027 } else
7028 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7029 } else {
7030 final |= DREF_SSC_SOURCE_DISABLE;
7031 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7032 }
7033
7034 if (final == val)
7035 return;
7036
7037 /* Always enable nonspread source */
7038 val &= ~DREF_NONSPREAD_SOURCE_MASK;
7039
7040 if (has_ck505)
7041 val |= DREF_NONSPREAD_CK505_ENABLE;
7042 else
7043 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7044
7045 if (has_panel) {
7046 val &= ~DREF_SSC_SOURCE_MASK;
7047 val |= DREF_SSC_SOURCE_ENABLE;
7048
7049 /* SSC must be turned on before enabling the CPU output */
7050 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7051 DRM_DEBUG_KMS("Using SSC on panel\n");
7052 val |= DREF_SSC1_ENABLE;
7053 } else
7054 val &= ~DREF_SSC1_ENABLE;
7055
7056 /* Get SSC going before enabling the outputs */
7057 I915_WRITE(PCH_DREF_CONTROL, val);
7058 POSTING_READ(PCH_DREF_CONTROL);
7059 udelay(200);
7060
7061 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7062
7063 /* Enable CPU source on CPU attached eDP */
7064 if (has_cpu_edp) {
7065 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7066 DRM_DEBUG_KMS("Using SSC on eDP\n");
7067 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7068 } else
7069 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7070 } else
7071 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7072
7073 I915_WRITE(PCH_DREF_CONTROL, val);
7074 POSTING_READ(PCH_DREF_CONTROL);
7075 udelay(200);
7076 } else {
7077 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7078
7079 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7080
7081 /* Turn off CPU output */
7082 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7083
7084 I915_WRITE(PCH_DREF_CONTROL, val);
7085 POSTING_READ(PCH_DREF_CONTROL);
7086 udelay(200);
7087
7088 /* Turn off the SSC source */
7089 val &= ~DREF_SSC_SOURCE_MASK;
7090 val |= DREF_SSC_SOURCE_DISABLE;
7091
7092 /* Turn off SSC1 */
7093 val &= ~DREF_SSC1_ENABLE;
7094
7095 I915_WRITE(PCH_DREF_CONTROL, val);
7096 POSTING_READ(PCH_DREF_CONTROL);
7097 udelay(200);
7098 }
7099
7100 BUG_ON(val != final);
7101 }
7102
7103 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7104 {
7105 uint32_t tmp;
7106
7107 tmp = I915_READ(SOUTH_CHICKEN2);
7108 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7109 I915_WRITE(SOUTH_CHICKEN2, tmp);
7110
7111 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7112 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7113 DRM_ERROR("FDI mPHY reset assert timeout\n");
7114
7115 tmp = I915_READ(SOUTH_CHICKEN2);
7116 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7117 I915_WRITE(SOUTH_CHICKEN2, tmp);
7118
7119 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7120 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7121 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7122 }
7123
7124 /* WaMPhyProgramming:hsw */
7125 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7126 {
7127 uint32_t tmp;
7128
7129 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7130 tmp &= ~(0xFF << 24);
7131 tmp |= (0x12 << 24);
7132 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7133
7134 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7135 tmp |= (1 << 11);
7136 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7137
7138 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7139 tmp |= (1 << 11);
7140 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7141
7142 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7143 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7144 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7145
7146 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7147 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7148 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7149
7150 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7151 tmp &= ~(7 << 13);
7152 tmp |= (5 << 13);
7153 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7154
7155 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7156 tmp &= ~(7 << 13);
7157 tmp |= (5 << 13);
7158 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7159
7160 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7161 tmp &= ~0xFF;
7162 tmp |= 0x1C;
7163 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7164
7165 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7166 tmp &= ~0xFF;
7167 tmp |= 0x1C;
7168 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7169
7170 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7171 tmp &= ~(0xFF << 16);
7172 tmp |= (0x1C << 16);
7173 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7174
7175 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7176 tmp &= ~(0xFF << 16);
7177 tmp |= (0x1C << 16);
7178 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7179
7180 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7181 tmp |= (1 << 27);
7182 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7183
7184 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7185 tmp |= (1 << 27);
7186 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7187
7188 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7189 tmp &= ~(0xF << 28);
7190 tmp |= (4 << 28);
7191 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7192
7193 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7194 tmp &= ~(0xF << 28);
7195 tmp |= (4 << 28);
7196 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7197 }
7198
7199 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7200 * Programming" based on the parameters passed:
7201 * - Sequence to enable CLKOUT_DP
7202 * - Sequence to enable CLKOUT_DP without spread
7203 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7204 */
7205 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
7206 bool with_fdi)
7207 {
7208 struct drm_i915_private *dev_priv = dev->dev_private;
7209 uint32_t reg, tmp;
7210
7211 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7212 with_spread = true;
7213 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
7214 with_fdi, "LP PCH doesn't have FDI\n"))
7215 with_fdi = false;
7216
7217 mutex_lock(&dev_priv->dpio_lock);
7218
7219 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7220 tmp &= ~SBI_SSCCTL_DISABLE;
7221 tmp |= SBI_SSCCTL_PATHALT;
7222 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7223
7224 udelay(24);
7225
7226 if (with_spread) {
7227 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7228 tmp &= ~SBI_SSCCTL_PATHALT;
7229 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7230
7231 if (with_fdi) {
7232 lpt_reset_fdi_mphy(dev_priv);
7233 lpt_program_fdi_mphy(dev_priv);
7234 }
7235 }
7236
7237 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7238 SBI_GEN0 : SBI_DBUFF0;
7239 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7240 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7241 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7242
7243 mutex_unlock(&dev_priv->dpio_lock);
7244 }
7245
7246 /* Sequence to disable CLKOUT_DP */
7247 static void lpt_disable_clkout_dp(struct drm_device *dev)
7248 {
7249 struct drm_i915_private *dev_priv = dev->dev_private;
7250 uint32_t reg, tmp;
7251
7252 mutex_lock(&dev_priv->dpio_lock);
7253
7254 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7255 SBI_GEN0 : SBI_DBUFF0;
7256 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7257 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7258 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7259
7260 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7261 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7262 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7263 tmp |= SBI_SSCCTL_PATHALT;
7264 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7265 udelay(32);
7266 }
7267 tmp |= SBI_SSCCTL_DISABLE;
7268 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7269 }
7270
7271 mutex_unlock(&dev_priv->dpio_lock);
7272 }
7273
7274 static void lpt_init_pch_refclk(struct drm_device *dev)
7275 {
7276 struct intel_encoder *encoder;
7277 bool has_vga = false;
7278
7279 for_each_intel_encoder(dev, encoder) {
7280 switch (encoder->type) {
7281 case INTEL_OUTPUT_ANALOG:
7282 has_vga = true;
7283 break;
7284 default:
7285 break;
7286 }
7287 }
7288
7289 if (has_vga)
7290 lpt_enable_clkout_dp(dev, true, true);
7291 else
7292 lpt_disable_clkout_dp(dev);
7293 }
7294
7295 /*
7296 * Initialize reference clocks when the driver loads
7297 */
7298 void intel_init_pch_refclk(struct drm_device *dev)
7299 {
7300 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7301 ironlake_init_pch_refclk(dev);
7302 else if (HAS_PCH_LPT(dev))
7303 lpt_init_pch_refclk(dev);
7304 }
7305
7306 static int ironlake_get_refclk(struct drm_crtc *crtc)
7307 {
7308 struct drm_device *dev = crtc->dev;
7309 struct drm_i915_private *dev_priv = dev->dev_private;
7310 struct intel_encoder *encoder;
7311 int num_connectors = 0;
7312 bool is_lvds = false;
7313
7314 for_each_intel_encoder(dev, encoder) {
7315 if (encoder->new_crtc != to_intel_crtc(crtc))
7316 continue;
7317
7318 switch (encoder->type) {
7319 case INTEL_OUTPUT_LVDS:
7320 is_lvds = true;
7321 break;
7322 default:
7323 break;
7324 }
7325 num_connectors++;
7326 }
7327
7328 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7329 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7330 dev_priv->vbt.lvds_ssc_freq);
7331 return dev_priv->vbt.lvds_ssc_freq;
7332 }
7333
7334 return 120000;
7335 }
7336
7337 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7338 {
7339 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7340 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7341 int pipe = intel_crtc->pipe;
7342 uint32_t val;
7343
7344 val = 0;
7345
7346 switch (intel_crtc->config->pipe_bpp) {
7347 case 18:
7348 val |= PIPECONF_6BPC;
7349 break;
7350 case 24:
7351 val |= PIPECONF_8BPC;
7352 break;
7353 case 30:
7354 val |= PIPECONF_10BPC;
7355 break;
7356 case 36:
7357 val |= PIPECONF_12BPC;
7358 break;
7359 default:
7360 /* Case prevented by intel_choose_pipe_bpp_dither. */
7361 BUG();
7362 }
7363
7364 if (intel_crtc->config->dither)
7365 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7366
7367 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7368 val |= PIPECONF_INTERLACED_ILK;
7369 else
7370 val |= PIPECONF_PROGRESSIVE;
7371
7372 if (intel_crtc->config->limited_color_range)
7373 val |= PIPECONF_COLOR_RANGE_SELECT;
7374
7375 I915_WRITE(PIPECONF(pipe), val);
7376 POSTING_READ(PIPECONF(pipe));
7377 }
7378
7379 /*
7380 * Set up the pipe CSC unit.
7381 *
7382 * Currently only full range RGB to limited range RGB conversion
7383 * is supported, but eventually this should handle various
7384 * RGB<->YCbCr scenarios as well.
7385 */
7386 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7387 {
7388 struct drm_device *dev = crtc->dev;
7389 struct drm_i915_private *dev_priv = dev->dev_private;
7390 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7391 int pipe = intel_crtc->pipe;
7392 uint16_t coeff = 0x7800; /* 1.0 */
7393
7394 /*
7395 * TODO: Check what kind of values actually come out of the pipe
7396 * with these coeff/postoff values and adjust to get the best
7397 * accuracy. Perhaps we even need to take the bpc value into
7398 * consideration.
7399 */
7400
7401 if (intel_crtc->config->limited_color_range)
7402 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7403
7404 /*
7405 * GY/GU and RY/RU should be the other way around according
7406 * to BSpec, but reality doesn't agree. Just set them up in
7407 * a way that results in the correct picture.
7408 */
7409 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7410 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7411
7412 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7413 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7414
7415 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7416 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7417
7418 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7419 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7420 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7421
7422 if (INTEL_INFO(dev)->gen > 6) {
7423 uint16_t postoff = 0;
7424
7425 if (intel_crtc->config->limited_color_range)
7426 postoff = (16 * (1 << 12) / 255) & 0x1fff;
7427
7428 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7429 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7430 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7431
7432 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7433 } else {
7434 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7435
7436 if (intel_crtc->config->limited_color_range)
7437 mode |= CSC_BLACK_SCREEN_OFFSET;
7438
7439 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7440 }
7441 }
7442
7443 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7444 {
7445 struct drm_device *dev = crtc->dev;
7446 struct drm_i915_private *dev_priv = dev->dev_private;
7447 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7448 enum pipe pipe = intel_crtc->pipe;
7449 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7450 uint32_t val;
7451
7452 val = 0;
7453
7454 if (IS_HASWELL(dev) && intel_crtc->config->dither)
7455 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7456
7457 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7458 val |= PIPECONF_INTERLACED_ILK;
7459 else
7460 val |= PIPECONF_PROGRESSIVE;
7461
7462 I915_WRITE(PIPECONF(cpu_transcoder), val);
7463 POSTING_READ(PIPECONF(cpu_transcoder));
7464
7465 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7466 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7467
7468 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7469 val = 0;
7470
7471 switch (intel_crtc->config->pipe_bpp) {
7472 case 18:
7473 val |= PIPEMISC_DITHER_6_BPC;
7474 break;
7475 case 24:
7476 val |= PIPEMISC_DITHER_8_BPC;
7477 break;
7478 case 30:
7479 val |= PIPEMISC_DITHER_10_BPC;
7480 break;
7481 case 36:
7482 val |= PIPEMISC_DITHER_12_BPC;
7483 break;
7484 default:
7485 /* Case prevented by pipe_config_set_bpp. */
7486 BUG();
7487 }
7488
7489 if (intel_crtc->config->dither)
7490 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7491
7492 I915_WRITE(PIPEMISC(pipe), val);
7493 }
7494 }
7495
7496 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7497 struct intel_crtc_state *crtc_state,
7498 intel_clock_t *clock,
7499 bool *has_reduced_clock,
7500 intel_clock_t *reduced_clock)
7501 {
7502 struct drm_device *dev = crtc->dev;
7503 struct drm_i915_private *dev_priv = dev->dev_private;
7504 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7505 int refclk;
7506 const intel_limit_t *limit;
7507 bool ret, is_lvds = false;
7508
7509 is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
7510
7511 refclk = ironlake_get_refclk(crtc);
7512
7513 /*
7514 * Returns a set of divisors for the desired target clock with the given
7515 * refclk, or FALSE. The returned values represent the clock equation:
7516 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7517 */
7518 limit = intel_limit(intel_crtc, refclk);
7519 ret = dev_priv->display.find_dpll(limit, intel_crtc,
7520 crtc_state->port_clock,
7521 refclk, NULL, clock);
7522 if (!ret)
7523 return false;
7524
7525 if (is_lvds && dev_priv->lvds_downclock_avail) {
7526 /*
7527 * Ensure we match the reduced clock's P to the target clock.
7528 * If the clocks don't match, we can't switch the display clock
7529 * by using the FP0/FP1. In such case we will disable the LVDS
7530 * downclock feature.
7531 */
7532 *has_reduced_clock =
7533 dev_priv->display.find_dpll(limit, intel_crtc,
7534 dev_priv->lvds_downclock,
7535 refclk, clock,
7536 reduced_clock);
7537 }
7538
7539 return true;
7540 }
7541
7542 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7543 {
7544 /*
7545 * Account for spread spectrum to avoid
7546 * oversubscribing the link. Max center spread
7547 * is 2.5%; use 5% for safety's sake.
7548 */
7549 u32 bps = target_clock * bpp * 21 / 20;
7550 return DIV_ROUND_UP(bps, link_bw * 8);
7551 }
7552
7553 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7554 {
7555 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7556 }
7557
7558 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7559 struct intel_crtc_state *crtc_state,
7560 u32 *fp,
7561 intel_clock_t *reduced_clock, u32 *fp2)
7562 {
7563 struct drm_crtc *crtc = &intel_crtc->base;
7564 struct drm_device *dev = crtc->dev;
7565 struct drm_i915_private *dev_priv = dev->dev_private;
7566 struct intel_encoder *intel_encoder;
7567 uint32_t dpll;
7568 int factor, num_connectors = 0;
7569 bool is_lvds = false, is_sdvo = false;
7570
7571 for_each_intel_encoder(dev, intel_encoder) {
7572 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7573 continue;
7574
7575 switch (intel_encoder->type) {
7576 case INTEL_OUTPUT_LVDS:
7577 is_lvds = true;
7578 break;
7579 case INTEL_OUTPUT_SDVO:
7580 case INTEL_OUTPUT_HDMI:
7581 is_sdvo = true;
7582 break;
7583 default:
7584 break;
7585 }
7586
7587 num_connectors++;
7588 }
7589
7590 /* Enable autotuning of the PLL clock (if permissible) */
7591 factor = 21;
7592 if (is_lvds) {
7593 if ((intel_panel_use_ssc(dev_priv) &&
7594 dev_priv->vbt.lvds_ssc_freq == 100000) ||
7595 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7596 factor = 25;
7597 } else if (crtc_state->sdvo_tv_clock)
7598 factor = 20;
7599
7600 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7601 *fp |= FP_CB_TUNE;
7602
7603 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7604 *fp2 |= FP_CB_TUNE;
7605
7606 dpll = 0;
7607
7608 if (is_lvds)
7609 dpll |= DPLLB_MODE_LVDS;
7610 else
7611 dpll |= DPLLB_MODE_DAC_SERIAL;
7612
7613 dpll |= (crtc_state->pixel_multiplier - 1)
7614 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7615
7616 if (is_sdvo)
7617 dpll |= DPLL_SDVO_HIGH_SPEED;
7618 if (crtc_state->has_dp_encoder)
7619 dpll |= DPLL_SDVO_HIGH_SPEED;
7620
7621 /* compute bitmask from p1 value */
7622 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7623 /* also FPA1 */
7624 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7625
7626 switch (crtc_state->dpll.p2) {
7627 case 5:
7628 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7629 break;
7630 case 7:
7631 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7632 break;
7633 case 10:
7634 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7635 break;
7636 case 14:
7637 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7638 break;
7639 }
7640
7641 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7642 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7643 else
7644 dpll |= PLL_REF_INPUT_DREFCLK;
7645
7646 return dpll | DPLL_VCO_ENABLE;
7647 }
7648
7649 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
7650 struct intel_crtc_state *crtc_state)
7651 {
7652 struct drm_device *dev = crtc->base.dev;
7653 intel_clock_t clock, reduced_clock;
7654 u32 dpll = 0, fp = 0, fp2 = 0;
7655 bool ok, has_reduced_clock = false;
7656 bool is_lvds = false;
7657 struct intel_shared_dpll *pll;
7658
7659 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7660
7661 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7662 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7663
7664 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
7665 &has_reduced_clock, &reduced_clock);
7666 if (!ok && !crtc_state->clock_set) {
7667 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7668 return -EINVAL;
7669 }
7670 /* Compat-code for transition, will disappear. */
7671 if (!crtc_state->clock_set) {
7672 crtc_state->dpll.n = clock.n;
7673 crtc_state->dpll.m1 = clock.m1;
7674 crtc_state->dpll.m2 = clock.m2;
7675 crtc_state->dpll.p1 = clock.p1;
7676 crtc_state->dpll.p2 = clock.p2;
7677 }
7678
7679 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7680 if (crtc_state->has_pch_encoder) {
7681 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7682 if (has_reduced_clock)
7683 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7684
7685 dpll = ironlake_compute_dpll(crtc, crtc_state,
7686 &fp, &reduced_clock,
7687 has_reduced_clock ? &fp2 : NULL);
7688
7689 crtc_state->dpll_hw_state.dpll = dpll;
7690 crtc_state->dpll_hw_state.fp0 = fp;
7691 if (has_reduced_clock)
7692 crtc_state->dpll_hw_state.fp1 = fp2;
7693 else
7694 crtc_state->dpll_hw_state.fp1 = fp;
7695
7696 pll = intel_get_shared_dpll(crtc, crtc_state);
7697 if (pll == NULL) {
7698 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7699 pipe_name(crtc->pipe));
7700 return -EINVAL;
7701 }
7702 }
7703
7704 if (is_lvds && has_reduced_clock && i915.powersave)
7705 crtc->lowfreq_avail = true;
7706 else
7707 crtc->lowfreq_avail = false;
7708
7709 return 0;
7710 }
7711
7712 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7713 struct intel_link_m_n *m_n)
7714 {
7715 struct drm_device *dev = crtc->base.dev;
7716 struct drm_i915_private *dev_priv = dev->dev_private;
7717 enum pipe pipe = crtc->pipe;
7718
7719 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7720 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7721 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7722 & ~TU_SIZE_MASK;
7723 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7724 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7725 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7726 }
7727
7728 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7729 enum transcoder transcoder,
7730 struct intel_link_m_n *m_n,
7731 struct intel_link_m_n *m2_n2)
7732 {
7733 struct drm_device *dev = crtc->base.dev;
7734 struct drm_i915_private *dev_priv = dev->dev_private;
7735 enum pipe pipe = crtc->pipe;
7736
7737 if (INTEL_INFO(dev)->gen >= 5) {
7738 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7739 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7740 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7741 & ~TU_SIZE_MASK;
7742 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7743 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7744 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7745 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7746 * gen < 8) and if DRRS is supported (to make sure the
7747 * registers are not unnecessarily read).
7748 */
7749 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7750 crtc->config->has_drrs) {
7751 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7752 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7753 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7754 & ~TU_SIZE_MASK;
7755 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7756 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7757 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7758 }
7759 } else {
7760 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7761 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7762 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7763 & ~TU_SIZE_MASK;
7764 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7765 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7766 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7767 }
7768 }
7769
7770 void intel_dp_get_m_n(struct intel_crtc *crtc,
7771 struct intel_crtc_state *pipe_config)
7772 {
7773 if (pipe_config->has_pch_encoder)
7774 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7775 else
7776 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7777 &pipe_config->dp_m_n,
7778 &pipe_config->dp_m2_n2);
7779 }
7780
7781 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7782 struct intel_crtc_state *pipe_config)
7783 {
7784 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7785 &pipe_config->fdi_m_n, NULL);
7786 }
7787
7788 static void skylake_get_pfit_config(struct intel_crtc *crtc,
7789 struct intel_crtc_state *pipe_config)
7790 {
7791 struct drm_device *dev = crtc->base.dev;
7792 struct drm_i915_private *dev_priv = dev->dev_private;
7793 uint32_t tmp;
7794
7795 tmp = I915_READ(PS_CTL(crtc->pipe));
7796
7797 if (tmp & PS_ENABLE) {
7798 pipe_config->pch_pfit.enabled = true;
7799 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
7800 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
7801 }
7802 }
7803
7804 static void
7805 skylake_get_initial_plane_config(struct intel_crtc *crtc,
7806 struct intel_initial_plane_config *plane_config)
7807 {
7808 struct drm_device *dev = crtc->base.dev;
7809 struct drm_i915_private *dev_priv = dev->dev_private;
7810 u32 val, base, offset, stride_mult, tiling;
7811 int pipe = crtc->pipe;
7812 int fourcc, pixel_format;
7813 int aligned_height;
7814 struct drm_framebuffer *fb;
7815 struct intel_framebuffer *intel_fb;
7816
7817 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7818 if (!intel_fb) {
7819 DRM_DEBUG_KMS("failed to alloc fb\n");
7820 return;
7821 }
7822
7823 fb = &intel_fb->base;
7824
7825 val = I915_READ(PLANE_CTL(pipe, 0));
7826 if (!(val & PLANE_CTL_ENABLE))
7827 goto error;
7828
7829 pixel_format = val & PLANE_CTL_FORMAT_MASK;
7830 fourcc = skl_format_to_fourcc(pixel_format,
7831 val & PLANE_CTL_ORDER_RGBX,
7832 val & PLANE_CTL_ALPHA_MASK);
7833 fb->pixel_format = fourcc;
7834 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7835
7836 tiling = val & PLANE_CTL_TILED_MASK;
7837 switch (tiling) {
7838 case PLANE_CTL_TILED_LINEAR:
7839 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
7840 break;
7841 case PLANE_CTL_TILED_X:
7842 plane_config->tiling = I915_TILING_X;
7843 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7844 break;
7845 case PLANE_CTL_TILED_Y:
7846 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
7847 break;
7848 case PLANE_CTL_TILED_YF:
7849 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
7850 break;
7851 default:
7852 MISSING_CASE(tiling);
7853 goto error;
7854 }
7855
7856 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
7857 plane_config->base = base;
7858
7859 offset = I915_READ(PLANE_OFFSET(pipe, 0));
7860
7861 val = I915_READ(PLANE_SIZE(pipe, 0));
7862 fb->height = ((val >> 16) & 0xfff) + 1;
7863 fb->width = ((val >> 0) & 0x1fff) + 1;
7864
7865 val = I915_READ(PLANE_STRIDE(pipe, 0));
7866 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
7867 fb->pixel_format);
7868 fb->pitches[0] = (val & 0x3ff) * stride_mult;
7869
7870 aligned_height = intel_fb_align_height(dev, fb->height,
7871 fb->pixel_format,
7872 fb->modifier[0]);
7873
7874 plane_config->size = fb->pitches[0] * aligned_height;
7875
7876 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7877 pipe_name(pipe), fb->width, fb->height,
7878 fb->bits_per_pixel, base, fb->pitches[0],
7879 plane_config->size);
7880
7881 plane_config->fb = intel_fb;
7882 return;
7883
7884 error:
7885 kfree(fb);
7886 }
7887
7888 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7889 struct intel_crtc_state *pipe_config)
7890 {
7891 struct drm_device *dev = crtc->base.dev;
7892 struct drm_i915_private *dev_priv = dev->dev_private;
7893 uint32_t tmp;
7894
7895 tmp = I915_READ(PF_CTL(crtc->pipe));
7896
7897 if (tmp & PF_ENABLE) {
7898 pipe_config->pch_pfit.enabled = true;
7899 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7900 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7901
7902 /* We currently do not free assignements of panel fitters on
7903 * ivb/hsw (since we don't use the higher upscaling modes which
7904 * differentiates them) so just WARN about this case for now. */
7905 if (IS_GEN7(dev)) {
7906 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7907 PF_PIPE_SEL_IVB(crtc->pipe));
7908 }
7909 }
7910 }
7911
7912 static void
7913 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
7914 struct intel_initial_plane_config *plane_config)
7915 {
7916 struct drm_device *dev = crtc->base.dev;
7917 struct drm_i915_private *dev_priv = dev->dev_private;
7918 u32 val, base, offset;
7919 int pipe = crtc->pipe;
7920 int fourcc, pixel_format;
7921 int aligned_height;
7922 struct drm_framebuffer *fb;
7923 struct intel_framebuffer *intel_fb;
7924
7925 val = I915_READ(DSPCNTR(pipe));
7926 if (!(val & DISPLAY_PLANE_ENABLE))
7927 return;
7928
7929 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7930 if (!intel_fb) {
7931 DRM_DEBUG_KMS("failed to alloc fb\n");
7932 return;
7933 }
7934
7935 fb = &intel_fb->base;
7936
7937 if (INTEL_INFO(dev)->gen >= 4) {
7938 if (val & DISPPLANE_TILED) {
7939 plane_config->tiling = I915_TILING_X;
7940 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7941 }
7942 }
7943
7944 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7945 fourcc = i9xx_format_to_fourcc(pixel_format);
7946 fb->pixel_format = fourcc;
7947 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7948
7949 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
7950 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7951 offset = I915_READ(DSPOFFSET(pipe));
7952 } else {
7953 if (plane_config->tiling)
7954 offset = I915_READ(DSPTILEOFF(pipe));
7955 else
7956 offset = I915_READ(DSPLINOFF(pipe));
7957 }
7958 plane_config->base = base;
7959
7960 val = I915_READ(PIPESRC(pipe));
7961 fb->width = ((val >> 16) & 0xfff) + 1;
7962 fb->height = ((val >> 0) & 0xfff) + 1;
7963
7964 val = I915_READ(DSPSTRIDE(pipe));
7965 fb->pitches[0] = val & 0xffffffc0;
7966
7967 aligned_height = intel_fb_align_height(dev, fb->height,
7968 fb->pixel_format,
7969 fb->modifier[0]);
7970
7971 plane_config->size = fb->pitches[0] * aligned_height;
7972
7973 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7974 pipe_name(pipe), fb->width, fb->height,
7975 fb->bits_per_pixel, base, fb->pitches[0],
7976 plane_config->size);
7977
7978 plane_config->fb = intel_fb;
7979 }
7980
7981 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7982 struct intel_crtc_state *pipe_config)
7983 {
7984 struct drm_device *dev = crtc->base.dev;
7985 struct drm_i915_private *dev_priv = dev->dev_private;
7986 uint32_t tmp;
7987
7988 if (!intel_display_power_is_enabled(dev_priv,
7989 POWER_DOMAIN_PIPE(crtc->pipe)))
7990 return false;
7991
7992 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7993 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7994
7995 tmp = I915_READ(PIPECONF(crtc->pipe));
7996 if (!(tmp & PIPECONF_ENABLE))
7997 return false;
7998
7999 switch (tmp & PIPECONF_BPC_MASK) {
8000 case PIPECONF_6BPC:
8001 pipe_config->pipe_bpp = 18;
8002 break;
8003 case PIPECONF_8BPC:
8004 pipe_config->pipe_bpp = 24;
8005 break;
8006 case PIPECONF_10BPC:
8007 pipe_config->pipe_bpp = 30;
8008 break;
8009 case PIPECONF_12BPC:
8010 pipe_config->pipe_bpp = 36;
8011 break;
8012 default:
8013 break;
8014 }
8015
8016 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8017 pipe_config->limited_color_range = true;
8018
8019 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8020 struct intel_shared_dpll *pll;
8021
8022 pipe_config->has_pch_encoder = true;
8023
8024 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8025 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8026 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8027
8028 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8029
8030 if (HAS_PCH_IBX(dev_priv->dev)) {
8031 pipe_config->shared_dpll =
8032 (enum intel_dpll_id) crtc->pipe;
8033 } else {
8034 tmp = I915_READ(PCH_DPLL_SEL);
8035 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8036 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
8037 else
8038 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
8039 }
8040
8041 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8042
8043 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8044 &pipe_config->dpll_hw_state));
8045
8046 tmp = pipe_config->dpll_hw_state.dpll;
8047 pipe_config->pixel_multiplier =
8048 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8049 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8050
8051 ironlake_pch_clock_get(crtc, pipe_config);
8052 } else {
8053 pipe_config->pixel_multiplier = 1;
8054 }
8055
8056 intel_get_pipe_timings(crtc, pipe_config);
8057
8058 ironlake_get_pfit_config(crtc, pipe_config);
8059
8060 return true;
8061 }
8062
8063 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8064 {
8065 struct drm_device *dev = dev_priv->dev;
8066 struct intel_crtc *crtc;
8067
8068 for_each_intel_crtc(dev, crtc)
8069 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8070 pipe_name(crtc->pipe));
8071
8072 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8073 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8074 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8075 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8076 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8077 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8078 "CPU PWM1 enabled\n");
8079 if (IS_HASWELL(dev))
8080 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8081 "CPU PWM2 enabled\n");
8082 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8083 "PCH PWM1 enabled\n");
8084 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8085 "Utility pin enabled\n");
8086 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8087
8088 /*
8089 * In theory we can still leave IRQs enabled, as long as only the HPD
8090 * interrupts remain enabled. We used to check for that, but since it's
8091 * gen-specific and since we only disable LCPLL after we fully disable
8092 * the interrupts, the check below should be enough.
8093 */
8094 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8095 }
8096
8097 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8098 {
8099 struct drm_device *dev = dev_priv->dev;
8100
8101 if (IS_HASWELL(dev))
8102 return I915_READ(D_COMP_HSW);
8103 else
8104 return I915_READ(D_COMP_BDW);
8105 }
8106
8107 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8108 {
8109 struct drm_device *dev = dev_priv->dev;
8110
8111 if (IS_HASWELL(dev)) {
8112 mutex_lock(&dev_priv->rps.hw_lock);
8113 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8114 val))
8115 DRM_ERROR("Failed to write to D_COMP\n");
8116 mutex_unlock(&dev_priv->rps.hw_lock);
8117 } else {
8118 I915_WRITE(D_COMP_BDW, val);
8119 POSTING_READ(D_COMP_BDW);
8120 }
8121 }
8122
8123 /*
8124 * This function implements pieces of two sequences from BSpec:
8125 * - Sequence for display software to disable LCPLL
8126 * - Sequence for display software to allow package C8+
8127 * The steps implemented here are just the steps that actually touch the LCPLL
8128 * register. Callers should take care of disabling all the display engine
8129 * functions, doing the mode unset, fixing interrupts, etc.
8130 */
8131 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8132 bool switch_to_fclk, bool allow_power_down)
8133 {
8134 uint32_t val;
8135
8136 assert_can_disable_lcpll(dev_priv);
8137
8138 val = I915_READ(LCPLL_CTL);
8139
8140 if (switch_to_fclk) {
8141 val |= LCPLL_CD_SOURCE_FCLK;
8142 I915_WRITE(LCPLL_CTL, val);
8143
8144 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
8145 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8146 DRM_ERROR("Switching to FCLK failed\n");
8147
8148 val = I915_READ(LCPLL_CTL);
8149 }
8150
8151 val |= LCPLL_PLL_DISABLE;
8152 I915_WRITE(LCPLL_CTL, val);
8153 POSTING_READ(LCPLL_CTL);
8154
8155 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
8156 DRM_ERROR("LCPLL still locked\n");
8157
8158 val = hsw_read_dcomp(dev_priv);
8159 val |= D_COMP_COMP_DISABLE;
8160 hsw_write_dcomp(dev_priv, val);
8161 ndelay(100);
8162
8163 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8164 1))
8165 DRM_ERROR("D_COMP RCOMP still in progress\n");
8166
8167 if (allow_power_down) {
8168 val = I915_READ(LCPLL_CTL);
8169 val |= LCPLL_POWER_DOWN_ALLOW;
8170 I915_WRITE(LCPLL_CTL, val);
8171 POSTING_READ(LCPLL_CTL);
8172 }
8173 }
8174
8175 /*
8176 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8177 * source.
8178 */
8179 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8180 {
8181 uint32_t val;
8182
8183 val = I915_READ(LCPLL_CTL);
8184
8185 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8186 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8187 return;
8188
8189 /*
8190 * Make sure we're not on PC8 state before disabling PC8, otherwise
8191 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8192 */
8193 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8194
8195 if (val & LCPLL_POWER_DOWN_ALLOW) {
8196 val &= ~LCPLL_POWER_DOWN_ALLOW;
8197 I915_WRITE(LCPLL_CTL, val);
8198 POSTING_READ(LCPLL_CTL);
8199 }
8200
8201 val = hsw_read_dcomp(dev_priv);
8202 val |= D_COMP_COMP_FORCE;
8203 val &= ~D_COMP_COMP_DISABLE;
8204 hsw_write_dcomp(dev_priv, val);
8205
8206 val = I915_READ(LCPLL_CTL);
8207 val &= ~LCPLL_PLL_DISABLE;
8208 I915_WRITE(LCPLL_CTL, val);
8209
8210 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
8211 DRM_ERROR("LCPLL not locked yet\n");
8212
8213 if (val & LCPLL_CD_SOURCE_FCLK) {
8214 val = I915_READ(LCPLL_CTL);
8215 val &= ~LCPLL_CD_SOURCE_FCLK;
8216 I915_WRITE(LCPLL_CTL, val);
8217
8218 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
8219 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8220 DRM_ERROR("Switching back to LCPLL failed\n");
8221 }
8222
8223 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8224 }
8225
8226 /*
8227 * Package states C8 and deeper are really deep PC states that can only be
8228 * reached when all the devices on the system allow it, so even if the graphics
8229 * device allows PC8+, it doesn't mean the system will actually get to these
8230 * states. Our driver only allows PC8+ when going into runtime PM.
8231 *
8232 * The requirements for PC8+ are that all the outputs are disabled, the power
8233 * well is disabled and most interrupts are disabled, and these are also
8234 * requirements for runtime PM. When these conditions are met, we manually do
8235 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8236 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8237 * hang the machine.
8238 *
8239 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8240 * the state of some registers, so when we come back from PC8+ we need to
8241 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8242 * need to take care of the registers kept by RC6. Notice that this happens even
8243 * if we don't put the device in PCI D3 state (which is what currently happens
8244 * because of the runtime PM support).
8245 *
8246 * For more, read "Display Sequences for Package C8" on the hardware
8247 * documentation.
8248 */
8249 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8250 {
8251 struct drm_device *dev = dev_priv->dev;
8252 uint32_t val;
8253
8254 DRM_DEBUG_KMS("Enabling package C8+\n");
8255
8256 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8257 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8258 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8259 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8260 }
8261
8262 lpt_disable_clkout_dp(dev);
8263 hsw_disable_lcpll(dev_priv, true, true);
8264 }
8265
8266 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8267 {
8268 struct drm_device *dev = dev_priv->dev;
8269 uint32_t val;
8270
8271 DRM_DEBUG_KMS("Disabling package C8+\n");
8272
8273 hsw_restore_lcpll(dev_priv);
8274 lpt_init_pch_refclk(dev);
8275
8276 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8277 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8278 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8279 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8280 }
8281
8282 intel_prepare_ddi(dev);
8283 }
8284
8285 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8286 struct intel_crtc_state *crtc_state)
8287 {
8288 if (!intel_ddi_pll_select(crtc, crtc_state))
8289 return -EINVAL;
8290
8291 crtc->lowfreq_avail = false;
8292
8293 return 0;
8294 }
8295
8296 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8297 enum port port,
8298 struct intel_crtc_state *pipe_config)
8299 {
8300 u32 temp, dpll_ctl1;
8301
8302 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8303 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
8304
8305 switch (pipe_config->ddi_pll_sel) {
8306 case SKL_DPLL0:
8307 /*
8308 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
8309 * of the shared DPLL framework and thus needs to be read out
8310 * separately
8311 */
8312 dpll_ctl1 = I915_READ(DPLL_CTRL1);
8313 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
8314 break;
8315 case SKL_DPLL1:
8316 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
8317 break;
8318 case SKL_DPLL2:
8319 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
8320 break;
8321 case SKL_DPLL3:
8322 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8323 break;
8324 }
8325 }
8326
8327 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8328 enum port port,
8329 struct intel_crtc_state *pipe_config)
8330 {
8331 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8332
8333 switch (pipe_config->ddi_pll_sel) {
8334 case PORT_CLK_SEL_WRPLL1:
8335 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8336 break;
8337 case PORT_CLK_SEL_WRPLL2:
8338 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8339 break;
8340 }
8341 }
8342
8343 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
8344 struct intel_crtc_state *pipe_config)
8345 {
8346 struct drm_device *dev = crtc->base.dev;
8347 struct drm_i915_private *dev_priv = dev->dev_private;
8348 struct intel_shared_dpll *pll;
8349 enum port port;
8350 uint32_t tmp;
8351
8352 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8353
8354 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8355
8356 if (IS_SKYLAKE(dev))
8357 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8358 else
8359 haswell_get_ddi_pll(dev_priv, port, pipe_config);
8360
8361 if (pipe_config->shared_dpll >= 0) {
8362 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8363
8364 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8365 &pipe_config->dpll_hw_state));
8366 }
8367
8368 /*
8369 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8370 * DDI E. So just check whether this pipe is wired to DDI E and whether
8371 * the PCH transcoder is on.
8372 */
8373 if (INTEL_INFO(dev)->gen < 9 &&
8374 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8375 pipe_config->has_pch_encoder = true;
8376
8377 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8378 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8379 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8380
8381 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8382 }
8383 }
8384
8385 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8386 struct intel_crtc_state *pipe_config)
8387 {
8388 struct drm_device *dev = crtc->base.dev;
8389 struct drm_i915_private *dev_priv = dev->dev_private;
8390 enum intel_display_power_domain pfit_domain;
8391 uint32_t tmp;
8392
8393 if (!intel_display_power_is_enabled(dev_priv,
8394 POWER_DOMAIN_PIPE(crtc->pipe)))
8395 return false;
8396
8397 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8398 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8399
8400 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8401 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8402 enum pipe trans_edp_pipe;
8403 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8404 default:
8405 WARN(1, "unknown pipe linked to edp transcoder\n");
8406 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8407 case TRANS_DDI_EDP_INPUT_A_ON:
8408 trans_edp_pipe = PIPE_A;
8409 break;
8410 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8411 trans_edp_pipe = PIPE_B;
8412 break;
8413 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8414 trans_edp_pipe = PIPE_C;
8415 break;
8416 }
8417
8418 if (trans_edp_pipe == crtc->pipe)
8419 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8420 }
8421
8422 if (!intel_display_power_is_enabled(dev_priv,
8423 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8424 return false;
8425
8426 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8427 if (!(tmp & PIPECONF_ENABLE))
8428 return false;
8429
8430 haswell_get_ddi_port_state(crtc, pipe_config);
8431
8432 intel_get_pipe_timings(crtc, pipe_config);
8433
8434 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8435 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8436 if (IS_SKYLAKE(dev))
8437 skylake_get_pfit_config(crtc, pipe_config);
8438 else
8439 ironlake_get_pfit_config(crtc, pipe_config);
8440 }
8441
8442 if (IS_HASWELL(dev))
8443 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8444 (I915_READ(IPS_CTL) & IPS_ENABLE);
8445
8446 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8447 pipe_config->pixel_multiplier =
8448 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8449 } else {
8450 pipe_config->pixel_multiplier = 1;
8451 }
8452
8453 return true;
8454 }
8455
8456 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8457 {
8458 struct drm_device *dev = crtc->dev;
8459 struct drm_i915_private *dev_priv = dev->dev_private;
8460 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8461 uint32_t cntl = 0, size = 0;
8462
8463 if (base) {
8464 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
8465 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
8466 unsigned int stride = roundup_pow_of_two(width) * 4;
8467
8468 switch (stride) {
8469 default:
8470 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8471 width, stride);
8472 stride = 256;
8473 /* fallthrough */
8474 case 256:
8475 case 512:
8476 case 1024:
8477 case 2048:
8478 break;
8479 }
8480
8481 cntl |= CURSOR_ENABLE |
8482 CURSOR_GAMMA_ENABLE |
8483 CURSOR_FORMAT_ARGB |
8484 CURSOR_STRIDE(stride);
8485
8486 size = (height << 12) | width;
8487 }
8488
8489 if (intel_crtc->cursor_cntl != 0 &&
8490 (intel_crtc->cursor_base != base ||
8491 intel_crtc->cursor_size != size ||
8492 intel_crtc->cursor_cntl != cntl)) {
8493 /* On these chipsets we can only modify the base/size/stride
8494 * whilst the cursor is disabled.
8495 */
8496 I915_WRITE(_CURACNTR, 0);
8497 POSTING_READ(_CURACNTR);
8498 intel_crtc->cursor_cntl = 0;
8499 }
8500
8501 if (intel_crtc->cursor_base != base) {
8502 I915_WRITE(_CURABASE, base);
8503 intel_crtc->cursor_base = base;
8504 }
8505
8506 if (intel_crtc->cursor_size != size) {
8507 I915_WRITE(CURSIZE, size);
8508 intel_crtc->cursor_size = size;
8509 }
8510
8511 if (intel_crtc->cursor_cntl != cntl) {
8512 I915_WRITE(_CURACNTR, cntl);
8513 POSTING_READ(_CURACNTR);
8514 intel_crtc->cursor_cntl = cntl;
8515 }
8516 }
8517
8518 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8519 {
8520 struct drm_device *dev = crtc->dev;
8521 struct drm_i915_private *dev_priv = dev->dev_private;
8522 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8523 int pipe = intel_crtc->pipe;
8524 uint32_t cntl;
8525
8526 cntl = 0;
8527 if (base) {
8528 cntl = MCURSOR_GAMMA_ENABLE;
8529 switch (intel_crtc->base.cursor->state->crtc_w) {
8530 case 64:
8531 cntl |= CURSOR_MODE_64_ARGB_AX;
8532 break;
8533 case 128:
8534 cntl |= CURSOR_MODE_128_ARGB_AX;
8535 break;
8536 case 256:
8537 cntl |= CURSOR_MODE_256_ARGB_AX;
8538 break;
8539 default:
8540 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
8541 return;
8542 }
8543 cntl |= pipe << 28; /* Connect to correct pipe */
8544
8545 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8546 cntl |= CURSOR_PIPE_CSC_ENABLE;
8547 }
8548
8549 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
8550 cntl |= CURSOR_ROTATE_180;
8551
8552 if (intel_crtc->cursor_cntl != cntl) {
8553 I915_WRITE(CURCNTR(pipe), cntl);
8554 POSTING_READ(CURCNTR(pipe));
8555 intel_crtc->cursor_cntl = cntl;
8556 }
8557
8558 /* and commit changes on next vblank */
8559 I915_WRITE(CURBASE(pipe), base);
8560 POSTING_READ(CURBASE(pipe));
8561
8562 intel_crtc->cursor_base = base;
8563 }
8564
8565 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8566 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8567 bool on)
8568 {
8569 struct drm_device *dev = crtc->dev;
8570 struct drm_i915_private *dev_priv = dev->dev_private;
8571 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8572 int pipe = intel_crtc->pipe;
8573 int x = crtc->cursor_x;
8574 int y = crtc->cursor_y;
8575 u32 base = 0, pos = 0;
8576
8577 if (on)
8578 base = intel_crtc->cursor_addr;
8579
8580 if (x >= intel_crtc->config->pipe_src_w)
8581 base = 0;
8582
8583 if (y >= intel_crtc->config->pipe_src_h)
8584 base = 0;
8585
8586 if (x < 0) {
8587 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
8588 base = 0;
8589
8590 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8591 x = -x;
8592 }
8593 pos |= x << CURSOR_X_SHIFT;
8594
8595 if (y < 0) {
8596 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
8597 base = 0;
8598
8599 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8600 y = -y;
8601 }
8602 pos |= y << CURSOR_Y_SHIFT;
8603
8604 if (base == 0 && intel_crtc->cursor_base == 0)
8605 return;
8606
8607 I915_WRITE(CURPOS(pipe), pos);
8608
8609 /* ILK+ do this automagically */
8610 if (HAS_GMCH_DISPLAY(dev) &&
8611 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
8612 base += (intel_crtc->base.cursor->state->crtc_h *
8613 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
8614 }
8615
8616 if (IS_845G(dev) || IS_I865G(dev))
8617 i845_update_cursor(crtc, base);
8618 else
8619 i9xx_update_cursor(crtc, base);
8620 }
8621
8622 static bool cursor_size_ok(struct drm_device *dev,
8623 uint32_t width, uint32_t height)
8624 {
8625 if (width == 0 || height == 0)
8626 return false;
8627
8628 /*
8629 * 845g/865g are special in that they are only limited by
8630 * the width of their cursors, the height is arbitrary up to
8631 * the precision of the register. Everything else requires
8632 * square cursors, limited to a few power-of-two sizes.
8633 */
8634 if (IS_845G(dev) || IS_I865G(dev)) {
8635 if ((width & 63) != 0)
8636 return false;
8637
8638 if (width > (IS_845G(dev) ? 64 : 512))
8639 return false;
8640
8641 if (height > 1023)
8642 return false;
8643 } else {
8644 switch (width | height) {
8645 case 256:
8646 case 128:
8647 if (IS_GEN2(dev))
8648 return false;
8649 case 64:
8650 break;
8651 default:
8652 return false;
8653 }
8654 }
8655
8656 return true;
8657 }
8658
8659 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8660 u16 *blue, uint32_t start, uint32_t size)
8661 {
8662 int end = (start + size > 256) ? 256 : start + size, i;
8663 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8664
8665 for (i = start; i < end; i++) {
8666 intel_crtc->lut_r[i] = red[i] >> 8;
8667 intel_crtc->lut_g[i] = green[i] >> 8;
8668 intel_crtc->lut_b[i] = blue[i] >> 8;
8669 }
8670
8671 intel_crtc_load_lut(crtc);
8672 }
8673
8674 /* VESA 640x480x72Hz mode to set on the pipe */
8675 static struct drm_display_mode load_detect_mode = {
8676 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8677 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8678 };
8679
8680 struct drm_framebuffer *
8681 __intel_framebuffer_create(struct drm_device *dev,
8682 struct drm_mode_fb_cmd2 *mode_cmd,
8683 struct drm_i915_gem_object *obj)
8684 {
8685 struct intel_framebuffer *intel_fb;
8686 int ret;
8687
8688 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8689 if (!intel_fb) {
8690 drm_gem_object_unreference(&obj->base);
8691 return ERR_PTR(-ENOMEM);
8692 }
8693
8694 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8695 if (ret)
8696 goto err;
8697
8698 return &intel_fb->base;
8699 err:
8700 drm_gem_object_unreference(&obj->base);
8701 kfree(intel_fb);
8702
8703 return ERR_PTR(ret);
8704 }
8705
8706 static struct drm_framebuffer *
8707 intel_framebuffer_create(struct drm_device *dev,
8708 struct drm_mode_fb_cmd2 *mode_cmd,
8709 struct drm_i915_gem_object *obj)
8710 {
8711 struct drm_framebuffer *fb;
8712 int ret;
8713
8714 ret = i915_mutex_lock_interruptible(dev);
8715 if (ret)
8716 return ERR_PTR(ret);
8717 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8718 mutex_unlock(&dev->struct_mutex);
8719
8720 return fb;
8721 }
8722
8723 static u32
8724 intel_framebuffer_pitch_for_width(int width, int bpp)
8725 {
8726 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8727 return ALIGN(pitch, 64);
8728 }
8729
8730 static u32
8731 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8732 {
8733 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8734 return PAGE_ALIGN(pitch * mode->vdisplay);
8735 }
8736
8737 static struct drm_framebuffer *
8738 intel_framebuffer_create_for_mode(struct drm_device *dev,
8739 struct drm_display_mode *mode,
8740 int depth, int bpp)
8741 {
8742 struct drm_i915_gem_object *obj;
8743 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8744
8745 obj = i915_gem_alloc_object(dev,
8746 intel_framebuffer_size_for_mode(mode, bpp));
8747 if (obj == NULL)
8748 return ERR_PTR(-ENOMEM);
8749
8750 mode_cmd.width = mode->hdisplay;
8751 mode_cmd.height = mode->vdisplay;
8752 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8753 bpp);
8754 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8755
8756 return intel_framebuffer_create(dev, &mode_cmd, obj);
8757 }
8758
8759 static struct drm_framebuffer *
8760 mode_fits_in_fbdev(struct drm_device *dev,
8761 struct drm_display_mode *mode)
8762 {
8763 #ifdef CONFIG_DRM_I915_FBDEV
8764 struct drm_i915_private *dev_priv = dev->dev_private;
8765 struct drm_i915_gem_object *obj;
8766 struct drm_framebuffer *fb;
8767
8768 if (!dev_priv->fbdev)
8769 return NULL;
8770
8771 if (!dev_priv->fbdev->fb)
8772 return NULL;
8773
8774 obj = dev_priv->fbdev->fb->obj;
8775 BUG_ON(!obj);
8776
8777 fb = &dev_priv->fbdev->fb->base;
8778 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8779 fb->bits_per_pixel))
8780 return NULL;
8781
8782 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8783 return NULL;
8784
8785 return fb;
8786 #else
8787 return NULL;
8788 #endif
8789 }
8790
8791 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8792 struct drm_display_mode *mode,
8793 struct intel_load_detect_pipe *old,
8794 struct drm_modeset_acquire_ctx *ctx)
8795 {
8796 struct intel_crtc *intel_crtc;
8797 struct intel_encoder *intel_encoder =
8798 intel_attached_encoder(connector);
8799 struct drm_crtc *possible_crtc;
8800 struct drm_encoder *encoder = &intel_encoder->base;
8801 struct drm_crtc *crtc = NULL;
8802 struct drm_device *dev = encoder->dev;
8803 struct drm_framebuffer *fb;
8804 struct drm_mode_config *config = &dev->mode_config;
8805 int ret, i = -1;
8806
8807 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8808 connector->base.id, connector->name,
8809 encoder->base.id, encoder->name);
8810
8811 retry:
8812 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8813 if (ret)
8814 goto fail_unlock;
8815
8816 /*
8817 * Algorithm gets a little messy:
8818 *
8819 * - if the connector already has an assigned crtc, use it (but make
8820 * sure it's on first)
8821 *
8822 * - try to find the first unused crtc that can drive this connector,
8823 * and use that if we find one
8824 */
8825
8826 /* See if we already have a CRTC for this connector */
8827 if (encoder->crtc) {
8828 crtc = encoder->crtc;
8829
8830 ret = drm_modeset_lock(&crtc->mutex, ctx);
8831 if (ret)
8832 goto fail_unlock;
8833 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8834 if (ret)
8835 goto fail_unlock;
8836
8837 old->dpms_mode = connector->dpms;
8838 old->load_detect_temp = false;
8839
8840 /* Make sure the crtc and connector are running */
8841 if (connector->dpms != DRM_MODE_DPMS_ON)
8842 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8843
8844 return true;
8845 }
8846
8847 /* Find an unused one (if possible) */
8848 for_each_crtc(dev, possible_crtc) {
8849 i++;
8850 if (!(encoder->possible_crtcs & (1 << i)))
8851 continue;
8852 if (possible_crtc->state->enable)
8853 continue;
8854 /* This can occur when applying the pipe A quirk on resume. */
8855 if (to_intel_crtc(possible_crtc)->new_enabled)
8856 continue;
8857
8858 crtc = possible_crtc;
8859 break;
8860 }
8861
8862 /*
8863 * If we didn't find an unused CRTC, don't use any.
8864 */
8865 if (!crtc) {
8866 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8867 goto fail_unlock;
8868 }
8869
8870 ret = drm_modeset_lock(&crtc->mutex, ctx);
8871 if (ret)
8872 goto fail_unlock;
8873 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8874 if (ret)
8875 goto fail_unlock;
8876 intel_encoder->new_crtc = to_intel_crtc(crtc);
8877 to_intel_connector(connector)->new_encoder = intel_encoder;
8878
8879 intel_crtc = to_intel_crtc(crtc);
8880 intel_crtc->new_enabled = true;
8881 intel_crtc->new_config = intel_crtc->config;
8882 old->dpms_mode = connector->dpms;
8883 old->load_detect_temp = true;
8884 old->release_fb = NULL;
8885
8886 if (!mode)
8887 mode = &load_detect_mode;
8888
8889 /* We need a framebuffer large enough to accommodate all accesses
8890 * that the plane may generate whilst we perform load detection.
8891 * We can not rely on the fbcon either being present (we get called
8892 * during its initialisation to detect all boot displays, or it may
8893 * not even exist) or that it is large enough to satisfy the
8894 * requested mode.
8895 */
8896 fb = mode_fits_in_fbdev(dev, mode);
8897 if (fb == NULL) {
8898 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8899 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8900 old->release_fb = fb;
8901 } else
8902 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8903 if (IS_ERR(fb)) {
8904 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8905 goto fail;
8906 }
8907
8908 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8909 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8910 if (old->release_fb)
8911 old->release_fb->funcs->destroy(old->release_fb);
8912 goto fail;
8913 }
8914 crtc->primary->crtc = crtc;
8915
8916 /* let the connector get through one full cycle before testing */
8917 intel_wait_for_vblank(dev, intel_crtc->pipe);
8918 return true;
8919
8920 fail:
8921 intel_crtc->new_enabled = crtc->state->enable;
8922 if (intel_crtc->new_enabled)
8923 intel_crtc->new_config = intel_crtc->config;
8924 else
8925 intel_crtc->new_config = NULL;
8926 fail_unlock:
8927 if (ret == -EDEADLK) {
8928 drm_modeset_backoff(ctx);
8929 goto retry;
8930 }
8931
8932 return false;
8933 }
8934
8935 void intel_release_load_detect_pipe(struct drm_connector *connector,
8936 struct intel_load_detect_pipe *old)
8937 {
8938 struct intel_encoder *intel_encoder =
8939 intel_attached_encoder(connector);
8940 struct drm_encoder *encoder = &intel_encoder->base;
8941 struct drm_crtc *crtc = encoder->crtc;
8942 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8943
8944 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8945 connector->base.id, connector->name,
8946 encoder->base.id, encoder->name);
8947
8948 if (old->load_detect_temp) {
8949 to_intel_connector(connector)->new_encoder = NULL;
8950 intel_encoder->new_crtc = NULL;
8951 intel_crtc->new_enabled = false;
8952 intel_crtc->new_config = NULL;
8953 intel_set_mode(crtc, NULL, 0, 0, NULL);
8954
8955 if (old->release_fb) {
8956 drm_framebuffer_unregister_private(old->release_fb);
8957 drm_framebuffer_unreference(old->release_fb);
8958 }
8959
8960 return;
8961 }
8962
8963 /* Switch crtc and encoder back off if necessary */
8964 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8965 connector->funcs->dpms(connector, old->dpms_mode);
8966 }
8967
8968 static int i9xx_pll_refclk(struct drm_device *dev,
8969 const struct intel_crtc_state *pipe_config)
8970 {
8971 struct drm_i915_private *dev_priv = dev->dev_private;
8972 u32 dpll = pipe_config->dpll_hw_state.dpll;
8973
8974 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8975 return dev_priv->vbt.lvds_ssc_freq;
8976 else if (HAS_PCH_SPLIT(dev))
8977 return 120000;
8978 else if (!IS_GEN2(dev))
8979 return 96000;
8980 else
8981 return 48000;
8982 }
8983
8984 /* Returns the clock of the currently programmed mode of the given pipe. */
8985 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8986 struct intel_crtc_state *pipe_config)
8987 {
8988 struct drm_device *dev = crtc->base.dev;
8989 struct drm_i915_private *dev_priv = dev->dev_private;
8990 int pipe = pipe_config->cpu_transcoder;
8991 u32 dpll = pipe_config->dpll_hw_state.dpll;
8992 u32 fp;
8993 intel_clock_t clock;
8994 int refclk = i9xx_pll_refclk(dev, pipe_config);
8995
8996 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8997 fp = pipe_config->dpll_hw_state.fp0;
8998 else
8999 fp = pipe_config->dpll_hw_state.fp1;
9000
9001 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
9002 if (IS_PINEVIEW(dev)) {
9003 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9004 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
9005 } else {
9006 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9007 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9008 }
9009
9010 if (!IS_GEN2(dev)) {
9011 if (IS_PINEVIEW(dev))
9012 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9013 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
9014 else
9015 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
9016 DPLL_FPA01_P1_POST_DIV_SHIFT);
9017
9018 switch (dpll & DPLL_MODE_MASK) {
9019 case DPLLB_MODE_DAC_SERIAL:
9020 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9021 5 : 10;
9022 break;
9023 case DPLLB_MODE_LVDS:
9024 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9025 7 : 14;
9026 break;
9027 default:
9028 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
9029 "mode\n", (int)(dpll & DPLL_MODE_MASK));
9030 return;
9031 }
9032
9033 if (IS_PINEVIEW(dev))
9034 pineview_clock(refclk, &clock);
9035 else
9036 i9xx_clock(refclk, &clock);
9037 } else {
9038 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
9039 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
9040
9041 if (is_lvds) {
9042 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9043 DPLL_FPA01_P1_POST_DIV_SHIFT);
9044
9045 if (lvds & LVDS_CLKB_POWER_UP)
9046 clock.p2 = 7;
9047 else
9048 clock.p2 = 14;
9049 } else {
9050 if (dpll & PLL_P1_DIVIDE_BY_TWO)
9051 clock.p1 = 2;
9052 else {
9053 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9054 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9055 }
9056 if (dpll & PLL_P2_DIVIDE_BY_4)
9057 clock.p2 = 4;
9058 else
9059 clock.p2 = 2;
9060 }
9061
9062 i9xx_clock(refclk, &clock);
9063 }
9064
9065 /*
9066 * This value includes pixel_multiplier. We will use
9067 * port_clock to compute adjusted_mode.crtc_clock in the
9068 * encoder's get_config() function.
9069 */
9070 pipe_config->port_clock = clock.dot;
9071 }
9072
9073 int intel_dotclock_calculate(int link_freq,
9074 const struct intel_link_m_n *m_n)
9075 {
9076 /*
9077 * The calculation for the data clock is:
9078 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
9079 * But we want to avoid losing precison if possible, so:
9080 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
9081 *
9082 * and the link clock is simpler:
9083 * link_clock = (m * link_clock) / n
9084 */
9085
9086 if (!m_n->link_n)
9087 return 0;
9088
9089 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
9090 }
9091
9092 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
9093 struct intel_crtc_state *pipe_config)
9094 {
9095 struct drm_device *dev = crtc->base.dev;
9096
9097 /* read out port_clock from the DPLL */
9098 i9xx_crtc_clock_get(crtc, pipe_config);
9099
9100 /*
9101 * This value does not include pixel_multiplier.
9102 * We will check that port_clock and adjusted_mode.crtc_clock
9103 * agree once we know their relationship in the encoder's
9104 * get_config() function.
9105 */
9106 pipe_config->base.adjusted_mode.crtc_clock =
9107 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
9108 &pipe_config->fdi_m_n);
9109 }
9110
9111 /** Returns the currently programmed mode of the given pipe. */
9112 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9113 struct drm_crtc *crtc)
9114 {
9115 struct drm_i915_private *dev_priv = dev->dev_private;
9116 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9117 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9118 struct drm_display_mode *mode;
9119 struct intel_crtc_state pipe_config;
9120 int htot = I915_READ(HTOTAL(cpu_transcoder));
9121 int hsync = I915_READ(HSYNC(cpu_transcoder));
9122 int vtot = I915_READ(VTOTAL(cpu_transcoder));
9123 int vsync = I915_READ(VSYNC(cpu_transcoder));
9124 enum pipe pipe = intel_crtc->pipe;
9125
9126 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9127 if (!mode)
9128 return NULL;
9129
9130 /*
9131 * Construct a pipe_config sufficient for getting the clock info
9132 * back out of crtc_clock_get.
9133 *
9134 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9135 * to use a real value here instead.
9136 */
9137 pipe_config.cpu_transcoder = (enum transcoder) pipe;
9138 pipe_config.pixel_multiplier = 1;
9139 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9140 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9141 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
9142 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
9143
9144 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
9145 mode->hdisplay = (htot & 0xffff) + 1;
9146 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9147 mode->hsync_start = (hsync & 0xffff) + 1;
9148 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9149 mode->vdisplay = (vtot & 0xffff) + 1;
9150 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9151 mode->vsync_start = (vsync & 0xffff) + 1;
9152 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9153
9154 drm_mode_set_name(mode);
9155
9156 return mode;
9157 }
9158
9159 static void intel_decrease_pllclock(struct drm_crtc *crtc)
9160 {
9161 struct drm_device *dev = crtc->dev;
9162 struct drm_i915_private *dev_priv = dev->dev_private;
9163 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9164
9165 if (!HAS_GMCH_DISPLAY(dev))
9166 return;
9167
9168 if (!dev_priv->lvds_downclock_avail)
9169 return;
9170
9171 /*
9172 * Since this is called by a timer, we should never get here in
9173 * the manual case.
9174 */
9175 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
9176 int pipe = intel_crtc->pipe;
9177 int dpll_reg = DPLL(pipe);
9178 int dpll;
9179
9180 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9181
9182 assert_panel_unlocked(dev_priv, pipe);
9183
9184 dpll = I915_READ(dpll_reg);
9185 dpll |= DISPLAY_RATE_SELECT_FPA1;
9186 I915_WRITE(dpll_reg, dpll);
9187 intel_wait_for_vblank(dev, pipe);
9188 dpll = I915_READ(dpll_reg);
9189 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
9190 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9191 }
9192
9193 }
9194
9195 void intel_mark_busy(struct drm_device *dev)
9196 {
9197 struct drm_i915_private *dev_priv = dev->dev_private;
9198
9199 if (dev_priv->mm.busy)
9200 return;
9201
9202 intel_runtime_pm_get(dev_priv);
9203 i915_update_gfx_val(dev_priv);
9204 dev_priv->mm.busy = true;
9205 }
9206
9207 void intel_mark_idle(struct drm_device *dev)
9208 {
9209 struct drm_i915_private *dev_priv = dev->dev_private;
9210 struct drm_crtc *crtc;
9211
9212 if (!dev_priv->mm.busy)
9213 return;
9214
9215 dev_priv->mm.busy = false;
9216
9217 if (!i915.powersave)
9218 goto out;
9219
9220 for_each_crtc(dev, crtc) {
9221 if (!crtc->primary->fb)
9222 continue;
9223
9224 intel_decrease_pllclock(crtc);
9225 }
9226
9227 if (INTEL_INFO(dev)->gen >= 6)
9228 gen6_rps_idle(dev->dev_private);
9229
9230 out:
9231 intel_runtime_pm_put(dev_priv);
9232 }
9233
9234 static void intel_crtc_set_state(struct intel_crtc *crtc,
9235 struct intel_crtc_state *crtc_state)
9236 {
9237 kfree(crtc->config);
9238 crtc->config = crtc_state;
9239 crtc->base.state = &crtc_state->base;
9240 }
9241
9242 static void intel_crtc_destroy(struct drm_crtc *crtc)
9243 {
9244 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9245 struct drm_device *dev = crtc->dev;
9246 struct intel_unpin_work *work;
9247
9248 spin_lock_irq(&dev->event_lock);
9249 work = intel_crtc->unpin_work;
9250 intel_crtc->unpin_work = NULL;
9251 spin_unlock_irq(&dev->event_lock);
9252
9253 if (work) {
9254 cancel_work_sync(&work->work);
9255 kfree(work);
9256 }
9257
9258 intel_crtc_set_state(intel_crtc, NULL);
9259 drm_crtc_cleanup(crtc);
9260
9261 kfree(intel_crtc);
9262 }
9263
9264 static void intel_unpin_work_fn(struct work_struct *__work)
9265 {
9266 struct intel_unpin_work *work =
9267 container_of(__work, struct intel_unpin_work, work);
9268 struct drm_device *dev = work->crtc->dev;
9269 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9270
9271 mutex_lock(&dev->struct_mutex);
9272 intel_unpin_fb_obj(intel_fb_obj(work->old_fb));
9273 drm_gem_object_unreference(&work->pending_flip_obj->base);
9274
9275 intel_fbc_update(dev);
9276
9277 if (work->flip_queued_req)
9278 i915_gem_request_assign(&work->flip_queued_req, NULL);
9279 mutex_unlock(&dev->struct_mutex);
9280
9281 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9282 drm_framebuffer_unreference(work->old_fb);
9283
9284 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9285 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9286
9287 kfree(work);
9288 }
9289
9290 static void do_intel_finish_page_flip(struct drm_device *dev,
9291 struct drm_crtc *crtc)
9292 {
9293 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9294 struct intel_unpin_work *work;
9295 unsigned long flags;
9296
9297 /* Ignore early vblank irqs */
9298 if (intel_crtc == NULL)
9299 return;
9300
9301 /*
9302 * This is called both by irq handlers and the reset code (to complete
9303 * lost pageflips) so needs the full irqsave spinlocks.
9304 */
9305 spin_lock_irqsave(&dev->event_lock, flags);
9306 work = intel_crtc->unpin_work;
9307
9308 /* Ensure we don't miss a work->pending update ... */
9309 smp_rmb();
9310
9311 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9312 spin_unlock_irqrestore(&dev->event_lock, flags);
9313 return;
9314 }
9315
9316 page_flip_completed(intel_crtc);
9317
9318 spin_unlock_irqrestore(&dev->event_lock, flags);
9319 }
9320
9321 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9322 {
9323 struct drm_i915_private *dev_priv = dev->dev_private;
9324 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9325
9326 do_intel_finish_page_flip(dev, crtc);
9327 }
9328
9329 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9330 {
9331 struct drm_i915_private *dev_priv = dev->dev_private;
9332 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9333
9334 do_intel_finish_page_flip(dev, crtc);
9335 }
9336
9337 /* Is 'a' after or equal to 'b'? */
9338 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9339 {
9340 return !((a - b) & 0x80000000);
9341 }
9342
9343 static bool page_flip_finished(struct intel_crtc *crtc)
9344 {
9345 struct drm_device *dev = crtc->base.dev;
9346 struct drm_i915_private *dev_priv = dev->dev_private;
9347
9348 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
9349 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
9350 return true;
9351
9352 /*
9353 * The relevant registers doen't exist on pre-ctg.
9354 * As the flip done interrupt doesn't trigger for mmio
9355 * flips on gmch platforms, a flip count check isn't
9356 * really needed there. But since ctg has the registers,
9357 * include it in the check anyway.
9358 */
9359 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9360 return true;
9361
9362 /*
9363 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9364 * used the same base address. In that case the mmio flip might
9365 * have completed, but the CS hasn't even executed the flip yet.
9366 *
9367 * A flip count check isn't enough as the CS might have updated
9368 * the base address just after start of vblank, but before we
9369 * managed to process the interrupt. This means we'd complete the
9370 * CS flip too soon.
9371 *
9372 * Combining both checks should get us a good enough result. It may
9373 * still happen that the CS flip has been executed, but has not
9374 * yet actually completed. But in case the base address is the same
9375 * anyway, we don't really care.
9376 */
9377 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9378 crtc->unpin_work->gtt_offset &&
9379 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9380 crtc->unpin_work->flip_count);
9381 }
9382
9383 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9384 {
9385 struct drm_i915_private *dev_priv = dev->dev_private;
9386 struct intel_crtc *intel_crtc =
9387 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9388 unsigned long flags;
9389
9390
9391 /*
9392 * This is called both by irq handlers and the reset code (to complete
9393 * lost pageflips) so needs the full irqsave spinlocks.
9394 *
9395 * NB: An MMIO update of the plane base pointer will also
9396 * generate a page-flip completion irq, i.e. every modeset
9397 * is also accompanied by a spurious intel_prepare_page_flip().
9398 */
9399 spin_lock_irqsave(&dev->event_lock, flags);
9400 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9401 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9402 spin_unlock_irqrestore(&dev->event_lock, flags);
9403 }
9404
9405 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9406 {
9407 /* Ensure that the work item is consistent when activating it ... */
9408 smp_wmb();
9409 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9410 /* and that it is marked active as soon as the irq could fire. */
9411 smp_wmb();
9412 }
9413
9414 static int intel_gen2_queue_flip(struct drm_device *dev,
9415 struct drm_crtc *crtc,
9416 struct drm_framebuffer *fb,
9417 struct drm_i915_gem_object *obj,
9418 struct intel_engine_cs *ring,
9419 uint32_t flags)
9420 {
9421 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9422 u32 flip_mask;
9423 int ret;
9424
9425 ret = intel_ring_begin(ring, 6);
9426 if (ret)
9427 return ret;
9428
9429 /* Can't queue multiple flips, so wait for the previous
9430 * one to finish before executing the next.
9431 */
9432 if (intel_crtc->plane)
9433 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9434 else
9435 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9436 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9437 intel_ring_emit(ring, MI_NOOP);
9438 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9439 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9440 intel_ring_emit(ring, fb->pitches[0]);
9441 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9442 intel_ring_emit(ring, 0); /* aux display base address, unused */
9443
9444 intel_mark_page_flip_active(intel_crtc);
9445 __intel_ring_advance(ring);
9446 return 0;
9447 }
9448
9449 static int intel_gen3_queue_flip(struct drm_device *dev,
9450 struct drm_crtc *crtc,
9451 struct drm_framebuffer *fb,
9452 struct drm_i915_gem_object *obj,
9453 struct intel_engine_cs *ring,
9454 uint32_t flags)
9455 {
9456 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9457 u32 flip_mask;
9458 int ret;
9459
9460 ret = intel_ring_begin(ring, 6);
9461 if (ret)
9462 return ret;
9463
9464 if (intel_crtc->plane)
9465 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9466 else
9467 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9468 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9469 intel_ring_emit(ring, MI_NOOP);
9470 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9471 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9472 intel_ring_emit(ring, fb->pitches[0]);
9473 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9474 intel_ring_emit(ring, MI_NOOP);
9475
9476 intel_mark_page_flip_active(intel_crtc);
9477 __intel_ring_advance(ring);
9478 return 0;
9479 }
9480
9481 static int intel_gen4_queue_flip(struct drm_device *dev,
9482 struct drm_crtc *crtc,
9483 struct drm_framebuffer *fb,
9484 struct drm_i915_gem_object *obj,
9485 struct intel_engine_cs *ring,
9486 uint32_t flags)
9487 {
9488 struct drm_i915_private *dev_priv = dev->dev_private;
9489 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9490 uint32_t pf, pipesrc;
9491 int ret;
9492
9493 ret = intel_ring_begin(ring, 4);
9494 if (ret)
9495 return ret;
9496
9497 /* i965+ uses the linear or tiled offsets from the
9498 * Display Registers (which do not change across a page-flip)
9499 * so we need only reprogram the base address.
9500 */
9501 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9502 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9503 intel_ring_emit(ring, fb->pitches[0]);
9504 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9505 obj->tiling_mode);
9506
9507 /* XXX Enabling the panel-fitter across page-flip is so far
9508 * untested on non-native modes, so ignore it for now.
9509 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9510 */
9511 pf = 0;
9512 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9513 intel_ring_emit(ring, pf | pipesrc);
9514
9515 intel_mark_page_flip_active(intel_crtc);
9516 __intel_ring_advance(ring);
9517 return 0;
9518 }
9519
9520 static int intel_gen6_queue_flip(struct drm_device *dev,
9521 struct drm_crtc *crtc,
9522 struct drm_framebuffer *fb,
9523 struct drm_i915_gem_object *obj,
9524 struct intel_engine_cs *ring,
9525 uint32_t flags)
9526 {
9527 struct drm_i915_private *dev_priv = dev->dev_private;
9528 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9529 uint32_t pf, pipesrc;
9530 int ret;
9531
9532 ret = intel_ring_begin(ring, 4);
9533 if (ret)
9534 return ret;
9535
9536 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9537 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9538 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9539 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9540
9541 /* Contrary to the suggestions in the documentation,
9542 * "Enable Panel Fitter" does not seem to be required when page
9543 * flipping with a non-native mode, and worse causes a normal
9544 * modeset to fail.
9545 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9546 */
9547 pf = 0;
9548 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9549 intel_ring_emit(ring, pf | pipesrc);
9550
9551 intel_mark_page_flip_active(intel_crtc);
9552 __intel_ring_advance(ring);
9553 return 0;
9554 }
9555
9556 static int intel_gen7_queue_flip(struct drm_device *dev,
9557 struct drm_crtc *crtc,
9558 struct drm_framebuffer *fb,
9559 struct drm_i915_gem_object *obj,
9560 struct intel_engine_cs *ring,
9561 uint32_t flags)
9562 {
9563 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9564 uint32_t plane_bit = 0;
9565 int len, ret;
9566
9567 switch (intel_crtc->plane) {
9568 case PLANE_A:
9569 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9570 break;
9571 case PLANE_B:
9572 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9573 break;
9574 case PLANE_C:
9575 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9576 break;
9577 default:
9578 WARN_ONCE(1, "unknown plane in flip command\n");
9579 return -ENODEV;
9580 }
9581
9582 len = 4;
9583 if (ring->id == RCS) {
9584 len += 6;
9585 /*
9586 * On Gen 8, SRM is now taking an extra dword to accommodate
9587 * 48bits addresses, and we need a NOOP for the batch size to
9588 * stay even.
9589 */
9590 if (IS_GEN8(dev))
9591 len += 2;
9592 }
9593
9594 /*
9595 * BSpec MI_DISPLAY_FLIP for IVB:
9596 * "The full packet must be contained within the same cache line."
9597 *
9598 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9599 * cacheline, if we ever start emitting more commands before
9600 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9601 * then do the cacheline alignment, and finally emit the
9602 * MI_DISPLAY_FLIP.
9603 */
9604 ret = intel_ring_cacheline_align(ring);
9605 if (ret)
9606 return ret;
9607
9608 ret = intel_ring_begin(ring, len);
9609 if (ret)
9610 return ret;
9611
9612 /* Unmask the flip-done completion message. Note that the bspec says that
9613 * we should do this for both the BCS and RCS, and that we must not unmask
9614 * more than one flip event at any time (or ensure that one flip message
9615 * can be sent by waiting for flip-done prior to queueing new flips).
9616 * Experimentation says that BCS works despite DERRMR masking all
9617 * flip-done completion events and that unmasking all planes at once
9618 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9619 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9620 */
9621 if (ring->id == RCS) {
9622 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9623 intel_ring_emit(ring, DERRMR);
9624 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9625 DERRMR_PIPEB_PRI_FLIP_DONE |
9626 DERRMR_PIPEC_PRI_FLIP_DONE));
9627 if (IS_GEN8(dev))
9628 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9629 MI_SRM_LRM_GLOBAL_GTT);
9630 else
9631 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9632 MI_SRM_LRM_GLOBAL_GTT);
9633 intel_ring_emit(ring, DERRMR);
9634 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9635 if (IS_GEN8(dev)) {
9636 intel_ring_emit(ring, 0);
9637 intel_ring_emit(ring, MI_NOOP);
9638 }
9639 }
9640
9641 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9642 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9643 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9644 intel_ring_emit(ring, (MI_NOOP));
9645
9646 intel_mark_page_flip_active(intel_crtc);
9647 __intel_ring_advance(ring);
9648 return 0;
9649 }
9650
9651 static bool use_mmio_flip(struct intel_engine_cs *ring,
9652 struct drm_i915_gem_object *obj)
9653 {
9654 /*
9655 * This is not being used for older platforms, because
9656 * non-availability of flip done interrupt forces us to use
9657 * CS flips. Older platforms derive flip done using some clever
9658 * tricks involving the flip_pending status bits and vblank irqs.
9659 * So using MMIO flips there would disrupt this mechanism.
9660 */
9661
9662 if (ring == NULL)
9663 return true;
9664
9665 if (INTEL_INFO(ring->dev)->gen < 5)
9666 return false;
9667
9668 if (i915.use_mmio_flip < 0)
9669 return false;
9670 else if (i915.use_mmio_flip > 0)
9671 return true;
9672 else if (i915.enable_execlists)
9673 return true;
9674 else
9675 return ring != i915_gem_request_get_ring(obj->last_read_req);
9676 }
9677
9678 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
9679 {
9680 struct drm_device *dev = intel_crtc->base.dev;
9681 struct drm_i915_private *dev_priv = dev->dev_private;
9682 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
9683 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9684 struct drm_i915_gem_object *obj = intel_fb->obj;
9685 const enum pipe pipe = intel_crtc->pipe;
9686 u32 ctl, stride;
9687
9688 ctl = I915_READ(PLANE_CTL(pipe, 0));
9689 ctl &= ~PLANE_CTL_TILED_MASK;
9690 if (obj->tiling_mode == I915_TILING_X)
9691 ctl |= PLANE_CTL_TILED_X;
9692
9693 /*
9694 * The stride is either expressed as a multiple of 64 bytes chunks for
9695 * linear buffers or in number of tiles for tiled buffers.
9696 */
9697 stride = fb->pitches[0] >> 6;
9698 if (obj->tiling_mode == I915_TILING_X)
9699 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
9700
9701 /*
9702 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
9703 * PLANE_SURF updates, the update is then guaranteed to be atomic.
9704 */
9705 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
9706 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
9707
9708 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
9709 POSTING_READ(PLANE_SURF(pipe, 0));
9710 }
9711
9712 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
9713 {
9714 struct drm_device *dev = intel_crtc->base.dev;
9715 struct drm_i915_private *dev_priv = dev->dev_private;
9716 struct intel_framebuffer *intel_fb =
9717 to_intel_framebuffer(intel_crtc->base.primary->fb);
9718 struct drm_i915_gem_object *obj = intel_fb->obj;
9719 u32 dspcntr;
9720 u32 reg;
9721
9722 reg = DSPCNTR(intel_crtc->plane);
9723 dspcntr = I915_READ(reg);
9724
9725 if (obj->tiling_mode != I915_TILING_NONE)
9726 dspcntr |= DISPPLANE_TILED;
9727 else
9728 dspcntr &= ~DISPPLANE_TILED;
9729
9730 I915_WRITE(reg, dspcntr);
9731
9732 I915_WRITE(DSPSURF(intel_crtc->plane),
9733 intel_crtc->unpin_work->gtt_offset);
9734 POSTING_READ(DSPSURF(intel_crtc->plane));
9735
9736 }
9737
9738 /*
9739 * XXX: This is the temporary way to update the plane registers until we get
9740 * around to using the usual plane update functions for MMIO flips
9741 */
9742 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9743 {
9744 struct drm_device *dev = intel_crtc->base.dev;
9745 bool atomic_update;
9746 u32 start_vbl_count;
9747
9748 intel_mark_page_flip_active(intel_crtc);
9749
9750 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9751
9752 if (INTEL_INFO(dev)->gen >= 9)
9753 skl_do_mmio_flip(intel_crtc);
9754 else
9755 /* use_mmio_flip() retricts MMIO flips to ilk+ */
9756 ilk_do_mmio_flip(intel_crtc);
9757
9758 if (atomic_update)
9759 intel_pipe_update_end(intel_crtc, start_vbl_count);
9760 }
9761
9762 static void intel_mmio_flip_work_func(struct work_struct *work)
9763 {
9764 struct intel_crtc *crtc =
9765 container_of(work, struct intel_crtc, mmio_flip.work);
9766 struct intel_mmio_flip *mmio_flip;
9767
9768 mmio_flip = &crtc->mmio_flip;
9769 if (mmio_flip->req)
9770 WARN_ON(__i915_wait_request(mmio_flip->req,
9771 crtc->reset_counter,
9772 false, NULL, NULL) != 0);
9773
9774 intel_do_mmio_flip(crtc);
9775 if (mmio_flip->req) {
9776 mutex_lock(&crtc->base.dev->struct_mutex);
9777 i915_gem_request_assign(&mmio_flip->req, NULL);
9778 mutex_unlock(&crtc->base.dev->struct_mutex);
9779 }
9780 }
9781
9782 static int intel_queue_mmio_flip(struct drm_device *dev,
9783 struct drm_crtc *crtc,
9784 struct drm_framebuffer *fb,
9785 struct drm_i915_gem_object *obj,
9786 struct intel_engine_cs *ring,
9787 uint32_t flags)
9788 {
9789 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9790
9791 i915_gem_request_assign(&intel_crtc->mmio_flip.req,
9792 obj->last_write_req);
9793
9794 schedule_work(&intel_crtc->mmio_flip.work);
9795
9796 return 0;
9797 }
9798
9799 static int intel_default_queue_flip(struct drm_device *dev,
9800 struct drm_crtc *crtc,
9801 struct drm_framebuffer *fb,
9802 struct drm_i915_gem_object *obj,
9803 struct intel_engine_cs *ring,
9804 uint32_t flags)
9805 {
9806 return -ENODEV;
9807 }
9808
9809 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9810 struct drm_crtc *crtc)
9811 {
9812 struct drm_i915_private *dev_priv = dev->dev_private;
9813 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9814 struct intel_unpin_work *work = intel_crtc->unpin_work;
9815 u32 addr;
9816
9817 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9818 return true;
9819
9820 if (!work->enable_stall_check)
9821 return false;
9822
9823 if (work->flip_ready_vblank == 0) {
9824 if (work->flip_queued_req &&
9825 !i915_gem_request_completed(work->flip_queued_req, true))
9826 return false;
9827
9828 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
9829 }
9830
9831 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
9832 return false;
9833
9834 /* Potential stall - if we see that the flip has happened,
9835 * assume a missed interrupt. */
9836 if (INTEL_INFO(dev)->gen >= 4)
9837 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9838 else
9839 addr = I915_READ(DSPADDR(intel_crtc->plane));
9840
9841 /* There is a potential issue here with a false positive after a flip
9842 * to the same address. We could address this by checking for a
9843 * non-incrementing frame counter.
9844 */
9845 return addr == work->gtt_offset;
9846 }
9847
9848 void intel_check_page_flip(struct drm_device *dev, int pipe)
9849 {
9850 struct drm_i915_private *dev_priv = dev->dev_private;
9851 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9852 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9853
9854 WARN_ON(!in_irq());
9855
9856 if (crtc == NULL)
9857 return;
9858
9859 spin_lock(&dev->event_lock);
9860 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9861 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9862 intel_crtc->unpin_work->flip_queued_vblank,
9863 drm_vblank_count(dev, pipe));
9864 page_flip_completed(intel_crtc);
9865 }
9866 spin_unlock(&dev->event_lock);
9867 }
9868
9869 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9870 struct drm_framebuffer *fb,
9871 struct drm_pending_vblank_event *event,
9872 uint32_t page_flip_flags)
9873 {
9874 struct drm_device *dev = crtc->dev;
9875 struct drm_i915_private *dev_priv = dev->dev_private;
9876 struct drm_framebuffer *old_fb = crtc->primary->fb;
9877 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9878 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9879 struct drm_plane *primary = crtc->primary;
9880 enum pipe pipe = intel_crtc->pipe;
9881 struct intel_unpin_work *work;
9882 struct intel_engine_cs *ring;
9883 int ret;
9884
9885 /*
9886 * drm_mode_page_flip_ioctl() should already catch this, but double
9887 * check to be safe. In the future we may enable pageflipping from
9888 * a disabled primary plane.
9889 */
9890 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9891 return -EBUSY;
9892
9893 /* Can't change pixel format via MI display flips. */
9894 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9895 return -EINVAL;
9896
9897 /*
9898 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9899 * Note that pitch changes could also affect these register.
9900 */
9901 if (INTEL_INFO(dev)->gen > 3 &&
9902 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9903 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9904 return -EINVAL;
9905
9906 if (i915_terminally_wedged(&dev_priv->gpu_error))
9907 goto out_hang;
9908
9909 work = kzalloc(sizeof(*work), GFP_KERNEL);
9910 if (work == NULL)
9911 return -ENOMEM;
9912
9913 work->event = event;
9914 work->crtc = crtc;
9915 work->old_fb = old_fb;
9916 INIT_WORK(&work->work, intel_unpin_work_fn);
9917
9918 ret = drm_crtc_vblank_get(crtc);
9919 if (ret)
9920 goto free_work;
9921
9922 /* We borrow the event spin lock for protecting unpin_work */
9923 spin_lock_irq(&dev->event_lock);
9924 if (intel_crtc->unpin_work) {
9925 /* Before declaring the flip queue wedged, check if
9926 * the hardware completed the operation behind our backs.
9927 */
9928 if (__intel_pageflip_stall_check(dev, crtc)) {
9929 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9930 page_flip_completed(intel_crtc);
9931 } else {
9932 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9933 spin_unlock_irq(&dev->event_lock);
9934
9935 drm_crtc_vblank_put(crtc);
9936 kfree(work);
9937 return -EBUSY;
9938 }
9939 }
9940 intel_crtc->unpin_work = work;
9941 spin_unlock_irq(&dev->event_lock);
9942
9943 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9944 flush_workqueue(dev_priv->wq);
9945
9946 /* Reference the objects for the scheduled work. */
9947 drm_framebuffer_reference(work->old_fb);
9948 drm_gem_object_reference(&obj->base);
9949
9950 crtc->primary->fb = fb;
9951 update_state_fb(crtc->primary);
9952
9953 work->pending_flip_obj = obj;
9954
9955 ret = i915_mutex_lock_interruptible(dev);
9956 if (ret)
9957 goto cleanup;
9958
9959 atomic_inc(&intel_crtc->unpin_work_count);
9960 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9961
9962 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9963 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9964
9965 if (IS_VALLEYVIEW(dev)) {
9966 ring = &dev_priv->ring[BCS];
9967 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
9968 /* vlv: DISPLAY_FLIP fails to change tiling */
9969 ring = NULL;
9970 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
9971 ring = &dev_priv->ring[BCS];
9972 } else if (INTEL_INFO(dev)->gen >= 7) {
9973 ring = i915_gem_request_get_ring(obj->last_read_req);
9974 if (ring == NULL || ring->id != RCS)
9975 ring = &dev_priv->ring[BCS];
9976 } else {
9977 ring = &dev_priv->ring[RCS];
9978 }
9979
9980 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, ring);
9981 if (ret)
9982 goto cleanup_pending;
9983
9984 work->gtt_offset =
9985 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9986
9987 if (use_mmio_flip(ring, obj)) {
9988 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9989 page_flip_flags);
9990 if (ret)
9991 goto cleanup_unpin;
9992
9993 i915_gem_request_assign(&work->flip_queued_req,
9994 obj->last_write_req);
9995 } else {
9996 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9997 page_flip_flags);
9998 if (ret)
9999 goto cleanup_unpin;
10000
10001 i915_gem_request_assign(&work->flip_queued_req,
10002 intel_ring_get_request(ring));
10003 }
10004
10005 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
10006 work->enable_stall_check = true;
10007
10008 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
10009 INTEL_FRONTBUFFER_PRIMARY(pipe));
10010
10011 intel_fbc_disable(dev);
10012 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10013 mutex_unlock(&dev->struct_mutex);
10014
10015 trace_i915_flip_request(intel_crtc->plane, obj);
10016
10017 return 0;
10018
10019 cleanup_unpin:
10020 intel_unpin_fb_obj(obj);
10021 cleanup_pending:
10022 atomic_dec(&intel_crtc->unpin_work_count);
10023 mutex_unlock(&dev->struct_mutex);
10024 cleanup:
10025 crtc->primary->fb = old_fb;
10026 update_state_fb(crtc->primary);
10027
10028 drm_gem_object_unreference_unlocked(&obj->base);
10029 drm_framebuffer_unreference(work->old_fb);
10030
10031 spin_lock_irq(&dev->event_lock);
10032 intel_crtc->unpin_work = NULL;
10033 spin_unlock_irq(&dev->event_lock);
10034
10035 drm_crtc_vblank_put(crtc);
10036 free_work:
10037 kfree(work);
10038
10039 if (ret == -EIO) {
10040 out_hang:
10041 ret = intel_plane_restore(primary);
10042 if (ret == 0 && event) {
10043 spin_lock_irq(&dev->event_lock);
10044 drm_send_vblank_event(dev, pipe, event);
10045 spin_unlock_irq(&dev->event_lock);
10046 }
10047 }
10048 return ret;
10049 }
10050
10051 static struct drm_crtc_helper_funcs intel_helper_funcs = {
10052 .mode_set_base_atomic = intel_pipe_set_base_atomic,
10053 .load_lut = intel_crtc_load_lut,
10054 .atomic_begin = intel_begin_crtc_commit,
10055 .atomic_flush = intel_finish_crtc_commit,
10056 };
10057
10058 /**
10059 * intel_modeset_update_staged_output_state
10060 *
10061 * Updates the staged output configuration state, e.g. after we've read out the
10062 * current hw state.
10063 */
10064 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
10065 {
10066 struct intel_crtc *crtc;
10067 struct intel_encoder *encoder;
10068 struct intel_connector *connector;
10069
10070 for_each_intel_connector(dev, connector) {
10071 connector->new_encoder =
10072 to_intel_encoder(connector->base.encoder);
10073 }
10074
10075 for_each_intel_encoder(dev, encoder) {
10076 encoder->new_crtc =
10077 to_intel_crtc(encoder->base.crtc);
10078 }
10079
10080 for_each_intel_crtc(dev, crtc) {
10081 crtc->new_enabled = crtc->base.state->enable;
10082
10083 if (crtc->new_enabled)
10084 crtc->new_config = crtc->config;
10085 else
10086 crtc->new_config = NULL;
10087 }
10088 }
10089
10090 /**
10091 * intel_modeset_commit_output_state
10092 *
10093 * This function copies the stage display pipe configuration to the real one.
10094 */
10095 static void intel_modeset_commit_output_state(struct drm_device *dev)
10096 {
10097 struct intel_crtc *crtc;
10098 struct intel_encoder *encoder;
10099 struct intel_connector *connector;
10100
10101 for_each_intel_connector(dev, connector) {
10102 connector->base.encoder = &connector->new_encoder->base;
10103 }
10104
10105 for_each_intel_encoder(dev, encoder) {
10106 encoder->base.crtc = &encoder->new_crtc->base;
10107 }
10108
10109 for_each_intel_crtc(dev, crtc) {
10110 crtc->base.state->enable = crtc->new_enabled;
10111 crtc->base.enabled = crtc->new_enabled;
10112 }
10113 }
10114
10115 static void
10116 connected_sink_compute_bpp(struct intel_connector *connector,
10117 struct intel_crtc_state *pipe_config)
10118 {
10119 int bpp = pipe_config->pipe_bpp;
10120
10121 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10122 connector->base.base.id,
10123 connector->base.name);
10124
10125 /* Don't use an invalid EDID bpc value */
10126 if (connector->base.display_info.bpc &&
10127 connector->base.display_info.bpc * 3 < bpp) {
10128 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10129 bpp, connector->base.display_info.bpc*3);
10130 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10131 }
10132
10133 /* Clamp bpp to 8 on screens without EDID 1.4 */
10134 if (connector->base.display_info.bpc == 0 && bpp > 24) {
10135 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10136 bpp);
10137 pipe_config->pipe_bpp = 24;
10138 }
10139 }
10140
10141 static int
10142 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10143 struct drm_framebuffer *fb,
10144 struct intel_crtc_state *pipe_config)
10145 {
10146 struct drm_device *dev = crtc->base.dev;
10147 struct intel_connector *connector;
10148 int bpp;
10149
10150 switch (fb->pixel_format) {
10151 case DRM_FORMAT_C8:
10152 bpp = 8*3; /* since we go through a colormap */
10153 break;
10154 case DRM_FORMAT_XRGB1555:
10155 case DRM_FORMAT_ARGB1555:
10156 /* checked in intel_framebuffer_init already */
10157 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10158 return -EINVAL;
10159 case DRM_FORMAT_RGB565:
10160 bpp = 6*3; /* min is 18bpp */
10161 break;
10162 case DRM_FORMAT_XBGR8888:
10163 case DRM_FORMAT_ABGR8888:
10164 /* checked in intel_framebuffer_init already */
10165 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10166 return -EINVAL;
10167 case DRM_FORMAT_XRGB8888:
10168 case DRM_FORMAT_ARGB8888:
10169 bpp = 8*3;
10170 break;
10171 case DRM_FORMAT_XRGB2101010:
10172 case DRM_FORMAT_ARGB2101010:
10173 case DRM_FORMAT_XBGR2101010:
10174 case DRM_FORMAT_ABGR2101010:
10175 /* checked in intel_framebuffer_init already */
10176 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10177 return -EINVAL;
10178 bpp = 10*3;
10179 break;
10180 /* TODO: gen4+ supports 16 bpc floating point, too. */
10181 default:
10182 DRM_DEBUG_KMS("unsupported depth\n");
10183 return -EINVAL;
10184 }
10185
10186 pipe_config->pipe_bpp = bpp;
10187
10188 /* Clamp display bpp to EDID value */
10189 for_each_intel_connector(dev, connector) {
10190 if (!connector->new_encoder ||
10191 connector->new_encoder->new_crtc != crtc)
10192 continue;
10193
10194 connected_sink_compute_bpp(connector, pipe_config);
10195 }
10196
10197 return bpp;
10198 }
10199
10200 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10201 {
10202 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10203 "type: 0x%x flags: 0x%x\n",
10204 mode->crtc_clock,
10205 mode->crtc_hdisplay, mode->crtc_hsync_start,
10206 mode->crtc_hsync_end, mode->crtc_htotal,
10207 mode->crtc_vdisplay, mode->crtc_vsync_start,
10208 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10209 }
10210
10211 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10212 struct intel_crtc_state *pipe_config,
10213 const char *context)
10214 {
10215 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10216 context, pipe_name(crtc->pipe));
10217
10218 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10219 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10220 pipe_config->pipe_bpp, pipe_config->dither);
10221 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10222 pipe_config->has_pch_encoder,
10223 pipe_config->fdi_lanes,
10224 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10225 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10226 pipe_config->fdi_m_n.tu);
10227 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10228 pipe_config->has_dp_encoder,
10229 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10230 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10231 pipe_config->dp_m_n.tu);
10232
10233 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10234 pipe_config->has_dp_encoder,
10235 pipe_config->dp_m2_n2.gmch_m,
10236 pipe_config->dp_m2_n2.gmch_n,
10237 pipe_config->dp_m2_n2.link_m,
10238 pipe_config->dp_m2_n2.link_n,
10239 pipe_config->dp_m2_n2.tu);
10240
10241 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10242 pipe_config->has_audio,
10243 pipe_config->has_infoframe);
10244
10245 DRM_DEBUG_KMS("requested mode:\n");
10246 drm_mode_debug_printmodeline(&pipe_config->base.mode);
10247 DRM_DEBUG_KMS("adjusted mode:\n");
10248 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10249 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10250 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10251 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10252 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10253 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10254 pipe_config->gmch_pfit.control,
10255 pipe_config->gmch_pfit.pgm_ratios,
10256 pipe_config->gmch_pfit.lvds_border_bits);
10257 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10258 pipe_config->pch_pfit.pos,
10259 pipe_config->pch_pfit.size,
10260 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10261 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10262 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10263 }
10264
10265 static bool encoders_cloneable(const struct intel_encoder *a,
10266 const struct intel_encoder *b)
10267 {
10268 /* masks could be asymmetric, so check both ways */
10269 return a == b || (a->cloneable & (1 << b->type) &&
10270 b->cloneable & (1 << a->type));
10271 }
10272
10273 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10274 struct intel_encoder *encoder)
10275 {
10276 struct drm_device *dev = crtc->base.dev;
10277 struct intel_encoder *source_encoder;
10278
10279 for_each_intel_encoder(dev, source_encoder) {
10280 if (source_encoder->new_crtc != crtc)
10281 continue;
10282
10283 if (!encoders_cloneable(encoder, source_encoder))
10284 return false;
10285 }
10286
10287 return true;
10288 }
10289
10290 static bool check_encoder_cloning(struct intel_crtc *crtc)
10291 {
10292 struct drm_device *dev = crtc->base.dev;
10293 struct intel_encoder *encoder;
10294
10295 for_each_intel_encoder(dev, encoder) {
10296 if (encoder->new_crtc != crtc)
10297 continue;
10298
10299 if (!check_single_encoder_cloning(crtc, encoder))
10300 return false;
10301 }
10302
10303 return true;
10304 }
10305
10306 static bool check_digital_port_conflicts(struct drm_device *dev)
10307 {
10308 struct intel_connector *connector;
10309 unsigned int used_ports = 0;
10310
10311 /*
10312 * Walk the connector list instead of the encoder
10313 * list to detect the problem on ddi platforms
10314 * where there's just one encoder per digital port.
10315 */
10316 for_each_intel_connector(dev, connector) {
10317 struct intel_encoder *encoder = connector->new_encoder;
10318
10319 if (!encoder)
10320 continue;
10321
10322 WARN_ON(!encoder->new_crtc);
10323
10324 switch (encoder->type) {
10325 unsigned int port_mask;
10326 case INTEL_OUTPUT_UNKNOWN:
10327 if (WARN_ON(!HAS_DDI(dev)))
10328 break;
10329 case INTEL_OUTPUT_DISPLAYPORT:
10330 case INTEL_OUTPUT_HDMI:
10331 case INTEL_OUTPUT_EDP:
10332 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10333
10334 /* the same port mustn't appear more than once */
10335 if (used_ports & port_mask)
10336 return false;
10337
10338 used_ports |= port_mask;
10339 default:
10340 break;
10341 }
10342 }
10343
10344 return true;
10345 }
10346
10347 static struct intel_crtc_state *
10348 intel_modeset_pipe_config(struct drm_crtc *crtc,
10349 struct drm_framebuffer *fb,
10350 struct drm_display_mode *mode)
10351 {
10352 struct drm_device *dev = crtc->dev;
10353 struct intel_encoder *encoder;
10354 struct intel_crtc_state *pipe_config;
10355 int plane_bpp, ret = -EINVAL;
10356 bool retry = true;
10357
10358 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10359 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10360 return ERR_PTR(-EINVAL);
10361 }
10362
10363 if (!check_digital_port_conflicts(dev)) {
10364 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10365 return ERR_PTR(-EINVAL);
10366 }
10367
10368 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10369 if (!pipe_config)
10370 return ERR_PTR(-ENOMEM);
10371
10372 pipe_config->base.crtc = crtc;
10373 drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
10374 drm_mode_copy(&pipe_config->base.mode, mode);
10375
10376 pipe_config->cpu_transcoder =
10377 (enum transcoder) to_intel_crtc(crtc)->pipe;
10378 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10379
10380 /*
10381 * Sanitize sync polarity flags based on requested ones. If neither
10382 * positive or negative polarity is requested, treat this as meaning
10383 * negative polarity.
10384 */
10385 if (!(pipe_config->base.adjusted_mode.flags &
10386 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10387 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10388
10389 if (!(pipe_config->base.adjusted_mode.flags &
10390 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10391 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10392
10393 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10394 * plane pixel format and any sink constraints into account. Returns the
10395 * source plane bpp so that dithering can be selected on mismatches
10396 * after encoders and crtc also have had their say. */
10397 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10398 fb, pipe_config);
10399 if (plane_bpp < 0)
10400 goto fail;
10401
10402 /*
10403 * Determine the real pipe dimensions. Note that stereo modes can
10404 * increase the actual pipe size due to the frame doubling and
10405 * insertion of additional space for blanks between the frame. This
10406 * is stored in the crtc timings. We use the requested mode to do this
10407 * computation to clearly distinguish it from the adjusted mode, which
10408 * can be changed by the connectors in the below retry loop.
10409 */
10410 drm_crtc_get_hv_timing(&pipe_config->base.mode,
10411 &pipe_config->pipe_src_w,
10412 &pipe_config->pipe_src_h);
10413
10414 encoder_retry:
10415 /* Ensure the port clock defaults are reset when retrying. */
10416 pipe_config->port_clock = 0;
10417 pipe_config->pixel_multiplier = 1;
10418
10419 /* Fill in default crtc timings, allow encoders to overwrite them. */
10420 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10421 CRTC_STEREO_DOUBLE);
10422
10423 /* Pass our mode to the connectors and the CRTC to give them a chance to
10424 * adjust it according to limitations or connector properties, and also
10425 * a chance to reject the mode entirely.
10426 */
10427 for_each_intel_encoder(dev, encoder) {
10428
10429 if (&encoder->new_crtc->base != crtc)
10430 continue;
10431
10432 if (!(encoder->compute_config(encoder, pipe_config))) {
10433 DRM_DEBUG_KMS("Encoder config failure\n");
10434 goto fail;
10435 }
10436 }
10437
10438 /* Set default port clock if not overwritten by the encoder. Needs to be
10439 * done afterwards in case the encoder adjusts the mode. */
10440 if (!pipe_config->port_clock)
10441 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10442 * pipe_config->pixel_multiplier;
10443
10444 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10445 if (ret < 0) {
10446 DRM_DEBUG_KMS("CRTC fixup failed\n");
10447 goto fail;
10448 }
10449
10450 if (ret == RETRY) {
10451 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10452 ret = -EINVAL;
10453 goto fail;
10454 }
10455
10456 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10457 retry = false;
10458 goto encoder_retry;
10459 }
10460
10461 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10462 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10463 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10464
10465 return pipe_config;
10466 fail:
10467 kfree(pipe_config);
10468 return ERR_PTR(ret);
10469 }
10470
10471 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10472 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10473 static void
10474 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10475 unsigned *prepare_pipes, unsigned *disable_pipes)
10476 {
10477 struct intel_crtc *intel_crtc;
10478 struct drm_device *dev = crtc->dev;
10479 struct intel_encoder *encoder;
10480 struct intel_connector *connector;
10481 struct drm_crtc *tmp_crtc;
10482
10483 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10484
10485 /* Check which crtcs have changed outputs connected to them, these need
10486 * to be part of the prepare_pipes mask. We don't (yet) support global
10487 * modeset across multiple crtcs, so modeset_pipes will only have one
10488 * bit set at most. */
10489 for_each_intel_connector(dev, connector) {
10490 if (connector->base.encoder == &connector->new_encoder->base)
10491 continue;
10492
10493 if (connector->base.encoder) {
10494 tmp_crtc = connector->base.encoder->crtc;
10495
10496 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10497 }
10498
10499 if (connector->new_encoder)
10500 *prepare_pipes |=
10501 1 << connector->new_encoder->new_crtc->pipe;
10502 }
10503
10504 for_each_intel_encoder(dev, encoder) {
10505 if (encoder->base.crtc == &encoder->new_crtc->base)
10506 continue;
10507
10508 if (encoder->base.crtc) {
10509 tmp_crtc = encoder->base.crtc;
10510
10511 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10512 }
10513
10514 if (encoder->new_crtc)
10515 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10516 }
10517
10518 /* Check for pipes that will be enabled/disabled ... */
10519 for_each_intel_crtc(dev, intel_crtc) {
10520 if (intel_crtc->base.state->enable == intel_crtc->new_enabled)
10521 continue;
10522
10523 if (!intel_crtc->new_enabled)
10524 *disable_pipes |= 1 << intel_crtc->pipe;
10525 else
10526 *prepare_pipes |= 1 << intel_crtc->pipe;
10527 }
10528
10529
10530 /* set_mode is also used to update properties on life display pipes. */
10531 intel_crtc = to_intel_crtc(crtc);
10532 if (intel_crtc->new_enabled)
10533 *prepare_pipes |= 1 << intel_crtc->pipe;
10534
10535 /*
10536 * For simplicity do a full modeset on any pipe where the output routing
10537 * changed. We could be more clever, but that would require us to be
10538 * more careful with calling the relevant encoder->mode_set functions.
10539 */
10540 if (*prepare_pipes)
10541 *modeset_pipes = *prepare_pipes;
10542
10543 /* ... and mask these out. */
10544 *modeset_pipes &= ~(*disable_pipes);
10545 *prepare_pipes &= ~(*disable_pipes);
10546
10547 /*
10548 * HACK: We don't (yet) fully support global modesets. intel_set_config
10549 * obies this rule, but the modeset restore mode of
10550 * intel_modeset_setup_hw_state does not.
10551 */
10552 *modeset_pipes &= 1 << intel_crtc->pipe;
10553 *prepare_pipes &= 1 << intel_crtc->pipe;
10554
10555 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10556 *modeset_pipes, *prepare_pipes, *disable_pipes);
10557 }
10558
10559 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10560 {
10561 struct drm_encoder *encoder;
10562 struct drm_device *dev = crtc->dev;
10563
10564 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10565 if (encoder->crtc == crtc)
10566 return true;
10567
10568 return false;
10569 }
10570
10571 static void
10572 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10573 {
10574 struct drm_i915_private *dev_priv = dev->dev_private;
10575 struct intel_encoder *intel_encoder;
10576 struct intel_crtc *intel_crtc;
10577 struct drm_connector *connector;
10578
10579 intel_shared_dpll_commit(dev_priv);
10580
10581 for_each_intel_encoder(dev, intel_encoder) {
10582 if (!intel_encoder->base.crtc)
10583 continue;
10584
10585 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10586
10587 if (prepare_pipes & (1 << intel_crtc->pipe))
10588 intel_encoder->connectors_active = false;
10589 }
10590
10591 intel_modeset_commit_output_state(dev);
10592
10593 /* Double check state. */
10594 for_each_intel_crtc(dev, intel_crtc) {
10595 WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base));
10596 WARN_ON(intel_crtc->new_config &&
10597 intel_crtc->new_config != intel_crtc->config);
10598 WARN_ON(intel_crtc->base.state->enable != !!intel_crtc->new_config);
10599 }
10600
10601 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10602 if (!connector->encoder || !connector->encoder->crtc)
10603 continue;
10604
10605 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10606
10607 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10608 struct drm_property *dpms_property =
10609 dev->mode_config.dpms_property;
10610
10611 connector->dpms = DRM_MODE_DPMS_ON;
10612 drm_object_property_set_value(&connector->base,
10613 dpms_property,
10614 DRM_MODE_DPMS_ON);
10615
10616 intel_encoder = to_intel_encoder(connector->encoder);
10617 intel_encoder->connectors_active = true;
10618 }
10619 }
10620
10621 }
10622
10623 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10624 {
10625 int diff;
10626
10627 if (clock1 == clock2)
10628 return true;
10629
10630 if (!clock1 || !clock2)
10631 return false;
10632
10633 diff = abs(clock1 - clock2);
10634
10635 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10636 return true;
10637
10638 return false;
10639 }
10640
10641 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10642 list_for_each_entry((intel_crtc), \
10643 &(dev)->mode_config.crtc_list, \
10644 base.head) \
10645 if (mask & (1 <<(intel_crtc)->pipe))
10646
10647 static bool
10648 intel_pipe_config_compare(struct drm_device *dev,
10649 struct intel_crtc_state *current_config,
10650 struct intel_crtc_state *pipe_config)
10651 {
10652 #define PIPE_CONF_CHECK_X(name) \
10653 if (current_config->name != pipe_config->name) { \
10654 DRM_ERROR("mismatch in " #name " " \
10655 "(expected 0x%08x, found 0x%08x)\n", \
10656 current_config->name, \
10657 pipe_config->name); \
10658 return false; \
10659 }
10660
10661 #define PIPE_CONF_CHECK_I(name) \
10662 if (current_config->name != pipe_config->name) { \
10663 DRM_ERROR("mismatch in " #name " " \
10664 "(expected %i, found %i)\n", \
10665 current_config->name, \
10666 pipe_config->name); \
10667 return false; \
10668 }
10669
10670 /* This is required for BDW+ where there is only one set of registers for
10671 * switching between high and low RR.
10672 * This macro can be used whenever a comparison has to be made between one
10673 * hw state and multiple sw state variables.
10674 */
10675 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10676 if ((current_config->name != pipe_config->name) && \
10677 (current_config->alt_name != pipe_config->name)) { \
10678 DRM_ERROR("mismatch in " #name " " \
10679 "(expected %i or %i, found %i)\n", \
10680 current_config->name, \
10681 current_config->alt_name, \
10682 pipe_config->name); \
10683 return false; \
10684 }
10685
10686 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10687 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10688 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10689 "(expected %i, found %i)\n", \
10690 current_config->name & (mask), \
10691 pipe_config->name & (mask)); \
10692 return false; \
10693 }
10694
10695 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10696 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10697 DRM_ERROR("mismatch in " #name " " \
10698 "(expected %i, found %i)\n", \
10699 current_config->name, \
10700 pipe_config->name); \
10701 return false; \
10702 }
10703
10704 #define PIPE_CONF_QUIRK(quirk) \
10705 ((current_config->quirks | pipe_config->quirks) & (quirk))
10706
10707 PIPE_CONF_CHECK_I(cpu_transcoder);
10708
10709 PIPE_CONF_CHECK_I(has_pch_encoder);
10710 PIPE_CONF_CHECK_I(fdi_lanes);
10711 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10712 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10713 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10714 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10715 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10716
10717 PIPE_CONF_CHECK_I(has_dp_encoder);
10718
10719 if (INTEL_INFO(dev)->gen < 8) {
10720 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10721 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10722 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10723 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10724 PIPE_CONF_CHECK_I(dp_m_n.tu);
10725
10726 if (current_config->has_drrs) {
10727 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10728 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10729 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10730 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10731 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10732 }
10733 } else {
10734 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10735 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10736 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10737 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10738 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10739 }
10740
10741 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
10742 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
10743 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
10744 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
10745 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
10746 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
10747
10748 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
10749 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
10750 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
10751 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
10752 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
10753 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
10754
10755 PIPE_CONF_CHECK_I(pixel_multiplier);
10756 PIPE_CONF_CHECK_I(has_hdmi_sink);
10757 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10758 IS_VALLEYVIEW(dev))
10759 PIPE_CONF_CHECK_I(limited_color_range);
10760 PIPE_CONF_CHECK_I(has_infoframe);
10761
10762 PIPE_CONF_CHECK_I(has_audio);
10763
10764 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10765 DRM_MODE_FLAG_INTERLACE);
10766
10767 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10768 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10769 DRM_MODE_FLAG_PHSYNC);
10770 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10771 DRM_MODE_FLAG_NHSYNC);
10772 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10773 DRM_MODE_FLAG_PVSYNC);
10774 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10775 DRM_MODE_FLAG_NVSYNC);
10776 }
10777
10778 PIPE_CONF_CHECK_I(pipe_src_w);
10779 PIPE_CONF_CHECK_I(pipe_src_h);
10780
10781 /*
10782 * FIXME: BIOS likes to set up a cloned config with lvds+external
10783 * screen. Since we don't yet re-compute the pipe config when moving
10784 * just the lvds port away to another pipe the sw tracking won't match.
10785 *
10786 * Proper atomic modesets with recomputed global state will fix this.
10787 * Until then just don't check gmch state for inherited modes.
10788 */
10789 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10790 PIPE_CONF_CHECK_I(gmch_pfit.control);
10791 /* pfit ratios are autocomputed by the hw on gen4+ */
10792 if (INTEL_INFO(dev)->gen < 4)
10793 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10794 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10795 }
10796
10797 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10798 if (current_config->pch_pfit.enabled) {
10799 PIPE_CONF_CHECK_I(pch_pfit.pos);
10800 PIPE_CONF_CHECK_I(pch_pfit.size);
10801 }
10802
10803 /* BDW+ don't expose a synchronous way to read the state */
10804 if (IS_HASWELL(dev))
10805 PIPE_CONF_CHECK_I(ips_enabled);
10806
10807 PIPE_CONF_CHECK_I(double_wide);
10808
10809 PIPE_CONF_CHECK_X(ddi_pll_sel);
10810
10811 PIPE_CONF_CHECK_I(shared_dpll);
10812 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10813 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10814 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10815 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10816 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10817 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
10818 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
10819 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
10820
10821 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10822 PIPE_CONF_CHECK_I(pipe_bpp);
10823
10824 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
10825 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10826
10827 #undef PIPE_CONF_CHECK_X
10828 #undef PIPE_CONF_CHECK_I
10829 #undef PIPE_CONF_CHECK_I_ALT
10830 #undef PIPE_CONF_CHECK_FLAGS
10831 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10832 #undef PIPE_CONF_QUIRK
10833
10834 return true;
10835 }
10836
10837 static void check_wm_state(struct drm_device *dev)
10838 {
10839 struct drm_i915_private *dev_priv = dev->dev_private;
10840 struct skl_ddb_allocation hw_ddb, *sw_ddb;
10841 struct intel_crtc *intel_crtc;
10842 int plane;
10843
10844 if (INTEL_INFO(dev)->gen < 9)
10845 return;
10846
10847 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
10848 sw_ddb = &dev_priv->wm.skl_hw.ddb;
10849
10850 for_each_intel_crtc(dev, intel_crtc) {
10851 struct skl_ddb_entry *hw_entry, *sw_entry;
10852 const enum pipe pipe = intel_crtc->pipe;
10853
10854 if (!intel_crtc->active)
10855 continue;
10856
10857 /* planes */
10858 for_each_plane(dev_priv, pipe, plane) {
10859 hw_entry = &hw_ddb.plane[pipe][plane];
10860 sw_entry = &sw_ddb->plane[pipe][plane];
10861
10862 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10863 continue;
10864
10865 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10866 "(expected (%u,%u), found (%u,%u))\n",
10867 pipe_name(pipe), plane + 1,
10868 sw_entry->start, sw_entry->end,
10869 hw_entry->start, hw_entry->end);
10870 }
10871
10872 /* cursor */
10873 hw_entry = &hw_ddb.cursor[pipe];
10874 sw_entry = &sw_ddb->cursor[pipe];
10875
10876 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10877 continue;
10878
10879 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10880 "(expected (%u,%u), found (%u,%u))\n",
10881 pipe_name(pipe),
10882 sw_entry->start, sw_entry->end,
10883 hw_entry->start, hw_entry->end);
10884 }
10885 }
10886
10887 static void
10888 check_connector_state(struct drm_device *dev)
10889 {
10890 struct intel_connector *connector;
10891
10892 for_each_intel_connector(dev, connector) {
10893 /* This also checks the encoder/connector hw state with the
10894 * ->get_hw_state callbacks. */
10895 intel_connector_check_state(connector);
10896
10897 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
10898 "connector's staged encoder doesn't match current encoder\n");
10899 }
10900 }
10901
10902 static void
10903 check_encoder_state(struct drm_device *dev)
10904 {
10905 struct intel_encoder *encoder;
10906 struct intel_connector *connector;
10907
10908 for_each_intel_encoder(dev, encoder) {
10909 bool enabled = false;
10910 bool active = false;
10911 enum pipe pipe, tracked_pipe;
10912
10913 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10914 encoder->base.base.id,
10915 encoder->base.name);
10916
10917 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
10918 "encoder's stage crtc doesn't match current crtc\n");
10919 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
10920 "encoder's active_connectors set, but no crtc\n");
10921
10922 for_each_intel_connector(dev, connector) {
10923 if (connector->base.encoder != &encoder->base)
10924 continue;
10925 enabled = true;
10926 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10927 active = true;
10928 }
10929 /*
10930 * for MST connectors if we unplug the connector is gone
10931 * away but the encoder is still connected to a crtc
10932 * until a modeset happens in response to the hotplug.
10933 */
10934 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10935 continue;
10936
10937 I915_STATE_WARN(!!encoder->base.crtc != enabled,
10938 "encoder's enabled state mismatch "
10939 "(expected %i, found %i)\n",
10940 !!encoder->base.crtc, enabled);
10941 I915_STATE_WARN(active && !encoder->base.crtc,
10942 "active encoder with no crtc\n");
10943
10944 I915_STATE_WARN(encoder->connectors_active != active,
10945 "encoder's computed active state doesn't match tracked active state "
10946 "(expected %i, found %i)\n", active, encoder->connectors_active);
10947
10948 active = encoder->get_hw_state(encoder, &pipe);
10949 I915_STATE_WARN(active != encoder->connectors_active,
10950 "encoder's hw state doesn't match sw tracking "
10951 "(expected %i, found %i)\n",
10952 encoder->connectors_active, active);
10953
10954 if (!encoder->base.crtc)
10955 continue;
10956
10957 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10958 I915_STATE_WARN(active && pipe != tracked_pipe,
10959 "active encoder's pipe doesn't match"
10960 "(expected %i, found %i)\n",
10961 tracked_pipe, pipe);
10962
10963 }
10964 }
10965
10966 static void
10967 check_crtc_state(struct drm_device *dev)
10968 {
10969 struct drm_i915_private *dev_priv = dev->dev_private;
10970 struct intel_crtc *crtc;
10971 struct intel_encoder *encoder;
10972 struct intel_crtc_state pipe_config;
10973
10974 for_each_intel_crtc(dev, crtc) {
10975 bool enabled = false;
10976 bool active = false;
10977
10978 memset(&pipe_config, 0, sizeof(pipe_config));
10979
10980 DRM_DEBUG_KMS("[CRTC:%d]\n",
10981 crtc->base.base.id);
10982
10983 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
10984 "active crtc, but not enabled in sw tracking\n");
10985
10986 for_each_intel_encoder(dev, encoder) {
10987 if (encoder->base.crtc != &crtc->base)
10988 continue;
10989 enabled = true;
10990 if (encoder->connectors_active)
10991 active = true;
10992 }
10993
10994 I915_STATE_WARN(active != crtc->active,
10995 "crtc's computed active state doesn't match tracked active state "
10996 "(expected %i, found %i)\n", active, crtc->active);
10997 I915_STATE_WARN(enabled != crtc->base.state->enable,
10998 "crtc's computed enabled state doesn't match tracked enabled state "
10999 "(expected %i, found %i)\n", enabled,
11000 crtc->base.state->enable);
11001
11002 active = dev_priv->display.get_pipe_config(crtc,
11003 &pipe_config);
11004
11005 /* hw state is inconsistent with the pipe quirk */
11006 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
11007 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
11008 active = crtc->active;
11009
11010 for_each_intel_encoder(dev, encoder) {
11011 enum pipe pipe;
11012 if (encoder->base.crtc != &crtc->base)
11013 continue;
11014 if (encoder->get_hw_state(encoder, &pipe))
11015 encoder->get_config(encoder, &pipe_config);
11016 }
11017
11018 I915_STATE_WARN(crtc->active != active,
11019 "crtc active state doesn't match with hw state "
11020 "(expected %i, found %i)\n", crtc->active, active);
11021
11022 if (active &&
11023 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
11024 I915_STATE_WARN(1, "pipe state doesn't match!\n");
11025 intel_dump_pipe_config(crtc, &pipe_config,
11026 "[hw state]");
11027 intel_dump_pipe_config(crtc, crtc->config,
11028 "[sw state]");
11029 }
11030 }
11031 }
11032
11033 static void
11034 check_shared_dpll_state(struct drm_device *dev)
11035 {
11036 struct drm_i915_private *dev_priv = dev->dev_private;
11037 struct intel_crtc *crtc;
11038 struct intel_dpll_hw_state dpll_hw_state;
11039 int i;
11040
11041 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11042 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11043 int enabled_crtcs = 0, active_crtcs = 0;
11044 bool active;
11045
11046 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11047
11048 DRM_DEBUG_KMS("%s\n", pll->name);
11049
11050 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
11051
11052 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
11053 "more active pll users than references: %i vs %i\n",
11054 pll->active, hweight32(pll->config.crtc_mask));
11055 I915_STATE_WARN(pll->active && !pll->on,
11056 "pll in active use but not on in sw tracking\n");
11057 I915_STATE_WARN(pll->on && !pll->active,
11058 "pll in on but not on in use in sw tracking\n");
11059 I915_STATE_WARN(pll->on != active,
11060 "pll on state mismatch (expected %i, found %i)\n",
11061 pll->on, active);
11062
11063 for_each_intel_crtc(dev, crtc) {
11064 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
11065 enabled_crtcs++;
11066 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11067 active_crtcs++;
11068 }
11069 I915_STATE_WARN(pll->active != active_crtcs,
11070 "pll active crtcs mismatch (expected %i, found %i)\n",
11071 pll->active, active_crtcs);
11072 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
11073 "pll enabled crtcs mismatch (expected %i, found %i)\n",
11074 hweight32(pll->config.crtc_mask), enabled_crtcs);
11075
11076 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
11077 sizeof(dpll_hw_state)),
11078 "pll hw state mismatch\n");
11079 }
11080 }
11081
11082 void
11083 intel_modeset_check_state(struct drm_device *dev)
11084 {
11085 check_wm_state(dev);
11086 check_connector_state(dev);
11087 check_encoder_state(dev);
11088 check_crtc_state(dev);
11089 check_shared_dpll_state(dev);
11090 }
11091
11092 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
11093 int dotclock)
11094 {
11095 /*
11096 * FDI already provided one idea for the dotclock.
11097 * Yell if the encoder disagrees.
11098 */
11099 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
11100 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11101 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
11102 }
11103
11104 static void update_scanline_offset(struct intel_crtc *crtc)
11105 {
11106 struct drm_device *dev = crtc->base.dev;
11107
11108 /*
11109 * The scanline counter increments at the leading edge of hsync.
11110 *
11111 * On most platforms it starts counting from vtotal-1 on the
11112 * first active line. That means the scanline counter value is
11113 * always one less than what we would expect. Ie. just after
11114 * start of vblank, which also occurs at start of hsync (on the
11115 * last active line), the scanline counter will read vblank_start-1.
11116 *
11117 * On gen2 the scanline counter starts counting from 1 instead
11118 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11119 * to keep the value positive), instead of adding one.
11120 *
11121 * On HSW+ the behaviour of the scanline counter depends on the output
11122 * type. For DP ports it behaves like most other platforms, but on HDMI
11123 * there's an extra 1 line difference. So we need to add two instead of
11124 * one to the value.
11125 */
11126 if (IS_GEN2(dev)) {
11127 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
11128 int vtotal;
11129
11130 vtotal = mode->crtc_vtotal;
11131 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
11132 vtotal /= 2;
11133
11134 crtc->scanline_offset = vtotal - 1;
11135 } else if (HAS_DDI(dev) &&
11136 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
11137 crtc->scanline_offset = 2;
11138 } else
11139 crtc->scanline_offset = 1;
11140 }
11141
11142 static struct intel_crtc_state *
11143 intel_modeset_compute_config(struct drm_crtc *crtc,
11144 struct drm_display_mode *mode,
11145 struct drm_framebuffer *fb,
11146 unsigned *modeset_pipes,
11147 unsigned *prepare_pipes,
11148 unsigned *disable_pipes)
11149 {
11150 struct intel_crtc_state *pipe_config = NULL;
11151
11152 intel_modeset_affected_pipes(crtc, modeset_pipes,
11153 prepare_pipes, disable_pipes);
11154
11155 if ((*modeset_pipes) == 0)
11156 goto out;
11157
11158 /*
11159 * Note this needs changes when we start tracking multiple modes
11160 * and crtcs. At that point we'll need to compute the whole config
11161 * (i.e. one pipe_config for each crtc) rather than just the one
11162 * for this crtc.
11163 */
11164 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
11165 if (IS_ERR(pipe_config)) {
11166 goto out;
11167 }
11168 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11169 "[modeset]");
11170
11171 out:
11172 return pipe_config;
11173 }
11174
11175 static int __intel_set_mode_setup_plls(struct drm_device *dev,
11176 unsigned modeset_pipes,
11177 unsigned disable_pipes)
11178 {
11179 struct drm_i915_private *dev_priv = to_i915(dev);
11180 unsigned clear_pipes = modeset_pipes | disable_pipes;
11181 struct intel_crtc *intel_crtc;
11182 int ret = 0;
11183
11184 if (!dev_priv->display.crtc_compute_clock)
11185 return 0;
11186
11187 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
11188 if (ret)
11189 goto done;
11190
11191 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11192 struct intel_crtc_state *state = intel_crtc->new_config;
11193 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11194 state);
11195 if (ret) {
11196 intel_shared_dpll_abort_config(dev_priv);
11197 goto done;
11198 }
11199 }
11200
11201 done:
11202 return ret;
11203 }
11204
11205 static int __intel_set_mode(struct drm_crtc *crtc,
11206 struct drm_display_mode *mode,
11207 int x, int y, struct drm_framebuffer *fb,
11208 struct intel_crtc_state *pipe_config,
11209 unsigned modeset_pipes,
11210 unsigned prepare_pipes,
11211 unsigned disable_pipes)
11212 {
11213 struct drm_device *dev = crtc->dev;
11214 struct drm_i915_private *dev_priv = dev->dev_private;
11215 struct drm_display_mode *saved_mode;
11216 struct intel_crtc *intel_crtc;
11217 int ret = 0;
11218
11219 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
11220 if (!saved_mode)
11221 return -ENOMEM;
11222
11223 *saved_mode = crtc->mode;
11224
11225 if (modeset_pipes)
11226 to_intel_crtc(crtc)->new_config = pipe_config;
11227
11228 /*
11229 * See if the config requires any additional preparation, e.g.
11230 * to adjust global state with pipes off. We need to do this
11231 * here so we can get the modeset_pipe updated config for the new
11232 * mode set on this crtc. For other crtcs we need to use the
11233 * adjusted_mode bits in the crtc directly.
11234 */
11235 if (IS_VALLEYVIEW(dev)) {
11236 valleyview_modeset_global_pipes(dev, &prepare_pipes);
11237
11238 /* may have added more to prepare_pipes than we should */
11239 prepare_pipes &= ~disable_pipes;
11240 }
11241
11242 ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
11243 if (ret)
11244 goto done;
11245
11246 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11247 intel_crtc_disable(&intel_crtc->base);
11248
11249 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11250 if (intel_crtc->base.state->enable)
11251 dev_priv->display.crtc_disable(&intel_crtc->base);
11252 }
11253
11254 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11255 * to set it here already despite that we pass it down the callchain.
11256 *
11257 * Note we'll need to fix this up when we start tracking multiple
11258 * pipes; here we assume a single modeset_pipe and only track the
11259 * single crtc and mode.
11260 */
11261 if (modeset_pipes) {
11262 crtc->mode = *mode;
11263 /* mode_set/enable/disable functions rely on a correct pipe
11264 * config. */
11265 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
11266
11267 /*
11268 * Calculate and store various constants which
11269 * are later needed by vblank and swap-completion
11270 * timestamping. They are derived from true hwmode.
11271 */
11272 drm_calc_timestamping_constants(crtc,
11273 &pipe_config->base.adjusted_mode);
11274 }
11275
11276 /* Only after disabling all output pipelines that will be changed can we
11277 * update the the output configuration. */
11278 intel_modeset_update_state(dev, prepare_pipes);
11279
11280 modeset_update_crtc_power_domains(dev);
11281
11282 /* Set up the DPLL and any encoders state that needs to adjust or depend
11283 * on the DPLL.
11284 */
11285 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11286 struct drm_plane *primary = intel_crtc->base.primary;
11287 int vdisplay, hdisplay;
11288
11289 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11290 ret = primary->funcs->update_plane(primary, &intel_crtc->base,
11291 fb, 0, 0,
11292 hdisplay, vdisplay,
11293 x << 16, y << 16,
11294 hdisplay << 16, vdisplay << 16);
11295 }
11296
11297 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11298 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11299 update_scanline_offset(intel_crtc);
11300
11301 dev_priv->display.crtc_enable(&intel_crtc->base);
11302 }
11303
11304 /* FIXME: add subpixel order */
11305 done:
11306 if (ret && crtc->state->enable)
11307 crtc->mode = *saved_mode;
11308
11309 kfree(saved_mode);
11310 return ret;
11311 }
11312
11313 static int intel_set_mode_pipes(struct drm_crtc *crtc,
11314 struct drm_display_mode *mode,
11315 int x, int y, struct drm_framebuffer *fb,
11316 struct intel_crtc_state *pipe_config,
11317 unsigned modeset_pipes,
11318 unsigned prepare_pipes,
11319 unsigned disable_pipes)
11320 {
11321 int ret;
11322
11323 ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11324 prepare_pipes, disable_pipes);
11325
11326 if (ret == 0)
11327 intel_modeset_check_state(crtc->dev);
11328
11329 return ret;
11330 }
11331
11332 static int intel_set_mode(struct drm_crtc *crtc,
11333 struct drm_display_mode *mode,
11334 int x, int y, struct drm_framebuffer *fb)
11335 {
11336 struct intel_crtc_state *pipe_config;
11337 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11338
11339 pipe_config = intel_modeset_compute_config(crtc, mode, fb,
11340 &modeset_pipes,
11341 &prepare_pipes,
11342 &disable_pipes);
11343
11344 if (IS_ERR(pipe_config))
11345 return PTR_ERR(pipe_config);
11346
11347 return intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11348 modeset_pipes, prepare_pipes,
11349 disable_pipes);
11350 }
11351
11352 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11353 {
11354 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11355 }
11356
11357 #undef for_each_intel_crtc_masked
11358
11359 static void intel_set_config_free(struct intel_set_config *config)
11360 {
11361 if (!config)
11362 return;
11363
11364 kfree(config->save_connector_encoders);
11365 kfree(config->save_encoder_crtcs);
11366 kfree(config->save_crtc_enabled);
11367 kfree(config);
11368 }
11369
11370 static int intel_set_config_save_state(struct drm_device *dev,
11371 struct intel_set_config *config)
11372 {
11373 struct drm_crtc *crtc;
11374 struct drm_encoder *encoder;
11375 struct drm_connector *connector;
11376 int count;
11377
11378 config->save_crtc_enabled =
11379 kcalloc(dev->mode_config.num_crtc,
11380 sizeof(bool), GFP_KERNEL);
11381 if (!config->save_crtc_enabled)
11382 return -ENOMEM;
11383
11384 config->save_encoder_crtcs =
11385 kcalloc(dev->mode_config.num_encoder,
11386 sizeof(struct drm_crtc *), GFP_KERNEL);
11387 if (!config->save_encoder_crtcs)
11388 return -ENOMEM;
11389
11390 config->save_connector_encoders =
11391 kcalloc(dev->mode_config.num_connector,
11392 sizeof(struct drm_encoder *), GFP_KERNEL);
11393 if (!config->save_connector_encoders)
11394 return -ENOMEM;
11395
11396 /* Copy data. Note that driver private data is not affected.
11397 * Should anything bad happen only the expected state is
11398 * restored, not the drivers personal bookkeeping.
11399 */
11400 count = 0;
11401 for_each_crtc(dev, crtc) {
11402 config->save_crtc_enabled[count++] = crtc->state->enable;
11403 }
11404
11405 count = 0;
11406 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11407 config->save_encoder_crtcs[count++] = encoder->crtc;
11408 }
11409
11410 count = 0;
11411 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11412 config->save_connector_encoders[count++] = connector->encoder;
11413 }
11414
11415 return 0;
11416 }
11417
11418 static void intel_set_config_restore_state(struct drm_device *dev,
11419 struct intel_set_config *config)
11420 {
11421 struct intel_crtc *crtc;
11422 struct intel_encoder *encoder;
11423 struct intel_connector *connector;
11424 int count;
11425
11426 count = 0;
11427 for_each_intel_crtc(dev, crtc) {
11428 crtc->new_enabled = config->save_crtc_enabled[count++];
11429
11430 if (crtc->new_enabled)
11431 crtc->new_config = crtc->config;
11432 else
11433 crtc->new_config = NULL;
11434 }
11435
11436 count = 0;
11437 for_each_intel_encoder(dev, encoder) {
11438 encoder->new_crtc =
11439 to_intel_crtc(config->save_encoder_crtcs[count++]);
11440 }
11441
11442 count = 0;
11443 for_each_intel_connector(dev, connector) {
11444 connector->new_encoder =
11445 to_intel_encoder(config->save_connector_encoders[count++]);
11446 }
11447 }
11448
11449 static bool
11450 is_crtc_connector_off(struct drm_mode_set *set)
11451 {
11452 int i;
11453
11454 if (set->num_connectors == 0)
11455 return false;
11456
11457 if (WARN_ON(set->connectors == NULL))
11458 return false;
11459
11460 for (i = 0; i < set->num_connectors; i++)
11461 if (set->connectors[i]->encoder &&
11462 set->connectors[i]->encoder->crtc == set->crtc &&
11463 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11464 return true;
11465
11466 return false;
11467 }
11468
11469 static void
11470 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11471 struct intel_set_config *config)
11472 {
11473
11474 /* We should be able to check here if the fb has the same properties
11475 * and then just flip_or_move it */
11476 if (is_crtc_connector_off(set)) {
11477 config->mode_changed = true;
11478 } else if (set->crtc->primary->fb != set->fb) {
11479 /*
11480 * If we have no fb, we can only flip as long as the crtc is
11481 * active, otherwise we need a full mode set. The crtc may
11482 * be active if we've only disabled the primary plane, or
11483 * in fastboot situations.
11484 */
11485 if (set->crtc->primary->fb == NULL) {
11486 struct intel_crtc *intel_crtc =
11487 to_intel_crtc(set->crtc);
11488
11489 if (intel_crtc->active) {
11490 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11491 config->fb_changed = true;
11492 } else {
11493 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11494 config->mode_changed = true;
11495 }
11496 } else if (set->fb == NULL) {
11497 config->mode_changed = true;
11498 } else if (set->fb->pixel_format !=
11499 set->crtc->primary->fb->pixel_format) {
11500 config->mode_changed = true;
11501 } else {
11502 config->fb_changed = true;
11503 }
11504 }
11505
11506 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11507 config->fb_changed = true;
11508
11509 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11510 DRM_DEBUG_KMS("modes are different, full mode set\n");
11511 drm_mode_debug_printmodeline(&set->crtc->mode);
11512 drm_mode_debug_printmodeline(set->mode);
11513 config->mode_changed = true;
11514 }
11515
11516 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11517 set->crtc->base.id, config->mode_changed, config->fb_changed);
11518 }
11519
11520 static int
11521 intel_modeset_stage_output_state(struct drm_device *dev,
11522 struct drm_mode_set *set,
11523 struct intel_set_config *config)
11524 {
11525 struct intel_connector *connector;
11526 struct intel_encoder *encoder;
11527 struct intel_crtc *crtc;
11528 int ro;
11529
11530 /* The upper layers ensure that we either disable a crtc or have a list
11531 * of connectors. For paranoia, double-check this. */
11532 WARN_ON(!set->fb && (set->num_connectors != 0));
11533 WARN_ON(set->fb && (set->num_connectors == 0));
11534
11535 for_each_intel_connector(dev, connector) {
11536 /* Otherwise traverse passed in connector list and get encoders
11537 * for them. */
11538 for (ro = 0; ro < set->num_connectors; ro++) {
11539 if (set->connectors[ro] == &connector->base) {
11540 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11541 break;
11542 }
11543 }
11544
11545 /* If we disable the crtc, disable all its connectors. Also, if
11546 * the connector is on the changing crtc but not on the new
11547 * connector list, disable it. */
11548 if ((!set->fb || ro == set->num_connectors) &&
11549 connector->base.encoder &&
11550 connector->base.encoder->crtc == set->crtc) {
11551 connector->new_encoder = NULL;
11552
11553 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11554 connector->base.base.id,
11555 connector->base.name);
11556 }
11557
11558
11559 if (&connector->new_encoder->base != connector->base.encoder) {
11560 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n",
11561 connector->base.base.id,
11562 connector->base.name);
11563 config->mode_changed = true;
11564 }
11565 }
11566 /* connector->new_encoder is now updated for all connectors. */
11567
11568 /* Update crtc of enabled connectors. */
11569 for_each_intel_connector(dev, connector) {
11570 struct drm_crtc *new_crtc;
11571
11572 if (!connector->new_encoder)
11573 continue;
11574
11575 new_crtc = connector->new_encoder->base.crtc;
11576
11577 for (ro = 0; ro < set->num_connectors; ro++) {
11578 if (set->connectors[ro] == &connector->base)
11579 new_crtc = set->crtc;
11580 }
11581
11582 /* Make sure the new CRTC will work with the encoder */
11583 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11584 new_crtc)) {
11585 return -EINVAL;
11586 }
11587 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11588
11589 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11590 connector->base.base.id,
11591 connector->base.name,
11592 new_crtc->base.id);
11593 }
11594
11595 /* Check for any encoders that needs to be disabled. */
11596 for_each_intel_encoder(dev, encoder) {
11597 int num_connectors = 0;
11598 for_each_intel_connector(dev, connector) {
11599 if (connector->new_encoder == encoder) {
11600 WARN_ON(!connector->new_encoder->new_crtc);
11601 num_connectors++;
11602 }
11603 }
11604
11605 if (num_connectors == 0)
11606 encoder->new_crtc = NULL;
11607 else if (num_connectors > 1)
11608 return -EINVAL;
11609
11610 /* Only now check for crtc changes so we don't miss encoders
11611 * that will be disabled. */
11612 if (&encoder->new_crtc->base != encoder->base.crtc) {
11613 DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n",
11614 encoder->base.base.id,
11615 encoder->base.name);
11616 config->mode_changed = true;
11617 }
11618 }
11619 /* Now we've also updated encoder->new_crtc for all encoders. */
11620 for_each_intel_connector(dev, connector) {
11621 if (connector->new_encoder)
11622 if (connector->new_encoder != connector->encoder)
11623 connector->encoder = connector->new_encoder;
11624 }
11625 for_each_intel_crtc(dev, crtc) {
11626 crtc->new_enabled = false;
11627
11628 for_each_intel_encoder(dev, encoder) {
11629 if (encoder->new_crtc == crtc) {
11630 crtc->new_enabled = true;
11631 break;
11632 }
11633 }
11634
11635 if (crtc->new_enabled != crtc->base.state->enable) {
11636 DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n",
11637 crtc->base.base.id,
11638 crtc->new_enabled ? "en" : "dis");
11639 config->mode_changed = true;
11640 }
11641
11642 if (crtc->new_enabled)
11643 crtc->new_config = crtc->config;
11644 else
11645 crtc->new_config = NULL;
11646 }
11647
11648 return 0;
11649 }
11650
11651 static void disable_crtc_nofb(struct intel_crtc *crtc)
11652 {
11653 struct drm_device *dev = crtc->base.dev;
11654 struct intel_encoder *encoder;
11655 struct intel_connector *connector;
11656
11657 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11658 pipe_name(crtc->pipe));
11659
11660 for_each_intel_connector(dev, connector) {
11661 if (connector->new_encoder &&
11662 connector->new_encoder->new_crtc == crtc)
11663 connector->new_encoder = NULL;
11664 }
11665
11666 for_each_intel_encoder(dev, encoder) {
11667 if (encoder->new_crtc == crtc)
11668 encoder->new_crtc = NULL;
11669 }
11670
11671 crtc->new_enabled = false;
11672 crtc->new_config = NULL;
11673 }
11674
11675 static int intel_crtc_set_config(struct drm_mode_set *set)
11676 {
11677 struct drm_device *dev;
11678 struct drm_mode_set save_set;
11679 struct intel_set_config *config;
11680 struct intel_crtc_state *pipe_config;
11681 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11682 int ret;
11683
11684 BUG_ON(!set);
11685 BUG_ON(!set->crtc);
11686 BUG_ON(!set->crtc->helper_private);
11687
11688 /* Enforce sane interface api - has been abused by the fb helper. */
11689 BUG_ON(!set->mode && set->fb);
11690 BUG_ON(set->fb && set->num_connectors == 0);
11691
11692 if (set->fb) {
11693 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11694 set->crtc->base.id, set->fb->base.id,
11695 (int)set->num_connectors, set->x, set->y);
11696 } else {
11697 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11698 }
11699
11700 dev = set->crtc->dev;
11701
11702 ret = -ENOMEM;
11703 config = kzalloc(sizeof(*config), GFP_KERNEL);
11704 if (!config)
11705 goto out_config;
11706
11707 ret = intel_set_config_save_state(dev, config);
11708 if (ret)
11709 goto out_config;
11710
11711 save_set.crtc = set->crtc;
11712 save_set.mode = &set->crtc->mode;
11713 save_set.x = set->crtc->x;
11714 save_set.y = set->crtc->y;
11715 save_set.fb = set->crtc->primary->fb;
11716
11717 /* Compute whether we need a full modeset, only an fb base update or no
11718 * change at all. In the future we might also check whether only the
11719 * mode changed, e.g. for LVDS where we only change the panel fitter in
11720 * such cases. */
11721 intel_set_config_compute_mode_changes(set, config);
11722
11723 ret = intel_modeset_stage_output_state(dev, set, config);
11724 if (ret)
11725 goto fail;
11726
11727 pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
11728 set->fb,
11729 &modeset_pipes,
11730 &prepare_pipes,
11731 &disable_pipes);
11732 if (IS_ERR(pipe_config)) {
11733 ret = PTR_ERR(pipe_config);
11734 goto fail;
11735 } else if (pipe_config) {
11736 if (pipe_config->has_audio !=
11737 to_intel_crtc(set->crtc)->config->has_audio)
11738 config->mode_changed = true;
11739
11740 /*
11741 * Note we have an issue here with infoframes: current code
11742 * only updates them on the full mode set path per hw
11743 * requirements. So here we should be checking for any
11744 * required changes and forcing a mode set.
11745 */
11746 }
11747
11748 /* set_mode will free it in the mode_changed case */
11749 if (!config->mode_changed)
11750 kfree(pipe_config);
11751
11752 intel_update_pipe_size(to_intel_crtc(set->crtc));
11753
11754 if (config->mode_changed) {
11755 ret = intel_set_mode_pipes(set->crtc, set->mode,
11756 set->x, set->y, set->fb, pipe_config,
11757 modeset_pipes, prepare_pipes,
11758 disable_pipes);
11759 } else if (config->fb_changed) {
11760 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11761 struct drm_plane *primary = set->crtc->primary;
11762 int vdisplay, hdisplay;
11763
11764 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
11765 ret = primary->funcs->update_plane(primary, set->crtc, set->fb,
11766 0, 0, hdisplay, vdisplay,
11767 set->x << 16, set->y << 16,
11768 hdisplay << 16, vdisplay << 16);
11769
11770 /*
11771 * We need to make sure the primary plane is re-enabled if it
11772 * has previously been turned off.
11773 */
11774 if (!intel_crtc->primary_enabled && ret == 0) {
11775 WARN_ON(!intel_crtc->active);
11776 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11777 }
11778
11779 /*
11780 * In the fastboot case this may be our only check of the
11781 * state after boot. It would be better to only do it on
11782 * the first update, but we don't have a nice way of doing that
11783 * (and really, set_config isn't used much for high freq page
11784 * flipping, so increasing its cost here shouldn't be a big
11785 * deal).
11786 */
11787 if (i915.fastboot && ret == 0)
11788 intel_modeset_check_state(set->crtc->dev);
11789 }
11790
11791 if (ret) {
11792 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11793 set->crtc->base.id, ret);
11794 fail:
11795 intel_set_config_restore_state(dev, config);
11796
11797 /*
11798 * HACK: if the pipe was on, but we didn't have a framebuffer,
11799 * force the pipe off to avoid oopsing in the modeset code
11800 * due to fb==NULL. This should only happen during boot since
11801 * we don't yet reconstruct the FB from the hardware state.
11802 */
11803 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11804 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11805
11806 /* Try to restore the config */
11807 if (config->mode_changed &&
11808 intel_set_mode(save_set.crtc, save_set.mode,
11809 save_set.x, save_set.y, save_set.fb))
11810 DRM_ERROR("failed to restore config after modeset failure\n");
11811 }
11812
11813 out_config:
11814 intel_set_config_free(config);
11815 return ret;
11816 }
11817
11818 static const struct drm_crtc_funcs intel_crtc_funcs = {
11819 .gamma_set = intel_crtc_gamma_set,
11820 .set_config = intel_crtc_set_config,
11821 .destroy = intel_crtc_destroy,
11822 .page_flip = intel_crtc_page_flip,
11823 .atomic_duplicate_state = intel_crtc_duplicate_state,
11824 .atomic_destroy_state = intel_crtc_destroy_state,
11825 };
11826
11827 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11828 struct intel_shared_dpll *pll,
11829 struct intel_dpll_hw_state *hw_state)
11830 {
11831 uint32_t val;
11832
11833 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11834 return false;
11835
11836 val = I915_READ(PCH_DPLL(pll->id));
11837 hw_state->dpll = val;
11838 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11839 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11840
11841 return val & DPLL_VCO_ENABLE;
11842 }
11843
11844 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11845 struct intel_shared_dpll *pll)
11846 {
11847 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11848 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
11849 }
11850
11851 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11852 struct intel_shared_dpll *pll)
11853 {
11854 /* PCH refclock must be enabled first */
11855 ibx_assert_pch_refclk_enabled(dev_priv);
11856
11857 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11858
11859 /* Wait for the clocks to stabilize. */
11860 POSTING_READ(PCH_DPLL(pll->id));
11861 udelay(150);
11862
11863 /* The pixel multiplier can only be updated once the
11864 * DPLL is enabled and the clocks are stable.
11865 *
11866 * So write it again.
11867 */
11868 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11869 POSTING_READ(PCH_DPLL(pll->id));
11870 udelay(200);
11871 }
11872
11873 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11874 struct intel_shared_dpll *pll)
11875 {
11876 struct drm_device *dev = dev_priv->dev;
11877 struct intel_crtc *crtc;
11878
11879 /* Make sure no transcoder isn't still depending on us. */
11880 for_each_intel_crtc(dev, crtc) {
11881 if (intel_crtc_to_shared_dpll(crtc) == pll)
11882 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11883 }
11884
11885 I915_WRITE(PCH_DPLL(pll->id), 0);
11886 POSTING_READ(PCH_DPLL(pll->id));
11887 udelay(200);
11888 }
11889
11890 static char *ibx_pch_dpll_names[] = {
11891 "PCH DPLL A",
11892 "PCH DPLL B",
11893 };
11894
11895 static void ibx_pch_dpll_init(struct drm_device *dev)
11896 {
11897 struct drm_i915_private *dev_priv = dev->dev_private;
11898 int i;
11899
11900 dev_priv->num_shared_dpll = 2;
11901
11902 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11903 dev_priv->shared_dplls[i].id = i;
11904 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11905 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11906 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11907 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11908 dev_priv->shared_dplls[i].get_hw_state =
11909 ibx_pch_dpll_get_hw_state;
11910 }
11911 }
11912
11913 static void intel_shared_dpll_init(struct drm_device *dev)
11914 {
11915 struct drm_i915_private *dev_priv = dev->dev_private;
11916
11917 if (HAS_DDI(dev))
11918 intel_ddi_pll_init(dev);
11919 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11920 ibx_pch_dpll_init(dev);
11921 else
11922 dev_priv->num_shared_dpll = 0;
11923
11924 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11925 }
11926
11927 /**
11928 * intel_prepare_plane_fb - Prepare fb for usage on plane
11929 * @plane: drm plane to prepare for
11930 * @fb: framebuffer to prepare for presentation
11931 *
11932 * Prepares a framebuffer for usage on a display plane. Generally this
11933 * involves pinning the underlying object and updating the frontbuffer tracking
11934 * bits. Some older platforms need special physical address handling for
11935 * cursor planes.
11936 *
11937 * Returns 0 on success, negative error code on failure.
11938 */
11939 int
11940 intel_prepare_plane_fb(struct drm_plane *plane,
11941 struct drm_framebuffer *fb,
11942 const struct drm_plane_state *new_state)
11943 {
11944 struct drm_device *dev = plane->dev;
11945 struct intel_plane *intel_plane = to_intel_plane(plane);
11946 enum pipe pipe = intel_plane->pipe;
11947 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11948 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11949 unsigned frontbuffer_bits = 0;
11950 int ret = 0;
11951
11952 if (!obj)
11953 return 0;
11954
11955 switch (plane->type) {
11956 case DRM_PLANE_TYPE_PRIMARY:
11957 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
11958 break;
11959 case DRM_PLANE_TYPE_CURSOR:
11960 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
11961 break;
11962 case DRM_PLANE_TYPE_OVERLAY:
11963 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
11964 break;
11965 }
11966
11967 mutex_lock(&dev->struct_mutex);
11968
11969 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
11970 INTEL_INFO(dev)->cursor_needs_physical) {
11971 int align = IS_I830(dev) ? 16 * 1024 : 256;
11972 ret = i915_gem_object_attach_phys(obj, align);
11973 if (ret)
11974 DRM_DEBUG_KMS("failed to attach phys object\n");
11975 } else {
11976 ret = intel_pin_and_fence_fb_obj(plane, fb, NULL);
11977 }
11978
11979 if (ret == 0)
11980 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
11981
11982 mutex_unlock(&dev->struct_mutex);
11983
11984 return ret;
11985 }
11986
11987 /**
11988 * intel_cleanup_plane_fb - Cleans up an fb after plane use
11989 * @plane: drm plane to clean up for
11990 * @fb: old framebuffer that was on plane
11991 *
11992 * Cleans up a framebuffer that has just been removed from a plane.
11993 */
11994 void
11995 intel_cleanup_plane_fb(struct drm_plane *plane,
11996 struct drm_framebuffer *fb,
11997 const struct drm_plane_state *old_state)
11998 {
11999 struct drm_device *dev = plane->dev;
12000 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12001
12002 if (WARN_ON(!obj))
12003 return;
12004
12005 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
12006 !INTEL_INFO(dev)->cursor_needs_physical) {
12007 mutex_lock(&dev->struct_mutex);
12008 intel_unpin_fb_obj(obj);
12009 mutex_unlock(&dev->struct_mutex);
12010 }
12011 }
12012
12013 static int
12014 intel_check_primary_plane(struct drm_plane *plane,
12015 struct intel_plane_state *state)
12016 {
12017 struct drm_device *dev = plane->dev;
12018 struct drm_i915_private *dev_priv = dev->dev_private;
12019 struct drm_crtc *crtc = state->base.crtc;
12020 struct intel_crtc *intel_crtc;
12021 struct drm_framebuffer *fb = state->base.fb;
12022 struct drm_rect *dest = &state->dst;
12023 struct drm_rect *src = &state->src;
12024 const struct drm_rect *clip = &state->clip;
12025 int ret;
12026
12027 crtc = crtc ? crtc : plane->crtc;
12028 intel_crtc = to_intel_crtc(crtc);
12029
12030 ret = drm_plane_helper_check_update(plane, crtc, fb,
12031 src, dest, clip,
12032 DRM_PLANE_HELPER_NO_SCALING,
12033 DRM_PLANE_HELPER_NO_SCALING,
12034 false, true, &state->visible);
12035 if (ret)
12036 return ret;
12037
12038 if (intel_crtc->active) {
12039 intel_crtc->atomic.wait_for_flips = true;
12040
12041 /*
12042 * FBC does not work on some platforms for rotated
12043 * planes, so disable it when rotation is not 0 and
12044 * update it when rotation is set back to 0.
12045 *
12046 * FIXME: This is redundant with the fbc update done in
12047 * the primary plane enable function except that that
12048 * one is done too late. We eventually need to unify
12049 * this.
12050 */
12051 if (intel_crtc->primary_enabled &&
12052 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
12053 dev_priv->fbc.crtc == intel_crtc &&
12054 state->base.rotation != BIT(DRM_ROTATE_0)) {
12055 intel_crtc->atomic.disable_fbc = true;
12056 }
12057
12058 if (state->visible) {
12059 /*
12060 * BDW signals flip done immediately if the plane
12061 * is disabled, even if the plane enable is already
12062 * armed to occur at the next vblank :(
12063 */
12064 if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
12065 intel_crtc->atomic.wait_vblank = true;
12066 }
12067
12068 intel_crtc->atomic.fb_bits |=
12069 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
12070
12071 intel_crtc->atomic.update_fbc = true;
12072
12073 /* Update watermarks on tiling changes. */
12074 if (!plane->state->fb || !state->base.fb ||
12075 plane->state->fb->modifier[0] !=
12076 state->base.fb->modifier[0])
12077 intel_crtc->atomic.update_wm = true;
12078 }
12079
12080 return 0;
12081 }
12082
12083 static void
12084 intel_commit_primary_plane(struct drm_plane *plane,
12085 struct intel_plane_state *state)
12086 {
12087 struct drm_crtc *crtc = state->base.crtc;
12088 struct drm_framebuffer *fb = state->base.fb;
12089 struct drm_device *dev = plane->dev;
12090 struct drm_i915_private *dev_priv = dev->dev_private;
12091 struct intel_crtc *intel_crtc;
12092 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12093 struct intel_plane *intel_plane = to_intel_plane(plane);
12094 struct drm_rect *src = &state->src;
12095
12096 crtc = crtc ? crtc : plane->crtc;
12097 intel_crtc = to_intel_crtc(crtc);
12098
12099 plane->fb = fb;
12100 crtc->x = src->x1 >> 16;
12101 crtc->y = src->y1 >> 16;
12102
12103 intel_plane->obj = obj;
12104
12105 if (intel_crtc->active) {
12106 if (state->visible) {
12107 /* FIXME: kill this fastboot hack */
12108 intel_update_pipe_size(intel_crtc);
12109
12110 intel_crtc->primary_enabled = true;
12111
12112 dev_priv->display.update_primary_plane(crtc, plane->fb,
12113 crtc->x, crtc->y);
12114 } else {
12115 /*
12116 * If clipping results in a non-visible primary plane,
12117 * we'll disable the primary plane. Note that this is
12118 * a bit different than what happens if userspace
12119 * explicitly disables the plane by passing fb=0
12120 * because plane->fb still gets set and pinned.
12121 */
12122 intel_disable_primary_hw_plane(plane, crtc);
12123 }
12124 }
12125 }
12126
12127 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
12128 {
12129 struct drm_device *dev = crtc->dev;
12130 struct drm_i915_private *dev_priv = dev->dev_private;
12131 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12132 struct intel_plane *intel_plane;
12133 struct drm_plane *p;
12134 unsigned fb_bits = 0;
12135
12136 /* Track fb's for any planes being disabled */
12137 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
12138 intel_plane = to_intel_plane(p);
12139
12140 if (intel_crtc->atomic.disabled_planes &
12141 (1 << drm_plane_index(p))) {
12142 switch (p->type) {
12143 case DRM_PLANE_TYPE_PRIMARY:
12144 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
12145 break;
12146 case DRM_PLANE_TYPE_CURSOR:
12147 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
12148 break;
12149 case DRM_PLANE_TYPE_OVERLAY:
12150 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
12151 break;
12152 }
12153
12154 mutex_lock(&dev->struct_mutex);
12155 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
12156 mutex_unlock(&dev->struct_mutex);
12157 }
12158 }
12159
12160 if (intel_crtc->atomic.wait_for_flips)
12161 intel_crtc_wait_for_pending_flips(crtc);
12162
12163 if (intel_crtc->atomic.disable_fbc)
12164 intel_fbc_disable(dev);
12165
12166 if (intel_crtc->atomic.pre_disable_primary)
12167 intel_pre_disable_primary(crtc);
12168
12169 if (intel_crtc->atomic.update_wm)
12170 intel_update_watermarks(crtc);
12171
12172 intel_runtime_pm_get(dev_priv);
12173
12174 /* Perform vblank evasion around commit operation */
12175 if (intel_crtc->active)
12176 intel_crtc->atomic.evade =
12177 intel_pipe_update_start(intel_crtc,
12178 &intel_crtc->atomic.start_vbl_count);
12179 }
12180
12181 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
12182 {
12183 struct drm_device *dev = crtc->dev;
12184 struct drm_i915_private *dev_priv = dev->dev_private;
12185 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12186 struct drm_plane *p;
12187
12188 if (intel_crtc->atomic.evade)
12189 intel_pipe_update_end(intel_crtc,
12190 intel_crtc->atomic.start_vbl_count);
12191
12192 intel_runtime_pm_put(dev_priv);
12193
12194 if (intel_crtc->atomic.wait_vblank)
12195 intel_wait_for_vblank(dev, intel_crtc->pipe);
12196
12197 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
12198
12199 if (intel_crtc->atomic.update_fbc) {
12200 mutex_lock(&dev->struct_mutex);
12201 intel_fbc_update(dev);
12202 mutex_unlock(&dev->struct_mutex);
12203 }
12204
12205 if (intel_crtc->atomic.post_enable_primary)
12206 intel_post_enable_primary(crtc);
12207
12208 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
12209 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
12210 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
12211 false, false);
12212
12213 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
12214 }
12215
12216 /**
12217 * intel_plane_destroy - destroy a plane
12218 * @plane: plane to destroy
12219 *
12220 * Common destruction function for all types of planes (primary, cursor,
12221 * sprite).
12222 */
12223 void intel_plane_destroy(struct drm_plane *plane)
12224 {
12225 struct intel_plane *intel_plane = to_intel_plane(plane);
12226 drm_plane_cleanup(plane);
12227 kfree(intel_plane);
12228 }
12229
12230 const struct drm_plane_funcs intel_plane_funcs = {
12231 .update_plane = drm_plane_helper_update,
12232 .disable_plane = drm_plane_helper_disable,
12233 .destroy = intel_plane_destroy,
12234 .set_property = drm_atomic_helper_plane_set_property,
12235 .atomic_get_property = intel_plane_atomic_get_property,
12236 .atomic_set_property = intel_plane_atomic_set_property,
12237 .atomic_duplicate_state = intel_plane_duplicate_state,
12238 .atomic_destroy_state = intel_plane_destroy_state,
12239
12240 };
12241
12242 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
12243 int pipe)
12244 {
12245 struct intel_plane *primary;
12246 struct intel_plane_state *state;
12247 const uint32_t *intel_primary_formats;
12248 int num_formats;
12249
12250 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
12251 if (primary == NULL)
12252 return NULL;
12253
12254 state = intel_create_plane_state(&primary->base);
12255 if (!state) {
12256 kfree(primary);
12257 return NULL;
12258 }
12259 primary->base.state = &state->base;
12260
12261 primary->can_scale = false;
12262 primary->max_downscale = 1;
12263 primary->pipe = pipe;
12264 primary->plane = pipe;
12265 primary->check_plane = intel_check_primary_plane;
12266 primary->commit_plane = intel_commit_primary_plane;
12267 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
12268 primary->plane = !pipe;
12269
12270 if (INTEL_INFO(dev)->gen <= 3) {
12271 intel_primary_formats = intel_primary_formats_gen2;
12272 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
12273 } else {
12274 intel_primary_formats = intel_primary_formats_gen4;
12275 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
12276 }
12277
12278 drm_universal_plane_init(dev, &primary->base, 0,
12279 &intel_plane_funcs,
12280 intel_primary_formats, num_formats,
12281 DRM_PLANE_TYPE_PRIMARY);
12282
12283 if (INTEL_INFO(dev)->gen >= 4) {
12284 if (!dev->mode_config.rotation_property)
12285 dev->mode_config.rotation_property =
12286 drm_mode_create_rotation_property(dev,
12287 BIT(DRM_ROTATE_0) |
12288 BIT(DRM_ROTATE_180));
12289 if (dev->mode_config.rotation_property)
12290 drm_object_attach_property(&primary->base.base,
12291 dev->mode_config.rotation_property,
12292 state->base.rotation);
12293 }
12294
12295 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
12296
12297 return &primary->base;
12298 }
12299
12300 static int
12301 intel_check_cursor_plane(struct drm_plane *plane,
12302 struct intel_plane_state *state)
12303 {
12304 struct drm_crtc *crtc = state->base.crtc;
12305 struct drm_device *dev = plane->dev;
12306 struct drm_framebuffer *fb = state->base.fb;
12307 struct drm_rect *dest = &state->dst;
12308 struct drm_rect *src = &state->src;
12309 const struct drm_rect *clip = &state->clip;
12310 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12311 struct intel_crtc *intel_crtc;
12312 unsigned stride;
12313 int ret;
12314
12315 crtc = crtc ? crtc : plane->crtc;
12316 intel_crtc = to_intel_crtc(crtc);
12317
12318 ret = drm_plane_helper_check_update(plane, crtc, fb,
12319 src, dest, clip,
12320 DRM_PLANE_HELPER_NO_SCALING,
12321 DRM_PLANE_HELPER_NO_SCALING,
12322 true, true, &state->visible);
12323 if (ret)
12324 return ret;
12325
12326
12327 /* if we want to turn off the cursor ignore width and height */
12328 if (!obj)
12329 goto finish;
12330
12331 /* Check for which cursor types we support */
12332 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
12333 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
12334 state->base.crtc_w, state->base.crtc_h);
12335 return -EINVAL;
12336 }
12337
12338 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
12339 if (obj->base.size < stride * state->base.crtc_h) {
12340 DRM_DEBUG_KMS("buffer is too small\n");
12341 return -ENOMEM;
12342 }
12343
12344 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
12345 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12346 ret = -EINVAL;
12347 }
12348
12349 finish:
12350 if (intel_crtc->active) {
12351 if (plane->state->crtc_w != state->base.crtc_w)
12352 intel_crtc->atomic.update_wm = true;
12353
12354 intel_crtc->atomic.fb_bits |=
12355 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
12356 }
12357
12358 return ret;
12359 }
12360
12361 static void
12362 intel_commit_cursor_plane(struct drm_plane *plane,
12363 struct intel_plane_state *state)
12364 {
12365 struct drm_crtc *crtc = state->base.crtc;
12366 struct drm_device *dev = plane->dev;
12367 struct intel_crtc *intel_crtc;
12368 struct intel_plane *intel_plane = to_intel_plane(plane);
12369 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
12370 uint32_t addr;
12371
12372 crtc = crtc ? crtc : plane->crtc;
12373 intel_crtc = to_intel_crtc(crtc);
12374
12375 plane->fb = state->base.fb;
12376 crtc->cursor_x = state->base.crtc_x;
12377 crtc->cursor_y = state->base.crtc_y;
12378
12379 intel_plane->obj = obj;
12380
12381 if (intel_crtc->cursor_bo == obj)
12382 goto update;
12383
12384 if (!obj)
12385 addr = 0;
12386 else if (!INTEL_INFO(dev)->cursor_needs_physical)
12387 addr = i915_gem_obj_ggtt_offset(obj);
12388 else
12389 addr = obj->phys_handle->busaddr;
12390
12391 intel_crtc->cursor_addr = addr;
12392 intel_crtc->cursor_bo = obj;
12393 update:
12394
12395 if (intel_crtc->active)
12396 intel_crtc_update_cursor(crtc, state->visible);
12397 }
12398
12399 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12400 int pipe)
12401 {
12402 struct intel_plane *cursor;
12403 struct intel_plane_state *state;
12404
12405 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12406 if (cursor == NULL)
12407 return NULL;
12408
12409 state = intel_create_plane_state(&cursor->base);
12410 if (!state) {
12411 kfree(cursor);
12412 return NULL;
12413 }
12414 cursor->base.state = &state->base;
12415
12416 cursor->can_scale = false;
12417 cursor->max_downscale = 1;
12418 cursor->pipe = pipe;
12419 cursor->plane = pipe;
12420 cursor->check_plane = intel_check_cursor_plane;
12421 cursor->commit_plane = intel_commit_cursor_plane;
12422
12423 drm_universal_plane_init(dev, &cursor->base, 0,
12424 &intel_plane_funcs,
12425 intel_cursor_formats,
12426 ARRAY_SIZE(intel_cursor_formats),
12427 DRM_PLANE_TYPE_CURSOR);
12428
12429 if (INTEL_INFO(dev)->gen >= 4) {
12430 if (!dev->mode_config.rotation_property)
12431 dev->mode_config.rotation_property =
12432 drm_mode_create_rotation_property(dev,
12433 BIT(DRM_ROTATE_0) |
12434 BIT(DRM_ROTATE_180));
12435 if (dev->mode_config.rotation_property)
12436 drm_object_attach_property(&cursor->base.base,
12437 dev->mode_config.rotation_property,
12438 state->base.rotation);
12439 }
12440
12441 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
12442
12443 return &cursor->base;
12444 }
12445
12446 static void intel_crtc_init(struct drm_device *dev, int pipe)
12447 {
12448 struct drm_i915_private *dev_priv = dev->dev_private;
12449 struct intel_crtc *intel_crtc;
12450 struct intel_crtc_state *crtc_state = NULL;
12451 struct drm_plane *primary = NULL;
12452 struct drm_plane *cursor = NULL;
12453 int i, ret;
12454
12455 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12456 if (intel_crtc == NULL)
12457 return;
12458
12459 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
12460 if (!crtc_state)
12461 goto fail;
12462 intel_crtc_set_state(intel_crtc, crtc_state);
12463 crtc_state->base.crtc = &intel_crtc->base;
12464
12465 primary = intel_primary_plane_create(dev, pipe);
12466 if (!primary)
12467 goto fail;
12468
12469 cursor = intel_cursor_plane_create(dev, pipe);
12470 if (!cursor)
12471 goto fail;
12472
12473 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12474 cursor, &intel_crtc_funcs);
12475 if (ret)
12476 goto fail;
12477
12478 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12479 for (i = 0; i < 256; i++) {
12480 intel_crtc->lut_r[i] = i;
12481 intel_crtc->lut_g[i] = i;
12482 intel_crtc->lut_b[i] = i;
12483 }
12484
12485 /*
12486 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12487 * is hooked to pipe B. Hence we want plane A feeding pipe B.
12488 */
12489 intel_crtc->pipe = pipe;
12490 intel_crtc->plane = pipe;
12491 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12492 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12493 intel_crtc->plane = !pipe;
12494 }
12495
12496 intel_crtc->cursor_base = ~0;
12497 intel_crtc->cursor_cntl = ~0;
12498 intel_crtc->cursor_size = ~0;
12499
12500 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12501 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12502 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12503 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12504
12505 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
12506
12507 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12508
12509 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12510 return;
12511
12512 fail:
12513 if (primary)
12514 drm_plane_cleanup(primary);
12515 if (cursor)
12516 drm_plane_cleanup(cursor);
12517 kfree(crtc_state);
12518 kfree(intel_crtc);
12519 }
12520
12521 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12522 {
12523 struct drm_encoder *encoder = connector->base.encoder;
12524 struct drm_device *dev = connector->base.dev;
12525
12526 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12527
12528 if (!encoder || WARN_ON(!encoder->crtc))
12529 return INVALID_PIPE;
12530
12531 return to_intel_crtc(encoder->crtc)->pipe;
12532 }
12533
12534 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12535 struct drm_file *file)
12536 {
12537 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12538 struct drm_crtc *drmmode_crtc;
12539 struct intel_crtc *crtc;
12540
12541 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12542
12543 if (!drmmode_crtc) {
12544 DRM_ERROR("no such CRTC id\n");
12545 return -ENOENT;
12546 }
12547
12548 crtc = to_intel_crtc(drmmode_crtc);
12549 pipe_from_crtc_id->pipe = crtc->pipe;
12550
12551 return 0;
12552 }
12553
12554 static int intel_encoder_clones(struct intel_encoder *encoder)
12555 {
12556 struct drm_device *dev = encoder->base.dev;
12557 struct intel_encoder *source_encoder;
12558 int index_mask = 0;
12559 int entry = 0;
12560
12561 for_each_intel_encoder(dev, source_encoder) {
12562 if (encoders_cloneable(encoder, source_encoder))
12563 index_mask |= (1 << entry);
12564
12565 entry++;
12566 }
12567
12568 return index_mask;
12569 }
12570
12571 static bool has_edp_a(struct drm_device *dev)
12572 {
12573 struct drm_i915_private *dev_priv = dev->dev_private;
12574
12575 if (!IS_MOBILE(dev))
12576 return false;
12577
12578 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12579 return false;
12580
12581 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12582 return false;
12583
12584 return true;
12585 }
12586
12587 static bool intel_crt_present(struct drm_device *dev)
12588 {
12589 struct drm_i915_private *dev_priv = dev->dev_private;
12590
12591 if (INTEL_INFO(dev)->gen >= 9)
12592 return false;
12593
12594 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12595 return false;
12596
12597 if (IS_CHERRYVIEW(dev))
12598 return false;
12599
12600 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12601 return false;
12602
12603 return true;
12604 }
12605
12606 static void intel_setup_outputs(struct drm_device *dev)
12607 {
12608 struct drm_i915_private *dev_priv = dev->dev_private;
12609 struct intel_encoder *encoder;
12610 struct drm_connector *connector;
12611 bool dpd_is_edp = false;
12612
12613 intel_lvds_init(dev);
12614
12615 if (intel_crt_present(dev))
12616 intel_crt_init(dev);
12617
12618 if (HAS_DDI(dev)) {
12619 int found;
12620
12621 /*
12622 * Haswell uses DDI functions to detect digital outputs.
12623 * On SKL pre-D0 the strap isn't connected, so we assume
12624 * it's there.
12625 */
12626 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12627 /* WaIgnoreDDIAStrap: skl */
12628 if (found ||
12629 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
12630 intel_ddi_init(dev, PORT_A);
12631
12632 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12633 * register */
12634 found = I915_READ(SFUSE_STRAP);
12635
12636 if (found & SFUSE_STRAP_DDIB_DETECTED)
12637 intel_ddi_init(dev, PORT_B);
12638 if (found & SFUSE_STRAP_DDIC_DETECTED)
12639 intel_ddi_init(dev, PORT_C);
12640 if (found & SFUSE_STRAP_DDID_DETECTED)
12641 intel_ddi_init(dev, PORT_D);
12642 } else if (HAS_PCH_SPLIT(dev)) {
12643 int found;
12644 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12645
12646 if (has_edp_a(dev))
12647 intel_dp_init(dev, DP_A, PORT_A);
12648
12649 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12650 /* PCH SDVOB multiplex with HDMIB */
12651 found = intel_sdvo_init(dev, PCH_SDVOB, true);
12652 if (!found)
12653 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12654 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12655 intel_dp_init(dev, PCH_DP_B, PORT_B);
12656 }
12657
12658 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12659 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12660
12661 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12662 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12663
12664 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12665 intel_dp_init(dev, PCH_DP_C, PORT_C);
12666
12667 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12668 intel_dp_init(dev, PCH_DP_D, PORT_D);
12669 } else if (IS_VALLEYVIEW(dev)) {
12670 /*
12671 * The DP_DETECTED bit is the latched state of the DDC
12672 * SDA pin at boot. However since eDP doesn't require DDC
12673 * (no way to plug in a DP->HDMI dongle) the DDC pins for
12674 * eDP ports may have been muxed to an alternate function.
12675 * Thus we can't rely on the DP_DETECTED bit alone to detect
12676 * eDP ports. Consult the VBT as well as DP_DETECTED to
12677 * detect eDP ports.
12678 */
12679 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
12680 !intel_dp_is_edp(dev, PORT_B))
12681 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12682 PORT_B);
12683 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12684 intel_dp_is_edp(dev, PORT_B))
12685 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12686
12687 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
12688 !intel_dp_is_edp(dev, PORT_C))
12689 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12690 PORT_C);
12691 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12692 intel_dp_is_edp(dev, PORT_C))
12693 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12694
12695 if (IS_CHERRYVIEW(dev)) {
12696 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12697 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12698 PORT_D);
12699 /* eDP not supported on port D, so don't check VBT */
12700 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12701 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12702 }
12703
12704 intel_dsi_init(dev);
12705 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12706 bool found = false;
12707
12708 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12709 DRM_DEBUG_KMS("probing SDVOB\n");
12710 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12711 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12712 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12713 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12714 }
12715
12716 if (!found && SUPPORTS_INTEGRATED_DP(dev))
12717 intel_dp_init(dev, DP_B, PORT_B);
12718 }
12719
12720 /* Before G4X SDVOC doesn't have its own detect register */
12721
12722 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12723 DRM_DEBUG_KMS("probing SDVOC\n");
12724 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12725 }
12726
12727 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12728
12729 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12730 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12731 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12732 }
12733 if (SUPPORTS_INTEGRATED_DP(dev))
12734 intel_dp_init(dev, DP_C, PORT_C);
12735 }
12736
12737 if (SUPPORTS_INTEGRATED_DP(dev) &&
12738 (I915_READ(DP_D) & DP_DETECTED))
12739 intel_dp_init(dev, DP_D, PORT_D);
12740 } else if (IS_GEN2(dev))
12741 intel_dvo_init(dev);
12742
12743 if (SUPPORTS_TV(dev))
12744 intel_tv_init(dev);
12745
12746 /*
12747 * FIXME: We don't have full atomic support yet, but we want to be
12748 * able to enable/test plane updates via the atomic interface in the
12749 * meantime. However as soon as we flip DRIVER_ATOMIC on, the DRM core
12750 * will take some atomic codepaths to lookup properties during
12751 * drmModeGetConnector() that unconditionally dereference
12752 * connector->state.
12753 *
12754 * We create a dummy connector state here for each connector to ensure
12755 * the DRM core doesn't try to dereference a NULL connector->state.
12756 * The actual connector properties will never be updated or contain
12757 * useful information, but since we're doing this specifically for
12758 * testing/debug of the plane operations (and only when a specific
12759 * kernel module option is given), that shouldn't really matter.
12760 *
12761 * Once atomic support for crtc's + connectors lands, this loop should
12762 * be removed since we'll be setting up real connector state, which
12763 * will contain Intel-specific properties.
12764 */
12765 if (drm_core_check_feature(dev, DRIVER_ATOMIC)) {
12766 list_for_each_entry(connector,
12767 &dev->mode_config.connector_list,
12768 head) {
12769 if (!WARN_ON(connector->state)) {
12770 connector->state =
12771 kzalloc(sizeof(*connector->state),
12772 GFP_KERNEL);
12773 }
12774 }
12775 }
12776
12777 intel_psr_init(dev);
12778
12779 for_each_intel_encoder(dev, encoder) {
12780 encoder->base.possible_crtcs = encoder->crtc_mask;
12781 encoder->base.possible_clones =
12782 intel_encoder_clones(encoder);
12783 }
12784
12785 intel_init_pch_refclk(dev);
12786
12787 drm_helper_move_panel_connectors_to_head(dev);
12788 }
12789
12790 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12791 {
12792 struct drm_device *dev = fb->dev;
12793 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12794
12795 drm_framebuffer_cleanup(fb);
12796 mutex_lock(&dev->struct_mutex);
12797 WARN_ON(!intel_fb->obj->framebuffer_references--);
12798 drm_gem_object_unreference(&intel_fb->obj->base);
12799 mutex_unlock(&dev->struct_mutex);
12800 kfree(intel_fb);
12801 }
12802
12803 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12804 struct drm_file *file,
12805 unsigned int *handle)
12806 {
12807 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12808 struct drm_i915_gem_object *obj = intel_fb->obj;
12809
12810 return drm_gem_handle_create(file, &obj->base, handle);
12811 }
12812
12813 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12814 .destroy = intel_user_framebuffer_destroy,
12815 .create_handle = intel_user_framebuffer_create_handle,
12816 };
12817
12818 static
12819 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
12820 uint32_t pixel_format)
12821 {
12822 u32 gen = INTEL_INFO(dev)->gen;
12823
12824 if (gen >= 9) {
12825 /* "The stride in bytes must not exceed the of the size of 8K
12826 * pixels and 32K bytes."
12827 */
12828 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
12829 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
12830 return 32*1024;
12831 } else if (gen >= 4) {
12832 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
12833 return 16*1024;
12834 else
12835 return 32*1024;
12836 } else if (gen >= 3) {
12837 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
12838 return 8*1024;
12839 else
12840 return 16*1024;
12841 } else {
12842 /* XXX DSPC is limited to 4k tiled */
12843 return 8*1024;
12844 }
12845 }
12846
12847 static int intel_framebuffer_init(struct drm_device *dev,
12848 struct intel_framebuffer *intel_fb,
12849 struct drm_mode_fb_cmd2 *mode_cmd,
12850 struct drm_i915_gem_object *obj)
12851 {
12852 int aligned_height;
12853 int ret;
12854 u32 pitch_limit, stride_alignment;
12855
12856 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12857
12858 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
12859 /* Enforce that fb modifier and tiling mode match, but only for
12860 * X-tiled. This is needed for FBC. */
12861 if (!!(obj->tiling_mode == I915_TILING_X) !=
12862 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
12863 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
12864 return -EINVAL;
12865 }
12866 } else {
12867 if (obj->tiling_mode == I915_TILING_X)
12868 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
12869 else if (obj->tiling_mode == I915_TILING_Y) {
12870 DRM_DEBUG("No Y tiling for legacy addfb\n");
12871 return -EINVAL;
12872 }
12873 }
12874
12875 /* Passed in modifier sanity checking. */
12876 switch (mode_cmd->modifier[0]) {
12877 case I915_FORMAT_MOD_Y_TILED:
12878 case I915_FORMAT_MOD_Yf_TILED:
12879 if (INTEL_INFO(dev)->gen < 9) {
12880 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
12881 mode_cmd->modifier[0]);
12882 return -EINVAL;
12883 }
12884 case DRM_FORMAT_MOD_NONE:
12885 case I915_FORMAT_MOD_X_TILED:
12886 break;
12887 default:
12888 DRM_ERROR("Unsupported fb modifier 0x%llx!\n",
12889 mode_cmd->modifier[0]);
12890 return -EINVAL;
12891 }
12892
12893 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
12894 mode_cmd->pixel_format);
12895 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
12896 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
12897 mode_cmd->pitches[0], stride_alignment);
12898 return -EINVAL;
12899 }
12900
12901 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
12902 mode_cmd->pixel_format);
12903 if (mode_cmd->pitches[0] > pitch_limit) {
12904 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
12905 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
12906 "tiled" : "linear",
12907 mode_cmd->pitches[0], pitch_limit);
12908 return -EINVAL;
12909 }
12910
12911 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
12912 mode_cmd->pitches[0] != obj->stride) {
12913 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12914 mode_cmd->pitches[0], obj->stride);
12915 return -EINVAL;
12916 }
12917
12918 /* Reject formats not supported by any plane early. */
12919 switch (mode_cmd->pixel_format) {
12920 case DRM_FORMAT_C8:
12921 case DRM_FORMAT_RGB565:
12922 case DRM_FORMAT_XRGB8888:
12923 case DRM_FORMAT_ARGB8888:
12924 break;
12925 case DRM_FORMAT_XRGB1555:
12926 case DRM_FORMAT_ARGB1555:
12927 if (INTEL_INFO(dev)->gen > 3) {
12928 DRM_DEBUG("unsupported pixel format: %s\n",
12929 drm_get_format_name(mode_cmd->pixel_format));
12930 return -EINVAL;
12931 }
12932 break;
12933 case DRM_FORMAT_XBGR8888:
12934 case DRM_FORMAT_ABGR8888:
12935 case DRM_FORMAT_XRGB2101010:
12936 case DRM_FORMAT_ARGB2101010:
12937 case DRM_FORMAT_XBGR2101010:
12938 case DRM_FORMAT_ABGR2101010:
12939 if (INTEL_INFO(dev)->gen < 4) {
12940 DRM_DEBUG("unsupported pixel format: %s\n",
12941 drm_get_format_name(mode_cmd->pixel_format));
12942 return -EINVAL;
12943 }
12944 break;
12945 case DRM_FORMAT_YUYV:
12946 case DRM_FORMAT_UYVY:
12947 case DRM_FORMAT_YVYU:
12948 case DRM_FORMAT_VYUY:
12949 if (INTEL_INFO(dev)->gen < 5) {
12950 DRM_DEBUG("unsupported pixel format: %s\n",
12951 drm_get_format_name(mode_cmd->pixel_format));
12952 return -EINVAL;
12953 }
12954 break;
12955 default:
12956 DRM_DEBUG("unsupported pixel format: %s\n",
12957 drm_get_format_name(mode_cmd->pixel_format));
12958 return -EINVAL;
12959 }
12960
12961 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12962 if (mode_cmd->offsets[0] != 0)
12963 return -EINVAL;
12964
12965 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
12966 mode_cmd->pixel_format,
12967 mode_cmd->modifier[0]);
12968 /* FIXME drm helper for size checks (especially planar formats)? */
12969 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12970 return -EINVAL;
12971
12972 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12973 intel_fb->obj = obj;
12974 intel_fb->obj->framebuffer_references++;
12975
12976 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12977 if (ret) {
12978 DRM_ERROR("framebuffer init failed %d\n", ret);
12979 return ret;
12980 }
12981
12982 return 0;
12983 }
12984
12985 static struct drm_framebuffer *
12986 intel_user_framebuffer_create(struct drm_device *dev,
12987 struct drm_file *filp,
12988 struct drm_mode_fb_cmd2 *mode_cmd)
12989 {
12990 struct drm_i915_gem_object *obj;
12991
12992 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12993 mode_cmd->handles[0]));
12994 if (&obj->base == NULL)
12995 return ERR_PTR(-ENOENT);
12996
12997 return intel_framebuffer_create(dev, mode_cmd, obj);
12998 }
12999
13000 #ifndef CONFIG_DRM_I915_FBDEV
13001 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
13002 {
13003 }
13004 #endif
13005
13006 static const struct drm_mode_config_funcs intel_mode_funcs = {
13007 .fb_create = intel_user_framebuffer_create,
13008 .output_poll_changed = intel_fbdev_output_poll_changed,
13009 .atomic_check = intel_atomic_check,
13010 .atomic_commit = intel_atomic_commit,
13011 };
13012
13013 /* Set up chip specific display functions */
13014 static void intel_init_display(struct drm_device *dev)
13015 {
13016 struct drm_i915_private *dev_priv = dev->dev_private;
13017
13018 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
13019 dev_priv->display.find_dpll = g4x_find_best_dpll;
13020 else if (IS_CHERRYVIEW(dev))
13021 dev_priv->display.find_dpll = chv_find_best_dpll;
13022 else if (IS_VALLEYVIEW(dev))
13023 dev_priv->display.find_dpll = vlv_find_best_dpll;
13024 else if (IS_PINEVIEW(dev))
13025 dev_priv->display.find_dpll = pnv_find_best_dpll;
13026 else
13027 dev_priv->display.find_dpll = i9xx_find_best_dpll;
13028
13029 if (INTEL_INFO(dev)->gen >= 9) {
13030 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
13031 dev_priv->display.get_initial_plane_config =
13032 skylake_get_initial_plane_config;
13033 dev_priv->display.crtc_compute_clock =
13034 haswell_crtc_compute_clock;
13035 dev_priv->display.crtc_enable = haswell_crtc_enable;
13036 dev_priv->display.crtc_disable = haswell_crtc_disable;
13037 dev_priv->display.off = ironlake_crtc_off;
13038 dev_priv->display.update_primary_plane =
13039 skylake_update_primary_plane;
13040 } else if (HAS_DDI(dev)) {
13041 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
13042 dev_priv->display.get_initial_plane_config =
13043 ironlake_get_initial_plane_config;
13044 dev_priv->display.crtc_compute_clock =
13045 haswell_crtc_compute_clock;
13046 dev_priv->display.crtc_enable = haswell_crtc_enable;
13047 dev_priv->display.crtc_disable = haswell_crtc_disable;
13048 dev_priv->display.off = ironlake_crtc_off;
13049 dev_priv->display.update_primary_plane =
13050 ironlake_update_primary_plane;
13051 } else if (HAS_PCH_SPLIT(dev)) {
13052 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
13053 dev_priv->display.get_initial_plane_config =
13054 ironlake_get_initial_plane_config;
13055 dev_priv->display.crtc_compute_clock =
13056 ironlake_crtc_compute_clock;
13057 dev_priv->display.crtc_enable = ironlake_crtc_enable;
13058 dev_priv->display.crtc_disable = ironlake_crtc_disable;
13059 dev_priv->display.off = ironlake_crtc_off;
13060 dev_priv->display.update_primary_plane =
13061 ironlake_update_primary_plane;
13062 } else if (IS_VALLEYVIEW(dev)) {
13063 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13064 dev_priv->display.get_initial_plane_config =
13065 i9xx_get_initial_plane_config;
13066 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
13067 dev_priv->display.crtc_enable = valleyview_crtc_enable;
13068 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13069 dev_priv->display.off = i9xx_crtc_off;
13070 dev_priv->display.update_primary_plane =
13071 i9xx_update_primary_plane;
13072 } else {
13073 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13074 dev_priv->display.get_initial_plane_config =
13075 i9xx_get_initial_plane_config;
13076 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
13077 dev_priv->display.crtc_enable = i9xx_crtc_enable;
13078 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13079 dev_priv->display.off = i9xx_crtc_off;
13080 dev_priv->display.update_primary_plane =
13081 i9xx_update_primary_plane;
13082 }
13083
13084 /* Returns the core display clock speed */
13085 if (IS_VALLEYVIEW(dev))
13086 dev_priv->display.get_display_clock_speed =
13087 valleyview_get_display_clock_speed;
13088 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
13089 dev_priv->display.get_display_clock_speed =
13090 i945_get_display_clock_speed;
13091 else if (IS_I915G(dev))
13092 dev_priv->display.get_display_clock_speed =
13093 i915_get_display_clock_speed;
13094 else if (IS_I945GM(dev) || IS_845G(dev))
13095 dev_priv->display.get_display_clock_speed =
13096 i9xx_misc_get_display_clock_speed;
13097 else if (IS_PINEVIEW(dev))
13098 dev_priv->display.get_display_clock_speed =
13099 pnv_get_display_clock_speed;
13100 else if (IS_I915GM(dev))
13101 dev_priv->display.get_display_clock_speed =
13102 i915gm_get_display_clock_speed;
13103 else if (IS_I865G(dev))
13104 dev_priv->display.get_display_clock_speed =
13105 i865_get_display_clock_speed;
13106 else if (IS_I85X(dev))
13107 dev_priv->display.get_display_clock_speed =
13108 i855_get_display_clock_speed;
13109 else /* 852, 830 */
13110 dev_priv->display.get_display_clock_speed =
13111 i830_get_display_clock_speed;
13112
13113 if (IS_GEN5(dev)) {
13114 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
13115 } else if (IS_GEN6(dev)) {
13116 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
13117 } else if (IS_IVYBRIDGE(dev)) {
13118 /* FIXME: detect B0+ stepping and use auto training */
13119 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
13120 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
13121 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
13122 } else if (IS_VALLEYVIEW(dev)) {
13123 dev_priv->display.modeset_global_resources =
13124 valleyview_modeset_global_resources;
13125 }
13126
13127 switch (INTEL_INFO(dev)->gen) {
13128 case 2:
13129 dev_priv->display.queue_flip = intel_gen2_queue_flip;
13130 break;
13131
13132 case 3:
13133 dev_priv->display.queue_flip = intel_gen3_queue_flip;
13134 break;
13135
13136 case 4:
13137 case 5:
13138 dev_priv->display.queue_flip = intel_gen4_queue_flip;
13139 break;
13140
13141 case 6:
13142 dev_priv->display.queue_flip = intel_gen6_queue_flip;
13143 break;
13144 case 7:
13145 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
13146 dev_priv->display.queue_flip = intel_gen7_queue_flip;
13147 break;
13148 case 9:
13149 /* Drop through - unsupported since execlist only. */
13150 default:
13151 /* Default just returns -ENODEV to indicate unsupported */
13152 dev_priv->display.queue_flip = intel_default_queue_flip;
13153 }
13154
13155 intel_panel_init_backlight_funcs(dev);
13156
13157 mutex_init(&dev_priv->pps_mutex);
13158 }
13159
13160 /*
13161 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
13162 * resume, or other times. This quirk makes sure that's the case for
13163 * affected systems.
13164 */
13165 static void quirk_pipea_force(struct drm_device *dev)
13166 {
13167 struct drm_i915_private *dev_priv = dev->dev_private;
13168
13169 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
13170 DRM_INFO("applying pipe a force quirk\n");
13171 }
13172
13173 static void quirk_pipeb_force(struct drm_device *dev)
13174 {
13175 struct drm_i915_private *dev_priv = dev->dev_private;
13176
13177 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
13178 DRM_INFO("applying pipe b force quirk\n");
13179 }
13180
13181 /*
13182 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
13183 */
13184 static void quirk_ssc_force_disable(struct drm_device *dev)
13185 {
13186 struct drm_i915_private *dev_priv = dev->dev_private;
13187 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
13188 DRM_INFO("applying lvds SSC disable quirk\n");
13189 }
13190
13191 /*
13192 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
13193 * brightness value
13194 */
13195 static void quirk_invert_brightness(struct drm_device *dev)
13196 {
13197 struct drm_i915_private *dev_priv = dev->dev_private;
13198 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
13199 DRM_INFO("applying inverted panel brightness quirk\n");
13200 }
13201
13202 /* Some VBT's incorrectly indicate no backlight is present */
13203 static void quirk_backlight_present(struct drm_device *dev)
13204 {
13205 struct drm_i915_private *dev_priv = dev->dev_private;
13206 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
13207 DRM_INFO("applying backlight present quirk\n");
13208 }
13209
13210 struct intel_quirk {
13211 int device;
13212 int subsystem_vendor;
13213 int subsystem_device;
13214 void (*hook)(struct drm_device *dev);
13215 };
13216
13217 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
13218 struct intel_dmi_quirk {
13219 void (*hook)(struct drm_device *dev);
13220 const struct dmi_system_id (*dmi_id_list)[];
13221 };
13222
13223 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
13224 {
13225 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
13226 return 1;
13227 }
13228
13229 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
13230 {
13231 .dmi_id_list = &(const struct dmi_system_id[]) {
13232 {
13233 .callback = intel_dmi_reverse_brightness,
13234 .ident = "NCR Corporation",
13235 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
13236 DMI_MATCH(DMI_PRODUCT_NAME, ""),
13237 },
13238 },
13239 { } /* terminating entry */
13240 },
13241 .hook = quirk_invert_brightness,
13242 },
13243 };
13244
13245 static struct intel_quirk intel_quirks[] = {
13246 /* HP Mini needs pipe A force quirk (LP: #322104) */
13247 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
13248
13249 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
13250 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
13251
13252 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
13253 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
13254
13255 /* 830 needs to leave pipe A & dpll A up */
13256 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
13257
13258 /* 830 needs to leave pipe B & dpll B up */
13259 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
13260
13261 /* Lenovo U160 cannot use SSC on LVDS */
13262 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
13263
13264 /* Sony Vaio Y cannot use SSC on LVDS */
13265 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
13266
13267 /* Acer Aspire 5734Z must invert backlight brightness */
13268 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
13269
13270 /* Acer/eMachines G725 */
13271 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
13272
13273 /* Acer/eMachines e725 */
13274 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
13275
13276 /* Acer/Packard Bell NCL20 */
13277 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
13278
13279 /* Acer Aspire 4736Z */
13280 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
13281
13282 /* Acer Aspire 5336 */
13283 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
13284
13285 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13286 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
13287
13288 /* Acer C720 Chromebook (Core i3 4005U) */
13289 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
13290
13291 /* Apple Macbook 2,1 (Core 2 T7400) */
13292 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
13293
13294 /* Toshiba CB35 Chromebook (Celeron 2955U) */
13295 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
13296
13297 /* HP Chromebook 14 (Celeron 2955U) */
13298 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
13299
13300 /* Dell Chromebook 11 */
13301 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
13302 };
13303
13304 static void intel_init_quirks(struct drm_device *dev)
13305 {
13306 struct pci_dev *d = dev->pdev;
13307 int i;
13308
13309 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
13310 struct intel_quirk *q = &intel_quirks[i];
13311
13312 if (d->device == q->device &&
13313 (d->subsystem_vendor == q->subsystem_vendor ||
13314 q->subsystem_vendor == PCI_ANY_ID) &&
13315 (d->subsystem_device == q->subsystem_device ||
13316 q->subsystem_device == PCI_ANY_ID))
13317 q->hook(dev);
13318 }
13319 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
13320 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
13321 intel_dmi_quirks[i].hook(dev);
13322 }
13323 }
13324
13325 /* Disable the VGA plane that we never use */
13326 static void i915_disable_vga(struct drm_device *dev)
13327 {
13328 struct drm_i915_private *dev_priv = dev->dev_private;
13329 u8 sr1;
13330 u32 vga_reg = i915_vgacntrl_reg(dev);
13331
13332 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
13333 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
13334 outb(SR01, VGA_SR_INDEX);
13335 sr1 = inb(VGA_SR_DATA);
13336 outb(sr1 | 1<<5, VGA_SR_DATA);
13337 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
13338 udelay(300);
13339
13340 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
13341 POSTING_READ(vga_reg);
13342 }
13343
13344 void intel_modeset_init_hw(struct drm_device *dev)
13345 {
13346 intel_prepare_ddi(dev);
13347
13348 if (IS_VALLEYVIEW(dev))
13349 vlv_update_cdclk(dev);
13350
13351 intel_init_clock_gating(dev);
13352
13353 intel_enable_gt_powersave(dev);
13354 }
13355
13356 void intel_modeset_init(struct drm_device *dev)
13357 {
13358 struct drm_i915_private *dev_priv = dev->dev_private;
13359 int sprite, ret;
13360 enum pipe pipe;
13361 struct intel_crtc *crtc;
13362
13363 drm_mode_config_init(dev);
13364
13365 dev->mode_config.min_width = 0;
13366 dev->mode_config.min_height = 0;
13367
13368 dev->mode_config.preferred_depth = 24;
13369 dev->mode_config.prefer_shadow = 1;
13370
13371 dev->mode_config.allow_fb_modifiers = true;
13372
13373 dev->mode_config.funcs = &intel_mode_funcs;
13374
13375 intel_init_quirks(dev);
13376
13377 intel_init_pm(dev);
13378
13379 if (INTEL_INFO(dev)->num_pipes == 0)
13380 return;
13381
13382 intel_init_display(dev);
13383 intel_init_audio(dev);
13384
13385 if (IS_GEN2(dev)) {
13386 dev->mode_config.max_width = 2048;
13387 dev->mode_config.max_height = 2048;
13388 } else if (IS_GEN3(dev)) {
13389 dev->mode_config.max_width = 4096;
13390 dev->mode_config.max_height = 4096;
13391 } else {
13392 dev->mode_config.max_width = 8192;
13393 dev->mode_config.max_height = 8192;
13394 }
13395
13396 if (IS_845G(dev) || IS_I865G(dev)) {
13397 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13398 dev->mode_config.cursor_height = 1023;
13399 } else if (IS_GEN2(dev)) {
13400 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13401 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13402 } else {
13403 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13404 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13405 }
13406
13407 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
13408
13409 DRM_DEBUG_KMS("%d display pipe%s available.\n",
13410 INTEL_INFO(dev)->num_pipes,
13411 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
13412
13413 for_each_pipe(dev_priv, pipe) {
13414 intel_crtc_init(dev, pipe);
13415 for_each_sprite(dev_priv, pipe, sprite) {
13416 ret = intel_plane_init(dev, pipe, sprite);
13417 if (ret)
13418 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13419 pipe_name(pipe), sprite_name(pipe, sprite), ret);
13420 }
13421 }
13422
13423 intel_init_dpio(dev);
13424
13425 intel_shared_dpll_init(dev);
13426
13427 /* Just disable it once at startup */
13428 i915_disable_vga(dev);
13429 intel_setup_outputs(dev);
13430
13431 /* Just in case the BIOS is doing something questionable. */
13432 intel_fbc_disable(dev);
13433
13434 drm_modeset_lock_all(dev);
13435 intel_modeset_setup_hw_state(dev, false);
13436 drm_modeset_unlock_all(dev);
13437
13438 for_each_intel_crtc(dev, crtc) {
13439 if (!crtc->active)
13440 continue;
13441
13442 /*
13443 * Note that reserving the BIOS fb up front prevents us
13444 * from stuffing other stolen allocations like the ring
13445 * on top. This prevents some ugliness at boot time, and
13446 * can even allow for smooth boot transitions if the BIOS
13447 * fb is large enough for the active pipe configuration.
13448 */
13449 if (dev_priv->display.get_initial_plane_config) {
13450 dev_priv->display.get_initial_plane_config(crtc,
13451 &crtc->plane_config);
13452 /*
13453 * If the fb is shared between multiple heads, we'll
13454 * just get the first one.
13455 */
13456 intel_find_plane_obj(crtc, &crtc->plane_config);
13457 }
13458 }
13459 }
13460
13461 static void intel_enable_pipe_a(struct drm_device *dev)
13462 {
13463 struct intel_connector *connector;
13464 struct drm_connector *crt = NULL;
13465 struct intel_load_detect_pipe load_detect_temp;
13466 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13467
13468 /* We can't just switch on the pipe A, we need to set things up with a
13469 * proper mode and output configuration. As a gross hack, enable pipe A
13470 * by enabling the load detect pipe once. */
13471 for_each_intel_connector(dev, connector) {
13472 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13473 crt = &connector->base;
13474 break;
13475 }
13476 }
13477
13478 if (!crt)
13479 return;
13480
13481 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13482 intel_release_load_detect_pipe(crt, &load_detect_temp);
13483 }
13484
13485 static bool
13486 intel_check_plane_mapping(struct intel_crtc *crtc)
13487 {
13488 struct drm_device *dev = crtc->base.dev;
13489 struct drm_i915_private *dev_priv = dev->dev_private;
13490 u32 reg, val;
13491
13492 if (INTEL_INFO(dev)->num_pipes == 1)
13493 return true;
13494
13495 reg = DSPCNTR(!crtc->plane);
13496 val = I915_READ(reg);
13497
13498 if ((val & DISPLAY_PLANE_ENABLE) &&
13499 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13500 return false;
13501
13502 return true;
13503 }
13504
13505 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13506 {
13507 struct drm_device *dev = crtc->base.dev;
13508 struct drm_i915_private *dev_priv = dev->dev_private;
13509 u32 reg;
13510
13511 /* Clear any frame start delays used for debugging left by the BIOS */
13512 reg = PIPECONF(crtc->config->cpu_transcoder);
13513 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13514
13515 /* restore vblank interrupts to correct state */
13516 drm_crtc_vblank_reset(&crtc->base);
13517 if (crtc->active) {
13518 update_scanline_offset(crtc);
13519 drm_crtc_vblank_on(&crtc->base);
13520 }
13521
13522 /* We need to sanitize the plane -> pipe mapping first because this will
13523 * disable the crtc (and hence change the state) if it is wrong. Note
13524 * that gen4+ has a fixed plane -> pipe mapping. */
13525 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13526 struct intel_connector *connector;
13527 bool plane;
13528
13529 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13530 crtc->base.base.id);
13531
13532 /* Pipe has the wrong plane attached and the plane is active.
13533 * Temporarily change the plane mapping and disable everything
13534 * ... */
13535 plane = crtc->plane;
13536 crtc->plane = !plane;
13537 crtc->primary_enabled = true;
13538 dev_priv->display.crtc_disable(&crtc->base);
13539 crtc->plane = plane;
13540
13541 /* ... and break all links. */
13542 for_each_intel_connector(dev, connector) {
13543 if (connector->encoder->base.crtc != &crtc->base)
13544 continue;
13545
13546 connector->base.dpms = DRM_MODE_DPMS_OFF;
13547 connector->base.encoder = NULL;
13548 }
13549 /* multiple connectors may have the same encoder:
13550 * handle them and break crtc link separately */
13551 for_each_intel_connector(dev, connector)
13552 if (connector->encoder->base.crtc == &crtc->base) {
13553 connector->encoder->base.crtc = NULL;
13554 connector->encoder->connectors_active = false;
13555 }
13556
13557 WARN_ON(crtc->active);
13558 crtc->base.state->enable = false;
13559 crtc->base.enabled = false;
13560 }
13561
13562 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13563 crtc->pipe == PIPE_A && !crtc->active) {
13564 /* BIOS forgot to enable pipe A, this mostly happens after
13565 * resume. Force-enable the pipe to fix this, the update_dpms
13566 * call below we restore the pipe to the right state, but leave
13567 * the required bits on. */
13568 intel_enable_pipe_a(dev);
13569 }
13570
13571 /* Adjust the state of the output pipe according to whether we
13572 * have active connectors/encoders. */
13573 intel_crtc_update_dpms(&crtc->base);
13574
13575 if (crtc->active != crtc->base.state->enable) {
13576 struct intel_encoder *encoder;
13577
13578 /* This can happen either due to bugs in the get_hw_state
13579 * functions or because the pipe is force-enabled due to the
13580 * pipe A quirk. */
13581 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13582 crtc->base.base.id,
13583 crtc->base.state->enable ? "enabled" : "disabled",
13584 crtc->active ? "enabled" : "disabled");
13585
13586 crtc->base.state->enable = crtc->active;
13587 crtc->base.enabled = crtc->active;
13588
13589 /* Because we only establish the connector -> encoder ->
13590 * crtc links if something is active, this means the
13591 * crtc is now deactivated. Break the links. connector
13592 * -> encoder links are only establish when things are
13593 * actually up, hence no need to break them. */
13594 WARN_ON(crtc->active);
13595
13596 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13597 WARN_ON(encoder->connectors_active);
13598 encoder->base.crtc = NULL;
13599 }
13600 }
13601
13602 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13603 /*
13604 * We start out with underrun reporting disabled to avoid races.
13605 * For correct bookkeeping mark this on active crtcs.
13606 *
13607 * Also on gmch platforms we dont have any hardware bits to
13608 * disable the underrun reporting. Which means we need to start
13609 * out with underrun reporting disabled also on inactive pipes,
13610 * since otherwise we'll complain about the garbage we read when
13611 * e.g. coming up after runtime pm.
13612 *
13613 * No protection against concurrent access is required - at
13614 * worst a fifo underrun happens which also sets this to false.
13615 */
13616 crtc->cpu_fifo_underrun_disabled = true;
13617 crtc->pch_fifo_underrun_disabled = true;
13618 }
13619 }
13620
13621 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13622 {
13623 struct intel_connector *connector;
13624 struct drm_device *dev = encoder->base.dev;
13625
13626 /* We need to check both for a crtc link (meaning that the
13627 * encoder is active and trying to read from a pipe) and the
13628 * pipe itself being active. */
13629 bool has_active_crtc = encoder->base.crtc &&
13630 to_intel_crtc(encoder->base.crtc)->active;
13631
13632 if (encoder->connectors_active && !has_active_crtc) {
13633 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13634 encoder->base.base.id,
13635 encoder->base.name);
13636
13637 /* Connector is active, but has no active pipe. This is
13638 * fallout from our resume register restoring. Disable
13639 * the encoder manually again. */
13640 if (encoder->base.crtc) {
13641 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13642 encoder->base.base.id,
13643 encoder->base.name);
13644 encoder->disable(encoder);
13645 if (encoder->post_disable)
13646 encoder->post_disable(encoder);
13647 }
13648 encoder->base.crtc = NULL;
13649 encoder->connectors_active = false;
13650
13651 /* Inconsistent output/port/pipe state happens presumably due to
13652 * a bug in one of the get_hw_state functions. Or someplace else
13653 * in our code, like the register restore mess on resume. Clamp
13654 * things to off as a safer default. */
13655 for_each_intel_connector(dev, connector) {
13656 if (connector->encoder != encoder)
13657 continue;
13658 connector->base.dpms = DRM_MODE_DPMS_OFF;
13659 connector->base.encoder = NULL;
13660 }
13661 }
13662 /* Enabled encoders without active connectors will be fixed in
13663 * the crtc fixup. */
13664 }
13665
13666 void i915_redisable_vga_power_on(struct drm_device *dev)
13667 {
13668 struct drm_i915_private *dev_priv = dev->dev_private;
13669 u32 vga_reg = i915_vgacntrl_reg(dev);
13670
13671 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13672 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13673 i915_disable_vga(dev);
13674 }
13675 }
13676
13677 void i915_redisable_vga(struct drm_device *dev)
13678 {
13679 struct drm_i915_private *dev_priv = dev->dev_private;
13680
13681 /* This function can be called both from intel_modeset_setup_hw_state or
13682 * at a very early point in our resume sequence, where the power well
13683 * structures are not yet restored. Since this function is at a very
13684 * paranoid "someone might have enabled VGA while we were not looking"
13685 * level, just check if the power well is enabled instead of trying to
13686 * follow the "don't touch the power well if we don't need it" policy
13687 * the rest of the driver uses. */
13688 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13689 return;
13690
13691 i915_redisable_vga_power_on(dev);
13692 }
13693
13694 static bool primary_get_hw_state(struct intel_crtc *crtc)
13695 {
13696 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13697
13698 if (!crtc->active)
13699 return false;
13700
13701 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13702 }
13703
13704 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13705 {
13706 struct drm_i915_private *dev_priv = dev->dev_private;
13707 enum pipe pipe;
13708 struct intel_crtc *crtc;
13709 struct intel_encoder *encoder;
13710 struct intel_connector *connector;
13711 int i;
13712
13713 for_each_intel_crtc(dev, crtc) {
13714 memset(crtc->config, 0, sizeof(*crtc->config));
13715
13716 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13717
13718 crtc->active = dev_priv->display.get_pipe_config(crtc,
13719 crtc->config);
13720
13721 crtc->base.state->enable = crtc->active;
13722 crtc->base.enabled = crtc->active;
13723 crtc->primary_enabled = primary_get_hw_state(crtc);
13724
13725 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13726 crtc->base.base.id,
13727 crtc->active ? "enabled" : "disabled");
13728 }
13729
13730 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13731 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13732
13733 pll->on = pll->get_hw_state(dev_priv, pll,
13734 &pll->config.hw_state);
13735 pll->active = 0;
13736 pll->config.crtc_mask = 0;
13737 for_each_intel_crtc(dev, crtc) {
13738 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
13739 pll->active++;
13740 pll->config.crtc_mask |= 1 << crtc->pipe;
13741 }
13742 }
13743
13744 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13745 pll->name, pll->config.crtc_mask, pll->on);
13746
13747 if (pll->config.crtc_mask)
13748 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13749 }
13750
13751 for_each_intel_encoder(dev, encoder) {
13752 pipe = 0;
13753
13754 if (encoder->get_hw_state(encoder, &pipe)) {
13755 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13756 encoder->base.crtc = &crtc->base;
13757 encoder->get_config(encoder, crtc->config);
13758 } else {
13759 encoder->base.crtc = NULL;
13760 }
13761
13762 encoder->connectors_active = false;
13763 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13764 encoder->base.base.id,
13765 encoder->base.name,
13766 encoder->base.crtc ? "enabled" : "disabled",
13767 pipe_name(pipe));
13768 }
13769
13770 for_each_intel_connector(dev, connector) {
13771 if (connector->get_hw_state(connector)) {
13772 connector->base.dpms = DRM_MODE_DPMS_ON;
13773 connector->encoder->connectors_active = true;
13774 connector->base.encoder = &connector->encoder->base;
13775 } else {
13776 connector->base.dpms = DRM_MODE_DPMS_OFF;
13777 connector->base.encoder = NULL;
13778 }
13779 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13780 connector->base.base.id,
13781 connector->base.name,
13782 connector->base.encoder ? "enabled" : "disabled");
13783 }
13784 }
13785
13786 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13787 * and i915 state tracking structures. */
13788 void intel_modeset_setup_hw_state(struct drm_device *dev,
13789 bool force_restore)
13790 {
13791 struct drm_i915_private *dev_priv = dev->dev_private;
13792 enum pipe pipe;
13793 struct intel_crtc *crtc;
13794 struct intel_encoder *encoder;
13795 int i;
13796
13797 intel_modeset_readout_hw_state(dev);
13798
13799 /*
13800 * Now that we have the config, copy it to each CRTC struct
13801 * Note that this could go away if we move to using crtc_config
13802 * checking everywhere.
13803 */
13804 for_each_intel_crtc(dev, crtc) {
13805 if (crtc->active && i915.fastboot) {
13806 intel_mode_from_pipe_config(&crtc->base.mode,
13807 crtc->config);
13808 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13809 crtc->base.base.id);
13810 drm_mode_debug_printmodeline(&crtc->base.mode);
13811 }
13812 }
13813
13814 /* HW state is read out, now we need to sanitize this mess. */
13815 for_each_intel_encoder(dev, encoder) {
13816 intel_sanitize_encoder(encoder);
13817 }
13818
13819 for_each_pipe(dev_priv, pipe) {
13820 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13821 intel_sanitize_crtc(crtc);
13822 intel_dump_pipe_config(crtc, crtc->config,
13823 "[setup_hw_state]");
13824 }
13825
13826 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13827 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13828
13829 if (!pll->on || pll->active)
13830 continue;
13831
13832 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13833
13834 pll->disable(dev_priv, pll);
13835 pll->on = false;
13836 }
13837
13838 if (IS_GEN9(dev))
13839 skl_wm_get_hw_state(dev);
13840 else if (HAS_PCH_SPLIT(dev))
13841 ilk_wm_get_hw_state(dev);
13842
13843 if (force_restore) {
13844 i915_redisable_vga(dev);
13845
13846 /*
13847 * We need to use raw interfaces for restoring state to avoid
13848 * checking (bogus) intermediate states.
13849 */
13850 for_each_pipe(dev_priv, pipe) {
13851 struct drm_crtc *crtc =
13852 dev_priv->pipe_to_crtc_mapping[pipe];
13853
13854 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13855 crtc->primary->fb);
13856 }
13857 } else {
13858 intel_modeset_update_staged_output_state(dev);
13859 }
13860
13861 intel_modeset_check_state(dev);
13862 }
13863
13864 void intel_modeset_gem_init(struct drm_device *dev)
13865 {
13866 struct drm_i915_private *dev_priv = dev->dev_private;
13867 struct drm_crtc *c;
13868 struct drm_i915_gem_object *obj;
13869
13870 mutex_lock(&dev->struct_mutex);
13871 intel_init_gt_powersave(dev);
13872 mutex_unlock(&dev->struct_mutex);
13873
13874 /*
13875 * There may be no VBT; and if the BIOS enabled SSC we can
13876 * just keep using it to avoid unnecessary flicker. Whereas if the
13877 * BIOS isn't using it, don't assume it will work even if the VBT
13878 * indicates as much.
13879 */
13880 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13881 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
13882 DREF_SSC1_ENABLE);
13883
13884 intel_modeset_init_hw(dev);
13885
13886 intel_setup_overlay(dev);
13887
13888 /*
13889 * Make sure any fbs we allocated at startup are properly
13890 * pinned & fenced. When we do the allocation it's too early
13891 * for this.
13892 */
13893 mutex_lock(&dev->struct_mutex);
13894 for_each_crtc(dev, c) {
13895 obj = intel_fb_obj(c->primary->fb);
13896 if (obj == NULL)
13897 continue;
13898
13899 if (intel_pin_and_fence_fb_obj(c->primary,
13900 c->primary->fb,
13901 NULL)) {
13902 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13903 to_intel_crtc(c)->pipe);
13904 drm_framebuffer_unreference(c->primary->fb);
13905 c->primary->fb = NULL;
13906 update_state_fb(c->primary);
13907 }
13908 }
13909 mutex_unlock(&dev->struct_mutex);
13910
13911 intel_backlight_register(dev);
13912 }
13913
13914 void intel_connector_unregister(struct intel_connector *intel_connector)
13915 {
13916 struct drm_connector *connector = &intel_connector->base;
13917
13918 intel_panel_destroy_backlight(connector);
13919 drm_connector_unregister(connector);
13920 }
13921
13922 void intel_modeset_cleanup(struct drm_device *dev)
13923 {
13924 struct drm_i915_private *dev_priv = dev->dev_private;
13925 struct drm_connector *connector;
13926
13927 intel_disable_gt_powersave(dev);
13928
13929 intel_backlight_unregister(dev);
13930
13931 /*
13932 * Interrupts and polling as the first thing to avoid creating havoc.
13933 * Too much stuff here (turning of connectors, ...) would
13934 * experience fancy races otherwise.
13935 */
13936 intel_irq_uninstall(dev_priv);
13937
13938 /*
13939 * Due to the hpd irq storm handling the hotplug work can re-arm the
13940 * poll handlers. Hence disable polling after hpd handling is shut down.
13941 */
13942 drm_kms_helper_poll_fini(dev);
13943
13944 mutex_lock(&dev->struct_mutex);
13945
13946 intel_unregister_dsm_handler();
13947
13948 intel_fbc_disable(dev);
13949
13950 mutex_unlock(&dev->struct_mutex);
13951
13952 /* flush any delayed tasks or pending work */
13953 flush_scheduled_work();
13954
13955 /* destroy the backlight and sysfs files before encoders/connectors */
13956 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13957 struct intel_connector *intel_connector;
13958
13959 intel_connector = to_intel_connector(connector);
13960 intel_connector->unregister(intel_connector);
13961 }
13962
13963 drm_mode_config_cleanup(dev);
13964
13965 intel_cleanup_overlay(dev);
13966
13967 mutex_lock(&dev->struct_mutex);
13968 intel_cleanup_gt_powersave(dev);
13969 mutex_unlock(&dev->struct_mutex);
13970 }
13971
13972 /*
13973 * Return which encoder is currently attached for connector.
13974 */
13975 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13976 {
13977 return &intel_attached_encoder(connector)->base;
13978 }
13979
13980 void intel_connector_attach_encoder(struct intel_connector *connector,
13981 struct intel_encoder *encoder)
13982 {
13983 connector->encoder = encoder;
13984 drm_mode_connector_attach_encoder(&connector->base,
13985 &encoder->base);
13986 }
13987
13988 /*
13989 * set vga decode state - true == enable VGA decode
13990 */
13991 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13992 {
13993 struct drm_i915_private *dev_priv = dev->dev_private;
13994 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13995 u16 gmch_ctrl;
13996
13997 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13998 DRM_ERROR("failed to read control word\n");
13999 return -EIO;
14000 }
14001
14002 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
14003 return 0;
14004
14005 if (state)
14006 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
14007 else
14008 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
14009
14010 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
14011 DRM_ERROR("failed to write control word\n");
14012 return -EIO;
14013 }
14014
14015 return 0;
14016 }
14017
14018 struct intel_display_error_state {
14019
14020 u32 power_well_driver;
14021
14022 int num_transcoders;
14023
14024 struct intel_cursor_error_state {
14025 u32 control;
14026 u32 position;
14027 u32 base;
14028 u32 size;
14029 } cursor[I915_MAX_PIPES];
14030
14031 struct intel_pipe_error_state {
14032 bool power_domain_on;
14033 u32 source;
14034 u32 stat;
14035 } pipe[I915_MAX_PIPES];
14036
14037 struct intel_plane_error_state {
14038 u32 control;
14039 u32 stride;
14040 u32 size;
14041 u32 pos;
14042 u32 addr;
14043 u32 surface;
14044 u32 tile_offset;
14045 } plane[I915_MAX_PIPES];
14046
14047 struct intel_transcoder_error_state {
14048 bool power_domain_on;
14049 enum transcoder cpu_transcoder;
14050
14051 u32 conf;
14052
14053 u32 htotal;
14054 u32 hblank;
14055 u32 hsync;
14056 u32 vtotal;
14057 u32 vblank;
14058 u32 vsync;
14059 } transcoder[4];
14060 };
14061
14062 struct intel_display_error_state *
14063 intel_display_capture_error_state(struct drm_device *dev)
14064 {
14065 struct drm_i915_private *dev_priv = dev->dev_private;
14066 struct intel_display_error_state *error;
14067 int transcoders[] = {
14068 TRANSCODER_A,
14069 TRANSCODER_B,
14070 TRANSCODER_C,
14071 TRANSCODER_EDP,
14072 };
14073 int i;
14074
14075 if (INTEL_INFO(dev)->num_pipes == 0)
14076 return NULL;
14077
14078 error = kzalloc(sizeof(*error), GFP_ATOMIC);
14079 if (error == NULL)
14080 return NULL;
14081
14082 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
14083 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
14084
14085 for_each_pipe(dev_priv, i) {
14086 error->pipe[i].power_domain_on =
14087 __intel_display_power_is_enabled(dev_priv,
14088 POWER_DOMAIN_PIPE(i));
14089 if (!error->pipe[i].power_domain_on)
14090 continue;
14091
14092 error->cursor[i].control = I915_READ(CURCNTR(i));
14093 error->cursor[i].position = I915_READ(CURPOS(i));
14094 error->cursor[i].base = I915_READ(CURBASE(i));
14095
14096 error->plane[i].control = I915_READ(DSPCNTR(i));
14097 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
14098 if (INTEL_INFO(dev)->gen <= 3) {
14099 error->plane[i].size = I915_READ(DSPSIZE(i));
14100 error->plane[i].pos = I915_READ(DSPPOS(i));
14101 }
14102 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14103 error->plane[i].addr = I915_READ(DSPADDR(i));
14104 if (INTEL_INFO(dev)->gen >= 4) {
14105 error->plane[i].surface = I915_READ(DSPSURF(i));
14106 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
14107 }
14108
14109 error->pipe[i].source = I915_READ(PIPESRC(i));
14110
14111 if (HAS_GMCH_DISPLAY(dev))
14112 error->pipe[i].stat = I915_READ(PIPESTAT(i));
14113 }
14114
14115 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
14116 if (HAS_DDI(dev_priv->dev))
14117 error->num_transcoders++; /* Account for eDP. */
14118
14119 for (i = 0; i < error->num_transcoders; i++) {
14120 enum transcoder cpu_transcoder = transcoders[i];
14121
14122 error->transcoder[i].power_domain_on =
14123 __intel_display_power_is_enabled(dev_priv,
14124 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
14125 if (!error->transcoder[i].power_domain_on)
14126 continue;
14127
14128 error->transcoder[i].cpu_transcoder = cpu_transcoder;
14129
14130 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
14131 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
14132 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
14133 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
14134 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
14135 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
14136 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
14137 }
14138
14139 return error;
14140 }
14141
14142 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
14143
14144 void
14145 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
14146 struct drm_device *dev,
14147 struct intel_display_error_state *error)
14148 {
14149 struct drm_i915_private *dev_priv = dev->dev_private;
14150 int i;
14151
14152 if (!error)
14153 return;
14154
14155 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
14156 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
14157 err_printf(m, "PWR_WELL_CTL2: %08x\n",
14158 error->power_well_driver);
14159 for_each_pipe(dev_priv, i) {
14160 err_printf(m, "Pipe [%d]:\n", i);
14161 err_printf(m, " Power: %s\n",
14162 error->pipe[i].power_domain_on ? "on" : "off");
14163 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
14164 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
14165
14166 err_printf(m, "Plane [%d]:\n", i);
14167 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
14168 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
14169 if (INTEL_INFO(dev)->gen <= 3) {
14170 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
14171 err_printf(m, " POS: %08x\n", error->plane[i].pos);
14172 }
14173 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14174 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
14175 if (INTEL_INFO(dev)->gen >= 4) {
14176 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
14177 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
14178 }
14179
14180 err_printf(m, "Cursor [%d]:\n", i);
14181 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
14182 err_printf(m, " POS: %08x\n", error->cursor[i].position);
14183 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
14184 }
14185
14186 for (i = 0; i < error->num_transcoders; i++) {
14187 err_printf(m, "CPU transcoder: %c\n",
14188 transcoder_name(error->transcoder[i].cpu_transcoder));
14189 err_printf(m, " Power: %s\n",
14190 error->transcoder[i].power_domain_on ? "on" : "off");
14191 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
14192 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
14193 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
14194 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
14195 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
14196 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
14197 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
14198 }
14199 }
14200
14201 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
14202 {
14203 struct intel_crtc *crtc;
14204
14205 for_each_intel_crtc(dev, crtc) {
14206 struct intel_unpin_work *work;
14207
14208 spin_lock_irq(&dev->event_lock);
14209
14210 work = crtc->unpin_work;
14211
14212 if (work && work->event &&
14213 work->event->base.file_priv == file) {
14214 kfree(work->event);
14215 work->event = NULL;
14216 }
14217
14218 spin_unlock_irq(&dev->event_lock);
14219 }
14220 }
Linux kernel - Deliverables
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