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drm/i915: Check for a stalled page flip after each vblank
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_rect.h>
44 #include <linux/dma_remapping.h>
45
46 /* Primary plane formats supported by all gen */
47 #define COMMON_PRIMARY_FORMATS \
48 DRM_FORMAT_C8, \
49 DRM_FORMAT_RGB565, \
50 DRM_FORMAT_XRGB8888, \
51 DRM_FORMAT_ARGB8888
52
53 /* Primary plane formats for gen <= 3 */
54 static const uint32_t intel_primary_formats_gen2[] = {
55 COMMON_PRIMARY_FORMATS,
56 DRM_FORMAT_XRGB1555,
57 DRM_FORMAT_ARGB1555,
58 };
59
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t intel_primary_formats_gen4[] = {
62 COMMON_PRIMARY_FORMATS, \
63 DRM_FORMAT_XBGR8888,
64 DRM_FORMAT_ABGR8888,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_ARGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 DRM_FORMAT_ABGR2101010,
69 };
70
71 /* Cursor formats */
72 static const uint32_t intel_cursor_formats[] = {
73 DRM_FORMAT_ARGB8888,
74 };
75
76 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
77 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
78
79 static void intel_increase_pllclock(struct drm_device *dev,
80 enum pipe pipe);
81 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
82
83 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
84 struct intel_crtc_config *pipe_config);
85 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
86 struct intel_crtc_config *pipe_config);
87
88 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
89 int x, int y, struct drm_framebuffer *old_fb);
90 static int intel_framebuffer_init(struct drm_device *dev,
91 struct intel_framebuffer *ifb,
92 struct drm_mode_fb_cmd2 *mode_cmd,
93 struct drm_i915_gem_object *obj);
94 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
95 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
96 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
97 struct intel_link_m_n *m_n,
98 struct intel_link_m_n *m2_n2);
99 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
100 static void haswell_set_pipeconf(struct drm_crtc *crtc);
101 static void intel_set_pipe_csc(struct drm_crtc *crtc);
102 static void vlv_prepare_pll(struct intel_crtc *crtc);
103 static void chv_prepare_pll(struct intel_crtc *crtc);
104
105 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
106 {
107 if (!connector->mst_port)
108 return connector->encoder;
109 else
110 return &connector->mst_port->mst_encoders[pipe]->base;
111 }
112
113 typedef struct {
114 int min, max;
115 } intel_range_t;
116
117 typedef struct {
118 int dot_limit;
119 int p2_slow, p2_fast;
120 } intel_p2_t;
121
122 typedef struct intel_limit intel_limit_t;
123 struct intel_limit {
124 intel_range_t dot, vco, n, m, m1, m2, p, p1;
125 intel_p2_t p2;
126 };
127
128 int
129 intel_pch_rawclk(struct drm_device *dev)
130 {
131 struct drm_i915_private *dev_priv = dev->dev_private;
132
133 WARN_ON(!HAS_PCH_SPLIT(dev));
134
135 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
136 }
137
138 static inline u32 /* units of 100MHz */
139 intel_fdi_link_freq(struct drm_device *dev)
140 {
141 if (IS_GEN5(dev)) {
142 struct drm_i915_private *dev_priv = dev->dev_private;
143 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
144 } else
145 return 27;
146 }
147
148 static const intel_limit_t intel_limits_i8xx_dac = {
149 .dot = { .min = 25000, .max = 350000 },
150 .vco = { .min = 908000, .max = 1512000 },
151 .n = { .min = 2, .max = 16 },
152 .m = { .min = 96, .max = 140 },
153 .m1 = { .min = 18, .max = 26 },
154 .m2 = { .min = 6, .max = 16 },
155 .p = { .min = 4, .max = 128 },
156 .p1 = { .min = 2, .max = 33 },
157 .p2 = { .dot_limit = 165000,
158 .p2_slow = 4, .p2_fast = 2 },
159 };
160
161 static const intel_limit_t intel_limits_i8xx_dvo = {
162 .dot = { .min = 25000, .max = 350000 },
163 .vco = { .min = 908000, .max = 1512000 },
164 .n = { .min = 2, .max = 16 },
165 .m = { .min = 96, .max = 140 },
166 .m1 = { .min = 18, .max = 26 },
167 .m2 = { .min = 6, .max = 16 },
168 .p = { .min = 4, .max = 128 },
169 .p1 = { .min = 2, .max = 33 },
170 .p2 = { .dot_limit = 165000,
171 .p2_slow = 4, .p2_fast = 4 },
172 };
173
174 static const intel_limit_t intel_limits_i8xx_lvds = {
175 .dot = { .min = 25000, .max = 350000 },
176 .vco = { .min = 908000, .max = 1512000 },
177 .n = { .min = 2, .max = 16 },
178 .m = { .min = 96, .max = 140 },
179 .m1 = { .min = 18, .max = 26 },
180 .m2 = { .min = 6, .max = 16 },
181 .p = { .min = 4, .max = 128 },
182 .p1 = { .min = 1, .max = 6 },
183 .p2 = { .dot_limit = 165000,
184 .p2_slow = 14, .p2_fast = 7 },
185 };
186
187 static const intel_limit_t intel_limits_i9xx_sdvo = {
188 .dot = { .min = 20000, .max = 400000 },
189 .vco = { .min = 1400000, .max = 2800000 },
190 .n = { .min = 1, .max = 6 },
191 .m = { .min = 70, .max = 120 },
192 .m1 = { .min = 8, .max = 18 },
193 .m2 = { .min = 3, .max = 7 },
194 .p = { .min = 5, .max = 80 },
195 .p1 = { .min = 1, .max = 8 },
196 .p2 = { .dot_limit = 200000,
197 .p2_slow = 10, .p2_fast = 5 },
198 };
199
200 static const intel_limit_t intel_limits_i9xx_lvds = {
201 .dot = { .min = 20000, .max = 400000 },
202 .vco = { .min = 1400000, .max = 2800000 },
203 .n = { .min = 1, .max = 6 },
204 .m = { .min = 70, .max = 120 },
205 .m1 = { .min = 8, .max = 18 },
206 .m2 = { .min = 3, .max = 7 },
207 .p = { .min = 7, .max = 98 },
208 .p1 = { .min = 1, .max = 8 },
209 .p2 = { .dot_limit = 112000,
210 .p2_slow = 14, .p2_fast = 7 },
211 };
212
213
214 static const intel_limit_t intel_limits_g4x_sdvo = {
215 .dot = { .min = 25000, .max = 270000 },
216 .vco = { .min = 1750000, .max = 3500000},
217 .n = { .min = 1, .max = 4 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 10, .max = 30 },
222 .p1 = { .min = 1, .max = 3},
223 .p2 = { .dot_limit = 270000,
224 .p2_slow = 10,
225 .p2_fast = 10
226 },
227 };
228
229 static const intel_limit_t intel_limits_g4x_hdmi = {
230 .dot = { .min = 22000, .max = 400000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 4 },
233 .m = { .min = 104, .max = 138 },
234 .m1 = { .min = 16, .max = 23 },
235 .m2 = { .min = 5, .max = 11 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8},
238 .p2 = { .dot_limit = 165000,
239 .p2_slow = 10, .p2_fast = 5 },
240 };
241
242 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
243 .dot = { .min = 20000, .max = 115000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 14, .p2_fast = 14
253 },
254 };
255
256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
257 .dot = { .min = 80000, .max = 224000 },
258 .vco = { .min = 1750000, .max = 3500000 },
259 .n = { .min = 1, .max = 3 },
260 .m = { .min = 104, .max = 138 },
261 .m1 = { .min = 17, .max = 23 },
262 .m2 = { .min = 5, .max = 11 },
263 .p = { .min = 14, .max = 42 },
264 .p1 = { .min = 2, .max = 6 },
265 .p2 = { .dot_limit = 0,
266 .p2_slow = 7, .p2_fast = 7
267 },
268 };
269
270 static const intel_limit_t intel_limits_pineview_sdvo = {
271 .dot = { .min = 20000, .max = 400000},
272 .vco = { .min = 1700000, .max = 3500000 },
273 /* Pineview's Ncounter is a ring counter */
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 /* Pineview only has one combined m divider, which we treat as m2. */
277 .m1 = { .min = 0, .max = 0 },
278 .m2 = { .min = 0, .max = 254 },
279 .p = { .min = 5, .max = 80 },
280 .p1 = { .min = 1, .max = 8 },
281 .p2 = { .dot_limit = 200000,
282 .p2_slow = 10, .p2_fast = 5 },
283 };
284
285 static const intel_limit_t intel_limits_pineview_lvds = {
286 .dot = { .min = 20000, .max = 400000 },
287 .vco = { .min = 1700000, .max = 3500000 },
288 .n = { .min = 3, .max = 6 },
289 .m = { .min = 2, .max = 256 },
290 .m1 = { .min = 0, .max = 0 },
291 .m2 = { .min = 0, .max = 254 },
292 .p = { .min = 7, .max = 112 },
293 .p1 = { .min = 1, .max = 8 },
294 .p2 = { .dot_limit = 112000,
295 .p2_slow = 14, .p2_fast = 14 },
296 };
297
298 /* Ironlake / Sandybridge
299 *
300 * We calculate clock using (register_value + 2) for N/M1/M2, so here
301 * the range value for them is (actual_value - 2).
302 */
303 static const intel_limit_t intel_limits_ironlake_dac = {
304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 5 },
307 .m = { .min = 79, .max = 127 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 5, .max = 80 },
311 .p1 = { .min = 1, .max = 8 },
312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 10, .p2_fast = 5 },
314 };
315
316 static const intel_limit_t intel_limits_ironlake_single_lvds = {
317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 3 },
320 .m = { .min = 79, .max = 118 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2, .max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
327 };
328
329 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
330 .dot = { .min = 25000, .max = 350000 },
331 .vco = { .min = 1760000, .max = 3510000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 79, .max = 127 },
334 .m1 = { .min = 12, .max = 22 },
335 .m2 = { .min = 5, .max = 9 },
336 .p = { .min = 14, .max = 56 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 225000,
339 .p2_slow = 7, .p2_fast = 7 },
340 };
341
342 /* LVDS 100mhz refclk limits. */
343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000 },
346 .n = { .min = 1, .max = 2 },
347 .m = { .min = 79, .max = 126 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 28, .max = 112 },
351 .p1 = { .min = 2, .max = 8 },
352 .p2 = { .dot_limit = 225000,
353 .p2_slow = 14, .p2_fast = 14 },
354 };
355
356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
357 .dot = { .min = 25000, .max = 350000 },
358 .vco = { .min = 1760000, .max = 3510000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 79, .max = 126 },
361 .m1 = { .min = 12, .max = 22 },
362 .m2 = { .min = 5, .max = 9 },
363 .p = { .min = 14, .max = 42 },
364 .p1 = { .min = 2, .max = 6 },
365 .p2 = { .dot_limit = 225000,
366 .p2_slow = 7, .p2_fast = 7 },
367 };
368
369 static const intel_limit_t intel_limits_vlv = {
370 /*
371 * These are the data rate limits (measured in fast clocks)
372 * since those are the strictest limits we have. The fast
373 * clock and actual rate limits are more relaxed, so checking
374 * them would make no difference.
375 */
376 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m1 = { .min = 2, .max = 3 },
380 .m2 = { .min = 11, .max = 156 },
381 .p1 = { .min = 2, .max = 3 },
382 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
383 };
384
385 static const intel_limit_t intel_limits_chv = {
386 /*
387 * These are the data rate limits (measured in fast clocks)
388 * since those are the strictest limits we have. The fast
389 * clock and actual rate limits are more relaxed, so checking
390 * them would make no difference.
391 */
392 .dot = { .min = 25000 * 5, .max = 540000 * 5},
393 .vco = { .min = 4860000, .max = 6700000 },
394 .n = { .min = 1, .max = 1 },
395 .m1 = { .min = 2, .max = 2 },
396 .m2 = { .min = 24 << 22, .max = 175 << 22 },
397 .p1 = { .min = 2, .max = 4 },
398 .p2 = { .p2_slow = 1, .p2_fast = 14 },
399 };
400
401 static void vlv_clock(int refclk, intel_clock_t *clock)
402 {
403 clock->m = clock->m1 * clock->m2;
404 clock->p = clock->p1 * clock->p2;
405 if (WARN_ON(clock->n == 0 || clock->p == 0))
406 return;
407 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
408 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
409 }
410
411 /**
412 * Returns whether any output on the specified pipe is of the specified type
413 */
414 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
415 {
416 struct drm_device *dev = crtc->dev;
417 struct intel_encoder *encoder;
418
419 for_each_encoder_on_crtc(dev, crtc, encoder)
420 if (encoder->type == type)
421 return true;
422
423 return false;
424 }
425
426 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
427 int refclk)
428 {
429 struct drm_device *dev = crtc->dev;
430 const intel_limit_t *limit;
431
432 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
433 if (intel_is_dual_link_lvds(dev)) {
434 if (refclk == 100000)
435 limit = &intel_limits_ironlake_dual_lvds_100m;
436 else
437 limit = &intel_limits_ironlake_dual_lvds;
438 } else {
439 if (refclk == 100000)
440 limit = &intel_limits_ironlake_single_lvds_100m;
441 else
442 limit = &intel_limits_ironlake_single_lvds;
443 }
444 } else
445 limit = &intel_limits_ironlake_dac;
446
447 return limit;
448 }
449
450 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
451 {
452 struct drm_device *dev = crtc->dev;
453 const intel_limit_t *limit;
454
455 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
456 if (intel_is_dual_link_lvds(dev))
457 limit = &intel_limits_g4x_dual_channel_lvds;
458 else
459 limit = &intel_limits_g4x_single_channel_lvds;
460 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
461 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
462 limit = &intel_limits_g4x_hdmi;
463 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
464 limit = &intel_limits_g4x_sdvo;
465 } else /* The option is for other outputs */
466 limit = &intel_limits_i9xx_sdvo;
467
468 return limit;
469 }
470
471 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
472 {
473 struct drm_device *dev = crtc->dev;
474 const intel_limit_t *limit;
475
476 if (HAS_PCH_SPLIT(dev))
477 limit = intel_ironlake_limit(crtc, refclk);
478 else if (IS_G4X(dev)) {
479 limit = intel_g4x_limit(crtc);
480 } else if (IS_PINEVIEW(dev)) {
481 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
482 limit = &intel_limits_pineview_lvds;
483 else
484 limit = &intel_limits_pineview_sdvo;
485 } else if (IS_CHERRYVIEW(dev)) {
486 limit = &intel_limits_chv;
487 } else if (IS_VALLEYVIEW(dev)) {
488 limit = &intel_limits_vlv;
489 } else if (!IS_GEN2(dev)) {
490 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
491 limit = &intel_limits_i9xx_lvds;
492 else
493 limit = &intel_limits_i9xx_sdvo;
494 } else {
495 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
496 limit = &intel_limits_i8xx_lvds;
497 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
498 limit = &intel_limits_i8xx_dvo;
499 else
500 limit = &intel_limits_i8xx_dac;
501 }
502 return limit;
503 }
504
505 /* m1 is reserved as 0 in Pineview, n is a ring counter */
506 static void pineview_clock(int refclk, intel_clock_t *clock)
507 {
508 clock->m = clock->m2 + 2;
509 clock->p = clock->p1 * clock->p2;
510 if (WARN_ON(clock->n == 0 || clock->p == 0))
511 return;
512 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
513 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
514 }
515
516 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
517 {
518 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
519 }
520
521 static void i9xx_clock(int refclk, intel_clock_t *clock)
522 {
523 clock->m = i9xx_dpll_compute_m(clock);
524 clock->p = clock->p1 * clock->p2;
525 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
526 return;
527 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
528 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
529 }
530
531 static void chv_clock(int refclk, intel_clock_t *clock)
532 {
533 clock->m = clock->m1 * clock->m2;
534 clock->p = clock->p1 * clock->p2;
535 if (WARN_ON(clock->n == 0 || clock->p == 0))
536 return;
537 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
538 clock->n << 22);
539 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
540 }
541
542 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
543 /**
544 * Returns whether the given set of divisors are valid for a given refclk with
545 * the given connectors.
546 */
547
548 static bool intel_PLL_is_valid(struct drm_device *dev,
549 const intel_limit_t *limit,
550 const intel_clock_t *clock)
551 {
552 if (clock->n < limit->n.min || limit->n.max < clock->n)
553 INTELPllInvalid("n out of range\n");
554 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
555 INTELPllInvalid("p1 out of range\n");
556 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
557 INTELPllInvalid("m2 out of range\n");
558 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
559 INTELPllInvalid("m1 out of range\n");
560
561 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
562 if (clock->m1 <= clock->m2)
563 INTELPllInvalid("m1 <= m2\n");
564
565 if (!IS_VALLEYVIEW(dev)) {
566 if (clock->p < limit->p.min || limit->p.max < clock->p)
567 INTELPllInvalid("p out of range\n");
568 if (clock->m < limit->m.min || limit->m.max < clock->m)
569 INTELPllInvalid("m out of range\n");
570 }
571
572 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
573 INTELPllInvalid("vco out of range\n");
574 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
575 * connector, etc., rather than just a single range.
576 */
577 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
578 INTELPllInvalid("dot out of range\n");
579
580 return true;
581 }
582
583 static bool
584 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
585 int target, int refclk, intel_clock_t *match_clock,
586 intel_clock_t *best_clock)
587 {
588 struct drm_device *dev = crtc->dev;
589 intel_clock_t clock;
590 int err = target;
591
592 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
593 /*
594 * For LVDS just rely on its current settings for dual-channel.
595 * We haven't figured out how to reliably set up different
596 * single/dual channel state, if we even can.
597 */
598 if (intel_is_dual_link_lvds(dev))
599 clock.p2 = limit->p2.p2_fast;
600 else
601 clock.p2 = limit->p2.p2_slow;
602 } else {
603 if (target < limit->p2.dot_limit)
604 clock.p2 = limit->p2.p2_slow;
605 else
606 clock.p2 = limit->p2.p2_fast;
607 }
608
609 memset(best_clock, 0, sizeof(*best_clock));
610
611 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
612 clock.m1++) {
613 for (clock.m2 = limit->m2.min;
614 clock.m2 <= limit->m2.max; clock.m2++) {
615 if (clock.m2 >= clock.m1)
616 break;
617 for (clock.n = limit->n.min;
618 clock.n <= limit->n.max; clock.n++) {
619 for (clock.p1 = limit->p1.min;
620 clock.p1 <= limit->p1.max; clock.p1++) {
621 int this_err;
622
623 i9xx_clock(refclk, &clock);
624 if (!intel_PLL_is_valid(dev, limit,
625 &clock))
626 continue;
627 if (match_clock &&
628 clock.p != match_clock->p)
629 continue;
630
631 this_err = abs(clock.dot - target);
632 if (this_err < err) {
633 *best_clock = clock;
634 err = this_err;
635 }
636 }
637 }
638 }
639 }
640
641 return (err != target);
642 }
643
644 static bool
645 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
646 int target, int refclk, intel_clock_t *match_clock,
647 intel_clock_t *best_clock)
648 {
649 struct drm_device *dev = crtc->dev;
650 intel_clock_t clock;
651 int err = target;
652
653 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
654 /*
655 * For LVDS just rely on its current settings for dual-channel.
656 * We haven't figured out how to reliably set up different
657 * single/dual channel state, if we even can.
658 */
659 if (intel_is_dual_link_lvds(dev))
660 clock.p2 = limit->p2.p2_fast;
661 else
662 clock.p2 = limit->p2.p2_slow;
663 } else {
664 if (target < limit->p2.dot_limit)
665 clock.p2 = limit->p2.p2_slow;
666 else
667 clock.p2 = limit->p2.p2_fast;
668 }
669
670 memset(best_clock, 0, sizeof(*best_clock));
671
672 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
673 clock.m1++) {
674 for (clock.m2 = limit->m2.min;
675 clock.m2 <= limit->m2.max; clock.m2++) {
676 for (clock.n = limit->n.min;
677 clock.n <= limit->n.max; clock.n++) {
678 for (clock.p1 = limit->p1.min;
679 clock.p1 <= limit->p1.max; clock.p1++) {
680 int this_err;
681
682 pineview_clock(refclk, &clock);
683 if (!intel_PLL_is_valid(dev, limit,
684 &clock))
685 continue;
686 if (match_clock &&
687 clock.p != match_clock->p)
688 continue;
689
690 this_err = abs(clock.dot - target);
691 if (this_err < err) {
692 *best_clock = clock;
693 err = this_err;
694 }
695 }
696 }
697 }
698 }
699
700 return (err != target);
701 }
702
703 static bool
704 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
705 int target, int refclk, intel_clock_t *match_clock,
706 intel_clock_t *best_clock)
707 {
708 struct drm_device *dev = crtc->dev;
709 intel_clock_t clock;
710 int max_n;
711 bool found;
712 /* approximately equals target * 0.00585 */
713 int err_most = (target >> 8) + (target >> 9);
714 found = false;
715
716 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
717 if (intel_is_dual_link_lvds(dev))
718 clock.p2 = limit->p2.p2_fast;
719 else
720 clock.p2 = limit->p2.p2_slow;
721 } else {
722 if (target < limit->p2.dot_limit)
723 clock.p2 = limit->p2.p2_slow;
724 else
725 clock.p2 = limit->p2.p2_fast;
726 }
727
728 memset(best_clock, 0, sizeof(*best_clock));
729 max_n = limit->n.max;
730 /* based on hardware requirement, prefer smaller n to precision */
731 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
732 /* based on hardware requirement, prefere larger m1,m2 */
733 for (clock.m1 = limit->m1.max;
734 clock.m1 >= limit->m1.min; clock.m1--) {
735 for (clock.m2 = limit->m2.max;
736 clock.m2 >= limit->m2.min; clock.m2--) {
737 for (clock.p1 = limit->p1.max;
738 clock.p1 >= limit->p1.min; clock.p1--) {
739 int this_err;
740
741 i9xx_clock(refclk, &clock);
742 if (!intel_PLL_is_valid(dev, limit,
743 &clock))
744 continue;
745
746 this_err = abs(clock.dot - target);
747 if (this_err < err_most) {
748 *best_clock = clock;
749 err_most = this_err;
750 max_n = clock.n;
751 found = true;
752 }
753 }
754 }
755 }
756 }
757 return found;
758 }
759
760 static bool
761 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
762 int target, int refclk, intel_clock_t *match_clock,
763 intel_clock_t *best_clock)
764 {
765 struct drm_device *dev = crtc->dev;
766 intel_clock_t clock;
767 unsigned int bestppm = 1000000;
768 /* min update 19.2 MHz */
769 int max_n = min(limit->n.max, refclk / 19200);
770 bool found = false;
771
772 target *= 5; /* fast clock */
773
774 memset(best_clock, 0, sizeof(*best_clock));
775
776 /* based on hardware requirement, prefer smaller n to precision */
777 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
778 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
779 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
780 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
781 clock.p = clock.p1 * clock.p2;
782 /* based on hardware requirement, prefer bigger m1,m2 values */
783 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
784 unsigned int ppm, diff;
785
786 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
787 refclk * clock.m1);
788
789 vlv_clock(refclk, &clock);
790
791 if (!intel_PLL_is_valid(dev, limit,
792 &clock))
793 continue;
794
795 diff = abs(clock.dot - target);
796 ppm = div_u64(1000000ULL * diff, target);
797
798 if (ppm < 100 && clock.p > best_clock->p) {
799 bestppm = 0;
800 *best_clock = clock;
801 found = true;
802 }
803
804 if (bestppm >= 10 && ppm < bestppm - 10) {
805 bestppm = ppm;
806 *best_clock = clock;
807 found = true;
808 }
809 }
810 }
811 }
812 }
813
814 return found;
815 }
816
817 static bool
818 chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
819 int target, int refclk, intel_clock_t *match_clock,
820 intel_clock_t *best_clock)
821 {
822 struct drm_device *dev = crtc->dev;
823 intel_clock_t clock;
824 uint64_t m2;
825 int found = false;
826
827 memset(best_clock, 0, sizeof(*best_clock));
828
829 /*
830 * Based on hardware doc, the n always set to 1, and m1 always
831 * set to 2. If requires to support 200Mhz refclk, we need to
832 * revisit this because n may not 1 anymore.
833 */
834 clock.n = 1, clock.m1 = 2;
835 target *= 5; /* fast clock */
836
837 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
838 for (clock.p2 = limit->p2.p2_fast;
839 clock.p2 >= limit->p2.p2_slow;
840 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
841
842 clock.p = clock.p1 * clock.p2;
843
844 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
845 clock.n) << 22, refclk * clock.m1);
846
847 if (m2 > INT_MAX/clock.m1)
848 continue;
849
850 clock.m2 = m2;
851
852 chv_clock(refclk, &clock);
853
854 if (!intel_PLL_is_valid(dev, limit, &clock))
855 continue;
856
857 /* based on hardware requirement, prefer bigger p
858 */
859 if (clock.p > best_clock->p) {
860 *best_clock = clock;
861 found = true;
862 }
863 }
864 }
865
866 return found;
867 }
868
869 bool intel_crtc_active(struct drm_crtc *crtc)
870 {
871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
872
873 /* Be paranoid as we can arrive here with only partial
874 * state retrieved from the hardware during setup.
875 *
876 * We can ditch the adjusted_mode.crtc_clock check as soon
877 * as Haswell has gained clock readout/fastboot support.
878 *
879 * We can ditch the crtc->primary->fb check as soon as we can
880 * properly reconstruct framebuffers.
881 */
882 return intel_crtc->active && crtc->primary->fb &&
883 intel_crtc->config.adjusted_mode.crtc_clock;
884 }
885
886 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
887 enum pipe pipe)
888 {
889 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
890 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
891
892 return intel_crtc->config.cpu_transcoder;
893 }
894
895 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
896 {
897 struct drm_i915_private *dev_priv = dev->dev_private;
898 u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
899
900 frame = I915_READ(frame_reg);
901
902 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
903 WARN(1, "vblank wait on pipe %c timed out\n",
904 pipe_name(pipe));
905 }
906
907 /**
908 * intel_wait_for_vblank - wait for vblank on a given pipe
909 * @dev: drm device
910 * @pipe: pipe to wait for
911 *
912 * Wait for vblank to occur on a given pipe. Needed for various bits of
913 * mode setting code.
914 */
915 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
916 {
917 struct drm_i915_private *dev_priv = dev->dev_private;
918 int pipestat_reg = PIPESTAT(pipe);
919
920 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
921 g4x_wait_for_vblank(dev, pipe);
922 return;
923 }
924
925 /* Clear existing vblank status. Note this will clear any other
926 * sticky status fields as well.
927 *
928 * This races with i915_driver_irq_handler() with the result
929 * that either function could miss a vblank event. Here it is not
930 * fatal, as we will either wait upon the next vblank interrupt or
931 * timeout. Generally speaking intel_wait_for_vblank() is only
932 * called during modeset at which time the GPU should be idle and
933 * should *not* be performing page flips and thus not waiting on
934 * vblanks...
935 * Currently, the result of us stealing a vblank from the irq
936 * handler is that a single frame will be skipped during swapbuffers.
937 */
938 I915_WRITE(pipestat_reg,
939 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
940
941 /* Wait for vblank interrupt bit to set */
942 if (wait_for(I915_READ(pipestat_reg) &
943 PIPE_VBLANK_INTERRUPT_STATUS,
944 50))
945 DRM_DEBUG_KMS("vblank wait on pipe %c timed out\n",
946 pipe_name(pipe));
947 }
948
949 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
950 {
951 struct drm_i915_private *dev_priv = dev->dev_private;
952 u32 reg = PIPEDSL(pipe);
953 u32 line1, line2;
954 u32 line_mask;
955
956 if (IS_GEN2(dev))
957 line_mask = DSL_LINEMASK_GEN2;
958 else
959 line_mask = DSL_LINEMASK_GEN3;
960
961 line1 = I915_READ(reg) & line_mask;
962 mdelay(5);
963 line2 = I915_READ(reg) & line_mask;
964
965 return line1 == line2;
966 }
967
968 /*
969 * intel_wait_for_pipe_off - wait for pipe to turn off
970 * @crtc: crtc whose pipe to wait for
971 *
972 * After disabling a pipe, we can't wait for vblank in the usual way,
973 * spinning on the vblank interrupt status bit, since we won't actually
974 * see an interrupt when the pipe is disabled.
975 *
976 * On Gen4 and above:
977 * wait for the pipe register state bit to turn off
978 *
979 * Otherwise:
980 * wait for the display line value to settle (it usually
981 * ends up stopping at the start of the next frame).
982 *
983 */
984 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
985 {
986 struct drm_device *dev = crtc->base.dev;
987 struct drm_i915_private *dev_priv = dev->dev_private;
988 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
989 enum pipe pipe = crtc->pipe;
990
991 if (INTEL_INFO(dev)->gen >= 4) {
992 int reg = PIPECONF(cpu_transcoder);
993
994 /* Wait for the Pipe State to go off */
995 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
996 100))
997 WARN(1, "pipe_off wait timed out\n");
998 } else {
999 /* Wait for the display line to settle */
1000 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1001 WARN(1, "pipe_off wait timed out\n");
1002 }
1003 }
1004
1005 /*
1006 * ibx_digital_port_connected - is the specified port connected?
1007 * @dev_priv: i915 private structure
1008 * @port: the port to test
1009 *
1010 * Returns true if @port is connected, false otherwise.
1011 */
1012 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1013 struct intel_digital_port *port)
1014 {
1015 u32 bit;
1016
1017 if (HAS_PCH_IBX(dev_priv->dev)) {
1018 switch (port->port) {
1019 case PORT_B:
1020 bit = SDE_PORTB_HOTPLUG;
1021 break;
1022 case PORT_C:
1023 bit = SDE_PORTC_HOTPLUG;
1024 break;
1025 case PORT_D:
1026 bit = SDE_PORTD_HOTPLUG;
1027 break;
1028 default:
1029 return true;
1030 }
1031 } else {
1032 switch (port->port) {
1033 case PORT_B:
1034 bit = SDE_PORTB_HOTPLUG_CPT;
1035 break;
1036 case PORT_C:
1037 bit = SDE_PORTC_HOTPLUG_CPT;
1038 break;
1039 case PORT_D:
1040 bit = SDE_PORTD_HOTPLUG_CPT;
1041 break;
1042 default:
1043 return true;
1044 }
1045 }
1046
1047 return I915_READ(SDEISR) & bit;
1048 }
1049
1050 static const char *state_string(bool enabled)
1051 {
1052 return enabled ? "on" : "off";
1053 }
1054
1055 /* Only for pre-ILK configs */
1056 void assert_pll(struct drm_i915_private *dev_priv,
1057 enum pipe pipe, bool state)
1058 {
1059 int reg;
1060 u32 val;
1061 bool cur_state;
1062
1063 reg = DPLL(pipe);
1064 val = I915_READ(reg);
1065 cur_state = !!(val & DPLL_VCO_ENABLE);
1066 WARN(cur_state != state,
1067 "PLL state assertion failure (expected %s, current %s)\n",
1068 state_string(state), state_string(cur_state));
1069 }
1070
1071 /* XXX: the dsi pll is shared between MIPI DSI ports */
1072 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1073 {
1074 u32 val;
1075 bool cur_state;
1076
1077 mutex_lock(&dev_priv->dpio_lock);
1078 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1079 mutex_unlock(&dev_priv->dpio_lock);
1080
1081 cur_state = val & DSI_PLL_VCO_EN;
1082 WARN(cur_state != state,
1083 "DSI PLL state assertion failure (expected %s, current %s)\n",
1084 state_string(state), state_string(cur_state));
1085 }
1086 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1087 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1088
1089 struct intel_shared_dpll *
1090 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1091 {
1092 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1093
1094 if (crtc->config.shared_dpll < 0)
1095 return NULL;
1096
1097 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1098 }
1099
1100 /* For ILK+ */
1101 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1102 struct intel_shared_dpll *pll,
1103 bool state)
1104 {
1105 bool cur_state;
1106 struct intel_dpll_hw_state hw_state;
1107
1108 if (WARN (!pll,
1109 "asserting DPLL %s with no DPLL\n", state_string(state)))
1110 return;
1111
1112 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1113 WARN(cur_state != state,
1114 "%s assertion failure (expected %s, current %s)\n",
1115 pll->name, state_string(state), state_string(cur_state));
1116 }
1117
1118 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1119 enum pipe pipe, bool state)
1120 {
1121 int reg;
1122 u32 val;
1123 bool cur_state;
1124 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1125 pipe);
1126
1127 if (HAS_DDI(dev_priv->dev)) {
1128 /* DDI does not have a specific FDI_TX register */
1129 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1130 val = I915_READ(reg);
1131 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1132 } else {
1133 reg = FDI_TX_CTL(pipe);
1134 val = I915_READ(reg);
1135 cur_state = !!(val & FDI_TX_ENABLE);
1136 }
1137 WARN(cur_state != state,
1138 "FDI TX state assertion failure (expected %s, current %s)\n",
1139 state_string(state), state_string(cur_state));
1140 }
1141 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1142 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1143
1144 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1145 enum pipe pipe, bool state)
1146 {
1147 int reg;
1148 u32 val;
1149 bool cur_state;
1150
1151 reg = FDI_RX_CTL(pipe);
1152 val = I915_READ(reg);
1153 cur_state = !!(val & FDI_RX_ENABLE);
1154 WARN(cur_state != state,
1155 "FDI RX state assertion failure (expected %s, current %s)\n",
1156 state_string(state), state_string(cur_state));
1157 }
1158 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1159 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1160
1161 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1162 enum pipe pipe)
1163 {
1164 int reg;
1165 u32 val;
1166
1167 /* ILK FDI PLL is always enabled */
1168 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1169 return;
1170
1171 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1172 if (HAS_DDI(dev_priv->dev))
1173 return;
1174
1175 reg = FDI_TX_CTL(pipe);
1176 val = I915_READ(reg);
1177 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1178 }
1179
1180 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1181 enum pipe pipe, bool state)
1182 {
1183 int reg;
1184 u32 val;
1185 bool cur_state;
1186
1187 reg = FDI_RX_CTL(pipe);
1188 val = I915_READ(reg);
1189 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1190 WARN(cur_state != state,
1191 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1192 state_string(state), state_string(cur_state));
1193 }
1194
1195 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1196 enum pipe pipe)
1197 {
1198 struct drm_device *dev = dev_priv->dev;
1199 int pp_reg;
1200 u32 val;
1201 enum pipe panel_pipe = PIPE_A;
1202 bool locked = true;
1203
1204 if (WARN_ON(HAS_DDI(dev)))
1205 return;
1206
1207 if (HAS_PCH_SPLIT(dev)) {
1208 u32 port_sel;
1209
1210 pp_reg = PCH_PP_CONTROL;
1211 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1212
1213 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1214 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1215 panel_pipe = PIPE_B;
1216 /* XXX: else fix for eDP */
1217 } else if (IS_VALLEYVIEW(dev)) {
1218 /* presumably write lock depends on pipe, not port select */
1219 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1220 panel_pipe = pipe;
1221 } else {
1222 pp_reg = PP_CONTROL;
1223 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1224 panel_pipe = PIPE_B;
1225 }
1226
1227 val = I915_READ(pp_reg);
1228 if (!(val & PANEL_POWER_ON) ||
1229 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1230 locked = false;
1231
1232 WARN(panel_pipe == pipe && locked,
1233 "panel assertion failure, pipe %c regs locked\n",
1234 pipe_name(pipe));
1235 }
1236
1237 static void assert_cursor(struct drm_i915_private *dev_priv,
1238 enum pipe pipe, bool state)
1239 {
1240 struct drm_device *dev = dev_priv->dev;
1241 bool cur_state;
1242
1243 if (IS_845G(dev) || IS_I865G(dev))
1244 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1245 else
1246 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1247
1248 WARN(cur_state != state,
1249 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1250 pipe_name(pipe), state_string(state), state_string(cur_state));
1251 }
1252 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1253 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1254
1255 void assert_pipe(struct drm_i915_private *dev_priv,
1256 enum pipe pipe, bool state)
1257 {
1258 int reg;
1259 u32 val;
1260 bool cur_state;
1261 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1262 pipe);
1263
1264 /* if we need the pipe quirk it must be always on */
1265 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1266 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1267 state = true;
1268
1269 if (!intel_display_power_enabled(dev_priv,
1270 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1271 cur_state = false;
1272 } else {
1273 reg = PIPECONF(cpu_transcoder);
1274 val = I915_READ(reg);
1275 cur_state = !!(val & PIPECONF_ENABLE);
1276 }
1277
1278 WARN(cur_state != state,
1279 "pipe %c assertion failure (expected %s, current %s)\n",
1280 pipe_name(pipe), state_string(state), state_string(cur_state));
1281 }
1282
1283 static void assert_plane(struct drm_i915_private *dev_priv,
1284 enum plane plane, bool state)
1285 {
1286 int reg;
1287 u32 val;
1288 bool cur_state;
1289
1290 reg = DSPCNTR(plane);
1291 val = I915_READ(reg);
1292 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1293 WARN(cur_state != state,
1294 "plane %c assertion failure (expected %s, current %s)\n",
1295 plane_name(plane), state_string(state), state_string(cur_state));
1296 }
1297
1298 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1299 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1300
1301 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1302 enum pipe pipe)
1303 {
1304 struct drm_device *dev = dev_priv->dev;
1305 int reg, i;
1306 u32 val;
1307 int cur_pipe;
1308
1309 /* Primary planes are fixed to pipes on gen4+ */
1310 if (INTEL_INFO(dev)->gen >= 4) {
1311 reg = DSPCNTR(pipe);
1312 val = I915_READ(reg);
1313 WARN(val & DISPLAY_PLANE_ENABLE,
1314 "plane %c assertion failure, should be disabled but not\n",
1315 plane_name(pipe));
1316 return;
1317 }
1318
1319 /* Need to check both planes against the pipe */
1320 for_each_pipe(dev_priv, i) {
1321 reg = DSPCNTR(i);
1322 val = I915_READ(reg);
1323 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1324 DISPPLANE_SEL_PIPE_SHIFT;
1325 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1326 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1327 plane_name(i), pipe_name(pipe));
1328 }
1329 }
1330
1331 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1332 enum pipe pipe)
1333 {
1334 struct drm_device *dev = dev_priv->dev;
1335 int reg, sprite;
1336 u32 val;
1337
1338 if (IS_VALLEYVIEW(dev)) {
1339 for_each_sprite(pipe, sprite) {
1340 reg = SPCNTR(pipe, sprite);
1341 val = I915_READ(reg);
1342 WARN(val & SP_ENABLE,
1343 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1344 sprite_name(pipe, sprite), pipe_name(pipe));
1345 }
1346 } else if (INTEL_INFO(dev)->gen >= 7) {
1347 reg = SPRCTL(pipe);
1348 val = I915_READ(reg);
1349 WARN(val & SPRITE_ENABLE,
1350 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1351 plane_name(pipe), pipe_name(pipe));
1352 } else if (INTEL_INFO(dev)->gen >= 5) {
1353 reg = DVSCNTR(pipe);
1354 val = I915_READ(reg);
1355 WARN(val & DVS_ENABLE,
1356 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1357 plane_name(pipe), pipe_name(pipe));
1358 }
1359 }
1360
1361 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1362 {
1363 u32 val;
1364 bool enabled;
1365
1366 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1367
1368 val = I915_READ(PCH_DREF_CONTROL);
1369 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1370 DREF_SUPERSPREAD_SOURCE_MASK));
1371 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1372 }
1373
1374 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1375 enum pipe pipe)
1376 {
1377 int reg;
1378 u32 val;
1379 bool enabled;
1380
1381 reg = PCH_TRANSCONF(pipe);
1382 val = I915_READ(reg);
1383 enabled = !!(val & TRANS_ENABLE);
1384 WARN(enabled,
1385 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1386 pipe_name(pipe));
1387 }
1388
1389 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1390 enum pipe pipe, u32 port_sel, u32 val)
1391 {
1392 if ((val & DP_PORT_EN) == 0)
1393 return false;
1394
1395 if (HAS_PCH_CPT(dev_priv->dev)) {
1396 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1397 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1398 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1399 return false;
1400 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1401 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1402 return false;
1403 } else {
1404 if ((val & DP_PIPE_MASK) != (pipe << 30))
1405 return false;
1406 }
1407 return true;
1408 }
1409
1410 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1411 enum pipe pipe, u32 val)
1412 {
1413 if ((val & SDVO_ENABLE) == 0)
1414 return false;
1415
1416 if (HAS_PCH_CPT(dev_priv->dev)) {
1417 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1418 return false;
1419 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1420 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1421 return false;
1422 } else {
1423 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1424 return false;
1425 }
1426 return true;
1427 }
1428
1429 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1430 enum pipe pipe, u32 val)
1431 {
1432 if ((val & LVDS_PORT_EN) == 0)
1433 return false;
1434
1435 if (HAS_PCH_CPT(dev_priv->dev)) {
1436 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1437 return false;
1438 } else {
1439 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1440 return false;
1441 }
1442 return true;
1443 }
1444
1445 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1446 enum pipe pipe, u32 val)
1447 {
1448 if ((val & ADPA_DAC_ENABLE) == 0)
1449 return false;
1450 if (HAS_PCH_CPT(dev_priv->dev)) {
1451 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1452 return false;
1453 } else {
1454 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1455 return false;
1456 }
1457 return true;
1458 }
1459
1460 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1461 enum pipe pipe, int reg, u32 port_sel)
1462 {
1463 u32 val = I915_READ(reg);
1464 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1465 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1466 reg, pipe_name(pipe));
1467
1468 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1469 && (val & DP_PIPEB_SELECT),
1470 "IBX PCH dp port still using transcoder B\n");
1471 }
1472
1473 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1474 enum pipe pipe, int reg)
1475 {
1476 u32 val = I915_READ(reg);
1477 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1478 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1479 reg, pipe_name(pipe));
1480
1481 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1482 && (val & SDVO_PIPE_B_SELECT),
1483 "IBX PCH hdmi port still using transcoder B\n");
1484 }
1485
1486 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1487 enum pipe pipe)
1488 {
1489 int reg;
1490 u32 val;
1491
1492 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1493 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1494 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1495
1496 reg = PCH_ADPA;
1497 val = I915_READ(reg);
1498 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1499 "PCH VGA enabled on transcoder %c, should be disabled\n",
1500 pipe_name(pipe));
1501
1502 reg = PCH_LVDS;
1503 val = I915_READ(reg);
1504 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1505 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1506 pipe_name(pipe));
1507
1508 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1509 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1510 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1511 }
1512
1513 static void intel_init_dpio(struct drm_device *dev)
1514 {
1515 struct drm_i915_private *dev_priv = dev->dev_private;
1516
1517 if (!IS_VALLEYVIEW(dev))
1518 return;
1519
1520 /*
1521 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1522 * CHV x1 PHY (DP/HDMI D)
1523 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1524 */
1525 if (IS_CHERRYVIEW(dev)) {
1526 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1527 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1528 } else {
1529 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1530 }
1531 }
1532
1533 static void vlv_enable_pll(struct intel_crtc *crtc)
1534 {
1535 struct drm_device *dev = crtc->base.dev;
1536 struct drm_i915_private *dev_priv = dev->dev_private;
1537 int reg = DPLL(crtc->pipe);
1538 u32 dpll = crtc->config.dpll_hw_state.dpll;
1539
1540 assert_pipe_disabled(dev_priv, crtc->pipe);
1541
1542 /* No really, not for ILK+ */
1543 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1544
1545 /* PLL is protected by panel, make sure we can write it */
1546 if (IS_MOBILE(dev_priv->dev))
1547 assert_panel_unlocked(dev_priv, crtc->pipe);
1548
1549 I915_WRITE(reg, dpll);
1550 POSTING_READ(reg);
1551 udelay(150);
1552
1553 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1554 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1555
1556 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1557 POSTING_READ(DPLL_MD(crtc->pipe));
1558
1559 /* We do this three times for luck */
1560 I915_WRITE(reg, dpll);
1561 POSTING_READ(reg);
1562 udelay(150); /* wait for warmup */
1563 I915_WRITE(reg, dpll);
1564 POSTING_READ(reg);
1565 udelay(150); /* wait for warmup */
1566 I915_WRITE(reg, dpll);
1567 POSTING_READ(reg);
1568 udelay(150); /* wait for warmup */
1569 }
1570
1571 static void chv_enable_pll(struct intel_crtc *crtc)
1572 {
1573 struct drm_device *dev = crtc->base.dev;
1574 struct drm_i915_private *dev_priv = dev->dev_private;
1575 int pipe = crtc->pipe;
1576 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1577 u32 tmp;
1578
1579 assert_pipe_disabled(dev_priv, crtc->pipe);
1580
1581 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1582
1583 mutex_lock(&dev_priv->dpio_lock);
1584
1585 /* Enable back the 10bit clock to display controller */
1586 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1587 tmp |= DPIO_DCLKP_EN;
1588 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1589
1590 /*
1591 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1592 */
1593 udelay(1);
1594
1595 /* Enable PLL */
1596 I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
1597
1598 /* Check PLL is locked */
1599 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1600 DRM_ERROR("PLL %d failed to lock\n", pipe);
1601
1602 /* not sure when this should be written */
1603 I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
1604 POSTING_READ(DPLL_MD(pipe));
1605
1606 mutex_unlock(&dev_priv->dpio_lock);
1607 }
1608
1609 static void i9xx_enable_pll(struct intel_crtc *crtc)
1610 {
1611 struct drm_device *dev = crtc->base.dev;
1612 struct drm_i915_private *dev_priv = dev->dev_private;
1613 int reg = DPLL(crtc->pipe);
1614 u32 dpll = crtc->config.dpll_hw_state.dpll;
1615
1616 assert_pipe_disabled(dev_priv, crtc->pipe);
1617
1618 /* No really, not for ILK+ */
1619 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1620
1621 /* PLL is protected by panel, make sure we can write it */
1622 if (IS_MOBILE(dev) && !IS_I830(dev))
1623 assert_panel_unlocked(dev_priv, crtc->pipe);
1624
1625 I915_WRITE(reg, dpll);
1626
1627 /* Wait for the clocks to stabilize. */
1628 POSTING_READ(reg);
1629 udelay(150);
1630
1631 if (INTEL_INFO(dev)->gen >= 4) {
1632 I915_WRITE(DPLL_MD(crtc->pipe),
1633 crtc->config.dpll_hw_state.dpll_md);
1634 } else {
1635 /* The pixel multiplier can only be updated once the
1636 * DPLL is enabled and the clocks are stable.
1637 *
1638 * So write it again.
1639 */
1640 I915_WRITE(reg, dpll);
1641 }
1642
1643 /* We do this three times for luck */
1644 I915_WRITE(reg, dpll);
1645 POSTING_READ(reg);
1646 udelay(150); /* wait for warmup */
1647 I915_WRITE(reg, dpll);
1648 POSTING_READ(reg);
1649 udelay(150); /* wait for warmup */
1650 I915_WRITE(reg, dpll);
1651 POSTING_READ(reg);
1652 udelay(150); /* wait for warmup */
1653 }
1654
1655 /**
1656 * i9xx_disable_pll - disable a PLL
1657 * @dev_priv: i915 private structure
1658 * @pipe: pipe PLL to disable
1659 *
1660 * Disable the PLL for @pipe, making sure the pipe is off first.
1661 *
1662 * Note! This is for pre-ILK only.
1663 */
1664 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1665 {
1666 /* Don't disable pipe or pipe PLLs if needed */
1667 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1668 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1669 return;
1670
1671 /* Make sure the pipe isn't still relying on us */
1672 assert_pipe_disabled(dev_priv, pipe);
1673
1674 I915_WRITE(DPLL(pipe), 0);
1675 POSTING_READ(DPLL(pipe));
1676 }
1677
1678 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1679 {
1680 u32 val = 0;
1681
1682 /* Make sure the pipe isn't still relying on us */
1683 assert_pipe_disabled(dev_priv, pipe);
1684
1685 /*
1686 * Leave integrated clock source and reference clock enabled for pipe B.
1687 * The latter is needed for VGA hotplug / manual detection.
1688 */
1689 if (pipe == PIPE_B)
1690 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1691 I915_WRITE(DPLL(pipe), val);
1692 POSTING_READ(DPLL(pipe));
1693
1694 }
1695
1696 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1697 {
1698 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1699 u32 val;
1700
1701 /* Make sure the pipe isn't still relying on us */
1702 assert_pipe_disabled(dev_priv, pipe);
1703
1704 /* Set PLL en = 0 */
1705 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1706 if (pipe != PIPE_A)
1707 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1708 I915_WRITE(DPLL(pipe), val);
1709 POSTING_READ(DPLL(pipe));
1710
1711 mutex_lock(&dev_priv->dpio_lock);
1712
1713 /* Disable 10bit clock to display controller */
1714 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1715 val &= ~DPIO_DCLKP_EN;
1716 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1717
1718 /* disable left/right clock distribution */
1719 if (pipe != PIPE_B) {
1720 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1721 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1722 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1723 } else {
1724 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1725 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1726 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1727 }
1728
1729 mutex_unlock(&dev_priv->dpio_lock);
1730 }
1731
1732 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1733 struct intel_digital_port *dport)
1734 {
1735 u32 port_mask;
1736 int dpll_reg;
1737
1738 switch (dport->port) {
1739 case PORT_B:
1740 port_mask = DPLL_PORTB_READY_MASK;
1741 dpll_reg = DPLL(0);
1742 break;
1743 case PORT_C:
1744 port_mask = DPLL_PORTC_READY_MASK;
1745 dpll_reg = DPLL(0);
1746 break;
1747 case PORT_D:
1748 port_mask = DPLL_PORTD_READY_MASK;
1749 dpll_reg = DPIO_PHY_STATUS;
1750 break;
1751 default:
1752 BUG();
1753 }
1754
1755 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1756 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1757 port_name(dport->port), I915_READ(dpll_reg));
1758 }
1759
1760 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1761 {
1762 struct drm_device *dev = crtc->base.dev;
1763 struct drm_i915_private *dev_priv = dev->dev_private;
1764 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1765
1766 if (WARN_ON(pll == NULL))
1767 return;
1768
1769 WARN_ON(!pll->refcount);
1770 if (pll->active == 0) {
1771 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1772 WARN_ON(pll->on);
1773 assert_shared_dpll_disabled(dev_priv, pll);
1774
1775 pll->mode_set(dev_priv, pll);
1776 }
1777 }
1778
1779 /**
1780 * intel_enable_shared_dpll - enable PCH PLL
1781 * @dev_priv: i915 private structure
1782 * @pipe: pipe PLL to enable
1783 *
1784 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1785 * drives the transcoder clock.
1786 */
1787 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1788 {
1789 struct drm_device *dev = crtc->base.dev;
1790 struct drm_i915_private *dev_priv = dev->dev_private;
1791 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1792
1793 if (WARN_ON(pll == NULL))
1794 return;
1795
1796 if (WARN_ON(pll->refcount == 0))
1797 return;
1798
1799 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1800 pll->name, pll->active, pll->on,
1801 crtc->base.base.id);
1802
1803 if (pll->active++) {
1804 WARN_ON(!pll->on);
1805 assert_shared_dpll_enabled(dev_priv, pll);
1806 return;
1807 }
1808 WARN_ON(pll->on);
1809
1810 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1811
1812 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1813 pll->enable(dev_priv, pll);
1814 pll->on = true;
1815 }
1816
1817 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1818 {
1819 struct drm_device *dev = crtc->base.dev;
1820 struct drm_i915_private *dev_priv = dev->dev_private;
1821 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1822
1823 /* PCH only available on ILK+ */
1824 BUG_ON(INTEL_INFO(dev)->gen < 5);
1825 if (WARN_ON(pll == NULL))
1826 return;
1827
1828 if (WARN_ON(pll->refcount == 0))
1829 return;
1830
1831 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1832 pll->name, pll->active, pll->on,
1833 crtc->base.base.id);
1834
1835 if (WARN_ON(pll->active == 0)) {
1836 assert_shared_dpll_disabled(dev_priv, pll);
1837 return;
1838 }
1839
1840 assert_shared_dpll_enabled(dev_priv, pll);
1841 WARN_ON(!pll->on);
1842 if (--pll->active)
1843 return;
1844
1845 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1846 pll->disable(dev_priv, pll);
1847 pll->on = false;
1848
1849 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1850 }
1851
1852 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1853 enum pipe pipe)
1854 {
1855 struct drm_device *dev = dev_priv->dev;
1856 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1857 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1858 uint32_t reg, val, pipeconf_val;
1859
1860 /* PCH only available on ILK+ */
1861 BUG_ON(!HAS_PCH_SPLIT(dev));
1862
1863 /* Make sure PCH DPLL is enabled */
1864 assert_shared_dpll_enabled(dev_priv,
1865 intel_crtc_to_shared_dpll(intel_crtc));
1866
1867 /* FDI must be feeding us bits for PCH ports */
1868 assert_fdi_tx_enabled(dev_priv, pipe);
1869 assert_fdi_rx_enabled(dev_priv, pipe);
1870
1871 if (HAS_PCH_CPT(dev)) {
1872 /* Workaround: Set the timing override bit before enabling the
1873 * pch transcoder. */
1874 reg = TRANS_CHICKEN2(pipe);
1875 val = I915_READ(reg);
1876 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1877 I915_WRITE(reg, val);
1878 }
1879
1880 reg = PCH_TRANSCONF(pipe);
1881 val = I915_READ(reg);
1882 pipeconf_val = I915_READ(PIPECONF(pipe));
1883
1884 if (HAS_PCH_IBX(dev_priv->dev)) {
1885 /*
1886 * make the BPC in transcoder be consistent with
1887 * that in pipeconf reg.
1888 */
1889 val &= ~PIPECONF_BPC_MASK;
1890 val |= pipeconf_val & PIPECONF_BPC_MASK;
1891 }
1892
1893 val &= ~TRANS_INTERLACE_MASK;
1894 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1895 if (HAS_PCH_IBX(dev_priv->dev) &&
1896 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1897 val |= TRANS_LEGACY_INTERLACED_ILK;
1898 else
1899 val |= TRANS_INTERLACED;
1900 else
1901 val |= TRANS_PROGRESSIVE;
1902
1903 I915_WRITE(reg, val | TRANS_ENABLE);
1904 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1905 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1906 }
1907
1908 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1909 enum transcoder cpu_transcoder)
1910 {
1911 u32 val, pipeconf_val;
1912
1913 /* PCH only available on ILK+ */
1914 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1915
1916 /* FDI must be feeding us bits for PCH ports */
1917 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1918 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1919
1920 /* Workaround: set timing override bit. */
1921 val = I915_READ(_TRANSA_CHICKEN2);
1922 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1923 I915_WRITE(_TRANSA_CHICKEN2, val);
1924
1925 val = TRANS_ENABLE;
1926 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1927
1928 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1929 PIPECONF_INTERLACED_ILK)
1930 val |= TRANS_INTERLACED;
1931 else
1932 val |= TRANS_PROGRESSIVE;
1933
1934 I915_WRITE(LPT_TRANSCONF, val);
1935 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1936 DRM_ERROR("Failed to enable PCH transcoder\n");
1937 }
1938
1939 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1940 enum pipe pipe)
1941 {
1942 struct drm_device *dev = dev_priv->dev;
1943 uint32_t reg, val;
1944
1945 /* FDI relies on the transcoder */
1946 assert_fdi_tx_disabled(dev_priv, pipe);
1947 assert_fdi_rx_disabled(dev_priv, pipe);
1948
1949 /* Ports must be off as well */
1950 assert_pch_ports_disabled(dev_priv, pipe);
1951
1952 reg = PCH_TRANSCONF(pipe);
1953 val = I915_READ(reg);
1954 val &= ~TRANS_ENABLE;
1955 I915_WRITE(reg, val);
1956 /* wait for PCH transcoder off, transcoder state */
1957 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1958 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1959
1960 if (!HAS_PCH_IBX(dev)) {
1961 /* Workaround: Clear the timing override chicken bit again. */
1962 reg = TRANS_CHICKEN2(pipe);
1963 val = I915_READ(reg);
1964 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1965 I915_WRITE(reg, val);
1966 }
1967 }
1968
1969 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1970 {
1971 u32 val;
1972
1973 val = I915_READ(LPT_TRANSCONF);
1974 val &= ~TRANS_ENABLE;
1975 I915_WRITE(LPT_TRANSCONF, val);
1976 /* wait for PCH transcoder off, transcoder state */
1977 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1978 DRM_ERROR("Failed to disable PCH transcoder\n");
1979
1980 /* Workaround: clear timing override bit. */
1981 val = I915_READ(_TRANSA_CHICKEN2);
1982 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1983 I915_WRITE(_TRANSA_CHICKEN2, val);
1984 }
1985
1986 /**
1987 * intel_enable_pipe - enable a pipe, asserting requirements
1988 * @crtc: crtc responsible for the pipe
1989 *
1990 * Enable @crtc's pipe, making sure that various hardware specific requirements
1991 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1992 */
1993 static void intel_enable_pipe(struct intel_crtc *crtc)
1994 {
1995 struct drm_device *dev = crtc->base.dev;
1996 struct drm_i915_private *dev_priv = dev->dev_private;
1997 enum pipe pipe = crtc->pipe;
1998 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1999 pipe);
2000 enum pipe pch_transcoder;
2001 int reg;
2002 u32 val;
2003
2004 assert_planes_disabled(dev_priv, pipe);
2005 assert_cursor_disabled(dev_priv, pipe);
2006 assert_sprites_disabled(dev_priv, pipe);
2007
2008 if (HAS_PCH_LPT(dev_priv->dev))
2009 pch_transcoder = TRANSCODER_A;
2010 else
2011 pch_transcoder = pipe;
2012
2013 /*
2014 * A pipe without a PLL won't actually be able to drive bits from
2015 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2016 * need the check.
2017 */
2018 if (!HAS_PCH_SPLIT(dev_priv->dev))
2019 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
2020 assert_dsi_pll_enabled(dev_priv);
2021 else
2022 assert_pll_enabled(dev_priv, pipe);
2023 else {
2024 if (crtc->config.has_pch_encoder) {
2025 /* if driving the PCH, we need FDI enabled */
2026 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2027 assert_fdi_tx_pll_enabled(dev_priv,
2028 (enum pipe) cpu_transcoder);
2029 }
2030 /* FIXME: assert CPU port conditions for SNB+ */
2031 }
2032
2033 reg = PIPECONF(cpu_transcoder);
2034 val = I915_READ(reg);
2035 if (val & PIPECONF_ENABLE) {
2036 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2037 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2038 return;
2039 }
2040
2041 I915_WRITE(reg, val | PIPECONF_ENABLE);
2042 POSTING_READ(reg);
2043 }
2044
2045 /**
2046 * intel_disable_pipe - disable a pipe, asserting requirements
2047 * @crtc: crtc whose pipes is to be disabled
2048 *
2049 * Disable the pipe of @crtc, making sure that various hardware
2050 * specific requirements are met, if applicable, e.g. plane
2051 * disabled, panel fitter off, etc.
2052 *
2053 * Will wait until the pipe has shut down before returning.
2054 */
2055 static void intel_disable_pipe(struct intel_crtc *crtc)
2056 {
2057 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2058 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2059 enum pipe pipe = crtc->pipe;
2060 int reg;
2061 u32 val;
2062
2063 /*
2064 * Make sure planes won't keep trying to pump pixels to us,
2065 * or we might hang the display.
2066 */
2067 assert_planes_disabled(dev_priv, pipe);
2068 assert_cursor_disabled(dev_priv, pipe);
2069 assert_sprites_disabled(dev_priv, pipe);
2070
2071 reg = PIPECONF(cpu_transcoder);
2072 val = I915_READ(reg);
2073 if ((val & PIPECONF_ENABLE) == 0)
2074 return;
2075
2076 /*
2077 * Double wide has implications for planes
2078 * so best keep it disabled when not needed.
2079 */
2080 if (crtc->config.double_wide)
2081 val &= ~PIPECONF_DOUBLE_WIDE;
2082
2083 /* Don't disable pipe or pipe PLLs if needed */
2084 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2085 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2086 val &= ~PIPECONF_ENABLE;
2087
2088 I915_WRITE(reg, val);
2089 if ((val & PIPECONF_ENABLE) == 0)
2090 intel_wait_for_pipe_off(crtc);
2091 }
2092
2093 /*
2094 * Plane regs are double buffered, going from enabled->disabled needs a
2095 * trigger in order to latch. The display address reg provides this.
2096 */
2097 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2098 enum plane plane)
2099 {
2100 struct drm_device *dev = dev_priv->dev;
2101 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2102
2103 I915_WRITE(reg, I915_READ(reg));
2104 POSTING_READ(reg);
2105 }
2106
2107 /**
2108 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2109 * @plane: plane to be enabled
2110 * @crtc: crtc for the plane
2111 *
2112 * Enable @plane on @crtc, making sure that the pipe is running first.
2113 */
2114 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2115 struct drm_crtc *crtc)
2116 {
2117 struct drm_device *dev = plane->dev;
2118 struct drm_i915_private *dev_priv = dev->dev_private;
2119 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2120
2121 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2122 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2123
2124 if (intel_crtc->primary_enabled)
2125 return;
2126
2127 intel_crtc->primary_enabled = true;
2128
2129 dev_priv->display.update_primary_plane(crtc, plane->fb,
2130 crtc->x, crtc->y);
2131
2132 /*
2133 * BDW signals flip done immediately if the plane
2134 * is disabled, even if the plane enable is already
2135 * armed to occur at the next vblank :(
2136 */
2137 if (IS_BROADWELL(dev))
2138 intel_wait_for_vblank(dev, intel_crtc->pipe);
2139 }
2140
2141 /**
2142 * intel_disable_primary_hw_plane - disable the primary hardware plane
2143 * @plane: plane to be disabled
2144 * @crtc: crtc for the plane
2145 *
2146 * Disable @plane on @crtc, making sure that the pipe is running first.
2147 */
2148 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2149 struct drm_crtc *crtc)
2150 {
2151 struct drm_device *dev = plane->dev;
2152 struct drm_i915_private *dev_priv = dev->dev_private;
2153 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2154
2155 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2156
2157 if (!intel_crtc->primary_enabled)
2158 return;
2159
2160 intel_crtc->primary_enabled = false;
2161
2162 dev_priv->display.update_primary_plane(crtc, plane->fb,
2163 crtc->x, crtc->y);
2164 }
2165
2166 static bool need_vtd_wa(struct drm_device *dev)
2167 {
2168 #ifdef CONFIG_INTEL_IOMMU
2169 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2170 return true;
2171 #endif
2172 return false;
2173 }
2174
2175 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2176 {
2177 int tile_height;
2178
2179 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2180 return ALIGN(height, tile_height);
2181 }
2182
2183 int
2184 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2185 struct drm_i915_gem_object *obj,
2186 struct intel_engine_cs *pipelined)
2187 {
2188 struct drm_i915_private *dev_priv = dev->dev_private;
2189 u32 alignment;
2190 int ret;
2191
2192 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2193
2194 switch (obj->tiling_mode) {
2195 case I915_TILING_NONE:
2196 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2197 alignment = 128 * 1024;
2198 else if (INTEL_INFO(dev)->gen >= 4)
2199 alignment = 4 * 1024;
2200 else
2201 alignment = 64 * 1024;
2202 break;
2203 case I915_TILING_X:
2204 /* pin() will align the object as required by fence */
2205 alignment = 0;
2206 break;
2207 case I915_TILING_Y:
2208 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2209 return -EINVAL;
2210 default:
2211 BUG();
2212 }
2213
2214 /* Note that the w/a also requires 64 PTE of padding following the
2215 * bo. We currently fill all unused PTE with the shadow page and so
2216 * we should always have valid PTE following the scanout preventing
2217 * the VT-d warning.
2218 */
2219 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2220 alignment = 256 * 1024;
2221
2222 dev_priv->mm.interruptible = false;
2223 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2224 if (ret)
2225 goto err_interruptible;
2226
2227 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2228 * fence, whereas 965+ only requires a fence if using
2229 * framebuffer compression. For simplicity, we always install
2230 * a fence as the cost is not that onerous.
2231 */
2232 ret = i915_gem_object_get_fence(obj);
2233 if (ret)
2234 goto err_unpin;
2235
2236 i915_gem_object_pin_fence(obj);
2237
2238 dev_priv->mm.interruptible = true;
2239 return 0;
2240
2241 err_unpin:
2242 i915_gem_object_unpin_from_display_plane(obj);
2243 err_interruptible:
2244 dev_priv->mm.interruptible = true;
2245 return ret;
2246 }
2247
2248 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2249 {
2250 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2251
2252 i915_gem_object_unpin_fence(obj);
2253 i915_gem_object_unpin_from_display_plane(obj);
2254 }
2255
2256 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2257 * is assumed to be a power-of-two. */
2258 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2259 unsigned int tiling_mode,
2260 unsigned int cpp,
2261 unsigned int pitch)
2262 {
2263 if (tiling_mode != I915_TILING_NONE) {
2264 unsigned int tile_rows, tiles;
2265
2266 tile_rows = *y / 8;
2267 *y %= 8;
2268
2269 tiles = *x / (512/cpp);
2270 *x %= 512/cpp;
2271
2272 return tile_rows * pitch * 8 + tiles * 4096;
2273 } else {
2274 unsigned int offset;
2275
2276 offset = *y * pitch + *x * cpp;
2277 *y = 0;
2278 *x = (offset & 4095) / cpp;
2279 return offset & -4096;
2280 }
2281 }
2282
2283 int intel_format_to_fourcc(int format)
2284 {
2285 switch (format) {
2286 case DISPPLANE_8BPP:
2287 return DRM_FORMAT_C8;
2288 case DISPPLANE_BGRX555:
2289 return DRM_FORMAT_XRGB1555;
2290 case DISPPLANE_BGRX565:
2291 return DRM_FORMAT_RGB565;
2292 default:
2293 case DISPPLANE_BGRX888:
2294 return DRM_FORMAT_XRGB8888;
2295 case DISPPLANE_RGBX888:
2296 return DRM_FORMAT_XBGR8888;
2297 case DISPPLANE_BGRX101010:
2298 return DRM_FORMAT_XRGB2101010;
2299 case DISPPLANE_RGBX101010:
2300 return DRM_FORMAT_XBGR2101010;
2301 }
2302 }
2303
2304 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2305 struct intel_plane_config *plane_config)
2306 {
2307 struct drm_device *dev = crtc->base.dev;
2308 struct drm_i915_gem_object *obj = NULL;
2309 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2310 u32 base = plane_config->base;
2311
2312 if (plane_config->size == 0)
2313 return false;
2314
2315 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2316 plane_config->size);
2317 if (!obj)
2318 return false;
2319
2320 if (plane_config->tiled) {
2321 obj->tiling_mode = I915_TILING_X;
2322 obj->stride = crtc->base.primary->fb->pitches[0];
2323 }
2324
2325 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2326 mode_cmd.width = crtc->base.primary->fb->width;
2327 mode_cmd.height = crtc->base.primary->fb->height;
2328 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2329
2330 mutex_lock(&dev->struct_mutex);
2331
2332 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2333 &mode_cmd, obj)) {
2334 DRM_DEBUG_KMS("intel fb init failed\n");
2335 goto out_unref_obj;
2336 }
2337
2338 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2339 mutex_unlock(&dev->struct_mutex);
2340
2341 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2342 return true;
2343
2344 out_unref_obj:
2345 drm_gem_object_unreference(&obj->base);
2346 mutex_unlock(&dev->struct_mutex);
2347 return false;
2348 }
2349
2350 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2351 struct intel_plane_config *plane_config)
2352 {
2353 struct drm_device *dev = intel_crtc->base.dev;
2354 struct drm_crtc *c;
2355 struct intel_crtc *i;
2356 struct drm_i915_gem_object *obj;
2357
2358 if (!intel_crtc->base.primary->fb)
2359 return;
2360
2361 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2362 return;
2363
2364 kfree(intel_crtc->base.primary->fb);
2365 intel_crtc->base.primary->fb = NULL;
2366
2367 /*
2368 * Failed to alloc the obj, check to see if we should share
2369 * an fb with another CRTC instead
2370 */
2371 for_each_crtc(dev, c) {
2372 i = to_intel_crtc(c);
2373
2374 if (c == &intel_crtc->base)
2375 continue;
2376
2377 if (!i->active)
2378 continue;
2379
2380 obj = intel_fb_obj(c->primary->fb);
2381 if (obj == NULL)
2382 continue;
2383
2384 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2385 drm_framebuffer_reference(c->primary->fb);
2386 intel_crtc->base.primary->fb = c->primary->fb;
2387 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2388 break;
2389 }
2390 }
2391 }
2392
2393 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2394 struct drm_framebuffer *fb,
2395 int x, int y)
2396 {
2397 struct drm_device *dev = crtc->dev;
2398 struct drm_i915_private *dev_priv = dev->dev_private;
2399 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2400 struct drm_i915_gem_object *obj;
2401 int plane = intel_crtc->plane;
2402 unsigned long linear_offset;
2403 u32 dspcntr;
2404 u32 reg = DSPCNTR(plane);
2405 int pixel_size;
2406
2407 if (!intel_crtc->primary_enabled) {
2408 I915_WRITE(reg, 0);
2409 if (INTEL_INFO(dev)->gen >= 4)
2410 I915_WRITE(DSPSURF(plane), 0);
2411 else
2412 I915_WRITE(DSPADDR(plane), 0);
2413 POSTING_READ(reg);
2414 return;
2415 }
2416
2417 obj = intel_fb_obj(fb);
2418 if (WARN_ON(obj == NULL))
2419 return;
2420
2421 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2422
2423 dspcntr = DISPPLANE_GAMMA_ENABLE;
2424
2425 dspcntr |= DISPLAY_PLANE_ENABLE;
2426
2427 if (INTEL_INFO(dev)->gen < 4) {
2428 if (intel_crtc->pipe == PIPE_B)
2429 dspcntr |= DISPPLANE_SEL_PIPE_B;
2430
2431 /* pipesrc and dspsize control the size that is scaled from,
2432 * which should always be the user's requested size.
2433 */
2434 I915_WRITE(DSPSIZE(plane),
2435 ((intel_crtc->config.pipe_src_h - 1) << 16) |
2436 (intel_crtc->config.pipe_src_w - 1));
2437 I915_WRITE(DSPPOS(plane), 0);
2438 }
2439
2440 switch (fb->pixel_format) {
2441 case DRM_FORMAT_C8:
2442 dspcntr |= DISPPLANE_8BPP;
2443 break;
2444 case DRM_FORMAT_XRGB1555:
2445 case DRM_FORMAT_ARGB1555:
2446 dspcntr |= DISPPLANE_BGRX555;
2447 break;
2448 case DRM_FORMAT_RGB565:
2449 dspcntr |= DISPPLANE_BGRX565;
2450 break;
2451 case DRM_FORMAT_XRGB8888:
2452 case DRM_FORMAT_ARGB8888:
2453 dspcntr |= DISPPLANE_BGRX888;
2454 break;
2455 case DRM_FORMAT_XBGR8888:
2456 case DRM_FORMAT_ABGR8888:
2457 dspcntr |= DISPPLANE_RGBX888;
2458 break;
2459 case DRM_FORMAT_XRGB2101010:
2460 case DRM_FORMAT_ARGB2101010:
2461 dspcntr |= DISPPLANE_BGRX101010;
2462 break;
2463 case DRM_FORMAT_XBGR2101010:
2464 case DRM_FORMAT_ABGR2101010:
2465 dspcntr |= DISPPLANE_RGBX101010;
2466 break;
2467 default:
2468 BUG();
2469 }
2470
2471 if (INTEL_INFO(dev)->gen >= 4 &&
2472 obj->tiling_mode != I915_TILING_NONE)
2473 dspcntr |= DISPPLANE_TILED;
2474
2475 if (IS_G4X(dev))
2476 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2477
2478 linear_offset = y * fb->pitches[0] + x * pixel_size;
2479
2480 if (INTEL_INFO(dev)->gen >= 4) {
2481 intel_crtc->dspaddr_offset =
2482 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2483 pixel_size,
2484 fb->pitches[0]);
2485 linear_offset -= intel_crtc->dspaddr_offset;
2486 } else {
2487 intel_crtc->dspaddr_offset = linear_offset;
2488 }
2489
2490 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2491 dspcntr |= DISPPLANE_ROTATE_180;
2492
2493 x += (intel_crtc->config.pipe_src_w - 1);
2494 y += (intel_crtc->config.pipe_src_h - 1);
2495
2496 /* Finding the last pixel of the last line of the display
2497 data and adding to linear_offset*/
2498 linear_offset +=
2499 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2500 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2501 }
2502
2503 I915_WRITE(reg, dspcntr);
2504
2505 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2506 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2507 fb->pitches[0]);
2508 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2509 if (INTEL_INFO(dev)->gen >= 4) {
2510 I915_WRITE(DSPSURF(plane),
2511 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2512 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2513 I915_WRITE(DSPLINOFF(plane), linear_offset);
2514 } else
2515 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2516 POSTING_READ(reg);
2517 }
2518
2519 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2520 struct drm_framebuffer *fb,
2521 int x, int y)
2522 {
2523 struct drm_device *dev = crtc->dev;
2524 struct drm_i915_private *dev_priv = dev->dev_private;
2525 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2526 struct drm_i915_gem_object *obj;
2527 int plane = intel_crtc->plane;
2528 unsigned long linear_offset;
2529 u32 dspcntr;
2530 u32 reg = DSPCNTR(plane);
2531 int pixel_size;
2532
2533 if (!intel_crtc->primary_enabled) {
2534 I915_WRITE(reg, 0);
2535 I915_WRITE(DSPSURF(plane), 0);
2536 POSTING_READ(reg);
2537 return;
2538 }
2539
2540 obj = intel_fb_obj(fb);
2541 if (WARN_ON(obj == NULL))
2542 return;
2543
2544 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2545
2546 dspcntr = DISPPLANE_GAMMA_ENABLE;
2547
2548 dspcntr |= DISPLAY_PLANE_ENABLE;
2549
2550 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2551 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2552
2553 switch (fb->pixel_format) {
2554 case DRM_FORMAT_C8:
2555 dspcntr |= DISPPLANE_8BPP;
2556 break;
2557 case DRM_FORMAT_RGB565:
2558 dspcntr |= DISPPLANE_BGRX565;
2559 break;
2560 case DRM_FORMAT_XRGB8888:
2561 case DRM_FORMAT_ARGB8888:
2562 dspcntr |= DISPPLANE_BGRX888;
2563 break;
2564 case DRM_FORMAT_XBGR8888:
2565 case DRM_FORMAT_ABGR8888:
2566 dspcntr |= DISPPLANE_RGBX888;
2567 break;
2568 case DRM_FORMAT_XRGB2101010:
2569 case DRM_FORMAT_ARGB2101010:
2570 dspcntr |= DISPPLANE_BGRX101010;
2571 break;
2572 case DRM_FORMAT_XBGR2101010:
2573 case DRM_FORMAT_ABGR2101010:
2574 dspcntr |= DISPPLANE_RGBX101010;
2575 break;
2576 default:
2577 BUG();
2578 }
2579
2580 if (obj->tiling_mode != I915_TILING_NONE)
2581 dspcntr |= DISPPLANE_TILED;
2582
2583 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2584 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2585
2586 linear_offset = y * fb->pitches[0] + x * pixel_size;
2587 intel_crtc->dspaddr_offset =
2588 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2589 pixel_size,
2590 fb->pitches[0]);
2591 linear_offset -= intel_crtc->dspaddr_offset;
2592 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2593 dspcntr |= DISPPLANE_ROTATE_180;
2594
2595 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2596 x += (intel_crtc->config.pipe_src_w - 1);
2597 y += (intel_crtc->config.pipe_src_h - 1);
2598
2599 /* Finding the last pixel of the last line of the display
2600 data and adding to linear_offset*/
2601 linear_offset +=
2602 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2603 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2604 }
2605 }
2606
2607 I915_WRITE(reg, dspcntr);
2608
2609 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2610 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2611 fb->pitches[0]);
2612 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2613 I915_WRITE(DSPSURF(plane),
2614 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2615 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2616 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2617 } else {
2618 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2619 I915_WRITE(DSPLINOFF(plane), linear_offset);
2620 }
2621 POSTING_READ(reg);
2622 }
2623
2624 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2625 static int
2626 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2627 int x, int y, enum mode_set_atomic state)
2628 {
2629 struct drm_device *dev = crtc->dev;
2630 struct drm_i915_private *dev_priv = dev->dev_private;
2631
2632 if (dev_priv->display.disable_fbc)
2633 dev_priv->display.disable_fbc(dev);
2634 intel_increase_pllclock(dev, to_intel_crtc(crtc)->pipe);
2635
2636 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2637
2638 return 0;
2639 }
2640
2641 void intel_display_handle_reset(struct drm_device *dev)
2642 {
2643 struct drm_i915_private *dev_priv = dev->dev_private;
2644 struct drm_crtc *crtc;
2645
2646 /*
2647 * Flips in the rings have been nuked by the reset,
2648 * so complete all pending flips so that user space
2649 * will get its events and not get stuck.
2650 *
2651 * Also update the base address of all primary
2652 * planes to the the last fb to make sure we're
2653 * showing the correct fb after a reset.
2654 *
2655 * Need to make two loops over the crtcs so that we
2656 * don't try to grab a crtc mutex before the
2657 * pending_flip_queue really got woken up.
2658 */
2659
2660 for_each_crtc(dev, crtc) {
2661 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2662 enum plane plane = intel_crtc->plane;
2663
2664 intel_prepare_page_flip(dev, plane);
2665 intel_finish_page_flip_plane(dev, plane);
2666 }
2667
2668 for_each_crtc(dev, crtc) {
2669 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2670
2671 drm_modeset_lock(&crtc->mutex, NULL);
2672 /*
2673 * FIXME: Once we have proper support for primary planes (and
2674 * disabling them without disabling the entire crtc) allow again
2675 * a NULL crtc->primary->fb.
2676 */
2677 if (intel_crtc->active && crtc->primary->fb)
2678 dev_priv->display.update_primary_plane(crtc,
2679 crtc->primary->fb,
2680 crtc->x,
2681 crtc->y);
2682 drm_modeset_unlock(&crtc->mutex);
2683 }
2684 }
2685
2686 static int
2687 intel_finish_fb(struct drm_framebuffer *old_fb)
2688 {
2689 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2690 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2691 bool was_interruptible = dev_priv->mm.interruptible;
2692 int ret;
2693
2694 /* Big Hammer, we also need to ensure that any pending
2695 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2696 * current scanout is retired before unpinning the old
2697 * framebuffer.
2698 *
2699 * This should only fail upon a hung GPU, in which case we
2700 * can safely continue.
2701 */
2702 dev_priv->mm.interruptible = false;
2703 ret = i915_gem_object_finish_gpu(obj);
2704 dev_priv->mm.interruptible = was_interruptible;
2705
2706 return ret;
2707 }
2708
2709 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2710 {
2711 struct drm_device *dev = crtc->dev;
2712 struct drm_i915_private *dev_priv = dev->dev_private;
2713 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2714 unsigned long flags;
2715 bool pending;
2716
2717 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2718 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2719 return false;
2720
2721 spin_lock_irqsave(&dev->event_lock, flags);
2722 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2723 spin_unlock_irqrestore(&dev->event_lock, flags);
2724
2725 return pending;
2726 }
2727
2728 static int
2729 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2730 struct drm_framebuffer *fb)
2731 {
2732 struct drm_device *dev = crtc->dev;
2733 struct drm_i915_private *dev_priv = dev->dev_private;
2734 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2735 enum pipe pipe = intel_crtc->pipe;
2736 struct drm_framebuffer *old_fb = crtc->primary->fb;
2737 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2738 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
2739 int ret;
2740
2741 if (intel_crtc_has_pending_flip(crtc)) {
2742 DRM_ERROR("pipe is still busy with an old pageflip\n");
2743 return -EBUSY;
2744 }
2745
2746 /* no fb bound */
2747 if (!fb) {
2748 DRM_ERROR("No FB bound\n");
2749 return 0;
2750 }
2751
2752 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2753 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2754 plane_name(intel_crtc->plane),
2755 INTEL_INFO(dev)->num_pipes);
2756 return -EINVAL;
2757 }
2758
2759 mutex_lock(&dev->struct_mutex);
2760 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
2761 if (ret == 0)
2762 i915_gem_track_fb(old_obj, obj,
2763 INTEL_FRONTBUFFER_PRIMARY(pipe));
2764 mutex_unlock(&dev->struct_mutex);
2765 if (ret != 0) {
2766 DRM_ERROR("pin & fence failed\n");
2767 return ret;
2768 }
2769
2770 /*
2771 * Update pipe size and adjust fitter if needed: the reason for this is
2772 * that in compute_mode_changes we check the native mode (not the pfit
2773 * mode) to see if we can flip rather than do a full mode set. In the
2774 * fastboot case, we'll flip, but if we don't update the pipesrc and
2775 * pfit state, we'll end up with a big fb scanned out into the wrong
2776 * sized surface.
2777 *
2778 * To fix this properly, we need to hoist the checks up into
2779 * compute_mode_changes (or above), check the actual pfit state and
2780 * whether the platform allows pfit disable with pipe active, and only
2781 * then update the pipesrc and pfit state, even on the flip path.
2782 */
2783 if (i915.fastboot) {
2784 const struct drm_display_mode *adjusted_mode =
2785 &intel_crtc->config.adjusted_mode;
2786
2787 I915_WRITE(PIPESRC(intel_crtc->pipe),
2788 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2789 (adjusted_mode->crtc_vdisplay - 1));
2790 if (!intel_crtc->config.pch_pfit.enabled &&
2791 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2792 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2793 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2794 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2795 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2796 }
2797 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2798 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2799 }
2800
2801 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2802
2803 if (intel_crtc->active)
2804 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2805
2806 crtc->primary->fb = fb;
2807 crtc->x = x;
2808 crtc->y = y;
2809
2810 if (old_fb) {
2811 if (intel_crtc->active && old_fb != fb)
2812 intel_wait_for_vblank(dev, intel_crtc->pipe);
2813 mutex_lock(&dev->struct_mutex);
2814 intel_unpin_fb_obj(old_obj);
2815 mutex_unlock(&dev->struct_mutex);
2816 }
2817
2818 mutex_lock(&dev->struct_mutex);
2819 intel_update_fbc(dev);
2820 mutex_unlock(&dev->struct_mutex);
2821
2822 return 0;
2823 }
2824
2825 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2826 {
2827 struct drm_device *dev = crtc->dev;
2828 struct drm_i915_private *dev_priv = dev->dev_private;
2829 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2830 int pipe = intel_crtc->pipe;
2831 u32 reg, temp;
2832
2833 /* enable normal train */
2834 reg = FDI_TX_CTL(pipe);
2835 temp = I915_READ(reg);
2836 if (IS_IVYBRIDGE(dev)) {
2837 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2838 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2839 } else {
2840 temp &= ~FDI_LINK_TRAIN_NONE;
2841 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2842 }
2843 I915_WRITE(reg, temp);
2844
2845 reg = FDI_RX_CTL(pipe);
2846 temp = I915_READ(reg);
2847 if (HAS_PCH_CPT(dev)) {
2848 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2849 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2850 } else {
2851 temp &= ~FDI_LINK_TRAIN_NONE;
2852 temp |= FDI_LINK_TRAIN_NONE;
2853 }
2854 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2855
2856 /* wait one idle pattern time */
2857 POSTING_READ(reg);
2858 udelay(1000);
2859
2860 /* IVB wants error correction enabled */
2861 if (IS_IVYBRIDGE(dev))
2862 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2863 FDI_FE_ERRC_ENABLE);
2864 }
2865
2866 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2867 {
2868 return crtc->base.enabled && crtc->active &&
2869 crtc->config.has_pch_encoder;
2870 }
2871
2872 static void ivb_modeset_global_resources(struct drm_device *dev)
2873 {
2874 struct drm_i915_private *dev_priv = dev->dev_private;
2875 struct intel_crtc *pipe_B_crtc =
2876 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2877 struct intel_crtc *pipe_C_crtc =
2878 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2879 uint32_t temp;
2880
2881 /*
2882 * When everything is off disable fdi C so that we could enable fdi B
2883 * with all lanes. Note that we don't care about enabled pipes without
2884 * an enabled pch encoder.
2885 */
2886 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2887 !pipe_has_enabled_pch(pipe_C_crtc)) {
2888 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2889 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2890
2891 temp = I915_READ(SOUTH_CHICKEN1);
2892 temp &= ~FDI_BC_BIFURCATION_SELECT;
2893 DRM_DEBUG_KMS("disabling fdi C rx\n");
2894 I915_WRITE(SOUTH_CHICKEN1, temp);
2895 }
2896 }
2897
2898 /* The FDI link training functions for ILK/Ibexpeak. */
2899 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2900 {
2901 struct drm_device *dev = crtc->dev;
2902 struct drm_i915_private *dev_priv = dev->dev_private;
2903 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2904 int pipe = intel_crtc->pipe;
2905 u32 reg, temp, tries;
2906
2907 /* FDI needs bits from pipe first */
2908 assert_pipe_enabled(dev_priv, pipe);
2909
2910 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2911 for train result */
2912 reg = FDI_RX_IMR(pipe);
2913 temp = I915_READ(reg);
2914 temp &= ~FDI_RX_SYMBOL_LOCK;
2915 temp &= ~FDI_RX_BIT_LOCK;
2916 I915_WRITE(reg, temp);
2917 I915_READ(reg);
2918 udelay(150);
2919
2920 /* enable CPU FDI TX and PCH FDI RX */
2921 reg = FDI_TX_CTL(pipe);
2922 temp = I915_READ(reg);
2923 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2924 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2925 temp &= ~FDI_LINK_TRAIN_NONE;
2926 temp |= FDI_LINK_TRAIN_PATTERN_1;
2927 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2928
2929 reg = FDI_RX_CTL(pipe);
2930 temp = I915_READ(reg);
2931 temp &= ~FDI_LINK_TRAIN_NONE;
2932 temp |= FDI_LINK_TRAIN_PATTERN_1;
2933 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2934
2935 POSTING_READ(reg);
2936 udelay(150);
2937
2938 /* Ironlake workaround, enable clock pointer after FDI enable*/
2939 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2940 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2941 FDI_RX_PHASE_SYNC_POINTER_EN);
2942
2943 reg = FDI_RX_IIR(pipe);
2944 for (tries = 0; tries < 5; tries++) {
2945 temp = I915_READ(reg);
2946 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2947
2948 if ((temp & FDI_RX_BIT_LOCK)) {
2949 DRM_DEBUG_KMS("FDI train 1 done.\n");
2950 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2951 break;
2952 }
2953 }
2954 if (tries == 5)
2955 DRM_ERROR("FDI train 1 fail!\n");
2956
2957 /* Train 2 */
2958 reg = FDI_TX_CTL(pipe);
2959 temp = I915_READ(reg);
2960 temp &= ~FDI_LINK_TRAIN_NONE;
2961 temp |= FDI_LINK_TRAIN_PATTERN_2;
2962 I915_WRITE(reg, temp);
2963
2964 reg = FDI_RX_CTL(pipe);
2965 temp = I915_READ(reg);
2966 temp &= ~FDI_LINK_TRAIN_NONE;
2967 temp |= FDI_LINK_TRAIN_PATTERN_2;
2968 I915_WRITE(reg, temp);
2969
2970 POSTING_READ(reg);
2971 udelay(150);
2972
2973 reg = FDI_RX_IIR(pipe);
2974 for (tries = 0; tries < 5; tries++) {
2975 temp = I915_READ(reg);
2976 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2977
2978 if (temp & FDI_RX_SYMBOL_LOCK) {
2979 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2980 DRM_DEBUG_KMS("FDI train 2 done.\n");
2981 break;
2982 }
2983 }
2984 if (tries == 5)
2985 DRM_ERROR("FDI train 2 fail!\n");
2986
2987 DRM_DEBUG_KMS("FDI train done\n");
2988
2989 }
2990
2991 static const int snb_b_fdi_train_param[] = {
2992 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2993 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2994 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2995 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2996 };
2997
2998 /* The FDI link training functions for SNB/Cougarpoint. */
2999 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3000 {
3001 struct drm_device *dev = crtc->dev;
3002 struct drm_i915_private *dev_priv = dev->dev_private;
3003 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3004 int pipe = intel_crtc->pipe;
3005 u32 reg, temp, i, retry;
3006
3007 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3008 for train result */
3009 reg = FDI_RX_IMR(pipe);
3010 temp = I915_READ(reg);
3011 temp &= ~FDI_RX_SYMBOL_LOCK;
3012 temp &= ~FDI_RX_BIT_LOCK;
3013 I915_WRITE(reg, temp);
3014
3015 POSTING_READ(reg);
3016 udelay(150);
3017
3018 /* enable CPU FDI TX and PCH FDI RX */
3019 reg = FDI_TX_CTL(pipe);
3020 temp = I915_READ(reg);
3021 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3022 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3023 temp &= ~FDI_LINK_TRAIN_NONE;
3024 temp |= FDI_LINK_TRAIN_PATTERN_1;
3025 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3026 /* SNB-B */
3027 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3028 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3029
3030 I915_WRITE(FDI_RX_MISC(pipe),
3031 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3032
3033 reg = FDI_RX_CTL(pipe);
3034 temp = I915_READ(reg);
3035 if (HAS_PCH_CPT(dev)) {
3036 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3037 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3038 } else {
3039 temp &= ~FDI_LINK_TRAIN_NONE;
3040 temp |= FDI_LINK_TRAIN_PATTERN_1;
3041 }
3042 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3043
3044 POSTING_READ(reg);
3045 udelay(150);
3046
3047 for (i = 0; i < 4; i++) {
3048 reg = FDI_TX_CTL(pipe);
3049 temp = I915_READ(reg);
3050 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3051 temp |= snb_b_fdi_train_param[i];
3052 I915_WRITE(reg, temp);
3053
3054 POSTING_READ(reg);
3055 udelay(500);
3056
3057 for (retry = 0; retry < 5; retry++) {
3058 reg = FDI_RX_IIR(pipe);
3059 temp = I915_READ(reg);
3060 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3061 if (temp & FDI_RX_BIT_LOCK) {
3062 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3063 DRM_DEBUG_KMS("FDI train 1 done.\n");
3064 break;
3065 }
3066 udelay(50);
3067 }
3068 if (retry < 5)
3069 break;
3070 }
3071 if (i == 4)
3072 DRM_ERROR("FDI train 1 fail!\n");
3073
3074 /* Train 2 */
3075 reg = FDI_TX_CTL(pipe);
3076 temp = I915_READ(reg);
3077 temp &= ~FDI_LINK_TRAIN_NONE;
3078 temp |= FDI_LINK_TRAIN_PATTERN_2;
3079 if (IS_GEN6(dev)) {
3080 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3081 /* SNB-B */
3082 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3083 }
3084 I915_WRITE(reg, temp);
3085
3086 reg = FDI_RX_CTL(pipe);
3087 temp = I915_READ(reg);
3088 if (HAS_PCH_CPT(dev)) {
3089 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3090 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3091 } else {
3092 temp &= ~FDI_LINK_TRAIN_NONE;
3093 temp |= FDI_LINK_TRAIN_PATTERN_2;
3094 }
3095 I915_WRITE(reg, temp);
3096
3097 POSTING_READ(reg);
3098 udelay(150);
3099
3100 for (i = 0; i < 4; i++) {
3101 reg = FDI_TX_CTL(pipe);
3102 temp = I915_READ(reg);
3103 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3104 temp |= snb_b_fdi_train_param[i];
3105 I915_WRITE(reg, temp);
3106
3107 POSTING_READ(reg);
3108 udelay(500);
3109
3110 for (retry = 0; retry < 5; retry++) {
3111 reg = FDI_RX_IIR(pipe);
3112 temp = I915_READ(reg);
3113 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3114 if (temp & FDI_RX_SYMBOL_LOCK) {
3115 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3116 DRM_DEBUG_KMS("FDI train 2 done.\n");
3117 break;
3118 }
3119 udelay(50);
3120 }
3121 if (retry < 5)
3122 break;
3123 }
3124 if (i == 4)
3125 DRM_ERROR("FDI train 2 fail!\n");
3126
3127 DRM_DEBUG_KMS("FDI train done.\n");
3128 }
3129
3130 /* Manual link training for Ivy Bridge A0 parts */
3131 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3132 {
3133 struct drm_device *dev = crtc->dev;
3134 struct drm_i915_private *dev_priv = dev->dev_private;
3135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3136 int pipe = intel_crtc->pipe;
3137 u32 reg, temp, i, j;
3138
3139 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3140 for train result */
3141 reg = FDI_RX_IMR(pipe);
3142 temp = I915_READ(reg);
3143 temp &= ~FDI_RX_SYMBOL_LOCK;
3144 temp &= ~FDI_RX_BIT_LOCK;
3145 I915_WRITE(reg, temp);
3146
3147 POSTING_READ(reg);
3148 udelay(150);
3149
3150 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3151 I915_READ(FDI_RX_IIR(pipe)));
3152
3153 /* Try each vswing and preemphasis setting twice before moving on */
3154 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3155 /* disable first in case we need to retry */
3156 reg = FDI_TX_CTL(pipe);
3157 temp = I915_READ(reg);
3158 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3159 temp &= ~FDI_TX_ENABLE;
3160 I915_WRITE(reg, temp);
3161
3162 reg = FDI_RX_CTL(pipe);
3163 temp = I915_READ(reg);
3164 temp &= ~FDI_LINK_TRAIN_AUTO;
3165 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3166 temp &= ~FDI_RX_ENABLE;
3167 I915_WRITE(reg, temp);
3168
3169 /* enable CPU FDI TX and PCH FDI RX */
3170 reg = FDI_TX_CTL(pipe);
3171 temp = I915_READ(reg);
3172 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3173 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3174 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3175 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3176 temp |= snb_b_fdi_train_param[j/2];
3177 temp |= FDI_COMPOSITE_SYNC;
3178 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3179
3180 I915_WRITE(FDI_RX_MISC(pipe),
3181 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3182
3183 reg = FDI_RX_CTL(pipe);
3184 temp = I915_READ(reg);
3185 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3186 temp |= FDI_COMPOSITE_SYNC;
3187 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3188
3189 POSTING_READ(reg);
3190 udelay(1); /* should be 0.5us */
3191
3192 for (i = 0; i < 4; i++) {
3193 reg = FDI_RX_IIR(pipe);
3194 temp = I915_READ(reg);
3195 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3196
3197 if (temp & FDI_RX_BIT_LOCK ||
3198 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3199 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3200 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3201 i);
3202 break;
3203 }
3204 udelay(1); /* should be 0.5us */
3205 }
3206 if (i == 4) {
3207 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3208 continue;
3209 }
3210
3211 /* Train 2 */
3212 reg = FDI_TX_CTL(pipe);
3213 temp = I915_READ(reg);
3214 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3215 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3216 I915_WRITE(reg, temp);
3217
3218 reg = FDI_RX_CTL(pipe);
3219 temp = I915_READ(reg);
3220 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3221 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3222 I915_WRITE(reg, temp);
3223
3224 POSTING_READ(reg);
3225 udelay(2); /* should be 1.5us */
3226
3227 for (i = 0; i < 4; i++) {
3228 reg = FDI_RX_IIR(pipe);
3229 temp = I915_READ(reg);
3230 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3231
3232 if (temp & FDI_RX_SYMBOL_LOCK ||
3233 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3234 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3235 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3236 i);
3237 goto train_done;
3238 }
3239 udelay(2); /* should be 1.5us */
3240 }
3241 if (i == 4)
3242 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3243 }
3244
3245 train_done:
3246 DRM_DEBUG_KMS("FDI train done.\n");
3247 }
3248
3249 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3250 {
3251 struct drm_device *dev = intel_crtc->base.dev;
3252 struct drm_i915_private *dev_priv = dev->dev_private;
3253 int pipe = intel_crtc->pipe;
3254 u32 reg, temp;
3255
3256
3257 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3258 reg = FDI_RX_CTL(pipe);
3259 temp = I915_READ(reg);
3260 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3261 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3262 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3263 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3264
3265 POSTING_READ(reg);
3266 udelay(200);
3267
3268 /* Switch from Rawclk to PCDclk */
3269 temp = I915_READ(reg);
3270 I915_WRITE(reg, temp | FDI_PCDCLK);
3271
3272 POSTING_READ(reg);
3273 udelay(200);
3274
3275 /* Enable CPU FDI TX PLL, always on for Ironlake */
3276 reg = FDI_TX_CTL(pipe);
3277 temp = I915_READ(reg);
3278 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3279 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3280
3281 POSTING_READ(reg);
3282 udelay(100);
3283 }
3284 }
3285
3286 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3287 {
3288 struct drm_device *dev = intel_crtc->base.dev;
3289 struct drm_i915_private *dev_priv = dev->dev_private;
3290 int pipe = intel_crtc->pipe;
3291 u32 reg, temp;
3292
3293 /* Switch from PCDclk to Rawclk */
3294 reg = FDI_RX_CTL(pipe);
3295 temp = I915_READ(reg);
3296 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3297
3298 /* Disable CPU FDI TX PLL */
3299 reg = FDI_TX_CTL(pipe);
3300 temp = I915_READ(reg);
3301 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3302
3303 POSTING_READ(reg);
3304 udelay(100);
3305
3306 reg = FDI_RX_CTL(pipe);
3307 temp = I915_READ(reg);
3308 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3309
3310 /* Wait for the clocks to turn off. */
3311 POSTING_READ(reg);
3312 udelay(100);
3313 }
3314
3315 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3316 {
3317 struct drm_device *dev = crtc->dev;
3318 struct drm_i915_private *dev_priv = dev->dev_private;
3319 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3320 int pipe = intel_crtc->pipe;
3321 u32 reg, temp;
3322
3323 /* disable CPU FDI tx and PCH FDI rx */
3324 reg = FDI_TX_CTL(pipe);
3325 temp = I915_READ(reg);
3326 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3327 POSTING_READ(reg);
3328
3329 reg = FDI_RX_CTL(pipe);
3330 temp = I915_READ(reg);
3331 temp &= ~(0x7 << 16);
3332 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3333 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3334
3335 POSTING_READ(reg);
3336 udelay(100);
3337
3338 /* Ironlake workaround, disable clock pointer after downing FDI */
3339 if (HAS_PCH_IBX(dev))
3340 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3341
3342 /* still set train pattern 1 */
3343 reg = FDI_TX_CTL(pipe);
3344 temp = I915_READ(reg);
3345 temp &= ~FDI_LINK_TRAIN_NONE;
3346 temp |= FDI_LINK_TRAIN_PATTERN_1;
3347 I915_WRITE(reg, temp);
3348
3349 reg = FDI_RX_CTL(pipe);
3350 temp = I915_READ(reg);
3351 if (HAS_PCH_CPT(dev)) {
3352 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3353 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3354 } else {
3355 temp &= ~FDI_LINK_TRAIN_NONE;
3356 temp |= FDI_LINK_TRAIN_PATTERN_1;
3357 }
3358 /* BPC in FDI rx is consistent with that in PIPECONF */
3359 temp &= ~(0x07 << 16);
3360 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3361 I915_WRITE(reg, temp);
3362
3363 POSTING_READ(reg);
3364 udelay(100);
3365 }
3366
3367 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3368 {
3369 struct intel_crtc *crtc;
3370
3371 /* Note that we don't need to be called with mode_config.lock here
3372 * as our list of CRTC objects is static for the lifetime of the
3373 * device and so cannot disappear as we iterate. Similarly, we can
3374 * happily treat the predicates as racy, atomic checks as userspace
3375 * cannot claim and pin a new fb without at least acquring the
3376 * struct_mutex and so serialising with us.
3377 */
3378 for_each_intel_crtc(dev, crtc) {
3379 if (atomic_read(&crtc->unpin_work_count) == 0)
3380 continue;
3381
3382 if (crtc->unpin_work)
3383 intel_wait_for_vblank(dev, crtc->pipe);
3384
3385 return true;
3386 }
3387
3388 return false;
3389 }
3390
3391 static void page_flip_completed(struct intel_crtc *intel_crtc)
3392 {
3393 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3394 struct intel_unpin_work *work = intel_crtc->unpin_work;
3395
3396 /* ensure that the unpin work is consistent wrt ->pending. */
3397 smp_rmb();
3398 intel_crtc->unpin_work = NULL;
3399
3400 if (work->event)
3401 drm_send_vblank_event(intel_crtc->base.dev,
3402 intel_crtc->pipe,
3403 work->event);
3404
3405 drm_crtc_vblank_put(&intel_crtc->base);
3406
3407 wake_up_all(&dev_priv->pending_flip_queue);
3408 queue_work(dev_priv->wq, &work->work);
3409
3410 trace_i915_flip_complete(intel_crtc->plane,
3411 work->pending_flip_obj);
3412 }
3413
3414 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3415 {
3416 struct drm_device *dev = crtc->dev;
3417 struct drm_i915_private *dev_priv = dev->dev_private;
3418
3419 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3420 WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3421 !intel_crtc_has_pending_flip(crtc),
3422 60*HZ) == 0);
3423
3424 if (crtc->primary->fb) {
3425 mutex_lock(&dev->struct_mutex);
3426 intel_finish_fb(crtc->primary->fb);
3427 mutex_unlock(&dev->struct_mutex);
3428 }
3429 }
3430
3431 /* Program iCLKIP clock to the desired frequency */
3432 static void lpt_program_iclkip(struct drm_crtc *crtc)
3433 {
3434 struct drm_device *dev = crtc->dev;
3435 struct drm_i915_private *dev_priv = dev->dev_private;
3436 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3437 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3438 u32 temp;
3439
3440 mutex_lock(&dev_priv->dpio_lock);
3441
3442 /* It is necessary to ungate the pixclk gate prior to programming
3443 * the divisors, and gate it back when it is done.
3444 */
3445 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3446
3447 /* Disable SSCCTL */
3448 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3449 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3450 SBI_SSCCTL_DISABLE,
3451 SBI_ICLK);
3452
3453 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3454 if (clock == 20000) {
3455 auxdiv = 1;
3456 divsel = 0x41;
3457 phaseinc = 0x20;
3458 } else {
3459 /* The iCLK virtual clock root frequency is in MHz,
3460 * but the adjusted_mode->crtc_clock in in KHz. To get the
3461 * divisors, it is necessary to divide one by another, so we
3462 * convert the virtual clock precision to KHz here for higher
3463 * precision.
3464 */
3465 u32 iclk_virtual_root_freq = 172800 * 1000;
3466 u32 iclk_pi_range = 64;
3467 u32 desired_divisor, msb_divisor_value, pi_value;
3468
3469 desired_divisor = (iclk_virtual_root_freq / clock);
3470 msb_divisor_value = desired_divisor / iclk_pi_range;
3471 pi_value = desired_divisor % iclk_pi_range;
3472
3473 auxdiv = 0;
3474 divsel = msb_divisor_value - 2;
3475 phaseinc = pi_value;
3476 }
3477
3478 /* This should not happen with any sane values */
3479 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3480 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3481 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3482 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3483
3484 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3485 clock,
3486 auxdiv,
3487 divsel,
3488 phasedir,
3489 phaseinc);
3490
3491 /* Program SSCDIVINTPHASE6 */
3492 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3493 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3494 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3495 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3496 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3497 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3498 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3499 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3500
3501 /* Program SSCAUXDIV */
3502 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3503 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3504 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3505 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3506
3507 /* Enable modulator and associated divider */
3508 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3509 temp &= ~SBI_SSCCTL_DISABLE;
3510 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3511
3512 /* Wait for initialization time */
3513 udelay(24);
3514
3515 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3516
3517 mutex_unlock(&dev_priv->dpio_lock);
3518 }
3519
3520 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3521 enum pipe pch_transcoder)
3522 {
3523 struct drm_device *dev = crtc->base.dev;
3524 struct drm_i915_private *dev_priv = dev->dev_private;
3525 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3526
3527 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3528 I915_READ(HTOTAL(cpu_transcoder)));
3529 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3530 I915_READ(HBLANK(cpu_transcoder)));
3531 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3532 I915_READ(HSYNC(cpu_transcoder)));
3533
3534 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3535 I915_READ(VTOTAL(cpu_transcoder)));
3536 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3537 I915_READ(VBLANK(cpu_transcoder)));
3538 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3539 I915_READ(VSYNC(cpu_transcoder)));
3540 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3541 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3542 }
3543
3544 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3545 {
3546 struct drm_i915_private *dev_priv = dev->dev_private;
3547 uint32_t temp;
3548
3549 temp = I915_READ(SOUTH_CHICKEN1);
3550 if (temp & FDI_BC_BIFURCATION_SELECT)
3551 return;
3552
3553 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3554 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3555
3556 temp |= FDI_BC_BIFURCATION_SELECT;
3557 DRM_DEBUG_KMS("enabling fdi C rx\n");
3558 I915_WRITE(SOUTH_CHICKEN1, temp);
3559 POSTING_READ(SOUTH_CHICKEN1);
3560 }
3561
3562 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3563 {
3564 struct drm_device *dev = intel_crtc->base.dev;
3565 struct drm_i915_private *dev_priv = dev->dev_private;
3566
3567 switch (intel_crtc->pipe) {
3568 case PIPE_A:
3569 break;
3570 case PIPE_B:
3571 if (intel_crtc->config.fdi_lanes > 2)
3572 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3573 else
3574 cpt_enable_fdi_bc_bifurcation(dev);
3575
3576 break;
3577 case PIPE_C:
3578 cpt_enable_fdi_bc_bifurcation(dev);
3579
3580 break;
3581 default:
3582 BUG();
3583 }
3584 }
3585
3586 /*
3587 * Enable PCH resources required for PCH ports:
3588 * - PCH PLLs
3589 * - FDI training & RX/TX
3590 * - update transcoder timings
3591 * - DP transcoding bits
3592 * - transcoder
3593 */
3594 static void ironlake_pch_enable(struct drm_crtc *crtc)
3595 {
3596 struct drm_device *dev = crtc->dev;
3597 struct drm_i915_private *dev_priv = dev->dev_private;
3598 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3599 int pipe = intel_crtc->pipe;
3600 u32 reg, temp;
3601
3602 assert_pch_transcoder_disabled(dev_priv, pipe);
3603
3604 if (IS_IVYBRIDGE(dev))
3605 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3606
3607 /* Write the TU size bits before fdi link training, so that error
3608 * detection works. */
3609 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3610 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3611
3612 /* For PCH output, training FDI link */
3613 dev_priv->display.fdi_link_train(crtc);
3614
3615 /* We need to program the right clock selection before writing the pixel
3616 * mutliplier into the DPLL. */
3617 if (HAS_PCH_CPT(dev)) {
3618 u32 sel;
3619
3620 temp = I915_READ(PCH_DPLL_SEL);
3621 temp |= TRANS_DPLL_ENABLE(pipe);
3622 sel = TRANS_DPLLB_SEL(pipe);
3623 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3624 temp |= sel;
3625 else
3626 temp &= ~sel;
3627 I915_WRITE(PCH_DPLL_SEL, temp);
3628 }
3629
3630 /* XXX: pch pll's can be enabled any time before we enable the PCH
3631 * transcoder, and we actually should do this to not upset any PCH
3632 * transcoder that already use the clock when we share it.
3633 *
3634 * Note that enable_shared_dpll tries to do the right thing, but
3635 * get_shared_dpll unconditionally resets the pll - we need that to have
3636 * the right LVDS enable sequence. */
3637 intel_enable_shared_dpll(intel_crtc);
3638
3639 /* set transcoder timing, panel must allow it */
3640 assert_panel_unlocked(dev_priv, pipe);
3641 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3642
3643 intel_fdi_normal_train(crtc);
3644
3645 /* For PCH DP, enable TRANS_DP_CTL */
3646 if (HAS_PCH_CPT(dev) &&
3647 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3648 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3649 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3650 reg = TRANS_DP_CTL(pipe);
3651 temp = I915_READ(reg);
3652 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3653 TRANS_DP_SYNC_MASK |
3654 TRANS_DP_BPC_MASK);
3655 temp |= (TRANS_DP_OUTPUT_ENABLE |
3656 TRANS_DP_ENH_FRAMING);
3657 temp |= bpc << 9; /* same format but at 11:9 */
3658
3659 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3660 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3661 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3662 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3663
3664 switch (intel_trans_dp_port_sel(crtc)) {
3665 case PCH_DP_B:
3666 temp |= TRANS_DP_PORT_SEL_B;
3667 break;
3668 case PCH_DP_C:
3669 temp |= TRANS_DP_PORT_SEL_C;
3670 break;
3671 case PCH_DP_D:
3672 temp |= TRANS_DP_PORT_SEL_D;
3673 break;
3674 default:
3675 BUG();
3676 }
3677
3678 I915_WRITE(reg, temp);
3679 }
3680
3681 ironlake_enable_pch_transcoder(dev_priv, pipe);
3682 }
3683
3684 static void lpt_pch_enable(struct drm_crtc *crtc)
3685 {
3686 struct drm_device *dev = crtc->dev;
3687 struct drm_i915_private *dev_priv = dev->dev_private;
3688 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3689 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3690
3691 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3692
3693 lpt_program_iclkip(crtc);
3694
3695 /* Set transcoder timing. */
3696 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3697
3698 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3699 }
3700
3701 void intel_put_shared_dpll(struct intel_crtc *crtc)
3702 {
3703 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3704
3705 if (pll == NULL)
3706 return;
3707
3708 if (pll->refcount == 0) {
3709 WARN(1, "bad %s refcount\n", pll->name);
3710 return;
3711 }
3712
3713 if (--pll->refcount == 0) {
3714 WARN_ON(pll->on);
3715 WARN_ON(pll->active);
3716 }
3717
3718 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3719 }
3720
3721 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3722 {
3723 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3724 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3725 enum intel_dpll_id i;
3726
3727 if (pll) {
3728 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3729 crtc->base.base.id, pll->name);
3730 intel_put_shared_dpll(crtc);
3731 }
3732
3733 if (HAS_PCH_IBX(dev_priv->dev)) {
3734 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3735 i = (enum intel_dpll_id) crtc->pipe;
3736 pll = &dev_priv->shared_dplls[i];
3737
3738 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3739 crtc->base.base.id, pll->name);
3740
3741 WARN_ON(pll->refcount);
3742
3743 goto found;
3744 }
3745
3746 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3747 pll = &dev_priv->shared_dplls[i];
3748
3749 /* Only want to check enabled timings first */
3750 if (pll->refcount == 0)
3751 continue;
3752
3753 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3754 sizeof(pll->hw_state)) == 0) {
3755 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3756 crtc->base.base.id,
3757 pll->name, pll->refcount, pll->active);
3758
3759 goto found;
3760 }
3761 }
3762
3763 /* Ok no matching timings, maybe there's a free one? */
3764 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3765 pll = &dev_priv->shared_dplls[i];
3766 if (pll->refcount == 0) {
3767 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3768 crtc->base.base.id, pll->name);
3769 goto found;
3770 }
3771 }
3772
3773 return NULL;
3774
3775 found:
3776 if (pll->refcount == 0)
3777 pll->hw_state = crtc->config.dpll_hw_state;
3778
3779 crtc->config.shared_dpll = i;
3780 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3781 pipe_name(crtc->pipe));
3782
3783 pll->refcount++;
3784
3785 return pll;
3786 }
3787
3788 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3789 {
3790 struct drm_i915_private *dev_priv = dev->dev_private;
3791 int dslreg = PIPEDSL(pipe);
3792 u32 temp;
3793
3794 temp = I915_READ(dslreg);
3795 udelay(500);
3796 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3797 if (wait_for(I915_READ(dslreg) != temp, 5))
3798 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3799 }
3800 }
3801
3802 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3803 {
3804 struct drm_device *dev = crtc->base.dev;
3805 struct drm_i915_private *dev_priv = dev->dev_private;
3806 int pipe = crtc->pipe;
3807
3808 if (crtc->config.pch_pfit.enabled) {
3809 /* Force use of hard-coded filter coefficients
3810 * as some pre-programmed values are broken,
3811 * e.g. x201.
3812 */
3813 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3814 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3815 PF_PIPE_SEL_IVB(pipe));
3816 else
3817 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3818 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3819 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3820 }
3821 }
3822
3823 static void intel_enable_planes(struct drm_crtc *crtc)
3824 {
3825 struct drm_device *dev = crtc->dev;
3826 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3827 struct drm_plane *plane;
3828 struct intel_plane *intel_plane;
3829
3830 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3831 intel_plane = to_intel_plane(plane);
3832 if (intel_plane->pipe == pipe)
3833 intel_plane_restore(&intel_plane->base);
3834 }
3835 }
3836
3837 static void intel_disable_planes(struct drm_crtc *crtc)
3838 {
3839 struct drm_device *dev = crtc->dev;
3840 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3841 struct drm_plane *plane;
3842 struct intel_plane *intel_plane;
3843
3844 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3845 intel_plane = to_intel_plane(plane);
3846 if (intel_plane->pipe == pipe)
3847 intel_plane_disable(&intel_plane->base);
3848 }
3849 }
3850
3851 void hsw_enable_ips(struct intel_crtc *crtc)
3852 {
3853 struct drm_device *dev = crtc->base.dev;
3854 struct drm_i915_private *dev_priv = dev->dev_private;
3855
3856 if (!crtc->config.ips_enabled)
3857 return;
3858
3859 /* We can only enable IPS after we enable a plane and wait for a vblank */
3860 intel_wait_for_vblank(dev, crtc->pipe);
3861
3862 assert_plane_enabled(dev_priv, crtc->plane);
3863 if (IS_BROADWELL(dev)) {
3864 mutex_lock(&dev_priv->rps.hw_lock);
3865 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3866 mutex_unlock(&dev_priv->rps.hw_lock);
3867 /* Quoting Art Runyan: "its not safe to expect any particular
3868 * value in IPS_CTL bit 31 after enabling IPS through the
3869 * mailbox." Moreover, the mailbox may return a bogus state,
3870 * so we need to just enable it and continue on.
3871 */
3872 } else {
3873 I915_WRITE(IPS_CTL, IPS_ENABLE);
3874 /* The bit only becomes 1 in the next vblank, so this wait here
3875 * is essentially intel_wait_for_vblank. If we don't have this
3876 * and don't wait for vblanks until the end of crtc_enable, then
3877 * the HW state readout code will complain that the expected
3878 * IPS_CTL value is not the one we read. */
3879 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3880 DRM_ERROR("Timed out waiting for IPS enable\n");
3881 }
3882 }
3883
3884 void hsw_disable_ips(struct intel_crtc *crtc)
3885 {
3886 struct drm_device *dev = crtc->base.dev;
3887 struct drm_i915_private *dev_priv = dev->dev_private;
3888
3889 if (!crtc->config.ips_enabled)
3890 return;
3891
3892 assert_plane_enabled(dev_priv, crtc->plane);
3893 if (IS_BROADWELL(dev)) {
3894 mutex_lock(&dev_priv->rps.hw_lock);
3895 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3896 mutex_unlock(&dev_priv->rps.hw_lock);
3897 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3898 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3899 DRM_ERROR("Timed out waiting for IPS disable\n");
3900 } else {
3901 I915_WRITE(IPS_CTL, 0);
3902 POSTING_READ(IPS_CTL);
3903 }
3904
3905 /* We need to wait for a vblank before we can disable the plane. */
3906 intel_wait_for_vblank(dev, crtc->pipe);
3907 }
3908
3909 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3910 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3911 {
3912 struct drm_device *dev = crtc->dev;
3913 struct drm_i915_private *dev_priv = dev->dev_private;
3914 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3915 enum pipe pipe = intel_crtc->pipe;
3916 int palreg = PALETTE(pipe);
3917 int i;
3918 bool reenable_ips = false;
3919
3920 /* The clocks have to be on to load the palette. */
3921 if (!crtc->enabled || !intel_crtc->active)
3922 return;
3923
3924 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3925 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3926 assert_dsi_pll_enabled(dev_priv);
3927 else
3928 assert_pll_enabled(dev_priv, pipe);
3929 }
3930
3931 /* use legacy palette for Ironlake */
3932 if (!HAS_GMCH_DISPLAY(dev))
3933 palreg = LGC_PALETTE(pipe);
3934
3935 /* Workaround : Do not read or write the pipe palette/gamma data while
3936 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3937 */
3938 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3939 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3940 GAMMA_MODE_MODE_SPLIT)) {
3941 hsw_disable_ips(intel_crtc);
3942 reenable_ips = true;
3943 }
3944
3945 for (i = 0; i < 256; i++) {
3946 I915_WRITE(palreg + 4 * i,
3947 (intel_crtc->lut_r[i] << 16) |
3948 (intel_crtc->lut_g[i] << 8) |
3949 intel_crtc->lut_b[i]);
3950 }
3951
3952 if (reenable_ips)
3953 hsw_enable_ips(intel_crtc);
3954 }
3955
3956 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3957 {
3958 if (!enable && intel_crtc->overlay) {
3959 struct drm_device *dev = intel_crtc->base.dev;
3960 struct drm_i915_private *dev_priv = dev->dev_private;
3961
3962 mutex_lock(&dev->struct_mutex);
3963 dev_priv->mm.interruptible = false;
3964 (void) intel_overlay_switch_off(intel_crtc->overlay);
3965 dev_priv->mm.interruptible = true;
3966 mutex_unlock(&dev->struct_mutex);
3967 }
3968
3969 /* Let userspace switch the overlay on again. In most cases userspace
3970 * has to recompute where to put it anyway.
3971 */
3972 }
3973
3974 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
3975 {
3976 struct drm_device *dev = crtc->dev;
3977 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3978 int pipe = intel_crtc->pipe;
3979
3980 drm_vblank_on(dev, pipe);
3981
3982 intel_enable_primary_hw_plane(crtc->primary, crtc);
3983 intel_enable_planes(crtc);
3984 intel_crtc_update_cursor(crtc, true);
3985 intel_crtc_dpms_overlay(intel_crtc, true);
3986
3987 hsw_enable_ips(intel_crtc);
3988
3989 mutex_lock(&dev->struct_mutex);
3990 intel_update_fbc(dev);
3991 mutex_unlock(&dev->struct_mutex);
3992
3993 /*
3994 * FIXME: Once we grow proper nuclear flip support out of this we need
3995 * to compute the mask of flip planes precisely. For the time being
3996 * consider this a flip from a NULL plane.
3997 */
3998 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
3999 }
4000
4001 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4002 {
4003 struct drm_device *dev = crtc->dev;
4004 struct drm_i915_private *dev_priv = dev->dev_private;
4005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4006 int pipe = intel_crtc->pipe;
4007 int plane = intel_crtc->plane;
4008
4009 intel_crtc_wait_for_pending_flips(crtc);
4010
4011 if (dev_priv->fbc.plane == plane)
4012 intel_disable_fbc(dev);
4013
4014 hsw_disable_ips(intel_crtc);
4015
4016 intel_crtc_dpms_overlay(intel_crtc, false);
4017 intel_crtc_update_cursor(crtc, false);
4018 intel_disable_planes(crtc);
4019 intel_disable_primary_hw_plane(crtc->primary, crtc);
4020
4021 /*
4022 * FIXME: Once we grow proper nuclear flip support out of this we need
4023 * to compute the mask of flip planes precisely. For the time being
4024 * consider this a flip to a NULL plane.
4025 */
4026 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4027
4028 drm_vblank_off(dev, pipe);
4029 }
4030
4031 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4032 {
4033 struct drm_device *dev = crtc->dev;
4034 struct drm_i915_private *dev_priv = dev->dev_private;
4035 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4036 struct intel_encoder *encoder;
4037 int pipe = intel_crtc->pipe;
4038
4039 WARN_ON(!crtc->enabled);
4040
4041 if (intel_crtc->active)
4042 return;
4043
4044 if (intel_crtc->config.has_pch_encoder)
4045 intel_prepare_shared_dpll(intel_crtc);
4046
4047 if (intel_crtc->config.has_dp_encoder)
4048 intel_dp_set_m_n(intel_crtc);
4049
4050 intel_set_pipe_timings(intel_crtc);
4051
4052 if (intel_crtc->config.has_pch_encoder) {
4053 intel_cpu_transcoder_set_m_n(intel_crtc,
4054 &intel_crtc->config.fdi_m_n, NULL);
4055 }
4056
4057 ironlake_set_pipeconf(crtc);
4058
4059 intel_crtc->active = true;
4060
4061 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4062 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4063
4064 for_each_encoder_on_crtc(dev, crtc, encoder)
4065 if (encoder->pre_enable)
4066 encoder->pre_enable(encoder);
4067
4068 if (intel_crtc->config.has_pch_encoder) {
4069 /* Note: FDI PLL enabling _must_ be done before we enable the
4070 * cpu pipes, hence this is separate from all the other fdi/pch
4071 * enabling. */
4072 ironlake_fdi_pll_enable(intel_crtc);
4073 } else {
4074 assert_fdi_tx_disabled(dev_priv, pipe);
4075 assert_fdi_rx_disabled(dev_priv, pipe);
4076 }
4077
4078 ironlake_pfit_enable(intel_crtc);
4079
4080 /*
4081 * On ILK+ LUT must be loaded before the pipe is running but with
4082 * clocks enabled
4083 */
4084 intel_crtc_load_lut(crtc);
4085
4086 intel_update_watermarks(crtc);
4087 intel_enable_pipe(intel_crtc);
4088
4089 if (intel_crtc->config.has_pch_encoder)
4090 ironlake_pch_enable(crtc);
4091
4092 for_each_encoder_on_crtc(dev, crtc, encoder)
4093 encoder->enable(encoder);
4094
4095 if (HAS_PCH_CPT(dev))
4096 cpt_verify_modeset(dev, intel_crtc->pipe);
4097
4098 intel_crtc_enable_planes(crtc);
4099 }
4100
4101 /* IPS only exists on ULT machines and is tied to pipe A. */
4102 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4103 {
4104 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4105 }
4106
4107 /*
4108 * This implements the workaround described in the "notes" section of the mode
4109 * set sequence documentation. When going from no pipes or single pipe to
4110 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4111 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4112 */
4113 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4114 {
4115 struct drm_device *dev = crtc->base.dev;
4116 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4117
4118 /* We want to get the other_active_crtc only if there's only 1 other
4119 * active crtc. */
4120 for_each_intel_crtc(dev, crtc_it) {
4121 if (!crtc_it->active || crtc_it == crtc)
4122 continue;
4123
4124 if (other_active_crtc)
4125 return;
4126
4127 other_active_crtc = crtc_it;
4128 }
4129 if (!other_active_crtc)
4130 return;
4131
4132 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4133 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4134 }
4135
4136 static void haswell_crtc_enable(struct drm_crtc *crtc)
4137 {
4138 struct drm_device *dev = crtc->dev;
4139 struct drm_i915_private *dev_priv = dev->dev_private;
4140 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4141 struct intel_encoder *encoder;
4142 int pipe = intel_crtc->pipe;
4143
4144 WARN_ON(!crtc->enabled);
4145
4146 if (intel_crtc->active)
4147 return;
4148
4149 if (intel_crtc_to_shared_dpll(intel_crtc))
4150 intel_enable_shared_dpll(intel_crtc);
4151
4152 if (intel_crtc->config.has_dp_encoder)
4153 intel_dp_set_m_n(intel_crtc);
4154
4155 intel_set_pipe_timings(intel_crtc);
4156
4157 if (intel_crtc->config.has_pch_encoder) {
4158 intel_cpu_transcoder_set_m_n(intel_crtc,
4159 &intel_crtc->config.fdi_m_n, NULL);
4160 }
4161
4162 haswell_set_pipeconf(crtc);
4163
4164 intel_set_pipe_csc(crtc);
4165
4166 intel_crtc->active = true;
4167
4168 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4169 for_each_encoder_on_crtc(dev, crtc, encoder)
4170 if (encoder->pre_enable)
4171 encoder->pre_enable(encoder);
4172
4173 if (intel_crtc->config.has_pch_encoder) {
4174 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4175 dev_priv->display.fdi_link_train(crtc);
4176 }
4177
4178 intel_ddi_enable_pipe_clock(intel_crtc);
4179
4180 ironlake_pfit_enable(intel_crtc);
4181
4182 /*
4183 * On ILK+ LUT must be loaded before the pipe is running but with
4184 * clocks enabled
4185 */
4186 intel_crtc_load_lut(crtc);
4187
4188 intel_ddi_set_pipe_settings(crtc);
4189 intel_ddi_enable_transcoder_func(crtc);
4190
4191 intel_update_watermarks(crtc);
4192 intel_enable_pipe(intel_crtc);
4193
4194 if (intel_crtc->config.has_pch_encoder)
4195 lpt_pch_enable(crtc);
4196
4197 if (intel_crtc->config.dp_encoder_is_mst)
4198 intel_ddi_set_vc_payload_alloc(crtc, true);
4199
4200 for_each_encoder_on_crtc(dev, crtc, encoder) {
4201 encoder->enable(encoder);
4202 intel_opregion_notify_encoder(encoder, true);
4203 }
4204
4205 /* If we change the relative order between pipe/planes enabling, we need
4206 * to change the workaround. */
4207 haswell_mode_set_planes_workaround(intel_crtc);
4208 intel_crtc_enable_planes(crtc);
4209 }
4210
4211 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4212 {
4213 struct drm_device *dev = crtc->base.dev;
4214 struct drm_i915_private *dev_priv = dev->dev_private;
4215 int pipe = crtc->pipe;
4216
4217 /* To avoid upsetting the power well on haswell only disable the pfit if
4218 * it's in use. The hw state code will make sure we get this right. */
4219 if (crtc->config.pch_pfit.enabled) {
4220 I915_WRITE(PF_CTL(pipe), 0);
4221 I915_WRITE(PF_WIN_POS(pipe), 0);
4222 I915_WRITE(PF_WIN_SZ(pipe), 0);
4223 }
4224 }
4225
4226 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4227 {
4228 struct drm_device *dev = crtc->dev;
4229 struct drm_i915_private *dev_priv = dev->dev_private;
4230 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4231 struct intel_encoder *encoder;
4232 int pipe = intel_crtc->pipe;
4233 u32 reg, temp;
4234
4235 if (!intel_crtc->active)
4236 return;
4237
4238 intel_crtc_disable_planes(crtc);
4239
4240 for_each_encoder_on_crtc(dev, crtc, encoder)
4241 encoder->disable(encoder);
4242
4243 if (intel_crtc->config.has_pch_encoder)
4244 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4245
4246 intel_disable_pipe(intel_crtc);
4247
4248 if (intel_crtc->config.dp_encoder_is_mst)
4249 intel_ddi_set_vc_payload_alloc(crtc, false);
4250
4251 ironlake_pfit_disable(intel_crtc);
4252
4253 for_each_encoder_on_crtc(dev, crtc, encoder)
4254 if (encoder->post_disable)
4255 encoder->post_disable(encoder);
4256
4257 if (intel_crtc->config.has_pch_encoder) {
4258 ironlake_fdi_disable(crtc);
4259
4260 ironlake_disable_pch_transcoder(dev_priv, pipe);
4261 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4262
4263 if (HAS_PCH_CPT(dev)) {
4264 /* disable TRANS_DP_CTL */
4265 reg = TRANS_DP_CTL(pipe);
4266 temp = I915_READ(reg);
4267 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4268 TRANS_DP_PORT_SEL_MASK);
4269 temp |= TRANS_DP_PORT_SEL_NONE;
4270 I915_WRITE(reg, temp);
4271
4272 /* disable DPLL_SEL */
4273 temp = I915_READ(PCH_DPLL_SEL);
4274 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4275 I915_WRITE(PCH_DPLL_SEL, temp);
4276 }
4277
4278 /* disable PCH DPLL */
4279 intel_disable_shared_dpll(intel_crtc);
4280
4281 ironlake_fdi_pll_disable(intel_crtc);
4282 }
4283
4284 intel_crtc->active = false;
4285 intel_update_watermarks(crtc);
4286
4287 mutex_lock(&dev->struct_mutex);
4288 intel_update_fbc(dev);
4289 mutex_unlock(&dev->struct_mutex);
4290 }
4291
4292 static void haswell_crtc_disable(struct drm_crtc *crtc)
4293 {
4294 struct drm_device *dev = crtc->dev;
4295 struct drm_i915_private *dev_priv = dev->dev_private;
4296 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4297 struct intel_encoder *encoder;
4298 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4299
4300 if (!intel_crtc->active)
4301 return;
4302
4303 intel_crtc_disable_planes(crtc);
4304
4305 for_each_encoder_on_crtc(dev, crtc, encoder) {
4306 intel_opregion_notify_encoder(encoder, false);
4307 encoder->disable(encoder);
4308 }
4309
4310 if (intel_crtc->config.has_pch_encoder)
4311 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4312 intel_disable_pipe(intel_crtc);
4313
4314 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4315
4316 ironlake_pfit_disable(intel_crtc);
4317
4318 intel_ddi_disable_pipe_clock(intel_crtc);
4319
4320 if (intel_crtc->config.has_pch_encoder) {
4321 lpt_disable_pch_transcoder(dev_priv);
4322 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4323 intel_ddi_fdi_disable(crtc);
4324 }
4325
4326 for_each_encoder_on_crtc(dev, crtc, encoder)
4327 if (encoder->post_disable)
4328 encoder->post_disable(encoder);
4329
4330 intel_crtc->active = false;
4331 intel_update_watermarks(crtc);
4332
4333 mutex_lock(&dev->struct_mutex);
4334 intel_update_fbc(dev);
4335 mutex_unlock(&dev->struct_mutex);
4336
4337 if (intel_crtc_to_shared_dpll(intel_crtc))
4338 intel_disable_shared_dpll(intel_crtc);
4339 }
4340
4341 static void ironlake_crtc_off(struct drm_crtc *crtc)
4342 {
4343 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4344 intel_put_shared_dpll(intel_crtc);
4345 }
4346
4347
4348 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4349 {
4350 struct drm_device *dev = crtc->base.dev;
4351 struct drm_i915_private *dev_priv = dev->dev_private;
4352 struct intel_crtc_config *pipe_config = &crtc->config;
4353
4354 if (!crtc->config.gmch_pfit.control)
4355 return;
4356
4357 /*
4358 * The panel fitter should only be adjusted whilst the pipe is disabled,
4359 * according to register description and PRM.
4360 */
4361 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4362 assert_pipe_disabled(dev_priv, crtc->pipe);
4363
4364 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4365 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4366
4367 /* Border color in case we don't scale up to the full screen. Black by
4368 * default, change to something else for debugging. */
4369 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4370 }
4371
4372 static enum intel_display_power_domain port_to_power_domain(enum port port)
4373 {
4374 switch (port) {
4375 case PORT_A:
4376 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4377 case PORT_B:
4378 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4379 case PORT_C:
4380 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4381 case PORT_D:
4382 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4383 default:
4384 WARN_ON_ONCE(1);
4385 return POWER_DOMAIN_PORT_OTHER;
4386 }
4387 }
4388
4389 #define for_each_power_domain(domain, mask) \
4390 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4391 if ((1 << (domain)) & (mask))
4392
4393 enum intel_display_power_domain
4394 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4395 {
4396 struct drm_device *dev = intel_encoder->base.dev;
4397 struct intel_digital_port *intel_dig_port;
4398
4399 switch (intel_encoder->type) {
4400 case INTEL_OUTPUT_UNKNOWN:
4401 /* Only DDI platforms should ever use this output type */
4402 WARN_ON_ONCE(!HAS_DDI(dev));
4403 case INTEL_OUTPUT_DISPLAYPORT:
4404 case INTEL_OUTPUT_HDMI:
4405 case INTEL_OUTPUT_EDP:
4406 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4407 return port_to_power_domain(intel_dig_port->port);
4408 case INTEL_OUTPUT_DP_MST:
4409 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4410 return port_to_power_domain(intel_dig_port->port);
4411 case INTEL_OUTPUT_ANALOG:
4412 return POWER_DOMAIN_PORT_CRT;
4413 case INTEL_OUTPUT_DSI:
4414 return POWER_DOMAIN_PORT_DSI;
4415 default:
4416 return POWER_DOMAIN_PORT_OTHER;
4417 }
4418 }
4419
4420 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4421 {
4422 struct drm_device *dev = crtc->dev;
4423 struct intel_encoder *intel_encoder;
4424 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4425 enum pipe pipe = intel_crtc->pipe;
4426 unsigned long mask;
4427 enum transcoder transcoder;
4428
4429 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4430
4431 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4432 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4433 if (intel_crtc->config.pch_pfit.enabled ||
4434 intel_crtc->config.pch_pfit.force_thru)
4435 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4436
4437 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4438 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4439
4440 return mask;
4441 }
4442
4443 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4444 bool enable)
4445 {
4446 if (dev_priv->power_domains.init_power_on == enable)
4447 return;
4448
4449 if (enable)
4450 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4451 else
4452 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4453
4454 dev_priv->power_domains.init_power_on = enable;
4455 }
4456
4457 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4458 {
4459 struct drm_i915_private *dev_priv = dev->dev_private;
4460 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4461 struct intel_crtc *crtc;
4462
4463 /*
4464 * First get all needed power domains, then put all unneeded, to avoid
4465 * any unnecessary toggling of the power wells.
4466 */
4467 for_each_intel_crtc(dev, crtc) {
4468 enum intel_display_power_domain domain;
4469
4470 if (!crtc->base.enabled)
4471 continue;
4472
4473 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4474
4475 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4476 intel_display_power_get(dev_priv, domain);
4477 }
4478
4479 for_each_intel_crtc(dev, crtc) {
4480 enum intel_display_power_domain domain;
4481
4482 for_each_power_domain(domain, crtc->enabled_power_domains)
4483 intel_display_power_put(dev_priv, domain);
4484
4485 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4486 }
4487
4488 intel_display_set_init_power(dev_priv, false);
4489 }
4490
4491 /* returns HPLL frequency in kHz */
4492 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4493 {
4494 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4495
4496 /* Obtain SKU information */
4497 mutex_lock(&dev_priv->dpio_lock);
4498 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4499 CCK_FUSE_HPLL_FREQ_MASK;
4500 mutex_unlock(&dev_priv->dpio_lock);
4501
4502 return vco_freq[hpll_freq] * 1000;
4503 }
4504
4505 static void vlv_update_cdclk(struct drm_device *dev)
4506 {
4507 struct drm_i915_private *dev_priv = dev->dev_private;
4508
4509 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4510 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz",
4511 dev_priv->vlv_cdclk_freq);
4512
4513 /*
4514 * Program the gmbus_freq based on the cdclk frequency.
4515 * BSpec erroneously claims we should aim for 4MHz, but
4516 * in fact 1MHz is the correct frequency.
4517 */
4518 I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
4519 }
4520
4521 /* Adjust CDclk dividers to allow high res or save power if possible */
4522 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4523 {
4524 struct drm_i915_private *dev_priv = dev->dev_private;
4525 u32 val, cmd;
4526
4527 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4528
4529 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4530 cmd = 2;
4531 else if (cdclk == 266667)
4532 cmd = 1;
4533 else
4534 cmd = 0;
4535
4536 mutex_lock(&dev_priv->rps.hw_lock);
4537 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4538 val &= ~DSPFREQGUAR_MASK;
4539 val |= (cmd << DSPFREQGUAR_SHIFT);
4540 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4541 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4542 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4543 50)) {
4544 DRM_ERROR("timed out waiting for CDclk change\n");
4545 }
4546 mutex_unlock(&dev_priv->rps.hw_lock);
4547
4548 if (cdclk == 400000) {
4549 u32 divider, vco;
4550
4551 vco = valleyview_get_vco(dev_priv);
4552 divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1;
4553
4554 mutex_lock(&dev_priv->dpio_lock);
4555 /* adjust cdclk divider */
4556 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4557 val &= ~DISPLAY_FREQUENCY_VALUES;
4558 val |= divider;
4559 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4560
4561 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4562 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4563 50))
4564 DRM_ERROR("timed out waiting for CDclk change\n");
4565 mutex_unlock(&dev_priv->dpio_lock);
4566 }
4567
4568 mutex_lock(&dev_priv->dpio_lock);
4569 /* adjust self-refresh exit latency value */
4570 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4571 val &= ~0x7f;
4572
4573 /*
4574 * For high bandwidth configs, we set a higher latency in the bunit
4575 * so that the core display fetch happens in time to avoid underruns.
4576 */
4577 if (cdclk == 400000)
4578 val |= 4500 / 250; /* 4.5 usec */
4579 else
4580 val |= 3000 / 250; /* 3.0 usec */
4581 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4582 mutex_unlock(&dev_priv->dpio_lock);
4583
4584 vlv_update_cdclk(dev);
4585 }
4586
4587 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4588 {
4589 struct drm_i915_private *dev_priv = dev->dev_private;
4590 u32 val, cmd;
4591
4592 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4593
4594 switch (cdclk) {
4595 case 400000:
4596 cmd = 3;
4597 break;
4598 case 333333:
4599 case 320000:
4600 cmd = 2;
4601 break;
4602 case 266667:
4603 cmd = 1;
4604 break;
4605 case 200000:
4606 cmd = 0;
4607 break;
4608 default:
4609 WARN_ON(1);
4610 return;
4611 }
4612
4613 mutex_lock(&dev_priv->rps.hw_lock);
4614 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4615 val &= ~DSPFREQGUAR_MASK_CHV;
4616 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4617 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4618 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4619 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4620 50)) {
4621 DRM_ERROR("timed out waiting for CDclk change\n");
4622 }
4623 mutex_unlock(&dev_priv->rps.hw_lock);
4624
4625 vlv_update_cdclk(dev);
4626 }
4627
4628 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4629 int max_pixclk)
4630 {
4631 int vco = valleyview_get_vco(dev_priv);
4632 int freq_320 = (vco << 1) % 320000 != 0 ? 333333 : 320000;
4633
4634 /* FIXME: Punit isn't quite ready yet */
4635 if (IS_CHERRYVIEW(dev_priv->dev))
4636 return 400000;
4637
4638 /*
4639 * Really only a few cases to deal with, as only 4 CDclks are supported:
4640 * 200MHz
4641 * 267MHz
4642 * 320/333MHz (depends on HPLL freq)
4643 * 400MHz
4644 * So we check to see whether we're above 90% of the lower bin and
4645 * adjust if needed.
4646 *
4647 * We seem to get an unstable or solid color picture at 200MHz.
4648 * Not sure what's wrong. For now use 200MHz only when all pipes
4649 * are off.
4650 */
4651 if (max_pixclk > freq_320*9/10)
4652 return 400000;
4653 else if (max_pixclk > 266667*9/10)
4654 return freq_320;
4655 else if (max_pixclk > 0)
4656 return 266667;
4657 else
4658 return 200000;
4659 }
4660
4661 /* compute the max pixel clock for new configuration */
4662 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4663 {
4664 struct drm_device *dev = dev_priv->dev;
4665 struct intel_crtc *intel_crtc;
4666 int max_pixclk = 0;
4667
4668 for_each_intel_crtc(dev, intel_crtc) {
4669 if (intel_crtc->new_enabled)
4670 max_pixclk = max(max_pixclk,
4671 intel_crtc->new_config->adjusted_mode.crtc_clock);
4672 }
4673
4674 return max_pixclk;
4675 }
4676
4677 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4678 unsigned *prepare_pipes)
4679 {
4680 struct drm_i915_private *dev_priv = dev->dev_private;
4681 struct intel_crtc *intel_crtc;
4682 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4683
4684 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4685 dev_priv->vlv_cdclk_freq)
4686 return;
4687
4688 /* disable/enable all currently active pipes while we change cdclk */
4689 for_each_intel_crtc(dev, intel_crtc)
4690 if (intel_crtc->base.enabled)
4691 *prepare_pipes |= (1 << intel_crtc->pipe);
4692 }
4693
4694 static void valleyview_modeset_global_resources(struct drm_device *dev)
4695 {
4696 struct drm_i915_private *dev_priv = dev->dev_private;
4697 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4698 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4699
4700 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4701 if (IS_CHERRYVIEW(dev))
4702 cherryview_set_cdclk(dev, req_cdclk);
4703 else
4704 valleyview_set_cdclk(dev, req_cdclk);
4705 }
4706
4707 modeset_update_crtc_power_domains(dev);
4708 }
4709
4710 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4711 {
4712 struct drm_device *dev = crtc->dev;
4713 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4714 struct intel_encoder *encoder;
4715 int pipe = intel_crtc->pipe;
4716 bool is_dsi;
4717
4718 WARN_ON(!crtc->enabled);
4719
4720 if (intel_crtc->active)
4721 return;
4722
4723 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4724
4725 if (!is_dsi) {
4726 if (IS_CHERRYVIEW(dev))
4727 chv_prepare_pll(intel_crtc);
4728 else
4729 vlv_prepare_pll(intel_crtc);
4730 }
4731
4732 if (intel_crtc->config.has_dp_encoder)
4733 intel_dp_set_m_n(intel_crtc);
4734
4735 intel_set_pipe_timings(intel_crtc);
4736
4737 i9xx_set_pipeconf(intel_crtc);
4738
4739 intel_crtc->active = true;
4740
4741 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4742
4743 for_each_encoder_on_crtc(dev, crtc, encoder)
4744 if (encoder->pre_pll_enable)
4745 encoder->pre_pll_enable(encoder);
4746
4747 if (!is_dsi) {
4748 if (IS_CHERRYVIEW(dev))
4749 chv_enable_pll(intel_crtc);
4750 else
4751 vlv_enable_pll(intel_crtc);
4752 }
4753
4754 for_each_encoder_on_crtc(dev, crtc, encoder)
4755 if (encoder->pre_enable)
4756 encoder->pre_enable(encoder);
4757
4758 i9xx_pfit_enable(intel_crtc);
4759
4760 intel_crtc_load_lut(crtc);
4761
4762 intel_update_watermarks(crtc);
4763 intel_enable_pipe(intel_crtc);
4764
4765 for_each_encoder_on_crtc(dev, crtc, encoder)
4766 encoder->enable(encoder);
4767
4768 intel_crtc_enable_planes(crtc);
4769
4770 /* Underruns don't raise interrupts, so check manually. */
4771 i9xx_check_fifo_underruns(dev);
4772 }
4773
4774 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4775 {
4776 struct drm_device *dev = crtc->base.dev;
4777 struct drm_i915_private *dev_priv = dev->dev_private;
4778
4779 I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4780 I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4781 }
4782
4783 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4784 {
4785 struct drm_device *dev = crtc->dev;
4786 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4787 struct intel_encoder *encoder;
4788 int pipe = intel_crtc->pipe;
4789
4790 WARN_ON(!crtc->enabled);
4791
4792 if (intel_crtc->active)
4793 return;
4794
4795 i9xx_set_pll_dividers(intel_crtc);
4796
4797 if (intel_crtc->config.has_dp_encoder)
4798 intel_dp_set_m_n(intel_crtc);
4799
4800 intel_set_pipe_timings(intel_crtc);
4801
4802 i9xx_set_pipeconf(intel_crtc);
4803
4804 intel_crtc->active = true;
4805
4806 if (!IS_GEN2(dev))
4807 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4808
4809 for_each_encoder_on_crtc(dev, crtc, encoder)
4810 if (encoder->pre_enable)
4811 encoder->pre_enable(encoder);
4812
4813 i9xx_enable_pll(intel_crtc);
4814
4815 i9xx_pfit_enable(intel_crtc);
4816
4817 intel_crtc_load_lut(crtc);
4818
4819 intel_update_watermarks(crtc);
4820 intel_enable_pipe(intel_crtc);
4821
4822 for_each_encoder_on_crtc(dev, crtc, encoder)
4823 encoder->enable(encoder);
4824
4825 intel_crtc_enable_planes(crtc);
4826
4827 /*
4828 * Gen2 reports pipe underruns whenever all planes are disabled.
4829 * So don't enable underrun reporting before at least some planes
4830 * are enabled.
4831 * FIXME: Need to fix the logic to work when we turn off all planes
4832 * but leave the pipe running.
4833 */
4834 if (IS_GEN2(dev))
4835 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4836
4837 /* Underruns don't raise interrupts, so check manually. */
4838 i9xx_check_fifo_underruns(dev);
4839 }
4840
4841 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4842 {
4843 struct drm_device *dev = crtc->base.dev;
4844 struct drm_i915_private *dev_priv = dev->dev_private;
4845
4846 if (!crtc->config.gmch_pfit.control)
4847 return;
4848
4849 assert_pipe_disabled(dev_priv, crtc->pipe);
4850
4851 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4852 I915_READ(PFIT_CONTROL));
4853 I915_WRITE(PFIT_CONTROL, 0);
4854 }
4855
4856 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4857 {
4858 struct drm_device *dev = crtc->dev;
4859 struct drm_i915_private *dev_priv = dev->dev_private;
4860 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4861 struct intel_encoder *encoder;
4862 int pipe = intel_crtc->pipe;
4863
4864 if (!intel_crtc->active)
4865 return;
4866
4867 /*
4868 * Gen2 reports pipe underruns whenever all planes are disabled.
4869 * So diasble underrun reporting before all the planes get disabled.
4870 * FIXME: Need to fix the logic to work when we turn off all planes
4871 * but leave the pipe running.
4872 */
4873 if (IS_GEN2(dev))
4874 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4875
4876 /*
4877 * Vblank time updates from the shadow to live plane control register
4878 * are blocked if the memory self-refresh mode is active at that
4879 * moment. So to make sure the plane gets truly disabled, disable
4880 * first the self-refresh mode. The self-refresh enable bit in turn
4881 * will be checked/applied by the HW only at the next frame start
4882 * event which is after the vblank start event, so we need to have a
4883 * wait-for-vblank between disabling the plane and the pipe.
4884 */
4885 intel_set_memory_cxsr(dev_priv, false);
4886 intel_crtc_disable_planes(crtc);
4887
4888 for_each_encoder_on_crtc(dev, crtc, encoder)
4889 encoder->disable(encoder);
4890
4891 /*
4892 * On gen2 planes are double buffered but the pipe isn't, so we must
4893 * wait for planes to fully turn off before disabling the pipe.
4894 * We also need to wait on all gmch platforms because of the
4895 * self-refresh mode constraint explained above.
4896 */
4897 intel_wait_for_vblank(dev, pipe);
4898
4899 intel_disable_pipe(intel_crtc);
4900
4901 i9xx_pfit_disable(intel_crtc);
4902
4903 for_each_encoder_on_crtc(dev, crtc, encoder)
4904 if (encoder->post_disable)
4905 encoder->post_disable(encoder);
4906
4907 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4908 if (IS_CHERRYVIEW(dev))
4909 chv_disable_pll(dev_priv, pipe);
4910 else if (IS_VALLEYVIEW(dev))
4911 vlv_disable_pll(dev_priv, pipe);
4912 else
4913 i9xx_disable_pll(dev_priv, pipe);
4914 }
4915
4916 if (!IS_GEN2(dev))
4917 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4918
4919 intel_crtc->active = false;
4920 intel_update_watermarks(crtc);
4921
4922 mutex_lock(&dev->struct_mutex);
4923 intel_update_fbc(dev);
4924 mutex_unlock(&dev->struct_mutex);
4925 }
4926
4927 static void i9xx_crtc_off(struct drm_crtc *crtc)
4928 {
4929 }
4930
4931 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4932 bool enabled)
4933 {
4934 struct drm_device *dev = crtc->dev;
4935 struct drm_i915_master_private *master_priv;
4936 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4937 int pipe = intel_crtc->pipe;
4938
4939 if (!dev->primary->master)
4940 return;
4941
4942 master_priv = dev->primary->master->driver_priv;
4943 if (!master_priv->sarea_priv)
4944 return;
4945
4946 switch (pipe) {
4947 case 0:
4948 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4949 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4950 break;
4951 case 1:
4952 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4953 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4954 break;
4955 default:
4956 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4957 break;
4958 }
4959 }
4960
4961 /* Master function to enable/disable CRTC and corresponding power wells */
4962 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
4963 {
4964 struct drm_device *dev = crtc->dev;
4965 struct drm_i915_private *dev_priv = dev->dev_private;
4966 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4967 enum intel_display_power_domain domain;
4968 unsigned long domains;
4969
4970 if (enable) {
4971 if (!intel_crtc->active) {
4972 domains = get_crtc_power_domains(crtc);
4973 for_each_power_domain(domain, domains)
4974 intel_display_power_get(dev_priv, domain);
4975 intel_crtc->enabled_power_domains = domains;
4976
4977 dev_priv->display.crtc_enable(crtc);
4978 }
4979 } else {
4980 if (intel_crtc->active) {
4981 dev_priv->display.crtc_disable(crtc);
4982
4983 domains = intel_crtc->enabled_power_domains;
4984 for_each_power_domain(domain, domains)
4985 intel_display_power_put(dev_priv, domain);
4986 intel_crtc->enabled_power_domains = 0;
4987 }
4988 }
4989 }
4990
4991 /**
4992 * Sets the power management mode of the pipe and plane.
4993 */
4994 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4995 {
4996 struct drm_device *dev = crtc->dev;
4997 struct intel_encoder *intel_encoder;
4998 bool enable = false;
4999
5000 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5001 enable |= intel_encoder->connectors_active;
5002
5003 intel_crtc_control(crtc, enable);
5004
5005 intel_crtc_update_sarea(crtc, enable);
5006 }
5007
5008 static void intel_crtc_disable(struct drm_crtc *crtc)
5009 {
5010 struct drm_device *dev = crtc->dev;
5011 struct drm_connector *connector;
5012 struct drm_i915_private *dev_priv = dev->dev_private;
5013 struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
5014 enum pipe pipe = to_intel_crtc(crtc)->pipe;
5015
5016 /* crtc should still be enabled when we disable it. */
5017 WARN_ON(!crtc->enabled);
5018
5019 dev_priv->display.crtc_disable(crtc);
5020 intel_crtc_update_sarea(crtc, false);
5021 dev_priv->display.off(crtc);
5022
5023 if (crtc->primary->fb) {
5024 mutex_lock(&dev->struct_mutex);
5025 intel_unpin_fb_obj(old_obj);
5026 i915_gem_track_fb(old_obj, NULL,
5027 INTEL_FRONTBUFFER_PRIMARY(pipe));
5028 mutex_unlock(&dev->struct_mutex);
5029 crtc->primary->fb = NULL;
5030 }
5031
5032 /* Update computed state. */
5033 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5034 if (!connector->encoder || !connector->encoder->crtc)
5035 continue;
5036
5037 if (connector->encoder->crtc != crtc)
5038 continue;
5039
5040 connector->dpms = DRM_MODE_DPMS_OFF;
5041 to_intel_encoder(connector->encoder)->connectors_active = false;
5042 }
5043 }
5044
5045 void intel_encoder_destroy(struct drm_encoder *encoder)
5046 {
5047 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5048
5049 drm_encoder_cleanup(encoder);
5050 kfree(intel_encoder);
5051 }
5052
5053 /* Simple dpms helper for encoders with just one connector, no cloning and only
5054 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5055 * state of the entire output pipe. */
5056 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5057 {
5058 if (mode == DRM_MODE_DPMS_ON) {
5059 encoder->connectors_active = true;
5060
5061 intel_crtc_update_dpms(encoder->base.crtc);
5062 } else {
5063 encoder->connectors_active = false;
5064
5065 intel_crtc_update_dpms(encoder->base.crtc);
5066 }
5067 }
5068
5069 /* Cross check the actual hw state with our own modeset state tracking (and it's
5070 * internal consistency). */
5071 static void intel_connector_check_state(struct intel_connector *connector)
5072 {
5073 if (connector->get_hw_state(connector)) {
5074 struct intel_encoder *encoder = connector->encoder;
5075 struct drm_crtc *crtc;
5076 bool encoder_enabled;
5077 enum pipe pipe;
5078
5079 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5080 connector->base.base.id,
5081 connector->base.name);
5082
5083 /* there is no real hw state for MST connectors */
5084 if (connector->mst_port)
5085 return;
5086
5087 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5088 "wrong connector dpms state\n");
5089 WARN(connector->base.encoder != &encoder->base,
5090 "active connector not linked to encoder\n");
5091
5092 if (encoder) {
5093 WARN(!encoder->connectors_active,
5094 "encoder->connectors_active not set\n");
5095
5096 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5097 WARN(!encoder_enabled, "encoder not enabled\n");
5098 if (WARN_ON(!encoder->base.crtc))
5099 return;
5100
5101 crtc = encoder->base.crtc;
5102
5103 WARN(!crtc->enabled, "crtc not enabled\n");
5104 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5105 WARN(pipe != to_intel_crtc(crtc)->pipe,
5106 "encoder active on the wrong pipe\n");
5107 }
5108 }
5109 }
5110
5111 /* Even simpler default implementation, if there's really no special case to
5112 * consider. */
5113 void intel_connector_dpms(struct drm_connector *connector, int mode)
5114 {
5115 /* All the simple cases only support two dpms states. */
5116 if (mode != DRM_MODE_DPMS_ON)
5117 mode = DRM_MODE_DPMS_OFF;
5118
5119 if (mode == connector->dpms)
5120 return;
5121
5122 connector->dpms = mode;
5123
5124 /* Only need to change hw state when actually enabled */
5125 if (connector->encoder)
5126 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5127
5128 intel_modeset_check_state(connector->dev);
5129 }
5130
5131 /* Simple connector->get_hw_state implementation for encoders that support only
5132 * one connector and no cloning and hence the encoder state determines the state
5133 * of the connector. */
5134 bool intel_connector_get_hw_state(struct intel_connector *connector)
5135 {
5136 enum pipe pipe = 0;
5137 struct intel_encoder *encoder = connector->encoder;
5138
5139 return encoder->get_hw_state(encoder, &pipe);
5140 }
5141
5142 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5143 struct intel_crtc_config *pipe_config)
5144 {
5145 struct drm_i915_private *dev_priv = dev->dev_private;
5146 struct intel_crtc *pipe_B_crtc =
5147 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5148
5149 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5150 pipe_name(pipe), pipe_config->fdi_lanes);
5151 if (pipe_config->fdi_lanes > 4) {
5152 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5153 pipe_name(pipe), pipe_config->fdi_lanes);
5154 return false;
5155 }
5156
5157 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5158 if (pipe_config->fdi_lanes > 2) {
5159 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5160 pipe_config->fdi_lanes);
5161 return false;
5162 } else {
5163 return true;
5164 }
5165 }
5166
5167 if (INTEL_INFO(dev)->num_pipes == 2)
5168 return true;
5169
5170 /* Ivybridge 3 pipe is really complicated */
5171 switch (pipe) {
5172 case PIPE_A:
5173 return true;
5174 case PIPE_B:
5175 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5176 pipe_config->fdi_lanes > 2) {
5177 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5178 pipe_name(pipe), pipe_config->fdi_lanes);
5179 return false;
5180 }
5181 return true;
5182 case PIPE_C:
5183 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5184 pipe_B_crtc->config.fdi_lanes <= 2) {
5185 if (pipe_config->fdi_lanes > 2) {
5186 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5187 pipe_name(pipe), pipe_config->fdi_lanes);
5188 return false;
5189 }
5190 } else {
5191 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5192 return false;
5193 }
5194 return true;
5195 default:
5196 BUG();
5197 }
5198 }
5199
5200 #define RETRY 1
5201 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5202 struct intel_crtc_config *pipe_config)
5203 {
5204 struct drm_device *dev = intel_crtc->base.dev;
5205 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5206 int lane, link_bw, fdi_dotclock;
5207 bool setup_ok, needs_recompute = false;
5208
5209 retry:
5210 /* FDI is a binary signal running at ~2.7GHz, encoding
5211 * each output octet as 10 bits. The actual frequency
5212 * is stored as a divider into a 100MHz clock, and the
5213 * mode pixel clock is stored in units of 1KHz.
5214 * Hence the bw of each lane in terms of the mode signal
5215 * is:
5216 */
5217 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5218
5219 fdi_dotclock = adjusted_mode->crtc_clock;
5220
5221 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5222 pipe_config->pipe_bpp);
5223
5224 pipe_config->fdi_lanes = lane;
5225
5226 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5227 link_bw, &pipe_config->fdi_m_n);
5228
5229 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5230 intel_crtc->pipe, pipe_config);
5231 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5232 pipe_config->pipe_bpp -= 2*3;
5233 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5234 pipe_config->pipe_bpp);
5235 needs_recompute = true;
5236 pipe_config->bw_constrained = true;
5237
5238 goto retry;
5239 }
5240
5241 if (needs_recompute)
5242 return RETRY;
5243
5244 return setup_ok ? 0 : -EINVAL;
5245 }
5246
5247 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5248 struct intel_crtc_config *pipe_config)
5249 {
5250 pipe_config->ips_enabled = i915.enable_ips &&
5251 hsw_crtc_supports_ips(crtc) &&
5252 pipe_config->pipe_bpp <= 24;
5253 }
5254
5255 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5256 struct intel_crtc_config *pipe_config)
5257 {
5258 struct drm_device *dev = crtc->base.dev;
5259 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5260
5261 /* FIXME should check pixel clock limits on all platforms */
5262 if (INTEL_INFO(dev)->gen < 4) {
5263 struct drm_i915_private *dev_priv = dev->dev_private;
5264 int clock_limit =
5265 dev_priv->display.get_display_clock_speed(dev);
5266
5267 /*
5268 * Enable pixel doubling when the dot clock
5269 * is > 90% of the (display) core speed.
5270 *
5271 * GDG double wide on either pipe,
5272 * otherwise pipe A only.
5273 */
5274 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5275 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5276 clock_limit *= 2;
5277 pipe_config->double_wide = true;
5278 }
5279
5280 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5281 return -EINVAL;
5282 }
5283
5284 /*
5285 * Pipe horizontal size must be even in:
5286 * - DVO ganged mode
5287 * - LVDS dual channel mode
5288 * - Double wide pipe
5289 */
5290 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5291 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5292 pipe_config->pipe_src_w &= ~1;
5293
5294 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5295 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5296 */
5297 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5298 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5299 return -EINVAL;
5300
5301 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5302 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5303 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5304 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5305 * for lvds. */
5306 pipe_config->pipe_bpp = 8*3;
5307 }
5308
5309 if (HAS_IPS(dev))
5310 hsw_compute_ips_config(crtc, pipe_config);
5311
5312 /*
5313 * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the
5314 * old clock survives for now.
5315 */
5316 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev) || HAS_DDI(dev))
5317 pipe_config->shared_dpll = crtc->config.shared_dpll;
5318
5319 if (pipe_config->has_pch_encoder)
5320 return ironlake_fdi_compute_config(crtc, pipe_config);
5321
5322 return 0;
5323 }
5324
5325 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5326 {
5327 struct drm_i915_private *dev_priv = dev->dev_private;
5328 int vco = valleyview_get_vco(dev_priv);
5329 u32 val;
5330 int divider;
5331
5332 /* FIXME: Punit isn't quite ready yet */
5333 if (IS_CHERRYVIEW(dev))
5334 return 400000;
5335
5336 mutex_lock(&dev_priv->dpio_lock);
5337 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5338 mutex_unlock(&dev_priv->dpio_lock);
5339
5340 divider = val & DISPLAY_FREQUENCY_VALUES;
5341
5342 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5343 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5344 "cdclk change in progress\n");
5345
5346 return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
5347 }
5348
5349 static int i945_get_display_clock_speed(struct drm_device *dev)
5350 {
5351 return 400000;
5352 }
5353
5354 static int i915_get_display_clock_speed(struct drm_device *dev)
5355 {
5356 return 333000;
5357 }
5358
5359 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5360 {
5361 return 200000;
5362 }
5363
5364 static int pnv_get_display_clock_speed(struct drm_device *dev)
5365 {
5366 u16 gcfgc = 0;
5367
5368 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5369
5370 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5371 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5372 return 267000;
5373 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5374 return 333000;
5375 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5376 return 444000;
5377 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5378 return 200000;
5379 default:
5380 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5381 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5382 return 133000;
5383 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5384 return 167000;
5385 }
5386 }
5387
5388 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5389 {
5390 u16 gcfgc = 0;
5391
5392 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5393
5394 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5395 return 133000;
5396 else {
5397 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5398 case GC_DISPLAY_CLOCK_333_MHZ:
5399 return 333000;
5400 default:
5401 case GC_DISPLAY_CLOCK_190_200_MHZ:
5402 return 190000;
5403 }
5404 }
5405 }
5406
5407 static int i865_get_display_clock_speed(struct drm_device *dev)
5408 {
5409 return 266000;
5410 }
5411
5412 static int i855_get_display_clock_speed(struct drm_device *dev)
5413 {
5414 u16 hpllcc = 0;
5415 /* Assume that the hardware is in the high speed state. This
5416 * should be the default.
5417 */
5418 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5419 case GC_CLOCK_133_200:
5420 case GC_CLOCK_100_200:
5421 return 200000;
5422 case GC_CLOCK_166_250:
5423 return 250000;
5424 case GC_CLOCK_100_133:
5425 return 133000;
5426 }
5427
5428 /* Shouldn't happen */
5429 return 0;
5430 }
5431
5432 static int i830_get_display_clock_speed(struct drm_device *dev)
5433 {
5434 return 133000;
5435 }
5436
5437 static void
5438 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5439 {
5440 while (*num > DATA_LINK_M_N_MASK ||
5441 *den > DATA_LINK_M_N_MASK) {
5442 *num >>= 1;
5443 *den >>= 1;
5444 }
5445 }
5446
5447 static void compute_m_n(unsigned int m, unsigned int n,
5448 uint32_t *ret_m, uint32_t *ret_n)
5449 {
5450 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5451 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5452 intel_reduce_m_n_ratio(ret_m, ret_n);
5453 }
5454
5455 void
5456 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5457 int pixel_clock, int link_clock,
5458 struct intel_link_m_n *m_n)
5459 {
5460 m_n->tu = 64;
5461
5462 compute_m_n(bits_per_pixel * pixel_clock,
5463 link_clock * nlanes * 8,
5464 &m_n->gmch_m, &m_n->gmch_n);
5465
5466 compute_m_n(pixel_clock, link_clock,
5467 &m_n->link_m, &m_n->link_n);
5468 }
5469
5470 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5471 {
5472 if (i915.panel_use_ssc >= 0)
5473 return i915.panel_use_ssc != 0;
5474 return dev_priv->vbt.lvds_use_ssc
5475 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5476 }
5477
5478 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5479 {
5480 struct drm_device *dev = crtc->dev;
5481 struct drm_i915_private *dev_priv = dev->dev_private;
5482 int refclk;
5483
5484 if (IS_VALLEYVIEW(dev)) {
5485 refclk = 100000;
5486 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5487 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5488 refclk = dev_priv->vbt.lvds_ssc_freq;
5489 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5490 } else if (!IS_GEN2(dev)) {
5491 refclk = 96000;
5492 } else {
5493 refclk = 48000;
5494 }
5495
5496 return refclk;
5497 }
5498
5499 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5500 {
5501 return (1 << dpll->n) << 16 | dpll->m2;
5502 }
5503
5504 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5505 {
5506 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5507 }
5508
5509 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5510 intel_clock_t *reduced_clock)
5511 {
5512 struct drm_device *dev = crtc->base.dev;
5513 u32 fp, fp2 = 0;
5514
5515 if (IS_PINEVIEW(dev)) {
5516 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5517 if (reduced_clock)
5518 fp2 = pnv_dpll_compute_fp(reduced_clock);
5519 } else {
5520 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5521 if (reduced_clock)
5522 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5523 }
5524
5525 crtc->config.dpll_hw_state.fp0 = fp;
5526
5527 crtc->lowfreq_avail = false;
5528 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5529 reduced_clock && i915.powersave) {
5530 crtc->config.dpll_hw_state.fp1 = fp2;
5531 crtc->lowfreq_avail = true;
5532 } else {
5533 crtc->config.dpll_hw_state.fp1 = fp;
5534 }
5535 }
5536
5537 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5538 pipe)
5539 {
5540 u32 reg_val;
5541
5542 /*
5543 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5544 * and set it to a reasonable value instead.
5545 */
5546 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5547 reg_val &= 0xffffff00;
5548 reg_val |= 0x00000030;
5549 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5550
5551 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5552 reg_val &= 0x8cffffff;
5553 reg_val = 0x8c000000;
5554 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5555
5556 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5557 reg_val &= 0xffffff00;
5558 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5559
5560 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5561 reg_val &= 0x00ffffff;
5562 reg_val |= 0xb0000000;
5563 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5564 }
5565
5566 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5567 struct intel_link_m_n *m_n)
5568 {
5569 struct drm_device *dev = crtc->base.dev;
5570 struct drm_i915_private *dev_priv = dev->dev_private;
5571 int pipe = crtc->pipe;
5572
5573 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5574 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5575 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5576 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5577 }
5578
5579 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5580 struct intel_link_m_n *m_n,
5581 struct intel_link_m_n *m2_n2)
5582 {
5583 struct drm_device *dev = crtc->base.dev;
5584 struct drm_i915_private *dev_priv = dev->dev_private;
5585 int pipe = crtc->pipe;
5586 enum transcoder transcoder = crtc->config.cpu_transcoder;
5587
5588 if (INTEL_INFO(dev)->gen >= 5) {
5589 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5590 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5591 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5592 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5593 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5594 * for gen < 8) and if DRRS is supported (to make sure the
5595 * registers are not unnecessarily accessed).
5596 */
5597 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5598 crtc->config.has_drrs) {
5599 I915_WRITE(PIPE_DATA_M2(transcoder),
5600 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5601 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5602 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5603 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5604 }
5605 } else {
5606 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5607 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5608 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5609 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5610 }
5611 }
5612
5613 void intel_dp_set_m_n(struct intel_crtc *crtc)
5614 {
5615 if (crtc->config.has_pch_encoder)
5616 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5617 else
5618 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
5619 &crtc->config.dp_m2_n2);
5620 }
5621
5622 static void vlv_update_pll(struct intel_crtc *crtc)
5623 {
5624 u32 dpll, dpll_md;
5625
5626 /*
5627 * Enable DPIO clock input. We should never disable the reference
5628 * clock for pipe B, since VGA hotplug / manual detection depends
5629 * on it.
5630 */
5631 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5632 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5633 /* We should never disable this, set it here for state tracking */
5634 if (crtc->pipe == PIPE_B)
5635 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5636 dpll |= DPLL_VCO_ENABLE;
5637 crtc->config.dpll_hw_state.dpll = dpll;
5638
5639 dpll_md = (crtc->config.pixel_multiplier - 1)
5640 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5641 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5642 }
5643
5644 static void vlv_prepare_pll(struct intel_crtc *crtc)
5645 {
5646 struct drm_device *dev = crtc->base.dev;
5647 struct drm_i915_private *dev_priv = dev->dev_private;
5648 int pipe = crtc->pipe;
5649 u32 mdiv;
5650 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5651 u32 coreclk, reg_val;
5652
5653 mutex_lock(&dev_priv->dpio_lock);
5654
5655 bestn = crtc->config.dpll.n;
5656 bestm1 = crtc->config.dpll.m1;
5657 bestm2 = crtc->config.dpll.m2;
5658 bestp1 = crtc->config.dpll.p1;
5659 bestp2 = crtc->config.dpll.p2;
5660
5661 /* See eDP HDMI DPIO driver vbios notes doc */
5662
5663 /* PLL B needs special handling */
5664 if (pipe == PIPE_B)
5665 vlv_pllb_recal_opamp(dev_priv, pipe);
5666
5667 /* Set up Tx target for periodic Rcomp update */
5668 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5669
5670 /* Disable target IRef on PLL */
5671 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5672 reg_val &= 0x00ffffff;
5673 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5674
5675 /* Disable fast lock */
5676 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5677
5678 /* Set idtafcrecal before PLL is enabled */
5679 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5680 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5681 mdiv |= ((bestn << DPIO_N_SHIFT));
5682 mdiv |= (1 << DPIO_K_SHIFT);
5683
5684 /*
5685 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5686 * but we don't support that).
5687 * Note: don't use the DAC post divider as it seems unstable.
5688 */
5689 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5690 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5691
5692 mdiv |= DPIO_ENABLE_CALIBRATION;
5693 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5694
5695 /* Set HBR and RBR LPF coefficients */
5696 if (crtc->config.port_clock == 162000 ||
5697 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5698 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5699 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5700 0x009f0003);
5701 else
5702 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5703 0x00d0000f);
5704
5705 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5706 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5707 /* Use SSC source */
5708 if (pipe == PIPE_A)
5709 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5710 0x0df40000);
5711 else
5712 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5713 0x0df70000);
5714 } else { /* HDMI or VGA */
5715 /* Use bend source */
5716 if (pipe == PIPE_A)
5717 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5718 0x0df70000);
5719 else
5720 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5721 0x0df40000);
5722 }
5723
5724 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5725 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5726 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5727 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5728 coreclk |= 0x01000000;
5729 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5730
5731 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5732 mutex_unlock(&dev_priv->dpio_lock);
5733 }
5734
5735 static void chv_update_pll(struct intel_crtc *crtc)
5736 {
5737 crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5738 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5739 DPLL_VCO_ENABLE;
5740 if (crtc->pipe != PIPE_A)
5741 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5742
5743 crtc->config.dpll_hw_state.dpll_md =
5744 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5745 }
5746
5747 static void chv_prepare_pll(struct intel_crtc *crtc)
5748 {
5749 struct drm_device *dev = crtc->base.dev;
5750 struct drm_i915_private *dev_priv = dev->dev_private;
5751 int pipe = crtc->pipe;
5752 int dpll_reg = DPLL(crtc->pipe);
5753 enum dpio_channel port = vlv_pipe_to_channel(pipe);
5754 u32 loopfilter, intcoeff;
5755 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5756 int refclk;
5757
5758 bestn = crtc->config.dpll.n;
5759 bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5760 bestm1 = crtc->config.dpll.m1;
5761 bestm2 = crtc->config.dpll.m2 >> 22;
5762 bestp1 = crtc->config.dpll.p1;
5763 bestp2 = crtc->config.dpll.p2;
5764
5765 /*
5766 * Enable Refclk and SSC
5767 */
5768 I915_WRITE(dpll_reg,
5769 crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5770
5771 mutex_lock(&dev_priv->dpio_lock);
5772
5773 /* p1 and p2 divider */
5774 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5775 5 << DPIO_CHV_S1_DIV_SHIFT |
5776 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5777 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5778 1 << DPIO_CHV_K_DIV_SHIFT);
5779
5780 /* Feedback post-divider - m2 */
5781 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5782
5783 /* Feedback refclk divider - n and m1 */
5784 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5785 DPIO_CHV_M1_DIV_BY_2 |
5786 1 << DPIO_CHV_N_DIV_SHIFT);
5787
5788 /* M2 fraction division */
5789 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5790
5791 /* M2 fraction division enable */
5792 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5793 DPIO_CHV_FRAC_DIV_EN |
5794 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5795
5796 /* Loop filter */
5797 refclk = i9xx_get_refclk(&crtc->base, 0);
5798 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5799 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5800 if (refclk == 100000)
5801 intcoeff = 11;
5802 else if (refclk == 38400)
5803 intcoeff = 10;
5804 else
5805 intcoeff = 9;
5806 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5807 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5808
5809 /* AFC Recal */
5810 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5811 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5812 DPIO_AFC_RECAL);
5813
5814 mutex_unlock(&dev_priv->dpio_lock);
5815 }
5816
5817 static void i9xx_update_pll(struct intel_crtc *crtc,
5818 intel_clock_t *reduced_clock,
5819 int num_connectors)
5820 {
5821 struct drm_device *dev = crtc->base.dev;
5822 struct drm_i915_private *dev_priv = dev->dev_private;
5823 u32 dpll;
5824 bool is_sdvo;
5825 struct dpll *clock = &crtc->config.dpll;
5826
5827 i9xx_update_pll_dividers(crtc, reduced_clock);
5828
5829 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5830 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5831
5832 dpll = DPLL_VGA_MODE_DIS;
5833
5834 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5835 dpll |= DPLLB_MODE_LVDS;
5836 else
5837 dpll |= DPLLB_MODE_DAC_SERIAL;
5838
5839 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5840 dpll |= (crtc->config.pixel_multiplier - 1)
5841 << SDVO_MULTIPLIER_SHIFT_HIRES;
5842 }
5843
5844 if (is_sdvo)
5845 dpll |= DPLL_SDVO_HIGH_SPEED;
5846
5847 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5848 dpll |= DPLL_SDVO_HIGH_SPEED;
5849
5850 /* compute bitmask from p1 value */
5851 if (IS_PINEVIEW(dev))
5852 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5853 else {
5854 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5855 if (IS_G4X(dev) && reduced_clock)
5856 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5857 }
5858 switch (clock->p2) {
5859 case 5:
5860 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5861 break;
5862 case 7:
5863 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5864 break;
5865 case 10:
5866 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5867 break;
5868 case 14:
5869 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5870 break;
5871 }
5872 if (INTEL_INFO(dev)->gen >= 4)
5873 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5874
5875 if (crtc->config.sdvo_tv_clock)
5876 dpll |= PLL_REF_INPUT_TVCLKINBC;
5877 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5878 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5879 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5880 else
5881 dpll |= PLL_REF_INPUT_DREFCLK;
5882
5883 dpll |= DPLL_VCO_ENABLE;
5884 crtc->config.dpll_hw_state.dpll = dpll;
5885
5886 if (INTEL_INFO(dev)->gen >= 4) {
5887 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5888 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5889 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5890 }
5891 }
5892
5893 static void i8xx_update_pll(struct intel_crtc *crtc,
5894 intel_clock_t *reduced_clock,
5895 int num_connectors)
5896 {
5897 struct drm_device *dev = crtc->base.dev;
5898 struct drm_i915_private *dev_priv = dev->dev_private;
5899 u32 dpll;
5900 struct dpll *clock = &crtc->config.dpll;
5901
5902 i9xx_update_pll_dividers(crtc, reduced_clock);
5903
5904 dpll = DPLL_VGA_MODE_DIS;
5905
5906 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5907 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5908 } else {
5909 if (clock->p1 == 2)
5910 dpll |= PLL_P1_DIVIDE_BY_TWO;
5911 else
5912 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5913 if (clock->p2 == 4)
5914 dpll |= PLL_P2_DIVIDE_BY_4;
5915 }
5916
5917 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5918 dpll |= DPLL_DVO_2X_MODE;
5919
5920 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5921 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5922 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5923 else
5924 dpll |= PLL_REF_INPUT_DREFCLK;
5925
5926 dpll |= DPLL_VCO_ENABLE;
5927 crtc->config.dpll_hw_state.dpll = dpll;
5928 }
5929
5930 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5931 {
5932 struct drm_device *dev = intel_crtc->base.dev;
5933 struct drm_i915_private *dev_priv = dev->dev_private;
5934 enum pipe pipe = intel_crtc->pipe;
5935 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5936 struct drm_display_mode *adjusted_mode =
5937 &intel_crtc->config.adjusted_mode;
5938 uint32_t crtc_vtotal, crtc_vblank_end;
5939 int vsyncshift = 0;
5940
5941 /* We need to be careful not to changed the adjusted mode, for otherwise
5942 * the hw state checker will get angry at the mismatch. */
5943 crtc_vtotal = adjusted_mode->crtc_vtotal;
5944 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5945
5946 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5947 /* the chip adds 2 halflines automatically */
5948 crtc_vtotal -= 1;
5949 crtc_vblank_end -= 1;
5950
5951 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5952 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5953 else
5954 vsyncshift = adjusted_mode->crtc_hsync_start -
5955 adjusted_mode->crtc_htotal / 2;
5956 if (vsyncshift < 0)
5957 vsyncshift += adjusted_mode->crtc_htotal;
5958 }
5959
5960 if (INTEL_INFO(dev)->gen > 3)
5961 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5962
5963 I915_WRITE(HTOTAL(cpu_transcoder),
5964 (adjusted_mode->crtc_hdisplay - 1) |
5965 ((adjusted_mode->crtc_htotal - 1) << 16));
5966 I915_WRITE(HBLANK(cpu_transcoder),
5967 (adjusted_mode->crtc_hblank_start - 1) |
5968 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5969 I915_WRITE(HSYNC(cpu_transcoder),
5970 (adjusted_mode->crtc_hsync_start - 1) |
5971 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5972
5973 I915_WRITE(VTOTAL(cpu_transcoder),
5974 (adjusted_mode->crtc_vdisplay - 1) |
5975 ((crtc_vtotal - 1) << 16));
5976 I915_WRITE(VBLANK(cpu_transcoder),
5977 (adjusted_mode->crtc_vblank_start - 1) |
5978 ((crtc_vblank_end - 1) << 16));
5979 I915_WRITE(VSYNC(cpu_transcoder),
5980 (adjusted_mode->crtc_vsync_start - 1) |
5981 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5982
5983 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5984 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5985 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5986 * bits. */
5987 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5988 (pipe == PIPE_B || pipe == PIPE_C))
5989 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5990
5991 /* pipesrc controls the size that is scaled from, which should
5992 * always be the user's requested size.
5993 */
5994 I915_WRITE(PIPESRC(pipe),
5995 ((intel_crtc->config.pipe_src_w - 1) << 16) |
5996 (intel_crtc->config.pipe_src_h - 1));
5997 }
5998
5999 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6000 struct intel_crtc_config *pipe_config)
6001 {
6002 struct drm_device *dev = crtc->base.dev;
6003 struct drm_i915_private *dev_priv = dev->dev_private;
6004 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6005 uint32_t tmp;
6006
6007 tmp = I915_READ(HTOTAL(cpu_transcoder));
6008 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6009 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6010 tmp = I915_READ(HBLANK(cpu_transcoder));
6011 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6012 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6013 tmp = I915_READ(HSYNC(cpu_transcoder));
6014 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6015 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6016
6017 tmp = I915_READ(VTOTAL(cpu_transcoder));
6018 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6019 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6020 tmp = I915_READ(VBLANK(cpu_transcoder));
6021 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6022 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6023 tmp = I915_READ(VSYNC(cpu_transcoder));
6024 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6025 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6026
6027 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6028 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6029 pipe_config->adjusted_mode.crtc_vtotal += 1;
6030 pipe_config->adjusted_mode.crtc_vblank_end += 1;
6031 }
6032
6033 tmp = I915_READ(PIPESRC(crtc->pipe));
6034 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6035 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6036
6037 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
6038 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
6039 }
6040
6041 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6042 struct intel_crtc_config *pipe_config)
6043 {
6044 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
6045 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
6046 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
6047 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
6048
6049 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
6050 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
6051 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
6052 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
6053
6054 mode->flags = pipe_config->adjusted_mode.flags;
6055
6056 mode->clock = pipe_config->adjusted_mode.crtc_clock;
6057 mode->flags |= pipe_config->adjusted_mode.flags;
6058 }
6059
6060 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6061 {
6062 struct drm_device *dev = intel_crtc->base.dev;
6063 struct drm_i915_private *dev_priv = dev->dev_private;
6064 uint32_t pipeconf;
6065
6066 pipeconf = 0;
6067
6068 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6069 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6070 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6071
6072 if (intel_crtc->config.double_wide)
6073 pipeconf |= PIPECONF_DOUBLE_WIDE;
6074
6075 /* only g4x and later have fancy bpc/dither controls */
6076 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6077 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6078 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
6079 pipeconf |= PIPECONF_DITHER_EN |
6080 PIPECONF_DITHER_TYPE_SP;
6081
6082 switch (intel_crtc->config.pipe_bpp) {
6083 case 18:
6084 pipeconf |= PIPECONF_6BPC;
6085 break;
6086 case 24:
6087 pipeconf |= PIPECONF_8BPC;
6088 break;
6089 case 30:
6090 pipeconf |= PIPECONF_10BPC;
6091 break;
6092 default:
6093 /* Case prevented by intel_choose_pipe_bpp_dither. */
6094 BUG();
6095 }
6096 }
6097
6098 if (HAS_PIPE_CXSR(dev)) {
6099 if (intel_crtc->lowfreq_avail) {
6100 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6101 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6102 } else {
6103 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6104 }
6105 }
6106
6107 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6108 if (INTEL_INFO(dev)->gen < 4 ||
6109 intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
6110 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6111 else
6112 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6113 } else
6114 pipeconf |= PIPECONF_PROGRESSIVE;
6115
6116 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6117 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6118
6119 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6120 POSTING_READ(PIPECONF(intel_crtc->pipe));
6121 }
6122
6123 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
6124 int x, int y,
6125 struct drm_framebuffer *fb)
6126 {
6127 struct drm_device *dev = crtc->dev;
6128 struct drm_i915_private *dev_priv = dev->dev_private;
6129 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6130 int refclk, num_connectors = 0;
6131 intel_clock_t clock, reduced_clock;
6132 bool ok, has_reduced_clock = false;
6133 bool is_lvds = false, is_dsi = false;
6134 struct intel_encoder *encoder;
6135 const intel_limit_t *limit;
6136
6137 for_each_encoder_on_crtc(dev, crtc, encoder) {
6138 switch (encoder->type) {
6139 case INTEL_OUTPUT_LVDS:
6140 is_lvds = true;
6141 break;
6142 case INTEL_OUTPUT_DSI:
6143 is_dsi = true;
6144 break;
6145 }
6146
6147 num_connectors++;
6148 }
6149
6150 if (is_dsi)
6151 return 0;
6152
6153 if (!intel_crtc->config.clock_set) {
6154 refclk = i9xx_get_refclk(crtc, num_connectors);
6155
6156 /*
6157 * Returns a set of divisors for the desired target clock with
6158 * the given refclk, or FALSE. The returned values represent
6159 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6160 * 2) / p1 / p2.
6161 */
6162 limit = intel_limit(crtc, refclk);
6163 ok = dev_priv->display.find_dpll(limit, crtc,
6164 intel_crtc->config.port_clock,
6165 refclk, NULL, &clock);
6166 if (!ok) {
6167 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6168 return -EINVAL;
6169 }
6170
6171 if (is_lvds && dev_priv->lvds_downclock_avail) {
6172 /*
6173 * Ensure we match the reduced clock's P to the target
6174 * clock. If the clocks don't match, we can't switch
6175 * the display clock by using the FP0/FP1. In such case
6176 * we will disable the LVDS downclock feature.
6177 */
6178 has_reduced_clock =
6179 dev_priv->display.find_dpll(limit, crtc,
6180 dev_priv->lvds_downclock,
6181 refclk, &clock,
6182 &reduced_clock);
6183 }
6184 /* Compat-code for transition, will disappear. */
6185 intel_crtc->config.dpll.n = clock.n;
6186 intel_crtc->config.dpll.m1 = clock.m1;
6187 intel_crtc->config.dpll.m2 = clock.m2;
6188 intel_crtc->config.dpll.p1 = clock.p1;
6189 intel_crtc->config.dpll.p2 = clock.p2;
6190 }
6191
6192 if (IS_GEN2(dev)) {
6193 i8xx_update_pll(intel_crtc,
6194 has_reduced_clock ? &reduced_clock : NULL,
6195 num_connectors);
6196 } else if (IS_CHERRYVIEW(dev)) {
6197 chv_update_pll(intel_crtc);
6198 } else if (IS_VALLEYVIEW(dev)) {
6199 vlv_update_pll(intel_crtc);
6200 } else {
6201 i9xx_update_pll(intel_crtc,
6202 has_reduced_clock ? &reduced_clock : NULL,
6203 num_connectors);
6204 }
6205
6206 return 0;
6207 }
6208
6209 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6210 struct intel_crtc_config *pipe_config)
6211 {
6212 struct drm_device *dev = crtc->base.dev;
6213 struct drm_i915_private *dev_priv = dev->dev_private;
6214 uint32_t tmp;
6215
6216 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6217 return;
6218
6219 tmp = I915_READ(PFIT_CONTROL);
6220 if (!(tmp & PFIT_ENABLE))
6221 return;
6222
6223 /* Check whether the pfit is attached to our pipe. */
6224 if (INTEL_INFO(dev)->gen < 4) {
6225 if (crtc->pipe != PIPE_B)
6226 return;
6227 } else {
6228 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6229 return;
6230 }
6231
6232 pipe_config->gmch_pfit.control = tmp;
6233 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6234 if (INTEL_INFO(dev)->gen < 5)
6235 pipe_config->gmch_pfit.lvds_border_bits =
6236 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6237 }
6238
6239 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6240 struct intel_crtc_config *pipe_config)
6241 {
6242 struct drm_device *dev = crtc->base.dev;
6243 struct drm_i915_private *dev_priv = dev->dev_private;
6244 int pipe = pipe_config->cpu_transcoder;
6245 intel_clock_t clock;
6246 u32 mdiv;
6247 int refclk = 100000;
6248
6249 /* In case of MIPI DPLL will not even be used */
6250 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6251 return;
6252
6253 mutex_lock(&dev_priv->dpio_lock);
6254 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6255 mutex_unlock(&dev_priv->dpio_lock);
6256
6257 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6258 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6259 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6260 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6261 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6262
6263 vlv_clock(refclk, &clock);
6264
6265 /* clock.dot is the fast clock */
6266 pipe_config->port_clock = clock.dot / 5;
6267 }
6268
6269 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6270 struct intel_plane_config *plane_config)
6271 {
6272 struct drm_device *dev = crtc->base.dev;
6273 struct drm_i915_private *dev_priv = dev->dev_private;
6274 u32 val, base, offset;
6275 int pipe = crtc->pipe, plane = crtc->plane;
6276 int fourcc, pixel_format;
6277 int aligned_height;
6278
6279 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6280 if (!crtc->base.primary->fb) {
6281 DRM_DEBUG_KMS("failed to alloc fb\n");
6282 return;
6283 }
6284
6285 val = I915_READ(DSPCNTR(plane));
6286
6287 if (INTEL_INFO(dev)->gen >= 4)
6288 if (val & DISPPLANE_TILED)
6289 plane_config->tiled = true;
6290
6291 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6292 fourcc = intel_format_to_fourcc(pixel_format);
6293 crtc->base.primary->fb->pixel_format = fourcc;
6294 crtc->base.primary->fb->bits_per_pixel =
6295 drm_format_plane_cpp(fourcc, 0) * 8;
6296
6297 if (INTEL_INFO(dev)->gen >= 4) {
6298 if (plane_config->tiled)
6299 offset = I915_READ(DSPTILEOFF(plane));
6300 else
6301 offset = I915_READ(DSPLINOFF(plane));
6302 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6303 } else {
6304 base = I915_READ(DSPADDR(plane));
6305 }
6306 plane_config->base = base;
6307
6308 val = I915_READ(PIPESRC(pipe));
6309 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6310 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6311
6312 val = I915_READ(DSPSTRIDE(pipe));
6313 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
6314
6315 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6316 plane_config->tiled);
6317
6318 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6319 aligned_height);
6320
6321 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6322 pipe, plane, crtc->base.primary->fb->width,
6323 crtc->base.primary->fb->height,
6324 crtc->base.primary->fb->bits_per_pixel, base,
6325 crtc->base.primary->fb->pitches[0],
6326 plane_config->size);
6327
6328 }
6329
6330 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6331 struct intel_crtc_config *pipe_config)
6332 {
6333 struct drm_device *dev = crtc->base.dev;
6334 struct drm_i915_private *dev_priv = dev->dev_private;
6335 int pipe = pipe_config->cpu_transcoder;
6336 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6337 intel_clock_t clock;
6338 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6339 int refclk = 100000;
6340
6341 mutex_lock(&dev_priv->dpio_lock);
6342 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6343 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6344 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6345 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6346 mutex_unlock(&dev_priv->dpio_lock);
6347
6348 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6349 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6350 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6351 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6352 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6353
6354 chv_clock(refclk, &clock);
6355
6356 /* clock.dot is the fast clock */
6357 pipe_config->port_clock = clock.dot / 5;
6358 }
6359
6360 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6361 struct intel_crtc_config *pipe_config)
6362 {
6363 struct drm_device *dev = crtc->base.dev;
6364 struct drm_i915_private *dev_priv = dev->dev_private;
6365 uint32_t tmp;
6366
6367 if (!intel_display_power_enabled(dev_priv,
6368 POWER_DOMAIN_PIPE(crtc->pipe)))
6369 return false;
6370
6371 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6372 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6373
6374 tmp = I915_READ(PIPECONF(crtc->pipe));
6375 if (!(tmp & PIPECONF_ENABLE))
6376 return false;
6377
6378 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6379 switch (tmp & PIPECONF_BPC_MASK) {
6380 case PIPECONF_6BPC:
6381 pipe_config->pipe_bpp = 18;
6382 break;
6383 case PIPECONF_8BPC:
6384 pipe_config->pipe_bpp = 24;
6385 break;
6386 case PIPECONF_10BPC:
6387 pipe_config->pipe_bpp = 30;
6388 break;
6389 default:
6390 break;
6391 }
6392 }
6393
6394 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6395 pipe_config->limited_color_range = true;
6396
6397 if (INTEL_INFO(dev)->gen < 4)
6398 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6399
6400 intel_get_pipe_timings(crtc, pipe_config);
6401
6402 i9xx_get_pfit_config(crtc, pipe_config);
6403
6404 if (INTEL_INFO(dev)->gen >= 4) {
6405 tmp = I915_READ(DPLL_MD(crtc->pipe));
6406 pipe_config->pixel_multiplier =
6407 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6408 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6409 pipe_config->dpll_hw_state.dpll_md = tmp;
6410 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6411 tmp = I915_READ(DPLL(crtc->pipe));
6412 pipe_config->pixel_multiplier =
6413 ((tmp & SDVO_MULTIPLIER_MASK)
6414 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6415 } else {
6416 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6417 * port and will be fixed up in the encoder->get_config
6418 * function. */
6419 pipe_config->pixel_multiplier = 1;
6420 }
6421 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6422 if (!IS_VALLEYVIEW(dev)) {
6423 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6424 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6425 } else {
6426 /* Mask out read-only status bits. */
6427 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6428 DPLL_PORTC_READY_MASK |
6429 DPLL_PORTB_READY_MASK);
6430 }
6431
6432 if (IS_CHERRYVIEW(dev))
6433 chv_crtc_clock_get(crtc, pipe_config);
6434 else if (IS_VALLEYVIEW(dev))
6435 vlv_crtc_clock_get(crtc, pipe_config);
6436 else
6437 i9xx_crtc_clock_get(crtc, pipe_config);
6438
6439 return true;
6440 }
6441
6442 static void ironlake_init_pch_refclk(struct drm_device *dev)
6443 {
6444 struct drm_i915_private *dev_priv = dev->dev_private;
6445 struct intel_encoder *encoder;
6446 u32 val, final;
6447 bool has_lvds = false;
6448 bool has_cpu_edp = false;
6449 bool has_panel = false;
6450 bool has_ck505 = false;
6451 bool can_ssc = false;
6452
6453 /* We need to take the global config into account */
6454 for_each_intel_encoder(dev, encoder) {
6455 switch (encoder->type) {
6456 case INTEL_OUTPUT_LVDS:
6457 has_panel = true;
6458 has_lvds = true;
6459 break;
6460 case INTEL_OUTPUT_EDP:
6461 has_panel = true;
6462 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6463 has_cpu_edp = true;
6464 break;
6465 }
6466 }
6467
6468 if (HAS_PCH_IBX(dev)) {
6469 has_ck505 = dev_priv->vbt.display_clock_mode;
6470 can_ssc = has_ck505;
6471 } else {
6472 has_ck505 = false;
6473 can_ssc = true;
6474 }
6475
6476 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6477 has_panel, has_lvds, has_ck505);
6478
6479 /* Ironlake: try to setup display ref clock before DPLL
6480 * enabling. This is only under driver's control after
6481 * PCH B stepping, previous chipset stepping should be
6482 * ignoring this setting.
6483 */
6484 val = I915_READ(PCH_DREF_CONTROL);
6485
6486 /* As we must carefully and slowly disable/enable each source in turn,
6487 * compute the final state we want first and check if we need to
6488 * make any changes at all.
6489 */
6490 final = val;
6491 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6492 if (has_ck505)
6493 final |= DREF_NONSPREAD_CK505_ENABLE;
6494 else
6495 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6496
6497 final &= ~DREF_SSC_SOURCE_MASK;
6498 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6499 final &= ~DREF_SSC1_ENABLE;
6500
6501 if (has_panel) {
6502 final |= DREF_SSC_SOURCE_ENABLE;
6503
6504 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6505 final |= DREF_SSC1_ENABLE;
6506
6507 if (has_cpu_edp) {
6508 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6509 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6510 else
6511 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6512 } else
6513 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6514 } else {
6515 final |= DREF_SSC_SOURCE_DISABLE;
6516 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6517 }
6518
6519 if (final == val)
6520 return;
6521
6522 /* Always enable nonspread source */
6523 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6524
6525 if (has_ck505)
6526 val |= DREF_NONSPREAD_CK505_ENABLE;
6527 else
6528 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6529
6530 if (has_panel) {
6531 val &= ~DREF_SSC_SOURCE_MASK;
6532 val |= DREF_SSC_SOURCE_ENABLE;
6533
6534 /* SSC must be turned on before enabling the CPU output */
6535 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6536 DRM_DEBUG_KMS("Using SSC on panel\n");
6537 val |= DREF_SSC1_ENABLE;
6538 } else
6539 val &= ~DREF_SSC1_ENABLE;
6540
6541 /* Get SSC going before enabling the outputs */
6542 I915_WRITE(PCH_DREF_CONTROL, val);
6543 POSTING_READ(PCH_DREF_CONTROL);
6544 udelay(200);
6545
6546 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6547
6548 /* Enable CPU source on CPU attached eDP */
6549 if (has_cpu_edp) {
6550 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6551 DRM_DEBUG_KMS("Using SSC on eDP\n");
6552 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6553 } else
6554 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6555 } else
6556 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6557
6558 I915_WRITE(PCH_DREF_CONTROL, val);
6559 POSTING_READ(PCH_DREF_CONTROL);
6560 udelay(200);
6561 } else {
6562 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6563
6564 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6565
6566 /* Turn off CPU output */
6567 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6568
6569 I915_WRITE(PCH_DREF_CONTROL, val);
6570 POSTING_READ(PCH_DREF_CONTROL);
6571 udelay(200);
6572
6573 /* Turn off the SSC source */
6574 val &= ~DREF_SSC_SOURCE_MASK;
6575 val |= DREF_SSC_SOURCE_DISABLE;
6576
6577 /* Turn off SSC1 */
6578 val &= ~DREF_SSC1_ENABLE;
6579
6580 I915_WRITE(PCH_DREF_CONTROL, val);
6581 POSTING_READ(PCH_DREF_CONTROL);
6582 udelay(200);
6583 }
6584
6585 BUG_ON(val != final);
6586 }
6587
6588 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6589 {
6590 uint32_t tmp;
6591
6592 tmp = I915_READ(SOUTH_CHICKEN2);
6593 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6594 I915_WRITE(SOUTH_CHICKEN2, tmp);
6595
6596 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6597 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6598 DRM_ERROR("FDI mPHY reset assert timeout\n");
6599
6600 tmp = I915_READ(SOUTH_CHICKEN2);
6601 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6602 I915_WRITE(SOUTH_CHICKEN2, tmp);
6603
6604 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6605 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6606 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6607 }
6608
6609 /* WaMPhyProgramming:hsw */
6610 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6611 {
6612 uint32_t tmp;
6613
6614 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6615 tmp &= ~(0xFF << 24);
6616 tmp |= (0x12 << 24);
6617 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6618
6619 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6620 tmp |= (1 << 11);
6621 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6622
6623 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6624 tmp |= (1 << 11);
6625 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6626
6627 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6628 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6629 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6630
6631 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6632 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6633 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6634
6635 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6636 tmp &= ~(7 << 13);
6637 tmp |= (5 << 13);
6638 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6639
6640 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6641 tmp &= ~(7 << 13);
6642 tmp |= (5 << 13);
6643 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6644
6645 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6646 tmp &= ~0xFF;
6647 tmp |= 0x1C;
6648 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6649
6650 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6651 tmp &= ~0xFF;
6652 tmp |= 0x1C;
6653 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6654
6655 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6656 tmp &= ~(0xFF << 16);
6657 tmp |= (0x1C << 16);
6658 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6659
6660 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6661 tmp &= ~(0xFF << 16);
6662 tmp |= (0x1C << 16);
6663 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6664
6665 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6666 tmp |= (1 << 27);
6667 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6668
6669 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6670 tmp |= (1 << 27);
6671 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6672
6673 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6674 tmp &= ~(0xF << 28);
6675 tmp |= (4 << 28);
6676 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6677
6678 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6679 tmp &= ~(0xF << 28);
6680 tmp |= (4 << 28);
6681 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6682 }
6683
6684 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6685 * Programming" based on the parameters passed:
6686 * - Sequence to enable CLKOUT_DP
6687 * - Sequence to enable CLKOUT_DP without spread
6688 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6689 */
6690 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6691 bool with_fdi)
6692 {
6693 struct drm_i915_private *dev_priv = dev->dev_private;
6694 uint32_t reg, tmp;
6695
6696 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6697 with_spread = true;
6698 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6699 with_fdi, "LP PCH doesn't have FDI\n"))
6700 with_fdi = false;
6701
6702 mutex_lock(&dev_priv->dpio_lock);
6703
6704 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6705 tmp &= ~SBI_SSCCTL_DISABLE;
6706 tmp |= SBI_SSCCTL_PATHALT;
6707 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6708
6709 udelay(24);
6710
6711 if (with_spread) {
6712 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6713 tmp &= ~SBI_SSCCTL_PATHALT;
6714 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6715
6716 if (with_fdi) {
6717 lpt_reset_fdi_mphy(dev_priv);
6718 lpt_program_fdi_mphy(dev_priv);
6719 }
6720 }
6721
6722 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6723 SBI_GEN0 : SBI_DBUFF0;
6724 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6725 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6726 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6727
6728 mutex_unlock(&dev_priv->dpio_lock);
6729 }
6730
6731 /* Sequence to disable CLKOUT_DP */
6732 static void lpt_disable_clkout_dp(struct drm_device *dev)
6733 {
6734 struct drm_i915_private *dev_priv = dev->dev_private;
6735 uint32_t reg, tmp;
6736
6737 mutex_lock(&dev_priv->dpio_lock);
6738
6739 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6740 SBI_GEN0 : SBI_DBUFF0;
6741 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6742 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6743 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6744
6745 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6746 if (!(tmp & SBI_SSCCTL_DISABLE)) {
6747 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6748 tmp |= SBI_SSCCTL_PATHALT;
6749 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6750 udelay(32);
6751 }
6752 tmp |= SBI_SSCCTL_DISABLE;
6753 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6754 }
6755
6756 mutex_unlock(&dev_priv->dpio_lock);
6757 }
6758
6759 static void lpt_init_pch_refclk(struct drm_device *dev)
6760 {
6761 struct intel_encoder *encoder;
6762 bool has_vga = false;
6763
6764 for_each_intel_encoder(dev, encoder) {
6765 switch (encoder->type) {
6766 case INTEL_OUTPUT_ANALOG:
6767 has_vga = true;
6768 break;
6769 }
6770 }
6771
6772 if (has_vga)
6773 lpt_enable_clkout_dp(dev, true, true);
6774 else
6775 lpt_disable_clkout_dp(dev);
6776 }
6777
6778 /*
6779 * Initialize reference clocks when the driver loads
6780 */
6781 void intel_init_pch_refclk(struct drm_device *dev)
6782 {
6783 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6784 ironlake_init_pch_refclk(dev);
6785 else if (HAS_PCH_LPT(dev))
6786 lpt_init_pch_refclk(dev);
6787 }
6788
6789 static int ironlake_get_refclk(struct drm_crtc *crtc)
6790 {
6791 struct drm_device *dev = crtc->dev;
6792 struct drm_i915_private *dev_priv = dev->dev_private;
6793 struct intel_encoder *encoder;
6794 int num_connectors = 0;
6795 bool is_lvds = false;
6796
6797 for_each_encoder_on_crtc(dev, crtc, encoder) {
6798 switch (encoder->type) {
6799 case INTEL_OUTPUT_LVDS:
6800 is_lvds = true;
6801 break;
6802 }
6803 num_connectors++;
6804 }
6805
6806 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6807 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6808 dev_priv->vbt.lvds_ssc_freq);
6809 return dev_priv->vbt.lvds_ssc_freq;
6810 }
6811
6812 return 120000;
6813 }
6814
6815 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6816 {
6817 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6818 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6819 int pipe = intel_crtc->pipe;
6820 uint32_t val;
6821
6822 val = 0;
6823
6824 switch (intel_crtc->config.pipe_bpp) {
6825 case 18:
6826 val |= PIPECONF_6BPC;
6827 break;
6828 case 24:
6829 val |= PIPECONF_8BPC;
6830 break;
6831 case 30:
6832 val |= PIPECONF_10BPC;
6833 break;
6834 case 36:
6835 val |= PIPECONF_12BPC;
6836 break;
6837 default:
6838 /* Case prevented by intel_choose_pipe_bpp_dither. */
6839 BUG();
6840 }
6841
6842 if (intel_crtc->config.dither)
6843 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6844
6845 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6846 val |= PIPECONF_INTERLACED_ILK;
6847 else
6848 val |= PIPECONF_PROGRESSIVE;
6849
6850 if (intel_crtc->config.limited_color_range)
6851 val |= PIPECONF_COLOR_RANGE_SELECT;
6852
6853 I915_WRITE(PIPECONF(pipe), val);
6854 POSTING_READ(PIPECONF(pipe));
6855 }
6856
6857 /*
6858 * Set up the pipe CSC unit.
6859 *
6860 * Currently only full range RGB to limited range RGB conversion
6861 * is supported, but eventually this should handle various
6862 * RGB<->YCbCr scenarios as well.
6863 */
6864 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6865 {
6866 struct drm_device *dev = crtc->dev;
6867 struct drm_i915_private *dev_priv = dev->dev_private;
6868 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6869 int pipe = intel_crtc->pipe;
6870 uint16_t coeff = 0x7800; /* 1.0 */
6871
6872 /*
6873 * TODO: Check what kind of values actually come out of the pipe
6874 * with these coeff/postoff values and adjust to get the best
6875 * accuracy. Perhaps we even need to take the bpc value into
6876 * consideration.
6877 */
6878
6879 if (intel_crtc->config.limited_color_range)
6880 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6881
6882 /*
6883 * GY/GU and RY/RU should be the other way around according
6884 * to BSpec, but reality doesn't agree. Just set them up in
6885 * a way that results in the correct picture.
6886 */
6887 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6888 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6889
6890 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6891 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6892
6893 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6894 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6895
6896 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6897 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6898 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6899
6900 if (INTEL_INFO(dev)->gen > 6) {
6901 uint16_t postoff = 0;
6902
6903 if (intel_crtc->config.limited_color_range)
6904 postoff = (16 * (1 << 12) / 255) & 0x1fff;
6905
6906 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6907 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6908 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6909
6910 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6911 } else {
6912 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6913
6914 if (intel_crtc->config.limited_color_range)
6915 mode |= CSC_BLACK_SCREEN_OFFSET;
6916
6917 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6918 }
6919 }
6920
6921 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6922 {
6923 struct drm_device *dev = crtc->dev;
6924 struct drm_i915_private *dev_priv = dev->dev_private;
6925 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6926 enum pipe pipe = intel_crtc->pipe;
6927 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6928 uint32_t val;
6929
6930 val = 0;
6931
6932 if (IS_HASWELL(dev) && intel_crtc->config.dither)
6933 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6934
6935 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6936 val |= PIPECONF_INTERLACED_ILK;
6937 else
6938 val |= PIPECONF_PROGRESSIVE;
6939
6940 I915_WRITE(PIPECONF(cpu_transcoder), val);
6941 POSTING_READ(PIPECONF(cpu_transcoder));
6942
6943 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6944 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6945
6946 if (IS_BROADWELL(dev)) {
6947 val = 0;
6948
6949 switch (intel_crtc->config.pipe_bpp) {
6950 case 18:
6951 val |= PIPEMISC_DITHER_6_BPC;
6952 break;
6953 case 24:
6954 val |= PIPEMISC_DITHER_8_BPC;
6955 break;
6956 case 30:
6957 val |= PIPEMISC_DITHER_10_BPC;
6958 break;
6959 case 36:
6960 val |= PIPEMISC_DITHER_12_BPC;
6961 break;
6962 default:
6963 /* Case prevented by pipe_config_set_bpp. */
6964 BUG();
6965 }
6966
6967 if (intel_crtc->config.dither)
6968 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6969
6970 I915_WRITE(PIPEMISC(pipe), val);
6971 }
6972 }
6973
6974 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6975 intel_clock_t *clock,
6976 bool *has_reduced_clock,
6977 intel_clock_t *reduced_clock)
6978 {
6979 struct drm_device *dev = crtc->dev;
6980 struct drm_i915_private *dev_priv = dev->dev_private;
6981 struct intel_encoder *intel_encoder;
6982 int refclk;
6983 const intel_limit_t *limit;
6984 bool ret, is_lvds = false;
6985
6986 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6987 switch (intel_encoder->type) {
6988 case INTEL_OUTPUT_LVDS:
6989 is_lvds = true;
6990 break;
6991 }
6992 }
6993
6994 refclk = ironlake_get_refclk(crtc);
6995
6996 /*
6997 * Returns a set of divisors for the desired target clock with the given
6998 * refclk, or FALSE. The returned values represent the clock equation:
6999 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7000 */
7001 limit = intel_limit(crtc, refclk);
7002 ret = dev_priv->display.find_dpll(limit, crtc,
7003 to_intel_crtc(crtc)->config.port_clock,
7004 refclk, NULL, clock);
7005 if (!ret)
7006 return false;
7007
7008 if (is_lvds && dev_priv->lvds_downclock_avail) {
7009 /*
7010 * Ensure we match the reduced clock's P to the target clock.
7011 * If the clocks don't match, we can't switch the display clock
7012 * by using the FP0/FP1. In such case we will disable the LVDS
7013 * downclock feature.
7014 */
7015 *has_reduced_clock =
7016 dev_priv->display.find_dpll(limit, crtc,
7017 dev_priv->lvds_downclock,
7018 refclk, clock,
7019 reduced_clock);
7020 }
7021
7022 return true;
7023 }
7024
7025 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7026 {
7027 /*
7028 * Account for spread spectrum to avoid
7029 * oversubscribing the link. Max center spread
7030 * is 2.5%; use 5% for safety's sake.
7031 */
7032 u32 bps = target_clock * bpp * 21 / 20;
7033 return DIV_ROUND_UP(bps, link_bw * 8);
7034 }
7035
7036 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7037 {
7038 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7039 }
7040
7041 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7042 u32 *fp,
7043 intel_clock_t *reduced_clock, u32 *fp2)
7044 {
7045 struct drm_crtc *crtc = &intel_crtc->base;
7046 struct drm_device *dev = crtc->dev;
7047 struct drm_i915_private *dev_priv = dev->dev_private;
7048 struct intel_encoder *intel_encoder;
7049 uint32_t dpll;
7050 int factor, num_connectors = 0;
7051 bool is_lvds = false, is_sdvo = false;
7052
7053 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
7054 switch (intel_encoder->type) {
7055 case INTEL_OUTPUT_LVDS:
7056 is_lvds = true;
7057 break;
7058 case INTEL_OUTPUT_SDVO:
7059 case INTEL_OUTPUT_HDMI:
7060 is_sdvo = true;
7061 break;
7062 }
7063
7064 num_connectors++;
7065 }
7066
7067 /* Enable autotuning of the PLL clock (if permissible) */
7068 factor = 21;
7069 if (is_lvds) {
7070 if ((intel_panel_use_ssc(dev_priv) &&
7071 dev_priv->vbt.lvds_ssc_freq == 100000) ||
7072 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7073 factor = 25;
7074 } else if (intel_crtc->config.sdvo_tv_clock)
7075 factor = 20;
7076
7077 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7078 *fp |= FP_CB_TUNE;
7079
7080 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7081 *fp2 |= FP_CB_TUNE;
7082
7083 dpll = 0;
7084
7085 if (is_lvds)
7086 dpll |= DPLLB_MODE_LVDS;
7087 else
7088 dpll |= DPLLB_MODE_DAC_SERIAL;
7089
7090 dpll |= (intel_crtc->config.pixel_multiplier - 1)
7091 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7092
7093 if (is_sdvo)
7094 dpll |= DPLL_SDVO_HIGH_SPEED;
7095 if (intel_crtc->config.has_dp_encoder)
7096 dpll |= DPLL_SDVO_HIGH_SPEED;
7097
7098 /* compute bitmask from p1 value */
7099 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7100 /* also FPA1 */
7101 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7102
7103 switch (intel_crtc->config.dpll.p2) {
7104 case 5:
7105 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7106 break;
7107 case 7:
7108 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7109 break;
7110 case 10:
7111 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7112 break;
7113 case 14:
7114 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7115 break;
7116 }
7117
7118 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7119 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7120 else
7121 dpll |= PLL_REF_INPUT_DREFCLK;
7122
7123 return dpll | DPLL_VCO_ENABLE;
7124 }
7125
7126 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
7127 int x, int y,
7128 struct drm_framebuffer *fb)
7129 {
7130 struct drm_device *dev = crtc->dev;
7131 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7132 int num_connectors = 0;
7133 intel_clock_t clock, reduced_clock;
7134 u32 dpll = 0, fp = 0, fp2 = 0;
7135 bool ok, has_reduced_clock = false;
7136 bool is_lvds = false;
7137 struct intel_encoder *encoder;
7138 struct intel_shared_dpll *pll;
7139
7140 for_each_encoder_on_crtc(dev, crtc, encoder) {
7141 switch (encoder->type) {
7142 case INTEL_OUTPUT_LVDS:
7143 is_lvds = true;
7144 break;
7145 }
7146
7147 num_connectors++;
7148 }
7149
7150 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7151 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7152
7153 ok = ironlake_compute_clocks(crtc, &clock,
7154 &has_reduced_clock, &reduced_clock);
7155 if (!ok && !intel_crtc->config.clock_set) {
7156 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7157 return -EINVAL;
7158 }
7159 /* Compat-code for transition, will disappear. */
7160 if (!intel_crtc->config.clock_set) {
7161 intel_crtc->config.dpll.n = clock.n;
7162 intel_crtc->config.dpll.m1 = clock.m1;
7163 intel_crtc->config.dpll.m2 = clock.m2;
7164 intel_crtc->config.dpll.p1 = clock.p1;
7165 intel_crtc->config.dpll.p2 = clock.p2;
7166 }
7167
7168 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7169 if (intel_crtc->config.has_pch_encoder) {
7170 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
7171 if (has_reduced_clock)
7172 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7173
7174 dpll = ironlake_compute_dpll(intel_crtc,
7175 &fp, &reduced_clock,
7176 has_reduced_clock ? &fp2 : NULL);
7177
7178 intel_crtc->config.dpll_hw_state.dpll = dpll;
7179 intel_crtc->config.dpll_hw_state.fp0 = fp;
7180 if (has_reduced_clock)
7181 intel_crtc->config.dpll_hw_state.fp1 = fp2;
7182 else
7183 intel_crtc->config.dpll_hw_state.fp1 = fp;
7184
7185 pll = intel_get_shared_dpll(intel_crtc);
7186 if (pll == NULL) {
7187 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7188 pipe_name(intel_crtc->pipe));
7189 return -EINVAL;
7190 }
7191 } else
7192 intel_put_shared_dpll(intel_crtc);
7193
7194 if (is_lvds && has_reduced_clock && i915.powersave)
7195 intel_crtc->lowfreq_avail = true;
7196 else
7197 intel_crtc->lowfreq_avail = false;
7198
7199 return 0;
7200 }
7201
7202 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7203 struct intel_link_m_n *m_n)
7204 {
7205 struct drm_device *dev = crtc->base.dev;
7206 struct drm_i915_private *dev_priv = dev->dev_private;
7207 enum pipe pipe = crtc->pipe;
7208
7209 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7210 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7211 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7212 & ~TU_SIZE_MASK;
7213 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7214 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7215 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7216 }
7217
7218 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7219 enum transcoder transcoder,
7220 struct intel_link_m_n *m_n,
7221 struct intel_link_m_n *m2_n2)
7222 {
7223 struct drm_device *dev = crtc->base.dev;
7224 struct drm_i915_private *dev_priv = dev->dev_private;
7225 enum pipe pipe = crtc->pipe;
7226
7227 if (INTEL_INFO(dev)->gen >= 5) {
7228 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7229 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7230 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7231 & ~TU_SIZE_MASK;
7232 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7233 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7234 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7235 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7236 * gen < 8) and if DRRS is supported (to make sure the
7237 * registers are not unnecessarily read).
7238 */
7239 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7240 crtc->config.has_drrs) {
7241 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7242 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7243 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7244 & ~TU_SIZE_MASK;
7245 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7246 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7247 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7248 }
7249 } else {
7250 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7251 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7252 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7253 & ~TU_SIZE_MASK;
7254 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7255 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7256 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7257 }
7258 }
7259
7260 void intel_dp_get_m_n(struct intel_crtc *crtc,
7261 struct intel_crtc_config *pipe_config)
7262 {
7263 if (crtc->config.has_pch_encoder)
7264 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7265 else
7266 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7267 &pipe_config->dp_m_n,
7268 &pipe_config->dp_m2_n2);
7269 }
7270
7271 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7272 struct intel_crtc_config *pipe_config)
7273 {
7274 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7275 &pipe_config->fdi_m_n, NULL);
7276 }
7277
7278 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7279 struct intel_crtc_config *pipe_config)
7280 {
7281 struct drm_device *dev = crtc->base.dev;
7282 struct drm_i915_private *dev_priv = dev->dev_private;
7283 uint32_t tmp;
7284
7285 tmp = I915_READ(PF_CTL(crtc->pipe));
7286
7287 if (tmp & PF_ENABLE) {
7288 pipe_config->pch_pfit.enabled = true;
7289 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7290 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7291
7292 /* We currently do not free assignements of panel fitters on
7293 * ivb/hsw (since we don't use the higher upscaling modes which
7294 * differentiates them) so just WARN about this case for now. */
7295 if (IS_GEN7(dev)) {
7296 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7297 PF_PIPE_SEL_IVB(crtc->pipe));
7298 }
7299 }
7300 }
7301
7302 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7303 struct intel_plane_config *plane_config)
7304 {
7305 struct drm_device *dev = crtc->base.dev;
7306 struct drm_i915_private *dev_priv = dev->dev_private;
7307 u32 val, base, offset;
7308 int pipe = crtc->pipe, plane = crtc->plane;
7309 int fourcc, pixel_format;
7310 int aligned_height;
7311
7312 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7313 if (!crtc->base.primary->fb) {
7314 DRM_DEBUG_KMS("failed to alloc fb\n");
7315 return;
7316 }
7317
7318 val = I915_READ(DSPCNTR(plane));
7319
7320 if (INTEL_INFO(dev)->gen >= 4)
7321 if (val & DISPPLANE_TILED)
7322 plane_config->tiled = true;
7323
7324 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7325 fourcc = intel_format_to_fourcc(pixel_format);
7326 crtc->base.primary->fb->pixel_format = fourcc;
7327 crtc->base.primary->fb->bits_per_pixel =
7328 drm_format_plane_cpp(fourcc, 0) * 8;
7329
7330 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7331 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7332 offset = I915_READ(DSPOFFSET(plane));
7333 } else {
7334 if (plane_config->tiled)
7335 offset = I915_READ(DSPTILEOFF(plane));
7336 else
7337 offset = I915_READ(DSPLINOFF(plane));
7338 }
7339 plane_config->base = base;
7340
7341 val = I915_READ(PIPESRC(pipe));
7342 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7343 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7344
7345 val = I915_READ(DSPSTRIDE(pipe));
7346 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
7347
7348 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7349 plane_config->tiled);
7350
7351 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7352 aligned_height);
7353
7354 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7355 pipe, plane, crtc->base.primary->fb->width,
7356 crtc->base.primary->fb->height,
7357 crtc->base.primary->fb->bits_per_pixel, base,
7358 crtc->base.primary->fb->pitches[0],
7359 plane_config->size);
7360 }
7361
7362 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7363 struct intel_crtc_config *pipe_config)
7364 {
7365 struct drm_device *dev = crtc->base.dev;
7366 struct drm_i915_private *dev_priv = dev->dev_private;
7367 uint32_t tmp;
7368
7369 if (!intel_display_power_enabled(dev_priv,
7370 POWER_DOMAIN_PIPE(crtc->pipe)))
7371 return false;
7372
7373 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7374 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7375
7376 tmp = I915_READ(PIPECONF(crtc->pipe));
7377 if (!(tmp & PIPECONF_ENABLE))
7378 return false;
7379
7380 switch (tmp & PIPECONF_BPC_MASK) {
7381 case PIPECONF_6BPC:
7382 pipe_config->pipe_bpp = 18;
7383 break;
7384 case PIPECONF_8BPC:
7385 pipe_config->pipe_bpp = 24;
7386 break;
7387 case PIPECONF_10BPC:
7388 pipe_config->pipe_bpp = 30;
7389 break;
7390 case PIPECONF_12BPC:
7391 pipe_config->pipe_bpp = 36;
7392 break;
7393 default:
7394 break;
7395 }
7396
7397 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7398 pipe_config->limited_color_range = true;
7399
7400 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7401 struct intel_shared_dpll *pll;
7402
7403 pipe_config->has_pch_encoder = true;
7404
7405 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7406 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7407 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7408
7409 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7410
7411 if (HAS_PCH_IBX(dev_priv->dev)) {
7412 pipe_config->shared_dpll =
7413 (enum intel_dpll_id) crtc->pipe;
7414 } else {
7415 tmp = I915_READ(PCH_DPLL_SEL);
7416 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7417 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7418 else
7419 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7420 }
7421
7422 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7423
7424 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7425 &pipe_config->dpll_hw_state));
7426
7427 tmp = pipe_config->dpll_hw_state.dpll;
7428 pipe_config->pixel_multiplier =
7429 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7430 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7431
7432 ironlake_pch_clock_get(crtc, pipe_config);
7433 } else {
7434 pipe_config->pixel_multiplier = 1;
7435 }
7436
7437 intel_get_pipe_timings(crtc, pipe_config);
7438
7439 ironlake_get_pfit_config(crtc, pipe_config);
7440
7441 return true;
7442 }
7443
7444 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7445 {
7446 struct drm_device *dev = dev_priv->dev;
7447 struct intel_crtc *crtc;
7448
7449 for_each_intel_crtc(dev, crtc)
7450 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7451 pipe_name(crtc->pipe));
7452
7453 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7454 WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7455 WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7456 WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7457 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7458 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7459 "CPU PWM1 enabled\n");
7460 if (IS_HASWELL(dev))
7461 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7462 "CPU PWM2 enabled\n");
7463 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7464 "PCH PWM1 enabled\n");
7465 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7466 "Utility pin enabled\n");
7467 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7468
7469 /*
7470 * In theory we can still leave IRQs enabled, as long as only the HPD
7471 * interrupts remain enabled. We used to check for that, but since it's
7472 * gen-specific and since we only disable LCPLL after we fully disable
7473 * the interrupts, the check below should be enough.
7474 */
7475 WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7476 }
7477
7478 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7479 {
7480 struct drm_device *dev = dev_priv->dev;
7481
7482 if (IS_HASWELL(dev))
7483 return I915_READ(D_COMP_HSW);
7484 else
7485 return I915_READ(D_COMP_BDW);
7486 }
7487
7488 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7489 {
7490 struct drm_device *dev = dev_priv->dev;
7491
7492 if (IS_HASWELL(dev)) {
7493 mutex_lock(&dev_priv->rps.hw_lock);
7494 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7495 val))
7496 DRM_ERROR("Failed to write to D_COMP\n");
7497 mutex_unlock(&dev_priv->rps.hw_lock);
7498 } else {
7499 I915_WRITE(D_COMP_BDW, val);
7500 POSTING_READ(D_COMP_BDW);
7501 }
7502 }
7503
7504 /*
7505 * This function implements pieces of two sequences from BSpec:
7506 * - Sequence for display software to disable LCPLL
7507 * - Sequence for display software to allow package C8+
7508 * The steps implemented here are just the steps that actually touch the LCPLL
7509 * register. Callers should take care of disabling all the display engine
7510 * functions, doing the mode unset, fixing interrupts, etc.
7511 */
7512 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7513 bool switch_to_fclk, bool allow_power_down)
7514 {
7515 uint32_t val;
7516
7517 assert_can_disable_lcpll(dev_priv);
7518
7519 val = I915_READ(LCPLL_CTL);
7520
7521 if (switch_to_fclk) {
7522 val |= LCPLL_CD_SOURCE_FCLK;
7523 I915_WRITE(LCPLL_CTL, val);
7524
7525 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7526 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7527 DRM_ERROR("Switching to FCLK failed\n");
7528
7529 val = I915_READ(LCPLL_CTL);
7530 }
7531
7532 val |= LCPLL_PLL_DISABLE;
7533 I915_WRITE(LCPLL_CTL, val);
7534 POSTING_READ(LCPLL_CTL);
7535
7536 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7537 DRM_ERROR("LCPLL still locked\n");
7538
7539 val = hsw_read_dcomp(dev_priv);
7540 val |= D_COMP_COMP_DISABLE;
7541 hsw_write_dcomp(dev_priv, val);
7542 ndelay(100);
7543
7544 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7545 1))
7546 DRM_ERROR("D_COMP RCOMP still in progress\n");
7547
7548 if (allow_power_down) {
7549 val = I915_READ(LCPLL_CTL);
7550 val |= LCPLL_POWER_DOWN_ALLOW;
7551 I915_WRITE(LCPLL_CTL, val);
7552 POSTING_READ(LCPLL_CTL);
7553 }
7554 }
7555
7556 /*
7557 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7558 * source.
7559 */
7560 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7561 {
7562 uint32_t val;
7563 unsigned long irqflags;
7564
7565 val = I915_READ(LCPLL_CTL);
7566
7567 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7568 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7569 return;
7570
7571 /*
7572 * Make sure we're not on PC8 state before disabling PC8, otherwise
7573 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7574 *
7575 * The other problem is that hsw_restore_lcpll() is called as part of
7576 * the runtime PM resume sequence, so we can't just call
7577 * gen6_gt_force_wake_get() because that function calls
7578 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7579 * while we are on the resume sequence. So to solve this problem we have
7580 * to call special forcewake code that doesn't touch runtime PM and
7581 * doesn't enable the forcewake delayed work.
7582 */
7583 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7584 if (dev_priv->uncore.forcewake_count++ == 0)
7585 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7586 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7587
7588 if (val & LCPLL_POWER_DOWN_ALLOW) {
7589 val &= ~LCPLL_POWER_DOWN_ALLOW;
7590 I915_WRITE(LCPLL_CTL, val);
7591 POSTING_READ(LCPLL_CTL);
7592 }
7593
7594 val = hsw_read_dcomp(dev_priv);
7595 val |= D_COMP_COMP_FORCE;
7596 val &= ~D_COMP_COMP_DISABLE;
7597 hsw_write_dcomp(dev_priv, val);
7598
7599 val = I915_READ(LCPLL_CTL);
7600 val &= ~LCPLL_PLL_DISABLE;
7601 I915_WRITE(LCPLL_CTL, val);
7602
7603 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7604 DRM_ERROR("LCPLL not locked yet\n");
7605
7606 if (val & LCPLL_CD_SOURCE_FCLK) {
7607 val = I915_READ(LCPLL_CTL);
7608 val &= ~LCPLL_CD_SOURCE_FCLK;
7609 I915_WRITE(LCPLL_CTL, val);
7610
7611 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7612 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7613 DRM_ERROR("Switching back to LCPLL failed\n");
7614 }
7615
7616 /* See the big comment above. */
7617 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7618 if (--dev_priv->uncore.forcewake_count == 0)
7619 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7620 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7621 }
7622
7623 /*
7624 * Package states C8 and deeper are really deep PC states that can only be
7625 * reached when all the devices on the system allow it, so even if the graphics
7626 * device allows PC8+, it doesn't mean the system will actually get to these
7627 * states. Our driver only allows PC8+ when going into runtime PM.
7628 *
7629 * The requirements for PC8+ are that all the outputs are disabled, the power
7630 * well is disabled and most interrupts are disabled, and these are also
7631 * requirements for runtime PM. When these conditions are met, we manually do
7632 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7633 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7634 * hang the machine.
7635 *
7636 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7637 * the state of some registers, so when we come back from PC8+ we need to
7638 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7639 * need to take care of the registers kept by RC6. Notice that this happens even
7640 * if we don't put the device in PCI D3 state (which is what currently happens
7641 * because of the runtime PM support).
7642 *
7643 * For more, read "Display Sequences for Package C8" on the hardware
7644 * documentation.
7645 */
7646 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7647 {
7648 struct drm_device *dev = dev_priv->dev;
7649 uint32_t val;
7650
7651 DRM_DEBUG_KMS("Enabling package C8+\n");
7652
7653 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7654 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7655 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7656 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7657 }
7658
7659 lpt_disable_clkout_dp(dev);
7660 hsw_disable_lcpll(dev_priv, true, true);
7661 }
7662
7663 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7664 {
7665 struct drm_device *dev = dev_priv->dev;
7666 uint32_t val;
7667
7668 DRM_DEBUG_KMS("Disabling package C8+\n");
7669
7670 hsw_restore_lcpll(dev_priv);
7671 lpt_init_pch_refclk(dev);
7672
7673 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7674 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7675 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7676 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7677 }
7678
7679 intel_prepare_ddi(dev);
7680 }
7681
7682 static void snb_modeset_global_resources(struct drm_device *dev)
7683 {
7684 modeset_update_crtc_power_domains(dev);
7685 }
7686
7687 static void haswell_modeset_global_resources(struct drm_device *dev)
7688 {
7689 modeset_update_crtc_power_domains(dev);
7690 }
7691
7692 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7693 int x, int y,
7694 struct drm_framebuffer *fb)
7695 {
7696 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7697
7698 if (!intel_ddi_pll_select(intel_crtc))
7699 return -EINVAL;
7700
7701 intel_crtc->lowfreq_avail = false;
7702
7703 return 0;
7704 }
7705
7706 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
7707 enum port port,
7708 struct intel_crtc_config *pipe_config)
7709 {
7710 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
7711
7712 switch (pipe_config->ddi_pll_sel) {
7713 case PORT_CLK_SEL_WRPLL1:
7714 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7715 break;
7716 case PORT_CLK_SEL_WRPLL2:
7717 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7718 break;
7719 }
7720 }
7721
7722 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
7723 struct intel_crtc_config *pipe_config)
7724 {
7725 struct drm_device *dev = crtc->base.dev;
7726 struct drm_i915_private *dev_priv = dev->dev_private;
7727 struct intel_shared_dpll *pll;
7728 enum port port;
7729 uint32_t tmp;
7730
7731 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7732
7733 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
7734
7735 haswell_get_ddi_pll(dev_priv, port, pipe_config);
7736
7737 if (pipe_config->shared_dpll >= 0) {
7738 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7739
7740 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7741 &pipe_config->dpll_hw_state));
7742 }
7743
7744 /*
7745 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7746 * DDI E. So just check whether this pipe is wired to DDI E and whether
7747 * the PCH transcoder is on.
7748 */
7749 if ((port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7750 pipe_config->has_pch_encoder = true;
7751
7752 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7753 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7754 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7755
7756 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7757 }
7758 }
7759
7760 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7761 struct intel_crtc_config *pipe_config)
7762 {
7763 struct drm_device *dev = crtc->base.dev;
7764 struct drm_i915_private *dev_priv = dev->dev_private;
7765 enum intel_display_power_domain pfit_domain;
7766 uint32_t tmp;
7767
7768 if (!intel_display_power_enabled(dev_priv,
7769 POWER_DOMAIN_PIPE(crtc->pipe)))
7770 return false;
7771
7772 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7773 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7774
7775 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7776 if (tmp & TRANS_DDI_FUNC_ENABLE) {
7777 enum pipe trans_edp_pipe;
7778 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7779 default:
7780 WARN(1, "unknown pipe linked to edp transcoder\n");
7781 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7782 case TRANS_DDI_EDP_INPUT_A_ON:
7783 trans_edp_pipe = PIPE_A;
7784 break;
7785 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7786 trans_edp_pipe = PIPE_B;
7787 break;
7788 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7789 trans_edp_pipe = PIPE_C;
7790 break;
7791 }
7792
7793 if (trans_edp_pipe == crtc->pipe)
7794 pipe_config->cpu_transcoder = TRANSCODER_EDP;
7795 }
7796
7797 if (!intel_display_power_enabled(dev_priv,
7798 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7799 return false;
7800
7801 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7802 if (!(tmp & PIPECONF_ENABLE))
7803 return false;
7804
7805 haswell_get_ddi_port_state(crtc, pipe_config);
7806
7807 intel_get_pipe_timings(crtc, pipe_config);
7808
7809 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7810 if (intel_display_power_enabled(dev_priv, pfit_domain))
7811 ironlake_get_pfit_config(crtc, pipe_config);
7812
7813 if (IS_HASWELL(dev))
7814 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7815 (I915_READ(IPS_CTL) & IPS_ENABLE);
7816
7817 pipe_config->pixel_multiplier = 1;
7818
7819 return true;
7820 }
7821
7822 static struct {
7823 int clock;
7824 u32 config;
7825 } hdmi_audio_clock[] = {
7826 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7827 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7828 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7829 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7830 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7831 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7832 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7833 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7834 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7835 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7836 };
7837
7838 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7839 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7840 {
7841 int i;
7842
7843 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7844 if (mode->clock == hdmi_audio_clock[i].clock)
7845 break;
7846 }
7847
7848 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7849 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7850 i = 1;
7851 }
7852
7853 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7854 hdmi_audio_clock[i].clock,
7855 hdmi_audio_clock[i].config);
7856
7857 return hdmi_audio_clock[i].config;
7858 }
7859
7860 static bool intel_eld_uptodate(struct drm_connector *connector,
7861 int reg_eldv, uint32_t bits_eldv,
7862 int reg_elda, uint32_t bits_elda,
7863 int reg_edid)
7864 {
7865 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7866 uint8_t *eld = connector->eld;
7867 uint32_t i;
7868
7869 i = I915_READ(reg_eldv);
7870 i &= bits_eldv;
7871
7872 if (!eld[0])
7873 return !i;
7874
7875 if (!i)
7876 return false;
7877
7878 i = I915_READ(reg_elda);
7879 i &= ~bits_elda;
7880 I915_WRITE(reg_elda, i);
7881
7882 for (i = 0; i < eld[2]; i++)
7883 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7884 return false;
7885
7886 return true;
7887 }
7888
7889 static void g4x_write_eld(struct drm_connector *connector,
7890 struct drm_crtc *crtc,
7891 struct drm_display_mode *mode)
7892 {
7893 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7894 uint8_t *eld = connector->eld;
7895 uint32_t eldv;
7896 uint32_t len;
7897 uint32_t i;
7898
7899 i = I915_READ(G4X_AUD_VID_DID);
7900
7901 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7902 eldv = G4X_ELDV_DEVCL_DEVBLC;
7903 else
7904 eldv = G4X_ELDV_DEVCTG;
7905
7906 if (intel_eld_uptodate(connector,
7907 G4X_AUD_CNTL_ST, eldv,
7908 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7909 G4X_HDMIW_HDMIEDID))
7910 return;
7911
7912 i = I915_READ(G4X_AUD_CNTL_ST);
7913 i &= ~(eldv | G4X_ELD_ADDR);
7914 len = (i >> 9) & 0x1f; /* ELD buffer size */
7915 I915_WRITE(G4X_AUD_CNTL_ST, i);
7916
7917 if (!eld[0])
7918 return;
7919
7920 len = min_t(uint8_t, eld[2], len);
7921 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7922 for (i = 0; i < len; i++)
7923 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7924
7925 i = I915_READ(G4X_AUD_CNTL_ST);
7926 i |= eldv;
7927 I915_WRITE(G4X_AUD_CNTL_ST, i);
7928 }
7929
7930 static void haswell_write_eld(struct drm_connector *connector,
7931 struct drm_crtc *crtc,
7932 struct drm_display_mode *mode)
7933 {
7934 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7935 uint8_t *eld = connector->eld;
7936 uint32_t eldv;
7937 uint32_t i;
7938 int len;
7939 int pipe = to_intel_crtc(crtc)->pipe;
7940 int tmp;
7941
7942 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7943 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7944 int aud_config = HSW_AUD_CFG(pipe);
7945 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7946
7947 /* Audio output enable */
7948 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7949 tmp = I915_READ(aud_cntrl_st2);
7950 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7951 I915_WRITE(aud_cntrl_st2, tmp);
7952 POSTING_READ(aud_cntrl_st2);
7953
7954 assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
7955
7956 /* Set ELD valid state */
7957 tmp = I915_READ(aud_cntrl_st2);
7958 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7959 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7960 I915_WRITE(aud_cntrl_st2, tmp);
7961 tmp = I915_READ(aud_cntrl_st2);
7962 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7963
7964 /* Enable HDMI mode */
7965 tmp = I915_READ(aud_config);
7966 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7967 /* clear N_programing_enable and N_value_index */
7968 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7969 I915_WRITE(aud_config, tmp);
7970
7971 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7972
7973 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7974
7975 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7976 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7977 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7978 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7979 } else {
7980 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7981 }
7982
7983 if (intel_eld_uptodate(connector,
7984 aud_cntrl_st2, eldv,
7985 aud_cntl_st, IBX_ELD_ADDRESS,
7986 hdmiw_hdmiedid))
7987 return;
7988
7989 i = I915_READ(aud_cntrl_st2);
7990 i &= ~eldv;
7991 I915_WRITE(aud_cntrl_st2, i);
7992
7993 if (!eld[0])
7994 return;
7995
7996 i = I915_READ(aud_cntl_st);
7997 i &= ~IBX_ELD_ADDRESS;
7998 I915_WRITE(aud_cntl_st, i);
7999 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
8000 DRM_DEBUG_DRIVER("port num:%d\n", i);
8001
8002 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
8003 DRM_DEBUG_DRIVER("ELD size %d\n", len);
8004 for (i = 0; i < len; i++)
8005 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
8006
8007 i = I915_READ(aud_cntrl_st2);
8008 i |= eldv;
8009 I915_WRITE(aud_cntrl_st2, i);
8010
8011 }
8012
8013 static void ironlake_write_eld(struct drm_connector *connector,
8014 struct drm_crtc *crtc,
8015 struct drm_display_mode *mode)
8016 {
8017 struct drm_i915_private *dev_priv = connector->dev->dev_private;
8018 uint8_t *eld = connector->eld;
8019 uint32_t eldv;
8020 uint32_t i;
8021 int len;
8022 int hdmiw_hdmiedid;
8023 int aud_config;
8024 int aud_cntl_st;
8025 int aud_cntrl_st2;
8026 int pipe = to_intel_crtc(crtc)->pipe;
8027
8028 if (HAS_PCH_IBX(connector->dev)) {
8029 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
8030 aud_config = IBX_AUD_CFG(pipe);
8031 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
8032 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
8033 } else if (IS_VALLEYVIEW(connector->dev)) {
8034 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
8035 aud_config = VLV_AUD_CFG(pipe);
8036 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
8037 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
8038 } else {
8039 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
8040 aud_config = CPT_AUD_CFG(pipe);
8041 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
8042 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
8043 }
8044
8045 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
8046
8047 if (IS_VALLEYVIEW(connector->dev)) {
8048 struct intel_encoder *intel_encoder;
8049 struct intel_digital_port *intel_dig_port;
8050
8051 intel_encoder = intel_attached_encoder(connector);
8052 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
8053 i = intel_dig_port->port;
8054 } else {
8055 i = I915_READ(aud_cntl_st);
8056 i = (i >> 29) & DIP_PORT_SEL_MASK;
8057 /* DIP_Port_Select, 0x1 = PortB */
8058 }
8059
8060 if (!i) {
8061 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
8062 /* operate blindly on all ports */
8063 eldv = IBX_ELD_VALIDB;
8064 eldv |= IBX_ELD_VALIDB << 4;
8065 eldv |= IBX_ELD_VALIDB << 8;
8066 } else {
8067 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
8068 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
8069 }
8070
8071 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
8072 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
8073 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
8074 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
8075 } else {
8076 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
8077 }
8078
8079 if (intel_eld_uptodate(connector,
8080 aud_cntrl_st2, eldv,
8081 aud_cntl_st, IBX_ELD_ADDRESS,
8082 hdmiw_hdmiedid))
8083 return;
8084
8085 i = I915_READ(aud_cntrl_st2);
8086 i &= ~eldv;
8087 I915_WRITE(aud_cntrl_st2, i);
8088
8089 if (!eld[0])
8090 return;
8091
8092 i = I915_READ(aud_cntl_st);
8093 i &= ~IBX_ELD_ADDRESS;
8094 I915_WRITE(aud_cntl_st, i);
8095
8096 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
8097 DRM_DEBUG_DRIVER("ELD size %d\n", len);
8098 for (i = 0; i < len; i++)
8099 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
8100
8101 i = I915_READ(aud_cntrl_st2);
8102 i |= eldv;
8103 I915_WRITE(aud_cntrl_st2, i);
8104 }
8105
8106 void intel_write_eld(struct drm_encoder *encoder,
8107 struct drm_display_mode *mode)
8108 {
8109 struct drm_crtc *crtc = encoder->crtc;
8110 struct drm_connector *connector;
8111 struct drm_device *dev = encoder->dev;
8112 struct drm_i915_private *dev_priv = dev->dev_private;
8113
8114 connector = drm_select_eld(encoder, mode);
8115 if (!connector)
8116 return;
8117
8118 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8119 connector->base.id,
8120 connector->name,
8121 connector->encoder->base.id,
8122 connector->encoder->name);
8123
8124 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
8125
8126 if (dev_priv->display.write_eld)
8127 dev_priv->display.write_eld(connector, crtc, mode);
8128 }
8129
8130 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8131 {
8132 struct drm_device *dev = crtc->dev;
8133 struct drm_i915_private *dev_priv = dev->dev_private;
8134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8135 uint32_t cntl = 0, size = 0;
8136
8137 if (base) {
8138 unsigned int width = intel_crtc->cursor_width;
8139 unsigned int height = intel_crtc->cursor_height;
8140 unsigned int stride = roundup_pow_of_two(width) * 4;
8141
8142 switch (stride) {
8143 default:
8144 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8145 width, stride);
8146 stride = 256;
8147 /* fallthrough */
8148 case 256:
8149 case 512:
8150 case 1024:
8151 case 2048:
8152 break;
8153 }
8154
8155 cntl |= CURSOR_ENABLE |
8156 CURSOR_GAMMA_ENABLE |
8157 CURSOR_FORMAT_ARGB |
8158 CURSOR_STRIDE(stride);
8159
8160 size = (height << 12) | width;
8161 }
8162
8163 if (intel_crtc->cursor_cntl != 0 &&
8164 (intel_crtc->cursor_base != base ||
8165 intel_crtc->cursor_size != size ||
8166 intel_crtc->cursor_cntl != cntl)) {
8167 /* On these chipsets we can only modify the base/size/stride
8168 * whilst the cursor is disabled.
8169 */
8170 I915_WRITE(_CURACNTR, 0);
8171 POSTING_READ(_CURACNTR);
8172 intel_crtc->cursor_cntl = 0;
8173 }
8174
8175 if (intel_crtc->cursor_base != base)
8176 I915_WRITE(_CURABASE, base);
8177
8178 if (intel_crtc->cursor_size != size) {
8179 I915_WRITE(CURSIZE, size);
8180 intel_crtc->cursor_size = size;
8181 }
8182
8183 if (intel_crtc->cursor_cntl != cntl) {
8184 I915_WRITE(_CURACNTR, cntl);
8185 POSTING_READ(_CURACNTR);
8186 intel_crtc->cursor_cntl = cntl;
8187 }
8188 }
8189
8190 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8191 {
8192 struct drm_device *dev = crtc->dev;
8193 struct drm_i915_private *dev_priv = dev->dev_private;
8194 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8195 int pipe = intel_crtc->pipe;
8196 uint32_t cntl;
8197
8198 cntl = 0;
8199 if (base) {
8200 cntl = MCURSOR_GAMMA_ENABLE;
8201 switch (intel_crtc->cursor_width) {
8202 case 64:
8203 cntl |= CURSOR_MODE_64_ARGB_AX;
8204 break;
8205 case 128:
8206 cntl |= CURSOR_MODE_128_ARGB_AX;
8207 break;
8208 case 256:
8209 cntl |= CURSOR_MODE_256_ARGB_AX;
8210 break;
8211 default:
8212 WARN_ON(1);
8213 return;
8214 }
8215 cntl |= pipe << 28; /* Connect to correct pipe */
8216 }
8217 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8218 cntl |= CURSOR_PIPE_CSC_ENABLE;
8219
8220 if (intel_crtc->cursor_cntl != cntl) {
8221 I915_WRITE(CURCNTR(pipe), cntl);
8222 POSTING_READ(CURCNTR(pipe));
8223 intel_crtc->cursor_cntl = cntl;
8224 }
8225
8226 /* and commit changes on next vblank */
8227 I915_WRITE(CURBASE(pipe), base);
8228 POSTING_READ(CURBASE(pipe));
8229 }
8230
8231 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8232 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8233 bool on)
8234 {
8235 struct drm_device *dev = crtc->dev;
8236 struct drm_i915_private *dev_priv = dev->dev_private;
8237 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8238 int pipe = intel_crtc->pipe;
8239 int x = crtc->cursor_x;
8240 int y = crtc->cursor_y;
8241 u32 base = 0, pos = 0;
8242
8243 if (on)
8244 base = intel_crtc->cursor_addr;
8245
8246 if (x >= intel_crtc->config.pipe_src_w)
8247 base = 0;
8248
8249 if (y >= intel_crtc->config.pipe_src_h)
8250 base = 0;
8251
8252 if (x < 0) {
8253 if (x + intel_crtc->cursor_width <= 0)
8254 base = 0;
8255
8256 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8257 x = -x;
8258 }
8259 pos |= x << CURSOR_X_SHIFT;
8260
8261 if (y < 0) {
8262 if (y + intel_crtc->cursor_height <= 0)
8263 base = 0;
8264
8265 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8266 y = -y;
8267 }
8268 pos |= y << CURSOR_Y_SHIFT;
8269
8270 if (base == 0 && intel_crtc->cursor_base == 0)
8271 return;
8272
8273 I915_WRITE(CURPOS(pipe), pos);
8274
8275 if (IS_845G(dev) || IS_I865G(dev))
8276 i845_update_cursor(crtc, base);
8277 else
8278 i9xx_update_cursor(crtc, base);
8279 intel_crtc->cursor_base = base;
8280 }
8281
8282 static bool cursor_size_ok(struct drm_device *dev,
8283 uint32_t width, uint32_t height)
8284 {
8285 if (width == 0 || height == 0)
8286 return false;
8287
8288 /*
8289 * 845g/865g are special in that they are only limited by
8290 * the width of their cursors, the height is arbitrary up to
8291 * the precision of the register. Everything else requires
8292 * square cursors, limited to a few power-of-two sizes.
8293 */
8294 if (IS_845G(dev) || IS_I865G(dev)) {
8295 if ((width & 63) != 0)
8296 return false;
8297
8298 if (width > (IS_845G(dev) ? 64 : 512))
8299 return false;
8300
8301 if (height > 1023)
8302 return false;
8303 } else {
8304 switch (width | height) {
8305 case 256:
8306 case 128:
8307 if (IS_GEN2(dev))
8308 return false;
8309 case 64:
8310 break;
8311 default:
8312 return false;
8313 }
8314 }
8315
8316 return true;
8317 }
8318
8319 /*
8320 * intel_crtc_cursor_set_obj - Set cursor to specified GEM object
8321 *
8322 * Note that the object's reference will be consumed if the update fails. If
8323 * the update succeeds, the reference of the old object (if any) will be
8324 * consumed.
8325 */
8326 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8327 struct drm_i915_gem_object *obj,
8328 uint32_t width, uint32_t height)
8329 {
8330 struct drm_device *dev = crtc->dev;
8331 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8332 enum pipe pipe = intel_crtc->pipe;
8333 unsigned old_width, stride;
8334 uint32_t addr;
8335 int ret;
8336
8337 /* if we want to turn off the cursor ignore width and height */
8338 if (!obj) {
8339 DRM_DEBUG_KMS("cursor off\n");
8340 addr = 0;
8341 mutex_lock(&dev->struct_mutex);
8342 goto finish;
8343 }
8344
8345 /* Check for which cursor types we support */
8346 if (!cursor_size_ok(dev, width, height)) {
8347 DRM_DEBUG("Cursor dimension not supported\n");
8348 return -EINVAL;
8349 }
8350
8351 stride = roundup_pow_of_two(width) * 4;
8352 if (obj->base.size < stride * height) {
8353 DRM_DEBUG_KMS("buffer is too small\n");
8354 ret = -ENOMEM;
8355 goto fail;
8356 }
8357
8358 /* we only need to pin inside GTT if cursor is non-phy */
8359 mutex_lock(&dev->struct_mutex);
8360 if (!INTEL_INFO(dev)->cursor_needs_physical) {
8361 unsigned alignment;
8362
8363 if (obj->tiling_mode) {
8364 DRM_DEBUG_KMS("cursor cannot be tiled\n");
8365 ret = -EINVAL;
8366 goto fail_locked;
8367 }
8368
8369 /* Note that the w/a also requires 2 PTE of padding following
8370 * the bo. We currently fill all unused PTE with the shadow
8371 * page and so we should always have valid PTE following the
8372 * cursor preventing the VT-d warning.
8373 */
8374 alignment = 0;
8375 if (need_vtd_wa(dev))
8376 alignment = 64*1024;
8377
8378 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8379 if (ret) {
8380 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8381 goto fail_locked;
8382 }
8383
8384 ret = i915_gem_object_put_fence(obj);
8385 if (ret) {
8386 DRM_DEBUG_KMS("failed to release fence for cursor");
8387 goto fail_unpin;
8388 }
8389
8390 addr = i915_gem_obj_ggtt_offset(obj);
8391 } else {
8392 int align = IS_I830(dev) ? 16 * 1024 : 256;
8393 ret = i915_gem_object_attach_phys(obj, align);
8394 if (ret) {
8395 DRM_DEBUG_KMS("failed to attach phys object\n");
8396 goto fail_locked;
8397 }
8398 addr = obj->phys_handle->busaddr;
8399 }
8400
8401 finish:
8402 if (intel_crtc->cursor_bo) {
8403 if (!INTEL_INFO(dev)->cursor_needs_physical)
8404 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8405 }
8406
8407 i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8408 INTEL_FRONTBUFFER_CURSOR(pipe));
8409 mutex_unlock(&dev->struct_mutex);
8410
8411 old_width = intel_crtc->cursor_width;
8412
8413 intel_crtc->cursor_addr = addr;
8414 intel_crtc->cursor_bo = obj;
8415 intel_crtc->cursor_width = width;
8416 intel_crtc->cursor_height = height;
8417
8418 if (intel_crtc->active) {
8419 if (old_width != width)
8420 intel_update_watermarks(crtc);
8421 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8422 }
8423
8424 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8425
8426 return 0;
8427 fail_unpin:
8428 i915_gem_object_unpin_from_display_plane(obj);
8429 fail_locked:
8430 mutex_unlock(&dev->struct_mutex);
8431 fail:
8432 drm_gem_object_unreference_unlocked(&obj->base);
8433 return ret;
8434 }
8435
8436 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8437 u16 *blue, uint32_t start, uint32_t size)
8438 {
8439 int end = (start + size > 256) ? 256 : start + size, i;
8440 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8441
8442 for (i = start; i < end; i++) {
8443 intel_crtc->lut_r[i] = red[i] >> 8;
8444 intel_crtc->lut_g[i] = green[i] >> 8;
8445 intel_crtc->lut_b[i] = blue[i] >> 8;
8446 }
8447
8448 intel_crtc_load_lut(crtc);
8449 }
8450
8451 /* VESA 640x480x72Hz mode to set on the pipe */
8452 static struct drm_display_mode load_detect_mode = {
8453 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8454 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8455 };
8456
8457 struct drm_framebuffer *
8458 __intel_framebuffer_create(struct drm_device *dev,
8459 struct drm_mode_fb_cmd2 *mode_cmd,
8460 struct drm_i915_gem_object *obj)
8461 {
8462 struct intel_framebuffer *intel_fb;
8463 int ret;
8464
8465 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8466 if (!intel_fb) {
8467 drm_gem_object_unreference_unlocked(&obj->base);
8468 return ERR_PTR(-ENOMEM);
8469 }
8470
8471 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8472 if (ret)
8473 goto err;
8474
8475 return &intel_fb->base;
8476 err:
8477 drm_gem_object_unreference_unlocked(&obj->base);
8478 kfree(intel_fb);
8479
8480 return ERR_PTR(ret);
8481 }
8482
8483 static struct drm_framebuffer *
8484 intel_framebuffer_create(struct drm_device *dev,
8485 struct drm_mode_fb_cmd2 *mode_cmd,
8486 struct drm_i915_gem_object *obj)
8487 {
8488 struct drm_framebuffer *fb;
8489 int ret;
8490
8491 ret = i915_mutex_lock_interruptible(dev);
8492 if (ret)
8493 return ERR_PTR(ret);
8494 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8495 mutex_unlock(&dev->struct_mutex);
8496
8497 return fb;
8498 }
8499
8500 static u32
8501 intel_framebuffer_pitch_for_width(int width, int bpp)
8502 {
8503 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8504 return ALIGN(pitch, 64);
8505 }
8506
8507 static u32
8508 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8509 {
8510 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8511 return PAGE_ALIGN(pitch * mode->vdisplay);
8512 }
8513
8514 static struct drm_framebuffer *
8515 intel_framebuffer_create_for_mode(struct drm_device *dev,
8516 struct drm_display_mode *mode,
8517 int depth, int bpp)
8518 {
8519 struct drm_i915_gem_object *obj;
8520 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8521
8522 obj = i915_gem_alloc_object(dev,
8523 intel_framebuffer_size_for_mode(mode, bpp));
8524 if (obj == NULL)
8525 return ERR_PTR(-ENOMEM);
8526
8527 mode_cmd.width = mode->hdisplay;
8528 mode_cmd.height = mode->vdisplay;
8529 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8530 bpp);
8531 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8532
8533 return intel_framebuffer_create(dev, &mode_cmd, obj);
8534 }
8535
8536 static struct drm_framebuffer *
8537 mode_fits_in_fbdev(struct drm_device *dev,
8538 struct drm_display_mode *mode)
8539 {
8540 #ifdef CONFIG_DRM_I915_FBDEV
8541 struct drm_i915_private *dev_priv = dev->dev_private;
8542 struct drm_i915_gem_object *obj;
8543 struct drm_framebuffer *fb;
8544
8545 if (!dev_priv->fbdev)
8546 return NULL;
8547
8548 if (!dev_priv->fbdev->fb)
8549 return NULL;
8550
8551 obj = dev_priv->fbdev->fb->obj;
8552 BUG_ON(!obj);
8553
8554 fb = &dev_priv->fbdev->fb->base;
8555 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8556 fb->bits_per_pixel))
8557 return NULL;
8558
8559 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8560 return NULL;
8561
8562 return fb;
8563 #else
8564 return NULL;
8565 #endif
8566 }
8567
8568 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8569 struct drm_display_mode *mode,
8570 struct intel_load_detect_pipe *old,
8571 struct drm_modeset_acquire_ctx *ctx)
8572 {
8573 struct intel_crtc *intel_crtc;
8574 struct intel_encoder *intel_encoder =
8575 intel_attached_encoder(connector);
8576 struct drm_crtc *possible_crtc;
8577 struct drm_encoder *encoder = &intel_encoder->base;
8578 struct drm_crtc *crtc = NULL;
8579 struct drm_device *dev = encoder->dev;
8580 struct drm_framebuffer *fb;
8581 struct drm_mode_config *config = &dev->mode_config;
8582 int ret, i = -1;
8583
8584 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8585 connector->base.id, connector->name,
8586 encoder->base.id, encoder->name);
8587
8588 retry:
8589 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8590 if (ret)
8591 goto fail_unlock;
8592
8593 /*
8594 * Algorithm gets a little messy:
8595 *
8596 * - if the connector already has an assigned crtc, use it (but make
8597 * sure it's on first)
8598 *
8599 * - try to find the first unused crtc that can drive this connector,
8600 * and use that if we find one
8601 */
8602
8603 /* See if we already have a CRTC for this connector */
8604 if (encoder->crtc) {
8605 crtc = encoder->crtc;
8606
8607 ret = drm_modeset_lock(&crtc->mutex, ctx);
8608 if (ret)
8609 goto fail_unlock;
8610
8611 old->dpms_mode = connector->dpms;
8612 old->load_detect_temp = false;
8613
8614 /* Make sure the crtc and connector are running */
8615 if (connector->dpms != DRM_MODE_DPMS_ON)
8616 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8617
8618 return true;
8619 }
8620
8621 /* Find an unused one (if possible) */
8622 for_each_crtc(dev, possible_crtc) {
8623 i++;
8624 if (!(encoder->possible_crtcs & (1 << i)))
8625 continue;
8626 if (possible_crtc->enabled)
8627 continue;
8628 /* This can occur when applying the pipe A quirk on resume. */
8629 if (to_intel_crtc(possible_crtc)->new_enabled)
8630 continue;
8631
8632 crtc = possible_crtc;
8633 break;
8634 }
8635
8636 /*
8637 * If we didn't find an unused CRTC, don't use any.
8638 */
8639 if (!crtc) {
8640 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8641 goto fail_unlock;
8642 }
8643
8644 ret = drm_modeset_lock(&crtc->mutex, ctx);
8645 if (ret)
8646 goto fail_unlock;
8647 intel_encoder->new_crtc = to_intel_crtc(crtc);
8648 to_intel_connector(connector)->new_encoder = intel_encoder;
8649
8650 intel_crtc = to_intel_crtc(crtc);
8651 intel_crtc->new_enabled = true;
8652 intel_crtc->new_config = &intel_crtc->config;
8653 old->dpms_mode = connector->dpms;
8654 old->load_detect_temp = true;
8655 old->release_fb = NULL;
8656
8657 if (!mode)
8658 mode = &load_detect_mode;
8659
8660 /* We need a framebuffer large enough to accommodate all accesses
8661 * that the plane may generate whilst we perform load detection.
8662 * We can not rely on the fbcon either being present (we get called
8663 * during its initialisation to detect all boot displays, or it may
8664 * not even exist) or that it is large enough to satisfy the
8665 * requested mode.
8666 */
8667 fb = mode_fits_in_fbdev(dev, mode);
8668 if (fb == NULL) {
8669 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8670 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8671 old->release_fb = fb;
8672 } else
8673 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8674 if (IS_ERR(fb)) {
8675 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8676 goto fail;
8677 }
8678
8679 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8680 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8681 if (old->release_fb)
8682 old->release_fb->funcs->destroy(old->release_fb);
8683 goto fail;
8684 }
8685
8686 /* let the connector get through one full cycle before testing */
8687 intel_wait_for_vblank(dev, intel_crtc->pipe);
8688 return true;
8689
8690 fail:
8691 intel_crtc->new_enabled = crtc->enabled;
8692 if (intel_crtc->new_enabled)
8693 intel_crtc->new_config = &intel_crtc->config;
8694 else
8695 intel_crtc->new_config = NULL;
8696 fail_unlock:
8697 if (ret == -EDEADLK) {
8698 drm_modeset_backoff(ctx);
8699 goto retry;
8700 }
8701
8702 return false;
8703 }
8704
8705 void intel_release_load_detect_pipe(struct drm_connector *connector,
8706 struct intel_load_detect_pipe *old)
8707 {
8708 struct intel_encoder *intel_encoder =
8709 intel_attached_encoder(connector);
8710 struct drm_encoder *encoder = &intel_encoder->base;
8711 struct drm_crtc *crtc = encoder->crtc;
8712 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8713
8714 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8715 connector->base.id, connector->name,
8716 encoder->base.id, encoder->name);
8717
8718 if (old->load_detect_temp) {
8719 to_intel_connector(connector)->new_encoder = NULL;
8720 intel_encoder->new_crtc = NULL;
8721 intel_crtc->new_enabled = false;
8722 intel_crtc->new_config = NULL;
8723 intel_set_mode(crtc, NULL, 0, 0, NULL);
8724
8725 if (old->release_fb) {
8726 drm_framebuffer_unregister_private(old->release_fb);
8727 drm_framebuffer_unreference(old->release_fb);
8728 }
8729
8730 return;
8731 }
8732
8733 /* Switch crtc and encoder back off if necessary */
8734 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8735 connector->funcs->dpms(connector, old->dpms_mode);
8736 }
8737
8738 static int i9xx_pll_refclk(struct drm_device *dev,
8739 const struct intel_crtc_config *pipe_config)
8740 {
8741 struct drm_i915_private *dev_priv = dev->dev_private;
8742 u32 dpll = pipe_config->dpll_hw_state.dpll;
8743
8744 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8745 return dev_priv->vbt.lvds_ssc_freq;
8746 else if (HAS_PCH_SPLIT(dev))
8747 return 120000;
8748 else if (!IS_GEN2(dev))
8749 return 96000;
8750 else
8751 return 48000;
8752 }
8753
8754 /* Returns the clock of the currently programmed mode of the given pipe. */
8755 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8756 struct intel_crtc_config *pipe_config)
8757 {
8758 struct drm_device *dev = crtc->base.dev;
8759 struct drm_i915_private *dev_priv = dev->dev_private;
8760 int pipe = pipe_config->cpu_transcoder;
8761 u32 dpll = pipe_config->dpll_hw_state.dpll;
8762 u32 fp;
8763 intel_clock_t clock;
8764 int refclk = i9xx_pll_refclk(dev, pipe_config);
8765
8766 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8767 fp = pipe_config->dpll_hw_state.fp0;
8768 else
8769 fp = pipe_config->dpll_hw_state.fp1;
8770
8771 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8772 if (IS_PINEVIEW(dev)) {
8773 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8774 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8775 } else {
8776 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8777 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8778 }
8779
8780 if (!IS_GEN2(dev)) {
8781 if (IS_PINEVIEW(dev))
8782 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8783 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8784 else
8785 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8786 DPLL_FPA01_P1_POST_DIV_SHIFT);
8787
8788 switch (dpll & DPLL_MODE_MASK) {
8789 case DPLLB_MODE_DAC_SERIAL:
8790 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8791 5 : 10;
8792 break;
8793 case DPLLB_MODE_LVDS:
8794 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8795 7 : 14;
8796 break;
8797 default:
8798 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8799 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8800 return;
8801 }
8802
8803 if (IS_PINEVIEW(dev))
8804 pineview_clock(refclk, &clock);
8805 else
8806 i9xx_clock(refclk, &clock);
8807 } else {
8808 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8809 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8810
8811 if (is_lvds) {
8812 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8813 DPLL_FPA01_P1_POST_DIV_SHIFT);
8814
8815 if (lvds & LVDS_CLKB_POWER_UP)
8816 clock.p2 = 7;
8817 else
8818 clock.p2 = 14;
8819 } else {
8820 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8821 clock.p1 = 2;
8822 else {
8823 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8824 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8825 }
8826 if (dpll & PLL_P2_DIVIDE_BY_4)
8827 clock.p2 = 4;
8828 else
8829 clock.p2 = 2;
8830 }
8831
8832 i9xx_clock(refclk, &clock);
8833 }
8834
8835 /*
8836 * This value includes pixel_multiplier. We will use
8837 * port_clock to compute adjusted_mode.crtc_clock in the
8838 * encoder's get_config() function.
8839 */
8840 pipe_config->port_clock = clock.dot;
8841 }
8842
8843 int intel_dotclock_calculate(int link_freq,
8844 const struct intel_link_m_n *m_n)
8845 {
8846 /*
8847 * The calculation for the data clock is:
8848 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8849 * But we want to avoid losing precison if possible, so:
8850 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8851 *
8852 * and the link clock is simpler:
8853 * link_clock = (m * link_clock) / n
8854 */
8855
8856 if (!m_n->link_n)
8857 return 0;
8858
8859 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8860 }
8861
8862 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8863 struct intel_crtc_config *pipe_config)
8864 {
8865 struct drm_device *dev = crtc->base.dev;
8866
8867 /* read out port_clock from the DPLL */
8868 i9xx_crtc_clock_get(crtc, pipe_config);
8869
8870 /*
8871 * This value does not include pixel_multiplier.
8872 * We will check that port_clock and adjusted_mode.crtc_clock
8873 * agree once we know their relationship in the encoder's
8874 * get_config() function.
8875 */
8876 pipe_config->adjusted_mode.crtc_clock =
8877 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8878 &pipe_config->fdi_m_n);
8879 }
8880
8881 /** Returns the currently programmed mode of the given pipe. */
8882 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8883 struct drm_crtc *crtc)
8884 {
8885 struct drm_i915_private *dev_priv = dev->dev_private;
8886 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8887 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8888 struct drm_display_mode *mode;
8889 struct intel_crtc_config pipe_config;
8890 int htot = I915_READ(HTOTAL(cpu_transcoder));
8891 int hsync = I915_READ(HSYNC(cpu_transcoder));
8892 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8893 int vsync = I915_READ(VSYNC(cpu_transcoder));
8894 enum pipe pipe = intel_crtc->pipe;
8895
8896 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8897 if (!mode)
8898 return NULL;
8899
8900 /*
8901 * Construct a pipe_config sufficient for getting the clock info
8902 * back out of crtc_clock_get.
8903 *
8904 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8905 * to use a real value here instead.
8906 */
8907 pipe_config.cpu_transcoder = (enum transcoder) pipe;
8908 pipe_config.pixel_multiplier = 1;
8909 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8910 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8911 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8912 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8913
8914 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8915 mode->hdisplay = (htot & 0xffff) + 1;
8916 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8917 mode->hsync_start = (hsync & 0xffff) + 1;
8918 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8919 mode->vdisplay = (vtot & 0xffff) + 1;
8920 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8921 mode->vsync_start = (vsync & 0xffff) + 1;
8922 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8923
8924 drm_mode_set_name(mode);
8925
8926 return mode;
8927 }
8928
8929 static void intel_increase_pllclock(struct drm_device *dev,
8930 enum pipe pipe)
8931 {
8932 struct drm_i915_private *dev_priv = dev->dev_private;
8933 int dpll_reg = DPLL(pipe);
8934 int dpll;
8935
8936 if (!HAS_GMCH_DISPLAY(dev))
8937 return;
8938
8939 if (!dev_priv->lvds_downclock_avail)
8940 return;
8941
8942 dpll = I915_READ(dpll_reg);
8943 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8944 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8945
8946 assert_panel_unlocked(dev_priv, pipe);
8947
8948 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8949 I915_WRITE(dpll_reg, dpll);
8950 intel_wait_for_vblank(dev, pipe);
8951
8952 dpll = I915_READ(dpll_reg);
8953 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8954 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8955 }
8956 }
8957
8958 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8959 {
8960 struct drm_device *dev = crtc->dev;
8961 struct drm_i915_private *dev_priv = dev->dev_private;
8962 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8963
8964 if (!HAS_GMCH_DISPLAY(dev))
8965 return;
8966
8967 if (!dev_priv->lvds_downclock_avail)
8968 return;
8969
8970 /*
8971 * Since this is called by a timer, we should never get here in
8972 * the manual case.
8973 */
8974 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8975 int pipe = intel_crtc->pipe;
8976 int dpll_reg = DPLL(pipe);
8977 int dpll;
8978
8979 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8980
8981 assert_panel_unlocked(dev_priv, pipe);
8982
8983 dpll = I915_READ(dpll_reg);
8984 dpll |= DISPLAY_RATE_SELECT_FPA1;
8985 I915_WRITE(dpll_reg, dpll);
8986 intel_wait_for_vblank(dev, pipe);
8987 dpll = I915_READ(dpll_reg);
8988 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8989 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8990 }
8991
8992 }
8993
8994 void intel_mark_busy(struct drm_device *dev)
8995 {
8996 struct drm_i915_private *dev_priv = dev->dev_private;
8997
8998 if (dev_priv->mm.busy)
8999 return;
9000
9001 intel_runtime_pm_get(dev_priv);
9002 i915_update_gfx_val(dev_priv);
9003 dev_priv->mm.busy = true;
9004 }
9005
9006 void intel_mark_idle(struct drm_device *dev)
9007 {
9008 struct drm_i915_private *dev_priv = dev->dev_private;
9009 struct drm_crtc *crtc;
9010
9011 if (!dev_priv->mm.busy)
9012 return;
9013
9014 dev_priv->mm.busy = false;
9015
9016 if (!i915.powersave)
9017 goto out;
9018
9019 for_each_crtc(dev, crtc) {
9020 if (!crtc->primary->fb)
9021 continue;
9022
9023 intel_decrease_pllclock(crtc);
9024 }
9025
9026 if (INTEL_INFO(dev)->gen >= 6)
9027 gen6_rps_idle(dev->dev_private);
9028
9029 out:
9030 intel_runtime_pm_put(dev_priv);
9031 }
9032
9033
9034 /**
9035 * intel_mark_fb_busy - mark given planes as busy
9036 * @dev: DRM device
9037 * @frontbuffer_bits: bits for the affected planes
9038 * @ring: optional ring for asynchronous commands
9039 *
9040 * This function gets called every time the screen contents change. It can be
9041 * used to keep e.g. the update rate at the nominal refresh rate with DRRS.
9042 */
9043 static void intel_mark_fb_busy(struct drm_device *dev,
9044 unsigned frontbuffer_bits,
9045 struct intel_engine_cs *ring)
9046 {
9047 struct drm_i915_private *dev_priv = dev->dev_private;
9048 enum pipe pipe;
9049
9050 if (!i915.powersave)
9051 return;
9052
9053 for_each_pipe(dev_priv, pipe) {
9054 if (!(frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe)))
9055 continue;
9056
9057 intel_increase_pllclock(dev, pipe);
9058 if (ring && intel_fbc_enabled(dev))
9059 ring->fbc_dirty = true;
9060 }
9061 }
9062
9063 /**
9064 * intel_fb_obj_invalidate - invalidate frontbuffer object
9065 * @obj: GEM object to invalidate
9066 * @ring: set for asynchronous rendering
9067 *
9068 * This function gets called every time rendering on the given object starts and
9069 * frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must
9070 * be invalidated. If @ring is non-NULL any subsequent invalidation will be delayed
9071 * until the rendering completes or a flip on this frontbuffer plane is
9072 * scheduled.
9073 */
9074 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
9075 struct intel_engine_cs *ring)
9076 {
9077 struct drm_device *dev = obj->base.dev;
9078 struct drm_i915_private *dev_priv = dev->dev_private;
9079
9080 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
9081
9082 if (!obj->frontbuffer_bits)
9083 return;
9084
9085 if (ring) {
9086 mutex_lock(&dev_priv->fb_tracking.lock);
9087 dev_priv->fb_tracking.busy_bits
9088 |= obj->frontbuffer_bits;
9089 dev_priv->fb_tracking.flip_bits
9090 &= ~obj->frontbuffer_bits;
9091 mutex_unlock(&dev_priv->fb_tracking.lock);
9092 }
9093
9094 intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring);
9095
9096 intel_edp_psr_invalidate(dev, obj->frontbuffer_bits);
9097 }
9098
9099 /**
9100 * intel_frontbuffer_flush - flush frontbuffer
9101 * @dev: DRM device
9102 * @frontbuffer_bits: frontbuffer plane tracking bits
9103 *
9104 * This function gets called every time rendering on the given planes has
9105 * completed and frontbuffer caching can be started again. Flushes will get
9106 * delayed if they're blocked by some oustanding asynchronous rendering.
9107 *
9108 * Can be called without any locks held.
9109 */
9110 void intel_frontbuffer_flush(struct drm_device *dev,
9111 unsigned frontbuffer_bits)
9112 {
9113 struct drm_i915_private *dev_priv = dev->dev_private;
9114
9115 /* Delay flushing when rings are still busy.*/
9116 mutex_lock(&dev_priv->fb_tracking.lock);
9117 frontbuffer_bits &= ~dev_priv->fb_tracking.busy_bits;
9118 mutex_unlock(&dev_priv->fb_tracking.lock);
9119
9120 intel_mark_fb_busy(dev, frontbuffer_bits, NULL);
9121
9122 intel_edp_psr_flush(dev, frontbuffer_bits);
9123
9124 /*
9125 * FIXME: Unconditional fbc flushing here is a rather gross hack and
9126 * needs to be reworked into a proper frontbuffer tracking scheme like
9127 * psr employs.
9128 */
9129 if (IS_BROADWELL(dev))
9130 gen8_fbc_sw_flush(dev, FBC_REND_CACHE_CLEAN);
9131 }
9132
9133 /**
9134 * intel_fb_obj_flush - flush frontbuffer object
9135 * @obj: GEM object to flush
9136 * @retire: set when retiring asynchronous rendering
9137 *
9138 * This function gets called every time rendering on the given object has
9139 * completed and frontbuffer caching can be started again. If @retire is true
9140 * then any delayed flushes will be unblocked.
9141 */
9142 void intel_fb_obj_flush(struct drm_i915_gem_object *obj,
9143 bool retire)
9144 {
9145 struct drm_device *dev = obj->base.dev;
9146 struct drm_i915_private *dev_priv = dev->dev_private;
9147 unsigned frontbuffer_bits;
9148
9149 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
9150
9151 if (!obj->frontbuffer_bits)
9152 return;
9153
9154 frontbuffer_bits = obj->frontbuffer_bits;
9155
9156 if (retire) {
9157 mutex_lock(&dev_priv->fb_tracking.lock);
9158 /* Filter out new bits since rendering started. */
9159 frontbuffer_bits &= dev_priv->fb_tracking.busy_bits;
9160
9161 dev_priv->fb_tracking.busy_bits &= ~frontbuffer_bits;
9162 mutex_unlock(&dev_priv->fb_tracking.lock);
9163 }
9164
9165 intel_frontbuffer_flush(dev, frontbuffer_bits);
9166 }
9167
9168 /**
9169 * intel_frontbuffer_flip_prepare - prepare asnychronous frontbuffer flip
9170 * @dev: DRM device
9171 * @frontbuffer_bits: frontbuffer plane tracking bits
9172 *
9173 * This function gets called after scheduling a flip on @obj. The actual
9174 * frontbuffer flushing will be delayed until completion is signalled with
9175 * intel_frontbuffer_flip_complete. If an invalidate happens in between this
9176 * flush will be cancelled.
9177 *
9178 * Can be called without any locks held.
9179 */
9180 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
9181 unsigned frontbuffer_bits)
9182 {
9183 struct drm_i915_private *dev_priv = dev->dev_private;
9184
9185 mutex_lock(&dev_priv->fb_tracking.lock);
9186 dev_priv->fb_tracking.flip_bits
9187 |= frontbuffer_bits;
9188 mutex_unlock(&dev_priv->fb_tracking.lock);
9189 }
9190
9191 /**
9192 * intel_frontbuffer_flip_complete - complete asynchronous frontbuffer flush
9193 * @dev: DRM device
9194 * @frontbuffer_bits: frontbuffer plane tracking bits
9195 *
9196 * This function gets called after the flip has been latched and will complete
9197 * on the next vblank. It will execute the fush if it hasn't been cancalled yet.
9198 *
9199 * Can be called without any locks held.
9200 */
9201 void intel_frontbuffer_flip_complete(struct drm_device *dev,
9202 unsigned frontbuffer_bits)
9203 {
9204 struct drm_i915_private *dev_priv = dev->dev_private;
9205
9206 mutex_lock(&dev_priv->fb_tracking.lock);
9207 /* Mask any cancelled flips. */
9208 frontbuffer_bits &= dev_priv->fb_tracking.flip_bits;
9209 dev_priv->fb_tracking.flip_bits &= ~frontbuffer_bits;
9210 mutex_unlock(&dev_priv->fb_tracking.lock);
9211
9212 intel_frontbuffer_flush(dev, frontbuffer_bits);
9213 }
9214
9215 static void intel_crtc_destroy(struct drm_crtc *crtc)
9216 {
9217 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9218 struct drm_device *dev = crtc->dev;
9219 struct intel_unpin_work *work;
9220 unsigned long flags;
9221
9222 spin_lock_irqsave(&dev->event_lock, flags);
9223 work = intel_crtc->unpin_work;
9224 intel_crtc->unpin_work = NULL;
9225 spin_unlock_irqrestore(&dev->event_lock, flags);
9226
9227 if (work) {
9228 cancel_work_sync(&work->work);
9229 kfree(work);
9230 }
9231
9232 drm_crtc_cleanup(crtc);
9233
9234 kfree(intel_crtc);
9235 }
9236
9237 static void intel_unpin_work_fn(struct work_struct *__work)
9238 {
9239 struct intel_unpin_work *work =
9240 container_of(__work, struct intel_unpin_work, work);
9241 struct drm_device *dev = work->crtc->dev;
9242 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9243
9244 mutex_lock(&dev->struct_mutex);
9245 intel_unpin_fb_obj(work->old_fb_obj);
9246 drm_gem_object_unreference(&work->pending_flip_obj->base);
9247 drm_gem_object_unreference(&work->old_fb_obj->base);
9248
9249 intel_update_fbc(dev);
9250 mutex_unlock(&dev->struct_mutex);
9251
9252 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9253
9254 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9255 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9256
9257 kfree(work);
9258 }
9259
9260 static void do_intel_finish_page_flip(struct drm_device *dev,
9261 struct drm_crtc *crtc)
9262 {
9263 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9264 struct intel_unpin_work *work;
9265 unsigned long flags;
9266
9267 /* Ignore early vblank irqs */
9268 if (intel_crtc == NULL)
9269 return;
9270
9271 spin_lock_irqsave(&dev->event_lock, flags);
9272 work = intel_crtc->unpin_work;
9273
9274 /* Ensure we don't miss a work->pending update ... */
9275 smp_rmb();
9276
9277 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9278 spin_unlock_irqrestore(&dev->event_lock, flags);
9279 return;
9280 }
9281
9282 page_flip_completed(intel_crtc);
9283
9284 spin_unlock_irqrestore(&dev->event_lock, flags);
9285 }
9286
9287 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9288 {
9289 struct drm_i915_private *dev_priv = dev->dev_private;
9290 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9291
9292 do_intel_finish_page_flip(dev, crtc);
9293 }
9294
9295 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9296 {
9297 struct drm_i915_private *dev_priv = dev->dev_private;
9298 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9299
9300 do_intel_finish_page_flip(dev, crtc);
9301 }
9302
9303 /* Is 'a' after or equal to 'b'? */
9304 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9305 {
9306 return !((a - b) & 0x80000000);
9307 }
9308
9309 static bool page_flip_finished(struct intel_crtc *crtc)
9310 {
9311 struct drm_device *dev = crtc->base.dev;
9312 struct drm_i915_private *dev_priv = dev->dev_private;
9313
9314 /*
9315 * The relevant registers doen't exist on pre-ctg.
9316 * As the flip done interrupt doesn't trigger for mmio
9317 * flips on gmch platforms, a flip count check isn't
9318 * really needed there. But since ctg has the registers,
9319 * include it in the check anyway.
9320 */
9321 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9322 return true;
9323
9324 /*
9325 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9326 * used the same base address. In that case the mmio flip might
9327 * have completed, but the CS hasn't even executed the flip yet.
9328 *
9329 * A flip count check isn't enough as the CS might have updated
9330 * the base address just after start of vblank, but before we
9331 * managed to process the interrupt. This means we'd complete the
9332 * CS flip too soon.
9333 *
9334 * Combining both checks should get us a good enough result. It may
9335 * still happen that the CS flip has been executed, but has not
9336 * yet actually completed. But in case the base address is the same
9337 * anyway, we don't really care.
9338 */
9339 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9340 crtc->unpin_work->gtt_offset &&
9341 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9342 crtc->unpin_work->flip_count);
9343 }
9344
9345 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9346 {
9347 struct drm_i915_private *dev_priv = dev->dev_private;
9348 struct intel_crtc *intel_crtc =
9349 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9350 unsigned long flags;
9351
9352 /* NB: An MMIO update of the plane base pointer will also
9353 * generate a page-flip completion irq, i.e. every modeset
9354 * is also accompanied by a spurious intel_prepare_page_flip().
9355 */
9356 spin_lock_irqsave(&dev->event_lock, flags);
9357 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9358 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9359 spin_unlock_irqrestore(&dev->event_lock, flags);
9360 }
9361
9362 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9363 {
9364 /* Ensure that the work item is consistent when activating it ... */
9365 smp_wmb();
9366 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9367 /* and that it is marked active as soon as the irq could fire. */
9368 smp_wmb();
9369 }
9370
9371 static int intel_gen2_queue_flip(struct drm_device *dev,
9372 struct drm_crtc *crtc,
9373 struct drm_framebuffer *fb,
9374 struct drm_i915_gem_object *obj,
9375 struct intel_engine_cs *ring,
9376 uint32_t flags)
9377 {
9378 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9379 u32 flip_mask;
9380 int ret;
9381
9382 ret = intel_ring_begin(ring, 6);
9383 if (ret)
9384 return ret;
9385
9386 /* Can't queue multiple flips, so wait for the previous
9387 * one to finish before executing the next.
9388 */
9389 if (intel_crtc->plane)
9390 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9391 else
9392 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9393 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9394 intel_ring_emit(ring, MI_NOOP);
9395 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9396 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9397 intel_ring_emit(ring, fb->pitches[0]);
9398 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9399 intel_ring_emit(ring, 0); /* aux display base address, unused */
9400
9401 intel_mark_page_flip_active(intel_crtc);
9402 __intel_ring_advance(ring);
9403 return 0;
9404 }
9405
9406 static int intel_gen3_queue_flip(struct drm_device *dev,
9407 struct drm_crtc *crtc,
9408 struct drm_framebuffer *fb,
9409 struct drm_i915_gem_object *obj,
9410 struct intel_engine_cs *ring,
9411 uint32_t flags)
9412 {
9413 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9414 u32 flip_mask;
9415 int ret;
9416
9417 ret = intel_ring_begin(ring, 6);
9418 if (ret)
9419 return ret;
9420
9421 if (intel_crtc->plane)
9422 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9423 else
9424 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9425 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9426 intel_ring_emit(ring, MI_NOOP);
9427 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9428 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9429 intel_ring_emit(ring, fb->pitches[0]);
9430 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9431 intel_ring_emit(ring, MI_NOOP);
9432
9433 intel_mark_page_flip_active(intel_crtc);
9434 __intel_ring_advance(ring);
9435 return 0;
9436 }
9437
9438 static int intel_gen4_queue_flip(struct drm_device *dev,
9439 struct drm_crtc *crtc,
9440 struct drm_framebuffer *fb,
9441 struct drm_i915_gem_object *obj,
9442 struct intel_engine_cs *ring,
9443 uint32_t flags)
9444 {
9445 struct drm_i915_private *dev_priv = dev->dev_private;
9446 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9447 uint32_t pf, pipesrc;
9448 int ret;
9449
9450 ret = intel_ring_begin(ring, 4);
9451 if (ret)
9452 return ret;
9453
9454 /* i965+ uses the linear or tiled offsets from the
9455 * Display Registers (which do not change across a page-flip)
9456 * so we need only reprogram the base address.
9457 */
9458 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9459 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9460 intel_ring_emit(ring, fb->pitches[0]);
9461 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9462 obj->tiling_mode);
9463
9464 /* XXX Enabling the panel-fitter across page-flip is so far
9465 * untested on non-native modes, so ignore it for now.
9466 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9467 */
9468 pf = 0;
9469 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9470 intel_ring_emit(ring, pf | pipesrc);
9471
9472 intel_mark_page_flip_active(intel_crtc);
9473 __intel_ring_advance(ring);
9474 return 0;
9475 }
9476
9477 static int intel_gen6_queue_flip(struct drm_device *dev,
9478 struct drm_crtc *crtc,
9479 struct drm_framebuffer *fb,
9480 struct drm_i915_gem_object *obj,
9481 struct intel_engine_cs *ring,
9482 uint32_t flags)
9483 {
9484 struct drm_i915_private *dev_priv = dev->dev_private;
9485 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9486 uint32_t pf, pipesrc;
9487 int ret;
9488
9489 ret = intel_ring_begin(ring, 4);
9490 if (ret)
9491 return ret;
9492
9493 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9494 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9495 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9496 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9497
9498 /* Contrary to the suggestions in the documentation,
9499 * "Enable Panel Fitter" does not seem to be required when page
9500 * flipping with a non-native mode, and worse causes a normal
9501 * modeset to fail.
9502 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9503 */
9504 pf = 0;
9505 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9506 intel_ring_emit(ring, pf | pipesrc);
9507
9508 intel_mark_page_flip_active(intel_crtc);
9509 __intel_ring_advance(ring);
9510 return 0;
9511 }
9512
9513 static int intel_gen7_queue_flip(struct drm_device *dev,
9514 struct drm_crtc *crtc,
9515 struct drm_framebuffer *fb,
9516 struct drm_i915_gem_object *obj,
9517 struct intel_engine_cs *ring,
9518 uint32_t flags)
9519 {
9520 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9521 uint32_t plane_bit = 0;
9522 int len, ret;
9523
9524 switch (intel_crtc->plane) {
9525 case PLANE_A:
9526 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9527 break;
9528 case PLANE_B:
9529 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9530 break;
9531 case PLANE_C:
9532 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9533 break;
9534 default:
9535 WARN_ONCE(1, "unknown plane in flip command\n");
9536 return -ENODEV;
9537 }
9538
9539 len = 4;
9540 if (ring->id == RCS) {
9541 len += 6;
9542 /*
9543 * On Gen 8, SRM is now taking an extra dword to accommodate
9544 * 48bits addresses, and we need a NOOP for the batch size to
9545 * stay even.
9546 */
9547 if (IS_GEN8(dev))
9548 len += 2;
9549 }
9550
9551 /*
9552 * BSpec MI_DISPLAY_FLIP for IVB:
9553 * "The full packet must be contained within the same cache line."
9554 *
9555 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9556 * cacheline, if we ever start emitting more commands before
9557 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9558 * then do the cacheline alignment, and finally emit the
9559 * MI_DISPLAY_FLIP.
9560 */
9561 ret = intel_ring_cacheline_align(ring);
9562 if (ret)
9563 return ret;
9564
9565 ret = intel_ring_begin(ring, len);
9566 if (ret)
9567 return ret;
9568
9569 /* Unmask the flip-done completion message. Note that the bspec says that
9570 * we should do this for both the BCS and RCS, and that we must not unmask
9571 * more than one flip event at any time (or ensure that one flip message
9572 * can be sent by waiting for flip-done prior to queueing new flips).
9573 * Experimentation says that BCS works despite DERRMR masking all
9574 * flip-done completion events and that unmasking all planes at once
9575 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9576 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9577 */
9578 if (ring->id == RCS) {
9579 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9580 intel_ring_emit(ring, DERRMR);
9581 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9582 DERRMR_PIPEB_PRI_FLIP_DONE |
9583 DERRMR_PIPEC_PRI_FLIP_DONE));
9584 if (IS_GEN8(dev))
9585 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9586 MI_SRM_LRM_GLOBAL_GTT);
9587 else
9588 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9589 MI_SRM_LRM_GLOBAL_GTT);
9590 intel_ring_emit(ring, DERRMR);
9591 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9592 if (IS_GEN8(dev)) {
9593 intel_ring_emit(ring, 0);
9594 intel_ring_emit(ring, MI_NOOP);
9595 }
9596 }
9597
9598 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9599 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9600 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9601 intel_ring_emit(ring, (MI_NOOP));
9602
9603 intel_mark_page_flip_active(intel_crtc);
9604 __intel_ring_advance(ring);
9605 return 0;
9606 }
9607
9608 static bool use_mmio_flip(struct intel_engine_cs *ring,
9609 struct drm_i915_gem_object *obj)
9610 {
9611 /*
9612 * This is not being used for older platforms, because
9613 * non-availability of flip done interrupt forces us to use
9614 * CS flips. Older platforms derive flip done using some clever
9615 * tricks involving the flip_pending status bits and vblank irqs.
9616 * So using MMIO flips there would disrupt this mechanism.
9617 */
9618
9619 if (ring == NULL)
9620 return true;
9621
9622 if (INTEL_INFO(ring->dev)->gen < 5)
9623 return false;
9624
9625 if (i915.use_mmio_flip < 0)
9626 return false;
9627 else if (i915.use_mmio_flip > 0)
9628 return true;
9629 else if (i915.enable_execlists)
9630 return true;
9631 else
9632 return ring != obj->ring;
9633 }
9634
9635 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9636 {
9637 struct drm_device *dev = intel_crtc->base.dev;
9638 struct drm_i915_private *dev_priv = dev->dev_private;
9639 struct intel_framebuffer *intel_fb =
9640 to_intel_framebuffer(intel_crtc->base.primary->fb);
9641 struct drm_i915_gem_object *obj = intel_fb->obj;
9642 u32 dspcntr;
9643 u32 reg;
9644
9645 intel_mark_page_flip_active(intel_crtc);
9646
9647 reg = DSPCNTR(intel_crtc->plane);
9648 dspcntr = I915_READ(reg);
9649
9650 if (INTEL_INFO(dev)->gen >= 4) {
9651 if (obj->tiling_mode != I915_TILING_NONE)
9652 dspcntr |= DISPPLANE_TILED;
9653 else
9654 dspcntr &= ~DISPPLANE_TILED;
9655 }
9656 I915_WRITE(reg, dspcntr);
9657
9658 I915_WRITE(DSPSURF(intel_crtc->plane),
9659 intel_crtc->unpin_work->gtt_offset);
9660 POSTING_READ(DSPSURF(intel_crtc->plane));
9661 }
9662
9663 static int intel_postpone_flip(struct drm_i915_gem_object *obj)
9664 {
9665 struct intel_engine_cs *ring;
9666 int ret;
9667
9668 lockdep_assert_held(&obj->base.dev->struct_mutex);
9669
9670 if (!obj->last_write_seqno)
9671 return 0;
9672
9673 ring = obj->ring;
9674
9675 if (i915_seqno_passed(ring->get_seqno(ring, true),
9676 obj->last_write_seqno))
9677 return 0;
9678
9679 ret = i915_gem_check_olr(ring, obj->last_write_seqno);
9680 if (ret)
9681 return ret;
9682
9683 if (WARN_ON(!ring->irq_get(ring)))
9684 return 0;
9685
9686 return 1;
9687 }
9688
9689 void intel_notify_mmio_flip(struct intel_engine_cs *ring)
9690 {
9691 struct drm_i915_private *dev_priv = to_i915(ring->dev);
9692 struct intel_crtc *intel_crtc;
9693 unsigned long irq_flags;
9694 u32 seqno;
9695
9696 seqno = ring->get_seqno(ring, false);
9697
9698 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9699 for_each_intel_crtc(ring->dev, intel_crtc) {
9700 struct intel_mmio_flip *mmio_flip;
9701
9702 mmio_flip = &intel_crtc->mmio_flip;
9703 if (mmio_flip->seqno == 0)
9704 continue;
9705
9706 if (ring->id != mmio_flip->ring_id)
9707 continue;
9708
9709 if (i915_seqno_passed(seqno, mmio_flip->seqno)) {
9710 intel_do_mmio_flip(intel_crtc);
9711 mmio_flip->seqno = 0;
9712 ring->irq_put(ring);
9713 }
9714 }
9715 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9716 }
9717
9718 static int intel_queue_mmio_flip(struct drm_device *dev,
9719 struct drm_crtc *crtc,
9720 struct drm_framebuffer *fb,
9721 struct drm_i915_gem_object *obj,
9722 struct intel_engine_cs *ring,
9723 uint32_t flags)
9724 {
9725 struct drm_i915_private *dev_priv = dev->dev_private;
9726 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9727 unsigned long irq_flags;
9728 int ret;
9729
9730 if (WARN_ON(intel_crtc->mmio_flip.seqno))
9731 return -EBUSY;
9732
9733 ret = intel_postpone_flip(obj);
9734 if (ret < 0)
9735 return ret;
9736 if (ret == 0) {
9737 intel_do_mmio_flip(intel_crtc);
9738 return 0;
9739 }
9740
9741 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9742 intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9743 intel_crtc->mmio_flip.ring_id = obj->ring->id;
9744 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9745
9746 /*
9747 * Double check to catch cases where irq fired before
9748 * mmio flip data was ready
9749 */
9750 intel_notify_mmio_flip(obj->ring);
9751 return 0;
9752 }
9753
9754 static int intel_default_queue_flip(struct drm_device *dev,
9755 struct drm_crtc *crtc,
9756 struct drm_framebuffer *fb,
9757 struct drm_i915_gem_object *obj,
9758 struct intel_engine_cs *ring,
9759 uint32_t flags)
9760 {
9761 return -ENODEV;
9762 }
9763
9764 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9765 struct drm_crtc *crtc)
9766 {
9767 struct drm_i915_private *dev_priv = dev->dev_private;
9768 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9769 struct intel_unpin_work *work = intel_crtc->unpin_work;
9770 u32 addr;
9771
9772 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9773 return true;
9774
9775 if (!work->enable_stall_check)
9776 return false;
9777
9778 if (work->flip_ready_vblank == 0) {
9779 if (work->flip_queued_ring &&
9780 !i915_seqno_passed(work->flip_queued_ring->get_seqno(work->flip_queued_ring, true),
9781 work->flip_queued_seqno))
9782 return false;
9783
9784 work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9785 }
9786
9787 if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3)
9788 return false;
9789
9790 /* Potential stall - if we see that the flip has happened,
9791 * assume a missed interrupt. */
9792 if (INTEL_INFO(dev)->gen >= 4)
9793 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9794 else
9795 addr = I915_READ(DSPADDR(intel_crtc->plane));
9796
9797 /* There is a potential issue here with a false positive after a flip
9798 * to the same address. We could address this by checking for a
9799 * non-incrementing frame counter.
9800 */
9801 return addr == work->gtt_offset;
9802 }
9803
9804 void intel_check_page_flip(struct drm_device *dev, int pipe)
9805 {
9806 struct drm_i915_private *dev_priv = dev->dev_private;
9807 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9808 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9809 unsigned long flags;
9810
9811 if (crtc == NULL)
9812 return;
9813
9814 spin_lock_irqsave(&dev->event_lock, flags);
9815 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9816 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9817 intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe));
9818 page_flip_completed(intel_crtc);
9819 }
9820 spin_unlock_irqrestore(&dev->event_lock, flags);
9821 }
9822
9823 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9824 struct drm_framebuffer *fb,
9825 struct drm_pending_vblank_event *event,
9826 uint32_t page_flip_flags)
9827 {
9828 struct drm_device *dev = crtc->dev;
9829 struct drm_i915_private *dev_priv = dev->dev_private;
9830 struct drm_framebuffer *old_fb = crtc->primary->fb;
9831 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9832 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9833 enum pipe pipe = intel_crtc->pipe;
9834 struct intel_unpin_work *work;
9835 struct intel_engine_cs *ring;
9836 unsigned long flags;
9837 int ret;
9838
9839 //trigger software GT busyness calculation
9840 gen8_flip_interrupt(dev);
9841
9842 /*
9843 * drm_mode_page_flip_ioctl() should already catch this, but double
9844 * check to be safe. In the future we may enable pageflipping from
9845 * a disabled primary plane.
9846 */
9847 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9848 return -EBUSY;
9849
9850 /* Can't change pixel format via MI display flips. */
9851 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9852 return -EINVAL;
9853
9854 /*
9855 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9856 * Note that pitch changes could also affect these register.
9857 */
9858 if (INTEL_INFO(dev)->gen > 3 &&
9859 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9860 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9861 return -EINVAL;
9862
9863 if (i915_terminally_wedged(&dev_priv->gpu_error))
9864 goto out_hang;
9865
9866 work = kzalloc(sizeof(*work), GFP_KERNEL);
9867 if (work == NULL)
9868 return -ENOMEM;
9869
9870 work->event = event;
9871 work->crtc = crtc;
9872 work->old_fb_obj = intel_fb_obj(old_fb);
9873 INIT_WORK(&work->work, intel_unpin_work_fn);
9874
9875 ret = drm_crtc_vblank_get(crtc);
9876 if (ret)
9877 goto free_work;
9878
9879 /* We borrow the event spin lock for protecting unpin_work */
9880 spin_lock_irqsave(&dev->event_lock, flags);
9881 if (intel_crtc->unpin_work) {
9882 /* Before declaring the flip queue wedged, check if
9883 * the hardware completed the operation behind our backs.
9884 */
9885 if (__intel_pageflip_stall_check(dev, crtc)) {
9886 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9887 page_flip_completed(intel_crtc);
9888 } else {
9889 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9890 spin_unlock_irqrestore(&dev->event_lock, flags);
9891
9892 drm_crtc_vblank_put(crtc);
9893 kfree(work);
9894 return -EBUSY;
9895 }
9896 }
9897 intel_crtc->unpin_work = work;
9898 spin_unlock_irqrestore(&dev->event_lock, flags);
9899
9900 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9901 flush_workqueue(dev_priv->wq);
9902
9903 ret = i915_mutex_lock_interruptible(dev);
9904 if (ret)
9905 goto cleanup;
9906
9907 /* Reference the objects for the scheduled work. */
9908 drm_gem_object_reference(&work->old_fb_obj->base);
9909 drm_gem_object_reference(&obj->base);
9910
9911 crtc->primary->fb = fb;
9912
9913 work->pending_flip_obj = obj;
9914
9915 atomic_inc(&intel_crtc->unpin_work_count);
9916 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9917
9918 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9919 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9920
9921 if (IS_VALLEYVIEW(dev)) {
9922 ring = &dev_priv->ring[BCS];
9923 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9924 /* vlv: DISPLAY_FLIP fails to change tiling */
9925 ring = NULL;
9926 } else if (IS_IVYBRIDGE(dev)) {
9927 ring = &dev_priv->ring[BCS];
9928 } else if (INTEL_INFO(dev)->gen >= 7) {
9929 ring = obj->ring;
9930 if (ring == NULL || ring->id != RCS)
9931 ring = &dev_priv->ring[BCS];
9932 } else {
9933 ring = &dev_priv->ring[RCS];
9934 }
9935
9936 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9937 if (ret)
9938 goto cleanup_pending;
9939
9940 work->gtt_offset =
9941 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9942
9943 if (use_mmio_flip(ring, obj)) {
9944 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9945 page_flip_flags);
9946 if (ret)
9947 goto cleanup_unpin;
9948
9949 work->flip_queued_seqno = obj->last_write_seqno;
9950 work->flip_queued_ring = obj->ring;
9951 } else {
9952 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9953 page_flip_flags);
9954 if (ret)
9955 goto cleanup_unpin;
9956
9957 work->flip_queued_seqno = intel_ring_get_seqno(ring);
9958 work->flip_queued_ring = ring;
9959 }
9960
9961 work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9962 work->enable_stall_check = true;
9963
9964 i915_gem_track_fb(work->old_fb_obj, obj,
9965 INTEL_FRONTBUFFER_PRIMARY(pipe));
9966
9967 intel_disable_fbc(dev);
9968 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9969 mutex_unlock(&dev->struct_mutex);
9970
9971 trace_i915_flip_request(intel_crtc->plane, obj);
9972
9973 return 0;
9974
9975 cleanup_unpin:
9976 intel_unpin_fb_obj(obj);
9977 cleanup_pending:
9978 atomic_dec(&intel_crtc->unpin_work_count);
9979 crtc->primary->fb = old_fb;
9980 drm_gem_object_unreference(&work->old_fb_obj->base);
9981 drm_gem_object_unreference(&obj->base);
9982 mutex_unlock(&dev->struct_mutex);
9983
9984 cleanup:
9985 spin_lock_irqsave(&dev->event_lock, flags);
9986 intel_crtc->unpin_work = NULL;
9987 spin_unlock_irqrestore(&dev->event_lock, flags);
9988
9989 drm_crtc_vblank_put(crtc);
9990 free_work:
9991 kfree(work);
9992
9993 if (ret == -EIO) {
9994 out_hang:
9995 intel_crtc_wait_for_pending_flips(crtc);
9996 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9997 if (ret == 0 && event)
9998 drm_send_vblank_event(dev, pipe, event);
9999 }
10000 return ret;
10001 }
10002
10003 static struct drm_crtc_helper_funcs intel_helper_funcs = {
10004 .mode_set_base_atomic = intel_pipe_set_base_atomic,
10005 .load_lut = intel_crtc_load_lut,
10006 };
10007
10008 /**
10009 * intel_modeset_update_staged_output_state
10010 *
10011 * Updates the staged output configuration state, e.g. after we've read out the
10012 * current hw state.
10013 */
10014 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
10015 {
10016 struct intel_crtc *crtc;
10017 struct intel_encoder *encoder;
10018 struct intel_connector *connector;
10019
10020 list_for_each_entry(connector, &dev->mode_config.connector_list,
10021 base.head) {
10022 connector->new_encoder =
10023 to_intel_encoder(connector->base.encoder);
10024 }
10025
10026 for_each_intel_encoder(dev, encoder) {
10027 encoder->new_crtc =
10028 to_intel_crtc(encoder->base.crtc);
10029 }
10030
10031 for_each_intel_crtc(dev, crtc) {
10032 crtc->new_enabled = crtc->base.enabled;
10033
10034 if (crtc->new_enabled)
10035 crtc->new_config = &crtc->config;
10036 else
10037 crtc->new_config = NULL;
10038 }
10039 }
10040
10041 /**
10042 * intel_modeset_commit_output_state
10043 *
10044 * This function copies the stage display pipe configuration to the real one.
10045 */
10046 static void intel_modeset_commit_output_state(struct drm_device *dev)
10047 {
10048 struct intel_crtc *crtc;
10049 struct intel_encoder *encoder;
10050 struct intel_connector *connector;
10051
10052 list_for_each_entry(connector, &dev->mode_config.connector_list,
10053 base.head) {
10054 connector->base.encoder = &connector->new_encoder->base;
10055 }
10056
10057 for_each_intel_encoder(dev, encoder) {
10058 encoder->base.crtc = &encoder->new_crtc->base;
10059 }
10060
10061 for_each_intel_crtc(dev, crtc) {
10062 crtc->base.enabled = crtc->new_enabled;
10063 }
10064 }
10065
10066 static void
10067 connected_sink_compute_bpp(struct intel_connector *connector,
10068 struct intel_crtc_config *pipe_config)
10069 {
10070 int bpp = pipe_config->pipe_bpp;
10071
10072 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10073 connector->base.base.id,
10074 connector->base.name);
10075
10076 /* Don't use an invalid EDID bpc value */
10077 if (connector->base.display_info.bpc &&
10078 connector->base.display_info.bpc * 3 < bpp) {
10079 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10080 bpp, connector->base.display_info.bpc*3);
10081 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10082 }
10083
10084 /* Clamp bpp to 8 on screens without EDID 1.4 */
10085 if (connector->base.display_info.bpc == 0 && bpp > 24) {
10086 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10087 bpp);
10088 pipe_config->pipe_bpp = 24;
10089 }
10090 }
10091
10092 static int
10093 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10094 struct drm_framebuffer *fb,
10095 struct intel_crtc_config *pipe_config)
10096 {
10097 struct drm_device *dev = crtc->base.dev;
10098 struct intel_connector *connector;
10099 int bpp;
10100
10101 switch (fb->pixel_format) {
10102 case DRM_FORMAT_C8:
10103 bpp = 8*3; /* since we go through a colormap */
10104 break;
10105 case DRM_FORMAT_XRGB1555:
10106 case DRM_FORMAT_ARGB1555:
10107 /* checked in intel_framebuffer_init already */
10108 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10109 return -EINVAL;
10110 case DRM_FORMAT_RGB565:
10111 bpp = 6*3; /* min is 18bpp */
10112 break;
10113 case DRM_FORMAT_XBGR8888:
10114 case DRM_FORMAT_ABGR8888:
10115 /* checked in intel_framebuffer_init already */
10116 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10117 return -EINVAL;
10118 case DRM_FORMAT_XRGB8888:
10119 case DRM_FORMAT_ARGB8888:
10120 bpp = 8*3;
10121 break;
10122 case DRM_FORMAT_XRGB2101010:
10123 case DRM_FORMAT_ARGB2101010:
10124 case DRM_FORMAT_XBGR2101010:
10125 case DRM_FORMAT_ABGR2101010:
10126 /* checked in intel_framebuffer_init already */
10127 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10128 return -EINVAL;
10129 bpp = 10*3;
10130 break;
10131 /* TODO: gen4+ supports 16 bpc floating point, too. */
10132 default:
10133 DRM_DEBUG_KMS("unsupported depth\n");
10134 return -EINVAL;
10135 }
10136
10137 pipe_config->pipe_bpp = bpp;
10138
10139 /* Clamp display bpp to EDID value */
10140 list_for_each_entry(connector, &dev->mode_config.connector_list,
10141 base.head) {
10142 if (!connector->new_encoder ||
10143 connector->new_encoder->new_crtc != crtc)
10144 continue;
10145
10146 connected_sink_compute_bpp(connector, pipe_config);
10147 }
10148
10149 return bpp;
10150 }
10151
10152 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10153 {
10154 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10155 "type: 0x%x flags: 0x%x\n",
10156 mode->crtc_clock,
10157 mode->crtc_hdisplay, mode->crtc_hsync_start,
10158 mode->crtc_hsync_end, mode->crtc_htotal,
10159 mode->crtc_vdisplay, mode->crtc_vsync_start,
10160 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10161 }
10162
10163 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10164 struct intel_crtc_config *pipe_config,
10165 const char *context)
10166 {
10167 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10168 context, pipe_name(crtc->pipe));
10169
10170 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10171 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10172 pipe_config->pipe_bpp, pipe_config->dither);
10173 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10174 pipe_config->has_pch_encoder,
10175 pipe_config->fdi_lanes,
10176 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10177 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10178 pipe_config->fdi_m_n.tu);
10179 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10180 pipe_config->has_dp_encoder,
10181 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10182 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10183 pipe_config->dp_m_n.tu);
10184
10185 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10186 pipe_config->has_dp_encoder,
10187 pipe_config->dp_m2_n2.gmch_m,
10188 pipe_config->dp_m2_n2.gmch_n,
10189 pipe_config->dp_m2_n2.link_m,
10190 pipe_config->dp_m2_n2.link_n,
10191 pipe_config->dp_m2_n2.tu);
10192
10193 DRM_DEBUG_KMS("requested mode:\n");
10194 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
10195 DRM_DEBUG_KMS("adjusted mode:\n");
10196 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
10197 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
10198 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10199 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10200 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10201 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10202 pipe_config->gmch_pfit.control,
10203 pipe_config->gmch_pfit.pgm_ratios,
10204 pipe_config->gmch_pfit.lvds_border_bits);
10205 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10206 pipe_config->pch_pfit.pos,
10207 pipe_config->pch_pfit.size,
10208 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10209 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10210 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10211 }
10212
10213 static bool encoders_cloneable(const struct intel_encoder *a,
10214 const struct intel_encoder *b)
10215 {
10216 /* masks could be asymmetric, so check both ways */
10217 return a == b || (a->cloneable & (1 << b->type) &&
10218 b->cloneable & (1 << a->type));
10219 }
10220
10221 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10222 struct intel_encoder *encoder)
10223 {
10224 struct drm_device *dev = crtc->base.dev;
10225 struct intel_encoder *source_encoder;
10226
10227 for_each_intel_encoder(dev, source_encoder) {
10228 if (source_encoder->new_crtc != crtc)
10229 continue;
10230
10231 if (!encoders_cloneable(encoder, source_encoder))
10232 return false;
10233 }
10234
10235 return true;
10236 }
10237
10238 static bool check_encoder_cloning(struct intel_crtc *crtc)
10239 {
10240 struct drm_device *dev = crtc->base.dev;
10241 struct intel_encoder *encoder;
10242
10243 for_each_intel_encoder(dev, encoder) {
10244 if (encoder->new_crtc != crtc)
10245 continue;
10246
10247 if (!check_single_encoder_cloning(crtc, encoder))
10248 return false;
10249 }
10250
10251 return true;
10252 }
10253
10254 static struct intel_crtc_config *
10255 intel_modeset_pipe_config(struct drm_crtc *crtc,
10256 struct drm_framebuffer *fb,
10257 struct drm_display_mode *mode)
10258 {
10259 struct drm_device *dev = crtc->dev;
10260 struct intel_encoder *encoder;
10261 struct intel_crtc_config *pipe_config;
10262 int plane_bpp, ret = -EINVAL;
10263 bool retry = true;
10264
10265 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10266 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10267 return ERR_PTR(-EINVAL);
10268 }
10269
10270 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10271 if (!pipe_config)
10272 return ERR_PTR(-ENOMEM);
10273
10274 drm_mode_copy(&pipe_config->adjusted_mode, mode);
10275 drm_mode_copy(&pipe_config->requested_mode, mode);
10276
10277 pipe_config->cpu_transcoder =
10278 (enum transcoder) to_intel_crtc(crtc)->pipe;
10279 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10280
10281 /*
10282 * Sanitize sync polarity flags based on requested ones. If neither
10283 * positive or negative polarity is requested, treat this as meaning
10284 * negative polarity.
10285 */
10286 if (!(pipe_config->adjusted_mode.flags &
10287 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10288 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10289
10290 if (!(pipe_config->adjusted_mode.flags &
10291 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10292 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10293
10294 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10295 * plane pixel format and any sink constraints into account. Returns the
10296 * source plane bpp so that dithering can be selected on mismatches
10297 * after encoders and crtc also have had their say. */
10298 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10299 fb, pipe_config);
10300 if (plane_bpp < 0)
10301 goto fail;
10302
10303 /*
10304 * Determine the real pipe dimensions. Note that stereo modes can
10305 * increase the actual pipe size due to the frame doubling and
10306 * insertion of additional space for blanks between the frame. This
10307 * is stored in the crtc timings. We use the requested mode to do this
10308 * computation to clearly distinguish it from the adjusted mode, which
10309 * can be changed by the connectors in the below retry loop.
10310 */
10311 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10312 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10313 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10314
10315 encoder_retry:
10316 /* Ensure the port clock defaults are reset when retrying. */
10317 pipe_config->port_clock = 0;
10318 pipe_config->pixel_multiplier = 1;
10319
10320 /* Fill in default crtc timings, allow encoders to overwrite them. */
10321 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
10322
10323 /* Pass our mode to the connectors and the CRTC to give them a chance to
10324 * adjust it according to limitations or connector properties, and also
10325 * a chance to reject the mode entirely.
10326 */
10327 for_each_intel_encoder(dev, encoder) {
10328
10329 if (&encoder->new_crtc->base != crtc)
10330 continue;
10331
10332 if (!(encoder->compute_config(encoder, pipe_config))) {
10333 DRM_DEBUG_KMS("Encoder config failure\n");
10334 goto fail;
10335 }
10336 }
10337
10338 /* Set default port clock if not overwritten by the encoder. Needs to be
10339 * done afterwards in case the encoder adjusts the mode. */
10340 if (!pipe_config->port_clock)
10341 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10342 * pipe_config->pixel_multiplier;
10343
10344 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10345 if (ret < 0) {
10346 DRM_DEBUG_KMS("CRTC fixup failed\n");
10347 goto fail;
10348 }
10349
10350 if (ret == RETRY) {
10351 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10352 ret = -EINVAL;
10353 goto fail;
10354 }
10355
10356 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10357 retry = false;
10358 goto encoder_retry;
10359 }
10360
10361 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10362 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10363 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10364
10365 return pipe_config;
10366 fail:
10367 kfree(pipe_config);
10368 return ERR_PTR(ret);
10369 }
10370
10371 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10372 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10373 static void
10374 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10375 unsigned *prepare_pipes, unsigned *disable_pipes)
10376 {
10377 struct intel_crtc *intel_crtc;
10378 struct drm_device *dev = crtc->dev;
10379 struct intel_encoder *encoder;
10380 struct intel_connector *connector;
10381 struct drm_crtc *tmp_crtc;
10382
10383 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10384
10385 /* Check which crtcs have changed outputs connected to them, these need
10386 * to be part of the prepare_pipes mask. We don't (yet) support global
10387 * modeset across multiple crtcs, so modeset_pipes will only have one
10388 * bit set at most. */
10389 list_for_each_entry(connector, &dev->mode_config.connector_list,
10390 base.head) {
10391 if (connector->base.encoder == &connector->new_encoder->base)
10392 continue;
10393
10394 if (connector->base.encoder) {
10395 tmp_crtc = connector->base.encoder->crtc;
10396
10397 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10398 }
10399
10400 if (connector->new_encoder)
10401 *prepare_pipes |=
10402 1 << connector->new_encoder->new_crtc->pipe;
10403 }
10404
10405 for_each_intel_encoder(dev, encoder) {
10406 if (encoder->base.crtc == &encoder->new_crtc->base)
10407 continue;
10408
10409 if (encoder->base.crtc) {
10410 tmp_crtc = encoder->base.crtc;
10411
10412 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10413 }
10414
10415 if (encoder->new_crtc)
10416 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10417 }
10418
10419 /* Check for pipes that will be enabled/disabled ... */
10420 for_each_intel_crtc(dev, intel_crtc) {
10421 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10422 continue;
10423
10424 if (!intel_crtc->new_enabled)
10425 *disable_pipes |= 1 << intel_crtc->pipe;
10426 else
10427 *prepare_pipes |= 1 << intel_crtc->pipe;
10428 }
10429
10430
10431 /* set_mode is also used to update properties on life display pipes. */
10432 intel_crtc = to_intel_crtc(crtc);
10433 if (intel_crtc->new_enabled)
10434 *prepare_pipes |= 1 << intel_crtc->pipe;
10435
10436 /*
10437 * For simplicity do a full modeset on any pipe where the output routing
10438 * changed. We could be more clever, but that would require us to be
10439 * more careful with calling the relevant encoder->mode_set functions.
10440 */
10441 if (*prepare_pipes)
10442 *modeset_pipes = *prepare_pipes;
10443
10444 /* ... and mask these out. */
10445 *modeset_pipes &= ~(*disable_pipes);
10446 *prepare_pipes &= ~(*disable_pipes);
10447
10448 /*
10449 * HACK: We don't (yet) fully support global modesets. intel_set_config
10450 * obies this rule, but the modeset restore mode of
10451 * intel_modeset_setup_hw_state does not.
10452 */
10453 *modeset_pipes &= 1 << intel_crtc->pipe;
10454 *prepare_pipes &= 1 << intel_crtc->pipe;
10455
10456 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10457 *modeset_pipes, *prepare_pipes, *disable_pipes);
10458 }
10459
10460 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10461 {
10462 struct drm_encoder *encoder;
10463 struct drm_device *dev = crtc->dev;
10464
10465 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10466 if (encoder->crtc == crtc)
10467 return true;
10468
10469 return false;
10470 }
10471
10472 static void
10473 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10474 {
10475 struct intel_encoder *intel_encoder;
10476 struct intel_crtc *intel_crtc;
10477 struct drm_connector *connector;
10478
10479 for_each_intel_encoder(dev, intel_encoder) {
10480 if (!intel_encoder->base.crtc)
10481 continue;
10482
10483 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10484
10485 if (prepare_pipes & (1 << intel_crtc->pipe))
10486 intel_encoder->connectors_active = false;
10487 }
10488
10489 intel_modeset_commit_output_state(dev);
10490
10491 /* Double check state. */
10492 for_each_intel_crtc(dev, intel_crtc) {
10493 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10494 WARN_ON(intel_crtc->new_config &&
10495 intel_crtc->new_config != &intel_crtc->config);
10496 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10497 }
10498
10499 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10500 if (!connector->encoder || !connector->encoder->crtc)
10501 continue;
10502
10503 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10504
10505 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10506 struct drm_property *dpms_property =
10507 dev->mode_config.dpms_property;
10508
10509 connector->dpms = DRM_MODE_DPMS_ON;
10510 drm_object_property_set_value(&connector->base,
10511 dpms_property,
10512 DRM_MODE_DPMS_ON);
10513
10514 intel_encoder = to_intel_encoder(connector->encoder);
10515 intel_encoder->connectors_active = true;
10516 }
10517 }
10518
10519 }
10520
10521 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10522 {
10523 int diff;
10524
10525 if (clock1 == clock2)
10526 return true;
10527
10528 if (!clock1 || !clock2)
10529 return false;
10530
10531 diff = abs(clock1 - clock2);
10532
10533 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10534 return true;
10535
10536 return false;
10537 }
10538
10539 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10540 list_for_each_entry((intel_crtc), \
10541 &(dev)->mode_config.crtc_list, \
10542 base.head) \
10543 if (mask & (1 <<(intel_crtc)->pipe))
10544
10545 static bool
10546 intel_pipe_config_compare(struct drm_device *dev,
10547 struct intel_crtc_config *current_config,
10548 struct intel_crtc_config *pipe_config)
10549 {
10550 #define PIPE_CONF_CHECK_X(name) \
10551 if (current_config->name != pipe_config->name) { \
10552 DRM_ERROR("mismatch in " #name " " \
10553 "(expected 0x%08x, found 0x%08x)\n", \
10554 current_config->name, \
10555 pipe_config->name); \
10556 return false; \
10557 }
10558
10559 #define PIPE_CONF_CHECK_I(name) \
10560 if (current_config->name != pipe_config->name) { \
10561 DRM_ERROR("mismatch in " #name " " \
10562 "(expected %i, found %i)\n", \
10563 current_config->name, \
10564 pipe_config->name); \
10565 return false; \
10566 }
10567
10568 /* This is required for BDW+ where there is only one set of registers for
10569 * switching between high and low RR.
10570 * This macro can be used whenever a comparison has to be made between one
10571 * hw state and multiple sw state variables.
10572 */
10573 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10574 if ((current_config->name != pipe_config->name) && \
10575 (current_config->alt_name != pipe_config->name)) { \
10576 DRM_ERROR("mismatch in " #name " " \
10577 "(expected %i or %i, found %i)\n", \
10578 current_config->name, \
10579 current_config->alt_name, \
10580 pipe_config->name); \
10581 return false; \
10582 }
10583
10584 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10585 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10586 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10587 "(expected %i, found %i)\n", \
10588 current_config->name & (mask), \
10589 pipe_config->name & (mask)); \
10590 return false; \
10591 }
10592
10593 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10594 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10595 DRM_ERROR("mismatch in " #name " " \
10596 "(expected %i, found %i)\n", \
10597 current_config->name, \
10598 pipe_config->name); \
10599 return false; \
10600 }
10601
10602 #define PIPE_CONF_QUIRK(quirk) \
10603 ((current_config->quirks | pipe_config->quirks) & (quirk))
10604
10605 PIPE_CONF_CHECK_I(cpu_transcoder);
10606
10607 PIPE_CONF_CHECK_I(has_pch_encoder);
10608 PIPE_CONF_CHECK_I(fdi_lanes);
10609 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10610 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10611 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10612 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10613 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10614
10615 PIPE_CONF_CHECK_I(has_dp_encoder);
10616
10617 if (INTEL_INFO(dev)->gen < 8) {
10618 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10619 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10620 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10621 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10622 PIPE_CONF_CHECK_I(dp_m_n.tu);
10623
10624 if (current_config->has_drrs) {
10625 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10626 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10627 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10628 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10629 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10630 }
10631 } else {
10632 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10633 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10634 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10635 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10636 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10637 }
10638
10639 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10640 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10641 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10642 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10643 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10644 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10645
10646 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10647 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10648 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10649 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10650 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10651 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10652
10653 PIPE_CONF_CHECK_I(pixel_multiplier);
10654 PIPE_CONF_CHECK_I(has_hdmi_sink);
10655 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10656 IS_VALLEYVIEW(dev))
10657 PIPE_CONF_CHECK_I(limited_color_range);
10658
10659 PIPE_CONF_CHECK_I(has_audio);
10660
10661 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10662 DRM_MODE_FLAG_INTERLACE);
10663
10664 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10665 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10666 DRM_MODE_FLAG_PHSYNC);
10667 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10668 DRM_MODE_FLAG_NHSYNC);
10669 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10670 DRM_MODE_FLAG_PVSYNC);
10671 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10672 DRM_MODE_FLAG_NVSYNC);
10673 }
10674
10675 PIPE_CONF_CHECK_I(pipe_src_w);
10676 PIPE_CONF_CHECK_I(pipe_src_h);
10677
10678 /*
10679 * FIXME: BIOS likes to set up a cloned config with lvds+external
10680 * screen. Since we don't yet re-compute the pipe config when moving
10681 * just the lvds port away to another pipe the sw tracking won't match.
10682 *
10683 * Proper atomic modesets with recomputed global state will fix this.
10684 * Until then just don't check gmch state for inherited modes.
10685 */
10686 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10687 PIPE_CONF_CHECK_I(gmch_pfit.control);
10688 /* pfit ratios are autocomputed by the hw on gen4+ */
10689 if (INTEL_INFO(dev)->gen < 4)
10690 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10691 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10692 }
10693
10694 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10695 if (current_config->pch_pfit.enabled) {
10696 PIPE_CONF_CHECK_I(pch_pfit.pos);
10697 PIPE_CONF_CHECK_I(pch_pfit.size);
10698 }
10699
10700 /* BDW+ don't expose a synchronous way to read the state */
10701 if (IS_HASWELL(dev))
10702 PIPE_CONF_CHECK_I(ips_enabled);
10703
10704 PIPE_CONF_CHECK_I(double_wide);
10705
10706 PIPE_CONF_CHECK_X(ddi_pll_sel);
10707
10708 PIPE_CONF_CHECK_I(shared_dpll);
10709 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10710 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10711 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10712 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10713 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10714
10715 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10716 PIPE_CONF_CHECK_I(pipe_bpp);
10717
10718 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10719 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10720
10721 #undef PIPE_CONF_CHECK_X
10722 #undef PIPE_CONF_CHECK_I
10723 #undef PIPE_CONF_CHECK_I_ALT
10724 #undef PIPE_CONF_CHECK_FLAGS
10725 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10726 #undef PIPE_CONF_QUIRK
10727
10728 return true;
10729 }
10730
10731 static void
10732 check_connector_state(struct drm_device *dev)
10733 {
10734 struct intel_connector *connector;
10735
10736 list_for_each_entry(connector, &dev->mode_config.connector_list,
10737 base.head) {
10738 /* This also checks the encoder/connector hw state with the
10739 * ->get_hw_state callbacks. */
10740 intel_connector_check_state(connector);
10741
10742 WARN(&connector->new_encoder->base != connector->base.encoder,
10743 "connector's staged encoder doesn't match current encoder\n");
10744 }
10745 }
10746
10747 static void
10748 check_encoder_state(struct drm_device *dev)
10749 {
10750 struct intel_encoder *encoder;
10751 struct intel_connector *connector;
10752
10753 for_each_intel_encoder(dev, encoder) {
10754 bool enabled = false;
10755 bool active = false;
10756 enum pipe pipe, tracked_pipe;
10757
10758 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10759 encoder->base.base.id,
10760 encoder->base.name);
10761
10762 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10763 "encoder's stage crtc doesn't match current crtc\n");
10764 WARN(encoder->connectors_active && !encoder->base.crtc,
10765 "encoder's active_connectors set, but no crtc\n");
10766
10767 list_for_each_entry(connector, &dev->mode_config.connector_list,
10768 base.head) {
10769 if (connector->base.encoder != &encoder->base)
10770 continue;
10771 enabled = true;
10772 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10773 active = true;
10774 }
10775 /*
10776 * for MST connectors if we unplug the connector is gone
10777 * away but the encoder is still connected to a crtc
10778 * until a modeset happens in response to the hotplug.
10779 */
10780 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10781 continue;
10782
10783 WARN(!!encoder->base.crtc != enabled,
10784 "encoder's enabled state mismatch "
10785 "(expected %i, found %i)\n",
10786 !!encoder->base.crtc, enabled);
10787 WARN(active && !encoder->base.crtc,
10788 "active encoder with no crtc\n");
10789
10790 WARN(encoder->connectors_active != active,
10791 "encoder's computed active state doesn't match tracked active state "
10792 "(expected %i, found %i)\n", active, encoder->connectors_active);
10793
10794 active = encoder->get_hw_state(encoder, &pipe);
10795 WARN(active != encoder->connectors_active,
10796 "encoder's hw state doesn't match sw tracking "
10797 "(expected %i, found %i)\n",
10798 encoder->connectors_active, active);
10799
10800 if (!encoder->base.crtc)
10801 continue;
10802
10803 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10804 WARN(active && pipe != tracked_pipe,
10805 "active encoder's pipe doesn't match"
10806 "(expected %i, found %i)\n",
10807 tracked_pipe, pipe);
10808
10809 }
10810 }
10811
10812 static void
10813 check_crtc_state(struct drm_device *dev)
10814 {
10815 struct drm_i915_private *dev_priv = dev->dev_private;
10816 struct intel_crtc *crtc;
10817 struct intel_encoder *encoder;
10818 struct intel_crtc_config pipe_config;
10819
10820 for_each_intel_crtc(dev, crtc) {
10821 bool enabled = false;
10822 bool active = false;
10823
10824 memset(&pipe_config, 0, sizeof(pipe_config));
10825
10826 DRM_DEBUG_KMS("[CRTC:%d]\n",
10827 crtc->base.base.id);
10828
10829 WARN(crtc->active && !crtc->base.enabled,
10830 "active crtc, but not enabled in sw tracking\n");
10831
10832 for_each_intel_encoder(dev, encoder) {
10833 if (encoder->base.crtc != &crtc->base)
10834 continue;
10835 enabled = true;
10836 if (encoder->connectors_active)
10837 active = true;
10838 }
10839
10840 WARN(active != crtc->active,
10841 "crtc's computed active state doesn't match tracked active state "
10842 "(expected %i, found %i)\n", active, crtc->active);
10843 WARN(enabled != crtc->base.enabled,
10844 "crtc's computed enabled state doesn't match tracked enabled state "
10845 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10846
10847 active = dev_priv->display.get_pipe_config(crtc,
10848 &pipe_config);
10849
10850 /* hw state is inconsistent with the pipe quirk */
10851 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10852 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10853 active = crtc->active;
10854
10855 for_each_intel_encoder(dev, encoder) {
10856 enum pipe pipe;
10857 if (encoder->base.crtc != &crtc->base)
10858 continue;
10859 if (encoder->get_hw_state(encoder, &pipe))
10860 encoder->get_config(encoder, &pipe_config);
10861 }
10862
10863 WARN(crtc->active != active,
10864 "crtc active state doesn't match with hw state "
10865 "(expected %i, found %i)\n", crtc->active, active);
10866
10867 if (active &&
10868 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10869 WARN(1, "pipe state doesn't match!\n");
10870 intel_dump_pipe_config(crtc, &pipe_config,
10871 "[hw state]");
10872 intel_dump_pipe_config(crtc, &crtc->config,
10873 "[sw state]");
10874 }
10875 }
10876 }
10877
10878 static void
10879 check_shared_dpll_state(struct drm_device *dev)
10880 {
10881 struct drm_i915_private *dev_priv = dev->dev_private;
10882 struct intel_crtc *crtc;
10883 struct intel_dpll_hw_state dpll_hw_state;
10884 int i;
10885
10886 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10887 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10888 int enabled_crtcs = 0, active_crtcs = 0;
10889 bool active;
10890
10891 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10892
10893 DRM_DEBUG_KMS("%s\n", pll->name);
10894
10895 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10896
10897 WARN(pll->active > pll->refcount,
10898 "more active pll users than references: %i vs %i\n",
10899 pll->active, pll->refcount);
10900 WARN(pll->active && !pll->on,
10901 "pll in active use but not on in sw tracking\n");
10902 WARN(pll->on && !pll->active,
10903 "pll in on but not on in use in sw tracking\n");
10904 WARN(pll->on != active,
10905 "pll on state mismatch (expected %i, found %i)\n",
10906 pll->on, active);
10907
10908 for_each_intel_crtc(dev, crtc) {
10909 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10910 enabled_crtcs++;
10911 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10912 active_crtcs++;
10913 }
10914 WARN(pll->active != active_crtcs,
10915 "pll active crtcs mismatch (expected %i, found %i)\n",
10916 pll->active, active_crtcs);
10917 WARN(pll->refcount != enabled_crtcs,
10918 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10919 pll->refcount, enabled_crtcs);
10920
10921 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10922 sizeof(dpll_hw_state)),
10923 "pll hw state mismatch\n");
10924 }
10925 }
10926
10927 void
10928 intel_modeset_check_state(struct drm_device *dev)
10929 {
10930 check_connector_state(dev);
10931 check_encoder_state(dev);
10932 check_crtc_state(dev);
10933 check_shared_dpll_state(dev);
10934 }
10935
10936 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10937 int dotclock)
10938 {
10939 /*
10940 * FDI already provided one idea for the dotclock.
10941 * Yell if the encoder disagrees.
10942 */
10943 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10944 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10945 pipe_config->adjusted_mode.crtc_clock, dotclock);
10946 }
10947
10948 static void update_scanline_offset(struct intel_crtc *crtc)
10949 {
10950 struct drm_device *dev = crtc->base.dev;
10951
10952 /*
10953 * The scanline counter increments at the leading edge of hsync.
10954 *
10955 * On most platforms it starts counting from vtotal-1 on the
10956 * first active line. That means the scanline counter value is
10957 * always one less than what we would expect. Ie. just after
10958 * start of vblank, which also occurs at start of hsync (on the
10959 * last active line), the scanline counter will read vblank_start-1.
10960 *
10961 * On gen2 the scanline counter starts counting from 1 instead
10962 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10963 * to keep the value positive), instead of adding one.
10964 *
10965 * On HSW+ the behaviour of the scanline counter depends on the output
10966 * type. For DP ports it behaves like most other platforms, but on HDMI
10967 * there's an extra 1 line difference. So we need to add two instead of
10968 * one to the value.
10969 */
10970 if (IS_GEN2(dev)) {
10971 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10972 int vtotal;
10973
10974 vtotal = mode->crtc_vtotal;
10975 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10976 vtotal /= 2;
10977
10978 crtc->scanline_offset = vtotal - 1;
10979 } else if (HAS_DDI(dev) &&
10980 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
10981 crtc->scanline_offset = 2;
10982 } else
10983 crtc->scanline_offset = 1;
10984 }
10985
10986 static int __intel_set_mode(struct drm_crtc *crtc,
10987 struct drm_display_mode *mode,
10988 int x, int y, struct drm_framebuffer *fb)
10989 {
10990 struct drm_device *dev = crtc->dev;
10991 struct drm_i915_private *dev_priv = dev->dev_private;
10992 struct drm_display_mode *saved_mode;
10993 struct intel_crtc_config *pipe_config = NULL;
10994 struct intel_crtc *intel_crtc;
10995 unsigned disable_pipes, prepare_pipes, modeset_pipes;
10996 int ret = 0;
10997
10998 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10999 if (!saved_mode)
11000 return -ENOMEM;
11001
11002 intel_modeset_affected_pipes(crtc, &modeset_pipes,
11003 &prepare_pipes, &disable_pipes);
11004
11005 *saved_mode = crtc->mode;
11006
11007 /* Hack: Because we don't (yet) support global modeset on multiple
11008 * crtcs, we don't keep track of the new mode for more than one crtc.
11009 * Hence simply check whether any bit is set in modeset_pipes in all the
11010 * pieces of code that are not yet converted to deal with mutliple crtcs
11011 * changing their mode at the same time. */
11012 if (modeset_pipes) {
11013 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
11014 if (IS_ERR(pipe_config)) {
11015 ret = PTR_ERR(pipe_config);
11016 pipe_config = NULL;
11017
11018 goto out;
11019 }
11020 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11021 "[modeset]");
11022 to_intel_crtc(crtc)->new_config = pipe_config;
11023 }
11024
11025 /*
11026 * See if the config requires any additional preparation, e.g.
11027 * to adjust global state with pipes off. We need to do this
11028 * here so we can get the modeset_pipe updated config for the new
11029 * mode set on this crtc. For other crtcs we need to use the
11030 * adjusted_mode bits in the crtc directly.
11031 */
11032 if (IS_VALLEYVIEW(dev)) {
11033 valleyview_modeset_global_pipes(dev, &prepare_pipes);
11034
11035 /* may have added more to prepare_pipes than we should */
11036 prepare_pipes &= ~disable_pipes;
11037 }
11038
11039 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11040 intel_crtc_disable(&intel_crtc->base);
11041
11042 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11043 if (intel_crtc->base.enabled)
11044 dev_priv->display.crtc_disable(&intel_crtc->base);
11045 }
11046
11047 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11048 * to set it here already despite that we pass it down the callchain.
11049 */
11050 if (modeset_pipes) {
11051 crtc->mode = *mode;
11052 /* mode_set/enable/disable functions rely on a correct pipe
11053 * config. */
11054 to_intel_crtc(crtc)->config = *pipe_config;
11055 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
11056
11057 /*
11058 * Calculate and store various constants which
11059 * are later needed by vblank and swap-completion
11060 * timestamping. They are derived from true hwmode.
11061 */
11062 drm_calc_timestamping_constants(crtc,
11063 &pipe_config->adjusted_mode);
11064 }
11065
11066 /* Only after disabling all output pipelines that will be changed can we
11067 * update the the output configuration. */
11068 intel_modeset_update_state(dev, prepare_pipes);
11069
11070 if (dev_priv->display.modeset_global_resources)
11071 dev_priv->display.modeset_global_resources(dev);
11072
11073 /* Set up the DPLL and any encoders state that needs to adjust or depend
11074 * on the DPLL.
11075 */
11076 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11077 struct drm_framebuffer *old_fb = crtc->primary->fb;
11078 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
11079 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11080
11081 mutex_lock(&dev->struct_mutex);
11082 ret = intel_pin_and_fence_fb_obj(dev,
11083 obj,
11084 NULL);
11085 if (ret != 0) {
11086 DRM_ERROR("pin & fence failed\n");
11087 mutex_unlock(&dev->struct_mutex);
11088 goto done;
11089 }
11090 if (old_fb)
11091 intel_unpin_fb_obj(old_obj);
11092 i915_gem_track_fb(old_obj, obj,
11093 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11094 mutex_unlock(&dev->struct_mutex);
11095
11096 crtc->primary->fb = fb;
11097 crtc->x = x;
11098 crtc->y = y;
11099
11100 ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
11101 x, y, fb);
11102 if (ret)
11103 goto done;
11104 }
11105
11106 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11107 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11108 update_scanline_offset(intel_crtc);
11109
11110 dev_priv->display.crtc_enable(&intel_crtc->base);
11111 }
11112
11113 /* FIXME: add subpixel order */
11114 done:
11115 if (ret && crtc->enabled)
11116 crtc->mode = *saved_mode;
11117
11118 out:
11119 kfree(pipe_config);
11120 kfree(saved_mode);
11121 return ret;
11122 }
11123
11124 static int intel_set_mode(struct drm_crtc *crtc,
11125 struct drm_display_mode *mode,
11126 int x, int y, struct drm_framebuffer *fb)
11127 {
11128 int ret;
11129
11130 ret = __intel_set_mode(crtc, mode, x, y, fb);
11131
11132 if (ret == 0)
11133 intel_modeset_check_state(crtc->dev);
11134
11135 return ret;
11136 }
11137
11138 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11139 {
11140 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11141 }
11142
11143 #undef for_each_intel_crtc_masked
11144
11145 static void intel_set_config_free(struct intel_set_config *config)
11146 {
11147 if (!config)
11148 return;
11149
11150 kfree(config->save_connector_encoders);
11151 kfree(config->save_encoder_crtcs);
11152 kfree(config->save_crtc_enabled);
11153 kfree(config);
11154 }
11155
11156 static int intel_set_config_save_state(struct drm_device *dev,
11157 struct intel_set_config *config)
11158 {
11159 struct drm_crtc *crtc;
11160 struct drm_encoder *encoder;
11161 struct drm_connector *connector;
11162 int count;
11163
11164 config->save_crtc_enabled =
11165 kcalloc(dev->mode_config.num_crtc,
11166 sizeof(bool), GFP_KERNEL);
11167 if (!config->save_crtc_enabled)
11168 return -ENOMEM;
11169
11170 config->save_encoder_crtcs =
11171 kcalloc(dev->mode_config.num_encoder,
11172 sizeof(struct drm_crtc *), GFP_KERNEL);
11173 if (!config->save_encoder_crtcs)
11174 return -ENOMEM;
11175
11176 config->save_connector_encoders =
11177 kcalloc(dev->mode_config.num_connector,
11178 sizeof(struct drm_encoder *), GFP_KERNEL);
11179 if (!config->save_connector_encoders)
11180 return -ENOMEM;
11181
11182 /* Copy data. Note that driver private data is not affected.
11183 * Should anything bad happen only the expected state is
11184 * restored, not the drivers personal bookkeeping.
11185 */
11186 count = 0;
11187 for_each_crtc(dev, crtc) {
11188 config->save_crtc_enabled[count++] = crtc->enabled;
11189 }
11190
11191 count = 0;
11192 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11193 config->save_encoder_crtcs[count++] = encoder->crtc;
11194 }
11195
11196 count = 0;
11197 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11198 config->save_connector_encoders[count++] = connector->encoder;
11199 }
11200
11201 return 0;
11202 }
11203
11204 static void intel_set_config_restore_state(struct drm_device *dev,
11205 struct intel_set_config *config)
11206 {
11207 struct intel_crtc *crtc;
11208 struct intel_encoder *encoder;
11209 struct intel_connector *connector;
11210 int count;
11211
11212 count = 0;
11213 for_each_intel_crtc(dev, crtc) {
11214 crtc->new_enabled = config->save_crtc_enabled[count++];
11215
11216 if (crtc->new_enabled)
11217 crtc->new_config = &crtc->config;
11218 else
11219 crtc->new_config = NULL;
11220 }
11221
11222 count = 0;
11223 for_each_intel_encoder(dev, encoder) {
11224 encoder->new_crtc =
11225 to_intel_crtc(config->save_encoder_crtcs[count++]);
11226 }
11227
11228 count = 0;
11229 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11230 connector->new_encoder =
11231 to_intel_encoder(config->save_connector_encoders[count++]);
11232 }
11233 }
11234
11235 static bool
11236 is_crtc_connector_off(struct drm_mode_set *set)
11237 {
11238 int i;
11239
11240 if (set->num_connectors == 0)
11241 return false;
11242
11243 if (WARN_ON(set->connectors == NULL))
11244 return false;
11245
11246 for (i = 0; i < set->num_connectors; i++)
11247 if (set->connectors[i]->encoder &&
11248 set->connectors[i]->encoder->crtc == set->crtc &&
11249 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11250 return true;
11251
11252 return false;
11253 }
11254
11255 static void
11256 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11257 struct intel_set_config *config)
11258 {
11259
11260 /* We should be able to check here if the fb has the same properties
11261 * and then just flip_or_move it */
11262 if (is_crtc_connector_off(set)) {
11263 config->mode_changed = true;
11264 } else if (set->crtc->primary->fb != set->fb) {
11265 /*
11266 * If we have no fb, we can only flip as long as the crtc is
11267 * active, otherwise we need a full mode set. The crtc may
11268 * be active if we've only disabled the primary plane, or
11269 * in fastboot situations.
11270 */
11271 if (set->crtc->primary->fb == NULL) {
11272 struct intel_crtc *intel_crtc =
11273 to_intel_crtc(set->crtc);
11274
11275 if (intel_crtc->active) {
11276 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11277 config->fb_changed = true;
11278 } else {
11279 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11280 config->mode_changed = true;
11281 }
11282 } else if (set->fb == NULL) {
11283 config->mode_changed = true;
11284 } else if (set->fb->pixel_format !=
11285 set->crtc->primary->fb->pixel_format) {
11286 config->mode_changed = true;
11287 } else {
11288 config->fb_changed = true;
11289 }
11290 }
11291
11292 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11293 config->fb_changed = true;
11294
11295 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11296 DRM_DEBUG_KMS("modes are different, full mode set\n");
11297 drm_mode_debug_printmodeline(&set->crtc->mode);
11298 drm_mode_debug_printmodeline(set->mode);
11299 config->mode_changed = true;
11300 }
11301
11302 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11303 set->crtc->base.id, config->mode_changed, config->fb_changed);
11304 }
11305
11306 static int
11307 intel_modeset_stage_output_state(struct drm_device *dev,
11308 struct drm_mode_set *set,
11309 struct intel_set_config *config)
11310 {
11311 struct intel_connector *connector;
11312 struct intel_encoder *encoder;
11313 struct intel_crtc *crtc;
11314 int ro;
11315
11316 /* The upper layers ensure that we either disable a crtc or have a list
11317 * of connectors. For paranoia, double-check this. */
11318 WARN_ON(!set->fb && (set->num_connectors != 0));
11319 WARN_ON(set->fb && (set->num_connectors == 0));
11320
11321 list_for_each_entry(connector, &dev->mode_config.connector_list,
11322 base.head) {
11323 /* Otherwise traverse passed in connector list and get encoders
11324 * for them. */
11325 for (ro = 0; ro < set->num_connectors; ro++) {
11326 if (set->connectors[ro] == &connector->base) {
11327 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11328 break;
11329 }
11330 }
11331
11332 /* If we disable the crtc, disable all its connectors. Also, if
11333 * the connector is on the changing crtc but not on the new
11334 * connector list, disable it. */
11335 if ((!set->fb || ro == set->num_connectors) &&
11336 connector->base.encoder &&
11337 connector->base.encoder->crtc == set->crtc) {
11338 connector->new_encoder = NULL;
11339
11340 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11341 connector->base.base.id,
11342 connector->base.name);
11343 }
11344
11345
11346 if (&connector->new_encoder->base != connector->base.encoder) {
11347 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11348 config->mode_changed = true;
11349 }
11350 }
11351 /* connector->new_encoder is now updated for all connectors. */
11352
11353 /* Update crtc of enabled connectors. */
11354 list_for_each_entry(connector, &dev->mode_config.connector_list,
11355 base.head) {
11356 struct drm_crtc *new_crtc;
11357
11358 if (!connector->new_encoder)
11359 continue;
11360
11361 new_crtc = connector->new_encoder->base.crtc;
11362
11363 for (ro = 0; ro < set->num_connectors; ro++) {
11364 if (set->connectors[ro] == &connector->base)
11365 new_crtc = set->crtc;
11366 }
11367
11368 /* Make sure the new CRTC will work with the encoder */
11369 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11370 new_crtc)) {
11371 return -EINVAL;
11372 }
11373 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11374
11375 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11376 connector->base.base.id,
11377 connector->base.name,
11378 new_crtc->base.id);
11379 }
11380
11381 /* Check for any encoders that needs to be disabled. */
11382 for_each_intel_encoder(dev, encoder) {
11383 int num_connectors = 0;
11384 list_for_each_entry(connector,
11385 &dev->mode_config.connector_list,
11386 base.head) {
11387 if (connector->new_encoder == encoder) {
11388 WARN_ON(!connector->new_encoder->new_crtc);
11389 num_connectors++;
11390 }
11391 }
11392
11393 if (num_connectors == 0)
11394 encoder->new_crtc = NULL;
11395 else if (num_connectors > 1)
11396 return -EINVAL;
11397
11398 /* Only now check for crtc changes so we don't miss encoders
11399 * that will be disabled. */
11400 if (&encoder->new_crtc->base != encoder->base.crtc) {
11401 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11402 config->mode_changed = true;
11403 }
11404 }
11405 /* Now we've also updated encoder->new_crtc for all encoders. */
11406 list_for_each_entry(connector, &dev->mode_config.connector_list,
11407 base.head) {
11408 if (connector->new_encoder)
11409 if (connector->new_encoder != connector->encoder)
11410 connector->encoder = connector->new_encoder;
11411 }
11412 for_each_intel_crtc(dev, crtc) {
11413 crtc->new_enabled = false;
11414
11415 for_each_intel_encoder(dev, encoder) {
11416 if (encoder->new_crtc == crtc) {
11417 crtc->new_enabled = true;
11418 break;
11419 }
11420 }
11421
11422 if (crtc->new_enabled != crtc->base.enabled) {
11423 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11424 crtc->new_enabled ? "en" : "dis");
11425 config->mode_changed = true;
11426 }
11427
11428 if (crtc->new_enabled)
11429 crtc->new_config = &crtc->config;
11430 else
11431 crtc->new_config = NULL;
11432 }
11433
11434 return 0;
11435 }
11436
11437 static void disable_crtc_nofb(struct intel_crtc *crtc)
11438 {
11439 struct drm_device *dev = crtc->base.dev;
11440 struct intel_encoder *encoder;
11441 struct intel_connector *connector;
11442
11443 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11444 pipe_name(crtc->pipe));
11445
11446 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11447 if (connector->new_encoder &&
11448 connector->new_encoder->new_crtc == crtc)
11449 connector->new_encoder = NULL;
11450 }
11451
11452 for_each_intel_encoder(dev, encoder) {
11453 if (encoder->new_crtc == crtc)
11454 encoder->new_crtc = NULL;
11455 }
11456
11457 crtc->new_enabled = false;
11458 crtc->new_config = NULL;
11459 }
11460
11461 static int intel_crtc_set_config(struct drm_mode_set *set)
11462 {
11463 struct drm_device *dev;
11464 struct drm_mode_set save_set;
11465 struct intel_set_config *config;
11466 int ret;
11467
11468 BUG_ON(!set);
11469 BUG_ON(!set->crtc);
11470 BUG_ON(!set->crtc->helper_private);
11471
11472 /* Enforce sane interface api - has been abused by the fb helper. */
11473 BUG_ON(!set->mode && set->fb);
11474 BUG_ON(set->fb && set->num_connectors == 0);
11475
11476 if (set->fb) {
11477 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11478 set->crtc->base.id, set->fb->base.id,
11479 (int)set->num_connectors, set->x, set->y);
11480 } else {
11481 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11482 }
11483
11484 dev = set->crtc->dev;
11485
11486 ret = -ENOMEM;
11487 config = kzalloc(sizeof(*config), GFP_KERNEL);
11488 if (!config)
11489 goto out_config;
11490
11491 ret = intel_set_config_save_state(dev, config);
11492 if (ret)
11493 goto out_config;
11494
11495 save_set.crtc = set->crtc;
11496 save_set.mode = &set->crtc->mode;
11497 save_set.x = set->crtc->x;
11498 save_set.y = set->crtc->y;
11499 save_set.fb = set->crtc->primary->fb;
11500
11501 /* Compute whether we need a full modeset, only an fb base update or no
11502 * change at all. In the future we might also check whether only the
11503 * mode changed, e.g. for LVDS where we only change the panel fitter in
11504 * such cases. */
11505 intel_set_config_compute_mode_changes(set, config);
11506
11507 ret = intel_modeset_stage_output_state(dev, set, config);
11508 if (ret)
11509 goto fail;
11510
11511 if (config->mode_changed) {
11512 ret = intel_set_mode(set->crtc, set->mode,
11513 set->x, set->y, set->fb);
11514 } else if (config->fb_changed) {
11515 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11516
11517 intel_crtc_wait_for_pending_flips(set->crtc);
11518
11519 ret = intel_pipe_set_base(set->crtc,
11520 set->x, set->y, set->fb);
11521
11522 /*
11523 * We need to make sure the primary plane is re-enabled if it
11524 * has previously been turned off.
11525 */
11526 if (!intel_crtc->primary_enabled && ret == 0) {
11527 WARN_ON(!intel_crtc->active);
11528 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11529 }
11530
11531 /*
11532 * In the fastboot case this may be our only check of the
11533 * state after boot. It would be better to only do it on
11534 * the first update, but we don't have a nice way of doing that
11535 * (and really, set_config isn't used much for high freq page
11536 * flipping, so increasing its cost here shouldn't be a big
11537 * deal).
11538 */
11539 if (i915.fastboot && ret == 0)
11540 intel_modeset_check_state(set->crtc->dev);
11541 }
11542
11543 if (ret) {
11544 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11545 set->crtc->base.id, ret);
11546 fail:
11547 intel_set_config_restore_state(dev, config);
11548
11549 /*
11550 * HACK: if the pipe was on, but we didn't have a framebuffer,
11551 * force the pipe off to avoid oopsing in the modeset code
11552 * due to fb==NULL. This should only happen during boot since
11553 * we don't yet reconstruct the FB from the hardware state.
11554 */
11555 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11556 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11557
11558 /* Try to restore the config */
11559 if (config->mode_changed &&
11560 intel_set_mode(save_set.crtc, save_set.mode,
11561 save_set.x, save_set.y, save_set.fb))
11562 DRM_ERROR("failed to restore config after modeset failure\n");
11563 }
11564
11565 out_config:
11566 intel_set_config_free(config);
11567 return ret;
11568 }
11569
11570 static const struct drm_crtc_funcs intel_crtc_funcs = {
11571 .gamma_set = intel_crtc_gamma_set,
11572 .set_config = intel_crtc_set_config,
11573 .destroy = intel_crtc_destroy,
11574 .page_flip = intel_crtc_page_flip,
11575 };
11576
11577 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11578 struct intel_shared_dpll *pll,
11579 struct intel_dpll_hw_state *hw_state)
11580 {
11581 uint32_t val;
11582
11583 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS))
11584 return false;
11585
11586 val = I915_READ(PCH_DPLL(pll->id));
11587 hw_state->dpll = val;
11588 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11589 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11590
11591 return val & DPLL_VCO_ENABLE;
11592 }
11593
11594 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11595 struct intel_shared_dpll *pll)
11596 {
11597 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
11598 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
11599 }
11600
11601 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11602 struct intel_shared_dpll *pll)
11603 {
11604 /* PCH refclock must be enabled first */
11605 ibx_assert_pch_refclk_enabled(dev_priv);
11606
11607 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11608
11609 /* Wait for the clocks to stabilize. */
11610 POSTING_READ(PCH_DPLL(pll->id));
11611 udelay(150);
11612
11613 /* The pixel multiplier can only be updated once the
11614 * DPLL is enabled and the clocks are stable.
11615 *
11616 * So write it again.
11617 */
11618 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11619 POSTING_READ(PCH_DPLL(pll->id));
11620 udelay(200);
11621 }
11622
11623 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11624 struct intel_shared_dpll *pll)
11625 {
11626 struct drm_device *dev = dev_priv->dev;
11627 struct intel_crtc *crtc;
11628
11629 /* Make sure no transcoder isn't still depending on us. */
11630 for_each_intel_crtc(dev, crtc) {
11631 if (intel_crtc_to_shared_dpll(crtc) == pll)
11632 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11633 }
11634
11635 I915_WRITE(PCH_DPLL(pll->id), 0);
11636 POSTING_READ(PCH_DPLL(pll->id));
11637 udelay(200);
11638 }
11639
11640 static char *ibx_pch_dpll_names[] = {
11641 "PCH DPLL A",
11642 "PCH DPLL B",
11643 };
11644
11645 static void ibx_pch_dpll_init(struct drm_device *dev)
11646 {
11647 struct drm_i915_private *dev_priv = dev->dev_private;
11648 int i;
11649
11650 dev_priv->num_shared_dpll = 2;
11651
11652 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11653 dev_priv->shared_dplls[i].id = i;
11654 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11655 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11656 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11657 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11658 dev_priv->shared_dplls[i].get_hw_state =
11659 ibx_pch_dpll_get_hw_state;
11660 }
11661 }
11662
11663 static void intel_shared_dpll_init(struct drm_device *dev)
11664 {
11665 struct drm_i915_private *dev_priv = dev->dev_private;
11666
11667 if (HAS_DDI(dev))
11668 intel_ddi_pll_init(dev);
11669 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11670 ibx_pch_dpll_init(dev);
11671 else
11672 dev_priv->num_shared_dpll = 0;
11673
11674 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11675 }
11676
11677 static int
11678 intel_primary_plane_disable(struct drm_plane *plane)
11679 {
11680 struct drm_device *dev = plane->dev;
11681 struct intel_crtc *intel_crtc;
11682
11683 if (!plane->fb)
11684 return 0;
11685
11686 BUG_ON(!plane->crtc);
11687
11688 intel_crtc = to_intel_crtc(plane->crtc);
11689
11690 /*
11691 * Even though we checked plane->fb above, it's still possible that
11692 * the primary plane has been implicitly disabled because the crtc
11693 * coordinates given weren't visible, or because we detected
11694 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11695 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11696 * In either case, we need to unpin the FB and let the fb pointer get
11697 * updated, but otherwise we don't need to touch the hardware.
11698 */
11699 if (!intel_crtc->primary_enabled)
11700 goto disable_unpin;
11701
11702 intel_crtc_wait_for_pending_flips(plane->crtc);
11703 intel_disable_primary_hw_plane(plane, plane->crtc);
11704
11705 disable_unpin:
11706 mutex_lock(&dev->struct_mutex);
11707 i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
11708 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11709 intel_unpin_fb_obj(intel_fb_obj(plane->fb));
11710 mutex_unlock(&dev->struct_mutex);
11711 plane->fb = NULL;
11712
11713 return 0;
11714 }
11715
11716 static int
11717 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11718 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11719 unsigned int crtc_w, unsigned int crtc_h,
11720 uint32_t src_x, uint32_t src_y,
11721 uint32_t src_w, uint32_t src_h)
11722 {
11723 struct drm_device *dev = crtc->dev;
11724 struct drm_i915_private *dev_priv = dev->dev_private;
11725 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11726 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11727 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11728 struct drm_rect dest = {
11729 /* integer pixels */
11730 .x1 = crtc_x,
11731 .y1 = crtc_y,
11732 .x2 = crtc_x + crtc_w,
11733 .y2 = crtc_y + crtc_h,
11734 };
11735 struct drm_rect src = {
11736 /* 16.16 fixed point */
11737 .x1 = src_x,
11738 .y1 = src_y,
11739 .x2 = src_x + src_w,
11740 .y2 = src_y + src_h,
11741 };
11742 const struct drm_rect clip = {
11743 /* integer pixels */
11744 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
11745 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
11746 };
11747 const struct {
11748 int crtc_x, crtc_y;
11749 unsigned int crtc_w, crtc_h;
11750 uint32_t src_x, src_y, src_w, src_h;
11751 } orig = {
11752 .crtc_x = crtc_x,
11753 .crtc_y = crtc_y,
11754 .crtc_w = crtc_w,
11755 .crtc_h = crtc_h,
11756 .src_x = src_x,
11757 .src_y = src_y,
11758 .src_w = src_w,
11759 .src_h = src_h,
11760 };
11761 struct intel_plane *intel_plane = to_intel_plane(plane);
11762 bool visible;
11763 int ret;
11764
11765 ret = drm_plane_helper_check_update(plane, crtc, fb,
11766 &src, &dest, &clip,
11767 DRM_PLANE_HELPER_NO_SCALING,
11768 DRM_PLANE_HELPER_NO_SCALING,
11769 false, true, &visible);
11770
11771 if (ret)
11772 return ret;
11773
11774 /*
11775 * If the CRTC isn't enabled, we're just pinning the framebuffer,
11776 * updating the fb pointer, and returning without touching the
11777 * hardware. This allows us to later do a drmModeSetCrtc with fb=-1 to
11778 * turn on the display with all planes setup as desired.
11779 */
11780 if (!crtc->enabled) {
11781 mutex_lock(&dev->struct_mutex);
11782
11783 /*
11784 * If we already called setplane while the crtc was disabled,
11785 * we may have an fb pinned; unpin it.
11786 */
11787 if (plane->fb)
11788 intel_unpin_fb_obj(old_obj);
11789
11790 i915_gem_track_fb(old_obj, obj,
11791 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11792
11793 /* Pin and return without programming hardware */
11794 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11795 mutex_unlock(&dev->struct_mutex);
11796
11797 return ret;
11798 }
11799
11800 intel_crtc_wait_for_pending_flips(crtc);
11801
11802 /*
11803 * If clipping results in a non-visible primary plane, we'll disable
11804 * the primary plane. Note that this is a bit different than what
11805 * happens if userspace explicitly disables the plane by passing fb=0
11806 * because plane->fb still gets set and pinned.
11807 */
11808 if (!visible) {
11809 mutex_lock(&dev->struct_mutex);
11810
11811 /*
11812 * Try to pin the new fb first so that we can bail out if we
11813 * fail.
11814 */
11815 if (plane->fb != fb) {
11816 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11817 if (ret) {
11818 mutex_unlock(&dev->struct_mutex);
11819 return ret;
11820 }
11821 }
11822
11823 i915_gem_track_fb(old_obj, obj,
11824 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11825
11826 if (intel_crtc->primary_enabled)
11827 intel_disable_primary_hw_plane(plane, crtc);
11828
11829
11830 if (plane->fb != fb)
11831 if (plane->fb)
11832 intel_unpin_fb_obj(old_obj);
11833
11834 mutex_unlock(&dev->struct_mutex);
11835
11836 } else {
11837 if (intel_crtc && intel_crtc->active &&
11838 intel_crtc->primary_enabled) {
11839 /*
11840 * FBC does not work on some platforms for rotated
11841 * planes, so disable it when rotation is not 0 and
11842 * update it when rotation is set back to 0.
11843 *
11844 * FIXME: This is redundant with the fbc update done in
11845 * the primary plane enable function except that that
11846 * one is done too late. We eventually need to unify
11847 * this.
11848 */
11849 if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11850 dev_priv->fbc.plane == intel_crtc->plane &&
11851 intel_plane->rotation != BIT(DRM_ROTATE_0)) {
11852 intel_disable_fbc(dev);
11853 }
11854 }
11855 ret = intel_pipe_set_base(crtc, src.x1, src.y1, fb);
11856 if (ret)
11857 return ret;
11858
11859 if (!intel_crtc->primary_enabled)
11860 intel_enable_primary_hw_plane(plane, crtc);
11861 }
11862
11863 intel_plane->crtc_x = orig.crtc_x;
11864 intel_plane->crtc_y = orig.crtc_y;
11865 intel_plane->crtc_w = orig.crtc_w;
11866 intel_plane->crtc_h = orig.crtc_h;
11867 intel_plane->src_x = orig.src_x;
11868 intel_plane->src_y = orig.src_y;
11869 intel_plane->src_w = orig.src_w;
11870 intel_plane->src_h = orig.src_h;
11871 intel_plane->obj = obj;
11872
11873 return 0;
11874 }
11875
11876 /* Common destruction function for both primary and cursor planes */
11877 static void intel_plane_destroy(struct drm_plane *plane)
11878 {
11879 struct intel_plane *intel_plane = to_intel_plane(plane);
11880 drm_plane_cleanup(plane);
11881 kfree(intel_plane);
11882 }
11883
11884 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11885 .update_plane = intel_primary_plane_setplane,
11886 .disable_plane = intel_primary_plane_disable,
11887 .destroy = intel_plane_destroy,
11888 .set_property = intel_plane_set_property
11889 };
11890
11891 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11892 int pipe)
11893 {
11894 struct intel_plane *primary;
11895 const uint32_t *intel_primary_formats;
11896 int num_formats;
11897
11898 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11899 if (primary == NULL)
11900 return NULL;
11901
11902 primary->can_scale = false;
11903 primary->max_downscale = 1;
11904 primary->pipe = pipe;
11905 primary->plane = pipe;
11906 primary->rotation = BIT(DRM_ROTATE_0);
11907 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11908 primary->plane = !pipe;
11909
11910 if (INTEL_INFO(dev)->gen <= 3) {
11911 intel_primary_formats = intel_primary_formats_gen2;
11912 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11913 } else {
11914 intel_primary_formats = intel_primary_formats_gen4;
11915 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11916 }
11917
11918 drm_universal_plane_init(dev, &primary->base, 0,
11919 &intel_primary_plane_funcs,
11920 intel_primary_formats, num_formats,
11921 DRM_PLANE_TYPE_PRIMARY);
11922
11923 if (INTEL_INFO(dev)->gen >= 4) {
11924 if (!dev->mode_config.rotation_property)
11925 dev->mode_config.rotation_property =
11926 drm_mode_create_rotation_property(dev,
11927 BIT(DRM_ROTATE_0) |
11928 BIT(DRM_ROTATE_180));
11929 if (dev->mode_config.rotation_property)
11930 drm_object_attach_property(&primary->base.base,
11931 dev->mode_config.rotation_property,
11932 primary->rotation);
11933 }
11934
11935 return &primary->base;
11936 }
11937
11938 static int
11939 intel_cursor_plane_disable(struct drm_plane *plane)
11940 {
11941 if (!plane->fb)
11942 return 0;
11943
11944 BUG_ON(!plane->crtc);
11945
11946 return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
11947 }
11948
11949 static int
11950 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
11951 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11952 unsigned int crtc_w, unsigned int crtc_h,
11953 uint32_t src_x, uint32_t src_y,
11954 uint32_t src_w, uint32_t src_h)
11955 {
11956 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11957 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11958 struct drm_i915_gem_object *obj = intel_fb->obj;
11959 struct drm_rect dest = {
11960 /* integer pixels */
11961 .x1 = crtc_x,
11962 .y1 = crtc_y,
11963 .x2 = crtc_x + crtc_w,
11964 .y2 = crtc_y + crtc_h,
11965 };
11966 struct drm_rect src = {
11967 /* 16.16 fixed point */
11968 .x1 = src_x,
11969 .y1 = src_y,
11970 .x2 = src_x + src_w,
11971 .y2 = src_y + src_h,
11972 };
11973 const struct drm_rect clip = {
11974 /* integer pixels */
11975 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
11976 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
11977 };
11978 bool visible;
11979 int ret;
11980
11981 ret = drm_plane_helper_check_update(plane, crtc, fb,
11982 &src, &dest, &clip,
11983 DRM_PLANE_HELPER_NO_SCALING,
11984 DRM_PLANE_HELPER_NO_SCALING,
11985 true, true, &visible);
11986 if (ret)
11987 return ret;
11988
11989 crtc->cursor_x = crtc_x;
11990 crtc->cursor_y = crtc_y;
11991 if (fb != crtc->cursor->fb) {
11992 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
11993 } else {
11994 intel_crtc_update_cursor(crtc, visible);
11995
11996 intel_frontbuffer_flip(crtc->dev,
11997 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe));
11998
11999 return 0;
12000 }
12001 }
12002 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
12003 .update_plane = intel_cursor_plane_update,
12004 .disable_plane = intel_cursor_plane_disable,
12005 .destroy = intel_plane_destroy,
12006 };
12007
12008 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12009 int pipe)
12010 {
12011 struct intel_plane *cursor;
12012
12013 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12014 if (cursor == NULL)
12015 return NULL;
12016
12017 cursor->can_scale = false;
12018 cursor->max_downscale = 1;
12019 cursor->pipe = pipe;
12020 cursor->plane = pipe;
12021
12022 drm_universal_plane_init(dev, &cursor->base, 0,
12023 &intel_cursor_plane_funcs,
12024 intel_cursor_formats,
12025 ARRAY_SIZE(intel_cursor_formats),
12026 DRM_PLANE_TYPE_CURSOR);
12027 return &cursor->base;
12028 }
12029
12030 static void intel_crtc_init(struct drm_device *dev, int pipe)
12031 {
12032 struct drm_i915_private *dev_priv = dev->dev_private;
12033 struct intel_crtc *intel_crtc;
12034 struct drm_plane *primary = NULL;
12035 struct drm_plane *cursor = NULL;
12036 int i, ret;
12037
12038 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12039 if (intel_crtc == NULL)
12040 return;
12041
12042 primary = intel_primary_plane_create(dev, pipe);
12043 if (!primary)
12044 goto fail;
12045
12046 cursor = intel_cursor_plane_create(dev, pipe);
12047 if (!cursor)
12048 goto fail;
12049
12050 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12051 cursor, &intel_crtc_funcs);
12052 if (ret)
12053 goto fail;
12054
12055 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12056 for (i = 0; i < 256; i++) {
12057 intel_crtc->lut_r[i] = i;
12058 intel_crtc->lut_g[i] = i;
12059 intel_crtc->lut_b[i] = i;
12060 }
12061
12062 /*
12063 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12064 * is hooked to pipe B. Hence we want plane A feeding pipe B.
12065 */
12066 intel_crtc->pipe = pipe;
12067 intel_crtc->plane = pipe;
12068 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12069 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12070 intel_crtc->plane = !pipe;
12071 }
12072
12073 intel_crtc->cursor_base = ~0;
12074 intel_crtc->cursor_cntl = ~0;
12075 intel_crtc->cursor_size = ~0;
12076
12077 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12078 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12079 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12080 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12081
12082 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12083
12084 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12085 return;
12086
12087 fail:
12088 if (primary)
12089 drm_plane_cleanup(primary);
12090 if (cursor)
12091 drm_plane_cleanup(cursor);
12092 kfree(intel_crtc);
12093 }
12094
12095 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12096 {
12097 struct drm_encoder *encoder = connector->base.encoder;
12098 struct drm_device *dev = connector->base.dev;
12099
12100 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12101
12102 if (!encoder)
12103 return INVALID_PIPE;
12104
12105 return to_intel_crtc(encoder->crtc)->pipe;
12106 }
12107
12108 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12109 struct drm_file *file)
12110 {
12111 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12112 struct drm_crtc *drmmode_crtc;
12113 struct intel_crtc *crtc;
12114
12115 if (!drm_core_check_feature(dev, DRIVER_MODESET))
12116 return -ENODEV;
12117
12118 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12119
12120 if (!drmmode_crtc) {
12121 DRM_ERROR("no such CRTC id\n");
12122 return -ENOENT;
12123 }
12124
12125 crtc = to_intel_crtc(drmmode_crtc);
12126 pipe_from_crtc_id->pipe = crtc->pipe;
12127
12128 return 0;
12129 }
12130
12131 static int intel_encoder_clones(struct intel_encoder *encoder)
12132 {
12133 struct drm_device *dev = encoder->base.dev;
12134 struct intel_encoder *source_encoder;
12135 int index_mask = 0;
12136 int entry = 0;
12137
12138 for_each_intel_encoder(dev, source_encoder) {
12139 if (encoders_cloneable(encoder, source_encoder))
12140 index_mask |= (1 << entry);
12141
12142 entry++;
12143 }
12144
12145 return index_mask;
12146 }
12147
12148 static bool has_edp_a(struct drm_device *dev)
12149 {
12150 struct drm_i915_private *dev_priv = dev->dev_private;
12151
12152 if (!IS_MOBILE(dev))
12153 return false;
12154
12155 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12156 return false;
12157
12158 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12159 return false;
12160
12161 return true;
12162 }
12163
12164 const char *intel_output_name(int output)
12165 {
12166 static const char *names[] = {
12167 [INTEL_OUTPUT_UNUSED] = "Unused",
12168 [INTEL_OUTPUT_ANALOG] = "Analog",
12169 [INTEL_OUTPUT_DVO] = "DVO",
12170 [INTEL_OUTPUT_SDVO] = "SDVO",
12171 [INTEL_OUTPUT_LVDS] = "LVDS",
12172 [INTEL_OUTPUT_TVOUT] = "TV",
12173 [INTEL_OUTPUT_HDMI] = "HDMI",
12174 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
12175 [INTEL_OUTPUT_EDP] = "eDP",
12176 [INTEL_OUTPUT_DSI] = "DSI",
12177 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
12178 };
12179
12180 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
12181 return "Invalid";
12182
12183 return names[output];
12184 }
12185
12186 static bool intel_crt_present(struct drm_device *dev)
12187 {
12188 struct drm_i915_private *dev_priv = dev->dev_private;
12189
12190 if (IS_ULT(dev))
12191 return false;
12192
12193 if (IS_CHERRYVIEW(dev))
12194 return false;
12195
12196 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12197 return false;
12198
12199 return true;
12200 }
12201
12202 static void intel_setup_outputs(struct drm_device *dev)
12203 {
12204 struct drm_i915_private *dev_priv = dev->dev_private;
12205 struct intel_encoder *encoder;
12206 bool dpd_is_edp = false;
12207
12208 intel_lvds_init(dev);
12209
12210 if (intel_crt_present(dev))
12211 intel_crt_init(dev);
12212
12213 if (HAS_DDI(dev)) {
12214 int found;
12215
12216 /* Haswell uses DDI functions to detect digital outputs */
12217 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12218 /* DDI A only supports eDP */
12219 if (found)
12220 intel_ddi_init(dev, PORT_A);
12221
12222 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12223 * register */
12224 found = I915_READ(SFUSE_STRAP);
12225
12226 if (found & SFUSE_STRAP_DDIB_DETECTED)
12227 intel_ddi_init(dev, PORT_B);
12228 if (found & SFUSE_STRAP_DDIC_DETECTED)
12229 intel_ddi_init(dev, PORT_C);
12230 if (found & SFUSE_STRAP_DDID_DETECTED)
12231 intel_ddi_init(dev, PORT_D);
12232 } else if (HAS_PCH_SPLIT(dev)) {
12233 int found;
12234 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12235
12236 if (has_edp_a(dev))
12237 intel_dp_init(dev, DP_A, PORT_A);
12238
12239 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12240 /* PCH SDVOB multiplex with HDMIB */
12241 found = intel_sdvo_init(dev, PCH_SDVOB, true);
12242 if (!found)
12243 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12244 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12245 intel_dp_init(dev, PCH_DP_B, PORT_B);
12246 }
12247
12248 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12249 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12250
12251 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12252 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12253
12254 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12255 intel_dp_init(dev, PCH_DP_C, PORT_C);
12256
12257 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12258 intel_dp_init(dev, PCH_DP_D, PORT_D);
12259 } else if (IS_VALLEYVIEW(dev)) {
12260 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
12261 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12262 PORT_B);
12263 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
12264 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12265 }
12266
12267 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
12268 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12269 PORT_C);
12270 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
12271 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12272 }
12273
12274 if (IS_CHERRYVIEW(dev)) {
12275 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) {
12276 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12277 PORT_D);
12278 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12279 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12280 }
12281 }
12282
12283 intel_dsi_init(dev);
12284 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12285 bool found = false;
12286
12287 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12288 DRM_DEBUG_KMS("probing SDVOB\n");
12289 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12290 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12291 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12292 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12293 }
12294
12295 if (!found && SUPPORTS_INTEGRATED_DP(dev))
12296 intel_dp_init(dev, DP_B, PORT_B);
12297 }
12298
12299 /* Before G4X SDVOC doesn't have its own detect register */
12300
12301 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12302 DRM_DEBUG_KMS("probing SDVOC\n");
12303 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12304 }
12305
12306 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12307
12308 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12309 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12310 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12311 }
12312 if (SUPPORTS_INTEGRATED_DP(dev))
12313 intel_dp_init(dev, DP_C, PORT_C);
12314 }
12315
12316 if (SUPPORTS_INTEGRATED_DP(dev) &&
12317 (I915_READ(DP_D) & DP_DETECTED))
12318 intel_dp_init(dev, DP_D, PORT_D);
12319 } else if (IS_GEN2(dev))
12320 intel_dvo_init(dev);
12321
12322 if (SUPPORTS_TV(dev))
12323 intel_tv_init(dev);
12324
12325 intel_edp_psr_init(dev);
12326
12327 for_each_intel_encoder(dev, encoder) {
12328 encoder->base.possible_crtcs = encoder->crtc_mask;
12329 encoder->base.possible_clones =
12330 intel_encoder_clones(encoder);
12331 }
12332
12333 intel_init_pch_refclk(dev);
12334
12335 drm_helper_move_panel_connectors_to_head(dev);
12336 }
12337
12338 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12339 {
12340 struct drm_device *dev = fb->dev;
12341 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12342
12343 drm_framebuffer_cleanup(fb);
12344 mutex_lock(&dev->struct_mutex);
12345 WARN_ON(!intel_fb->obj->framebuffer_references--);
12346 drm_gem_object_unreference(&intel_fb->obj->base);
12347 mutex_unlock(&dev->struct_mutex);
12348 kfree(intel_fb);
12349 }
12350
12351 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12352 struct drm_file *file,
12353 unsigned int *handle)
12354 {
12355 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12356 struct drm_i915_gem_object *obj = intel_fb->obj;
12357
12358 return drm_gem_handle_create(file, &obj->base, handle);
12359 }
12360
12361 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12362 .destroy = intel_user_framebuffer_destroy,
12363 .create_handle = intel_user_framebuffer_create_handle,
12364 };
12365
12366 static int intel_framebuffer_init(struct drm_device *dev,
12367 struct intel_framebuffer *intel_fb,
12368 struct drm_mode_fb_cmd2 *mode_cmd,
12369 struct drm_i915_gem_object *obj)
12370 {
12371 int aligned_height;
12372 int pitch_limit;
12373 int ret;
12374
12375 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12376
12377 if (obj->tiling_mode == I915_TILING_Y) {
12378 DRM_DEBUG("hardware does not support tiling Y\n");
12379 return -EINVAL;
12380 }
12381
12382 if (mode_cmd->pitches[0] & 63) {
12383 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12384 mode_cmd->pitches[0]);
12385 return -EINVAL;
12386 }
12387
12388 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12389 pitch_limit = 32*1024;
12390 } else if (INTEL_INFO(dev)->gen >= 4) {
12391 if (obj->tiling_mode)
12392 pitch_limit = 16*1024;
12393 else
12394 pitch_limit = 32*1024;
12395 } else if (INTEL_INFO(dev)->gen >= 3) {
12396 if (obj->tiling_mode)
12397 pitch_limit = 8*1024;
12398 else
12399 pitch_limit = 16*1024;
12400 } else
12401 /* XXX DSPC is limited to 4k tiled */
12402 pitch_limit = 8*1024;
12403
12404 if (mode_cmd->pitches[0] > pitch_limit) {
12405 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12406 obj->tiling_mode ? "tiled" : "linear",
12407 mode_cmd->pitches[0], pitch_limit);
12408 return -EINVAL;
12409 }
12410
12411 if (obj->tiling_mode != I915_TILING_NONE &&
12412 mode_cmd->pitches[0] != obj->stride) {
12413 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12414 mode_cmd->pitches[0], obj->stride);
12415 return -EINVAL;
12416 }
12417
12418 /* Reject formats not supported by any plane early. */
12419 switch (mode_cmd->pixel_format) {
12420 case DRM_FORMAT_C8:
12421 case DRM_FORMAT_RGB565:
12422 case DRM_FORMAT_XRGB8888:
12423 case DRM_FORMAT_ARGB8888:
12424 break;
12425 case DRM_FORMAT_XRGB1555:
12426 case DRM_FORMAT_ARGB1555:
12427 if (INTEL_INFO(dev)->gen > 3) {
12428 DRM_DEBUG("unsupported pixel format: %s\n",
12429 drm_get_format_name(mode_cmd->pixel_format));
12430 return -EINVAL;
12431 }
12432 break;
12433 case DRM_FORMAT_XBGR8888:
12434 case DRM_FORMAT_ABGR8888:
12435 case DRM_FORMAT_XRGB2101010:
12436 case DRM_FORMAT_ARGB2101010:
12437 case DRM_FORMAT_XBGR2101010:
12438 case DRM_FORMAT_ABGR2101010:
12439 if (INTEL_INFO(dev)->gen < 4) {
12440 DRM_DEBUG("unsupported pixel format: %s\n",
12441 drm_get_format_name(mode_cmd->pixel_format));
12442 return -EINVAL;
12443 }
12444 break;
12445 case DRM_FORMAT_YUYV:
12446 case DRM_FORMAT_UYVY:
12447 case DRM_FORMAT_YVYU:
12448 case DRM_FORMAT_VYUY:
12449 if (INTEL_INFO(dev)->gen < 5) {
12450 DRM_DEBUG("unsupported pixel format: %s\n",
12451 drm_get_format_name(mode_cmd->pixel_format));
12452 return -EINVAL;
12453 }
12454 break;
12455 default:
12456 DRM_DEBUG("unsupported pixel format: %s\n",
12457 drm_get_format_name(mode_cmd->pixel_format));
12458 return -EINVAL;
12459 }
12460
12461 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12462 if (mode_cmd->offsets[0] != 0)
12463 return -EINVAL;
12464
12465 aligned_height = intel_align_height(dev, mode_cmd->height,
12466 obj->tiling_mode);
12467 /* FIXME drm helper for size checks (especially planar formats)? */
12468 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12469 return -EINVAL;
12470
12471 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12472 intel_fb->obj = obj;
12473 intel_fb->obj->framebuffer_references++;
12474
12475 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12476 if (ret) {
12477 DRM_ERROR("framebuffer init failed %d\n", ret);
12478 return ret;
12479 }
12480
12481 return 0;
12482 }
12483
12484 static struct drm_framebuffer *
12485 intel_user_framebuffer_create(struct drm_device *dev,
12486 struct drm_file *filp,
12487 struct drm_mode_fb_cmd2 *mode_cmd)
12488 {
12489 struct drm_i915_gem_object *obj;
12490
12491 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12492 mode_cmd->handles[0]));
12493 if (&obj->base == NULL)
12494 return ERR_PTR(-ENOENT);
12495
12496 return intel_framebuffer_create(dev, mode_cmd, obj);
12497 }
12498
12499 #ifndef CONFIG_DRM_I915_FBDEV
12500 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12501 {
12502 }
12503 #endif
12504
12505 static const struct drm_mode_config_funcs intel_mode_funcs = {
12506 .fb_create = intel_user_framebuffer_create,
12507 .output_poll_changed = intel_fbdev_output_poll_changed,
12508 };
12509
12510 /* Set up chip specific display functions */
12511 static void intel_init_display(struct drm_device *dev)
12512 {
12513 struct drm_i915_private *dev_priv = dev->dev_private;
12514
12515 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12516 dev_priv->display.find_dpll = g4x_find_best_dpll;
12517 else if (IS_CHERRYVIEW(dev))
12518 dev_priv->display.find_dpll = chv_find_best_dpll;
12519 else if (IS_VALLEYVIEW(dev))
12520 dev_priv->display.find_dpll = vlv_find_best_dpll;
12521 else if (IS_PINEVIEW(dev))
12522 dev_priv->display.find_dpll = pnv_find_best_dpll;
12523 else
12524 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12525
12526 if (HAS_DDI(dev)) {
12527 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12528 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12529 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
12530 dev_priv->display.crtc_enable = haswell_crtc_enable;
12531 dev_priv->display.crtc_disable = haswell_crtc_disable;
12532 dev_priv->display.off = ironlake_crtc_off;
12533 dev_priv->display.update_primary_plane =
12534 ironlake_update_primary_plane;
12535 } else if (HAS_PCH_SPLIT(dev)) {
12536 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12537 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12538 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
12539 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12540 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12541 dev_priv->display.off = ironlake_crtc_off;
12542 dev_priv->display.update_primary_plane =
12543 ironlake_update_primary_plane;
12544 } else if (IS_VALLEYVIEW(dev)) {
12545 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12546 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12547 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12548 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12549 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12550 dev_priv->display.off = i9xx_crtc_off;
12551 dev_priv->display.update_primary_plane =
12552 i9xx_update_primary_plane;
12553 } else {
12554 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12555 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12556 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12557 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12558 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12559 dev_priv->display.off = i9xx_crtc_off;
12560 dev_priv->display.update_primary_plane =
12561 i9xx_update_primary_plane;
12562 }
12563
12564 /* Returns the core display clock speed */
12565 if (IS_VALLEYVIEW(dev))
12566 dev_priv->display.get_display_clock_speed =
12567 valleyview_get_display_clock_speed;
12568 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12569 dev_priv->display.get_display_clock_speed =
12570 i945_get_display_clock_speed;
12571 else if (IS_I915G(dev))
12572 dev_priv->display.get_display_clock_speed =
12573 i915_get_display_clock_speed;
12574 else if (IS_I945GM(dev) || IS_845G(dev))
12575 dev_priv->display.get_display_clock_speed =
12576 i9xx_misc_get_display_clock_speed;
12577 else if (IS_PINEVIEW(dev))
12578 dev_priv->display.get_display_clock_speed =
12579 pnv_get_display_clock_speed;
12580 else if (IS_I915GM(dev))
12581 dev_priv->display.get_display_clock_speed =
12582 i915gm_get_display_clock_speed;
12583 else if (IS_I865G(dev))
12584 dev_priv->display.get_display_clock_speed =
12585 i865_get_display_clock_speed;
12586 else if (IS_I85X(dev))
12587 dev_priv->display.get_display_clock_speed =
12588 i855_get_display_clock_speed;
12589 else /* 852, 830 */
12590 dev_priv->display.get_display_clock_speed =
12591 i830_get_display_clock_speed;
12592
12593 if (IS_G4X(dev)) {
12594 dev_priv->display.write_eld = g4x_write_eld;
12595 } else if (IS_GEN5(dev)) {
12596 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12597 dev_priv->display.write_eld = ironlake_write_eld;
12598 } else if (IS_GEN6(dev)) {
12599 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12600 dev_priv->display.write_eld = ironlake_write_eld;
12601 dev_priv->display.modeset_global_resources =
12602 snb_modeset_global_resources;
12603 } else if (IS_IVYBRIDGE(dev)) {
12604 /* FIXME: detect B0+ stepping and use auto training */
12605 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12606 dev_priv->display.write_eld = ironlake_write_eld;
12607 dev_priv->display.modeset_global_resources =
12608 ivb_modeset_global_resources;
12609 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12610 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12611 dev_priv->display.write_eld = haswell_write_eld;
12612 dev_priv->display.modeset_global_resources =
12613 haswell_modeset_global_resources;
12614 } else if (IS_VALLEYVIEW(dev)) {
12615 dev_priv->display.modeset_global_resources =
12616 valleyview_modeset_global_resources;
12617 dev_priv->display.write_eld = ironlake_write_eld;
12618 }
12619
12620 /* Default just returns -ENODEV to indicate unsupported */
12621 dev_priv->display.queue_flip = intel_default_queue_flip;
12622
12623 switch (INTEL_INFO(dev)->gen) {
12624 case 2:
12625 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12626 break;
12627
12628 case 3:
12629 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12630 break;
12631
12632 case 4:
12633 case 5:
12634 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12635 break;
12636
12637 case 6:
12638 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12639 break;
12640 case 7:
12641 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12642 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12643 break;
12644 }
12645
12646 intel_panel_init_backlight_funcs(dev);
12647
12648 mutex_init(&dev_priv->pps_mutex);
12649 }
12650
12651 /*
12652 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12653 * resume, or other times. This quirk makes sure that's the case for
12654 * affected systems.
12655 */
12656 static void quirk_pipea_force(struct drm_device *dev)
12657 {
12658 struct drm_i915_private *dev_priv = dev->dev_private;
12659
12660 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12661 DRM_INFO("applying pipe a force quirk\n");
12662 }
12663
12664 static void quirk_pipeb_force(struct drm_device *dev)
12665 {
12666 struct drm_i915_private *dev_priv = dev->dev_private;
12667
12668 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
12669 DRM_INFO("applying pipe b force quirk\n");
12670 }
12671
12672 /*
12673 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12674 */
12675 static void quirk_ssc_force_disable(struct drm_device *dev)
12676 {
12677 struct drm_i915_private *dev_priv = dev->dev_private;
12678 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12679 DRM_INFO("applying lvds SSC disable quirk\n");
12680 }
12681
12682 /*
12683 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12684 * brightness value
12685 */
12686 static void quirk_invert_brightness(struct drm_device *dev)
12687 {
12688 struct drm_i915_private *dev_priv = dev->dev_private;
12689 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12690 DRM_INFO("applying inverted panel brightness quirk\n");
12691 }
12692
12693 /* Some VBT's incorrectly indicate no backlight is present */
12694 static void quirk_backlight_present(struct drm_device *dev)
12695 {
12696 struct drm_i915_private *dev_priv = dev->dev_private;
12697 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12698 DRM_INFO("applying backlight present quirk\n");
12699 }
12700
12701 struct intel_quirk {
12702 int device;
12703 int subsystem_vendor;
12704 int subsystem_device;
12705 void (*hook)(struct drm_device *dev);
12706 };
12707
12708 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12709 struct intel_dmi_quirk {
12710 void (*hook)(struct drm_device *dev);
12711 const struct dmi_system_id (*dmi_id_list)[];
12712 };
12713
12714 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12715 {
12716 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12717 return 1;
12718 }
12719
12720 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12721 {
12722 .dmi_id_list = &(const struct dmi_system_id[]) {
12723 {
12724 .callback = intel_dmi_reverse_brightness,
12725 .ident = "NCR Corporation",
12726 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12727 DMI_MATCH(DMI_PRODUCT_NAME, ""),
12728 },
12729 },
12730 { } /* terminating entry */
12731 },
12732 .hook = quirk_invert_brightness,
12733 },
12734 };
12735
12736 static struct intel_quirk intel_quirks[] = {
12737 /* HP Mini needs pipe A force quirk (LP: #322104) */
12738 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12739
12740 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12741 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12742
12743 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12744 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12745
12746 /* 830 needs to leave pipe A & dpll A up */
12747 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
12748
12749 /* 830 needs to leave pipe B & dpll B up */
12750 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
12751
12752 /* Lenovo U160 cannot use SSC on LVDS */
12753 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12754
12755 /* Sony Vaio Y cannot use SSC on LVDS */
12756 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12757
12758 /* Acer Aspire 5734Z must invert backlight brightness */
12759 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12760
12761 /* Acer/eMachines G725 */
12762 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12763
12764 /* Acer/eMachines e725 */
12765 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12766
12767 /* Acer/Packard Bell NCL20 */
12768 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12769
12770 /* Acer Aspire 4736Z */
12771 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12772
12773 /* Acer Aspire 5336 */
12774 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12775
12776 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12777 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
12778
12779 /* Toshiba CB35 Chromebook (Celeron 2955U) */
12780 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
12781
12782 /* HP Chromebook 14 (Celeron 2955U) */
12783 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
12784 };
12785
12786 static void intel_init_quirks(struct drm_device *dev)
12787 {
12788 struct pci_dev *d = dev->pdev;
12789 int i;
12790
12791 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12792 struct intel_quirk *q = &intel_quirks[i];
12793
12794 if (d->device == q->device &&
12795 (d->subsystem_vendor == q->subsystem_vendor ||
12796 q->subsystem_vendor == PCI_ANY_ID) &&
12797 (d->subsystem_device == q->subsystem_device ||
12798 q->subsystem_device == PCI_ANY_ID))
12799 q->hook(dev);
12800 }
12801 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12802 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12803 intel_dmi_quirks[i].hook(dev);
12804 }
12805 }
12806
12807 /* Disable the VGA plane that we never use */
12808 static void i915_disable_vga(struct drm_device *dev)
12809 {
12810 struct drm_i915_private *dev_priv = dev->dev_private;
12811 u8 sr1;
12812 u32 vga_reg = i915_vgacntrl_reg(dev);
12813
12814 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12815 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12816 outb(SR01, VGA_SR_INDEX);
12817 sr1 = inb(VGA_SR_DATA);
12818 outb(sr1 | 1<<5, VGA_SR_DATA);
12819 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12820 udelay(300);
12821
12822 /*
12823 * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming
12824 * from S3 without preserving (some of?) the other bits.
12825 */
12826 I915_WRITE(vga_reg, dev_priv->bios_vgacntr | VGA_DISP_DISABLE);
12827 POSTING_READ(vga_reg);
12828 }
12829
12830 void intel_modeset_init_hw(struct drm_device *dev)
12831 {
12832 intel_prepare_ddi(dev);
12833
12834 if (IS_VALLEYVIEW(dev))
12835 vlv_update_cdclk(dev);
12836
12837 intel_init_clock_gating(dev);
12838
12839 intel_enable_gt_powersave(dev);
12840 }
12841
12842 void intel_modeset_suspend_hw(struct drm_device *dev)
12843 {
12844 intel_suspend_hw(dev);
12845 }
12846
12847 void intel_modeset_init(struct drm_device *dev)
12848 {
12849 struct drm_i915_private *dev_priv = dev->dev_private;
12850 int sprite, ret;
12851 enum pipe pipe;
12852 struct intel_crtc *crtc;
12853
12854 drm_mode_config_init(dev);
12855
12856 dev->mode_config.min_width = 0;
12857 dev->mode_config.min_height = 0;
12858
12859 dev->mode_config.preferred_depth = 24;
12860 dev->mode_config.prefer_shadow = 1;
12861
12862 dev->mode_config.funcs = &intel_mode_funcs;
12863
12864 intel_init_quirks(dev);
12865
12866 intel_init_pm(dev);
12867
12868 if (INTEL_INFO(dev)->num_pipes == 0)
12869 return;
12870
12871 intel_init_display(dev);
12872
12873 if (IS_GEN2(dev)) {
12874 dev->mode_config.max_width = 2048;
12875 dev->mode_config.max_height = 2048;
12876 } else if (IS_GEN3(dev)) {
12877 dev->mode_config.max_width = 4096;
12878 dev->mode_config.max_height = 4096;
12879 } else {
12880 dev->mode_config.max_width = 8192;
12881 dev->mode_config.max_height = 8192;
12882 }
12883
12884 if (IS_845G(dev) || IS_I865G(dev)) {
12885 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
12886 dev->mode_config.cursor_height = 1023;
12887 } else if (IS_GEN2(dev)) {
12888 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12889 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12890 } else {
12891 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
12892 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
12893 }
12894
12895 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
12896
12897 DRM_DEBUG_KMS("%d display pipe%s available.\n",
12898 INTEL_INFO(dev)->num_pipes,
12899 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
12900
12901 for_each_pipe(dev_priv, pipe) {
12902 intel_crtc_init(dev, pipe);
12903 for_each_sprite(pipe, sprite) {
12904 ret = intel_plane_init(dev, pipe, sprite);
12905 if (ret)
12906 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12907 pipe_name(pipe), sprite_name(pipe, sprite), ret);
12908 }
12909 }
12910
12911 intel_init_dpio(dev);
12912
12913 intel_shared_dpll_init(dev);
12914
12915 /* save the BIOS value before clobbering it */
12916 dev_priv->bios_vgacntr = I915_READ(i915_vgacntrl_reg(dev));
12917 /* Just disable it once at startup */
12918 i915_disable_vga(dev);
12919 intel_setup_outputs(dev);
12920
12921 /* Just in case the BIOS is doing something questionable. */
12922 intel_disable_fbc(dev);
12923
12924 drm_modeset_lock_all(dev);
12925 intel_modeset_setup_hw_state(dev, false);
12926 drm_modeset_unlock_all(dev);
12927
12928 for_each_intel_crtc(dev, crtc) {
12929 if (!crtc->active)
12930 continue;
12931
12932 /*
12933 * Note that reserving the BIOS fb up front prevents us
12934 * from stuffing other stolen allocations like the ring
12935 * on top. This prevents some ugliness at boot time, and
12936 * can even allow for smooth boot transitions if the BIOS
12937 * fb is large enough for the active pipe configuration.
12938 */
12939 if (dev_priv->display.get_plane_config) {
12940 dev_priv->display.get_plane_config(crtc,
12941 &crtc->plane_config);
12942 /*
12943 * If the fb is shared between multiple heads, we'll
12944 * just get the first one.
12945 */
12946 intel_find_plane_obj(crtc, &crtc->plane_config);
12947 }
12948 }
12949 }
12950
12951 static void intel_enable_pipe_a(struct drm_device *dev)
12952 {
12953 struct intel_connector *connector;
12954 struct drm_connector *crt = NULL;
12955 struct intel_load_detect_pipe load_detect_temp;
12956 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
12957
12958 /* We can't just switch on the pipe A, we need to set things up with a
12959 * proper mode and output configuration. As a gross hack, enable pipe A
12960 * by enabling the load detect pipe once. */
12961 list_for_each_entry(connector,
12962 &dev->mode_config.connector_list,
12963 base.head) {
12964 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
12965 crt = &connector->base;
12966 break;
12967 }
12968 }
12969
12970 if (!crt)
12971 return;
12972
12973 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
12974 intel_release_load_detect_pipe(crt, &load_detect_temp);
12975 }
12976
12977 static bool
12978 intel_check_plane_mapping(struct intel_crtc *crtc)
12979 {
12980 struct drm_device *dev = crtc->base.dev;
12981 struct drm_i915_private *dev_priv = dev->dev_private;
12982 u32 reg, val;
12983
12984 if (INTEL_INFO(dev)->num_pipes == 1)
12985 return true;
12986
12987 reg = DSPCNTR(!crtc->plane);
12988 val = I915_READ(reg);
12989
12990 if ((val & DISPLAY_PLANE_ENABLE) &&
12991 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
12992 return false;
12993
12994 return true;
12995 }
12996
12997 static void intel_sanitize_crtc(struct intel_crtc *crtc)
12998 {
12999 struct drm_device *dev = crtc->base.dev;
13000 struct drm_i915_private *dev_priv = dev->dev_private;
13001 u32 reg;
13002
13003 /* Clear any frame start delays used for debugging left by the BIOS */
13004 reg = PIPECONF(crtc->config.cpu_transcoder);
13005 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13006
13007 /* restore vblank interrupts to correct state */
13008 if (crtc->active)
13009 drm_vblank_on(dev, crtc->pipe);
13010 else
13011 drm_vblank_off(dev, crtc->pipe);
13012
13013 /* We need to sanitize the plane -> pipe mapping first because this will
13014 * disable the crtc (and hence change the state) if it is wrong. Note
13015 * that gen4+ has a fixed plane -> pipe mapping. */
13016 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13017 struct intel_connector *connector;
13018 bool plane;
13019
13020 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13021 crtc->base.base.id);
13022
13023 /* Pipe has the wrong plane attached and the plane is active.
13024 * Temporarily change the plane mapping and disable everything
13025 * ... */
13026 plane = crtc->plane;
13027 crtc->plane = !plane;
13028 crtc->primary_enabled = true;
13029 dev_priv->display.crtc_disable(&crtc->base);
13030 crtc->plane = plane;
13031
13032 /* ... and break all links. */
13033 list_for_each_entry(connector, &dev->mode_config.connector_list,
13034 base.head) {
13035 if (connector->encoder->base.crtc != &crtc->base)
13036 continue;
13037
13038 connector->base.dpms = DRM_MODE_DPMS_OFF;
13039 connector->base.encoder = NULL;
13040 }
13041 /* multiple connectors may have the same encoder:
13042 * handle them and break crtc link separately */
13043 list_for_each_entry(connector, &dev->mode_config.connector_list,
13044 base.head)
13045 if (connector->encoder->base.crtc == &crtc->base) {
13046 connector->encoder->base.crtc = NULL;
13047 connector->encoder->connectors_active = false;
13048 }
13049
13050 WARN_ON(crtc->active);
13051 crtc->base.enabled = false;
13052 }
13053
13054 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13055 crtc->pipe == PIPE_A && !crtc->active) {
13056 /* BIOS forgot to enable pipe A, this mostly happens after
13057 * resume. Force-enable the pipe to fix this, the update_dpms
13058 * call below we restore the pipe to the right state, but leave
13059 * the required bits on. */
13060 intel_enable_pipe_a(dev);
13061 }
13062
13063 /* Adjust the state of the output pipe according to whether we
13064 * have active connectors/encoders. */
13065 intel_crtc_update_dpms(&crtc->base);
13066
13067 if (crtc->active != crtc->base.enabled) {
13068 struct intel_encoder *encoder;
13069
13070 /* This can happen either due to bugs in the get_hw_state
13071 * functions or because the pipe is force-enabled due to the
13072 * pipe A quirk. */
13073 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13074 crtc->base.base.id,
13075 crtc->base.enabled ? "enabled" : "disabled",
13076 crtc->active ? "enabled" : "disabled");
13077
13078 crtc->base.enabled = crtc->active;
13079
13080 /* Because we only establish the connector -> encoder ->
13081 * crtc links if something is active, this means the
13082 * crtc is now deactivated. Break the links. connector
13083 * -> encoder links are only establish when things are
13084 * actually up, hence no need to break them. */
13085 WARN_ON(crtc->active);
13086
13087 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13088 WARN_ON(encoder->connectors_active);
13089 encoder->base.crtc = NULL;
13090 }
13091 }
13092
13093 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13094 /*
13095 * We start out with underrun reporting disabled to avoid races.
13096 * For correct bookkeeping mark this on active crtcs.
13097 *
13098 * Also on gmch platforms we dont have any hardware bits to
13099 * disable the underrun reporting. Which means we need to start
13100 * out with underrun reporting disabled also on inactive pipes,
13101 * since otherwise we'll complain about the garbage we read when
13102 * e.g. coming up after runtime pm.
13103 *
13104 * No protection against concurrent access is required - at
13105 * worst a fifo underrun happens which also sets this to false.
13106 */
13107 crtc->cpu_fifo_underrun_disabled = true;
13108 crtc->pch_fifo_underrun_disabled = true;
13109
13110 update_scanline_offset(crtc);
13111 }
13112 }
13113
13114 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13115 {
13116 struct intel_connector *connector;
13117 struct drm_device *dev = encoder->base.dev;
13118
13119 /* We need to check both for a crtc link (meaning that the
13120 * encoder is active and trying to read from a pipe) and the
13121 * pipe itself being active. */
13122 bool has_active_crtc = encoder->base.crtc &&
13123 to_intel_crtc(encoder->base.crtc)->active;
13124
13125 if (encoder->connectors_active && !has_active_crtc) {
13126 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13127 encoder->base.base.id,
13128 encoder->base.name);
13129
13130 /* Connector is active, but has no active pipe. This is
13131 * fallout from our resume register restoring. Disable
13132 * the encoder manually again. */
13133 if (encoder->base.crtc) {
13134 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13135 encoder->base.base.id,
13136 encoder->base.name);
13137 encoder->disable(encoder);
13138 if (encoder->post_disable)
13139 encoder->post_disable(encoder);
13140 }
13141 encoder->base.crtc = NULL;
13142 encoder->connectors_active = false;
13143
13144 /* Inconsistent output/port/pipe state happens presumably due to
13145 * a bug in one of the get_hw_state functions. Or someplace else
13146 * in our code, like the register restore mess on resume. Clamp
13147 * things to off as a safer default. */
13148 list_for_each_entry(connector,
13149 &dev->mode_config.connector_list,
13150 base.head) {
13151 if (connector->encoder != encoder)
13152 continue;
13153 connector->base.dpms = DRM_MODE_DPMS_OFF;
13154 connector->base.encoder = NULL;
13155 }
13156 }
13157 /* Enabled encoders without active connectors will be fixed in
13158 * the crtc fixup. */
13159 }
13160
13161 void i915_redisable_vga_power_on(struct drm_device *dev)
13162 {
13163 struct drm_i915_private *dev_priv = dev->dev_private;
13164 u32 vga_reg = i915_vgacntrl_reg(dev);
13165
13166 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13167 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13168 i915_disable_vga(dev);
13169 }
13170 }
13171
13172 void i915_redisable_vga(struct drm_device *dev)
13173 {
13174 struct drm_i915_private *dev_priv = dev->dev_private;
13175
13176 /* This function can be called both from intel_modeset_setup_hw_state or
13177 * at a very early point in our resume sequence, where the power well
13178 * structures are not yet restored. Since this function is at a very
13179 * paranoid "someone might have enabled VGA while we were not looking"
13180 * level, just check if the power well is enabled instead of trying to
13181 * follow the "don't touch the power well if we don't need it" policy
13182 * the rest of the driver uses. */
13183 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
13184 return;
13185
13186 i915_redisable_vga_power_on(dev);
13187 }
13188
13189 static bool primary_get_hw_state(struct intel_crtc *crtc)
13190 {
13191 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13192
13193 if (!crtc->active)
13194 return false;
13195
13196 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13197 }
13198
13199 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13200 {
13201 struct drm_i915_private *dev_priv = dev->dev_private;
13202 enum pipe pipe;
13203 struct intel_crtc *crtc;
13204 struct intel_encoder *encoder;
13205 struct intel_connector *connector;
13206 int i;
13207
13208 for_each_intel_crtc(dev, crtc) {
13209 memset(&crtc->config, 0, sizeof(crtc->config));
13210
13211 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13212
13213 crtc->active = dev_priv->display.get_pipe_config(crtc,
13214 &crtc->config);
13215
13216 crtc->base.enabled = crtc->active;
13217 crtc->primary_enabled = primary_get_hw_state(crtc);
13218
13219 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13220 crtc->base.base.id,
13221 crtc->active ? "enabled" : "disabled");
13222 }
13223
13224 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13225 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13226
13227 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
13228 pll->active = 0;
13229 for_each_intel_crtc(dev, crtc) {
13230 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
13231 pll->active++;
13232 }
13233 pll->refcount = pll->active;
13234
13235 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
13236 pll->name, pll->refcount, pll->on);
13237
13238 if (pll->refcount)
13239 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13240 }
13241
13242 for_each_intel_encoder(dev, encoder) {
13243 pipe = 0;
13244
13245 if (encoder->get_hw_state(encoder, &pipe)) {
13246 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13247 encoder->base.crtc = &crtc->base;
13248 encoder->get_config(encoder, &crtc->config);
13249 } else {
13250 encoder->base.crtc = NULL;
13251 }
13252
13253 encoder->connectors_active = false;
13254 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13255 encoder->base.base.id,
13256 encoder->base.name,
13257 encoder->base.crtc ? "enabled" : "disabled",
13258 pipe_name(pipe));
13259 }
13260
13261 list_for_each_entry(connector, &dev->mode_config.connector_list,
13262 base.head) {
13263 if (connector->get_hw_state(connector)) {
13264 connector->base.dpms = DRM_MODE_DPMS_ON;
13265 connector->encoder->connectors_active = true;
13266 connector->base.encoder = &connector->encoder->base;
13267 } else {
13268 connector->base.dpms = DRM_MODE_DPMS_OFF;
13269 connector->base.encoder = NULL;
13270 }
13271 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13272 connector->base.base.id,
13273 connector->base.name,
13274 connector->base.encoder ? "enabled" : "disabled");
13275 }
13276 }
13277
13278 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13279 * and i915 state tracking structures. */
13280 void intel_modeset_setup_hw_state(struct drm_device *dev,
13281 bool force_restore)
13282 {
13283 struct drm_i915_private *dev_priv = dev->dev_private;
13284 enum pipe pipe;
13285 struct intel_crtc *crtc;
13286 struct intel_encoder *encoder;
13287 int i;
13288
13289 intel_modeset_readout_hw_state(dev);
13290
13291 /*
13292 * Now that we have the config, copy it to each CRTC struct
13293 * Note that this could go away if we move to using crtc_config
13294 * checking everywhere.
13295 */
13296 for_each_intel_crtc(dev, crtc) {
13297 if (crtc->active && i915.fastboot) {
13298 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
13299 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13300 crtc->base.base.id);
13301 drm_mode_debug_printmodeline(&crtc->base.mode);
13302 }
13303 }
13304
13305 /* HW state is read out, now we need to sanitize this mess. */
13306 for_each_intel_encoder(dev, encoder) {
13307 intel_sanitize_encoder(encoder);
13308 }
13309
13310 for_each_pipe(dev_priv, pipe) {
13311 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13312 intel_sanitize_crtc(crtc);
13313 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
13314 }
13315
13316 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13317 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13318
13319 if (!pll->on || pll->active)
13320 continue;
13321
13322 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13323
13324 pll->disable(dev_priv, pll);
13325 pll->on = false;
13326 }
13327
13328 if (HAS_PCH_SPLIT(dev))
13329 ilk_wm_get_hw_state(dev);
13330
13331 if (force_restore) {
13332 i915_redisable_vga(dev);
13333
13334 /*
13335 * We need to use raw interfaces for restoring state to avoid
13336 * checking (bogus) intermediate states.
13337 */
13338 for_each_pipe(dev_priv, pipe) {
13339 struct drm_crtc *crtc =
13340 dev_priv->pipe_to_crtc_mapping[pipe];
13341
13342 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13343 crtc->primary->fb);
13344 }
13345 } else {
13346 intel_modeset_update_staged_output_state(dev);
13347 }
13348
13349 intel_modeset_check_state(dev);
13350 }
13351
13352 void intel_modeset_gem_init(struct drm_device *dev)
13353 {
13354 struct drm_crtc *c;
13355 struct drm_i915_gem_object *obj;
13356
13357 mutex_lock(&dev->struct_mutex);
13358 intel_init_gt_powersave(dev);
13359 mutex_unlock(&dev->struct_mutex);
13360
13361 intel_modeset_init_hw(dev);
13362
13363 intel_setup_overlay(dev);
13364
13365 /*
13366 * Make sure any fbs we allocated at startup are properly
13367 * pinned & fenced. When we do the allocation it's too early
13368 * for this.
13369 */
13370 mutex_lock(&dev->struct_mutex);
13371 for_each_crtc(dev, c) {
13372 obj = intel_fb_obj(c->primary->fb);
13373 if (obj == NULL)
13374 continue;
13375
13376 if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) {
13377 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13378 to_intel_crtc(c)->pipe);
13379 drm_framebuffer_unreference(c->primary->fb);
13380 c->primary->fb = NULL;
13381 }
13382 }
13383 mutex_unlock(&dev->struct_mutex);
13384 }
13385
13386 void intel_connector_unregister(struct intel_connector *intel_connector)
13387 {
13388 struct drm_connector *connector = &intel_connector->base;
13389
13390 intel_panel_destroy_backlight(connector);
13391 drm_connector_unregister(connector);
13392 }
13393
13394 void intel_modeset_cleanup(struct drm_device *dev)
13395 {
13396 struct drm_i915_private *dev_priv = dev->dev_private;
13397 struct drm_connector *connector;
13398
13399 /*
13400 * Interrupts and polling as the first thing to avoid creating havoc.
13401 * Too much stuff here (turning of rps, connectors, ...) would
13402 * experience fancy races otherwise.
13403 */
13404 drm_irq_uninstall(dev);
13405 intel_hpd_cancel_work(dev_priv);
13406 dev_priv->pm._irqs_disabled = true;
13407
13408 /*
13409 * Due to the hpd irq storm handling the hotplug work can re-arm the
13410 * poll handlers. Hence disable polling after hpd handling is shut down.
13411 */
13412 drm_kms_helper_poll_fini(dev);
13413
13414 mutex_lock(&dev->struct_mutex);
13415
13416 intel_unregister_dsm_handler();
13417
13418 intel_disable_fbc(dev);
13419
13420 intel_disable_gt_powersave(dev);
13421
13422 ironlake_teardown_rc6(dev);
13423
13424 mutex_unlock(&dev->struct_mutex);
13425
13426 /* flush any delayed tasks or pending work */
13427 flush_scheduled_work();
13428
13429 /* destroy the backlight and sysfs files before encoders/connectors */
13430 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13431 struct intel_connector *intel_connector;
13432
13433 intel_connector = to_intel_connector(connector);
13434 intel_connector->unregister(intel_connector);
13435 }
13436
13437 drm_mode_config_cleanup(dev);
13438
13439 intel_cleanup_overlay(dev);
13440
13441 mutex_lock(&dev->struct_mutex);
13442 intel_cleanup_gt_powersave(dev);
13443 mutex_unlock(&dev->struct_mutex);
13444 }
13445
13446 /*
13447 * Return which encoder is currently attached for connector.
13448 */
13449 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13450 {
13451 return &intel_attached_encoder(connector)->base;
13452 }
13453
13454 void intel_connector_attach_encoder(struct intel_connector *connector,
13455 struct intel_encoder *encoder)
13456 {
13457 connector->encoder = encoder;
13458 drm_mode_connector_attach_encoder(&connector->base,
13459 &encoder->base);
13460 }
13461
13462 /*
13463 * set vga decode state - true == enable VGA decode
13464 */
13465 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13466 {
13467 struct drm_i915_private *dev_priv = dev->dev_private;
13468 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13469 u16 gmch_ctrl;
13470
13471 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13472 DRM_ERROR("failed to read control word\n");
13473 return -EIO;
13474 }
13475
13476 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13477 return 0;
13478
13479 if (state)
13480 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13481 else
13482 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13483
13484 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13485 DRM_ERROR("failed to write control word\n");
13486 return -EIO;
13487 }
13488
13489 return 0;
13490 }
13491
13492 struct intel_display_error_state {
13493
13494 u32 power_well_driver;
13495
13496 int num_transcoders;
13497
13498 struct intel_cursor_error_state {
13499 u32 control;
13500 u32 position;
13501 u32 base;
13502 u32 size;
13503 } cursor[I915_MAX_PIPES];
13504
13505 struct intel_pipe_error_state {
13506 bool power_domain_on;
13507 u32 source;
13508 u32 stat;
13509 } pipe[I915_MAX_PIPES];
13510
13511 struct intel_plane_error_state {
13512 u32 control;
13513 u32 stride;
13514 u32 size;
13515 u32 pos;
13516 u32 addr;
13517 u32 surface;
13518 u32 tile_offset;
13519 } plane[I915_MAX_PIPES];
13520
13521 struct intel_transcoder_error_state {
13522 bool power_domain_on;
13523 enum transcoder cpu_transcoder;
13524
13525 u32 conf;
13526
13527 u32 htotal;
13528 u32 hblank;
13529 u32 hsync;
13530 u32 vtotal;
13531 u32 vblank;
13532 u32 vsync;
13533 } transcoder[4];
13534 };
13535
13536 struct intel_display_error_state *
13537 intel_display_capture_error_state(struct drm_device *dev)
13538 {
13539 struct drm_i915_private *dev_priv = dev->dev_private;
13540 struct intel_display_error_state *error;
13541 int transcoders[] = {
13542 TRANSCODER_A,
13543 TRANSCODER_B,
13544 TRANSCODER_C,
13545 TRANSCODER_EDP,
13546 };
13547 int i;
13548
13549 if (INTEL_INFO(dev)->num_pipes == 0)
13550 return NULL;
13551
13552 error = kzalloc(sizeof(*error), GFP_ATOMIC);
13553 if (error == NULL)
13554 return NULL;
13555
13556 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13557 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13558
13559 for_each_pipe(dev_priv, i) {
13560 error->pipe[i].power_domain_on =
13561 intel_display_power_enabled_unlocked(dev_priv,
13562 POWER_DOMAIN_PIPE(i));
13563 if (!error->pipe[i].power_domain_on)
13564 continue;
13565
13566 error->cursor[i].control = I915_READ(CURCNTR(i));
13567 error->cursor[i].position = I915_READ(CURPOS(i));
13568 error->cursor[i].base = I915_READ(CURBASE(i));
13569
13570 error->plane[i].control = I915_READ(DSPCNTR(i));
13571 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13572 if (INTEL_INFO(dev)->gen <= 3) {
13573 error->plane[i].size = I915_READ(DSPSIZE(i));
13574 error->plane[i].pos = I915_READ(DSPPOS(i));
13575 }
13576 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13577 error->plane[i].addr = I915_READ(DSPADDR(i));
13578 if (INTEL_INFO(dev)->gen >= 4) {
13579 error->plane[i].surface = I915_READ(DSPSURF(i));
13580 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13581 }
13582
13583 error->pipe[i].source = I915_READ(PIPESRC(i));
13584
13585 if (HAS_GMCH_DISPLAY(dev))
13586 error->pipe[i].stat = I915_READ(PIPESTAT(i));
13587 }
13588
13589 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13590 if (HAS_DDI(dev_priv->dev))
13591 error->num_transcoders++; /* Account for eDP. */
13592
13593 for (i = 0; i < error->num_transcoders; i++) {
13594 enum transcoder cpu_transcoder = transcoders[i];
13595
13596 error->transcoder[i].power_domain_on =
13597 intel_display_power_enabled_unlocked(dev_priv,
13598 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13599 if (!error->transcoder[i].power_domain_on)
13600 continue;
13601
13602 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13603
13604 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13605 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13606 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13607 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13608 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13609 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13610 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13611 }
13612
13613 return error;
13614 }
13615
13616 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13617
13618 void
13619 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13620 struct drm_device *dev,
13621 struct intel_display_error_state *error)
13622 {
13623 struct drm_i915_private *dev_priv = dev->dev_private;
13624 int i;
13625
13626 if (!error)
13627 return;
13628
13629 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13630 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13631 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13632 error->power_well_driver);
13633 for_each_pipe(dev_priv, i) {
13634 err_printf(m, "Pipe [%d]:\n", i);
13635 err_printf(m, " Power: %s\n",
13636 error->pipe[i].power_domain_on ? "on" : "off");
13637 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
13638 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
13639
13640 err_printf(m, "Plane [%d]:\n", i);
13641 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
13642 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
13643 if (INTEL_INFO(dev)->gen <= 3) {
13644 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
13645 err_printf(m, " POS: %08x\n", error->plane[i].pos);
13646 }
13647 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13648 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
13649 if (INTEL_INFO(dev)->gen >= 4) {
13650 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
13651 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
13652 }
13653
13654 err_printf(m, "Cursor [%d]:\n", i);
13655 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
13656 err_printf(m, " POS: %08x\n", error->cursor[i].position);
13657 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
13658 }
13659
13660 for (i = 0; i < error->num_transcoders; i++) {
13661 err_printf(m, "CPU transcoder: %c\n",
13662 transcoder_name(error->transcoder[i].cpu_transcoder));
13663 err_printf(m, " Power: %s\n",
13664 error->transcoder[i].power_domain_on ? "on" : "off");
13665 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
13666 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
13667 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
13668 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
13669 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
13670 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
13671 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
13672 }
13673 }
13674
13675 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
13676 {
13677 struct intel_crtc *crtc;
13678
13679 for_each_intel_crtc(dev, crtc) {
13680 struct intel_unpin_work *work;
13681 unsigned long irqflags;
13682
13683 spin_lock_irqsave(&dev->event_lock, irqflags);
13684
13685 work = crtc->unpin_work;
13686
13687 if (work && work->event &&
13688 work->event->base.file_priv == file) {
13689 kfree(work->event);
13690 work->event = NULL;
13691 }
13692
13693 spin_unlock_irqrestore(&dev->event_lock, irqflags);
13694 }
13695 }
Linux kernel - Deliverables
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