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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/hid
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/vgaarb.h>
33 #include "drmP.h"
34 #include "intel_drv.h"
35 #include "i915_drm.h"
36 #include "i915_drv.h"
37 #include "i915_trace.h"
38 #include "drm_dp_helper.h"
39
40 #include "drm_crtc_helper.h"
41
42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
43
44 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
45 static void intel_update_watermarks(struct drm_device *dev);
46 static void intel_increase_pllclock(struct drm_crtc *crtc);
47 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
48
49 typedef struct {
50 /* given values */
51 int n;
52 int m1, m2;
53 int p1, p2;
54 /* derived values */
55 int dot;
56 int vco;
57 int m;
58 int p;
59 } intel_clock_t;
60
61 typedef struct {
62 int min, max;
63 } intel_range_t;
64
65 typedef struct {
66 int dot_limit;
67 int p2_slow, p2_fast;
68 } intel_p2_t;
69
70 #define INTEL_P2_NUM 2
71 typedef struct intel_limit intel_limit_t;
72 struct intel_limit {
73 intel_range_t dot, vco, n, m, m1, m2, p, p1;
74 intel_p2_t p2;
75 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
76 int, int, intel_clock_t *);
77 };
78
79 /* FDI */
80 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
81
82 static bool
83 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
84 int target, int refclk, intel_clock_t *best_clock);
85 static bool
86 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
87 int target, int refclk, intel_clock_t *best_clock);
88
89 static bool
90 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
91 int target, int refclk, intel_clock_t *best_clock);
92 static bool
93 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
94 int target, int refclk, intel_clock_t *best_clock);
95
96 static inline u32 /* units of 100MHz */
97 intel_fdi_link_freq(struct drm_device *dev)
98 {
99 if (IS_GEN5(dev)) {
100 struct drm_i915_private *dev_priv = dev->dev_private;
101 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
102 } else
103 return 27;
104 }
105
106 static const intel_limit_t intel_limits_i8xx_dvo = {
107 .dot = { .min = 25000, .max = 350000 },
108 .vco = { .min = 930000, .max = 1400000 },
109 .n = { .min = 3, .max = 16 },
110 .m = { .min = 96, .max = 140 },
111 .m1 = { .min = 18, .max = 26 },
112 .m2 = { .min = 6, .max = 16 },
113 .p = { .min = 4, .max = 128 },
114 .p1 = { .min = 2, .max = 33 },
115 .p2 = { .dot_limit = 165000,
116 .p2_slow = 4, .p2_fast = 2 },
117 .find_pll = intel_find_best_PLL,
118 };
119
120 static const intel_limit_t intel_limits_i8xx_lvds = {
121 .dot = { .min = 25000, .max = 350000 },
122 .vco = { .min = 930000, .max = 1400000 },
123 .n = { .min = 3, .max = 16 },
124 .m = { .min = 96, .max = 140 },
125 .m1 = { .min = 18, .max = 26 },
126 .m2 = { .min = 6, .max = 16 },
127 .p = { .min = 4, .max = 128 },
128 .p1 = { .min = 1, .max = 6 },
129 .p2 = { .dot_limit = 165000,
130 .p2_slow = 14, .p2_fast = 7 },
131 .find_pll = intel_find_best_PLL,
132 };
133
134 static const intel_limit_t intel_limits_i9xx_sdvo = {
135 .dot = { .min = 20000, .max = 400000 },
136 .vco = { .min = 1400000, .max = 2800000 },
137 .n = { .min = 1, .max = 6 },
138 .m = { .min = 70, .max = 120 },
139 .m1 = { .min = 10, .max = 22 },
140 .m2 = { .min = 5, .max = 9 },
141 .p = { .min = 5, .max = 80 },
142 .p1 = { .min = 1, .max = 8 },
143 .p2 = { .dot_limit = 200000,
144 .p2_slow = 10, .p2_fast = 5 },
145 .find_pll = intel_find_best_PLL,
146 };
147
148 static const intel_limit_t intel_limits_i9xx_lvds = {
149 .dot = { .min = 20000, .max = 400000 },
150 .vco = { .min = 1400000, .max = 2800000 },
151 .n = { .min = 1, .max = 6 },
152 .m = { .min = 70, .max = 120 },
153 .m1 = { .min = 10, .max = 22 },
154 .m2 = { .min = 5, .max = 9 },
155 .p = { .min = 7, .max = 98 },
156 .p1 = { .min = 1, .max = 8 },
157 .p2 = { .dot_limit = 112000,
158 .p2_slow = 14, .p2_fast = 7 },
159 .find_pll = intel_find_best_PLL,
160 };
161
162
163 static const intel_limit_t intel_limits_g4x_sdvo = {
164 .dot = { .min = 25000, .max = 270000 },
165 .vco = { .min = 1750000, .max = 3500000},
166 .n = { .min = 1, .max = 4 },
167 .m = { .min = 104, .max = 138 },
168 .m1 = { .min = 17, .max = 23 },
169 .m2 = { .min = 5, .max = 11 },
170 .p = { .min = 10, .max = 30 },
171 .p1 = { .min = 1, .max = 3},
172 .p2 = { .dot_limit = 270000,
173 .p2_slow = 10,
174 .p2_fast = 10
175 },
176 .find_pll = intel_g4x_find_best_PLL,
177 };
178
179 static const intel_limit_t intel_limits_g4x_hdmi = {
180 .dot = { .min = 22000, .max = 400000 },
181 .vco = { .min = 1750000, .max = 3500000},
182 .n = { .min = 1, .max = 4 },
183 .m = { .min = 104, .max = 138 },
184 .m1 = { .min = 16, .max = 23 },
185 .m2 = { .min = 5, .max = 11 },
186 .p = { .min = 5, .max = 80 },
187 .p1 = { .min = 1, .max = 8},
188 .p2 = { .dot_limit = 165000,
189 .p2_slow = 10, .p2_fast = 5 },
190 .find_pll = intel_g4x_find_best_PLL,
191 };
192
193 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
194 .dot = { .min = 20000, .max = 115000 },
195 .vco = { .min = 1750000, .max = 3500000 },
196 .n = { .min = 1, .max = 3 },
197 .m = { .min = 104, .max = 138 },
198 .m1 = { .min = 17, .max = 23 },
199 .m2 = { .min = 5, .max = 11 },
200 .p = { .min = 28, .max = 112 },
201 .p1 = { .min = 2, .max = 8 },
202 .p2 = { .dot_limit = 0,
203 .p2_slow = 14, .p2_fast = 14
204 },
205 .find_pll = intel_g4x_find_best_PLL,
206 };
207
208 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
209 .dot = { .min = 80000, .max = 224000 },
210 .vco = { .min = 1750000, .max = 3500000 },
211 .n = { .min = 1, .max = 3 },
212 .m = { .min = 104, .max = 138 },
213 .m1 = { .min = 17, .max = 23 },
214 .m2 = { .min = 5, .max = 11 },
215 .p = { .min = 14, .max = 42 },
216 .p1 = { .min = 2, .max = 6 },
217 .p2 = { .dot_limit = 0,
218 .p2_slow = 7, .p2_fast = 7
219 },
220 .find_pll = intel_g4x_find_best_PLL,
221 };
222
223 static const intel_limit_t intel_limits_g4x_display_port = {
224 .dot = { .min = 161670, .max = 227000 },
225 .vco = { .min = 1750000, .max = 3500000},
226 .n = { .min = 1, .max = 2 },
227 .m = { .min = 97, .max = 108 },
228 .m1 = { .min = 0x10, .max = 0x12 },
229 .m2 = { .min = 0x05, .max = 0x06 },
230 .p = { .min = 10, .max = 20 },
231 .p1 = { .min = 1, .max = 2},
232 .p2 = { .dot_limit = 0,
233 .p2_slow = 10, .p2_fast = 10 },
234 .find_pll = intel_find_pll_g4x_dp,
235 };
236
237 static const intel_limit_t intel_limits_pineview_sdvo = {
238 .dot = { .min = 20000, .max = 400000},
239 .vco = { .min = 1700000, .max = 3500000 },
240 /* Pineview's Ncounter is a ring counter */
241 .n = { .min = 3, .max = 6 },
242 .m = { .min = 2, .max = 256 },
243 /* Pineview only has one combined m divider, which we treat as m2. */
244 .m1 = { .min = 0, .max = 0 },
245 .m2 = { .min = 0, .max = 254 },
246 .p = { .min = 5, .max = 80 },
247 .p1 = { .min = 1, .max = 8 },
248 .p2 = { .dot_limit = 200000,
249 .p2_slow = 10, .p2_fast = 5 },
250 .find_pll = intel_find_best_PLL,
251 };
252
253 static const intel_limit_t intel_limits_pineview_lvds = {
254 .dot = { .min = 20000, .max = 400000 },
255 .vco = { .min = 1700000, .max = 3500000 },
256 .n = { .min = 3, .max = 6 },
257 .m = { .min = 2, .max = 256 },
258 .m1 = { .min = 0, .max = 0 },
259 .m2 = { .min = 0, .max = 254 },
260 .p = { .min = 7, .max = 112 },
261 .p1 = { .min = 1, .max = 8 },
262 .p2 = { .dot_limit = 112000,
263 .p2_slow = 14, .p2_fast = 14 },
264 .find_pll = intel_find_best_PLL,
265 };
266
267 /* Ironlake / Sandybridge
268 *
269 * We calculate clock using (register_value + 2) for N/M1/M2, so here
270 * the range value for them is (actual_value - 2).
271 */
272 static const intel_limit_t intel_limits_ironlake_dac = {
273 .dot = { .min = 25000, .max = 350000 },
274 .vco = { .min = 1760000, .max = 3510000 },
275 .n = { .min = 1, .max = 5 },
276 .m = { .min = 79, .max = 127 },
277 .m1 = { .min = 12, .max = 22 },
278 .m2 = { .min = 5, .max = 9 },
279 .p = { .min = 5, .max = 80 },
280 .p1 = { .min = 1, .max = 8 },
281 .p2 = { .dot_limit = 225000,
282 .p2_slow = 10, .p2_fast = 5 },
283 .find_pll = intel_g4x_find_best_PLL,
284 };
285
286 static const intel_limit_t intel_limits_ironlake_single_lvds = {
287 .dot = { .min = 25000, .max = 350000 },
288 .vco = { .min = 1760000, .max = 3510000 },
289 .n = { .min = 1, .max = 3 },
290 .m = { .min = 79, .max = 118 },
291 .m1 = { .min = 12, .max = 22 },
292 .m2 = { .min = 5, .max = 9 },
293 .p = { .min = 28, .max = 112 },
294 .p1 = { .min = 2, .max = 8 },
295 .p2 = { .dot_limit = 225000,
296 .p2_slow = 14, .p2_fast = 14 },
297 .find_pll = intel_g4x_find_best_PLL,
298 };
299
300 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
301 .dot = { .min = 25000, .max = 350000 },
302 .vco = { .min = 1760000, .max = 3510000 },
303 .n = { .min = 1, .max = 3 },
304 .m = { .min = 79, .max = 127 },
305 .m1 = { .min = 12, .max = 22 },
306 .m2 = { .min = 5, .max = 9 },
307 .p = { .min = 14, .max = 56 },
308 .p1 = { .min = 2, .max = 8 },
309 .p2 = { .dot_limit = 225000,
310 .p2_slow = 7, .p2_fast = 7 },
311 .find_pll = intel_g4x_find_best_PLL,
312 };
313
314 /* LVDS 100mhz refclk limits. */
315 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
316 .dot = { .min = 25000, .max = 350000 },
317 .vco = { .min = 1760000, .max = 3510000 },
318 .n = { .min = 1, .max = 2 },
319 .m = { .min = 79, .max = 126 },
320 .m1 = { .min = 12, .max = 22 },
321 .m2 = { .min = 5, .max = 9 },
322 .p = { .min = 28, .max = 112 },
323 .p1 = { .min = 2,.max = 8 },
324 .p2 = { .dot_limit = 225000,
325 .p2_slow = 14, .p2_fast = 14 },
326 .find_pll = intel_g4x_find_best_PLL,
327 };
328
329 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
330 .dot = { .min = 25000, .max = 350000 },
331 .vco = { .min = 1760000, .max = 3510000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 79, .max = 126 },
334 .m1 = { .min = 12, .max = 22 },
335 .m2 = { .min = 5, .max = 9 },
336 .p = { .min = 14, .max = 42 },
337 .p1 = { .min = 2,.max = 6 },
338 .p2 = { .dot_limit = 225000,
339 .p2_slow = 7, .p2_fast = 7 },
340 .find_pll = intel_g4x_find_best_PLL,
341 };
342
343 static const intel_limit_t intel_limits_ironlake_display_port = {
344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000},
346 .n = { .min = 1, .max = 2 },
347 .m = { .min = 81, .max = 90 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 10, .max = 20 },
351 .p1 = { .min = 1, .max = 2},
352 .p2 = { .dot_limit = 0,
353 .p2_slow = 10, .p2_fast = 10 },
354 .find_pll = intel_find_pll_ironlake_dp,
355 };
356
357 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
358 int refclk)
359 {
360 struct drm_device *dev = crtc->dev;
361 struct drm_i915_private *dev_priv = dev->dev_private;
362 const intel_limit_t *limit;
363
364 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
365 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
366 LVDS_CLKB_POWER_UP) {
367 /* LVDS dual channel */
368 if (refclk == 100000)
369 limit = &intel_limits_ironlake_dual_lvds_100m;
370 else
371 limit = &intel_limits_ironlake_dual_lvds;
372 } else {
373 if (refclk == 100000)
374 limit = &intel_limits_ironlake_single_lvds_100m;
375 else
376 limit = &intel_limits_ironlake_single_lvds;
377 }
378 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
379 HAS_eDP)
380 limit = &intel_limits_ironlake_display_port;
381 else
382 limit = &intel_limits_ironlake_dac;
383
384 return limit;
385 }
386
387 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
388 {
389 struct drm_device *dev = crtc->dev;
390 struct drm_i915_private *dev_priv = dev->dev_private;
391 const intel_limit_t *limit;
392
393 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
394 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
395 LVDS_CLKB_POWER_UP)
396 /* LVDS with dual channel */
397 limit = &intel_limits_g4x_dual_channel_lvds;
398 else
399 /* LVDS with dual channel */
400 limit = &intel_limits_g4x_single_channel_lvds;
401 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
402 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
403 limit = &intel_limits_g4x_hdmi;
404 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
405 limit = &intel_limits_g4x_sdvo;
406 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
407 limit = &intel_limits_g4x_display_port;
408 } else /* The option is for other outputs */
409 limit = &intel_limits_i9xx_sdvo;
410
411 return limit;
412 }
413
414 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
415 {
416 struct drm_device *dev = crtc->dev;
417 const intel_limit_t *limit;
418
419 if (HAS_PCH_SPLIT(dev))
420 limit = intel_ironlake_limit(crtc, refclk);
421 else if (IS_G4X(dev)) {
422 limit = intel_g4x_limit(crtc);
423 } else if (IS_PINEVIEW(dev)) {
424 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
425 limit = &intel_limits_pineview_lvds;
426 else
427 limit = &intel_limits_pineview_sdvo;
428 } else if (!IS_GEN2(dev)) {
429 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
430 limit = &intel_limits_i9xx_lvds;
431 else
432 limit = &intel_limits_i9xx_sdvo;
433 } else {
434 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
435 limit = &intel_limits_i8xx_lvds;
436 else
437 limit = &intel_limits_i8xx_dvo;
438 }
439 return limit;
440 }
441
442 /* m1 is reserved as 0 in Pineview, n is a ring counter */
443 static void pineview_clock(int refclk, intel_clock_t *clock)
444 {
445 clock->m = clock->m2 + 2;
446 clock->p = clock->p1 * clock->p2;
447 clock->vco = refclk * clock->m / clock->n;
448 clock->dot = clock->vco / clock->p;
449 }
450
451 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
452 {
453 if (IS_PINEVIEW(dev)) {
454 pineview_clock(refclk, clock);
455 return;
456 }
457 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
458 clock->p = clock->p1 * clock->p2;
459 clock->vco = refclk * clock->m / (clock->n + 2);
460 clock->dot = clock->vco / clock->p;
461 }
462
463 /**
464 * Returns whether any output on the specified pipe is of the specified type
465 */
466 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
467 {
468 struct drm_device *dev = crtc->dev;
469 struct drm_mode_config *mode_config = &dev->mode_config;
470 struct intel_encoder *encoder;
471
472 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
473 if (encoder->base.crtc == crtc && encoder->type == type)
474 return true;
475
476 return false;
477 }
478
479 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
480 /**
481 * Returns whether the given set of divisors are valid for a given refclk with
482 * the given connectors.
483 */
484
485 static bool intel_PLL_is_valid(struct drm_device *dev,
486 const intel_limit_t *limit,
487 const intel_clock_t *clock)
488 {
489 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
490 INTELPllInvalid ("p1 out of range\n");
491 if (clock->p < limit->p.min || limit->p.max < clock->p)
492 INTELPllInvalid ("p out of range\n");
493 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
494 INTELPllInvalid ("m2 out of range\n");
495 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
496 INTELPllInvalid ("m1 out of range\n");
497 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
498 INTELPllInvalid ("m1 <= m2\n");
499 if (clock->m < limit->m.min || limit->m.max < clock->m)
500 INTELPllInvalid ("m out of range\n");
501 if (clock->n < limit->n.min || limit->n.max < clock->n)
502 INTELPllInvalid ("n out of range\n");
503 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
504 INTELPllInvalid ("vco out of range\n");
505 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
506 * connector, etc., rather than just a single range.
507 */
508 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
509 INTELPllInvalid ("dot out of range\n");
510
511 return true;
512 }
513
514 static bool
515 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
516 int target, int refclk, intel_clock_t *best_clock)
517
518 {
519 struct drm_device *dev = crtc->dev;
520 struct drm_i915_private *dev_priv = dev->dev_private;
521 intel_clock_t clock;
522 int err = target;
523
524 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
525 (I915_READ(LVDS)) != 0) {
526 /*
527 * For LVDS, if the panel is on, just rely on its current
528 * settings for dual-channel. We haven't figured out how to
529 * reliably set up different single/dual channel state, if we
530 * even can.
531 */
532 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
533 LVDS_CLKB_POWER_UP)
534 clock.p2 = limit->p2.p2_fast;
535 else
536 clock.p2 = limit->p2.p2_slow;
537 } else {
538 if (target < limit->p2.dot_limit)
539 clock.p2 = limit->p2.p2_slow;
540 else
541 clock.p2 = limit->p2.p2_fast;
542 }
543
544 memset (best_clock, 0, sizeof (*best_clock));
545
546 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
547 clock.m1++) {
548 for (clock.m2 = limit->m2.min;
549 clock.m2 <= limit->m2.max; clock.m2++) {
550 /* m1 is always 0 in Pineview */
551 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
552 break;
553 for (clock.n = limit->n.min;
554 clock.n <= limit->n.max; clock.n++) {
555 for (clock.p1 = limit->p1.min;
556 clock.p1 <= limit->p1.max; clock.p1++) {
557 int this_err;
558
559 intel_clock(dev, refclk, &clock);
560 if (!intel_PLL_is_valid(dev, limit,
561 &clock))
562 continue;
563
564 this_err = abs(clock.dot - target);
565 if (this_err < err) {
566 *best_clock = clock;
567 err = this_err;
568 }
569 }
570 }
571 }
572 }
573
574 return (err != target);
575 }
576
577 static bool
578 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
579 int target, int refclk, intel_clock_t *best_clock)
580 {
581 struct drm_device *dev = crtc->dev;
582 struct drm_i915_private *dev_priv = dev->dev_private;
583 intel_clock_t clock;
584 int max_n;
585 bool found;
586 /* approximately equals target * 0.00585 */
587 int err_most = (target >> 8) + (target >> 9);
588 found = false;
589
590 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
591 int lvds_reg;
592
593 if (HAS_PCH_SPLIT(dev))
594 lvds_reg = PCH_LVDS;
595 else
596 lvds_reg = LVDS;
597 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
598 LVDS_CLKB_POWER_UP)
599 clock.p2 = limit->p2.p2_fast;
600 else
601 clock.p2 = limit->p2.p2_slow;
602 } else {
603 if (target < limit->p2.dot_limit)
604 clock.p2 = limit->p2.p2_slow;
605 else
606 clock.p2 = limit->p2.p2_fast;
607 }
608
609 memset(best_clock, 0, sizeof(*best_clock));
610 max_n = limit->n.max;
611 /* based on hardware requirement, prefer smaller n to precision */
612 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
613 /* based on hardware requirement, prefere larger m1,m2 */
614 for (clock.m1 = limit->m1.max;
615 clock.m1 >= limit->m1.min; clock.m1--) {
616 for (clock.m2 = limit->m2.max;
617 clock.m2 >= limit->m2.min; clock.m2--) {
618 for (clock.p1 = limit->p1.max;
619 clock.p1 >= limit->p1.min; clock.p1--) {
620 int this_err;
621
622 intel_clock(dev, refclk, &clock);
623 if (!intel_PLL_is_valid(dev, limit,
624 &clock))
625 continue;
626
627 this_err = abs(clock.dot - target);
628 if (this_err < err_most) {
629 *best_clock = clock;
630 err_most = this_err;
631 max_n = clock.n;
632 found = true;
633 }
634 }
635 }
636 }
637 }
638 return found;
639 }
640
641 static bool
642 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
643 int target, int refclk, intel_clock_t *best_clock)
644 {
645 struct drm_device *dev = crtc->dev;
646 intel_clock_t clock;
647
648 if (target < 200000) {
649 clock.n = 1;
650 clock.p1 = 2;
651 clock.p2 = 10;
652 clock.m1 = 12;
653 clock.m2 = 9;
654 } else {
655 clock.n = 2;
656 clock.p1 = 1;
657 clock.p2 = 10;
658 clock.m1 = 14;
659 clock.m2 = 8;
660 }
661 intel_clock(dev, refclk, &clock);
662 memcpy(best_clock, &clock, sizeof(intel_clock_t));
663 return true;
664 }
665
666 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
667 static bool
668 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
669 int target, int refclk, intel_clock_t *best_clock)
670 {
671 intel_clock_t clock;
672 if (target < 200000) {
673 clock.p1 = 2;
674 clock.p2 = 10;
675 clock.n = 2;
676 clock.m1 = 23;
677 clock.m2 = 8;
678 } else {
679 clock.p1 = 1;
680 clock.p2 = 10;
681 clock.n = 1;
682 clock.m1 = 14;
683 clock.m2 = 2;
684 }
685 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
686 clock.p = (clock.p1 * clock.p2);
687 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
688 clock.vco = 0;
689 memcpy(best_clock, &clock, sizeof(intel_clock_t));
690 return true;
691 }
692
693 /**
694 * intel_wait_for_vblank - wait for vblank on a given pipe
695 * @dev: drm device
696 * @pipe: pipe to wait for
697 *
698 * Wait for vblank to occur on a given pipe. Needed for various bits of
699 * mode setting code.
700 */
701 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
702 {
703 struct drm_i915_private *dev_priv = dev->dev_private;
704 int pipestat_reg = PIPESTAT(pipe);
705
706 /* Clear existing vblank status. Note this will clear any other
707 * sticky status fields as well.
708 *
709 * This races with i915_driver_irq_handler() with the result
710 * that either function could miss a vblank event. Here it is not
711 * fatal, as we will either wait upon the next vblank interrupt or
712 * timeout. Generally speaking intel_wait_for_vblank() is only
713 * called during modeset at which time the GPU should be idle and
714 * should *not* be performing page flips and thus not waiting on
715 * vblanks...
716 * Currently, the result of us stealing a vblank from the irq
717 * handler is that a single frame will be skipped during swapbuffers.
718 */
719 I915_WRITE(pipestat_reg,
720 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
721
722 /* Wait for vblank interrupt bit to set */
723 if (wait_for(I915_READ(pipestat_reg) &
724 PIPE_VBLANK_INTERRUPT_STATUS,
725 50))
726 DRM_DEBUG_KMS("vblank wait timed out\n");
727 }
728
729 /*
730 * intel_wait_for_pipe_off - wait for pipe to turn off
731 * @dev: drm device
732 * @pipe: pipe to wait for
733 *
734 * After disabling a pipe, we can't wait for vblank in the usual way,
735 * spinning on the vblank interrupt status bit, since we won't actually
736 * see an interrupt when the pipe is disabled.
737 *
738 * On Gen4 and above:
739 * wait for the pipe register state bit to turn off
740 *
741 * Otherwise:
742 * wait for the display line value to settle (it usually
743 * ends up stopping at the start of the next frame).
744 *
745 */
746 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
747 {
748 struct drm_i915_private *dev_priv = dev->dev_private;
749
750 if (INTEL_INFO(dev)->gen >= 4) {
751 int reg = PIPECONF(pipe);
752
753 /* Wait for the Pipe State to go off */
754 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
755 100))
756 DRM_DEBUG_KMS("pipe_off wait timed out\n");
757 } else {
758 u32 last_line;
759 int reg = PIPEDSL(pipe);
760 unsigned long timeout = jiffies + msecs_to_jiffies(100);
761
762 /* Wait for the display line to settle */
763 do {
764 last_line = I915_READ(reg) & DSL_LINEMASK;
765 mdelay(5);
766 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
767 time_after(timeout, jiffies));
768 if (time_after(jiffies, timeout))
769 DRM_DEBUG_KMS("pipe_off wait timed out\n");
770 }
771 }
772
773 static const char *state_string(bool enabled)
774 {
775 return enabled ? "on" : "off";
776 }
777
778 /* Only for pre-ILK configs */
779 static void assert_pll(struct drm_i915_private *dev_priv,
780 enum pipe pipe, bool state)
781 {
782 int reg;
783 u32 val;
784 bool cur_state;
785
786 reg = DPLL(pipe);
787 val = I915_READ(reg);
788 cur_state = !!(val & DPLL_VCO_ENABLE);
789 WARN(cur_state != state,
790 "PLL state assertion failure (expected %s, current %s)\n",
791 state_string(state), state_string(cur_state));
792 }
793 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
794 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
795
796 /* For ILK+ */
797 static void assert_pch_pll(struct drm_i915_private *dev_priv,
798 enum pipe pipe, bool state)
799 {
800 int reg;
801 u32 val;
802 bool cur_state;
803
804 reg = PCH_DPLL(pipe);
805 val = I915_READ(reg);
806 cur_state = !!(val & DPLL_VCO_ENABLE);
807 WARN(cur_state != state,
808 "PCH PLL state assertion failure (expected %s, current %s)\n",
809 state_string(state), state_string(cur_state));
810 }
811 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
812 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
813
814 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
815 enum pipe pipe, bool state)
816 {
817 int reg;
818 u32 val;
819 bool cur_state;
820
821 reg = FDI_TX_CTL(pipe);
822 val = I915_READ(reg);
823 cur_state = !!(val & FDI_TX_ENABLE);
824 WARN(cur_state != state,
825 "FDI TX state assertion failure (expected %s, current %s)\n",
826 state_string(state), state_string(cur_state));
827 }
828 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
829 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
830
831 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
832 enum pipe pipe, bool state)
833 {
834 int reg;
835 u32 val;
836 bool cur_state;
837
838 reg = FDI_RX_CTL(pipe);
839 val = I915_READ(reg);
840 cur_state = !!(val & FDI_RX_ENABLE);
841 WARN(cur_state != state,
842 "FDI RX state assertion failure (expected %s, current %s)\n",
843 state_string(state), state_string(cur_state));
844 }
845 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
846 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
847
848 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
849 enum pipe pipe)
850 {
851 int reg;
852 u32 val;
853
854 /* ILK FDI PLL is always enabled */
855 if (dev_priv->info->gen == 5)
856 return;
857
858 reg = FDI_TX_CTL(pipe);
859 val = I915_READ(reg);
860 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
861 }
862
863 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
864 enum pipe pipe)
865 {
866 int reg;
867 u32 val;
868
869 reg = FDI_RX_CTL(pipe);
870 val = I915_READ(reg);
871 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
872 }
873
874 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
875 enum pipe pipe)
876 {
877 int pp_reg, lvds_reg;
878 u32 val;
879 enum pipe panel_pipe = PIPE_A;
880 bool locked = locked;
881
882 if (HAS_PCH_SPLIT(dev_priv->dev)) {
883 pp_reg = PCH_PP_CONTROL;
884 lvds_reg = PCH_LVDS;
885 } else {
886 pp_reg = PP_CONTROL;
887 lvds_reg = LVDS;
888 }
889
890 val = I915_READ(pp_reg);
891 if (!(val & PANEL_POWER_ON) ||
892 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
893 locked = false;
894
895 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
896 panel_pipe = PIPE_B;
897
898 WARN(panel_pipe == pipe && locked,
899 "panel assertion failure, pipe %c regs locked\n",
900 pipe_name(pipe));
901 }
902
903 static void assert_pipe(struct drm_i915_private *dev_priv,
904 enum pipe pipe, bool state)
905 {
906 int reg;
907 u32 val;
908 bool cur_state;
909
910 reg = PIPECONF(pipe);
911 val = I915_READ(reg);
912 cur_state = !!(val & PIPECONF_ENABLE);
913 WARN(cur_state != state,
914 "pipe %c assertion failure (expected %s, current %s)\n",
915 pipe_name(pipe), state_string(state), state_string(cur_state));
916 }
917 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
918 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
919
920 static void assert_plane_enabled(struct drm_i915_private *dev_priv,
921 enum plane plane)
922 {
923 int reg;
924 u32 val;
925
926 reg = DSPCNTR(plane);
927 val = I915_READ(reg);
928 WARN(!(val & DISPLAY_PLANE_ENABLE),
929 "plane %c assertion failure, should be active but is disabled\n",
930 plane_name(plane));
931 }
932
933 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
934 enum pipe pipe)
935 {
936 int reg, i;
937 u32 val;
938 int cur_pipe;
939
940 /* Planes are fixed to pipes on ILK+ */
941 if (HAS_PCH_SPLIT(dev_priv->dev))
942 return;
943
944 /* Need to check both planes against the pipe */
945 for (i = 0; i < 2; i++) {
946 reg = DSPCNTR(i);
947 val = I915_READ(reg);
948 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
949 DISPPLANE_SEL_PIPE_SHIFT;
950 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
951 "plane %c assertion failure, should be off on pipe %c but is still active\n",
952 plane_name(i), pipe_name(pipe));
953 }
954 }
955
956 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
957 {
958 u32 val;
959 bool enabled;
960
961 val = I915_READ(PCH_DREF_CONTROL);
962 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
963 DREF_SUPERSPREAD_SOURCE_MASK));
964 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
965 }
966
967 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
968 enum pipe pipe)
969 {
970 int reg;
971 u32 val;
972 bool enabled;
973
974 reg = TRANSCONF(pipe);
975 val = I915_READ(reg);
976 enabled = !!(val & TRANS_ENABLE);
977 WARN(enabled,
978 "transcoder assertion failed, should be off on pipe %c but is still active\n",
979 pipe_name(pipe));
980 }
981
982 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
983 enum pipe pipe, int reg)
984 {
985 u32 val = I915_READ(reg);
986 WARN(DP_PIPE_ENABLED(val, pipe),
987 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
988 reg, pipe_name(pipe));
989 }
990
991 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
992 enum pipe pipe, int reg)
993 {
994 u32 val = I915_READ(reg);
995 WARN(HDMI_PIPE_ENABLED(val, pipe),
996 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
997 reg, pipe_name(pipe));
998 }
999
1000 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1001 enum pipe pipe)
1002 {
1003 int reg;
1004 u32 val;
1005
1006 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B);
1007 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C);
1008 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D);
1009
1010 reg = PCH_ADPA;
1011 val = I915_READ(reg);
1012 WARN(ADPA_PIPE_ENABLED(val, pipe),
1013 "PCH VGA enabled on transcoder %c, should be disabled\n",
1014 pipe_name(pipe));
1015
1016 reg = PCH_LVDS;
1017 val = I915_READ(reg);
1018 WARN(LVDS_PIPE_ENABLED(val, pipe),
1019 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1020 pipe_name(pipe));
1021
1022 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1023 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1024 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1025 }
1026
1027 /**
1028 * intel_enable_pll - enable a PLL
1029 * @dev_priv: i915 private structure
1030 * @pipe: pipe PLL to enable
1031 *
1032 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1033 * make sure the PLL reg is writable first though, since the panel write
1034 * protect mechanism may be enabled.
1035 *
1036 * Note! This is for pre-ILK only.
1037 */
1038 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1039 {
1040 int reg;
1041 u32 val;
1042
1043 /* No really, not for ILK+ */
1044 BUG_ON(dev_priv->info->gen >= 5);
1045
1046 /* PLL is protected by panel, make sure we can write it */
1047 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1048 assert_panel_unlocked(dev_priv, pipe);
1049
1050 reg = DPLL(pipe);
1051 val = I915_READ(reg);
1052 val |= DPLL_VCO_ENABLE;
1053
1054 /* We do this three times for luck */
1055 I915_WRITE(reg, val);
1056 POSTING_READ(reg);
1057 udelay(150); /* wait for warmup */
1058 I915_WRITE(reg, val);
1059 POSTING_READ(reg);
1060 udelay(150); /* wait for warmup */
1061 I915_WRITE(reg, val);
1062 POSTING_READ(reg);
1063 udelay(150); /* wait for warmup */
1064 }
1065
1066 /**
1067 * intel_disable_pll - disable a PLL
1068 * @dev_priv: i915 private structure
1069 * @pipe: pipe PLL to disable
1070 *
1071 * Disable the PLL for @pipe, making sure the pipe is off first.
1072 *
1073 * Note! This is for pre-ILK only.
1074 */
1075 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1076 {
1077 int reg;
1078 u32 val;
1079
1080 /* Don't disable pipe A or pipe A PLLs if needed */
1081 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1082 return;
1083
1084 /* Make sure the pipe isn't still relying on us */
1085 assert_pipe_disabled(dev_priv, pipe);
1086
1087 reg = DPLL(pipe);
1088 val = I915_READ(reg);
1089 val &= ~DPLL_VCO_ENABLE;
1090 I915_WRITE(reg, val);
1091 POSTING_READ(reg);
1092 }
1093
1094 /**
1095 * intel_enable_pch_pll - enable PCH PLL
1096 * @dev_priv: i915 private structure
1097 * @pipe: pipe PLL to enable
1098 *
1099 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1100 * drives the transcoder clock.
1101 */
1102 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1103 enum pipe pipe)
1104 {
1105 int reg;
1106 u32 val;
1107
1108 /* PCH only available on ILK+ */
1109 BUG_ON(dev_priv->info->gen < 5);
1110
1111 /* PCH refclock must be enabled first */
1112 assert_pch_refclk_enabled(dev_priv);
1113
1114 reg = PCH_DPLL(pipe);
1115 val = I915_READ(reg);
1116 val |= DPLL_VCO_ENABLE;
1117 I915_WRITE(reg, val);
1118 POSTING_READ(reg);
1119 udelay(200);
1120 }
1121
1122 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1123 enum pipe pipe)
1124 {
1125 int reg;
1126 u32 val;
1127
1128 /* PCH only available on ILK+ */
1129 BUG_ON(dev_priv->info->gen < 5);
1130
1131 /* Make sure transcoder isn't still depending on us */
1132 assert_transcoder_disabled(dev_priv, pipe);
1133
1134 reg = PCH_DPLL(pipe);
1135 val = I915_READ(reg);
1136 val &= ~DPLL_VCO_ENABLE;
1137 I915_WRITE(reg, val);
1138 POSTING_READ(reg);
1139 udelay(200);
1140 }
1141
1142 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1143 enum pipe pipe)
1144 {
1145 int reg;
1146 u32 val;
1147
1148 /* PCH only available on ILK+ */
1149 BUG_ON(dev_priv->info->gen < 5);
1150
1151 /* Make sure PCH DPLL is enabled */
1152 assert_pch_pll_enabled(dev_priv, pipe);
1153
1154 /* FDI must be feeding us bits for PCH ports */
1155 assert_fdi_tx_enabled(dev_priv, pipe);
1156 assert_fdi_rx_enabled(dev_priv, pipe);
1157
1158 reg = TRANSCONF(pipe);
1159 val = I915_READ(reg);
1160 /*
1161 * make the BPC in transcoder be consistent with
1162 * that in pipeconf reg.
1163 */
1164 val &= ~PIPE_BPC_MASK;
1165 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1166 I915_WRITE(reg, val | TRANS_ENABLE);
1167 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1168 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1169 }
1170
1171 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1172 enum pipe pipe)
1173 {
1174 int reg;
1175 u32 val;
1176
1177 /* FDI relies on the transcoder */
1178 assert_fdi_tx_disabled(dev_priv, pipe);
1179 assert_fdi_rx_disabled(dev_priv, pipe);
1180
1181 /* Ports must be off as well */
1182 assert_pch_ports_disabled(dev_priv, pipe);
1183
1184 reg = TRANSCONF(pipe);
1185 val = I915_READ(reg);
1186 val &= ~TRANS_ENABLE;
1187 I915_WRITE(reg, val);
1188 /* wait for PCH transcoder off, transcoder state */
1189 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1190 DRM_ERROR("failed to disable transcoder\n");
1191 }
1192
1193 /**
1194 * intel_enable_pipe - enable a pipe, asserting requirements
1195 * @dev_priv: i915 private structure
1196 * @pipe: pipe to enable
1197 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1198 *
1199 * Enable @pipe, making sure that various hardware specific requirements
1200 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1201 *
1202 * @pipe should be %PIPE_A or %PIPE_B.
1203 *
1204 * Will wait until the pipe is actually running (i.e. first vblank) before
1205 * returning.
1206 */
1207 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1208 bool pch_port)
1209 {
1210 int reg;
1211 u32 val;
1212
1213 /*
1214 * A pipe without a PLL won't actually be able to drive bits from
1215 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1216 * need the check.
1217 */
1218 if (!HAS_PCH_SPLIT(dev_priv->dev))
1219 assert_pll_enabled(dev_priv, pipe);
1220 else {
1221 if (pch_port) {
1222 /* if driving the PCH, we need FDI enabled */
1223 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1224 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1225 }
1226 /* FIXME: assert CPU port conditions for SNB+ */
1227 }
1228
1229 reg = PIPECONF(pipe);
1230 val = I915_READ(reg);
1231 if (val & PIPECONF_ENABLE)
1232 return;
1233
1234 I915_WRITE(reg, val | PIPECONF_ENABLE);
1235 intel_wait_for_vblank(dev_priv->dev, pipe);
1236 }
1237
1238 /**
1239 * intel_disable_pipe - disable a pipe, asserting requirements
1240 * @dev_priv: i915 private structure
1241 * @pipe: pipe to disable
1242 *
1243 * Disable @pipe, making sure that various hardware specific requirements
1244 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1245 *
1246 * @pipe should be %PIPE_A or %PIPE_B.
1247 *
1248 * Will wait until the pipe has shut down before returning.
1249 */
1250 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1251 enum pipe pipe)
1252 {
1253 int reg;
1254 u32 val;
1255
1256 /*
1257 * Make sure planes won't keep trying to pump pixels to us,
1258 * or we might hang the display.
1259 */
1260 assert_planes_disabled(dev_priv, pipe);
1261
1262 /* Don't disable pipe A or pipe A PLLs if needed */
1263 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1264 return;
1265
1266 reg = PIPECONF(pipe);
1267 val = I915_READ(reg);
1268 if ((val & PIPECONF_ENABLE) == 0)
1269 return;
1270
1271 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1272 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1273 }
1274
1275 /**
1276 * intel_enable_plane - enable a display plane on a given pipe
1277 * @dev_priv: i915 private structure
1278 * @plane: plane to enable
1279 * @pipe: pipe being fed
1280 *
1281 * Enable @plane on @pipe, making sure that @pipe is running first.
1282 */
1283 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1284 enum plane plane, enum pipe pipe)
1285 {
1286 int reg;
1287 u32 val;
1288
1289 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1290 assert_pipe_enabled(dev_priv, pipe);
1291
1292 reg = DSPCNTR(plane);
1293 val = I915_READ(reg);
1294 if (val & DISPLAY_PLANE_ENABLE)
1295 return;
1296
1297 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1298 intel_wait_for_vblank(dev_priv->dev, pipe);
1299 }
1300
1301 /*
1302 * Plane regs are double buffered, going from enabled->disabled needs a
1303 * trigger in order to latch. The display address reg provides this.
1304 */
1305 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1306 enum plane plane)
1307 {
1308 u32 reg = DSPADDR(plane);
1309 I915_WRITE(reg, I915_READ(reg));
1310 }
1311
1312 /**
1313 * intel_disable_plane - disable a display plane
1314 * @dev_priv: i915 private structure
1315 * @plane: plane to disable
1316 * @pipe: pipe consuming the data
1317 *
1318 * Disable @plane; should be an independent operation.
1319 */
1320 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1321 enum plane plane, enum pipe pipe)
1322 {
1323 int reg;
1324 u32 val;
1325
1326 reg = DSPCNTR(plane);
1327 val = I915_READ(reg);
1328 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1329 return;
1330
1331 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1332 intel_flush_display_plane(dev_priv, plane);
1333 intel_wait_for_vblank(dev_priv->dev, pipe);
1334 }
1335
1336 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1337 enum pipe pipe, int reg)
1338 {
1339 u32 val = I915_READ(reg);
1340 if (DP_PIPE_ENABLED(val, pipe))
1341 I915_WRITE(reg, val & ~DP_PORT_EN);
1342 }
1343
1344 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1345 enum pipe pipe, int reg)
1346 {
1347 u32 val = I915_READ(reg);
1348 if (HDMI_PIPE_ENABLED(val, pipe))
1349 I915_WRITE(reg, val & ~PORT_ENABLE);
1350 }
1351
1352 /* Disable any ports connected to this transcoder */
1353 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1354 enum pipe pipe)
1355 {
1356 u32 reg, val;
1357
1358 val = I915_READ(PCH_PP_CONTROL);
1359 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1360
1361 disable_pch_dp(dev_priv, pipe, PCH_DP_B);
1362 disable_pch_dp(dev_priv, pipe, PCH_DP_C);
1363 disable_pch_dp(dev_priv, pipe, PCH_DP_D);
1364
1365 reg = PCH_ADPA;
1366 val = I915_READ(reg);
1367 if (ADPA_PIPE_ENABLED(val, pipe))
1368 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1369
1370 reg = PCH_LVDS;
1371 val = I915_READ(reg);
1372 if (LVDS_PIPE_ENABLED(val, pipe)) {
1373 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1374 POSTING_READ(reg);
1375 udelay(100);
1376 }
1377
1378 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1379 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1380 disable_pch_hdmi(dev_priv, pipe, HDMID);
1381 }
1382
1383 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1384 {
1385 struct drm_device *dev = crtc->dev;
1386 struct drm_i915_private *dev_priv = dev->dev_private;
1387 struct drm_framebuffer *fb = crtc->fb;
1388 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1389 struct drm_i915_gem_object *obj = intel_fb->obj;
1390 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1391 int plane, i;
1392 u32 fbc_ctl, fbc_ctl2;
1393
1394 if (fb->pitch == dev_priv->cfb_pitch &&
1395 obj->fence_reg == dev_priv->cfb_fence &&
1396 intel_crtc->plane == dev_priv->cfb_plane &&
1397 I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1398 return;
1399
1400 i8xx_disable_fbc(dev);
1401
1402 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1403
1404 if (fb->pitch < dev_priv->cfb_pitch)
1405 dev_priv->cfb_pitch = fb->pitch;
1406
1407 /* FBC_CTL wants 64B units */
1408 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1409 dev_priv->cfb_fence = obj->fence_reg;
1410 dev_priv->cfb_plane = intel_crtc->plane;
1411 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1412
1413 /* Clear old tags */
1414 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1415 I915_WRITE(FBC_TAG + (i * 4), 0);
1416
1417 /* Set it up... */
1418 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1419 if (obj->tiling_mode != I915_TILING_NONE)
1420 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1421 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1422 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1423
1424 /* enable it... */
1425 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1426 if (IS_I945GM(dev))
1427 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1428 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1429 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1430 if (obj->tiling_mode != I915_TILING_NONE)
1431 fbc_ctl |= dev_priv->cfb_fence;
1432 I915_WRITE(FBC_CONTROL, fbc_ctl);
1433
1434 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1435 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1436 }
1437
1438 void i8xx_disable_fbc(struct drm_device *dev)
1439 {
1440 struct drm_i915_private *dev_priv = dev->dev_private;
1441 u32 fbc_ctl;
1442
1443 /* Disable compression */
1444 fbc_ctl = I915_READ(FBC_CONTROL);
1445 if ((fbc_ctl & FBC_CTL_EN) == 0)
1446 return;
1447
1448 fbc_ctl &= ~FBC_CTL_EN;
1449 I915_WRITE(FBC_CONTROL, fbc_ctl);
1450
1451 /* Wait for compressing bit to clear */
1452 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1453 DRM_DEBUG_KMS("FBC idle timed out\n");
1454 return;
1455 }
1456
1457 DRM_DEBUG_KMS("disabled FBC\n");
1458 }
1459
1460 static bool i8xx_fbc_enabled(struct drm_device *dev)
1461 {
1462 struct drm_i915_private *dev_priv = dev->dev_private;
1463
1464 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1465 }
1466
1467 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1468 {
1469 struct drm_device *dev = crtc->dev;
1470 struct drm_i915_private *dev_priv = dev->dev_private;
1471 struct drm_framebuffer *fb = crtc->fb;
1472 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1473 struct drm_i915_gem_object *obj = intel_fb->obj;
1474 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1475 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1476 unsigned long stall_watermark = 200;
1477 u32 dpfc_ctl;
1478
1479 dpfc_ctl = I915_READ(DPFC_CONTROL);
1480 if (dpfc_ctl & DPFC_CTL_EN) {
1481 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1482 dev_priv->cfb_fence == obj->fence_reg &&
1483 dev_priv->cfb_plane == intel_crtc->plane &&
1484 dev_priv->cfb_y == crtc->y)
1485 return;
1486
1487 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1488 intel_wait_for_vblank(dev, intel_crtc->pipe);
1489 }
1490
1491 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1492 dev_priv->cfb_fence = obj->fence_reg;
1493 dev_priv->cfb_plane = intel_crtc->plane;
1494 dev_priv->cfb_y = crtc->y;
1495
1496 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1497 if (obj->tiling_mode != I915_TILING_NONE) {
1498 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1499 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1500 } else {
1501 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1502 }
1503
1504 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1505 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1506 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1507 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1508
1509 /* enable it... */
1510 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1511
1512 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1513 }
1514
1515 void g4x_disable_fbc(struct drm_device *dev)
1516 {
1517 struct drm_i915_private *dev_priv = dev->dev_private;
1518 u32 dpfc_ctl;
1519
1520 /* Disable compression */
1521 dpfc_ctl = I915_READ(DPFC_CONTROL);
1522 if (dpfc_ctl & DPFC_CTL_EN) {
1523 dpfc_ctl &= ~DPFC_CTL_EN;
1524 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1525
1526 DRM_DEBUG_KMS("disabled FBC\n");
1527 }
1528 }
1529
1530 static bool g4x_fbc_enabled(struct drm_device *dev)
1531 {
1532 struct drm_i915_private *dev_priv = dev->dev_private;
1533
1534 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1535 }
1536
1537 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1538 {
1539 struct drm_i915_private *dev_priv = dev->dev_private;
1540 u32 blt_ecoskpd;
1541
1542 /* Make sure blitter notifies FBC of writes */
1543 gen6_gt_force_wake_get(dev_priv);
1544 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1545 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1546 GEN6_BLITTER_LOCK_SHIFT;
1547 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1548 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1549 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1550 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1551 GEN6_BLITTER_LOCK_SHIFT);
1552 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1553 POSTING_READ(GEN6_BLITTER_ECOSKPD);
1554 gen6_gt_force_wake_put(dev_priv);
1555 }
1556
1557 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1558 {
1559 struct drm_device *dev = crtc->dev;
1560 struct drm_i915_private *dev_priv = dev->dev_private;
1561 struct drm_framebuffer *fb = crtc->fb;
1562 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1563 struct drm_i915_gem_object *obj = intel_fb->obj;
1564 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1565 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1566 unsigned long stall_watermark = 200;
1567 u32 dpfc_ctl;
1568
1569 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1570 if (dpfc_ctl & DPFC_CTL_EN) {
1571 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1572 dev_priv->cfb_fence == obj->fence_reg &&
1573 dev_priv->cfb_plane == intel_crtc->plane &&
1574 dev_priv->cfb_offset == obj->gtt_offset &&
1575 dev_priv->cfb_y == crtc->y)
1576 return;
1577
1578 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1579 intel_wait_for_vblank(dev, intel_crtc->pipe);
1580 }
1581
1582 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1583 dev_priv->cfb_fence = obj->fence_reg;
1584 dev_priv->cfb_plane = intel_crtc->plane;
1585 dev_priv->cfb_offset = obj->gtt_offset;
1586 dev_priv->cfb_y = crtc->y;
1587
1588 dpfc_ctl &= DPFC_RESERVED;
1589 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1590 if (obj->tiling_mode != I915_TILING_NONE) {
1591 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1592 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1593 } else {
1594 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1595 }
1596
1597 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1598 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1599 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1600 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1601 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1602 /* enable it... */
1603 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1604
1605 if (IS_GEN6(dev)) {
1606 I915_WRITE(SNB_DPFC_CTL_SA,
1607 SNB_CPU_FENCE_ENABLE | dev_priv->cfb_fence);
1608 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1609 sandybridge_blit_fbc_update(dev);
1610 }
1611
1612 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1613 }
1614
1615 void ironlake_disable_fbc(struct drm_device *dev)
1616 {
1617 struct drm_i915_private *dev_priv = dev->dev_private;
1618 u32 dpfc_ctl;
1619
1620 /* Disable compression */
1621 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1622 if (dpfc_ctl & DPFC_CTL_EN) {
1623 dpfc_ctl &= ~DPFC_CTL_EN;
1624 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1625
1626 DRM_DEBUG_KMS("disabled FBC\n");
1627 }
1628 }
1629
1630 static bool ironlake_fbc_enabled(struct drm_device *dev)
1631 {
1632 struct drm_i915_private *dev_priv = dev->dev_private;
1633
1634 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1635 }
1636
1637 bool intel_fbc_enabled(struct drm_device *dev)
1638 {
1639 struct drm_i915_private *dev_priv = dev->dev_private;
1640
1641 if (!dev_priv->display.fbc_enabled)
1642 return false;
1643
1644 return dev_priv->display.fbc_enabled(dev);
1645 }
1646
1647 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1648 {
1649 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1650
1651 if (!dev_priv->display.enable_fbc)
1652 return;
1653
1654 dev_priv->display.enable_fbc(crtc, interval);
1655 }
1656
1657 void intel_disable_fbc(struct drm_device *dev)
1658 {
1659 struct drm_i915_private *dev_priv = dev->dev_private;
1660
1661 if (!dev_priv->display.disable_fbc)
1662 return;
1663
1664 dev_priv->display.disable_fbc(dev);
1665 }
1666
1667 /**
1668 * intel_update_fbc - enable/disable FBC as needed
1669 * @dev: the drm_device
1670 *
1671 * Set up the framebuffer compression hardware at mode set time. We
1672 * enable it if possible:
1673 * - plane A only (on pre-965)
1674 * - no pixel mulitply/line duplication
1675 * - no alpha buffer discard
1676 * - no dual wide
1677 * - framebuffer <= 2048 in width, 1536 in height
1678 *
1679 * We can't assume that any compression will take place (worst case),
1680 * so the compressed buffer has to be the same size as the uncompressed
1681 * one. It also must reside (along with the line length buffer) in
1682 * stolen memory.
1683 *
1684 * We need to enable/disable FBC on a global basis.
1685 */
1686 static void intel_update_fbc(struct drm_device *dev)
1687 {
1688 struct drm_i915_private *dev_priv = dev->dev_private;
1689 struct drm_crtc *crtc = NULL, *tmp_crtc;
1690 struct intel_crtc *intel_crtc;
1691 struct drm_framebuffer *fb;
1692 struct intel_framebuffer *intel_fb;
1693 struct drm_i915_gem_object *obj;
1694
1695 DRM_DEBUG_KMS("\n");
1696
1697 if (!i915_powersave)
1698 return;
1699
1700 if (!I915_HAS_FBC(dev))
1701 return;
1702
1703 /*
1704 * If FBC is already on, we just have to verify that we can
1705 * keep it that way...
1706 * Need to disable if:
1707 * - more than one pipe is active
1708 * - changing FBC params (stride, fence, mode)
1709 * - new fb is too large to fit in compressed buffer
1710 * - going to an unsupported config (interlace, pixel multiply, etc.)
1711 */
1712 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1713 if (tmp_crtc->enabled && tmp_crtc->fb) {
1714 if (crtc) {
1715 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1716 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1717 goto out_disable;
1718 }
1719 crtc = tmp_crtc;
1720 }
1721 }
1722
1723 if (!crtc || crtc->fb == NULL) {
1724 DRM_DEBUG_KMS("no output, disabling\n");
1725 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1726 goto out_disable;
1727 }
1728
1729 intel_crtc = to_intel_crtc(crtc);
1730 fb = crtc->fb;
1731 intel_fb = to_intel_framebuffer(fb);
1732 obj = intel_fb->obj;
1733
1734 if (!i915_enable_fbc) {
1735 DRM_DEBUG_KMS("fbc disabled per module param (default off)\n");
1736 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1737 goto out_disable;
1738 }
1739 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1740 DRM_DEBUG_KMS("framebuffer too large, disabling "
1741 "compression\n");
1742 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1743 goto out_disable;
1744 }
1745 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1746 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1747 DRM_DEBUG_KMS("mode incompatible with compression, "
1748 "disabling\n");
1749 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1750 goto out_disable;
1751 }
1752 if ((crtc->mode.hdisplay > 2048) ||
1753 (crtc->mode.vdisplay > 1536)) {
1754 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1755 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1756 goto out_disable;
1757 }
1758 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1759 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1760 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1761 goto out_disable;
1762 }
1763 if (obj->tiling_mode != I915_TILING_X) {
1764 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1765 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1766 goto out_disable;
1767 }
1768
1769 /* If the kernel debugger is active, always disable compression */
1770 if (in_dbg_master())
1771 goto out_disable;
1772
1773 intel_enable_fbc(crtc, 500);
1774 return;
1775
1776 out_disable:
1777 /* Multiple disables should be harmless */
1778 if (intel_fbc_enabled(dev)) {
1779 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1780 intel_disable_fbc(dev);
1781 }
1782 }
1783
1784 int
1785 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1786 struct drm_i915_gem_object *obj,
1787 struct intel_ring_buffer *pipelined)
1788 {
1789 struct drm_i915_private *dev_priv = dev->dev_private;
1790 u32 alignment;
1791 int ret;
1792
1793 switch (obj->tiling_mode) {
1794 case I915_TILING_NONE:
1795 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1796 alignment = 128 * 1024;
1797 else if (INTEL_INFO(dev)->gen >= 4)
1798 alignment = 4 * 1024;
1799 else
1800 alignment = 64 * 1024;
1801 break;
1802 case I915_TILING_X:
1803 /* pin() will align the object as required by fence */
1804 alignment = 0;
1805 break;
1806 case I915_TILING_Y:
1807 /* FIXME: Is this true? */
1808 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1809 return -EINVAL;
1810 default:
1811 BUG();
1812 }
1813
1814 dev_priv->mm.interruptible = false;
1815 ret = i915_gem_object_pin(obj, alignment, true);
1816 if (ret)
1817 goto err_interruptible;
1818
1819 ret = i915_gem_object_set_to_display_plane(obj, pipelined);
1820 if (ret)
1821 goto err_unpin;
1822
1823 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1824 * fence, whereas 965+ only requires a fence if using
1825 * framebuffer compression. For simplicity, we always install
1826 * a fence as the cost is not that onerous.
1827 */
1828 if (obj->tiling_mode != I915_TILING_NONE) {
1829 ret = i915_gem_object_get_fence(obj, pipelined);
1830 if (ret)
1831 goto err_unpin;
1832 }
1833
1834 dev_priv->mm.interruptible = true;
1835 return 0;
1836
1837 err_unpin:
1838 i915_gem_object_unpin(obj);
1839 err_interruptible:
1840 dev_priv->mm.interruptible = true;
1841 return ret;
1842 }
1843
1844 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1845 static int
1846 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1847 int x, int y, enum mode_set_atomic state)
1848 {
1849 struct drm_device *dev = crtc->dev;
1850 struct drm_i915_private *dev_priv = dev->dev_private;
1851 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1852 struct intel_framebuffer *intel_fb;
1853 struct drm_i915_gem_object *obj;
1854 int plane = intel_crtc->plane;
1855 unsigned long Start, Offset;
1856 u32 dspcntr;
1857 u32 reg;
1858
1859 switch (plane) {
1860 case 0:
1861 case 1:
1862 break;
1863 default:
1864 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1865 return -EINVAL;
1866 }
1867
1868 intel_fb = to_intel_framebuffer(fb);
1869 obj = intel_fb->obj;
1870
1871 reg = DSPCNTR(plane);
1872 dspcntr = I915_READ(reg);
1873 /* Mask out pixel format bits in case we change it */
1874 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1875 switch (fb->bits_per_pixel) {
1876 case 8:
1877 dspcntr |= DISPPLANE_8BPP;
1878 break;
1879 case 16:
1880 if (fb->depth == 15)
1881 dspcntr |= DISPPLANE_15_16BPP;
1882 else
1883 dspcntr |= DISPPLANE_16BPP;
1884 break;
1885 case 24:
1886 case 32:
1887 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1888 break;
1889 default:
1890 DRM_ERROR("Unknown color depth\n");
1891 return -EINVAL;
1892 }
1893 if (INTEL_INFO(dev)->gen >= 4) {
1894 if (obj->tiling_mode != I915_TILING_NONE)
1895 dspcntr |= DISPPLANE_TILED;
1896 else
1897 dspcntr &= ~DISPPLANE_TILED;
1898 }
1899
1900 if (HAS_PCH_SPLIT(dev))
1901 /* must disable */
1902 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1903
1904 I915_WRITE(reg, dspcntr);
1905
1906 Start = obj->gtt_offset;
1907 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1908
1909 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1910 Start, Offset, x, y, fb->pitch);
1911 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
1912 if (INTEL_INFO(dev)->gen >= 4) {
1913 I915_WRITE(DSPSURF(plane), Start);
1914 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1915 I915_WRITE(DSPADDR(plane), Offset);
1916 } else
1917 I915_WRITE(DSPADDR(plane), Start + Offset);
1918 POSTING_READ(reg);
1919
1920 intel_update_fbc(dev);
1921 intel_increase_pllclock(crtc);
1922
1923 return 0;
1924 }
1925
1926 static int
1927 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1928 struct drm_framebuffer *old_fb)
1929 {
1930 struct drm_device *dev = crtc->dev;
1931 struct drm_i915_master_private *master_priv;
1932 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1933 int ret;
1934
1935 /* no fb bound */
1936 if (!crtc->fb) {
1937 DRM_DEBUG_KMS("No FB bound\n");
1938 return 0;
1939 }
1940
1941 switch (intel_crtc->plane) {
1942 case 0:
1943 case 1:
1944 break;
1945 default:
1946 return -EINVAL;
1947 }
1948
1949 mutex_lock(&dev->struct_mutex);
1950 ret = intel_pin_and_fence_fb_obj(dev,
1951 to_intel_framebuffer(crtc->fb)->obj,
1952 NULL);
1953 if (ret != 0) {
1954 mutex_unlock(&dev->struct_mutex);
1955 return ret;
1956 }
1957
1958 if (old_fb) {
1959 struct drm_i915_private *dev_priv = dev->dev_private;
1960 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1961
1962 wait_event(dev_priv->pending_flip_queue,
1963 atomic_read(&dev_priv->mm.wedged) ||
1964 atomic_read(&obj->pending_flip) == 0);
1965
1966 /* Big Hammer, we also need to ensure that any pending
1967 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1968 * current scanout is retired before unpinning the old
1969 * framebuffer.
1970 *
1971 * This should only fail upon a hung GPU, in which case we
1972 * can safely continue.
1973 */
1974 ret = i915_gem_object_flush_gpu(obj);
1975 (void) ret;
1976 }
1977
1978 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
1979 LEAVE_ATOMIC_MODE_SET);
1980 if (ret) {
1981 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
1982 mutex_unlock(&dev->struct_mutex);
1983 return ret;
1984 }
1985
1986 if (old_fb) {
1987 intel_wait_for_vblank(dev, intel_crtc->pipe);
1988 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
1989 }
1990
1991 mutex_unlock(&dev->struct_mutex);
1992
1993 if (!dev->primary->master)
1994 return 0;
1995
1996 master_priv = dev->primary->master->driver_priv;
1997 if (!master_priv->sarea_priv)
1998 return 0;
1999
2000 if (intel_crtc->pipe) {
2001 master_priv->sarea_priv->pipeB_x = x;
2002 master_priv->sarea_priv->pipeB_y = y;
2003 } else {
2004 master_priv->sarea_priv->pipeA_x = x;
2005 master_priv->sarea_priv->pipeA_y = y;
2006 }
2007
2008 return 0;
2009 }
2010
2011 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2012 {
2013 struct drm_device *dev = crtc->dev;
2014 struct drm_i915_private *dev_priv = dev->dev_private;
2015 u32 dpa_ctl;
2016
2017 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2018 dpa_ctl = I915_READ(DP_A);
2019 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2020
2021 if (clock < 200000) {
2022 u32 temp;
2023 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2024 /* workaround for 160Mhz:
2025 1) program 0x4600c bits 15:0 = 0x8124
2026 2) program 0x46010 bit 0 = 1
2027 3) program 0x46034 bit 24 = 1
2028 4) program 0x64000 bit 14 = 1
2029 */
2030 temp = I915_READ(0x4600c);
2031 temp &= 0xffff0000;
2032 I915_WRITE(0x4600c, temp | 0x8124);
2033
2034 temp = I915_READ(0x46010);
2035 I915_WRITE(0x46010, temp | 1);
2036
2037 temp = I915_READ(0x46034);
2038 I915_WRITE(0x46034, temp | (1 << 24));
2039 } else {
2040 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2041 }
2042 I915_WRITE(DP_A, dpa_ctl);
2043
2044 POSTING_READ(DP_A);
2045 udelay(500);
2046 }
2047
2048 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2049 {
2050 struct drm_device *dev = crtc->dev;
2051 struct drm_i915_private *dev_priv = dev->dev_private;
2052 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2053 int pipe = intel_crtc->pipe;
2054 u32 reg, temp;
2055
2056 /* enable normal train */
2057 reg = FDI_TX_CTL(pipe);
2058 temp = I915_READ(reg);
2059 if (IS_IVYBRIDGE(dev)) {
2060 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2061 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2062 } else {
2063 temp &= ~FDI_LINK_TRAIN_NONE;
2064 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2065 }
2066 I915_WRITE(reg, temp);
2067
2068 reg = FDI_RX_CTL(pipe);
2069 temp = I915_READ(reg);
2070 if (HAS_PCH_CPT(dev)) {
2071 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2072 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2073 } else {
2074 temp &= ~FDI_LINK_TRAIN_NONE;
2075 temp |= FDI_LINK_TRAIN_NONE;
2076 }
2077 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2078
2079 /* wait one idle pattern time */
2080 POSTING_READ(reg);
2081 udelay(1000);
2082
2083 /* IVB wants error correction enabled */
2084 if (IS_IVYBRIDGE(dev))
2085 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2086 FDI_FE_ERRC_ENABLE);
2087 }
2088
2089 /* The FDI link training functions for ILK/Ibexpeak. */
2090 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2091 {
2092 struct drm_device *dev = crtc->dev;
2093 struct drm_i915_private *dev_priv = dev->dev_private;
2094 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2095 int pipe = intel_crtc->pipe;
2096 int plane = intel_crtc->plane;
2097 u32 reg, temp, tries;
2098
2099 /* FDI needs bits from pipe & plane first */
2100 assert_pipe_enabled(dev_priv, pipe);
2101 assert_plane_enabled(dev_priv, plane);
2102
2103 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2104 for train result */
2105 reg = FDI_RX_IMR(pipe);
2106 temp = I915_READ(reg);
2107 temp &= ~FDI_RX_SYMBOL_LOCK;
2108 temp &= ~FDI_RX_BIT_LOCK;
2109 I915_WRITE(reg, temp);
2110 I915_READ(reg);
2111 udelay(150);
2112
2113 /* enable CPU FDI TX and PCH FDI RX */
2114 reg = FDI_TX_CTL(pipe);
2115 temp = I915_READ(reg);
2116 temp &= ~(7 << 19);
2117 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2118 temp &= ~FDI_LINK_TRAIN_NONE;
2119 temp |= FDI_LINK_TRAIN_PATTERN_1;
2120 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2121
2122 reg = FDI_RX_CTL(pipe);
2123 temp = I915_READ(reg);
2124 temp &= ~FDI_LINK_TRAIN_NONE;
2125 temp |= FDI_LINK_TRAIN_PATTERN_1;
2126 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2127
2128 POSTING_READ(reg);
2129 udelay(150);
2130
2131 /* Ironlake workaround, enable clock pointer after FDI enable*/
2132 if (HAS_PCH_IBX(dev)) {
2133 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2134 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2135 FDI_RX_PHASE_SYNC_POINTER_EN);
2136 }
2137
2138 reg = FDI_RX_IIR(pipe);
2139 for (tries = 0; tries < 5; tries++) {
2140 temp = I915_READ(reg);
2141 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2142
2143 if ((temp & FDI_RX_BIT_LOCK)) {
2144 DRM_DEBUG_KMS("FDI train 1 done.\n");
2145 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2146 break;
2147 }
2148 }
2149 if (tries == 5)
2150 DRM_ERROR("FDI train 1 fail!\n");
2151
2152 /* Train 2 */
2153 reg = FDI_TX_CTL(pipe);
2154 temp = I915_READ(reg);
2155 temp &= ~FDI_LINK_TRAIN_NONE;
2156 temp |= FDI_LINK_TRAIN_PATTERN_2;
2157 I915_WRITE(reg, temp);
2158
2159 reg = FDI_RX_CTL(pipe);
2160 temp = I915_READ(reg);
2161 temp &= ~FDI_LINK_TRAIN_NONE;
2162 temp |= FDI_LINK_TRAIN_PATTERN_2;
2163 I915_WRITE(reg, temp);
2164
2165 POSTING_READ(reg);
2166 udelay(150);
2167
2168 reg = FDI_RX_IIR(pipe);
2169 for (tries = 0; tries < 5; tries++) {
2170 temp = I915_READ(reg);
2171 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2172
2173 if (temp & FDI_RX_SYMBOL_LOCK) {
2174 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2175 DRM_DEBUG_KMS("FDI train 2 done.\n");
2176 break;
2177 }
2178 }
2179 if (tries == 5)
2180 DRM_ERROR("FDI train 2 fail!\n");
2181
2182 DRM_DEBUG_KMS("FDI train done\n");
2183
2184 }
2185
2186 static const int snb_b_fdi_train_param [] = {
2187 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2188 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2189 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2190 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2191 };
2192
2193 /* The FDI link training functions for SNB/Cougarpoint. */
2194 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2195 {
2196 struct drm_device *dev = crtc->dev;
2197 struct drm_i915_private *dev_priv = dev->dev_private;
2198 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2199 int pipe = intel_crtc->pipe;
2200 u32 reg, temp, i;
2201
2202 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2203 for train result */
2204 reg = FDI_RX_IMR(pipe);
2205 temp = I915_READ(reg);
2206 temp &= ~FDI_RX_SYMBOL_LOCK;
2207 temp &= ~FDI_RX_BIT_LOCK;
2208 I915_WRITE(reg, temp);
2209
2210 POSTING_READ(reg);
2211 udelay(150);
2212
2213 /* enable CPU FDI TX and PCH FDI RX */
2214 reg = FDI_TX_CTL(pipe);
2215 temp = I915_READ(reg);
2216 temp &= ~(7 << 19);
2217 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2218 temp &= ~FDI_LINK_TRAIN_NONE;
2219 temp |= FDI_LINK_TRAIN_PATTERN_1;
2220 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2221 /* SNB-B */
2222 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2223 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2224
2225 reg = FDI_RX_CTL(pipe);
2226 temp = I915_READ(reg);
2227 if (HAS_PCH_CPT(dev)) {
2228 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2229 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2230 } else {
2231 temp &= ~FDI_LINK_TRAIN_NONE;
2232 temp |= FDI_LINK_TRAIN_PATTERN_1;
2233 }
2234 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2235
2236 POSTING_READ(reg);
2237 udelay(150);
2238
2239 for (i = 0; i < 4; i++ ) {
2240 reg = FDI_TX_CTL(pipe);
2241 temp = I915_READ(reg);
2242 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2243 temp |= snb_b_fdi_train_param[i];
2244 I915_WRITE(reg, temp);
2245
2246 POSTING_READ(reg);
2247 udelay(500);
2248
2249 reg = FDI_RX_IIR(pipe);
2250 temp = I915_READ(reg);
2251 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2252
2253 if (temp & FDI_RX_BIT_LOCK) {
2254 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2255 DRM_DEBUG_KMS("FDI train 1 done.\n");
2256 break;
2257 }
2258 }
2259 if (i == 4)
2260 DRM_ERROR("FDI train 1 fail!\n");
2261
2262 /* Train 2 */
2263 reg = FDI_TX_CTL(pipe);
2264 temp = I915_READ(reg);
2265 temp &= ~FDI_LINK_TRAIN_NONE;
2266 temp |= FDI_LINK_TRAIN_PATTERN_2;
2267 if (IS_GEN6(dev)) {
2268 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2269 /* SNB-B */
2270 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2271 }
2272 I915_WRITE(reg, temp);
2273
2274 reg = FDI_RX_CTL(pipe);
2275 temp = I915_READ(reg);
2276 if (HAS_PCH_CPT(dev)) {
2277 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2278 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2279 } else {
2280 temp &= ~FDI_LINK_TRAIN_NONE;
2281 temp |= FDI_LINK_TRAIN_PATTERN_2;
2282 }
2283 I915_WRITE(reg, temp);
2284
2285 POSTING_READ(reg);
2286 udelay(150);
2287
2288 for (i = 0; i < 4; i++ ) {
2289 reg = FDI_TX_CTL(pipe);
2290 temp = I915_READ(reg);
2291 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2292 temp |= snb_b_fdi_train_param[i];
2293 I915_WRITE(reg, temp);
2294
2295 POSTING_READ(reg);
2296 udelay(500);
2297
2298 reg = FDI_RX_IIR(pipe);
2299 temp = I915_READ(reg);
2300 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2301
2302 if (temp & FDI_RX_SYMBOL_LOCK) {
2303 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2304 DRM_DEBUG_KMS("FDI train 2 done.\n");
2305 break;
2306 }
2307 }
2308 if (i == 4)
2309 DRM_ERROR("FDI train 2 fail!\n");
2310
2311 DRM_DEBUG_KMS("FDI train done.\n");
2312 }
2313
2314 /* Manual link training for Ivy Bridge A0 parts */
2315 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2316 {
2317 struct drm_device *dev = crtc->dev;
2318 struct drm_i915_private *dev_priv = dev->dev_private;
2319 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2320 int pipe = intel_crtc->pipe;
2321 u32 reg, temp, i;
2322
2323 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2324 for train result */
2325 reg = FDI_RX_IMR(pipe);
2326 temp = I915_READ(reg);
2327 temp &= ~FDI_RX_SYMBOL_LOCK;
2328 temp &= ~FDI_RX_BIT_LOCK;
2329 I915_WRITE(reg, temp);
2330
2331 POSTING_READ(reg);
2332 udelay(150);
2333
2334 /* enable CPU FDI TX and PCH FDI RX */
2335 reg = FDI_TX_CTL(pipe);
2336 temp = I915_READ(reg);
2337 temp &= ~(7 << 19);
2338 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2339 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2340 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2341 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2342 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2343 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2344
2345 reg = FDI_RX_CTL(pipe);
2346 temp = I915_READ(reg);
2347 temp &= ~FDI_LINK_TRAIN_AUTO;
2348 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2349 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2350 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2351
2352 POSTING_READ(reg);
2353 udelay(150);
2354
2355 for (i = 0; i < 4; i++ ) {
2356 reg = FDI_TX_CTL(pipe);
2357 temp = I915_READ(reg);
2358 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2359 temp |= snb_b_fdi_train_param[i];
2360 I915_WRITE(reg, temp);
2361
2362 POSTING_READ(reg);
2363 udelay(500);
2364
2365 reg = FDI_RX_IIR(pipe);
2366 temp = I915_READ(reg);
2367 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2368
2369 if (temp & FDI_RX_BIT_LOCK ||
2370 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2371 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2372 DRM_DEBUG_KMS("FDI train 1 done.\n");
2373 break;
2374 }
2375 }
2376 if (i == 4)
2377 DRM_ERROR("FDI train 1 fail!\n");
2378
2379 /* Train 2 */
2380 reg = FDI_TX_CTL(pipe);
2381 temp = I915_READ(reg);
2382 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2383 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2384 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2385 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2386 I915_WRITE(reg, temp);
2387
2388 reg = FDI_RX_CTL(pipe);
2389 temp = I915_READ(reg);
2390 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2391 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2392 I915_WRITE(reg, temp);
2393
2394 POSTING_READ(reg);
2395 udelay(150);
2396
2397 for (i = 0; i < 4; i++ ) {
2398 reg = FDI_TX_CTL(pipe);
2399 temp = I915_READ(reg);
2400 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2401 temp |= snb_b_fdi_train_param[i];
2402 I915_WRITE(reg, temp);
2403
2404 POSTING_READ(reg);
2405 udelay(500);
2406
2407 reg = FDI_RX_IIR(pipe);
2408 temp = I915_READ(reg);
2409 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2410
2411 if (temp & FDI_RX_SYMBOL_LOCK) {
2412 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2413 DRM_DEBUG_KMS("FDI train 2 done.\n");
2414 break;
2415 }
2416 }
2417 if (i == 4)
2418 DRM_ERROR("FDI train 2 fail!\n");
2419
2420 DRM_DEBUG_KMS("FDI train done.\n");
2421 }
2422
2423 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2424 {
2425 struct drm_device *dev = crtc->dev;
2426 struct drm_i915_private *dev_priv = dev->dev_private;
2427 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2428 int pipe = intel_crtc->pipe;
2429 u32 reg, temp;
2430
2431 /* Write the TU size bits so error detection works */
2432 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2433 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2434
2435 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2436 reg = FDI_RX_CTL(pipe);
2437 temp = I915_READ(reg);
2438 temp &= ~((0x7 << 19) | (0x7 << 16));
2439 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2440 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2441 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2442
2443 POSTING_READ(reg);
2444 udelay(200);
2445
2446 /* Switch from Rawclk to PCDclk */
2447 temp = I915_READ(reg);
2448 I915_WRITE(reg, temp | FDI_PCDCLK);
2449
2450 POSTING_READ(reg);
2451 udelay(200);
2452
2453 /* Enable CPU FDI TX PLL, always on for Ironlake */
2454 reg = FDI_TX_CTL(pipe);
2455 temp = I915_READ(reg);
2456 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2457 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2458
2459 POSTING_READ(reg);
2460 udelay(100);
2461 }
2462 }
2463
2464 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2465 {
2466 struct drm_device *dev = crtc->dev;
2467 struct drm_i915_private *dev_priv = dev->dev_private;
2468 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2469 int pipe = intel_crtc->pipe;
2470 u32 reg, temp;
2471
2472 /* disable CPU FDI tx and PCH FDI rx */
2473 reg = FDI_TX_CTL(pipe);
2474 temp = I915_READ(reg);
2475 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2476 POSTING_READ(reg);
2477
2478 reg = FDI_RX_CTL(pipe);
2479 temp = I915_READ(reg);
2480 temp &= ~(0x7 << 16);
2481 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2482 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2483
2484 POSTING_READ(reg);
2485 udelay(100);
2486
2487 /* Ironlake workaround, disable clock pointer after downing FDI */
2488 if (HAS_PCH_IBX(dev)) {
2489 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2490 I915_WRITE(FDI_RX_CHICKEN(pipe),
2491 I915_READ(FDI_RX_CHICKEN(pipe) &
2492 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2493 }
2494
2495 /* still set train pattern 1 */
2496 reg = FDI_TX_CTL(pipe);
2497 temp = I915_READ(reg);
2498 temp &= ~FDI_LINK_TRAIN_NONE;
2499 temp |= FDI_LINK_TRAIN_PATTERN_1;
2500 I915_WRITE(reg, temp);
2501
2502 reg = FDI_RX_CTL(pipe);
2503 temp = I915_READ(reg);
2504 if (HAS_PCH_CPT(dev)) {
2505 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2506 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2507 } else {
2508 temp &= ~FDI_LINK_TRAIN_NONE;
2509 temp |= FDI_LINK_TRAIN_PATTERN_1;
2510 }
2511 /* BPC in FDI rx is consistent with that in PIPECONF */
2512 temp &= ~(0x07 << 16);
2513 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2514 I915_WRITE(reg, temp);
2515
2516 POSTING_READ(reg);
2517 udelay(100);
2518 }
2519
2520 /*
2521 * When we disable a pipe, we need to clear any pending scanline wait events
2522 * to avoid hanging the ring, which we assume we are waiting on.
2523 */
2524 static void intel_clear_scanline_wait(struct drm_device *dev)
2525 {
2526 struct drm_i915_private *dev_priv = dev->dev_private;
2527 struct intel_ring_buffer *ring;
2528 u32 tmp;
2529
2530 if (IS_GEN2(dev))
2531 /* Can't break the hang on i8xx */
2532 return;
2533
2534 ring = LP_RING(dev_priv);
2535 tmp = I915_READ_CTL(ring);
2536 if (tmp & RING_WAIT)
2537 I915_WRITE_CTL(ring, tmp);
2538 }
2539
2540 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2541 {
2542 struct drm_i915_gem_object *obj;
2543 struct drm_i915_private *dev_priv;
2544
2545 if (crtc->fb == NULL)
2546 return;
2547
2548 obj = to_intel_framebuffer(crtc->fb)->obj;
2549 dev_priv = crtc->dev->dev_private;
2550 wait_event(dev_priv->pending_flip_queue,
2551 atomic_read(&obj->pending_flip) == 0);
2552 }
2553
2554 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2555 {
2556 struct drm_device *dev = crtc->dev;
2557 struct drm_mode_config *mode_config = &dev->mode_config;
2558 struct intel_encoder *encoder;
2559
2560 /*
2561 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2562 * must be driven by its own crtc; no sharing is possible.
2563 */
2564 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2565 if (encoder->base.crtc != crtc)
2566 continue;
2567
2568 switch (encoder->type) {
2569 case INTEL_OUTPUT_EDP:
2570 if (!intel_encoder_is_pch_edp(&encoder->base))
2571 return false;
2572 continue;
2573 }
2574 }
2575
2576 return true;
2577 }
2578
2579 /*
2580 * Enable PCH resources required for PCH ports:
2581 * - PCH PLLs
2582 * - FDI training & RX/TX
2583 * - update transcoder timings
2584 * - DP transcoding bits
2585 * - transcoder
2586 */
2587 static void ironlake_pch_enable(struct drm_crtc *crtc)
2588 {
2589 struct drm_device *dev = crtc->dev;
2590 struct drm_i915_private *dev_priv = dev->dev_private;
2591 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2592 int pipe = intel_crtc->pipe;
2593 u32 reg, temp;
2594
2595 /* For PCH output, training FDI link */
2596 dev_priv->display.fdi_link_train(crtc);
2597
2598 intel_enable_pch_pll(dev_priv, pipe);
2599
2600 if (HAS_PCH_CPT(dev)) {
2601 /* Be sure PCH DPLL SEL is set */
2602 temp = I915_READ(PCH_DPLL_SEL);
2603 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2604 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2605 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2606 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2607 I915_WRITE(PCH_DPLL_SEL, temp);
2608 }
2609
2610 /* set transcoder timing, panel must allow it */
2611 assert_panel_unlocked(dev_priv, pipe);
2612 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2613 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2614 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
2615
2616 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2617 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2618 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
2619
2620 intel_fdi_normal_train(crtc);
2621
2622 /* For PCH DP, enable TRANS_DP_CTL */
2623 if (HAS_PCH_CPT(dev) &&
2624 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2625 reg = TRANS_DP_CTL(pipe);
2626 temp = I915_READ(reg);
2627 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2628 TRANS_DP_SYNC_MASK |
2629 TRANS_DP_BPC_MASK);
2630 temp |= (TRANS_DP_OUTPUT_ENABLE |
2631 TRANS_DP_ENH_FRAMING);
2632 temp |= TRANS_DP_8BPC;
2633
2634 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2635 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2636 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2637 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2638
2639 switch (intel_trans_dp_port_sel(crtc)) {
2640 case PCH_DP_B:
2641 temp |= TRANS_DP_PORT_SEL_B;
2642 break;
2643 case PCH_DP_C:
2644 temp |= TRANS_DP_PORT_SEL_C;
2645 break;
2646 case PCH_DP_D:
2647 temp |= TRANS_DP_PORT_SEL_D;
2648 break;
2649 default:
2650 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2651 temp |= TRANS_DP_PORT_SEL_B;
2652 break;
2653 }
2654
2655 I915_WRITE(reg, temp);
2656 }
2657
2658 intel_enable_transcoder(dev_priv, pipe);
2659 }
2660
2661 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2662 {
2663 struct drm_device *dev = crtc->dev;
2664 struct drm_i915_private *dev_priv = dev->dev_private;
2665 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2666 int pipe = intel_crtc->pipe;
2667 int plane = intel_crtc->plane;
2668 u32 temp;
2669 bool is_pch_port;
2670
2671 if (intel_crtc->active)
2672 return;
2673
2674 intel_crtc->active = true;
2675 intel_update_watermarks(dev);
2676
2677 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2678 temp = I915_READ(PCH_LVDS);
2679 if ((temp & LVDS_PORT_EN) == 0)
2680 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2681 }
2682
2683 is_pch_port = intel_crtc_driving_pch(crtc);
2684
2685 if (is_pch_port)
2686 ironlake_fdi_pll_enable(crtc);
2687 else
2688 ironlake_fdi_disable(crtc);
2689
2690 /* Enable panel fitting for LVDS */
2691 if (dev_priv->pch_pf_size &&
2692 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2693 /* Force use of hard-coded filter coefficients
2694 * as some pre-programmed values are broken,
2695 * e.g. x201.
2696 */
2697 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2698 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2699 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
2700 }
2701
2702 intel_enable_pipe(dev_priv, pipe, is_pch_port);
2703 intel_enable_plane(dev_priv, plane, pipe);
2704
2705 if (is_pch_port)
2706 ironlake_pch_enable(crtc);
2707
2708 intel_crtc_load_lut(crtc);
2709
2710 mutex_lock(&dev->struct_mutex);
2711 intel_update_fbc(dev);
2712 mutex_unlock(&dev->struct_mutex);
2713
2714 intel_crtc_update_cursor(crtc, true);
2715 }
2716
2717 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2718 {
2719 struct drm_device *dev = crtc->dev;
2720 struct drm_i915_private *dev_priv = dev->dev_private;
2721 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2722 int pipe = intel_crtc->pipe;
2723 int plane = intel_crtc->plane;
2724 u32 reg, temp;
2725
2726 if (!intel_crtc->active)
2727 return;
2728
2729 intel_crtc_wait_for_pending_flips(crtc);
2730 drm_vblank_off(dev, pipe);
2731 intel_crtc_update_cursor(crtc, false);
2732
2733 intel_disable_plane(dev_priv, plane, pipe);
2734
2735 if (dev_priv->cfb_plane == plane &&
2736 dev_priv->display.disable_fbc)
2737 dev_priv->display.disable_fbc(dev);
2738
2739 intel_disable_pipe(dev_priv, pipe);
2740
2741 /* Disable PF */
2742 I915_WRITE(PF_CTL(pipe), 0);
2743 I915_WRITE(PF_WIN_SZ(pipe), 0);
2744
2745 ironlake_fdi_disable(crtc);
2746
2747 /* This is a horrible layering violation; we should be doing this in
2748 * the connector/encoder ->prepare instead, but we don't always have
2749 * enough information there about the config to know whether it will
2750 * actually be necessary or just cause undesired flicker.
2751 */
2752 intel_disable_pch_ports(dev_priv, pipe);
2753
2754 intel_disable_transcoder(dev_priv, pipe);
2755
2756 if (HAS_PCH_CPT(dev)) {
2757 /* disable TRANS_DP_CTL */
2758 reg = TRANS_DP_CTL(pipe);
2759 temp = I915_READ(reg);
2760 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2761 temp |= TRANS_DP_PORT_SEL_NONE;
2762 I915_WRITE(reg, temp);
2763
2764 /* disable DPLL_SEL */
2765 temp = I915_READ(PCH_DPLL_SEL);
2766 switch (pipe) {
2767 case 0:
2768 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2769 break;
2770 case 1:
2771 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2772 break;
2773 case 2:
2774 /* FIXME: manage transcoder PLLs? */
2775 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
2776 break;
2777 default:
2778 BUG(); /* wtf */
2779 }
2780 I915_WRITE(PCH_DPLL_SEL, temp);
2781 }
2782
2783 /* disable PCH DPLL */
2784 intel_disable_pch_pll(dev_priv, pipe);
2785
2786 /* Switch from PCDclk to Rawclk */
2787 reg = FDI_RX_CTL(pipe);
2788 temp = I915_READ(reg);
2789 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2790
2791 /* Disable CPU FDI TX PLL */
2792 reg = FDI_TX_CTL(pipe);
2793 temp = I915_READ(reg);
2794 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2795
2796 POSTING_READ(reg);
2797 udelay(100);
2798
2799 reg = FDI_RX_CTL(pipe);
2800 temp = I915_READ(reg);
2801 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2802
2803 /* Wait for the clocks to turn off. */
2804 POSTING_READ(reg);
2805 udelay(100);
2806
2807 intel_crtc->active = false;
2808 intel_update_watermarks(dev);
2809
2810 mutex_lock(&dev->struct_mutex);
2811 intel_update_fbc(dev);
2812 intel_clear_scanline_wait(dev);
2813 mutex_unlock(&dev->struct_mutex);
2814 }
2815
2816 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2817 {
2818 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2819 int pipe = intel_crtc->pipe;
2820 int plane = intel_crtc->plane;
2821
2822 /* XXX: When our outputs are all unaware of DPMS modes other than off
2823 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2824 */
2825 switch (mode) {
2826 case DRM_MODE_DPMS_ON:
2827 case DRM_MODE_DPMS_STANDBY:
2828 case DRM_MODE_DPMS_SUSPEND:
2829 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2830 ironlake_crtc_enable(crtc);
2831 break;
2832
2833 case DRM_MODE_DPMS_OFF:
2834 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2835 ironlake_crtc_disable(crtc);
2836 break;
2837 }
2838 }
2839
2840 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2841 {
2842 if (!enable && intel_crtc->overlay) {
2843 struct drm_device *dev = intel_crtc->base.dev;
2844 struct drm_i915_private *dev_priv = dev->dev_private;
2845
2846 mutex_lock(&dev->struct_mutex);
2847 dev_priv->mm.interruptible = false;
2848 (void) intel_overlay_switch_off(intel_crtc->overlay);
2849 dev_priv->mm.interruptible = true;
2850 mutex_unlock(&dev->struct_mutex);
2851 }
2852
2853 /* Let userspace switch the overlay on again. In most cases userspace
2854 * has to recompute where to put it anyway.
2855 */
2856 }
2857
2858 static void i9xx_crtc_enable(struct drm_crtc *crtc)
2859 {
2860 struct drm_device *dev = crtc->dev;
2861 struct drm_i915_private *dev_priv = dev->dev_private;
2862 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2863 int pipe = intel_crtc->pipe;
2864 int plane = intel_crtc->plane;
2865
2866 if (intel_crtc->active)
2867 return;
2868
2869 intel_crtc->active = true;
2870 intel_update_watermarks(dev);
2871
2872 intel_enable_pll(dev_priv, pipe);
2873 intel_enable_pipe(dev_priv, pipe, false);
2874 intel_enable_plane(dev_priv, plane, pipe);
2875
2876 intel_crtc_load_lut(crtc);
2877 intel_update_fbc(dev);
2878
2879 /* Give the overlay scaler a chance to enable if it's on this pipe */
2880 intel_crtc_dpms_overlay(intel_crtc, true);
2881 intel_crtc_update_cursor(crtc, true);
2882 }
2883
2884 static void i9xx_crtc_disable(struct drm_crtc *crtc)
2885 {
2886 struct drm_device *dev = crtc->dev;
2887 struct drm_i915_private *dev_priv = dev->dev_private;
2888 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2889 int pipe = intel_crtc->pipe;
2890 int plane = intel_crtc->plane;
2891
2892 if (!intel_crtc->active)
2893 return;
2894
2895 /* Give the overlay scaler a chance to disable if it's on this pipe */
2896 intel_crtc_wait_for_pending_flips(crtc);
2897 drm_vblank_off(dev, pipe);
2898 intel_crtc_dpms_overlay(intel_crtc, false);
2899 intel_crtc_update_cursor(crtc, false);
2900
2901 if (dev_priv->cfb_plane == plane &&
2902 dev_priv->display.disable_fbc)
2903 dev_priv->display.disable_fbc(dev);
2904
2905 intel_disable_plane(dev_priv, plane, pipe);
2906 intel_disable_pipe(dev_priv, pipe);
2907 intel_disable_pll(dev_priv, pipe);
2908
2909 intel_crtc->active = false;
2910 intel_update_fbc(dev);
2911 intel_update_watermarks(dev);
2912 intel_clear_scanline_wait(dev);
2913 }
2914
2915 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2916 {
2917 /* XXX: When our outputs are all unaware of DPMS modes other than off
2918 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2919 */
2920 switch (mode) {
2921 case DRM_MODE_DPMS_ON:
2922 case DRM_MODE_DPMS_STANDBY:
2923 case DRM_MODE_DPMS_SUSPEND:
2924 i9xx_crtc_enable(crtc);
2925 break;
2926 case DRM_MODE_DPMS_OFF:
2927 i9xx_crtc_disable(crtc);
2928 break;
2929 }
2930 }
2931
2932 /**
2933 * Sets the power management mode of the pipe and plane.
2934 */
2935 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2936 {
2937 struct drm_device *dev = crtc->dev;
2938 struct drm_i915_private *dev_priv = dev->dev_private;
2939 struct drm_i915_master_private *master_priv;
2940 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2941 int pipe = intel_crtc->pipe;
2942 bool enabled;
2943
2944 if (intel_crtc->dpms_mode == mode)
2945 return;
2946
2947 intel_crtc->dpms_mode = mode;
2948
2949 dev_priv->display.dpms(crtc, mode);
2950
2951 if (!dev->primary->master)
2952 return;
2953
2954 master_priv = dev->primary->master->driver_priv;
2955 if (!master_priv->sarea_priv)
2956 return;
2957
2958 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2959
2960 switch (pipe) {
2961 case 0:
2962 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2963 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2964 break;
2965 case 1:
2966 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2967 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2968 break;
2969 default:
2970 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
2971 break;
2972 }
2973 }
2974
2975 static void intel_crtc_disable(struct drm_crtc *crtc)
2976 {
2977 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2978 struct drm_device *dev = crtc->dev;
2979
2980 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2981
2982 if (crtc->fb) {
2983 mutex_lock(&dev->struct_mutex);
2984 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2985 mutex_unlock(&dev->struct_mutex);
2986 }
2987 }
2988
2989 /* Prepare for a mode set.
2990 *
2991 * Note we could be a lot smarter here. We need to figure out which outputs
2992 * will be enabled, which disabled (in short, how the config will changes)
2993 * and perform the minimum necessary steps to accomplish that, e.g. updating
2994 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
2995 * panel fitting is in the proper state, etc.
2996 */
2997 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
2998 {
2999 i9xx_crtc_disable(crtc);
3000 }
3001
3002 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3003 {
3004 i9xx_crtc_enable(crtc);
3005 }
3006
3007 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3008 {
3009 ironlake_crtc_disable(crtc);
3010 }
3011
3012 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3013 {
3014 ironlake_crtc_enable(crtc);
3015 }
3016
3017 void intel_encoder_prepare (struct drm_encoder *encoder)
3018 {
3019 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3020 /* lvds has its own version of prepare see intel_lvds_prepare */
3021 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3022 }
3023
3024 void intel_encoder_commit (struct drm_encoder *encoder)
3025 {
3026 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3027 /* lvds has its own version of commit see intel_lvds_commit */
3028 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3029 }
3030
3031 void intel_encoder_destroy(struct drm_encoder *encoder)
3032 {
3033 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3034
3035 drm_encoder_cleanup(encoder);
3036 kfree(intel_encoder);
3037 }
3038
3039 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3040 struct drm_display_mode *mode,
3041 struct drm_display_mode *adjusted_mode)
3042 {
3043 struct drm_device *dev = crtc->dev;
3044
3045 if (HAS_PCH_SPLIT(dev)) {
3046 /* FDI link clock is fixed at 2.7G */
3047 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3048 return false;
3049 }
3050
3051 /* XXX some encoders set the crtcinfo, others don't.
3052 * Obviously we need some form of conflict resolution here...
3053 */
3054 if (adjusted_mode->crtc_htotal == 0)
3055 drm_mode_set_crtcinfo(adjusted_mode, 0);
3056
3057 return true;
3058 }
3059
3060 static int i945_get_display_clock_speed(struct drm_device *dev)
3061 {
3062 return 400000;
3063 }
3064
3065 static int i915_get_display_clock_speed(struct drm_device *dev)
3066 {
3067 return 333000;
3068 }
3069
3070 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3071 {
3072 return 200000;
3073 }
3074
3075 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3076 {
3077 u16 gcfgc = 0;
3078
3079 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3080
3081 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3082 return 133000;
3083 else {
3084 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3085 case GC_DISPLAY_CLOCK_333_MHZ:
3086 return 333000;
3087 default:
3088 case GC_DISPLAY_CLOCK_190_200_MHZ:
3089 return 190000;
3090 }
3091 }
3092 }
3093
3094 static int i865_get_display_clock_speed(struct drm_device *dev)
3095 {
3096 return 266000;
3097 }
3098
3099 static int i855_get_display_clock_speed(struct drm_device *dev)
3100 {
3101 u16 hpllcc = 0;
3102 /* Assume that the hardware is in the high speed state. This
3103 * should be the default.
3104 */
3105 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3106 case GC_CLOCK_133_200:
3107 case GC_CLOCK_100_200:
3108 return 200000;
3109 case GC_CLOCK_166_250:
3110 return 250000;
3111 case GC_CLOCK_100_133:
3112 return 133000;
3113 }
3114
3115 /* Shouldn't happen */
3116 return 0;
3117 }
3118
3119 static int i830_get_display_clock_speed(struct drm_device *dev)
3120 {
3121 return 133000;
3122 }
3123
3124 struct fdi_m_n {
3125 u32 tu;
3126 u32 gmch_m;
3127 u32 gmch_n;
3128 u32 link_m;
3129 u32 link_n;
3130 };
3131
3132 static void
3133 fdi_reduce_ratio(u32 *num, u32 *den)
3134 {
3135 while (*num > 0xffffff || *den > 0xffffff) {
3136 *num >>= 1;
3137 *den >>= 1;
3138 }
3139 }
3140
3141 static void
3142 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3143 int link_clock, struct fdi_m_n *m_n)
3144 {
3145 m_n->tu = 64; /* default size */
3146
3147 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3148 m_n->gmch_m = bits_per_pixel * pixel_clock;
3149 m_n->gmch_n = link_clock * nlanes * 8;
3150 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3151
3152 m_n->link_m = pixel_clock;
3153 m_n->link_n = link_clock;
3154 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3155 }
3156
3157
3158 struct intel_watermark_params {
3159 unsigned long fifo_size;
3160 unsigned long max_wm;
3161 unsigned long default_wm;
3162 unsigned long guard_size;
3163 unsigned long cacheline_size;
3164 };
3165
3166 /* Pineview has different values for various configs */
3167 static const struct intel_watermark_params pineview_display_wm = {
3168 PINEVIEW_DISPLAY_FIFO,
3169 PINEVIEW_MAX_WM,
3170 PINEVIEW_DFT_WM,
3171 PINEVIEW_GUARD_WM,
3172 PINEVIEW_FIFO_LINE_SIZE
3173 };
3174 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3175 PINEVIEW_DISPLAY_FIFO,
3176 PINEVIEW_MAX_WM,
3177 PINEVIEW_DFT_HPLLOFF_WM,
3178 PINEVIEW_GUARD_WM,
3179 PINEVIEW_FIFO_LINE_SIZE
3180 };
3181 static const struct intel_watermark_params pineview_cursor_wm = {
3182 PINEVIEW_CURSOR_FIFO,
3183 PINEVIEW_CURSOR_MAX_WM,
3184 PINEVIEW_CURSOR_DFT_WM,
3185 PINEVIEW_CURSOR_GUARD_WM,
3186 PINEVIEW_FIFO_LINE_SIZE,
3187 };
3188 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3189 PINEVIEW_CURSOR_FIFO,
3190 PINEVIEW_CURSOR_MAX_WM,
3191 PINEVIEW_CURSOR_DFT_WM,
3192 PINEVIEW_CURSOR_GUARD_WM,
3193 PINEVIEW_FIFO_LINE_SIZE
3194 };
3195 static const struct intel_watermark_params g4x_wm_info = {
3196 G4X_FIFO_SIZE,
3197 G4X_MAX_WM,
3198 G4X_MAX_WM,
3199 2,
3200 G4X_FIFO_LINE_SIZE,
3201 };
3202 static const struct intel_watermark_params g4x_cursor_wm_info = {
3203 I965_CURSOR_FIFO,
3204 I965_CURSOR_MAX_WM,
3205 I965_CURSOR_DFT_WM,
3206 2,
3207 G4X_FIFO_LINE_SIZE,
3208 };
3209 static const struct intel_watermark_params i965_cursor_wm_info = {
3210 I965_CURSOR_FIFO,
3211 I965_CURSOR_MAX_WM,
3212 I965_CURSOR_DFT_WM,
3213 2,
3214 I915_FIFO_LINE_SIZE,
3215 };
3216 static const struct intel_watermark_params i945_wm_info = {
3217 I945_FIFO_SIZE,
3218 I915_MAX_WM,
3219 1,
3220 2,
3221 I915_FIFO_LINE_SIZE
3222 };
3223 static const struct intel_watermark_params i915_wm_info = {
3224 I915_FIFO_SIZE,
3225 I915_MAX_WM,
3226 1,
3227 2,
3228 I915_FIFO_LINE_SIZE
3229 };
3230 static const struct intel_watermark_params i855_wm_info = {
3231 I855GM_FIFO_SIZE,
3232 I915_MAX_WM,
3233 1,
3234 2,
3235 I830_FIFO_LINE_SIZE
3236 };
3237 static const struct intel_watermark_params i830_wm_info = {
3238 I830_FIFO_SIZE,
3239 I915_MAX_WM,
3240 1,
3241 2,
3242 I830_FIFO_LINE_SIZE
3243 };
3244
3245 static const struct intel_watermark_params ironlake_display_wm_info = {
3246 ILK_DISPLAY_FIFO,
3247 ILK_DISPLAY_MAXWM,
3248 ILK_DISPLAY_DFTWM,
3249 2,
3250 ILK_FIFO_LINE_SIZE
3251 };
3252 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3253 ILK_CURSOR_FIFO,
3254 ILK_CURSOR_MAXWM,
3255 ILK_CURSOR_DFTWM,
3256 2,
3257 ILK_FIFO_LINE_SIZE
3258 };
3259 static const struct intel_watermark_params ironlake_display_srwm_info = {
3260 ILK_DISPLAY_SR_FIFO,
3261 ILK_DISPLAY_MAX_SRWM,
3262 ILK_DISPLAY_DFT_SRWM,
3263 2,
3264 ILK_FIFO_LINE_SIZE
3265 };
3266 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3267 ILK_CURSOR_SR_FIFO,
3268 ILK_CURSOR_MAX_SRWM,
3269 ILK_CURSOR_DFT_SRWM,
3270 2,
3271 ILK_FIFO_LINE_SIZE
3272 };
3273
3274 static const struct intel_watermark_params sandybridge_display_wm_info = {
3275 SNB_DISPLAY_FIFO,
3276 SNB_DISPLAY_MAXWM,
3277 SNB_DISPLAY_DFTWM,
3278 2,
3279 SNB_FIFO_LINE_SIZE
3280 };
3281 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3282 SNB_CURSOR_FIFO,
3283 SNB_CURSOR_MAXWM,
3284 SNB_CURSOR_DFTWM,
3285 2,
3286 SNB_FIFO_LINE_SIZE
3287 };
3288 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3289 SNB_DISPLAY_SR_FIFO,
3290 SNB_DISPLAY_MAX_SRWM,
3291 SNB_DISPLAY_DFT_SRWM,
3292 2,
3293 SNB_FIFO_LINE_SIZE
3294 };
3295 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3296 SNB_CURSOR_SR_FIFO,
3297 SNB_CURSOR_MAX_SRWM,
3298 SNB_CURSOR_DFT_SRWM,
3299 2,
3300 SNB_FIFO_LINE_SIZE
3301 };
3302
3303
3304 /**
3305 * intel_calculate_wm - calculate watermark level
3306 * @clock_in_khz: pixel clock
3307 * @wm: chip FIFO params
3308 * @pixel_size: display pixel size
3309 * @latency_ns: memory latency for the platform
3310 *
3311 * Calculate the watermark level (the level at which the display plane will
3312 * start fetching from memory again). Each chip has a different display
3313 * FIFO size and allocation, so the caller needs to figure that out and pass
3314 * in the correct intel_watermark_params structure.
3315 *
3316 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3317 * on the pixel size. When it reaches the watermark level, it'll start
3318 * fetching FIFO line sized based chunks from memory until the FIFO fills
3319 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3320 * will occur, and a display engine hang could result.
3321 */
3322 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3323 const struct intel_watermark_params *wm,
3324 int fifo_size,
3325 int pixel_size,
3326 unsigned long latency_ns)
3327 {
3328 long entries_required, wm_size;
3329
3330 /*
3331 * Note: we need to make sure we don't overflow for various clock &
3332 * latency values.
3333 * clocks go from a few thousand to several hundred thousand.
3334 * latency is usually a few thousand
3335 */
3336 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3337 1000;
3338 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3339
3340 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3341
3342 wm_size = fifo_size - (entries_required + wm->guard_size);
3343
3344 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3345
3346 /* Don't promote wm_size to unsigned... */
3347 if (wm_size > (long)wm->max_wm)
3348 wm_size = wm->max_wm;
3349 if (wm_size <= 0)
3350 wm_size = wm->default_wm;
3351 return wm_size;
3352 }
3353
3354 struct cxsr_latency {
3355 int is_desktop;
3356 int is_ddr3;
3357 unsigned long fsb_freq;
3358 unsigned long mem_freq;
3359 unsigned long display_sr;
3360 unsigned long display_hpll_disable;
3361 unsigned long cursor_sr;
3362 unsigned long cursor_hpll_disable;
3363 };
3364
3365 static const struct cxsr_latency cxsr_latency_table[] = {
3366 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3367 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3368 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3369 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3370 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3371
3372 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3373 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3374 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3375 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3376 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3377
3378 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3379 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3380 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3381 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3382 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3383
3384 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3385 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3386 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3387 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3388 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3389
3390 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3391 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3392 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3393 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3394 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3395
3396 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3397 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3398 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3399 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3400 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
3401 };
3402
3403 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3404 int is_ddr3,
3405 int fsb,
3406 int mem)
3407 {
3408 const struct cxsr_latency *latency;
3409 int i;
3410
3411 if (fsb == 0 || mem == 0)
3412 return NULL;
3413
3414 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3415 latency = &cxsr_latency_table[i];
3416 if (is_desktop == latency->is_desktop &&
3417 is_ddr3 == latency->is_ddr3 &&
3418 fsb == latency->fsb_freq && mem == latency->mem_freq)
3419 return latency;
3420 }
3421
3422 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3423
3424 return NULL;
3425 }
3426
3427 static void pineview_disable_cxsr(struct drm_device *dev)
3428 {
3429 struct drm_i915_private *dev_priv = dev->dev_private;
3430
3431 /* deactivate cxsr */
3432 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3433 }
3434
3435 /*
3436 * Latency for FIFO fetches is dependent on several factors:
3437 * - memory configuration (speed, channels)
3438 * - chipset
3439 * - current MCH state
3440 * It can be fairly high in some situations, so here we assume a fairly
3441 * pessimal value. It's a tradeoff between extra memory fetches (if we
3442 * set this value too high, the FIFO will fetch frequently to stay full)
3443 * and power consumption (set it too low to save power and we might see
3444 * FIFO underruns and display "flicker").
3445 *
3446 * A value of 5us seems to be a good balance; safe for very low end
3447 * platforms but not overly aggressive on lower latency configs.
3448 */
3449 static const int latency_ns = 5000;
3450
3451 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3452 {
3453 struct drm_i915_private *dev_priv = dev->dev_private;
3454 uint32_t dsparb = I915_READ(DSPARB);
3455 int size;
3456
3457 size = dsparb & 0x7f;
3458 if (plane)
3459 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3460
3461 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3462 plane ? "B" : "A", size);
3463
3464 return size;
3465 }
3466
3467 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3468 {
3469 struct drm_i915_private *dev_priv = dev->dev_private;
3470 uint32_t dsparb = I915_READ(DSPARB);
3471 int size;
3472
3473 size = dsparb & 0x1ff;
3474 if (plane)
3475 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3476 size >>= 1; /* Convert to cachelines */
3477
3478 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3479 plane ? "B" : "A", size);
3480
3481 return size;
3482 }
3483
3484 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3485 {
3486 struct drm_i915_private *dev_priv = dev->dev_private;
3487 uint32_t dsparb = I915_READ(DSPARB);
3488 int size;
3489
3490 size = dsparb & 0x7f;
3491 size >>= 2; /* Convert to cachelines */
3492
3493 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3494 plane ? "B" : "A",
3495 size);
3496
3497 return size;
3498 }
3499
3500 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3501 {
3502 struct drm_i915_private *dev_priv = dev->dev_private;
3503 uint32_t dsparb = I915_READ(DSPARB);
3504 int size;
3505
3506 size = dsparb & 0x7f;
3507 size >>= 1; /* Convert to cachelines */
3508
3509 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3510 plane ? "B" : "A", size);
3511
3512 return size;
3513 }
3514
3515 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3516 {
3517 struct drm_crtc *crtc, *enabled = NULL;
3518
3519 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3520 if (crtc->enabled && crtc->fb) {
3521 if (enabled)
3522 return NULL;
3523 enabled = crtc;
3524 }
3525 }
3526
3527 return enabled;
3528 }
3529
3530 static void pineview_update_wm(struct drm_device *dev)
3531 {
3532 struct drm_i915_private *dev_priv = dev->dev_private;
3533 struct drm_crtc *crtc;
3534 const struct cxsr_latency *latency;
3535 u32 reg;
3536 unsigned long wm;
3537
3538 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3539 dev_priv->fsb_freq, dev_priv->mem_freq);
3540 if (!latency) {
3541 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3542 pineview_disable_cxsr(dev);
3543 return;
3544 }
3545
3546 crtc = single_enabled_crtc(dev);
3547 if (crtc) {
3548 int clock = crtc->mode.clock;
3549 int pixel_size = crtc->fb->bits_per_pixel / 8;
3550
3551 /* Display SR */
3552 wm = intel_calculate_wm(clock, &pineview_display_wm,
3553 pineview_display_wm.fifo_size,
3554 pixel_size, latency->display_sr);
3555 reg = I915_READ(DSPFW1);
3556 reg &= ~DSPFW_SR_MASK;
3557 reg |= wm << DSPFW_SR_SHIFT;
3558 I915_WRITE(DSPFW1, reg);
3559 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3560
3561 /* cursor SR */
3562 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3563 pineview_display_wm.fifo_size,
3564 pixel_size, latency->cursor_sr);
3565 reg = I915_READ(DSPFW3);
3566 reg &= ~DSPFW_CURSOR_SR_MASK;
3567 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3568 I915_WRITE(DSPFW3, reg);
3569
3570 /* Display HPLL off SR */
3571 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3572 pineview_display_hplloff_wm.fifo_size,
3573 pixel_size, latency->display_hpll_disable);
3574 reg = I915_READ(DSPFW3);
3575 reg &= ~DSPFW_HPLL_SR_MASK;
3576 reg |= wm & DSPFW_HPLL_SR_MASK;
3577 I915_WRITE(DSPFW3, reg);
3578
3579 /* cursor HPLL off SR */
3580 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3581 pineview_display_hplloff_wm.fifo_size,
3582 pixel_size, latency->cursor_hpll_disable);
3583 reg = I915_READ(DSPFW3);
3584 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3585 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3586 I915_WRITE(DSPFW3, reg);
3587 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3588
3589 /* activate cxsr */
3590 I915_WRITE(DSPFW3,
3591 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3592 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3593 } else {
3594 pineview_disable_cxsr(dev);
3595 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3596 }
3597 }
3598
3599 static bool g4x_compute_wm0(struct drm_device *dev,
3600 int plane,
3601 const struct intel_watermark_params *display,
3602 int display_latency_ns,
3603 const struct intel_watermark_params *cursor,
3604 int cursor_latency_ns,
3605 int *plane_wm,
3606 int *cursor_wm)
3607 {
3608 struct drm_crtc *crtc;
3609 int htotal, hdisplay, clock, pixel_size;
3610 int line_time_us, line_count;
3611 int entries, tlb_miss;
3612
3613 crtc = intel_get_crtc_for_plane(dev, plane);
3614 if (crtc->fb == NULL || !crtc->enabled) {
3615 *cursor_wm = cursor->guard_size;
3616 *plane_wm = display->guard_size;
3617 return false;
3618 }
3619
3620 htotal = crtc->mode.htotal;
3621 hdisplay = crtc->mode.hdisplay;
3622 clock = crtc->mode.clock;
3623 pixel_size = crtc->fb->bits_per_pixel / 8;
3624
3625 /* Use the small buffer method to calculate plane watermark */
3626 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3627 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3628 if (tlb_miss > 0)
3629 entries += tlb_miss;
3630 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3631 *plane_wm = entries + display->guard_size;
3632 if (*plane_wm > (int)display->max_wm)
3633 *plane_wm = display->max_wm;
3634
3635 /* Use the large buffer method to calculate cursor watermark */
3636 line_time_us = ((htotal * 1000) / clock);
3637 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3638 entries = line_count * 64 * pixel_size;
3639 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3640 if (tlb_miss > 0)
3641 entries += tlb_miss;
3642 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3643 *cursor_wm = entries + cursor->guard_size;
3644 if (*cursor_wm > (int)cursor->max_wm)
3645 *cursor_wm = (int)cursor->max_wm;
3646
3647 return true;
3648 }
3649
3650 /*
3651 * Check the wm result.
3652 *
3653 * If any calculated watermark values is larger than the maximum value that
3654 * can be programmed into the associated watermark register, that watermark
3655 * must be disabled.
3656 */
3657 static bool g4x_check_srwm(struct drm_device *dev,
3658 int display_wm, int cursor_wm,
3659 const struct intel_watermark_params *display,
3660 const struct intel_watermark_params *cursor)
3661 {
3662 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
3663 display_wm, cursor_wm);
3664
3665 if (display_wm > display->max_wm) {
3666 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
3667 display_wm, display->max_wm);
3668 return false;
3669 }
3670
3671 if (cursor_wm > cursor->max_wm) {
3672 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
3673 cursor_wm, cursor->max_wm);
3674 return false;
3675 }
3676
3677 if (!(display_wm || cursor_wm)) {
3678 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
3679 return false;
3680 }
3681
3682 return true;
3683 }
3684
3685 static bool g4x_compute_srwm(struct drm_device *dev,
3686 int plane,
3687 int latency_ns,
3688 const struct intel_watermark_params *display,
3689 const struct intel_watermark_params *cursor,
3690 int *display_wm, int *cursor_wm)
3691 {
3692 struct drm_crtc *crtc;
3693 int hdisplay, htotal, pixel_size, clock;
3694 unsigned long line_time_us;
3695 int line_count, line_size;
3696 int small, large;
3697 int entries;
3698
3699 if (!latency_ns) {
3700 *display_wm = *cursor_wm = 0;
3701 return false;
3702 }
3703
3704 crtc = intel_get_crtc_for_plane(dev, plane);
3705 hdisplay = crtc->mode.hdisplay;
3706 htotal = crtc->mode.htotal;
3707 clock = crtc->mode.clock;
3708 pixel_size = crtc->fb->bits_per_pixel / 8;
3709
3710 line_time_us = (htotal * 1000) / clock;
3711 line_count = (latency_ns / line_time_us + 1000) / 1000;
3712 line_size = hdisplay * pixel_size;
3713
3714 /* Use the minimum of the small and large buffer method for primary */
3715 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3716 large = line_count * line_size;
3717
3718 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3719 *display_wm = entries + display->guard_size;
3720
3721 /* calculate the self-refresh watermark for display cursor */
3722 entries = line_count * pixel_size * 64;
3723 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3724 *cursor_wm = entries + cursor->guard_size;
3725
3726 return g4x_check_srwm(dev,
3727 *display_wm, *cursor_wm,
3728 display, cursor);
3729 }
3730
3731 #define single_plane_enabled(mask) is_power_of_2(mask)
3732
3733 static void g4x_update_wm(struct drm_device *dev)
3734 {
3735 static const int sr_latency_ns = 12000;
3736 struct drm_i915_private *dev_priv = dev->dev_private;
3737 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3738 int plane_sr, cursor_sr;
3739 unsigned int enabled = 0;
3740
3741 if (g4x_compute_wm0(dev, 0,
3742 &g4x_wm_info, latency_ns,
3743 &g4x_cursor_wm_info, latency_ns,
3744 &planea_wm, &cursora_wm))
3745 enabled |= 1;
3746
3747 if (g4x_compute_wm0(dev, 1,
3748 &g4x_wm_info, latency_ns,
3749 &g4x_cursor_wm_info, latency_ns,
3750 &planeb_wm, &cursorb_wm))
3751 enabled |= 2;
3752
3753 plane_sr = cursor_sr = 0;
3754 if (single_plane_enabled(enabled) &&
3755 g4x_compute_srwm(dev, ffs(enabled) - 1,
3756 sr_latency_ns,
3757 &g4x_wm_info,
3758 &g4x_cursor_wm_info,
3759 &plane_sr, &cursor_sr))
3760 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3761 else
3762 I915_WRITE(FW_BLC_SELF,
3763 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
3764
3765 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
3766 planea_wm, cursora_wm,
3767 planeb_wm, cursorb_wm,
3768 plane_sr, cursor_sr);
3769
3770 I915_WRITE(DSPFW1,
3771 (plane_sr << DSPFW_SR_SHIFT) |
3772 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3773 (planeb_wm << DSPFW_PLANEB_SHIFT) |
3774 planea_wm);
3775 I915_WRITE(DSPFW2,
3776 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3777 (cursora_wm << DSPFW_CURSORA_SHIFT));
3778 /* HPLL off in SR has some issues on G4x... disable it */
3779 I915_WRITE(DSPFW3,
3780 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3781 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3782 }
3783
3784 static void i965_update_wm(struct drm_device *dev)
3785 {
3786 struct drm_i915_private *dev_priv = dev->dev_private;
3787 struct drm_crtc *crtc;
3788 int srwm = 1;
3789 int cursor_sr = 16;
3790
3791 /* Calc sr entries for one plane configs */
3792 crtc = single_enabled_crtc(dev);
3793 if (crtc) {
3794 /* self-refresh has much higher latency */
3795 static const int sr_latency_ns = 12000;
3796 int clock = crtc->mode.clock;
3797 int htotal = crtc->mode.htotal;
3798 int hdisplay = crtc->mode.hdisplay;
3799 int pixel_size = crtc->fb->bits_per_pixel / 8;
3800 unsigned long line_time_us;
3801 int entries;
3802
3803 line_time_us = ((htotal * 1000) / clock);
3804
3805 /* Use ns/us then divide to preserve precision */
3806 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3807 pixel_size * hdisplay;
3808 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
3809 srwm = I965_FIFO_SIZE - entries;
3810 if (srwm < 0)
3811 srwm = 1;
3812 srwm &= 0x1ff;
3813 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
3814 entries, srwm);
3815
3816 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3817 pixel_size * 64;
3818 entries = DIV_ROUND_UP(entries,
3819 i965_cursor_wm_info.cacheline_size);
3820 cursor_sr = i965_cursor_wm_info.fifo_size -
3821 (entries + i965_cursor_wm_info.guard_size);
3822
3823 if (cursor_sr > i965_cursor_wm_info.max_wm)
3824 cursor_sr = i965_cursor_wm_info.max_wm;
3825
3826 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3827 "cursor %d\n", srwm, cursor_sr);
3828
3829 if (IS_CRESTLINE(dev))
3830 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3831 } else {
3832 /* Turn off self refresh if both pipes are enabled */
3833 if (IS_CRESTLINE(dev))
3834 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3835 & ~FW_BLC_SELF_EN);
3836 }
3837
3838 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3839 srwm);
3840
3841 /* 965 has limitations... */
3842 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
3843 (8 << 16) | (8 << 8) | (8 << 0));
3844 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3845 /* update cursor SR watermark */
3846 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3847 }
3848
3849 static void i9xx_update_wm(struct drm_device *dev)
3850 {
3851 struct drm_i915_private *dev_priv = dev->dev_private;
3852 const struct intel_watermark_params *wm_info;
3853 uint32_t fwater_lo;
3854 uint32_t fwater_hi;
3855 int cwm, srwm = 1;
3856 int fifo_size;
3857 int planea_wm, planeb_wm;
3858 struct drm_crtc *crtc, *enabled = NULL;
3859
3860 if (IS_I945GM(dev))
3861 wm_info = &i945_wm_info;
3862 else if (!IS_GEN2(dev))
3863 wm_info = &i915_wm_info;
3864 else
3865 wm_info = &i855_wm_info;
3866
3867 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3868 crtc = intel_get_crtc_for_plane(dev, 0);
3869 if (crtc->enabled && crtc->fb) {
3870 planea_wm = intel_calculate_wm(crtc->mode.clock,
3871 wm_info, fifo_size,
3872 crtc->fb->bits_per_pixel / 8,
3873 latency_ns);
3874 enabled = crtc;
3875 } else
3876 planea_wm = fifo_size - wm_info->guard_size;
3877
3878 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3879 crtc = intel_get_crtc_for_plane(dev, 1);
3880 if (crtc->enabled && crtc->fb) {
3881 planeb_wm = intel_calculate_wm(crtc->mode.clock,
3882 wm_info, fifo_size,
3883 crtc->fb->bits_per_pixel / 8,
3884 latency_ns);
3885 if (enabled == NULL)
3886 enabled = crtc;
3887 else
3888 enabled = NULL;
3889 } else
3890 planeb_wm = fifo_size - wm_info->guard_size;
3891
3892 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3893
3894 /*
3895 * Overlay gets an aggressive default since video jitter is bad.
3896 */
3897 cwm = 2;
3898
3899 /* Play safe and disable self-refresh before adjusting watermarks. */
3900 if (IS_I945G(dev) || IS_I945GM(dev))
3901 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
3902 else if (IS_I915GM(dev))
3903 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3904
3905 /* Calc sr entries for one plane configs */
3906 if (HAS_FW_BLC(dev) && enabled) {
3907 /* self-refresh has much higher latency */
3908 static const int sr_latency_ns = 6000;
3909 int clock = enabled->mode.clock;
3910 int htotal = enabled->mode.htotal;
3911 int hdisplay = enabled->mode.hdisplay;
3912 int pixel_size = enabled->fb->bits_per_pixel / 8;
3913 unsigned long line_time_us;
3914 int entries;
3915
3916 line_time_us = (htotal * 1000) / clock;
3917
3918 /* Use ns/us then divide to preserve precision */
3919 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3920 pixel_size * hdisplay;
3921 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
3922 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
3923 srwm = wm_info->fifo_size - entries;
3924 if (srwm < 0)
3925 srwm = 1;
3926
3927 if (IS_I945G(dev) || IS_I945GM(dev))
3928 I915_WRITE(FW_BLC_SELF,
3929 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3930 else if (IS_I915GM(dev))
3931 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3932 }
3933
3934 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3935 planea_wm, planeb_wm, cwm, srwm);
3936
3937 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3938 fwater_hi = (cwm & 0x1f);
3939
3940 /* Set request length to 8 cachelines per fetch */
3941 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3942 fwater_hi = fwater_hi | (1 << 8);
3943
3944 I915_WRITE(FW_BLC, fwater_lo);
3945 I915_WRITE(FW_BLC2, fwater_hi);
3946
3947 if (HAS_FW_BLC(dev)) {
3948 if (enabled) {
3949 if (IS_I945G(dev) || IS_I945GM(dev))
3950 I915_WRITE(FW_BLC_SELF,
3951 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
3952 else if (IS_I915GM(dev))
3953 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3954 DRM_DEBUG_KMS("memory self refresh enabled\n");
3955 } else
3956 DRM_DEBUG_KMS("memory self refresh disabled\n");
3957 }
3958 }
3959
3960 static void i830_update_wm(struct drm_device *dev)
3961 {
3962 struct drm_i915_private *dev_priv = dev->dev_private;
3963 struct drm_crtc *crtc;
3964 uint32_t fwater_lo;
3965 int planea_wm;
3966
3967 crtc = single_enabled_crtc(dev);
3968 if (crtc == NULL)
3969 return;
3970
3971 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
3972 dev_priv->display.get_fifo_size(dev, 0),
3973 crtc->fb->bits_per_pixel / 8,
3974 latency_ns);
3975 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3976 fwater_lo |= (3<<8) | planea_wm;
3977
3978 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3979
3980 I915_WRITE(FW_BLC, fwater_lo);
3981 }
3982
3983 #define ILK_LP0_PLANE_LATENCY 700
3984 #define ILK_LP0_CURSOR_LATENCY 1300
3985
3986 /*
3987 * Check the wm result.
3988 *
3989 * If any calculated watermark values is larger than the maximum value that
3990 * can be programmed into the associated watermark register, that watermark
3991 * must be disabled.
3992 */
3993 static bool ironlake_check_srwm(struct drm_device *dev, int level,
3994 int fbc_wm, int display_wm, int cursor_wm,
3995 const struct intel_watermark_params *display,
3996 const struct intel_watermark_params *cursor)
3997 {
3998 struct drm_i915_private *dev_priv = dev->dev_private;
3999
4000 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4001 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4002
4003 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4004 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4005 fbc_wm, SNB_FBC_MAX_SRWM, level);
4006
4007 /* fbc has it's own way to disable FBC WM */
4008 I915_WRITE(DISP_ARB_CTL,
4009 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4010 return false;
4011 }
4012
4013 if (display_wm > display->max_wm) {
4014 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4015 display_wm, SNB_DISPLAY_MAX_SRWM, level);
4016 return false;
4017 }
4018
4019 if (cursor_wm > cursor->max_wm) {
4020 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4021 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4022 return false;
4023 }
4024
4025 if (!(fbc_wm || display_wm || cursor_wm)) {
4026 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4027 return false;
4028 }
4029
4030 return true;
4031 }
4032
4033 /*
4034 * Compute watermark values of WM[1-3],
4035 */
4036 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4037 int latency_ns,
4038 const struct intel_watermark_params *display,
4039 const struct intel_watermark_params *cursor,
4040 int *fbc_wm, int *display_wm, int *cursor_wm)
4041 {
4042 struct drm_crtc *crtc;
4043 unsigned long line_time_us;
4044 int hdisplay, htotal, pixel_size, clock;
4045 int line_count, line_size;
4046 int small, large;
4047 int entries;
4048
4049 if (!latency_ns) {
4050 *fbc_wm = *display_wm = *cursor_wm = 0;
4051 return false;
4052 }
4053
4054 crtc = intel_get_crtc_for_plane(dev, plane);
4055 hdisplay = crtc->mode.hdisplay;
4056 htotal = crtc->mode.htotal;
4057 clock = crtc->mode.clock;
4058 pixel_size = crtc->fb->bits_per_pixel / 8;
4059
4060 line_time_us = (htotal * 1000) / clock;
4061 line_count = (latency_ns / line_time_us + 1000) / 1000;
4062 line_size = hdisplay * pixel_size;
4063
4064 /* Use the minimum of the small and large buffer method for primary */
4065 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4066 large = line_count * line_size;
4067
4068 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4069 *display_wm = entries + display->guard_size;
4070
4071 /*
4072 * Spec says:
4073 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4074 */
4075 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4076
4077 /* calculate the self-refresh watermark for display cursor */
4078 entries = line_count * pixel_size * 64;
4079 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4080 *cursor_wm = entries + cursor->guard_size;
4081
4082 return ironlake_check_srwm(dev, level,
4083 *fbc_wm, *display_wm, *cursor_wm,
4084 display, cursor);
4085 }
4086
4087 static void ironlake_update_wm(struct drm_device *dev)
4088 {
4089 struct drm_i915_private *dev_priv = dev->dev_private;
4090 int fbc_wm, plane_wm, cursor_wm;
4091 unsigned int enabled;
4092
4093 enabled = 0;
4094 if (g4x_compute_wm0(dev, 0,
4095 &ironlake_display_wm_info,
4096 ILK_LP0_PLANE_LATENCY,
4097 &ironlake_cursor_wm_info,
4098 ILK_LP0_CURSOR_LATENCY,
4099 &plane_wm, &cursor_wm)) {
4100 I915_WRITE(WM0_PIPEA_ILK,
4101 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4102 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4103 " plane %d, " "cursor: %d\n",
4104 plane_wm, cursor_wm);
4105 enabled |= 1;
4106 }
4107
4108 if (g4x_compute_wm0(dev, 1,
4109 &ironlake_display_wm_info,
4110 ILK_LP0_PLANE_LATENCY,
4111 &ironlake_cursor_wm_info,
4112 ILK_LP0_CURSOR_LATENCY,
4113 &plane_wm, &cursor_wm)) {
4114 I915_WRITE(WM0_PIPEB_ILK,
4115 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4116 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4117 " plane %d, cursor: %d\n",
4118 plane_wm, cursor_wm);
4119 enabled |= 2;
4120 }
4121
4122 /*
4123 * Calculate and update the self-refresh watermark only when one
4124 * display plane is used.
4125 */
4126 I915_WRITE(WM3_LP_ILK, 0);
4127 I915_WRITE(WM2_LP_ILK, 0);
4128 I915_WRITE(WM1_LP_ILK, 0);
4129
4130 if (!single_plane_enabled(enabled))
4131 return;
4132 enabled = ffs(enabled) - 1;
4133
4134 /* WM1 */
4135 if (!ironlake_compute_srwm(dev, 1, enabled,
4136 ILK_READ_WM1_LATENCY() * 500,
4137 &ironlake_display_srwm_info,
4138 &ironlake_cursor_srwm_info,
4139 &fbc_wm, &plane_wm, &cursor_wm))
4140 return;
4141
4142 I915_WRITE(WM1_LP_ILK,
4143 WM1_LP_SR_EN |
4144 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4145 (fbc_wm << WM1_LP_FBC_SHIFT) |
4146 (plane_wm << WM1_LP_SR_SHIFT) |
4147 cursor_wm);
4148
4149 /* WM2 */
4150 if (!ironlake_compute_srwm(dev, 2, enabled,
4151 ILK_READ_WM2_LATENCY() * 500,
4152 &ironlake_display_srwm_info,
4153 &ironlake_cursor_srwm_info,
4154 &fbc_wm, &plane_wm, &cursor_wm))
4155 return;
4156
4157 I915_WRITE(WM2_LP_ILK,
4158 WM2_LP_EN |
4159 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4160 (fbc_wm << WM1_LP_FBC_SHIFT) |
4161 (plane_wm << WM1_LP_SR_SHIFT) |
4162 cursor_wm);
4163
4164 /*
4165 * WM3 is unsupported on ILK, probably because we don't have latency
4166 * data for that power state
4167 */
4168 }
4169
4170 static void sandybridge_update_wm(struct drm_device *dev)
4171 {
4172 struct drm_i915_private *dev_priv = dev->dev_private;
4173 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
4174 int fbc_wm, plane_wm, cursor_wm;
4175 unsigned int enabled;
4176
4177 enabled = 0;
4178 if (g4x_compute_wm0(dev, 0,
4179 &sandybridge_display_wm_info, latency,
4180 &sandybridge_cursor_wm_info, latency,
4181 &plane_wm, &cursor_wm)) {
4182 I915_WRITE(WM0_PIPEA_ILK,
4183 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4184 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4185 " plane %d, " "cursor: %d\n",
4186 plane_wm, cursor_wm);
4187 enabled |= 1;
4188 }
4189
4190 if (g4x_compute_wm0(dev, 1,
4191 &sandybridge_display_wm_info, latency,
4192 &sandybridge_cursor_wm_info, latency,
4193 &plane_wm, &cursor_wm)) {
4194 I915_WRITE(WM0_PIPEB_ILK,
4195 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4196 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4197 " plane %d, cursor: %d\n",
4198 plane_wm, cursor_wm);
4199 enabled |= 2;
4200 }
4201
4202 /*
4203 * Calculate and update the self-refresh watermark only when one
4204 * display plane is used.
4205 *
4206 * SNB support 3 levels of watermark.
4207 *
4208 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4209 * and disabled in the descending order
4210 *
4211 */
4212 I915_WRITE(WM3_LP_ILK, 0);
4213 I915_WRITE(WM2_LP_ILK, 0);
4214 I915_WRITE(WM1_LP_ILK, 0);
4215
4216 if (!single_plane_enabled(enabled))
4217 return;
4218 enabled = ffs(enabled) - 1;
4219
4220 /* WM1 */
4221 if (!ironlake_compute_srwm(dev, 1, enabled,
4222 SNB_READ_WM1_LATENCY() * 500,
4223 &sandybridge_display_srwm_info,
4224 &sandybridge_cursor_srwm_info,
4225 &fbc_wm, &plane_wm, &cursor_wm))
4226 return;
4227
4228 I915_WRITE(WM1_LP_ILK,
4229 WM1_LP_SR_EN |
4230 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4231 (fbc_wm << WM1_LP_FBC_SHIFT) |
4232 (plane_wm << WM1_LP_SR_SHIFT) |
4233 cursor_wm);
4234
4235 /* WM2 */
4236 if (!ironlake_compute_srwm(dev, 2, enabled,
4237 SNB_READ_WM2_LATENCY() * 500,
4238 &sandybridge_display_srwm_info,
4239 &sandybridge_cursor_srwm_info,
4240 &fbc_wm, &plane_wm, &cursor_wm))
4241 return;
4242
4243 I915_WRITE(WM2_LP_ILK,
4244 WM2_LP_EN |
4245 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4246 (fbc_wm << WM1_LP_FBC_SHIFT) |
4247 (plane_wm << WM1_LP_SR_SHIFT) |
4248 cursor_wm);
4249
4250 /* WM3 */
4251 if (!ironlake_compute_srwm(dev, 3, enabled,
4252 SNB_READ_WM3_LATENCY() * 500,
4253 &sandybridge_display_srwm_info,
4254 &sandybridge_cursor_srwm_info,
4255 &fbc_wm, &plane_wm, &cursor_wm))
4256 return;
4257
4258 I915_WRITE(WM3_LP_ILK,
4259 WM3_LP_EN |
4260 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4261 (fbc_wm << WM1_LP_FBC_SHIFT) |
4262 (plane_wm << WM1_LP_SR_SHIFT) |
4263 cursor_wm);
4264 }
4265
4266 /**
4267 * intel_update_watermarks - update FIFO watermark values based on current modes
4268 *
4269 * Calculate watermark values for the various WM regs based on current mode
4270 * and plane configuration.
4271 *
4272 * There are several cases to deal with here:
4273 * - normal (i.e. non-self-refresh)
4274 * - self-refresh (SR) mode
4275 * - lines are large relative to FIFO size (buffer can hold up to 2)
4276 * - lines are small relative to FIFO size (buffer can hold more than 2
4277 * lines), so need to account for TLB latency
4278 *
4279 * The normal calculation is:
4280 * watermark = dotclock * bytes per pixel * latency
4281 * where latency is platform & configuration dependent (we assume pessimal
4282 * values here).
4283 *
4284 * The SR calculation is:
4285 * watermark = (trunc(latency/line time)+1) * surface width *
4286 * bytes per pixel
4287 * where
4288 * line time = htotal / dotclock
4289 * surface width = hdisplay for normal plane and 64 for cursor
4290 * and latency is assumed to be high, as above.
4291 *
4292 * The final value programmed to the register should always be rounded up,
4293 * and include an extra 2 entries to account for clock crossings.
4294 *
4295 * We don't use the sprite, so we can ignore that. And on Crestline we have
4296 * to set the non-SR watermarks to 8.
4297 */
4298 static void intel_update_watermarks(struct drm_device *dev)
4299 {
4300 struct drm_i915_private *dev_priv = dev->dev_private;
4301
4302 if (dev_priv->display.update_wm)
4303 dev_priv->display.update_wm(dev);
4304 }
4305
4306 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4307 {
4308 return dev_priv->lvds_use_ssc && i915_panel_use_ssc;
4309 }
4310
4311 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4312 struct drm_display_mode *mode,
4313 struct drm_display_mode *adjusted_mode,
4314 int x, int y,
4315 struct drm_framebuffer *old_fb)
4316 {
4317 struct drm_device *dev = crtc->dev;
4318 struct drm_i915_private *dev_priv = dev->dev_private;
4319 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4320 int pipe = intel_crtc->pipe;
4321 int plane = intel_crtc->plane;
4322 int refclk, num_connectors = 0;
4323 intel_clock_t clock, reduced_clock;
4324 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4325 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
4326 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4327 struct drm_mode_config *mode_config = &dev->mode_config;
4328 struct intel_encoder *encoder;
4329 const intel_limit_t *limit;
4330 int ret;
4331 u32 temp;
4332 u32 lvds_sync = 0;
4333
4334 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4335 if (encoder->base.crtc != crtc)
4336 continue;
4337
4338 switch (encoder->type) {
4339 case INTEL_OUTPUT_LVDS:
4340 is_lvds = true;
4341 break;
4342 case INTEL_OUTPUT_SDVO:
4343 case INTEL_OUTPUT_HDMI:
4344 is_sdvo = true;
4345 if (encoder->needs_tv_clock)
4346 is_tv = true;
4347 break;
4348 case INTEL_OUTPUT_DVO:
4349 is_dvo = true;
4350 break;
4351 case INTEL_OUTPUT_TVOUT:
4352 is_tv = true;
4353 break;
4354 case INTEL_OUTPUT_ANALOG:
4355 is_crt = true;
4356 break;
4357 case INTEL_OUTPUT_DISPLAYPORT:
4358 is_dp = true;
4359 break;
4360 }
4361
4362 num_connectors++;
4363 }
4364
4365 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4366 refclk = dev_priv->lvds_ssc_freq * 1000;
4367 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4368 refclk / 1000);
4369 } else if (!IS_GEN2(dev)) {
4370 refclk = 96000;
4371 } else {
4372 refclk = 48000;
4373 }
4374
4375 /*
4376 * Returns a set of divisors for the desired target clock with the given
4377 * refclk, or FALSE. The returned values represent the clock equation:
4378 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4379 */
4380 limit = intel_limit(crtc, refclk);
4381 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4382 if (!ok) {
4383 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4384 return -EINVAL;
4385 }
4386
4387 /* Ensure that the cursor is valid for the new mode before changing... */
4388 intel_crtc_update_cursor(crtc, true);
4389
4390 if (is_lvds && dev_priv->lvds_downclock_avail) {
4391 has_reduced_clock = limit->find_pll(limit, crtc,
4392 dev_priv->lvds_downclock,
4393 refclk,
4394 &reduced_clock);
4395 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4396 /*
4397 * If the different P is found, it means that we can't
4398 * switch the display clock by using the FP0/FP1.
4399 * In such case we will disable the LVDS downclock
4400 * feature.
4401 */
4402 DRM_DEBUG_KMS("Different P is found for "
4403 "LVDS clock/downclock\n");
4404 has_reduced_clock = 0;
4405 }
4406 }
4407 /* SDVO TV has fixed PLL values depend on its clock range,
4408 this mirrors vbios setting. */
4409 if (is_sdvo && is_tv) {
4410 if (adjusted_mode->clock >= 100000
4411 && adjusted_mode->clock < 140500) {
4412 clock.p1 = 2;
4413 clock.p2 = 10;
4414 clock.n = 3;
4415 clock.m1 = 16;
4416 clock.m2 = 8;
4417 } else if (adjusted_mode->clock >= 140500
4418 && adjusted_mode->clock <= 200000) {
4419 clock.p1 = 1;
4420 clock.p2 = 10;
4421 clock.n = 6;
4422 clock.m1 = 12;
4423 clock.m2 = 8;
4424 }
4425 }
4426
4427 if (IS_PINEVIEW(dev)) {
4428 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
4429 if (has_reduced_clock)
4430 fp2 = (1 << reduced_clock.n) << 16 |
4431 reduced_clock.m1 << 8 | reduced_clock.m2;
4432 } else {
4433 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4434 if (has_reduced_clock)
4435 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4436 reduced_clock.m2;
4437 }
4438
4439 dpll = DPLL_VGA_MODE_DIS;
4440
4441 if (!IS_GEN2(dev)) {
4442 if (is_lvds)
4443 dpll |= DPLLB_MODE_LVDS;
4444 else
4445 dpll |= DPLLB_MODE_DAC_SERIAL;
4446 if (is_sdvo) {
4447 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4448 if (pixel_multiplier > 1) {
4449 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4450 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4451 }
4452 dpll |= DPLL_DVO_HIGH_SPEED;
4453 }
4454 if (is_dp)
4455 dpll |= DPLL_DVO_HIGH_SPEED;
4456
4457 /* compute bitmask from p1 value */
4458 if (IS_PINEVIEW(dev))
4459 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4460 else {
4461 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4462 if (IS_G4X(dev) && has_reduced_clock)
4463 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4464 }
4465 switch (clock.p2) {
4466 case 5:
4467 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4468 break;
4469 case 7:
4470 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4471 break;
4472 case 10:
4473 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4474 break;
4475 case 14:
4476 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4477 break;
4478 }
4479 if (INTEL_INFO(dev)->gen >= 4)
4480 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4481 } else {
4482 if (is_lvds) {
4483 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4484 } else {
4485 if (clock.p1 == 2)
4486 dpll |= PLL_P1_DIVIDE_BY_TWO;
4487 else
4488 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4489 if (clock.p2 == 4)
4490 dpll |= PLL_P2_DIVIDE_BY_4;
4491 }
4492 }
4493
4494 if (is_sdvo && is_tv)
4495 dpll |= PLL_REF_INPUT_TVCLKINBC;
4496 else if (is_tv)
4497 /* XXX: just matching BIOS for now */
4498 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4499 dpll |= 3;
4500 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4501 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4502 else
4503 dpll |= PLL_REF_INPUT_DREFCLK;
4504
4505 /* setup pipeconf */
4506 pipeconf = I915_READ(PIPECONF(pipe));
4507
4508 /* Set up the display plane register */
4509 dspcntr = DISPPLANE_GAMMA_ENABLE;
4510
4511 /* Ironlake's plane is forced to pipe, bit 24 is to
4512 enable color space conversion */
4513 if (pipe == 0)
4514 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4515 else
4516 dspcntr |= DISPPLANE_SEL_PIPE_B;
4517
4518 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4519 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4520 * core speed.
4521 *
4522 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4523 * pipe == 0 check?
4524 */
4525 if (mode->clock >
4526 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4527 pipeconf |= PIPECONF_DOUBLE_WIDE;
4528 else
4529 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4530 }
4531
4532 dpll |= DPLL_VCO_ENABLE;
4533
4534 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4535 drm_mode_debug_printmodeline(mode);
4536
4537 I915_WRITE(FP0(pipe), fp);
4538 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4539
4540 POSTING_READ(DPLL(pipe));
4541 udelay(150);
4542
4543 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4544 * This is an exception to the general rule that mode_set doesn't turn
4545 * things on.
4546 */
4547 if (is_lvds) {
4548 temp = I915_READ(LVDS);
4549 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4550 if (pipe == 1) {
4551 temp |= LVDS_PIPEB_SELECT;
4552 } else {
4553 temp &= ~LVDS_PIPEB_SELECT;
4554 }
4555 /* set the corresponsding LVDS_BORDER bit */
4556 temp |= dev_priv->lvds_border_bits;
4557 /* Set the B0-B3 data pairs corresponding to whether we're going to
4558 * set the DPLLs for dual-channel mode or not.
4559 */
4560 if (clock.p2 == 7)
4561 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4562 else
4563 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4564
4565 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4566 * appropriately here, but we need to look more thoroughly into how
4567 * panels behave in the two modes.
4568 */
4569 /* set the dithering flag on LVDS as needed */
4570 if (INTEL_INFO(dev)->gen >= 4) {
4571 if (dev_priv->lvds_dither)
4572 temp |= LVDS_ENABLE_DITHER;
4573 else
4574 temp &= ~LVDS_ENABLE_DITHER;
4575 }
4576 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4577 lvds_sync |= LVDS_HSYNC_POLARITY;
4578 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4579 lvds_sync |= LVDS_VSYNC_POLARITY;
4580 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
4581 != lvds_sync) {
4582 char flags[2] = "-+";
4583 DRM_INFO("Changing LVDS panel from "
4584 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
4585 flags[!(temp & LVDS_HSYNC_POLARITY)],
4586 flags[!(temp & LVDS_VSYNC_POLARITY)],
4587 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
4588 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
4589 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4590 temp |= lvds_sync;
4591 }
4592 I915_WRITE(LVDS, temp);
4593 }
4594
4595 if (is_dp) {
4596 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4597 }
4598
4599 I915_WRITE(DPLL(pipe), dpll);
4600
4601 /* Wait for the clocks to stabilize. */
4602 POSTING_READ(DPLL(pipe));
4603 udelay(150);
4604
4605 if (INTEL_INFO(dev)->gen >= 4) {
4606 temp = 0;
4607 if (is_sdvo) {
4608 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4609 if (temp > 1)
4610 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4611 else
4612 temp = 0;
4613 }
4614 I915_WRITE(DPLL_MD(pipe), temp);
4615 } else {
4616 /* The pixel multiplier can only be updated once the
4617 * DPLL is enabled and the clocks are stable.
4618 *
4619 * So write it again.
4620 */
4621 I915_WRITE(DPLL(pipe), dpll);
4622 }
4623
4624 intel_crtc->lowfreq_avail = false;
4625 if (is_lvds && has_reduced_clock && i915_powersave) {
4626 I915_WRITE(FP1(pipe), fp2);
4627 intel_crtc->lowfreq_avail = true;
4628 if (HAS_PIPE_CXSR(dev)) {
4629 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4630 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4631 }
4632 } else {
4633 I915_WRITE(FP1(pipe), fp);
4634 if (HAS_PIPE_CXSR(dev)) {
4635 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4636 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4637 }
4638 }
4639
4640 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4641 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4642 /* the chip adds 2 halflines automatically */
4643 adjusted_mode->crtc_vdisplay -= 1;
4644 adjusted_mode->crtc_vtotal -= 1;
4645 adjusted_mode->crtc_vblank_start -= 1;
4646 adjusted_mode->crtc_vblank_end -= 1;
4647 adjusted_mode->crtc_vsync_end -= 1;
4648 adjusted_mode->crtc_vsync_start -= 1;
4649 } else
4650 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4651
4652 I915_WRITE(HTOTAL(pipe),
4653 (adjusted_mode->crtc_hdisplay - 1) |
4654 ((adjusted_mode->crtc_htotal - 1) << 16));
4655 I915_WRITE(HBLANK(pipe),
4656 (adjusted_mode->crtc_hblank_start - 1) |
4657 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4658 I915_WRITE(HSYNC(pipe),
4659 (adjusted_mode->crtc_hsync_start - 1) |
4660 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4661
4662 I915_WRITE(VTOTAL(pipe),
4663 (adjusted_mode->crtc_vdisplay - 1) |
4664 ((adjusted_mode->crtc_vtotal - 1) << 16));
4665 I915_WRITE(VBLANK(pipe),
4666 (adjusted_mode->crtc_vblank_start - 1) |
4667 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4668 I915_WRITE(VSYNC(pipe),
4669 (adjusted_mode->crtc_vsync_start - 1) |
4670 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4671
4672 /* pipesrc and dspsize control the size that is scaled from,
4673 * which should always be the user's requested size.
4674 */
4675 I915_WRITE(DSPSIZE(plane),
4676 ((mode->vdisplay - 1) << 16) |
4677 (mode->hdisplay - 1));
4678 I915_WRITE(DSPPOS(plane), 0);
4679 I915_WRITE(PIPESRC(pipe),
4680 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4681
4682 I915_WRITE(PIPECONF(pipe), pipeconf);
4683 POSTING_READ(PIPECONF(pipe));
4684 intel_enable_pipe(dev_priv, pipe, false);
4685
4686 intel_wait_for_vblank(dev, pipe);
4687
4688 I915_WRITE(DSPCNTR(plane), dspcntr);
4689 POSTING_READ(DSPCNTR(plane));
4690
4691 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4692
4693 intel_update_watermarks(dev);
4694
4695 return ret;
4696 }
4697
4698 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4699 struct drm_display_mode *mode,
4700 struct drm_display_mode *adjusted_mode,
4701 int x, int y,
4702 struct drm_framebuffer *old_fb)
4703 {
4704 struct drm_device *dev = crtc->dev;
4705 struct drm_i915_private *dev_priv = dev->dev_private;
4706 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4707 int pipe = intel_crtc->pipe;
4708 int plane = intel_crtc->plane;
4709 int refclk, num_connectors = 0;
4710 intel_clock_t clock, reduced_clock;
4711 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4712 bool ok, has_reduced_clock = false, is_sdvo = false;
4713 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4714 struct intel_encoder *has_edp_encoder = NULL;
4715 struct drm_mode_config *mode_config = &dev->mode_config;
4716 struct intel_encoder *encoder;
4717 const intel_limit_t *limit;
4718 int ret;
4719 struct fdi_m_n m_n = {0};
4720 u32 temp;
4721 u32 lvds_sync = 0;
4722 int target_clock, pixel_multiplier, lane, link_bw, bpp, factor;
4723
4724 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4725 if (encoder->base.crtc != crtc)
4726 continue;
4727
4728 switch (encoder->type) {
4729 case INTEL_OUTPUT_LVDS:
4730 is_lvds = true;
4731 break;
4732 case INTEL_OUTPUT_SDVO:
4733 case INTEL_OUTPUT_HDMI:
4734 is_sdvo = true;
4735 if (encoder->needs_tv_clock)
4736 is_tv = true;
4737 break;
4738 case INTEL_OUTPUT_TVOUT:
4739 is_tv = true;
4740 break;
4741 case INTEL_OUTPUT_ANALOG:
4742 is_crt = true;
4743 break;
4744 case INTEL_OUTPUT_DISPLAYPORT:
4745 is_dp = true;
4746 break;
4747 case INTEL_OUTPUT_EDP:
4748 has_edp_encoder = encoder;
4749 break;
4750 }
4751
4752 num_connectors++;
4753 }
4754
4755 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4756 refclk = dev_priv->lvds_ssc_freq * 1000;
4757 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4758 refclk / 1000);
4759 } else {
4760 refclk = 96000;
4761 if (!has_edp_encoder ||
4762 intel_encoder_is_pch_edp(&has_edp_encoder->base))
4763 refclk = 120000; /* 120Mhz refclk */
4764 }
4765
4766 /*
4767 * Returns a set of divisors for the desired target clock with the given
4768 * refclk, or FALSE. The returned values represent the clock equation:
4769 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4770 */
4771 limit = intel_limit(crtc, refclk);
4772 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4773 if (!ok) {
4774 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4775 return -EINVAL;
4776 }
4777
4778 /* Ensure that the cursor is valid for the new mode before changing... */
4779 intel_crtc_update_cursor(crtc, true);
4780
4781 if (is_lvds && dev_priv->lvds_downclock_avail) {
4782 has_reduced_clock = limit->find_pll(limit, crtc,
4783 dev_priv->lvds_downclock,
4784 refclk,
4785 &reduced_clock);
4786 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4787 /*
4788 * If the different P is found, it means that we can't
4789 * switch the display clock by using the FP0/FP1.
4790 * In such case we will disable the LVDS downclock
4791 * feature.
4792 */
4793 DRM_DEBUG_KMS("Different P is found for "
4794 "LVDS clock/downclock\n");
4795 has_reduced_clock = 0;
4796 }
4797 }
4798 /* SDVO TV has fixed PLL values depend on its clock range,
4799 this mirrors vbios setting. */
4800 if (is_sdvo && is_tv) {
4801 if (adjusted_mode->clock >= 100000
4802 && adjusted_mode->clock < 140500) {
4803 clock.p1 = 2;
4804 clock.p2 = 10;
4805 clock.n = 3;
4806 clock.m1 = 16;
4807 clock.m2 = 8;
4808 } else if (adjusted_mode->clock >= 140500
4809 && adjusted_mode->clock <= 200000) {
4810 clock.p1 = 1;
4811 clock.p2 = 10;
4812 clock.n = 6;
4813 clock.m1 = 12;
4814 clock.m2 = 8;
4815 }
4816 }
4817
4818 /* FDI link */
4819 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4820 lane = 0;
4821 /* CPU eDP doesn't require FDI link, so just set DP M/N
4822 according to current link config */
4823 if (has_edp_encoder &&
4824 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4825 target_clock = mode->clock;
4826 intel_edp_link_config(has_edp_encoder,
4827 &lane, &link_bw);
4828 } else {
4829 /* [e]DP over FDI requires target mode clock
4830 instead of link clock */
4831 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
4832 target_clock = mode->clock;
4833 else
4834 target_clock = adjusted_mode->clock;
4835
4836 /* FDI is a binary signal running at ~2.7GHz, encoding
4837 * each output octet as 10 bits. The actual frequency
4838 * is stored as a divider into a 100MHz clock, and the
4839 * mode pixel clock is stored in units of 1KHz.
4840 * Hence the bw of each lane in terms of the mode signal
4841 * is:
4842 */
4843 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4844 }
4845
4846 /* determine panel color depth */
4847 temp = I915_READ(PIPECONF(pipe));
4848 temp &= ~PIPE_BPC_MASK;
4849 if (is_lvds) {
4850 /* the BPC will be 6 if it is 18-bit LVDS panel */
4851 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
4852 temp |= PIPE_8BPC;
4853 else
4854 temp |= PIPE_6BPC;
4855 } else if (has_edp_encoder) {
4856 switch (dev_priv->edp.bpp/3) {
4857 case 8:
4858 temp |= PIPE_8BPC;
4859 break;
4860 case 10:
4861 temp |= PIPE_10BPC;
4862 break;
4863 case 6:
4864 temp |= PIPE_6BPC;
4865 break;
4866 case 12:
4867 temp |= PIPE_12BPC;
4868 break;
4869 }
4870 } else
4871 temp |= PIPE_8BPC;
4872 I915_WRITE(PIPECONF(pipe), temp);
4873
4874 switch (temp & PIPE_BPC_MASK) {
4875 case PIPE_8BPC:
4876 bpp = 24;
4877 break;
4878 case PIPE_10BPC:
4879 bpp = 30;
4880 break;
4881 case PIPE_6BPC:
4882 bpp = 18;
4883 break;
4884 case PIPE_12BPC:
4885 bpp = 36;
4886 break;
4887 default:
4888 DRM_ERROR("unknown pipe bpc value\n");
4889 bpp = 24;
4890 }
4891
4892 if (!lane) {
4893 /*
4894 * Account for spread spectrum to avoid
4895 * oversubscribing the link. Max center spread
4896 * is 2.5%; use 5% for safety's sake.
4897 */
4898 u32 bps = target_clock * bpp * 21 / 20;
4899 lane = bps / (link_bw * 8) + 1;
4900 }
4901
4902 intel_crtc->fdi_lanes = lane;
4903
4904 if (pixel_multiplier > 1)
4905 link_bw *= pixel_multiplier;
4906 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
4907
4908 /* Ironlake: try to setup display ref clock before DPLL
4909 * enabling. This is only under driver's control after
4910 * PCH B stepping, previous chipset stepping should be
4911 * ignoring this setting.
4912 */
4913 temp = I915_READ(PCH_DREF_CONTROL);
4914 /* Always enable nonspread source */
4915 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4916 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4917 temp &= ~DREF_SSC_SOURCE_MASK;
4918 temp |= DREF_SSC_SOURCE_ENABLE;
4919 I915_WRITE(PCH_DREF_CONTROL, temp);
4920
4921 POSTING_READ(PCH_DREF_CONTROL);
4922 udelay(200);
4923
4924 if (has_edp_encoder) {
4925 if (intel_panel_use_ssc(dev_priv)) {
4926 temp |= DREF_SSC1_ENABLE;
4927 I915_WRITE(PCH_DREF_CONTROL, temp);
4928
4929 POSTING_READ(PCH_DREF_CONTROL);
4930 udelay(200);
4931 }
4932 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4933
4934 /* Enable CPU source on CPU attached eDP */
4935 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4936 if (intel_panel_use_ssc(dev_priv))
4937 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4938 else
4939 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4940 } else {
4941 /* Enable SSC on PCH eDP if needed */
4942 if (intel_panel_use_ssc(dev_priv)) {
4943 DRM_ERROR("enabling SSC on PCH\n");
4944 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
4945 }
4946 }
4947 I915_WRITE(PCH_DREF_CONTROL, temp);
4948 POSTING_READ(PCH_DREF_CONTROL);
4949 udelay(200);
4950 }
4951
4952 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4953 if (has_reduced_clock)
4954 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4955 reduced_clock.m2;
4956
4957 /* Enable autotuning of the PLL clock (if permissible) */
4958 factor = 21;
4959 if (is_lvds) {
4960 if ((intel_panel_use_ssc(dev_priv) &&
4961 dev_priv->lvds_ssc_freq == 100) ||
4962 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4963 factor = 25;
4964 } else if (is_sdvo && is_tv)
4965 factor = 20;
4966
4967 if (clock.m1 < factor * clock.n)
4968 fp |= FP_CB_TUNE;
4969
4970 dpll = 0;
4971
4972 if (is_lvds)
4973 dpll |= DPLLB_MODE_LVDS;
4974 else
4975 dpll |= DPLLB_MODE_DAC_SERIAL;
4976 if (is_sdvo) {
4977 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4978 if (pixel_multiplier > 1) {
4979 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4980 }
4981 dpll |= DPLL_DVO_HIGH_SPEED;
4982 }
4983 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
4984 dpll |= DPLL_DVO_HIGH_SPEED;
4985
4986 /* compute bitmask from p1 value */
4987 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4988 /* also FPA1 */
4989 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4990
4991 switch (clock.p2) {
4992 case 5:
4993 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4994 break;
4995 case 7:
4996 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4997 break;
4998 case 10:
4999 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5000 break;
5001 case 14:
5002 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5003 break;
5004 }
5005
5006 if (is_sdvo && is_tv)
5007 dpll |= PLL_REF_INPUT_TVCLKINBC;
5008 else if (is_tv)
5009 /* XXX: just matching BIOS for now */
5010 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5011 dpll |= 3;
5012 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5013 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5014 else
5015 dpll |= PLL_REF_INPUT_DREFCLK;
5016
5017 /* setup pipeconf */
5018 pipeconf = I915_READ(PIPECONF(pipe));
5019
5020 /* Set up the display plane register */
5021 dspcntr = DISPPLANE_GAMMA_ENABLE;
5022
5023 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5024 drm_mode_debug_printmodeline(mode);
5025
5026 /* PCH eDP needs FDI, but CPU eDP does not */
5027 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5028 I915_WRITE(PCH_FP0(pipe), fp);
5029 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5030
5031 POSTING_READ(PCH_DPLL(pipe));
5032 udelay(150);
5033 }
5034
5035 /* enable transcoder DPLL */
5036 if (HAS_PCH_CPT(dev)) {
5037 temp = I915_READ(PCH_DPLL_SEL);
5038 switch (pipe) {
5039 case 0:
5040 temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
5041 break;
5042 case 1:
5043 temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
5044 break;
5045 case 2:
5046 /* FIXME: manage transcoder PLLs? */
5047 temp |= TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL;
5048 break;
5049 default:
5050 BUG();
5051 }
5052 I915_WRITE(PCH_DPLL_SEL, temp);
5053
5054 POSTING_READ(PCH_DPLL_SEL);
5055 udelay(150);
5056 }
5057
5058 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5059 * This is an exception to the general rule that mode_set doesn't turn
5060 * things on.
5061 */
5062 if (is_lvds) {
5063 temp = I915_READ(PCH_LVDS);
5064 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5065 if (pipe == 1) {
5066 if (HAS_PCH_CPT(dev))
5067 temp |= PORT_TRANS_B_SEL_CPT;
5068 else
5069 temp |= LVDS_PIPEB_SELECT;
5070 } else {
5071 if (HAS_PCH_CPT(dev))
5072 temp &= ~PORT_TRANS_SEL_MASK;
5073 else
5074 temp &= ~LVDS_PIPEB_SELECT;
5075 }
5076 /* set the corresponsding LVDS_BORDER bit */
5077 temp |= dev_priv->lvds_border_bits;
5078 /* Set the B0-B3 data pairs corresponding to whether we're going to
5079 * set the DPLLs for dual-channel mode or not.
5080 */
5081 if (clock.p2 == 7)
5082 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5083 else
5084 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5085
5086 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5087 * appropriately here, but we need to look more thoroughly into how
5088 * panels behave in the two modes.
5089 */
5090 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5091 lvds_sync |= LVDS_HSYNC_POLARITY;
5092 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5093 lvds_sync |= LVDS_VSYNC_POLARITY;
5094 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5095 != lvds_sync) {
5096 char flags[2] = "-+";
5097 DRM_INFO("Changing LVDS panel from "
5098 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5099 flags[!(temp & LVDS_HSYNC_POLARITY)],
5100 flags[!(temp & LVDS_VSYNC_POLARITY)],
5101 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5102 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5103 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5104 temp |= lvds_sync;
5105 }
5106 I915_WRITE(PCH_LVDS, temp);
5107 }
5108
5109 /* set the dithering flag and clear for anything other than a panel. */
5110 pipeconf &= ~PIPECONF_DITHER_EN;
5111 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5112 if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
5113 pipeconf |= PIPECONF_DITHER_EN;
5114 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
5115 }
5116
5117 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5118 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5119 } else {
5120 /* For non-DP output, clear any trans DP clock recovery setting.*/
5121 I915_WRITE(TRANSDATA_M1(pipe), 0);
5122 I915_WRITE(TRANSDATA_N1(pipe), 0);
5123 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5124 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5125 }
5126
5127 if (!has_edp_encoder ||
5128 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5129 I915_WRITE(PCH_DPLL(pipe), dpll);
5130
5131 /* Wait for the clocks to stabilize. */
5132 POSTING_READ(PCH_DPLL(pipe));
5133 udelay(150);
5134
5135 /* The pixel multiplier can only be updated once the
5136 * DPLL is enabled and the clocks are stable.
5137 *
5138 * So write it again.
5139 */
5140 I915_WRITE(PCH_DPLL(pipe), dpll);
5141 }
5142
5143 intel_crtc->lowfreq_avail = false;
5144 if (is_lvds && has_reduced_clock && i915_powersave) {
5145 I915_WRITE(PCH_FP1(pipe), fp2);
5146 intel_crtc->lowfreq_avail = true;
5147 if (HAS_PIPE_CXSR(dev)) {
5148 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5149 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5150 }
5151 } else {
5152 I915_WRITE(PCH_FP1(pipe), fp);
5153 if (HAS_PIPE_CXSR(dev)) {
5154 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5155 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5156 }
5157 }
5158
5159 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5160 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5161 /* the chip adds 2 halflines automatically */
5162 adjusted_mode->crtc_vdisplay -= 1;
5163 adjusted_mode->crtc_vtotal -= 1;
5164 adjusted_mode->crtc_vblank_start -= 1;
5165 adjusted_mode->crtc_vblank_end -= 1;
5166 adjusted_mode->crtc_vsync_end -= 1;
5167 adjusted_mode->crtc_vsync_start -= 1;
5168 } else
5169 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5170
5171 I915_WRITE(HTOTAL(pipe),
5172 (adjusted_mode->crtc_hdisplay - 1) |
5173 ((adjusted_mode->crtc_htotal - 1) << 16));
5174 I915_WRITE(HBLANK(pipe),
5175 (adjusted_mode->crtc_hblank_start - 1) |
5176 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5177 I915_WRITE(HSYNC(pipe),
5178 (adjusted_mode->crtc_hsync_start - 1) |
5179 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5180
5181 I915_WRITE(VTOTAL(pipe),
5182 (adjusted_mode->crtc_vdisplay - 1) |
5183 ((adjusted_mode->crtc_vtotal - 1) << 16));
5184 I915_WRITE(VBLANK(pipe),
5185 (adjusted_mode->crtc_vblank_start - 1) |
5186 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5187 I915_WRITE(VSYNC(pipe),
5188 (adjusted_mode->crtc_vsync_start - 1) |
5189 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5190
5191 /* pipesrc controls the size that is scaled from, which should
5192 * always be the user's requested size.
5193 */
5194 I915_WRITE(PIPESRC(pipe),
5195 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5196
5197 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5198 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5199 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5200 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
5201
5202 if (has_edp_encoder &&
5203 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5204 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5205 }
5206
5207 I915_WRITE(PIPECONF(pipe), pipeconf);
5208 POSTING_READ(PIPECONF(pipe));
5209
5210 intel_wait_for_vblank(dev, pipe);
5211
5212 if (IS_GEN5(dev)) {
5213 /* enable address swizzle for tiling buffer */
5214 temp = I915_READ(DISP_ARB_CTL);
5215 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5216 }
5217
5218 I915_WRITE(DSPCNTR(plane), dspcntr);
5219 POSTING_READ(DSPCNTR(plane));
5220 if (!HAS_PCH_SPLIT(dev))
5221 intel_enable_plane(dev_priv, plane, pipe);
5222
5223 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5224
5225 intel_update_watermarks(dev);
5226
5227 return ret;
5228 }
5229
5230 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5231 struct drm_display_mode *mode,
5232 struct drm_display_mode *adjusted_mode,
5233 int x, int y,
5234 struct drm_framebuffer *old_fb)
5235 {
5236 struct drm_device *dev = crtc->dev;
5237 struct drm_i915_private *dev_priv = dev->dev_private;
5238 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5239 int pipe = intel_crtc->pipe;
5240 int ret;
5241
5242 drm_vblank_pre_modeset(dev, pipe);
5243
5244 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5245 x, y, old_fb);
5246
5247 drm_vblank_post_modeset(dev, pipe);
5248
5249 return ret;
5250 }
5251
5252 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5253 void intel_crtc_load_lut(struct drm_crtc *crtc)
5254 {
5255 struct drm_device *dev = crtc->dev;
5256 struct drm_i915_private *dev_priv = dev->dev_private;
5257 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5258 int palreg = PALETTE(intel_crtc->pipe);
5259 int i;
5260
5261 /* The clocks have to be on to load the palette. */
5262 if (!crtc->enabled)
5263 return;
5264
5265 /* use legacy palette for Ironlake */
5266 if (HAS_PCH_SPLIT(dev))
5267 palreg = LGC_PALETTE(intel_crtc->pipe);
5268
5269 for (i = 0; i < 256; i++) {
5270 I915_WRITE(palreg + 4 * i,
5271 (intel_crtc->lut_r[i] << 16) |
5272 (intel_crtc->lut_g[i] << 8) |
5273 intel_crtc->lut_b[i]);
5274 }
5275 }
5276
5277 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5278 {
5279 struct drm_device *dev = crtc->dev;
5280 struct drm_i915_private *dev_priv = dev->dev_private;
5281 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5282 bool visible = base != 0;
5283 u32 cntl;
5284
5285 if (intel_crtc->cursor_visible == visible)
5286 return;
5287
5288 cntl = I915_READ(_CURACNTR);
5289 if (visible) {
5290 /* On these chipsets we can only modify the base whilst
5291 * the cursor is disabled.
5292 */
5293 I915_WRITE(_CURABASE, base);
5294
5295 cntl &= ~(CURSOR_FORMAT_MASK);
5296 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5297 cntl |= CURSOR_ENABLE |
5298 CURSOR_GAMMA_ENABLE |
5299 CURSOR_FORMAT_ARGB;
5300 } else
5301 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5302 I915_WRITE(_CURACNTR, cntl);
5303
5304 intel_crtc->cursor_visible = visible;
5305 }
5306
5307 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5308 {
5309 struct drm_device *dev = crtc->dev;
5310 struct drm_i915_private *dev_priv = dev->dev_private;
5311 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5312 int pipe = intel_crtc->pipe;
5313 bool visible = base != 0;
5314
5315 if (intel_crtc->cursor_visible != visible) {
5316 uint32_t cntl = I915_READ(CURCNTR(pipe));
5317 if (base) {
5318 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5319 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5320 cntl |= pipe << 28; /* Connect to correct pipe */
5321 } else {
5322 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5323 cntl |= CURSOR_MODE_DISABLE;
5324 }
5325 I915_WRITE(CURCNTR(pipe), cntl);
5326
5327 intel_crtc->cursor_visible = visible;
5328 }
5329 /* and commit changes on next vblank */
5330 I915_WRITE(CURBASE(pipe), base);
5331 }
5332
5333 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5334 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5335 bool on)
5336 {
5337 struct drm_device *dev = crtc->dev;
5338 struct drm_i915_private *dev_priv = dev->dev_private;
5339 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5340 int pipe = intel_crtc->pipe;
5341 int x = intel_crtc->cursor_x;
5342 int y = intel_crtc->cursor_y;
5343 u32 base, pos;
5344 bool visible;
5345
5346 pos = 0;
5347
5348 if (on && crtc->enabled && crtc->fb) {
5349 base = intel_crtc->cursor_addr;
5350 if (x > (int) crtc->fb->width)
5351 base = 0;
5352
5353 if (y > (int) crtc->fb->height)
5354 base = 0;
5355 } else
5356 base = 0;
5357
5358 if (x < 0) {
5359 if (x + intel_crtc->cursor_width < 0)
5360 base = 0;
5361
5362 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5363 x = -x;
5364 }
5365 pos |= x << CURSOR_X_SHIFT;
5366
5367 if (y < 0) {
5368 if (y + intel_crtc->cursor_height < 0)
5369 base = 0;
5370
5371 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5372 y = -y;
5373 }
5374 pos |= y << CURSOR_Y_SHIFT;
5375
5376 visible = base != 0;
5377 if (!visible && !intel_crtc->cursor_visible)
5378 return;
5379
5380 I915_WRITE(CURPOS(pipe), pos);
5381 if (IS_845G(dev) || IS_I865G(dev))
5382 i845_update_cursor(crtc, base);
5383 else
5384 i9xx_update_cursor(crtc, base);
5385
5386 if (visible)
5387 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
5388 }
5389
5390 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5391 struct drm_file *file,
5392 uint32_t handle,
5393 uint32_t width, uint32_t height)
5394 {
5395 struct drm_device *dev = crtc->dev;
5396 struct drm_i915_private *dev_priv = dev->dev_private;
5397 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5398 struct drm_i915_gem_object *obj;
5399 uint32_t addr;
5400 int ret;
5401
5402 DRM_DEBUG_KMS("\n");
5403
5404 /* if we want to turn off the cursor ignore width and height */
5405 if (!handle) {
5406 DRM_DEBUG_KMS("cursor off\n");
5407 addr = 0;
5408 obj = NULL;
5409 mutex_lock(&dev->struct_mutex);
5410 goto finish;
5411 }
5412
5413 /* Currently we only support 64x64 cursors */
5414 if (width != 64 || height != 64) {
5415 DRM_ERROR("we currently only support 64x64 cursors\n");
5416 return -EINVAL;
5417 }
5418
5419 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5420 if (&obj->base == NULL)
5421 return -ENOENT;
5422
5423 if (obj->base.size < width * height * 4) {
5424 DRM_ERROR("buffer is to small\n");
5425 ret = -ENOMEM;
5426 goto fail;
5427 }
5428
5429 /* we only need to pin inside GTT if cursor is non-phy */
5430 mutex_lock(&dev->struct_mutex);
5431 if (!dev_priv->info->cursor_needs_physical) {
5432 if (obj->tiling_mode) {
5433 DRM_ERROR("cursor cannot be tiled\n");
5434 ret = -EINVAL;
5435 goto fail_locked;
5436 }
5437
5438 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
5439 if (ret) {
5440 DRM_ERROR("failed to pin cursor bo\n");
5441 goto fail_locked;
5442 }
5443
5444 ret = i915_gem_object_set_to_gtt_domain(obj, 0);
5445 if (ret) {
5446 DRM_ERROR("failed to move cursor bo into the GTT\n");
5447 goto fail_unpin;
5448 }
5449
5450 ret = i915_gem_object_put_fence(obj);
5451 if (ret) {
5452 DRM_ERROR("failed to move cursor bo into the GTT\n");
5453 goto fail_unpin;
5454 }
5455
5456 addr = obj->gtt_offset;
5457 } else {
5458 int align = IS_I830(dev) ? 16 * 1024 : 256;
5459 ret = i915_gem_attach_phys_object(dev, obj,
5460 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5461 align);
5462 if (ret) {
5463 DRM_ERROR("failed to attach phys object\n");
5464 goto fail_locked;
5465 }
5466 addr = obj->phys_obj->handle->busaddr;
5467 }
5468
5469 if (IS_GEN2(dev))
5470 I915_WRITE(CURSIZE, (height << 12) | width);
5471
5472 finish:
5473 if (intel_crtc->cursor_bo) {
5474 if (dev_priv->info->cursor_needs_physical) {
5475 if (intel_crtc->cursor_bo != obj)
5476 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5477 } else
5478 i915_gem_object_unpin(intel_crtc->cursor_bo);
5479 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5480 }
5481
5482 mutex_unlock(&dev->struct_mutex);
5483
5484 intel_crtc->cursor_addr = addr;
5485 intel_crtc->cursor_bo = obj;
5486 intel_crtc->cursor_width = width;
5487 intel_crtc->cursor_height = height;
5488
5489 intel_crtc_update_cursor(crtc, true);
5490
5491 return 0;
5492 fail_unpin:
5493 i915_gem_object_unpin(obj);
5494 fail_locked:
5495 mutex_unlock(&dev->struct_mutex);
5496 fail:
5497 drm_gem_object_unreference_unlocked(&obj->base);
5498 return ret;
5499 }
5500
5501 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5502 {
5503 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5504
5505 intel_crtc->cursor_x = x;
5506 intel_crtc->cursor_y = y;
5507
5508 intel_crtc_update_cursor(crtc, true);
5509
5510 return 0;
5511 }
5512
5513 /** Sets the color ramps on behalf of RandR */
5514 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5515 u16 blue, int regno)
5516 {
5517 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5518
5519 intel_crtc->lut_r[regno] = red >> 8;
5520 intel_crtc->lut_g[regno] = green >> 8;
5521 intel_crtc->lut_b[regno] = blue >> 8;
5522 }
5523
5524 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5525 u16 *blue, int regno)
5526 {
5527 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5528
5529 *red = intel_crtc->lut_r[regno] << 8;
5530 *green = intel_crtc->lut_g[regno] << 8;
5531 *blue = intel_crtc->lut_b[regno] << 8;
5532 }
5533
5534 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5535 u16 *blue, uint32_t start, uint32_t size)
5536 {
5537 int end = (start + size > 256) ? 256 : start + size, i;
5538 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5539
5540 for (i = start; i < end; i++) {
5541 intel_crtc->lut_r[i] = red[i] >> 8;
5542 intel_crtc->lut_g[i] = green[i] >> 8;
5543 intel_crtc->lut_b[i] = blue[i] >> 8;
5544 }
5545
5546 intel_crtc_load_lut(crtc);
5547 }
5548
5549 /**
5550 * Get a pipe with a simple mode set on it for doing load-based monitor
5551 * detection.
5552 *
5553 * It will be up to the load-detect code to adjust the pipe as appropriate for
5554 * its requirements. The pipe will be connected to no other encoders.
5555 *
5556 * Currently this code will only succeed if there is a pipe with no encoders
5557 * configured for it. In the future, it could choose to temporarily disable
5558 * some outputs to free up a pipe for its use.
5559 *
5560 * \return crtc, or NULL if no pipes are available.
5561 */
5562
5563 /* VESA 640x480x72Hz mode to set on the pipe */
5564 static struct drm_display_mode load_detect_mode = {
5565 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5566 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5567 };
5568
5569 static struct drm_framebuffer *
5570 intel_framebuffer_create(struct drm_device *dev,
5571 struct drm_mode_fb_cmd *mode_cmd,
5572 struct drm_i915_gem_object *obj)
5573 {
5574 struct intel_framebuffer *intel_fb;
5575 int ret;
5576
5577 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5578 if (!intel_fb) {
5579 drm_gem_object_unreference_unlocked(&obj->base);
5580 return ERR_PTR(-ENOMEM);
5581 }
5582
5583 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5584 if (ret) {
5585 drm_gem_object_unreference_unlocked(&obj->base);
5586 kfree(intel_fb);
5587 return ERR_PTR(ret);
5588 }
5589
5590 return &intel_fb->base;
5591 }
5592
5593 static u32
5594 intel_framebuffer_pitch_for_width(int width, int bpp)
5595 {
5596 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5597 return ALIGN(pitch, 64);
5598 }
5599
5600 static u32
5601 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5602 {
5603 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5604 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5605 }
5606
5607 static struct drm_framebuffer *
5608 intel_framebuffer_create_for_mode(struct drm_device *dev,
5609 struct drm_display_mode *mode,
5610 int depth, int bpp)
5611 {
5612 struct drm_i915_gem_object *obj;
5613 struct drm_mode_fb_cmd mode_cmd;
5614
5615 obj = i915_gem_alloc_object(dev,
5616 intel_framebuffer_size_for_mode(mode, bpp));
5617 if (obj == NULL)
5618 return ERR_PTR(-ENOMEM);
5619
5620 mode_cmd.width = mode->hdisplay;
5621 mode_cmd.height = mode->vdisplay;
5622 mode_cmd.depth = depth;
5623 mode_cmd.bpp = bpp;
5624 mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
5625
5626 return intel_framebuffer_create(dev, &mode_cmd, obj);
5627 }
5628
5629 static struct drm_framebuffer *
5630 mode_fits_in_fbdev(struct drm_device *dev,
5631 struct drm_display_mode *mode)
5632 {
5633 struct drm_i915_private *dev_priv = dev->dev_private;
5634 struct drm_i915_gem_object *obj;
5635 struct drm_framebuffer *fb;
5636
5637 if (dev_priv->fbdev == NULL)
5638 return NULL;
5639
5640 obj = dev_priv->fbdev->ifb.obj;
5641 if (obj == NULL)
5642 return NULL;
5643
5644 fb = &dev_priv->fbdev->ifb.base;
5645 if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
5646 fb->bits_per_pixel))
5647 return NULL;
5648
5649 if (obj->base.size < mode->vdisplay * fb->pitch)
5650 return NULL;
5651
5652 return fb;
5653 }
5654
5655 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5656 struct drm_connector *connector,
5657 struct drm_display_mode *mode,
5658 struct intel_load_detect_pipe *old)
5659 {
5660 struct intel_crtc *intel_crtc;
5661 struct drm_crtc *possible_crtc;
5662 struct drm_encoder *encoder = &intel_encoder->base;
5663 struct drm_crtc *crtc = NULL;
5664 struct drm_device *dev = encoder->dev;
5665 struct drm_framebuffer *old_fb;
5666 int i = -1;
5667
5668 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5669 connector->base.id, drm_get_connector_name(connector),
5670 encoder->base.id, drm_get_encoder_name(encoder));
5671
5672 /*
5673 * Algorithm gets a little messy:
5674 *
5675 * - if the connector already has an assigned crtc, use it (but make
5676 * sure it's on first)
5677 *
5678 * - try to find the first unused crtc that can drive this connector,
5679 * and use that if we find one
5680 */
5681
5682 /* See if we already have a CRTC for this connector */
5683 if (encoder->crtc) {
5684 crtc = encoder->crtc;
5685
5686 intel_crtc = to_intel_crtc(crtc);
5687 old->dpms_mode = intel_crtc->dpms_mode;
5688 old->load_detect_temp = false;
5689
5690 /* Make sure the crtc and connector are running */
5691 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5692 struct drm_encoder_helper_funcs *encoder_funcs;
5693 struct drm_crtc_helper_funcs *crtc_funcs;
5694
5695 crtc_funcs = crtc->helper_private;
5696 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5697
5698 encoder_funcs = encoder->helper_private;
5699 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5700 }
5701
5702 return true;
5703 }
5704
5705 /* Find an unused one (if possible) */
5706 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5707 i++;
5708 if (!(encoder->possible_crtcs & (1 << i)))
5709 continue;
5710 if (!possible_crtc->enabled) {
5711 crtc = possible_crtc;
5712 break;
5713 }
5714 }
5715
5716 /*
5717 * If we didn't find an unused CRTC, don't use any.
5718 */
5719 if (!crtc) {
5720 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5721 return false;
5722 }
5723
5724 encoder->crtc = crtc;
5725 connector->encoder = encoder;
5726
5727 intel_crtc = to_intel_crtc(crtc);
5728 old->dpms_mode = intel_crtc->dpms_mode;
5729 old->load_detect_temp = true;
5730 old->release_fb = NULL;
5731
5732 if (!mode)
5733 mode = &load_detect_mode;
5734
5735 old_fb = crtc->fb;
5736
5737 /* We need a framebuffer large enough to accommodate all accesses
5738 * that the plane may generate whilst we perform load detection.
5739 * We can not rely on the fbcon either being present (we get called
5740 * during its initialisation to detect all boot displays, or it may
5741 * not even exist) or that it is large enough to satisfy the
5742 * requested mode.
5743 */
5744 crtc->fb = mode_fits_in_fbdev(dev, mode);
5745 if (crtc->fb == NULL) {
5746 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5747 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5748 old->release_fb = crtc->fb;
5749 } else
5750 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5751 if (IS_ERR(crtc->fb)) {
5752 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5753 crtc->fb = old_fb;
5754 return false;
5755 }
5756
5757 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
5758 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
5759 if (old->release_fb)
5760 old->release_fb->funcs->destroy(old->release_fb);
5761 crtc->fb = old_fb;
5762 return false;
5763 }
5764
5765 /* let the connector get through one full cycle before testing */
5766 intel_wait_for_vblank(dev, intel_crtc->pipe);
5767
5768 return true;
5769 }
5770
5771 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
5772 struct drm_connector *connector,
5773 struct intel_load_detect_pipe *old)
5774 {
5775 struct drm_encoder *encoder = &intel_encoder->base;
5776 struct drm_device *dev = encoder->dev;
5777 struct drm_crtc *crtc = encoder->crtc;
5778 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5779 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5780
5781 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5782 connector->base.id, drm_get_connector_name(connector),
5783 encoder->base.id, drm_get_encoder_name(encoder));
5784
5785 if (old->load_detect_temp) {
5786 connector->encoder = NULL;
5787 drm_helper_disable_unused_functions(dev);
5788
5789 if (old->release_fb)
5790 old->release_fb->funcs->destroy(old->release_fb);
5791
5792 return;
5793 }
5794
5795 /* Switch crtc and encoder back off if necessary */
5796 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5797 encoder_funcs->dpms(encoder, old->dpms_mode);
5798 crtc_funcs->dpms(crtc, old->dpms_mode);
5799 }
5800 }
5801
5802 /* Returns the clock of the currently programmed mode of the given pipe. */
5803 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5804 {
5805 struct drm_i915_private *dev_priv = dev->dev_private;
5806 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5807 int pipe = intel_crtc->pipe;
5808 u32 dpll = I915_READ(DPLL(pipe));
5809 u32 fp;
5810 intel_clock_t clock;
5811
5812 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5813 fp = I915_READ(FP0(pipe));
5814 else
5815 fp = I915_READ(FP1(pipe));
5816
5817 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5818 if (IS_PINEVIEW(dev)) {
5819 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5820 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5821 } else {
5822 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5823 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5824 }
5825
5826 if (!IS_GEN2(dev)) {
5827 if (IS_PINEVIEW(dev))
5828 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5829 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
5830 else
5831 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5832 DPLL_FPA01_P1_POST_DIV_SHIFT);
5833
5834 switch (dpll & DPLL_MODE_MASK) {
5835 case DPLLB_MODE_DAC_SERIAL:
5836 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5837 5 : 10;
5838 break;
5839 case DPLLB_MODE_LVDS:
5840 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5841 7 : 14;
5842 break;
5843 default:
5844 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5845 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5846 return 0;
5847 }
5848
5849 /* XXX: Handle the 100Mhz refclk */
5850 intel_clock(dev, 96000, &clock);
5851 } else {
5852 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5853
5854 if (is_lvds) {
5855 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5856 DPLL_FPA01_P1_POST_DIV_SHIFT);
5857 clock.p2 = 14;
5858
5859 if ((dpll & PLL_REF_INPUT_MASK) ==
5860 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5861 /* XXX: might not be 66MHz */
5862 intel_clock(dev, 66000, &clock);
5863 } else
5864 intel_clock(dev, 48000, &clock);
5865 } else {
5866 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5867 clock.p1 = 2;
5868 else {
5869 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5870 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5871 }
5872 if (dpll & PLL_P2_DIVIDE_BY_4)
5873 clock.p2 = 4;
5874 else
5875 clock.p2 = 2;
5876
5877 intel_clock(dev, 48000, &clock);
5878 }
5879 }
5880
5881 /* XXX: It would be nice to validate the clocks, but we can't reuse
5882 * i830PllIsValid() because it relies on the xf86_config connector
5883 * configuration being accurate, which it isn't necessarily.
5884 */
5885
5886 return clock.dot;
5887 }
5888
5889 /** Returns the currently programmed mode of the given pipe. */
5890 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5891 struct drm_crtc *crtc)
5892 {
5893 struct drm_i915_private *dev_priv = dev->dev_private;
5894 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5895 int pipe = intel_crtc->pipe;
5896 struct drm_display_mode *mode;
5897 int htot = I915_READ(HTOTAL(pipe));
5898 int hsync = I915_READ(HSYNC(pipe));
5899 int vtot = I915_READ(VTOTAL(pipe));
5900 int vsync = I915_READ(VSYNC(pipe));
5901
5902 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5903 if (!mode)
5904 return NULL;
5905
5906 mode->clock = intel_crtc_clock_get(dev, crtc);
5907 mode->hdisplay = (htot & 0xffff) + 1;
5908 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5909 mode->hsync_start = (hsync & 0xffff) + 1;
5910 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5911 mode->vdisplay = (vtot & 0xffff) + 1;
5912 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5913 mode->vsync_start = (vsync & 0xffff) + 1;
5914 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5915
5916 drm_mode_set_name(mode);
5917 drm_mode_set_crtcinfo(mode, 0);
5918
5919 return mode;
5920 }
5921
5922 #define GPU_IDLE_TIMEOUT 500 /* ms */
5923
5924 /* When this timer fires, we've been idle for awhile */
5925 static void intel_gpu_idle_timer(unsigned long arg)
5926 {
5927 struct drm_device *dev = (struct drm_device *)arg;
5928 drm_i915_private_t *dev_priv = dev->dev_private;
5929
5930 if (!list_empty(&dev_priv->mm.active_list)) {
5931 /* Still processing requests, so just re-arm the timer. */
5932 mod_timer(&dev_priv->idle_timer, jiffies +
5933 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5934 return;
5935 }
5936
5937 dev_priv->busy = false;
5938 queue_work(dev_priv->wq, &dev_priv->idle_work);
5939 }
5940
5941 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
5942
5943 static void intel_crtc_idle_timer(unsigned long arg)
5944 {
5945 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5946 struct drm_crtc *crtc = &intel_crtc->base;
5947 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
5948 struct intel_framebuffer *intel_fb;
5949
5950 intel_fb = to_intel_framebuffer(crtc->fb);
5951 if (intel_fb && intel_fb->obj->active) {
5952 /* The framebuffer is still being accessed by the GPU. */
5953 mod_timer(&intel_crtc->idle_timer, jiffies +
5954 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5955 return;
5956 }
5957
5958 intel_crtc->busy = false;
5959 queue_work(dev_priv->wq, &dev_priv->idle_work);
5960 }
5961
5962 static void intel_increase_pllclock(struct drm_crtc *crtc)
5963 {
5964 struct drm_device *dev = crtc->dev;
5965 drm_i915_private_t *dev_priv = dev->dev_private;
5966 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5967 int pipe = intel_crtc->pipe;
5968 int dpll_reg = DPLL(pipe);
5969 int dpll;
5970
5971 if (HAS_PCH_SPLIT(dev))
5972 return;
5973
5974 if (!dev_priv->lvds_downclock_avail)
5975 return;
5976
5977 dpll = I915_READ(dpll_reg);
5978 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
5979 DRM_DEBUG_DRIVER("upclocking LVDS\n");
5980
5981 /* Unlock panel regs */
5982 I915_WRITE(PP_CONTROL,
5983 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
5984
5985 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5986 I915_WRITE(dpll_reg, dpll);
5987 intel_wait_for_vblank(dev, pipe);
5988
5989 dpll = I915_READ(dpll_reg);
5990 if (dpll & DISPLAY_RATE_SELECT_FPA1)
5991 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
5992
5993 /* ...and lock them again */
5994 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
5995 }
5996
5997 /* Schedule downclock */
5998 mod_timer(&intel_crtc->idle_timer, jiffies +
5999 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6000 }
6001
6002 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6003 {
6004 struct drm_device *dev = crtc->dev;
6005 drm_i915_private_t *dev_priv = dev->dev_private;
6006 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6007 int pipe = intel_crtc->pipe;
6008 int dpll_reg = DPLL(pipe);
6009 int dpll = I915_READ(dpll_reg);
6010
6011 if (HAS_PCH_SPLIT(dev))
6012 return;
6013
6014 if (!dev_priv->lvds_downclock_avail)
6015 return;
6016
6017 /*
6018 * Since this is called by a timer, we should never get here in
6019 * the manual case.
6020 */
6021 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6022 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6023
6024 /* Unlock panel regs */
6025 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
6026 PANEL_UNLOCK_REGS);
6027
6028 dpll |= DISPLAY_RATE_SELECT_FPA1;
6029 I915_WRITE(dpll_reg, dpll);
6030 intel_wait_for_vblank(dev, pipe);
6031 dpll = I915_READ(dpll_reg);
6032 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6033 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6034
6035 /* ...and lock them again */
6036 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6037 }
6038
6039 }
6040
6041 /**
6042 * intel_idle_update - adjust clocks for idleness
6043 * @work: work struct
6044 *
6045 * Either the GPU or display (or both) went idle. Check the busy status
6046 * here and adjust the CRTC and GPU clocks as necessary.
6047 */
6048 static void intel_idle_update(struct work_struct *work)
6049 {
6050 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
6051 idle_work);
6052 struct drm_device *dev = dev_priv->dev;
6053 struct drm_crtc *crtc;
6054 struct intel_crtc *intel_crtc;
6055
6056 if (!i915_powersave)
6057 return;
6058
6059 mutex_lock(&dev->struct_mutex);
6060
6061 i915_update_gfx_val(dev_priv);
6062
6063 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6064 /* Skip inactive CRTCs */
6065 if (!crtc->fb)
6066 continue;
6067
6068 intel_crtc = to_intel_crtc(crtc);
6069 if (!intel_crtc->busy)
6070 intel_decrease_pllclock(crtc);
6071 }
6072
6073
6074 mutex_unlock(&dev->struct_mutex);
6075 }
6076
6077 /**
6078 * intel_mark_busy - mark the GPU and possibly the display busy
6079 * @dev: drm device
6080 * @obj: object we're operating on
6081 *
6082 * Callers can use this function to indicate that the GPU is busy processing
6083 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
6084 * buffer), we'll also mark the display as busy, so we know to increase its
6085 * clock frequency.
6086 */
6087 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
6088 {
6089 drm_i915_private_t *dev_priv = dev->dev_private;
6090 struct drm_crtc *crtc = NULL;
6091 struct intel_framebuffer *intel_fb;
6092 struct intel_crtc *intel_crtc;
6093
6094 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6095 return;
6096
6097 if (!dev_priv->busy)
6098 dev_priv->busy = true;
6099 else
6100 mod_timer(&dev_priv->idle_timer, jiffies +
6101 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6102
6103 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6104 if (!crtc->fb)
6105 continue;
6106
6107 intel_crtc = to_intel_crtc(crtc);
6108 intel_fb = to_intel_framebuffer(crtc->fb);
6109 if (intel_fb->obj == obj) {
6110 if (!intel_crtc->busy) {
6111 /* Non-busy -> busy, upclock */
6112 intel_increase_pllclock(crtc);
6113 intel_crtc->busy = true;
6114 } else {
6115 /* Busy -> busy, put off timer */
6116 mod_timer(&intel_crtc->idle_timer, jiffies +
6117 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6118 }
6119 }
6120 }
6121 }
6122
6123 static void intel_crtc_destroy(struct drm_crtc *crtc)
6124 {
6125 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6126 struct drm_device *dev = crtc->dev;
6127 struct intel_unpin_work *work;
6128 unsigned long flags;
6129
6130 spin_lock_irqsave(&dev->event_lock, flags);
6131 work = intel_crtc->unpin_work;
6132 intel_crtc->unpin_work = NULL;
6133 spin_unlock_irqrestore(&dev->event_lock, flags);
6134
6135 if (work) {
6136 cancel_work_sync(&work->work);
6137 kfree(work);
6138 }
6139
6140 drm_crtc_cleanup(crtc);
6141
6142 kfree(intel_crtc);
6143 }
6144
6145 static void intel_unpin_work_fn(struct work_struct *__work)
6146 {
6147 struct intel_unpin_work *work =
6148 container_of(__work, struct intel_unpin_work, work);
6149
6150 mutex_lock(&work->dev->struct_mutex);
6151 i915_gem_object_unpin(work->old_fb_obj);
6152 drm_gem_object_unreference(&work->pending_flip_obj->base);
6153 drm_gem_object_unreference(&work->old_fb_obj->base);
6154
6155 mutex_unlock(&work->dev->struct_mutex);
6156 kfree(work);
6157 }
6158
6159 static void do_intel_finish_page_flip(struct drm_device *dev,
6160 struct drm_crtc *crtc)
6161 {
6162 drm_i915_private_t *dev_priv = dev->dev_private;
6163 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6164 struct intel_unpin_work *work;
6165 struct drm_i915_gem_object *obj;
6166 struct drm_pending_vblank_event *e;
6167 struct timeval tnow, tvbl;
6168 unsigned long flags;
6169
6170 /* Ignore early vblank irqs */
6171 if (intel_crtc == NULL)
6172 return;
6173
6174 do_gettimeofday(&tnow);
6175
6176 spin_lock_irqsave(&dev->event_lock, flags);
6177 work = intel_crtc->unpin_work;
6178 if (work == NULL || !work->pending) {
6179 spin_unlock_irqrestore(&dev->event_lock, flags);
6180 return;
6181 }
6182
6183 intel_crtc->unpin_work = NULL;
6184
6185 if (work->event) {
6186 e = work->event;
6187 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6188
6189 /* Called before vblank count and timestamps have
6190 * been updated for the vblank interval of flip
6191 * completion? Need to increment vblank count and
6192 * add one videorefresh duration to returned timestamp
6193 * to account for this. We assume this happened if we
6194 * get called over 0.9 frame durations after the last
6195 * timestamped vblank.
6196 *
6197 * This calculation can not be used with vrefresh rates
6198 * below 5Hz (10Hz to be on the safe side) without
6199 * promoting to 64 integers.
6200 */
6201 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6202 9 * crtc->framedur_ns) {
6203 e->event.sequence++;
6204 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6205 crtc->framedur_ns);
6206 }
6207
6208 e->event.tv_sec = tvbl.tv_sec;
6209 e->event.tv_usec = tvbl.tv_usec;
6210
6211 list_add_tail(&e->base.link,
6212 &e->base.file_priv->event_list);
6213 wake_up_interruptible(&e->base.file_priv->event_wait);
6214 }
6215
6216 drm_vblank_put(dev, intel_crtc->pipe);
6217
6218 spin_unlock_irqrestore(&dev->event_lock, flags);
6219
6220 obj = work->old_fb_obj;
6221
6222 atomic_clear_mask(1 << intel_crtc->plane,
6223 &obj->pending_flip.counter);
6224 if (atomic_read(&obj->pending_flip) == 0)
6225 wake_up(&dev_priv->pending_flip_queue);
6226
6227 schedule_work(&work->work);
6228
6229 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6230 }
6231
6232 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6233 {
6234 drm_i915_private_t *dev_priv = dev->dev_private;
6235 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6236
6237 do_intel_finish_page_flip(dev, crtc);
6238 }
6239
6240 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6241 {
6242 drm_i915_private_t *dev_priv = dev->dev_private;
6243 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6244
6245 do_intel_finish_page_flip(dev, crtc);
6246 }
6247
6248 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6249 {
6250 drm_i915_private_t *dev_priv = dev->dev_private;
6251 struct intel_crtc *intel_crtc =
6252 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6253 unsigned long flags;
6254
6255 spin_lock_irqsave(&dev->event_lock, flags);
6256 if (intel_crtc->unpin_work) {
6257 if ((++intel_crtc->unpin_work->pending) > 1)
6258 DRM_ERROR("Prepared flip multiple times\n");
6259 } else {
6260 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6261 }
6262 spin_unlock_irqrestore(&dev->event_lock, flags);
6263 }
6264
6265 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6266 struct drm_framebuffer *fb,
6267 struct drm_pending_vblank_event *event)
6268 {
6269 struct drm_device *dev = crtc->dev;
6270 struct drm_i915_private *dev_priv = dev->dev_private;
6271 struct intel_framebuffer *intel_fb;
6272 struct drm_i915_gem_object *obj;
6273 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6274 struct intel_unpin_work *work;
6275 unsigned long flags, offset;
6276 int pipe = intel_crtc->pipe;
6277 u32 pf, pipesrc;
6278 int ret;
6279
6280 work = kzalloc(sizeof *work, GFP_KERNEL);
6281 if (work == NULL)
6282 return -ENOMEM;
6283
6284 work->event = event;
6285 work->dev = crtc->dev;
6286 intel_fb = to_intel_framebuffer(crtc->fb);
6287 work->old_fb_obj = intel_fb->obj;
6288 INIT_WORK(&work->work, intel_unpin_work_fn);
6289
6290 /* We borrow the event spin lock for protecting unpin_work */
6291 spin_lock_irqsave(&dev->event_lock, flags);
6292 if (intel_crtc->unpin_work) {
6293 spin_unlock_irqrestore(&dev->event_lock, flags);
6294 kfree(work);
6295
6296 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6297 return -EBUSY;
6298 }
6299 intel_crtc->unpin_work = work;
6300 spin_unlock_irqrestore(&dev->event_lock, flags);
6301
6302 intel_fb = to_intel_framebuffer(fb);
6303 obj = intel_fb->obj;
6304
6305 mutex_lock(&dev->struct_mutex);
6306 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6307 if (ret)
6308 goto cleanup_work;
6309
6310 /* Reference the objects for the scheduled work. */
6311 drm_gem_object_reference(&work->old_fb_obj->base);
6312 drm_gem_object_reference(&obj->base);
6313
6314 crtc->fb = fb;
6315
6316 ret = drm_vblank_get(dev, intel_crtc->pipe);
6317 if (ret)
6318 goto cleanup_objs;
6319
6320 if (IS_GEN3(dev) || IS_GEN2(dev)) {
6321 u32 flip_mask;
6322
6323 /* Can't queue multiple flips, so wait for the previous
6324 * one to finish before executing the next.
6325 */
6326 ret = BEGIN_LP_RING(2);
6327 if (ret)
6328 goto cleanup_objs;
6329
6330 if (intel_crtc->plane)
6331 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6332 else
6333 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6334 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6335 OUT_RING(MI_NOOP);
6336 ADVANCE_LP_RING();
6337 }
6338
6339 work->pending_flip_obj = obj;
6340
6341 work->enable_stall_check = true;
6342
6343 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6344 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6345
6346 ret = BEGIN_LP_RING(4);
6347 if (ret)
6348 goto cleanup_objs;
6349
6350 /* Block clients from rendering to the new back buffer until
6351 * the flip occurs and the object is no longer visible.
6352 */
6353 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6354
6355 switch (INTEL_INFO(dev)->gen) {
6356 case 2:
6357 OUT_RING(MI_DISPLAY_FLIP |
6358 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6359 OUT_RING(fb->pitch);
6360 OUT_RING(obj->gtt_offset + offset);
6361 OUT_RING(MI_NOOP);
6362 break;
6363
6364 case 3:
6365 OUT_RING(MI_DISPLAY_FLIP_I915 |
6366 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6367 OUT_RING(fb->pitch);
6368 OUT_RING(obj->gtt_offset + offset);
6369 OUT_RING(MI_NOOP);
6370 break;
6371
6372 case 4:
6373 case 5:
6374 /* i965+ uses the linear or tiled offsets from the
6375 * Display Registers (which do not change across a page-flip)
6376 * so we need only reprogram the base address.
6377 */
6378 OUT_RING(MI_DISPLAY_FLIP |
6379 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6380 OUT_RING(fb->pitch);
6381 OUT_RING(obj->gtt_offset | obj->tiling_mode);
6382
6383 /* XXX Enabling the panel-fitter across page-flip is so far
6384 * untested on non-native modes, so ignore it for now.
6385 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6386 */
6387 pf = 0;
6388 pipesrc = I915_READ(PIPESRC(pipe)) & 0x0fff0fff;
6389 OUT_RING(pf | pipesrc);
6390 break;
6391
6392 case 6:
6393 case 7:
6394 OUT_RING(MI_DISPLAY_FLIP |
6395 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6396 OUT_RING(fb->pitch | obj->tiling_mode);
6397 OUT_RING(obj->gtt_offset);
6398
6399 pf = I915_READ(PF_CTL(pipe)) & PF_ENABLE;
6400 pipesrc = I915_READ(PIPESRC(pipe)) & 0x0fff0fff;
6401 OUT_RING(pf | pipesrc);
6402 break;
6403 }
6404 ADVANCE_LP_RING();
6405
6406 mutex_unlock(&dev->struct_mutex);
6407
6408 trace_i915_flip_request(intel_crtc->plane, obj);
6409
6410 return 0;
6411
6412 cleanup_objs:
6413 drm_gem_object_unreference(&work->old_fb_obj->base);
6414 drm_gem_object_unreference(&obj->base);
6415 cleanup_work:
6416 mutex_unlock(&dev->struct_mutex);
6417
6418 spin_lock_irqsave(&dev->event_lock, flags);
6419 intel_crtc->unpin_work = NULL;
6420 spin_unlock_irqrestore(&dev->event_lock, flags);
6421
6422 kfree(work);
6423
6424 return ret;
6425 }
6426
6427 static void intel_sanitize_modesetting(struct drm_device *dev,
6428 int pipe, int plane)
6429 {
6430 struct drm_i915_private *dev_priv = dev->dev_private;
6431 u32 reg, val;
6432
6433 if (HAS_PCH_SPLIT(dev))
6434 return;
6435
6436 /* Who knows what state these registers were left in by the BIOS or
6437 * grub?
6438 *
6439 * If we leave the registers in a conflicting state (e.g. with the
6440 * display plane reading from the other pipe than the one we intend
6441 * to use) then when we attempt to teardown the active mode, we will
6442 * not disable the pipes and planes in the correct order -- leaving
6443 * a plane reading from a disabled pipe and possibly leading to
6444 * undefined behaviour.
6445 */
6446
6447 reg = DSPCNTR(plane);
6448 val = I915_READ(reg);
6449
6450 if ((val & DISPLAY_PLANE_ENABLE) == 0)
6451 return;
6452 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6453 return;
6454
6455 /* This display plane is active and attached to the other CPU pipe. */
6456 pipe = !pipe;
6457
6458 /* Disable the plane and wait for it to stop reading from the pipe. */
6459 intel_disable_plane(dev_priv, plane, pipe);
6460 intel_disable_pipe(dev_priv, pipe);
6461 }
6462
6463 static void intel_crtc_reset(struct drm_crtc *crtc)
6464 {
6465 struct drm_device *dev = crtc->dev;
6466 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6467
6468 /* Reset flags back to the 'unknown' status so that they
6469 * will be correctly set on the initial modeset.
6470 */
6471 intel_crtc->dpms_mode = -1;
6472
6473 /* We need to fix up any BIOS configuration that conflicts with
6474 * our expectations.
6475 */
6476 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6477 }
6478
6479 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6480 .dpms = intel_crtc_dpms,
6481 .mode_fixup = intel_crtc_mode_fixup,
6482 .mode_set = intel_crtc_mode_set,
6483 .mode_set_base = intel_pipe_set_base,
6484 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6485 .load_lut = intel_crtc_load_lut,
6486 .disable = intel_crtc_disable,
6487 };
6488
6489 static const struct drm_crtc_funcs intel_crtc_funcs = {
6490 .reset = intel_crtc_reset,
6491 .cursor_set = intel_crtc_cursor_set,
6492 .cursor_move = intel_crtc_cursor_move,
6493 .gamma_set = intel_crtc_gamma_set,
6494 .set_config = drm_crtc_helper_set_config,
6495 .destroy = intel_crtc_destroy,
6496 .page_flip = intel_crtc_page_flip,
6497 };
6498
6499 static void intel_crtc_init(struct drm_device *dev, int pipe)
6500 {
6501 drm_i915_private_t *dev_priv = dev->dev_private;
6502 struct intel_crtc *intel_crtc;
6503 int i;
6504
6505 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6506 if (intel_crtc == NULL)
6507 return;
6508
6509 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6510
6511 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
6512 for (i = 0; i < 256; i++) {
6513 intel_crtc->lut_r[i] = i;
6514 intel_crtc->lut_g[i] = i;
6515 intel_crtc->lut_b[i] = i;
6516 }
6517
6518 /* Swap pipes & planes for FBC on pre-965 */
6519 intel_crtc->pipe = pipe;
6520 intel_crtc->plane = pipe;
6521 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
6522 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
6523 intel_crtc->plane = !pipe;
6524 }
6525
6526 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6527 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6528 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6529 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6530
6531 intel_crtc_reset(&intel_crtc->base);
6532 intel_crtc->active = true; /* force the pipe off on setup_init_config */
6533
6534 if (HAS_PCH_SPLIT(dev)) {
6535 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6536 intel_helper_funcs.commit = ironlake_crtc_commit;
6537 } else {
6538 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6539 intel_helper_funcs.commit = i9xx_crtc_commit;
6540 }
6541
6542 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6543
6544 intel_crtc->busy = false;
6545
6546 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6547 (unsigned long)intel_crtc);
6548 }
6549
6550 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
6551 struct drm_file *file)
6552 {
6553 drm_i915_private_t *dev_priv = dev->dev_private;
6554 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
6555 struct drm_mode_object *drmmode_obj;
6556 struct intel_crtc *crtc;
6557
6558 if (!dev_priv) {
6559 DRM_ERROR("called with no initialization\n");
6560 return -EINVAL;
6561 }
6562
6563 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6564 DRM_MODE_OBJECT_CRTC);
6565
6566 if (!drmmode_obj) {
6567 DRM_ERROR("no such CRTC id\n");
6568 return -EINVAL;
6569 }
6570
6571 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6572 pipe_from_crtc_id->pipe = crtc->pipe;
6573
6574 return 0;
6575 }
6576
6577 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
6578 {
6579 struct intel_encoder *encoder;
6580 int index_mask = 0;
6581 int entry = 0;
6582
6583 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6584 if (type_mask & encoder->clone_mask)
6585 index_mask |= (1 << entry);
6586 entry++;
6587 }
6588
6589 return index_mask;
6590 }
6591
6592 static bool has_edp_a(struct drm_device *dev)
6593 {
6594 struct drm_i915_private *dev_priv = dev->dev_private;
6595
6596 if (!IS_MOBILE(dev))
6597 return false;
6598
6599 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6600 return false;
6601
6602 if (IS_GEN5(dev) &&
6603 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6604 return false;
6605
6606 return true;
6607 }
6608
6609 static void intel_setup_outputs(struct drm_device *dev)
6610 {
6611 struct drm_i915_private *dev_priv = dev->dev_private;
6612 struct intel_encoder *encoder;
6613 bool dpd_is_edp = false;
6614 bool has_lvds = false;
6615
6616 if (IS_MOBILE(dev) && !IS_I830(dev))
6617 has_lvds = intel_lvds_init(dev);
6618 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6619 /* disable the panel fitter on everything but LVDS */
6620 I915_WRITE(PFIT_CONTROL, 0);
6621 }
6622
6623 if (HAS_PCH_SPLIT(dev)) {
6624 dpd_is_edp = intel_dpd_is_edp(dev);
6625
6626 if (has_edp_a(dev))
6627 intel_dp_init(dev, DP_A);
6628
6629 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6630 intel_dp_init(dev, PCH_DP_D);
6631 }
6632
6633 intel_crt_init(dev);
6634
6635 if (HAS_PCH_SPLIT(dev)) {
6636 int found;
6637
6638 if (I915_READ(HDMIB) & PORT_DETECTED) {
6639 /* PCH SDVOB multiplex with HDMIB */
6640 found = intel_sdvo_init(dev, PCH_SDVOB);
6641 if (!found)
6642 intel_hdmi_init(dev, HDMIB);
6643 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6644 intel_dp_init(dev, PCH_DP_B);
6645 }
6646
6647 if (I915_READ(HDMIC) & PORT_DETECTED)
6648 intel_hdmi_init(dev, HDMIC);
6649
6650 if (I915_READ(HDMID) & PORT_DETECTED)
6651 intel_hdmi_init(dev, HDMID);
6652
6653 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6654 intel_dp_init(dev, PCH_DP_C);
6655
6656 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6657 intel_dp_init(dev, PCH_DP_D);
6658
6659 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
6660 bool found = false;
6661
6662 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6663 DRM_DEBUG_KMS("probing SDVOB\n");
6664 found = intel_sdvo_init(dev, SDVOB);
6665 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6666 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
6667 intel_hdmi_init(dev, SDVOB);
6668 }
6669
6670 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6671 DRM_DEBUG_KMS("probing DP_B\n");
6672 intel_dp_init(dev, DP_B);
6673 }
6674 }
6675
6676 /* Before G4X SDVOC doesn't have its own detect register */
6677
6678 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6679 DRM_DEBUG_KMS("probing SDVOC\n");
6680 found = intel_sdvo_init(dev, SDVOC);
6681 }
6682
6683 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6684
6685 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6686 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
6687 intel_hdmi_init(dev, SDVOC);
6688 }
6689 if (SUPPORTS_INTEGRATED_DP(dev)) {
6690 DRM_DEBUG_KMS("probing DP_C\n");
6691 intel_dp_init(dev, DP_C);
6692 }
6693 }
6694
6695 if (SUPPORTS_INTEGRATED_DP(dev) &&
6696 (I915_READ(DP_D) & DP_DETECTED)) {
6697 DRM_DEBUG_KMS("probing DP_D\n");
6698 intel_dp_init(dev, DP_D);
6699 }
6700 } else if (IS_GEN2(dev))
6701 intel_dvo_init(dev);
6702
6703 if (SUPPORTS_TV(dev))
6704 intel_tv_init(dev);
6705
6706 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6707 encoder->base.possible_crtcs = encoder->crtc_mask;
6708 encoder->base.possible_clones =
6709 intel_encoder_clones(dev, encoder->clone_mask);
6710 }
6711
6712 intel_panel_setup_backlight(dev);
6713
6714 /* disable all the possible outputs/crtcs before entering KMS mode */
6715 drm_helper_disable_unused_functions(dev);
6716 }
6717
6718 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6719 {
6720 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6721
6722 drm_framebuffer_cleanup(fb);
6723 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
6724
6725 kfree(intel_fb);
6726 }
6727
6728 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
6729 struct drm_file *file,
6730 unsigned int *handle)
6731 {
6732 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6733 struct drm_i915_gem_object *obj = intel_fb->obj;
6734
6735 return drm_gem_handle_create(file, &obj->base, handle);
6736 }
6737
6738 static const struct drm_framebuffer_funcs intel_fb_funcs = {
6739 .destroy = intel_user_framebuffer_destroy,
6740 .create_handle = intel_user_framebuffer_create_handle,
6741 };
6742
6743 int intel_framebuffer_init(struct drm_device *dev,
6744 struct intel_framebuffer *intel_fb,
6745 struct drm_mode_fb_cmd *mode_cmd,
6746 struct drm_i915_gem_object *obj)
6747 {
6748 int ret;
6749
6750 if (obj->tiling_mode == I915_TILING_Y)
6751 return -EINVAL;
6752
6753 if (mode_cmd->pitch & 63)
6754 return -EINVAL;
6755
6756 switch (mode_cmd->bpp) {
6757 case 8:
6758 case 16:
6759 case 24:
6760 case 32:
6761 break;
6762 default:
6763 return -EINVAL;
6764 }
6765
6766 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6767 if (ret) {
6768 DRM_ERROR("framebuffer init failed %d\n", ret);
6769 return ret;
6770 }
6771
6772 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
6773 intel_fb->obj = obj;
6774 return 0;
6775 }
6776
6777 static struct drm_framebuffer *
6778 intel_user_framebuffer_create(struct drm_device *dev,
6779 struct drm_file *filp,
6780 struct drm_mode_fb_cmd *mode_cmd)
6781 {
6782 struct drm_i915_gem_object *obj;
6783
6784 obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
6785 if (&obj->base == NULL)
6786 return ERR_PTR(-ENOENT);
6787
6788 return intel_framebuffer_create(dev, mode_cmd, obj);
6789 }
6790
6791 static const struct drm_mode_config_funcs intel_mode_funcs = {
6792 .fb_create = intel_user_framebuffer_create,
6793 .output_poll_changed = intel_fb_output_poll_changed,
6794 };
6795
6796 static struct drm_i915_gem_object *
6797 intel_alloc_context_page(struct drm_device *dev)
6798 {
6799 struct drm_i915_gem_object *ctx;
6800 int ret;
6801
6802 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
6803
6804 ctx = i915_gem_alloc_object(dev, 4096);
6805 if (!ctx) {
6806 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
6807 return NULL;
6808 }
6809
6810 ret = i915_gem_object_pin(ctx, 4096, true);
6811 if (ret) {
6812 DRM_ERROR("failed to pin power context: %d\n", ret);
6813 goto err_unref;
6814 }
6815
6816 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
6817 if (ret) {
6818 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
6819 goto err_unpin;
6820 }
6821
6822 return ctx;
6823
6824 err_unpin:
6825 i915_gem_object_unpin(ctx);
6826 err_unref:
6827 drm_gem_object_unreference(&ctx->base);
6828 mutex_unlock(&dev->struct_mutex);
6829 return NULL;
6830 }
6831
6832 bool ironlake_set_drps(struct drm_device *dev, u8 val)
6833 {
6834 struct drm_i915_private *dev_priv = dev->dev_private;
6835 u16 rgvswctl;
6836
6837 rgvswctl = I915_READ16(MEMSWCTL);
6838 if (rgvswctl & MEMCTL_CMD_STS) {
6839 DRM_DEBUG("gpu busy, RCS change rejected\n");
6840 return false; /* still busy with another command */
6841 }
6842
6843 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
6844 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
6845 I915_WRITE16(MEMSWCTL, rgvswctl);
6846 POSTING_READ16(MEMSWCTL);
6847
6848 rgvswctl |= MEMCTL_CMD_STS;
6849 I915_WRITE16(MEMSWCTL, rgvswctl);
6850
6851 return true;
6852 }
6853
6854 void ironlake_enable_drps(struct drm_device *dev)
6855 {
6856 struct drm_i915_private *dev_priv = dev->dev_private;
6857 u32 rgvmodectl = I915_READ(MEMMODECTL);
6858 u8 fmax, fmin, fstart, vstart;
6859
6860 /* Enable temp reporting */
6861 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
6862 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
6863
6864 /* 100ms RC evaluation intervals */
6865 I915_WRITE(RCUPEI, 100000);
6866 I915_WRITE(RCDNEI, 100000);
6867
6868 /* Set max/min thresholds to 90ms and 80ms respectively */
6869 I915_WRITE(RCBMAXAVG, 90000);
6870 I915_WRITE(RCBMINAVG, 80000);
6871
6872 I915_WRITE(MEMIHYST, 1);
6873
6874 /* Set up min, max, and cur for interrupt handling */
6875 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
6876 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
6877 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
6878 MEMMODE_FSTART_SHIFT;
6879
6880 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
6881 PXVFREQ_PX_SHIFT;
6882
6883 dev_priv->fmax = fmax; /* IPS callback will increase this */
6884 dev_priv->fstart = fstart;
6885
6886 dev_priv->max_delay = fstart;
6887 dev_priv->min_delay = fmin;
6888 dev_priv->cur_delay = fstart;
6889
6890 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
6891 fmax, fmin, fstart);
6892
6893 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
6894
6895 /*
6896 * Interrupts will be enabled in ironlake_irq_postinstall
6897 */
6898
6899 I915_WRITE(VIDSTART, vstart);
6900 POSTING_READ(VIDSTART);
6901
6902 rgvmodectl |= MEMMODE_SWMODE_EN;
6903 I915_WRITE(MEMMODECTL, rgvmodectl);
6904
6905 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
6906 DRM_ERROR("stuck trying to change perf mode\n");
6907 msleep(1);
6908
6909 ironlake_set_drps(dev, fstart);
6910
6911 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
6912 I915_READ(0x112e0);
6913 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
6914 dev_priv->last_count2 = I915_READ(0x112f4);
6915 getrawmonotonic(&dev_priv->last_time2);
6916 }
6917
6918 void ironlake_disable_drps(struct drm_device *dev)
6919 {
6920 struct drm_i915_private *dev_priv = dev->dev_private;
6921 u16 rgvswctl = I915_READ16(MEMSWCTL);
6922
6923 /* Ack interrupts, disable EFC interrupt */
6924 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
6925 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
6926 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
6927 I915_WRITE(DEIIR, DE_PCU_EVENT);
6928 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
6929
6930 /* Go back to the starting frequency */
6931 ironlake_set_drps(dev, dev_priv->fstart);
6932 msleep(1);
6933 rgvswctl |= MEMCTL_CMD_STS;
6934 I915_WRITE(MEMSWCTL, rgvswctl);
6935 msleep(1);
6936
6937 }
6938
6939 void gen6_set_rps(struct drm_device *dev, u8 val)
6940 {
6941 struct drm_i915_private *dev_priv = dev->dev_private;
6942 u32 swreq;
6943
6944 swreq = (val & 0x3ff) << 25;
6945 I915_WRITE(GEN6_RPNSWREQ, swreq);
6946 }
6947
6948 void gen6_disable_rps(struct drm_device *dev)
6949 {
6950 struct drm_i915_private *dev_priv = dev->dev_private;
6951
6952 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
6953 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
6954 I915_WRITE(GEN6_PMIER, 0);
6955
6956 spin_lock_irq(&dev_priv->rps_lock);
6957 dev_priv->pm_iir = 0;
6958 spin_unlock_irq(&dev_priv->rps_lock);
6959
6960 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
6961 }
6962
6963 static unsigned long intel_pxfreq(u32 vidfreq)
6964 {
6965 unsigned long freq;
6966 int div = (vidfreq & 0x3f0000) >> 16;
6967 int post = (vidfreq & 0x3000) >> 12;
6968 int pre = (vidfreq & 0x7);
6969
6970 if (!pre)
6971 return 0;
6972
6973 freq = ((div * 133333) / ((1<<post) * pre));
6974
6975 return freq;
6976 }
6977
6978 void intel_init_emon(struct drm_device *dev)
6979 {
6980 struct drm_i915_private *dev_priv = dev->dev_private;
6981 u32 lcfuse;
6982 u8 pxw[16];
6983 int i;
6984
6985 /* Disable to program */
6986 I915_WRITE(ECR, 0);
6987 POSTING_READ(ECR);
6988
6989 /* Program energy weights for various events */
6990 I915_WRITE(SDEW, 0x15040d00);
6991 I915_WRITE(CSIEW0, 0x007f0000);
6992 I915_WRITE(CSIEW1, 0x1e220004);
6993 I915_WRITE(CSIEW2, 0x04000004);
6994
6995 for (i = 0; i < 5; i++)
6996 I915_WRITE(PEW + (i * 4), 0);
6997 for (i = 0; i < 3; i++)
6998 I915_WRITE(DEW + (i * 4), 0);
6999
7000 /* Program P-state weights to account for frequency power adjustment */
7001 for (i = 0; i < 16; i++) {
7002 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
7003 unsigned long freq = intel_pxfreq(pxvidfreq);
7004 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
7005 PXVFREQ_PX_SHIFT;
7006 unsigned long val;
7007
7008 val = vid * vid;
7009 val *= (freq / 1000);
7010 val *= 255;
7011 val /= (127*127*900);
7012 if (val > 0xff)
7013 DRM_ERROR("bad pxval: %ld\n", val);
7014 pxw[i] = val;
7015 }
7016 /* Render standby states get 0 weight */
7017 pxw[14] = 0;
7018 pxw[15] = 0;
7019
7020 for (i = 0; i < 4; i++) {
7021 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
7022 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
7023 I915_WRITE(PXW + (i * 4), val);
7024 }
7025
7026 /* Adjust magic regs to magic values (more experimental results) */
7027 I915_WRITE(OGW0, 0);
7028 I915_WRITE(OGW1, 0);
7029 I915_WRITE(EG0, 0x00007f00);
7030 I915_WRITE(EG1, 0x0000000e);
7031 I915_WRITE(EG2, 0x000e0000);
7032 I915_WRITE(EG3, 0x68000300);
7033 I915_WRITE(EG4, 0x42000000);
7034 I915_WRITE(EG5, 0x00140031);
7035 I915_WRITE(EG6, 0);
7036 I915_WRITE(EG7, 0);
7037
7038 for (i = 0; i < 8; i++)
7039 I915_WRITE(PXWL + (i * 4), 0);
7040
7041 /* Enable PMON + select events */
7042 I915_WRITE(ECR, 0x80000019);
7043
7044 lcfuse = I915_READ(LCFUSE02);
7045
7046 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
7047 }
7048
7049 void gen6_enable_rps(struct drm_i915_private *dev_priv)
7050 {
7051 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
7052 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
7053 u32 pcu_mbox, rc6_mask = 0;
7054 int cur_freq, min_freq, max_freq;
7055 int i;
7056
7057 /* Here begins a magic sequence of register writes to enable
7058 * auto-downclocking.
7059 *
7060 * Perhaps there might be some value in exposing these to
7061 * userspace...
7062 */
7063 I915_WRITE(GEN6_RC_STATE, 0);
7064 mutex_lock(&dev_priv->dev->struct_mutex);
7065 gen6_gt_force_wake_get(dev_priv);
7066
7067 /* disable the counters and set deterministic thresholds */
7068 I915_WRITE(GEN6_RC_CONTROL, 0);
7069
7070 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
7071 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
7072 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
7073 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
7074 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
7075
7076 for (i = 0; i < I915_NUM_RINGS; i++)
7077 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
7078
7079 I915_WRITE(GEN6_RC_SLEEP, 0);
7080 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
7081 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
7082 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
7083 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
7084
7085 if (i915_enable_rc6)
7086 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
7087 GEN6_RC_CTL_RC6_ENABLE;
7088
7089 I915_WRITE(GEN6_RC_CONTROL,
7090 rc6_mask |
7091 GEN6_RC_CTL_EI_MODE(1) |
7092 GEN6_RC_CTL_HW_ENABLE);
7093
7094 I915_WRITE(GEN6_RPNSWREQ,
7095 GEN6_FREQUENCY(10) |
7096 GEN6_OFFSET(0) |
7097 GEN6_AGGRESSIVE_TURBO);
7098 I915_WRITE(GEN6_RC_VIDEO_FREQ,
7099 GEN6_FREQUENCY(12));
7100
7101 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7102 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
7103 18 << 24 |
7104 6 << 16);
7105 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
7106 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
7107 I915_WRITE(GEN6_RP_UP_EI, 100000);
7108 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
7109 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7110 I915_WRITE(GEN6_RP_CONTROL,
7111 GEN6_RP_MEDIA_TURBO |
7112 GEN6_RP_USE_NORMAL_FREQ |
7113 GEN6_RP_MEDIA_IS_GFX |
7114 GEN6_RP_ENABLE |
7115 GEN6_RP_UP_BUSY_AVG |
7116 GEN6_RP_DOWN_IDLE_CONT);
7117
7118 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7119 500))
7120 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7121
7122 I915_WRITE(GEN6_PCODE_DATA, 0);
7123 I915_WRITE(GEN6_PCODE_MAILBOX,
7124 GEN6_PCODE_READY |
7125 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7126 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7127 500))
7128 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7129
7130 min_freq = (rp_state_cap & 0xff0000) >> 16;
7131 max_freq = rp_state_cap & 0xff;
7132 cur_freq = (gt_perf_status & 0xff00) >> 8;
7133
7134 /* Check for overclock support */
7135 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7136 500))
7137 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7138 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
7139 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
7140 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7141 500))
7142 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7143 if (pcu_mbox & (1<<31)) { /* OC supported */
7144 max_freq = pcu_mbox & 0xff;
7145 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
7146 }
7147
7148 /* In units of 100MHz */
7149 dev_priv->max_delay = max_freq;
7150 dev_priv->min_delay = min_freq;
7151 dev_priv->cur_delay = cur_freq;
7152
7153 /* requires MSI enabled */
7154 I915_WRITE(GEN6_PMIER,
7155 GEN6_PM_MBOX_EVENT |
7156 GEN6_PM_THERMAL_EVENT |
7157 GEN6_PM_RP_DOWN_TIMEOUT |
7158 GEN6_PM_RP_UP_THRESHOLD |
7159 GEN6_PM_RP_DOWN_THRESHOLD |
7160 GEN6_PM_RP_UP_EI_EXPIRED |
7161 GEN6_PM_RP_DOWN_EI_EXPIRED);
7162 spin_lock_irq(&dev_priv->rps_lock);
7163 WARN_ON(dev_priv->pm_iir != 0);
7164 I915_WRITE(GEN6_PMIMR, 0);
7165 spin_unlock_irq(&dev_priv->rps_lock);
7166 /* enable all PM interrupts */
7167 I915_WRITE(GEN6_PMINTRMSK, 0);
7168
7169 gen6_gt_force_wake_put(dev_priv);
7170 mutex_unlock(&dev_priv->dev->struct_mutex);
7171 }
7172
7173 static void ironlake_init_clock_gating(struct drm_device *dev)
7174 {
7175 struct drm_i915_private *dev_priv = dev->dev_private;
7176 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7177
7178 /* Required for FBC */
7179 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
7180 DPFCRUNIT_CLOCK_GATE_DISABLE |
7181 DPFDUNIT_CLOCK_GATE_DISABLE;
7182 /* Required for CxSR */
7183 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
7184
7185 I915_WRITE(PCH_3DCGDIS0,
7186 MARIUNIT_CLOCK_GATE_DISABLE |
7187 SVSMUNIT_CLOCK_GATE_DISABLE);
7188 I915_WRITE(PCH_3DCGDIS1,
7189 VFMUNIT_CLOCK_GATE_DISABLE);
7190
7191 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7192
7193 /*
7194 * According to the spec the following bits should be set in
7195 * order to enable memory self-refresh
7196 * The bit 22/21 of 0x42004
7197 * The bit 5 of 0x42020
7198 * The bit 15 of 0x45000
7199 */
7200 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7201 (I915_READ(ILK_DISPLAY_CHICKEN2) |
7202 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
7203 I915_WRITE(ILK_DSPCLK_GATE,
7204 (I915_READ(ILK_DSPCLK_GATE) |
7205 ILK_DPARB_CLK_GATE));
7206 I915_WRITE(DISP_ARB_CTL,
7207 (I915_READ(DISP_ARB_CTL) |
7208 DISP_FBC_WM_DIS));
7209 I915_WRITE(WM3_LP_ILK, 0);
7210 I915_WRITE(WM2_LP_ILK, 0);
7211 I915_WRITE(WM1_LP_ILK, 0);
7212
7213 /*
7214 * Based on the document from hardware guys the following bits
7215 * should be set unconditionally in order to enable FBC.
7216 * The bit 22 of 0x42000
7217 * The bit 22 of 0x42004
7218 * The bit 7,8,9 of 0x42020.
7219 */
7220 if (IS_IRONLAKE_M(dev)) {
7221 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7222 I915_READ(ILK_DISPLAY_CHICKEN1) |
7223 ILK_FBCQ_DIS);
7224 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7225 I915_READ(ILK_DISPLAY_CHICKEN2) |
7226 ILK_DPARB_GATE);
7227 I915_WRITE(ILK_DSPCLK_GATE,
7228 I915_READ(ILK_DSPCLK_GATE) |
7229 ILK_DPFC_DIS1 |
7230 ILK_DPFC_DIS2 |
7231 ILK_CLK_FBC);
7232 }
7233
7234 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7235 I915_READ(ILK_DISPLAY_CHICKEN2) |
7236 ILK_ELPIN_409_SELECT);
7237 I915_WRITE(_3D_CHICKEN2,
7238 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
7239 _3D_CHICKEN2_WM_READ_PIPELINED);
7240 }
7241
7242 static void gen6_init_clock_gating(struct drm_device *dev)
7243 {
7244 struct drm_i915_private *dev_priv = dev->dev_private;
7245 int pipe;
7246 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7247
7248 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7249
7250 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7251 I915_READ(ILK_DISPLAY_CHICKEN2) |
7252 ILK_ELPIN_409_SELECT);
7253
7254 I915_WRITE(WM3_LP_ILK, 0);
7255 I915_WRITE(WM2_LP_ILK, 0);
7256 I915_WRITE(WM1_LP_ILK, 0);
7257
7258 /*
7259 * According to the spec the following bits should be
7260 * set in order to enable memory self-refresh and fbc:
7261 * The bit21 and bit22 of 0x42000
7262 * The bit21 and bit22 of 0x42004
7263 * The bit5 and bit7 of 0x42020
7264 * The bit14 of 0x70180
7265 * The bit14 of 0x71180
7266 */
7267 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7268 I915_READ(ILK_DISPLAY_CHICKEN1) |
7269 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7270 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7271 I915_READ(ILK_DISPLAY_CHICKEN2) |
7272 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7273 I915_WRITE(ILK_DSPCLK_GATE,
7274 I915_READ(ILK_DSPCLK_GATE) |
7275 ILK_DPARB_CLK_GATE |
7276 ILK_DPFD_CLK_GATE);
7277
7278 for_each_pipe(pipe)
7279 I915_WRITE(DSPCNTR(pipe),
7280 I915_READ(DSPCNTR(pipe)) |
7281 DISPPLANE_TRICKLE_FEED_DISABLE);
7282 }
7283
7284 static void ivybridge_init_clock_gating(struct drm_device *dev)
7285 {
7286 struct drm_i915_private *dev_priv = dev->dev_private;
7287 int pipe;
7288 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7289
7290 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7291
7292 I915_WRITE(WM3_LP_ILK, 0);
7293 I915_WRITE(WM2_LP_ILK, 0);
7294 I915_WRITE(WM1_LP_ILK, 0);
7295
7296 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
7297
7298 for_each_pipe(pipe)
7299 I915_WRITE(DSPCNTR(pipe),
7300 I915_READ(DSPCNTR(pipe)) |
7301 DISPPLANE_TRICKLE_FEED_DISABLE);
7302 }
7303
7304 static void g4x_init_clock_gating(struct drm_device *dev)
7305 {
7306 struct drm_i915_private *dev_priv = dev->dev_private;
7307 uint32_t dspclk_gate;
7308
7309 I915_WRITE(RENCLK_GATE_D1, 0);
7310 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7311 GS_UNIT_CLOCK_GATE_DISABLE |
7312 CL_UNIT_CLOCK_GATE_DISABLE);
7313 I915_WRITE(RAMCLK_GATE_D, 0);
7314 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7315 OVRUNIT_CLOCK_GATE_DISABLE |
7316 OVCUNIT_CLOCK_GATE_DISABLE;
7317 if (IS_GM45(dev))
7318 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7319 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7320 }
7321
7322 static void crestline_init_clock_gating(struct drm_device *dev)
7323 {
7324 struct drm_i915_private *dev_priv = dev->dev_private;
7325
7326 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7327 I915_WRITE(RENCLK_GATE_D2, 0);
7328 I915_WRITE(DSPCLK_GATE_D, 0);
7329 I915_WRITE(RAMCLK_GATE_D, 0);
7330 I915_WRITE16(DEUC, 0);
7331 }
7332
7333 static void broadwater_init_clock_gating(struct drm_device *dev)
7334 {
7335 struct drm_i915_private *dev_priv = dev->dev_private;
7336
7337 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7338 I965_RCC_CLOCK_GATE_DISABLE |
7339 I965_RCPB_CLOCK_GATE_DISABLE |
7340 I965_ISC_CLOCK_GATE_DISABLE |
7341 I965_FBC_CLOCK_GATE_DISABLE);
7342 I915_WRITE(RENCLK_GATE_D2, 0);
7343 }
7344
7345 static void gen3_init_clock_gating(struct drm_device *dev)
7346 {
7347 struct drm_i915_private *dev_priv = dev->dev_private;
7348 u32 dstate = I915_READ(D_STATE);
7349
7350 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7351 DSTATE_DOT_CLOCK_GATING;
7352 I915_WRITE(D_STATE, dstate);
7353 }
7354
7355 static void i85x_init_clock_gating(struct drm_device *dev)
7356 {
7357 struct drm_i915_private *dev_priv = dev->dev_private;
7358
7359 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7360 }
7361
7362 static void i830_init_clock_gating(struct drm_device *dev)
7363 {
7364 struct drm_i915_private *dev_priv = dev->dev_private;
7365
7366 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7367 }
7368
7369 static void ibx_init_clock_gating(struct drm_device *dev)
7370 {
7371 struct drm_i915_private *dev_priv = dev->dev_private;
7372
7373 /*
7374 * On Ibex Peak and Cougar Point, we need to disable clock
7375 * gating for the panel power sequencer or it will fail to
7376 * start up when no ports are active.
7377 */
7378 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7379 }
7380
7381 static void cpt_init_clock_gating(struct drm_device *dev)
7382 {
7383 struct drm_i915_private *dev_priv = dev->dev_private;
7384
7385 /*
7386 * On Ibex Peak and Cougar Point, we need to disable clock
7387 * gating for the panel power sequencer or it will fail to
7388 * start up when no ports are active.
7389 */
7390 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7391 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
7392 DPLS_EDP_PPS_FIX_DIS);
7393 }
7394
7395 static void ironlake_teardown_rc6(struct drm_device *dev)
7396 {
7397 struct drm_i915_private *dev_priv = dev->dev_private;
7398
7399 if (dev_priv->renderctx) {
7400 i915_gem_object_unpin(dev_priv->renderctx);
7401 drm_gem_object_unreference(&dev_priv->renderctx->base);
7402 dev_priv->renderctx = NULL;
7403 }
7404
7405 if (dev_priv->pwrctx) {
7406 i915_gem_object_unpin(dev_priv->pwrctx);
7407 drm_gem_object_unreference(&dev_priv->pwrctx->base);
7408 dev_priv->pwrctx = NULL;
7409 }
7410 }
7411
7412 static void ironlake_disable_rc6(struct drm_device *dev)
7413 {
7414 struct drm_i915_private *dev_priv = dev->dev_private;
7415
7416 if (I915_READ(PWRCTXA)) {
7417 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
7418 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
7419 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
7420 50);
7421
7422 I915_WRITE(PWRCTXA, 0);
7423 POSTING_READ(PWRCTXA);
7424
7425 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7426 POSTING_READ(RSTDBYCTL);
7427 }
7428
7429 ironlake_teardown_rc6(dev);
7430 }
7431
7432 static int ironlake_setup_rc6(struct drm_device *dev)
7433 {
7434 struct drm_i915_private *dev_priv = dev->dev_private;
7435
7436 if (dev_priv->renderctx == NULL)
7437 dev_priv->renderctx = intel_alloc_context_page(dev);
7438 if (!dev_priv->renderctx)
7439 return -ENOMEM;
7440
7441 if (dev_priv->pwrctx == NULL)
7442 dev_priv->pwrctx = intel_alloc_context_page(dev);
7443 if (!dev_priv->pwrctx) {
7444 ironlake_teardown_rc6(dev);
7445 return -ENOMEM;
7446 }
7447
7448 return 0;
7449 }
7450
7451 void ironlake_enable_rc6(struct drm_device *dev)
7452 {
7453 struct drm_i915_private *dev_priv = dev->dev_private;
7454 int ret;
7455
7456 /* rc6 disabled by default due to repeated reports of hanging during
7457 * boot and resume.
7458 */
7459 if (!i915_enable_rc6)
7460 return;
7461
7462 mutex_lock(&dev->struct_mutex);
7463 ret = ironlake_setup_rc6(dev);
7464 if (ret) {
7465 mutex_unlock(&dev->struct_mutex);
7466 return;
7467 }
7468
7469 /*
7470 * GPU can automatically power down the render unit if given a page
7471 * to save state.
7472 */
7473 ret = BEGIN_LP_RING(6);
7474 if (ret) {
7475 ironlake_teardown_rc6(dev);
7476 mutex_unlock(&dev->struct_mutex);
7477 return;
7478 }
7479
7480 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
7481 OUT_RING(MI_SET_CONTEXT);
7482 OUT_RING(dev_priv->renderctx->gtt_offset |
7483 MI_MM_SPACE_GTT |
7484 MI_SAVE_EXT_STATE_EN |
7485 MI_RESTORE_EXT_STATE_EN |
7486 MI_RESTORE_INHIBIT);
7487 OUT_RING(MI_SUSPEND_FLUSH);
7488 OUT_RING(MI_NOOP);
7489 OUT_RING(MI_FLUSH);
7490 ADVANCE_LP_RING();
7491
7492 /*
7493 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
7494 * does an implicit flush, combined with MI_FLUSH above, it should be
7495 * safe to assume that renderctx is valid
7496 */
7497 ret = intel_wait_ring_idle(LP_RING(dev_priv));
7498 if (ret) {
7499 DRM_ERROR("failed to enable ironlake power power savings\n");
7500 ironlake_teardown_rc6(dev);
7501 mutex_unlock(&dev->struct_mutex);
7502 return;
7503 }
7504
7505 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
7506 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7507 mutex_unlock(&dev->struct_mutex);
7508 }
7509
7510 void intel_init_clock_gating(struct drm_device *dev)
7511 {
7512 struct drm_i915_private *dev_priv = dev->dev_private;
7513
7514 dev_priv->display.init_clock_gating(dev);
7515
7516 if (dev_priv->display.init_pch_clock_gating)
7517 dev_priv->display.init_pch_clock_gating(dev);
7518 }
7519
7520 /* Set up chip specific display functions */
7521 static void intel_init_display(struct drm_device *dev)
7522 {
7523 struct drm_i915_private *dev_priv = dev->dev_private;
7524
7525 /* We always want a DPMS function */
7526 if (HAS_PCH_SPLIT(dev)) {
7527 dev_priv->display.dpms = ironlake_crtc_dpms;
7528 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
7529 } else {
7530 dev_priv->display.dpms = i9xx_crtc_dpms;
7531 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
7532 }
7533
7534 if (I915_HAS_FBC(dev)) {
7535 if (HAS_PCH_SPLIT(dev)) {
7536 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7537 dev_priv->display.enable_fbc = ironlake_enable_fbc;
7538 dev_priv->display.disable_fbc = ironlake_disable_fbc;
7539 } else if (IS_GM45(dev)) {
7540 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
7541 dev_priv->display.enable_fbc = g4x_enable_fbc;
7542 dev_priv->display.disable_fbc = g4x_disable_fbc;
7543 } else if (IS_CRESTLINE(dev)) {
7544 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
7545 dev_priv->display.enable_fbc = i8xx_enable_fbc;
7546 dev_priv->display.disable_fbc = i8xx_disable_fbc;
7547 }
7548 /* 855GM needs testing */
7549 }
7550
7551 /* Returns the core display clock speed */
7552 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
7553 dev_priv->display.get_display_clock_speed =
7554 i945_get_display_clock_speed;
7555 else if (IS_I915G(dev))
7556 dev_priv->display.get_display_clock_speed =
7557 i915_get_display_clock_speed;
7558 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
7559 dev_priv->display.get_display_clock_speed =
7560 i9xx_misc_get_display_clock_speed;
7561 else if (IS_I915GM(dev))
7562 dev_priv->display.get_display_clock_speed =
7563 i915gm_get_display_clock_speed;
7564 else if (IS_I865G(dev))
7565 dev_priv->display.get_display_clock_speed =
7566 i865_get_display_clock_speed;
7567 else if (IS_I85X(dev))
7568 dev_priv->display.get_display_clock_speed =
7569 i855_get_display_clock_speed;
7570 else /* 852, 830 */
7571 dev_priv->display.get_display_clock_speed =
7572 i830_get_display_clock_speed;
7573
7574 /* For FIFO watermark updates */
7575 if (HAS_PCH_SPLIT(dev)) {
7576 if (HAS_PCH_IBX(dev))
7577 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
7578 else if (HAS_PCH_CPT(dev))
7579 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
7580
7581 if (IS_GEN5(dev)) {
7582 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
7583 dev_priv->display.update_wm = ironlake_update_wm;
7584 else {
7585 DRM_DEBUG_KMS("Failed to get proper latency. "
7586 "Disable CxSR\n");
7587 dev_priv->display.update_wm = NULL;
7588 }
7589 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
7590 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7591 } else if (IS_GEN6(dev)) {
7592 if (SNB_READ_WM0_LATENCY()) {
7593 dev_priv->display.update_wm = sandybridge_update_wm;
7594 } else {
7595 DRM_DEBUG_KMS("Failed to read display plane latency. "
7596 "Disable CxSR\n");
7597 dev_priv->display.update_wm = NULL;
7598 }
7599 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
7600 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7601 } else if (IS_IVYBRIDGE(dev)) {
7602 /* FIXME: detect B0+ stepping and use auto training */
7603 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
7604 if (SNB_READ_WM0_LATENCY()) {
7605 dev_priv->display.update_wm = sandybridge_update_wm;
7606 } else {
7607 DRM_DEBUG_KMS("Failed to read display plane latency. "
7608 "Disable CxSR\n");
7609 dev_priv->display.update_wm = NULL;
7610 }
7611 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7612
7613 } else
7614 dev_priv->display.update_wm = NULL;
7615 } else if (IS_PINEVIEW(dev)) {
7616 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7617 dev_priv->is_ddr3,
7618 dev_priv->fsb_freq,
7619 dev_priv->mem_freq)) {
7620 DRM_INFO("failed to find known CxSR latency "
7621 "(found ddr%s fsb freq %d, mem freq %d), "
7622 "disabling CxSR\n",
7623 (dev_priv->is_ddr3 == 1) ? "3": "2",
7624 dev_priv->fsb_freq, dev_priv->mem_freq);
7625 /* Disable CxSR and never update its watermark again */
7626 pineview_disable_cxsr(dev);
7627 dev_priv->display.update_wm = NULL;
7628 } else
7629 dev_priv->display.update_wm = pineview_update_wm;
7630 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7631 } else if (IS_G4X(dev)) {
7632 dev_priv->display.update_wm = g4x_update_wm;
7633 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7634 } else if (IS_GEN4(dev)) {
7635 dev_priv->display.update_wm = i965_update_wm;
7636 if (IS_CRESTLINE(dev))
7637 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7638 else if (IS_BROADWATER(dev))
7639 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7640 } else if (IS_GEN3(dev)) {
7641 dev_priv->display.update_wm = i9xx_update_wm;
7642 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7643 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7644 } else if (IS_I865G(dev)) {
7645 dev_priv->display.update_wm = i830_update_wm;
7646 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7647 dev_priv->display.get_fifo_size = i830_get_fifo_size;
7648 } else if (IS_I85X(dev)) {
7649 dev_priv->display.update_wm = i9xx_update_wm;
7650 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
7651 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7652 } else {
7653 dev_priv->display.update_wm = i830_update_wm;
7654 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7655 if (IS_845G(dev))
7656 dev_priv->display.get_fifo_size = i845_get_fifo_size;
7657 else
7658 dev_priv->display.get_fifo_size = i830_get_fifo_size;
7659 }
7660 }
7661
7662 /*
7663 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7664 * resume, or other times. This quirk makes sure that's the case for
7665 * affected systems.
7666 */
7667 static void quirk_pipea_force (struct drm_device *dev)
7668 {
7669 struct drm_i915_private *dev_priv = dev->dev_private;
7670
7671 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
7672 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
7673 }
7674
7675 struct intel_quirk {
7676 int device;
7677 int subsystem_vendor;
7678 int subsystem_device;
7679 void (*hook)(struct drm_device *dev);
7680 };
7681
7682 struct intel_quirk intel_quirks[] = {
7683 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
7684 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
7685 /* HP Mini needs pipe A force quirk (LP: #322104) */
7686 { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
7687
7688 /* Thinkpad R31 needs pipe A force quirk */
7689 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
7690 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7691 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7692
7693 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
7694 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
7695 /* ThinkPad X40 needs pipe A force quirk */
7696
7697 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7698 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7699
7700 /* 855 & before need to leave pipe A & dpll A up */
7701 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7702 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7703 };
7704
7705 static void intel_init_quirks(struct drm_device *dev)
7706 {
7707 struct pci_dev *d = dev->pdev;
7708 int i;
7709
7710 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7711 struct intel_quirk *q = &intel_quirks[i];
7712
7713 if (d->device == q->device &&
7714 (d->subsystem_vendor == q->subsystem_vendor ||
7715 q->subsystem_vendor == PCI_ANY_ID) &&
7716 (d->subsystem_device == q->subsystem_device ||
7717 q->subsystem_device == PCI_ANY_ID))
7718 q->hook(dev);
7719 }
7720 }
7721
7722 /* Disable the VGA plane that we never use */
7723 static void i915_disable_vga(struct drm_device *dev)
7724 {
7725 struct drm_i915_private *dev_priv = dev->dev_private;
7726 u8 sr1;
7727 u32 vga_reg;
7728
7729 if (HAS_PCH_SPLIT(dev))
7730 vga_reg = CPU_VGACNTRL;
7731 else
7732 vga_reg = VGACNTRL;
7733
7734 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
7735 outb(1, VGA_SR_INDEX);
7736 sr1 = inb(VGA_SR_DATA);
7737 outb(sr1 | 1<<5, VGA_SR_DATA);
7738 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7739 udelay(300);
7740
7741 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7742 POSTING_READ(vga_reg);
7743 }
7744
7745 void intel_modeset_init(struct drm_device *dev)
7746 {
7747 struct drm_i915_private *dev_priv = dev->dev_private;
7748 int i;
7749
7750 drm_mode_config_init(dev);
7751
7752 dev->mode_config.min_width = 0;
7753 dev->mode_config.min_height = 0;
7754
7755 dev->mode_config.funcs = (void *)&intel_mode_funcs;
7756
7757 intel_init_quirks(dev);
7758
7759 intel_init_display(dev);
7760
7761 if (IS_GEN2(dev)) {
7762 dev->mode_config.max_width = 2048;
7763 dev->mode_config.max_height = 2048;
7764 } else if (IS_GEN3(dev)) {
7765 dev->mode_config.max_width = 4096;
7766 dev->mode_config.max_height = 4096;
7767 } else {
7768 dev->mode_config.max_width = 8192;
7769 dev->mode_config.max_height = 8192;
7770 }
7771 dev->mode_config.fb_base = dev->agp->base;
7772
7773 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7774 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
7775
7776 for (i = 0; i < dev_priv->num_pipe; i++) {
7777 intel_crtc_init(dev, i);
7778 }
7779
7780 /* Just disable it once at startup */
7781 i915_disable_vga(dev);
7782 intel_setup_outputs(dev);
7783
7784 intel_init_clock_gating(dev);
7785
7786 if (IS_IRONLAKE_M(dev)) {
7787 ironlake_enable_drps(dev);
7788 intel_init_emon(dev);
7789 }
7790
7791 if (IS_GEN6(dev))
7792 gen6_enable_rps(dev_priv);
7793
7794 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
7795 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
7796 (unsigned long)dev);
7797 }
7798
7799 void intel_modeset_gem_init(struct drm_device *dev)
7800 {
7801 if (IS_IRONLAKE_M(dev))
7802 ironlake_enable_rc6(dev);
7803
7804 intel_setup_overlay(dev);
7805 }
7806
7807 void intel_modeset_cleanup(struct drm_device *dev)
7808 {
7809 struct drm_i915_private *dev_priv = dev->dev_private;
7810 struct drm_crtc *crtc;
7811 struct intel_crtc *intel_crtc;
7812
7813 drm_kms_helper_poll_fini(dev);
7814 mutex_lock(&dev->struct_mutex);
7815
7816 intel_unregister_dsm_handler();
7817
7818
7819 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7820 /* Skip inactive CRTCs */
7821 if (!crtc->fb)
7822 continue;
7823
7824 intel_crtc = to_intel_crtc(crtc);
7825 intel_increase_pllclock(crtc);
7826 }
7827
7828 if (dev_priv->display.disable_fbc)
7829 dev_priv->display.disable_fbc(dev);
7830
7831 if (IS_IRONLAKE_M(dev))
7832 ironlake_disable_drps(dev);
7833 if (IS_GEN6(dev))
7834 gen6_disable_rps(dev);
7835
7836 if (IS_IRONLAKE_M(dev))
7837 ironlake_disable_rc6(dev);
7838
7839 mutex_unlock(&dev->struct_mutex);
7840
7841 /* Disable the irq before mode object teardown, for the irq might
7842 * enqueue unpin/hotplug work. */
7843 drm_irq_uninstall(dev);
7844 cancel_work_sync(&dev_priv->hotplug_work);
7845
7846 /* Shut off idle work before the crtcs get freed. */
7847 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7848 intel_crtc = to_intel_crtc(crtc);
7849 del_timer_sync(&intel_crtc->idle_timer);
7850 }
7851 del_timer_sync(&dev_priv->idle_timer);
7852 cancel_work_sync(&dev_priv->idle_work);
7853
7854 drm_mode_config_cleanup(dev);
7855 }
7856
7857 /*
7858 * Return which encoder is currently attached for connector.
7859 */
7860 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
7861 {
7862 return &intel_attached_encoder(connector)->base;
7863 }
7864
7865 void intel_connector_attach_encoder(struct intel_connector *connector,
7866 struct intel_encoder *encoder)
7867 {
7868 connector->encoder = encoder;
7869 drm_mode_connector_attach_encoder(&connector->base,
7870 &encoder->base);
7871 }
7872
7873 /*
7874 * set vga decode state - true == enable VGA decode
7875 */
7876 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
7877 {
7878 struct drm_i915_private *dev_priv = dev->dev_private;
7879 u16 gmch_ctrl;
7880
7881 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
7882 if (state)
7883 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
7884 else
7885 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
7886 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
7887 return 0;
7888 }
7889
7890 #ifdef CONFIG_DEBUG_FS
7891 #include <linux/seq_file.h>
7892
7893 struct intel_display_error_state {
7894 struct intel_cursor_error_state {
7895 u32 control;
7896 u32 position;
7897 u32 base;
7898 u32 size;
7899 } cursor[2];
7900
7901 struct intel_pipe_error_state {
7902 u32 conf;
7903 u32 source;
7904
7905 u32 htotal;
7906 u32 hblank;
7907 u32 hsync;
7908 u32 vtotal;
7909 u32 vblank;
7910 u32 vsync;
7911 } pipe[2];
7912
7913 struct intel_plane_error_state {
7914 u32 control;
7915 u32 stride;
7916 u32 size;
7917 u32 pos;
7918 u32 addr;
7919 u32 surface;
7920 u32 tile_offset;
7921 } plane[2];
7922 };
7923
7924 struct intel_display_error_state *
7925 intel_display_capture_error_state(struct drm_device *dev)
7926 {
7927 drm_i915_private_t *dev_priv = dev->dev_private;
7928 struct intel_display_error_state *error;
7929 int i;
7930
7931 error = kmalloc(sizeof(*error), GFP_ATOMIC);
7932 if (error == NULL)
7933 return NULL;
7934
7935 for (i = 0; i < 2; i++) {
7936 error->cursor[i].control = I915_READ(CURCNTR(i));
7937 error->cursor[i].position = I915_READ(CURPOS(i));
7938 error->cursor[i].base = I915_READ(CURBASE(i));
7939
7940 error->plane[i].control = I915_READ(DSPCNTR(i));
7941 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
7942 error->plane[i].size = I915_READ(DSPSIZE(i));
7943 error->plane[i].pos= I915_READ(DSPPOS(i));
7944 error->plane[i].addr = I915_READ(DSPADDR(i));
7945 if (INTEL_INFO(dev)->gen >= 4) {
7946 error->plane[i].surface = I915_READ(DSPSURF(i));
7947 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
7948 }
7949
7950 error->pipe[i].conf = I915_READ(PIPECONF(i));
7951 error->pipe[i].source = I915_READ(PIPESRC(i));
7952 error->pipe[i].htotal = I915_READ(HTOTAL(i));
7953 error->pipe[i].hblank = I915_READ(HBLANK(i));
7954 error->pipe[i].hsync = I915_READ(HSYNC(i));
7955 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
7956 error->pipe[i].vblank = I915_READ(VBLANK(i));
7957 error->pipe[i].vsync = I915_READ(VSYNC(i));
7958 }
7959
7960 return error;
7961 }
7962
7963 void
7964 intel_display_print_error_state(struct seq_file *m,
7965 struct drm_device *dev,
7966 struct intel_display_error_state *error)
7967 {
7968 int i;
7969
7970 for (i = 0; i < 2; i++) {
7971 seq_printf(m, "Pipe [%d]:\n", i);
7972 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
7973 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
7974 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
7975 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
7976 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
7977 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
7978 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
7979 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
7980
7981 seq_printf(m, "Plane [%d]:\n", i);
7982 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
7983 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
7984 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
7985 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
7986 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
7987 if (INTEL_INFO(dev)->gen >= 4) {
7988 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
7989 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
7990 }
7991
7992 seq_printf(m, "Cursor [%d]:\n", i);
7993 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
7994 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
7995 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
7996 }
7997 }
7998 #endif
Linux kernel - Deliverables
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