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Merge tag 'v3.1-rc10' into drm-core-next
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/cpufreq.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include "drmP.h"
36 #include "intel_drv.h"
37 #include "i915_drm.h"
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include "drm_dp_helper.h"
41
42 #include "drm_crtc_helper.h"
43
44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
47 static void intel_update_watermarks(struct drm_device *dev);
48 static void intel_increase_pllclock(struct drm_crtc *crtc);
49 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
50
51 typedef struct {
52 /* given values */
53 int n;
54 int m1, m2;
55 int p1, p2;
56 /* derived values */
57 int dot;
58 int vco;
59 int m;
60 int p;
61 } intel_clock_t;
62
63 typedef struct {
64 int min, max;
65 } intel_range_t;
66
67 typedef struct {
68 int dot_limit;
69 int p2_slow, p2_fast;
70 } intel_p2_t;
71
72 #define INTEL_P2_NUM 2
73 typedef struct intel_limit intel_limit_t;
74 struct intel_limit {
75 intel_range_t dot, vco, n, m, m1, m2, p, p1;
76 intel_p2_t p2;
77 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
78 int, int, intel_clock_t *);
79 };
80
81 /* FDI */
82 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
83
84 static bool
85 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
86 int target, int refclk, intel_clock_t *best_clock);
87 static bool
88 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
89 int target, int refclk, intel_clock_t *best_clock);
90
91 static bool
92 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
93 int target, int refclk, intel_clock_t *best_clock);
94 static bool
95 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
96 int target, int refclk, intel_clock_t *best_clock);
97
98 static inline u32 /* units of 100MHz */
99 intel_fdi_link_freq(struct drm_device *dev)
100 {
101 if (IS_GEN5(dev)) {
102 struct drm_i915_private *dev_priv = dev->dev_private;
103 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
104 } else
105 return 27;
106 }
107
108 static const intel_limit_t intel_limits_i8xx_dvo = {
109 .dot = { .min = 25000, .max = 350000 },
110 .vco = { .min = 930000, .max = 1400000 },
111 .n = { .min = 3, .max = 16 },
112 .m = { .min = 96, .max = 140 },
113 .m1 = { .min = 18, .max = 26 },
114 .m2 = { .min = 6, .max = 16 },
115 .p = { .min = 4, .max = 128 },
116 .p1 = { .min = 2, .max = 33 },
117 .p2 = { .dot_limit = 165000,
118 .p2_slow = 4, .p2_fast = 2 },
119 .find_pll = intel_find_best_PLL,
120 };
121
122 static const intel_limit_t intel_limits_i8xx_lvds = {
123 .dot = { .min = 25000, .max = 350000 },
124 .vco = { .min = 930000, .max = 1400000 },
125 .n = { .min = 3, .max = 16 },
126 .m = { .min = 96, .max = 140 },
127 .m1 = { .min = 18, .max = 26 },
128 .m2 = { .min = 6, .max = 16 },
129 .p = { .min = 4, .max = 128 },
130 .p1 = { .min = 1, .max = 6 },
131 .p2 = { .dot_limit = 165000,
132 .p2_slow = 14, .p2_fast = 7 },
133 .find_pll = intel_find_best_PLL,
134 };
135
136 static const intel_limit_t intel_limits_i9xx_sdvo = {
137 .dot = { .min = 20000, .max = 400000 },
138 .vco = { .min = 1400000, .max = 2800000 },
139 .n = { .min = 1, .max = 6 },
140 .m = { .min = 70, .max = 120 },
141 .m1 = { .min = 10, .max = 22 },
142 .m2 = { .min = 5, .max = 9 },
143 .p = { .min = 5, .max = 80 },
144 .p1 = { .min = 1, .max = 8 },
145 .p2 = { .dot_limit = 200000,
146 .p2_slow = 10, .p2_fast = 5 },
147 .find_pll = intel_find_best_PLL,
148 };
149
150 static const intel_limit_t intel_limits_i9xx_lvds = {
151 .dot = { .min = 20000, .max = 400000 },
152 .vco = { .min = 1400000, .max = 2800000 },
153 .n = { .min = 1, .max = 6 },
154 .m = { .min = 70, .max = 120 },
155 .m1 = { .min = 10, .max = 22 },
156 .m2 = { .min = 5, .max = 9 },
157 .p = { .min = 7, .max = 98 },
158 .p1 = { .min = 1, .max = 8 },
159 .p2 = { .dot_limit = 112000,
160 .p2_slow = 14, .p2_fast = 7 },
161 .find_pll = intel_find_best_PLL,
162 };
163
164
165 static const intel_limit_t intel_limits_g4x_sdvo = {
166 .dot = { .min = 25000, .max = 270000 },
167 .vco = { .min = 1750000, .max = 3500000},
168 .n = { .min = 1, .max = 4 },
169 .m = { .min = 104, .max = 138 },
170 .m1 = { .min = 17, .max = 23 },
171 .m2 = { .min = 5, .max = 11 },
172 .p = { .min = 10, .max = 30 },
173 .p1 = { .min = 1, .max = 3},
174 .p2 = { .dot_limit = 270000,
175 .p2_slow = 10,
176 .p2_fast = 10
177 },
178 .find_pll = intel_g4x_find_best_PLL,
179 };
180
181 static const intel_limit_t intel_limits_g4x_hdmi = {
182 .dot = { .min = 22000, .max = 400000 },
183 .vco = { .min = 1750000, .max = 3500000},
184 .n = { .min = 1, .max = 4 },
185 .m = { .min = 104, .max = 138 },
186 .m1 = { .min = 16, .max = 23 },
187 .m2 = { .min = 5, .max = 11 },
188 .p = { .min = 5, .max = 80 },
189 .p1 = { .min = 1, .max = 8},
190 .p2 = { .dot_limit = 165000,
191 .p2_slow = 10, .p2_fast = 5 },
192 .find_pll = intel_g4x_find_best_PLL,
193 };
194
195 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
196 .dot = { .min = 20000, .max = 115000 },
197 .vco = { .min = 1750000, .max = 3500000 },
198 .n = { .min = 1, .max = 3 },
199 .m = { .min = 104, .max = 138 },
200 .m1 = { .min = 17, .max = 23 },
201 .m2 = { .min = 5, .max = 11 },
202 .p = { .min = 28, .max = 112 },
203 .p1 = { .min = 2, .max = 8 },
204 .p2 = { .dot_limit = 0,
205 .p2_slow = 14, .p2_fast = 14
206 },
207 .find_pll = intel_g4x_find_best_PLL,
208 };
209
210 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
211 .dot = { .min = 80000, .max = 224000 },
212 .vco = { .min = 1750000, .max = 3500000 },
213 .n = { .min = 1, .max = 3 },
214 .m = { .min = 104, .max = 138 },
215 .m1 = { .min = 17, .max = 23 },
216 .m2 = { .min = 5, .max = 11 },
217 .p = { .min = 14, .max = 42 },
218 .p1 = { .min = 2, .max = 6 },
219 .p2 = { .dot_limit = 0,
220 .p2_slow = 7, .p2_fast = 7
221 },
222 .find_pll = intel_g4x_find_best_PLL,
223 };
224
225 static const intel_limit_t intel_limits_g4x_display_port = {
226 .dot = { .min = 161670, .max = 227000 },
227 .vco = { .min = 1750000, .max = 3500000},
228 .n = { .min = 1, .max = 2 },
229 .m = { .min = 97, .max = 108 },
230 .m1 = { .min = 0x10, .max = 0x12 },
231 .m2 = { .min = 0x05, .max = 0x06 },
232 .p = { .min = 10, .max = 20 },
233 .p1 = { .min = 1, .max = 2},
234 .p2 = { .dot_limit = 0,
235 .p2_slow = 10, .p2_fast = 10 },
236 .find_pll = intel_find_pll_g4x_dp,
237 };
238
239 static const intel_limit_t intel_limits_pineview_sdvo = {
240 .dot = { .min = 20000, .max = 400000},
241 .vco = { .min = 1700000, .max = 3500000 },
242 /* Pineview's Ncounter is a ring counter */
243 .n = { .min = 3, .max = 6 },
244 .m = { .min = 2, .max = 256 },
245 /* Pineview only has one combined m divider, which we treat as m2. */
246 .m1 = { .min = 0, .max = 0 },
247 .m2 = { .min = 0, .max = 254 },
248 .p = { .min = 5, .max = 80 },
249 .p1 = { .min = 1, .max = 8 },
250 .p2 = { .dot_limit = 200000,
251 .p2_slow = 10, .p2_fast = 5 },
252 .find_pll = intel_find_best_PLL,
253 };
254
255 static const intel_limit_t intel_limits_pineview_lvds = {
256 .dot = { .min = 20000, .max = 400000 },
257 .vco = { .min = 1700000, .max = 3500000 },
258 .n = { .min = 3, .max = 6 },
259 .m = { .min = 2, .max = 256 },
260 .m1 = { .min = 0, .max = 0 },
261 .m2 = { .min = 0, .max = 254 },
262 .p = { .min = 7, .max = 112 },
263 .p1 = { .min = 1, .max = 8 },
264 .p2 = { .dot_limit = 112000,
265 .p2_slow = 14, .p2_fast = 14 },
266 .find_pll = intel_find_best_PLL,
267 };
268
269 /* Ironlake / Sandybridge
270 *
271 * We calculate clock using (register_value + 2) for N/M1/M2, so here
272 * the range value for them is (actual_value - 2).
273 */
274 static const intel_limit_t intel_limits_ironlake_dac = {
275 .dot = { .min = 25000, .max = 350000 },
276 .vco = { .min = 1760000, .max = 3510000 },
277 .n = { .min = 1, .max = 5 },
278 .m = { .min = 79, .max = 127 },
279 .m1 = { .min = 12, .max = 22 },
280 .m2 = { .min = 5, .max = 9 },
281 .p = { .min = 5, .max = 80 },
282 .p1 = { .min = 1, .max = 8 },
283 .p2 = { .dot_limit = 225000,
284 .p2_slow = 10, .p2_fast = 5 },
285 .find_pll = intel_g4x_find_best_PLL,
286 };
287
288 static const intel_limit_t intel_limits_ironlake_single_lvds = {
289 .dot = { .min = 25000, .max = 350000 },
290 .vco = { .min = 1760000, .max = 3510000 },
291 .n = { .min = 1, .max = 3 },
292 .m = { .min = 79, .max = 118 },
293 .m1 = { .min = 12, .max = 22 },
294 .m2 = { .min = 5, .max = 9 },
295 .p = { .min = 28, .max = 112 },
296 .p1 = { .min = 2, .max = 8 },
297 .p2 = { .dot_limit = 225000,
298 .p2_slow = 14, .p2_fast = 14 },
299 .find_pll = intel_g4x_find_best_PLL,
300 };
301
302 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
303 .dot = { .min = 25000, .max = 350000 },
304 .vco = { .min = 1760000, .max = 3510000 },
305 .n = { .min = 1, .max = 3 },
306 .m = { .min = 79, .max = 127 },
307 .m1 = { .min = 12, .max = 22 },
308 .m2 = { .min = 5, .max = 9 },
309 .p = { .min = 14, .max = 56 },
310 .p1 = { .min = 2, .max = 8 },
311 .p2 = { .dot_limit = 225000,
312 .p2_slow = 7, .p2_fast = 7 },
313 .find_pll = intel_g4x_find_best_PLL,
314 };
315
316 /* LVDS 100mhz refclk limits. */
317 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
318 .dot = { .min = 25000, .max = 350000 },
319 .vco = { .min = 1760000, .max = 3510000 },
320 .n = { .min = 1, .max = 2 },
321 .m = { .min = 79, .max = 126 },
322 .m1 = { .min = 12, .max = 22 },
323 .m2 = { .min = 5, .max = 9 },
324 .p = { .min = 28, .max = 112 },
325 .p1 = { .min = 2, .max = 8 },
326 .p2 = { .dot_limit = 225000,
327 .p2_slow = 14, .p2_fast = 14 },
328 .find_pll = intel_g4x_find_best_PLL,
329 };
330
331 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
332 .dot = { .min = 25000, .max = 350000 },
333 .vco = { .min = 1760000, .max = 3510000 },
334 .n = { .min = 1, .max = 3 },
335 .m = { .min = 79, .max = 126 },
336 .m1 = { .min = 12, .max = 22 },
337 .m2 = { .min = 5, .max = 9 },
338 .p = { .min = 14, .max = 42 },
339 .p1 = { .min = 2, .max = 6 },
340 .p2 = { .dot_limit = 225000,
341 .p2_slow = 7, .p2_fast = 7 },
342 .find_pll = intel_g4x_find_best_PLL,
343 };
344
345 static const intel_limit_t intel_limits_ironlake_display_port = {
346 .dot = { .min = 25000, .max = 350000 },
347 .vco = { .min = 1760000, .max = 3510000},
348 .n = { .min = 1, .max = 2 },
349 .m = { .min = 81, .max = 90 },
350 .m1 = { .min = 12, .max = 22 },
351 .m2 = { .min = 5, .max = 9 },
352 .p = { .min = 10, .max = 20 },
353 .p1 = { .min = 1, .max = 2},
354 .p2 = { .dot_limit = 0,
355 .p2_slow = 10, .p2_fast = 10 },
356 .find_pll = intel_find_pll_ironlake_dp,
357 };
358
359 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
360 int refclk)
361 {
362 struct drm_device *dev = crtc->dev;
363 struct drm_i915_private *dev_priv = dev->dev_private;
364 const intel_limit_t *limit;
365
366 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
367 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
368 LVDS_CLKB_POWER_UP) {
369 /* LVDS dual channel */
370 if (refclk == 100000)
371 limit = &intel_limits_ironlake_dual_lvds_100m;
372 else
373 limit = &intel_limits_ironlake_dual_lvds;
374 } else {
375 if (refclk == 100000)
376 limit = &intel_limits_ironlake_single_lvds_100m;
377 else
378 limit = &intel_limits_ironlake_single_lvds;
379 }
380 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
381 HAS_eDP)
382 limit = &intel_limits_ironlake_display_port;
383 else
384 limit = &intel_limits_ironlake_dac;
385
386 return limit;
387 }
388
389 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
390 {
391 struct drm_device *dev = crtc->dev;
392 struct drm_i915_private *dev_priv = dev->dev_private;
393 const intel_limit_t *limit;
394
395 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
396 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
397 LVDS_CLKB_POWER_UP)
398 /* LVDS with dual channel */
399 limit = &intel_limits_g4x_dual_channel_lvds;
400 else
401 /* LVDS with dual channel */
402 limit = &intel_limits_g4x_single_channel_lvds;
403 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
404 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
405 limit = &intel_limits_g4x_hdmi;
406 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
407 limit = &intel_limits_g4x_sdvo;
408 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
409 limit = &intel_limits_g4x_display_port;
410 } else /* The option is for other outputs */
411 limit = &intel_limits_i9xx_sdvo;
412
413 return limit;
414 }
415
416 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
417 {
418 struct drm_device *dev = crtc->dev;
419 const intel_limit_t *limit;
420
421 if (HAS_PCH_SPLIT(dev))
422 limit = intel_ironlake_limit(crtc, refclk);
423 else if (IS_G4X(dev)) {
424 limit = intel_g4x_limit(crtc);
425 } else if (IS_PINEVIEW(dev)) {
426 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
427 limit = &intel_limits_pineview_lvds;
428 else
429 limit = &intel_limits_pineview_sdvo;
430 } else if (!IS_GEN2(dev)) {
431 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
432 limit = &intel_limits_i9xx_lvds;
433 else
434 limit = &intel_limits_i9xx_sdvo;
435 } else {
436 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
437 limit = &intel_limits_i8xx_lvds;
438 else
439 limit = &intel_limits_i8xx_dvo;
440 }
441 return limit;
442 }
443
444 /* m1 is reserved as 0 in Pineview, n is a ring counter */
445 static void pineview_clock(int refclk, intel_clock_t *clock)
446 {
447 clock->m = clock->m2 + 2;
448 clock->p = clock->p1 * clock->p2;
449 clock->vco = refclk * clock->m / clock->n;
450 clock->dot = clock->vco / clock->p;
451 }
452
453 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
454 {
455 if (IS_PINEVIEW(dev)) {
456 pineview_clock(refclk, clock);
457 return;
458 }
459 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
460 clock->p = clock->p1 * clock->p2;
461 clock->vco = refclk * clock->m / (clock->n + 2);
462 clock->dot = clock->vco / clock->p;
463 }
464
465 /**
466 * Returns whether any output on the specified pipe is of the specified type
467 */
468 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
469 {
470 struct drm_device *dev = crtc->dev;
471 struct drm_mode_config *mode_config = &dev->mode_config;
472 struct intel_encoder *encoder;
473
474 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
475 if (encoder->base.crtc == crtc && encoder->type == type)
476 return true;
477
478 return false;
479 }
480
481 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
482 /**
483 * Returns whether the given set of divisors are valid for a given refclk with
484 * the given connectors.
485 */
486
487 static bool intel_PLL_is_valid(struct drm_device *dev,
488 const intel_limit_t *limit,
489 const intel_clock_t *clock)
490 {
491 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
492 INTELPllInvalid("p1 out of range\n");
493 if (clock->p < limit->p.min || limit->p.max < clock->p)
494 INTELPllInvalid("p out of range\n");
495 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
496 INTELPllInvalid("m2 out of range\n");
497 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
498 INTELPllInvalid("m1 out of range\n");
499 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
500 INTELPllInvalid("m1 <= m2\n");
501 if (clock->m < limit->m.min || limit->m.max < clock->m)
502 INTELPllInvalid("m out of range\n");
503 if (clock->n < limit->n.min || limit->n.max < clock->n)
504 INTELPllInvalid("n out of range\n");
505 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
506 INTELPllInvalid("vco out of range\n");
507 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
508 * connector, etc., rather than just a single range.
509 */
510 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
511 INTELPllInvalid("dot out of range\n");
512
513 return true;
514 }
515
516 static bool
517 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
518 int target, int refclk, intel_clock_t *best_clock)
519
520 {
521 struct drm_device *dev = crtc->dev;
522 struct drm_i915_private *dev_priv = dev->dev_private;
523 intel_clock_t clock;
524 int err = target;
525
526 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
527 (I915_READ(LVDS)) != 0) {
528 /*
529 * For LVDS, if the panel is on, just rely on its current
530 * settings for dual-channel. We haven't figured out how to
531 * reliably set up different single/dual channel state, if we
532 * even can.
533 */
534 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
535 LVDS_CLKB_POWER_UP)
536 clock.p2 = limit->p2.p2_fast;
537 else
538 clock.p2 = limit->p2.p2_slow;
539 } else {
540 if (target < limit->p2.dot_limit)
541 clock.p2 = limit->p2.p2_slow;
542 else
543 clock.p2 = limit->p2.p2_fast;
544 }
545
546 memset(best_clock, 0, sizeof(*best_clock));
547
548 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
549 clock.m1++) {
550 for (clock.m2 = limit->m2.min;
551 clock.m2 <= limit->m2.max; clock.m2++) {
552 /* m1 is always 0 in Pineview */
553 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
554 break;
555 for (clock.n = limit->n.min;
556 clock.n <= limit->n.max; clock.n++) {
557 for (clock.p1 = limit->p1.min;
558 clock.p1 <= limit->p1.max; clock.p1++) {
559 int this_err;
560
561 intel_clock(dev, refclk, &clock);
562 if (!intel_PLL_is_valid(dev, limit,
563 &clock))
564 continue;
565
566 this_err = abs(clock.dot - target);
567 if (this_err < err) {
568 *best_clock = clock;
569 err = this_err;
570 }
571 }
572 }
573 }
574 }
575
576 return (err != target);
577 }
578
579 static bool
580 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
581 int target, int refclk, intel_clock_t *best_clock)
582 {
583 struct drm_device *dev = crtc->dev;
584 struct drm_i915_private *dev_priv = dev->dev_private;
585 intel_clock_t clock;
586 int max_n;
587 bool found;
588 /* approximately equals target * 0.00585 */
589 int err_most = (target >> 8) + (target >> 9);
590 found = false;
591
592 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
593 int lvds_reg;
594
595 if (HAS_PCH_SPLIT(dev))
596 lvds_reg = PCH_LVDS;
597 else
598 lvds_reg = LVDS;
599 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
600 LVDS_CLKB_POWER_UP)
601 clock.p2 = limit->p2.p2_fast;
602 else
603 clock.p2 = limit->p2.p2_slow;
604 } else {
605 if (target < limit->p2.dot_limit)
606 clock.p2 = limit->p2.p2_slow;
607 else
608 clock.p2 = limit->p2.p2_fast;
609 }
610
611 memset(best_clock, 0, sizeof(*best_clock));
612 max_n = limit->n.max;
613 /* based on hardware requirement, prefer smaller n to precision */
614 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
615 /* based on hardware requirement, prefere larger m1,m2 */
616 for (clock.m1 = limit->m1.max;
617 clock.m1 >= limit->m1.min; clock.m1--) {
618 for (clock.m2 = limit->m2.max;
619 clock.m2 >= limit->m2.min; clock.m2--) {
620 for (clock.p1 = limit->p1.max;
621 clock.p1 >= limit->p1.min; clock.p1--) {
622 int this_err;
623
624 intel_clock(dev, refclk, &clock);
625 if (!intel_PLL_is_valid(dev, limit,
626 &clock))
627 continue;
628
629 this_err = abs(clock.dot - target);
630 if (this_err < err_most) {
631 *best_clock = clock;
632 err_most = this_err;
633 max_n = clock.n;
634 found = true;
635 }
636 }
637 }
638 }
639 }
640 return found;
641 }
642
643 static bool
644 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
645 int target, int refclk, intel_clock_t *best_clock)
646 {
647 struct drm_device *dev = crtc->dev;
648 intel_clock_t clock;
649
650 if (target < 200000) {
651 clock.n = 1;
652 clock.p1 = 2;
653 clock.p2 = 10;
654 clock.m1 = 12;
655 clock.m2 = 9;
656 } else {
657 clock.n = 2;
658 clock.p1 = 1;
659 clock.p2 = 10;
660 clock.m1 = 14;
661 clock.m2 = 8;
662 }
663 intel_clock(dev, refclk, &clock);
664 memcpy(best_clock, &clock, sizeof(intel_clock_t));
665 return true;
666 }
667
668 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
669 static bool
670 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
671 int target, int refclk, intel_clock_t *best_clock)
672 {
673 intel_clock_t clock;
674 if (target < 200000) {
675 clock.p1 = 2;
676 clock.p2 = 10;
677 clock.n = 2;
678 clock.m1 = 23;
679 clock.m2 = 8;
680 } else {
681 clock.p1 = 1;
682 clock.p2 = 10;
683 clock.n = 1;
684 clock.m1 = 14;
685 clock.m2 = 2;
686 }
687 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
688 clock.p = (clock.p1 * clock.p2);
689 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
690 clock.vco = 0;
691 memcpy(best_clock, &clock, sizeof(intel_clock_t));
692 return true;
693 }
694
695 /**
696 * intel_wait_for_vblank - wait for vblank on a given pipe
697 * @dev: drm device
698 * @pipe: pipe to wait for
699 *
700 * Wait for vblank to occur on a given pipe. Needed for various bits of
701 * mode setting code.
702 */
703 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
704 {
705 struct drm_i915_private *dev_priv = dev->dev_private;
706 int pipestat_reg = PIPESTAT(pipe);
707
708 /* Clear existing vblank status. Note this will clear any other
709 * sticky status fields as well.
710 *
711 * This races with i915_driver_irq_handler() with the result
712 * that either function could miss a vblank event. Here it is not
713 * fatal, as we will either wait upon the next vblank interrupt or
714 * timeout. Generally speaking intel_wait_for_vblank() is only
715 * called during modeset at which time the GPU should be idle and
716 * should *not* be performing page flips and thus not waiting on
717 * vblanks...
718 * Currently, the result of us stealing a vblank from the irq
719 * handler is that a single frame will be skipped during swapbuffers.
720 */
721 I915_WRITE(pipestat_reg,
722 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
723
724 /* Wait for vblank interrupt bit to set */
725 if (wait_for(I915_READ(pipestat_reg) &
726 PIPE_VBLANK_INTERRUPT_STATUS,
727 50))
728 DRM_DEBUG_KMS("vblank wait timed out\n");
729 }
730
731 /*
732 * intel_wait_for_pipe_off - wait for pipe to turn off
733 * @dev: drm device
734 * @pipe: pipe to wait for
735 *
736 * After disabling a pipe, we can't wait for vblank in the usual way,
737 * spinning on the vblank interrupt status bit, since we won't actually
738 * see an interrupt when the pipe is disabled.
739 *
740 * On Gen4 and above:
741 * wait for the pipe register state bit to turn off
742 *
743 * Otherwise:
744 * wait for the display line value to settle (it usually
745 * ends up stopping at the start of the next frame).
746 *
747 */
748 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
749 {
750 struct drm_i915_private *dev_priv = dev->dev_private;
751
752 if (INTEL_INFO(dev)->gen >= 4) {
753 int reg = PIPECONF(pipe);
754
755 /* Wait for the Pipe State to go off */
756 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
757 100))
758 DRM_DEBUG_KMS("pipe_off wait timed out\n");
759 } else {
760 u32 last_line;
761 int reg = PIPEDSL(pipe);
762 unsigned long timeout = jiffies + msecs_to_jiffies(100);
763
764 /* Wait for the display line to settle */
765 do {
766 last_line = I915_READ(reg) & DSL_LINEMASK;
767 mdelay(5);
768 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
769 time_after(timeout, jiffies));
770 if (time_after(jiffies, timeout))
771 DRM_DEBUG_KMS("pipe_off wait timed out\n");
772 }
773 }
774
775 static const char *state_string(bool enabled)
776 {
777 return enabled ? "on" : "off";
778 }
779
780 /* Only for pre-ILK configs */
781 static void assert_pll(struct drm_i915_private *dev_priv,
782 enum pipe pipe, bool state)
783 {
784 int reg;
785 u32 val;
786 bool cur_state;
787
788 reg = DPLL(pipe);
789 val = I915_READ(reg);
790 cur_state = !!(val & DPLL_VCO_ENABLE);
791 WARN(cur_state != state,
792 "PLL state assertion failure (expected %s, current %s)\n",
793 state_string(state), state_string(cur_state));
794 }
795 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
796 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
797
798 /* For ILK+ */
799 static void assert_pch_pll(struct drm_i915_private *dev_priv,
800 enum pipe pipe, bool state)
801 {
802 int reg;
803 u32 val;
804 bool cur_state;
805
806 reg = PCH_DPLL(pipe);
807 val = I915_READ(reg);
808 cur_state = !!(val & DPLL_VCO_ENABLE);
809 WARN(cur_state != state,
810 "PCH PLL state assertion failure (expected %s, current %s)\n",
811 state_string(state), state_string(cur_state));
812 }
813 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
814 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
815
816 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
817 enum pipe pipe, bool state)
818 {
819 int reg;
820 u32 val;
821 bool cur_state;
822
823 reg = FDI_TX_CTL(pipe);
824 val = I915_READ(reg);
825 cur_state = !!(val & FDI_TX_ENABLE);
826 WARN(cur_state != state,
827 "FDI TX state assertion failure (expected %s, current %s)\n",
828 state_string(state), state_string(cur_state));
829 }
830 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
831 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
832
833 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
834 enum pipe pipe, bool state)
835 {
836 int reg;
837 u32 val;
838 bool cur_state;
839
840 reg = FDI_RX_CTL(pipe);
841 val = I915_READ(reg);
842 cur_state = !!(val & FDI_RX_ENABLE);
843 WARN(cur_state != state,
844 "FDI RX state assertion failure (expected %s, current %s)\n",
845 state_string(state), state_string(cur_state));
846 }
847 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
848 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
849
850 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
851 enum pipe pipe)
852 {
853 int reg;
854 u32 val;
855
856 /* ILK FDI PLL is always enabled */
857 if (dev_priv->info->gen == 5)
858 return;
859
860 reg = FDI_TX_CTL(pipe);
861 val = I915_READ(reg);
862 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
863 }
864
865 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
866 enum pipe pipe)
867 {
868 int reg;
869 u32 val;
870
871 reg = FDI_RX_CTL(pipe);
872 val = I915_READ(reg);
873 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
874 }
875
876 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
877 enum pipe pipe)
878 {
879 int pp_reg, lvds_reg;
880 u32 val;
881 enum pipe panel_pipe = PIPE_A;
882 bool locked = true;
883
884 if (HAS_PCH_SPLIT(dev_priv->dev)) {
885 pp_reg = PCH_PP_CONTROL;
886 lvds_reg = PCH_LVDS;
887 } else {
888 pp_reg = PP_CONTROL;
889 lvds_reg = LVDS;
890 }
891
892 val = I915_READ(pp_reg);
893 if (!(val & PANEL_POWER_ON) ||
894 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
895 locked = false;
896
897 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
898 panel_pipe = PIPE_B;
899
900 WARN(panel_pipe == pipe && locked,
901 "panel assertion failure, pipe %c regs locked\n",
902 pipe_name(pipe));
903 }
904
905 static void assert_pipe(struct drm_i915_private *dev_priv,
906 enum pipe pipe, bool state)
907 {
908 int reg;
909 u32 val;
910 bool cur_state;
911
912 reg = PIPECONF(pipe);
913 val = I915_READ(reg);
914 cur_state = !!(val & PIPECONF_ENABLE);
915 WARN(cur_state != state,
916 "pipe %c assertion failure (expected %s, current %s)\n",
917 pipe_name(pipe), state_string(state), state_string(cur_state));
918 }
919 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
920 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
921
922 static void assert_plane_enabled(struct drm_i915_private *dev_priv,
923 enum plane plane)
924 {
925 int reg;
926 u32 val;
927
928 reg = DSPCNTR(plane);
929 val = I915_READ(reg);
930 WARN(!(val & DISPLAY_PLANE_ENABLE),
931 "plane %c assertion failure, should be active but is disabled\n",
932 plane_name(plane));
933 }
934
935 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
936 enum pipe pipe)
937 {
938 int reg, i;
939 u32 val;
940 int cur_pipe;
941
942 /* Planes are fixed to pipes on ILK+ */
943 if (HAS_PCH_SPLIT(dev_priv->dev))
944 return;
945
946 /* Need to check both planes against the pipe */
947 for (i = 0; i < 2; i++) {
948 reg = DSPCNTR(i);
949 val = I915_READ(reg);
950 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
951 DISPPLANE_SEL_PIPE_SHIFT;
952 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
953 "plane %c assertion failure, should be off on pipe %c but is still active\n",
954 plane_name(i), pipe_name(pipe));
955 }
956 }
957
958 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
959 {
960 u32 val;
961 bool enabled;
962
963 val = I915_READ(PCH_DREF_CONTROL);
964 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
965 DREF_SUPERSPREAD_SOURCE_MASK));
966 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
967 }
968
969 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
970 enum pipe pipe)
971 {
972 int reg;
973 u32 val;
974 bool enabled;
975
976 reg = TRANSCONF(pipe);
977 val = I915_READ(reg);
978 enabled = !!(val & TRANS_ENABLE);
979 WARN(enabled,
980 "transcoder assertion failed, should be off on pipe %c but is still active\n",
981 pipe_name(pipe));
982 }
983
984 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
985 enum pipe pipe, u32 port_sel, u32 val)
986 {
987 if ((val & DP_PORT_EN) == 0)
988 return false;
989
990 if (HAS_PCH_CPT(dev_priv->dev)) {
991 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
992 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
993 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
994 return false;
995 } else {
996 if ((val & DP_PIPE_MASK) != (pipe << 30))
997 return false;
998 }
999 return true;
1000 }
1001
1002 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1003 enum pipe pipe, u32 val)
1004 {
1005 if ((val & PORT_ENABLE) == 0)
1006 return false;
1007
1008 if (HAS_PCH_CPT(dev_priv->dev)) {
1009 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1010 return false;
1011 } else {
1012 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1013 return false;
1014 }
1015 return true;
1016 }
1017
1018 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1019 enum pipe pipe, u32 val)
1020 {
1021 if ((val & LVDS_PORT_EN) == 0)
1022 return false;
1023
1024 if (HAS_PCH_CPT(dev_priv->dev)) {
1025 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1026 return false;
1027 } else {
1028 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1029 return false;
1030 }
1031 return true;
1032 }
1033
1034 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1035 enum pipe pipe, u32 val)
1036 {
1037 if ((val & ADPA_DAC_ENABLE) == 0)
1038 return false;
1039 if (HAS_PCH_CPT(dev_priv->dev)) {
1040 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1041 return false;
1042 } else {
1043 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1044 return false;
1045 }
1046 return true;
1047 }
1048
1049 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1050 enum pipe pipe, int reg, u32 port_sel)
1051 {
1052 u32 val = I915_READ(reg);
1053 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1054 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1055 reg, pipe_name(pipe));
1056 }
1057
1058 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1059 enum pipe pipe, int reg)
1060 {
1061 u32 val = I915_READ(reg);
1062 WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
1063 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1064 reg, pipe_name(pipe));
1065 }
1066
1067 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1068 enum pipe pipe)
1069 {
1070 int reg;
1071 u32 val;
1072
1073 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1074 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1075 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1076
1077 reg = PCH_ADPA;
1078 val = I915_READ(reg);
1079 WARN(adpa_pipe_enabled(dev_priv, val, pipe),
1080 "PCH VGA enabled on transcoder %c, should be disabled\n",
1081 pipe_name(pipe));
1082
1083 reg = PCH_LVDS;
1084 val = I915_READ(reg);
1085 WARN(lvds_pipe_enabled(dev_priv, val, pipe),
1086 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1087 pipe_name(pipe));
1088
1089 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1090 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1091 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1092 }
1093
1094 /**
1095 * intel_enable_pll - enable a PLL
1096 * @dev_priv: i915 private structure
1097 * @pipe: pipe PLL to enable
1098 *
1099 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1100 * make sure the PLL reg is writable first though, since the panel write
1101 * protect mechanism may be enabled.
1102 *
1103 * Note! This is for pre-ILK only.
1104 */
1105 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1106 {
1107 int reg;
1108 u32 val;
1109
1110 /* No really, not for ILK+ */
1111 BUG_ON(dev_priv->info->gen >= 5);
1112
1113 /* PLL is protected by panel, make sure we can write it */
1114 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1115 assert_panel_unlocked(dev_priv, pipe);
1116
1117 reg = DPLL(pipe);
1118 val = I915_READ(reg);
1119 val |= DPLL_VCO_ENABLE;
1120
1121 /* We do this three times for luck */
1122 I915_WRITE(reg, val);
1123 POSTING_READ(reg);
1124 udelay(150); /* wait for warmup */
1125 I915_WRITE(reg, val);
1126 POSTING_READ(reg);
1127 udelay(150); /* wait for warmup */
1128 I915_WRITE(reg, val);
1129 POSTING_READ(reg);
1130 udelay(150); /* wait for warmup */
1131 }
1132
1133 /**
1134 * intel_disable_pll - disable a PLL
1135 * @dev_priv: i915 private structure
1136 * @pipe: pipe PLL to disable
1137 *
1138 * Disable the PLL for @pipe, making sure the pipe is off first.
1139 *
1140 * Note! This is for pre-ILK only.
1141 */
1142 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1143 {
1144 int reg;
1145 u32 val;
1146
1147 /* Don't disable pipe A or pipe A PLLs if needed */
1148 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1149 return;
1150
1151 /* Make sure the pipe isn't still relying on us */
1152 assert_pipe_disabled(dev_priv, pipe);
1153
1154 reg = DPLL(pipe);
1155 val = I915_READ(reg);
1156 val &= ~DPLL_VCO_ENABLE;
1157 I915_WRITE(reg, val);
1158 POSTING_READ(reg);
1159 }
1160
1161 /**
1162 * intel_enable_pch_pll - enable PCH PLL
1163 * @dev_priv: i915 private structure
1164 * @pipe: pipe PLL to enable
1165 *
1166 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1167 * drives the transcoder clock.
1168 */
1169 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1170 enum pipe pipe)
1171 {
1172 int reg;
1173 u32 val;
1174
1175 /* PCH only available on ILK+ */
1176 BUG_ON(dev_priv->info->gen < 5);
1177
1178 /* PCH refclock must be enabled first */
1179 assert_pch_refclk_enabled(dev_priv);
1180
1181 reg = PCH_DPLL(pipe);
1182 val = I915_READ(reg);
1183 val |= DPLL_VCO_ENABLE;
1184 I915_WRITE(reg, val);
1185 POSTING_READ(reg);
1186 udelay(200);
1187 }
1188
1189 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1190 enum pipe pipe)
1191 {
1192 int reg;
1193 u32 val;
1194
1195 /* PCH only available on ILK+ */
1196 BUG_ON(dev_priv->info->gen < 5);
1197
1198 /* Make sure transcoder isn't still depending on us */
1199 assert_transcoder_disabled(dev_priv, pipe);
1200
1201 reg = PCH_DPLL(pipe);
1202 val = I915_READ(reg);
1203 val &= ~DPLL_VCO_ENABLE;
1204 I915_WRITE(reg, val);
1205 POSTING_READ(reg);
1206 udelay(200);
1207 }
1208
1209 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1210 enum pipe pipe)
1211 {
1212 int reg;
1213 u32 val;
1214
1215 /* PCH only available on ILK+ */
1216 BUG_ON(dev_priv->info->gen < 5);
1217
1218 /* Make sure PCH DPLL is enabled */
1219 assert_pch_pll_enabled(dev_priv, pipe);
1220
1221 /* FDI must be feeding us bits for PCH ports */
1222 assert_fdi_tx_enabled(dev_priv, pipe);
1223 assert_fdi_rx_enabled(dev_priv, pipe);
1224
1225 reg = TRANSCONF(pipe);
1226 val = I915_READ(reg);
1227
1228 if (HAS_PCH_IBX(dev_priv->dev)) {
1229 /*
1230 * make the BPC in transcoder be consistent with
1231 * that in pipeconf reg.
1232 */
1233 val &= ~PIPE_BPC_MASK;
1234 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1235 }
1236 I915_WRITE(reg, val | TRANS_ENABLE);
1237 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1238 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1239 }
1240
1241 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1242 enum pipe pipe)
1243 {
1244 int reg;
1245 u32 val;
1246
1247 /* FDI relies on the transcoder */
1248 assert_fdi_tx_disabled(dev_priv, pipe);
1249 assert_fdi_rx_disabled(dev_priv, pipe);
1250
1251 /* Ports must be off as well */
1252 assert_pch_ports_disabled(dev_priv, pipe);
1253
1254 reg = TRANSCONF(pipe);
1255 val = I915_READ(reg);
1256 val &= ~TRANS_ENABLE;
1257 I915_WRITE(reg, val);
1258 /* wait for PCH transcoder off, transcoder state */
1259 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1260 DRM_ERROR("failed to disable transcoder\n");
1261 }
1262
1263 /**
1264 * intel_enable_pipe - enable a pipe, asserting requirements
1265 * @dev_priv: i915 private structure
1266 * @pipe: pipe to enable
1267 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1268 *
1269 * Enable @pipe, making sure that various hardware specific requirements
1270 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1271 *
1272 * @pipe should be %PIPE_A or %PIPE_B.
1273 *
1274 * Will wait until the pipe is actually running (i.e. first vblank) before
1275 * returning.
1276 */
1277 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1278 bool pch_port)
1279 {
1280 int reg;
1281 u32 val;
1282
1283 /*
1284 * A pipe without a PLL won't actually be able to drive bits from
1285 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1286 * need the check.
1287 */
1288 if (!HAS_PCH_SPLIT(dev_priv->dev))
1289 assert_pll_enabled(dev_priv, pipe);
1290 else {
1291 if (pch_port) {
1292 /* if driving the PCH, we need FDI enabled */
1293 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1294 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1295 }
1296 /* FIXME: assert CPU port conditions for SNB+ */
1297 }
1298
1299 reg = PIPECONF(pipe);
1300 val = I915_READ(reg);
1301 if (val & PIPECONF_ENABLE)
1302 return;
1303
1304 I915_WRITE(reg, val | PIPECONF_ENABLE);
1305 intel_wait_for_vblank(dev_priv->dev, pipe);
1306 }
1307
1308 /**
1309 * intel_disable_pipe - disable a pipe, asserting requirements
1310 * @dev_priv: i915 private structure
1311 * @pipe: pipe to disable
1312 *
1313 * Disable @pipe, making sure that various hardware specific requirements
1314 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1315 *
1316 * @pipe should be %PIPE_A or %PIPE_B.
1317 *
1318 * Will wait until the pipe has shut down before returning.
1319 */
1320 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1321 enum pipe pipe)
1322 {
1323 int reg;
1324 u32 val;
1325
1326 /*
1327 * Make sure planes won't keep trying to pump pixels to us,
1328 * or we might hang the display.
1329 */
1330 assert_planes_disabled(dev_priv, pipe);
1331
1332 /* Don't disable pipe A or pipe A PLLs if needed */
1333 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1334 return;
1335
1336 reg = PIPECONF(pipe);
1337 val = I915_READ(reg);
1338 if ((val & PIPECONF_ENABLE) == 0)
1339 return;
1340
1341 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1342 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1343 }
1344
1345 /*
1346 * Plane regs are double buffered, going from enabled->disabled needs a
1347 * trigger in order to latch. The display address reg provides this.
1348 */
1349 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1350 enum plane plane)
1351 {
1352 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1353 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1354 }
1355
1356 /**
1357 * intel_enable_plane - enable a display plane on a given pipe
1358 * @dev_priv: i915 private structure
1359 * @plane: plane to enable
1360 * @pipe: pipe being fed
1361 *
1362 * Enable @plane on @pipe, making sure that @pipe is running first.
1363 */
1364 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1365 enum plane plane, enum pipe pipe)
1366 {
1367 int reg;
1368 u32 val;
1369
1370 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1371 assert_pipe_enabled(dev_priv, pipe);
1372
1373 reg = DSPCNTR(plane);
1374 val = I915_READ(reg);
1375 if (val & DISPLAY_PLANE_ENABLE)
1376 return;
1377
1378 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1379 intel_flush_display_plane(dev_priv, plane);
1380 intel_wait_for_vblank(dev_priv->dev, pipe);
1381 }
1382
1383 /**
1384 * intel_disable_plane - disable a display plane
1385 * @dev_priv: i915 private structure
1386 * @plane: plane to disable
1387 * @pipe: pipe consuming the data
1388 *
1389 * Disable @plane; should be an independent operation.
1390 */
1391 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1392 enum plane plane, enum pipe pipe)
1393 {
1394 int reg;
1395 u32 val;
1396
1397 reg = DSPCNTR(plane);
1398 val = I915_READ(reg);
1399 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1400 return;
1401
1402 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1403 intel_flush_display_plane(dev_priv, plane);
1404 intel_wait_for_vblank(dev_priv->dev, pipe);
1405 }
1406
1407 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1408 enum pipe pipe, int reg, u32 port_sel)
1409 {
1410 u32 val = I915_READ(reg);
1411 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1412 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1413 I915_WRITE(reg, val & ~DP_PORT_EN);
1414 }
1415 }
1416
1417 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1418 enum pipe pipe, int reg)
1419 {
1420 u32 val = I915_READ(reg);
1421 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1422 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1423 reg, pipe);
1424 I915_WRITE(reg, val & ~PORT_ENABLE);
1425 }
1426 }
1427
1428 /* Disable any ports connected to this transcoder */
1429 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1430 enum pipe pipe)
1431 {
1432 u32 reg, val;
1433
1434 val = I915_READ(PCH_PP_CONTROL);
1435 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1436
1437 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1438 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1439 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1440
1441 reg = PCH_ADPA;
1442 val = I915_READ(reg);
1443 if (adpa_pipe_enabled(dev_priv, val, pipe))
1444 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1445
1446 reg = PCH_LVDS;
1447 val = I915_READ(reg);
1448 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1449 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1450 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1451 POSTING_READ(reg);
1452 udelay(100);
1453 }
1454
1455 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1456 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1457 disable_pch_hdmi(dev_priv, pipe, HDMID);
1458 }
1459
1460 static void i8xx_disable_fbc(struct drm_device *dev)
1461 {
1462 struct drm_i915_private *dev_priv = dev->dev_private;
1463 u32 fbc_ctl;
1464
1465 /* Disable compression */
1466 fbc_ctl = I915_READ(FBC_CONTROL);
1467 if ((fbc_ctl & FBC_CTL_EN) == 0)
1468 return;
1469
1470 fbc_ctl &= ~FBC_CTL_EN;
1471 I915_WRITE(FBC_CONTROL, fbc_ctl);
1472
1473 /* Wait for compressing bit to clear */
1474 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1475 DRM_DEBUG_KMS("FBC idle timed out\n");
1476 return;
1477 }
1478
1479 DRM_DEBUG_KMS("disabled FBC\n");
1480 }
1481
1482 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1483 {
1484 struct drm_device *dev = crtc->dev;
1485 struct drm_i915_private *dev_priv = dev->dev_private;
1486 struct drm_framebuffer *fb = crtc->fb;
1487 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1488 struct drm_i915_gem_object *obj = intel_fb->obj;
1489 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1490 int cfb_pitch;
1491 int plane, i;
1492 u32 fbc_ctl, fbc_ctl2;
1493
1494 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1495 if (fb->pitch < cfb_pitch)
1496 cfb_pitch = fb->pitch;
1497
1498 /* FBC_CTL wants 64B units */
1499 cfb_pitch = (cfb_pitch / 64) - 1;
1500 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1501
1502 /* Clear old tags */
1503 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1504 I915_WRITE(FBC_TAG + (i * 4), 0);
1505
1506 /* Set it up... */
1507 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1508 fbc_ctl2 |= plane;
1509 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1510 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1511
1512 /* enable it... */
1513 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1514 if (IS_I945GM(dev))
1515 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1516 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1517 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1518 fbc_ctl |= obj->fence_reg;
1519 I915_WRITE(FBC_CONTROL, fbc_ctl);
1520
1521 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1522 cfb_pitch, crtc->y, intel_crtc->plane);
1523 }
1524
1525 static bool i8xx_fbc_enabled(struct drm_device *dev)
1526 {
1527 struct drm_i915_private *dev_priv = dev->dev_private;
1528
1529 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1530 }
1531
1532 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1533 {
1534 struct drm_device *dev = crtc->dev;
1535 struct drm_i915_private *dev_priv = dev->dev_private;
1536 struct drm_framebuffer *fb = crtc->fb;
1537 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1538 struct drm_i915_gem_object *obj = intel_fb->obj;
1539 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1540 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1541 unsigned long stall_watermark = 200;
1542 u32 dpfc_ctl;
1543
1544 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1545 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
1546 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1547
1548 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1549 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1550 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1551 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1552
1553 /* enable it... */
1554 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1555
1556 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1557 }
1558
1559 static void g4x_disable_fbc(struct drm_device *dev)
1560 {
1561 struct drm_i915_private *dev_priv = dev->dev_private;
1562 u32 dpfc_ctl;
1563
1564 /* Disable compression */
1565 dpfc_ctl = I915_READ(DPFC_CONTROL);
1566 if (dpfc_ctl & DPFC_CTL_EN) {
1567 dpfc_ctl &= ~DPFC_CTL_EN;
1568 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1569
1570 DRM_DEBUG_KMS("disabled FBC\n");
1571 }
1572 }
1573
1574 static bool g4x_fbc_enabled(struct drm_device *dev)
1575 {
1576 struct drm_i915_private *dev_priv = dev->dev_private;
1577
1578 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1579 }
1580
1581 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1582 {
1583 struct drm_i915_private *dev_priv = dev->dev_private;
1584 u32 blt_ecoskpd;
1585
1586 /* Make sure blitter notifies FBC of writes */
1587 gen6_gt_force_wake_get(dev_priv);
1588 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1589 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1590 GEN6_BLITTER_LOCK_SHIFT;
1591 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1592 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1593 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1594 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1595 GEN6_BLITTER_LOCK_SHIFT);
1596 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1597 POSTING_READ(GEN6_BLITTER_ECOSKPD);
1598 gen6_gt_force_wake_put(dev_priv);
1599 }
1600
1601 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1602 {
1603 struct drm_device *dev = crtc->dev;
1604 struct drm_i915_private *dev_priv = dev->dev_private;
1605 struct drm_framebuffer *fb = crtc->fb;
1606 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1607 struct drm_i915_gem_object *obj = intel_fb->obj;
1608 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1609 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1610 unsigned long stall_watermark = 200;
1611 u32 dpfc_ctl;
1612
1613 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1614 dpfc_ctl &= DPFC_RESERVED;
1615 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1616 /* Set persistent mode for front-buffer rendering, ala X. */
1617 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
1618 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
1619 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1620
1621 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1622 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1623 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1624 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1625 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1626 /* enable it... */
1627 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1628
1629 if (IS_GEN6(dev)) {
1630 I915_WRITE(SNB_DPFC_CTL_SA,
1631 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
1632 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1633 sandybridge_blit_fbc_update(dev);
1634 }
1635
1636 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1637 }
1638
1639 static void ironlake_disable_fbc(struct drm_device *dev)
1640 {
1641 struct drm_i915_private *dev_priv = dev->dev_private;
1642 u32 dpfc_ctl;
1643
1644 /* Disable compression */
1645 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1646 if (dpfc_ctl & DPFC_CTL_EN) {
1647 dpfc_ctl &= ~DPFC_CTL_EN;
1648 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1649
1650 DRM_DEBUG_KMS("disabled FBC\n");
1651 }
1652 }
1653
1654 static bool ironlake_fbc_enabled(struct drm_device *dev)
1655 {
1656 struct drm_i915_private *dev_priv = dev->dev_private;
1657
1658 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1659 }
1660
1661 bool intel_fbc_enabled(struct drm_device *dev)
1662 {
1663 struct drm_i915_private *dev_priv = dev->dev_private;
1664
1665 if (!dev_priv->display.fbc_enabled)
1666 return false;
1667
1668 return dev_priv->display.fbc_enabled(dev);
1669 }
1670
1671 static void intel_fbc_work_fn(struct work_struct *__work)
1672 {
1673 struct intel_fbc_work *work =
1674 container_of(to_delayed_work(__work),
1675 struct intel_fbc_work, work);
1676 struct drm_device *dev = work->crtc->dev;
1677 struct drm_i915_private *dev_priv = dev->dev_private;
1678
1679 mutex_lock(&dev->struct_mutex);
1680 if (work == dev_priv->fbc_work) {
1681 /* Double check that we haven't switched fb without cancelling
1682 * the prior work.
1683 */
1684 if (work->crtc->fb == work->fb) {
1685 dev_priv->display.enable_fbc(work->crtc,
1686 work->interval);
1687
1688 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1689 dev_priv->cfb_fb = work->crtc->fb->base.id;
1690 dev_priv->cfb_y = work->crtc->y;
1691 }
1692
1693 dev_priv->fbc_work = NULL;
1694 }
1695 mutex_unlock(&dev->struct_mutex);
1696
1697 kfree(work);
1698 }
1699
1700 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1701 {
1702 if (dev_priv->fbc_work == NULL)
1703 return;
1704
1705 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1706
1707 /* Synchronisation is provided by struct_mutex and checking of
1708 * dev_priv->fbc_work, so we can perform the cancellation
1709 * entirely asynchronously.
1710 */
1711 if (cancel_delayed_work(&dev_priv->fbc_work->work))
1712 /* tasklet was killed before being run, clean up */
1713 kfree(dev_priv->fbc_work);
1714
1715 /* Mark the work as no longer wanted so that if it does
1716 * wake-up (because the work was already running and waiting
1717 * for our mutex), it will discover that is no longer
1718 * necessary to run.
1719 */
1720 dev_priv->fbc_work = NULL;
1721 }
1722
1723 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1724 {
1725 struct intel_fbc_work *work;
1726 struct drm_device *dev = crtc->dev;
1727 struct drm_i915_private *dev_priv = dev->dev_private;
1728
1729 if (!dev_priv->display.enable_fbc)
1730 return;
1731
1732 intel_cancel_fbc_work(dev_priv);
1733
1734 work = kzalloc(sizeof *work, GFP_KERNEL);
1735 if (work == NULL) {
1736 dev_priv->display.enable_fbc(crtc, interval);
1737 return;
1738 }
1739
1740 work->crtc = crtc;
1741 work->fb = crtc->fb;
1742 work->interval = interval;
1743 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1744
1745 dev_priv->fbc_work = work;
1746
1747 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1748
1749 /* Delay the actual enabling to let pageflipping cease and the
1750 * display to settle before starting the compression. Note that
1751 * this delay also serves a second purpose: it allows for a
1752 * vblank to pass after disabling the FBC before we attempt
1753 * to modify the control registers.
1754 *
1755 * A more complicated solution would involve tracking vblanks
1756 * following the termination of the page-flipping sequence
1757 * and indeed performing the enable as a co-routine and not
1758 * waiting synchronously upon the vblank.
1759 */
1760 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
1761 }
1762
1763 void intel_disable_fbc(struct drm_device *dev)
1764 {
1765 struct drm_i915_private *dev_priv = dev->dev_private;
1766
1767 intel_cancel_fbc_work(dev_priv);
1768
1769 if (!dev_priv->display.disable_fbc)
1770 return;
1771
1772 dev_priv->display.disable_fbc(dev);
1773 dev_priv->cfb_plane = -1;
1774 }
1775
1776 /**
1777 * intel_update_fbc - enable/disable FBC as needed
1778 * @dev: the drm_device
1779 *
1780 * Set up the framebuffer compression hardware at mode set time. We
1781 * enable it if possible:
1782 * - plane A only (on pre-965)
1783 * - no pixel mulitply/line duplication
1784 * - no alpha buffer discard
1785 * - no dual wide
1786 * - framebuffer <= 2048 in width, 1536 in height
1787 *
1788 * We can't assume that any compression will take place (worst case),
1789 * so the compressed buffer has to be the same size as the uncompressed
1790 * one. It also must reside (along with the line length buffer) in
1791 * stolen memory.
1792 *
1793 * We need to enable/disable FBC on a global basis.
1794 */
1795 static void intel_update_fbc(struct drm_device *dev)
1796 {
1797 struct drm_i915_private *dev_priv = dev->dev_private;
1798 struct drm_crtc *crtc = NULL, *tmp_crtc;
1799 struct intel_crtc *intel_crtc;
1800 struct drm_framebuffer *fb;
1801 struct intel_framebuffer *intel_fb;
1802 struct drm_i915_gem_object *obj;
1803 int enable_fbc;
1804
1805 DRM_DEBUG_KMS("\n");
1806
1807 if (!i915_powersave)
1808 return;
1809
1810 if (!I915_HAS_FBC(dev))
1811 return;
1812
1813 /*
1814 * If FBC is already on, we just have to verify that we can
1815 * keep it that way...
1816 * Need to disable if:
1817 * - more than one pipe is active
1818 * - changing FBC params (stride, fence, mode)
1819 * - new fb is too large to fit in compressed buffer
1820 * - going to an unsupported config (interlace, pixel multiply, etc.)
1821 */
1822 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1823 if (tmp_crtc->enabled && tmp_crtc->fb) {
1824 if (crtc) {
1825 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1826 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1827 goto out_disable;
1828 }
1829 crtc = tmp_crtc;
1830 }
1831 }
1832
1833 if (!crtc || crtc->fb == NULL) {
1834 DRM_DEBUG_KMS("no output, disabling\n");
1835 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1836 goto out_disable;
1837 }
1838
1839 intel_crtc = to_intel_crtc(crtc);
1840 fb = crtc->fb;
1841 intel_fb = to_intel_framebuffer(fb);
1842 obj = intel_fb->obj;
1843
1844 enable_fbc = i915_enable_fbc;
1845 if (enable_fbc < 0) {
1846 DRM_DEBUG_KMS("fbc set to per-chip default\n");
1847 enable_fbc = 1;
1848 if (INTEL_INFO(dev)->gen <= 5)
1849 enable_fbc = 0;
1850 }
1851 if (!enable_fbc) {
1852 DRM_DEBUG_KMS("fbc disabled per module param\n");
1853 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1854 goto out_disable;
1855 }
1856 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1857 DRM_DEBUG_KMS("framebuffer too large, disabling "
1858 "compression\n");
1859 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1860 goto out_disable;
1861 }
1862 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1863 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1864 DRM_DEBUG_KMS("mode incompatible with compression, "
1865 "disabling\n");
1866 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1867 goto out_disable;
1868 }
1869 if ((crtc->mode.hdisplay > 2048) ||
1870 (crtc->mode.vdisplay > 1536)) {
1871 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1872 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1873 goto out_disable;
1874 }
1875 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1876 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1877 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1878 goto out_disable;
1879 }
1880
1881 /* The use of a CPU fence is mandatory in order to detect writes
1882 * by the CPU to the scanout and trigger updates to the FBC.
1883 */
1884 if (obj->tiling_mode != I915_TILING_X ||
1885 obj->fence_reg == I915_FENCE_REG_NONE) {
1886 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
1887 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1888 goto out_disable;
1889 }
1890
1891 /* If the kernel debugger is active, always disable compression */
1892 if (in_dbg_master())
1893 goto out_disable;
1894
1895 /* If the scanout has not changed, don't modify the FBC settings.
1896 * Note that we make the fundamental assumption that the fb->obj
1897 * cannot be unpinned (and have its GTT offset and fence revoked)
1898 * without first being decoupled from the scanout and FBC disabled.
1899 */
1900 if (dev_priv->cfb_plane == intel_crtc->plane &&
1901 dev_priv->cfb_fb == fb->base.id &&
1902 dev_priv->cfb_y == crtc->y)
1903 return;
1904
1905 if (intel_fbc_enabled(dev)) {
1906 /* We update FBC along two paths, after changing fb/crtc
1907 * configuration (modeswitching) and after page-flipping
1908 * finishes. For the latter, we know that not only did
1909 * we disable the FBC at the start of the page-flip
1910 * sequence, but also more than one vblank has passed.
1911 *
1912 * For the former case of modeswitching, it is possible
1913 * to switch between two FBC valid configurations
1914 * instantaneously so we do need to disable the FBC
1915 * before we can modify its control registers. We also
1916 * have to wait for the next vblank for that to take
1917 * effect. However, since we delay enabling FBC we can
1918 * assume that a vblank has passed since disabling and
1919 * that we can safely alter the registers in the deferred
1920 * callback.
1921 *
1922 * In the scenario that we go from a valid to invalid
1923 * and then back to valid FBC configuration we have
1924 * no strict enforcement that a vblank occurred since
1925 * disabling the FBC. However, along all current pipe
1926 * disabling paths we do need to wait for a vblank at
1927 * some point. And we wait before enabling FBC anyway.
1928 */
1929 DRM_DEBUG_KMS("disabling active FBC for update\n");
1930 intel_disable_fbc(dev);
1931 }
1932
1933 intel_enable_fbc(crtc, 500);
1934 return;
1935
1936 out_disable:
1937 /* Multiple disables should be harmless */
1938 if (intel_fbc_enabled(dev)) {
1939 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1940 intel_disable_fbc(dev);
1941 }
1942 }
1943
1944 int
1945 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1946 struct drm_i915_gem_object *obj,
1947 struct intel_ring_buffer *pipelined)
1948 {
1949 struct drm_i915_private *dev_priv = dev->dev_private;
1950 u32 alignment;
1951 int ret;
1952
1953 switch (obj->tiling_mode) {
1954 case I915_TILING_NONE:
1955 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1956 alignment = 128 * 1024;
1957 else if (INTEL_INFO(dev)->gen >= 4)
1958 alignment = 4 * 1024;
1959 else
1960 alignment = 64 * 1024;
1961 break;
1962 case I915_TILING_X:
1963 /* pin() will align the object as required by fence */
1964 alignment = 0;
1965 break;
1966 case I915_TILING_Y:
1967 /* FIXME: Is this true? */
1968 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1969 return -EINVAL;
1970 default:
1971 BUG();
1972 }
1973
1974 dev_priv->mm.interruptible = false;
1975 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1976 if (ret)
1977 goto err_interruptible;
1978
1979 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1980 * fence, whereas 965+ only requires a fence if using
1981 * framebuffer compression. For simplicity, we always install
1982 * a fence as the cost is not that onerous.
1983 */
1984 if (obj->tiling_mode != I915_TILING_NONE) {
1985 ret = i915_gem_object_get_fence(obj, pipelined);
1986 if (ret)
1987 goto err_unpin;
1988 }
1989
1990 dev_priv->mm.interruptible = true;
1991 return 0;
1992
1993 err_unpin:
1994 i915_gem_object_unpin(obj);
1995 err_interruptible:
1996 dev_priv->mm.interruptible = true;
1997 return ret;
1998 }
1999
2000 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2001 int x, int y)
2002 {
2003 struct drm_device *dev = crtc->dev;
2004 struct drm_i915_private *dev_priv = dev->dev_private;
2005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2006 struct intel_framebuffer *intel_fb;
2007 struct drm_i915_gem_object *obj;
2008 int plane = intel_crtc->plane;
2009 unsigned long Start, Offset;
2010 u32 dspcntr;
2011 u32 reg;
2012
2013 switch (plane) {
2014 case 0:
2015 case 1:
2016 break;
2017 default:
2018 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2019 return -EINVAL;
2020 }
2021
2022 intel_fb = to_intel_framebuffer(fb);
2023 obj = intel_fb->obj;
2024
2025 reg = DSPCNTR(plane);
2026 dspcntr = I915_READ(reg);
2027 /* Mask out pixel format bits in case we change it */
2028 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2029 switch (fb->bits_per_pixel) {
2030 case 8:
2031 dspcntr |= DISPPLANE_8BPP;
2032 break;
2033 case 16:
2034 if (fb->depth == 15)
2035 dspcntr |= DISPPLANE_15_16BPP;
2036 else
2037 dspcntr |= DISPPLANE_16BPP;
2038 break;
2039 case 24:
2040 case 32:
2041 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2042 break;
2043 default:
2044 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2045 return -EINVAL;
2046 }
2047 if (INTEL_INFO(dev)->gen >= 4) {
2048 if (obj->tiling_mode != I915_TILING_NONE)
2049 dspcntr |= DISPPLANE_TILED;
2050 else
2051 dspcntr &= ~DISPPLANE_TILED;
2052 }
2053
2054 I915_WRITE(reg, dspcntr);
2055
2056 Start = obj->gtt_offset;
2057 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2058
2059 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2060 Start, Offset, x, y, fb->pitch);
2061 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2062 if (INTEL_INFO(dev)->gen >= 4) {
2063 I915_WRITE(DSPSURF(plane), Start);
2064 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2065 I915_WRITE(DSPADDR(plane), Offset);
2066 } else
2067 I915_WRITE(DSPADDR(plane), Start + Offset);
2068 POSTING_READ(reg);
2069
2070 return 0;
2071 }
2072
2073 static int ironlake_update_plane(struct drm_crtc *crtc,
2074 struct drm_framebuffer *fb, int x, int y)
2075 {
2076 struct drm_device *dev = crtc->dev;
2077 struct drm_i915_private *dev_priv = dev->dev_private;
2078 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2079 struct intel_framebuffer *intel_fb;
2080 struct drm_i915_gem_object *obj;
2081 int plane = intel_crtc->plane;
2082 unsigned long Start, Offset;
2083 u32 dspcntr;
2084 u32 reg;
2085
2086 switch (plane) {
2087 case 0:
2088 case 1:
2089 break;
2090 default:
2091 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2092 return -EINVAL;
2093 }
2094
2095 intel_fb = to_intel_framebuffer(fb);
2096 obj = intel_fb->obj;
2097
2098 reg = DSPCNTR(plane);
2099 dspcntr = I915_READ(reg);
2100 /* Mask out pixel format bits in case we change it */
2101 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2102 switch (fb->bits_per_pixel) {
2103 case 8:
2104 dspcntr |= DISPPLANE_8BPP;
2105 break;
2106 case 16:
2107 if (fb->depth != 16)
2108 return -EINVAL;
2109
2110 dspcntr |= DISPPLANE_16BPP;
2111 break;
2112 case 24:
2113 case 32:
2114 if (fb->depth == 24)
2115 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2116 else if (fb->depth == 30)
2117 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2118 else
2119 return -EINVAL;
2120 break;
2121 default:
2122 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2123 return -EINVAL;
2124 }
2125
2126 if (obj->tiling_mode != I915_TILING_NONE)
2127 dspcntr |= DISPPLANE_TILED;
2128 else
2129 dspcntr &= ~DISPPLANE_TILED;
2130
2131 /* must disable */
2132 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2133
2134 I915_WRITE(reg, dspcntr);
2135
2136 Start = obj->gtt_offset;
2137 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2138
2139 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2140 Start, Offset, x, y, fb->pitch);
2141 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2142 I915_WRITE(DSPSURF(plane), Start);
2143 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2144 I915_WRITE(DSPADDR(plane), Offset);
2145 POSTING_READ(reg);
2146
2147 return 0;
2148 }
2149
2150 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2151 static int
2152 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2153 int x, int y, enum mode_set_atomic state)
2154 {
2155 struct drm_device *dev = crtc->dev;
2156 struct drm_i915_private *dev_priv = dev->dev_private;
2157 int ret;
2158
2159 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2160 if (ret)
2161 return ret;
2162
2163 intel_update_fbc(dev);
2164 intel_increase_pllclock(crtc);
2165
2166 return 0;
2167 }
2168
2169 static int
2170 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2171 struct drm_framebuffer *old_fb)
2172 {
2173 struct drm_device *dev = crtc->dev;
2174 struct drm_i915_master_private *master_priv;
2175 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2176 int ret;
2177
2178 /* no fb bound */
2179 if (!crtc->fb) {
2180 DRM_ERROR("No FB bound\n");
2181 return 0;
2182 }
2183
2184 switch (intel_crtc->plane) {
2185 case 0:
2186 case 1:
2187 break;
2188 default:
2189 DRM_ERROR("no plane for crtc\n");
2190 return -EINVAL;
2191 }
2192
2193 mutex_lock(&dev->struct_mutex);
2194 ret = intel_pin_and_fence_fb_obj(dev,
2195 to_intel_framebuffer(crtc->fb)->obj,
2196 NULL);
2197 if (ret != 0) {
2198 mutex_unlock(&dev->struct_mutex);
2199 DRM_ERROR("pin & fence failed\n");
2200 return ret;
2201 }
2202
2203 if (old_fb) {
2204 struct drm_i915_private *dev_priv = dev->dev_private;
2205 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2206
2207 wait_event(dev_priv->pending_flip_queue,
2208 atomic_read(&dev_priv->mm.wedged) ||
2209 atomic_read(&obj->pending_flip) == 0);
2210
2211 /* Big Hammer, we also need to ensure that any pending
2212 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2213 * current scanout is retired before unpinning the old
2214 * framebuffer.
2215 *
2216 * This should only fail upon a hung GPU, in which case we
2217 * can safely continue.
2218 */
2219 ret = i915_gem_object_finish_gpu(obj);
2220 (void) ret;
2221 }
2222
2223 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2224 LEAVE_ATOMIC_MODE_SET);
2225 if (ret) {
2226 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2227 mutex_unlock(&dev->struct_mutex);
2228 DRM_ERROR("failed to update base address\n");
2229 return ret;
2230 }
2231
2232 if (old_fb) {
2233 intel_wait_for_vblank(dev, intel_crtc->pipe);
2234 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
2235 }
2236
2237 mutex_unlock(&dev->struct_mutex);
2238
2239 if (!dev->primary->master)
2240 return 0;
2241
2242 master_priv = dev->primary->master->driver_priv;
2243 if (!master_priv->sarea_priv)
2244 return 0;
2245
2246 if (intel_crtc->pipe) {
2247 master_priv->sarea_priv->pipeB_x = x;
2248 master_priv->sarea_priv->pipeB_y = y;
2249 } else {
2250 master_priv->sarea_priv->pipeA_x = x;
2251 master_priv->sarea_priv->pipeA_y = y;
2252 }
2253
2254 return 0;
2255 }
2256
2257 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2258 {
2259 struct drm_device *dev = crtc->dev;
2260 struct drm_i915_private *dev_priv = dev->dev_private;
2261 u32 dpa_ctl;
2262
2263 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2264 dpa_ctl = I915_READ(DP_A);
2265 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2266
2267 if (clock < 200000) {
2268 u32 temp;
2269 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2270 /* workaround for 160Mhz:
2271 1) program 0x4600c bits 15:0 = 0x8124
2272 2) program 0x46010 bit 0 = 1
2273 3) program 0x46034 bit 24 = 1
2274 4) program 0x64000 bit 14 = 1
2275 */
2276 temp = I915_READ(0x4600c);
2277 temp &= 0xffff0000;
2278 I915_WRITE(0x4600c, temp | 0x8124);
2279
2280 temp = I915_READ(0x46010);
2281 I915_WRITE(0x46010, temp | 1);
2282
2283 temp = I915_READ(0x46034);
2284 I915_WRITE(0x46034, temp | (1 << 24));
2285 } else {
2286 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2287 }
2288 I915_WRITE(DP_A, dpa_ctl);
2289
2290 POSTING_READ(DP_A);
2291 udelay(500);
2292 }
2293
2294 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2295 {
2296 struct drm_device *dev = crtc->dev;
2297 struct drm_i915_private *dev_priv = dev->dev_private;
2298 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2299 int pipe = intel_crtc->pipe;
2300 u32 reg, temp;
2301
2302 /* enable normal train */
2303 reg = FDI_TX_CTL(pipe);
2304 temp = I915_READ(reg);
2305 if (IS_IVYBRIDGE(dev)) {
2306 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2307 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2308 } else {
2309 temp &= ~FDI_LINK_TRAIN_NONE;
2310 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2311 }
2312 I915_WRITE(reg, temp);
2313
2314 reg = FDI_RX_CTL(pipe);
2315 temp = I915_READ(reg);
2316 if (HAS_PCH_CPT(dev)) {
2317 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2318 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2319 } else {
2320 temp &= ~FDI_LINK_TRAIN_NONE;
2321 temp |= FDI_LINK_TRAIN_NONE;
2322 }
2323 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2324
2325 /* wait one idle pattern time */
2326 POSTING_READ(reg);
2327 udelay(1000);
2328
2329 /* IVB wants error correction enabled */
2330 if (IS_IVYBRIDGE(dev))
2331 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2332 FDI_FE_ERRC_ENABLE);
2333 }
2334
2335 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2336 {
2337 struct drm_i915_private *dev_priv = dev->dev_private;
2338 u32 flags = I915_READ(SOUTH_CHICKEN1);
2339
2340 flags |= FDI_PHASE_SYNC_OVR(pipe);
2341 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2342 flags |= FDI_PHASE_SYNC_EN(pipe);
2343 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2344 POSTING_READ(SOUTH_CHICKEN1);
2345 }
2346
2347 /* The FDI link training functions for ILK/Ibexpeak. */
2348 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2349 {
2350 struct drm_device *dev = crtc->dev;
2351 struct drm_i915_private *dev_priv = dev->dev_private;
2352 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2353 int pipe = intel_crtc->pipe;
2354 int plane = intel_crtc->plane;
2355 u32 reg, temp, tries;
2356
2357 /* FDI needs bits from pipe & plane first */
2358 assert_pipe_enabled(dev_priv, pipe);
2359 assert_plane_enabled(dev_priv, plane);
2360
2361 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2362 for train result */
2363 reg = FDI_RX_IMR(pipe);
2364 temp = I915_READ(reg);
2365 temp &= ~FDI_RX_SYMBOL_LOCK;
2366 temp &= ~FDI_RX_BIT_LOCK;
2367 I915_WRITE(reg, temp);
2368 I915_READ(reg);
2369 udelay(150);
2370
2371 /* enable CPU FDI TX and PCH FDI RX */
2372 reg = FDI_TX_CTL(pipe);
2373 temp = I915_READ(reg);
2374 temp &= ~(7 << 19);
2375 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2376 temp &= ~FDI_LINK_TRAIN_NONE;
2377 temp |= FDI_LINK_TRAIN_PATTERN_1;
2378 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2379
2380 reg = FDI_RX_CTL(pipe);
2381 temp = I915_READ(reg);
2382 temp &= ~FDI_LINK_TRAIN_NONE;
2383 temp |= FDI_LINK_TRAIN_PATTERN_1;
2384 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2385
2386 POSTING_READ(reg);
2387 udelay(150);
2388
2389 /* Ironlake workaround, enable clock pointer after FDI enable*/
2390 if (HAS_PCH_IBX(dev)) {
2391 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2392 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2393 FDI_RX_PHASE_SYNC_POINTER_EN);
2394 }
2395
2396 reg = FDI_RX_IIR(pipe);
2397 for (tries = 0; tries < 5; tries++) {
2398 temp = I915_READ(reg);
2399 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2400
2401 if ((temp & FDI_RX_BIT_LOCK)) {
2402 DRM_DEBUG_KMS("FDI train 1 done.\n");
2403 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2404 break;
2405 }
2406 }
2407 if (tries == 5)
2408 DRM_ERROR("FDI train 1 fail!\n");
2409
2410 /* Train 2 */
2411 reg = FDI_TX_CTL(pipe);
2412 temp = I915_READ(reg);
2413 temp &= ~FDI_LINK_TRAIN_NONE;
2414 temp |= FDI_LINK_TRAIN_PATTERN_2;
2415 I915_WRITE(reg, temp);
2416
2417 reg = FDI_RX_CTL(pipe);
2418 temp = I915_READ(reg);
2419 temp &= ~FDI_LINK_TRAIN_NONE;
2420 temp |= FDI_LINK_TRAIN_PATTERN_2;
2421 I915_WRITE(reg, temp);
2422
2423 POSTING_READ(reg);
2424 udelay(150);
2425
2426 reg = FDI_RX_IIR(pipe);
2427 for (tries = 0; tries < 5; tries++) {
2428 temp = I915_READ(reg);
2429 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2430
2431 if (temp & FDI_RX_SYMBOL_LOCK) {
2432 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2433 DRM_DEBUG_KMS("FDI train 2 done.\n");
2434 break;
2435 }
2436 }
2437 if (tries == 5)
2438 DRM_ERROR("FDI train 2 fail!\n");
2439
2440 DRM_DEBUG_KMS("FDI train done\n");
2441
2442 }
2443
2444 static const int snb_b_fdi_train_param[] = {
2445 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2446 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2447 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2448 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2449 };
2450
2451 /* The FDI link training functions for SNB/Cougarpoint. */
2452 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2453 {
2454 struct drm_device *dev = crtc->dev;
2455 struct drm_i915_private *dev_priv = dev->dev_private;
2456 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2457 int pipe = intel_crtc->pipe;
2458 u32 reg, temp, i;
2459
2460 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2461 for train result */
2462 reg = FDI_RX_IMR(pipe);
2463 temp = I915_READ(reg);
2464 temp &= ~FDI_RX_SYMBOL_LOCK;
2465 temp &= ~FDI_RX_BIT_LOCK;
2466 I915_WRITE(reg, temp);
2467
2468 POSTING_READ(reg);
2469 udelay(150);
2470
2471 /* enable CPU FDI TX and PCH FDI RX */
2472 reg = FDI_TX_CTL(pipe);
2473 temp = I915_READ(reg);
2474 temp &= ~(7 << 19);
2475 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2476 temp &= ~FDI_LINK_TRAIN_NONE;
2477 temp |= FDI_LINK_TRAIN_PATTERN_1;
2478 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2479 /* SNB-B */
2480 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2481 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2482
2483 reg = FDI_RX_CTL(pipe);
2484 temp = I915_READ(reg);
2485 if (HAS_PCH_CPT(dev)) {
2486 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2487 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2488 } else {
2489 temp &= ~FDI_LINK_TRAIN_NONE;
2490 temp |= FDI_LINK_TRAIN_PATTERN_1;
2491 }
2492 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2493
2494 POSTING_READ(reg);
2495 udelay(150);
2496
2497 if (HAS_PCH_CPT(dev))
2498 cpt_phase_pointer_enable(dev, pipe);
2499
2500 for (i = 0; i < 4; i++) {
2501 reg = FDI_TX_CTL(pipe);
2502 temp = I915_READ(reg);
2503 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2504 temp |= snb_b_fdi_train_param[i];
2505 I915_WRITE(reg, temp);
2506
2507 POSTING_READ(reg);
2508 udelay(500);
2509
2510 reg = FDI_RX_IIR(pipe);
2511 temp = I915_READ(reg);
2512 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2513
2514 if (temp & FDI_RX_BIT_LOCK) {
2515 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2516 DRM_DEBUG_KMS("FDI train 1 done.\n");
2517 break;
2518 }
2519 }
2520 if (i == 4)
2521 DRM_ERROR("FDI train 1 fail!\n");
2522
2523 /* Train 2 */
2524 reg = FDI_TX_CTL(pipe);
2525 temp = I915_READ(reg);
2526 temp &= ~FDI_LINK_TRAIN_NONE;
2527 temp |= FDI_LINK_TRAIN_PATTERN_2;
2528 if (IS_GEN6(dev)) {
2529 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2530 /* SNB-B */
2531 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2532 }
2533 I915_WRITE(reg, temp);
2534
2535 reg = FDI_RX_CTL(pipe);
2536 temp = I915_READ(reg);
2537 if (HAS_PCH_CPT(dev)) {
2538 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2539 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2540 } else {
2541 temp &= ~FDI_LINK_TRAIN_NONE;
2542 temp |= FDI_LINK_TRAIN_PATTERN_2;
2543 }
2544 I915_WRITE(reg, temp);
2545
2546 POSTING_READ(reg);
2547 udelay(150);
2548
2549 for (i = 0; i < 4; i++) {
2550 reg = FDI_TX_CTL(pipe);
2551 temp = I915_READ(reg);
2552 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2553 temp |= snb_b_fdi_train_param[i];
2554 I915_WRITE(reg, temp);
2555
2556 POSTING_READ(reg);
2557 udelay(500);
2558
2559 reg = FDI_RX_IIR(pipe);
2560 temp = I915_READ(reg);
2561 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2562
2563 if (temp & FDI_RX_SYMBOL_LOCK) {
2564 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2565 DRM_DEBUG_KMS("FDI train 2 done.\n");
2566 break;
2567 }
2568 }
2569 if (i == 4)
2570 DRM_ERROR("FDI train 2 fail!\n");
2571
2572 DRM_DEBUG_KMS("FDI train done.\n");
2573 }
2574
2575 /* Manual link training for Ivy Bridge A0 parts */
2576 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2577 {
2578 struct drm_device *dev = crtc->dev;
2579 struct drm_i915_private *dev_priv = dev->dev_private;
2580 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2581 int pipe = intel_crtc->pipe;
2582 u32 reg, temp, i;
2583
2584 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2585 for train result */
2586 reg = FDI_RX_IMR(pipe);
2587 temp = I915_READ(reg);
2588 temp &= ~FDI_RX_SYMBOL_LOCK;
2589 temp &= ~FDI_RX_BIT_LOCK;
2590 I915_WRITE(reg, temp);
2591
2592 POSTING_READ(reg);
2593 udelay(150);
2594
2595 /* enable CPU FDI TX and PCH FDI RX */
2596 reg = FDI_TX_CTL(pipe);
2597 temp = I915_READ(reg);
2598 temp &= ~(7 << 19);
2599 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2600 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2601 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2602 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2603 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2604 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2605
2606 reg = FDI_RX_CTL(pipe);
2607 temp = I915_READ(reg);
2608 temp &= ~FDI_LINK_TRAIN_AUTO;
2609 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2610 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2611 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2612
2613 POSTING_READ(reg);
2614 udelay(150);
2615
2616 if (HAS_PCH_CPT(dev))
2617 cpt_phase_pointer_enable(dev, pipe);
2618
2619 for (i = 0; i < 4; i++) {
2620 reg = FDI_TX_CTL(pipe);
2621 temp = I915_READ(reg);
2622 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2623 temp |= snb_b_fdi_train_param[i];
2624 I915_WRITE(reg, temp);
2625
2626 POSTING_READ(reg);
2627 udelay(500);
2628
2629 reg = FDI_RX_IIR(pipe);
2630 temp = I915_READ(reg);
2631 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2632
2633 if (temp & FDI_RX_BIT_LOCK ||
2634 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2635 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2636 DRM_DEBUG_KMS("FDI train 1 done.\n");
2637 break;
2638 }
2639 }
2640 if (i == 4)
2641 DRM_ERROR("FDI train 1 fail!\n");
2642
2643 /* Train 2 */
2644 reg = FDI_TX_CTL(pipe);
2645 temp = I915_READ(reg);
2646 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2647 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2648 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2649 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2650 I915_WRITE(reg, temp);
2651
2652 reg = FDI_RX_CTL(pipe);
2653 temp = I915_READ(reg);
2654 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2655 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2656 I915_WRITE(reg, temp);
2657
2658 POSTING_READ(reg);
2659 udelay(150);
2660
2661 for (i = 0; i < 4; i++) {
2662 reg = FDI_TX_CTL(pipe);
2663 temp = I915_READ(reg);
2664 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2665 temp |= snb_b_fdi_train_param[i];
2666 I915_WRITE(reg, temp);
2667
2668 POSTING_READ(reg);
2669 udelay(500);
2670
2671 reg = FDI_RX_IIR(pipe);
2672 temp = I915_READ(reg);
2673 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2674
2675 if (temp & FDI_RX_SYMBOL_LOCK) {
2676 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2677 DRM_DEBUG_KMS("FDI train 2 done.\n");
2678 break;
2679 }
2680 }
2681 if (i == 4)
2682 DRM_ERROR("FDI train 2 fail!\n");
2683
2684 DRM_DEBUG_KMS("FDI train done.\n");
2685 }
2686
2687 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2688 {
2689 struct drm_device *dev = crtc->dev;
2690 struct drm_i915_private *dev_priv = dev->dev_private;
2691 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2692 int pipe = intel_crtc->pipe;
2693 u32 reg, temp;
2694
2695 /* Write the TU size bits so error detection works */
2696 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2697 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2698
2699 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2700 reg = FDI_RX_CTL(pipe);
2701 temp = I915_READ(reg);
2702 temp &= ~((0x7 << 19) | (0x7 << 16));
2703 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2704 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2705 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2706
2707 POSTING_READ(reg);
2708 udelay(200);
2709
2710 /* Switch from Rawclk to PCDclk */
2711 temp = I915_READ(reg);
2712 I915_WRITE(reg, temp | FDI_PCDCLK);
2713
2714 POSTING_READ(reg);
2715 udelay(200);
2716
2717 /* Enable CPU FDI TX PLL, always on for Ironlake */
2718 reg = FDI_TX_CTL(pipe);
2719 temp = I915_READ(reg);
2720 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2721 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2722
2723 POSTING_READ(reg);
2724 udelay(100);
2725 }
2726 }
2727
2728 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2729 {
2730 struct drm_i915_private *dev_priv = dev->dev_private;
2731 u32 flags = I915_READ(SOUTH_CHICKEN1);
2732
2733 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2734 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2735 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2736 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2737 POSTING_READ(SOUTH_CHICKEN1);
2738 }
2739 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2740 {
2741 struct drm_device *dev = crtc->dev;
2742 struct drm_i915_private *dev_priv = dev->dev_private;
2743 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2744 int pipe = intel_crtc->pipe;
2745 u32 reg, temp;
2746
2747 /* disable CPU FDI tx and PCH FDI rx */
2748 reg = FDI_TX_CTL(pipe);
2749 temp = I915_READ(reg);
2750 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2751 POSTING_READ(reg);
2752
2753 reg = FDI_RX_CTL(pipe);
2754 temp = I915_READ(reg);
2755 temp &= ~(0x7 << 16);
2756 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2757 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2758
2759 POSTING_READ(reg);
2760 udelay(100);
2761
2762 /* Ironlake workaround, disable clock pointer after downing FDI */
2763 if (HAS_PCH_IBX(dev)) {
2764 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2765 I915_WRITE(FDI_RX_CHICKEN(pipe),
2766 I915_READ(FDI_RX_CHICKEN(pipe) &
2767 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2768 } else if (HAS_PCH_CPT(dev)) {
2769 cpt_phase_pointer_disable(dev, pipe);
2770 }
2771
2772 /* still set train pattern 1 */
2773 reg = FDI_TX_CTL(pipe);
2774 temp = I915_READ(reg);
2775 temp &= ~FDI_LINK_TRAIN_NONE;
2776 temp |= FDI_LINK_TRAIN_PATTERN_1;
2777 I915_WRITE(reg, temp);
2778
2779 reg = FDI_RX_CTL(pipe);
2780 temp = I915_READ(reg);
2781 if (HAS_PCH_CPT(dev)) {
2782 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2783 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2784 } else {
2785 temp &= ~FDI_LINK_TRAIN_NONE;
2786 temp |= FDI_LINK_TRAIN_PATTERN_1;
2787 }
2788 /* BPC in FDI rx is consistent with that in PIPECONF */
2789 temp &= ~(0x07 << 16);
2790 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2791 I915_WRITE(reg, temp);
2792
2793 POSTING_READ(reg);
2794 udelay(100);
2795 }
2796
2797 /*
2798 * When we disable a pipe, we need to clear any pending scanline wait events
2799 * to avoid hanging the ring, which we assume we are waiting on.
2800 */
2801 static void intel_clear_scanline_wait(struct drm_device *dev)
2802 {
2803 struct drm_i915_private *dev_priv = dev->dev_private;
2804 struct intel_ring_buffer *ring;
2805 u32 tmp;
2806
2807 if (IS_GEN2(dev))
2808 /* Can't break the hang on i8xx */
2809 return;
2810
2811 ring = LP_RING(dev_priv);
2812 tmp = I915_READ_CTL(ring);
2813 if (tmp & RING_WAIT)
2814 I915_WRITE_CTL(ring, tmp);
2815 }
2816
2817 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2818 {
2819 struct drm_i915_gem_object *obj;
2820 struct drm_i915_private *dev_priv;
2821
2822 if (crtc->fb == NULL)
2823 return;
2824
2825 obj = to_intel_framebuffer(crtc->fb)->obj;
2826 dev_priv = crtc->dev->dev_private;
2827 wait_event(dev_priv->pending_flip_queue,
2828 atomic_read(&obj->pending_flip) == 0);
2829 }
2830
2831 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2832 {
2833 struct drm_device *dev = crtc->dev;
2834 struct drm_mode_config *mode_config = &dev->mode_config;
2835 struct intel_encoder *encoder;
2836
2837 /*
2838 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2839 * must be driven by its own crtc; no sharing is possible.
2840 */
2841 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2842 if (encoder->base.crtc != crtc)
2843 continue;
2844
2845 switch (encoder->type) {
2846 case INTEL_OUTPUT_EDP:
2847 if (!intel_encoder_is_pch_edp(&encoder->base))
2848 return false;
2849 continue;
2850 }
2851 }
2852
2853 return true;
2854 }
2855
2856 /*
2857 * Enable PCH resources required for PCH ports:
2858 * - PCH PLLs
2859 * - FDI training & RX/TX
2860 * - update transcoder timings
2861 * - DP transcoding bits
2862 * - transcoder
2863 */
2864 static void ironlake_pch_enable(struct drm_crtc *crtc)
2865 {
2866 struct drm_device *dev = crtc->dev;
2867 struct drm_i915_private *dev_priv = dev->dev_private;
2868 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2869 int pipe = intel_crtc->pipe;
2870 u32 reg, temp;
2871
2872 /* For PCH output, training FDI link */
2873 dev_priv->display.fdi_link_train(crtc);
2874
2875 intel_enable_pch_pll(dev_priv, pipe);
2876
2877 if (HAS_PCH_CPT(dev)) {
2878 /* Be sure PCH DPLL SEL is set */
2879 temp = I915_READ(PCH_DPLL_SEL);
2880 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2881 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2882 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2883 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2884 I915_WRITE(PCH_DPLL_SEL, temp);
2885 }
2886
2887 /* set transcoder timing, panel must allow it */
2888 assert_panel_unlocked(dev_priv, pipe);
2889 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2890 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2891 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
2892
2893 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2894 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2895 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
2896
2897 intel_fdi_normal_train(crtc);
2898
2899 /* For PCH DP, enable TRANS_DP_CTL */
2900 if (HAS_PCH_CPT(dev) &&
2901 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2902 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2903 reg = TRANS_DP_CTL(pipe);
2904 temp = I915_READ(reg);
2905 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2906 TRANS_DP_SYNC_MASK |
2907 TRANS_DP_BPC_MASK);
2908 temp |= (TRANS_DP_OUTPUT_ENABLE |
2909 TRANS_DP_ENH_FRAMING);
2910 temp |= bpc << 9; /* same format but at 11:9 */
2911
2912 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2913 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2914 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2915 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2916
2917 switch (intel_trans_dp_port_sel(crtc)) {
2918 case PCH_DP_B:
2919 temp |= TRANS_DP_PORT_SEL_B;
2920 break;
2921 case PCH_DP_C:
2922 temp |= TRANS_DP_PORT_SEL_C;
2923 break;
2924 case PCH_DP_D:
2925 temp |= TRANS_DP_PORT_SEL_D;
2926 break;
2927 default:
2928 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2929 temp |= TRANS_DP_PORT_SEL_B;
2930 break;
2931 }
2932
2933 I915_WRITE(reg, temp);
2934 }
2935
2936 intel_enable_transcoder(dev_priv, pipe);
2937 }
2938
2939 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2940 {
2941 struct drm_device *dev = crtc->dev;
2942 struct drm_i915_private *dev_priv = dev->dev_private;
2943 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2944 int pipe = intel_crtc->pipe;
2945 int plane = intel_crtc->plane;
2946 u32 temp;
2947 bool is_pch_port;
2948
2949 if (intel_crtc->active)
2950 return;
2951
2952 intel_crtc->active = true;
2953 intel_update_watermarks(dev);
2954
2955 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2956 temp = I915_READ(PCH_LVDS);
2957 if ((temp & LVDS_PORT_EN) == 0)
2958 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2959 }
2960
2961 is_pch_port = intel_crtc_driving_pch(crtc);
2962
2963 if (is_pch_port)
2964 ironlake_fdi_pll_enable(crtc);
2965 else
2966 ironlake_fdi_disable(crtc);
2967
2968 /* Enable panel fitting for LVDS */
2969 if (dev_priv->pch_pf_size &&
2970 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2971 /* Force use of hard-coded filter coefficients
2972 * as some pre-programmed values are broken,
2973 * e.g. x201.
2974 */
2975 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2976 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2977 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
2978 }
2979
2980 /*
2981 * On ILK+ LUT must be loaded before the pipe is running but with
2982 * clocks enabled
2983 */
2984 intel_crtc_load_lut(crtc);
2985
2986 intel_enable_pipe(dev_priv, pipe, is_pch_port);
2987 intel_enable_plane(dev_priv, plane, pipe);
2988
2989 if (is_pch_port)
2990 ironlake_pch_enable(crtc);
2991
2992 mutex_lock(&dev->struct_mutex);
2993 intel_update_fbc(dev);
2994 mutex_unlock(&dev->struct_mutex);
2995
2996 intel_crtc_update_cursor(crtc, true);
2997 }
2998
2999 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3000 {
3001 struct drm_device *dev = crtc->dev;
3002 struct drm_i915_private *dev_priv = dev->dev_private;
3003 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3004 int pipe = intel_crtc->pipe;
3005 int plane = intel_crtc->plane;
3006 u32 reg, temp;
3007
3008 if (!intel_crtc->active)
3009 return;
3010
3011 intel_crtc_wait_for_pending_flips(crtc);
3012 drm_vblank_off(dev, pipe);
3013 intel_crtc_update_cursor(crtc, false);
3014
3015 intel_disable_plane(dev_priv, plane, pipe);
3016
3017 if (dev_priv->cfb_plane == plane)
3018 intel_disable_fbc(dev);
3019
3020 intel_disable_pipe(dev_priv, pipe);
3021
3022 /* Disable PF */
3023 I915_WRITE(PF_CTL(pipe), 0);
3024 I915_WRITE(PF_WIN_SZ(pipe), 0);
3025
3026 ironlake_fdi_disable(crtc);
3027
3028 /* This is a horrible layering violation; we should be doing this in
3029 * the connector/encoder ->prepare instead, but we don't always have
3030 * enough information there about the config to know whether it will
3031 * actually be necessary or just cause undesired flicker.
3032 */
3033 intel_disable_pch_ports(dev_priv, pipe);
3034
3035 intel_disable_transcoder(dev_priv, pipe);
3036
3037 if (HAS_PCH_CPT(dev)) {
3038 /* disable TRANS_DP_CTL */
3039 reg = TRANS_DP_CTL(pipe);
3040 temp = I915_READ(reg);
3041 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3042 temp |= TRANS_DP_PORT_SEL_NONE;
3043 I915_WRITE(reg, temp);
3044
3045 /* disable DPLL_SEL */
3046 temp = I915_READ(PCH_DPLL_SEL);
3047 switch (pipe) {
3048 case 0:
3049 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3050 break;
3051 case 1:
3052 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3053 break;
3054 case 2:
3055 /* FIXME: manage transcoder PLLs? */
3056 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3057 break;
3058 default:
3059 BUG(); /* wtf */
3060 }
3061 I915_WRITE(PCH_DPLL_SEL, temp);
3062 }
3063
3064 /* disable PCH DPLL */
3065 intel_disable_pch_pll(dev_priv, pipe);
3066
3067 /* Switch from PCDclk to Rawclk */
3068 reg = FDI_RX_CTL(pipe);
3069 temp = I915_READ(reg);
3070 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3071
3072 /* Disable CPU FDI TX PLL */
3073 reg = FDI_TX_CTL(pipe);
3074 temp = I915_READ(reg);
3075 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3076
3077 POSTING_READ(reg);
3078 udelay(100);
3079
3080 reg = FDI_RX_CTL(pipe);
3081 temp = I915_READ(reg);
3082 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3083
3084 /* Wait for the clocks to turn off. */
3085 POSTING_READ(reg);
3086 udelay(100);
3087
3088 intel_crtc->active = false;
3089 intel_update_watermarks(dev);
3090
3091 mutex_lock(&dev->struct_mutex);
3092 intel_update_fbc(dev);
3093 intel_clear_scanline_wait(dev);
3094 mutex_unlock(&dev->struct_mutex);
3095 }
3096
3097 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3098 {
3099 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3100 int pipe = intel_crtc->pipe;
3101 int plane = intel_crtc->plane;
3102
3103 /* XXX: When our outputs are all unaware of DPMS modes other than off
3104 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3105 */
3106 switch (mode) {
3107 case DRM_MODE_DPMS_ON:
3108 case DRM_MODE_DPMS_STANDBY:
3109 case DRM_MODE_DPMS_SUSPEND:
3110 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3111 ironlake_crtc_enable(crtc);
3112 break;
3113
3114 case DRM_MODE_DPMS_OFF:
3115 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3116 ironlake_crtc_disable(crtc);
3117 break;
3118 }
3119 }
3120
3121 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3122 {
3123 if (!enable && intel_crtc->overlay) {
3124 struct drm_device *dev = intel_crtc->base.dev;
3125 struct drm_i915_private *dev_priv = dev->dev_private;
3126
3127 mutex_lock(&dev->struct_mutex);
3128 dev_priv->mm.interruptible = false;
3129 (void) intel_overlay_switch_off(intel_crtc->overlay);
3130 dev_priv->mm.interruptible = true;
3131 mutex_unlock(&dev->struct_mutex);
3132 }
3133
3134 /* Let userspace switch the overlay on again. In most cases userspace
3135 * has to recompute where to put it anyway.
3136 */
3137 }
3138
3139 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3140 {
3141 struct drm_device *dev = crtc->dev;
3142 struct drm_i915_private *dev_priv = dev->dev_private;
3143 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3144 int pipe = intel_crtc->pipe;
3145 int plane = intel_crtc->plane;
3146
3147 if (intel_crtc->active)
3148 return;
3149
3150 intel_crtc->active = true;
3151 intel_update_watermarks(dev);
3152
3153 intel_enable_pll(dev_priv, pipe);
3154 intel_enable_pipe(dev_priv, pipe, false);
3155 intel_enable_plane(dev_priv, plane, pipe);
3156
3157 intel_crtc_load_lut(crtc);
3158 intel_update_fbc(dev);
3159
3160 /* Give the overlay scaler a chance to enable if it's on this pipe */
3161 intel_crtc_dpms_overlay(intel_crtc, true);
3162 intel_crtc_update_cursor(crtc, true);
3163 }
3164
3165 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3166 {
3167 struct drm_device *dev = crtc->dev;
3168 struct drm_i915_private *dev_priv = dev->dev_private;
3169 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3170 int pipe = intel_crtc->pipe;
3171 int plane = intel_crtc->plane;
3172
3173 if (!intel_crtc->active)
3174 return;
3175
3176 /* Give the overlay scaler a chance to disable if it's on this pipe */
3177 intel_crtc_wait_for_pending_flips(crtc);
3178 drm_vblank_off(dev, pipe);
3179 intel_crtc_dpms_overlay(intel_crtc, false);
3180 intel_crtc_update_cursor(crtc, false);
3181
3182 if (dev_priv->cfb_plane == plane)
3183 intel_disable_fbc(dev);
3184
3185 intel_disable_plane(dev_priv, plane, pipe);
3186 intel_disable_pipe(dev_priv, pipe);
3187 intel_disable_pll(dev_priv, pipe);
3188
3189 intel_crtc->active = false;
3190 intel_update_fbc(dev);
3191 intel_update_watermarks(dev);
3192 intel_clear_scanline_wait(dev);
3193 }
3194
3195 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3196 {
3197 /* XXX: When our outputs are all unaware of DPMS modes other than off
3198 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3199 */
3200 switch (mode) {
3201 case DRM_MODE_DPMS_ON:
3202 case DRM_MODE_DPMS_STANDBY:
3203 case DRM_MODE_DPMS_SUSPEND:
3204 i9xx_crtc_enable(crtc);
3205 break;
3206 case DRM_MODE_DPMS_OFF:
3207 i9xx_crtc_disable(crtc);
3208 break;
3209 }
3210 }
3211
3212 /**
3213 * Sets the power management mode of the pipe and plane.
3214 */
3215 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3216 {
3217 struct drm_device *dev = crtc->dev;
3218 struct drm_i915_private *dev_priv = dev->dev_private;
3219 struct drm_i915_master_private *master_priv;
3220 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3221 int pipe = intel_crtc->pipe;
3222 bool enabled;
3223
3224 if (intel_crtc->dpms_mode == mode)
3225 return;
3226
3227 intel_crtc->dpms_mode = mode;
3228
3229 dev_priv->display.dpms(crtc, mode);
3230
3231 if (!dev->primary->master)
3232 return;
3233
3234 master_priv = dev->primary->master->driver_priv;
3235 if (!master_priv->sarea_priv)
3236 return;
3237
3238 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3239
3240 switch (pipe) {
3241 case 0:
3242 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3243 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3244 break;
3245 case 1:
3246 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3247 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3248 break;
3249 default:
3250 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3251 break;
3252 }
3253 }
3254
3255 static void intel_crtc_disable(struct drm_crtc *crtc)
3256 {
3257 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3258 struct drm_device *dev = crtc->dev;
3259
3260 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3261
3262 if (crtc->fb) {
3263 mutex_lock(&dev->struct_mutex);
3264 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3265 mutex_unlock(&dev->struct_mutex);
3266 }
3267 }
3268
3269 /* Prepare for a mode set.
3270 *
3271 * Note we could be a lot smarter here. We need to figure out which outputs
3272 * will be enabled, which disabled (in short, how the config will changes)
3273 * and perform the minimum necessary steps to accomplish that, e.g. updating
3274 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3275 * panel fitting is in the proper state, etc.
3276 */
3277 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3278 {
3279 i9xx_crtc_disable(crtc);
3280 }
3281
3282 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3283 {
3284 i9xx_crtc_enable(crtc);
3285 }
3286
3287 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3288 {
3289 ironlake_crtc_disable(crtc);
3290 }
3291
3292 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3293 {
3294 ironlake_crtc_enable(crtc);
3295 }
3296
3297 void intel_encoder_prepare(struct drm_encoder *encoder)
3298 {
3299 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3300 /* lvds has its own version of prepare see intel_lvds_prepare */
3301 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3302 }
3303
3304 void intel_encoder_commit(struct drm_encoder *encoder)
3305 {
3306 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3307 /* lvds has its own version of commit see intel_lvds_commit */
3308 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3309 }
3310
3311 void intel_encoder_destroy(struct drm_encoder *encoder)
3312 {
3313 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3314
3315 drm_encoder_cleanup(encoder);
3316 kfree(intel_encoder);
3317 }
3318
3319 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3320 struct drm_display_mode *mode,
3321 struct drm_display_mode *adjusted_mode)
3322 {
3323 struct drm_device *dev = crtc->dev;
3324
3325 if (HAS_PCH_SPLIT(dev)) {
3326 /* FDI link clock is fixed at 2.7G */
3327 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3328 return false;
3329 }
3330
3331 /* XXX some encoders set the crtcinfo, others don't.
3332 * Obviously we need some form of conflict resolution here...
3333 */
3334 if (adjusted_mode->crtc_htotal == 0)
3335 drm_mode_set_crtcinfo(adjusted_mode, 0);
3336
3337 return true;
3338 }
3339
3340 static int i945_get_display_clock_speed(struct drm_device *dev)
3341 {
3342 return 400000;
3343 }
3344
3345 static int i915_get_display_clock_speed(struct drm_device *dev)
3346 {
3347 return 333000;
3348 }
3349
3350 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3351 {
3352 return 200000;
3353 }
3354
3355 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3356 {
3357 u16 gcfgc = 0;
3358
3359 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3360
3361 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3362 return 133000;
3363 else {
3364 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3365 case GC_DISPLAY_CLOCK_333_MHZ:
3366 return 333000;
3367 default:
3368 case GC_DISPLAY_CLOCK_190_200_MHZ:
3369 return 190000;
3370 }
3371 }
3372 }
3373
3374 static int i865_get_display_clock_speed(struct drm_device *dev)
3375 {
3376 return 266000;
3377 }
3378
3379 static int i855_get_display_clock_speed(struct drm_device *dev)
3380 {
3381 u16 hpllcc = 0;
3382 /* Assume that the hardware is in the high speed state. This
3383 * should be the default.
3384 */
3385 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3386 case GC_CLOCK_133_200:
3387 case GC_CLOCK_100_200:
3388 return 200000;
3389 case GC_CLOCK_166_250:
3390 return 250000;
3391 case GC_CLOCK_100_133:
3392 return 133000;
3393 }
3394
3395 /* Shouldn't happen */
3396 return 0;
3397 }
3398
3399 static int i830_get_display_clock_speed(struct drm_device *dev)
3400 {
3401 return 133000;
3402 }
3403
3404 struct fdi_m_n {
3405 u32 tu;
3406 u32 gmch_m;
3407 u32 gmch_n;
3408 u32 link_m;
3409 u32 link_n;
3410 };
3411
3412 static void
3413 fdi_reduce_ratio(u32 *num, u32 *den)
3414 {
3415 while (*num > 0xffffff || *den > 0xffffff) {
3416 *num >>= 1;
3417 *den >>= 1;
3418 }
3419 }
3420
3421 static void
3422 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3423 int link_clock, struct fdi_m_n *m_n)
3424 {
3425 m_n->tu = 64; /* default size */
3426
3427 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3428 m_n->gmch_m = bits_per_pixel * pixel_clock;
3429 m_n->gmch_n = link_clock * nlanes * 8;
3430 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3431
3432 m_n->link_m = pixel_clock;
3433 m_n->link_n = link_clock;
3434 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3435 }
3436
3437
3438 struct intel_watermark_params {
3439 unsigned long fifo_size;
3440 unsigned long max_wm;
3441 unsigned long default_wm;
3442 unsigned long guard_size;
3443 unsigned long cacheline_size;
3444 };
3445
3446 /* Pineview has different values for various configs */
3447 static const struct intel_watermark_params pineview_display_wm = {
3448 PINEVIEW_DISPLAY_FIFO,
3449 PINEVIEW_MAX_WM,
3450 PINEVIEW_DFT_WM,
3451 PINEVIEW_GUARD_WM,
3452 PINEVIEW_FIFO_LINE_SIZE
3453 };
3454 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3455 PINEVIEW_DISPLAY_FIFO,
3456 PINEVIEW_MAX_WM,
3457 PINEVIEW_DFT_HPLLOFF_WM,
3458 PINEVIEW_GUARD_WM,
3459 PINEVIEW_FIFO_LINE_SIZE
3460 };
3461 static const struct intel_watermark_params pineview_cursor_wm = {
3462 PINEVIEW_CURSOR_FIFO,
3463 PINEVIEW_CURSOR_MAX_WM,
3464 PINEVIEW_CURSOR_DFT_WM,
3465 PINEVIEW_CURSOR_GUARD_WM,
3466 PINEVIEW_FIFO_LINE_SIZE,
3467 };
3468 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3469 PINEVIEW_CURSOR_FIFO,
3470 PINEVIEW_CURSOR_MAX_WM,
3471 PINEVIEW_CURSOR_DFT_WM,
3472 PINEVIEW_CURSOR_GUARD_WM,
3473 PINEVIEW_FIFO_LINE_SIZE
3474 };
3475 static const struct intel_watermark_params g4x_wm_info = {
3476 G4X_FIFO_SIZE,
3477 G4X_MAX_WM,
3478 G4X_MAX_WM,
3479 2,
3480 G4X_FIFO_LINE_SIZE,
3481 };
3482 static const struct intel_watermark_params g4x_cursor_wm_info = {
3483 I965_CURSOR_FIFO,
3484 I965_CURSOR_MAX_WM,
3485 I965_CURSOR_DFT_WM,
3486 2,
3487 G4X_FIFO_LINE_SIZE,
3488 };
3489 static const struct intel_watermark_params i965_cursor_wm_info = {
3490 I965_CURSOR_FIFO,
3491 I965_CURSOR_MAX_WM,
3492 I965_CURSOR_DFT_WM,
3493 2,
3494 I915_FIFO_LINE_SIZE,
3495 };
3496 static const struct intel_watermark_params i945_wm_info = {
3497 I945_FIFO_SIZE,
3498 I915_MAX_WM,
3499 1,
3500 2,
3501 I915_FIFO_LINE_SIZE
3502 };
3503 static const struct intel_watermark_params i915_wm_info = {
3504 I915_FIFO_SIZE,
3505 I915_MAX_WM,
3506 1,
3507 2,
3508 I915_FIFO_LINE_SIZE
3509 };
3510 static const struct intel_watermark_params i855_wm_info = {
3511 I855GM_FIFO_SIZE,
3512 I915_MAX_WM,
3513 1,
3514 2,
3515 I830_FIFO_LINE_SIZE
3516 };
3517 static const struct intel_watermark_params i830_wm_info = {
3518 I830_FIFO_SIZE,
3519 I915_MAX_WM,
3520 1,
3521 2,
3522 I830_FIFO_LINE_SIZE
3523 };
3524
3525 static const struct intel_watermark_params ironlake_display_wm_info = {
3526 ILK_DISPLAY_FIFO,
3527 ILK_DISPLAY_MAXWM,
3528 ILK_DISPLAY_DFTWM,
3529 2,
3530 ILK_FIFO_LINE_SIZE
3531 };
3532 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3533 ILK_CURSOR_FIFO,
3534 ILK_CURSOR_MAXWM,
3535 ILK_CURSOR_DFTWM,
3536 2,
3537 ILK_FIFO_LINE_SIZE
3538 };
3539 static const struct intel_watermark_params ironlake_display_srwm_info = {
3540 ILK_DISPLAY_SR_FIFO,
3541 ILK_DISPLAY_MAX_SRWM,
3542 ILK_DISPLAY_DFT_SRWM,
3543 2,
3544 ILK_FIFO_LINE_SIZE
3545 };
3546 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3547 ILK_CURSOR_SR_FIFO,
3548 ILK_CURSOR_MAX_SRWM,
3549 ILK_CURSOR_DFT_SRWM,
3550 2,
3551 ILK_FIFO_LINE_SIZE
3552 };
3553
3554 static const struct intel_watermark_params sandybridge_display_wm_info = {
3555 SNB_DISPLAY_FIFO,
3556 SNB_DISPLAY_MAXWM,
3557 SNB_DISPLAY_DFTWM,
3558 2,
3559 SNB_FIFO_LINE_SIZE
3560 };
3561 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3562 SNB_CURSOR_FIFO,
3563 SNB_CURSOR_MAXWM,
3564 SNB_CURSOR_DFTWM,
3565 2,
3566 SNB_FIFO_LINE_SIZE
3567 };
3568 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3569 SNB_DISPLAY_SR_FIFO,
3570 SNB_DISPLAY_MAX_SRWM,
3571 SNB_DISPLAY_DFT_SRWM,
3572 2,
3573 SNB_FIFO_LINE_SIZE
3574 };
3575 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3576 SNB_CURSOR_SR_FIFO,
3577 SNB_CURSOR_MAX_SRWM,
3578 SNB_CURSOR_DFT_SRWM,
3579 2,
3580 SNB_FIFO_LINE_SIZE
3581 };
3582
3583
3584 /**
3585 * intel_calculate_wm - calculate watermark level
3586 * @clock_in_khz: pixel clock
3587 * @wm: chip FIFO params
3588 * @pixel_size: display pixel size
3589 * @latency_ns: memory latency for the platform
3590 *
3591 * Calculate the watermark level (the level at which the display plane will
3592 * start fetching from memory again). Each chip has a different display
3593 * FIFO size and allocation, so the caller needs to figure that out and pass
3594 * in the correct intel_watermark_params structure.
3595 *
3596 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3597 * on the pixel size. When it reaches the watermark level, it'll start
3598 * fetching FIFO line sized based chunks from memory until the FIFO fills
3599 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3600 * will occur, and a display engine hang could result.
3601 */
3602 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3603 const struct intel_watermark_params *wm,
3604 int fifo_size,
3605 int pixel_size,
3606 unsigned long latency_ns)
3607 {
3608 long entries_required, wm_size;
3609
3610 /*
3611 * Note: we need to make sure we don't overflow for various clock &
3612 * latency values.
3613 * clocks go from a few thousand to several hundred thousand.
3614 * latency is usually a few thousand
3615 */
3616 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3617 1000;
3618 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3619
3620 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3621
3622 wm_size = fifo_size - (entries_required + wm->guard_size);
3623
3624 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3625
3626 /* Don't promote wm_size to unsigned... */
3627 if (wm_size > (long)wm->max_wm)
3628 wm_size = wm->max_wm;
3629 if (wm_size <= 0)
3630 wm_size = wm->default_wm;
3631 return wm_size;
3632 }
3633
3634 struct cxsr_latency {
3635 int is_desktop;
3636 int is_ddr3;
3637 unsigned long fsb_freq;
3638 unsigned long mem_freq;
3639 unsigned long display_sr;
3640 unsigned long display_hpll_disable;
3641 unsigned long cursor_sr;
3642 unsigned long cursor_hpll_disable;
3643 };
3644
3645 static const struct cxsr_latency cxsr_latency_table[] = {
3646 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3647 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3648 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3649 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3650 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3651
3652 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3653 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3654 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3655 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3656 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3657
3658 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3659 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3660 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3661 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3662 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3663
3664 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3665 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3666 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3667 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3668 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3669
3670 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3671 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3672 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3673 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3674 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3675
3676 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3677 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3678 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3679 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3680 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
3681 };
3682
3683 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3684 int is_ddr3,
3685 int fsb,
3686 int mem)
3687 {
3688 const struct cxsr_latency *latency;
3689 int i;
3690
3691 if (fsb == 0 || mem == 0)
3692 return NULL;
3693
3694 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3695 latency = &cxsr_latency_table[i];
3696 if (is_desktop == latency->is_desktop &&
3697 is_ddr3 == latency->is_ddr3 &&
3698 fsb == latency->fsb_freq && mem == latency->mem_freq)
3699 return latency;
3700 }
3701
3702 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3703
3704 return NULL;
3705 }
3706
3707 static void pineview_disable_cxsr(struct drm_device *dev)
3708 {
3709 struct drm_i915_private *dev_priv = dev->dev_private;
3710
3711 /* deactivate cxsr */
3712 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3713 }
3714
3715 /*
3716 * Latency for FIFO fetches is dependent on several factors:
3717 * - memory configuration (speed, channels)
3718 * - chipset
3719 * - current MCH state
3720 * It can be fairly high in some situations, so here we assume a fairly
3721 * pessimal value. It's a tradeoff between extra memory fetches (if we
3722 * set this value too high, the FIFO will fetch frequently to stay full)
3723 * and power consumption (set it too low to save power and we might see
3724 * FIFO underruns and display "flicker").
3725 *
3726 * A value of 5us seems to be a good balance; safe for very low end
3727 * platforms but not overly aggressive on lower latency configs.
3728 */
3729 static const int latency_ns = 5000;
3730
3731 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3732 {
3733 struct drm_i915_private *dev_priv = dev->dev_private;
3734 uint32_t dsparb = I915_READ(DSPARB);
3735 int size;
3736
3737 size = dsparb & 0x7f;
3738 if (plane)
3739 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3740
3741 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3742 plane ? "B" : "A", size);
3743
3744 return size;
3745 }
3746
3747 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3748 {
3749 struct drm_i915_private *dev_priv = dev->dev_private;
3750 uint32_t dsparb = I915_READ(DSPARB);
3751 int size;
3752
3753 size = dsparb & 0x1ff;
3754 if (plane)
3755 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3756 size >>= 1; /* Convert to cachelines */
3757
3758 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3759 plane ? "B" : "A", size);
3760
3761 return size;
3762 }
3763
3764 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3765 {
3766 struct drm_i915_private *dev_priv = dev->dev_private;
3767 uint32_t dsparb = I915_READ(DSPARB);
3768 int size;
3769
3770 size = dsparb & 0x7f;
3771 size >>= 2; /* Convert to cachelines */
3772
3773 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3774 plane ? "B" : "A",
3775 size);
3776
3777 return size;
3778 }
3779
3780 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3781 {
3782 struct drm_i915_private *dev_priv = dev->dev_private;
3783 uint32_t dsparb = I915_READ(DSPARB);
3784 int size;
3785
3786 size = dsparb & 0x7f;
3787 size >>= 1; /* Convert to cachelines */
3788
3789 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3790 plane ? "B" : "A", size);
3791
3792 return size;
3793 }
3794
3795 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3796 {
3797 struct drm_crtc *crtc, *enabled = NULL;
3798
3799 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3800 if (crtc->enabled && crtc->fb) {
3801 if (enabled)
3802 return NULL;
3803 enabled = crtc;
3804 }
3805 }
3806
3807 return enabled;
3808 }
3809
3810 static void pineview_update_wm(struct drm_device *dev)
3811 {
3812 struct drm_i915_private *dev_priv = dev->dev_private;
3813 struct drm_crtc *crtc;
3814 const struct cxsr_latency *latency;
3815 u32 reg;
3816 unsigned long wm;
3817
3818 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3819 dev_priv->fsb_freq, dev_priv->mem_freq);
3820 if (!latency) {
3821 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3822 pineview_disable_cxsr(dev);
3823 return;
3824 }
3825
3826 crtc = single_enabled_crtc(dev);
3827 if (crtc) {
3828 int clock = crtc->mode.clock;
3829 int pixel_size = crtc->fb->bits_per_pixel / 8;
3830
3831 /* Display SR */
3832 wm = intel_calculate_wm(clock, &pineview_display_wm,
3833 pineview_display_wm.fifo_size,
3834 pixel_size, latency->display_sr);
3835 reg = I915_READ(DSPFW1);
3836 reg &= ~DSPFW_SR_MASK;
3837 reg |= wm << DSPFW_SR_SHIFT;
3838 I915_WRITE(DSPFW1, reg);
3839 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3840
3841 /* cursor SR */
3842 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3843 pineview_display_wm.fifo_size,
3844 pixel_size, latency->cursor_sr);
3845 reg = I915_READ(DSPFW3);
3846 reg &= ~DSPFW_CURSOR_SR_MASK;
3847 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3848 I915_WRITE(DSPFW3, reg);
3849
3850 /* Display HPLL off SR */
3851 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3852 pineview_display_hplloff_wm.fifo_size,
3853 pixel_size, latency->display_hpll_disable);
3854 reg = I915_READ(DSPFW3);
3855 reg &= ~DSPFW_HPLL_SR_MASK;
3856 reg |= wm & DSPFW_HPLL_SR_MASK;
3857 I915_WRITE(DSPFW3, reg);
3858
3859 /* cursor HPLL off SR */
3860 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3861 pineview_display_hplloff_wm.fifo_size,
3862 pixel_size, latency->cursor_hpll_disable);
3863 reg = I915_READ(DSPFW3);
3864 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3865 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3866 I915_WRITE(DSPFW3, reg);
3867 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3868
3869 /* activate cxsr */
3870 I915_WRITE(DSPFW3,
3871 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3872 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3873 } else {
3874 pineview_disable_cxsr(dev);
3875 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3876 }
3877 }
3878
3879 static bool g4x_compute_wm0(struct drm_device *dev,
3880 int plane,
3881 const struct intel_watermark_params *display,
3882 int display_latency_ns,
3883 const struct intel_watermark_params *cursor,
3884 int cursor_latency_ns,
3885 int *plane_wm,
3886 int *cursor_wm)
3887 {
3888 struct drm_crtc *crtc;
3889 int htotal, hdisplay, clock, pixel_size;
3890 int line_time_us, line_count;
3891 int entries, tlb_miss;
3892
3893 crtc = intel_get_crtc_for_plane(dev, plane);
3894 if (crtc->fb == NULL || !crtc->enabled) {
3895 *cursor_wm = cursor->guard_size;
3896 *plane_wm = display->guard_size;
3897 return false;
3898 }
3899
3900 htotal = crtc->mode.htotal;
3901 hdisplay = crtc->mode.hdisplay;
3902 clock = crtc->mode.clock;
3903 pixel_size = crtc->fb->bits_per_pixel / 8;
3904
3905 /* Use the small buffer method to calculate plane watermark */
3906 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3907 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3908 if (tlb_miss > 0)
3909 entries += tlb_miss;
3910 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3911 *plane_wm = entries + display->guard_size;
3912 if (*plane_wm > (int)display->max_wm)
3913 *plane_wm = display->max_wm;
3914
3915 /* Use the large buffer method to calculate cursor watermark */
3916 line_time_us = ((htotal * 1000) / clock);
3917 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3918 entries = line_count * 64 * pixel_size;
3919 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3920 if (tlb_miss > 0)
3921 entries += tlb_miss;
3922 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3923 *cursor_wm = entries + cursor->guard_size;
3924 if (*cursor_wm > (int)cursor->max_wm)
3925 *cursor_wm = (int)cursor->max_wm;
3926
3927 return true;
3928 }
3929
3930 /*
3931 * Check the wm result.
3932 *
3933 * If any calculated watermark values is larger than the maximum value that
3934 * can be programmed into the associated watermark register, that watermark
3935 * must be disabled.
3936 */
3937 static bool g4x_check_srwm(struct drm_device *dev,
3938 int display_wm, int cursor_wm,
3939 const struct intel_watermark_params *display,
3940 const struct intel_watermark_params *cursor)
3941 {
3942 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
3943 display_wm, cursor_wm);
3944
3945 if (display_wm > display->max_wm) {
3946 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
3947 display_wm, display->max_wm);
3948 return false;
3949 }
3950
3951 if (cursor_wm > cursor->max_wm) {
3952 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
3953 cursor_wm, cursor->max_wm);
3954 return false;
3955 }
3956
3957 if (!(display_wm || cursor_wm)) {
3958 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
3959 return false;
3960 }
3961
3962 return true;
3963 }
3964
3965 static bool g4x_compute_srwm(struct drm_device *dev,
3966 int plane,
3967 int latency_ns,
3968 const struct intel_watermark_params *display,
3969 const struct intel_watermark_params *cursor,
3970 int *display_wm, int *cursor_wm)
3971 {
3972 struct drm_crtc *crtc;
3973 int hdisplay, htotal, pixel_size, clock;
3974 unsigned long line_time_us;
3975 int line_count, line_size;
3976 int small, large;
3977 int entries;
3978
3979 if (!latency_ns) {
3980 *display_wm = *cursor_wm = 0;
3981 return false;
3982 }
3983
3984 crtc = intel_get_crtc_for_plane(dev, plane);
3985 hdisplay = crtc->mode.hdisplay;
3986 htotal = crtc->mode.htotal;
3987 clock = crtc->mode.clock;
3988 pixel_size = crtc->fb->bits_per_pixel / 8;
3989
3990 line_time_us = (htotal * 1000) / clock;
3991 line_count = (latency_ns / line_time_us + 1000) / 1000;
3992 line_size = hdisplay * pixel_size;
3993
3994 /* Use the minimum of the small and large buffer method for primary */
3995 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3996 large = line_count * line_size;
3997
3998 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3999 *display_wm = entries + display->guard_size;
4000
4001 /* calculate the self-refresh watermark for display cursor */
4002 entries = line_count * pixel_size * 64;
4003 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4004 *cursor_wm = entries + cursor->guard_size;
4005
4006 return g4x_check_srwm(dev,
4007 *display_wm, *cursor_wm,
4008 display, cursor);
4009 }
4010
4011 #define single_plane_enabled(mask) is_power_of_2(mask)
4012
4013 static void g4x_update_wm(struct drm_device *dev)
4014 {
4015 static const int sr_latency_ns = 12000;
4016 struct drm_i915_private *dev_priv = dev->dev_private;
4017 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
4018 int plane_sr, cursor_sr;
4019 unsigned int enabled = 0;
4020
4021 if (g4x_compute_wm0(dev, 0,
4022 &g4x_wm_info, latency_ns,
4023 &g4x_cursor_wm_info, latency_ns,
4024 &planea_wm, &cursora_wm))
4025 enabled |= 1;
4026
4027 if (g4x_compute_wm0(dev, 1,
4028 &g4x_wm_info, latency_ns,
4029 &g4x_cursor_wm_info, latency_ns,
4030 &planeb_wm, &cursorb_wm))
4031 enabled |= 2;
4032
4033 plane_sr = cursor_sr = 0;
4034 if (single_plane_enabled(enabled) &&
4035 g4x_compute_srwm(dev, ffs(enabled) - 1,
4036 sr_latency_ns,
4037 &g4x_wm_info,
4038 &g4x_cursor_wm_info,
4039 &plane_sr, &cursor_sr))
4040 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4041 else
4042 I915_WRITE(FW_BLC_SELF,
4043 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
4044
4045 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4046 planea_wm, cursora_wm,
4047 planeb_wm, cursorb_wm,
4048 plane_sr, cursor_sr);
4049
4050 I915_WRITE(DSPFW1,
4051 (plane_sr << DSPFW_SR_SHIFT) |
4052 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
4053 (planeb_wm << DSPFW_PLANEB_SHIFT) |
4054 planea_wm);
4055 I915_WRITE(DSPFW2,
4056 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
4057 (cursora_wm << DSPFW_CURSORA_SHIFT));
4058 /* HPLL off in SR has some issues on G4x... disable it */
4059 I915_WRITE(DSPFW3,
4060 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
4061 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4062 }
4063
4064 static void i965_update_wm(struct drm_device *dev)
4065 {
4066 struct drm_i915_private *dev_priv = dev->dev_private;
4067 struct drm_crtc *crtc;
4068 int srwm = 1;
4069 int cursor_sr = 16;
4070
4071 /* Calc sr entries for one plane configs */
4072 crtc = single_enabled_crtc(dev);
4073 if (crtc) {
4074 /* self-refresh has much higher latency */
4075 static const int sr_latency_ns = 12000;
4076 int clock = crtc->mode.clock;
4077 int htotal = crtc->mode.htotal;
4078 int hdisplay = crtc->mode.hdisplay;
4079 int pixel_size = crtc->fb->bits_per_pixel / 8;
4080 unsigned long line_time_us;
4081 int entries;
4082
4083 line_time_us = ((htotal * 1000) / clock);
4084
4085 /* Use ns/us then divide to preserve precision */
4086 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4087 pixel_size * hdisplay;
4088 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
4089 srwm = I965_FIFO_SIZE - entries;
4090 if (srwm < 0)
4091 srwm = 1;
4092 srwm &= 0x1ff;
4093 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4094 entries, srwm);
4095
4096 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4097 pixel_size * 64;
4098 entries = DIV_ROUND_UP(entries,
4099 i965_cursor_wm_info.cacheline_size);
4100 cursor_sr = i965_cursor_wm_info.fifo_size -
4101 (entries + i965_cursor_wm_info.guard_size);
4102
4103 if (cursor_sr > i965_cursor_wm_info.max_wm)
4104 cursor_sr = i965_cursor_wm_info.max_wm;
4105
4106 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4107 "cursor %d\n", srwm, cursor_sr);
4108
4109 if (IS_CRESTLINE(dev))
4110 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4111 } else {
4112 /* Turn off self refresh if both pipes are enabled */
4113 if (IS_CRESTLINE(dev))
4114 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4115 & ~FW_BLC_SELF_EN);
4116 }
4117
4118 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4119 srwm);
4120
4121 /* 965 has limitations... */
4122 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4123 (8 << 16) | (8 << 8) | (8 << 0));
4124 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4125 /* update cursor SR watermark */
4126 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4127 }
4128
4129 static void i9xx_update_wm(struct drm_device *dev)
4130 {
4131 struct drm_i915_private *dev_priv = dev->dev_private;
4132 const struct intel_watermark_params *wm_info;
4133 uint32_t fwater_lo;
4134 uint32_t fwater_hi;
4135 int cwm, srwm = 1;
4136 int fifo_size;
4137 int planea_wm, planeb_wm;
4138 struct drm_crtc *crtc, *enabled = NULL;
4139
4140 if (IS_I945GM(dev))
4141 wm_info = &i945_wm_info;
4142 else if (!IS_GEN2(dev))
4143 wm_info = &i915_wm_info;
4144 else
4145 wm_info = &i855_wm_info;
4146
4147 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4148 crtc = intel_get_crtc_for_plane(dev, 0);
4149 if (crtc->enabled && crtc->fb) {
4150 planea_wm = intel_calculate_wm(crtc->mode.clock,
4151 wm_info, fifo_size,
4152 crtc->fb->bits_per_pixel / 8,
4153 latency_ns);
4154 enabled = crtc;
4155 } else
4156 planea_wm = fifo_size - wm_info->guard_size;
4157
4158 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4159 crtc = intel_get_crtc_for_plane(dev, 1);
4160 if (crtc->enabled && crtc->fb) {
4161 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4162 wm_info, fifo_size,
4163 crtc->fb->bits_per_pixel / 8,
4164 latency_ns);
4165 if (enabled == NULL)
4166 enabled = crtc;
4167 else
4168 enabled = NULL;
4169 } else
4170 planeb_wm = fifo_size - wm_info->guard_size;
4171
4172 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
4173
4174 /*
4175 * Overlay gets an aggressive default since video jitter is bad.
4176 */
4177 cwm = 2;
4178
4179 /* Play safe and disable self-refresh before adjusting watermarks. */
4180 if (IS_I945G(dev) || IS_I945GM(dev))
4181 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4182 else if (IS_I915GM(dev))
4183 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4184
4185 /* Calc sr entries for one plane configs */
4186 if (HAS_FW_BLC(dev) && enabled) {
4187 /* self-refresh has much higher latency */
4188 static const int sr_latency_ns = 6000;
4189 int clock = enabled->mode.clock;
4190 int htotal = enabled->mode.htotal;
4191 int hdisplay = enabled->mode.hdisplay;
4192 int pixel_size = enabled->fb->bits_per_pixel / 8;
4193 unsigned long line_time_us;
4194 int entries;
4195
4196 line_time_us = (htotal * 1000) / clock;
4197
4198 /* Use ns/us then divide to preserve precision */
4199 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4200 pixel_size * hdisplay;
4201 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4202 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4203 srwm = wm_info->fifo_size - entries;
4204 if (srwm < 0)
4205 srwm = 1;
4206
4207 if (IS_I945G(dev) || IS_I945GM(dev))
4208 I915_WRITE(FW_BLC_SELF,
4209 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4210 else if (IS_I915GM(dev))
4211 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
4212 }
4213
4214 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4215 planea_wm, planeb_wm, cwm, srwm);
4216
4217 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4218 fwater_hi = (cwm & 0x1f);
4219
4220 /* Set request length to 8 cachelines per fetch */
4221 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4222 fwater_hi = fwater_hi | (1 << 8);
4223
4224 I915_WRITE(FW_BLC, fwater_lo);
4225 I915_WRITE(FW_BLC2, fwater_hi);
4226
4227 if (HAS_FW_BLC(dev)) {
4228 if (enabled) {
4229 if (IS_I945G(dev) || IS_I945GM(dev))
4230 I915_WRITE(FW_BLC_SELF,
4231 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4232 else if (IS_I915GM(dev))
4233 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4234 DRM_DEBUG_KMS("memory self refresh enabled\n");
4235 } else
4236 DRM_DEBUG_KMS("memory self refresh disabled\n");
4237 }
4238 }
4239
4240 static void i830_update_wm(struct drm_device *dev)
4241 {
4242 struct drm_i915_private *dev_priv = dev->dev_private;
4243 struct drm_crtc *crtc;
4244 uint32_t fwater_lo;
4245 int planea_wm;
4246
4247 crtc = single_enabled_crtc(dev);
4248 if (crtc == NULL)
4249 return;
4250
4251 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4252 dev_priv->display.get_fifo_size(dev, 0),
4253 crtc->fb->bits_per_pixel / 8,
4254 latency_ns);
4255 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4256 fwater_lo |= (3<<8) | planea_wm;
4257
4258 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4259
4260 I915_WRITE(FW_BLC, fwater_lo);
4261 }
4262
4263 #define ILK_LP0_PLANE_LATENCY 700
4264 #define ILK_LP0_CURSOR_LATENCY 1300
4265
4266 /*
4267 * Check the wm result.
4268 *
4269 * If any calculated watermark values is larger than the maximum value that
4270 * can be programmed into the associated watermark register, that watermark
4271 * must be disabled.
4272 */
4273 static bool ironlake_check_srwm(struct drm_device *dev, int level,
4274 int fbc_wm, int display_wm, int cursor_wm,
4275 const struct intel_watermark_params *display,
4276 const struct intel_watermark_params *cursor)
4277 {
4278 struct drm_i915_private *dev_priv = dev->dev_private;
4279
4280 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4281 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4282
4283 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4284 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4285 fbc_wm, SNB_FBC_MAX_SRWM, level);
4286
4287 /* fbc has it's own way to disable FBC WM */
4288 I915_WRITE(DISP_ARB_CTL,
4289 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4290 return false;
4291 }
4292
4293 if (display_wm > display->max_wm) {
4294 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4295 display_wm, SNB_DISPLAY_MAX_SRWM, level);
4296 return false;
4297 }
4298
4299 if (cursor_wm > cursor->max_wm) {
4300 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4301 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4302 return false;
4303 }
4304
4305 if (!(fbc_wm || display_wm || cursor_wm)) {
4306 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4307 return false;
4308 }
4309
4310 return true;
4311 }
4312
4313 /*
4314 * Compute watermark values of WM[1-3],
4315 */
4316 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4317 int latency_ns,
4318 const struct intel_watermark_params *display,
4319 const struct intel_watermark_params *cursor,
4320 int *fbc_wm, int *display_wm, int *cursor_wm)
4321 {
4322 struct drm_crtc *crtc;
4323 unsigned long line_time_us;
4324 int hdisplay, htotal, pixel_size, clock;
4325 int line_count, line_size;
4326 int small, large;
4327 int entries;
4328
4329 if (!latency_ns) {
4330 *fbc_wm = *display_wm = *cursor_wm = 0;
4331 return false;
4332 }
4333
4334 crtc = intel_get_crtc_for_plane(dev, plane);
4335 hdisplay = crtc->mode.hdisplay;
4336 htotal = crtc->mode.htotal;
4337 clock = crtc->mode.clock;
4338 pixel_size = crtc->fb->bits_per_pixel / 8;
4339
4340 line_time_us = (htotal * 1000) / clock;
4341 line_count = (latency_ns / line_time_us + 1000) / 1000;
4342 line_size = hdisplay * pixel_size;
4343
4344 /* Use the minimum of the small and large buffer method for primary */
4345 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4346 large = line_count * line_size;
4347
4348 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4349 *display_wm = entries + display->guard_size;
4350
4351 /*
4352 * Spec says:
4353 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4354 */
4355 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4356
4357 /* calculate the self-refresh watermark for display cursor */
4358 entries = line_count * pixel_size * 64;
4359 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4360 *cursor_wm = entries + cursor->guard_size;
4361
4362 return ironlake_check_srwm(dev, level,
4363 *fbc_wm, *display_wm, *cursor_wm,
4364 display, cursor);
4365 }
4366
4367 static void ironlake_update_wm(struct drm_device *dev)
4368 {
4369 struct drm_i915_private *dev_priv = dev->dev_private;
4370 int fbc_wm, plane_wm, cursor_wm;
4371 unsigned int enabled;
4372
4373 enabled = 0;
4374 if (g4x_compute_wm0(dev, 0,
4375 &ironlake_display_wm_info,
4376 ILK_LP0_PLANE_LATENCY,
4377 &ironlake_cursor_wm_info,
4378 ILK_LP0_CURSOR_LATENCY,
4379 &plane_wm, &cursor_wm)) {
4380 I915_WRITE(WM0_PIPEA_ILK,
4381 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4382 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4383 " plane %d, " "cursor: %d\n",
4384 plane_wm, cursor_wm);
4385 enabled |= 1;
4386 }
4387
4388 if (g4x_compute_wm0(dev, 1,
4389 &ironlake_display_wm_info,
4390 ILK_LP0_PLANE_LATENCY,
4391 &ironlake_cursor_wm_info,
4392 ILK_LP0_CURSOR_LATENCY,
4393 &plane_wm, &cursor_wm)) {
4394 I915_WRITE(WM0_PIPEB_ILK,
4395 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4396 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4397 " plane %d, cursor: %d\n",
4398 plane_wm, cursor_wm);
4399 enabled |= 2;
4400 }
4401
4402 /*
4403 * Calculate and update the self-refresh watermark only when one
4404 * display plane is used.
4405 */
4406 I915_WRITE(WM3_LP_ILK, 0);
4407 I915_WRITE(WM2_LP_ILK, 0);
4408 I915_WRITE(WM1_LP_ILK, 0);
4409
4410 if (!single_plane_enabled(enabled))
4411 return;
4412 enabled = ffs(enabled) - 1;
4413
4414 /* WM1 */
4415 if (!ironlake_compute_srwm(dev, 1, enabled,
4416 ILK_READ_WM1_LATENCY() * 500,
4417 &ironlake_display_srwm_info,
4418 &ironlake_cursor_srwm_info,
4419 &fbc_wm, &plane_wm, &cursor_wm))
4420 return;
4421
4422 I915_WRITE(WM1_LP_ILK,
4423 WM1_LP_SR_EN |
4424 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4425 (fbc_wm << WM1_LP_FBC_SHIFT) |
4426 (plane_wm << WM1_LP_SR_SHIFT) |
4427 cursor_wm);
4428
4429 /* WM2 */
4430 if (!ironlake_compute_srwm(dev, 2, enabled,
4431 ILK_READ_WM2_LATENCY() * 500,
4432 &ironlake_display_srwm_info,
4433 &ironlake_cursor_srwm_info,
4434 &fbc_wm, &plane_wm, &cursor_wm))
4435 return;
4436
4437 I915_WRITE(WM2_LP_ILK,
4438 WM2_LP_EN |
4439 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4440 (fbc_wm << WM1_LP_FBC_SHIFT) |
4441 (plane_wm << WM1_LP_SR_SHIFT) |
4442 cursor_wm);
4443
4444 /*
4445 * WM3 is unsupported on ILK, probably because we don't have latency
4446 * data for that power state
4447 */
4448 }
4449
4450 static void sandybridge_update_wm(struct drm_device *dev)
4451 {
4452 struct drm_i915_private *dev_priv = dev->dev_private;
4453 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
4454 int fbc_wm, plane_wm, cursor_wm;
4455 unsigned int enabled;
4456
4457 enabled = 0;
4458 if (g4x_compute_wm0(dev, 0,
4459 &sandybridge_display_wm_info, latency,
4460 &sandybridge_cursor_wm_info, latency,
4461 &plane_wm, &cursor_wm)) {
4462 I915_WRITE(WM0_PIPEA_ILK,
4463 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4464 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4465 " plane %d, " "cursor: %d\n",
4466 plane_wm, cursor_wm);
4467 enabled |= 1;
4468 }
4469
4470 if (g4x_compute_wm0(dev, 1,
4471 &sandybridge_display_wm_info, latency,
4472 &sandybridge_cursor_wm_info, latency,
4473 &plane_wm, &cursor_wm)) {
4474 I915_WRITE(WM0_PIPEB_ILK,
4475 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4476 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4477 " plane %d, cursor: %d\n",
4478 plane_wm, cursor_wm);
4479 enabled |= 2;
4480 }
4481
4482 /*
4483 * Calculate and update the self-refresh watermark only when one
4484 * display plane is used.
4485 *
4486 * SNB support 3 levels of watermark.
4487 *
4488 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4489 * and disabled in the descending order
4490 *
4491 */
4492 I915_WRITE(WM3_LP_ILK, 0);
4493 I915_WRITE(WM2_LP_ILK, 0);
4494 I915_WRITE(WM1_LP_ILK, 0);
4495
4496 if (!single_plane_enabled(enabled))
4497 return;
4498 enabled = ffs(enabled) - 1;
4499
4500 /* WM1 */
4501 if (!ironlake_compute_srwm(dev, 1, enabled,
4502 SNB_READ_WM1_LATENCY() * 500,
4503 &sandybridge_display_srwm_info,
4504 &sandybridge_cursor_srwm_info,
4505 &fbc_wm, &plane_wm, &cursor_wm))
4506 return;
4507
4508 I915_WRITE(WM1_LP_ILK,
4509 WM1_LP_SR_EN |
4510 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4511 (fbc_wm << WM1_LP_FBC_SHIFT) |
4512 (plane_wm << WM1_LP_SR_SHIFT) |
4513 cursor_wm);
4514
4515 /* WM2 */
4516 if (!ironlake_compute_srwm(dev, 2, enabled,
4517 SNB_READ_WM2_LATENCY() * 500,
4518 &sandybridge_display_srwm_info,
4519 &sandybridge_cursor_srwm_info,
4520 &fbc_wm, &plane_wm, &cursor_wm))
4521 return;
4522
4523 I915_WRITE(WM2_LP_ILK,
4524 WM2_LP_EN |
4525 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4526 (fbc_wm << WM1_LP_FBC_SHIFT) |
4527 (plane_wm << WM1_LP_SR_SHIFT) |
4528 cursor_wm);
4529
4530 /* WM3 */
4531 if (!ironlake_compute_srwm(dev, 3, enabled,
4532 SNB_READ_WM3_LATENCY() * 500,
4533 &sandybridge_display_srwm_info,
4534 &sandybridge_cursor_srwm_info,
4535 &fbc_wm, &plane_wm, &cursor_wm))
4536 return;
4537
4538 I915_WRITE(WM3_LP_ILK,
4539 WM3_LP_EN |
4540 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4541 (fbc_wm << WM1_LP_FBC_SHIFT) |
4542 (plane_wm << WM1_LP_SR_SHIFT) |
4543 cursor_wm);
4544 }
4545
4546 /**
4547 * intel_update_watermarks - update FIFO watermark values based on current modes
4548 *
4549 * Calculate watermark values for the various WM regs based on current mode
4550 * and plane configuration.
4551 *
4552 * There are several cases to deal with here:
4553 * - normal (i.e. non-self-refresh)
4554 * - self-refresh (SR) mode
4555 * - lines are large relative to FIFO size (buffer can hold up to 2)
4556 * - lines are small relative to FIFO size (buffer can hold more than 2
4557 * lines), so need to account for TLB latency
4558 *
4559 * The normal calculation is:
4560 * watermark = dotclock * bytes per pixel * latency
4561 * where latency is platform & configuration dependent (we assume pessimal
4562 * values here).
4563 *
4564 * The SR calculation is:
4565 * watermark = (trunc(latency/line time)+1) * surface width *
4566 * bytes per pixel
4567 * where
4568 * line time = htotal / dotclock
4569 * surface width = hdisplay for normal plane and 64 for cursor
4570 * and latency is assumed to be high, as above.
4571 *
4572 * The final value programmed to the register should always be rounded up,
4573 * and include an extra 2 entries to account for clock crossings.
4574 *
4575 * We don't use the sprite, so we can ignore that. And on Crestline we have
4576 * to set the non-SR watermarks to 8.
4577 */
4578 static void intel_update_watermarks(struct drm_device *dev)
4579 {
4580 struct drm_i915_private *dev_priv = dev->dev_private;
4581
4582 if (dev_priv->display.update_wm)
4583 dev_priv->display.update_wm(dev);
4584 }
4585
4586 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4587 {
4588 return dev_priv->lvds_use_ssc && i915_panel_use_ssc
4589 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4590 }
4591
4592 /**
4593 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4594 * @crtc: CRTC structure
4595 *
4596 * A pipe may be connected to one or more outputs. Based on the depth of the
4597 * attached framebuffer, choose a good color depth to use on the pipe.
4598 *
4599 * If possible, match the pipe depth to the fb depth. In some cases, this
4600 * isn't ideal, because the connected output supports a lesser or restricted
4601 * set of depths. Resolve that here:
4602 * LVDS typically supports only 6bpc, so clamp down in that case
4603 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4604 * Displays may support a restricted set as well, check EDID and clamp as
4605 * appropriate.
4606 *
4607 * RETURNS:
4608 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4609 * true if they don't match).
4610 */
4611 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4612 unsigned int *pipe_bpp)
4613 {
4614 struct drm_device *dev = crtc->dev;
4615 struct drm_i915_private *dev_priv = dev->dev_private;
4616 struct drm_encoder *encoder;
4617 struct drm_connector *connector;
4618 unsigned int display_bpc = UINT_MAX, bpc;
4619
4620 /* Walk the encoders & connectors on this crtc, get min bpc */
4621 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4622 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4623
4624 if (encoder->crtc != crtc)
4625 continue;
4626
4627 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4628 unsigned int lvds_bpc;
4629
4630 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4631 LVDS_A3_POWER_UP)
4632 lvds_bpc = 8;
4633 else
4634 lvds_bpc = 6;
4635
4636 if (lvds_bpc < display_bpc) {
4637 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4638 display_bpc = lvds_bpc;
4639 }
4640 continue;
4641 }
4642
4643 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4644 /* Use VBT settings if we have an eDP panel */
4645 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4646
4647 if (edp_bpc < display_bpc) {
4648 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4649 display_bpc = edp_bpc;
4650 }
4651 continue;
4652 }
4653
4654 /* Not one of the known troublemakers, check the EDID */
4655 list_for_each_entry(connector, &dev->mode_config.connector_list,
4656 head) {
4657 if (connector->encoder != encoder)
4658 continue;
4659
4660 /* Don't use an invalid EDID bpc value */
4661 if (connector->display_info.bpc &&
4662 connector->display_info.bpc < display_bpc) {
4663 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4664 display_bpc = connector->display_info.bpc;
4665 }
4666 }
4667
4668 /*
4669 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4670 * through, clamp it down. (Note: >12bpc will be caught below.)
4671 */
4672 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4673 if (display_bpc > 8 && display_bpc < 12) {
4674 DRM_DEBUG_DRIVER("forcing bpc to 12 for HDMI\n");
4675 display_bpc = 12;
4676 } else {
4677 DRM_DEBUG_DRIVER("forcing bpc to 8 for HDMI\n");
4678 display_bpc = 8;
4679 }
4680 }
4681 }
4682
4683 /*
4684 * We could just drive the pipe at the highest bpc all the time and
4685 * enable dithering as needed, but that costs bandwidth. So choose
4686 * the minimum value that expresses the full color range of the fb but
4687 * also stays within the max display bpc discovered above.
4688 */
4689
4690 switch (crtc->fb->depth) {
4691 case 8:
4692 bpc = 8; /* since we go through a colormap */
4693 break;
4694 case 15:
4695 case 16:
4696 bpc = 6; /* min is 18bpp */
4697 break;
4698 case 24:
4699 bpc = 8;
4700 break;
4701 case 30:
4702 bpc = 10;
4703 break;
4704 case 48:
4705 bpc = 12;
4706 break;
4707 default:
4708 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4709 bpc = min((unsigned int)8, display_bpc);
4710 break;
4711 }
4712
4713 display_bpc = min(display_bpc, bpc);
4714
4715 DRM_DEBUG_DRIVER("setting pipe bpc to %d (max display bpc %d)\n",
4716 bpc, display_bpc);
4717
4718 *pipe_bpp = display_bpc * 3;
4719
4720 return display_bpc != bpc;
4721 }
4722
4723 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4724 struct drm_display_mode *mode,
4725 struct drm_display_mode *adjusted_mode,
4726 int x, int y,
4727 struct drm_framebuffer *old_fb)
4728 {
4729 struct drm_device *dev = crtc->dev;
4730 struct drm_i915_private *dev_priv = dev->dev_private;
4731 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4732 int pipe = intel_crtc->pipe;
4733 int plane = intel_crtc->plane;
4734 int refclk, num_connectors = 0;
4735 intel_clock_t clock, reduced_clock;
4736 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4737 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
4738 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4739 struct drm_mode_config *mode_config = &dev->mode_config;
4740 struct intel_encoder *encoder;
4741 const intel_limit_t *limit;
4742 int ret;
4743 u32 temp;
4744 u32 lvds_sync = 0;
4745
4746 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4747 if (encoder->base.crtc != crtc)
4748 continue;
4749
4750 switch (encoder->type) {
4751 case INTEL_OUTPUT_LVDS:
4752 is_lvds = true;
4753 break;
4754 case INTEL_OUTPUT_SDVO:
4755 case INTEL_OUTPUT_HDMI:
4756 is_sdvo = true;
4757 if (encoder->needs_tv_clock)
4758 is_tv = true;
4759 break;
4760 case INTEL_OUTPUT_DVO:
4761 is_dvo = true;
4762 break;
4763 case INTEL_OUTPUT_TVOUT:
4764 is_tv = true;
4765 break;
4766 case INTEL_OUTPUT_ANALOG:
4767 is_crt = true;
4768 break;
4769 case INTEL_OUTPUT_DISPLAYPORT:
4770 is_dp = true;
4771 break;
4772 }
4773
4774 num_connectors++;
4775 }
4776
4777 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4778 refclk = dev_priv->lvds_ssc_freq * 1000;
4779 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4780 refclk / 1000);
4781 } else if (!IS_GEN2(dev)) {
4782 refclk = 96000;
4783 } else {
4784 refclk = 48000;
4785 }
4786
4787 /*
4788 * Returns a set of divisors for the desired target clock with the given
4789 * refclk, or FALSE. The returned values represent the clock equation:
4790 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4791 */
4792 limit = intel_limit(crtc, refclk);
4793 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4794 if (!ok) {
4795 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4796 return -EINVAL;
4797 }
4798
4799 /* Ensure that the cursor is valid for the new mode before changing... */
4800 intel_crtc_update_cursor(crtc, true);
4801
4802 if (is_lvds && dev_priv->lvds_downclock_avail) {
4803 has_reduced_clock = limit->find_pll(limit, crtc,
4804 dev_priv->lvds_downclock,
4805 refclk,
4806 &reduced_clock);
4807 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4808 /*
4809 * If the different P is found, it means that we can't
4810 * switch the display clock by using the FP0/FP1.
4811 * In such case we will disable the LVDS downclock
4812 * feature.
4813 */
4814 DRM_DEBUG_KMS("Different P is found for "
4815 "LVDS clock/downclock\n");
4816 has_reduced_clock = 0;
4817 }
4818 }
4819 /* SDVO TV has fixed PLL values depend on its clock range,
4820 this mirrors vbios setting. */
4821 if (is_sdvo && is_tv) {
4822 if (adjusted_mode->clock >= 100000
4823 && adjusted_mode->clock < 140500) {
4824 clock.p1 = 2;
4825 clock.p2 = 10;
4826 clock.n = 3;
4827 clock.m1 = 16;
4828 clock.m2 = 8;
4829 } else if (adjusted_mode->clock >= 140500
4830 && adjusted_mode->clock <= 200000) {
4831 clock.p1 = 1;
4832 clock.p2 = 10;
4833 clock.n = 6;
4834 clock.m1 = 12;
4835 clock.m2 = 8;
4836 }
4837 }
4838
4839 if (IS_PINEVIEW(dev)) {
4840 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
4841 if (has_reduced_clock)
4842 fp2 = (1 << reduced_clock.n) << 16 |
4843 reduced_clock.m1 << 8 | reduced_clock.m2;
4844 } else {
4845 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4846 if (has_reduced_clock)
4847 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4848 reduced_clock.m2;
4849 }
4850
4851 dpll = DPLL_VGA_MODE_DIS;
4852
4853 if (!IS_GEN2(dev)) {
4854 if (is_lvds)
4855 dpll |= DPLLB_MODE_LVDS;
4856 else
4857 dpll |= DPLLB_MODE_DAC_SERIAL;
4858 if (is_sdvo) {
4859 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4860 if (pixel_multiplier > 1) {
4861 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4862 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4863 }
4864 dpll |= DPLL_DVO_HIGH_SPEED;
4865 }
4866 if (is_dp)
4867 dpll |= DPLL_DVO_HIGH_SPEED;
4868
4869 /* compute bitmask from p1 value */
4870 if (IS_PINEVIEW(dev))
4871 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4872 else {
4873 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4874 if (IS_G4X(dev) && has_reduced_clock)
4875 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4876 }
4877 switch (clock.p2) {
4878 case 5:
4879 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4880 break;
4881 case 7:
4882 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4883 break;
4884 case 10:
4885 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4886 break;
4887 case 14:
4888 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4889 break;
4890 }
4891 if (INTEL_INFO(dev)->gen >= 4)
4892 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4893 } else {
4894 if (is_lvds) {
4895 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4896 } else {
4897 if (clock.p1 == 2)
4898 dpll |= PLL_P1_DIVIDE_BY_TWO;
4899 else
4900 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4901 if (clock.p2 == 4)
4902 dpll |= PLL_P2_DIVIDE_BY_4;
4903 }
4904 }
4905
4906 if (is_sdvo && is_tv)
4907 dpll |= PLL_REF_INPUT_TVCLKINBC;
4908 else if (is_tv)
4909 /* XXX: just matching BIOS for now */
4910 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4911 dpll |= 3;
4912 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4913 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4914 else
4915 dpll |= PLL_REF_INPUT_DREFCLK;
4916
4917 /* setup pipeconf */
4918 pipeconf = I915_READ(PIPECONF(pipe));
4919
4920 /* Set up the display plane register */
4921 dspcntr = DISPPLANE_GAMMA_ENABLE;
4922
4923 /* Ironlake's plane is forced to pipe, bit 24 is to
4924 enable color space conversion */
4925 if (pipe == 0)
4926 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4927 else
4928 dspcntr |= DISPPLANE_SEL_PIPE_B;
4929
4930 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4931 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4932 * core speed.
4933 *
4934 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4935 * pipe == 0 check?
4936 */
4937 if (mode->clock >
4938 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4939 pipeconf |= PIPECONF_DOUBLE_WIDE;
4940 else
4941 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4942 }
4943
4944 dpll |= DPLL_VCO_ENABLE;
4945
4946 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4947 drm_mode_debug_printmodeline(mode);
4948
4949 I915_WRITE(FP0(pipe), fp);
4950 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4951
4952 POSTING_READ(DPLL(pipe));
4953 udelay(150);
4954
4955 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4956 * This is an exception to the general rule that mode_set doesn't turn
4957 * things on.
4958 */
4959 if (is_lvds) {
4960 temp = I915_READ(LVDS);
4961 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4962 if (pipe == 1) {
4963 temp |= LVDS_PIPEB_SELECT;
4964 } else {
4965 temp &= ~LVDS_PIPEB_SELECT;
4966 }
4967 /* set the corresponsding LVDS_BORDER bit */
4968 temp |= dev_priv->lvds_border_bits;
4969 /* Set the B0-B3 data pairs corresponding to whether we're going to
4970 * set the DPLLs for dual-channel mode or not.
4971 */
4972 if (clock.p2 == 7)
4973 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4974 else
4975 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4976
4977 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4978 * appropriately here, but we need to look more thoroughly into how
4979 * panels behave in the two modes.
4980 */
4981 /* set the dithering flag on LVDS as needed */
4982 if (INTEL_INFO(dev)->gen >= 4) {
4983 if (dev_priv->lvds_dither)
4984 temp |= LVDS_ENABLE_DITHER;
4985 else
4986 temp &= ~LVDS_ENABLE_DITHER;
4987 }
4988 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4989 lvds_sync |= LVDS_HSYNC_POLARITY;
4990 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4991 lvds_sync |= LVDS_VSYNC_POLARITY;
4992 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
4993 != lvds_sync) {
4994 char flags[2] = "-+";
4995 DRM_INFO("Changing LVDS panel from "
4996 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
4997 flags[!(temp & LVDS_HSYNC_POLARITY)],
4998 flags[!(temp & LVDS_VSYNC_POLARITY)],
4999 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5000 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5001 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5002 temp |= lvds_sync;
5003 }
5004 I915_WRITE(LVDS, temp);
5005 }
5006
5007 if (is_dp) {
5008 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5009 }
5010
5011 I915_WRITE(DPLL(pipe), dpll);
5012
5013 /* Wait for the clocks to stabilize. */
5014 POSTING_READ(DPLL(pipe));
5015 udelay(150);
5016
5017 if (INTEL_INFO(dev)->gen >= 4) {
5018 temp = 0;
5019 if (is_sdvo) {
5020 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5021 if (temp > 1)
5022 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5023 else
5024 temp = 0;
5025 }
5026 I915_WRITE(DPLL_MD(pipe), temp);
5027 } else {
5028 /* The pixel multiplier can only be updated once the
5029 * DPLL is enabled and the clocks are stable.
5030 *
5031 * So write it again.
5032 */
5033 I915_WRITE(DPLL(pipe), dpll);
5034 }
5035
5036 intel_crtc->lowfreq_avail = false;
5037 if (is_lvds && has_reduced_clock && i915_powersave) {
5038 I915_WRITE(FP1(pipe), fp2);
5039 intel_crtc->lowfreq_avail = true;
5040 if (HAS_PIPE_CXSR(dev)) {
5041 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5042 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5043 }
5044 } else {
5045 I915_WRITE(FP1(pipe), fp);
5046 if (HAS_PIPE_CXSR(dev)) {
5047 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5048 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5049 }
5050 }
5051
5052 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5053 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5054 /* the chip adds 2 halflines automatically */
5055 adjusted_mode->crtc_vdisplay -= 1;
5056 adjusted_mode->crtc_vtotal -= 1;
5057 adjusted_mode->crtc_vblank_start -= 1;
5058 adjusted_mode->crtc_vblank_end -= 1;
5059 adjusted_mode->crtc_vsync_end -= 1;
5060 adjusted_mode->crtc_vsync_start -= 1;
5061 } else
5062 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5063
5064 I915_WRITE(HTOTAL(pipe),
5065 (adjusted_mode->crtc_hdisplay - 1) |
5066 ((adjusted_mode->crtc_htotal - 1) << 16));
5067 I915_WRITE(HBLANK(pipe),
5068 (adjusted_mode->crtc_hblank_start - 1) |
5069 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5070 I915_WRITE(HSYNC(pipe),
5071 (adjusted_mode->crtc_hsync_start - 1) |
5072 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5073
5074 I915_WRITE(VTOTAL(pipe),
5075 (adjusted_mode->crtc_vdisplay - 1) |
5076 ((adjusted_mode->crtc_vtotal - 1) << 16));
5077 I915_WRITE(VBLANK(pipe),
5078 (adjusted_mode->crtc_vblank_start - 1) |
5079 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5080 I915_WRITE(VSYNC(pipe),
5081 (adjusted_mode->crtc_vsync_start - 1) |
5082 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5083
5084 /* pipesrc and dspsize control the size that is scaled from,
5085 * which should always be the user's requested size.
5086 */
5087 I915_WRITE(DSPSIZE(plane),
5088 ((mode->vdisplay - 1) << 16) |
5089 (mode->hdisplay - 1));
5090 I915_WRITE(DSPPOS(plane), 0);
5091 I915_WRITE(PIPESRC(pipe),
5092 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5093
5094 I915_WRITE(PIPECONF(pipe), pipeconf);
5095 POSTING_READ(PIPECONF(pipe));
5096 intel_enable_pipe(dev_priv, pipe, false);
5097
5098 intel_wait_for_vblank(dev, pipe);
5099
5100 I915_WRITE(DSPCNTR(plane), dspcntr);
5101 POSTING_READ(DSPCNTR(plane));
5102 intel_enable_plane(dev_priv, plane, pipe);
5103
5104 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5105
5106 intel_update_watermarks(dev);
5107
5108 return ret;
5109 }
5110
5111 static void ironlake_update_pch_refclk(struct drm_device *dev)
5112 {
5113 struct drm_i915_private *dev_priv = dev->dev_private;
5114 struct drm_mode_config *mode_config = &dev->mode_config;
5115 struct drm_crtc *crtc;
5116 struct intel_encoder *encoder;
5117 struct intel_encoder *has_edp_encoder = NULL;
5118 u32 temp;
5119 bool has_lvds = false;
5120
5121 /* We need to take the global config into account */
5122 list_for_each_entry(crtc, &mode_config->crtc_list, head) {
5123 if (!crtc->enabled)
5124 continue;
5125
5126 list_for_each_entry(encoder, &mode_config->encoder_list,
5127 base.head) {
5128 if (encoder->base.crtc != crtc)
5129 continue;
5130
5131 switch (encoder->type) {
5132 case INTEL_OUTPUT_LVDS:
5133 has_lvds = true;
5134 case INTEL_OUTPUT_EDP:
5135 has_edp_encoder = encoder;
5136 break;
5137 }
5138 }
5139 }
5140
5141 /* Ironlake: try to setup display ref clock before DPLL
5142 * enabling. This is only under driver's control after
5143 * PCH B stepping, previous chipset stepping should be
5144 * ignoring this setting.
5145 */
5146 temp = I915_READ(PCH_DREF_CONTROL);
5147 /* Always enable nonspread source */
5148 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5149 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5150 temp &= ~DREF_SSC_SOURCE_MASK;
5151 temp |= DREF_SSC_SOURCE_ENABLE;
5152 I915_WRITE(PCH_DREF_CONTROL, temp);
5153
5154 POSTING_READ(PCH_DREF_CONTROL);
5155 udelay(200);
5156
5157 if (has_edp_encoder) {
5158 if (intel_panel_use_ssc(dev_priv)) {
5159 temp |= DREF_SSC1_ENABLE;
5160 I915_WRITE(PCH_DREF_CONTROL, temp);
5161
5162 POSTING_READ(PCH_DREF_CONTROL);
5163 udelay(200);
5164 }
5165 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5166
5167 /* Enable CPU source on CPU attached eDP */
5168 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5169 if (intel_panel_use_ssc(dev_priv))
5170 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5171 else
5172 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5173 } else {
5174 /* Enable SSC on PCH eDP if needed */
5175 if (intel_panel_use_ssc(dev_priv)) {
5176 DRM_ERROR("enabling SSC on PCH\n");
5177 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
5178 }
5179 }
5180 I915_WRITE(PCH_DREF_CONTROL, temp);
5181 POSTING_READ(PCH_DREF_CONTROL);
5182 udelay(200);
5183 }
5184 }
5185
5186 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5187 struct drm_display_mode *mode,
5188 struct drm_display_mode *adjusted_mode,
5189 int x, int y,
5190 struct drm_framebuffer *old_fb)
5191 {
5192 struct drm_device *dev = crtc->dev;
5193 struct drm_i915_private *dev_priv = dev->dev_private;
5194 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5195 int pipe = intel_crtc->pipe;
5196 int plane = intel_crtc->plane;
5197 int refclk, num_connectors = 0;
5198 intel_clock_t clock, reduced_clock;
5199 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
5200 bool ok, has_reduced_clock = false, is_sdvo = false;
5201 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5202 struct intel_encoder *has_edp_encoder = NULL;
5203 struct drm_mode_config *mode_config = &dev->mode_config;
5204 struct intel_encoder *encoder;
5205 const intel_limit_t *limit;
5206 int ret;
5207 struct fdi_m_n m_n = {0};
5208 u32 temp;
5209 u32 lvds_sync = 0;
5210 int target_clock, pixel_multiplier, lane, link_bw, factor;
5211 unsigned int pipe_bpp;
5212 bool dither;
5213
5214 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5215 if (encoder->base.crtc != crtc)
5216 continue;
5217
5218 switch (encoder->type) {
5219 case INTEL_OUTPUT_LVDS:
5220 is_lvds = true;
5221 break;
5222 case INTEL_OUTPUT_SDVO:
5223 case INTEL_OUTPUT_HDMI:
5224 is_sdvo = true;
5225 if (encoder->needs_tv_clock)
5226 is_tv = true;
5227 break;
5228 case INTEL_OUTPUT_TVOUT:
5229 is_tv = true;
5230 break;
5231 case INTEL_OUTPUT_ANALOG:
5232 is_crt = true;
5233 break;
5234 case INTEL_OUTPUT_DISPLAYPORT:
5235 is_dp = true;
5236 break;
5237 case INTEL_OUTPUT_EDP:
5238 has_edp_encoder = encoder;
5239 break;
5240 }
5241
5242 num_connectors++;
5243 }
5244
5245 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5246 refclk = dev_priv->lvds_ssc_freq * 1000;
5247 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5248 refclk / 1000);
5249 } else {
5250 refclk = 96000;
5251 if (!has_edp_encoder ||
5252 intel_encoder_is_pch_edp(&has_edp_encoder->base))
5253 refclk = 120000; /* 120Mhz refclk */
5254 }
5255
5256 /*
5257 * Returns a set of divisors for the desired target clock with the given
5258 * refclk, or FALSE. The returned values represent the clock equation:
5259 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5260 */
5261 limit = intel_limit(crtc, refclk);
5262 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
5263 if (!ok) {
5264 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5265 return -EINVAL;
5266 }
5267
5268 /* Ensure that the cursor is valid for the new mode before changing... */
5269 intel_crtc_update_cursor(crtc, true);
5270
5271 if (is_lvds && dev_priv->lvds_downclock_avail) {
5272 has_reduced_clock = limit->find_pll(limit, crtc,
5273 dev_priv->lvds_downclock,
5274 refclk,
5275 &reduced_clock);
5276 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
5277 /*
5278 * If the different P is found, it means that we can't
5279 * switch the display clock by using the FP0/FP1.
5280 * In such case we will disable the LVDS downclock
5281 * feature.
5282 */
5283 DRM_DEBUG_KMS("Different P is found for "
5284 "LVDS clock/downclock\n");
5285 has_reduced_clock = 0;
5286 }
5287 }
5288 /* SDVO TV has fixed PLL values depend on its clock range,
5289 this mirrors vbios setting. */
5290 if (is_sdvo && is_tv) {
5291 if (adjusted_mode->clock >= 100000
5292 && adjusted_mode->clock < 140500) {
5293 clock.p1 = 2;
5294 clock.p2 = 10;
5295 clock.n = 3;
5296 clock.m1 = 16;
5297 clock.m2 = 8;
5298 } else if (adjusted_mode->clock >= 140500
5299 && adjusted_mode->clock <= 200000) {
5300 clock.p1 = 1;
5301 clock.p2 = 10;
5302 clock.n = 6;
5303 clock.m1 = 12;
5304 clock.m2 = 8;
5305 }
5306 }
5307
5308 /* FDI link */
5309 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5310 lane = 0;
5311 /* CPU eDP doesn't require FDI link, so just set DP M/N
5312 according to current link config */
5313 if (has_edp_encoder &&
5314 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5315 target_clock = mode->clock;
5316 intel_edp_link_config(has_edp_encoder,
5317 &lane, &link_bw);
5318 } else {
5319 /* [e]DP over FDI requires target mode clock
5320 instead of link clock */
5321 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5322 target_clock = mode->clock;
5323 else
5324 target_clock = adjusted_mode->clock;
5325
5326 /* FDI is a binary signal running at ~2.7GHz, encoding
5327 * each output octet as 10 bits. The actual frequency
5328 * is stored as a divider into a 100MHz clock, and the
5329 * mode pixel clock is stored in units of 1KHz.
5330 * Hence the bw of each lane in terms of the mode signal
5331 * is:
5332 */
5333 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5334 }
5335
5336 /* determine panel color depth */
5337 temp = I915_READ(PIPECONF(pipe));
5338 temp &= ~PIPE_BPC_MASK;
5339 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp);
5340 switch (pipe_bpp) {
5341 case 18:
5342 temp |= PIPE_6BPC;
5343 break;
5344 case 24:
5345 temp |= PIPE_8BPC;
5346 break;
5347 case 30:
5348 temp |= PIPE_10BPC;
5349 break;
5350 case 36:
5351 temp |= PIPE_12BPC;
5352 break;
5353 default:
5354 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5355 pipe_bpp);
5356 temp |= PIPE_8BPC;
5357 pipe_bpp = 24;
5358 break;
5359 }
5360
5361 intel_crtc->bpp = pipe_bpp;
5362 I915_WRITE(PIPECONF(pipe), temp);
5363
5364 if (!lane) {
5365 /*
5366 * Account for spread spectrum to avoid
5367 * oversubscribing the link. Max center spread
5368 * is 2.5%; use 5% for safety's sake.
5369 */
5370 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5371 lane = bps / (link_bw * 8) + 1;
5372 }
5373
5374 intel_crtc->fdi_lanes = lane;
5375
5376 if (pixel_multiplier > 1)
5377 link_bw *= pixel_multiplier;
5378 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5379 &m_n);
5380
5381 ironlake_update_pch_refclk(dev);
5382
5383 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5384 if (has_reduced_clock)
5385 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5386 reduced_clock.m2;
5387
5388 /* Enable autotuning of the PLL clock (if permissible) */
5389 factor = 21;
5390 if (is_lvds) {
5391 if ((intel_panel_use_ssc(dev_priv) &&
5392 dev_priv->lvds_ssc_freq == 100) ||
5393 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5394 factor = 25;
5395 } else if (is_sdvo && is_tv)
5396 factor = 20;
5397
5398 if (clock.m < factor * clock.n)
5399 fp |= FP_CB_TUNE;
5400
5401 dpll = 0;
5402
5403 if (is_lvds)
5404 dpll |= DPLLB_MODE_LVDS;
5405 else
5406 dpll |= DPLLB_MODE_DAC_SERIAL;
5407 if (is_sdvo) {
5408 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5409 if (pixel_multiplier > 1) {
5410 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5411 }
5412 dpll |= DPLL_DVO_HIGH_SPEED;
5413 }
5414 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5415 dpll |= DPLL_DVO_HIGH_SPEED;
5416
5417 /* compute bitmask from p1 value */
5418 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5419 /* also FPA1 */
5420 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5421
5422 switch (clock.p2) {
5423 case 5:
5424 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5425 break;
5426 case 7:
5427 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5428 break;
5429 case 10:
5430 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5431 break;
5432 case 14:
5433 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5434 break;
5435 }
5436
5437 if (is_sdvo && is_tv)
5438 dpll |= PLL_REF_INPUT_TVCLKINBC;
5439 else if (is_tv)
5440 /* XXX: just matching BIOS for now */
5441 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5442 dpll |= 3;
5443 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5444 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5445 else
5446 dpll |= PLL_REF_INPUT_DREFCLK;
5447
5448 /* setup pipeconf */
5449 pipeconf = I915_READ(PIPECONF(pipe));
5450
5451 /* Set up the display plane register */
5452 dspcntr = DISPPLANE_GAMMA_ENABLE;
5453
5454 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5455 drm_mode_debug_printmodeline(mode);
5456
5457 /* PCH eDP needs FDI, but CPU eDP does not */
5458 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5459 I915_WRITE(PCH_FP0(pipe), fp);
5460 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5461
5462 POSTING_READ(PCH_DPLL(pipe));
5463 udelay(150);
5464 }
5465
5466 /* enable transcoder DPLL */
5467 if (HAS_PCH_CPT(dev)) {
5468 temp = I915_READ(PCH_DPLL_SEL);
5469 switch (pipe) {
5470 case 0:
5471 temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
5472 break;
5473 case 1:
5474 temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
5475 break;
5476 case 2:
5477 /* FIXME: manage transcoder PLLs? */
5478 temp |= TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL;
5479 break;
5480 default:
5481 BUG();
5482 }
5483 I915_WRITE(PCH_DPLL_SEL, temp);
5484
5485 POSTING_READ(PCH_DPLL_SEL);
5486 udelay(150);
5487 }
5488
5489 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5490 * This is an exception to the general rule that mode_set doesn't turn
5491 * things on.
5492 */
5493 if (is_lvds) {
5494 temp = I915_READ(PCH_LVDS);
5495 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5496 if (pipe == 1) {
5497 if (HAS_PCH_CPT(dev))
5498 temp |= PORT_TRANS_B_SEL_CPT;
5499 else
5500 temp |= LVDS_PIPEB_SELECT;
5501 } else {
5502 if (HAS_PCH_CPT(dev))
5503 temp &= ~PORT_TRANS_SEL_MASK;
5504 else
5505 temp &= ~LVDS_PIPEB_SELECT;
5506 }
5507 /* set the corresponsding LVDS_BORDER bit */
5508 temp |= dev_priv->lvds_border_bits;
5509 /* Set the B0-B3 data pairs corresponding to whether we're going to
5510 * set the DPLLs for dual-channel mode or not.
5511 */
5512 if (clock.p2 == 7)
5513 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5514 else
5515 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5516
5517 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5518 * appropriately here, but we need to look more thoroughly into how
5519 * panels behave in the two modes.
5520 */
5521 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5522 lvds_sync |= LVDS_HSYNC_POLARITY;
5523 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5524 lvds_sync |= LVDS_VSYNC_POLARITY;
5525 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5526 != lvds_sync) {
5527 char flags[2] = "-+";
5528 DRM_INFO("Changing LVDS panel from "
5529 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5530 flags[!(temp & LVDS_HSYNC_POLARITY)],
5531 flags[!(temp & LVDS_VSYNC_POLARITY)],
5532 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5533 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5534 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5535 temp |= lvds_sync;
5536 }
5537 I915_WRITE(PCH_LVDS, temp);
5538 }
5539
5540 pipeconf &= ~PIPECONF_DITHER_EN;
5541 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5542 if ((is_lvds && dev_priv->lvds_dither) || dither) {
5543 pipeconf |= PIPECONF_DITHER_EN;
5544 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
5545 }
5546 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5547 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5548 } else {
5549 /* For non-DP output, clear any trans DP clock recovery setting.*/
5550 I915_WRITE(TRANSDATA_M1(pipe), 0);
5551 I915_WRITE(TRANSDATA_N1(pipe), 0);
5552 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5553 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5554 }
5555
5556 if (!has_edp_encoder ||
5557 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5558 I915_WRITE(PCH_DPLL(pipe), dpll);
5559
5560 /* Wait for the clocks to stabilize. */
5561 POSTING_READ(PCH_DPLL(pipe));
5562 udelay(150);
5563
5564 /* The pixel multiplier can only be updated once the
5565 * DPLL is enabled and the clocks are stable.
5566 *
5567 * So write it again.
5568 */
5569 I915_WRITE(PCH_DPLL(pipe), dpll);
5570 }
5571
5572 intel_crtc->lowfreq_avail = false;
5573 if (is_lvds && has_reduced_clock && i915_powersave) {
5574 I915_WRITE(PCH_FP1(pipe), fp2);
5575 intel_crtc->lowfreq_avail = true;
5576 if (HAS_PIPE_CXSR(dev)) {
5577 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5578 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5579 }
5580 } else {
5581 I915_WRITE(PCH_FP1(pipe), fp);
5582 if (HAS_PIPE_CXSR(dev)) {
5583 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5584 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5585 }
5586 }
5587
5588 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5589 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5590 /* the chip adds 2 halflines automatically */
5591 adjusted_mode->crtc_vdisplay -= 1;
5592 adjusted_mode->crtc_vtotal -= 1;
5593 adjusted_mode->crtc_vblank_start -= 1;
5594 adjusted_mode->crtc_vblank_end -= 1;
5595 adjusted_mode->crtc_vsync_end -= 1;
5596 adjusted_mode->crtc_vsync_start -= 1;
5597 } else
5598 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5599
5600 I915_WRITE(HTOTAL(pipe),
5601 (adjusted_mode->crtc_hdisplay - 1) |
5602 ((adjusted_mode->crtc_htotal - 1) << 16));
5603 I915_WRITE(HBLANK(pipe),
5604 (adjusted_mode->crtc_hblank_start - 1) |
5605 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5606 I915_WRITE(HSYNC(pipe),
5607 (adjusted_mode->crtc_hsync_start - 1) |
5608 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5609
5610 I915_WRITE(VTOTAL(pipe),
5611 (adjusted_mode->crtc_vdisplay - 1) |
5612 ((adjusted_mode->crtc_vtotal - 1) << 16));
5613 I915_WRITE(VBLANK(pipe),
5614 (adjusted_mode->crtc_vblank_start - 1) |
5615 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5616 I915_WRITE(VSYNC(pipe),
5617 (adjusted_mode->crtc_vsync_start - 1) |
5618 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5619
5620 /* pipesrc controls the size that is scaled from, which should
5621 * always be the user's requested size.
5622 */
5623 I915_WRITE(PIPESRC(pipe),
5624 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5625
5626 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5627 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5628 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5629 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
5630
5631 if (has_edp_encoder &&
5632 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5633 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5634 }
5635
5636 I915_WRITE(PIPECONF(pipe), pipeconf);
5637 POSTING_READ(PIPECONF(pipe));
5638
5639 intel_wait_for_vblank(dev, pipe);
5640
5641 if (IS_GEN5(dev)) {
5642 /* enable address swizzle for tiling buffer */
5643 temp = I915_READ(DISP_ARB_CTL);
5644 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5645 }
5646
5647 I915_WRITE(DSPCNTR(plane), dspcntr);
5648 POSTING_READ(DSPCNTR(plane));
5649
5650 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5651
5652 intel_update_watermarks(dev);
5653
5654 return ret;
5655 }
5656
5657 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5658 struct drm_display_mode *mode,
5659 struct drm_display_mode *adjusted_mode,
5660 int x, int y,
5661 struct drm_framebuffer *old_fb)
5662 {
5663 struct drm_device *dev = crtc->dev;
5664 struct drm_i915_private *dev_priv = dev->dev_private;
5665 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5666 int pipe = intel_crtc->pipe;
5667 int ret;
5668
5669 drm_vblank_pre_modeset(dev, pipe);
5670
5671 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5672 x, y, old_fb);
5673
5674 drm_vblank_post_modeset(dev, pipe);
5675
5676 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
5677
5678 return ret;
5679 }
5680
5681 static void g4x_write_eld(struct drm_connector *connector,
5682 struct drm_crtc *crtc)
5683 {
5684 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5685 uint8_t *eld = connector->eld;
5686 uint32_t eldv;
5687 uint32_t len;
5688 uint32_t i;
5689
5690 i = I915_READ(G4X_AUD_VID_DID);
5691
5692 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5693 eldv = G4X_ELDV_DEVCL_DEVBLC;
5694 else
5695 eldv = G4X_ELDV_DEVCTG;
5696
5697 i = I915_READ(G4X_AUD_CNTL_ST);
5698 i &= ~(eldv | G4X_ELD_ADDR);
5699 len = (i >> 9) & 0x1f; /* ELD buffer size */
5700 I915_WRITE(G4X_AUD_CNTL_ST, i);
5701
5702 if (!eld[0])
5703 return;
5704
5705 len = min_t(uint8_t, eld[2], len);
5706 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5707 for (i = 0; i < len; i++)
5708 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5709
5710 i = I915_READ(G4X_AUD_CNTL_ST);
5711 i |= eldv;
5712 I915_WRITE(G4X_AUD_CNTL_ST, i);
5713 }
5714
5715 static void ironlake_write_eld(struct drm_connector *connector,
5716 struct drm_crtc *crtc)
5717 {
5718 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5719 uint8_t *eld = connector->eld;
5720 uint32_t eldv;
5721 uint32_t i;
5722 int len;
5723 int hdmiw_hdmiedid;
5724 int aud_cntl_st;
5725 int aud_cntrl_st2;
5726
5727 if (IS_IVYBRIDGE(connector->dev)) {
5728 hdmiw_hdmiedid = GEN7_HDMIW_HDMIEDID_A;
5729 aud_cntl_st = GEN7_AUD_CNTRL_ST_A;
5730 aud_cntrl_st2 = GEN7_AUD_CNTRL_ST2;
5731 } else {
5732 hdmiw_hdmiedid = GEN5_HDMIW_HDMIEDID_A;
5733 aud_cntl_st = GEN5_AUD_CNTL_ST_A;
5734 aud_cntrl_st2 = GEN5_AUD_CNTL_ST2;
5735 }
5736
5737 i = to_intel_crtc(crtc)->pipe;
5738 hdmiw_hdmiedid += i * 0x100;
5739 aud_cntl_st += i * 0x100;
5740
5741 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
5742
5743 i = I915_READ(aud_cntl_st);
5744 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
5745 if (!i) {
5746 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5747 /* operate blindly on all ports */
5748 eldv = GEN5_ELD_VALIDB;
5749 eldv |= GEN5_ELD_VALIDB << 4;
5750 eldv |= GEN5_ELD_VALIDB << 8;
5751 } else {
5752 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5753 eldv = GEN5_ELD_VALIDB << ((i - 1) * 4);
5754 }
5755
5756 i = I915_READ(aud_cntrl_st2);
5757 i &= ~eldv;
5758 I915_WRITE(aud_cntrl_st2, i);
5759
5760 if (!eld[0])
5761 return;
5762
5763 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5764 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5765 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5766 }
5767
5768 i = I915_READ(aud_cntl_st);
5769 i &= ~GEN5_ELD_ADDRESS;
5770 I915_WRITE(aud_cntl_st, i);
5771
5772 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5773 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5774 for (i = 0; i < len; i++)
5775 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5776
5777 i = I915_READ(aud_cntrl_st2);
5778 i |= eldv;
5779 I915_WRITE(aud_cntrl_st2, i);
5780 }
5781
5782 void intel_write_eld(struct drm_encoder *encoder,
5783 struct drm_display_mode *mode)
5784 {
5785 struct drm_crtc *crtc = encoder->crtc;
5786 struct drm_connector *connector;
5787 struct drm_device *dev = encoder->dev;
5788 struct drm_i915_private *dev_priv = dev->dev_private;
5789
5790 connector = drm_select_eld(encoder, mode);
5791 if (!connector)
5792 return;
5793
5794 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5795 connector->base.id,
5796 drm_get_connector_name(connector),
5797 connector->encoder->base.id,
5798 drm_get_encoder_name(connector->encoder));
5799
5800 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5801
5802 if (dev_priv->display.write_eld)
5803 dev_priv->display.write_eld(connector, crtc);
5804 }
5805
5806 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5807 void intel_crtc_load_lut(struct drm_crtc *crtc)
5808 {
5809 struct drm_device *dev = crtc->dev;
5810 struct drm_i915_private *dev_priv = dev->dev_private;
5811 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5812 int palreg = PALETTE(intel_crtc->pipe);
5813 int i;
5814
5815 /* The clocks have to be on to load the palette. */
5816 if (!crtc->enabled)
5817 return;
5818
5819 /* use legacy palette for Ironlake */
5820 if (HAS_PCH_SPLIT(dev))
5821 palreg = LGC_PALETTE(intel_crtc->pipe);
5822
5823 for (i = 0; i < 256; i++) {
5824 I915_WRITE(palreg + 4 * i,
5825 (intel_crtc->lut_r[i] << 16) |
5826 (intel_crtc->lut_g[i] << 8) |
5827 intel_crtc->lut_b[i]);
5828 }
5829 }
5830
5831 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5832 {
5833 struct drm_device *dev = crtc->dev;
5834 struct drm_i915_private *dev_priv = dev->dev_private;
5835 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5836 bool visible = base != 0;
5837 u32 cntl;
5838
5839 if (intel_crtc->cursor_visible == visible)
5840 return;
5841
5842 cntl = I915_READ(_CURACNTR);
5843 if (visible) {
5844 /* On these chipsets we can only modify the base whilst
5845 * the cursor is disabled.
5846 */
5847 I915_WRITE(_CURABASE, base);
5848
5849 cntl &= ~(CURSOR_FORMAT_MASK);
5850 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5851 cntl |= CURSOR_ENABLE |
5852 CURSOR_GAMMA_ENABLE |
5853 CURSOR_FORMAT_ARGB;
5854 } else
5855 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5856 I915_WRITE(_CURACNTR, cntl);
5857
5858 intel_crtc->cursor_visible = visible;
5859 }
5860
5861 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5862 {
5863 struct drm_device *dev = crtc->dev;
5864 struct drm_i915_private *dev_priv = dev->dev_private;
5865 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5866 int pipe = intel_crtc->pipe;
5867 bool visible = base != 0;
5868
5869 if (intel_crtc->cursor_visible != visible) {
5870 uint32_t cntl = I915_READ(CURCNTR(pipe));
5871 if (base) {
5872 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5873 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5874 cntl |= pipe << 28; /* Connect to correct pipe */
5875 } else {
5876 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5877 cntl |= CURSOR_MODE_DISABLE;
5878 }
5879 I915_WRITE(CURCNTR(pipe), cntl);
5880
5881 intel_crtc->cursor_visible = visible;
5882 }
5883 /* and commit changes on next vblank */
5884 I915_WRITE(CURBASE(pipe), base);
5885 }
5886
5887 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5888 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5889 bool on)
5890 {
5891 struct drm_device *dev = crtc->dev;
5892 struct drm_i915_private *dev_priv = dev->dev_private;
5893 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5894 int pipe = intel_crtc->pipe;
5895 int x = intel_crtc->cursor_x;
5896 int y = intel_crtc->cursor_y;
5897 u32 base, pos;
5898 bool visible;
5899
5900 pos = 0;
5901
5902 if (on && crtc->enabled && crtc->fb) {
5903 base = intel_crtc->cursor_addr;
5904 if (x > (int) crtc->fb->width)
5905 base = 0;
5906
5907 if (y > (int) crtc->fb->height)
5908 base = 0;
5909 } else
5910 base = 0;
5911
5912 if (x < 0) {
5913 if (x + intel_crtc->cursor_width < 0)
5914 base = 0;
5915
5916 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5917 x = -x;
5918 }
5919 pos |= x << CURSOR_X_SHIFT;
5920
5921 if (y < 0) {
5922 if (y + intel_crtc->cursor_height < 0)
5923 base = 0;
5924
5925 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5926 y = -y;
5927 }
5928 pos |= y << CURSOR_Y_SHIFT;
5929
5930 visible = base != 0;
5931 if (!visible && !intel_crtc->cursor_visible)
5932 return;
5933
5934 I915_WRITE(CURPOS(pipe), pos);
5935 if (IS_845G(dev) || IS_I865G(dev))
5936 i845_update_cursor(crtc, base);
5937 else
5938 i9xx_update_cursor(crtc, base);
5939
5940 if (visible)
5941 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
5942 }
5943
5944 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5945 struct drm_file *file,
5946 uint32_t handle,
5947 uint32_t width, uint32_t height)
5948 {
5949 struct drm_device *dev = crtc->dev;
5950 struct drm_i915_private *dev_priv = dev->dev_private;
5951 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5952 struct drm_i915_gem_object *obj;
5953 uint32_t addr;
5954 int ret;
5955
5956 DRM_DEBUG_KMS("\n");
5957
5958 /* if we want to turn off the cursor ignore width and height */
5959 if (!handle) {
5960 DRM_DEBUG_KMS("cursor off\n");
5961 addr = 0;
5962 obj = NULL;
5963 mutex_lock(&dev->struct_mutex);
5964 goto finish;
5965 }
5966
5967 /* Currently we only support 64x64 cursors */
5968 if (width != 64 || height != 64) {
5969 DRM_ERROR("we currently only support 64x64 cursors\n");
5970 return -EINVAL;
5971 }
5972
5973 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5974 if (&obj->base == NULL)
5975 return -ENOENT;
5976
5977 if (obj->base.size < width * height * 4) {
5978 DRM_ERROR("buffer is to small\n");
5979 ret = -ENOMEM;
5980 goto fail;
5981 }
5982
5983 /* we only need to pin inside GTT if cursor is non-phy */
5984 mutex_lock(&dev->struct_mutex);
5985 if (!dev_priv->info->cursor_needs_physical) {
5986 if (obj->tiling_mode) {
5987 DRM_ERROR("cursor cannot be tiled\n");
5988 ret = -EINVAL;
5989 goto fail_locked;
5990 }
5991
5992 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
5993 if (ret) {
5994 DRM_ERROR("failed to move cursor bo into the GTT\n");
5995 goto fail_locked;
5996 }
5997
5998 ret = i915_gem_object_put_fence(obj);
5999 if (ret) {
6000 DRM_ERROR("failed to release fence for cursor");
6001 goto fail_unpin;
6002 }
6003
6004 addr = obj->gtt_offset;
6005 } else {
6006 int align = IS_I830(dev) ? 16 * 1024 : 256;
6007 ret = i915_gem_attach_phys_object(dev, obj,
6008 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6009 align);
6010 if (ret) {
6011 DRM_ERROR("failed to attach phys object\n");
6012 goto fail_locked;
6013 }
6014 addr = obj->phys_obj->handle->busaddr;
6015 }
6016
6017 if (IS_GEN2(dev))
6018 I915_WRITE(CURSIZE, (height << 12) | width);
6019
6020 finish:
6021 if (intel_crtc->cursor_bo) {
6022 if (dev_priv->info->cursor_needs_physical) {
6023 if (intel_crtc->cursor_bo != obj)
6024 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6025 } else
6026 i915_gem_object_unpin(intel_crtc->cursor_bo);
6027 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6028 }
6029
6030 mutex_unlock(&dev->struct_mutex);
6031
6032 intel_crtc->cursor_addr = addr;
6033 intel_crtc->cursor_bo = obj;
6034 intel_crtc->cursor_width = width;
6035 intel_crtc->cursor_height = height;
6036
6037 intel_crtc_update_cursor(crtc, true);
6038
6039 return 0;
6040 fail_unpin:
6041 i915_gem_object_unpin(obj);
6042 fail_locked:
6043 mutex_unlock(&dev->struct_mutex);
6044 fail:
6045 drm_gem_object_unreference_unlocked(&obj->base);
6046 return ret;
6047 }
6048
6049 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6050 {
6051 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6052
6053 intel_crtc->cursor_x = x;
6054 intel_crtc->cursor_y = y;
6055
6056 intel_crtc_update_cursor(crtc, true);
6057
6058 return 0;
6059 }
6060
6061 /** Sets the color ramps on behalf of RandR */
6062 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6063 u16 blue, int regno)
6064 {
6065 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6066
6067 intel_crtc->lut_r[regno] = red >> 8;
6068 intel_crtc->lut_g[regno] = green >> 8;
6069 intel_crtc->lut_b[regno] = blue >> 8;
6070 }
6071
6072 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6073 u16 *blue, int regno)
6074 {
6075 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6076
6077 *red = intel_crtc->lut_r[regno] << 8;
6078 *green = intel_crtc->lut_g[regno] << 8;
6079 *blue = intel_crtc->lut_b[regno] << 8;
6080 }
6081
6082 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6083 u16 *blue, uint32_t start, uint32_t size)
6084 {
6085 int end = (start + size > 256) ? 256 : start + size, i;
6086 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6087
6088 for (i = start; i < end; i++) {
6089 intel_crtc->lut_r[i] = red[i] >> 8;
6090 intel_crtc->lut_g[i] = green[i] >> 8;
6091 intel_crtc->lut_b[i] = blue[i] >> 8;
6092 }
6093
6094 intel_crtc_load_lut(crtc);
6095 }
6096
6097 /**
6098 * Get a pipe with a simple mode set on it for doing load-based monitor
6099 * detection.
6100 *
6101 * It will be up to the load-detect code to adjust the pipe as appropriate for
6102 * its requirements. The pipe will be connected to no other encoders.
6103 *
6104 * Currently this code will only succeed if there is a pipe with no encoders
6105 * configured for it. In the future, it could choose to temporarily disable
6106 * some outputs to free up a pipe for its use.
6107 *
6108 * \return crtc, or NULL if no pipes are available.
6109 */
6110
6111 /* VESA 640x480x72Hz mode to set on the pipe */
6112 static struct drm_display_mode load_detect_mode = {
6113 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6114 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6115 };
6116
6117 static struct drm_framebuffer *
6118 intel_framebuffer_create(struct drm_device *dev,
6119 struct drm_mode_fb_cmd *mode_cmd,
6120 struct drm_i915_gem_object *obj)
6121 {
6122 struct intel_framebuffer *intel_fb;
6123 int ret;
6124
6125 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6126 if (!intel_fb) {
6127 drm_gem_object_unreference_unlocked(&obj->base);
6128 return ERR_PTR(-ENOMEM);
6129 }
6130
6131 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6132 if (ret) {
6133 drm_gem_object_unreference_unlocked(&obj->base);
6134 kfree(intel_fb);
6135 return ERR_PTR(ret);
6136 }
6137
6138 return &intel_fb->base;
6139 }
6140
6141 static u32
6142 intel_framebuffer_pitch_for_width(int width, int bpp)
6143 {
6144 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6145 return ALIGN(pitch, 64);
6146 }
6147
6148 static u32
6149 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6150 {
6151 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6152 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6153 }
6154
6155 static struct drm_framebuffer *
6156 intel_framebuffer_create_for_mode(struct drm_device *dev,
6157 struct drm_display_mode *mode,
6158 int depth, int bpp)
6159 {
6160 struct drm_i915_gem_object *obj;
6161 struct drm_mode_fb_cmd mode_cmd;
6162
6163 obj = i915_gem_alloc_object(dev,
6164 intel_framebuffer_size_for_mode(mode, bpp));
6165 if (obj == NULL)
6166 return ERR_PTR(-ENOMEM);
6167
6168 mode_cmd.width = mode->hdisplay;
6169 mode_cmd.height = mode->vdisplay;
6170 mode_cmd.depth = depth;
6171 mode_cmd.bpp = bpp;
6172 mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
6173
6174 return intel_framebuffer_create(dev, &mode_cmd, obj);
6175 }
6176
6177 static struct drm_framebuffer *
6178 mode_fits_in_fbdev(struct drm_device *dev,
6179 struct drm_display_mode *mode)
6180 {
6181 struct drm_i915_private *dev_priv = dev->dev_private;
6182 struct drm_i915_gem_object *obj;
6183 struct drm_framebuffer *fb;
6184
6185 if (dev_priv->fbdev == NULL)
6186 return NULL;
6187
6188 obj = dev_priv->fbdev->ifb.obj;
6189 if (obj == NULL)
6190 return NULL;
6191
6192 fb = &dev_priv->fbdev->ifb.base;
6193 if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
6194 fb->bits_per_pixel))
6195 return NULL;
6196
6197 if (obj->base.size < mode->vdisplay * fb->pitch)
6198 return NULL;
6199
6200 return fb;
6201 }
6202
6203 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
6204 struct drm_connector *connector,
6205 struct drm_display_mode *mode,
6206 struct intel_load_detect_pipe *old)
6207 {
6208 struct intel_crtc *intel_crtc;
6209 struct drm_crtc *possible_crtc;
6210 struct drm_encoder *encoder = &intel_encoder->base;
6211 struct drm_crtc *crtc = NULL;
6212 struct drm_device *dev = encoder->dev;
6213 struct drm_framebuffer *old_fb;
6214 int i = -1;
6215
6216 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6217 connector->base.id, drm_get_connector_name(connector),
6218 encoder->base.id, drm_get_encoder_name(encoder));
6219
6220 /*
6221 * Algorithm gets a little messy:
6222 *
6223 * - if the connector already has an assigned crtc, use it (but make
6224 * sure it's on first)
6225 *
6226 * - try to find the first unused crtc that can drive this connector,
6227 * and use that if we find one
6228 */
6229
6230 /* See if we already have a CRTC for this connector */
6231 if (encoder->crtc) {
6232 crtc = encoder->crtc;
6233
6234 intel_crtc = to_intel_crtc(crtc);
6235 old->dpms_mode = intel_crtc->dpms_mode;
6236 old->load_detect_temp = false;
6237
6238 /* Make sure the crtc and connector are running */
6239 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6240 struct drm_encoder_helper_funcs *encoder_funcs;
6241 struct drm_crtc_helper_funcs *crtc_funcs;
6242
6243 crtc_funcs = crtc->helper_private;
6244 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6245
6246 encoder_funcs = encoder->helper_private;
6247 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
6248 }
6249
6250 return true;
6251 }
6252
6253 /* Find an unused one (if possible) */
6254 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6255 i++;
6256 if (!(encoder->possible_crtcs & (1 << i)))
6257 continue;
6258 if (!possible_crtc->enabled) {
6259 crtc = possible_crtc;
6260 break;
6261 }
6262 }
6263
6264 /*
6265 * If we didn't find an unused CRTC, don't use any.
6266 */
6267 if (!crtc) {
6268 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6269 return false;
6270 }
6271
6272 encoder->crtc = crtc;
6273 connector->encoder = encoder;
6274
6275 intel_crtc = to_intel_crtc(crtc);
6276 old->dpms_mode = intel_crtc->dpms_mode;
6277 old->load_detect_temp = true;
6278 old->release_fb = NULL;
6279
6280 if (!mode)
6281 mode = &load_detect_mode;
6282
6283 old_fb = crtc->fb;
6284
6285 /* We need a framebuffer large enough to accommodate all accesses
6286 * that the plane may generate whilst we perform load detection.
6287 * We can not rely on the fbcon either being present (we get called
6288 * during its initialisation to detect all boot displays, or it may
6289 * not even exist) or that it is large enough to satisfy the
6290 * requested mode.
6291 */
6292 crtc->fb = mode_fits_in_fbdev(dev, mode);
6293 if (crtc->fb == NULL) {
6294 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6295 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6296 old->release_fb = crtc->fb;
6297 } else
6298 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6299 if (IS_ERR(crtc->fb)) {
6300 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6301 crtc->fb = old_fb;
6302 return false;
6303 }
6304
6305 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6306 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6307 if (old->release_fb)
6308 old->release_fb->funcs->destroy(old->release_fb);
6309 crtc->fb = old_fb;
6310 return false;
6311 }
6312
6313 /* let the connector get through one full cycle before testing */
6314 intel_wait_for_vblank(dev, intel_crtc->pipe);
6315
6316 return true;
6317 }
6318
6319 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
6320 struct drm_connector *connector,
6321 struct intel_load_detect_pipe *old)
6322 {
6323 struct drm_encoder *encoder = &intel_encoder->base;
6324 struct drm_device *dev = encoder->dev;
6325 struct drm_crtc *crtc = encoder->crtc;
6326 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6327 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6328
6329 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6330 connector->base.id, drm_get_connector_name(connector),
6331 encoder->base.id, drm_get_encoder_name(encoder));
6332
6333 if (old->load_detect_temp) {
6334 connector->encoder = NULL;
6335 drm_helper_disable_unused_functions(dev);
6336
6337 if (old->release_fb)
6338 old->release_fb->funcs->destroy(old->release_fb);
6339
6340 return;
6341 }
6342
6343 /* Switch crtc and encoder back off if necessary */
6344 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6345 encoder_funcs->dpms(encoder, old->dpms_mode);
6346 crtc_funcs->dpms(crtc, old->dpms_mode);
6347 }
6348 }
6349
6350 /* Returns the clock of the currently programmed mode of the given pipe. */
6351 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6352 {
6353 struct drm_i915_private *dev_priv = dev->dev_private;
6354 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6355 int pipe = intel_crtc->pipe;
6356 u32 dpll = I915_READ(DPLL(pipe));
6357 u32 fp;
6358 intel_clock_t clock;
6359
6360 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6361 fp = I915_READ(FP0(pipe));
6362 else
6363 fp = I915_READ(FP1(pipe));
6364
6365 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6366 if (IS_PINEVIEW(dev)) {
6367 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6368 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6369 } else {
6370 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6371 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6372 }
6373
6374 if (!IS_GEN2(dev)) {
6375 if (IS_PINEVIEW(dev))
6376 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6377 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6378 else
6379 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6380 DPLL_FPA01_P1_POST_DIV_SHIFT);
6381
6382 switch (dpll & DPLL_MODE_MASK) {
6383 case DPLLB_MODE_DAC_SERIAL:
6384 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6385 5 : 10;
6386 break;
6387 case DPLLB_MODE_LVDS:
6388 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6389 7 : 14;
6390 break;
6391 default:
6392 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6393 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6394 return 0;
6395 }
6396
6397 /* XXX: Handle the 100Mhz refclk */
6398 intel_clock(dev, 96000, &clock);
6399 } else {
6400 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6401
6402 if (is_lvds) {
6403 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6404 DPLL_FPA01_P1_POST_DIV_SHIFT);
6405 clock.p2 = 14;
6406
6407 if ((dpll & PLL_REF_INPUT_MASK) ==
6408 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6409 /* XXX: might not be 66MHz */
6410 intel_clock(dev, 66000, &clock);
6411 } else
6412 intel_clock(dev, 48000, &clock);
6413 } else {
6414 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6415 clock.p1 = 2;
6416 else {
6417 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6418 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6419 }
6420 if (dpll & PLL_P2_DIVIDE_BY_4)
6421 clock.p2 = 4;
6422 else
6423 clock.p2 = 2;
6424
6425 intel_clock(dev, 48000, &clock);
6426 }
6427 }
6428
6429 /* XXX: It would be nice to validate the clocks, but we can't reuse
6430 * i830PllIsValid() because it relies on the xf86_config connector
6431 * configuration being accurate, which it isn't necessarily.
6432 */
6433
6434 return clock.dot;
6435 }
6436
6437 /** Returns the currently programmed mode of the given pipe. */
6438 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6439 struct drm_crtc *crtc)
6440 {
6441 struct drm_i915_private *dev_priv = dev->dev_private;
6442 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6443 int pipe = intel_crtc->pipe;
6444 struct drm_display_mode *mode;
6445 int htot = I915_READ(HTOTAL(pipe));
6446 int hsync = I915_READ(HSYNC(pipe));
6447 int vtot = I915_READ(VTOTAL(pipe));
6448 int vsync = I915_READ(VSYNC(pipe));
6449
6450 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6451 if (!mode)
6452 return NULL;
6453
6454 mode->clock = intel_crtc_clock_get(dev, crtc);
6455 mode->hdisplay = (htot & 0xffff) + 1;
6456 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6457 mode->hsync_start = (hsync & 0xffff) + 1;
6458 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6459 mode->vdisplay = (vtot & 0xffff) + 1;
6460 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6461 mode->vsync_start = (vsync & 0xffff) + 1;
6462 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6463
6464 drm_mode_set_name(mode);
6465 drm_mode_set_crtcinfo(mode, 0);
6466
6467 return mode;
6468 }
6469
6470 #define GPU_IDLE_TIMEOUT 500 /* ms */
6471
6472 /* When this timer fires, we've been idle for awhile */
6473 static void intel_gpu_idle_timer(unsigned long arg)
6474 {
6475 struct drm_device *dev = (struct drm_device *)arg;
6476 drm_i915_private_t *dev_priv = dev->dev_private;
6477
6478 if (!list_empty(&dev_priv->mm.active_list)) {
6479 /* Still processing requests, so just re-arm the timer. */
6480 mod_timer(&dev_priv->idle_timer, jiffies +
6481 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6482 return;
6483 }
6484
6485 dev_priv->busy = false;
6486 queue_work(dev_priv->wq, &dev_priv->idle_work);
6487 }
6488
6489 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
6490
6491 static void intel_crtc_idle_timer(unsigned long arg)
6492 {
6493 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
6494 struct drm_crtc *crtc = &intel_crtc->base;
6495 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
6496 struct intel_framebuffer *intel_fb;
6497
6498 intel_fb = to_intel_framebuffer(crtc->fb);
6499 if (intel_fb && intel_fb->obj->active) {
6500 /* The framebuffer is still being accessed by the GPU. */
6501 mod_timer(&intel_crtc->idle_timer, jiffies +
6502 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6503 return;
6504 }
6505
6506 intel_crtc->busy = false;
6507 queue_work(dev_priv->wq, &dev_priv->idle_work);
6508 }
6509
6510 static void intel_increase_pllclock(struct drm_crtc *crtc)
6511 {
6512 struct drm_device *dev = crtc->dev;
6513 drm_i915_private_t *dev_priv = dev->dev_private;
6514 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6515 int pipe = intel_crtc->pipe;
6516 int dpll_reg = DPLL(pipe);
6517 int dpll;
6518
6519 if (HAS_PCH_SPLIT(dev))
6520 return;
6521
6522 if (!dev_priv->lvds_downclock_avail)
6523 return;
6524
6525 dpll = I915_READ(dpll_reg);
6526 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6527 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6528
6529 /* Unlock panel regs */
6530 I915_WRITE(PP_CONTROL,
6531 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
6532
6533 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6534 I915_WRITE(dpll_reg, dpll);
6535 intel_wait_for_vblank(dev, pipe);
6536
6537 dpll = I915_READ(dpll_reg);
6538 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6539 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6540
6541 /* ...and lock them again */
6542 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6543 }
6544
6545 /* Schedule downclock */
6546 mod_timer(&intel_crtc->idle_timer, jiffies +
6547 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6548 }
6549
6550 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6551 {
6552 struct drm_device *dev = crtc->dev;
6553 drm_i915_private_t *dev_priv = dev->dev_private;
6554 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6555 int pipe = intel_crtc->pipe;
6556 int dpll_reg = DPLL(pipe);
6557 int dpll = I915_READ(dpll_reg);
6558
6559 if (HAS_PCH_SPLIT(dev))
6560 return;
6561
6562 if (!dev_priv->lvds_downclock_avail)
6563 return;
6564
6565 /*
6566 * Since this is called by a timer, we should never get here in
6567 * the manual case.
6568 */
6569 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6570 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6571
6572 /* Unlock panel regs */
6573 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
6574 PANEL_UNLOCK_REGS);
6575
6576 dpll |= DISPLAY_RATE_SELECT_FPA1;
6577 I915_WRITE(dpll_reg, dpll);
6578 intel_wait_for_vblank(dev, pipe);
6579 dpll = I915_READ(dpll_reg);
6580 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6581 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6582
6583 /* ...and lock them again */
6584 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6585 }
6586
6587 }
6588
6589 /**
6590 * intel_idle_update - adjust clocks for idleness
6591 * @work: work struct
6592 *
6593 * Either the GPU or display (or both) went idle. Check the busy status
6594 * here and adjust the CRTC and GPU clocks as necessary.
6595 */
6596 static void intel_idle_update(struct work_struct *work)
6597 {
6598 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
6599 idle_work);
6600 struct drm_device *dev = dev_priv->dev;
6601 struct drm_crtc *crtc;
6602 struct intel_crtc *intel_crtc;
6603
6604 if (!i915_powersave)
6605 return;
6606
6607 mutex_lock(&dev->struct_mutex);
6608
6609 i915_update_gfx_val(dev_priv);
6610
6611 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6612 /* Skip inactive CRTCs */
6613 if (!crtc->fb)
6614 continue;
6615
6616 intel_crtc = to_intel_crtc(crtc);
6617 if (!intel_crtc->busy)
6618 intel_decrease_pllclock(crtc);
6619 }
6620
6621
6622 mutex_unlock(&dev->struct_mutex);
6623 }
6624
6625 /**
6626 * intel_mark_busy - mark the GPU and possibly the display busy
6627 * @dev: drm device
6628 * @obj: object we're operating on
6629 *
6630 * Callers can use this function to indicate that the GPU is busy processing
6631 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
6632 * buffer), we'll also mark the display as busy, so we know to increase its
6633 * clock frequency.
6634 */
6635 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
6636 {
6637 drm_i915_private_t *dev_priv = dev->dev_private;
6638 struct drm_crtc *crtc = NULL;
6639 struct intel_framebuffer *intel_fb;
6640 struct intel_crtc *intel_crtc;
6641
6642 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6643 return;
6644
6645 if (!dev_priv->busy)
6646 dev_priv->busy = true;
6647 else
6648 mod_timer(&dev_priv->idle_timer, jiffies +
6649 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6650
6651 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6652 if (!crtc->fb)
6653 continue;
6654
6655 intel_crtc = to_intel_crtc(crtc);
6656 intel_fb = to_intel_framebuffer(crtc->fb);
6657 if (intel_fb->obj == obj) {
6658 if (!intel_crtc->busy) {
6659 /* Non-busy -> busy, upclock */
6660 intel_increase_pllclock(crtc);
6661 intel_crtc->busy = true;
6662 } else {
6663 /* Busy -> busy, put off timer */
6664 mod_timer(&intel_crtc->idle_timer, jiffies +
6665 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6666 }
6667 }
6668 }
6669 }
6670
6671 static void intel_crtc_destroy(struct drm_crtc *crtc)
6672 {
6673 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6674 struct drm_device *dev = crtc->dev;
6675 struct intel_unpin_work *work;
6676 unsigned long flags;
6677
6678 spin_lock_irqsave(&dev->event_lock, flags);
6679 work = intel_crtc->unpin_work;
6680 intel_crtc->unpin_work = NULL;
6681 spin_unlock_irqrestore(&dev->event_lock, flags);
6682
6683 if (work) {
6684 cancel_work_sync(&work->work);
6685 kfree(work);
6686 }
6687
6688 drm_crtc_cleanup(crtc);
6689
6690 kfree(intel_crtc);
6691 }
6692
6693 static void intel_unpin_work_fn(struct work_struct *__work)
6694 {
6695 struct intel_unpin_work *work =
6696 container_of(__work, struct intel_unpin_work, work);
6697
6698 mutex_lock(&work->dev->struct_mutex);
6699 i915_gem_object_unpin(work->old_fb_obj);
6700 drm_gem_object_unreference(&work->pending_flip_obj->base);
6701 drm_gem_object_unreference(&work->old_fb_obj->base);
6702
6703 intel_update_fbc(work->dev);
6704 mutex_unlock(&work->dev->struct_mutex);
6705 kfree(work);
6706 }
6707
6708 static void do_intel_finish_page_flip(struct drm_device *dev,
6709 struct drm_crtc *crtc)
6710 {
6711 drm_i915_private_t *dev_priv = dev->dev_private;
6712 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6713 struct intel_unpin_work *work;
6714 struct drm_i915_gem_object *obj;
6715 struct drm_pending_vblank_event *e;
6716 struct timeval tnow, tvbl;
6717 unsigned long flags;
6718
6719 /* Ignore early vblank irqs */
6720 if (intel_crtc == NULL)
6721 return;
6722
6723 do_gettimeofday(&tnow);
6724
6725 spin_lock_irqsave(&dev->event_lock, flags);
6726 work = intel_crtc->unpin_work;
6727 if (work == NULL || !work->pending) {
6728 spin_unlock_irqrestore(&dev->event_lock, flags);
6729 return;
6730 }
6731
6732 intel_crtc->unpin_work = NULL;
6733
6734 if (work->event) {
6735 e = work->event;
6736 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6737
6738 /* Called before vblank count and timestamps have
6739 * been updated for the vblank interval of flip
6740 * completion? Need to increment vblank count and
6741 * add one videorefresh duration to returned timestamp
6742 * to account for this. We assume this happened if we
6743 * get called over 0.9 frame durations after the last
6744 * timestamped vblank.
6745 *
6746 * This calculation can not be used with vrefresh rates
6747 * below 5Hz (10Hz to be on the safe side) without
6748 * promoting to 64 integers.
6749 */
6750 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6751 9 * crtc->framedur_ns) {
6752 e->event.sequence++;
6753 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6754 crtc->framedur_ns);
6755 }
6756
6757 e->event.tv_sec = tvbl.tv_sec;
6758 e->event.tv_usec = tvbl.tv_usec;
6759
6760 list_add_tail(&e->base.link,
6761 &e->base.file_priv->event_list);
6762 wake_up_interruptible(&e->base.file_priv->event_wait);
6763 }
6764
6765 drm_vblank_put(dev, intel_crtc->pipe);
6766
6767 spin_unlock_irqrestore(&dev->event_lock, flags);
6768
6769 obj = work->old_fb_obj;
6770
6771 atomic_clear_mask(1 << intel_crtc->plane,
6772 &obj->pending_flip.counter);
6773 if (atomic_read(&obj->pending_flip) == 0)
6774 wake_up(&dev_priv->pending_flip_queue);
6775
6776 schedule_work(&work->work);
6777
6778 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6779 }
6780
6781 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6782 {
6783 drm_i915_private_t *dev_priv = dev->dev_private;
6784 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6785
6786 do_intel_finish_page_flip(dev, crtc);
6787 }
6788
6789 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6790 {
6791 drm_i915_private_t *dev_priv = dev->dev_private;
6792 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6793
6794 do_intel_finish_page_flip(dev, crtc);
6795 }
6796
6797 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6798 {
6799 drm_i915_private_t *dev_priv = dev->dev_private;
6800 struct intel_crtc *intel_crtc =
6801 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6802 unsigned long flags;
6803
6804 spin_lock_irqsave(&dev->event_lock, flags);
6805 if (intel_crtc->unpin_work) {
6806 if ((++intel_crtc->unpin_work->pending) > 1)
6807 DRM_ERROR("Prepared flip multiple times\n");
6808 } else {
6809 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6810 }
6811 spin_unlock_irqrestore(&dev->event_lock, flags);
6812 }
6813
6814 static int intel_gen2_queue_flip(struct drm_device *dev,
6815 struct drm_crtc *crtc,
6816 struct drm_framebuffer *fb,
6817 struct drm_i915_gem_object *obj)
6818 {
6819 struct drm_i915_private *dev_priv = dev->dev_private;
6820 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6821 unsigned long offset;
6822 u32 flip_mask;
6823 int ret;
6824
6825 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6826 if (ret)
6827 goto out;
6828
6829 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6830 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6831
6832 ret = BEGIN_LP_RING(6);
6833 if (ret)
6834 goto out;
6835
6836 /* Can't queue multiple flips, so wait for the previous
6837 * one to finish before executing the next.
6838 */
6839 if (intel_crtc->plane)
6840 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6841 else
6842 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6843 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6844 OUT_RING(MI_NOOP);
6845 OUT_RING(MI_DISPLAY_FLIP |
6846 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6847 OUT_RING(fb->pitch);
6848 OUT_RING(obj->gtt_offset + offset);
6849 OUT_RING(MI_NOOP);
6850 ADVANCE_LP_RING();
6851 out:
6852 return ret;
6853 }
6854
6855 static int intel_gen3_queue_flip(struct drm_device *dev,
6856 struct drm_crtc *crtc,
6857 struct drm_framebuffer *fb,
6858 struct drm_i915_gem_object *obj)
6859 {
6860 struct drm_i915_private *dev_priv = dev->dev_private;
6861 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6862 unsigned long offset;
6863 u32 flip_mask;
6864 int ret;
6865
6866 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6867 if (ret)
6868 goto out;
6869
6870 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6871 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6872
6873 ret = BEGIN_LP_RING(6);
6874 if (ret)
6875 goto out;
6876
6877 if (intel_crtc->plane)
6878 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6879 else
6880 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6881 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6882 OUT_RING(MI_NOOP);
6883 OUT_RING(MI_DISPLAY_FLIP_I915 |
6884 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6885 OUT_RING(fb->pitch);
6886 OUT_RING(obj->gtt_offset + offset);
6887 OUT_RING(MI_NOOP);
6888
6889 ADVANCE_LP_RING();
6890 out:
6891 return ret;
6892 }
6893
6894 static int intel_gen4_queue_flip(struct drm_device *dev,
6895 struct drm_crtc *crtc,
6896 struct drm_framebuffer *fb,
6897 struct drm_i915_gem_object *obj)
6898 {
6899 struct drm_i915_private *dev_priv = dev->dev_private;
6900 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6901 uint32_t pf, pipesrc;
6902 int ret;
6903
6904 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6905 if (ret)
6906 goto out;
6907
6908 ret = BEGIN_LP_RING(4);
6909 if (ret)
6910 goto out;
6911
6912 /* i965+ uses the linear or tiled offsets from the
6913 * Display Registers (which do not change across a page-flip)
6914 * so we need only reprogram the base address.
6915 */
6916 OUT_RING(MI_DISPLAY_FLIP |
6917 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6918 OUT_RING(fb->pitch);
6919 OUT_RING(obj->gtt_offset | obj->tiling_mode);
6920
6921 /* XXX Enabling the panel-fitter across page-flip is so far
6922 * untested on non-native modes, so ignore it for now.
6923 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6924 */
6925 pf = 0;
6926 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6927 OUT_RING(pf | pipesrc);
6928 ADVANCE_LP_RING();
6929 out:
6930 return ret;
6931 }
6932
6933 static int intel_gen6_queue_flip(struct drm_device *dev,
6934 struct drm_crtc *crtc,
6935 struct drm_framebuffer *fb,
6936 struct drm_i915_gem_object *obj)
6937 {
6938 struct drm_i915_private *dev_priv = dev->dev_private;
6939 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6940 uint32_t pf, pipesrc;
6941 int ret;
6942
6943 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6944 if (ret)
6945 goto out;
6946
6947 ret = BEGIN_LP_RING(4);
6948 if (ret)
6949 goto out;
6950
6951 OUT_RING(MI_DISPLAY_FLIP |
6952 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6953 OUT_RING(fb->pitch | obj->tiling_mode);
6954 OUT_RING(obj->gtt_offset);
6955
6956 pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6957 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6958 OUT_RING(pf | pipesrc);
6959 ADVANCE_LP_RING();
6960 out:
6961 return ret;
6962 }
6963
6964 /*
6965 * On gen7 we currently use the blit ring because (in early silicon at least)
6966 * the render ring doesn't give us interrpts for page flip completion, which
6967 * means clients will hang after the first flip is queued. Fortunately the
6968 * blit ring generates interrupts properly, so use it instead.
6969 */
6970 static int intel_gen7_queue_flip(struct drm_device *dev,
6971 struct drm_crtc *crtc,
6972 struct drm_framebuffer *fb,
6973 struct drm_i915_gem_object *obj)
6974 {
6975 struct drm_i915_private *dev_priv = dev->dev_private;
6976 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6977 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6978 int ret;
6979
6980 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6981 if (ret)
6982 goto out;
6983
6984 ret = intel_ring_begin(ring, 4);
6985 if (ret)
6986 goto out;
6987
6988 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
6989 intel_ring_emit(ring, (fb->pitch | obj->tiling_mode));
6990 intel_ring_emit(ring, (obj->gtt_offset));
6991 intel_ring_emit(ring, (MI_NOOP));
6992 intel_ring_advance(ring);
6993 out:
6994 return ret;
6995 }
6996
6997 static int intel_default_queue_flip(struct drm_device *dev,
6998 struct drm_crtc *crtc,
6999 struct drm_framebuffer *fb,
7000 struct drm_i915_gem_object *obj)
7001 {
7002 return -ENODEV;
7003 }
7004
7005 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7006 struct drm_framebuffer *fb,
7007 struct drm_pending_vblank_event *event)
7008 {
7009 struct drm_device *dev = crtc->dev;
7010 struct drm_i915_private *dev_priv = dev->dev_private;
7011 struct intel_framebuffer *intel_fb;
7012 struct drm_i915_gem_object *obj;
7013 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7014 struct intel_unpin_work *work;
7015 unsigned long flags;
7016 int ret;
7017
7018 work = kzalloc(sizeof *work, GFP_KERNEL);
7019 if (work == NULL)
7020 return -ENOMEM;
7021
7022 work->event = event;
7023 work->dev = crtc->dev;
7024 intel_fb = to_intel_framebuffer(crtc->fb);
7025 work->old_fb_obj = intel_fb->obj;
7026 INIT_WORK(&work->work, intel_unpin_work_fn);
7027
7028 /* We borrow the event spin lock for protecting unpin_work */
7029 spin_lock_irqsave(&dev->event_lock, flags);
7030 if (intel_crtc->unpin_work) {
7031 spin_unlock_irqrestore(&dev->event_lock, flags);
7032 kfree(work);
7033
7034 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7035 return -EBUSY;
7036 }
7037 intel_crtc->unpin_work = work;
7038 spin_unlock_irqrestore(&dev->event_lock, flags);
7039
7040 intel_fb = to_intel_framebuffer(fb);
7041 obj = intel_fb->obj;
7042
7043 mutex_lock(&dev->struct_mutex);
7044
7045 /* Reference the objects for the scheduled work. */
7046 drm_gem_object_reference(&work->old_fb_obj->base);
7047 drm_gem_object_reference(&obj->base);
7048
7049 crtc->fb = fb;
7050
7051 ret = drm_vblank_get(dev, intel_crtc->pipe);
7052 if (ret)
7053 goto cleanup_objs;
7054
7055 work->pending_flip_obj = obj;
7056
7057 work->enable_stall_check = true;
7058
7059 /* Block clients from rendering to the new back buffer until
7060 * the flip occurs and the object is no longer visible.
7061 */
7062 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7063
7064 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7065 if (ret)
7066 goto cleanup_pending;
7067
7068 intel_disable_fbc(dev);
7069 mutex_unlock(&dev->struct_mutex);
7070
7071 trace_i915_flip_request(intel_crtc->plane, obj);
7072
7073 return 0;
7074
7075 cleanup_pending:
7076 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7077 cleanup_objs:
7078 drm_gem_object_unreference(&work->old_fb_obj->base);
7079 drm_gem_object_unreference(&obj->base);
7080 mutex_unlock(&dev->struct_mutex);
7081
7082 spin_lock_irqsave(&dev->event_lock, flags);
7083 intel_crtc->unpin_work = NULL;
7084 spin_unlock_irqrestore(&dev->event_lock, flags);
7085
7086 kfree(work);
7087
7088 return ret;
7089 }
7090
7091 static void intel_sanitize_modesetting(struct drm_device *dev,
7092 int pipe, int plane)
7093 {
7094 struct drm_i915_private *dev_priv = dev->dev_private;
7095 u32 reg, val;
7096
7097 if (HAS_PCH_SPLIT(dev))
7098 return;
7099
7100 /* Who knows what state these registers were left in by the BIOS or
7101 * grub?
7102 *
7103 * If we leave the registers in a conflicting state (e.g. with the
7104 * display plane reading from the other pipe than the one we intend
7105 * to use) then when we attempt to teardown the active mode, we will
7106 * not disable the pipes and planes in the correct order -- leaving
7107 * a plane reading from a disabled pipe and possibly leading to
7108 * undefined behaviour.
7109 */
7110
7111 reg = DSPCNTR(plane);
7112 val = I915_READ(reg);
7113
7114 if ((val & DISPLAY_PLANE_ENABLE) == 0)
7115 return;
7116 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
7117 return;
7118
7119 /* This display plane is active and attached to the other CPU pipe. */
7120 pipe = !pipe;
7121
7122 /* Disable the plane and wait for it to stop reading from the pipe. */
7123 intel_disable_plane(dev_priv, plane, pipe);
7124 intel_disable_pipe(dev_priv, pipe);
7125 }
7126
7127 static void intel_crtc_reset(struct drm_crtc *crtc)
7128 {
7129 struct drm_device *dev = crtc->dev;
7130 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7131
7132 /* Reset flags back to the 'unknown' status so that they
7133 * will be correctly set on the initial modeset.
7134 */
7135 intel_crtc->dpms_mode = -1;
7136
7137 /* We need to fix up any BIOS configuration that conflicts with
7138 * our expectations.
7139 */
7140 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
7141 }
7142
7143 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7144 .dpms = intel_crtc_dpms,
7145 .mode_fixup = intel_crtc_mode_fixup,
7146 .mode_set = intel_crtc_mode_set,
7147 .mode_set_base = intel_pipe_set_base,
7148 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7149 .load_lut = intel_crtc_load_lut,
7150 .disable = intel_crtc_disable,
7151 };
7152
7153 static const struct drm_crtc_funcs intel_crtc_funcs = {
7154 .reset = intel_crtc_reset,
7155 .cursor_set = intel_crtc_cursor_set,
7156 .cursor_move = intel_crtc_cursor_move,
7157 .gamma_set = intel_crtc_gamma_set,
7158 .set_config = drm_crtc_helper_set_config,
7159 .destroy = intel_crtc_destroy,
7160 .page_flip = intel_crtc_page_flip,
7161 };
7162
7163 static void intel_crtc_init(struct drm_device *dev, int pipe)
7164 {
7165 drm_i915_private_t *dev_priv = dev->dev_private;
7166 struct intel_crtc *intel_crtc;
7167 int i;
7168
7169 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7170 if (intel_crtc == NULL)
7171 return;
7172
7173 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7174
7175 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7176 for (i = 0; i < 256; i++) {
7177 intel_crtc->lut_r[i] = i;
7178 intel_crtc->lut_g[i] = i;
7179 intel_crtc->lut_b[i] = i;
7180 }
7181
7182 /* Swap pipes & planes for FBC on pre-965 */
7183 intel_crtc->pipe = pipe;
7184 intel_crtc->plane = pipe;
7185 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7186 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7187 intel_crtc->plane = !pipe;
7188 }
7189
7190 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7191 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7192 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7193 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7194
7195 intel_crtc_reset(&intel_crtc->base);
7196 intel_crtc->active = true; /* force the pipe off on setup_init_config */
7197 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7198
7199 if (HAS_PCH_SPLIT(dev)) {
7200 intel_helper_funcs.prepare = ironlake_crtc_prepare;
7201 intel_helper_funcs.commit = ironlake_crtc_commit;
7202 } else {
7203 intel_helper_funcs.prepare = i9xx_crtc_prepare;
7204 intel_helper_funcs.commit = i9xx_crtc_commit;
7205 }
7206
7207 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7208
7209 intel_crtc->busy = false;
7210
7211 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
7212 (unsigned long)intel_crtc);
7213 }
7214
7215 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7216 struct drm_file *file)
7217 {
7218 drm_i915_private_t *dev_priv = dev->dev_private;
7219 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7220 struct drm_mode_object *drmmode_obj;
7221 struct intel_crtc *crtc;
7222
7223 if (!dev_priv) {
7224 DRM_ERROR("called with no initialization\n");
7225 return -EINVAL;
7226 }
7227
7228 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7229 DRM_MODE_OBJECT_CRTC);
7230
7231 if (!drmmode_obj) {
7232 DRM_ERROR("no such CRTC id\n");
7233 return -EINVAL;
7234 }
7235
7236 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7237 pipe_from_crtc_id->pipe = crtc->pipe;
7238
7239 return 0;
7240 }
7241
7242 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
7243 {
7244 struct intel_encoder *encoder;
7245 int index_mask = 0;
7246 int entry = 0;
7247
7248 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7249 if (type_mask & encoder->clone_mask)
7250 index_mask |= (1 << entry);
7251 entry++;
7252 }
7253
7254 return index_mask;
7255 }
7256
7257 static bool has_edp_a(struct drm_device *dev)
7258 {
7259 struct drm_i915_private *dev_priv = dev->dev_private;
7260
7261 if (!IS_MOBILE(dev))
7262 return false;
7263
7264 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7265 return false;
7266
7267 if (IS_GEN5(dev) &&
7268 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7269 return false;
7270
7271 return true;
7272 }
7273
7274 static void intel_setup_outputs(struct drm_device *dev)
7275 {
7276 struct drm_i915_private *dev_priv = dev->dev_private;
7277 struct intel_encoder *encoder;
7278 bool dpd_is_edp = false;
7279 bool has_lvds = false;
7280
7281 if (IS_MOBILE(dev) && !IS_I830(dev))
7282 has_lvds = intel_lvds_init(dev);
7283 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7284 /* disable the panel fitter on everything but LVDS */
7285 I915_WRITE(PFIT_CONTROL, 0);
7286 }
7287
7288 if (HAS_PCH_SPLIT(dev)) {
7289 dpd_is_edp = intel_dpd_is_edp(dev);
7290
7291 if (has_edp_a(dev))
7292 intel_dp_init(dev, DP_A);
7293
7294 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7295 intel_dp_init(dev, PCH_DP_D);
7296 }
7297
7298 intel_crt_init(dev);
7299
7300 if (HAS_PCH_SPLIT(dev)) {
7301 int found;
7302
7303 if (I915_READ(HDMIB) & PORT_DETECTED) {
7304 /* PCH SDVOB multiplex with HDMIB */
7305 found = intel_sdvo_init(dev, PCH_SDVOB);
7306 if (!found)
7307 intel_hdmi_init(dev, HDMIB);
7308 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7309 intel_dp_init(dev, PCH_DP_B);
7310 }
7311
7312 if (I915_READ(HDMIC) & PORT_DETECTED)
7313 intel_hdmi_init(dev, HDMIC);
7314
7315 if (I915_READ(HDMID) & PORT_DETECTED)
7316 intel_hdmi_init(dev, HDMID);
7317
7318 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7319 intel_dp_init(dev, PCH_DP_C);
7320
7321 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7322 intel_dp_init(dev, PCH_DP_D);
7323
7324 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7325 bool found = false;
7326
7327 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7328 DRM_DEBUG_KMS("probing SDVOB\n");
7329 found = intel_sdvo_init(dev, SDVOB);
7330 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7331 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7332 intel_hdmi_init(dev, SDVOB);
7333 }
7334
7335 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7336 DRM_DEBUG_KMS("probing DP_B\n");
7337 intel_dp_init(dev, DP_B);
7338 }
7339 }
7340
7341 /* Before G4X SDVOC doesn't have its own detect register */
7342
7343 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7344 DRM_DEBUG_KMS("probing SDVOC\n");
7345 found = intel_sdvo_init(dev, SDVOC);
7346 }
7347
7348 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7349
7350 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7351 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7352 intel_hdmi_init(dev, SDVOC);
7353 }
7354 if (SUPPORTS_INTEGRATED_DP(dev)) {
7355 DRM_DEBUG_KMS("probing DP_C\n");
7356 intel_dp_init(dev, DP_C);
7357 }
7358 }
7359
7360 if (SUPPORTS_INTEGRATED_DP(dev) &&
7361 (I915_READ(DP_D) & DP_DETECTED)) {
7362 DRM_DEBUG_KMS("probing DP_D\n");
7363 intel_dp_init(dev, DP_D);
7364 }
7365 } else if (IS_GEN2(dev))
7366 intel_dvo_init(dev);
7367
7368 if (SUPPORTS_TV(dev))
7369 intel_tv_init(dev);
7370
7371 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7372 encoder->base.possible_crtcs = encoder->crtc_mask;
7373 encoder->base.possible_clones =
7374 intel_encoder_clones(dev, encoder->clone_mask);
7375 }
7376
7377 /* disable all the possible outputs/crtcs before entering KMS mode */
7378 drm_helper_disable_unused_functions(dev);
7379 }
7380
7381 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7382 {
7383 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7384
7385 drm_framebuffer_cleanup(fb);
7386 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
7387
7388 kfree(intel_fb);
7389 }
7390
7391 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
7392 struct drm_file *file,
7393 unsigned int *handle)
7394 {
7395 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7396 struct drm_i915_gem_object *obj = intel_fb->obj;
7397
7398 return drm_gem_handle_create(file, &obj->base, handle);
7399 }
7400
7401 static const struct drm_framebuffer_funcs intel_fb_funcs = {
7402 .destroy = intel_user_framebuffer_destroy,
7403 .create_handle = intel_user_framebuffer_create_handle,
7404 };
7405
7406 int intel_framebuffer_init(struct drm_device *dev,
7407 struct intel_framebuffer *intel_fb,
7408 struct drm_mode_fb_cmd *mode_cmd,
7409 struct drm_i915_gem_object *obj)
7410 {
7411 int ret;
7412
7413 if (obj->tiling_mode == I915_TILING_Y)
7414 return -EINVAL;
7415
7416 if (mode_cmd->pitch & 63)
7417 return -EINVAL;
7418
7419 switch (mode_cmd->bpp) {
7420 case 8:
7421 case 16:
7422 /* Only pre-ILK can handle 5:5:5 */
7423 if (mode_cmd->depth == 15 && !HAS_PCH_SPLIT(dev))
7424 return -EINVAL;
7425 break;
7426
7427 case 24:
7428 case 32:
7429 break;
7430 default:
7431 return -EINVAL;
7432 }
7433
7434 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7435 if (ret) {
7436 DRM_ERROR("framebuffer init failed %d\n", ret);
7437 return ret;
7438 }
7439
7440 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
7441 intel_fb->obj = obj;
7442 return 0;
7443 }
7444
7445 static struct drm_framebuffer *
7446 intel_user_framebuffer_create(struct drm_device *dev,
7447 struct drm_file *filp,
7448 struct drm_mode_fb_cmd *mode_cmd)
7449 {
7450 struct drm_i915_gem_object *obj;
7451
7452 obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
7453 if (&obj->base == NULL)
7454 return ERR_PTR(-ENOENT);
7455
7456 return intel_framebuffer_create(dev, mode_cmd, obj);
7457 }
7458
7459 static const struct drm_mode_config_funcs intel_mode_funcs = {
7460 .fb_create = intel_user_framebuffer_create,
7461 .output_poll_changed = intel_fb_output_poll_changed,
7462 };
7463
7464 static struct drm_i915_gem_object *
7465 intel_alloc_context_page(struct drm_device *dev)
7466 {
7467 struct drm_i915_gem_object *ctx;
7468 int ret;
7469
7470 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
7471
7472 ctx = i915_gem_alloc_object(dev, 4096);
7473 if (!ctx) {
7474 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
7475 return NULL;
7476 }
7477
7478 ret = i915_gem_object_pin(ctx, 4096, true);
7479 if (ret) {
7480 DRM_ERROR("failed to pin power context: %d\n", ret);
7481 goto err_unref;
7482 }
7483
7484 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
7485 if (ret) {
7486 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
7487 goto err_unpin;
7488 }
7489
7490 return ctx;
7491
7492 err_unpin:
7493 i915_gem_object_unpin(ctx);
7494 err_unref:
7495 drm_gem_object_unreference(&ctx->base);
7496 mutex_unlock(&dev->struct_mutex);
7497 return NULL;
7498 }
7499
7500 bool ironlake_set_drps(struct drm_device *dev, u8 val)
7501 {
7502 struct drm_i915_private *dev_priv = dev->dev_private;
7503 u16 rgvswctl;
7504
7505 rgvswctl = I915_READ16(MEMSWCTL);
7506 if (rgvswctl & MEMCTL_CMD_STS) {
7507 DRM_DEBUG("gpu busy, RCS change rejected\n");
7508 return false; /* still busy with another command */
7509 }
7510
7511 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
7512 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
7513 I915_WRITE16(MEMSWCTL, rgvswctl);
7514 POSTING_READ16(MEMSWCTL);
7515
7516 rgvswctl |= MEMCTL_CMD_STS;
7517 I915_WRITE16(MEMSWCTL, rgvswctl);
7518
7519 return true;
7520 }
7521
7522 void ironlake_enable_drps(struct drm_device *dev)
7523 {
7524 struct drm_i915_private *dev_priv = dev->dev_private;
7525 u32 rgvmodectl = I915_READ(MEMMODECTL);
7526 u8 fmax, fmin, fstart, vstart;
7527
7528 /* Enable temp reporting */
7529 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
7530 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
7531
7532 /* 100ms RC evaluation intervals */
7533 I915_WRITE(RCUPEI, 100000);
7534 I915_WRITE(RCDNEI, 100000);
7535
7536 /* Set max/min thresholds to 90ms and 80ms respectively */
7537 I915_WRITE(RCBMAXAVG, 90000);
7538 I915_WRITE(RCBMINAVG, 80000);
7539
7540 I915_WRITE(MEMIHYST, 1);
7541
7542 /* Set up min, max, and cur for interrupt handling */
7543 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
7544 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
7545 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
7546 MEMMODE_FSTART_SHIFT;
7547
7548 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
7549 PXVFREQ_PX_SHIFT;
7550
7551 dev_priv->fmax = fmax; /* IPS callback will increase this */
7552 dev_priv->fstart = fstart;
7553
7554 dev_priv->max_delay = fstart;
7555 dev_priv->min_delay = fmin;
7556 dev_priv->cur_delay = fstart;
7557
7558 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
7559 fmax, fmin, fstart);
7560
7561 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
7562
7563 /*
7564 * Interrupts will be enabled in ironlake_irq_postinstall
7565 */
7566
7567 I915_WRITE(VIDSTART, vstart);
7568 POSTING_READ(VIDSTART);
7569
7570 rgvmodectl |= MEMMODE_SWMODE_EN;
7571 I915_WRITE(MEMMODECTL, rgvmodectl);
7572
7573 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
7574 DRM_ERROR("stuck trying to change perf mode\n");
7575 msleep(1);
7576
7577 ironlake_set_drps(dev, fstart);
7578
7579 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
7580 I915_READ(0x112e0);
7581 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
7582 dev_priv->last_count2 = I915_READ(0x112f4);
7583 getrawmonotonic(&dev_priv->last_time2);
7584 }
7585
7586 void ironlake_disable_drps(struct drm_device *dev)
7587 {
7588 struct drm_i915_private *dev_priv = dev->dev_private;
7589 u16 rgvswctl = I915_READ16(MEMSWCTL);
7590
7591 /* Ack interrupts, disable EFC interrupt */
7592 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
7593 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
7594 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
7595 I915_WRITE(DEIIR, DE_PCU_EVENT);
7596 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
7597
7598 /* Go back to the starting frequency */
7599 ironlake_set_drps(dev, dev_priv->fstart);
7600 msleep(1);
7601 rgvswctl |= MEMCTL_CMD_STS;
7602 I915_WRITE(MEMSWCTL, rgvswctl);
7603 msleep(1);
7604
7605 }
7606
7607 void gen6_set_rps(struct drm_device *dev, u8 val)
7608 {
7609 struct drm_i915_private *dev_priv = dev->dev_private;
7610 u32 swreq;
7611
7612 swreq = (val & 0x3ff) << 25;
7613 I915_WRITE(GEN6_RPNSWREQ, swreq);
7614 }
7615
7616 void gen6_disable_rps(struct drm_device *dev)
7617 {
7618 struct drm_i915_private *dev_priv = dev->dev_private;
7619
7620 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
7621 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
7622 I915_WRITE(GEN6_PMIER, 0);
7623
7624 spin_lock_irq(&dev_priv->rps_lock);
7625 dev_priv->pm_iir = 0;
7626 spin_unlock_irq(&dev_priv->rps_lock);
7627
7628 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
7629 }
7630
7631 static unsigned long intel_pxfreq(u32 vidfreq)
7632 {
7633 unsigned long freq;
7634 int div = (vidfreq & 0x3f0000) >> 16;
7635 int post = (vidfreq & 0x3000) >> 12;
7636 int pre = (vidfreq & 0x7);
7637
7638 if (!pre)
7639 return 0;
7640
7641 freq = ((div * 133333) / ((1<<post) * pre));
7642
7643 return freq;
7644 }
7645
7646 void intel_init_emon(struct drm_device *dev)
7647 {
7648 struct drm_i915_private *dev_priv = dev->dev_private;
7649 u32 lcfuse;
7650 u8 pxw[16];
7651 int i;
7652
7653 /* Disable to program */
7654 I915_WRITE(ECR, 0);
7655 POSTING_READ(ECR);
7656
7657 /* Program energy weights for various events */
7658 I915_WRITE(SDEW, 0x15040d00);
7659 I915_WRITE(CSIEW0, 0x007f0000);
7660 I915_WRITE(CSIEW1, 0x1e220004);
7661 I915_WRITE(CSIEW2, 0x04000004);
7662
7663 for (i = 0; i < 5; i++)
7664 I915_WRITE(PEW + (i * 4), 0);
7665 for (i = 0; i < 3; i++)
7666 I915_WRITE(DEW + (i * 4), 0);
7667
7668 /* Program P-state weights to account for frequency power adjustment */
7669 for (i = 0; i < 16; i++) {
7670 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
7671 unsigned long freq = intel_pxfreq(pxvidfreq);
7672 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
7673 PXVFREQ_PX_SHIFT;
7674 unsigned long val;
7675
7676 val = vid * vid;
7677 val *= (freq / 1000);
7678 val *= 255;
7679 val /= (127*127*900);
7680 if (val > 0xff)
7681 DRM_ERROR("bad pxval: %ld\n", val);
7682 pxw[i] = val;
7683 }
7684 /* Render standby states get 0 weight */
7685 pxw[14] = 0;
7686 pxw[15] = 0;
7687
7688 for (i = 0; i < 4; i++) {
7689 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
7690 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
7691 I915_WRITE(PXW + (i * 4), val);
7692 }
7693
7694 /* Adjust magic regs to magic values (more experimental results) */
7695 I915_WRITE(OGW0, 0);
7696 I915_WRITE(OGW1, 0);
7697 I915_WRITE(EG0, 0x00007f00);
7698 I915_WRITE(EG1, 0x0000000e);
7699 I915_WRITE(EG2, 0x000e0000);
7700 I915_WRITE(EG3, 0x68000300);
7701 I915_WRITE(EG4, 0x42000000);
7702 I915_WRITE(EG5, 0x00140031);
7703 I915_WRITE(EG6, 0);
7704 I915_WRITE(EG7, 0);
7705
7706 for (i = 0; i < 8; i++)
7707 I915_WRITE(PXWL + (i * 4), 0);
7708
7709 /* Enable PMON + select events */
7710 I915_WRITE(ECR, 0x80000019);
7711
7712 lcfuse = I915_READ(LCFUSE02);
7713
7714 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
7715 }
7716
7717 void gen6_enable_rps(struct drm_i915_private *dev_priv)
7718 {
7719 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
7720 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
7721 u32 pcu_mbox, rc6_mask = 0;
7722 int cur_freq, min_freq, max_freq;
7723 int i;
7724
7725 /* Here begins a magic sequence of register writes to enable
7726 * auto-downclocking.
7727 *
7728 * Perhaps there might be some value in exposing these to
7729 * userspace...
7730 */
7731 I915_WRITE(GEN6_RC_STATE, 0);
7732 mutex_lock(&dev_priv->dev->struct_mutex);
7733 gen6_gt_force_wake_get(dev_priv);
7734
7735 /* disable the counters and set deterministic thresholds */
7736 I915_WRITE(GEN6_RC_CONTROL, 0);
7737
7738 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
7739 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
7740 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
7741 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
7742 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
7743
7744 for (i = 0; i < I915_NUM_RINGS; i++)
7745 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
7746
7747 I915_WRITE(GEN6_RC_SLEEP, 0);
7748 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
7749 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
7750 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
7751 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
7752
7753 if (i915_enable_rc6)
7754 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
7755 GEN6_RC_CTL_RC6_ENABLE;
7756
7757 I915_WRITE(GEN6_RC_CONTROL,
7758 rc6_mask |
7759 GEN6_RC_CTL_EI_MODE(1) |
7760 GEN6_RC_CTL_HW_ENABLE);
7761
7762 I915_WRITE(GEN6_RPNSWREQ,
7763 GEN6_FREQUENCY(10) |
7764 GEN6_OFFSET(0) |
7765 GEN6_AGGRESSIVE_TURBO);
7766 I915_WRITE(GEN6_RC_VIDEO_FREQ,
7767 GEN6_FREQUENCY(12));
7768
7769 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7770 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
7771 18 << 24 |
7772 6 << 16);
7773 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
7774 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
7775 I915_WRITE(GEN6_RP_UP_EI, 100000);
7776 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
7777 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7778 I915_WRITE(GEN6_RP_CONTROL,
7779 GEN6_RP_MEDIA_TURBO |
7780 GEN6_RP_USE_NORMAL_FREQ |
7781 GEN6_RP_MEDIA_IS_GFX |
7782 GEN6_RP_ENABLE |
7783 GEN6_RP_UP_BUSY_AVG |
7784 GEN6_RP_DOWN_IDLE_CONT);
7785
7786 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7787 500))
7788 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7789
7790 I915_WRITE(GEN6_PCODE_DATA, 0);
7791 I915_WRITE(GEN6_PCODE_MAILBOX,
7792 GEN6_PCODE_READY |
7793 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7794 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7795 500))
7796 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7797
7798 min_freq = (rp_state_cap & 0xff0000) >> 16;
7799 max_freq = rp_state_cap & 0xff;
7800 cur_freq = (gt_perf_status & 0xff00) >> 8;
7801
7802 /* Check for overclock support */
7803 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7804 500))
7805 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7806 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
7807 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
7808 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7809 500))
7810 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7811 if (pcu_mbox & (1<<31)) { /* OC supported */
7812 max_freq = pcu_mbox & 0xff;
7813 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
7814 }
7815
7816 /* In units of 100MHz */
7817 dev_priv->max_delay = max_freq;
7818 dev_priv->min_delay = min_freq;
7819 dev_priv->cur_delay = cur_freq;
7820
7821 /* requires MSI enabled */
7822 I915_WRITE(GEN6_PMIER,
7823 GEN6_PM_MBOX_EVENT |
7824 GEN6_PM_THERMAL_EVENT |
7825 GEN6_PM_RP_DOWN_TIMEOUT |
7826 GEN6_PM_RP_UP_THRESHOLD |
7827 GEN6_PM_RP_DOWN_THRESHOLD |
7828 GEN6_PM_RP_UP_EI_EXPIRED |
7829 GEN6_PM_RP_DOWN_EI_EXPIRED);
7830 spin_lock_irq(&dev_priv->rps_lock);
7831 WARN_ON(dev_priv->pm_iir != 0);
7832 I915_WRITE(GEN6_PMIMR, 0);
7833 spin_unlock_irq(&dev_priv->rps_lock);
7834 /* enable all PM interrupts */
7835 I915_WRITE(GEN6_PMINTRMSK, 0);
7836
7837 gen6_gt_force_wake_put(dev_priv);
7838 mutex_unlock(&dev_priv->dev->struct_mutex);
7839 }
7840
7841 void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
7842 {
7843 int min_freq = 15;
7844 int gpu_freq, ia_freq, max_ia_freq;
7845 int scaling_factor = 180;
7846
7847 max_ia_freq = cpufreq_quick_get_max(0);
7848 /*
7849 * Default to measured freq if none found, PCU will ensure we don't go
7850 * over
7851 */
7852 if (!max_ia_freq)
7853 max_ia_freq = tsc_khz;
7854
7855 /* Convert from kHz to MHz */
7856 max_ia_freq /= 1000;
7857
7858 mutex_lock(&dev_priv->dev->struct_mutex);
7859
7860 /*
7861 * For each potential GPU frequency, load a ring frequency we'd like
7862 * to use for memory access. We do this by specifying the IA frequency
7863 * the PCU should use as a reference to determine the ring frequency.
7864 */
7865 for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
7866 gpu_freq--) {
7867 int diff = dev_priv->max_delay - gpu_freq;
7868
7869 /*
7870 * For GPU frequencies less than 750MHz, just use the lowest
7871 * ring freq.
7872 */
7873 if (gpu_freq < min_freq)
7874 ia_freq = 800;
7875 else
7876 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
7877 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
7878
7879 I915_WRITE(GEN6_PCODE_DATA,
7880 (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
7881 gpu_freq);
7882 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
7883 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7884 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
7885 GEN6_PCODE_READY) == 0, 10)) {
7886 DRM_ERROR("pcode write of freq table timed out\n");
7887 continue;
7888 }
7889 }
7890
7891 mutex_unlock(&dev_priv->dev->struct_mutex);
7892 }
7893
7894 static void ironlake_init_clock_gating(struct drm_device *dev)
7895 {
7896 struct drm_i915_private *dev_priv = dev->dev_private;
7897 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7898
7899 /* Required for FBC */
7900 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
7901 DPFCRUNIT_CLOCK_GATE_DISABLE |
7902 DPFDUNIT_CLOCK_GATE_DISABLE;
7903 /* Required for CxSR */
7904 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
7905
7906 I915_WRITE(PCH_3DCGDIS0,
7907 MARIUNIT_CLOCK_GATE_DISABLE |
7908 SVSMUNIT_CLOCK_GATE_DISABLE);
7909 I915_WRITE(PCH_3DCGDIS1,
7910 VFMUNIT_CLOCK_GATE_DISABLE);
7911
7912 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7913
7914 /*
7915 * According to the spec the following bits should be set in
7916 * order to enable memory self-refresh
7917 * The bit 22/21 of 0x42004
7918 * The bit 5 of 0x42020
7919 * The bit 15 of 0x45000
7920 */
7921 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7922 (I915_READ(ILK_DISPLAY_CHICKEN2) |
7923 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
7924 I915_WRITE(ILK_DSPCLK_GATE,
7925 (I915_READ(ILK_DSPCLK_GATE) |
7926 ILK_DPARB_CLK_GATE));
7927 I915_WRITE(DISP_ARB_CTL,
7928 (I915_READ(DISP_ARB_CTL) |
7929 DISP_FBC_WM_DIS));
7930 I915_WRITE(WM3_LP_ILK, 0);
7931 I915_WRITE(WM2_LP_ILK, 0);
7932 I915_WRITE(WM1_LP_ILK, 0);
7933
7934 /*
7935 * Based on the document from hardware guys the following bits
7936 * should be set unconditionally in order to enable FBC.
7937 * The bit 22 of 0x42000
7938 * The bit 22 of 0x42004
7939 * The bit 7,8,9 of 0x42020.
7940 */
7941 if (IS_IRONLAKE_M(dev)) {
7942 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7943 I915_READ(ILK_DISPLAY_CHICKEN1) |
7944 ILK_FBCQ_DIS);
7945 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7946 I915_READ(ILK_DISPLAY_CHICKEN2) |
7947 ILK_DPARB_GATE);
7948 I915_WRITE(ILK_DSPCLK_GATE,
7949 I915_READ(ILK_DSPCLK_GATE) |
7950 ILK_DPFC_DIS1 |
7951 ILK_DPFC_DIS2 |
7952 ILK_CLK_FBC);
7953 }
7954
7955 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7956 I915_READ(ILK_DISPLAY_CHICKEN2) |
7957 ILK_ELPIN_409_SELECT);
7958 I915_WRITE(_3D_CHICKEN2,
7959 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
7960 _3D_CHICKEN2_WM_READ_PIPELINED);
7961 }
7962
7963 static void gen6_init_clock_gating(struct drm_device *dev)
7964 {
7965 struct drm_i915_private *dev_priv = dev->dev_private;
7966 int pipe;
7967 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7968
7969 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7970
7971 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7972 I915_READ(ILK_DISPLAY_CHICKEN2) |
7973 ILK_ELPIN_409_SELECT);
7974
7975 I915_WRITE(WM3_LP_ILK, 0);
7976 I915_WRITE(WM2_LP_ILK, 0);
7977 I915_WRITE(WM1_LP_ILK, 0);
7978
7979 /*
7980 * According to the spec the following bits should be
7981 * set in order to enable memory self-refresh and fbc:
7982 * The bit21 and bit22 of 0x42000
7983 * The bit21 and bit22 of 0x42004
7984 * The bit5 and bit7 of 0x42020
7985 * The bit14 of 0x70180
7986 * The bit14 of 0x71180
7987 */
7988 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7989 I915_READ(ILK_DISPLAY_CHICKEN1) |
7990 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7991 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7992 I915_READ(ILK_DISPLAY_CHICKEN2) |
7993 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7994 I915_WRITE(ILK_DSPCLK_GATE,
7995 I915_READ(ILK_DSPCLK_GATE) |
7996 ILK_DPARB_CLK_GATE |
7997 ILK_DPFD_CLK_GATE);
7998
7999 for_each_pipe(pipe) {
8000 I915_WRITE(DSPCNTR(pipe),
8001 I915_READ(DSPCNTR(pipe)) |
8002 DISPPLANE_TRICKLE_FEED_DISABLE);
8003 intel_flush_display_plane(dev_priv, pipe);
8004 }
8005 }
8006
8007 static void ivybridge_init_clock_gating(struct drm_device *dev)
8008 {
8009 struct drm_i915_private *dev_priv = dev->dev_private;
8010 int pipe;
8011 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8012
8013 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8014
8015 I915_WRITE(WM3_LP_ILK, 0);
8016 I915_WRITE(WM2_LP_ILK, 0);
8017 I915_WRITE(WM1_LP_ILK, 0);
8018
8019 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
8020
8021 for_each_pipe(pipe) {
8022 I915_WRITE(DSPCNTR(pipe),
8023 I915_READ(DSPCNTR(pipe)) |
8024 DISPPLANE_TRICKLE_FEED_DISABLE);
8025 intel_flush_display_plane(dev_priv, pipe);
8026 }
8027 }
8028
8029 static void g4x_init_clock_gating(struct drm_device *dev)
8030 {
8031 struct drm_i915_private *dev_priv = dev->dev_private;
8032 uint32_t dspclk_gate;
8033
8034 I915_WRITE(RENCLK_GATE_D1, 0);
8035 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
8036 GS_UNIT_CLOCK_GATE_DISABLE |
8037 CL_UNIT_CLOCK_GATE_DISABLE);
8038 I915_WRITE(RAMCLK_GATE_D, 0);
8039 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
8040 OVRUNIT_CLOCK_GATE_DISABLE |
8041 OVCUNIT_CLOCK_GATE_DISABLE;
8042 if (IS_GM45(dev))
8043 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
8044 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
8045 }
8046
8047 static void crestline_init_clock_gating(struct drm_device *dev)
8048 {
8049 struct drm_i915_private *dev_priv = dev->dev_private;
8050
8051 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
8052 I915_WRITE(RENCLK_GATE_D2, 0);
8053 I915_WRITE(DSPCLK_GATE_D, 0);
8054 I915_WRITE(RAMCLK_GATE_D, 0);
8055 I915_WRITE16(DEUC, 0);
8056 }
8057
8058 static void broadwater_init_clock_gating(struct drm_device *dev)
8059 {
8060 struct drm_i915_private *dev_priv = dev->dev_private;
8061
8062 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
8063 I965_RCC_CLOCK_GATE_DISABLE |
8064 I965_RCPB_CLOCK_GATE_DISABLE |
8065 I965_ISC_CLOCK_GATE_DISABLE |
8066 I965_FBC_CLOCK_GATE_DISABLE);
8067 I915_WRITE(RENCLK_GATE_D2, 0);
8068 }
8069
8070 static void gen3_init_clock_gating(struct drm_device *dev)
8071 {
8072 struct drm_i915_private *dev_priv = dev->dev_private;
8073 u32 dstate = I915_READ(D_STATE);
8074
8075 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
8076 DSTATE_DOT_CLOCK_GATING;
8077 I915_WRITE(D_STATE, dstate);
8078 }
8079
8080 static void i85x_init_clock_gating(struct drm_device *dev)
8081 {
8082 struct drm_i915_private *dev_priv = dev->dev_private;
8083
8084 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
8085 }
8086
8087 static void i830_init_clock_gating(struct drm_device *dev)
8088 {
8089 struct drm_i915_private *dev_priv = dev->dev_private;
8090
8091 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
8092 }
8093
8094 static void ibx_init_clock_gating(struct drm_device *dev)
8095 {
8096 struct drm_i915_private *dev_priv = dev->dev_private;
8097
8098 /*
8099 * On Ibex Peak and Cougar Point, we need to disable clock
8100 * gating for the panel power sequencer or it will fail to
8101 * start up when no ports are active.
8102 */
8103 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8104 }
8105
8106 static void cpt_init_clock_gating(struct drm_device *dev)
8107 {
8108 struct drm_i915_private *dev_priv = dev->dev_private;
8109 int pipe;
8110
8111 /*
8112 * On Ibex Peak and Cougar Point, we need to disable clock
8113 * gating for the panel power sequencer or it will fail to
8114 * start up when no ports are active.
8115 */
8116 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8117 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8118 DPLS_EDP_PPS_FIX_DIS);
8119 /* Without this, mode sets may fail silently on FDI */
8120 for_each_pipe(pipe)
8121 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
8122 }
8123
8124 static void ironlake_teardown_rc6(struct drm_device *dev)
8125 {
8126 struct drm_i915_private *dev_priv = dev->dev_private;
8127
8128 if (dev_priv->renderctx) {
8129 i915_gem_object_unpin(dev_priv->renderctx);
8130 drm_gem_object_unreference(&dev_priv->renderctx->base);
8131 dev_priv->renderctx = NULL;
8132 }
8133
8134 if (dev_priv->pwrctx) {
8135 i915_gem_object_unpin(dev_priv->pwrctx);
8136 drm_gem_object_unreference(&dev_priv->pwrctx->base);
8137 dev_priv->pwrctx = NULL;
8138 }
8139 }
8140
8141 static void ironlake_disable_rc6(struct drm_device *dev)
8142 {
8143 struct drm_i915_private *dev_priv = dev->dev_private;
8144
8145 if (I915_READ(PWRCTXA)) {
8146 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
8147 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
8148 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
8149 50);
8150
8151 I915_WRITE(PWRCTXA, 0);
8152 POSTING_READ(PWRCTXA);
8153
8154 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8155 POSTING_READ(RSTDBYCTL);
8156 }
8157
8158 ironlake_teardown_rc6(dev);
8159 }
8160
8161 static int ironlake_setup_rc6(struct drm_device *dev)
8162 {
8163 struct drm_i915_private *dev_priv = dev->dev_private;
8164
8165 if (dev_priv->renderctx == NULL)
8166 dev_priv->renderctx = intel_alloc_context_page(dev);
8167 if (!dev_priv->renderctx)
8168 return -ENOMEM;
8169
8170 if (dev_priv->pwrctx == NULL)
8171 dev_priv->pwrctx = intel_alloc_context_page(dev);
8172 if (!dev_priv->pwrctx) {
8173 ironlake_teardown_rc6(dev);
8174 return -ENOMEM;
8175 }
8176
8177 return 0;
8178 }
8179
8180 void ironlake_enable_rc6(struct drm_device *dev)
8181 {
8182 struct drm_i915_private *dev_priv = dev->dev_private;
8183 int ret;
8184
8185 /* rc6 disabled by default due to repeated reports of hanging during
8186 * boot and resume.
8187 */
8188 if (!i915_enable_rc6)
8189 return;
8190
8191 mutex_lock(&dev->struct_mutex);
8192 ret = ironlake_setup_rc6(dev);
8193 if (ret) {
8194 mutex_unlock(&dev->struct_mutex);
8195 return;
8196 }
8197
8198 /*
8199 * GPU can automatically power down the render unit if given a page
8200 * to save state.
8201 */
8202 ret = BEGIN_LP_RING(6);
8203 if (ret) {
8204 ironlake_teardown_rc6(dev);
8205 mutex_unlock(&dev->struct_mutex);
8206 return;
8207 }
8208
8209 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
8210 OUT_RING(MI_SET_CONTEXT);
8211 OUT_RING(dev_priv->renderctx->gtt_offset |
8212 MI_MM_SPACE_GTT |
8213 MI_SAVE_EXT_STATE_EN |
8214 MI_RESTORE_EXT_STATE_EN |
8215 MI_RESTORE_INHIBIT);
8216 OUT_RING(MI_SUSPEND_FLUSH);
8217 OUT_RING(MI_NOOP);
8218 OUT_RING(MI_FLUSH);
8219 ADVANCE_LP_RING();
8220
8221 /*
8222 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
8223 * does an implicit flush, combined with MI_FLUSH above, it should be
8224 * safe to assume that renderctx is valid
8225 */
8226 ret = intel_wait_ring_idle(LP_RING(dev_priv));
8227 if (ret) {
8228 DRM_ERROR("failed to enable ironlake power power savings\n");
8229 ironlake_teardown_rc6(dev);
8230 mutex_unlock(&dev->struct_mutex);
8231 return;
8232 }
8233
8234 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
8235 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8236 mutex_unlock(&dev->struct_mutex);
8237 }
8238
8239 void intel_init_clock_gating(struct drm_device *dev)
8240 {
8241 struct drm_i915_private *dev_priv = dev->dev_private;
8242
8243 dev_priv->display.init_clock_gating(dev);
8244
8245 if (dev_priv->display.init_pch_clock_gating)
8246 dev_priv->display.init_pch_clock_gating(dev);
8247 }
8248
8249 /* Set up chip specific display functions */
8250 static void intel_init_display(struct drm_device *dev)
8251 {
8252 struct drm_i915_private *dev_priv = dev->dev_private;
8253
8254 /* We always want a DPMS function */
8255 if (HAS_PCH_SPLIT(dev)) {
8256 dev_priv->display.dpms = ironlake_crtc_dpms;
8257 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8258 dev_priv->display.update_plane = ironlake_update_plane;
8259 } else {
8260 dev_priv->display.dpms = i9xx_crtc_dpms;
8261 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8262 dev_priv->display.update_plane = i9xx_update_plane;
8263 }
8264
8265 if (I915_HAS_FBC(dev)) {
8266 if (HAS_PCH_SPLIT(dev)) {
8267 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
8268 dev_priv->display.enable_fbc = ironlake_enable_fbc;
8269 dev_priv->display.disable_fbc = ironlake_disable_fbc;
8270 } else if (IS_GM45(dev)) {
8271 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
8272 dev_priv->display.enable_fbc = g4x_enable_fbc;
8273 dev_priv->display.disable_fbc = g4x_disable_fbc;
8274 } else if (IS_CRESTLINE(dev)) {
8275 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
8276 dev_priv->display.enable_fbc = i8xx_enable_fbc;
8277 dev_priv->display.disable_fbc = i8xx_disable_fbc;
8278 }
8279 /* 855GM needs testing */
8280 }
8281
8282 /* Returns the core display clock speed */
8283 if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8284 dev_priv->display.get_display_clock_speed =
8285 i945_get_display_clock_speed;
8286 else if (IS_I915G(dev))
8287 dev_priv->display.get_display_clock_speed =
8288 i915_get_display_clock_speed;
8289 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8290 dev_priv->display.get_display_clock_speed =
8291 i9xx_misc_get_display_clock_speed;
8292 else if (IS_I915GM(dev))
8293 dev_priv->display.get_display_clock_speed =
8294 i915gm_get_display_clock_speed;
8295 else if (IS_I865G(dev))
8296 dev_priv->display.get_display_clock_speed =
8297 i865_get_display_clock_speed;
8298 else if (IS_I85X(dev))
8299 dev_priv->display.get_display_clock_speed =
8300 i855_get_display_clock_speed;
8301 else /* 852, 830 */
8302 dev_priv->display.get_display_clock_speed =
8303 i830_get_display_clock_speed;
8304
8305 /* For FIFO watermark updates */
8306 if (HAS_PCH_SPLIT(dev)) {
8307 if (HAS_PCH_IBX(dev))
8308 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
8309 else if (HAS_PCH_CPT(dev))
8310 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
8311
8312 if (IS_GEN5(dev)) {
8313 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
8314 dev_priv->display.update_wm = ironlake_update_wm;
8315 else {
8316 DRM_DEBUG_KMS("Failed to get proper latency. "
8317 "Disable CxSR\n");
8318 dev_priv->display.update_wm = NULL;
8319 }
8320 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8321 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
8322 dev_priv->display.write_eld = ironlake_write_eld;
8323 } else if (IS_GEN6(dev)) {
8324 if (SNB_READ_WM0_LATENCY()) {
8325 dev_priv->display.update_wm = sandybridge_update_wm;
8326 } else {
8327 DRM_DEBUG_KMS("Failed to read display plane latency. "
8328 "Disable CxSR\n");
8329 dev_priv->display.update_wm = NULL;
8330 }
8331 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8332 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
8333 dev_priv->display.write_eld = ironlake_write_eld;
8334 } else if (IS_IVYBRIDGE(dev)) {
8335 /* FIXME: detect B0+ stepping and use auto training */
8336 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8337 if (SNB_READ_WM0_LATENCY()) {
8338 dev_priv->display.update_wm = sandybridge_update_wm;
8339 } else {
8340 DRM_DEBUG_KMS("Failed to read display plane latency. "
8341 "Disable CxSR\n");
8342 dev_priv->display.update_wm = NULL;
8343 }
8344 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
8345 dev_priv->display.write_eld = ironlake_write_eld;
8346 } else
8347 dev_priv->display.update_wm = NULL;
8348 } else if (IS_PINEVIEW(dev)) {
8349 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
8350 dev_priv->is_ddr3,
8351 dev_priv->fsb_freq,
8352 dev_priv->mem_freq)) {
8353 DRM_INFO("failed to find known CxSR latency "
8354 "(found ddr%s fsb freq %d, mem freq %d), "
8355 "disabling CxSR\n",
8356 (dev_priv->is_ddr3 == 1) ? "3" : "2",
8357 dev_priv->fsb_freq, dev_priv->mem_freq);
8358 /* Disable CxSR and never update its watermark again */
8359 pineview_disable_cxsr(dev);
8360 dev_priv->display.update_wm = NULL;
8361 } else
8362 dev_priv->display.update_wm = pineview_update_wm;
8363 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8364 } else if (IS_G4X(dev)) {
8365 dev_priv->display.write_eld = g4x_write_eld;
8366 dev_priv->display.update_wm = g4x_update_wm;
8367 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
8368 } else if (IS_GEN4(dev)) {
8369 dev_priv->display.update_wm = i965_update_wm;
8370 if (IS_CRESTLINE(dev))
8371 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
8372 else if (IS_BROADWATER(dev))
8373 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
8374 } else if (IS_GEN3(dev)) {
8375 dev_priv->display.update_wm = i9xx_update_wm;
8376 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
8377 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8378 } else if (IS_I865G(dev)) {
8379 dev_priv->display.update_wm = i830_update_wm;
8380 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8381 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8382 } else if (IS_I85X(dev)) {
8383 dev_priv->display.update_wm = i9xx_update_wm;
8384 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
8385 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8386 } else {
8387 dev_priv->display.update_wm = i830_update_wm;
8388 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8389 if (IS_845G(dev))
8390 dev_priv->display.get_fifo_size = i845_get_fifo_size;
8391 else
8392 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8393 }
8394
8395 /* Default just returns -ENODEV to indicate unsupported */
8396 dev_priv->display.queue_flip = intel_default_queue_flip;
8397
8398 switch (INTEL_INFO(dev)->gen) {
8399 case 2:
8400 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8401 break;
8402
8403 case 3:
8404 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8405 break;
8406
8407 case 4:
8408 case 5:
8409 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8410 break;
8411
8412 case 6:
8413 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8414 break;
8415 case 7:
8416 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8417 break;
8418 }
8419 }
8420
8421 /*
8422 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8423 * resume, or other times. This quirk makes sure that's the case for
8424 * affected systems.
8425 */
8426 static void quirk_pipea_force(struct drm_device *dev)
8427 {
8428 struct drm_i915_private *dev_priv = dev->dev_private;
8429
8430 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8431 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
8432 }
8433
8434 /*
8435 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8436 */
8437 static void quirk_ssc_force_disable(struct drm_device *dev)
8438 {
8439 struct drm_i915_private *dev_priv = dev->dev_private;
8440 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8441 }
8442
8443 struct intel_quirk {
8444 int device;
8445 int subsystem_vendor;
8446 int subsystem_device;
8447 void (*hook)(struct drm_device *dev);
8448 };
8449
8450 struct intel_quirk intel_quirks[] = {
8451 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
8452 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
8453 /* HP Mini needs pipe A force quirk (LP: #322104) */
8454 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8455
8456 /* Thinkpad R31 needs pipe A force quirk */
8457 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
8458 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8459 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8460
8461 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
8462 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
8463 /* ThinkPad X40 needs pipe A force quirk */
8464
8465 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8466 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8467
8468 /* 855 & before need to leave pipe A & dpll A up */
8469 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8470 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8471
8472 /* Lenovo U160 cannot use SSC on LVDS */
8473 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8474
8475 /* Sony Vaio Y cannot use SSC on LVDS */
8476 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8477 };
8478
8479 static void intel_init_quirks(struct drm_device *dev)
8480 {
8481 struct pci_dev *d = dev->pdev;
8482 int i;
8483
8484 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8485 struct intel_quirk *q = &intel_quirks[i];
8486
8487 if (d->device == q->device &&
8488 (d->subsystem_vendor == q->subsystem_vendor ||
8489 q->subsystem_vendor == PCI_ANY_ID) &&
8490 (d->subsystem_device == q->subsystem_device ||
8491 q->subsystem_device == PCI_ANY_ID))
8492 q->hook(dev);
8493 }
8494 }
8495
8496 /* Disable the VGA plane that we never use */
8497 static void i915_disable_vga(struct drm_device *dev)
8498 {
8499 struct drm_i915_private *dev_priv = dev->dev_private;
8500 u8 sr1;
8501 u32 vga_reg;
8502
8503 if (HAS_PCH_SPLIT(dev))
8504 vga_reg = CPU_VGACNTRL;
8505 else
8506 vga_reg = VGACNTRL;
8507
8508 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8509 outb(1, VGA_SR_INDEX);
8510 sr1 = inb(VGA_SR_DATA);
8511 outb(sr1 | 1<<5, VGA_SR_DATA);
8512 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8513 udelay(300);
8514
8515 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8516 POSTING_READ(vga_reg);
8517 }
8518
8519 void intel_modeset_init(struct drm_device *dev)
8520 {
8521 struct drm_i915_private *dev_priv = dev->dev_private;
8522 int i;
8523
8524 drm_mode_config_init(dev);
8525
8526 dev->mode_config.min_width = 0;
8527 dev->mode_config.min_height = 0;
8528
8529 dev->mode_config.funcs = (void *)&intel_mode_funcs;
8530
8531 intel_init_quirks(dev);
8532
8533 intel_init_display(dev);
8534
8535 if (IS_GEN2(dev)) {
8536 dev->mode_config.max_width = 2048;
8537 dev->mode_config.max_height = 2048;
8538 } else if (IS_GEN3(dev)) {
8539 dev->mode_config.max_width = 4096;
8540 dev->mode_config.max_height = 4096;
8541 } else {
8542 dev->mode_config.max_width = 8192;
8543 dev->mode_config.max_height = 8192;
8544 }
8545 dev->mode_config.fb_base = dev->agp->base;
8546
8547 DRM_DEBUG_KMS("%d display pipe%s available.\n",
8548 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8549
8550 for (i = 0; i < dev_priv->num_pipe; i++) {
8551 intel_crtc_init(dev, i);
8552 }
8553
8554 /* Just disable it once at startup */
8555 i915_disable_vga(dev);
8556 intel_setup_outputs(dev);
8557
8558 intel_init_clock_gating(dev);
8559
8560 if (IS_IRONLAKE_M(dev)) {
8561 ironlake_enable_drps(dev);
8562 intel_init_emon(dev);
8563 }
8564
8565 if (IS_GEN6(dev) || IS_GEN7(dev)) {
8566 gen6_enable_rps(dev_priv);
8567 gen6_update_ring_freq(dev_priv);
8568 }
8569
8570 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
8571 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
8572 (unsigned long)dev);
8573 }
8574
8575 void intel_modeset_gem_init(struct drm_device *dev)
8576 {
8577 if (IS_IRONLAKE_M(dev))
8578 ironlake_enable_rc6(dev);
8579
8580 intel_setup_overlay(dev);
8581 }
8582
8583 void intel_modeset_cleanup(struct drm_device *dev)
8584 {
8585 struct drm_i915_private *dev_priv = dev->dev_private;
8586 struct drm_crtc *crtc;
8587 struct intel_crtc *intel_crtc;
8588
8589 drm_kms_helper_poll_fini(dev);
8590 mutex_lock(&dev->struct_mutex);
8591
8592 intel_unregister_dsm_handler();
8593
8594
8595 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8596 /* Skip inactive CRTCs */
8597 if (!crtc->fb)
8598 continue;
8599
8600 intel_crtc = to_intel_crtc(crtc);
8601 intel_increase_pllclock(crtc);
8602 }
8603
8604 intel_disable_fbc(dev);
8605
8606 if (IS_IRONLAKE_M(dev))
8607 ironlake_disable_drps(dev);
8608 if (IS_GEN6(dev) || IS_GEN7(dev))
8609 gen6_disable_rps(dev);
8610
8611 if (IS_IRONLAKE_M(dev))
8612 ironlake_disable_rc6(dev);
8613
8614 mutex_unlock(&dev->struct_mutex);
8615
8616 /* Disable the irq before mode object teardown, for the irq might
8617 * enqueue unpin/hotplug work. */
8618 drm_irq_uninstall(dev);
8619 cancel_work_sync(&dev_priv->hotplug_work);
8620
8621 /* flush any delayed tasks or pending work */
8622 flush_scheduled_work();
8623
8624 /* Shut off idle work before the crtcs get freed. */
8625 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8626 intel_crtc = to_intel_crtc(crtc);
8627 del_timer_sync(&intel_crtc->idle_timer);
8628 }
8629 del_timer_sync(&dev_priv->idle_timer);
8630 cancel_work_sync(&dev_priv->idle_work);
8631
8632 drm_mode_config_cleanup(dev);
8633 }
8634
8635 /*
8636 * Return which encoder is currently attached for connector.
8637 */
8638 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
8639 {
8640 return &intel_attached_encoder(connector)->base;
8641 }
8642
8643 void intel_connector_attach_encoder(struct intel_connector *connector,
8644 struct intel_encoder *encoder)
8645 {
8646 connector->encoder = encoder;
8647 drm_mode_connector_attach_encoder(&connector->base,
8648 &encoder->base);
8649 }
8650
8651 /*
8652 * set vga decode state - true == enable VGA decode
8653 */
8654 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8655 {
8656 struct drm_i915_private *dev_priv = dev->dev_private;
8657 u16 gmch_ctrl;
8658
8659 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8660 if (state)
8661 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8662 else
8663 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8664 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8665 return 0;
8666 }
8667
8668 #ifdef CONFIG_DEBUG_FS
8669 #include <linux/seq_file.h>
8670
8671 struct intel_display_error_state {
8672 struct intel_cursor_error_state {
8673 u32 control;
8674 u32 position;
8675 u32 base;
8676 u32 size;
8677 } cursor[2];
8678
8679 struct intel_pipe_error_state {
8680 u32 conf;
8681 u32 source;
8682
8683 u32 htotal;
8684 u32 hblank;
8685 u32 hsync;
8686 u32 vtotal;
8687 u32 vblank;
8688 u32 vsync;
8689 } pipe[2];
8690
8691 struct intel_plane_error_state {
8692 u32 control;
8693 u32 stride;
8694 u32 size;
8695 u32 pos;
8696 u32 addr;
8697 u32 surface;
8698 u32 tile_offset;
8699 } plane[2];
8700 };
8701
8702 struct intel_display_error_state *
8703 intel_display_capture_error_state(struct drm_device *dev)
8704 {
8705 drm_i915_private_t *dev_priv = dev->dev_private;
8706 struct intel_display_error_state *error;
8707 int i;
8708
8709 error = kmalloc(sizeof(*error), GFP_ATOMIC);
8710 if (error == NULL)
8711 return NULL;
8712
8713 for (i = 0; i < 2; i++) {
8714 error->cursor[i].control = I915_READ(CURCNTR(i));
8715 error->cursor[i].position = I915_READ(CURPOS(i));
8716 error->cursor[i].base = I915_READ(CURBASE(i));
8717
8718 error->plane[i].control = I915_READ(DSPCNTR(i));
8719 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8720 error->plane[i].size = I915_READ(DSPSIZE(i));
8721 error->plane[i].pos = I915_READ(DSPPOS(i));
8722 error->plane[i].addr = I915_READ(DSPADDR(i));
8723 if (INTEL_INFO(dev)->gen >= 4) {
8724 error->plane[i].surface = I915_READ(DSPSURF(i));
8725 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8726 }
8727
8728 error->pipe[i].conf = I915_READ(PIPECONF(i));
8729 error->pipe[i].source = I915_READ(PIPESRC(i));
8730 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8731 error->pipe[i].hblank = I915_READ(HBLANK(i));
8732 error->pipe[i].hsync = I915_READ(HSYNC(i));
8733 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8734 error->pipe[i].vblank = I915_READ(VBLANK(i));
8735 error->pipe[i].vsync = I915_READ(VSYNC(i));
8736 }
8737
8738 return error;
8739 }
8740
8741 void
8742 intel_display_print_error_state(struct seq_file *m,
8743 struct drm_device *dev,
8744 struct intel_display_error_state *error)
8745 {
8746 int i;
8747
8748 for (i = 0; i < 2; i++) {
8749 seq_printf(m, "Pipe [%d]:\n", i);
8750 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
8751 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
8752 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
8753 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
8754 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
8755 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
8756 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
8757 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
8758
8759 seq_printf(m, "Plane [%d]:\n", i);
8760 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
8761 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
8762 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
8763 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
8764 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
8765 if (INTEL_INFO(dev)->gen >= 4) {
8766 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
8767 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
8768 }
8769
8770 seq_printf(m, "Cursor [%d]:\n", i);
8771 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
8772 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
8773 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
8774 }
8775 }
8776 #endif
Linux kernel - Deliverables
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