2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_rect.h>
44 #include <linux/dma_remapping.h>
46 /* Primary plane formats supported by all gen */
47 #define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_XRGB8888, \
53 /* Primary plane formats for gen <= 3 */
54 static const uint32_t intel_primary_formats_gen2
[] = {
55 COMMON_PRIMARY_FORMATS
,
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t intel_primary_formats_gen4
[] = {
62 COMMON_PRIMARY_FORMATS
, \
65 DRM_FORMAT_XRGB2101010
,
66 DRM_FORMAT_ARGB2101010
,
67 DRM_FORMAT_XBGR2101010
,
68 DRM_FORMAT_ABGR2101010
,
72 static const uint32_t intel_cursor_formats
[] = {
76 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
78 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
79 struct intel_crtc_config
*pipe_config
);
80 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
81 struct intel_crtc_config
*pipe_config
);
83 static int intel_set_mode(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
84 int x
, int y
, struct drm_framebuffer
*old_fb
);
85 static int intel_framebuffer_init(struct drm_device
*dev
,
86 struct intel_framebuffer
*ifb
,
87 struct drm_mode_fb_cmd2
*mode_cmd
,
88 struct drm_i915_gem_object
*obj
);
89 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
);
90 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
);
91 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
92 struct intel_link_m_n
*m_n
,
93 struct intel_link_m_n
*m2_n2
);
94 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
);
95 static void haswell_set_pipeconf(struct drm_crtc
*crtc
);
96 static void intel_set_pipe_csc(struct drm_crtc
*crtc
);
97 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
98 const struct intel_crtc_config
*pipe_config
);
99 static void chv_prepare_pll(struct intel_crtc
*crtc
,
100 const struct intel_crtc_config
*pipe_config
);
102 static struct intel_encoder
*intel_find_encoder(struct intel_connector
*connector
, int pipe
)
104 if (!connector
->mst_port
)
105 return connector
->encoder
;
107 return &connector
->mst_port
->mst_encoders
[pipe
]->base
;
116 int p2_slow
, p2_fast
;
119 typedef struct intel_limit intel_limit_t
;
121 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
126 intel_pch_rawclk(struct drm_device
*dev
)
128 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
130 WARN_ON(!HAS_PCH_SPLIT(dev
));
132 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
135 static inline u32
/* units of 100MHz */
136 intel_fdi_link_freq(struct drm_device
*dev
)
139 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
140 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
145 static const intel_limit_t intel_limits_i8xx_dac
= {
146 .dot
= { .min
= 25000, .max
= 350000 },
147 .vco
= { .min
= 908000, .max
= 1512000 },
148 .n
= { .min
= 2, .max
= 16 },
149 .m
= { .min
= 96, .max
= 140 },
150 .m1
= { .min
= 18, .max
= 26 },
151 .m2
= { .min
= 6, .max
= 16 },
152 .p
= { .min
= 4, .max
= 128 },
153 .p1
= { .min
= 2, .max
= 33 },
154 .p2
= { .dot_limit
= 165000,
155 .p2_slow
= 4, .p2_fast
= 2 },
158 static const intel_limit_t intel_limits_i8xx_dvo
= {
159 .dot
= { .min
= 25000, .max
= 350000 },
160 .vco
= { .min
= 908000, .max
= 1512000 },
161 .n
= { .min
= 2, .max
= 16 },
162 .m
= { .min
= 96, .max
= 140 },
163 .m1
= { .min
= 18, .max
= 26 },
164 .m2
= { .min
= 6, .max
= 16 },
165 .p
= { .min
= 4, .max
= 128 },
166 .p1
= { .min
= 2, .max
= 33 },
167 .p2
= { .dot_limit
= 165000,
168 .p2_slow
= 4, .p2_fast
= 4 },
171 static const intel_limit_t intel_limits_i8xx_lvds
= {
172 .dot
= { .min
= 25000, .max
= 350000 },
173 .vco
= { .min
= 908000, .max
= 1512000 },
174 .n
= { .min
= 2, .max
= 16 },
175 .m
= { .min
= 96, .max
= 140 },
176 .m1
= { .min
= 18, .max
= 26 },
177 .m2
= { .min
= 6, .max
= 16 },
178 .p
= { .min
= 4, .max
= 128 },
179 .p1
= { .min
= 1, .max
= 6 },
180 .p2
= { .dot_limit
= 165000,
181 .p2_slow
= 14, .p2_fast
= 7 },
184 static const intel_limit_t intel_limits_i9xx_sdvo
= {
185 .dot
= { .min
= 20000, .max
= 400000 },
186 .vco
= { .min
= 1400000, .max
= 2800000 },
187 .n
= { .min
= 1, .max
= 6 },
188 .m
= { .min
= 70, .max
= 120 },
189 .m1
= { .min
= 8, .max
= 18 },
190 .m2
= { .min
= 3, .max
= 7 },
191 .p
= { .min
= 5, .max
= 80 },
192 .p1
= { .min
= 1, .max
= 8 },
193 .p2
= { .dot_limit
= 200000,
194 .p2_slow
= 10, .p2_fast
= 5 },
197 static const intel_limit_t intel_limits_i9xx_lvds
= {
198 .dot
= { .min
= 20000, .max
= 400000 },
199 .vco
= { .min
= 1400000, .max
= 2800000 },
200 .n
= { .min
= 1, .max
= 6 },
201 .m
= { .min
= 70, .max
= 120 },
202 .m1
= { .min
= 8, .max
= 18 },
203 .m2
= { .min
= 3, .max
= 7 },
204 .p
= { .min
= 7, .max
= 98 },
205 .p1
= { .min
= 1, .max
= 8 },
206 .p2
= { .dot_limit
= 112000,
207 .p2_slow
= 14, .p2_fast
= 7 },
211 static const intel_limit_t intel_limits_g4x_sdvo
= {
212 .dot
= { .min
= 25000, .max
= 270000 },
213 .vco
= { .min
= 1750000, .max
= 3500000},
214 .n
= { .min
= 1, .max
= 4 },
215 .m
= { .min
= 104, .max
= 138 },
216 .m1
= { .min
= 17, .max
= 23 },
217 .m2
= { .min
= 5, .max
= 11 },
218 .p
= { .min
= 10, .max
= 30 },
219 .p1
= { .min
= 1, .max
= 3},
220 .p2
= { .dot_limit
= 270000,
226 static const intel_limit_t intel_limits_g4x_hdmi
= {
227 .dot
= { .min
= 22000, .max
= 400000 },
228 .vco
= { .min
= 1750000, .max
= 3500000},
229 .n
= { .min
= 1, .max
= 4 },
230 .m
= { .min
= 104, .max
= 138 },
231 .m1
= { .min
= 16, .max
= 23 },
232 .m2
= { .min
= 5, .max
= 11 },
233 .p
= { .min
= 5, .max
= 80 },
234 .p1
= { .min
= 1, .max
= 8},
235 .p2
= { .dot_limit
= 165000,
236 .p2_slow
= 10, .p2_fast
= 5 },
239 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
240 .dot
= { .min
= 20000, .max
= 115000 },
241 .vco
= { .min
= 1750000, .max
= 3500000 },
242 .n
= { .min
= 1, .max
= 3 },
243 .m
= { .min
= 104, .max
= 138 },
244 .m1
= { .min
= 17, .max
= 23 },
245 .m2
= { .min
= 5, .max
= 11 },
246 .p
= { .min
= 28, .max
= 112 },
247 .p1
= { .min
= 2, .max
= 8 },
248 .p2
= { .dot_limit
= 0,
249 .p2_slow
= 14, .p2_fast
= 14
253 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
254 .dot
= { .min
= 80000, .max
= 224000 },
255 .vco
= { .min
= 1750000, .max
= 3500000 },
256 .n
= { .min
= 1, .max
= 3 },
257 .m
= { .min
= 104, .max
= 138 },
258 .m1
= { .min
= 17, .max
= 23 },
259 .m2
= { .min
= 5, .max
= 11 },
260 .p
= { .min
= 14, .max
= 42 },
261 .p1
= { .min
= 2, .max
= 6 },
262 .p2
= { .dot_limit
= 0,
263 .p2_slow
= 7, .p2_fast
= 7
267 static const intel_limit_t intel_limits_pineview_sdvo
= {
268 .dot
= { .min
= 20000, .max
= 400000},
269 .vco
= { .min
= 1700000, .max
= 3500000 },
270 /* Pineview's Ncounter is a ring counter */
271 .n
= { .min
= 3, .max
= 6 },
272 .m
= { .min
= 2, .max
= 256 },
273 /* Pineview only has one combined m divider, which we treat as m2. */
274 .m1
= { .min
= 0, .max
= 0 },
275 .m2
= { .min
= 0, .max
= 254 },
276 .p
= { .min
= 5, .max
= 80 },
277 .p1
= { .min
= 1, .max
= 8 },
278 .p2
= { .dot_limit
= 200000,
279 .p2_slow
= 10, .p2_fast
= 5 },
282 static const intel_limit_t intel_limits_pineview_lvds
= {
283 .dot
= { .min
= 20000, .max
= 400000 },
284 .vco
= { .min
= 1700000, .max
= 3500000 },
285 .n
= { .min
= 3, .max
= 6 },
286 .m
= { .min
= 2, .max
= 256 },
287 .m1
= { .min
= 0, .max
= 0 },
288 .m2
= { .min
= 0, .max
= 254 },
289 .p
= { .min
= 7, .max
= 112 },
290 .p1
= { .min
= 1, .max
= 8 },
291 .p2
= { .dot_limit
= 112000,
292 .p2_slow
= 14, .p2_fast
= 14 },
295 /* Ironlake / Sandybridge
297 * We calculate clock using (register_value + 2) for N/M1/M2, so here
298 * the range value for them is (actual_value - 2).
300 static const intel_limit_t intel_limits_ironlake_dac
= {
301 .dot
= { .min
= 25000, .max
= 350000 },
302 .vco
= { .min
= 1760000, .max
= 3510000 },
303 .n
= { .min
= 1, .max
= 5 },
304 .m
= { .min
= 79, .max
= 127 },
305 .m1
= { .min
= 12, .max
= 22 },
306 .m2
= { .min
= 5, .max
= 9 },
307 .p
= { .min
= 5, .max
= 80 },
308 .p1
= { .min
= 1, .max
= 8 },
309 .p2
= { .dot_limit
= 225000,
310 .p2_slow
= 10, .p2_fast
= 5 },
313 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
314 .dot
= { .min
= 25000, .max
= 350000 },
315 .vco
= { .min
= 1760000, .max
= 3510000 },
316 .n
= { .min
= 1, .max
= 3 },
317 .m
= { .min
= 79, .max
= 118 },
318 .m1
= { .min
= 12, .max
= 22 },
319 .m2
= { .min
= 5, .max
= 9 },
320 .p
= { .min
= 28, .max
= 112 },
321 .p1
= { .min
= 2, .max
= 8 },
322 .p2
= { .dot_limit
= 225000,
323 .p2_slow
= 14, .p2_fast
= 14 },
326 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
327 .dot
= { .min
= 25000, .max
= 350000 },
328 .vco
= { .min
= 1760000, .max
= 3510000 },
329 .n
= { .min
= 1, .max
= 3 },
330 .m
= { .min
= 79, .max
= 127 },
331 .m1
= { .min
= 12, .max
= 22 },
332 .m2
= { .min
= 5, .max
= 9 },
333 .p
= { .min
= 14, .max
= 56 },
334 .p1
= { .min
= 2, .max
= 8 },
335 .p2
= { .dot_limit
= 225000,
336 .p2_slow
= 7, .p2_fast
= 7 },
339 /* LVDS 100mhz refclk limits. */
340 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
341 .dot
= { .min
= 25000, .max
= 350000 },
342 .vco
= { .min
= 1760000, .max
= 3510000 },
343 .n
= { .min
= 1, .max
= 2 },
344 .m
= { .min
= 79, .max
= 126 },
345 .m1
= { .min
= 12, .max
= 22 },
346 .m2
= { .min
= 5, .max
= 9 },
347 .p
= { .min
= 28, .max
= 112 },
348 .p1
= { .min
= 2, .max
= 8 },
349 .p2
= { .dot_limit
= 225000,
350 .p2_slow
= 14, .p2_fast
= 14 },
353 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
354 .dot
= { .min
= 25000, .max
= 350000 },
355 .vco
= { .min
= 1760000, .max
= 3510000 },
356 .n
= { .min
= 1, .max
= 3 },
357 .m
= { .min
= 79, .max
= 126 },
358 .m1
= { .min
= 12, .max
= 22 },
359 .m2
= { .min
= 5, .max
= 9 },
360 .p
= { .min
= 14, .max
= 42 },
361 .p1
= { .min
= 2, .max
= 6 },
362 .p2
= { .dot_limit
= 225000,
363 .p2_slow
= 7, .p2_fast
= 7 },
366 static const intel_limit_t intel_limits_vlv
= {
368 * These are the data rate limits (measured in fast clocks)
369 * since those are the strictest limits we have. The fast
370 * clock and actual rate limits are more relaxed, so checking
371 * them would make no difference.
373 .dot
= { .min
= 25000 * 5, .max
= 270000 * 5 },
374 .vco
= { .min
= 4000000, .max
= 6000000 },
375 .n
= { .min
= 1, .max
= 7 },
376 .m1
= { .min
= 2, .max
= 3 },
377 .m2
= { .min
= 11, .max
= 156 },
378 .p1
= { .min
= 2, .max
= 3 },
379 .p2
= { .p2_slow
= 2, .p2_fast
= 20 }, /* slow=min, fast=max */
382 static const intel_limit_t intel_limits_chv
= {
384 * These are the data rate limits (measured in fast clocks)
385 * since those are the strictest limits we have. The fast
386 * clock and actual rate limits are more relaxed, so checking
387 * them would make no difference.
389 .dot
= { .min
= 25000 * 5, .max
= 540000 * 5},
390 .vco
= { .min
= 4860000, .max
= 6700000 },
391 .n
= { .min
= 1, .max
= 1 },
392 .m1
= { .min
= 2, .max
= 2 },
393 .m2
= { .min
= 24 << 22, .max
= 175 << 22 },
394 .p1
= { .min
= 2, .max
= 4 },
395 .p2
= { .p2_slow
= 1, .p2_fast
= 14 },
398 static void vlv_clock(int refclk
, intel_clock_t
*clock
)
400 clock
->m
= clock
->m1
* clock
->m2
;
401 clock
->p
= clock
->p1
* clock
->p2
;
402 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
404 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
405 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
409 * Returns whether any output on the specified pipe is of the specified type
411 bool intel_pipe_has_type(struct intel_crtc
*crtc
, enum intel_output_type type
)
413 struct drm_device
*dev
= crtc
->base
.dev
;
414 struct intel_encoder
*encoder
;
416 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
417 if (encoder
->type
== type
)
424 * Returns whether any output on the specified pipe will have the specified
425 * type after a staged modeset is complete, i.e., the same as
426 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
429 static bool intel_pipe_will_have_type(struct intel_crtc
*crtc
, int type
)
431 struct drm_device
*dev
= crtc
->base
.dev
;
432 struct intel_encoder
*encoder
;
434 for_each_intel_encoder(dev
, encoder
)
435 if (encoder
->new_crtc
== crtc
&& encoder
->type
== type
)
441 static const intel_limit_t
*intel_ironlake_limit(struct intel_crtc
*crtc
,
444 struct drm_device
*dev
= crtc
->base
.dev
;
445 const intel_limit_t
*limit
;
447 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
)) {
448 if (intel_is_dual_link_lvds(dev
)) {
449 if (refclk
== 100000)
450 limit
= &intel_limits_ironlake_dual_lvds_100m
;
452 limit
= &intel_limits_ironlake_dual_lvds
;
454 if (refclk
== 100000)
455 limit
= &intel_limits_ironlake_single_lvds_100m
;
457 limit
= &intel_limits_ironlake_single_lvds
;
460 limit
= &intel_limits_ironlake_dac
;
465 static const intel_limit_t
*intel_g4x_limit(struct intel_crtc
*crtc
)
467 struct drm_device
*dev
= crtc
->base
.dev
;
468 const intel_limit_t
*limit
;
470 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
)) {
471 if (intel_is_dual_link_lvds(dev
))
472 limit
= &intel_limits_g4x_dual_channel_lvds
;
474 limit
= &intel_limits_g4x_single_channel_lvds
;
475 } else if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_HDMI
) ||
476 intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
477 limit
= &intel_limits_g4x_hdmi
;
478 } else if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_SDVO
)) {
479 limit
= &intel_limits_g4x_sdvo
;
480 } else /* The option is for other outputs */
481 limit
= &intel_limits_i9xx_sdvo
;
486 static const intel_limit_t
*intel_limit(struct intel_crtc
*crtc
, int refclk
)
488 struct drm_device
*dev
= crtc
->base
.dev
;
489 const intel_limit_t
*limit
;
491 if (HAS_PCH_SPLIT(dev
))
492 limit
= intel_ironlake_limit(crtc
, refclk
);
493 else if (IS_G4X(dev
)) {
494 limit
= intel_g4x_limit(crtc
);
495 } else if (IS_PINEVIEW(dev
)) {
496 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
))
497 limit
= &intel_limits_pineview_lvds
;
499 limit
= &intel_limits_pineview_sdvo
;
500 } else if (IS_CHERRYVIEW(dev
)) {
501 limit
= &intel_limits_chv
;
502 } else if (IS_VALLEYVIEW(dev
)) {
503 limit
= &intel_limits_vlv
;
504 } else if (!IS_GEN2(dev
)) {
505 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
))
506 limit
= &intel_limits_i9xx_lvds
;
508 limit
= &intel_limits_i9xx_sdvo
;
510 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
))
511 limit
= &intel_limits_i8xx_lvds
;
512 else if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_DVO
))
513 limit
= &intel_limits_i8xx_dvo
;
515 limit
= &intel_limits_i8xx_dac
;
520 /* m1 is reserved as 0 in Pineview, n is a ring counter */
521 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
523 clock
->m
= clock
->m2
+ 2;
524 clock
->p
= clock
->p1
* clock
->p2
;
525 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
527 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
528 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
531 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
533 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
536 static void i9xx_clock(int refclk
, intel_clock_t
*clock
)
538 clock
->m
= i9xx_dpll_compute_m(clock
);
539 clock
->p
= clock
->p1
* clock
->p2
;
540 if (WARN_ON(clock
->n
+ 2 == 0 || clock
->p
== 0))
542 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
+ 2);
543 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
546 static void chv_clock(int refclk
, intel_clock_t
*clock
)
548 clock
->m
= clock
->m1
* clock
->m2
;
549 clock
->p
= clock
->p1
* clock
->p2
;
550 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
552 clock
->vco
= DIV_ROUND_CLOSEST_ULL((uint64_t)refclk
* clock
->m
,
554 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
557 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
559 * Returns whether the given set of divisors are valid for a given refclk with
560 * the given connectors.
563 static bool intel_PLL_is_valid(struct drm_device
*dev
,
564 const intel_limit_t
*limit
,
565 const intel_clock_t
*clock
)
567 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
568 INTELPllInvalid("n out of range\n");
569 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
570 INTELPllInvalid("p1 out of range\n");
571 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
572 INTELPllInvalid("m2 out of range\n");
573 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
574 INTELPllInvalid("m1 out of range\n");
576 if (!IS_PINEVIEW(dev
) && !IS_VALLEYVIEW(dev
))
577 if (clock
->m1
<= clock
->m2
)
578 INTELPllInvalid("m1 <= m2\n");
580 if (!IS_VALLEYVIEW(dev
)) {
581 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
582 INTELPllInvalid("p out of range\n");
583 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
584 INTELPllInvalid("m out of range\n");
587 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
588 INTELPllInvalid("vco out of range\n");
589 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
590 * connector, etc., rather than just a single range.
592 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
593 INTELPllInvalid("dot out of range\n");
599 i9xx_find_best_dpll(const intel_limit_t
*limit
, struct intel_crtc
*crtc
,
600 int target
, int refclk
, intel_clock_t
*match_clock
,
601 intel_clock_t
*best_clock
)
603 struct drm_device
*dev
= crtc
->base
.dev
;
607 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
)) {
609 * For LVDS just rely on its current settings for dual-channel.
610 * We haven't figured out how to reliably set up different
611 * single/dual channel state, if we even can.
613 if (intel_is_dual_link_lvds(dev
))
614 clock
.p2
= limit
->p2
.p2_fast
;
616 clock
.p2
= limit
->p2
.p2_slow
;
618 if (target
< limit
->p2
.dot_limit
)
619 clock
.p2
= limit
->p2
.p2_slow
;
621 clock
.p2
= limit
->p2
.p2_fast
;
624 memset(best_clock
, 0, sizeof(*best_clock
));
626 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
628 for (clock
.m2
= limit
->m2
.min
;
629 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
630 if (clock
.m2
>= clock
.m1
)
632 for (clock
.n
= limit
->n
.min
;
633 clock
.n
<= limit
->n
.max
; clock
.n
++) {
634 for (clock
.p1
= limit
->p1
.min
;
635 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
638 i9xx_clock(refclk
, &clock
);
639 if (!intel_PLL_is_valid(dev
, limit
,
643 clock
.p
!= match_clock
->p
)
646 this_err
= abs(clock
.dot
- target
);
647 if (this_err
< err
) {
656 return (err
!= target
);
660 pnv_find_best_dpll(const intel_limit_t
*limit
, struct intel_crtc
*crtc
,
661 int target
, int refclk
, intel_clock_t
*match_clock
,
662 intel_clock_t
*best_clock
)
664 struct drm_device
*dev
= crtc
->base
.dev
;
668 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
)) {
670 * For LVDS just rely on its current settings for dual-channel.
671 * We haven't figured out how to reliably set up different
672 * single/dual channel state, if we even can.
674 if (intel_is_dual_link_lvds(dev
))
675 clock
.p2
= limit
->p2
.p2_fast
;
677 clock
.p2
= limit
->p2
.p2_slow
;
679 if (target
< limit
->p2
.dot_limit
)
680 clock
.p2
= limit
->p2
.p2_slow
;
682 clock
.p2
= limit
->p2
.p2_fast
;
685 memset(best_clock
, 0, sizeof(*best_clock
));
687 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
689 for (clock
.m2
= limit
->m2
.min
;
690 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
691 for (clock
.n
= limit
->n
.min
;
692 clock
.n
<= limit
->n
.max
; clock
.n
++) {
693 for (clock
.p1
= limit
->p1
.min
;
694 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
697 pineview_clock(refclk
, &clock
);
698 if (!intel_PLL_is_valid(dev
, limit
,
702 clock
.p
!= match_clock
->p
)
705 this_err
= abs(clock
.dot
- target
);
706 if (this_err
< err
) {
715 return (err
!= target
);
719 g4x_find_best_dpll(const intel_limit_t
*limit
, struct intel_crtc
*crtc
,
720 int target
, int refclk
, intel_clock_t
*match_clock
,
721 intel_clock_t
*best_clock
)
723 struct drm_device
*dev
= crtc
->base
.dev
;
727 /* approximately equals target * 0.00585 */
728 int err_most
= (target
>> 8) + (target
>> 9);
731 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
)) {
732 if (intel_is_dual_link_lvds(dev
))
733 clock
.p2
= limit
->p2
.p2_fast
;
735 clock
.p2
= limit
->p2
.p2_slow
;
737 if (target
< limit
->p2
.dot_limit
)
738 clock
.p2
= limit
->p2
.p2_slow
;
740 clock
.p2
= limit
->p2
.p2_fast
;
743 memset(best_clock
, 0, sizeof(*best_clock
));
744 max_n
= limit
->n
.max
;
745 /* based on hardware requirement, prefer smaller n to precision */
746 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
747 /* based on hardware requirement, prefere larger m1,m2 */
748 for (clock
.m1
= limit
->m1
.max
;
749 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
750 for (clock
.m2
= limit
->m2
.max
;
751 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
752 for (clock
.p1
= limit
->p1
.max
;
753 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
756 i9xx_clock(refclk
, &clock
);
757 if (!intel_PLL_is_valid(dev
, limit
,
761 this_err
= abs(clock
.dot
- target
);
762 if (this_err
< err_most
) {
776 vlv_find_best_dpll(const intel_limit_t
*limit
, struct intel_crtc
*crtc
,
777 int target
, int refclk
, intel_clock_t
*match_clock
,
778 intel_clock_t
*best_clock
)
780 struct drm_device
*dev
= crtc
->base
.dev
;
782 unsigned int bestppm
= 1000000;
783 /* min update 19.2 MHz */
784 int max_n
= min(limit
->n
.max
, refclk
/ 19200);
787 target
*= 5; /* fast clock */
789 memset(best_clock
, 0, sizeof(*best_clock
));
791 /* based on hardware requirement, prefer smaller n to precision */
792 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
793 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
794 for (clock
.p2
= limit
->p2
.p2_fast
; clock
.p2
>= limit
->p2
.p2_slow
;
795 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
796 clock
.p
= clock
.p1
* clock
.p2
;
797 /* based on hardware requirement, prefer bigger m1,m2 values */
798 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
799 unsigned int ppm
, diff
;
801 clock
.m2
= DIV_ROUND_CLOSEST(target
* clock
.p
* clock
.n
,
804 vlv_clock(refclk
, &clock
);
806 if (!intel_PLL_is_valid(dev
, limit
,
810 diff
= abs(clock
.dot
- target
);
811 ppm
= div_u64(1000000ULL * diff
, target
);
813 if (ppm
< 100 && clock
.p
> best_clock
->p
) {
819 if (bestppm
>= 10 && ppm
< bestppm
- 10) {
833 chv_find_best_dpll(const intel_limit_t
*limit
, struct intel_crtc
*crtc
,
834 int target
, int refclk
, intel_clock_t
*match_clock
,
835 intel_clock_t
*best_clock
)
837 struct drm_device
*dev
= crtc
->base
.dev
;
842 memset(best_clock
, 0, sizeof(*best_clock
));
845 * Based on hardware doc, the n always set to 1, and m1 always
846 * set to 2. If requires to support 200Mhz refclk, we need to
847 * revisit this because n may not 1 anymore.
849 clock
.n
= 1, clock
.m1
= 2;
850 target
*= 5; /* fast clock */
852 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
853 for (clock
.p2
= limit
->p2
.p2_fast
;
854 clock
.p2
>= limit
->p2
.p2_slow
;
855 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
857 clock
.p
= clock
.p1
* clock
.p2
;
859 m2
= DIV_ROUND_CLOSEST_ULL(((uint64_t)target
* clock
.p
*
860 clock
.n
) << 22, refclk
* clock
.m1
);
862 if (m2
> INT_MAX
/clock
.m1
)
867 chv_clock(refclk
, &clock
);
869 if (!intel_PLL_is_valid(dev
, limit
, &clock
))
872 /* based on hardware requirement, prefer bigger p
874 if (clock
.p
> best_clock
->p
) {
884 bool intel_crtc_active(struct drm_crtc
*crtc
)
886 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
888 /* Be paranoid as we can arrive here with only partial
889 * state retrieved from the hardware during setup.
891 * We can ditch the adjusted_mode.crtc_clock check as soon
892 * as Haswell has gained clock readout/fastboot support.
894 * We can ditch the crtc->primary->fb check as soon as we can
895 * properly reconstruct framebuffers.
897 return intel_crtc
->active
&& crtc
->primary
->fb
&&
898 intel_crtc
->config
.adjusted_mode
.crtc_clock
;
901 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
904 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
905 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
907 return intel_crtc
->config
.cpu_transcoder
;
910 static bool pipe_dsl_stopped(struct drm_device
*dev
, enum pipe pipe
)
912 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
913 u32 reg
= PIPEDSL(pipe
);
918 line_mask
= DSL_LINEMASK_GEN2
;
920 line_mask
= DSL_LINEMASK_GEN3
;
922 line1
= I915_READ(reg
) & line_mask
;
924 line2
= I915_READ(reg
) & line_mask
;
926 return line1
== line2
;
930 * intel_wait_for_pipe_off - wait for pipe to turn off
931 * @crtc: crtc whose pipe to wait for
933 * After disabling a pipe, we can't wait for vblank in the usual way,
934 * spinning on the vblank interrupt status bit, since we won't actually
935 * see an interrupt when the pipe is disabled.
938 * wait for the pipe register state bit to turn off
941 * wait for the display line value to settle (it usually
942 * ends up stopping at the start of the next frame).
945 static void intel_wait_for_pipe_off(struct intel_crtc
*crtc
)
947 struct drm_device
*dev
= crtc
->base
.dev
;
948 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
949 enum transcoder cpu_transcoder
= crtc
->config
.cpu_transcoder
;
950 enum pipe pipe
= crtc
->pipe
;
952 if (INTEL_INFO(dev
)->gen
>= 4) {
953 int reg
= PIPECONF(cpu_transcoder
);
955 /* Wait for the Pipe State to go off */
956 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
958 WARN(1, "pipe_off wait timed out\n");
960 /* Wait for the display line to settle */
961 if (wait_for(pipe_dsl_stopped(dev
, pipe
), 100))
962 WARN(1, "pipe_off wait timed out\n");
967 * ibx_digital_port_connected - is the specified port connected?
968 * @dev_priv: i915 private structure
969 * @port: the port to test
971 * Returns true if @port is connected, false otherwise.
973 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
974 struct intel_digital_port
*port
)
978 if (HAS_PCH_IBX(dev_priv
->dev
)) {
979 switch (port
->port
) {
981 bit
= SDE_PORTB_HOTPLUG
;
984 bit
= SDE_PORTC_HOTPLUG
;
987 bit
= SDE_PORTD_HOTPLUG
;
993 switch (port
->port
) {
995 bit
= SDE_PORTB_HOTPLUG_CPT
;
998 bit
= SDE_PORTC_HOTPLUG_CPT
;
1001 bit
= SDE_PORTD_HOTPLUG_CPT
;
1008 return I915_READ(SDEISR
) & bit
;
1011 static const char *state_string(bool enabled
)
1013 return enabled
? "on" : "off";
1016 /* Only for pre-ILK configs */
1017 void assert_pll(struct drm_i915_private
*dev_priv
,
1018 enum pipe pipe
, bool state
)
1025 val
= I915_READ(reg
);
1026 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1027 WARN(cur_state
!= state
,
1028 "PLL state assertion failure (expected %s, current %s)\n",
1029 state_string(state
), state_string(cur_state
));
1032 /* XXX: the dsi pll is shared between MIPI DSI ports */
1033 static void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
1038 mutex_lock(&dev_priv
->dpio_lock
);
1039 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
1040 mutex_unlock(&dev_priv
->dpio_lock
);
1042 cur_state
= val
& DSI_PLL_VCO_EN
;
1043 WARN(cur_state
!= state
,
1044 "DSI PLL state assertion failure (expected %s, current %s)\n",
1045 state_string(state
), state_string(cur_state
));
1047 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1048 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1050 struct intel_shared_dpll
*
1051 intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
)
1053 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1055 if (crtc
->config
.shared_dpll
< 0)
1058 return &dev_priv
->shared_dplls
[crtc
->config
.shared_dpll
];
1062 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
1063 struct intel_shared_dpll
*pll
,
1067 struct intel_dpll_hw_state hw_state
;
1070 "asserting DPLL %s with no DPLL\n", state_string(state
)))
1073 cur_state
= pll
->get_hw_state(dev_priv
, pll
, &hw_state
);
1074 WARN(cur_state
!= state
,
1075 "%s assertion failure (expected %s, current %s)\n",
1076 pll
->name
, state_string(state
), state_string(cur_state
));
1079 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1080 enum pipe pipe
, bool state
)
1085 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1088 if (HAS_DDI(dev_priv
->dev
)) {
1089 /* DDI does not have a specific FDI_TX register */
1090 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1091 val
= I915_READ(reg
);
1092 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1094 reg
= FDI_TX_CTL(pipe
);
1095 val
= I915_READ(reg
);
1096 cur_state
= !!(val
& FDI_TX_ENABLE
);
1098 WARN(cur_state
!= state
,
1099 "FDI TX state assertion failure (expected %s, current %s)\n",
1100 state_string(state
), state_string(cur_state
));
1102 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1103 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1105 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1106 enum pipe pipe
, bool state
)
1112 reg
= FDI_RX_CTL(pipe
);
1113 val
= I915_READ(reg
);
1114 cur_state
= !!(val
& FDI_RX_ENABLE
);
1115 WARN(cur_state
!= state
,
1116 "FDI RX state assertion failure (expected %s, current %s)\n",
1117 state_string(state
), state_string(cur_state
));
1119 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1120 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1122 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1128 /* ILK FDI PLL is always enabled */
1129 if (INTEL_INFO(dev_priv
->dev
)->gen
== 5)
1132 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1133 if (HAS_DDI(dev_priv
->dev
))
1136 reg
= FDI_TX_CTL(pipe
);
1137 val
= I915_READ(reg
);
1138 WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1141 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1142 enum pipe pipe
, bool state
)
1148 reg
= FDI_RX_CTL(pipe
);
1149 val
= I915_READ(reg
);
1150 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1151 WARN(cur_state
!= state
,
1152 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1153 state_string(state
), state_string(cur_state
));
1156 void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1159 struct drm_device
*dev
= dev_priv
->dev
;
1162 enum pipe panel_pipe
= PIPE_A
;
1165 if (WARN_ON(HAS_DDI(dev
)))
1168 if (HAS_PCH_SPLIT(dev
)) {
1171 pp_reg
= PCH_PP_CONTROL
;
1172 port_sel
= I915_READ(PCH_PP_ON_DELAYS
) & PANEL_PORT_SELECT_MASK
;
1174 if (port_sel
== PANEL_PORT_SELECT_LVDS
&&
1175 I915_READ(PCH_LVDS
) & LVDS_PIPEB_SELECT
)
1176 panel_pipe
= PIPE_B
;
1177 /* XXX: else fix for eDP */
1178 } else if (IS_VALLEYVIEW(dev
)) {
1179 /* presumably write lock depends on pipe, not port select */
1180 pp_reg
= VLV_PIPE_PP_CONTROL(pipe
);
1183 pp_reg
= PP_CONTROL
;
1184 if (I915_READ(LVDS
) & LVDS_PIPEB_SELECT
)
1185 panel_pipe
= PIPE_B
;
1188 val
= I915_READ(pp_reg
);
1189 if (!(val
& PANEL_POWER_ON
) ||
1190 ((val
& PANEL_UNLOCK_MASK
) == PANEL_UNLOCK_REGS
))
1193 WARN(panel_pipe
== pipe
&& locked
,
1194 "panel assertion failure, pipe %c regs locked\n",
1198 static void assert_cursor(struct drm_i915_private
*dev_priv
,
1199 enum pipe pipe
, bool state
)
1201 struct drm_device
*dev
= dev_priv
->dev
;
1204 if (IS_845G(dev
) || IS_I865G(dev
))
1205 cur_state
= I915_READ(_CURACNTR
) & CURSOR_ENABLE
;
1207 cur_state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
1209 WARN(cur_state
!= state
,
1210 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1211 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1213 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1214 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1216 void assert_pipe(struct drm_i915_private
*dev_priv
,
1217 enum pipe pipe
, bool state
)
1222 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1225 /* if we need the pipe quirk it must be always on */
1226 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1227 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1230 if (!intel_display_power_is_enabled(dev_priv
,
1231 POWER_DOMAIN_TRANSCODER(cpu_transcoder
))) {
1234 reg
= PIPECONF(cpu_transcoder
);
1235 val
= I915_READ(reg
);
1236 cur_state
= !!(val
& PIPECONF_ENABLE
);
1239 WARN(cur_state
!= state
,
1240 "pipe %c assertion failure (expected %s, current %s)\n",
1241 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1244 static void assert_plane(struct drm_i915_private
*dev_priv
,
1245 enum plane plane
, bool state
)
1251 reg
= DSPCNTR(plane
);
1252 val
= I915_READ(reg
);
1253 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1254 WARN(cur_state
!= state
,
1255 "plane %c assertion failure (expected %s, current %s)\n",
1256 plane_name(plane
), state_string(state
), state_string(cur_state
));
1259 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1262 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1265 struct drm_device
*dev
= dev_priv
->dev
;
1270 /* Primary planes are fixed to pipes on gen4+ */
1271 if (INTEL_INFO(dev
)->gen
>= 4) {
1272 reg
= DSPCNTR(pipe
);
1273 val
= I915_READ(reg
);
1274 WARN(val
& DISPLAY_PLANE_ENABLE
,
1275 "plane %c assertion failure, should be disabled but not\n",
1280 /* Need to check both planes against the pipe */
1281 for_each_pipe(dev_priv
, i
) {
1283 val
= I915_READ(reg
);
1284 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1285 DISPPLANE_SEL_PIPE_SHIFT
;
1286 WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1287 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1288 plane_name(i
), pipe_name(pipe
));
1292 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1295 struct drm_device
*dev
= dev_priv
->dev
;
1299 if (INTEL_INFO(dev
)->gen
>= 9) {
1300 for_each_sprite(pipe
, sprite
) {
1301 val
= I915_READ(PLANE_CTL(pipe
, sprite
));
1302 WARN(val
& PLANE_CTL_ENABLE
,
1303 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1304 sprite
, pipe_name(pipe
));
1306 } else if (IS_VALLEYVIEW(dev
)) {
1307 for_each_sprite(pipe
, sprite
) {
1308 reg
= SPCNTR(pipe
, sprite
);
1309 val
= I915_READ(reg
);
1310 WARN(val
& SP_ENABLE
,
1311 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1312 sprite_name(pipe
, sprite
), pipe_name(pipe
));
1314 } else if (INTEL_INFO(dev
)->gen
>= 7) {
1316 val
= I915_READ(reg
);
1317 WARN(val
& SPRITE_ENABLE
,
1318 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1319 plane_name(pipe
), pipe_name(pipe
));
1320 } else if (INTEL_INFO(dev
)->gen
>= 5) {
1321 reg
= DVSCNTR(pipe
);
1322 val
= I915_READ(reg
);
1323 WARN(val
& DVS_ENABLE
,
1324 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1325 plane_name(pipe
), pipe_name(pipe
));
1329 static void assert_vblank_disabled(struct drm_crtc
*crtc
)
1331 if (WARN_ON(drm_crtc_vblank_get(crtc
) == 0))
1332 drm_crtc_vblank_put(crtc
);
1335 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1340 WARN_ON(!(HAS_PCH_IBX(dev_priv
->dev
) || HAS_PCH_CPT(dev_priv
->dev
)));
1342 val
= I915_READ(PCH_DREF_CONTROL
);
1343 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1344 DREF_SUPERSPREAD_SOURCE_MASK
));
1345 WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1348 static void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1355 reg
= PCH_TRANSCONF(pipe
);
1356 val
= I915_READ(reg
);
1357 enabled
= !!(val
& TRANS_ENABLE
);
1359 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1363 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1364 enum pipe pipe
, u32 port_sel
, u32 val
)
1366 if ((val
& DP_PORT_EN
) == 0)
1369 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1370 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1371 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1372 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1374 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1375 if ((val
& DP_PIPE_MASK_CHV
) != DP_PIPE_SELECT_CHV(pipe
))
1378 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1384 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1385 enum pipe pipe
, u32 val
)
1387 if ((val
& SDVO_ENABLE
) == 0)
1390 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1391 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1393 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1394 if ((val
& SDVO_PIPE_SEL_MASK_CHV
) != SDVO_PIPE_SEL_CHV(pipe
))
1397 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1403 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1404 enum pipe pipe
, u32 val
)
1406 if ((val
& LVDS_PORT_EN
) == 0)
1409 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1410 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1413 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1419 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1420 enum pipe pipe
, u32 val
)
1422 if ((val
& ADPA_DAC_ENABLE
) == 0)
1424 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1425 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1428 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1434 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1435 enum pipe pipe
, int reg
, u32 port_sel
)
1437 u32 val
= I915_READ(reg
);
1438 WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1439 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1440 reg
, pipe_name(pipe
));
1442 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1443 && (val
& DP_PIPEB_SELECT
),
1444 "IBX PCH dp port still using transcoder B\n");
1447 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1448 enum pipe pipe
, int reg
)
1450 u32 val
= I915_READ(reg
);
1451 WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1452 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1453 reg
, pipe_name(pipe
));
1455 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_ENABLE
) == 0
1456 && (val
& SDVO_PIPE_B_SELECT
),
1457 "IBX PCH hdmi port still using transcoder B\n");
1460 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1466 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1467 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1468 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1471 val
= I915_READ(reg
);
1472 WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1473 "PCH VGA enabled on transcoder %c, should be disabled\n",
1477 val
= I915_READ(reg
);
1478 WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1479 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1482 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1483 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1484 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1487 static void intel_init_dpio(struct drm_device
*dev
)
1489 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1491 if (!IS_VALLEYVIEW(dev
))
1495 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1496 * CHV x1 PHY (DP/HDMI D)
1497 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1499 if (IS_CHERRYVIEW(dev
)) {
1500 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO_2
;
1501 DPIO_PHY_IOSF_PORT(DPIO_PHY1
) = IOSF_PORT_DPIO
;
1503 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO
;
1507 static void vlv_enable_pll(struct intel_crtc
*crtc
,
1508 const struct intel_crtc_config
*pipe_config
)
1510 struct drm_device
*dev
= crtc
->base
.dev
;
1511 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1512 int reg
= DPLL(crtc
->pipe
);
1513 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
1515 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1517 /* No really, not for ILK+ */
1518 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
));
1520 /* PLL is protected by panel, make sure we can write it */
1521 if (IS_MOBILE(dev_priv
->dev
))
1522 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1524 I915_WRITE(reg
, dpll
);
1528 if (wait_for(((I915_READ(reg
) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1529 DRM_ERROR("DPLL %d failed to lock\n", crtc
->pipe
);
1531 I915_WRITE(DPLL_MD(crtc
->pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1532 POSTING_READ(DPLL_MD(crtc
->pipe
));
1534 /* We do this three times for luck */
1535 I915_WRITE(reg
, dpll
);
1537 udelay(150); /* wait for warmup */
1538 I915_WRITE(reg
, dpll
);
1540 udelay(150); /* wait for warmup */
1541 I915_WRITE(reg
, dpll
);
1543 udelay(150); /* wait for warmup */
1546 static void chv_enable_pll(struct intel_crtc
*crtc
,
1547 const struct intel_crtc_config
*pipe_config
)
1549 struct drm_device
*dev
= crtc
->base
.dev
;
1550 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1551 int pipe
= crtc
->pipe
;
1552 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1555 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1557 BUG_ON(!IS_CHERRYVIEW(dev_priv
->dev
));
1559 mutex_lock(&dev_priv
->dpio_lock
);
1561 /* Enable back the 10bit clock to display controller */
1562 tmp
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1563 tmp
|= DPIO_DCLKP_EN
;
1564 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), tmp
);
1567 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1572 I915_WRITE(DPLL(pipe
), pipe_config
->dpll_hw_state
.dpll
);
1574 /* Check PLL is locked */
1575 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1576 DRM_ERROR("PLL %d failed to lock\n", pipe
);
1578 /* not sure when this should be written */
1579 I915_WRITE(DPLL_MD(pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1580 POSTING_READ(DPLL_MD(pipe
));
1582 mutex_unlock(&dev_priv
->dpio_lock
);
1585 static int intel_num_dvo_pipes(struct drm_device
*dev
)
1587 struct intel_crtc
*crtc
;
1590 for_each_intel_crtc(dev
, crtc
)
1591 count
+= crtc
->active
&&
1592 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
);
1597 static void i9xx_enable_pll(struct intel_crtc
*crtc
)
1599 struct drm_device
*dev
= crtc
->base
.dev
;
1600 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1601 int reg
= DPLL(crtc
->pipe
);
1602 u32 dpll
= crtc
->config
.dpll_hw_state
.dpll
;
1604 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1606 /* No really, not for ILK+ */
1607 BUG_ON(INTEL_INFO(dev
)->gen
>= 5);
1609 /* PLL is protected by panel, make sure we can write it */
1610 if (IS_MOBILE(dev
) && !IS_I830(dev
))
1611 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1613 /* Enable DVO 2x clock on both PLLs if necessary */
1614 if (IS_I830(dev
) && intel_num_dvo_pipes(dev
) > 0) {
1616 * It appears to be important that we don't enable this
1617 * for the current pipe before otherwise configuring the
1618 * PLL. No idea how this should be handled if multiple
1619 * DVO outputs are enabled simultaneosly.
1621 dpll
|= DPLL_DVO_2X_MODE
;
1622 I915_WRITE(DPLL(!crtc
->pipe
),
1623 I915_READ(DPLL(!crtc
->pipe
)) | DPLL_DVO_2X_MODE
);
1626 /* Wait for the clocks to stabilize. */
1630 if (INTEL_INFO(dev
)->gen
>= 4) {
1631 I915_WRITE(DPLL_MD(crtc
->pipe
),
1632 crtc
->config
.dpll_hw_state
.dpll_md
);
1634 /* The pixel multiplier can only be updated once the
1635 * DPLL is enabled and the clocks are stable.
1637 * So write it again.
1639 I915_WRITE(reg
, dpll
);
1642 /* We do this three times for luck */
1643 I915_WRITE(reg
, dpll
);
1645 udelay(150); /* wait for warmup */
1646 I915_WRITE(reg
, dpll
);
1648 udelay(150); /* wait for warmup */
1649 I915_WRITE(reg
, dpll
);
1651 udelay(150); /* wait for warmup */
1655 * i9xx_disable_pll - disable a PLL
1656 * @dev_priv: i915 private structure
1657 * @pipe: pipe PLL to disable
1659 * Disable the PLL for @pipe, making sure the pipe is off first.
1661 * Note! This is for pre-ILK only.
1663 static void i9xx_disable_pll(struct intel_crtc
*crtc
)
1665 struct drm_device
*dev
= crtc
->base
.dev
;
1666 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1667 enum pipe pipe
= crtc
->pipe
;
1669 /* Disable DVO 2x clock on both PLLs if necessary */
1671 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
) &&
1672 intel_num_dvo_pipes(dev
) == 1) {
1673 I915_WRITE(DPLL(PIPE_B
),
1674 I915_READ(DPLL(PIPE_B
)) & ~DPLL_DVO_2X_MODE
);
1675 I915_WRITE(DPLL(PIPE_A
),
1676 I915_READ(DPLL(PIPE_A
)) & ~DPLL_DVO_2X_MODE
);
1679 /* Don't disable pipe or pipe PLLs if needed */
1680 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1681 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1684 /* Make sure the pipe isn't still relying on us */
1685 assert_pipe_disabled(dev_priv
, pipe
);
1687 I915_WRITE(DPLL(pipe
), 0);
1688 POSTING_READ(DPLL(pipe
));
1691 static void vlv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1695 /* Make sure the pipe isn't still relying on us */
1696 assert_pipe_disabled(dev_priv
, pipe
);
1699 * Leave integrated clock source and reference clock enabled for pipe B.
1700 * The latter is needed for VGA hotplug / manual detection.
1703 val
= DPLL_INTEGRATED_CRI_CLK_VLV
| DPLL_REFA_CLK_ENABLE_VLV
;
1704 I915_WRITE(DPLL(pipe
), val
);
1705 POSTING_READ(DPLL(pipe
));
1709 static void chv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1711 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1714 /* Make sure the pipe isn't still relying on us */
1715 assert_pipe_disabled(dev_priv
, pipe
);
1717 /* Set PLL en = 0 */
1718 val
= DPLL_SSC_REF_CLOCK_CHV
| DPLL_REFA_CLK_ENABLE_VLV
;
1720 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1721 I915_WRITE(DPLL(pipe
), val
);
1722 POSTING_READ(DPLL(pipe
));
1724 mutex_lock(&dev_priv
->dpio_lock
);
1726 /* Disable 10bit clock to display controller */
1727 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1728 val
&= ~DPIO_DCLKP_EN
;
1729 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), val
);
1731 /* disable left/right clock distribution */
1732 if (pipe
!= PIPE_B
) {
1733 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
1734 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
1735 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
1737 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
1738 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
1739 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
1742 mutex_unlock(&dev_priv
->dpio_lock
);
1745 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1746 struct intel_digital_port
*dport
)
1751 switch (dport
->port
) {
1753 port_mask
= DPLL_PORTB_READY_MASK
;
1757 port_mask
= DPLL_PORTC_READY_MASK
;
1761 port_mask
= DPLL_PORTD_READY_MASK
;
1762 dpll_reg
= DPIO_PHY_STATUS
;
1768 if (wait_for((I915_READ(dpll_reg
) & port_mask
) == 0, 1000))
1769 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1770 port_name(dport
->port
), I915_READ(dpll_reg
));
1773 static void intel_prepare_shared_dpll(struct intel_crtc
*crtc
)
1775 struct drm_device
*dev
= crtc
->base
.dev
;
1776 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1777 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1779 if (WARN_ON(pll
== NULL
))
1782 WARN_ON(!pll
->config
.crtc_mask
);
1783 if (pll
->active
== 0) {
1784 DRM_DEBUG_DRIVER("setting up %s\n", pll
->name
);
1786 assert_shared_dpll_disabled(dev_priv
, pll
);
1788 pll
->mode_set(dev_priv
, pll
);
1793 * intel_enable_shared_dpll - enable PCH PLL
1794 * @dev_priv: i915 private structure
1795 * @pipe: pipe PLL to enable
1797 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1798 * drives the transcoder clock.
1800 static void intel_enable_shared_dpll(struct intel_crtc
*crtc
)
1802 struct drm_device
*dev
= crtc
->base
.dev
;
1803 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1804 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1806 if (WARN_ON(pll
== NULL
))
1809 if (WARN_ON(pll
->config
.crtc_mask
== 0))
1812 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1813 pll
->name
, pll
->active
, pll
->on
,
1814 crtc
->base
.base
.id
);
1816 if (pll
->active
++) {
1818 assert_shared_dpll_enabled(dev_priv
, pll
);
1823 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
1825 DRM_DEBUG_KMS("enabling %s\n", pll
->name
);
1826 pll
->enable(dev_priv
, pll
);
1830 static void intel_disable_shared_dpll(struct intel_crtc
*crtc
)
1832 struct drm_device
*dev
= crtc
->base
.dev
;
1833 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1834 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1836 /* PCH only available on ILK+ */
1837 BUG_ON(INTEL_INFO(dev
)->gen
< 5);
1838 if (WARN_ON(pll
== NULL
))
1841 if (WARN_ON(pll
->config
.crtc_mask
== 0))
1844 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1845 pll
->name
, pll
->active
, pll
->on
,
1846 crtc
->base
.base
.id
);
1848 if (WARN_ON(pll
->active
== 0)) {
1849 assert_shared_dpll_disabled(dev_priv
, pll
);
1853 assert_shared_dpll_enabled(dev_priv
, pll
);
1858 DRM_DEBUG_KMS("disabling %s\n", pll
->name
);
1859 pll
->disable(dev_priv
, pll
);
1862 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
1865 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1868 struct drm_device
*dev
= dev_priv
->dev
;
1869 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1870 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1871 uint32_t reg
, val
, pipeconf_val
;
1873 /* PCH only available on ILK+ */
1874 BUG_ON(!HAS_PCH_SPLIT(dev
));
1876 /* Make sure PCH DPLL is enabled */
1877 assert_shared_dpll_enabled(dev_priv
,
1878 intel_crtc_to_shared_dpll(intel_crtc
));
1880 /* FDI must be feeding us bits for PCH ports */
1881 assert_fdi_tx_enabled(dev_priv
, pipe
);
1882 assert_fdi_rx_enabled(dev_priv
, pipe
);
1884 if (HAS_PCH_CPT(dev
)) {
1885 /* Workaround: Set the timing override bit before enabling the
1886 * pch transcoder. */
1887 reg
= TRANS_CHICKEN2(pipe
);
1888 val
= I915_READ(reg
);
1889 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1890 I915_WRITE(reg
, val
);
1893 reg
= PCH_TRANSCONF(pipe
);
1894 val
= I915_READ(reg
);
1895 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1897 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1899 * make the BPC in transcoder be consistent with
1900 * that in pipeconf reg.
1902 val
&= ~PIPECONF_BPC_MASK
;
1903 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1906 val
&= ~TRANS_INTERLACE_MASK
;
1907 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1908 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1909 intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
1910 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1912 val
|= TRANS_INTERLACED
;
1914 val
|= TRANS_PROGRESSIVE
;
1916 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1917 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1918 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
1921 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1922 enum transcoder cpu_transcoder
)
1924 u32 val
, pipeconf_val
;
1926 /* PCH only available on ILK+ */
1927 BUG_ON(!HAS_PCH_SPLIT(dev_priv
->dev
));
1929 /* FDI must be feeding us bits for PCH ports */
1930 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1931 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
1933 /* Workaround: set timing override bit. */
1934 val
= I915_READ(_TRANSA_CHICKEN2
);
1935 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1936 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1939 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1941 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1942 PIPECONF_INTERLACED_ILK
)
1943 val
|= TRANS_INTERLACED
;
1945 val
|= TRANS_PROGRESSIVE
;
1947 I915_WRITE(LPT_TRANSCONF
, val
);
1948 if (wait_for(I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
, 100))
1949 DRM_ERROR("Failed to enable PCH transcoder\n");
1952 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1955 struct drm_device
*dev
= dev_priv
->dev
;
1958 /* FDI relies on the transcoder */
1959 assert_fdi_tx_disabled(dev_priv
, pipe
);
1960 assert_fdi_rx_disabled(dev_priv
, pipe
);
1962 /* Ports must be off as well */
1963 assert_pch_ports_disabled(dev_priv
, pipe
);
1965 reg
= PCH_TRANSCONF(pipe
);
1966 val
= I915_READ(reg
);
1967 val
&= ~TRANS_ENABLE
;
1968 I915_WRITE(reg
, val
);
1969 /* wait for PCH transcoder off, transcoder state */
1970 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1971 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
1973 if (!HAS_PCH_IBX(dev
)) {
1974 /* Workaround: Clear the timing override chicken bit again. */
1975 reg
= TRANS_CHICKEN2(pipe
);
1976 val
= I915_READ(reg
);
1977 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1978 I915_WRITE(reg
, val
);
1982 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1986 val
= I915_READ(LPT_TRANSCONF
);
1987 val
&= ~TRANS_ENABLE
;
1988 I915_WRITE(LPT_TRANSCONF
, val
);
1989 /* wait for PCH transcoder off, transcoder state */
1990 if (wait_for((I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
) == 0, 50))
1991 DRM_ERROR("Failed to disable PCH transcoder\n");
1993 /* Workaround: clear timing override bit. */
1994 val
= I915_READ(_TRANSA_CHICKEN2
);
1995 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1996 I915_WRITE(_TRANSA_CHICKEN2
, val
);
2000 * intel_enable_pipe - enable a pipe, asserting requirements
2001 * @crtc: crtc responsible for the pipe
2003 * Enable @crtc's pipe, making sure that various hardware specific requirements
2004 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2006 static void intel_enable_pipe(struct intel_crtc
*crtc
)
2008 struct drm_device
*dev
= crtc
->base
.dev
;
2009 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2010 enum pipe pipe
= crtc
->pipe
;
2011 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
2013 enum pipe pch_transcoder
;
2017 assert_planes_disabled(dev_priv
, pipe
);
2018 assert_cursor_disabled(dev_priv
, pipe
);
2019 assert_sprites_disabled(dev_priv
, pipe
);
2021 if (HAS_PCH_LPT(dev_priv
->dev
))
2022 pch_transcoder
= TRANSCODER_A
;
2024 pch_transcoder
= pipe
;
2027 * A pipe without a PLL won't actually be able to drive bits from
2028 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2031 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
2032 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
))
2033 assert_dsi_pll_enabled(dev_priv
);
2035 assert_pll_enabled(dev_priv
, pipe
);
2037 if (crtc
->config
.has_pch_encoder
) {
2038 /* if driving the PCH, we need FDI enabled */
2039 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
2040 assert_fdi_tx_pll_enabled(dev_priv
,
2041 (enum pipe
) cpu_transcoder
);
2043 /* FIXME: assert CPU port conditions for SNB+ */
2046 reg
= PIPECONF(cpu_transcoder
);
2047 val
= I915_READ(reg
);
2048 if (val
& PIPECONF_ENABLE
) {
2049 WARN_ON(!((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
2050 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
)));
2054 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
2059 * intel_disable_pipe - disable a pipe, asserting requirements
2060 * @crtc: crtc whose pipes is to be disabled
2062 * Disable the pipe of @crtc, making sure that various hardware
2063 * specific requirements are met, if applicable, e.g. plane
2064 * disabled, panel fitter off, etc.
2066 * Will wait until the pipe has shut down before returning.
2068 static void intel_disable_pipe(struct intel_crtc
*crtc
)
2070 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
2071 enum transcoder cpu_transcoder
= crtc
->config
.cpu_transcoder
;
2072 enum pipe pipe
= crtc
->pipe
;
2077 * Make sure planes won't keep trying to pump pixels to us,
2078 * or we might hang the display.
2080 assert_planes_disabled(dev_priv
, pipe
);
2081 assert_cursor_disabled(dev_priv
, pipe
);
2082 assert_sprites_disabled(dev_priv
, pipe
);
2084 reg
= PIPECONF(cpu_transcoder
);
2085 val
= I915_READ(reg
);
2086 if ((val
& PIPECONF_ENABLE
) == 0)
2090 * Double wide has implications for planes
2091 * so best keep it disabled when not needed.
2093 if (crtc
->config
.double_wide
)
2094 val
&= ~PIPECONF_DOUBLE_WIDE
;
2096 /* Don't disable pipe or pipe PLLs if needed */
2097 if (!(pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) &&
2098 !(pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
2099 val
&= ~PIPECONF_ENABLE
;
2101 I915_WRITE(reg
, val
);
2102 if ((val
& PIPECONF_ENABLE
) == 0)
2103 intel_wait_for_pipe_off(crtc
);
2107 * Plane regs are double buffered, going from enabled->disabled needs a
2108 * trigger in order to latch. The display address reg provides this.
2110 void intel_flush_primary_plane(struct drm_i915_private
*dev_priv
,
2113 struct drm_device
*dev
= dev_priv
->dev
;
2114 u32 reg
= INTEL_INFO(dev
)->gen
>= 4 ? DSPSURF(plane
) : DSPADDR(plane
);
2116 I915_WRITE(reg
, I915_READ(reg
));
2121 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2122 * @plane: plane to be enabled
2123 * @crtc: crtc for the plane
2125 * Enable @plane on @crtc, making sure that the pipe is running first.
2127 static void intel_enable_primary_hw_plane(struct drm_plane
*plane
,
2128 struct drm_crtc
*crtc
)
2130 struct drm_device
*dev
= plane
->dev
;
2131 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2132 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2134 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2135 assert_pipe_enabled(dev_priv
, intel_crtc
->pipe
);
2137 if (intel_crtc
->primary_enabled
)
2140 intel_crtc
->primary_enabled
= true;
2142 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
2146 * BDW signals flip done immediately if the plane
2147 * is disabled, even if the plane enable is already
2148 * armed to occur at the next vblank :(
2150 if (IS_BROADWELL(dev
))
2151 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2155 * intel_disable_primary_hw_plane - disable the primary hardware plane
2156 * @plane: plane to be disabled
2157 * @crtc: crtc for the plane
2159 * Disable @plane on @crtc, making sure that the pipe is running first.
2161 static void intel_disable_primary_hw_plane(struct drm_plane
*plane
,
2162 struct drm_crtc
*crtc
)
2164 struct drm_device
*dev
= plane
->dev
;
2165 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2166 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2168 assert_pipe_enabled(dev_priv
, intel_crtc
->pipe
);
2170 if (!intel_crtc
->primary_enabled
)
2173 intel_crtc
->primary_enabled
= false;
2175 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
2179 static bool need_vtd_wa(struct drm_device
*dev
)
2181 #ifdef CONFIG_INTEL_IOMMU
2182 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
2188 static int intel_align_height(struct drm_device
*dev
, int height
, bool tiled
)
2192 tile_height
= tiled
? (IS_GEN2(dev
) ? 16 : 8) : 1;
2193 return ALIGN(height
, tile_height
);
2197 intel_pin_and_fence_fb_obj(struct drm_plane
*plane
,
2198 struct drm_framebuffer
*fb
,
2199 struct intel_engine_cs
*pipelined
)
2201 struct drm_device
*dev
= fb
->dev
;
2202 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2203 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2207 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2209 switch (obj
->tiling_mode
) {
2210 case I915_TILING_NONE
:
2211 if (INTEL_INFO(dev
)->gen
>= 9)
2212 alignment
= 256 * 1024;
2213 else if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
2214 alignment
= 128 * 1024;
2215 else if (INTEL_INFO(dev
)->gen
>= 4)
2216 alignment
= 4 * 1024;
2218 alignment
= 64 * 1024;
2221 if (INTEL_INFO(dev
)->gen
>= 9)
2222 alignment
= 256 * 1024;
2224 /* pin() will align the object as required by fence */
2229 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2235 /* Note that the w/a also requires 64 PTE of padding following the
2236 * bo. We currently fill all unused PTE with the shadow page and so
2237 * we should always have valid PTE following the scanout preventing
2240 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
2241 alignment
= 256 * 1024;
2244 * Global gtt pte registers are special registers which actually forward
2245 * writes to a chunk of system memory. Which means that there is no risk
2246 * that the register values disappear as soon as we call
2247 * intel_runtime_pm_put(), so it is correct to wrap only the
2248 * pin/unpin/fence and not more.
2250 intel_runtime_pm_get(dev_priv
);
2252 dev_priv
->mm
.interruptible
= false;
2253 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
);
2255 goto err_interruptible
;
2257 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2258 * fence, whereas 965+ only requires a fence if using
2259 * framebuffer compression. For simplicity, we always install
2260 * a fence as the cost is not that onerous.
2262 ret
= i915_gem_object_get_fence(obj
);
2266 i915_gem_object_pin_fence(obj
);
2268 dev_priv
->mm
.interruptible
= true;
2269 intel_runtime_pm_put(dev_priv
);
2273 i915_gem_object_unpin_from_display_plane(obj
);
2275 dev_priv
->mm
.interruptible
= true;
2276 intel_runtime_pm_put(dev_priv
);
2280 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
)
2282 WARN_ON(!mutex_is_locked(&obj
->base
.dev
->struct_mutex
));
2284 i915_gem_object_unpin_fence(obj
);
2285 i915_gem_object_unpin_from_display_plane(obj
);
2288 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2289 * is assumed to be a power-of-two. */
2290 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
2291 unsigned int tiling_mode
,
2295 if (tiling_mode
!= I915_TILING_NONE
) {
2296 unsigned int tile_rows
, tiles
;
2301 tiles
= *x
/ (512/cpp
);
2304 return tile_rows
* pitch
* 8 + tiles
* 4096;
2306 unsigned int offset
;
2308 offset
= *y
* pitch
+ *x
* cpp
;
2310 *x
= (offset
& 4095) / cpp
;
2311 return offset
& -4096;
2315 int intel_format_to_fourcc(int format
)
2318 case DISPPLANE_8BPP
:
2319 return DRM_FORMAT_C8
;
2320 case DISPPLANE_BGRX555
:
2321 return DRM_FORMAT_XRGB1555
;
2322 case DISPPLANE_BGRX565
:
2323 return DRM_FORMAT_RGB565
;
2325 case DISPPLANE_BGRX888
:
2326 return DRM_FORMAT_XRGB8888
;
2327 case DISPPLANE_RGBX888
:
2328 return DRM_FORMAT_XBGR8888
;
2329 case DISPPLANE_BGRX101010
:
2330 return DRM_FORMAT_XRGB2101010
;
2331 case DISPPLANE_RGBX101010
:
2332 return DRM_FORMAT_XBGR2101010
;
2336 static bool intel_alloc_plane_obj(struct intel_crtc
*crtc
,
2337 struct intel_plane_config
*plane_config
)
2339 struct drm_device
*dev
= crtc
->base
.dev
;
2340 struct drm_i915_gem_object
*obj
= NULL
;
2341 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
2342 u32 base
= plane_config
->base
;
2344 if (plane_config
->size
== 0)
2347 obj
= i915_gem_object_create_stolen_for_preallocated(dev
, base
, base
,
2348 plane_config
->size
);
2352 if (plane_config
->tiled
) {
2353 obj
->tiling_mode
= I915_TILING_X
;
2354 obj
->stride
= crtc
->base
.primary
->fb
->pitches
[0];
2357 mode_cmd
.pixel_format
= crtc
->base
.primary
->fb
->pixel_format
;
2358 mode_cmd
.width
= crtc
->base
.primary
->fb
->width
;
2359 mode_cmd
.height
= crtc
->base
.primary
->fb
->height
;
2360 mode_cmd
.pitches
[0] = crtc
->base
.primary
->fb
->pitches
[0];
2362 mutex_lock(&dev
->struct_mutex
);
2364 if (intel_framebuffer_init(dev
, to_intel_framebuffer(crtc
->base
.primary
->fb
),
2366 DRM_DEBUG_KMS("intel fb init failed\n");
2370 obj
->frontbuffer_bits
= INTEL_FRONTBUFFER_PRIMARY(crtc
->pipe
);
2371 mutex_unlock(&dev
->struct_mutex
);
2373 DRM_DEBUG_KMS("plane fb obj %p\n", obj
);
2377 drm_gem_object_unreference(&obj
->base
);
2378 mutex_unlock(&dev
->struct_mutex
);
2382 static void intel_find_plane_obj(struct intel_crtc
*intel_crtc
,
2383 struct intel_plane_config
*plane_config
)
2385 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2386 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2388 struct intel_crtc
*i
;
2389 struct drm_i915_gem_object
*obj
;
2391 if (!intel_crtc
->base
.primary
->fb
)
2394 if (intel_alloc_plane_obj(intel_crtc
, plane_config
))
2397 kfree(intel_crtc
->base
.primary
->fb
);
2398 intel_crtc
->base
.primary
->fb
= NULL
;
2401 * Failed to alloc the obj, check to see if we should share
2402 * an fb with another CRTC instead
2404 for_each_crtc(dev
, c
) {
2405 i
= to_intel_crtc(c
);
2407 if (c
== &intel_crtc
->base
)
2413 obj
= intel_fb_obj(c
->primary
->fb
);
2417 if (i915_gem_obj_ggtt_offset(obj
) == plane_config
->base
) {
2418 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2419 dev_priv
->preserve_bios_swizzle
= true;
2421 drm_framebuffer_reference(c
->primary
->fb
);
2422 intel_crtc
->base
.primary
->fb
= c
->primary
->fb
;
2423 obj
->frontbuffer_bits
|= INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
);
2429 static void i9xx_update_primary_plane(struct drm_crtc
*crtc
,
2430 struct drm_framebuffer
*fb
,
2433 struct drm_device
*dev
= crtc
->dev
;
2434 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2435 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2436 struct drm_i915_gem_object
*obj
;
2437 int plane
= intel_crtc
->plane
;
2438 unsigned long linear_offset
;
2440 u32 reg
= DSPCNTR(plane
);
2443 if (!intel_crtc
->primary_enabled
) {
2445 if (INTEL_INFO(dev
)->gen
>= 4)
2446 I915_WRITE(DSPSURF(plane
), 0);
2448 I915_WRITE(DSPADDR(plane
), 0);
2453 obj
= intel_fb_obj(fb
);
2454 if (WARN_ON(obj
== NULL
))
2457 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2459 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2461 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2463 if (INTEL_INFO(dev
)->gen
< 4) {
2464 if (intel_crtc
->pipe
== PIPE_B
)
2465 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
2467 /* pipesrc and dspsize control the size that is scaled from,
2468 * which should always be the user's requested size.
2470 I915_WRITE(DSPSIZE(plane
),
2471 ((intel_crtc
->config
.pipe_src_h
- 1) << 16) |
2472 (intel_crtc
->config
.pipe_src_w
- 1));
2473 I915_WRITE(DSPPOS(plane
), 0);
2474 } else if (IS_CHERRYVIEW(dev
) && plane
== PLANE_B
) {
2475 I915_WRITE(PRIMSIZE(plane
),
2476 ((intel_crtc
->config
.pipe_src_h
- 1) << 16) |
2477 (intel_crtc
->config
.pipe_src_w
- 1));
2478 I915_WRITE(PRIMPOS(plane
), 0);
2479 I915_WRITE(PRIMCNSTALPHA(plane
), 0);
2482 switch (fb
->pixel_format
) {
2484 dspcntr
|= DISPPLANE_8BPP
;
2486 case DRM_FORMAT_XRGB1555
:
2487 case DRM_FORMAT_ARGB1555
:
2488 dspcntr
|= DISPPLANE_BGRX555
;
2490 case DRM_FORMAT_RGB565
:
2491 dspcntr
|= DISPPLANE_BGRX565
;
2493 case DRM_FORMAT_XRGB8888
:
2494 case DRM_FORMAT_ARGB8888
:
2495 dspcntr
|= DISPPLANE_BGRX888
;
2497 case DRM_FORMAT_XBGR8888
:
2498 case DRM_FORMAT_ABGR8888
:
2499 dspcntr
|= DISPPLANE_RGBX888
;
2501 case DRM_FORMAT_XRGB2101010
:
2502 case DRM_FORMAT_ARGB2101010
:
2503 dspcntr
|= DISPPLANE_BGRX101010
;
2505 case DRM_FORMAT_XBGR2101010
:
2506 case DRM_FORMAT_ABGR2101010
:
2507 dspcntr
|= DISPPLANE_RGBX101010
;
2513 if (INTEL_INFO(dev
)->gen
>= 4 &&
2514 obj
->tiling_mode
!= I915_TILING_NONE
)
2515 dspcntr
|= DISPPLANE_TILED
;
2518 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2520 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2522 if (INTEL_INFO(dev
)->gen
>= 4) {
2523 intel_crtc
->dspaddr_offset
=
2524 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2527 linear_offset
-= intel_crtc
->dspaddr_offset
;
2529 intel_crtc
->dspaddr_offset
= linear_offset
;
2532 if (to_intel_plane(crtc
->primary
)->rotation
== BIT(DRM_ROTATE_180
)) {
2533 dspcntr
|= DISPPLANE_ROTATE_180
;
2535 x
+= (intel_crtc
->config
.pipe_src_w
- 1);
2536 y
+= (intel_crtc
->config
.pipe_src_h
- 1);
2538 /* Finding the last pixel of the last line of the display
2539 data and adding to linear_offset*/
2541 (intel_crtc
->config
.pipe_src_h
- 1) * fb
->pitches
[0] +
2542 (intel_crtc
->config
.pipe_src_w
- 1) * pixel_size
;
2545 I915_WRITE(reg
, dspcntr
);
2547 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2548 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2550 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2551 if (INTEL_INFO(dev
)->gen
>= 4) {
2552 I915_WRITE(DSPSURF(plane
),
2553 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2554 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2555 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2557 I915_WRITE(DSPADDR(plane
), i915_gem_obj_ggtt_offset(obj
) + linear_offset
);
2561 static void ironlake_update_primary_plane(struct drm_crtc
*crtc
,
2562 struct drm_framebuffer
*fb
,
2565 struct drm_device
*dev
= crtc
->dev
;
2566 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2567 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2568 struct drm_i915_gem_object
*obj
;
2569 int plane
= intel_crtc
->plane
;
2570 unsigned long linear_offset
;
2572 u32 reg
= DSPCNTR(plane
);
2575 if (!intel_crtc
->primary_enabled
) {
2577 I915_WRITE(DSPSURF(plane
), 0);
2582 obj
= intel_fb_obj(fb
);
2583 if (WARN_ON(obj
== NULL
))
2586 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2588 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2590 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2592 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2593 dspcntr
|= DISPPLANE_PIPE_CSC_ENABLE
;
2595 switch (fb
->pixel_format
) {
2597 dspcntr
|= DISPPLANE_8BPP
;
2599 case DRM_FORMAT_RGB565
:
2600 dspcntr
|= DISPPLANE_BGRX565
;
2602 case DRM_FORMAT_XRGB8888
:
2603 case DRM_FORMAT_ARGB8888
:
2604 dspcntr
|= DISPPLANE_BGRX888
;
2606 case DRM_FORMAT_XBGR8888
:
2607 case DRM_FORMAT_ABGR8888
:
2608 dspcntr
|= DISPPLANE_RGBX888
;
2610 case DRM_FORMAT_XRGB2101010
:
2611 case DRM_FORMAT_ARGB2101010
:
2612 dspcntr
|= DISPPLANE_BGRX101010
;
2614 case DRM_FORMAT_XBGR2101010
:
2615 case DRM_FORMAT_ABGR2101010
:
2616 dspcntr
|= DISPPLANE_RGBX101010
;
2622 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2623 dspcntr
|= DISPPLANE_TILED
;
2625 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
))
2626 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2628 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2629 intel_crtc
->dspaddr_offset
=
2630 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2633 linear_offset
-= intel_crtc
->dspaddr_offset
;
2634 if (to_intel_plane(crtc
->primary
)->rotation
== BIT(DRM_ROTATE_180
)) {
2635 dspcntr
|= DISPPLANE_ROTATE_180
;
2637 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
)) {
2638 x
+= (intel_crtc
->config
.pipe_src_w
- 1);
2639 y
+= (intel_crtc
->config
.pipe_src_h
- 1);
2641 /* Finding the last pixel of the last line of the display
2642 data and adding to linear_offset*/
2644 (intel_crtc
->config
.pipe_src_h
- 1) * fb
->pitches
[0] +
2645 (intel_crtc
->config
.pipe_src_w
- 1) * pixel_size
;
2649 I915_WRITE(reg
, dspcntr
);
2651 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2652 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2654 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2655 I915_WRITE(DSPSURF(plane
),
2656 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2657 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2658 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2660 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2661 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2666 static void skylake_update_primary_plane(struct drm_crtc
*crtc
,
2667 struct drm_framebuffer
*fb
,
2670 struct drm_device
*dev
= crtc
->dev
;
2671 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2672 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2673 struct intel_framebuffer
*intel_fb
;
2674 struct drm_i915_gem_object
*obj
;
2675 int pipe
= intel_crtc
->pipe
;
2676 u32 plane_ctl
, stride
;
2678 if (!intel_crtc
->primary_enabled
) {
2679 I915_WRITE(PLANE_CTL(pipe
, 0), 0);
2680 I915_WRITE(PLANE_SURF(pipe
, 0), 0);
2681 POSTING_READ(PLANE_CTL(pipe
, 0));
2685 plane_ctl
= PLANE_CTL_ENABLE
|
2686 PLANE_CTL_PIPE_GAMMA_ENABLE
|
2687 PLANE_CTL_PIPE_CSC_ENABLE
;
2689 switch (fb
->pixel_format
) {
2690 case DRM_FORMAT_RGB565
:
2691 plane_ctl
|= PLANE_CTL_FORMAT_RGB_565
;
2693 case DRM_FORMAT_XRGB8888
:
2694 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_8888
;
2696 case DRM_FORMAT_XBGR8888
:
2697 plane_ctl
|= PLANE_CTL_ORDER_RGBX
;
2698 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_8888
;
2700 case DRM_FORMAT_XRGB2101010
:
2701 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_2101010
;
2703 case DRM_FORMAT_XBGR2101010
:
2704 plane_ctl
|= PLANE_CTL_ORDER_RGBX
;
2705 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_2101010
;
2711 intel_fb
= to_intel_framebuffer(fb
);
2712 obj
= intel_fb
->obj
;
2715 * The stride is either expressed as a multiple of 64 bytes chunks for
2716 * linear buffers or in number of tiles for tiled buffers.
2718 switch (obj
->tiling_mode
) {
2719 case I915_TILING_NONE
:
2720 stride
= fb
->pitches
[0] >> 6;
2723 plane_ctl
|= PLANE_CTL_TILED_X
;
2724 stride
= fb
->pitches
[0] >> 9;
2730 plane_ctl
|= PLANE_CTL_PLANE_GAMMA_DISABLE
;
2731 if (to_intel_plane(crtc
->primary
)->rotation
== BIT(DRM_ROTATE_180
))
2732 plane_ctl
|= PLANE_CTL_ROTATE_180
;
2734 I915_WRITE(PLANE_CTL(pipe
, 0), plane_ctl
);
2736 DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2737 i915_gem_obj_ggtt_offset(obj
),
2738 x
, y
, fb
->width
, fb
->height
,
2741 I915_WRITE(PLANE_POS(pipe
, 0), 0);
2742 I915_WRITE(PLANE_OFFSET(pipe
, 0), (y
<< 16) | x
);
2743 I915_WRITE(PLANE_SIZE(pipe
, 0),
2744 (intel_crtc
->config
.pipe_src_h
- 1) << 16 |
2745 (intel_crtc
->config
.pipe_src_w
- 1));
2746 I915_WRITE(PLANE_STRIDE(pipe
, 0), stride
);
2747 I915_WRITE(PLANE_SURF(pipe
, 0), i915_gem_obj_ggtt_offset(obj
));
2749 POSTING_READ(PLANE_SURF(pipe
, 0));
2752 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2754 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2755 int x
, int y
, enum mode_set_atomic state
)
2757 struct drm_device
*dev
= crtc
->dev
;
2758 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2760 if (dev_priv
->display
.disable_fbc
)
2761 dev_priv
->display
.disable_fbc(dev
);
2763 dev_priv
->display
.update_primary_plane(crtc
, fb
, x
, y
);
2768 void intel_display_handle_reset(struct drm_device
*dev
)
2770 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2771 struct drm_crtc
*crtc
;
2774 * Flips in the rings have been nuked by the reset,
2775 * so complete all pending flips so that user space
2776 * will get its events and not get stuck.
2778 * Also update the base address of all primary
2779 * planes to the the last fb to make sure we're
2780 * showing the correct fb after a reset.
2782 * Need to make two loops over the crtcs so that we
2783 * don't try to grab a crtc mutex before the
2784 * pending_flip_queue really got woken up.
2787 for_each_crtc(dev
, crtc
) {
2788 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2789 enum plane plane
= intel_crtc
->plane
;
2791 intel_prepare_page_flip(dev
, plane
);
2792 intel_finish_page_flip_plane(dev
, plane
);
2795 for_each_crtc(dev
, crtc
) {
2796 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2798 drm_modeset_lock(&crtc
->mutex
, NULL
);
2800 * FIXME: Once we have proper support for primary planes (and
2801 * disabling them without disabling the entire crtc) allow again
2802 * a NULL crtc->primary->fb.
2804 if (intel_crtc
->active
&& crtc
->primary
->fb
)
2805 dev_priv
->display
.update_primary_plane(crtc
,
2809 drm_modeset_unlock(&crtc
->mutex
);
2814 intel_finish_fb(struct drm_framebuffer
*old_fb
)
2816 struct drm_i915_gem_object
*obj
= intel_fb_obj(old_fb
);
2817 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2818 bool was_interruptible
= dev_priv
->mm
.interruptible
;
2821 /* Big Hammer, we also need to ensure that any pending
2822 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2823 * current scanout is retired before unpinning the old
2826 * This should only fail upon a hung GPU, in which case we
2827 * can safely continue.
2829 dev_priv
->mm
.interruptible
= false;
2830 ret
= i915_gem_object_finish_gpu(obj
);
2831 dev_priv
->mm
.interruptible
= was_interruptible
;
2836 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
2838 struct drm_device
*dev
= crtc
->dev
;
2839 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2840 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2843 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
2844 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
2847 spin_lock_irq(&dev
->event_lock
);
2848 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
2849 spin_unlock_irq(&dev
->event_lock
);
2854 static void intel_update_pipe_size(struct intel_crtc
*crtc
)
2856 struct drm_device
*dev
= crtc
->base
.dev
;
2857 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2858 const struct drm_display_mode
*adjusted_mode
;
2864 * Update pipe size and adjust fitter if needed: the reason for this is
2865 * that in compute_mode_changes we check the native mode (not the pfit
2866 * mode) to see if we can flip rather than do a full mode set. In the
2867 * fastboot case, we'll flip, but if we don't update the pipesrc and
2868 * pfit state, we'll end up with a big fb scanned out into the wrong
2871 * To fix this properly, we need to hoist the checks up into
2872 * compute_mode_changes (or above), check the actual pfit state and
2873 * whether the platform allows pfit disable with pipe active, and only
2874 * then update the pipesrc and pfit state, even on the flip path.
2877 adjusted_mode
= &crtc
->config
.adjusted_mode
;
2879 I915_WRITE(PIPESRC(crtc
->pipe
),
2880 ((adjusted_mode
->crtc_hdisplay
- 1) << 16) |
2881 (adjusted_mode
->crtc_vdisplay
- 1));
2882 if (!crtc
->config
.pch_pfit
.enabled
&&
2883 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) ||
2884 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
2885 I915_WRITE(PF_CTL(crtc
->pipe
), 0);
2886 I915_WRITE(PF_WIN_POS(crtc
->pipe
), 0);
2887 I915_WRITE(PF_WIN_SZ(crtc
->pipe
), 0);
2889 crtc
->config
.pipe_src_w
= adjusted_mode
->crtc_hdisplay
;
2890 crtc
->config
.pipe_src_h
= adjusted_mode
->crtc_vdisplay
;
2894 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2895 struct drm_framebuffer
*fb
)
2897 struct drm_device
*dev
= crtc
->dev
;
2898 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2899 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2900 enum pipe pipe
= intel_crtc
->pipe
;
2901 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
2902 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(old_fb
);
2905 if (intel_crtc_has_pending_flip(crtc
)) {
2906 DRM_ERROR("pipe is still busy with an old pageflip\n");
2912 DRM_ERROR("No FB bound\n");
2916 if (intel_crtc
->plane
> INTEL_INFO(dev
)->num_pipes
) {
2917 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2918 plane_name(intel_crtc
->plane
),
2919 INTEL_INFO(dev
)->num_pipes
);
2923 mutex_lock(&dev
->struct_mutex
);
2924 ret
= intel_pin_and_fence_fb_obj(crtc
->primary
, fb
, NULL
);
2926 i915_gem_track_fb(old_obj
, intel_fb_obj(fb
),
2927 INTEL_FRONTBUFFER_PRIMARY(pipe
));
2928 mutex_unlock(&dev
->struct_mutex
);
2930 DRM_ERROR("pin & fence failed\n");
2934 intel_update_pipe_size(intel_crtc
);
2936 dev_priv
->display
.update_primary_plane(crtc
, fb
, x
, y
);
2938 if (intel_crtc
->active
)
2939 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
2941 crtc
->primary
->fb
= fb
;
2946 if (intel_crtc
->active
&& old_fb
!= fb
)
2947 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2948 mutex_lock(&dev
->struct_mutex
);
2949 intel_unpin_fb_obj(old_obj
);
2950 mutex_unlock(&dev
->struct_mutex
);
2953 mutex_lock(&dev
->struct_mutex
);
2954 intel_update_fbc(dev
);
2955 mutex_unlock(&dev
->struct_mutex
);
2960 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
2962 struct drm_device
*dev
= crtc
->dev
;
2963 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2964 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2965 int pipe
= intel_crtc
->pipe
;
2968 /* enable normal train */
2969 reg
= FDI_TX_CTL(pipe
);
2970 temp
= I915_READ(reg
);
2971 if (IS_IVYBRIDGE(dev
)) {
2972 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2973 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2975 temp
&= ~FDI_LINK_TRAIN_NONE
;
2976 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2978 I915_WRITE(reg
, temp
);
2980 reg
= FDI_RX_CTL(pipe
);
2981 temp
= I915_READ(reg
);
2982 if (HAS_PCH_CPT(dev
)) {
2983 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2984 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2986 temp
&= ~FDI_LINK_TRAIN_NONE
;
2987 temp
|= FDI_LINK_TRAIN_NONE
;
2989 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2991 /* wait one idle pattern time */
2995 /* IVB wants error correction enabled */
2996 if (IS_IVYBRIDGE(dev
))
2997 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
2998 FDI_FE_ERRC_ENABLE
);
3001 static bool pipe_has_enabled_pch(struct intel_crtc
*crtc
)
3003 return crtc
->base
.enabled
&& crtc
->active
&&
3004 crtc
->config
.has_pch_encoder
;
3007 static void ivb_modeset_global_resources(struct drm_device
*dev
)
3009 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3010 struct intel_crtc
*pipe_B_crtc
=
3011 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
3012 struct intel_crtc
*pipe_C_crtc
=
3013 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]);
3017 * When everything is off disable fdi C so that we could enable fdi B
3018 * with all lanes. Note that we don't care about enabled pipes without
3019 * an enabled pch encoder.
3021 if (!pipe_has_enabled_pch(pipe_B_crtc
) &&
3022 !pipe_has_enabled_pch(pipe_C_crtc
)) {
3023 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
3024 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
3026 temp
= I915_READ(SOUTH_CHICKEN1
);
3027 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
3028 DRM_DEBUG_KMS("disabling fdi C rx\n");
3029 I915_WRITE(SOUTH_CHICKEN1
, temp
);
3033 /* The FDI link training functions for ILK/Ibexpeak. */
3034 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
3036 struct drm_device
*dev
= crtc
->dev
;
3037 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3038 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3039 int pipe
= intel_crtc
->pipe
;
3040 u32 reg
, temp
, tries
;
3042 /* FDI needs bits from pipe first */
3043 assert_pipe_enabled(dev_priv
, pipe
);
3045 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3047 reg
= FDI_RX_IMR(pipe
);
3048 temp
= I915_READ(reg
);
3049 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3050 temp
&= ~FDI_RX_BIT_LOCK
;
3051 I915_WRITE(reg
, temp
);
3055 /* enable CPU FDI TX and PCH FDI RX */
3056 reg
= FDI_TX_CTL(pipe
);
3057 temp
= I915_READ(reg
);
3058 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3059 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
3060 temp
&= ~FDI_LINK_TRAIN_NONE
;
3061 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3062 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3064 reg
= FDI_RX_CTL(pipe
);
3065 temp
= I915_READ(reg
);
3066 temp
&= ~FDI_LINK_TRAIN_NONE
;
3067 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3068 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3073 /* Ironlake workaround, enable clock pointer after FDI enable*/
3074 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3075 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
3076 FDI_RX_PHASE_SYNC_POINTER_EN
);
3078 reg
= FDI_RX_IIR(pipe
);
3079 for (tries
= 0; tries
< 5; tries
++) {
3080 temp
= I915_READ(reg
);
3081 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3083 if ((temp
& FDI_RX_BIT_LOCK
)) {
3084 DRM_DEBUG_KMS("FDI train 1 done.\n");
3085 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3090 DRM_ERROR("FDI train 1 fail!\n");
3093 reg
= FDI_TX_CTL(pipe
);
3094 temp
= I915_READ(reg
);
3095 temp
&= ~FDI_LINK_TRAIN_NONE
;
3096 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3097 I915_WRITE(reg
, temp
);
3099 reg
= FDI_RX_CTL(pipe
);
3100 temp
= I915_READ(reg
);
3101 temp
&= ~FDI_LINK_TRAIN_NONE
;
3102 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3103 I915_WRITE(reg
, temp
);
3108 reg
= FDI_RX_IIR(pipe
);
3109 for (tries
= 0; tries
< 5; tries
++) {
3110 temp
= I915_READ(reg
);
3111 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3113 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3114 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3115 DRM_DEBUG_KMS("FDI train 2 done.\n");
3120 DRM_ERROR("FDI train 2 fail!\n");
3122 DRM_DEBUG_KMS("FDI train done\n");
3126 static const int snb_b_fdi_train_param
[] = {
3127 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
3128 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
3129 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
3130 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
3133 /* The FDI link training functions for SNB/Cougarpoint. */
3134 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
3136 struct drm_device
*dev
= crtc
->dev
;
3137 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3138 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3139 int pipe
= intel_crtc
->pipe
;
3140 u32 reg
, temp
, i
, retry
;
3142 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3144 reg
= FDI_RX_IMR(pipe
);
3145 temp
= I915_READ(reg
);
3146 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3147 temp
&= ~FDI_RX_BIT_LOCK
;
3148 I915_WRITE(reg
, temp
);
3153 /* enable CPU FDI TX and PCH FDI RX */
3154 reg
= FDI_TX_CTL(pipe
);
3155 temp
= I915_READ(reg
);
3156 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3157 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
3158 temp
&= ~FDI_LINK_TRAIN_NONE
;
3159 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3160 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3162 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3163 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3165 I915_WRITE(FDI_RX_MISC(pipe
),
3166 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3168 reg
= FDI_RX_CTL(pipe
);
3169 temp
= I915_READ(reg
);
3170 if (HAS_PCH_CPT(dev
)) {
3171 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3172 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3174 temp
&= ~FDI_LINK_TRAIN_NONE
;
3175 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3177 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3182 for (i
= 0; i
< 4; i
++) {
3183 reg
= FDI_TX_CTL(pipe
);
3184 temp
= I915_READ(reg
);
3185 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3186 temp
|= snb_b_fdi_train_param
[i
];
3187 I915_WRITE(reg
, temp
);
3192 for (retry
= 0; retry
< 5; retry
++) {
3193 reg
= FDI_RX_IIR(pipe
);
3194 temp
= I915_READ(reg
);
3195 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3196 if (temp
& FDI_RX_BIT_LOCK
) {
3197 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3198 DRM_DEBUG_KMS("FDI train 1 done.\n");
3207 DRM_ERROR("FDI train 1 fail!\n");
3210 reg
= FDI_TX_CTL(pipe
);
3211 temp
= I915_READ(reg
);
3212 temp
&= ~FDI_LINK_TRAIN_NONE
;
3213 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3215 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3217 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3219 I915_WRITE(reg
, temp
);
3221 reg
= FDI_RX_CTL(pipe
);
3222 temp
= I915_READ(reg
);
3223 if (HAS_PCH_CPT(dev
)) {
3224 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3225 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3227 temp
&= ~FDI_LINK_TRAIN_NONE
;
3228 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3230 I915_WRITE(reg
, temp
);
3235 for (i
= 0; i
< 4; i
++) {
3236 reg
= FDI_TX_CTL(pipe
);
3237 temp
= I915_READ(reg
);
3238 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3239 temp
|= snb_b_fdi_train_param
[i
];
3240 I915_WRITE(reg
, temp
);
3245 for (retry
= 0; retry
< 5; retry
++) {
3246 reg
= FDI_RX_IIR(pipe
);
3247 temp
= I915_READ(reg
);
3248 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3249 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3250 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3251 DRM_DEBUG_KMS("FDI train 2 done.\n");
3260 DRM_ERROR("FDI train 2 fail!\n");
3262 DRM_DEBUG_KMS("FDI train done.\n");
3265 /* Manual link training for Ivy Bridge A0 parts */
3266 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
3268 struct drm_device
*dev
= crtc
->dev
;
3269 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3270 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3271 int pipe
= intel_crtc
->pipe
;
3272 u32 reg
, temp
, i
, j
;
3274 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3276 reg
= FDI_RX_IMR(pipe
);
3277 temp
= I915_READ(reg
);
3278 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3279 temp
&= ~FDI_RX_BIT_LOCK
;
3280 I915_WRITE(reg
, temp
);
3285 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3286 I915_READ(FDI_RX_IIR(pipe
)));
3288 /* Try each vswing and preemphasis setting twice before moving on */
3289 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
3290 /* disable first in case we need to retry */
3291 reg
= FDI_TX_CTL(pipe
);
3292 temp
= I915_READ(reg
);
3293 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
3294 temp
&= ~FDI_TX_ENABLE
;
3295 I915_WRITE(reg
, temp
);
3297 reg
= FDI_RX_CTL(pipe
);
3298 temp
= I915_READ(reg
);
3299 temp
&= ~FDI_LINK_TRAIN_AUTO
;
3300 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3301 temp
&= ~FDI_RX_ENABLE
;
3302 I915_WRITE(reg
, temp
);
3304 /* enable CPU FDI TX and PCH FDI RX */
3305 reg
= FDI_TX_CTL(pipe
);
3306 temp
= I915_READ(reg
);
3307 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3308 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
3309 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
3310 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3311 temp
|= snb_b_fdi_train_param
[j
/2];
3312 temp
|= FDI_COMPOSITE_SYNC
;
3313 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3315 I915_WRITE(FDI_RX_MISC(pipe
),
3316 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3318 reg
= FDI_RX_CTL(pipe
);
3319 temp
= I915_READ(reg
);
3320 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3321 temp
|= FDI_COMPOSITE_SYNC
;
3322 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3325 udelay(1); /* should be 0.5us */
3327 for (i
= 0; i
< 4; i
++) {
3328 reg
= FDI_RX_IIR(pipe
);
3329 temp
= I915_READ(reg
);
3330 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3332 if (temp
& FDI_RX_BIT_LOCK
||
3333 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
3334 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3335 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3339 udelay(1); /* should be 0.5us */
3342 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
3347 reg
= FDI_TX_CTL(pipe
);
3348 temp
= I915_READ(reg
);
3349 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3350 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
3351 I915_WRITE(reg
, temp
);
3353 reg
= FDI_RX_CTL(pipe
);
3354 temp
= I915_READ(reg
);
3355 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3356 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3357 I915_WRITE(reg
, temp
);
3360 udelay(2); /* should be 1.5us */
3362 for (i
= 0; i
< 4; i
++) {
3363 reg
= FDI_RX_IIR(pipe
);
3364 temp
= I915_READ(reg
);
3365 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3367 if (temp
& FDI_RX_SYMBOL_LOCK
||
3368 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
3369 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3370 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3374 udelay(2); /* should be 1.5us */
3377 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
3381 DRM_DEBUG_KMS("FDI train done.\n");
3384 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
3386 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3387 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3388 int pipe
= intel_crtc
->pipe
;
3392 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3393 reg
= FDI_RX_CTL(pipe
);
3394 temp
= I915_READ(reg
);
3395 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
3396 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
3397 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3398 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
3403 /* Switch from Rawclk to PCDclk */
3404 temp
= I915_READ(reg
);
3405 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
3410 /* Enable CPU FDI TX PLL, always on for Ironlake */
3411 reg
= FDI_TX_CTL(pipe
);
3412 temp
= I915_READ(reg
);
3413 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
3414 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
3421 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
3423 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3424 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3425 int pipe
= intel_crtc
->pipe
;
3428 /* Switch from PCDclk to Rawclk */
3429 reg
= FDI_RX_CTL(pipe
);
3430 temp
= I915_READ(reg
);
3431 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
3433 /* Disable CPU FDI TX PLL */
3434 reg
= FDI_TX_CTL(pipe
);
3435 temp
= I915_READ(reg
);
3436 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
3441 reg
= FDI_RX_CTL(pipe
);
3442 temp
= I915_READ(reg
);
3443 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
3445 /* Wait for the clocks to turn off. */
3450 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
3452 struct drm_device
*dev
= crtc
->dev
;
3453 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3454 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3455 int pipe
= intel_crtc
->pipe
;
3458 /* disable CPU FDI tx and PCH FDI rx */
3459 reg
= FDI_TX_CTL(pipe
);
3460 temp
= I915_READ(reg
);
3461 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
3464 reg
= FDI_RX_CTL(pipe
);
3465 temp
= I915_READ(reg
);
3466 temp
&= ~(0x7 << 16);
3467 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3468 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
3473 /* Ironlake workaround, disable clock pointer after downing FDI */
3474 if (HAS_PCH_IBX(dev
))
3475 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3477 /* still set train pattern 1 */
3478 reg
= FDI_TX_CTL(pipe
);
3479 temp
= I915_READ(reg
);
3480 temp
&= ~FDI_LINK_TRAIN_NONE
;
3481 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3482 I915_WRITE(reg
, temp
);
3484 reg
= FDI_RX_CTL(pipe
);
3485 temp
= I915_READ(reg
);
3486 if (HAS_PCH_CPT(dev
)) {
3487 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3488 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3490 temp
&= ~FDI_LINK_TRAIN_NONE
;
3491 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3493 /* BPC in FDI rx is consistent with that in PIPECONF */
3494 temp
&= ~(0x07 << 16);
3495 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3496 I915_WRITE(reg
, temp
);
3502 bool intel_has_pending_fb_unpin(struct drm_device
*dev
)
3504 struct intel_crtc
*crtc
;
3506 /* Note that we don't need to be called with mode_config.lock here
3507 * as our list of CRTC objects is static for the lifetime of the
3508 * device and so cannot disappear as we iterate. Similarly, we can
3509 * happily treat the predicates as racy, atomic checks as userspace
3510 * cannot claim and pin a new fb without at least acquring the
3511 * struct_mutex and so serialising with us.
3513 for_each_intel_crtc(dev
, crtc
) {
3514 if (atomic_read(&crtc
->unpin_work_count
) == 0)
3517 if (crtc
->unpin_work
)
3518 intel_wait_for_vblank(dev
, crtc
->pipe
);
3526 static void page_flip_completed(struct intel_crtc
*intel_crtc
)
3528 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
3529 struct intel_unpin_work
*work
= intel_crtc
->unpin_work
;
3531 /* ensure that the unpin work is consistent wrt ->pending. */
3533 intel_crtc
->unpin_work
= NULL
;
3536 drm_send_vblank_event(intel_crtc
->base
.dev
,
3540 drm_crtc_vblank_put(&intel_crtc
->base
);
3542 wake_up_all(&dev_priv
->pending_flip_queue
);
3543 queue_work(dev_priv
->wq
, &work
->work
);
3545 trace_i915_flip_complete(intel_crtc
->plane
,
3546 work
->pending_flip_obj
);
3549 void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
3551 struct drm_device
*dev
= crtc
->dev
;
3552 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3554 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
3555 if (WARN_ON(wait_event_timeout(dev_priv
->pending_flip_queue
,
3556 !intel_crtc_has_pending_flip(crtc
),
3558 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3560 spin_lock_irq(&dev
->event_lock
);
3561 if (intel_crtc
->unpin_work
) {
3562 WARN_ONCE(1, "Removing stuck page flip\n");
3563 page_flip_completed(intel_crtc
);
3565 spin_unlock_irq(&dev
->event_lock
);
3568 if (crtc
->primary
->fb
) {
3569 mutex_lock(&dev
->struct_mutex
);
3570 intel_finish_fb(crtc
->primary
->fb
);
3571 mutex_unlock(&dev
->struct_mutex
);
3575 /* Program iCLKIP clock to the desired frequency */
3576 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
3578 struct drm_device
*dev
= crtc
->dev
;
3579 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3580 int clock
= to_intel_crtc(crtc
)->config
.adjusted_mode
.crtc_clock
;
3581 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
3584 mutex_lock(&dev_priv
->dpio_lock
);
3586 /* It is necessary to ungate the pixclk gate prior to programming
3587 * the divisors, and gate it back when it is done.
3589 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
3591 /* Disable SSCCTL */
3592 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
3593 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
3597 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3598 if (clock
== 20000) {
3603 /* The iCLK virtual clock root frequency is in MHz,
3604 * but the adjusted_mode->crtc_clock in in KHz. To get the
3605 * divisors, it is necessary to divide one by another, so we
3606 * convert the virtual clock precision to KHz here for higher
3609 u32 iclk_virtual_root_freq
= 172800 * 1000;
3610 u32 iclk_pi_range
= 64;
3611 u32 desired_divisor
, msb_divisor_value
, pi_value
;
3613 desired_divisor
= (iclk_virtual_root_freq
/ clock
);
3614 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
3615 pi_value
= desired_divisor
% iclk_pi_range
;
3618 divsel
= msb_divisor_value
- 2;
3619 phaseinc
= pi_value
;
3622 /* This should not happen with any sane values */
3623 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
3624 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
3625 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
3626 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
3628 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3635 /* Program SSCDIVINTPHASE6 */
3636 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
3637 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
3638 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
3639 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
3640 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
3641 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
3642 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
3643 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
3645 /* Program SSCAUXDIV */
3646 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
3647 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3648 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
3649 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
3651 /* Enable modulator and associated divider */
3652 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
3653 temp
&= ~SBI_SSCCTL_DISABLE
;
3654 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
3656 /* Wait for initialization time */
3659 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
3661 mutex_unlock(&dev_priv
->dpio_lock
);
3664 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
3665 enum pipe pch_transcoder
)
3667 struct drm_device
*dev
= crtc
->base
.dev
;
3668 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3669 enum transcoder cpu_transcoder
= crtc
->config
.cpu_transcoder
;
3671 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
3672 I915_READ(HTOTAL(cpu_transcoder
)));
3673 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
3674 I915_READ(HBLANK(cpu_transcoder
)));
3675 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
3676 I915_READ(HSYNC(cpu_transcoder
)));
3678 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
3679 I915_READ(VTOTAL(cpu_transcoder
)));
3680 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
3681 I915_READ(VBLANK(cpu_transcoder
)));
3682 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
3683 I915_READ(VSYNC(cpu_transcoder
)));
3684 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
3685 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
3688 static void cpt_enable_fdi_bc_bifurcation(struct drm_device
*dev
)
3690 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3693 temp
= I915_READ(SOUTH_CHICKEN1
);
3694 if (temp
& FDI_BC_BIFURCATION_SELECT
)
3697 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
3698 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
3700 temp
|= FDI_BC_BIFURCATION_SELECT
;
3701 DRM_DEBUG_KMS("enabling fdi C rx\n");
3702 I915_WRITE(SOUTH_CHICKEN1
, temp
);
3703 POSTING_READ(SOUTH_CHICKEN1
);
3706 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
3708 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3709 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3711 switch (intel_crtc
->pipe
) {
3715 if (intel_crtc
->config
.fdi_lanes
> 2)
3716 WARN_ON(I915_READ(SOUTH_CHICKEN1
) & FDI_BC_BIFURCATION_SELECT
);
3718 cpt_enable_fdi_bc_bifurcation(dev
);
3722 cpt_enable_fdi_bc_bifurcation(dev
);
3731 * Enable PCH resources required for PCH ports:
3733 * - FDI training & RX/TX
3734 * - update transcoder timings
3735 * - DP transcoding bits
3738 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
3740 struct drm_device
*dev
= crtc
->dev
;
3741 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3742 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3743 int pipe
= intel_crtc
->pipe
;
3746 assert_pch_transcoder_disabled(dev_priv
, pipe
);
3748 if (IS_IVYBRIDGE(dev
))
3749 ivybridge_update_fdi_bc_bifurcation(intel_crtc
);
3751 /* Write the TU size bits before fdi link training, so that error
3752 * detection works. */
3753 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
3754 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
3756 /* For PCH output, training FDI link */
3757 dev_priv
->display
.fdi_link_train(crtc
);
3759 /* We need to program the right clock selection before writing the pixel
3760 * mutliplier into the DPLL. */
3761 if (HAS_PCH_CPT(dev
)) {
3764 temp
= I915_READ(PCH_DPLL_SEL
);
3765 temp
|= TRANS_DPLL_ENABLE(pipe
);
3766 sel
= TRANS_DPLLB_SEL(pipe
);
3767 if (intel_crtc
->config
.shared_dpll
== DPLL_ID_PCH_PLL_B
)
3771 I915_WRITE(PCH_DPLL_SEL
, temp
);
3774 /* XXX: pch pll's can be enabled any time before we enable the PCH
3775 * transcoder, and we actually should do this to not upset any PCH
3776 * transcoder that already use the clock when we share it.
3778 * Note that enable_shared_dpll tries to do the right thing, but
3779 * get_shared_dpll unconditionally resets the pll - we need that to have
3780 * the right LVDS enable sequence. */
3781 intel_enable_shared_dpll(intel_crtc
);
3783 /* set transcoder timing, panel must allow it */
3784 assert_panel_unlocked(dev_priv
, pipe
);
3785 ironlake_pch_transcoder_set_timings(intel_crtc
, pipe
);
3787 intel_fdi_normal_train(crtc
);
3789 /* For PCH DP, enable TRANS_DP_CTL */
3790 if (HAS_PCH_CPT(dev
) && intel_crtc
->config
.has_dp_encoder
) {
3791 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
3792 reg
= TRANS_DP_CTL(pipe
);
3793 temp
= I915_READ(reg
);
3794 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
3795 TRANS_DP_SYNC_MASK
|
3797 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
3798 TRANS_DP_ENH_FRAMING
);
3799 temp
|= bpc
<< 9; /* same format but at 11:9 */
3801 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
3802 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
3803 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
3804 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
3806 switch (intel_trans_dp_port_sel(crtc
)) {
3808 temp
|= TRANS_DP_PORT_SEL_B
;
3811 temp
|= TRANS_DP_PORT_SEL_C
;
3814 temp
|= TRANS_DP_PORT_SEL_D
;
3820 I915_WRITE(reg
, temp
);
3823 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
3826 static void lpt_pch_enable(struct drm_crtc
*crtc
)
3828 struct drm_device
*dev
= crtc
->dev
;
3829 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3830 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3831 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
3833 assert_pch_transcoder_disabled(dev_priv
, TRANSCODER_A
);
3835 lpt_program_iclkip(crtc
);
3837 /* Set transcoder timing. */
3838 ironlake_pch_transcoder_set_timings(intel_crtc
, PIPE_A
);
3840 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
3843 void intel_put_shared_dpll(struct intel_crtc
*crtc
)
3845 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3850 if (!(pll
->config
.crtc_mask
& (1 << crtc
->pipe
))) {
3851 WARN(1, "bad %s crtc mask\n", pll
->name
);
3855 pll
->config
.crtc_mask
&= ~(1 << crtc
->pipe
);
3856 if (pll
->config
.crtc_mask
== 0) {
3858 WARN_ON(pll
->active
);
3861 crtc
->config
.shared_dpll
= DPLL_ID_PRIVATE
;
3864 struct intel_shared_dpll
*intel_get_shared_dpll(struct intel_crtc
*crtc
)
3866 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
3867 struct intel_shared_dpll
*pll
;
3868 enum intel_dpll_id i
;
3870 if (HAS_PCH_IBX(dev_priv
->dev
)) {
3871 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3872 i
= (enum intel_dpll_id
) crtc
->pipe
;
3873 pll
= &dev_priv
->shared_dplls
[i
];
3875 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3876 crtc
->base
.base
.id
, pll
->name
);
3878 WARN_ON(pll
->new_config
->crtc_mask
);
3883 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3884 pll
= &dev_priv
->shared_dplls
[i
];
3886 /* Only want to check enabled timings first */
3887 if (pll
->new_config
->crtc_mask
== 0)
3890 if (memcmp(&crtc
->new_config
->dpll_hw_state
,
3891 &pll
->new_config
->hw_state
,
3892 sizeof(pll
->new_config
->hw_state
)) == 0) {
3893 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
3894 crtc
->base
.base
.id
, pll
->name
,
3895 pll
->new_config
->crtc_mask
,
3901 /* Ok no matching timings, maybe there's a free one? */
3902 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3903 pll
= &dev_priv
->shared_dplls
[i
];
3904 if (pll
->new_config
->crtc_mask
== 0) {
3905 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3906 crtc
->base
.base
.id
, pll
->name
);
3914 if (pll
->new_config
->crtc_mask
== 0)
3915 pll
->new_config
->hw_state
= crtc
->new_config
->dpll_hw_state
;
3917 crtc
->new_config
->shared_dpll
= i
;
3918 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll
->name
,
3919 pipe_name(crtc
->pipe
));
3921 pll
->new_config
->crtc_mask
|= 1 << crtc
->pipe
;
3927 * intel_shared_dpll_start_config - start a new PLL staged config
3928 * @dev_priv: DRM device
3929 * @clear_pipes: mask of pipes that will have their PLLs freed
3931 * Starts a new PLL staged config, copying the current config but
3932 * releasing the references of pipes specified in clear_pipes.
3934 static int intel_shared_dpll_start_config(struct drm_i915_private
*dev_priv
,
3935 unsigned clear_pipes
)
3937 struct intel_shared_dpll
*pll
;
3938 enum intel_dpll_id i
;
3940 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3941 pll
= &dev_priv
->shared_dplls
[i
];
3943 pll
->new_config
= kmemdup(&pll
->config
, sizeof pll
->config
,
3945 if (!pll
->new_config
)
3948 pll
->new_config
->crtc_mask
&= ~clear_pipes
;
3955 pll
= &dev_priv
->shared_dplls
[i
];
3956 pll
->new_config
= NULL
;
3962 static void intel_shared_dpll_commit(struct drm_i915_private
*dev_priv
)
3964 struct intel_shared_dpll
*pll
;
3965 enum intel_dpll_id i
;
3967 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3968 pll
= &dev_priv
->shared_dplls
[i
];
3970 WARN_ON(pll
->new_config
== &pll
->config
);
3972 pll
->config
= *pll
->new_config
;
3973 kfree(pll
->new_config
);
3974 pll
->new_config
= NULL
;
3978 static void intel_shared_dpll_abort_config(struct drm_i915_private
*dev_priv
)
3980 struct intel_shared_dpll
*pll
;
3981 enum intel_dpll_id i
;
3983 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3984 pll
= &dev_priv
->shared_dplls
[i
];
3986 WARN_ON(pll
->new_config
== &pll
->config
);
3988 kfree(pll
->new_config
);
3989 pll
->new_config
= NULL
;
3993 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
3995 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3996 int dslreg
= PIPEDSL(pipe
);
3999 temp
= I915_READ(dslreg
);
4001 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
4002 if (wait_for(I915_READ(dslreg
) != temp
, 5))
4003 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
4007 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
4009 struct drm_device
*dev
= crtc
->base
.dev
;
4010 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4011 int pipe
= crtc
->pipe
;
4013 if (crtc
->config
.pch_pfit
.enabled
) {
4014 /* Force use of hard-coded filter coefficients
4015 * as some pre-programmed values are broken,
4018 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
4019 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
4020 PF_PIPE_SEL_IVB(pipe
));
4022 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
4023 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
.pch_pfit
.pos
);
4024 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
.pch_pfit
.size
);
4028 static void intel_enable_planes(struct drm_crtc
*crtc
)
4030 struct drm_device
*dev
= crtc
->dev
;
4031 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
4032 struct drm_plane
*plane
;
4033 struct intel_plane
*intel_plane
;
4035 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
4036 intel_plane
= to_intel_plane(plane
);
4037 if (intel_plane
->pipe
== pipe
)
4038 intel_plane_restore(&intel_plane
->base
);
4042 static void intel_disable_planes(struct drm_crtc
*crtc
)
4044 struct drm_device
*dev
= crtc
->dev
;
4045 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
4046 struct drm_plane
*plane
;
4047 struct intel_plane
*intel_plane
;
4049 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
4050 intel_plane
= to_intel_plane(plane
);
4051 if (intel_plane
->pipe
== pipe
)
4052 intel_plane_disable(&intel_plane
->base
);
4056 void hsw_enable_ips(struct intel_crtc
*crtc
)
4058 struct drm_device
*dev
= crtc
->base
.dev
;
4059 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4061 if (!crtc
->config
.ips_enabled
)
4064 /* We can only enable IPS after we enable a plane and wait for a vblank */
4065 intel_wait_for_vblank(dev
, crtc
->pipe
);
4067 assert_plane_enabled(dev_priv
, crtc
->plane
);
4068 if (IS_BROADWELL(dev
)) {
4069 mutex_lock(&dev_priv
->rps
.hw_lock
);
4070 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0xc0000000));
4071 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4072 /* Quoting Art Runyan: "its not safe to expect any particular
4073 * value in IPS_CTL bit 31 after enabling IPS through the
4074 * mailbox." Moreover, the mailbox may return a bogus state,
4075 * so we need to just enable it and continue on.
4078 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
4079 /* The bit only becomes 1 in the next vblank, so this wait here
4080 * is essentially intel_wait_for_vblank. If we don't have this
4081 * and don't wait for vblanks until the end of crtc_enable, then
4082 * the HW state readout code will complain that the expected
4083 * IPS_CTL value is not the one we read. */
4084 if (wait_for(I915_READ_NOTRACE(IPS_CTL
) & IPS_ENABLE
, 50))
4085 DRM_ERROR("Timed out waiting for IPS enable\n");
4089 void hsw_disable_ips(struct intel_crtc
*crtc
)
4091 struct drm_device
*dev
= crtc
->base
.dev
;
4092 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4094 if (!crtc
->config
.ips_enabled
)
4097 assert_plane_enabled(dev_priv
, crtc
->plane
);
4098 if (IS_BROADWELL(dev
)) {
4099 mutex_lock(&dev_priv
->rps
.hw_lock
);
4100 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0));
4101 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4102 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4103 if (wait_for((I915_READ(IPS_CTL
) & IPS_ENABLE
) == 0, 42))
4104 DRM_ERROR("Timed out waiting for IPS disable\n");
4106 I915_WRITE(IPS_CTL
, 0);
4107 POSTING_READ(IPS_CTL
);
4110 /* We need to wait for a vblank before we can disable the plane. */
4111 intel_wait_for_vblank(dev
, crtc
->pipe
);
4114 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4115 static void intel_crtc_load_lut(struct drm_crtc
*crtc
)
4117 struct drm_device
*dev
= crtc
->dev
;
4118 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4119 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4120 enum pipe pipe
= intel_crtc
->pipe
;
4121 int palreg
= PALETTE(pipe
);
4123 bool reenable_ips
= false;
4125 /* The clocks have to be on to load the palette. */
4126 if (!crtc
->enabled
|| !intel_crtc
->active
)
4129 if (!HAS_PCH_SPLIT(dev_priv
->dev
)) {
4130 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
))
4131 assert_dsi_pll_enabled(dev_priv
);
4133 assert_pll_enabled(dev_priv
, pipe
);
4136 /* use legacy palette for Ironlake */
4137 if (!HAS_GMCH_DISPLAY(dev
))
4138 palreg
= LGC_PALETTE(pipe
);
4140 /* Workaround : Do not read or write the pipe palette/gamma data while
4141 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4143 if (IS_HASWELL(dev
) && intel_crtc
->config
.ips_enabled
&&
4144 ((I915_READ(GAMMA_MODE(pipe
)) & GAMMA_MODE_MODE_MASK
) ==
4145 GAMMA_MODE_MODE_SPLIT
)) {
4146 hsw_disable_ips(intel_crtc
);
4147 reenable_ips
= true;
4150 for (i
= 0; i
< 256; i
++) {
4151 I915_WRITE(palreg
+ 4 * i
,
4152 (intel_crtc
->lut_r
[i
] << 16) |
4153 (intel_crtc
->lut_g
[i
] << 8) |
4154 intel_crtc
->lut_b
[i
]);
4158 hsw_enable_ips(intel_crtc
);
4161 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
4163 if (!enable
&& intel_crtc
->overlay
) {
4164 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4165 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4167 mutex_lock(&dev
->struct_mutex
);
4168 dev_priv
->mm
.interruptible
= false;
4169 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
4170 dev_priv
->mm
.interruptible
= true;
4171 mutex_unlock(&dev
->struct_mutex
);
4174 /* Let userspace switch the overlay on again. In most cases userspace
4175 * has to recompute where to put it anyway.
4179 static void intel_crtc_enable_planes(struct drm_crtc
*crtc
)
4181 struct drm_device
*dev
= crtc
->dev
;
4182 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4183 int pipe
= intel_crtc
->pipe
;
4185 intel_enable_primary_hw_plane(crtc
->primary
, crtc
);
4186 intel_enable_planes(crtc
);
4187 intel_crtc_update_cursor(crtc
, true);
4188 intel_crtc_dpms_overlay(intel_crtc
, true);
4190 hsw_enable_ips(intel_crtc
);
4192 mutex_lock(&dev
->struct_mutex
);
4193 intel_update_fbc(dev
);
4194 mutex_unlock(&dev
->struct_mutex
);
4197 * FIXME: Once we grow proper nuclear flip support out of this we need
4198 * to compute the mask of flip planes precisely. For the time being
4199 * consider this a flip from a NULL plane.
4201 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
4204 static void intel_crtc_disable_planes(struct drm_crtc
*crtc
)
4206 struct drm_device
*dev
= crtc
->dev
;
4207 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4208 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4209 int pipe
= intel_crtc
->pipe
;
4210 int plane
= intel_crtc
->plane
;
4212 intel_crtc_wait_for_pending_flips(crtc
);
4214 if (dev_priv
->fbc
.plane
== plane
)
4215 intel_disable_fbc(dev
);
4217 hsw_disable_ips(intel_crtc
);
4219 intel_crtc_dpms_overlay(intel_crtc
, false);
4220 intel_crtc_update_cursor(crtc
, false);
4221 intel_disable_planes(crtc
);
4222 intel_disable_primary_hw_plane(crtc
->primary
, crtc
);
4225 * FIXME: Once we grow proper nuclear flip support out of this we need
4226 * to compute the mask of flip planes precisely. For the time being
4227 * consider this a flip to a NULL plane.
4229 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
4232 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
4234 struct drm_device
*dev
= crtc
->dev
;
4235 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4236 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4237 struct intel_encoder
*encoder
;
4238 int pipe
= intel_crtc
->pipe
;
4240 WARN_ON(!crtc
->enabled
);
4242 if (intel_crtc
->active
)
4245 if (intel_crtc
->config
.has_pch_encoder
)
4246 intel_prepare_shared_dpll(intel_crtc
);
4248 if (intel_crtc
->config
.has_dp_encoder
)
4249 intel_dp_set_m_n(intel_crtc
);
4251 intel_set_pipe_timings(intel_crtc
);
4253 if (intel_crtc
->config
.has_pch_encoder
) {
4254 intel_cpu_transcoder_set_m_n(intel_crtc
,
4255 &intel_crtc
->config
.fdi_m_n
, NULL
);
4258 ironlake_set_pipeconf(crtc
);
4260 intel_crtc
->active
= true;
4262 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4263 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, true);
4265 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4266 if (encoder
->pre_enable
)
4267 encoder
->pre_enable(encoder
);
4269 if (intel_crtc
->config
.has_pch_encoder
) {
4270 /* Note: FDI PLL enabling _must_ be done before we enable the
4271 * cpu pipes, hence this is separate from all the other fdi/pch
4273 ironlake_fdi_pll_enable(intel_crtc
);
4275 assert_fdi_tx_disabled(dev_priv
, pipe
);
4276 assert_fdi_rx_disabled(dev_priv
, pipe
);
4279 ironlake_pfit_enable(intel_crtc
);
4282 * On ILK+ LUT must be loaded before the pipe is running but with
4285 intel_crtc_load_lut(crtc
);
4287 intel_update_watermarks(crtc
);
4288 intel_enable_pipe(intel_crtc
);
4290 if (intel_crtc
->config
.has_pch_encoder
)
4291 ironlake_pch_enable(crtc
);
4293 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4294 encoder
->enable(encoder
);
4296 if (HAS_PCH_CPT(dev
))
4297 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
4299 assert_vblank_disabled(crtc
);
4300 drm_crtc_vblank_on(crtc
);
4302 intel_crtc_enable_planes(crtc
);
4305 /* IPS only exists on ULT machines and is tied to pipe A. */
4306 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
4308 return HAS_IPS(crtc
->base
.dev
) && crtc
->pipe
== PIPE_A
;
4312 * This implements the workaround described in the "notes" section of the mode
4313 * set sequence documentation. When going from no pipes or single pipe to
4314 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4315 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4317 static void haswell_mode_set_planes_workaround(struct intel_crtc
*crtc
)
4319 struct drm_device
*dev
= crtc
->base
.dev
;
4320 struct intel_crtc
*crtc_it
, *other_active_crtc
= NULL
;
4322 /* We want to get the other_active_crtc only if there's only 1 other
4324 for_each_intel_crtc(dev
, crtc_it
) {
4325 if (!crtc_it
->active
|| crtc_it
== crtc
)
4328 if (other_active_crtc
)
4331 other_active_crtc
= crtc_it
;
4333 if (!other_active_crtc
)
4336 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
4337 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
4340 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
4342 struct drm_device
*dev
= crtc
->dev
;
4343 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4344 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4345 struct intel_encoder
*encoder
;
4346 int pipe
= intel_crtc
->pipe
;
4348 WARN_ON(!crtc
->enabled
);
4350 if (intel_crtc
->active
)
4353 if (intel_crtc_to_shared_dpll(intel_crtc
))
4354 intel_enable_shared_dpll(intel_crtc
);
4356 if (intel_crtc
->config
.has_dp_encoder
)
4357 intel_dp_set_m_n(intel_crtc
);
4359 intel_set_pipe_timings(intel_crtc
);
4361 if (intel_crtc
->config
.cpu_transcoder
!= TRANSCODER_EDP
) {
4362 I915_WRITE(PIPE_MULT(intel_crtc
->config
.cpu_transcoder
),
4363 intel_crtc
->config
.pixel_multiplier
- 1);
4366 if (intel_crtc
->config
.has_pch_encoder
) {
4367 intel_cpu_transcoder_set_m_n(intel_crtc
,
4368 &intel_crtc
->config
.fdi_m_n
, NULL
);
4371 haswell_set_pipeconf(crtc
);
4373 intel_set_pipe_csc(crtc
);
4375 intel_crtc
->active
= true;
4377 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4378 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4379 if (encoder
->pre_enable
)
4380 encoder
->pre_enable(encoder
);
4382 if (intel_crtc
->config
.has_pch_encoder
) {
4383 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
4385 dev_priv
->display
.fdi_link_train(crtc
);
4388 intel_ddi_enable_pipe_clock(intel_crtc
);
4390 ironlake_pfit_enable(intel_crtc
);
4393 * On ILK+ LUT must be loaded before the pipe is running but with
4396 intel_crtc_load_lut(crtc
);
4398 intel_ddi_set_pipe_settings(crtc
);
4399 intel_ddi_enable_transcoder_func(crtc
);
4401 intel_update_watermarks(crtc
);
4402 intel_enable_pipe(intel_crtc
);
4404 if (intel_crtc
->config
.has_pch_encoder
)
4405 lpt_pch_enable(crtc
);
4407 if (intel_crtc
->config
.dp_encoder_is_mst
)
4408 intel_ddi_set_vc_payload_alloc(crtc
, true);
4410 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4411 encoder
->enable(encoder
);
4412 intel_opregion_notify_encoder(encoder
, true);
4415 assert_vblank_disabled(crtc
);
4416 drm_crtc_vblank_on(crtc
);
4418 /* If we change the relative order between pipe/planes enabling, we need
4419 * to change the workaround. */
4420 haswell_mode_set_planes_workaround(intel_crtc
);
4421 intel_crtc_enable_planes(crtc
);
4424 static void ironlake_pfit_disable(struct intel_crtc
*crtc
)
4426 struct drm_device
*dev
= crtc
->base
.dev
;
4427 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4428 int pipe
= crtc
->pipe
;
4430 /* To avoid upsetting the power well on haswell only disable the pfit if
4431 * it's in use. The hw state code will make sure we get this right. */
4432 if (crtc
->config
.pch_pfit
.enabled
) {
4433 I915_WRITE(PF_CTL(pipe
), 0);
4434 I915_WRITE(PF_WIN_POS(pipe
), 0);
4435 I915_WRITE(PF_WIN_SZ(pipe
), 0);
4439 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
4441 struct drm_device
*dev
= crtc
->dev
;
4442 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4443 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4444 struct intel_encoder
*encoder
;
4445 int pipe
= intel_crtc
->pipe
;
4448 if (!intel_crtc
->active
)
4451 intel_crtc_disable_planes(crtc
);
4453 drm_crtc_vblank_off(crtc
);
4454 assert_vblank_disabled(crtc
);
4456 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4457 encoder
->disable(encoder
);
4459 if (intel_crtc
->config
.has_pch_encoder
)
4460 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, false);
4462 intel_disable_pipe(intel_crtc
);
4464 ironlake_pfit_disable(intel_crtc
);
4466 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4467 if (encoder
->post_disable
)
4468 encoder
->post_disable(encoder
);
4470 if (intel_crtc
->config
.has_pch_encoder
) {
4471 ironlake_fdi_disable(crtc
);
4473 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
4474 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, true);
4476 if (HAS_PCH_CPT(dev
)) {
4477 /* disable TRANS_DP_CTL */
4478 reg
= TRANS_DP_CTL(pipe
);
4479 temp
= I915_READ(reg
);
4480 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
4481 TRANS_DP_PORT_SEL_MASK
);
4482 temp
|= TRANS_DP_PORT_SEL_NONE
;
4483 I915_WRITE(reg
, temp
);
4485 /* disable DPLL_SEL */
4486 temp
= I915_READ(PCH_DPLL_SEL
);
4487 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
4488 I915_WRITE(PCH_DPLL_SEL
, temp
);
4491 /* disable PCH DPLL */
4492 intel_disable_shared_dpll(intel_crtc
);
4494 ironlake_fdi_pll_disable(intel_crtc
);
4497 intel_crtc
->active
= false;
4498 intel_update_watermarks(crtc
);
4500 mutex_lock(&dev
->struct_mutex
);
4501 intel_update_fbc(dev
);
4502 mutex_unlock(&dev
->struct_mutex
);
4505 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
4507 struct drm_device
*dev
= crtc
->dev
;
4508 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4509 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4510 struct intel_encoder
*encoder
;
4511 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
4513 if (!intel_crtc
->active
)
4516 intel_crtc_disable_planes(crtc
);
4518 drm_crtc_vblank_off(crtc
);
4519 assert_vblank_disabled(crtc
);
4521 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4522 intel_opregion_notify_encoder(encoder
, false);
4523 encoder
->disable(encoder
);
4526 if (intel_crtc
->config
.has_pch_encoder
)
4527 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
4529 intel_disable_pipe(intel_crtc
);
4531 if (intel_crtc
->config
.dp_encoder_is_mst
)
4532 intel_ddi_set_vc_payload_alloc(crtc
, false);
4534 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
4536 ironlake_pfit_disable(intel_crtc
);
4538 intel_ddi_disable_pipe_clock(intel_crtc
);
4540 if (intel_crtc
->config
.has_pch_encoder
) {
4541 lpt_disable_pch_transcoder(dev_priv
);
4542 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
4544 intel_ddi_fdi_disable(crtc
);
4547 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4548 if (encoder
->post_disable
)
4549 encoder
->post_disable(encoder
);
4551 intel_crtc
->active
= false;
4552 intel_update_watermarks(crtc
);
4554 mutex_lock(&dev
->struct_mutex
);
4555 intel_update_fbc(dev
);
4556 mutex_unlock(&dev
->struct_mutex
);
4558 if (intel_crtc_to_shared_dpll(intel_crtc
))
4559 intel_disable_shared_dpll(intel_crtc
);
4562 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
4564 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4565 intel_put_shared_dpll(intel_crtc
);
4569 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
4571 struct drm_device
*dev
= crtc
->base
.dev
;
4572 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4573 struct intel_crtc_config
*pipe_config
= &crtc
->config
;
4575 if (!crtc
->config
.gmch_pfit
.control
)
4579 * The panel fitter should only be adjusted whilst the pipe is disabled,
4580 * according to register description and PRM.
4582 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
4583 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
4585 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
4586 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
4588 /* Border color in case we don't scale up to the full screen. Black by
4589 * default, change to something else for debugging. */
4590 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
4593 static enum intel_display_power_domain
port_to_power_domain(enum port port
)
4597 return POWER_DOMAIN_PORT_DDI_A_4_LANES
;
4599 return POWER_DOMAIN_PORT_DDI_B_4_LANES
;
4601 return POWER_DOMAIN_PORT_DDI_C_4_LANES
;
4603 return POWER_DOMAIN_PORT_DDI_D_4_LANES
;
4606 return POWER_DOMAIN_PORT_OTHER
;
4610 #define for_each_power_domain(domain, mask) \
4611 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4612 if ((1 << (domain)) & (mask))
4614 enum intel_display_power_domain
4615 intel_display_port_power_domain(struct intel_encoder
*intel_encoder
)
4617 struct drm_device
*dev
= intel_encoder
->base
.dev
;
4618 struct intel_digital_port
*intel_dig_port
;
4620 switch (intel_encoder
->type
) {
4621 case INTEL_OUTPUT_UNKNOWN
:
4622 /* Only DDI platforms should ever use this output type */
4623 WARN_ON_ONCE(!HAS_DDI(dev
));
4624 case INTEL_OUTPUT_DISPLAYPORT
:
4625 case INTEL_OUTPUT_HDMI
:
4626 case INTEL_OUTPUT_EDP
:
4627 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
4628 return port_to_power_domain(intel_dig_port
->port
);
4629 case INTEL_OUTPUT_DP_MST
:
4630 intel_dig_port
= enc_to_mst(&intel_encoder
->base
)->primary
;
4631 return port_to_power_domain(intel_dig_port
->port
);
4632 case INTEL_OUTPUT_ANALOG
:
4633 return POWER_DOMAIN_PORT_CRT
;
4634 case INTEL_OUTPUT_DSI
:
4635 return POWER_DOMAIN_PORT_DSI
;
4637 return POWER_DOMAIN_PORT_OTHER
;
4641 static unsigned long get_crtc_power_domains(struct drm_crtc
*crtc
)
4643 struct drm_device
*dev
= crtc
->dev
;
4644 struct intel_encoder
*intel_encoder
;
4645 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4646 enum pipe pipe
= intel_crtc
->pipe
;
4648 enum transcoder transcoder
;
4650 transcoder
= intel_pipe_to_cpu_transcoder(dev
->dev_private
, pipe
);
4652 mask
= BIT(POWER_DOMAIN_PIPE(pipe
));
4653 mask
|= BIT(POWER_DOMAIN_TRANSCODER(transcoder
));
4654 if (intel_crtc
->config
.pch_pfit
.enabled
||
4655 intel_crtc
->config
.pch_pfit
.force_thru
)
4656 mask
|= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe
));
4658 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
4659 mask
|= BIT(intel_display_port_power_domain(intel_encoder
));
4664 static void modeset_update_crtc_power_domains(struct drm_device
*dev
)
4666 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4667 unsigned long pipe_domains
[I915_MAX_PIPES
] = { 0, };
4668 struct intel_crtc
*crtc
;
4671 * First get all needed power domains, then put all unneeded, to avoid
4672 * any unnecessary toggling of the power wells.
4674 for_each_intel_crtc(dev
, crtc
) {
4675 enum intel_display_power_domain domain
;
4677 if (!crtc
->base
.enabled
)
4680 pipe_domains
[crtc
->pipe
] = get_crtc_power_domains(&crtc
->base
);
4682 for_each_power_domain(domain
, pipe_domains
[crtc
->pipe
])
4683 intel_display_power_get(dev_priv
, domain
);
4686 for_each_intel_crtc(dev
, crtc
) {
4687 enum intel_display_power_domain domain
;
4689 for_each_power_domain(domain
, crtc
->enabled_power_domains
)
4690 intel_display_power_put(dev_priv
, domain
);
4692 crtc
->enabled_power_domains
= pipe_domains
[crtc
->pipe
];
4695 intel_display_set_init_power(dev_priv
, false);
4698 /* returns HPLL frequency in kHz */
4699 static int valleyview_get_vco(struct drm_i915_private
*dev_priv
)
4701 int hpll_freq
, vco_freq
[] = { 800, 1600, 2000, 2400 };
4703 /* Obtain SKU information */
4704 mutex_lock(&dev_priv
->dpio_lock
);
4705 hpll_freq
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
) &
4706 CCK_FUSE_HPLL_FREQ_MASK
;
4707 mutex_unlock(&dev_priv
->dpio_lock
);
4709 return vco_freq
[hpll_freq
] * 1000;
4712 static void vlv_update_cdclk(struct drm_device
*dev
)
4714 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4716 dev_priv
->vlv_cdclk_freq
= dev_priv
->display
.get_display_clock_speed(dev
);
4717 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4718 dev_priv
->vlv_cdclk_freq
);
4721 * Program the gmbus_freq based on the cdclk frequency.
4722 * BSpec erroneously claims we should aim for 4MHz, but
4723 * in fact 1MHz is the correct frequency.
4725 I915_WRITE(GMBUSFREQ_VLV
, dev_priv
->vlv_cdclk_freq
);
4728 /* Adjust CDclk dividers to allow high res or save power if possible */
4729 static void valleyview_set_cdclk(struct drm_device
*dev
, int cdclk
)
4731 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4734 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
) != dev_priv
->vlv_cdclk_freq
);
4736 if (cdclk
>= 320000) /* jump to highest voltage for 400MHz too */
4738 else if (cdclk
== 266667)
4743 mutex_lock(&dev_priv
->rps
.hw_lock
);
4744 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
4745 val
&= ~DSPFREQGUAR_MASK
;
4746 val
|= (cmd
<< DSPFREQGUAR_SHIFT
);
4747 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
4748 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
4749 DSPFREQSTAT_MASK
) == (cmd
<< DSPFREQSTAT_SHIFT
),
4751 DRM_ERROR("timed out waiting for CDclk change\n");
4753 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4755 if (cdclk
== 400000) {
4758 vco
= valleyview_get_vco(dev_priv
);
4759 divider
= DIV_ROUND_CLOSEST(vco
<< 1, cdclk
) - 1;
4761 mutex_lock(&dev_priv
->dpio_lock
);
4762 /* adjust cdclk divider */
4763 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
4764 val
&= ~DISPLAY_FREQUENCY_VALUES
;
4766 vlv_cck_write(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
, val
);
4768 if (wait_for((vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
) &
4769 DISPLAY_FREQUENCY_STATUS
) == (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
4771 DRM_ERROR("timed out waiting for CDclk change\n");
4772 mutex_unlock(&dev_priv
->dpio_lock
);
4775 mutex_lock(&dev_priv
->dpio_lock
);
4776 /* adjust self-refresh exit latency value */
4777 val
= vlv_bunit_read(dev_priv
, BUNIT_REG_BISOC
);
4781 * For high bandwidth configs, we set a higher latency in the bunit
4782 * so that the core display fetch happens in time to avoid underruns.
4784 if (cdclk
== 400000)
4785 val
|= 4500 / 250; /* 4.5 usec */
4787 val
|= 3000 / 250; /* 3.0 usec */
4788 vlv_bunit_write(dev_priv
, BUNIT_REG_BISOC
, val
);
4789 mutex_unlock(&dev_priv
->dpio_lock
);
4791 vlv_update_cdclk(dev
);
4794 static void cherryview_set_cdclk(struct drm_device
*dev
, int cdclk
)
4796 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4799 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
) != dev_priv
->vlv_cdclk_freq
);
4820 mutex_lock(&dev_priv
->rps
.hw_lock
);
4821 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
4822 val
&= ~DSPFREQGUAR_MASK_CHV
;
4823 val
|= (cmd
<< DSPFREQGUAR_SHIFT_CHV
);
4824 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
4825 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
4826 DSPFREQSTAT_MASK_CHV
) == (cmd
<< DSPFREQSTAT_SHIFT_CHV
),
4828 DRM_ERROR("timed out waiting for CDclk change\n");
4830 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4832 vlv_update_cdclk(dev
);
4835 static int valleyview_calc_cdclk(struct drm_i915_private
*dev_priv
,
4838 int vco
= valleyview_get_vco(dev_priv
);
4839 int freq_320
= (vco
<< 1) % 320000 != 0 ? 333333 : 320000;
4841 /* FIXME: Punit isn't quite ready yet */
4842 if (IS_CHERRYVIEW(dev_priv
->dev
))
4846 * Really only a few cases to deal with, as only 4 CDclks are supported:
4849 * 320/333MHz (depends on HPLL freq)
4851 * So we check to see whether we're above 90% of the lower bin and
4854 * We seem to get an unstable or solid color picture at 200MHz.
4855 * Not sure what's wrong. For now use 200MHz only when all pipes
4858 if (max_pixclk
> freq_320
*9/10)
4860 else if (max_pixclk
> 266667*9/10)
4862 else if (max_pixclk
> 0)
4868 /* compute the max pixel clock for new configuration */
4869 static int intel_mode_max_pixclk(struct drm_i915_private
*dev_priv
)
4871 struct drm_device
*dev
= dev_priv
->dev
;
4872 struct intel_crtc
*intel_crtc
;
4875 for_each_intel_crtc(dev
, intel_crtc
) {
4876 if (intel_crtc
->new_enabled
)
4877 max_pixclk
= max(max_pixclk
,
4878 intel_crtc
->new_config
->adjusted_mode
.crtc_clock
);
4884 static void valleyview_modeset_global_pipes(struct drm_device
*dev
,
4885 unsigned *prepare_pipes
)
4887 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4888 struct intel_crtc
*intel_crtc
;
4889 int max_pixclk
= intel_mode_max_pixclk(dev_priv
);
4891 if (valleyview_calc_cdclk(dev_priv
, max_pixclk
) ==
4892 dev_priv
->vlv_cdclk_freq
)
4895 /* disable/enable all currently active pipes while we change cdclk */
4896 for_each_intel_crtc(dev
, intel_crtc
)
4897 if (intel_crtc
->base
.enabled
)
4898 *prepare_pipes
|= (1 << intel_crtc
->pipe
);
4901 static void valleyview_modeset_global_resources(struct drm_device
*dev
)
4903 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4904 int max_pixclk
= intel_mode_max_pixclk(dev_priv
);
4905 int req_cdclk
= valleyview_calc_cdclk(dev_priv
, max_pixclk
);
4907 if (req_cdclk
!= dev_priv
->vlv_cdclk_freq
) {
4908 if (IS_CHERRYVIEW(dev
))
4909 cherryview_set_cdclk(dev
, req_cdclk
);
4911 valleyview_set_cdclk(dev
, req_cdclk
);
4914 modeset_update_crtc_power_domains(dev
);
4917 static void valleyview_crtc_enable(struct drm_crtc
*crtc
)
4919 struct drm_device
*dev
= crtc
->dev
;
4920 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4921 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4922 struct intel_encoder
*encoder
;
4923 int pipe
= intel_crtc
->pipe
;
4926 WARN_ON(!crtc
->enabled
);
4928 if (intel_crtc
->active
)
4931 is_dsi
= intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
);
4934 if (IS_CHERRYVIEW(dev
))
4935 chv_prepare_pll(intel_crtc
, &intel_crtc
->config
);
4937 vlv_prepare_pll(intel_crtc
, &intel_crtc
->config
);
4940 if (intel_crtc
->config
.has_dp_encoder
)
4941 intel_dp_set_m_n(intel_crtc
);
4943 intel_set_pipe_timings(intel_crtc
);
4945 if (IS_CHERRYVIEW(dev
) && pipe
== PIPE_B
) {
4946 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4948 I915_WRITE(CHV_BLEND(pipe
), CHV_BLEND_LEGACY
);
4949 I915_WRITE(CHV_CANVAS(pipe
), 0);
4952 i9xx_set_pipeconf(intel_crtc
);
4954 intel_crtc
->active
= true;
4956 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4958 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4959 if (encoder
->pre_pll_enable
)
4960 encoder
->pre_pll_enable(encoder
);
4963 if (IS_CHERRYVIEW(dev
))
4964 chv_enable_pll(intel_crtc
, &intel_crtc
->config
);
4966 vlv_enable_pll(intel_crtc
, &intel_crtc
->config
);
4969 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4970 if (encoder
->pre_enable
)
4971 encoder
->pre_enable(encoder
);
4973 i9xx_pfit_enable(intel_crtc
);
4975 intel_crtc_load_lut(crtc
);
4977 intel_update_watermarks(crtc
);
4978 intel_enable_pipe(intel_crtc
);
4980 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4981 encoder
->enable(encoder
);
4983 assert_vblank_disabled(crtc
);
4984 drm_crtc_vblank_on(crtc
);
4986 intel_crtc_enable_planes(crtc
);
4988 /* Underruns don't raise interrupts, so check manually. */
4989 i9xx_check_fifo_underruns(dev_priv
);
4992 static void i9xx_set_pll_dividers(struct intel_crtc
*crtc
)
4994 struct drm_device
*dev
= crtc
->base
.dev
;
4995 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4997 I915_WRITE(FP0(crtc
->pipe
), crtc
->config
.dpll_hw_state
.fp0
);
4998 I915_WRITE(FP1(crtc
->pipe
), crtc
->config
.dpll_hw_state
.fp1
);
5001 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
5003 struct drm_device
*dev
= crtc
->dev
;
5004 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5005 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5006 struct intel_encoder
*encoder
;
5007 int pipe
= intel_crtc
->pipe
;
5009 WARN_ON(!crtc
->enabled
);
5011 if (intel_crtc
->active
)
5014 i9xx_set_pll_dividers(intel_crtc
);
5016 if (intel_crtc
->config
.has_dp_encoder
)
5017 intel_dp_set_m_n(intel_crtc
);
5019 intel_set_pipe_timings(intel_crtc
);
5021 i9xx_set_pipeconf(intel_crtc
);
5023 intel_crtc
->active
= true;
5026 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5028 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5029 if (encoder
->pre_enable
)
5030 encoder
->pre_enable(encoder
);
5032 i9xx_enable_pll(intel_crtc
);
5034 i9xx_pfit_enable(intel_crtc
);
5036 intel_crtc_load_lut(crtc
);
5038 intel_update_watermarks(crtc
);
5039 intel_enable_pipe(intel_crtc
);
5041 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5042 encoder
->enable(encoder
);
5044 assert_vblank_disabled(crtc
);
5045 drm_crtc_vblank_on(crtc
);
5047 intel_crtc_enable_planes(crtc
);
5050 * Gen2 reports pipe underruns whenever all planes are disabled.
5051 * So don't enable underrun reporting before at least some planes
5053 * FIXME: Need to fix the logic to work when we turn off all planes
5054 * but leave the pipe running.
5057 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5059 /* Underruns don't raise interrupts, so check manually. */
5060 i9xx_check_fifo_underruns(dev_priv
);
5063 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
5065 struct drm_device
*dev
= crtc
->base
.dev
;
5066 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5068 if (!crtc
->config
.gmch_pfit
.control
)
5071 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
5073 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5074 I915_READ(PFIT_CONTROL
));
5075 I915_WRITE(PFIT_CONTROL
, 0);
5078 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
5080 struct drm_device
*dev
= crtc
->dev
;
5081 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5082 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5083 struct intel_encoder
*encoder
;
5084 int pipe
= intel_crtc
->pipe
;
5086 if (!intel_crtc
->active
)
5090 * Gen2 reports pipe underruns whenever all planes are disabled.
5091 * So diasble underrun reporting before all the planes get disabled.
5092 * FIXME: Need to fix the logic to work when we turn off all planes
5093 * but leave the pipe running.
5096 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
5099 * Vblank time updates from the shadow to live plane control register
5100 * are blocked if the memory self-refresh mode is active at that
5101 * moment. So to make sure the plane gets truly disabled, disable
5102 * first the self-refresh mode. The self-refresh enable bit in turn
5103 * will be checked/applied by the HW only at the next frame start
5104 * event which is after the vblank start event, so we need to have a
5105 * wait-for-vblank between disabling the plane and the pipe.
5107 intel_set_memory_cxsr(dev_priv
, false);
5108 intel_crtc_disable_planes(crtc
);
5111 * On gen2 planes are double buffered but the pipe isn't, so we must
5112 * wait for planes to fully turn off before disabling the pipe.
5113 * We also need to wait on all gmch platforms because of the
5114 * self-refresh mode constraint explained above.
5116 intel_wait_for_vblank(dev
, pipe
);
5118 drm_crtc_vblank_off(crtc
);
5119 assert_vblank_disabled(crtc
);
5121 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5122 encoder
->disable(encoder
);
5124 intel_disable_pipe(intel_crtc
);
5126 i9xx_pfit_disable(intel_crtc
);
5128 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5129 if (encoder
->post_disable
)
5130 encoder
->post_disable(encoder
);
5132 if (!intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
)) {
5133 if (IS_CHERRYVIEW(dev
))
5134 chv_disable_pll(dev_priv
, pipe
);
5135 else if (IS_VALLEYVIEW(dev
))
5136 vlv_disable_pll(dev_priv
, pipe
);
5138 i9xx_disable_pll(intel_crtc
);
5142 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
5144 intel_crtc
->active
= false;
5145 intel_update_watermarks(crtc
);
5147 mutex_lock(&dev
->struct_mutex
);
5148 intel_update_fbc(dev
);
5149 mutex_unlock(&dev
->struct_mutex
);
5152 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
5156 static void intel_crtc_update_sarea(struct drm_crtc
*crtc
,
5159 struct drm_device
*dev
= crtc
->dev
;
5160 struct drm_i915_master_private
*master_priv
;
5161 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5162 int pipe
= intel_crtc
->pipe
;
5164 if (!dev
->primary
->master
)
5167 master_priv
= dev
->primary
->master
->driver_priv
;
5168 if (!master_priv
->sarea_priv
)
5173 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
5174 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
5177 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
5178 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
5181 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe
));
5186 /* Master function to enable/disable CRTC and corresponding power wells */
5187 void intel_crtc_control(struct drm_crtc
*crtc
, bool enable
)
5189 struct drm_device
*dev
= crtc
->dev
;
5190 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5191 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5192 enum intel_display_power_domain domain
;
5193 unsigned long domains
;
5196 if (!intel_crtc
->active
) {
5197 domains
= get_crtc_power_domains(crtc
);
5198 for_each_power_domain(domain
, domains
)
5199 intel_display_power_get(dev_priv
, domain
);
5200 intel_crtc
->enabled_power_domains
= domains
;
5202 dev_priv
->display
.crtc_enable(crtc
);
5205 if (intel_crtc
->active
) {
5206 dev_priv
->display
.crtc_disable(crtc
);
5208 domains
= intel_crtc
->enabled_power_domains
;
5209 for_each_power_domain(domain
, domains
)
5210 intel_display_power_put(dev_priv
, domain
);
5211 intel_crtc
->enabled_power_domains
= 0;
5217 * Sets the power management mode of the pipe and plane.
5219 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
5221 struct drm_device
*dev
= crtc
->dev
;
5222 struct intel_encoder
*intel_encoder
;
5223 bool enable
= false;
5225 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
5226 enable
|= intel_encoder
->connectors_active
;
5228 intel_crtc_control(crtc
, enable
);
5230 intel_crtc_update_sarea(crtc
, enable
);
5233 static void intel_crtc_disable(struct drm_crtc
*crtc
)
5235 struct drm_device
*dev
= crtc
->dev
;
5236 struct drm_connector
*connector
;
5237 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5238 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(crtc
->primary
->fb
);
5239 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
5241 /* crtc should still be enabled when we disable it. */
5242 WARN_ON(!crtc
->enabled
);
5244 dev_priv
->display
.crtc_disable(crtc
);
5245 intel_crtc_update_sarea(crtc
, false);
5246 dev_priv
->display
.off(crtc
);
5248 if (crtc
->primary
->fb
) {
5249 mutex_lock(&dev
->struct_mutex
);
5250 intel_unpin_fb_obj(old_obj
);
5251 i915_gem_track_fb(old_obj
, NULL
,
5252 INTEL_FRONTBUFFER_PRIMARY(pipe
));
5253 mutex_unlock(&dev
->struct_mutex
);
5254 crtc
->primary
->fb
= NULL
;
5257 /* Update computed state. */
5258 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
5259 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
5262 if (connector
->encoder
->crtc
!= crtc
)
5265 connector
->dpms
= DRM_MODE_DPMS_OFF
;
5266 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
5270 void intel_encoder_destroy(struct drm_encoder
*encoder
)
5272 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
5274 drm_encoder_cleanup(encoder
);
5275 kfree(intel_encoder
);
5278 /* Simple dpms helper for encoders with just one connector, no cloning and only
5279 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5280 * state of the entire output pipe. */
5281 static void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
5283 if (mode
== DRM_MODE_DPMS_ON
) {
5284 encoder
->connectors_active
= true;
5286 intel_crtc_update_dpms(encoder
->base
.crtc
);
5288 encoder
->connectors_active
= false;
5290 intel_crtc_update_dpms(encoder
->base
.crtc
);
5294 /* Cross check the actual hw state with our own modeset state tracking (and it's
5295 * internal consistency). */
5296 static void intel_connector_check_state(struct intel_connector
*connector
)
5298 if (connector
->get_hw_state(connector
)) {
5299 struct intel_encoder
*encoder
= connector
->encoder
;
5300 struct drm_crtc
*crtc
;
5301 bool encoder_enabled
;
5304 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5305 connector
->base
.base
.id
,
5306 connector
->base
.name
);
5308 /* there is no real hw state for MST connectors */
5309 if (connector
->mst_port
)
5312 WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
5313 "wrong connector dpms state\n");
5314 WARN(connector
->base
.encoder
!= &encoder
->base
,
5315 "active connector not linked to encoder\n");
5318 WARN(!encoder
->connectors_active
,
5319 "encoder->connectors_active not set\n");
5321 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
5322 WARN(!encoder_enabled
, "encoder not enabled\n");
5323 if (WARN_ON(!encoder
->base
.crtc
))
5326 crtc
= encoder
->base
.crtc
;
5328 WARN(!crtc
->enabled
, "crtc not enabled\n");
5329 WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
5330 WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
5331 "encoder active on the wrong pipe\n");
5336 /* Even simpler default implementation, if there's really no special case to
5338 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
5340 /* All the simple cases only support two dpms states. */
5341 if (mode
!= DRM_MODE_DPMS_ON
)
5342 mode
= DRM_MODE_DPMS_OFF
;
5344 if (mode
== connector
->dpms
)
5347 connector
->dpms
= mode
;
5349 /* Only need to change hw state when actually enabled */
5350 if (connector
->encoder
)
5351 intel_encoder_dpms(to_intel_encoder(connector
->encoder
), mode
);
5353 intel_modeset_check_state(connector
->dev
);
5356 /* Simple connector->get_hw_state implementation for encoders that support only
5357 * one connector and no cloning and hence the encoder state determines the state
5358 * of the connector. */
5359 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
5362 struct intel_encoder
*encoder
= connector
->encoder
;
5364 return encoder
->get_hw_state(encoder
, &pipe
);
5367 static bool ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
5368 struct intel_crtc_config
*pipe_config
)
5370 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5371 struct intel_crtc
*pipe_B_crtc
=
5372 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
5374 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5375 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5376 if (pipe_config
->fdi_lanes
> 4) {
5377 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5378 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5382 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
5383 if (pipe_config
->fdi_lanes
> 2) {
5384 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5385 pipe_config
->fdi_lanes
);
5392 if (INTEL_INFO(dev
)->num_pipes
== 2)
5395 /* Ivybridge 3 pipe is really complicated */
5400 if (dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]->enabled
&&
5401 pipe_config
->fdi_lanes
> 2) {
5402 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5403 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5408 if (!pipe_has_enabled_pch(pipe_B_crtc
) ||
5409 pipe_B_crtc
->config
.fdi_lanes
<= 2) {
5410 if (pipe_config
->fdi_lanes
> 2) {
5411 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5412 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5416 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5426 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
5427 struct intel_crtc_config
*pipe_config
)
5429 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5430 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
5431 int lane
, link_bw
, fdi_dotclock
;
5432 bool setup_ok
, needs_recompute
= false;
5435 /* FDI is a binary signal running at ~2.7GHz, encoding
5436 * each output octet as 10 bits. The actual frequency
5437 * is stored as a divider into a 100MHz clock, and the
5438 * mode pixel clock is stored in units of 1KHz.
5439 * Hence the bw of each lane in terms of the mode signal
5442 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
5444 fdi_dotclock
= adjusted_mode
->crtc_clock
;
5446 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
5447 pipe_config
->pipe_bpp
);
5449 pipe_config
->fdi_lanes
= lane
;
5451 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
5452 link_bw
, &pipe_config
->fdi_m_n
);
5454 setup_ok
= ironlake_check_fdi_lanes(intel_crtc
->base
.dev
,
5455 intel_crtc
->pipe
, pipe_config
);
5456 if (!setup_ok
&& pipe_config
->pipe_bpp
> 6*3) {
5457 pipe_config
->pipe_bpp
-= 2*3;
5458 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5459 pipe_config
->pipe_bpp
);
5460 needs_recompute
= true;
5461 pipe_config
->bw_constrained
= true;
5466 if (needs_recompute
)
5469 return setup_ok
? 0 : -EINVAL
;
5472 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
5473 struct intel_crtc_config
*pipe_config
)
5475 pipe_config
->ips_enabled
= i915
.enable_ips
&&
5476 hsw_crtc_supports_ips(crtc
) &&
5477 pipe_config
->pipe_bpp
<= 24;
5480 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
5481 struct intel_crtc_config
*pipe_config
)
5483 struct drm_device
*dev
= crtc
->base
.dev
;
5484 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5485 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
5487 /* FIXME should check pixel clock limits on all platforms */
5488 if (INTEL_INFO(dev
)->gen
< 4) {
5490 dev_priv
->display
.get_display_clock_speed(dev
);
5493 * Enable pixel doubling when the dot clock
5494 * is > 90% of the (display) core speed.
5496 * GDG double wide on either pipe,
5497 * otherwise pipe A only.
5499 if ((crtc
->pipe
== PIPE_A
|| IS_I915G(dev
)) &&
5500 adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10) {
5502 pipe_config
->double_wide
= true;
5505 if (adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10)
5510 * Pipe horizontal size must be even in:
5512 * - LVDS dual channel mode
5513 * - Double wide pipe
5515 if ((intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
5516 intel_is_dual_link_lvds(dev
)) || pipe_config
->double_wide
)
5517 pipe_config
->pipe_src_w
&= ~1;
5519 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5520 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5522 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
5523 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
5526 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) && pipe_config
->pipe_bpp
> 10*3) {
5527 pipe_config
->pipe_bpp
= 10*3; /* 12bpc is gen5+ */
5528 } else if (INTEL_INFO(dev
)->gen
<= 4 && pipe_config
->pipe_bpp
> 8*3) {
5529 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5531 pipe_config
->pipe_bpp
= 8*3;
5535 hsw_compute_ips_config(crtc
, pipe_config
);
5537 if (pipe_config
->has_pch_encoder
)
5538 return ironlake_fdi_compute_config(crtc
, pipe_config
);
5543 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
5545 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5546 int vco
= valleyview_get_vco(dev_priv
);
5550 /* FIXME: Punit isn't quite ready yet */
5551 if (IS_CHERRYVIEW(dev
))
5554 mutex_lock(&dev_priv
->dpio_lock
);
5555 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
5556 mutex_unlock(&dev_priv
->dpio_lock
);
5558 divider
= val
& DISPLAY_FREQUENCY_VALUES
;
5560 WARN((val
& DISPLAY_FREQUENCY_STATUS
) !=
5561 (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
5562 "cdclk change in progress\n");
5564 return DIV_ROUND_CLOSEST(vco
<< 1, divider
+ 1);
5567 static int i945_get_display_clock_speed(struct drm_device
*dev
)
5572 static int i915_get_display_clock_speed(struct drm_device
*dev
)
5577 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
5582 static int pnv_get_display_clock_speed(struct drm_device
*dev
)
5586 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
5588 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
5589 case GC_DISPLAY_CLOCK_267_MHZ_PNV
:
5591 case GC_DISPLAY_CLOCK_333_MHZ_PNV
:
5593 case GC_DISPLAY_CLOCK_444_MHZ_PNV
:
5595 case GC_DISPLAY_CLOCK_200_MHZ_PNV
:
5598 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc
);
5599 case GC_DISPLAY_CLOCK_133_MHZ_PNV
:
5601 case GC_DISPLAY_CLOCK_167_MHZ_PNV
:
5606 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
5610 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
5612 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
5615 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
5616 case GC_DISPLAY_CLOCK_333_MHZ
:
5619 case GC_DISPLAY_CLOCK_190_200_MHZ
:
5625 static int i865_get_display_clock_speed(struct drm_device
*dev
)
5630 static int i855_get_display_clock_speed(struct drm_device
*dev
)
5633 /* Assume that the hardware is in the high speed state. This
5634 * should be the default.
5636 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
5637 case GC_CLOCK_133_200
:
5638 case GC_CLOCK_100_200
:
5640 case GC_CLOCK_166_250
:
5642 case GC_CLOCK_100_133
:
5646 /* Shouldn't happen */
5650 static int i830_get_display_clock_speed(struct drm_device
*dev
)
5656 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
5658 while (*num
> DATA_LINK_M_N_MASK
||
5659 *den
> DATA_LINK_M_N_MASK
) {
5665 static void compute_m_n(unsigned int m
, unsigned int n
,
5666 uint32_t *ret_m
, uint32_t *ret_n
)
5668 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
5669 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
5670 intel_reduce_m_n_ratio(ret_m
, ret_n
);
5674 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
5675 int pixel_clock
, int link_clock
,
5676 struct intel_link_m_n
*m_n
)
5680 compute_m_n(bits_per_pixel
* pixel_clock
,
5681 link_clock
* nlanes
* 8,
5682 &m_n
->gmch_m
, &m_n
->gmch_n
);
5684 compute_m_n(pixel_clock
, link_clock
,
5685 &m_n
->link_m
, &m_n
->link_n
);
5688 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
5690 if (i915
.panel_use_ssc
>= 0)
5691 return i915
.panel_use_ssc
!= 0;
5692 return dev_priv
->vbt
.lvds_use_ssc
5693 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
5696 static int i9xx_get_refclk(struct intel_crtc
*crtc
, int num_connectors
)
5698 struct drm_device
*dev
= crtc
->base
.dev
;
5699 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5702 if (IS_VALLEYVIEW(dev
)) {
5704 } else if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
) &&
5705 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
5706 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
5707 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
5708 } else if (!IS_GEN2(dev
)) {
5717 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
5719 return (1 << dpll
->n
) << 16 | dpll
->m2
;
5722 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
5724 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
5727 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
5728 intel_clock_t
*reduced_clock
)
5730 struct drm_device
*dev
= crtc
->base
.dev
;
5733 if (IS_PINEVIEW(dev
)) {
5734 fp
= pnv_dpll_compute_fp(&crtc
->config
.dpll
);
5736 fp2
= pnv_dpll_compute_fp(reduced_clock
);
5738 fp
= i9xx_dpll_compute_fp(&crtc
->config
.dpll
);
5740 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
5743 crtc
->config
.dpll_hw_state
.fp0
= fp
;
5745 crtc
->lowfreq_avail
= false;
5746 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
5747 reduced_clock
&& i915
.powersave
) {
5748 crtc
->config
.dpll_hw_state
.fp1
= fp2
;
5749 crtc
->lowfreq_avail
= true;
5751 crtc
->config
.dpll_hw_state
.fp1
= fp
;
5755 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
5761 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5762 * and set it to a reasonable value instead.
5764 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
5765 reg_val
&= 0xffffff00;
5766 reg_val
|= 0x00000030;
5767 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
5769 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
5770 reg_val
&= 0x8cffffff;
5771 reg_val
= 0x8c000000;
5772 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
5774 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
5775 reg_val
&= 0xffffff00;
5776 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
5778 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
5779 reg_val
&= 0x00ffffff;
5780 reg_val
|= 0xb0000000;
5781 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
5784 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
5785 struct intel_link_m_n
*m_n
)
5787 struct drm_device
*dev
= crtc
->base
.dev
;
5788 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5789 int pipe
= crtc
->pipe
;
5791 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5792 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
5793 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
5794 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
5797 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
5798 struct intel_link_m_n
*m_n
,
5799 struct intel_link_m_n
*m2_n2
)
5801 struct drm_device
*dev
= crtc
->base
.dev
;
5802 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5803 int pipe
= crtc
->pipe
;
5804 enum transcoder transcoder
= crtc
->config
.cpu_transcoder
;
5806 if (INTEL_INFO(dev
)->gen
>= 5) {
5807 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5808 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
5809 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
5810 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
5811 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5812 * for gen < 8) and if DRRS is supported (to make sure the
5813 * registers are not unnecessarily accessed).
5815 if (m2_n2
&& INTEL_INFO(dev
)->gen
< 8 &&
5816 crtc
->config
.has_drrs
) {
5817 I915_WRITE(PIPE_DATA_M2(transcoder
),
5818 TU_SIZE(m2_n2
->tu
) | m2_n2
->gmch_m
);
5819 I915_WRITE(PIPE_DATA_N2(transcoder
), m2_n2
->gmch_n
);
5820 I915_WRITE(PIPE_LINK_M2(transcoder
), m2_n2
->link_m
);
5821 I915_WRITE(PIPE_LINK_N2(transcoder
), m2_n2
->link_n
);
5824 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5825 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
5826 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
5827 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
5831 void intel_dp_set_m_n(struct intel_crtc
*crtc
)
5833 if (crtc
->config
.has_pch_encoder
)
5834 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
5836 intel_cpu_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
,
5837 &crtc
->config
.dp_m2_n2
);
5840 static void vlv_update_pll(struct intel_crtc
*crtc
,
5841 struct intel_crtc_config
*pipe_config
)
5846 * Enable DPIO clock input. We should never disable the reference
5847 * clock for pipe B, since VGA hotplug / manual detection depends
5850 dpll
= DPLL_EXT_BUFFER_ENABLE_VLV
| DPLL_REFA_CLK_ENABLE_VLV
|
5851 DPLL_VGA_MODE_DIS
| DPLL_INTEGRATED_CLOCK_VLV
;
5852 /* We should never disable this, set it here for state tracking */
5853 if (crtc
->pipe
== PIPE_B
)
5854 dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
5855 dpll
|= DPLL_VCO_ENABLE
;
5856 pipe_config
->dpll_hw_state
.dpll
= dpll
;
5858 dpll_md
= (pipe_config
->pixel_multiplier
- 1)
5859 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
5860 pipe_config
->dpll_hw_state
.dpll_md
= dpll_md
;
5863 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
5864 const struct intel_crtc_config
*pipe_config
)
5866 struct drm_device
*dev
= crtc
->base
.dev
;
5867 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5868 int pipe
= crtc
->pipe
;
5870 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
5871 u32 coreclk
, reg_val
;
5873 mutex_lock(&dev_priv
->dpio_lock
);
5875 bestn
= pipe_config
->dpll
.n
;
5876 bestm1
= pipe_config
->dpll
.m1
;
5877 bestm2
= pipe_config
->dpll
.m2
;
5878 bestp1
= pipe_config
->dpll
.p1
;
5879 bestp2
= pipe_config
->dpll
.p2
;
5881 /* See eDP HDMI DPIO driver vbios notes doc */
5883 /* PLL B needs special handling */
5885 vlv_pllb_recal_opamp(dev_priv
, pipe
);
5887 /* Set up Tx target for periodic Rcomp update */
5888 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9_BCAST
, 0x0100000f);
5890 /* Disable target IRef on PLL */
5891 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW8(pipe
));
5892 reg_val
&= 0x00ffffff;
5893 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW8(pipe
), reg_val
);
5895 /* Disable fast lock */
5896 vlv_dpio_write(dev_priv
, pipe
, VLV_CMN_DW0
, 0x610);
5898 /* Set idtafcrecal before PLL is enabled */
5899 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
5900 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
5901 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
5902 mdiv
|= (1 << DPIO_K_SHIFT
);
5905 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5906 * but we don't support that).
5907 * Note: don't use the DAC post divider as it seems unstable.
5909 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
5910 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
5912 mdiv
|= DPIO_ENABLE_CALIBRATION
;
5913 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
5915 /* Set HBR and RBR LPF coefficients */
5916 if (pipe_config
->port_clock
== 162000 ||
5917 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
) ||
5918 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
5919 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
5922 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
5925 if (crtc
->config
.has_dp_encoder
) {
5926 /* Use SSC source */
5928 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5931 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5933 } else { /* HDMI or VGA */
5934 /* Use bend source */
5936 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5939 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5943 coreclk
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW7(pipe
));
5944 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
5945 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
5946 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))
5947 coreclk
|= 0x01000000;
5948 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW7(pipe
), coreclk
);
5950 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW11(pipe
), 0x87871000);
5951 mutex_unlock(&dev_priv
->dpio_lock
);
5954 static void chv_update_pll(struct intel_crtc
*crtc
,
5955 struct intel_crtc_config
*pipe_config
)
5957 pipe_config
->dpll_hw_state
.dpll
= DPLL_SSC_REF_CLOCK_CHV
|
5958 DPLL_REFA_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
|
5960 if (crtc
->pipe
!= PIPE_A
)
5961 pipe_config
->dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
5963 pipe_config
->dpll_hw_state
.dpll_md
=
5964 (pipe_config
->pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
5967 static void chv_prepare_pll(struct intel_crtc
*crtc
,
5968 const struct intel_crtc_config
*pipe_config
)
5970 struct drm_device
*dev
= crtc
->base
.dev
;
5971 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5972 int pipe
= crtc
->pipe
;
5973 int dpll_reg
= DPLL(crtc
->pipe
);
5974 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
5975 u32 loopfilter
, intcoeff
;
5976 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
, bestm2_frac
;
5979 bestn
= pipe_config
->dpll
.n
;
5980 bestm2_frac
= pipe_config
->dpll
.m2
& 0x3fffff;
5981 bestm1
= pipe_config
->dpll
.m1
;
5982 bestm2
= pipe_config
->dpll
.m2
>> 22;
5983 bestp1
= pipe_config
->dpll
.p1
;
5984 bestp2
= pipe_config
->dpll
.p2
;
5987 * Enable Refclk and SSC
5989 I915_WRITE(dpll_reg
,
5990 pipe_config
->dpll_hw_state
.dpll
& ~DPLL_VCO_ENABLE
);
5992 mutex_lock(&dev_priv
->dpio_lock
);
5994 /* p1 and p2 divider */
5995 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW13(port
),
5996 5 << DPIO_CHV_S1_DIV_SHIFT
|
5997 bestp1
<< DPIO_CHV_P1_DIV_SHIFT
|
5998 bestp2
<< DPIO_CHV_P2_DIV_SHIFT
|
5999 1 << DPIO_CHV_K_DIV_SHIFT
);
6001 /* Feedback post-divider - m2 */
6002 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW0(port
), bestm2
);
6004 /* Feedback refclk divider - n and m1 */
6005 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW1(port
),
6006 DPIO_CHV_M1_DIV_BY_2
|
6007 1 << DPIO_CHV_N_DIV_SHIFT
);
6009 /* M2 fraction division */
6010 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW2(port
), bestm2_frac
);
6012 /* M2 fraction division enable */
6013 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW3(port
),
6014 DPIO_CHV_FRAC_DIV_EN
|
6015 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT
));
6018 refclk
= i9xx_get_refclk(crtc
, 0);
6019 loopfilter
= 5 << DPIO_CHV_PROP_COEFF_SHIFT
|
6020 2 << DPIO_CHV_GAIN_CTRL_SHIFT
;
6021 if (refclk
== 100000)
6023 else if (refclk
== 38400)
6027 loopfilter
|= intcoeff
<< DPIO_CHV_INT_COEFF_SHIFT
;
6028 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW6(port
), loopfilter
);
6031 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
),
6032 vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
)) |
6035 mutex_unlock(&dev_priv
->dpio_lock
);
6039 * vlv_force_pll_on - forcibly enable just the PLL
6040 * @dev_priv: i915 private structure
6041 * @pipe: pipe PLL to enable
6042 * @dpll: PLL configuration
6044 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6045 * in cases where we need the PLL enabled even when @pipe is not going to
6048 void vlv_force_pll_on(struct drm_device
*dev
, enum pipe pipe
,
6049 const struct dpll
*dpll
)
6051 struct intel_crtc
*crtc
=
6052 to_intel_crtc(intel_get_crtc_for_pipe(dev
, pipe
));
6053 struct intel_crtc_config pipe_config
= {
6054 .pixel_multiplier
= 1,
6058 if (IS_CHERRYVIEW(dev
)) {
6059 chv_update_pll(crtc
, &pipe_config
);
6060 chv_prepare_pll(crtc
, &pipe_config
);
6061 chv_enable_pll(crtc
, &pipe_config
);
6063 vlv_update_pll(crtc
, &pipe_config
);
6064 vlv_prepare_pll(crtc
, &pipe_config
);
6065 vlv_enable_pll(crtc
, &pipe_config
);
6070 * vlv_force_pll_off - forcibly disable just the PLL
6071 * @dev_priv: i915 private structure
6072 * @pipe: pipe PLL to disable
6074 * Disable the PLL for @pipe. To be used in cases where we need
6075 * the PLL enabled even when @pipe is not going to be enabled.
6077 void vlv_force_pll_off(struct drm_device
*dev
, enum pipe pipe
)
6079 if (IS_CHERRYVIEW(dev
))
6080 chv_disable_pll(to_i915(dev
), pipe
);
6082 vlv_disable_pll(to_i915(dev
), pipe
);
6085 static void i9xx_update_pll(struct intel_crtc
*crtc
,
6086 intel_clock_t
*reduced_clock
,
6089 struct drm_device
*dev
= crtc
->base
.dev
;
6090 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6093 struct dpll
*clock
= &crtc
->new_config
->dpll
;
6095 i9xx_update_pll_dividers(crtc
, reduced_clock
);
6097 is_sdvo
= intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_SDVO
) ||
6098 intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_HDMI
);
6100 dpll
= DPLL_VGA_MODE_DIS
;
6102 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
))
6103 dpll
|= DPLLB_MODE_LVDS
;
6105 dpll
|= DPLLB_MODE_DAC_SERIAL
;
6107 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
6108 dpll
|= (crtc
->new_config
->pixel_multiplier
- 1)
6109 << SDVO_MULTIPLIER_SHIFT_HIRES
;
6113 dpll
|= DPLL_SDVO_HIGH_SPEED
;
6115 if (crtc
->new_config
->has_dp_encoder
)
6116 dpll
|= DPLL_SDVO_HIGH_SPEED
;
6118 /* compute bitmask from p1 value */
6119 if (IS_PINEVIEW(dev
))
6120 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
6122 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
6123 if (IS_G4X(dev
) && reduced_clock
)
6124 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
6126 switch (clock
->p2
) {
6128 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
6131 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
6134 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
6137 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
6140 if (INTEL_INFO(dev
)->gen
>= 4)
6141 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
6143 if (crtc
->new_config
->sdvo_tv_clock
)
6144 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
6145 else if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
) &&
6146 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
6147 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
6149 dpll
|= PLL_REF_INPUT_DREFCLK
;
6151 dpll
|= DPLL_VCO_ENABLE
;
6152 crtc
->new_config
->dpll_hw_state
.dpll
= dpll
;
6154 if (INTEL_INFO(dev
)->gen
>= 4) {
6155 u32 dpll_md
= (crtc
->new_config
->pixel_multiplier
- 1)
6156 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
6157 crtc
->new_config
->dpll_hw_state
.dpll_md
= dpll_md
;
6161 static void i8xx_update_pll(struct intel_crtc
*crtc
,
6162 intel_clock_t
*reduced_clock
,
6165 struct drm_device
*dev
= crtc
->base
.dev
;
6166 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6168 struct dpll
*clock
= &crtc
->new_config
->dpll
;
6170 i9xx_update_pll_dividers(crtc
, reduced_clock
);
6172 dpll
= DPLL_VGA_MODE_DIS
;
6174 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
)) {
6175 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
6178 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
6180 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
6182 dpll
|= PLL_P2_DIVIDE_BY_4
;
6185 if (!IS_I830(dev
) && intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_DVO
))
6186 dpll
|= DPLL_DVO_2X_MODE
;
6188 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
) &&
6189 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
6190 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
6192 dpll
|= PLL_REF_INPUT_DREFCLK
;
6194 dpll
|= DPLL_VCO_ENABLE
;
6195 crtc
->new_config
->dpll_hw_state
.dpll
= dpll
;
6198 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
6200 struct drm_device
*dev
= intel_crtc
->base
.dev
;
6201 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6202 enum pipe pipe
= intel_crtc
->pipe
;
6203 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
6204 struct drm_display_mode
*adjusted_mode
=
6205 &intel_crtc
->config
.adjusted_mode
;
6206 uint32_t crtc_vtotal
, crtc_vblank_end
;
6209 /* We need to be careful not to changed the adjusted mode, for otherwise
6210 * the hw state checker will get angry at the mismatch. */
6211 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
6212 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
6214 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
6215 /* the chip adds 2 halflines automatically */
6217 crtc_vblank_end
-= 1;
6219 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
6220 vsyncshift
= (adjusted_mode
->crtc_htotal
- 1) / 2;
6222 vsyncshift
= adjusted_mode
->crtc_hsync_start
-
6223 adjusted_mode
->crtc_htotal
/ 2;
6225 vsyncshift
+= adjusted_mode
->crtc_htotal
;
6228 if (INTEL_INFO(dev
)->gen
> 3)
6229 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
6231 I915_WRITE(HTOTAL(cpu_transcoder
),
6232 (adjusted_mode
->crtc_hdisplay
- 1) |
6233 ((adjusted_mode
->crtc_htotal
- 1) << 16));
6234 I915_WRITE(HBLANK(cpu_transcoder
),
6235 (adjusted_mode
->crtc_hblank_start
- 1) |
6236 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
6237 I915_WRITE(HSYNC(cpu_transcoder
),
6238 (adjusted_mode
->crtc_hsync_start
- 1) |
6239 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
6241 I915_WRITE(VTOTAL(cpu_transcoder
),
6242 (adjusted_mode
->crtc_vdisplay
- 1) |
6243 ((crtc_vtotal
- 1) << 16));
6244 I915_WRITE(VBLANK(cpu_transcoder
),
6245 (adjusted_mode
->crtc_vblank_start
- 1) |
6246 ((crtc_vblank_end
- 1) << 16));
6247 I915_WRITE(VSYNC(cpu_transcoder
),
6248 (adjusted_mode
->crtc_vsync_start
- 1) |
6249 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
6251 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6252 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6253 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6255 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
6256 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
6257 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
6259 /* pipesrc controls the size that is scaled from, which should
6260 * always be the user's requested size.
6262 I915_WRITE(PIPESRC(pipe
),
6263 ((intel_crtc
->config
.pipe_src_w
- 1) << 16) |
6264 (intel_crtc
->config
.pipe_src_h
- 1));
6267 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
6268 struct intel_crtc_config
*pipe_config
)
6270 struct drm_device
*dev
= crtc
->base
.dev
;
6271 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6272 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
6275 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
6276 pipe_config
->adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
6277 pipe_config
->adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
6278 tmp
= I915_READ(HBLANK(cpu_transcoder
));
6279 pipe_config
->adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
6280 pipe_config
->adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
6281 tmp
= I915_READ(HSYNC(cpu_transcoder
));
6282 pipe_config
->adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
6283 pipe_config
->adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
6285 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
6286 pipe_config
->adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
6287 pipe_config
->adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
6288 tmp
= I915_READ(VBLANK(cpu_transcoder
));
6289 pipe_config
->adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
6290 pipe_config
->adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
6291 tmp
= I915_READ(VSYNC(cpu_transcoder
));
6292 pipe_config
->adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
6293 pipe_config
->adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
6295 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
6296 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
6297 pipe_config
->adjusted_mode
.crtc_vtotal
+= 1;
6298 pipe_config
->adjusted_mode
.crtc_vblank_end
+= 1;
6301 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
6302 pipe_config
->pipe_src_h
= (tmp
& 0xffff) + 1;
6303 pipe_config
->pipe_src_w
= ((tmp
>> 16) & 0xffff) + 1;
6305 pipe_config
->requested_mode
.vdisplay
= pipe_config
->pipe_src_h
;
6306 pipe_config
->requested_mode
.hdisplay
= pipe_config
->pipe_src_w
;
6309 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
6310 struct intel_crtc_config
*pipe_config
)
6312 mode
->hdisplay
= pipe_config
->adjusted_mode
.crtc_hdisplay
;
6313 mode
->htotal
= pipe_config
->adjusted_mode
.crtc_htotal
;
6314 mode
->hsync_start
= pipe_config
->adjusted_mode
.crtc_hsync_start
;
6315 mode
->hsync_end
= pipe_config
->adjusted_mode
.crtc_hsync_end
;
6317 mode
->vdisplay
= pipe_config
->adjusted_mode
.crtc_vdisplay
;
6318 mode
->vtotal
= pipe_config
->adjusted_mode
.crtc_vtotal
;
6319 mode
->vsync_start
= pipe_config
->adjusted_mode
.crtc_vsync_start
;
6320 mode
->vsync_end
= pipe_config
->adjusted_mode
.crtc_vsync_end
;
6322 mode
->flags
= pipe_config
->adjusted_mode
.flags
;
6324 mode
->clock
= pipe_config
->adjusted_mode
.crtc_clock
;
6325 mode
->flags
|= pipe_config
->adjusted_mode
.flags
;
6328 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
6330 struct drm_device
*dev
= intel_crtc
->base
.dev
;
6331 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6336 if ((intel_crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
6337 (intel_crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
6338 pipeconf
|= I915_READ(PIPECONF(intel_crtc
->pipe
)) & PIPECONF_ENABLE
;
6340 if (intel_crtc
->config
.double_wide
)
6341 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
6343 /* only g4x and later have fancy bpc/dither controls */
6344 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
6345 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6346 if (intel_crtc
->config
.dither
&& intel_crtc
->config
.pipe_bpp
!= 30)
6347 pipeconf
|= PIPECONF_DITHER_EN
|
6348 PIPECONF_DITHER_TYPE_SP
;
6350 switch (intel_crtc
->config
.pipe_bpp
) {
6352 pipeconf
|= PIPECONF_6BPC
;
6355 pipeconf
|= PIPECONF_8BPC
;
6358 pipeconf
|= PIPECONF_10BPC
;
6361 /* Case prevented by intel_choose_pipe_bpp_dither. */
6366 if (HAS_PIPE_CXSR(dev
)) {
6367 if (intel_crtc
->lowfreq_avail
) {
6368 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6369 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
6371 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6375 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
6376 if (INTEL_INFO(dev
)->gen
< 4 ||
6377 intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
6378 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
6380 pipeconf
|= PIPECONF_INTERLACE_W_SYNC_SHIFT
;
6382 pipeconf
|= PIPECONF_PROGRESSIVE
;
6384 if (IS_VALLEYVIEW(dev
) && intel_crtc
->config
.limited_color_range
)
6385 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
6387 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
6388 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
6391 static int i9xx_crtc_compute_clock(struct intel_crtc
*crtc
)
6393 struct drm_device
*dev
= crtc
->base
.dev
;
6394 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6395 int refclk
, num_connectors
= 0;
6396 intel_clock_t clock
, reduced_clock
;
6397 bool ok
, has_reduced_clock
= false;
6398 bool is_lvds
= false, is_dsi
= false;
6399 struct intel_encoder
*encoder
;
6400 const intel_limit_t
*limit
;
6402 for_each_intel_encoder(dev
, encoder
) {
6403 if (encoder
->new_crtc
!= crtc
)
6406 switch (encoder
->type
) {
6407 case INTEL_OUTPUT_LVDS
:
6410 case INTEL_OUTPUT_DSI
:
6423 if (!crtc
->new_config
->clock_set
) {
6424 refclk
= i9xx_get_refclk(crtc
, num_connectors
);
6427 * Returns a set of divisors for the desired target clock with
6428 * the given refclk, or FALSE. The returned values represent
6429 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6432 limit
= intel_limit(crtc
, refclk
);
6433 ok
= dev_priv
->display
.find_dpll(limit
, crtc
,
6434 crtc
->new_config
->port_clock
,
6435 refclk
, NULL
, &clock
);
6437 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6441 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
6443 * Ensure we match the reduced clock's P to the target
6444 * clock. If the clocks don't match, we can't switch
6445 * the display clock by using the FP0/FP1. In such case
6446 * we will disable the LVDS downclock feature.
6449 dev_priv
->display
.find_dpll(limit
, crtc
,
6450 dev_priv
->lvds_downclock
,
6454 /* Compat-code for transition, will disappear. */
6455 crtc
->new_config
->dpll
.n
= clock
.n
;
6456 crtc
->new_config
->dpll
.m1
= clock
.m1
;
6457 crtc
->new_config
->dpll
.m2
= clock
.m2
;
6458 crtc
->new_config
->dpll
.p1
= clock
.p1
;
6459 crtc
->new_config
->dpll
.p2
= clock
.p2
;
6463 i8xx_update_pll(crtc
,
6464 has_reduced_clock
? &reduced_clock
: NULL
,
6466 } else if (IS_CHERRYVIEW(dev
)) {
6467 chv_update_pll(crtc
, crtc
->new_config
);
6468 } else if (IS_VALLEYVIEW(dev
)) {
6469 vlv_update_pll(crtc
, crtc
->new_config
);
6471 i9xx_update_pll(crtc
,
6472 has_reduced_clock
? &reduced_clock
: NULL
,
6479 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
6480 struct intel_crtc_config
*pipe_config
)
6482 struct drm_device
*dev
= crtc
->base
.dev
;
6483 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6486 if (INTEL_INFO(dev
)->gen
<= 3 && (IS_I830(dev
) || !IS_MOBILE(dev
)))
6489 tmp
= I915_READ(PFIT_CONTROL
);
6490 if (!(tmp
& PFIT_ENABLE
))
6493 /* Check whether the pfit is attached to our pipe. */
6494 if (INTEL_INFO(dev
)->gen
< 4) {
6495 if (crtc
->pipe
!= PIPE_B
)
6498 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
6502 pipe_config
->gmch_pfit
.control
= tmp
;
6503 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
6504 if (INTEL_INFO(dev
)->gen
< 5)
6505 pipe_config
->gmch_pfit
.lvds_border_bits
=
6506 I915_READ(LVDS
) & LVDS_BORDER_ENABLE
;
6509 static void vlv_crtc_clock_get(struct intel_crtc
*crtc
,
6510 struct intel_crtc_config
*pipe_config
)
6512 struct drm_device
*dev
= crtc
->base
.dev
;
6513 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6514 int pipe
= pipe_config
->cpu_transcoder
;
6515 intel_clock_t clock
;
6517 int refclk
= 100000;
6519 /* In case of MIPI DPLL will not even be used */
6520 if (!(pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
))
6523 mutex_lock(&dev_priv
->dpio_lock
);
6524 mdiv
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW3(pipe
));
6525 mutex_unlock(&dev_priv
->dpio_lock
);
6527 clock
.m1
= (mdiv
>> DPIO_M1DIV_SHIFT
) & 7;
6528 clock
.m2
= mdiv
& DPIO_M2DIV_MASK
;
6529 clock
.n
= (mdiv
>> DPIO_N_SHIFT
) & 0xf;
6530 clock
.p1
= (mdiv
>> DPIO_P1_SHIFT
) & 7;
6531 clock
.p2
= (mdiv
>> DPIO_P2_SHIFT
) & 0x1f;
6533 vlv_clock(refclk
, &clock
);
6535 /* clock.dot is the fast clock */
6536 pipe_config
->port_clock
= clock
.dot
/ 5;
6539 static void i9xx_get_plane_config(struct intel_crtc
*crtc
,
6540 struct intel_plane_config
*plane_config
)
6542 struct drm_device
*dev
= crtc
->base
.dev
;
6543 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6544 u32 val
, base
, offset
;
6545 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
6546 int fourcc
, pixel_format
;
6549 crtc
->base
.primary
->fb
= kzalloc(sizeof(struct intel_framebuffer
), GFP_KERNEL
);
6550 if (!crtc
->base
.primary
->fb
) {
6551 DRM_DEBUG_KMS("failed to alloc fb\n");
6555 val
= I915_READ(DSPCNTR(plane
));
6557 if (INTEL_INFO(dev
)->gen
>= 4)
6558 if (val
& DISPPLANE_TILED
)
6559 plane_config
->tiled
= true;
6561 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
6562 fourcc
= intel_format_to_fourcc(pixel_format
);
6563 crtc
->base
.primary
->fb
->pixel_format
= fourcc
;
6564 crtc
->base
.primary
->fb
->bits_per_pixel
=
6565 drm_format_plane_cpp(fourcc
, 0) * 8;
6567 if (INTEL_INFO(dev
)->gen
>= 4) {
6568 if (plane_config
->tiled
)
6569 offset
= I915_READ(DSPTILEOFF(plane
));
6571 offset
= I915_READ(DSPLINOFF(plane
));
6572 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
6574 base
= I915_READ(DSPADDR(plane
));
6576 plane_config
->base
= base
;
6578 val
= I915_READ(PIPESRC(pipe
));
6579 crtc
->base
.primary
->fb
->width
= ((val
>> 16) & 0xfff) + 1;
6580 crtc
->base
.primary
->fb
->height
= ((val
>> 0) & 0xfff) + 1;
6582 val
= I915_READ(DSPSTRIDE(pipe
));
6583 crtc
->base
.primary
->fb
->pitches
[0] = val
& 0xffffffc0;
6585 aligned_height
= intel_align_height(dev
, crtc
->base
.primary
->fb
->height
,
6586 plane_config
->tiled
);
6588 plane_config
->size
= PAGE_ALIGN(crtc
->base
.primary
->fb
->pitches
[0] *
6591 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6592 pipe
, plane
, crtc
->base
.primary
->fb
->width
,
6593 crtc
->base
.primary
->fb
->height
,
6594 crtc
->base
.primary
->fb
->bits_per_pixel
, base
,
6595 crtc
->base
.primary
->fb
->pitches
[0],
6596 plane_config
->size
);
6600 static void chv_crtc_clock_get(struct intel_crtc
*crtc
,
6601 struct intel_crtc_config
*pipe_config
)
6603 struct drm_device
*dev
= crtc
->base
.dev
;
6604 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6605 int pipe
= pipe_config
->cpu_transcoder
;
6606 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
6607 intel_clock_t clock
;
6608 u32 cmn_dw13
, pll_dw0
, pll_dw1
, pll_dw2
;
6609 int refclk
= 100000;
6611 mutex_lock(&dev_priv
->dpio_lock
);
6612 cmn_dw13
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW13(port
));
6613 pll_dw0
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW0(port
));
6614 pll_dw1
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW1(port
));
6615 pll_dw2
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW2(port
));
6616 mutex_unlock(&dev_priv
->dpio_lock
);
6618 clock
.m1
= (pll_dw1
& 0x7) == DPIO_CHV_M1_DIV_BY_2
? 2 : 0;
6619 clock
.m2
= ((pll_dw0
& 0xff) << 22) | (pll_dw2
& 0x3fffff);
6620 clock
.n
= (pll_dw1
>> DPIO_CHV_N_DIV_SHIFT
) & 0xf;
6621 clock
.p1
= (cmn_dw13
>> DPIO_CHV_P1_DIV_SHIFT
) & 0x7;
6622 clock
.p2
= (cmn_dw13
>> DPIO_CHV_P2_DIV_SHIFT
) & 0x1f;
6624 chv_clock(refclk
, &clock
);
6626 /* clock.dot is the fast clock */
6627 pipe_config
->port_clock
= clock
.dot
/ 5;
6630 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
6631 struct intel_crtc_config
*pipe_config
)
6633 struct drm_device
*dev
= crtc
->base
.dev
;
6634 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6637 if (!intel_display_power_is_enabled(dev_priv
,
6638 POWER_DOMAIN_PIPE(crtc
->pipe
)))
6641 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
6642 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
6644 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
6645 if (!(tmp
& PIPECONF_ENABLE
))
6648 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
6649 switch (tmp
& PIPECONF_BPC_MASK
) {
6651 pipe_config
->pipe_bpp
= 18;
6654 pipe_config
->pipe_bpp
= 24;
6656 case PIPECONF_10BPC
:
6657 pipe_config
->pipe_bpp
= 30;
6664 if (IS_VALLEYVIEW(dev
) && (tmp
& PIPECONF_COLOR_RANGE_SELECT
))
6665 pipe_config
->limited_color_range
= true;
6667 if (INTEL_INFO(dev
)->gen
< 4)
6668 pipe_config
->double_wide
= tmp
& PIPECONF_DOUBLE_WIDE
;
6670 intel_get_pipe_timings(crtc
, pipe_config
);
6672 i9xx_get_pfit_config(crtc
, pipe_config
);
6674 if (INTEL_INFO(dev
)->gen
>= 4) {
6675 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
6676 pipe_config
->pixel_multiplier
=
6677 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
6678 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
6679 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
6680 } else if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
6681 tmp
= I915_READ(DPLL(crtc
->pipe
));
6682 pipe_config
->pixel_multiplier
=
6683 ((tmp
& SDVO_MULTIPLIER_MASK
)
6684 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
6686 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6687 * port and will be fixed up in the encoder->get_config
6689 pipe_config
->pixel_multiplier
= 1;
6691 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
6692 if (!IS_VALLEYVIEW(dev
)) {
6694 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6695 * on 830. Filter it out here so that we don't
6696 * report errors due to that.
6699 pipe_config
->dpll_hw_state
.dpll
&= ~DPLL_DVO_2X_MODE
;
6701 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
6702 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
6704 /* Mask out read-only status bits. */
6705 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
6706 DPLL_PORTC_READY_MASK
|
6707 DPLL_PORTB_READY_MASK
);
6710 if (IS_CHERRYVIEW(dev
))
6711 chv_crtc_clock_get(crtc
, pipe_config
);
6712 else if (IS_VALLEYVIEW(dev
))
6713 vlv_crtc_clock_get(crtc
, pipe_config
);
6715 i9xx_crtc_clock_get(crtc
, pipe_config
);
6720 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
6722 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6723 struct intel_encoder
*encoder
;
6725 bool has_lvds
= false;
6726 bool has_cpu_edp
= false;
6727 bool has_panel
= false;
6728 bool has_ck505
= false;
6729 bool can_ssc
= false;
6731 /* We need to take the global config into account */
6732 for_each_intel_encoder(dev
, encoder
) {
6733 switch (encoder
->type
) {
6734 case INTEL_OUTPUT_LVDS
:
6738 case INTEL_OUTPUT_EDP
:
6740 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
6748 if (HAS_PCH_IBX(dev
)) {
6749 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
6750 can_ssc
= has_ck505
;
6756 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6757 has_panel
, has_lvds
, has_ck505
);
6759 /* Ironlake: try to setup display ref clock before DPLL
6760 * enabling. This is only under driver's control after
6761 * PCH B stepping, previous chipset stepping should be
6762 * ignoring this setting.
6764 val
= I915_READ(PCH_DREF_CONTROL
);
6766 /* As we must carefully and slowly disable/enable each source in turn,
6767 * compute the final state we want first and check if we need to
6768 * make any changes at all.
6771 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
6773 final
|= DREF_NONSPREAD_CK505_ENABLE
;
6775 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
6777 final
&= ~DREF_SSC_SOURCE_MASK
;
6778 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
6779 final
&= ~DREF_SSC1_ENABLE
;
6782 final
|= DREF_SSC_SOURCE_ENABLE
;
6784 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
6785 final
|= DREF_SSC1_ENABLE
;
6788 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
6789 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
6791 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
6793 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6795 final
|= DREF_SSC_SOURCE_DISABLE
;
6796 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6802 /* Always enable nonspread source */
6803 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
6806 val
|= DREF_NONSPREAD_CK505_ENABLE
;
6808 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
6811 val
&= ~DREF_SSC_SOURCE_MASK
;
6812 val
|= DREF_SSC_SOURCE_ENABLE
;
6814 /* SSC must be turned on before enabling the CPU output */
6815 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
6816 DRM_DEBUG_KMS("Using SSC on panel\n");
6817 val
|= DREF_SSC1_ENABLE
;
6819 val
&= ~DREF_SSC1_ENABLE
;
6821 /* Get SSC going before enabling the outputs */
6822 I915_WRITE(PCH_DREF_CONTROL
, val
);
6823 POSTING_READ(PCH_DREF_CONTROL
);
6826 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
6828 /* Enable CPU source on CPU attached eDP */
6830 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
6831 DRM_DEBUG_KMS("Using SSC on eDP\n");
6832 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
6834 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
6836 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6838 I915_WRITE(PCH_DREF_CONTROL
, val
);
6839 POSTING_READ(PCH_DREF_CONTROL
);
6842 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6844 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
6846 /* Turn off CPU output */
6847 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6849 I915_WRITE(PCH_DREF_CONTROL
, val
);
6850 POSTING_READ(PCH_DREF_CONTROL
);
6853 /* Turn off the SSC source */
6854 val
&= ~DREF_SSC_SOURCE_MASK
;
6855 val
|= DREF_SSC_SOURCE_DISABLE
;
6858 val
&= ~DREF_SSC1_ENABLE
;
6860 I915_WRITE(PCH_DREF_CONTROL
, val
);
6861 POSTING_READ(PCH_DREF_CONTROL
);
6865 BUG_ON(val
!= final
);
6868 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
6872 tmp
= I915_READ(SOUTH_CHICKEN2
);
6873 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
6874 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
6876 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
6877 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
6878 DRM_ERROR("FDI mPHY reset assert timeout\n");
6880 tmp
= I915_READ(SOUTH_CHICKEN2
);
6881 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
6882 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
6884 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
6885 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
6886 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6889 /* WaMPhyProgramming:hsw */
6890 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
6894 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
6895 tmp
&= ~(0xFF << 24);
6896 tmp
|= (0x12 << 24);
6897 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
6899 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
6901 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
6903 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
6905 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
6907 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
6908 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
6909 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
6911 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
6912 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
6913 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
6915 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
6918 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
6920 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
6923 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
6925 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
6928 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
6930 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
6933 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
6935 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
6936 tmp
&= ~(0xFF << 16);
6937 tmp
|= (0x1C << 16);
6938 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
6940 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
6941 tmp
&= ~(0xFF << 16);
6942 tmp
|= (0x1C << 16);
6943 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
6945 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
6947 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
6949 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
6951 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
6953 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
6954 tmp
&= ~(0xF << 28);
6956 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
6958 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
6959 tmp
&= ~(0xF << 28);
6961 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
6964 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6965 * Programming" based on the parameters passed:
6966 * - Sequence to enable CLKOUT_DP
6967 * - Sequence to enable CLKOUT_DP without spread
6968 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6970 static void lpt_enable_clkout_dp(struct drm_device
*dev
, bool with_spread
,
6973 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6976 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
6978 if (WARN(dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
&&
6979 with_fdi
, "LP PCH doesn't have FDI\n"))
6982 mutex_lock(&dev_priv
->dpio_lock
);
6984 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
6985 tmp
&= ~SBI_SSCCTL_DISABLE
;
6986 tmp
|= SBI_SSCCTL_PATHALT
;
6987 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
6992 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
6993 tmp
&= ~SBI_SSCCTL_PATHALT
;
6994 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
6997 lpt_reset_fdi_mphy(dev_priv
);
6998 lpt_program_fdi_mphy(dev_priv
);
7002 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
7003 SBI_GEN0
: SBI_DBUFF0
;
7004 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
7005 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
7006 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
7008 mutex_unlock(&dev_priv
->dpio_lock
);
7011 /* Sequence to disable CLKOUT_DP */
7012 static void lpt_disable_clkout_dp(struct drm_device
*dev
)
7014 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7017 mutex_lock(&dev_priv
->dpio_lock
);
7019 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
7020 SBI_GEN0
: SBI_DBUFF0
;
7021 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
7022 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
7023 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
7025 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
7026 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
7027 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
7028 tmp
|= SBI_SSCCTL_PATHALT
;
7029 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
7032 tmp
|= SBI_SSCCTL_DISABLE
;
7033 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
7036 mutex_unlock(&dev_priv
->dpio_lock
);
7039 static void lpt_init_pch_refclk(struct drm_device
*dev
)
7041 struct intel_encoder
*encoder
;
7042 bool has_vga
= false;
7044 for_each_intel_encoder(dev
, encoder
) {
7045 switch (encoder
->type
) {
7046 case INTEL_OUTPUT_ANALOG
:
7055 lpt_enable_clkout_dp(dev
, true, true);
7057 lpt_disable_clkout_dp(dev
);
7061 * Initialize reference clocks when the driver loads
7063 void intel_init_pch_refclk(struct drm_device
*dev
)
7065 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
7066 ironlake_init_pch_refclk(dev
);
7067 else if (HAS_PCH_LPT(dev
))
7068 lpt_init_pch_refclk(dev
);
7071 static int ironlake_get_refclk(struct drm_crtc
*crtc
)
7073 struct drm_device
*dev
= crtc
->dev
;
7074 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7075 struct intel_encoder
*encoder
;
7076 int num_connectors
= 0;
7077 bool is_lvds
= false;
7079 for_each_intel_encoder(dev
, encoder
) {
7080 if (encoder
->new_crtc
!= to_intel_crtc(crtc
))
7083 switch (encoder
->type
) {
7084 case INTEL_OUTPUT_LVDS
:
7093 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
7094 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7095 dev_priv
->vbt
.lvds_ssc_freq
);
7096 return dev_priv
->vbt
.lvds_ssc_freq
;
7102 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
7104 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
7105 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7106 int pipe
= intel_crtc
->pipe
;
7111 switch (intel_crtc
->config
.pipe_bpp
) {
7113 val
|= PIPECONF_6BPC
;
7116 val
|= PIPECONF_8BPC
;
7119 val
|= PIPECONF_10BPC
;
7122 val
|= PIPECONF_12BPC
;
7125 /* Case prevented by intel_choose_pipe_bpp_dither. */
7129 if (intel_crtc
->config
.dither
)
7130 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
7132 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
7133 val
|= PIPECONF_INTERLACED_ILK
;
7135 val
|= PIPECONF_PROGRESSIVE
;
7137 if (intel_crtc
->config
.limited_color_range
)
7138 val
|= PIPECONF_COLOR_RANGE_SELECT
;
7140 I915_WRITE(PIPECONF(pipe
), val
);
7141 POSTING_READ(PIPECONF(pipe
));
7145 * Set up the pipe CSC unit.
7147 * Currently only full range RGB to limited range RGB conversion
7148 * is supported, but eventually this should handle various
7149 * RGB<->YCbCr scenarios as well.
7151 static void intel_set_pipe_csc(struct drm_crtc
*crtc
)
7153 struct drm_device
*dev
= crtc
->dev
;
7154 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7155 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7156 int pipe
= intel_crtc
->pipe
;
7157 uint16_t coeff
= 0x7800; /* 1.0 */
7160 * TODO: Check what kind of values actually come out of the pipe
7161 * with these coeff/postoff values and adjust to get the best
7162 * accuracy. Perhaps we even need to take the bpc value into
7166 if (intel_crtc
->config
.limited_color_range
)
7167 coeff
= ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7170 * GY/GU and RY/RU should be the other way around according
7171 * to BSpec, but reality doesn't agree. Just set them up in
7172 * a way that results in the correct picture.
7174 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeff
<< 16);
7175 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), 0);
7177 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeff
);
7178 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), 0);
7180 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), 0);
7181 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeff
<< 16);
7183 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
7184 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
7185 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
7187 if (INTEL_INFO(dev
)->gen
> 6) {
7188 uint16_t postoff
= 0;
7190 if (intel_crtc
->config
.limited_color_range
)
7191 postoff
= (16 * (1 << 12) / 255) & 0x1fff;
7193 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
7194 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
7195 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
7197 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
7199 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
7201 if (intel_crtc
->config
.limited_color_range
)
7202 mode
|= CSC_BLACK_SCREEN_OFFSET
;
7204 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
7208 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
7210 struct drm_device
*dev
= crtc
->dev
;
7211 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7212 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7213 enum pipe pipe
= intel_crtc
->pipe
;
7214 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
7219 if (IS_HASWELL(dev
) && intel_crtc
->config
.dither
)
7220 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
7222 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
7223 val
|= PIPECONF_INTERLACED_ILK
;
7225 val
|= PIPECONF_PROGRESSIVE
;
7227 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
7228 POSTING_READ(PIPECONF(cpu_transcoder
));
7230 I915_WRITE(GAMMA_MODE(intel_crtc
->pipe
), GAMMA_MODE_MODE_8BIT
);
7231 POSTING_READ(GAMMA_MODE(intel_crtc
->pipe
));
7233 if (IS_BROADWELL(dev
) || INTEL_INFO(dev
)->gen
>= 9) {
7236 switch (intel_crtc
->config
.pipe_bpp
) {
7238 val
|= PIPEMISC_DITHER_6_BPC
;
7241 val
|= PIPEMISC_DITHER_8_BPC
;
7244 val
|= PIPEMISC_DITHER_10_BPC
;
7247 val
|= PIPEMISC_DITHER_12_BPC
;
7250 /* Case prevented by pipe_config_set_bpp. */
7254 if (intel_crtc
->config
.dither
)
7255 val
|= PIPEMISC_DITHER_ENABLE
| PIPEMISC_DITHER_TYPE_SP
;
7257 I915_WRITE(PIPEMISC(pipe
), val
);
7261 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
7262 intel_clock_t
*clock
,
7263 bool *has_reduced_clock
,
7264 intel_clock_t
*reduced_clock
)
7266 struct drm_device
*dev
= crtc
->dev
;
7267 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7268 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7270 const intel_limit_t
*limit
;
7271 bool ret
, is_lvds
= false;
7273 is_lvds
= intel_pipe_will_have_type(intel_crtc
, INTEL_OUTPUT_LVDS
);
7275 refclk
= ironlake_get_refclk(crtc
);
7278 * Returns a set of divisors for the desired target clock with the given
7279 * refclk, or FALSE. The returned values represent the clock equation:
7280 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7282 limit
= intel_limit(intel_crtc
, refclk
);
7283 ret
= dev_priv
->display
.find_dpll(limit
, intel_crtc
,
7284 intel_crtc
->new_config
->port_clock
,
7285 refclk
, NULL
, clock
);
7289 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
7291 * Ensure we match the reduced clock's P to the target clock.
7292 * If the clocks don't match, we can't switch the display clock
7293 * by using the FP0/FP1. In such case we will disable the LVDS
7294 * downclock feature.
7296 *has_reduced_clock
=
7297 dev_priv
->display
.find_dpll(limit
, intel_crtc
,
7298 dev_priv
->lvds_downclock
,
7306 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
7309 * Account for spread spectrum to avoid
7310 * oversubscribing the link. Max center spread
7311 * is 2.5%; use 5% for safety's sake.
7313 u32 bps
= target_clock
* bpp
* 21 / 20;
7314 return DIV_ROUND_UP(bps
, link_bw
* 8);
7317 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
7319 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
7322 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
7324 intel_clock_t
*reduced_clock
, u32
*fp2
)
7326 struct drm_crtc
*crtc
= &intel_crtc
->base
;
7327 struct drm_device
*dev
= crtc
->dev
;
7328 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7329 struct intel_encoder
*intel_encoder
;
7331 int factor
, num_connectors
= 0;
7332 bool is_lvds
= false, is_sdvo
= false;
7334 for_each_intel_encoder(dev
, intel_encoder
) {
7335 if (intel_encoder
->new_crtc
!= to_intel_crtc(crtc
))
7338 switch (intel_encoder
->type
) {
7339 case INTEL_OUTPUT_LVDS
:
7342 case INTEL_OUTPUT_SDVO
:
7343 case INTEL_OUTPUT_HDMI
:
7353 /* Enable autotuning of the PLL clock (if permissible) */
7356 if ((intel_panel_use_ssc(dev_priv
) &&
7357 dev_priv
->vbt
.lvds_ssc_freq
== 100000) ||
7358 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
7360 } else if (intel_crtc
->new_config
->sdvo_tv_clock
)
7363 if (ironlake_needs_fb_cb_tune(&intel_crtc
->new_config
->dpll
, factor
))
7366 if (fp2
&& (reduced_clock
->m
< factor
* reduced_clock
->n
))
7372 dpll
|= DPLLB_MODE_LVDS
;
7374 dpll
|= DPLLB_MODE_DAC_SERIAL
;
7376 dpll
|= (intel_crtc
->new_config
->pixel_multiplier
- 1)
7377 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
7380 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7381 if (intel_crtc
->new_config
->has_dp_encoder
)
7382 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7384 /* compute bitmask from p1 value */
7385 dpll
|= (1 << (intel_crtc
->new_config
->dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7387 dpll
|= (1 << (intel_crtc
->new_config
->dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
7389 switch (intel_crtc
->new_config
->dpll
.p2
) {
7391 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
7394 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
7397 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
7400 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
7404 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
7405 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7407 dpll
|= PLL_REF_INPUT_DREFCLK
;
7409 return dpll
| DPLL_VCO_ENABLE
;
7412 static int ironlake_crtc_compute_clock(struct intel_crtc
*crtc
)
7414 struct drm_device
*dev
= crtc
->base
.dev
;
7415 intel_clock_t clock
, reduced_clock
;
7416 u32 dpll
= 0, fp
= 0, fp2
= 0;
7417 bool ok
, has_reduced_clock
= false;
7418 bool is_lvds
= false;
7419 struct intel_shared_dpll
*pll
;
7421 is_lvds
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
);
7423 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
7424 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
7426 ok
= ironlake_compute_clocks(&crtc
->base
, &clock
,
7427 &has_reduced_clock
, &reduced_clock
);
7428 if (!ok
&& !crtc
->new_config
->clock_set
) {
7429 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7432 /* Compat-code for transition, will disappear. */
7433 if (!crtc
->new_config
->clock_set
) {
7434 crtc
->new_config
->dpll
.n
= clock
.n
;
7435 crtc
->new_config
->dpll
.m1
= clock
.m1
;
7436 crtc
->new_config
->dpll
.m2
= clock
.m2
;
7437 crtc
->new_config
->dpll
.p1
= clock
.p1
;
7438 crtc
->new_config
->dpll
.p2
= clock
.p2
;
7441 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7442 if (crtc
->new_config
->has_pch_encoder
) {
7443 fp
= i9xx_dpll_compute_fp(&crtc
->new_config
->dpll
);
7444 if (has_reduced_clock
)
7445 fp2
= i9xx_dpll_compute_fp(&reduced_clock
);
7447 dpll
= ironlake_compute_dpll(crtc
,
7448 &fp
, &reduced_clock
,
7449 has_reduced_clock
? &fp2
: NULL
);
7451 crtc
->new_config
->dpll_hw_state
.dpll
= dpll
;
7452 crtc
->new_config
->dpll_hw_state
.fp0
= fp
;
7453 if (has_reduced_clock
)
7454 crtc
->new_config
->dpll_hw_state
.fp1
= fp2
;
7456 crtc
->new_config
->dpll_hw_state
.fp1
= fp
;
7458 pll
= intel_get_shared_dpll(crtc
);
7460 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7461 pipe_name(crtc
->pipe
));
7466 if (is_lvds
&& has_reduced_clock
&& i915
.powersave
)
7467 crtc
->lowfreq_avail
= true;
7469 crtc
->lowfreq_avail
= false;
7474 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
7475 struct intel_link_m_n
*m_n
)
7477 struct drm_device
*dev
= crtc
->base
.dev
;
7478 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7479 enum pipe pipe
= crtc
->pipe
;
7481 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
7482 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
7483 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
7485 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
7486 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
7487 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7490 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
7491 enum transcoder transcoder
,
7492 struct intel_link_m_n
*m_n
,
7493 struct intel_link_m_n
*m2_n2
)
7495 struct drm_device
*dev
= crtc
->base
.dev
;
7496 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7497 enum pipe pipe
= crtc
->pipe
;
7499 if (INTEL_INFO(dev
)->gen
>= 5) {
7500 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
7501 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
7502 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
7504 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
7505 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
7506 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7507 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7508 * gen < 8) and if DRRS is supported (to make sure the
7509 * registers are not unnecessarily read).
7511 if (m2_n2
&& INTEL_INFO(dev
)->gen
< 8 &&
7512 crtc
->config
.has_drrs
) {
7513 m2_n2
->link_m
= I915_READ(PIPE_LINK_M2(transcoder
));
7514 m2_n2
->link_n
= I915_READ(PIPE_LINK_N2(transcoder
));
7515 m2_n2
->gmch_m
= I915_READ(PIPE_DATA_M2(transcoder
))
7517 m2_n2
->gmch_n
= I915_READ(PIPE_DATA_N2(transcoder
));
7518 m2_n2
->tu
= ((I915_READ(PIPE_DATA_M2(transcoder
))
7519 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7522 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
7523 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
7524 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
7526 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
7527 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
7528 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7532 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
7533 struct intel_crtc_config
*pipe_config
)
7535 if (crtc
->config
.has_pch_encoder
)
7536 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
7538 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
7539 &pipe_config
->dp_m_n
,
7540 &pipe_config
->dp_m2_n2
);
7543 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
7544 struct intel_crtc_config
*pipe_config
)
7546 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
7547 &pipe_config
->fdi_m_n
, NULL
);
7550 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
7551 struct intel_crtc_config
*pipe_config
)
7553 struct drm_device
*dev
= crtc
->base
.dev
;
7554 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7557 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
7559 if (tmp
& PF_ENABLE
) {
7560 pipe_config
->pch_pfit
.enabled
= true;
7561 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
7562 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
7564 /* We currently do not free assignements of panel fitters on
7565 * ivb/hsw (since we don't use the higher upscaling modes which
7566 * differentiates them) so just WARN about this case for now. */
7568 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
7569 PF_PIPE_SEL_IVB(crtc
->pipe
));
7574 static void ironlake_get_plane_config(struct intel_crtc
*crtc
,
7575 struct intel_plane_config
*plane_config
)
7577 struct drm_device
*dev
= crtc
->base
.dev
;
7578 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7579 u32 val
, base
, offset
;
7580 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
7581 int fourcc
, pixel_format
;
7584 crtc
->base
.primary
->fb
= kzalloc(sizeof(struct intel_framebuffer
), GFP_KERNEL
);
7585 if (!crtc
->base
.primary
->fb
) {
7586 DRM_DEBUG_KMS("failed to alloc fb\n");
7590 val
= I915_READ(DSPCNTR(plane
));
7592 if (INTEL_INFO(dev
)->gen
>= 4)
7593 if (val
& DISPPLANE_TILED
)
7594 plane_config
->tiled
= true;
7596 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
7597 fourcc
= intel_format_to_fourcc(pixel_format
);
7598 crtc
->base
.primary
->fb
->pixel_format
= fourcc
;
7599 crtc
->base
.primary
->fb
->bits_per_pixel
=
7600 drm_format_plane_cpp(fourcc
, 0) * 8;
7602 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
7603 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
7604 offset
= I915_READ(DSPOFFSET(plane
));
7606 if (plane_config
->tiled
)
7607 offset
= I915_READ(DSPTILEOFF(plane
));
7609 offset
= I915_READ(DSPLINOFF(plane
));
7611 plane_config
->base
= base
;
7613 val
= I915_READ(PIPESRC(pipe
));
7614 crtc
->base
.primary
->fb
->width
= ((val
>> 16) & 0xfff) + 1;
7615 crtc
->base
.primary
->fb
->height
= ((val
>> 0) & 0xfff) + 1;
7617 val
= I915_READ(DSPSTRIDE(pipe
));
7618 crtc
->base
.primary
->fb
->pitches
[0] = val
& 0xffffffc0;
7620 aligned_height
= intel_align_height(dev
, crtc
->base
.primary
->fb
->height
,
7621 plane_config
->tiled
);
7623 plane_config
->size
= PAGE_ALIGN(crtc
->base
.primary
->fb
->pitches
[0] *
7626 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7627 pipe
, plane
, crtc
->base
.primary
->fb
->width
,
7628 crtc
->base
.primary
->fb
->height
,
7629 crtc
->base
.primary
->fb
->bits_per_pixel
, base
,
7630 crtc
->base
.primary
->fb
->pitches
[0],
7631 plane_config
->size
);
7634 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
7635 struct intel_crtc_config
*pipe_config
)
7637 struct drm_device
*dev
= crtc
->base
.dev
;
7638 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7641 if (!intel_display_power_is_enabled(dev_priv
,
7642 POWER_DOMAIN_PIPE(crtc
->pipe
)))
7645 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
7646 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
7648 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
7649 if (!(tmp
& PIPECONF_ENABLE
))
7652 switch (tmp
& PIPECONF_BPC_MASK
) {
7654 pipe_config
->pipe_bpp
= 18;
7657 pipe_config
->pipe_bpp
= 24;
7659 case PIPECONF_10BPC
:
7660 pipe_config
->pipe_bpp
= 30;
7662 case PIPECONF_12BPC
:
7663 pipe_config
->pipe_bpp
= 36;
7669 if (tmp
& PIPECONF_COLOR_RANGE_SELECT
)
7670 pipe_config
->limited_color_range
= true;
7672 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
7673 struct intel_shared_dpll
*pll
;
7675 pipe_config
->has_pch_encoder
= true;
7677 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
7678 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
7679 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
7681 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
7683 if (HAS_PCH_IBX(dev_priv
->dev
)) {
7684 pipe_config
->shared_dpll
=
7685 (enum intel_dpll_id
) crtc
->pipe
;
7687 tmp
= I915_READ(PCH_DPLL_SEL
);
7688 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
7689 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_B
;
7691 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_A
;
7694 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
7696 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
7697 &pipe_config
->dpll_hw_state
));
7699 tmp
= pipe_config
->dpll_hw_state
.dpll
;
7700 pipe_config
->pixel_multiplier
=
7701 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
7702 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
7704 ironlake_pch_clock_get(crtc
, pipe_config
);
7706 pipe_config
->pixel_multiplier
= 1;
7709 intel_get_pipe_timings(crtc
, pipe_config
);
7711 ironlake_get_pfit_config(crtc
, pipe_config
);
7716 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
7718 struct drm_device
*dev
= dev_priv
->dev
;
7719 struct intel_crtc
*crtc
;
7721 for_each_intel_crtc(dev
, crtc
)
7722 WARN(crtc
->active
, "CRTC for pipe %c enabled\n",
7723 pipe_name(crtc
->pipe
));
7725 WARN(I915_READ(HSW_PWR_WELL_DRIVER
), "Power well on\n");
7726 WARN(I915_READ(SPLL_CTL
) & SPLL_PLL_ENABLE
, "SPLL enabled\n");
7727 WARN(I915_READ(WRPLL_CTL1
) & WRPLL_PLL_ENABLE
, "WRPLL1 enabled\n");
7728 WARN(I915_READ(WRPLL_CTL2
) & WRPLL_PLL_ENABLE
, "WRPLL2 enabled\n");
7729 WARN(I915_READ(PCH_PP_STATUS
) & PP_ON
, "Panel power on\n");
7730 WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
7731 "CPU PWM1 enabled\n");
7732 if (IS_HASWELL(dev
))
7733 WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
7734 "CPU PWM2 enabled\n");
7735 WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
7736 "PCH PWM1 enabled\n");
7737 WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
7738 "Utility pin enabled\n");
7739 WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
7742 * In theory we can still leave IRQs enabled, as long as only the HPD
7743 * interrupts remain enabled. We used to check for that, but since it's
7744 * gen-specific and since we only disable LCPLL after we fully disable
7745 * the interrupts, the check below should be enough.
7747 WARN(intel_irqs_enabled(dev_priv
), "IRQs enabled\n");
7750 static uint32_t hsw_read_dcomp(struct drm_i915_private
*dev_priv
)
7752 struct drm_device
*dev
= dev_priv
->dev
;
7754 if (IS_HASWELL(dev
))
7755 return I915_READ(D_COMP_HSW
);
7757 return I915_READ(D_COMP_BDW
);
7760 static void hsw_write_dcomp(struct drm_i915_private
*dev_priv
, uint32_t val
)
7762 struct drm_device
*dev
= dev_priv
->dev
;
7764 if (IS_HASWELL(dev
)) {
7765 mutex_lock(&dev_priv
->rps
.hw_lock
);
7766 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
,
7768 DRM_ERROR("Failed to write to D_COMP\n");
7769 mutex_unlock(&dev_priv
->rps
.hw_lock
);
7771 I915_WRITE(D_COMP_BDW
, val
);
7772 POSTING_READ(D_COMP_BDW
);
7777 * This function implements pieces of two sequences from BSpec:
7778 * - Sequence for display software to disable LCPLL
7779 * - Sequence for display software to allow package C8+
7780 * The steps implemented here are just the steps that actually touch the LCPLL
7781 * register. Callers should take care of disabling all the display engine
7782 * functions, doing the mode unset, fixing interrupts, etc.
7784 static void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
7785 bool switch_to_fclk
, bool allow_power_down
)
7789 assert_can_disable_lcpll(dev_priv
);
7791 val
= I915_READ(LCPLL_CTL
);
7793 if (switch_to_fclk
) {
7794 val
|= LCPLL_CD_SOURCE_FCLK
;
7795 I915_WRITE(LCPLL_CTL
, val
);
7797 if (wait_for_atomic_us(I915_READ(LCPLL_CTL
) &
7798 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
7799 DRM_ERROR("Switching to FCLK failed\n");
7801 val
= I915_READ(LCPLL_CTL
);
7804 val
|= LCPLL_PLL_DISABLE
;
7805 I915_WRITE(LCPLL_CTL
, val
);
7806 POSTING_READ(LCPLL_CTL
);
7808 if (wait_for((I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
) == 0, 1))
7809 DRM_ERROR("LCPLL still locked\n");
7811 val
= hsw_read_dcomp(dev_priv
);
7812 val
|= D_COMP_COMP_DISABLE
;
7813 hsw_write_dcomp(dev_priv
, val
);
7816 if (wait_for((hsw_read_dcomp(dev_priv
) & D_COMP_RCOMP_IN_PROGRESS
) == 0,
7818 DRM_ERROR("D_COMP RCOMP still in progress\n");
7820 if (allow_power_down
) {
7821 val
= I915_READ(LCPLL_CTL
);
7822 val
|= LCPLL_POWER_DOWN_ALLOW
;
7823 I915_WRITE(LCPLL_CTL
, val
);
7824 POSTING_READ(LCPLL_CTL
);
7829 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7832 static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
7836 val
= I915_READ(LCPLL_CTL
);
7838 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
7839 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
7843 * Make sure we're not on PC8 state before disabling PC8, otherwise
7844 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7846 * The other problem is that hsw_restore_lcpll() is called as part of
7847 * the runtime PM resume sequence, so we can't just call
7848 * gen6_gt_force_wake_get() because that function calls
7849 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7850 * while we are on the resume sequence. So to solve this problem we have
7851 * to call special forcewake code that doesn't touch runtime PM and
7852 * doesn't enable the forcewake delayed work.
7854 spin_lock_irq(&dev_priv
->uncore
.lock
);
7855 if (dev_priv
->uncore
.forcewake_count
++ == 0)
7856 dev_priv
->uncore
.funcs
.force_wake_get(dev_priv
, FORCEWAKE_ALL
);
7857 spin_unlock_irq(&dev_priv
->uncore
.lock
);
7859 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
7860 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
7861 I915_WRITE(LCPLL_CTL
, val
);
7862 POSTING_READ(LCPLL_CTL
);
7865 val
= hsw_read_dcomp(dev_priv
);
7866 val
|= D_COMP_COMP_FORCE
;
7867 val
&= ~D_COMP_COMP_DISABLE
;
7868 hsw_write_dcomp(dev_priv
, val
);
7870 val
= I915_READ(LCPLL_CTL
);
7871 val
&= ~LCPLL_PLL_DISABLE
;
7872 I915_WRITE(LCPLL_CTL
, val
);
7874 if (wait_for(I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
, 5))
7875 DRM_ERROR("LCPLL not locked yet\n");
7877 if (val
& LCPLL_CD_SOURCE_FCLK
) {
7878 val
= I915_READ(LCPLL_CTL
);
7879 val
&= ~LCPLL_CD_SOURCE_FCLK
;
7880 I915_WRITE(LCPLL_CTL
, val
);
7882 if (wait_for_atomic_us((I915_READ(LCPLL_CTL
) &
7883 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
7884 DRM_ERROR("Switching back to LCPLL failed\n");
7887 /* See the big comment above. */
7888 spin_lock_irq(&dev_priv
->uncore
.lock
);
7889 if (--dev_priv
->uncore
.forcewake_count
== 0)
7890 dev_priv
->uncore
.funcs
.force_wake_put(dev_priv
, FORCEWAKE_ALL
);
7891 spin_unlock_irq(&dev_priv
->uncore
.lock
);
7895 * Package states C8 and deeper are really deep PC states that can only be
7896 * reached when all the devices on the system allow it, so even if the graphics
7897 * device allows PC8+, it doesn't mean the system will actually get to these
7898 * states. Our driver only allows PC8+ when going into runtime PM.
7900 * The requirements for PC8+ are that all the outputs are disabled, the power
7901 * well is disabled and most interrupts are disabled, and these are also
7902 * requirements for runtime PM. When these conditions are met, we manually do
7903 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7904 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7907 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7908 * the state of some registers, so when we come back from PC8+ we need to
7909 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7910 * need to take care of the registers kept by RC6. Notice that this happens even
7911 * if we don't put the device in PCI D3 state (which is what currently happens
7912 * because of the runtime PM support).
7914 * For more, read "Display Sequences for Package C8" on the hardware
7917 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
)
7919 struct drm_device
*dev
= dev_priv
->dev
;
7922 DRM_DEBUG_KMS("Enabling package C8+\n");
7924 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
7925 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
7926 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
7927 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
7930 lpt_disable_clkout_dp(dev
);
7931 hsw_disable_lcpll(dev_priv
, true, true);
7934 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
)
7936 struct drm_device
*dev
= dev_priv
->dev
;
7939 DRM_DEBUG_KMS("Disabling package C8+\n");
7941 hsw_restore_lcpll(dev_priv
);
7942 lpt_init_pch_refclk(dev
);
7944 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
7945 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
7946 val
|= PCH_LP_PARTITION_LEVEL_DISABLE
;
7947 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
7950 intel_prepare_ddi(dev
);
7953 static void snb_modeset_global_resources(struct drm_device
*dev
)
7955 modeset_update_crtc_power_domains(dev
);
7958 static void haswell_modeset_global_resources(struct drm_device
*dev
)
7960 modeset_update_crtc_power_domains(dev
);
7963 static int haswell_crtc_compute_clock(struct intel_crtc
*crtc
)
7965 if (!intel_ddi_pll_select(crtc
))
7968 crtc
->lowfreq_avail
= false;
7973 static void haswell_get_ddi_pll(struct drm_i915_private
*dev_priv
,
7975 struct intel_crtc_config
*pipe_config
)
7977 pipe_config
->ddi_pll_sel
= I915_READ(PORT_CLK_SEL(port
));
7979 switch (pipe_config
->ddi_pll_sel
) {
7980 case PORT_CLK_SEL_WRPLL1
:
7981 pipe_config
->shared_dpll
= DPLL_ID_WRPLL1
;
7983 case PORT_CLK_SEL_WRPLL2
:
7984 pipe_config
->shared_dpll
= DPLL_ID_WRPLL2
;
7989 static void haswell_get_ddi_port_state(struct intel_crtc
*crtc
,
7990 struct intel_crtc_config
*pipe_config
)
7992 struct drm_device
*dev
= crtc
->base
.dev
;
7993 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7994 struct intel_shared_dpll
*pll
;
7998 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
8000 port
= (tmp
& TRANS_DDI_PORT_MASK
) >> TRANS_DDI_PORT_SHIFT
;
8002 haswell_get_ddi_pll(dev_priv
, port
, pipe_config
);
8004 if (pipe_config
->shared_dpll
>= 0) {
8005 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
8007 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
8008 &pipe_config
->dpll_hw_state
));
8012 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8013 * DDI E. So just check whether this pipe is wired to DDI E and whether
8014 * the PCH transcoder is on.
8016 if (INTEL_INFO(dev
)->gen
< 9 &&
8017 (port
== PORT_E
) && I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
8018 pipe_config
->has_pch_encoder
= true;
8020 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
8021 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
8022 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
8024 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
8028 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
8029 struct intel_crtc_config
*pipe_config
)
8031 struct drm_device
*dev
= crtc
->base
.dev
;
8032 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8033 enum intel_display_power_domain pfit_domain
;
8036 if (!intel_display_power_is_enabled(dev_priv
,
8037 POWER_DOMAIN_PIPE(crtc
->pipe
)))
8040 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
8041 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
8043 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
8044 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
8045 enum pipe trans_edp_pipe
;
8046 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
8048 WARN(1, "unknown pipe linked to edp transcoder\n");
8049 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
8050 case TRANS_DDI_EDP_INPUT_A_ON
:
8051 trans_edp_pipe
= PIPE_A
;
8053 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
8054 trans_edp_pipe
= PIPE_B
;
8056 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
8057 trans_edp_pipe
= PIPE_C
;
8061 if (trans_edp_pipe
== crtc
->pipe
)
8062 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
8065 if (!intel_display_power_is_enabled(dev_priv
,
8066 POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
)))
8069 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
8070 if (!(tmp
& PIPECONF_ENABLE
))
8073 haswell_get_ddi_port_state(crtc
, pipe_config
);
8075 intel_get_pipe_timings(crtc
, pipe_config
);
8077 pfit_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
8078 if (intel_display_power_is_enabled(dev_priv
, pfit_domain
))
8079 ironlake_get_pfit_config(crtc
, pipe_config
);
8081 if (IS_HASWELL(dev
))
8082 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
8083 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
8085 if (pipe_config
->cpu_transcoder
!= TRANSCODER_EDP
) {
8086 pipe_config
->pixel_multiplier
=
8087 I915_READ(PIPE_MULT(pipe_config
->cpu_transcoder
)) + 1;
8089 pipe_config
->pixel_multiplier
= 1;
8095 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
8097 struct drm_device
*dev
= crtc
->dev
;
8098 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8099 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8100 uint32_t cntl
= 0, size
= 0;
8103 unsigned int width
= intel_crtc
->cursor_width
;
8104 unsigned int height
= intel_crtc
->cursor_height
;
8105 unsigned int stride
= roundup_pow_of_two(width
) * 4;
8109 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8120 cntl
|= CURSOR_ENABLE
|
8121 CURSOR_GAMMA_ENABLE
|
8122 CURSOR_FORMAT_ARGB
|
8123 CURSOR_STRIDE(stride
);
8125 size
= (height
<< 12) | width
;
8128 if (intel_crtc
->cursor_cntl
!= 0 &&
8129 (intel_crtc
->cursor_base
!= base
||
8130 intel_crtc
->cursor_size
!= size
||
8131 intel_crtc
->cursor_cntl
!= cntl
)) {
8132 /* On these chipsets we can only modify the base/size/stride
8133 * whilst the cursor is disabled.
8135 I915_WRITE(_CURACNTR
, 0);
8136 POSTING_READ(_CURACNTR
);
8137 intel_crtc
->cursor_cntl
= 0;
8140 if (intel_crtc
->cursor_base
!= base
) {
8141 I915_WRITE(_CURABASE
, base
);
8142 intel_crtc
->cursor_base
= base
;
8145 if (intel_crtc
->cursor_size
!= size
) {
8146 I915_WRITE(CURSIZE
, size
);
8147 intel_crtc
->cursor_size
= size
;
8150 if (intel_crtc
->cursor_cntl
!= cntl
) {
8151 I915_WRITE(_CURACNTR
, cntl
);
8152 POSTING_READ(_CURACNTR
);
8153 intel_crtc
->cursor_cntl
= cntl
;
8157 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
8159 struct drm_device
*dev
= crtc
->dev
;
8160 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8161 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8162 int pipe
= intel_crtc
->pipe
;
8167 cntl
= MCURSOR_GAMMA_ENABLE
;
8168 switch (intel_crtc
->cursor_width
) {
8170 cntl
|= CURSOR_MODE_64_ARGB_AX
;
8173 cntl
|= CURSOR_MODE_128_ARGB_AX
;
8176 cntl
|= CURSOR_MODE_256_ARGB_AX
;
8182 cntl
|= pipe
<< 28; /* Connect to correct pipe */
8184 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
8185 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
8188 if (to_intel_plane(crtc
->cursor
)->rotation
== BIT(DRM_ROTATE_180
))
8189 cntl
|= CURSOR_ROTATE_180
;
8191 if (intel_crtc
->cursor_cntl
!= cntl
) {
8192 I915_WRITE(CURCNTR(pipe
), cntl
);
8193 POSTING_READ(CURCNTR(pipe
));
8194 intel_crtc
->cursor_cntl
= cntl
;
8197 /* and commit changes on next vblank */
8198 I915_WRITE(CURBASE(pipe
), base
);
8199 POSTING_READ(CURBASE(pipe
));
8201 intel_crtc
->cursor_base
= base
;
8204 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8205 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
8208 struct drm_device
*dev
= crtc
->dev
;
8209 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8210 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8211 int pipe
= intel_crtc
->pipe
;
8212 int x
= crtc
->cursor_x
;
8213 int y
= crtc
->cursor_y
;
8214 u32 base
= 0, pos
= 0;
8217 base
= intel_crtc
->cursor_addr
;
8219 if (x
>= intel_crtc
->config
.pipe_src_w
)
8222 if (y
>= intel_crtc
->config
.pipe_src_h
)
8226 if (x
+ intel_crtc
->cursor_width
<= 0)
8229 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
8232 pos
|= x
<< CURSOR_X_SHIFT
;
8235 if (y
+ intel_crtc
->cursor_height
<= 0)
8238 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
8241 pos
|= y
<< CURSOR_Y_SHIFT
;
8243 if (base
== 0 && intel_crtc
->cursor_base
== 0)
8246 I915_WRITE(CURPOS(pipe
), pos
);
8248 /* ILK+ do this automagically */
8249 if (HAS_GMCH_DISPLAY(dev
) &&
8250 to_intel_plane(crtc
->cursor
)->rotation
== BIT(DRM_ROTATE_180
)) {
8251 base
+= (intel_crtc
->cursor_height
*
8252 intel_crtc
->cursor_width
- 1) * 4;
8255 if (IS_845G(dev
) || IS_I865G(dev
))
8256 i845_update_cursor(crtc
, base
);
8258 i9xx_update_cursor(crtc
, base
);
8261 static bool cursor_size_ok(struct drm_device
*dev
,
8262 uint32_t width
, uint32_t height
)
8264 if (width
== 0 || height
== 0)
8268 * 845g/865g are special in that they are only limited by
8269 * the width of their cursors, the height is arbitrary up to
8270 * the precision of the register. Everything else requires
8271 * square cursors, limited to a few power-of-two sizes.
8273 if (IS_845G(dev
) || IS_I865G(dev
)) {
8274 if ((width
& 63) != 0)
8277 if (width
> (IS_845G(dev
) ? 64 : 512))
8283 switch (width
| height
) {
8298 static int intel_crtc_cursor_set_obj(struct drm_crtc
*crtc
,
8299 struct drm_i915_gem_object
*obj
,
8300 uint32_t width
, uint32_t height
)
8302 struct drm_device
*dev
= crtc
->dev
;
8303 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8304 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8305 enum pipe pipe
= intel_crtc
->pipe
;
8310 /* if we want to turn off the cursor ignore width and height */
8312 DRM_DEBUG_KMS("cursor off\n");
8314 mutex_lock(&dev
->struct_mutex
);
8318 /* we only need to pin inside GTT if cursor is non-phy */
8319 mutex_lock(&dev
->struct_mutex
);
8320 if (!INTEL_INFO(dev
)->cursor_needs_physical
) {
8324 * Global gtt pte registers are special registers which actually
8325 * forward writes to a chunk of system memory. Which means that
8326 * there is no risk that the register values disappear as soon
8327 * as we call intel_runtime_pm_put(), so it is correct to wrap
8328 * only the pin/unpin/fence and not more.
8330 intel_runtime_pm_get(dev_priv
);
8332 /* Note that the w/a also requires 2 PTE of padding following
8333 * the bo. We currently fill all unused PTE with the shadow
8334 * page and so we should always have valid PTE following the
8335 * cursor preventing the VT-d warning.
8338 if (need_vtd_wa(dev
))
8339 alignment
= 64*1024;
8341 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, NULL
);
8343 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8344 intel_runtime_pm_put(dev_priv
);
8348 ret
= i915_gem_object_put_fence(obj
);
8350 DRM_DEBUG_KMS("failed to release fence for cursor");
8351 intel_runtime_pm_put(dev_priv
);
8355 addr
= i915_gem_obj_ggtt_offset(obj
);
8357 intel_runtime_pm_put(dev_priv
);
8359 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
8360 ret
= i915_gem_object_attach_phys(obj
, align
);
8362 DRM_DEBUG_KMS("failed to attach phys object\n");
8365 addr
= obj
->phys_handle
->busaddr
;
8369 if (intel_crtc
->cursor_bo
) {
8370 if (!INTEL_INFO(dev
)->cursor_needs_physical
)
8371 i915_gem_object_unpin_from_display_plane(intel_crtc
->cursor_bo
);
8374 i915_gem_track_fb(intel_crtc
->cursor_bo
, obj
,
8375 INTEL_FRONTBUFFER_CURSOR(pipe
));
8376 mutex_unlock(&dev
->struct_mutex
);
8378 old_width
= intel_crtc
->cursor_width
;
8380 intel_crtc
->cursor_addr
= addr
;
8381 intel_crtc
->cursor_bo
= obj
;
8382 intel_crtc
->cursor_width
= width
;
8383 intel_crtc
->cursor_height
= height
;
8385 if (intel_crtc
->active
) {
8386 if (old_width
!= width
)
8387 intel_update_watermarks(crtc
);
8388 intel_crtc_update_cursor(crtc
, intel_crtc
->cursor_bo
!= NULL
);
8390 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_CURSOR(pipe
));
8395 i915_gem_object_unpin_from_display_plane(obj
);
8397 mutex_unlock(&dev
->struct_mutex
);
8401 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
8402 u16
*blue
, uint32_t start
, uint32_t size
)
8404 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
8405 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8407 for (i
= start
; i
< end
; i
++) {
8408 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
8409 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
8410 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
8413 intel_crtc_load_lut(crtc
);
8416 /* VESA 640x480x72Hz mode to set on the pipe */
8417 static struct drm_display_mode load_detect_mode
= {
8418 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
8419 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
8422 struct drm_framebuffer
*
8423 __intel_framebuffer_create(struct drm_device
*dev
,
8424 struct drm_mode_fb_cmd2
*mode_cmd
,
8425 struct drm_i915_gem_object
*obj
)
8427 struct intel_framebuffer
*intel_fb
;
8430 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
8432 drm_gem_object_unreference_unlocked(&obj
->base
);
8433 return ERR_PTR(-ENOMEM
);
8436 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
8440 return &intel_fb
->base
;
8442 drm_gem_object_unreference_unlocked(&obj
->base
);
8445 return ERR_PTR(ret
);
8448 static struct drm_framebuffer
*
8449 intel_framebuffer_create(struct drm_device
*dev
,
8450 struct drm_mode_fb_cmd2
*mode_cmd
,
8451 struct drm_i915_gem_object
*obj
)
8453 struct drm_framebuffer
*fb
;
8456 ret
= i915_mutex_lock_interruptible(dev
);
8458 return ERR_PTR(ret
);
8459 fb
= __intel_framebuffer_create(dev
, mode_cmd
, obj
);
8460 mutex_unlock(&dev
->struct_mutex
);
8466 intel_framebuffer_pitch_for_width(int width
, int bpp
)
8468 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
8469 return ALIGN(pitch
, 64);
8473 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
8475 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
8476 return PAGE_ALIGN(pitch
* mode
->vdisplay
);
8479 static struct drm_framebuffer
*
8480 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
8481 struct drm_display_mode
*mode
,
8484 struct drm_i915_gem_object
*obj
;
8485 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
8487 obj
= i915_gem_alloc_object(dev
,
8488 intel_framebuffer_size_for_mode(mode
, bpp
));
8490 return ERR_PTR(-ENOMEM
);
8492 mode_cmd
.width
= mode
->hdisplay
;
8493 mode_cmd
.height
= mode
->vdisplay
;
8494 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
8496 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
8498 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
8501 static struct drm_framebuffer
*
8502 mode_fits_in_fbdev(struct drm_device
*dev
,
8503 struct drm_display_mode
*mode
)
8505 #ifdef CONFIG_DRM_I915_FBDEV
8506 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8507 struct drm_i915_gem_object
*obj
;
8508 struct drm_framebuffer
*fb
;
8510 if (!dev_priv
->fbdev
)
8513 if (!dev_priv
->fbdev
->fb
)
8516 obj
= dev_priv
->fbdev
->fb
->obj
;
8519 fb
= &dev_priv
->fbdev
->fb
->base
;
8520 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
8521 fb
->bits_per_pixel
))
8524 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
8533 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
8534 struct drm_display_mode
*mode
,
8535 struct intel_load_detect_pipe
*old
,
8536 struct drm_modeset_acquire_ctx
*ctx
)
8538 struct intel_crtc
*intel_crtc
;
8539 struct intel_encoder
*intel_encoder
=
8540 intel_attached_encoder(connector
);
8541 struct drm_crtc
*possible_crtc
;
8542 struct drm_encoder
*encoder
= &intel_encoder
->base
;
8543 struct drm_crtc
*crtc
= NULL
;
8544 struct drm_device
*dev
= encoder
->dev
;
8545 struct drm_framebuffer
*fb
;
8546 struct drm_mode_config
*config
= &dev
->mode_config
;
8549 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8550 connector
->base
.id
, connector
->name
,
8551 encoder
->base
.id
, encoder
->name
);
8554 ret
= drm_modeset_lock(&config
->connection_mutex
, ctx
);
8559 * Algorithm gets a little messy:
8561 * - if the connector already has an assigned crtc, use it (but make
8562 * sure it's on first)
8564 * - try to find the first unused crtc that can drive this connector,
8565 * and use that if we find one
8568 /* See if we already have a CRTC for this connector */
8569 if (encoder
->crtc
) {
8570 crtc
= encoder
->crtc
;
8572 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
8576 old
->dpms_mode
= connector
->dpms
;
8577 old
->load_detect_temp
= false;
8579 /* Make sure the crtc and connector are running */
8580 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
8581 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
8586 /* Find an unused one (if possible) */
8587 for_each_crtc(dev
, possible_crtc
) {
8589 if (!(encoder
->possible_crtcs
& (1 << i
)))
8591 if (possible_crtc
->enabled
)
8593 /* This can occur when applying the pipe A quirk on resume. */
8594 if (to_intel_crtc(possible_crtc
)->new_enabled
)
8597 crtc
= possible_crtc
;
8602 * If we didn't find an unused CRTC, don't use any.
8605 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8609 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
8612 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
8613 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
8615 intel_crtc
= to_intel_crtc(crtc
);
8616 intel_crtc
->new_enabled
= true;
8617 intel_crtc
->new_config
= &intel_crtc
->config
;
8618 old
->dpms_mode
= connector
->dpms
;
8619 old
->load_detect_temp
= true;
8620 old
->release_fb
= NULL
;
8623 mode
= &load_detect_mode
;
8625 /* We need a framebuffer large enough to accommodate all accesses
8626 * that the plane may generate whilst we perform load detection.
8627 * We can not rely on the fbcon either being present (we get called
8628 * during its initialisation to detect all boot displays, or it may
8629 * not even exist) or that it is large enough to satisfy the
8632 fb
= mode_fits_in_fbdev(dev
, mode
);
8634 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8635 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
8636 old
->release_fb
= fb
;
8638 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8640 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8644 if (intel_set_mode(crtc
, mode
, 0, 0, fb
)) {
8645 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8646 if (old
->release_fb
)
8647 old
->release_fb
->funcs
->destroy(old
->release_fb
);
8651 /* let the connector get through one full cycle before testing */
8652 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
8656 intel_crtc
->new_enabled
= crtc
->enabled
;
8657 if (intel_crtc
->new_enabled
)
8658 intel_crtc
->new_config
= &intel_crtc
->config
;
8660 intel_crtc
->new_config
= NULL
;
8662 if (ret
== -EDEADLK
) {
8663 drm_modeset_backoff(ctx
);
8670 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
8671 struct intel_load_detect_pipe
*old
)
8673 struct intel_encoder
*intel_encoder
=
8674 intel_attached_encoder(connector
);
8675 struct drm_encoder
*encoder
= &intel_encoder
->base
;
8676 struct drm_crtc
*crtc
= encoder
->crtc
;
8677 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8679 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8680 connector
->base
.id
, connector
->name
,
8681 encoder
->base
.id
, encoder
->name
);
8683 if (old
->load_detect_temp
) {
8684 to_intel_connector(connector
)->new_encoder
= NULL
;
8685 intel_encoder
->new_crtc
= NULL
;
8686 intel_crtc
->new_enabled
= false;
8687 intel_crtc
->new_config
= NULL
;
8688 intel_set_mode(crtc
, NULL
, 0, 0, NULL
);
8690 if (old
->release_fb
) {
8691 drm_framebuffer_unregister_private(old
->release_fb
);
8692 drm_framebuffer_unreference(old
->release_fb
);
8698 /* Switch crtc and encoder back off if necessary */
8699 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
8700 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
8703 static int i9xx_pll_refclk(struct drm_device
*dev
,
8704 const struct intel_crtc_config
*pipe_config
)
8706 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8707 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
8709 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
8710 return dev_priv
->vbt
.lvds_ssc_freq
;
8711 else if (HAS_PCH_SPLIT(dev
))
8713 else if (!IS_GEN2(dev
))
8719 /* Returns the clock of the currently programmed mode of the given pipe. */
8720 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
8721 struct intel_crtc_config
*pipe_config
)
8723 struct drm_device
*dev
= crtc
->base
.dev
;
8724 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8725 int pipe
= pipe_config
->cpu_transcoder
;
8726 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
8728 intel_clock_t clock
;
8729 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
8731 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
8732 fp
= pipe_config
->dpll_hw_state
.fp0
;
8734 fp
= pipe_config
->dpll_hw_state
.fp1
;
8736 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
8737 if (IS_PINEVIEW(dev
)) {
8738 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
8739 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
8741 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
8742 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
8745 if (!IS_GEN2(dev
)) {
8746 if (IS_PINEVIEW(dev
))
8747 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
8748 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
8750 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
8751 DPLL_FPA01_P1_POST_DIV_SHIFT
);
8753 switch (dpll
& DPLL_MODE_MASK
) {
8754 case DPLLB_MODE_DAC_SERIAL
:
8755 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
8758 case DPLLB_MODE_LVDS
:
8759 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
8763 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8764 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
8768 if (IS_PINEVIEW(dev
))
8769 pineview_clock(refclk
, &clock
);
8771 i9xx_clock(refclk
, &clock
);
8773 u32 lvds
= IS_I830(dev
) ? 0 : I915_READ(LVDS
);
8774 bool is_lvds
= (pipe
== 1) && (lvds
& LVDS_PORT_EN
);
8777 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
8778 DPLL_FPA01_P1_POST_DIV_SHIFT
);
8780 if (lvds
& LVDS_CLKB_POWER_UP
)
8785 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
8788 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
8789 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
8791 if (dpll
& PLL_P2_DIVIDE_BY_4
)
8797 i9xx_clock(refclk
, &clock
);
8801 * This value includes pixel_multiplier. We will use
8802 * port_clock to compute adjusted_mode.crtc_clock in the
8803 * encoder's get_config() function.
8805 pipe_config
->port_clock
= clock
.dot
;
8808 int intel_dotclock_calculate(int link_freq
,
8809 const struct intel_link_m_n
*m_n
)
8812 * The calculation for the data clock is:
8813 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8814 * But we want to avoid losing precison if possible, so:
8815 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8817 * and the link clock is simpler:
8818 * link_clock = (m * link_clock) / n
8824 return div_u64((u64
)m_n
->link_m
* link_freq
, m_n
->link_n
);
8827 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
8828 struct intel_crtc_config
*pipe_config
)
8830 struct drm_device
*dev
= crtc
->base
.dev
;
8832 /* read out port_clock from the DPLL */
8833 i9xx_crtc_clock_get(crtc
, pipe_config
);
8836 * This value does not include pixel_multiplier.
8837 * We will check that port_clock and adjusted_mode.crtc_clock
8838 * agree once we know their relationship in the encoder's
8839 * get_config() function.
8841 pipe_config
->adjusted_mode
.crtc_clock
=
8842 intel_dotclock_calculate(intel_fdi_link_freq(dev
) * 10000,
8843 &pipe_config
->fdi_m_n
);
8846 /** Returns the currently programmed mode of the given pipe. */
8847 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
8848 struct drm_crtc
*crtc
)
8850 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8851 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8852 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
8853 struct drm_display_mode
*mode
;
8854 struct intel_crtc_config pipe_config
;
8855 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
8856 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
8857 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
8858 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
8859 enum pipe pipe
= intel_crtc
->pipe
;
8861 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
8866 * Construct a pipe_config sufficient for getting the clock info
8867 * back out of crtc_clock_get.
8869 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8870 * to use a real value here instead.
8872 pipe_config
.cpu_transcoder
= (enum transcoder
) pipe
;
8873 pipe_config
.pixel_multiplier
= 1;
8874 pipe_config
.dpll_hw_state
.dpll
= I915_READ(DPLL(pipe
));
8875 pipe_config
.dpll_hw_state
.fp0
= I915_READ(FP0(pipe
));
8876 pipe_config
.dpll_hw_state
.fp1
= I915_READ(FP1(pipe
));
8877 i9xx_crtc_clock_get(intel_crtc
, &pipe_config
);
8879 mode
->clock
= pipe_config
.port_clock
/ pipe_config
.pixel_multiplier
;
8880 mode
->hdisplay
= (htot
& 0xffff) + 1;
8881 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
8882 mode
->hsync_start
= (hsync
& 0xffff) + 1;
8883 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
8884 mode
->vdisplay
= (vtot
& 0xffff) + 1;
8885 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
8886 mode
->vsync_start
= (vsync
& 0xffff) + 1;
8887 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
8889 drm_mode_set_name(mode
);
8894 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
8896 struct drm_device
*dev
= crtc
->dev
;
8897 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8898 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8900 if (!HAS_GMCH_DISPLAY(dev
))
8903 if (!dev_priv
->lvds_downclock_avail
)
8907 * Since this is called by a timer, we should never get here in
8910 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
8911 int pipe
= intel_crtc
->pipe
;
8912 int dpll_reg
= DPLL(pipe
);
8915 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8917 assert_panel_unlocked(dev_priv
, pipe
);
8919 dpll
= I915_READ(dpll_reg
);
8920 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
8921 I915_WRITE(dpll_reg
, dpll
);
8922 intel_wait_for_vblank(dev
, pipe
);
8923 dpll
= I915_READ(dpll_reg
);
8924 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
8925 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8930 void intel_mark_busy(struct drm_device
*dev
)
8932 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8934 if (dev_priv
->mm
.busy
)
8937 intel_runtime_pm_get(dev_priv
);
8938 i915_update_gfx_val(dev_priv
);
8939 dev_priv
->mm
.busy
= true;
8942 void intel_mark_idle(struct drm_device
*dev
)
8944 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8945 struct drm_crtc
*crtc
;
8947 if (!dev_priv
->mm
.busy
)
8950 dev_priv
->mm
.busy
= false;
8952 if (!i915
.powersave
)
8955 for_each_crtc(dev
, crtc
) {
8956 if (!crtc
->primary
->fb
)
8959 intel_decrease_pllclock(crtc
);
8962 if (INTEL_INFO(dev
)->gen
>= 6)
8963 gen6_rps_idle(dev
->dev_private
);
8966 intel_runtime_pm_put(dev_priv
);
8969 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
8971 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8972 struct drm_device
*dev
= crtc
->dev
;
8973 struct intel_unpin_work
*work
;
8975 spin_lock_irq(&dev
->event_lock
);
8976 work
= intel_crtc
->unpin_work
;
8977 intel_crtc
->unpin_work
= NULL
;
8978 spin_unlock_irq(&dev
->event_lock
);
8981 cancel_work_sync(&work
->work
);
8985 drm_crtc_cleanup(crtc
);
8990 static void intel_unpin_work_fn(struct work_struct
*__work
)
8992 struct intel_unpin_work
*work
=
8993 container_of(__work
, struct intel_unpin_work
, work
);
8994 struct drm_device
*dev
= work
->crtc
->dev
;
8995 enum pipe pipe
= to_intel_crtc(work
->crtc
)->pipe
;
8997 mutex_lock(&dev
->struct_mutex
);
8998 intel_unpin_fb_obj(work
->old_fb_obj
);
8999 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
9000 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
9002 intel_update_fbc(dev
);
9003 mutex_unlock(&dev
->struct_mutex
);
9005 intel_frontbuffer_flip_complete(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
9007 BUG_ON(atomic_read(&to_intel_crtc(work
->crtc
)->unpin_work_count
) == 0);
9008 atomic_dec(&to_intel_crtc(work
->crtc
)->unpin_work_count
);
9013 static void do_intel_finish_page_flip(struct drm_device
*dev
,
9014 struct drm_crtc
*crtc
)
9016 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9017 struct intel_unpin_work
*work
;
9018 unsigned long flags
;
9020 /* Ignore early vblank irqs */
9021 if (intel_crtc
== NULL
)
9025 * This is called both by irq handlers and the reset code (to complete
9026 * lost pageflips) so needs the full irqsave spinlocks.
9028 spin_lock_irqsave(&dev
->event_lock
, flags
);
9029 work
= intel_crtc
->unpin_work
;
9031 /* Ensure we don't miss a work->pending update ... */
9034 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
9035 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9039 page_flip_completed(intel_crtc
);
9041 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9044 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
9046 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9047 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
9049 do_intel_finish_page_flip(dev
, crtc
);
9052 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
9054 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9055 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
9057 do_intel_finish_page_flip(dev
, crtc
);
9060 /* Is 'a' after or equal to 'b'? */
9061 static bool g4x_flip_count_after_eq(u32 a
, u32 b
)
9063 return !((a
- b
) & 0x80000000);
9066 static bool page_flip_finished(struct intel_crtc
*crtc
)
9068 struct drm_device
*dev
= crtc
->base
.dev
;
9069 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9072 * The relevant registers doen't exist on pre-ctg.
9073 * As the flip done interrupt doesn't trigger for mmio
9074 * flips on gmch platforms, a flip count check isn't
9075 * really needed there. But since ctg has the registers,
9076 * include it in the check anyway.
9078 if (INTEL_INFO(dev
)->gen
< 5 && !IS_G4X(dev
))
9082 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9083 * used the same base address. In that case the mmio flip might
9084 * have completed, but the CS hasn't even executed the flip yet.
9086 * A flip count check isn't enough as the CS might have updated
9087 * the base address just after start of vblank, but before we
9088 * managed to process the interrupt. This means we'd complete the
9091 * Combining both checks should get us a good enough result. It may
9092 * still happen that the CS flip has been executed, but has not
9093 * yet actually completed. But in case the base address is the same
9094 * anyway, we don't really care.
9096 return (I915_READ(DSPSURFLIVE(crtc
->plane
)) & ~0xfff) ==
9097 crtc
->unpin_work
->gtt_offset
&&
9098 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc
->pipe
)),
9099 crtc
->unpin_work
->flip_count
);
9102 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
9104 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9105 struct intel_crtc
*intel_crtc
=
9106 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
9107 unsigned long flags
;
9111 * This is called both by irq handlers and the reset code (to complete
9112 * lost pageflips) so needs the full irqsave spinlocks.
9114 * NB: An MMIO update of the plane base pointer will also
9115 * generate a page-flip completion irq, i.e. every modeset
9116 * is also accompanied by a spurious intel_prepare_page_flip().
9118 spin_lock_irqsave(&dev
->event_lock
, flags
);
9119 if (intel_crtc
->unpin_work
&& page_flip_finished(intel_crtc
))
9120 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
9121 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9124 static inline void intel_mark_page_flip_active(struct intel_crtc
*intel_crtc
)
9126 /* Ensure that the work item is consistent when activating it ... */
9128 atomic_set(&intel_crtc
->unpin_work
->pending
, INTEL_FLIP_PENDING
);
9129 /* and that it is marked active as soon as the irq could fire. */
9133 static int intel_gen2_queue_flip(struct drm_device
*dev
,
9134 struct drm_crtc
*crtc
,
9135 struct drm_framebuffer
*fb
,
9136 struct drm_i915_gem_object
*obj
,
9137 struct intel_engine_cs
*ring
,
9140 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9144 ret
= intel_ring_begin(ring
, 6);
9148 /* Can't queue multiple flips, so wait for the previous
9149 * one to finish before executing the next.
9151 if (intel_crtc
->plane
)
9152 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
9154 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
9155 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
9156 intel_ring_emit(ring
, MI_NOOP
);
9157 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9158 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9159 intel_ring_emit(ring
, fb
->pitches
[0]);
9160 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9161 intel_ring_emit(ring
, 0); /* aux display base address, unused */
9163 intel_mark_page_flip_active(intel_crtc
);
9164 __intel_ring_advance(ring
);
9168 static int intel_gen3_queue_flip(struct drm_device
*dev
,
9169 struct drm_crtc
*crtc
,
9170 struct drm_framebuffer
*fb
,
9171 struct drm_i915_gem_object
*obj
,
9172 struct intel_engine_cs
*ring
,
9175 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9179 ret
= intel_ring_begin(ring
, 6);
9183 if (intel_crtc
->plane
)
9184 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
9186 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
9187 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
9188 intel_ring_emit(ring
, MI_NOOP
);
9189 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
9190 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9191 intel_ring_emit(ring
, fb
->pitches
[0]);
9192 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9193 intel_ring_emit(ring
, MI_NOOP
);
9195 intel_mark_page_flip_active(intel_crtc
);
9196 __intel_ring_advance(ring
);
9200 static int intel_gen4_queue_flip(struct drm_device
*dev
,
9201 struct drm_crtc
*crtc
,
9202 struct drm_framebuffer
*fb
,
9203 struct drm_i915_gem_object
*obj
,
9204 struct intel_engine_cs
*ring
,
9207 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9208 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9209 uint32_t pf
, pipesrc
;
9212 ret
= intel_ring_begin(ring
, 4);
9216 /* i965+ uses the linear or tiled offsets from the
9217 * Display Registers (which do not change across a page-flip)
9218 * so we need only reprogram the base address.
9220 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9221 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9222 intel_ring_emit(ring
, fb
->pitches
[0]);
9223 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
|
9226 /* XXX Enabling the panel-fitter across page-flip is so far
9227 * untested on non-native modes, so ignore it for now.
9228 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9231 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
9232 intel_ring_emit(ring
, pf
| pipesrc
);
9234 intel_mark_page_flip_active(intel_crtc
);
9235 __intel_ring_advance(ring
);
9239 static int intel_gen6_queue_flip(struct drm_device
*dev
,
9240 struct drm_crtc
*crtc
,
9241 struct drm_framebuffer
*fb
,
9242 struct drm_i915_gem_object
*obj
,
9243 struct intel_engine_cs
*ring
,
9246 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9247 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9248 uint32_t pf
, pipesrc
;
9251 ret
= intel_ring_begin(ring
, 4);
9255 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9256 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9257 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
9258 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9260 /* Contrary to the suggestions in the documentation,
9261 * "Enable Panel Fitter" does not seem to be required when page
9262 * flipping with a non-native mode, and worse causes a normal
9264 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9267 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
9268 intel_ring_emit(ring
, pf
| pipesrc
);
9270 intel_mark_page_flip_active(intel_crtc
);
9271 __intel_ring_advance(ring
);
9275 static int intel_gen7_queue_flip(struct drm_device
*dev
,
9276 struct drm_crtc
*crtc
,
9277 struct drm_framebuffer
*fb
,
9278 struct drm_i915_gem_object
*obj
,
9279 struct intel_engine_cs
*ring
,
9282 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9283 uint32_t plane_bit
= 0;
9286 switch (intel_crtc
->plane
) {
9288 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
9291 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
9294 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
9297 WARN_ONCE(1, "unknown plane in flip command\n");
9302 if (ring
->id
== RCS
) {
9305 * On Gen 8, SRM is now taking an extra dword to accommodate
9306 * 48bits addresses, and we need a NOOP for the batch size to
9314 * BSpec MI_DISPLAY_FLIP for IVB:
9315 * "The full packet must be contained within the same cache line."
9317 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9318 * cacheline, if we ever start emitting more commands before
9319 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9320 * then do the cacheline alignment, and finally emit the
9323 ret
= intel_ring_cacheline_align(ring
);
9327 ret
= intel_ring_begin(ring
, len
);
9331 /* Unmask the flip-done completion message. Note that the bspec says that
9332 * we should do this for both the BCS and RCS, and that we must not unmask
9333 * more than one flip event at any time (or ensure that one flip message
9334 * can be sent by waiting for flip-done prior to queueing new flips).
9335 * Experimentation says that BCS works despite DERRMR masking all
9336 * flip-done completion events and that unmasking all planes at once
9337 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9338 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9340 if (ring
->id
== RCS
) {
9341 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
9342 intel_ring_emit(ring
, DERRMR
);
9343 intel_ring_emit(ring
, ~(DERRMR_PIPEA_PRI_FLIP_DONE
|
9344 DERRMR_PIPEB_PRI_FLIP_DONE
|
9345 DERRMR_PIPEC_PRI_FLIP_DONE
));
9347 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM_GEN8(1) |
9348 MI_SRM_LRM_GLOBAL_GTT
);
9350 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM(1) |
9351 MI_SRM_LRM_GLOBAL_GTT
);
9352 intel_ring_emit(ring
, DERRMR
);
9353 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
+ 256);
9355 intel_ring_emit(ring
, 0);
9356 intel_ring_emit(ring
, MI_NOOP
);
9360 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
9361 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
9362 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9363 intel_ring_emit(ring
, (MI_NOOP
));
9365 intel_mark_page_flip_active(intel_crtc
);
9366 __intel_ring_advance(ring
);
9370 static bool use_mmio_flip(struct intel_engine_cs
*ring
,
9371 struct drm_i915_gem_object
*obj
)
9374 * This is not being used for older platforms, because
9375 * non-availability of flip done interrupt forces us to use
9376 * CS flips. Older platforms derive flip done using some clever
9377 * tricks involving the flip_pending status bits and vblank irqs.
9378 * So using MMIO flips there would disrupt this mechanism.
9384 if (INTEL_INFO(ring
->dev
)->gen
< 5)
9387 if (i915
.use_mmio_flip
< 0)
9389 else if (i915
.use_mmio_flip
> 0)
9391 else if (i915
.enable_execlists
)
9394 return ring
!= obj
->ring
;
9397 static void intel_do_mmio_flip(struct intel_crtc
*intel_crtc
)
9399 struct drm_device
*dev
= intel_crtc
->base
.dev
;
9400 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9401 struct intel_framebuffer
*intel_fb
=
9402 to_intel_framebuffer(intel_crtc
->base
.primary
->fb
);
9403 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
9405 u32 start_vbl_count
;
9409 intel_mark_page_flip_active(intel_crtc
);
9411 atomic_update
= intel_pipe_update_start(intel_crtc
, &start_vbl_count
);
9413 reg
= DSPCNTR(intel_crtc
->plane
);
9414 dspcntr
= I915_READ(reg
);
9416 if (obj
->tiling_mode
!= I915_TILING_NONE
)
9417 dspcntr
|= DISPPLANE_TILED
;
9419 dspcntr
&= ~DISPPLANE_TILED
;
9421 I915_WRITE(reg
, dspcntr
);
9423 I915_WRITE(DSPSURF(intel_crtc
->plane
),
9424 intel_crtc
->unpin_work
->gtt_offset
);
9425 POSTING_READ(DSPSURF(intel_crtc
->plane
));
9428 intel_pipe_update_end(intel_crtc
, start_vbl_count
);
9430 spin_lock_irq(&dev_priv
->mmio_flip_lock
);
9431 intel_crtc
->mmio_flip
.status
= INTEL_MMIO_FLIP_IDLE
;
9432 spin_unlock_irq(&dev_priv
->mmio_flip_lock
);
9435 static void intel_mmio_flip_work_func(struct work_struct
*work
)
9437 struct intel_crtc
*intel_crtc
=
9438 container_of(work
, struct intel_crtc
, mmio_flip
.work
);
9440 intel_do_mmio_flip(intel_crtc
);
9443 static int intel_postpone_flip(struct drm_i915_gem_object
*obj
)
9445 struct intel_engine_cs
*ring
;
9448 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
9450 if (!obj
->last_write_seqno
)
9455 if (i915_seqno_passed(ring
->get_seqno(ring
, true),
9456 obj
->last_write_seqno
))
9459 ret
= i915_gem_check_olr(ring
, obj
->last_write_seqno
);
9463 if (WARN_ON(!ring
->irq_get(ring
)))
9469 void intel_notify_mmio_flip(struct intel_engine_cs
*ring
)
9471 struct drm_i915_private
*dev_priv
= to_i915(ring
->dev
);
9472 struct intel_crtc
*intel_crtc
;
9473 unsigned long irq_flags
;
9476 seqno
= ring
->get_seqno(ring
, false);
9478 spin_lock_irqsave(&dev_priv
->mmio_flip_lock
, irq_flags
);
9479 for_each_intel_crtc(ring
->dev
, intel_crtc
) {
9480 struct intel_mmio_flip
*mmio_flip
;
9482 mmio_flip
= &intel_crtc
->mmio_flip
;
9483 if (mmio_flip
->status
!= INTEL_MMIO_FLIP_WAIT_RING
)
9486 if (ring
->id
!= mmio_flip
->ring_id
)
9489 if (i915_seqno_passed(seqno
, mmio_flip
->seqno
)) {
9490 schedule_work(&intel_crtc
->mmio_flip
.work
);
9491 mmio_flip
->status
= INTEL_MMIO_FLIP_WORK_SCHEDULED
;
9492 ring
->irq_put(ring
);
9495 spin_unlock_irqrestore(&dev_priv
->mmio_flip_lock
, irq_flags
);
9498 static int intel_queue_mmio_flip(struct drm_device
*dev
,
9499 struct drm_crtc
*crtc
,
9500 struct drm_framebuffer
*fb
,
9501 struct drm_i915_gem_object
*obj
,
9502 struct intel_engine_cs
*ring
,
9505 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9506 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9509 if (WARN_ON(intel_crtc
->mmio_flip
.status
!= INTEL_MMIO_FLIP_IDLE
))
9512 ret
= intel_postpone_flip(obj
);
9516 intel_do_mmio_flip(intel_crtc
);
9520 spin_lock_irq(&dev_priv
->mmio_flip_lock
);
9521 intel_crtc
->mmio_flip
.status
= INTEL_MMIO_FLIP_WAIT_RING
;
9522 intel_crtc
->mmio_flip
.seqno
= obj
->last_write_seqno
;
9523 intel_crtc
->mmio_flip
.ring_id
= obj
->ring
->id
;
9524 spin_unlock_irq(&dev_priv
->mmio_flip_lock
);
9527 * Double check to catch cases where irq fired before
9528 * mmio flip data was ready
9530 intel_notify_mmio_flip(obj
->ring
);
9534 static int intel_default_queue_flip(struct drm_device
*dev
,
9535 struct drm_crtc
*crtc
,
9536 struct drm_framebuffer
*fb
,
9537 struct drm_i915_gem_object
*obj
,
9538 struct intel_engine_cs
*ring
,
9544 static bool __intel_pageflip_stall_check(struct drm_device
*dev
,
9545 struct drm_crtc
*crtc
)
9547 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9548 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9549 struct intel_unpin_work
*work
= intel_crtc
->unpin_work
;
9552 if (atomic_read(&work
->pending
) >= INTEL_FLIP_COMPLETE
)
9555 if (!work
->enable_stall_check
)
9558 if (work
->flip_ready_vblank
== 0) {
9559 if (work
->flip_queued_ring
&&
9560 !i915_seqno_passed(work
->flip_queued_ring
->get_seqno(work
->flip_queued_ring
, true),
9561 work
->flip_queued_seqno
))
9564 work
->flip_ready_vblank
= drm_vblank_count(dev
, intel_crtc
->pipe
);
9567 if (drm_vblank_count(dev
, intel_crtc
->pipe
) - work
->flip_ready_vblank
< 3)
9570 /* Potential stall - if we see that the flip has happened,
9571 * assume a missed interrupt. */
9572 if (INTEL_INFO(dev
)->gen
>= 4)
9573 addr
= I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc
->plane
)));
9575 addr
= I915_READ(DSPADDR(intel_crtc
->plane
));
9577 /* There is a potential issue here with a false positive after a flip
9578 * to the same address. We could address this by checking for a
9579 * non-incrementing frame counter.
9581 return addr
== work
->gtt_offset
;
9584 void intel_check_page_flip(struct drm_device
*dev
, int pipe
)
9586 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9587 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
9588 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9595 spin_lock(&dev
->event_lock
);
9596 if (intel_crtc
->unpin_work
&& __intel_pageflip_stall_check(dev
, crtc
)) {
9597 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9598 intel_crtc
->unpin_work
->flip_queued_vblank
, drm_vblank_count(dev
, pipe
));
9599 page_flip_completed(intel_crtc
);
9601 spin_unlock(&dev
->event_lock
);
9604 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
9605 struct drm_framebuffer
*fb
,
9606 struct drm_pending_vblank_event
*event
,
9607 uint32_t page_flip_flags
)
9609 struct drm_device
*dev
= crtc
->dev
;
9610 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9611 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
9612 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
9613 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9614 enum pipe pipe
= intel_crtc
->pipe
;
9615 struct intel_unpin_work
*work
;
9616 struct intel_engine_cs
*ring
;
9620 * drm_mode_page_flip_ioctl() should already catch this, but double
9621 * check to be safe. In the future we may enable pageflipping from
9622 * a disabled primary plane.
9624 if (WARN_ON(intel_fb_obj(old_fb
) == NULL
))
9627 /* Can't change pixel format via MI display flips. */
9628 if (fb
->pixel_format
!= crtc
->primary
->fb
->pixel_format
)
9632 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9633 * Note that pitch changes could also affect these register.
9635 if (INTEL_INFO(dev
)->gen
> 3 &&
9636 (fb
->offsets
[0] != crtc
->primary
->fb
->offsets
[0] ||
9637 fb
->pitches
[0] != crtc
->primary
->fb
->pitches
[0]))
9640 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
9643 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
9647 work
->event
= event
;
9649 work
->old_fb_obj
= intel_fb_obj(old_fb
);
9650 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
9652 ret
= drm_crtc_vblank_get(crtc
);
9656 /* We borrow the event spin lock for protecting unpin_work */
9657 spin_lock_irq(&dev
->event_lock
);
9658 if (intel_crtc
->unpin_work
) {
9659 /* Before declaring the flip queue wedged, check if
9660 * the hardware completed the operation behind our backs.
9662 if (__intel_pageflip_stall_check(dev
, crtc
)) {
9663 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9664 page_flip_completed(intel_crtc
);
9666 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9667 spin_unlock_irq(&dev
->event_lock
);
9669 drm_crtc_vblank_put(crtc
);
9674 intel_crtc
->unpin_work
= work
;
9675 spin_unlock_irq(&dev
->event_lock
);
9677 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
9678 flush_workqueue(dev_priv
->wq
);
9680 ret
= i915_mutex_lock_interruptible(dev
);
9684 /* Reference the objects for the scheduled work. */
9685 drm_gem_object_reference(&work
->old_fb_obj
->base
);
9686 drm_gem_object_reference(&obj
->base
);
9688 crtc
->primary
->fb
= fb
;
9690 work
->pending_flip_obj
= obj
;
9692 atomic_inc(&intel_crtc
->unpin_work_count
);
9693 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
9695 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
9696 work
->flip_count
= I915_READ(PIPE_FLIPCOUNT_GM45(pipe
)) + 1;
9698 if (IS_VALLEYVIEW(dev
)) {
9699 ring
= &dev_priv
->ring
[BCS
];
9700 if (obj
->tiling_mode
!= work
->old_fb_obj
->tiling_mode
)
9701 /* vlv: DISPLAY_FLIP fails to change tiling */
9703 } else if (IS_IVYBRIDGE(dev
)) {
9704 ring
= &dev_priv
->ring
[BCS
];
9705 } else if (INTEL_INFO(dev
)->gen
>= 7) {
9707 if (ring
== NULL
|| ring
->id
!= RCS
)
9708 ring
= &dev_priv
->ring
[BCS
];
9710 ring
= &dev_priv
->ring
[RCS
];
9713 ret
= intel_pin_and_fence_fb_obj(crtc
->primary
, fb
, ring
);
9715 goto cleanup_pending
;
9718 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
;
9720 if (use_mmio_flip(ring
, obj
)) {
9721 ret
= intel_queue_mmio_flip(dev
, crtc
, fb
, obj
, ring
,
9726 work
->flip_queued_seqno
= obj
->last_write_seqno
;
9727 work
->flip_queued_ring
= obj
->ring
;
9729 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
, ring
,
9734 work
->flip_queued_seqno
= intel_ring_get_seqno(ring
);
9735 work
->flip_queued_ring
= ring
;
9738 work
->flip_queued_vblank
= drm_vblank_count(dev
, intel_crtc
->pipe
);
9739 work
->enable_stall_check
= true;
9741 i915_gem_track_fb(work
->old_fb_obj
, obj
,
9742 INTEL_FRONTBUFFER_PRIMARY(pipe
));
9744 intel_disable_fbc(dev
);
9745 intel_frontbuffer_flip_prepare(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
9746 mutex_unlock(&dev
->struct_mutex
);
9748 trace_i915_flip_request(intel_crtc
->plane
, obj
);
9753 intel_unpin_fb_obj(obj
);
9755 atomic_dec(&intel_crtc
->unpin_work_count
);
9756 crtc
->primary
->fb
= old_fb
;
9757 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
9758 drm_gem_object_unreference(&obj
->base
);
9759 mutex_unlock(&dev
->struct_mutex
);
9762 spin_lock_irq(&dev
->event_lock
);
9763 intel_crtc
->unpin_work
= NULL
;
9764 spin_unlock_irq(&dev
->event_lock
);
9766 drm_crtc_vblank_put(crtc
);
9772 intel_crtc_wait_for_pending_flips(crtc
);
9773 ret
= intel_pipe_set_base(crtc
, crtc
->x
, crtc
->y
, fb
);
9774 if (ret
== 0 && event
) {
9775 spin_lock_irq(&dev
->event_lock
);
9776 drm_send_vblank_event(dev
, pipe
, event
);
9777 spin_unlock_irq(&dev
->event_lock
);
9783 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
9784 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
9785 .load_lut
= intel_crtc_load_lut
,
9789 * intel_modeset_update_staged_output_state
9791 * Updates the staged output configuration state, e.g. after we've read out the
9794 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
9796 struct intel_crtc
*crtc
;
9797 struct intel_encoder
*encoder
;
9798 struct intel_connector
*connector
;
9800 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9802 connector
->new_encoder
=
9803 to_intel_encoder(connector
->base
.encoder
);
9806 for_each_intel_encoder(dev
, encoder
) {
9808 to_intel_crtc(encoder
->base
.crtc
);
9811 for_each_intel_crtc(dev
, crtc
) {
9812 crtc
->new_enabled
= crtc
->base
.enabled
;
9814 if (crtc
->new_enabled
)
9815 crtc
->new_config
= &crtc
->config
;
9817 crtc
->new_config
= NULL
;
9822 * intel_modeset_commit_output_state
9824 * This function copies the stage display pipe configuration to the real one.
9826 static void intel_modeset_commit_output_state(struct drm_device
*dev
)
9828 struct intel_crtc
*crtc
;
9829 struct intel_encoder
*encoder
;
9830 struct intel_connector
*connector
;
9832 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9834 connector
->base
.encoder
= &connector
->new_encoder
->base
;
9837 for_each_intel_encoder(dev
, encoder
) {
9838 encoder
->base
.crtc
= &encoder
->new_crtc
->base
;
9841 for_each_intel_crtc(dev
, crtc
) {
9842 crtc
->base
.enabled
= crtc
->new_enabled
;
9847 connected_sink_compute_bpp(struct intel_connector
*connector
,
9848 struct intel_crtc_config
*pipe_config
)
9850 int bpp
= pipe_config
->pipe_bpp
;
9852 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9853 connector
->base
.base
.id
,
9854 connector
->base
.name
);
9856 /* Don't use an invalid EDID bpc value */
9857 if (connector
->base
.display_info
.bpc
&&
9858 connector
->base
.display_info
.bpc
* 3 < bpp
) {
9859 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9860 bpp
, connector
->base
.display_info
.bpc
*3);
9861 pipe_config
->pipe_bpp
= connector
->base
.display_info
.bpc
*3;
9864 /* Clamp bpp to 8 on screens without EDID 1.4 */
9865 if (connector
->base
.display_info
.bpc
== 0 && bpp
> 24) {
9866 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9868 pipe_config
->pipe_bpp
= 24;
9873 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
9874 struct drm_framebuffer
*fb
,
9875 struct intel_crtc_config
*pipe_config
)
9877 struct drm_device
*dev
= crtc
->base
.dev
;
9878 struct intel_connector
*connector
;
9881 switch (fb
->pixel_format
) {
9883 bpp
= 8*3; /* since we go through a colormap */
9885 case DRM_FORMAT_XRGB1555
:
9886 case DRM_FORMAT_ARGB1555
:
9887 /* checked in intel_framebuffer_init already */
9888 if (WARN_ON(INTEL_INFO(dev
)->gen
> 3))
9890 case DRM_FORMAT_RGB565
:
9891 bpp
= 6*3; /* min is 18bpp */
9893 case DRM_FORMAT_XBGR8888
:
9894 case DRM_FORMAT_ABGR8888
:
9895 /* checked in intel_framebuffer_init already */
9896 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
9898 case DRM_FORMAT_XRGB8888
:
9899 case DRM_FORMAT_ARGB8888
:
9902 case DRM_FORMAT_XRGB2101010
:
9903 case DRM_FORMAT_ARGB2101010
:
9904 case DRM_FORMAT_XBGR2101010
:
9905 case DRM_FORMAT_ABGR2101010
:
9906 /* checked in intel_framebuffer_init already */
9907 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
9911 /* TODO: gen4+ supports 16 bpc floating point, too. */
9913 DRM_DEBUG_KMS("unsupported depth\n");
9917 pipe_config
->pipe_bpp
= bpp
;
9919 /* Clamp display bpp to EDID value */
9920 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9922 if (!connector
->new_encoder
||
9923 connector
->new_encoder
->new_crtc
!= crtc
)
9926 connected_sink_compute_bpp(connector
, pipe_config
);
9932 static void intel_dump_crtc_timings(const struct drm_display_mode
*mode
)
9934 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9935 "type: 0x%x flags: 0x%x\n",
9937 mode
->crtc_hdisplay
, mode
->crtc_hsync_start
,
9938 mode
->crtc_hsync_end
, mode
->crtc_htotal
,
9939 mode
->crtc_vdisplay
, mode
->crtc_vsync_start
,
9940 mode
->crtc_vsync_end
, mode
->crtc_vtotal
, mode
->type
, mode
->flags
);
9943 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
9944 struct intel_crtc_config
*pipe_config
,
9945 const char *context
)
9947 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc
->base
.base
.id
,
9948 context
, pipe_name(crtc
->pipe
));
9950 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config
->cpu_transcoder
));
9951 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9952 pipe_config
->pipe_bpp
, pipe_config
->dither
);
9953 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9954 pipe_config
->has_pch_encoder
,
9955 pipe_config
->fdi_lanes
,
9956 pipe_config
->fdi_m_n
.gmch_m
, pipe_config
->fdi_m_n
.gmch_n
,
9957 pipe_config
->fdi_m_n
.link_m
, pipe_config
->fdi_m_n
.link_n
,
9958 pipe_config
->fdi_m_n
.tu
);
9959 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9960 pipe_config
->has_dp_encoder
,
9961 pipe_config
->dp_m_n
.gmch_m
, pipe_config
->dp_m_n
.gmch_n
,
9962 pipe_config
->dp_m_n
.link_m
, pipe_config
->dp_m_n
.link_n
,
9963 pipe_config
->dp_m_n
.tu
);
9965 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
9966 pipe_config
->has_dp_encoder
,
9967 pipe_config
->dp_m2_n2
.gmch_m
,
9968 pipe_config
->dp_m2_n2
.gmch_n
,
9969 pipe_config
->dp_m2_n2
.link_m
,
9970 pipe_config
->dp_m2_n2
.link_n
,
9971 pipe_config
->dp_m2_n2
.tu
);
9973 DRM_DEBUG_KMS("requested mode:\n");
9974 drm_mode_debug_printmodeline(&pipe_config
->requested_mode
);
9975 DRM_DEBUG_KMS("adjusted mode:\n");
9976 drm_mode_debug_printmodeline(&pipe_config
->adjusted_mode
);
9977 intel_dump_crtc_timings(&pipe_config
->adjusted_mode
);
9978 DRM_DEBUG_KMS("port clock: %d\n", pipe_config
->port_clock
);
9979 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9980 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
9981 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9982 pipe_config
->gmch_pfit
.control
,
9983 pipe_config
->gmch_pfit
.pgm_ratios
,
9984 pipe_config
->gmch_pfit
.lvds_border_bits
);
9985 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9986 pipe_config
->pch_pfit
.pos
,
9987 pipe_config
->pch_pfit
.size
,
9988 pipe_config
->pch_pfit
.enabled
? "enabled" : "disabled");
9989 DRM_DEBUG_KMS("ips: %i\n", pipe_config
->ips_enabled
);
9990 DRM_DEBUG_KMS("double wide: %i\n", pipe_config
->double_wide
);
9993 static bool encoders_cloneable(const struct intel_encoder
*a
,
9994 const struct intel_encoder
*b
)
9996 /* masks could be asymmetric, so check both ways */
9997 return a
== b
|| (a
->cloneable
& (1 << b
->type
) &&
9998 b
->cloneable
& (1 << a
->type
));
10001 static bool check_single_encoder_cloning(struct intel_crtc
*crtc
,
10002 struct intel_encoder
*encoder
)
10004 struct drm_device
*dev
= crtc
->base
.dev
;
10005 struct intel_encoder
*source_encoder
;
10007 for_each_intel_encoder(dev
, source_encoder
) {
10008 if (source_encoder
->new_crtc
!= crtc
)
10011 if (!encoders_cloneable(encoder
, source_encoder
))
10018 static bool check_encoder_cloning(struct intel_crtc
*crtc
)
10020 struct drm_device
*dev
= crtc
->base
.dev
;
10021 struct intel_encoder
*encoder
;
10023 for_each_intel_encoder(dev
, encoder
) {
10024 if (encoder
->new_crtc
!= crtc
)
10027 if (!check_single_encoder_cloning(crtc
, encoder
))
10034 static struct intel_crtc_config
*
10035 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
10036 struct drm_framebuffer
*fb
,
10037 struct drm_display_mode
*mode
)
10039 struct drm_device
*dev
= crtc
->dev
;
10040 struct intel_encoder
*encoder
;
10041 struct intel_crtc_config
*pipe_config
;
10042 int plane_bpp
, ret
= -EINVAL
;
10045 if (!check_encoder_cloning(to_intel_crtc(crtc
))) {
10046 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10047 return ERR_PTR(-EINVAL
);
10050 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
10052 return ERR_PTR(-ENOMEM
);
10054 drm_mode_copy(&pipe_config
->adjusted_mode
, mode
);
10055 drm_mode_copy(&pipe_config
->requested_mode
, mode
);
10057 pipe_config
->cpu_transcoder
=
10058 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
10059 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
10062 * Sanitize sync polarity flags based on requested ones. If neither
10063 * positive or negative polarity is requested, treat this as meaning
10064 * negative polarity.
10066 if (!(pipe_config
->adjusted_mode
.flags
&
10067 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
10068 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
10070 if (!(pipe_config
->adjusted_mode
.flags
&
10071 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
10072 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
10074 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10075 * plane pixel format and any sink constraints into account. Returns the
10076 * source plane bpp so that dithering can be selected on mismatches
10077 * after encoders and crtc also have had their say. */
10078 plane_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
10084 * Determine the real pipe dimensions. Note that stereo modes can
10085 * increase the actual pipe size due to the frame doubling and
10086 * insertion of additional space for blanks between the frame. This
10087 * is stored in the crtc timings. We use the requested mode to do this
10088 * computation to clearly distinguish it from the adjusted mode, which
10089 * can be changed by the connectors in the below retry loop.
10091 drm_mode_set_crtcinfo(&pipe_config
->requested_mode
, CRTC_STEREO_DOUBLE
);
10092 pipe_config
->pipe_src_w
= pipe_config
->requested_mode
.crtc_hdisplay
;
10093 pipe_config
->pipe_src_h
= pipe_config
->requested_mode
.crtc_vdisplay
;
10096 /* Ensure the port clock defaults are reset when retrying. */
10097 pipe_config
->port_clock
= 0;
10098 pipe_config
->pixel_multiplier
= 1;
10100 /* Fill in default crtc timings, allow encoders to overwrite them. */
10101 drm_mode_set_crtcinfo(&pipe_config
->adjusted_mode
, CRTC_STEREO_DOUBLE
);
10103 /* Pass our mode to the connectors and the CRTC to give them a chance to
10104 * adjust it according to limitations or connector properties, and also
10105 * a chance to reject the mode entirely.
10107 for_each_intel_encoder(dev
, encoder
) {
10109 if (&encoder
->new_crtc
->base
!= crtc
)
10112 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
10113 DRM_DEBUG_KMS("Encoder config failure\n");
10118 /* Set default port clock if not overwritten by the encoder. Needs to be
10119 * done afterwards in case the encoder adjusts the mode. */
10120 if (!pipe_config
->port_clock
)
10121 pipe_config
->port_clock
= pipe_config
->adjusted_mode
.crtc_clock
10122 * pipe_config
->pixel_multiplier
;
10124 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
10126 DRM_DEBUG_KMS("CRTC fixup failed\n");
10130 if (ret
== RETRY
) {
10131 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
10136 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10138 goto encoder_retry
;
10141 pipe_config
->dither
= pipe_config
->pipe_bpp
!= plane_bpp
;
10142 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10143 plane_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
10145 return pipe_config
;
10147 kfree(pipe_config
);
10148 return ERR_PTR(ret
);
10151 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10152 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10154 intel_modeset_affected_pipes(struct drm_crtc
*crtc
, unsigned *modeset_pipes
,
10155 unsigned *prepare_pipes
, unsigned *disable_pipes
)
10157 struct intel_crtc
*intel_crtc
;
10158 struct drm_device
*dev
= crtc
->dev
;
10159 struct intel_encoder
*encoder
;
10160 struct intel_connector
*connector
;
10161 struct drm_crtc
*tmp_crtc
;
10163 *disable_pipes
= *modeset_pipes
= *prepare_pipes
= 0;
10165 /* Check which crtcs have changed outputs connected to them, these need
10166 * to be part of the prepare_pipes mask. We don't (yet) support global
10167 * modeset across multiple crtcs, so modeset_pipes will only have one
10168 * bit set at most. */
10169 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10171 if (connector
->base
.encoder
== &connector
->new_encoder
->base
)
10174 if (connector
->base
.encoder
) {
10175 tmp_crtc
= connector
->base
.encoder
->crtc
;
10177 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
10180 if (connector
->new_encoder
)
10182 1 << connector
->new_encoder
->new_crtc
->pipe
;
10185 for_each_intel_encoder(dev
, encoder
) {
10186 if (encoder
->base
.crtc
== &encoder
->new_crtc
->base
)
10189 if (encoder
->base
.crtc
) {
10190 tmp_crtc
= encoder
->base
.crtc
;
10192 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
10195 if (encoder
->new_crtc
)
10196 *prepare_pipes
|= 1 << encoder
->new_crtc
->pipe
;
10199 /* Check for pipes that will be enabled/disabled ... */
10200 for_each_intel_crtc(dev
, intel_crtc
) {
10201 if (intel_crtc
->base
.enabled
== intel_crtc
->new_enabled
)
10204 if (!intel_crtc
->new_enabled
)
10205 *disable_pipes
|= 1 << intel_crtc
->pipe
;
10207 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
10211 /* set_mode is also used to update properties on life display pipes. */
10212 intel_crtc
= to_intel_crtc(crtc
);
10213 if (intel_crtc
->new_enabled
)
10214 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
10217 * For simplicity do a full modeset on any pipe where the output routing
10218 * changed. We could be more clever, but that would require us to be
10219 * more careful with calling the relevant encoder->mode_set functions.
10221 if (*prepare_pipes
)
10222 *modeset_pipes
= *prepare_pipes
;
10224 /* ... and mask these out. */
10225 *modeset_pipes
&= ~(*disable_pipes
);
10226 *prepare_pipes
&= ~(*disable_pipes
);
10229 * HACK: We don't (yet) fully support global modesets. intel_set_config
10230 * obies this rule, but the modeset restore mode of
10231 * intel_modeset_setup_hw_state does not.
10233 *modeset_pipes
&= 1 << intel_crtc
->pipe
;
10234 *prepare_pipes
&= 1 << intel_crtc
->pipe
;
10236 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10237 *modeset_pipes
, *prepare_pipes
, *disable_pipes
);
10240 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
10242 struct drm_encoder
*encoder
;
10243 struct drm_device
*dev
= crtc
->dev
;
10245 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
10246 if (encoder
->crtc
== crtc
)
10253 intel_modeset_update_state(struct drm_device
*dev
, unsigned prepare_pipes
)
10255 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10256 struct intel_encoder
*intel_encoder
;
10257 struct intel_crtc
*intel_crtc
;
10258 struct drm_connector
*connector
;
10260 intel_shared_dpll_commit(dev_priv
);
10262 for_each_intel_encoder(dev
, intel_encoder
) {
10263 if (!intel_encoder
->base
.crtc
)
10266 intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
10268 if (prepare_pipes
& (1 << intel_crtc
->pipe
))
10269 intel_encoder
->connectors_active
= false;
10272 intel_modeset_commit_output_state(dev
);
10274 /* Double check state. */
10275 for_each_intel_crtc(dev
, intel_crtc
) {
10276 WARN_ON(intel_crtc
->base
.enabled
!= intel_crtc_in_use(&intel_crtc
->base
));
10277 WARN_ON(intel_crtc
->new_config
&&
10278 intel_crtc
->new_config
!= &intel_crtc
->config
);
10279 WARN_ON(intel_crtc
->base
.enabled
!= !!intel_crtc
->new_config
);
10282 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
10283 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
10286 intel_crtc
= to_intel_crtc(connector
->encoder
->crtc
);
10288 if (prepare_pipes
& (1 << intel_crtc
->pipe
)) {
10289 struct drm_property
*dpms_property
=
10290 dev
->mode_config
.dpms_property
;
10292 connector
->dpms
= DRM_MODE_DPMS_ON
;
10293 drm_object_property_set_value(&connector
->base
,
10297 intel_encoder
= to_intel_encoder(connector
->encoder
);
10298 intel_encoder
->connectors_active
= true;
10304 static bool intel_fuzzy_clock_check(int clock1
, int clock2
)
10308 if (clock1
== clock2
)
10311 if (!clock1
|| !clock2
)
10314 diff
= abs(clock1
- clock2
);
10316 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
10322 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10323 list_for_each_entry((intel_crtc), \
10324 &(dev)->mode_config.crtc_list, \
10326 if (mask & (1 <<(intel_crtc)->pipe))
10329 intel_pipe_config_compare(struct drm_device
*dev
,
10330 struct intel_crtc_config
*current_config
,
10331 struct intel_crtc_config
*pipe_config
)
10333 #define PIPE_CONF_CHECK_X(name) \
10334 if (current_config->name != pipe_config->name) { \
10335 DRM_ERROR("mismatch in " #name " " \
10336 "(expected 0x%08x, found 0x%08x)\n", \
10337 current_config->name, \
10338 pipe_config->name); \
10342 #define PIPE_CONF_CHECK_I(name) \
10343 if (current_config->name != pipe_config->name) { \
10344 DRM_ERROR("mismatch in " #name " " \
10345 "(expected %i, found %i)\n", \
10346 current_config->name, \
10347 pipe_config->name); \
10351 /* This is required for BDW+ where there is only one set of registers for
10352 * switching between high and low RR.
10353 * This macro can be used whenever a comparison has to be made between one
10354 * hw state and multiple sw state variables.
10356 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10357 if ((current_config->name != pipe_config->name) && \
10358 (current_config->alt_name != pipe_config->name)) { \
10359 DRM_ERROR("mismatch in " #name " " \
10360 "(expected %i or %i, found %i)\n", \
10361 current_config->name, \
10362 current_config->alt_name, \
10363 pipe_config->name); \
10367 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10368 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10369 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10370 "(expected %i, found %i)\n", \
10371 current_config->name & (mask), \
10372 pipe_config->name & (mask)); \
10376 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10377 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10378 DRM_ERROR("mismatch in " #name " " \
10379 "(expected %i, found %i)\n", \
10380 current_config->name, \
10381 pipe_config->name); \
10385 #define PIPE_CONF_QUIRK(quirk) \
10386 ((current_config->quirks | pipe_config->quirks) & (quirk))
10388 PIPE_CONF_CHECK_I(cpu_transcoder
);
10390 PIPE_CONF_CHECK_I(has_pch_encoder
);
10391 PIPE_CONF_CHECK_I(fdi_lanes
);
10392 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_m
);
10393 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_n
);
10394 PIPE_CONF_CHECK_I(fdi_m_n
.link_m
);
10395 PIPE_CONF_CHECK_I(fdi_m_n
.link_n
);
10396 PIPE_CONF_CHECK_I(fdi_m_n
.tu
);
10398 PIPE_CONF_CHECK_I(has_dp_encoder
);
10400 if (INTEL_INFO(dev
)->gen
< 8) {
10401 PIPE_CONF_CHECK_I(dp_m_n
.gmch_m
);
10402 PIPE_CONF_CHECK_I(dp_m_n
.gmch_n
);
10403 PIPE_CONF_CHECK_I(dp_m_n
.link_m
);
10404 PIPE_CONF_CHECK_I(dp_m_n
.link_n
);
10405 PIPE_CONF_CHECK_I(dp_m_n
.tu
);
10407 if (current_config
->has_drrs
) {
10408 PIPE_CONF_CHECK_I(dp_m2_n2
.gmch_m
);
10409 PIPE_CONF_CHECK_I(dp_m2_n2
.gmch_n
);
10410 PIPE_CONF_CHECK_I(dp_m2_n2
.link_m
);
10411 PIPE_CONF_CHECK_I(dp_m2_n2
.link_n
);
10412 PIPE_CONF_CHECK_I(dp_m2_n2
.tu
);
10415 PIPE_CONF_CHECK_I_ALT(dp_m_n
.gmch_m
, dp_m2_n2
.gmch_m
);
10416 PIPE_CONF_CHECK_I_ALT(dp_m_n
.gmch_n
, dp_m2_n2
.gmch_n
);
10417 PIPE_CONF_CHECK_I_ALT(dp_m_n
.link_m
, dp_m2_n2
.link_m
);
10418 PIPE_CONF_CHECK_I_ALT(dp_m_n
.link_n
, dp_m2_n2
.link_n
);
10419 PIPE_CONF_CHECK_I_ALT(dp_m_n
.tu
, dp_m2_n2
.tu
);
10422 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hdisplay
);
10423 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_htotal
);
10424 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_start
);
10425 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_end
);
10426 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_start
);
10427 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_end
);
10429 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vdisplay
);
10430 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vtotal
);
10431 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_start
);
10432 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_end
);
10433 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_start
);
10434 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_end
);
10436 PIPE_CONF_CHECK_I(pixel_multiplier
);
10437 PIPE_CONF_CHECK_I(has_hdmi_sink
);
10438 if ((INTEL_INFO(dev
)->gen
< 8 && !IS_HASWELL(dev
)) ||
10439 IS_VALLEYVIEW(dev
))
10440 PIPE_CONF_CHECK_I(limited_color_range
);
10442 PIPE_CONF_CHECK_I(has_audio
);
10444 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10445 DRM_MODE_FLAG_INTERLACE
);
10447 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
10448 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10449 DRM_MODE_FLAG_PHSYNC
);
10450 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10451 DRM_MODE_FLAG_NHSYNC
);
10452 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10453 DRM_MODE_FLAG_PVSYNC
);
10454 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10455 DRM_MODE_FLAG_NVSYNC
);
10458 PIPE_CONF_CHECK_I(pipe_src_w
);
10459 PIPE_CONF_CHECK_I(pipe_src_h
);
10462 * FIXME: BIOS likes to set up a cloned config with lvds+external
10463 * screen. Since we don't yet re-compute the pipe config when moving
10464 * just the lvds port away to another pipe the sw tracking won't match.
10466 * Proper atomic modesets with recomputed global state will fix this.
10467 * Until then just don't check gmch state for inherited modes.
10469 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE
)) {
10470 PIPE_CONF_CHECK_I(gmch_pfit
.control
);
10471 /* pfit ratios are autocomputed by the hw on gen4+ */
10472 if (INTEL_INFO(dev
)->gen
< 4)
10473 PIPE_CONF_CHECK_I(gmch_pfit
.pgm_ratios
);
10474 PIPE_CONF_CHECK_I(gmch_pfit
.lvds_border_bits
);
10477 PIPE_CONF_CHECK_I(pch_pfit
.enabled
);
10478 if (current_config
->pch_pfit
.enabled
) {
10479 PIPE_CONF_CHECK_I(pch_pfit
.pos
);
10480 PIPE_CONF_CHECK_I(pch_pfit
.size
);
10483 /* BDW+ don't expose a synchronous way to read the state */
10484 if (IS_HASWELL(dev
))
10485 PIPE_CONF_CHECK_I(ips_enabled
);
10487 PIPE_CONF_CHECK_I(double_wide
);
10489 PIPE_CONF_CHECK_X(ddi_pll_sel
);
10491 PIPE_CONF_CHECK_I(shared_dpll
);
10492 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
10493 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
10494 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
10495 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
10496 PIPE_CONF_CHECK_X(dpll_hw_state
.wrpll
);
10498 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5)
10499 PIPE_CONF_CHECK_I(pipe_bpp
);
10501 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode
.crtc_clock
);
10502 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
10504 #undef PIPE_CONF_CHECK_X
10505 #undef PIPE_CONF_CHECK_I
10506 #undef PIPE_CONF_CHECK_I_ALT
10507 #undef PIPE_CONF_CHECK_FLAGS
10508 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10509 #undef PIPE_CONF_QUIRK
10515 check_connector_state(struct drm_device
*dev
)
10517 struct intel_connector
*connector
;
10519 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10521 /* This also checks the encoder/connector hw state with the
10522 * ->get_hw_state callbacks. */
10523 intel_connector_check_state(connector
);
10525 WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
10526 "connector's staged encoder doesn't match current encoder\n");
10531 check_encoder_state(struct drm_device
*dev
)
10533 struct intel_encoder
*encoder
;
10534 struct intel_connector
*connector
;
10536 for_each_intel_encoder(dev
, encoder
) {
10537 bool enabled
= false;
10538 bool active
= false;
10539 enum pipe pipe
, tracked_pipe
;
10541 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10542 encoder
->base
.base
.id
,
10543 encoder
->base
.name
);
10545 WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
10546 "encoder's stage crtc doesn't match current crtc\n");
10547 WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
10548 "encoder's active_connectors set, but no crtc\n");
10550 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10552 if (connector
->base
.encoder
!= &encoder
->base
)
10555 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
10559 * for MST connectors if we unplug the connector is gone
10560 * away but the encoder is still connected to a crtc
10561 * until a modeset happens in response to the hotplug.
10563 if (!enabled
&& encoder
->base
.encoder_type
== DRM_MODE_ENCODER_DPMST
)
10566 WARN(!!encoder
->base
.crtc
!= enabled
,
10567 "encoder's enabled state mismatch "
10568 "(expected %i, found %i)\n",
10569 !!encoder
->base
.crtc
, enabled
);
10570 WARN(active
&& !encoder
->base
.crtc
,
10571 "active encoder with no crtc\n");
10573 WARN(encoder
->connectors_active
!= active
,
10574 "encoder's computed active state doesn't match tracked active state "
10575 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
10577 active
= encoder
->get_hw_state(encoder
, &pipe
);
10578 WARN(active
!= encoder
->connectors_active
,
10579 "encoder's hw state doesn't match sw tracking "
10580 "(expected %i, found %i)\n",
10581 encoder
->connectors_active
, active
);
10583 if (!encoder
->base
.crtc
)
10586 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
10587 WARN(active
&& pipe
!= tracked_pipe
,
10588 "active encoder's pipe doesn't match"
10589 "(expected %i, found %i)\n",
10590 tracked_pipe
, pipe
);
10596 check_crtc_state(struct drm_device
*dev
)
10598 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10599 struct intel_crtc
*crtc
;
10600 struct intel_encoder
*encoder
;
10601 struct intel_crtc_config pipe_config
;
10603 for_each_intel_crtc(dev
, crtc
) {
10604 bool enabled
= false;
10605 bool active
= false;
10607 memset(&pipe_config
, 0, sizeof(pipe_config
));
10609 DRM_DEBUG_KMS("[CRTC:%d]\n",
10610 crtc
->base
.base
.id
);
10612 WARN(crtc
->active
&& !crtc
->base
.enabled
,
10613 "active crtc, but not enabled in sw tracking\n");
10615 for_each_intel_encoder(dev
, encoder
) {
10616 if (encoder
->base
.crtc
!= &crtc
->base
)
10619 if (encoder
->connectors_active
)
10623 WARN(active
!= crtc
->active
,
10624 "crtc's computed active state doesn't match tracked active state "
10625 "(expected %i, found %i)\n", active
, crtc
->active
);
10626 WARN(enabled
!= crtc
->base
.enabled
,
10627 "crtc's computed enabled state doesn't match tracked enabled state "
10628 "(expected %i, found %i)\n", enabled
, crtc
->base
.enabled
);
10630 active
= dev_priv
->display
.get_pipe_config(crtc
,
10633 /* hw state is inconsistent with the pipe quirk */
10634 if ((crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
10635 (crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
10636 active
= crtc
->active
;
10638 for_each_intel_encoder(dev
, encoder
) {
10640 if (encoder
->base
.crtc
!= &crtc
->base
)
10642 if (encoder
->get_hw_state(encoder
, &pipe
))
10643 encoder
->get_config(encoder
, &pipe_config
);
10646 WARN(crtc
->active
!= active
,
10647 "crtc active state doesn't match with hw state "
10648 "(expected %i, found %i)\n", crtc
->active
, active
);
10651 !intel_pipe_config_compare(dev
, &crtc
->config
, &pipe_config
)) {
10652 WARN(1, "pipe state doesn't match!\n");
10653 intel_dump_pipe_config(crtc
, &pipe_config
,
10655 intel_dump_pipe_config(crtc
, &crtc
->config
,
10662 check_shared_dpll_state(struct drm_device
*dev
)
10664 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10665 struct intel_crtc
*crtc
;
10666 struct intel_dpll_hw_state dpll_hw_state
;
10669 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
10670 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
10671 int enabled_crtcs
= 0, active_crtcs
= 0;
10674 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
10676 DRM_DEBUG_KMS("%s\n", pll
->name
);
10678 active
= pll
->get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
10680 WARN(pll
->active
> hweight32(pll
->config
.crtc_mask
),
10681 "more active pll users than references: %i vs %i\n",
10682 pll
->active
, hweight32(pll
->config
.crtc_mask
));
10683 WARN(pll
->active
&& !pll
->on
,
10684 "pll in active use but not on in sw tracking\n");
10685 WARN(pll
->on
&& !pll
->active
,
10686 "pll in on but not on in use in sw tracking\n");
10687 WARN(pll
->on
!= active
,
10688 "pll on state mismatch (expected %i, found %i)\n",
10691 for_each_intel_crtc(dev
, crtc
) {
10692 if (crtc
->base
.enabled
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
10694 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
10697 WARN(pll
->active
!= active_crtcs
,
10698 "pll active crtcs mismatch (expected %i, found %i)\n",
10699 pll
->active
, active_crtcs
);
10700 WARN(hweight32(pll
->config
.crtc_mask
) != enabled_crtcs
,
10701 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10702 hweight32(pll
->config
.crtc_mask
), enabled_crtcs
);
10704 WARN(pll
->on
&& memcmp(&pll
->config
.hw_state
, &dpll_hw_state
,
10705 sizeof(dpll_hw_state
)),
10706 "pll hw state mismatch\n");
10711 intel_modeset_check_state(struct drm_device
*dev
)
10713 check_connector_state(dev
);
10714 check_encoder_state(dev
);
10715 check_crtc_state(dev
);
10716 check_shared_dpll_state(dev
);
10719 void ironlake_check_encoder_dotclock(const struct intel_crtc_config
*pipe_config
,
10723 * FDI already provided one idea for the dotclock.
10724 * Yell if the encoder disagrees.
10726 WARN(!intel_fuzzy_clock_check(pipe_config
->adjusted_mode
.crtc_clock
, dotclock
),
10727 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10728 pipe_config
->adjusted_mode
.crtc_clock
, dotclock
);
10731 static void update_scanline_offset(struct intel_crtc
*crtc
)
10733 struct drm_device
*dev
= crtc
->base
.dev
;
10736 * The scanline counter increments at the leading edge of hsync.
10738 * On most platforms it starts counting from vtotal-1 on the
10739 * first active line. That means the scanline counter value is
10740 * always one less than what we would expect. Ie. just after
10741 * start of vblank, which also occurs at start of hsync (on the
10742 * last active line), the scanline counter will read vblank_start-1.
10744 * On gen2 the scanline counter starts counting from 1 instead
10745 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10746 * to keep the value positive), instead of adding one.
10748 * On HSW+ the behaviour of the scanline counter depends on the output
10749 * type. For DP ports it behaves like most other platforms, but on HDMI
10750 * there's an extra 1 line difference. So we need to add two instead of
10751 * one to the value.
10753 if (IS_GEN2(dev
)) {
10754 const struct drm_display_mode
*mode
= &crtc
->config
.adjusted_mode
;
10757 vtotal
= mode
->crtc_vtotal
;
10758 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
10761 crtc
->scanline_offset
= vtotal
- 1;
10762 } else if (HAS_DDI(dev
) &&
10763 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
)) {
10764 crtc
->scanline_offset
= 2;
10766 crtc
->scanline_offset
= 1;
10769 static int __intel_set_mode(struct drm_crtc
*crtc
,
10770 struct drm_display_mode
*mode
,
10771 int x
, int y
, struct drm_framebuffer
*fb
)
10773 struct drm_device
*dev
= crtc
->dev
;
10774 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10775 struct drm_display_mode
*saved_mode
;
10776 struct intel_crtc_config
*pipe_config
= NULL
;
10777 struct intel_crtc
*intel_crtc
;
10778 unsigned disable_pipes
, prepare_pipes
, modeset_pipes
;
10781 saved_mode
= kmalloc(sizeof(*saved_mode
), GFP_KERNEL
);
10785 intel_modeset_affected_pipes(crtc
, &modeset_pipes
,
10786 &prepare_pipes
, &disable_pipes
);
10788 *saved_mode
= crtc
->mode
;
10790 /* Hack: Because we don't (yet) support global modeset on multiple
10791 * crtcs, we don't keep track of the new mode for more than one crtc.
10792 * Hence simply check whether any bit is set in modeset_pipes in all the
10793 * pieces of code that are not yet converted to deal with mutliple crtcs
10794 * changing their mode at the same time. */
10795 if (modeset_pipes
) {
10796 pipe_config
= intel_modeset_pipe_config(crtc
, fb
, mode
);
10797 if (IS_ERR(pipe_config
)) {
10798 ret
= PTR_ERR(pipe_config
);
10799 pipe_config
= NULL
;
10803 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,
10805 to_intel_crtc(crtc
)->new_config
= pipe_config
;
10809 * See if the config requires any additional preparation, e.g.
10810 * to adjust global state with pipes off. We need to do this
10811 * here so we can get the modeset_pipe updated config for the new
10812 * mode set on this crtc. For other crtcs we need to use the
10813 * adjusted_mode bits in the crtc directly.
10815 if (IS_VALLEYVIEW(dev
)) {
10816 valleyview_modeset_global_pipes(dev
, &prepare_pipes
);
10818 /* may have added more to prepare_pipes than we should */
10819 prepare_pipes
&= ~disable_pipes
;
10822 if (dev_priv
->display
.crtc_compute_clock
) {
10823 unsigned clear_pipes
= modeset_pipes
| disable_pipes
;
10825 ret
= intel_shared_dpll_start_config(dev_priv
, clear_pipes
);
10829 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
10830 ret
= dev_priv
->display
.crtc_compute_clock(intel_crtc
);
10832 intel_shared_dpll_abort_config(dev_priv
);
10838 for_each_intel_crtc_masked(dev
, disable_pipes
, intel_crtc
)
10839 intel_crtc_disable(&intel_crtc
->base
);
10841 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
10842 if (intel_crtc
->base
.enabled
)
10843 dev_priv
->display
.crtc_disable(&intel_crtc
->base
);
10846 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10847 * to set it here already despite that we pass it down the callchain.
10849 if (modeset_pipes
) {
10850 crtc
->mode
= *mode
;
10851 /* mode_set/enable/disable functions rely on a correct pipe
10853 to_intel_crtc(crtc
)->config
= *pipe_config
;
10854 to_intel_crtc(crtc
)->new_config
= &to_intel_crtc(crtc
)->config
;
10857 * Calculate and store various constants which
10858 * are later needed by vblank and swap-completion
10859 * timestamping. They are derived from true hwmode.
10861 drm_calc_timestamping_constants(crtc
,
10862 &pipe_config
->adjusted_mode
);
10865 /* Only after disabling all output pipelines that will be changed can we
10866 * update the the output configuration. */
10867 intel_modeset_update_state(dev
, prepare_pipes
);
10869 if (dev_priv
->display
.modeset_global_resources
)
10870 dev_priv
->display
.modeset_global_resources(dev
);
10872 /* Set up the DPLL and any encoders state that needs to adjust or depend
10875 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
10876 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
10877 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(old_fb
);
10878 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
10880 mutex_lock(&dev
->struct_mutex
);
10881 ret
= intel_pin_and_fence_fb_obj(crtc
->primary
, fb
, NULL
);
10883 DRM_ERROR("pin & fence failed\n");
10884 mutex_unlock(&dev
->struct_mutex
);
10888 intel_unpin_fb_obj(old_obj
);
10889 i915_gem_track_fb(old_obj
, obj
,
10890 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
));
10891 mutex_unlock(&dev
->struct_mutex
);
10893 crtc
->primary
->fb
= fb
;
10898 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10899 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
10900 update_scanline_offset(intel_crtc
);
10902 dev_priv
->display
.crtc_enable(&intel_crtc
->base
);
10905 /* FIXME: add subpixel order */
10907 if (ret
&& crtc
->enabled
)
10908 crtc
->mode
= *saved_mode
;
10911 kfree(pipe_config
);
10916 static int intel_set_mode(struct drm_crtc
*crtc
,
10917 struct drm_display_mode
*mode
,
10918 int x
, int y
, struct drm_framebuffer
*fb
)
10922 ret
= __intel_set_mode(crtc
, mode
, x
, y
, fb
);
10925 intel_modeset_check_state(crtc
->dev
);
10930 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
10932 intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
, crtc
->primary
->fb
);
10935 #undef for_each_intel_crtc_masked
10937 static void intel_set_config_free(struct intel_set_config
*config
)
10942 kfree(config
->save_connector_encoders
);
10943 kfree(config
->save_encoder_crtcs
);
10944 kfree(config
->save_crtc_enabled
);
10948 static int intel_set_config_save_state(struct drm_device
*dev
,
10949 struct intel_set_config
*config
)
10951 struct drm_crtc
*crtc
;
10952 struct drm_encoder
*encoder
;
10953 struct drm_connector
*connector
;
10956 config
->save_crtc_enabled
=
10957 kcalloc(dev
->mode_config
.num_crtc
,
10958 sizeof(bool), GFP_KERNEL
);
10959 if (!config
->save_crtc_enabled
)
10962 config
->save_encoder_crtcs
=
10963 kcalloc(dev
->mode_config
.num_encoder
,
10964 sizeof(struct drm_crtc
*), GFP_KERNEL
);
10965 if (!config
->save_encoder_crtcs
)
10968 config
->save_connector_encoders
=
10969 kcalloc(dev
->mode_config
.num_connector
,
10970 sizeof(struct drm_encoder
*), GFP_KERNEL
);
10971 if (!config
->save_connector_encoders
)
10974 /* Copy data. Note that driver private data is not affected.
10975 * Should anything bad happen only the expected state is
10976 * restored, not the drivers personal bookkeeping.
10979 for_each_crtc(dev
, crtc
) {
10980 config
->save_crtc_enabled
[count
++] = crtc
->enabled
;
10984 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
10985 config
->save_encoder_crtcs
[count
++] = encoder
->crtc
;
10989 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
10990 config
->save_connector_encoders
[count
++] = connector
->encoder
;
10996 static void intel_set_config_restore_state(struct drm_device
*dev
,
10997 struct intel_set_config
*config
)
10999 struct intel_crtc
*crtc
;
11000 struct intel_encoder
*encoder
;
11001 struct intel_connector
*connector
;
11005 for_each_intel_crtc(dev
, crtc
) {
11006 crtc
->new_enabled
= config
->save_crtc_enabled
[count
++];
11008 if (crtc
->new_enabled
)
11009 crtc
->new_config
= &crtc
->config
;
11011 crtc
->new_config
= NULL
;
11015 for_each_intel_encoder(dev
, encoder
) {
11016 encoder
->new_crtc
=
11017 to_intel_crtc(config
->save_encoder_crtcs
[count
++]);
11021 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
11022 connector
->new_encoder
=
11023 to_intel_encoder(config
->save_connector_encoders
[count
++]);
11028 is_crtc_connector_off(struct drm_mode_set
*set
)
11032 if (set
->num_connectors
== 0)
11035 if (WARN_ON(set
->connectors
== NULL
))
11038 for (i
= 0; i
< set
->num_connectors
; i
++)
11039 if (set
->connectors
[i
]->encoder
&&
11040 set
->connectors
[i
]->encoder
->crtc
== set
->crtc
&&
11041 set
->connectors
[i
]->dpms
!= DRM_MODE_DPMS_ON
)
11048 intel_set_config_compute_mode_changes(struct drm_mode_set
*set
,
11049 struct intel_set_config
*config
)
11052 /* We should be able to check here if the fb has the same properties
11053 * and then just flip_or_move it */
11054 if (is_crtc_connector_off(set
)) {
11055 config
->mode_changed
= true;
11056 } else if (set
->crtc
->primary
->fb
!= set
->fb
) {
11058 * If we have no fb, we can only flip as long as the crtc is
11059 * active, otherwise we need a full mode set. The crtc may
11060 * be active if we've only disabled the primary plane, or
11061 * in fastboot situations.
11063 if (set
->crtc
->primary
->fb
== NULL
) {
11064 struct intel_crtc
*intel_crtc
=
11065 to_intel_crtc(set
->crtc
);
11067 if (intel_crtc
->active
) {
11068 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11069 config
->fb_changed
= true;
11071 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11072 config
->mode_changed
= true;
11074 } else if (set
->fb
== NULL
) {
11075 config
->mode_changed
= true;
11076 } else if (set
->fb
->pixel_format
!=
11077 set
->crtc
->primary
->fb
->pixel_format
) {
11078 config
->mode_changed
= true;
11080 config
->fb_changed
= true;
11084 if (set
->fb
&& (set
->x
!= set
->crtc
->x
|| set
->y
!= set
->crtc
->y
))
11085 config
->fb_changed
= true;
11087 if (set
->mode
&& !drm_mode_equal(set
->mode
, &set
->crtc
->mode
)) {
11088 DRM_DEBUG_KMS("modes are different, full mode set\n");
11089 drm_mode_debug_printmodeline(&set
->crtc
->mode
);
11090 drm_mode_debug_printmodeline(set
->mode
);
11091 config
->mode_changed
= true;
11094 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11095 set
->crtc
->base
.id
, config
->mode_changed
, config
->fb_changed
);
11099 intel_modeset_stage_output_state(struct drm_device
*dev
,
11100 struct drm_mode_set
*set
,
11101 struct intel_set_config
*config
)
11103 struct intel_connector
*connector
;
11104 struct intel_encoder
*encoder
;
11105 struct intel_crtc
*crtc
;
11108 /* The upper layers ensure that we either disable a crtc or have a list
11109 * of connectors. For paranoia, double-check this. */
11110 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
11111 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
11113 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11115 /* Otherwise traverse passed in connector list and get encoders
11117 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
11118 if (set
->connectors
[ro
] == &connector
->base
) {
11119 connector
->new_encoder
= intel_find_encoder(connector
, to_intel_crtc(set
->crtc
)->pipe
);
11124 /* If we disable the crtc, disable all its connectors. Also, if
11125 * the connector is on the changing crtc but not on the new
11126 * connector list, disable it. */
11127 if ((!set
->fb
|| ro
== set
->num_connectors
) &&
11128 connector
->base
.encoder
&&
11129 connector
->base
.encoder
->crtc
== set
->crtc
) {
11130 connector
->new_encoder
= NULL
;
11132 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11133 connector
->base
.base
.id
,
11134 connector
->base
.name
);
11138 if (&connector
->new_encoder
->base
!= connector
->base
.encoder
) {
11139 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11140 config
->mode_changed
= true;
11143 /* connector->new_encoder is now updated for all connectors. */
11145 /* Update crtc of enabled connectors. */
11146 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11148 struct drm_crtc
*new_crtc
;
11150 if (!connector
->new_encoder
)
11153 new_crtc
= connector
->new_encoder
->base
.crtc
;
11155 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
11156 if (set
->connectors
[ro
] == &connector
->base
)
11157 new_crtc
= set
->crtc
;
11160 /* Make sure the new CRTC will work with the encoder */
11161 if (!drm_encoder_crtc_ok(&connector
->new_encoder
->base
,
11165 connector
->new_encoder
->new_crtc
= to_intel_crtc(new_crtc
);
11167 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11168 connector
->base
.base
.id
,
11169 connector
->base
.name
,
11170 new_crtc
->base
.id
);
11173 /* Check for any encoders that needs to be disabled. */
11174 for_each_intel_encoder(dev
, encoder
) {
11175 int num_connectors
= 0;
11176 list_for_each_entry(connector
,
11177 &dev
->mode_config
.connector_list
,
11179 if (connector
->new_encoder
== encoder
) {
11180 WARN_ON(!connector
->new_encoder
->new_crtc
);
11185 if (num_connectors
== 0)
11186 encoder
->new_crtc
= NULL
;
11187 else if (num_connectors
> 1)
11190 /* Only now check for crtc changes so we don't miss encoders
11191 * that will be disabled. */
11192 if (&encoder
->new_crtc
->base
!= encoder
->base
.crtc
) {
11193 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11194 config
->mode_changed
= true;
11197 /* Now we've also updated encoder->new_crtc for all encoders. */
11198 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11200 if (connector
->new_encoder
)
11201 if (connector
->new_encoder
!= connector
->encoder
)
11202 connector
->encoder
= connector
->new_encoder
;
11204 for_each_intel_crtc(dev
, crtc
) {
11205 crtc
->new_enabled
= false;
11207 for_each_intel_encoder(dev
, encoder
) {
11208 if (encoder
->new_crtc
== crtc
) {
11209 crtc
->new_enabled
= true;
11214 if (crtc
->new_enabled
!= crtc
->base
.enabled
) {
11215 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11216 crtc
->new_enabled
? "en" : "dis");
11217 config
->mode_changed
= true;
11220 if (crtc
->new_enabled
)
11221 crtc
->new_config
= &crtc
->config
;
11223 crtc
->new_config
= NULL
;
11229 static void disable_crtc_nofb(struct intel_crtc
*crtc
)
11231 struct drm_device
*dev
= crtc
->base
.dev
;
11232 struct intel_encoder
*encoder
;
11233 struct intel_connector
*connector
;
11235 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11236 pipe_name(crtc
->pipe
));
11238 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
11239 if (connector
->new_encoder
&&
11240 connector
->new_encoder
->new_crtc
== crtc
)
11241 connector
->new_encoder
= NULL
;
11244 for_each_intel_encoder(dev
, encoder
) {
11245 if (encoder
->new_crtc
== crtc
)
11246 encoder
->new_crtc
= NULL
;
11249 crtc
->new_enabled
= false;
11250 crtc
->new_config
= NULL
;
11253 static int intel_crtc_set_config(struct drm_mode_set
*set
)
11255 struct drm_device
*dev
;
11256 struct drm_mode_set save_set
;
11257 struct intel_set_config
*config
;
11261 BUG_ON(!set
->crtc
);
11262 BUG_ON(!set
->crtc
->helper_private
);
11264 /* Enforce sane interface api - has been abused by the fb helper. */
11265 BUG_ON(!set
->mode
&& set
->fb
);
11266 BUG_ON(set
->fb
&& set
->num_connectors
== 0);
11269 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11270 set
->crtc
->base
.id
, set
->fb
->base
.id
,
11271 (int)set
->num_connectors
, set
->x
, set
->y
);
11273 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
11276 dev
= set
->crtc
->dev
;
11279 config
= kzalloc(sizeof(*config
), GFP_KERNEL
);
11283 ret
= intel_set_config_save_state(dev
, config
);
11287 save_set
.crtc
= set
->crtc
;
11288 save_set
.mode
= &set
->crtc
->mode
;
11289 save_set
.x
= set
->crtc
->x
;
11290 save_set
.y
= set
->crtc
->y
;
11291 save_set
.fb
= set
->crtc
->primary
->fb
;
11293 /* Compute whether we need a full modeset, only an fb base update or no
11294 * change at all. In the future we might also check whether only the
11295 * mode changed, e.g. for LVDS where we only change the panel fitter in
11297 intel_set_config_compute_mode_changes(set
, config
);
11299 ret
= intel_modeset_stage_output_state(dev
, set
, config
);
11303 if (config
->mode_changed
) {
11304 ret
= intel_set_mode(set
->crtc
, set
->mode
,
11305 set
->x
, set
->y
, set
->fb
);
11306 } else if (config
->fb_changed
) {
11307 struct intel_crtc
*intel_crtc
= to_intel_crtc(set
->crtc
);
11309 intel_crtc_wait_for_pending_flips(set
->crtc
);
11311 ret
= intel_pipe_set_base(set
->crtc
,
11312 set
->x
, set
->y
, set
->fb
);
11315 * We need to make sure the primary plane is re-enabled if it
11316 * has previously been turned off.
11318 if (!intel_crtc
->primary_enabled
&& ret
== 0) {
11319 WARN_ON(!intel_crtc
->active
);
11320 intel_enable_primary_hw_plane(set
->crtc
->primary
, set
->crtc
);
11324 * In the fastboot case this may be our only check of the
11325 * state after boot. It would be better to only do it on
11326 * the first update, but we don't have a nice way of doing that
11327 * (and really, set_config isn't used much for high freq page
11328 * flipping, so increasing its cost here shouldn't be a big
11331 if (i915
.fastboot
&& ret
== 0)
11332 intel_modeset_check_state(set
->crtc
->dev
);
11336 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11337 set
->crtc
->base
.id
, ret
);
11339 intel_set_config_restore_state(dev
, config
);
11342 * HACK: if the pipe was on, but we didn't have a framebuffer,
11343 * force the pipe off to avoid oopsing in the modeset code
11344 * due to fb==NULL. This should only happen during boot since
11345 * we don't yet reconstruct the FB from the hardware state.
11347 if (to_intel_crtc(save_set
.crtc
)->new_enabled
&& !save_set
.fb
)
11348 disable_crtc_nofb(to_intel_crtc(save_set
.crtc
));
11350 /* Try to restore the config */
11351 if (config
->mode_changed
&&
11352 intel_set_mode(save_set
.crtc
, save_set
.mode
,
11353 save_set
.x
, save_set
.y
, save_set
.fb
))
11354 DRM_ERROR("failed to restore config after modeset failure\n");
11358 intel_set_config_free(config
);
11362 static const struct drm_crtc_funcs intel_crtc_funcs
= {
11363 .gamma_set
= intel_crtc_gamma_set
,
11364 .set_config
= intel_crtc_set_config
,
11365 .destroy
= intel_crtc_destroy
,
11366 .page_flip
= intel_crtc_page_flip
,
11369 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private
*dev_priv
,
11370 struct intel_shared_dpll
*pll
,
11371 struct intel_dpll_hw_state
*hw_state
)
11375 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
11378 val
= I915_READ(PCH_DPLL(pll
->id
));
11379 hw_state
->dpll
= val
;
11380 hw_state
->fp0
= I915_READ(PCH_FP0(pll
->id
));
11381 hw_state
->fp1
= I915_READ(PCH_FP1(pll
->id
));
11383 return val
& DPLL_VCO_ENABLE
;
11386 static void ibx_pch_dpll_mode_set(struct drm_i915_private
*dev_priv
,
11387 struct intel_shared_dpll
*pll
)
11389 I915_WRITE(PCH_FP0(pll
->id
), pll
->config
.hw_state
.fp0
);
11390 I915_WRITE(PCH_FP1(pll
->id
), pll
->config
.hw_state
.fp1
);
11393 static void ibx_pch_dpll_enable(struct drm_i915_private
*dev_priv
,
11394 struct intel_shared_dpll
*pll
)
11396 /* PCH refclock must be enabled first */
11397 ibx_assert_pch_refclk_enabled(dev_priv
);
11399 I915_WRITE(PCH_DPLL(pll
->id
), pll
->config
.hw_state
.dpll
);
11401 /* Wait for the clocks to stabilize. */
11402 POSTING_READ(PCH_DPLL(pll
->id
));
11405 /* The pixel multiplier can only be updated once the
11406 * DPLL is enabled and the clocks are stable.
11408 * So write it again.
11410 I915_WRITE(PCH_DPLL(pll
->id
), pll
->config
.hw_state
.dpll
);
11411 POSTING_READ(PCH_DPLL(pll
->id
));
11415 static void ibx_pch_dpll_disable(struct drm_i915_private
*dev_priv
,
11416 struct intel_shared_dpll
*pll
)
11418 struct drm_device
*dev
= dev_priv
->dev
;
11419 struct intel_crtc
*crtc
;
11421 /* Make sure no transcoder isn't still depending on us. */
11422 for_each_intel_crtc(dev
, crtc
) {
11423 if (intel_crtc_to_shared_dpll(crtc
) == pll
)
11424 assert_pch_transcoder_disabled(dev_priv
, crtc
->pipe
);
11427 I915_WRITE(PCH_DPLL(pll
->id
), 0);
11428 POSTING_READ(PCH_DPLL(pll
->id
));
11432 static char *ibx_pch_dpll_names
[] = {
11437 static void ibx_pch_dpll_init(struct drm_device
*dev
)
11439 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11442 dev_priv
->num_shared_dpll
= 2;
11444 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
11445 dev_priv
->shared_dplls
[i
].id
= i
;
11446 dev_priv
->shared_dplls
[i
].name
= ibx_pch_dpll_names
[i
];
11447 dev_priv
->shared_dplls
[i
].mode_set
= ibx_pch_dpll_mode_set
;
11448 dev_priv
->shared_dplls
[i
].enable
= ibx_pch_dpll_enable
;
11449 dev_priv
->shared_dplls
[i
].disable
= ibx_pch_dpll_disable
;
11450 dev_priv
->shared_dplls
[i
].get_hw_state
=
11451 ibx_pch_dpll_get_hw_state
;
11455 static void intel_shared_dpll_init(struct drm_device
*dev
)
11457 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11460 intel_ddi_pll_init(dev
);
11461 else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
11462 ibx_pch_dpll_init(dev
);
11464 dev_priv
->num_shared_dpll
= 0;
11466 BUG_ON(dev_priv
->num_shared_dpll
> I915_NUM_PLLS
);
11470 intel_primary_plane_disable(struct drm_plane
*plane
)
11472 struct drm_device
*dev
= plane
->dev
;
11473 struct intel_crtc
*intel_crtc
;
11478 BUG_ON(!plane
->crtc
);
11480 intel_crtc
= to_intel_crtc(plane
->crtc
);
11483 * Even though we checked plane->fb above, it's still possible that
11484 * the primary plane has been implicitly disabled because the crtc
11485 * coordinates given weren't visible, or because we detected
11486 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11487 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11488 * In either case, we need to unpin the FB and let the fb pointer get
11489 * updated, but otherwise we don't need to touch the hardware.
11491 if (!intel_crtc
->primary_enabled
)
11492 goto disable_unpin
;
11494 intel_crtc_wait_for_pending_flips(plane
->crtc
);
11495 intel_disable_primary_hw_plane(plane
, plane
->crtc
);
11498 mutex_lock(&dev
->struct_mutex
);
11499 i915_gem_track_fb(intel_fb_obj(plane
->fb
), NULL
,
11500 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
));
11501 intel_unpin_fb_obj(intel_fb_obj(plane
->fb
));
11502 mutex_unlock(&dev
->struct_mutex
);
11509 intel_check_primary_plane(struct drm_plane
*plane
,
11510 struct intel_plane_state
*state
)
11512 struct drm_crtc
*crtc
= state
->crtc
;
11513 struct drm_framebuffer
*fb
= state
->fb
;
11514 struct drm_rect
*dest
= &state
->dst
;
11515 struct drm_rect
*src
= &state
->src
;
11516 const struct drm_rect
*clip
= &state
->clip
;
11518 return drm_plane_helper_check_update(plane
, crtc
, fb
,
11520 DRM_PLANE_HELPER_NO_SCALING
,
11521 DRM_PLANE_HELPER_NO_SCALING
,
11522 false, true, &state
->visible
);
11526 intel_prepare_primary_plane(struct drm_plane
*plane
,
11527 struct intel_plane_state
*state
)
11529 struct drm_crtc
*crtc
= state
->crtc
;
11530 struct drm_framebuffer
*fb
= state
->fb
;
11531 struct drm_device
*dev
= crtc
->dev
;
11532 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11533 enum pipe pipe
= intel_crtc
->pipe
;
11534 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
11535 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(plane
->fb
);
11538 intel_crtc_wait_for_pending_flips(crtc
);
11540 if (intel_crtc_has_pending_flip(crtc
)) {
11541 DRM_ERROR("pipe is still busy with an old pageflip\n");
11545 if (old_obj
!= obj
) {
11546 mutex_lock(&dev
->struct_mutex
);
11547 ret
= intel_pin_and_fence_fb_obj(plane
, fb
, NULL
);
11549 i915_gem_track_fb(old_obj
, obj
,
11550 INTEL_FRONTBUFFER_PRIMARY(pipe
));
11551 mutex_unlock(&dev
->struct_mutex
);
11553 DRM_DEBUG_KMS("pin & fence failed\n");
11562 intel_commit_primary_plane(struct drm_plane
*plane
,
11563 struct intel_plane_state
*state
)
11565 struct drm_crtc
*crtc
= state
->crtc
;
11566 struct drm_framebuffer
*fb
= state
->fb
;
11567 struct drm_device
*dev
= crtc
->dev
;
11568 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11569 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11570 enum pipe pipe
= intel_crtc
->pipe
;
11571 struct drm_framebuffer
*old_fb
= plane
->fb
;
11572 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
11573 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(plane
->fb
);
11574 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
11575 struct drm_rect
*src
= &state
->src
;
11577 crtc
->primary
->fb
= fb
;
11581 intel_plane
->crtc_x
= state
->orig_dst
.x1
;
11582 intel_plane
->crtc_y
= state
->orig_dst
.y1
;
11583 intel_plane
->crtc_w
= drm_rect_width(&state
->orig_dst
);
11584 intel_plane
->crtc_h
= drm_rect_height(&state
->orig_dst
);
11585 intel_plane
->src_x
= state
->orig_src
.x1
;
11586 intel_plane
->src_y
= state
->orig_src
.y1
;
11587 intel_plane
->src_w
= drm_rect_width(&state
->orig_src
);
11588 intel_plane
->src_h
= drm_rect_height(&state
->orig_src
);
11589 intel_plane
->obj
= obj
;
11591 if (intel_crtc
->active
) {
11593 * FBC does not work on some platforms for rotated
11594 * planes, so disable it when rotation is not 0 and
11595 * update it when rotation is set back to 0.
11597 * FIXME: This is redundant with the fbc update done in
11598 * the primary plane enable function except that that
11599 * one is done too late. We eventually need to unify
11602 if (intel_crtc
->primary_enabled
&&
11603 INTEL_INFO(dev
)->gen
<= 4 && !IS_G4X(dev
) &&
11604 dev_priv
->fbc
.plane
== intel_crtc
->plane
&&
11605 intel_plane
->rotation
!= BIT(DRM_ROTATE_0
)) {
11606 intel_disable_fbc(dev
);
11609 if (state
->visible
) {
11610 bool was_enabled
= intel_crtc
->primary_enabled
;
11612 /* FIXME: kill this fastboot hack */
11613 intel_update_pipe_size(intel_crtc
);
11615 intel_crtc
->primary_enabled
= true;
11617 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
11621 * BDW signals flip done immediately if the plane
11622 * is disabled, even if the plane enable is already
11623 * armed to occur at the next vblank :(
11625 if (IS_BROADWELL(dev
) && !was_enabled
)
11626 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
11629 * If clipping results in a non-visible primary plane,
11630 * we'll disable the primary plane. Note that this is
11631 * a bit different than what happens if userspace
11632 * explicitly disables the plane by passing fb=0
11633 * because plane->fb still gets set and pinned.
11635 intel_disable_primary_hw_plane(plane
, crtc
);
11638 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
11640 mutex_lock(&dev
->struct_mutex
);
11641 intel_update_fbc(dev
);
11642 mutex_unlock(&dev
->struct_mutex
);
11645 if (old_fb
&& old_fb
!= fb
) {
11646 if (intel_crtc
->active
)
11647 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
11649 mutex_lock(&dev
->struct_mutex
);
11650 intel_unpin_fb_obj(old_obj
);
11651 mutex_unlock(&dev
->struct_mutex
);
11656 intel_primary_plane_setplane(struct drm_plane
*plane
, struct drm_crtc
*crtc
,
11657 struct drm_framebuffer
*fb
, int crtc_x
, int crtc_y
,
11658 unsigned int crtc_w
, unsigned int crtc_h
,
11659 uint32_t src_x
, uint32_t src_y
,
11660 uint32_t src_w
, uint32_t src_h
)
11662 struct intel_plane_state state
;
11663 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11669 /* sample coordinates in 16.16 fixed point */
11670 state
.src
.x1
= src_x
;
11671 state
.src
.x2
= src_x
+ src_w
;
11672 state
.src
.y1
= src_y
;
11673 state
.src
.y2
= src_y
+ src_h
;
11675 /* integer pixels */
11676 state
.dst
.x1
= crtc_x
;
11677 state
.dst
.x2
= crtc_x
+ crtc_w
;
11678 state
.dst
.y1
= crtc_y
;
11679 state
.dst
.y2
= crtc_y
+ crtc_h
;
11683 state
.clip
.x2
= intel_crtc
->active
? intel_crtc
->config
.pipe_src_w
: 0;
11684 state
.clip
.y2
= intel_crtc
->active
? intel_crtc
->config
.pipe_src_h
: 0;
11686 state
.orig_src
= state
.src
;
11687 state
.orig_dst
= state
.dst
;
11689 ret
= intel_check_primary_plane(plane
, &state
);
11693 ret
= intel_prepare_primary_plane(plane
, &state
);
11697 intel_commit_primary_plane(plane
, &state
);
11702 /* Common destruction function for both primary and cursor planes */
11703 static void intel_plane_destroy(struct drm_plane
*plane
)
11705 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
11706 drm_plane_cleanup(plane
);
11707 kfree(intel_plane
);
11710 static const struct drm_plane_funcs intel_primary_plane_funcs
= {
11711 .update_plane
= intel_primary_plane_setplane
,
11712 .disable_plane
= intel_primary_plane_disable
,
11713 .destroy
= intel_plane_destroy
,
11714 .set_property
= intel_plane_set_property
11717 static struct drm_plane
*intel_primary_plane_create(struct drm_device
*dev
,
11720 struct intel_plane
*primary
;
11721 const uint32_t *intel_primary_formats
;
11724 primary
= kzalloc(sizeof(*primary
), GFP_KERNEL
);
11725 if (primary
== NULL
)
11728 primary
->can_scale
= false;
11729 primary
->max_downscale
= 1;
11730 primary
->pipe
= pipe
;
11731 primary
->plane
= pipe
;
11732 primary
->rotation
= BIT(DRM_ROTATE_0
);
11733 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4)
11734 primary
->plane
= !pipe
;
11736 if (INTEL_INFO(dev
)->gen
<= 3) {
11737 intel_primary_formats
= intel_primary_formats_gen2
;
11738 num_formats
= ARRAY_SIZE(intel_primary_formats_gen2
);
11740 intel_primary_formats
= intel_primary_formats_gen4
;
11741 num_formats
= ARRAY_SIZE(intel_primary_formats_gen4
);
11744 drm_universal_plane_init(dev
, &primary
->base
, 0,
11745 &intel_primary_plane_funcs
,
11746 intel_primary_formats
, num_formats
,
11747 DRM_PLANE_TYPE_PRIMARY
);
11749 if (INTEL_INFO(dev
)->gen
>= 4) {
11750 if (!dev
->mode_config
.rotation_property
)
11751 dev
->mode_config
.rotation_property
=
11752 drm_mode_create_rotation_property(dev
,
11753 BIT(DRM_ROTATE_0
) |
11754 BIT(DRM_ROTATE_180
));
11755 if (dev
->mode_config
.rotation_property
)
11756 drm_object_attach_property(&primary
->base
.base
,
11757 dev
->mode_config
.rotation_property
,
11758 primary
->rotation
);
11761 return &primary
->base
;
11765 intel_cursor_plane_disable(struct drm_plane
*plane
)
11770 BUG_ON(!plane
->crtc
);
11772 return intel_crtc_cursor_set_obj(plane
->crtc
, NULL
, 0, 0);
11776 intel_check_cursor_plane(struct drm_plane
*plane
,
11777 struct intel_plane_state
*state
)
11779 struct drm_crtc
*crtc
= state
->crtc
;
11780 struct drm_device
*dev
= crtc
->dev
;
11781 struct drm_framebuffer
*fb
= state
->fb
;
11782 struct drm_rect
*dest
= &state
->dst
;
11783 struct drm_rect
*src
= &state
->src
;
11784 const struct drm_rect
*clip
= &state
->clip
;
11785 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
11786 int crtc_w
, crtc_h
;
11790 ret
= drm_plane_helper_check_update(plane
, crtc
, fb
,
11792 DRM_PLANE_HELPER_NO_SCALING
,
11793 DRM_PLANE_HELPER_NO_SCALING
,
11794 true, true, &state
->visible
);
11799 /* if we want to turn off the cursor ignore width and height */
11803 /* Check for which cursor types we support */
11804 crtc_w
= drm_rect_width(&state
->orig_dst
);
11805 crtc_h
= drm_rect_height(&state
->orig_dst
);
11806 if (!cursor_size_ok(dev
, crtc_w
, crtc_h
)) {
11807 DRM_DEBUG("Cursor dimension not supported\n");
11811 stride
= roundup_pow_of_two(crtc_w
) * 4;
11812 if (obj
->base
.size
< stride
* crtc_h
) {
11813 DRM_DEBUG_KMS("buffer is too small\n");
11817 if (fb
== crtc
->cursor
->fb
)
11820 /* we only need to pin inside GTT if cursor is non-phy */
11821 mutex_lock(&dev
->struct_mutex
);
11822 if (!INTEL_INFO(dev
)->cursor_needs_physical
&& obj
->tiling_mode
) {
11823 DRM_DEBUG_KMS("cursor cannot be tiled\n");
11826 mutex_unlock(&dev
->struct_mutex
);
11832 intel_commit_cursor_plane(struct drm_plane
*plane
,
11833 struct intel_plane_state
*state
)
11835 struct drm_crtc
*crtc
= state
->crtc
;
11836 struct drm_framebuffer
*fb
= state
->fb
;
11837 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11838 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
11839 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
11840 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
11841 int crtc_w
, crtc_h
;
11843 crtc
->cursor_x
= state
->orig_dst
.x1
;
11844 crtc
->cursor_y
= state
->orig_dst
.y1
;
11846 intel_plane
->crtc_x
= state
->orig_dst
.x1
;
11847 intel_plane
->crtc_y
= state
->orig_dst
.y1
;
11848 intel_plane
->crtc_w
= drm_rect_width(&state
->orig_dst
);
11849 intel_plane
->crtc_h
= drm_rect_height(&state
->orig_dst
);
11850 intel_plane
->src_x
= state
->orig_src
.x1
;
11851 intel_plane
->src_y
= state
->orig_src
.y1
;
11852 intel_plane
->src_w
= drm_rect_width(&state
->orig_src
);
11853 intel_plane
->src_h
= drm_rect_height(&state
->orig_src
);
11854 intel_plane
->obj
= obj
;
11856 if (fb
!= crtc
->cursor
->fb
) {
11857 crtc_w
= drm_rect_width(&state
->orig_dst
);
11858 crtc_h
= drm_rect_height(&state
->orig_dst
);
11859 return intel_crtc_cursor_set_obj(crtc
, obj
, crtc_w
, crtc_h
);
11861 intel_crtc_update_cursor(crtc
, state
->visible
);
11863 intel_frontbuffer_flip(crtc
->dev
,
11864 INTEL_FRONTBUFFER_CURSOR(intel_crtc
->pipe
));
11871 intel_cursor_plane_update(struct drm_plane
*plane
, struct drm_crtc
*crtc
,
11872 struct drm_framebuffer
*fb
, int crtc_x
, int crtc_y
,
11873 unsigned int crtc_w
, unsigned int crtc_h
,
11874 uint32_t src_x
, uint32_t src_y
,
11875 uint32_t src_w
, uint32_t src_h
)
11877 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11878 struct intel_plane_state state
;
11884 /* sample coordinates in 16.16 fixed point */
11885 state
.src
.x1
= src_x
;
11886 state
.src
.x2
= src_x
+ src_w
;
11887 state
.src
.y1
= src_y
;
11888 state
.src
.y2
= src_y
+ src_h
;
11890 /* integer pixels */
11891 state
.dst
.x1
= crtc_x
;
11892 state
.dst
.x2
= crtc_x
+ crtc_w
;
11893 state
.dst
.y1
= crtc_y
;
11894 state
.dst
.y2
= crtc_y
+ crtc_h
;
11898 state
.clip
.x2
= intel_crtc
->active
? intel_crtc
->config
.pipe_src_w
: 0;
11899 state
.clip
.y2
= intel_crtc
->active
? intel_crtc
->config
.pipe_src_h
: 0;
11901 state
.orig_src
= state
.src
;
11902 state
.orig_dst
= state
.dst
;
11904 ret
= intel_check_cursor_plane(plane
, &state
);
11908 return intel_commit_cursor_plane(plane
, &state
);
11911 static const struct drm_plane_funcs intel_cursor_plane_funcs
= {
11912 .update_plane
= intel_cursor_plane_update
,
11913 .disable_plane
= intel_cursor_plane_disable
,
11914 .destroy
= intel_plane_destroy
,
11915 .set_property
= intel_plane_set_property
,
11918 static struct drm_plane
*intel_cursor_plane_create(struct drm_device
*dev
,
11921 struct intel_plane
*cursor
;
11923 cursor
= kzalloc(sizeof(*cursor
), GFP_KERNEL
);
11924 if (cursor
== NULL
)
11927 cursor
->can_scale
= false;
11928 cursor
->max_downscale
= 1;
11929 cursor
->pipe
= pipe
;
11930 cursor
->plane
= pipe
;
11931 cursor
->rotation
= BIT(DRM_ROTATE_0
);
11933 drm_universal_plane_init(dev
, &cursor
->base
, 0,
11934 &intel_cursor_plane_funcs
,
11935 intel_cursor_formats
,
11936 ARRAY_SIZE(intel_cursor_formats
),
11937 DRM_PLANE_TYPE_CURSOR
);
11939 if (INTEL_INFO(dev
)->gen
>= 4) {
11940 if (!dev
->mode_config
.rotation_property
)
11941 dev
->mode_config
.rotation_property
=
11942 drm_mode_create_rotation_property(dev
,
11943 BIT(DRM_ROTATE_0
) |
11944 BIT(DRM_ROTATE_180
));
11945 if (dev
->mode_config
.rotation_property
)
11946 drm_object_attach_property(&cursor
->base
.base
,
11947 dev
->mode_config
.rotation_property
,
11951 return &cursor
->base
;
11954 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
11956 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11957 struct intel_crtc
*intel_crtc
;
11958 struct drm_plane
*primary
= NULL
;
11959 struct drm_plane
*cursor
= NULL
;
11962 intel_crtc
= kzalloc(sizeof(*intel_crtc
), GFP_KERNEL
);
11963 if (intel_crtc
== NULL
)
11966 primary
= intel_primary_plane_create(dev
, pipe
);
11970 cursor
= intel_cursor_plane_create(dev
, pipe
);
11974 ret
= drm_crtc_init_with_planes(dev
, &intel_crtc
->base
, primary
,
11975 cursor
, &intel_crtc_funcs
);
11979 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
11980 for (i
= 0; i
< 256; i
++) {
11981 intel_crtc
->lut_r
[i
] = i
;
11982 intel_crtc
->lut_g
[i
] = i
;
11983 intel_crtc
->lut_b
[i
] = i
;
11987 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
11988 * is hooked to pipe B. Hence we want plane A feeding pipe B.
11990 intel_crtc
->pipe
= pipe
;
11991 intel_crtc
->plane
= pipe
;
11992 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4) {
11993 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
11994 intel_crtc
->plane
= !pipe
;
11997 intel_crtc
->cursor_base
= ~0;
11998 intel_crtc
->cursor_cntl
= ~0;
11999 intel_crtc
->cursor_size
= ~0;
12001 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
12002 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
12003 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
12004 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
12006 INIT_WORK(&intel_crtc
->mmio_flip
.work
, intel_mmio_flip_work_func
);
12008 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
12010 WARN_ON(drm_crtc_index(&intel_crtc
->base
) != intel_crtc
->pipe
);
12015 drm_plane_cleanup(primary
);
12017 drm_plane_cleanup(cursor
);
12021 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
)
12023 struct drm_encoder
*encoder
= connector
->base
.encoder
;
12024 struct drm_device
*dev
= connector
->base
.dev
;
12026 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
12029 return INVALID_PIPE
;
12031 return to_intel_crtc(encoder
->crtc
)->pipe
;
12034 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
12035 struct drm_file
*file
)
12037 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
12038 struct drm_crtc
*drmmode_crtc
;
12039 struct intel_crtc
*crtc
;
12041 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
12044 drmmode_crtc
= drm_crtc_find(dev
, pipe_from_crtc_id
->crtc_id
);
12046 if (!drmmode_crtc
) {
12047 DRM_ERROR("no such CRTC id\n");
12051 crtc
= to_intel_crtc(drmmode_crtc
);
12052 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
12057 static int intel_encoder_clones(struct intel_encoder
*encoder
)
12059 struct drm_device
*dev
= encoder
->base
.dev
;
12060 struct intel_encoder
*source_encoder
;
12061 int index_mask
= 0;
12064 for_each_intel_encoder(dev
, source_encoder
) {
12065 if (encoders_cloneable(encoder
, source_encoder
))
12066 index_mask
|= (1 << entry
);
12074 static bool has_edp_a(struct drm_device
*dev
)
12076 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12078 if (!IS_MOBILE(dev
))
12081 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
12084 if (IS_GEN5(dev
) && (I915_READ(FUSE_STRAP
) & ILK_eDP_A_DISABLE
))
12090 const char *intel_output_name(int output
)
12092 static const char *names
[] = {
12093 [INTEL_OUTPUT_UNUSED
] = "Unused",
12094 [INTEL_OUTPUT_ANALOG
] = "Analog",
12095 [INTEL_OUTPUT_DVO
] = "DVO",
12096 [INTEL_OUTPUT_SDVO
] = "SDVO",
12097 [INTEL_OUTPUT_LVDS
] = "LVDS",
12098 [INTEL_OUTPUT_TVOUT
] = "TV",
12099 [INTEL_OUTPUT_HDMI
] = "HDMI",
12100 [INTEL_OUTPUT_DISPLAYPORT
] = "DisplayPort",
12101 [INTEL_OUTPUT_EDP
] = "eDP",
12102 [INTEL_OUTPUT_DSI
] = "DSI",
12103 [INTEL_OUTPUT_UNKNOWN
] = "Unknown",
12106 if (output
< 0 || output
>= ARRAY_SIZE(names
) || !names
[output
])
12109 return names
[output
];
12112 static bool intel_crt_present(struct drm_device
*dev
)
12114 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12116 if (INTEL_INFO(dev
)->gen
>= 9)
12119 if (IS_HSW_ULT(dev
) || IS_BDW_ULT(dev
))
12122 if (IS_CHERRYVIEW(dev
))
12125 if (IS_VALLEYVIEW(dev
) && !dev_priv
->vbt
.int_crt_support
)
12131 static void intel_setup_outputs(struct drm_device
*dev
)
12133 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12134 struct intel_encoder
*encoder
;
12135 bool dpd_is_edp
= false;
12137 intel_lvds_init(dev
);
12139 if (intel_crt_present(dev
))
12140 intel_crt_init(dev
);
12142 if (HAS_DDI(dev
)) {
12145 /* Haswell uses DDI functions to detect digital outputs */
12146 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
12147 /* DDI A only supports eDP */
12149 intel_ddi_init(dev
, PORT_A
);
12151 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12153 found
= I915_READ(SFUSE_STRAP
);
12155 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
12156 intel_ddi_init(dev
, PORT_B
);
12157 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
12158 intel_ddi_init(dev
, PORT_C
);
12159 if (found
& SFUSE_STRAP_DDID_DETECTED
)
12160 intel_ddi_init(dev
, PORT_D
);
12161 } else if (HAS_PCH_SPLIT(dev
)) {
12163 dpd_is_edp
= intel_dp_is_edp(dev
, PORT_D
);
12165 if (has_edp_a(dev
))
12166 intel_dp_init(dev
, DP_A
, PORT_A
);
12168 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
12169 /* PCH SDVOB multiplex with HDMIB */
12170 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
12172 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
12173 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
12174 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
12177 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
12178 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
12180 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
12181 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
12183 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
12184 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
12186 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
12187 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
12188 } else if (IS_VALLEYVIEW(dev
)) {
12190 * The DP_DETECTED bit is the latched state of the DDC
12191 * SDA pin at boot. However since eDP doesn't require DDC
12192 * (no way to plug in a DP->HDMI dongle) the DDC pins for
12193 * eDP ports may have been muxed to an alternate function.
12194 * Thus we can't rely on the DP_DETECTED bit alone to detect
12195 * eDP ports. Consult the VBT as well as DP_DETECTED to
12196 * detect eDP ports.
12198 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIB
) & SDVO_DETECTED
)
12199 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIB
,
12201 if (I915_READ(VLV_DISPLAY_BASE
+ DP_B
) & DP_DETECTED
||
12202 intel_dp_is_edp(dev
, PORT_B
))
12203 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_B
, PORT_B
);
12205 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIC
) & SDVO_DETECTED
)
12206 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIC
,
12208 if (I915_READ(VLV_DISPLAY_BASE
+ DP_C
) & DP_DETECTED
||
12209 intel_dp_is_edp(dev
, PORT_C
))
12210 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_C
, PORT_C
);
12212 if (IS_CHERRYVIEW(dev
)) {
12213 if (I915_READ(VLV_DISPLAY_BASE
+ CHV_HDMID
) & SDVO_DETECTED
)
12214 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ CHV_HDMID
,
12216 /* eDP not supported on port D, so don't check VBT */
12217 if (I915_READ(VLV_DISPLAY_BASE
+ DP_D
) & DP_DETECTED
)
12218 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_D
, PORT_D
);
12221 intel_dsi_init(dev
);
12222 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
12223 bool found
= false;
12225 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
12226 DRM_DEBUG_KMS("probing SDVOB\n");
12227 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, true);
12228 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
12229 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12230 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
12233 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
))
12234 intel_dp_init(dev
, DP_B
, PORT_B
);
12237 /* Before G4X SDVOC doesn't have its own detect register */
12239 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
12240 DRM_DEBUG_KMS("probing SDVOC\n");
12241 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, false);
12244 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
12246 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
12247 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12248 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
12250 if (SUPPORTS_INTEGRATED_DP(dev
))
12251 intel_dp_init(dev
, DP_C
, PORT_C
);
12254 if (SUPPORTS_INTEGRATED_DP(dev
) &&
12255 (I915_READ(DP_D
) & DP_DETECTED
))
12256 intel_dp_init(dev
, DP_D
, PORT_D
);
12257 } else if (IS_GEN2(dev
))
12258 intel_dvo_init(dev
);
12260 if (SUPPORTS_TV(dev
))
12261 intel_tv_init(dev
);
12263 intel_edp_psr_init(dev
);
12265 for_each_intel_encoder(dev
, encoder
) {
12266 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
12267 encoder
->base
.possible_clones
=
12268 intel_encoder_clones(encoder
);
12271 intel_init_pch_refclk(dev
);
12273 drm_helper_move_panel_connectors_to_head(dev
);
12276 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
12278 struct drm_device
*dev
= fb
->dev
;
12279 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
12281 drm_framebuffer_cleanup(fb
);
12282 mutex_lock(&dev
->struct_mutex
);
12283 WARN_ON(!intel_fb
->obj
->framebuffer_references
--);
12284 drm_gem_object_unreference(&intel_fb
->obj
->base
);
12285 mutex_unlock(&dev
->struct_mutex
);
12289 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
12290 struct drm_file
*file
,
12291 unsigned int *handle
)
12293 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
12294 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
12296 return drm_gem_handle_create(file
, &obj
->base
, handle
);
12299 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
12300 .destroy
= intel_user_framebuffer_destroy
,
12301 .create_handle
= intel_user_framebuffer_create_handle
,
12304 static int intel_framebuffer_init(struct drm_device
*dev
,
12305 struct intel_framebuffer
*intel_fb
,
12306 struct drm_mode_fb_cmd2
*mode_cmd
,
12307 struct drm_i915_gem_object
*obj
)
12309 int aligned_height
;
12313 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
12315 if (obj
->tiling_mode
== I915_TILING_Y
) {
12316 DRM_DEBUG("hardware does not support tiling Y\n");
12320 if (mode_cmd
->pitches
[0] & 63) {
12321 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12322 mode_cmd
->pitches
[0]);
12326 if (INTEL_INFO(dev
)->gen
>= 5 && !IS_VALLEYVIEW(dev
)) {
12327 pitch_limit
= 32*1024;
12328 } else if (INTEL_INFO(dev
)->gen
>= 4) {
12329 if (obj
->tiling_mode
)
12330 pitch_limit
= 16*1024;
12332 pitch_limit
= 32*1024;
12333 } else if (INTEL_INFO(dev
)->gen
>= 3) {
12334 if (obj
->tiling_mode
)
12335 pitch_limit
= 8*1024;
12337 pitch_limit
= 16*1024;
12339 /* XXX DSPC is limited to 4k tiled */
12340 pitch_limit
= 8*1024;
12342 if (mode_cmd
->pitches
[0] > pitch_limit
) {
12343 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12344 obj
->tiling_mode
? "tiled" : "linear",
12345 mode_cmd
->pitches
[0], pitch_limit
);
12349 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
12350 mode_cmd
->pitches
[0] != obj
->stride
) {
12351 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12352 mode_cmd
->pitches
[0], obj
->stride
);
12356 /* Reject formats not supported by any plane early. */
12357 switch (mode_cmd
->pixel_format
) {
12358 case DRM_FORMAT_C8
:
12359 case DRM_FORMAT_RGB565
:
12360 case DRM_FORMAT_XRGB8888
:
12361 case DRM_FORMAT_ARGB8888
:
12363 case DRM_FORMAT_XRGB1555
:
12364 case DRM_FORMAT_ARGB1555
:
12365 if (INTEL_INFO(dev
)->gen
> 3) {
12366 DRM_DEBUG("unsupported pixel format: %s\n",
12367 drm_get_format_name(mode_cmd
->pixel_format
));
12371 case DRM_FORMAT_XBGR8888
:
12372 case DRM_FORMAT_ABGR8888
:
12373 case DRM_FORMAT_XRGB2101010
:
12374 case DRM_FORMAT_ARGB2101010
:
12375 case DRM_FORMAT_XBGR2101010
:
12376 case DRM_FORMAT_ABGR2101010
:
12377 if (INTEL_INFO(dev
)->gen
< 4) {
12378 DRM_DEBUG("unsupported pixel format: %s\n",
12379 drm_get_format_name(mode_cmd
->pixel_format
));
12383 case DRM_FORMAT_YUYV
:
12384 case DRM_FORMAT_UYVY
:
12385 case DRM_FORMAT_YVYU
:
12386 case DRM_FORMAT_VYUY
:
12387 if (INTEL_INFO(dev
)->gen
< 5) {
12388 DRM_DEBUG("unsupported pixel format: %s\n",
12389 drm_get_format_name(mode_cmd
->pixel_format
));
12394 DRM_DEBUG("unsupported pixel format: %s\n",
12395 drm_get_format_name(mode_cmd
->pixel_format
));
12399 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12400 if (mode_cmd
->offsets
[0] != 0)
12403 aligned_height
= intel_align_height(dev
, mode_cmd
->height
,
12405 /* FIXME drm helper for size checks (especially planar formats)? */
12406 if (obj
->base
.size
< aligned_height
* mode_cmd
->pitches
[0])
12409 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
12410 intel_fb
->obj
= obj
;
12411 intel_fb
->obj
->framebuffer_references
++;
12413 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
12415 DRM_ERROR("framebuffer init failed %d\n", ret
);
12422 static struct drm_framebuffer
*
12423 intel_user_framebuffer_create(struct drm_device
*dev
,
12424 struct drm_file
*filp
,
12425 struct drm_mode_fb_cmd2
*mode_cmd
)
12427 struct drm_i915_gem_object
*obj
;
12429 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
12430 mode_cmd
->handles
[0]));
12431 if (&obj
->base
== NULL
)
12432 return ERR_PTR(-ENOENT
);
12434 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
12437 #ifndef CONFIG_DRM_I915_FBDEV
12438 static inline void intel_fbdev_output_poll_changed(struct drm_device
*dev
)
12443 static const struct drm_mode_config_funcs intel_mode_funcs
= {
12444 .fb_create
= intel_user_framebuffer_create
,
12445 .output_poll_changed
= intel_fbdev_output_poll_changed
,
12448 /* Set up chip specific display functions */
12449 static void intel_init_display(struct drm_device
*dev
)
12451 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12453 if (HAS_PCH_SPLIT(dev
) || IS_G4X(dev
))
12454 dev_priv
->display
.find_dpll
= g4x_find_best_dpll
;
12455 else if (IS_CHERRYVIEW(dev
))
12456 dev_priv
->display
.find_dpll
= chv_find_best_dpll
;
12457 else if (IS_VALLEYVIEW(dev
))
12458 dev_priv
->display
.find_dpll
= vlv_find_best_dpll
;
12459 else if (IS_PINEVIEW(dev
))
12460 dev_priv
->display
.find_dpll
= pnv_find_best_dpll
;
12462 dev_priv
->display
.find_dpll
= i9xx_find_best_dpll
;
12464 if (HAS_DDI(dev
)) {
12465 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
12466 dev_priv
->display
.get_plane_config
= ironlake_get_plane_config
;
12467 dev_priv
->display
.crtc_compute_clock
=
12468 haswell_crtc_compute_clock
;
12469 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
12470 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
12471 dev_priv
->display
.off
= ironlake_crtc_off
;
12472 if (INTEL_INFO(dev
)->gen
>= 9)
12473 dev_priv
->display
.update_primary_plane
=
12474 skylake_update_primary_plane
;
12476 dev_priv
->display
.update_primary_plane
=
12477 ironlake_update_primary_plane
;
12478 } else if (HAS_PCH_SPLIT(dev
)) {
12479 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
12480 dev_priv
->display
.get_plane_config
= ironlake_get_plane_config
;
12481 dev_priv
->display
.crtc_compute_clock
=
12482 ironlake_crtc_compute_clock
;
12483 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
12484 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
12485 dev_priv
->display
.off
= ironlake_crtc_off
;
12486 dev_priv
->display
.update_primary_plane
=
12487 ironlake_update_primary_plane
;
12488 } else if (IS_VALLEYVIEW(dev
)) {
12489 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
12490 dev_priv
->display
.get_plane_config
= i9xx_get_plane_config
;
12491 dev_priv
->display
.crtc_compute_clock
= i9xx_crtc_compute_clock
;
12492 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
12493 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
12494 dev_priv
->display
.off
= i9xx_crtc_off
;
12495 dev_priv
->display
.update_primary_plane
=
12496 i9xx_update_primary_plane
;
12498 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
12499 dev_priv
->display
.get_plane_config
= i9xx_get_plane_config
;
12500 dev_priv
->display
.crtc_compute_clock
= i9xx_crtc_compute_clock
;
12501 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
12502 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
12503 dev_priv
->display
.off
= i9xx_crtc_off
;
12504 dev_priv
->display
.update_primary_plane
=
12505 i9xx_update_primary_plane
;
12508 /* Returns the core display clock speed */
12509 if (IS_VALLEYVIEW(dev
))
12510 dev_priv
->display
.get_display_clock_speed
=
12511 valleyview_get_display_clock_speed
;
12512 else if (IS_I945G(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
12513 dev_priv
->display
.get_display_clock_speed
=
12514 i945_get_display_clock_speed
;
12515 else if (IS_I915G(dev
))
12516 dev_priv
->display
.get_display_clock_speed
=
12517 i915_get_display_clock_speed
;
12518 else if (IS_I945GM(dev
) || IS_845G(dev
))
12519 dev_priv
->display
.get_display_clock_speed
=
12520 i9xx_misc_get_display_clock_speed
;
12521 else if (IS_PINEVIEW(dev
))
12522 dev_priv
->display
.get_display_clock_speed
=
12523 pnv_get_display_clock_speed
;
12524 else if (IS_I915GM(dev
))
12525 dev_priv
->display
.get_display_clock_speed
=
12526 i915gm_get_display_clock_speed
;
12527 else if (IS_I865G(dev
))
12528 dev_priv
->display
.get_display_clock_speed
=
12529 i865_get_display_clock_speed
;
12530 else if (IS_I85X(dev
))
12531 dev_priv
->display
.get_display_clock_speed
=
12532 i855_get_display_clock_speed
;
12533 else /* 852, 830 */
12534 dev_priv
->display
.get_display_clock_speed
=
12535 i830_get_display_clock_speed
;
12537 if (IS_GEN5(dev
)) {
12538 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
12539 } else if (IS_GEN6(dev
)) {
12540 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
12541 dev_priv
->display
.modeset_global_resources
=
12542 snb_modeset_global_resources
;
12543 } else if (IS_IVYBRIDGE(dev
)) {
12544 /* FIXME: detect B0+ stepping and use auto training */
12545 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
12546 dev_priv
->display
.modeset_global_resources
=
12547 ivb_modeset_global_resources
;
12548 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
12549 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
12550 dev_priv
->display
.modeset_global_resources
=
12551 haswell_modeset_global_resources
;
12552 } else if (IS_VALLEYVIEW(dev
)) {
12553 dev_priv
->display
.modeset_global_resources
=
12554 valleyview_modeset_global_resources
;
12555 } else if (INTEL_INFO(dev
)->gen
>= 9) {
12556 dev_priv
->display
.modeset_global_resources
=
12557 haswell_modeset_global_resources
;
12560 /* Default just returns -ENODEV to indicate unsupported */
12561 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
12563 switch (INTEL_INFO(dev
)->gen
) {
12565 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
12569 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
12574 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
12578 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
12581 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12582 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
12586 intel_panel_init_backlight_funcs(dev
);
12588 mutex_init(&dev_priv
->pps_mutex
);
12592 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12593 * resume, or other times. This quirk makes sure that's the case for
12594 * affected systems.
12596 static void quirk_pipea_force(struct drm_device
*dev
)
12598 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12600 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
12601 DRM_INFO("applying pipe a force quirk\n");
12604 static void quirk_pipeb_force(struct drm_device
*dev
)
12606 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12608 dev_priv
->quirks
|= QUIRK_PIPEB_FORCE
;
12609 DRM_INFO("applying pipe b force quirk\n");
12613 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12615 static void quirk_ssc_force_disable(struct drm_device
*dev
)
12617 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12618 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
12619 DRM_INFO("applying lvds SSC disable quirk\n");
12623 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12626 static void quirk_invert_brightness(struct drm_device
*dev
)
12628 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12629 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
12630 DRM_INFO("applying inverted panel brightness quirk\n");
12633 /* Some VBT's incorrectly indicate no backlight is present */
12634 static void quirk_backlight_present(struct drm_device
*dev
)
12636 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12637 dev_priv
->quirks
|= QUIRK_BACKLIGHT_PRESENT
;
12638 DRM_INFO("applying backlight present quirk\n");
12641 struct intel_quirk
{
12643 int subsystem_vendor
;
12644 int subsystem_device
;
12645 void (*hook
)(struct drm_device
*dev
);
12648 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12649 struct intel_dmi_quirk
{
12650 void (*hook
)(struct drm_device
*dev
);
12651 const struct dmi_system_id (*dmi_id_list
)[];
12654 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
12656 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
12660 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
12662 .dmi_id_list
= &(const struct dmi_system_id
[]) {
12664 .callback
= intel_dmi_reverse_brightness
,
12665 .ident
= "NCR Corporation",
12666 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
12667 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
12670 { } /* terminating entry */
12672 .hook
= quirk_invert_brightness
,
12676 static struct intel_quirk intel_quirks
[] = {
12677 /* HP Mini needs pipe A force quirk (LP: #322104) */
12678 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
12680 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12681 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
12683 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12684 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
12686 /* 830 needs to leave pipe A & dpll A up */
12687 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
12689 /* 830 needs to leave pipe B & dpll B up */
12690 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipeb_force
},
12692 /* Lenovo U160 cannot use SSC on LVDS */
12693 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
12695 /* Sony Vaio Y cannot use SSC on LVDS */
12696 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
12698 /* Acer Aspire 5734Z must invert backlight brightness */
12699 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
12701 /* Acer/eMachines G725 */
12702 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
12704 /* Acer/eMachines e725 */
12705 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
12707 /* Acer/Packard Bell NCL20 */
12708 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
12710 /* Acer Aspire 4736Z */
12711 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
12713 /* Acer Aspire 5336 */
12714 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness
},
12716 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12717 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present
},
12719 /* Acer C720 Chromebook (Core i3 4005U) */
12720 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present
},
12722 /* Toshiba CB35 Chromebook (Celeron 2955U) */
12723 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present
},
12725 /* HP Chromebook 14 (Celeron 2955U) */
12726 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present
},
12729 static void intel_init_quirks(struct drm_device
*dev
)
12731 struct pci_dev
*d
= dev
->pdev
;
12734 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
12735 struct intel_quirk
*q
= &intel_quirks
[i
];
12737 if (d
->device
== q
->device
&&
12738 (d
->subsystem_vendor
== q
->subsystem_vendor
||
12739 q
->subsystem_vendor
== PCI_ANY_ID
) &&
12740 (d
->subsystem_device
== q
->subsystem_device
||
12741 q
->subsystem_device
== PCI_ANY_ID
))
12744 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
12745 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
12746 intel_dmi_quirks
[i
].hook(dev
);
12750 /* Disable the VGA plane that we never use */
12751 static void i915_disable_vga(struct drm_device
*dev
)
12753 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12755 u32 vga_reg
= i915_vgacntrl_reg(dev
);
12757 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12758 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
12759 outb(SR01
, VGA_SR_INDEX
);
12760 sr1
= inb(VGA_SR_DATA
);
12761 outb(sr1
| 1<<5, VGA_SR_DATA
);
12762 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
12766 * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming
12767 * from S3 without preserving (some of?) the other bits.
12769 I915_WRITE(vga_reg
, dev_priv
->bios_vgacntr
| VGA_DISP_DISABLE
);
12770 POSTING_READ(vga_reg
);
12773 void intel_modeset_init_hw(struct drm_device
*dev
)
12775 intel_prepare_ddi(dev
);
12777 if (IS_VALLEYVIEW(dev
))
12778 vlv_update_cdclk(dev
);
12780 intel_init_clock_gating(dev
);
12782 intel_enable_gt_powersave(dev
);
12785 void intel_modeset_init(struct drm_device
*dev
)
12787 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12790 struct intel_crtc
*crtc
;
12792 drm_mode_config_init(dev
);
12794 dev
->mode_config
.min_width
= 0;
12795 dev
->mode_config
.min_height
= 0;
12797 dev
->mode_config
.preferred_depth
= 24;
12798 dev
->mode_config
.prefer_shadow
= 1;
12800 dev
->mode_config
.funcs
= &intel_mode_funcs
;
12802 intel_init_quirks(dev
);
12804 intel_init_pm(dev
);
12806 if (INTEL_INFO(dev
)->num_pipes
== 0)
12809 intel_init_display(dev
);
12810 intel_init_audio(dev
);
12812 if (IS_GEN2(dev
)) {
12813 dev
->mode_config
.max_width
= 2048;
12814 dev
->mode_config
.max_height
= 2048;
12815 } else if (IS_GEN3(dev
)) {
12816 dev
->mode_config
.max_width
= 4096;
12817 dev
->mode_config
.max_height
= 4096;
12819 dev
->mode_config
.max_width
= 8192;
12820 dev
->mode_config
.max_height
= 8192;
12823 if (IS_845G(dev
) || IS_I865G(dev
)) {
12824 dev
->mode_config
.cursor_width
= IS_845G(dev
) ? 64 : 512;
12825 dev
->mode_config
.cursor_height
= 1023;
12826 } else if (IS_GEN2(dev
)) {
12827 dev
->mode_config
.cursor_width
= GEN2_CURSOR_WIDTH
;
12828 dev
->mode_config
.cursor_height
= GEN2_CURSOR_HEIGHT
;
12830 dev
->mode_config
.cursor_width
= MAX_CURSOR_WIDTH
;
12831 dev
->mode_config
.cursor_height
= MAX_CURSOR_HEIGHT
;
12834 dev
->mode_config
.fb_base
= dev_priv
->gtt
.mappable_base
;
12836 DRM_DEBUG_KMS("%d display pipe%s available.\n",
12837 INTEL_INFO(dev
)->num_pipes
,
12838 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
12840 for_each_pipe(dev_priv
, pipe
) {
12841 intel_crtc_init(dev
, pipe
);
12842 for_each_sprite(pipe
, sprite
) {
12843 ret
= intel_plane_init(dev
, pipe
, sprite
);
12845 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12846 pipe_name(pipe
), sprite_name(pipe
, sprite
), ret
);
12850 intel_init_dpio(dev
);
12852 intel_shared_dpll_init(dev
);
12854 /* save the BIOS value before clobbering it */
12855 dev_priv
->bios_vgacntr
= I915_READ(i915_vgacntrl_reg(dev
));
12856 /* Just disable it once at startup */
12857 i915_disable_vga(dev
);
12858 intel_setup_outputs(dev
);
12860 /* Just in case the BIOS is doing something questionable. */
12861 intel_disable_fbc(dev
);
12863 drm_modeset_lock_all(dev
);
12864 intel_modeset_setup_hw_state(dev
, false);
12865 drm_modeset_unlock_all(dev
);
12867 for_each_intel_crtc(dev
, crtc
) {
12872 * Note that reserving the BIOS fb up front prevents us
12873 * from stuffing other stolen allocations like the ring
12874 * on top. This prevents some ugliness at boot time, and
12875 * can even allow for smooth boot transitions if the BIOS
12876 * fb is large enough for the active pipe configuration.
12878 if (dev_priv
->display
.get_plane_config
) {
12879 dev_priv
->display
.get_plane_config(crtc
,
12880 &crtc
->plane_config
);
12882 * If the fb is shared between multiple heads, we'll
12883 * just get the first one.
12885 intel_find_plane_obj(crtc
, &crtc
->plane_config
);
12890 static void intel_enable_pipe_a(struct drm_device
*dev
)
12892 struct intel_connector
*connector
;
12893 struct drm_connector
*crt
= NULL
;
12894 struct intel_load_detect_pipe load_detect_temp
;
12895 struct drm_modeset_acquire_ctx
*ctx
= dev
->mode_config
.acquire_ctx
;
12897 /* We can't just switch on the pipe A, we need to set things up with a
12898 * proper mode and output configuration. As a gross hack, enable pipe A
12899 * by enabling the load detect pipe once. */
12900 list_for_each_entry(connector
,
12901 &dev
->mode_config
.connector_list
,
12903 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
12904 crt
= &connector
->base
;
12912 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
, ctx
))
12913 intel_release_load_detect_pipe(crt
, &load_detect_temp
);
12917 intel_check_plane_mapping(struct intel_crtc
*crtc
)
12919 struct drm_device
*dev
= crtc
->base
.dev
;
12920 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12923 if (INTEL_INFO(dev
)->num_pipes
== 1)
12926 reg
= DSPCNTR(!crtc
->plane
);
12927 val
= I915_READ(reg
);
12929 if ((val
& DISPLAY_PLANE_ENABLE
) &&
12930 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
12936 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
12938 struct drm_device
*dev
= crtc
->base
.dev
;
12939 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12942 /* Clear any frame start delays used for debugging left by the BIOS */
12943 reg
= PIPECONF(crtc
->config
.cpu_transcoder
);
12944 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
12946 /* restore vblank interrupts to correct state */
12947 if (crtc
->active
) {
12948 update_scanline_offset(crtc
);
12949 drm_vblank_on(dev
, crtc
->pipe
);
12951 drm_vblank_off(dev
, crtc
->pipe
);
12953 /* We need to sanitize the plane -> pipe mapping first because this will
12954 * disable the crtc (and hence change the state) if it is wrong. Note
12955 * that gen4+ has a fixed plane -> pipe mapping. */
12956 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
12957 struct intel_connector
*connector
;
12960 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
12961 crtc
->base
.base
.id
);
12963 /* Pipe has the wrong plane attached and the plane is active.
12964 * Temporarily change the plane mapping and disable everything
12966 plane
= crtc
->plane
;
12967 crtc
->plane
= !plane
;
12968 crtc
->primary_enabled
= true;
12969 dev_priv
->display
.crtc_disable(&crtc
->base
);
12970 crtc
->plane
= plane
;
12972 /* ... and break all links. */
12973 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
12975 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
12978 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
12979 connector
->base
.encoder
= NULL
;
12981 /* multiple connectors may have the same encoder:
12982 * handle them and break crtc link separately */
12983 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
12985 if (connector
->encoder
->base
.crtc
== &crtc
->base
) {
12986 connector
->encoder
->base
.crtc
= NULL
;
12987 connector
->encoder
->connectors_active
= false;
12990 WARN_ON(crtc
->active
);
12991 crtc
->base
.enabled
= false;
12994 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
12995 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
12996 /* BIOS forgot to enable pipe A, this mostly happens after
12997 * resume. Force-enable the pipe to fix this, the update_dpms
12998 * call below we restore the pipe to the right state, but leave
12999 * the required bits on. */
13000 intel_enable_pipe_a(dev
);
13003 /* Adjust the state of the output pipe according to whether we
13004 * have active connectors/encoders. */
13005 intel_crtc_update_dpms(&crtc
->base
);
13007 if (crtc
->active
!= crtc
->base
.enabled
) {
13008 struct intel_encoder
*encoder
;
13010 /* This can happen either due to bugs in the get_hw_state
13011 * functions or because the pipe is force-enabled due to the
13013 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13014 crtc
->base
.base
.id
,
13015 crtc
->base
.enabled
? "enabled" : "disabled",
13016 crtc
->active
? "enabled" : "disabled");
13018 crtc
->base
.enabled
= crtc
->active
;
13020 /* Because we only establish the connector -> encoder ->
13021 * crtc links if something is active, this means the
13022 * crtc is now deactivated. Break the links. connector
13023 * -> encoder links are only establish when things are
13024 * actually up, hence no need to break them. */
13025 WARN_ON(crtc
->active
);
13027 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
13028 WARN_ON(encoder
->connectors_active
);
13029 encoder
->base
.crtc
= NULL
;
13033 if (crtc
->active
|| HAS_GMCH_DISPLAY(dev
)) {
13035 * We start out with underrun reporting disabled to avoid races.
13036 * For correct bookkeeping mark this on active crtcs.
13038 * Also on gmch platforms we dont have any hardware bits to
13039 * disable the underrun reporting. Which means we need to start
13040 * out with underrun reporting disabled also on inactive pipes,
13041 * since otherwise we'll complain about the garbage we read when
13042 * e.g. coming up after runtime pm.
13044 * No protection against concurrent access is required - at
13045 * worst a fifo underrun happens which also sets this to false.
13047 crtc
->cpu_fifo_underrun_disabled
= true;
13048 crtc
->pch_fifo_underrun_disabled
= true;
13052 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
13054 struct intel_connector
*connector
;
13055 struct drm_device
*dev
= encoder
->base
.dev
;
13057 /* We need to check both for a crtc link (meaning that the
13058 * encoder is active and trying to read from a pipe) and the
13059 * pipe itself being active. */
13060 bool has_active_crtc
= encoder
->base
.crtc
&&
13061 to_intel_crtc(encoder
->base
.crtc
)->active
;
13063 if (encoder
->connectors_active
&& !has_active_crtc
) {
13064 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13065 encoder
->base
.base
.id
,
13066 encoder
->base
.name
);
13068 /* Connector is active, but has no active pipe. This is
13069 * fallout from our resume register restoring. Disable
13070 * the encoder manually again. */
13071 if (encoder
->base
.crtc
) {
13072 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13073 encoder
->base
.base
.id
,
13074 encoder
->base
.name
);
13075 encoder
->disable(encoder
);
13076 if (encoder
->post_disable
)
13077 encoder
->post_disable(encoder
);
13079 encoder
->base
.crtc
= NULL
;
13080 encoder
->connectors_active
= false;
13082 /* Inconsistent output/port/pipe state happens presumably due to
13083 * a bug in one of the get_hw_state functions. Or someplace else
13084 * in our code, like the register restore mess on resume. Clamp
13085 * things to off as a safer default. */
13086 list_for_each_entry(connector
,
13087 &dev
->mode_config
.connector_list
,
13089 if (connector
->encoder
!= encoder
)
13091 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
13092 connector
->base
.encoder
= NULL
;
13095 /* Enabled encoders without active connectors will be fixed in
13096 * the crtc fixup. */
13099 void i915_redisable_vga_power_on(struct drm_device
*dev
)
13101 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13102 u32 vga_reg
= i915_vgacntrl_reg(dev
);
13104 if (!(I915_READ(vga_reg
) & VGA_DISP_DISABLE
)) {
13105 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13106 i915_disable_vga(dev
);
13110 void i915_redisable_vga(struct drm_device
*dev
)
13112 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13114 /* This function can be called both from intel_modeset_setup_hw_state or
13115 * at a very early point in our resume sequence, where the power well
13116 * structures are not yet restored. Since this function is at a very
13117 * paranoid "someone might have enabled VGA while we were not looking"
13118 * level, just check if the power well is enabled instead of trying to
13119 * follow the "don't touch the power well if we don't need it" policy
13120 * the rest of the driver uses. */
13121 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_VGA
))
13124 i915_redisable_vga_power_on(dev
);
13127 static bool primary_get_hw_state(struct intel_crtc
*crtc
)
13129 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
13134 return I915_READ(DSPCNTR(crtc
->plane
)) & DISPLAY_PLANE_ENABLE
;
13137 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
13139 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13141 struct intel_crtc
*crtc
;
13142 struct intel_encoder
*encoder
;
13143 struct intel_connector
*connector
;
13146 for_each_intel_crtc(dev
, crtc
) {
13147 memset(&crtc
->config
, 0, sizeof(crtc
->config
));
13149 crtc
->config
.quirks
|= PIPE_CONFIG_QUIRK_INHERITED_MODE
;
13151 crtc
->active
= dev_priv
->display
.get_pipe_config(crtc
,
13154 crtc
->base
.enabled
= crtc
->active
;
13155 crtc
->primary_enabled
= primary_get_hw_state(crtc
);
13157 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13158 crtc
->base
.base
.id
,
13159 crtc
->active
? "enabled" : "disabled");
13162 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
13163 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
13165 pll
->on
= pll
->get_hw_state(dev_priv
, pll
,
13166 &pll
->config
.hw_state
);
13168 pll
->config
.crtc_mask
= 0;
13169 for_each_intel_crtc(dev
, crtc
) {
13170 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
) {
13172 pll
->config
.crtc_mask
|= 1 << crtc
->pipe
;
13176 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13177 pll
->name
, pll
->config
.crtc_mask
, pll
->on
);
13179 if (pll
->config
.crtc_mask
)
13180 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
13183 for_each_intel_encoder(dev
, encoder
) {
13186 if (encoder
->get_hw_state(encoder
, &pipe
)) {
13187 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
13188 encoder
->base
.crtc
= &crtc
->base
;
13189 encoder
->get_config(encoder
, &crtc
->config
);
13191 encoder
->base
.crtc
= NULL
;
13194 encoder
->connectors_active
= false;
13195 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13196 encoder
->base
.base
.id
,
13197 encoder
->base
.name
,
13198 encoder
->base
.crtc
? "enabled" : "disabled",
13202 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
13204 if (connector
->get_hw_state(connector
)) {
13205 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
13206 connector
->encoder
->connectors_active
= true;
13207 connector
->base
.encoder
= &connector
->encoder
->base
;
13209 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
13210 connector
->base
.encoder
= NULL
;
13212 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13213 connector
->base
.base
.id
,
13214 connector
->base
.name
,
13215 connector
->base
.encoder
? "enabled" : "disabled");
13219 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13220 * and i915 state tracking structures. */
13221 void intel_modeset_setup_hw_state(struct drm_device
*dev
,
13222 bool force_restore
)
13224 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13226 struct intel_crtc
*crtc
;
13227 struct intel_encoder
*encoder
;
13230 intel_modeset_readout_hw_state(dev
);
13233 * Now that we have the config, copy it to each CRTC struct
13234 * Note that this could go away if we move to using crtc_config
13235 * checking everywhere.
13237 for_each_intel_crtc(dev
, crtc
) {
13238 if (crtc
->active
&& i915
.fastboot
) {
13239 intel_mode_from_pipe_config(&crtc
->base
.mode
, &crtc
->config
);
13240 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13241 crtc
->base
.base
.id
);
13242 drm_mode_debug_printmodeline(&crtc
->base
.mode
);
13246 /* HW state is read out, now we need to sanitize this mess. */
13247 for_each_intel_encoder(dev
, encoder
) {
13248 intel_sanitize_encoder(encoder
);
13251 for_each_pipe(dev_priv
, pipe
) {
13252 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
13253 intel_sanitize_crtc(crtc
);
13254 intel_dump_pipe_config(crtc
, &crtc
->config
, "[setup_hw_state]");
13257 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
13258 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
13260 if (!pll
->on
|| pll
->active
)
13263 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll
->name
);
13265 pll
->disable(dev_priv
, pll
);
13269 if (HAS_PCH_SPLIT(dev
))
13270 ilk_wm_get_hw_state(dev
);
13272 if (force_restore
) {
13273 i915_redisable_vga(dev
);
13276 * We need to use raw interfaces for restoring state to avoid
13277 * checking (bogus) intermediate states.
13279 for_each_pipe(dev_priv
, pipe
) {
13280 struct drm_crtc
*crtc
=
13281 dev_priv
->pipe_to_crtc_mapping
[pipe
];
13283 __intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
,
13284 crtc
->primary
->fb
);
13287 intel_modeset_update_staged_output_state(dev
);
13290 intel_modeset_check_state(dev
);
13293 void intel_modeset_gem_init(struct drm_device
*dev
)
13295 struct drm_crtc
*c
;
13296 struct drm_i915_gem_object
*obj
;
13298 mutex_lock(&dev
->struct_mutex
);
13299 intel_init_gt_powersave(dev
);
13300 mutex_unlock(&dev
->struct_mutex
);
13302 intel_modeset_init_hw(dev
);
13304 intel_setup_overlay(dev
);
13307 * Make sure any fbs we allocated at startup are properly
13308 * pinned & fenced. When we do the allocation it's too early
13311 mutex_lock(&dev
->struct_mutex
);
13312 for_each_crtc(dev
, c
) {
13313 obj
= intel_fb_obj(c
->primary
->fb
);
13317 if (intel_pin_and_fence_fb_obj(c
->primary
,
13320 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13321 to_intel_crtc(c
)->pipe
);
13322 drm_framebuffer_unreference(c
->primary
->fb
);
13323 c
->primary
->fb
= NULL
;
13326 mutex_unlock(&dev
->struct_mutex
);
13329 void intel_connector_unregister(struct intel_connector
*intel_connector
)
13331 struct drm_connector
*connector
= &intel_connector
->base
;
13333 intel_panel_destroy_backlight(connector
);
13334 drm_connector_unregister(connector
);
13337 void intel_modeset_cleanup(struct drm_device
*dev
)
13339 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13340 struct drm_connector
*connector
;
13343 * Interrupts and polling as the first thing to avoid creating havoc.
13344 * Too much stuff here (turning of rps, connectors, ...) would
13345 * experience fancy races otherwise.
13347 intel_irq_uninstall(dev_priv
);
13350 * Due to the hpd irq storm handling the hotplug work can re-arm the
13351 * poll handlers. Hence disable polling after hpd handling is shut down.
13353 drm_kms_helper_poll_fini(dev
);
13355 mutex_lock(&dev
->struct_mutex
);
13357 intel_unregister_dsm_handler();
13359 intel_disable_fbc(dev
);
13361 intel_disable_gt_powersave(dev
);
13363 ironlake_teardown_rc6(dev
);
13365 mutex_unlock(&dev
->struct_mutex
);
13367 /* flush any delayed tasks or pending work */
13368 flush_scheduled_work();
13370 /* destroy the backlight and sysfs files before encoders/connectors */
13371 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
13372 struct intel_connector
*intel_connector
;
13374 intel_connector
= to_intel_connector(connector
);
13375 intel_connector
->unregister(intel_connector
);
13378 drm_mode_config_cleanup(dev
);
13380 intel_cleanup_overlay(dev
);
13382 mutex_lock(&dev
->struct_mutex
);
13383 intel_cleanup_gt_powersave(dev
);
13384 mutex_unlock(&dev
->struct_mutex
);
13388 * Return which encoder is currently attached for connector.
13390 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
13392 return &intel_attached_encoder(connector
)->base
;
13395 void intel_connector_attach_encoder(struct intel_connector
*connector
,
13396 struct intel_encoder
*encoder
)
13398 connector
->encoder
= encoder
;
13399 drm_mode_connector_attach_encoder(&connector
->base
,
13404 * set vga decode state - true == enable VGA decode
13406 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
13408 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13409 unsigned reg
= INTEL_INFO(dev
)->gen
>= 6 ? SNB_GMCH_CTRL
: INTEL_GMCH_CTRL
;
13412 if (pci_read_config_word(dev_priv
->bridge_dev
, reg
, &gmch_ctrl
)) {
13413 DRM_ERROR("failed to read control word\n");
13417 if (!!(gmch_ctrl
& INTEL_GMCH_VGA_DISABLE
) == !state
)
13421 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
13423 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
13425 if (pci_write_config_word(dev_priv
->bridge_dev
, reg
, gmch_ctrl
)) {
13426 DRM_ERROR("failed to write control word\n");
13433 struct intel_display_error_state
{
13435 u32 power_well_driver
;
13437 int num_transcoders
;
13439 struct intel_cursor_error_state
{
13444 } cursor
[I915_MAX_PIPES
];
13446 struct intel_pipe_error_state
{
13447 bool power_domain_on
;
13450 } pipe
[I915_MAX_PIPES
];
13452 struct intel_plane_error_state
{
13460 } plane
[I915_MAX_PIPES
];
13462 struct intel_transcoder_error_state
{
13463 bool power_domain_on
;
13464 enum transcoder cpu_transcoder
;
13477 struct intel_display_error_state
*
13478 intel_display_capture_error_state(struct drm_device
*dev
)
13480 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13481 struct intel_display_error_state
*error
;
13482 int transcoders
[] = {
13490 if (INTEL_INFO(dev
)->num_pipes
== 0)
13493 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
13497 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
13498 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_DRIVER
);
13500 for_each_pipe(dev_priv
, i
) {
13501 error
->pipe
[i
].power_domain_on
=
13502 __intel_display_power_is_enabled(dev_priv
,
13503 POWER_DOMAIN_PIPE(i
));
13504 if (!error
->pipe
[i
].power_domain_on
)
13507 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
13508 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
13509 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
13511 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
13512 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
13513 if (INTEL_INFO(dev
)->gen
<= 3) {
13514 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
13515 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
13517 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
13518 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
13519 if (INTEL_INFO(dev
)->gen
>= 4) {
13520 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
13521 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
13524 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
13526 if (HAS_GMCH_DISPLAY(dev
))
13527 error
->pipe
[i
].stat
= I915_READ(PIPESTAT(i
));
13530 error
->num_transcoders
= INTEL_INFO(dev
)->num_pipes
;
13531 if (HAS_DDI(dev_priv
->dev
))
13532 error
->num_transcoders
++; /* Account for eDP. */
13534 for (i
= 0; i
< error
->num_transcoders
; i
++) {
13535 enum transcoder cpu_transcoder
= transcoders
[i
];
13537 error
->transcoder
[i
].power_domain_on
=
13538 __intel_display_power_is_enabled(dev_priv
,
13539 POWER_DOMAIN_TRANSCODER(cpu_transcoder
));
13540 if (!error
->transcoder
[i
].power_domain_on
)
13543 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
13545 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
13546 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
13547 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
13548 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
13549 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
13550 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
13551 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
13557 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13560 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
13561 struct drm_device
*dev
,
13562 struct intel_display_error_state
*error
)
13564 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13570 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
13571 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
13572 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
13573 error
->power_well_driver
);
13574 for_each_pipe(dev_priv
, i
) {
13575 err_printf(m
, "Pipe [%d]:\n", i
);
13576 err_printf(m
, " Power: %s\n",
13577 error
->pipe
[i
].power_domain_on
? "on" : "off");
13578 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
13579 err_printf(m
, " STAT: %08x\n", error
->pipe
[i
].stat
);
13581 err_printf(m
, "Plane [%d]:\n", i
);
13582 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
13583 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
13584 if (INTEL_INFO(dev
)->gen
<= 3) {
13585 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
13586 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
13588 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
13589 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
13590 if (INTEL_INFO(dev
)->gen
>= 4) {
13591 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
13592 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
13595 err_printf(m
, "Cursor [%d]:\n", i
);
13596 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
13597 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
13598 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
13601 for (i
= 0; i
< error
->num_transcoders
; i
++) {
13602 err_printf(m
, "CPU transcoder: %c\n",
13603 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
13604 err_printf(m
, " Power: %s\n",
13605 error
->transcoder
[i
].power_domain_on
? "on" : "off");
13606 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
13607 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
13608 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
13609 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
13610 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
13611 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
13612 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);
13616 void intel_modeset_preclose(struct drm_device
*dev
, struct drm_file
*file
)
13618 struct intel_crtc
*crtc
;
13620 for_each_intel_crtc(dev
, crtc
) {
13621 struct intel_unpin_work
*work
;
13623 spin_lock_irq(&dev
->event_lock
);
13625 work
= crtc
->unpin_work
;
13627 if (work
&& work
->event
&&
13628 work
->event
->base
.file_priv
== file
) {
13629 kfree(work
->event
);
13630 work
->event
= NULL
;
13633 spin_unlock_irq(&dev
->event_lock
);