2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
);
45 static void intel_increase_pllclock(struct drm_crtc
*crtc
);
46 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
48 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
49 struct intel_crtc_config
*pipe_config
);
50 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
51 struct intel_crtc_config
*pipe_config
);
53 static int intel_set_mode(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
54 int x
, int y
, struct drm_framebuffer
*old_fb
);
66 typedef struct intel_limit intel_limit_t
;
68 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
73 intel_pch_rawclk(struct drm_device
*dev
)
75 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
77 WARN_ON(!HAS_PCH_SPLIT(dev
));
79 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
82 static inline u32
/* units of 100MHz */
83 intel_fdi_link_freq(struct drm_device
*dev
)
86 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
87 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
92 static const intel_limit_t intel_limits_i8xx_dac
= {
93 .dot
= { .min
= 25000, .max
= 350000 },
94 .vco
= { .min
= 930000, .max
= 1400000 },
95 .n
= { .min
= 3, .max
= 16 },
96 .m
= { .min
= 96, .max
= 140 },
97 .m1
= { .min
= 18, .max
= 26 },
98 .m2
= { .min
= 6, .max
= 16 },
99 .p
= { .min
= 4, .max
= 128 },
100 .p1
= { .min
= 2, .max
= 33 },
101 .p2
= { .dot_limit
= 165000,
102 .p2_slow
= 4, .p2_fast
= 2 },
105 static const intel_limit_t intel_limits_i8xx_dvo
= {
106 .dot
= { .min
= 25000, .max
= 350000 },
107 .vco
= { .min
= 930000, .max
= 1400000 },
108 .n
= { .min
= 3, .max
= 16 },
109 .m
= { .min
= 96, .max
= 140 },
110 .m1
= { .min
= 18, .max
= 26 },
111 .m2
= { .min
= 6, .max
= 16 },
112 .p
= { .min
= 4, .max
= 128 },
113 .p1
= { .min
= 2, .max
= 33 },
114 .p2
= { .dot_limit
= 165000,
115 .p2_slow
= 4, .p2_fast
= 4 },
118 static const intel_limit_t intel_limits_i8xx_lvds
= {
119 .dot
= { .min
= 25000, .max
= 350000 },
120 .vco
= { .min
= 930000, .max
= 1400000 },
121 .n
= { .min
= 3, .max
= 16 },
122 .m
= { .min
= 96, .max
= 140 },
123 .m1
= { .min
= 18, .max
= 26 },
124 .m2
= { .min
= 6, .max
= 16 },
125 .p
= { .min
= 4, .max
= 128 },
126 .p1
= { .min
= 1, .max
= 6 },
127 .p2
= { .dot_limit
= 165000,
128 .p2_slow
= 14, .p2_fast
= 7 },
131 static const intel_limit_t intel_limits_i9xx_sdvo
= {
132 .dot
= { .min
= 20000, .max
= 400000 },
133 .vco
= { .min
= 1400000, .max
= 2800000 },
134 .n
= { .min
= 1, .max
= 6 },
135 .m
= { .min
= 70, .max
= 120 },
136 .m1
= { .min
= 8, .max
= 18 },
137 .m2
= { .min
= 3, .max
= 7 },
138 .p
= { .min
= 5, .max
= 80 },
139 .p1
= { .min
= 1, .max
= 8 },
140 .p2
= { .dot_limit
= 200000,
141 .p2_slow
= 10, .p2_fast
= 5 },
144 static const intel_limit_t intel_limits_i9xx_lvds
= {
145 .dot
= { .min
= 20000, .max
= 400000 },
146 .vco
= { .min
= 1400000, .max
= 2800000 },
147 .n
= { .min
= 1, .max
= 6 },
148 .m
= { .min
= 70, .max
= 120 },
149 .m1
= { .min
= 8, .max
= 18 },
150 .m2
= { .min
= 3, .max
= 7 },
151 .p
= { .min
= 7, .max
= 98 },
152 .p1
= { .min
= 1, .max
= 8 },
153 .p2
= { .dot_limit
= 112000,
154 .p2_slow
= 14, .p2_fast
= 7 },
158 static const intel_limit_t intel_limits_g4x_sdvo
= {
159 .dot
= { .min
= 25000, .max
= 270000 },
160 .vco
= { .min
= 1750000, .max
= 3500000},
161 .n
= { .min
= 1, .max
= 4 },
162 .m
= { .min
= 104, .max
= 138 },
163 .m1
= { .min
= 17, .max
= 23 },
164 .m2
= { .min
= 5, .max
= 11 },
165 .p
= { .min
= 10, .max
= 30 },
166 .p1
= { .min
= 1, .max
= 3},
167 .p2
= { .dot_limit
= 270000,
173 static const intel_limit_t intel_limits_g4x_hdmi
= {
174 .dot
= { .min
= 22000, .max
= 400000 },
175 .vco
= { .min
= 1750000, .max
= 3500000},
176 .n
= { .min
= 1, .max
= 4 },
177 .m
= { .min
= 104, .max
= 138 },
178 .m1
= { .min
= 16, .max
= 23 },
179 .m2
= { .min
= 5, .max
= 11 },
180 .p
= { .min
= 5, .max
= 80 },
181 .p1
= { .min
= 1, .max
= 8},
182 .p2
= { .dot_limit
= 165000,
183 .p2_slow
= 10, .p2_fast
= 5 },
186 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
187 .dot
= { .min
= 20000, .max
= 115000 },
188 .vco
= { .min
= 1750000, .max
= 3500000 },
189 .n
= { .min
= 1, .max
= 3 },
190 .m
= { .min
= 104, .max
= 138 },
191 .m1
= { .min
= 17, .max
= 23 },
192 .m2
= { .min
= 5, .max
= 11 },
193 .p
= { .min
= 28, .max
= 112 },
194 .p1
= { .min
= 2, .max
= 8 },
195 .p2
= { .dot_limit
= 0,
196 .p2_slow
= 14, .p2_fast
= 14
200 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
201 .dot
= { .min
= 80000, .max
= 224000 },
202 .vco
= { .min
= 1750000, .max
= 3500000 },
203 .n
= { .min
= 1, .max
= 3 },
204 .m
= { .min
= 104, .max
= 138 },
205 .m1
= { .min
= 17, .max
= 23 },
206 .m2
= { .min
= 5, .max
= 11 },
207 .p
= { .min
= 14, .max
= 42 },
208 .p1
= { .min
= 2, .max
= 6 },
209 .p2
= { .dot_limit
= 0,
210 .p2_slow
= 7, .p2_fast
= 7
214 static const intel_limit_t intel_limits_pineview_sdvo
= {
215 .dot
= { .min
= 20000, .max
= 400000},
216 .vco
= { .min
= 1700000, .max
= 3500000 },
217 /* Pineview's Ncounter is a ring counter */
218 .n
= { .min
= 3, .max
= 6 },
219 .m
= { .min
= 2, .max
= 256 },
220 /* Pineview only has one combined m divider, which we treat as m2. */
221 .m1
= { .min
= 0, .max
= 0 },
222 .m2
= { .min
= 0, .max
= 254 },
223 .p
= { .min
= 5, .max
= 80 },
224 .p1
= { .min
= 1, .max
= 8 },
225 .p2
= { .dot_limit
= 200000,
226 .p2_slow
= 10, .p2_fast
= 5 },
229 static const intel_limit_t intel_limits_pineview_lvds
= {
230 .dot
= { .min
= 20000, .max
= 400000 },
231 .vco
= { .min
= 1700000, .max
= 3500000 },
232 .n
= { .min
= 3, .max
= 6 },
233 .m
= { .min
= 2, .max
= 256 },
234 .m1
= { .min
= 0, .max
= 0 },
235 .m2
= { .min
= 0, .max
= 254 },
236 .p
= { .min
= 7, .max
= 112 },
237 .p1
= { .min
= 1, .max
= 8 },
238 .p2
= { .dot_limit
= 112000,
239 .p2_slow
= 14, .p2_fast
= 14 },
242 /* Ironlake / Sandybridge
244 * We calculate clock using (register_value + 2) for N/M1/M2, so here
245 * the range value for them is (actual_value - 2).
247 static const intel_limit_t intel_limits_ironlake_dac
= {
248 .dot
= { .min
= 25000, .max
= 350000 },
249 .vco
= { .min
= 1760000, .max
= 3510000 },
250 .n
= { .min
= 1, .max
= 5 },
251 .m
= { .min
= 79, .max
= 127 },
252 .m1
= { .min
= 12, .max
= 22 },
253 .m2
= { .min
= 5, .max
= 9 },
254 .p
= { .min
= 5, .max
= 80 },
255 .p1
= { .min
= 1, .max
= 8 },
256 .p2
= { .dot_limit
= 225000,
257 .p2_slow
= 10, .p2_fast
= 5 },
260 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
261 .dot
= { .min
= 25000, .max
= 350000 },
262 .vco
= { .min
= 1760000, .max
= 3510000 },
263 .n
= { .min
= 1, .max
= 3 },
264 .m
= { .min
= 79, .max
= 118 },
265 .m1
= { .min
= 12, .max
= 22 },
266 .m2
= { .min
= 5, .max
= 9 },
267 .p
= { .min
= 28, .max
= 112 },
268 .p1
= { .min
= 2, .max
= 8 },
269 .p2
= { .dot_limit
= 225000,
270 .p2_slow
= 14, .p2_fast
= 14 },
273 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
274 .dot
= { .min
= 25000, .max
= 350000 },
275 .vco
= { .min
= 1760000, .max
= 3510000 },
276 .n
= { .min
= 1, .max
= 3 },
277 .m
= { .min
= 79, .max
= 127 },
278 .m1
= { .min
= 12, .max
= 22 },
279 .m2
= { .min
= 5, .max
= 9 },
280 .p
= { .min
= 14, .max
= 56 },
281 .p1
= { .min
= 2, .max
= 8 },
282 .p2
= { .dot_limit
= 225000,
283 .p2_slow
= 7, .p2_fast
= 7 },
286 /* LVDS 100mhz refclk limits. */
287 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
288 .dot
= { .min
= 25000, .max
= 350000 },
289 .vco
= { .min
= 1760000, .max
= 3510000 },
290 .n
= { .min
= 1, .max
= 2 },
291 .m
= { .min
= 79, .max
= 126 },
292 .m1
= { .min
= 12, .max
= 22 },
293 .m2
= { .min
= 5, .max
= 9 },
294 .p
= { .min
= 28, .max
= 112 },
295 .p1
= { .min
= 2, .max
= 8 },
296 .p2
= { .dot_limit
= 225000,
297 .p2_slow
= 14, .p2_fast
= 14 },
300 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
301 .dot
= { .min
= 25000, .max
= 350000 },
302 .vco
= { .min
= 1760000, .max
= 3510000 },
303 .n
= { .min
= 1, .max
= 3 },
304 .m
= { .min
= 79, .max
= 126 },
305 .m1
= { .min
= 12, .max
= 22 },
306 .m2
= { .min
= 5, .max
= 9 },
307 .p
= { .min
= 14, .max
= 42 },
308 .p1
= { .min
= 2, .max
= 6 },
309 .p2
= { .dot_limit
= 225000,
310 .p2_slow
= 7, .p2_fast
= 7 },
313 static const intel_limit_t intel_limits_vlv_dac
= {
314 .dot
= { .min
= 25000, .max
= 270000 },
315 .vco
= { .min
= 4000000, .max
= 6000000 },
316 .n
= { .min
= 1, .max
= 7 },
317 .m
= { .min
= 22, .max
= 450 }, /* guess */
318 .m1
= { .min
= 2, .max
= 3 },
319 .m2
= { .min
= 11, .max
= 156 },
320 .p
= { .min
= 10, .max
= 30 },
321 .p1
= { .min
= 1, .max
= 3 },
322 .p2
= { .dot_limit
= 270000,
323 .p2_slow
= 2, .p2_fast
= 20 },
326 static const intel_limit_t intel_limits_vlv_hdmi
= {
327 .dot
= { .min
= 25000, .max
= 270000 },
328 .vco
= { .min
= 4000000, .max
= 6000000 },
329 .n
= { .min
= 1, .max
= 7 },
330 .m
= { .min
= 60, .max
= 300 }, /* guess */
331 .m1
= { .min
= 2, .max
= 3 },
332 .m2
= { .min
= 11, .max
= 156 },
333 .p
= { .min
= 10, .max
= 30 },
334 .p1
= { .min
= 2, .max
= 3 },
335 .p2
= { .dot_limit
= 270000,
336 .p2_slow
= 2, .p2_fast
= 20 },
339 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
,
342 struct drm_device
*dev
= crtc
->dev
;
343 const intel_limit_t
*limit
;
345 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
346 if (intel_is_dual_link_lvds(dev
)) {
347 if (refclk
== 100000)
348 limit
= &intel_limits_ironlake_dual_lvds_100m
;
350 limit
= &intel_limits_ironlake_dual_lvds
;
352 if (refclk
== 100000)
353 limit
= &intel_limits_ironlake_single_lvds_100m
;
355 limit
= &intel_limits_ironlake_single_lvds
;
358 limit
= &intel_limits_ironlake_dac
;
363 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
365 struct drm_device
*dev
= crtc
->dev
;
366 const intel_limit_t
*limit
;
368 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
369 if (intel_is_dual_link_lvds(dev
))
370 limit
= &intel_limits_g4x_dual_channel_lvds
;
372 limit
= &intel_limits_g4x_single_channel_lvds
;
373 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
374 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
375 limit
= &intel_limits_g4x_hdmi
;
376 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
377 limit
= &intel_limits_g4x_sdvo
;
378 } else /* The option is for other outputs */
379 limit
= &intel_limits_i9xx_sdvo
;
384 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
, int refclk
)
386 struct drm_device
*dev
= crtc
->dev
;
387 const intel_limit_t
*limit
;
389 if (HAS_PCH_SPLIT(dev
))
390 limit
= intel_ironlake_limit(crtc
, refclk
);
391 else if (IS_G4X(dev
)) {
392 limit
= intel_g4x_limit(crtc
);
393 } else if (IS_PINEVIEW(dev
)) {
394 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
395 limit
= &intel_limits_pineview_lvds
;
397 limit
= &intel_limits_pineview_sdvo
;
398 } else if (IS_VALLEYVIEW(dev
)) {
399 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
))
400 limit
= &intel_limits_vlv_dac
;
402 limit
= &intel_limits_vlv_hdmi
;
403 } else if (!IS_GEN2(dev
)) {
404 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
405 limit
= &intel_limits_i9xx_lvds
;
407 limit
= &intel_limits_i9xx_sdvo
;
409 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
410 limit
= &intel_limits_i8xx_lvds
;
411 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
))
412 limit
= &intel_limits_i8xx_dvo
;
414 limit
= &intel_limits_i8xx_dac
;
419 /* m1 is reserved as 0 in Pineview, n is a ring counter */
420 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
422 clock
->m
= clock
->m2
+ 2;
423 clock
->p
= clock
->p1
* clock
->p2
;
424 clock
->vco
= refclk
* clock
->m
/ clock
->n
;
425 clock
->dot
= clock
->vco
/ clock
->p
;
428 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
430 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
433 static void i9xx_clock(int refclk
, intel_clock_t
*clock
)
435 clock
->m
= i9xx_dpll_compute_m(clock
);
436 clock
->p
= clock
->p1
* clock
->p2
;
437 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
438 clock
->dot
= clock
->vco
/ clock
->p
;
442 * Returns whether any output on the specified pipe is of the specified type
444 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
446 struct drm_device
*dev
= crtc
->dev
;
447 struct intel_encoder
*encoder
;
449 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
450 if (encoder
->type
== type
)
456 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
458 * Returns whether the given set of divisors are valid for a given refclk with
459 * the given connectors.
462 static bool intel_PLL_is_valid(struct drm_device
*dev
,
463 const intel_limit_t
*limit
,
464 const intel_clock_t
*clock
)
466 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
467 INTELPllInvalid("p1 out of range\n");
468 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
469 INTELPllInvalid("p out of range\n");
470 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
471 INTELPllInvalid("m2 out of range\n");
472 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
473 INTELPllInvalid("m1 out of range\n");
474 if (clock
->m1
<= clock
->m2
&& !IS_PINEVIEW(dev
))
475 INTELPllInvalid("m1 <= m2\n");
476 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
477 INTELPllInvalid("m out of range\n");
478 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
479 INTELPllInvalid("n out of range\n");
480 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
481 INTELPllInvalid("vco out of range\n");
482 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
483 * connector, etc., rather than just a single range.
485 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
486 INTELPllInvalid("dot out of range\n");
492 i9xx_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
493 int target
, int refclk
, intel_clock_t
*match_clock
,
494 intel_clock_t
*best_clock
)
496 struct drm_device
*dev
= crtc
->dev
;
500 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
502 * For LVDS just rely on its current settings for dual-channel.
503 * We haven't figured out how to reliably set up different
504 * single/dual channel state, if we even can.
506 if (intel_is_dual_link_lvds(dev
))
507 clock
.p2
= limit
->p2
.p2_fast
;
509 clock
.p2
= limit
->p2
.p2_slow
;
511 if (target
< limit
->p2
.dot_limit
)
512 clock
.p2
= limit
->p2
.p2_slow
;
514 clock
.p2
= limit
->p2
.p2_fast
;
517 memset(best_clock
, 0, sizeof(*best_clock
));
519 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
521 for (clock
.m2
= limit
->m2
.min
;
522 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
523 if (clock
.m2
>= clock
.m1
)
525 for (clock
.n
= limit
->n
.min
;
526 clock
.n
<= limit
->n
.max
; clock
.n
++) {
527 for (clock
.p1
= limit
->p1
.min
;
528 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
531 i9xx_clock(refclk
, &clock
);
532 if (!intel_PLL_is_valid(dev
, limit
,
536 clock
.p
!= match_clock
->p
)
539 this_err
= abs(clock
.dot
- target
);
540 if (this_err
< err
) {
549 return (err
!= target
);
553 pnv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
554 int target
, int refclk
, intel_clock_t
*match_clock
,
555 intel_clock_t
*best_clock
)
557 struct drm_device
*dev
= crtc
->dev
;
561 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
563 * For LVDS just rely on its current settings for dual-channel.
564 * We haven't figured out how to reliably set up different
565 * single/dual channel state, if we even can.
567 if (intel_is_dual_link_lvds(dev
))
568 clock
.p2
= limit
->p2
.p2_fast
;
570 clock
.p2
= limit
->p2
.p2_slow
;
572 if (target
< limit
->p2
.dot_limit
)
573 clock
.p2
= limit
->p2
.p2_slow
;
575 clock
.p2
= limit
->p2
.p2_fast
;
578 memset(best_clock
, 0, sizeof(*best_clock
));
580 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
582 for (clock
.m2
= limit
->m2
.min
;
583 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
584 for (clock
.n
= limit
->n
.min
;
585 clock
.n
<= limit
->n
.max
; clock
.n
++) {
586 for (clock
.p1
= limit
->p1
.min
;
587 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
590 pineview_clock(refclk
, &clock
);
591 if (!intel_PLL_is_valid(dev
, limit
,
595 clock
.p
!= match_clock
->p
)
598 this_err
= abs(clock
.dot
- target
);
599 if (this_err
< err
) {
608 return (err
!= target
);
612 g4x_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
613 int target
, int refclk
, intel_clock_t
*match_clock
,
614 intel_clock_t
*best_clock
)
616 struct drm_device
*dev
= crtc
->dev
;
620 /* approximately equals target * 0.00585 */
621 int err_most
= (target
>> 8) + (target
>> 9);
624 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
625 if (intel_is_dual_link_lvds(dev
))
626 clock
.p2
= limit
->p2
.p2_fast
;
628 clock
.p2
= limit
->p2
.p2_slow
;
630 if (target
< limit
->p2
.dot_limit
)
631 clock
.p2
= limit
->p2
.p2_slow
;
633 clock
.p2
= limit
->p2
.p2_fast
;
636 memset(best_clock
, 0, sizeof(*best_clock
));
637 max_n
= limit
->n
.max
;
638 /* based on hardware requirement, prefer smaller n to precision */
639 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
640 /* based on hardware requirement, prefere larger m1,m2 */
641 for (clock
.m1
= limit
->m1
.max
;
642 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
643 for (clock
.m2
= limit
->m2
.max
;
644 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
645 for (clock
.p1
= limit
->p1
.max
;
646 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
649 i9xx_clock(refclk
, &clock
);
650 if (!intel_PLL_is_valid(dev
, limit
,
654 this_err
= abs(clock
.dot
- target
);
655 if (this_err
< err_most
) {
669 vlv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
670 int target
, int refclk
, intel_clock_t
*match_clock
,
671 intel_clock_t
*best_clock
)
673 u32 p1
, p2
, m1
, m2
, vco
, bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
675 u32 updrate
, minupdate
, p
;
676 unsigned long bestppm
, ppm
, absppm
;
680 dotclk
= target
* 1000;
683 fastclk
= dotclk
/ (2*100);
686 n
= p
= p1
= p2
= m
= m1
= m2
= vco
= bestn
= 0;
687 bestm1
= bestm2
= bestp1
= bestp2
= 0;
689 /* based on hardware requirement, prefer smaller n to precision */
690 for (n
= limit
->n
.min
; n
<= ((refclk
) / minupdate
); n
++) {
691 updrate
= refclk
/ n
;
692 for (p1
= limit
->p1
.max
; p1
> limit
->p1
.min
; p1
--) {
693 for (p2
= limit
->p2
.p2_fast
+1; p2
> 0; p2
--) {
697 /* based on hardware requirement, prefer bigger m1,m2 values */
698 for (m1
= limit
->m1
.min
; m1
<= limit
->m1
.max
; m1
++) {
699 m2
= (((2*(fastclk
* p
* n
/ m1
)) +
700 refclk
) / (2*refclk
));
703 if (vco
>= limit
->vco
.min
&& vco
< limit
->vco
.max
) {
704 ppm
= 1000000 * ((vco
/ p
) - fastclk
) / fastclk
;
705 absppm
= (ppm
> 0) ? ppm
: (-ppm
);
706 if (absppm
< 100 && ((p1
* p2
) > (bestp1
* bestp2
))) {
710 if (absppm
< bestppm
- 10) {
727 best_clock
->n
= bestn
;
728 best_clock
->m1
= bestm1
;
729 best_clock
->m2
= bestm2
;
730 best_clock
->p1
= bestp1
;
731 best_clock
->p2
= bestp2
;
736 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
739 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
740 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
742 return intel_crtc
->config
.cpu_transcoder
;
745 static void ironlake_wait_for_vblank(struct drm_device
*dev
, int pipe
)
747 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
748 u32 frame
, frame_reg
= PIPEFRAME(pipe
);
750 frame
= I915_READ(frame_reg
);
752 if (wait_for(I915_READ_NOTRACE(frame_reg
) != frame
, 50))
753 DRM_DEBUG_KMS("vblank wait timed out\n");
757 * intel_wait_for_vblank - wait for vblank on a given pipe
759 * @pipe: pipe to wait for
761 * Wait for vblank to occur on a given pipe. Needed for various bits of
764 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
766 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
767 int pipestat_reg
= PIPESTAT(pipe
);
769 if (INTEL_INFO(dev
)->gen
>= 5) {
770 ironlake_wait_for_vblank(dev
, pipe
);
774 /* Clear existing vblank status. Note this will clear any other
775 * sticky status fields as well.
777 * This races with i915_driver_irq_handler() with the result
778 * that either function could miss a vblank event. Here it is not
779 * fatal, as we will either wait upon the next vblank interrupt or
780 * timeout. Generally speaking intel_wait_for_vblank() is only
781 * called during modeset at which time the GPU should be idle and
782 * should *not* be performing page flips and thus not waiting on
784 * Currently, the result of us stealing a vblank from the irq
785 * handler is that a single frame will be skipped during swapbuffers.
787 I915_WRITE(pipestat_reg
,
788 I915_READ(pipestat_reg
) | PIPE_VBLANK_INTERRUPT_STATUS
);
790 /* Wait for vblank interrupt bit to set */
791 if (wait_for(I915_READ(pipestat_reg
) &
792 PIPE_VBLANK_INTERRUPT_STATUS
,
794 DRM_DEBUG_KMS("vblank wait timed out\n");
798 * intel_wait_for_pipe_off - wait for pipe to turn off
800 * @pipe: pipe to wait for
802 * After disabling a pipe, we can't wait for vblank in the usual way,
803 * spinning on the vblank interrupt status bit, since we won't actually
804 * see an interrupt when the pipe is disabled.
807 * wait for the pipe register state bit to turn off
810 * wait for the display line value to settle (it usually
811 * ends up stopping at the start of the next frame).
814 void intel_wait_for_pipe_off(struct drm_device
*dev
, int pipe
)
816 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
817 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
820 if (INTEL_INFO(dev
)->gen
>= 4) {
821 int reg
= PIPECONF(cpu_transcoder
);
823 /* Wait for the Pipe State to go off */
824 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
826 WARN(1, "pipe_off wait timed out\n");
828 u32 last_line
, line_mask
;
829 int reg
= PIPEDSL(pipe
);
830 unsigned long timeout
= jiffies
+ msecs_to_jiffies(100);
833 line_mask
= DSL_LINEMASK_GEN2
;
835 line_mask
= DSL_LINEMASK_GEN3
;
837 /* Wait for the display line to settle */
839 last_line
= I915_READ(reg
) & line_mask
;
841 } while (((I915_READ(reg
) & line_mask
) != last_line
) &&
842 time_after(timeout
, jiffies
));
843 if (time_after(jiffies
, timeout
))
844 WARN(1, "pipe_off wait timed out\n");
849 * ibx_digital_port_connected - is the specified port connected?
850 * @dev_priv: i915 private structure
851 * @port: the port to test
853 * Returns true if @port is connected, false otherwise.
855 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
856 struct intel_digital_port
*port
)
860 if (HAS_PCH_IBX(dev_priv
->dev
)) {
863 bit
= SDE_PORTB_HOTPLUG
;
866 bit
= SDE_PORTC_HOTPLUG
;
869 bit
= SDE_PORTD_HOTPLUG
;
877 bit
= SDE_PORTB_HOTPLUG_CPT
;
880 bit
= SDE_PORTC_HOTPLUG_CPT
;
883 bit
= SDE_PORTD_HOTPLUG_CPT
;
890 return I915_READ(SDEISR
) & bit
;
893 static const char *state_string(bool enabled
)
895 return enabled
? "on" : "off";
898 /* Only for pre-ILK configs */
899 void assert_pll(struct drm_i915_private
*dev_priv
,
900 enum pipe pipe
, bool state
)
907 val
= I915_READ(reg
);
908 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
909 WARN(cur_state
!= state
,
910 "PLL state assertion failure (expected %s, current %s)\n",
911 state_string(state
), state_string(cur_state
));
914 /* XXX: the dsi pll is shared between MIPI DSI ports */
915 static void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
920 mutex_lock(&dev_priv
->dpio_lock
);
921 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
922 mutex_unlock(&dev_priv
->dpio_lock
);
924 cur_state
= val
& DSI_PLL_VCO_EN
;
925 WARN(cur_state
!= state
,
926 "DSI PLL state assertion failure (expected %s, current %s)\n",
927 state_string(state
), state_string(cur_state
));
929 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
930 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
932 struct intel_shared_dpll
*
933 intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
)
935 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
937 if (crtc
->config
.shared_dpll
< 0)
940 return &dev_priv
->shared_dplls
[crtc
->config
.shared_dpll
];
944 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
945 struct intel_shared_dpll
*pll
,
949 struct intel_dpll_hw_state hw_state
;
951 if (HAS_PCH_LPT(dev_priv
->dev
)) {
952 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
957 "asserting DPLL %s with no DPLL\n", state_string(state
)))
960 cur_state
= pll
->get_hw_state(dev_priv
, pll
, &hw_state
);
961 WARN(cur_state
!= state
,
962 "%s assertion failure (expected %s, current %s)\n",
963 pll
->name
, state_string(state
), state_string(cur_state
));
966 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
967 enum pipe pipe
, bool state
)
972 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
975 if (HAS_DDI(dev_priv
->dev
)) {
976 /* DDI does not have a specific FDI_TX register */
977 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
978 val
= I915_READ(reg
);
979 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
981 reg
= FDI_TX_CTL(pipe
);
982 val
= I915_READ(reg
);
983 cur_state
= !!(val
& FDI_TX_ENABLE
);
985 WARN(cur_state
!= state
,
986 "FDI TX state assertion failure (expected %s, current %s)\n",
987 state_string(state
), state_string(cur_state
));
989 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
990 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
992 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
993 enum pipe pipe
, bool state
)
999 reg
= FDI_RX_CTL(pipe
);
1000 val
= I915_READ(reg
);
1001 cur_state
= !!(val
& FDI_RX_ENABLE
);
1002 WARN(cur_state
!= state
,
1003 "FDI RX state assertion failure (expected %s, current %s)\n",
1004 state_string(state
), state_string(cur_state
));
1006 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1007 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1009 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1015 /* ILK FDI PLL is always enabled */
1016 if (dev_priv
->info
->gen
== 5)
1019 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1020 if (HAS_DDI(dev_priv
->dev
))
1023 reg
= FDI_TX_CTL(pipe
);
1024 val
= I915_READ(reg
);
1025 WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1028 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1029 enum pipe pipe
, bool state
)
1035 reg
= FDI_RX_CTL(pipe
);
1036 val
= I915_READ(reg
);
1037 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1038 WARN(cur_state
!= state
,
1039 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1040 state_string(state
), state_string(cur_state
));
1043 static void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1046 int pp_reg
, lvds_reg
;
1048 enum pipe panel_pipe
= PIPE_A
;
1051 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
1052 pp_reg
= PCH_PP_CONTROL
;
1053 lvds_reg
= PCH_LVDS
;
1055 pp_reg
= PP_CONTROL
;
1059 val
= I915_READ(pp_reg
);
1060 if (!(val
& PANEL_POWER_ON
) ||
1061 ((val
& PANEL_UNLOCK_REGS
) == PANEL_UNLOCK_REGS
))
1064 if (I915_READ(lvds_reg
) & LVDS_PIPEB_SELECT
)
1065 panel_pipe
= PIPE_B
;
1067 WARN(panel_pipe
== pipe
&& locked
,
1068 "panel assertion failure, pipe %c regs locked\n",
1072 static void assert_cursor(struct drm_i915_private
*dev_priv
,
1073 enum pipe pipe
, bool state
)
1075 struct drm_device
*dev
= dev_priv
->dev
;
1078 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
1079 cur_state
= I915_READ(CURCNTR_IVB(pipe
)) & CURSOR_MODE
;
1080 else if (IS_845G(dev
) || IS_I865G(dev
))
1081 cur_state
= I915_READ(_CURACNTR
) & CURSOR_ENABLE
;
1083 cur_state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
1085 WARN(cur_state
!= state
,
1086 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1087 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1089 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1090 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1092 void assert_pipe(struct drm_i915_private
*dev_priv
,
1093 enum pipe pipe
, bool state
)
1098 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1101 /* if we need the pipe A quirk it must be always on */
1102 if (pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
1105 if (!intel_display_power_enabled(dev_priv
->dev
,
1106 POWER_DOMAIN_TRANSCODER(cpu_transcoder
))) {
1109 reg
= PIPECONF(cpu_transcoder
);
1110 val
= I915_READ(reg
);
1111 cur_state
= !!(val
& PIPECONF_ENABLE
);
1114 WARN(cur_state
!= state
,
1115 "pipe %c assertion failure (expected %s, current %s)\n",
1116 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1119 static void assert_plane(struct drm_i915_private
*dev_priv
,
1120 enum plane plane
, bool state
)
1126 reg
= DSPCNTR(plane
);
1127 val
= I915_READ(reg
);
1128 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1129 WARN(cur_state
!= state
,
1130 "plane %c assertion failure (expected %s, current %s)\n",
1131 plane_name(plane
), state_string(state
), state_string(cur_state
));
1134 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1135 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1137 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1140 struct drm_device
*dev
= dev_priv
->dev
;
1145 /* Primary planes are fixed to pipes on gen4+ */
1146 if (INTEL_INFO(dev
)->gen
>= 4) {
1147 reg
= DSPCNTR(pipe
);
1148 val
= I915_READ(reg
);
1149 WARN((val
& DISPLAY_PLANE_ENABLE
),
1150 "plane %c assertion failure, should be disabled but not\n",
1155 /* Need to check both planes against the pipe */
1158 val
= I915_READ(reg
);
1159 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1160 DISPPLANE_SEL_PIPE_SHIFT
;
1161 WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1162 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1163 plane_name(i
), pipe_name(pipe
));
1167 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1170 struct drm_device
*dev
= dev_priv
->dev
;
1174 if (IS_VALLEYVIEW(dev
)) {
1175 for (i
= 0; i
< dev_priv
->num_plane
; i
++) {
1176 reg
= SPCNTR(pipe
, i
);
1177 val
= I915_READ(reg
);
1178 WARN((val
& SP_ENABLE
),
1179 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1180 sprite_name(pipe
, i
), pipe_name(pipe
));
1182 } else if (INTEL_INFO(dev
)->gen
>= 7) {
1184 val
= I915_READ(reg
);
1185 WARN((val
& SPRITE_ENABLE
),
1186 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1187 plane_name(pipe
), pipe_name(pipe
));
1188 } else if (INTEL_INFO(dev
)->gen
>= 5) {
1189 reg
= DVSCNTR(pipe
);
1190 val
= I915_READ(reg
);
1191 WARN((val
& DVS_ENABLE
),
1192 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1193 plane_name(pipe
), pipe_name(pipe
));
1197 static void assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1202 if (HAS_PCH_LPT(dev_priv
->dev
)) {
1203 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1207 val
= I915_READ(PCH_DREF_CONTROL
);
1208 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1209 DREF_SUPERSPREAD_SOURCE_MASK
));
1210 WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1213 static void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1220 reg
= PCH_TRANSCONF(pipe
);
1221 val
= I915_READ(reg
);
1222 enabled
= !!(val
& TRANS_ENABLE
);
1224 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1228 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1229 enum pipe pipe
, u32 port_sel
, u32 val
)
1231 if ((val
& DP_PORT_EN
) == 0)
1234 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1235 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1236 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1237 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1240 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1246 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1247 enum pipe pipe
, u32 val
)
1249 if ((val
& SDVO_ENABLE
) == 0)
1252 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1253 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1256 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1262 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1263 enum pipe pipe
, u32 val
)
1265 if ((val
& LVDS_PORT_EN
) == 0)
1268 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1269 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1272 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1278 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1279 enum pipe pipe
, u32 val
)
1281 if ((val
& ADPA_DAC_ENABLE
) == 0)
1283 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1284 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1287 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1293 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1294 enum pipe pipe
, int reg
, u32 port_sel
)
1296 u32 val
= I915_READ(reg
);
1297 WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1298 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1299 reg
, pipe_name(pipe
));
1301 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1302 && (val
& DP_PIPEB_SELECT
),
1303 "IBX PCH dp port still using transcoder B\n");
1306 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1307 enum pipe pipe
, int reg
)
1309 u32 val
= I915_READ(reg
);
1310 WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1311 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1312 reg
, pipe_name(pipe
));
1314 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_ENABLE
) == 0
1315 && (val
& SDVO_PIPE_B_SELECT
),
1316 "IBX PCH hdmi port still using transcoder B\n");
1319 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1325 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1326 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1327 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1330 val
= I915_READ(reg
);
1331 WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1332 "PCH VGA enabled on transcoder %c, should be disabled\n",
1336 val
= I915_READ(reg
);
1337 WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1338 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1341 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1342 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1343 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1346 static void vlv_enable_pll(struct intel_crtc
*crtc
)
1348 struct drm_device
*dev
= crtc
->base
.dev
;
1349 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1350 int reg
= DPLL(crtc
->pipe
);
1351 u32 dpll
= crtc
->config
.dpll_hw_state
.dpll
;
1353 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1355 /* No really, not for ILK+ */
1356 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
));
1358 /* PLL is protected by panel, make sure we can write it */
1359 if (IS_MOBILE(dev_priv
->dev
) && !IS_I830(dev_priv
->dev
))
1360 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1362 I915_WRITE(reg
, dpll
);
1366 if (wait_for(((I915_READ(reg
) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1367 DRM_ERROR("DPLL %d failed to lock\n", crtc
->pipe
);
1369 I915_WRITE(DPLL_MD(crtc
->pipe
), crtc
->config
.dpll_hw_state
.dpll_md
);
1370 POSTING_READ(DPLL_MD(crtc
->pipe
));
1372 /* We do this three times for luck */
1373 I915_WRITE(reg
, dpll
);
1375 udelay(150); /* wait for warmup */
1376 I915_WRITE(reg
, dpll
);
1378 udelay(150); /* wait for warmup */
1379 I915_WRITE(reg
, dpll
);
1381 udelay(150); /* wait for warmup */
1384 static void i9xx_enable_pll(struct intel_crtc
*crtc
)
1386 struct drm_device
*dev
= crtc
->base
.dev
;
1387 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1388 int reg
= DPLL(crtc
->pipe
);
1389 u32 dpll
= crtc
->config
.dpll_hw_state
.dpll
;
1391 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1393 /* No really, not for ILK+ */
1394 BUG_ON(dev_priv
->info
->gen
>= 5);
1396 /* PLL is protected by panel, make sure we can write it */
1397 if (IS_MOBILE(dev
) && !IS_I830(dev
))
1398 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1400 I915_WRITE(reg
, dpll
);
1402 /* Wait for the clocks to stabilize. */
1406 if (INTEL_INFO(dev
)->gen
>= 4) {
1407 I915_WRITE(DPLL_MD(crtc
->pipe
),
1408 crtc
->config
.dpll_hw_state
.dpll_md
);
1410 /* The pixel multiplier can only be updated once the
1411 * DPLL is enabled and the clocks are stable.
1413 * So write it again.
1415 I915_WRITE(reg
, dpll
);
1418 /* We do this three times for luck */
1419 I915_WRITE(reg
, dpll
);
1421 udelay(150); /* wait for warmup */
1422 I915_WRITE(reg
, dpll
);
1424 udelay(150); /* wait for warmup */
1425 I915_WRITE(reg
, dpll
);
1427 udelay(150); /* wait for warmup */
1431 * i9xx_disable_pll - disable a PLL
1432 * @dev_priv: i915 private structure
1433 * @pipe: pipe PLL to disable
1435 * Disable the PLL for @pipe, making sure the pipe is off first.
1437 * Note! This is for pre-ILK only.
1439 static void i9xx_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1441 /* Don't disable pipe A or pipe A PLLs if needed */
1442 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1445 /* Make sure the pipe isn't still relying on us */
1446 assert_pipe_disabled(dev_priv
, pipe
);
1448 I915_WRITE(DPLL(pipe
), 0);
1449 POSTING_READ(DPLL(pipe
));
1452 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
, int port
)
1457 port_mask
= DPLL_PORTB_READY_MASK
;
1459 port_mask
= DPLL_PORTC_READY_MASK
;
1461 if (wait_for((I915_READ(DPLL(0)) & port_mask
) == 0, 1000))
1462 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1463 'B' + port
, I915_READ(DPLL(0)));
1467 * ironlake_enable_shared_dpll - enable PCH PLL
1468 * @dev_priv: i915 private structure
1469 * @pipe: pipe PLL to enable
1471 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1472 * drives the transcoder clock.
1474 static void ironlake_enable_shared_dpll(struct intel_crtc
*crtc
)
1476 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1477 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1479 /* PCH PLLs only available on ILK, SNB and IVB */
1480 BUG_ON(dev_priv
->info
->gen
< 5);
1481 if (WARN_ON(pll
== NULL
))
1484 if (WARN_ON(pll
->refcount
== 0))
1487 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1488 pll
->name
, pll
->active
, pll
->on
,
1489 crtc
->base
.base
.id
);
1491 if (pll
->active
++) {
1493 assert_shared_dpll_enabled(dev_priv
, pll
);
1498 DRM_DEBUG_KMS("enabling %s\n", pll
->name
);
1499 pll
->enable(dev_priv
, pll
);
1503 static void intel_disable_shared_dpll(struct intel_crtc
*crtc
)
1505 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1506 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1508 /* PCH only available on ILK+ */
1509 BUG_ON(dev_priv
->info
->gen
< 5);
1510 if (WARN_ON(pll
== NULL
))
1513 if (WARN_ON(pll
->refcount
== 0))
1516 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1517 pll
->name
, pll
->active
, pll
->on
,
1518 crtc
->base
.base
.id
);
1520 if (WARN_ON(pll
->active
== 0)) {
1521 assert_shared_dpll_disabled(dev_priv
, pll
);
1525 assert_shared_dpll_enabled(dev_priv
, pll
);
1530 DRM_DEBUG_KMS("disabling %s\n", pll
->name
);
1531 pll
->disable(dev_priv
, pll
);
1535 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1538 struct drm_device
*dev
= dev_priv
->dev
;
1539 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1540 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1541 uint32_t reg
, val
, pipeconf_val
;
1543 /* PCH only available on ILK+ */
1544 BUG_ON(dev_priv
->info
->gen
< 5);
1546 /* Make sure PCH DPLL is enabled */
1547 assert_shared_dpll_enabled(dev_priv
,
1548 intel_crtc_to_shared_dpll(intel_crtc
));
1550 /* FDI must be feeding us bits for PCH ports */
1551 assert_fdi_tx_enabled(dev_priv
, pipe
);
1552 assert_fdi_rx_enabled(dev_priv
, pipe
);
1554 if (HAS_PCH_CPT(dev
)) {
1555 /* Workaround: Set the timing override bit before enabling the
1556 * pch transcoder. */
1557 reg
= TRANS_CHICKEN2(pipe
);
1558 val
= I915_READ(reg
);
1559 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1560 I915_WRITE(reg
, val
);
1563 reg
= PCH_TRANSCONF(pipe
);
1564 val
= I915_READ(reg
);
1565 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1567 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1569 * make the BPC in transcoder be consistent with
1570 * that in pipeconf reg.
1572 val
&= ~PIPECONF_BPC_MASK
;
1573 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1576 val
&= ~TRANS_INTERLACE_MASK
;
1577 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1578 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1579 intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
))
1580 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1582 val
|= TRANS_INTERLACED
;
1584 val
|= TRANS_PROGRESSIVE
;
1586 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1587 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1588 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
1591 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1592 enum transcoder cpu_transcoder
)
1594 u32 val
, pipeconf_val
;
1596 /* PCH only available on ILK+ */
1597 BUG_ON(dev_priv
->info
->gen
< 5);
1599 /* FDI must be feeding us bits for PCH ports */
1600 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1601 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
1603 /* Workaround: set timing override bit. */
1604 val
= I915_READ(_TRANSA_CHICKEN2
);
1605 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1606 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1609 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1611 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1612 PIPECONF_INTERLACED_ILK
)
1613 val
|= TRANS_INTERLACED
;
1615 val
|= TRANS_PROGRESSIVE
;
1617 I915_WRITE(LPT_TRANSCONF
, val
);
1618 if (wait_for(I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
, 100))
1619 DRM_ERROR("Failed to enable PCH transcoder\n");
1622 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1625 struct drm_device
*dev
= dev_priv
->dev
;
1628 /* FDI relies on the transcoder */
1629 assert_fdi_tx_disabled(dev_priv
, pipe
);
1630 assert_fdi_rx_disabled(dev_priv
, pipe
);
1632 /* Ports must be off as well */
1633 assert_pch_ports_disabled(dev_priv
, pipe
);
1635 reg
= PCH_TRANSCONF(pipe
);
1636 val
= I915_READ(reg
);
1637 val
&= ~TRANS_ENABLE
;
1638 I915_WRITE(reg
, val
);
1639 /* wait for PCH transcoder off, transcoder state */
1640 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1641 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
1643 if (!HAS_PCH_IBX(dev
)) {
1644 /* Workaround: Clear the timing override chicken bit again. */
1645 reg
= TRANS_CHICKEN2(pipe
);
1646 val
= I915_READ(reg
);
1647 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1648 I915_WRITE(reg
, val
);
1652 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1656 val
= I915_READ(LPT_TRANSCONF
);
1657 val
&= ~TRANS_ENABLE
;
1658 I915_WRITE(LPT_TRANSCONF
, val
);
1659 /* wait for PCH transcoder off, transcoder state */
1660 if (wait_for((I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
) == 0, 50))
1661 DRM_ERROR("Failed to disable PCH transcoder\n");
1663 /* Workaround: clear timing override bit. */
1664 val
= I915_READ(_TRANSA_CHICKEN2
);
1665 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1666 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1670 * intel_enable_pipe - enable a pipe, asserting requirements
1671 * @dev_priv: i915 private structure
1672 * @pipe: pipe to enable
1673 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1675 * Enable @pipe, making sure that various hardware specific requirements
1676 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1678 * @pipe should be %PIPE_A or %PIPE_B.
1680 * Will wait until the pipe is actually running (i.e. first vblank) before
1683 static void intel_enable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
1684 bool pch_port
, bool dsi
)
1686 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1688 enum pipe pch_transcoder
;
1692 assert_planes_disabled(dev_priv
, pipe
);
1693 assert_cursor_disabled(dev_priv
, pipe
);
1694 assert_sprites_disabled(dev_priv
, pipe
);
1696 if (HAS_PCH_LPT(dev_priv
->dev
))
1697 pch_transcoder
= TRANSCODER_A
;
1699 pch_transcoder
= pipe
;
1702 * A pipe without a PLL won't actually be able to drive bits from
1703 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1706 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
1708 assert_dsi_pll_enabled(dev_priv
);
1710 assert_pll_enabled(dev_priv
, pipe
);
1713 /* if driving the PCH, we need FDI enabled */
1714 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
1715 assert_fdi_tx_pll_enabled(dev_priv
,
1716 (enum pipe
) cpu_transcoder
);
1718 /* FIXME: assert CPU port conditions for SNB+ */
1721 reg
= PIPECONF(cpu_transcoder
);
1722 val
= I915_READ(reg
);
1723 if (val
& PIPECONF_ENABLE
)
1726 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
1727 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1731 * intel_disable_pipe - disable a pipe, asserting requirements
1732 * @dev_priv: i915 private structure
1733 * @pipe: pipe to disable
1735 * Disable @pipe, making sure that various hardware specific requirements
1736 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1738 * @pipe should be %PIPE_A or %PIPE_B.
1740 * Will wait until the pipe has shut down before returning.
1742 static void intel_disable_pipe(struct drm_i915_private
*dev_priv
,
1745 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1751 * Make sure planes won't keep trying to pump pixels to us,
1752 * or we might hang the display.
1754 assert_planes_disabled(dev_priv
, pipe
);
1755 assert_cursor_disabled(dev_priv
, pipe
);
1756 assert_sprites_disabled(dev_priv
, pipe
);
1758 /* Don't disable pipe A or pipe A PLLs if needed */
1759 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1762 reg
= PIPECONF(cpu_transcoder
);
1763 val
= I915_READ(reg
);
1764 if ((val
& PIPECONF_ENABLE
) == 0)
1767 I915_WRITE(reg
, val
& ~PIPECONF_ENABLE
);
1768 intel_wait_for_pipe_off(dev_priv
->dev
, pipe
);
1772 * Plane regs are double buffered, going from enabled->disabled needs a
1773 * trigger in order to latch. The display address reg provides this.
1775 void intel_flush_display_plane(struct drm_i915_private
*dev_priv
,
1778 if (dev_priv
->info
->gen
>= 4)
1779 I915_WRITE(DSPSURF(plane
), I915_READ(DSPSURF(plane
)));
1781 I915_WRITE(DSPADDR(plane
), I915_READ(DSPADDR(plane
)));
1785 * intel_enable_plane - enable a display plane on a given pipe
1786 * @dev_priv: i915 private structure
1787 * @plane: plane to enable
1788 * @pipe: pipe being fed
1790 * Enable @plane on @pipe, making sure that @pipe is running first.
1792 static void intel_enable_plane(struct drm_i915_private
*dev_priv
,
1793 enum plane plane
, enum pipe pipe
)
1798 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1799 assert_pipe_enabled(dev_priv
, pipe
);
1801 reg
= DSPCNTR(plane
);
1802 val
= I915_READ(reg
);
1803 if (val
& DISPLAY_PLANE_ENABLE
)
1806 I915_WRITE(reg
, val
| DISPLAY_PLANE_ENABLE
);
1807 intel_flush_display_plane(dev_priv
, plane
);
1808 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1812 * intel_disable_plane - disable a display plane
1813 * @dev_priv: i915 private structure
1814 * @plane: plane to disable
1815 * @pipe: pipe consuming the data
1817 * Disable @plane; should be an independent operation.
1819 static void intel_disable_plane(struct drm_i915_private
*dev_priv
,
1820 enum plane plane
, enum pipe pipe
)
1825 reg
= DSPCNTR(plane
);
1826 val
= I915_READ(reg
);
1827 if ((val
& DISPLAY_PLANE_ENABLE
) == 0)
1830 I915_WRITE(reg
, val
& ~DISPLAY_PLANE_ENABLE
);
1831 intel_flush_display_plane(dev_priv
, plane
);
1832 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1835 static bool need_vtd_wa(struct drm_device
*dev
)
1837 #ifdef CONFIG_INTEL_IOMMU
1838 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
1845 intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
1846 struct drm_i915_gem_object
*obj
,
1847 struct intel_ring_buffer
*pipelined
)
1849 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1853 switch (obj
->tiling_mode
) {
1854 case I915_TILING_NONE
:
1855 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
1856 alignment
= 128 * 1024;
1857 else if (INTEL_INFO(dev
)->gen
>= 4)
1858 alignment
= 4 * 1024;
1860 alignment
= 64 * 1024;
1863 /* pin() will align the object as required by fence */
1867 /* Despite that we check this in framebuffer_init userspace can
1868 * screw us over and change the tiling after the fact. Only
1869 * pinned buffers can't change their tiling. */
1870 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1876 /* Note that the w/a also requires 64 PTE of padding following the
1877 * bo. We currently fill all unused PTE with the shadow page and so
1878 * we should always have valid PTE following the scanout preventing
1881 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
1882 alignment
= 256 * 1024;
1884 dev_priv
->mm
.interruptible
= false;
1885 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
);
1887 goto err_interruptible
;
1889 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1890 * fence, whereas 965+ only requires a fence if using
1891 * framebuffer compression. For simplicity, we always install
1892 * a fence as the cost is not that onerous.
1894 ret
= i915_gem_object_get_fence(obj
);
1898 i915_gem_object_pin_fence(obj
);
1900 dev_priv
->mm
.interruptible
= true;
1904 i915_gem_object_unpin_from_display_plane(obj
);
1906 dev_priv
->mm
.interruptible
= true;
1910 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
)
1912 i915_gem_object_unpin_fence(obj
);
1913 i915_gem_object_unpin_from_display_plane(obj
);
1916 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1917 * is assumed to be a power-of-two. */
1918 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
1919 unsigned int tiling_mode
,
1923 if (tiling_mode
!= I915_TILING_NONE
) {
1924 unsigned int tile_rows
, tiles
;
1929 tiles
= *x
/ (512/cpp
);
1932 return tile_rows
* pitch
* 8 + tiles
* 4096;
1934 unsigned int offset
;
1936 offset
= *y
* pitch
+ *x
* cpp
;
1938 *x
= (offset
& 4095) / cpp
;
1939 return offset
& -4096;
1943 static int i9xx_update_plane(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
1946 struct drm_device
*dev
= crtc
->dev
;
1947 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1948 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1949 struct intel_framebuffer
*intel_fb
;
1950 struct drm_i915_gem_object
*obj
;
1951 int plane
= intel_crtc
->plane
;
1952 unsigned long linear_offset
;
1961 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane
));
1965 intel_fb
= to_intel_framebuffer(fb
);
1966 obj
= intel_fb
->obj
;
1968 reg
= DSPCNTR(plane
);
1969 dspcntr
= I915_READ(reg
);
1970 /* Mask out pixel format bits in case we change it */
1971 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
1972 switch (fb
->pixel_format
) {
1974 dspcntr
|= DISPPLANE_8BPP
;
1976 case DRM_FORMAT_XRGB1555
:
1977 case DRM_FORMAT_ARGB1555
:
1978 dspcntr
|= DISPPLANE_BGRX555
;
1980 case DRM_FORMAT_RGB565
:
1981 dspcntr
|= DISPPLANE_BGRX565
;
1983 case DRM_FORMAT_XRGB8888
:
1984 case DRM_FORMAT_ARGB8888
:
1985 dspcntr
|= DISPPLANE_BGRX888
;
1987 case DRM_FORMAT_XBGR8888
:
1988 case DRM_FORMAT_ABGR8888
:
1989 dspcntr
|= DISPPLANE_RGBX888
;
1991 case DRM_FORMAT_XRGB2101010
:
1992 case DRM_FORMAT_ARGB2101010
:
1993 dspcntr
|= DISPPLANE_BGRX101010
;
1995 case DRM_FORMAT_XBGR2101010
:
1996 case DRM_FORMAT_ABGR2101010
:
1997 dspcntr
|= DISPPLANE_RGBX101010
;
2003 if (INTEL_INFO(dev
)->gen
>= 4) {
2004 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2005 dspcntr
|= DISPPLANE_TILED
;
2007 dspcntr
&= ~DISPPLANE_TILED
;
2011 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2013 I915_WRITE(reg
, dspcntr
);
2015 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2017 if (INTEL_INFO(dev
)->gen
>= 4) {
2018 intel_crtc
->dspaddr_offset
=
2019 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2020 fb
->bits_per_pixel
/ 8,
2022 linear_offset
-= intel_crtc
->dspaddr_offset
;
2024 intel_crtc
->dspaddr_offset
= linear_offset
;
2027 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2028 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2030 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2031 if (INTEL_INFO(dev
)->gen
>= 4) {
2032 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2033 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2034 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2035 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2037 I915_WRITE(DSPADDR(plane
), i915_gem_obj_ggtt_offset(obj
) + linear_offset
);
2043 static int ironlake_update_plane(struct drm_crtc
*crtc
,
2044 struct drm_framebuffer
*fb
, int x
, int y
)
2046 struct drm_device
*dev
= crtc
->dev
;
2047 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2048 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2049 struct intel_framebuffer
*intel_fb
;
2050 struct drm_i915_gem_object
*obj
;
2051 int plane
= intel_crtc
->plane
;
2052 unsigned long linear_offset
;
2062 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane
));
2066 intel_fb
= to_intel_framebuffer(fb
);
2067 obj
= intel_fb
->obj
;
2069 reg
= DSPCNTR(plane
);
2070 dspcntr
= I915_READ(reg
);
2071 /* Mask out pixel format bits in case we change it */
2072 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2073 switch (fb
->pixel_format
) {
2075 dspcntr
|= DISPPLANE_8BPP
;
2077 case DRM_FORMAT_RGB565
:
2078 dspcntr
|= DISPPLANE_BGRX565
;
2080 case DRM_FORMAT_XRGB8888
:
2081 case DRM_FORMAT_ARGB8888
:
2082 dspcntr
|= DISPPLANE_BGRX888
;
2084 case DRM_FORMAT_XBGR8888
:
2085 case DRM_FORMAT_ABGR8888
:
2086 dspcntr
|= DISPPLANE_RGBX888
;
2088 case DRM_FORMAT_XRGB2101010
:
2089 case DRM_FORMAT_ARGB2101010
:
2090 dspcntr
|= DISPPLANE_BGRX101010
;
2092 case DRM_FORMAT_XBGR2101010
:
2093 case DRM_FORMAT_ABGR2101010
:
2094 dspcntr
|= DISPPLANE_RGBX101010
;
2100 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2101 dspcntr
|= DISPPLANE_TILED
;
2103 dspcntr
&= ~DISPPLANE_TILED
;
2105 if (IS_HASWELL(dev
))
2106 dspcntr
&= ~DISPPLANE_TRICKLE_FEED_DISABLE
;
2108 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2110 I915_WRITE(reg
, dspcntr
);
2112 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2113 intel_crtc
->dspaddr_offset
=
2114 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2115 fb
->bits_per_pixel
/ 8,
2117 linear_offset
-= intel_crtc
->dspaddr_offset
;
2119 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2120 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2122 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2123 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2124 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2125 if (IS_HASWELL(dev
)) {
2126 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2128 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2129 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2136 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2138 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2139 int x
, int y
, enum mode_set_atomic state
)
2141 struct drm_device
*dev
= crtc
->dev
;
2142 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2144 if (dev_priv
->display
.disable_fbc
)
2145 dev_priv
->display
.disable_fbc(dev
);
2146 intel_increase_pllclock(crtc
);
2148 return dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2151 void intel_display_handle_reset(struct drm_device
*dev
)
2153 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2154 struct drm_crtc
*crtc
;
2157 * Flips in the rings have been nuked by the reset,
2158 * so complete all pending flips so that user space
2159 * will get its events and not get stuck.
2161 * Also update the base address of all primary
2162 * planes to the the last fb to make sure we're
2163 * showing the correct fb after a reset.
2165 * Need to make two loops over the crtcs so that we
2166 * don't try to grab a crtc mutex before the
2167 * pending_flip_queue really got woken up.
2170 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2171 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2172 enum plane plane
= intel_crtc
->plane
;
2174 intel_prepare_page_flip(dev
, plane
);
2175 intel_finish_page_flip_plane(dev
, plane
);
2178 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2179 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2181 mutex_lock(&crtc
->mutex
);
2182 if (intel_crtc
->active
)
2183 dev_priv
->display
.update_plane(crtc
, crtc
->fb
,
2185 mutex_unlock(&crtc
->mutex
);
2190 intel_finish_fb(struct drm_framebuffer
*old_fb
)
2192 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(old_fb
)->obj
;
2193 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2194 bool was_interruptible
= dev_priv
->mm
.interruptible
;
2197 /* Big Hammer, we also need to ensure that any pending
2198 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2199 * current scanout is retired before unpinning the old
2202 * This should only fail upon a hung GPU, in which case we
2203 * can safely continue.
2205 dev_priv
->mm
.interruptible
= false;
2206 ret
= i915_gem_object_finish_gpu(obj
);
2207 dev_priv
->mm
.interruptible
= was_interruptible
;
2212 static void intel_crtc_update_sarea_pos(struct drm_crtc
*crtc
, int x
, int y
)
2214 struct drm_device
*dev
= crtc
->dev
;
2215 struct drm_i915_master_private
*master_priv
;
2216 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2218 if (!dev
->primary
->master
)
2221 master_priv
= dev
->primary
->master
->driver_priv
;
2222 if (!master_priv
->sarea_priv
)
2225 switch (intel_crtc
->pipe
) {
2227 master_priv
->sarea_priv
->pipeA_x
= x
;
2228 master_priv
->sarea_priv
->pipeA_y
= y
;
2231 master_priv
->sarea_priv
->pipeB_x
= x
;
2232 master_priv
->sarea_priv
->pipeB_y
= y
;
2240 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2241 struct drm_framebuffer
*fb
)
2243 struct drm_device
*dev
= crtc
->dev
;
2244 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2245 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2246 struct drm_framebuffer
*old_fb
;
2251 DRM_ERROR("No FB bound\n");
2255 if (intel_crtc
->plane
> INTEL_INFO(dev
)->num_pipes
) {
2256 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2257 plane_name(intel_crtc
->plane
),
2258 INTEL_INFO(dev
)->num_pipes
);
2262 mutex_lock(&dev
->struct_mutex
);
2263 ret
= intel_pin_and_fence_fb_obj(dev
,
2264 to_intel_framebuffer(fb
)->obj
,
2267 mutex_unlock(&dev
->struct_mutex
);
2268 DRM_ERROR("pin & fence failed\n");
2272 /* Update pipe size and adjust fitter if needed */
2273 if (i915_fastboot
) {
2274 I915_WRITE(PIPESRC(intel_crtc
->pipe
),
2275 ((crtc
->mode
.hdisplay
- 1) << 16) |
2276 (crtc
->mode
.vdisplay
- 1));
2277 if (!intel_crtc
->config
.pch_pfit
.size
&&
2278 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) ||
2279 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
2280 I915_WRITE(PF_CTL(intel_crtc
->pipe
), 0);
2281 I915_WRITE(PF_WIN_POS(intel_crtc
->pipe
), 0);
2282 I915_WRITE(PF_WIN_SZ(intel_crtc
->pipe
), 0);
2286 ret
= dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2288 intel_unpin_fb_obj(to_intel_framebuffer(fb
)->obj
);
2289 mutex_unlock(&dev
->struct_mutex
);
2290 DRM_ERROR("failed to update base address\n");
2300 if (intel_crtc
->active
&& old_fb
!= fb
)
2301 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2302 intel_unpin_fb_obj(to_intel_framebuffer(old_fb
)->obj
);
2305 intel_update_fbc(dev
);
2306 intel_edp_psr_update(dev
);
2307 mutex_unlock(&dev
->struct_mutex
);
2309 intel_crtc_update_sarea_pos(crtc
, x
, y
);
2314 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
2316 struct drm_device
*dev
= crtc
->dev
;
2317 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2318 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2319 int pipe
= intel_crtc
->pipe
;
2322 /* enable normal train */
2323 reg
= FDI_TX_CTL(pipe
);
2324 temp
= I915_READ(reg
);
2325 if (IS_IVYBRIDGE(dev
)) {
2326 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2327 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2329 temp
&= ~FDI_LINK_TRAIN_NONE
;
2330 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2332 I915_WRITE(reg
, temp
);
2334 reg
= FDI_RX_CTL(pipe
);
2335 temp
= I915_READ(reg
);
2336 if (HAS_PCH_CPT(dev
)) {
2337 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2338 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2340 temp
&= ~FDI_LINK_TRAIN_NONE
;
2341 temp
|= FDI_LINK_TRAIN_NONE
;
2343 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2345 /* wait one idle pattern time */
2349 /* IVB wants error correction enabled */
2350 if (IS_IVYBRIDGE(dev
))
2351 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
2352 FDI_FE_ERRC_ENABLE
);
2355 static bool pipe_has_enabled_pch(struct intel_crtc
*intel_crtc
)
2357 return intel_crtc
->base
.enabled
&& intel_crtc
->config
.has_pch_encoder
;
2360 static void ivb_modeset_global_resources(struct drm_device
*dev
)
2362 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2363 struct intel_crtc
*pipe_B_crtc
=
2364 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
2365 struct intel_crtc
*pipe_C_crtc
=
2366 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]);
2370 * When everything is off disable fdi C so that we could enable fdi B
2371 * with all lanes. Note that we don't care about enabled pipes without
2372 * an enabled pch encoder.
2374 if (!pipe_has_enabled_pch(pipe_B_crtc
) &&
2375 !pipe_has_enabled_pch(pipe_C_crtc
)) {
2376 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
2377 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
2379 temp
= I915_READ(SOUTH_CHICKEN1
);
2380 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
2381 DRM_DEBUG_KMS("disabling fdi C rx\n");
2382 I915_WRITE(SOUTH_CHICKEN1
, temp
);
2386 /* The FDI link training functions for ILK/Ibexpeak. */
2387 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
2389 struct drm_device
*dev
= crtc
->dev
;
2390 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2391 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2392 int pipe
= intel_crtc
->pipe
;
2393 int plane
= intel_crtc
->plane
;
2394 u32 reg
, temp
, tries
;
2396 /* FDI needs bits from pipe & plane first */
2397 assert_pipe_enabled(dev_priv
, pipe
);
2398 assert_plane_enabled(dev_priv
, plane
);
2400 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2402 reg
= FDI_RX_IMR(pipe
);
2403 temp
= I915_READ(reg
);
2404 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2405 temp
&= ~FDI_RX_BIT_LOCK
;
2406 I915_WRITE(reg
, temp
);
2410 /* enable CPU FDI TX and PCH FDI RX */
2411 reg
= FDI_TX_CTL(pipe
);
2412 temp
= I915_READ(reg
);
2413 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2414 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2415 temp
&= ~FDI_LINK_TRAIN_NONE
;
2416 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2417 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2419 reg
= FDI_RX_CTL(pipe
);
2420 temp
= I915_READ(reg
);
2421 temp
&= ~FDI_LINK_TRAIN_NONE
;
2422 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2423 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2428 /* Ironlake workaround, enable clock pointer after FDI enable*/
2429 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2430 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
2431 FDI_RX_PHASE_SYNC_POINTER_EN
);
2433 reg
= FDI_RX_IIR(pipe
);
2434 for (tries
= 0; tries
< 5; tries
++) {
2435 temp
= I915_READ(reg
);
2436 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2438 if ((temp
& FDI_RX_BIT_LOCK
)) {
2439 DRM_DEBUG_KMS("FDI train 1 done.\n");
2440 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2445 DRM_ERROR("FDI train 1 fail!\n");
2448 reg
= FDI_TX_CTL(pipe
);
2449 temp
= I915_READ(reg
);
2450 temp
&= ~FDI_LINK_TRAIN_NONE
;
2451 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2452 I915_WRITE(reg
, temp
);
2454 reg
= FDI_RX_CTL(pipe
);
2455 temp
= I915_READ(reg
);
2456 temp
&= ~FDI_LINK_TRAIN_NONE
;
2457 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2458 I915_WRITE(reg
, temp
);
2463 reg
= FDI_RX_IIR(pipe
);
2464 for (tries
= 0; tries
< 5; tries
++) {
2465 temp
= I915_READ(reg
);
2466 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2468 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2469 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2470 DRM_DEBUG_KMS("FDI train 2 done.\n");
2475 DRM_ERROR("FDI train 2 fail!\n");
2477 DRM_DEBUG_KMS("FDI train done\n");
2481 static const int snb_b_fdi_train_param
[] = {
2482 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
2483 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
2484 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
2485 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
2488 /* The FDI link training functions for SNB/Cougarpoint. */
2489 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
2491 struct drm_device
*dev
= crtc
->dev
;
2492 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2493 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2494 int pipe
= intel_crtc
->pipe
;
2495 u32 reg
, temp
, i
, retry
;
2497 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2499 reg
= FDI_RX_IMR(pipe
);
2500 temp
= I915_READ(reg
);
2501 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2502 temp
&= ~FDI_RX_BIT_LOCK
;
2503 I915_WRITE(reg
, temp
);
2508 /* enable CPU FDI TX and PCH FDI RX */
2509 reg
= FDI_TX_CTL(pipe
);
2510 temp
= I915_READ(reg
);
2511 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2512 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2513 temp
&= ~FDI_LINK_TRAIN_NONE
;
2514 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2515 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2517 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2518 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2520 I915_WRITE(FDI_RX_MISC(pipe
),
2521 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2523 reg
= FDI_RX_CTL(pipe
);
2524 temp
= I915_READ(reg
);
2525 if (HAS_PCH_CPT(dev
)) {
2526 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2527 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2529 temp
&= ~FDI_LINK_TRAIN_NONE
;
2530 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2532 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2537 for (i
= 0; i
< 4; i
++) {
2538 reg
= FDI_TX_CTL(pipe
);
2539 temp
= I915_READ(reg
);
2540 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2541 temp
|= snb_b_fdi_train_param
[i
];
2542 I915_WRITE(reg
, temp
);
2547 for (retry
= 0; retry
< 5; retry
++) {
2548 reg
= FDI_RX_IIR(pipe
);
2549 temp
= I915_READ(reg
);
2550 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2551 if (temp
& FDI_RX_BIT_LOCK
) {
2552 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2553 DRM_DEBUG_KMS("FDI train 1 done.\n");
2562 DRM_ERROR("FDI train 1 fail!\n");
2565 reg
= FDI_TX_CTL(pipe
);
2566 temp
= I915_READ(reg
);
2567 temp
&= ~FDI_LINK_TRAIN_NONE
;
2568 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2570 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2572 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2574 I915_WRITE(reg
, temp
);
2576 reg
= FDI_RX_CTL(pipe
);
2577 temp
= I915_READ(reg
);
2578 if (HAS_PCH_CPT(dev
)) {
2579 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2580 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2582 temp
&= ~FDI_LINK_TRAIN_NONE
;
2583 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2585 I915_WRITE(reg
, temp
);
2590 for (i
= 0; i
< 4; i
++) {
2591 reg
= FDI_TX_CTL(pipe
);
2592 temp
= I915_READ(reg
);
2593 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2594 temp
|= snb_b_fdi_train_param
[i
];
2595 I915_WRITE(reg
, temp
);
2600 for (retry
= 0; retry
< 5; retry
++) {
2601 reg
= FDI_RX_IIR(pipe
);
2602 temp
= I915_READ(reg
);
2603 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2604 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2605 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2606 DRM_DEBUG_KMS("FDI train 2 done.\n");
2615 DRM_ERROR("FDI train 2 fail!\n");
2617 DRM_DEBUG_KMS("FDI train done.\n");
2620 /* Manual link training for Ivy Bridge A0 parts */
2621 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
2623 struct drm_device
*dev
= crtc
->dev
;
2624 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2625 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2626 int pipe
= intel_crtc
->pipe
;
2627 u32 reg
, temp
, i
, j
;
2629 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2631 reg
= FDI_RX_IMR(pipe
);
2632 temp
= I915_READ(reg
);
2633 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2634 temp
&= ~FDI_RX_BIT_LOCK
;
2635 I915_WRITE(reg
, temp
);
2640 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2641 I915_READ(FDI_RX_IIR(pipe
)));
2643 /* Try each vswing and preemphasis setting twice before moving on */
2644 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
2645 /* disable first in case we need to retry */
2646 reg
= FDI_TX_CTL(pipe
);
2647 temp
= I915_READ(reg
);
2648 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
2649 temp
&= ~FDI_TX_ENABLE
;
2650 I915_WRITE(reg
, temp
);
2652 reg
= FDI_RX_CTL(pipe
);
2653 temp
= I915_READ(reg
);
2654 temp
&= ~FDI_LINK_TRAIN_AUTO
;
2655 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2656 temp
&= ~FDI_RX_ENABLE
;
2657 I915_WRITE(reg
, temp
);
2659 /* enable CPU FDI TX and PCH FDI RX */
2660 reg
= FDI_TX_CTL(pipe
);
2661 temp
= I915_READ(reg
);
2662 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2663 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2664 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
2665 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2666 temp
|= snb_b_fdi_train_param
[j
/2];
2667 temp
|= FDI_COMPOSITE_SYNC
;
2668 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2670 I915_WRITE(FDI_RX_MISC(pipe
),
2671 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2673 reg
= FDI_RX_CTL(pipe
);
2674 temp
= I915_READ(reg
);
2675 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2676 temp
|= FDI_COMPOSITE_SYNC
;
2677 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2680 udelay(1); /* should be 0.5us */
2682 for (i
= 0; i
< 4; i
++) {
2683 reg
= FDI_RX_IIR(pipe
);
2684 temp
= I915_READ(reg
);
2685 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2687 if (temp
& FDI_RX_BIT_LOCK
||
2688 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
2689 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2690 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2694 udelay(1); /* should be 0.5us */
2697 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
2702 reg
= FDI_TX_CTL(pipe
);
2703 temp
= I915_READ(reg
);
2704 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2705 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
2706 I915_WRITE(reg
, temp
);
2708 reg
= FDI_RX_CTL(pipe
);
2709 temp
= I915_READ(reg
);
2710 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2711 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2712 I915_WRITE(reg
, temp
);
2715 udelay(2); /* should be 1.5us */
2717 for (i
= 0; i
< 4; i
++) {
2718 reg
= FDI_RX_IIR(pipe
);
2719 temp
= I915_READ(reg
);
2720 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2722 if (temp
& FDI_RX_SYMBOL_LOCK
||
2723 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
2724 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2725 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2729 udelay(2); /* should be 1.5us */
2732 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
2736 DRM_DEBUG_KMS("FDI train done.\n");
2739 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
2741 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2742 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2743 int pipe
= intel_crtc
->pipe
;
2747 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2748 reg
= FDI_RX_CTL(pipe
);
2749 temp
= I915_READ(reg
);
2750 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
2751 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2752 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2753 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
2758 /* Switch from Rawclk to PCDclk */
2759 temp
= I915_READ(reg
);
2760 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
2765 /* Enable CPU FDI TX PLL, always on for Ironlake */
2766 reg
= FDI_TX_CTL(pipe
);
2767 temp
= I915_READ(reg
);
2768 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
2769 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
2776 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
2778 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2779 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2780 int pipe
= intel_crtc
->pipe
;
2783 /* Switch from PCDclk to Rawclk */
2784 reg
= FDI_RX_CTL(pipe
);
2785 temp
= I915_READ(reg
);
2786 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
2788 /* Disable CPU FDI TX PLL */
2789 reg
= FDI_TX_CTL(pipe
);
2790 temp
= I915_READ(reg
);
2791 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
2796 reg
= FDI_RX_CTL(pipe
);
2797 temp
= I915_READ(reg
);
2798 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
2800 /* Wait for the clocks to turn off. */
2805 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
2807 struct drm_device
*dev
= crtc
->dev
;
2808 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2809 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2810 int pipe
= intel_crtc
->pipe
;
2813 /* disable CPU FDI tx and PCH FDI rx */
2814 reg
= FDI_TX_CTL(pipe
);
2815 temp
= I915_READ(reg
);
2816 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
2819 reg
= FDI_RX_CTL(pipe
);
2820 temp
= I915_READ(reg
);
2821 temp
&= ~(0x7 << 16);
2822 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2823 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
2828 /* Ironlake workaround, disable clock pointer after downing FDI */
2829 if (HAS_PCH_IBX(dev
)) {
2830 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2833 /* still set train pattern 1 */
2834 reg
= FDI_TX_CTL(pipe
);
2835 temp
= I915_READ(reg
);
2836 temp
&= ~FDI_LINK_TRAIN_NONE
;
2837 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2838 I915_WRITE(reg
, temp
);
2840 reg
= FDI_RX_CTL(pipe
);
2841 temp
= I915_READ(reg
);
2842 if (HAS_PCH_CPT(dev
)) {
2843 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2844 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2846 temp
&= ~FDI_LINK_TRAIN_NONE
;
2847 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2849 /* BPC in FDI rx is consistent with that in PIPECONF */
2850 temp
&= ~(0x07 << 16);
2851 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2852 I915_WRITE(reg
, temp
);
2858 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
2860 struct drm_device
*dev
= crtc
->dev
;
2861 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2862 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2863 unsigned long flags
;
2866 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
2867 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
2870 spin_lock_irqsave(&dev
->event_lock
, flags
);
2871 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
2872 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2877 static void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
2879 struct drm_device
*dev
= crtc
->dev
;
2880 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2882 if (crtc
->fb
== NULL
)
2885 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
2887 wait_event(dev_priv
->pending_flip_queue
,
2888 !intel_crtc_has_pending_flip(crtc
));
2890 mutex_lock(&dev
->struct_mutex
);
2891 intel_finish_fb(crtc
->fb
);
2892 mutex_unlock(&dev
->struct_mutex
);
2895 /* Program iCLKIP clock to the desired frequency */
2896 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
2898 struct drm_device
*dev
= crtc
->dev
;
2899 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2900 int clock
= to_intel_crtc(crtc
)->config
.adjusted_mode
.clock
;
2901 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
2904 mutex_lock(&dev_priv
->dpio_lock
);
2906 /* It is necessary to ungate the pixclk gate prior to programming
2907 * the divisors, and gate it back when it is done.
2909 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
2911 /* Disable SSCCTL */
2912 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
2913 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
2917 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2918 if (clock
== 20000) {
2923 /* The iCLK virtual clock root frequency is in MHz,
2924 * but the adjusted_mode->clock in in KHz. To get the divisors,
2925 * it is necessary to divide one by another, so we
2926 * convert the virtual clock precision to KHz here for higher
2929 u32 iclk_virtual_root_freq
= 172800 * 1000;
2930 u32 iclk_pi_range
= 64;
2931 u32 desired_divisor
, msb_divisor_value
, pi_value
;
2933 desired_divisor
= (iclk_virtual_root_freq
/ clock
);
2934 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
2935 pi_value
= desired_divisor
% iclk_pi_range
;
2938 divsel
= msb_divisor_value
- 2;
2939 phaseinc
= pi_value
;
2942 /* This should not happen with any sane values */
2943 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
2944 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
2945 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
2946 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
2948 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2955 /* Program SSCDIVINTPHASE6 */
2956 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
2957 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
2958 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
2959 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
2960 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
2961 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
2962 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
2963 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
2965 /* Program SSCAUXDIV */
2966 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
2967 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2968 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
2969 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
2971 /* Enable modulator and associated divider */
2972 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
2973 temp
&= ~SBI_SSCCTL_DISABLE
;
2974 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
2976 /* Wait for initialization time */
2979 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
2981 mutex_unlock(&dev_priv
->dpio_lock
);
2984 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
2985 enum pipe pch_transcoder
)
2987 struct drm_device
*dev
= crtc
->base
.dev
;
2988 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2989 enum transcoder cpu_transcoder
= crtc
->config
.cpu_transcoder
;
2991 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
2992 I915_READ(HTOTAL(cpu_transcoder
)));
2993 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
2994 I915_READ(HBLANK(cpu_transcoder
)));
2995 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
2996 I915_READ(HSYNC(cpu_transcoder
)));
2998 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
2999 I915_READ(VTOTAL(cpu_transcoder
)));
3000 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
3001 I915_READ(VBLANK(cpu_transcoder
)));
3002 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
3003 I915_READ(VSYNC(cpu_transcoder
)));
3004 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
3005 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
3009 * Enable PCH resources required for PCH ports:
3011 * - FDI training & RX/TX
3012 * - update transcoder timings
3013 * - DP transcoding bits
3016 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
3018 struct drm_device
*dev
= crtc
->dev
;
3019 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3020 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3021 int pipe
= intel_crtc
->pipe
;
3024 assert_pch_transcoder_disabled(dev_priv
, pipe
);
3026 /* Write the TU size bits before fdi link training, so that error
3027 * detection works. */
3028 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
3029 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
3031 /* For PCH output, training FDI link */
3032 dev_priv
->display
.fdi_link_train(crtc
);
3034 /* We need to program the right clock selection before writing the pixel
3035 * mutliplier into the DPLL. */
3036 if (HAS_PCH_CPT(dev
)) {
3039 temp
= I915_READ(PCH_DPLL_SEL
);
3040 temp
|= TRANS_DPLL_ENABLE(pipe
);
3041 sel
= TRANS_DPLLB_SEL(pipe
);
3042 if (intel_crtc
->config
.shared_dpll
== DPLL_ID_PCH_PLL_B
)
3046 I915_WRITE(PCH_DPLL_SEL
, temp
);
3049 /* XXX: pch pll's can be enabled any time before we enable the PCH
3050 * transcoder, and we actually should do this to not upset any PCH
3051 * transcoder that already use the clock when we share it.
3053 * Note that enable_shared_dpll tries to do the right thing, but
3054 * get_shared_dpll unconditionally resets the pll - we need that to have
3055 * the right LVDS enable sequence. */
3056 ironlake_enable_shared_dpll(intel_crtc
);
3058 /* set transcoder timing, panel must allow it */
3059 assert_panel_unlocked(dev_priv
, pipe
);
3060 ironlake_pch_transcoder_set_timings(intel_crtc
, pipe
);
3062 intel_fdi_normal_train(crtc
);
3064 /* For PCH DP, enable TRANS_DP_CTL */
3065 if (HAS_PCH_CPT(dev
) &&
3066 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
3067 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3068 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
3069 reg
= TRANS_DP_CTL(pipe
);
3070 temp
= I915_READ(reg
);
3071 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
3072 TRANS_DP_SYNC_MASK
|
3074 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
3075 TRANS_DP_ENH_FRAMING
);
3076 temp
|= bpc
<< 9; /* same format but at 11:9 */
3078 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
3079 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
3080 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
3081 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
3083 switch (intel_trans_dp_port_sel(crtc
)) {
3085 temp
|= TRANS_DP_PORT_SEL_B
;
3088 temp
|= TRANS_DP_PORT_SEL_C
;
3091 temp
|= TRANS_DP_PORT_SEL_D
;
3097 I915_WRITE(reg
, temp
);
3100 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
3103 static void lpt_pch_enable(struct drm_crtc
*crtc
)
3105 struct drm_device
*dev
= crtc
->dev
;
3106 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3107 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3108 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
3110 assert_pch_transcoder_disabled(dev_priv
, TRANSCODER_A
);
3112 lpt_program_iclkip(crtc
);
3114 /* Set transcoder timing. */
3115 ironlake_pch_transcoder_set_timings(intel_crtc
, PIPE_A
);
3117 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
3120 static void intel_put_shared_dpll(struct intel_crtc
*crtc
)
3122 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3127 if (pll
->refcount
== 0) {
3128 WARN(1, "bad %s refcount\n", pll
->name
);
3132 if (--pll
->refcount
== 0) {
3134 WARN_ON(pll
->active
);
3137 crtc
->config
.shared_dpll
= DPLL_ID_PRIVATE
;
3140 static struct intel_shared_dpll
*intel_get_shared_dpll(struct intel_crtc
*crtc
)
3142 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
3143 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3144 enum intel_dpll_id i
;
3147 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3148 crtc
->base
.base
.id
, pll
->name
);
3149 intel_put_shared_dpll(crtc
);
3152 if (HAS_PCH_IBX(dev_priv
->dev
)) {
3153 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3154 i
= (enum intel_dpll_id
) crtc
->pipe
;
3155 pll
= &dev_priv
->shared_dplls
[i
];
3157 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3158 crtc
->base
.base
.id
, pll
->name
);
3163 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3164 pll
= &dev_priv
->shared_dplls
[i
];
3166 /* Only want to check enabled timings first */
3167 if (pll
->refcount
== 0)
3170 if (memcmp(&crtc
->config
.dpll_hw_state
, &pll
->hw_state
,
3171 sizeof(pll
->hw_state
)) == 0) {
3172 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3174 pll
->name
, pll
->refcount
, pll
->active
);
3180 /* Ok no matching timings, maybe there's a free one? */
3181 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3182 pll
= &dev_priv
->shared_dplls
[i
];
3183 if (pll
->refcount
== 0) {
3184 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3185 crtc
->base
.base
.id
, pll
->name
);
3193 crtc
->config
.shared_dpll
= i
;
3194 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll
->name
,
3195 pipe_name(crtc
->pipe
));
3197 if (pll
->active
== 0) {
3198 memcpy(&pll
->hw_state
, &crtc
->config
.dpll_hw_state
,
3199 sizeof(pll
->hw_state
));
3201 DRM_DEBUG_DRIVER("setting up %s\n", pll
->name
);
3203 assert_shared_dpll_disabled(dev_priv
, pll
);
3205 pll
->mode_set(dev_priv
, pll
);
3212 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
3214 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3215 int dslreg
= PIPEDSL(pipe
);
3218 temp
= I915_READ(dslreg
);
3220 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
3221 if (wait_for(I915_READ(dslreg
) != temp
, 5))
3222 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
3226 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
3228 struct drm_device
*dev
= crtc
->base
.dev
;
3229 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3230 int pipe
= crtc
->pipe
;
3232 if (crtc
->config
.pch_pfit
.size
) {
3233 /* Force use of hard-coded filter coefficients
3234 * as some pre-programmed values are broken,
3237 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
3238 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
3239 PF_PIPE_SEL_IVB(pipe
));
3241 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
3242 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
.pch_pfit
.pos
);
3243 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
.pch_pfit
.size
);
3247 static void intel_enable_planes(struct drm_crtc
*crtc
)
3249 struct drm_device
*dev
= crtc
->dev
;
3250 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
3251 struct intel_plane
*intel_plane
;
3253 list_for_each_entry(intel_plane
, &dev
->mode_config
.plane_list
, base
.head
)
3254 if (intel_plane
->pipe
== pipe
)
3255 intel_plane_restore(&intel_plane
->base
);
3258 static void intel_disable_planes(struct drm_crtc
*crtc
)
3260 struct drm_device
*dev
= crtc
->dev
;
3261 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
3262 struct intel_plane
*intel_plane
;
3264 list_for_each_entry(intel_plane
, &dev
->mode_config
.plane_list
, base
.head
)
3265 if (intel_plane
->pipe
== pipe
)
3266 intel_plane_disable(&intel_plane
->base
);
3269 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
3271 struct drm_device
*dev
= crtc
->dev
;
3272 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3273 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3274 struct intel_encoder
*encoder
;
3275 int pipe
= intel_crtc
->pipe
;
3276 int plane
= intel_crtc
->plane
;
3278 WARN_ON(!crtc
->enabled
);
3280 if (intel_crtc
->active
)
3283 intel_crtc
->active
= true;
3285 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
3286 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
3288 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3289 if (encoder
->pre_enable
)
3290 encoder
->pre_enable(encoder
);
3292 if (intel_crtc
->config
.has_pch_encoder
) {
3293 /* Note: FDI PLL enabling _must_ be done before we enable the
3294 * cpu pipes, hence this is separate from all the other fdi/pch
3296 ironlake_fdi_pll_enable(intel_crtc
);
3298 assert_fdi_tx_disabled(dev_priv
, pipe
);
3299 assert_fdi_rx_disabled(dev_priv
, pipe
);
3302 ironlake_pfit_enable(intel_crtc
);
3305 * On ILK+ LUT must be loaded before the pipe is running but with
3308 intel_crtc_load_lut(crtc
);
3310 intel_update_watermarks(crtc
);
3311 intel_enable_pipe(dev_priv
, pipe
,
3312 intel_crtc
->config
.has_pch_encoder
, false);
3313 intel_enable_plane(dev_priv
, plane
, pipe
);
3314 intel_enable_planes(crtc
);
3315 intel_crtc_update_cursor(crtc
, true);
3317 if (intel_crtc
->config
.has_pch_encoder
)
3318 ironlake_pch_enable(crtc
);
3320 mutex_lock(&dev
->struct_mutex
);
3321 intel_update_fbc(dev
);
3322 mutex_unlock(&dev
->struct_mutex
);
3324 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3325 encoder
->enable(encoder
);
3327 if (HAS_PCH_CPT(dev
))
3328 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
3331 * There seems to be a race in PCH platform hw (at least on some
3332 * outputs) where an enabled pipe still completes any pageflip right
3333 * away (as if the pipe is off) instead of waiting for vblank. As soon
3334 * as the first vblank happend, everything works as expected. Hence just
3335 * wait for one vblank before returning to avoid strange things
3338 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3341 /* IPS only exists on ULT machines and is tied to pipe A. */
3342 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
3344 return HAS_IPS(crtc
->base
.dev
) && crtc
->pipe
== PIPE_A
;
3347 static void hsw_enable_ips(struct intel_crtc
*crtc
)
3349 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
3351 if (!crtc
->config
.ips_enabled
)
3354 /* We can only enable IPS after we enable a plane and wait for a vblank.
3355 * We guarantee that the plane is enabled by calling intel_enable_ips
3356 * only after intel_enable_plane. And intel_enable_plane already waits
3357 * for a vblank, so all we need to do here is to enable the IPS bit. */
3358 assert_plane_enabled(dev_priv
, crtc
->plane
);
3359 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
3362 static void hsw_disable_ips(struct intel_crtc
*crtc
)
3364 struct drm_device
*dev
= crtc
->base
.dev
;
3365 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3367 if (!crtc
->config
.ips_enabled
)
3370 assert_plane_enabled(dev_priv
, crtc
->plane
);
3371 I915_WRITE(IPS_CTL
, 0);
3373 /* We need to wait for a vblank before we can disable the plane. */
3374 intel_wait_for_vblank(dev
, crtc
->pipe
);
3377 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
3379 struct drm_device
*dev
= crtc
->dev
;
3380 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3381 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3382 struct intel_encoder
*encoder
;
3383 int pipe
= intel_crtc
->pipe
;
3384 int plane
= intel_crtc
->plane
;
3386 WARN_ON(!crtc
->enabled
);
3388 if (intel_crtc
->active
)
3391 intel_crtc
->active
= true;
3393 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
3394 if (intel_crtc
->config
.has_pch_encoder
)
3395 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
3397 if (intel_crtc
->config
.has_pch_encoder
)
3398 dev_priv
->display
.fdi_link_train(crtc
);
3400 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3401 if (encoder
->pre_enable
)
3402 encoder
->pre_enable(encoder
);
3404 intel_ddi_enable_pipe_clock(intel_crtc
);
3406 ironlake_pfit_enable(intel_crtc
);
3409 * On ILK+ LUT must be loaded before the pipe is running but with
3412 intel_crtc_load_lut(crtc
);
3414 intel_ddi_set_pipe_settings(crtc
);
3415 intel_ddi_enable_transcoder_func(crtc
);
3417 intel_update_watermarks(crtc
);
3418 intel_enable_pipe(dev_priv
, pipe
,
3419 intel_crtc
->config
.has_pch_encoder
, false);
3420 intel_enable_plane(dev_priv
, plane
, pipe
);
3421 intel_enable_planes(crtc
);
3422 intel_crtc_update_cursor(crtc
, true);
3424 hsw_enable_ips(intel_crtc
);
3426 if (intel_crtc
->config
.has_pch_encoder
)
3427 lpt_pch_enable(crtc
);
3429 mutex_lock(&dev
->struct_mutex
);
3430 intel_update_fbc(dev
);
3431 mutex_unlock(&dev
->struct_mutex
);
3433 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
3434 encoder
->enable(encoder
);
3435 intel_opregion_notify_encoder(encoder
, true);
3439 * There seems to be a race in PCH platform hw (at least on some
3440 * outputs) where an enabled pipe still completes any pageflip right
3441 * away (as if the pipe is off) instead of waiting for vblank. As soon
3442 * as the first vblank happend, everything works as expected. Hence just
3443 * wait for one vblank before returning to avoid strange things
3446 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3449 static void ironlake_pfit_disable(struct intel_crtc
*crtc
)
3451 struct drm_device
*dev
= crtc
->base
.dev
;
3452 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3453 int pipe
= crtc
->pipe
;
3455 /* To avoid upsetting the power well on haswell only disable the pfit if
3456 * it's in use. The hw state code will make sure we get this right. */
3457 if (crtc
->config
.pch_pfit
.size
) {
3458 I915_WRITE(PF_CTL(pipe
), 0);
3459 I915_WRITE(PF_WIN_POS(pipe
), 0);
3460 I915_WRITE(PF_WIN_SZ(pipe
), 0);
3464 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
3466 struct drm_device
*dev
= crtc
->dev
;
3467 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3468 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3469 struct intel_encoder
*encoder
;
3470 int pipe
= intel_crtc
->pipe
;
3471 int plane
= intel_crtc
->plane
;
3475 if (!intel_crtc
->active
)
3478 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3479 encoder
->disable(encoder
);
3481 intel_crtc_wait_for_pending_flips(crtc
);
3482 drm_vblank_off(dev
, pipe
);
3484 if (dev_priv
->fbc
.plane
== plane
)
3485 intel_disable_fbc(dev
);
3487 intel_crtc_update_cursor(crtc
, false);
3488 intel_disable_planes(crtc
);
3489 intel_disable_plane(dev_priv
, plane
, pipe
);
3491 if (intel_crtc
->config
.has_pch_encoder
)
3492 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, false);
3494 intel_disable_pipe(dev_priv
, pipe
);
3496 ironlake_pfit_disable(intel_crtc
);
3498 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3499 if (encoder
->post_disable
)
3500 encoder
->post_disable(encoder
);
3502 if (intel_crtc
->config
.has_pch_encoder
) {
3503 ironlake_fdi_disable(crtc
);
3505 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
3506 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
3508 if (HAS_PCH_CPT(dev
)) {
3509 /* disable TRANS_DP_CTL */
3510 reg
= TRANS_DP_CTL(pipe
);
3511 temp
= I915_READ(reg
);
3512 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
3513 TRANS_DP_PORT_SEL_MASK
);
3514 temp
|= TRANS_DP_PORT_SEL_NONE
;
3515 I915_WRITE(reg
, temp
);
3517 /* disable DPLL_SEL */
3518 temp
= I915_READ(PCH_DPLL_SEL
);
3519 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
3520 I915_WRITE(PCH_DPLL_SEL
, temp
);
3523 /* disable PCH DPLL */
3524 intel_disable_shared_dpll(intel_crtc
);
3526 ironlake_fdi_pll_disable(intel_crtc
);
3529 intel_crtc
->active
= false;
3530 intel_update_watermarks(crtc
);
3532 mutex_lock(&dev
->struct_mutex
);
3533 intel_update_fbc(dev
);
3534 mutex_unlock(&dev
->struct_mutex
);
3537 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
3539 struct drm_device
*dev
= crtc
->dev
;
3540 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3541 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3542 struct intel_encoder
*encoder
;
3543 int pipe
= intel_crtc
->pipe
;
3544 int plane
= intel_crtc
->plane
;
3545 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
3547 if (!intel_crtc
->active
)
3550 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
3551 intel_opregion_notify_encoder(encoder
, false);
3552 encoder
->disable(encoder
);
3555 intel_crtc_wait_for_pending_flips(crtc
);
3556 drm_vblank_off(dev
, pipe
);
3558 /* FBC must be disabled before disabling the plane on HSW. */
3559 if (dev_priv
->fbc
.plane
== plane
)
3560 intel_disable_fbc(dev
);
3562 hsw_disable_ips(intel_crtc
);
3564 intel_crtc_update_cursor(crtc
, false);
3565 intel_disable_planes(crtc
);
3566 intel_disable_plane(dev_priv
, plane
, pipe
);
3568 if (intel_crtc
->config
.has_pch_encoder
)
3569 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, false);
3570 intel_disable_pipe(dev_priv
, pipe
);
3572 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
3574 ironlake_pfit_disable(intel_crtc
);
3576 intel_ddi_disable_pipe_clock(intel_crtc
);
3578 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3579 if (encoder
->post_disable
)
3580 encoder
->post_disable(encoder
);
3582 if (intel_crtc
->config
.has_pch_encoder
) {
3583 lpt_disable_pch_transcoder(dev_priv
);
3584 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
3585 intel_ddi_fdi_disable(crtc
);
3588 intel_crtc
->active
= false;
3589 intel_update_watermarks(crtc
);
3591 mutex_lock(&dev
->struct_mutex
);
3592 intel_update_fbc(dev
);
3593 mutex_unlock(&dev
->struct_mutex
);
3596 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
3598 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3599 intel_put_shared_dpll(intel_crtc
);
3602 static void haswell_crtc_off(struct drm_crtc
*crtc
)
3604 intel_ddi_put_crtc_pll(crtc
);
3607 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
3609 if (!enable
&& intel_crtc
->overlay
) {
3610 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3611 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3613 mutex_lock(&dev
->struct_mutex
);
3614 dev_priv
->mm
.interruptible
= false;
3615 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
3616 dev_priv
->mm
.interruptible
= true;
3617 mutex_unlock(&dev
->struct_mutex
);
3620 /* Let userspace switch the overlay on again. In most cases userspace
3621 * has to recompute where to put it anyway.
3626 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3627 * cursor plane briefly if not already running after enabling the display
3629 * This workaround avoids occasional blank screens when self refresh is
3633 g4x_fixup_plane(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
3635 u32 cntl
= I915_READ(CURCNTR(pipe
));
3637 if ((cntl
& CURSOR_MODE
) == 0) {
3638 u32 fw_bcl_self
= I915_READ(FW_BLC_SELF
);
3640 I915_WRITE(FW_BLC_SELF
, fw_bcl_self
& ~FW_BLC_SELF_EN
);
3641 I915_WRITE(CURCNTR(pipe
), CURSOR_MODE_64_ARGB_AX
);
3642 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
3643 I915_WRITE(CURCNTR(pipe
), cntl
);
3644 I915_WRITE(CURBASE(pipe
), I915_READ(CURBASE(pipe
)));
3645 I915_WRITE(FW_BLC_SELF
, fw_bcl_self
);
3649 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
3651 struct drm_device
*dev
= crtc
->base
.dev
;
3652 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3653 struct intel_crtc_config
*pipe_config
= &crtc
->config
;
3655 if (!crtc
->config
.gmch_pfit
.control
)
3659 * The panel fitter should only be adjusted whilst the pipe is disabled,
3660 * according to register description and PRM.
3662 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
3663 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
3665 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
3666 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
3668 /* Border color in case we don't scale up to the full screen. Black by
3669 * default, change to something else for debugging. */
3670 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
3673 static void valleyview_crtc_enable(struct drm_crtc
*crtc
)
3675 struct drm_device
*dev
= crtc
->dev
;
3676 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3677 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3678 struct intel_encoder
*encoder
;
3679 int pipe
= intel_crtc
->pipe
;
3680 int plane
= intel_crtc
->plane
;
3683 WARN_ON(!crtc
->enabled
);
3685 if (intel_crtc
->active
)
3688 intel_crtc
->active
= true;
3690 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3691 if (encoder
->pre_pll_enable
)
3692 encoder
->pre_pll_enable(encoder
);
3694 is_dsi
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
);
3697 vlv_enable_pll(intel_crtc
);
3699 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3700 if (encoder
->pre_enable
)
3701 encoder
->pre_enable(encoder
);
3703 i9xx_pfit_enable(intel_crtc
);
3705 intel_crtc_load_lut(crtc
);
3707 intel_update_watermarks(crtc
);
3708 intel_enable_pipe(dev_priv
, pipe
, false, is_dsi
);
3709 intel_enable_plane(dev_priv
, plane
, pipe
);
3710 intel_enable_planes(crtc
);
3711 intel_crtc_update_cursor(crtc
, true);
3713 intel_update_fbc(dev
);
3715 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3716 encoder
->enable(encoder
);
3719 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
3721 struct drm_device
*dev
= crtc
->dev
;
3722 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3723 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3724 struct intel_encoder
*encoder
;
3725 int pipe
= intel_crtc
->pipe
;
3726 int plane
= intel_crtc
->plane
;
3728 WARN_ON(!crtc
->enabled
);
3730 if (intel_crtc
->active
)
3733 intel_crtc
->active
= true;
3735 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3736 if (encoder
->pre_enable
)
3737 encoder
->pre_enable(encoder
);
3739 i9xx_enable_pll(intel_crtc
);
3741 i9xx_pfit_enable(intel_crtc
);
3743 intel_crtc_load_lut(crtc
);
3745 intel_update_watermarks(crtc
);
3746 intel_enable_pipe(dev_priv
, pipe
, false, false);
3747 intel_enable_plane(dev_priv
, plane
, pipe
);
3748 intel_enable_planes(crtc
);
3749 /* The fixup needs to happen before cursor is enabled */
3751 g4x_fixup_plane(dev_priv
, pipe
);
3752 intel_crtc_update_cursor(crtc
, true);
3754 /* Give the overlay scaler a chance to enable if it's on this pipe */
3755 intel_crtc_dpms_overlay(intel_crtc
, true);
3757 intel_update_fbc(dev
);
3759 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3760 encoder
->enable(encoder
);
3763 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
3765 struct drm_device
*dev
= crtc
->base
.dev
;
3766 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3768 if (!crtc
->config
.gmch_pfit
.control
)
3771 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
3773 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3774 I915_READ(PFIT_CONTROL
));
3775 I915_WRITE(PFIT_CONTROL
, 0);
3778 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
3780 struct drm_device
*dev
= crtc
->dev
;
3781 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3782 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3783 struct intel_encoder
*encoder
;
3784 int pipe
= intel_crtc
->pipe
;
3785 int plane
= intel_crtc
->plane
;
3787 if (!intel_crtc
->active
)
3790 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3791 encoder
->disable(encoder
);
3793 /* Give the overlay scaler a chance to disable if it's on this pipe */
3794 intel_crtc_wait_for_pending_flips(crtc
);
3795 drm_vblank_off(dev
, pipe
);
3797 if (dev_priv
->fbc
.plane
== plane
)
3798 intel_disable_fbc(dev
);
3800 intel_crtc_dpms_overlay(intel_crtc
, false);
3801 intel_crtc_update_cursor(crtc
, false);
3802 intel_disable_planes(crtc
);
3803 intel_disable_plane(dev_priv
, plane
, pipe
);
3805 intel_disable_pipe(dev_priv
, pipe
);
3807 i9xx_pfit_disable(intel_crtc
);
3809 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3810 if (encoder
->post_disable
)
3811 encoder
->post_disable(encoder
);
3813 if (!intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
))
3814 i9xx_disable_pll(dev_priv
, pipe
);
3816 intel_crtc
->active
= false;
3817 intel_update_watermarks(crtc
);
3819 intel_update_fbc(dev
);
3822 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
3826 static void intel_crtc_update_sarea(struct drm_crtc
*crtc
,
3829 struct drm_device
*dev
= crtc
->dev
;
3830 struct drm_i915_master_private
*master_priv
;
3831 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3832 int pipe
= intel_crtc
->pipe
;
3834 if (!dev
->primary
->master
)
3837 master_priv
= dev
->primary
->master
->driver_priv
;
3838 if (!master_priv
->sarea_priv
)
3843 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3844 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3847 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3848 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3851 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe
));
3857 * Sets the power management mode of the pipe and plane.
3859 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
3861 struct drm_device
*dev
= crtc
->dev
;
3862 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3863 struct intel_encoder
*intel_encoder
;
3864 bool enable
= false;
3866 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
3867 enable
|= intel_encoder
->connectors_active
;
3870 dev_priv
->display
.crtc_enable(crtc
);
3872 dev_priv
->display
.crtc_disable(crtc
);
3874 intel_crtc_update_sarea(crtc
, enable
);
3877 static void intel_crtc_disable(struct drm_crtc
*crtc
)
3879 struct drm_device
*dev
= crtc
->dev
;
3880 struct drm_connector
*connector
;
3881 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3882 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3884 /* crtc should still be enabled when we disable it. */
3885 WARN_ON(!crtc
->enabled
);
3887 dev_priv
->display
.crtc_disable(crtc
);
3888 intel_crtc
->eld_vld
= false;
3889 intel_crtc_update_sarea(crtc
, false);
3890 dev_priv
->display
.off(crtc
);
3892 assert_plane_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->plane
);
3893 assert_cursor_disabled(dev_priv
, to_intel_crtc(crtc
)->pipe
);
3894 assert_pipe_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->pipe
);
3897 mutex_lock(&dev
->struct_mutex
);
3898 intel_unpin_fb_obj(to_intel_framebuffer(crtc
->fb
)->obj
);
3899 mutex_unlock(&dev
->struct_mutex
);
3903 /* Update computed state. */
3904 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
3905 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
3908 if (connector
->encoder
->crtc
!= crtc
)
3911 connector
->dpms
= DRM_MODE_DPMS_OFF
;
3912 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
3916 void intel_encoder_destroy(struct drm_encoder
*encoder
)
3918 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
3920 drm_encoder_cleanup(encoder
);
3921 kfree(intel_encoder
);
3924 /* Simple dpms helper for encoders with just one connector, no cloning and only
3925 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3926 * state of the entire output pipe. */
3927 static void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
3929 if (mode
== DRM_MODE_DPMS_ON
) {
3930 encoder
->connectors_active
= true;
3932 intel_crtc_update_dpms(encoder
->base
.crtc
);
3934 encoder
->connectors_active
= false;
3936 intel_crtc_update_dpms(encoder
->base
.crtc
);
3940 /* Cross check the actual hw state with our own modeset state tracking (and it's
3941 * internal consistency). */
3942 static void intel_connector_check_state(struct intel_connector
*connector
)
3944 if (connector
->get_hw_state(connector
)) {
3945 struct intel_encoder
*encoder
= connector
->encoder
;
3946 struct drm_crtc
*crtc
;
3947 bool encoder_enabled
;
3950 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3951 connector
->base
.base
.id
,
3952 drm_get_connector_name(&connector
->base
));
3954 WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
3955 "wrong connector dpms state\n");
3956 WARN(connector
->base
.encoder
!= &encoder
->base
,
3957 "active connector not linked to encoder\n");
3958 WARN(!encoder
->connectors_active
,
3959 "encoder->connectors_active not set\n");
3961 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
3962 WARN(!encoder_enabled
, "encoder not enabled\n");
3963 if (WARN_ON(!encoder
->base
.crtc
))
3966 crtc
= encoder
->base
.crtc
;
3968 WARN(!crtc
->enabled
, "crtc not enabled\n");
3969 WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
3970 WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
3971 "encoder active on the wrong pipe\n");
3975 /* Even simpler default implementation, if there's really no special case to
3977 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
3979 struct intel_encoder
*encoder
= intel_attached_encoder(connector
);
3981 /* All the simple cases only support two dpms states. */
3982 if (mode
!= DRM_MODE_DPMS_ON
)
3983 mode
= DRM_MODE_DPMS_OFF
;
3985 if (mode
== connector
->dpms
)
3988 connector
->dpms
= mode
;
3990 /* Only need to change hw state when actually enabled */
3991 if (encoder
->base
.crtc
)
3992 intel_encoder_dpms(encoder
, mode
);
3994 WARN_ON(encoder
->connectors_active
!= false);
3996 intel_modeset_check_state(connector
->dev
);
3999 /* Simple connector->get_hw_state implementation for encoders that support only
4000 * one connector and no cloning and hence the encoder state determines the state
4001 * of the connector. */
4002 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
4005 struct intel_encoder
*encoder
= connector
->encoder
;
4007 return encoder
->get_hw_state(encoder
, &pipe
);
4010 static bool ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
4011 struct intel_crtc_config
*pipe_config
)
4013 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4014 struct intel_crtc
*pipe_B_crtc
=
4015 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
4017 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4018 pipe_name(pipe
), pipe_config
->fdi_lanes
);
4019 if (pipe_config
->fdi_lanes
> 4) {
4020 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4021 pipe_name(pipe
), pipe_config
->fdi_lanes
);
4025 if (IS_HASWELL(dev
)) {
4026 if (pipe_config
->fdi_lanes
> 2) {
4027 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4028 pipe_config
->fdi_lanes
);
4035 if (INTEL_INFO(dev
)->num_pipes
== 2)
4038 /* Ivybridge 3 pipe is really complicated */
4043 if (dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]->enabled
&&
4044 pipe_config
->fdi_lanes
> 2) {
4045 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4046 pipe_name(pipe
), pipe_config
->fdi_lanes
);
4051 if (!pipe_has_enabled_pch(pipe_B_crtc
) ||
4052 pipe_B_crtc
->config
.fdi_lanes
<= 2) {
4053 if (pipe_config
->fdi_lanes
> 2) {
4054 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4055 pipe_name(pipe
), pipe_config
->fdi_lanes
);
4059 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4069 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
4070 struct intel_crtc_config
*pipe_config
)
4072 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4073 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
4074 int lane
, link_bw
, fdi_dotclock
;
4075 bool setup_ok
, needs_recompute
= false;
4078 /* FDI is a binary signal running at ~2.7GHz, encoding
4079 * each output octet as 10 bits. The actual frequency
4080 * is stored as a divider into a 100MHz clock, and the
4081 * mode pixel clock is stored in units of 1KHz.
4082 * Hence the bw of each lane in terms of the mode signal
4085 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
4087 fdi_dotclock
= adjusted_mode
->clock
;
4089 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
4090 pipe_config
->pipe_bpp
);
4092 pipe_config
->fdi_lanes
= lane
;
4094 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
4095 link_bw
, &pipe_config
->fdi_m_n
);
4097 setup_ok
= ironlake_check_fdi_lanes(intel_crtc
->base
.dev
,
4098 intel_crtc
->pipe
, pipe_config
);
4099 if (!setup_ok
&& pipe_config
->pipe_bpp
> 6*3) {
4100 pipe_config
->pipe_bpp
-= 2*3;
4101 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4102 pipe_config
->pipe_bpp
);
4103 needs_recompute
= true;
4104 pipe_config
->bw_constrained
= true;
4109 if (needs_recompute
)
4112 return setup_ok
? 0 : -EINVAL
;
4115 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
4116 struct intel_crtc_config
*pipe_config
)
4118 pipe_config
->ips_enabled
= i915_enable_ips
&&
4119 hsw_crtc_supports_ips(crtc
) &&
4120 pipe_config
->pipe_bpp
<= 24;
4123 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
4124 struct intel_crtc_config
*pipe_config
)
4126 struct drm_device
*dev
= crtc
->base
.dev
;
4127 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
4129 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4130 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4132 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
4133 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
4136 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) && pipe_config
->pipe_bpp
> 10*3) {
4137 pipe_config
->pipe_bpp
= 10*3; /* 12bpc is gen5+ */
4138 } else if (INTEL_INFO(dev
)->gen
<= 4 && pipe_config
->pipe_bpp
> 8*3) {
4139 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4141 pipe_config
->pipe_bpp
= 8*3;
4145 hsw_compute_ips_config(crtc
, pipe_config
);
4147 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4148 * clock survives for now. */
4149 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
4150 pipe_config
->shared_dpll
= crtc
->config
.shared_dpll
;
4152 if (pipe_config
->has_pch_encoder
)
4153 return ironlake_fdi_compute_config(crtc
, pipe_config
);
4158 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
4160 return 400000; /* FIXME */
4163 static int i945_get_display_clock_speed(struct drm_device
*dev
)
4168 static int i915_get_display_clock_speed(struct drm_device
*dev
)
4173 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
4178 static int pnv_get_display_clock_speed(struct drm_device
*dev
)
4182 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
4184 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
4185 case GC_DISPLAY_CLOCK_267_MHZ_PNV
:
4187 case GC_DISPLAY_CLOCK_333_MHZ_PNV
:
4189 case GC_DISPLAY_CLOCK_444_MHZ_PNV
:
4191 case GC_DISPLAY_CLOCK_200_MHZ_PNV
:
4194 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc
);
4195 case GC_DISPLAY_CLOCK_133_MHZ_PNV
:
4197 case GC_DISPLAY_CLOCK_167_MHZ_PNV
:
4202 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
4206 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
4208 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
4211 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
4212 case GC_DISPLAY_CLOCK_333_MHZ
:
4215 case GC_DISPLAY_CLOCK_190_200_MHZ
:
4221 static int i865_get_display_clock_speed(struct drm_device
*dev
)
4226 static int i855_get_display_clock_speed(struct drm_device
*dev
)
4229 /* Assume that the hardware is in the high speed state. This
4230 * should be the default.
4232 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
4233 case GC_CLOCK_133_200
:
4234 case GC_CLOCK_100_200
:
4236 case GC_CLOCK_166_250
:
4238 case GC_CLOCK_100_133
:
4242 /* Shouldn't happen */
4246 static int i830_get_display_clock_speed(struct drm_device
*dev
)
4252 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
4254 while (*num
> DATA_LINK_M_N_MASK
||
4255 *den
> DATA_LINK_M_N_MASK
) {
4261 static void compute_m_n(unsigned int m
, unsigned int n
,
4262 uint32_t *ret_m
, uint32_t *ret_n
)
4264 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
4265 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
4266 intel_reduce_m_n_ratio(ret_m
, ret_n
);
4270 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
4271 int pixel_clock
, int link_clock
,
4272 struct intel_link_m_n
*m_n
)
4276 compute_m_n(bits_per_pixel
* pixel_clock
,
4277 link_clock
* nlanes
* 8,
4278 &m_n
->gmch_m
, &m_n
->gmch_n
);
4280 compute_m_n(pixel_clock
, link_clock
,
4281 &m_n
->link_m
, &m_n
->link_n
);
4284 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
4286 if (i915_panel_use_ssc
>= 0)
4287 return i915_panel_use_ssc
!= 0;
4288 return dev_priv
->vbt
.lvds_use_ssc
4289 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
4292 static int vlv_get_refclk(struct drm_crtc
*crtc
)
4294 struct drm_device
*dev
= crtc
->dev
;
4295 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4296 int refclk
= 27000; /* for DP & HDMI */
4298 return 100000; /* only one validated so far */
4300 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
4302 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
4303 if (intel_panel_use_ssc(dev_priv
))
4307 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
)) {
4314 static int i9xx_get_refclk(struct drm_crtc
*crtc
, int num_connectors
)
4316 struct drm_device
*dev
= crtc
->dev
;
4317 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4320 if (IS_VALLEYVIEW(dev
)) {
4321 refclk
= vlv_get_refclk(crtc
);
4322 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4323 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
4324 refclk
= dev_priv
->vbt
.lvds_ssc_freq
* 1000;
4325 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4327 } else if (!IS_GEN2(dev
)) {
4336 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
4338 return (1 << dpll
->n
) << 16 | dpll
->m2
;
4341 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
4343 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
4346 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
4347 intel_clock_t
*reduced_clock
)
4349 struct drm_device
*dev
= crtc
->base
.dev
;
4350 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4351 int pipe
= crtc
->pipe
;
4354 if (IS_PINEVIEW(dev
)) {
4355 fp
= pnv_dpll_compute_fp(&crtc
->config
.dpll
);
4357 fp2
= pnv_dpll_compute_fp(reduced_clock
);
4359 fp
= i9xx_dpll_compute_fp(&crtc
->config
.dpll
);
4361 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
4364 I915_WRITE(FP0(pipe
), fp
);
4365 crtc
->config
.dpll_hw_state
.fp0
= fp
;
4367 crtc
->lowfreq_avail
= false;
4368 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4369 reduced_clock
&& i915_powersave
) {
4370 I915_WRITE(FP1(pipe
), fp2
);
4371 crtc
->config
.dpll_hw_state
.fp1
= fp2
;
4372 crtc
->lowfreq_avail
= true;
4374 I915_WRITE(FP1(pipe
), fp
);
4375 crtc
->config
.dpll_hw_state
.fp1
= fp
;
4379 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
4385 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4386 * and set it to a reasonable value instead.
4388 reg_val
= vlv_dpio_read(dev_priv
, pipe
, DPIO_IREF(1));
4389 reg_val
&= 0xffffff00;
4390 reg_val
|= 0x00000030;
4391 vlv_dpio_write(dev_priv
, pipe
, DPIO_IREF(1), reg_val
);
4393 reg_val
= vlv_dpio_read(dev_priv
, pipe
, DPIO_CALIBRATION
);
4394 reg_val
&= 0x8cffffff;
4395 reg_val
= 0x8c000000;
4396 vlv_dpio_write(dev_priv
, pipe
, DPIO_CALIBRATION
, reg_val
);
4398 reg_val
= vlv_dpio_read(dev_priv
, pipe
, DPIO_IREF(1));
4399 reg_val
&= 0xffffff00;
4400 vlv_dpio_write(dev_priv
, pipe
, DPIO_IREF(1), reg_val
);
4402 reg_val
= vlv_dpio_read(dev_priv
, pipe
, DPIO_CALIBRATION
);
4403 reg_val
&= 0x00ffffff;
4404 reg_val
|= 0xb0000000;
4405 vlv_dpio_write(dev_priv
, pipe
, DPIO_CALIBRATION
, reg_val
);
4408 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
4409 struct intel_link_m_n
*m_n
)
4411 struct drm_device
*dev
= crtc
->base
.dev
;
4412 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4413 int pipe
= crtc
->pipe
;
4415 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
4416 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
4417 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
4418 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
4421 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
4422 struct intel_link_m_n
*m_n
)
4424 struct drm_device
*dev
= crtc
->base
.dev
;
4425 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4426 int pipe
= crtc
->pipe
;
4427 enum transcoder transcoder
= crtc
->config
.cpu_transcoder
;
4429 if (INTEL_INFO(dev
)->gen
>= 5) {
4430 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
4431 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
4432 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
4433 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
4435 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
4436 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
4437 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
4438 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
4442 static void intel_dp_set_m_n(struct intel_crtc
*crtc
)
4444 if (crtc
->config
.has_pch_encoder
)
4445 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
4447 intel_cpu_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
4450 static void vlv_update_pll(struct intel_crtc
*crtc
)
4452 struct drm_device
*dev
= crtc
->base
.dev
;
4453 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4454 int pipe
= crtc
->pipe
;
4456 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
4457 u32 coreclk
, reg_val
, dpll_md
;
4459 mutex_lock(&dev_priv
->dpio_lock
);
4461 bestn
= crtc
->config
.dpll
.n
;
4462 bestm1
= crtc
->config
.dpll
.m1
;
4463 bestm2
= crtc
->config
.dpll
.m2
;
4464 bestp1
= crtc
->config
.dpll
.p1
;
4465 bestp2
= crtc
->config
.dpll
.p2
;
4467 /* See eDP HDMI DPIO driver vbios notes doc */
4469 /* PLL B needs special handling */
4471 vlv_pllb_recal_opamp(dev_priv
, pipe
);
4473 /* Set up Tx target for periodic Rcomp update */
4474 vlv_dpio_write(dev_priv
, pipe
, DPIO_IREF_BCAST
, 0x0100000f);
4476 /* Disable target IRef on PLL */
4477 reg_val
= vlv_dpio_read(dev_priv
, pipe
, DPIO_IREF_CTL(pipe
));
4478 reg_val
&= 0x00ffffff;
4479 vlv_dpio_write(dev_priv
, pipe
, DPIO_IREF_CTL(pipe
), reg_val
);
4481 /* Disable fast lock */
4482 vlv_dpio_write(dev_priv
, pipe
, DPIO_FASTCLK_DISABLE
, 0x610);
4484 /* Set idtafcrecal before PLL is enabled */
4485 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
4486 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
4487 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
4488 mdiv
|= (1 << DPIO_K_SHIFT
);
4491 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4492 * but we don't support that).
4493 * Note: don't use the DAC post divider as it seems unstable.
4495 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
4496 vlv_dpio_write(dev_priv
, pipe
, DPIO_DIV(pipe
), mdiv
);
4498 mdiv
|= DPIO_ENABLE_CALIBRATION
;
4499 vlv_dpio_write(dev_priv
, pipe
, DPIO_DIV(pipe
), mdiv
);
4501 /* Set HBR and RBR LPF coefficients */
4502 if (crtc
->config
.port_clock
== 162000 ||
4503 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_ANALOG
) ||
4504 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
))
4505 vlv_dpio_write(dev_priv
, pipe
, DPIO_LPF_COEFF(pipe
),
4508 vlv_dpio_write(dev_priv
, pipe
, DPIO_LPF_COEFF(pipe
),
4511 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
) ||
4512 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
)) {
4513 /* Use SSC source */
4515 vlv_dpio_write(dev_priv
, pipe
, DPIO_REFSFR(pipe
),
4518 vlv_dpio_write(dev_priv
, pipe
, DPIO_REFSFR(pipe
),
4520 } else { /* HDMI or VGA */
4521 /* Use bend source */
4523 vlv_dpio_write(dev_priv
, pipe
, DPIO_REFSFR(pipe
),
4526 vlv_dpio_write(dev_priv
, pipe
, DPIO_REFSFR(pipe
),
4530 coreclk
= vlv_dpio_read(dev_priv
, pipe
, DPIO_CORE_CLK(pipe
));
4531 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
4532 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
) ||
4533 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
))
4534 coreclk
|= 0x01000000;
4535 vlv_dpio_write(dev_priv
, pipe
, DPIO_CORE_CLK(pipe
), coreclk
);
4537 vlv_dpio_write(dev_priv
, pipe
, DPIO_PLL_CML(pipe
), 0x87871000);
4539 /* Enable DPIO clock input */
4540 dpll
= DPLL_EXT_BUFFER_ENABLE_VLV
| DPLL_REFA_CLK_ENABLE_VLV
|
4541 DPLL_VGA_MODE_DIS
| DPLL_INTEGRATED_CLOCK_VLV
;
4543 dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
4545 dpll
|= DPLL_VCO_ENABLE
;
4546 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
4548 dpll_md
= (crtc
->config
.pixel_multiplier
- 1)
4549 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4550 crtc
->config
.dpll_hw_state
.dpll_md
= dpll_md
;
4552 if (crtc
->config
.has_dp_encoder
)
4553 intel_dp_set_m_n(crtc
);
4555 mutex_unlock(&dev_priv
->dpio_lock
);
4558 static void i9xx_update_pll(struct intel_crtc
*crtc
,
4559 intel_clock_t
*reduced_clock
,
4562 struct drm_device
*dev
= crtc
->base
.dev
;
4563 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4566 struct dpll
*clock
= &crtc
->config
.dpll
;
4568 i9xx_update_pll_dividers(crtc
, reduced_clock
);
4570 is_sdvo
= intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_SDVO
) ||
4571 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
);
4573 dpll
= DPLL_VGA_MODE_DIS
;
4575 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
))
4576 dpll
|= DPLLB_MODE_LVDS
;
4578 dpll
|= DPLLB_MODE_DAC_SERIAL
;
4580 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
4581 dpll
|= (crtc
->config
.pixel_multiplier
- 1)
4582 << SDVO_MULTIPLIER_SHIFT_HIRES
;
4586 dpll
|= DPLL_SDVO_HIGH_SPEED
;
4588 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
))
4589 dpll
|= DPLL_SDVO_HIGH_SPEED
;
4591 /* compute bitmask from p1 value */
4592 if (IS_PINEVIEW(dev
))
4593 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
4595 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4596 if (IS_G4X(dev
) && reduced_clock
)
4597 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
4599 switch (clock
->p2
) {
4601 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
4604 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
4607 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
4610 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
4613 if (INTEL_INFO(dev
)->gen
>= 4)
4614 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
4616 if (crtc
->config
.sdvo_tv_clock
)
4617 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
4618 else if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4619 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4620 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4622 dpll
|= PLL_REF_INPUT_DREFCLK
;
4624 dpll
|= DPLL_VCO_ENABLE
;
4625 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
4627 if (INTEL_INFO(dev
)->gen
>= 4) {
4628 u32 dpll_md
= (crtc
->config
.pixel_multiplier
- 1)
4629 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4630 crtc
->config
.dpll_hw_state
.dpll_md
= dpll_md
;
4633 if (crtc
->config
.has_dp_encoder
)
4634 intel_dp_set_m_n(crtc
);
4637 static void i8xx_update_pll(struct intel_crtc
*crtc
,
4638 intel_clock_t
*reduced_clock
,
4641 struct drm_device
*dev
= crtc
->base
.dev
;
4642 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4644 struct dpll
*clock
= &crtc
->config
.dpll
;
4646 i9xx_update_pll_dividers(crtc
, reduced_clock
);
4648 dpll
= DPLL_VGA_MODE_DIS
;
4650 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
)) {
4651 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4654 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
4656 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4658 dpll
|= PLL_P2_DIVIDE_BY_4
;
4661 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DVO
))
4662 dpll
|= DPLL_DVO_2X_MODE
;
4664 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4665 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4666 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4668 dpll
|= PLL_REF_INPUT_DREFCLK
;
4670 dpll
|= DPLL_VCO_ENABLE
;
4671 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
4674 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
4676 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4677 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4678 enum pipe pipe
= intel_crtc
->pipe
;
4679 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
4680 struct drm_display_mode
*adjusted_mode
=
4681 &intel_crtc
->config
.adjusted_mode
;
4682 struct drm_display_mode
*mode
= &intel_crtc
->config
.requested_mode
;
4683 uint32_t vsyncshift
, crtc_vtotal
, crtc_vblank_end
;
4685 /* We need to be careful not to changed the adjusted mode, for otherwise
4686 * the hw state checker will get angry at the mismatch. */
4687 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
4688 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
4690 if (!IS_GEN2(dev
) && adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
4691 /* the chip adds 2 halflines automatically */
4693 crtc_vblank_end
-= 1;
4694 vsyncshift
= adjusted_mode
->crtc_hsync_start
4695 - adjusted_mode
->crtc_htotal
/ 2;
4700 if (INTEL_INFO(dev
)->gen
> 3)
4701 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
4703 I915_WRITE(HTOTAL(cpu_transcoder
),
4704 (adjusted_mode
->crtc_hdisplay
- 1) |
4705 ((adjusted_mode
->crtc_htotal
- 1) << 16));
4706 I915_WRITE(HBLANK(cpu_transcoder
),
4707 (adjusted_mode
->crtc_hblank_start
- 1) |
4708 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
4709 I915_WRITE(HSYNC(cpu_transcoder
),
4710 (adjusted_mode
->crtc_hsync_start
- 1) |
4711 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
4713 I915_WRITE(VTOTAL(cpu_transcoder
),
4714 (adjusted_mode
->crtc_vdisplay
- 1) |
4715 ((crtc_vtotal
- 1) << 16));
4716 I915_WRITE(VBLANK(cpu_transcoder
),
4717 (adjusted_mode
->crtc_vblank_start
- 1) |
4718 ((crtc_vblank_end
- 1) << 16));
4719 I915_WRITE(VSYNC(cpu_transcoder
),
4720 (adjusted_mode
->crtc_vsync_start
- 1) |
4721 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
4723 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4724 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4725 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4727 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
4728 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
4729 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
4731 /* pipesrc controls the size that is scaled from, which should
4732 * always be the user's requested size.
4734 I915_WRITE(PIPESRC(pipe
),
4735 ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
4738 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
4739 struct intel_crtc_config
*pipe_config
)
4741 struct drm_device
*dev
= crtc
->base
.dev
;
4742 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4743 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
4746 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
4747 pipe_config
->adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
4748 pipe_config
->adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
4749 tmp
= I915_READ(HBLANK(cpu_transcoder
));
4750 pipe_config
->adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
4751 pipe_config
->adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
4752 tmp
= I915_READ(HSYNC(cpu_transcoder
));
4753 pipe_config
->adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
4754 pipe_config
->adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
4756 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
4757 pipe_config
->adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
4758 pipe_config
->adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
4759 tmp
= I915_READ(VBLANK(cpu_transcoder
));
4760 pipe_config
->adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
4761 pipe_config
->adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
4762 tmp
= I915_READ(VSYNC(cpu_transcoder
));
4763 pipe_config
->adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
4764 pipe_config
->adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
4766 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
4767 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
4768 pipe_config
->adjusted_mode
.crtc_vtotal
+= 1;
4769 pipe_config
->adjusted_mode
.crtc_vblank_end
+= 1;
4772 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
4773 pipe_config
->requested_mode
.vdisplay
= (tmp
& 0xffff) + 1;
4774 pipe_config
->requested_mode
.hdisplay
= ((tmp
>> 16) & 0xffff) + 1;
4777 static void intel_crtc_mode_from_pipe_config(struct intel_crtc
*intel_crtc
,
4778 struct intel_crtc_config
*pipe_config
)
4780 struct drm_crtc
*crtc
= &intel_crtc
->base
;
4782 crtc
->mode
.hdisplay
= pipe_config
->adjusted_mode
.crtc_hdisplay
;
4783 crtc
->mode
.htotal
= pipe_config
->adjusted_mode
.crtc_htotal
;
4784 crtc
->mode
.hsync_start
= pipe_config
->adjusted_mode
.crtc_hsync_start
;
4785 crtc
->mode
.hsync_end
= pipe_config
->adjusted_mode
.crtc_hsync_end
;
4787 crtc
->mode
.vdisplay
= pipe_config
->adjusted_mode
.crtc_vdisplay
;
4788 crtc
->mode
.vtotal
= pipe_config
->adjusted_mode
.crtc_vtotal
;
4789 crtc
->mode
.vsync_start
= pipe_config
->adjusted_mode
.crtc_vsync_start
;
4790 crtc
->mode
.vsync_end
= pipe_config
->adjusted_mode
.crtc_vsync_end
;
4792 crtc
->mode
.flags
= pipe_config
->adjusted_mode
.flags
;
4794 crtc
->mode
.clock
= pipe_config
->adjusted_mode
.clock
;
4795 crtc
->mode
.flags
|= pipe_config
->adjusted_mode
.flags
;
4798 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
4800 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4801 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4806 if (intel_crtc
->pipe
== 0 && INTEL_INFO(dev
)->gen
< 4) {
4807 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4810 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4813 if (intel_crtc
->config
.adjusted_mode
.clock
>
4814 dev_priv
->display
.get_display_clock_speed(dev
) * 9 / 10)
4815 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
4818 /* only g4x and later have fancy bpc/dither controls */
4819 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
4820 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4821 if (intel_crtc
->config
.dither
&& intel_crtc
->config
.pipe_bpp
!= 30)
4822 pipeconf
|= PIPECONF_DITHER_EN
|
4823 PIPECONF_DITHER_TYPE_SP
;
4825 switch (intel_crtc
->config
.pipe_bpp
) {
4827 pipeconf
|= PIPECONF_6BPC
;
4830 pipeconf
|= PIPECONF_8BPC
;
4833 pipeconf
|= PIPECONF_10BPC
;
4836 /* Case prevented by intel_choose_pipe_bpp_dither. */
4841 if (HAS_PIPE_CXSR(dev
)) {
4842 if (intel_crtc
->lowfreq_avail
) {
4843 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4844 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
4846 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4850 if (!IS_GEN2(dev
) &&
4851 intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
4852 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
4854 pipeconf
|= PIPECONF_PROGRESSIVE
;
4856 if (IS_VALLEYVIEW(dev
) && intel_crtc
->config
.limited_color_range
)
4857 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
4859 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
4860 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
4863 static int i9xx_crtc_mode_set(struct drm_crtc
*crtc
,
4865 struct drm_framebuffer
*fb
)
4867 struct drm_device
*dev
= crtc
->dev
;
4868 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4869 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4870 struct drm_display_mode
*mode
= &intel_crtc
->config
.requested_mode
;
4871 int pipe
= intel_crtc
->pipe
;
4872 int plane
= intel_crtc
->plane
;
4873 int refclk
, num_connectors
= 0;
4874 intel_clock_t clock
, reduced_clock
;
4876 bool ok
, has_reduced_clock
= false;
4877 bool is_lvds
= false, is_dsi
= false;
4878 struct intel_encoder
*encoder
;
4879 const intel_limit_t
*limit
;
4882 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4883 switch (encoder
->type
) {
4884 case INTEL_OUTPUT_LVDS
:
4887 case INTEL_OUTPUT_DSI
:
4895 refclk
= i9xx_get_refclk(crtc
, num_connectors
);
4897 if (!is_dsi
&& !intel_crtc
->config
.clock_set
) {
4899 * Returns a set of divisors for the desired target clock with
4900 * the given refclk, or FALSE. The returned values represent
4901 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
4904 limit
= intel_limit(crtc
, refclk
);
4905 ok
= dev_priv
->display
.find_dpll(limit
, crtc
,
4906 intel_crtc
->config
.port_clock
,
4907 refclk
, NULL
, &clock
);
4908 if (!ok
&& !intel_crtc
->config
.clock_set
) {
4909 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4914 /* Ensure that the cursor is valid for the new mode before changing... */
4915 intel_crtc_update_cursor(crtc
, true);
4917 if (!is_dsi
&& is_lvds
&& dev_priv
->lvds_downclock_avail
) {
4919 * Ensure we match the reduced clock's P to the target clock.
4920 * If the clocks don't match, we can't switch the display clock
4921 * by using the FP0/FP1. In such case we will disable the LVDS
4922 * downclock feature.
4924 limit
= intel_limit(crtc
, refclk
);
4926 dev_priv
->display
.find_dpll(limit
, crtc
,
4927 dev_priv
->lvds_downclock
,
4931 /* Compat-code for transition, will disappear. */
4932 if (!intel_crtc
->config
.clock_set
) {
4933 intel_crtc
->config
.dpll
.n
= clock
.n
;
4934 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
4935 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
4936 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
4937 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
4941 i8xx_update_pll(intel_crtc
,
4942 has_reduced_clock
? &reduced_clock
: NULL
,
4944 } else if (IS_VALLEYVIEW(dev
)) {
4946 vlv_update_pll(intel_crtc
);
4948 i9xx_update_pll(intel_crtc
,
4949 has_reduced_clock
? &reduced_clock
: NULL
,
4953 /* Set up the display plane register */
4954 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
4956 if (!IS_VALLEYVIEW(dev
)) {
4958 dspcntr
&= ~DISPPLANE_SEL_PIPE_MASK
;
4960 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
4963 intel_set_pipe_timings(intel_crtc
);
4965 /* pipesrc and dspsize control the size that is scaled from,
4966 * which should always be the user's requested size.
4968 I915_WRITE(DSPSIZE(plane
),
4969 ((mode
->vdisplay
- 1) << 16) |
4970 (mode
->hdisplay
- 1));
4971 I915_WRITE(DSPPOS(plane
), 0);
4973 i9xx_set_pipeconf(intel_crtc
);
4975 I915_WRITE(DSPCNTR(plane
), dspcntr
);
4976 POSTING_READ(DSPCNTR(plane
));
4978 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
4983 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
4984 struct intel_crtc_config
*pipe_config
)
4986 struct drm_device
*dev
= crtc
->base
.dev
;
4987 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4990 tmp
= I915_READ(PFIT_CONTROL
);
4991 if (!(tmp
& PFIT_ENABLE
))
4994 /* Check whether the pfit is attached to our pipe. */
4995 if (INTEL_INFO(dev
)->gen
< 4) {
4996 if (crtc
->pipe
!= PIPE_B
)
4999 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
5003 pipe_config
->gmch_pfit
.control
= tmp
;
5004 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
5005 if (INTEL_INFO(dev
)->gen
< 5)
5006 pipe_config
->gmch_pfit
.lvds_border_bits
=
5007 I915_READ(LVDS
) & LVDS_BORDER_ENABLE
;
5010 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
5011 struct intel_crtc_config
*pipe_config
)
5013 struct drm_device
*dev
= crtc
->base
.dev
;
5014 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5017 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
5018 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
5020 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
5021 if (!(tmp
& PIPECONF_ENABLE
))
5024 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
5025 switch (tmp
& PIPECONF_BPC_MASK
) {
5027 pipe_config
->pipe_bpp
= 18;
5030 pipe_config
->pipe_bpp
= 24;
5032 case PIPECONF_10BPC
:
5033 pipe_config
->pipe_bpp
= 30;
5040 intel_get_pipe_timings(crtc
, pipe_config
);
5042 i9xx_get_pfit_config(crtc
, pipe_config
);
5044 if (INTEL_INFO(dev
)->gen
>= 4) {
5045 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
5046 pipe_config
->pixel_multiplier
=
5047 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
5048 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
5049 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
5050 } else if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
5051 tmp
= I915_READ(DPLL(crtc
->pipe
));
5052 pipe_config
->pixel_multiplier
=
5053 ((tmp
& SDVO_MULTIPLIER_MASK
)
5054 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
5056 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5057 * port and will be fixed up in the encoder->get_config
5059 pipe_config
->pixel_multiplier
= 1;
5061 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
5062 if (!IS_VALLEYVIEW(dev
)) {
5063 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
5064 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
5066 /* Mask out read-only status bits. */
5067 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
5068 DPLL_PORTC_READY_MASK
|
5069 DPLL_PORTB_READY_MASK
);
5072 i9xx_crtc_clock_get(crtc
, pipe_config
);
5077 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
5079 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5080 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
5081 struct intel_encoder
*encoder
;
5083 bool has_lvds
= false;
5084 bool has_cpu_edp
= false;
5085 bool has_panel
= false;
5086 bool has_ck505
= false;
5087 bool can_ssc
= false;
5089 /* We need to take the global config into account */
5090 list_for_each_entry(encoder
, &mode_config
->encoder_list
,
5092 switch (encoder
->type
) {
5093 case INTEL_OUTPUT_LVDS
:
5097 case INTEL_OUTPUT_EDP
:
5099 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
5105 if (HAS_PCH_IBX(dev
)) {
5106 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
5107 can_ssc
= has_ck505
;
5113 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5114 has_panel
, has_lvds
, has_ck505
);
5116 /* Ironlake: try to setup display ref clock before DPLL
5117 * enabling. This is only under driver's control after
5118 * PCH B stepping, previous chipset stepping should be
5119 * ignoring this setting.
5121 val
= I915_READ(PCH_DREF_CONTROL
);
5123 /* As we must carefully and slowly disable/enable each source in turn,
5124 * compute the final state we want first and check if we need to
5125 * make any changes at all.
5128 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
5130 final
|= DREF_NONSPREAD_CK505_ENABLE
;
5132 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
5134 final
&= ~DREF_SSC_SOURCE_MASK
;
5135 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
5136 final
&= ~DREF_SSC1_ENABLE
;
5139 final
|= DREF_SSC_SOURCE_ENABLE
;
5141 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
5142 final
|= DREF_SSC1_ENABLE
;
5145 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
5146 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
5148 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
5150 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5152 final
|= DREF_SSC_SOURCE_DISABLE
;
5153 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5159 /* Always enable nonspread source */
5160 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
5163 val
|= DREF_NONSPREAD_CK505_ENABLE
;
5165 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
5168 val
&= ~DREF_SSC_SOURCE_MASK
;
5169 val
|= DREF_SSC_SOURCE_ENABLE
;
5171 /* SSC must be turned on before enabling the CPU output */
5172 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
5173 DRM_DEBUG_KMS("Using SSC on panel\n");
5174 val
|= DREF_SSC1_ENABLE
;
5176 val
&= ~DREF_SSC1_ENABLE
;
5178 /* Get SSC going before enabling the outputs */
5179 I915_WRITE(PCH_DREF_CONTROL
, val
);
5180 POSTING_READ(PCH_DREF_CONTROL
);
5183 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
5185 /* Enable CPU source on CPU attached eDP */
5187 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
5188 DRM_DEBUG_KMS("Using SSC on eDP\n");
5189 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
5192 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
5194 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5196 I915_WRITE(PCH_DREF_CONTROL
, val
);
5197 POSTING_READ(PCH_DREF_CONTROL
);
5200 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5202 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
5204 /* Turn off CPU output */
5205 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5207 I915_WRITE(PCH_DREF_CONTROL
, val
);
5208 POSTING_READ(PCH_DREF_CONTROL
);
5211 /* Turn off the SSC source */
5212 val
&= ~DREF_SSC_SOURCE_MASK
;
5213 val
|= DREF_SSC_SOURCE_DISABLE
;
5216 val
&= ~DREF_SSC1_ENABLE
;
5218 I915_WRITE(PCH_DREF_CONTROL
, val
);
5219 POSTING_READ(PCH_DREF_CONTROL
);
5223 BUG_ON(val
!= final
);
5226 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
5230 tmp
= I915_READ(SOUTH_CHICKEN2
);
5231 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
5232 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
5234 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
5235 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
5236 DRM_ERROR("FDI mPHY reset assert timeout\n");
5238 tmp
= I915_READ(SOUTH_CHICKEN2
);
5239 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
5240 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
5242 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
5243 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
5244 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5247 /* WaMPhyProgramming:hsw */
5248 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
5252 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
5253 tmp
&= ~(0xFF << 24);
5254 tmp
|= (0x12 << 24);
5255 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
5257 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
5259 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
5261 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
5263 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
5265 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
5266 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
5267 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
5269 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
5270 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
5271 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
5273 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
5276 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
5278 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
5281 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
5283 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
5286 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
5288 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
5291 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
5293 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
5294 tmp
&= ~(0xFF << 16);
5295 tmp
|= (0x1C << 16);
5296 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
5298 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
5299 tmp
&= ~(0xFF << 16);
5300 tmp
|= (0x1C << 16);
5301 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
5303 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
5305 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
5307 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
5309 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
5311 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
5312 tmp
&= ~(0xF << 28);
5314 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
5316 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
5317 tmp
&= ~(0xF << 28);
5319 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
5322 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5323 * Programming" based on the parameters passed:
5324 * - Sequence to enable CLKOUT_DP
5325 * - Sequence to enable CLKOUT_DP without spread
5326 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5328 static void lpt_enable_clkout_dp(struct drm_device
*dev
, bool with_spread
,
5331 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5334 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
5336 if (WARN(dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
&&
5337 with_fdi
, "LP PCH doesn't have FDI\n"))
5340 mutex_lock(&dev_priv
->dpio_lock
);
5342 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
5343 tmp
&= ~SBI_SSCCTL_DISABLE
;
5344 tmp
|= SBI_SSCCTL_PATHALT
;
5345 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5350 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
5351 tmp
&= ~SBI_SSCCTL_PATHALT
;
5352 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5355 lpt_reset_fdi_mphy(dev_priv
);
5356 lpt_program_fdi_mphy(dev_priv
);
5360 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
5361 SBI_GEN0
: SBI_DBUFF0
;
5362 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
5363 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
5364 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
5366 mutex_unlock(&dev_priv
->dpio_lock
);
5369 /* Sequence to disable CLKOUT_DP */
5370 static void lpt_disable_clkout_dp(struct drm_device
*dev
)
5372 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5375 mutex_lock(&dev_priv
->dpio_lock
);
5377 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
5378 SBI_GEN0
: SBI_DBUFF0
;
5379 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
5380 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
5381 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
5383 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
5384 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
5385 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
5386 tmp
|= SBI_SSCCTL_PATHALT
;
5387 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5390 tmp
|= SBI_SSCCTL_DISABLE
;
5391 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5394 mutex_unlock(&dev_priv
->dpio_lock
);
5397 static void lpt_init_pch_refclk(struct drm_device
*dev
)
5399 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
5400 struct intel_encoder
*encoder
;
5401 bool has_vga
= false;
5403 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
) {
5404 switch (encoder
->type
) {
5405 case INTEL_OUTPUT_ANALOG
:
5412 lpt_enable_clkout_dp(dev
, true, true);
5414 lpt_disable_clkout_dp(dev
);
5418 * Initialize reference clocks when the driver loads
5420 void intel_init_pch_refclk(struct drm_device
*dev
)
5422 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
5423 ironlake_init_pch_refclk(dev
);
5424 else if (HAS_PCH_LPT(dev
))
5425 lpt_init_pch_refclk(dev
);
5428 static int ironlake_get_refclk(struct drm_crtc
*crtc
)
5430 struct drm_device
*dev
= crtc
->dev
;
5431 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5432 struct intel_encoder
*encoder
;
5433 int num_connectors
= 0;
5434 bool is_lvds
= false;
5436 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5437 switch (encoder
->type
) {
5438 case INTEL_OUTPUT_LVDS
:
5445 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
5446 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5447 dev_priv
->vbt
.lvds_ssc_freq
);
5448 return dev_priv
->vbt
.lvds_ssc_freq
* 1000;
5454 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
5456 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
5457 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5458 int pipe
= intel_crtc
->pipe
;
5463 switch (intel_crtc
->config
.pipe_bpp
) {
5465 val
|= PIPECONF_6BPC
;
5468 val
|= PIPECONF_8BPC
;
5471 val
|= PIPECONF_10BPC
;
5474 val
|= PIPECONF_12BPC
;
5477 /* Case prevented by intel_choose_pipe_bpp_dither. */
5481 if (intel_crtc
->config
.dither
)
5482 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
5484 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
5485 val
|= PIPECONF_INTERLACED_ILK
;
5487 val
|= PIPECONF_PROGRESSIVE
;
5489 if (intel_crtc
->config
.limited_color_range
)
5490 val
|= PIPECONF_COLOR_RANGE_SELECT
;
5492 I915_WRITE(PIPECONF(pipe
), val
);
5493 POSTING_READ(PIPECONF(pipe
));
5497 * Set up the pipe CSC unit.
5499 * Currently only full range RGB to limited range RGB conversion
5500 * is supported, but eventually this should handle various
5501 * RGB<->YCbCr scenarios as well.
5503 static void intel_set_pipe_csc(struct drm_crtc
*crtc
)
5505 struct drm_device
*dev
= crtc
->dev
;
5506 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5507 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5508 int pipe
= intel_crtc
->pipe
;
5509 uint16_t coeff
= 0x7800; /* 1.0 */
5512 * TODO: Check what kind of values actually come out of the pipe
5513 * with these coeff/postoff values and adjust to get the best
5514 * accuracy. Perhaps we even need to take the bpc value into
5518 if (intel_crtc
->config
.limited_color_range
)
5519 coeff
= ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5522 * GY/GU and RY/RU should be the other way around according
5523 * to BSpec, but reality doesn't agree. Just set them up in
5524 * a way that results in the correct picture.
5526 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeff
<< 16);
5527 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), 0);
5529 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeff
);
5530 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), 0);
5532 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), 0);
5533 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeff
<< 16);
5535 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
5536 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
5537 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
5539 if (INTEL_INFO(dev
)->gen
> 6) {
5540 uint16_t postoff
= 0;
5542 if (intel_crtc
->config
.limited_color_range
)
5543 postoff
= (16 * (1 << 13) / 255) & 0x1fff;
5545 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
5546 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
5547 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
5549 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
5551 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
5553 if (intel_crtc
->config
.limited_color_range
)
5554 mode
|= CSC_BLACK_SCREEN_OFFSET
;
5556 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
5560 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
5562 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
5563 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5564 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
5569 if (intel_crtc
->config
.dither
)
5570 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
5572 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
5573 val
|= PIPECONF_INTERLACED_ILK
;
5575 val
|= PIPECONF_PROGRESSIVE
;
5577 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
5578 POSTING_READ(PIPECONF(cpu_transcoder
));
5580 I915_WRITE(GAMMA_MODE(intel_crtc
->pipe
), GAMMA_MODE_MODE_8BIT
);
5581 POSTING_READ(GAMMA_MODE(intel_crtc
->pipe
));
5584 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
5585 intel_clock_t
*clock
,
5586 bool *has_reduced_clock
,
5587 intel_clock_t
*reduced_clock
)
5589 struct drm_device
*dev
= crtc
->dev
;
5590 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5591 struct intel_encoder
*intel_encoder
;
5593 const intel_limit_t
*limit
;
5594 bool ret
, is_lvds
= false;
5596 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5597 switch (intel_encoder
->type
) {
5598 case INTEL_OUTPUT_LVDS
:
5604 refclk
= ironlake_get_refclk(crtc
);
5607 * Returns a set of divisors for the desired target clock with the given
5608 * refclk, or FALSE. The returned values represent the clock equation:
5609 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5611 limit
= intel_limit(crtc
, refclk
);
5612 ret
= dev_priv
->display
.find_dpll(limit
, crtc
,
5613 to_intel_crtc(crtc
)->config
.port_clock
,
5614 refclk
, NULL
, clock
);
5618 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
5620 * Ensure we match the reduced clock's P to the target clock.
5621 * If the clocks don't match, we can't switch the display clock
5622 * by using the FP0/FP1. In such case we will disable the LVDS
5623 * downclock feature.
5625 *has_reduced_clock
=
5626 dev_priv
->display
.find_dpll(limit
, crtc
,
5627 dev_priv
->lvds_downclock
,
5635 static void cpt_enable_fdi_bc_bifurcation(struct drm_device
*dev
)
5637 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5640 temp
= I915_READ(SOUTH_CHICKEN1
);
5641 if (temp
& FDI_BC_BIFURCATION_SELECT
)
5644 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
5645 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
5647 temp
|= FDI_BC_BIFURCATION_SELECT
;
5648 DRM_DEBUG_KMS("enabling fdi C rx\n");
5649 I915_WRITE(SOUTH_CHICKEN1
, temp
);
5650 POSTING_READ(SOUTH_CHICKEN1
);
5653 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
5655 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5656 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5658 switch (intel_crtc
->pipe
) {
5662 if (intel_crtc
->config
.fdi_lanes
> 2)
5663 WARN_ON(I915_READ(SOUTH_CHICKEN1
) & FDI_BC_BIFURCATION_SELECT
);
5665 cpt_enable_fdi_bc_bifurcation(dev
);
5669 cpt_enable_fdi_bc_bifurcation(dev
);
5677 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
5680 * Account for spread spectrum to avoid
5681 * oversubscribing the link. Max center spread
5682 * is 2.5%; use 5% for safety's sake.
5684 u32 bps
= target_clock
* bpp
* 21 / 20;
5685 return bps
/ (link_bw
* 8) + 1;
5688 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
5690 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
5693 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
5695 intel_clock_t
*reduced_clock
, u32
*fp2
)
5697 struct drm_crtc
*crtc
= &intel_crtc
->base
;
5698 struct drm_device
*dev
= crtc
->dev
;
5699 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5700 struct intel_encoder
*intel_encoder
;
5702 int factor
, num_connectors
= 0;
5703 bool is_lvds
= false, is_sdvo
= false;
5705 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5706 switch (intel_encoder
->type
) {
5707 case INTEL_OUTPUT_LVDS
:
5710 case INTEL_OUTPUT_SDVO
:
5711 case INTEL_OUTPUT_HDMI
:
5719 /* Enable autotuning of the PLL clock (if permissible) */
5722 if ((intel_panel_use_ssc(dev_priv
) &&
5723 dev_priv
->vbt
.lvds_ssc_freq
== 100) ||
5724 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
5726 } else if (intel_crtc
->config
.sdvo_tv_clock
)
5729 if (ironlake_needs_fb_cb_tune(&intel_crtc
->config
.dpll
, factor
))
5732 if (fp2
&& (reduced_clock
->m
< factor
* reduced_clock
->n
))
5738 dpll
|= DPLLB_MODE_LVDS
;
5740 dpll
|= DPLLB_MODE_DAC_SERIAL
;
5742 dpll
|= (intel_crtc
->config
.pixel_multiplier
- 1)
5743 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
5746 dpll
|= DPLL_SDVO_HIGH_SPEED
;
5747 if (intel_crtc
->config
.has_dp_encoder
)
5748 dpll
|= DPLL_SDVO_HIGH_SPEED
;
5750 /* compute bitmask from p1 value */
5751 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5753 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
5755 switch (intel_crtc
->config
.dpll
.p2
) {
5757 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
5760 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
5763 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
5766 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
5770 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
5771 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
5773 dpll
|= PLL_REF_INPUT_DREFCLK
;
5775 return dpll
| DPLL_VCO_ENABLE
;
5778 static int ironlake_crtc_mode_set(struct drm_crtc
*crtc
,
5780 struct drm_framebuffer
*fb
)
5782 struct drm_device
*dev
= crtc
->dev
;
5783 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5784 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5785 int pipe
= intel_crtc
->pipe
;
5786 int plane
= intel_crtc
->plane
;
5787 int num_connectors
= 0;
5788 intel_clock_t clock
, reduced_clock
;
5789 u32 dpll
= 0, fp
= 0, fp2
= 0;
5790 bool ok
, has_reduced_clock
= false;
5791 bool is_lvds
= false;
5792 struct intel_encoder
*encoder
;
5793 struct intel_shared_dpll
*pll
;
5796 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5797 switch (encoder
->type
) {
5798 case INTEL_OUTPUT_LVDS
:
5806 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
5807 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
5809 ok
= ironlake_compute_clocks(crtc
, &clock
,
5810 &has_reduced_clock
, &reduced_clock
);
5811 if (!ok
&& !intel_crtc
->config
.clock_set
) {
5812 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5815 /* Compat-code for transition, will disappear. */
5816 if (!intel_crtc
->config
.clock_set
) {
5817 intel_crtc
->config
.dpll
.n
= clock
.n
;
5818 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
5819 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
5820 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
5821 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
5824 /* Ensure that the cursor is valid for the new mode before changing... */
5825 intel_crtc_update_cursor(crtc
, true);
5827 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5828 if (intel_crtc
->config
.has_pch_encoder
) {
5829 fp
= i9xx_dpll_compute_fp(&intel_crtc
->config
.dpll
);
5830 if (has_reduced_clock
)
5831 fp2
= i9xx_dpll_compute_fp(&reduced_clock
);
5833 dpll
= ironlake_compute_dpll(intel_crtc
,
5834 &fp
, &reduced_clock
,
5835 has_reduced_clock
? &fp2
: NULL
);
5837 intel_crtc
->config
.dpll_hw_state
.dpll
= dpll
;
5838 intel_crtc
->config
.dpll_hw_state
.fp0
= fp
;
5839 if (has_reduced_clock
)
5840 intel_crtc
->config
.dpll_hw_state
.fp1
= fp2
;
5842 intel_crtc
->config
.dpll_hw_state
.fp1
= fp
;
5844 pll
= intel_get_shared_dpll(intel_crtc
);
5846 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5851 intel_put_shared_dpll(intel_crtc
);
5853 if (intel_crtc
->config
.has_dp_encoder
)
5854 intel_dp_set_m_n(intel_crtc
);
5856 if (is_lvds
&& has_reduced_clock
&& i915_powersave
)
5857 intel_crtc
->lowfreq_avail
= true;
5859 intel_crtc
->lowfreq_avail
= false;
5861 if (intel_crtc
->config
.has_pch_encoder
) {
5862 pll
= intel_crtc_to_shared_dpll(intel_crtc
);
5866 intel_set_pipe_timings(intel_crtc
);
5868 if (intel_crtc
->config
.has_pch_encoder
) {
5869 intel_cpu_transcoder_set_m_n(intel_crtc
,
5870 &intel_crtc
->config
.fdi_m_n
);
5873 if (IS_IVYBRIDGE(dev
))
5874 ivybridge_update_fdi_bc_bifurcation(intel_crtc
);
5876 ironlake_set_pipeconf(crtc
);
5878 /* Set up the display plane register */
5879 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
);
5880 POSTING_READ(DSPCNTR(plane
));
5882 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
5887 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
5888 struct intel_link_m_n
*m_n
)
5890 struct drm_device
*dev
= crtc
->base
.dev
;
5891 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5892 enum pipe pipe
= crtc
->pipe
;
5894 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
5895 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
5896 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
5898 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
5899 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
5900 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
5903 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
5904 enum transcoder transcoder
,
5905 struct intel_link_m_n
*m_n
)
5907 struct drm_device
*dev
= crtc
->base
.dev
;
5908 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5909 enum pipe pipe
= crtc
->pipe
;
5911 if (INTEL_INFO(dev
)->gen
>= 5) {
5912 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
5913 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
5914 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
5916 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
5917 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
5918 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
5920 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
5921 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
5922 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
5924 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
5925 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
5926 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
5930 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
5931 struct intel_crtc_config
*pipe_config
)
5933 if (crtc
->config
.has_pch_encoder
)
5934 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
5936 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
5937 &pipe_config
->dp_m_n
);
5940 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
5941 struct intel_crtc_config
*pipe_config
)
5943 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
5944 &pipe_config
->fdi_m_n
);
5947 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
5948 struct intel_crtc_config
*pipe_config
)
5950 struct drm_device
*dev
= crtc
->base
.dev
;
5951 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5954 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
5956 if (tmp
& PF_ENABLE
) {
5957 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
5958 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
5960 /* We currently do not free assignements of panel fitters on
5961 * ivb/hsw (since we don't use the higher upscaling modes which
5962 * differentiates them) so just WARN about this case for now. */
5964 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
5965 PF_PIPE_SEL_IVB(crtc
->pipe
));
5970 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
5971 struct intel_crtc_config
*pipe_config
)
5973 struct drm_device
*dev
= crtc
->base
.dev
;
5974 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5977 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
5978 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
5980 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
5981 if (!(tmp
& PIPECONF_ENABLE
))
5984 switch (tmp
& PIPECONF_BPC_MASK
) {
5986 pipe_config
->pipe_bpp
= 18;
5989 pipe_config
->pipe_bpp
= 24;
5991 case PIPECONF_10BPC
:
5992 pipe_config
->pipe_bpp
= 30;
5994 case PIPECONF_12BPC
:
5995 pipe_config
->pipe_bpp
= 36;
6001 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
6002 struct intel_shared_dpll
*pll
;
6004 pipe_config
->has_pch_encoder
= true;
6006 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
6007 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
6008 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
6010 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
6012 if (HAS_PCH_IBX(dev_priv
->dev
)) {
6013 pipe_config
->shared_dpll
=
6014 (enum intel_dpll_id
) crtc
->pipe
;
6016 tmp
= I915_READ(PCH_DPLL_SEL
);
6017 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
6018 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_B
;
6020 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_A
;
6023 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
6025 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
6026 &pipe_config
->dpll_hw_state
));
6028 tmp
= pipe_config
->dpll_hw_state
.dpll
;
6029 pipe_config
->pixel_multiplier
=
6030 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
6031 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
6033 ironlake_pch_clock_get(crtc
, pipe_config
);
6035 pipe_config
->pixel_multiplier
= 1;
6038 intel_get_pipe_timings(crtc
, pipe_config
);
6040 ironlake_get_pfit_config(crtc
, pipe_config
);
6045 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
6047 struct drm_device
*dev
= dev_priv
->dev
;
6048 struct intel_ddi_plls
*plls
= &dev_priv
->ddi_plls
;
6049 struct intel_crtc
*crtc
;
6050 unsigned long irqflags
;
6053 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
)
6054 WARN(crtc
->base
.enabled
, "CRTC for pipe %c enabled\n",
6055 pipe_name(crtc
->pipe
));
6057 WARN(I915_READ(HSW_PWR_WELL_DRIVER
), "Power well on\n");
6058 WARN(plls
->spll_refcount
, "SPLL enabled\n");
6059 WARN(plls
->wrpll1_refcount
, "WRPLL1 enabled\n");
6060 WARN(plls
->wrpll2_refcount
, "WRPLL2 enabled\n");
6061 WARN(I915_READ(PCH_PP_STATUS
) & PP_ON
, "Panel power on\n");
6062 WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
6063 "CPU PWM1 enabled\n");
6064 WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
6065 "CPU PWM2 enabled\n");
6066 WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
6067 "PCH PWM1 enabled\n");
6068 WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
6069 "Utility pin enabled\n");
6070 WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
6072 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
6073 val
= I915_READ(DEIMR
);
6074 WARN((val
& ~DE_PCH_EVENT_IVB
) != val
,
6075 "Unexpected DEIMR bits enabled: 0x%x\n", val
);
6076 val
= I915_READ(SDEIMR
);
6077 WARN((val
| SDE_HOTPLUG_MASK_CPT
) != 0xffffffff,
6078 "Unexpected SDEIMR bits enabled: 0x%x\n", val
);
6079 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
6083 * This function implements pieces of two sequences from BSpec:
6084 * - Sequence for display software to disable LCPLL
6085 * - Sequence for display software to allow package C8+
6086 * The steps implemented here are just the steps that actually touch the LCPLL
6087 * register. Callers should take care of disabling all the display engine
6088 * functions, doing the mode unset, fixing interrupts, etc.
6090 void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
6091 bool switch_to_fclk
, bool allow_power_down
)
6095 assert_can_disable_lcpll(dev_priv
);
6097 val
= I915_READ(LCPLL_CTL
);
6099 if (switch_to_fclk
) {
6100 val
|= LCPLL_CD_SOURCE_FCLK
;
6101 I915_WRITE(LCPLL_CTL
, val
);
6103 if (wait_for_atomic_us(I915_READ(LCPLL_CTL
) &
6104 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
6105 DRM_ERROR("Switching to FCLK failed\n");
6107 val
= I915_READ(LCPLL_CTL
);
6110 val
|= LCPLL_PLL_DISABLE
;
6111 I915_WRITE(LCPLL_CTL
, val
);
6112 POSTING_READ(LCPLL_CTL
);
6114 if (wait_for((I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
) == 0, 1))
6115 DRM_ERROR("LCPLL still locked\n");
6117 val
= I915_READ(D_COMP
);
6118 val
|= D_COMP_COMP_DISABLE
;
6119 I915_WRITE(D_COMP
, val
);
6120 POSTING_READ(D_COMP
);
6123 if (wait_for((I915_READ(D_COMP
) & D_COMP_RCOMP_IN_PROGRESS
) == 0, 1))
6124 DRM_ERROR("D_COMP RCOMP still in progress\n");
6126 if (allow_power_down
) {
6127 val
= I915_READ(LCPLL_CTL
);
6128 val
|= LCPLL_POWER_DOWN_ALLOW
;
6129 I915_WRITE(LCPLL_CTL
, val
);
6130 POSTING_READ(LCPLL_CTL
);
6135 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6138 void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
6142 val
= I915_READ(LCPLL_CTL
);
6144 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
6145 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
6148 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6149 * we'll hang the machine! */
6150 dev_priv
->uncore
.funcs
.force_wake_get(dev_priv
);
6152 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
6153 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
6154 I915_WRITE(LCPLL_CTL
, val
);
6155 POSTING_READ(LCPLL_CTL
);
6158 val
= I915_READ(D_COMP
);
6159 val
|= D_COMP_COMP_FORCE
;
6160 val
&= ~D_COMP_COMP_DISABLE
;
6161 I915_WRITE(D_COMP
, val
);
6162 POSTING_READ(D_COMP
);
6164 val
= I915_READ(LCPLL_CTL
);
6165 val
&= ~LCPLL_PLL_DISABLE
;
6166 I915_WRITE(LCPLL_CTL
, val
);
6168 if (wait_for(I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
, 5))
6169 DRM_ERROR("LCPLL not locked yet\n");
6171 if (val
& LCPLL_CD_SOURCE_FCLK
) {
6172 val
= I915_READ(LCPLL_CTL
);
6173 val
&= ~LCPLL_CD_SOURCE_FCLK
;
6174 I915_WRITE(LCPLL_CTL
, val
);
6176 if (wait_for_atomic_us((I915_READ(LCPLL_CTL
) &
6177 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
6178 DRM_ERROR("Switching back to LCPLL failed\n");
6181 dev_priv
->uncore
.funcs
.force_wake_put(dev_priv
);
6184 void hsw_enable_pc8_work(struct work_struct
*__work
)
6186 struct drm_i915_private
*dev_priv
=
6187 container_of(to_delayed_work(__work
), struct drm_i915_private
,
6189 struct drm_device
*dev
= dev_priv
->dev
;
6192 if (dev_priv
->pc8
.enabled
)
6195 DRM_DEBUG_KMS("Enabling package C8+\n");
6197 dev_priv
->pc8
.enabled
= true;
6199 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
6200 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
6201 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
6202 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
6205 lpt_disable_clkout_dp(dev
);
6206 hsw_pc8_disable_interrupts(dev
);
6207 hsw_disable_lcpll(dev_priv
, true, true);
6210 static void __hsw_enable_package_c8(struct drm_i915_private
*dev_priv
)
6212 WARN_ON(!mutex_is_locked(&dev_priv
->pc8
.lock
));
6213 WARN(dev_priv
->pc8
.disable_count
< 1,
6214 "pc8.disable_count: %d\n", dev_priv
->pc8
.disable_count
);
6216 dev_priv
->pc8
.disable_count
--;
6217 if (dev_priv
->pc8
.disable_count
!= 0)
6220 schedule_delayed_work(&dev_priv
->pc8
.enable_work
,
6221 msecs_to_jiffies(i915_pc8_timeout
));
6224 static void __hsw_disable_package_c8(struct drm_i915_private
*dev_priv
)
6226 struct drm_device
*dev
= dev_priv
->dev
;
6229 WARN_ON(!mutex_is_locked(&dev_priv
->pc8
.lock
));
6230 WARN(dev_priv
->pc8
.disable_count
< 0,
6231 "pc8.disable_count: %d\n", dev_priv
->pc8
.disable_count
);
6233 dev_priv
->pc8
.disable_count
++;
6234 if (dev_priv
->pc8
.disable_count
!= 1)
6237 cancel_delayed_work_sync(&dev_priv
->pc8
.enable_work
);
6238 if (!dev_priv
->pc8
.enabled
)
6241 DRM_DEBUG_KMS("Disabling package C8+\n");
6243 hsw_restore_lcpll(dev_priv
);
6244 hsw_pc8_restore_interrupts(dev
);
6245 lpt_init_pch_refclk(dev
);
6247 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
6248 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
6249 val
|= PCH_LP_PARTITION_LEVEL_DISABLE
;
6250 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
6253 intel_prepare_ddi(dev
);
6254 i915_gem_init_swizzling(dev
);
6255 mutex_lock(&dev_priv
->rps
.hw_lock
);
6256 gen6_update_ring_freq(dev
);
6257 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6258 dev_priv
->pc8
.enabled
= false;
6261 void hsw_enable_package_c8(struct drm_i915_private
*dev_priv
)
6263 mutex_lock(&dev_priv
->pc8
.lock
);
6264 __hsw_enable_package_c8(dev_priv
);
6265 mutex_unlock(&dev_priv
->pc8
.lock
);
6268 void hsw_disable_package_c8(struct drm_i915_private
*dev_priv
)
6270 mutex_lock(&dev_priv
->pc8
.lock
);
6271 __hsw_disable_package_c8(dev_priv
);
6272 mutex_unlock(&dev_priv
->pc8
.lock
);
6275 static bool hsw_can_enable_package_c8(struct drm_i915_private
*dev_priv
)
6277 struct drm_device
*dev
= dev_priv
->dev
;
6278 struct intel_crtc
*crtc
;
6281 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
)
6282 if (crtc
->base
.enabled
)
6285 /* This case is still possible since we have the i915.disable_power_well
6286 * parameter and also the KVMr or something else might be requesting the
6288 val
= I915_READ(HSW_PWR_WELL_DRIVER
);
6290 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6297 /* Since we're called from modeset_global_resources there's no way to
6298 * symmetrically increase and decrease the refcount, so we use
6299 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6302 static void hsw_update_package_c8(struct drm_device
*dev
)
6304 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6307 if (!i915_enable_pc8
)
6310 mutex_lock(&dev_priv
->pc8
.lock
);
6312 allow
= hsw_can_enable_package_c8(dev_priv
);
6314 if (allow
== dev_priv
->pc8
.requirements_met
)
6317 dev_priv
->pc8
.requirements_met
= allow
;
6320 __hsw_enable_package_c8(dev_priv
);
6322 __hsw_disable_package_c8(dev_priv
);
6325 mutex_unlock(&dev_priv
->pc8
.lock
);
6328 static void hsw_package_c8_gpu_idle(struct drm_i915_private
*dev_priv
)
6330 if (!dev_priv
->pc8
.gpu_idle
) {
6331 dev_priv
->pc8
.gpu_idle
= true;
6332 hsw_enable_package_c8(dev_priv
);
6336 static void hsw_package_c8_gpu_busy(struct drm_i915_private
*dev_priv
)
6338 if (dev_priv
->pc8
.gpu_idle
) {
6339 dev_priv
->pc8
.gpu_idle
= false;
6340 hsw_disable_package_c8(dev_priv
);
6344 static void haswell_modeset_global_resources(struct drm_device
*dev
)
6346 bool enable
= false;
6347 struct intel_crtc
*crtc
;
6349 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
6350 if (!crtc
->base
.enabled
)
6353 if (crtc
->pipe
!= PIPE_A
|| crtc
->config
.pch_pfit
.size
||
6354 crtc
->config
.cpu_transcoder
!= TRANSCODER_EDP
)
6358 intel_set_power_well(dev
, enable
);
6360 hsw_update_package_c8(dev
);
6363 static int haswell_crtc_mode_set(struct drm_crtc
*crtc
,
6365 struct drm_framebuffer
*fb
)
6367 struct drm_device
*dev
= crtc
->dev
;
6368 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6369 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6370 int plane
= intel_crtc
->plane
;
6373 if (!intel_ddi_pll_mode_set(crtc
))
6376 /* Ensure that the cursor is valid for the new mode before changing... */
6377 intel_crtc_update_cursor(crtc
, true);
6379 if (intel_crtc
->config
.has_dp_encoder
)
6380 intel_dp_set_m_n(intel_crtc
);
6382 intel_crtc
->lowfreq_avail
= false;
6384 intel_set_pipe_timings(intel_crtc
);
6386 if (intel_crtc
->config
.has_pch_encoder
) {
6387 intel_cpu_transcoder_set_m_n(intel_crtc
,
6388 &intel_crtc
->config
.fdi_m_n
);
6391 haswell_set_pipeconf(crtc
);
6393 intel_set_pipe_csc(crtc
);
6395 /* Set up the display plane register */
6396 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
| DISPPLANE_PIPE_CSC_ENABLE
);
6397 POSTING_READ(DSPCNTR(plane
));
6399 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
6404 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
6405 struct intel_crtc_config
*pipe_config
)
6407 struct drm_device
*dev
= crtc
->base
.dev
;
6408 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6409 enum intel_display_power_domain pfit_domain
;
6412 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
6413 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
6415 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
6416 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
6417 enum pipe trans_edp_pipe
;
6418 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
6420 WARN(1, "unknown pipe linked to edp transcoder\n");
6421 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
6422 case TRANS_DDI_EDP_INPUT_A_ON
:
6423 trans_edp_pipe
= PIPE_A
;
6425 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
6426 trans_edp_pipe
= PIPE_B
;
6428 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
6429 trans_edp_pipe
= PIPE_C
;
6433 if (trans_edp_pipe
== crtc
->pipe
)
6434 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
6437 if (!intel_display_power_enabled(dev
,
6438 POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
)))
6441 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
6442 if (!(tmp
& PIPECONF_ENABLE
))
6446 * Haswell has only FDI/PCH transcoder A. It is which is connected to
6447 * DDI E. So just check whether this pipe is wired to DDI E and whether
6448 * the PCH transcoder is on.
6450 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
6451 if ((tmp
& TRANS_DDI_PORT_MASK
) == TRANS_DDI_SELECT_PORT(PORT_E
) &&
6452 I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
6453 pipe_config
->has_pch_encoder
= true;
6455 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
6456 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
6457 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
6459 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
6462 intel_get_pipe_timings(crtc
, pipe_config
);
6464 pfit_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
6465 if (intel_display_power_enabled(dev
, pfit_domain
))
6466 ironlake_get_pfit_config(crtc
, pipe_config
);
6468 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
6469 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
6471 pipe_config
->pixel_multiplier
= 1;
6476 static int intel_crtc_mode_set(struct drm_crtc
*crtc
,
6478 struct drm_framebuffer
*fb
)
6480 struct drm_device
*dev
= crtc
->dev
;
6481 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6482 struct intel_encoder
*encoder
;
6483 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6484 struct drm_display_mode
*mode
= &intel_crtc
->config
.requested_mode
;
6485 int pipe
= intel_crtc
->pipe
;
6488 drm_vblank_pre_modeset(dev
, pipe
);
6490 ret
= dev_priv
->display
.crtc_mode_set(crtc
, x
, y
, fb
);
6492 drm_vblank_post_modeset(dev
, pipe
);
6497 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
6498 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6499 encoder
->base
.base
.id
,
6500 drm_get_encoder_name(&encoder
->base
),
6501 mode
->base
.id
, mode
->name
);
6502 encoder
->mode_set(encoder
);
6508 static bool intel_eld_uptodate(struct drm_connector
*connector
,
6509 int reg_eldv
, uint32_t bits_eldv
,
6510 int reg_elda
, uint32_t bits_elda
,
6513 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6514 uint8_t *eld
= connector
->eld
;
6517 i
= I915_READ(reg_eldv
);
6526 i
= I915_READ(reg_elda
);
6528 I915_WRITE(reg_elda
, i
);
6530 for (i
= 0; i
< eld
[2]; i
++)
6531 if (I915_READ(reg_edid
) != *((uint32_t *)eld
+ i
))
6537 static void g4x_write_eld(struct drm_connector
*connector
,
6538 struct drm_crtc
*crtc
)
6540 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6541 uint8_t *eld
= connector
->eld
;
6546 i
= I915_READ(G4X_AUD_VID_DID
);
6548 if (i
== INTEL_AUDIO_DEVBLC
|| i
== INTEL_AUDIO_DEVCL
)
6549 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
6551 eldv
= G4X_ELDV_DEVCTG
;
6553 if (intel_eld_uptodate(connector
,
6554 G4X_AUD_CNTL_ST
, eldv
,
6555 G4X_AUD_CNTL_ST
, G4X_ELD_ADDR
,
6556 G4X_HDMIW_HDMIEDID
))
6559 i
= I915_READ(G4X_AUD_CNTL_ST
);
6560 i
&= ~(eldv
| G4X_ELD_ADDR
);
6561 len
= (i
>> 9) & 0x1f; /* ELD buffer size */
6562 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
6567 len
= min_t(uint8_t, eld
[2], len
);
6568 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6569 for (i
= 0; i
< len
; i
++)
6570 I915_WRITE(G4X_HDMIW_HDMIEDID
, *((uint32_t *)eld
+ i
));
6572 i
= I915_READ(G4X_AUD_CNTL_ST
);
6574 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
6577 static void haswell_write_eld(struct drm_connector
*connector
,
6578 struct drm_crtc
*crtc
)
6580 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6581 uint8_t *eld
= connector
->eld
;
6582 struct drm_device
*dev
= crtc
->dev
;
6583 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6587 int pipe
= to_intel_crtc(crtc
)->pipe
;
6590 int hdmiw_hdmiedid
= HSW_AUD_EDID_DATA(pipe
);
6591 int aud_cntl_st
= HSW_AUD_DIP_ELD_CTRL(pipe
);
6592 int aud_config
= HSW_AUD_CFG(pipe
);
6593 int aud_cntrl_st2
= HSW_AUD_PIN_ELD_CP_VLD
;
6596 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6598 /* Audio output enable */
6599 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6600 tmp
= I915_READ(aud_cntrl_st2
);
6601 tmp
|= (AUDIO_OUTPUT_ENABLE_A
<< (pipe
* 4));
6602 I915_WRITE(aud_cntrl_st2
, tmp
);
6604 /* Wait for 1 vertical blank */
6605 intel_wait_for_vblank(dev
, pipe
);
6607 /* Set ELD valid state */
6608 tmp
= I915_READ(aud_cntrl_st2
);
6609 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp
);
6610 tmp
|= (AUDIO_ELD_VALID_A
<< (pipe
* 4));
6611 I915_WRITE(aud_cntrl_st2
, tmp
);
6612 tmp
= I915_READ(aud_cntrl_st2
);
6613 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp
);
6615 /* Enable HDMI mode */
6616 tmp
= I915_READ(aud_config
);
6617 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp
);
6618 /* clear N_programing_enable and N_value_index */
6619 tmp
&= ~(AUD_CONFIG_N_VALUE_INDEX
| AUD_CONFIG_N_PROG_ENABLE
);
6620 I915_WRITE(aud_config
, tmp
);
6622 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
6624 eldv
= AUDIO_ELD_VALID_A
<< (pipe
* 4);
6625 intel_crtc
->eld_vld
= true;
6627 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
6628 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6629 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6630 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
6632 I915_WRITE(aud_config
, 0);
6634 if (intel_eld_uptodate(connector
,
6635 aud_cntrl_st2
, eldv
,
6636 aud_cntl_st
, IBX_ELD_ADDRESS
,
6640 i
= I915_READ(aud_cntrl_st2
);
6642 I915_WRITE(aud_cntrl_st2
, i
);
6647 i
= I915_READ(aud_cntl_st
);
6648 i
&= ~IBX_ELD_ADDRESS
;
6649 I915_WRITE(aud_cntl_st
, i
);
6650 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
6651 DRM_DEBUG_DRIVER("port num:%d\n", i
);
6653 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
6654 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6655 for (i
= 0; i
< len
; i
++)
6656 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
6658 i
= I915_READ(aud_cntrl_st2
);
6660 I915_WRITE(aud_cntrl_st2
, i
);
6664 static void ironlake_write_eld(struct drm_connector
*connector
,
6665 struct drm_crtc
*crtc
)
6667 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6668 uint8_t *eld
= connector
->eld
;
6676 int pipe
= to_intel_crtc(crtc
)->pipe
;
6678 if (HAS_PCH_IBX(connector
->dev
)) {
6679 hdmiw_hdmiedid
= IBX_HDMIW_HDMIEDID(pipe
);
6680 aud_config
= IBX_AUD_CFG(pipe
);
6681 aud_cntl_st
= IBX_AUD_CNTL_ST(pipe
);
6682 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
6684 hdmiw_hdmiedid
= CPT_HDMIW_HDMIEDID(pipe
);
6685 aud_config
= CPT_AUD_CFG(pipe
);
6686 aud_cntl_st
= CPT_AUD_CNTL_ST(pipe
);
6687 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
6690 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
6692 i
= I915_READ(aud_cntl_st
);
6693 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
6695 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6696 /* operate blindly on all ports */
6697 eldv
= IBX_ELD_VALIDB
;
6698 eldv
|= IBX_ELD_VALIDB
<< 4;
6699 eldv
|= IBX_ELD_VALIDB
<< 8;
6701 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i
));
6702 eldv
= IBX_ELD_VALIDB
<< ((i
- 1) * 4);
6705 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
6706 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6707 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6708 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
6710 I915_WRITE(aud_config
, 0);
6712 if (intel_eld_uptodate(connector
,
6713 aud_cntrl_st2
, eldv
,
6714 aud_cntl_st
, IBX_ELD_ADDRESS
,
6718 i
= I915_READ(aud_cntrl_st2
);
6720 I915_WRITE(aud_cntrl_st2
, i
);
6725 i
= I915_READ(aud_cntl_st
);
6726 i
&= ~IBX_ELD_ADDRESS
;
6727 I915_WRITE(aud_cntl_st
, i
);
6729 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
6730 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6731 for (i
= 0; i
< len
; i
++)
6732 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
6734 i
= I915_READ(aud_cntrl_st2
);
6736 I915_WRITE(aud_cntrl_st2
, i
);
6739 void intel_write_eld(struct drm_encoder
*encoder
,
6740 struct drm_display_mode
*mode
)
6742 struct drm_crtc
*crtc
= encoder
->crtc
;
6743 struct drm_connector
*connector
;
6744 struct drm_device
*dev
= encoder
->dev
;
6745 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6747 connector
= drm_select_eld(encoder
, mode
);
6751 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6753 drm_get_connector_name(connector
),
6754 connector
->encoder
->base
.id
,
6755 drm_get_encoder_name(connector
->encoder
));
6757 connector
->eld
[6] = drm_av_sync_delay(connector
, mode
) / 2;
6759 if (dev_priv
->display
.write_eld
)
6760 dev_priv
->display
.write_eld(connector
, crtc
);
6763 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6764 void intel_crtc_load_lut(struct drm_crtc
*crtc
)
6766 struct drm_device
*dev
= crtc
->dev
;
6767 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6768 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6769 enum pipe pipe
= intel_crtc
->pipe
;
6770 int palreg
= PALETTE(pipe
);
6772 bool reenable_ips
= false;
6774 /* The clocks have to be on to load the palette. */
6775 if (!crtc
->enabled
|| !intel_crtc
->active
)
6778 if (!HAS_PCH_SPLIT(dev_priv
->dev
)) {
6779 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
))
6780 assert_dsi_pll_enabled(dev_priv
);
6782 assert_pll_enabled(dev_priv
, pipe
);
6785 /* use legacy palette for Ironlake */
6786 if (HAS_PCH_SPLIT(dev
))
6787 palreg
= LGC_PALETTE(pipe
);
6789 /* Workaround : Do not read or write the pipe palette/gamma data while
6790 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6792 if (intel_crtc
->config
.ips_enabled
&&
6793 ((I915_READ(GAMMA_MODE(pipe
)) & GAMMA_MODE_MODE_MASK
) ==
6794 GAMMA_MODE_MODE_SPLIT
)) {
6795 hsw_disable_ips(intel_crtc
);
6796 reenable_ips
= true;
6799 for (i
= 0; i
< 256; i
++) {
6800 I915_WRITE(palreg
+ 4 * i
,
6801 (intel_crtc
->lut_r
[i
] << 16) |
6802 (intel_crtc
->lut_g
[i
] << 8) |
6803 intel_crtc
->lut_b
[i
]);
6807 hsw_enable_ips(intel_crtc
);
6810 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6812 struct drm_device
*dev
= crtc
->dev
;
6813 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6814 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6815 bool visible
= base
!= 0;
6818 if (intel_crtc
->cursor_visible
== visible
)
6821 cntl
= I915_READ(_CURACNTR
);
6823 /* On these chipsets we can only modify the base whilst
6824 * the cursor is disabled.
6826 I915_WRITE(_CURABASE
, base
);
6828 cntl
&= ~(CURSOR_FORMAT_MASK
);
6829 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6830 cntl
|= CURSOR_ENABLE
|
6831 CURSOR_GAMMA_ENABLE
|
6834 cntl
&= ~(CURSOR_ENABLE
| CURSOR_GAMMA_ENABLE
);
6835 I915_WRITE(_CURACNTR
, cntl
);
6837 intel_crtc
->cursor_visible
= visible
;
6840 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6842 struct drm_device
*dev
= crtc
->dev
;
6843 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6844 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6845 int pipe
= intel_crtc
->pipe
;
6846 bool visible
= base
!= 0;
6848 if (intel_crtc
->cursor_visible
!= visible
) {
6849 uint32_t cntl
= I915_READ(CURCNTR(pipe
));
6851 cntl
&= ~(CURSOR_MODE
| MCURSOR_PIPE_SELECT
);
6852 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
6853 cntl
|= pipe
<< 28; /* Connect to correct pipe */
6855 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
6856 cntl
|= CURSOR_MODE_DISABLE
;
6858 I915_WRITE(CURCNTR(pipe
), cntl
);
6860 intel_crtc
->cursor_visible
= visible
;
6862 /* and commit changes on next vblank */
6863 I915_WRITE(CURBASE(pipe
), base
);
6866 static void ivb_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6868 struct drm_device
*dev
= crtc
->dev
;
6869 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6870 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6871 int pipe
= intel_crtc
->pipe
;
6872 bool visible
= base
!= 0;
6874 if (intel_crtc
->cursor_visible
!= visible
) {
6875 uint32_t cntl
= I915_READ(CURCNTR_IVB(pipe
));
6877 cntl
&= ~CURSOR_MODE
;
6878 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
6880 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
6881 cntl
|= CURSOR_MODE_DISABLE
;
6883 if (IS_HASWELL(dev
)) {
6884 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
6885 cntl
&= ~CURSOR_TRICKLE_FEED_DISABLE
;
6887 I915_WRITE(CURCNTR_IVB(pipe
), cntl
);
6889 intel_crtc
->cursor_visible
= visible
;
6891 /* and commit changes on next vblank */
6892 I915_WRITE(CURBASE_IVB(pipe
), base
);
6895 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6896 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
6899 struct drm_device
*dev
= crtc
->dev
;
6900 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6901 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6902 int pipe
= intel_crtc
->pipe
;
6903 int x
= intel_crtc
->cursor_x
;
6904 int y
= intel_crtc
->cursor_y
;
6910 if (on
&& crtc
->enabled
&& crtc
->fb
) {
6911 base
= intel_crtc
->cursor_addr
;
6912 if (x
> (int) crtc
->fb
->width
)
6915 if (y
> (int) crtc
->fb
->height
)
6921 if (x
+ intel_crtc
->cursor_width
< 0)
6924 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
6927 pos
|= x
<< CURSOR_X_SHIFT
;
6930 if (y
+ intel_crtc
->cursor_height
< 0)
6933 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
6936 pos
|= y
<< CURSOR_Y_SHIFT
;
6938 visible
= base
!= 0;
6939 if (!visible
&& !intel_crtc
->cursor_visible
)
6942 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
6943 I915_WRITE(CURPOS_IVB(pipe
), pos
);
6944 ivb_update_cursor(crtc
, base
);
6946 I915_WRITE(CURPOS(pipe
), pos
);
6947 if (IS_845G(dev
) || IS_I865G(dev
))
6948 i845_update_cursor(crtc
, base
);
6950 i9xx_update_cursor(crtc
, base
);
6954 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
6955 struct drm_file
*file
,
6957 uint32_t width
, uint32_t height
)
6959 struct drm_device
*dev
= crtc
->dev
;
6960 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6961 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6962 struct drm_i915_gem_object
*obj
;
6966 /* if we want to turn off the cursor ignore width and height */
6968 DRM_DEBUG_KMS("cursor off\n");
6971 mutex_lock(&dev
->struct_mutex
);
6975 /* Currently we only support 64x64 cursors */
6976 if (width
!= 64 || height
!= 64) {
6977 DRM_ERROR("we currently only support 64x64 cursors\n");
6981 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
6982 if (&obj
->base
== NULL
)
6985 if (obj
->base
.size
< width
* height
* 4) {
6986 DRM_ERROR("buffer is to small\n");
6991 /* we only need to pin inside GTT if cursor is non-phy */
6992 mutex_lock(&dev
->struct_mutex
);
6993 if (!dev_priv
->info
->cursor_needs_physical
) {
6996 if (obj
->tiling_mode
) {
6997 DRM_ERROR("cursor cannot be tiled\n");
7002 /* Note that the w/a also requires 2 PTE of padding following
7003 * the bo. We currently fill all unused PTE with the shadow
7004 * page and so we should always have valid PTE following the
7005 * cursor preventing the VT-d warning.
7008 if (need_vtd_wa(dev
))
7009 alignment
= 64*1024;
7011 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, NULL
);
7013 DRM_ERROR("failed to move cursor bo into the GTT\n");
7017 ret
= i915_gem_object_put_fence(obj
);
7019 DRM_ERROR("failed to release fence for cursor");
7023 addr
= i915_gem_obj_ggtt_offset(obj
);
7025 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
7026 ret
= i915_gem_attach_phys_object(dev
, obj
,
7027 (intel_crtc
->pipe
== 0) ? I915_GEM_PHYS_CURSOR_0
: I915_GEM_PHYS_CURSOR_1
,
7030 DRM_ERROR("failed to attach phys object\n");
7033 addr
= obj
->phys_obj
->handle
->busaddr
;
7037 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
7040 if (intel_crtc
->cursor_bo
) {
7041 if (dev_priv
->info
->cursor_needs_physical
) {
7042 if (intel_crtc
->cursor_bo
!= obj
)
7043 i915_gem_detach_phys_object(dev
, intel_crtc
->cursor_bo
);
7045 i915_gem_object_unpin_from_display_plane(intel_crtc
->cursor_bo
);
7046 drm_gem_object_unreference(&intel_crtc
->cursor_bo
->base
);
7049 mutex_unlock(&dev
->struct_mutex
);
7051 intel_crtc
->cursor_addr
= addr
;
7052 intel_crtc
->cursor_bo
= obj
;
7053 intel_crtc
->cursor_width
= width
;
7054 intel_crtc
->cursor_height
= height
;
7056 intel_crtc_update_cursor(crtc
, intel_crtc
->cursor_bo
!= NULL
);
7060 i915_gem_object_unpin_from_display_plane(obj
);
7062 mutex_unlock(&dev
->struct_mutex
);
7064 drm_gem_object_unreference_unlocked(&obj
->base
);
7068 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
7070 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7072 intel_crtc
->cursor_x
= x
;
7073 intel_crtc
->cursor_y
= y
;
7075 intel_crtc_update_cursor(crtc
, intel_crtc
->cursor_bo
!= NULL
);
7080 /** Sets the color ramps on behalf of RandR */
7081 void intel_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
7082 u16 blue
, int regno
)
7084 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7086 intel_crtc
->lut_r
[regno
] = red
>> 8;
7087 intel_crtc
->lut_g
[regno
] = green
>> 8;
7088 intel_crtc
->lut_b
[regno
] = blue
>> 8;
7091 void intel_crtc_fb_gamma_get(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
7092 u16
*blue
, int regno
)
7094 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7096 *red
= intel_crtc
->lut_r
[regno
] << 8;
7097 *green
= intel_crtc
->lut_g
[regno
] << 8;
7098 *blue
= intel_crtc
->lut_b
[regno
] << 8;
7101 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
7102 u16
*blue
, uint32_t start
, uint32_t size
)
7104 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
7105 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7107 for (i
= start
; i
< end
; i
++) {
7108 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
7109 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
7110 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
7113 intel_crtc_load_lut(crtc
);
7116 /* VESA 640x480x72Hz mode to set on the pipe */
7117 static struct drm_display_mode load_detect_mode
= {
7118 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
7119 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
7122 static struct drm_framebuffer
*
7123 intel_framebuffer_create(struct drm_device
*dev
,
7124 struct drm_mode_fb_cmd2
*mode_cmd
,
7125 struct drm_i915_gem_object
*obj
)
7127 struct intel_framebuffer
*intel_fb
;
7130 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
7132 drm_gem_object_unreference_unlocked(&obj
->base
);
7133 return ERR_PTR(-ENOMEM
);
7136 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
7138 drm_gem_object_unreference_unlocked(&obj
->base
);
7140 return ERR_PTR(ret
);
7143 return &intel_fb
->base
;
7147 intel_framebuffer_pitch_for_width(int width
, int bpp
)
7149 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
7150 return ALIGN(pitch
, 64);
7154 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
7156 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
7157 return ALIGN(pitch
* mode
->vdisplay
, PAGE_SIZE
);
7160 static struct drm_framebuffer
*
7161 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
7162 struct drm_display_mode
*mode
,
7165 struct drm_i915_gem_object
*obj
;
7166 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
7168 obj
= i915_gem_alloc_object(dev
,
7169 intel_framebuffer_size_for_mode(mode
, bpp
));
7171 return ERR_PTR(-ENOMEM
);
7173 mode_cmd
.width
= mode
->hdisplay
;
7174 mode_cmd
.height
= mode
->vdisplay
;
7175 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
7177 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
7179 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
7182 static struct drm_framebuffer
*
7183 mode_fits_in_fbdev(struct drm_device
*dev
,
7184 struct drm_display_mode
*mode
)
7186 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7187 struct drm_i915_gem_object
*obj
;
7188 struct drm_framebuffer
*fb
;
7190 if (dev_priv
->fbdev
== NULL
)
7193 obj
= dev_priv
->fbdev
->ifb
.obj
;
7197 fb
= &dev_priv
->fbdev
->ifb
.base
;
7198 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
7199 fb
->bits_per_pixel
))
7202 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
7208 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
7209 struct drm_display_mode
*mode
,
7210 struct intel_load_detect_pipe
*old
)
7212 struct intel_crtc
*intel_crtc
;
7213 struct intel_encoder
*intel_encoder
=
7214 intel_attached_encoder(connector
);
7215 struct drm_crtc
*possible_crtc
;
7216 struct drm_encoder
*encoder
= &intel_encoder
->base
;
7217 struct drm_crtc
*crtc
= NULL
;
7218 struct drm_device
*dev
= encoder
->dev
;
7219 struct drm_framebuffer
*fb
;
7222 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7223 connector
->base
.id
, drm_get_connector_name(connector
),
7224 encoder
->base
.id
, drm_get_encoder_name(encoder
));
7227 * Algorithm gets a little messy:
7229 * - if the connector already has an assigned crtc, use it (but make
7230 * sure it's on first)
7232 * - try to find the first unused crtc that can drive this connector,
7233 * and use that if we find one
7236 /* See if we already have a CRTC for this connector */
7237 if (encoder
->crtc
) {
7238 crtc
= encoder
->crtc
;
7240 mutex_lock(&crtc
->mutex
);
7242 old
->dpms_mode
= connector
->dpms
;
7243 old
->load_detect_temp
= false;
7245 /* Make sure the crtc and connector are running */
7246 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
7247 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
7252 /* Find an unused one (if possible) */
7253 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
7255 if (!(encoder
->possible_crtcs
& (1 << i
)))
7257 if (!possible_crtc
->enabled
) {
7258 crtc
= possible_crtc
;
7264 * If we didn't find an unused CRTC, don't use any.
7267 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7271 mutex_lock(&crtc
->mutex
);
7272 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
7273 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
7275 intel_crtc
= to_intel_crtc(crtc
);
7276 old
->dpms_mode
= connector
->dpms
;
7277 old
->load_detect_temp
= true;
7278 old
->release_fb
= NULL
;
7281 mode
= &load_detect_mode
;
7283 /* We need a framebuffer large enough to accommodate all accesses
7284 * that the plane may generate whilst we perform load detection.
7285 * We can not rely on the fbcon either being present (we get called
7286 * during its initialisation to detect all boot displays, or it may
7287 * not even exist) or that it is large enough to satisfy the
7290 fb
= mode_fits_in_fbdev(dev
, mode
);
7292 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7293 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
7294 old
->release_fb
= fb
;
7296 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7298 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7299 mutex_unlock(&crtc
->mutex
);
7303 if (intel_set_mode(crtc
, mode
, 0, 0, fb
)) {
7304 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7305 if (old
->release_fb
)
7306 old
->release_fb
->funcs
->destroy(old
->release_fb
);
7307 mutex_unlock(&crtc
->mutex
);
7311 /* let the connector get through one full cycle before testing */
7312 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
7316 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
7317 struct intel_load_detect_pipe
*old
)
7319 struct intel_encoder
*intel_encoder
=
7320 intel_attached_encoder(connector
);
7321 struct drm_encoder
*encoder
= &intel_encoder
->base
;
7322 struct drm_crtc
*crtc
= encoder
->crtc
;
7324 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7325 connector
->base
.id
, drm_get_connector_name(connector
),
7326 encoder
->base
.id
, drm_get_encoder_name(encoder
));
7328 if (old
->load_detect_temp
) {
7329 to_intel_connector(connector
)->new_encoder
= NULL
;
7330 intel_encoder
->new_crtc
= NULL
;
7331 intel_set_mode(crtc
, NULL
, 0, 0, NULL
);
7333 if (old
->release_fb
) {
7334 drm_framebuffer_unregister_private(old
->release_fb
);
7335 drm_framebuffer_unreference(old
->release_fb
);
7338 mutex_unlock(&crtc
->mutex
);
7342 /* Switch crtc and encoder back off if necessary */
7343 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
7344 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
7346 mutex_unlock(&crtc
->mutex
);
7349 static int i9xx_pll_refclk(struct drm_device
*dev
,
7350 const struct intel_crtc_config
*pipe_config
)
7352 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7353 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
7355 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
7356 return dev_priv
->vbt
.lvds_ssc_freq
* 1000;
7357 else if (HAS_PCH_SPLIT(dev
))
7359 else if (!IS_GEN2(dev
))
7365 /* Returns the clock of the currently programmed mode of the given pipe. */
7366 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
7367 struct intel_crtc_config
*pipe_config
)
7369 struct drm_device
*dev
= crtc
->base
.dev
;
7370 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7371 int pipe
= pipe_config
->cpu_transcoder
;
7372 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
7374 intel_clock_t clock
;
7375 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
7377 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
7378 fp
= pipe_config
->dpll_hw_state
.fp0
;
7380 fp
= pipe_config
->dpll_hw_state
.fp1
;
7382 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
7383 if (IS_PINEVIEW(dev
)) {
7384 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
7385 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
7387 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
7388 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
7391 if (!IS_GEN2(dev
)) {
7392 if (IS_PINEVIEW(dev
))
7393 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
7394 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
7396 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
7397 DPLL_FPA01_P1_POST_DIV_SHIFT
);
7399 switch (dpll
& DPLL_MODE_MASK
) {
7400 case DPLLB_MODE_DAC_SERIAL
:
7401 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
7404 case DPLLB_MODE_LVDS
:
7405 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
7409 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7410 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
7414 if (IS_PINEVIEW(dev
))
7415 pineview_clock(refclk
, &clock
);
7417 i9xx_clock(refclk
, &clock
);
7419 bool is_lvds
= (pipe
== 1) && (I915_READ(LVDS
) & LVDS_PORT_EN
);
7422 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
7423 DPLL_FPA01_P1_POST_DIV_SHIFT
);
7426 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
7429 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
7430 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
7432 if (dpll
& PLL_P2_DIVIDE_BY_4
)
7438 i9xx_clock(refclk
, &clock
);
7442 * This value includes pixel_multiplier. We will use
7443 * port_clock to compute adjusted_mode.clock in the
7444 * encoder's get_config() function.
7446 pipe_config
->port_clock
= clock
.dot
;
7449 int intel_dotclock_calculate(int link_freq
,
7450 const struct intel_link_m_n
*m_n
)
7453 * The calculation for the data clock is:
7454 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
7455 * But we want to avoid losing precison if possible, so:
7456 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
7458 * and the link clock is simpler:
7459 * link_clock = (m * link_clock) / n
7465 return div_u64((u64
)m_n
->link_m
* link_freq
, m_n
->link_n
);
7468 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
7469 struct intel_crtc_config
*pipe_config
)
7471 struct drm_device
*dev
= crtc
->base
.dev
;
7473 /* read out port_clock from the DPLL */
7474 i9xx_crtc_clock_get(crtc
, pipe_config
);
7477 * This value does not include pixel_multiplier.
7478 * We will check that port_clock and adjusted_mode.clock
7479 * agree once we know their relationship in the encoder's
7480 * get_config() function.
7482 pipe_config
->adjusted_mode
.clock
=
7483 intel_dotclock_calculate(intel_fdi_link_freq(dev
) * 10000,
7484 &pipe_config
->fdi_m_n
);
7487 /** Returns the currently programmed mode of the given pipe. */
7488 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
7489 struct drm_crtc
*crtc
)
7491 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7492 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7493 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
7494 struct drm_display_mode
*mode
;
7495 struct intel_crtc_config pipe_config
;
7496 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
7497 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
7498 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
7499 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
7500 enum pipe pipe
= intel_crtc
->pipe
;
7502 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
7507 * Construct a pipe_config sufficient for getting the clock info
7508 * back out of crtc_clock_get.
7510 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7511 * to use a real value here instead.
7513 pipe_config
.cpu_transcoder
= (enum transcoder
) pipe
;
7514 pipe_config
.pixel_multiplier
= 1;
7515 pipe_config
.dpll_hw_state
.dpll
= I915_READ(DPLL(pipe
));
7516 pipe_config
.dpll_hw_state
.fp0
= I915_READ(FP0(pipe
));
7517 pipe_config
.dpll_hw_state
.fp1
= I915_READ(FP1(pipe
));
7518 i9xx_crtc_clock_get(intel_crtc
, &pipe_config
);
7520 mode
->clock
= pipe_config
.adjusted_mode
.clock
;
7521 mode
->hdisplay
= (htot
& 0xffff) + 1;
7522 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
7523 mode
->hsync_start
= (hsync
& 0xffff) + 1;
7524 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
7525 mode
->vdisplay
= (vtot
& 0xffff) + 1;
7526 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
7527 mode
->vsync_start
= (vsync
& 0xffff) + 1;
7528 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
7530 drm_mode_set_name(mode
);
7535 static void intel_increase_pllclock(struct drm_crtc
*crtc
)
7537 struct drm_device
*dev
= crtc
->dev
;
7538 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7539 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7540 int pipe
= intel_crtc
->pipe
;
7541 int dpll_reg
= DPLL(pipe
);
7544 if (HAS_PCH_SPLIT(dev
))
7547 if (!dev_priv
->lvds_downclock_avail
)
7550 dpll
= I915_READ(dpll_reg
);
7551 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
7552 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7554 assert_panel_unlocked(dev_priv
, pipe
);
7556 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
7557 I915_WRITE(dpll_reg
, dpll
);
7558 intel_wait_for_vblank(dev
, pipe
);
7560 dpll
= I915_READ(dpll_reg
);
7561 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
7562 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7566 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
7568 struct drm_device
*dev
= crtc
->dev
;
7569 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7570 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7572 if (HAS_PCH_SPLIT(dev
))
7575 if (!dev_priv
->lvds_downclock_avail
)
7579 * Since this is called by a timer, we should never get here in
7582 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
7583 int pipe
= intel_crtc
->pipe
;
7584 int dpll_reg
= DPLL(pipe
);
7587 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7589 assert_panel_unlocked(dev_priv
, pipe
);
7591 dpll
= I915_READ(dpll_reg
);
7592 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
7593 I915_WRITE(dpll_reg
, dpll
);
7594 intel_wait_for_vblank(dev
, pipe
);
7595 dpll
= I915_READ(dpll_reg
);
7596 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
7597 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7602 void intel_mark_busy(struct drm_device
*dev
)
7604 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7606 hsw_package_c8_gpu_busy(dev_priv
);
7607 i915_update_gfx_val(dev_priv
);
7610 void intel_mark_idle(struct drm_device
*dev
)
7612 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7613 struct drm_crtc
*crtc
;
7615 hsw_package_c8_gpu_idle(dev_priv
);
7617 if (!i915_powersave
)
7620 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
7624 intel_decrease_pllclock(crtc
);
7628 void intel_mark_fb_busy(struct drm_i915_gem_object
*obj
,
7629 struct intel_ring_buffer
*ring
)
7631 struct drm_device
*dev
= obj
->base
.dev
;
7632 struct drm_crtc
*crtc
;
7634 if (!i915_powersave
)
7637 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
7641 if (to_intel_framebuffer(crtc
->fb
)->obj
!= obj
)
7644 intel_increase_pllclock(crtc
);
7645 if (ring
&& intel_fbc_enabled(dev
))
7646 ring
->fbc_dirty
= true;
7650 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
7652 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7653 struct drm_device
*dev
= crtc
->dev
;
7654 struct intel_unpin_work
*work
;
7655 unsigned long flags
;
7657 spin_lock_irqsave(&dev
->event_lock
, flags
);
7658 work
= intel_crtc
->unpin_work
;
7659 intel_crtc
->unpin_work
= NULL
;
7660 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7663 cancel_work_sync(&work
->work
);
7667 intel_crtc_cursor_set(crtc
, NULL
, 0, 0, 0);
7669 drm_crtc_cleanup(crtc
);
7674 static void intel_unpin_work_fn(struct work_struct
*__work
)
7676 struct intel_unpin_work
*work
=
7677 container_of(__work
, struct intel_unpin_work
, work
);
7678 struct drm_device
*dev
= work
->crtc
->dev
;
7680 mutex_lock(&dev
->struct_mutex
);
7681 intel_unpin_fb_obj(work
->old_fb_obj
);
7682 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
7683 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
7685 intel_update_fbc(dev
);
7686 mutex_unlock(&dev
->struct_mutex
);
7688 BUG_ON(atomic_read(&to_intel_crtc(work
->crtc
)->unpin_work_count
) == 0);
7689 atomic_dec(&to_intel_crtc(work
->crtc
)->unpin_work_count
);
7694 static void do_intel_finish_page_flip(struct drm_device
*dev
,
7695 struct drm_crtc
*crtc
)
7697 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7698 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7699 struct intel_unpin_work
*work
;
7700 unsigned long flags
;
7702 /* Ignore early vblank irqs */
7703 if (intel_crtc
== NULL
)
7706 spin_lock_irqsave(&dev
->event_lock
, flags
);
7707 work
= intel_crtc
->unpin_work
;
7709 /* Ensure we don't miss a work->pending update ... */
7712 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
7713 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7717 /* and that the unpin work is consistent wrt ->pending. */
7720 intel_crtc
->unpin_work
= NULL
;
7723 drm_send_vblank_event(dev
, intel_crtc
->pipe
, work
->event
);
7725 drm_vblank_put(dev
, intel_crtc
->pipe
);
7727 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7729 wake_up_all(&dev_priv
->pending_flip_queue
);
7731 queue_work(dev_priv
->wq
, &work
->work
);
7733 trace_i915_flip_complete(intel_crtc
->plane
, work
->pending_flip_obj
);
7736 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
7738 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7739 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
7741 do_intel_finish_page_flip(dev
, crtc
);
7744 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
7746 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7747 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
7749 do_intel_finish_page_flip(dev
, crtc
);
7752 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
7754 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7755 struct intel_crtc
*intel_crtc
=
7756 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
7757 unsigned long flags
;
7759 /* NB: An MMIO update of the plane base pointer will also
7760 * generate a page-flip completion irq, i.e. every modeset
7761 * is also accompanied by a spurious intel_prepare_page_flip().
7763 spin_lock_irqsave(&dev
->event_lock
, flags
);
7764 if (intel_crtc
->unpin_work
)
7765 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
7766 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7769 inline static void intel_mark_page_flip_active(struct intel_crtc
*intel_crtc
)
7771 /* Ensure that the work item is consistent when activating it ... */
7773 atomic_set(&intel_crtc
->unpin_work
->pending
, INTEL_FLIP_PENDING
);
7774 /* and that it is marked active as soon as the irq could fire. */
7778 static int intel_gen2_queue_flip(struct drm_device
*dev
,
7779 struct drm_crtc
*crtc
,
7780 struct drm_framebuffer
*fb
,
7781 struct drm_i915_gem_object
*obj
,
7784 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7785 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7787 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7790 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7794 ret
= intel_ring_begin(ring
, 6);
7798 /* Can't queue multiple flips, so wait for the previous
7799 * one to finish before executing the next.
7801 if (intel_crtc
->plane
)
7802 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
7804 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
7805 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
7806 intel_ring_emit(ring
, MI_NOOP
);
7807 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7808 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7809 intel_ring_emit(ring
, fb
->pitches
[0]);
7810 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
7811 intel_ring_emit(ring
, 0); /* aux display base address, unused */
7813 intel_mark_page_flip_active(intel_crtc
);
7814 __intel_ring_advance(ring
);
7818 intel_unpin_fb_obj(obj
);
7823 static int intel_gen3_queue_flip(struct drm_device
*dev
,
7824 struct drm_crtc
*crtc
,
7825 struct drm_framebuffer
*fb
,
7826 struct drm_i915_gem_object
*obj
,
7829 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7830 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7832 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7835 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7839 ret
= intel_ring_begin(ring
, 6);
7843 if (intel_crtc
->plane
)
7844 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
7846 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
7847 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
7848 intel_ring_emit(ring
, MI_NOOP
);
7849 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
7850 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7851 intel_ring_emit(ring
, fb
->pitches
[0]);
7852 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
7853 intel_ring_emit(ring
, MI_NOOP
);
7855 intel_mark_page_flip_active(intel_crtc
);
7856 __intel_ring_advance(ring
);
7860 intel_unpin_fb_obj(obj
);
7865 static int intel_gen4_queue_flip(struct drm_device
*dev
,
7866 struct drm_crtc
*crtc
,
7867 struct drm_framebuffer
*fb
,
7868 struct drm_i915_gem_object
*obj
,
7871 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7872 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7873 uint32_t pf
, pipesrc
;
7874 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7877 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7881 ret
= intel_ring_begin(ring
, 4);
7885 /* i965+ uses the linear or tiled offsets from the
7886 * Display Registers (which do not change across a page-flip)
7887 * so we need only reprogram the base address.
7889 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7890 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7891 intel_ring_emit(ring
, fb
->pitches
[0]);
7892 intel_ring_emit(ring
,
7893 (i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
) |
7896 /* XXX Enabling the panel-fitter across page-flip is so far
7897 * untested on non-native modes, so ignore it for now.
7898 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7901 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
7902 intel_ring_emit(ring
, pf
| pipesrc
);
7904 intel_mark_page_flip_active(intel_crtc
);
7905 __intel_ring_advance(ring
);
7909 intel_unpin_fb_obj(obj
);
7914 static int intel_gen6_queue_flip(struct drm_device
*dev
,
7915 struct drm_crtc
*crtc
,
7916 struct drm_framebuffer
*fb
,
7917 struct drm_i915_gem_object
*obj
,
7920 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7921 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7922 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7923 uint32_t pf
, pipesrc
;
7926 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7930 ret
= intel_ring_begin(ring
, 4);
7934 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7935 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7936 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
7937 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
7939 /* Contrary to the suggestions in the documentation,
7940 * "Enable Panel Fitter" does not seem to be required when page
7941 * flipping with a non-native mode, and worse causes a normal
7943 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7946 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
7947 intel_ring_emit(ring
, pf
| pipesrc
);
7949 intel_mark_page_flip_active(intel_crtc
);
7950 __intel_ring_advance(ring
);
7954 intel_unpin_fb_obj(obj
);
7959 static int intel_gen7_queue_flip(struct drm_device
*dev
,
7960 struct drm_crtc
*crtc
,
7961 struct drm_framebuffer
*fb
,
7962 struct drm_i915_gem_object
*obj
,
7965 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7966 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7967 struct intel_ring_buffer
*ring
;
7968 uint32_t plane_bit
= 0;
7972 if (ring
== NULL
|| ring
->id
!= RCS
)
7973 ring
= &dev_priv
->ring
[BCS
];
7975 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7979 switch(intel_crtc
->plane
) {
7981 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
7984 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
7987 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
7990 WARN_ONCE(1, "unknown plane in flip command\n");
7996 if (ring
->id
== RCS
)
7999 ret
= intel_ring_begin(ring
, len
);
8003 /* Unmask the flip-done completion message. Note that the bspec says that
8004 * we should do this for both the BCS and RCS, and that we must not unmask
8005 * more than one flip event at any time (or ensure that one flip message
8006 * can be sent by waiting for flip-done prior to queueing new flips).
8007 * Experimentation says that BCS works despite DERRMR masking all
8008 * flip-done completion events and that unmasking all planes at once
8009 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8010 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8012 if (ring
->id
== RCS
) {
8013 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
8014 intel_ring_emit(ring
, DERRMR
);
8015 intel_ring_emit(ring
, ~(DERRMR_PIPEA_PRI_FLIP_DONE
|
8016 DERRMR_PIPEB_PRI_FLIP_DONE
|
8017 DERRMR_PIPEC_PRI_FLIP_DONE
));
8018 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM(1));
8019 intel_ring_emit(ring
, DERRMR
);
8020 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
+ 256);
8023 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
8024 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
8025 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
8026 intel_ring_emit(ring
, (MI_NOOP
));
8028 intel_mark_page_flip_active(intel_crtc
);
8029 __intel_ring_advance(ring
);
8033 intel_unpin_fb_obj(obj
);
8038 static int intel_default_queue_flip(struct drm_device
*dev
,
8039 struct drm_crtc
*crtc
,
8040 struct drm_framebuffer
*fb
,
8041 struct drm_i915_gem_object
*obj
,
8047 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
8048 struct drm_framebuffer
*fb
,
8049 struct drm_pending_vblank_event
*event
,
8050 uint32_t page_flip_flags
)
8052 struct drm_device
*dev
= crtc
->dev
;
8053 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8054 struct drm_framebuffer
*old_fb
= crtc
->fb
;
8055 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(fb
)->obj
;
8056 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8057 struct intel_unpin_work
*work
;
8058 unsigned long flags
;
8061 /* Can't change pixel format via MI display flips. */
8062 if (fb
->pixel_format
!= crtc
->fb
->pixel_format
)
8066 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8067 * Note that pitch changes could also affect these register.
8069 if (INTEL_INFO(dev
)->gen
> 3 &&
8070 (fb
->offsets
[0] != crtc
->fb
->offsets
[0] ||
8071 fb
->pitches
[0] != crtc
->fb
->pitches
[0]))
8074 work
= kzalloc(sizeof *work
, GFP_KERNEL
);
8078 work
->event
= event
;
8080 work
->old_fb_obj
= to_intel_framebuffer(old_fb
)->obj
;
8081 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
8083 ret
= drm_vblank_get(dev
, intel_crtc
->pipe
);
8087 /* We borrow the event spin lock for protecting unpin_work */
8088 spin_lock_irqsave(&dev
->event_lock
, flags
);
8089 if (intel_crtc
->unpin_work
) {
8090 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
8092 drm_vblank_put(dev
, intel_crtc
->pipe
);
8094 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8097 intel_crtc
->unpin_work
= work
;
8098 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
8100 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
8101 flush_workqueue(dev_priv
->wq
);
8103 ret
= i915_mutex_lock_interruptible(dev
);
8107 /* Reference the objects for the scheduled work. */
8108 drm_gem_object_reference(&work
->old_fb_obj
->base
);
8109 drm_gem_object_reference(&obj
->base
);
8113 work
->pending_flip_obj
= obj
;
8115 work
->enable_stall_check
= true;
8117 atomic_inc(&intel_crtc
->unpin_work_count
);
8118 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
8120 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
, page_flip_flags
);
8122 goto cleanup_pending
;
8124 intel_disable_fbc(dev
);
8125 intel_mark_fb_busy(obj
, NULL
);
8126 mutex_unlock(&dev
->struct_mutex
);
8128 trace_i915_flip_request(intel_crtc
->plane
, obj
);
8133 atomic_dec(&intel_crtc
->unpin_work_count
);
8135 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
8136 drm_gem_object_unreference(&obj
->base
);
8137 mutex_unlock(&dev
->struct_mutex
);
8140 spin_lock_irqsave(&dev
->event_lock
, flags
);
8141 intel_crtc
->unpin_work
= NULL
;
8142 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
8144 drm_vblank_put(dev
, intel_crtc
->pipe
);
8151 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
8152 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
8153 .load_lut
= intel_crtc_load_lut
,
8156 static bool intel_encoder_crtc_ok(struct drm_encoder
*encoder
,
8157 struct drm_crtc
*crtc
)
8159 struct drm_device
*dev
;
8160 struct drm_crtc
*tmp
;
8163 WARN(!crtc
, "checking null crtc?\n");
8167 list_for_each_entry(tmp
, &dev
->mode_config
.crtc_list
, head
) {
8173 if (encoder
->possible_crtcs
& crtc_mask
)
8179 * intel_modeset_update_staged_output_state
8181 * Updates the staged output configuration state, e.g. after we've read out the
8184 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
8186 struct intel_encoder
*encoder
;
8187 struct intel_connector
*connector
;
8189 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8191 connector
->new_encoder
=
8192 to_intel_encoder(connector
->base
.encoder
);
8195 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8198 to_intel_crtc(encoder
->base
.crtc
);
8203 * intel_modeset_commit_output_state
8205 * This function copies the stage display pipe configuration to the real one.
8207 static void intel_modeset_commit_output_state(struct drm_device
*dev
)
8209 struct intel_encoder
*encoder
;
8210 struct intel_connector
*connector
;
8212 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8214 connector
->base
.encoder
= &connector
->new_encoder
->base
;
8217 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8219 encoder
->base
.crtc
= &encoder
->new_crtc
->base
;
8224 connected_sink_compute_bpp(struct intel_connector
* connector
,
8225 struct intel_crtc_config
*pipe_config
)
8227 int bpp
= pipe_config
->pipe_bpp
;
8229 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8230 connector
->base
.base
.id
,
8231 drm_get_connector_name(&connector
->base
));
8233 /* Don't use an invalid EDID bpc value */
8234 if (connector
->base
.display_info
.bpc
&&
8235 connector
->base
.display_info
.bpc
* 3 < bpp
) {
8236 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8237 bpp
, connector
->base
.display_info
.bpc
*3);
8238 pipe_config
->pipe_bpp
= connector
->base
.display_info
.bpc
*3;
8241 /* Clamp bpp to 8 on screens without EDID 1.4 */
8242 if (connector
->base
.display_info
.bpc
== 0 && bpp
> 24) {
8243 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8245 pipe_config
->pipe_bpp
= 24;
8250 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
8251 struct drm_framebuffer
*fb
,
8252 struct intel_crtc_config
*pipe_config
)
8254 struct drm_device
*dev
= crtc
->base
.dev
;
8255 struct intel_connector
*connector
;
8258 switch (fb
->pixel_format
) {
8260 bpp
= 8*3; /* since we go through a colormap */
8262 case DRM_FORMAT_XRGB1555
:
8263 case DRM_FORMAT_ARGB1555
:
8264 /* checked in intel_framebuffer_init already */
8265 if (WARN_ON(INTEL_INFO(dev
)->gen
> 3))
8267 case DRM_FORMAT_RGB565
:
8268 bpp
= 6*3; /* min is 18bpp */
8270 case DRM_FORMAT_XBGR8888
:
8271 case DRM_FORMAT_ABGR8888
:
8272 /* checked in intel_framebuffer_init already */
8273 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
8275 case DRM_FORMAT_XRGB8888
:
8276 case DRM_FORMAT_ARGB8888
:
8279 case DRM_FORMAT_XRGB2101010
:
8280 case DRM_FORMAT_ARGB2101010
:
8281 case DRM_FORMAT_XBGR2101010
:
8282 case DRM_FORMAT_ABGR2101010
:
8283 /* checked in intel_framebuffer_init already */
8284 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
8288 /* TODO: gen4+ supports 16 bpc floating point, too. */
8290 DRM_DEBUG_KMS("unsupported depth\n");
8294 pipe_config
->pipe_bpp
= bpp
;
8296 /* Clamp display bpp to EDID value */
8297 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8299 if (!connector
->new_encoder
||
8300 connector
->new_encoder
->new_crtc
!= crtc
)
8303 connected_sink_compute_bpp(connector
, pipe_config
);
8309 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
8310 struct intel_crtc_config
*pipe_config
,
8311 const char *context
)
8313 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc
->base
.base
.id
,
8314 context
, pipe_name(crtc
->pipe
));
8316 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config
->cpu_transcoder
));
8317 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8318 pipe_config
->pipe_bpp
, pipe_config
->dither
);
8319 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8320 pipe_config
->has_pch_encoder
,
8321 pipe_config
->fdi_lanes
,
8322 pipe_config
->fdi_m_n
.gmch_m
, pipe_config
->fdi_m_n
.gmch_n
,
8323 pipe_config
->fdi_m_n
.link_m
, pipe_config
->fdi_m_n
.link_n
,
8324 pipe_config
->fdi_m_n
.tu
);
8325 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8326 pipe_config
->has_dp_encoder
,
8327 pipe_config
->dp_m_n
.gmch_m
, pipe_config
->dp_m_n
.gmch_n
,
8328 pipe_config
->dp_m_n
.link_m
, pipe_config
->dp_m_n
.link_n
,
8329 pipe_config
->dp_m_n
.tu
);
8330 DRM_DEBUG_KMS("requested mode:\n");
8331 drm_mode_debug_printmodeline(&pipe_config
->requested_mode
);
8332 DRM_DEBUG_KMS("adjusted mode:\n");
8333 drm_mode_debug_printmodeline(&pipe_config
->adjusted_mode
);
8334 DRM_DEBUG_KMS("port clock: %d\n", pipe_config
->port_clock
);
8335 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8336 pipe_config
->gmch_pfit
.control
,
8337 pipe_config
->gmch_pfit
.pgm_ratios
,
8338 pipe_config
->gmch_pfit
.lvds_border_bits
);
8339 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
8340 pipe_config
->pch_pfit
.pos
,
8341 pipe_config
->pch_pfit
.size
);
8342 DRM_DEBUG_KMS("ips: %i\n", pipe_config
->ips_enabled
);
8345 static bool check_encoder_cloning(struct drm_crtc
*crtc
)
8347 int num_encoders
= 0;
8348 bool uncloneable_encoders
= false;
8349 struct intel_encoder
*encoder
;
8351 list_for_each_entry(encoder
, &crtc
->dev
->mode_config
.encoder_list
,
8353 if (&encoder
->new_crtc
->base
!= crtc
)
8357 if (!encoder
->cloneable
)
8358 uncloneable_encoders
= true;
8361 return !(num_encoders
> 1 && uncloneable_encoders
);
8364 static struct intel_crtc_config
*
8365 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
8366 struct drm_framebuffer
*fb
,
8367 struct drm_display_mode
*mode
)
8369 struct drm_device
*dev
= crtc
->dev
;
8370 struct intel_encoder
*encoder
;
8371 struct intel_crtc_config
*pipe_config
;
8372 int plane_bpp
, ret
= -EINVAL
;
8375 if (!check_encoder_cloning(crtc
)) {
8376 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8377 return ERR_PTR(-EINVAL
);
8380 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
8382 return ERR_PTR(-ENOMEM
);
8384 drm_mode_copy(&pipe_config
->adjusted_mode
, mode
);
8385 drm_mode_copy(&pipe_config
->requested_mode
, mode
);
8386 pipe_config
->cpu_transcoder
=
8387 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
8388 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
8391 * Sanitize sync polarity flags based on requested ones. If neither
8392 * positive or negative polarity is requested, treat this as meaning
8393 * negative polarity.
8395 if (!(pipe_config
->adjusted_mode
.flags
&
8396 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
8397 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
8399 if (!(pipe_config
->adjusted_mode
.flags
&
8400 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
8401 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
8403 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8404 * plane pixel format and any sink constraints into account. Returns the
8405 * source plane bpp so that dithering can be selected on mismatches
8406 * after encoders and crtc also have had their say. */
8407 plane_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
8413 /* Ensure the port clock defaults are reset when retrying. */
8414 pipe_config
->port_clock
= 0;
8415 pipe_config
->pixel_multiplier
= 1;
8417 /* Fill in default crtc timings, allow encoders to overwrite them. */
8418 drm_mode_set_crtcinfo(&pipe_config
->adjusted_mode
, 0);
8420 /* Pass our mode to the connectors and the CRTC to give them a chance to
8421 * adjust it according to limitations or connector properties, and also
8422 * a chance to reject the mode entirely.
8424 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8427 if (&encoder
->new_crtc
->base
!= crtc
)
8430 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
8431 DRM_DEBUG_KMS("Encoder config failure\n");
8436 /* Set default port clock if not overwritten by the encoder. Needs to be
8437 * done afterwards in case the encoder adjusts the mode. */
8438 if (!pipe_config
->port_clock
)
8439 pipe_config
->port_clock
= pipe_config
->adjusted_mode
.clock
*
8440 pipe_config
->pixel_multiplier
;
8442 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
8444 DRM_DEBUG_KMS("CRTC fixup failed\n");
8449 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
8454 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8459 pipe_config
->dither
= pipe_config
->pipe_bpp
!= plane_bpp
;
8460 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8461 plane_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
8466 return ERR_PTR(ret
);
8469 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
8470 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8472 intel_modeset_affected_pipes(struct drm_crtc
*crtc
, unsigned *modeset_pipes
,
8473 unsigned *prepare_pipes
, unsigned *disable_pipes
)
8475 struct intel_crtc
*intel_crtc
;
8476 struct drm_device
*dev
= crtc
->dev
;
8477 struct intel_encoder
*encoder
;
8478 struct intel_connector
*connector
;
8479 struct drm_crtc
*tmp_crtc
;
8481 *disable_pipes
= *modeset_pipes
= *prepare_pipes
= 0;
8483 /* Check which crtcs have changed outputs connected to them, these need
8484 * to be part of the prepare_pipes mask. We don't (yet) support global
8485 * modeset across multiple crtcs, so modeset_pipes will only have one
8486 * bit set at most. */
8487 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8489 if (connector
->base
.encoder
== &connector
->new_encoder
->base
)
8492 if (connector
->base
.encoder
) {
8493 tmp_crtc
= connector
->base
.encoder
->crtc
;
8495 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
8498 if (connector
->new_encoder
)
8500 1 << connector
->new_encoder
->new_crtc
->pipe
;
8503 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8505 if (encoder
->base
.crtc
== &encoder
->new_crtc
->base
)
8508 if (encoder
->base
.crtc
) {
8509 tmp_crtc
= encoder
->base
.crtc
;
8511 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
8514 if (encoder
->new_crtc
)
8515 *prepare_pipes
|= 1 << encoder
->new_crtc
->pipe
;
8518 /* Check for any pipes that will be fully disabled ... */
8519 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
8523 /* Don't try to disable disabled crtcs. */
8524 if (!intel_crtc
->base
.enabled
)
8527 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8529 if (encoder
->new_crtc
== intel_crtc
)
8534 *disable_pipes
|= 1 << intel_crtc
->pipe
;
8538 /* set_mode is also used to update properties on life display pipes. */
8539 intel_crtc
= to_intel_crtc(crtc
);
8541 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
8544 * For simplicity do a full modeset on any pipe where the output routing
8545 * changed. We could be more clever, but that would require us to be
8546 * more careful with calling the relevant encoder->mode_set functions.
8549 *modeset_pipes
= *prepare_pipes
;
8551 /* ... and mask these out. */
8552 *modeset_pipes
&= ~(*disable_pipes
);
8553 *prepare_pipes
&= ~(*disable_pipes
);
8556 * HACK: We don't (yet) fully support global modesets. intel_set_config
8557 * obies this rule, but the modeset restore mode of
8558 * intel_modeset_setup_hw_state does not.
8560 *modeset_pipes
&= 1 << intel_crtc
->pipe
;
8561 *prepare_pipes
&= 1 << intel_crtc
->pipe
;
8563 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8564 *modeset_pipes
, *prepare_pipes
, *disable_pipes
);
8567 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
8569 struct drm_encoder
*encoder
;
8570 struct drm_device
*dev
= crtc
->dev
;
8572 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
8573 if (encoder
->crtc
== crtc
)
8580 intel_modeset_update_state(struct drm_device
*dev
, unsigned prepare_pipes
)
8582 struct intel_encoder
*intel_encoder
;
8583 struct intel_crtc
*intel_crtc
;
8584 struct drm_connector
*connector
;
8586 list_for_each_entry(intel_encoder
, &dev
->mode_config
.encoder_list
,
8588 if (!intel_encoder
->base
.crtc
)
8591 intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
8593 if (prepare_pipes
& (1 << intel_crtc
->pipe
))
8594 intel_encoder
->connectors_active
= false;
8597 intel_modeset_commit_output_state(dev
);
8599 /* Update computed state. */
8600 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
8602 intel_crtc
->base
.enabled
= intel_crtc_in_use(&intel_crtc
->base
);
8605 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
8606 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
8609 intel_crtc
= to_intel_crtc(connector
->encoder
->crtc
);
8611 if (prepare_pipes
& (1 << intel_crtc
->pipe
)) {
8612 struct drm_property
*dpms_property
=
8613 dev
->mode_config
.dpms_property
;
8615 connector
->dpms
= DRM_MODE_DPMS_ON
;
8616 drm_object_property_set_value(&connector
->base
,
8620 intel_encoder
= to_intel_encoder(connector
->encoder
);
8621 intel_encoder
->connectors_active
= true;
8627 static bool intel_fuzzy_clock_check(int clock1
, int clock2
)
8631 if (clock1
== clock2
)
8634 if (!clock1
|| !clock2
)
8637 diff
= abs(clock1
- clock2
);
8639 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
8645 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8646 list_for_each_entry((intel_crtc), \
8647 &(dev)->mode_config.crtc_list, \
8649 if (mask & (1 <<(intel_crtc)->pipe))
8652 intel_pipe_config_compare(struct drm_device
*dev
,
8653 struct intel_crtc_config
*current_config
,
8654 struct intel_crtc_config
*pipe_config
)
8656 #define PIPE_CONF_CHECK_X(name) \
8657 if (current_config->name != pipe_config->name) { \
8658 DRM_ERROR("mismatch in " #name " " \
8659 "(expected 0x%08x, found 0x%08x)\n", \
8660 current_config->name, \
8661 pipe_config->name); \
8665 #define PIPE_CONF_CHECK_I(name) \
8666 if (current_config->name != pipe_config->name) { \
8667 DRM_ERROR("mismatch in " #name " " \
8668 "(expected %i, found %i)\n", \
8669 current_config->name, \
8670 pipe_config->name); \
8674 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
8675 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8676 DRM_ERROR("mismatch in " #name "(" #mask ") " \
8677 "(expected %i, found %i)\n", \
8678 current_config->name & (mask), \
8679 pipe_config->name & (mask)); \
8683 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
8684 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
8685 DRM_ERROR("mismatch in " #name " " \
8686 "(expected %i, found %i)\n", \
8687 current_config->name, \
8688 pipe_config->name); \
8692 #define PIPE_CONF_QUIRK(quirk) \
8693 ((current_config->quirks | pipe_config->quirks) & (quirk))
8695 PIPE_CONF_CHECK_I(cpu_transcoder
);
8697 PIPE_CONF_CHECK_I(has_pch_encoder
);
8698 PIPE_CONF_CHECK_I(fdi_lanes
);
8699 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_m
);
8700 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_n
);
8701 PIPE_CONF_CHECK_I(fdi_m_n
.link_m
);
8702 PIPE_CONF_CHECK_I(fdi_m_n
.link_n
);
8703 PIPE_CONF_CHECK_I(fdi_m_n
.tu
);
8705 PIPE_CONF_CHECK_I(has_dp_encoder
);
8706 PIPE_CONF_CHECK_I(dp_m_n
.gmch_m
);
8707 PIPE_CONF_CHECK_I(dp_m_n
.gmch_n
);
8708 PIPE_CONF_CHECK_I(dp_m_n
.link_m
);
8709 PIPE_CONF_CHECK_I(dp_m_n
.link_n
);
8710 PIPE_CONF_CHECK_I(dp_m_n
.tu
);
8712 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hdisplay
);
8713 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_htotal
);
8714 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_start
);
8715 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_end
);
8716 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_start
);
8717 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_end
);
8719 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vdisplay
);
8720 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vtotal
);
8721 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_start
);
8722 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_end
);
8723 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_start
);
8724 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_end
);
8726 PIPE_CONF_CHECK_I(pixel_multiplier
);
8728 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8729 DRM_MODE_FLAG_INTERLACE
);
8731 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
8732 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8733 DRM_MODE_FLAG_PHSYNC
);
8734 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8735 DRM_MODE_FLAG_NHSYNC
);
8736 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8737 DRM_MODE_FLAG_PVSYNC
);
8738 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8739 DRM_MODE_FLAG_NVSYNC
);
8742 PIPE_CONF_CHECK_I(requested_mode
.hdisplay
);
8743 PIPE_CONF_CHECK_I(requested_mode
.vdisplay
);
8745 PIPE_CONF_CHECK_I(gmch_pfit
.control
);
8746 /* pfit ratios are autocomputed by the hw on gen4+ */
8747 if (INTEL_INFO(dev
)->gen
< 4)
8748 PIPE_CONF_CHECK_I(gmch_pfit
.pgm_ratios
);
8749 PIPE_CONF_CHECK_I(gmch_pfit
.lvds_border_bits
);
8750 PIPE_CONF_CHECK_I(pch_pfit
.pos
);
8751 PIPE_CONF_CHECK_I(pch_pfit
.size
);
8753 PIPE_CONF_CHECK_I(ips_enabled
);
8755 PIPE_CONF_CHECK_I(shared_dpll
);
8756 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
8757 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
8758 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
8759 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
8761 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5)
8762 PIPE_CONF_CHECK_I(pipe_bpp
);
8764 if (!IS_HASWELL(dev
)) {
8765 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode
.clock
);
8766 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
8769 #undef PIPE_CONF_CHECK_X
8770 #undef PIPE_CONF_CHECK_I
8771 #undef PIPE_CONF_CHECK_FLAGS
8772 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
8773 #undef PIPE_CONF_QUIRK
8779 check_connector_state(struct drm_device
*dev
)
8781 struct intel_connector
*connector
;
8783 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8785 /* This also checks the encoder/connector hw state with the
8786 * ->get_hw_state callbacks. */
8787 intel_connector_check_state(connector
);
8789 WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
8790 "connector's staged encoder doesn't match current encoder\n");
8795 check_encoder_state(struct drm_device
*dev
)
8797 struct intel_encoder
*encoder
;
8798 struct intel_connector
*connector
;
8800 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8802 bool enabled
= false;
8803 bool active
= false;
8804 enum pipe pipe
, tracked_pipe
;
8806 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8807 encoder
->base
.base
.id
,
8808 drm_get_encoder_name(&encoder
->base
));
8810 WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
8811 "encoder's stage crtc doesn't match current crtc\n");
8812 WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
8813 "encoder's active_connectors set, but no crtc\n");
8815 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8817 if (connector
->base
.encoder
!= &encoder
->base
)
8820 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
8823 WARN(!!encoder
->base
.crtc
!= enabled
,
8824 "encoder's enabled state mismatch "
8825 "(expected %i, found %i)\n",
8826 !!encoder
->base
.crtc
, enabled
);
8827 WARN(active
&& !encoder
->base
.crtc
,
8828 "active encoder with no crtc\n");
8830 WARN(encoder
->connectors_active
!= active
,
8831 "encoder's computed active state doesn't match tracked active state "
8832 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
8834 active
= encoder
->get_hw_state(encoder
, &pipe
);
8835 WARN(active
!= encoder
->connectors_active
,
8836 "encoder's hw state doesn't match sw tracking "
8837 "(expected %i, found %i)\n",
8838 encoder
->connectors_active
, active
);
8840 if (!encoder
->base
.crtc
)
8843 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
8844 WARN(active
&& pipe
!= tracked_pipe
,
8845 "active encoder's pipe doesn't match"
8846 "(expected %i, found %i)\n",
8847 tracked_pipe
, pipe
);
8853 check_crtc_state(struct drm_device
*dev
)
8855 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8856 struct intel_crtc
*crtc
;
8857 struct intel_encoder
*encoder
;
8858 struct intel_crtc_config pipe_config
;
8860 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
8862 bool enabled
= false;
8863 bool active
= false;
8865 memset(&pipe_config
, 0, sizeof(pipe_config
));
8867 DRM_DEBUG_KMS("[CRTC:%d]\n",
8868 crtc
->base
.base
.id
);
8870 WARN(crtc
->active
&& !crtc
->base
.enabled
,
8871 "active crtc, but not enabled in sw tracking\n");
8873 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8875 if (encoder
->base
.crtc
!= &crtc
->base
)
8878 if (encoder
->connectors_active
)
8882 WARN(active
!= crtc
->active
,
8883 "crtc's computed active state doesn't match tracked active state "
8884 "(expected %i, found %i)\n", active
, crtc
->active
);
8885 WARN(enabled
!= crtc
->base
.enabled
,
8886 "crtc's computed enabled state doesn't match tracked enabled state "
8887 "(expected %i, found %i)\n", enabled
, crtc
->base
.enabled
);
8889 active
= dev_priv
->display
.get_pipe_config(crtc
,
8892 /* hw state is inconsistent with the pipe A quirk */
8893 if (crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
8894 active
= crtc
->active
;
8896 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8899 if (encoder
->base
.crtc
!= &crtc
->base
)
8901 if (encoder
->get_config
&&
8902 encoder
->get_hw_state(encoder
, &pipe
))
8903 encoder
->get_config(encoder
, &pipe_config
);
8906 WARN(crtc
->active
!= active
,
8907 "crtc active state doesn't match with hw state "
8908 "(expected %i, found %i)\n", crtc
->active
, active
);
8911 !intel_pipe_config_compare(dev
, &crtc
->config
, &pipe_config
)) {
8912 WARN(1, "pipe state doesn't match!\n");
8913 intel_dump_pipe_config(crtc
, &pipe_config
,
8915 intel_dump_pipe_config(crtc
, &crtc
->config
,
8922 check_shared_dpll_state(struct drm_device
*dev
)
8924 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8925 struct intel_crtc
*crtc
;
8926 struct intel_dpll_hw_state dpll_hw_state
;
8929 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
8930 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
8931 int enabled_crtcs
= 0, active_crtcs
= 0;
8934 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
8936 DRM_DEBUG_KMS("%s\n", pll
->name
);
8938 active
= pll
->get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
8940 WARN(pll
->active
> pll
->refcount
,
8941 "more active pll users than references: %i vs %i\n",
8942 pll
->active
, pll
->refcount
);
8943 WARN(pll
->active
&& !pll
->on
,
8944 "pll in active use but not on in sw tracking\n");
8945 WARN(pll
->on
&& !pll
->active
,
8946 "pll in on but not on in use in sw tracking\n");
8947 WARN(pll
->on
!= active
,
8948 "pll on state mismatch (expected %i, found %i)\n",
8951 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
8953 if (crtc
->base
.enabled
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
8955 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
8958 WARN(pll
->active
!= active_crtcs
,
8959 "pll active crtcs mismatch (expected %i, found %i)\n",
8960 pll
->active
, active_crtcs
);
8961 WARN(pll
->refcount
!= enabled_crtcs
,
8962 "pll enabled crtcs mismatch (expected %i, found %i)\n",
8963 pll
->refcount
, enabled_crtcs
);
8965 WARN(pll
->on
&& memcmp(&pll
->hw_state
, &dpll_hw_state
,
8966 sizeof(dpll_hw_state
)),
8967 "pll hw state mismatch\n");
8972 intel_modeset_check_state(struct drm_device
*dev
)
8974 check_connector_state(dev
);
8975 check_encoder_state(dev
);
8976 check_crtc_state(dev
);
8977 check_shared_dpll_state(dev
);
8980 void ironlake_check_encoder_dotclock(const struct intel_crtc_config
*pipe_config
,
8984 * FDI already provided one idea for the dotclock.
8985 * Yell if the encoder disagrees.
8987 WARN(!intel_fuzzy_clock_check(pipe_config
->adjusted_mode
.clock
, dotclock
),
8988 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
8989 pipe_config
->adjusted_mode
.clock
, dotclock
);
8992 static int __intel_set_mode(struct drm_crtc
*crtc
,
8993 struct drm_display_mode
*mode
,
8994 int x
, int y
, struct drm_framebuffer
*fb
)
8996 struct drm_device
*dev
= crtc
->dev
;
8997 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8998 struct drm_display_mode
*saved_mode
, *saved_hwmode
;
8999 struct intel_crtc_config
*pipe_config
= NULL
;
9000 struct intel_crtc
*intel_crtc
;
9001 unsigned disable_pipes
, prepare_pipes
, modeset_pipes
;
9004 saved_mode
= kmalloc(2 * sizeof(*saved_mode
), GFP_KERNEL
);
9007 saved_hwmode
= saved_mode
+ 1;
9009 intel_modeset_affected_pipes(crtc
, &modeset_pipes
,
9010 &prepare_pipes
, &disable_pipes
);
9012 *saved_hwmode
= crtc
->hwmode
;
9013 *saved_mode
= crtc
->mode
;
9015 /* Hack: Because we don't (yet) support global modeset on multiple
9016 * crtcs, we don't keep track of the new mode for more than one crtc.
9017 * Hence simply check whether any bit is set in modeset_pipes in all the
9018 * pieces of code that are not yet converted to deal with mutliple crtcs
9019 * changing their mode at the same time. */
9020 if (modeset_pipes
) {
9021 pipe_config
= intel_modeset_pipe_config(crtc
, fb
, mode
);
9022 if (IS_ERR(pipe_config
)) {
9023 ret
= PTR_ERR(pipe_config
);
9028 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,
9032 for_each_intel_crtc_masked(dev
, disable_pipes
, intel_crtc
)
9033 intel_crtc_disable(&intel_crtc
->base
);
9035 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
9036 if (intel_crtc
->base
.enabled
)
9037 dev_priv
->display
.crtc_disable(&intel_crtc
->base
);
9040 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9041 * to set it here already despite that we pass it down the callchain.
9043 if (modeset_pipes
) {
9045 /* mode_set/enable/disable functions rely on a correct pipe
9047 to_intel_crtc(crtc
)->config
= *pipe_config
;
9050 /* Only after disabling all output pipelines that will be changed can we
9051 * update the the output configuration. */
9052 intel_modeset_update_state(dev
, prepare_pipes
);
9054 if (dev_priv
->display
.modeset_global_resources
)
9055 dev_priv
->display
.modeset_global_resources(dev
);
9057 /* Set up the DPLL and any encoders state that needs to adjust or depend
9060 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
9061 ret
= intel_crtc_mode_set(&intel_crtc
->base
,
9067 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9068 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
)
9069 dev_priv
->display
.crtc_enable(&intel_crtc
->base
);
9071 if (modeset_pipes
) {
9072 /* Store real post-adjustment hardware mode. */
9073 crtc
->hwmode
= pipe_config
->adjusted_mode
;
9075 /* Calculate and store various constants which
9076 * are later needed by vblank and swap-completion
9077 * timestamping. They are derived from true hwmode.
9079 drm_calc_timestamping_constants(crtc
);
9082 /* FIXME: add subpixel order */
9084 if (ret
&& crtc
->enabled
) {
9085 crtc
->hwmode
= *saved_hwmode
;
9086 crtc
->mode
= *saved_mode
;
9095 static int intel_set_mode(struct drm_crtc
*crtc
,
9096 struct drm_display_mode
*mode
,
9097 int x
, int y
, struct drm_framebuffer
*fb
)
9101 ret
= __intel_set_mode(crtc
, mode
, x
, y
, fb
);
9104 intel_modeset_check_state(crtc
->dev
);
9109 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
9111 intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
, crtc
->fb
);
9114 #undef for_each_intel_crtc_masked
9116 static void intel_set_config_free(struct intel_set_config
*config
)
9121 kfree(config
->save_connector_encoders
);
9122 kfree(config
->save_encoder_crtcs
);
9126 static int intel_set_config_save_state(struct drm_device
*dev
,
9127 struct intel_set_config
*config
)
9129 struct drm_encoder
*encoder
;
9130 struct drm_connector
*connector
;
9133 config
->save_encoder_crtcs
=
9134 kcalloc(dev
->mode_config
.num_encoder
,
9135 sizeof(struct drm_crtc
*), GFP_KERNEL
);
9136 if (!config
->save_encoder_crtcs
)
9139 config
->save_connector_encoders
=
9140 kcalloc(dev
->mode_config
.num_connector
,
9141 sizeof(struct drm_encoder
*), GFP_KERNEL
);
9142 if (!config
->save_connector_encoders
)
9145 /* Copy data. Note that driver private data is not affected.
9146 * Should anything bad happen only the expected state is
9147 * restored, not the drivers personal bookkeeping.
9150 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
9151 config
->save_encoder_crtcs
[count
++] = encoder
->crtc
;
9155 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
9156 config
->save_connector_encoders
[count
++] = connector
->encoder
;
9162 static void intel_set_config_restore_state(struct drm_device
*dev
,
9163 struct intel_set_config
*config
)
9165 struct intel_encoder
*encoder
;
9166 struct intel_connector
*connector
;
9170 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
9172 to_intel_crtc(config
->save_encoder_crtcs
[count
++]);
9176 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
9177 connector
->new_encoder
=
9178 to_intel_encoder(config
->save_connector_encoders
[count
++]);
9183 is_crtc_connector_off(struct drm_mode_set
*set
)
9187 if (set
->num_connectors
== 0)
9190 if (WARN_ON(set
->connectors
== NULL
))
9193 for (i
= 0; i
< set
->num_connectors
; i
++)
9194 if (set
->connectors
[i
]->encoder
&&
9195 set
->connectors
[i
]->encoder
->crtc
== set
->crtc
&&
9196 set
->connectors
[i
]->dpms
!= DRM_MODE_DPMS_ON
)
9203 intel_set_config_compute_mode_changes(struct drm_mode_set
*set
,
9204 struct intel_set_config
*config
)
9207 /* We should be able to check here if the fb has the same properties
9208 * and then just flip_or_move it */
9209 if (is_crtc_connector_off(set
)) {
9210 config
->mode_changed
= true;
9211 } else if (set
->crtc
->fb
!= set
->fb
) {
9212 /* If we have no fb then treat it as a full mode set */
9213 if (set
->crtc
->fb
== NULL
) {
9214 struct intel_crtc
*intel_crtc
=
9215 to_intel_crtc(set
->crtc
);
9217 if (intel_crtc
->active
&& i915_fastboot
) {
9218 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9219 config
->fb_changed
= true;
9221 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9222 config
->mode_changed
= true;
9224 } else if (set
->fb
== NULL
) {
9225 config
->mode_changed
= true;
9226 } else if (set
->fb
->pixel_format
!=
9227 set
->crtc
->fb
->pixel_format
) {
9228 config
->mode_changed
= true;
9230 config
->fb_changed
= true;
9234 if (set
->fb
&& (set
->x
!= set
->crtc
->x
|| set
->y
!= set
->crtc
->y
))
9235 config
->fb_changed
= true;
9237 if (set
->mode
&& !drm_mode_equal(set
->mode
, &set
->crtc
->mode
)) {
9238 DRM_DEBUG_KMS("modes are different, full mode set\n");
9239 drm_mode_debug_printmodeline(&set
->crtc
->mode
);
9240 drm_mode_debug_printmodeline(set
->mode
);
9241 config
->mode_changed
= true;
9244 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9245 set
->crtc
->base
.id
, config
->mode_changed
, config
->fb_changed
);
9249 intel_modeset_stage_output_state(struct drm_device
*dev
,
9250 struct drm_mode_set
*set
,
9251 struct intel_set_config
*config
)
9253 struct drm_crtc
*new_crtc
;
9254 struct intel_connector
*connector
;
9255 struct intel_encoder
*encoder
;
9258 /* The upper layers ensure that we either disable a crtc or have a list
9259 * of connectors. For paranoia, double-check this. */
9260 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
9261 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
9263 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9265 /* Otherwise traverse passed in connector list and get encoders
9267 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
9268 if (set
->connectors
[ro
] == &connector
->base
) {
9269 connector
->new_encoder
= connector
->encoder
;
9274 /* If we disable the crtc, disable all its connectors. Also, if
9275 * the connector is on the changing crtc but not on the new
9276 * connector list, disable it. */
9277 if ((!set
->fb
|| ro
== set
->num_connectors
) &&
9278 connector
->base
.encoder
&&
9279 connector
->base
.encoder
->crtc
== set
->crtc
) {
9280 connector
->new_encoder
= NULL
;
9282 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9283 connector
->base
.base
.id
,
9284 drm_get_connector_name(&connector
->base
));
9288 if (&connector
->new_encoder
->base
!= connector
->base
.encoder
) {
9289 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
9290 config
->mode_changed
= true;
9293 /* connector->new_encoder is now updated for all connectors. */
9295 /* Update crtc of enabled connectors. */
9296 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9298 if (!connector
->new_encoder
)
9301 new_crtc
= connector
->new_encoder
->base
.crtc
;
9303 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
9304 if (set
->connectors
[ro
] == &connector
->base
)
9305 new_crtc
= set
->crtc
;
9308 /* Make sure the new CRTC will work with the encoder */
9309 if (!intel_encoder_crtc_ok(&connector
->new_encoder
->base
,
9313 connector
->encoder
->new_crtc
= to_intel_crtc(new_crtc
);
9315 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9316 connector
->base
.base
.id
,
9317 drm_get_connector_name(&connector
->base
),
9321 /* Check for any encoders that needs to be disabled. */
9322 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9324 list_for_each_entry(connector
,
9325 &dev
->mode_config
.connector_list
,
9327 if (connector
->new_encoder
== encoder
) {
9328 WARN_ON(!connector
->new_encoder
->new_crtc
);
9333 encoder
->new_crtc
= NULL
;
9335 /* Only now check for crtc changes so we don't miss encoders
9336 * that will be disabled. */
9337 if (&encoder
->new_crtc
->base
!= encoder
->base
.crtc
) {
9338 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
9339 config
->mode_changed
= true;
9342 /* Now we've also updated encoder->new_crtc for all encoders. */
9347 static int intel_crtc_set_config(struct drm_mode_set
*set
)
9349 struct drm_device
*dev
;
9350 struct drm_mode_set save_set
;
9351 struct intel_set_config
*config
;
9356 BUG_ON(!set
->crtc
->helper_private
);
9358 /* Enforce sane interface api - has been abused by the fb helper. */
9359 BUG_ON(!set
->mode
&& set
->fb
);
9360 BUG_ON(set
->fb
&& set
->num_connectors
== 0);
9363 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9364 set
->crtc
->base
.id
, set
->fb
->base
.id
,
9365 (int)set
->num_connectors
, set
->x
, set
->y
);
9367 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
9370 dev
= set
->crtc
->dev
;
9373 config
= kzalloc(sizeof(*config
), GFP_KERNEL
);
9377 ret
= intel_set_config_save_state(dev
, config
);
9381 save_set
.crtc
= set
->crtc
;
9382 save_set
.mode
= &set
->crtc
->mode
;
9383 save_set
.x
= set
->crtc
->x
;
9384 save_set
.y
= set
->crtc
->y
;
9385 save_set
.fb
= set
->crtc
->fb
;
9387 /* Compute whether we need a full modeset, only an fb base update or no
9388 * change at all. In the future we might also check whether only the
9389 * mode changed, e.g. for LVDS where we only change the panel fitter in
9391 intel_set_config_compute_mode_changes(set
, config
);
9393 ret
= intel_modeset_stage_output_state(dev
, set
, config
);
9397 if (config
->mode_changed
) {
9398 ret
= intel_set_mode(set
->crtc
, set
->mode
,
9399 set
->x
, set
->y
, set
->fb
);
9400 } else if (config
->fb_changed
) {
9401 intel_crtc_wait_for_pending_flips(set
->crtc
);
9403 ret
= intel_pipe_set_base(set
->crtc
,
9404 set
->x
, set
->y
, set
->fb
);
9408 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9409 set
->crtc
->base
.id
, ret
);
9411 intel_set_config_restore_state(dev
, config
);
9413 /* Try to restore the config */
9414 if (config
->mode_changed
&&
9415 intel_set_mode(save_set
.crtc
, save_set
.mode
,
9416 save_set
.x
, save_set
.y
, save_set
.fb
))
9417 DRM_ERROR("failed to restore config after modeset failure\n");
9421 intel_set_config_free(config
);
9425 static const struct drm_crtc_funcs intel_crtc_funcs
= {
9426 .cursor_set
= intel_crtc_cursor_set
,
9427 .cursor_move
= intel_crtc_cursor_move
,
9428 .gamma_set
= intel_crtc_gamma_set
,
9429 .set_config
= intel_crtc_set_config
,
9430 .destroy
= intel_crtc_destroy
,
9431 .page_flip
= intel_crtc_page_flip
,
9434 static void intel_cpu_pll_init(struct drm_device
*dev
)
9437 intel_ddi_pll_init(dev
);
9440 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private
*dev_priv
,
9441 struct intel_shared_dpll
*pll
,
9442 struct intel_dpll_hw_state
*hw_state
)
9446 val
= I915_READ(PCH_DPLL(pll
->id
));
9447 hw_state
->dpll
= val
;
9448 hw_state
->fp0
= I915_READ(PCH_FP0(pll
->id
));
9449 hw_state
->fp1
= I915_READ(PCH_FP1(pll
->id
));
9451 return val
& DPLL_VCO_ENABLE
;
9454 static void ibx_pch_dpll_mode_set(struct drm_i915_private
*dev_priv
,
9455 struct intel_shared_dpll
*pll
)
9457 I915_WRITE(PCH_FP0(pll
->id
), pll
->hw_state
.fp0
);
9458 I915_WRITE(PCH_FP1(pll
->id
), pll
->hw_state
.fp1
);
9461 static void ibx_pch_dpll_enable(struct drm_i915_private
*dev_priv
,
9462 struct intel_shared_dpll
*pll
)
9464 /* PCH refclock must be enabled first */
9465 assert_pch_refclk_enabled(dev_priv
);
9467 I915_WRITE(PCH_DPLL(pll
->id
), pll
->hw_state
.dpll
);
9469 /* Wait for the clocks to stabilize. */
9470 POSTING_READ(PCH_DPLL(pll
->id
));
9473 /* The pixel multiplier can only be updated once the
9474 * DPLL is enabled and the clocks are stable.
9476 * So write it again.
9478 I915_WRITE(PCH_DPLL(pll
->id
), pll
->hw_state
.dpll
);
9479 POSTING_READ(PCH_DPLL(pll
->id
));
9483 static void ibx_pch_dpll_disable(struct drm_i915_private
*dev_priv
,
9484 struct intel_shared_dpll
*pll
)
9486 struct drm_device
*dev
= dev_priv
->dev
;
9487 struct intel_crtc
*crtc
;
9489 /* Make sure no transcoder isn't still depending on us. */
9490 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
9491 if (intel_crtc_to_shared_dpll(crtc
) == pll
)
9492 assert_pch_transcoder_disabled(dev_priv
, crtc
->pipe
);
9495 I915_WRITE(PCH_DPLL(pll
->id
), 0);
9496 POSTING_READ(PCH_DPLL(pll
->id
));
9500 static char *ibx_pch_dpll_names
[] = {
9505 static void ibx_pch_dpll_init(struct drm_device
*dev
)
9507 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9510 dev_priv
->num_shared_dpll
= 2;
9512 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
9513 dev_priv
->shared_dplls
[i
].id
= i
;
9514 dev_priv
->shared_dplls
[i
].name
= ibx_pch_dpll_names
[i
];
9515 dev_priv
->shared_dplls
[i
].mode_set
= ibx_pch_dpll_mode_set
;
9516 dev_priv
->shared_dplls
[i
].enable
= ibx_pch_dpll_enable
;
9517 dev_priv
->shared_dplls
[i
].disable
= ibx_pch_dpll_disable
;
9518 dev_priv
->shared_dplls
[i
].get_hw_state
=
9519 ibx_pch_dpll_get_hw_state
;
9523 static void intel_shared_dpll_init(struct drm_device
*dev
)
9525 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9527 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
9528 ibx_pch_dpll_init(dev
);
9530 dev_priv
->num_shared_dpll
= 0;
9532 BUG_ON(dev_priv
->num_shared_dpll
> I915_NUM_PLLS
);
9533 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9534 dev_priv
->num_shared_dpll
);
9537 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
9539 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
9540 struct intel_crtc
*intel_crtc
;
9543 intel_crtc
= kzalloc(sizeof(struct intel_crtc
) + (INTELFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
9544 if (intel_crtc
== NULL
)
9547 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
9549 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
9550 for (i
= 0; i
< 256; i
++) {
9551 intel_crtc
->lut_r
[i
] = i
;
9552 intel_crtc
->lut_g
[i
] = i
;
9553 intel_crtc
->lut_b
[i
] = i
;
9556 /* Swap pipes & planes for FBC on pre-965 */
9557 intel_crtc
->pipe
= pipe
;
9558 intel_crtc
->plane
= pipe
;
9559 if (IS_MOBILE(dev
) && IS_GEN3(dev
)) {
9560 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
9561 intel_crtc
->plane
= !pipe
;
9564 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
9565 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
9566 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
9567 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
9569 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
9572 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
9573 struct drm_file
*file
)
9575 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
9576 struct drm_mode_object
*drmmode_obj
;
9577 struct intel_crtc
*crtc
;
9579 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
9582 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
9583 DRM_MODE_OBJECT_CRTC
);
9586 DRM_ERROR("no such CRTC id\n");
9590 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
9591 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
9596 static int intel_encoder_clones(struct intel_encoder
*encoder
)
9598 struct drm_device
*dev
= encoder
->base
.dev
;
9599 struct intel_encoder
*source_encoder
;
9603 list_for_each_entry(source_encoder
,
9604 &dev
->mode_config
.encoder_list
, base
.head
) {
9606 if (encoder
== source_encoder
)
9607 index_mask
|= (1 << entry
);
9609 /* Intel hw has only one MUX where enocoders could be cloned. */
9610 if (encoder
->cloneable
&& source_encoder
->cloneable
)
9611 index_mask
|= (1 << entry
);
9619 static bool has_edp_a(struct drm_device
*dev
)
9621 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9623 if (!IS_MOBILE(dev
))
9626 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
9630 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES
) & ILK_eDP_A_DISABLE
))
9636 static void intel_setup_outputs(struct drm_device
*dev
)
9638 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9639 struct intel_encoder
*encoder
;
9640 bool dpd_is_edp
= false;
9642 intel_lvds_init(dev
);
9645 intel_crt_init(dev
);
9650 /* Haswell uses DDI functions to detect digital outputs */
9651 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
9652 /* DDI A only supports eDP */
9654 intel_ddi_init(dev
, PORT_A
);
9656 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9658 found
= I915_READ(SFUSE_STRAP
);
9660 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
9661 intel_ddi_init(dev
, PORT_B
);
9662 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
9663 intel_ddi_init(dev
, PORT_C
);
9664 if (found
& SFUSE_STRAP_DDID_DETECTED
)
9665 intel_ddi_init(dev
, PORT_D
);
9666 } else if (HAS_PCH_SPLIT(dev
)) {
9668 dpd_is_edp
= intel_dpd_is_edp(dev
);
9671 intel_dp_init(dev
, DP_A
, PORT_A
);
9673 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
9674 /* PCH SDVOB multiplex with HDMIB */
9675 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
9677 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
9678 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
9679 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
9682 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
9683 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
9685 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
9686 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
9688 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
9689 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
9691 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
9692 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
9693 } else if (IS_VALLEYVIEW(dev
)) {
9694 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9695 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIC
) & SDVO_DETECTED
) {
9696 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIC
,
9698 if (I915_READ(VLV_DISPLAY_BASE
+ DP_C
) & DP_DETECTED
)
9699 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_C
,
9703 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIB
) & SDVO_DETECTED
) {
9704 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIB
,
9706 if (I915_READ(VLV_DISPLAY_BASE
+ DP_B
) & DP_DETECTED
)
9707 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_B
, PORT_B
);
9710 intel_dsi_init(dev
);
9711 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
9714 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
9715 DRM_DEBUG_KMS("probing SDVOB\n");
9716 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, true);
9717 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
9718 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9719 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
9722 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
))
9723 intel_dp_init(dev
, DP_B
, PORT_B
);
9726 /* Before G4X SDVOC doesn't have its own detect register */
9728 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
9729 DRM_DEBUG_KMS("probing SDVOC\n");
9730 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, false);
9733 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
9735 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
9736 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9737 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
9739 if (SUPPORTS_INTEGRATED_DP(dev
))
9740 intel_dp_init(dev
, DP_C
, PORT_C
);
9743 if (SUPPORTS_INTEGRATED_DP(dev
) &&
9744 (I915_READ(DP_D
) & DP_DETECTED
))
9745 intel_dp_init(dev
, DP_D
, PORT_D
);
9746 } else if (IS_GEN2(dev
))
9747 intel_dvo_init(dev
);
9749 if (SUPPORTS_TV(dev
))
9752 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
9753 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
9754 encoder
->base
.possible_clones
=
9755 intel_encoder_clones(encoder
);
9758 intel_init_pch_refclk(dev
);
9760 drm_helper_move_panel_connectors_to_head(dev
);
9763 void intel_framebuffer_fini(struct intel_framebuffer
*fb
)
9765 drm_framebuffer_cleanup(&fb
->base
);
9766 drm_gem_object_unreference_unlocked(&fb
->obj
->base
);
9769 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
9771 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
9773 intel_framebuffer_fini(intel_fb
);
9777 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
9778 struct drm_file
*file
,
9779 unsigned int *handle
)
9781 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
9782 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
9784 return drm_gem_handle_create(file
, &obj
->base
, handle
);
9787 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
9788 .destroy
= intel_user_framebuffer_destroy
,
9789 .create_handle
= intel_user_framebuffer_create_handle
,
9792 int intel_framebuffer_init(struct drm_device
*dev
,
9793 struct intel_framebuffer
*intel_fb
,
9794 struct drm_mode_fb_cmd2
*mode_cmd
,
9795 struct drm_i915_gem_object
*obj
)
9800 if (obj
->tiling_mode
== I915_TILING_Y
) {
9801 DRM_DEBUG("hardware does not support tiling Y\n");
9805 if (mode_cmd
->pitches
[0] & 63) {
9806 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9807 mode_cmd
->pitches
[0]);
9811 if (INTEL_INFO(dev
)->gen
>= 5 && !IS_VALLEYVIEW(dev
)) {
9812 pitch_limit
= 32*1024;
9813 } else if (INTEL_INFO(dev
)->gen
>= 4) {
9814 if (obj
->tiling_mode
)
9815 pitch_limit
= 16*1024;
9817 pitch_limit
= 32*1024;
9818 } else if (INTEL_INFO(dev
)->gen
>= 3) {
9819 if (obj
->tiling_mode
)
9820 pitch_limit
= 8*1024;
9822 pitch_limit
= 16*1024;
9824 /* XXX DSPC is limited to 4k tiled */
9825 pitch_limit
= 8*1024;
9827 if (mode_cmd
->pitches
[0] > pitch_limit
) {
9828 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9829 obj
->tiling_mode
? "tiled" : "linear",
9830 mode_cmd
->pitches
[0], pitch_limit
);
9834 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
9835 mode_cmd
->pitches
[0] != obj
->stride
) {
9836 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9837 mode_cmd
->pitches
[0], obj
->stride
);
9841 /* Reject formats not supported by any plane early. */
9842 switch (mode_cmd
->pixel_format
) {
9844 case DRM_FORMAT_RGB565
:
9845 case DRM_FORMAT_XRGB8888
:
9846 case DRM_FORMAT_ARGB8888
:
9848 case DRM_FORMAT_XRGB1555
:
9849 case DRM_FORMAT_ARGB1555
:
9850 if (INTEL_INFO(dev
)->gen
> 3) {
9851 DRM_DEBUG("unsupported pixel format: %s\n",
9852 drm_get_format_name(mode_cmd
->pixel_format
));
9856 case DRM_FORMAT_XBGR8888
:
9857 case DRM_FORMAT_ABGR8888
:
9858 case DRM_FORMAT_XRGB2101010
:
9859 case DRM_FORMAT_ARGB2101010
:
9860 case DRM_FORMAT_XBGR2101010
:
9861 case DRM_FORMAT_ABGR2101010
:
9862 if (INTEL_INFO(dev
)->gen
< 4) {
9863 DRM_DEBUG("unsupported pixel format: %s\n",
9864 drm_get_format_name(mode_cmd
->pixel_format
));
9868 case DRM_FORMAT_YUYV
:
9869 case DRM_FORMAT_UYVY
:
9870 case DRM_FORMAT_YVYU
:
9871 case DRM_FORMAT_VYUY
:
9872 if (INTEL_INFO(dev
)->gen
< 5) {
9873 DRM_DEBUG("unsupported pixel format: %s\n",
9874 drm_get_format_name(mode_cmd
->pixel_format
));
9879 DRM_DEBUG("unsupported pixel format: %s\n",
9880 drm_get_format_name(mode_cmd
->pixel_format
));
9884 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9885 if (mode_cmd
->offsets
[0] != 0)
9888 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
9889 intel_fb
->obj
= obj
;
9891 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
9893 DRM_ERROR("framebuffer init failed %d\n", ret
);
9900 static struct drm_framebuffer
*
9901 intel_user_framebuffer_create(struct drm_device
*dev
,
9902 struct drm_file
*filp
,
9903 struct drm_mode_fb_cmd2
*mode_cmd
)
9905 struct drm_i915_gem_object
*obj
;
9907 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
9908 mode_cmd
->handles
[0]));
9909 if (&obj
->base
== NULL
)
9910 return ERR_PTR(-ENOENT
);
9912 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
9915 static const struct drm_mode_config_funcs intel_mode_funcs
= {
9916 .fb_create
= intel_user_framebuffer_create
,
9917 .output_poll_changed
= intel_fb_output_poll_changed
,
9920 /* Set up chip specific display functions */
9921 static void intel_init_display(struct drm_device
*dev
)
9923 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9925 if (HAS_PCH_SPLIT(dev
) || IS_G4X(dev
))
9926 dev_priv
->display
.find_dpll
= g4x_find_best_dpll
;
9927 else if (IS_VALLEYVIEW(dev
))
9928 dev_priv
->display
.find_dpll
= vlv_find_best_dpll
;
9929 else if (IS_PINEVIEW(dev
))
9930 dev_priv
->display
.find_dpll
= pnv_find_best_dpll
;
9932 dev_priv
->display
.find_dpll
= i9xx_find_best_dpll
;
9935 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
9936 dev_priv
->display
.crtc_mode_set
= haswell_crtc_mode_set
;
9937 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
9938 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
9939 dev_priv
->display
.off
= haswell_crtc_off
;
9940 dev_priv
->display
.update_plane
= ironlake_update_plane
;
9941 } else if (HAS_PCH_SPLIT(dev
)) {
9942 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
9943 dev_priv
->display
.crtc_mode_set
= ironlake_crtc_mode_set
;
9944 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
9945 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
9946 dev_priv
->display
.off
= ironlake_crtc_off
;
9947 dev_priv
->display
.update_plane
= ironlake_update_plane
;
9948 } else if (IS_VALLEYVIEW(dev
)) {
9949 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
9950 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
9951 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
9952 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
9953 dev_priv
->display
.off
= i9xx_crtc_off
;
9954 dev_priv
->display
.update_plane
= i9xx_update_plane
;
9956 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
9957 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
9958 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
9959 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
9960 dev_priv
->display
.off
= i9xx_crtc_off
;
9961 dev_priv
->display
.update_plane
= i9xx_update_plane
;
9964 /* Returns the core display clock speed */
9965 if (IS_VALLEYVIEW(dev
))
9966 dev_priv
->display
.get_display_clock_speed
=
9967 valleyview_get_display_clock_speed
;
9968 else if (IS_I945G(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
9969 dev_priv
->display
.get_display_clock_speed
=
9970 i945_get_display_clock_speed
;
9971 else if (IS_I915G(dev
))
9972 dev_priv
->display
.get_display_clock_speed
=
9973 i915_get_display_clock_speed
;
9974 else if (IS_I945GM(dev
) || IS_845G(dev
))
9975 dev_priv
->display
.get_display_clock_speed
=
9976 i9xx_misc_get_display_clock_speed
;
9977 else if (IS_PINEVIEW(dev
))
9978 dev_priv
->display
.get_display_clock_speed
=
9979 pnv_get_display_clock_speed
;
9980 else if (IS_I915GM(dev
))
9981 dev_priv
->display
.get_display_clock_speed
=
9982 i915gm_get_display_clock_speed
;
9983 else if (IS_I865G(dev
))
9984 dev_priv
->display
.get_display_clock_speed
=
9985 i865_get_display_clock_speed
;
9986 else if (IS_I85X(dev
))
9987 dev_priv
->display
.get_display_clock_speed
=
9988 i855_get_display_clock_speed
;
9990 dev_priv
->display
.get_display_clock_speed
=
9991 i830_get_display_clock_speed
;
9993 if (HAS_PCH_SPLIT(dev
)) {
9995 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
9996 dev_priv
->display
.write_eld
= ironlake_write_eld
;
9997 } else if (IS_GEN6(dev
)) {
9998 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
9999 dev_priv
->display
.write_eld
= ironlake_write_eld
;
10000 } else if (IS_IVYBRIDGE(dev
)) {
10001 /* FIXME: detect B0+ stepping and use auto training */
10002 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
10003 dev_priv
->display
.write_eld
= ironlake_write_eld
;
10004 dev_priv
->display
.modeset_global_resources
=
10005 ivb_modeset_global_resources
;
10006 } else if (IS_HASWELL(dev
)) {
10007 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
10008 dev_priv
->display
.write_eld
= haswell_write_eld
;
10009 dev_priv
->display
.modeset_global_resources
=
10010 haswell_modeset_global_resources
;
10012 } else if (IS_G4X(dev
)) {
10013 dev_priv
->display
.write_eld
= g4x_write_eld
;
10016 /* Default just returns -ENODEV to indicate unsupported */
10017 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
10019 switch (INTEL_INFO(dev
)->gen
) {
10021 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
10025 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
10030 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
10034 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
10037 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
10043 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10044 * resume, or other times. This quirk makes sure that's the case for
10045 * affected systems.
10047 static void quirk_pipea_force(struct drm_device
*dev
)
10049 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10051 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
10052 DRM_INFO("applying pipe a force quirk\n");
10056 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10058 static void quirk_ssc_force_disable(struct drm_device
*dev
)
10060 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10061 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
10062 DRM_INFO("applying lvds SSC disable quirk\n");
10066 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10069 static void quirk_invert_brightness(struct drm_device
*dev
)
10071 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10072 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
10073 DRM_INFO("applying inverted panel brightness quirk\n");
10077 * Some machines (Dell XPS13) suffer broken backlight controls if
10078 * BLM_PCH_PWM_ENABLE is set.
10080 static void quirk_no_pcm_pwm_enable(struct drm_device
*dev
)
10082 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10083 dev_priv
->quirks
|= QUIRK_NO_PCH_PWM_ENABLE
;
10084 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10087 struct intel_quirk
{
10089 int subsystem_vendor
;
10090 int subsystem_device
;
10091 void (*hook
)(struct drm_device
*dev
);
10094 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10095 struct intel_dmi_quirk
{
10096 void (*hook
)(struct drm_device
*dev
);
10097 const struct dmi_system_id (*dmi_id_list
)[];
10100 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
10102 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
10106 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
10108 .dmi_id_list
= &(const struct dmi_system_id
[]) {
10110 .callback
= intel_dmi_reverse_brightness
,
10111 .ident
= "NCR Corporation",
10112 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
10113 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
10116 { } /* terminating entry */
10118 .hook
= quirk_invert_brightness
,
10122 static struct intel_quirk intel_quirks
[] = {
10123 /* HP Mini needs pipe A force quirk (LP: #322104) */
10124 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
10126 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10127 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
10129 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10130 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
10132 /* 830/845 need to leave pipe A & dpll A up */
10133 { 0x2562, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
10134 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
10136 /* Lenovo U160 cannot use SSC on LVDS */
10137 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
10139 /* Sony Vaio Y cannot use SSC on LVDS */
10140 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
10142 /* Acer Aspire 5734Z must invert backlight brightness */
10143 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
10145 /* Acer/eMachines G725 */
10146 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
10148 /* Acer/eMachines e725 */
10149 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
10151 /* Acer/Packard Bell NCL20 */
10152 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
10154 /* Acer Aspire 4736Z */
10155 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
10157 /* Dell XPS13 HD Sandy Bridge */
10158 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable
},
10159 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10160 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable
},
10163 static void intel_init_quirks(struct drm_device
*dev
)
10165 struct pci_dev
*d
= dev
->pdev
;
10168 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
10169 struct intel_quirk
*q
= &intel_quirks
[i
];
10171 if (d
->device
== q
->device
&&
10172 (d
->subsystem_vendor
== q
->subsystem_vendor
||
10173 q
->subsystem_vendor
== PCI_ANY_ID
) &&
10174 (d
->subsystem_device
== q
->subsystem_device
||
10175 q
->subsystem_device
== PCI_ANY_ID
))
10178 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
10179 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
10180 intel_dmi_quirks
[i
].hook(dev
);
10184 /* Disable the VGA plane that we never use */
10185 static void i915_disable_vga(struct drm_device
*dev
)
10187 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10189 u32 vga_reg
= i915_vgacntrl_reg(dev
);
10191 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
10192 outb(SR01
, VGA_SR_INDEX
);
10193 sr1
= inb(VGA_SR_DATA
);
10194 outb(sr1
| 1<<5, VGA_SR_DATA
);
10196 /* Disable VGA memory on Intel HD */
10197 if (HAS_PCH_SPLIT(dev
)) {
10198 outb(inb(VGA_MSR_READ
) & ~VGA_MSR_MEM_EN
, VGA_MSR_WRITE
);
10199 vga_set_legacy_decoding(dev
->pdev
, VGA_RSRC_LEGACY_IO
|
10200 VGA_RSRC_NORMAL_IO
|
10201 VGA_RSRC_NORMAL_MEM
);
10204 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
10207 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
10208 POSTING_READ(vga_reg
);
10211 static void i915_enable_vga(struct drm_device
*dev
)
10213 /* Enable VGA memory on Intel HD */
10214 if (HAS_PCH_SPLIT(dev
)) {
10215 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
10216 outb(inb(VGA_MSR_READ
) | VGA_MSR_MEM_EN
, VGA_MSR_WRITE
);
10217 vga_set_legacy_decoding(dev
->pdev
, VGA_RSRC_LEGACY_IO
|
10218 VGA_RSRC_LEGACY_MEM
|
10219 VGA_RSRC_NORMAL_IO
|
10220 VGA_RSRC_NORMAL_MEM
);
10221 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
10225 void intel_modeset_init_hw(struct drm_device
*dev
)
10227 intel_init_power_well(dev
);
10229 intel_prepare_ddi(dev
);
10231 intel_init_clock_gating(dev
);
10233 mutex_lock(&dev
->struct_mutex
);
10234 intel_enable_gt_powersave(dev
);
10235 mutex_unlock(&dev
->struct_mutex
);
10238 void intel_modeset_suspend_hw(struct drm_device
*dev
)
10240 intel_suspend_hw(dev
);
10243 void intel_modeset_init(struct drm_device
*dev
)
10245 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10248 drm_mode_config_init(dev
);
10250 dev
->mode_config
.min_width
= 0;
10251 dev
->mode_config
.min_height
= 0;
10253 dev
->mode_config
.preferred_depth
= 24;
10254 dev
->mode_config
.prefer_shadow
= 1;
10256 dev
->mode_config
.funcs
= &intel_mode_funcs
;
10258 intel_init_quirks(dev
);
10260 intel_init_pm(dev
);
10262 if (INTEL_INFO(dev
)->num_pipes
== 0)
10265 intel_init_display(dev
);
10267 if (IS_GEN2(dev
)) {
10268 dev
->mode_config
.max_width
= 2048;
10269 dev
->mode_config
.max_height
= 2048;
10270 } else if (IS_GEN3(dev
)) {
10271 dev
->mode_config
.max_width
= 4096;
10272 dev
->mode_config
.max_height
= 4096;
10274 dev
->mode_config
.max_width
= 8192;
10275 dev
->mode_config
.max_height
= 8192;
10277 dev
->mode_config
.fb_base
= dev_priv
->gtt
.mappable_base
;
10279 DRM_DEBUG_KMS("%d display pipe%s available.\n",
10280 INTEL_INFO(dev
)->num_pipes
,
10281 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
10284 intel_crtc_init(dev
, i
);
10285 for (j
= 0; j
< dev_priv
->num_plane
; j
++) {
10286 ret
= intel_plane_init(dev
, i
, j
);
10288 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10289 pipe_name(i
), sprite_name(i
, j
), ret
);
10293 intel_cpu_pll_init(dev
);
10294 intel_shared_dpll_init(dev
);
10296 /* Just disable it once at startup */
10297 i915_disable_vga(dev
);
10298 intel_setup_outputs(dev
);
10300 /* Just in case the BIOS is doing something questionable. */
10301 intel_disable_fbc(dev
);
10305 intel_connector_break_all_links(struct intel_connector
*connector
)
10307 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
10308 connector
->base
.encoder
= NULL
;
10309 connector
->encoder
->connectors_active
= false;
10310 connector
->encoder
->base
.crtc
= NULL
;
10313 static void intel_enable_pipe_a(struct drm_device
*dev
)
10315 struct intel_connector
*connector
;
10316 struct drm_connector
*crt
= NULL
;
10317 struct intel_load_detect_pipe load_detect_temp
;
10319 /* We can't just switch on the pipe A, we need to set things up with a
10320 * proper mode and output configuration. As a gross hack, enable pipe A
10321 * by enabling the load detect pipe once. */
10322 list_for_each_entry(connector
,
10323 &dev
->mode_config
.connector_list
,
10325 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
10326 crt
= &connector
->base
;
10334 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
))
10335 intel_release_load_detect_pipe(crt
, &load_detect_temp
);
10341 intel_check_plane_mapping(struct intel_crtc
*crtc
)
10343 struct drm_device
*dev
= crtc
->base
.dev
;
10344 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10347 if (INTEL_INFO(dev
)->num_pipes
== 1)
10350 reg
= DSPCNTR(!crtc
->plane
);
10351 val
= I915_READ(reg
);
10353 if ((val
& DISPLAY_PLANE_ENABLE
) &&
10354 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
10360 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
10362 struct drm_device
*dev
= crtc
->base
.dev
;
10363 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10366 /* Clear any frame start delays used for debugging left by the BIOS */
10367 reg
= PIPECONF(crtc
->config
.cpu_transcoder
);
10368 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
10370 /* We need to sanitize the plane -> pipe mapping first because this will
10371 * disable the crtc (and hence change the state) if it is wrong. Note
10372 * that gen4+ has a fixed plane -> pipe mapping. */
10373 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
10374 struct intel_connector
*connector
;
10377 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10378 crtc
->base
.base
.id
);
10380 /* Pipe has the wrong plane attached and the plane is active.
10381 * Temporarily change the plane mapping and disable everything
10383 plane
= crtc
->plane
;
10384 crtc
->plane
= !plane
;
10385 dev_priv
->display
.crtc_disable(&crtc
->base
);
10386 crtc
->plane
= plane
;
10388 /* ... and break all links. */
10389 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10391 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
10394 intel_connector_break_all_links(connector
);
10397 WARN_ON(crtc
->active
);
10398 crtc
->base
.enabled
= false;
10401 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
10402 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
10403 /* BIOS forgot to enable pipe A, this mostly happens after
10404 * resume. Force-enable the pipe to fix this, the update_dpms
10405 * call below we restore the pipe to the right state, but leave
10406 * the required bits on. */
10407 intel_enable_pipe_a(dev
);
10410 /* Adjust the state of the output pipe according to whether we
10411 * have active connectors/encoders. */
10412 intel_crtc_update_dpms(&crtc
->base
);
10414 if (crtc
->active
!= crtc
->base
.enabled
) {
10415 struct intel_encoder
*encoder
;
10417 /* This can happen either due to bugs in the get_hw_state
10418 * functions or because the pipe is force-enabled due to the
10420 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10421 crtc
->base
.base
.id
,
10422 crtc
->base
.enabled
? "enabled" : "disabled",
10423 crtc
->active
? "enabled" : "disabled");
10425 crtc
->base
.enabled
= crtc
->active
;
10427 /* Because we only establish the connector -> encoder ->
10428 * crtc links if something is active, this means the
10429 * crtc is now deactivated. Break the links. connector
10430 * -> encoder links are only establish when things are
10431 * actually up, hence no need to break them. */
10432 WARN_ON(crtc
->active
);
10434 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
10435 WARN_ON(encoder
->connectors_active
);
10436 encoder
->base
.crtc
= NULL
;
10441 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
10443 struct intel_connector
*connector
;
10444 struct drm_device
*dev
= encoder
->base
.dev
;
10446 /* We need to check both for a crtc link (meaning that the
10447 * encoder is active and trying to read from a pipe) and the
10448 * pipe itself being active. */
10449 bool has_active_crtc
= encoder
->base
.crtc
&&
10450 to_intel_crtc(encoder
->base
.crtc
)->active
;
10452 if (encoder
->connectors_active
&& !has_active_crtc
) {
10453 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10454 encoder
->base
.base
.id
,
10455 drm_get_encoder_name(&encoder
->base
));
10457 /* Connector is active, but has no active pipe. This is
10458 * fallout from our resume register restoring. Disable
10459 * the encoder manually again. */
10460 if (encoder
->base
.crtc
) {
10461 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10462 encoder
->base
.base
.id
,
10463 drm_get_encoder_name(&encoder
->base
));
10464 encoder
->disable(encoder
);
10467 /* Inconsistent output/port/pipe state happens presumably due to
10468 * a bug in one of the get_hw_state functions. Or someplace else
10469 * in our code, like the register restore mess on resume. Clamp
10470 * things to off as a safer default. */
10471 list_for_each_entry(connector
,
10472 &dev
->mode_config
.connector_list
,
10474 if (connector
->encoder
!= encoder
)
10477 intel_connector_break_all_links(connector
);
10480 /* Enabled encoders without active connectors will be fixed in
10481 * the crtc fixup. */
10484 void i915_redisable_vga(struct drm_device
*dev
)
10486 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10487 u32 vga_reg
= i915_vgacntrl_reg(dev
);
10489 /* This function can be called both from intel_modeset_setup_hw_state or
10490 * at a very early point in our resume sequence, where the power well
10491 * structures are not yet restored. Since this function is at a very
10492 * paranoid "someone might have enabled VGA while we were not looking"
10493 * level, just check if the power well is enabled instead of trying to
10494 * follow the "don't touch the power well if we don't need it" policy
10495 * the rest of the driver uses. */
10496 if (HAS_POWER_WELL(dev
) &&
10497 (I915_READ(HSW_PWR_WELL_DRIVER
) & HSW_PWR_WELL_STATE_ENABLED
) == 0)
10500 if (I915_READ(vga_reg
) != VGA_DISP_DISABLE
) {
10501 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
10502 i915_disable_vga(dev
);
10506 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
10508 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10510 struct intel_crtc
*crtc
;
10511 struct intel_encoder
*encoder
;
10512 struct intel_connector
*connector
;
10515 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
10517 memset(&crtc
->config
, 0, sizeof(crtc
->config
));
10519 crtc
->active
= dev_priv
->display
.get_pipe_config(crtc
,
10522 crtc
->base
.enabled
= crtc
->active
;
10524 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10525 crtc
->base
.base
.id
,
10526 crtc
->active
? "enabled" : "disabled");
10529 /* FIXME: Smash this into the new shared dpll infrastructure. */
10531 intel_ddi_setup_hw_pll_state(dev
);
10533 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
10534 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
10536 pll
->on
= pll
->get_hw_state(dev_priv
, pll
, &pll
->hw_state
);
10538 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
10540 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
10543 pll
->refcount
= pll
->active
;
10545 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10546 pll
->name
, pll
->refcount
, pll
->on
);
10549 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
10553 if (encoder
->get_hw_state(encoder
, &pipe
)) {
10554 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
10555 encoder
->base
.crtc
= &crtc
->base
;
10556 if (encoder
->get_config
)
10557 encoder
->get_config(encoder
, &crtc
->config
);
10559 encoder
->base
.crtc
= NULL
;
10562 encoder
->connectors_active
= false;
10563 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10564 encoder
->base
.base
.id
,
10565 drm_get_encoder_name(&encoder
->base
),
10566 encoder
->base
.crtc
? "enabled" : "disabled",
10570 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10572 if (connector
->get_hw_state(connector
)) {
10573 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
10574 connector
->encoder
->connectors_active
= true;
10575 connector
->base
.encoder
= &connector
->encoder
->base
;
10577 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
10578 connector
->base
.encoder
= NULL
;
10580 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10581 connector
->base
.base
.id
,
10582 drm_get_connector_name(&connector
->base
),
10583 connector
->base
.encoder
? "enabled" : "disabled");
10587 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10588 * and i915 state tracking structures. */
10589 void intel_modeset_setup_hw_state(struct drm_device
*dev
,
10590 bool force_restore
)
10592 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10594 struct drm_plane
*plane
;
10595 struct intel_crtc
*crtc
;
10596 struct intel_encoder
*encoder
;
10599 intel_modeset_readout_hw_state(dev
);
10602 * Now that we have the config, copy it to each CRTC struct
10603 * Note that this could go away if we move to using crtc_config
10604 * checking everywhere.
10606 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
10608 if (crtc
->active
&& i915_fastboot
) {
10609 intel_crtc_mode_from_pipe_config(crtc
, &crtc
->config
);
10611 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10612 crtc
->base
.base
.id
);
10613 drm_mode_debug_printmodeline(&crtc
->base
.mode
);
10617 /* HW state is read out, now we need to sanitize this mess. */
10618 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
10620 intel_sanitize_encoder(encoder
);
10623 for_each_pipe(pipe
) {
10624 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
10625 intel_sanitize_crtc(crtc
);
10626 intel_dump_pipe_config(crtc
, &crtc
->config
, "[setup_hw_state]");
10629 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
10630 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
10632 if (!pll
->on
|| pll
->active
)
10635 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll
->name
);
10637 pll
->disable(dev_priv
, pll
);
10641 if (force_restore
) {
10643 * We need to use raw interfaces for restoring state to avoid
10644 * checking (bogus) intermediate states.
10646 for_each_pipe(pipe
) {
10647 struct drm_crtc
*crtc
=
10648 dev_priv
->pipe_to_crtc_mapping
[pipe
];
10650 __intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
,
10653 list_for_each_entry(plane
, &dev
->mode_config
.plane_list
, head
)
10654 intel_plane_restore(plane
);
10656 i915_redisable_vga(dev
);
10658 intel_modeset_update_staged_output_state(dev
);
10661 intel_modeset_check_state(dev
);
10663 drm_mode_config_reset(dev
);
10666 void intel_modeset_gem_init(struct drm_device
*dev
)
10668 intel_modeset_init_hw(dev
);
10670 intel_setup_overlay(dev
);
10672 intel_modeset_setup_hw_state(dev
, false);
10675 void intel_modeset_cleanup(struct drm_device
*dev
)
10677 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10678 struct drm_crtc
*crtc
;
10681 * Interrupts and polling as the first thing to avoid creating havoc.
10682 * Too much stuff here (turning of rps, connectors, ...) would
10683 * experience fancy races otherwise.
10685 drm_irq_uninstall(dev
);
10686 cancel_work_sync(&dev_priv
->hotplug_work
);
10688 * Due to the hpd irq storm handling the hotplug work can re-arm the
10689 * poll handlers. Hence disable polling after hpd handling is shut down.
10691 drm_kms_helper_poll_fini(dev
);
10693 mutex_lock(&dev
->struct_mutex
);
10695 intel_unregister_dsm_handler();
10697 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
10698 /* Skip inactive CRTCs */
10702 intel_increase_pllclock(crtc
);
10705 intel_disable_fbc(dev
);
10707 i915_enable_vga(dev
);
10709 intel_disable_gt_powersave(dev
);
10711 ironlake_teardown_rc6(dev
);
10713 mutex_unlock(&dev
->struct_mutex
);
10715 /* flush any delayed tasks or pending work */
10716 flush_scheduled_work();
10718 /* destroy backlight, if any, before the connectors */
10719 intel_panel_destroy_backlight(dev
);
10721 drm_mode_config_cleanup(dev
);
10723 intel_cleanup_overlay(dev
);
10727 * Return which encoder is currently attached for connector.
10729 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
10731 return &intel_attached_encoder(connector
)->base
;
10734 void intel_connector_attach_encoder(struct intel_connector
*connector
,
10735 struct intel_encoder
*encoder
)
10737 connector
->encoder
= encoder
;
10738 drm_mode_connector_attach_encoder(&connector
->base
,
10743 * set vga decode state - true == enable VGA decode
10745 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
10747 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10750 pci_read_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, &gmch_ctrl
);
10752 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
10754 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
10755 pci_write_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, gmch_ctrl
);
10759 struct intel_display_error_state
{
10761 u32 power_well_driver
;
10763 int num_transcoders
;
10765 struct intel_cursor_error_state
{
10770 } cursor
[I915_MAX_PIPES
];
10772 struct intel_pipe_error_state
{
10774 } pipe
[I915_MAX_PIPES
];
10776 struct intel_plane_error_state
{
10784 } plane
[I915_MAX_PIPES
];
10786 struct intel_transcoder_error_state
{
10787 enum transcoder cpu_transcoder
;
10800 struct intel_display_error_state
*
10801 intel_display_capture_error_state(struct drm_device
*dev
)
10803 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
10804 struct intel_display_error_state
*error
;
10805 int transcoders
[] = {
10813 if (INTEL_INFO(dev
)->num_pipes
== 0)
10816 error
= kmalloc(sizeof(*error
), GFP_ATOMIC
);
10820 if (HAS_POWER_WELL(dev
))
10821 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_DRIVER
);
10824 if (INTEL_INFO(dev
)->gen
<= 6 || IS_VALLEYVIEW(dev
)) {
10825 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
10826 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
10827 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
10829 error
->cursor
[i
].control
= I915_READ(CURCNTR_IVB(i
));
10830 error
->cursor
[i
].position
= I915_READ(CURPOS_IVB(i
));
10831 error
->cursor
[i
].base
= I915_READ(CURBASE_IVB(i
));
10834 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
10835 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
10836 if (INTEL_INFO(dev
)->gen
<= 3) {
10837 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
10838 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
10840 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
10841 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
10842 if (INTEL_INFO(dev
)->gen
>= 4) {
10843 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
10844 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
10847 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
10850 error
->num_transcoders
= INTEL_INFO(dev
)->num_pipes
;
10851 if (HAS_DDI(dev_priv
->dev
))
10852 error
->num_transcoders
++; /* Account for eDP. */
10854 for (i
= 0; i
< error
->num_transcoders
; i
++) {
10855 enum transcoder cpu_transcoder
= transcoders
[i
];
10857 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
10859 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
10860 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
10861 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
10862 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
10863 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
10864 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
10865 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
10868 /* In the code above we read the registers without checking if the power
10869 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10870 * prevent the next I915_WRITE from detecting it and printing an error
10872 intel_uncore_clear_errors(dev
);
10877 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10880 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
10881 struct drm_device
*dev
,
10882 struct intel_display_error_state
*error
)
10889 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
10890 if (HAS_POWER_WELL(dev
))
10891 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
10892 error
->power_well_driver
);
10894 err_printf(m
, "Pipe [%d]:\n", i
);
10895 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
10897 err_printf(m
, "Plane [%d]:\n", i
);
10898 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
10899 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
10900 if (INTEL_INFO(dev
)->gen
<= 3) {
10901 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
10902 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
10904 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
10905 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
10906 if (INTEL_INFO(dev
)->gen
>= 4) {
10907 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
10908 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
10911 err_printf(m
, "Cursor [%d]:\n", i
);
10912 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
10913 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
10914 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
10917 for (i
= 0; i
< error
->num_transcoders
; i
++) {
10918 err_printf(m
, " CPU transcoder: %c\n",
10919 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
10920 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
10921 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
10922 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
10923 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
10924 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
10925 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
10926 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);