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drm/i915: Make plane fb tracking work correctly, v2.
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
47
48 /* Primary plane formats for gen <= 3 */
49 static const uint32_t i8xx_primary_formats[] = {
50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
52 DRM_FORMAT_XRGB1555,
53 DRM_FORMAT_XRGB8888,
54 };
55
56 /* Primary plane formats for gen >= 4 */
57 static const uint32_t i965_primary_formats[] = {
58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64 };
65
66 static const uint32_t skl_primary_formats[] = {
67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
70 DRM_FORMAT_XBGR8888,
71 DRM_FORMAT_ARGB8888,
72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
74 DRM_FORMAT_XBGR2101010,
75 DRM_FORMAT_YUYV,
76 DRM_FORMAT_YVYU,
77 DRM_FORMAT_UYVY,
78 DRM_FORMAT_VYUY,
79 };
80
81 /* Cursor formats */
82 static const uint32_t intel_cursor_formats[] = {
83 DRM_FORMAT_ARGB8888,
84 };
85
86 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
87
88 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
89 struct intel_crtc_state *pipe_config);
90 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
91 struct intel_crtc_state *pipe_config);
92
93 static int intel_framebuffer_init(struct drm_device *dev,
94 struct intel_framebuffer *ifb,
95 struct drm_mode_fb_cmd2 *mode_cmd,
96 struct drm_i915_gem_object *obj);
97 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
98 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
99 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
100 struct intel_link_m_n *m_n,
101 struct intel_link_m_n *m2_n2);
102 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
103 static void haswell_set_pipeconf(struct drm_crtc *crtc);
104 static void intel_set_pipe_csc(struct drm_crtc *crtc);
105 static void vlv_prepare_pll(struct intel_crtc *crtc,
106 const struct intel_crtc_state *pipe_config);
107 static void chv_prepare_pll(struct intel_crtc *crtc,
108 const struct intel_crtc_state *pipe_config);
109 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
110 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
111 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
112 struct intel_crtc_state *crtc_state);
113 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
114 int num_connectors);
115 static void skylake_pfit_enable(struct intel_crtc *crtc);
116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
118 static void intel_modeset_setup_hw_state(struct drm_device *dev);
119
120 typedef struct {
121 int min, max;
122 } intel_range_t;
123
124 typedef struct {
125 int dot_limit;
126 int p2_slow, p2_fast;
127 } intel_p2_t;
128
129 typedef struct intel_limit intel_limit_t;
130 struct intel_limit {
131 intel_range_t dot, vco, n, m, m1, m2, p, p1;
132 intel_p2_t p2;
133 };
134
135 /* returns HPLL frequency in kHz */
136 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
137 {
138 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
139
140 /* Obtain SKU information */
141 mutex_lock(&dev_priv->sb_lock);
142 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
143 CCK_FUSE_HPLL_FREQ_MASK;
144 mutex_unlock(&dev_priv->sb_lock);
145
146 return vco_freq[hpll_freq] * 1000;
147 }
148
149 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
150 const char *name, u32 reg)
151 {
152 u32 val;
153 int divider;
154
155 if (dev_priv->hpll_freq == 0)
156 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
157
158 mutex_lock(&dev_priv->sb_lock);
159 val = vlv_cck_read(dev_priv, reg);
160 mutex_unlock(&dev_priv->sb_lock);
161
162 divider = val & CCK_FREQUENCY_VALUES;
163
164 WARN((val & CCK_FREQUENCY_STATUS) !=
165 (divider << CCK_FREQUENCY_STATUS_SHIFT),
166 "%s change in progress\n", name);
167
168 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
169 }
170
171 int
172 intel_pch_rawclk(struct drm_device *dev)
173 {
174 struct drm_i915_private *dev_priv = dev->dev_private;
175
176 WARN_ON(!HAS_PCH_SPLIT(dev));
177
178 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
179 }
180
181 /* hrawclock is 1/4 the FSB frequency */
182 int intel_hrawclk(struct drm_device *dev)
183 {
184 struct drm_i915_private *dev_priv = dev->dev_private;
185 uint32_t clkcfg;
186
187 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
188 if (IS_VALLEYVIEW(dev))
189 return 200;
190
191 clkcfg = I915_READ(CLKCFG);
192 switch (clkcfg & CLKCFG_FSB_MASK) {
193 case CLKCFG_FSB_400:
194 return 100;
195 case CLKCFG_FSB_533:
196 return 133;
197 case CLKCFG_FSB_667:
198 return 166;
199 case CLKCFG_FSB_800:
200 return 200;
201 case CLKCFG_FSB_1067:
202 return 266;
203 case CLKCFG_FSB_1333:
204 return 333;
205 /* these two are just a guess; one of them might be right */
206 case CLKCFG_FSB_1600:
207 case CLKCFG_FSB_1600_ALT:
208 return 400;
209 default:
210 return 133;
211 }
212 }
213
214 static void intel_update_czclk(struct drm_i915_private *dev_priv)
215 {
216 if (!IS_VALLEYVIEW(dev_priv))
217 return;
218
219 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
220 CCK_CZ_CLOCK_CONTROL);
221
222 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
223 }
224
225 static inline u32 /* units of 100MHz */
226 intel_fdi_link_freq(struct drm_device *dev)
227 {
228 if (IS_GEN5(dev)) {
229 struct drm_i915_private *dev_priv = dev->dev_private;
230 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
231 } else
232 return 27;
233 }
234
235 static const intel_limit_t intel_limits_i8xx_dac = {
236 .dot = { .min = 25000, .max = 350000 },
237 .vco = { .min = 908000, .max = 1512000 },
238 .n = { .min = 2, .max = 16 },
239 .m = { .min = 96, .max = 140 },
240 .m1 = { .min = 18, .max = 26 },
241 .m2 = { .min = 6, .max = 16 },
242 .p = { .min = 4, .max = 128 },
243 .p1 = { .min = 2, .max = 33 },
244 .p2 = { .dot_limit = 165000,
245 .p2_slow = 4, .p2_fast = 2 },
246 };
247
248 static const intel_limit_t intel_limits_i8xx_dvo = {
249 .dot = { .min = 25000, .max = 350000 },
250 .vco = { .min = 908000, .max = 1512000 },
251 .n = { .min = 2, .max = 16 },
252 .m = { .min = 96, .max = 140 },
253 .m1 = { .min = 18, .max = 26 },
254 .m2 = { .min = 6, .max = 16 },
255 .p = { .min = 4, .max = 128 },
256 .p1 = { .min = 2, .max = 33 },
257 .p2 = { .dot_limit = 165000,
258 .p2_slow = 4, .p2_fast = 4 },
259 };
260
261 static const intel_limit_t intel_limits_i8xx_lvds = {
262 .dot = { .min = 25000, .max = 350000 },
263 .vco = { .min = 908000, .max = 1512000 },
264 .n = { .min = 2, .max = 16 },
265 .m = { .min = 96, .max = 140 },
266 .m1 = { .min = 18, .max = 26 },
267 .m2 = { .min = 6, .max = 16 },
268 .p = { .min = 4, .max = 128 },
269 .p1 = { .min = 1, .max = 6 },
270 .p2 = { .dot_limit = 165000,
271 .p2_slow = 14, .p2_fast = 7 },
272 };
273
274 static const intel_limit_t intel_limits_i9xx_sdvo = {
275 .dot = { .min = 20000, .max = 400000 },
276 .vco = { .min = 1400000, .max = 2800000 },
277 .n = { .min = 1, .max = 6 },
278 .m = { .min = 70, .max = 120 },
279 .m1 = { .min = 8, .max = 18 },
280 .m2 = { .min = 3, .max = 7 },
281 .p = { .min = 5, .max = 80 },
282 .p1 = { .min = 1, .max = 8 },
283 .p2 = { .dot_limit = 200000,
284 .p2_slow = 10, .p2_fast = 5 },
285 };
286
287 static const intel_limit_t intel_limits_i9xx_lvds = {
288 .dot = { .min = 20000, .max = 400000 },
289 .vco = { .min = 1400000, .max = 2800000 },
290 .n = { .min = 1, .max = 6 },
291 .m = { .min = 70, .max = 120 },
292 .m1 = { .min = 8, .max = 18 },
293 .m2 = { .min = 3, .max = 7 },
294 .p = { .min = 7, .max = 98 },
295 .p1 = { .min = 1, .max = 8 },
296 .p2 = { .dot_limit = 112000,
297 .p2_slow = 14, .p2_fast = 7 },
298 };
299
300
301 static const intel_limit_t intel_limits_g4x_sdvo = {
302 .dot = { .min = 25000, .max = 270000 },
303 .vco = { .min = 1750000, .max = 3500000},
304 .n = { .min = 1, .max = 4 },
305 .m = { .min = 104, .max = 138 },
306 .m1 = { .min = 17, .max = 23 },
307 .m2 = { .min = 5, .max = 11 },
308 .p = { .min = 10, .max = 30 },
309 .p1 = { .min = 1, .max = 3},
310 .p2 = { .dot_limit = 270000,
311 .p2_slow = 10,
312 .p2_fast = 10
313 },
314 };
315
316 static const intel_limit_t intel_limits_g4x_hdmi = {
317 .dot = { .min = 22000, .max = 400000 },
318 .vco = { .min = 1750000, .max = 3500000},
319 .n = { .min = 1, .max = 4 },
320 .m = { .min = 104, .max = 138 },
321 .m1 = { .min = 16, .max = 23 },
322 .m2 = { .min = 5, .max = 11 },
323 .p = { .min = 5, .max = 80 },
324 .p1 = { .min = 1, .max = 8},
325 .p2 = { .dot_limit = 165000,
326 .p2_slow = 10, .p2_fast = 5 },
327 };
328
329 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
330 .dot = { .min = 20000, .max = 115000 },
331 .vco = { .min = 1750000, .max = 3500000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 104, .max = 138 },
334 .m1 = { .min = 17, .max = 23 },
335 .m2 = { .min = 5, .max = 11 },
336 .p = { .min = 28, .max = 112 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 0,
339 .p2_slow = 14, .p2_fast = 14
340 },
341 };
342
343 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
344 .dot = { .min = 80000, .max = 224000 },
345 .vco = { .min = 1750000, .max = 3500000 },
346 .n = { .min = 1, .max = 3 },
347 .m = { .min = 104, .max = 138 },
348 .m1 = { .min = 17, .max = 23 },
349 .m2 = { .min = 5, .max = 11 },
350 .p = { .min = 14, .max = 42 },
351 .p1 = { .min = 2, .max = 6 },
352 .p2 = { .dot_limit = 0,
353 .p2_slow = 7, .p2_fast = 7
354 },
355 };
356
357 static const intel_limit_t intel_limits_pineview_sdvo = {
358 .dot = { .min = 20000, .max = 400000},
359 .vco = { .min = 1700000, .max = 3500000 },
360 /* Pineview's Ncounter is a ring counter */
361 .n = { .min = 3, .max = 6 },
362 .m = { .min = 2, .max = 256 },
363 /* Pineview only has one combined m divider, which we treat as m2. */
364 .m1 = { .min = 0, .max = 0 },
365 .m2 = { .min = 0, .max = 254 },
366 .p = { .min = 5, .max = 80 },
367 .p1 = { .min = 1, .max = 8 },
368 .p2 = { .dot_limit = 200000,
369 .p2_slow = 10, .p2_fast = 5 },
370 };
371
372 static const intel_limit_t intel_limits_pineview_lvds = {
373 .dot = { .min = 20000, .max = 400000 },
374 .vco = { .min = 1700000, .max = 3500000 },
375 .n = { .min = 3, .max = 6 },
376 .m = { .min = 2, .max = 256 },
377 .m1 = { .min = 0, .max = 0 },
378 .m2 = { .min = 0, .max = 254 },
379 .p = { .min = 7, .max = 112 },
380 .p1 = { .min = 1, .max = 8 },
381 .p2 = { .dot_limit = 112000,
382 .p2_slow = 14, .p2_fast = 14 },
383 };
384
385 /* Ironlake / Sandybridge
386 *
387 * We calculate clock using (register_value + 2) for N/M1/M2, so here
388 * the range value for them is (actual_value - 2).
389 */
390 static const intel_limit_t intel_limits_ironlake_dac = {
391 .dot = { .min = 25000, .max = 350000 },
392 .vco = { .min = 1760000, .max = 3510000 },
393 .n = { .min = 1, .max = 5 },
394 .m = { .min = 79, .max = 127 },
395 .m1 = { .min = 12, .max = 22 },
396 .m2 = { .min = 5, .max = 9 },
397 .p = { .min = 5, .max = 80 },
398 .p1 = { .min = 1, .max = 8 },
399 .p2 = { .dot_limit = 225000,
400 .p2_slow = 10, .p2_fast = 5 },
401 };
402
403 static const intel_limit_t intel_limits_ironlake_single_lvds = {
404 .dot = { .min = 25000, .max = 350000 },
405 .vco = { .min = 1760000, .max = 3510000 },
406 .n = { .min = 1, .max = 3 },
407 .m = { .min = 79, .max = 118 },
408 .m1 = { .min = 12, .max = 22 },
409 .m2 = { .min = 5, .max = 9 },
410 .p = { .min = 28, .max = 112 },
411 .p1 = { .min = 2, .max = 8 },
412 .p2 = { .dot_limit = 225000,
413 .p2_slow = 14, .p2_fast = 14 },
414 };
415
416 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
417 .dot = { .min = 25000, .max = 350000 },
418 .vco = { .min = 1760000, .max = 3510000 },
419 .n = { .min = 1, .max = 3 },
420 .m = { .min = 79, .max = 127 },
421 .m1 = { .min = 12, .max = 22 },
422 .m2 = { .min = 5, .max = 9 },
423 .p = { .min = 14, .max = 56 },
424 .p1 = { .min = 2, .max = 8 },
425 .p2 = { .dot_limit = 225000,
426 .p2_slow = 7, .p2_fast = 7 },
427 };
428
429 /* LVDS 100mhz refclk limits. */
430 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
431 .dot = { .min = 25000, .max = 350000 },
432 .vco = { .min = 1760000, .max = 3510000 },
433 .n = { .min = 1, .max = 2 },
434 .m = { .min = 79, .max = 126 },
435 .m1 = { .min = 12, .max = 22 },
436 .m2 = { .min = 5, .max = 9 },
437 .p = { .min = 28, .max = 112 },
438 .p1 = { .min = 2, .max = 8 },
439 .p2 = { .dot_limit = 225000,
440 .p2_slow = 14, .p2_fast = 14 },
441 };
442
443 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
444 .dot = { .min = 25000, .max = 350000 },
445 .vco = { .min = 1760000, .max = 3510000 },
446 .n = { .min = 1, .max = 3 },
447 .m = { .min = 79, .max = 126 },
448 .m1 = { .min = 12, .max = 22 },
449 .m2 = { .min = 5, .max = 9 },
450 .p = { .min = 14, .max = 42 },
451 .p1 = { .min = 2, .max = 6 },
452 .p2 = { .dot_limit = 225000,
453 .p2_slow = 7, .p2_fast = 7 },
454 };
455
456 static const intel_limit_t intel_limits_vlv = {
457 /*
458 * These are the data rate limits (measured in fast clocks)
459 * since those are the strictest limits we have. The fast
460 * clock and actual rate limits are more relaxed, so checking
461 * them would make no difference.
462 */
463 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
464 .vco = { .min = 4000000, .max = 6000000 },
465 .n = { .min = 1, .max = 7 },
466 .m1 = { .min = 2, .max = 3 },
467 .m2 = { .min = 11, .max = 156 },
468 .p1 = { .min = 2, .max = 3 },
469 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
470 };
471
472 static const intel_limit_t intel_limits_chv = {
473 /*
474 * These are the data rate limits (measured in fast clocks)
475 * since those are the strictest limits we have. The fast
476 * clock and actual rate limits are more relaxed, so checking
477 * them would make no difference.
478 */
479 .dot = { .min = 25000 * 5, .max = 540000 * 5},
480 .vco = { .min = 4800000, .max = 6480000 },
481 .n = { .min = 1, .max = 1 },
482 .m1 = { .min = 2, .max = 2 },
483 .m2 = { .min = 24 << 22, .max = 175 << 22 },
484 .p1 = { .min = 2, .max = 4 },
485 .p2 = { .p2_slow = 1, .p2_fast = 14 },
486 };
487
488 static const intel_limit_t intel_limits_bxt = {
489 /* FIXME: find real dot limits */
490 .dot = { .min = 0, .max = INT_MAX },
491 .vco = { .min = 4800000, .max = 6700000 },
492 .n = { .min = 1, .max = 1 },
493 .m1 = { .min = 2, .max = 2 },
494 /* FIXME: find real m2 limits */
495 .m2 = { .min = 2 << 22, .max = 255 << 22 },
496 .p1 = { .min = 2, .max = 4 },
497 .p2 = { .p2_slow = 1, .p2_fast = 20 },
498 };
499
500 static bool
501 needs_modeset(struct drm_crtc_state *state)
502 {
503 return drm_atomic_crtc_needs_modeset(state);
504 }
505
506 /**
507 * Returns whether any output on the specified pipe is of the specified type
508 */
509 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
510 {
511 struct drm_device *dev = crtc->base.dev;
512 struct intel_encoder *encoder;
513
514 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
515 if (encoder->type == type)
516 return true;
517
518 return false;
519 }
520
521 /**
522 * Returns whether any output on the specified pipe will have the specified
523 * type after a staged modeset is complete, i.e., the same as
524 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
525 * encoder->crtc.
526 */
527 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
528 int type)
529 {
530 struct drm_atomic_state *state = crtc_state->base.state;
531 struct drm_connector *connector;
532 struct drm_connector_state *connector_state;
533 struct intel_encoder *encoder;
534 int i, num_connectors = 0;
535
536 for_each_connector_in_state(state, connector, connector_state, i) {
537 if (connector_state->crtc != crtc_state->base.crtc)
538 continue;
539
540 num_connectors++;
541
542 encoder = to_intel_encoder(connector_state->best_encoder);
543 if (encoder->type == type)
544 return true;
545 }
546
547 WARN_ON(num_connectors == 0);
548
549 return false;
550 }
551
552 static const intel_limit_t *
553 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
554 {
555 struct drm_device *dev = crtc_state->base.crtc->dev;
556 const intel_limit_t *limit;
557
558 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
559 if (intel_is_dual_link_lvds(dev)) {
560 if (refclk == 100000)
561 limit = &intel_limits_ironlake_dual_lvds_100m;
562 else
563 limit = &intel_limits_ironlake_dual_lvds;
564 } else {
565 if (refclk == 100000)
566 limit = &intel_limits_ironlake_single_lvds_100m;
567 else
568 limit = &intel_limits_ironlake_single_lvds;
569 }
570 } else
571 limit = &intel_limits_ironlake_dac;
572
573 return limit;
574 }
575
576 static const intel_limit_t *
577 intel_g4x_limit(struct intel_crtc_state *crtc_state)
578 {
579 struct drm_device *dev = crtc_state->base.crtc->dev;
580 const intel_limit_t *limit;
581
582 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
583 if (intel_is_dual_link_lvds(dev))
584 limit = &intel_limits_g4x_dual_channel_lvds;
585 else
586 limit = &intel_limits_g4x_single_channel_lvds;
587 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
588 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
589 limit = &intel_limits_g4x_hdmi;
590 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
591 limit = &intel_limits_g4x_sdvo;
592 } else /* The option is for other outputs */
593 limit = &intel_limits_i9xx_sdvo;
594
595 return limit;
596 }
597
598 static const intel_limit_t *
599 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
600 {
601 struct drm_device *dev = crtc_state->base.crtc->dev;
602 const intel_limit_t *limit;
603
604 if (IS_BROXTON(dev))
605 limit = &intel_limits_bxt;
606 else if (HAS_PCH_SPLIT(dev))
607 limit = intel_ironlake_limit(crtc_state, refclk);
608 else if (IS_G4X(dev)) {
609 limit = intel_g4x_limit(crtc_state);
610 } else if (IS_PINEVIEW(dev)) {
611 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
612 limit = &intel_limits_pineview_lvds;
613 else
614 limit = &intel_limits_pineview_sdvo;
615 } else if (IS_CHERRYVIEW(dev)) {
616 limit = &intel_limits_chv;
617 } else if (IS_VALLEYVIEW(dev)) {
618 limit = &intel_limits_vlv;
619 } else if (!IS_GEN2(dev)) {
620 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
621 limit = &intel_limits_i9xx_lvds;
622 else
623 limit = &intel_limits_i9xx_sdvo;
624 } else {
625 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
626 limit = &intel_limits_i8xx_lvds;
627 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
628 limit = &intel_limits_i8xx_dvo;
629 else
630 limit = &intel_limits_i8xx_dac;
631 }
632 return limit;
633 }
634
635 /*
636 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
637 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
638 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
639 * The helpers' return value is the rate of the clock that is fed to the
640 * display engine's pipe which can be the above fast dot clock rate or a
641 * divided-down version of it.
642 */
643 /* m1 is reserved as 0 in Pineview, n is a ring counter */
644 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
645 {
646 clock->m = clock->m2 + 2;
647 clock->p = clock->p1 * clock->p2;
648 if (WARN_ON(clock->n == 0 || clock->p == 0))
649 return 0;
650 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
651 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
652
653 return clock->dot;
654 }
655
656 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
657 {
658 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
659 }
660
661 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
662 {
663 clock->m = i9xx_dpll_compute_m(clock);
664 clock->p = clock->p1 * clock->p2;
665 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
666 return 0;
667 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
668 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
669
670 return clock->dot;
671 }
672
673 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
674 {
675 clock->m = clock->m1 * clock->m2;
676 clock->p = clock->p1 * clock->p2;
677 if (WARN_ON(clock->n == 0 || clock->p == 0))
678 return 0;
679 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
680 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
681
682 return clock->dot / 5;
683 }
684
685 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
686 {
687 clock->m = clock->m1 * clock->m2;
688 clock->p = clock->p1 * clock->p2;
689 if (WARN_ON(clock->n == 0 || clock->p == 0))
690 return 0;
691 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
692 clock->n << 22);
693 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
694
695 return clock->dot / 5;
696 }
697
698 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
699 /**
700 * Returns whether the given set of divisors are valid for a given refclk with
701 * the given connectors.
702 */
703
704 static bool intel_PLL_is_valid(struct drm_device *dev,
705 const intel_limit_t *limit,
706 const intel_clock_t *clock)
707 {
708 if (clock->n < limit->n.min || limit->n.max < clock->n)
709 INTELPllInvalid("n out of range\n");
710 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
711 INTELPllInvalid("p1 out of range\n");
712 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
713 INTELPllInvalid("m2 out of range\n");
714 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
715 INTELPllInvalid("m1 out of range\n");
716
717 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
718 if (clock->m1 <= clock->m2)
719 INTELPllInvalid("m1 <= m2\n");
720
721 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
722 if (clock->p < limit->p.min || limit->p.max < clock->p)
723 INTELPllInvalid("p out of range\n");
724 if (clock->m < limit->m.min || limit->m.max < clock->m)
725 INTELPllInvalid("m out of range\n");
726 }
727
728 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
729 INTELPllInvalid("vco out of range\n");
730 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
731 * connector, etc., rather than just a single range.
732 */
733 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
734 INTELPllInvalid("dot out of range\n");
735
736 return true;
737 }
738
739 static int
740 i9xx_select_p2_div(const intel_limit_t *limit,
741 const struct intel_crtc_state *crtc_state,
742 int target)
743 {
744 struct drm_device *dev = crtc_state->base.crtc->dev;
745
746 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
747 /*
748 * For LVDS just rely on its current settings for dual-channel.
749 * We haven't figured out how to reliably set up different
750 * single/dual channel state, if we even can.
751 */
752 if (intel_is_dual_link_lvds(dev))
753 return limit->p2.p2_fast;
754 else
755 return limit->p2.p2_slow;
756 } else {
757 if (target < limit->p2.dot_limit)
758 return limit->p2.p2_slow;
759 else
760 return limit->p2.p2_fast;
761 }
762 }
763
764 static bool
765 i9xx_find_best_dpll(const intel_limit_t *limit,
766 struct intel_crtc_state *crtc_state,
767 int target, int refclk, intel_clock_t *match_clock,
768 intel_clock_t *best_clock)
769 {
770 struct drm_device *dev = crtc_state->base.crtc->dev;
771 intel_clock_t clock;
772 int err = target;
773
774 memset(best_clock, 0, sizeof(*best_clock));
775
776 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
777
778 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
779 clock.m1++) {
780 for (clock.m2 = limit->m2.min;
781 clock.m2 <= limit->m2.max; clock.m2++) {
782 if (clock.m2 >= clock.m1)
783 break;
784 for (clock.n = limit->n.min;
785 clock.n <= limit->n.max; clock.n++) {
786 for (clock.p1 = limit->p1.min;
787 clock.p1 <= limit->p1.max; clock.p1++) {
788 int this_err;
789
790 i9xx_calc_dpll_params(refclk, &clock);
791 if (!intel_PLL_is_valid(dev, limit,
792 &clock))
793 continue;
794 if (match_clock &&
795 clock.p != match_clock->p)
796 continue;
797
798 this_err = abs(clock.dot - target);
799 if (this_err < err) {
800 *best_clock = clock;
801 err = this_err;
802 }
803 }
804 }
805 }
806 }
807
808 return (err != target);
809 }
810
811 static bool
812 pnv_find_best_dpll(const intel_limit_t *limit,
813 struct intel_crtc_state *crtc_state,
814 int target, int refclk, intel_clock_t *match_clock,
815 intel_clock_t *best_clock)
816 {
817 struct drm_device *dev = crtc_state->base.crtc->dev;
818 intel_clock_t clock;
819 int err = target;
820
821 memset(best_clock, 0, sizeof(*best_clock));
822
823 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
824
825 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
826 clock.m1++) {
827 for (clock.m2 = limit->m2.min;
828 clock.m2 <= limit->m2.max; clock.m2++) {
829 for (clock.n = limit->n.min;
830 clock.n <= limit->n.max; clock.n++) {
831 for (clock.p1 = limit->p1.min;
832 clock.p1 <= limit->p1.max; clock.p1++) {
833 int this_err;
834
835 pnv_calc_dpll_params(refclk, &clock);
836 if (!intel_PLL_is_valid(dev, limit,
837 &clock))
838 continue;
839 if (match_clock &&
840 clock.p != match_clock->p)
841 continue;
842
843 this_err = abs(clock.dot - target);
844 if (this_err < err) {
845 *best_clock = clock;
846 err = this_err;
847 }
848 }
849 }
850 }
851 }
852
853 return (err != target);
854 }
855
856 static bool
857 g4x_find_best_dpll(const intel_limit_t *limit,
858 struct intel_crtc_state *crtc_state,
859 int target, int refclk, intel_clock_t *match_clock,
860 intel_clock_t *best_clock)
861 {
862 struct drm_device *dev = crtc_state->base.crtc->dev;
863 intel_clock_t clock;
864 int max_n;
865 bool found = false;
866 /* approximately equals target * 0.00585 */
867 int err_most = (target >> 8) + (target >> 9);
868
869 memset(best_clock, 0, sizeof(*best_clock));
870
871 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
872
873 max_n = limit->n.max;
874 /* based on hardware requirement, prefer smaller n to precision */
875 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
876 /* based on hardware requirement, prefere larger m1,m2 */
877 for (clock.m1 = limit->m1.max;
878 clock.m1 >= limit->m1.min; clock.m1--) {
879 for (clock.m2 = limit->m2.max;
880 clock.m2 >= limit->m2.min; clock.m2--) {
881 for (clock.p1 = limit->p1.max;
882 clock.p1 >= limit->p1.min; clock.p1--) {
883 int this_err;
884
885 i9xx_calc_dpll_params(refclk, &clock);
886 if (!intel_PLL_is_valid(dev, limit,
887 &clock))
888 continue;
889
890 this_err = abs(clock.dot - target);
891 if (this_err < err_most) {
892 *best_clock = clock;
893 err_most = this_err;
894 max_n = clock.n;
895 found = true;
896 }
897 }
898 }
899 }
900 }
901 return found;
902 }
903
904 /*
905 * Check if the calculated PLL configuration is more optimal compared to the
906 * best configuration and error found so far. Return the calculated error.
907 */
908 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
909 const intel_clock_t *calculated_clock,
910 const intel_clock_t *best_clock,
911 unsigned int best_error_ppm,
912 unsigned int *error_ppm)
913 {
914 /*
915 * For CHV ignore the error and consider only the P value.
916 * Prefer a bigger P value based on HW requirements.
917 */
918 if (IS_CHERRYVIEW(dev)) {
919 *error_ppm = 0;
920
921 return calculated_clock->p > best_clock->p;
922 }
923
924 if (WARN_ON_ONCE(!target_freq))
925 return false;
926
927 *error_ppm = div_u64(1000000ULL *
928 abs(target_freq - calculated_clock->dot),
929 target_freq);
930 /*
931 * Prefer a better P value over a better (smaller) error if the error
932 * is small. Ensure this preference for future configurations too by
933 * setting the error to 0.
934 */
935 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
936 *error_ppm = 0;
937
938 return true;
939 }
940
941 return *error_ppm + 10 < best_error_ppm;
942 }
943
944 static bool
945 vlv_find_best_dpll(const intel_limit_t *limit,
946 struct intel_crtc_state *crtc_state,
947 int target, int refclk, intel_clock_t *match_clock,
948 intel_clock_t *best_clock)
949 {
950 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
951 struct drm_device *dev = crtc->base.dev;
952 intel_clock_t clock;
953 unsigned int bestppm = 1000000;
954 /* min update 19.2 MHz */
955 int max_n = min(limit->n.max, refclk / 19200);
956 bool found = false;
957
958 target *= 5; /* fast clock */
959
960 memset(best_clock, 0, sizeof(*best_clock));
961
962 /* based on hardware requirement, prefer smaller n to precision */
963 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
964 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
965 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
966 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
967 clock.p = clock.p1 * clock.p2;
968 /* based on hardware requirement, prefer bigger m1,m2 values */
969 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
970 unsigned int ppm;
971
972 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
973 refclk * clock.m1);
974
975 vlv_calc_dpll_params(refclk, &clock);
976
977 if (!intel_PLL_is_valid(dev, limit,
978 &clock))
979 continue;
980
981 if (!vlv_PLL_is_optimal(dev, target,
982 &clock,
983 best_clock,
984 bestppm, &ppm))
985 continue;
986
987 *best_clock = clock;
988 bestppm = ppm;
989 found = true;
990 }
991 }
992 }
993 }
994
995 return found;
996 }
997
998 static bool
999 chv_find_best_dpll(const intel_limit_t *limit,
1000 struct intel_crtc_state *crtc_state,
1001 int target, int refclk, intel_clock_t *match_clock,
1002 intel_clock_t *best_clock)
1003 {
1004 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1005 struct drm_device *dev = crtc->base.dev;
1006 unsigned int best_error_ppm;
1007 intel_clock_t clock;
1008 uint64_t m2;
1009 int found = false;
1010
1011 memset(best_clock, 0, sizeof(*best_clock));
1012 best_error_ppm = 1000000;
1013
1014 /*
1015 * Based on hardware doc, the n always set to 1, and m1 always
1016 * set to 2. If requires to support 200Mhz refclk, we need to
1017 * revisit this because n may not 1 anymore.
1018 */
1019 clock.n = 1, clock.m1 = 2;
1020 target *= 5; /* fast clock */
1021
1022 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1023 for (clock.p2 = limit->p2.p2_fast;
1024 clock.p2 >= limit->p2.p2_slow;
1025 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1026 unsigned int error_ppm;
1027
1028 clock.p = clock.p1 * clock.p2;
1029
1030 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1031 clock.n) << 22, refclk * clock.m1);
1032
1033 if (m2 > INT_MAX/clock.m1)
1034 continue;
1035
1036 clock.m2 = m2;
1037
1038 chv_calc_dpll_params(refclk, &clock);
1039
1040 if (!intel_PLL_is_valid(dev, limit, &clock))
1041 continue;
1042
1043 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1044 best_error_ppm, &error_ppm))
1045 continue;
1046
1047 *best_clock = clock;
1048 best_error_ppm = error_ppm;
1049 found = true;
1050 }
1051 }
1052
1053 return found;
1054 }
1055
1056 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1057 intel_clock_t *best_clock)
1058 {
1059 int refclk = i9xx_get_refclk(crtc_state, 0);
1060
1061 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1062 target_clock, refclk, NULL, best_clock);
1063 }
1064
1065 bool intel_crtc_active(struct drm_crtc *crtc)
1066 {
1067 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1068
1069 /* Be paranoid as we can arrive here with only partial
1070 * state retrieved from the hardware during setup.
1071 *
1072 * We can ditch the adjusted_mode.crtc_clock check as soon
1073 * as Haswell has gained clock readout/fastboot support.
1074 *
1075 * We can ditch the crtc->primary->fb check as soon as we can
1076 * properly reconstruct framebuffers.
1077 *
1078 * FIXME: The intel_crtc->active here should be switched to
1079 * crtc->state->active once we have proper CRTC states wired up
1080 * for atomic.
1081 */
1082 return intel_crtc->active && crtc->primary->state->fb &&
1083 intel_crtc->config->base.adjusted_mode.crtc_clock;
1084 }
1085
1086 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1087 enum pipe pipe)
1088 {
1089 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1090 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1091
1092 return intel_crtc->config->cpu_transcoder;
1093 }
1094
1095 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1096 {
1097 struct drm_i915_private *dev_priv = dev->dev_private;
1098 u32 reg = PIPEDSL(pipe);
1099 u32 line1, line2;
1100 u32 line_mask;
1101
1102 if (IS_GEN2(dev))
1103 line_mask = DSL_LINEMASK_GEN2;
1104 else
1105 line_mask = DSL_LINEMASK_GEN3;
1106
1107 line1 = I915_READ(reg) & line_mask;
1108 msleep(5);
1109 line2 = I915_READ(reg) & line_mask;
1110
1111 return line1 == line2;
1112 }
1113
1114 /*
1115 * intel_wait_for_pipe_off - wait for pipe to turn off
1116 * @crtc: crtc whose pipe to wait for
1117 *
1118 * After disabling a pipe, we can't wait for vblank in the usual way,
1119 * spinning on the vblank interrupt status bit, since we won't actually
1120 * see an interrupt when the pipe is disabled.
1121 *
1122 * On Gen4 and above:
1123 * wait for the pipe register state bit to turn off
1124 *
1125 * Otherwise:
1126 * wait for the display line value to settle (it usually
1127 * ends up stopping at the start of the next frame).
1128 *
1129 */
1130 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1131 {
1132 struct drm_device *dev = crtc->base.dev;
1133 struct drm_i915_private *dev_priv = dev->dev_private;
1134 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1135 enum pipe pipe = crtc->pipe;
1136
1137 if (INTEL_INFO(dev)->gen >= 4) {
1138 int reg = PIPECONF(cpu_transcoder);
1139
1140 /* Wait for the Pipe State to go off */
1141 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1142 100))
1143 WARN(1, "pipe_off wait timed out\n");
1144 } else {
1145 /* Wait for the display line to settle */
1146 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1147 WARN(1, "pipe_off wait timed out\n");
1148 }
1149 }
1150
1151 static const char *state_string(bool enabled)
1152 {
1153 return enabled ? "on" : "off";
1154 }
1155
1156 /* Only for pre-ILK configs */
1157 void assert_pll(struct drm_i915_private *dev_priv,
1158 enum pipe pipe, bool state)
1159 {
1160 u32 val;
1161 bool cur_state;
1162
1163 val = I915_READ(DPLL(pipe));
1164 cur_state = !!(val & DPLL_VCO_ENABLE);
1165 I915_STATE_WARN(cur_state != state,
1166 "PLL state assertion failure (expected %s, current %s)\n",
1167 state_string(state), state_string(cur_state));
1168 }
1169
1170 /* XXX: the dsi pll is shared between MIPI DSI ports */
1171 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1172 {
1173 u32 val;
1174 bool cur_state;
1175
1176 mutex_lock(&dev_priv->sb_lock);
1177 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1178 mutex_unlock(&dev_priv->sb_lock);
1179
1180 cur_state = val & DSI_PLL_VCO_EN;
1181 I915_STATE_WARN(cur_state != state,
1182 "DSI PLL state assertion failure (expected %s, current %s)\n",
1183 state_string(state), state_string(cur_state));
1184 }
1185 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1186 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1187
1188 struct intel_shared_dpll *
1189 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1190 {
1191 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1192
1193 if (crtc->config->shared_dpll < 0)
1194 return NULL;
1195
1196 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1197 }
1198
1199 /* For ILK+ */
1200 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1201 struct intel_shared_dpll *pll,
1202 bool state)
1203 {
1204 bool cur_state;
1205 struct intel_dpll_hw_state hw_state;
1206
1207 if (WARN (!pll,
1208 "asserting DPLL %s with no DPLL\n", state_string(state)))
1209 return;
1210
1211 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1212 I915_STATE_WARN(cur_state != state,
1213 "%s assertion failure (expected %s, current %s)\n",
1214 pll->name, state_string(state), state_string(cur_state));
1215 }
1216
1217 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1218 enum pipe pipe, bool state)
1219 {
1220 bool cur_state;
1221 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1222 pipe);
1223
1224 if (HAS_DDI(dev_priv->dev)) {
1225 /* DDI does not have a specific FDI_TX register */
1226 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1227 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1228 } else {
1229 u32 val = I915_READ(FDI_TX_CTL(pipe));
1230 cur_state = !!(val & FDI_TX_ENABLE);
1231 }
1232 I915_STATE_WARN(cur_state != state,
1233 "FDI TX state assertion failure (expected %s, current %s)\n",
1234 state_string(state), state_string(cur_state));
1235 }
1236 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1237 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1238
1239 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1240 enum pipe pipe, bool state)
1241 {
1242 u32 val;
1243 bool cur_state;
1244
1245 val = I915_READ(FDI_RX_CTL(pipe));
1246 cur_state = !!(val & FDI_RX_ENABLE);
1247 I915_STATE_WARN(cur_state != state,
1248 "FDI RX state assertion failure (expected %s, current %s)\n",
1249 state_string(state), state_string(cur_state));
1250 }
1251 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1252 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1253
1254 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1255 enum pipe pipe)
1256 {
1257 u32 val;
1258
1259 /* ILK FDI PLL is always enabled */
1260 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1261 return;
1262
1263 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1264 if (HAS_DDI(dev_priv->dev))
1265 return;
1266
1267 val = I915_READ(FDI_TX_CTL(pipe));
1268 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1269 }
1270
1271 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1272 enum pipe pipe, bool state)
1273 {
1274 u32 val;
1275 bool cur_state;
1276
1277 val = I915_READ(FDI_RX_CTL(pipe));
1278 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1279 I915_STATE_WARN(cur_state != state,
1280 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1281 state_string(state), state_string(cur_state));
1282 }
1283
1284 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1285 enum pipe pipe)
1286 {
1287 struct drm_device *dev = dev_priv->dev;
1288 int pp_reg;
1289 u32 val;
1290 enum pipe panel_pipe = PIPE_A;
1291 bool locked = true;
1292
1293 if (WARN_ON(HAS_DDI(dev)))
1294 return;
1295
1296 if (HAS_PCH_SPLIT(dev)) {
1297 u32 port_sel;
1298
1299 pp_reg = PCH_PP_CONTROL;
1300 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1301
1302 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1303 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1304 panel_pipe = PIPE_B;
1305 /* XXX: else fix for eDP */
1306 } else if (IS_VALLEYVIEW(dev)) {
1307 /* presumably write lock depends on pipe, not port select */
1308 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1309 panel_pipe = pipe;
1310 } else {
1311 pp_reg = PP_CONTROL;
1312 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1313 panel_pipe = PIPE_B;
1314 }
1315
1316 val = I915_READ(pp_reg);
1317 if (!(val & PANEL_POWER_ON) ||
1318 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1319 locked = false;
1320
1321 I915_STATE_WARN(panel_pipe == pipe && locked,
1322 "panel assertion failure, pipe %c regs locked\n",
1323 pipe_name(pipe));
1324 }
1325
1326 static void assert_cursor(struct drm_i915_private *dev_priv,
1327 enum pipe pipe, bool state)
1328 {
1329 struct drm_device *dev = dev_priv->dev;
1330 bool cur_state;
1331
1332 if (IS_845G(dev) || IS_I865G(dev))
1333 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1334 else
1335 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1336
1337 I915_STATE_WARN(cur_state != state,
1338 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1339 pipe_name(pipe), state_string(state), state_string(cur_state));
1340 }
1341 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1342 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1343
1344 void assert_pipe(struct drm_i915_private *dev_priv,
1345 enum pipe pipe, bool state)
1346 {
1347 bool cur_state;
1348 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1349 pipe);
1350
1351 /* if we need the pipe quirk it must be always on */
1352 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1353 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1354 state = true;
1355
1356 if (!intel_display_power_is_enabled(dev_priv,
1357 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1358 cur_state = false;
1359 } else {
1360 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1361 cur_state = !!(val & PIPECONF_ENABLE);
1362 }
1363
1364 I915_STATE_WARN(cur_state != state,
1365 "pipe %c assertion failure (expected %s, current %s)\n",
1366 pipe_name(pipe), state_string(state), state_string(cur_state));
1367 }
1368
1369 static void assert_plane(struct drm_i915_private *dev_priv,
1370 enum plane plane, bool state)
1371 {
1372 u32 val;
1373 bool cur_state;
1374
1375 val = I915_READ(DSPCNTR(plane));
1376 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1377 I915_STATE_WARN(cur_state != state,
1378 "plane %c assertion failure (expected %s, current %s)\n",
1379 plane_name(plane), state_string(state), state_string(cur_state));
1380 }
1381
1382 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1383 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1384
1385 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1386 enum pipe pipe)
1387 {
1388 struct drm_device *dev = dev_priv->dev;
1389 int i;
1390
1391 /* Primary planes are fixed to pipes on gen4+ */
1392 if (INTEL_INFO(dev)->gen >= 4) {
1393 u32 val = I915_READ(DSPCNTR(pipe));
1394 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1395 "plane %c assertion failure, should be disabled but not\n",
1396 plane_name(pipe));
1397 return;
1398 }
1399
1400 /* Need to check both planes against the pipe */
1401 for_each_pipe(dev_priv, i) {
1402 u32 val = I915_READ(DSPCNTR(i));
1403 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1404 DISPPLANE_SEL_PIPE_SHIFT;
1405 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1406 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1407 plane_name(i), pipe_name(pipe));
1408 }
1409 }
1410
1411 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1412 enum pipe pipe)
1413 {
1414 struct drm_device *dev = dev_priv->dev;
1415 int sprite;
1416
1417 if (INTEL_INFO(dev)->gen >= 9) {
1418 for_each_sprite(dev_priv, pipe, sprite) {
1419 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1420 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1421 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1422 sprite, pipe_name(pipe));
1423 }
1424 } else if (IS_VALLEYVIEW(dev)) {
1425 for_each_sprite(dev_priv, pipe, sprite) {
1426 u32 val = I915_READ(SPCNTR(pipe, sprite));
1427 I915_STATE_WARN(val & SP_ENABLE,
1428 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1429 sprite_name(pipe, sprite), pipe_name(pipe));
1430 }
1431 } else if (INTEL_INFO(dev)->gen >= 7) {
1432 u32 val = I915_READ(SPRCTL(pipe));
1433 I915_STATE_WARN(val & SPRITE_ENABLE,
1434 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1435 plane_name(pipe), pipe_name(pipe));
1436 } else if (INTEL_INFO(dev)->gen >= 5) {
1437 u32 val = I915_READ(DVSCNTR(pipe));
1438 I915_STATE_WARN(val & DVS_ENABLE,
1439 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1440 plane_name(pipe), pipe_name(pipe));
1441 }
1442 }
1443
1444 static void assert_vblank_disabled(struct drm_crtc *crtc)
1445 {
1446 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1447 drm_crtc_vblank_put(crtc);
1448 }
1449
1450 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1451 {
1452 u32 val;
1453 bool enabled;
1454
1455 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1456
1457 val = I915_READ(PCH_DREF_CONTROL);
1458 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1459 DREF_SUPERSPREAD_SOURCE_MASK));
1460 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1461 }
1462
1463 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1464 enum pipe pipe)
1465 {
1466 u32 val;
1467 bool enabled;
1468
1469 val = I915_READ(PCH_TRANSCONF(pipe));
1470 enabled = !!(val & TRANS_ENABLE);
1471 I915_STATE_WARN(enabled,
1472 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1473 pipe_name(pipe));
1474 }
1475
1476 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1477 enum pipe pipe, u32 port_sel, u32 val)
1478 {
1479 if ((val & DP_PORT_EN) == 0)
1480 return false;
1481
1482 if (HAS_PCH_CPT(dev_priv->dev)) {
1483 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1484 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1485 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1486 return false;
1487 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1488 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1489 return false;
1490 } else {
1491 if ((val & DP_PIPE_MASK) != (pipe << 30))
1492 return false;
1493 }
1494 return true;
1495 }
1496
1497 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1498 enum pipe pipe, u32 val)
1499 {
1500 if ((val & SDVO_ENABLE) == 0)
1501 return false;
1502
1503 if (HAS_PCH_CPT(dev_priv->dev)) {
1504 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1505 return false;
1506 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1507 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1508 return false;
1509 } else {
1510 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1511 return false;
1512 }
1513 return true;
1514 }
1515
1516 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1517 enum pipe pipe, u32 val)
1518 {
1519 if ((val & LVDS_PORT_EN) == 0)
1520 return false;
1521
1522 if (HAS_PCH_CPT(dev_priv->dev)) {
1523 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1524 return false;
1525 } else {
1526 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1527 return false;
1528 }
1529 return true;
1530 }
1531
1532 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1533 enum pipe pipe, u32 val)
1534 {
1535 if ((val & ADPA_DAC_ENABLE) == 0)
1536 return false;
1537 if (HAS_PCH_CPT(dev_priv->dev)) {
1538 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1539 return false;
1540 } else {
1541 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1542 return false;
1543 }
1544 return true;
1545 }
1546
1547 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1548 enum pipe pipe, int reg, u32 port_sel)
1549 {
1550 u32 val = I915_READ(reg);
1551 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1552 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1553 reg, pipe_name(pipe));
1554
1555 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1556 && (val & DP_PIPEB_SELECT),
1557 "IBX PCH dp port still using transcoder B\n");
1558 }
1559
1560 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1561 enum pipe pipe, int reg)
1562 {
1563 u32 val = I915_READ(reg);
1564 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1565 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1566 reg, pipe_name(pipe));
1567
1568 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1569 && (val & SDVO_PIPE_B_SELECT),
1570 "IBX PCH hdmi port still using transcoder B\n");
1571 }
1572
1573 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1574 enum pipe pipe)
1575 {
1576 u32 val;
1577
1578 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1579 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1580 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1581
1582 val = I915_READ(PCH_ADPA);
1583 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1584 "PCH VGA enabled on transcoder %c, should be disabled\n",
1585 pipe_name(pipe));
1586
1587 val = I915_READ(PCH_LVDS);
1588 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1589 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1590 pipe_name(pipe));
1591
1592 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1593 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1594 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1595 }
1596
1597 static void vlv_enable_pll(struct intel_crtc *crtc,
1598 const struct intel_crtc_state *pipe_config)
1599 {
1600 struct drm_device *dev = crtc->base.dev;
1601 struct drm_i915_private *dev_priv = dev->dev_private;
1602 int reg = DPLL(crtc->pipe);
1603 u32 dpll = pipe_config->dpll_hw_state.dpll;
1604
1605 assert_pipe_disabled(dev_priv, crtc->pipe);
1606
1607 /* No really, not for ILK+ */
1608 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1609
1610 /* PLL is protected by panel, make sure we can write it */
1611 if (IS_MOBILE(dev_priv->dev))
1612 assert_panel_unlocked(dev_priv, crtc->pipe);
1613
1614 I915_WRITE(reg, dpll);
1615 POSTING_READ(reg);
1616 udelay(150);
1617
1618 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1619 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1620
1621 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1622 POSTING_READ(DPLL_MD(crtc->pipe));
1623
1624 /* We do this three times for luck */
1625 I915_WRITE(reg, dpll);
1626 POSTING_READ(reg);
1627 udelay(150); /* wait for warmup */
1628 I915_WRITE(reg, dpll);
1629 POSTING_READ(reg);
1630 udelay(150); /* wait for warmup */
1631 I915_WRITE(reg, dpll);
1632 POSTING_READ(reg);
1633 udelay(150); /* wait for warmup */
1634 }
1635
1636 static void chv_enable_pll(struct intel_crtc *crtc,
1637 const struct intel_crtc_state *pipe_config)
1638 {
1639 struct drm_device *dev = crtc->base.dev;
1640 struct drm_i915_private *dev_priv = dev->dev_private;
1641 int pipe = crtc->pipe;
1642 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1643 u32 tmp;
1644
1645 assert_pipe_disabled(dev_priv, crtc->pipe);
1646
1647 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1648
1649 mutex_lock(&dev_priv->sb_lock);
1650
1651 /* Enable back the 10bit clock to display controller */
1652 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1653 tmp |= DPIO_DCLKP_EN;
1654 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1655
1656 mutex_unlock(&dev_priv->sb_lock);
1657
1658 /*
1659 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1660 */
1661 udelay(1);
1662
1663 /* Enable PLL */
1664 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1665
1666 /* Check PLL is locked */
1667 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1668 DRM_ERROR("PLL %d failed to lock\n", pipe);
1669
1670 /* not sure when this should be written */
1671 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1672 POSTING_READ(DPLL_MD(pipe));
1673 }
1674
1675 static int intel_num_dvo_pipes(struct drm_device *dev)
1676 {
1677 struct intel_crtc *crtc;
1678 int count = 0;
1679
1680 for_each_intel_crtc(dev, crtc)
1681 count += crtc->base.state->active &&
1682 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1683
1684 return count;
1685 }
1686
1687 static void i9xx_enable_pll(struct intel_crtc *crtc)
1688 {
1689 struct drm_device *dev = crtc->base.dev;
1690 struct drm_i915_private *dev_priv = dev->dev_private;
1691 int reg = DPLL(crtc->pipe);
1692 u32 dpll = crtc->config->dpll_hw_state.dpll;
1693
1694 assert_pipe_disabled(dev_priv, crtc->pipe);
1695
1696 /* No really, not for ILK+ */
1697 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1698
1699 /* PLL is protected by panel, make sure we can write it */
1700 if (IS_MOBILE(dev) && !IS_I830(dev))
1701 assert_panel_unlocked(dev_priv, crtc->pipe);
1702
1703 /* Enable DVO 2x clock on both PLLs if necessary */
1704 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1705 /*
1706 * It appears to be important that we don't enable this
1707 * for the current pipe before otherwise configuring the
1708 * PLL. No idea how this should be handled if multiple
1709 * DVO outputs are enabled simultaneosly.
1710 */
1711 dpll |= DPLL_DVO_2X_MODE;
1712 I915_WRITE(DPLL(!crtc->pipe),
1713 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1714 }
1715
1716 /* Wait for the clocks to stabilize. */
1717 POSTING_READ(reg);
1718 udelay(150);
1719
1720 if (INTEL_INFO(dev)->gen >= 4) {
1721 I915_WRITE(DPLL_MD(crtc->pipe),
1722 crtc->config->dpll_hw_state.dpll_md);
1723 } else {
1724 /* The pixel multiplier can only be updated once the
1725 * DPLL is enabled and the clocks are stable.
1726 *
1727 * So write it again.
1728 */
1729 I915_WRITE(reg, dpll);
1730 }
1731
1732 /* We do this three times for luck */
1733 I915_WRITE(reg, dpll);
1734 POSTING_READ(reg);
1735 udelay(150); /* wait for warmup */
1736 I915_WRITE(reg, dpll);
1737 POSTING_READ(reg);
1738 udelay(150); /* wait for warmup */
1739 I915_WRITE(reg, dpll);
1740 POSTING_READ(reg);
1741 udelay(150); /* wait for warmup */
1742 }
1743
1744 /**
1745 * i9xx_disable_pll - disable a PLL
1746 * @dev_priv: i915 private structure
1747 * @pipe: pipe PLL to disable
1748 *
1749 * Disable the PLL for @pipe, making sure the pipe is off first.
1750 *
1751 * Note! This is for pre-ILK only.
1752 */
1753 static void i9xx_disable_pll(struct intel_crtc *crtc)
1754 {
1755 struct drm_device *dev = crtc->base.dev;
1756 struct drm_i915_private *dev_priv = dev->dev_private;
1757 enum pipe pipe = crtc->pipe;
1758
1759 /* Disable DVO 2x clock on both PLLs if necessary */
1760 if (IS_I830(dev) &&
1761 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1762 !intel_num_dvo_pipes(dev)) {
1763 I915_WRITE(DPLL(PIPE_B),
1764 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1765 I915_WRITE(DPLL(PIPE_A),
1766 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1767 }
1768
1769 /* Don't disable pipe or pipe PLLs if needed */
1770 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1771 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1772 return;
1773
1774 /* Make sure the pipe isn't still relying on us */
1775 assert_pipe_disabled(dev_priv, pipe);
1776
1777 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1778 POSTING_READ(DPLL(pipe));
1779 }
1780
1781 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1782 {
1783 u32 val;
1784
1785 /* Make sure the pipe isn't still relying on us */
1786 assert_pipe_disabled(dev_priv, pipe);
1787
1788 /*
1789 * Leave integrated clock source and reference clock enabled for pipe B.
1790 * The latter is needed for VGA hotplug / manual detection.
1791 */
1792 val = DPLL_VGA_MODE_DIS;
1793 if (pipe == PIPE_B)
1794 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1795 I915_WRITE(DPLL(pipe), val);
1796 POSTING_READ(DPLL(pipe));
1797
1798 }
1799
1800 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1801 {
1802 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1803 u32 val;
1804
1805 /* Make sure the pipe isn't still relying on us */
1806 assert_pipe_disabled(dev_priv, pipe);
1807
1808 /* Set PLL en = 0 */
1809 val = DPLL_SSC_REF_CLK_CHV |
1810 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1811 if (pipe != PIPE_A)
1812 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1813 I915_WRITE(DPLL(pipe), val);
1814 POSTING_READ(DPLL(pipe));
1815
1816 mutex_lock(&dev_priv->sb_lock);
1817
1818 /* Disable 10bit clock to display controller */
1819 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1820 val &= ~DPIO_DCLKP_EN;
1821 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1822
1823 mutex_unlock(&dev_priv->sb_lock);
1824 }
1825
1826 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1827 struct intel_digital_port *dport,
1828 unsigned int expected_mask)
1829 {
1830 u32 port_mask;
1831 int dpll_reg;
1832
1833 switch (dport->port) {
1834 case PORT_B:
1835 port_mask = DPLL_PORTB_READY_MASK;
1836 dpll_reg = DPLL(0);
1837 break;
1838 case PORT_C:
1839 port_mask = DPLL_PORTC_READY_MASK;
1840 dpll_reg = DPLL(0);
1841 expected_mask <<= 4;
1842 break;
1843 case PORT_D:
1844 port_mask = DPLL_PORTD_READY_MASK;
1845 dpll_reg = DPIO_PHY_STATUS;
1846 break;
1847 default:
1848 BUG();
1849 }
1850
1851 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1852 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1853 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1854 }
1855
1856 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1857 {
1858 struct drm_device *dev = crtc->base.dev;
1859 struct drm_i915_private *dev_priv = dev->dev_private;
1860 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1861
1862 if (WARN_ON(pll == NULL))
1863 return;
1864
1865 WARN_ON(!pll->config.crtc_mask);
1866 if (pll->active == 0) {
1867 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1868 WARN_ON(pll->on);
1869 assert_shared_dpll_disabled(dev_priv, pll);
1870
1871 pll->mode_set(dev_priv, pll);
1872 }
1873 }
1874
1875 /**
1876 * intel_enable_shared_dpll - enable PCH PLL
1877 * @dev_priv: i915 private structure
1878 * @pipe: pipe PLL to enable
1879 *
1880 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1881 * drives the transcoder clock.
1882 */
1883 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1884 {
1885 struct drm_device *dev = crtc->base.dev;
1886 struct drm_i915_private *dev_priv = dev->dev_private;
1887 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1888
1889 if (WARN_ON(pll == NULL))
1890 return;
1891
1892 if (WARN_ON(pll->config.crtc_mask == 0))
1893 return;
1894
1895 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1896 pll->name, pll->active, pll->on,
1897 crtc->base.base.id);
1898
1899 if (pll->active++) {
1900 WARN_ON(!pll->on);
1901 assert_shared_dpll_enabled(dev_priv, pll);
1902 return;
1903 }
1904 WARN_ON(pll->on);
1905
1906 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1907
1908 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1909 pll->enable(dev_priv, pll);
1910 pll->on = true;
1911 }
1912
1913 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1914 {
1915 struct drm_device *dev = crtc->base.dev;
1916 struct drm_i915_private *dev_priv = dev->dev_private;
1917 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1918
1919 /* PCH only available on ILK+ */
1920 if (INTEL_INFO(dev)->gen < 5)
1921 return;
1922
1923 if (pll == NULL)
1924 return;
1925
1926 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1927 return;
1928
1929 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1930 pll->name, pll->active, pll->on,
1931 crtc->base.base.id);
1932
1933 if (WARN_ON(pll->active == 0)) {
1934 assert_shared_dpll_disabled(dev_priv, pll);
1935 return;
1936 }
1937
1938 assert_shared_dpll_enabled(dev_priv, pll);
1939 WARN_ON(!pll->on);
1940 if (--pll->active)
1941 return;
1942
1943 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1944 pll->disable(dev_priv, pll);
1945 pll->on = false;
1946
1947 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1948 }
1949
1950 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1951 enum pipe pipe)
1952 {
1953 struct drm_device *dev = dev_priv->dev;
1954 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1955 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1956 uint32_t reg, val, pipeconf_val;
1957
1958 /* PCH only available on ILK+ */
1959 BUG_ON(!HAS_PCH_SPLIT(dev));
1960
1961 /* Make sure PCH DPLL is enabled */
1962 assert_shared_dpll_enabled(dev_priv,
1963 intel_crtc_to_shared_dpll(intel_crtc));
1964
1965 /* FDI must be feeding us bits for PCH ports */
1966 assert_fdi_tx_enabled(dev_priv, pipe);
1967 assert_fdi_rx_enabled(dev_priv, pipe);
1968
1969 if (HAS_PCH_CPT(dev)) {
1970 /* Workaround: Set the timing override bit before enabling the
1971 * pch transcoder. */
1972 reg = TRANS_CHICKEN2(pipe);
1973 val = I915_READ(reg);
1974 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1975 I915_WRITE(reg, val);
1976 }
1977
1978 reg = PCH_TRANSCONF(pipe);
1979 val = I915_READ(reg);
1980 pipeconf_val = I915_READ(PIPECONF(pipe));
1981
1982 if (HAS_PCH_IBX(dev_priv->dev)) {
1983 /*
1984 * Make the BPC in transcoder be consistent with
1985 * that in pipeconf reg. For HDMI we must use 8bpc
1986 * here for both 8bpc and 12bpc.
1987 */
1988 val &= ~PIPECONF_BPC_MASK;
1989 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1990 val |= PIPECONF_8BPC;
1991 else
1992 val |= pipeconf_val & PIPECONF_BPC_MASK;
1993 }
1994
1995 val &= ~TRANS_INTERLACE_MASK;
1996 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1997 if (HAS_PCH_IBX(dev_priv->dev) &&
1998 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1999 val |= TRANS_LEGACY_INTERLACED_ILK;
2000 else
2001 val |= TRANS_INTERLACED;
2002 else
2003 val |= TRANS_PROGRESSIVE;
2004
2005 I915_WRITE(reg, val | TRANS_ENABLE);
2006 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2007 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2008 }
2009
2010 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2011 enum transcoder cpu_transcoder)
2012 {
2013 u32 val, pipeconf_val;
2014
2015 /* PCH only available on ILK+ */
2016 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2017
2018 /* FDI must be feeding us bits for PCH ports */
2019 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2020 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2021
2022 /* Workaround: set timing override bit. */
2023 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2024 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2025 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2026
2027 val = TRANS_ENABLE;
2028 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2029
2030 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2031 PIPECONF_INTERLACED_ILK)
2032 val |= TRANS_INTERLACED;
2033 else
2034 val |= TRANS_PROGRESSIVE;
2035
2036 I915_WRITE(LPT_TRANSCONF, val);
2037 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2038 DRM_ERROR("Failed to enable PCH transcoder\n");
2039 }
2040
2041 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2042 enum pipe pipe)
2043 {
2044 struct drm_device *dev = dev_priv->dev;
2045 uint32_t reg, val;
2046
2047 /* FDI relies on the transcoder */
2048 assert_fdi_tx_disabled(dev_priv, pipe);
2049 assert_fdi_rx_disabled(dev_priv, pipe);
2050
2051 /* Ports must be off as well */
2052 assert_pch_ports_disabled(dev_priv, pipe);
2053
2054 reg = PCH_TRANSCONF(pipe);
2055 val = I915_READ(reg);
2056 val &= ~TRANS_ENABLE;
2057 I915_WRITE(reg, val);
2058 /* wait for PCH transcoder off, transcoder state */
2059 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2060 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2061
2062 if (!HAS_PCH_IBX(dev)) {
2063 /* Workaround: Clear the timing override chicken bit again. */
2064 reg = TRANS_CHICKEN2(pipe);
2065 val = I915_READ(reg);
2066 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2067 I915_WRITE(reg, val);
2068 }
2069 }
2070
2071 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2072 {
2073 u32 val;
2074
2075 val = I915_READ(LPT_TRANSCONF);
2076 val &= ~TRANS_ENABLE;
2077 I915_WRITE(LPT_TRANSCONF, val);
2078 /* wait for PCH transcoder off, transcoder state */
2079 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2080 DRM_ERROR("Failed to disable PCH transcoder\n");
2081
2082 /* Workaround: clear timing override bit. */
2083 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2084 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2085 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2086 }
2087
2088 /**
2089 * intel_enable_pipe - enable a pipe, asserting requirements
2090 * @crtc: crtc responsible for the pipe
2091 *
2092 * Enable @crtc's pipe, making sure that various hardware specific requirements
2093 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2094 */
2095 static void intel_enable_pipe(struct intel_crtc *crtc)
2096 {
2097 struct drm_device *dev = crtc->base.dev;
2098 struct drm_i915_private *dev_priv = dev->dev_private;
2099 enum pipe pipe = crtc->pipe;
2100 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2101 pipe);
2102 enum pipe pch_transcoder;
2103 int reg;
2104 u32 val;
2105
2106 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2107
2108 assert_planes_disabled(dev_priv, pipe);
2109 assert_cursor_disabled(dev_priv, pipe);
2110 assert_sprites_disabled(dev_priv, pipe);
2111
2112 if (HAS_PCH_LPT(dev_priv->dev))
2113 pch_transcoder = TRANSCODER_A;
2114 else
2115 pch_transcoder = pipe;
2116
2117 /*
2118 * A pipe without a PLL won't actually be able to drive bits from
2119 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2120 * need the check.
2121 */
2122 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2123 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2124 assert_dsi_pll_enabled(dev_priv);
2125 else
2126 assert_pll_enabled(dev_priv, pipe);
2127 else {
2128 if (crtc->config->has_pch_encoder) {
2129 /* if driving the PCH, we need FDI enabled */
2130 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2131 assert_fdi_tx_pll_enabled(dev_priv,
2132 (enum pipe) cpu_transcoder);
2133 }
2134 /* FIXME: assert CPU port conditions for SNB+ */
2135 }
2136
2137 reg = PIPECONF(cpu_transcoder);
2138 val = I915_READ(reg);
2139 if (val & PIPECONF_ENABLE) {
2140 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2141 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2142 return;
2143 }
2144
2145 I915_WRITE(reg, val | PIPECONF_ENABLE);
2146 POSTING_READ(reg);
2147 }
2148
2149 /**
2150 * intel_disable_pipe - disable a pipe, asserting requirements
2151 * @crtc: crtc whose pipes is to be disabled
2152 *
2153 * Disable the pipe of @crtc, making sure that various hardware
2154 * specific requirements are met, if applicable, e.g. plane
2155 * disabled, panel fitter off, etc.
2156 *
2157 * Will wait until the pipe has shut down before returning.
2158 */
2159 static void intel_disable_pipe(struct intel_crtc *crtc)
2160 {
2161 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2162 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2163 enum pipe pipe = crtc->pipe;
2164 int reg;
2165 u32 val;
2166
2167 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2168
2169 /*
2170 * Make sure planes won't keep trying to pump pixels to us,
2171 * or we might hang the display.
2172 */
2173 assert_planes_disabled(dev_priv, pipe);
2174 assert_cursor_disabled(dev_priv, pipe);
2175 assert_sprites_disabled(dev_priv, pipe);
2176
2177 reg = PIPECONF(cpu_transcoder);
2178 val = I915_READ(reg);
2179 if ((val & PIPECONF_ENABLE) == 0)
2180 return;
2181
2182 /*
2183 * Double wide has implications for planes
2184 * so best keep it disabled when not needed.
2185 */
2186 if (crtc->config->double_wide)
2187 val &= ~PIPECONF_DOUBLE_WIDE;
2188
2189 /* Don't disable pipe or pipe PLLs if needed */
2190 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2191 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2192 val &= ~PIPECONF_ENABLE;
2193
2194 I915_WRITE(reg, val);
2195 if ((val & PIPECONF_ENABLE) == 0)
2196 intel_wait_for_pipe_off(crtc);
2197 }
2198
2199 static bool need_vtd_wa(struct drm_device *dev)
2200 {
2201 #ifdef CONFIG_INTEL_IOMMU
2202 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2203 return true;
2204 #endif
2205 return false;
2206 }
2207
2208 unsigned int
2209 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2210 uint64_t fb_format_modifier, unsigned int plane)
2211 {
2212 unsigned int tile_height;
2213 uint32_t pixel_bytes;
2214
2215 switch (fb_format_modifier) {
2216 case DRM_FORMAT_MOD_NONE:
2217 tile_height = 1;
2218 break;
2219 case I915_FORMAT_MOD_X_TILED:
2220 tile_height = IS_GEN2(dev) ? 16 : 8;
2221 break;
2222 case I915_FORMAT_MOD_Y_TILED:
2223 tile_height = 32;
2224 break;
2225 case I915_FORMAT_MOD_Yf_TILED:
2226 pixel_bytes = drm_format_plane_cpp(pixel_format, plane);
2227 switch (pixel_bytes) {
2228 default:
2229 case 1:
2230 tile_height = 64;
2231 break;
2232 case 2:
2233 case 4:
2234 tile_height = 32;
2235 break;
2236 case 8:
2237 tile_height = 16;
2238 break;
2239 case 16:
2240 WARN_ONCE(1,
2241 "128-bit pixels are not supported for display!");
2242 tile_height = 16;
2243 break;
2244 }
2245 break;
2246 default:
2247 MISSING_CASE(fb_format_modifier);
2248 tile_height = 1;
2249 break;
2250 }
2251
2252 return tile_height;
2253 }
2254
2255 unsigned int
2256 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2257 uint32_t pixel_format, uint64_t fb_format_modifier)
2258 {
2259 return ALIGN(height, intel_tile_height(dev, pixel_format,
2260 fb_format_modifier, 0));
2261 }
2262
2263 static int
2264 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2265 const struct drm_plane_state *plane_state)
2266 {
2267 struct intel_rotation_info *info = &view->rotation_info;
2268 unsigned int tile_height, tile_pitch;
2269
2270 *view = i915_ggtt_view_normal;
2271
2272 if (!plane_state)
2273 return 0;
2274
2275 if (!intel_rotation_90_or_270(plane_state->rotation))
2276 return 0;
2277
2278 *view = i915_ggtt_view_rotated;
2279
2280 info->height = fb->height;
2281 info->pixel_format = fb->pixel_format;
2282 info->pitch = fb->pitches[0];
2283 info->uv_offset = fb->offsets[1];
2284 info->fb_modifier = fb->modifier[0];
2285
2286 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2287 fb->modifier[0], 0);
2288 tile_pitch = PAGE_SIZE / tile_height;
2289 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2290 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2291 info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2292
2293 if (info->pixel_format == DRM_FORMAT_NV12) {
2294 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2295 fb->modifier[0], 1);
2296 tile_pitch = PAGE_SIZE / tile_height;
2297 info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2298 info->height_pages_uv = DIV_ROUND_UP(fb->height / 2,
2299 tile_height);
2300 info->size_uv = info->width_pages_uv * info->height_pages_uv *
2301 PAGE_SIZE;
2302 }
2303
2304 return 0;
2305 }
2306
2307 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2308 {
2309 if (INTEL_INFO(dev_priv)->gen >= 9)
2310 return 256 * 1024;
2311 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2312 IS_VALLEYVIEW(dev_priv))
2313 return 128 * 1024;
2314 else if (INTEL_INFO(dev_priv)->gen >= 4)
2315 return 4 * 1024;
2316 else
2317 return 0;
2318 }
2319
2320 int
2321 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2322 struct drm_framebuffer *fb,
2323 const struct drm_plane_state *plane_state,
2324 struct intel_engine_cs *pipelined,
2325 struct drm_i915_gem_request **pipelined_request)
2326 {
2327 struct drm_device *dev = fb->dev;
2328 struct drm_i915_private *dev_priv = dev->dev_private;
2329 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2330 struct i915_ggtt_view view;
2331 u32 alignment;
2332 int ret;
2333
2334 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2335
2336 switch (fb->modifier[0]) {
2337 case DRM_FORMAT_MOD_NONE:
2338 alignment = intel_linear_alignment(dev_priv);
2339 break;
2340 case I915_FORMAT_MOD_X_TILED:
2341 if (INTEL_INFO(dev)->gen >= 9)
2342 alignment = 256 * 1024;
2343 else {
2344 /* pin() will align the object as required by fence */
2345 alignment = 0;
2346 }
2347 break;
2348 case I915_FORMAT_MOD_Y_TILED:
2349 case I915_FORMAT_MOD_Yf_TILED:
2350 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2351 "Y tiling bo slipped through, driver bug!\n"))
2352 return -EINVAL;
2353 alignment = 1 * 1024 * 1024;
2354 break;
2355 default:
2356 MISSING_CASE(fb->modifier[0]);
2357 return -EINVAL;
2358 }
2359
2360 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2361 if (ret)
2362 return ret;
2363
2364 /* Note that the w/a also requires 64 PTE of padding following the
2365 * bo. We currently fill all unused PTE with the shadow page and so
2366 * we should always have valid PTE following the scanout preventing
2367 * the VT-d warning.
2368 */
2369 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2370 alignment = 256 * 1024;
2371
2372 /*
2373 * Global gtt pte registers are special registers which actually forward
2374 * writes to a chunk of system memory. Which means that there is no risk
2375 * that the register values disappear as soon as we call
2376 * intel_runtime_pm_put(), so it is correct to wrap only the
2377 * pin/unpin/fence and not more.
2378 */
2379 intel_runtime_pm_get(dev_priv);
2380
2381 dev_priv->mm.interruptible = false;
2382 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2383 pipelined_request, &view);
2384 if (ret)
2385 goto err_interruptible;
2386
2387 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2388 * fence, whereas 965+ only requires a fence if using
2389 * framebuffer compression. For simplicity, we always install
2390 * a fence as the cost is not that onerous.
2391 */
2392 ret = i915_gem_object_get_fence(obj);
2393 if (ret == -EDEADLK) {
2394 /*
2395 * -EDEADLK means there are no free fences
2396 * no pending flips.
2397 *
2398 * This is propagated to atomic, but it uses
2399 * -EDEADLK to force a locking recovery, so
2400 * change the returned error to -EBUSY.
2401 */
2402 ret = -EBUSY;
2403 goto err_unpin;
2404 } else if (ret)
2405 goto err_unpin;
2406
2407 i915_gem_object_pin_fence(obj);
2408
2409 dev_priv->mm.interruptible = true;
2410 intel_runtime_pm_put(dev_priv);
2411 return 0;
2412
2413 err_unpin:
2414 i915_gem_object_unpin_from_display_plane(obj, &view);
2415 err_interruptible:
2416 dev_priv->mm.interruptible = true;
2417 intel_runtime_pm_put(dev_priv);
2418 return ret;
2419 }
2420
2421 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2422 const struct drm_plane_state *plane_state)
2423 {
2424 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2425 struct i915_ggtt_view view;
2426 int ret;
2427
2428 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2429
2430 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2431 WARN_ONCE(ret, "Couldn't get view from plane state!");
2432
2433 i915_gem_object_unpin_fence(obj);
2434 i915_gem_object_unpin_from_display_plane(obj, &view);
2435 }
2436
2437 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2438 * is assumed to be a power-of-two. */
2439 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2440 int *x, int *y,
2441 unsigned int tiling_mode,
2442 unsigned int cpp,
2443 unsigned int pitch)
2444 {
2445 if (tiling_mode != I915_TILING_NONE) {
2446 unsigned int tile_rows, tiles;
2447
2448 tile_rows = *y / 8;
2449 *y %= 8;
2450
2451 tiles = *x / (512/cpp);
2452 *x %= 512/cpp;
2453
2454 return tile_rows * pitch * 8 + tiles * 4096;
2455 } else {
2456 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2457 unsigned int offset;
2458
2459 offset = *y * pitch + *x * cpp;
2460 *y = (offset & alignment) / pitch;
2461 *x = ((offset & alignment) - *y * pitch) / cpp;
2462 return offset & ~alignment;
2463 }
2464 }
2465
2466 static int i9xx_format_to_fourcc(int format)
2467 {
2468 switch (format) {
2469 case DISPPLANE_8BPP:
2470 return DRM_FORMAT_C8;
2471 case DISPPLANE_BGRX555:
2472 return DRM_FORMAT_XRGB1555;
2473 case DISPPLANE_BGRX565:
2474 return DRM_FORMAT_RGB565;
2475 default:
2476 case DISPPLANE_BGRX888:
2477 return DRM_FORMAT_XRGB8888;
2478 case DISPPLANE_RGBX888:
2479 return DRM_FORMAT_XBGR8888;
2480 case DISPPLANE_BGRX101010:
2481 return DRM_FORMAT_XRGB2101010;
2482 case DISPPLANE_RGBX101010:
2483 return DRM_FORMAT_XBGR2101010;
2484 }
2485 }
2486
2487 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2488 {
2489 switch (format) {
2490 case PLANE_CTL_FORMAT_RGB_565:
2491 return DRM_FORMAT_RGB565;
2492 default:
2493 case PLANE_CTL_FORMAT_XRGB_8888:
2494 if (rgb_order) {
2495 if (alpha)
2496 return DRM_FORMAT_ABGR8888;
2497 else
2498 return DRM_FORMAT_XBGR8888;
2499 } else {
2500 if (alpha)
2501 return DRM_FORMAT_ARGB8888;
2502 else
2503 return DRM_FORMAT_XRGB8888;
2504 }
2505 case PLANE_CTL_FORMAT_XRGB_2101010:
2506 if (rgb_order)
2507 return DRM_FORMAT_XBGR2101010;
2508 else
2509 return DRM_FORMAT_XRGB2101010;
2510 }
2511 }
2512
2513 static bool
2514 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2515 struct intel_initial_plane_config *plane_config)
2516 {
2517 struct drm_device *dev = crtc->base.dev;
2518 struct drm_i915_private *dev_priv = to_i915(dev);
2519 struct drm_i915_gem_object *obj = NULL;
2520 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2521 struct drm_framebuffer *fb = &plane_config->fb->base;
2522 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2523 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2524 PAGE_SIZE);
2525
2526 size_aligned -= base_aligned;
2527
2528 if (plane_config->size == 0)
2529 return false;
2530
2531 /* If the FB is too big, just don't use it since fbdev is not very
2532 * important and we should probably use that space with FBC or other
2533 * features. */
2534 if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size)
2535 return false;
2536
2537 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2538 base_aligned,
2539 base_aligned,
2540 size_aligned);
2541 if (!obj)
2542 return false;
2543
2544 obj->tiling_mode = plane_config->tiling;
2545 if (obj->tiling_mode == I915_TILING_X)
2546 obj->stride = fb->pitches[0];
2547
2548 mode_cmd.pixel_format = fb->pixel_format;
2549 mode_cmd.width = fb->width;
2550 mode_cmd.height = fb->height;
2551 mode_cmd.pitches[0] = fb->pitches[0];
2552 mode_cmd.modifier[0] = fb->modifier[0];
2553 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2554
2555 mutex_lock(&dev->struct_mutex);
2556 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2557 &mode_cmd, obj)) {
2558 DRM_DEBUG_KMS("intel fb init failed\n");
2559 goto out_unref_obj;
2560 }
2561 mutex_unlock(&dev->struct_mutex);
2562
2563 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2564 return true;
2565
2566 out_unref_obj:
2567 drm_gem_object_unreference(&obj->base);
2568 mutex_unlock(&dev->struct_mutex);
2569 return false;
2570 }
2571
2572 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2573 static void
2574 update_state_fb(struct drm_plane *plane)
2575 {
2576 if (plane->fb == plane->state->fb)
2577 return;
2578
2579 if (plane->state->fb)
2580 drm_framebuffer_unreference(plane->state->fb);
2581 plane->state->fb = plane->fb;
2582 if (plane->state->fb)
2583 drm_framebuffer_reference(plane->state->fb);
2584 }
2585
2586 static void
2587 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2588 struct intel_initial_plane_config *plane_config)
2589 {
2590 struct drm_device *dev = intel_crtc->base.dev;
2591 struct drm_i915_private *dev_priv = dev->dev_private;
2592 struct drm_crtc *c;
2593 struct intel_crtc *i;
2594 struct drm_i915_gem_object *obj;
2595 struct drm_plane *primary = intel_crtc->base.primary;
2596 struct drm_plane_state *plane_state = primary->state;
2597 struct drm_framebuffer *fb;
2598
2599 if (!plane_config->fb)
2600 return;
2601
2602 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2603 fb = &plane_config->fb->base;
2604 goto valid_fb;
2605 }
2606
2607 kfree(plane_config->fb);
2608
2609 /*
2610 * Failed to alloc the obj, check to see if we should share
2611 * an fb with another CRTC instead
2612 */
2613 for_each_crtc(dev, c) {
2614 i = to_intel_crtc(c);
2615
2616 if (c == &intel_crtc->base)
2617 continue;
2618
2619 if (!i->active)
2620 continue;
2621
2622 fb = c->primary->fb;
2623 if (!fb)
2624 continue;
2625
2626 obj = intel_fb_obj(fb);
2627 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2628 drm_framebuffer_reference(fb);
2629 goto valid_fb;
2630 }
2631 }
2632
2633 return;
2634
2635 valid_fb:
2636 plane_state->src_x = plane_state->src_y = 0;
2637 plane_state->src_w = fb->width << 16;
2638 plane_state->src_h = fb->height << 16;
2639
2640 plane_state->crtc_x = plane_state->src_y = 0;
2641 plane_state->crtc_w = fb->width;
2642 plane_state->crtc_h = fb->height;
2643
2644 obj = intel_fb_obj(fb);
2645 if (obj->tiling_mode != I915_TILING_NONE)
2646 dev_priv->preserve_bios_swizzle = true;
2647
2648 drm_framebuffer_reference(fb);
2649 primary->fb = primary->state->fb = fb;
2650 primary->crtc = primary->state->crtc = &intel_crtc->base;
2651 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2652 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2653 }
2654
2655 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2656 struct drm_framebuffer *fb,
2657 int x, int y)
2658 {
2659 struct drm_device *dev = crtc->dev;
2660 struct drm_i915_private *dev_priv = dev->dev_private;
2661 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2662 struct drm_plane *primary = crtc->primary;
2663 bool visible = to_intel_plane_state(primary->state)->visible;
2664 struct drm_i915_gem_object *obj;
2665 int plane = intel_crtc->plane;
2666 unsigned long linear_offset;
2667 u32 dspcntr;
2668 u32 reg = DSPCNTR(plane);
2669 int pixel_size;
2670
2671 if (!visible || !fb) {
2672 I915_WRITE(reg, 0);
2673 if (INTEL_INFO(dev)->gen >= 4)
2674 I915_WRITE(DSPSURF(plane), 0);
2675 else
2676 I915_WRITE(DSPADDR(plane), 0);
2677 POSTING_READ(reg);
2678 return;
2679 }
2680
2681 obj = intel_fb_obj(fb);
2682 if (WARN_ON(obj == NULL))
2683 return;
2684
2685 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2686
2687 dspcntr = DISPPLANE_GAMMA_ENABLE;
2688
2689 dspcntr |= DISPLAY_PLANE_ENABLE;
2690
2691 if (INTEL_INFO(dev)->gen < 4) {
2692 if (intel_crtc->pipe == PIPE_B)
2693 dspcntr |= DISPPLANE_SEL_PIPE_B;
2694
2695 /* pipesrc and dspsize control the size that is scaled from,
2696 * which should always be the user's requested size.
2697 */
2698 I915_WRITE(DSPSIZE(plane),
2699 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2700 (intel_crtc->config->pipe_src_w - 1));
2701 I915_WRITE(DSPPOS(plane), 0);
2702 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2703 I915_WRITE(PRIMSIZE(plane),
2704 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2705 (intel_crtc->config->pipe_src_w - 1));
2706 I915_WRITE(PRIMPOS(plane), 0);
2707 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2708 }
2709
2710 switch (fb->pixel_format) {
2711 case DRM_FORMAT_C8:
2712 dspcntr |= DISPPLANE_8BPP;
2713 break;
2714 case DRM_FORMAT_XRGB1555:
2715 dspcntr |= DISPPLANE_BGRX555;
2716 break;
2717 case DRM_FORMAT_RGB565:
2718 dspcntr |= DISPPLANE_BGRX565;
2719 break;
2720 case DRM_FORMAT_XRGB8888:
2721 dspcntr |= DISPPLANE_BGRX888;
2722 break;
2723 case DRM_FORMAT_XBGR8888:
2724 dspcntr |= DISPPLANE_RGBX888;
2725 break;
2726 case DRM_FORMAT_XRGB2101010:
2727 dspcntr |= DISPPLANE_BGRX101010;
2728 break;
2729 case DRM_FORMAT_XBGR2101010:
2730 dspcntr |= DISPPLANE_RGBX101010;
2731 break;
2732 default:
2733 BUG();
2734 }
2735
2736 if (INTEL_INFO(dev)->gen >= 4 &&
2737 obj->tiling_mode != I915_TILING_NONE)
2738 dspcntr |= DISPPLANE_TILED;
2739
2740 if (IS_G4X(dev))
2741 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2742
2743 linear_offset = y * fb->pitches[0] + x * pixel_size;
2744
2745 if (INTEL_INFO(dev)->gen >= 4) {
2746 intel_crtc->dspaddr_offset =
2747 intel_gen4_compute_page_offset(dev_priv,
2748 &x, &y, obj->tiling_mode,
2749 pixel_size,
2750 fb->pitches[0]);
2751 linear_offset -= intel_crtc->dspaddr_offset;
2752 } else {
2753 intel_crtc->dspaddr_offset = linear_offset;
2754 }
2755
2756 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2757 dspcntr |= DISPPLANE_ROTATE_180;
2758
2759 x += (intel_crtc->config->pipe_src_w - 1);
2760 y += (intel_crtc->config->pipe_src_h - 1);
2761
2762 /* Finding the last pixel of the last line of the display
2763 data and adding to linear_offset*/
2764 linear_offset +=
2765 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2766 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2767 }
2768
2769 intel_crtc->adjusted_x = x;
2770 intel_crtc->adjusted_y = y;
2771
2772 I915_WRITE(reg, dspcntr);
2773
2774 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2775 if (INTEL_INFO(dev)->gen >= 4) {
2776 I915_WRITE(DSPSURF(plane),
2777 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2778 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2779 I915_WRITE(DSPLINOFF(plane), linear_offset);
2780 } else
2781 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2782 POSTING_READ(reg);
2783 }
2784
2785 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2786 struct drm_framebuffer *fb,
2787 int x, int y)
2788 {
2789 struct drm_device *dev = crtc->dev;
2790 struct drm_i915_private *dev_priv = dev->dev_private;
2791 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2792 struct drm_plane *primary = crtc->primary;
2793 bool visible = to_intel_plane_state(primary->state)->visible;
2794 struct drm_i915_gem_object *obj;
2795 int plane = intel_crtc->plane;
2796 unsigned long linear_offset;
2797 u32 dspcntr;
2798 u32 reg = DSPCNTR(plane);
2799 int pixel_size;
2800
2801 if (!visible || !fb) {
2802 I915_WRITE(reg, 0);
2803 I915_WRITE(DSPSURF(plane), 0);
2804 POSTING_READ(reg);
2805 return;
2806 }
2807
2808 obj = intel_fb_obj(fb);
2809 if (WARN_ON(obj == NULL))
2810 return;
2811
2812 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2813
2814 dspcntr = DISPPLANE_GAMMA_ENABLE;
2815
2816 dspcntr |= DISPLAY_PLANE_ENABLE;
2817
2818 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2819 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2820
2821 switch (fb->pixel_format) {
2822 case DRM_FORMAT_C8:
2823 dspcntr |= DISPPLANE_8BPP;
2824 break;
2825 case DRM_FORMAT_RGB565:
2826 dspcntr |= DISPPLANE_BGRX565;
2827 break;
2828 case DRM_FORMAT_XRGB8888:
2829 dspcntr |= DISPPLANE_BGRX888;
2830 break;
2831 case DRM_FORMAT_XBGR8888:
2832 dspcntr |= DISPPLANE_RGBX888;
2833 break;
2834 case DRM_FORMAT_XRGB2101010:
2835 dspcntr |= DISPPLANE_BGRX101010;
2836 break;
2837 case DRM_FORMAT_XBGR2101010:
2838 dspcntr |= DISPPLANE_RGBX101010;
2839 break;
2840 default:
2841 BUG();
2842 }
2843
2844 if (obj->tiling_mode != I915_TILING_NONE)
2845 dspcntr |= DISPPLANE_TILED;
2846
2847 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2848 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2849
2850 linear_offset = y * fb->pitches[0] + x * pixel_size;
2851 intel_crtc->dspaddr_offset =
2852 intel_gen4_compute_page_offset(dev_priv,
2853 &x, &y, obj->tiling_mode,
2854 pixel_size,
2855 fb->pitches[0]);
2856 linear_offset -= intel_crtc->dspaddr_offset;
2857 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2858 dspcntr |= DISPPLANE_ROTATE_180;
2859
2860 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2861 x += (intel_crtc->config->pipe_src_w - 1);
2862 y += (intel_crtc->config->pipe_src_h - 1);
2863
2864 /* Finding the last pixel of the last line of the display
2865 data and adding to linear_offset*/
2866 linear_offset +=
2867 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2868 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2869 }
2870 }
2871
2872 intel_crtc->adjusted_x = x;
2873 intel_crtc->adjusted_y = y;
2874
2875 I915_WRITE(reg, dspcntr);
2876
2877 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2878 I915_WRITE(DSPSURF(plane),
2879 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2880 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2881 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2882 } else {
2883 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2884 I915_WRITE(DSPLINOFF(plane), linear_offset);
2885 }
2886 POSTING_READ(reg);
2887 }
2888
2889 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2890 uint32_t pixel_format)
2891 {
2892 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2893
2894 /*
2895 * The stride is either expressed as a multiple of 64 bytes
2896 * chunks for linear buffers or in number of tiles for tiled
2897 * buffers.
2898 */
2899 switch (fb_modifier) {
2900 case DRM_FORMAT_MOD_NONE:
2901 return 64;
2902 case I915_FORMAT_MOD_X_TILED:
2903 if (INTEL_INFO(dev)->gen == 2)
2904 return 128;
2905 return 512;
2906 case I915_FORMAT_MOD_Y_TILED:
2907 /* No need to check for old gens and Y tiling since this is
2908 * about the display engine and those will be blocked before
2909 * we get here.
2910 */
2911 return 128;
2912 case I915_FORMAT_MOD_Yf_TILED:
2913 if (bits_per_pixel == 8)
2914 return 64;
2915 else
2916 return 128;
2917 default:
2918 MISSING_CASE(fb_modifier);
2919 return 64;
2920 }
2921 }
2922
2923 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2924 struct drm_i915_gem_object *obj,
2925 unsigned int plane)
2926 {
2927 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2928 struct i915_vma *vma;
2929 unsigned char *offset;
2930
2931 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2932 view = &i915_ggtt_view_rotated;
2933
2934 vma = i915_gem_obj_to_ggtt_view(obj, view);
2935 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2936 view->type))
2937 return -1;
2938
2939 offset = (unsigned char *)vma->node.start;
2940
2941 if (plane == 1) {
2942 offset += vma->ggtt_view.rotation_info.uv_start_page *
2943 PAGE_SIZE;
2944 }
2945
2946 return (unsigned long)offset;
2947 }
2948
2949 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2950 {
2951 struct drm_device *dev = intel_crtc->base.dev;
2952 struct drm_i915_private *dev_priv = dev->dev_private;
2953
2954 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2955 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2956 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2957 }
2958
2959 /*
2960 * This function detaches (aka. unbinds) unused scalers in hardware
2961 */
2962 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2963 {
2964 struct intel_crtc_scaler_state *scaler_state;
2965 int i;
2966
2967 scaler_state = &intel_crtc->config->scaler_state;
2968
2969 /* loop through and disable scalers that aren't in use */
2970 for (i = 0; i < intel_crtc->num_scalers; i++) {
2971 if (!scaler_state->scalers[i].in_use)
2972 skl_detach_scaler(intel_crtc, i);
2973 }
2974 }
2975
2976 u32 skl_plane_ctl_format(uint32_t pixel_format)
2977 {
2978 switch (pixel_format) {
2979 case DRM_FORMAT_C8:
2980 return PLANE_CTL_FORMAT_INDEXED;
2981 case DRM_FORMAT_RGB565:
2982 return PLANE_CTL_FORMAT_RGB_565;
2983 case DRM_FORMAT_XBGR8888:
2984 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2985 case DRM_FORMAT_XRGB8888:
2986 return PLANE_CTL_FORMAT_XRGB_8888;
2987 /*
2988 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2989 * to be already pre-multiplied. We need to add a knob (or a different
2990 * DRM_FORMAT) for user-space to configure that.
2991 */
2992 case DRM_FORMAT_ABGR8888:
2993 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2994 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2995 case DRM_FORMAT_ARGB8888:
2996 return PLANE_CTL_FORMAT_XRGB_8888 |
2997 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2998 case DRM_FORMAT_XRGB2101010:
2999 return PLANE_CTL_FORMAT_XRGB_2101010;
3000 case DRM_FORMAT_XBGR2101010:
3001 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3002 case DRM_FORMAT_YUYV:
3003 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3004 case DRM_FORMAT_YVYU:
3005 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3006 case DRM_FORMAT_UYVY:
3007 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3008 case DRM_FORMAT_VYUY:
3009 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3010 default:
3011 MISSING_CASE(pixel_format);
3012 }
3013
3014 return 0;
3015 }
3016
3017 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3018 {
3019 switch (fb_modifier) {
3020 case DRM_FORMAT_MOD_NONE:
3021 break;
3022 case I915_FORMAT_MOD_X_TILED:
3023 return PLANE_CTL_TILED_X;
3024 case I915_FORMAT_MOD_Y_TILED:
3025 return PLANE_CTL_TILED_Y;
3026 case I915_FORMAT_MOD_Yf_TILED:
3027 return PLANE_CTL_TILED_YF;
3028 default:
3029 MISSING_CASE(fb_modifier);
3030 }
3031
3032 return 0;
3033 }
3034
3035 u32 skl_plane_ctl_rotation(unsigned int rotation)
3036 {
3037 switch (rotation) {
3038 case BIT(DRM_ROTATE_0):
3039 break;
3040 /*
3041 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3042 * while i915 HW rotation is clockwise, thats why this swapping.
3043 */
3044 case BIT(DRM_ROTATE_90):
3045 return PLANE_CTL_ROTATE_270;
3046 case BIT(DRM_ROTATE_180):
3047 return PLANE_CTL_ROTATE_180;
3048 case BIT(DRM_ROTATE_270):
3049 return PLANE_CTL_ROTATE_90;
3050 default:
3051 MISSING_CASE(rotation);
3052 }
3053
3054 return 0;
3055 }
3056
3057 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3058 struct drm_framebuffer *fb,
3059 int x, int y)
3060 {
3061 struct drm_device *dev = crtc->dev;
3062 struct drm_i915_private *dev_priv = dev->dev_private;
3063 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3064 struct drm_plane *plane = crtc->primary;
3065 bool visible = to_intel_plane_state(plane->state)->visible;
3066 struct drm_i915_gem_object *obj;
3067 int pipe = intel_crtc->pipe;
3068 u32 plane_ctl, stride_div, stride;
3069 u32 tile_height, plane_offset, plane_size;
3070 unsigned int rotation;
3071 int x_offset, y_offset;
3072 unsigned long surf_addr;
3073 struct intel_crtc_state *crtc_state = intel_crtc->config;
3074 struct intel_plane_state *plane_state;
3075 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3076 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3077 int scaler_id = -1;
3078
3079 plane_state = to_intel_plane_state(plane->state);
3080
3081 if (!visible || !fb) {
3082 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3083 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3084 POSTING_READ(PLANE_CTL(pipe, 0));
3085 return;
3086 }
3087
3088 plane_ctl = PLANE_CTL_ENABLE |
3089 PLANE_CTL_PIPE_GAMMA_ENABLE |
3090 PLANE_CTL_PIPE_CSC_ENABLE;
3091
3092 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3093 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3094 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3095
3096 rotation = plane->state->rotation;
3097 plane_ctl |= skl_plane_ctl_rotation(rotation);
3098
3099 obj = intel_fb_obj(fb);
3100 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3101 fb->pixel_format);
3102 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3103
3104 WARN_ON(drm_rect_width(&plane_state->src) == 0);
3105
3106 scaler_id = plane_state->scaler_id;
3107 src_x = plane_state->src.x1 >> 16;
3108 src_y = plane_state->src.y1 >> 16;
3109 src_w = drm_rect_width(&plane_state->src) >> 16;
3110 src_h = drm_rect_height(&plane_state->src) >> 16;
3111 dst_x = plane_state->dst.x1;
3112 dst_y = plane_state->dst.y1;
3113 dst_w = drm_rect_width(&plane_state->dst);
3114 dst_h = drm_rect_height(&plane_state->dst);
3115
3116 WARN_ON(x != src_x || y != src_y);
3117
3118 if (intel_rotation_90_or_270(rotation)) {
3119 /* stride = Surface height in tiles */
3120 tile_height = intel_tile_height(dev, fb->pixel_format,
3121 fb->modifier[0], 0);
3122 stride = DIV_ROUND_UP(fb->height, tile_height);
3123 x_offset = stride * tile_height - y - src_h;
3124 y_offset = x;
3125 plane_size = (src_w - 1) << 16 | (src_h - 1);
3126 } else {
3127 stride = fb->pitches[0] / stride_div;
3128 x_offset = x;
3129 y_offset = y;
3130 plane_size = (src_h - 1) << 16 | (src_w - 1);
3131 }
3132 plane_offset = y_offset << 16 | x_offset;
3133
3134 intel_crtc->adjusted_x = x_offset;
3135 intel_crtc->adjusted_y = y_offset;
3136
3137 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3138 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3139 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3140 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3141
3142 if (scaler_id >= 0) {
3143 uint32_t ps_ctrl = 0;
3144
3145 WARN_ON(!dst_w || !dst_h);
3146 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3147 crtc_state->scaler_state.scalers[scaler_id].mode;
3148 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3149 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3150 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3151 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3152 I915_WRITE(PLANE_POS(pipe, 0), 0);
3153 } else {
3154 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3155 }
3156
3157 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3158
3159 POSTING_READ(PLANE_SURF(pipe, 0));
3160 }
3161
3162 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3163 static int
3164 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3165 int x, int y, enum mode_set_atomic state)
3166 {
3167 struct drm_device *dev = crtc->dev;
3168 struct drm_i915_private *dev_priv = dev->dev_private;
3169
3170 if (dev_priv->fbc.disable_fbc)
3171 dev_priv->fbc.disable_fbc(dev_priv);
3172
3173 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3174
3175 return 0;
3176 }
3177
3178 static void intel_complete_page_flips(struct drm_device *dev)
3179 {
3180 struct drm_crtc *crtc;
3181
3182 for_each_crtc(dev, crtc) {
3183 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3184 enum plane plane = intel_crtc->plane;
3185
3186 intel_prepare_page_flip(dev, plane);
3187 intel_finish_page_flip_plane(dev, plane);
3188 }
3189 }
3190
3191 static void intel_update_primary_planes(struct drm_device *dev)
3192 {
3193 struct drm_crtc *crtc;
3194
3195 for_each_crtc(dev, crtc) {
3196 struct intel_plane *plane = to_intel_plane(crtc->primary);
3197 struct intel_plane_state *plane_state;
3198
3199 drm_modeset_lock_crtc(crtc, &plane->base);
3200
3201 plane_state = to_intel_plane_state(plane->base.state);
3202
3203 if (plane_state->base.fb)
3204 plane->commit_plane(&plane->base, plane_state);
3205
3206 drm_modeset_unlock_crtc(crtc);
3207 }
3208 }
3209
3210 void intel_prepare_reset(struct drm_device *dev)
3211 {
3212 /* no reset support for gen2 */
3213 if (IS_GEN2(dev))
3214 return;
3215
3216 /* reset doesn't touch the display */
3217 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3218 return;
3219
3220 drm_modeset_lock_all(dev);
3221 /*
3222 * Disabling the crtcs gracefully seems nicer. Also the
3223 * g33 docs say we should at least disable all the planes.
3224 */
3225 intel_display_suspend(dev);
3226 }
3227
3228 void intel_finish_reset(struct drm_device *dev)
3229 {
3230 struct drm_i915_private *dev_priv = to_i915(dev);
3231
3232 /*
3233 * Flips in the rings will be nuked by the reset,
3234 * so complete all pending flips so that user space
3235 * will get its events and not get stuck.
3236 */
3237 intel_complete_page_flips(dev);
3238
3239 /* no reset support for gen2 */
3240 if (IS_GEN2(dev))
3241 return;
3242
3243 /* reset doesn't touch the display */
3244 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3245 /*
3246 * Flips in the rings have been nuked by the reset,
3247 * so update the base address of all primary
3248 * planes to the the last fb to make sure we're
3249 * showing the correct fb after a reset.
3250 *
3251 * FIXME: Atomic will make this obsolete since we won't schedule
3252 * CS-based flips (which might get lost in gpu resets) any more.
3253 */
3254 intel_update_primary_planes(dev);
3255 return;
3256 }
3257
3258 /*
3259 * The display has been reset as well,
3260 * so need a full re-initialization.
3261 */
3262 intel_runtime_pm_disable_interrupts(dev_priv);
3263 intel_runtime_pm_enable_interrupts(dev_priv);
3264
3265 intel_modeset_init_hw(dev);
3266
3267 spin_lock_irq(&dev_priv->irq_lock);
3268 if (dev_priv->display.hpd_irq_setup)
3269 dev_priv->display.hpd_irq_setup(dev);
3270 spin_unlock_irq(&dev_priv->irq_lock);
3271
3272 intel_display_resume(dev);
3273
3274 intel_hpd_init(dev_priv);
3275
3276 drm_modeset_unlock_all(dev);
3277 }
3278
3279 static void
3280 intel_finish_fb(struct drm_framebuffer *old_fb)
3281 {
3282 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3283 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3284 bool was_interruptible = dev_priv->mm.interruptible;
3285 int ret;
3286
3287 /* Big Hammer, we also need to ensure that any pending
3288 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3289 * current scanout is retired before unpinning the old
3290 * framebuffer. Note that we rely on userspace rendering
3291 * into the buffer attached to the pipe they are waiting
3292 * on. If not, userspace generates a GPU hang with IPEHR
3293 * point to the MI_WAIT_FOR_EVENT.
3294 *
3295 * This should only fail upon a hung GPU, in which case we
3296 * can safely continue.
3297 */
3298 dev_priv->mm.interruptible = false;
3299 ret = i915_gem_object_wait_rendering(obj, true);
3300 dev_priv->mm.interruptible = was_interruptible;
3301
3302 WARN_ON(ret);
3303 }
3304
3305 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3306 {
3307 struct drm_device *dev = crtc->dev;
3308 struct drm_i915_private *dev_priv = dev->dev_private;
3309 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3310 bool pending;
3311
3312 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3313 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3314 return false;
3315
3316 spin_lock_irq(&dev->event_lock);
3317 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3318 spin_unlock_irq(&dev->event_lock);
3319
3320 return pending;
3321 }
3322
3323 static void intel_update_pipe_config(struct intel_crtc *crtc,
3324 struct intel_crtc_state *old_crtc_state)
3325 {
3326 struct drm_device *dev = crtc->base.dev;
3327 struct drm_i915_private *dev_priv = dev->dev_private;
3328 struct intel_crtc_state *pipe_config =
3329 to_intel_crtc_state(crtc->base.state);
3330
3331 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3332 crtc->base.mode = crtc->base.state->mode;
3333
3334 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3335 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3336 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3337
3338 if (HAS_DDI(dev))
3339 intel_set_pipe_csc(&crtc->base);
3340
3341 /*
3342 * Update pipe size and adjust fitter if needed: the reason for this is
3343 * that in compute_mode_changes we check the native mode (not the pfit
3344 * mode) to see if we can flip rather than do a full mode set. In the
3345 * fastboot case, we'll flip, but if we don't update the pipesrc and
3346 * pfit state, we'll end up with a big fb scanned out into the wrong
3347 * sized surface.
3348 */
3349
3350 I915_WRITE(PIPESRC(crtc->pipe),
3351 ((pipe_config->pipe_src_w - 1) << 16) |
3352 (pipe_config->pipe_src_h - 1));
3353
3354 /* on skylake this is done by detaching scalers */
3355 if (INTEL_INFO(dev)->gen >= 9) {
3356 skl_detach_scalers(crtc);
3357
3358 if (pipe_config->pch_pfit.enabled)
3359 skylake_pfit_enable(crtc);
3360 } else if (HAS_PCH_SPLIT(dev)) {
3361 if (pipe_config->pch_pfit.enabled)
3362 ironlake_pfit_enable(crtc);
3363 else if (old_crtc_state->pch_pfit.enabled)
3364 ironlake_pfit_disable(crtc, true);
3365 }
3366 }
3367
3368 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3369 {
3370 struct drm_device *dev = crtc->dev;
3371 struct drm_i915_private *dev_priv = dev->dev_private;
3372 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3373 int pipe = intel_crtc->pipe;
3374 u32 reg, temp;
3375
3376 /* enable normal train */
3377 reg = FDI_TX_CTL(pipe);
3378 temp = I915_READ(reg);
3379 if (IS_IVYBRIDGE(dev)) {
3380 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3381 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3382 } else {
3383 temp &= ~FDI_LINK_TRAIN_NONE;
3384 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3385 }
3386 I915_WRITE(reg, temp);
3387
3388 reg = FDI_RX_CTL(pipe);
3389 temp = I915_READ(reg);
3390 if (HAS_PCH_CPT(dev)) {
3391 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3392 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3393 } else {
3394 temp &= ~FDI_LINK_TRAIN_NONE;
3395 temp |= FDI_LINK_TRAIN_NONE;
3396 }
3397 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3398
3399 /* wait one idle pattern time */
3400 POSTING_READ(reg);
3401 udelay(1000);
3402
3403 /* IVB wants error correction enabled */
3404 if (IS_IVYBRIDGE(dev))
3405 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3406 FDI_FE_ERRC_ENABLE);
3407 }
3408
3409 /* The FDI link training functions for ILK/Ibexpeak. */
3410 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3411 {
3412 struct drm_device *dev = crtc->dev;
3413 struct drm_i915_private *dev_priv = dev->dev_private;
3414 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3415 int pipe = intel_crtc->pipe;
3416 u32 reg, temp, tries;
3417
3418 /* FDI needs bits from pipe first */
3419 assert_pipe_enabled(dev_priv, pipe);
3420
3421 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3422 for train result */
3423 reg = FDI_RX_IMR(pipe);
3424 temp = I915_READ(reg);
3425 temp &= ~FDI_RX_SYMBOL_LOCK;
3426 temp &= ~FDI_RX_BIT_LOCK;
3427 I915_WRITE(reg, temp);
3428 I915_READ(reg);
3429 udelay(150);
3430
3431 /* enable CPU FDI TX and PCH FDI RX */
3432 reg = FDI_TX_CTL(pipe);
3433 temp = I915_READ(reg);
3434 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3435 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3436 temp &= ~FDI_LINK_TRAIN_NONE;
3437 temp |= FDI_LINK_TRAIN_PATTERN_1;
3438 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3439
3440 reg = FDI_RX_CTL(pipe);
3441 temp = I915_READ(reg);
3442 temp &= ~FDI_LINK_TRAIN_NONE;
3443 temp |= FDI_LINK_TRAIN_PATTERN_1;
3444 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3445
3446 POSTING_READ(reg);
3447 udelay(150);
3448
3449 /* Ironlake workaround, enable clock pointer after FDI enable*/
3450 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3451 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3452 FDI_RX_PHASE_SYNC_POINTER_EN);
3453
3454 reg = FDI_RX_IIR(pipe);
3455 for (tries = 0; tries < 5; tries++) {
3456 temp = I915_READ(reg);
3457 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3458
3459 if ((temp & FDI_RX_BIT_LOCK)) {
3460 DRM_DEBUG_KMS("FDI train 1 done.\n");
3461 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3462 break;
3463 }
3464 }
3465 if (tries == 5)
3466 DRM_ERROR("FDI train 1 fail!\n");
3467
3468 /* Train 2 */
3469 reg = FDI_TX_CTL(pipe);
3470 temp = I915_READ(reg);
3471 temp &= ~FDI_LINK_TRAIN_NONE;
3472 temp |= FDI_LINK_TRAIN_PATTERN_2;
3473 I915_WRITE(reg, temp);
3474
3475 reg = FDI_RX_CTL(pipe);
3476 temp = I915_READ(reg);
3477 temp &= ~FDI_LINK_TRAIN_NONE;
3478 temp |= FDI_LINK_TRAIN_PATTERN_2;
3479 I915_WRITE(reg, temp);
3480
3481 POSTING_READ(reg);
3482 udelay(150);
3483
3484 reg = FDI_RX_IIR(pipe);
3485 for (tries = 0; tries < 5; tries++) {
3486 temp = I915_READ(reg);
3487 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3488
3489 if (temp & FDI_RX_SYMBOL_LOCK) {
3490 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3491 DRM_DEBUG_KMS("FDI train 2 done.\n");
3492 break;
3493 }
3494 }
3495 if (tries == 5)
3496 DRM_ERROR("FDI train 2 fail!\n");
3497
3498 DRM_DEBUG_KMS("FDI train done\n");
3499
3500 }
3501
3502 static const int snb_b_fdi_train_param[] = {
3503 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3504 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3505 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3506 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3507 };
3508
3509 /* The FDI link training functions for SNB/Cougarpoint. */
3510 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3511 {
3512 struct drm_device *dev = crtc->dev;
3513 struct drm_i915_private *dev_priv = dev->dev_private;
3514 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3515 int pipe = intel_crtc->pipe;
3516 u32 reg, temp, i, retry;
3517
3518 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3519 for train result */
3520 reg = FDI_RX_IMR(pipe);
3521 temp = I915_READ(reg);
3522 temp &= ~FDI_RX_SYMBOL_LOCK;
3523 temp &= ~FDI_RX_BIT_LOCK;
3524 I915_WRITE(reg, temp);
3525
3526 POSTING_READ(reg);
3527 udelay(150);
3528
3529 /* enable CPU FDI TX and PCH FDI RX */
3530 reg = FDI_TX_CTL(pipe);
3531 temp = I915_READ(reg);
3532 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3533 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3534 temp &= ~FDI_LINK_TRAIN_NONE;
3535 temp |= FDI_LINK_TRAIN_PATTERN_1;
3536 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3537 /* SNB-B */
3538 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3539 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3540
3541 I915_WRITE(FDI_RX_MISC(pipe),
3542 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3543
3544 reg = FDI_RX_CTL(pipe);
3545 temp = I915_READ(reg);
3546 if (HAS_PCH_CPT(dev)) {
3547 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3548 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3549 } else {
3550 temp &= ~FDI_LINK_TRAIN_NONE;
3551 temp |= FDI_LINK_TRAIN_PATTERN_1;
3552 }
3553 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3554
3555 POSTING_READ(reg);
3556 udelay(150);
3557
3558 for (i = 0; i < 4; i++) {
3559 reg = FDI_TX_CTL(pipe);
3560 temp = I915_READ(reg);
3561 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3562 temp |= snb_b_fdi_train_param[i];
3563 I915_WRITE(reg, temp);
3564
3565 POSTING_READ(reg);
3566 udelay(500);
3567
3568 for (retry = 0; retry < 5; retry++) {
3569 reg = FDI_RX_IIR(pipe);
3570 temp = I915_READ(reg);
3571 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3572 if (temp & FDI_RX_BIT_LOCK) {
3573 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3574 DRM_DEBUG_KMS("FDI train 1 done.\n");
3575 break;
3576 }
3577 udelay(50);
3578 }
3579 if (retry < 5)
3580 break;
3581 }
3582 if (i == 4)
3583 DRM_ERROR("FDI train 1 fail!\n");
3584
3585 /* Train 2 */
3586 reg = FDI_TX_CTL(pipe);
3587 temp = I915_READ(reg);
3588 temp &= ~FDI_LINK_TRAIN_NONE;
3589 temp |= FDI_LINK_TRAIN_PATTERN_2;
3590 if (IS_GEN6(dev)) {
3591 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3592 /* SNB-B */
3593 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3594 }
3595 I915_WRITE(reg, temp);
3596
3597 reg = FDI_RX_CTL(pipe);
3598 temp = I915_READ(reg);
3599 if (HAS_PCH_CPT(dev)) {
3600 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3601 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3602 } else {
3603 temp &= ~FDI_LINK_TRAIN_NONE;
3604 temp |= FDI_LINK_TRAIN_PATTERN_2;
3605 }
3606 I915_WRITE(reg, temp);
3607
3608 POSTING_READ(reg);
3609 udelay(150);
3610
3611 for (i = 0; i < 4; i++) {
3612 reg = FDI_TX_CTL(pipe);
3613 temp = I915_READ(reg);
3614 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3615 temp |= snb_b_fdi_train_param[i];
3616 I915_WRITE(reg, temp);
3617
3618 POSTING_READ(reg);
3619 udelay(500);
3620
3621 for (retry = 0; retry < 5; retry++) {
3622 reg = FDI_RX_IIR(pipe);
3623 temp = I915_READ(reg);
3624 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3625 if (temp & FDI_RX_SYMBOL_LOCK) {
3626 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3627 DRM_DEBUG_KMS("FDI train 2 done.\n");
3628 break;
3629 }
3630 udelay(50);
3631 }
3632 if (retry < 5)
3633 break;
3634 }
3635 if (i == 4)
3636 DRM_ERROR("FDI train 2 fail!\n");
3637
3638 DRM_DEBUG_KMS("FDI train done.\n");
3639 }
3640
3641 /* Manual link training for Ivy Bridge A0 parts */
3642 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3643 {
3644 struct drm_device *dev = crtc->dev;
3645 struct drm_i915_private *dev_priv = dev->dev_private;
3646 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3647 int pipe = intel_crtc->pipe;
3648 u32 reg, temp, i, j;
3649
3650 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3651 for train result */
3652 reg = FDI_RX_IMR(pipe);
3653 temp = I915_READ(reg);
3654 temp &= ~FDI_RX_SYMBOL_LOCK;
3655 temp &= ~FDI_RX_BIT_LOCK;
3656 I915_WRITE(reg, temp);
3657
3658 POSTING_READ(reg);
3659 udelay(150);
3660
3661 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3662 I915_READ(FDI_RX_IIR(pipe)));
3663
3664 /* Try each vswing and preemphasis setting twice before moving on */
3665 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3666 /* disable first in case we need to retry */
3667 reg = FDI_TX_CTL(pipe);
3668 temp = I915_READ(reg);
3669 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3670 temp &= ~FDI_TX_ENABLE;
3671 I915_WRITE(reg, temp);
3672
3673 reg = FDI_RX_CTL(pipe);
3674 temp = I915_READ(reg);
3675 temp &= ~FDI_LINK_TRAIN_AUTO;
3676 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3677 temp &= ~FDI_RX_ENABLE;
3678 I915_WRITE(reg, temp);
3679
3680 /* enable CPU FDI TX and PCH FDI RX */
3681 reg = FDI_TX_CTL(pipe);
3682 temp = I915_READ(reg);
3683 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3684 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3685 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3686 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3687 temp |= snb_b_fdi_train_param[j/2];
3688 temp |= FDI_COMPOSITE_SYNC;
3689 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3690
3691 I915_WRITE(FDI_RX_MISC(pipe),
3692 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3693
3694 reg = FDI_RX_CTL(pipe);
3695 temp = I915_READ(reg);
3696 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3697 temp |= FDI_COMPOSITE_SYNC;
3698 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3699
3700 POSTING_READ(reg);
3701 udelay(1); /* should be 0.5us */
3702
3703 for (i = 0; i < 4; i++) {
3704 reg = FDI_RX_IIR(pipe);
3705 temp = I915_READ(reg);
3706 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3707
3708 if (temp & FDI_RX_BIT_LOCK ||
3709 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3710 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3711 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3712 i);
3713 break;
3714 }
3715 udelay(1); /* should be 0.5us */
3716 }
3717 if (i == 4) {
3718 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3719 continue;
3720 }
3721
3722 /* Train 2 */
3723 reg = FDI_TX_CTL(pipe);
3724 temp = I915_READ(reg);
3725 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3726 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3727 I915_WRITE(reg, temp);
3728
3729 reg = FDI_RX_CTL(pipe);
3730 temp = I915_READ(reg);
3731 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3732 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3733 I915_WRITE(reg, temp);
3734
3735 POSTING_READ(reg);
3736 udelay(2); /* should be 1.5us */
3737
3738 for (i = 0; i < 4; i++) {
3739 reg = FDI_RX_IIR(pipe);
3740 temp = I915_READ(reg);
3741 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3742
3743 if (temp & FDI_RX_SYMBOL_LOCK ||
3744 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3745 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3746 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3747 i);
3748 goto train_done;
3749 }
3750 udelay(2); /* should be 1.5us */
3751 }
3752 if (i == 4)
3753 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3754 }
3755
3756 train_done:
3757 DRM_DEBUG_KMS("FDI train done.\n");
3758 }
3759
3760 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3761 {
3762 struct drm_device *dev = intel_crtc->base.dev;
3763 struct drm_i915_private *dev_priv = dev->dev_private;
3764 int pipe = intel_crtc->pipe;
3765 u32 reg, temp;
3766
3767
3768 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3769 reg = FDI_RX_CTL(pipe);
3770 temp = I915_READ(reg);
3771 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3772 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3773 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3774 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3775
3776 POSTING_READ(reg);
3777 udelay(200);
3778
3779 /* Switch from Rawclk to PCDclk */
3780 temp = I915_READ(reg);
3781 I915_WRITE(reg, temp | FDI_PCDCLK);
3782
3783 POSTING_READ(reg);
3784 udelay(200);
3785
3786 /* Enable CPU FDI TX PLL, always on for Ironlake */
3787 reg = FDI_TX_CTL(pipe);
3788 temp = I915_READ(reg);
3789 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3790 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3791
3792 POSTING_READ(reg);
3793 udelay(100);
3794 }
3795 }
3796
3797 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3798 {
3799 struct drm_device *dev = intel_crtc->base.dev;
3800 struct drm_i915_private *dev_priv = dev->dev_private;
3801 int pipe = intel_crtc->pipe;
3802 u32 reg, temp;
3803
3804 /* Switch from PCDclk to Rawclk */
3805 reg = FDI_RX_CTL(pipe);
3806 temp = I915_READ(reg);
3807 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3808
3809 /* Disable CPU FDI TX PLL */
3810 reg = FDI_TX_CTL(pipe);
3811 temp = I915_READ(reg);
3812 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3813
3814 POSTING_READ(reg);
3815 udelay(100);
3816
3817 reg = FDI_RX_CTL(pipe);
3818 temp = I915_READ(reg);
3819 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3820
3821 /* Wait for the clocks to turn off. */
3822 POSTING_READ(reg);
3823 udelay(100);
3824 }
3825
3826 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3827 {
3828 struct drm_device *dev = crtc->dev;
3829 struct drm_i915_private *dev_priv = dev->dev_private;
3830 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3831 int pipe = intel_crtc->pipe;
3832 u32 reg, temp;
3833
3834 /* disable CPU FDI tx and PCH FDI rx */
3835 reg = FDI_TX_CTL(pipe);
3836 temp = I915_READ(reg);
3837 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3838 POSTING_READ(reg);
3839
3840 reg = FDI_RX_CTL(pipe);
3841 temp = I915_READ(reg);
3842 temp &= ~(0x7 << 16);
3843 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3844 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3845
3846 POSTING_READ(reg);
3847 udelay(100);
3848
3849 /* Ironlake workaround, disable clock pointer after downing FDI */
3850 if (HAS_PCH_IBX(dev))
3851 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3852
3853 /* still set train pattern 1 */
3854 reg = FDI_TX_CTL(pipe);
3855 temp = I915_READ(reg);
3856 temp &= ~FDI_LINK_TRAIN_NONE;
3857 temp |= FDI_LINK_TRAIN_PATTERN_1;
3858 I915_WRITE(reg, temp);
3859
3860 reg = FDI_RX_CTL(pipe);
3861 temp = I915_READ(reg);
3862 if (HAS_PCH_CPT(dev)) {
3863 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3864 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3865 } else {
3866 temp &= ~FDI_LINK_TRAIN_NONE;
3867 temp |= FDI_LINK_TRAIN_PATTERN_1;
3868 }
3869 /* BPC in FDI rx is consistent with that in PIPECONF */
3870 temp &= ~(0x07 << 16);
3871 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3872 I915_WRITE(reg, temp);
3873
3874 POSTING_READ(reg);
3875 udelay(100);
3876 }
3877
3878 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3879 {
3880 struct intel_crtc *crtc;
3881
3882 /* Note that we don't need to be called with mode_config.lock here
3883 * as our list of CRTC objects is static for the lifetime of the
3884 * device and so cannot disappear as we iterate. Similarly, we can
3885 * happily treat the predicates as racy, atomic checks as userspace
3886 * cannot claim and pin a new fb without at least acquring the
3887 * struct_mutex and so serialising with us.
3888 */
3889 for_each_intel_crtc(dev, crtc) {
3890 if (atomic_read(&crtc->unpin_work_count) == 0)
3891 continue;
3892
3893 if (crtc->unpin_work)
3894 intel_wait_for_vblank(dev, crtc->pipe);
3895
3896 return true;
3897 }
3898
3899 return false;
3900 }
3901
3902 static void page_flip_completed(struct intel_crtc *intel_crtc)
3903 {
3904 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3905 struct intel_unpin_work *work = intel_crtc->unpin_work;
3906
3907 /* ensure that the unpin work is consistent wrt ->pending. */
3908 smp_rmb();
3909 intel_crtc->unpin_work = NULL;
3910
3911 if (work->event)
3912 drm_send_vblank_event(intel_crtc->base.dev,
3913 intel_crtc->pipe,
3914 work->event);
3915
3916 drm_crtc_vblank_put(&intel_crtc->base);
3917
3918 wake_up_all(&dev_priv->pending_flip_queue);
3919 queue_work(dev_priv->wq, &work->work);
3920
3921 trace_i915_flip_complete(intel_crtc->plane,
3922 work->pending_flip_obj);
3923 }
3924
3925 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3926 {
3927 struct drm_device *dev = crtc->dev;
3928 struct drm_i915_private *dev_priv = dev->dev_private;
3929
3930 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3931 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3932 !intel_crtc_has_pending_flip(crtc),
3933 60*HZ) == 0)) {
3934 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3935
3936 spin_lock_irq(&dev->event_lock);
3937 if (intel_crtc->unpin_work) {
3938 WARN_ONCE(1, "Removing stuck page flip\n");
3939 page_flip_completed(intel_crtc);
3940 }
3941 spin_unlock_irq(&dev->event_lock);
3942 }
3943
3944 if (crtc->primary->fb) {
3945 mutex_lock(&dev->struct_mutex);
3946 intel_finish_fb(crtc->primary->fb);
3947 mutex_unlock(&dev->struct_mutex);
3948 }
3949 }
3950
3951 /* Program iCLKIP clock to the desired frequency */
3952 static void lpt_program_iclkip(struct drm_crtc *crtc)
3953 {
3954 struct drm_device *dev = crtc->dev;
3955 struct drm_i915_private *dev_priv = dev->dev_private;
3956 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3957 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3958 u32 temp;
3959
3960 mutex_lock(&dev_priv->sb_lock);
3961
3962 /* It is necessary to ungate the pixclk gate prior to programming
3963 * the divisors, and gate it back when it is done.
3964 */
3965 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3966
3967 /* Disable SSCCTL */
3968 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3969 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3970 SBI_SSCCTL_DISABLE,
3971 SBI_ICLK);
3972
3973 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3974 if (clock == 20000) {
3975 auxdiv = 1;
3976 divsel = 0x41;
3977 phaseinc = 0x20;
3978 } else {
3979 /* The iCLK virtual clock root frequency is in MHz,
3980 * but the adjusted_mode->crtc_clock in in KHz. To get the
3981 * divisors, it is necessary to divide one by another, so we
3982 * convert the virtual clock precision to KHz here for higher
3983 * precision.
3984 */
3985 u32 iclk_virtual_root_freq = 172800 * 1000;
3986 u32 iclk_pi_range = 64;
3987 u32 desired_divisor, msb_divisor_value, pi_value;
3988
3989 desired_divisor = (iclk_virtual_root_freq / clock);
3990 msb_divisor_value = desired_divisor / iclk_pi_range;
3991 pi_value = desired_divisor % iclk_pi_range;
3992
3993 auxdiv = 0;
3994 divsel = msb_divisor_value - 2;
3995 phaseinc = pi_value;
3996 }
3997
3998 /* This should not happen with any sane values */
3999 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4000 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4001 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4002 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4003
4004 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4005 clock,
4006 auxdiv,
4007 divsel,
4008 phasedir,
4009 phaseinc);
4010
4011 /* Program SSCDIVINTPHASE6 */
4012 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4013 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4014 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4015 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4016 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4017 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4018 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4019 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4020
4021 /* Program SSCAUXDIV */
4022 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4023 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4024 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4025 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4026
4027 /* Enable modulator and associated divider */
4028 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4029 temp &= ~SBI_SSCCTL_DISABLE;
4030 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4031
4032 /* Wait for initialization time */
4033 udelay(24);
4034
4035 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4036
4037 mutex_unlock(&dev_priv->sb_lock);
4038 }
4039
4040 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4041 enum pipe pch_transcoder)
4042 {
4043 struct drm_device *dev = crtc->base.dev;
4044 struct drm_i915_private *dev_priv = dev->dev_private;
4045 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4046
4047 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4048 I915_READ(HTOTAL(cpu_transcoder)));
4049 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4050 I915_READ(HBLANK(cpu_transcoder)));
4051 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4052 I915_READ(HSYNC(cpu_transcoder)));
4053
4054 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4055 I915_READ(VTOTAL(cpu_transcoder)));
4056 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4057 I915_READ(VBLANK(cpu_transcoder)));
4058 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4059 I915_READ(VSYNC(cpu_transcoder)));
4060 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4061 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4062 }
4063
4064 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4065 {
4066 struct drm_i915_private *dev_priv = dev->dev_private;
4067 uint32_t temp;
4068
4069 temp = I915_READ(SOUTH_CHICKEN1);
4070 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4071 return;
4072
4073 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4074 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4075
4076 temp &= ~FDI_BC_BIFURCATION_SELECT;
4077 if (enable)
4078 temp |= FDI_BC_BIFURCATION_SELECT;
4079
4080 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4081 I915_WRITE(SOUTH_CHICKEN1, temp);
4082 POSTING_READ(SOUTH_CHICKEN1);
4083 }
4084
4085 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4086 {
4087 struct drm_device *dev = intel_crtc->base.dev;
4088
4089 switch (intel_crtc->pipe) {
4090 case PIPE_A:
4091 break;
4092 case PIPE_B:
4093 if (intel_crtc->config->fdi_lanes > 2)
4094 cpt_set_fdi_bc_bifurcation(dev, false);
4095 else
4096 cpt_set_fdi_bc_bifurcation(dev, true);
4097
4098 break;
4099 case PIPE_C:
4100 cpt_set_fdi_bc_bifurcation(dev, true);
4101
4102 break;
4103 default:
4104 BUG();
4105 }
4106 }
4107
4108 /*
4109 * Enable PCH resources required for PCH ports:
4110 * - PCH PLLs
4111 * - FDI training & RX/TX
4112 * - update transcoder timings
4113 * - DP transcoding bits
4114 * - transcoder
4115 */
4116 static void ironlake_pch_enable(struct drm_crtc *crtc)
4117 {
4118 struct drm_device *dev = crtc->dev;
4119 struct drm_i915_private *dev_priv = dev->dev_private;
4120 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4121 int pipe = intel_crtc->pipe;
4122 u32 reg, temp;
4123
4124 assert_pch_transcoder_disabled(dev_priv, pipe);
4125
4126 if (IS_IVYBRIDGE(dev))
4127 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4128
4129 /* Write the TU size bits before fdi link training, so that error
4130 * detection works. */
4131 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4132 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4133
4134 /* For PCH output, training FDI link */
4135 dev_priv->display.fdi_link_train(crtc);
4136
4137 /* We need to program the right clock selection before writing the pixel
4138 * mutliplier into the DPLL. */
4139 if (HAS_PCH_CPT(dev)) {
4140 u32 sel;
4141
4142 temp = I915_READ(PCH_DPLL_SEL);
4143 temp |= TRANS_DPLL_ENABLE(pipe);
4144 sel = TRANS_DPLLB_SEL(pipe);
4145 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4146 temp |= sel;
4147 else
4148 temp &= ~sel;
4149 I915_WRITE(PCH_DPLL_SEL, temp);
4150 }
4151
4152 /* XXX: pch pll's can be enabled any time before we enable the PCH
4153 * transcoder, and we actually should do this to not upset any PCH
4154 * transcoder that already use the clock when we share it.
4155 *
4156 * Note that enable_shared_dpll tries to do the right thing, but
4157 * get_shared_dpll unconditionally resets the pll - we need that to have
4158 * the right LVDS enable sequence. */
4159 intel_enable_shared_dpll(intel_crtc);
4160
4161 /* set transcoder timing, panel must allow it */
4162 assert_panel_unlocked(dev_priv, pipe);
4163 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4164
4165 intel_fdi_normal_train(crtc);
4166
4167 /* For PCH DP, enable TRANS_DP_CTL */
4168 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4169 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4170 reg = TRANS_DP_CTL(pipe);
4171 temp = I915_READ(reg);
4172 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4173 TRANS_DP_SYNC_MASK |
4174 TRANS_DP_BPC_MASK);
4175 temp |= TRANS_DP_OUTPUT_ENABLE;
4176 temp |= bpc << 9; /* same format but at 11:9 */
4177
4178 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4179 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4180 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4181 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4182
4183 switch (intel_trans_dp_port_sel(crtc)) {
4184 case PCH_DP_B:
4185 temp |= TRANS_DP_PORT_SEL_B;
4186 break;
4187 case PCH_DP_C:
4188 temp |= TRANS_DP_PORT_SEL_C;
4189 break;
4190 case PCH_DP_D:
4191 temp |= TRANS_DP_PORT_SEL_D;
4192 break;
4193 default:
4194 BUG();
4195 }
4196
4197 I915_WRITE(reg, temp);
4198 }
4199
4200 ironlake_enable_pch_transcoder(dev_priv, pipe);
4201 }
4202
4203 static void lpt_pch_enable(struct drm_crtc *crtc)
4204 {
4205 struct drm_device *dev = crtc->dev;
4206 struct drm_i915_private *dev_priv = dev->dev_private;
4207 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4208 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4209
4210 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4211
4212 lpt_program_iclkip(crtc);
4213
4214 /* Set transcoder timing. */
4215 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4216
4217 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4218 }
4219
4220 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4221 struct intel_crtc_state *crtc_state)
4222 {
4223 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4224 struct intel_shared_dpll *pll;
4225 struct intel_shared_dpll_config *shared_dpll;
4226 enum intel_dpll_id i;
4227
4228 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4229
4230 if (HAS_PCH_IBX(dev_priv->dev)) {
4231 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4232 i = (enum intel_dpll_id) crtc->pipe;
4233 pll = &dev_priv->shared_dplls[i];
4234
4235 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4236 crtc->base.base.id, pll->name);
4237
4238 WARN_ON(shared_dpll[i].crtc_mask);
4239
4240 goto found;
4241 }
4242
4243 if (IS_BROXTON(dev_priv->dev)) {
4244 /* PLL is attached to port in bxt */
4245 struct intel_encoder *encoder;
4246 struct intel_digital_port *intel_dig_port;
4247
4248 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4249 if (WARN_ON(!encoder))
4250 return NULL;
4251
4252 intel_dig_port = enc_to_dig_port(&encoder->base);
4253 /* 1:1 mapping between ports and PLLs */
4254 i = (enum intel_dpll_id)intel_dig_port->port;
4255 pll = &dev_priv->shared_dplls[i];
4256 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4257 crtc->base.base.id, pll->name);
4258 WARN_ON(shared_dpll[i].crtc_mask);
4259
4260 goto found;
4261 }
4262
4263 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4264 pll = &dev_priv->shared_dplls[i];
4265
4266 /* Only want to check enabled timings first */
4267 if (shared_dpll[i].crtc_mask == 0)
4268 continue;
4269
4270 if (memcmp(&crtc_state->dpll_hw_state,
4271 &shared_dpll[i].hw_state,
4272 sizeof(crtc_state->dpll_hw_state)) == 0) {
4273 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4274 crtc->base.base.id, pll->name,
4275 shared_dpll[i].crtc_mask,
4276 pll->active);
4277 goto found;
4278 }
4279 }
4280
4281 /* Ok no matching timings, maybe there's a free one? */
4282 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4283 pll = &dev_priv->shared_dplls[i];
4284 if (shared_dpll[i].crtc_mask == 0) {
4285 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4286 crtc->base.base.id, pll->name);
4287 goto found;
4288 }
4289 }
4290
4291 return NULL;
4292
4293 found:
4294 if (shared_dpll[i].crtc_mask == 0)
4295 shared_dpll[i].hw_state =
4296 crtc_state->dpll_hw_state;
4297
4298 crtc_state->shared_dpll = i;
4299 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4300 pipe_name(crtc->pipe));
4301
4302 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4303
4304 return pll;
4305 }
4306
4307 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4308 {
4309 struct drm_i915_private *dev_priv = to_i915(state->dev);
4310 struct intel_shared_dpll_config *shared_dpll;
4311 struct intel_shared_dpll *pll;
4312 enum intel_dpll_id i;
4313
4314 if (!to_intel_atomic_state(state)->dpll_set)
4315 return;
4316
4317 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4318 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4319 pll = &dev_priv->shared_dplls[i];
4320 pll->config = shared_dpll[i];
4321 }
4322 }
4323
4324 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4325 {
4326 struct drm_i915_private *dev_priv = dev->dev_private;
4327 int dslreg = PIPEDSL(pipe);
4328 u32 temp;
4329
4330 temp = I915_READ(dslreg);
4331 udelay(500);
4332 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4333 if (wait_for(I915_READ(dslreg) != temp, 5))
4334 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4335 }
4336 }
4337
4338 static int
4339 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4340 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4341 int src_w, int src_h, int dst_w, int dst_h)
4342 {
4343 struct intel_crtc_scaler_state *scaler_state =
4344 &crtc_state->scaler_state;
4345 struct intel_crtc *intel_crtc =
4346 to_intel_crtc(crtc_state->base.crtc);
4347 int need_scaling;
4348
4349 need_scaling = intel_rotation_90_or_270(rotation) ?
4350 (src_h != dst_w || src_w != dst_h):
4351 (src_w != dst_w || src_h != dst_h);
4352
4353 /*
4354 * if plane is being disabled or scaler is no more required or force detach
4355 * - free scaler binded to this plane/crtc
4356 * - in order to do this, update crtc->scaler_usage
4357 *
4358 * Here scaler state in crtc_state is set free so that
4359 * scaler can be assigned to other user. Actual register
4360 * update to free the scaler is done in plane/panel-fit programming.
4361 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4362 */
4363 if (force_detach || !need_scaling) {
4364 if (*scaler_id >= 0) {
4365 scaler_state->scaler_users &= ~(1 << scaler_user);
4366 scaler_state->scalers[*scaler_id].in_use = 0;
4367
4368 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4369 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4370 intel_crtc->pipe, scaler_user, *scaler_id,
4371 scaler_state->scaler_users);
4372 *scaler_id = -1;
4373 }
4374 return 0;
4375 }
4376
4377 /* range checks */
4378 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4379 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4380
4381 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4382 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4383 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4384 "size is out of scaler range\n",
4385 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4386 return -EINVAL;
4387 }
4388
4389 /* mark this plane as a scaler user in crtc_state */
4390 scaler_state->scaler_users |= (1 << scaler_user);
4391 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4392 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4393 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4394 scaler_state->scaler_users);
4395
4396 return 0;
4397 }
4398
4399 /**
4400 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4401 *
4402 * @state: crtc's scaler state
4403 *
4404 * Return
4405 * 0 - scaler_usage updated successfully
4406 * error - requested scaling cannot be supported or other error condition
4407 */
4408 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4409 {
4410 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4411 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4412
4413 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4414 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4415
4416 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4417 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4418 state->pipe_src_w, state->pipe_src_h,
4419 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4420 }
4421
4422 /**
4423 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4424 *
4425 * @state: crtc's scaler state
4426 * @plane_state: atomic plane state to update
4427 *
4428 * Return
4429 * 0 - scaler_usage updated successfully
4430 * error - requested scaling cannot be supported or other error condition
4431 */
4432 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4433 struct intel_plane_state *plane_state)
4434 {
4435
4436 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4437 struct intel_plane *intel_plane =
4438 to_intel_plane(plane_state->base.plane);
4439 struct drm_framebuffer *fb = plane_state->base.fb;
4440 int ret;
4441
4442 bool force_detach = !fb || !plane_state->visible;
4443
4444 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4445 intel_plane->base.base.id, intel_crtc->pipe,
4446 drm_plane_index(&intel_plane->base));
4447
4448 ret = skl_update_scaler(crtc_state, force_detach,
4449 drm_plane_index(&intel_plane->base),
4450 &plane_state->scaler_id,
4451 plane_state->base.rotation,
4452 drm_rect_width(&plane_state->src) >> 16,
4453 drm_rect_height(&plane_state->src) >> 16,
4454 drm_rect_width(&plane_state->dst),
4455 drm_rect_height(&plane_state->dst));
4456
4457 if (ret || plane_state->scaler_id < 0)
4458 return ret;
4459
4460 /* check colorkey */
4461 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4462 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4463 intel_plane->base.base.id);
4464 return -EINVAL;
4465 }
4466
4467 /* Check src format */
4468 switch (fb->pixel_format) {
4469 case DRM_FORMAT_RGB565:
4470 case DRM_FORMAT_XBGR8888:
4471 case DRM_FORMAT_XRGB8888:
4472 case DRM_FORMAT_ABGR8888:
4473 case DRM_FORMAT_ARGB8888:
4474 case DRM_FORMAT_XRGB2101010:
4475 case DRM_FORMAT_XBGR2101010:
4476 case DRM_FORMAT_YUYV:
4477 case DRM_FORMAT_YVYU:
4478 case DRM_FORMAT_UYVY:
4479 case DRM_FORMAT_VYUY:
4480 break;
4481 default:
4482 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4483 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4484 return -EINVAL;
4485 }
4486
4487 return 0;
4488 }
4489
4490 static void skylake_scaler_disable(struct intel_crtc *crtc)
4491 {
4492 int i;
4493
4494 for (i = 0; i < crtc->num_scalers; i++)
4495 skl_detach_scaler(crtc, i);
4496 }
4497
4498 static void skylake_pfit_enable(struct intel_crtc *crtc)
4499 {
4500 struct drm_device *dev = crtc->base.dev;
4501 struct drm_i915_private *dev_priv = dev->dev_private;
4502 int pipe = crtc->pipe;
4503 struct intel_crtc_scaler_state *scaler_state =
4504 &crtc->config->scaler_state;
4505
4506 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4507
4508 if (crtc->config->pch_pfit.enabled) {
4509 int id;
4510
4511 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4512 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4513 return;
4514 }
4515
4516 id = scaler_state->scaler_id;
4517 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4518 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4519 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4520 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4521
4522 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4523 }
4524 }
4525
4526 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4527 {
4528 struct drm_device *dev = crtc->base.dev;
4529 struct drm_i915_private *dev_priv = dev->dev_private;
4530 int pipe = crtc->pipe;
4531
4532 if (crtc->config->pch_pfit.enabled) {
4533 /* Force use of hard-coded filter coefficients
4534 * as some pre-programmed values are broken,
4535 * e.g. x201.
4536 */
4537 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4538 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4539 PF_PIPE_SEL_IVB(pipe));
4540 else
4541 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4542 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4543 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4544 }
4545 }
4546
4547 void hsw_enable_ips(struct intel_crtc *crtc)
4548 {
4549 struct drm_device *dev = crtc->base.dev;
4550 struct drm_i915_private *dev_priv = dev->dev_private;
4551
4552 if (!crtc->config->ips_enabled)
4553 return;
4554
4555 /* We can only enable IPS after we enable a plane and wait for a vblank */
4556 intel_wait_for_vblank(dev, crtc->pipe);
4557
4558 assert_plane_enabled(dev_priv, crtc->plane);
4559 if (IS_BROADWELL(dev)) {
4560 mutex_lock(&dev_priv->rps.hw_lock);
4561 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4562 mutex_unlock(&dev_priv->rps.hw_lock);
4563 /* Quoting Art Runyan: "its not safe to expect any particular
4564 * value in IPS_CTL bit 31 after enabling IPS through the
4565 * mailbox." Moreover, the mailbox may return a bogus state,
4566 * so we need to just enable it and continue on.
4567 */
4568 } else {
4569 I915_WRITE(IPS_CTL, IPS_ENABLE);
4570 /* The bit only becomes 1 in the next vblank, so this wait here
4571 * is essentially intel_wait_for_vblank. If we don't have this
4572 * and don't wait for vblanks until the end of crtc_enable, then
4573 * the HW state readout code will complain that the expected
4574 * IPS_CTL value is not the one we read. */
4575 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4576 DRM_ERROR("Timed out waiting for IPS enable\n");
4577 }
4578 }
4579
4580 void hsw_disable_ips(struct intel_crtc *crtc)
4581 {
4582 struct drm_device *dev = crtc->base.dev;
4583 struct drm_i915_private *dev_priv = dev->dev_private;
4584
4585 if (!crtc->config->ips_enabled)
4586 return;
4587
4588 assert_plane_enabled(dev_priv, crtc->plane);
4589 if (IS_BROADWELL(dev)) {
4590 mutex_lock(&dev_priv->rps.hw_lock);
4591 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4592 mutex_unlock(&dev_priv->rps.hw_lock);
4593 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4594 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4595 DRM_ERROR("Timed out waiting for IPS disable\n");
4596 } else {
4597 I915_WRITE(IPS_CTL, 0);
4598 POSTING_READ(IPS_CTL);
4599 }
4600
4601 /* We need to wait for a vblank before we can disable the plane. */
4602 intel_wait_for_vblank(dev, crtc->pipe);
4603 }
4604
4605 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4606 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4607 {
4608 struct drm_device *dev = crtc->dev;
4609 struct drm_i915_private *dev_priv = dev->dev_private;
4610 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4611 enum pipe pipe = intel_crtc->pipe;
4612 int i;
4613 bool reenable_ips = false;
4614
4615 /* The clocks have to be on to load the palette. */
4616 if (!crtc->state->active)
4617 return;
4618
4619 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4620 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4621 assert_dsi_pll_enabled(dev_priv);
4622 else
4623 assert_pll_enabled(dev_priv, pipe);
4624 }
4625
4626 /* Workaround : Do not read or write the pipe palette/gamma data while
4627 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4628 */
4629 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4630 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4631 GAMMA_MODE_MODE_SPLIT)) {
4632 hsw_disable_ips(intel_crtc);
4633 reenable_ips = true;
4634 }
4635
4636 for (i = 0; i < 256; i++) {
4637 u32 palreg;
4638
4639 if (HAS_GMCH_DISPLAY(dev))
4640 palreg = PALETTE(pipe, i);
4641 else
4642 palreg = LGC_PALETTE(pipe, i);
4643
4644 I915_WRITE(palreg,
4645 (intel_crtc->lut_r[i] << 16) |
4646 (intel_crtc->lut_g[i] << 8) |
4647 intel_crtc->lut_b[i]);
4648 }
4649
4650 if (reenable_ips)
4651 hsw_enable_ips(intel_crtc);
4652 }
4653
4654 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4655 {
4656 if (intel_crtc->overlay) {
4657 struct drm_device *dev = intel_crtc->base.dev;
4658 struct drm_i915_private *dev_priv = dev->dev_private;
4659
4660 mutex_lock(&dev->struct_mutex);
4661 dev_priv->mm.interruptible = false;
4662 (void) intel_overlay_switch_off(intel_crtc->overlay);
4663 dev_priv->mm.interruptible = true;
4664 mutex_unlock(&dev->struct_mutex);
4665 }
4666
4667 /* Let userspace switch the overlay on again. In most cases userspace
4668 * has to recompute where to put it anyway.
4669 */
4670 }
4671
4672 /**
4673 * intel_post_enable_primary - Perform operations after enabling primary plane
4674 * @crtc: the CRTC whose primary plane was just enabled
4675 *
4676 * Performs potentially sleeping operations that must be done after the primary
4677 * plane is enabled, such as updating FBC and IPS. Note that this may be
4678 * called due to an explicit primary plane update, or due to an implicit
4679 * re-enable that is caused when a sprite plane is updated to no longer
4680 * completely hide the primary plane.
4681 */
4682 static void
4683 intel_post_enable_primary(struct drm_crtc *crtc)
4684 {
4685 struct drm_device *dev = crtc->dev;
4686 struct drm_i915_private *dev_priv = dev->dev_private;
4687 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4688 int pipe = intel_crtc->pipe;
4689
4690 /*
4691 * BDW signals flip done immediately if the plane
4692 * is disabled, even if the plane enable is already
4693 * armed to occur at the next vblank :(
4694 */
4695 if (IS_BROADWELL(dev))
4696 intel_wait_for_vblank(dev, pipe);
4697
4698 /*
4699 * FIXME IPS should be fine as long as one plane is
4700 * enabled, but in practice it seems to have problems
4701 * when going from primary only to sprite only and vice
4702 * versa.
4703 */
4704 hsw_enable_ips(intel_crtc);
4705
4706 /*
4707 * Gen2 reports pipe underruns whenever all planes are disabled.
4708 * So don't enable underrun reporting before at least some planes
4709 * are enabled.
4710 * FIXME: Need to fix the logic to work when we turn off all planes
4711 * but leave the pipe running.
4712 */
4713 if (IS_GEN2(dev))
4714 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4715
4716 /* Underruns don't raise interrupts, so check manually. */
4717 if (HAS_GMCH_DISPLAY(dev))
4718 i9xx_check_fifo_underruns(dev_priv);
4719 }
4720
4721 /**
4722 * intel_pre_disable_primary - Perform operations before disabling primary plane
4723 * @crtc: the CRTC whose primary plane is to be disabled
4724 *
4725 * Performs potentially sleeping operations that must be done before the
4726 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4727 * be called due to an explicit primary plane update, or due to an implicit
4728 * disable that is caused when a sprite plane completely hides the primary
4729 * plane.
4730 */
4731 static void
4732 intel_pre_disable_primary(struct drm_crtc *crtc)
4733 {
4734 struct drm_device *dev = crtc->dev;
4735 struct drm_i915_private *dev_priv = dev->dev_private;
4736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4737 int pipe = intel_crtc->pipe;
4738
4739 /*
4740 * Gen2 reports pipe underruns whenever all planes are disabled.
4741 * So diasble underrun reporting before all the planes get disabled.
4742 * FIXME: Need to fix the logic to work when we turn off all planes
4743 * but leave the pipe running.
4744 */
4745 if (IS_GEN2(dev))
4746 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4747
4748 /*
4749 * Vblank time updates from the shadow to live plane control register
4750 * are blocked if the memory self-refresh mode is active at that
4751 * moment. So to make sure the plane gets truly disabled, disable
4752 * first the self-refresh mode. The self-refresh enable bit in turn
4753 * will be checked/applied by the HW only at the next frame start
4754 * event which is after the vblank start event, so we need to have a
4755 * wait-for-vblank between disabling the plane and the pipe.
4756 */
4757 if (HAS_GMCH_DISPLAY(dev)) {
4758 intel_set_memory_cxsr(dev_priv, false);
4759 dev_priv->wm.vlv.cxsr = false;
4760 intel_wait_for_vblank(dev, pipe);
4761 }
4762
4763 /*
4764 * FIXME IPS should be fine as long as one plane is
4765 * enabled, but in practice it seems to have problems
4766 * when going from primary only to sprite only and vice
4767 * versa.
4768 */
4769 hsw_disable_ips(intel_crtc);
4770 }
4771
4772 static void intel_post_plane_update(struct intel_crtc *crtc)
4773 {
4774 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4775 struct drm_device *dev = crtc->base.dev;
4776 struct drm_i915_private *dev_priv = dev->dev_private;
4777 struct drm_plane *plane;
4778
4779 if (atomic->wait_vblank)
4780 intel_wait_for_vblank(dev, crtc->pipe);
4781
4782 intel_frontbuffer_flip(dev, atomic->fb_bits);
4783
4784 if (atomic->disable_cxsr)
4785 crtc->wm.cxsr_allowed = true;
4786
4787 if (crtc->atomic.update_wm_post)
4788 intel_update_watermarks(&crtc->base);
4789
4790 if (atomic->update_fbc)
4791 intel_fbc_update(dev_priv);
4792
4793 if (atomic->post_enable_primary)
4794 intel_post_enable_primary(&crtc->base);
4795
4796 drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4797 intel_update_sprite_watermarks(plane, &crtc->base,
4798 0, 0, 0, false, false);
4799
4800 memset(atomic, 0, sizeof(*atomic));
4801 }
4802
4803 static void intel_pre_plane_update(struct intel_crtc *crtc)
4804 {
4805 struct drm_device *dev = crtc->base.dev;
4806 struct drm_i915_private *dev_priv = dev->dev_private;
4807 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4808
4809 if (atomic->wait_for_flips)
4810 intel_crtc_wait_for_pending_flips(&crtc->base);
4811
4812 if (atomic->disable_fbc)
4813 intel_fbc_disable_crtc(crtc);
4814
4815 if (crtc->atomic.disable_ips)
4816 hsw_disable_ips(crtc);
4817
4818 if (atomic->pre_disable_primary)
4819 intel_pre_disable_primary(&crtc->base);
4820
4821 if (atomic->disable_cxsr) {
4822 crtc->wm.cxsr_allowed = false;
4823 intel_set_memory_cxsr(dev_priv, false);
4824 }
4825 }
4826
4827 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4828 {
4829 struct drm_device *dev = crtc->dev;
4830 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4831 struct drm_plane *p;
4832 int pipe = intel_crtc->pipe;
4833
4834 intel_crtc_dpms_overlay_disable(intel_crtc);
4835
4836 drm_for_each_plane_mask(p, dev, plane_mask)
4837 to_intel_plane(p)->disable_plane(p, crtc);
4838
4839 /*
4840 * FIXME: Once we grow proper nuclear flip support out of this we need
4841 * to compute the mask of flip planes precisely. For the time being
4842 * consider this a flip to a NULL plane.
4843 */
4844 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4845 }
4846
4847 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4848 {
4849 struct drm_device *dev = crtc->dev;
4850 struct drm_i915_private *dev_priv = dev->dev_private;
4851 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4852 struct intel_encoder *encoder;
4853 int pipe = intel_crtc->pipe;
4854
4855 if (WARN_ON(intel_crtc->active))
4856 return;
4857
4858 if (intel_crtc->config->has_pch_encoder)
4859 intel_prepare_shared_dpll(intel_crtc);
4860
4861 if (intel_crtc->config->has_dp_encoder)
4862 intel_dp_set_m_n(intel_crtc, M1_N1);
4863
4864 intel_set_pipe_timings(intel_crtc);
4865
4866 if (intel_crtc->config->has_pch_encoder) {
4867 intel_cpu_transcoder_set_m_n(intel_crtc,
4868 &intel_crtc->config->fdi_m_n, NULL);
4869 }
4870
4871 ironlake_set_pipeconf(crtc);
4872
4873 intel_crtc->active = true;
4874
4875 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4876 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4877
4878 for_each_encoder_on_crtc(dev, crtc, encoder)
4879 if (encoder->pre_enable)
4880 encoder->pre_enable(encoder);
4881
4882 if (intel_crtc->config->has_pch_encoder) {
4883 /* Note: FDI PLL enabling _must_ be done before we enable the
4884 * cpu pipes, hence this is separate from all the other fdi/pch
4885 * enabling. */
4886 ironlake_fdi_pll_enable(intel_crtc);
4887 } else {
4888 assert_fdi_tx_disabled(dev_priv, pipe);
4889 assert_fdi_rx_disabled(dev_priv, pipe);
4890 }
4891
4892 ironlake_pfit_enable(intel_crtc);
4893
4894 /*
4895 * On ILK+ LUT must be loaded before the pipe is running but with
4896 * clocks enabled
4897 */
4898 intel_crtc_load_lut(crtc);
4899
4900 intel_update_watermarks(crtc);
4901 intel_enable_pipe(intel_crtc);
4902
4903 if (intel_crtc->config->has_pch_encoder)
4904 ironlake_pch_enable(crtc);
4905
4906 assert_vblank_disabled(crtc);
4907 drm_crtc_vblank_on(crtc);
4908
4909 for_each_encoder_on_crtc(dev, crtc, encoder)
4910 encoder->enable(encoder);
4911
4912 if (HAS_PCH_CPT(dev))
4913 cpt_verify_modeset(dev, intel_crtc->pipe);
4914 }
4915
4916 /* IPS only exists on ULT machines and is tied to pipe A. */
4917 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4918 {
4919 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4920 }
4921
4922 static void haswell_crtc_enable(struct drm_crtc *crtc)
4923 {
4924 struct drm_device *dev = crtc->dev;
4925 struct drm_i915_private *dev_priv = dev->dev_private;
4926 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4927 struct intel_encoder *encoder;
4928 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4929 struct intel_crtc_state *pipe_config =
4930 to_intel_crtc_state(crtc->state);
4931 bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
4932
4933 if (WARN_ON(intel_crtc->active))
4934 return;
4935
4936 if (intel_crtc_to_shared_dpll(intel_crtc))
4937 intel_enable_shared_dpll(intel_crtc);
4938
4939 if (intel_crtc->config->has_dp_encoder)
4940 intel_dp_set_m_n(intel_crtc, M1_N1);
4941
4942 intel_set_pipe_timings(intel_crtc);
4943
4944 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4945 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4946 intel_crtc->config->pixel_multiplier - 1);
4947 }
4948
4949 if (intel_crtc->config->has_pch_encoder) {
4950 intel_cpu_transcoder_set_m_n(intel_crtc,
4951 &intel_crtc->config->fdi_m_n, NULL);
4952 }
4953
4954 haswell_set_pipeconf(crtc);
4955
4956 intel_set_pipe_csc(crtc);
4957
4958 intel_crtc->active = true;
4959
4960 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4961 for_each_encoder_on_crtc(dev, crtc, encoder) {
4962 if (encoder->pre_pll_enable)
4963 encoder->pre_pll_enable(encoder);
4964 if (encoder->pre_enable)
4965 encoder->pre_enable(encoder);
4966 }
4967
4968 if (intel_crtc->config->has_pch_encoder) {
4969 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4970 true);
4971 dev_priv->display.fdi_link_train(crtc);
4972 }
4973
4974 if (!is_dsi)
4975 intel_ddi_enable_pipe_clock(intel_crtc);
4976
4977 if (INTEL_INFO(dev)->gen >= 9)
4978 skylake_pfit_enable(intel_crtc);
4979 else
4980 ironlake_pfit_enable(intel_crtc);
4981
4982 /*
4983 * On ILK+ LUT must be loaded before the pipe is running but with
4984 * clocks enabled
4985 */
4986 intel_crtc_load_lut(crtc);
4987
4988 intel_ddi_set_pipe_settings(crtc);
4989 if (!is_dsi)
4990 intel_ddi_enable_transcoder_func(crtc);
4991
4992 intel_update_watermarks(crtc);
4993 intel_enable_pipe(intel_crtc);
4994
4995 if (intel_crtc->config->has_pch_encoder)
4996 lpt_pch_enable(crtc);
4997
4998 if (intel_crtc->config->dp_encoder_is_mst && !is_dsi)
4999 intel_ddi_set_vc_payload_alloc(crtc, true);
5000
5001 assert_vblank_disabled(crtc);
5002 drm_crtc_vblank_on(crtc);
5003
5004 for_each_encoder_on_crtc(dev, crtc, encoder) {
5005 encoder->enable(encoder);
5006 intel_opregion_notify_encoder(encoder, true);
5007 }
5008
5009 /* If we change the relative order between pipe/planes enabling, we need
5010 * to change the workaround. */
5011 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5012 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5013 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5014 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5015 }
5016 }
5017
5018 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5019 {
5020 struct drm_device *dev = crtc->base.dev;
5021 struct drm_i915_private *dev_priv = dev->dev_private;
5022 int pipe = crtc->pipe;
5023
5024 /* To avoid upsetting the power well on haswell only disable the pfit if
5025 * it's in use. The hw state code will make sure we get this right. */
5026 if (force || crtc->config->pch_pfit.enabled) {
5027 I915_WRITE(PF_CTL(pipe), 0);
5028 I915_WRITE(PF_WIN_POS(pipe), 0);
5029 I915_WRITE(PF_WIN_SZ(pipe), 0);
5030 }
5031 }
5032
5033 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5034 {
5035 struct drm_device *dev = crtc->dev;
5036 struct drm_i915_private *dev_priv = dev->dev_private;
5037 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5038 struct intel_encoder *encoder;
5039 int pipe = intel_crtc->pipe;
5040 u32 reg, temp;
5041
5042 for_each_encoder_on_crtc(dev, crtc, encoder)
5043 encoder->disable(encoder);
5044
5045 drm_crtc_vblank_off(crtc);
5046 assert_vblank_disabled(crtc);
5047
5048 if (intel_crtc->config->has_pch_encoder)
5049 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5050
5051 intel_disable_pipe(intel_crtc);
5052
5053 ironlake_pfit_disable(intel_crtc, false);
5054
5055 if (intel_crtc->config->has_pch_encoder)
5056 ironlake_fdi_disable(crtc);
5057
5058 for_each_encoder_on_crtc(dev, crtc, encoder)
5059 if (encoder->post_disable)
5060 encoder->post_disable(encoder);
5061
5062 if (intel_crtc->config->has_pch_encoder) {
5063 ironlake_disable_pch_transcoder(dev_priv, pipe);
5064
5065 if (HAS_PCH_CPT(dev)) {
5066 /* disable TRANS_DP_CTL */
5067 reg = TRANS_DP_CTL(pipe);
5068 temp = I915_READ(reg);
5069 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5070 TRANS_DP_PORT_SEL_MASK);
5071 temp |= TRANS_DP_PORT_SEL_NONE;
5072 I915_WRITE(reg, temp);
5073
5074 /* disable DPLL_SEL */
5075 temp = I915_READ(PCH_DPLL_SEL);
5076 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5077 I915_WRITE(PCH_DPLL_SEL, temp);
5078 }
5079
5080 ironlake_fdi_pll_disable(intel_crtc);
5081 }
5082 }
5083
5084 static void haswell_crtc_disable(struct drm_crtc *crtc)
5085 {
5086 struct drm_device *dev = crtc->dev;
5087 struct drm_i915_private *dev_priv = dev->dev_private;
5088 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5089 struct intel_encoder *encoder;
5090 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5091 bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5092
5093 for_each_encoder_on_crtc(dev, crtc, encoder) {
5094 intel_opregion_notify_encoder(encoder, false);
5095 encoder->disable(encoder);
5096 }
5097
5098 drm_crtc_vblank_off(crtc);
5099 assert_vblank_disabled(crtc);
5100
5101 if (intel_crtc->config->has_pch_encoder)
5102 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5103 false);
5104 intel_disable_pipe(intel_crtc);
5105
5106 if (intel_crtc->config->dp_encoder_is_mst)
5107 intel_ddi_set_vc_payload_alloc(crtc, false);
5108
5109 if (!is_dsi)
5110 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5111
5112 if (INTEL_INFO(dev)->gen >= 9)
5113 skylake_scaler_disable(intel_crtc);
5114 else
5115 ironlake_pfit_disable(intel_crtc, false);
5116
5117 if (!is_dsi)
5118 intel_ddi_disable_pipe_clock(intel_crtc);
5119
5120 if (intel_crtc->config->has_pch_encoder) {
5121 lpt_disable_pch_transcoder(dev_priv);
5122 intel_ddi_fdi_disable(crtc);
5123 }
5124
5125 for_each_encoder_on_crtc(dev, crtc, encoder)
5126 if (encoder->post_disable)
5127 encoder->post_disable(encoder);
5128 }
5129
5130 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5131 {
5132 struct drm_device *dev = crtc->base.dev;
5133 struct drm_i915_private *dev_priv = dev->dev_private;
5134 struct intel_crtc_state *pipe_config = crtc->config;
5135
5136 if (!pipe_config->gmch_pfit.control)
5137 return;
5138
5139 /*
5140 * The panel fitter should only be adjusted whilst the pipe is disabled,
5141 * according to register description and PRM.
5142 */
5143 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5144 assert_pipe_disabled(dev_priv, crtc->pipe);
5145
5146 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5147 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5148
5149 /* Border color in case we don't scale up to the full screen. Black by
5150 * default, change to something else for debugging. */
5151 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5152 }
5153
5154 static enum intel_display_power_domain port_to_power_domain(enum port port)
5155 {
5156 switch (port) {
5157 case PORT_A:
5158 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5159 case PORT_B:
5160 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5161 case PORT_C:
5162 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5163 case PORT_D:
5164 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5165 case PORT_E:
5166 return POWER_DOMAIN_PORT_DDI_E_2_LANES;
5167 default:
5168 WARN_ON_ONCE(1);
5169 return POWER_DOMAIN_PORT_OTHER;
5170 }
5171 }
5172
5173 #define for_each_power_domain(domain, mask) \
5174 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5175 if ((1 << (domain)) & (mask))
5176
5177 enum intel_display_power_domain
5178 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5179 {
5180 struct drm_device *dev = intel_encoder->base.dev;
5181 struct intel_digital_port *intel_dig_port;
5182
5183 switch (intel_encoder->type) {
5184 case INTEL_OUTPUT_UNKNOWN:
5185 /* Only DDI platforms should ever use this output type */
5186 WARN_ON_ONCE(!HAS_DDI(dev));
5187 case INTEL_OUTPUT_DISPLAYPORT:
5188 case INTEL_OUTPUT_HDMI:
5189 case INTEL_OUTPUT_EDP:
5190 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5191 return port_to_power_domain(intel_dig_port->port);
5192 case INTEL_OUTPUT_DP_MST:
5193 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5194 return port_to_power_domain(intel_dig_port->port);
5195 case INTEL_OUTPUT_ANALOG:
5196 return POWER_DOMAIN_PORT_CRT;
5197 case INTEL_OUTPUT_DSI:
5198 return POWER_DOMAIN_PORT_DSI;
5199 default:
5200 return POWER_DOMAIN_PORT_OTHER;
5201 }
5202 }
5203
5204 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5205 {
5206 struct drm_device *dev = crtc->dev;
5207 struct intel_encoder *intel_encoder;
5208 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5209 enum pipe pipe = intel_crtc->pipe;
5210 unsigned long mask;
5211 enum transcoder transcoder;
5212
5213 if (!crtc->state->active)
5214 return 0;
5215
5216 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5217
5218 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5219 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5220 if (intel_crtc->config->pch_pfit.enabled ||
5221 intel_crtc->config->pch_pfit.force_thru)
5222 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5223
5224 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5225 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5226
5227 return mask;
5228 }
5229
5230 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5231 {
5232 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5233 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5234 enum intel_display_power_domain domain;
5235 unsigned long domains, new_domains, old_domains;
5236
5237 old_domains = intel_crtc->enabled_power_domains;
5238 intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5239
5240 domains = new_domains & ~old_domains;
5241
5242 for_each_power_domain(domain, domains)
5243 intel_display_power_get(dev_priv, domain);
5244
5245 return old_domains & ~new_domains;
5246 }
5247
5248 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5249 unsigned long domains)
5250 {
5251 enum intel_display_power_domain domain;
5252
5253 for_each_power_domain(domain, domains)
5254 intel_display_power_put(dev_priv, domain);
5255 }
5256
5257 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5258 {
5259 struct drm_device *dev = state->dev;
5260 struct drm_i915_private *dev_priv = dev->dev_private;
5261 unsigned long put_domains[I915_MAX_PIPES] = {};
5262 struct drm_crtc_state *crtc_state;
5263 struct drm_crtc *crtc;
5264 int i;
5265
5266 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5267 if (needs_modeset(crtc->state))
5268 put_domains[to_intel_crtc(crtc)->pipe] =
5269 modeset_get_crtc_power_domains(crtc);
5270 }
5271
5272 if (dev_priv->display.modeset_commit_cdclk) {
5273 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5274
5275 if (cdclk != dev_priv->cdclk_freq &&
5276 !WARN_ON(!state->allow_modeset))
5277 dev_priv->display.modeset_commit_cdclk(state);
5278 }
5279
5280 for (i = 0; i < I915_MAX_PIPES; i++)
5281 if (put_domains[i])
5282 modeset_put_power_domains(dev_priv, put_domains[i]);
5283 }
5284
5285 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5286 {
5287 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5288
5289 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5290 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5291 return max_cdclk_freq;
5292 else if (IS_CHERRYVIEW(dev_priv))
5293 return max_cdclk_freq*95/100;
5294 else if (INTEL_INFO(dev_priv)->gen < 4)
5295 return 2*max_cdclk_freq*90/100;
5296 else
5297 return max_cdclk_freq*90/100;
5298 }
5299
5300 static void intel_update_max_cdclk(struct drm_device *dev)
5301 {
5302 struct drm_i915_private *dev_priv = dev->dev_private;
5303
5304 if (IS_SKYLAKE(dev)) {
5305 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5306
5307 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5308 dev_priv->max_cdclk_freq = 675000;
5309 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5310 dev_priv->max_cdclk_freq = 540000;
5311 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5312 dev_priv->max_cdclk_freq = 450000;
5313 else
5314 dev_priv->max_cdclk_freq = 337500;
5315 } else if (IS_BROADWELL(dev)) {
5316 /*
5317 * FIXME with extra cooling we can allow
5318 * 540 MHz for ULX and 675 Mhz for ULT.
5319 * How can we know if extra cooling is
5320 * available? PCI ID, VTB, something else?
5321 */
5322 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5323 dev_priv->max_cdclk_freq = 450000;
5324 else if (IS_BDW_ULX(dev))
5325 dev_priv->max_cdclk_freq = 450000;
5326 else if (IS_BDW_ULT(dev))
5327 dev_priv->max_cdclk_freq = 540000;
5328 else
5329 dev_priv->max_cdclk_freq = 675000;
5330 } else if (IS_CHERRYVIEW(dev)) {
5331 dev_priv->max_cdclk_freq = 320000;
5332 } else if (IS_VALLEYVIEW(dev)) {
5333 dev_priv->max_cdclk_freq = 400000;
5334 } else {
5335 /* otherwise assume cdclk is fixed */
5336 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5337 }
5338
5339 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5340
5341 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5342 dev_priv->max_cdclk_freq);
5343
5344 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5345 dev_priv->max_dotclk_freq);
5346 }
5347
5348 static void intel_update_cdclk(struct drm_device *dev)
5349 {
5350 struct drm_i915_private *dev_priv = dev->dev_private;
5351
5352 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5353 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5354 dev_priv->cdclk_freq);
5355
5356 /*
5357 * Program the gmbus_freq based on the cdclk frequency.
5358 * BSpec erroneously claims we should aim for 4MHz, but
5359 * in fact 1MHz is the correct frequency.
5360 */
5361 if (IS_VALLEYVIEW(dev)) {
5362 /*
5363 * Program the gmbus_freq based on the cdclk frequency.
5364 * BSpec erroneously claims we should aim for 4MHz, but
5365 * in fact 1MHz is the correct frequency.
5366 */
5367 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5368 }
5369
5370 if (dev_priv->max_cdclk_freq == 0)
5371 intel_update_max_cdclk(dev);
5372 }
5373
5374 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5375 {
5376 struct drm_i915_private *dev_priv = dev->dev_private;
5377 uint32_t divider;
5378 uint32_t ratio;
5379 uint32_t current_freq;
5380 int ret;
5381
5382 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5383 switch (frequency) {
5384 case 144000:
5385 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5386 ratio = BXT_DE_PLL_RATIO(60);
5387 break;
5388 case 288000:
5389 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5390 ratio = BXT_DE_PLL_RATIO(60);
5391 break;
5392 case 384000:
5393 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5394 ratio = BXT_DE_PLL_RATIO(60);
5395 break;
5396 case 576000:
5397 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5398 ratio = BXT_DE_PLL_RATIO(60);
5399 break;
5400 case 624000:
5401 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5402 ratio = BXT_DE_PLL_RATIO(65);
5403 break;
5404 case 19200:
5405 /*
5406 * Bypass frequency with DE PLL disabled. Init ratio, divider
5407 * to suppress GCC warning.
5408 */
5409 ratio = 0;
5410 divider = 0;
5411 break;
5412 default:
5413 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5414
5415 return;
5416 }
5417
5418 mutex_lock(&dev_priv->rps.hw_lock);
5419 /* Inform power controller of upcoming frequency change */
5420 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5421 0x80000000);
5422 mutex_unlock(&dev_priv->rps.hw_lock);
5423
5424 if (ret) {
5425 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5426 ret, frequency);
5427 return;
5428 }
5429
5430 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5431 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5432 current_freq = current_freq * 500 + 1000;
5433
5434 /*
5435 * DE PLL has to be disabled when
5436 * - setting to 19.2MHz (bypass, PLL isn't used)
5437 * - before setting to 624MHz (PLL needs toggling)
5438 * - before setting to any frequency from 624MHz (PLL needs toggling)
5439 */
5440 if (frequency == 19200 || frequency == 624000 ||
5441 current_freq == 624000) {
5442 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5443 /* Timeout 200us */
5444 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5445 1))
5446 DRM_ERROR("timout waiting for DE PLL unlock\n");
5447 }
5448
5449 if (frequency != 19200) {
5450 uint32_t val;
5451
5452 val = I915_READ(BXT_DE_PLL_CTL);
5453 val &= ~BXT_DE_PLL_RATIO_MASK;
5454 val |= ratio;
5455 I915_WRITE(BXT_DE_PLL_CTL, val);
5456
5457 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5458 /* Timeout 200us */
5459 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5460 DRM_ERROR("timeout waiting for DE PLL lock\n");
5461
5462 val = I915_READ(CDCLK_CTL);
5463 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5464 val |= divider;
5465 /*
5466 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5467 * enable otherwise.
5468 */
5469 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5470 if (frequency >= 500000)
5471 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5472
5473 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5474 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5475 val |= (frequency - 1000) / 500;
5476 I915_WRITE(CDCLK_CTL, val);
5477 }
5478
5479 mutex_lock(&dev_priv->rps.hw_lock);
5480 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5481 DIV_ROUND_UP(frequency, 25000));
5482 mutex_unlock(&dev_priv->rps.hw_lock);
5483
5484 if (ret) {
5485 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5486 ret, frequency);
5487 return;
5488 }
5489
5490 intel_update_cdclk(dev);
5491 }
5492
5493 void broxton_init_cdclk(struct drm_device *dev)
5494 {
5495 struct drm_i915_private *dev_priv = dev->dev_private;
5496 uint32_t val;
5497
5498 /*
5499 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5500 * or else the reset will hang because there is no PCH to respond.
5501 * Move the handshake programming to initialization sequence.
5502 * Previously was left up to BIOS.
5503 */
5504 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5505 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5506 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5507
5508 /* Enable PG1 for cdclk */
5509 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5510
5511 /* check if cd clock is enabled */
5512 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5513 DRM_DEBUG_KMS("Display already initialized\n");
5514 return;
5515 }
5516
5517 /*
5518 * FIXME:
5519 * - The initial CDCLK needs to be read from VBT.
5520 * Need to make this change after VBT has changes for BXT.
5521 * - check if setting the max (or any) cdclk freq is really necessary
5522 * here, it belongs to modeset time
5523 */
5524 broxton_set_cdclk(dev, 624000);
5525
5526 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5527 POSTING_READ(DBUF_CTL);
5528
5529 udelay(10);
5530
5531 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5532 DRM_ERROR("DBuf power enable timeout!\n");
5533 }
5534
5535 void broxton_uninit_cdclk(struct drm_device *dev)
5536 {
5537 struct drm_i915_private *dev_priv = dev->dev_private;
5538
5539 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5540 POSTING_READ(DBUF_CTL);
5541
5542 udelay(10);
5543
5544 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5545 DRM_ERROR("DBuf power disable timeout!\n");
5546
5547 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5548 broxton_set_cdclk(dev, 19200);
5549
5550 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5551 }
5552
5553 static const struct skl_cdclk_entry {
5554 unsigned int freq;
5555 unsigned int vco;
5556 } skl_cdclk_frequencies[] = {
5557 { .freq = 308570, .vco = 8640 },
5558 { .freq = 337500, .vco = 8100 },
5559 { .freq = 432000, .vco = 8640 },
5560 { .freq = 450000, .vco = 8100 },
5561 { .freq = 540000, .vco = 8100 },
5562 { .freq = 617140, .vco = 8640 },
5563 { .freq = 675000, .vco = 8100 },
5564 };
5565
5566 static unsigned int skl_cdclk_decimal(unsigned int freq)
5567 {
5568 return (freq - 1000) / 500;
5569 }
5570
5571 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5572 {
5573 unsigned int i;
5574
5575 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5576 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5577
5578 if (e->freq == freq)
5579 return e->vco;
5580 }
5581
5582 return 8100;
5583 }
5584
5585 static void
5586 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5587 {
5588 unsigned int min_freq;
5589 u32 val;
5590
5591 /* select the minimum CDCLK before enabling DPLL 0 */
5592 val = I915_READ(CDCLK_CTL);
5593 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5594 val |= CDCLK_FREQ_337_308;
5595
5596 if (required_vco == 8640)
5597 min_freq = 308570;
5598 else
5599 min_freq = 337500;
5600
5601 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5602
5603 I915_WRITE(CDCLK_CTL, val);
5604 POSTING_READ(CDCLK_CTL);
5605
5606 /*
5607 * We always enable DPLL0 with the lowest link rate possible, but still
5608 * taking into account the VCO required to operate the eDP panel at the
5609 * desired frequency. The usual DP link rates operate with a VCO of
5610 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5611 * The modeset code is responsible for the selection of the exact link
5612 * rate later on, with the constraint of choosing a frequency that
5613 * works with required_vco.
5614 */
5615 val = I915_READ(DPLL_CTRL1);
5616
5617 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5618 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5619 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5620 if (required_vco == 8640)
5621 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5622 SKL_DPLL0);
5623 else
5624 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5625 SKL_DPLL0);
5626
5627 I915_WRITE(DPLL_CTRL1, val);
5628 POSTING_READ(DPLL_CTRL1);
5629
5630 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5631
5632 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5633 DRM_ERROR("DPLL0 not locked\n");
5634 }
5635
5636 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5637 {
5638 int ret;
5639 u32 val;
5640
5641 /* inform PCU we want to change CDCLK */
5642 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5643 mutex_lock(&dev_priv->rps.hw_lock);
5644 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5645 mutex_unlock(&dev_priv->rps.hw_lock);
5646
5647 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5648 }
5649
5650 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5651 {
5652 unsigned int i;
5653
5654 for (i = 0; i < 15; i++) {
5655 if (skl_cdclk_pcu_ready(dev_priv))
5656 return true;
5657 udelay(10);
5658 }
5659
5660 return false;
5661 }
5662
5663 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5664 {
5665 struct drm_device *dev = dev_priv->dev;
5666 u32 freq_select, pcu_ack;
5667
5668 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5669
5670 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5671 DRM_ERROR("failed to inform PCU about cdclk change\n");
5672 return;
5673 }
5674
5675 /* set CDCLK_CTL */
5676 switch(freq) {
5677 case 450000:
5678 case 432000:
5679 freq_select = CDCLK_FREQ_450_432;
5680 pcu_ack = 1;
5681 break;
5682 case 540000:
5683 freq_select = CDCLK_FREQ_540;
5684 pcu_ack = 2;
5685 break;
5686 case 308570:
5687 case 337500:
5688 default:
5689 freq_select = CDCLK_FREQ_337_308;
5690 pcu_ack = 0;
5691 break;
5692 case 617140:
5693 case 675000:
5694 freq_select = CDCLK_FREQ_675_617;
5695 pcu_ack = 3;
5696 break;
5697 }
5698
5699 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5700 POSTING_READ(CDCLK_CTL);
5701
5702 /* inform PCU of the change */
5703 mutex_lock(&dev_priv->rps.hw_lock);
5704 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5705 mutex_unlock(&dev_priv->rps.hw_lock);
5706
5707 intel_update_cdclk(dev);
5708 }
5709
5710 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5711 {
5712 /* disable DBUF power */
5713 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5714 POSTING_READ(DBUF_CTL);
5715
5716 udelay(10);
5717
5718 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5719 DRM_ERROR("DBuf power disable timeout\n");
5720
5721 /*
5722 * DMC assumes ownership of LCPLL and will get confused if we touch it.
5723 */
5724 if (dev_priv->csr.dmc_payload) {
5725 /* disable DPLL0 */
5726 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) &
5727 ~LCPLL_PLL_ENABLE);
5728 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5729 DRM_ERROR("Couldn't disable DPLL0\n");
5730 }
5731
5732 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5733 }
5734
5735 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5736 {
5737 u32 val;
5738 unsigned int required_vco;
5739
5740 /* enable PCH reset handshake */
5741 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5742 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5743
5744 /* enable PG1 and Misc I/O */
5745 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5746
5747 /* DPLL0 not enabled (happens on early BIOS versions) */
5748 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5749 /* enable DPLL0 */
5750 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5751 skl_dpll0_enable(dev_priv, required_vco);
5752 }
5753
5754 /* set CDCLK to the frequency the BIOS chose */
5755 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5756
5757 /* enable DBUF power */
5758 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5759 POSTING_READ(DBUF_CTL);
5760
5761 udelay(10);
5762
5763 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5764 DRM_ERROR("DBuf power enable timeout\n");
5765 }
5766
5767 /* Adjust CDclk dividers to allow high res or save power if possible */
5768 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5769 {
5770 struct drm_i915_private *dev_priv = dev->dev_private;
5771 u32 val, cmd;
5772
5773 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5774 != dev_priv->cdclk_freq);
5775
5776 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5777 cmd = 2;
5778 else if (cdclk == 266667)
5779 cmd = 1;
5780 else
5781 cmd = 0;
5782
5783 mutex_lock(&dev_priv->rps.hw_lock);
5784 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5785 val &= ~DSPFREQGUAR_MASK;
5786 val |= (cmd << DSPFREQGUAR_SHIFT);
5787 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5788 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5789 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5790 50)) {
5791 DRM_ERROR("timed out waiting for CDclk change\n");
5792 }
5793 mutex_unlock(&dev_priv->rps.hw_lock);
5794
5795 mutex_lock(&dev_priv->sb_lock);
5796
5797 if (cdclk == 400000) {
5798 u32 divider;
5799
5800 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5801
5802 /* adjust cdclk divider */
5803 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5804 val &= ~CCK_FREQUENCY_VALUES;
5805 val |= divider;
5806 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5807
5808 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5809 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5810 50))
5811 DRM_ERROR("timed out waiting for CDclk change\n");
5812 }
5813
5814 /* adjust self-refresh exit latency value */
5815 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5816 val &= ~0x7f;
5817
5818 /*
5819 * For high bandwidth configs, we set a higher latency in the bunit
5820 * so that the core display fetch happens in time to avoid underruns.
5821 */
5822 if (cdclk == 400000)
5823 val |= 4500 / 250; /* 4.5 usec */
5824 else
5825 val |= 3000 / 250; /* 3.0 usec */
5826 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5827
5828 mutex_unlock(&dev_priv->sb_lock);
5829
5830 intel_update_cdclk(dev);
5831 }
5832
5833 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5834 {
5835 struct drm_i915_private *dev_priv = dev->dev_private;
5836 u32 val, cmd;
5837
5838 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5839 != dev_priv->cdclk_freq);
5840
5841 switch (cdclk) {
5842 case 333333:
5843 case 320000:
5844 case 266667:
5845 case 200000:
5846 break;
5847 default:
5848 MISSING_CASE(cdclk);
5849 return;
5850 }
5851
5852 /*
5853 * Specs are full of misinformation, but testing on actual
5854 * hardware has shown that we just need to write the desired
5855 * CCK divider into the Punit register.
5856 */
5857 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5858
5859 mutex_lock(&dev_priv->rps.hw_lock);
5860 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5861 val &= ~DSPFREQGUAR_MASK_CHV;
5862 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5863 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5864 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5865 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5866 50)) {
5867 DRM_ERROR("timed out waiting for CDclk change\n");
5868 }
5869 mutex_unlock(&dev_priv->rps.hw_lock);
5870
5871 intel_update_cdclk(dev);
5872 }
5873
5874 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5875 int max_pixclk)
5876 {
5877 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5878 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5879
5880 /*
5881 * Really only a few cases to deal with, as only 4 CDclks are supported:
5882 * 200MHz
5883 * 267MHz
5884 * 320/333MHz (depends on HPLL freq)
5885 * 400MHz (VLV only)
5886 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5887 * of the lower bin and adjust if needed.
5888 *
5889 * We seem to get an unstable or solid color picture at 200MHz.
5890 * Not sure what's wrong. For now use 200MHz only when all pipes
5891 * are off.
5892 */
5893 if (!IS_CHERRYVIEW(dev_priv) &&
5894 max_pixclk > freq_320*limit/100)
5895 return 400000;
5896 else if (max_pixclk > 266667*limit/100)
5897 return freq_320;
5898 else if (max_pixclk > 0)
5899 return 266667;
5900 else
5901 return 200000;
5902 }
5903
5904 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5905 int max_pixclk)
5906 {
5907 /*
5908 * FIXME:
5909 * - remove the guardband, it's not needed on BXT
5910 * - set 19.2MHz bypass frequency if there are no active pipes
5911 */
5912 if (max_pixclk > 576000*9/10)
5913 return 624000;
5914 else if (max_pixclk > 384000*9/10)
5915 return 576000;
5916 else if (max_pixclk > 288000*9/10)
5917 return 384000;
5918 else if (max_pixclk > 144000*9/10)
5919 return 288000;
5920 else
5921 return 144000;
5922 }
5923
5924 /* Compute the max pixel clock for new configuration. Uses atomic state if
5925 * that's non-NULL, look at current state otherwise. */
5926 static int intel_mode_max_pixclk(struct drm_device *dev,
5927 struct drm_atomic_state *state)
5928 {
5929 struct intel_crtc *intel_crtc;
5930 struct intel_crtc_state *crtc_state;
5931 int max_pixclk = 0;
5932
5933 for_each_intel_crtc(dev, intel_crtc) {
5934 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5935 if (IS_ERR(crtc_state))
5936 return PTR_ERR(crtc_state);
5937
5938 if (!crtc_state->base.enable)
5939 continue;
5940
5941 max_pixclk = max(max_pixclk,
5942 crtc_state->base.adjusted_mode.crtc_clock);
5943 }
5944
5945 return max_pixclk;
5946 }
5947
5948 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5949 {
5950 struct drm_device *dev = state->dev;
5951 struct drm_i915_private *dev_priv = dev->dev_private;
5952 int max_pixclk = intel_mode_max_pixclk(dev, state);
5953
5954 if (max_pixclk < 0)
5955 return max_pixclk;
5956
5957 to_intel_atomic_state(state)->cdclk =
5958 valleyview_calc_cdclk(dev_priv, max_pixclk);
5959
5960 return 0;
5961 }
5962
5963 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5964 {
5965 struct drm_device *dev = state->dev;
5966 struct drm_i915_private *dev_priv = dev->dev_private;
5967 int max_pixclk = intel_mode_max_pixclk(dev, state);
5968
5969 if (max_pixclk < 0)
5970 return max_pixclk;
5971
5972 to_intel_atomic_state(state)->cdclk =
5973 broxton_calc_cdclk(dev_priv, max_pixclk);
5974
5975 return 0;
5976 }
5977
5978 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5979 {
5980 unsigned int credits, default_credits;
5981
5982 if (IS_CHERRYVIEW(dev_priv))
5983 default_credits = PFI_CREDIT(12);
5984 else
5985 default_credits = PFI_CREDIT(8);
5986
5987 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
5988 /* CHV suggested value is 31 or 63 */
5989 if (IS_CHERRYVIEW(dev_priv))
5990 credits = PFI_CREDIT_63;
5991 else
5992 credits = PFI_CREDIT(15);
5993 } else {
5994 credits = default_credits;
5995 }
5996
5997 /*
5998 * WA - write default credits before re-programming
5999 * FIXME: should we also set the resend bit here?
6000 */
6001 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6002 default_credits);
6003
6004 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6005 credits | PFI_CREDIT_RESEND);
6006
6007 /*
6008 * FIXME is this guaranteed to clear
6009 * immediately or should we poll for it?
6010 */
6011 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6012 }
6013
6014 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6015 {
6016 struct drm_device *dev = old_state->dev;
6017 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
6018 struct drm_i915_private *dev_priv = dev->dev_private;
6019
6020 /*
6021 * FIXME: We can end up here with all power domains off, yet
6022 * with a CDCLK frequency other than the minimum. To account
6023 * for this take the PIPE-A power domain, which covers the HW
6024 * blocks needed for the following programming. This can be
6025 * removed once it's guaranteed that we get here either with
6026 * the minimum CDCLK set, or the required power domains
6027 * enabled.
6028 */
6029 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6030
6031 if (IS_CHERRYVIEW(dev))
6032 cherryview_set_cdclk(dev, req_cdclk);
6033 else
6034 valleyview_set_cdclk(dev, req_cdclk);
6035
6036 vlv_program_pfi_credits(dev_priv);
6037
6038 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6039 }
6040
6041 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6042 {
6043 struct drm_device *dev = crtc->dev;
6044 struct drm_i915_private *dev_priv = to_i915(dev);
6045 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6046 struct intel_encoder *encoder;
6047 int pipe = intel_crtc->pipe;
6048 bool is_dsi;
6049
6050 if (WARN_ON(intel_crtc->active))
6051 return;
6052
6053 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6054
6055 if (intel_crtc->config->has_dp_encoder)
6056 intel_dp_set_m_n(intel_crtc, M1_N1);
6057
6058 intel_set_pipe_timings(intel_crtc);
6059
6060 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6061 struct drm_i915_private *dev_priv = dev->dev_private;
6062
6063 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6064 I915_WRITE(CHV_CANVAS(pipe), 0);
6065 }
6066
6067 i9xx_set_pipeconf(intel_crtc);
6068
6069 intel_crtc->active = true;
6070
6071 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6072
6073 for_each_encoder_on_crtc(dev, crtc, encoder)
6074 if (encoder->pre_pll_enable)
6075 encoder->pre_pll_enable(encoder);
6076
6077 if (!is_dsi) {
6078 if (IS_CHERRYVIEW(dev)) {
6079 chv_prepare_pll(intel_crtc, intel_crtc->config);
6080 chv_enable_pll(intel_crtc, intel_crtc->config);
6081 } else {
6082 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6083 vlv_enable_pll(intel_crtc, intel_crtc->config);
6084 }
6085 }
6086
6087 for_each_encoder_on_crtc(dev, crtc, encoder)
6088 if (encoder->pre_enable)
6089 encoder->pre_enable(encoder);
6090
6091 i9xx_pfit_enable(intel_crtc);
6092
6093 intel_crtc_load_lut(crtc);
6094
6095 intel_enable_pipe(intel_crtc);
6096
6097 assert_vblank_disabled(crtc);
6098 drm_crtc_vblank_on(crtc);
6099
6100 for_each_encoder_on_crtc(dev, crtc, encoder)
6101 encoder->enable(encoder);
6102 }
6103
6104 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6105 {
6106 struct drm_device *dev = crtc->base.dev;
6107 struct drm_i915_private *dev_priv = dev->dev_private;
6108
6109 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6110 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6111 }
6112
6113 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6114 {
6115 struct drm_device *dev = crtc->dev;
6116 struct drm_i915_private *dev_priv = to_i915(dev);
6117 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6118 struct intel_encoder *encoder;
6119 int pipe = intel_crtc->pipe;
6120
6121 if (WARN_ON(intel_crtc->active))
6122 return;
6123
6124 i9xx_set_pll_dividers(intel_crtc);
6125
6126 if (intel_crtc->config->has_dp_encoder)
6127 intel_dp_set_m_n(intel_crtc, M1_N1);
6128
6129 intel_set_pipe_timings(intel_crtc);
6130
6131 i9xx_set_pipeconf(intel_crtc);
6132
6133 intel_crtc->active = true;
6134
6135 if (!IS_GEN2(dev))
6136 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6137
6138 for_each_encoder_on_crtc(dev, crtc, encoder)
6139 if (encoder->pre_enable)
6140 encoder->pre_enable(encoder);
6141
6142 i9xx_enable_pll(intel_crtc);
6143
6144 i9xx_pfit_enable(intel_crtc);
6145
6146 intel_crtc_load_lut(crtc);
6147
6148 intel_update_watermarks(crtc);
6149 intel_enable_pipe(intel_crtc);
6150
6151 assert_vblank_disabled(crtc);
6152 drm_crtc_vblank_on(crtc);
6153
6154 for_each_encoder_on_crtc(dev, crtc, encoder)
6155 encoder->enable(encoder);
6156 }
6157
6158 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6159 {
6160 struct drm_device *dev = crtc->base.dev;
6161 struct drm_i915_private *dev_priv = dev->dev_private;
6162
6163 if (!crtc->config->gmch_pfit.control)
6164 return;
6165
6166 assert_pipe_disabled(dev_priv, crtc->pipe);
6167
6168 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6169 I915_READ(PFIT_CONTROL));
6170 I915_WRITE(PFIT_CONTROL, 0);
6171 }
6172
6173 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6174 {
6175 struct drm_device *dev = crtc->dev;
6176 struct drm_i915_private *dev_priv = dev->dev_private;
6177 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6178 struct intel_encoder *encoder;
6179 int pipe = intel_crtc->pipe;
6180
6181 /*
6182 * On gen2 planes are double buffered but the pipe isn't, so we must
6183 * wait for planes to fully turn off before disabling the pipe.
6184 * We also need to wait on all gmch platforms because of the
6185 * self-refresh mode constraint explained above.
6186 */
6187 intel_wait_for_vblank(dev, pipe);
6188
6189 for_each_encoder_on_crtc(dev, crtc, encoder)
6190 encoder->disable(encoder);
6191
6192 drm_crtc_vblank_off(crtc);
6193 assert_vblank_disabled(crtc);
6194
6195 intel_disable_pipe(intel_crtc);
6196
6197 i9xx_pfit_disable(intel_crtc);
6198
6199 for_each_encoder_on_crtc(dev, crtc, encoder)
6200 if (encoder->post_disable)
6201 encoder->post_disable(encoder);
6202
6203 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6204 if (IS_CHERRYVIEW(dev))
6205 chv_disable_pll(dev_priv, pipe);
6206 else if (IS_VALLEYVIEW(dev))
6207 vlv_disable_pll(dev_priv, pipe);
6208 else
6209 i9xx_disable_pll(intel_crtc);
6210 }
6211
6212 for_each_encoder_on_crtc(dev, crtc, encoder)
6213 if (encoder->post_pll_disable)
6214 encoder->post_pll_disable(encoder);
6215
6216 if (!IS_GEN2(dev))
6217 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6218 }
6219
6220 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6221 {
6222 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6223 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6224 enum intel_display_power_domain domain;
6225 unsigned long domains;
6226
6227 if (!intel_crtc->active)
6228 return;
6229
6230 if (to_intel_plane_state(crtc->primary->state)->visible) {
6231 intel_crtc_wait_for_pending_flips(crtc);
6232 intel_pre_disable_primary(crtc);
6233 }
6234
6235 intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
6236 dev_priv->display.crtc_disable(crtc);
6237 intel_crtc->active = false;
6238 intel_update_watermarks(crtc);
6239 intel_disable_shared_dpll(intel_crtc);
6240
6241 domains = intel_crtc->enabled_power_domains;
6242 for_each_power_domain(domain, domains)
6243 intel_display_power_put(dev_priv, domain);
6244 intel_crtc->enabled_power_domains = 0;
6245 }
6246
6247 /*
6248 * turn all crtc's off, but do not adjust state
6249 * This has to be paired with a call to intel_modeset_setup_hw_state.
6250 */
6251 int intel_display_suspend(struct drm_device *dev)
6252 {
6253 struct drm_mode_config *config = &dev->mode_config;
6254 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6255 struct drm_atomic_state *state;
6256 struct drm_crtc *crtc;
6257 unsigned crtc_mask = 0;
6258 int ret = 0;
6259
6260 if (WARN_ON(!ctx))
6261 return 0;
6262
6263 lockdep_assert_held(&ctx->ww_ctx);
6264 state = drm_atomic_state_alloc(dev);
6265 if (WARN_ON(!state))
6266 return -ENOMEM;
6267
6268 state->acquire_ctx = ctx;
6269 state->allow_modeset = true;
6270
6271 for_each_crtc(dev, crtc) {
6272 struct drm_crtc_state *crtc_state =
6273 drm_atomic_get_crtc_state(state, crtc);
6274
6275 ret = PTR_ERR_OR_ZERO(crtc_state);
6276 if (ret)
6277 goto free;
6278
6279 if (!crtc_state->active)
6280 continue;
6281
6282 crtc_state->active = false;
6283 crtc_mask |= 1 << drm_crtc_index(crtc);
6284 }
6285
6286 if (crtc_mask) {
6287 ret = drm_atomic_commit(state);
6288
6289 if (!ret) {
6290 for_each_crtc(dev, crtc)
6291 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6292 crtc->state->active = true;
6293
6294 return ret;
6295 }
6296 }
6297
6298 free:
6299 if (ret)
6300 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6301 drm_atomic_state_free(state);
6302 return ret;
6303 }
6304
6305 void intel_encoder_destroy(struct drm_encoder *encoder)
6306 {
6307 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6308
6309 drm_encoder_cleanup(encoder);
6310 kfree(intel_encoder);
6311 }
6312
6313 /* Cross check the actual hw state with our own modeset state tracking (and it's
6314 * internal consistency). */
6315 static void intel_connector_check_state(struct intel_connector *connector)
6316 {
6317 struct drm_crtc *crtc = connector->base.state->crtc;
6318
6319 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6320 connector->base.base.id,
6321 connector->base.name);
6322
6323 if (connector->get_hw_state(connector)) {
6324 struct intel_encoder *encoder = connector->encoder;
6325 struct drm_connector_state *conn_state = connector->base.state;
6326
6327 I915_STATE_WARN(!crtc,
6328 "connector enabled without attached crtc\n");
6329
6330 if (!crtc)
6331 return;
6332
6333 I915_STATE_WARN(!crtc->state->active,
6334 "connector is active, but attached crtc isn't\n");
6335
6336 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6337 return;
6338
6339 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6340 "atomic encoder doesn't match attached encoder\n");
6341
6342 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6343 "attached encoder crtc differs from connector crtc\n");
6344 } else {
6345 I915_STATE_WARN(crtc && crtc->state->active,
6346 "attached crtc is active, but connector isn't\n");
6347 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6348 "best encoder set without crtc!\n");
6349 }
6350 }
6351
6352 int intel_connector_init(struct intel_connector *connector)
6353 {
6354 struct drm_connector_state *connector_state;
6355
6356 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6357 if (!connector_state)
6358 return -ENOMEM;
6359
6360 connector->base.state = connector_state;
6361 return 0;
6362 }
6363
6364 struct intel_connector *intel_connector_alloc(void)
6365 {
6366 struct intel_connector *connector;
6367
6368 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6369 if (!connector)
6370 return NULL;
6371
6372 if (intel_connector_init(connector) < 0) {
6373 kfree(connector);
6374 return NULL;
6375 }
6376
6377 return connector;
6378 }
6379
6380 /* Simple connector->get_hw_state implementation for encoders that support only
6381 * one connector and no cloning and hence the encoder state determines the state
6382 * of the connector. */
6383 bool intel_connector_get_hw_state(struct intel_connector *connector)
6384 {
6385 enum pipe pipe = 0;
6386 struct intel_encoder *encoder = connector->encoder;
6387
6388 return encoder->get_hw_state(encoder, &pipe);
6389 }
6390
6391 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6392 {
6393 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6394 return crtc_state->fdi_lanes;
6395
6396 return 0;
6397 }
6398
6399 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6400 struct intel_crtc_state *pipe_config)
6401 {
6402 struct drm_atomic_state *state = pipe_config->base.state;
6403 struct intel_crtc *other_crtc;
6404 struct intel_crtc_state *other_crtc_state;
6405
6406 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6407 pipe_name(pipe), pipe_config->fdi_lanes);
6408 if (pipe_config->fdi_lanes > 4) {
6409 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6410 pipe_name(pipe), pipe_config->fdi_lanes);
6411 return -EINVAL;
6412 }
6413
6414 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6415 if (pipe_config->fdi_lanes > 2) {
6416 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6417 pipe_config->fdi_lanes);
6418 return -EINVAL;
6419 } else {
6420 return 0;
6421 }
6422 }
6423
6424 if (INTEL_INFO(dev)->num_pipes == 2)
6425 return 0;
6426
6427 /* Ivybridge 3 pipe is really complicated */
6428 switch (pipe) {
6429 case PIPE_A:
6430 return 0;
6431 case PIPE_B:
6432 if (pipe_config->fdi_lanes <= 2)
6433 return 0;
6434
6435 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6436 other_crtc_state =
6437 intel_atomic_get_crtc_state(state, other_crtc);
6438 if (IS_ERR(other_crtc_state))
6439 return PTR_ERR(other_crtc_state);
6440
6441 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6442 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6443 pipe_name(pipe), pipe_config->fdi_lanes);
6444 return -EINVAL;
6445 }
6446 return 0;
6447 case PIPE_C:
6448 if (pipe_config->fdi_lanes > 2) {
6449 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6450 pipe_name(pipe), pipe_config->fdi_lanes);
6451 return -EINVAL;
6452 }
6453
6454 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6455 other_crtc_state =
6456 intel_atomic_get_crtc_state(state, other_crtc);
6457 if (IS_ERR(other_crtc_state))
6458 return PTR_ERR(other_crtc_state);
6459
6460 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6461 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6462 return -EINVAL;
6463 }
6464 return 0;
6465 default:
6466 BUG();
6467 }
6468 }
6469
6470 #define RETRY 1
6471 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6472 struct intel_crtc_state *pipe_config)
6473 {
6474 struct drm_device *dev = intel_crtc->base.dev;
6475 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6476 int lane, link_bw, fdi_dotclock, ret;
6477 bool needs_recompute = false;
6478
6479 retry:
6480 /* FDI is a binary signal running at ~2.7GHz, encoding
6481 * each output octet as 10 bits. The actual frequency
6482 * is stored as a divider into a 100MHz clock, and the
6483 * mode pixel clock is stored in units of 1KHz.
6484 * Hence the bw of each lane in terms of the mode signal
6485 * is:
6486 */
6487 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6488
6489 fdi_dotclock = adjusted_mode->crtc_clock;
6490
6491 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6492 pipe_config->pipe_bpp);
6493
6494 pipe_config->fdi_lanes = lane;
6495
6496 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6497 link_bw, &pipe_config->fdi_m_n);
6498
6499 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6500 intel_crtc->pipe, pipe_config);
6501 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6502 pipe_config->pipe_bpp -= 2*3;
6503 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6504 pipe_config->pipe_bpp);
6505 needs_recompute = true;
6506 pipe_config->bw_constrained = true;
6507
6508 goto retry;
6509 }
6510
6511 if (needs_recompute)
6512 return RETRY;
6513
6514 return ret;
6515 }
6516
6517 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6518 struct intel_crtc_state *pipe_config)
6519 {
6520 if (pipe_config->pipe_bpp > 24)
6521 return false;
6522
6523 /* HSW can handle pixel rate up to cdclk? */
6524 if (IS_HASWELL(dev_priv->dev))
6525 return true;
6526
6527 /*
6528 * We compare against max which means we must take
6529 * the increased cdclk requirement into account when
6530 * calculating the new cdclk.
6531 *
6532 * Should measure whether using a lower cdclk w/o IPS
6533 */
6534 return ilk_pipe_pixel_rate(pipe_config) <=
6535 dev_priv->max_cdclk_freq * 95 / 100;
6536 }
6537
6538 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6539 struct intel_crtc_state *pipe_config)
6540 {
6541 struct drm_device *dev = crtc->base.dev;
6542 struct drm_i915_private *dev_priv = dev->dev_private;
6543
6544 pipe_config->ips_enabled = i915.enable_ips &&
6545 hsw_crtc_supports_ips(crtc) &&
6546 pipe_config_supports_ips(dev_priv, pipe_config);
6547 }
6548
6549 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6550 struct intel_crtc_state *pipe_config)
6551 {
6552 struct drm_device *dev = crtc->base.dev;
6553 struct drm_i915_private *dev_priv = dev->dev_private;
6554 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6555
6556 /* FIXME should check pixel clock limits on all platforms */
6557 if (INTEL_INFO(dev)->gen < 4) {
6558 int clock_limit = dev_priv->max_cdclk_freq;
6559
6560 /*
6561 * Enable pixel doubling when the dot clock
6562 * is > 90% of the (display) core speed.
6563 *
6564 * GDG double wide on either pipe,
6565 * otherwise pipe A only.
6566 */
6567 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6568 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6569 clock_limit *= 2;
6570 pipe_config->double_wide = true;
6571 }
6572
6573 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6574 return -EINVAL;
6575 }
6576
6577 /*
6578 * Pipe horizontal size must be even in:
6579 * - DVO ganged mode
6580 * - LVDS dual channel mode
6581 * - Double wide pipe
6582 */
6583 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6584 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6585 pipe_config->pipe_src_w &= ~1;
6586
6587 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6588 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6589 */
6590 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6591 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6592 return -EINVAL;
6593
6594 if (HAS_IPS(dev))
6595 hsw_compute_ips_config(crtc, pipe_config);
6596
6597 if (pipe_config->has_pch_encoder)
6598 return ironlake_fdi_compute_config(crtc, pipe_config);
6599
6600 return 0;
6601 }
6602
6603 static int skylake_get_display_clock_speed(struct drm_device *dev)
6604 {
6605 struct drm_i915_private *dev_priv = to_i915(dev);
6606 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6607 uint32_t cdctl = I915_READ(CDCLK_CTL);
6608 uint32_t linkrate;
6609
6610 if (!(lcpll1 & LCPLL_PLL_ENABLE))
6611 return 24000; /* 24MHz is the cd freq with NSSC ref */
6612
6613 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6614 return 540000;
6615
6616 linkrate = (I915_READ(DPLL_CTRL1) &
6617 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6618
6619 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6620 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6621 /* vco 8640 */
6622 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6623 case CDCLK_FREQ_450_432:
6624 return 432000;
6625 case CDCLK_FREQ_337_308:
6626 return 308570;
6627 case CDCLK_FREQ_675_617:
6628 return 617140;
6629 default:
6630 WARN(1, "Unknown cd freq selection\n");
6631 }
6632 } else {
6633 /* vco 8100 */
6634 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6635 case CDCLK_FREQ_450_432:
6636 return 450000;
6637 case CDCLK_FREQ_337_308:
6638 return 337500;
6639 case CDCLK_FREQ_675_617:
6640 return 675000;
6641 default:
6642 WARN(1, "Unknown cd freq selection\n");
6643 }
6644 }
6645
6646 /* error case, do as if DPLL0 isn't enabled */
6647 return 24000;
6648 }
6649
6650 static int broxton_get_display_clock_speed(struct drm_device *dev)
6651 {
6652 struct drm_i915_private *dev_priv = to_i915(dev);
6653 uint32_t cdctl = I915_READ(CDCLK_CTL);
6654 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6655 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6656 int cdclk;
6657
6658 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6659 return 19200;
6660
6661 cdclk = 19200 * pll_ratio / 2;
6662
6663 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6664 case BXT_CDCLK_CD2X_DIV_SEL_1:
6665 return cdclk; /* 576MHz or 624MHz */
6666 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6667 return cdclk * 2 / 3; /* 384MHz */
6668 case BXT_CDCLK_CD2X_DIV_SEL_2:
6669 return cdclk / 2; /* 288MHz */
6670 case BXT_CDCLK_CD2X_DIV_SEL_4:
6671 return cdclk / 4; /* 144MHz */
6672 }
6673
6674 /* error case, do as if DE PLL isn't enabled */
6675 return 19200;
6676 }
6677
6678 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6679 {
6680 struct drm_i915_private *dev_priv = dev->dev_private;
6681 uint32_t lcpll = I915_READ(LCPLL_CTL);
6682 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6683
6684 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6685 return 800000;
6686 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6687 return 450000;
6688 else if (freq == LCPLL_CLK_FREQ_450)
6689 return 450000;
6690 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6691 return 540000;
6692 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6693 return 337500;
6694 else
6695 return 675000;
6696 }
6697
6698 static int haswell_get_display_clock_speed(struct drm_device *dev)
6699 {
6700 struct drm_i915_private *dev_priv = dev->dev_private;
6701 uint32_t lcpll = I915_READ(LCPLL_CTL);
6702 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6703
6704 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6705 return 800000;
6706 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6707 return 450000;
6708 else if (freq == LCPLL_CLK_FREQ_450)
6709 return 450000;
6710 else if (IS_HSW_ULT(dev))
6711 return 337500;
6712 else
6713 return 540000;
6714 }
6715
6716 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6717 {
6718 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6719 CCK_DISPLAY_CLOCK_CONTROL);
6720 }
6721
6722 static int ilk_get_display_clock_speed(struct drm_device *dev)
6723 {
6724 return 450000;
6725 }
6726
6727 static int i945_get_display_clock_speed(struct drm_device *dev)
6728 {
6729 return 400000;
6730 }
6731
6732 static int i915_get_display_clock_speed(struct drm_device *dev)
6733 {
6734 return 333333;
6735 }
6736
6737 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6738 {
6739 return 200000;
6740 }
6741
6742 static int pnv_get_display_clock_speed(struct drm_device *dev)
6743 {
6744 u16 gcfgc = 0;
6745
6746 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6747
6748 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6749 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6750 return 266667;
6751 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6752 return 333333;
6753 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6754 return 444444;
6755 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6756 return 200000;
6757 default:
6758 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6759 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6760 return 133333;
6761 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6762 return 166667;
6763 }
6764 }
6765
6766 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6767 {
6768 u16 gcfgc = 0;
6769
6770 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6771
6772 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6773 return 133333;
6774 else {
6775 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6776 case GC_DISPLAY_CLOCK_333_MHZ:
6777 return 333333;
6778 default:
6779 case GC_DISPLAY_CLOCK_190_200_MHZ:
6780 return 190000;
6781 }
6782 }
6783 }
6784
6785 static int i865_get_display_clock_speed(struct drm_device *dev)
6786 {
6787 return 266667;
6788 }
6789
6790 static int i85x_get_display_clock_speed(struct drm_device *dev)
6791 {
6792 u16 hpllcc = 0;
6793
6794 /*
6795 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6796 * encoding is different :(
6797 * FIXME is this the right way to detect 852GM/852GMV?
6798 */
6799 if (dev->pdev->revision == 0x1)
6800 return 133333;
6801
6802 pci_bus_read_config_word(dev->pdev->bus,
6803 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6804
6805 /* Assume that the hardware is in the high speed state. This
6806 * should be the default.
6807 */
6808 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6809 case GC_CLOCK_133_200:
6810 case GC_CLOCK_133_200_2:
6811 case GC_CLOCK_100_200:
6812 return 200000;
6813 case GC_CLOCK_166_250:
6814 return 250000;
6815 case GC_CLOCK_100_133:
6816 return 133333;
6817 case GC_CLOCK_133_266:
6818 case GC_CLOCK_133_266_2:
6819 case GC_CLOCK_166_266:
6820 return 266667;
6821 }
6822
6823 /* Shouldn't happen */
6824 return 0;
6825 }
6826
6827 static int i830_get_display_clock_speed(struct drm_device *dev)
6828 {
6829 return 133333;
6830 }
6831
6832 static unsigned int intel_hpll_vco(struct drm_device *dev)
6833 {
6834 struct drm_i915_private *dev_priv = dev->dev_private;
6835 static const unsigned int blb_vco[8] = {
6836 [0] = 3200000,
6837 [1] = 4000000,
6838 [2] = 5333333,
6839 [3] = 4800000,
6840 [4] = 6400000,
6841 };
6842 static const unsigned int pnv_vco[8] = {
6843 [0] = 3200000,
6844 [1] = 4000000,
6845 [2] = 5333333,
6846 [3] = 4800000,
6847 [4] = 2666667,
6848 };
6849 static const unsigned int cl_vco[8] = {
6850 [0] = 3200000,
6851 [1] = 4000000,
6852 [2] = 5333333,
6853 [3] = 6400000,
6854 [4] = 3333333,
6855 [5] = 3566667,
6856 [6] = 4266667,
6857 };
6858 static const unsigned int elk_vco[8] = {
6859 [0] = 3200000,
6860 [1] = 4000000,
6861 [2] = 5333333,
6862 [3] = 4800000,
6863 };
6864 static const unsigned int ctg_vco[8] = {
6865 [0] = 3200000,
6866 [1] = 4000000,
6867 [2] = 5333333,
6868 [3] = 6400000,
6869 [4] = 2666667,
6870 [5] = 4266667,
6871 };
6872 const unsigned int *vco_table;
6873 unsigned int vco;
6874 uint8_t tmp = 0;
6875
6876 /* FIXME other chipsets? */
6877 if (IS_GM45(dev))
6878 vco_table = ctg_vco;
6879 else if (IS_G4X(dev))
6880 vco_table = elk_vco;
6881 else if (IS_CRESTLINE(dev))
6882 vco_table = cl_vco;
6883 else if (IS_PINEVIEW(dev))
6884 vco_table = pnv_vco;
6885 else if (IS_G33(dev))
6886 vco_table = blb_vco;
6887 else
6888 return 0;
6889
6890 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6891
6892 vco = vco_table[tmp & 0x7];
6893 if (vco == 0)
6894 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6895 else
6896 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6897
6898 return vco;
6899 }
6900
6901 static int gm45_get_display_clock_speed(struct drm_device *dev)
6902 {
6903 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6904 uint16_t tmp = 0;
6905
6906 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6907
6908 cdclk_sel = (tmp >> 12) & 0x1;
6909
6910 switch (vco) {
6911 case 2666667:
6912 case 4000000:
6913 case 5333333:
6914 return cdclk_sel ? 333333 : 222222;
6915 case 3200000:
6916 return cdclk_sel ? 320000 : 228571;
6917 default:
6918 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6919 return 222222;
6920 }
6921 }
6922
6923 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6924 {
6925 static const uint8_t div_3200[] = { 16, 10, 8 };
6926 static const uint8_t div_4000[] = { 20, 12, 10 };
6927 static const uint8_t div_5333[] = { 24, 16, 14 };
6928 const uint8_t *div_table;
6929 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6930 uint16_t tmp = 0;
6931
6932 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6933
6934 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6935
6936 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6937 goto fail;
6938
6939 switch (vco) {
6940 case 3200000:
6941 div_table = div_3200;
6942 break;
6943 case 4000000:
6944 div_table = div_4000;
6945 break;
6946 case 5333333:
6947 div_table = div_5333;
6948 break;
6949 default:
6950 goto fail;
6951 }
6952
6953 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6954
6955 fail:
6956 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6957 return 200000;
6958 }
6959
6960 static int g33_get_display_clock_speed(struct drm_device *dev)
6961 {
6962 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6963 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6964 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6965 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6966 const uint8_t *div_table;
6967 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6968 uint16_t tmp = 0;
6969
6970 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6971
6972 cdclk_sel = (tmp >> 4) & 0x7;
6973
6974 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6975 goto fail;
6976
6977 switch (vco) {
6978 case 3200000:
6979 div_table = div_3200;
6980 break;
6981 case 4000000:
6982 div_table = div_4000;
6983 break;
6984 case 4800000:
6985 div_table = div_4800;
6986 break;
6987 case 5333333:
6988 div_table = div_5333;
6989 break;
6990 default:
6991 goto fail;
6992 }
6993
6994 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6995
6996 fail:
6997 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
6998 return 190476;
6999 }
7000
7001 static void
7002 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7003 {
7004 while (*num > DATA_LINK_M_N_MASK ||
7005 *den > DATA_LINK_M_N_MASK) {
7006 *num >>= 1;
7007 *den >>= 1;
7008 }
7009 }
7010
7011 static void compute_m_n(unsigned int m, unsigned int n,
7012 uint32_t *ret_m, uint32_t *ret_n)
7013 {
7014 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7015 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7016 intel_reduce_m_n_ratio(ret_m, ret_n);
7017 }
7018
7019 void
7020 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7021 int pixel_clock, int link_clock,
7022 struct intel_link_m_n *m_n)
7023 {
7024 m_n->tu = 64;
7025
7026 compute_m_n(bits_per_pixel * pixel_clock,
7027 link_clock * nlanes * 8,
7028 &m_n->gmch_m, &m_n->gmch_n);
7029
7030 compute_m_n(pixel_clock, link_clock,
7031 &m_n->link_m, &m_n->link_n);
7032 }
7033
7034 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7035 {
7036 if (i915.panel_use_ssc >= 0)
7037 return i915.panel_use_ssc != 0;
7038 return dev_priv->vbt.lvds_use_ssc
7039 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7040 }
7041
7042 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7043 int num_connectors)
7044 {
7045 struct drm_device *dev = crtc_state->base.crtc->dev;
7046 struct drm_i915_private *dev_priv = dev->dev_private;
7047 int refclk;
7048
7049 WARN_ON(!crtc_state->base.state);
7050
7051 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7052 refclk = 100000;
7053 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7054 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7055 refclk = dev_priv->vbt.lvds_ssc_freq;
7056 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7057 } else if (!IS_GEN2(dev)) {
7058 refclk = 96000;
7059 } else {
7060 refclk = 48000;
7061 }
7062
7063 return refclk;
7064 }
7065
7066 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7067 {
7068 return (1 << dpll->n) << 16 | dpll->m2;
7069 }
7070
7071 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7072 {
7073 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7074 }
7075
7076 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7077 struct intel_crtc_state *crtc_state,
7078 intel_clock_t *reduced_clock)
7079 {
7080 struct drm_device *dev = crtc->base.dev;
7081 u32 fp, fp2 = 0;
7082
7083 if (IS_PINEVIEW(dev)) {
7084 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7085 if (reduced_clock)
7086 fp2 = pnv_dpll_compute_fp(reduced_clock);
7087 } else {
7088 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7089 if (reduced_clock)
7090 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7091 }
7092
7093 crtc_state->dpll_hw_state.fp0 = fp;
7094
7095 crtc->lowfreq_avail = false;
7096 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7097 reduced_clock) {
7098 crtc_state->dpll_hw_state.fp1 = fp2;
7099 crtc->lowfreq_avail = true;
7100 } else {
7101 crtc_state->dpll_hw_state.fp1 = fp;
7102 }
7103 }
7104
7105 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7106 pipe)
7107 {
7108 u32 reg_val;
7109
7110 /*
7111 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7112 * and set it to a reasonable value instead.
7113 */
7114 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7115 reg_val &= 0xffffff00;
7116 reg_val |= 0x00000030;
7117 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7118
7119 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7120 reg_val &= 0x8cffffff;
7121 reg_val = 0x8c000000;
7122 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7123
7124 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7125 reg_val &= 0xffffff00;
7126 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7127
7128 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7129 reg_val &= 0x00ffffff;
7130 reg_val |= 0xb0000000;
7131 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7132 }
7133
7134 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7135 struct intel_link_m_n *m_n)
7136 {
7137 struct drm_device *dev = crtc->base.dev;
7138 struct drm_i915_private *dev_priv = dev->dev_private;
7139 int pipe = crtc->pipe;
7140
7141 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7142 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7143 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7144 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7145 }
7146
7147 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7148 struct intel_link_m_n *m_n,
7149 struct intel_link_m_n *m2_n2)
7150 {
7151 struct drm_device *dev = crtc->base.dev;
7152 struct drm_i915_private *dev_priv = dev->dev_private;
7153 int pipe = crtc->pipe;
7154 enum transcoder transcoder = crtc->config->cpu_transcoder;
7155
7156 if (INTEL_INFO(dev)->gen >= 5) {
7157 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7158 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7159 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7160 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7161 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7162 * for gen < 8) and if DRRS is supported (to make sure the
7163 * registers are not unnecessarily accessed).
7164 */
7165 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7166 crtc->config->has_drrs) {
7167 I915_WRITE(PIPE_DATA_M2(transcoder),
7168 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7169 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7170 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7171 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7172 }
7173 } else {
7174 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7175 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7176 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7177 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7178 }
7179 }
7180
7181 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7182 {
7183 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7184
7185 if (m_n == M1_N1) {
7186 dp_m_n = &crtc->config->dp_m_n;
7187 dp_m2_n2 = &crtc->config->dp_m2_n2;
7188 } else if (m_n == M2_N2) {
7189
7190 /*
7191 * M2_N2 registers are not supported. Hence m2_n2 divider value
7192 * needs to be programmed into M1_N1.
7193 */
7194 dp_m_n = &crtc->config->dp_m2_n2;
7195 } else {
7196 DRM_ERROR("Unsupported divider value\n");
7197 return;
7198 }
7199
7200 if (crtc->config->has_pch_encoder)
7201 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7202 else
7203 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7204 }
7205
7206 static void vlv_compute_dpll(struct intel_crtc *crtc,
7207 struct intel_crtc_state *pipe_config)
7208 {
7209 u32 dpll, dpll_md;
7210
7211 /*
7212 * Enable DPIO clock input. We should never disable the reference
7213 * clock for pipe B, since VGA hotplug / manual detection depends
7214 * on it.
7215 */
7216 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7217 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7218 /* We should never disable this, set it here for state tracking */
7219 if (crtc->pipe == PIPE_B)
7220 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7221 dpll |= DPLL_VCO_ENABLE;
7222 pipe_config->dpll_hw_state.dpll = dpll;
7223
7224 dpll_md = (pipe_config->pixel_multiplier - 1)
7225 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7226 pipe_config->dpll_hw_state.dpll_md = dpll_md;
7227 }
7228
7229 static void vlv_prepare_pll(struct intel_crtc *crtc,
7230 const struct intel_crtc_state *pipe_config)
7231 {
7232 struct drm_device *dev = crtc->base.dev;
7233 struct drm_i915_private *dev_priv = dev->dev_private;
7234 int pipe = crtc->pipe;
7235 u32 mdiv;
7236 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7237 u32 coreclk, reg_val;
7238
7239 mutex_lock(&dev_priv->sb_lock);
7240
7241 bestn = pipe_config->dpll.n;
7242 bestm1 = pipe_config->dpll.m1;
7243 bestm2 = pipe_config->dpll.m2;
7244 bestp1 = pipe_config->dpll.p1;
7245 bestp2 = pipe_config->dpll.p2;
7246
7247 /* See eDP HDMI DPIO driver vbios notes doc */
7248
7249 /* PLL B needs special handling */
7250 if (pipe == PIPE_B)
7251 vlv_pllb_recal_opamp(dev_priv, pipe);
7252
7253 /* Set up Tx target for periodic Rcomp update */
7254 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7255
7256 /* Disable target IRef on PLL */
7257 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7258 reg_val &= 0x00ffffff;
7259 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7260
7261 /* Disable fast lock */
7262 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7263
7264 /* Set idtafcrecal before PLL is enabled */
7265 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7266 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7267 mdiv |= ((bestn << DPIO_N_SHIFT));
7268 mdiv |= (1 << DPIO_K_SHIFT);
7269
7270 /*
7271 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7272 * but we don't support that).
7273 * Note: don't use the DAC post divider as it seems unstable.
7274 */
7275 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7276 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7277
7278 mdiv |= DPIO_ENABLE_CALIBRATION;
7279 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7280
7281 /* Set HBR and RBR LPF coefficients */
7282 if (pipe_config->port_clock == 162000 ||
7283 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7284 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7285 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7286 0x009f0003);
7287 else
7288 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7289 0x00d0000f);
7290
7291 if (pipe_config->has_dp_encoder) {
7292 /* Use SSC source */
7293 if (pipe == PIPE_A)
7294 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7295 0x0df40000);
7296 else
7297 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7298 0x0df70000);
7299 } else { /* HDMI or VGA */
7300 /* Use bend source */
7301 if (pipe == PIPE_A)
7302 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7303 0x0df70000);
7304 else
7305 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7306 0x0df40000);
7307 }
7308
7309 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7310 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7311 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7312 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7313 coreclk |= 0x01000000;
7314 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7315
7316 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7317 mutex_unlock(&dev_priv->sb_lock);
7318 }
7319
7320 static void chv_compute_dpll(struct intel_crtc *crtc,
7321 struct intel_crtc_state *pipe_config)
7322 {
7323 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7324 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7325 DPLL_VCO_ENABLE;
7326 if (crtc->pipe != PIPE_A)
7327 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7328
7329 pipe_config->dpll_hw_state.dpll_md =
7330 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7331 }
7332
7333 static void chv_prepare_pll(struct intel_crtc *crtc,
7334 const struct intel_crtc_state *pipe_config)
7335 {
7336 struct drm_device *dev = crtc->base.dev;
7337 struct drm_i915_private *dev_priv = dev->dev_private;
7338 int pipe = crtc->pipe;
7339 int dpll_reg = DPLL(crtc->pipe);
7340 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7341 u32 loopfilter, tribuf_calcntr;
7342 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7343 u32 dpio_val;
7344 int vco;
7345
7346 bestn = pipe_config->dpll.n;
7347 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7348 bestm1 = pipe_config->dpll.m1;
7349 bestm2 = pipe_config->dpll.m2 >> 22;
7350 bestp1 = pipe_config->dpll.p1;
7351 bestp2 = pipe_config->dpll.p2;
7352 vco = pipe_config->dpll.vco;
7353 dpio_val = 0;
7354 loopfilter = 0;
7355
7356 /*
7357 * Enable Refclk and SSC
7358 */
7359 I915_WRITE(dpll_reg,
7360 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7361
7362 mutex_lock(&dev_priv->sb_lock);
7363
7364 /* p1 and p2 divider */
7365 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7366 5 << DPIO_CHV_S1_DIV_SHIFT |
7367 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7368 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7369 1 << DPIO_CHV_K_DIV_SHIFT);
7370
7371 /* Feedback post-divider - m2 */
7372 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7373
7374 /* Feedback refclk divider - n and m1 */
7375 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7376 DPIO_CHV_M1_DIV_BY_2 |
7377 1 << DPIO_CHV_N_DIV_SHIFT);
7378
7379 /* M2 fraction division */
7380 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7381
7382 /* M2 fraction division enable */
7383 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7384 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7385 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7386 if (bestm2_frac)
7387 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7388 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7389
7390 /* Program digital lock detect threshold */
7391 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7392 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7393 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7394 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7395 if (!bestm2_frac)
7396 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7397 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7398
7399 /* Loop filter */
7400 if (vco == 5400000) {
7401 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7402 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7403 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7404 tribuf_calcntr = 0x9;
7405 } else if (vco <= 6200000) {
7406 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7407 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7408 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7409 tribuf_calcntr = 0x9;
7410 } else if (vco <= 6480000) {
7411 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7412 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7413 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7414 tribuf_calcntr = 0x8;
7415 } else {
7416 /* Not supported. Apply the same limits as in the max case */
7417 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7418 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7419 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7420 tribuf_calcntr = 0;
7421 }
7422 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7423
7424 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7425 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7426 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7427 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7428
7429 /* AFC Recal */
7430 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7431 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7432 DPIO_AFC_RECAL);
7433
7434 mutex_unlock(&dev_priv->sb_lock);
7435 }
7436
7437 /**
7438 * vlv_force_pll_on - forcibly enable just the PLL
7439 * @dev_priv: i915 private structure
7440 * @pipe: pipe PLL to enable
7441 * @dpll: PLL configuration
7442 *
7443 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7444 * in cases where we need the PLL enabled even when @pipe is not going to
7445 * be enabled.
7446 */
7447 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7448 const struct dpll *dpll)
7449 {
7450 struct intel_crtc *crtc =
7451 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7452 struct intel_crtc_state pipe_config = {
7453 .base.crtc = &crtc->base,
7454 .pixel_multiplier = 1,
7455 .dpll = *dpll,
7456 };
7457
7458 if (IS_CHERRYVIEW(dev)) {
7459 chv_compute_dpll(crtc, &pipe_config);
7460 chv_prepare_pll(crtc, &pipe_config);
7461 chv_enable_pll(crtc, &pipe_config);
7462 } else {
7463 vlv_compute_dpll(crtc, &pipe_config);
7464 vlv_prepare_pll(crtc, &pipe_config);
7465 vlv_enable_pll(crtc, &pipe_config);
7466 }
7467 }
7468
7469 /**
7470 * vlv_force_pll_off - forcibly disable just the PLL
7471 * @dev_priv: i915 private structure
7472 * @pipe: pipe PLL to disable
7473 *
7474 * Disable the PLL for @pipe. To be used in cases where we need
7475 * the PLL enabled even when @pipe is not going to be enabled.
7476 */
7477 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7478 {
7479 if (IS_CHERRYVIEW(dev))
7480 chv_disable_pll(to_i915(dev), pipe);
7481 else
7482 vlv_disable_pll(to_i915(dev), pipe);
7483 }
7484
7485 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7486 struct intel_crtc_state *crtc_state,
7487 intel_clock_t *reduced_clock,
7488 int num_connectors)
7489 {
7490 struct drm_device *dev = crtc->base.dev;
7491 struct drm_i915_private *dev_priv = dev->dev_private;
7492 u32 dpll;
7493 bool is_sdvo;
7494 struct dpll *clock = &crtc_state->dpll;
7495
7496 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7497
7498 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7499 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7500
7501 dpll = DPLL_VGA_MODE_DIS;
7502
7503 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7504 dpll |= DPLLB_MODE_LVDS;
7505 else
7506 dpll |= DPLLB_MODE_DAC_SERIAL;
7507
7508 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7509 dpll |= (crtc_state->pixel_multiplier - 1)
7510 << SDVO_MULTIPLIER_SHIFT_HIRES;
7511 }
7512
7513 if (is_sdvo)
7514 dpll |= DPLL_SDVO_HIGH_SPEED;
7515
7516 if (crtc_state->has_dp_encoder)
7517 dpll |= DPLL_SDVO_HIGH_SPEED;
7518
7519 /* compute bitmask from p1 value */
7520 if (IS_PINEVIEW(dev))
7521 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7522 else {
7523 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7524 if (IS_G4X(dev) && reduced_clock)
7525 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7526 }
7527 switch (clock->p2) {
7528 case 5:
7529 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7530 break;
7531 case 7:
7532 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7533 break;
7534 case 10:
7535 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7536 break;
7537 case 14:
7538 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7539 break;
7540 }
7541 if (INTEL_INFO(dev)->gen >= 4)
7542 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7543
7544 if (crtc_state->sdvo_tv_clock)
7545 dpll |= PLL_REF_INPUT_TVCLKINBC;
7546 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7547 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7548 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7549 else
7550 dpll |= PLL_REF_INPUT_DREFCLK;
7551
7552 dpll |= DPLL_VCO_ENABLE;
7553 crtc_state->dpll_hw_state.dpll = dpll;
7554
7555 if (INTEL_INFO(dev)->gen >= 4) {
7556 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7557 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7558 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7559 }
7560 }
7561
7562 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7563 struct intel_crtc_state *crtc_state,
7564 intel_clock_t *reduced_clock,
7565 int num_connectors)
7566 {
7567 struct drm_device *dev = crtc->base.dev;
7568 struct drm_i915_private *dev_priv = dev->dev_private;
7569 u32 dpll;
7570 struct dpll *clock = &crtc_state->dpll;
7571
7572 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7573
7574 dpll = DPLL_VGA_MODE_DIS;
7575
7576 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7577 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7578 } else {
7579 if (clock->p1 == 2)
7580 dpll |= PLL_P1_DIVIDE_BY_TWO;
7581 else
7582 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7583 if (clock->p2 == 4)
7584 dpll |= PLL_P2_DIVIDE_BY_4;
7585 }
7586
7587 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7588 dpll |= DPLL_DVO_2X_MODE;
7589
7590 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7591 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7592 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7593 else
7594 dpll |= PLL_REF_INPUT_DREFCLK;
7595
7596 dpll |= DPLL_VCO_ENABLE;
7597 crtc_state->dpll_hw_state.dpll = dpll;
7598 }
7599
7600 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7601 {
7602 struct drm_device *dev = intel_crtc->base.dev;
7603 struct drm_i915_private *dev_priv = dev->dev_private;
7604 enum pipe pipe = intel_crtc->pipe;
7605 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7606 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7607 uint32_t crtc_vtotal, crtc_vblank_end;
7608 int vsyncshift = 0;
7609
7610 /* We need to be careful not to changed the adjusted mode, for otherwise
7611 * the hw state checker will get angry at the mismatch. */
7612 crtc_vtotal = adjusted_mode->crtc_vtotal;
7613 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7614
7615 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7616 /* the chip adds 2 halflines automatically */
7617 crtc_vtotal -= 1;
7618 crtc_vblank_end -= 1;
7619
7620 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7621 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7622 else
7623 vsyncshift = adjusted_mode->crtc_hsync_start -
7624 adjusted_mode->crtc_htotal / 2;
7625 if (vsyncshift < 0)
7626 vsyncshift += adjusted_mode->crtc_htotal;
7627 }
7628
7629 if (INTEL_INFO(dev)->gen > 3)
7630 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7631
7632 I915_WRITE(HTOTAL(cpu_transcoder),
7633 (adjusted_mode->crtc_hdisplay - 1) |
7634 ((adjusted_mode->crtc_htotal - 1) << 16));
7635 I915_WRITE(HBLANK(cpu_transcoder),
7636 (adjusted_mode->crtc_hblank_start - 1) |
7637 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7638 I915_WRITE(HSYNC(cpu_transcoder),
7639 (adjusted_mode->crtc_hsync_start - 1) |
7640 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7641
7642 I915_WRITE(VTOTAL(cpu_transcoder),
7643 (adjusted_mode->crtc_vdisplay - 1) |
7644 ((crtc_vtotal - 1) << 16));
7645 I915_WRITE(VBLANK(cpu_transcoder),
7646 (adjusted_mode->crtc_vblank_start - 1) |
7647 ((crtc_vblank_end - 1) << 16));
7648 I915_WRITE(VSYNC(cpu_transcoder),
7649 (adjusted_mode->crtc_vsync_start - 1) |
7650 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7651
7652 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7653 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7654 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7655 * bits. */
7656 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7657 (pipe == PIPE_B || pipe == PIPE_C))
7658 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7659
7660 /* pipesrc controls the size that is scaled from, which should
7661 * always be the user's requested size.
7662 */
7663 I915_WRITE(PIPESRC(pipe),
7664 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7665 (intel_crtc->config->pipe_src_h - 1));
7666 }
7667
7668 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7669 struct intel_crtc_state *pipe_config)
7670 {
7671 struct drm_device *dev = crtc->base.dev;
7672 struct drm_i915_private *dev_priv = dev->dev_private;
7673 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7674 uint32_t tmp;
7675
7676 tmp = I915_READ(HTOTAL(cpu_transcoder));
7677 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7678 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7679 tmp = I915_READ(HBLANK(cpu_transcoder));
7680 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7681 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7682 tmp = I915_READ(HSYNC(cpu_transcoder));
7683 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7684 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7685
7686 tmp = I915_READ(VTOTAL(cpu_transcoder));
7687 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7688 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7689 tmp = I915_READ(VBLANK(cpu_transcoder));
7690 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7691 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7692 tmp = I915_READ(VSYNC(cpu_transcoder));
7693 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7694 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7695
7696 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7697 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7698 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7699 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7700 }
7701
7702 tmp = I915_READ(PIPESRC(crtc->pipe));
7703 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7704 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7705
7706 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7707 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7708 }
7709
7710 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7711 struct intel_crtc_state *pipe_config)
7712 {
7713 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7714 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7715 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7716 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7717
7718 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7719 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7720 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7721 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7722
7723 mode->flags = pipe_config->base.adjusted_mode.flags;
7724 mode->type = DRM_MODE_TYPE_DRIVER;
7725
7726 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7727 mode->flags |= pipe_config->base.adjusted_mode.flags;
7728
7729 mode->hsync = drm_mode_hsync(mode);
7730 mode->vrefresh = drm_mode_vrefresh(mode);
7731 drm_mode_set_name(mode);
7732 }
7733
7734 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7735 {
7736 struct drm_device *dev = intel_crtc->base.dev;
7737 struct drm_i915_private *dev_priv = dev->dev_private;
7738 uint32_t pipeconf;
7739
7740 pipeconf = 0;
7741
7742 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7743 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7744 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7745
7746 if (intel_crtc->config->double_wide)
7747 pipeconf |= PIPECONF_DOUBLE_WIDE;
7748
7749 /* only g4x and later have fancy bpc/dither controls */
7750 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7751 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7752 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7753 pipeconf |= PIPECONF_DITHER_EN |
7754 PIPECONF_DITHER_TYPE_SP;
7755
7756 switch (intel_crtc->config->pipe_bpp) {
7757 case 18:
7758 pipeconf |= PIPECONF_6BPC;
7759 break;
7760 case 24:
7761 pipeconf |= PIPECONF_8BPC;
7762 break;
7763 case 30:
7764 pipeconf |= PIPECONF_10BPC;
7765 break;
7766 default:
7767 /* Case prevented by intel_choose_pipe_bpp_dither. */
7768 BUG();
7769 }
7770 }
7771
7772 if (HAS_PIPE_CXSR(dev)) {
7773 if (intel_crtc->lowfreq_avail) {
7774 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7775 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7776 } else {
7777 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7778 }
7779 }
7780
7781 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7782 if (INTEL_INFO(dev)->gen < 4 ||
7783 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7784 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7785 else
7786 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7787 } else
7788 pipeconf |= PIPECONF_PROGRESSIVE;
7789
7790 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7791 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7792
7793 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7794 POSTING_READ(PIPECONF(intel_crtc->pipe));
7795 }
7796
7797 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7798 struct intel_crtc_state *crtc_state)
7799 {
7800 struct drm_device *dev = crtc->base.dev;
7801 struct drm_i915_private *dev_priv = dev->dev_private;
7802 int refclk, num_connectors = 0;
7803 intel_clock_t clock;
7804 bool ok;
7805 bool is_dsi = false;
7806 struct intel_encoder *encoder;
7807 const intel_limit_t *limit;
7808 struct drm_atomic_state *state = crtc_state->base.state;
7809 struct drm_connector *connector;
7810 struct drm_connector_state *connector_state;
7811 int i;
7812
7813 memset(&crtc_state->dpll_hw_state, 0,
7814 sizeof(crtc_state->dpll_hw_state));
7815
7816 for_each_connector_in_state(state, connector, connector_state, i) {
7817 if (connector_state->crtc != &crtc->base)
7818 continue;
7819
7820 encoder = to_intel_encoder(connector_state->best_encoder);
7821
7822 switch (encoder->type) {
7823 case INTEL_OUTPUT_DSI:
7824 is_dsi = true;
7825 break;
7826 default:
7827 break;
7828 }
7829
7830 num_connectors++;
7831 }
7832
7833 if (is_dsi)
7834 return 0;
7835
7836 if (!crtc_state->clock_set) {
7837 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7838
7839 /*
7840 * Returns a set of divisors for the desired target clock with
7841 * the given refclk, or FALSE. The returned values represent
7842 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7843 * 2) / p1 / p2.
7844 */
7845 limit = intel_limit(crtc_state, refclk);
7846 ok = dev_priv->display.find_dpll(limit, crtc_state,
7847 crtc_state->port_clock,
7848 refclk, NULL, &clock);
7849 if (!ok) {
7850 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7851 return -EINVAL;
7852 }
7853
7854 /* Compat-code for transition, will disappear. */
7855 crtc_state->dpll.n = clock.n;
7856 crtc_state->dpll.m1 = clock.m1;
7857 crtc_state->dpll.m2 = clock.m2;
7858 crtc_state->dpll.p1 = clock.p1;
7859 crtc_state->dpll.p2 = clock.p2;
7860 }
7861
7862 if (IS_GEN2(dev)) {
7863 i8xx_compute_dpll(crtc, crtc_state, NULL,
7864 num_connectors);
7865 } else if (IS_CHERRYVIEW(dev)) {
7866 chv_compute_dpll(crtc, crtc_state);
7867 } else if (IS_VALLEYVIEW(dev)) {
7868 vlv_compute_dpll(crtc, crtc_state);
7869 } else {
7870 i9xx_compute_dpll(crtc, crtc_state, NULL,
7871 num_connectors);
7872 }
7873
7874 return 0;
7875 }
7876
7877 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7878 struct intel_crtc_state *pipe_config)
7879 {
7880 struct drm_device *dev = crtc->base.dev;
7881 struct drm_i915_private *dev_priv = dev->dev_private;
7882 uint32_t tmp;
7883
7884 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7885 return;
7886
7887 tmp = I915_READ(PFIT_CONTROL);
7888 if (!(tmp & PFIT_ENABLE))
7889 return;
7890
7891 /* Check whether the pfit is attached to our pipe. */
7892 if (INTEL_INFO(dev)->gen < 4) {
7893 if (crtc->pipe != PIPE_B)
7894 return;
7895 } else {
7896 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7897 return;
7898 }
7899
7900 pipe_config->gmch_pfit.control = tmp;
7901 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7902 if (INTEL_INFO(dev)->gen < 5)
7903 pipe_config->gmch_pfit.lvds_border_bits =
7904 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7905 }
7906
7907 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7908 struct intel_crtc_state *pipe_config)
7909 {
7910 struct drm_device *dev = crtc->base.dev;
7911 struct drm_i915_private *dev_priv = dev->dev_private;
7912 int pipe = pipe_config->cpu_transcoder;
7913 intel_clock_t clock;
7914 u32 mdiv;
7915 int refclk = 100000;
7916
7917 /* In case of MIPI DPLL will not even be used */
7918 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7919 return;
7920
7921 mutex_lock(&dev_priv->sb_lock);
7922 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7923 mutex_unlock(&dev_priv->sb_lock);
7924
7925 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7926 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7927 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7928 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7929 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7930
7931 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7932 }
7933
7934 static void
7935 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7936 struct intel_initial_plane_config *plane_config)
7937 {
7938 struct drm_device *dev = crtc->base.dev;
7939 struct drm_i915_private *dev_priv = dev->dev_private;
7940 u32 val, base, offset;
7941 int pipe = crtc->pipe, plane = crtc->plane;
7942 int fourcc, pixel_format;
7943 unsigned int aligned_height;
7944 struct drm_framebuffer *fb;
7945 struct intel_framebuffer *intel_fb;
7946
7947 val = I915_READ(DSPCNTR(plane));
7948 if (!(val & DISPLAY_PLANE_ENABLE))
7949 return;
7950
7951 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7952 if (!intel_fb) {
7953 DRM_DEBUG_KMS("failed to alloc fb\n");
7954 return;
7955 }
7956
7957 fb = &intel_fb->base;
7958
7959 if (INTEL_INFO(dev)->gen >= 4) {
7960 if (val & DISPPLANE_TILED) {
7961 plane_config->tiling = I915_TILING_X;
7962 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7963 }
7964 }
7965
7966 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7967 fourcc = i9xx_format_to_fourcc(pixel_format);
7968 fb->pixel_format = fourcc;
7969 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7970
7971 if (INTEL_INFO(dev)->gen >= 4) {
7972 if (plane_config->tiling)
7973 offset = I915_READ(DSPTILEOFF(plane));
7974 else
7975 offset = I915_READ(DSPLINOFF(plane));
7976 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7977 } else {
7978 base = I915_READ(DSPADDR(plane));
7979 }
7980 plane_config->base = base;
7981
7982 val = I915_READ(PIPESRC(pipe));
7983 fb->width = ((val >> 16) & 0xfff) + 1;
7984 fb->height = ((val >> 0) & 0xfff) + 1;
7985
7986 val = I915_READ(DSPSTRIDE(pipe));
7987 fb->pitches[0] = val & 0xffffffc0;
7988
7989 aligned_height = intel_fb_align_height(dev, fb->height,
7990 fb->pixel_format,
7991 fb->modifier[0]);
7992
7993 plane_config->size = fb->pitches[0] * aligned_height;
7994
7995 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7996 pipe_name(pipe), plane, fb->width, fb->height,
7997 fb->bits_per_pixel, base, fb->pitches[0],
7998 plane_config->size);
7999
8000 plane_config->fb = intel_fb;
8001 }
8002
8003 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8004 struct intel_crtc_state *pipe_config)
8005 {
8006 struct drm_device *dev = crtc->base.dev;
8007 struct drm_i915_private *dev_priv = dev->dev_private;
8008 int pipe = pipe_config->cpu_transcoder;
8009 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8010 intel_clock_t clock;
8011 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8012 int refclk = 100000;
8013
8014 mutex_lock(&dev_priv->sb_lock);
8015 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8016 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8017 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8018 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8019 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8020 mutex_unlock(&dev_priv->sb_lock);
8021
8022 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8023 clock.m2 = (pll_dw0 & 0xff) << 22;
8024 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8025 clock.m2 |= pll_dw2 & 0x3fffff;
8026 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8027 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8028 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8029
8030 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8031 }
8032
8033 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8034 struct intel_crtc_state *pipe_config)
8035 {
8036 struct drm_device *dev = crtc->base.dev;
8037 struct drm_i915_private *dev_priv = dev->dev_private;
8038 uint32_t tmp;
8039
8040 if (!intel_display_power_is_enabled(dev_priv,
8041 POWER_DOMAIN_PIPE(crtc->pipe)))
8042 return false;
8043
8044 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8045 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8046
8047 tmp = I915_READ(PIPECONF(crtc->pipe));
8048 if (!(tmp & PIPECONF_ENABLE))
8049 return false;
8050
8051 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8052 switch (tmp & PIPECONF_BPC_MASK) {
8053 case PIPECONF_6BPC:
8054 pipe_config->pipe_bpp = 18;
8055 break;
8056 case PIPECONF_8BPC:
8057 pipe_config->pipe_bpp = 24;
8058 break;
8059 case PIPECONF_10BPC:
8060 pipe_config->pipe_bpp = 30;
8061 break;
8062 default:
8063 break;
8064 }
8065 }
8066
8067 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8068 pipe_config->limited_color_range = true;
8069
8070 if (INTEL_INFO(dev)->gen < 4)
8071 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8072
8073 intel_get_pipe_timings(crtc, pipe_config);
8074
8075 i9xx_get_pfit_config(crtc, pipe_config);
8076
8077 if (INTEL_INFO(dev)->gen >= 4) {
8078 tmp = I915_READ(DPLL_MD(crtc->pipe));
8079 pipe_config->pixel_multiplier =
8080 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8081 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8082 pipe_config->dpll_hw_state.dpll_md = tmp;
8083 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8084 tmp = I915_READ(DPLL(crtc->pipe));
8085 pipe_config->pixel_multiplier =
8086 ((tmp & SDVO_MULTIPLIER_MASK)
8087 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8088 } else {
8089 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8090 * port and will be fixed up in the encoder->get_config
8091 * function. */
8092 pipe_config->pixel_multiplier = 1;
8093 }
8094 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8095 if (!IS_VALLEYVIEW(dev)) {
8096 /*
8097 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8098 * on 830. Filter it out here so that we don't
8099 * report errors due to that.
8100 */
8101 if (IS_I830(dev))
8102 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8103
8104 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8105 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8106 } else {
8107 /* Mask out read-only status bits. */
8108 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8109 DPLL_PORTC_READY_MASK |
8110 DPLL_PORTB_READY_MASK);
8111 }
8112
8113 if (IS_CHERRYVIEW(dev))
8114 chv_crtc_clock_get(crtc, pipe_config);
8115 else if (IS_VALLEYVIEW(dev))
8116 vlv_crtc_clock_get(crtc, pipe_config);
8117 else
8118 i9xx_crtc_clock_get(crtc, pipe_config);
8119
8120 /*
8121 * Normally the dotclock is filled in by the encoder .get_config()
8122 * but in case the pipe is enabled w/o any ports we need a sane
8123 * default.
8124 */
8125 pipe_config->base.adjusted_mode.crtc_clock =
8126 pipe_config->port_clock / pipe_config->pixel_multiplier;
8127
8128 return true;
8129 }
8130
8131 static void ironlake_init_pch_refclk(struct drm_device *dev)
8132 {
8133 struct drm_i915_private *dev_priv = dev->dev_private;
8134 struct intel_encoder *encoder;
8135 u32 val, final;
8136 bool has_lvds = false;
8137 bool has_cpu_edp = false;
8138 bool has_panel = false;
8139 bool has_ck505 = false;
8140 bool can_ssc = false;
8141
8142 /* We need to take the global config into account */
8143 for_each_intel_encoder(dev, encoder) {
8144 switch (encoder->type) {
8145 case INTEL_OUTPUT_LVDS:
8146 has_panel = true;
8147 has_lvds = true;
8148 break;
8149 case INTEL_OUTPUT_EDP:
8150 has_panel = true;
8151 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8152 has_cpu_edp = true;
8153 break;
8154 default:
8155 break;
8156 }
8157 }
8158
8159 if (HAS_PCH_IBX(dev)) {
8160 has_ck505 = dev_priv->vbt.display_clock_mode;
8161 can_ssc = has_ck505;
8162 } else {
8163 has_ck505 = false;
8164 can_ssc = true;
8165 }
8166
8167 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8168 has_panel, has_lvds, has_ck505);
8169
8170 /* Ironlake: try to setup display ref clock before DPLL
8171 * enabling. This is only under driver's control after
8172 * PCH B stepping, previous chipset stepping should be
8173 * ignoring this setting.
8174 */
8175 val = I915_READ(PCH_DREF_CONTROL);
8176
8177 /* As we must carefully and slowly disable/enable each source in turn,
8178 * compute the final state we want first and check if we need to
8179 * make any changes at all.
8180 */
8181 final = val;
8182 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8183 if (has_ck505)
8184 final |= DREF_NONSPREAD_CK505_ENABLE;
8185 else
8186 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8187
8188 final &= ~DREF_SSC_SOURCE_MASK;
8189 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8190 final &= ~DREF_SSC1_ENABLE;
8191
8192 if (has_panel) {
8193 final |= DREF_SSC_SOURCE_ENABLE;
8194
8195 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8196 final |= DREF_SSC1_ENABLE;
8197
8198 if (has_cpu_edp) {
8199 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8200 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8201 else
8202 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8203 } else
8204 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8205 } else {
8206 final |= DREF_SSC_SOURCE_DISABLE;
8207 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8208 }
8209
8210 if (final == val)
8211 return;
8212
8213 /* Always enable nonspread source */
8214 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8215
8216 if (has_ck505)
8217 val |= DREF_NONSPREAD_CK505_ENABLE;
8218 else
8219 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8220
8221 if (has_panel) {
8222 val &= ~DREF_SSC_SOURCE_MASK;
8223 val |= DREF_SSC_SOURCE_ENABLE;
8224
8225 /* SSC must be turned on before enabling the CPU output */
8226 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8227 DRM_DEBUG_KMS("Using SSC on panel\n");
8228 val |= DREF_SSC1_ENABLE;
8229 } else
8230 val &= ~DREF_SSC1_ENABLE;
8231
8232 /* Get SSC going before enabling the outputs */
8233 I915_WRITE(PCH_DREF_CONTROL, val);
8234 POSTING_READ(PCH_DREF_CONTROL);
8235 udelay(200);
8236
8237 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8238
8239 /* Enable CPU source on CPU attached eDP */
8240 if (has_cpu_edp) {
8241 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8242 DRM_DEBUG_KMS("Using SSC on eDP\n");
8243 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8244 } else
8245 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8246 } else
8247 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8248
8249 I915_WRITE(PCH_DREF_CONTROL, val);
8250 POSTING_READ(PCH_DREF_CONTROL);
8251 udelay(200);
8252 } else {
8253 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8254
8255 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8256
8257 /* Turn off CPU output */
8258 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8259
8260 I915_WRITE(PCH_DREF_CONTROL, val);
8261 POSTING_READ(PCH_DREF_CONTROL);
8262 udelay(200);
8263
8264 /* Turn off the SSC source */
8265 val &= ~DREF_SSC_SOURCE_MASK;
8266 val |= DREF_SSC_SOURCE_DISABLE;
8267
8268 /* Turn off SSC1 */
8269 val &= ~DREF_SSC1_ENABLE;
8270
8271 I915_WRITE(PCH_DREF_CONTROL, val);
8272 POSTING_READ(PCH_DREF_CONTROL);
8273 udelay(200);
8274 }
8275
8276 BUG_ON(val != final);
8277 }
8278
8279 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8280 {
8281 uint32_t tmp;
8282
8283 tmp = I915_READ(SOUTH_CHICKEN2);
8284 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8285 I915_WRITE(SOUTH_CHICKEN2, tmp);
8286
8287 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8288 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8289 DRM_ERROR("FDI mPHY reset assert timeout\n");
8290
8291 tmp = I915_READ(SOUTH_CHICKEN2);
8292 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8293 I915_WRITE(SOUTH_CHICKEN2, tmp);
8294
8295 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8296 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8297 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8298 }
8299
8300 /* WaMPhyProgramming:hsw */
8301 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8302 {
8303 uint32_t tmp;
8304
8305 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8306 tmp &= ~(0xFF << 24);
8307 tmp |= (0x12 << 24);
8308 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8309
8310 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8311 tmp |= (1 << 11);
8312 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8313
8314 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8315 tmp |= (1 << 11);
8316 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8317
8318 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8319 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8320 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8321
8322 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8323 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8324 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8325
8326 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8327 tmp &= ~(7 << 13);
8328 tmp |= (5 << 13);
8329 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8330
8331 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8332 tmp &= ~(7 << 13);
8333 tmp |= (5 << 13);
8334 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8335
8336 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8337 tmp &= ~0xFF;
8338 tmp |= 0x1C;
8339 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8340
8341 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8342 tmp &= ~0xFF;
8343 tmp |= 0x1C;
8344 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8345
8346 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8347 tmp &= ~(0xFF << 16);
8348 tmp |= (0x1C << 16);
8349 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8350
8351 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8352 tmp &= ~(0xFF << 16);
8353 tmp |= (0x1C << 16);
8354 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8355
8356 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8357 tmp |= (1 << 27);
8358 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8359
8360 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8361 tmp |= (1 << 27);
8362 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8363
8364 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8365 tmp &= ~(0xF << 28);
8366 tmp |= (4 << 28);
8367 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8368
8369 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8370 tmp &= ~(0xF << 28);
8371 tmp |= (4 << 28);
8372 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8373 }
8374
8375 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8376 * Programming" based on the parameters passed:
8377 * - Sequence to enable CLKOUT_DP
8378 * - Sequence to enable CLKOUT_DP without spread
8379 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8380 */
8381 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8382 bool with_fdi)
8383 {
8384 struct drm_i915_private *dev_priv = dev->dev_private;
8385 uint32_t reg, tmp;
8386
8387 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8388 with_spread = true;
8389 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8390 with_fdi = false;
8391
8392 mutex_lock(&dev_priv->sb_lock);
8393
8394 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8395 tmp &= ~SBI_SSCCTL_DISABLE;
8396 tmp |= SBI_SSCCTL_PATHALT;
8397 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8398
8399 udelay(24);
8400
8401 if (with_spread) {
8402 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8403 tmp &= ~SBI_SSCCTL_PATHALT;
8404 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8405
8406 if (with_fdi) {
8407 lpt_reset_fdi_mphy(dev_priv);
8408 lpt_program_fdi_mphy(dev_priv);
8409 }
8410 }
8411
8412 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8413 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8414 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8415 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8416
8417 mutex_unlock(&dev_priv->sb_lock);
8418 }
8419
8420 /* Sequence to disable CLKOUT_DP */
8421 static void lpt_disable_clkout_dp(struct drm_device *dev)
8422 {
8423 struct drm_i915_private *dev_priv = dev->dev_private;
8424 uint32_t reg, tmp;
8425
8426 mutex_lock(&dev_priv->sb_lock);
8427
8428 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8429 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8430 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8431 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8432
8433 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8434 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8435 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8436 tmp |= SBI_SSCCTL_PATHALT;
8437 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8438 udelay(32);
8439 }
8440 tmp |= SBI_SSCCTL_DISABLE;
8441 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8442 }
8443
8444 mutex_unlock(&dev_priv->sb_lock);
8445 }
8446
8447 static void lpt_init_pch_refclk(struct drm_device *dev)
8448 {
8449 struct intel_encoder *encoder;
8450 bool has_vga = false;
8451
8452 for_each_intel_encoder(dev, encoder) {
8453 switch (encoder->type) {
8454 case INTEL_OUTPUT_ANALOG:
8455 has_vga = true;
8456 break;
8457 default:
8458 break;
8459 }
8460 }
8461
8462 if (has_vga)
8463 lpt_enable_clkout_dp(dev, true, true);
8464 else
8465 lpt_disable_clkout_dp(dev);
8466 }
8467
8468 /*
8469 * Initialize reference clocks when the driver loads
8470 */
8471 void intel_init_pch_refclk(struct drm_device *dev)
8472 {
8473 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8474 ironlake_init_pch_refclk(dev);
8475 else if (HAS_PCH_LPT(dev))
8476 lpt_init_pch_refclk(dev);
8477 }
8478
8479 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8480 {
8481 struct drm_device *dev = crtc_state->base.crtc->dev;
8482 struct drm_i915_private *dev_priv = dev->dev_private;
8483 struct drm_atomic_state *state = crtc_state->base.state;
8484 struct drm_connector *connector;
8485 struct drm_connector_state *connector_state;
8486 struct intel_encoder *encoder;
8487 int num_connectors = 0, i;
8488 bool is_lvds = false;
8489
8490 for_each_connector_in_state(state, connector, connector_state, i) {
8491 if (connector_state->crtc != crtc_state->base.crtc)
8492 continue;
8493
8494 encoder = to_intel_encoder(connector_state->best_encoder);
8495
8496 switch (encoder->type) {
8497 case INTEL_OUTPUT_LVDS:
8498 is_lvds = true;
8499 break;
8500 default:
8501 break;
8502 }
8503 num_connectors++;
8504 }
8505
8506 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8507 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8508 dev_priv->vbt.lvds_ssc_freq);
8509 return dev_priv->vbt.lvds_ssc_freq;
8510 }
8511
8512 return 120000;
8513 }
8514
8515 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8516 {
8517 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8518 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8519 int pipe = intel_crtc->pipe;
8520 uint32_t val;
8521
8522 val = 0;
8523
8524 switch (intel_crtc->config->pipe_bpp) {
8525 case 18:
8526 val |= PIPECONF_6BPC;
8527 break;
8528 case 24:
8529 val |= PIPECONF_8BPC;
8530 break;
8531 case 30:
8532 val |= PIPECONF_10BPC;
8533 break;
8534 case 36:
8535 val |= PIPECONF_12BPC;
8536 break;
8537 default:
8538 /* Case prevented by intel_choose_pipe_bpp_dither. */
8539 BUG();
8540 }
8541
8542 if (intel_crtc->config->dither)
8543 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8544
8545 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8546 val |= PIPECONF_INTERLACED_ILK;
8547 else
8548 val |= PIPECONF_PROGRESSIVE;
8549
8550 if (intel_crtc->config->limited_color_range)
8551 val |= PIPECONF_COLOR_RANGE_SELECT;
8552
8553 I915_WRITE(PIPECONF(pipe), val);
8554 POSTING_READ(PIPECONF(pipe));
8555 }
8556
8557 /*
8558 * Set up the pipe CSC unit.
8559 *
8560 * Currently only full range RGB to limited range RGB conversion
8561 * is supported, but eventually this should handle various
8562 * RGB<->YCbCr scenarios as well.
8563 */
8564 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8565 {
8566 struct drm_device *dev = crtc->dev;
8567 struct drm_i915_private *dev_priv = dev->dev_private;
8568 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8569 int pipe = intel_crtc->pipe;
8570 uint16_t coeff = 0x7800; /* 1.0 */
8571
8572 /*
8573 * TODO: Check what kind of values actually come out of the pipe
8574 * with these coeff/postoff values and adjust to get the best
8575 * accuracy. Perhaps we even need to take the bpc value into
8576 * consideration.
8577 */
8578
8579 if (intel_crtc->config->limited_color_range)
8580 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8581
8582 /*
8583 * GY/GU and RY/RU should be the other way around according
8584 * to BSpec, but reality doesn't agree. Just set them up in
8585 * a way that results in the correct picture.
8586 */
8587 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8588 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8589
8590 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8591 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8592
8593 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8594 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8595
8596 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8597 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8598 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8599
8600 if (INTEL_INFO(dev)->gen > 6) {
8601 uint16_t postoff = 0;
8602
8603 if (intel_crtc->config->limited_color_range)
8604 postoff = (16 * (1 << 12) / 255) & 0x1fff;
8605
8606 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8607 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8608 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8609
8610 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8611 } else {
8612 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8613
8614 if (intel_crtc->config->limited_color_range)
8615 mode |= CSC_BLACK_SCREEN_OFFSET;
8616
8617 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8618 }
8619 }
8620
8621 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8622 {
8623 struct drm_device *dev = crtc->dev;
8624 struct drm_i915_private *dev_priv = dev->dev_private;
8625 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8626 enum pipe pipe = intel_crtc->pipe;
8627 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8628 uint32_t val;
8629
8630 val = 0;
8631
8632 if (IS_HASWELL(dev) && intel_crtc->config->dither)
8633 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8634
8635 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8636 val |= PIPECONF_INTERLACED_ILK;
8637 else
8638 val |= PIPECONF_PROGRESSIVE;
8639
8640 I915_WRITE(PIPECONF(cpu_transcoder), val);
8641 POSTING_READ(PIPECONF(cpu_transcoder));
8642
8643 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8644 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8645
8646 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8647 val = 0;
8648
8649 switch (intel_crtc->config->pipe_bpp) {
8650 case 18:
8651 val |= PIPEMISC_DITHER_6_BPC;
8652 break;
8653 case 24:
8654 val |= PIPEMISC_DITHER_8_BPC;
8655 break;
8656 case 30:
8657 val |= PIPEMISC_DITHER_10_BPC;
8658 break;
8659 case 36:
8660 val |= PIPEMISC_DITHER_12_BPC;
8661 break;
8662 default:
8663 /* Case prevented by pipe_config_set_bpp. */
8664 BUG();
8665 }
8666
8667 if (intel_crtc->config->dither)
8668 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8669
8670 I915_WRITE(PIPEMISC(pipe), val);
8671 }
8672 }
8673
8674 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8675 struct intel_crtc_state *crtc_state,
8676 intel_clock_t *clock,
8677 bool *has_reduced_clock,
8678 intel_clock_t *reduced_clock)
8679 {
8680 struct drm_device *dev = crtc->dev;
8681 struct drm_i915_private *dev_priv = dev->dev_private;
8682 int refclk;
8683 const intel_limit_t *limit;
8684 bool ret;
8685
8686 refclk = ironlake_get_refclk(crtc_state);
8687
8688 /*
8689 * Returns a set of divisors for the desired target clock with the given
8690 * refclk, or FALSE. The returned values represent the clock equation:
8691 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8692 */
8693 limit = intel_limit(crtc_state, refclk);
8694 ret = dev_priv->display.find_dpll(limit, crtc_state,
8695 crtc_state->port_clock,
8696 refclk, NULL, clock);
8697 if (!ret)
8698 return false;
8699
8700 return true;
8701 }
8702
8703 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8704 {
8705 /*
8706 * Account for spread spectrum to avoid
8707 * oversubscribing the link. Max center spread
8708 * is 2.5%; use 5% for safety's sake.
8709 */
8710 u32 bps = target_clock * bpp * 21 / 20;
8711 return DIV_ROUND_UP(bps, link_bw * 8);
8712 }
8713
8714 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8715 {
8716 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8717 }
8718
8719 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8720 struct intel_crtc_state *crtc_state,
8721 u32 *fp,
8722 intel_clock_t *reduced_clock, u32 *fp2)
8723 {
8724 struct drm_crtc *crtc = &intel_crtc->base;
8725 struct drm_device *dev = crtc->dev;
8726 struct drm_i915_private *dev_priv = dev->dev_private;
8727 struct drm_atomic_state *state = crtc_state->base.state;
8728 struct drm_connector *connector;
8729 struct drm_connector_state *connector_state;
8730 struct intel_encoder *encoder;
8731 uint32_t dpll;
8732 int factor, num_connectors = 0, i;
8733 bool is_lvds = false, is_sdvo = false;
8734
8735 for_each_connector_in_state(state, connector, connector_state, i) {
8736 if (connector_state->crtc != crtc_state->base.crtc)
8737 continue;
8738
8739 encoder = to_intel_encoder(connector_state->best_encoder);
8740
8741 switch (encoder->type) {
8742 case INTEL_OUTPUT_LVDS:
8743 is_lvds = true;
8744 break;
8745 case INTEL_OUTPUT_SDVO:
8746 case INTEL_OUTPUT_HDMI:
8747 is_sdvo = true;
8748 break;
8749 default:
8750 break;
8751 }
8752
8753 num_connectors++;
8754 }
8755
8756 /* Enable autotuning of the PLL clock (if permissible) */
8757 factor = 21;
8758 if (is_lvds) {
8759 if ((intel_panel_use_ssc(dev_priv) &&
8760 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8761 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8762 factor = 25;
8763 } else if (crtc_state->sdvo_tv_clock)
8764 factor = 20;
8765
8766 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8767 *fp |= FP_CB_TUNE;
8768
8769 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8770 *fp2 |= FP_CB_TUNE;
8771
8772 dpll = 0;
8773
8774 if (is_lvds)
8775 dpll |= DPLLB_MODE_LVDS;
8776 else
8777 dpll |= DPLLB_MODE_DAC_SERIAL;
8778
8779 dpll |= (crtc_state->pixel_multiplier - 1)
8780 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8781
8782 if (is_sdvo)
8783 dpll |= DPLL_SDVO_HIGH_SPEED;
8784 if (crtc_state->has_dp_encoder)
8785 dpll |= DPLL_SDVO_HIGH_SPEED;
8786
8787 /* compute bitmask from p1 value */
8788 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8789 /* also FPA1 */
8790 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8791
8792 switch (crtc_state->dpll.p2) {
8793 case 5:
8794 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8795 break;
8796 case 7:
8797 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8798 break;
8799 case 10:
8800 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8801 break;
8802 case 14:
8803 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8804 break;
8805 }
8806
8807 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8808 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8809 else
8810 dpll |= PLL_REF_INPUT_DREFCLK;
8811
8812 return dpll | DPLL_VCO_ENABLE;
8813 }
8814
8815 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8816 struct intel_crtc_state *crtc_state)
8817 {
8818 struct drm_device *dev = crtc->base.dev;
8819 intel_clock_t clock, reduced_clock;
8820 u32 dpll = 0, fp = 0, fp2 = 0;
8821 bool ok, has_reduced_clock = false;
8822 bool is_lvds = false;
8823 struct intel_shared_dpll *pll;
8824
8825 memset(&crtc_state->dpll_hw_state, 0,
8826 sizeof(crtc_state->dpll_hw_state));
8827
8828 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8829
8830 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8831 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8832
8833 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8834 &has_reduced_clock, &reduced_clock);
8835 if (!ok && !crtc_state->clock_set) {
8836 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8837 return -EINVAL;
8838 }
8839 /* Compat-code for transition, will disappear. */
8840 if (!crtc_state->clock_set) {
8841 crtc_state->dpll.n = clock.n;
8842 crtc_state->dpll.m1 = clock.m1;
8843 crtc_state->dpll.m2 = clock.m2;
8844 crtc_state->dpll.p1 = clock.p1;
8845 crtc_state->dpll.p2 = clock.p2;
8846 }
8847
8848 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8849 if (crtc_state->has_pch_encoder) {
8850 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8851 if (has_reduced_clock)
8852 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8853
8854 dpll = ironlake_compute_dpll(crtc, crtc_state,
8855 &fp, &reduced_clock,
8856 has_reduced_clock ? &fp2 : NULL);
8857
8858 crtc_state->dpll_hw_state.dpll = dpll;
8859 crtc_state->dpll_hw_state.fp0 = fp;
8860 if (has_reduced_clock)
8861 crtc_state->dpll_hw_state.fp1 = fp2;
8862 else
8863 crtc_state->dpll_hw_state.fp1 = fp;
8864
8865 pll = intel_get_shared_dpll(crtc, crtc_state);
8866 if (pll == NULL) {
8867 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8868 pipe_name(crtc->pipe));
8869 return -EINVAL;
8870 }
8871 }
8872
8873 if (is_lvds && has_reduced_clock)
8874 crtc->lowfreq_avail = true;
8875 else
8876 crtc->lowfreq_avail = false;
8877
8878 return 0;
8879 }
8880
8881 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8882 struct intel_link_m_n *m_n)
8883 {
8884 struct drm_device *dev = crtc->base.dev;
8885 struct drm_i915_private *dev_priv = dev->dev_private;
8886 enum pipe pipe = crtc->pipe;
8887
8888 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8889 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8890 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8891 & ~TU_SIZE_MASK;
8892 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8893 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8894 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8895 }
8896
8897 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8898 enum transcoder transcoder,
8899 struct intel_link_m_n *m_n,
8900 struct intel_link_m_n *m2_n2)
8901 {
8902 struct drm_device *dev = crtc->base.dev;
8903 struct drm_i915_private *dev_priv = dev->dev_private;
8904 enum pipe pipe = crtc->pipe;
8905
8906 if (INTEL_INFO(dev)->gen >= 5) {
8907 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8908 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8909 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8910 & ~TU_SIZE_MASK;
8911 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8912 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8913 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8914 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8915 * gen < 8) and if DRRS is supported (to make sure the
8916 * registers are not unnecessarily read).
8917 */
8918 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8919 crtc->config->has_drrs) {
8920 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8921 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8922 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8923 & ~TU_SIZE_MASK;
8924 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8925 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8926 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8927 }
8928 } else {
8929 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8930 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8931 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8932 & ~TU_SIZE_MASK;
8933 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8934 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8935 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8936 }
8937 }
8938
8939 void intel_dp_get_m_n(struct intel_crtc *crtc,
8940 struct intel_crtc_state *pipe_config)
8941 {
8942 if (pipe_config->has_pch_encoder)
8943 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8944 else
8945 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8946 &pipe_config->dp_m_n,
8947 &pipe_config->dp_m2_n2);
8948 }
8949
8950 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8951 struct intel_crtc_state *pipe_config)
8952 {
8953 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8954 &pipe_config->fdi_m_n, NULL);
8955 }
8956
8957 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8958 struct intel_crtc_state *pipe_config)
8959 {
8960 struct drm_device *dev = crtc->base.dev;
8961 struct drm_i915_private *dev_priv = dev->dev_private;
8962 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8963 uint32_t ps_ctrl = 0;
8964 int id = -1;
8965 int i;
8966
8967 /* find scaler attached to this pipe */
8968 for (i = 0; i < crtc->num_scalers; i++) {
8969 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8970 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8971 id = i;
8972 pipe_config->pch_pfit.enabled = true;
8973 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8974 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8975 break;
8976 }
8977 }
8978
8979 scaler_state->scaler_id = id;
8980 if (id >= 0) {
8981 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8982 } else {
8983 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8984 }
8985 }
8986
8987 static void
8988 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8989 struct intel_initial_plane_config *plane_config)
8990 {
8991 struct drm_device *dev = crtc->base.dev;
8992 struct drm_i915_private *dev_priv = dev->dev_private;
8993 u32 val, base, offset, stride_mult, tiling;
8994 int pipe = crtc->pipe;
8995 int fourcc, pixel_format;
8996 unsigned int aligned_height;
8997 struct drm_framebuffer *fb;
8998 struct intel_framebuffer *intel_fb;
8999
9000 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9001 if (!intel_fb) {
9002 DRM_DEBUG_KMS("failed to alloc fb\n");
9003 return;
9004 }
9005
9006 fb = &intel_fb->base;
9007
9008 val = I915_READ(PLANE_CTL(pipe, 0));
9009 if (!(val & PLANE_CTL_ENABLE))
9010 goto error;
9011
9012 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9013 fourcc = skl_format_to_fourcc(pixel_format,
9014 val & PLANE_CTL_ORDER_RGBX,
9015 val & PLANE_CTL_ALPHA_MASK);
9016 fb->pixel_format = fourcc;
9017 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9018
9019 tiling = val & PLANE_CTL_TILED_MASK;
9020 switch (tiling) {
9021 case PLANE_CTL_TILED_LINEAR:
9022 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9023 break;
9024 case PLANE_CTL_TILED_X:
9025 plane_config->tiling = I915_TILING_X;
9026 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9027 break;
9028 case PLANE_CTL_TILED_Y:
9029 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9030 break;
9031 case PLANE_CTL_TILED_YF:
9032 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9033 break;
9034 default:
9035 MISSING_CASE(tiling);
9036 goto error;
9037 }
9038
9039 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9040 plane_config->base = base;
9041
9042 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9043
9044 val = I915_READ(PLANE_SIZE(pipe, 0));
9045 fb->height = ((val >> 16) & 0xfff) + 1;
9046 fb->width = ((val >> 0) & 0x1fff) + 1;
9047
9048 val = I915_READ(PLANE_STRIDE(pipe, 0));
9049 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9050 fb->pixel_format);
9051 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9052
9053 aligned_height = intel_fb_align_height(dev, fb->height,
9054 fb->pixel_format,
9055 fb->modifier[0]);
9056
9057 plane_config->size = fb->pitches[0] * aligned_height;
9058
9059 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9060 pipe_name(pipe), fb->width, fb->height,
9061 fb->bits_per_pixel, base, fb->pitches[0],
9062 plane_config->size);
9063
9064 plane_config->fb = intel_fb;
9065 return;
9066
9067 error:
9068 kfree(fb);
9069 }
9070
9071 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9072 struct intel_crtc_state *pipe_config)
9073 {
9074 struct drm_device *dev = crtc->base.dev;
9075 struct drm_i915_private *dev_priv = dev->dev_private;
9076 uint32_t tmp;
9077
9078 tmp = I915_READ(PF_CTL(crtc->pipe));
9079
9080 if (tmp & PF_ENABLE) {
9081 pipe_config->pch_pfit.enabled = true;
9082 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9083 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9084
9085 /* We currently do not free assignements of panel fitters on
9086 * ivb/hsw (since we don't use the higher upscaling modes which
9087 * differentiates them) so just WARN about this case for now. */
9088 if (IS_GEN7(dev)) {
9089 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9090 PF_PIPE_SEL_IVB(crtc->pipe));
9091 }
9092 }
9093 }
9094
9095 static void
9096 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9097 struct intel_initial_plane_config *plane_config)
9098 {
9099 struct drm_device *dev = crtc->base.dev;
9100 struct drm_i915_private *dev_priv = dev->dev_private;
9101 u32 val, base, offset;
9102 int pipe = crtc->pipe;
9103 int fourcc, pixel_format;
9104 unsigned int aligned_height;
9105 struct drm_framebuffer *fb;
9106 struct intel_framebuffer *intel_fb;
9107
9108 val = I915_READ(DSPCNTR(pipe));
9109 if (!(val & DISPLAY_PLANE_ENABLE))
9110 return;
9111
9112 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9113 if (!intel_fb) {
9114 DRM_DEBUG_KMS("failed to alloc fb\n");
9115 return;
9116 }
9117
9118 fb = &intel_fb->base;
9119
9120 if (INTEL_INFO(dev)->gen >= 4) {
9121 if (val & DISPPLANE_TILED) {
9122 plane_config->tiling = I915_TILING_X;
9123 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9124 }
9125 }
9126
9127 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9128 fourcc = i9xx_format_to_fourcc(pixel_format);
9129 fb->pixel_format = fourcc;
9130 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9131
9132 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9133 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9134 offset = I915_READ(DSPOFFSET(pipe));
9135 } else {
9136 if (plane_config->tiling)
9137 offset = I915_READ(DSPTILEOFF(pipe));
9138 else
9139 offset = I915_READ(DSPLINOFF(pipe));
9140 }
9141 plane_config->base = base;
9142
9143 val = I915_READ(PIPESRC(pipe));
9144 fb->width = ((val >> 16) & 0xfff) + 1;
9145 fb->height = ((val >> 0) & 0xfff) + 1;
9146
9147 val = I915_READ(DSPSTRIDE(pipe));
9148 fb->pitches[0] = val & 0xffffffc0;
9149
9150 aligned_height = intel_fb_align_height(dev, fb->height,
9151 fb->pixel_format,
9152 fb->modifier[0]);
9153
9154 plane_config->size = fb->pitches[0] * aligned_height;
9155
9156 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9157 pipe_name(pipe), fb->width, fb->height,
9158 fb->bits_per_pixel, base, fb->pitches[0],
9159 plane_config->size);
9160
9161 plane_config->fb = intel_fb;
9162 }
9163
9164 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9165 struct intel_crtc_state *pipe_config)
9166 {
9167 struct drm_device *dev = crtc->base.dev;
9168 struct drm_i915_private *dev_priv = dev->dev_private;
9169 uint32_t tmp;
9170
9171 if (!intel_display_power_is_enabled(dev_priv,
9172 POWER_DOMAIN_PIPE(crtc->pipe)))
9173 return false;
9174
9175 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9176 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9177
9178 tmp = I915_READ(PIPECONF(crtc->pipe));
9179 if (!(tmp & PIPECONF_ENABLE))
9180 return false;
9181
9182 switch (tmp & PIPECONF_BPC_MASK) {
9183 case PIPECONF_6BPC:
9184 pipe_config->pipe_bpp = 18;
9185 break;
9186 case PIPECONF_8BPC:
9187 pipe_config->pipe_bpp = 24;
9188 break;
9189 case PIPECONF_10BPC:
9190 pipe_config->pipe_bpp = 30;
9191 break;
9192 case PIPECONF_12BPC:
9193 pipe_config->pipe_bpp = 36;
9194 break;
9195 default:
9196 break;
9197 }
9198
9199 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9200 pipe_config->limited_color_range = true;
9201
9202 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9203 struct intel_shared_dpll *pll;
9204
9205 pipe_config->has_pch_encoder = true;
9206
9207 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9208 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9209 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9210
9211 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9212
9213 if (HAS_PCH_IBX(dev_priv->dev)) {
9214 pipe_config->shared_dpll =
9215 (enum intel_dpll_id) crtc->pipe;
9216 } else {
9217 tmp = I915_READ(PCH_DPLL_SEL);
9218 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9219 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9220 else
9221 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9222 }
9223
9224 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9225
9226 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9227 &pipe_config->dpll_hw_state));
9228
9229 tmp = pipe_config->dpll_hw_state.dpll;
9230 pipe_config->pixel_multiplier =
9231 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9232 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9233
9234 ironlake_pch_clock_get(crtc, pipe_config);
9235 } else {
9236 pipe_config->pixel_multiplier = 1;
9237 }
9238
9239 intel_get_pipe_timings(crtc, pipe_config);
9240
9241 ironlake_get_pfit_config(crtc, pipe_config);
9242
9243 return true;
9244 }
9245
9246 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9247 {
9248 struct drm_device *dev = dev_priv->dev;
9249 struct intel_crtc *crtc;
9250
9251 for_each_intel_crtc(dev, crtc)
9252 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9253 pipe_name(crtc->pipe));
9254
9255 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9256 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9257 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9258 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9259 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9260 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9261 "CPU PWM1 enabled\n");
9262 if (IS_HASWELL(dev))
9263 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9264 "CPU PWM2 enabled\n");
9265 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9266 "PCH PWM1 enabled\n");
9267 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9268 "Utility pin enabled\n");
9269 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9270
9271 /*
9272 * In theory we can still leave IRQs enabled, as long as only the HPD
9273 * interrupts remain enabled. We used to check for that, but since it's
9274 * gen-specific and since we only disable LCPLL after we fully disable
9275 * the interrupts, the check below should be enough.
9276 */
9277 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9278 }
9279
9280 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9281 {
9282 struct drm_device *dev = dev_priv->dev;
9283
9284 if (IS_HASWELL(dev))
9285 return I915_READ(D_COMP_HSW);
9286 else
9287 return I915_READ(D_COMP_BDW);
9288 }
9289
9290 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9291 {
9292 struct drm_device *dev = dev_priv->dev;
9293
9294 if (IS_HASWELL(dev)) {
9295 mutex_lock(&dev_priv->rps.hw_lock);
9296 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9297 val))
9298 DRM_ERROR("Failed to write to D_COMP\n");
9299 mutex_unlock(&dev_priv->rps.hw_lock);
9300 } else {
9301 I915_WRITE(D_COMP_BDW, val);
9302 POSTING_READ(D_COMP_BDW);
9303 }
9304 }
9305
9306 /*
9307 * This function implements pieces of two sequences from BSpec:
9308 * - Sequence for display software to disable LCPLL
9309 * - Sequence for display software to allow package C8+
9310 * The steps implemented here are just the steps that actually touch the LCPLL
9311 * register. Callers should take care of disabling all the display engine
9312 * functions, doing the mode unset, fixing interrupts, etc.
9313 */
9314 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9315 bool switch_to_fclk, bool allow_power_down)
9316 {
9317 uint32_t val;
9318
9319 assert_can_disable_lcpll(dev_priv);
9320
9321 val = I915_READ(LCPLL_CTL);
9322
9323 if (switch_to_fclk) {
9324 val |= LCPLL_CD_SOURCE_FCLK;
9325 I915_WRITE(LCPLL_CTL, val);
9326
9327 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9328 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9329 DRM_ERROR("Switching to FCLK failed\n");
9330
9331 val = I915_READ(LCPLL_CTL);
9332 }
9333
9334 val |= LCPLL_PLL_DISABLE;
9335 I915_WRITE(LCPLL_CTL, val);
9336 POSTING_READ(LCPLL_CTL);
9337
9338 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9339 DRM_ERROR("LCPLL still locked\n");
9340
9341 val = hsw_read_dcomp(dev_priv);
9342 val |= D_COMP_COMP_DISABLE;
9343 hsw_write_dcomp(dev_priv, val);
9344 ndelay(100);
9345
9346 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9347 1))
9348 DRM_ERROR("D_COMP RCOMP still in progress\n");
9349
9350 if (allow_power_down) {
9351 val = I915_READ(LCPLL_CTL);
9352 val |= LCPLL_POWER_DOWN_ALLOW;
9353 I915_WRITE(LCPLL_CTL, val);
9354 POSTING_READ(LCPLL_CTL);
9355 }
9356 }
9357
9358 /*
9359 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9360 * source.
9361 */
9362 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9363 {
9364 uint32_t val;
9365
9366 val = I915_READ(LCPLL_CTL);
9367
9368 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9369 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9370 return;
9371
9372 /*
9373 * Make sure we're not on PC8 state before disabling PC8, otherwise
9374 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9375 */
9376 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9377
9378 if (val & LCPLL_POWER_DOWN_ALLOW) {
9379 val &= ~LCPLL_POWER_DOWN_ALLOW;
9380 I915_WRITE(LCPLL_CTL, val);
9381 POSTING_READ(LCPLL_CTL);
9382 }
9383
9384 val = hsw_read_dcomp(dev_priv);
9385 val |= D_COMP_COMP_FORCE;
9386 val &= ~D_COMP_COMP_DISABLE;
9387 hsw_write_dcomp(dev_priv, val);
9388
9389 val = I915_READ(LCPLL_CTL);
9390 val &= ~LCPLL_PLL_DISABLE;
9391 I915_WRITE(LCPLL_CTL, val);
9392
9393 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9394 DRM_ERROR("LCPLL not locked yet\n");
9395
9396 if (val & LCPLL_CD_SOURCE_FCLK) {
9397 val = I915_READ(LCPLL_CTL);
9398 val &= ~LCPLL_CD_SOURCE_FCLK;
9399 I915_WRITE(LCPLL_CTL, val);
9400
9401 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9402 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9403 DRM_ERROR("Switching back to LCPLL failed\n");
9404 }
9405
9406 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9407 intel_update_cdclk(dev_priv->dev);
9408 }
9409
9410 /*
9411 * Package states C8 and deeper are really deep PC states that can only be
9412 * reached when all the devices on the system allow it, so even if the graphics
9413 * device allows PC8+, it doesn't mean the system will actually get to these
9414 * states. Our driver only allows PC8+ when going into runtime PM.
9415 *
9416 * The requirements for PC8+ are that all the outputs are disabled, the power
9417 * well is disabled and most interrupts are disabled, and these are also
9418 * requirements for runtime PM. When these conditions are met, we manually do
9419 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9420 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9421 * hang the machine.
9422 *
9423 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9424 * the state of some registers, so when we come back from PC8+ we need to
9425 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9426 * need to take care of the registers kept by RC6. Notice that this happens even
9427 * if we don't put the device in PCI D3 state (which is what currently happens
9428 * because of the runtime PM support).
9429 *
9430 * For more, read "Display Sequences for Package C8" on the hardware
9431 * documentation.
9432 */
9433 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9434 {
9435 struct drm_device *dev = dev_priv->dev;
9436 uint32_t val;
9437
9438 DRM_DEBUG_KMS("Enabling package C8+\n");
9439
9440 if (HAS_PCH_LPT_LP(dev)) {
9441 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9442 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9443 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9444 }
9445
9446 lpt_disable_clkout_dp(dev);
9447 hsw_disable_lcpll(dev_priv, true, true);
9448 }
9449
9450 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9451 {
9452 struct drm_device *dev = dev_priv->dev;
9453 uint32_t val;
9454
9455 DRM_DEBUG_KMS("Disabling package C8+\n");
9456
9457 hsw_restore_lcpll(dev_priv);
9458 lpt_init_pch_refclk(dev);
9459
9460 if (HAS_PCH_LPT_LP(dev)) {
9461 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9462 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9463 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9464 }
9465
9466 intel_prepare_ddi(dev);
9467 }
9468
9469 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9470 {
9471 struct drm_device *dev = old_state->dev;
9472 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9473
9474 broxton_set_cdclk(dev, req_cdclk);
9475 }
9476
9477 /* compute the max rate for new configuration */
9478 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9479 {
9480 struct intel_crtc *intel_crtc;
9481 struct intel_crtc_state *crtc_state;
9482 int max_pixel_rate = 0;
9483
9484 for_each_intel_crtc(state->dev, intel_crtc) {
9485 int pixel_rate;
9486
9487 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9488 if (IS_ERR(crtc_state))
9489 return PTR_ERR(crtc_state);
9490
9491 if (!crtc_state->base.enable)
9492 continue;
9493
9494 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9495
9496 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9497 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9498 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9499
9500 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9501 }
9502
9503 return max_pixel_rate;
9504 }
9505
9506 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9507 {
9508 struct drm_i915_private *dev_priv = dev->dev_private;
9509 uint32_t val, data;
9510 int ret;
9511
9512 if (WARN((I915_READ(LCPLL_CTL) &
9513 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9514 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9515 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9516 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9517 "trying to change cdclk frequency with cdclk not enabled\n"))
9518 return;
9519
9520 mutex_lock(&dev_priv->rps.hw_lock);
9521 ret = sandybridge_pcode_write(dev_priv,
9522 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9523 mutex_unlock(&dev_priv->rps.hw_lock);
9524 if (ret) {
9525 DRM_ERROR("failed to inform pcode about cdclk change\n");
9526 return;
9527 }
9528
9529 val = I915_READ(LCPLL_CTL);
9530 val |= LCPLL_CD_SOURCE_FCLK;
9531 I915_WRITE(LCPLL_CTL, val);
9532
9533 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9534 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9535 DRM_ERROR("Switching to FCLK failed\n");
9536
9537 val = I915_READ(LCPLL_CTL);
9538 val &= ~LCPLL_CLK_FREQ_MASK;
9539
9540 switch (cdclk) {
9541 case 450000:
9542 val |= LCPLL_CLK_FREQ_450;
9543 data = 0;
9544 break;
9545 case 540000:
9546 val |= LCPLL_CLK_FREQ_54O_BDW;
9547 data = 1;
9548 break;
9549 case 337500:
9550 val |= LCPLL_CLK_FREQ_337_5_BDW;
9551 data = 2;
9552 break;
9553 case 675000:
9554 val |= LCPLL_CLK_FREQ_675_BDW;
9555 data = 3;
9556 break;
9557 default:
9558 WARN(1, "invalid cdclk frequency\n");
9559 return;
9560 }
9561
9562 I915_WRITE(LCPLL_CTL, val);
9563
9564 val = I915_READ(LCPLL_CTL);
9565 val &= ~LCPLL_CD_SOURCE_FCLK;
9566 I915_WRITE(LCPLL_CTL, val);
9567
9568 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9569 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9570 DRM_ERROR("Switching back to LCPLL failed\n");
9571
9572 mutex_lock(&dev_priv->rps.hw_lock);
9573 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9574 mutex_unlock(&dev_priv->rps.hw_lock);
9575
9576 intel_update_cdclk(dev);
9577
9578 WARN(cdclk != dev_priv->cdclk_freq,
9579 "cdclk requested %d kHz but got %d kHz\n",
9580 cdclk, dev_priv->cdclk_freq);
9581 }
9582
9583 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9584 {
9585 struct drm_i915_private *dev_priv = to_i915(state->dev);
9586 int max_pixclk = ilk_max_pixel_rate(state);
9587 int cdclk;
9588
9589 /*
9590 * FIXME should also account for plane ratio
9591 * once 64bpp pixel formats are supported.
9592 */
9593 if (max_pixclk > 540000)
9594 cdclk = 675000;
9595 else if (max_pixclk > 450000)
9596 cdclk = 540000;
9597 else if (max_pixclk > 337500)
9598 cdclk = 450000;
9599 else
9600 cdclk = 337500;
9601
9602 /*
9603 * FIXME move the cdclk caclulation to
9604 * compute_config() so we can fail gracegully.
9605 */
9606 if (cdclk > dev_priv->max_cdclk_freq) {
9607 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9608 cdclk, dev_priv->max_cdclk_freq);
9609 cdclk = dev_priv->max_cdclk_freq;
9610 }
9611
9612 to_intel_atomic_state(state)->cdclk = cdclk;
9613
9614 return 0;
9615 }
9616
9617 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9618 {
9619 struct drm_device *dev = old_state->dev;
9620 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9621
9622 broadwell_set_cdclk(dev, req_cdclk);
9623 }
9624
9625 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9626 struct intel_crtc_state *crtc_state)
9627 {
9628 if (!intel_ddi_pll_select(crtc, crtc_state))
9629 return -EINVAL;
9630
9631 crtc->lowfreq_avail = false;
9632
9633 return 0;
9634 }
9635
9636 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9637 enum port port,
9638 struct intel_crtc_state *pipe_config)
9639 {
9640 switch (port) {
9641 case PORT_A:
9642 pipe_config->ddi_pll_sel = SKL_DPLL0;
9643 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9644 break;
9645 case PORT_B:
9646 pipe_config->ddi_pll_sel = SKL_DPLL1;
9647 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9648 break;
9649 case PORT_C:
9650 pipe_config->ddi_pll_sel = SKL_DPLL2;
9651 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9652 break;
9653 default:
9654 DRM_ERROR("Incorrect port type\n");
9655 }
9656 }
9657
9658 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9659 enum port port,
9660 struct intel_crtc_state *pipe_config)
9661 {
9662 u32 temp, dpll_ctl1;
9663
9664 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9665 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9666
9667 switch (pipe_config->ddi_pll_sel) {
9668 case SKL_DPLL0:
9669 /*
9670 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9671 * of the shared DPLL framework and thus needs to be read out
9672 * separately
9673 */
9674 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9675 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9676 break;
9677 case SKL_DPLL1:
9678 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9679 break;
9680 case SKL_DPLL2:
9681 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9682 break;
9683 case SKL_DPLL3:
9684 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9685 break;
9686 }
9687 }
9688
9689 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9690 enum port port,
9691 struct intel_crtc_state *pipe_config)
9692 {
9693 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9694
9695 switch (pipe_config->ddi_pll_sel) {
9696 case PORT_CLK_SEL_WRPLL1:
9697 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9698 break;
9699 case PORT_CLK_SEL_WRPLL2:
9700 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9701 break;
9702 }
9703 }
9704
9705 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9706 struct intel_crtc_state *pipe_config)
9707 {
9708 struct drm_device *dev = crtc->base.dev;
9709 struct drm_i915_private *dev_priv = dev->dev_private;
9710 struct intel_shared_dpll *pll;
9711 enum port port;
9712 uint32_t tmp;
9713
9714 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9715
9716 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9717
9718 if (IS_SKYLAKE(dev))
9719 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9720 else if (IS_BROXTON(dev))
9721 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9722 else
9723 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9724
9725 if (pipe_config->shared_dpll >= 0) {
9726 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9727
9728 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9729 &pipe_config->dpll_hw_state));
9730 }
9731
9732 /*
9733 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9734 * DDI E. So just check whether this pipe is wired to DDI E and whether
9735 * the PCH transcoder is on.
9736 */
9737 if (INTEL_INFO(dev)->gen < 9 &&
9738 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9739 pipe_config->has_pch_encoder = true;
9740
9741 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9742 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9743 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9744
9745 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9746 }
9747 }
9748
9749 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9750 struct intel_crtc_state *pipe_config)
9751 {
9752 struct drm_device *dev = crtc->base.dev;
9753 struct drm_i915_private *dev_priv = dev->dev_private;
9754 enum intel_display_power_domain pfit_domain;
9755 uint32_t tmp;
9756
9757 if (!intel_display_power_is_enabled(dev_priv,
9758 POWER_DOMAIN_PIPE(crtc->pipe)))
9759 return false;
9760
9761 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9762 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9763
9764 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9765 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9766 enum pipe trans_edp_pipe;
9767 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9768 default:
9769 WARN(1, "unknown pipe linked to edp transcoder\n");
9770 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9771 case TRANS_DDI_EDP_INPUT_A_ON:
9772 trans_edp_pipe = PIPE_A;
9773 break;
9774 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9775 trans_edp_pipe = PIPE_B;
9776 break;
9777 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9778 trans_edp_pipe = PIPE_C;
9779 break;
9780 }
9781
9782 if (trans_edp_pipe == crtc->pipe)
9783 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9784 }
9785
9786 if (!intel_display_power_is_enabled(dev_priv,
9787 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9788 return false;
9789
9790 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9791 if (!(tmp & PIPECONF_ENABLE))
9792 return false;
9793
9794 haswell_get_ddi_port_state(crtc, pipe_config);
9795
9796 intel_get_pipe_timings(crtc, pipe_config);
9797
9798 if (INTEL_INFO(dev)->gen >= 9) {
9799 skl_init_scalers(dev, crtc, pipe_config);
9800 }
9801
9802 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9803
9804 if (INTEL_INFO(dev)->gen >= 9) {
9805 pipe_config->scaler_state.scaler_id = -1;
9806 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9807 }
9808
9809 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9810 if (INTEL_INFO(dev)->gen >= 9)
9811 skylake_get_pfit_config(crtc, pipe_config);
9812 else
9813 ironlake_get_pfit_config(crtc, pipe_config);
9814 }
9815
9816 if (IS_HASWELL(dev))
9817 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9818 (I915_READ(IPS_CTL) & IPS_ENABLE);
9819
9820 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9821 pipe_config->pixel_multiplier =
9822 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9823 } else {
9824 pipe_config->pixel_multiplier = 1;
9825 }
9826
9827 return true;
9828 }
9829
9830 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9831 {
9832 struct drm_device *dev = crtc->dev;
9833 struct drm_i915_private *dev_priv = dev->dev_private;
9834 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9835 uint32_t cntl = 0, size = 0;
9836
9837 if (base) {
9838 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9839 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9840 unsigned int stride = roundup_pow_of_two(width) * 4;
9841
9842 switch (stride) {
9843 default:
9844 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9845 width, stride);
9846 stride = 256;
9847 /* fallthrough */
9848 case 256:
9849 case 512:
9850 case 1024:
9851 case 2048:
9852 break;
9853 }
9854
9855 cntl |= CURSOR_ENABLE |
9856 CURSOR_GAMMA_ENABLE |
9857 CURSOR_FORMAT_ARGB |
9858 CURSOR_STRIDE(stride);
9859
9860 size = (height << 12) | width;
9861 }
9862
9863 if (intel_crtc->cursor_cntl != 0 &&
9864 (intel_crtc->cursor_base != base ||
9865 intel_crtc->cursor_size != size ||
9866 intel_crtc->cursor_cntl != cntl)) {
9867 /* On these chipsets we can only modify the base/size/stride
9868 * whilst the cursor is disabled.
9869 */
9870 I915_WRITE(CURCNTR(PIPE_A), 0);
9871 POSTING_READ(CURCNTR(PIPE_A));
9872 intel_crtc->cursor_cntl = 0;
9873 }
9874
9875 if (intel_crtc->cursor_base != base) {
9876 I915_WRITE(CURBASE(PIPE_A), base);
9877 intel_crtc->cursor_base = base;
9878 }
9879
9880 if (intel_crtc->cursor_size != size) {
9881 I915_WRITE(CURSIZE, size);
9882 intel_crtc->cursor_size = size;
9883 }
9884
9885 if (intel_crtc->cursor_cntl != cntl) {
9886 I915_WRITE(CURCNTR(PIPE_A), cntl);
9887 POSTING_READ(CURCNTR(PIPE_A));
9888 intel_crtc->cursor_cntl = cntl;
9889 }
9890 }
9891
9892 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9893 {
9894 struct drm_device *dev = crtc->dev;
9895 struct drm_i915_private *dev_priv = dev->dev_private;
9896 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9897 int pipe = intel_crtc->pipe;
9898 uint32_t cntl;
9899
9900 cntl = 0;
9901 if (base) {
9902 cntl = MCURSOR_GAMMA_ENABLE;
9903 switch (intel_crtc->base.cursor->state->crtc_w) {
9904 case 64:
9905 cntl |= CURSOR_MODE_64_ARGB_AX;
9906 break;
9907 case 128:
9908 cntl |= CURSOR_MODE_128_ARGB_AX;
9909 break;
9910 case 256:
9911 cntl |= CURSOR_MODE_256_ARGB_AX;
9912 break;
9913 default:
9914 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9915 return;
9916 }
9917 cntl |= pipe << 28; /* Connect to correct pipe */
9918
9919 if (HAS_DDI(dev))
9920 cntl |= CURSOR_PIPE_CSC_ENABLE;
9921 }
9922
9923 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
9924 cntl |= CURSOR_ROTATE_180;
9925
9926 if (intel_crtc->cursor_cntl != cntl) {
9927 I915_WRITE(CURCNTR(pipe), cntl);
9928 POSTING_READ(CURCNTR(pipe));
9929 intel_crtc->cursor_cntl = cntl;
9930 }
9931
9932 /* and commit changes on next vblank */
9933 I915_WRITE(CURBASE(pipe), base);
9934 POSTING_READ(CURBASE(pipe));
9935
9936 intel_crtc->cursor_base = base;
9937 }
9938
9939 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9940 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9941 bool on)
9942 {
9943 struct drm_device *dev = crtc->dev;
9944 struct drm_i915_private *dev_priv = dev->dev_private;
9945 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9946 int pipe = intel_crtc->pipe;
9947 struct drm_plane_state *cursor_state = crtc->cursor->state;
9948 int x = cursor_state->crtc_x;
9949 int y = cursor_state->crtc_y;
9950 u32 base = 0, pos = 0;
9951
9952 if (on)
9953 base = intel_crtc->cursor_addr;
9954
9955 if (x >= intel_crtc->config->pipe_src_w)
9956 base = 0;
9957
9958 if (y >= intel_crtc->config->pipe_src_h)
9959 base = 0;
9960
9961 if (x < 0) {
9962 if (x + cursor_state->crtc_w <= 0)
9963 base = 0;
9964
9965 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9966 x = -x;
9967 }
9968 pos |= x << CURSOR_X_SHIFT;
9969
9970 if (y < 0) {
9971 if (y + cursor_state->crtc_h <= 0)
9972 base = 0;
9973
9974 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9975 y = -y;
9976 }
9977 pos |= y << CURSOR_Y_SHIFT;
9978
9979 if (base == 0 && intel_crtc->cursor_base == 0)
9980 return;
9981
9982 I915_WRITE(CURPOS(pipe), pos);
9983
9984 /* ILK+ do this automagically */
9985 if (HAS_GMCH_DISPLAY(dev) &&
9986 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
9987 base += (cursor_state->crtc_h *
9988 cursor_state->crtc_w - 1) * 4;
9989 }
9990
9991 if (IS_845G(dev) || IS_I865G(dev))
9992 i845_update_cursor(crtc, base);
9993 else
9994 i9xx_update_cursor(crtc, base);
9995 }
9996
9997 static bool cursor_size_ok(struct drm_device *dev,
9998 uint32_t width, uint32_t height)
9999 {
10000 if (width == 0 || height == 0)
10001 return false;
10002
10003 /*
10004 * 845g/865g are special in that they are only limited by
10005 * the width of their cursors, the height is arbitrary up to
10006 * the precision of the register. Everything else requires
10007 * square cursors, limited to a few power-of-two sizes.
10008 */
10009 if (IS_845G(dev) || IS_I865G(dev)) {
10010 if ((width & 63) != 0)
10011 return false;
10012
10013 if (width > (IS_845G(dev) ? 64 : 512))
10014 return false;
10015
10016 if (height > 1023)
10017 return false;
10018 } else {
10019 switch (width | height) {
10020 case 256:
10021 case 128:
10022 if (IS_GEN2(dev))
10023 return false;
10024 case 64:
10025 break;
10026 default:
10027 return false;
10028 }
10029 }
10030
10031 return true;
10032 }
10033
10034 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10035 u16 *blue, uint32_t start, uint32_t size)
10036 {
10037 int end = (start + size > 256) ? 256 : start + size, i;
10038 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10039
10040 for (i = start; i < end; i++) {
10041 intel_crtc->lut_r[i] = red[i] >> 8;
10042 intel_crtc->lut_g[i] = green[i] >> 8;
10043 intel_crtc->lut_b[i] = blue[i] >> 8;
10044 }
10045
10046 intel_crtc_load_lut(crtc);
10047 }
10048
10049 /* VESA 640x480x72Hz mode to set on the pipe */
10050 static struct drm_display_mode load_detect_mode = {
10051 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10052 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10053 };
10054
10055 struct drm_framebuffer *
10056 __intel_framebuffer_create(struct drm_device *dev,
10057 struct drm_mode_fb_cmd2 *mode_cmd,
10058 struct drm_i915_gem_object *obj)
10059 {
10060 struct intel_framebuffer *intel_fb;
10061 int ret;
10062
10063 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10064 if (!intel_fb) {
10065 drm_gem_object_unreference(&obj->base);
10066 return ERR_PTR(-ENOMEM);
10067 }
10068
10069 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10070 if (ret)
10071 goto err;
10072
10073 return &intel_fb->base;
10074 err:
10075 drm_gem_object_unreference(&obj->base);
10076 kfree(intel_fb);
10077
10078 return ERR_PTR(ret);
10079 }
10080
10081 static struct drm_framebuffer *
10082 intel_framebuffer_create(struct drm_device *dev,
10083 struct drm_mode_fb_cmd2 *mode_cmd,
10084 struct drm_i915_gem_object *obj)
10085 {
10086 struct drm_framebuffer *fb;
10087 int ret;
10088
10089 ret = i915_mutex_lock_interruptible(dev);
10090 if (ret)
10091 return ERR_PTR(ret);
10092 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10093 mutex_unlock(&dev->struct_mutex);
10094
10095 return fb;
10096 }
10097
10098 static u32
10099 intel_framebuffer_pitch_for_width(int width, int bpp)
10100 {
10101 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10102 return ALIGN(pitch, 64);
10103 }
10104
10105 static u32
10106 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10107 {
10108 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10109 return PAGE_ALIGN(pitch * mode->vdisplay);
10110 }
10111
10112 static struct drm_framebuffer *
10113 intel_framebuffer_create_for_mode(struct drm_device *dev,
10114 struct drm_display_mode *mode,
10115 int depth, int bpp)
10116 {
10117 struct drm_i915_gem_object *obj;
10118 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10119
10120 obj = i915_gem_alloc_object(dev,
10121 intel_framebuffer_size_for_mode(mode, bpp));
10122 if (obj == NULL)
10123 return ERR_PTR(-ENOMEM);
10124
10125 mode_cmd.width = mode->hdisplay;
10126 mode_cmd.height = mode->vdisplay;
10127 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10128 bpp);
10129 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10130
10131 return intel_framebuffer_create(dev, &mode_cmd, obj);
10132 }
10133
10134 static struct drm_framebuffer *
10135 mode_fits_in_fbdev(struct drm_device *dev,
10136 struct drm_display_mode *mode)
10137 {
10138 #ifdef CONFIG_DRM_FBDEV_EMULATION
10139 struct drm_i915_private *dev_priv = dev->dev_private;
10140 struct drm_i915_gem_object *obj;
10141 struct drm_framebuffer *fb;
10142
10143 if (!dev_priv->fbdev)
10144 return NULL;
10145
10146 if (!dev_priv->fbdev->fb)
10147 return NULL;
10148
10149 obj = dev_priv->fbdev->fb->obj;
10150 BUG_ON(!obj);
10151
10152 fb = &dev_priv->fbdev->fb->base;
10153 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10154 fb->bits_per_pixel))
10155 return NULL;
10156
10157 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10158 return NULL;
10159
10160 return fb;
10161 #else
10162 return NULL;
10163 #endif
10164 }
10165
10166 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10167 struct drm_crtc *crtc,
10168 struct drm_display_mode *mode,
10169 struct drm_framebuffer *fb,
10170 int x, int y)
10171 {
10172 struct drm_plane_state *plane_state;
10173 int hdisplay, vdisplay;
10174 int ret;
10175
10176 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10177 if (IS_ERR(plane_state))
10178 return PTR_ERR(plane_state);
10179
10180 if (mode)
10181 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10182 else
10183 hdisplay = vdisplay = 0;
10184
10185 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10186 if (ret)
10187 return ret;
10188 drm_atomic_set_fb_for_plane(plane_state, fb);
10189 plane_state->crtc_x = 0;
10190 plane_state->crtc_y = 0;
10191 plane_state->crtc_w = hdisplay;
10192 plane_state->crtc_h = vdisplay;
10193 plane_state->src_x = x << 16;
10194 plane_state->src_y = y << 16;
10195 plane_state->src_w = hdisplay << 16;
10196 plane_state->src_h = vdisplay << 16;
10197
10198 return 0;
10199 }
10200
10201 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10202 struct drm_display_mode *mode,
10203 struct intel_load_detect_pipe *old,
10204 struct drm_modeset_acquire_ctx *ctx)
10205 {
10206 struct intel_crtc *intel_crtc;
10207 struct intel_encoder *intel_encoder =
10208 intel_attached_encoder(connector);
10209 struct drm_crtc *possible_crtc;
10210 struct drm_encoder *encoder = &intel_encoder->base;
10211 struct drm_crtc *crtc = NULL;
10212 struct drm_device *dev = encoder->dev;
10213 struct drm_framebuffer *fb;
10214 struct drm_mode_config *config = &dev->mode_config;
10215 struct drm_atomic_state *state = NULL;
10216 struct drm_connector_state *connector_state;
10217 struct intel_crtc_state *crtc_state;
10218 int ret, i = -1;
10219
10220 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10221 connector->base.id, connector->name,
10222 encoder->base.id, encoder->name);
10223
10224 retry:
10225 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10226 if (ret)
10227 goto fail;
10228
10229 /*
10230 * Algorithm gets a little messy:
10231 *
10232 * - if the connector already has an assigned crtc, use it (but make
10233 * sure it's on first)
10234 *
10235 * - try to find the first unused crtc that can drive this connector,
10236 * and use that if we find one
10237 */
10238
10239 /* See if we already have a CRTC for this connector */
10240 if (encoder->crtc) {
10241 crtc = encoder->crtc;
10242
10243 ret = drm_modeset_lock(&crtc->mutex, ctx);
10244 if (ret)
10245 goto fail;
10246 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10247 if (ret)
10248 goto fail;
10249
10250 old->dpms_mode = connector->dpms;
10251 old->load_detect_temp = false;
10252
10253 /* Make sure the crtc and connector are running */
10254 if (connector->dpms != DRM_MODE_DPMS_ON)
10255 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10256
10257 return true;
10258 }
10259
10260 /* Find an unused one (if possible) */
10261 for_each_crtc(dev, possible_crtc) {
10262 i++;
10263 if (!(encoder->possible_crtcs & (1 << i)))
10264 continue;
10265 if (possible_crtc->state->enable)
10266 continue;
10267
10268 crtc = possible_crtc;
10269 break;
10270 }
10271
10272 /*
10273 * If we didn't find an unused CRTC, don't use any.
10274 */
10275 if (!crtc) {
10276 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10277 goto fail;
10278 }
10279
10280 ret = drm_modeset_lock(&crtc->mutex, ctx);
10281 if (ret)
10282 goto fail;
10283 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10284 if (ret)
10285 goto fail;
10286
10287 intel_crtc = to_intel_crtc(crtc);
10288 old->dpms_mode = connector->dpms;
10289 old->load_detect_temp = true;
10290 old->release_fb = NULL;
10291
10292 state = drm_atomic_state_alloc(dev);
10293 if (!state)
10294 return false;
10295
10296 state->acquire_ctx = ctx;
10297
10298 connector_state = drm_atomic_get_connector_state(state, connector);
10299 if (IS_ERR(connector_state)) {
10300 ret = PTR_ERR(connector_state);
10301 goto fail;
10302 }
10303
10304 connector_state->crtc = crtc;
10305 connector_state->best_encoder = &intel_encoder->base;
10306
10307 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10308 if (IS_ERR(crtc_state)) {
10309 ret = PTR_ERR(crtc_state);
10310 goto fail;
10311 }
10312
10313 crtc_state->base.active = crtc_state->base.enable = true;
10314
10315 if (!mode)
10316 mode = &load_detect_mode;
10317
10318 /* We need a framebuffer large enough to accommodate all accesses
10319 * that the plane may generate whilst we perform load detection.
10320 * We can not rely on the fbcon either being present (we get called
10321 * during its initialisation to detect all boot displays, or it may
10322 * not even exist) or that it is large enough to satisfy the
10323 * requested mode.
10324 */
10325 fb = mode_fits_in_fbdev(dev, mode);
10326 if (fb == NULL) {
10327 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10328 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10329 old->release_fb = fb;
10330 } else
10331 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10332 if (IS_ERR(fb)) {
10333 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10334 goto fail;
10335 }
10336
10337 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10338 if (ret)
10339 goto fail;
10340
10341 drm_mode_copy(&crtc_state->base.mode, mode);
10342
10343 if (drm_atomic_commit(state)) {
10344 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10345 if (old->release_fb)
10346 old->release_fb->funcs->destroy(old->release_fb);
10347 goto fail;
10348 }
10349 crtc->primary->crtc = crtc;
10350
10351 /* let the connector get through one full cycle before testing */
10352 intel_wait_for_vblank(dev, intel_crtc->pipe);
10353 return true;
10354
10355 fail:
10356 drm_atomic_state_free(state);
10357 state = NULL;
10358
10359 if (ret == -EDEADLK) {
10360 drm_modeset_backoff(ctx);
10361 goto retry;
10362 }
10363
10364 return false;
10365 }
10366
10367 void intel_release_load_detect_pipe(struct drm_connector *connector,
10368 struct intel_load_detect_pipe *old,
10369 struct drm_modeset_acquire_ctx *ctx)
10370 {
10371 struct drm_device *dev = connector->dev;
10372 struct intel_encoder *intel_encoder =
10373 intel_attached_encoder(connector);
10374 struct drm_encoder *encoder = &intel_encoder->base;
10375 struct drm_crtc *crtc = encoder->crtc;
10376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10377 struct drm_atomic_state *state;
10378 struct drm_connector_state *connector_state;
10379 struct intel_crtc_state *crtc_state;
10380 int ret;
10381
10382 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10383 connector->base.id, connector->name,
10384 encoder->base.id, encoder->name);
10385
10386 if (old->load_detect_temp) {
10387 state = drm_atomic_state_alloc(dev);
10388 if (!state)
10389 goto fail;
10390
10391 state->acquire_ctx = ctx;
10392
10393 connector_state = drm_atomic_get_connector_state(state, connector);
10394 if (IS_ERR(connector_state))
10395 goto fail;
10396
10397 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10398 if (IS_ERR(crtc_state))
10399 goto fail;
10400
10401 connector_state->best_encoder = NULL;
10402 connector_state->crtc = NULL;
10403
10404 crtc_state->base.enable = crtc_state->base.active = false;
10405
10406 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10407 0, 0);
10408 if (ret)
10409 goto fail;
10410
10411 ret = drm_atomic_commit(state);
10412 if (ret)
10413 goto fail;
10414
10415 if (old->release_fb) {
10416 drm_framebuffer_unregister_private(old->release_fb);
10417 drm_framebuffer_unreference(old->release_fb);
10418 }
10419
10420 return;
10421 }
10422
10423 /* Switch crtc and encoder back off if necessary */
10424 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10425 connector->funcs->dpms(connector, old->dpms_mode);
10426
10427 return;
10428 fail:
10429 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10430 drm_atomic_state_free(state);
10431 }
10432
10433 static int i9xx_pll_refclk(struct drm_device *dev,
10434 const struct intel_crtc_state *pipe_config)
10435 {
10436 struct drm_i915_private *dev_priv = dev->dev_private;
10437 u32 dpll = pipe_config->dpll_hw_state.dpll;
10438
10439 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10440 return dev_priv->vbt.lvds_ssc_freq;
10441 else if (HAS_PCH_SPLIT(dev))
10442 return 120000;
10443 else if (!IS_GEN2(dev))
10444 return 96000;
10445 else
10446 return 48000;
10447 }
10448
10449 /* Returns the clock of the currently programmed mode of the given pipe. */
10450 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10451 struct intel_crtc_state *pipe_config)
10452 {
10453 struct drm_device *dev = crtc->base.dev;
10454 struct drm_i915_private *dev_priv = dev->dev_private;
10455 int pipe = pipe_config->cpu_transcoder;
10456 u32 dpll = pipe_config->dpll_hw_state.dpll;
10457 u32 fp;
10458 intel_clock_t clock;
10459 int port_clock;
10460 int refclk = i9xx_pll_refclk(dev, pipe_config);
10461
10462 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10463 fp = pipe_config->dpll_hw_state.fp0;
10464 else
10465 fp = pipe_config->dpll_hw_state.fp1;
10466
10467 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10468 if (IS_PINEVIEW(dev)) {
10469 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10470 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10471 } else {
10472 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10473 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10474 }
10475
10476 if (!IS_GEN2(dev)) {
10477 if (IS_PINEVIEW(dev))
10478 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10479 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10480 else
10481 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10482 DPLL_FPA01_P1_POST_DIV_SHIFT);
10483
10484 switch (dpll & DPLL_MODE_MASK) {
10485 case DPLLB_MODE_DAC_SERIAL:
10486 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10487 5 : 10;
10488 break;
10489 case DPLLB_MODE_LVDS:
10490 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10491 7 : 14;
10492 break;
10493 default:
10494 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10495 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10496 return;
10497 }
10498
10499 if (IS_PINEVIEW(dev))
10500 port_clock = pnv_calc_dpll_params(refclk, &clock);
10501 else
10502 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10503 } else {
10504 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10505 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10506
10507 if (is_lvds) {
10508 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10509 DPLL_FPA01_P1_POST_DIV_SHIFT);
10510
10511 if (lvds & LVDS_CLKB_POWER_UP)
10512 clock.p2 = 7;
10513 else
10514 clock.p2 = 14;
10515 } else {
10516 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10517 clock.p1 = 2;
10518 else {
10519 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10520 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10521 }
10522 if (dpll & PLL_P2_DIVIDE_BY_4)
10523 clock.p2 = 4;
10524 else
10525 clock.p2 = 2;
10526 }
10527
10528 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10529 }
10530
10531 /*
10532 * This value includes pixel_multiplier. We will use
10533 * port_clock to compute adjusted_mode.crtc_clock in the
10534 * encoder's get_config() function.
10535 */
10536 pipe_config->port_clock = port_clock;
10537 }
10538
10539 int intel_dotclock_calculate(int link_freq,
10540 const struct intel_link_m_n *m_n)
10541 {
10542 /*
10543 * The calculation for the data clock is:
10544 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10545 * But we want to avoid losing precison if possible, so:
10546 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10547 *
10548 * and the link clock is simpler:
10549 * link_clock = (m * link_clock) / n
10550 */
10551
10552 if (!m_n->link_n)
10553 return 0;
10554
10555 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10556 }
10557
10558 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10559 struct intel_crtc_state *pipe_config)
10560 {
10561 struct drm_device *dev = crtc->base.dev;
10562
10563 /* read out port_clock from the DPLL */
10564 i9xx_crtc_clock_get(crtc, pipe_config);
10565
10566 /*
10567 * This value does not include pixel_multiplier.
10568 * We will check that port_clock and adjusted_mode.crtc_clock
10569 * agree once we know their relationship in the encoder's
10570 * get_config() function.
10571 */
10572 pipe_config->base.adjusted_mode.crtc_clock =
10573 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10574 &pipe_config->fdi_m_n);
10575 }
10576
10577 /** Returns the currently programmed mode of the given pipe. */
10578 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10579 struct drm_crtc *crtc)
10580 {
10581 struct drm_i915_private *dev_priv = dev->dev_private;
10582 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10583 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10584 struct drm_display_mode *mode;
10585 struct intel_crtc_state pipe_config;
10586 int htot = I915_READ(HTOTAL(cpu_transcoder));
10587 int hsync = I915_READ(HSYNC(cpu_transcoder));
10588 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10589 int vsync = I915_READ(VSYNC(cpu_transcoder));
10590 enum pipe pipe = intel_crtc->pipe;
10591
10592 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10593 if (!mode)
10594 return NULL;
10595
10596 /*
10597 * Construct a pipe_config sufficient for getting the clock info
10598 * back out of crtc_clock_get.
10599 *
10600 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10601 * to use a real value here instead.
10602 */
10603 pipe_config.cpu_transcoder = (enum transcoder) pipe;
10604 pipe_config.pixel_multiplier = 1;
10605 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10606 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10607 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10608 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10609
10610 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10611 mode->hdisplay = (htot & 0xffff) + 1;
10612 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10613 mode->hsync_start = (hsync & 0xffff) + 1;
10614 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10615 mode->vdisplay = (vtot & 0xffff) + 1;
10616 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10617 mode->vsync_start = (vsync & 0xffff) + 1;
10618 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10619
10620 drm_mode_set_name(mode);
10621
10622 return mode;
10623 }
10624
10625 void intel_mark_busy(struct drm_device *dev)
10626 {
10627 struct drm_i915_private *dev_priv = dev->dev_private;
10628
10629 if (dev_priv->mm.busy)
10630 return;
10631
10632 intel_runtime_pm_get(dev_priv);
10633 i915_update_gfx_val(dev_priv);
10634 if (INTEL_INFO(dev)->gen >= 6)
10635 gen6_rps_busy(dev_priv);
10636 dev_priv->mm.busy = true;
10637 }
10638
10639 void intel_mark_idle(struct drm_device *dev)
10640 {
10641 struct drm_i915_private *dev_priv = dev->dev_private;
10642
10643 if (!dev_priv->mm.busy)
10644 return;
10645
10646 dev_priv->mm.busy = false;
10647
10648 if (INTEL_INFO(dev)->gen >= 6)
10649 gen6_rps_idle(dev->dev_private);
10650
10651 intel_runtime_pm_put(dev_priv);
10652 }
10653
10654 static void intel_crtc_destroy(struct drm_crtc *crtc)
10655 {
10656 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10657 struct drm_device *dev = crtc->dev;
10658 struct intel_unpin_work *work;
10659
10660 spin_lock_irq(&dev->event_lock);
10661 work = intel_crtc->unpin_work;
10662 intel_crtc->unpin_work = NULL;
10663 spin_unlock_irq(&dev->event_lock);
10664
10665 if (work) {
10666 cancel_work_sync(&work->work);
10667 kfree(work);
10668 }
10669
10670 drm_crtc_cleanup(crtc);
10671
10672 kfree(intel_crtc);
10673 }
10674
10675 static void intel_unpin_work_fn(struct work_struct *__work)
10676 {
10677 struct intel_unpin_work *work =
10678 container_of(__work, struct intel_unpin_work, work);
10679 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10680 struct drm_device *dev = crtc->base.dev;
10681 struct drm_plane *primary = crtc->base.primary;
10682
10683 mutex_lock(&dev->struct_mutex);
10684 intel_unpin_fb_obj(work->old_fb, primary->state);
10685 drm_gem_object_unreference(&work->pending_flip_obj->base);
10686
10687 if (work->flip_queued_req)
10688 i915_gem_request_assign(&work->flip_queued_req, NULL);
10689 mutex_unlock(&dev->struct_mutex);
10690
10691 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10692 drm_framebuffer_unreference(work->old_fb);
10693
10694 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10695 atomic_dec(&crtc->unpin_work_count);
10696
10697 kfree(work);
10698 }
10699
10700 static void do_intel_finish_page_flip(struct drm_device *dev,
10701 struct drm_crtc *crtc)
10702 {
10703 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10704 struct intel_unpin_work *work;
10705 unsigned long flags;
10706
10707 /* Ignore early vblank irqs */
10708 if (intel_crtc == NULL)
10709 return;
10710
10711 /*
10712 * This is called both by irq handlers and the reset code (to complete
10713 * lost pageflips) so needs the full irqsave spinlocks.
10714 */
10715 spin_lock_irqsave(&dev->event_lock, flags);
10716 work = intel_crtc->unpin_work;
10717
10718 /* Ensure we don't miss a work->pending update ... */
10719 smp_rmb();
10720
10721 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10722 spin_unlock_irqrestore(&dev->event_lock, flags);
10723 return;
10724 }
10725
10726 page_flip_completed(intel_crtc);
10727
10728 spin_unlock_irqrestore(&dev->event_lock, flags);
10729 }
10730
10731 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10732 {
10733 struct drm_i915_private *dev_priv = dev->dev_private;
10734 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10735
10736 do_intel_finish_page_flip(dev, crtc);
10737 }
10738
10739 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10740 {
10741 struct drm_i915_private *dev_priv = dev->dev_private;
10742 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10743
10744 do_intel_finish_page_flip(dev, crtc);
10745 }
10746
10747 /* Is 'a' after or equal to 'b'? */
10748 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10749 {
10750 return !((a - b) & 0x80000000);
10751 }
10752
10753 static bool page_flip_finished(struct intel_crtc *crtc)
10754 {
10755 struct drm_device *dev = crtc->base.dev;
10756 struct drm_i915_private *dev_priv = dev->dev_private;
10757
10758 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10759 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10760 return true;
10761
10762 /*
10763 * The relevant registers doen't exist on pre-ctg.
10764 * As the flip done interrupt doesn't trigger for mmio
10765 * flips on gmch platforms, a flip count check isn't
10766 * really needed there. But since ctg has the registers,
10767 * include it in the check anyway.
10768 */
10769 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10770 return true;
10771
10772 /*
10773 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10774 * used the same base address. In that case the mmio flip might
10775 * have completed, but the CS hasn't even executed the flip yet.
10776 *
10777 * A flip count check isn't enough as the CS might have updated
10778 * the base address just after start of vblank, but before we
10779 * managed to process the interrupt. This means we'd complete the
10780 * CS flip too soon.
10781 *
10782 * Combining both checks should get us a good enough result. It may
10783 * still happen that the CS flip has been executed, but has not
10784 * yet actually completed. But in case the base address is the same
10785 * anyway, we don't really care.
10786 */
10787 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10788 crtc->unpin_work->gtt_offset &&
10789 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10790 crtc->unpin_work->flip_count);
10791 }
10792
10793 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10794 {
10795 struct drm_i915_private *dev_priv = dev->dev_private;
10796 struct intel_crtc *intel_crtc =
10797 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10798 unsigned long flags;
10799
10800
10801 /*
10802 * This is called both by irq handlers and the reset code (to complete
10803 * lost pageflips) so needs the full irqsave spinlocks.
10804 *
10805 * NB: An MMIO update of the plane base pointer will also
10806 * generate a page-flip completion irq, i.e. every modeset
10807 * is also accompanied by a spurious intel_prepare_page_flip().
10808 */
10809 spin_lock_irqsave(&dev->event_lock, flags);
10810 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10811 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10812 spin_unlock_irqrestore(&dev->event_lock, flags);
10813 }
10814
10815 static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
10816 {
10817 /* Ensure that the work item is consistent when activating it ... */
10818 smp_wmb();
10819 atomic_set(&work->pending, INTEL_FLIP_PENDING);
10820 /* and that it is marked active as soon as the irq could fire. */
10821 smp_wmb();
10822 }
10823
10824 static int intel_gen2_queue_flip(struct drm_device *dev,
10825 struct drm_crtc *crtc,
10826 struct drm_framebuffer *fb,
10827 struct drm_i915_gem_object *obj,
10828 struct drm_i915_gem_request *req,
10829 uint32_t flags)
10830 {
10831 struct intel_engine_cs *ring = req->ring;
10832 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10833 u32 flip_mask;
10834 int ret;
10835
10836 ret = intel_ring_begin(req, 6);
10837 if (ret)
10838 return ret;
10839
10840 /* Can't queue multiple flips, so wait for the previous
10841 * one to finish before executing the next.
10842 */
10843 if (intel_crtc->plane)
10844 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10845 else
10846 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10847 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10848 intel_ring_emit(ring, MI_NOOP);
10849 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10850 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10851 intel_ring_emit(ring, fb->pitches[0]);
10852 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10853 intel_ring_emit(ring, 0); /* aux display base address, unused */
10854
10855 intel_mark_page_flip_active(intel_crtc->unpin_work);
10856 return 0;
10857 }
10858
10859 static int intel_gen3_queue_flip(struct drm_device *dev,
10860 struct drm_crtc *crtc,
10861 struct drm_framebuffer *fb,
10862 struct drm_i915_gem_object *obj,
10863 struct drm_i915_gem_request *req,
10864 uint32_t flags)
10865 {
10866 struct intel_engine_cs *ring = req->ring;
10867 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10868 u32 flip_mask;
10869 int ret;
10870
10871 ret = intel_ring_begin(req, 6);
10872 if (ret)
10873 return ret;
10874
10875 if (intel_crtc->plane)
10876 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10877 else
10878 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10879 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10880 intel_ring_emit(ring, MI_NOOP);
10881 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10882 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10883 intel_ring_emit(ring, fb->pitches[0]);
10884 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10885 intel_ring_emit(ring, MI_NOOP);
10886
10887 intel_mark_page_flip_active(intel_crtc->unpin_work);
10888 return 0;
10889 }
10890
10891 static int intel_gen4_queue_flip(struct drm_device *dev,
10892 struct drm_crtc *crtc,
10893 struct drm_framebuffer *fb,
10894 struct drm_i915_gem_object *obj,
10895 struct drm_i915_gem_request *req,
10896 uint32_t flags)
10897 {
10898 struct intel_engine_cs *ring = req->ring;
10899 struct drm_i915_private *dev_priv = dev->dev_private;
10900 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10901 uint32_t pf, pipesrc;
10902 int ret;
10903
10904 ret = intel_ring_begin(req, 4);
10905 if (ret)
10906 return ret;
10907
10908 /* i965+ uses the linear or tiled offsets from the
10909 * Display Registers (which do not change across a page-flip)
10910 * so we need only reprogram the base address.
10911 */
10912 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10913 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10914 intel_ring_emit(ring, fb->pitches[0]);
10915 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
10916 obj->tiling_mode);
10917
10918 /* XXX Enabling the panel-fitter across page-flip is so far
10919 * untested on non-native modes, so ignore it for now.
10920 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10921 */
10922 pf = 0;
10923 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10924 intel_ring_emit(ring, pf | pipesrc);
10925
10926 intel_mark_page_flip_active(intel_crtc->unpin_work);
10927 return 0;
10928 }
10929
10930 static int intel_gen6_queue_flip(struct drm_device *dev,
10931 struct drm_crtc *crtc,
10932 struct drm_framebuffer *fb,
10933 struct drm_i915_gem_object *obj,
10934 struct drm_i915_gem_request *req,
10935 uint32_t flags)
10936 {
10937 struct intel_engine_cs *ring = req->ring;
10938 struct drm_i915_private *dev_priv = dev->dev_private;
10939 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10940 uint32_t pf, pipesrc;
10941 int ret;
10942
10943 ret = intel_ring_begin(req, 4);
10944 if (ret)
10945 return ret;
10946
10947 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10948 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10949 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
10950 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10951
10952 /* Contrary to the suggestions in the documentation,
10953 * "Enable Panel Fitter" does not seem to be required when page
10954 * flipping with a non-native mode, and worse causes a normal
10955 * modeset to fail.
10956 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10957 */
10958 pf = 0;
10959 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10960 intel_ring_emit(ring, pf | pipesrc);
10961
10962 intel_mark_page_flip_active(intel_crtc->unpin_work);
10963 return 0;
10964 }
10965
10966 static int intel_gen7_queue_flip(struct drm_device *dev,
10967 struct drm_crtc *crtc,
10968 struct drm_framebuffer *fb,
10969 struct drm_i915_gem_object *obj,
10970 struct drm_i915_gem_request *req,
10971 uint32_t flags)
10972 {
10973 struct intel_engine_cs *ring = req->ring;
10974 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10975 uint32_t plane_bit = 0;
10976 int len, ret;
10977
10978 switch (intel_crtc->plane) {
10979 case PLANE_A:
10980 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10981 break;
10982 case PLANE_B:
10983 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10984 break;
10985 case PLANE_C:
10986 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10987 break;
10988 default:
10989 WARN_ONCE(1, "unknown plane in flip command\n");
10990 return -ENODEV;
10991 }
10992
10993 len = 4;
10994 if (ring->id == RCS) {
10995 len += 6;
10996 /*
10997 * On Gen 8, SRM is now taking an extra dword to accommodate
10998 * 48bits addresses, and we need a NOOP for the batch size to
10999 * stay even.
11000 */
11001 if (IS_GEN8(dev))
11002 len += 2;
11003 }
11004
11005 /*
11006 * BSpec MI_DISPLAY_FLIP for IVB:
11007 * "The full packet must be contained within the same cache line."
11008 *
11009 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11010 * cacheline, if we ever start emitting more commands before
11011 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11012 * then do the cacheline alignment, and finally emit the
11013 * MI_DISPLAY_FLIP.
11014 */
11015 ret = intel_ring_cacheline_align(req);
11016 if (ret)
11017 return ret;
11018
11019 ret = intel_ring_begin(req, len);
11020 if (ret)
11021 return ret;
11022
11023 /* Unmask the flip-done completion message. Note that the bspec says that
11024 * we should do this for both the BCS and RCS, and that we must not unmask
11025 * more than one flip event at any time (or ensure that one flip message
11026 * can be sent by waiting for flip-done prior to queueing new flips).
11027 * Experimentation says that BCS works despite DERRMR masking all
11028 * flip-done completion events and that unmasking all planes at once
11029 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11030 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11031 */
11032 if (ring->id == RCS) {
11033 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11034 intel_ring_emit(ring, DERRMR);
11035 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11036 DERRMR_PIPEB_PRI_FLIP_DONE |
11037 DERRMR_PIPEC_PRI_FLIP_DONE));
11038 if (IS_GEN8(dev))
11039 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11040 MI_SRM_LRM_GLOBAL_GTT);
11041 else
11042 intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11043 MI_SRM_LRM_GLOBAL_GTT);
11044 intel_ring_emit(ring, DERRMR);
11045 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11046 if (IS_GEN8(dev)) {
11047 intel_ring_emit(ring, 0);
11048 intel_ring_emit(ring, MI_NOOP);
11049 }
11050 }
11051
11052 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11053 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11054 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11055 intel_ring_emit(ring, (MI_NOOP));
11056
11057 intel_mark_page_flip_active(intel_crtc->unpin_work);
11058 return 0;
11059 }
11060
11061 static bool use_mmio_flip(struct intel_engine_cs *ring,
11062 struct drm_i915_gem_object *obj)
11063 {
11064 /*
11065 * This is not being used for older platforms, because
11066 * non-availability of flip done interrupt forces us to use
11067 * CS flips. Older platforms derive flip done using some clever
11068 * tricks involving the flip_pending status bits and vblank irqs.
11069 * So using MMIO flips there would disrupt this mechanism.
11070 */
11071
11072 if (ring == NULL)
11073 return true;
11074
11075 if (INTEL_INFO(ring->dev)->gen < 5)
11076 return false;
11077
11078 if (i915.use_mmio_flip < 0)
11079 return false;
11080 else if (i915.use_mmio_flip > 0)
11081 return true;
11082 else if (i915.enable_execlists)
11083 return true;
11084 else
11085 return ring != i915_gem_request_get_ring(obj->last_write_req);
11086 }
11087
11088 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11089 struct intel_unpin_work *work)
11090 {
11091 struct drm_device *dev = intel_crtc->base.dev;
11092 struct drm_i915_private *dev_priv = dev->dev_private;
11093 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11094 const enum pipe pipe = intel_crtc->pipe;
11095 u32 ctl, stride;
11096
11097 ctl = I915_READ(PLANE_CTL(pipe, 0));
11098 ctl &= ~PLANE_CTL_TILED_MASK;
11099 switch (fb->modifier[0]) {
11100 case DRM_FORMAT_MOD_NONE:
11101 break;
11102 case I915_FORMAT_MOD_X_TILED:
11103 ctl |= PLANE_CTL_TILED_X;
11104 break;
11105 case I915_FORMAT_MOD_Y_TILED:
11106 ctl |= PLANE_CTL_TILED_Y;
11107 break;
11108 case I915_FORMAT_MOD_Yf_TILED:
11109 ctl |= PLANE_CTL_TILED_YF;
11110 break;
11111 default:
11112 MISSING_CASE(fb->modifier[0]);
11113 }
11114
11115 /*
11116 * The stride is either expressed as a multiple of 64 bytes chunks for
11117 * linear buffers or in number of tiles for tiled buffers.
11118 */
11119 stride = fb->pitches[0] /
11120 intel_fb_stride_alignment(dev, fb->modifier[0],
11121 fb->pixel_format);
11122
11123 /*
11124 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11125 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11126 */
11127 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11128 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11129
11130 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11131 POSTING_READ(PLANE_SURF(pipe, 0));
11132 }
11133
11134 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11135 struct intel_unpin_work *work)
11136 {
11137 struct drm_device *dev = intel_crtc->base.dev;
11138 struct drm_i915_private *dev_priv = dev->dev_private;
11139 struct intel_framebuffer *intel_fb =
11140 to_intel_framebuffer(intel_crtc->base.primary->fb);
11141 struct drm_i915_gem_object *obj = intel_fb->obj;
11142 u32 dspcntr;
11143 u32 reg;
11144
11145 reg = DSPCNTR(intel_crtc->plane);
11146 dspcntr = I915_READ(reg);
11147
11148 if (obj->tiling_mode != I915_TILING_NONE)
11149 dspcntr |= DISPPLANE_TILED;
11150 else
11151 dspcntr &= ~DISPPLANE_TILED;
11152
11153 I915_WRITE(reg, dspcntr);
11154
11155 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11156 POSTING_READ(DSPSURF(intel_crtc->plane));
11157 }
11158
11159 /*
11160 * XXX: This is the temporary way to update the plane registers until we get
11161 * around to using the usual plane update functions for MMIO flips
11162 */
11163 static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
11164 {
11165 struct intel_crtc *crtc = mmio_flip->crtc;
11166 struct intel_unpin_work *work;
11167
11168 spin_lock_irq(&crtc->base.dev->event_lock);
11169 work = crtc->unpin_work;
11170 spin_unlock_irq(&crtc->base.dev->event_lock);
11171 if (work == NULL)
11172 return;
11173
11174 intel_mark_page_flip_active(work);
11175
11176 intel_pipe_update_start(crtc);
11177
11178 if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
11179 skl_do_mmio_flip(crtc, work);
11180 else
11181 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11182 ilk_do_mmio_flip(crtc, work);
11183
11184 intel_pipe_update_end(crtc);
11185 }
11186
11187 static void intel_mmio_flip_work_func(struct work_struct *work)
11188 {
11189 struct intel_mmio_flip *mmio_flip =
11190 container_of(work, struct intel_mmio_flip, work);
11191
11192 if (mmio_flip->req) {
11193 WARN_ON(__i915_wait_request(mmio_flip->req,
11194 mmio_flip->crtc->reset_counter,
11195 false, NULL,
11196 &mmio_flip->i915->rps.mmioflips));
11197 i915_gem_request_unreference__unlocked(mmio_flip->req);
11198 }
11199
11200 intel_do_mmio_flip(mmio_flip);
11201 kfree(mmio_flip);
11202 }
11203
11204 static int intel_queue_mmio_flip(struct drm_device *dev,
11205 struct drm_crtc *crtc,
11206 struct drm_framebuffer *fb,
11207 struct drm_i915_gem_object *obj,
11208 struct intel_engine_cs *ring,
11209 uint32_t flags)
11210 {
11211 struct intel_mmio_flip *mmio_flip;
11212
11213 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11214 if (mmio_flip == NULL)
11215 return -ENOMEM;
11216
11217 mmio_flip->i915 = to_i915(dev);
11218 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11219 mmio_flip->crtc = to_intel_crtc(crtc);
11220
11221 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11222 schedule_work(&mmio_flip->work);
11223
11224 return 0;
11225 }
11226
11227 static int intel_default_queue_flip(struct drm_device *dev,
11228 struct drm_crtc *crtc,
11229 struct drm_framebuffer *fb,
11230 struct drm_i915_gem_object *obj,
11231 struct drm_i915_gem_request *req,
11232 uint32_t flags)
11233 {
11234 return -ENODEV;
11235 }
11236
11237 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11238 struct drm_crtc *crtc)
11239 {
11240 struct drm_i915_private *dev_priv = dev->dev_private;
11241 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11242 struct intel_unpin_work *work = intel_crtc->unpin_work;
11243 u32 addr;
11244
11245 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11246 return true;
11247
11248 if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11249 return false;
11250
11251 if (!work->enable_stall_check)
11252 return false;
11253
11254 if (work->flip_ready_vblank == 0) {
11255 if (work->flip_queued_req &&
11256 !i915_gem_request_completed(work->flip_queued_req, true))
11257 return false;
11258
11259 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11260 }
11261
11262 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11263 return false;
11264
11265 /* Potential stall - if we see that the flip has happened,
11266 * assume a missed interrupt. */
11267 if (INTEL_INFO(dev)->gen >= 4)
11268 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11269 else
11270 addr = I915_READ(DSPADDR(intel_crtc->plane));
11271
11272 /* There is a potential issue here with a false positive after a flip
11273 * to the same address. We could address this by checking for a
11274 * non-incrementing frame counter.
11275 */
11276 return addr == work->gtt_offset;
11277 }
11278
11279 void intel_check_page_flip(struct drm_device *dev, int pipe)
11280 {
11281 struct drm_i915_private *dev_priv = dev->dev_private;
11282 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11283 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11284 struct intel_unpin_work *work;
11285
11286 WARN_ON(!in_interrupt());
11287
11288 if (crtc == NULL)
11289 return;
11290
11291 spin_lock(&dev->event_lock);
11292 work = intel_crtc->unpin_work;
11293 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11294 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11295 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11296 page_flip_completed(intel_crtc);
11297 work = NULL;
11298 }
11299 if (work != NULL &&
11300 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11301 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11302 spin_unlock(&dev->event_lock);
11303 }
11304
11305 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11306 struct drm_framebuffer *fb,
11307 struct drm_pending_vblank_event *event,
11308 uint32_t page_flip_flags)
11309 {
11310 struct drm_device *dev = crtc->dev;
11311 struct drm_i915_private *dev_priv = dev->dev_private;
11312 struct drm_framebuffer *old_fb = crtc->primary->fb;
11313 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11314 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11315 struct drm_plane *primary = crtc->primary;
11316 enum pipe pipe = intel_crtc->pipe;
11317 struct intel_unpin_work *work;
11318 struct intel_engine_cs *ring;
11319 bool mmio_flip;
11320 struct drm_i915_gem_request *request = NULL;
11321 int ret;
11322
11323 /*
11324 * drm_mode_page_flip_ioctl() should already catch this, but double
11325 * check to be safe. In the future we may enable pageflipping from
11326 * a disabled primary plane.
11327 */
11328 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11329 return -EBUSY;
11330
11331 /* Can't change pixel format via MI display flips. */
11332 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11333 return -EINVAL;
11334
11335 /*
11336 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11337 * Note that pitch changes could also affect these register.
11338 */
11339 if (INTEL_INFO(dev)->gen > 3 &&
11340 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11341 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11342 return -EINVAL;
11343
11344 if (i915_terminally_wedged(&dev_priv->gpu_error))
11345 goto out_hang;
11346
11347 work = kzalloc(sizeof(*work), GFP_KERNEL);
11348 if (work == NULL)
11349 return -ENOMEM;
11350
11351 work->event = event;
11352 work->crtc = crtc;
11353 work->old_fb = old_fb;
11354 INIT_WORK(&work->work, intel_unpin_work_fn);
11355
11356 ret = drm_crtc_vblank_get(crtc);
11357 if (ret)
11358 goto free_work;
11359
11360 /* We borrow the event spin lock for protecting unpin_work */
11361 spin_lock_irq(&dev->event_lock);
11362 if (intel_crtc->unpin_work) {
11363 /* Before declaring the flip queue wedged, check if
11364 * the hardware completed the operation behind our backs.
11365 */
11366 if (__intel_pageflip_stall_check(dev, crtc)) {
11367 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11368 page_flip_completed(intel_crtc);
11369 } else {
11370 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11371 spin_unlock_irq(&dev->event_lock);
11372
11373 drm_crtc_vblank_put(crtc);
11374 kfree(work);
11375 return -EBUSY;
11376 }
11377 }
11378 intel_crtc->unpin_work = work;
11379 spin_unlock_irq(&dev->event_lock);
11380
11381 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11382 flush_workqueue(dev_priv->wq);
11383
11384 /* Reference the objects for the scheduled work. */
11385 drm_framebuffer_reference(work->old_fb);
11386 drm_gem_object_reference(&obj->base);
11387
11388 crtc->primary->fb = fb;
11389 update_state_fb(crtc->primary);
11390
11391 work->pending_flip_obj = obj;
11392
11393 ret = i915_mutex_lock_interruptible(dev);
11394 if (ret)
11395 goto cleanup;
11396
11397 atomic_inc(&intel_crtc->unpin_work_count);
11398 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11399
11400 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11401 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11402
11403 if (IS_VALLEYVIEW(dev)) {
11404 ring = &dev_priv->ring[BCS];
11405 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11406 /* vlv: DISPLAY_FLIP fails to change tiling */
11407 ring = NULL;
11408 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11409 ring = &dev_priv->ring[BCS];
11410 } else if (INTEL_INFO(dev)->gen >= 7) {
11411 ring = i915_gem_request_get_ring(obj->last_write_req);
11412 if (ring == NULL || ring->id != RCS)
11413 ring = &dev_priv->ring[BCS];
11414 } else {
11415 ring = &dev_priv->ring[RCS];
11416 }
11417
11418 mmio_flip = use_mmio_flip(ring, obj);
11419
11420 /* When using CS flips, we want to emit semaphores between rings.
11421 * However, when using mmio flips we will create a task to do the
11422 * synchronisation, so all we want here is to pin the framebuffer
11423 * into the display plane and skip any waits.
11424 */
11425 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11426 crtc->primary->state,
11427 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
11428 if (ret)
11429 goto cleanup_pending;
11430
11431 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11432 obj, 0);
11433 work->gtt_offset += intel_crtc->dspaddr_offset;
11434
11435 if (mmio_flip) {
11436 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11437 page_flip_flags);
11438 if (ret)
11439 goto cleanup_unpin;
11440
11441 i915_gem_request_assign(&work->flip_queued_req,
11442 obj->last_write_req);
11443 } else {
11444 if (!request) {
11445 ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11446 if (ret)
11447 goto cleanup_unpin;
11448 }
11449
11450 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11451 page_flip_flags);
11452 if (ret)
11453 goto cleanup_unpin;
11454
11455 i915_gem_request_assign(&work->flip_queued_req, request);
11456 }
11457
11458 if (request)
11459 i915_add_request_no_flush(request);
11460
11461 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11462 work->enable_stall_check = true;
11463
11464 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11465 to_intel_plane(primary)->frontbuffer_bit);
11466 mutex_unlock(&dev->struct_mutex);
11467
11468 intel_fbc_disable_crtc(intel_crtc);
11469 intel_frontbuffer_flip_prepare(dev,
11470 to_intel_plane(primary)->frontbuffer_bit);
11471
11472 trace_i915_flip_request(intel_crtc->plane, obj);
11473
11474 return 0;
11475
11476 cleanup_unpin:
11477 intel_unpin_fb_obj(fb, crtc->primary->state);
11478 cleanup_pending:
11479 if (request)
11480 i915_gem_request_cancel(request);
11481 atomic_dec(&intel_crtc->unpin_work_count);
11482 mutex_unlock(&dev->struct_mutex);
11483 cleanup:
11484 crtc->primary->fb = old_fb;
11485 update_state_fb(crtc->primary);
11486
11487 drm_gem_object_unreference_unlocked(&obj->base);
11488 drm_framebuffer_unreference(work->old_fb);
11489
11490 spin_lock_irq(&dev->event_lock);
11491 intel_crtc->unpin_work = NULL;
11492 spin_unlock_irq(&dev->event_lock);
11493
11494 drm_crtc_vblank_put(crtc);
11495 free_work:
11496 kfree(work);
11497
11498 if (ret == -EIO) {
11499 struct drm_atomic_state *state;
11500 struct drm_plane_state *plane_state;
11501
11502 out_hang:
11503 state = drm_atomic_state_alloc(dev);
11504 if (!state)
11505 return -ENOMEM;
11506 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11507
11508 retry:
11509 plane_state = drm_atomic_get_plane_state(state, primary);
11510 ret = PTR_ERR_OR_ZERO(plane_state);
11511 if (!ret) {
11512 drm_atomic_set_fb_for_plane(plane_state, fb);
11513
11514 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11515 if (!ret)
11516 ret = drm_atomic_commit(state);
11517 }
11518
11519 if (ret == -EDEADLK) {
11520 drm_modeset_backoff(state->acquire_ctx);
11521 drm_atomic_state_clear(state);
11522 goto retry;
11523 }
11524
11525 if (ret)
11526 drm_atomic_state_free(state);
11527
11528 if (ret == 0 && event) {
11529 spin_lock_irq(&dev->event_lock);
11530 drm_send_vblank_event(dev, pipe, event);
11531 spin_unlock_irq(&dev->event_lock);
11532 }
11533 }
11534 return ret;
11535 }
11536
11537
11538 /**
11539 * intel_wm_need_update - Check whether watermarks need updating
11540 * @plane: drm plane
11541 * @state: new plane state
11542 *
11543 * Check current plane state versus the new one to determine whether
11544 * watermarks need to be recalculated.
11545 *
11546 * Returns true or false.
11547 */
11548 static bool intel_wm_need_update(struct drm_plane *plane,
11549 struct drm_plane_state *state)
11550 {
11551 /* Update watermarks on tiling changes. */
11552 if (!plane->state->fb || !state->fb ||
11553 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11554 plane->state->rotation != state->rotation)
11555 return true;
11556
11557 if (plane->state->crtc_w != state->crtc_w)
11558 return true;
11559
11560 return false;
11561 }
11562
11563 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11564 struct drm_plane_state *plane_state)
11565 {
11566 struct drm_crtc *crtc = crtc_state->crtc;
11567 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11568 struct drm_plane *plane = plane_state->plane;
11569 struct drm_device *dev = crtc->dev;
11570 struct drm_i915_private *dev_priv = dev->dev_private;
11571 struct intel_plane_state *old_plane_state =
11572 to_intel_plane_state(plane->state);
11573 int idx = intel_crtc->base.base.id, ret;
11574 int i = drm_plane_index(plane);
11575 bool mode_changed = needs_modeset(crtc_state);
11576 bool was_crtc_enabled = crtc->state->active;
11577 bool is_crtc_enabled = crtc_state->active;
11578
11579 bool turn_off, turn_on, visible, was_visible;
11580 struct drm_framebuffer *fb = plane_state->fb;
11581
11582 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11583 plane->type != DRM_PLANE_TYPE_CURSOR) {
11584 ret = skl_update_scaler_plane(
11585 to_intel_crtc_state(crtc_state),
11586 to_intel_plane_state(plane_state));
11587 if (ret)
11588 return ret;
11589 }
11590
11591 was_visible = old_plane_state->visible;
11592 visible = to_intel_plane_state(plane_state)->visible;
11593
11594 if (!was_crtc_enabled && WARN_ON(was_visible))
11595 was_visible = false;
11596
11597 if (!is_crtc_enabled && WARN_ON(visible))
11598 visible = false;
11599
11600 if (!was_visible && !visible)
11601 return 0;
11602
11603 turn_off = was_visible && (!visible || mode_changed);
11604 turn_on = visible && (!was_visible || mode_changed);
11605
11606 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11607 plane->base.id, fb ? fb->base.id : -1);
11608
11609 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11610 plane->base.id, was_visible, visible,
11611 turn_off, turn_on, mode_changed);
11612
11613 if (turn_on) {
11614 intel_crtc->atomic.update_wm_pre = true;
11615 /* must disable cxsr around plane enable/disable */
11616 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11617 intel_crtc->atomic.disable_cxsr = true;
11618 /* to potentially re-enable cxsr */
11619 intel_crtc->atomic.wait_vblank = true;
11620 intel_crtc->atomic.update_wm_post = true;
11621 }
11622 } else if (turn_off) {
11623 intel_crtc->atomic.update_wm_post = true;
11624 /* must disable cxsr around plane enable/disable */
11625 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11626 if (is_crtc_enabled)
11627 intel_crtc->atomic.wait_vblank = true;
11628 intel_crtc->atomic.disable_cxsr = true;
11629 }
11630 } else if (intel_wm_need_update(plane, plane_state)) {
11631 intel_crtc->atomic.update_wm_pre = true;
11632 }
11633
11634 if (visible || was_visible)
11635 intel_crtc->atomic.fb_bits |=
11636 to_intel_plane(plane)->frontbuffer_bit;
11637
11638 switch (plane->type) {
11639 case DRM_PLANE_TYPE_PRIMARY:
11640 intel_crtc->atomic.wait_for_flips = true;
11641 intel_crtc->atomic.pre_disable_primary = turn_off;
11642 intel_crtc->atomic.post_enable_primary = turn_on;
11643
11644 if (turn_off) {
11645 /*
11646 * FIXME: Actually if we will still have any other
11647 * plane enabled on the pipe we could let IPS enabled
11648 * still, but for now lets consider that when we make
11649 * primary invisible by setting DSPCNTR to 0 on
11650 * update_primary_plane function IPS needs to be
11651 * disable.
11652 */
11653 intel_crtc->atomic.disable_ips = true;
11654
11655 intel_crtc->atomic.disable_fbc = true;
11656 }
11657
11658 /*
11659 * FBC does not work on some platforms for rotated
11660 * planes, so disable it when rotation is not 0 and
11661 * update it when rotation is set back to 0.
11662 *
11663 * FIXME: This is redundant with the fbc update done in
11664 * the primary plane enable function except that that
11665 * one is done too late. We eventually need to unify
11666 * this.
11667 */
11668
11669 if (visible &&
11670 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11671 dev_priv->fbc.crtc == intel_crtc &&
11672 plane_state->rotation != BIT(DRM_ROTATE_0))
11673 intel_crtc->atomic.disable_fbc = true;
11674
11675 /*
11676 * BDW signals flip done immediately if the plane
11677 * is disabled, even if the plane enable is already
11678 * armed to occur at the next vblank :(
11679 */
11680 if (turn_on && IS_BROADWELL(dev))
11681 intel_crtc->atomic.wait_vblank = true;
11682
11683 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11684 break;
11685 case DRM_PLANE_TYPE_CURSOR:
11686 break;
11687 case DRM_PLANE_TYPE_OVERLAY:
11688 if (turn_off && !mode_changed) {
11689 intel_crtc->atomic.wait_vblank = true;
11690 intel_crtc->atomic.update_sprite_watermarks |=
11691 1 << i;
11692 }
11693 }
11694 return 0;
11695 }
11696
11697 static bool encoders_cloneable(const struct intel_encoder *a,
11698 const struct intel_encoder *b)
11699 {
11700 /* masks could be asymmetric, so check both ways */
11701 return a == b || (a->cloneable & (1 << b->type) &&
11702 b->cloneable & (1 << a->type));
11703 }
11704
11705 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11706 struct intel_crtc *crtc,
11707 struct intel_encoder *encoder)
11708 {
11709 struct intel_encoder *source_encoder;
11710 struct drm_connector *connector;
11711 struct drm_connector_state *connector_state;
11712 int i;
11713
11714 for_each_connector_in_state(state, connector, connector_state, i) {
11715 if (connector_state->crtc != &crtc->base)
11716 continue;
11717
11718 source_encoder =
11719 to_intel_encoder(connector_state->best_encoder);
11720 if (!encoders_cloneable(encoder, source_encoder))
11721 return false;
11722 }
11723
11724 return true;
11725 }
11726
11727 static bool check_encoder_cloning(struct drm_atomic_state *state,
11728 struct intel_crtc *crtc)
11729 {
11730 struct intel_encoder *encoder;
11731 struct drm_connector *connector;
11732 struct drm_connector_state *connector_state;
11733 int i;
11734
11735 for_each_connector_in_state(state, connector, connector_state, i) {
11736 if (connector_state->crtc != &crtc->base)
11737 continue;
11738
11739 encoder = to_intel_encoder(connector_state->best_encoder);
11740 if (!check_single_encoder_cloning(state, crtc, encoder))
11741 return false;
11742 }
11743
11744 return true;
11745 }
11746
11747 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11748 struct drm_crtc_state *crtc_state)
11749 {
11750 struct drm_device *dev = crtc->dev;
11751 struct drm_i915_private *dev_priv = dev->dev_private;
11752 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11753 struct intel_crtc_state *pipe_config =
11754 to_intel_crtc_state(crtc_state);
11755 struct drm_atomic_state *state = crtc_state->state;
11756 int ret;
11757 bool mode_changed = needs_modeset(crtc_state);
11758
11759 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11760 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11761 return -EINVAL;
11762 }
11763
11764 if (mode_changed && !crtc_state->active)
11765 intel_crtc->atomic.update_wm_post = true;
11766
11767 if (mode_changed && crtc_state->enable &&
11768 dev_priv->display.crtc_compute_clock &&
11769 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11770 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11771 pipe_config);
11772 if (ret)
11773 return ret;
11774 }
11775
11776 ret = 0;
11777 if (INTEL_INFO(dev)->gen >= 9) {
11778 if (mode_changed)
11779 ret = skl_update_scaler_crtc(pipe_config);
11780
11781 if (!ret)
11782 ret = intel_atomic_setup_scalers(dev, intel_crtc,
11783 pipe_config);
11784 }
11785
11786 return ret;
11787 }
11788
11789 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11790 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11791 .load_lut = intel_crtc_load_lut,
11792 .atomic_begin = intel_begin_crtc_commit,
11793 .atomic_flush = intel_finish_crtc_commit,
11794 .atomic_check = intel_crtc_atomic_check,
11795 };
11796
11797 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11798 {
11799 struct intel_connector *connector;
11800
11801 for_each_intel_connector(dev, connector) {
11802 if (connector->base.encoder) {
11803 connector->base.state->best_encoder =
11804 connector->base.encoder;
11805 connector->base.state->crtc =
11806 connector->base.encoder->crtc;
11807 } else {
11808 connector->base.state->best_encoder = NULL;
11809 connector->base.state->crtc = NULL;
11810 }
11811 }
11812 }
11813
11814 static void
11815 connected_sink_compute_bpp(struct intel_connector *connector,
11816 struct intel_crtc_state *pipe_config)
11817 {
11818 int bpp = pipe_config->pipe_bpp;
11819
11820 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11821 connector->base.base.id,
11822 connector->base.name);
11823
11824 /* Don't use an invalid EDID bpc value */
11825 if (connector->base.display_info.bpc &&
11826 connector->base.display_info.bpc * 3 < bpp) {
11827 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11828 bpp, connector->base.display_info.bpc*3);
11829 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11830 }
11831
11832 /* Clamp bpp to 8 on screens without EDID 1.4 */
11833 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11834 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11835 bpp);
11836 pipe_config->pipe_bpp = 24;
11837 }
11838 }
11839
11840 static int
11841 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11842 struct intel_crtc_state *pipe_config)
11843 {
11844 struct drm_device *dev = crtc->base.dev;
11845 struct drm_atomic_state *state;
11846 struct drm_connector *connector;
11847 struct drm_connector_state *connector_state;
11848 int bpp, i;
11849
11850 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11851 bpp = 10*3;
11852 else if (INTEL_INFO(dev)->gen >= 5)
11853 bpp = 12*3;
11854 else
11855 bpp = 8*3;
11856
11857
11858 pipe_config->pipe_bpp = bpp;
11859
11860 state = pipe_config->base.state;
11861
11862 /* Clamp display bpp to EDID value */
11863 for_each_connector_in_state(state, connector, connector_state, i) {
11864 if (connector_state->crtc != &crtc->base)
11865 continue;
11866
11867 connected_sink_compute_bpp(to_intel_connector(connector),
11868 pipe_config);
11869 }
11870
11871 return bpp;
11872 }
11873
11874 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11875 {
11876 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11877 "type: 0x%x flags: 0x%x\n",
11878 mode->crtc_clock,
11879 mode->crtc_hdisplay, mode->crtc_hsync_start,
11880 mode->crtc_hsync_end, mode->crtc_htotal,
11881 mode->crtc_vdisplay, mode->crtc_vsync_start,
11882 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11883 }
11884
11885 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11886 struct intel_crtc_state *pipe_config,
11887 const char *context)
11888 {
11889 struct drm_device *dev = crtc->base.dev;
11890 struct drm_plane *plane;
11891 struct intel_plane *intel_plane;
11892 struct intel_plane_state *state;
11893 struct drm_framebuffer *fb;
11894
11895 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11896 context, pipe_config, pipe_name(crtc->pipe));
11897
11898 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11899 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11900 pipe_config->pipe_bpp, pipe_config->dither);
11901 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11902 pipe_config->has_pch_encoder,
11903 pipe_config->fdi_lanes,
11904 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11905 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11906 pipe_config->fdi_m_n.tu);
11907 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11908 pipe_config->has_dp_encoder,
11909 pipe_config->lane_count,
11910 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11911 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11912 pipe_config->dp_m_n.tu);
11913
11914 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11915 pipe_config->has_dp_encoder,
11916 pipe_config->lane_count,
11917 pipe_config->dp_m2_n2.gmch_m,
11918 pipe_config->dp_m2_n2.gmch_n,
11919 pipe_config->dp_m2_n2.link_m,
11920 pipe_config->dp_m2_n2.link_n,
11921 pipe_config->dp_m2_n2.tu);
11922
11923 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11924 pipe_config->has_audio,
11925 pipe_config->has_infoframe);
11926
11927 DRM_DEBUG_KMS("requested mode:\n");
11928 drm_mode_debug_printmodeline(&pipe_config->base.mode);
11929 DRM_DEBUG_KMS("adjusted mode:\n");
11930 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11931 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11932 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
11933 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11934 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
11935 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11936 crtc->num_scalers,
11937 pipe_config->scaler_state.scaler_users,
11938 pipe_config->scaler_state.scaler_id);
11939 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11940 pipe_config->gmch_pfit.control,
11941 pipe_config->gmch_pfit.pgm_ratios,
11942 pipe_config->gmch_pfit.lvds_border_bits);
11943 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11944 pipe_config->pch_pfit.pos,
11945 pipe_config->pch_pfit.size,
11946 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
11947 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
11948 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
11949
11950 if (IS_BROXTON(dev)) {
11951 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
11952 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11953 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
11954 pipe_config->ddi_pll_sel,
11955 pipe_config->dpll_hw_state.ebb0,
11956 pipe_config->dpll_hw_state.ebb4,
11957 pipe_config->dpll_hw_state.pll0,
11958 pipe_config->dpll_hw_state.pll1,
11959 pipe_config->dpll_hw_state.pll2,
11960 pipe_config->dpll_hw_state.pll3,
11961 pipe_config->dpll_hw_state.pll6,
11962 pipe_config->dpll_hw_state.pll8,
11963 pipe_config->dpll_hw_state.pll9,
11964 pipe_config->dpll_hw_state.pll10,
11965 pipe_config->dpll_hw_state.pcsdw12);
11966 } else if (IS_SKYLAKE(dev)) {
11967 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11968 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11969 pipe_config->ddi_pll_sel,
11970 pipe_config->dpll_hw_state.ctrl1,
11971 pipe_config->dpll_hw_state.cfgcr1,
11972 pipe_config->dpll_hw_state.cfgcr2);
11973 } else if (HAS_DDI(dev)) {
11974 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11975 pipe_config->ddi_pll_sel,
11976 pipe_config->dpll_hw_state.wrpll);
11977 } else {
11978 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11979 "fp0: 0x%x, fp1: 0x%x\n",
11980 pipe_config->dpll_hw_state.dpll,
11981 pipe_config->dpll_hw_state.dpll_md,
11982 pipe_config->dpll_hw_state.fp0,
11983 pipe_config->dpll_hw_state.fp1);
11984 }
11985
11986 DRM_DEBUG_KMS("planes on this crtc\n");
11987 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11988 intel_plane = to_intel_plane(plane);
11989 if (intel_plane->pipe != crtc->pipe)
11990 continue;
11991
11992 state = to_intel_plane_state(plane->state);
11993 fb = state->base.fb;
11994 if (!fb) {
11995 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11996 "disabled, scaler_id = %d\n",
11997 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11998 plane->base.id, intel_plane->pipe,
11999 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12000 drm_plane_index(plane), state->scaler_id);
12001 continue;
12002 }
12003
12004 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12005 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12006 plane->base.id, intel_plane->pipe,
12007 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12008 drm_plane_index(plane));
12009 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12010 fb->base.id, fb->width, fb->height, fb->pixel_format);
12011 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12012 state->scaler_id,
12013 state->src.x1 >> 16, state->src.y1 >> 16,
12014 drm_rect_width(&state->src) >> 16,
12015 drm_rect_height(&state->src) >> 16,
12016 state->dst.x1, state->dst.y1,
12017 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12018 }
12019 }
12020
12021 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12022 {
12023 struct drm_device *dev = state->dev;
12024 struct intel_encoder *encoder;
12025 struct drm_connector *connector;
12026 struct drm_connector_state *connector_state;
12027 unsigned int used_ports = 0;
12028 int i;
12029
12030 /*
12031 * Walk the connector list instead of the encoder
12032 * list to detect the problem on ddi platforms
12033 * where there's just one encoder per digital port.
12034 */
12035 for_each_connector_in_state(state, connector, connector_state, i) {
12036 if (!connector_state->best_encoder)
12037 continue;
12038
12039 encoder = to_intel_encoder(connector_state->best_encoder);
12040
12041 WARN_ON(!connector_state->crtc);
12042
12043 switch (encoder->type) {
12044 unsigned int port_mask;
12045 case INTEL_OUTPUT_UNKNOWN:
12046 if (WARN_ON(!HAS_DDI(dev)))
12047 break;
12048 case INTEL_OUTPUT_DISPLAYPORT:
12049 case INTEL_OUTPUT_HDMI:
12050 case INTEL_OUTPUT_EDP:
12051 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12052
12053 /* the same port mustn't appear more than once */
12054 if (used_ports & port_mask)
12055 return false;
12056
12057 used_ports |= port_mask;
12058 default:
12059 break;
12060 }
12061 }
12062
12063 return true;
12064 }
12065
12066 static void
12067 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12068 {
12069 struct drm_crtc_state tmp_state;
12070 struct intel_crtc_scaler_state scaler_state;
12071 struct intel_dpll_hw_state dpll_hw_state;
12072 enum intel_dpll_id shared_dpll;
12073 uint32_t ddi_pll_sel;
12074 bool force_thru;
12075
12076 /* FIXME: before the switch to atomic started, a new pipe_config was
12077 * kzalloc'd. Code that depends on any field being zero should be
12078 * fixed, so that the crtc_state can be safely duplicated. For now,
12079 * only fields that are know to not cause problems are preserved. */
12080
12081 tmp_state = crtc_state->base;
12082 scaler_state = crtc_state->scaler_state;
12083 shared_dpll = crtc_state->shared_dpll;
12084 dpll_hw_state = crtc_state->dpll_hw_state;
12085 ddi_pll_sel = crtc_state->ddi_pll_sel;
12086 force_thru = crtc_state->pch_pfit.force_thru;
12087
12088 memset(crtc_state, 0, sizeof *crtc_state);
12089
12090 crtc_state->base = tmp_state;
12091 crtc_state->scaler_state = scaler_state;
12092 crtc_state->shared_dpll = shared_dpll;
12093 crtc_state->dpll_hw_state = dpll_hw_state;
12094 crtc_state->ddi_pll_sel = ddi_pll_sel;
12095 crtc_state->pch_pfit.force_thru = force_thru;
12096 }
12097
12098 static int
12099 intel_modeset_pipe_config(struct drm_crtc *crtc,
12100 struct intel_crtc_state *pipe_config)
12101 {
12102 struct drm_atomic_state *state = pipe_config->base.state;
12103 struct intel_encoder *encoder;
12104 struct drm_connector *connector;
12105 struct drm_connector_state *connector_state;
12106 int base_bpp, ret = -EINVAL;
12107 int i;
12108 bool retry = true;
12109
12110 clear_intel_crtc_state(pipe_config);
12111
12112 pipe_config->cpu_transcoder =
12113 (enum transcoder) to_intel_crtc(crtc)->pipe;
12114
12115 /*
12116 * Sanitize sync polarity flags based on requested ones. If neither
12117 * positive or negative polarity is requested, treat this as meaning
12118 * negative polarity.
12119 */
12120 if (!(pipe_config->base.adjusted_mode.flags &
12121 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12122 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12123
12124 if (!(pipe_config->base.adjusted_mode.flags &
12125 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12126 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12127
12128 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12129 pipe_config);
12130 if (base_bpp < 0)
12131 goto fail;
12132
12133 /*
12134 * Determine the real pipe dimensions. Note that stereo modes can
12135 * increase the actual pipe size due to the frame doubling and
12136 * insertion of additional space for blanks between the frame. This
12137 * is stored in the crtc timings. We use the requested mode to do this
12138 * computation to clearly distinguish it from the adjusted mode, which
12139 * can be changed by the connectors in the below retry loop.
12140 */
12141 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12142 &pipe_config->pipe_src_w,
12143 &pipe_config->pipe_src_h);
12144
12145 encoder_retry:
12146 /* Ensure the port clock defaults are reset when retrying. */
12147 pipe_config->port_clock = 0;
12148 pipe_config->pixel_multiplier = 1;
12149
12150 /* Fill in default crtc timings, allow encoders to overwrite them. */
12151 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12152 CRTC_STEREO_DOUBLE);
12153
12154 /* Pass our mode to the connectors and the CRTC to give them a chance to
12155 * adjust it according to limitations or connector properties, and also
12156 * a chance to reject the mode entirely.
12157 */
12158 for_each_connector_in_state(state, connector, connector_state, i) {
12159 if (connector_state->crtc != crtc)
12160 continue;
12161
12162 encoder = to_intel_encoder(connector_state->best_encoder);
12163
12164 if (!(encoder->compute_config(encoder, pipe_config))) {
12165 DRM_DEBUG_KMS("Encoder config failure\n");
12166 goto fail;
12167 }
12168 }
12169
12170 /* Set default port clock if not overwritten by the encoder. Needs to be
12171 * done afterwards in case the encoder adjusts the mode. */
12172 if (!pipe_config->port_clock)
12173 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12174 * pipe_config->pixel_multiplier;
12175
12176 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12177 if (ret < 0) {
12178 DRM_DEBUG_KMS("CRTC fixup failed\n");
12179 goto fail;
12180 }
12181
12182 if (ret == RETRY) {
12183 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12184 ret = -EINVAL;
12185 goto fail;
12186 }
12187
12188 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12189 retry = false;
12190 goto encoder_retry;
12191 }
12192
12193 /* Dithering seems to not pass-through bits correctly when it should, so
12194 * only enable it on 6bpc panels. */
12195 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12196 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12197 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12198
12199 fail:
12200 return ret;
12201 }
12202
12203 static void
12204 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12205 {
12206 struct drm_crtc *crtc;
12207 struct drm_crtc_state *crtc_state;
12208 int i;
12209
12210 /* Double check state. */
12211 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12212 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12213
12214 /* Update hwmode for vblank functions */
12215 if (crtc->state->active)
12216 crtc->hwmode = crtc->state->adjusted_mode;
12217 else
12218 crtc->hwmode.crtc_clock = 0;
12219 }
12220 }
12221
12222 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12223 {
12224 int diff;
12225
12226 if (clock1 == clock2)
12227 return true;
12228
12229 if (!clock1 || !clock2)
12230 return false;
12231
12232 diff = abs(clock1 - clock2);
12233
12234 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12235 return true;
12236
12237 return false;
12238 }
12239
12240 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12241 list_for_each_entry((intel_crtc), \
12242 &(dev)->mode_config.crtc_list, \
12243 base.head) \
12244 if (mask & (1 <<(intel_crtc)->pipe))
12245
12246 static bool
12247 intel_compare_m_n(unsigned int m, unsigned int n,
12248 unsigned int m2, unsigned int n2,
12249 bool exact)
12250 {
12251 if (m == m2 && n == n2)
12252 return true;
12253
12254 if (exact || !m || !n || !m2 || !n2)
12255 return false;
12256
12257 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12258
12259 if (m > m2) {
12260 while (m > m2) {
12261 m2 <<= 1;
12262 n2 <<= 1;
12263 }
12264 } else if (m < m2) {
12265 while (m < m2) {
12266 m <<= 1;
12267 n <<= 1;
12268 }
12269 }
12270
12271 return m == m2 && n == n2;
12272 }
12273
12274 static bool
12275 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12276 struct intel_link_m_n *m2_n2,
12277 bool adjust)
12278 {
12279 if (m_n->tu == m2_n2->tu &&
12280 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12281 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12282 intel_compare_m_n(m_n->link_m, m_n->link_n,
12283 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12284 if (adjust)
12285 *m2_n2 = *m_n;
12286
12287 return true;
12288 }
12289
12290 return false;
12291 }
12292
12293 static bool
12294 intel_pipe_config_compare(struct drm_device *dev,
12295 struct intel_crtc_state *current_config,
12296 struct intel_crtc_state *pipe_config,
12297 bool adjust)
12298 {
12299 bool ret = true;
12300
12301 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12302 do { \
12303 if (!adjust) \
12304 DRM_ERROR(fmt, ##__VA_ARGS__); \
12305 else \
12306 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12307 } while (0)
12308
12309 #define PIPE_CONF_CHECK_X(name) \
12310 if (current_config->name != pipe_config->name) { \
12311 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12312 "(expected 0x%08x, found 0x%08x)\n", \
12313 current_config->name, \
12314 pipe_config->name); \
12315 ret = false; \
12316 }
12317
12318 #define PIPE_CONF_CHECK_I(name) \
12319 if (current_config->name != pipe_config->name) { \
12320 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12321 "(expected %i, found %i)\n", \
12322 current_config->name, \
12323 pipe_config->name); \
12324 ret = false; \
12325 }
12326
12327 #define PIPE_CONF_CHECK_M_N(name) \
12328 if (!intel_compare_link_m_n(&current_config->name, \
12329 &pipe_config->name,\
12330 adjust)) { \
12331 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12332 "(expected tu %i gmch %i/%i link %i/%i, " \
12333 "found tu %i, gmch %i/%i link %i/%i)\n", \
12334 current_config->name.tu, \
12335 current_config->name.gmch_m, \
12336 current_config->name.gmch_n, \
12337 current_config->name.link_m, \
12338 current_config->name.link_n, \
12339 pipe_config->name.tu, \
12340 pipe_config->name.gmch_m, \
12341 pipe_config->name.gmch_n, \
12342 pipe_config->name.link_m, \
12343 pipe_config->name.link_n); \
12344 ret = false; \
12345 }
12346
12347 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12348 if (!intel_compare_link_m_n(&current_config->name, \
12349 &pipe_config->name, adjust) && \
12350 !intel_compare_link_m_n(&current_config->alt_name, \
12351 &pipe_config->name, adjust)) { \
12352 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12353 "(expected tu %i gmch %i/%i link %i/%i, " \
12354 "or tu %i gmch %i/%i link %i/%i, " \
12355 "found tu %i, gmch %i/%i link %i/%i)\n", \
12356 current_config->name.tu, \
12357 current_config->name.gmch_m, \
12358 current_config->name.gmch_n, \
12359 current_config->name.link_m, \
12360 current_config->name.link_n, \
12361 current_config->alt_name.tu, \
12362 current_config->alt_name.gmch_m, \
12363 current_config->alt_name.gmch_n, \
12364 current_config->alt_name.link_m, \
12365 current_config->alt_name.link_n, \
12366 pipe_config->name.tu, \
12367 pipe_config->name.gmch_m, \
12368 pipe_config->name.gmch_n, \
12369 pipe_config->name.link_m, \
12370 pipe_config->name.link_n); \
12371 ret = false; \
12372 }
12373
12374 /* This is required for BDW+ where there is only one set of registers for
12375 * switching between high and low RR.
12376 * This macro can be used whenever a comparison has to be made between one
12377 * hw state and multiple sw state variables.
12378 */
12379 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12380 if ((current_config->name != pipe_config->name) && \
12381 (current_config->alt_name != pipe_config->name)) { \
12382 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12383 "(expected %i or %i, found %i)\n", \
12384 current_config->name, \
12385 current_config->alt_name, \
12386 pipe_config->name); \
12387 ret = false; \
12388 }
12389
12390 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12391 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12392 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12393 "(expected %i, found %i)\n", \
12394 current_config->name & (mask), \
12395 pipe_config->name & (mask)); \
12396 ret = false; \
12397 }
12398
12399 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12400 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12401 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12402 "(expected %i, found %i)\n", \
12403 current_config->name, \
12404 pipe_config->name); \
12405 ret = false; \
12406 }
12407
12408 #define PIPE_CONF_QUIRK(quirk) \
12409 ((current_config->quirks | pipe_config->quirks) & (quirk))
12410
12411 PIPE_CONF_CHECK_I(cpu_transcoder);
12412
12413 PIPE_CONF_CHECK_I(has_pch_encoder);
12414 PIPE_CONF_CHECK_I(fdi_lanes);
12415 PIPE_CONF_CHECK_M_N(fdi_m_n);
12416
12417 PIPE_CONF_CHECK_I(has_dp_encoder);
12418 PIPE_CONF_CHECK_I(lane_count);
12419
12420 if (INTEL_INFO(dev)->gen < 8) {
12421 PIPE_CONF_CHECK_M_N(dp_m_n);
12422
12423 PIPE_CONF_CHECK_I(has_drrs);
12424 if (current_config->has_drrs)
12425 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12426 } else
12427 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12428
12429 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12430 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12431 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12432 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12433 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12434 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12435
12436 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12437 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12438 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12439 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12440 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12441 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12442
12443 PIPE_CONF_CHECK_I(pixel_multiplier);
12444 PIPE_CONF_CHECK_I(has_hdmi_sink);
12445 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12446 IS_VALLEYVIEW(dev))
12447 PIPE_CONF_CHECK_I(limited_color_range);
12448 PIPE_CONF_CHECK_I(has_infoframe);
12449
12450 PIPE_CONF_CHECK_I(has_audio);
12451
12452 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12453 DRM_MODE_FLAG_INTERLACE);
12454
12455 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12456 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12457 DRM_MODE_FLAG_PHSYNC);
12458 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12459 DRM_MODE_FLAG_NHSYNC);
12460 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12461 DRM_MODE_FLAG_PVSYNC);
12462 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12463 DRM_MODE_FLAG_NVSYNC);
12464 }
12465
12466 PIPE_CONF_CHECK_X(gmch_pfit.control);
12467 /* pfit ratios are autocomputed by the hw on gen4+ */
12468 if (INTEL_INFO(dev)->gen < 4)
12469 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12470 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12471
12472 if (!adjust) {
12473 PIPE_CONF_CHECK_I(pipe_src_w);
12474 PIPE_CONF_CHECK_I(pipe_src_h);
12475
12476 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12477 if (current_config->pch_pfit.enabled) {
12478 PIPE_CONF_CHECK_X(pch_pfit.pos);
12479 PIPE_CONF_CHECK_X(pch_pfit.size);
12480 }
12481
12482 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12483 }
12484
12485 /* BDW+ don't expose a synchronous way to read the state */
12486 if (IS_HASWELL(dev))
12487 PIPE_CONF_CHECK_I(ips_enabled);
12488
12489 PIPE_CONF_CHECK_I(double_wide);
12490
12491 PIPE_CONF_CHECK_X(ddi_pll_sel);
12492
12493 PIPE_CONF_CHECK_I(shared_dpll);
12494 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12495 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12496 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12497 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12498 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12499 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12500 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12501 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12502
12503 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12504 PIPE_CONF_CHECK_I(pipe_bpp);
12505
12506 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12507 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12508
12509 #undef PIPE_CONF_CHECK_X
12510 #undef PIPE_CONF_CHECK_I
12511 #undef PIPE_CONF_CHECK_I_ALT
12512 #undef PIPE_CONF_CHECK_FLAGS
12513 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12514 #undef PIPE_CONF_QUIRK
12515 #undef INTEL_ERR_OR_DBG_KMS
12516
12517 return ret;
12518 }
12519
12520 static void check_wm_state(struct drm_device *dev)
12521 {
12522 struct drm_i915_private *dev_priv = dev->dev_private;
12523 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12524 struct intel_crtc *intel_crtc;
12525 int plane;
12526
12527 if (INTEL_INFO(dev)->gen < 9)
12528 return;
12529
12530 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12531 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12532
12533 for_each_intel_crtc(dev, intel_crtc) {
12534 struct skl_ddb_entry *hw_entry, *sw_entry;
12535 const enum pipe pipe = intel_crtc->pipe;
12536
12537 if (!intel_crtc->active)
12538 continue;
12539
12540 /* planes */
12541 for_each_plane(dev_priv, pipe, plane) {
12542 hw_entry = &hw_ddb.plane[pipe][plane];
12543 sw_entry = &sw_ddb->plane[pipe][plane];
12544
12545 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12546 continue;
12547
12548 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12549 "(expected (%u,%u), found (%u,%u))\n",
12550 pipe_name(pipe), plane + 1,
12551 sw_entry->start, sw_entry->end,
12552 hw_entry->start, hw_entry->end);
12553 }
12554
12555 /* cursor */
12556 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12557 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12558
12559 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12560 continue;
12561
12562 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12563 "(expected (%u,%u), found (%u,%u))\n",
12564 pipe_name(pipe),
12565 sw_entry->start, sw_entry->end,
12566 hw_entry->start, hw_entry->end);
12567 }
12568 }
12569
12570 static void
12571 check_connector_state(struct drm_device *dev,
12572 struct drm_atomic_state *old_state)
12573 {
12574 struct drm_connector_state *old_conn_state;
12575 struct drm_connector *connector;
12576 int i;
12577
12578 for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12579 struct drm_encoder *encoder = connector->encoder;
12580 struct drm_connector_state *state = connector->state;
12581
12582 /* This also checks the encoder/connector hw state with the
12583 * ->get_hw_state callbacks. */
12584 intel_connector_check_state(to_intel_connector(connector));
12585
12586 I915_STATE_WARN(state->best_encoder != encoder,
12587 "connector's atomic encoder doesn't match legacy encoder\n");
12588 }
12589 }
12590
12591 static void
12592 check_encoder_state(struct drm_device *dev)
12593 {
12594 struct intel_encoder *encoder;
12595 struct intel_connector *connector;
12596
12597 for_each_intel_encoder(dev, encoder) {
12598 bool enabled = false;
12599 enum pipe pipe;
12600
12601 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12602 encoder->base.base.id,
12603 encoder->base.name);
12604
12605 for_each_intel_connector(dev, connector) {
12606 if (connector->base.state->best_encoder != &encoder->base)
12607 continue;
12608 enabled = true;
12609
12610 I915_STATE_WARN(connector->base.state->crtc !=
12611 encoder->base.crtc,
12612 "connector's crtc doesn't match encoder crtc\n");
12613 }
12614
12615 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12616 "encoder's enabled state mismatch "
12617 "(expected %i, found %i)\n",
12618 !!encoder->base.crtc, enabled);
12619
12620 if (!encoder->base.crtc) {
12621 bool active;
12622
12623 active = encoder->get_hw_state(encoder, &pipe);
12624 I915_STATE_WARN(active,
12625 "encoder detached but still enabled on pipe %c.\n",
12626 pipe_name(pipe));
12627 }
12628 }
12629 }
12630
12631 static void
12632 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12633 {
12634 struct drm_i915_private *dev_priv = dev->dev_private;
12635 struct intel_encoder *encoder;
12636 struct drm_crtc_state *old_crtc_state;
12637 struct drm_crtc *crtc;
12638 int i;
12639
12640 for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12641 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12642 struct intel_crtc_state *pipe_config, *sw_config;
12643 bool active;
12644
12645 if (!needs_modeset(crtc->state) &&
12646 !to_intel_crtc_state(crtc->state)->update_pipe)
12647 continue;
12648
12649 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12650 pipe_config = to_intel_crtc_state(old_crtc_state);
12651 memset(pipe_config, 0, sizeof(*pipe_config));
12652 pipe_config->base.crtc = crtc;
12653 pipe_config->base.state = old_state;
12654
12655 DRM_DEBUG_KMS("[CRTC:%d]\n",
12656 crtc->base.id);
12657
12658 active = dev_priv->display.get_pipe_config(intel_crtc,
12659 pipe_config);
12660
12661 /* hw state is inconsistent with the pipe quirk */
12662 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12663 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12664 active = crtc->state->active;
12665
12666 I915_STATE_WARN(crtc->state->active != active,
12667 "crtc active state doesn't match with hw state "
12668 "(expected %i, found %i)\n", crtc->state->active, active);
12669
12670 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
12671 "transitional active state does not match atomic hw state "
12672 "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12673
12674 for_each_encoder_on_crtc(dev, crtc, encoder) {
12675 enum pipe pipe;
12676
12677 active = encoder->get_hw_state(encoder, &pipe);
12678 I915_STATE_WARN(active != crtc->state->active,
12679 "[ENCODER:%i] active %i with crtc active %i\n",
12680 encoder->base.base.id, active, crtc->state->active);
12681
12682 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12683 "Encoder connected to wrong pipe %c\n",
12684 pipe_name(pipe));
12685
12686 if (active)
12687 encoder->get_config(encoder, pipe_config);
12688 }
12689
12690 if (!crtc->state->active)
12691 continue;
12692
12693 sw_config = to_intel_crtc_state(crtc->state);
12694 if (!intel_pipe_config_compare(dev, sw_config,
12695 pipe_config, false)) {
12696 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12697 intel_dump_pipe_config(intel_crtc, pipe_config,
12698 "[hw state]");
12699 intel_dump_pipe_config(intel_crtc, sw_config,
12700 "[sw state]");
12701 }
12702 }
12703 }
12704
12705 static void
12706 check_shared_dpll_state(struct drm_device *dev)
12707 {
12708 struct drm_i915_private *dev_priv = dev->dev_private;
12709 struct intel_crtc *crtc;
12710 struct intel_dpll_hw_state dpll_hw_state;
12711 int i;
12712
12713 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12714 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12715 int enabled_crtcs = 0, active_crtcs = 0;
12716 bool active;
12717
12718 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12719
12720 DRM_DEBUG_KMS("%s\n", pll->name);
12721
12722 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12723
12724 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12725 "more active pll users than references: %i vs %i\n",
12726 pll->active, hweight32(pll->config.crtc_mask));
12727 I915_STATE_WARN(pll->active && !pll->on,
12728 "pll in active use but not on in sw tracking\n");
12729 I915_STATE_WARN(pll->on && !pll->active,
12730 "pll in on but not on in use in sw tracking\n");
12731 I915_STATE_WARN(pll->on != active,
12732 "pll on state mismatch (expected %i, found %i)\n",
12733 pll->on, active);
12734
12735 for_each_intel_crtc(dev, crtc) {
12736 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12737 enabled_crtcs++;
12738 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12739 active_crtcs++;
12740 }
12741 I915_STATE_WARN(pll->active != active_crtcs,
12742 "pll active crtcs mismatch (expected %i, found %i)\n",
12743 pll->active, active_crtcs);
12744 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12745 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12746 hweight32(pll->config.crtc_mask), enabled_crtcs);
12747
12748 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12749 sizeof(dpll_hw_state)),
12750 "pll hw state mismatch\n");
12751 }
12752 }
12753
12754 static void
12755 intel_modeset_check_state(struct drm_device *dev,
12756 struct drm_atomic_state *old_state)
12757 {
12758 check_wm_state(dev);
12759 check_connector_state(dev, old_state);
12760 check_encoder_state(dev);
12761 check_crtc_state(dev, old_state);
12762 check_shared_dpll_state(dev);
12763 }
12764
12765 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12766 int dotclock)
12767 {
12768 /*
12769 * FDI already provided one idea for the dotclock.
12770 * Yell if the encoder disagrees.
12771 */
12772 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12773 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12774 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12775 }
12776
12777 static void update_scanline_offset(struct intel_crtc *crtc)
12778 {
12779 struct drm_device *dev = crtc->base.dev;
12780
12781 /*
12782 * The scanline counter increments at the leading edge of hsync.
12783 *
12784 * On most platforms it starts counting from vtotal-1 on the
12785 * first active line. That means the scanline counter value is
12786 * always one less than what we would expect. Ie. just after
12787 * start of vblank, which also occurs at start of hsync (on the
12788 * last active line), the scanline counter will read vblank_start-1.
12789 *
12790 * On gen2 the scanline counter starts counting from 1 instead
12791 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12792 * to keep the value positive), instead of adding one.
12793 *
12794 * On HSW+ the behaviour of the scanline counter depends on the output
12795 * type. For DP ports it behaves like most other platforms, but on HDMI
12796 * there's an extra 1 line difference. So we need to add two instead of
12797 * one to the value.
12798 */
12799 if (IS_GEN2(dev)) {
12800 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
12801 int vtotal;
12802
12803 vtotal = adjusted_mode->crtc_vtotal;
12804 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12805 vtotal /= 2;
12806
12807 crtc->scanline_offset = vtotal - 1;
12808 } else if (HAS_DDI(dev) &&
12809 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12810 crtc->scanline_offset = 2;
12811 } else
12812 crtc->scanline_offset = 1;
12813 }
12814
12815 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12816 {
12817 struct drm_device *dev = state->dev;
12818 struct drm_i915_private *dev_priv = to_i915(dev);
12819 struct intel_shared_dpll_config *shared_dpll = NULL;
12820 struct intel_crtc *intel_crtc;
12821 struct intel_crtc_state *intel_crtc_state;
12822 struct drm_crtc *crtc;
12823 struct drm_crtc_state *crtc_state;
12824 int i;
12825
12826 if (!dev_priv->display.crtc_compute_clock)
12827 return;
12828
12829 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12830 int dpll;
12831
12832 intel_crtc = to_intel_crtc(crtc);
12833 intel_crtc_state = to_intel_crtc_state(crtc_state);
12834 dpll = intel_crtc_state->shared_dpll;
12835
12836 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
12837 continue;
12838
12839 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12840
12841 if (!shared_dpll)
12842 shared_dpll = intel_atomic_get_shared_dpll_state(state);
12843
12844 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12845 }
12846 }
12847
12848 /*
12849 * This implements the workaround described in the "notes" section of the mode
12850 * set sequence documentation. When going from no pipes or single pipe to
12851 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12852 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12853 */
12854 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12855 {
12856 struct drm_crtc_state *crtc_state;
12857 struct intel_crtc *intel_crtc;
12858 struct drm_crtc *crtc;
12859 struct intel_crtc_state *first_crtc_state = NULL;
12860 struct intel_crtc_state *other_crtc_state = NULL;
12861 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12862 int i;
12863
12864 /* look at all crtc's that are going to be enabled in during modeset */
12865 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12866 intel_crtc = to_intel_crtc(crtc);
12867
12868 if (!crtc_state->active || !needs_modeset(crtc_state))
12869 continue;
12870
12871 if (first_crtc_state) {
12872 other_crtc_state = to_intel_crtc_state(crtc_state);
12873 break;
12874 } else {
12875 first_crtc_state = to_intel_crtc_state(crtc_state);
12876 first_pipe = intel_crtc->pipe;
12877 }
12878 }
12879
12880 /* No workaround needed? */
12881 if (!first_crtc_state)
12882 return 0;
12883
12884 /* w/a possibly needed, check how many crtc's are already enabled. */
12885 for_each_intel_crtc(state->dev, intel_crtc) {
12886 struct intel_crtc_state *pipe_config;
12887
12888 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12889 if (IS_ERR(pipe_config))
12890 return PTR_ERR(pipe_config);
12891
12892 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12893
12894 if (!pipe_config->base.active ||
12895 needs_modeset(&pipe_config->base))
12896 continue;
12897
12898 /* 2 or more enabled crtcs means no need for w/a */
12899 if (enabled_pipe != INVALID_PIPE)
12900 return 0;
12901
12902 enabled_pipe = intel_crtc->pipe;
12903 }
12904
12905 if (enabled_pipe != INVALID_PIPE)
12906 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12907 else if (other_crtc_state)
12908 other_crtc_state->hsw_workaround_pipe = first_pipe;
12909
12910 return 0;
12911 }
12912
12913 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12914 {
12915 struct drm_crtc *crtc;
12916 struct drm_crtc_state *crtc_state;
12917 int ret = 0;
12918
12919 /* add all active pipes to the state */
12920 for_each_crtc(state->dev, crtc) {
12921 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12922 if (IS_ERR(crtc_state))
12923 return PTR_ERR(crtc_state);
12924
12925 if (!crtc_state->active || needs_modeset(crtc_state))
12926 continue;
12927
12928 crtc_state->mode_changed = true;
12929
12930 ret = drm_atomic_add_affected_connectors(state, crtc);
12931 if (ret)
12932 break;
12933
12934 ret = drm_atomic_add_affected_planes(state, crtc);
12935 if (ret)
12936 break;
12937 }
12938
12939 return ret;
12940 }
12941
12942 static int intel_modeset_checks(struct drm_atomic_state *state)
12943 {
12944 struct drm_device *dev = state->dev;
12945 struct drm_i915_private *dev_priv = dev->dev_private;
12946 int ret;
12947
12948 if (!check_digital_port_conflicts(state)) {
12949 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12950 return -EINVAL;
12951 }
12952
12953 /*
12954 * See if the config requires any additional preparation, e.g.
12955 * to adjust global state with pipes off. We need to do this
12956 * here so we can get the modeset_pipe updated config for the new
12957 * mode set on this crtc. For other crtcs we need to use the
12958 * adjusted_mode bits in the crtc directly.
12959 */
12960 if (dev_priv->display.modeset_calc_cdclk) {
12961 unsigned int cdclk;
12962
12963 ret = dev_priv->display.modeset_calc_cdclk(state);
12964
12965 cdclk = to_intel_atomic_state(state)->cdclk;
12966 if (!ret && cdclk != dev_priv->cdclk_freq)
12967 ret = intel_modeset_all_pipes(state);
12968
12969 if (ret < 0)
12970 return ret;
12971 } else
12972 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
12973
12974 intel_modeset_clear_plls(state);
12975
12976 if (IS_HASWELL(dev))
12977 return haswell_mode_set_planes_workaround(state);
12978
12979 return 0;
12980 }
12981
12982 /**
12983 * intel_atomic_check - validate state object
12984 * @dev: drm device
12985 * @state: state to validate
12986 */
12987 static int intel_atomic_check(struct drm_device *dev,
12988 struct drm_atomic_state *state)
12989 {
12990 struct drm_crtc *crtc;
12991 struct drm_crtc_state *crtc_state;
12992 int ret, i;
12993 bool any_ms = false;
12994
12995 ret = drm_atomic_helper_check_modeset(dev, state);
12996 if (ret)
12997 return ret;
12998
12999 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13000 struct intel_crtc_state *pipe_config =
13001 to_intel_crtc_state(crtc_state);
13002
13003 /* Catch I915_MODE_FLAG_INHERITED */
13004 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13005 crtc_state->mode_changed = true;
13006
13007 if (!crtc_state->enable) {
13008 if (needs_modeset(crtc_state))
13009 any_ms = true;
13010 continue;
13011 }
13012
13013 if (!needs_modeset(crtc_state))
13014 continue;
13015
13016 /* FIXME: For only active_changed we shouldn't need to do any
13017 * state recomputation at all. */
13018
13019 ret = drm_atomic_add_affected_connectors(state, crtc);
13020 if (ret)
13021 return ret;
13022
13023 ret = intel_modeset_pipe_config(crtc, pipe_config);
13024 if (ret)
13025 return ret;
13026
13027 if (intel_pipe_config_compare(state->dev,
13028 to_intel_crtc_state(crtc->state),
13029 pipe_config, true)) {
13030 crtc_state->mode_changed = false;
13031 to_intel_crtc_state(crtc_state)->update_pipe = true;
13032 }
13033
13034 if (needs_modeset(crtc_state)) {
13035 any_ms = true;
13036
13037 ret = drm_atomic_add_affected_planes(state, crtc);
13038 if (ret)
13039 return ret;
13040 }
13041
13042 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13043 needs_modeset(crtc_state) ?
13044 "[modeset]" : "[fastset]");
13045 }
13046
13047 if (any_ms) {
13048 ret = intel_modeset_checks(state);
13049
13050 if (ret)
13051 return ret;
13052 } else
13053 to_intel_atomic_state(state)->cdclk =
13054 to_i915(state->dev)->cdclk_freq;
13055
13056 return drm_atomic_helper_check_planes(state->dev, state);
13057 }
13058
13059 /**
13060 * intel_atomic_commit - commit validated state object
13061 * @dev: DRM device
13062 * @state: the top-level driver state object
13063 * @async: asynchronous commit
13064 *
13065 * This function commits a top-level state object that has been validated
13066 * with drm_atomic_helper_check().
13067 *
13068 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13069 * we can only handle plane-related operations and do not yet support
13070 * asynchronous commit.
13071 *
13072 * RETURNS
13073 * Zero for success or -errno.
13074 */
13075 static int intel_atomic_commit(struct drm_device *dev,
13076 struct drm_atomic_state *state,
13077 bool async)
13078 {
13079 struct drm_i915_private *dev_priv = dev->dev_private;
13080 struct drm_crtc *crtc;
13081 struct drm_crtc_state *crtc_state;
13082 int ret = 0;
13083 int i;
13084 bool any_ms = false;
13085
13086 if (async) {
13087 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13088 return -EINVAL;
13089 }
13090
13091 ret = drm_atomic_helper_prepare_planes(dev, state);
13092 if (ret)
13093 return ret;
13094
13095 drm_atomic_helper_swap_state(dev, state);
13096
13097 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13098 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13099
13100 if (!needs_modeset(crtc->state))
13101 continue;
13102
13103 any_ms = true;
13104 intel_pre_plane_update(intel_crtc);
13105
13106 if (crtc_state->active) {
13107 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13108 dev_priv->display.crtc_disable(crtc);
13109 intel_crtc->active = false;
13110 intel_disable_shared_dpll(intel_crtc);
13111 }
13112 }
13113
13114 /* Only after disabling all output pipelines that will be changed can we
13115 * update the the output configuration. */
13116 intel_modeset_update_crtc_state(state);
13117
13118 if (any_ms) {
13119 intel_shared_dpll_commit(state);
13120
13121 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13122 modeset_update_crtc_power_domains(state);
13123 }
13124
13125 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13126 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13127 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13128 bool modeset = needs_modeset(crtc->state);
13129 bool update_pipe = !modeset &&
13130 to_intel_crtc_state(crtc->state)->update_pipe;
13131 unsigned long put_domains = 0;
13132
13133 if (modeset && crtc->state->active) {
13134 update_scanline_offset(to_intel_crtc(crtc));
13135 dev_priv->display.crtc_enable(crtc);
13136 }
13137
13138 if (update_pipe) {
13139 put_domains = modeset_get_crtc_power_domains(crtc);
13140
13141 /* make sure intel_modeset_check_state runs */
13142 any_ms = true;
13143 }
13144
13145 if (!modeset)
13146 intel_pre_plane_update(intel_crtc);
13147
13148 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13149
13150 if (put_domains)
13151 modeset_put_power_domains(dev_priv, put_domains);
13152
13153 intel_post_plane_update(intel_crtc);
13154 }
13155
13156 /* FIXME: add subpixel order */
13157
13158 drm_atomic_helper_wait_for_vblanks(dev, state);
13159 drm_atomic_helper_cleanup_planes(dev, state);
13160
13161 if (any_ms)
13162 intel_modeset_check_state(dev, state);
13163
13164 drm_atomic_state_free(state);
13165
13166 return 0;
13167 }
13168
13169 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13170 {
13171 struct drm_device *dev = crtc->dev;
13172 struct drm_atomic_state *state;
13173 struct drm_crtc_state *crtc_state;
13174 int ret;
13175
13176 state = drm_atomic_state_alloc(dev);
13177 if (!state) {
13178 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13179 crtc->base.id);
13180 return;
13181 }
13182
13183 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13184
13185 retry:
13186 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13187 ret = PTR_ERR_OR_ZERO(crtc_state);
13188 if (!ret) {
13189 if (!crtc_state->active)
13190 goto out;
13191
13192 crtc_state->mode_changed = true;
13193 ret = drm_atomic_commit(state);
13194 }
13195
13196 if (ret == -EDEADLK) {
13197 drm_atomic_state_clear(state);
13198 drm_modeset_backoff(state->acquire_ctx);
13199 goto retry;
13200 }
13201
13202 if (ret)
13203 out:
13204 drm_atomic_state_free(state);
13205 }
13206
13207 #undef for_each_intel_crtc_masked
13208
13209 static const struct drm_crtc_funcs intel_crtc_funcs = {
13210 .gamma_set = intel_crtc_gamma_set,
13211 .set_config = drm_atomic_helper_set_config,
13212 .destroy = intel_crtc_destroy,
13213 .page_flip = intel_crtc_page_flip,
13214 .atomic_duplicate_state = intel_crtc_duplicate_state,
13215 .atomic_destroy_state = intel_crtc_destroy_state,
13216 };
13217
13218 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13219 struct intel_shared_dpll *pll,
13220 struct intel_dpll_hw_state *hw_state)
13221 {
13222 uint32_t val;
13223
13224 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13225 return false;
13226
13227 val = I915_READ(PCH_DPLL(pll->id));
13228 hw_state->dpll = val;
13229 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13230 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13231
13232 return val & DPLL_VCO_ENABLE;
13233 }
13234
13235 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13236 struct intel_shared_dpll *pll)
13237 {
13238 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13239 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13240 }
13241
13242 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13243 struct intel_shared_dpll *pll)
13244 {
13245 /* PCH refclock must be enabled first */
13246 ibx_assert_pch_refclk_enabled(dev_priv);
13247
13248 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13249
13250 /* Wait for the clocks to stabilize. */
13251 POSTING_READ(PCH_DPLL(pll->id));
13252 udelay(150);
13253
13254 /* The pixel multiplier can only be updated once the
13255 * DPLL is enabled and the clocks are stable.
13256 *
13257 * So write it again.
13258 */
13259 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13260 POSTING_READ(PCH_DPLL(pll->id));
13261 udelay(200);
13262 }
13263
13264 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13265 struct intel_shared_dpll *pll)
13266 {
13267 struct drm_device *dev = dev_priv->dev;
13268 struct intel_crtc *crtc;
13269
13270 /* Make sure no transcoder isn't still depending on us. */
13271 for_each_intel_crtc(dev, crtc) {
13272 if (intel_crtc_to_shared_dpll(crtc) == pll)
13273 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13274 }
13275
13276 I915_WRITE(PCH_DPLL(pll->id), 0);
13277 POSTING_READ(PCH_DPLL(pll->id));
13278 udelay(200);
13279 }
13280
13281 static char *ibx_pch_dpll_names[] = {
13282 "PCH DPLL A",
13283 "PCH DPLL B",
13284 };
13285
13286 static void ibx_pch_dpll_init(struct drm_device *dev)
13287 {
13288 struct drm_i915_private *dev_priv = dev->dev_private;
13289 int i;
13290
13291 dev_priv->num_shared_dpll = 2;
13292
13293 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13294 dev_priv->shared_dplls[i].id = i;
13295 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13296 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13297 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13298 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13299 dev_priv->shared_dplls[i].get_hw_state =
13300 ibx_pch_dpll_get_hw_state;
13301 }
13302 }
13303
13304 static void intel_shared_dpll_init(struct drm_device *dev)
13305 {
13306 struct drm_i915_private *dev_priv = dev->dev_private;
13307
13308 if (HAS_DDI(dev))
13309 intel_ddi_pll_init(dev);
13310 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13311 ibx_pch_dpll_init(dev);
13312 else
13313 dev_priv->num_shared_dpll = 0;
13314
13315 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13316 }
13317
13318 /**
13319 * intel_prepare_plane_fb - Prepare fb for usage on plane
13320 * @plane: drm plane to prepare for
13321 * @fb: framebuffer to prepare for presentation
13322 *
13323 * Prepares a framebuffer for usage on a display plane. Generally this
13324 * involves pinning the underlying object and updating the frontbuffer tracking
13325 * bits. Some older platforms need special physical address handling for
13326 * cursor planes.
13327 *
13328 * Returns 0 on success, negative error code on failure.
13329 */
13330 int
13331 intel_prepare_plane_fb(struct drm_plane *plane,
13332 const struct drm_plane_state *new_state)
13333 {
13334 struct drm_device *dev = plane->dev;
13335 struct drm_framebuffer *fb = new_state->fb;
13336 struct intel_plane *intel_plane = to_intel_plane(plane);
13337 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13338 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13339 int ret = 0;
13340
13341 if (!obj && !old_obj)
13342 return 0;
13343
13344 mutex_lock(&dev->struct_mutex);
13345
13346 if (!obj) {
13347 ret = 0;
13348 } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13349 INTEL_INFO(dev)->cursor_needs_physical) {
13350 int align = IS_I830(dev) ? 16 * 1024 : 256;
13351 ret = i915_gem_object_attach_phys(obj, align);
13352 if (ret)
13353 DRM_DEBUG_KMS("failed to attach phys object\n");
13354 } else {
13355 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
13356 }
13357
13358 if (ret == 0)
13359 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13360
13361 mutex_unlock(&dev->struct_mutex);
13362
13363 return ret;
13364 }
13365
13366 /**
13367 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13368 * @plane: drm plane to clean up for
13369 * @fb: old framebuffer that was on plane
13370 *
13371 * Cleans up a framebuffer that has just been removed from a plane.
13372 */
13373 void
13374 intel_cleanup_plane_fb(struct drm_plane *plane,
13375 const struct drm_plane_state *old_state)
13376 {
13377 struct drm_device *dev = plane->dev;
13378 struct intel_plane *intel_plane = to_intel_plane(plane);
13379 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13380 struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
13381
13382 if (!obj && !old_obj)
13383 return;
13384
13385 mutex_lock(&dev->struct_mutex);
13386 if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13387 !INTEL_INFO(dev)->cursor_needs_physical))
13388 intel_unpin_fb_obj(old_state->fb, old_state);
13389
13390 /* prepare_fb aborted? */
13391 if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13392 (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13393 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13394 mutex_unlock(&dev->struct_mutex);
13395 }
13396
13397 int
13398 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13399 {
13400 int max_scale;
13401 struct drm_device *dev;
13402 struct drm_i915_private *dev_priv;
13403 int crtc_clock, cdclk;
13404
13405 if (!intel_crtc || !crtc_state)
13406 return DRM_PLANE_HELPER_NO_SCALING;
13407
13408 dev = intel_crtc->base.dev;
13409 dev_priv = dev->dev_private;
13410 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13411 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13412
13413 if (!crtc_clock || !cdclk)
13414 return DRM_PLANE_HELPER_NO_SCALING;
13415
13416 /*
13417 * skl max scale is lower of:
13418 * close to 3 but not 3, -1 is for that purpose
13419 * or
13420 * cdclk/crtc_clock
13421 */
13422 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13423
13424 return max_scale;
13425 }
13426
13427 static int
13428 intel_check_primary_plane(struct drm_plane *plane,
13429 struct intel_crtc_state *crtc_state,
13430 struct intel_plane_state *state)
13431 {
13432 struct drm_crtc *crtc = state->base.crtc;
13433 struct drm_framebuffer *fb = state->base.fb;
13434 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13435 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13436 bool can_position = false;
13437
13438 /* use scaler when colorkey is not required */
13439 if (INTEL_INFO(plane->dev)->gen >= 9 &&
13440 state->ckey.flags == I915_SET_COLORKEY_NONE) {
13441 min_scale = 1;
13442 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13443 can_position = true;
13444 }
13445
13446 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13447 &state->dst, &state->clip,
13448 min_scale, max_scale,
13449 can_position, true,
13450 &state->visible);
13451 }
13452
13453 static void
13454 intel_commit_primary_plane(struct drm_plane *plane,
13455 struct intel_plane_state *state)
13456 {
13457 struct drm_crtc *crtc = state->base.crtc;
13458 struct drm_framebuffer *fb = state->base.fb;
13459 struct drm_device *dev = plane->dev;
13460 struct drm_i915_private *dev_priv = dev->dev_private;
13461 struct intel_crtc *intel_crtc;
13462 struct drm_rect *src = &state->src;
13463
13464 crtc = crtc ? crtc : plane->crtc;
13465 intel_crtc = to_intel_crtc(crtc);
13466
13467 plane->fb = fb;
13468 crtc->x = src->x1 >> 16;
13469 crtc->y = src->y1 >> 16;
13470
13471 if (!crtc->state->active)
13472 return;
13473
13474 dev_priv->display.update_primary_plane(crtc, fb,
13475 state->src.x1 >> 16,
13476 state->src.y1 >> 16);
13477 }
13478
13479 static void
13480 intel_disable_primary_plane(struct drm_plane *plane,
13481 struct drm_crtc *crtc)
13482 {
13483 struct drm_device *dev = plane->dev;
13484 struct drm_i915_private *dev_priv = dev->dev_private;
13485
13486 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13487 }
13488
13489 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13490 struct drm_crtc_state *old_crtc_state)
13491 {
13492 struct drm_device *dev = crtc->dev;
13493 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13494 struct intel_crtc_state *old_intel_state =
13495 to_intel_crtc_state(old_crtc_state);
13496 bool modeset = needs_modeset(crtc->state);
13497
13498 if (intel_crtc->atomic.update_wm_pre)
13499 intel_update_watermarks(crtc);
13500
13501 /* Perform vblank evasion around commit operation */
13502 if (crtc->state->active)
13503 intel_pipe_update_start(intel_crtc);
13504
13505 if (modeset)
13506 return;
13507
13508 if (to_intel_crtc_state(crtc->state)->update_pipe)
13509 intel_update_pipe_config(intel_crtc, old_intel_state);
13510 else if (INTEL_INFO(dev)->gen >= 9)
13511 skl_detach_scalers(intel_crtc);
13512 }
13513
13514 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13515 struct drm_crtc_state *old_crtc_state)
13516 {
13517 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13518
13519 if (crtc->state->active)
13520 intel_pipe_update_end(intel_crtc);
13521 }
13522
13523 /**
13524 * intel_plane_destroy - destroy a plane
13525 * @plane: plane to destroy
13526 *
13527 * Common destruction function for all types of planes (primary, cursor,
13528 * sprite).
13529 */
13530 void intel_plane_destroy(struct drm_plane *plane)
13531 {
13532 struct intel_plane *intel_plane = to_intel_plane(plane);
13533 drm_plane_cleanup(plane);
13534 kfree(intel_plane);
13535 }
13536
13537 const struct drm_plane_funcs intel_plane_funcs = {
13538 .update_plane = drm_atomic_helper_update_plane,
13539 .disable_plane = drm_atomic_helper_disable_plane,
13540 .destroy = intel_plane_destroy,
13541 .set_property = drm_atomic_helper_plane_set_property,
13542 .atomic_get_property = intel_plane_atomic_get_property,
13543 .atomic_set_property = intel_plane_atomic_set_property,
13544 .atomic_duplicate_state = intel_plane_duplicate_state,
13545 .atomic_destroy_state = intel_plane_destroy_state,
13546
13547 };
13548
13549 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13550 int pipe)
13551 {
13552 struct intel_plane *primary;
13553 struct intel_plane_state *state;
13554 const uint32_t *intel_primary_formats;
13555 unsigned int num_formats;
13556
13557 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13558 if (primary == NULL)
13559 return NULL;
13560
13561 state = intel_create_plane_state(&primary->base);
13562 if (!state) {
13563 kfree(primary);
13564 return NULL;
13565 }
13566 primary->base.state = &state->base;
13567
13568 primary->can_scale = false;
13569 primary->max_downscale = 1;
13570 if (INTEL_INFO(dev)->gen >= 9) {
13571 primary->can_scale = true;
13572 state->scaler_id = -1;
13573 }
13574 primary->pipe = pipe;
13575 primary->plane = pipe;
13576 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13577 primary->check_plane = intel_check_primary_plane;
13578 primary->commit_plane = intel_commit_primary_plane;
13579 primary->disable_plane = intel_disable_primary_plane;
13580 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13581 primary->plane = !pipe;
13582
13583 if (INTEL_INFO(dev)->gen >= 9) {
13584 intel_primary_formats = skl_primary_formats;
13585 num_formats = ARRAY_SIZE(skl_primary_formats);
13586 } else if (INTEL_INFO(dev)->gen >= 4) {
13587 intel_primary_formats = i965_primary_formats;
13588 num_formats = ARRAY_SIZE(i965_primary_formats);
13589 } else {
13590 intel_primary_formats = i8xx_primary_formats;
13591 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13592 }
13593
13594 drm_universal_plane_init(dev, &primary->base, 0,
13595 &intel_plane_funcs,
13596 intel_primary_formats, num_formats,
13597 DRM_PLANE_TYPE_PRIMARY);
13598
13599 if (INTEL_INFO(dev)->gen >= 4)
13600 intel_create_rotation_property(dev, primary);
13601
13602 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13603
13604 return &primary->base;
13605 }
13606
13607 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13608 {
13609 if (!dev->mode_config.rotation_property) {
13610 unsigned long flags = BIT(DRM_ROTATE_0) |
13611 BIT(DRM_ROTATE_180);
13612
13613 if (INTEL_INFO(dev)->gen >= 9)
13614 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13615
13616 dev->mode_config.rotation_property =
13617 drm_mode_create_rotation_property(dev, flags);
13618 }
13619 if (dev->mode_config.rotation_property)
13620 drm_object_attach_property(&plane->base.base,
13621 dev->mode_config.rotation_property,
13622 plane->base.state->rotation);
13623 }
13624
13625 static int
13626 intel_check_cursor_plane(struct drm_plane *plane,
13627 struct intel_crtc_state *crtc_state,
13628 struct intel_plane_state *state)
13629 {
13630 struct drm_crtc *crtc = crtc_state->base.crtc;
13631 struct drm_framebuffer *fb = state->base.fb;
13632 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13633 unsigned stride;
13634 int ret;
13635
13636 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13637 &state->dst, &state->clip,
13638 DRM_PLANE_HELPER_NO_SCALING,
13639 DRM_PLANE_HELPER_NO_SCALING,
13640 true, true, &state->visible);
13641 if (ret)
13642 return ret;
13643
13644 /* if we want to turn off the cursor ignore width and height */
13645 if (!obj)
13646 return 0;
13647
13648 /* Check for which cursor types we support */
13649 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
13650 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13651 state->base.crtc_w, state->base.crtc_h);
13652 return -EINVAL;
13653 }
13654
13655 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13656 if (obj->base.size < stride * state->base.crtc_h) {
13657 DRM_DEBUG_KMS("buffer is too small\n");
13658 return -ENOMEM;
13659 }
13660
13661 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13662 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13663 return -EINVAL;
13664 }
13665
13666 return 0;
13667 }
13668
13669 static void
13670 intel_disable_cursor_plane(struct drm_plane *plane,
13671 struct drm_crtc *crtc)
13672 {
13673 intel_crtc_update_cursor(crtc, false);
13674 }
13675
13676 static void
13677 intel_commit_cursor_plane(struct drm_plane *plane,
13678 struct intel_plane_state *state)
13679 {
13680 struct drm_crtc *crtc = state->base.crtc;
13681 struct drm_device *dev = plane->dev;
13682 struct intel_crtc *intel_crtc;
13683 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13684 uint32_t addr;
13685
13686 crtc = crtc ? crtc : plane->crtc;
13687 intel_crtc = to_intel_crtc(crtc);
13688
13689 if (intel_crtc->cursor_bo == obj)
13690 goto update;
13691
13692 if (!obj)
13693 addr = 0;
13694 else if (!INTEL_INFO(dev)->cursor_needs_physical)
13695 addr = i915_gem_obj_ggtt_offset(obj);
13696 else
13697 addr = obj->phys_handle->busaddr;
13698
13699 intel_crtc->cursor_addr = addr;
13700 intel_crtc->cursor_bo = obj;
13701
13702 update:
13703 if (crtc->state->active)
13704 intel_crtc_update_cursor(crtc, state->visible);
13705 }
13706
13707 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13708 int pipe)
13709 {
13710 struct intel_plane *cursor;
13711 struct intel_plane_state *state;
13712
13713 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13714 if (cursor == NULL)
13715 return NULL;
13716
13717 state = intel_create_plane_state(&cursor->base);
13718 if (!state) {
13719 kfree(cursor);
13720 return NULL;
13721 }
13722 cursor->base.state = &state->base;
13723
13724 cursor->can_scale = false;
13725 cursor->max_downscale = 1;
13726 cursor->pipe = pipe;
13727 cursor->plane = pipe;
13728 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13729 cursor->check_plane = intel_check_cursor_plane;
13730 cursor->commit_plane = intel_commit_cursor_plane;
13731 cursor->disable_plane = intel_disable_cursor_plane;
13732
13733 drm_universal_plane_init(dev, &cursor->base, 0,
13734 &intel_plane_funcs,
13735 intel_cursor_formats,
13736 ARRAY_SIZE(intel_cursor_formats),
13737 DRM_PLANE_TYPE_CURSOR);
13738
13739 if (INTEL_INFO(dev)->gen >= 4) {
13740 if (!dev->mode_config.rotation_property)
13741 dev->mode_config.rotation_property =
13742 drm_mode_create_rotation_property(dev,
13743 BIT(DRM_ROTATE_0) |
13744 BIT(DRM_ROTATE_180));
13745 if (dev->mode_config.rotation_property)
13746 drm_object_attach_property(&cursor->base.base,
13747 dev->mode_config.rotation_property,
13748 state->base.rotation);
13749 }
13750
13751 if (INTEL_INFO(dev)->gen >=9)
13752 state->scaler_id = -1;
13753
13754 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13755
13756 return &cursor->base;
13757 }
13758
13759 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13760 struct intel_crtc_state *crtc_state)
13761 {
13762 int i;
13763 struct intel_scaler *intel_scaler;
13764 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13765
13766 for (i = 0; i < intel_crtc->num_scalers; i++) {
13767 intel_scaler = &scaler_state->scalers[i];
13768 intel_scaler->in_use = 0;
13769 intel_scaler->mode = PS_SCALER_MODE_DYN;
13770 }
13771
13772 scaler_state->scaler_id = -1;
13773 }
13774
13775 static void intel_crtc_init(struct drm_device *dev, int pipe)
13776 {
13777 struct drm_i915_private *dev_priv = dev->dev_private;
13778 struct intel_crtc *intel_crtc;
13779 struct intel_crtc_state *crtc_state = NULL;
13780 struct drm_plane *primary = NULL;
13781 struct drm_plane *cursor = NULL;
13782 int i, ret;
13783
13784 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13785 if (intel_crtc == NULL)
13786 return;
13787
13788 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13789 if (!crtc_state)
13790 goto fail;
13791 intel_crtc->config = crtc_state;
13792 intel_crtc->base.state = &crtc_state->base;
13793 crtc_state->base.crtc = &intel_crtc->base;
13794
13795 /* initialize shared scalers */
13796 if (INTEL_INFO(dev)->gen >= 9) {
13797 if (pipe == PIPE_C)
13798 intel_crtc->num_scalers = 1;
13799 else
13800 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13801
13802 skl_init_scalers(dev, intel_crtc, crtc_state);
13803 }
13804
13805 primary = intel_primary_plane_create(dev, pipe);
13806 if (!primary)
13807 goto fail;
13808
13809 cursor = intel_cursor_plane_create(dev, pipe);
13810 if (!cursor)
13811 goto fail;
13812
13813 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
13814 cursor, &intel_crtc_funcs);
13815 if (ret)
13816 goto fail;
13817
13818 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
13819 for (i = 0; i < 256; i++) {
13820 intel_crtc->lut_r[i] = i;
13821 intel_crtc->lut_g[i] = i;
13822 intel_crtc->lut_b[i] = i;
13823 }
13824
13825 /*
13826 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13827 * is hooked to pipe B. Hence we want plane A feeding pipe B.
13828 */
13829 intel_crtc->pipe = pipe;
13830 intel_crtc->plane = pipe;
13831 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
13832 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13833 intel_crtc->plane = !pipe;
13834 }
13835
13836 intel_crtc->cursor_base = ~0;
13837 intel_crtc->cursor_cntl = ~0;
13838 intel_crtc->cursor_size = ~0;
13839
13840 intel_crtc->wm.cxsr_allowed = true;
13841
13842 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13843 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13844 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13845 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13846
13847 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13848
13849 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13850 return;
13851
13852 fail:
13853 if (primary)
13854 drm_plane_cleanup(primary);
13855 if (cursor)
13856 drm_plane_cleanup(cursor);
13857 kfree(crtc_state);
13858 kfree(intel_crtc);
13859 }
13860
13861 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13862 {
13863 struct drm_encoder *encoder = connector->base.encoder;
13864 struct drm_device *dev = connector->base.dev;
13865
13866 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13867
13868 if (!encoder || WARN_ON(!encoder->crtc))
13869 return INVALID_PIPE;
13870
13871 return to_intel_crtc(encoder->crtc)->pipe;
13872 }
13873
13874 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13875 struct drm_file *file)
13876 {
13877 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13878 struct drm_crtc *drmmode_crtc;
13879 struct intel_crtc *crtc;
13880
13881 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13882
13883 if (!drmmode_crtc) {
13884 DRM_ERROR("no such CRTC id\n");
13885 return -ENOENT;
13886 }
13887
13888 crtc = to_intel_crtc(drmmode_crtc);
13889 pipe_from_crtc_id->pipe = crtc->pipe;
13890
13891 return 0;
13892 }
13893
13894 static int intel_encoder_clones(struct intel_encoder *encoder)
13895 {
13896 struct drm_device *dev = encoder->base.dev;
13897 struct intel_encoder *source_encoder;
13898 int index_mask = 0;
13899 int entry = 0;
13900
13901 for_each_intel_encoder(dev, source_encoder) {
13902 if (encoders_cloneable(encoder, source_encoder))
13903 index_mask |= (1 << entry);
13904
13905 entry++;
13906 }
13907
13908 return index_mask;
13909 }
13910
13911 static bool has_edp_a(struct drm_device *dev)
13912 {
13913 struct drm_i915_private *dev_priv = dev->dev_private;
13914
13915 if (!IS_MOBILE(dev))
13916 return false;
13917
13918 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13919 return false;
13920
13921 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13922 return false;
13923
13924 return true;
13925 }
13926
13927 static bool intel_crt_present(struct drm_device *dev)
13928 {
13929 struct drm_i915_private *dev_priv = dev->dev_private;
13930
13931 if (INTEL_INFO(dev)->gen >= 9)
13932 return false;
13933
13934 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
13935 return false;
13936
13937 if (IS_CHERRYVIEW(dev))
13938 return false;
13939
13940 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13941 return false;
13942
13943 return true;
13944 }
13945
13946 static void intel_setup_outputs(struct drm_device *dev)
13947 {
13948 struct drm_i915_private *dev_priv = dev->dev_private;
13949 struct intel_encoder *encoder;
13950 bool dpd_is_edp = false;
13951
13952 intel_lvds_init(dev);
13953
13954 if (intel_crt_present(dev))
13955 intel_crt_init(dev);
13956
13957 if (IS_BROXTON(dev)) {
13958 /*
13959 * FIXME: Broxton doesn't support port detection via the
13960 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13961 * detect the ports.
13962 */
13963 intel_ddi_init(dev, PORT_A);
13964 intel_ddi_init(dev, PORT_B);
13965 intel_ddi_init(dev, PORT_C);
13966 } else if (HAS_DDI(dev)) {
13967 int found;
13968
13969 /*
13970 * Haswell uses DDI functions to detect digital outputs.
13971 * On SKL pre-D0 the strap isn't connected, so we assume
13972 * it's there.
13973 */
13974 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
13975 /* WaIgnoreDDIAStrap: skl */
13976 if (found || IS_SKYLAKE(dev))
13977 intel_ddi_init(dev, PORT_A);
13978
13979 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13980 * register */
13981 found = I915_READ(SFUSE_STRAP);
13982
13983 if (found & SFUSE_STRAP_DDIB_DETECTED)
13984 intel_ddi_init(dev, PORT_B);
13985 if (found & SFUSE_STRAP_DDIC_DETECTED)
13986 intel_ddi_init(dev, PORT_C);
13987 if (found & SFUSE_STRAP_DDID_DETECTED)
13988 intel_ddi_init(dev, PORT_D);
13989 /*
13990 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
13991 */
13992 if (IS_SKYLAKE(dev) &&
13993 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
13994 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
13995 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
13996 intel_ddi_init(dev, PORT_E);
13997
13998 } else if (HAS_PCH_SPLIT(dev)) {
13999 int found;
14000 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14001
14002 if (has_edp_a(dev))
14003 intel_dp_init(dev, DP_A, PORT_A);
14004
14005 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14006 /* PCH SDVOB multiplex with HDMIB */
14007 found = intel_sdvo_init(dev, PCH_SDVOB, true);
14008 if (!found)
14009 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14010 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14011 intel_dp_init(dev, PCH_DP_B, PORT_B);
14012 }
14013
14014 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14015 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14016
14017 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14018 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14019
14020 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14021 intel_dp_init(dev, PCH_DP_C, PORT_C);
14022
14023 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14024 intel_dp_init(dev, PCH_DP_D, PORT_D);
14025 } else if (IS_VALLEYVIEW(dev)) {
14026 /*
14027 * The DP_DETECTED bit is the latched state of the DDC
14028 * SDA pin at boot. However since eDP doesn't require DDC
14029 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14030 * eDP ports may have been muxed to an alternate function.
14031 * Thus we can't rely on the DP_DETECTED bit alone to detect
14032 * eDP ports. Consult the VBT as well as DP_DETECTED to
14033 * detect eDP ports.
14034 */
14035 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14036 !intel_dp_is_edp(dev, PORT_B))
14037 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14038 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14039 intel_dp_is_edp(dev, PORT_B))
14040 intel_dp_init(dev, VLV_DP_B, PORT_B);
14041
14042 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14043 !intel_dp_is_edp(dev, PORT_C))
14044 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14045 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14046 intel_dp_is_edp(dev, PORT_C))
14047 intel_dp_init(dev, VLV_DP_C, PORT_C);
14048
14049 if (IS_CHERRYVIEW(dev)) {
14050 /* eDP not supported on port D, so don't check VBT */
14051 if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14052 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14053 if (I915_READ(CHV_DP_D) & DP_DETECTED)
14054 intel_dp_init(dev, CHV_DP_D, PORT_D);
14055 }
14056
14057 intel_dsi_init(dev);
14058 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14059 bool found = false;
14060
14061 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14062 DRM_DEBUG_KMS("probing SDVOB\n");
14063 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14064 if (!found && IS_G4X(dev)) {
14065 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14066 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14067 }
14068
14069 if (!found && IS_G4X(dev))
14070 intel_dp_init(dev, DP_B, PORT_B);
14071 }
14072
14073 /* Before G4X SDVOC doesn't have its own detect register */
14074
14075 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14076 DRM_DEBUG_KMS("probing SDVOC\n");
14077 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14078 }
14079
14080 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14081
14082 if (IS_G4X(dev)) {
14083 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14084 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14085 }
14086 if (IS_G4X(dev))
14087 intel_dp_init(dev, DP_C, PORT_C);
14088 }
14089
14090 if (IS_G4X(dev) &&
14091 (I915_READ(DP_D) & DP_DETECTED))
14092 intel_dp_init(dev, DP_D, PORT_D);
14093 } else if (IS_GEN2(dev))
14094 intel_dvo_init(dev);
14095
14096 if (SUPPORTS_TV(dev))
14097 intel_tv_init(dev);
14098
14099 intel_psr_init(dev);
14100
14101 for_each_intel_encoder(dev, encoder) {
14102 encoder->base.possible_crtcs = encoder->crtc_mask;
14103 encoder->base.possible_clones =
14104 intel_encoder_clones(encoder);
14105 }
14106
14107 intel_init_pch_refclk(dev);
14108
14109 drm_helper_move_panel_connectors_to_head(dev);
14110 }
14111
14112 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14113 {
14114 struct drm_device *dev = fb->dev;
14115 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14116
14117 drm_framebuffer_cleanup(fb);
14118 mutex_lock(&dev->struct_mutex);
14119 WARN_ON(!intel_fb->obj->framebuffer_references--);
14120 drm_gem_object_unreference(&intel_fb->obj->base);
14121 mutex_unlock(&dev->struct_mutex);
14122 kfree(intel_fb);
14123 }
14124
14125 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14126 struct drm_file *file,
14127 unsigned int *handle)
14128 {
14129 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14130 struct drm_i915_gem_object *obj = intel_fb->obj;
14131
14132 return drm_gem_handle_create(file, &obj->base, handle);
14133 }
14134
14135 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14136 struct drm_file *file,
14137 unsigned flags, unsigned color,
14138 struct drm_clip_rect *clips,
14139 unsigned num_clips)
14140 {
14141 struct drm_device *dev = fb->dev;
14142 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14143 struct drm_i915_gem_object *obj = intel_fb->obj;
14144
14145 mutex_lock(&dev->struct_mutex);
14146 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14147 mutex_unlock(&dev->struct_mutex);
14148
14149 return 0;
14150 }
14151
14152 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14153 .destroy = intel_user_framebuffer_destroy,
14154 .create_handle = intel_user_framebuffer_create_handle,
14155 .dirty = intel_user_framebuffer_dirty,
14156 };
14157
14158 static
14159 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14160 uint32_t pixel_format)
14161 {
14162 u32 gen = INTEL_INFO(dev)->gen;
14163
14164 if (gen >= 9) {
14165 /* "The stride in bytes must not exceed the of the size of 8K
14166 * pixels and 32K bytes."
14167 */
14168 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14169 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14170 return 32*1024;
14171 } else if (gen >= 4) {
14172 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14173 return 16*1024;
14174 else
14175 return 32*1024;
14176 } else if (gen >= 3) {
14177 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14178 return 8*1024;
14179 else
14180 return 16*1024;
14181 } else {
14182 /* XXX DSPC is limited to 4k tiled */
14183 return 8*1024;
14184 }
14185 }
14186
14187 static int intel_framebuffer_init(struct drm_device *dev,
14188 struct intel_framebuffer *intel_fb,
14189 struct drm_mode_fb_cmd2 *mode_cmd,
14190 struct drm_i915_gem_object *obj)
14191 {
14192 unsigned int aligned_height;
14193 int ret;
14194 u32 pitch_limit, stride_alignment;
14195
14196 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14197
14198 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14199 /* Enforce that fb modifier and tiling mode match, but only for
14200 * X-tiled. This is needed for FBC. */
14201 if (!!(obj->tiling_mode == I915_TILING_X) !=
14202 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14203 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14204 return -EINVAL;
14205 }
14206 } else {
14207 if (obj->tiling_mode == I915_TILING_X)
14208 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14209 else if (obj->tiling_mode == I915_TILING_Y) {
14210 DRM_DEBUG("No Y tiling for legacy addfb\n");
14211 return -EINVAL;
14212 }
14213 }
14214
14215 /* Passed in modifier sanity checking. */
14216 switch (mode_cmd->modifier[0]) {
14217 case I915_FORMAT_MOD_Y_TILED:
14218 case I915_FORMAT_MOD_Yf_TILED:
14219 if (INTEL_INFO(dev)->gen < 9) {
14220 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14221 mode_cmd->modifier[0]);
14222 return -EINVAL;
14223 }
14224 case DRM_FORMAT_MOD_NONE:
14225 case I915_FORMAT_MOD_X_TILED:
14226 break;
14227 default:
14228 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14229 mode_cmd->modifier[0]);
14230 return -EINVAL;
14231 }
14232
14233 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14234 mode_cmd->pixel_format);
14235 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14236 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14237 mode_cmd->pitches[0], stride_alignment);
14238 return -EINVAL;
14239 }
14240
14241 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14242 mode_cmd->pixel_format);
14243 if (mode_cmd->pitches[0] > pitch_limit) {
14244 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14245 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14246 "tiled" : "linear",
14247 mode_cmd->pitches[0], pitch_limit);
14248 return -EINVAL;
14249 }
14250
14251 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14252 mode_cmd->pitches[0] != obj->stride) {
14253 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14254 mode_cmd->pitches[0], obj->stride);
14255 return -EINVAL;
14256 }
14257
14258 /* Reject formats not supported by any plane early. */
14259 switch (mode_cmd->pixel_format) {
14260 case DRM_FORMAT_C8:
14261 case DRM_FORMAT_RGB565:
14262 case DRM_FORMAT_XRGB8888:
14263 case DRM_FORMAT_ARGB8888:
14264 break;
14265 case DRM_FORMAT_XRGB1555:
14266 if (INTEL_INFO(dev)->gen > 3) {
14267 DRM_DEBUG("unsupported pixel format: %s\n",
14268 drm_get_format_name(mode_cmd->pixel_format));
14269 return -EINVAL;
14270 }
14271 break;
14272 case DRM_FORMAT_ABGR8888:
14273 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14274 DRM_DEBUG("unsupported pixel format: %s\n",
14275 drm_get_format_name(mode_cmd->pixel_format));
14276 return -EINVAL;
14277 }
14278 break;
14279 case DRM_FORMAT_XBGR8888:
14280 case DRM_FORMAT_XRGB2101010:
14281 case DRM_FORMAT_XBGR2101010:
14282 if (INTEL_INFO(dev)->gen < 4) {
14283 DRM_DEBUG("unsupported pixel format: %s\n",
14284 drm_get_format_name(mode_cmd->pixel_format));
14285 return -EINVAL;
14286 }
14287 break;
14288 case DRM_FORMAT_ABGR2101010:
14289 if (!IS_VALLEYVIEW(dev)) {
14290 DRM_DEBUG("unsupported pixel format: %s\n",
14291 drm_get_format_name(mode_cmd->pixel_format));
14292 return -EINVAL;
14293 }
14294 break;
14295 case DRM_FORMAT_YUYV:
14296 case DRM_FORMAT_UYVY:
14297 case DRM_FORMAT_YVYU:
14298 case DRM_FORMAT_VYUY:
14299 if (INTEL_INFO(dev)->gen < 5) {
14300 DRM_DEBUG("unsupported pixel format: %s\n",
14301 drm_get_format_name(mode_cmd->pixel_format));
14302 return -EINVAL;
14303 }
14304 break;
14305 default:
14306 DRM_DEBUG("unsupported pixel format: %s\n",
14307 drm_get_format_name(mode_cmd->pixel_format));
14308 return -EINVAL;
14309 }
14310
14311 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14312 if (mode_cmd->offsets[0] != 0)
14313 return -EINVAL;
14314
14315 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14316 mode_cmd->pixel_format,
14317 mode_cmd->modifier[0]);
14318 /* FIXME drm helper for size checks (especially planar formats)? */
14319 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14320 return -EINVAL;
14321
14322 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14323 intel_fb->obj = obj;
14324 intel_fb->obj->framebuffer_references++;
14325
14326 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14327 if (ret) {
14328 DRM_ERROR("framebuffer init failed %d\n", ret);
14329 return ret;
14330 }
14331
14332 return 0;
14333 }
14334
14335 static struct drm_framebuffer *
14336 intel_user_framebuffer_create(struct drm_device *dev,
14337 struct drm_file *filp,
14338 struct drm_mode_fb_cmd2 *mode_cmd)
14339 {
14340 struct drm_i915_gem_object *obj;
14341
14342 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14343 mode_cmd->handles[0]));
14344 if (&obj->base == NULL)
14345 return ERR_PTR(-ENOENT);
14346
14347 return intel_framebuffer_create(dev, mode_cmd, obj);
14348 }
14349
14350 #ifndef CONFIG_DRM_FBDEV_EMULATION
14351 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14352 {
14353 }
14354 #endif
14355
14356 static const struct drm_mode_config_funcs intel_mode_funcs = {
14357 .fb_create = intel_user_framebuffer_create,
14358 .output_poll_changed = intel_fbdev_output_poll_changed,
14359 .atomic_check = intel_atomic_check,
14360 .atomic_commit = intel_atomic_commit,
14361 .atomic_state_alloc = intel_atomic_state_alloc,
14362 .atomic_state_clear = intel_atomic_state_clear,
14363 };
14364
14365 /* Set up chip specific display functions */
14366 static void intel_init_display(struct drm_device *dev)
14367 {
14368 struct drm_i915_private *dev_priv = dev->dev_private;
14369
14370 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14371 dev_priv->display.find_dpll = g4x_find_best_dpll;
14372 else if (IS_CHERRYVIEW(dev))
14373 dev_priv->display.find_dpll = chv_find_best_dpll;
14374 else if (IS_VALLEYVIEW(dev))
14375 dev_priv->display.find_dpll = vlv_find_best_dpll;
14376 else if (IS_PINEVIEW(dev))
14377 dev_priv->display.find_dpll = pnv_find_best_dpll;
14378 else
14379 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14380
14381 if (INTEL_INFO(dev)->gen >= 9) {
14382 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14383 dev_priv->display.get_initial_plane_config =
14384 skylake_get_initial_plane_config;
14385 dev_priv->display.crtc_compute_clock =
14386 haswell_crtc_compute_clock;
14387 dev_priv->display.crtc_enable = haswell_crtc_enable;
14388 dev_priv->display.crtc_disable = haswell_crtc_disable;
14389 dev_priv->display.update_primary_plane =
14390 skylake_update_primary_plane;
14391 } else if (HAS_DDI(dev)) {
14392 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14393 dev_priv->display.get_initial_plane_config =
14394 ironlake_get_initial_plane_config;
14395 dev_priv->display.crtc_compute_clock =
14396 haswell_crtc_compute_clock;
14397 dev_priv->display.crtc_enable = haswell_crtc_enable;
14398 dev_priv->display.crtc_disable = haswell_crtc_disable;
14399 dev_priv->display.update_primary_plane =
14400 ironlake_update_primary_plane;
14401 } else if (HAS_PCH_SPLIT(dev)) {
14402 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14403 dev_priv->display.get_initial_plane_config =
14404 ironlake_get_initial_plane_config;
14405 dev_priv->display.crtc_compute_clock =
14406 ironlake_crtc_compute_clock;
14407 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14408 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14409 dev_priv->display.update_primary_plane =
14410 ironlake_update_primary_plane;
14411 } else if (IS_VALLEYVIEW(dev)) {
14412 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14413 dev_priv->display.get_initial_plane_config =
14414 i9xx_get_initial_plane_config;
14415 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14416 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14417 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14418 dev_priv->display.update_primary_plane =
14419 i9xx_update_primary_plane;
14420 } else {
14421 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14422 dev_priv->display.get_initial_plane_config =
14423 i9xx_get_initial_plane_config;
14424 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14425 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14426 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14427 dev_priv->display.update_primary_plane =
14428 i9xx_update_primary_plane;
14429 }
14430
14431 /* Returns the core display clock speed */
14432 if (IS_SKYLAKE(dev))
14433 dev_priv->display.get_display_clock_speed =
14434 skylake_get_display_clock_speed;
14435 else if (IS_BROXTON(dev))
14436 dev_priv->display.get_display_clock_speed =
14437 broxton_get_display_clock_speed;
14438 else if (IS_BROADWELL(dev))
14439 dev_priv->display.get_display_clock_speed =
14440 broadwell_get_display_clock_speed;
14441 else if (IS_HASWELL(dev))
14442 dev_priv->display.get_display_clock_speed =
14443 haswell_get_display_clock_speed;
14444 else if (IS_VALLEYVIEW(dev))
14445 dev_priv->display.get_display_clock_speed =
14446 valleyview_get_display_clock_speed;
14447 else if (IS_GEN5(dev))
14448 dev_priv->display.get_display_clock_speed =
14449 ilk_get_display_clock_speed;
14450 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14451 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14452 dev_priv->display.get_display_clock_speed =
14453 i945_get_display_clock_speed;
14454 else if (IS_GM45(dev))
14455 dev_priv->display.get_display_clock_speed =
14456 gm45_get_display_clock_speed;
14457 else if (IS_CRESTLINE(dev))
14458 dev_priv->display.get_display_clock_speed =
14459 i965gm_get_display_clock_speed;
14460 else if (IS_PINEVIEW(dev))
14461 dev_priv->display.get_display_clock_speed =
14462 pnv_get_display_clock_speed;
14463 else if (IS_G33(dev) || IS_G4X(dev))
14464 dev_priv->display.get_display_clock_speed =
14465 g33_get_display_clock_speed;
14466 else if (IS_I915G(dev))
14467 dev_priv->display.get_display_clock_speed =
14468 i915_get_display_clock_speed;
14469 else if (IS_I945GM(dev) || IS_845G(dev))
14470 dev_priv->display.get_display_clock_speed =
14471 i9xx_misc_get_display_clock_speed;
14472 else if (IS_PINEVIEW(dev))
14473 dev_priv->display.get_display_clock_speed =
14474 pnv_get_display_clock_speed;
14475 else if (IS_I915GM(dev))
14476 dev_priv->display.get_display_clock_speed =
14477 i915gm_get_display_clock_speed;
14478 else if (IS_I865G(dev))
14479 dev_priv->display.get_display_clock_speed =
14480 i865_get_display_clock_speed;
14481 else if (IS_I85X(dev))
14482 dev_priv->display.get_display_clock_speed =
14483 i85x_get_display_clock_speed;
14484 else { /* 830 */
14485 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14486 dev_priv->display.get_display_clock_speed =
14487 i830_get_display_clock_speed;
14488 }
14489
14490 if (IS_GEN5(dev)) {
14491 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14492 } else if (IS_GEN6(dev)) {
14493 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14494 } else if (IS_IVYBRIDGE(dev)) {
14495 /* FIXME: detect B0+ stepping and use auto training */
14496 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14497 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14498 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14499 if (IS_BROADWELL(dev)) {
14500 dev_priv->display.modeset_commit_cdclk =
14501 broadwell_modeset_commit_cdclk;
14502 dev_priv->display.modeset_calc_cdclk =
14503 broadwell_modeset_calc_cdclk;
14504 }
14505 } else if (IS_VALLEYVIEW(dev)) {
14506 dev_priv->display.modeset_commit_cdclk =
14507 valleyview_modeset_commit_cdclk;
14508 dev_priv->display.modeset_calc_cdclk =
14509 valleyview_modeset_calc_cdclk;
14510 } else if (IS_BROXTON(dev)) {
14511 dev_priv->display.modeset_commit_cdclk =
14512 broxton_modeset_commit_cdclk;
14513 dev_priv->display.modeset_calc_cdclk =
14514 broxton_modeset_calc_cdclk;
14515 }
14516
14517 switch (INTEL_INFO(dev)->gen) {
14518 case 2:
14519 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14520 break;
14521
14522 case 3:
14523 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14524 break;
14525
14526 case 4:
14527 case 5:
14528 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14529 break;
14530
14531 case 6:
14532 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14533 break;
14534 case 7:
14535 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14536 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14537 break;
14538 case 9:
14539 /* Drop through - unsupported since execlist only. */
14540 default:
14541 /* Default just returns -ENODEV to indicate unsupported */
14542 dev_priv->display.queue_flip = intel_default_queue_flip;
14543 }
14544
14545 mutex_init(&dev_priv->pps_mutex);
14546 }
14547
14548 /*
14549 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14550 * resume, or other times. This quirk makes sure that's the case for
14551 * affected systems.
14552 */
14553 static void quirk_pipea_force(struct drm_device *dev)
14554 {
14555 struct drm_i915_private *dev_priv = dev->dev_private;
14556
14557 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14558 DRM_INFO("applying pipe a force quirk\n");
14559 }
14560
14561 static void quirk_pipeb_force(struct drm_device *dev)
14562 {
14563 struct drm_i915_private *dev_priv = dev->dev_private;
14564
14565 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14566 DRM_INFO("applying pipe b force quirk\n");
14567 }
14568
14569 /*
14570 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14571 */
14572 static void quirk_ssc_force_disable(struct drm_device *dev)
14573 {
14574 struct drm_i915_private *dev_priv = dev->dev_private;
14575 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14576 DRM_INFO("applying lvds SSC disable quirk\n");
14577 }
14578
14579 /*
14580 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14581 * brightness value
14582 */
14583 static void quirk_invert_brightness(struct drm_device *dev)
14584 {
14585 struct drm_i915_private *dev_priv = dev->dev_private;
14586 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14587 DRM_INFO("applying inverted panel brightness quirk\n");
14588 }
14589
14590 /* Some VBT's incorrectly indicate no backlight is present */
14591 static void quirk_backlight_present(struct drm_device *dev)
14592 {
14593 struct drm_i915_private *dev_priv = dev->dev_private;
14594 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14595 DRM_INFO("applying backlight present quirk\n");
14596 }
14597
14598 struct intel_quirk {
14599 int device;
14600 int subsystem_vendor;
14601 int subsystem_device;
14602 void (*hook)(struct drm_device *dev);
14603 };
14604
14605 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14606 struct intel_dmi_quirk {
14607 void (*hook)(struct drm_device *dev);
14608 const struct dmi_system_id (*dmi_id_list)[];
14609 };
14610
14611 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14612 {
14613 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14614 return 1;
14615 }
14616
14617 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14618 {
14619 .dmi_id_list = &(const struct dmi_system_id[]) {
14620 {
14621 .callback = intel_dmi_reverse_brightness,
14622 .ident = "NCR Corporation",
14623 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14624 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14625 },
14626 },
14627 { } /* terminating entry */
14628 },
14629 .hook = quirk_invert_brightness,
14630 },
14631 };
14632
14633 static struct intel_quirk intel_quirks[] = {
14634 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14635 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14636
14637 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14638 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14639
14640 /* 830 needs to leave pipe A & dpll A up */
14641 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14642
14643 /* 830 needs to leave pipe B & dpll B up */
14644 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14645
14646 /* Lenovo U160 cannot use SSC on LVDS */
14647 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14648
14649 /* Sony Vaio Y cannot use SSC on LVDS */
14650 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14651
14652 /* Acer Aspire 5734Z must invert backlight brightness */
14653 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14654
14655 /* Acer/eMachines G725 */
14656 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14657
14658 /* Acer/eMachines e725 */
14659 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14660
14661 /* Acer/Packard Bell NCL20 */
14662 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14663
14664 /* Acer Aspire 4736Z */
14665 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14666
14667 /* Acer Aspire 5336 */
14668 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14669
14670 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14671 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14672
14673 /* Acer C720 Chromebook (Core i3 4005U) */
14674 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14675
14676 /* Apple Macbook 2,1 (Core 2 T7400) */
14677 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14678
14679 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14680 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14681
14682 /* HP Chromebook 14 (Celeron 2955U) */
14683 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14684
14685 /* Dell Chromebook 11 */
14686 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14687 };
14688
14689 static void intel_init_quirks(struct drm_device *dev)
14690 {
14691 struct pci_dev *d = dev->pdev;
14692 int i;
14693
14694 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14695 struct intel_quirk *q = &intel_quirks[i];
14696
14697 if (d->device == q->device &&
14698 (d->subsystem_vendor == q->subsystem_vendor ||
14699 q->subsystem_vendor == PCI_ANY_ID) &&
14700 (d->subsystem_device == q->subsystem_device ||
14701 q->subsystem_device == PCI_ANY_ID))
14702 q->hook(dev);
14703 }
14704 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14705 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14706 intel_dmi_quirks[i].hook(dev);
14707 }
14708 }
14709
14710 /* Disable the VGA plane that we never use */
14711 static void i915_disable_vga(struct drm_device *dev)
14712 {
14713 struct drm_i915_private *dev_priv = dev->dev_private;
14714 u8 sr1;
14715 u32 vga_reg = i915_vgacntrl_reg(dev);
14716
14717 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14718 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14719 outb(SR01, VGA_SR_INDEX);
14720 sr1 = inb(VGA_SR_DATA);
14721 outb(sr1 | 1<<5, VGA_SR_DATA);
14722 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14723 udelay(300);
14724
14725 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14726 POSTING_READ(vga_reg);
14727 }
14728
14729 void intel_modeset_init_hw(struct drm_device *dev)
14730 {
14731 intel_update_cdclk(dev);
14732 intel_prepare_ddi(dev);
14733 intel_init_clock_gating(dev);
14734 intel_enable_gt_powersave(dev);
14735 }
14736
14737 void intel_modeset_init(struct drm_device *dev)
14738 {
14739 struct drm_i915_private *dev_priv = dev->dev_private;
14740 int sprite, ret;
14741 enum pipe pipe;
14742 struct intel_crtc *crtc;
14743
14744 drm_mode_config_init(dev);
14745
14746 dev->mode_config.min_width = 0;
14747 dev->mode_config.min_height = 0;
14748
14749 dev->mode_config.preferred_depth = 24;
14750 dev->mode_config.prefer_shadow = 1;
14751
14752 dev->mode_config.allow_fb_modifiers = true;
14753
14754 dev->mode_config.funcs = &intel_mode_funcs;
14755
14756 intel_init_quirks(dev);
14757
14758 intel_init_pm(dev);
14759
14760 if (INTEL_INFO(dev)->num_pipes == 0)
14761 return;
14762
14763 /*
14764 * There may be no VBT; and if the BIOS enabled SSC we can
14765 * just keep using it to avoid unnecessary flicker. Whereas if the
14766 * BIOS isn't using it, don't assume it will work even if the VBT
14767 * indicates as much.
14768 */
14769 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
14770 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14771 DREF_SSC1_ENABLE);
14772
14773 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14774 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14775 bios_lvds_use_ssc ? "en" : "dis",
14776 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14777 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14778 }
14779 }
14780
14781 intel_init_display(dev);
14782 intel_init_audio(dev);
14783
14784 if (IS_GEN2(dev)) {
14785 dev->mode_config.max_width = 2048;
14786 dev->mode_config.max_height = 2048;
14787 } else if (IS_GEN3(dev)) {
14788 dev->mode_config.max_width = 4096;
14789 dev->mode_config.max_height = 4096;
14790 } else {
14791 dev->mode_config.max_width = 8192;
14792 dev->mode_config.max_height = 8192;
14793 }
14794
14795 if (IS_845G(dev) || IS_I865G(dev)) {
14796 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14797 dev->mode_config.cursor_height = 1023;
14798 } else if (IS_GEN2(dev)) {
14799 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14800 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14801 } else {
14802 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14803 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14804 }
14805
14806 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
14807
14808 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14809 INTEL_INFO(dev)->num_pipes,
14810 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14811
14812 for_each_pipe(dev_priv, pipe) {
14813 intel_crtc_init(dev, pipe);
14814 for_each_sprite(dev_priv, pipe, sprite) {
14815 ret = intel_plane_init(dev, pipe, sprite);
14816 if (ret)
14817 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14818 pipe_name(pipe), sprite_name(pipe, sprite), ret);
14819 }
14820 }
14821
14822 intel_update_czclk(dev_priv);
14823 intel_update_cdclk(dev);
14824
14825 intel_shared_dpll_init(dev);
14826
14827 /* Just disable it once at startup */
14828 i915_disable_vga(dev);
14829 intel_setup_outputs(dev);
14830
14831 /* Just in case the BIOS is doing something questionable. */
14832 intel_fbc_disable(dev_priv);
14833
14834 drm_modeset_lock_all(dev);
14835 intel_modeset_setup_hw_state(dev);
14836 drm_modeset_unlock_all(dev);
14837
14838 for_each_intel_crtc(dev, crtc) {
14839 struct intel_initial_plane_config plane_config = {};
14840
14841 if (!crtc->active)
14842 continue;
14843
14844 /*
14845 * Note that reserving the BIOS fb up front prevents us
14846 * from stuffing other stolen allocations like the ring
14847 * on top. This prevents some ugliness at boot time, and
14848 * can even allow for smooth boot transitions if the BIOS
14849 * fb is large enough for the active pipe configuration.
14850 */
14851 dev_priv->display.get_initial_plane_config(crtc,
14852 &plane_config);
14853
14854 /*
14855 * If the fb is shared between multiple heads, we'll
14856 * just get the first one.
14857 */
14858 intel_find_initial_plane_obj(crtc, &plane_config);
14859 }
14860 }
14861
14862 static void intel_enable_pipe_a(struct drm_device *dev)
14863 {
14864 struct intel_connector *connector;
14865 struct drm_connector *crt = NULL;
14866 struct intel_load_detect_pipe load_detect_temp;
14867 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
14868
14869 /* We can't just switch on the pipe A, we need to set things up with a
14870 * proper mode and output configuration. As a gross hack, enable pipe A
14871 * by enabling the load detect pipe once. */
14872 for_each_intel_connector(dev, connector) {
14873 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14874 crt = &connector->base;
14875 break;
14876 }
14877 }
14878
14879 if (!crt)
14880 return;
14881
14882 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
14883 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
14884 }
14885
14886 static bool
14887 intel_check_plane_mapping(struct intel_crtc *crtc)
14888 {
14889 struct drm_device *dev = crtc->base.dev;
14890 struct drm_i915_private *dev_priv = dev->dev_private;
14891 u32 val;
14892
14893 if (INTEL_INFO(dev)->num_pipes == 1)
14894 return true;
14895
14896 val = I915_READ(DSPCNTR(!crtc->plane));
14897
14898 if ((val & DISPLAY_PLANE_ENABLE) &&
14899 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14900 return false;
14901
14902 return true;
14903 }
14904
14905 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
14906 {
14907 struct drm_device *dev = crtc->base.dev;
14908 struct intel_encoder *encoder;
14909
14910 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
14911 return true;
14912
14913 return false;
14914 }
14915
14916 static void intel_sanitize_crtc(struct intel_crtc *crtc)
14917 {
14918 struct drm_device *dev = crtc->base.dev;
14919 struct drm_i915_private *dev_priv = dev->dev_private;
14920 u32 reg;
14921
14922 /* Clear any frame start delays used for debugging left by the BIOS */
14923 reg = PIPECONF(crtc->config->cpu_transcoder);
14924 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14925
14926 /* restore vblank interrupts to correct state */
14927 drm_crtc_vblank_reset(&crtc->base);
14928 if (crtc->active) {
14929 struct intel_plane *plane;
14930
14931 drm_crtc_vblank_on(&crtc->base);
14932
14933 /* Disable everything but the primary plane */
14934 for_each_intel_plane_on_crtc(dev, crtc, plane) {
14935 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
14936 continue;
14937
14938 plane->disable_plane(&plane->base, &crtc->base);
14939 }
14940 }
14941
14942 /* We need to sanitize the plane -> pipe mapping first because this will
14943 * disable the crtc (and hence change the state) if it is wrong. Note
14944 * that gen4+ has a fixed plane -> pipe mapping. */
14945 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
14946 bool plane;
14947
14948 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14949 crtc->base.base.id);
14950
14951 /* Pipe has the wrong plane attached and the plane is active.
14952 * Temporarily change the plane mapping and disable everything
14953 * ... */
14954 plane = crtc->plane;
14955 to_intel_plane_state(crtc->base.primary->state)->visible = true;
14956 crtc->plane = !plane;
14957 intel_crtc_disable_noatomic(&crtc->base);
14958 crtc->plane = plane;
14959 }
14960
14961 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14962 crtc->pipe == PIPE_A && !crtc->active) {
14963 /* BIOS forgot to enable pipe A, this mostly happens after
14964 * resume. Force-enable the pipe to fix this, the update_dpms
14965 * call below we restore the pipe to the right state, but leave
14966 * the required bits on. */
14967 intel_enable_pipe_a(dev);
14968 }
14969
14970 /* Adjust the state of the output pipe according to whether we
14971 * have active connectors/encoders. */
14972 if (!intel_crtc_has_encoders(crtc))
14973 intel_crtc_disable_noatomic(&crtc->base);
14974
14975 if (crtc->active != crtc->base.state->active) {
14976 struct intel_encoder *encoder;
14977
14978 /* This can happen either due to bugs in the get_hw_state
14979 * functions or because of calls to intel_crtc_disable_noatomic,
14980 * or because the pipe is force-enabled due to the
14981 * pipe A quirk. */
14982 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14983 crtc->base.base.id,
14984 crtc->base.state->enable ? "enabled" : "disabled",
14985 crtc->active ? "enabled" : "disabled");
14986
14987 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
14988 crtc->base.state->active = crtc->active;
14989 crtc->base.enabled = crtc->active;
14990
14991 /* Because we only establish the connector -> encoder ->
14992 * crtc links if something is active, this means the
14993 * crtc is now deactivated. Break the links. connector
14994 * -> encoder links are only establish when things are
14995 * actually up, hence no need to break them. */
14996 WARN_ON(crtc->active);
14997
14998 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
14999 encoder->base.crtc = NULL;
15000 }
15001
15002 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15003 /*
15004 * We start out with underrun reporting disabled to avoid races.
15005 * For correct bookkeeping mark this on active crtcs.
15006 *
15007 * Also on gmch platforms we dont have any hardware bits to
15008 * disable the underrun reporting. Which means we need to start
15009 * out with underrun reporting disabled also on inactive pipes,
15010 * since otherwise we'll complain about the garbage we read when
15011 * e.g. coming up after runtime pm.
15012 *
15013 * No protection against concurrent access is required - at
15014 * worst a fifo underrun happens which also sets this to false.
15015 */
15016 crtc->cpu_fifo_underrun_disabled = true;
15017 crtc->pch_fifo_underrun_disabled = true;
15018 }
15019 }
15020
15021 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15022 {
15023 struct intel_connector *connector;
15024 struct drm_device *dev = encoder->base.dev;
15025 bool active = false;
15026
15027 /* We need to check both for a crtc link (meaning that the
15028 * encoder is active and trying to read from a pipe) and the
15029 * pipe itself being active. */
15030 bool has_active_crtc = encoder->base.crtc &&
15031 to_intel_crtc(encoder->base.crtc)->active;
15032
15033 for_each_intel_connector(dev, connector) {
15034 if (connector->base.encoder != &encoder->base)
15035 continue;
15036
15037 active = true;
15038 break;
15039 }
15040
15041 if (active && !has_active_crtc) {
15042 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15043 encoder->base.base.id,
15044 encoder->base.name);
15045
15046 /* Connector is active, but has no active pipe. This is
15047 * fallout from our resume register restoring. Disable
15048 * the encoder manually again. */
15049 if (encoder->base.crtc) {
15050 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15051 encoder->base.base.id,
15052 encoder->base.name);
15053 encoder->disable(encoder);
15054 if (encoder->post_disable)
15055 encoder->post_disable(encoder);
15056 }
15057 encoder->base.crtc = NULL;
15058
15059 /* Inconsistent output/port/pipe state happens presumably due to
15060 * a bug in one of the get_hw_state functions. Or someplace else
15061 * in our code, like the register restore mess on resume. Clamp
15062 * things to off as a safer default. */
15063 for_each_intel_connector(dev, connector) {
15064 if (connector->encoder != encoder)
15065 continue;
15066 connector->base.dpms = DRM_MODE_DPMS_OFF;
15067 connector->base.encoder = NULL;
15068 }
15069 }
15070 /* Enabled encoders without active connectors will be fixed in
15071 * the crtc fixup. */
15072 }
15073
15074 void i915_redisable_vga_power_on(struct drm_device *dev)
15075 {
15076 struct drm_i915_private *dev_priv = dev->dev_private;
15077 u32 vga_reg = i915_vgacntrl_reg(dev);
15078
15079 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15080 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15081 i915_disable_vga(dev);
15082 }
15083 }
15084
15085 void i915_redisable_vga(struct drm_device *dev)
15086 {
15087 struct drm_i915_private *dev_priv = dev->dev_private;
15088
15089 /* This function can be called both from intel_modeset_setup_hw_state or
15090 * at a very early point in our resume sequence, where the power well
15091 * structures are not yet restored. Since this function is at a very
15092 * paranoid "someone might have enabled VGA while we were not looking"
15093 * level, just check if the power well is enabled instead of trying to
15094 * follow the "don't touch the power well if we don't need it" policy
15095 * the rest of the driver uses. */
15096 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15097 return;
15098
15099 i915_redisable_vga_power_on(dev);
15100 }
15101
15102 static bool primary_get_hw_state(struct intel_plane *plane)
15103 {
15104 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15105
15106 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15107 }
15108
15109 /* FIXME read out full plane state for all planes */
15110 static void readout_plane_state(struct intel_crtc *crtc)
15111 {
15112 struct drm_plane *primary = crtc->base.primary;
15113 struct intel_plane_state *plane_state =
15114 to_intel_plane_state(primary->state);
15115
15116 plane_state->visible =
15117 primary_get_hw_state(to_intel_plane(primary));
15118
15119 if (plane_state->visible)
15120 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15121 }
15122
15123 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15124 {
15125 struct drm_i915_private *dev_priv = dev->dev_private;
15126 enum pipe pipe;
15127 struct intel_crtc *crtc;
15128 struct intel_encoder *encoder;
15129 struct intel_connector *connector;
15130 int i;
15131
15132 for_each_intel_crtc(dev, crtc) {
15133 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
15134 memset(crtc->config, 0, sizeof(*crtc->config));
15135 crtc->config->base.crtc = &crtc->base;
15136
15137 crtc->active = dev_priv->display.get_pipe_config(crtc,
15138 crtc->config);
15139
15140 crtc->base.state->active = crtc->active;
15141 crtc->base.enabled = crtc->active;
15142
15143 readout_plane_state(crtc);
15144
15145 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15146 crtc->base.base.id,
15147 crtc->active ? "enabled" : "disabled");
15148 }
15149
15150 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15151 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15152
15153 pll->on = pll->get_hw_state(dev_priv, pll,
15154 &pll->config.hw_state);
15155 pll->active = 0;
15156 pll->config.crtc_mask = 0;
15157 for_each_intel_crtc(dev, crtc) {
15158 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15159 pll->active++;
15160 pll->config.crtc_mask |= 1 << crtc->pipe;
15161 }
15162 }
15163
15164 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15165 pll->name, pll->config.crtc_mask, pll->on);
15166
15167 if (pll->config.crtc_mask)
15168 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15169 }
15170
15171 for_each_intel_encoder(dev, encoder) {
15172 pipe = 0;
15173
15174 if (encoder->get_hw_state(encoder, &pipe)) {
15175 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15176 encoder->base.crtc = &crtc->base;
15177 encoder->get_config(encoder, crtc->config);
15178 } else {
15179 encoder->base.crtc = NULL;
15180 }
15181
15182 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15183 encoder->base.base.id,
15184 encoder->base.name,
15185 encoder->base.crtc ? "enabled" : "disabled",
15186 pipe_name(pipe));
15187 }
15188
15189 for_each_intel_connector(dev, connector) {
15190 if (connector->get_hw_state(connector)) {
15191 connector->base.dpms = DRM_MODE_DPMS_ON;
15192 connector->base.encoder = &connector->encoder->base;
15193 } else {
15194 connector->base.dpms = DRM_MODE_DPMS_OFF;
15195 connector->base.encoder = NULL;
15196 }
15197 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15198 connector->base.base.id,
15199 connector->base.name,
15200 connector->base.encoder ? "enabled" : "disabled");
15201 }
15202
15203 for_each_intel_crtc(dev, crtc) {
15204 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15205
15206 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15207 if (crtc->base.state->active) {
15208 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15209 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15210 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15211
15212 /*
15213 * The initial mode needs to be set in order to keep
15214 * the atomic core happy. It wants a valid mode if the
15215 * crtc's enabled, so we do the above call.
15216 *
15217 * At this point some state updated by the connectors
15218 * in their ->detect() callback has not run yet, so
15219 * no recalculation can be done yet.
15220 *
15221 * Even if we could do a recalculation and modeset
15222 * right now it would cause a double modeset if
15223 * fbdev or userspace chooses a different initial mode.
15224 *
15225 * If that happens, someone indicated they wanted a
15226 * mode change, which means it's safe to do a full
15227 * recalculation.
15228 */
15229 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15230
15231 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15232 update_scanline_offset(crtc);
15233 }
15234 }
15235 }
15236
15237 /* Scan out the current hw modeset state,
15238 * and sanitizes it to the current state
15239 */
15240 static void
15241 intel_modeset_setup_hw_state(struct drm_device *dev)
15242 {
15243 struct drm_i915_private *dev_priv = dev->dev_private;
15244 enum pipe pipe;
15245 struct intel_crtc *crtc;
15246 struct intel_encoder *encoder;
15247 int i;
15248
15249 intel_modeset_readout_hw_state(dev);
15250
15251 /* HW state is read out, now we need to sanitize this mess. */
15252 for_each_intel_encoder(dev, encoder) {
15253 intel_sanitize_encoder(encoder);
15254 }
15255
15256 for_each_pipe(dev_priv, pipe) {
15257 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15258 intel_sanitize_crtc(crtc);
15259 intel_dump_pipe_config(crtc, crtc->config,
15260 "[setup_hw_state]");
15261 }
15262
15263 intel_modeset_update_connector_atomic_state(dev);
15264
15265 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15266 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15267
15268 if (!pll->on || pll->active)
15269 continue;
15270
15271 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15272
15273 pll->disable(dev_priv, pll);
15274 pll->on = false;
15275 }
15276
15277 if (IS_VALLEYVIEW(dev))
15278 vlv_wm_get_hw_state(dev);
15279 else if (IS_GEN9(dev))
15280 skl_wm_get_hw_state(dev);
15281 else if (HAS_PCH_SPLIT(dev))
15282 ilk_wm_get_hw_state(dev);
15283
15284 for_each_intel_crtc(dev, crtc) {
15285 unsigned long put_domains;
15286
15287 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15288 if (WARN_ON(put_domains))
15289 modeset_put_power_domains(dev_priv, put_domains);
15290 }
15291 intel_display_set_init_power(dev_priv, false);
15292 }
15293
15294 void intel_display_resume(struct drm_device *dev)
15295 {
15296 struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15297 struct intel_connector *conn;
15298 struct intel_plane *plane;
15299 struct drm_crtc *crtc;
15300 int ret;
15301
15302 if (!state)
15303 return;
15304
15305 state->acquire_ctx = dev->mode_config.acquire_ctx;
15306
15307 /* preserve complete old state, including dpll */
15308 intel_atomic_get_shared_dpll_state(state);
15309
15310 for_each_crtc(dev, crtc) {
15311 struct drm_crtc_state *crtc_state =
15312 drm_atomic_get_crtc_state(state, crtc);
15313
15314 ret = PTR_ERR_OR_ZERO(crtc_state);
15315 if (ret)
15316 goto err;
15317
15318 /* force a restore */
15319 crtc_state->mode_changed = true;
15320 }
15321
15322 for_each_intel_plane(dev, plane) {
15323 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15324 if (ret)
15325 goto err;
15326 }
15327
15328 for_each_intel_connector(dev, conn) {
15329 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15330 if (ret)
15331 goto err;
15332 }
15333
15334 intel_modeset_setup_hw_state(dev);
15335
15336 i915_redisable_vga(dev);
15337 ret = drm_atomic_commit(state);
15338 if (!ret)
15339 return;
15340
15341 err:
15342 DRM_ERROR("Restoring old state failed with %i\n", ret);
15343 drm_atomic_state_free(state);
15344 }
15345
15346 void intel_modeset_gem_init(struct drm_device *dev)
15347 {
15348 struct drm_crtc *c;
15349 struct drm_i915_gem_object *obj;
15350 int ret;
15351
15352 mutex_lock(&dev->struct_mutex);
15353 intel_init_gt_powersave(dev);
15354 mutex_unlock(&dev->struct_mutex);
15355
15356 intel_modeset_init_hw(dev);
15357
15358 intel_setup_overlay(dev);
15359
15360 /*
15361 * Make sure any fbs we allocated at startup are properly
15362 * pinned & fenced. When we do the allocation it's too early
15363 * for this.
15364 */
15365 for_each_crtc(dev, c) {
15366 obj = intel_fb_obj(c->primary->fb);
15367 if (obj == NULL)
15368 continue;
15369
15370 mutex_lock(&dev->struct_mutex);
15371 ret = intel_pin_and_fence_fb_obj(c->primary,
15372 c->primary->fb,
15373 c->primary->state,
15374 NULL, NULL);
15375 mutex_unlock(&dev->struct_mutex);
15376 if (ret) {
15377 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15378 to_intel_crtc(c)->pipe);
15379 drm_framebuffer_unreference(c->primary->fb);
15380 c->primary->fb = NULL;
15381 c->primary->crtc = c->primary->state->crtc = NULL;
15382 update_state_fb(c->primary);
15383 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15384 }
15385 }
15386
15387 intel_backlight_register(dev);
15388 }
15389
15390 void intel_connector_unregister(struct intel_connector *intel_connector)
15391 {
15392 struct drm_connector *connector = &intel_connector->base;
15393
15394 intel_panel_destroy_backlight(connector);
15395 drm_connector_unregister(connector);
15396 }
15397
15398 void intel_modeset_cleanup(struct drm_device *dev)
15399 {
15400 struct drm_i915_private *dev_priv = dev->dev_private;
15401 struct drm_connector *connector;
15402
15403 intel_disable_gt_powersave(dev);
15404
15405 intel_backlight_unregister(dev);
15406
15407 /*
15408 * Interrupts and polling as the first thing to avoid creating havoc.
15409 * Too much stuff here (turning of connectors, ...) would
15410 * experience fancy races otherwise.
15411 */
15412 intel_irq_uninstall(dev_priv);
15413
15414 /*
15415 * Due to the hpd irq storm handling the hotplug work can re-arm the
15416 * poll handlers. Hence disable polling after hpd handling is shut down.
15417 */
15418 drm_kms_helper_poll_fini(dev);
15419
15420 intel_unregister_dsm_handler();
15421
15422 intel_fbc_disable(dev_priv);
15423
15424 /* flush any delayed tasks or pending work */
15425 flush_scheduled_work();
15426
15427 /* destroy the backlight and sysfs files before encoders/connectors */
15428 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15429 struct intel_connector *intel_connector;
15430
15431 intel_connector = to_intel_connector(connector);
15432 intel_connector->unregister(intel_connector);
15433 }
15434
15435 drm_mode_config_cleanup(dev);
15436
15437 intel_cleanup_overlay(dev);
15438
15439 mutex_lock(&dev->struct_mutex);
15440 intel_cleanup_gt_powersave(dev);
15441 mutex_unlock(&dev->struct_mutex);
15442 }
15443
15444 /*
15445 * Return which encoder is currently attached for connector.
15446 */
15447 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15448 {
15449 return &intel_attached_encoder(connector)->base;
15450 }
15451
15452 void intel_connector_attach_encoder(struct intel_connector *connector,
15453 struct intel_encoder *encoder)
15454 {
15455 connector->encoder = encoder;
15456 drm_mode_connector_attach_encoder(&connector->base,
15457 &encoder->base);
15458 }
15459
15460 /*
15461 * set vga decode state - true == enable VGA decode
15462 */
15463 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15464 {
15465 struct drm_i915_private *dev_priv = dev->dev_private;
15466 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15467 u16 gmch_ctrl;
15468
15469 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15470 DRM_ERROR("failed to read control word\n");
15471 return -EIO;
15472 }
15473
15474 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15475 return 0;
15476
15477 if (state)
15478 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15479 else
15480 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15481
15482 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15483 DRM_ERROR("failed to write control word\n");
15484 return -EIO;
15485 }
15486
15487 return 0;
15488 }
15489
15490 struct intel_display_error_state {
15491
15492 u32 power_well_driver;
15493
15494 int num_transcoders;
15495
15496 struct intel_cursor_error_state {
15497 u32 control;
15498 u32 position;
15499 u32 base;
15500 u32 size;
15501 } cursor[I915_MAX_PIPES];
15502
15503 struct intel_pipe_error_state {
15504 bool power_domain_on;
15505 u32 source;
15506 u32 stat;
15507 } pipe[I915_MAX_PIPES];
15508
15509 struct intel_plane_error_state {
15510 u32 control;
15511 u32 stride;
15512 u32 size;
15513 u32 pos;
15514 u32 addr;
15515 u32 surface;
15516 u32 tile_offset;
15517 } plane[I915_MAX_PIPES];
15518
15519 struct intel_transcoder_error_state {
15520 bool power_domain_on;
15521 enum transcoder cpu_transcoder;
15522
15523 u32 conf;
15524
15525 u32 htotal;
15526 u32 hblank;
15527 u32 hsync;
15528 u32 vtotal;
15529 u32 vblank;
15530 u32 vsync;
15531 } transcoder[4];
15532 };
15533
15534 struct intel_display_error_state *
15535 intel_display_capture_error_state(struct drm_device *dev)
15536 {
15537 struct drm_i915_private *dev_priv = dev->dev_private;
15538 struct intel_display_error_state *error;
15539 int transcoders[] = {
15540 TRANSCODER_A,
15541 TRANSCODER_B,
15542 TRANSCODER_C,
15543 TRANSCODER_EDP,
15544 };
15545 int i;
15546
15547 if (INTEL_INFO(dev)->num_pipes == 0)
15548 return NULL;
15549
15550 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15551 if (error == NULL)
15552 return NULL;
15553
15554 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15555 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15556
15557 for_each_pipe(dev_priv, i) {
15558 error->pipe[i].power_domain_on =
15559 __intel_display_power_is_enabled(dev_priv,
15560 POWER_DOMAIN_PIPE(i));
15561 if (!error->pipe[i].power_domain_on)
15562 continue;
15563
15564 error->cursor[i].control = I915_READ(CURCNTR(i));
15565 error->cursor[i].position = I915_READ(CURPOS(i));
15566 error->cursor[i].base = I915_READ(CURBASE(i));
15567
15568 error->plane[i].control = I915_READ(DSPCNTR(i));
15569 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15570 if (INTEL_INFO(dev)->gen <= 3) {
15571 error->plane[i].size = I915_READ(DSPSIZE(i));
15572 error->plane[i].pos = I915_READ(DSPPOS(i));
15573 }
15574 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15575 error->plane[i].addr = I915_READ(DSPADDR(i));
15576 if (INTEL_INFO(dev)->gen >= 4) {
15577 error->plane[i].surface = I915_READ(DSPSURF(i));
15578 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15579 }
15580
15581 error->pipe[i].source = I915_READ(PIPESRC(i));
15582
15583 if (HAS_GMCH_DISPLAY(dev))
15584 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15585 }
15586
15587 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15588 if (HAS_DDI(dev_priv->dev))
15589 error->num_transcoders++; /* Account for eDP. */
15590
15591 for (i = 0; i < error->num_transcoders; i++) {
15592 enum transcoder cpu_transcoder = transcoders[i];
15593
15594 error->transcoder[i].power_domain_on =
15595 __intel_display_power_is_enabled(dev_priv,
15596 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15597 if (!error->transcoder[i].power_domain_on)
15598 continue;
15599
15600 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15601
15602 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15603 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15604 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15605 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15606 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15607 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15608 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15609 }
15610
15611 return error;
15612 }
15613
15614 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15615
15616 void
15617 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15618 struct drm_device *dev,
15619 struct intel_display_error_state *error)
15620 {
15621 struct drm_i915_private *dev_priv = dev->dev_private;
15622 int i;
15623
15624 if (!error)
15625 return;
15626
15627 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15628 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15629 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15630 error->power_well_driver);
15631 for_each_pipe(dev_priv, i) {
15632 err_printf(m, "Pipe [%d]:\n", i);
15633 err_printf(m, " Power: %s\n",
15634 error->pipe[i].power_domain_on ? "on" : "off");
15635 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15636 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15637
15638 err_printf(m, "Plane [%d]:\n", i);
15639 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15640 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15641 if (INTEL_INFO(dev)->gen <= 3) {
15642 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15643 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15644 }
15645 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15646 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15647 if (INTEL_INFO(dev)->gen >= 4) {
15648 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15649 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15650 }
15651
15652 err_printf(m, "Cursor [%d]:\n", i);
15653 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15654 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15655 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15656 }
15657
15658 for (i = 0; i < error->num_transcoders; i++) {
15659 err_printf(m, "CPU transcoder: %c\n",
15660 transcoder_name(error->transcoder[i].cpu_transcoder));
15661 err_printf(m, " Power: %s\n",
15662 error->transcoder[i].power_domain_on ? "on" : "off");
15663 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15664 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15665 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15666 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15667 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15668 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15669 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15670 }
15671 }
15672
15673 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15674 {
15675 struct intel_crtc *crtc;
15676
15677 for_each_intel_crtc(dev, crtc) {
15678 struct intel_unpin_work *work;
15679
15680 spin_lock_irq(&dev->event_lock);
15681
15682 work = crtc->unpin_work;
15683
15684 if (work && work->event &&
15685 work->event->base.file_priv == file) {
15686 kfree(work->event);
15687 work->event = NULL;
15688 }
15689
15690 spin_unlock_irq(&dev->event_lock);
15691 }
15692 }
Linux kernel - Deliverables
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