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Merge tag 'v3.4-rc6' into drm-intel-next
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include "drmP.h"
36 #include "intel_drv.h"
37 #include "i915_drm.h"
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include "drm_dp_helper.h"
41 #include "drm_crtc_helper.h"
42 #include <linux/dma_remapping.h>
43
44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
47 static void intel_increase_pllclock(struct drm_crtc *crtc);
48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
49
50 typedef struct {
51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
60 } intel_clock_t;
61
62 typedef struct {
63 int min, max;
64 } intel_range_t;
65
66 typedef struct {
67 int dot_limit;
68 int p2_slow, p2_fast;
69 } intel_p2_t;
70
71 #define INTEL_P2_NUM 2
72 typedef struct intel_limit intel_limit_t;
73 struct intel_limit {
74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
77 int, int, intel_clock_t *, intel_clock_t *);
78 };
79
80 /* FDI */
81 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
83 static bool
84 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
85 int target, int refclk, intel_clock_t *match_clock,
86 intel_clock_t *best_clock);
87 static bool
88 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
89 int target, int refclk, intel_clock_t *match_clock,
90 intel_clock_t *best_clock);
91
92 static bool
93 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
94 int target, int refclk, intel_clock_t *match_clock,
95 intel_clock_t *best_clock);
96 static bool
97 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
98 int target, int refclk, intel_clock_t *match_clock,
99 intel_clock_t *best_clock);
100
101 static inline u32 /* units of 100MHz */
102 intel_fdi_link_freq(struct drm_device *dev)
103 {
104 if (IS_GEN5(dev)) {
105 struct drm_i915_private *dev_priv = dev->dev_private;
106 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
107 } else
108 return 27;
109 }
110
111 static const intel_limit_t intel_limits_i8xx_dvo = {
112 .dot = { .min = 25000, .max = 350000 },
113 .vco = { .min = 930000, .max = 1400000 },
114 .n = { .min = 3, .max = 16 },
115 .m = { .min = 96, .max = 140 },
116 .m1 = { .min = 18, .max = 26 },
117 .m2 = { .min = 6, .max = 16 },
118 .p = { .min = 4, .max = 128 },
119 .p1 = { .min = 2, .max = 33 },
120 .p2 = { .dot_limit = 165000,
121 .p2_slow = 4, .p2_fast = 2 },
122 .find_pll = intel_find_best_PLL,
123 };
124
125 static const intel_limit_t intel_limits_i8xx_lvds = {
126 .dot = { .min = 25000, .max = 350000 },
127 .vco = { .min = 930000, .max = 1400000 },
128 .n = { .min = 3, .max = 16 },
129 .m = { .min = 96, .max = 140 },
130 .m1 = { .min = 18, .max = 26 },
131 .m2 = { .min = 6, .max = 16 },
132 .p = { .min = 4, .max = 128 },
133 .p1 = { .min = 1, .max = 6 },
134 .p2 = { .dot_limit = 165000,
135 .p2_slow = 14, .p2_fast = 7 },
136 .find_pll = intel_find_best_PLL,
137 };
138
139 static const intel_limit_t intel_limits_i9xx_sdvo = {
140 .dot = { .min = 20000, .max = 400000 },
141 .vco = { .min = 1400000, .max = 2800000 },
142 .n = { .min = 1, .max = 6 },
143 .m = { .min = 70, .max = 120 },
144 .m1 = { .min = 10, .max = 22 },
145 .m2 = { .min = 5, .max = 9 },
146 .p = { .min = 5, .max = 80 },
147 .p1 = { .min = 1, .max = 8 },
148 .p2 = { .dot_limit = 200000,
149 .p2_slow = 10, .p2_fast = 5 },
150 .find_pll = intel_find_best_PLL,
151 };
152
153 static const intel_limit_t intel_limits_i9xx_lvds = {
154 .dot = { .min = 20000, .max = 400000 },
155 .vco = { .min = 1400000, .max = 2800000 },
156 .n = { .min = 1, .max = 6 },
157 .m = { .min = 70, .max = 120 },
158 .m1 = { .min = 10, .max = 22 },
159 .m2 = { .min = 5, .max = 9 },
160 .p = { .min = 7, .max = 98 },
161 .p1 = { .min = 1, .max = 8 },
162 .p2 = { .dot_limit = 112000,
163 .p2_slow = 14, .p2_fast = 7 },
164 .find_pll = intel_find_best_PLL,
165 };
166
167
168 static const intel_limit_t intel_limits_g4x_sdvo = {
169 .dot = { .min = 25000, .max = 270000 },
170 .vco = { .min = 1750000, .max = 3500000},
171 .n = { .min = 1, .max = 4 },
172 .m = { .min = 104, .max = 138 },
173 .m1 = { .min = 17, .max = 23 },
174 .m2 = { .min = 5, .max = 11 },
175 .p = { .min = 10, .max = 30 },
176 .p1 = { .min = 1, .max = 3},
177 .p2 = { .dot_limit = 270000,
178 .p2_slow = 10,
179 .p2_fast = 10
180 },
181 .find_pll = intel_g4x_find_best_PLL,
182 };
183
184 static const intel_limit_t intel_limits_g4x_hdmi = {
185 .dot = { .min = 22000, .max = 400000 },
186 .vco = { .min = 1750000, .max = 3500000},
187 .n = { .min = 1, .max = 4 },
188 .m = { .min = 104, .max = 138 },
189 .m1 = { .min = 16, .max = 23 },
190 .m2 = { .min = 5, .max = 11 },
191 .p = { .min = 5, .max = 80 },
192 .p1 = { .min = 1, .max = 8},
193 .p2 = { .dot_limit = 165000,
194 .p2_slow = 10, .p2_fast = 5 },
195 .find_pll = intel_g4x_find_best_PLL,
196 };
197
198 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
199 .dot = { .min = 20000, .max = 115000 },
200 .vco = { .min = 1750000, .max = 3500000 },
201 .n = { .min = 1, .max = 3 },
202 .m = { .min = 104, .max = 138 },
203 .m1 = { .min = 17, .max = 23 },
204 .m2 = { .min = 5, .max = 11 },
205 .p = { .min = 28, .max = 112 },
206 .p1 = { .min = 2, .max = 8 },
207 .p2 = { .dot_limit = 0,
208 .p2_slow = 14, .p2_fast = 14
209 },
210 .find_pll = intel_g4x_find_best_PLL,
211 };
212
213 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
214 .dot = { .min = 80000, .max = 224000 },
215 .vco = { .min = 1750000, .max = 3500000 },
216 .n = { .min = 1, .max = 3 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 17, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 14, .max = 42 },
221 .p1 = { .min = 2, .max = 6 },
222 .p2 = { .dot_limit = 0,
223 .p2_slow = 7, .p2_fast = 7
224 },
225 .find_pll = intel_g4x_find_best_PLL,
226 };
227
228 static const intel_limit_t intel_limits_g4x_display_port = {
229 .dot = { .min = 161670, .max = 227000 },
230 .vco = { .min = 1750000, .max = 3500000},
231 .n = { .min = 1, .max = 2 },
232 .m = { .min = 97, .max = 108 },
233 .m1 = { .min = 0x10, .max = 0x12 },
234 .m2 = { .min = 0x05, .max = 0x06 },
235 .p = { .min = 10, .max = 20 },
236 .p1 = { .min = 1, .max = 2},
237 .p2 = { .dot_limit = 0,
238 .p2_slow = 10, .p2_fast = 10 },
239 .find_pll = intel_find_pll_g4x_dp,
240 };
241
242 static const intel_limit_t intel_limits_pineview_sdvo = {
243 .dot = { .min = 20000, .max = 400000},
244 .vco = { .min = 1700000, .max = 3500000 },
245 /* Pineview's Ncounter is a ring counter */
246 .n = { .min = 3, .max = 6 },
247 .m = { .min = 2, .max = 256 },
248 /* Pineview only has one combined m divider, which we treat as m2. */
249 .m1 = { .min = 0, .max = 0 },
250 .m2 = { .min = 0, .max = 254 },
251 .p = { .min = 5, .max = 80 },
252 .p1 = { .min = 1, .max = 8 },
253 .p2 = { .dot_limit = 200000,
254 .p2_slow = 10, .p2_fast = 5 },
255 .find_pll = intel_find_best_PLL,
256 };
257
258 static const intel_limit_t intel_limits_pineview_lvds = {
259 .dot = { .min = 20000, .max = 400000 },
260 .vco = { .min = 1700000, .max = 3500000 },
261 .n = { .min = 3, .max = 6 },
262 .m = { .min = 2, .max = 256 },
263 .m1 = { .min = 0, .max = 0 },
264 .m2 = { .min = 0, .max = 254 },
265 .p = { .min = 7, .max = 112 },
266 .p1 = { .min = 1, .max = 8 },
267 .p2 = { .dot_limit = 112000,
268 .p2_slow = 14, .p2_fast = 14 },
269 .find_pll = intel_find_best_PLL,
270 };
271
272 /* Ironlake / Sandybridge
273 *
274 * We calculate clock using (register_value + 2) for N/M1/M2, so here
275 * the range value for them is (actual_value - 2).
276 */
277 static const intel_limit_t intel_limits_ironlake_dac = {
278 .dot = { .min = 25000, .max = 350000 },
279 .vco = { .min = 1760000, .max = 3510000 },
280 .n = { .min = 1, .max = 5 },
281 .m = { .min = 79, .max = 127 },
282 .m1 = { .min = 12, .max = 22 },
283 .m2 = { .min = 5, .max = 9 },
284 .p = { .min = 5, .max = 80 },
285 .p1 = { .min = 1, .max = 8 },
286 .p2 = { .dot_limit = 225000,
287 .p2_slow = 10, .p2_fast = 5 },
288 .find_pll = intel_g4x_find_best_PLL,
289 };
290
291 static const intel_limit_t intel_limits_ironlake_single_lvds = {
292 .dot = { .min = 25000, .max = 350000 },
293 .vco = { .min = 1760000, .max = 3510000 },
294 .n = { .min = 1, .max = 3 },
295 .m = { .min = 79, .max = 118 },
296 .m1 = { .min = 12, .max = 22 },
297 .m2 = { .min = 5, .max = 9 },
298 .p = { .min = 28, .max = 112 },
299 .p1 = { .min = 2, .max = 8 },
300 .p2 = { .dot_limit = 225000,
301 .p2_slow = 14, .p2_fast = 14 },
302 .find_pll = intel_g4x_find_best_PLL,
303 };
304
305 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
306 .dot = { .min = 25000, .max = 350000 },
307 .vco = { .min = 1760000, .max = 3510000 },
308 .n = { .min = 1, .max = 3 },
309 .m = { .min = 79, .max = 127 },
310 .m1 = { .min = 12, .max = 22 },
311 .m2 = { .min = 5, .max = 9 },
312 .p = { .min = 14, .max = 56 },
313 .p1 = { .min = 2, .max = 8 },
314 .p2 = { .dot_limit = 225000,
315 .p2_slow = 7, .p2_fast = 7 },
316 .find_pll = intel_g4x_find_best_PLL,
317 };
318
319 /* LVDS 100mhz refclk limits. */
320 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 2 },
324 .m = { .min = 79, .max = 126 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 28, .max = 112 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 14, .p2_fast = 14 },
331 .find_pll = intel_g4x_find_best_PLL,
332 };
333
334 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
335 .dot = { .min = 25000, .max = 350000 },
336 .vco = { .min = 1760000, .max = 3510000 },
337 .n = { .min = 1, .max = 3 },
338 .m = { .min = 79, .max = 126 },
339 .m1 = { .min = 12, .max = 22 },
340 .m2 = { .min = 5, .max = 9 },
341 .p = { .min = 14, .max = 42 },
342 .p1 = { .min = 2, .max = 6 },
343 .p2 = { .dot_limit = 225000,
344 .p2_slow = 7, .p2_fast = 7 },
345 .find_pll = intel_g4x_find_best_PLL,
346 };
347
348 static const intel_limit_t intel_limits_ironlake_display_port = {
349 .dot = { .min = 25000, .max = 350000 },
350 .vco = { .min = 1760000, .max = 3510000},
351 .n = { .min = 1, .max = 2 },
352 .m = { .min = 81, .max = 90 },
353 .m1 = { .min = 12, .max = 22 },
354 .m2 = { .min = 5, .max = 9 },
355 .p = { .min = 10, .max = 20 },
356 .p1 = { .min = 1, .max = 2},
357 .p2 = { .dot_limit = 0,
358 .p2_slow = 10, .p2_fast = 10 },
359 .find_pll = intel_find_pll_ironlake_dp,
360 };
361
362 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
363 {
364 unsigned long flags;
365 u32 val = 0;
366
367 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
368 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
369 DRM_ERROR("DPIO idle wait timed out\n");
370 goto out_unlock;
371 }
372
373 I915_WRITE(DPIO_REG, reg);
374 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
375 DPIO_BYTE);
376 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
377 DRM_ERROR("DPIO read wait timed out\n");
378 goto out_unlock;
379 }
380 val = I915_READ(DPIO_DATA);
381
382 out_unlock:
383 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
384 return val;
385 }
386
387 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
388 u32 val)
389 {
390 unsigned long flags;
391
392 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
393 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
394 DRM_ERROR("DPIO idle wait timed out\n");
395 goto out_unlock;
396 }
397
398 I915_WRITE(DPIO_DATA, val);
399 I915_WRITE(DPIO_REG, reg);
400 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
401 DPIO_BYTE);
402 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
403 DRM_ERROR("DPIO write wait timed out\n");
404
405 out_unlock:
406 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
407 }
408
409 static void vlv_init_dpio(struct drm_device *dev)
410 {
411 struct drm_i915_private *dev_priv = dev->dev_private;
412
413 /* Reset the DPIO config */
414 I915_WRITE(DPIO_CTL, 0);
415 POSTING_READ(DPIO_CTL);
416 I915_WRITE(DPIO_CTL, 1);
417 POSTING_READ(DPIO_CTL);
418 }
419
420 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
421 {
422 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
423 return 1;
424 }
425
426 static const struct dmi_system_id intel_dual_link_lvds[] = {
427 {
428 .callback = intel_dual_link_lvds_callback,
429 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
430 .matches = {
431 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
432 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
433 },
434 },
435 { } /* terminating entry */
436 };
437
438 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
439 unsigned int reg)
440 {
441 unsigned int val;
442
443 /* use the module option value if specified */
444 if (i915_lvds_channel_mode > 0)
445 return i915_lvds_channel_mode == 2;
446
447 if (dmi_check_system(intel_dual_link_lvds))
448 return true;
449
450 if (dev_priv->lvds_val)
451 val = dev_priv->lvds_val;
452 else {
453 /* BIOS should set the proper LVDS register value at boot, but
454 * in reality, it doesn't set the value when the lid is closed;
455 * we need to check "the value to be set" in VBT when LVDS
456 * register is uninitialized.
457 */
458 val = I915_READ(reg);
459 if (!(val & ~LVDS_DETECTED))
460 val = dev_priv->bios_lvds_val;
461 dev_priv->lvds_val = val;
462 }
463 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
464 }
465
466 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
467 int refclk)
468 {
469 struct drm_device *dev = crtc->dev;
470 struct drm_i915_private *dev_priv = dev->dev_private;
471 const intel_limit_t *limit;
472
473 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
474 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
475 /* LVDS dual channel */
476 if (refclk == 100000)
477 limit = &intel_limits_ironlake_dual_lvds_100m;
478 else
479 limit = &intel_limits_ironlake_dual_lvds;
480 } else {
481 if (refclk == 100000)
482 limit = &intel_limits_ironlake_single_lvds_100m;
483 else
484 limit = &intel_limits_ironlake_single_lvds;
485 }
486 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
487 HAS_eDP)
488 limit = &intel_limits_ironlake_display_port;
489 else
490 limit = &intel_limits_ironlake_dac;
491
492 return limit;
493 }
494
495 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
496 {
497 struct drm_device *dev = crtc->dev;
498 struct drm_i915_private *dev_priv = dev->dev_private;
499 const intel_limit_t *limit;
500
501 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
502 if (is_dual_link_lvds(dev_priv, LVDS))
503 /* LVDS with dual channel */
504 limit = &intel_limits_g4x_dual_channel_lvds;
505 else
506 /* LVDS with dual channel */
507 limit = &intel_limits_g4x_single_channel_lvds;
508 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
509 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
510 limit = &intel_limits_g4x_hdmi;
511 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
512 limit = &intel_limits_g4x_sdvo;
513 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
514 limit = &intel_limits_g4x_display_port;
515 } else /* The option is for other outputs */
516 limit = &intel_limits_i9xx_sdvo;
517
518 return limit;
519 }
520
521 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
522 {
523 struct drm_device *dev = crtc->dev;
524 const intel_limit_t *limit;
525
526 if (HAS_PCH_SPLIT(dev))
527 limit = intel_ironlake_limit(crtc, refclk);
528 else if (IS_G4X(dev)) {
529 limit = intel_g4x_limit(crtc);
530 } else if (IS_PINEVIEW(dev)) {
531 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
532 limit = &intel_limits_pineview_lvds;
533 else
534 limit = &intel_limits_pineview_sdvo;
535 } else if (!IS_GEN2(dev)) {
536 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
537 limit = &intel_limits_i9xx_lvds;
538 else
539 limit = &intel_limits_i9xx_sdvo;
540 } else {
541 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
542 limit = &intel_limits_i8xx_lvds;
543 else
544 limit = &intel_limits_i8xx_dvo;
545 }
546 return limit;
547 }
548
549 /* m1 is reserved as 0 in Pineview, n is a ring counter */
550 static void pineview_clock(int refclk, intel_clock_t *clock)
551 {
552 clock->m = clock->m2 + 2;
553 clock->p = clock->p1 * clock->p2;
554 clock->vco = refclk * clock->m / clock->n;
555 clock->dot = clock->vco / clock->p;
556 }
557
558 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
559 {
560 if (IS_PINEVIEW(dev)) {
561 pineview_clock(refclk, clock);
562 return;
563 }
564 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
565 clock->p = clock->p1 * clock->p2;
566 clock->vco = refclk * clock->m / (clock->n + 2);
567 clock->dot = clock->vco / clock->p;
568 }
569
570 /**
571 * Returns whether any output on the specified pipe is of the specified type
572 */
573 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
574 {
575 struct drm_device *dev = crtc->dev;
576 struct drm_mode_config *mode_config = &dev->mode_config;
577 struct intel_encoder *encoder;
578
579 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
580 if (encoder->base.crtc == crtc && encoder->type == type)
581 return true;
582
583 return false;
584 }
585
586 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
587 /**
588 * Returns whether the given set of divisors are valid for a given refclk with
589 * the given connectors.
590 */
591
592 static bool intel_PLL_is_valid(struct drm_device *dev,
593 const intel_limit_t *limit,
594 const intel_clock_t *clock)
595 {
596 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
597 INTELPllInvalid("p1 out of range\n");
598 if (clock->p < limit->p.min || limit->p.max < clock->p)
599 INTELPllInvalid("p out of range\n");
600 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
601 INTELPllInvalid("m2 out of range\n");
602 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
603 INTELPllInvalid("m1 out of range\n");
604 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
605 INTELPllInvalid("m1 <= m2\n");
606 if (clock->m < limit->m.min || limit->m.max < clock->m)
607 INTELPllInvalid("m out of range\n");
608 if (clock->n < limit->n.min || limit->n.max < clock->n)
609 INTELPllInvalid("n out of range\n");
610 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
611 INTELPllInvalid("vco out of range\n");
612 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
613 * connector, etc., rather than just a single range.
614 */
615 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
616 INTELPllInvalid("dot out of range\n");
617
618 return true;
619 }
620
621 static bool
622 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
623 int target, int refclk, intel_clock_t *match_clock,
624 intel_clock_t *best_clock)
625
626 {
627 struct drm_device *dev = crtc->dev;
628 struct drm_i915_private *dev_priv = dev->dev_private;
629 intel_clock_t clock;
630 int err = target;
631
632 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
633 (I915_READ(LVDS)) != 0) {
634 /*
635 * For LVDS, if the panel is on, just rely on its current
636 * settings for dual-channel. We haven't figured out how to
637 * reliably set up different single/dual channel state, if we
638 * even can.
639 */
640 if (is_dual_link_lvds(dev_priv, LVDS))
641 clock.p2 = limit->p2.p2_fast;
642 else
643 clock.p2 = limit->p2.p2_slow;
644 } else {
645 if (target < limit->p2.dot_limit)
646 clock.p2 = limit->p2.p2_slow;
647 else
648 clock.p2 = limit->p2.p2_fast;
649 }
650
651 memset(best_clock, 0, sizeof(*best_clock));
652
653 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
654 clock.m1++) {
655 for (clock.m2 = limit->m2.min;
656 clock.m2 <= limit->m2.max; clock.m2++) {
657 /* m1 is always 0 in Pineview */
658 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
659 break;
660 for (clock.n = limit->n.min;
661 clock.n <= limit->n.max; clock.n++) {
662 for (clock.p1 = limit->p1.min;
663 clock.p1 <= limit->p1.max; clock.p1++) {
664 int this_err;
665
666 intel_clock(dev, refclk, &clock);
667 if (!intel_PLL_is_valid(dev, limit,
668 &clock))
669 continue;
670 if (match_clock &&
671 clock.p != match_clock->p)
672 continue;
673
674 this_err = abs(clock.dot - target);
675 if (this_err < err) {
676 *best_clock = clock;
677 err = this_err;
678 }
679 }
680 }
681 }
682 }
683
684 return (err != target);
685 }
686
687 static bool
688 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
689 int target, int refclk, intel_clock_t *match_clock,
690 intel_clock_t *best_clock)
691 {
692 struct drm_device *dev = crtc->dev;
693 struct drm_i915_private *dev_priv = dev->dev_private;
694 intel_clock_t clock;
695 int max_n;
696 bool found;
697 /* approximately equals target * 0.00585 */
698 int err_most = (target >> 8) + (target >> 9);
699 found = false;
700
701 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
702 int lvds_reg;
703
704 if (HAS_PCH_SPLIT(dev))
705 lvds_reg = PCH_LVDS;
706 else
707 lvds_reg = LVDS;
708 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
709 LVDS_CLKB_POWER_UP)
710 clock.p2 = limit->p2.p2_fast;
711 else
712 clock.p2 = limit->p2.p2_slow;
713 } else {
714 if (target < limit->p2.dot_limit)
715 clock.p2 = limit->p2.p2_slow;
716 else
717 clock.p2 = limit->p2.p2_fast;
718 }
719
720 memset(best_clock, 0, sizeof(*best_clock));
721 max_n = limit->n.max;
722 /* based on hardware requirement, prefer smaller n to precision */
723 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
724 /* based on hardware requirement, prefere larger m1,m2 */
725 for (clock.m1 = limit->m1.max;
726 clock.m1 >= limit->m1.min; clock.m1--) {
727 for (clock.m2 = limit->m2.max;
728 clock.m2 >= limit->m2.min; clock.m2--) {
729 for (clock.p1 = limit->p1.max;
730 clock.p1 >= limit->p1.min; clock.p1--) {
731 int this_err;
732
733 intel_clock(dev, refclk, &clock);
734 if (!intel_PLL_is_valid(dev, limit,
735 &clock))
736 continue;
737 if (match_clock &&
738 clock.p != match_clock->p)
739 continue;
740
741 this_err = abs(clock.dot - target);
742 if (this_err < err_most) {
743 *best_clock = clock;
744 err_most = this_err;
745 max_n = clock.n;
746 found = true;
747 }
748 }
749 }
750 }
751 }
752 return found;
753 }
754
755 static bool
756 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
757 int target, int refclk, intel_clock_t *match_clock,
758 intel_clock_t *best_clock)
759 {
760 struct drm_device *dev = crtc->dev;
761 intel_clock_t clock;
762
763 if (target < 200000) {
764 clock.n = 1;
765 clock.p1 = 2;
766 clock.p2 = 10;
767 clock.m1 = 12;
768 clock.m2 = 9;
769 } else {
770 clock.n = 2;
771 clock.p1 = 1;
772 clock.p2 = 10;
773 clock.m1 = 14;
774 clock.m2 = 8;
775 }
776 intel_clock(dev, refclk, &clock);
777 memcpy(best_clock, &clock, sizeof(intel_clock_t));
778 return true;
779 }
780
781 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
782 static bool
783 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
784 int target, int refclk, intel_clock_t *match_clock,
785 intel_clock_t *best_clock)
786 {
787 intel_clock_t clock;
788 if (target < 200000) {
789 clock.p1 = 2;
790 clock.p2 = 10;
791 clock.n = 2;
792 clock.m1 = 23;
793 clock.m2 = 8;
794 } else {
795 clock.p1 = 1;
796 clock.p2 = 10;
797 clock.n = 1;
798 clock.m1 = 14;
799 clock.m2 = 2;
800 }
801 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
802 clock.p = (clock.p1 * clock.p2);
803 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
804 clock.vco = 0;
805 memcpy(best_clock, &clock, sizeof(intel_clock_t));
806 return true;
807 }
808
809 /**
810 * intel_wait_for_vblank - wait for vblank on a given pipe
811 * @dev: drm device
812 * @pipe: pipe to wait for
813 *
814 * Wait for vblank to occur on a given pipe. Needed for various bits of
815 * mode setting code.
816 */
817 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
818 {
819 struct drm_i915_private *dev_priv = dev->dev_private;
820 int pipestat_reg = PIPESTAT(pipe);
821
822 /* Clear existing vblank status. Note this will clear any other
823 * sticky status fields as well.
824 *
825 * This races with i915_driver_irq_handler() with the result
826 * that either function could miss a vblank event. Here it is not
827 * fatal, as we will either wait upon the next vblank interrupt or
828 * timeout. Generally speaking intel_wait_for_vblank() is only
829 * called during modeset at which time the GPU should be idle and
830 * should *not* be performing page flips and thus not waiting on
831 * vblanks...
832 * Currently, the result of us stealing a vblank from the irq
833 * handler is that a single frame will be skipped during swapbuffers.
834 */
835 I915_WRITE(pipestat_reg,
836 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
837
838 /* Wait for vblank interrupt bit to set */
839 if (wait_for(I915_READ(pipestat_reg) &
840 PIPE_VBLANK_INTERRUPT_STATUS,
841 50))
842 DRM_DEBUG_KMS("vblank wait timed out\n");
843 }
844
845 /*
846 * intel_wait_for_pipe_off - wait for pipe to turn off
847 * @dev: drm device
848 * @pipe: pipe to wait for
849 *
850 * After disabling a pipe, we can't wait for vblank in the usual way,
851 * spinning on the vblank interrupt status bit, since we won't actually
852 * see an interrupt when the pipe is disabled.
853 *
854 * On Gen4 and above:
855 * wait for the pipe register state bit to turn off
856 *
857 * Otherwise:
858 * wait for the display line value to settle (it usually
859 * ends up stopping at the start of the next frame).
860 *
861 */
862 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
863 {
864 struct drm_i915_private *dev_priv = dev->dev_private;
865
866 if (INTEL_INFO(dev)->gen >= 4) {
867 int reg = PIPECONF(pipe);
868
869 /* Wait for the Pipe State to go off */
870 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
871 100))
872 DRM_DEBUG_KMS("pipe_off wait timed out\n");
873 } else {
874 u32 last_line;
875 int reg = PIPEDSL(pipe);
876 unsigned long timeout = jiffies + msecs_to_jiffies(100);
877
878 /* Wait for the display line to settle */
879 do {
880 last_line = I915_READ(reg) & DSL_LINEMASK;
881 mdelay(5);
882 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
883 time_after(timeout, jiffies));
884 if (time_after(jiffies, timeout))
885 DRM_DEBUG_KMS("pipe_off wait timed out\n");
886 }
887 }
888
889 static const char *state_string(bool enabled)
890 {
891 return enabled ? "on" : "off";
892 }
893
894 /* Only for pre-ILK configs */
895 static void assert_pll(struct drm_i915_private *dev_priv,
896 enum pipe pipe, bool state)
897 {
898 int reg;
899 u32 val;
900 bool cur_state;
901
902 reg = DPLL(pipe);
903 val = I915_READ(reg);
904 cur_state = !!(val & DPLL_VCO_ENABLE);
905 WARN(cur_state != state,
906 "PLL state assertion failure (expected %s, current %s)\n",
907 state_string(state), state_string(cur_state));
908 }
909 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
910 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
911
912 /* For ILK+ */
913 static void assert_pch_pll(struct drm_i915_private *dev_priv,
914 enum pipe pipe, bool state)
915 {
916 int reg;
917 u32 val;
918 bool cur_state;
919
920 if (HAS_PCH_CPT(dev_priv->dev)) {
921 u32 pch_dpll;
922
923 pch_dpll = I915_READ(PCH_DPLL_SEL);
924
925 /* Make sure the selected PLL is enabled to the transcoder */
926 WARN(!((pch_dpll >> (4 * pipe)) & 8),
927 "transcoder %d PLL not enabled\n", pipe);
928
929 /* Convert the transcoder pipe number to a pll pipe number */
930 pipe = (pch_dpll >> (4 * pipe)) & 1;
931 }
932
933 reg = PCH_DPLL(pipe);
934 val = I915_READ(reg);
935 cur_state = !!(val & DPLL_VCO_ENABLE);
936 WARN(cur_state != state,
937 "PCH PLL state assertion failure (expected %s, current %s)\n",
938 state_string(state), state_string(cur_state));
939 }
940 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
941 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
942
943 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
944 enum pipe pipe, bool state)
945 {
946 int reg;
947 u32 val;
948 bool cur_state;
949
950 reg = FDI_TX_CTL(pipe);
951 val = I915_READ(reg);
952 cur_state = !!(val & FDI_TX_ENABLE);
953 WARN(cur_state != state,
954 "FDI TX state assertion failure (expected %s, current %s)\n",
955 state_string(state), state_string(cur_state));
956 }
957 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
958 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
959
960 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
961 enum pipe pipe, bool state)
962 {
963 int reg;
964 u32 val;
965 bool cur_state;
966
967 reg = FDI_RX_CTL(pipe);
968 val = I915_READ(reg);
969 cur_state = !!(val & FDI_RX_ENABLE);
970 WARN(cur_state != state,
971 "FDI RX state assertion failure (expected %s, current %s)\n",
972 state_string(state), state_string(cur_state));
973 }
974 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
975 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
976
977 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
978 enum pipe pipe)
979 {
980 int reg;
981 u32 val;
982
983 /* ILK FDI PLL is always enabled */
984 if (dev_priv->info->gen == 5)
985 return;
986
987 reg = FDI_TX_CTL(pipe);
988 val = I915_READ(reg);
989 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
990 }
991
992 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
993 enum pipe pipe)
994 {
995 int reg;
996 u32 val;
997
998 reg = FDI_RX_CTL(pipe);
999 val = I915_READ(reg);
1000 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1001 }
1002
1003 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1004 enum pipe pipe)
1005 {
1006 int pp_reg, lvds_reg;
1007 u32 val;
1008 enum pipe panel_pipe = PIPE_A;
1009 bool locked = true;
1010
1011 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1012 pp_reg = PCH_PP_CONTROL;
1013 lvds_reg = PCH_LVDS;
1014 } else {
1015 pp_reg = PP_CONTROL;
1016 lvds_reg = LVDS;
1017 }
1018
1019 val = I915_READ(pp_reg);
1020 if (!(val & PANEL_POWER_ON) ||
1021 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1022 locked = false;
1023
1024 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1025 panel_pipe = PIPE_B;
1026
1027 WARN(panel_pipe == pipe && locked,
1028 "panel assertion failure, pipe %c regs locked\n",
1029 pipe_name(pipe));
1030 }
1031
1032 void assert_pipe(struct drm_i915_private *dev_priv,
1033 enum pipe pipe, bool state)
1034 {
1035 int reg;
1036 u32 val;
1037 bool cur_state;
1038
1039 /* if we need the pipe A quirk it must be always on */
1040 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1041 state = true;
1042
1043 reg = PIPECONF(pipe);
1044 val = I915_READ(reg);
1045 cur_state = !!(val & PIPECONF_ENABLE);
1046 WARN(cur_state != state,
1047 "pipe %c assertion failure (expected %s, current %s)\n",
1048 pipe_name(pipe), state_string(state), state_string(cur_state));
1049 }
1050
1051 static void assert_plane(struct drm_i915_private *dev_priv,
1052 enum plane plane, bool state)
1053 {
1054 int reg;
1055 u32 val;
1056 bool cur_state;
1057
1058 reg = DSPCNTR(plane);
1059 val = I915_READ(reg);
1060 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1061 WARN(cur_state != state,
1062 "plane %c assertion failure (expected %s, current %s)\n",
1063 plane_name(plane), state_string(state), state_string(cur_state));
1064 }
1065
1066 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1067 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1068
1069 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1070 enum pipe pipe)
1071 {
1072 int reg, i;
1073 u32 val;
1074 int cur_pipe;
1075
1076 /* Planes are fixed to pipes on ILK+ */
1077 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1078 reg = DSPCNTR(pipe);
1079 val = I915_READ(reg);
1080 WARN((val & DISPLAY_PLANE_ENABLE),
1081 "plane %c assertion failure, should be disabled but not\n",
1082 plane_name(pipe));
1083 return;
1084 }
1085
1086 /* Need to check both planes against the pipe */
1087 for (i = 0; i < 2; i++) {
1088 reg = DSPCNTR(i);
1089 val = I915_READ(reg);
1090 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1091 DISPPLANE_SEL_PIPE_SHIFT;
1092 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1093 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1094 plane_name(i), pipe_name(pipe));
1095 }
1096 }
1097
1098 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1099 {
1100 u32 val;
1101 bool enabled;
1102
1103 val = I915_READ(PCH_DREF_CONTROL);
1104 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1105 DREF_SUPERSPREAD_SOURCE_MASK));
1106 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1107 }
1108
1109 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1110 enum pipe pipe)
1111 {
1112 int reg;
1113 u32 val;
1114 bool enabled;
1115
1116 reg = TRANSCONF(pipe);
1117 val = I915_READ(reg);
1118 enabled = !!(val & TRANS_ENABLE);
1119 WARN(enabled,
1120 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1121 pipe_name(pipe));
1122 }
1123
1124 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1125 enum pipe pipe, u32 port_sel, u32 val)
1126 {
1127 if ((val & DP_PORT_EN) == 0)
1128 return false;
1129
1130 if (HAS_PCH_CPT(dev_priv->dev)) {
1131 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1132 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1133 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1134 return false;
1135 } else {
1136 if ((val & DP_PIPE_MASK) != (pipe << 30))
1137 return false;
1138 }
1139 return true;
1140 }
1141
1142 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1143 enum pipe pipe, u32 val)
1144 {
1145 if ((val & PORT_ENABLE) == 0)
1146 return false;
1147
1148 if (HAS_PCH_CPT(dev_priv->dev)) {
1149 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1150 return false;
1151 } else {
1152 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1153 return false;
1154 }
1155 return true;
1156 }
1157
1158 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1159 enum pipe pipe, u32 val)
1160 {
1161 if ((val & LVDS_PORT_EN) == 0)
1162 return false;
1163
1164 if (HAS_PCH_CPT(dev_priv->dev)) {
1165 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1166 return false;
1167 } else {
1168 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1169 return false;
1170 }
1171 return true;
1172 }
1173
1174 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1175 enum pipe pipe, u32 val)
1176 {
1177 if ((val & ADPA_DAC_ENABLE) == 0)
1178 return false;
1179 if (HAS_PCH_CPT(dev_priv->dev)) {
1180 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1181 return false;
1182 } else {
1183 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1184 return false;
1185 }
1186 return true;
1187 }
1188
1189 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1190 enum pipe pipe, int reg, u32 port_sel)
1191 {
1192 u32 val = I915_READ(reg);
1193 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1194 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1195 reg, pipe_name(pipe));
1196 }
1197
1198 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1199 enum pipe pipe, int reg)
1200 {
1201 u32 val = I915_READ(reg);
1202 WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
1203 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1204 reg, pipe_name(pipe));
1205 }
1206
1207 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1208 enum pipe pipe)
1209 {
1210 int reg;
1211 u32 val;
1212
1213 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1214 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1215 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1216
1217 reg = PCH_ADPA;
1218 val = I915_READ(reg);
1219 WARN(adpa_pipe_enabled(dev_priv, val, pipe),
1220 "PCH VGA enabled on transcoder %c, should be disabled\n",
1221 pipe_name(pipe));
1222
1223 reg = PCH_LVDS;
1224 val = I915_READ(reg);
1225 WARN(lvds_pipe_enabled(dev_priv, val, pipe),
1226 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1227 pipe_name(pipe));
1228
1229 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1230 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1231 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1232 }
1233
1234 /**
1235 * intel_enable_pll - enable a PLL
1236 * @dev_priv: i915 private structure
1237 * @pipe: pipe PLL to enable
1238 *
1239 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1240 * make sure the PLL reg is writable first though, since the panel write
1241 * protect mechanism may be enabled.
1242 *
1243 * Note! This is for pre-ILK only.
1244 */
1245 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1246 {
1247 int reg;
1248 u32 val;
1249
1250 /* No really, not for ILK+ */
1251 BUG_ON(dev_priv->info->gen >= 5);
1252
1253 /* PLL is protected by panel, make sure we can write it */
1254 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1255 assert_panel_unlocked(dev_priv, pipe);
1256
1257 reg = DPLL(pipe);
1258 val = I915_READ(reg);
1259 val |= DPLL_VCO_ENABLE;
1260
1261 /* We do this three times for luck */
1262 I915_WRITE(reg, val);
1263 POSTING_READ(reg);
1264 udelay(150); /* wait for warmup */
1265 I915_WRITE(reg, val);
1266 POSTING_READ(reg);
1267 udelay(150); /* wait for warmup */
1268 I915_WRITE(reg, val);
1269 POSTING_READ(reg);
1270 udelay(150); /* wait for warmup */
1271 }
1272
1273 /**
1274 * intel_disable_pll - disable a PLL
1275 * @dev_priv: i915 private structure
1276 * @pipe: pipe PLL to disable
1277 *
1278 * Disable the PLL for @pipe, making sure the pipe is off first.
1279 *
1280 * Note! This is for pre-ILK only.
1281 */
1282 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1283 {
1284 int reg;
1285 u32 val;
1286
1287 /* Don't disable pipe A or pipe A PLLs if needed */
1288 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1289 return;
1290
1291 /* Make sure the pipe isn't still relying on us */
1292 assert_pipe_disabled(dev_priv, pipe);
1293
1294 reg = DPLL(pipe);
1295 val = I915_READ(reg);
1296 val &= ~DPLL_VCO_ENABLE;
1297 I915_WRITE(reg, val);
1298 POSTING_READ(reg);
1299 }
1300
1301 /**
1302 * intel_enable_pch_pll - enable PCH PLL
1303 * @dev_priv: i915 private structure
1304 * @pipe: pipe PLL to enable
1305 *
1306 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1307 * drives the transcoder clock.
1308 */
1309 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1310 enum pipe pipe)
1311 {
1312 int reg;
1313 u32 val;
1314
1315 if (pipe > 1)
1316 return;
1317
1318 /* PCH only available on ILK+ */
1319 BUG_ON(dev_priv->info->gen < 5);
1320
1321 /* PCH refclock must be enabled first */
1322 assert_pch_refclk_enabled(dev_priv);
1323
1324 reg = PCH_DPLL(pipe);
1325 val = I915_READ(reg);
1326 val |= DPLL_VCO_ENABLE;
1327 I915_WRITE(reg, val);
1328 POSTING_READ(reg);
1329 udelay(200);
1330 }
1331
1332 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1333 enum pipe pipe)
1334 {
1335 int reg;
1336 u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL,
1337 pll_sel = TRANSC_DPLL_ENABLE;
1338
1339 if (pipe > 1)
1340 return;
1341
1342 /* PCH only available on ILK+ */
1343 BUG_ON(dev_priv->info->gen < 5);
1344
1345 /* Make sure transcoder isn't still depending on us */
1346 assert_transcoder_disabled(dev_priv, pipe);
1347
1348 if (pipe == 0)
1349 pll_sel |= TRANSC_DPLLA_SEL;
1350 else if (pipe == 1)
1351 pll_sel |= TRANSC_DPLLB_SEL;
1352
1353
1354 if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel)
1355 return;
1356
1357 reg = PCH_DPLL(pipe);
1358 val = I915_READ(reg);
1359 val &= ~DPLL_VCO_ENABLE;
1360 I915_WRITE(reg, val);
1361 POSTING_READ(reg);
1362 udelay(200);
1363 }
1364
1365 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1366 enum pipe pipe)
1367 {
1368 int reg;
1369 u32 val, pipeconf_val;
1370 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1371
1372 /* PCH only available on ILK+ */
1373 BUG_ON(dev_priv->info->gen < 5);
1374
1375 /* Make sure PCH DPLL is enabled */
1376 assert_pch_pll_enabled(dev_priv, pipe);
1377
1378 /* FDI must be feeding us bits for PCH ports */
1379 assert_fdi_tx_enabled(dev_priv, pipe);
1380 assert_fdi_rx_enabled(dev_priv, pipe);
1381
1382 reg = TRANSCONF(pipe);
1383 val = I915_READ(reg);
1384 pipeconf_val = I915_READ(PIPECONF(pipe));
1385
1386 if (HAS_PCH_IBX(dev_priv->dev)) {
1387 /*
1388 * make the BPC in transcoder be consistent with
1389 * that in pipeconf reg.
1390 */
1391 val &= ~PIPE_BPC_MASK;
1392 val |= pipeconf_val & PIPE_BPC_MASK;
1393 }
1394
1395 val &= ~TRANS_INTERLACE_MASK;
1396 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1397 if (HAS_PCH_IBX(dev_priv->dev) &&
1398 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1399 val |= TRANS_LEGACY_INTERLACED_ILK;
1400 else
1401 val |= TRANS_INTERLACED;
1402 else
1403 val |= TRANS_PROGRESSIVE;
1404
1405 I915_WRITE(reg, val | TRANS_ENABLE);
1406 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1407 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1408 }
1409
1410 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1411 enum pipe pipe)
1412 {
1413 int reg;
1414 u32 val;
1415
1416 /* FDI relies on the transcoder */
1417 assert_fdi_tx_disabled(dev_priv, pipe);
1418 assert_fdi_rx_disabled(dev_priv, pipe);
1419
1420 /* Ports must be off as well */
1421 assert_pch_ports_disabled(dev_priv, pipe);
1422
1423 reg = TRANSCONF(pipe);
1424 val = I915_READ(reg);
1425 val &= ~TRANS_ENABLE;
1426 I915_WRITE(reg, val);
1427 /* wait for PCH transcoder off, transcoder state */
1428 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1429 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1430 }
1431
1432 /**
1433 * intel_enable_pipe - enable a pipe, asserting requirements
1434 * @dev_priv: i915 private structure
1435 * @pipe: pipe to enable
1436 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1437 *
1438 * Enable @pipe, making sure that various hardware specific requirements
1439 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1440 *
1441 * @pipe should be %PIPE_A or %PIPE_B.
1442 *
1443 * Will wait until the pipe is actually running (i.e. first vblank) before
1444 * returning.
1445 */
1446 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1447 bool pch_port)
1448 {
1449 int reg;
1450 u32 val;
1451
1452 /*
1453 * A pipe without a PLL won't actually be able to drive bits from
1454 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1455 * need the check.
1456 */
1457 if (!HAS_PCH_SPLIT(dev_priv->dev))
1458 assert_pll_enabled(dev_priv, pipe);
1459 else {
1460 if (pch_port) {
1461 /* if driving the PCH, we need FDI enabled */
1462 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1463 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1464 }
1465 /* FIXME: assert CPU port conditions for SNB+ */
1466 }
1467
1468 reg = PIPECONF(pipe);
1469 val = I915_READ(reg);
1470 if (val & PIPECONF_ENABLE)
1471 return;
1472
1473 I915_WRITE(reg, val | PIPECONF_ENABLE);
1474 intel_wait_for_vblank(dev_priv->dev, pipe);
1475 }
1476
1477 /**
1478 * intel_disable_pipe - disable a pipe, asserting requirements
1479 * @dev_priv: i915 private structure
1480 * @pipe: pipe to disable
1481 *
1482 * Disable @pipe, making sure that various hardware specific requirements
1483 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1484 *
1485 * @pipe should be %PIPE_A or %PIPE_B.
1486 *
1487 * Will wait until the pipe has shut down before returning.
1488 */
1489 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1490 enum pipe pipe)
1491 {
1492 int reg;
1493 u32 val;
1494
1495 /*
1496 * Make sure planes won't keep trying to pump pixels to us,
1497 * or we might hang the display.
1498 */
1499 assert_planes_disabled(dev_priv, pipe);
1500
1501 /* Don't disable pipe A or pipe A PLLs if needed */
1502 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1503 return;
1504
1505 reg = PIPECONF(pipe);
1506 val = I915_READ(reg);
1507 if ((val & PIPECONF_ENABLE) == 0)
1508 return;
1509
1510 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1511 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1512 }
1513
1514 /*
1515 * Plane regs are double buffered, going from enabled->disabled needs a
1516 * trigger in order to latch. The display address reg provides this.
1517 */
1518 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1519 enum plane plane)
1520 {
1521 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1522 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1523 }
1524
1525 /**
1526 * intel_enable_plane - enable a display plane on a given pipe
1527 * @dev_priv: i915 private structure
1528 * @plane: plane to enable
1529 * @pipe: pipe being fed
1530 *
1531 * Enable @plane on @pipe, making sure that @pipe is running first.
1532 */
1533 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1534 enum plane plane, enum pipe pipe)
1535 {
1536 int reg;
1537 u32 val;
1538
1539 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1540 assert_pipe_enabled(dev_priv, pipe);
1541
1542 reg = DSPCNTR(plane);
1543 val = I915_READ(reg);
1544 if (val & DISPLAY_PLANE_ENABLE)
1545 return;
1546
1547 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1548 intel_flush_display_plane(dev_priv, plane);
1549 intel_wait_for_vblank(dev_priv->dev, pipe);
1550 }
1551
1552 /**
1553 * intel_disable_plane - disable a display plane
1554 * @dev_priv: i915 private structure
1555 * @plane: plane to disable
1556 * @pipe: pipe consuming the data
1557 *
1558 * Disable @plane; should be an independent operation.
1559 */
1560 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1561 enum plane plane, enum pipe pipe)
1562 {
1563 int reg;
1564 u32 val;
1565
1566 reg = DSPCNTR(plane);
1567 val = I915_READ(reg);
1568 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1569 return;
1570
1571 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1572 intel_flush_display_plane(dev_priv, plane);
1573 intel_wait_for_vblank(dev_priv->dev, pipe);
1574 }
1575
1576 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1577 enum pipe pipe, int reg, u32 port_sel)
1578 {
1579 u32 val = I915_READ(reg);
1580 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1581 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1582 I915_WRITE(reg, val & ~DP_PORT_EN);
1583 }
1584 }
1585
1586 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1587 enum pipe pipe, int reg)
1588 {
1589 u32 val = I915_READ(reg);
1590 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1591 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1592 reg, pipe);
1593 I915_WRITE(reg, val & ~PORT_ENABLE);
1594 }
1595 }
1596
1597 /* Disable any ports connected to this transcoder */
1598 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1599 enum pipe pipe)
1600 {
1601 u32 reg, val;
1602
1603 val = I915_READ(PCH_PP_CONTROL);
1604 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1605
1606 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1607 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1608 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1609
1610 reg = PCH_ADPA;
1611 val = I915_READ(reg);
1612 if (adpa_pipe_enabled(dev_priv, val, pipe))
1613 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1614
1615 reg = PCH_LVDS;
1616 val = I915_READ(reg);
1617 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1618 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1619 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1620 POSTING_READ(reg);
1621 udelay(100);
1622 }
1623
1624 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1625 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1626 disable_pch_hdmi(dev_priv, pipe, HDMID);
1627 }
1628
1629 int
1630 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1631 struct drm_i915_gem_object *obj,
1632 struct intel_ring_buffer *pipelined)
1633 {
1634 struct drm_i915_private *dev_priv = dev->dev_private;
1635 u32 alignment;
1636 int ret;
1637
1638 switch (obj->tiling_mode) {
1639 case I915_TILING_NONE:
1640 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1641 alignment = 128 * 1024;
1642 else if (INTEL_INFO(dev)->gen >= 4)
1643 alignment = 4 * 1024;
1644 else
1645 alignment = 64 * 1024;
1646 break;
1647 case I915_TILING_X:
1648 /* pin() will align the object as required by fence */
1649 alignment = 0;
1650 break;
1651 case I915_TILING_Y:
1652 /* FIXME: Is this true? */
1653 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1654 return -EINVAL;
1655 default:
1656 BUG();
1657 }
1658
1659 dev_priv->mm.interruptible = false;
1660 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1661 if (ret)
1662 goto err_interruptible;
1663
1664 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1665 * fence, whereas 965+ only requires a fence if using
1666 * framebuffer compression. For simplicity, we always install
1667 * a fence as the cost is not that onerous.
1668 */
1669 ret = i915_gem_object_get_fence(obj);
1670 if (ret)
1671 goto err_unpin;
1672
1673 i915_gem_object_pin_fence(obj);
1674
1675 dev_priv->mm.interruptible = true;
1676 return 0;
1677
1678 err_unpin:
1679 i915_gem_object_unpin(obj);
1680 err_interruptible:
1681 dev_priv->mm.interruptible = true;
1682 return ret;
1683 }
1684
1685 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1686 {
1687 i915_gem_object_unpin_fence(obj);
1688 i915_gem_object_unpin(obj);
1689 }
1690
1691 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1692 int x, int y)
1693 {
1694 struct drm_device *dev = crtc->dev;
1695 struct drm_i915_private *dev_priv = dev->dev_private;
1696 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1697 struct intel_framebuffer *intel_fb;
1698 struct drm_i915_gem_object *obj;
1699 int plane = intel_crtc->plane;
1700 unsigned long Start, Offset;
1701 u32 dspcntr;
1702 u32 reg;
1703
1704 switch (plane) {
1705 case 0:
1706 case 1:
1707 break;
1708 default:
1709 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1710 return -EINVAL;
1711 }
1712
1713 intel_fb = to_intel_framebuffer(fb);
1714 obj = intel_fb->obj;
1715
1716 reg = DSPCNTR(plane);
1717 dspcntr = I915_READ(reg);
1718 /* Mask out pixel format bits in case we change it */
1719 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1720 switch (fb->bits_per_pixel) {
1721 case 8:
1722 dspcntr |= DISPPLANE_8BPP;
1723 break;
1724 case 16:
1725 if (fb->depth == 15)
1726 dspcntr |= DISPPLANE_15_16BPP;
1727 else
1728 dspcntr |= DISPPLANE_16BPP;
1729 break;
1730 case 24:
1731 case 32:
1732 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1733 break;
1734 default:
1735 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1736 return -EINVAL;
1737 }
1738 if (INTEL_INFO(dev)->gen >= 4) {
1739 if (obj->tiling_mode != I915_TILING_NONE)
1740 dspcntr |= DISPPLANE_TILED;
1741 else
1742 dspcntr &= ~DISPPLANE_TILED;
1743 }
1744
1745 I915_WRITE(reg, dspcntr);
1746
1747 Start = obj->gtt_offset;
1748 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1749
1750 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1751 Start, Offset, x, y, fb->pitches[0]);
1752 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1753 if (INTEL_INFO(dev)->gen >= 4) {
1754 I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
1755 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1756 I915_WRITE(DSPADDR(plane), Offset);
1757 } else
1758 I915_WRITE(DSPADDR(plane), Start + Offset);
1759 POSTING_READ(reg);
1760
1761 return 0;
1762 }
1763
1764 static int ironlake_update_plane(struct drm_crtc *crtc,
1765 struct drm_framebuffer *fb, int x, int y)
1766 {
1767 struct drm_device *dev = crtc->dev;
1768 struct drm_i915_private *dev_priv = dev->dev_private;
1769 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1770 struct intel_framebuffer *intel_fb;
1771 struct drm_i915_gem_object *obj;
1772 int plane = intel_crtc->plane;
1773 unsigned long Start, Offset;
1774 u32 dspcntr;
1775 u32 reg;
1776
1777 switch (plane) {
1778 case 0:
1779 case 1:
1780 case 2:
1781 break;
1782 default:
1783 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1784 return -EINVAL;
1785 }
1786
1787 intel_fb = to_intel_framebuffer(fb);
1788 obj = intel_fb->obj;
1789
1790 reg = DSPCNTR(plane);
1791 dspcntr = I915_READ(reg);
1792 /* Mask out pixel format bits in case we change it */
1793 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1794 switch (fb->bits_per_pixel) {
1795 case 8:
1796 dspcntr |= DISPPLANE_8BPP;
1797 break;
1798 case 16:
1799 if (fb->depth != 16)
1800 return -EINVAL;
1801
1802 dspcntr |= DISPPLANE_16BPP;
1803 break;
1804 case 24:
1805 case 32:
1806 if (fb->depth == 24)
1807 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1808 else if (fb->depth == 30)
1809 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1810 else
1811 return -EINVAL;
1812 break;
1813 default:
1814 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1815 return -EINVAL;
1816 }
1817
1818 if (obj->tiling_mode != I915_TILING_NONE)
1819 dspcntr |= DISPPLANE_TILED;
1820 else
1821 dspcntr &= ~DISPPLANE_TILED;
1822
1823 /* must disable */
1824 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1825
1826 I915_WRITE(reg, dspcntr);
1827
1828 Start = obj->gtt_offset;
1829 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1830
1831 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1832 Start, Offset, x, y, fb->pitches[0]);
1833 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1834 I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
1835 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1836 I915_WRITE(DSPADDR(plane), Offset);
1837 POSTING_READ(reg);
1838
1839 return 0;
1840 }
1841
1842 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1843 static int
1844 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1845 int x, int y, enum mode_set_atomic state)
1846 {
1847 struct drm_device *dev = crtc->dev;
1848 struct drm_i915_private *dev_priv = dev->dev_private;
1849
1850 if (dev_priv->display.disable_fbc)
1851 dev_priv->display.disable_fbc(dev);
1852 intel_increase_pllclock(crtc);
1853
1854 return dev_priv->display.update_plane(crtc, fb, x, y);
1855 }
1856
1857 static int
1858 intel_finish_fb(struct drm_framebuffer *old_fb)
1859 {
1860 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1861 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1862 bool was_interruptible = dev_priv->mm.interruptible;
1863 int ret;
1864
1865 wait_event(dev_priv->pending_flip_queue,
1866 atomic_read(&dev_priv->mm.wedged) ||
1867 atomic_read(&obj->pending_flip) == 0);
1868
1869 /* Big Hammer, we also need to ensure that any pending
1870 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1871 * current scanout is retired before unpinning the old
1872 * framebuffer.
1873 *
1874 * This should only fail upon a hung GPU, in which case we
1875 * can safely continue.
1876 */
1877 dev_priv->mm.interruptible = false;
1878 ret = i915_gem_object_finish_gpu(obj);
1879 dev_priv->mm.interruptible = was_interruptible;
1880
1881 return ret;
1882 }
1883
1884 static int
1885 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1886 struct drm_framebuffer *old_fb)
1887 {
1888 struct drm_device *dev = crtc->dev;
1889 struct drm_i915_private *dev_priv = dev->dev_private;
1890 struct drm_i915_master_private *master_priv;
1891 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1892 int ret;
1893
1894 /* no fb bound */
1895 if (!crtc->fb) {
1896 DRM_ERROR("No FB bound\n");
1897 return 0;
1898 }
1899
1900 switch (intel_crtc->plane) {
1901 case 0:
1902 case 1:
1903 break;
1904 case 2:
1905 if (IS_IVYBRIDGE(dev))
1906 break;
1907 /* fall through otherwise */
1908 default:
1909 DRM_ERROR("no plane for crtc\n");
1910 return -EINVAL;
1911 }
1912
1913 mutex_lock(&dev->struct_mutex);
1914 ret = intel_pin_and_fence_fb_obj(dev,
1915 to_intel_framebuffer(crtc->fb)->obj,
1916 NULL);
1917 if (ret != 0) {
1918 mutex_unlock(&dev->struct_mutex);
1919 DRM_ERROR("pin & fence failed\n");
1920 return ret;
1921 }
1922
1923 if (old_fb)
1924 intel_finish_fb(old_fb);
1925
1926 ret = dev_priv->display.update_plane(crtc, crtc->fb, x, y);
1927 if (ret) {
1928 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
1929 mutex_unlock(&dev->struct_mutex);
1930 DRM_ERROR("failed to update base address\n");
1931 return ret;
1932 }
1933
1934 if (old_fb) {
1935 intel_wait_for_vblank(dev, intel_crtc->pipe);
1936 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
1937 }
1938
1939 intel_update_fbc(dev);
1940 mutex_unlock(&dev->struct_mutex);
1941
1942 if (!dev->primary->master)
1943 return 0;
1944
1945 master_priv = dev->primary->master->driver_priv;
1946 if (!master_priv->sarea_priv)
1947 return 0;
1948
1949 if (intel_crtc->pipe) {
1950 master_priv->sarea_priv->pipeB_x = x;
1951 master_priv->sarea_priv->pipeB_y = y;
1952 } else {
1953 master_priv->sarea_priv->pipeA_x = x;
1954 master_priv->sarea_priv->pipeA_y = y;
1955 }
1956
1957 return 0;
1958 }
1959
1960 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
1961 {
1962 struct drm_device *dev = crtc->dev;
1963 struct drm_i915_private *dev_priv = dev->dev_private;
1964 u32 dpa_ctl;
1965
1966 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1967 dpa_ctl = I915_READ(DP_A);
1968 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1969
1970 if (clock < 200000) {
1971 u32 temp;
1972 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1973 /* workaround for 160Mhz:
1974 1) program 0x4600c bits 15:0 = 0x8124
1975 2) program 0x46010 bit 0 = 1
1976 3) program 0x46034 bit 24 = 1
1977 4) program 0x64000 bit 14 = 1
1978 */
1979 temp = I915_READ(0x4600c);
1980 temp &= 0xffff0000;
1981 I915_WRITE(0x4600c, temp | 0x8124);
1982
1983 temp = I915_READ(0x46010);
1984 I915_WRITE(0x46010, temp | 1);
1985
1986 temp = I915_READ(0x46034);
1987 I915_WRITE(0x46034, temp | (1 << 24));
1988 } else {
1989 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1990 }
1991 I915_WRITE(DP_A, dpa_ctl);
1992
1993 POSTING_READ(DP_A);
1994 udelay(500);
1995 }
1996
1997 static void intel_fdi_normal_train(struct drm_crtc *crtc)
1998 {
1999 struct drm_device *dev = crtc->dev;
2000 struct drm_i915_private *dev_priv = dev->dev_private;
2001 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2002 int pipe = intel_crtc->pipe;
2003 u32 reg, temp;
2004
2005 /* enable normal train */
2006 reg = FDI_TX_CTL(pipe);
2007 temp = I915_READ(reg);
2008 if (IS_IVYBRIDGE(dev)) {
2009 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2010 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2011 } else {
2012 temp &= ~FDI_LINK_TRAIN_NONE;
2013 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2014 }
2015 I915_WRITE(reg, temp);
2016
2017 reg = FDI_RX_CTL(pipe);
2018 temp = I915_READ(reg);
2019 if (HAS_PCH_CPT(dev)) {
2020 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2021 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2022 } else {
2023 temp &= ~FDI_LINK_TRAIN_NONE;
2024 temp |= FDI_LINK_TRAIN_NONE;
2025 }
2026 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2027
2028 /* wait one idle pattern time */
2029 POSTING_READ(reg);
2030 udelay(1000);
2031
2032 /* IVB wants error correction enabled */
2033 if (IS_IVYBRIDGE(dev))
2034 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2035 FDI_FE_ERRC_ENABLE);
2036 }
2037
2038 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2039 {
2040 struct drm_i915_private *dev_priv = dev->dev_private;
2041 u32 flags = I915_READ(SOUTH_CHICKEN1);
2042
2043 flags |= FDI_PHASE_SYNC_OVR(pipe);
2044 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2045 flags |= FDI_PHASE_SYNC_EN(pipe);
2046 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2047 POSTING_READ(SOUTH_CHICKEN1);
2048 }
2049
2050 /* The FDI link training functions for ILK/Ibexpeak. */
2051 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2052 {
2053 struct drm_device *dev = crtc->dev;
2054 struct drm_i915_private *dev_priv = dev->dev_private;
2055 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2056 int pipe = intel_crtc->pipe;
2057 int plane = intel_crtc->plane;
2058 u32 reg, temp, tries;
2059
2060 /* FDI needs bits from pipe & plane first */
2061 assert_pipe_enabled(dev_priv, pipe);
2062 assert_plane_enabled(dev_priv, plane);
2063
2064 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2065 for train result */
2066 reg = FDI_RX_IMR(pipe);
2067 temp = I915_READ(reg);
2068 temp &= ~FDI_RX_SYMBOL_LOCK;
2069 temp &= ~FDI_RX_BIT_LOCK;
2070 I915_WRITE(reg, temp);
2071 I915_READ(reg);
2072 udelay(150);
2073
2074 /* enable CPU FDI TX and PCH FDI RX */
2075 reg = FDI_TX_CTL(pipe);
2076 temp = I915_READ(reg);
2077 temp &= ~(7 << 19);
2078 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2079 temp &= ~FDI_LINK_TRAIN_NONE;
2080 temp |= FDI_LINK_TRAIN_PATTERN_1;
2081 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2082
2083 reg = FDI_RX_CTL(pipe);
2084 temp = I915_READ(reg);
2085 temp &= ~FDI_LINK_TRAIN_NONE;
2086 temp |= FDI_LINK_TRAIN_PATTERN_1;
2087 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2088
2089 POSTING_READ(reg);
2090 udelay(150);
2091
2092 /* Ironlake workaround, enable clock pointer after FDI enable*/
2093 if (HAS_PCH_IBX(dev)) {
2094 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2095 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2096 FDI_RX_PHASE_SYNC_POINTER_EN);
2097 }
2098
2099 reg = FDI_RX_IIR(pipe);
2100 for (tries = 0; tries < 5; tries++) {
2101 temp = I915_READ(reg);
2102 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2103
2104 if ((temp & FDI_RX_BIT_LOCK)) {
2105 DRM_DEBUG_KMS("FDI train 1 done.\n");
2106 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2107 break;
2108 }
2109 }
2110 if (tries == 5)
2111 DRM_ERROR("FDI train 1 fail!\n");
2112
2113 /* Train 2 */
2114 reg = FDI_TX_CTL(pipe);
2115 temp = I915_READ(reg);
2116 temp &= ~FDI_LINK_TRAIN_NONE;
2117 temp |= FDI_LINK_TRAIN_PATTERN_2;
2118 I915_WRITE(reg, temp);
2119
2120 reg = FDI_RX_CTL(pipe);
2121 temp = I915_READ(reg);
2122 temp &= ~FDI_LINK_TRAIN_NONE;
2123 temp |= FDI_LINK_TRAIN_PATTERN_2;
2124 I915_WRITE(reg, temp);
2125
2126 POSTING_READ(reg);
2127 udelay(150);
2128
2129 reg = FDI_RX_IIR(pipe);
2130 for (tries = 0; tries < 5; tries++) {
2131 temp = I915_READ(reg);
2132 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2133
2134 if (temp & FDI_RX_SYMBOL_LOCK) {
2135 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2136 DRM_DEBUG_KMS("FDI train 2 done.\n");
2137 break;
2138 }
2139 }
2140 if (tries == 5)
2141 DRM_ERROR("FDI train 2 fail!\n");
2142
2143 DRM_DEBUG_KMS("FDI train done\n");
2144
2145 }
2146
2147 static const int snb_b_fdi_train_param[] = {
2148 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2149 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2150 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2151 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2152 };
2153
2154 /* The FDI link training functions for SNB/Cougarpoint. */
2155 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2156 {
2157 struct drm_device *dev = crtc->dev;
2158 struct drm_i915_private *dev_priv = dev->dev_private;
2159 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2160 int pipe = intel_crtc->pipe;
2161 u32 reg, temp, i, retry;
2162
2163 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2164 for train result */
2165 reg = FDI_RX_IMR(pipe);
2166 temp = I915_READ(reg);
2167 temp &= ~FDI_RX_SYMBOL_LOCK;
2168 temp &= ~FDI_RX_BIT_LOCK;
2169 I915_WRITE(reg, temp);
2170
2171 POSTING_READ(reg);
2172 udelay(150);
2173
2174 /* enable CPU FDI TX and PCH FDI RX */
2175 reg = FDI_TX_CTL(pipe);
2176 temp = I915_READ(reg);
2177 temp &= ~(7 << 19);
2178 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2179 temp &= ~FDI_LINK_TRAIN_NONE;
2180 temp |= FDI_LINK_TRAIN_PATTERN_1;
2181 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2182 /* SNB-B */
2183 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2184 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2185
2186 reg = FDI_RX_CTL(pipe);
2187 temp = I915_READ(reg);
2188 if (HAS_PCH_CPT(dev)) {
2189 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2190 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2191 } else {
2192 temp &= ~FDI_LINK_TRAIN_NONE;
2193 temp |= FDI_LINK_TRAIN_PATTERN_1;
2194 }
2195 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2196
2197 POSTING_READ(reg);
2198 udelay(150);
2199
2200 if (HAS_PCH_CPT(dev))
2201 cpt_phase_pointer_enable(dev, pipe);
2202
2203 for (i = 0; i < 4; i++) {
2204 reg = FDI_TX_CTL(pipe);
2205 temp = I915_READ(reg);
2206 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2207 temp |= snb_b_fdi_train_param[i];
2208 I915_WRITE(reg, temp);
2209
2210 POSTING_READ(reg);
2211 udelay(500);
2212
2213 for (retry = 0; retry < 5; retry++) {
2214 reg = FDI_RX_IIR(pipe);
2215 temp = I915_READ(reg);
2216 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2217 if (temp & FDI_RX_BIT_LOCK) {
2218 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2219 DRM_DEBUG_KMS("FDI train 1 done.\n");
2220 break;
2221 }
2222 udelay(50);
2223 }
2224 if (retry < 5)
2225 break;
2226 }
2227 if (i == 4)
2228 DRM_ERROR("FDI train 1 fail!\n");
2229
2230 /* Train 2 */
2231 reg = FDI_TX_CTL(pipe);
2232 temp = I915_READ(reg);
2233 temp &= ~FDI_LINK_TRAIN_NONE;
2234 temp |= FDI_LINK_TRAIN_PATTERN_2;
2235 if (IS_GEN6(dev)) {
2236 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2237 /* SNB-B */
2238 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2239 }
2240 I915_WRITE(reg, temp);
2241
2242 reg = FDI_RX_CTL(pipe);
2243 temp = I915_READ(reg);
2244 if (HAS_PCH_CPT(dev)) {
2245 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2246 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2247 } else {
2248 temp &= ~FDI_LINK_TRAIN_NONE;
2249 temp |= FDI_LINK_TRAIN_PATTERN_2;
2250 }
2251 I915_WRITE(reg, temp);
2252
2253 POSTING_READ(reg);
2254 udelay(150);
2255
2256 for (i = 0; i < 4; i++) {
2257 reg = FDI_TX_CTL(pipe);
2258 temp = I915_READ(reg);
2259 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2260 temp |= snb_b_fdi_train_param[i];
2261 I915_WRITE(reg, temp);
2262
2263 POSTING_READ(reg);
2264 udelay(500);
2265
2266 for (retry = 0; retry < 5; retry++) {
2267 reg = FDI_RX_IIR(pipe);
2268 temp = I915_READ(reg);
2269 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2270 if (temp & FDI_RX_SYMBOL_LOCK) {
2271 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2272 DRM_DEBUG_KMS("FDI train 2 done.\n");
2273 break;
2274 }
2275 udelay(50);
2276 }
2277 if (retry < 5)
2278 break;
2279 }
2280 if (i == 4)
2281 DRM_ERROR("FDI train 2 fail!\n");
2282
2283 DRM_DEBUG_KMS("FDI train done.\n");
2284 }
2285
2286 /* Manual link training for Ivy Bridge A0 parts */
2287 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2288 {
2289 struct drm_device *dev = crtc->dev;
2290 struct drm_i915_private *dev_priv = dev->dev_private;
2291 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2292 int pipe = intel_crtc->pipe;
2293 u32 reg, temp, i;
2294
2295 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2296 for train result */
2297 reg = FDI_RX_IMR(pipe);
2298 temp = I915_READ(reg);
2299 temp &= ~FDI_RX_SYMBOL_LOCK;
2300 temp &= ~FDI_RX_BIT_LOCK;
2301 I915_WRITE(reg, temp);
2302
2303 POSTING_READ(reg);
2304 udelay(150);
2305
2306 /* enable CPU FDI TX and PCH FDI RX */
2307 reg = FDI_TX_CTL(pipe);
2308 temp = I915_READ(reg);
2309 temp &= ~(7 << 19);
2310 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2311 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2312 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2313 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2314 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2315 temp |= FDI_COMPOSITE_SYNC;
2316 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2317
2318 reg = FDI_RX_CTL(pipe);
2319 temp = I915_READ(reg);
2320 temp &= ~FDI_LINK_TRAIN_AUTO;
2321 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2322 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2323 temp |= FDI_COMPOSITE_SYNC;
2324 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2325
2326 POSTING_READ(reg);
2327 udelay(150);
2328
2329 if (HAS_PCH_CPT(dev))
2330 cpt_phase_pointer_enable(dev, pipe);
2331
2332 for (i = 0; i < 4; i++) {
2333 reg = FDI_TX_CTL(pipe);
2334 temp = I915_READ(reg);
2335 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2336 temp |= snb_b_fdi_train_param[i];
2337 I915_WRITE(reg, temp);
2338
2339 POSTING_READ(reg);
2340 udelay(500);
2341
2342 reg = FDI_RX_IIR(pipe);
2343 temp = I915_READ(reg);
2344 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2345
2346 if (temp & FDI_RX_BIT_LOCK ||
2347 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2348 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2349 DRM_DEBUG_KMS("FDI train 1 done.\n");
2350 break;
2351 }
2352 }
2353 if (i == 4)
2354 DRM_ERROR("FDI train 1 fail!\n");
2355
2356 /* Train 2 */
2357 reg = FDI_TX_CTL(pipe);
2358 temp = I915_READ(reg);
2359 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2360 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2361 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2362 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2363 I915_WRITE(reg, temp);
2364
2365 reg = FDI_RX_CTL(pipe);
2366 temp = I915_READ(reg);
2367 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2368 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2369 I915_WRITE(reg, temp);
2370
2371 POSTING_READ(reg);
2372 udelay(150);
2373
2374 for (i = 0; i < 4; i++) {
2375 reg = FDI_TX_CTL(pipe);
2376 temp = I915_READ(reg);
2377 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2378 temp |= snb_b_fdi_train_param[i];
2379 I915_WRITE(reg, temp);
2380
2381 POSTING_READ(reg);
2382 udelay(500);
2383
2384 reg = FDI_RX_IIR(pipe);
2385 temp = I915_READ(reg);
2386 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2387
2388 if (temp & FDI_RX_SYMBOL_LOCK) {
2389 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2390 DRM_DEBUG_KMS("FDI train 2 done.\n");
2391 break;
2392 }
2393 }
2394 if (i == 4)
2395 DRM_ERROR("FDI train 2 fail!\n");
2396
2397 DRM_DEBUG_KMS("FDI train done.\n");
2398 }
2399
2400 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2401 {
2402 struct drm_device *dev = crtc->dev;
2403 struct drm_i915_private *dev_priv = dev->dev_private;
2404 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2405 int pipe = intel_crtc->pipe;
2406 u32 reg, temp;
2407
2408 /* Write the TU size bits so error detection works */
2409 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2410 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2411
2412 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2413 reg = FDI_RX_CTL(pipe);
2414 temp = I915_READ(reg);
2415 temp &= ~((0x7 << 19) | (0x7 << 16));
2416 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2417 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2418 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2419
2420 POSTING_READ(reg);
2421 udelay(200);
2422
2423 /* Switch from Rawclk to PCDclk */
2424 temp = I915_READ(reg);
2425 I915_WRITE(reg, temp | FDI_PCDCLK);
2426
2427 POSTING_READ(reg);
2428 udelay(200);
2429
2430 /* Enable CPU FDI TX PLL, always on for Ironlake */
2431 reg = FDI_TX_CTL(pipe);
2432 temp = I915_READ(reg);
2433 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2434 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2435
2436 POSTING_READ(reg);
2437 udelay(100);
2438 }
2439 }
2440
2441 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2442 {
2443 struct drm_i915_private *dev_priv = dev->dev_private;
2444 u32 flags = I915_READ(SOUTH_CHICKEN1);
2445
2446 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2447 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2448 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2449 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2450 POSTING_READ(SOUTH_CHICKEN1);
2451 }
2452 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2453 {
2454 struct drm_device *dev = crtc->dev;
2455 struct drm_i915_private *dev_priv = dev->dev_private;
2456 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2457 int pipe = intel_crtc->pipe;
2458 u32 reg, temp;
2459
2460 /* disable CPU FDI tx and PCH FDI rx */
2461 reg = FDI_TX_CTL(pipe);
2462 temp = I915_READ(reg);
2463 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2464 POSTING_READ(reg);
2465
2466 reg = FDI_RX_CTL(pipe);
2467 temp = I915_READ(reg);
2468 temp &= ~(0x7 << 16);
2469 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2470 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2471
2472 POSTING_READ(reg);
2473 udelay(100);
2474
2475 /* Ironlake workaround, disable clock pointer after downing FDI */
2476 if (HAS_PCH_IBX(dev)) {
2477 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2478 I915_WRITE(FDI_RX_CHICKEN(pipe),
2479 I915_READ(FDI_RX_CHICKEN(pipe) &
2480 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2481 } else if (HAS_PCH_CPT(dev)) {
2482 cpt_phase_pointer_disable(dev, pipe);
2483 }
2484
2485 /* still set train pattern 1 */
2486 reg = FDI_TX_CTL(pipe);
2487 temp = I915_READ(reg);
2488 temp &= ~FDI_LINK_TRAIN_NONE;
2489 temp |= FDI_LINK_TRAIN_PATTERN_1;
2490 I915_WRITE(reg, temp);
2491
2492 reg = FDI_RX_CTL(pipe);
2493 temp = I915_READ(reg);
2494 if (HAS_PCH_CPT(dev)) {
2495 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2496 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2497 } else {
2498 temp &= ~FDI_LINK_TRAIN_NONE;
2499 temp |= FDI_LINK_TRAIN_PATTERN_1;
2500 }
2501 /* BPC in FDI rx is consistent with that in PIPECONF */
2502 temp &= ~(0x07 << 16);
2503 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2504 I915_WRITE(reg, temp);
2505
2506 POSTING_READ(reg);
2507 udelay(100);
2508 }
2509
2510 /*
2511 * When we disable a pipe, we need to clear any pending scanline wait events
2512 * to avoid hanging the ring, which we assume we are waiting on.
2513 */
2514 static void intel_clear_scanline_wait(struct drm_device *dev)
2515 {
2516 struct drm_i915_private *dev_priv = dev->dev_private;
2517 struct intel_ring_buffer *ring;
2518 u32 tmp;
2519
2520 if (IS_GEN2(dev))
2521 /* Can't break the hang on i8xx */
2522 return;
2523
2524 ring = LP_RING(dev_priv);
2525 tmp = I915_READ_CTL(ring);
2526 if (tmp & RING_WAIT)
2527 I915_WRITE_CTL(ring, tmp);
2528 }
2529
2530 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2531 {
2532 struct drm_device *dev = crtc->dev;
2533
2534 if (crtc->fb == NULL)
2535 return;
2536
2537 mutex_lock(&dev->struct_mutex);
2538 intel_finish_fb(crtc->fb);
2539 mutex_unlock(&dev->struct_mutex);
2540 }
2541
2542 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2543 {
2544 struct drm_device *dev = crtc->dev;
2545 struct drm_mode_config *mode_config = &dev->mode_config;
2546 struct intel_encoder *encoder;
2547
2548 /*
2549 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2550 * must be driven by its own crtc; no sharing is possible.
2551 */
2552 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2553 if (encoder->base.crtc != crtc)
2554 continue;
2555
2556 switch (encoder->type) {
2557 case INTEL_OUTPUT_EDP:
2558 if (!intel_encoder_is_pch_edp(&encoder->base))
2559 return false;
2560 continue;
2561 }
2562 }
2563
2564 return true;
2565 }
2566
2567 /*
2568 * Enable PCH resources required for PCH ports:
2569 * - PCH PLLs
2570 * - FDI training & RX/TX
2571 * - update transcoder timings
2572 * - DP transcoding bits
2573 * - transcoder
2574 */
2575 static void ironlake_pch_enable(struct drm_crtc *crtc)
2576 {
2577 struct drm_device *dev = crtc->dev;
2578 struct drm_i915_private *dev_priv = dev->dev_private;
2579 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2580 int pipe = intel_crtc->pipe;
2581 u32 reg, temp, transc_sel;
2582
2583 /* For PCH output, training FDI link */
2584 dev_priv->display.fdi_link_train(crtc);
2585
2586 intel_enable_pch_pll(dev_priv, pipe);
2587
2588 if (HAS_PCH_CPT(dev)) {
2589 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
2590 TRANSC_DPLLB_SEL;
2591
2592 /* Be sure PCH DPLL SEL is set */
2593 temp = I915_READ(PCH_DPLL_SEL);
2594 if (pipe == 0) {
2595 temp &= ~(TRANSA_DPLLB_SEL);
2596 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2597 } else if (pipe == 1) {
2598 temp &= ~(TRANSB_DPLLB_SEL);
2599 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2600 } else if (pipe == 2) {
2601 temp &= ~(TRANSC_DPLLB_SEL);
2602 temp |= (TRANSC_DPLL_ENABLE | transc_sel);
2603 }
2604 I915_WRITE(PCH_DPLL_SEL, temp);
2605 }
2606
2607 /* set transcoder timing, panel must allow it */
2608 assert_panel_unlocked(dev_priv, pipe);
2609 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2610 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2611 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
2612
2613 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2614 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2615 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
2616 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
2617
2618 intel_fdi_normal_train(crtc);
2619
2620 /* For PCH DP, enable TRANS_DP_CTL */
2621 if (HAS_PCH_CPT(dev) &&
2622 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2623 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2624 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2625 reg = TRANS_DP_CTL(pipe);
2626 temp = I915_READ(reg);
2627 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2628 TRANS_DP_SYNC_MASK |
2629 TRANS_DP_BPC_MASK);
2630 temp |= (TRANS_DP_OUTPUT_ENABLE |
2631 TRANS_DP_ENH_FRAMING);
2632 temp |= bpc << 9; /* same format but at 11:9 */
2633
2634 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2635 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2636 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2637 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2638
2639 switch (intel_trans_dp_port_sel(crtc)) {
2640 case PCH_DP_B:
2641 temp |= TRANS_DP_PORT_SEL_B;
2642 break;
2643 case PCH_DP_C:
2644 temp |= TRANS_DP_PORT_SEL_C;
2645 break;
2646 case PCH_DP_D:
2647 temp |= TRANS_DP_PORT_SEL_D;
2648 break;
2649 default:
2650 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2651 temp |= TRANS_DP_PORT_SEL_B;
2652 break;
2653 }
2654
2655 I915_WRITE(reg, temp);
2656 }
2657
2658 intel_enable_transcoder(dev_priv, pipe);
2659 }
2660
2661 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
2662 {
2663 struct drm_i915_private *dev_priv = dev->dev_private;
2664 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
2665 u32 temp;
2666
2667 temp = I915_READ(dslreg);
2668 udelay(500);
2669 if (wait_for(I915_READ(dslreg) != temp, 5)) {
2670 /* Without this, mode sets may fail silently on FDI */
2671 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
2672 udelay(250);
2673 I915_WRITE(tc2reg, 0);
2674 if (wait_for(I915_READ(dslreg) != temp, 5))
2675 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
2676 }
2677 }
2678
2679 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2680 {
2681 struct drm_device *dev = crtc->dev;
2682 struct drm_i915_private *dev_priv = dev->dev_private;
2683 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2684 int pipe = intel_crtc->pipe;
2685 int plane = intel_crtc->plane;
2686 u32 temp;
2687 bool is_pch_port;
2688
2689 if (intel_crtc->active)
2690 return;
2691
2692 intel_crtc->active = true;
2693 intel_update_watermarks(dev);
2694
2695 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2696 temp = I915_READ(PCH_LVDS);
2697 if ((temp & LVDS_PORT_EN) == 0)
2698 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2699 }
2700
2701 is_pch_port = intel_crtc_driving_pch(crtc);
2702
2703 if (is_pch_port)
2704 ironlake_fdi_pll_enable(crtc);
2705 else
2706 ironlake_fdi_disable(crtc);
2707
2708 /* Enable panel fitting for LVDS */
2709 if (dev_priv->pch_pf_size &&
2710 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2711 /* Force use of hard-coded filter coefficients
2712 * as some pre-programmed values are broken,
2713 * e.g. x201.
2714 */
2715 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2716 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2717 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
2718 }
2719
2720 /*
2721 * On ILK+ LUT must be loaded before the pipe is running but with
2722 * clocks enabled
2723 */
2724 intel_crtc_load_lut(crtc);
2725
2726 intel_enable_pipe(dev_priv, pipe, is_pch_port);
2727 intel_enable_plane(dev_priv, plane, pipe);
2728
2729 if (is_pch_port)
2730 ironlake_pch_enable(crtc);
2731
2732 mutex_lock(&dev->struct_mutex);
2733 intel_update_fbc(dev);
2734 mutex_unlock(&dev->struct_mutex);
2735
2736 intel_crtc_update_cursor(crtc, true);
2737 }
2738
2739 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2740 {
2741 struct drm_device *dev = crtc->dev;
2742 struct drm_i915_private *dev_priv = dev->dev_private;
2743 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2744 int pipe = intel_crtc->pipe;
2745 int plane = intel_crtc->plane;
2746 u32 reg, temp;
2747
2748 if (!intel_crtc->active)
2749 return;
2750
2751 intel_crtc_wait_for_pending_flips(crtc);
2752 drm_vblank_off(dev, pipe);
2753 intel_crtc_update_cursor(crtc, false);
2754
2755 intel_disable_plane(dev_priv, plane, pipe);
2756
2757 if (dev_priv->cfb_plane == plane)
2758 intel_disable_fbc(dev);
2759
2760 intel_disable_pipe(dev_priv, pipe);
2761
2762 /* Disable PF */
2763 I915_WRITE(PF_CTL(pipe), 0);
2764 I915_WRITE(PF_WIN_SZ(pipe), 0);
2765
2766 ironlake_fdi_disable(crtc);
2767
2768 /* This is a horrible layering violation; we should be doing this in
2769 * the connector/encoder ->prepare instead, but we don't always have
2770 * enough information there about the config to know whether it will
2771 * actually be necessary or just cause undesired flicker.
2772 */
2773 intel_disable_pch_ports(dev_priv, pipe);
2774
2775 intel_disable_transcoder(dev_priv, pipe);
2776
2777 if (HAS_PCH_CPT(dev)) {
2778 /* disable TRANS_DP_CTL */
2779 reg = TRANS_DP_CTL(pipe);
2780 temp = I915_READ(reg);
2781 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2782 temp |= TRANS_DP_PORT_SEL_NONE;
2783 I915_WRITE(reg, temp);
2784
2785 /* disable DPLL_SEL */
2786 temp = I915_READ(PCH_DPLL_SEL);
2787 switch (pipe) {
2788 case 0:
2789 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2790 break;
2791 case 1:
2792 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2793 break;
2794 case 2:
2795 /* C shares PLL A or B */
2796 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
2797 break;
2798 default:
2799 BUG(); /* wtf */
2800 }
2801 I915_WRITE(PCH_DPLL_SEL, temp);
2802 }
2803
2804 /* disable PCH DPLL */
2805 if (!intel_crtc->no_pll)
2806 intel_disable_pch_pll(dev_priv, pipe);
2807
2808 /* Switch from PCDclk to Rawclk */
2809 reg = FDI_RX_CTL(pipe);
2810 temp = I915_READ(reg);
2811 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2812
2813 /* Disable CPU FDI TX PLL */
2814 reg = FDI_TX_CTL(pipe);
2815 temp = I915_READ(reg);
2816 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2817
2818 POSTING_READ(reg);
2819 udelay(100);
2820
2821 reg = FDI_RX_CTL(pipe);
2822 temp = I915_READ(reg);
2823 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2824
2825 /* Wait for the clocks to turn off. */
2826 POSTING_READ(reg);
2827 udelay(100);
2828
2829 intel_crtc->active = false;
2830 intel_update_watermarks(dev);
2831
2832 mutex_lock(&dev->struct_mutex);
2833 intel_update_fbc(dev);
2834 intel_clear_scanline_wait(dev);
2835 mutex_unlock(&dev->struct_mutex);
2836 }
2837
2838 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2839 {
2840 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2841 int pipe = intel_crtc->pipe;
2842 int plane = intel_crtc->plane;
2843
2844 /* XXX: When our outputs are all unaware of DPMS modes other than off
2845 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2846 */
2847 switch (mode) {
2848 case DRM_MODE_DPMS_ON:
2849 case DRM_MODE_DPMS_STANDBY:
2850 case DRM_MODE_DPMS_SUSPEND:
2851 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2852 ironlake_crtc_enable(crtc);
2853 break;
2854
2855 case DRM_MODE_DPMS_OFF:
2856 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2857 ironlake_crtc_disable(crtc);
2858 break;
2859 }
2860 }
2861
2862 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2863 {
2864 if (!enable && intel_crtc->overlay) {
2865 struct drm_device *dev = intel_crtc->base.dev;
2866 struct drm_i915_private *dev_priv = dev->dev_private;
2867
2868 mutex_lock(&dev->struct_mutex);
2869 dev_priv->mm.interruptible = false;
2870 (void) intel_overlay_switch_off(intel_crtc->overlay);
2871 dev_priv->mm.interruptible = true;
2872 mutex_unlock(&dev->struct_mutex);
2873 }
2874
2875 /* Let userspace switch the overlay on again. In most cases userspace
2876 * has to recompute where to put it anyway.
2877 */
2878 }
2879
2880 static void i9xx_crtc_enable(struct drm_crtc *crtc)
2881 {
2882 struct drm_device *dev = crtc->dev;
2883 struct drm_i915_private *dev_priv = dev->dev_private;
2884 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2885 int pipe = intel_crtc->pipe;
2886 int plane = intel_crtc->plane;
2887
2888 if (intel_crtc->active)
2889 return;
2890
2891 intel_crtc->active = true;
2892 intel_update_watermarks(dev);
2893
2894 intel_enable_pll(dev_priv, pipe);
2895 intel_enable_pipe(dev_priv, pipe, false);
2896 intel_enable_plane(dev_priv, plane, pipe);
2897
2898 intel_crtc_load_lut(crtc);
2899 intel_update_fbc(dev);
2900
2901 /* Give the overlay scaler a chance to enable if it's on this pipe */
2902 intel_crtc_dpms_overlay(intel_crtc, true);
2903 intel_crtc_update_cursor(crtc, true);
2904 }
2905
2906 static void i9xx_crtc_disable(struct drm_crtc *crtc)
2907 {
2908 struct drm_device *dev = crtc->dev;
2909 struct drm_i915_private *dev_priv = dev->dev_private;
2910 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2911 int pipe = intel_crtc->pipe;
2912 int plane = intel_crtc->plane;
2913
2914 if (!intel_crtc->active)
2915 return;
2916
2917 /* Give the overlay scaler a chance to disable if it's on this pipe */
2918 intel_crtc_wait_for_pending_flips(crtc);
2919 drm_vblank_off(dev, pipe);
2920 intel_crtc_dpms_overlay(intel_crtc, false);
2921 intel_crtc_update_cursor(crtc, false);
2922
2923 if (dev_priv->cfb_plane == plane)
2924 intel_disable_fbc(dev);
2925
2926 intel_disable_plane(dev_priv, plane, pipe);
2927 intel_disable_pipe(dev_priv, pipe);
2928 intel_disable_pll(dev_priv, pipe);
2929
2930 intel_crtc->active = false;
2931 intel_update_fbc(dev);
2932 intel_update_watermarks(dev);
2933 intel_clear_scanline_wait(dev);
2934 }
2935
2936 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2937 {
2938 /* XXX: When our outputs are all unaware of DPMS modes other than off
2939 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2940 */
2941 switch (mode) {
2942 case DRM_MODE_DPMS_ON:
2943 case DRM_MODE_DPMS_STANDBY:
2944 case DRM_MODE_DPMS_SUSPEND:
2945 i9xx_crtc_enable(crtc);
2946 break;
2947 case DRM_MODE_DPMS_OFF:
2948 i9xx_crtc_disable(crtc);
2949 break;
2950 }
2951 }
2952
2953 /**
2954 * Sets the power management mode of the pipe and plane.
2955 */
2956 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2957 {
2958 struct drm_device *dev = crtc->dev;
2959 struct drm_i915_private *dev_priv = dev->dev_private;
2960 struct drm_i915_master_private *master_priv;
2961 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2962 int pipe = intel_crtc->pipe;
2963 bool enabled;
2964
2965 if (intel_crtc->dpms_mode == mode)
2966 return;
2967
2968 intel_crtc->dpms_mode = mode;
2969
2970 dev_priv->display.dpms(crtc, mode);
2971
2972 if (!dev->primary->master)
2973 return;
2974
2975 master_priv = dev->primary->master->driver_priv;
2976 if (!master_priv->sarea_priv)
2977 return;
2978
2979 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2980
2981 switch (pipe) {
2982 case 0:
2983 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2984 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2985 break;
2986 case 1:
2987 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2988 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2989 break;
2990 default:
2991 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
2992 break;
2993 }
2994 }
2995
2996 static void intel_crtc_disable(struct drm_crtc *crtc)
2997 {
2998 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2999 struct drm_device *dev = crtc->dev;
3000
3001 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3002 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3003 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3004
3005 if (crtc->fb) {
3006 mutex_lock(&dev->struct_mutex);
3007 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3008 mutex_unlock(&dev->struct_mutex);
3009 }
3010 }
3011
3012 /* Prepare for a mode set.
3013 *
3014 * Note we could be a lot smarter here. We need to figure out which outputs
3015 * will be enabled, which disabled (in short, how the config will changes)
3016 * and perform the minimum necessary steps to accomplish that, e.g. updating
3017 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3018 * panel fitting is in the proper state, etc.
3019 */
3020 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3021 {
3022 i9xx_crtc_disable(crtc);
3023 }
3024
3025 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3026 {
3027 i9xx_crtc_enable(crtc);
3028 }
3029
3030 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3031 {
3032 ironlake_crtc_disable(crtc);
3033 }
3034
3035 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3036 {
3037 ironlake_crtc_enable(crtc);
3038 }
3039
3040 void intel_encoder_prepare(struct drm_encoder *encoder)
3041 {
3042 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3043 /* lvds has its own version of prepare see intel_lvds_prepare */
3044 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3045 }
3046
3047 void intel_encoder_commit(struct drm_encoder *encoder)
3048 {
3049 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3050 struct drm_device *dev = encoder->dev;
3051 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3052 struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3053
3054 /* lvds has its own version of commit see intel_lvds_commit */
3055 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3056
3057 if (HAS_PCH_CPT(dev))
3058 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3059 }
3060
3061 void intel_encoder_destroy(struct drm_encoder *encoder)
3062 {
3063 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3064
3065 drm_encoder_cleanup(encoder);
3066 kfree(intel_encoder);
3067 }
3068
3069 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3070 struct drm_display_mode *mode,
3071 struct drm_display_mode *adjusted_mode)
3072 {
3073 struct drm_device *dev = crtc->dev;
3074
3075 if (HAS_PCH_SPLIT(dev)) {
3076 /* FDI link clock is fixed at 2.7G */
3077 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3078 return false;
3079 }
3080
3081 /* All interlaced capable intel hw wants timings in frames. Note though
3082 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3083 * timings, so we need to be careful not to clobber these.*/
3084 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3085 drm_mode_set_crtcinfo(adjusted_mode, 0);
3086
3087 return true;
3088 }
3089
3090 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3091 {
3092 return 400000; /* FIXME */
3093 }
3094
3095 static int i945_get_display_clock_speed(struct drm_device *dev)
3096 {
3097 return 400000;
3098 }
3099
3100 static int i915_get_display_clock_speed(struct drm_device *dev)
3101 {
3102 return 333000;
3103 }
3104
3105 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3106 {
3107 return 200000;
3108 }
3109
3110 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3111 {
3112 u16 gcfgc = 0;
3113
3114 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3115
3116 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3117 return 133000;
3118 else {
3119 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3120 case GC_DISPLAY_CLOCK_333_MHZ:
3121 return 333000;
3122 default:
3123 case GC_DISPLAY_CLOCK_190_200_MHZ:
3124 return 190000;
3125 }
3126 }
3127 }
3128
3129 static int i865_get_display_clock_speed(struct drm_device *dev)
3130 {
3131 return 266000;
3132 }
3133
3134 static int i855_get_display_clock_speed(struct drm_device *dev)
3135 {
3136 u16 hpllcc = 0;
3137 /* Assume that the hardware is in the high speed state. This
3138 * should be the default.
3139 */
3140 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3141 case GC_CLOCK_133_200:
3142 case GC_CLOCK_100_200:
3143 return 200000;
3144 case GC_CLOCK_166_250:
3145 return 250000;
3146 case GC_CLOCK_100_133:
3147 return 133000;
3148 }
3149
3150 /* Shouldn't happen */
3151 return 0;
3152 }
3153
3154 static int i830_get_display_clock_speed(struct drm_device *dev)
3155 {
3156 return 133000;
3157 }
3158
3159 struct fdi_m_n {
3160 u32 tu;
3161 u32 gmch_m;
3162 u32 gmch_n;
3163 u32 link_m;
3164 u32 link_n;
3165 };
3166
3167 static void
3168 fdi_reduce_ratio(u32 *num, u32 *den)
3169 {
3170 while (*num > 0xffffff || *den > 0xffffff) {
3171 *num >>= 1;
3172 *den >>= 1;
3173 }
3174 }
3175
3176 static void
3177 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3178 int link_clock, struct fdi_m_n *m_n)
3179 {
3180 m_n->tu = 64; /* default size */
3181
3182 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3183 m_n->gmch_m = bits_per_pixel * pixel_clock;
3184 m_n->gmch_n = link_clock * nlanes * 8;
3185 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3186
3187 m_n->link_m = pixel_clock;
3188 m_n->link_n = link_clock;
3189 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3190 }
3191
3192 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3193 {
3194 if (i915_panel_use_ssc >= 0)
3195 return i915_panel_use_ssc != 0;
3196 return dev_priv->lvds_use_ssc
3197 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
3198 }
3199
3200 /**
3201 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3202 * @crtc: CRTC structure
3203 * @mode: requested mode
3204 *
3205 * A pipe may be connected to one or more outputs. Based on the depth of the
3206 * attached framebuffer, choose a good color depth to use on the pipe.
3207 *
3208 * If possible, match the pipe depth to the fb depth. In some cases, this
3209 * isn't ideal, because the connected output supports a lesser or restricted
3210 * set of depths. Resolve that here:
3211 * LVDS typically supports only 6bpc, so clamp down in that case
3212 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3213 * Displays may support a restricted set as well, check EDID and clamp as
3214 * appropriate.
3215 * DP may want to dither down to 6bpc to fit larger modes
3216 *
3217 * RETURNS:
3218 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3219 * true if they don't match).
3220 */
3221 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3222 unsigned int *pipe_bpp,
3223 struct drm_display_mode *mode)
3224 {
3225 struct drm_device *dev = crtc->dev;
3226 struct drm_i915_private *dev_priv = dev->dev_private;
3227 struct drm_encoder *encoder;
3228 struct drm_connector *connector;
3229 unsigned int display_bpc = UINT_MAX, bpc;
3230
3231 /* Walk the encoders & connectors on this crtc, get min bpc */
3232 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3233 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3234
3235 if (encoder->crtc != crtc)
3236 continue;
3237
3238 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3239 unsigned int lvds_bpc;
3240
3241 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3242 LVDS_A3_POWER_UP)
3243 lvds_bpc = 8;
3244 else
3245 lvds_bpc = 6;
3246
3247 if (lvds_bpc < display_bpc) {
3248 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
3249 display_bpc = lvds_bpc;
3250 }
3251 continue;
3252 }
3253
3254 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
3255 /* Use VBT settings if we have an eDP panel */
3256 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
3257
3258 if (edp_bpc < display_bpc) {
3259 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
3260 display_bpc = edp_bpc;
3261 }
3262 continue;
3263 }
3264
3265 /* Not one of the known troublemakers, check the EDID */
3266 list_for_each_entry(connector, &dev->mode_config.connector_list,
3267 head) {
3268 if (connector->encoder != encoder)
3269 continue;
3270
3271 /* Don't use an invalid EDID bpc value */
3272 if (connector->display_info.bpc &&
3273 connector->display_info.bpc < display_bpc) {
3274 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
3275 display_bpc = connector->display_info.bpc;
3276 }
3277 }
3278
3279 /*
3280 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3281 * through, clamp it down. (Note: >12bpc will be caught below.)
3282 */
3283 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3284 if (display_bpc > 8 && display_bpc < 12) {
3285 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
3286 display_bpc = 12;
3287 } else {
3288 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
3289 display_bpc = 8;
3290 }
3291 }
3292 }
3293
3294 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3295 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3296 display_bpc = 6;
3297 }
3298
3299 /*
3300 * We could just drive the pipe at the highest bpc all the time and
3301 * enable dithering as needed, but that costs bandwidth. So choose
3302 * the minimum value that expresses the full color range of the fb but
3303 * also stays within the max display bpc discovered above.
3304 */
3305
3306 switch (crtc->fb->depth) {
3307 case 8:
3308 bpc = 8; /* since we go through a colormap */
3309 break;
3310 case 15:
3311 case 16:
3312 bpc = 6; /* min is 18bpp */
3313 break;
3314 case 24:
3315 bpc = 8;
3316 break;
3317 case 30:
3318 bpc = 10;
3319 break;
3320 case 48:
3321 bpc = 12;
3322 break;
3323 default:
3324 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3325 bpc = min((unsigned int)8, display_bpc);
3326 break;
3327 }
3328
3329 display_bpc = min(display_bpc, bpc);
3330
3331 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3332 bpc, display_bpc);
3333
3334 *pipe_bpp = display_bpc * 3;
3335
3336 return display_bpc != bpc;
3337 }
3338
3339 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3340 {
3341 struct drm_device *dev = crtc->dev;
3342 struct drm_i915_private *dev_priv = dev->dev_private;
3343 int refclk;
3344
3345 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3346 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3347 refclk = dev_priv->lvds_ssc_freq * 1000;
3348 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3349 refclk / 1000);
3350 } else if (!IS_GEN2(dev)) {
3351 refclk = 96000;
3352 } else {
3353 refclk = 48000;
3354 }
3355
3356 return refclk;
3357 }
3358
3359 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3360 intel_clock_t *clock)
3361 {
3362 /* SDVO TV has fixed PLL values depend on its clock range,
3363 this mirrors vbios setting. */
3364 if (adjusted_mode->clock >= 100000
3365 && adjusted_mode->clock < 140500) {
3366 clock->p1 = 2;
3367 clock->p2 = 10;
3368 clock->n = 3;
3369 clock->m1 = 16;
3370 clock->m2 = 8;
3371 } else if (adjusted_mode->clock >= 140500
3372 && adjusted_mode->clock <= 200000) {
3373 clock->p1 = 1;
3374 clock->p2 = 10;
3375 clock->n = 6;
3376 clock->m1 = 12;
3377 clock->m2 = 8;
3378 }
3379 }
3380
3381 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3382 intel_clock_t *clock,
3383 intel_clock_t *reduced_clock)
3384 {
3385 struct drm_device *dev = crtc->dev;
3386 struct drm_i915_private *dev_priv = dev->dev_private;
3387 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3388 int pipe = intel_crtc->pipe;
3389 u32 fp, fp2 = 0;
3390
3391 if (IS_PINEVIEW(dev)) {
3392 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3393 if (reduced_clock)
3394 fp2 = (1 << reduced_clock->n) << 16 |
3395 reduced_clock->m1 << 8 | reduced_clock->m2;
3396 } else {
3397 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3398 if (reduced_clock)
3399 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3400 reduced_clock->m2;
3401 }
3402
3403 I915_WRITE(FP0(pipe), fp);
3404
3405 intel_crtc->lowfreq_avail = false;
3406 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3407 reduced_clock && i915_powersave) {
3408 I915_WRITE(FP1(pipe), fp2);
3409 intel_crtc->lowfreq_avail = true;
3410 } else {
3411 I915_WRITE(FP1(pipe), fp);
3412 }
3413 }
3414
3415 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3416 struct drm_display_mode *adjusted_mode)
3417 {
3418 struct drm_device *dev = crtc->dev;
3419 struct drm_i915_private *dev_priv = dev->dev_private;
3420 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3421 int pipe = intel_crtc->pipe;
3422 u32 temp;
3423
3424 temp = I915_READ(LVDS);
3425 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3426 if (pipe == 1) {
3427 temp |= LVDS_PIPEB_SELECT;
3428 } else {
3429 temp &= ~LVDS_PIPEB_SELECT;
3430 }
3431 /* set the corresponsding LVDS_BORDER bit */
3432 temp |= dev_priv->lvds_border_bits;
3433 /* Set the B0-B3 data pairs corresponding to whether we're going to
3434 * set the DPLLs for dual-channel mode or not.
3435 */
3436 if (clock->p2 == 7)
3437 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3438 else
3439 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3440
3441 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3442 * appropriately here, but we need to look more thoroughly into how
3443 * panels behave in the two modes.
3444 */
3445 /* set the dithering flag on LVDS as needed */
3446 if (INTEL_INFO(dev)->gen >= 4) {
3447 if (dev_priv->lvds_dither)
3448 temp |= LVDS_ENABLE_DITHER;
3449 else
3450 temp &= ~LVDS_ENABLE_DITHER;
3451 }
3452 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
3453 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
3454 temp |= LVDS_HSYNC_POLARITY;
3455 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
3456 temp |= LVDS_VSYNC_POLARITY;
3457 I915_WRITE(LVDS, temp);
3458 }
3459
3460 static void i9xx_update_pll(struct drm_crtc *crtc,
3461 struct drm_display_mode *mode,
3462 struct drm_display_mode *adjusted_mode,
3463 intel_clock_t *clock, intel_clock_t *reduced_clock,
3464 int num_connectors)
3465 {
3466 struct drm_device *dev = crtc->dev;
3467 struct drm_i915_private *dev_priv = dev->dev_private;
3468 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3469 int pipe = intel_crtc->pipe;
3470 u32 dpll;
3471 bool is_sdvo;
3472
3473 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
3474 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
3475
3476 dpll = DPLL_VGA_MODE_DIS;
3477
3478 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3479 dpll |= DPLLB_MODE_LVDS;
3480 else
3481 dpll |= DPLLB_MODE_DAC_SERIAL;
3482 if (is_sdvo) {
3483 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3484 if (pixel_multiplier > 1) {
3485 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3486 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3487 }
3488 dpll |= DPLL_DVO_HIGH_SPEED;
3489 }
3490 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
3491 dpll |= DPLL_DVO_HIGH_SPEED;
3492
3493 /* compute bitmask from p1 value */
3494 if (IS_PINEVIEW(dev))
3495 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3496 else {
3497 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3498 if (IS_G4X(dev) && reduced_clock)
3499 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3500 }
3501 switch (clock->p2) {
3502 case 5:
3503 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3504 break;
3505 case 7:
3506 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3507 break;
3508 case 10:
3509 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3510 break;
3511 case 14:
3512 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3513 break;
3514 }
3515 if (INTEL_INFO(dev)->gen >= 4)
3516 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3517
3518 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3519 dpll |= PLL_REF_INPUT_TVCLKINBC;
3520 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3521 /* XXX: just matching BIOS for now */
3522 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3523 dpll |= 3;
3524 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3525 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3526 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3527 else
3528 dpll |= PLL_REF_INPUT_DREFCLK;
3529
3530 dpll |= DPLL_VCO_ENABLE;
3531 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3532 POSTING_READ(DPLL(pipe));
3533 udelay(150);
3534
3535 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3536 * This is an exception to the general rule that mode_set doesn't turn
3537 * things on.
3538 */
3539 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3540 intel_update_lvds(crtc, clock, adjusted_mode);
3541
3542 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
3543 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3544
3545 I915_WRITE(DPLL(pipe), dpll);
3546
3547 /* Wait for the clocks to stabilize. */
3548 POSTING_READ(DPLL(pipe));
3549 udelay(150);
3550
3551 if (INTEL_INFO(dev)->gen >= 4) {
3552 u32 temp = 0;
3553 if (is_sdvo) {
3554 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
3555 if (temp > 1)
3556 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
3557 else
3558 temp = 0;
3559 }
3560 I915_WRITE(DPLL_MD(pipe), temp);
3561 } else {
3562 /* The pixel multiplier can only be updated once the
3563 * DPLL is enabled and the clocks are stable.
3564 *
3565 * So write it again.
3566 */
3567 I915_WRITE(DPLL(pipe), dpll);
3568 }
3569 }
3570
3571 static void i8xx_update_pll(struct drm_crtc *crtc,
3572 struct drm_display_mode *adjusted_mode,
3573 intel_clock_t *clock,
3574 int num_connectors)
3575 {
3576 struct drm_device *dev = crtc->dev;
3577 struct drm_i915_private *dev_priv = dev->dev_private;
3578 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3579 int pipe = intel_crtc->pipe;
3580 u32 dpll;
3581
3582 dpll = DPLL_VGA_MODE_DIS;
3583
3584 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3585 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3586 } else {
3587 if (clock->p1 == 2)
3588 dpll |= PLL_P1_DIVIDE_BY_TWO;
3589 else
3590 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3591 if (clock->p2 == 4)
3592 dpll |= PLL_P2_DIVIDE_BY_4;
3593 }
3594
3595 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3596 /* XXX: just matching BIOS for now */
3597 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3598 dpll |= 3;
3599 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3600 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3601 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3602 else
3603 dpll |= PLL_REF_INPUT_DREFCLK;
3604
3605 dpll |= DPLL_VCO_ENABLE;
3606 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3607 POSTING_READ(DPLL(pipe));
3608 udelay(150);
3609
3610 I915_WRITE(DPLL(pipe), dpll);
3611
3612 /* Wait for the clocks to stabilize. */
3613 POSTING_READ(DPLL(pipe));
3614 udelay(150);
3615
3616 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3617 * This is an exception to the general rule that mode_set doesn't turn
3618 * things on.
3619 */
3620 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3621 intel_update_lvds(crtc, clock, adjusted_mode);
3622
3623 /* The pixel multiplier can only be updated once the
3624 * DPLL is enabled and the clocks are stable.
3625 *
3626 * So write it again.
3627 */
3628 I915_WRITE(DPLL(pipe), dpll);
3629 }
3630
3631 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
3632 struct drm_display_mode *mode,
3633 struct drm_display_mode *adjusted_mode,
3634 int x, int y,
3635 struct drm_framebuffer *old_fb)
3636 {
3637 struct drm_device *dev = crtc->dev;
3638 struct drm_i915_private *dev_priv = dev->dev_private;
3639 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3640 int pipe = intel_crtc->pipe;
3641 int plane = intel_crtc->plane;
3642 int refclk, num_connectors = 0;
3643 intel_clock_t clock, reduced_clock;
3644 u32 dspcntr, pipeconf, vsyncshift;
3645 bool ok, has_reduced_clock = false, is_sdvo = false;
3646 bool is_lvds = false, is_tv = false, is_dp = false;
3647 struct drm_mode_config *mode_config = &dev->mode_config;
3648 struct intel_encoder *encoder;
3649 const intel_limit_t *limit;
3650 int ret;
3651
3652 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3653 if (encoder->base.crtc != crtc)
3654 continue;
3655
3656 switch (encoder->type) {
3657 case INTEL_OUTPUT_LVDS:
3658 is_lvds = true;
3659 break;
3660 case INTEL_OUTPUT_SDVO:
3661 case INTEL_OUTPUT_HDMI:
3662 is_sdvo = true;
3663 if (encoder->needs_tv_clock)
3664 is_tv = true;
3665 break;
3666 case INTEL_OUTPUT_TVOUT:
3667 is_tv = true;
3668 break;
3669 case INTEL_OUTPUT_DISPLAYPORT:
3670 is_dp = true;
3671 break;
3672 }
3673
3674 num_connectors++;
3675 }
3676
3677 refclk = i9xx_get_refclk(crtc, num_connectors);
3678
3679 /*
3680 * Returns a set of divisors for the desired target clock with the given
3681 * refclk, or FALSE. The returned values represent the clock equation:
3682 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3683 */
3684 limit = intel_limit(crtc, refclk);
3685 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
3686 &clock);
3687 if (!ok) {
3688 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3689 return -EINVAL;
3690 }
3691
3692 /* Ensure that the cursor is valid for the new mode before changing... */
3693 intel_crtc_update_cursor(crtc, true);
3694
3695 if (is_lvds && dev_priv->lvds_downclock_avail) {
3696 /*
3697 * Ensure we match the reduced clock's P to the target clock.
3698 * If the clocks don't match, we can't switch the display clock
3699 * by using the FP0/FP1. In such case we will disable the LVDS
3700 * downclock feature.
3701 */
3702 has_reduced_clock = limit->find_pll(limit, crtc,
3703 dev_priv->lvds_downclock,
3704 refclk,
3705 &clock,
3706 &reduced_clock);
3707 }
3708
3709 if (is_sdvo && is_tv)
3710 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
3711
3712 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
3713 &reduced_clock : NULL);
3714
3715 if (IS_GEN2(dev))
3716 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
3717 else
3718 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
3719 has_reduced_clock ? &reduced_clock : NULL,
3720 num_connectors);
3721
3722 /* setup pipeconf */
3723 pipeconf = I915_READ(PIPECONF(pipe));
3724
3725 /* Set up the display plane register */
3726 dspcntr = DISPPLANE_GAMMA_ENABLE;
3727
3728 if (pipe == 0)
3729 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3730 else
3731 dspcntr |= DISPPLANE_SEL_PIPE_B;
3732
3733 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
3734 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3735 * core speed.
3736 *
3737 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3738 * pipe == 0 check?
3739 */
3740 if (mode->clock >
3741 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3742 pipeconf |= PIPECONF_DOUBLE_WIDE;
3743 else
3744 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
3745 }
3746
3747 /* default to 8bpc */
3748 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
3749 if (is_dp) {
3750 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3751 pipeconf |= PIPECONF_BPP_6 |
3752 PIPECONF_DITHER_EN |
3753 PIPECONF_DITHER_TYPE_SP;
3754 }
3755 }
3756
3757 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3758 drm_mode_debug_printmodeline(mode);
3759
3760 if (HAS_PIPE_CXSR(dev)) {
3761 if (intel_crtc->lowfreq_avail) {
3762 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3763 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3764 } else {
3765 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3766 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3767 }
3768 }
3769
3770 pipeconf &= ~PIPECONF_INTERLACE_MASK;
3771 if (!IS_GEN2(dev) &&
3772 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
3773 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
3774 /* the chip adds 2 halflines automatically */
3775 adjusted_mode->crtc_vtotal -= 1;
3776 adjusted_mode->crtc_vblank_end -= 1;
3777 vsyncshift = adjusted_mode->crtc_hsync_start
3778 - adjusted_mode->crtc_htotal/2;
3779 } else {
3780 pipeconf |= PIPECONF_PROGRESSIVE;
3781 vsyncshift = 0;
3782 }
3783
3784 if (!IS_GEN3(dev))
3785 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
3786
3787 I915_WRITE(HTOTAL(pipe),
3788 (adjusted_mode->crtc_hdisplay - 1) |
3789 ((adjusted_mode->crtc_htotal - 1) << 16));
3790 I915_WRITE(HBLANK(pipe),
3791 (adjusted_mode->crtc_hblank_start - 1) |
3792 ((adjusted_mode->crtc_hblank_end - 1) << 16));
3793 I915_WRITE(HSYNC(pipe),
3794 (adjusted_mode->crtc_hsync_start - 1) |
3795 ((adjusted_mode->crtc_hsync_end - 1) << 16));
3796
3797 I915_WRITE(VTOTAL(pipe),
3798 (adjusted_mode->crtc_vdisplay - 1) |
3799 ((adjusted_mode->crtc_vtotal - 1) << 16));
3800 I915_WRITE(VBLANK(pipe),
3801 (adjusted_mode->crtc_vblank_start - 1) |
3802 ((adjusted_mode->crtc_vblank_end - 1) << 16));
3803 I915_WRITE(VSYNC(pipe),
3804 (adjusted_mode->crtc_vsync_start - 1) |
3805 ((adjusted_mode->crtc_vsync_end - 1) << 16));
3806
3807 /* pipesrc and dspsize control the size that is scaled from,
3808 * which should always be the user's requested size.
3809 */
3810 I915_WRITE(DSPSIZE(plane),
3811 ((mode->vdisplay - 1) << 16) |
3812 (mode->hdisplay - 1));
3813 I915_WRITE(DSPPOS(plane), 0);
3814 I915_WRITE(PIPESRC(pipe),
3815 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
3816
3817 I915_WRITE(PIPECONF(pipe), pipeconf);
3818 POSTING_READ(PIPECONF(pipe));
3819 intel_enable_pipe(dev_priv, pipe, false);
3820
3821 intel_wait_for_vblank(dev, pipe);
3822
3823 I915_WRITE(DSPCNTR(plane), dspcntr);
3824 POSTING_READ(DSPCNTR(plane));
3825 intel_enable_plane(dev_priv, plane, pipe);
3826
3827 ret = intel_pipe_set_base(crtc, x, y, old_fb);
3828
3829 intel_update_watermarks(dev);
3830
3831 return ret;
3832 }
3833
3834 /*
3835 * Initialize reference clocks when the driver loads
3836 */
3837 void ironlake_init_pch_refclk(struct drm_device *dev)
3838 {
3839 struct drm_i915_private *dev_priv = dev->dev_private;
3840 struct drm_mode_config *mode_config = &dev->mode_config;
3841 struct intel_encoder *encoder;
3842 u32 temp;
3843 bool has_lvds = false;
3844 bool has_cpu_edp = false;
3845 bool has_pch_edp = false;
3846 bool has_panel = false;
3847 bool has_ck505 = false;
3848 bool can_ssc = false;
3849
3850 /* We need to take the global config into account */
3851 list_for_each_entry(encoder, &mode_config->encoder_list,
3852 base.head) {
3853 switch (encoder->type) {
3854 case INTEL_OUTPUT_LVDS:
3855 has_panel = true;
3856 has_lvds = true;
3857 break;
3858 case INTEL_OUTPUT_EDP:
3859 has_panel = true;
3860 if (intel_encoder_is_pch_edp(&encoder->base))
3861 has_pch_edp = true;
3862 else
3863 has_cpu_edp = true;
3864 break;
3865 }
3866 }
3867
3868 if (HAS_PCH_IBX(dev)) {
3869 has_ck505 = dev_priv->display_clock_mode;
3870 can_ssc = has_ck505;
3871 } else {
3872 has_ck505 = false;
3873 can_ssc = true;
3874 }
3875
3876 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
3877 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
3878 has_ck505);
3879
3880 /* Ironlake: try to setup display ref clock before DPLL
3881 * enabling. This is only under driver's control after
3882 * PCH B stepping, previous chipset stepping should be
3883 * ignoring this setting.
3884 */
3885 temp = I915_READ(PCH_DREF_CONTROL);
3886 /* Always enable nonspread source */
3887 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3888
3889 if (has_ck505)
3890 temp |= DREF_NONSPREAD_CK505_ENABLE;
3891 else
3892 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3893
3894 if (has_panel) {
3895 temp &= ~DREF_SSC_SOURCE_MASK;
3896 temp |= DREF_SSC_SOURCE_ENABLE;
3897
3898 /* SSC must be turned on before enabling the CPU output */
3899 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
3900 DRM_DEBUG_KMS("Using SSC on panel\n");
3901 temp |= DREF_SSC1_ENABLE;
3902 } else
3903 temp &= ~DREF_SSC1_ENABLE;
3904
3905 /* Get SSC going before enabling the outputs */
3906 I915_WRITE(PCH_DREF_CONTROL, temp);
3907 POSTING_READ(PCH_DREF_CONTROL);
3908 udelay(200);
3909
3910 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3911
3912 /* Enable CPU source on CPU attached eDP */
3913 if (has_cpu_edp) {
3914 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
3915 DRM_DEBUG_KMS("Using SSC on eDP\n");
3916 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3917 }
3918 else
3919 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3920 } else
3921 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
3922
3923 I915_WRITE(PCH_DREF_CONTROL, temp);
3924 POSTING_READ(PCH_DREF_CONTROL);
3925 udelay(200);
3926 } else {
3927 DRM_DEBUG_KMS("Disabling SSC entirely\n");
3928
3929 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3930
3931 /* Turn off CPU output */
3932 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
3933
3934 I915_WRITE(PCH_DREF_CONTROL, temp);
3935 POSTING_READ(PCH_DREF_CONTROL);
3936 udelay(200);
3937
3938 /* Turn off the SSC source */
3939 temp &= ~DREF_SSC_SOURCE_MASK;
3940 temp |= DREF_SSC_SOURCE_DISABLE;
3941
3942 /* Turn off SSC1 */
3943 temp &= ~ DREF_SSC1_ENABLE;
3944
3945 I915_WRITE(PCH_DREF_CONTROL, temp);
3946 POSTING_READ(PCH_DREF_CONTROL);
3947 udelay(200);
3948 }
3949 }
3950
3951 static int ironlake_get_refclk(struct drm_crtc *crtc)
3952 {
3953 struct drm_device *dev = crtc->dev;
3954 struct drm_i915_private *dev_priv = dev->dev_private;
3955 struct intel_encoder *encoder;
3956 struct drm_mode_config *mode_config = &dev->mode_config;
3957 struct intel_encoder *edp_encoder = NULL;
3958 int num_connectors = 0;
3959 bool is_lvds = false;
3960
3961 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3962 if (encoder->base.crtc != crtc)
3963 continue;
3964
3965 switch (encoder->type) {
3966 case INTEL_OUTPUT_LVDS:
3967 is_lvds = true;
3968 break;
3969 case INTEL_OUTPUT_EDP:
3970 edp_encoder = encoder;
3971 break;
3972 }
3973 num_connectors++;
3974 }
3975
3976 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3977 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3978 dev_priv->lvds_ssc_freq);
3979 return dev_priv->lvds_ssc_freq * 1000;
3980 }
3981
3982 return 120000;
3983 }
3984
3985 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
3986 struct drm_display_mode *mode,
3987 struct drm_display_mode *adjusted_mode,
3988 int x, int y,
3989 struct drm_framebuffer *old_fb)
3990 {
3991 struct drm_device *dev = crtc->dev;
3992 struct drm_i915_private *dev_priv = dev->dev_private;
3993 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3994 int pipe = intel_crtc->pipe;
3995 int plane = intel_crtc->plane;
3996 int refclk, num_connectors = 0;
3997 intel_clock_t clock, reduced_clock;
3998 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
3999 bool ok, has_reduced_clock = false, is_sdvo = false;
4000 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4001 struct drm_mode_config *mode_config = &dev->mode_config;
4002 struct intel_encoder *encoder, *edp_encoder = NULL;
4003 const intel_limit_t *limit;
4004 int ret;
4005 struct fdi_m_n m_n = {0};
4006 u32 temp;
4007 int target_clock, pixel_multiplier, lane, link_bw, factor;
4008 unsigned int pipe_bpp;
4009 bool dither;
4010 bool is_cpu_edp = false, is_pch_edp = false;
4011
4012 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4013 if (encoder->base.crtc != crtc)
4014 continue;
4015
4016 switch (encoder->type) {
4017 case INTEL_OUTPUT_LVDS:
4018 is_lvds = true;
4019 break;
4020 case INTEL_OUTPUT_SDVO:
4021 case INTEL_OUTPUT_HDMI:
4022 is_sdvo = true;
4023 if (encoder->needs_tv_clock)
4024 is_tv = true;
4025 break;
4026 case INTEL_OUTPUT_TVOUT:
4027 is_tv = true;
4028 break;
4029 case INTEL_OUTPUT_ANALOG:
4030 is_crt = true;
4031 break;
4032 case INTEL_OUTPUT_DISPLAYPORT:
4033 is_dp = true;
4034 break;
4035 case INTEL_OUTPUT_EDP:
4036 is_dp = true;
4037 if (intel_encoder_is_pch_edp(&encoder->base))
4038 is_pch_edp = true;
4039 else
4040 is_cpu_edp = true;
4041 edp_encoder = encoder;
4042 break;
4043 }
4044
4045 num_connectors++;
4046 }
4047
4048 refclk = ironlake_get_refclk(crtc);
4049
4050 /*
4051 * Returns a set of divisors for the desired target clock with the given
4052 * refclk, or FALSE. The returned values represent the clock equation:
4053 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4054 */
4055 limit = intel_limit(crtc, refclk);
4056 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4057 &clock);
4058 if (!ok) {
4059 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4060 return -EINVAL;
4061 }
4062
4063 /* Ensure that the cursor is valid for the new mode before changing... */
4064 intel_crtc_update_cursor(crtc, true);
4065
4066 if (is_lvds && dev_priv->lvds_downclock_avail) {
4067 /*
4068 * Ensure we match the reduced clock's P to the target clock.
4069 * If the clocks don't match, we can't switch the display clock
4070 * by using the FP0/FP1. In such case we will disable the LVDS
4071 * downclock feature.
4072 */
4073 has_reduced_clock = limit->find_pll(limit, crtc,
4074 dev_priv->lvds_downclock,
4075 refclk,
4076 &clock,
4077 &reduced_clock);
4078 }
4079 /* SDVO TV has fixed PLL values depend on its clock range,
4080 this mirrors vbios setting. */
4081 if (is_sdvo && is_tv) {
4082 if (adjusted_mode->clock >= 100000
4083 && adjusted_mode->clock < 140500) {
4084 clock.p1 = 2;
4085 clock.p2 = 10;
4086 clock.n = 3;
4087 clock.m1 = 16;
4088 clock.m2 = 8;
4089 } else if (adjusted_mode->clock >= 140500
4090 && adjusted_mode->clock <= 200000) {
4091 clock.p1 = 1;
4092 clock.p2 = 10;
4093 clock.n = 6;
4094 clock.m1 = 12;
4095 clock.m2 = 8;
4096 }
4097 }
4098
4099 /* FDI link */
4100 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4101 lane = 0;
4102 /* CPU eDP doesn't require FDI link, so just set DP M/N
4103 according to current link config */
4104 if (is_cpu_edp) {
4105 target_clock = mode->clock;
4106 intel_edp_link_config(edp_encoder, &lane, &link_bw);
4107 } else {
4108 /* [e]DP over FDI requires target mode clock
4109 instead of link clock */
4110 if (is_dp)
4111 target_clock = mode->clock;
4112 else
4113 target_clock = adjusted_mode->clock;
4114
4115 /* FDI is a binary signal running at ~2.7GHz, encoding
4116 * each output octet as 10 bits. The actual frequency
4117 * is stored as a divider into a 100MHz clock, and the
4118 * mode pixel clock is stored in units of 1KHz.
4119 * Hence the bw of each lane in terms of the mode signal
4120 * is:
4121 */
4122 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4123 }
4124
4125 /* determine panel color depth */
4126 temp = I915_READ(PIPECONF(pipe));
4127 temp &= ~PIPE_BPC_MASK;
4128 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
4129 switch (pipe_bpp) {
4130 case 18:
4131 temp |= PIPE_6BPC;
4132 break;
4133 case 24:
4134 temp |= PIPE_8BPC;
4135 break;
4136 case 30:
4137 temp |= PIPE_10BPC;
4138 break;
4139 case 36:
4140 temp |= PIPE_12BPC;
4141 break;
4142 default:
4143 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4144 pipe_bpp);
4145 temp |= PIPE_8BPC;
4146 pipe_bpp = 24;
4147 break;
4148 }
4149
4150 intel_crtc->bpp = pipe_bpp;
4151 I915_WRITE(PIPECONF(pipe), temp);
4152
4153 if (!lane) {
4154 /*
4155 * Account for spread spectrum to avoid
4156 * oversubscribing the link. Max center spread
4157 * is 2.5%; use 5% for safety's sake.
4158 */
4159 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
4160 lane = bps / (link_bw * 8) + 1;
4161 }
4162
4163 intel_crtc->fdi_lanes = lane;
4164
4165 if (pixel_multiplier > 1)
4166 link_bw *= pixel_multiplier;
4167 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4168 &m_n);
4169
4170 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4171 if (has_reduced_clock)
4172 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4173 reduced_clock.m2;
4174
4175 /* Enable autotuning of the PLL clock (if permissible) */
4176 factor = 21;
4177 if (is_lvds) {
4178 if ((intel_panel_use_ssc(dev_priv) &&
4179 dev_priv->lvds_ssc_freq == 100) ||
4180 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4181 factor = 25;
4182 } else if (is_sdvo && is_tv)
4183 factor = 20;
4184
4185 if (clock.m < factor * clock.n)
4186 fp |= FP_CB_TUNE;
4187
4188 dpll = 0;
4189
4190 if (is_lvds)
4191 dpll |= DPLLB_MODE_LVDS;
4192 else
4193 dpll |= DPLLB_MODE_DAC_SERIAL;
4194 if (is_sdvo) {
4195 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4196 if (pixel_multiplier > 1) {
4197 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4198 }
4199 dpll |= DPLL_DVO_HIGH_SPEED;
4200 }
4201 if (is_dp && !is_cpu_edp)
4202 dpll |= DPLL_DVO_HIGH_SPEED;
4203
4204 /* compute bitmask from p1 value */
4205 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4206 /* also FPA1 */
4207 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4208
4209 switch (clock.p2) {
4210 case 5:
4211 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4212 break;
4213 case 7:
4214 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4215 break;
4216 case 10:
4217 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4218 break;
4219 case 14:
4220 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4221 break;
4222 }
4223
4224 if (is_sdvo && is_tv)
4225 dpll |= PLL_REF_INPUT_TVCLKINBC;
4226 else if (is_tv)
4227 /* XXX: just matching BIOS for now */
4228 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4229 dpll |= 3;
4230 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4231 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4232 else
4233 dpll |= PLL_REF_INPUT_DREFCLK;
4234
4235 /* setup pipeconf */
4236 pipeconf = I915_READ(PIPECONF(pipe));
4237
4238 /* Set up the display plane register */
4239 dspcntr = DISPPLANE_GAMMA_ENABLE;
4240
4241 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
4242 drm_mode_debug_printmodeline(mode);
4243
4244 /* PCH eDP needs FDI, but CPU eDP does not */
4245 if (!intel_crtc->no_pll) {
4246 if (!is_cpu_edp) {
4247 I915_WRITE(PCH_FP0(pipe), fp);
4248 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4249
4250 POSTING_READ(PCH_DPLL(pipe));
4251 udelay(150);
4252 }
4253 } else {
4254 if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
4255 fp == I915_READ(PCH_FP0(0))) {
4256 intel_crtc->use_pll_a = true;
4257 DRM_DEBUG_KMS("using pipe a dpll\n");
4258 } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
4259 fp == I915_READ(PCH_FP0(1))) {
4260 intel_crtc->use_pll_a = false;
4261 DRM_DEBUG_KMS("using pipe b dpll\n");
4262 } else {
4263 DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
4264 return -EINVAL;
4265 }
4266 }
4267
4268 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4269 * This is an exception to the general rule that mode_set doesn't turn
4270 * things on.
4271 */
4272 if (is_lvds) {
4273 temp = I915_READ(PCH_LVDS);
4274 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4275 if (HAS_PCH_CPT(dev)) {
4276 temp &= ~PORT_TRANS_SEL_MASK;
4277 temp |= PORT_TRANS_SEL_CPT(pipe);
4278 } else {
4279 if (pipe == 1)
4280 temp |= LVDS_PIPEB_SELECT;
4281 else
4282 temp &= ~LVDS_PIPEB_SELECT;
4283 }
4284
4285 /* set the corresponsding LVDS_BORDER bit */
4286 temp |= dev_priv->lvds_border_bits;
4287 /* Set the B0-B3 data pairs corresponding to whether we're going to
4288 * set the DPLLs for dual-channel mode or not.
4289 */
4290 if (clock.p2 == 7)
4291 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4292 else
4293 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4294
4295 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4296 * appropriately here, but we need to look more thoroughly into how
4297 * panels behave in the two modes.
4298 */
4299 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4300 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4301 temp |= LVDS_HSYNC_POLARITY;
4302 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4303 temp |= LVDS_VSYNC_POLARITY;
4304 I915_WRITE(PCH_LVDS, temp);
4305 }
4306
4307 pipeconf &= ~PIPECONF_DITHER_EN;
4308 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4309 if ((is_lvds && dev_priv->lvds_dither) || dither) {
4310 pipeconf |= PIPECONF_DITHER_EN;
4311 pipeconf |= PIPECONF_DITHER_TYPE_SP;
4312 }
4313 if (is_dp && !is_cpu_edp) {
4314 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4315 } else {
4316 /* For non-DP output, clear any trans DP clock recovery setting.*/
4317 I915_WRITE(TRANSDATA_M1(pipe), 0);
4318 I915_WRITE(TRANSDATA_N1(pipe), 0);
4319 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4320 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
4321 }
4322
4323 if (!intel_crtc->no_pll && (!edp_encoder || is_pch_edp)) {
4324 I915_WRITE(PCH_DPLL(pipe), dpll);
4325
4326 /* Wait for the clocks to stabilize. */
4327 POSTING_READ(PCH_DPLL(pipe));
4328 udelay(150);
4329
4330 /* The pixel multiplier can only be updated once the
4331 * DPLL is enabled and the clocks are stable.
4332 *
4333 * So write it again.
4334 */
4335 I915_WRITE(PCH_DPLL(pipe), dpll);
4336 }
4337
4338 intel_crtc->lowfreq_avail = false;
4339 if (!intel_crtc->no_pll) {
4340 if (is_lvds && has_reduced_clock && i915_powersave) {
4341 I915_WRITE(PCH_FP1(pipe), fp2);
4342 intel_crtc->lowfreq_avail = true;
4343 if (HAS_PIPE_CXSR(dev)) {
4344 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4345 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4346 }
4347 } else {
4348 I915_WRITE(PCH_FP1(pipe), fp);
4349 if (HAS_PIPE_CXSR(dev)) {
4350 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4351 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4352 }
4353 }
4354 }
4355
4356 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4357 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4358 pipeconf |= PIPECONF_INTERLACED_ILK;
4359 /* the chip adds 2 halflines automatically */
4360 adjusted_mode->crtc_vtotal -= 1;
4361 adjusted_mode->crtc_vblank_end -= 1;
4362 I915_WRITE(VSYNCSHIFT(pipe),
4363 adjusted_mode->crtc_hsync_start
4364 - adjusted_mode->crtc_htotal/2);
4365 } else {
4366 pipeconf |= PIPECONF_PROGRESSIVE;
4367 I915_WRITE(VSYNCSHIFT(pipe), 0);
4368 }
4369
4370 I915_WRITE(HTOTAL(pipe),
4371 (adjusted_mode->crtc_hdisplay - 1) |
4372 ((adjusted_mode->crtc_htotal - 1) << 16));
4373 I915_WRITE(HBLANK(pipe),
4374 (adjusted_mode->crtc_hblank_start - 1) |
4375 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4376 I915_WRITE(HSYNC(pipe),
4377 (adjusted_mode->crtc_hsync_start - 1) |
4378 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4379
4380 I915_WRITE(VTOTAL(pipe),
4381 (adjusted_mode->crtc_vdisplay - 1) |
4382 ((adjusted_mode->crtc_vtotal - 1) << 16));
4383 I915_WRITE(VBLANK(pipe),
4384 (adjusted_mode->crtc_vblank_start - 1) |
4385 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4386 I915_WRITE(VSYNC(pipe),
4387 (adjusted_mode->crtc_vsync_start - 1) |
4388 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4389
4390 /* pipesrc controls the size that is scaled from, which should
4391 * always be the user's requested size.
4392 */
4393 I915_WRITE(PIPESRC(pipe),
4394 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4395
4396 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4397 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4398 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4399 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4400
4401 if (is_cpu_edp)
4402 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4403
4404 I915_WRITE(PIPECONF(pipe), pipeconf);
4405 POSTING_READ(PIPECONF(pipe));
4406
4407 intel_wait_for_vblank(dev, pipe);
4408
4409 I915_WRITE(DSPCNTR(plane), dspcntr);
4410 POSTING_READ(DSPCNTR(plane));
4411
4412 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4413
4414 intel_update_watermarks(dev);
4415
4416 return ret;
4417 }
4418
4419 static int intel_crtc_mode_set(struct drm_crtc *crtc,
4420 struct drm_display_mode *mode,
4421 struct drm_display_mode *adjusted_mode,
4422 int x, int y,
4423 struct drm_framebuffer *old_fb)
4424 {
4425 struct drm_device *dev = crtc->dev;
4426 struct drm_i915_private *dev_priv = dev->dev_private;
4427 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4428 int pipe = intel_crtc->pipe;
4429 int ret;
4430
4431 drm_vblank_pre_modeset(dev, pipe);
4432
4433 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
4434 x, y, old_fb);
4435 drm_vblank_post_modeset(dev, pipe);
4436
4437 if (ret)
4438 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4439 else
4440 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
4441
4442 return ret;
4443 }
4444
4445 static bool intel_eld_uptodate(struct drm_connector *connector,
4446 int reg_eldv, uint32_t bits_eldv,
4447 int reg_elda, uint32_t bits_elda,
4448 int reg_edid)
4449 {
4450 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4451 uint8_t *eld = connector->eld;
4452 uint32_t i;
4453
4454 i = I915_READ(reg_eldv);
4455 i &= bits_eldv;
4456
4457 if (!eld[0])
4458 return !i;
4459
4460 if (!i)
4461 return false;
4462
4463 i = I915_READ(reg_elda);
4464 i &= ~bits_elda;
4465 I915_WRITE(reg_elda, i);
4466
4467 for (i = 0; i < eld[2]; i++)
4468 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
4469 return false;
4470
4471 return true;
4472 }
4473
4474 static void g4x_write_eld(struct drm_connector *connector,
4475 struct drm_crtc *crtc)
4476 {
4477 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4478 uint8_t *eld = connector->eld;
4479 uint32_t eldv;
4480 uint32_t len;
4481 uint32_t i;
4482
4483 i = I915_READ(G4X_AUD_VID_DID);
4484
4485 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
4486 eldv = G4X_ELDV_DEVCL_DEVBLC;
4487 else
4488 eldv = G4X_ELDV_DEVCTG;
4489
4490 if (intel_eld_uptodate(connector,
4491 G4X_AUD_CNTL_ST, eldv,
4492 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
4493 G4X_HDMIW_HDMIEDID))
4494 return;
4495
4496 i = I915_READ(G4X_AUD_CNTL_ST);
4497 i &= ~(eldv | G4X_ELD_ADDR);
4498 len = (i >> 9) & 0x1f; /* ELD buffer size */
4499 I915_WRITE(G4X_AUD_CNTL_ST, i);
4500
4501 if (!eld[0])
4502 return;
4503
4504 len = min_t(uint8_t, eld[2], len);
4505 DRM_DEBUG_DRIVER("ELD size %d\n", len);
4506 for (i = 0; i < len; i++)
4507 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
4508
4509 i = I915_READ(G4X_AUD_CNTL_ST);
4510 i |= eldv;
4511 I915_WRITE(G4X_AUD_CNTL_ST, i);
4512 }
4513
4514 static void ironlake_write_eld(struct drm_connector *connector,
4515 struct drm_crtc *crtc)
4516 {
4517 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4518 uint8_t *eld = connector->eld;
4519 uint32_t eldv;
4520 uint32_t i;
4521 int len;
4522 int hdmiw_hdmiedid;
4523 int aud_config;
4524 int aud_cntl_st;
4525 int aud_cntrl_st2;
4526
4527 if (HAS_PCH_IBX(connector->dev)) {
4528 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
4529 aud_config = IBX_AUD_CONFIG_A;
4530 aud_cntl_st = IBX_AUD_CNTL_ST_A;
4531 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
4532 } else {
4533 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
4534 aud_config = CPT_AUD_CONFIG_A;
4535 aud_cntl_st = CPT_AUD_CNTL_ST_A;
4536 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
4537 }
4538
4539 i = to_intel_crtc(crtc)->pipe;
4540 hdmiw_hdmiedid += i * 0x100;
4541 aud_cntl_st += i * 0x100;
4542 aud_config += i * 0x100;
4543
4544 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
4545
4546 i = I915_READ(aud_cntl_st);
4547 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
4548 if (!i) {
4549 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
4550 /* operate blindly on all ports */
4551 eldv = IBX_ELD_VALIDB;
4552 eldv |= IBX_ELD_VALIDB << 4;
4553 eldv |= IBX_ELD_VALIDB << 8;
4554 } else {
4555 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
4556 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
4557 }
4558
4559 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
4560 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
4561 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
4562 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
4563 } else
4564 I915_WRITE(aud_config, 0);
4565
4566 if (intel_eld_uptodate(connector,
4567 aud_cntrl_st2, eldv,
4568 aud_cntl_st, IBX_ELD_ADDRESS,
4569 hdmiw_hdmiedid))
4570 return;
4571
4572 i = I915_READ(aud_cntrl_st2);
4573 i &= ~eldv;
4574 I915_WRITE(aud_cntrl_st2, i);
4575
4576 if (!eld[0])
4577 return;
4578
4579 i = I915_READ(aud_cntl_st);
4580 i &= ~IBX_ELD_ADDRESS;
4581 I915_WRITE(aud_cntl_st, i);
4582
4583 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
4584 DRM_DEBUG_DRIVER("ELD size %d\n", len);
4585 for (i = 0; i < len; i++)
4586 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
4587
4588 i = I915_READ(aud_cntrl_st2);
4589 i |= eldv;
4590 I915_WRITE(aud_cntrl_st2, i);
4591 }
4592
4593 void intel_write_eld(struct drm_encoder *encoder,
4594 struct drm_display_mode *mode)
4595 {
4596 struct drm_crtc *crtc = encoder->crtc;
4597 struct drm_connector *connector;
4598 struct drm_device *dev = encoder->dev;
4599 struct drm_i915_private *dev_priv = dev->dev_private;
4600
4601 connector = drm_select_eld(encoder, mode);
4602 if (!connector)
4603 return;
4604
4605 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
4606 connector->base.id,
4607 drm_get_connector_name(connector),
4608 connector->encoder->base.id,
4609 drm_get_encoder_name(connector->encoder));
4610
4611 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
4612
4613 if (dev_priv->display.write_eld)
4614 dev_priv->display.write_eld(connector, crtc);
4615 }
4616
4617 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4618 void intel_crtc_load_lut(struct drm_crtc *crtc)
4619 {
4620 struct drm_device *dev = crtc->dev;
4621 struct drm_i915_private *dev_priv = dev->dev_private;
4622 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4623 int palreg = PALETTE(intel_crtc->pipe);
4624 int i;
4625
4626 /* The clocks have to be on to load the palette. */
4627 if (!crtc->enabled || !intel_crtc->active)
4628 return;
4629
4630 /* use legacy palette for Ironlake */
4631 if (HAS_PCH_SPLIT(dev))
4632 palreg = LGC_PALETTE(intel_crtc->pipe);
4633
4634 for (i = 0; i < 256; i++) {
4635 I915_WRITE(palreg + 4 * i,
4636 (intel_crtc->lut_r[i] << 16) |
4637 (intel_crtc->lut_g[i] << 8) |
4638 intel_crtc->lut_b[i]);
4639 }
4640 }
4641
4642 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4643 {
4644 struct drm_device *dev = crtc->dev;
4645 struct drm_i915_private *dev_priv = dev->dev_private;
4646 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4647 bool visible = base != 0;
4648 u32 cntl;
4649
4650 if (intel_crtc->cursor_visible == visible)
4651 return;
4652
4653 cntl = I915_READ(_CURACNTR);
4654 if (visible) {
4655 /* On these chipsets we can only modify the base whilst
4656 * the cursor is disabled.
4657 */
4658 I915_WRITE(_CURABASE, base);
4659
4660 cntl &= ~(CURSOR_FORMAT_MASK);
4661 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4662 cntl |= CURSOR_ENABLE |
4663 CURSOR_GAMMA_ENABLE |
4664 CURSOR_FORMAT_ARGB;
4665 } else
4666 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4667 I915_WRITE(_CURACNTR, cntl);
4668
4669 intel_crtc->cursor_visible = visible;
4670 }
4671
4672 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4673 {
4674 struct drm_device *dev = crtc->dev;
4675 struct drm_i915_private *dev_priv = dev->dev_private;
4676 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4677 int pipe = intel_crtc->pipe;
4678 bool visible = base != 0;
4679
4680 if (intel_crtc->cursor_visible != visible) {
4681 uint32_t cntl = I915_READ(CURCNTR(pipe));
4682 if (base) {
4683 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4684 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4685 cntl |= pipe << 28; /* Connect to correct pipe */
4686 } else {
4687 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4688 cntl |= CURSOR_MODE_DISABLE;
4689 }
4690 I915_WRITE(CURCNTR(pipe), cntl);
4691
4692 intel_crtc->cursor_visible = visible;
4693 }
4694 /* and commit changes on next vblank */
4695 I915_WRITE(CURBASE(pipe), base);
4696 }
4697
4698 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
4699 {
4700 struct drm_device *dev = crtc->dev;
4701 struct drm_i915_private *dev_priv = dev->dev_private;
4702 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4703 int pipe = intel_crtc->pipe;
4704 bool visible = base != 0;
4705
4706 if (intel_crtc->cursor_visible != visible) {
4707 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
4708 if (base) {
4709 cntl &= ~CURSOR_MODE;
4710 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4711 } else {
4712 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4713 cntl |= CURSOR_MODE_DISABLE;
4714 }
4715 I915_WRITE(CURCNTR_IVB(pipe), cntl);
4716
4717 intel_crtc->cursor_visible = visible;
4718 }
4719 /* and commit changes on next vblank */
4720 I915_WRITE(CURBASE_IVB(pipe), base);
4721 }
4722
4723 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4724 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
4725 bool on)
4726 {
4727 struct drm_device *dev = crtc->dev;
4728 struct drm_i915_private *dev_priv = dev->dev_private;
4729 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4730 int pipe = intel_crtc->pipe;
4731 int x = intel_crtc->cursor_x;
4732 int y = intel_crtc->cursor_y;
4733 u32 base, pos;
4734 bool visible;
4735
4736 pos = 0;
4737
4738 if (on && crtc->enabled && crtc->fb) {
4739 base = intel_crtc->cursor_addr;
4740 if (x > (int) crtc->fb->width)
4741 base = 0;
4742
4743 if (y > (int) crtc->fb->height)
4744 base = 0;
4745 } else
4746 base = 0;
4747
4748 if (x < 0) {
4749 if (x + intel_crtc->cursor_width < 0)
4750 base = 0;
4751
4752 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4753 x = -x;
4754 }
4755 pos |= x << CURSOR_X_SHIFT;
4756
4757 if (y < 0) {
4758 if (y + intel_crtc->cursor_height < 0)
4759 base = 0;
4760
4761 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4762 y = -y;
4763 }
4764 pos |= y << CURSOR_Y_SHIFT;
4765
4766 visible = base != 0;
4767 if (!visible && !intel_crtc->cursor_visible)
4768 return;
4769
4770 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
4771 I915_WRITE(CURPOS_IVB(pipe), pos);
4772 ivb_update_cursor(crtc, base);
4773 } else {
4774 I915_WRITE(CURPOS(pipe), pos);
4775 if (IS_845G(dev) || IS_I865G(dev))
4776 i845_update_cursor(crtc, base);
4777 else
4778 i9xx_update_cursor(crtc, base);
4779 }
4780
4781 if (visible)
4782 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4783 }
4784
4785 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4786 struct drm_file *file,
4787 uint32_t handle,
4788 uint32_t width, uint32_t height)
4789 {
4790 struct drm_device *dev = crtc->dev;
4791 struct drm_i915_private *dev_priv = dev->dev_private;
4792 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4793 struct drm_i915_gem_object *obj;
4794 uint32_t addr;
4795 int ret;
4796
4797 DRM_DEBUG_KMS("\n");
4798
4799 /* if we want to turn off the cursor ignore width and height */
4800 if (!handle) {
4801 DRM_DEBUG_KMS("cursor off\n");
4802 addr = 0;
4803 obj = NULL;
4804 mutex_lock(&dev->struct_mutex);
4805 goto finish;
4806 }
4807
4808 /* Currently we only support 64x64 cursors */
4809 if (width != 64 || height != 64) {
4810 DRM_ERROR("we currently only support 64x64 cursors\n");
4811 return -EINVAL;
4812 }
4813
4814 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
4815 if (&obj->base == NULL)
4816 return -ENOENT;
4817
4818 if (obj->base.size < width * height * 4) {
4819 DRM_ERROR("buffer is to small\n");
4820 ret = -ENOMEM;
4821 goto fail;
4822 }
4823
4824 /* we only need to pin inside GTT if cursor is non-phy */
4825 mutex_lock(&dev->struct_mutex);
4826 if (!dev_priv->info->cursor_needs_physical) {
4827 if (obj->tiling_mode) {
4828 DRM_ERROR("cursor cannot be tiled\n");
4829 ret = -EINVAL;
4830 goto fail_locked;
4831 }
4832
4833 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
4834 if (ret) {
4835 DRM_ERROR("failed to move cursor bo into the GTT\n");
4836 goto fail_locked;
4837 }
4838
4839 ret = i915_gem_object_put_fence(obj);
4840 if (ret) {
4841 DRM_ERROR("failed to release fence for cursor");
4842 goto fail_unpin;
4843 }
4844
4845 addr = obj->gtt_offset;
4846 } else {
4847 int align = IS_I830(dev) ? 16 * 1024 : 256;
4848 ret = i915_gem_attach_phys_object(dev, obj,
4849 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4850 align);
4851 if (ret) {
4852 DRM_ERROR("failed to attach phys object\n");
4853 goto fail_locked;
4854 }
4855 addr = obj->phys_obj->handle->busaddr;
4856 }
4857
4858 if (IS_GEN2(dev))
4859 I915_WRITE(CURSIZE, (height << 12) | width);
4860
4861 finish:
4862 if (intel_crtc->cursor_bo) {
4863 if (dev_priv->info->cursor_needs_physical) {
4864 if (intel_crtc->cursor_bo != obj)
4865 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4866 } else
4867 i915_gem_object_unpin(intel_crtc->cursor_bo);
4868 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
4869 }
4870
4871 mutex_unlock(&dev->struct_mutex);
4872
4873 intel_crtc->cursor_addr = addr;
4874 intel_crtc->cursor_bo = obj;
4875 intel_crtc->cursor_width = width;
4876 intel_crtc->cursor_height = height;
4877
4878 intel_crtc_update_cursor(crtc, true);
4879
4880 return 0;
4881 fail_unpin:
4882 i915_gem_object_unpin(obj);
4883 fail_locked:
4884 mutex_unlock(&dev->struct_mutex);
4885 fail:
4886 drm_gem_object_unreference_unlocked(&obj->base);
4887 return ret;
4888 }
4889
4890 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4891 {
4892 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4893
4894 intel_crtc->cursor_x = x;
4895 intel_crtc->cursor_y = y;
4896
4897 intel_crtc_update_cursor(crtc, true);
4898
4899 return 0;
4900 }
4901
4902 /** Sets the color ramps on behalf of RandR */
4903 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4904 u16 blue, int regno)
4905 {
4906 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4907
4908 intel_crtc->lut_r[regno] = red >> 8;
4909 intel_crtc->lut_g[regno] = green >> 8;
4910 intel_crtc->lut_b[regno] = blue >> 8;
4911 }
4912
4913 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4914 u16 *blue, int regno)
4915 {
4916 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4917
4918 *red = intel_crtc->lut_r[regno] << 8;
4919 *green = intel_crtc->lut_g[regno] << 8;
4920 *blue = intel_crtc->lut_b[regno] << 8;
4921 }
4922
4923 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4924 u16 *blue, uint32_t start, uint32_t size)
4925 {
4926 int end = (start + size > 256) ? 256 : start + size, i;
4927 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4928
4929 for (i = start; i < end; i++) {
4930 intel_crtc->lut_r[i] = red[i] >> 8;
4931 intel_crtc->lut_g[i] = green[i] >> 8;
4932 intel_crtc->lut_b[i] = blue[i] >> 8;
4933 }
4934
4935 intel_crtc_load_lut(crtc);
4936 }
4937
4938 /**
4939 * Get a pipe with a simple mode set on it for doing load-based monitor
4940 * detection.
4941 *
4942 * It will be up to the load-detect code to adjust the pipe as appropriate for
4943 * its requirements. The pipe will be connected to no other encoders.
4944 *
4945 * Currently this code will only succeed if there is a pipe with no encoders
4946 * configured for it. In the future, it could choose to temporarily disable
4947 * some outputs to free up a pipe for its use.
4948 *
4949 * \return crtc, or NULL if no pipes are available.
4950 */
4951
4952 /* VESA 640x480x72Hz mode to set on the pipe */
4953 static struct drm_display_mode load_detect_mode = {
4954 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4955 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4956 };
4957
4958 static struct drm_framebuffer *
4959 intel_framebuffer_create(struct drm_device *dev,
4960 struct drm_mode_fb_cmd2 *mode_cmd,
4961 struct drm_i915_gem_object *obj)
4962 {
4963 struct intel_framebuffer *intel_fb;
4964 int ret;
4965
4966 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
4967 if (!intel_fb) {
4968 drm_gem_object_unreference_unlocked(&obj->base);
4969 return ERR_PTR(-ENOMEM);
4970 }
4971
4972 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
4973 if (ret) {
4974 drm_gem_object_unreference_unlocked(&obj->base);
4975 kfree(intel_fb);
4976 return ERR_PTR(ret);
4977 }
4978
4979 return &intel_fb->base;
4980 }
4981
4982 static u32
4983 intel_framebuffer_pitch_for_width(int width, int bpp)
4984 {
4985 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
4986 return ALIGN(pitch, 64);
4987 }
4988
4989 static u32
4990 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
4991 {
4992 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
4993 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
4994 }
4995
4996 static struct drm_framebuffer *
4997 intel_framebuffer_create_for_mode(struct drm_device *dev,
4998 struct drm_display_mode *mode,
4999 int depth, int bpp)
5000 {
5001 struct drm_i915_gem_object *obj;
5002 struct drm_mode_fb_cmd2 mode_cmd;
5003
5004 obj = i915_gem_alloc_object(dev,
5005 intel_framebuffer_size_for_mode(mode, bpp));
5006 if (obj == NULL)
5007 return ERR_PTR(-ENOMEM);
5008
5009 mode_cmd.width = mode->hdisplay;
5010 mode_cmd.height = mode->vdisplay;
5011 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5012 bpp);
5013 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
5014
5015 return intel_framebuffer_create(dev, &mode_cmd, obj);
5016 }
5017
5018 static struct drm_framebuffer *
5019 mode_fits_in_fbdev(struct drm_device *dev,
5020 struct drm_display_mode *mode)
5021 {
5022 struct drm_i915_private *dev_priv = dev->dev_private;
5023 struct drm_i915_gem_object *obj;
5024 struct drm_framebuffer *fb;
5025
5026 if (dev_priv->fbdev == NULL)
5027 return NULL;
5028
5029 obj = dev_priv->fbdev->ifb.obj;
5030 if (obj == NULL)
5031 return NULL;
5032
5033 fb = &dev_priv->fbdev->ifb.base;
5034 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5035 fb->bits_per_pixel))
5036 return NULL;
5037
5038 if (obj->base.size < mode->vdisplay * fb->pitches[0])
5039 return NULL;
5040
5041 return fb;
5042 }
5043
5044 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5045 struct drm_connector *connector,
5046 struct drm_display_mode *mode,
5047 struct intel_load_detect_pipe *old)
5048 {
5049 struct intel_crtc *intel_crtc;
5050 struct drm_crtc *possible_crtc;
5051 struct drm_encoder *encoder = &intel_encoder->base;
5052 struct drm_crtc *crtc = NULL;
5053 struct drm_device *dev = encoder->dev;
5054 struct drm_framebuffer *old_fb;
5055 int i = -1;
5056
5057 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5058 connector->base.id, drm_get_connector_name(connector),
5059 encoder->base.id, drm_get_encoder_name(encoder));
5060
5061 /*
5062 * Algorithm gets a little messy:
5063 *
5064 * - if the connector already has an assigned crtc, use it (but make
5065 * sure it's on first)
5066 *
5067 * - try to find the first unused crtc that can drive this connector,
5068 * and use that if we find one
5069 */
5070
5071 /* See if we already have a CRTC for this connector */
5072 if (encoder->crtc) {
5073 crtc = encoder->crtc;
5074
5075 intel_crtc = to_intel_crtc(crtc);
5076 old->dpms_mode = intel_crtc->dpms_mode;
5077 old->load_detect_temp = false;
5078
5079 /* Make sure the crtc and connector are running */
5080 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5081 struct drm_encoder_helper_funcs *encoder_funcs;
5082 struct drm_crtc_helper_funcs *crtc_funcs;
5083
5084 crtc_funcs = crtc->helper_private;
5085 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5086
5087 encoder_funcs = encoder->helper_private;
5088 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5089 }
5090
5091 return true;
5092 }
5093
5094 /* Find an unused one (if possible) */
5095 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5096 i++;
5097 if (!(encoder->possible_crtcs & (1 << i)))
5098 continue;
5099 if (!possible_crtc->enabled) {
5100 crtc = possible_crtc;
5101 break;
5102 }
5103 }
5104
5105 /*
5106 * If we didn't find an unused CRTC, don't use any.
5107 */
5108 if (!crtc) {
5109 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5110 return false;
5111 }
5112
5113 encoder->crtc = crtc;
5114 connector->encoder = encoder;
5115
5116 intel_crtc = to_intel_crtc(crtc);
5117 old->dpms_mode = intel_crtc->dpms_mode;
5118 old->load_detect_temp = true;
5119 old->release_fb = NULL;
5120
5121 if (!mode)
5122 mode = &load_detect_mode;
5123
5124 old_fb = crtc->fb;
5125
5126 /* We need a framebuffer large enough to accommodate all accesses
5127 * that the plane may generate whilst we perform load detection.
5128 * We can not rely on the fbcon either being present (we get called
5129 * during its initialisation to detect all boot displays, or it may
5130 * not even exist) or that it is large enough to satisfy the
5131 * requested mode.
5132 */
5133 crtc->fb = mode_fits_in_fbdev(dev, mode);
5134 if (crtc->fb == NULL) {
5135 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5136 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5137 old->release_fb = crtc->fb;
5138 } else
5139 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5140 if (IS_ERR(crtc->fb)) {
5141 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5142 crtc->fb = old_fb;
5143 return false;
5144 }
5145
5146 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
5147 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
5148 if (old->release_fb)
5149 old->release_fb->funcs->destroy(old->release_fb);
5150 crtc->fb = old_fb;
5151 return false;
5152 }
5153
5154 /* let the connector get through one full cycle before testing */
5155 intel_wait_for_vblank(dev, intel_crtc->pipe);
5156
5157 return true;
5158 }
5159
5160 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
5161 struct drm_connector *connector,
5162 struct intel_load_detect_pipe *old)
5163 {
5164 struct drm_encoder *encoder = &intel_encoder->base;
5165 struct drm_device *dev = encoder->dev;
5166 struct drm_crtc *crtc = encoder->crtc;
5167 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5168 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5169
5170 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5171 connector->base.id, drm_get_connector_name(connector),
5172 encoder->base.id, drm_get_encoder_name(encoder));
5173
5174 if (old->load_detect_temp) {
5175 connector->encoder = NULL;
5176 drm_helper_disable_unused_functions(dev);
5177
5178 if (old->release_fb)
5179 old->release_fb->funcs->destroy(old->release_fb);
5180
5181 return;
5182 }
5183
5184 /* Switch crtc and encoder back off if necessary */
5185 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5186 encoder_funcs->dpms(encoder, old->dpms_mode);
5187 crtc_funcs->dpms(crtc, old->dpms_mode);
5188 }
5189 }
5190
5191 /* Returns the clock of the currently programmed mode of the given pipe. */
5192 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5193 {
5194 struct drm_i915_private *dev_priv = dev->dev_private;
5195 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5196 int pipe = intel_crtc->pipe;
5197 u32 dpll = I915_READ(DPLL(pipe));
5198 u32 fp;
5199 intel_clock_t clock;
5200
5201 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5202 fp = I915_READ(FP0(pipe));
5203 else
5204 fp = I915_READ(FP1(pipe));
5205
5206 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5207 if (IS_PINEVIEW(dev)) {
5208 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5209 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5210 } else {
5211 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5212 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5213 }
5214
5215 if (!IS_GEN2(dev)) {
5216 if (IS_PINEVIEW(dev))
5217 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5218 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
5219 else
5220 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5221 DPLL_FPA01_P1_POST_DIV_SHIFT);
5222
5223 switch (dpll & DPLL_MODE_MASK) {
5224 case DPLLB_MODE_DAC_SERIAL:
5225 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5226 5 : 10;
5227 break;
5228 case DPLLB_MODE_LVDS:
5229 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5230 7 : 14;
5231 break;
5232 default:
5233 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5234 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5235 return 0;
5236 }
5237
5238 /* XXX: Handle the 100Mhz refclk */
5239 intel_clock(dev, 96000, &clock);
5240 } else {
5241 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5242
5243 if (is_lvds) {
5244 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5245 DPLL_FPA01_P1_POST_DIV_SHIFT);
5246 clock.p2 = 14;
5247
5248 if ((dpll & PLL_REF_INPUT_MASK) ==
5249 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5250 /* XXX: might not be 66MHz */
5251 intel_clock(dev, 66000, &clock);
5252 } else
5253 intel_clock(dev, 48000, &clock);
5254 } else {
5255 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5256 clock.p1 = 2;
5257 else {
5258 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5259 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5260 }
5261 if (dpll & PLL_P2_DIVIDE_BY_4)
5262 clock.p2 = 4;
5263 else
5264 clock.p2 = 2;
5265
5266 intel_clock(dev, 48000, &clock);
5267 }
5268 }
5269
5270 /* XXX: It would be nice to validate the clocks, but we can't reuse
5271 * i830PllIsValid() because it relies on the xf86_config connector
5272 * configuration being accurate, which it isn't necessarily.
5273 */
5274
5275 return clock.dot;
5276 }
5277
5278 /** Returns the currently programmed mode of the given pipe. */
5279 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5280 struct drm_crtc *crtc)
5281 {
5282 struct drm_i915_private *dev_priv = dev->dev_private;
5283 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5284 int pipe = intel_crtc->pipe;
5285 struct drm_display_mode *mode;
5286 int htot = I915_READ(HTOTAL(pipe));
5287 int hsync = I915_READ(HSYNC(pipe));
5288 int vtot = I915_READ(VTOTAL(pipe));
5289 int vsync = I915_READ(VSYNC(pipe));
5290
5291 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5292 if (!mode)
5293 return NULL;
5294
5295 mode->clock = intel_crtc_clock_get(dev, crtc);
5296 mode->hdisplay = (htot & 0xffff) + 1;
5297 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5298 mode->hsync_start = (hsync & 0xffff) + 1;
5299 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5300 mode->vdisplay = (vtot & 0xffff) + 1;
5301 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5302 mode->vsync_start = (vsync & 0xffff) + 1;
5303 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5304
5305 drm_mode_set_name(mode);
5306 drm_mode_set_crtcinfo(mode, 0);
5307
5308 return mode;
5309 }
5310
5311 #define GPU_IDLE_TIMEOUT 500 /* ms */
5312
5313 /* When this timer fires, we've been idle for awhile */
5314 static void intel_gpu_idle_timer(unsigned long arg)
5315 {
5316 struct drm_device *dev = (struct drm_device *)arg;
5317 drm_i915_private_t *dev_priv = dev->dev_private;
5318
5319 if (!list_empty(&dev_priv->mm.active_list)) {
5320 /* Still processing requests, so just re-arm the timer. */
5321 mod_timer(&dev_priv->idle_timer, jiffies +
5322 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5323 return;
5324 }
5325
5326 dev_priv->busy = false;
5327 queue_work(dev_priv->wq, &dev_priv->idle_work);
5328 }
5329
5330 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
5331
5332 static void intel_crtc_idle_timer(unsigned long arg)
5333 {
5334 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5335 struct drm_crtc *crtc = &intel_crtc->base;
5336 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
5337 struct intel_framebuffer *intel_fb;
5338
5339 intel_fb = to_intel_framebuffer(crtc->fb);
5340 if (intel_fb && intel_fb->obj->active) {
5341 /* The framebuffer is still being accessed by the GPU. */
5342 mod_timer(&intel_crtc->idle_timer, jiffies +
5343 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5344 return;
5345 }
5346
5347 intel_crtc->busy = false;
5348 queue_work(dev_priv->wq, &dev_priv->idle_work);
5349 }
5350
5351 static void intel_increase_pllclock(struct drm_crtc *crtc)
5352 {
5353 struct drm_device *dev = crtc->dev;
5354 drm_i915_private_t *dev_priv = dev->dev_private;
5355 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5356 int pipe = intel_crtc->pipe;
5357 int dpll_reg = DPLL(pipe);
5358 int dpll;
5359
5360 if (HAS_PCH_SPLIT(dev))
5361 return;
5362
5363 if (!dev_priv->lvds_downclock_avail)
5364 return;
5365
5366 dpll = I915_READ(dpll_reg);
5367 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
5368 DRM_DEBUG_DRIVER("upclocking LVDS\n");
5369
5370 assert_panel_unlocked(dev_priv, pipe);
5371
5372 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5373 I915_WRITE(dpll_reg, dpll);
5374 intel_wait_for_vblank(dev, pipe);
5375
5376 dpll = I915_READ(dpll_reg);
5377 if (dpll & DISPLAY_RATE_SELECT_FPA1)
5378 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
5379 }
5380
5381 /* Schedule downclock */
5382 mod_timer(&intel_crtc->idle_timer, jiffies +
5383 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5384 }
5385
5386 static void intel_decrease_pllclock(struct drm_crtc *crtc)
5387 {
5388 struct drm_device *dev = crtc->dev;
5389 drm_i915_private_t *dev_priv = dev->dev_private;
5390 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5391
5392 if (HAS_PCH_SPLIT(dev))
5393 return;
5394
5395 if (!dev_priv->lvds_downclock_avail)
5396 return;
5397
5398 /*
5399 * Since this is called by a timer, we should never get here in
5400 * the manual case.
5401 */
5402 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
5403 int pipe = intel_crtc->pipe;
5404 int dpll_reg = DPLL(pipe);
5405 int dpll;
5406
5407 DRM_DEBUG_DRIVER("downclocking LVDS\n");
5408
5409 assert_panel_unlocked(dev_priv, pipe);
5410
5411 dpll = I915_READ(dpll_reg);
5412 dpll |= DISPLAY_RATE_SELECT_FPA1;
5413 I915_WRITE(dpll_reg, dpll);
5414 intel_wait_for_vblank(dev, pipe);
5415 dpll = I915_READ(dpll_reg);
5416 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
5417 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
5418 }
5419
5420 }
5421
5422 /**
5423 * intel_idle_update - adjust clocks for idleness
5424 * @work: work struct
5425 *
5426 * Either the GPU or display (or both) went idle. Check the busy status
5427 * here and adjust the CRTC and GPU clocks as necessary.
5428 */
5429 static void intel_idle_update(struct work_struct *work)
5430 {
5431 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
5432 idle_work);
5433 struct drm_device *dev = dev_priv->dev;
5434 struct drm_crtc *crtc;
5435 struct intel_crtc *intel_crtc;
5436
5437 if (!i915_powersave)
5438 return;
5439
5440 mutex_lock(&dev->struct_mutex);
5441
5442 i915_update_gfx_val(dev_priv);
5443
5444 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5445 /* Skip inactive CRTCs */
5446 if (!crtc->fb)
5447 continue;
5448
5449 intel_crtc = to_intel_crtc(crtc);
5450 if (!intel_crtc->busy)
5451 intel_decrease_pllclock(crtc);
5452 }
5453
5454
5455 mutex_unlock(&dev->struct_mutex);
5456 }
5457
5458 /**
5459 * intel_mark_busy - mark the GPU and possibly the display busy
5460 * @dev: drm device
5461 * @obj: object we're operating on
5462 *
5463 * Callers can use this function to indicate that the GPU is busy processing
5464 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
5465 * buffer), we'll also mark the display as busy, so we know to increase its
5466 * clock frequency.
5467 */
5468 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
5469 {
5470 drm_i915_private_t *dev_priv = dev->dev_private;
5471 struct drm_crtc *crtc = NULL;
5472 struct intel_framebuffer *intel_fb;
5473 struct intel_crtc *intel_crtc;
5474
5475 if (!drm_core_check_feature(dev, DRIVER_MODESET))
5476 return;
5477
5478 if (!dev_priv->busy)
5479 dev_priv->busy = true;
5480 else
5481 mod_timer(&dev_priv->idle_timer, jiffies +
5482 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5483
5484 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5485 if (!crtc->fb)
5486 continue;
5487
5488 intel_crtc = to_intel_crtc(crtc);
5489 intel_fb = to_intel_framebuffer(crtc->fb);
5490 if (intel_fb->obj == obj) {
5491 if (!intel_crtc->busy) {
5492 /* Non-busy -> busy, upclock */
5493 intel_increase_pllclock(crtc);
5494 intel_crtc->busy = true;
5495 } else {
5496 /* Busy -> busy, put off timer */
5497 mod_timer(&intel_crtc->idle_timer, jiffies +
5498 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5499 }
5500 }
5501 }
5502 }
5503
5504 static void intel_crtc_destroy(struct drm_crtc *crtc)
5505 {
5506 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5507 struct drm_device *dev = crtc->dev;
5508 struct intel_unpin_work *work;
5509 unsigned long flags;
5510
5511 spin_lock_irqsave(&dev->event_lock, flags);
5512 work = intel_crtc->unpin_work;
5513 intel_crtc->unpin_work = NULL;
5514 spin_unlock_irqrestore(&dev->event_lock, flags);
5515
5516 if (work) {
5517 cancel_work_sync(&work->work);
5518 kfree(work);
5519 }
5520
5521 drm_crtc_cleanup(crtc);
5522
5523 kfree(intel_crtc);
5524 }
5525
5526 static void intel_unpin_work_fn(struct work_struct *__work)
5527 {
5528 struct intel_unpin_work *work =
5529 container_of(__work, struct intel_unpin_work, work);
5530
5531 mutex_lock(&work->dev->struct_mutex);
5532 intel_unpin_fb_obj(work->old_fb_obj);
5533 drm_gem_object_unreference(&work->pending_flip_obj->base);
5534 drm_gem_object_unreference(&work->old_fb_obj->base);
5535
5536 intel_update_fbc(work->dev);
5537 mutex_unlock(&work->dev->struct_mutex);
5538 kfree(work);
5539 }
5540
5541 static void do_intel_finish_page_flip(struct drm_device *dev,
5542 struct drm_crtc *crtc)
5543 {
5544 drm_i915_private_t *dev_priv = dev->dev_private;
5545 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5546 struct intel_unpin_work *work;
5547 struct drm_i915_gem_object *obj;
5548 struct drm_pending_vblank_event *e;
5549 struct timeval tnow, tvbl;
5550 unsigned long flags;
5551
5552 /* Ignore early vblank irqs */
5553 if (intel_crtc == NULL)
5554 return;
5555
5556 do_gettimeofday(&tnow);
5557
5558 spin_lock_irqsave(&dev->event_lock, flags);
5559 work = intel_crtc->unpin_work;
5560 if (work == NULL || !work->pending) {
5561 spin_unlock_irqrestore(&dev->event_lock, flags);
5562 return;
5563 }
5564
5565 intel_crtc->unpin_work = NULL;
5566
5567 if (work->event) {
5568 e = work->event;
5569 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
5570
5571 /* Called before vblank count and timestamps have
5572 * been updated for the vblank interval of flip
5573 * completion? Need to increment vblank count and
5574 * add one videorefresh duration to returned timestamp
5575 * to account for this. We assume this happened if we
5576 * get called over 0.9 frame durations after the last
5577 * timestamped vblank.
5578 *
5579 * This calculation can not be used with vrefresh rates
5580 * below 5Hz (10Hz to be on the safe side) without
5581 * promoting to 64 integers.
5582 */
5583 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
5584 9 * crtc->framedur_ns) {
5585 e->event.sequence++;
5586 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
5587 crtc->framedur_ns);
5588 }
5589
5590 e->event.tv_sec = tvbl.tv_sec;
5591 e->event.tv_usec = tvbl.tv_usec;
5592
5593 list_add_tail(&e->base.link,
5594 &e->base.file_priv->event_list);
5595 wake_up_interruptible(&e->base.file_priv->event_wait);
5596 }
5597
5598 drm_vblank_put(dev, intel_crtc->pipe);
5599
5600 spin_unlock_irqrestore(&dev->event_lock, flags);
5601
5602 obj = work->old_fb_obj;
5603
5604 atomic_clear_mask(1 << intel_crtc->plane,
5605 &obj->pending_flip.counter);
5606 if (atomic_read(&obj->pending_flip) == 0)
5607 wake_up(&dev_priv->pending_flip_queue);
5608
5609 schedule_work(&work->work);
5610
5611 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
5612 }
5613
5614 void intel_finish_page_flip(struct drm_device *dev, int pipe)
5615 {
5616 drm_i915_private_t *dev_priv = dev->dev_private;
5617 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5618
5619 do_intel_finish_page_flip(dev, crtc);
5620 }
5621
5622 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5623 {
5624 drm_i915_private_t *dev_priv = dev->dev_private;
5625 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5626
5627 do_intel_finish_page_flip(dev, crtc);
5628 }
5629
5630 void intel_prepare_page_flip(struct drm_device *dev, int plane)
5631 {
5632 drm_i915_private_t *dev_priv = dev->dev_private;
5633 struct intel_crtc *intel_crtc =
5634 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5635 unsigned long flags;
5636
5637 spin_lock_irqsave(&dev->event_lock, flags);
5638 if (intel_crtc->unpin_work) {
5639 if ((++intel_crtc->unpin_work->pending) > 1)
5640 DRM_ERROR("Prepared flip multiple times\n");
5641 } else {
5642 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5643 }
5644 spin_unlock_irqrestore(&dev->event_lock, flags);
5645 }
5646
5647 static int intel_gen2_queue_flip(struct drm_device *dev,
5648 struct drm_crtc *crtc,
5649 struct drm_framebuffer *fb,
5650 struct drm_i915_gem_object *obj)
5651 {
5652 struct drm_i915_private *dev_priv = dev->dev_private;
5653 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5654 unsigned long offset;
5655 u32 flip_mask;
5656 int ret;
5657
5658 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
5659 if (ret)
5660 goto err;
5661
5662 /* Offset into the new buffer for cases of shared fbs between CRTCs */
5663 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
5664
5665 ret = BEGIN_LP_RING(6);
5666 if (ret)
5667 goto err_unpin;
5668
5669 /* Can't queue multiple flips, so wait for the previous
5670 * one to finish before executing the next.
5671 */
5672 if (intel_crtc->plane)
5673 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5674 else
5675 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5676 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5677 OUT_RING(MI_NOOP);
5678 OUT_RING(MI_DISPLAY_FLIP |
5679 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5680 OUT_RING(fb->pitches[0]);
5681 OUT_RING(obj->gtt_offset + offset);
5682 OUT_RING(0); /* aux display base address, unused */
5683 ADVANCE_LP_RING();
5684 return 0;
5685
5686 err_unpin:
5687 intel_unpin_fb_obj(obj);
5688 err:
5689 return ret;
5690 }
5691
5692 static int intel_gen3_queue_flip(struct drm_device *dev,
5693 struct drm_crtc *crtc,
5694 struct drm_framebuffer *fb,
5695 struct drm_i915_gem_object *obj)
5696 {
5697 struct drm_i915_private *dev_priv = dev->dev_private;
5698 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5699 unsigned long offset;
5700 u32 flip_mask;
5701 int ret;
5702
5703 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
5704 if (ret)
5705 goto err;
5706
5707 /* Offset into the new buffer for cases of shared fbs between CRTCs */
5708 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
5709
5710 ret = BEGIN_LP_RING(6);
5711 if (ret)
5712 goto err_unpin;
5713
5714 if (intel_crtc->plane)
5715 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5716 else
5717 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5718 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5719 OUT_RING(MI_NOOP);
5720 OUT_RING(MI_DISPLAY_FLIP_I915 |
5721 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5722 OUT_RING(fb->pitches[0]);
5723 OUT_RING(obj->gtt_offset + offset);
5724 OUT_RING(MI_NOOP);
5725
5726 ADVANCE_LP_RING();
5727 return 0;
5728
5729 err_unpin:
5730 intel_unpin_fb_obj(obj);
5731 err:
5732 return ret;
5733 }
5734
5735 static int intel_gen4_queue_flip(struct drm_device *dev,
5736 struct drm_crtc *crtc,
5737 struct drm_framebuffer *fb,
5738 struct drm_i915_gem_object *obj)
5739 {
5740 struct drm_i915_private *dev_priv = dev->dev_private;
5741 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5742 uint32_t pf, pipesrc;
5743 int ret;
5744
5745 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
5746 if (ret)
5747 goto err;
5748
5749 ret = BEGIN_LP_RING(4);
5750 if (ret)
5751 goto err_unpin;
5752
5753 /* i965+ uses the linear or tiled offsets from the
5754 * Display Registers (which do not change across a page-flip)
5755 * so we need only reprogram the base address.
5756 */
5757 OUT_RING(MI_DISPLAY_FLIP |
5758 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5759 OUT_RING(fb->pitches[0]);
5760 OUT_RING(obj->gtt_offset | obj->tiling_mode);
5761
5762 /* XXX Enabling the panel-fitter across page-flip is so far
5763 * untested on non-native modes, so ignore it for now.
5764 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5765 */
5766 pf = 0;
5767 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
5768 OUT_RING(pf | pipesrc);
5769 ADVANCE_LP_RING();
5770 return 0;
5771
5772 err_unpin:
5773 intel_unpin_fb_obj(obj);
5774 err:
5775 return ret;
5776 }
5777
5778 static int intel_gen6_queue_flip(struct drm_device *dev,
5779 struct drm_crtc *crtc,
5780 struct drm_framebuffer *fb,
5781 struct drm_i915_gem_object *obj)
5782 {
5783 struct drm_i915_private *dev_priv = dev->dev_private;
5784 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5785 uint32_t pf, pipesrc;
5786 int ret;
5787
5788 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
5789 if (ret)
5790 goto err;
5791
5792 ret = BEGIN_LP_RING(4);
5793 if (ret)
5794 goto err_unpin;
5795
5796 OUT_RING(MI_DISPLAY_FLIP |
5797 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5798 OUT_RING(fb->pitches[0] | obj->tiling_mode);
5799 OUT_RING(obj->gtt_offset);
5800
5801 /* Contrary to the suggestions in the documentation,
5802 * "Enable Panel Fitter" does not seem to be required when page
5803 * flipping with a non-native mode, and worse causes a normal
5804 * modeset to fail.
5805 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
5806 */
5807 pf = 0;
5808 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
5809 OUT_RING(pf | pipesrc);
5810 ADVANCE_LP_RING();
5811 return 0;
5812
5813 err_unpin:
5814 intel_unpin_fb_obj(obj);
5815 err:
5816 return ret;
5817 }
5818
5819 /*
5820 * On gen7 we currently use the blit ring because (in early silicon at least)
5821 * the render ring doesn't give us interrpts for page flip completion, which
5822 * means clients will hang after the first flip is queued. Fortunately the
5823 * blit ring generates interrupts properly, so use it instead.
5824 */
5825 static int intel_gen7_queue_flip(struct drm_device *dev,
5826 struct drm_crtc *crtc,
5827 struct drm_framebuffer *fb,
5828 struct drm_i915_gem_object *obj)
5829 {
5830 struct drm_i915_private *dev_priv = dev->dev_private;
5831 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5832 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
5833 int ret;
5834
5835 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
5836 if (ret)
5837 goto err;
5838
5839 ret = intel_ring_begin(ring, 4);
5840 if (ret)
5841 goto err_unpin;
5842
5843 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
5844 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
5845 intel_ring_emit(ring, (obj->gtt_offset));
5846 intel_ring_emit(ring, (MI_NOOP));
5847 intel_ring_advance(ring);
5848 return 0;
5849
5850 err_unpin:
5851 intel_unpin_fb_obj(obj);
5852 err:
5853 return ret;
5854 }
5855
5856 static int intel_default_queue_flip(struct drm_device *dev,
5857 struct drm_crtc *crtc,
5858 struct drm_framebuffer *fb,
5859 struct drm_i915_gem_object *obj)
5860 {
5861 return -ENODEV;
5862 }
5863
5864 static int intel_crtc_page_flip(struct drm_crtc *crtc,
5865 struct drm_framebuffer *fb,
5866 struct drm_pending_vblank_event *event)
5867 {
5868 struct drm_device *dev = crtc->dev;
5869 struct drm_i915_private *dev_priv = dev->dev_private;
5870 struct intel_framebuffer *intel_fb;
5871 struct drm_i915_gem_object *obj;
5872 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5873 struct intel_unpin_work *work;
5874 unsigned long flags;
5875 int ret;
5876
5877 work = kzalloc(sizeof *work, GFP_KERNEL);
5878 if (work == NULL)
5879 return -ENOMEM;
5880
5881 work->event = event;
5882 work->dev = crtc->dev;
5883 intel_fb = to_intel_framebuffer(crtc->fb);
5884 work->old_fb_obj = intel_fb->obj;
5885 INIT_WORK(&work->work, intel_unpin_work_fn);
5886
5887 ret = drm_vblank_get(dev, intel_crtc->pipe);
5888 if (ret)
5889 goto free_work;
5890
5891 /* We borrow the event spin lock for protecting unpin_work */
5892 spin_lock_irqsave(&dev->event_lock, flags);
5893 if (intel_crtc->unpin_work) {
5894 spin_unlock_irqrestore(&dev->event_lock, flags);
5895 kfree(work);
5896 drm_vblank_put(dev, intel_crtc->pipe);
5897
5898 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5899 return -EBUSY;
5900 }
5901 intel_crtc->unpin_work = work;
5902 spin_unlock_irqrestore(&dev->event_lock, flags);
5903
5904 intel_fb = to_intel_framebuffer(fb);
5905 obj = intel_fb->obj;
5906
5907 mutex_lock(&dev->struct_mutex);
5908
5909 /* Reference the objects for the scheduled work. */
5910 drm_gem_object_reference(&work->old_fb_obj->base);
5911 drm_gem_object_reference(&obj->base);
5912
5913 crtc->fb = fb;
5914
5915 work->pending_flip_obj = obj;
5916
5917 work->enable_stall_check = true;
5918
5919 /* Block clients from rendering to the new back buffer until
5920 * the flip occurs and the object is no longer visible.
5921 */
5922 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
5923
5924 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
5925 if (ret)
5926 goto cleanup_pending;
5927
5928 intel_disable_fbc(dev);
5929 mutex_unlock(&dev->struct_mutex);
5930
5931 trace_i915_flip_request(intel_crtc->plane, obj);
5932
5933 return 0;
5934
5935 cleanup_pending:
5936 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
5937 drm_gem_object_unreference(&work->old_fb_obj->base);
5938 drm_gem_object_unreference(&obj->base);
5939 mutex_unlock(&dev->struct_mutex);
5940
5941 spin_lock_irqsave(&dev->event_lock, flags);
5942 intel_crtc->unpin_work = NULL;
5943 spin_unlock_irqrestore(&dev->event_lock, flags);
5944
5945 drm_vblank_put(dev, intel_crtc->pipe);
5946 free_work:
5947 kfree(work);
5948
5949 return ret;
5950 }
5951
5952 static void intel_sanitize_modesetting(struct drm_device *dev,
5953 int pipe, int plane)
5954 {
5955 struct drm_i915_private *dev_priv = dev->dev_private;
5956 u32 reg, val;
5957
5958 /* Clear any frame start delays used for debugging left by the BIOS */
5959 for_each_pipe(pipe) {
5960 reg = PIPECONF(pipe);
5961 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
5962 }
5963
5964 if (HAS_PCH_SPLIT(dev))
5965 return;
5966
5967 /* Who knows what state these registers were left in by the BIOS or
5968 * grub?
5969 *
5970 * If we leave the registers in a conflicting state (e.g. with the
5971 * display plane reading from the other pipe than the one we intend
5972 * to use) then when we attempt to teardown the active mode, we will
5973 * not disable the pipes and planes in the correct order -- leaving
5974 * a plane reading from a disabled pipe and possibly leading to
5975 * undefined behaviour.
5976 */
5977
5978 reg = DSPCNTR(plane);
5979 val = I915_READ(reg);
5980
5981 if ((val & DISPLAY_PLANE_ENABLE) == 0)
5982 return;
5983 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
5984 return;
5985
5986 /* This display plane is active and attached to the other CPU pipe. */
5987 pipe = !pipe;
5988
5989 /* Disable the plane and wait for it to stop reading from the pipe. */
5990 intel_disable_plane(dev_priv, plane, pipe);
5991 intel_disable_pipe(dev_priv, pipe);
5992 }
5993
5994 static void intel_crtc_reset(struct drm_crtc *crtc)
5995 {
5996 struct drm_device *dev = crtc->dev;
5997 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5998
5999 /* Reset flags back to the 'unknown' status so that they
6000 * will be correctly set on the initial modeset.
6001 */
6002 intel_crtc->dpms_mode = -1;
6003
6004 /* We need to fix up any BIOS configuration that conflicts with
6005 * our expectations.
6006 */
6007 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6008 }
6009
6010 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6011 .dpms = intel_crtc_dpms,
6012 .mode_fixup = intel_crtc_mode_fixup,
6013 .mode_set = intel_crtc_mode_set,
6014 .mode_set_base = intel_pipe_set_base,
6015 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6016 .load_lut = intel_crtc_load_lut,
6017 .disable = intel_crtc_disable,
6018 };
6019
6020 static const struct drm_crtc_funcs intel_crtc_funcs = {
6021 .reset = intel_crtc_reset,
6022 .cursor_set = intel_crtc_cursor_set,
6023 .cursor_move = intel_crtc_cursor_move,
6024 .gamma_set = intel_crtc_gamma_set,
6025 .set_config = drm_crtc_helper_set_config,
6026 .destroy = intel_crtc_destroy,
6027 .page_flip = intel_crtc_page_flip,
6028 };
6029
6030 static void intel_crtc_init(struct drm_device *dev, int pipe)
6031 {
6032 drm_i915_private_t *dev_priv = dev->dev_private;
6033 struct intel_crtc *intel_crtc;
6034 int i;
6035
6036 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6037 if (intel_crtc == NULL)
6038 return;
6039
6040 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6041
6042 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
6043 for (i = 0; i < 256; i++) {
6044 intel_crtc->lut_r[i] = i;
6045 intel_crtc->lut_g[i] = i;
6046 intel_crtc->lut_b[i] = i;
6047 }
6048
6049 /* Swap pipes & planes for FBC on pre-965 */
6050 intel_crtc->pipe = pipe;
6051 intel_crtc->plane = pipe;
6052 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
6053 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
6054 intel_crtc->plane = !pipe;
6055 }
6056
6057 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6058 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6059 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6060 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6061
6062 intel_crtc_reset(&intel_crtc->base);
6063 intel_crtc->active = true; /* force the pipe off on setup_init_config */
6064 intel_crtc->bpp = 24; /* default for pre-Ironlake */
6065
6066 if (HAS_PCH_SPLIT(dev)) {
6067 if (pipe == 2 && IS_IVYBRIDGE(dev))
6068 intel_crtc->no_pll = true;
6069 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6070 intel_helper_funcs.commit = ironlake_crtc_commit;
6071 } else {
6072 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6073 intel_helper_funcs.commit = i9xx_crtc_commit;
6074 }
6075
6076 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6077
6078 intel_crtc->busy = false;
6079
6080 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6081 (unsigned long)intel_crtc);
6082 }
6083
6084 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
6085 struct drm_file *file)
6086 {
6087 drm_i915_private_t *dev_priv = dev->dev_private;
6088 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
6089 struct drm_mode_object *drmmode_obj;
6090 struct intel_crtc *crtc;
6091
6092 if (!dev_priv) {
6093 DRM_ERROR("called with no initialization\n");
6094 return -EINVAL;
6095 }
6096
6097 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6098 DRM_MODE_OBJECT_CRTC);
6099
6100 if (!drmmode_obj) {
6101 DRM_ERROR("no such CRTC id\n");
6102 return -EINVAL;
6103 }
6104
6105 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6106 pipe_from_crtc_id->pipe = crtc->pipe;
6107
6108 return 0;
6109 }
6110
6111 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
6112 {
6113 struct intel_encoder *encoder;
6114 int index_mask = 0;
6115 int entry = 0;
6116
6117 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6118 if (type_mask & encoder->clone_mask)
6119 index_mask |= (1 << entry);
6120 entry++;
6121 }
6122
6123 return index_mask;
6124 }
6125
6126 static bool has_edp_a(struct drm_device *dev)
6127 {
6128 struct drm_i915_private *dev_priv = dev->dev_private;
6129
6130 if (!IS_MOBILE(dev))
6131 return false;
6132
6133 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6134 return false;
6135
6136 if (IS_GEN5(dev) &&
6137 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6138 return false;
6139
6140 return true;
6141 }
6142
6143 static void intel_setup_outputs(struct drm_device *dev)
6144 {
6145 struct drm_i915_private *dev_priv = dev->dev_private;
6146 struct intel_encoder *encoder;
6147 bool dpd_is_edp = false;
6148 bool has_lvds;
6149
6150 has_lvds = intel_lvds_init(dev);
6151 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6152 /* disable the panel fitter on everything but LVDS */
6153 I915_WRITE(PFIT_CONTROL, 0);
6154 }
6155
6156 if (HAS_PCH_SPLIT(dev)) {
6157 dpd_is_edp = intel_dpd_is_edp(dev);
6158
6159 if (has_edp_a(dev))
6160 intel_dp_init(dev, DP_A);
6161
6162 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6163 intel_dp_init(dev, PCH_DP_D);
6164 }
6165
6166 intel_crt_init(dev);
6167
6168 if (HAS_PCH_SPLIT(dev)) {
6169 int found;
6170
6171 if (I915_READ(HDMIB) & PORT_DETECTED) {
6172 /* PCH SDVOB multiplex with HDMIB */
6173 found = intel_sdvo_init(dev, PCH_SDVOB, true);
6174 if (!found)
6175 intel_hdmi_init(dev, HDMIB);
6176 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6177 intel_dp_init(dev, PCH_DP_B);
6178 }
6179
6180 if (I915_READ(HDMIC) & PORT_DETECTED)
6181 intel_hdmi_init(dev, HDMIC);
6182
6183 if (I915_READ(HDMID) & PORT_DETECTED)
6184 intel_hdmi_init(dev, HDMID);
6185
6186 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6187 intel_dp_init(dev, PCH_DP_C);
6188
6189 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6190 intel_dp_init(dev, PCH_DP_D);
6191
6192 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
6193 bool found = false;
6194
6195 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6196 DRM_DEBUG_KMS("probing SDVOB\n");
6197 found = intel_sdvo_init(dev, SDVOB, true);
6198 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6199 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
6200 intel_hdmi_init(dev, SDVOB);
6201 }
6202
6203 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6204 DRM_DEBUG_KMS("probing DP_B\n");
6205 intel_dp_init(dev, DP_B);
6206 }
6207 }
6208
6209 /* Before G4X SDVOC doesn't have its own detect register */
6210
6211 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6212 DRM_DEBUG_KMS("probing SDVOC\n");
6213 found = intel_sdvo_init(dev, SDVOC, false);
6214 }
6215
6216 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6217
6218 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6219 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
6220 intel_hdmi_init(dev, SDVOC);
6221 }
6222 if (SUPPORTS_INTEGRATED_DP(dev)) {
6223 DRM_DEBUG_KMS("probing DP_C\n");
6224 intel_dp_init(dev, DP_C);
6225 }
6226 }
6227
6228 if (SUPPORTS_INTEGRATED_DP(dev) &&
6229 (I915_READ(DP_D) & DP_DETECTED)) {
6230 DRM_DEBUG_KMS("probing DP_D\n");
6231 intel_dp_init(dev, DP_D);
6232 }
6233 } else if (IS_GEN2(dev))
6234 intel_dvo_init(dev);
6235
6236 if (SUPPORTS_TV(dev))
6237 intel_tv_init(dev);
6238
6239 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6240 encoder->base.possible_crtcs = encoder->crtc_mask;
6241 encoder->base.possible_clones =
6242 intel_encoder_clones(dev, encoder->clone_mask);
6243 }
6244
6245 /* disable all the possible outputs/crtcs before entering KMS mode */
6246 drm_helper_disable_unused_functions(dev);
6247
6248 if (HAS_PCH_SPLIT(dev))
6249 ironlake_init_pch_refclk(dev);
6250 }
6251
6252 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6253 {
6254 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6255
6256 drm_framebuffer_cleanup(fb);
6257 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
6258
6259 kfree(intel_fb);
6260 }
6261
6262 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
6263 struct drm_file *file,
6264 unsigned int *handle)
6265 {
6266 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6267 struct drm_i915_gem_object *obj = intel_fb->obj;
6268
6269 return drm_gem_handle_create(file, &obj->base, handle);
6270 }
6271
6272 static const struct drm_framebuffer_funcs intel_fb_funcs = {
6273 .destroy = intel_user_framebuffer_destroy,
6274 .create_handle = intel_user_framebuffer_create_handle,
6275 };
6276
6277 int intel_framebuffer_init(struct drm_device *dev,
6278 struct intel_framebuffer *intel_fb,
6279 struct drm_mode_fb_cmd2 *mode_cmd,
6280 struct drm_i915_gem_object *obj)
6281 {
6282 int ret;
6283
6284 if (obj->tiling_mode == I915_TILING_Y)
6285 return -EINVAL;
6286
6287 if (mode_cmd->pitches[0] & 63)
6288 return -EINVAL;
6289
6290 switch (mode_cmd->pixel_format) {
6291 case DRM_FORMAT_RGB332:
6292 case DRM_FORMAT_RGB565:
6293 case DRM_FORMAT_XRGB8888:
6294 case DRM_FORMAT_XBGR8888:
6295 case DRM_FORMAT_ARGB8888:
6296 case DRM_FORMAT_XRGB2101010:
6297 case DRM_FORMAT_ARGB2101010:
6298 /* RGB formats are common across chipsets */
6299 break;
6300 case DRM_FORMAT_YUYV:
6301 case DRM_FORMAT_UYVY:
6302 case DRM_FORMAT_YVYU:
6303 case DRM_FORMAT_VYUY:
6304 break;
6305 default:
6306 DRM_DEBUG_KMS("unsupported pixel format %u\n",
6307 mode_cmd->pixel_format);
6308 return -EINVAL;
6309 }
6310
6311 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6312 if (ret) {
6313 DRM_ERROR("framebuffer init failed %d\n", ret);
6314 return ret;
6315 }
6316
6317 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
6318 intel_fb->obj = obj;
6319 return 0;
6320 }
6321
6322 static struct drm_framebuffer *
6323 intel_user_framebuffer_create(struct drm_device *dev,
6324 struct drm_file *filp,
6325 struct drm_mode_fb_cmd2 *mode_cmd)
6326 {
6327 struct drm_i915_gem_object *obj;
6328
6329 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
6330 mode_cmd->handles[0]));
6331 if (&obj->base == NULL)
6332 return ERR_PTR(-ENOENT);
6333
6334 return intel_framebuffer_create(dev, mode_cmd, obj);
6335 }
6336
6337 static const struct drm_mode_config_funcs intel_mode_funcs = {
6338 .fb_create = intel_user_framebuffer_create,
6339 .output_poll_changed = intel_fb_output_poll_changed,
6340 };
6341
6342 /* Set up chip specific display functions */
6343 static void intel_init_display(struct drm_device *dev)
6344 {
6345 struct drm_i915_private *dev_priv = dev->dev_private;
6346
6347 /* We always want a DPMS function */
6348 if (HAS_PCH_SPLIT(dev)) {
6349 dev_priv->display.dpms = ironlake_crtc_dpms;
6350 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
6351 dev_priv->display.update_plane = ironlake_update_plane;
6352 } else {
6353 dev_priv->display.dpms = i9xx_crtc_dpms;
6354 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
6355 dev_priv->display.update_plane = i9xx_update_plane;
6356 }
6357
6358 /* Returns the core display clock speed */
6359 if (IS_VALLEYVIEW(dev))
6360 dev_priv->display.get_display_clock_speed =
6361 valleyview_get_display_clock_speed;
6362 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
6363 dev_priv->display.get_display_clock_speed =
6364 i945_get_display_clock_speed;
6365 else if (IS_I915G(dev))
6366 dev_priv->display.get_display_clock_speed =
6367 i915_get_display_clock_speed;
6368 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
6369 dev_priv->display.get_display_clock_speed =
6370 i9xx_misc_get_display_clock_speed;
6371 else if (IS_I915GM(dev))
6372 dev_priv->display.get_display_clock_speed =
6373 i915gm_get_display_clock_speed;
6374 else if (IS_I865G(dev))
6375 dev_priv->display.get_display_clock_speed =
6376 i865_get_display_clock_speed;
6377 else if (IS_I85X(dev))
6378 dev_priv->display.get_display_clock_speed =
6379 i855_get_display_clock_speed;
6380 else /* 852, 830 */
6381 dev_priv->display.get_display_clock_speed =
6382 i830_get_display_clock_speed;
6383
6384 if (HAS_PCH_SPLIT(dev)) {
6385 if (IS_GEN5(dev)) {
6386 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
6387 dev_priv->display.write_eld = ironlake_write_eld;
6388 } else if (IS_GEN6(dev)) {
6389 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
6390 dev_priv->display.write_eld = ironlake_write_eld;
6391 } else if (IS_IVYBRIDGE(dev)) {
6392 /* FIXME: detect B0+ stepping and use auto training */
6393 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
6394 dev_priv->display.write_eld = ironlake_write_eld;
6395 } else
6396 dev_priv->display.update_wm = NULL;
6397 } else if (IS_VALLEYVIEW(dev)) {
6398 dev_priv->display.force_wake_get = vlv_force_wake_get;
6399 dev_priv->display.force_wake_put = vlv_force_wake_put;
6400 } else if (IS_G4X(dev)) {
6401 dev_priv->display.write_eld = g4x_write_eld;
6402 }
6403
6404 /* Default just returns -ENODEV to indicate unsupported */
6405 dev_priv->display.queue_flip = intel_default_queue_flip;
6406
6407 switch (INTEL_INFO(dev)->gen) {
6408 case 2:
6409 dev_priv->display.queue_flip = intel_gen2_queue_flip;
6410 break;
6411
6412 case 3:
6413 dev_priv->display.queue_flip = intel_gen3_queue_flip;
6414 break;
6415
6416 case 4:
6417 case 5:
6418 dev_priv->display.queue_flip = intel_gen4_queue_flip;
6419 break;
6420
6421 case 6:
6422 dev_priv->display.queue_flip = intel_gen6_queue_flip;
6423 break;
6424 case 7:
6425 dev_priv->display.queue_flip = intel_gen7_queue_flip;
6426 break;
6427 }
6428 }
6429
6430 /*
6431 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
6432 * resume, or other times. This quirk makes sure that's the case for
6433 * affected systems.
6434 */
6435 static void quirk_pipea_force(struct drm_device *dev)
6436 {
6437 struct drm_i915_private *dev_priv = dev->dev_private;
6438
6439 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
6440 DRM_INFO("applying pipe a force quirk\n");
6441 }
6442
6443 /*
6444 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
6445 */
6446 static void quirk_ssc_force_disable(struct drm_device *dev)
6447 {
6448 struct drm_i915_private *dev_priv = dev->dev_private;
6449 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
6450 DRM_INFO("applying lvds SSC disable quirk\n");
6451 }
6452
6453 /*
6454 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
6455 * brightness value
6456 */
6457 static void quirk_invert_brightness(struct drm_device *dev)
6458 {
6459 struct drm_i915_private *dev_priv = dev->dev_private;
6460 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
6461 DRM_INFO("applying inverted panel brightness quirk\n");
6462 }
6463
6464 struct intel_quirk {
6465 int device;
6466 int subsystem_vendor;
6467 int subsystem_device;
6468 void (*hook)(struct drm_device *dev);
6469 };
6470
6471 static struct intel_quirk intel_quirks[] = {
6472 /* HP Mini needs pipe A force quirk (LP: #322104) */
6473 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
6474
6475 /* Thinkpad R31 needs pipe A force quirk */
6476 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
6477 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
6478 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
6479
6480 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
6481 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
6482 /* ThinkPad X40 needs pipe A force quirk */
6483
6484 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6485 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
6486
6487 /* 855 & before need to leave pipe A & dpll A up */
6488 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6489 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6490
6491 /* Lenovo U160 cannot use SSC on LVDS */
6492 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
6493
6494 /* Sony Vaio Y cannot use SSC on LVDS */
6495 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
6496
6497 /* Acer Aspire 5734Z must invert backlight brightness */
6498 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
6499 };
6500
6501 static void intel_init_quirks(struct drm_device *dev)
6502 {
6503 struct pci_dev *d = dev->pdev;
6504 int i;
6505
6506 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
6507 struct intel_quirk *q = &intel_quirks[i];
6508
6509 if (d->device == q->device &&
6510 (d->subsystem_vendor == q->subsystem_vendor ||
6511 q->subsystem_vendor == PCI_ANY_ID) &&
6512 (d->subsystem_device == q->subsystem_device ||
6513 q->subsystem_device == PCI_ANY_ID))
6514 q->hook(dev);
6515 }
6516 }
6517
6518 /* Disable the VGA plane that we never use */
6519 static void i915_disable_vga(struct drm_device *dev)
6520 {
6521 struct drm_i915_private *dev_priv = dev->dev_private;
6522 u8 sr1;
6523 u32 vga_reg;
6524
6525 if (HAS_PCH_SPLIT(dev))
6526 vga_reg = CPU_VGACNTRL;
6527 else
6528 vga_reg = VGACNTRL;
6529
6530 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6531 outb(SR01, VGA_SR_INDEX);
6532 sr1 = inb(VGA_SR_DATA);
6533 outb(sr1 | 1<<5, VGA_SR_DATA);
6534 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6535 udelay(300);
6536
6537 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6538 POSTING_READ(vga_reg);
6539 }
6540
6541 static void ivb_pch_pwm_override(struct drm_device *dev)
6542 {
6543 struct drm_i915_private *dev_priv = dev->dev_private;
6544
6545 /*
6546 * IVB has CPU eDP backlight regs too, set things up to let the
6547 * PCH regs control the backlight
6548 */
6549 I915_WRITE(BLC_PWM_CPU_CTL2, PWM_ENABLE);
6550 I915_WRITE(BLC_PWM_CPU_CTL, 0);
6551 I915_WRITE(BLC_PWM_PCH_CTL1, PWM_ENABLE | (1<<30));
6552 }
6553
6554 void intel_modeset_init_hw(struct drm_device *dev)
6555 {
6556 struct drm_i915_private *dev_priv = dev->dev_private;
6557
6558 intel_init_clock_gating(dev);
6559
6560 if (IS_IRONLAKE_M(dev)) {
6561 ironlake_enable_drps(dev);
6562 intel_init_emon(dev);
6563 }
6564
6565 if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
6566 gen6_enable_rps(dev_priv);
6567 gen6_update_ring_freq(dev_priv);
6568 }
6569
6570 if (IS_IVYBRIDGE(dev))
6571 ivb_pch_pwm_override(dev);
6572 }
6573
6574 void intel_modeset_init(struct drm_device *dev)
6575 {
6576 struct drm_i915_private *dev_priv = dev->dev_private;
6577 int i, ret;
6578
6579 drm_mode_config_init(dev);
6580
6581 dev->mode_config.min_width = 0;
6582 dev->mode_config.min_height = 0;
6583
6584 dev->mode_config.preferred_depth = 24;
6585 dev->mode_config.prefer_shadow = 1;
6586
6587 dev->mode_config.funcs = (void *)&intel_mode_funcs;
6588
6589 intel_init_quirks(dev);
6590
6591 intel_init_pm(dev);
6592
6593 intel_init_display(dev);
6594
6595 if (IS_GEN2(dev)) {
6596 dev->mode_config.max_width = 2048;
6597 dev->mode_config.max_height = 2048;
6598 } else if (IS_GEN3(dev)) {
6599 dev->mode_config.max_width = 4096;
6600 dev->mode_config.max_height = 4096;
6601 } else {
6602 dev->mode_config.max_width = 8192;
6603 dev->mode_config.max_height = 8192;
6604 }
6605 dev->mode_config.fb_base = dev->agp->base;
6606
6607 DRM_DEBUG_KMS("%d display pipe%s available.\n",
6608 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6609
6610 for (i = 0; i < dev_priv->num_pipe; i++) {
6611 intel_crtc_init(dev, i);
6612 ret = intel_plane_init(dev, i);
6613 if (ret)
6614 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
6615 }
6616
6617 /* Just disable it once at startup */
6618 i915_disable_vga(dev);
6619 intel_setup_outputs(dev);
6620
6621 intel_modeset_init_hw(dev);
6622
6623 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6624 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6625 (unsigned long)dev);
6626 }
6627
6628 void intel_modeset_gem_init(struct drm_device *dev)
6629 {
6630 if (IS_IRONLAKE_M(dev))
6631 ironlake_enable_rc6(dev);
6632
6633 intel_setup_overlay(dev);
6634 }
6635
6636 void intel_modeset_cleanup(struct drm_device *dev)
6637 {
6638 struct drm_i915_private *dev_priv = dev->dev_private;
6639 struct drm_crtc *crtc;
6640 struct intel_crtc *intel_crtc;
6641
6642 drm_kms_helper_poll_fini(dev);
6643 mutex_lock(&dev->struct_mutex);
6644
6645 intel_unregister_dsm_handler();
6646
6647
6648 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6649 /* Skip inactive CRTCs */
6650 if (!crtc->fb)
6651 continue;
6652
6653 intel_crtc = to_intel_crtc(crtc);
6654 intel_increase_pllclock(crtc);
6655 }
6656
6657 intel_disable_fbc(dev);
6658
6659 if (IS_IRONLAKE_M(dev))
6660 ironlake_disable_drps(dev);
6661 if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev))
6662 gen6_disable_rps(dev);
6663
6664 if (IS_IRONLAKE_M(dev))
6665 ironlake_disable_rc6(dev);
6666
6667 if (IS_VALLEYVIEW(dev))
6668 vlv_init_dpio(dev);
6669
6670 mutex_unlock(&dev->struct_mutex);
6671
6672 /* Disable the irq before mode object teardown, for the irq might
6673 * enqueue unpin/hotplug work. */
6674 drm_irq_uninstall(dev);
6675 cancel_work_sync(&dev_priv->hotplug_work);
6676 cancel_work_sync(&dev_priv->rps_work);
6677
6678 /* flush any delayed tasks or pending work */
6679 flush_scheduled_work();
6680
6681 /* Shut off idle work before the crtcs get freed. */
6682 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6683 intel_crtc = to_intel_crtc(crtc);
6684 del_timer_sync(&intel_crtc->idle_timer);
6685 }
6686 del_timer_sync(&dev_priv->idle_timer);
6687 cancel_work_sync(&dev_priv->idle_work);
6688
6689 drm_mode_config_cleanup(dev);
6690 }
6691
6692 /*
6693 * Return which encoder is currently attached for connector.
6694 */
6695 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
6696 {
6697 return &intel_attached_encoder(connector)->base;
6698 }
6699
6700 void intel_connector_attach_encoder(struct intel_connector *connector,
6701 struct intel_encoder *encoder)
6702 {
6703 connector->encoder = encoder;
6704 drm_mode_connector_attach_encoder(&connector->base,
6705 &encoder->base);
6706 }
6707
6708 /*
6709 * set vga decode state - true == enable VGA decode
6710 */
6711 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6712 {
6713 struct drm_i915_private *dev_priv = dev->dev_private;
6714 u16 gmch_ctrl;
6715
6716 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6717 if (state)
6718 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6719 else
6720 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6721 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6722 return 0;
6723 }
6724
6725 #ifdef CONFIG_DEBUG_FS
6726 #include <linux/seq_file.h>
6727
6728 struct intel_display_error_state {
6729 struct intel_cursor_error_state {
6730 u32 control;
6731 u32 position;
6732 u32 base;
6733 u32 size;
6734 } cursor[2];
6735
6736 struct intel_pipe_error_state {
6737 u32 conf;
6738 u32 source;
6739
6740 u32 htotal;
6741 u32 hblank;
6742 u32 hsync;
6743 u32 vtotal;
6744 u32 vblank;
6745 u32 vsync;
6746 } pipe[2];
6747
6748 struct intel_plane_error_state {
6749 u32 control;
6750 u32 stride;
6751 u32 size;
6752 u32 pos;
6753 u32 addr;
6754 u32 surface;
6755 u32 tile_offset;
6756 } plane[2];
6757 };
6758
6759 struct intel_display_error_state *
6760 intel_display_capture_error_state(struct drm_device *dev)
6761 {
6762 drm_i915_private_t *dev_priv = dev->dev_private;
6763 struct intel_display_error_state *error;
6764 int i;
6765
6766 error = kmalloc(sizeof(*error), GFP_ATOMIC);
6767 if (error == NULL)
6768 return NULL;
6769
6770 for (i = 0; i < 2; i++) {
6771 error->cursor[i].control = I915_READ(CURCNTR(i));
6772 error->cursor[i].position = I915_READ(CURPOS(i));
6773 error->cursor[i].base = I915_READ(CURBASE(i));
6774
6775 error->plane[i].control = I915_READ(DSPCNTR(i));
6776 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
6777 error->plane[i].size = I915_READ(DSPSIZE(i));
6778 error->plane[i].pos = I915_READ(DSPPOS(i));
6779 error->plane[i].addr = I915_READ(DSPADDR(i));
6780 if (INTEL_INFO(dev)->gen >= 4) {
6781 error->plane[i].surface = I915_READ(DSPSURF(i));
6782 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
6783 }
6784
6785 error->pipe[i].conf = I915_READ(PIPECONF(i));
6786 error->pipe[i].source = I915_READ(PIPESRC(i));
6787 error->pipe[i].htotal = I915_READ(HTOTAL(i));
6788 error->pipe[i].hblank = I915_READ(HBLANK(i));
6789 error->pipe[i].hsync = I915_READ(HSYNC(i));
6790 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
6791 error->pipe[i].vblank = I915_READ(VBLANK(i));
6792 error->pipe[i].vsync = I915_READ(VSYNC(i));
6793 }
6794
6795 return error;
6796 }
6797
6798 void
6799 intel_display_print_error_state(struct seq_file *m,
6800 struct drm_device *dev,
6801 struct intel_display_error_state *error)
6802 {
6803 int i;
6804
6805 for (i = 0; i < 2; i++) {
6806 seq_printf(m, "Pipe [%d]:\n", i);
6807 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
6808 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
6809 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
6810 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
6811 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
6812 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
6813 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
6814 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
6815
6816 seq_printf(m, "Plane [%d]:\n", i);
6817 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
6818 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
6819 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
6820 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
6821 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
6822 if (INTEL_INFO(dev)->gen >= 4) {
6823 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
6824 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
6825 }
6826
6827 seq_printf(m, "Cursor [%d]:\n", i);
6828 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
6829 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
6830 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
6831 }
6832 }
6833 #endif
Linux kernel - Deliverables
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