2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
);
45 static void intel_increase_pllclock(struct drm_crtc
*crtc
);
46 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
69 #define INTEL_P2_NUM 2
70 typedef struct intel_limit intel_limit_t
;
72 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
74 bool (* find_pll
)(const intel_limit_t
*, struct drm_crtc
*,
75 int, int, intel_clock_t
*, intel_clock_t
*);
79 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82 intel_pch_rawclk(struct drm_device
*dev
)
84 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
86 WARN_ON(!HAS_PCH_SPLIT(dev
));
88 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
92 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
93 int target
, int refclk
, intel_clock_t
*match_clock
,
94 intel_clock_t
*best_clock
);
96 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
97 int target
, int refclk
, intel_clock_t
*match_clock
,
98 intel_clock_t
*best_clock
);
101 intel_find_pll_g4x_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
102 int target
, int refclk
, intel_clock_t
*match_clock
,
103 intel_clock_t
*best_clock
);
105 intel_find_pll_ironlake_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
106 int target
, int refclk
, intel_clock_t
*match_clock
,
107 intel_clock_t
*best_clock
);
110 intel_vlv_find_best_pll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
111 int target
, int refclk
, intel_clock_t
*match_clock
,
112 intel_clock_t
*best_clock
);
114 static inline u32
/* units of 100MHz */
115 intel_fdi_link_freq(struct drm_device
*dev
)
118 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
119 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
124 static const intel_limit_t intel_limits_i8xx_dvo
= {
125 .dot
= { .min
= 25000, .max
= 350000 },
126 .vco
= { .min
= 930000, .max
= 1400000 },
127 .n
= { .min
= 3, .max
= 16 },
128 .m
= { .min
= 96, .max
= 140 },
129 .m1
= { .min
= 18, .max
= 26 },
130 .m2
= { .min
= 6, .max
= 16 },
131 .p
= { .min
= 4, .max
= 128 },
132 .p1
= { .min
= 2, .max
= 33 },
133 .p2
= { .dot_limit
= 165000,
134 .p2_slow
= 4, .p2_fast
= 2 },
135 .find_pll
= intel_find_best_PLL
,
138 static const intel_limit_t intel_limits_i8xx_lvds
= {
139 .dot
= { .min
= 25000, .max
= 350000 },
140 .vco
= { .min
= 930000, .max
= 1400000 },
141 .n
= { .min
= 3, .max
= 16 },
142 .m
= { .min
= 96, .max
= 140 },
143 .m1
= { .min
= 18, .max
= 26 },
144 .m2
= { .min
= 6, .max
= 16 },
145 .p
= { .min
= 4, .max
= 128 },
146 .p1
= { .min
= 1, .max
= 6 },
147 .p2
= { .dot_limit
= 165000,
148 .p2_slow
= 14, .p2_fast
= 7 },
149 .find_pll
= intel_find_best_PLL
,
152 static const intel_limit_t intel_limits_i9xx_sdvo
= {
153 .dot
= { .min
= 20000, .max
= 400000 },
154 .vco
= { .min
= 1400000, .max
= 2800000 },
155 .n
= { .min
= 1, .max
= 6 },
156 .m
= { .min
= 70, .max
= 120 },
157 .m1
= { .min
= 10, .max
= 22 },
158 .m2
= { .min
= 5, .max
= 9 },
159 .p
= { .min
= 5, .max
= 80 },
160 .p1
= { .min
= 1, .max
= 8 },
161 .p2
= { .dot_limit
= 200000,
162 .p2_slow
= 10, .p2_fast
= 5 },
163 .find_pll
= intel_find_best_PLL
,
166 static const intel_limit_t intel_limits_i9xx_lvds
= {
167 .dot
= { .min
= 20000, .max
= 400000 },
168 .vco
= { .min
= 1400000, .max
= 2800000 },
169 .n
= { .min
= 1, .max
= 6 },
170 .m
= { .min
= 70, .max
= 120 },
171 .m1
= { .min
= 10, .max
= 22 },
172 .m2
= { .min
= 5, .max
= 9 },
173 .p
= { .min
= 7, .max
= 98 },
174 .p1
= { .min
= 1, .max
= 8 },
175 .p2
= { .dot_limit
= 112000,
176 .p2_slow
= 14, .p2_fast
= 7 },
177 .find_pll
= intel_find_best_PLL
,
181 static const intel_limit_t intel_limits_g4x_sdvo
= {
182 .dot
= { .min
= 25000, .max
= 270000 },
183 .vco
= { .min
= 1750000, .max
= 3500000},
184 .n
= { .min
= 1, .max
= 4 },
185 .m
= { .min
= 104, .max
= 138 },
186 .m1
= { .min
= 17, .max
= 23 },
187 .m2
= { .min
= 5, .max
= 11 },
188 .p
= { .min
= 10, .max
= 30 },
189 .p1
= { .min
= 1, .max
= 3},
190 .p2
= { .dot_limit
= 270000,
194 .find_pll
= intel_g4x_find_best_PLL
,
197 static const intel_limit_t intel_limits_g4x_hdmi
= {
198 .dot
= { .min
= 22000, .max
= 400000 },
199 .vco
= { .min
= 1750000, .max
= 3500000},
200 .n
= { .min
= 1, .max
= 4 },
201 .m
= { .min
= 104, .max
= 138 },
202 .m1
= { .min
= 16, .max
= 23 },
203 .m2
= { .min
= 5, .max
= 11 },
204 .p
= { .min
= 5, .max
= 80 },
205 .p1
= { .min
= 1, .max
= 8},
206 .p2
= { .dot_limit
= 165000,
207 .p2_slow
= 10, .p2_fast
= 5 },
208 .find_pll
= intel_g4x_find_best_PLL
,
211 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
212 .dot
= { .min
= 20000, .max
= 115000 },
213 .vco
= { .min
= 1750000, .max
= 3500000 },
214 .n
= { .min
= 1, .max
= 3 },
215 .m
= { .min
= 104, .max
= 138 },
216 .m1
= { .min
= 17, .max
= 23 },
217 .m2
= { .min
= 5, .max
= 11 },
218 .p
= { .min
= 28, .max
= 112 },
219 .p1
= { .min
= 2, .max
= 8 },
220 .p2
= { .dot_limit
= 0,
221 .p2_slow
= 14, .p2_fast
= 14
223 .find_pll
= intel_g4x_find_best_PLL
,
226 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
227 .dot
= { .min
= 80000, .max
= 224000 },
228 .vco
= { .min
= 1750000, .max
= 3500000 },
229 .n
= { .min
= 1, .max
= 3 },
230 .m
= { .min
= 104, .max
= 138 },
231 .m1
= { .min
= 17, .max
= 23 },
232 .m2
= { .min
= 5, .max
= 11 },
233 .p
= { .min
= 14, .max
= 42 },
234 .p1
= { .min
= 2, .max
= 6 },
235 .p2
= { .dot_limit
= 0,
236 .p2_slow
= 7, .p2_fast
= 7
238 .find_pll
= intel_g4x_find_best_PLL
,
241 static const intel_limit_t intel_limits_g4x_display_port
= {
242 .dot
= { .min
= 161670, .max
= 227000 },
243 .vco
= { .min
= 1750000, .max
= 3500000},
244 .n
= { .min
= 1, .max
= 2 },
245 .m
= { .min
= 97, .max
= 108 },
246 .m1
= { .min
= 0x10, .max
= 0x12 },
247 .m2
= { .min
= 0x05, .max
= 0x06 },
248 .p
= { .min
= 10, .max
= 20 },
249 .p1
= { .min
= 1, .max
= 2},
250 .p2
= { .dot_limit
= 0,
251 .p2_slow
= 10, .p2_fast
= 10 },
252 .find_pll
= intel_find_pll_g4x_dp
,
255 static const intel_limit_t intel_limits_pineview_sdvo
= {
256 .dot
= { .min
= 20000, .max
= 400000},
257 .vco
= { .min
= 1700000, .max
= 3500000 },
258 /* Pineview's Ncounter is a ring counter */
259 .n
= { .min
= 3, .max
= 6 },
260 .m
= { .min
= 2, .max
= 256 },
261 /* Pineview only has one combined m divider, which we treat as m2. */
262 .m1
= { .min
= 0, .max
= 0 },
263 .m2
= { .min
= 0, .max
= 254 },
264 .p
= { .min
= 5, .max
= 80 },
265 .p1
= { .min
= 1, .max
= 8 },
266 .p2
= { .dot_limit
= 200000,
267 .p2_slow
= 10, .p2_fast
= 5 },
268 .find_pll
= intel_find_best_PLL
,
271 static const intel_limit_t intel_limits_pineview_lvds
= {
272 .dot
= { .min
= 20000, .max
= 400000 },
273 .vco
= { .min
= 1700000, .max
= 3500000 },
274 .n
= { .min
= 3, .max
= 6 },
275 .m
= { .min
= 2, .max
= 256 },
276 .m1
= { .min
= 0, .max
= 0 },
277 .m2
= { .min
= 0, .max
= 254 },
278 .p
= { .min
= 7, .max
= 112 },
279 .p1
= { .min
= 1, .max
= 8 },
280 .p2
= { .dot_limit
= 112000,
281 .p2_slow
= 14, .p2_fast
= 14 },
282 .find_pll
= intel_find_best_PLL
,
285 /* Ironlake / Sandybridge
287 * We calculate clock using (register_value + 2) for N/M1/M2, so here
288 * the range value for them is (actual_value - 2).
290 static const intel_limit_t intel_limits_ironlake_dac
= {
291 .dot
= { .min
= 25000, .max
= 350000 },
292 .vco
= { .min
= 1760000, .max
= 3510000 },
293 .n
= { .min
= 1, .max
= 5 },
294 .m
= { .min
= 79, .max
= 127 },
295 .m1
= { .min
= 12, .max
= 22 },
296 .m2
= { .min
= 5, .max
= 9 },
297 .p
= { .min
= 5, .max
= 80 },
298 .p1
= { .min
= 1, .max
= 8 },
299 .p2
= { .dot_limit
= 225000,
300 .p2_slow
= 10, .p2_fast
= 5 },
301 .find_pll
= intel_g4x_find_best_PLL
,
304 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
305 .dot
= { .min
= 25000, .max
= 350000 },
306 .vco
= { .min
= 1760000, .max
= 3510000 },
307 .n
= { .min
= 1, .max
= 3 },
308 .m
= { .min
= 79, .max
= 118 },
309 .m1
= { .min
= 12, .max
= 22 },
310 .m2
= { .min
= 5, .max
= 9 },
311 .p
= { .min
= 28, .max
= 112 },
312 .p1
= { .min
= 2, .max
= 8 },
313 .p2
= { .dot_limit
= 225000,
314 .p2_slow
= 14, .p2_fast
= 14 },
315 .find_pll
= intel_g4x_find_best_PLL
,
318 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
319 .dot
= { .min
= 25000, .max
= 350000 },
320 .vco
= { .min
= 1760000, .max
= 3510000 },
321 .n
= { .min
= 1, .max
= 3 },
322 .m
= { .min
= 79, .max
= 127 },
323 .m1
= { .min
= 12, .max
= 22 },
324 .m2
= { .min
= 5, .max
= 9 },
325 .p
= { .min
= 14, .max
= 56 },
326 .p1
= { .min
= 2, .max
= 8 },
327 .p2
= { .dot_limit
= 225000,
328 .p2_slow
= 7, .p2_fast
= 7 },
329 .find_pll
= intel_g4x_find_best_PLL
,
332 /* LVDS 100mhz refclk limits. */
333 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
334 .dot
= { .min
= 25000, .max
= 350000 },
335 .vco
= { .min
= 1760000, .max
= 3510000 },
336 .n
= { .min
= 1, .max
= 2 },
337 .m
= { .min
= 79, .max
= 126 },
338 .m1
= { .min
= 12, .max
= 22 },
339 .m2
= { .min
= 5, .max
= 9 },
340 .p
= { .min
= 28, .max
= 112 },
341 .p1
= { .min
= 2, .max
= 8 },
342 .p2
= { .dot_limit
= 225000,
343 .p2_slow
= 14, .p2_fast
= 14 },
344 .find_pll
= intel_g4x_find_best_PLL
,
347 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
348 .dot
= { .min
= 25000, .max
= 350000 },
349 .vco
= { .min
= 1760000, .max
= 3510000 },
350 .n
= { .min
= 1, .max
= 3 },
351 .m
= { .min
= 79, .max
= 126 },
352 .m1
= { .min
= 12, .max
= 22 },
353 .m2
= { .min
= 5, .max
= 9 },
354 .p
= { .min
= 14, .max
= 42 },
355 .p1
= { .min
= 2, .max
= 6 },
356 .p2
= { .dot_limit
= 225000,
357 .p2_slow
= 7, .p2_fast
= 7 },
358 .find_pll
= intel_g4x_find_best_PLL
,
361 static const intel_limit_t intel_limits_ironlake_display_port
= {
362 .dot
= { .min
= 25000, .max
= 350000 },
363 .vco
= { .min
= 1760000, .max
= 3510000},
364 .n
= { .min
= 1, .max
= 2 },
365 .m
= { .min
= 81, .max
= 90 },
366 .m1
= { .min
= 12, .max
= 22 },
367 .m2
= { .min
= 5, .max
= 9 },
368 .p
= { .min
= 10, .max
= 20 },
369 .p1
= { .min
= 1, .max
= 2},
370 .p2
= { .dot_limit
= 0,
371 .p2_slow
= 10, .p2_fast
= 10 },
372 .find_pll
= intel_find_pll_ironlake_dp
,
375 static const intel_limit_t intel_limits_vlv_dac
= {
376 .dot
= { .min
= 25000, .max
= 270000 },
377 .vco
= { .min
= 4000000, .max
= 6000000 },
378 .n
= { .min
= 1, .max
= 7 },
379 .m
= { .min
= 22, .max
= 450 }, /* guess */
380 .m1
= { .min
= 2, .max
= 3 },
381 .m2
= { .min
= 11, .max
= 156 },
382 .p
= { .min
= 10, .max
= 30 },
383 .p1
= { .min
= 2, .max
= 3 },
384 .p2
= { .dot_limit
= 270000,
385 .p2_slow
= 2, .p2_fast
= 20 },
386 .find_pll
= intel_vlv_find_best_pll
,
389 static const intel_limit_t intel_limits_vlv_hdmi
= {
390 .dot
= { .min
= 20000, .max
= 165000 },
391 .vco
= { .min
= 4000000, .max
= 5994000},
392 .n
= { .min
= 1, .max
= 7 },
393 .m
= { .min
= 60, .max
= 300 }, /* guess */
394 .m1
= { .min
= 2, .max
= 3 },
395 .m2
= { .min
= 11, .max
= 156 },
396 .p
= { .min
= 10, .max
= 30 },
397 .p1
= { .min
= 2, .max
= 3 },
398 .p2
= { .dot_limit
= 270000,
399 .p2_slow
= 2, .p2_fast
= 20 },
400 .find_pll
= intel_vlv_find_best_pll
,
403 static const intel_limit_t intel_limits_vlv_dp
= {
404 .dot
= { .min
= 25000, .max
= 270000 },
405 .vco
= { .min
= 4000000, .max
= 6000000 },
406 .n
= { .min
= 1, .max
= 7 },
407 .m
= { .min
= 22, .max
= 450 },
408 .m1
= { .min
= 2, .max
= 3 },
409 .m2
= { .min
= 11, .max
= 156 },
410 .p
= { .min
= 10, .max
= 30 },
411 .p1
= { .min
= 2, .max
= 3 },
412 .p2
= { .dot_limit
= 270000,
413 .p2_slow
= 2, .p2_fast
= 20 },
414 .find_pll
= intel_vlv_find_best_pll
,
417 u32
intel_dpio_read(struct drm_i915_private
*dev_priv
, int reg
)
419 WARN_ON(!mutex_is_locked(&dev_priv
->dpio_lock
));
421 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
422 DRM_ERROR("DPIO idle wait timed out\n");
426 I915_WRITE(DPIO_REG
, reg
);
427 I915_WRITE(DPIO_PKT
, DPIO_RID
| DPIO_OP_READ
| DPIO_PORTID
|
429 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
430 DRM_ERROR("DPIO read wait timed out\n");
434 return I915_READ(DPIO_DATA
);
437 static void intel_dpio_write(struct drm_i915_private
*dev_priv
, int reg
,
440 WARN_ON(!mutex_is_locked(&dev_priv
->dpio_lock
));
442 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
443 DRM_ERROR("DPIO idle wait timed out\n");
447 I915_WRITE(DPIO_DATA
, val
);
448 I915_WRITE(DPIO_REG
, reg
);
449 I915_WRITE(DPIO_PKT
, DPIO_RID
| DPIO_OP_WRITE
| DPIO_PORTID
|
451 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100))
452 DRM_ERROR("DPIO write wait timed out\n");
455 static void vlv_init_dpio(struct drm_device
*dev
)
457 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
459 /* Reset the DPIO config */
460 I915_WRITE(DPIO_CTL
, 0);
461 POSTING_READ(DPIO_CTL
);
462 I915_WRITE(DPIO_CTL
, 1);
463 POSTING_READ(DPIO_CTL
);
466 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
,
469 struct drm_device
*dev
= crtc
->dev
;
470 const intel_limit_t
*limit
;
472 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
473 if (intel_is_dual_link_lvds(dev
)) {
474 /* LVDS dual channel */
475 if (refclk
== 100000)
476 limit
= &intel_limits_ironlake_dual_lvds_100m
;
478 limit
= &intel_limits_ironlake_dual_lvds
;
480 if (refclk
== 100000)
481 limit
= &intel_limits_ironlake_single_lvds_100m
;
483 limit
= &intel_limits_ironlake_single_lvds
;
485 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
486 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))
487 limit
= &intel_limits_ironlake_display_port
;
489 limit
= &intel_limits_ironlake_dac
;
494 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
496 struct drm_device
*dev
= crtc
->dev
;
497 const intel_limit_t
*limit
;
499 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
500 if (intel_is_dual_link_lvds(dev
))
501 /* LVDS with dual channel */
502 limit
= &intel_limits_g4x_dual_channel_lvds
;
504 /* LVDS with dual channel */
505 limit
= &intel_limits_g4x_single_channel_lvds
;
506 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
507 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
508 limit
= &intel_limits_g4x_hdmi
;
509 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
510 limit
= &intel_limits_g4x_sdvo
;
511 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
512 limit
= &intel_limits_g4x_display_port
;
513 } else /* The option is for other outputs */
514 limit
= &intel_limits_i9xx_sdvo
;
519 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
, int refclk
)
521 struct drm_device
*dev
= crtc
->dev
;
522 const intel_limit_t
*limit
;
524 if (HAS_PCH_SPLIT(dev
))
525 limit
= intel_ironlake_limit(crtc
, refclk
);
526 else if (IS_G4X(dev
)) {
527 limit
= intel_g4x_limit(crtc
);
528 } else if (IS_PINEVIEW(dev
)) {
529 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
530 limit
= &intel_limits_pineview_lvds
;
532 limit
= &intel_limits_pineview_sdvo
;
533 } else if (IS_VALLEYVIEW(dev
)) {
534 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
))
535 limit
= &intel_limits_vlv_dac
;
536 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
537 limit
= &intel_limits_vlv_hdmi
;
539 limit
= &intel_limits_vlv_dp
;
540 } else if (!IS_GEN2(dev
)) {
541 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
542 limit
= &intel_limits_i9xx_lvds
;
544 limit
= &intel_limits_i9xx_sdvo
;
546 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
547 limit
= &intel_limits_i8xx_lvds
;
549 limit
= &intel_limits_i8xx_dvo
;
554 /* m1 is reserved as 0 in Pineview, n is a ring counter */
555 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
557 clock
->m
= clock
->m2
+ 2;
558 clock
->p
= clock
->p1
* clock
->p2
;
559 clock
->vco
= refclk
* clock
->m
/ clock
->n
;
560 clock
->dot
= clock
->vco
/ clock
->p
;
563 static void intel_clock(struct drm_device
*dev
, int refclk
, intel_clock_t
*clock
)
565 if (IS_PINEVIEW(dev
)) {
566 pineview_clock(refclk
, clock
);
569 clock
->m
= 5 * (clock
->m1
+ 2) + (clock
->m2
+ 2);
570 clock
->p
= clock
->p1
* clock
->p2
;
571 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
572 clock
->dot
= clock
->vco
/ clock
->p
;
576 * Returns whether any output on the specified pipe is of the specified type
578 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
580 struct drm_device
*dev
= crtc
->dev
;
581 struct intel_encoder
*encoder
;
583 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
584 if (encoder
->type
== type
)
590 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
592 * Returns whether the given set of divisors are valid for a given refclk with
593 * the given connectors.
596 static bool intel_PLL_is_valid(struct drm_device
*dev
,
597 const intel_limit_t
*limit
,
598 const intel_clock_t
*clock
)
600 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
601 INTELPllInvalid("p1 out of range\n");
602 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
603 INTELPllInvalid("p out of range\n");
604 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
605 INTELPllInvalid("m2 out of range\n");
606 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
607 INTELPllInvalid("m1 out of range\n");
608 if (clock
->m1
<= clock
->m2
&& !IS_PINEVIEW(dev
))
609 INTELPllInvalid("m1 <= m2\n");
610 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
611 INTELPllInvalid("m out of range\n");
612 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
613 INTELPllInvalid("n out of range\n");
614 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
615 INTELPllInvalid("vco out of range\n");
616 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
617 * connector, etc., rather than just a single range.
619 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
620 INTELPllInvalid("dot out of range\n");
626 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
627 int target
, int refclk
, intel_clock_t
*match_clock
,
628 intel_clock_t
*best_clock
)
631 struct drm_device
*dev
= crtc
->dev
;
635 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
637 * For LVDS just rely on its current settings for dual-channel.
638 * We haven't figured out how to reliably set up different
639 * single/dual channel state, if we even can.
641 if (intel_is_dual_link_lvds(dev
))
642 clock
.p2
= limit
->p2
.p2_fast
;
644 clock
.p2
= limit
->p2
.p2_slow
;
646 if (target
< limit
->p2
.dot_limit
)
647 clock
.p2
= limit
->p2
.p2_slow
;
649 clock
.p2
= limit
->p2
.p2_fast
;
652 memset(best_clock
, 0, sizeof(*best_clock
));
654 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
656 for (clock
.m2
= limit
->m2
.min
;
657 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
658 /* m1 is always 0 in Pineview */
659 if (clock
.m2
>= clock
.m1
&& !IS_PINEVIEW(dev
))
661 for (clock
.n
= limit
->n
.min
;
662 clock
.n
<= limit
->n
.max
; clock
.n
++) {
663 for (clock
.p1
= limit
->p1
.min
;
664 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
667 intel_clock(dev
, refclk
, &clock
);
668 if (!intel_PLL_is_valid(dev
, limit
,
672 clock
.p
!= match_clock
->p
)
675 this_err
= abs(clock
.dot
- target
);
676 if (this_err
< err
) {
685 return (err
!= target
);
689 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
690 int target
, int refclk
, intel_clock_t
*match_clock
,
691 intel_clock_t
*best_clock
)
693 struct drm_device
*dev
= crtc
->dev
;
697 /* approximately equals target * 0.00585 */
698 int err_most
= (target
>> 8) + (target
>> 9);
701 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
704 if (HAS_PCH_SPLIT(dev
))
708 if (intel_is_dual_link_lvds(dev
))
709 clock
.p2
= limit
->p2
.p2_fast
;
711 clock
.p2
= limit
->p2
.p2_slow
;
713 if (target
< limit
->p2
.dot_limit
)
714 clock
.p2
= limit
->p2
.p2_slow
;
716 clock
.p2
= limit
->p2
.p2_fast
;
719 memset(best_clock
, 0, sizeof(*best_clock
));
720 max_n
= limit
->n
.max
;
721 /* based on hardware requirement, prefer smaller n to precision */
722 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
723 /* based on hardware requirement, prefere larger m1,m2 */
724 for (clock
.m1
= limit
->m1
.max
;
725 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
726 for (clock
.m2
= limit
->m2
.max
;
727 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
728 for (clock
.p1
= limit
->p1
.max
;
729 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
732 intel_clock(dev
, refclk
, &clock
);
733 if (!intel_PLL_is_valid(dev
, limit
,
737 clock
.p
!= match_clock
->p
)
740 this_err
= abs(clock
.dot
- target
);
741 if (this_err
< err_most
) {
755 intel_find_pll_ironlake_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
756 int target
, int refclk
, intel_clock_t
*match_clock
,
757 intel_clock_t
*best_clock
)
759 struct drm_device
*dev
= crtc
->dev
;
762 if (target
< 200000) {
775 intel_clock(dev
, refclk
, &clock
);
776 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
780 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
782 intel_find_pll_g4x_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
783 int target
, int refclk
, intel_clock_t
*match_clock
,
784 intel_clock_t
*best_clock
)
787 if (target
< 200000) {
800 clock
.m
= 5 * (clock
.m1
+ 2) + (clock
.m2
+ 2);
801 clock
.p
= (clock
.p1
* clock
.p2
);
802 clock
.dot
= 96000 * clock
.m
/ (clock
.n
+ 2) / clock
.p
;
804 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
808 intel_vlv_find_best_pll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
809 int target
, int refclk
, intel_clock_t
*match_clock
,
810 intel_clock_t
*best_clock
)
812 u32 p1
, p2
, m1
, m2
, vco
, bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
814 u32 updrate
, minupdate
, fracbits
, p
;
815 unsigned long bestppm
, ppm
, absppm
;
819 dotclk
= target
* 1000;
822 fastclk
= dotclk
/ (2*100);
826 n
= p
= p1
= p2
= m
= m1
= m2
= vco
= bestn
= 0;
827 bestm1
= bestm2
= bestp1
= bestp2
= 0;
829 /* based on hardware requirement, prefer smaller n to precision */
830 for (n
= limit
->n
.min
; n
<= ((refclk
) / minupdate
); n
++) {
831 updrate
= refclk
/ n
;
832 for (p1
= limit
->p1
.max
; p1
> limit
->p1
.min
; p1
--) {
833 for (p2
= limit
->p2
.p2_fast
+1; p2
> 0; p2
--) {
837 /* based on hardware requirement, prefer bigger m1,m2 values */
838 for (m1
= limit
->m1
.min
; m1
<= limit
->m1
.max
; m1
++) {
839 m2
= (((2*(fastclk
* p
* n
/ m1
)) +
840 refclk
) / (2*refclk
));
843 if (vco
>= limit
->vco
.min
&& vco
< limit
->vco
.max
) {
844 ppm
= 1000000 * ((vco
/ p
) - fastclk
) / fastclk
;
845 absppm
= (ppm
> 0) ? ppm
: (-ppm
);
846 if (absppm
< 100 && ((p1
* p2
) > (bestp1
* bestp2
))) {
850 if (absppm
< bestppm
- 10) {
867 best_clock
->n
= bestn
;
868 best_clock
->m1
= bestm1
;
869 best_clock
->m2
= bestm2
;
870 best_clock
->p1
= bestp1
;
871 best_clock
->p2
= bestp2
;
876 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
879 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
880 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
882 return intel_crtc
->cpu_transcoder
;
885 static void ironlake_wait_for_vblank(struct drm_device
*dev
, int pipe
)
887 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
888 u32 frame
, frame_reg
= PIPEFRAME(pipe
);
890 frame
= I915_READ(frame_reg
);
892 if (wait_for(I915_READ_NOTRACE(frame_reg
) != frame
, 50))
893 DRM_DEBUG_KMS("vblank wait timed out\n");
897 * intel_wait_for_vblank - wait for vblank on a given pipe
899 * @pipe: pipe to wait for
901 * Wait for vblank to occur on a given pipe. Needed for various bits of
904 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
906 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
907 int pipestat_reg
= PIPESTAT(pipe
);
909 if (INTEL_INFO(dev
)->gen
>= 5) {
910 ironlake_wait_for_vblank(dev
, pipe
);
914 /* Clear existing vblank status. Note this will clear any other
915 * sticky status fields as well.
917 * This races with i915_driver_irq_handler() with the result
918 * that either function could miss a vblank event. Here it is not
919 * fatal, as we will either wait upon the next vblank interrupt or
920 * timeout. Generally speaking intel_wait_for_vblank() is only
921 * called during modeset at which time the GPU should be idle and
922 * should *not* be performing page flips and thus not waiting on
924 * Currently, the result of us stealing a vblank from the irq
925 * handler is that a single frame will be skipped during swapbuffers.
927 I915_WRITE(pipestat_reg
,
928 I915_READ(pipestat_reg
) | PIPE_VBLANK_INTERRUPT_STATUS
);
930 /* Wait for vblank interrupt bit to set */
931 if (wait_for(I915_READ(pipestat_reg
) &
932 PIPE_VBLANK_INTERRUPT_STATUS
,
934 DRM_DEBUG_KMS("vblank wait timed out\n");
938 * intel_wait_for_pipe_off - wait for pipe to turn off
940 * @pipe: pipe to wait for
942 * After disabling a pipe, we can't wait for vblank in the usual way,
943 * spinning on the vblank interrupt status bit, since we won't actually
944 * see an interrupt when the pipe is disabled.
947 * wait for the pipe register state bit to turn off
950 * wait for the display line value to settle (it usually
951 * ends up stopping at the start of the next frame).
954 void intel_wait_for_pipe_off(struct drm_device
*dev
, int pipe
)
956 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
957 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
960 if (INTEL_INFO(dev
)->gen
>= 4) {
961 int reg
= PIPECONF(cpu_transcoder
);
963 /* Wait for the Pipe State to go off */
964 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
966 WARN(1, "pipe_off wait timed out\n");
968 u32 last_line
, line_mask
;
969 int reg
= PIPEDSL(pipe
);
970 unsigned long timeout
= jiffies
+ msecs_to_jiffies(100);
973 line_mask
= DSL_LINEMASK_GEN2
;
975 line_mask
= DSL_LINEMASK_GEN3
;
977 /* Wait for the display line to settle */
979 last_line
= I915_READ(reg
) & line_mask
;
981 } while (((I915_READ(reg
) & line_mask
) != last_line
) &&
982 time_after(timeout
, jiffies
));
983 if (time_after(jiffies
, timeout
))
984 WARN(1, "pipe_off wait timed out\n");
989 * ibx_digital_port_connected - is the specified port connected?
990 * @dev_priv: i915 private structure
991 * @port: the port to test
993 * Returns true if @port is connected, false otherwise.
995 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
996 struct intel_digital_port
*port
)
1000 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1001 switch(port
->port
) {
1003 bit
= SDE_PORTB_HOTPLUG
;
1006 bit
= SDE_PORTC_HOTPLUG
;
1009 bit
= SDE_PORTD_HOTPLUG
;
1015 switch(port
->port
) {
1017 bit
= SDE_PORTB_HOTPLUG_CPT
;
1020 bit
= SDE_PORTC_HOTPLUG_CPT
;
1023 bit
= SDE_PORTD_HOTPLUG_CPT
;
1030 return I915_READ(SDEISR
) & bit
;
1033 static const char *state_string(bool enabled
)
1035 return enabled
? "on" : "off";
1038 /* Only for pre-ILK configs */
1039 static void assert_pll(struct drm_i915_private
*dev_priv
,
1040 enum pipe pipe
, bool state
)
1047 val
= I915_READ(reg
);
1048 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1049 WARN(cur_state
!= state
,
1050 "PLL state assertion failure (expected %s, current %s)\n",
1051 state_string(state
), state_string(cur_state
));
1053 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1054 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1057 static void assert_pch_pll(struct drm_i915_private
*dev_priv
,
1058 struct intel_pch_pll
*pll
,
1059 struct intel_crtc
*crtc
,
1065 if (HAS_PCH_LPT(dev_priv
->dev
)) {
1066 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1071 "asserting PCH PLL %s with no PLL\n", state_string(state
)))
1074 val
= I915_READ(pll
->pll_reg
);
1075 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1076 WARN(cur_state
!= state
,
1077 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1078 pll
->pll_reg
, state_string(state
), state_string(cur_state
), val
);
1080 /* Make sure the selected PLL is correctly attached to the transcoder */
1081 if (crtc
&& HAS_PCH_CPT(dev_priv
->dev
)) {
1084 pch_dpll
= I915_READ(PCH_DPLL_SEL
);
1085 cur_state
= pll
->pll_reg
== _PCH_DPLL_B
;
1086 if (!WARN(((pch_dpll
>> (4 * crtc
->pipe
)) & 1) != cur_state
,
1087 "PLL[%d] not attached to this transcoder %d: %08x\n",
1088 cur_state
, crtc
->pipe
, pch_dpll
)) {
1089 cur_state
= !!(val
>> (4*crtc
->pipe
+ 3));
1090 WARN(cur_state
!= state
,
1091 "PLL[%d] not %s on this transcoder %d: %08x\n",
1092 pll
->pll_reg
== _PCH_DPLL_B
,
1093 state_string(state
),
1099 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1100 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1102 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1103 enum pipe pipe
, bool state
)
1108 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1111 if (HAS_DDI(dev_priv
->dev
)) {
1112 /* DDI does not have a specific FDI_TX register */
1113 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1114 val
= I915_READ(reg
);
1115 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1117 reg
= FDI_TX_CTL(pipe
);
1118 val
= I915_READ(reg
);
1119 cur_state
= !!(val
& FDI_TX_ENABLE
);
1121 WARN(cur_state
!= state
,
1122 "FDI TX state assertion failure (expected %s, current %s)\n",
1123 state_string(state
), state_string(cur_state
));
1125 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1126 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1128 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1129 enum pipe pipe
, bool state
)
1135 reg
= FDI_RX_CTL(pipe
);
1136 val
= I915_READ(reg
);
1137 cur_state
= !!(val
& FDI_RX_ENABLE
);
1138 WARN(cur_state
!= state
,
1139 "FDI RX state assertion failure (expected %s, current %s)\n",
1140 state_string(state
), state_string(cur_state
));
1142 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1143 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1145 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1151 /* ILK FDI PLL is always enabled */
1152 if (dev_priv
->info
->gen
== 5)
1155 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1156 if (HAS_DDI(dev_priv
->dev
))
1159 reg
= FDI_TX_CTL(pipe
);
1160 val
= I915_READ(reg
);
1161 WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1164 static void assert_fdi_rx_pll_enabled(struct drm_i915_private
*dev_priv
,
1170 reg
= FDI_RX_CTL(pipe
);
1171 val
= I915_READ(reg
);
1172 WARN(!(val
& FDI_RX_PLL_ENABLE
), "FDI RX PLL assertion failure, should be active but is disabled\n");
1175 static void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1178 int pp_reg
, lvds_reg
;
1180 enum pipe panel_pipe
= PIPE_A
;
1183 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
1184 pp_reg
= PCH_PP_CONTROL
;
1185 lvds_reg
= PCH_LVDS
;
1187 pp_reg
= PP_CONTROL
;
1191 val
= I915_READ(pp_reg
);
1192 if (!(val
& PANEL_POWER_ON
) ||
1193 ((val
& PANEL_UNLOCK_REGS
) == PANEL_UNLOCK_REGS
))
1196 if (I915_READ(lvds_reg
) & LVDS_PIPEB_SELECT
)
1197 panel_pipe
= PIPE_B
;
1199 WARN(panel_pipe
== pipe
&& locked
,
1200 "panel assertion failure, pipe %c regs locked\n",
1204 void assert_pipe(struct drm_i915_private
*dev_priv
,
1205 enum pipe pipe
, bool state
)
1210 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1213 /* if we need the pipe A quirk it must be always on */
1214 if (pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
1217 reg
= PIPECONF(cpu_transcoder
);
1218 val
= I915_READ(reg
);
1219 cur_state
= !!(val
& PIPECONF_ENABLE
);
1220 WARN(cur_state
!= state
,
1221 "pipe %c assertion failure (expected %s, current %s)\n",
1222 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1225 static void assert_plane(struct drm_i915_private
*dev_priv
,
1226 enum plane plane
, bool state
)
1232 reg
= DSPCNTR(plane
);
1233 val
= I915_READ(reg
);
1234 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1235 WARN(cur_state
!= state
,
1236 "plane %c assertion failure (expected %s, current %s)\n",
1237 plane_name(plane
), state_string(state
), state_string(cur_state
));
1240 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1241 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1243 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1250 /* Planes are fixed to pipes on ILK+ */
1251 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
1252 reg
= DSPCNTR(pipe
);
1253 val
= I915_READ(reg
);
1254 WARN((val
& DISPLAY_PLANE_ENABLE
),
1255 "plane %c assertion failure, should be disabled but not\n",
1260 /* Need to check both planes against the pipe */
1261 for (i
= 0; i
< 2; i
++) {
1263 val
= I915_READ(reg
);
1264 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1265 DISPPLANE_SEL_PIPE_SHIFT
;
1266 WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1267 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1268 plane_name(i
), pipe_name(pipe
));
1272 static void assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1277 if (HAS_PCH_LPT(dev_priv
->dev
)) {
1278 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1282 val
= I915_READ(PCH_DREF_CONTROL
);
1283 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1284 DREF_SUPERSPREAD_SOURCE_MASK
));
1285 WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1288 static void assert_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1295 reg
= TRANSCONF(pipe
);
1296 val
= I915_READ(reg
);
1297 enabled
= !!(val
& TRANS_ENABLE
);
1299 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1303 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1304 enum pipe pipe
, u32 port_sel
, u32 val
)
1306 if ((val
& DP_PORT_EN
) == 0)
1309 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1310 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1311 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1312 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1315 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1321 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1322 enum pipe pipe
, u32 val
)
1324 if ((val
& PORT_ENABLE
) == 0)
1327 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1328 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1331 if ((val
& TRANSCODER_MASK
) != TRANSCODER(pipe
))
1337 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1338 enum pipe pipe
, u32 val
)
1340 if ((val
& LVDS_PORT_EN
) == 0)
1343 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1344 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1347 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1353 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1354 enum pipe pipe
, u32 val
)
1356 if ((val
& ADPA_DAC_ENABLE
) == 0)
1358 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1359 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1362 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1368 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1369 enum pipe pipe
, int reg
, u32 port_sel
)
1371 u32 val
= I915_READ(reg
);
1372 WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1373 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1374 reg
, pipe_name(pipe
));
1376 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1377 && (val
& DP_PIPEB_SELECT
),
1378 "IBX PCH dp port still using transcoder B\n");
1381 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1382 enum pipe pipe
, int reg
)
1384 u32 val
= I915_READ(reg
);
1385 WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1386 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1387 reg
, pipe_name(pipe
));
1389 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& PORT_ENABLE
) == 0
1390 && (val
& SDVO_PIPE_B_SELECT
),
1391 "IBX PCH hdmi port still using transcoder B\n");
1394 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1400 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1401 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1402 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1405 val
= I915_READ(reg
);
1406 WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1407 "PCH VGA enabled on transcoder %c, should be disabled\n",
1411 val
= I915_READ(reg
);
1412 WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1413 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1416 assert_pch_hdmi_disabled(dev_priv
, pipe
, HDMIB
);
1417 assert_pch_hdmi_disabled(dev_priv
, pipe
, HDMIC
);
1418 assert_pch_hdmi_disabled(dev_priv
, pipe
, HDMID
);
1422 * intel_enable_pll - enable a PLL
1423 * @dev_priv: i915 private structure
1424 * @pipe: pipe PLL to enable
1426 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1427 * make sure the PLL reg is writable first though, since the panel write
1428 * protect mechanism may be enabled.
1430 * Note! This is for pre-ILK only.
1432 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1434 static void intel_enable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1439 /* No really, not for ILK+ */
1440 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
) && dev_priv
->info
->gen
>= 5);
1442 /* PLL is protected by panel, make sure we can write it */
1443 if (IS_MOBILE(dev_priv
->dev
) && !IS_I830(dev_priv
->dev
))
1444 assert_panel_unlocked(dev_priv
, pipe
);
1447 val
= I915_READ(reg
);
1448 val
|= DPLL_VCO_ENABLE
;
1450 /* We do this three times for luck */
1451 I915_WRITE(reg
, val
);
1453 udelay(150); /* wait for warmup */
1454 I915_WRITE(reg
, val
);
1456 udelay(150); /* wait for warmup */
1457 I915_WRITE(reg
, val
);
1459 udelay(150); /* wait for warmup */
1463 * intel_disable_pll - disable a PLL
1464 * @dev_priv: i915 private structure
1465 * @pipe: pipe PLL to disable
1467 * Disable the PLL for @pipe, making sure the pipe is off first.
1469 * Note! This is for pre-ILK only.
1471 static void intel_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1476 /* Don't disable pipe A or pipe A PLLs if needed */
1477 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1480 /* Make sure the pipe isn't still relying on us */
1481 assert_pipe_disabled(dev_priv
, pipe
);
1484 val
= I915_READ(reg
);
1485 val
&= ~DPLL_VCO_ENABLE
;
1486 I915_WRITE(reg
, val
);
1492 intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
1493 enum intel_sbi_destination destination
)
1497 WARN_ON(!mutex_is_locked(&dev_priv
->dpio_lock
));
1499 if (wait_for((I915_READ(SBI_CTL_STAT
) & SBI_BUSY
) == 0,
1501 DRM_ERROR("timeout waiting for SBI to become ready\n");
1505 I915_WRITE(SBI_ADDR
, (reg
<< 16));
1506 I915_WRITE(SBI_DATA
, value
);
1508 if (destination
== SBI_ICLK
)
1509 tmp
= SBI_CTL_DEST_ICLK
| SBI_CTL_OP_CRWR
;
1511 tmp
= SBI_CTL_DEST_MPHY
| SBI_CTL_OP_IOWR
;
1512 I915_WRITE(SBI_CTL_STAT
, SBI_BUSY
| tmp
);
1514 if (wait_for((I915_READ(SBI_CTL_STAT
) & (SBI_BUSY
| SBI_RESPONSE_FAIL
)) == 0,
1516 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1522 intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
1523 enum intel_sbi_destination destination
)
1526 WARN_ON(!mutex_is_locked(&dev_priv
->dpio_lock
));
1528 if (wait_for((I915_READ(SBI_CTL_STAT
) & SBI_BUSY
) == 0,
1530 DRM_ERROR("timeout waiting for SBI to become ready\n");
1534 I915_WRITE(SBI_ADDR
, (reg
<< 16));
1536 if (destination
== SBI_ICLK
)
1537 value
= SBI_CTL_DEST_ICLK
| SBI_CTL_OP_CRRD
;
1539 value
= SBI_CTL_DEST_MPHY
| SBI_CTL_OP_IORD
;
1540 I915_WRITE(SBI_CTL_STAT
, value
| SBI_BUSY
);
1542 if (wait_for((I915_READ(SBI_CTL_STAT
) & (SBI_BUSY
| SBI_RESPONSE_FAIL
)) == 0,
1544 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1548 return I915_READ(SBI_DATA
);
1552 * ironlake_enable_pch_pll - enable PCH PLL
1553 * @dev_priv: i915 private structure
1554 * @pipe: pipe PLL to enable
1556 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1557 * drives the transcoder clock.
1559 static void ironlake_enable_pch_pll(struct intel_crtc
*intel_crtc
)
1561 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
1562 struct intel_pch_pll
*pll
;
1566 /* PCH PLLs only available on ILK, SNB and IVB */
1567 BUG_ON(dev_priv
->info
->gen
< 5);
1568 pll
= intel_crtc
->pch_pll
;
1572 if (WARN_ON(pll
->refcount
== 0))
1575 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1576 pll
->pll_reg
, pll
->active
, pll
->on
,
1577 intel_crtc
->base
.base
.id
);
1579 /* PCH refclock must be enabled first */
1580 assert_pch_refclk_enabled(dev_priv
);
1582 if (pll
->active
++ && pll
->on
) {
1583 assert_pch_pll_enabled(dev_priv
, pll
, NULL
);
1587 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll
->pll_reg
);
1590 val
= I915_READ(reg
);
1591 val
|= DPLL_VCO_ENABLE
;
1592 I915_WRITE(reg
, val
);
1599 static void intel_disable_pch_pll(struct intel_crtc
*intel_crtc
)
1601 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
1602 struct intel_pch_pll
*pll
= intel_crtc
->pch_pll
;
1606 /* PCH only available on ILK+ */
1607 BUG_ON(dev_priv
->info
->gen
< 5);
1611 if (WARN_ON(pll
->refcount
== 0))
1614 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1615 pll
->pll_reg
, pll
->active
, pll
->on
,
1616 intel_crtc
->base
.base
.id
);
1618 if (WARN_ON(pll
->active
== 0)) {
1619 assert_pch_pll_disabled(dev_priv
, pll
, NULL
);
1623 if (--pll
->active
) {
1624 assert_pch_pll_enabled(dev_priv
, pll
, NULL
);
1628 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll
->pll_reg
);
1630 /* Make sure transcoder isn't still depending on us */
1631 assert_transcoder_disabled(dev_priv
, intel_crtc
->pipe
);
1634 val
= I915_READ(reg
);
1635 val
&= ~DPLL_VCO_ENABLE
;
1636 I915_WRITE(reg
, val
);
1643 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1646 struct drm_device
*dev
= dev_priv
->dev
;
1647 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1648 uint32_t reg
, val
, pipeconf_val
;
1650 /* PCH only available on ILK+ */
1651 BUG_ON(dev_priv
->info
->gen
< 5);
1653 /* Make sure PCH DPLL is enabled */
1654 assert_pch_pll_enabled(dev_priv
,
1655 to_intel_crtc(crtc
)->pch_pll
,
1656 to_intel_crtc(crtc
));
1658 /* FDI must be feeding us bits for PCH ports */
1659 assert_fdi_tx_enabled(dev_priv
, pipe
);
1660 assert_fdi_rx_enabled(dev_priv
, pipe
);
1662 if (HAS_PCH_CPT(dev
)) {
1663 /* Workaround: Set the timing override bit before enabling the
1664 * pch transcoder. */
1665 reg
= TRANS_CHICKEN2(pipe
);
1666 val
= I915_READ(reg
);
1667 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1668 I915_WRITE(reg
, val
);
1671 reg
= TRANSCONF(pipe
);
1672 val
= I915_READ(reg
);
1673 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1675 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1677 * make the BPC in transcoder be consistent with
1678 * that in pipeconf reg.
1680 val
&= ~PIPECONF_BPC_MASK
;
1681 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1684 val
&= ~TRANS_INTERLACE_MASK
;
1685 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1686 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1687 intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
))
1688 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1690 val
|= TRANS_INTERLACED
;
1692 val
|= TRANS_PROGRESSIVE
;
1694 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1695 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1696 DRM_ERROR("failed to enable transcoder %d\n", pipe
);
1699 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1700 enum transcoder cpu_transcoder
)
1702 u32 val
, pipeconf_val
;
1704 /* PCH only available on ILK+ */
1705 BUG_ON(dev_priv
->info
->gen
< 5);
1707 /* FDI must be feeding us bits for PCH ports */
1708 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1709 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
1711 /* Workaround: set timing override bit. */
1712 val
= I915_READ(_TRANSA_CHICKEN2
);
1713 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1714 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1717 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1719 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1720 PIPECONF_INTERLACED_ILK
)
1721 val
|= TRANS_INTERLACED
;
1723 val
|= TRANS_PROGRESSIVE
;
1725 I915_WRITE(TRANSCONF(TRANSCODER_A
), val
);
1726 if (wait_for(I915_READ(_TRANSACONF
) & TRANS_STATE_ENABLE
, 100))
1727 DRM_ERROR("Failed to enable PCH transcoder\n");
1730 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1733 struct drm_device
*dev
= dev_priv
->dev
;
1736 /* FDI relies on the transcoder */
1737 assert_fdi_tx_disabled(dev_priv
, pipe
);
1738 assert_fdi_rx_disabled(dev_priv
, pipe
);
1740 /* Ports must be off as well */
1741 assert_pch_ports_disabled(dev_priv
, pipe
);
1743 reg
= TRANSCONF(pipe
);
1744 val
= I915_READ(reg
);
1745 val
&= ~TRANS_ENABLE
;
1746 I915_WRITE(reg
, val
);
1747 /* wait for PCH transcoder off, transcoder state */
1748 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1749 DRM_ERROR("failed to disable transcoder %d\n", pipe
);
1751 if (!HAS_PCH_IBX(dev
)) {
1752 /* Workaround: Clear the timing override chicken bit again. */
1753 reg
= TRANS_CHICKEN2(pipe
);
1754 val
= I915_READ(reg
);
1755 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1756 I915_WRITE(reg
, val
);
1760 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1764 val
= I915_READ(_TRANSACONF
);
1765 val
&= ~TRANS_ENABLE
;
1766 I915_WRITE(_TRANSACONF
, val
);
1767 /* wait for PCH transcoder off, transcoder state */
1768 if (wait_for((I915_READ(_TRANSACONF
) & TRANS_STATE_ENABLE
) == 0, 50))
1769 DRM_ERROR("Failed to disable PCH transcoder\n");
1771 /* Workaround: clear timing override bit. */
1772 val
= I915_READ(_TRANSA_CHICKEN2
);
1773 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1774 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1778 * intel_enable_pipe - enable a pipe, asserting requirements
1779 * @dev_priv: i915 private structure
1780 * @pipe: pipe to enable
1781 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1783 * Enable @pipe, making sure that various hardware specific requirements
1784 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1786 * @pipe should be %PIPE_A or %PIPE_B.
1788 * Will wait until the pipe is actually running (i.e. first vblank) before
1791 static void intel_enable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
1794 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1796 enum pipe pch_transcoder
;
1800 if (HAS_PCH_LPT(dev_priv
->dev
))
1801 pch_transcoder
= TRANSCODER_A
;
1803 pch_transcoder
= pipe
;
1806 * A pipe without a PLL won't actually be able to drive bits from
1807 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1810 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
1811 assert_pll_enabled(dev_priv
, pipe
);
1814 /* if driving the PCH, we need FDI enabled */
1815 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
1816 assert_fdi_tx_pll_enabled(dev_priv
,
1817 (enum pipe
) cpu_transcoder
);
1819 /* FIXME: assert CPU port conditions for SNB+ */
1822 reg
= PIPECONF(cpu_transcoder
);
1823 val
= I915_READ(reg
);
1824 if (val
& PIPECONF_ENABLE
)
1827 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
1828 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1832 * intel_disable_pipe - disable a pipe, asserting requirements
1833 * @dev_priv: i915 private structure
1834 * @pipe: pipe to disable
1836 * Disable @pipe, making sure that various hardware specific requirements
1837 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1839 * @pipe should be %PIPE_A or %PIPE_B.
1841 * Will wait until the pipe has shut down before returning.
1843 static void intel_disable_pipe(struct drm_i915_private
*dev_priv
,
1846 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1852 * Make sure planes won't keep trying to pump pixels to us,
1853 * or we might hang the display.
1855 assert_planes_disabled(dev_priv
, pipe
);
1857 /* Don't disable pipe A or pipe A PLLs if needed */
1858 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1861 reg
= PIPECONF(cpu_transcoder
);
1862 val
= I915_READ(reg
);
1863 if ((val
& PIPECONF_ENABLE
) == 0)
1866 I915_WRITE(reg
, val
& ~PIPECONF_ENABLE
);
1867 intel_wait_for_pipe_off(dev_priv
->dev
, pipe
);
1871 * Plane regs are double buffered, going from enabled->disabled needs a
1872 * trigger in order to latch. The display address reg provides this.
1874 void intel_flush_display_plane(struct drm_i915_private
*dev_priv
,
1877 if (dev_priv
->info
->gen
>= 4)
1878 I915_WRITE(DSPSURF(plane
), I915_READ(DSPSURF(plane
)));
1880 I915_WRITE(DSPADDR(plane
), I915_READ(DSPADDR(plane
)));
1884 * intel_enable_plane - enable a display plane on a given pipe
1885 * @dev_priv: i915 private structure
1886 * @plane: plane to enable
1887 * @pipe: pipe being fed
1889 * Enable @plane on @pipe, making sure that @pipe is running first.
1891 static void intel_enable_plane(struct drm_i915_private
*dev_priv
,
1892 enum plane plane
, enum pipe pipe
)
1897 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1898 assert_pipe_enabled(dev_priv
, pipe
);
1900 reg
= DSPCNTR(plane
);
1901 val
= I915_READ(reg
);
1902 if (val
& DISPLAY_PLANE_ENABLE
)
1905 I915_WRITE(reg
, val
| DISPLAY_PLANE_ENABLE
);
1906 intel_flush_display_plane(dev_priv
, plane
);
1907 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1911 * intel_disable_plane - disable a display plane
1912 * @dev_priv: i915 private structure
1913 * @plane: plane to disable
1914 * @pipe: pipe consuming the data
1916 * Disable @plane; should be an independent operation.
1918 static void intel_disable_plane(struct drm_i915_private
*dev_priv
,
1919 enum plane plane
, enum pipe pipe
)
1924 reg
= DSPCNTR(plane
);
1925 val
= I915_READ(reg
);
1926 if ((val
& DISPLAY_PLANE_ENABLE
) == 0)
1929 I915_WRITE(reg
, val
& ~DISPLAY_PLANE_ENABLE
);
1930 intel_flush_display_plane(dev_priv
, plane
);
1931 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1935 intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
1936 struct drm_i915_gem_object
*obj
,
1937 struct intel_ring_buffer
*pipelined
)
1939 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1943 switch (obj
->tiling_mode
) {
1944 case I915_TILING_NONE
:
1945 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
1946 alignment
= 128 * 1024;
1947 else if (INTEL_INFO(dev
)->gen
>= 4)
1948 alignment
= 4 * 1024;
1950 alignment
= 64 * 1024;
1953 /* pin() will align the object as required by fence */
1957 /* FIXME: Is this true? */
1958 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1964 dev_priv
->mm
.interruptible
= false;
1965 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
);
1967 goto err_interruptible
;
1969 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1970 * fence, whereas 965+ only requires a fence if using
1971 * framebuffer compression. For simplicity, we always install
1972 * a fence as the cost is not that onerous.
1974 ret
= i915_gem_object_get_fence(obj
);
1978 i915_gem_object_pin_fence(obj
);
1980 dev_priv
->mm
.interruptible
= true;
1984 i915_gem_object_unpin(obj
);
1986 dev_priv
->mm
.interruptible
= true;
1990 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
)
1992 i915_gem_object_unpin_fence(obj
);
1993 i915_gem_object_unpin(obj
);
1996 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1997 * is assumed to be a power-of-two. */
1998 unsigned long intel_gen4_compute_offset_xtiled(int *x
, int *y
,
2002 int tile_rows
, tiles
;
2006 tiles
= *x
/ (512/bpp
);
2009 return tile_rows
* pitch
* 8 + tiles
* 4096;
2012 static int i9xx_update_plane(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2015 struct drm_device
*dev
= crtc
->dev
;
2016 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2017 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2018 struct intel_framebuffer
*intel_fb
;
2019 struct drm_i915_gem_object
*obj
;
2020 int plane
= intel_crtc
->plane
;
2021 unsigned long linear_offset
;
2030 DRM_ERROR("Can't update plane %d in SAREA\n", plane
);
2034 intel_fb
= to_intel_framebuffer(fb
);
2035 obj
= intel_fb
->obj
;
2037 reg
= DSPCNTR(plane
);
2038 dspcntr
= I915_READ(reg
);
2039 /* Mask out pixel format bits in case we change it */
2040 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2041 switch (fb
->pixel_format
) {
2043 dspcntr
|= DISPPLANE_8BPP
;
2045 case DRM_FORMAT_XRGB1555
:
2046 case DRM_FORMAT_ARGB1555
:
2047 dspcntr
|= DISPPLANE_BGRX555
;
2049 case DRM_FORMAT_RGB565
:
2050 dspcntr
|= DISPPLANE_BGRX565
;
2052 case DRM_FORMAT_XRGB8888
:
2053 case DRM_FORMAT_ARGB8888
:
2054 dspcntr
|= DISPPLANE_BGRX888
;
2056 case DRM_FORMAT_XBGR8888
:
2057 case DRM_FORMAT_ABGR8888
:
2058 dspcntr
|= DISPPLANE_RGBX888
;
2060 case DRM_FORMAT_XRGB2101010
:
2061 case DRM_FORMAT_ARGB2101010
:
2062 dspcntr
|= DISPPLANE_BGRX101010
;
2064 case DRM_FORMAT_XBGR2101010
:
2065 case DRM_FORMAT_ABGR2101010
:
2066 dspcntr
|= DISPPLANE_RGBX101010
;
2069 DRM_ERROR("Unknown pixel format 0x%08x\n", fb
->pixel_format
);
2073 if (INTEL_INFO(dev
)->gen
>= 4) {
2074 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2075 dspcntr
|= DISPPLANE_TILED
;
2077 dspcntr
&= ~DISPPLANE_TILED
;
2080 I915_WRITE(reg
, dspcntr
);
2082 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2084 if (INTEL_INFO(dev
)->gen
>= 4) {
2085 intel_crtc
->dspaddr_offset
=
2086 intel_gen4_compute_offset_xtiled(&x
, &y
,
2087 fb
->bits_per_pixel
/ 8,
2089 linear_offset
-= intel_crtc
->dspaddr_offset
;
2091 intel_crtc
->dspaddr_offset
= linear_offset
;
2094 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2095 obj
->gtt_offset
, linear_offset
, x
, y
, fb
->pitches
[0]);
2096 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2097 if (INTEL_INFO(dev
)->gen
>= 4) {
2098 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2099 obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
2100 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2101 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2103 I915_WRITE(DSPADDR(plane
), obj
->gtt_offset
+ linear_offset
);
2109 static int ironlake_update_plane(struct drm_crtc
*crtc
,
2110 struct drm_framebuffer
*fb
, int x
, int y
)
2112 struct drm_device
*dev
= crtc
->dev
;
2113 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2114 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2115 struct intel_framebuffer
*intel_fb
;
2116 struct drm_i915_gem_object
*obj
;
2117 int plane
= intel_crtc
->plane
;
2118 unsigned long linear_offset
;
2128 DRM_ERROR("Can't update plane %d in SAREA\n", plane
);
2132 intel_fb
= to_intel_framebuffer(fb
);
2133 obj
= intel_fb
->obj
;
2135 reg
= DSPCNTR(plane
);
2136 dspcntr
= I915_READ(reg
);
2137 /* Mask out pixel format bits in case we change it */
2138 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2139 switch (fb
->pixel_format
) {
2141 dspcntr
|= DISPPLANE_8BPP
;
2143 case DRM_FORMAT_RGB565
:
2144 dspcntr
|= DISPPLANE_BGRX565
;
2146 case DRM_FORMAT_XRGB8888
:
2147 case DRM_FORMAT_ARGB8888
:
2148 dspcntr
|= DISPPLANE_BGRX888
;
2150 case DRM_FORMAT_XBGR8888
:
2151 case DRM_FORMAT_ABGR8888
:
2152 dspcntr
|= DISPPLANE_RGBX888
;
2154 case DRM_FORMAT_XRGB2101010
:
2155 case DRM_FORMAT_ARGB2101010
:
2156 dspcntr
|= DISPPLANE_BGRX101010
;
2158 case DRM_FORMAT_XBGR2101010
:
2159 case DRM_FORMAT_ABGR2101010
:
2160 dspcntr
|= DISPPLANE_RGBX101010
;
2163 DRM_ERROR("Unknown pixel format 0x%08x\n", fb
->pixel_format
);
2167 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2168 dspcntr
|= DISPPLANE_TILED
;
2170 dspcntr
&= ~DISPPLANE_TILED
;
2173 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2175 I915_WRITE(reg
, dspcntr
);
2177 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2178 intel_crtc
->dspaddr_offset
=
2179 intel_gen4_compute_offset_xtiled(&x
, &y
,
2180 fb
->bits_per_pixel
/ 8,
2182 linear_offset
-= intel_crtc
->dspaddr_offset
;
2184 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2185 obj
->gtt_offset
, linear_offset
, x
, y
, fb
->pitches
[0]);
2186 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2187 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2188 obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
2189 if (IS_HASWELL(dev
)) {
2190 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2192 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2193 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2200 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2202 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2203 int x
, int y
, enum mode_set_atomic state
)
2205 struct drm_device
*dev
= crtc
->dev
;
2206 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2208 if (dev_priv
->display
.disable_fbc
)
2209 dev_priv
->display
.disable_fbc(dev
);
2210 intel_increase_pllclock(crtc
);
2212 return dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2216 intel_finish_fb(struct drm_framebuffer
*old_fb
)
2218 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(old_fb
)->obj
;
2219 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2220 bool was_interruptible
= dev_priv
->mm
.interruptible
;
2223 wait_event(dev_priv
->pending_flip_queue
,
2224 atomic_read(&dev_priv
->mm
.wedged
) ||
2225 atomic_read(&obj
->pending_flip
) == 0);
2227 /* Big Hammer, we also need to ensure that any pending
2228 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2229 * current scanout is retired before unpinning the old
2232 * This should only fail upon a hung GPU, in which case we
2233 * can safely continue.
2235 dev_priv
->mm
.interruptible
= false;
2236 ret
= i915_gem_object_finish_gpu(obj
);
2237 dev_priv
->mm
.interruptible
= was_interruptible
;
2242 static void intel_crtc_update_sarea_pos(struct drm_crtc
*crtc
, int x
, int y
)
2244 struct drm_device
*dev
= crtc
->dev
;
2245 struct drm_i915_master_private
*master_priv
;
2246 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2248 if (!dev
->primary
->master
)
2251 master_priv
= dev
->primary
->master
->driver_priv
;
2252 if (!master_priv
->sarea_priv
)
2255 switch (intel_crtc
->pipe
) {
2257 master_priv
->sarea_priv
->pipeA_x
= x
;
2258 master_priv
->sarea_priv
->pipeA_y
= y
;
2261 master_priv
->sarea_priv
->pipeB_x
= x
;
2262 master_priv
->sarea_priv
->pipeB_y
= y
;
2270 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2271 struct drm_framebuffer
*fb
)
2273 struct drm_device
*dev
= crtc
->dev
;
2274 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2275 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2276 struct drm_framebuffer
*old_fb
;
2281 DRM_ERROR("No FB bound\n");
2285 if(intel_crtc
->plane
> dev_priv
->num_pipe
) {
2286 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2288 dev_priv
->num_pipe
);
2292 mutex_lock(&dev
->struct_mutex
);
2293 ret
= intel_pin_and_fence_fb_obj(dev
,
2294 to_intel_framebuffer(fb
)->obj
,
2297 mutex_unlock(&dev
->struct_mutex
);
2298 DRM_ERROR("pin & fence failed\n");
2303 intel_finish_fb(crtc
->fb
);
2305 ret
= dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2307 intel_unpin_fb_obj(to_intel_framebuffer(fb
)->obj
);
2308 mutex_unlock(&dev
->struct_mutex
);
2309 DRM_ERROR("failed to update base address\n");
2319 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2320 intel_unpin_fb_obj(to_intel_framebuffer(old_fb
)->obj
);
2323 intel_update_fbc(dev
);
2324 mutex_unlock(&dev
->struct_mutex
);
2326 intel_crtc_update_sarea_pos(crtc
, x
, y
);
2331 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
2333 struct drm_device
*dev
= crtc
->dev
;
2334 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2335 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2336 int pipe
= intel_crtc
->pipe
;
2339 /* enable normal train */
2340 reg
= FDI_TX_CTL(pipe
);
2341 temp
= I915_READ(reg
);
2342 if (IS_IVYBRIDGE(dev
)) {
2343 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2344 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2346 temp
&= ~FDI_LINK_TRAIN_NONE
;
2347 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2349 I915_WRITE(reg
, temp
);
2351 reg
= FDI_RX_CTL(pipe
);
2352 temp
= I915_READ(reg
);
2353 if (HAS_PCH_CPT(dev
)) {
2354 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2355 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2357 temp
&= ~FDI_LINK_TRAIN_NONE
;
2358 temp
|= FDI_LINK_TRAIN_NONE
;
2360 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2362 /* wait one idle pattern time */
2366 /* IVB wants error correction enabled */
2367 if (IS_IVYBRIDGE(dev
))
2368 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
2369 FDI_FE_ERRC_ENABLE
);
2372 static void ivb_modeset_global_resources(struct drm_device
*dev
)
2374 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2375 struct intel_crtc
*pipe_B_crtc
=
2376 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
2377 struct intel_crtc
*pipe_C_crtc
=
2378 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]);
2381 /* When everything is off disable fdi C so that we could enable fdi B
2382 * with all lanes. XXX: This misses the case where a pipe is not using
2383 * any pch resources and so doesn't need any fdi lanes. */
2384 if (!pipe_B_crtc
->base
.enabled
&& !pipe_C_crtc
->base
.enabled
) {
2385 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
2386 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
2388 temp
= I915_READ(SOUTH_CHICKEN1
);
2389 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
2390 DRM_DEBUG_KMS("disabling fdi C rx\n");
2391 I915_WRITE(SOUTH_CHICKEN1
, temp
);
2395 /* The FDI link training functions for ILK/Ibexpeak. */
2396 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
2398 struct drm_device
*dev
= crtc
->dev
;
2399 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2400 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2401 int pipe
= intel_crtc
->pipe
;
2402 int plane
= intel_crtc
->plane
;
2403 u32 reg
, temp
, tries
;
2405 /* FDI needs bits from pipe & plane first */
2406 assert_pipe_enabled(dev_priv
, pipe
);
2407 assert_plane_enabled(dev_priv
, plane
);
2409 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2411 reg
= FDI_RX_IMR(pipe
);
2412 temp
= I915_READ(reg
);
2413 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2414 temp
&= ~FDI_RX_BIT_LOCK
;
2415 I915_WRITE(reg
, temp
);
2419 /* enable CPU FDI TX and PCH FDI RX */
2420 reg
= FDI_TX_CTL(pipe
);
2421 temp
= I915_READ(reg
);
2423 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2424 temp
&= ~FDI_LINK_TRAIN_NONE
;
2425 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2426 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2428 reg
= FDI_RX_CTL(pipe
);
2429 temp
= I915_READ(reg
);
2430 temp
&= ~FDI_LINK_TRAIN_NONE
;
2431 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2432 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2437 /* Ironlake workaround, enable clock pointer after FDI enable*/
2438 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2439 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
2440 FDI_RX_PHASE_SYNC_POINTER_EN
);
2442 reg
= FDI_RX_IIR(pipe
);
2443 for (tries
= 0; tries
< 5; tries
++) {
2444 temp
= I915_READ(reg
);
2445 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2447 if ((temp
& FDI_RX_BIT_LOCK
)) {
2448 DRM_DEBUG_KMS("FDI train 1 done.\n");
2449 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2454 DRM_ERROR("FDI train 1 fail!\n");
2457 reg
= FDI_TX_CTL(pipe
);
2458 temp
= I915_READ(reg
);
2459 temp
&= ~FDI_LINK_TRAIN_NONE
;
2460 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2461 I915_WRITE(reg
, temp
);
2463 reg
= FDI_RX_CTL(pipe
);
2464 temp
= I915_READ(reg
);
2465 temp
&= ~FDI_LINK_TRAIN_NONE
;
2466 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2467 I915_WRITE(reg
, temp
);
2472 reg
= FDI_RX_IIR(pipe
);
2473 for (tries
= 0; tries
< 5; tries
++) {
2474 temp
= I915_READ(reg
);
2475 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2477 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2478 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2479 DRM_DEBUG_KMS("FDI train 2 done.\n");
2484 DRM_ERROR("FDI train 2 fail!\n");
2486 DRM_DEBUG_KMS("FDI train done\n");
2490 static const int snb_b_fdi_train_param
[] = {
2491 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
2492 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
2493 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
2494 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
2497 /* The FDI link training functions for SNB/Cougarpoint. */
2498 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
2500 struct drm_device
*dev
= crtc
->dev
;
2501 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2502 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2503 int pipe
= intel_crtc
->pipe
;
2504 u32 reg
, temp
, i
, retry
;
2506 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2508 reg
= FDI_RX_IMR(pipe
);
2509 temp
= I915_READ(reg
);
2510 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2511 temp
&= ~FDI_RX_BIT_LOCK
;
2512 I915_WRITE(reg
, temp
);
2517 /* enable CPU FDI TX and PCH FDI RX */
2518 reg
= FDI_TX_CTL(pipe
);
2519 temp
= I915_READ(reg
);
2521 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2522 temp
&= ~FDI_LINK_TRAIN_NONE
;
2523 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2524 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2526 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2527 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2529 I915_WRITE(FDI_RX_MISC(pipe
),
2530 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2532 reg
= FDI_RX_CTL(pipe
);
2533 temp
= I915_READ(reg
);
2534 if (HAS_PCH_CPT(dev
)) {
2535 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2536 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2538 temp
&= ~FDI_LINK_TRAIN_NONE
;
2539 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2541 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2546 for (i
= 0; i
< 4; i
++) {
2547 reg
= FDI_TX_CTL(pipe
);
2548 temp
= I915_READ(reg
);
2549 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2550 temp
|= snb_b_fdi_train_param
[i
];
2551 I915_WRITE(reg
, temp
);
2556 for (retry
= 0; retry
< 5; retry
++) {
2557 reg
= FDI_RX_IIR(pipe
);
2558 temp
= I915_READ(reg
);
2559 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2560 if (temp
& FDI_RX_BIT_LOCK
) {
2561 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2562 DRM_DEBUG_KMS("FDI train 1 done.\n");
2571 DRM_ERROR("FDI train 1 fail!\n");
2574 reg
= FDI_TX_CTL(pipe
);
2575 temp
= I915_READ(reg
);
2576 temp
&= ~FDI_LINK_TRAIN_NONE
;
2577 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2579 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2581 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2583 I915_WRITE(reg
, temp
);
2585 reg
= FDI_RX_CTL(pipe
);
2586 temp
= I915_READ(reg
);
2587 if (HAS_PCH_CPT(dev
)) {
2588 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2589 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2591 temp
&= ~FDI_LINK_TRAIN_NONE
;
2592 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2594 I915_WRITE(reg
, temp
);
2599 for (i
= 0; i
< 4; i
++) {
2600 reg
= FDI_TX_CTL(pipe
);
2601 temp
= I915_READ(reg
);
2602 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2603 temp
|= snb_b_fdi_train_param
[i
];
2604 I915_WRITE(reg
, temp
);
2609 for (retry
= 0; retry
< 5; retry
++) {
2610 reg
= FDI_RX_IIR(pipe
);
2611 temp
= I915_READ(reg
);
2612 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2613 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2614 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2615 DRM_DEBUG_KMS("FDI train 2 done.\n");
2624 DRM_ERROR("FDI train 2 fail!\n");
2626 DRM_DEBUG_KMS("FDI train done.\n");
2629 /* Manual link training for Ivy Bridge A0 parts */
2630 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
2632 struct drm_device
*dev
= crtc
->dev
;
2633 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2634 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2635 int pipe
= intel_crtc
->pipe
;
2638 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2640 reg
= FDI_RX_IMR(pipe
);
2641 temp
= I915_READ(reg
);
2642 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2643 temp
&= ~FDI_RX_BIT_LOCK
;
2644 I915_WRITE(reg
, temp
);
2649 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2650 I915_READ(FDI_RX_IIR(pipe
)));
2652 /* enable CPU FDI TX and PCH FDI RX */
2653 reg
= FDI_TX_CTL(pipe
);
2654 temp
= I915_READ(reg
);
2656 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2657 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
2658 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
2659 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2660 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2661 temp
|= FDI_COMPOSITE_SYNC
;
2662 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2664 I915_WRITE(FDI_RX_MISC(pipe
),
2665 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2667 reg
= FDI_RX_CTL(pipe
);
2668 temp
= I915_READ(reg
);
2669 temp
&= ~FDI_LINK_TRAIN_AUTO
;
2670 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2671 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2672 temp
|= FDI_COMPOSITE_SYNC
;
2673 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2678 for (i
= 0; i
< 4; i
++) {
2679 reg
= FDI_TX_CTL(pipe
);
2680 temp
= I915_READ(reg
);
2681 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2682 temp
|= snb_b_fdi_train_param
[i
];
2683 I915_WRITE(reg
, temp
);
2688 reg
= FDI_RX_IIR(pipe
);
2689 temp
= I915_READ(reg
);
2690 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2692 if (temp
& FDI_RX_BIT_LOCK
||
2693 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
2694 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2695 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i
);
2700 DRM_ERROR("FDI train 1 fail!\n");
2703 reg
= FDI_TX_CTL(pipe
);
2704 temp
= I915_READ(reg
);
2705 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2706 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
2707 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2708 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2709 I915_WRITE(reg
, temp
);
2711 reg
= FDI_RX_CTL(pipe
);
2712 temp
= I915_READ(reg
);
2713 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2714 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2715 I915_WRITE(reg
, temp
);
2720 for (i
= 0; i
< 4; i
++) {
2721 reg
= FDI_TX_CTL(pipe
);
2722 temp
= I915_READ(reg
);
2723 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2724 temp
|= snb_b_fdi_train_param
[i
];
2725 I915_WRITE(reg
, temp
);
2730 reg
= FDI_RX_IIR(pipe
);
2731 temp
= I915_READ(reg
);
2732 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2734 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2735 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2736 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i
);
2741 DRM_ERROR("FDI train 2 fail!\n");
2743 DRM_DEBUG_KMS("FDI train done.\n");
2746 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
2748 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2749 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2750 int pipe
= intel_crtc
->pipe
;
2754 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2755 reg
= FDI_RX_CTL(pipe
);
2756 temp
= I915_READ(reg
);
2757 temp
&= ~((0x7 << 19) | (0x7 << 16));
2758 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2759 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2760 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
2765 /* Switch from Rawclk to PCDclk */
2766 temp
= I915_READ(reg
);
2767 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
2772 /* Enable CPU FDI TX PLL, always on for Ironlake */
2773 reg
= FDI_TX_CTL(pipe
);
2774 temp
= I915_READ(reg
);
2775 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
2776 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
2783 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
2785 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2786 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2787 int pipe
= intel_crtc
->pipe
;
2790 /* Switch from PCDclk to Rawclk */
2791 reg
= FDI_RX_CTL(pipe
);
2792 temp
= I915_READ(reg
);
2793 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
2795 /* Disable CPU FDI TX PLL */
2796 reg
= FDI_TX_CTL(pipe
);
2797 temp
= I915_READ(reg
);
2798 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
2803 reg
= FDI_RX_CTL(pipe
);
2804 temp
= I915_READ(reg
);
2805 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
2807 /* Wait for the clocks to turn off. */
2812 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
2814 struct drm_device
*dev
= crtc
->dev
;
2815 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2816 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2817 int pipe
= intel_crtc
->pipe
;
2820 /* disable CPU FDI tx and PCH FDI rx */
2821 reg
= FDI_TX_CTL(pipe
);
2822 temp
= I915_READ(reg
);
2823 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
2826 reg
= FDI_RX_CTL(pipe
);
2827 temp
= I915_READ(reg
);
2828 temp
&= ~(0x7 << 16);
2829 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2830 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
2835 /* Ironlake workaround, disable clock pointer after downing FDI */
2836 if (HAS_PCH_IBX(dev
)) {
2837 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2840 /* still set train pattern 1 */
2841 reg
= FDI_TX_CTL(pipe
);
2842 temp
= I915_READ(reg
);
2843 temp
&= ~FDI_LINK_TRAIN_NONE
;
2844 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2845 I915_WRITE(reg
, temp
);
2847 reg
= FDI_RX_CTL(pipe
);
2848 temp
= I915_READ(reg
);
2849 if (HAS_PCH_CPT(dev
)) {
2850 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2851 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2853 temp
&= ~FDI_LINK_TRAIN_NONE
;
2854 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2856 /* BPC in FDI rx is consistent with that in PIPECONF */
2857 temp
&= ~(0x07 << 16);
2858 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2859 I915_WRITE(reg
, temp
);
2865 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
2867 struct drm_device
*dev
= crtc
->dev
;
2868 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2869 unsigned long flags
;
2872 if (atomic_read(&dev_priv
->mm
.wedged
))
2875 spin_lock_irqsave(&dev
->event_lock
, flags
);
2876 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
2877 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2882 static void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
2884 struct drm_device
*dev
= crtc
->dev
;
2885 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2887 if (crtc
->fb
== NULL
)
2890 wait_event(dev_priv
->pending_flip_queue
,
2891 !intel_crtc_has_pending_flip(crtc
));
2893 mutex_lock(&dev
->struct_mutex
);
2894 intel_finish_fb(crtc
->fb
);
2895 mutex_unlock(&dev
->struct_mutex
);
2898 static bool ironlake_crtc_driving_pch(struct drm_crtc
*crtc
)
2900 struct drm_device
*dev
= crtc
->dev
;
2901 struct intel_encoder
*intel_encoder
;
2904 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2905 * must be driven by its own crtc; no sharing is possible.
2907 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
2908 switch (intel_encoder
->type
) {
2909 case INTEL_OUTPUT_EDP
:
2910 if (!intel_encoder_is_pch_edp(&intel_encoder
->base
))
2919 static bool haswell_crtc_driving_pch(struct drm_crtc
*crtc
)
2921 return intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
);
2924 /* Program iCLKIP clock to the desired frequency */
2925 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
2927 struct drm_device
*dev
= crtc
->dev
;
2928 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2929 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
2932 mutex_lock(&dev_priv
->dpio_lock
);
2934 /* It is necessary to ungate the pixclk gate prior to programming
2935 * the divisors, and gate it back when it is done.
2937 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
2939 /* Disable SSCCTL */
2940 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
2941 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
2945 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2946 if (crtc
->mode
.clock
== 20000) {
2951 /* The iCLK virtual clock root frequency is in MHz,
2952 * but the crtc->mode.clock in in KHz. To get the divisors,
2953 * it is necessary to divide one by another, so we
2954 * convert the virtual clock precision to KHz here for higher
2957 u32 iclk_virtual_root_freq
= 172800 * 1000;
2958 u32 iclk_pi_range
= 64;
2959 u32 desired_divisor
, msb_divisor_value
, pi_value
;
2961 desired_divisor
= (iclk_virtual_root_freq
/ crtc
->mode
.clock
);
2962 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
2963 pi_value
= desired_divisor
% iclk_pi_range
;
2966 divsel
= msb_divisor_value
- 2;
2967 phaseinc
= pi_value
;
2970 /* This should not happen with any sane values */
2971 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
2972 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
2973 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
2974 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
2976 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2983 /* Program SSCDIVINTPHASE6 */
2984 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
2985 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
2986 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
2987 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
2988 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
2989 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
2990 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
2991 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
2993 /* Program SSCAUXDIV */
2994 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
2995 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2996 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
2997 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
2999 /* Enable modulator and associated divider */
3000 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
3001 temp
&= ~SBI_SSCCTL_DISABLE
;
3002 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
3004 /* Wait for initialization time */
3007 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
3009 mutex_unlock(&dev_priv
->dpio_lock
);
3013 * Enable PCH resources required for PCH ports:
3015 * - FDI training & RX/TX
3016 * - update transcoder timings
3017 * - DP transcoding bits
3020 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
3022 struct drm_device
*dev
= crtc
->dev
;
3023 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3024 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3025 int pipe
= intel_crtc
->pipe
;
3028 assert_transcoder_disabled(dev_priv
, pipe
);
3030 /* Write the TU size bits before fdi link training, so that error
3031 * detection works. */
3032 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
3033 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
3035 /* For PCH output, training FDI link */
3036 dev_priv
->display
.fdi_link_train(crtc
);
3038 /* XXX: pch pll's can be enabled any time before we enable the PCH
3039 * transcoder, and we actually should do this to not upset any PCH
3040 * transcoder that already use the clock when we share it.
3042 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3043 * unconditionally resets the pll - we need that to have the right LVDS
3044 * enable sequence. */
3045 ironlake_enable_pch_pll(intel_crtc
);
3047 if (HAS_PCH_CPT(dev
)) {
3050 temp
= I915_READ(PCH_DPLL_SEL
);
3054 temp
|= TRANSA_DPLL_ENABLE
;
3055 sel
= TRANSA_DPLLB_SEL
;
3058 temp
|= TRANSB_DPLL_ENABLE
;
3059 sel
= TRANSB_DPLLB_SEL
;
3062 temp
|= TRANSC_DPLL_ENABLE
;
3063 sel
= TRANSC_DPLLB_SEL
;
3066 if (intel_crtc
->pch_pll
->pll_reg
== _PCH_DPLL_B
)
3070 I915_WRITE(PCH_DPLL_SEL
, temp
);
3073 /* set transcoder timing, panel must allow it */
3074 assert_panel_unlocked(dev_priv
, pipe
);
3075 I915_WRITE(TRANS_HTOTAL(pipe
), I915_READ(HTOTAL(pipe
)));
3076 I915_WRITE(TRANS_HBLANK(pipe
), I915_READ(HBLANK(pipe
)));
3077 I915_WRITE(TRANS_HSYNC(pipe
), I915_READ(HSYNC(pipe
)));
3079 I915_WRITE(TRANS_VTOTAL(pipe
), I915_READ(VTOTAL(pipe
)));
3080 I915_WRITE(TRANS_VBLANK(pipe
), I915_READ(VBLANK(pipe
)));
3081 I915_WRITE(TRANS_VSYNC(pipe
), I915_READ(VSYNC(pipe
)));
3082 I915_WRITE(TRANS_VSYNCSHIFT(pipe
), I915_READ(VSYNCSHIFT(pipe
)));
3084 intel_fdi_normal_train(crtc
);
3086 /* For PCH DP, enable TRANS_DP_CTL */
3087 if (HAS_PCH_CPT(dev
) &&
3088 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
3089 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3090 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
3091 reg
= TRANS_DP_CTL(pipe
);
3092 temp
= I915_READ(reg
);
3093 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
3094 TRANS_DP_SYNC_MASK
|
3096 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
3097 TRANS_DP_ENH_FRAMING
);
3098 temp
|= bpc
<< 9; /* same format but at 11:9 */
3100 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
3101 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
3102 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
3103 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
3105 switch (intel_trans_dp_port_sel(crtc
)) {
3107 temp
|= TRANS_DP_PORT_SEL_B
;
3110 temp
|= TRANS_DP_PORT_SEL_C
;
3113 temp
|= TRANS_DP_PORT_SEL_D
;
3119 I915_WRITE(reg
, temp
);
3122 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
3125 static void lpt_pch_enable(struct drm_crtc
*crtc
)
3127 struct drm_device
*dev
= crtc
->dev
;
3128 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3129 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3130 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
3132 assert_transcoder_disabled(dev_priv
, TRANSCODER_A
);
3134 lpt_program_iclkip(crtc
);
3136 /* Set transcoder timing. */
3137 I915_WRITE(_TRANS_HTOTAL_A
, I915_READ(HTOTAL(cpu_transcoder
)));
3138 I915_WRITE(_TRANS_HBLANK_A
, I915_READ(HBLANK(cpu_transcoder
)));
3139 I915_WRITE(_TRANS_HSYNC_A
, I915_READ(HSYNC(cpu_transcoder
)));
3141 I915_WRITE(_TRANS_VTOTAL_A
, I915_READ(VTOTAL(cpu_transcoder
)));
3142 I915_WRITE(_TRANS_VBLANK_A
, I915_READ(VBLANK(cpu_transcoder
)));
3143 I915_WRITE(_TRANS_VSYNC_A
, I915_READ(VSYNC(cpu_transcoder
)));
3144 I915_WRITE(_TRANS_VSYNCSHIFT_A
, I915_READ(VSYNCSHIFT(cpu_transcoder
)));
3146 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
3149 static void intel_put_pch_pll(struct intel_crtc
*intel_crtc
)
3151 struct intel_pch_pll
*pll
= intel_crtc
->pch_pll
;
3156 if (pll
->refcount
== 0) {
3157 WARN(1, "bad PCH PLL refcount\n");
3162 intel_crtc
->pch_pll
= NULL
;
3165 static struct intel_pch_pll
*intel_get_pch_pll(struct intel_crtc
*intel_crtc
, u32 dpll
, u32 fp
)
3167 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
3168 struct intel_pch_pll
*pll
;
3171 pll
= intel_crtc
->pch_pll
;
3173 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3174 intel_crtc
->base
.base
.id
, pll
->pll_reg
);
3178 if (HAS_PCH_IBX(dev_priv
->dev
)) {
3179 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3180 i
= intel_crtc
->pipe
;
3181 pll
= &dev_priv
->pch_plls
[i
];
3183 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3184 intel_crtc
->base
.base
.id
, pll
->pll_reg
);
3189 for (i
= 0; i
< dev_priv
->num_pch_pll
; i
++) {
3190 pll
= &dev_priv
->pch_plls
[i
];
3192 /* Only want to check enabled timings first */
3193 if (pll
->refcount
== 0)
3196 if (dpll
== (I915_READ(pll
->pll_reg
) & 0x7fffffff) &&
3197 fp
== I915_READ(pll
->fp0_reg
)) {
3198 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3199 intel_crtc
->base
.base
.id
,
3200 pll
->pll_reg
, pll
->refcount
, pll
->active
);
3206 /* Ok no matching timings, maybe there's a free one? */
3207 for (i
= 0; i
< dev_priv
->num_pch_pll
; i
++) {
3208 pll
= &dev_priv
->pch_plls
[i
];
3209 if (pll
->refcount
== 0) {
3210 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3211 intel_crtc
->base
.base
.id
, pll
->pll_reg
);
3219 intel_crtc
->pch_pll
= pll
;
3221 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i
, intel_crtc
->pipe
);
3222 prepare
: /* separate function? */
3223 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll
->pll_reg
);
3225 /* Wait for the clocks to stabilize before rewriting the regs */
3226 I915_WRITE(pll
->pll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
3227 POSTING_READ(pll
->pll_reg
);
3230 I915_WRITE(pll
->fp0_reg
, fp
);
3231 I915_WRITE(pll
->pll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
3236 void intel_cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
3238 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3239 int dslreg
= PIPEDSL(pipe
);
3242 temp
= I915_READ(dslreg
);
3244 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
3245 if (wait_for(I915_READ(dslreg
) != temp
, 5))
3246 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe
);
3250 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
3252 struct drm_device
*dev
= crtc
->dev
;
3253 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3254 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3255 struct intel_encoder
*encoder
;
3256 int pipe
= intel_crtc
->pipe
;
3257 int plane
= intel_crtc
->plane
;
3261 WARN_ON(!crtc
->enabled
);
3263 if (intel_crtc
->active
)
3266 intel_crtc
->active
= true;
3267 intel_update_watermarks(dev
);
3269 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
3270 temp
= I915_READ(PCH_LVDS
);
3271 if ((temp
& LVDS_PORT_EN
) == 0)
3272 I915_WRITE(PCH_LVDS
, temp
| LVDS_PORT_EN
);
3275 is_pch_port
= ironlake_crtc_driving_pch(crtc
);
3278 /* Note: FDI PLL enabling _must_ be done before we enable the
3279 * cpu pipes, hence this is separate from all the other fdi/pch
3281 ironlake_fdi_pll_enable(intel_crtc
);
3283 assert_fdi_tx_disabled(dev_priv
, pipe
);
3284 assert_fdi_rx_disabled(dev_priv
, pipe
);
3287 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3288 if (encoder
->pre_enable
)
3289 encoder
->pre_enable(encoder
);
3291 /* Enable panel fitting for LVDS */
3292 if (dev_priv
->pch_pf_size
&&
3293 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) ||
3294 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3295 /* Force use of hard-coded filter coefficients
3296 * as some pre-programmed values are broken,
3299 if (IS_IVYBRIDGE(dev
))
3300 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
3301 PF_PIPE_SEL_IVB(pipe
));
3303 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
3304 I915_WRITE(PF_WIN_POS(pipe
), dev_priv
->pch_pf_pos
);
3305 I915_WRITE(PF_WIN_SZ(pipe
), dev_priv
->pch_pf_size
);
3309 * On ILK+ LUT must be loaded before the pipe is running but with
3312 intel_crtc_load_lut(crtc
);
3314 intel_enable_pipe(dev_priv
, pipe
, is_pch_port
);
3315 intel_enable_plane(dev_priv
, plane
, pipe
);
3318 ironlake_pch_enable(crtc
);
3320 mutex_lock(&dev
->struct_mutex
);
3321 intel_update_fbc(dev
);
3322 mutex_unlock(&dev
->struct_mutex
);
3324 intel_crtc_update_cursor(crtc
, true);
3326 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3327 encoder
->enable(encoder
);
3329 if (HAS_PCH_CPT(dev
))
3330 intel_cpt_verify_modeset(dev
, intel_crtc
->pipe
);
3333 * There seems to be a race in PCH platform hw (at least on some
3334 * outputs) where an enabled pipe still completes any pageflip right
3335 * away (as if the pipe is off) instead of waiting for vblank. As soon
3336 * as the first vblank happend, everything works as expected. Hence just
3337 * wait for one vblank before returning to avoid strange things
3340 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3343 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
3345 struct drm_device
*dev
= crtc
->dev
;
3346 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3347 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3348 struct intel_encoder
*encoder
;
3349 int pipe
= intel_crtc
->pipe
;
3350 int plane
= intel_crtc
->plane
;
3353 WARN_ON(!crtc
->enabled
);
3355 if (intel_crtc
->active
)
3358 intel_crtc
->active
= true;
3359 intel_update_watermarks(dev
);
3361 is_pch_port
= haswell_crtc_driving_pch(crtc
);
3364 dev_priv
->display
.fdi_link_train(crtc
);
3366 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3367 if (encoder
->pre_enable
)
3368 encoder
->pre_enable(encoder
);
3370 intel_ddi_enable_pipe_clock(intel_crtc
);
3372 /* Enable panel fitting for eDP */
3373 if (dev_priv
->pch_pf_size
&&
3374 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
)) {
3375 /* Force use of hard-coded filter coefficients
3376 * as some pre-programmed values are broken,
3379 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
3380 PF_PIPE_SEL_IVB(pipe
));
3381 I915_WRITE(PF_WIN_POS(pipe
), dev_priv
->pch_pf_pos
);
3382 I915_WRITE(PF_WIN_SZ(pipe
), dev_priv
->pch_pf_size
);
3386 * On ILK+ LUT must be loaded before the pipe is running but with
3389 intel_crtc_load_lut(crtc
);
3391 intel_ddi_set_pipe_settings(crtc
);
3392 intel_ddi_enable_pipe_func(crtc
);
3394 intel_enable_pipe(dev_priv
, pipe
, is_pch_port
);
3395 intel_enable_plane(dev_priv
, plane
, pipe
);
3398 lpt_pch_enable(crtc
);
3400 mutex_lock(&dev
->struct_mutex
);
3401 intel_update_fbc(dev
);
3402 mutex_unlock(&dev
->struct_mutex
);
3404 intel_crtc_update_cursor(crtc
, true);
3406 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3407 encoder
->enable(encoder
);
3410 * There seems to be a race in PCH platform hw (at least on some
3411 * outputs) where an enabled pipe still completes any pageflip right
3412 * away (as if the pipe is off) instead of waiting for vblank. As soon
3413 * as the first vblank happend, everything works as expected. Hence just
3414 * wait for one vblank before returning to avoid strange things
3417 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3420 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
3422 struct drm_device
*dev
= crtc
->dev
;
3423 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3424 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3425 struct intel_encoder
*encoder
;
3426 int pipe
= intel_crtc
->pipe
;
3427 int plane
= intel_crtc
->plane
;
3431 if (!intel_crtc
->active
)
3434 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3435 encoder
->disable(encoder
);
3437 intel_crtc_wait_for_pending_flips(crtc
);
3438 drm_vblank_off(dev
, pipe
);
3439 intel_crtc_update_cursor(crtc
, false);
3441 intel_disable_plane(dev_priv
, plane
, pipe
);
3443 if (dev_priv
->cfb_plane
== plane
)
3444 intel_disable_fbc(dev
);
3446 intel_disable_pipe(dev_priv
, pipe
);
3449 I915_WRITE(PF_CTL(pipe
), 0);
3450 I915_WRITE(PF_WIN_SZ(pipe
), 0);
3452 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3453 if (encoder
->post_disable
)
3454 encoder
->post_disable(encoder
);
3456 ironlake_fdi_disable(crtc
);
3458 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
3460 if (HAS_PCH_CPT(dev
)) {
3461 /* disable TRANS_DP_CTL */
3462 reg
= TRANS_DP_CTL(pipe
);
3463 temp
= I915_READ(reg
);
3464 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
| TRANS_DP_PORT_SEL_MASK
);
3465 temp
|= TRANS_DP_PORT_SEL_NONE
;
3466 I915_WRITE(reg
, temp
);
3468 /* disable DPLL_SEL */
3469 temp
= I915_READ(PCH_DPLL_SEL
);
3472 temp
&= ~(TRANSA_DPLL_ENABLE
| TRANSA_DPLLB_SEL
);
3475 temp
&= ~(TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
);
3478 /* C shares PLL A or B */
3479 temp
&= ~(TRANSC_DPLL_ENABLE
| TRANSC_DPLLB_SEL
);
3484 I915_WRITE(PCH_DPLL_SEL
, temp
);
3487 /* disable PCH DPLL */
3488 intel_disable_pch_pll(intel_crtc
);
3490 ironlake_fdi_pll_disable(intel_crtc
);
3492 intel_crtc
->active
= false;
3493 intel_update_watermarks(dev
);
3495 mutex_lock(&dev
->struct_mutex
);
3496 intel_update_fbc(dev
);
3497 mutex_unlock(&dev
->struct_mutex
);
3500 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
3502 struct drm_device
*dev
= crtc
->dev
;
3503 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3504 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3505 struct intel_encoder
*encoder
;
3506 int pipe
= intel_crtc
->pipe
;
3507 int plane
= intel_crtc
->plane
;
3508 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
3511 if (!intel_crtc
->active
)
3514 is_pch_port
= haswell_crtc_driving_pch(crtc
);
3516 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3517 encoder
->disable(encoder
);
3519 intel_crtc_wait_for_pending_flips(crtc
);
3520 drm_vblank_off(dev
, pipe
);
3521 intel_crtc_update_cursor(crtc
, false);
3523 intel_disable_plane(dev_priv
, plane
, pipe
);
3525 if (dev_priv
->cfb_plane
== plane
)
3526 intel_disable_fbc(dev
);
3528 intel_disable_pipe(dev_priv
, pipe
);
3530 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
3533 I915_WRITE(PF_CTL(pipe
), 0);
3534 I915_WRITE(PF_WIN_SZ(pipe
), 0);
3536 intel_ddi_disable_pipe_clock(intel_crtc
);
3538 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3539 if (encoder
->post_disable
)
3540 encoder
->post_disable(encoder
);
3543 lpt_disable_pch_transcoder(dev_priv
);
3544 intel_ddi_fdi_disable(crtc
);
3547 intel_crtc
->active
= false;
3548 intel_update_watermarks(dev
);
3550 mutex_lock(&dev
->struct_mutex
);
3551 intel_update_fbc(dev
);
3552 mutex_unlock(&dev
->struct_mutex
);
3555 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
3557 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3558 intel_put_pch_pll(intel_crtc
);
3561 static void haswell_crtc_off(struct drm_crtc
*crtc
)
3563 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3565 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3566 * start using it. */
3567 intel_crtc
->cpu_transcoder
= (enum transcoder
) intel_crtc
->pipe
;
3569 intel_ddi_put_crtc_pll(crtc
);
3572 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
3574 if (!enable
&& intel_crtc
->overlay
) {
3575 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3576 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3578 mutex_lock(&dev
->struct_mutex
);
3579 dev_priv
->mm
.interruptible
= false;
3580 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
3581 dev_priv
->mm
.interruptible
= true;
3582 mutex_unlock(&dev
->struct_mutex
);
3585 /* Let userspace switch the overlay on again. In most cases userspace
3586 * has to recompute where to put it anyway.
3590 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
3592 struct drm_device
*dev
= crtc
->dev
;
3593 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3594 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3595 struct intel_encoder
*encoder
;
3596 int pipe
= intel_crtc
->pipe
;
3597 int plane
= intel_crtc
->plane
;
3599 WARN_ON(!crtc
->enabled
);
3601 if (intel_crtc
->active
)
3604 intel_crtc
->active
= true;
3605 intel_update_watermarks(dev
);
3607 intel_enable_pll(dev_priv
, pipe
);
3608 intel_enable_pipe(dev_priv
, pipe
, false);
3609 intel_enable_plane(dev_priv
, plane
, pipe
);
3611 intel_crtc_load_lut(crtc
);
3612 intel_update_fbc(dev
);
3614 /* Give the overlay scaler a chance to enable if it's on this pipe */
3615 intel_crtc_dpms_overlay(intel_crtc
, true);
3616 intel_crtc_update_cursor(crtc
, true);
3618 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3619 encoder
->enable(encoder
);
3622 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
3624 struct drm_device
*dev
= crtc
->dev
;
3625 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3626 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3627 struct intel_encoder
*encoder
;
3628 int pipe
= intel_crtc
->pipe
;
3629 int plane
= intel_crtc
->plane
;
3632 if (!intel_crtc
->active
)
3635 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3636 encoder
->disable(encoder
);
3638 /* Give the overlay scaler a chance to disable if it's on this pipe */
3639 intel_crtc_wait_for_pending_flips(crtc
);
3640 drm_vblank_off(dev
, pipe
);
3641 intel_crtc_dpms_overlay(intel_crtc
, false);
3642 intel_crtc_update_cursor(crtc
, false);
3644 if (dev_priv
->cfb_plane
== plane
)
3645 intel_disable_fbc(dev
);
3647 intel_disable_plane(dev_priv
, plane
, pipe
);
3648 intel_disable_pipe(dev_priv
, pipe
);
3649 intel_disable_pll(dev_priv
, pipe
);
3651 intel_crtc
->active
= false;
3652 intel_update_fbc(dev
);
3653 intel_update_watermarks(dev
);
3656 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
3660 static void intel_crtc_update_sarea(struct drm_crtc
*crtc
,
3663 struct drm_device
*dev
= crtc
->dev
;
3664 struct drm_i915_master_private
*master_priv
;
3665 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3666 int pipe
= intel_crtc
->pipe
;
3668 if (!dev
->primary
->master
)
3671 master_priv
= dev
->primary
->master
->driver_priv
;
3672 if (!master_priv
->sarea_priv
)
3677 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3678 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3681 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3682 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3685 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe
));
3691 * Sets the power management mode of the pipe and plane.
3693 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
3695 struct drm_device
*dev
= crtc
->dev
;
3696 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3697 struct intel_encoder
*intel_encoder
;
3698 bool enable
= false;
3700 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
3701 enable
|= intel_encoder
->connectors_active
;
3704 dev_priv
->display
.crtc_enable(crtc
);
3706 dev_priv
->display
.crtc_disable(crtc
);
3708 intel_crtc_update_sarea(crtc
, enable
);
3711 static void intel_crtc_noop(struct drm_crtc
*crtc
)
3715 static void intel_crtc_disable(struct drm_crtc
*crtc
)
3717 struct drm_device
*dev
= crtc
->dev
;
3718 struct drm_connector
*connector
;
3719 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3721 /* crtc should still be enabled when we disable it. */
3722 WARN_ON(!crtc
->enabled
);
3724 dev_priv
->display
.crtc_disable(crtc
);
3725 intel_crtc_update_sarea(crtc
, false);
3726 dev_priv
->display
.off(crtc
);
3728 assert_plane_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->plane
);
3729 assert_pipe_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->pipe
);
3732 mutex_lock(&dev
->struct_mutex
);
3733 intel_unpin_fb_obj(to_intel_framebuffer(crtc
->fb
)->obj
);
3734 mutex_unlock(&dev
->struct_mutex
);
3738 /* Update computed state. */
3739 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
3740 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
3743 if (connector
->encoder
->crtc
!= crtc
)
3746 connector
->dpms
= DRM_MODE_DPMS_OFF
;
3747 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
3751 void intel_modeset_disable(struct drm_device
*dev
)
3753 struct drm_crtc
*crtc
;
3755 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
3757 intel_crtc_disable(crtc
);
3761 void intel_encoder_noop(struct drm_encoder
*encoder
)
3765 void intel_encoder_destroy(struct drm_encoder
*encoder
)
3767 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
3769 drm_encoder_cleanup(encoder
);
3770 kfree(intel_encoder
);
3773 /* Simple dpms helper for encodres with just one connector, no cloning and only
3774 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3775 * state of the entire output pipe. */
3776 void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
3778 if (mode
== DRM_MODE_DPMS_ON
) {
3779 encoder
->connectors_active
= true;
3781 intel_crtc_update_dpms(encoder
->base
.crtc
);
3783 encoder
->connectors_active
= false;
3785 intel_crtc_update_dpms(encoder
->base
.crtc
);
3789 /* Cross check the actual hw state with our own modeset state tracking (and it's
3790 * internal consistency). */
3791 static void intel_connector_check_state(struct intel_connector
*connector
)
3793 if (connector
->get_hw_state(connector
)) {
3794 struct intel_encoder
*encoder
= connector
->encoder
;
3795 struct drm_crtc
*crtc
;
3796 bool encoder_enabled
;
3799 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3800 connector
->base
.base
.id
,
3801 drm_get_connector_name(&connector
->base
));
3803 WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
3804 "wrong connector dpms state\n");
3805 WARN(connector
->base
.encoder
!= &encoder
->base
,
3806 "active connector not linked to encoder\n");
3807 WARN(!encoder
->connectors_active
,
3808 "encoder->connectors_active not set\n");
3810 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
3811 WARN(!encoder_enabled
, "encoder not enabled\n");
3812 if (WARN_ON(!encoder
->base
.crtc
))
3815 crtc
= encoder
->base
.crtc
;
3817 WARN(!crtc
->enabled
, "crtc not enabled\n");
3818 WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
3819 WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
3820 "encoder active on the wrong pipe\n");
3824 /* Even simpler default implementation, if there's really no special case to
3826 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
3828 struct intel_encoder
*encoder
= intel_attached_encoder(connector
);
3830 /* All the simple cases only support two dpms states. */
3831 if (mode
!= DRM_MODE_DPMS_ON
)
3832 mode
= DRM_MODE_DPMS_OFF
;
3834 if (mode
== connector
->dpms
)
3837 connector
->dpms
= mode
;
3839 /* Only need to change hw state when actually enabled */
3840 if (encoder
->base
.crtc
)
3841 intel_encoder_dpms(encoder
, mode
);
3843 WARN_ON(encoder
->connectors_active
!= false);
3845 intel_modeset_check_state(connector
->dev
);
3848 /* Simple connector->get_hw_state implementation for encoders that support only
3849 * one connector and no cloning and hence the encoder state determines the state
3850 * of the connector. */
3851 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
3854 struct intel_encoder
*encoder
= connector
->encoder
;
3856 return encoder
->get_hw_state(encoder
, &pipe
);
3859 static bool intel_crtc_mode_fixup(struct drm_crtc
*crtc
,
3860 const struct drm_display_mode
*mode
,
3861 struct drm_display_mode
*adjusted_mode
)
3863 struct drm_device
*dev
= crtc
->dev
;
3865 if (HAS_PCH_SPLIT(dev
)) {
3866 /* FDI link clock is fixed at 2.7G */
3867 if (mode
->clock
* 3 > IRONLAKE_FDI_FREQ
* 4)
3871 /* All interlaced capable intel hw wants timings in frames. Note though
3872 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3873 * timings, so we need to be careful not to clobber these.*/
3874 if (!(adjusted_mode
->private_flags
& INTEL_MODE_CRTC_TIMINGS_SET
))
3875 drm_mode_set_crtcinfo(adjusted_mode
, 0);
3877 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3878 * with a hsync front porch of 0.
3880 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
3881 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
3887 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
3889 return 400000; /* FIXME */
3892 static int i945_get_display_clock_speed(struct drm_device
*dev
)
3897 static int i915_get_display_clock_speed(struct drm_device
*dev
)
3902 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
3907 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
3911 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
3913 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
3916 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
3917 case GC_DISPLAY_CLOCK_333_MHZ
:
3920 case GC_DISPLAY_CLOCK_190_200_MHZ
:
3926 static int i865_get_display_clock_speed(struct drm_device
*dev
)
3931 static int i855_get_display_clock_speed(struct drm_device
*dev
)
3934 /* Assume that the hardware is in the high speed state. This
3935 * should be the default.
3937 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
3938 case GC_CLOCK_133_200
:
3939 case GC_CLOCK_100_200
:
3941 case GC_CLOCK_166_250
:
3943 case GC_CLOCK_100_133
:
3947 /* Shouldn't happen */
3951 static int i830_get_display_clock_speed(struct drm_device
*dev
)
3957 intel_reduce_ratio(uint32_t *num
, uint32_t *den
)
3959 while (*num
> 0xffffff || *den
> 0xffffff) {
3966 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
3967 int pixel_clock
, int link_clock
,
3968 struct intel_link_m_n
*m_n
)
3971 m_n
->gmch_m
= bits_per_pixel
* pixel_clock
;
3972 m_n
->gmch_n
= link_clock
* nlanes
* 8;
3973 intel_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
3974 m_n
->link_m
= pixel_clock
;
3975 m_n
->link_n
= link_clock
;
3976 intel_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
3979 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
3981 if (i915_panel_use_ssc
>= 0)
3982 return i915_panel_use_ssc
!= 0;
3983 return dev_priv
->lvds_use_ssc
3984 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
3988 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3989 * @crtc: CRTC structure
3990 * @mode: requested mode
3992 * A pipe may be connected to one or more outputs. Based on the depth of the
3993 * attached framebuffer, choose a good color depth to use on the pipe.
3995 * If possible, match the pipe depth to the fb depth. In some cases, this
3996 * isn't ideal, because the connected output supports a lesser or restricted
3997 * set of depths. Resolve that here:
3998 * LVDS typically supports only 6bpc, so clamp down in that case
3999 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4000 * Displays may support a restricted set as well, check EDID and clamp as
4002 * DP may want to dither down to 6bpc to fit larger modes
4005 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4006 * true if they don't match).
4008 static bool intel_choose_pipe_bpp_dither(struct drm_crtc
*crtc
,
4009 struct drm_framebuffer
*fb
,
4010 unsigned int *pipe_bpp
,
4011 struct drm_display_mode
*mode
)
4013 struct drm_device
*dev
= crtc
->dev
;
4014 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4015 struct drm_connector
*connector
;
4016 struct intel_encoder
*intel_encoder
;
4017 unsigned int display_bpc
= UINT_MAX
, bpc
;
4019 /* Walk the encoders & connectors on this crtc, get min bpc */
4020 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
4022 if (intel_encoder
->type
== INTEL_OUTPUT_LVDS
) {
4023 unsigned int lvds_bpc
;
4025 if ((I915_READ(PCH_LVDS
) & LVDS_A3_POWER_MASK
) ==
4031 if (lvds_bpc
< display_bpc
) {
4032 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc
, lvds_bpc
);
4033 display_bpc
= lvds_bpc
;
4038 /* Not one of the known troublemakers, check the EDID */
4039 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
4041 if (connector
->encoder
!= &intel_encoder
->base
)
4044 /* Don't use an invalid EDID bpc value */
4045 if (connector
->display_info
.bpc
&&
4046 connector
->display_info
.bpc
< display_bpc
) {
4047 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc
, connector
->display_info
.bpc
);
4048 display_bpc
= connector
->display_info
.bpc
;
4052 if (intel_encoder
->type
== INTEL_OUTPUT_EDP
) {
4053 /* Use VBT settings if we have an eDP panel */
4054 unsigned int edp_bpc
= dev_priv
->edp
.bpp
/ 3;
4056 if (edp_bpc
&& edp_bpc
< display_bpc
) {
4057 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc
, edp_bpc
);
4058 display_bpc
= edp_bpc
;
4064 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4065 * through, clamp it down. (Note: >12bpc will be caught below.)
4067 if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
) {
4068 if (display_bpc
> 8 && display_bpc
< 12) {
4069 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4072 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4078 if (mode
->private_flags
& INTEL_MODE_DP_FORCE_6BPC
) {
4079 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4084 * We could just drive the pipe at the highest bpc all the time and
4085 * enable dithering as needed, but that costs bandwidth. So choose
4086 * the minimum value that expresses the full color range of the fb but
4087 * also stays within the max display bpc discovered above.
4090 switch (fb
->depth
) {
4092 bpc
= 8; /* since we go through a colormap */
4096 bpc
= 6; /* min is 18bpp */
4108 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4109 bpc
= min((unsigned int)8, display_bpc
);
4113 display_bpc
= min(display_bpc
, bpc
);
4115 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4118 *pipe_bpp
= display_bpc
* 3;
4120 return display_bpc
!= bpc
;
4123 static int vlv_get_refclk(struct drm_crtc
*crtc
)
4125 struct drm_device
*dev
= crtc
->dev
;
4126 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4127 int refclk
= 27000; /* for DP & HDMI */
4129 return 100000; /* only one validated so far */
4131 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
4133 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
4134 if (intel_panel_use_ssc(dev_priv
))
4138 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
)) {
4145 static int i9xx_get_refclk(struct drm_crtc
*crtc
, int num_connectors
)
4147 struct drm_device
*dev
= crtc
->dev
;
4148 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4151 if (IS_VALLEYVIEW(dev
)) {
4152 refclk
= vlv_get_refclk(crtc
);
4153 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4154 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
4155 refclk
= dev_priv
->lvds_ssc_freq
* 1000;
4156 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4158 } else if (!IS_GEN2(dev
)) {
4167 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode
*adjusted_mode
,
4168 intel_clock_t
*clock
)
4170 /* SDVO TV has fixed PLL values depend on its clock range,
4171 this mirrors vbios setting. */
4172 if (adjusted_mode
->clock
>= 100000
4173 && adjusted_mode
->clock
< 140500) {
4179 } else if (adjusted_mode
->clock
>= 140500
4180 && adjusted_mode
->clock
<= 200000) {
4189 static void i9xx_update_pll_dividers(struct drm_crtc
*crtc
,
4190 intel_clock_t
*clock
,
4191 intel_clock_t
*reduced_clock
)
4193 struct drm_device
*dev
= crtc
->dev
;
4194 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4195 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4196 int pipe
= intel_crtc
->pipe
;
4199 if (IS_PINEVIEW(dev
)) {
4200 fp
= (1 << clock
->n
) << 16 | clock
->m1
<< 8 | clock
->m2
;
4202 fp2
= (1 << reduced_clock
->n
) << 16 |
4203 reduced_clock
->m1
<< 8 | reduced_clock
->m2
;
4205 fp
= clock
->n
<< 16 | clock
->m1
<< 8 | clock
->m2
;
4207 fp2
= reduced_clock
->n
<< 16 | reduced_clock
->m1
<< 8 |
4211 I915_WRITE(FP0(pipe
), fp
);
4213 intel_crtc
->lowfreq_avail
= false;
4214 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4215 reduced_clock
&& i915_powersave
) {
4216 I915_WRITE(FP1(pipe
), fp2
);
4217 intel_crtc
->lowfreq_avail
= true;
4219 I915_WRITE(FP1(pipe
), fp
);
4223 static void vlv_update_pll(struct drm_crtc
*crtc
,
4224 struct drm_display_mode
*mode
,
4225 struct drm_display_mode
*adjusted_mode
,
4226 intel_clock_t
*clock
, intel_clock_t
*reduced_clock
,
4229 struct drm_device
*dev
= crtc
->dev
;
4230 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4231 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4232 int pipe
= intel_crtc
->pipe
;
4233 u32 dpll
, mdiv
, pdiv
;
4234 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
4238 mutex_lock(&dev_priv
->dpio_lock
);
4240 is_sdvo
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
) ||
4241 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
);
4243 dpll
= DPLL_VGA_MODE_DIS
;
4244 dpll
|= DPLL_EXT_BUFFER_ENABLE_VLV
;
4245 dpll
|= DPLL_REFA_CLK_ENABLE_VLV
;
4246 dpll
|= DPLL_INTEGRATED_CLOCK_VLV
;
4248 I915_WRITE(DPLL(pipe
), dpll
);
4249 POSTING_READ(DPLL(pipe
));
4258 * In Valleyview PLL and program lane counter registers are exposed
4259 * through DPIO interface
4261 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
4262 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
4263 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
4264 mdiv
|= (1 << DPIO_POST_DIV_SHIFT
);
4265 mdiv
|= (1 << DPIO_K_SHIFT
);
4266 mdiv
|= DPIO_ENABLE_CALIBRATION
;
4267 intel_dpio_write(dev_priv
, DPIO_DIV(pipe
), mdiv
);
4269 intel_dpio_write(dev_priv
, DPIO_CORE_CLK(pipe
), 0x01000000);
4271 pdiv
= (1 << DPIO_REFSEL_OVERRIDE
) | (5 << DPIO_PLL_MODESEL_SHIFT
) |
4272 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT
) | (1<<20) |
4273 (7 << DPIO_PLL_REFCLK_SEL_SHIFT
) | (8 << DPIO_DRIVER_CTL_SHIFT
) |
4274 (5 << DPIO_CLK_BIAS_CTL_SHIFT
);
4275 intel_dpio_write(dev_priv
, DPIO_REFSFR(pipe
), pdiv
);
4277 intel_dpio_write(dev_priv
, DPIO_LFP_COEFF(pipe
), 0x005f003b);
4279 dpll
|= DPLL_VCO_ENABLE
;
4280 I915_WRITE(DPLL(pipe
), dpll
);
4281 POSTING_READ(DPLL(pipe
));
4282 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
4283 DRM_ERROR("DPLL %d failed to lock\n", pipe
);
4285 intel_dpio_write(dev_priv
, DPIO_FASTCLK_DISABLE
, 0x620);
4287 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
))
4288 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
4290 I915_WRITE(DPLL(pipe
), dpll
);
4292 /* Wait for the clocks to stabilize. */
4293 POSTING_READ(DPLL(pipe
));
4298 temp
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4300 temp
= (temp
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4304 I915_WRITE(DPLL_MD(pipe
), temp
);
4305 POSTING_READ(DPLL_MD(pipe
));
4307 /* Now program lane control registers */
4308 if(intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)
4309 || intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
4314 intel_dpio_write(dev_priv
, DPIO_DATA_CHANNEL1
, temp
);
4316 if(intel_pipe_has_type(crtc
,INTEL_OUTPUT_EDP
))
4321 intel_dpio_write(dev_priv
, DPIO_DATA_CHANNEL2
, temp
);
4324 mutex_unlock(&dev_priv
->dpio_lock
);
4327 static void i9xx_update_pll(struct drm_crtc
*crtc
,
4328 struct drm_display_mode
*mode
,
4329 struct drm_display_mode
*adjusted_mode
,
4330 intel_clock_t
*clock
, intel_clock_t
*reduced_clock
,
4333 struct drm_device
*dev
= crtc
->dev
;
4334 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4335 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4336 struct intel_encoder
*encoder
;
4337 int pipe
= intel_crtc
->pipe
;
4341 i9xx_update_pll_dividers(crtc
, clock
, reduced_clock
);
4343 is_sdvo
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
) ||
4344 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
);
4346 dpll
= DPLL_VGA_MODE_DIS
;
4348 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
4349 dpll
|= DPLLB_MODE_LVDS
;
4351 dpll
|= DPLLB_MODE_DAC_SERIAL
;
4353 int pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4354 if (pixel_multiplier
> 1) {
4355 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4356 dpll
|= (pixel_multiplier
- 1) << SDVO_MULTIPLIER_SHIFT_HIRES
;
4358 dpll
|= DPLL_DVO_HIGH_SPEED
;
4360 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
))
4361 dpll
|= DPLL_DVO_HIGH_SPEED
;
4363 /* compute bitmask from p1 value */
4364 if (IS_PINEVIEW(dev
))
4365 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
4367 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4368 if (IS_G4X(dev
) && reduced_clock
)
4369 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
4371 switch (clock
->p2
) {
4373 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
4376 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
4379 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
4382 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
4385 if (INTEL_INFO(dev
)->gen
>= 4)
4386 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
4388 if (is_sdvo
&& intel_pipe_has_type(crtc
, INTEL_OUTPUT_TVOUT
))
4389 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
4390 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_TVOUT
))
4391 /* XXX: just matching BIOS for now */
4392 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4394 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4395 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4396 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4398 dpll
|= PLL_REF_INPUT_DREFCLK
;
4400 dpll
|= DPLL_VCO_ENABLE
;
4401 I915_WRITE(DPLL(pipe
), dpll
& ~DPLL_VCO_ENABLE
);
4402 POSTING_READ(DPLL(pipe
));
4405 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4406 if (encoder
->pre_pll_enable
)
4407 encoder
->pre_pll_enable(encoder
);
4409 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
))
4410 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
4412 I915_WRITE(DPLL(pipe
), dpll
);
4414 /* Wait for the clocks to stabilize. */
4415 POSTING_READ(DPLL(pipe
));
4418 if (INTEL_INFO(dev
)->gen
>= 4) {
4421 temp
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4423 temp
= (temp
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4427 I915_WRITE(DPLL_MD(pipe
), temp
);
4429 /* The pixel multiplier can only be updated once the
4430 * DPLL is enabled and the clocks are stable.
4432 * So write it again.
4434 I915_WRITE(DPLL(pipe
), dpll
);
4438 static void i8xx_update_pll(struct drm_crtc
*crtc
,
4439 struct drm_display_mode
*adjusted_mode
,
4440 intel_clock_t
*clock
, intel_clock_t
*reduced_clock
,
4443 struct drm_device
*dev
= crtc
->dev
;
4444 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4445 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4446 struct intel_encoder
*encoder
;
4447 int pipe
= intel_crtc
->pipe
;
4450 i9xx_update_pll_dividers(crtc
, clock
, reduced_clock
);
4452 dpll
= DPLL_VGA_MODE_DIS
;
4454 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
4455 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4458 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
4460 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4462 dpll
|= PLL_P2_DIVIDE_BY_4
;
4465 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_TVOUT
))
4466 /* XXX: just matching BIOS for now */
4467 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4469 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4470 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4471 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4473 dpll
|= PLL_REF_INPUT_DREFCLK
;
4475 dpll
|= DPLL_VCO_ENABLE
;
4476 I915_WRITE(DPLL(pipe
), dpll
& ~DPLL_VCO_ENABLE
);
4477 POSTING_READ(DPLL(pipe
));
4480 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4481 if (encoder
->pre_pll_enable
)
4482 encoder
->pre_pll_enable(encoder
);
4484 I915_WRITE(DPLL(pipe
), dpll
);
4486 /* Wait for the clocks to stabilize. */
4487 POSTING_READ(DPLL(pipe
));
4490 /* The pixel multiplier can only be updated once the
4491 * DPLL is enabled and the clocks are stable.
4493 * So write it again.
4495 I915_WRITE(DPLL(pipe
), dpll
);
4498 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
,
4499 struct drm_display_mode
*mode
,
4500 struct drm_display_mode
*adjusted_mode
)
4502 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4503 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4504 enum pipe pipe
= intel_crtc
->pipe
;
4505 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
4506 uint32_t vsyncshift
;
4508 if (!IS_GEN2(dev
) && adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
4509 /* the chip adds 2 halflines automatically */
4510 adjusted_mode
->crtc_vtotal
-= 1;
4511 adjusted_mode
->crtc_vblank_end
-= 1;
4512 vsyncshift
= adjusted_mode
->crtc_hsync_start
4513 - adjusted_mode
->crtc_htotal
/ 2;
4518 if (INTEL_INFO(dev
)->gen
> 3)
4519 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
4521 I915_WRITE(HTOTAL(cpu_transcoder
),
4522 (adjusted_mode
->crtc_hdisplay
- 1) |
4523 ((adjusted_mode
->crtc_htotal
- 1) << 16));
4524 I915_WRITE(HBLANK(cpu_transcoder
),
4525 (adjusted_mode
->crtc_hblank_start
- 1) |
4526 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
4527 I915_WRITE(HSYNC(cpu_transcoder
),
4528 (adjusted_mode
->crtc_hsync_start
- 1) |
4529 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
4531 I915_WRITE(VTOTAL(cpu_transcoder
),
4532 (adjusted_mode
->crtc_vdisplay
- 1) |
4533 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
4534 I915_WRITE(VBLANK(cpu_transcoder
),
4535 (adjusted_mode
->crtc_vblank_start
- 1) |
4536 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
4537 I915_WRITE(VSYNC(cpu_transcoder
),
4538 (adjusted_mode
->crtc_vsync_start
- 1) |
4539 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
4541 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4542 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4543 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4545 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
4546 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
4547 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
4549 /* pipesrc controls the size that is scaled from, which should
4550 * always be the user's requested size.
4552 I915_WRITE(PIPESRC(pipe
),
4553 ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
4556 static int i9xx_crtc_mode_set(struct drm_crtc
*crtc
,
4557 struct drm_display_mode
*mode
,
4558 struct drm_display_mode
*adjusted_mode
,
4560 struct drm_framebuffer
*fb
)
4562 struct drm_device
*dev
= crtc
->dev
;
4563 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4564 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4565 int pipe
= intel_crtc
->pipe
;
4566 int plane
= intel_crtc
->plane
;
4567 int refclk
, num_connectors
= 0;
4568 intel_clock_t clock
, reduced_clock
;
4569 u32 dspcntr
, pipeconf
;
4570 bool ok
, has_reduced_clock
= false, is_sdvo
= false;
4571 bool is_lvds
= false, is_tv
= false, is_dp
= false;
4572 struct intel_encoder
*encoder
;
4573 const intel_limit_t
*limit
;
4576 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4577 switch (encoder
->type
) {
4578 case INTEL_OUTPUT_LVDS
:
4581 case INTEL_OUTPUT_SDVO
:
4582 case INTEL_OUTPUT_HDMI
:
4584 if (encoder
->needs_tv_clock
)
4587 case INTEL_OUTPUT_TVOUT
:
4590 case INTEL_OUTPUT_DISPLAYPORT
:
4598 refclk
= i9xx_get_refclk(crtc
, num_connectors
);
4601 * Returns a set of divisors for the desired target clock with the given
4602 * refclk, or FALSE. The returned values represent the clock equation:
4603 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4605 limit
= intel_limit(crtc
, refclk
);
4606 ok
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, NULL
,
4609 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4613 /* Ensure that the cursor is valid for the new mode before changing... */
4614 intel_crtc_update_cursor(crtc
, true);
4616 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
4618 * Ensure we match the reduced clock's P to the target clock.
4619 * If the clocks don't match, we can't switch the display clock
4620 * by using the FP0/FP1. In such case we will disable the LVDS
4621 * downclock feature.
4623 has_reduced_clock
= limit
->find_pll(limit
, crtc
,
4624 dev_priv
->lvds_downclock
,
4630 if (is_sdvo
&& is_tv
)
4631 i9xx_adjust_sdvo_tv_clock(adjusted_mode
, &clock
);
4634 i8xx_update_pll(crtc
, adjusted_mode
, &clock
,
4635 has_reduced_clock
? &reduced_clock
: NULL
,
4637 else if (IS_VALLEYVIEW(dev
))
4638 vlv_update_pll(crtc
, mode
, adjusted_mode
, &clock
,
4639 has_reduced_clock
? &reduced_clock
: NULL
,
4642 i9xx_update_pll(crtc
, mode
, adjusted_mode
, &clock
,
4643 has_reduced_clock
? &reduced_clock
: NULL
,
4646 /* setup pipeconf */
4647 pipeconf
= I915_READ(PIPECONF(pipe
));
4649 /* Set up the display plane register */
4650 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
4653 dspcntr
&= ~DISPPLANE_SEL_PIPE_MASK
;
4655 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
4657 if (pipe
== 0 && INTEL_INFO(dev
)->gen
< 4) {
4658 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4661 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4665 dev_priv
->display
.get_display_clock_speed(dev
) * 9 / 10)
4666 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
4668 pipeconf
&= ~PIPECONF_DOUBLE_WIDE
;
4671 /* default to 8bpc */
4672 pipeconf
&= ~(PIPECONF_BPC_MASK
| PIPECONF_DITHER_EN
);
4674 if (adjusted_mode
->private_flags
& INTEL_MODE_DP_FORCE_6BPC
) {
4675 pipeconf
|= PIPECONF_6BPC
|
4676 PIPECONF_DITHER_EN
|
4677 PIPECONF_DITHER_TYPE_SP
;
4681 if (IS_VALLEYVIEW(dev
) && intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
)) {
4682 if (adjusted_mode
->private_flags
& INTEL_MODE_DP_FORCE_6BPC
) {
4683 pipeconf
|= PIPECONF_6BPC
|
4685 I965_PIPECONF_ACTIVE
;
4689 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe
== 0 ? 'A' : 'B');
4690 drm_mode_debug_printmodeline(mode
);
4692 if (HAS_PIPE_CXSR(dev
)) {
4693 if (intel_crtc
->lowfreq_avail
) {
4694 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4695 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
4697 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4698 pipeconf
&= ~PIPECONF_CXSR_DOWNCLOCK
;
4702 pipeconf
&= ~PIPECONF_INTERLACE_MASK
;
4703 if (!IS_GEN2(dev
) &&
4704 adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
4705 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
4707 pipeconf
|= PIPECONF_PROGRESSIVE
;
4709 intel_set_pipe_timings(intel_crtc
, mode
, adjusted_mode
);
4711 /* pipesrc and dspsize control the size that is scaled from,
4712 * which should always be the user's requested size.
4714 I915_WRITE(DSPSIZE(plane
),
4715 ((mode
->vdisplay
- 1) << 16) |
4716 (mode
->hdisplay
- 1));
4717 I915_WRITE(DSPPOS(plane
), 0);
4719 I915_WRITE(PIPECONF(pipe
), pipeconf
);
4720 POSTING_READ(PIPECONF(pipe
));
4721 intel_enable_pipe(dev_priv
, pipe
, false);
4723 intel_wait_for_vblank(dev
, pipe
);
4725 I915_WRITE(DSPCNTR(plane
), dspcntr
);
4726 POSTING_READ(DSPCNTR(plane
));
4728 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
4730 intel_update_watermarks(dev
);
4735 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
4737 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4738 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
4739 struct intel_encoder
*encoder
;
4741 bool has_lvds
= false;
4742 bool has_cpu_edp
= false;
4743 bool has_pch_edp
= false;
4744 bool has_panel
= false;
4745 bool has_ck505
= false;
4746 bool can_ssc
= false;
4748 /* We need to take the global config into account */
4749 list_for_each_entry(encoder
, &mode_config
->encoder_list
,
4751 switch (encoder
->type
) {
4752 case INTEL_OUTPUT_LVDS
:
4756 case INTEL_OUTPUT_EDP
:
4758 if (intel_encoder_is_pch_edp(&encoder
->base
))
4766 if (HAS_PCH_IBX(dev
)) {
4767 has_ck505
= dev_priv
->display_clock_mode
;
4768 can_ssc
= has_ck505
;
4774 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4775 has_panel
, has_lvds
, has_pch_edp
, has_cpu_edp
,
4778 /* Ironlake: try to setup display ref clock before DPLL
4779 * enabling. This is only under driver's control after
4780 * PCH B stepping, previous chipset stepping should be
4781 * ignoring this setting.
4783 temp
= I915_READ(PCH_DREF_CONTROL
);
4784 /* Always enable nonspread source */
4785 temp
&= ~DREF_NONSPREAD_SOURCE_MASK
;
4788 temp
|= DREF_NONSPREAD_CK505_ENABLE
;
4790 temp
|= DREF_NONSPREAD_SOURCE_ENABLE
;
4793 temp
&= ~DREF_SSC_SOURCE_MASK
;
4794 temp
|= DREF_SSC_SOURCE_ENABLE
;
4796 /* SSC must be turned on before enabling the CPU output */
4797 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
4798 DRM_DEBUG_KMS("Using SSC on panel\n");
4799 temp
|= DREF_SSC1_ENABLE
;
4801 temp
&= ~DREF_SSC1_ENABLE
;
4803 /* Get SSC going before enabling the outputs */
4804 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4805 POSTING_READ(PCH_DREF_CONTROL
);
4808 temp
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
4810 /* Enable CPU source on CPU attached eDP */
4812 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
4813 DRM_DEBUG_KMS("Using SSC on eDP\n");
4814 temp
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
4817 temp
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
4819 temp
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
4821 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4822 POSTING_READ(PCH_DREF_CONTROL
);
4825 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4827 temp
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
4829 /* Turn off CPU output */
4830 temp
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
4832 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4833 POSTING_READ(PCH_DREF_CONTROL
);
4836 /* Turn off the SSC source */
4837 temp
&= ~DREF_SSC_SOURCE_MASK
;
4838 temp
|= DREF_SSC_SOURCE_DISABLE
;
4841 temp
&= ~ DREF_SSC1_ENABLE
;
4843 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4844 POSTING_READ(PCH_DREF_CONTROL
);
4849 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4850 static void lpt_init_pch_refclk(struct drm_device
*dev
)
4852 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4853 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
4854 struct intel_encoder
*encoder
;
4855 bool has_vga
= false;
4856 bool is_sdv
= false;
4859 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
) {
4860 switch (encoder
->type
) {
4861 case INTEL_OUTPUT_ANALOG
:
4870 /* XXX: Rip out SDV support once Haswell ships for real. */
4871 if (IS_HASWELL(dev
) && (dev
->pci_device
& 0xFF00) == 0x0C00)
4874 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
4875 tmp
&= ~SBI_SSCCTL_DISABLE
;
4876 tmp
|= SBI_SSCCTL_PATHALT
;
4877 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
4881 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
4882 tmp
&= ~SBI_SSCCTL_PATHALT
;
4883 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
4886 tmp
= I915_READ(SOUTH_CHICKEN2
);
4887 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
4888 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
4890 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
4891 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
4892 DRM_ERROR("FDI mPHY reset assert timeout\n");
4894 tmp
= I915_READ(SOUTH_CHICKEN2
);
4895 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
4896 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
4898 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
4899 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0,
4901 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
4904 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
4905 tmp
&= ~(0xFF << 24);
4906 tmp
|= (0x12 << 24);
4907 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
4910 tmp
= intel_sbi_read(dev_priv
, 0x808C, SBI_MPHY
);
4912 tmp
|= (1 << 6) | (1 << 0);
4913 intel_sbi_write(dev_priv
, 0x808C, tmp
, SBI_MPHY
);
4917 tmp
= intel_sbi_read(dev_priv
, 0x800C, SBI_MPHY
);
4919 intel_sbi_write(dev_priv
, 0x800C, tmp
, SBI_MPHY
);
4922 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
4924 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
4926 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
4928 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
4931 tmp
= intel_sbi_read(dev_priv
, 0x2038, SBI_MPHY
);
4932 tmp
|= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4933 intel_sbi_write(dev_priv
, 0x2038, tmp
, SBI_MPHY
);
4935 tmp
= intel_sbi_read(dev_priv
, 0x2138, SBI_MPHY
);
4936 tmp
|= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4937 intel_sbi_write(dev_priv
, 0x2138, tmp
, SBI_MPHY
);
4939 tmp
= intel_sbi_read(dev_priv
, 0x203C, SBI_MPHY
);
4941 intel_sbi_write(dev_priv
, 0x203C, tmp
, SBI_MPHY
);
4943 tmp
= intel_sbi_read(dev_priv
, 0x213C, SBI_MPHY
);
4945 intel_sbi_write(dev_priv
, 0x213C, tmp
, SBI_MPHY
);
4948 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
4949 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
4950 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
4952 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
4953 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
4954 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
4957 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
4960 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
4962 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
4965 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
4968 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
4971 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
4973 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
4976 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
4978 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
4979 tmp
&= ~(0xFF << 16);
4980 tmp
|= (0x1C << 16);
4981 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
4983 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
4984 tmp
&= ~(0xFF << 16);
4985 tmp
|= (0x1C << 16);
4986 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
4989 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
4991 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
4993 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
4995 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
4997 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
4998 tmp
&= ~(0xF << 28);
5000 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
5002 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
5003 tmp
&= ~(0xF << 28);
5005 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
5008 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5009 tmp
= intel_sbi_read(dev_priv
, SBI_DBUFF0
, SBI_ICLK
);
5010 tmp
|= SBI_DBUFF0_ENABLE
;
5011 intel_sbi_write(dev_priv
, SBI_DBUFF0
, tmp
, SBI_ICLK
);
5015 * Initialize reference clocks when the driver loads
5017 void intel_init_pch_refclk(struct drm_device
*dev
)
5019 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
5020 ironlake_init_pch_refclk(dev
);
5021 else if (HAS_PCH_LPT(dev
))
5022 lpt_init_pch_refclk(dev
);
5025 static int ironlake_get_refclk(struct drm_crtc
*crtc
)
5027 struct drm_device
*dev
= crtc
->dev
;
5028 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5029 struct intel_encoder
*encoder
;
5030 struct intel_encoder
*edp_encoder
= NULL
;
5031 int num_connectors
= 0;
5032 bool is_lvds
= false;
5034 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5035 switch (encoder
->type
) {
5036 case INTEL_OUTPUT_LVDS
:
5039 case INTEL_OUTPUT_EDP
:
5040 edp_encoder
= encoder
;
5046 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
5047 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5048 dev_priv
->lvds_ssc_freq
);
5049 return dev_priv
->lvds_ssc_freq
* 1000;
5055 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
,
5056 struct drm_display_mode
*adjusted_mode
,
5059 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
5060 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5061 int pipe
= intel_crtc
->pipe
;
5064 val
= I915_READ(PIPECONF(pipe
));
5066 val
&= ~PIPECONF_BPC_MASK
;
5067 switch (intel_crtc
->bpp
) {
5069 val
|= PIPECONF_6BPC
;
5072 val
|= PIPECONF_8BPC
;
5075 val
|= PIPECONF_10BPC
;
5078 val
|= PIPECONF_12BPC
;
5081 /* Case prevented by intel_choose_pipe_bpp_dither. */
5085 val
&= ~(PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_MASK
);
5087 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
5089 val
&= ~PIPECONF_INTERLACE_MASK
;
5090 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
5091 val
|= PIPECONF_INTERLACED_ILK
;
5093 val
|= PIPECONF_PROGRESSIVE
;
5095 I915_WRITE(PIPECONF(pipe
), val
);
5096 POSTING_READ(PIPECONF(pipe
));
5099 static void haswell_set_pipeconf(struct drm_crtc
*crtc
,
5100 struct drm_display_mode
*adjusted_mode
,
5103 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
5104 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5105 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
5108 val
= I915_READ(PIPECONF(cpu_transcoder
));
5110 val
&= ~(PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_MASK
);
5112 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
5114 val
&= ~PIPECONF_INTERLACE_MASK_HSW
;
5115 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
5116 val
|= PIPECONF_INTERLACED_ILK
;
5118 val
|= PIPECONF_PROGRESSIVE
;
5120 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
5121 POSTING_READ(PIPECONF(cpu_transcoder
));
5124 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
5125 struct drm_display_mode
*adjusted_mode
,
5126 intel_clock_t
*clock
,
5127 bool *has_reduced_clock
,
5128 intel_clock_t
*reduced_clock
)
5130 struct drm_device
*dev
= crtc
->dev
;
5131 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5132 struct intel_encoder
*intel_encoder
;
5134 const intel_limit_t
*limit
;
5135 bool ret
, is_sdvo
= false, is_tv
= false, is_lvds
= false;
5137 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5138 switch (intel_encoder
->type
) {
5139 case INTEL_OUTPUT_LVDS
:
5142 case INTEL_OUTPUT_SDVO
:
5143 case INTEL_OUTPUT_HDMI
:
5145 if (intel_encoder
->needs_tv_clock
)
5148 case INTEL_OUTPUT_TVOUT
:
5154 refclk
= ironlake_get_refclk(crtc
);
5157 * Returns a set of divisors for the desired target clock with the given
5158 * refclk, or FALSE. The returned values represent the clock equation:
5159 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5161 limit
= intel_limit(crtc
, refclk
);
5162 ret
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, NULL
,
5167 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
5169 * Ensure we match the reduced clock's P to the target clock.
5170 * If the clocks don't match, we can't switch the display clock
5171 * by using the FP0/FP1. In such case we will disable the LVDS
5172 * downclock feature.
5174 *has_reduced_clock
= limit
->find_pll(limit
, crtc
,
5175 dev_priv
->lvds_downclock
,
5181 if (is_sdvo
&& is_tv
)
5182 i9xx_adjust_sdvo_tv_clock(adjusted_mode
, clock
);
5187 static void cpt_enable_fdi_bc_bifurcation(struct drm_device
*dev
)
5189 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5192 temp
= I915_READ(SOUTH_CHICKEN1
);
5193 if (temp
& FDI_BC_BIFURCATION_SELECT
)
5196 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
5197 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
5199 temp
|= FDI_BC_BIFURCATION_SELECT
;
5200 DRM_DEBUG_KMS("enabling fdi C rx\n");
5201 I915_WRITE(SOUTH_CHICKEN1
, temp
);
5202 POSTING_READ(SOUTH_CHICKEN1
);
5205 static bool ironlake_check_fdi_lanes(struct intel_crtc
*intel_crtc
)
5207 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5208 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5209 struct intel_crtc
*pipe_B_crtc
=
5210 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
5212 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5213 intel_crtc
->pipe
, intel_crtc
->fdi_lanes
);
5214 if (intel_crtc
->fdi_lanes
> 4) {
5215 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5216 intel_crtc
->pipe
, intel_crtc
->fdi_lanes
);
5217 /* Clamp lanes to avoid programming the hw with bogus values. */
5218 intel_crtc
->fdi_lanes
= 4;
5223 if (dev_priv
->num_pipe
== 2)
5226 switch (intel_crtc
->pipe
) {
5230 if (dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]->enabled
&&
5231 intel_crtc
->fdi_lanes
> 2) {
5232 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5233 intel_crtc
->pipe
, intel_crtc
->fdi_lanes
);
5234 /* Clamp lanes to avoid programming the hw with bogus values. */
5235 intel_crtc
->fdi_lanes
= 2;
5240 if (intel_crtc
->fdi_lanes
> 2)
5241 WARN_ON(I915_READ(SOUTH_CHICKEN1
) & FDI_BC_BIFURCATION_SELECT
);
5243 cpt_enable_fdi_bc_bifurcation(dev
);
5247 if (!pipe_B_crtc
->base
.enabled
|| pipe_B_crtc
->fdi_lanes
<= 2) {
5248 if (intel_crtc
->fdi_lanes
> 2) {
5249 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5250 intel_crtc
->pipe
, intel_crtc
->fdi_lanes
);
5251 /* Clamp lanes to avoid programming the hw with bogus values. */
5252 intel_crtc
->fdi_lanes
= 2;
5257 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5261 cpt_enable_fdi_bc_bifurcation(dev
);
5269 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
5272 * Account for spread spectrum to avoid
5273 * oversubscribing the link. Max center spread
5274 * is 2.5%; use 5% for safety's sake.
5276 u32 bps
= target_clock
* bpp
* 21 / 20;
5277 return bps
/ (link_bw
* 8) + 1;
5280 static void ironlake_set_m_n(struct drm_crtc
*crtc
,
5281 struct drm_display_mode
*mode
,
5282 struct drm_display_mode
*adjusted_mode
)
5284 struct drm_device
*dev
= crtc
->dev
;
5285 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5286 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5287 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
5288 struct intel_encoder
*intel_encoder
, *edp_encoder
= NULL
;
5289 struct intel_link_m_n m_n
= {0};
5290 int target_clock
, pixel_multiplier
, lane
, link_bw
;
5291 bool is_dp
= false, is_cpu_edp
= false;
5293 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5294 switch (intel_encoder
->type
) {
5295 case INTEL_OUTPUT_DISPLAYPORT
:
5298 case INTEL_OUTPUT_EDP
:
5300 if (!intel_encoder_is_pch_edp(&intel_encoder
->base
))
5302 edp_encoder
= intel_encoder
;
5308 pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
5310 /* CPU eDP doesn't require FDI link, so just set DP M/N
5311 according to current link config */
5313 intel_edp_link_config(edp_encoder
, &lane
, &link_bw
);
5315 /* FDI is a binary signal running at ~2.7GHz, encoding
5316 * each output octet as 10 bits. The actual frequency
5317 * is stored as a divider into a 100MHz clock, and the
5318 * mode pixel clock is stored in units of 1KHz.
5319 * Hence the bw of each lane in terms of the mode signal
5322 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
5325 /* [e]DP over FDI requires target mode clock instead of link clock. */
5327 target_clock
= intel_edp_target_clock(edp_encoder
, mode
);
5329 target_clock
= mode
->clock
;
5331 target_clock
= adjusted_mode
->clock
;
5334 lane
= ironlake_get_lanes_required(target_clock
, link_bw
,
5337 intel_crtc
->fdi_lanes
= lane
;
5339 if (pixel_multiplier
> 1)
5340 link_bw
*= pixel_multiplier
;
5341 intel_link_compute_m_n(intel_crtc
->bpp
, lane
, target_clock
, link_bw
, &m_n
);
5343 I915_WRITE(PIPE_DATA_M1(cpu_transcoder
), TU_SIZE(m_n
.tu
) | m_n
.gmch_m
);
5344 I915_WRITE(PIPE_DATA_N1(cpu_transcoder
), m_n
.gmch_n
);
5345 I915_WRITE(PIPE_LINK_M1(cpu_transcoder
), m_n
.link_m
);
5346 I915_WRITE(PIPE_LINK_N1(cpu_transcoder
), m_n
.link_n
);
5349 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
5350 struct drm_display_mode
*adjusted_mode
,
5351 intel_clock_t
*clock
, u32 fp
)
5353 struct drm_crtc
*crtc
= &intel_crtc
->base
;
5354 struct drm_device
*dev
= crtc
->dev
;
5355 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5356 struct intel_encoder
*intel_encoder
;
5358 int factor
, pixel_multiplier
, num_connectors
= 0;
5359 bool is_lvds
= false, is_sdvo
= false, is_tv
= false;
5360 bool is_dp
= false, is_cpu_edp
= false;
5362 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5363 switch (intel_encoder
->type
) {
5364 case INTEL_OUTPUT_LVDS
:
5367 case INTEL_OUTPUT_SDVO
:
5368 case INTEL_OUTPUT_HDMI
:
5370 if (intel_encoder
->needs_tv_clock
)
5373 case INTEL_OUTPUT_TVOUT
:
5376 case INTEL_OUTPUT_DISPLAYPORT
:
5379 case INTEL_OUTPUT_EDP
:
5381 if (!intel_encoder_is_pch_edp(&intel_encoder
->base
))
5389 /* Enable autotuning of the PLL clock (if permissible) */
5392 if ((intel_panel_use_ssc(dev_priv
) &&
5393 dev_priv
->lvds_ssc_freq
== 100) ||
5394 intel_is_dual_link_lvds(dev
))
5396 } else if (is_sdvo
&& is_tv
)
5399 if (clock
->m
< factor
* clock
->n
)
5405 dpll
|= DPLLB_MODE_LVDS
;
5407 dpll
|= DPLLB_MODE_DAC_SERIAL
;
5409 pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
5410 if (pixel_multiplier
> 1) {
5411 dpll
|= (pixel_multiplier
- 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
5413 dpll
|= DPLL_DVO_HIGH_SPEED
;
5415 if (is_dp
&& !is_cpu_edp
)
5416 dpll
|= DPLL_DVO_HIGH_SPEED
;
5418 /* compute bitmask from p1 value */
5419 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5421 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
5423 switch (clock
->p2
) {
5425 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
5428 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
5431 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
5434 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
5438 if (is_sdvo
&& is_tv
)
5439 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
5441 /* XXX: just matching BIOS for now */
5442 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5444 else if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
5445 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
5447 dpll
|= PLL_REF_INPUT_DREFCLK
;
5452 static int ironlake_crtc_mode_set(struct drm_crtc
*crtc
,
5453 struct drm_display_mode
*mode
,
5454 struct drm_display_mode
*adjusted_mode
,
5456 struct drm_framebuffer
*fb
)
5458 struct drm_device
*dev
= crtc
->dev
;
5459 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5460 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5461 int pipe
= intel_crtc
->pipe
;
5462 int plane
= intel_crtc
->plane
;
5463 int num_connectors
= 0;
5464 intel_clock_t clock
, reduced_clock
;
5465 u32 dpll
, fp
= 0, fp2
= 0;
5466 bool ok
, has_reduced_clock
= false;
5467 bool is_lvds
= false, is_dp
= false, is_cpu_edp
= false;
5468 struct intel_encoder
*encoder
;
5470 bool dither
, fdi_config_ok
;
5472 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5473 switch (encoder
->type
) {
5474 case INTEL_OUTPUT_LVDS
:
5477 case INTEL_OUTPUT_DISPLAYPORT
:
5480 case INTEL_OUTPUT_EDP
:
5482 if (!intel_encoder_is_pch_edp(&encoder
->base
))
5490 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
5491 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
5493 ok
= ironlake_compute_clocks(crtc
, adjusted_mode
, &clock
,
5494 &has_reduced_clock
, &reduced_clock
);
5496 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5500 /* Ensure that the cursor is valid for the new mode before changing... */
5501 intel_crtc_update_cursor(crtc
, true);
5503 /* determine panel color depth */
5504 dither
= intel_choose_pipe_bpp_dither(crtc
, fb
, &intel_crtc
->bpp
,
5506 if (is_lvds
&& dev_priv
->lvds_dither
)
5509 fp
= clock
.n
<< 16 | clock
.m1
<< 8 | clock
.m2
;
5510 if (has_reduced_clock
)
5511 fp2
= reduced_clock
.n
<< 16 | reduced_clock
.m1
<< 8 |
5514 dpll
= ironlake_compute_dpll(intel_crtc
, adjusted_mode
, &clock
, fp
);
5516 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe
);
5517 drm_mode_debug_printmodeline(mode
);
5519 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5521 struct intel_pch_pll
*pll
;
5523 pll
= intel_get_pch_pll(intel_crtc
, dpll
, fp
);
5525 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5530 intel_put_pch_pll(intel_crtc
);
5532 if (is_dp
&& !is_cpu_edp
)
5533 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
5535 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5536 if (encoder
->pre_pll_enable
)
5537 encoder
->pre_pll_enable(encoder
);
5539 if (intel_crtc
->pch_pll
) {
5540 I915_WRITE(intel_crtc
->pch_pll
->pll_reg
, dpll
);
5542 /* Wait for the clocks to stabilize. */
5543 POSTING_READ(intel_crtc
->pch_pll
->pll_reg
);
5546 /* The pixel multiplier can only be updated once the
5547 * DPLL is enabled and the clocks are stable.
5549 * So write it again.
5551 I915_WRITE(intel_crtc
->pch_pll
->pll_reg
, dpll
);
5554 intel_crtc
->lowfreq_avail
= false;
5555 if (intel_crtc
->pch_pll
) {
5556 if (is_lvds
&& has_reduced_clock
&& i915_powersave
) {
5557 I915_WRITE(intel_crtc
->pch_pll
->fp1_reg
, fp2
);
5558 intel_crtc
->lowfreq_avail
= true;
5560 I915_WRITE(intel_crtc
->pch_pll
->fp1_reg
, fp
);
5564 intel_set_pipe_timings(intel_crtc
, mode
, adjusted_mode
);
5566 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5567 * ironlake_check_fdi_lanes. */
5568 ironlake_set_m_n(crtc
, mode
, adjusted_mode
);
5570 fdi_config_ok
= ironlake_check_fdi_lanes(intel_crtc
);
5572 ironlake_set_pipeconf(crtc
, adjusted_mode
, dither
);
5574 intel_wait_for_vblank(dev
, pipe
);
5576 /* Set up the display plane register */
5577 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
);
5578 POSTING_READ(DSPCNTR(plane
));
5580 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
5582 intel_update_watermarks(dev
);
5584 intel_update_linetime_watermarks(dev
, pipe
, adjusted_mode
);
5586 return fdi_config_ok
? ret
: -EINVAL
;
5589 static int haswell_crtc_mode_set(struct drm_crtc
*crtc
,
5590 struct drm_display_mode
*mode
,
5591 struct drm_display_mode
*adjusted_mode
,
5593 struct drm_framebuffer
*fb
)
5595 struct drm_device
*dev
= crtc
->dev
;
5596 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5597 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5598 int pipe
= intel_crtc
->pipe
;
5599 int plane
= intel_crtc
->plane
;
5600 int num_connectors
= 0;
5601 bool is_dp
= false, is_cpu_edp
= false;
5602 struct intel_encoder
*encoder
;
5606 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5607 switch (encoder
->type
) {
5608 case INTEL_OUTPUT_DISPLAYPORT
:
5611 case INTEL_OUTPUT_EDP
:
5613 if (!intel_encoder_is_pch_edp(&encoder
->base
))
5622 intel_crtc
->cpu_transcoder
= TRANSCODER_EDP
;
5624 intel_crtc
->cpu_transcoder
= pipe
;
5626 /* We are not sure yet this won't happen. */
5627 WARN(!HAS_PCH_LPT(dev
), "Unexpected PCH type %d\n",
5628 INTEL_PCH_TYPE(dev
));
5630 WARN(num_connectors
!= 1, "%d connectors attached to pipe %c\n",
5631 num_connectors
, pipe_name(pipe
));
5633 WARN_ON(I915_READ(PIPECONF(intel_crtc
->cpu_transcoder
)) &
5634 (PIPECONF_ENABLE
| I965_PIPECONF_ACTIVE
));
5636 WARN_ON(I915_READ(DSPCNTR(plane
)) & DISPLAY_PLANE_ENABLE
);
5638 if (!intel_ddi_pll_mode_set(crtc
, adjusted_mode
->clock
))
5641 /* Ensure that the cursor is valid for the new mode before changing... */
5642 intel_crtc_update_cursor(crtc
, true);
5644 /* determine panel color depth */
5645 dither
= intel_choose_pipe_bpp_dither(crtc
, fb
, &intel_crtc
->bpp
,
5648 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe
);
5649 drm_mode_debug_printmodeline(mode
);
5651 if (is_dp
&& !is_cpu_edp
)
5652 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
5654 intel_crtc
->lowfreq_avail
= false;
5656 intel_set_pipe_timings(intel_crtc
, mode
, adjusted_mode
);
5658 if (!is_dp
|| is_cpu_edp
)
5659 ironlake_set_m_n(crtc
, mode
, adjusted_mode
);
5661 haswell_set_pipeconf(crtc
, adjusted_mode
, dither
);
5663 /* Set up the display plane register */
5664 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
);
5665 POSTING_READ(DSPCNTR(plane
));
5667 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
5669 intel_update_watermarks(dev
);
5671 intel_update_linetime_watermarks(dev
, pipe
, adjusted_mode
);
5676 static int intel_crtc_mode_set(struct drm_crtc
*crtc
,
5677 struct drm_display_mode
*mode
,
5678 struct drm_display_mode
*adjusted_mode
,
5680 struct drm_framebuffer
*fb
)
5682 struct drm_device
*dev
= crtc
->dev
;
5683 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5684 struct drm_encoder_helper_funcs
*encoder_funcs
;
5685 struct intel_encoder
*encoder
;
5686 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5687 int pipe
= intel_crtc
->pipe
;
5690 drm_vblank_pre_modeset(dev
, pipe
);
5692 ret
= dev_priv
->display
.crtc_mode_set(crtc
, mode
, adjusted_mode
,
5694 drm_vblank_post_modeset(dev
, pipe
);
5699 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5700 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5701 encoder
->base
.base
.id
,
5702 drm_get_encoder_name(&encoder
->base
),
5703 mode
->base
.id
, mode
->name
);
5704 encoder_funcs
= encoder
->base
.helper_private
;
5705 encoder_funcs
->mode_set(&encoder
->base
, mode
, adjusted_mode
);
5711 static bool intel_eld_uptodate(struct drm_connector
*connector
,
5712 int reg_eldv
, uint32_t bits_eldv
,
5713 int reg_elda
, uint32_t bits_elda
,
5716 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
5717 uint8_t *eld
= connector
->eld
;
5720 i
= I915_READ(reg_eldv
);
5729 i
= I915_READ(reg_elda
);
5731 I915_WRITE(reg_elda
, i
);
5733 for (i
= 0; i
< eld
[2]; i
++)
5734 if (I915_READ(reg_edid
) != *((uint32_t *)eld
+ i
))
5740 static void g4x_write_eld(struct drm_connector
*connector
,
5741 struct drm_crtc
*crtc
)
5743 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
5744 uint8_t *eld
= connector
->eld
;
5749 i
= I915_READ(G4X_AUD_VID_DID
);
5751 if (i
== INTEL_AUDIO_DEVBLC
|| i
== INTEL_AUDIO_DEVCL
)
5752 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
5754 eldv
= G4X_ELDV_DEVCTG
;
5756 if (intel_eld_uptodate(connector
,
5757 G4X_AUD_CNTL_ST
, eldv
,
5758 G4X_AUD_CNTL_ST
, G4X_ELD_ADDR
,
5759 G4X_HDMIW_HDMIEDID
))
5762 i
= I915_READ(G4X_AUD_CNTL_ST
);
5763 i
&= ~(eldv
| G4X_ELD_ADDR
);
5764 len
= (i
>> 9) & 0x1f; /* ELD buffer size */
5765 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
5770 len
= min_t(uint8_t, eld
[2], len
);
5771 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
5772 for (i
= 0; i
< len
; i
++)
5773 I915_WRITE(G4X_HDMIW_HDMIEDID
, *((uint32_t *)eld
+ i
));
5775 i
= I915_READ(G4X_AUD_CNTL_ST
);
5777 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
5780 static void haswell_write_eld(struct drm_connector
*connector
,
5781 struct drm_crtc
*crtc
)
5783 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
5784 uint8_t *eld
= connector
->eld
;
5785 struct drm_device
*dev
= crtc
->dev
;
5789 int pipe
= to_intel_crtc(crtc
)->pipe
;
5792 int hdmiw_hdmiedid
= HSW_AUD_EDID_DATA(pipe
);
5793 int aud_cntl_st
= HSW_AUD_DIP_ELD_CTRL(pipe
);
5794 int aud_config
= HSW_AUD_CFG(pipe
);
5795 int aud_cntrl_st2
= HSW_AUD_PIN_ELD_CP_VLD
;
5798 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5800 /* Audio output enable */
5801 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5802 tmp
= I915_READ(aud_cntrl_st2
);
5803 tmp
|= (AUDIO_OUTPUT_ENABLE_A
<< (pipe
* 4));
5804 I915_WRITE(aud_cntrl_st2
, tmp
);
5806 /* Wait for 1 vertical blank */
5807 intel_wait_for_vblank(dev
, pipe
);
5809 /* Set ELD valid state */
5810 tmp
= I915_READ(aud_cntrl_st2
);
5811 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp
);
5812 tmp
|= (AUDIO_ELD_VALID_A
<< (pipe
* 4));
5813 I915_WRITE(aud_cntrl_st2
, tmp
);
5814 tmp
= I915_READ(aud_cntrl_st2
);
5815 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp
);
5817 /* Enable HDMI mode */
5818 tmp
= I915_READ(aud_config
);
5819 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp
);
5820 /* clear N_programing_enable and N_value_index */
5821 tmp
&= ~(AUD_CONFIG_N_VALUE_INDEX
| AUD_CONFIG_N_PROG_ENABLE
);
5822 I915_WRITE(aud_config
, tmp
);
5824 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
5826 eldv
= AUDIO_ELD_VALID_A
<< (pipe
* 4);
5828 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
5829 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5830 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5831 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
5833 I915_WRITE(aud_config
, 0);
5835 if (intel_eld_uptodate(connector
,
5836 aud_cntrl_st2
, eldv
,
5837 aud_cntl_st
, IBX_ELD_ADDRESS
,
5841 i
= I915_READ(aud_cntrl_st2
);
5843 I915_WRITE(aud_cntrl_st2
, i
);
5848 i
= I915_READ(aud_cntl_st
);
5849 i
&= ~IBX_ELD_ADDRESS
;
5850 I915_WRITE(aud_cntl_st
, i
);
5851 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
5852 DRM_DEBUG_DRIVER("port num:%d\n", i
);
5854 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
5855 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
5856 for (i
= 0; i
< len
; i
++)
5857 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
5859 i
= I915_READ(aud_cntrl_st2
);
5861 I915_WRITE(aud_cntrl_st2
, i
);
5865 static void ironlake_write_eld(struct drm_connector
*connector
,
5866 struct drm_crtc
*crtc
)
5868 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
5869 uint8_t *eld
= connector
->eld
;
5877 int pipe
= to_intel_crtc(crtc
)->pipe
;
5879 if (HAS_PCH_IBX(connector
->dev
)) {
5880 hdmiw_hdmiedid
= IBX_HDMIW_HDMIEDID(pipe
);
5881 aud_config
= IBX_AUD_CFG(pipe
);
5882 aud_cntl_st
= IBX_AUD_CNTL_ST(pipe
);
5883 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
5885 hdmiw_hdmiedid
= CPT_HDMIW_HDMIEDID(pipe
);
5886 aud_config
= CPT_AUD_CFG(pipe
);
5887 aud_cntl_st
= CPT_AUD_CNTL_ST(pipe
);
5888 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
5891 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
5893 i
= I915_READ(aud_cntl_st
);
5894 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
5896 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5897 /* operate blindly on all ports */
5898 eldv
= IBX_ELD_VALIDB
;
5899 eldv
|= IBX_ELD_VALIDB
<< 4;
5900 eldv
|= IBX_ELD_VALIDB
<< 8;
5902 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i
);
5903 eldv
= IBX_ELD_VALIDB
<< ((i
- 1) * 4);
5906 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
5907 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5908 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5909 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
5911 I915_WRITE(aud_config
, 0);
5913 if (intel_eld_uptodate(connector
,
5914 aud_cntrl_st2
, eldv
,
5915 aud_cntl_st
, IBX_ELD_ADDRESS
,
5919 i
= I915_READ(aud_cntrl_st2
);
5921 I915_WRITE(aud_cntrl_st2
, i
);
5926 i
= I915_READ(aud_cntl_st
);
5927 i
&= ~IBX_ELD_ADDRESS
;
5928 I915_WRITE(aud_cntl_st
, i
);
5930 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
5931 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
5932 for (i
= 0; i
< len
; i
++)
5933 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
5935 i
= I915_READ(aud_cntrl_st2
);
5937 I915_WRITE(aud_cntrl_st2
, i
);
5940 void intel_write_eld(struct drm_encoder
*encoder
,
5941 struct drm_display_mode
*mode
)
5943 struct drm_crtc
*crtc
= encoder
->crtc
;
5944 struct drm_connector
*connector
;
5945 struct drm_device
*dev
= encoder
->dev
;
5946 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5948 connector
= drm_select_eld(encoder
, mode
);
5952 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5954 drm_get_connector_name(connector
),
5955 connector
->encoder
->base
.id
,
5956 drm_get_encoder_name(connector
->encoder
));
5958 connector
->eld
[6] = drm_av_sync_delay(connector
, mode
) / 2;
5960 if (dev_priv
->display
.write_eld
)
5961 dev_priv
->display
.write_eld(connector
, crtc
);
5964 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5965 void intel_crtc_load_lut(struct drm_crtc
*crtc
)
5967 struct drm_device
*dev
= crtc
->dev
;
5968 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5969 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5970 int palreg
= PALETTE(intel_crtc
->pipe
);
5973 /* The clocks have to be on to load the palette. */
5974 if (!crtc
->enabled
|| !intel_crtc
->active
)
5977 /* use legacy palette for Ironlake */
5978 if (HAS_PCH_SPLIT(dev
))
5979 palreg
= LGC_PALETTE(intel_crtc
->pipe
);
5981 for (i
= 0; i
< 256; i
++) {
5982 I915_WRITE(palreg
+ 4 * i
,
5983 (intel_crtc
->lut_r
[i
] << 16) |
5984 (intel_crtc
->lut_g
[i
] << 8) |
5985 intel_crtc
->lut_b
[i
]);
5989 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
5991 struct drm_device
*dev
= crtc
->dev
;
5992 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5993 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5994 bool visible
= base
!= 0;
5997 if (intel_crtc
->cursor_visible
== visible
)
6000 cntl
= I915_READ(_CURACNTR
);
6002 /* On these chipsets we can only modify the base whilst
6003 * the cursor is disabled.
6005 I915_WRITE(_CURABASE
, base
);
6007 cntl
&= ~(CURSOR_FORMAT_MASK
);
6008 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6009 cntl
|= CURSOR_ENABLE
|
6010 CURSOR_GAMMA_ENABLE
|
6013 cntl
&= ~(CURSOR_ENABLE
| CURSOR_GAMMA_ENABLE
);
6014 I915_WRITE(_CURACNTR
, cntl
);
6016 intel_crtc
->cursor_visible
= visible
;
6019 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6021 struct drm_device
*dev
= crtc
->dev
;
6022 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6023 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6024 int pipe
= intel_crtc
->pipe
;
6025 bool visible
= base
!= 0;
6027 if (intel_crtc
->cursor_visible
!= visible
) {
6028 uint32_t cntl
= I915_READ(CURCNTR(pipe
));
6030 cntl
&= ~(CURSOR_MODE
| MCURSOR_PIPE_SELECT
);
6031 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
6032 cntl
|= pipe
<< 28; /* Connect to correct pipe */
6034 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
6035 cntl
|= CURSOR_MODE_DISABLE
;
6037 I915_WRITE(CURCNTR(pipe
), cntl
);
6039 intel_crtc
->cursor_visible
= visible
;
6041 /* and commit changes on next vblank */
6042 I915_WRITE(CURBASE(pipe
), base
);
6045 static void ivb_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6047 struct drm_device
*dev
= crtc
->dev
;
6048 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6049 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6050 int pipe
= intel_crtc
->pipe
;
6051 bool visible
= base
!= 0;
6053 if (intel_crtc
->cursor_visible
!= visible
) {
6054 uint32_t cntl
= I915_READ(CURCNTR_IVB(pipe
));
6056 cntl
&= ~CURSOR_MODE
;
6057 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
6059 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
6060 cntl
|= CURSOR_MODE_DISABLE
;
6062 I915_WRITE(CURCNTR_IVB(pipe
), cntl
);
6064 intel_crtc
->cursor_visible
= visible
;
6066 /* and commit changes on next vblank */
6067 I915_WRITE(CURBASE_IVB(pipe
), base
);
6070 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6071 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
6074 struct drm_device
*dev
= crtc
->dev
;
6075 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6076 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6077 int pipe
= intel_crtc
->pipe
;
6078 int x
= intel_crtc
->cursor_x
;
6079 int y
= intel_crtc
->cursor_y
;
6085 if (on
&& crtc
->enabled
&& crtc
->fb
) {
6086 base
= intel_crtc
->cursor_addr
;
6087 if (x
> (int) crtc
->fb
->width
)
6090 if (y
> (int) crtc
->fb
->height
)
6096 if (x
+ intel_crtc
->cursor_width
< 0)
6099 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
6102 pos
|= x
<< CURSOR_X_SHIFT
;
6105 if (y
+ intel_crtc
->cursor_height
< 0)
6108 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
6111 pos
|= y
<< CURSOR_Y_SHIFT
;
6113 visible
= base
!= 0;
6114 if (!visible
&& !intel_crtc
->cursor_visible
)
6117 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
6118 I915_WRITE(CURPOS_IVB(pipe
), pos
);
6119 ivb_update_cursor(crtc
, base
);
6121 I915_WRITE(CURPOS(pipe
), pos
);
6122 if (IS_845G(dev
) || IS_I865G(dev
))
6123 i845_update_cursor(crtc
, base
);
6125 i9xx_update_cursor(crtc
, base
);
6129 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
6130 struct drm_file
*file
,
6132 uint32_t width
, uint32_t height
)
6134 struct drm_device
*dev
= crtc
->dev
;
6135 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6136 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6137 struct drm_i915_gem_object
*obj
;
6141 /* if we want to turn off the cursor ignore width and height */
6143 DRM_DEBUG_KMS("cursor off\n");
6146 mutex_lock(&dev
->struct_mutex
);
6150 /* Currently we only support 64x64 cursors */
6151 if (width
!= 64 || height
!= 64) {
6152 DRM_ERROR("we currently only support 64x64 cursors\n");
6156 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
6157 if (&obj
->base
== NULL
)
6160 if (obj
->base
.size
< width
* height
* 4) {
6161 DRM_ERROR("buffer is to small\n");
6166 /* we only need to pin inside GTT if cursor is non-phy */
6167 mutex_lock(&dev
->struct_mutex
);
6168 if (!dev_priv
->info
->cursor_needs_physical
) {
6169 if (obj
->tiling_mode
) {
6170 DRM_ERROR("cursor cannot be tiled\n");
6175 ret
= i915_gem_object_pin_to_display_plane(obj
, 0, NULL
);
6177 DRM_ERROR("failed to move cursor bo into the GTT\n");
6181 ret
= i915_gem_object_put_fence(obj
);
6183 DRM_ERROR("failed to release fence for cursor");
6187 addr
= obj
->gtt_offset
;
6189 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
6190 ret
= i915_gem_attach_phys_object(dev
, obj
,
6191 (intel_crtc
->pipe
== 0) ? I915_GEM_PHYS_CURSOR_0
: I915_GEM_PHYS_CURSOR_1
,
6194 DRM_ERROR("failed to attach phys object\n");
6197 addr
= obj
->phys_obj
->handle
->busaddr
;
6201 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
6204 if (intel_crtc
->cursor_bo
) {
6205 if (dev_priv
->info
->cursor_needs_physical
) {
6206 if (intel_crtc
->cursor_bo
!= obj
)
6207 i915_gem_detach_phys_object(dev
, intel_crtc
->cursor_bo
);
6209 i915_gem_object_unpin(intel_crtc
->cursor_bo
);
6210 drm_gem_object_unreference(&intel_crtc
->cursor_bo
->base
);
6213 mutex_unlock(&dev
->struct_mutex
);
6215 intel_crtc
->cursor_addr
= addr
;
6216 intel_crtc
->cursor_bo
= obj
;
6217 intel_crtc
->cursor_width
= width
;
6218 intel_crtc
->cursor_height
= height
;
6220 intel_crtc_update_cursor(crtc
, true);
6224 i915_gem_object_unpin(obj
);
6226 mutex_unlock(&dev
->struct_mutex
);
6228 drm_gem_object_unreference_unlocked(&obj
->base
);
6232 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
6234 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6236 intel_crtc
->cursor_x
= x
;
6237 intel_crtc
->cursor_y
= y
;
6239 intel_crtc_update_cursor(crtc
, true);
6244 /** Sets the color ramps on behalf of RandR */
6245 void intel_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
6246 u16 blue
, int regno
)
6248 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6250 intel_crtc
->lut_r
[regno
] = red
>> 8;
6251 intel_crtc
->lut_g
[regno
] = green
>> 8;
6252 intel_crtc
->lut_b
[regno
] = blue
>> 8;
6255 void intel_crtc_fb_gamma_get(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
6256 u16
*blue
, int regno
)
6258 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6260 *red
= intel_crtc
->lut_r
[regno
] << 8;
6261 *green
= intel_crtc
->lut_g
[regno
] << 8;
6262 *blue
= intel_crtc
->lut_b
[regno
] << 8;
6265 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
6266 u16
*blue
, uint32_t start
, uint32_t size
)
6268 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
6269 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6271 for (i
= start
; i
< end
; i
++) {
6272 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
6273 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
6274 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
6277 intel_crtc_load_lut(crtc
);
6281 * Get a pipe with a simple mode set on it for doing load-based monitor
6284 * It will be up to the load-detect code to adjust the pipe as appropriate for
6285 * its requirements. The pipe will be connected to no other encoders.
6287 * Currently this code will only succeed if there is a pipe with no encoders
6288 * configured for it. In the future, it could choose to temporarily disable
6289 * some outputs to free up a pipe for its use.
6291 * \return crtc, or NULL if no pipes are available.
6294 /* VESA 640x480x72Hz mode to set on the pipe */
6295 static struct drm_display_mode load_detect_mode
= {
6296 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
6297 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
6300 static struct drm_framebuffer
*
6301 intel_framebuffer_create(struct drm_device
*dev
,
6302 struct drm_mode_fb_cmd2
*mode_cmd
,
6303 struct drm_i915_gem_object
*obj
)
6305 struct intel_framebuffer
*intel_fb
;
6308 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
6310 drm_gem_object_unreference_unlocked(&obj
->base
);
6311 return ERR_PTR(-ENOMEM
);
6314 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
6316 drm_gem_object_unreference_unlocked(&obj
->base
);
6318 return ERR_PTR(ret
);
6321 return &intel_fb
->base
;
6325 intel_framebuffer_pitch_for_width(int width
, int bpp
)
6327 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
6328 return ALIGN(pitch
, 64);
6332 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
6334 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
6335 return ALIGN(pitch
* mode
->vdisplay
, PAGE_SIZE
);
6338 static struct drm_framebuffer
*
6339 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
6340 struct drm_display_mode
*mode
,
6343 struct drm_i915_gem_object
*obj
;
6344 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
6346 obj
= i915_gem_alloc_object(dev
,
6347 intel_framebuffer_size_for_mode(mode
, bpp
));
6349 return ERR_PTR(-ENOMEM
);
6351 mode_cmd
.width
= mode
->hdisplay
;
6352 mode_cmd
.height
= mode
->vdisplay
;
6353 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
6355 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
6357 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
6360 static struct drm_framebuffer
*
6361 mode_fits_in_fbdev(struct drm_device
*dev
,
6362 struct drm_display_mode
*mode
)
6364 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6365 struct drm_i915_gem_object
*obj
;
6366 struct drm_framebuffer
*fb
;
6368 if (dev_priv
->fbdev
== NULL
)
6371 obj
= dev_priv
->fbdev
->ifb
.obj
;
6375 fb
= &dev_priv
->fbdev
->ifb
.base
;
6376 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
6377 fb
->bits_per_pixel
))
6380 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
6386 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
6387 struct drm_display_mode
*mode
,
6388 struct intel_load_detect_pipe
*old
)
6390 struct intel_crtc
*intel_crtc
;
6391 struct intel_encoder
*intel_encoder
=
6392 intel_attached_encoder(connector
);
6393 struct drm_crtc
*possible_crtc
;
6394 struct drm_encoder
*encoder
= &intel_encoder
->base
;
6395 struct drm_crtc
*crtc
= NULL
;
6396 struct drm_device
*dev
= encoder
->dev
;
6397 struct drm_framebuffer
*fb
;
6400 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6401 connector
->base
.id
, drm_get_connector_name(connector
),
6402 encoder
->base
.id
, drm_get_encoder_name(encoder
));
6405 * Algorithm gets a little messy:
6407 * - if the connector already has an assigned crtc, use it (but make
6408 * sure it's on first)
6410 * - try to find the first unused crtc that can drive this connector,
6411 * and use that if we find one
6414 /* See if we already have a CRTC for this connector */
6415 if (encoder
->crtc
) {
6416 crtc
= encoder
->crtc
;
6418 old
->dpms_mode
= connector
->dpms
;
6419 old
->load_detect_temp
= false;
6421 /* Make sure the crtc and connector are running */
6422 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
6423 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
6428 /* Find an unused one (if possible) */
6429 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
6431 if (!(encoder
->possible_crtcs
& (1 << i
)))
6433 if (!possible_crtc
->enabled
) {
6434 crtc
= possible_crtc
;
6440 * If we didn't find an unused CRTC, don't use any.
6443 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6447 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
6448 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
6450 intel_crtc
= to_intel_crtc(crtc
);
6451 old
->dpms_mode
= connector
->dpms
;
6452 old
->load_detect_temp
= true;
6453 old
->release_fb
= NULL
;
6456 mode
= &load_detect_mode
;
6458 /* We need a framebuffer large enough to accommodate all accesses
6459 * that the plane may generate whilst we perform load detection.
6460 * We can not rely on the fbcon either being present (we get called
6461 * during its initialisation to detect all boot displays, or it may
6462 * not even exist) or that it is large enough to satisfy the
6465 fb
= mode_fits_in_fbdev(dev
, mode
);
6467 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6468 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
6469 old
->release_fb
= fb
;
6471 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6473 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6477 if (intel_set_mode(crtc
, mode
, 0, 0, fb
)) {
6478 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6479 if (old
->release_fb
)
6480 old
->release_fb
->funcs
->destroy(old
->release_fb
);
6484 /* let the connector get through one full cycle before testing */
6485 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
6489 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
6490 struct intel_load_detect_pipe
*old
)
6492 struct intel_encoder
*intel_encoder
=
6493 intel_attached_encoder(connector
);
6494 struct drm_encoder
*encoder
= &intel_encoder
->base
;
6496 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6497 connector
->base
.id
, drm_get_connector_name(connector
),
6498 encoder
->base
.id
, drm_get_encoder_name(encoder
));
6500 if (old
->load_detect_temp
) {
6501 struct drm_crtc
*crtc
= encoder
->crtc
;
6503 to_intel_connector(connector
)->new_encoder
= NULL
;
6504 intel_encoder
->new_crtc
= NULL
;
6505 intel_set_mode(crtc
, NULL
, 0, 0, NULL
);
6507 if (old
->release_fb
)
6508 old
->release_fb
->funcs
->destroy(old
->release_fb
);
6513 /* Switch crtc and encoder back off if necessary */
6514 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
6515 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
6518 /* Returns the clock of the currently programmed mode of the given pipe. */
6519 static int intel_crtc_clock_get(struct drm_device
*dev
, struct drm_crtc
*crtc
)
6521 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6522 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6523 int pipe
= intel_crtc
->pipe
;
6524 u32 dpll
= I915_READ(DPLL(pipe
));
6526 intel_clock_t clock
;
6528 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
6529 fp
= I915_READ(FP0(pipe
));
6531 fp
= I915_READ(FP1(pipe
));
6533 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
6534 if (IS_PINEVIEW(dev
)) {
6535 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
6536 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
6538 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
6539 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
6542 if (!IS_GEN2(dev
)) {
6543 if (IS_PINEVIEW(dev
))
6544 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
6545 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
6547 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
6548 DPLL_FPA01_P1_POST_DIV_SHIFT
);
6550 switch (dpll
& DPLL_MODE_MASK
) {
6551 case DPLLB_MODE_DAC_SERIAL
:
6552 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
6555 case DPLLB_MODE_LVDS
:
6556 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
6560 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6561 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
6565 /* XXX: Handle the 100Mhz refclk */
6566 intel_clock(dev
, 96000, &clock
);
6568 bool is_lvds
= (pipe
== 1) && (I915_READ(LVDS
) & LVDS_PORT_EN
);
6571 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
6572 DPLL_FPA01_P1_POST_DIV_SHIFT
);
6575 if ((dpll
& PLL_REF_INPUT_MASK
) ==
6576 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
6577 /* XXX: might not be 66MHz */
6578 intel_clock(dev
, 66000, &clock
);
6580 intel_clock(dev
, 48000, &clock
);
6582 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
6585 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
6586 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
6588 if (dpll
& PLL_P2_DIVIDE_BY_4
)
6593 intel_clock(dev
, 48000, &clock
);
6597 /* XXX: It would be nice to validate the clocks, but we can't reuse
6598 * i830PllIsValid() because it relies on the xf86_config connector
6599 * configuration being accurate, which it isn't necessarily.
6605 /** Returns the currently programmed mode of the given pipe. */
6606 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
6607 struct drm_crtc
*crtc
)
6609 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6610 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6611 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
6612 struct drm_display_mode
*mode
;
6613 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
6614 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
6615 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
6616 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
6618 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
6622 mode
->clock
= intel_crtc_clock_get(dev
, crtc
);
6623 mode
->hdisplay
= (htot
& 0xffff) + 1;
6624 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
6625 mode
->hsync_start
= (hsync
& 0xffff) + 1;
6626 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
6627 mode
->vdisplay
= (vtot
& 0xffff) + 1;
6628 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
6629 mode
->vsync_start
= (vsync
& 0xffff) + 1;
6630 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
6632 drm_mode_set_name(mode
);
6637 static void intel_increase_pllclock(struct drm_crtc
*crtc
)
6639 struct drm_device
*dev
= crtc
->dev
;
6640 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6641 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6642 int pipe
= intel_crtc
->pipe
;
6643 int dpll_reg
= DPLL(pipe
);
6646 if (HAS_PCH_SPLIT(dev
))
6649 if (!dev_priv
->lvds_downclock_avail
)
6652 dpll
= I915_READ(dpll_reg
);
6653 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
6654 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6656 assert_panel_unlocked(dev_priv
, pipe
);
6658 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
6659 I915_WRITE(dpll_reg
, dpll
);
6660 intel_wait_for_vblank(dev
, pipe
);
6662 dpll
= I915_READ(dpll_reg
);
6663 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
6664 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6668 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
6670 struct drm_device
*dev
= crtc
->dev
;
6671 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6672 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6674 if (HAS_PCH_SPLIT(dev
))
6677 if (!dev_priv
->lvds_downclock_avail
)
6681 * Since this is called by a timer, we should never get here in
6684 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
6685 int pipe
= intel_crtc
->pipe
;
6686 int dpll_reg
= DPLL(pipe
);
6689 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6691 assert_panel_unlocked(dev_priv
, pipe
);
6693 dpll
= I915_READ(dpll_reg
);
6694 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
6695 I915_WRITE(dpll_reg
, dpll
);
6696 intel_wait_for_vblank(dev
, pipe
);
6697 dpll
= I915_READ(dpll_reg
);
6698 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
6699 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6704 void intel_mark_busy(struct drm_device
*dev
)
6706 i915_update_gfx_val(dev
->dev_private
);
6709 void intel_mark_idle(struct drm_device
*dev
)
6713 void intel_mark_fb_busy(struct drm_i915_gem_object
*obj
)
6715 struct drm_device
*dev
= obj
->base
.dev
;
6716 struct drm_crtc
*crtc
;
6718 if (!i915_powersave
)
6721 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
6725 if (to_intel_framebuffer(crtc
->fb
)->obj
== obj
)
6726 intel_increase_pllclock(crtc
);
6730 void intel_mark_fb_idle(struct drm_i915_gem_object
*obj
)
6732 struct drm_device
*dev
= obj
->base
.dev
;
6733 struct drm_crtc
*crtc
;
6735 if (!i915_powersave
)
6738 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
6742 if (to_intel_framebuffer(crtc
->fb
)->obj
== obj
)
6743 intel_decrease_pllclock(crtc
);
6747 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
6749 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6750 struct drm_device
*dev
= crtc
->dev
;
6751 struct intel_unpin_work
*work
;
6752 unsigned long flags
;
6754 spin_lock_irqsave(&dev
->event_lock
, flags
);
6755 work
= intel_crtc
->unpin_work
;
6756 intel_crtc
->unpin_work
= NULL
;
6757 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6760 cancel_work_sync(&work
->work
);
6764 drm_crtc_cleanup(crtc
);
6769 static void intel_unpin_work_fn(struct work_struct
*__work
)
6771 struct intel_unpin_work
*work
=
6772 container_of(__work
, struct intel_unpin_work
, work
);
6773 struct drm_device
*dev
= work
->crtc
->dev
;
6775 mutex_lock(&dev
->struct_mutex
);
6776 intel_unpin_fb_obj(work
->old_fb_obj
);
6777 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
6778 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
6780 intel_update_fbc(dev
);
6781 mutex_unlock(&dev
->struct_mutex
);
6783 BUG_ON(atomic_read(&to_intel_crtc(work
->crtc
)->unpin_work_count
) == 0);
6784 atomic_dec(&to_intel_crtc(work
->crtc
)->unpin_work_count
);
6789 static void do_intel_finish_page_flip(struct drm_device
*dev
,
6790 struct drm_crtc
*crtc
)
6792 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6793 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6794 struct intel_unpin_work
*work
;
6795 struct drm_i915_gem_object
*obj
;
6796 unsigned long flags
;
6798 /* Ignore early vblank irqs */
6799 if (intel_crtc
== NULL
)
6802 spin_lock_irqsave(&dev
->event_lock
, flags
);
6803 work
= intel_crtc
->unpin_work
;
6805 /* Ensure we don't miss a work->pending update ... */
6808 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
6809 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6813 /* and that the unpin work is consistent wrt ->pending. */
6816 intel_crtc
->unpin_work
= NULL
;
6819 drm_send_vblank_event(dev
, intel_crtc
->pipe
, work
->event
);
6821 drm_vblank_put(dev
, intel_crtc
->pipe
);
6823 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6825 obj
= work
->old_fb_obj
;
6827 wake_up(&dev_priv
->pending_flip_queue
);
6829 queue_work(dev_priv
->wq
, &work
->work
);
6831 trace_i915_flip_complete(intel_crtc
->plane
, work
->pending_flip_obj
);
6834 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
6836 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6837 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
6839 do_intel_finish_page_flip(dev
, crtc
);
6842 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
6844 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6845 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
6847 do_intel_finish_page_flip(dev
, crtc
);
6850 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
6852 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6853 struct intel_crtc
*intel_crtc
=
6854 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
6855 unsigned long flags
;
6857 /* NB: An MMIO update of the plane base pointer will also
6858 * generate a page-flip completion irq, i.e. every modeset
6859 * is also accompanied by a spurious intel_prepare_page_flip().
6861 spin_lock_irqsave(&dev
->event_lock
, flags
);
6862 if (intel_crtc
->unpin_work
)
6863 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
6864 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6867 inline static void intel_mark_page_flip_active(struct intel_crtc
*intel_crtc
)
6869 /* Ensure that the work item is consistent when activating it ... */
6871 atomic_set(&intel_crtc
->unpin_work
->pending
, INTEL_FLIP_PENDING
);
6872 /* and that it is marked active as soon as the irq could fire. */
6876 static int intel_gen2_queue_flip(struct drm_device
*dev
,
6877 struct drm_crtc
*crtc
,
6878 struct drm_framebuffer
*fb
,
6879 struct drm_i915_gem_object
*obj
)
6881 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6882 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6884 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
6887 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
6891 ret
= intel_ring_begin(ring
, 6);
6895 /* Can't queue multiple flips, so wait for the previous
6896 * one to finish before executing the next.
6898 if (intel_crtc
->plane
)
6899 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
6901 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
6902 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
6903 intel_ring_emit(ring
, MI_NOOP
);
6904 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
6905 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
6906 intel_ring_emit(ring
, fb
->pitches
[0]);
6907 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
6908 intel_ring_emit(ring
, 0); /* aux display base address, unused */
6910 intel_mark_page_flip_active(intel_crtc
);
6911 intel_ring_advance(ring
);
6915 intel_unpin_fb_obj(obj
);
6920 static int intel_gen3_queue_flip(struct drm_device
*dev
,
6921 struct drm_crtc
*crtc
,
6922 struct drm_framebuffer
*fb
,
6923 struct drm_i915_gem_object
*obj
)
6925 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6926 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6928 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
6931 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
6935 ret
= intel_ring_begin(ring
, 6);
6939 if (intel_crtc
->plane
)
6940 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
6942 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
6943 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
6944 intel_ring_emit(ring
, MI_NOOP
);
6945 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
6946 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
6947 intel_ring_emit(ring
, fb
->pitches
[0]);
6948 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
6949 intel_ring_emit(ring
, MI_NOOP
);
6951 intel_mark_page_flip_active(intel_crtc
);
6952 intel_ring_advance(ring
);
6956 intel_unpin_fb_obj(obj
);
6961 static int intel_gen4_queue_flip(struct drm_device
*dev
,
6962 struct drm_crtc
*crtc
,
6963 struct drm_framebuffer
*fb
,
6964 struct drm_i915_gem_object
*obj
)
6966 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6967 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6968 uint32_t pf
, pipesrc
;
6969 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
6972 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
6976 ret
= intel_ring_begin(ring
, 4);
6980 /* i965+ uses the linear or tiled offsets from the
6981 * Display Registers (which do not change across a page-flip)
6982 * so we need only reprogram the base address.
6984 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
6985 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
6986 intel_ring_emit(ring
, fb
->pitches
[0]);
6987 intel_ring_emit(ring
,
6988 (obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
) |
6991 /* XXX Enabling the panel-fitter across page-flip is so far
6992 * untested on non-native modes, so ignore it for now.
6993 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6996 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
6997 intel_ring_emit(ring
, pf
| pipesrc
);
6999 intel_mark_page_flip_active(intel_crtc
);
7000 intel_ring_advance(ring
);
7004 intel_unpin_fb_obj(obj
);
7009 static int intel_gen6_queue_flip(struct drm_device
*dev
,
7010 struct drm_crtc
*crtc
,
7011 struct drm_framebuffer
*fb
,
7012 struct drm_i915_gem_object
*obj
)
7014 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7015 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7016 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7017 uint32_t pf
, pipesrc
;
7020 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7024 ret
= intel_ring_begin(ring
, 4);
7028 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7029 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7030 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
7031 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
7033 /* Contrary to the suggestions in the documentation,
7034 * "Enable Panel Fitter" does not seem to be required when page
7035 * flipping with a non-native mode, and worse causes a normal
7037 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7040 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
7041 intel_ring_emit(ring
, pf
| pipesrc
);
7043 intel_mark_page_flip_active(intel_crtc
);
7044 intel_ring_advance(ring
);
7048 intel_unpin_fb_obj(obj
);
7054 * On gen7 we currently use the blit ring because (in early silicon at least)
7055 * the render ring doesn't give us interrpts for page flip completion, which
7056 * means clients will hang after the first flip is queued. Fortunately the
7057 * blit ring generates interrupts properly, so use it instead.
7059 static int intel_gen7_queue_flip(struct drm_device
*dev
,
7060 struct drm_crtc
*crtc
,
7061 struct drm_framebuffer
*fb
,
7062 struct drm_i915_gem_object
*obj
)
7064 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7065 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7066 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[BCS
];
7067 uint32_t plane_bit
= 0;
7070 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7074 switch(intel_crtc
->plane
) {
7076 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
7079 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
7082 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
7085 WARN_ONCE(1, "unknown plane in flip command\n");
7090 ret
= intel_ring_begin(ring
, 4);
7094 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
7095 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
7096 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
7097 intel_ring_emit(ring
, (MI_NOOP
));
7099 intel_mark_page_flip_active(intel_crtc
);
7100 intel_ring_advance(ring
);
7104 intel_unpin_fb_obj(obj
);
7109 static int intel_default_queue_flip(struct drm_device
*dev
,
7110 struct drm_crtc
*crtc
,
7111 struct drm_framebuffer
*fb
,
7112 struct drm_i915_gem_object
*obj
)
7117 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
7118 struct drm_framebuffer
*fb
,
7119 struct drm_pending_vblank_event
*event
)
7121 struct drm_device
*dev
= crtc
->dev
;
7122 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7123 struct intel_framebuffer
*intel_fb
;
7124 struct drm_i915_gem_object
*obj
;
7125 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7126 struct intel_unpin_work
*work
;
7127 unsigned long flags
;
7130 /* Can't change pixel format via MI display flips. */
7131 if (fb
->pixel_format
!= crtc
->fb
->pixel_format
)
7135 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7136 * Note that pitch changes could also affect these register.
7138 if (INTEL_INFO(dev
)->gen
> 3 &&
7139 (fb
->offsets
[0] != crtc
->fb
->offsets
[0] ||
7140 fb
->pitches
[0] != crtc
->fb
->pitches
[0]))
7143 work
= kzalloc(sizeof *work
, GFP_KERNEL
);
7147 work
->event
= event
;
7149 intel_fb
= to_intel_framebuffer(crtc
->fb
);
7150 work
->old_fb_obj
= intel_fb
->obj
;
7151 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
7153 ret
= drm_vblank_get(dev
, intel_crtc
->pipe
);
7157 /* We borrow the event spin lock for protecting unpin_work */
7158 spin_lock_irqsave(&dev
->event_lock
, flags
);
7159 if (intel_crtc
->unpin_work
) {
7160 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7162 drm_vblank_put(dev
, intel_crtc
->pipe
);
7164 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7167 intel_crtc
->unpin_work
= work
;
7168 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7170 intel_fb
= to_intel_framebuffer(fb
);
7171 obj
= intel_fb
->obj
;
7173 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
7174 flush_workqueue(dev_priv
->wq
);
7176 ret
= i915_mutex_lock_interruptible(dev
);
7180 /* Reference the objects for the scheduled work. */
7181 drm_gem_object_reference(&work
->old_fb_obj
->base
);
7182 drm_gem_object_reference(&obj
->base
);
7186 work
->pending_flip_obj
= obj
;
7188 work
->enable_stall_check
= true;
7190 atomic_inc(&intel_crtc
->unpin_work_count
);
7192 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
);
7194 goto cleanup_pending
;
7196 intel_disable_fbc(dev
);
7197 intel_mark_fb_busy(obj
);
7198 mutex_unlock(&dev
->struct_mutex
);
7200 trace_i915_flip_request(intel_crtc
->plane
, obj
);
7205 atomic_dec(&intel_crtc
->unpin_work_count
);
7206 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
7207 drm_gem_object_unreference(&obj
->base
);
7208 mutex_unlock(&dev
->struct_mutex
);
7211 spin_lock_irqsave(&dev
->event_lock
, flags
);
7212 intel_crtc
->unpin_work
= NULL
;
7213 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7215 drm_vblank_put(dev
, intel_crtc
->pipe
);
7222 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
7223 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
7224 .load_lut
= intel_crtc_load_lut
,
7225 .disable
= intel_crtc_noop
,
7228 bool intel_encoder_check_is_cloned(struct intel_encoder
*encoder
)
7230 struct intel_encoder
*other_encoder
;
7231 struct drm_crtc
*crtc
= &encoder
->new_crtc
->base
;
7236 list_for_each_entry(other_encoder
,
7237 &crtc
->dev
->mode_config
.encoder_list
,
7240 if (&other_encoder
->new_crtc
->base
!= crtc
||
7241 encoder
== other_encoder
)
7250 static bool intel_encoder_crtc_ok(struct drm_encoder
*encoder
,
7251 struct drm_crtc
*crtc
)
7253 struct drm_device
*dev
;
7254 struct drm_crtc
*tmp
;
7257 WARN(!crtc
, "checking null crtc?\n");
7261 list_for_each_entry(tmp
, &dev
->mode_config
.crtc_list
, head
) {
7267 if (encoder
->possible_crtcs
& crtc_mask
)
7273 * intel_modeset_update_staged_output_state
7275 * Updates the staged output configuration state, e.g. after we've read out the
7278 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
7280 struct intel_encoder
*encoder
;
7281 struct intel_connector
*connector
;
7283 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7285 connector
->new_encoder
=
7286 to_intel_encoder(connector
->base
.encoder
);
7289 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7292 to_intel_crtc(encoder
->base
.crtc
);
7297 * intel_modeset_commit_output_state
7299 * This function copies the stage display pipe configuration to the real one.
7301 static void intel_modeset_commit_output_state(struct drm_device
*dev
)
7303 struct intel_encoder
*encoder
;
7304 struct intel_connector
*connector
;
7306 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7308 connector
->base
.encoder
= &connector
->new_encoder
->base
;
7311 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7313 encoder
->base
.crtc
= &encoder
->new_crtc
->base
;
7317 static struct drm_display_mode
*
7318 intel_modeset_adjusted_mode(struct drm_crtc
*crtc
,
7319 struct drm_display_mode
*mode
)
7321 struct drm_device
*dev
= crtc
->dev
;
7322 struct drm_display_mode
*adjusted_mode
;
7323 struct drm_encoder_helper_funcs
*encoder_funcs
;
7324 struct intel_encoder
*encoder
;
7326 adjusted_mode
= drm_mode_duplicate(dev
, mode
);
7328 return ERR_PTR(-ENOMEM
);
7330 /* Pass our mode to the connectors and the CRTC to give them a chance to
7331 * adjust it according to limitations or connector properties, and also
7332 * a chance to reject the mode entirely.
7334 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7337 if (&encoder
->new_crtc
->base
!= crtc
)
7339 encoder_funcs
= encoder
->base
.helper_private
;
7340 if (!(encoder_funcs
->mode_fixup(&encoder
->base
, mode
,
7342 DRM_DEBUG_KMS("Encoder fixup failed\n");
7347 if (!(intel_crtc_mode_fixup(crtc
, mode
, adjusted_mode
))) {
7348 DRM_DEBUG_KMS("CRTC fixup failed\n");
7351 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc
->base
.id
);
7353 return adjusted_mode
;
7355 drm_mode_destroy(dev
, adjusted_mode
);
7356 return ERR_PTR(-EINVAL
);
7359 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7360 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7362 intel_modeset_affected_pipes(struct drm_crtc
*crtc
, unsigned *modeset_pipes
,
7363 unsigned *prepare_pipes
, unsigned *disable_pipes
)
7365 struct intel_crtc
*intel_crtc
;
7366 struct drm_device
*dev
= crtc
->dev
;
7367 struct intel_encoder
*encoder
;
7368 struct intel_connector
*connector
;
7369 struct drm_crtc
*tmp_crtc
;
7371 *disable_pipes
= *modeset_pipes
= *prepare_pipes
= 0;
7373 /* Check which crtcs have changed outputs connected to them, these need
7374 * to be part of the prepare_pipes mask. We don't (yet) support global
7375 * modeset across multiple crtcs, so modeset_pipes will only have one
7376 * bit set at most. */
7377 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7379 if (connector
->base
.encoder
== &connector
->new_encoder
->base
)
7382 if (connector
->base
.encoder
) {
7383 tmp_crtc
= connector
->base
.encoder
->crtc
;
7385 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
7388 if (connector
->new_encoder
)
7390 1 << connector
->new_encoder
->new_crtc
->pipe
;
7393 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7395 if (encoder
->base
.crtc
== &encoder
->new_crtc
->base
)
7398 if (encoder
->base
.crtc
) {
7399 tmp_crtc
= encoder
->base
.crtc
;
7401 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
7404 if (encoder
->new_crtc
)
7405 *prepare_pipes
|= 1 << encoder
->new_crtc
->pipe
;
7408 /* Check for any pipes that will be fully disabled ... */
7409 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
7413 /* Don't try to disable disabled crtcs. */
7414 if (!intel_crtc
->base
.enabled
)
7417 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7419 if (encoder
->new_crtc
== intel_crtc
)
7424 *disable_pipes
|= 1 << intel_crtc
->pipe
;
7428 /* set_mode is also used to update properties on life display pipes. */
7429 intel_crtc
= to_intel_crtc(crtc
);
7431 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
7433 /* We only support modeset on one single crtc, hence we need to do that
7434 * only for the passed in crtc iff we change anything else than just
7437 * This is actually not true, to be fully compatible with the old crtc
7438 * helper we automatically disable _any_ output (i.e. doesn't need to be
7439 * connected to the crtc we're modesetting on) if it's disconnected.
7440 * Which is a rather nutty api (since changed the output configuration
7441 * without userspace's explicit request can lead to confusion), but
7442 * alas. Hence we currently need to modeset on all pipes we prepare. */
7444 *modeset_pipes
= *prepare_pipes
;
7446 /* ... and mask these out. */
7447 *modeset_pipes
&= ~(*disable_pipes
);
7448 *prepare_pipes
&= ~(*disable_pipes
);
7451 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
7453 struct drm_encoder
*encoder
;
7454 struct drm_device
*dev
= crtc
->dev
;
7456 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
7457 if (encoder
->crtc
== crtc
)
7464 intel_modeset_update_state(struct drm_device
*dev
, unsigned prepare_pipes
)
7466 struct intel_encoder
*intel_encoder
;
7467 struct intel_crtc
*intel_crtc
;
7468 struct drm_connector
*connector
;
7470 list_for_each_entry(intel_encoder
, &dev
->mode_config
.encoder_list
,
7472 if (!intel_encoder
->base
.crtc
)
7475 intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
7477 if (prepare_pipes
& (1 << intel_crtc
->pipe
))
7478 intel_encoder
->connectors_active
= false;
7481 intel_modeset_commit_output_state(dev
);
7483 /* Update computed state. */
7484 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
7486 intel_crtc
->base
.enabled
= intel_crtc_in_use(&intel_crtc
->base
);
7489 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
7490 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
7493 intel_crtc
= to_intel_crtc(connector
->encoder
->crtc
);
7495 if (prepare_pipes
& (1 << intel_crtc
->pipe
)) {
7496 struct drm_property
*dpms_property
=
7497 dev
->mode_config
.dpms_property
;
7499 connector
->dpms
= DRM_MODE_DPMS_ON
;
7500 drm_object_property_set_value(&connector
->base
,
7504 intel_encoder
= to_intel_encoder(connector
->encoder
);
7505 intel_encoder
->connectors_active
= true;
7511 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7512 list_for_each_entry((intel_crtc), \
7513 &(dev)->mode_config.crtc_list, \
7515 if (mask & (1 <<(intel_crtc)->pipe)) \
7518 intel_modeset_check_state(struct drm_device
*dev
)
7520 struct intel_crtc
*crtc
;
7521 struct intel_encoder
*encoder
;
7522 struct intel_connector
*connector
;
7524 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7526 /* This also checks the encoder/connector hw state with the
7527 * ->get_hw_state callbacks. */
7528 intel_connector_check_state(connector
);
7530 WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
7531 "connector's staged encoder doesn't match current encoder\n");
7534 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7536 bool enabled
= false;
7537 bool active
= false;
7538 enum pipe pipe
, tracked_pipe
;
7540 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7541 encoder
->base
.base
.id
,
7542 drm_get_encoder_name(&encoder
->base
));
7544 WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
7545 "encoder's stage crtc doesn't match current crtc\n");
7546 WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
7547 "encoder's active_connectors set, but no crtc\n");
7549 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7551 if (connector
->base
.encoder
!= &encoder
->base
)
7554 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
7557 WARN(!!encoder
->base
.crtc
!= enabled
,
7558 "encoder's enabled state mismatch "
7559 "(expected %i, found %i)\n",
7560 !!encoder
->base
.crtc
, enabled
);
7561 WARN(active
&& !encoder
->base
.crtc
,
7562 "active encoder with no crtc\n");
7564 WARN(encoder
->connectors_active
!= active
,
7565 "encoder's computed active state doesn't match tracked active state "
7566 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
7568 active
= encoder
->get_hw_state(encoder
, &pipe
);
7569 WARN(active
!= encoder
->connectors_active
,
7570 "encoder's hw state doesn't match sw tracking "
7571 "(expected %i, found %i)\n",
7572 encoder
->connectors_active
, active
);
7574 if (!encoder
->base
.crtc
)
7577 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
7578 WARN(active
&& pipe
!= tracked_pipe
,
7579 "active encoder's pipe doesn't match"
7580 "(expected %i, found %i)\n",
7581 tracked_pipe
, pipe
);
7585 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
7587 bool enabled
= false;
7588 bool active
= false;
7590 DRM_DEBUG_KMS("[CRTC:%d]\n",
7591 crtc
->base
.base
.id
);
7593 WARN(crtc
->active
&& !crtc
->base
.enabled
,
7594 "active crtc, but not enabled in sw tracking\n");
7596 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7598 if (encoder
->base
.crtc
!= &crtc
->base
)
7601 if (encoder
->connectors_active
)
7604 WARN(active
!= crtc
->active
,
7605 "crtc's computed active state doesn't match tracked active state "
7606 "(expected %i, found %i)\n", active
, crtc
->active
);
7607 WARN(enabled
!= crtc
->base
.enabled
,
7608 "crtc's computed enabled state doesn't match tracked enabled state "
7609 "(expected %i, found %i)\n", enabled
, crtc
->base
.enabled
);
7611 assert_pipe(dev
->dev_private
, crtc
->pipe
, crtc
->active
);
7615 int intel_set_mode(struct drm_crtc
*crtc
,
7616 struct drm_display_mode
*mode
,
7617 int x
, int y
, struct drm_framebuffer
*fb
)
7619 struct drm_device
*dev
= crtc
->dev
;
7620 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7621 struct drm_display_mode
*adjusted_mode
, *saved_mode
, *saved_hwmode
;
7622 struct intel_crtc
*intel_crtc
;
7623 unsigned disable_pipes
, prepare_pipes
, modeset_pipes
;
7626 saved_mode
= kmalloc(2 * sizeof(*saved_mode
), GFP_KERNEL
);
7629 saved_hwmode
= saved_mode
+ 1;
7631 intel_modeset_affected_pipes(crtc
, &modeset_pipes
,
7632 &prepare_pipes
, &disable_pipes
);
7634 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7635 modeset_pipes
, prepare_pipes
, disable_pipes
);
7637 for_each_intel_crtc_masked(dev
, disable_pipes
, intel_crtc
)
7638 intel_crtc_disable(&intel_crtc
->base
);
7640 *saved_hwmode
= crtc
->hwmode
;
7641 *saved_mode
= crtc
->mode
;
7643 /* Hack: Because we don't (yet) support global modeset on multiple
7644 * crtcs, we don't keep track of the new mode for more than one crtc.
7645 * Hence simply check whether any bit is set in modeset_pipes in all the
7646 * pieces of code that are not yet converted to deal with mutliple crtcs
7647 * changing their mode at the same time. */
7648 adjusted_mode
= NULL
;
7649 if (modeset_pipes
) {
7650 adjusted_mode
= intel_modeset_adjusted_mode(crtc
, mode
);
7651 if (IS_ERR(adjusted_mode
)) {
7652 ret
= PTR_ERR(adjusted_mode
);
7657 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
7658 if (intel_crtc
->base
.enabled
)
7659 dev_priv
->display
.crtc_disable(&intel_crtc
->base
);
7662 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7663 * to set it here already despite that we pass it down the callchain.
7668 /* Only after disabling all output pipelines that will be changed can we
7669 * update the the output configuration. */
7670 intel_modeset_update_state(dev
, prepare_pipes
);
7672 if (dev_priv
->display
.modeset_global_resources
)
7673 dev_priv
->display
.modeset_global_resources(dev
);
7675 /* Set up the DPLL and any encoders state that needs to adjust or depend
7678 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
7679 ret
= intel_crtc_mode_set(&intel_crtc
->base
,
7680 mode
, adjusted_mode
,
7686 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7687 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
)
7688 dev_priv
->display
.crtc_enable(&intel_crtc
->base
);
7690 if (modeset_pipes
) {
7691 /* Store real post-adjustment hardware mode. */
7692 crtc
->hwmode
= *adjusted_mode
;
7694 /* Calculate and store various constants which
7695 * are later needed by vblank and swap-completion
7696 * timestamping. They are derived from true hwmode.
7698 drm_calc_timestamping_constants(crtc
);
7701 /* FIXME: add subpixel order */
7703 drm_mode_destroy(dev
, adjusted_mode
);
7704 if (ret
&& crtc
->enabled
) {
7705 crtc
->hwmode
= *saved_hwmode
;
7706 crtc
->mode
= *saved_mode
;
7708 intel_modeset_check_state(dev
);
7716 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
7718 intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
, crtc
->fb
);
7721 #undef for_each_intel_crtc_masked
7723 static void intel_set_config_free(struct intel_set_config
*config
)
7728 kfree(config
->save_connector_encoders
);
7729 kfree(config
->save_encoder_crtcs
);
7733 static int intel_set_config_save_state(struct drm_device
*dev
,
7734 struct intel_set_config
*config
)
7736 struct drm_encoder
*encoder
;
7737 struct drm_connector
*connector
;
7740 config
->save_encoder_crtcs
=
7741 kcalloc(dev
->mode_config
.num_encoder
,
7742 sizeof(struct drm_crtc
*), GFP_KERNEL
);
7743 if (!config
->save_encoder_crtcs
)
7746 config
->save_connector_encoders
=
7747 kcalloc(dev
->mode_config
.num_connector
,
7748 sizeof(struct drm_encoder
*), GFP_KERNEL
);
7749 if (!config
->save_connector_encoders
)
7752 /* Copy data. Note that driver private data is not affected.
7753 * Should anything bad happen only the expected state is
7754 * restored, not the drivers personal bookkeeping.
7757 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
7758 config
->save_encoder_crtcs
[count
++] = encoder
->crtc
;
7762 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
7763 config
->save_connector_encoders
[count
++] = connector
->encoder
;
7769 static void intel_set_config_restore_state(struct drm_device
*dev
,
7770 struct intel_set_config
*config
)
7772 struct intel_encoder
*encoder
;
7773 struct intel_connector
*connector
;
7777 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
7779 to_intel_crtc(config
->save_encoder_crtcs
[count
++]);
7783 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
7784 connector
->new_encoder
=
7785 to_intel_encoder(config
->save_connector_encoders
[count
++]);
7790 intel_set_config_compute_mode_changes(struct drm_mode_set
*set
,
7791 struct intel_set_config
*config
)
7794 /* We should be able to check here if the fb has the same properties
7795 * and then just flip_or_move it */
7796 if (set
->crtc
->fb
!= set
->fb
) {
7797 /* If we have no fb then treat it as a full mode set */
7798 if (set
->crtc
->fb
== NULL
) {
7799 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7800 config
->mode_changed
= true;
7801 } else if (set
->fb
== NULL
) {
7802 config
->mode_changed
= true;
7803 } else if (set
->fb
->depth
!= set
->crtc
->fb
->depth
) {
7804 config
->mode_changed
= true;
7805 } else if (set
->fb
->bits_per_pixel
!=
7806 set
->crtc
->fb
->bits_per_pixel
) {
7807 config
->mode_changed
= true;
7809 config
->fb_changed
= true;
7812 if (set
->fb
&& (set
->x
!= set
->crtc
->x
|| set
->y
!= set
->crtc
->y
))
7813 config
->fb_changed
= true;
7815 if (set
->mode
&& !drm_mode_equal(set
->mode
, &set
->crtc
->mode
)) {
7816 DRM_DEBUG_KMS("modes are different, full mode set\n");
7817 drm_mode_debug_printmodeline(&set
->crtc
->mode
);
7818 drm_mode_debug_printmodeline(set
->mode
);
7819 config
->mode_changed
= true;
7824 intel_modeset_stage_output_state(struct drm_device
*dev
,
7825 struct drm_mode_set
*set
,
7826 struct intel_set_config
*config
)
7828 struct drm_crtc
*new_crtc
;
7829 struct intel_connector
*connector
;
7830 struct intel_encoder
*encoder
;
7833 /* The upper layers ensure that we either disabl a crtc or have a list
7834 * of connectors. For paranoia, double-check this. */
7835 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
7836 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
7839 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7841 /* Otherwise traverse passed in connector list and get encoders
7843 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
7844 if (set
->connectors
[ro
] == &connector
->base
) {
7845 connector
->new_encoder
= connector
->encoder
;
7850 /* If we disable the crtc, disable all its connectors. Also, if
7851 * the connector is on the changing crtc but not on the new
7852 * connector list, disable it. */
7853 if ((!set
->fb
|| ro
== set
->num_connectors
) &&
7854 connector
->base
.encoder
&&
7855 connector
->base
.encoder
->crtc
== set
->crtc
) {
7856 connector
->new_encoder
= NULL
;
7858 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7859 connector
->base
.base
.id
,
7860 drm_get_connector_name(&connector
->base
));
7864 if (&connector
->new_encoder
->base
!= connector
->base
.encoder
) {
7865 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
7866 config
->mode_changed
= true;
7869 /* connector->new_encoder is now updated for all connectors. */
7871 /* Update crtc of enabled connectors. */
7873 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7875 if (!connector
->new_encoder
)
7878 new_crtc
= connector
->new_encoder
->base
.crtc
;
7880 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
7881 if (set
->connectors
[ro
] == &connector
->base
)
7882 new_crtc
= set
->crtc
;
7885 /* Make sure the new CRTC will work with the encoder */
7886 if (!intel_encoder_crtc_ok(&connector
->new_encoder
->base
,
7890 connector
->encoder
->new_crtc
= to_intel_crtc(new_crtc
);
7892 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7893 connector
->base
.base
.id
,
7894 drm_get_connector_name(&connector
->base
),
7898 /* Check for any encoders that needs to be disabled. */
7899 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7901 list_for_each_entry(connector
,
7902 &dev
->mode_config
.connector_list
,
7904 if (connector
->new_encoder
== encoder
) {
7905 WARN_ON(!connector
->new_encoder
->new_crtc
);
7910 encoder
->new_crtc
= NULL
;
7912 /* Only now check for crtc changes so we don't miss encoders
7913 * that will be disabled. */
7914 if (&encoder
->new_crtc
->base
!= encoder
->base
.crtc
) {
7915 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
7916 config
->mode_changed
= true;
7919 /* Now we've also updated encoder->new_crtc for all encoders. */
7924 static int intel_crtc_set_config(struct drm_mode_set
*set
)
7926 struct drm_device
*dev
;
7927 struct drm_mode_set save_set
;
7928 struct intel_set_config
*config
;
7933 BUG_ON(!set
->crtc
->helper_private
);
7938 /* The fb helper likes to play gross jokes with ->mode_set_config.
7939 * Unfortunately the crtc helper doesn't do much at all for this case,
7940 * so we have to cope with this madness until the fb helper is fixed up. */
7941 if (set
->fb
&& set
->num_connectors
== 0)
7945 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
7946 set
->crtc
->base
.id
, set
->fb
->base
.id
,
7947 (int)set
->num_connectors
, set
->x
, set
->y
);
7949 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
7952 dev
= set
->crtc
->dev
;
7955 config
= kzalloc(sizeof(*config
), GFP_KERNEL
);
7959 ret
= intel_set_config_save_state(dev
, config
);
7963 save_set
.crtc
= set
->crtc
;
7964 save_set
.mode
= &set
->crtc
->mode
;
7965 save_set
.x
= set
->crtc
->x
;
7966 save_set
.y
= set
->crtc
->y
;
7967 save_set
.fb
= set
->crtc
->fb
;
7969 /* Compute whether we need a full modeset, only an fb base update or no
7970 * change at all. In the future we might also check whether only the
7971 * mode changed, e.g. for LVDS where we only change the panel fitter in
7973 intel_set_config_compute_mode_changes(set
, config
);
7975 ret
= intel_modeset_stage_output_state(dev
, set
, config
);
7979 if (config
->mode_changed
) {
7981 DRM_DEBUG_KMS("attempting to set mode from"
7983 drm_mode_debug_printmodeline(set
->mode
);
7986 ret
= intel_set_mode(set
->crtc
, set
->mode
,
7987 set
->x
, set
->y
, set
->fb
);
7989 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
7990 set
->crtc
->base
.id
, ret
);
7993 } else if (config
->fb_changed
) {
7994 ret
= intel_pipe_set_base(set
->crtc
,
7995 set
->x
, set
->y
, set
->fb
);
7998 intel_set_config_free(config
);
8003 intel_set_config_restore_state(dev
, config
);
8005 /* Try to restore the config */
8006 if (config
->mode_changed
&&
8007 intel_set_mode(save_set
.crtc
, save_set
.mode
,
8008 save_set
.x
, save_set
.y
, save_set
.fb
))
8009 DRM_ERROR("failed to restore config after modeset failure\n");
8012 intel_set_config_free(config
);
8016 static const struct drm_crtc_funcs intel_crtc_funcs
= {
8017 .cursor_set
= intel_crtc_cursor_set
,
8018 .cursor_move
= intel_crtc_cursor_move
,
8019 .gamma_set
= intel_crtc_gamma_set
,
8020 .set_config
= intel_crtc_set_config
,
8021 .destroy
= intel_crtc_destroy
,
8022 .page_flip
= intel_crtc_page_flip
,
8025 static void intel_cpu_pll_init(struct drm_device
*dev
)
8028 intel_ddi_pll_init(dev
);
8031 static void intel_pch_pll_init(struct drm_device
*dev
)
8033 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8036 if (dev_priv
->num_pch_pll
== 0) {
8037 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8041 for (i
= 0; i
< dev_priv
->num_pch_pll
; i
++) {
8042 dev_priv
->pch_plls
[i
].pll_reg
= _PCH_DPLL(i
);
8043 dev_priv
->pch_plls
[i
].fp0_reg
= _PCH_FP0(i
);
8044 dev_priv
->pch_plls
[i
].fp1_reg
= _PCH_FP1(i
);
8048 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
8050 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8051 struct intel_crtc
*intel_crtc
;
8054 intel_crtc
= kzalloc(sizeof(struct intel_crtc
) + (INTELFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
8055 if (intel_crtc
== NULL
)
8058 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
8060 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
8061 for (i
= 0; i
< 256; i
++) {
8062 intel_crtc
->lut_r
[i
] = i
;
8063 intel_crtc
->lut_g
[i
] = i
;
8064 intel_crtc
->lut_b
[i
] = i
;
8067 /* Swap pipes & planes for FBC on pre-965 */
8068 intel_crtc
->pipe
= pipe
;
8069 intel_crtc
->plane
= pipe
;
8070 intel_crtc
->cpu_transcoder
= pipe
;
8071 if (IS_MOBILE(dev
) && IS_GEN3(dev
)) {
8072 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8073 intel_crtc
->plane
= !pipe
;
8076 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
8077 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
8078 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
8079 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
8081 intel_crtc
->bpp
= 24; /* default for pre-Ironlake */
8083 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
8086 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
8087 struct drm_file
*file
)
8089 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
8090 struct drm_mode_object
*drmmode_obj
;
8091 struct intel_crtc
*crtc
;
8093 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
8096 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
8097 DRM_MODE_OBJECT_CRTC
);
8100 DRM_ERROR("no such CRTC id\n");
8104 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
8105 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
8110 static int intel_encoder_clones(struct intel_encoder
*encoder
)
8112 struct drm_device
*dev
= encoder
->base
.dev
;
8113 struct intel_encoder
*source_encoder
;
8117 list_for_each_entry(source_encoder
,
8118 &dev
->mode_config
.encoder_list
, base
.head
) {
8120 if (encoder
== source_encoder
)
8121 index_mask
|= (1 << entry
);
8123 /* Intel hw has only one MUX where enocoders could be cloned. */
8124 if (encoder
->cloneable
&& source_encoder
->cloneable
)
8125 index_mask
|= (1 << entry
);
8133 static bool has_edp_a(struct drm_device
*dev
)
8135 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8137 if (!IS_MOBILE(dev
))
8140 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
8144 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES
) & ILK_eDP_A_DISABLE
))
8150 static void intel_setup_outputs(struct drm_device
*dev
)
8152 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8153 struct intel_encoder
*encoder
;
8154 bool dpd_is_edp
= false;
8157 has_lvds
= intel_lvds_init(dev
);
8158 if (!has_lvds
&& !HAS_PCH_SPLIT(dev
)) {
8159 /* disable the panel fitter on everything but LVDS */
8160 I915_WRITE(PFIT_CONTROL
, 0);
8163 if (!(HAS_DDI(dev
) && (I915_READ(DDI_BUF_CTL(PORT_A
)) & DDI_A_4_LANES
)))
8164 intel_crt_init(dev
);
8169 /* Haswell uses DDI functions to detect digital outputs */
8170 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
8171 /* DDI A only supports eDP */
8173 intel_ddi_init(dev
, PORT_A
);
8175 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8177 found
= I915_READ(SFUSE_STRAP
);
8179 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
8180 intel_ddi_init(dev
, PORT_B
);
8181 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
8182 intel_ddi_init(dev
, PORT_C
);
8183 if (found
& SFUSE_STRAP_DDID_DETECTED
)
8184 intel_ddi_init(dev
, PORT_D
);
8185 } else if (HAS_PCH_SPLIT(dev
)) {
8187 dpd_is_edp
= intel_dpd_is_edp(dev
);
8190 intel_dp_init(dev
, DP_A
, PORT_A
);
8192 if (I915_READ(HDMIB
) & PORT_DETECTED
) {
8193 /* PCH SDVOB multiplex with HDMIB */
8194 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
8196 intel_hdmi_init(dev
, HDMIB
, PORT_B
);
8197 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
8198 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
8201 if (I915_READ(HDMIC
) & PORT_DETECTED
)
8202 intel_hdmi_init(dev
, HDMIC
, PORT_C
);
8204 if (!dpd_is_edp
&& I915_READ(HDMID
) & PORT_DETECTED
)
8205 intel_hdmi_init(dev
, HDMID
, PORT_D
);
8207 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
8208 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
8210 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
8211 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
8212 } else if (IS_VALLEYVIEW(dev
)) {
8215 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8216 if (I915_READ(DP_C
) & DP_DETECTED
)
8217 intel_dp_init(dev
, DP_C
, PORT_C
);
8219 if (I915_READ(SDVOB
) & PORT_DETECTED
) {
8220 /* SDVOB multiplex with HDMIB */
8221 found
= intel_sdvo_init(dev
, SDVOB
, true);
8223 intel_hdmi_init(dev
, SDVOB
, PORT_B
);
8224 if (!found
&& (I915_READ(DP_B
) & DP_DETECTED
))
8225 intel_dp_init(dev
, DP_B
, PORT_B
);
8228 if (I915_READ(SDVOC
) & PORT_DETECTED
)
8229 intel_hdmi_init(dev
, SDVOC
, PORT_C
);
8231 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
8234 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
8235 DRM_DEBUG_KMS("probing SDVOB\n");
8236 found
= intel_sdvo_init(dev
, SDVOB
, true);
8237 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
8238 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8239 intel_hdmi_init(dev
, SDVOB
, PORT_B
);
8242 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
)) {
8243 DRM_DEBUG_KMS("probing DP_B\n");
8244 intel_dp_init(dev
, DP_B
, PORT_B
);
8248 /* Before G4X SDVOC doesn't have its own detect register */
8250 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
8251 DRM_DEBUG_KMS("probing SDVOC\n");
8252 found
= intel_sdvo_init(dev
, SDVOC
, false);
8255 if (!found
&& (I915_READ(SDVOC
) & SDVO_DETECTED
)) {
8257 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
8258 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8259 intel_hdmi_init(dev
, SDVOC
, PORT_C
);
8261 if (SUPPORTS_INTEGRATED_DP(dev
)) {
8262 DRM_DEBUG_KMS("probing DP_C\n");
8263 intel_dp_init(dev
, DP_C
, PORT_C
);
8267 if (SUPPORTS_INTEGRATED_DP(dev
) &&
8268 (I915_READ(DP_D
) & DP_DETECTED
)) {
8269 DRM_DEBUG_KMS("probing DP_D\n");
8270 intel_dp_init(dev
, DP_D
, PORT_D
);
8272 } else if (IS_GEN2(dev
))
8273 intel_dvo_init(dev
);
8275 if (SUPPORTS_TV(dev
))
8278 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
8279 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
8280 encoder
->base
.possible_clones
=
8281 intel_encoder_clones(encoder
);
8284 intel_init_pch_refclk(dev
);
8286 drm_helper_move_panel_connectors_to_head(dev
);
8289 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
8291 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
8293 drm_framebuffer_cleanup(fb
);
8294 drm_gem_object_unreference_unlocked(&intel_fb
->obj
->base
);
8299 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
8300 struct drm_file
*file
,
8301 unsigned int *handle
)
8303 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
8304 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
8306 return drm_gem_handle_create(file
, &obj
->base
, handle
);
8309 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
8310 .destroy
= intel_user_framebuffer_destroy
,
8311 .create_handle
= intel_user_framebuffer_create_handle
,
8314 int intel_framebuffer_init(struct drm_device
*dev
,
8315 struct intel_framebuffer
*intel_fb
,
8316 struct drm_mode_fb_cmd2
*mode_cmd
,
8317 struct drm_i915_gem_object
*obj
)
8321 if (obj
->tiling_mode
== I915_TILING_Y
)
8324 if (mode_cmd
->pitches
[0] & 63)
8327 /* FIXME <= Gen4 stride limits are bit unclear */
8328 if (mode_cmd
->pitches
[0] > 32768)
8331 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
8332 mode_cmd
->pitches
[0] != obj
->stride
)
8335 /* Reject formats not supported by any plane early. */
8336 switch (mode_cmd
->pixel_format
) {
8338 case DRM_FORMAT_RGB565
:
8339 case DRM_FORMAT_XRGB8888
:
8340 case DRM_FORMAT_ARGB8888
:
8342 case DRM_FORMAT_XRGB1555
:
8343 case DRM_FORMAT_ARGB1555
:
8344 if (INTEL_INFO(dev
)->gen
> 3)
8347 case DRM_FORMAT_XBGR8888
:
8348 case DRM_FORMAT_ABGR8888
:
8349 case DRM_FORMAT_XRGB2101010
:
8350 case DRM_FORMAT_ARGB2101010
:
8351 case DRM_FORMAT_XBGR2101010
:
8352 case DRM_FORMAT_ABGR2101010
:
8353 if (INTEL_INFO(dev
)->gen
< 4)
8356 case DRM_FORMAT_YUYV
:
8357 case DRM_FORMAT_UYVY
:
8358 case DRM_FORMAT_YVYU
:
8359 case DRM_FORMAT_VYUY
:
8360 if (INTEL_INFO(dev
)->gen
< 6)
8364 DRM_DEBUG_KMS("unsupported pixel format 0x%08x\n", mode_cmd
->pixel_format
);
8368 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8369 if (mode_cmd
->offsets
[0] != 0)
8372 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
8374 DRM_ERROR("framebuffer init failed %d\n", ret
);
8378 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
8379 intel_fb
->obj
= obj
;
8383 static struct drm_framebuffer
*
8384 intel_user_framebuffer_create(struct drm_device
*dev
,
8385 struct drm_file
*filp
,
8386 struct drm_mode_fb_cmd2
*mode_cmd
)
8388 struct drm_i915_gem_object
*obj
;
8390 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
8391 mode_cmd
->handles
[0]));
8392 if (&obj
->base
== NULL
)
8393 return ERR_PTR(-ENOENT
);
8395 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
8398 static const struct drm_mode_config_funcs intel_mode_funcs
= {
8399 .fb_create
= intel_user_framebuffer_create
,
8400 .output_poll_changed
= intel_fb_output_poll_changed
,
8403 /* Set up chip specific display functions */
8404 static void intel_init_display(struct drm_device
*dev
)
8406 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8408 /* We always want a DPMS function */
8410 dev_priv
->display
.crtc_mode_set
= haswell_crtc_mode_set
;
8411 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
8412 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
8413 dev_priv
->display
.off
= haswell_crtc_off
;
8414 dev_priv
->display
.update_plane
= ironlake_update_plane
;
8415 } else if (HAS_PCH_SPLIT(dev
)) {
8416 dev_priv
->display
.crtc_mode_set
= ironlake_crtc_mode_set
;
8417 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
8418 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
8419 dev_priv
->display
.off
= ironlake_crtc_off
;
8420 dev_priv
->display
.update_plane
= ironlake_update_plane
;
8422 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
8423 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
8424 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
8425 dev_priv
->display
.off
= i9xx_crtc_off
;
8426 dev_priv
->display
.update_plane
= i9xx_update_plane
;
8429 /* Returns the core display clock speed */
8430 if (IS_VALLEYVIEW(dev
))
8431 dev_priv
->display
.get_display_clock_speed
=
8432 valleyview_get_display_clock_speed
;
8433 else if (IS_I945G(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
8434 dev_priv
->display
.get_display_clock_speed
=
8435 i945_get_display_clock_speed
;
8436 else if (IS_I915G(dev
))
8437 dev_priv
->display
.get_display_clock_speed
=
8438 i915_get_display_clock_speed
;
8439 else if (IS_I945GM(dev
) || IS_845G(dev
) || IS_PINEVIEW_M(dev
))
8440 dev_priv
->display
.get_display_clock_speed
=
8441 i9xx_misc_get_display_clock_speed
;
8442 else if (IS_I915GM(dev
))
8443 dev_priv
->display
.get_display_clock_speed
=
8444 i915gm_get_display_clock_speed
;
8445 else if (IS_I865G(dev
))
8446 dev_priv
->display
.get_display_clock_speed
=
8447 i865_get_display_clock_speed
;
8448 else if (IS_I85X(dev
))
8449 dev_priv
->display
.get_display_clock_speed
=
8450 i855_get_display_clock_speed
;
8452 dev_priv
->display
.get_display_clock_speed
=
8453 i830_get_display_clock_speed
;
8455 if (HAS_PCH_SPLIT(dev
)) {
8457 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
8458 dev_priv
->display
.write_eld
= ironlake_write_eld
;
8459 } else if (IS_GEN6(dev
)) {
8460 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
8461 dev_priv
->display
.write_eld
= ironlake_write_eld
;
8462 } else if (IS_IVYBRIDGE(dev
)) {
8463 /* FIXME: detect B0+ stepping and use auto training */
8464 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
8465 dev_priv
->display
.write_eld
= ironlake_write_eld
;
8466 dev_priv
->display
.modeset_global_resources
=
8467 ivb_modeset_global_resources
;
8468 } else if (IS_HASWELL(dev
)) {
8469 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
8470 dev_priv
->display
.write_eld
= haswell_write_eld
;
8472 } else if (IS_G4X(dev
)) {
8473 dev_priv
->display
.write_eld
= g4x_write_eld
;
8476 /* Default just returns -ENODEV to indicate unsupported */
8477 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
8479 switch (INTEL_INFO(dev
)->gen
) {
8481 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
8485 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
8490 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
8494 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
8497 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
8503 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8504 * resume, or other times. This quirk makes sure that's the case for
8507 static void quirk_pipea_force(struct drm_device
*dev
)
8509 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8511 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
8512 DRM_INFO("applying pipe a force quirk\n");
8516 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8518 static void quirk_ssc_force_disable(struct drm_device
*dev
)
8520 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8521 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
8522 DRM_INFO("applying lvds SSC disable quirk\n");
8526 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8529 static void quirk_invert_brightness(struct drm_device
*dev
)
8531 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8532 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
8533 DRM_INFO("applying inverted panel brightness quirk\n");
8536 struct intel_quirk
{
8538 int subsystem_vendor
;
8539 int subsystem_device
;
8540 void (*hook
)(struct drm_device
*dev
);
8543 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8544 struct intel_dmi_quirk
{
8545 void (*hook
)(struct drm_device
*dev
);
8546 const struct dmi_system_id (*dmi_id_list
)[];
8549 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
8551 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
8555 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
8557 .dmi_id_list
= &(const struct dmi_system_id
[]) {
8559 .callback
= intel_dmi_reverse_brightness
,
8560 .ident
= "NCR Corporation",
8561 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
8562 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
8565 { } /* terminating entry */
8567 .hook
= quirk_invert_brightness
,
8571 static struct intel_quirk intel_quirks
[] = {
8572 /* HP Mini needs pipe A force quirk (LP: #322104) */
8573 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
8575 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8576 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
8578 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8579 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
8581 /* 830/845 need to leave pipe A & dpll A up */
8582 { 0x2562, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
8583 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
8585 /* Lenovo U160 cannot use SSC on LVDS */
8586 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
8588 /* Sony Vaio Y cannot use SSC on LVDS */
8589 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
8591 /* Acer Aspire 5734Z must invert backlight brightness */
8592 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
8595 static void intel_init_quirks(struct drm_device
*dev
)
8597 struct pci_dev
*d
= dev
->pdev
;
8600 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
8601 struct intel_quirk
*q
= &intel_quirks
[i
];
8603 if (d
->device
== q
->device
&&
8604 (d
->subsystem_vendor
== q
->subsystem_vendor
||
8605 q
->subsystem_vendor
== PCI_ANY_ID
) &&
8606 (d
->subsystem_device
== q
->subsystem_device
||
8607 q
->subsystem_device
== PCI_ANY_ID
))
8610 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
8611 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
8612 intel_dmi_quirks
[i
].hook(dev
);
8616 /* Disable the VGA plane that we never use */
8617 static void i915_disable_vga(struct drm_device
*dev
)
8619 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8623 if (HAS_PCH_SPLIT(dev
))
8624 vga_reg
= CPU_VGACNTRL
;
8628 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
8629 outb(SR01
, VGA_SR_INDEX
);
8630 sr1
= inb(VGA_SR_DATA
);
8631 outb(sr1
| 1<<5, VGA_SR_DATA
);
8632 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
8635 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
8636 POSTING_READ(vga_reg
);
8639 void intel_modeset_init_hw(struct drm_device
*dev
)
8641 /* We attempt to init the necessary power wells early in the initialization
8642 * time, so the subsystems that expect power to be enabled can work.
8644 intel_init_power_wells(dev
);
8646 intel_prepare_ddi(dev
);
8648 intel_init_clock_gating(dev
);
8650 mutex_lock(&dev
->struct_mutex
);
8651 intel_enable_gt_powersave(dev
);
8652 mutex_unlock(&dev
->struct_mutex
);
8655 void intel_modeset_init(struct drm_device
*dev
)
8657 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8660 drm_mode_config_init(dev
);
8662 dev
->mode_config
.min_width
= 0;
8663 dev
->mode_config
.min_height
= 0;
8665 dev
->mode_config
.preferred_depth
= 24;
8666 dev
->mode_config
.prefer_shadow
= 1;
8668 dev
->mode_config
.funcs
= &intel_mode_funcs
;
8670 intel_init_quirks(dev
);
8674 intel_init_display(dev
);
8677 dev
->mode_config
.max_width
= 2048;
8678 dev
->mode_config
.max_height
= 2048;
8679 } else if (IS_GEN3(dev
)) {
8680 dev
->mode_config
.max_width
= 4096;
8681 dev
->mode_config
.max_height
= 4096;
8683 dev
->mode_config
.max_width
= 8192;
8684 dev
->mode_config
.max_height
= 8192;
8686 dev
->mode_config
.fb_base
= dev_priv
->mm
.gtt_base_addr
;
8688 DRM_DEBUG_KMS("%d display pipe%s available.\n",
8689 dev_priv
->num_pipe
, dev_priv
->num_pipe
> 1 ? "s" : "");
8691 for (i
= 0; i
< dev_priv
->num_pipe
; i
++) {
8692 intel_crtc_init(dev
, i
);
8693 ret
= intel_plane_init(dev
, i
);
8695 DRM_DEBUG_KMS("plane %d init failed: %d\n", i
, ret
);
8698 intel_cpu_pll_init(dev
);
8699 intel_pch_pll_init(dev
);
8701 /* Just disable it once at startup */
8702 i915_disable_vga(dev
);
8703 intel_setup_outputs(dev
);
8705 /* Just in case the BIOS is doing something questionable. */
8706 intel_disable_fbc(dev
);
8710 intel_connector_break_all_links(struct intel_connector
*connector
)
8712 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
8713 connector
->base
.encoder
= NULL
;
8714 connector
->encoder
->connectors_active
= false;
8715 connector
->encoder
->base
.crtc
= NULL
;
8718 static void intel_enable_pipe_a(struct drm_device
*dev
)
8720 struct intel_connector
*connector
;
8721 struct drm_connector
*crt
= NULL
;
8722 struct intel_load_detect_pipe load_detect_temp
;
8724 /* We can't just switch on the pipe A, we need to set things up with a
8725 * proper mode and output configuration. As a gross hack, enable pipe A
8726 * by enabling the load detect pipe once. */
8727 list_for_each_entry(connector
,
8728 &dev
->mode_config
.connector_list
,
8730 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
8731 crt
= &connector
->base
;
8739 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
))
8740 intel_release_load_detect_pipe(crt
, &load_detect_temp
);
8746 intel_check_plane_mapping(struct intel_crtc
*crtc
)
8748 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
8751 if (dev_priv
->num_pipe
== 1)
8754 reg
= DSPCNTR(!crtc
->plane
);
8755 val
= I915_READ(reg
);
8757 if ((val
& DISPLAY_PLANE_ENABLE
) &&
8758 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
8764 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
8766 struct drm_device
*dev
= crtc
->base
.dev
;
8767 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8770 /* Clear any frame start delays used for debugging left by the BIOS */
8771 reg
= PIPECONF(crtc
->cpu_transcoder
);
8772 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
8774 /* We need to sanitize the plane -> pipe mapping first because this will
8775 * disable the crtc (and hence change the state) if it is wrong. Note
8776 * that gen4+ has a fixed plane -> pipe mapping. */
8777 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
8778 struct intel_connector
*connector
;
8781 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8782 crtc
->base
.base
.id
);
8784 /* Pipe has the wrong plane attached and the plane is active.
8785 * Temporarily change the plane mapping and disable everything
8787 plane
= crtc
->plane
;
8788 crtc
->plane
= !plane
;
8789 dev_priv
->display
.crtc_disable(&crtc
->base
);
8790 crtc
->plane
= plane
;
8792 /* ... and break all links. */
8793 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8795 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
8798 intel_connector_break_all_links(connector
);
8801 WARN_ON(crtc
->active
);
8802 crtc
->base
.enabled
= false;
8805 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
8806 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
8807 /* BIOS forgot to enable pipe A, this mostly happens after
8808 * resume. Force-enable the pipe to fix this, the update_dpms
8809 * call below we restore the pipe to the right state, but leave
8810 * the required bits on. */
8811 intel_enable_pipe_a(dev
);
8814 /* Adjust the state of the output pipe according to whether we
8815 * have active connectors/encoders. */
8816 intel_crtc_update_dpms(&crtc
->base
);
8818 if (crtc
->active
!= crtc
->base
.enabled
) {
8819 struct intel_encoder
*encoder
;
8821 /* This can happen either due to bugs in the get_hw_state
8822 * functions or because the pipe is force-enabled due to the
8824 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8826 crtc
->base
.enabled
? "enabled" : "disabled",
8827 crtc
->active
? "enabled" : "disabled");
8829 crtc
->base
.enabled
= crtc
->active
;
8831 /* Because we only establish the connector -> encoder ->
8832 * crtc links if something is active, this means the
8833 * crtc is now deactivated. Break the links. connector
8834 * -> encoder links are only establish when things are
8835 * actually up, hence no need to break them. */
8836 WARN_ON(crtc
->active
);
8838 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
8839 WARN_ON(encoder
->connectors_active
);
8840 encoder
->base
.crtc
= NULL
;
8845 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
8847 struct intel_connector
*connector
;
8848 struct drm_device
*dev
= encoder
->base
.dev
;
8850 /* We need to check both for a crtc link (meaning that the
8851 * encoder is active and trying to read from a pipe) and the
8852 * pipe itself being active. */
8853 bool has_active_crtc
= encoder
->base
.crtc
&&
8854 to_intel_crtc(encoder
->base
.crtc
)->active
;
8856 if (encoder
->connectors_active
&& !has_active_crtc
) {
8857 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8858 encoder
->base
.base
.id
,
8859 drm_get_encoder_name(&encoder
->base
));
8861 /* Connector is active, but has no active pipe. This is
8862 * fallout from our resume register restoring. Disable
8863 * the encoder manually again. */
8864 if (encoder
->base
.crtc
) {
8865 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8866 encoder
->base
.base
.id
,
8867 drm_get_encoder_name(&encoder
->base
));
8868 encoder
->disable(encoder
);
8871 /* Inconsistent output/port/pipe state happens presumably due to
8872 * a bug in one of the get_hw_state functions. Or someplace else
8873 * in our code, like the register restore mess on resume. Clamp
8874 * things to off as a safer default. */
8875 list_for_each_entry(connector
,
8876 &dev
->mode_config
.connector_list
,
8878 if (connector
->encoder
!= encoder
)
8881 intel_connector_break_all_links(connector
);
8884 /* Enabled encoders without active connectors will be fixed in
8885 * the crtc fixup. */
8888 static void i915_redisable_vga(struct drm_device
*dev
)
8890 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8893 if (HAS_PCH_SPLIT(dev
))
8894 vga_reg
= CPU_VGACNTRL
;
8898 if (I915_READ(vga_reg
) != VGA_DISP_DISABLE
) {
8899 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
8900 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
8901 POSTING_READ(vga_reg
);
8905 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8906 * and i915 state tracking structures. */
8907 void intel_modeset_setup_hw_state(struct drm_device
*dev
,
8910 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8913 struct intel_crtc
*crtc
;
8914 struct intel_encoder
*encoder
;
8915 struct intel_connector
*connector
;
8918 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
8920 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
8921 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
8922 case TRANS_DDI_EDP_INPUT_A_ON
:
8923 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
8926 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
8929 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
8934 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
8935 crtc
->cpu_transcoder
= TRANSCODER_EDP
;
8937 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
8942 for_each_pipe(pipe
) {
8943 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
8945 tmp
= I915_READ(PIPECONF(crtc
->cpu_transcoder
));
8946 if (tmp
& PIPECONF_ENABLE
)
8947 crtc
->active
= true;
8949 crtc
->active
= false;
8951 crtc
->base
.enabled
= crtc
->active
;
8953 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
8955 crtc
->active
? "enabled" : "disabled");
8959 intel_ddi_setup_hw_pll_state(dev
);
8961 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8965 if (encoder
->get_hw_state(encoder
, &pipe
)) {
8966 encoder
->base
.crtc
=
8967 dev_priv
->pipe_to_crtc_mapping
[pipe
];
8969 encoder
->base
.crtc
= NULL
;
8972 encoder
->connectors_active
= false;
8973 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
8974 encoder
->base
.base
.id
,
8975 drm_get_encoder_name(&encoder
->base
),
8976 encoder
->base
.crtc
? "enabled" : "disabled",
8980 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8982 if (connector
->get_hw_state(connector
)) {
8983 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
8984 connector
->encoder
->connectors_active
= true;
8985 connector
->base
.encoder
= &connector
->encoder
->base
;
8987 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
8988 connector
->base
.encoder
= NULL
;
8990 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
8991 connector
->base
.base
.id
,
8992 drm_get_connector_name(&connector
->base
),
8993 connector
->base
.encoder
? "enabled" : "disabled");
8996 /* HW state is read out, now we need to sanitize this mess. */
8997 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8999 intel_sanitize_encoder(encoder
);
9002 for_each_pipe(pipe
) {
9003 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
9004 intel_sanitize_crtc(crtc
);
9007 if (force_restore
) {
9008 for_each_pipe(pipe
) {
9009 intel_crtc_restore_mode(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
9012 i915_redisable_vga(dev
);
9014 intel_modeset_update_staged_output_state(dev
);
9017 intel_modeset_check_state(dev
);
9019 drm_mode_config_reset(dev
);
9022 void intel_modeset_gem_init(struct drm_device
*dev
)
9024 intel_modeset_init_hw(dev
);
9026 intel_setup_overlay(dev
);
9028 intel_modeset_setup_hw_state(dev
, false);
9031 void intel_modeset_cleanup(struct drm_device
*dev
)
9033 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9034 struct drm_crtc
*crtc
;
9035 struct intel_crtc
*intel_crtc
;
9037 drm_kms_helper_poll_fini(dev
);
9038 mutex_lock(&dev
->struct_mutex
);
9040 intel_unregister_dsm_handler();
9043 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
9044 /* Skip inactive CRTCs */
9048 intel_crtc
= to_intel_crtc(crtc
);
9049 intel_increase_pllclock(crtc
);
9052 intel_disable_fbc(dev
);
9054 intel_disable_gt_powersave(dev
);
9056 ironlake_teardown_rc6(dev
);
9058 if (IS_VALLEYVIEW(dev
))
9061 mutex_unlock(&dev
->struct_mutex
);
9063 /* Disable the irq before mode object teardown, for the irq might
9064 * enqueue unpin/hotplug work. */
9065 drm_irq_uninstall(dev
);
9066 cancel_work_sync(&dev_priv
->hotplug_work
);
9067 cancel_work_sync(&dev_priv
->rps
.work
);
9069 /* flush any delayed tasks or pending work */
9070 flush_scheduled_work();
9072 drm_mode_config_cleanup(dev
);
9074 intel_cleanup_overlay(dev
);
9078 * Return which encoder is currently attached for connector.
9080 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
9082 return &intel_attached_encoder(connector
)->base
;
9085 void intel_connector_attach_encoder(struct intel_connector
*connector
,
9086 struct intel_encoder
*encoder
)
9088 connector
->encoder
= encoder
;
9089 drm_mode_connector_attach_encoder(&connector
->base
,
9094 * set vga decode state - true == enable VGA decode
9096 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
9098 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9101 pci_read_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, &gmch_ctrl
);
9103 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
9105 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
9106 pci_write_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, gmch_ctrl
);
9110 #ifdef CONFIG_DEBUG_FS
9111 #include <linux/seq_file.h>
9113 struct intel_display_error_state
{
9114 struct intel_cursor_error_state
{
9119 } cursor
[I915_MAX_PIPES
];
9121 struct intel_pipe_error_state
{
9131 } pipe
[I915_MAX_PIPES
];
9133 struct intel_plane_error_state
{
9141 } plane
[I915_MAX_PIPES
];
9144 struct intel_display_error_state
*
9145 intel_display_capture_error_state(struct drm_device
*dev
)
9147 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
9148 struct intel_display_error_state
*error
;
9149 enum transcoder cpu_transcoder
;
9152 error
= kmalloc(sizeof(*error
), GFP_ATOMIC
);
9157 cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
, i
);
9159 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
9160 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
9161 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
9163 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
9164 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
9165 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
9166 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
9167 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
9168 if (INTEL_INFO(dev
)->gen
>= 4) {
9169 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
9170 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
9173 error
->pipe
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
9174 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
9175 error
->pipe
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
9176 error
->pipe
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
9177 error
->pipe
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
9178 error
->pipe
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
9179 error
->pipe
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
9180 error
->pipe
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
9187 intel_display_print_error_state(struct seq_file
*m
,
9188 struct drm_device
*dev
,
9189 struct intel_display_error_state
*error
)
9191 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
9194 seq_printf(m
, "Num Pipes: %d\n", dev_priv
->num_pipe
);
9196 seq_printf(m
, "Pipe [%d]:\n", i
);
9197 seq_printf(m
, " CONF: %08x\n", error
->pipe
[i
].conf
);
9198 seq_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
9199 seq_printf(m
, " HTOTAL: %08x\n", error
->pipe
[i
].htotal
);
9200 seq_printf(m
, " HBLANK: %08x\n", error
->pipe
[i
].hblank
);
9201 seq_printf(m
, " HSYNC: %08x\n", error
->pipe
[i
].hsync
);
9202 seq_printf(m
, " VTOTAL: %08x\n", error
->pipe
[i
].vtotal
);
9203 seq_printf(m
, " VBLANK: %08x\n", error
->pipe
[i
].vblank
);
9204 seq_printf(m
, " VSYNC: %08x\n", error
->pipe
[i
].vsync
);
9206 seq_printf(m
, "Plane [%d]:\n", i
);
9207 seq_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
9208 seq_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
9209 seq_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
9210 seq_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
9211 seq_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
9212 if (INTEL_INFO(dev
)->gen
>= 4) {
9213 seq_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
9214 seq_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
9217 seq_printf(m
, "Cursor [%d]:\n", i
);
9218 seq_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
9219 seq_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
9220 seq_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);