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drm/i915: ddi: move pch setup after encoder->pre_enable
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_rect.h>
44 #include <linux/dma_remapping.h>
45
46 /* Primary plane formats supported by all gen */
47 #define COMMON_PRIMARY_FORMATS \
48 DRM_FORMAT_C8, \
49 DRM_FORMAT_RGB565, \
50 DRM_FORMAT_XRGB8888, \
51 DRM_FORMAT_ARGB8888
52
53 /* Primary plane formats for gen <= 3 */
54 static const uint32_t intel_primary_formats_gen2[] = {
55 COMMON_PRIMARY_FORMATS,
56 DRM_FORMAT_XRGB1555,
57 DRM_FORMAT_ARGB1555,
58 };
59
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t intel_primary_formats_gen4[] = {
62 COMMON_PRIMARY_FORMATS, \
63 DRM_FORMAT_XBGR8888,
64 DRM_FORMAT_ABGR8888,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_ARGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 DRM_FORMAT_ABGR2101010,
69 };
70
71 /* Cursor formats */
72 static const uint32_t intel_cursor_formats[] = {
73 DRM_FORMAT_ARGB8888,
74 };
75
76 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
77 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
78
79 static void intel_increase_pllclock(struct drm_device *dev,
80 enum pipe pipe);
81 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
82
83 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
84 struct intel_crtc_config *pipe_config);
85 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
86 struct intel_crtc_config *pipe_config);
87
88 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
89 int x, int y, struct drm_framebuffer *old_fb);
90 static int intel_framebuffer_init(struct drm_device *dev,
91 struct intel_framebuffer *ifb,
92 struct drm_mode_fb_cmd2 *mode_cmd,
93 struct drm_i915_gem_object *obj);
94 static void intel_dp_set_m_n(struct intel_crtc *crtc);
95 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
96 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
97 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
98 struct intel_link_m_n *m_n);
99 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
100 static void haswell_set_pipeconf(struct drm_crtc *crtc);
101 static void intel_set_pipe_csc(struct drm_crtc *crtc);
102 static void vlv_prepare_pll(struct intel_crtc *crtc);
103
104 typedef struct {
105 int min, max;
106 } intel_range_t;
107
108 typedef struct {
109 int dot_limit;
110 int p2_slow, p2_fast;
111 } intel_p2_t;
112
113 typedef struct intel_limit intel_limit_t;
114 struct intel_limit {
115 intel_range_t dot, vco, n, m, m1, m2, p, p1;
116 intel_p2_t p2;
117 };
118
119 int
120 intel_pch_rawclk(struct drm_device *dev)
121 {
122 struct drm_i915_private *dev_priv = dev->dev_private;
123
124 WARN_ON(!HAS_PCH_SPLIT(dev));
125
126 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
127 }
128
129 static inline u32 /* units of 100MHz */
130 intel_fdi_link_freq(struct drm_device *dev)
131 {
132 if (IS_GEN5(dev)) {
133 struct drm_i915_private *dev_priv = dev->dev_private;
134 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
135 } else
136 return 27;
137 }
138
139 static const intel_limit_t intel_limits_i8xx_dac = {
140 .dot = { .min = 25000, .max = 350000 },
141 .vco = { .min = 908000, .max = 1512000 },
142 .n = { .min = 2, .max = 16 },
143 .m = { .min = 96, .max = 140 },
144 .m1 = { .min = 18, .max = 26 },
145 .m2 = { .min = 6, .max = 16 },
146 .p = { .min = 4, .max = 128 },
147 .p1 = { .min = 2, .max = 33 },
148 .p2 = { .dot_limit = 165000,
149 .p2_slow = 4, .p2_fast = 2 },
150 };
151
152 static const intel_limit_t intel_limits_i8xx_dvo = {
153 .dot = { .min = 25000, .max = 350000 },
154 .vco = { .min = 908000, .max = 1512000 },
155 .n = { .min = 2, .max = 16 },
156 .m = { .min = 96, .max = 140 },
157 .m1 = { .min = 18, .max = 26 },
158 .m2 = { .min = 6, .max = 16 },
159 .p = { .min = 4, .max = 128 },
160 .p1 = { .min = 2, .max = 33 },
161 .p2 = { .dot_limit = 165000,
162 .p2_slow = 4, .p2_fast = 4 },
163 };
164
165 static const intel_limit_t intel_limits_i8xx_lvds = {
166 .dot = { .min = 25000, .max = 350000 },
167 .vco = { .min = 908000, .max = 1512000 },
168 .n = { .min = 2, .max = 16 },
169 .m = { .min = 96, .max = 140 },
170 .m1 = { .min = 18, .max = 26 },
171 .m2 = { .min = 6, .max = 16 },
172 .p = { .min = 4, .max = 128 },
173 .p1 = { .min = 1, .max = 6 },
174 .p2 = { .dot_limit = 165000,
175 .p2_slow = 14, .p2_fast = 7 },
176 };
177
178 static const intel_limit_t intel_limits_i9xx_sdvo = {
179 .dot = { .min = 20000, .max = 400000 },
180 .vco = { .min = 1400000, .max = 2800000 },
181 .n = { .min = 1, .max = 6 },
182 .m = { .min = 70, .max = 120 },
183 .m1 = { .min = 8, .max = 18 },
184 .m2 = { .min = 3, .max = 7 },
185 .p = { .min = 5, .max = 80 },
186 .p1 = { .min = 1, .max = 8 },
187 .p2 = { .dot_limit = 200000,
188 .p2_slow = 10, .p2_fast = 5 },
189 };
190
191 static const intel_limit_t intel_limits_i9xx_lvds = {
192 .dot = { .min = 20000, .max = 400000 },
193 .vco = { .min = 1400000, .max = 2800000 },
194 .n = { .min = 1, .max = 6 },
195 .m = { .min = 70, .max = 120 },
196 .m1 = { .min = 8, .max = 18 },
197 .m2 = { .min = 3, .max = 7 },
198 .p = { .min = 7, .max = 98 },
199 .p1 = { .min = 1, .max = 8 },
200 .p2 = { .dot_limit = 112000,
201 .p2_slow = 14, .p2_fast = 7 },
202 };
203
204
205 static const intel_limit_t intel_limits_g4x_sdvo = {
206 .dot = { .min = 25000, .max = 270000 },
207 .vco = { .min = 1750000, .max = 3500000},
208 .n = { .min = 1, .max = 4 },
209 .m = { .min = 104, .max = 138 },
210 .m1 = { .min = 17, .max = 23 },
211 .m2 = { .min = 5, .max = 11 },
212 .p = { .min = 10, .max = 30 },
213 .p1 = { .min = 1, .max = 3},
214 .p2 = { .dot_limit = 270000,
215 .p2_slow = 10,
216 .p2_fast = 10
217 },
218 };
219
220 static const intel_limit_t intel_limits_g4x_hdmi = {
221 .dot = { .min = 22000, .max = 400000 },
222 .vco = { .min = 1750000, .max = 3500000},
223 .n = { .min = 1, .max = 4 },
224 .m = { .min = 104, .max = 138 },
225 .m1 = { .min = 16, .max = 23 },
226 .m2 = { .min = 5, .max = 11 },
227 .p = { .min = 5, .max = 80 },
228 .p1 = { .min = 1, .max = 8},
229 .p2 = { .dot_limit = 165000,
230 .p2_slow = 10, .p2_fast = 5 },
231 };
232
233 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
234 .dot = { .min = 20000, .max = 115000 },
235 .vco = { .min = 1750000, .max = 3500000 },
236 .n = { .min = 1, .max = 3 },
237 .m = { .min = 104, .max = 138 },
238 .m1 = { .min = 17, .max = 23 },
239 .m2 = { .min = 5, .max = 11 },
240 .p = { .min = 28, .max = 112 },
241 .p1 = { .min = 2, .max = 8 },
242 .p2 = { .dot_limit = 0,
243 .p2_slow = 14, .p2_fast = 14
244 },
245 };
246
247 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
248 .dot = { .min = 80000, .max = 224000 },
249 .vco = { .min = 1750000, .max = 3500000 },
250 .n = { .min = 1, .max = 3 },
251 .m = { .min = 104, .max = 138 },
252 .m1 = { .min = 17, .max = 23 },
253 .m2 = { .min = 5, .max = 11 },
254 .p = { .min = 14, .max = 42 },
255 .p1 = { .min = 2, .max = 6 },
256 .p2 = { .dot_limit = 0,
257 .p2_slow = 7, .p2_fast = 7
258 },
259 };
260
261 static const intel_limit_t intel_limits_pineview_sdvo = {
262 .dot = { .min = 20000, .max = 400000},
263 .vco = { .min = 1700000, .max = 3500000 },
264 /* Pineview's Ncounter is a ring counter */
265 .n = { .min = 3, .max = 6 },
266 .m = { .min = 2, .max = 256 },
267 /* Pineview only has one combined m divider, which we treat as m2. */
268 .m1 = { .min = 0, .max = 0 },
269 .m2 = { .min = 0, .max = 254 },
270 .p = { .min = 5, .max = 80 },
271 .p1 = { .min = 1, .max = 8 },
272 .p2 = { .dot_limit = 200000,
273 .p2_slow = 10, .p2_fast = 5 },
274 };
275
276 static const intel_limit_t intel_limits_pineview_lvds = {
277 .dot = { .min = 20000, .max = 400000 },
278 .vco = { .min = 1700000, .max = 3500000 },
279 .n = { .min = 3, .max = 6 },
280 .m = { .min = 2, .max = 256 },
281 .m1 = { .min = 0, .max = 0 },
282 .m2 = { .min = 0, .max = 254 },
283 .p = { .min = 7, .max = 112 },
284 .p1 = { .min = 1, .max = 8 },
285 .p2 = { .dot_limit = 112000,
286 .p2_slow = 14, .p2_fast = 14 },
287 };
288
289 /* Ironlake / Sandybridge
290 *
291 * We calculate clock using (register_value + 2) for N/M1/M2, so here
292 * the range value for them is (actual_value - 2).
293 */
294 static const intel_limit_t intel_limits_ironlake_dac = {
295 .dot = { .min = 25000, .max = 350000 },
296 .vco = { .min = 1760000, .max = 3510000 },
297 .n = { .min = 1, .max = 5 },
298 .m = { .min = 79, .max = 127 },
299 .m1 = { .min = 12, .max = 22 },
300 .m2 = { .min = 5, .max = 9 },
301 .p = { .min = 5, .max = 80 },
302 .p1 = { .min = 1, .max = 8 },
303 .p2 = { .dot_limit = 225000,
304 .p2_slow = 10, .p2_fast = 5 },
305 };
306
307 static const intel_limit_t intel_limits_ironlake_single_lvds = {
308 .dot = { .min = 25000, .max = 350000 },
309 .vco = { .min = 1760000, .max = 3510000 },
310 .n = { .min = 1, .max = 3 },
311 .m = { .min = 79, .max = 118 },
312 .m1 = { .min = 12, .max = 22 },
313 .m2 = { .min = 5, .max = 9 },
314 .p = { .min = 28, .max = 112 },
315 .p1 = { .min = 2, .max = 8 },
316 .p2 = { .dot_limit = 225000,
317 .p2_slow = 14, .p2_fast = 14 },
318 };
319
320 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 79, .max = 127 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 14, .max = 56 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 7, .p2_fast = 7 },
331 };
332
333 /* LVDS 100mhz refclk limits. */
334 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
335 .dot = { .min = 25000, .max = 350000 },
336 .vco = { .min = 1760000, .max = 3510000 },
337 .n = { .min = 1, .max = 2 },
338 .m = { .min = 79, .max = 126 },
339 .m1 = { .min = 12, .max = 22 },
340 .m2 = { .min = 5, .max = 9 },
341 .p = { .min = 28, .max = 112 },
342 .p1 = { .min = 2, .max = 8 },
343 .p2 = { .dot_limit = 225000,
344 .p2_slow = 14, .p2_fast = 14 },
345 };
346
347 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
348 .dot = { .min = 25000, .max = 350000 },
349 .vco = { .min = 1760000, .max = 3510000 },
350 .n = { .min = 1, .max = 3 },
351 .m = { .min = 79, .max = 126 },
352 .m1 = { .min = 12, .max = 22 },
353 .m2 = { .min = 5, .max = 9 },
354 .p = { .min = 14, .max = 42 },
355 .p1 = { .min = 2, .max = 6 },
356 .p2 = { .dot_limit = 225000,
357 .p2_slow = 7, .p2_fast = 7 },
358 };
359
360 static const intel_limit_t intel_limits_vlv = {
361 /*
362 * These are the data rate limits (measured in fast clocks)
363 * since those are the strictest limits we have. The fast
364 * clock and actual rate limits are more relaxed, so checking
365 * them would make no difference.
366 */
367 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
368 .vco = { .min = 4000000, .max = 6000000 },
369 .n = { .min = 1, .max = 7 },
370 .m1 = { .min = 2, .max = 3 },
371 .m2 = { .min = 11, .max = 156 },
372 .p1 = { .min = 2, .max = 3 },
373 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
374 };
375
376 static const intel_limit_t intel_limits_chv = {
377 /*
378 * These are the data rate limits (measured in fast clocks)
379 * since those are the strictest limits we have. The fast
380 * clock and actual rate limits are more relaxed, so checking
381 * them would make no difference.
382 */
383 .dot = { .min = 25000 * 5, .max = 540000 * 5},
384 .vco = { .min = 4860000, .max = 6700000 },
385 .n = { .min = 1, .max = 1 },
386 .m1 = { .min = 2, .max = 2 },
387 .m2 = { .min = 24 << 22, .max = 175 << 22 },
388 .p1 = { .min = 2, .max = 4 },
389 .p2 = { .p2_slow = 1, .p2_fast = 14 },
390 };
391
392 static void vlv_clock(int refclk, intel_clock_t *clock)
393 {
394 clock->m = clock->m1 * clock->m2;
395 clock->p = clock->p1 * clock->p2;
396 if (WARN_ON(clock->n == 0 || clock->p == 0))
397 return;
398 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
399 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
400 }
401
402 /**
403 * Returns whether any output on the specified pipe is of the specified type
404 */
405 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
406 {
407 struct drm_device *dev = crtc->dev;
408 struct intel_encoder *encoder;
409
410 for_each_encoder_on_crtc(dev, crtc, encoder)
411 if (encoder->type == type)
412 return true;
413
414 return false;
415 }
416
417 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
418 int refclk)
419 {
420 struct drm_device *dev = crtc->dev;
421 const intel_limit_t *limit;
422
423 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
424 if (intel_is_dual_link_lvds(dev)) {
425 if (refclk == 100000)
426 limit = &intel_limits_ironlake_dual_lvds_100m;
427 else
428 limit = &intel_limits_ironlake_dual_lvds;
429 } else {
430 if (refclk == 100000)
431 limit = &intel_limits_ironlake_single_lvds_100m;
432 else
433 limit = &intel_limits_ironlake_single_lvds;
434 }
435 } else
436 limit = &intel_limits_ironlake_dac;
437
438 return limit;
439 }
440
441 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
442 {
443 struct drm_device *dev = crtc->dev;
444 const intel_limit_t *limit;
445
446 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
447 if (intel_is_dual_link_lvds(dev))
448 limit = &intel_limits_g4x_dual_channel_lvds;
449 else
450 limit = &intel_limits_g4x_single_channel_lvds;
451 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
452 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
453 limit = &intel_limits_g4x_hdmi;
454 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
455 limit = &intel_limits_g4x_sdvo;
456 } else /* The option is for other outputs */
457 limit = &intel_limits_i9xx_sdvo;
458
459 return limit;
460 }
461
462 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
463 {
464 struct drm_device *dev = crtc->dev;
465 const intel_limit_t *limit;
466
467 if (HAS_PCH_SPLIT(dev))
468 limit = intel_ironlake_limit(crtc, refclk);
469 else if (IS_G4X(dev)) {
470 limit = intel_g4x_limit(crtc);
471 } else if (IS_PINEVIEW(dev)) {
472 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
473 limit = &intel_limits_pineview_lvds;
474 else
475 limit = &intel_limits_pineview_sdvo;
476 } else if (IS_CHERRYVIEW(dev)) {
477 limit = &intel_limits_chv;
478 } else if (IS_VALLEYVIEW(dev)) {
479 limit = &intel_limits_vlv;
480 } else if (!IS_GEN2(dev)) {
481 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
482 limit = &intel_limits_i9xx_lvds;
483 else
484 limit = &intel_limits_i9xx_sdvo;
485 } else {
486 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
487 limit = &intel_limits_i8xx_lvds;
488 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
489 limit = &intel_limits_i8xx_dvo;
490 else
491 limit = &intel_limits_i8xx_dac;
492 }
493 return limit;
494 }
495
496 /* m1 is reserved as 0 in Pineview, n is a ring counter */
497 static void pineview_clock(int refclk, intel_clock_t *clock)
498 {
499 clock->m = clock->m2 + 2;
500 clock->p = clock->p1 * clock->p2;
501 if (WARN_ON(clock->n == 0 || clock->p == 0))
502 return;
503 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
504 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
505 }
506
507 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
508 {
509 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
510 }
511
512 static void i9xx_clock(int refclk, intel_clock_t *clock)
513 {
514 clock->m = i9xx_dpll_compute_m(clock);
515 clock->p = clock->p1 * clock->p2;
516 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
517 return;
518 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
519 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
520 }
521
522 static void chv_clock(int refclk, intel_clock_t *clock)
523 {
524 clock->m = clock->m1 * clock->m2;
525 clock->p = clock->p1 * clock->p2;
526 if (WARN_ON(clock->n == 0 || clock->p == 0))
527 return;
528 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
529 clock->n << 22);
530 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
531 }
532
533 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
534 /**
535 * Returns whether the given set of divisors are valid for a given refclk with
536 * the given connectors.
537 */
538
539 static bool intel_PLL_is_valid(struct drm_device *dev,
540 const intel_limit_t *limit,
541 const intel_clock_t *clock)
542 {
543 if (clock->n < limit->n.min || limit->n.max < clock->n)
544 INTELPllInvalid("n out of range\n");
545 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
546 INTELPllInvalid("p1 out of range\n");
547 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
548 INTELPllInvalid("m2 out of range\n");
549 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
550 INTELPllInvalid("m1 out of range\n");
551
552 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
553 if (clock->m1 <= clock->m2)
554 INTELPllInvalid("m1 <= m2\n");
555
556 if (!IS_VALLEYVIEW(dev)) {
557 if (clock->p < limit->p.min || limit->p.max < clock->p)
558 INTELPllInvalid("p out of range\n");
559 if (clock->m < limit->m.min || limit->m.max < clock->m)
560 INTELPllInvalid("m out of range\n");
561 }
562
563 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
564 INTELPllInvalid("vco out of range\n");
565 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
566 * connector, etc., rather than just a single range.
567 */
568 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
569 INTELPllInvalid("dot out of range\n");
570
571 return true;
572 }
573
574 static bool
575 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
576 int target, int refclk, intel_clock_t *match_clock,
577 intel_clock_t *best_clock)
578 {
579 struct drm_device *dev = crtc->dev;
580 intel_clock_t clock;
581 int err = target;
582
583 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
584 /*
585 * For LVDS just rely on its current settings for dual-channel.
586 * We haven't figured out how to reliably set up different
587 * single/dual channel state, if we even can.
588 */
589 if (intel_is_dual_link_lvds(dev))
590 clock.p2 = limit->p2.p2_fast;
591 else
592 clock.p2 = limit->p2.p2_slow;
593 } else {
594 if (target < limit->p2.dot_limit)
595 clock.p2 = limit->p2.p2_slow;
596 else
597 clock.p2 = limit->p2.p2_fast;
598 }
599
600 memset(best_clock, 0, sizeof(*best_clock));
601
602 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
603 clock.m1++) {
604 for (clock.m2 = limit->m2.min;
605 clock.m2 <= limit->m2.max; clock.m2++) {
606 if (clock.m2 >= clock.m1)
607 break;
608 for (clock.n = limit->n.min;
609 clock.n <= limit->n.max; clock.n++) {
610 for (clock.p1 = limit->p1.min;
611 clock.p1 <= limit->p1.max; clock.p1++) {
612 int this_err;
613
614 i9xx_clock(refclk, &clock);
615 if (!intel_PLL_is_valid(dev, limit,
616 &clock))
617 continue;
618 if (match_clock &&
619 clock.p != match_clock->p)
620 continue;
621
622 this_err = abs(clock.dot - target);
623 if (this_err < err) {
624 *best_clock = clock;
625 err = this_err;
626 }
627 }
628 }
629 }
630 }
631
632 return (err != target);
633 }
634
635 static bool
636 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
637 int target, int refclk, intel_clock_t *match_clock,
638 intel_clock_t *best_clock)
639 {
640 struct drm_device *dev = crtc->dev;
641 intel_clock_t clock;
642 int err = target;
643
644 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
645 /*
646 * For LVDS just rely on its current settings for dual-channel.
647 * We haven't figured out how to reliably set up different
648 * single/dual channel state, if we even can.
649 */
650 if (intel_is_dual_link_lvds(dev))
651 clock.p2 = limit->p2.p2_fast;
652 else
653 clock.p2 = limit->p2.p2_slow;
654 } else {
655 if (target < limit->p2.dot_limit)
656 clock.p2 = limit->p2.p2_slow;
657 else
658 clock.p2 = limit->p2.p2_fast;
659 }
660
661 memset(best_clock, 0, sizeof(*best_clock));
662
663 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
664 clock.m1++) {
665 for (clock.m2 = limit->m2.min;
666 clock.m2 <= limit->m2.max; clock.m2++) {
667 for (clock.n = limit->n.min;
668 clock.n <= limit->n.max; clock.n++) {
669 for (clock.p1 = limit->p1.min;
670 clock.p1 <= limit->p1.max; clock.p1++) {
671 int this_err;
672
673 pineview_clock(refclk, &clock);
674 if (!intel_PLL_is_valid(dev, limit,
675 &clock))
676 continue;
677 if (match_clock &&
678 clock.p != match_clock->p)
679 continue;
680
681 this_err = abs(clock.dot - target);
682 if (this_err < err) {
683 *best_clock = clock;
684 err = this_err;
685 }
686 }
687 }
688 }
689 }
690
691 return (err != target);
692 }
693
694 static bool
695 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
696 int target, int refclk, intel_clock_t *match_clock,
697 intel_clock_t *best_clock)
698 {
699 struct drm_device *dev = crtc->dev;
700 intel_clock_t clock;
701 int max_n;
702 bool found;
703 /* approximately equals target * 0.00585 */
704 int err_most = (target >> 8) + (target >> 9);
705 found = false;
706
707 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
708 if (intel_is_dual_link_lvds(dev))
709 clock.p2 = limit->p2.p2_fast;
710 else
711 clock.p2 = limit->p2.p2_slow;
712 } else {
713 if (target < limit->p2.dot_limit)
714 clock.p2 = limit->p2.p2_slow;
715 else
716 clock.p2 = limit->p2.p2_fast;
717 }
718
719 memset(best_clock, 0, sizeof(*best_clock));
720 max_n = limit->n.max;
721 /* based on hardware requirement, prefer smaller n to precision */
722 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
723 /* based on hardware requirement, prefere larger m1,m2 */
724 for (clock.m1 = limit->m1.max;
725 clock.m1 >= limit->m1.min; clock.m1--) {
726 for (clock.m2 = limit->m2.max;
727 clock.m2 >= limit->m2.min; clock.m2--) {
728 for (clock.p1 = limit->p1.max;
729 clock.p1 >= limit->p1.min; clock.p1--) {
730 int this_err;
731
732 i9xx_clock(refclk, &clock);
733 if (!intel_PLL_is_valid(dev, limit,
734 &clock))
735 continue;
736
737 this_err = abs(clock.dot - target);
738 if (this_err < err_most) {
739 *best_clock = clock;
740 err_most = this_err;
741 max_n = clock.n;
742 found = true;
743 }
744 }
745 }
746 }
747 }
748 return found;
749 }
750
751 static bool
752 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
753 int target, int refclk, intel_clock_t *match_clock,
754 intel_clock_t *best_clock)
755 {
756 struct drm_device *dev = crtc->dev;
757 intel_clock_t clock;
758 unsigned int bestppm = 1000000;
759 /* min update 19.2 MHz */
760 int max_n = min(limit->n.max, refclk / 19200);
761 bool found = false;
762
763 target *= 5; /* fast clock */
764
765 memset(best_clock, 0, sizeof(*best_clock));
766
767 /* based on hardware requirement, prefer smaller n to precision */
768 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
769 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
770 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
771 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
772 clock.p = clock.p1 * clock.p2;
773 /* based on hardware requirement, prefer bigger m1,m2 values */
774 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
775 unsigned int ppm, diff;
776
777 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
778 refclk * clock.m1);
779
780 vlv_clock(refclk, &clock);
781
782 if (!intel_PLL_is_valid(dev, limit,
783 &clock))
784 continue;
785
786 diff = abs(clock.dot - target);
787 ppm = div_u64(1000000ULL * diff, target);
788
789 if (ppm < 100 && clock.p > best_clock->p) {
790 bestppm = 0;
791 *best_clock = clock;
792 found = true;
793 }
794
795 if (bestppm >= 10 && ppm < bestppm - 10) {
796 bestppm = ppm;
797 *best_clock = clock;
798 found = true;
799 }
800 }
801 }
802 }
803 }
804
805 return found;
806 }
807
808 static bool
809 chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
810 int target, int refclk, intel_clock_t *match_clock,
811 intel_clock_t *best_clock)
812 {
813 struct drm_device *dev = crtc->dev;
814 intel_clock_t clock;
815 uint64_t m2;
816 int found = false;
817
818 memset(best_clock, 0, sizeof(*best_clock));
819
820 /*
821 * Based on hardware doc, the n always set to 1, and m1 always
822 * set to 2. If requires to support 200Mhz refclk, we need to
823 * revisit this because n may not 1 anymore.
824 */
825 clock.n = 1, clock.m1 = 2;
826 target *= 5; /* fast clock */
827
828 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
829 for (clock.p2 = limit->p2.p2_fast;
830 clock.p2 >= limit->p2.p2_slow;
831 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
832
833 clock.p = clock.p1 * clock.p2;
834
835 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
836 clock.n) << 22, refclk * clock.m1);
837
838 if (m2 > INT_MAX/clock.m1)
839 continue;
840
841 clock.m2 = m2;
842
843 chv_clock(refclk, &clock);
844
845 if (!intel_PLL_is_valid(dev, limit, &clock))
846 continue;
847
848 /* based on hardware requirement, prefer bigger p
849 */
850 if (clock.p > best_clock->p) {
851 *best_clock = clock;
852 found = true;
853 }
854 }
855 }
856
857 return found;
858 }
859
860 bool intel_crtc_active(struct drm_crtc *crtc)
861 {
862 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
863
864 /* Be paranoid as we can arrive here with only partial
865 * state retrieved from the hardware during setup.
866 *
867 * We can ditch the adjusted_mode.crtc_clock check as soon
868 * as Haswell has gained clock readout/fastboot support.
869 *
870 * We can ditch the crtc->primary->fb check as soon as we can
871 * properly reconstruct framebuffers.
872 */
873 return intel_crtc->active && crtc->primary->fb &&
874 intel_crtc->config.adjusted_mode.crtc_clock;
875 }
876
877 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
878 enum pipe pipe)
879 {
880 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
881 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
882
883 return intel_crtc->config.cpu_transcoder;
884 }
885
886 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
887 {
888 struct drm_i915_private *dev_priv = dev->dev_private;
889 u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
890
891 frame = I915_READ(frame_reg);
892
893 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
894 WARN(1, "vblank wait timed out\n");
895 }
896
897 /**
898 * intel_wait_for_vblank - wait for vblank on a given pipe
899 * @dev: drm device
900 * @pipe: pipe to wait for
901 *
902 * Wait for vblank to occur on a given pipe. Needed for various bits of
903 * mode setting code.
904 */
905 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
906 {
907 struct drm_i915_private *dev_priv = dev->dev_private;
908 int pipestat_reg = PIPESTAT(pipe);
909
910 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
911 g4x_wait_for_vblank(dev, pipe);
912 return;
913 }
914
915 /* Clear existing vblank status. Note this will clear any other
916 * sticky status fields as well.
917 *
918 * This races with i915_driver_irq_handler() with the result
919 * that either function could miss a vblank event. Here it is not
920 * fatal, as we will either wait upon the next vblank interrupt or
921 * timeout. Generally speaking intel_wait_for_vblank() is only
922 * called during modeset at which time the GPU should be idle and
923 * should *not* be performing page flips and thus not waiting on
924 * vblanks...
925 * Currently, the result of us stealing a vblank from the irq
926 * handler is that a single frame will be skipped during swapbuffers.
927 */
928 I915_WRITE(pipestat_reg,
929 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
930
931 /* Wait for vblank interrupt bit to set */
932 if (wait_for(I915_READ(pipestat_reg) &
933 PIPE_VBLANK_INTERRUPT_STATUS,
934 50))
935 DRM_DEBUG_KMS("vblank wait timed out\n");
936 }
937
938 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
939 {
940 struct drm_i915_private *dev_priv = dev->dev_private;
941 u32 reg = PIPEDSL(pipe);
942 u32 line1, line2;
943 u32 line_mask;
944
945 if (IS_GEN2(dev))
946 line_mask = DSL_LINEMASK_GEN2;
947 else
948 line_mask = DSL_LINEMASK_GEN3;
949
950 line1 = I915_READ(reg) & line_mask;
951 mdelay(5);
952 line2 = I915_READ(reg) & line_mask;
953
954 return line1 == line2;
955 }
956
957 /*
958 * intel_wait_for_pipe_off - wait for pipe to turn off
959 * @dev: drm device
960 * @pipe: pipe to wait for
961 *
962 * After disabling a pipe, we can't wait for vblank in the usual way,
963 * spinning on the vblank interrupt status bit, since we won't actually
964 * see an interrupt when the pipe is disabled.
965 *
966 * On Gen4 and above:
967 * wait for the pipe register state bit to turn off
968 *
969 * Otherwise:
970 * wait for the display line value to settle (it usually
971 * ends up stopping at the start of the next frame).
972 *
973 */
974 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
975 {
976 struct drm_i915_private *dev_priv = dev->dev_private;
977 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
978 pipe);
979
980 if (INTEL_INFO(dev)->gen >= 4) {
981 int reg = PIPECONF(cpu_transcoder);
982
983 /* Wait for the Pipe State to go off */
984 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
985 100))
986 WARN(1, "pipe_off wait timed out\n");
987 } else {
988 /* Wait for the display line to settle */
989 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
990 WARN(1, "pipe_off wait timed out\n");
991 }
992 }
993
994 /*
995 * ibx_digital_port_connected - is the specified port connected?
996 * @dev_priv: i915 private structure
997 * @port: the port to test
998 *
999 * Returns true if @port is connected, false otherwise.
1000 */
1001 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1002 struct intel_digital_port *port)
1003 {
1004 u32 bit;
1005
1006 if (HAS_PCH_IBX(dev_priv->dev)) {
1007 switch (port->port) {
1008 case PORT_B:
1009 bit = SDE_PORTB_HOTPLUG;
1010 break;
1011 case PORT_C:
1012 bit = SDE_PORTC_HOTPLUG;
1013 break;
1014 case PORT_D:
1015 bit = SDE_PORTD_HOTPLUG;
1016 break;
1017 default:
1018 return true;
1019 }
1020 } else {
1021 switch (port->port) {
1022 case PORT_B:
1023 bit = SDE_PORTB_HOTPLUG_CPT;
1024 break;
1025 case PORT_C:
1026 bit = SDE_PORTC_HOTPLUG_CPT;
1027 break;
1028 case PORT_D:
1029 bit = SDE_PORTD_HOTPLUG_CPT;
1030 break;
1031 default:
1032 return true;
1033 }
1034 }
1035
1036 return I915_READ(SDEISR) & bit;
1037 }
1038
1039 static const char *state_string(bool enabled)
1040 {
1041 return enabled ? "on" : "off";
1042 }
1043
1044 /* Only for pre-ILK configs */
1045 void assert_pll(struct drm_i915_private *dev_priv,
1046 enum pipe pipe, bool state)
1047 {
1048 int reg;
1049 u32 val;
1050 bool cur_state;
1051
1052 reg = DPLL(pipe);
1053 val = I915_READ(reg);
1054 cur_state = !!(val & DPLL_VCO_ENABLE);
1055 WARN(cur_state != state,
1056 "PLL state assertion failure (expected %s, current %s)\n",
1057 state_string(state), state_string(cur_state));
1058 }
1059
1060 /* XXX: the dsi pll is shared between MIPI DSI ports */
1061 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1062 {
1063 u32 val;
1064 bool cur_state;
1065
1066 mutex_lock(&dev_priv->dpio_lock);
1067 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1068 mutex_unlock(&dev_priv->dpio_lock);
1069
1070 cur_state = val & DSI_PLL_VCO_EN;
1071 WARN(cur_state != state,
1072 "DSI PLL state assertion failure (expected %s, current %s)\n",
1073 state_string(state), state_string(cur_state));
1074 }
1075 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1076 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1077
1078 struct intel_shared_dpll *
1079 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1080 {
1081 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1082
1083 if (crtc->config.shared_dpll < 0)
1084 return NULL;
1085
1086 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1087 }
1088
1089 /* For ILK+ */
1090 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1091 struct intel_shared_dpll *pll,
1092 bool state)
1093 {
1094 bool cur_state;
1095 struct intel_dpll_hw_state hw_state;
1096
1097 if (HAS_PCH_LPT(dev_priv->dev)) {
1098 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1099 return;
1100 }
1101
1102 if (WARN (!pll,
1103 "asserting DPLL %s with no DPLL\n", state_string(state)))
1104 return;
1105
1106 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1107 WARN(cur_state != state,
1108 "%s assertion failure (expected %s, current %s)\n",
1109 pll->name, state_string(state), state_string(cur_state));
1110 }
1111
1112 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1113 enum pipe pipe, bool state)
1114 {
1115 int reg;
1116 u32 val;
1117 bool cur_state;
1118 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1119 pipe);
1120
1121 if (HAS_DDI(dev_priv->dev)) {
1122 /* DDI does not have a specific FDI_TX register */
1123 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1124 val = I915_READ(reg);
1125 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1126 } else {
1127 reg = FDI_TX_CTL(pipe);
1128 val = I915_READ(reg);
1129 cur_state = !!(val & FDI_TX_ENABLE);
1130 }
1131 WARN(cur_state != state,
1132 "FDI TX state assertion failure (expected %s, current %s)\n",
1133 state_string(state), state_string(cur_state));
1134 }
1135 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1136 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1137
1138 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1139 enum pipe pipe, bool state)
1140 {
1141 int reg;
1142 u32 val;
1143 bool cur_state;
1144
1145 reg = FDI_RX_CTL(pipe);
1146 val = I915_READ(reg);
1147 cur_state = !!(val & FDI_RX_ENABLE);
1148 WARN(cur_state != state,
1149 "FDI RX state assertion failure (expected %s, current %s)\n",
1150 state_string(state), state_string(cur_state));
1151 }
1152 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1153 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1154
1155 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1156 enum pipe pipe)
1157 {
1158 int reg;
1159 u32 val;
1160
1161 /* ILK FDI PLL is always enabled */
1162 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1163 return;
1164
1165 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1166 if (HAS_DDI(dev_priv->dev))
1167 return;
1168
1169 reg = FDI_TX_CTL(pipe);
1170 val = I915_READ(reg);
1171 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1172 }
1173
1174 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1175 enum pipe pipe, bool state)
1176 {
1177 int reg;
1178 u32 val;
1179 bool cur_state;
1180
1181 reg = FDI_RX_CTL(pipe);
1182 val = I915_READ(reg);
1183 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1184 WARN(cur_state != state,
1185 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1186 state_string(state), state_string(cur_state));
1187 }
1188
1189 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1190 enum pipe pipe)
1191 {
1192 int pp_reg, lvds_reg;
1193 u32 val;
1194 enum pipe panel_pipe = PIPE_A;
1195 bool locked = true;
1196
1197 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1198 pp_reg = PCH_PP_CONTROL;
1199 lvds_reg = PCH_LVDS;
1200 } else {
1201 pp_reg = PP_CONTROL;
1202 lvds_reg = LVDS;
1203 }
1204
1205 val = I915_READ(pp_reg);
1206 if (!(val & PANEL_POWER_ON) ||
1207 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1208 locked = false;
1209
1210 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1211 panel_pipe = PIPE_B;
1212
1213 WARN(panel_pipe == pipe && locked,
1214 "panel assertion failure, pipe %c regs locked\n",
1215 pipe_name(pipe));
1216 }
1217
1218 static void assert_cursor(struct drm_i915_private *dev_priv,
1219 enum pipe pipe, bool state)
1220 {
1221 struct drm_device *dev = dev_priv->dev;
1222 bool cur_state;
1223
1224 if (IS_845G(dev) || IS_I865G(dev))
1225 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1226 else
1227 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1228
1229 WARN(cur_state != state,
1230 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1231 pipe_name(pipe), state_string(state), state_string(cur_state));
1232 }
1233 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1234 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1235
1236 void assert_pipe(struct drm_i915_private *dev_priv,
1237 enum pipe pipe, bool state)
1238 {
1239 int reg;
1240 u32 val;
1241 bool cur_state;
1242 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1243 pipe);
1244
1245 /* if we need the pipe A quirk it must be always on */
1246 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1247 state = true;
1248
1249 if (!intel_display_power_enabled(dev_priv,
1250 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1251 cur_state = false;
1252 } else {
1253 reg = PIPECONF(cpu_transcoder);
1254 val = I915_READ(reg);
1255 cur_state = !!(val & PIPECONF_ENABLE);
1256 }
1257
1258 WARN(cur_state != state,
1259 "pipe %c assertion failure (expected %s, current %s)\n",
1260 pipe_name(pipe), state_string(state), state_string(cur_state));
1261 }
1262
1263 static void assert_plane(struct drm_i915_private *dev_priv,
1264 enum plane plane, bool state)
1265 {
1266 int reg;
1267 u32 val;
1268 bool cur_state;
1269
1270 reg = DSPCNTR(plane);
1271 val = I915_READ(reg);
1272 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1273 WARN(cur_state != state,
1274 "plane %c assertion failure (expected %s, current %s)\n",
1275 plane_name(plane), state_string(state), state_string(cur_state));
1276 }
1277
1278 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1279 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1280
1281 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1282 enum pipe pipe)
1283 {
1284 struct drm_device *dev = dev_priv->dev;
1285 int reg, i;
1286 u32 val;
1287 int cur_pipe;
1288
1289 /* Primary planes are fixed to pipes on gen4+ */
1290 if (INTEL_INFO(dev)->gen >= 4) {
1291 reg = DSPCNTR(pipe);
1292 val = I915_READ(reg);
1293 WARN(val & DISPLAY_PLANE_ENABLE,
1294 "plane %c assertion failure, should be disabled but not\n",
1295 plane_name(pipe));
1296 return;
1297 }
1298
1299 /* Need to check both planes against the pipe */
1300 for_each_pipe(i) {
1301 reg = DSPCNTR(i);
1302 val = I915_READ(reg);
1303 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1304 DISPPLANE_SEL_PIPE_SHIFT;
1305 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1306 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1307 plane_name(i), pipe_name(pipe));
1308 }
1309 }
1310
1311 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1312 enum pipe pipe)
1313 {
1314 struct drm_device *dev = dev_priv->dev;
1315 int reg, sprite;
1316 u32 val;
1317
1318 if (IS_VALLEYVIEW(dev)) {
1319 for_each_sprite(pipe, sprite) {
1320 reg = SPCNTR(pipe, sprite);
1321 val = I915_READ(reg);
1322 WARN(val & SP_ENABLE,
1323 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1324 sprite_name(pipe, sprite), pipe_name(pipe));
1325 }
1326 } else if (INTEL_INFO(dev)->gen >= 7) {
1327 reg = SPRCTL(pipe);
1328 val = I915_READ(reg);
1329 WARN(val & SPRITE_ENABLE,
1330 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1331 plane_name(pipe), pipe_name(pipe));
1332 } else if (INTEL_INFO(dev)->gen >= 5) {
1333 reg = DVSCNTR(pipe);
1334 val = I915_READ(reg);
1335 WARN(val & DVS_ENABLE,
1336 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1337 plane_name(pipe), pipe_name(pipe));
1338 }
1339 }
1340
1341 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1342 {
1343 u32 val;
1344 bool enabled;
1345
1346 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1347
1348 val = I915_READ(PCH_DREF_CONTROL);
1349 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1350 DREF_SUPERSPREAD_SOURCE_MASK));
1351 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1352 }
1353
1354 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1355 enum pipe pipe)
1356 {
1357 int reg;
1358 u32 val;
1359 bool enabled;
1360
1361 reg = PCH_TRANSCONF(pipe);
1362 val = I915_READ(reg);
1363 enabled = !!(val & TRANS_ENABLE);
1364 WARN(enabled,
1365 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1366 pipe_name(pipe));
1367 }
1368
1369 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1370 enum pipe pipe, u32 port_sel, u32 val)
1371 {
1372 if ((val & DP_PORT_EN) == 0)
1373 return false;
1374
1375 if (HAS_PCH_CPT(dev_priv->dev)) {
1376 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1377 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1378 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1379 return false;
1380 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1381 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1382 return false;
1383 } else {
1384 if ((val & DP_PIPE_MASK) != (pipe << 30))
1385 return false;
1386 }
1387 return true;
1388 }
1389
1390 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1391 enum pipe pipe, u32 val)
1392 {
1393 if ((val & SDVO_ENABLE) == 0)
1394 return false;
1395
1396 if (HAS_PCH_CPT(dev_priv->dev)) {
1397 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1398 return false;
1399 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1400 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1401 return false;
1402 } else {
1403 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1404 return false;
1405 }
1406 return true;
1407 }
1408
1409 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1410 enum pipe pipe, u32 val)
1411 {
1412 if ((val & LVDS_PORT_EN) == 0)
1413 return false;
1414
1415 if (HAS_PCH_CPT(dev_priv->dev)) {
1416 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1417 return false;
1418 } else {
1419 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1420 return false;
1421 }
1422 return true;
1423 }
1424
1425 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1426 enum pipe pipe, u32 val)
1427 {
1428 if ((val & ADPA_DAC_ENABLE) == 0)
1429 return false;
1430 if (HAS_PCH_CPT(dev_priv->dev)) {
1431 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1432 return false;
1433 } else {
1434 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1435 return false;
1436 }
1437 return true;
1438 }
1439
1440 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1441 enum pipe pipe, int reg, u32 port_sel)
1442 {
1443 u32 val = I915_READ(reg);
1444 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1445 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1446 reg, pipe_name(pipe));
1447
1448 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1449 && (val & DP_PIPEB_SELECT),
1450 "IBX PCH dp port still using transcoder B\n");
1451 }
1452
1453 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1454 enum pipe pipe, int reg)
1455 {
1456 u32 val = I915_READ(reg);
1457 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1458 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1459 reg, pipe_name(pipe));
1460
1461 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1462 && (val & SDVO_PIPE_B_SELECT),
1463 "IBX PCH hdmi port still using transcoder B\n");
1464 }
1465
1466 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1467 enum pipe pipe)
1468 {
1469 int reg;
1470 u32 val;
1471
1472 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1473 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1474 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1475
1476 reg = PCH_ADPA;
1477 val = I915_READ(reg);
1478 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1479 "PCH VGA enabled on transcoder %c, should be disabled\n",
1480 pipe_name(pipe));
1481
1482 reg = PCH_LVDS;
1483 val = I915_READ(reg);
1484 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1485 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1486 pipe_name(pipe));
1487
1488 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1489 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1490 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1491 }
1492
1493 static void intel_init_dpio(struct drm_device *dev)
1494 {
1495 struct drm_i915_private *dev_priv = dev->dev_private;
1496
1497 if (!IS_VALLEYVIEW(dev))
1498 return;
1499
1500 /*
1501 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1502 * CHV x1 PHY (DP/HDMI D)
1503 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1504 */
1505 if (IS_CHERRYVIEW(dev)) {
1506 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1507 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1508 } else {
1509 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1510 }
1511 }
1512
1513 static void intel_reset_dpio(struct drm_device *dev)
1514 {
1515 struct drm_i915_private *dev_priv = dev->dev_private;
1516
1517 if (IS_CHERRYVIEW(dev)) {
1518 enum dpio_phy phy;
1519 u32 val;
1520
1521 for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) {
1522 /* Poll for phypwrgood signal */
1523 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) &
1524 PHY_POWERGOOD(phy), 1))
1525 DRM_ERROR("Display PHY %d is not power up\n", phy);
1526
1527 /*
1528 * Deassert common lane reset for PHY.
1529 *
1530 * This should only be done on init and resume from S3
1531 * with both PLLs disabled, or we risk losing DPIO and
1532 * PLL synchronization.
1533 */
1534 val = I915_READ(DISPLAY_PHY_CONTROL);
1535 I915_WRITE(DISPLAY_PHY_CONTROL,
1536 PHY_COM_LANE_RESET_DEASSERT(phy, val));
1537 }
1538 }
1539 }
1540
1541 static void vlv_enable_pll(struct intel_crtc *crtc)
1542 {
1543 struct drm_device *dev = crtc->base.dev;
1544 struct drm_i915_private *dev_priv = dev->dev_private;
1545 int reg = DPLL(crtc->pipe);
1546 u32 dpll = crtc->config.dpll_hw_state.dpll;
1547
1548 assert_pipe_disabled(dev_priv, crtc->pipe);
1549
1550 /* No really, not for ILK+ */
1551 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1552
1553 /* PLL is protected by panel, make sure we can write it */
1554 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1555 assert_panel_unlocked(dev_priv, crtc->pipe);
1556
1557 I915_WRITE(reg, dpll);
1558 POSTING_READ(reg);
1559 udelay(150);
1560
1561 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1562 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1563
1564 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1565 POSTING_READ(DPLL_MD(crtc->pipe));
1566
1567 /* We do this three times for luck */
1568 I915_WRITE(reg, dpll);
1569 POSTING_READ(reg);
1570 udelay(150); /* wait for warmup */
1571 I915_WRITE(reg, dpll);
1572 POSTING_READ(reg);
1573 udelay(150); /* wait for warmup */
1574 I915_WRITE(reg, dpll);
1575 POSTING_READ(reg);
1576 udelay(150); /* wait for warmup */
1577 }
1578
1579 static void chv_enable_pll(struct intel_crtc *crtc)
1580 {
1581 struct drm_device *dev = crtc->base.dev;
1582 struct drm_i915_private *dev_priv = dev->dev_private;
1583 int pipe = crtc->pipe;
1584 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1585 u32 tmp;
1586
1587 assert_pipe_disabled(dev_priv, crtc->pipe);
1588
1589 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1590
1591 mutex_lock(&dev_priv->dpio_lock);
1592
1593 /* Enable back the 10bit clock to display controller */
1594 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1595 tmp |= DPIO_DCLKP_EN;
1596 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1597
1598 /*
1599 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1600 */
1601 udelay(1);
1602
1603 /* Enable PLL */
1604 I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
1605
1606 /* Check PLL is locked */
1607 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1608 DRM_ERROR("PLL %d failed to lock\n", pipe);
1609
1610 /* not sure when this should be written */
1611 I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
1612 POSTING_READ(DPLL_MD(pipe));
1613
1614 mutex_unlock(&dev_priv->dpio_lock);
1615 }
1616
1617 static void i9xx_enable_pll(struct intel_crtc *crtc)
1618 {
1619 struct drm_device *dev = crtc->base.dev;
1620 struct drm_i915_private *dev_priv = dev->dev_private;
1621 int reg = DPLL(crtc->pipe);
1622 u32 dpll = crtc->config.dpll_hw_state.dpll;
1623
1624 assert_pipe_disabled(dev_priv, crtc->pipe);
1625
1626 /* No really, not for ILK+ */
1627 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1628
1629 /* PLL is protected by panel, make sure we can write it */
1630 if (IS_MOBILE(dev) && !IS_I830(dev))
1631 assert_panel_unlocked(dev_priv, crtc->pipe);
1632
1633 I915_WRITE(reg, dpll);
1634
1635 /* Wait for the clocks to stabilize. */
1636 POSTING_READ(reg);
1637 udelay(150);
1638
1639 if (INTEL_INFO(dev)->gen >= 4) {
1640 I915_WRITE(DPLL_MD(crtc->pipe),
1641 crtc->config.dpll_hw_state.dpll_md);
1642 } else {
1643 /* The pixel multiplier can only be updated once the
1644 * DPLL is enabled and the clocks are stable.
1645 *
1646 * So write it again.
1647 */
1648 I915_WRITE(reg, dpll);
1649 }
1650
1651 /* We do this three times for luck */
1652 I915_WRITE(reg, dpll);
1653 POSTING_READ(reg);
1654 udelay(150); /* wait for warmup */
1655 I915_WRITE(reg, dpll);
1656 POSTING_READ(reg);
1657 udelay(150); /* wait for warmup */
1658 I915_WRITE(reg, dpll);
1659 POSTING_READ(reg);
1660 udelay(150); /* wait for warmup */
1661 }
1662
1663 /**
1664 * i9xx_disable_pll - disable a PLL
1665 * @dev_priv: i915 private structure
1666 * @pipe: pipe PLL to disable
1667 *
1668 * Disable the PLL for @pipe, making sure the pipe is off first.
1669 *
1670 * Note! This is for pre-ILK only.
1671 */
1672 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1673 {
1674 /* Don't disable pipe A or pipe A PLLs if needed */
1675 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1676 return;
1677
1678 /* Make sure the pipe isn't still relying on us */
1679 assert_pipe_disabled(dev_priv, pipe);
1680
1681 I915_WRITE(DPLL(pipe), 0);
1682 POSTING_READ(DPLL(pipe));
1683 }
1684
1685 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1686 {
1687 u32 val = 0;
1688
1689 /* Make sure the pipe isn't still relying on us */
1690 assert_pipe_disabled(dev_priv, pipe);
1691
1692 /*
1693 * Leave integrated clock source and reference clock enabled for pipe B.
1694 * The latter is needed for VGA hotplug / manual detection.
1695 */
1696 if (pipe == PIPE_B)
1697 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1698 I915_WRITE(DPLL(pipe), val);
1699 POSTING_READ(DPLL(pipe));
1700
1701 }
1702
1703 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1704 {
1705 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1706 u32 val;
1707
1708 /* Make sure the pipe isn't still relying on us */
1709 assert_pipe_disabled(dev_priv, pipe);
1710
1711 /* Set PLL en = 0 */
1712 val = DPLL_SSC_REF_CLOCK_CHV;
1713 if (pipe != PIPE_A)
1714 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1715 I915_WRITE(DPLL(pipe), val);
1716 POSTING_READ(DPLL(pipe));
1717
1718 mutex_lock(&dev_priv->dpio_lock);
1719
1720 /* Disable 10bit clock to display controller */
1721 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1722 val &= ~DPIO_DCLKP_EN;
1723 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1724
1725 /* disable left/right clock distribution */
1726 if (pipe != PIPE_B) {
1727 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1728 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1729 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1730 } else {
1731 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1732 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1733 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1734 }
1735
1736 mutex_unlock(&dev_priv->dpio_lock);
1737 }
1738
1739 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1740 struct intel_digital_port *dport)
1741 {
1742 u32 port_mask;
1743 int dpll_reg;
1744
1745 switch (dport->port) {
1746 case PORT_B:
1747 port_mask = DPLL_PORTB_READY_MASK;
1748 dpll_reg = DPLL(0);
1749 break;
1750 case PORT_C:
1751 port_mask = DPLL_PORTC_READY_MASK;
1752 dpll_reg = DPLL(0);
1753 break;
1754 case PORT_D:
1755 port_mask = DPLL_PORTD_READY_MASK;
1756 dpll_reg = DPIO_PHY_STATUS;
1757 break;
1758 default:
1759 BUG();
1760 }
1761
1762 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1763 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1764 port_name(dport->port), I915_READ(dpll_reg));
1765 }
1766
1767 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1768 {
1769 struct drm_device *dev = crtc->base.dev;
1770 struct drm_i915_private *dev_priv = dev->dev_private;
1771 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1772
1773 if (WARN_ON(pll == NULL))
1774 return;
1775
1776 WARN_ON(!pll->refcount);
1777 if (pll->active == 0) {
1778 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1779 WARN_ON(pll->on);
1780 assert_shared_dpll_disabled(dev_priv, pll);
1781
1782 pll->mode_set(dev_priv, pll);
1783 }
1784 }
1785
1786 /**
1787 * intel_enable_shared_dpll - enable PCH PLL
1788 * @dev_priv: i915 private structure
1789 * @pipe: pipe PLL to enable
1790 *
1791 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1792 * drives the transcoder clock.
1793 */
1794 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1795 {
1796 struct drm_device *dev = crtc->base.dev;
1797 struct drm_i915_private *dev_priv = dev->dev_private;
1798 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1799
1800 if (WARN_ON(pll == NULL))
1801 return;
1802
1803 if (WARN_ON(pll->refcount == 0))
1804 return;
1805
1806 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1807 pll->name, pll->active, pll->on,
1808 crtc->base.base.id);
1809
1810 if (pll->active++) {
1811 WARN_ON(!pll->on);
1812 assert_shared_dpll_enabled(dev_priv, pll);
1813 return;
1814 }
1815 WARN_ON(pll->on);
1816
1817 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1818 pll->enable(dev_priv, pll);
1819 pll->on = true;
1820 }
1821
1822 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1823 {
1824 struct drm_device *dev = crtc->base.dev;
1825 struct drm_i915_private *dev_priv = dev->dev_private;
1826 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1827
1828 /* PCH only available on ILK+ */
1829 BUG_ON(INTEL_INFO(dev)->gen < 5);
1830 if (WARN_ON(pll == NULL))
1831 return;
1832
1833 if (WARN_ON(pll->refcount == 0))
1834 return;
1835
1836 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1837 pll->name, pll->active, pll->on,
1838 crtc->base.base.id);
1839
1840 if (WARN_ON(pll->active == 0)) {
1841 assert_shared_dpll_disabled(dev_priv, pll);
1842 return;
1843 }
1844
1845 assert_shared_dpll_enabled(dev_priv, pll);
1846 WARN_ON(!pll->on);
1847 if (--pll->active)
1848 return;
1849
1850 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1851 pll->disable(dev_priv, pll);
1852 pll->on = false;
1853 }
1854
1855 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1856 enum pipe pipe)
1857 {
1858 struct drm_device *dev = dev_priv->dev;
1859 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1860 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1861 uint32_t reg, val, pipeconf_val;
1862
1863 /* PCH only available on ILK+ */
1864 BUG_ON(INTEL_INFO(dev)->gen < 5);
1865
1866 /* Make sure PCH DPLL is enabled */
1867 assert_shared_dpll_enabled(dev_priv,
1868 intel_crtc_to_shared_dpll(intel_crtc));
1869
1870 /* FDI must be feeding us bits for PCH ports */
1871 assert_fdi_tx_enabled(dev_priv, pipe);
1872 assert_fdi_rx_enabled(dev_priv, pipe);
1873
1874 if (HAS_PCH_CPT(dev)) {
1875 /* Workaround: Set the timing override bit before enabling the
1876 * pch transcoder. */
1877 reg = TRANS_CHICKEN2(pipe);
1878 val = I915_READ(reg);
1879 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1880 I915_WRITE(reg, val);
1881 }
1882
1883 reg = PCH_TRANSCONF(pipe);
1884 val = I915_READ(reg);
1885 pipeconf_val = I915_READ(PIPECONF(pipe));
1886
1887 if (HAS_PCH_IBX(dev_priv->dev)) {
1888 /*
1889 * make the BPC in transcoder be consistent with
1890 * that in pipeconf reg.
1891 */
1892 val &= ~PIPECONF_BPC_MASK;
1893 val |= pipeconf_val & PIPECONF_BPC_MASK;
1894 }
1895
1896 val &= ~TRANS_INTERLACE_MASK;
1897 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1898 if (HAS_PCH_IBX(dev_priv->dev) &&
1899 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1900 val |= TRANS_LEGACY_INTERLACED_ILK;
1901 else
1902 val |= TRANS_INTERLACED;
1903 else
1904 val |= TRANS_PROGRESSIVE;
1905
1906 I915_WRITE(reg, val | TRANS_ENABLE);
1907 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1908 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1909 }
1910
1911 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1912 enum transcoder cpu_transcoder)
1913 {
1914 u32 val, pipeconf_val;
1915
1916 /* PCH only available on ILK+ */
1917 BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1918
1919 /* FDI must be feeding us bits for PCH ports */
1920 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1921 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1922
1923 /* Workaround: set timing override bit. */
1924 val = I915_READ(_TRANSA_CHICKEN2);
1925 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1926 I915_WRITE(_TRANSA_CHICKEN2, val);
1927
1928 val = TRANS_ENABLE;
1929 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1930
1931 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1932 PIPECONF_INTERLACED_ILK)
1933 val |= TRANS_INTERLACED;
1934 else
1935 val |= TRANS_PROGRESSIVE;
1936
1937 I915_WRITE(LPT_TRANSCONF, val);
1938 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1939 DRM_ERROR("Failed to enable PCH transcoder\n");
1940 }
1941
1942 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1943 enum pipe pipe)
1944 {
1945 struct drm_device *dev = dev_priv->dev;
1946 uint32_t reg, val;
1947
1948 /* FDI relies on the transcoder */
1949 assert_fdi_tx_disabled(dev_priv, pipe);
1950 assert_fdi_rx_disabled(dev_priv, pipe);
1951
1952 /* Ports must be off as well */
1953 assert_pch_ports_disabled(dev_priv, pipe);
1954
1955 reg = PCH_TRANSCONF(pipe);
1956 val = I915_READ(reg);
1957 val &= ~TRANS_ENABLE;
1958 I915_WRITE(reg, val);
1959 /* wait for PCH transcoder off, transcoder state */
1960 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1961 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1962
1963 if (!HAS_PCH_IBX(dev)) {
1964 /* Workaround: Clear the timing override chicken bit again. */
1965 reg = TRANS_CHICKEN2(pipe);
1966 val = I915_READ(reg);
1967 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1968 I915_WRITE(reg, val);
1969 }
1970 }
1971
1972 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1973 {
1974 u32 val;
1975
1976 val = I915_READ(LPT_TRANSCONF);
1977 val &= ~TRANS_ENABLE;
1978 I915_WRITE(LPT_TRANSCONF, val);
1979 /* wait for PCH transcoder off, transcoder state */
1980 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1981 DRM_ERROR("Failed to disable PCH transcoder\n");
1982
1983 /* Workaround: clear timing override bit. */
1984 val = I915_READ(_TRANSA_CHICKEN2);
1985 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1986 I915_WRITE(_TRANSA_CHICKEN2, val);
1987 }
1988
1989 /**
1990 * intel_enable_pipe - enable a pipe, asserting requirements
1991 * @crtc: crtc responsible for the pipe
1992 *
1993 * Enable @crtc's pipe, making sure that various hardware specific requirements
1994 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1995 */
1996 static void intel_enable_pipe(struct intel_crtc *crtc)
1997 {
1998 struct drm_device *dev = crtc->base.dev;
1999 struct drm_i915_private *dev_priv = dev->dev_private;
2000 enum pipe pipe = crtc->pipe;
2001 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2002 pipe);
2003 enum pipe pch_transcoder;
2004 int reg;
2005 u32 val;
2006
2007 assert_planes_disabled(dev_priv, pipe);
2008 assert_cursor_disabled(dev_priv, pipe);
2009 assert_sprites_disabled(dev_priv, pipe);
2010
2011 if (HAS_PCH_LPT(dev_priv->dev))
2012 pch_transcoder = TRANSCODER_A;
2013 else
2014 pch_transcoder = pipe;
2015
2016 /*
2017 * A pipe without a PLL won't actually be able to drive bits from
2018 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2019 * need the check.
2020 */
2021 if (!HAS_PCH_SPLIT(dev_priv->dev))
2022 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
2023 assert_dsi_pll_enabled(dev_priv);
2024 else
2025 assert_pll_enabled(dev_priv, pipe);
2026 else {
2027 if (crtc->config.has_pch_encoder) {
2028 /* if driving the PCH, we need FDI enabled */
2029 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2030 assert_fdi_tx_pll_enabled(dev_priv,
2031 (enum pipe) cpu_transcoder);
2032 }
2033 /* FIXME: assert CPU port conditions for SNB+ */
2034 }
2035
2036 reg = PIPECONF(cpu_transcoder);
2037 val = I915_READ(reg);
2038 if (val & PIPECONF_ENABLE) {
2039 WARN_ON(!(pipe == PIPE_A &&
2040 dev_priv->quirks & QUIRK_PIPEA_FORCE));
2041 return;
2042 }
2043
2044 I915_WRITE(reg, val | PIPECONF_ENABLE);
2045 POSTING_READ(reg);
2046 }
2047
2048 /**
2049 * intel_disable_pipe - disable a pipe, asserting requirements
2050 * @dev_priv: i915 private structure
2051 * @pipe: pipe to disable
2052 *
2053 * Disable @pipe, making sure that various hardware specific requirements
2054 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
2055 *
2056 * @pipe should be %PIPE_A or %PIPE_B.
2057 *
2058 * Will wait until the pipe has shut down before returning.
2059 */
2060 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
2061 enum pipe pipe)
2062 {
2063 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2064 pipe);
2065 int reg;
2066 u32 val;
2067
2068 /*
2069 * Make sure planes won't keep trying to pump pixels to us,
2070 * or we might hang the display.
2071 */
2072 assert_planes_disabled(dev_priv, pipe);
2073 assert_cursor_disabled(dev_priv, pipe);
2074 assert_sprites_disabled(dev_priv, pipe);
2075
2076 /* Don't disable pipe A or pipe A PLLs if needed */
2077 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2078 return;
2079
2080 reg = PIPECONF(cpu_transcoder);
2081 val = I915_READ(reg);
2082 if ((val & PIPECONF_ENABLE) == 0)
2083 return;
2084
2085 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
2086 intel_wait_for_pipe_off(dev_priv->dev, pipe);
2087 }
2088
2089 /*
2090 * Plane regs are double buffered, going from enabled->disabled needs a
2091 * trigger in order to latch. The display address reg provides this.
2092 */
2093 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2094 enum plane plane)
2095 {
2096 struct drm_device *dev = dev_priv->dev;
2097 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2098
2099 I915_WRITE(reg, I915_READ(reg));
2100 POSTING_READ(reg);
2101 }
2102
2103 /**
2104 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2105 * @dev_priv: i915 private structure
2106 * @plane: plane to enable
2107 * @pipe: pipe being fed
2108 *
2109 * Enable @plane on @pipe, making sure that @pipe is running first.
2110 */
2111 static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
2112 enum plane plane, enum pipe pipe)
2113 {
2114 struct drm_device *dev = dev_priv->dev;
2115 struct intel_crtc *intel_crtc =
2116 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2117 int reg;
2118 u32 val;
2119
2120 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2121 assert_pipe_enabled(dev_priv, pipe);
2122
2123 if (intel_crtc->primary_enabled)
2124 return;
2125
2126 intel_crtc->primary_enabled = true;
2127
2128 reg = DSPCNTR(plane);
2129 val = I915_READ(reg);
2130 WARN_ON(val & DISPLAY_PLANE_ENABLE);
2131
2132 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
2133 intel_flush_primary_plane(dev_priv, plane);
2134
2135 /*
2136 * BDW signals flip done immediately if the plane
2137 * is disabled, even if the plane enable is already
2138 * armed to occur at the next vblank :(
2139 */
2140 if (IS_BROADWELL(dev))
2141 intel_wait_for_vblank(dev, intel_crtc->pipe);
2142 }
2143
2144 /**
2145 * intel_disable_primary_hw_plane - disable the primary hardware plane
2146 * @dev_priv: i915 private structure
2147 * @plane: plane to disable
2148 * @pipe: pipe consuming the data
2149 *
2150 * Disable @plane; should be an independent operation.
2151 */
2152 static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
2153 enum plane plane, enum pipe pipe)
2154 {
2155 struct intel_crtc *intel_crtc =
2156 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2157 int reg;
2158 u32 val;
2159
2160 if (!intel_crtc->primary_enabled)
2161 return;
2162
2163 intel_crtc->primary_enabled = false;
2164
2165 reg = DSPCNTR(plane);
2166 val = I915_READ(reg);
2167 WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0);
2168
2169 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
2170 intel_flush_primary_plane(dev_priv, plane);
2171 }
2172
2173 static bool need_vtd_wa(struct drm_device *dev)
2174 {
2175 #ifdef CONFIG_INTEL_IOMMU
2176 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2177 return true;
2178 #endif
2179 return false;
2180 }
2181
2182 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2183 {
2184 int tile_height;
2185
2186 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2187 return ALIGN(height, tile_height);
2188 }
2189
2190 int
2191 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2192 struct drm_i915_gem_object *obj,
2193 struct intel_engine_cs *pipelined)
2194 {
2195 struct drm_i915_private *dev_priv = dev->dev_private;
2196 u32 alignment;
2197 int ret;
2198
2199 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2200
2201 switch (obj->tiling_mode) {
2202 case I915_TILING_NONE:
2203 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2204 alignment = 128 * 1024;
2205 else if (INTEL_INFO(dev)->gen >= 4)
2206 alignment = 4 * 1024;
2207 else
2208 alignment = 64 * 1024;
2209 break;
2210 case I915_TILING_X:
2211 /* pin() will align the object as required by fence */
2212 alignment = 0;
2213 break;
2214 case I915_TILING_Y:
2215 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2216 return -EINVAL;
2217 default:
2218 BUG();
2219 }
2220
2221 /* Note that the w/a also requires 64 PTE of padding following the
2222 * bo. We currently fill all unused PTE with the shadow page and so
2223 * we should always have valid PTE following the scanout preventing
2224 * the VT-d warning.
2225 */
2226 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2227 alignment = 256 * 1024;
2228
2229 dev_priv->mm.interruptible = false;
2230 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2231 if (ret)
2232 goto err_interruptible;
2233
2234 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2235 * fence, whereas 965+ only requires a fence if using
2236 * framebuffer compression. For simplicity, we always install
2237 * a fence as the cost is not that onerous.
2238 */
2239 ret = i915_gem_object_get_fence(obj);
2240 if (ret)
2241 goto err_unpin;
2242
2243 i915_gem_object_pin_fence(obj);
2244
2245 dev_priv->mm.interruptible = true;
2246 return 0;
2247
2248 err_unpin:
2249 i915_gem_object_unpin_from_display_plane(obj);
2250 err_interruptible:
2251 dev_priv->mm.interruptible = true;
2252 return ret;
2253 }
2254
2255 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2256 {
2257 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2258
2259 i915_gem_object_unpin_fence(obj);
2260 i915_gem_object_unpin_from_display_plane(obj);
2261 }
2262
2263 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2264 * is assumed to be a power-of-two. */
2265 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2266 unsigned int tiling_mode,
2267 unsigned int cpp,
2268 unsigned int pitch)
2269 {
2270 if (tiling_mode != I915_TILING_NONE) {
2271 unsigned int tile_rows, tiles;
2272
2273 tile_rows = *y / 8;
2274 *y %= 8;
2275
2276 tiles = *x / (512/cpp);
2277 *x %= 512/cpp;
2278
2279 return tile_rows * pitch * 8 + tiles * 4096;
2280 } else {
2281 unsigned int offset;
2282
2283 offset = *y * pitch + *x * cpp;
2284 *y = 0;
2285 *x = (offset & 4095) / cpp;
2286 return offset & -4096;
2287 }
2288 }
2289
2290 int intel_format_to_fourcc(int format)
2291 {
2292 switch (format) {
2293 case DISPPLANE_8BPP:
2294 return DRM_FORMAT_C8;
2295 case DISPPLANE_BGRX555:
2296 return DRM_FORMAT_XRGB1555;
2297 case DISPPLANE_BGRX565:
2298 return DRM_FORMAT_RGB565;
2299 default:
2300 case DISPPLANE_BGRX888:
2301 return DRM_FORMAT_XRGB8888;
2302 case DISPPLANE_RGBX888:
2303 return DRM_FORMAT_XBGR8888;
2304 case DISPPLANE_BGRX101010:
2305 return DRM_FORMAT_XRGB2101010;
2306 case DISPPLANE_RGBX101010:
2307 return DRM_FORMAT_XBGR2101010;
2308 }
2309 }
2310
2311 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2312 struct intel_plane_config *plane_config)
2313 {
2314 struct drm_device *dev = crtc->base.dev;
2315 struct drm_i915_gem_object *obj = NULL;
2316 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2317 u32 base = plane_config->base;
2318
2319 if (plane_config->size == 0)
2320 return false;
2321
2322 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2323 plane_config->size);
2324 if (!obj)
2325 return false;
2326
2327 if (plane_config->tiled) {
2328 obj->tiling_mode = I915_TILING_X;
2329 obj->stride = crtc->base.primary->fb->pitches[0];
2330 }
2331
2332 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2333 mode_cmd.width = crtc->base.primary->fb->width;
2334 mode_cmd.height = crtc->base.primary->fb->height;
2335 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2336
2337 mutex_lock(&dev->struct_mutex);
2338
2339 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2340 &mode_cmd, obj)) {
2341 DRM_DEBUG_KMS("intel fb init failed\n");
2342 goto out_unref_obj;
2343 }
2344
2345 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2346 mutex_unlock(&dev->struct_mutex);
2347
2348 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2349 return true;
2350
2351 out_unref_obj:
2352 drm_gem_object_unreference(&obj->base);
2353 mutex_unlock(&dev->struct_mutex);
2354 return false;
2355 }
2356
2357 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2358 struct intel_plane_config *plane_config)
2359 {
2360 struct drm_device *dev = intel_crtc->base.dev;
2361 struct drm_crtc *c;
2362 struct intel_crtc *i;
2363 struct drm_i915_gem_object *obj;
2364
2365 if (!intel_crtc->base.primary->fb)
2366 return;
2367
2368 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2369 return;
2370
2371 kfree(intel_crtc->base.primary->fb);
2372 intel_crtc->base.primary->fb = NULL;
2373
2374 /*
2375 * Failed to alloc the obj, check to see if we should share
2376 * an fb with another CRTC instead
2377 */
2378 for_each_crtc(dev, c) {
2379 i = to_intel_crtc(c);
2380
2381 if (c == &intel_crtc->base)
2382 continue;
2383
2384 if (!i->active)
2385 continue;
2386
2387 obj = intel_fb_obj(c->primary->fb);
2388 if (obj == NULL)
2389 continue;
2390
2391 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2392 drm_framebuffer_reference(c->primary->fb);
2393 intel_crtc->base.primary->fb = c->primary->fb;
2394 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2395 break;
2396 }
2397 }
2398 }
2399
2400 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2401 struct drm_framebuffer *fb,
2402 int x, int y)
2403 {
2404 struct drm_device *dev = crtc->dev;
2405 struct drm_i915_private *dev_priv = dev->dev_private;
2406 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2407 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2408 int plane = intel_crtc->plane;
2409 unsigned long linear_offset;
2410 u32 dspcntr;
2411 u32 reg;
2412
2413 reg = DSPCNTR(plane);
2414 dspcntr = I915_READ(reg);
2415 /* Mask out pixel format bits in case we change it */
2416 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2417 switch (fb->pixel_format) {
2418 case DRM_FORMAT_C8:
2419 dspcntr |= DISPPLANE_8BPP;
2420 break;
2421 case DRM_FORMAT_XRGB1555:
2422 case DRM_FORMAT_ARGB1555:
2423 dspcntr |= DISPPLANE_BGRX555;
2424 break;
2425 case DRM_FORMAT_RGB565:
2426 dspcntr |= DISPPLANE_BGRX565;
2427 break;
2428 case DRM_FORMAT_XRGB8888:
2429 case DRM_FORMAT_ARGB8888:
2430 dspcntr |= DISPPLANE_BGRX888;
2431 break;
2432 case DRM_FORMAT_XBGR8888:
2433 case DRM_FORMAT_ABGR8888:
2434 dspcntr |= DISPPLANE_RGBX888;
2435 break;
2436 case DRM_FORMAT_XRGB2101010:
2437 case DRM_FORMAT_ARGB2101010:
2438 dspcntr |= DISPPLANE_BGRX101010;
2439 break;
2440 case DRM_FORMAT_XBGR2101010:
2441 case DRM_FORMAT_ABGR2101010:
2442 dspcntr |= DISPPLANE_RGBX101010;
2443 break;
2444 default:
2445 BUG();
2446 }
2447
2448 if (INTEL_INFO(dev)->gen >= 4) {
2449 if (obj->tiling_mode != I915_TILING_NONE)
2450 dspcntr |= DISPPLANE_TILED;
2451 else
2452 dspcntr &= ~DISPPLANE_TILED;
2453 }
2454
2455 if (IS_G4X(dev))
2456 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2457
2458 I915_WRITE(reg, dspcntr);
2459
2460 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2461
2462 if (INTEL_INFO(dev)->gen >= 4) {
2463 intel_crtc->dspaddr_offset =
2464 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2465 fb->bits_per_pixel / 8,
2466 fb->pitches[0]);
2467 linear_offset -= intel_crtc->dspaddr_offset;
2468 } else {
2469 intel_crtc->dspaddr_offset = linear_offset;
2470 }
2471
2472 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2473 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2474 fb->pitches[0]);
2475 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2476 if (INTEL_INFO(dev)->gen >= 4) {
2477 I915_WRITE(DSPSURF(plane),
2478 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2479 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2480 I915_WRITE(DSPLINOFF(plane), linear_offset);
2481 } else
2482 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2483 POSTING_READ(reg);
2484 }
2485
2486 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2487 struct drm_framebuffer *fb,
2488 int x, int y)
2489 {
2490 struct drm_device *dev = crtc->dev;
2491 struct drm_i915_private *dev_priv = dev->dev_private;
2492 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2493 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2494 int plane = intel_crtc->plane;
2495 unsigned long linear_offset;
2496 u32 dspcntr;
2497 u32 reg;
2498
2499 reg = DSPCNTR(plane);
2500 dspcntr = I915_READ(reg);
2501 /* Mask out pixel format bits in case we change it */
2502 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2503 switch (fb->pixel_format) {
2504 case DRM_FORMAT_C8:
2505 dspcntr |= DISPPLANE_8BPP;
2506 break;
2507 case DRM_FORMAT_RGB565:
2508 dspcntr |= DISPPLANE_BGRX565;
2509 break;
2510 case DRM_FORMAT_XRGB8888:
2511 case DRM_FORMAT_ARGB8888:
2512 dspcntr |= DISPPLANE_BGRX888;
2513 break;
2514 case DRM_FORMAT_XBGR8888:
2515 case DRM_FORMAT_ABGR8888:
2516 dspcntr |= DISPPLANE_RGBX888;
2517 break;
2518 case DRM_FORMAT_XRGB2101010:
2519 case DRM_FORMAT_ARGB2101010:
2520 dspcntr |= DISPPLANE_BGRX101010;
2521 break;
2522 case DRM_FORMAT_XBGR2101010:
2523 case DRM_FORMAT_ABGR2101010:
2524 dspcntr |= DISPPLANE_RGBX101010;
2525 break;
2526 default:
2527 BUG();
2528 }
2529
2530 if (obj->tiling_mode != I915_TILING_NONE)
2531 dspcntr |= DISPPLANE_TILED;
2532 else
2533 dspcntr &= ~DISPPLANE_TILED;
2534
2535 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2536 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2537 else
2538 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2539
2540 I915_WRITE(reg, dspcntr);
2541
2542 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2543 intel_crtc->dspaddr_offset =
2544 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2545 fb->bits_per_pixel / 8,
2546 fb->pitches[0]);
2547 linear_offset -= intel_crtc->dspaddr_offset;
2548
2549 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2550 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2551 fb->pitches[0]);
2552 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2553 I915_WRITE(DSPSURF(plane),
2554 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2555 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2556 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2557 } else {
2558 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2559 I915_WRITE(DSPLINOFF(plane), linear_offset);
2560 }
2561 POSTING_READ(reg);
2562 }
2563
2564 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2565 static int
2566 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2567 int x, int y, enum mode_set_atomic state)
2568 {
2569 struct drm_device *dev = crtc->dev;
2570 struct drm_i915_private *dev_priv = dev->dev_private;
2571
2572 if (dev_priv->display.disable_fbc)
2573 dev_priv->display.disable_fbc(dev);
2574 intel_increase_pllclock(dev, to_intel_crtc(crtc)->pipe);
2575
2576 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2577
2578 return 0;
2579 }
2580
2581 void intel_display_handle_reset(struct drm_device *dev)
2582 {
2583 struct drm_i915_private *dev_priv = dev->dev_private;
2584 struct drm_crtc *crtc;
2585
2586 /*
2587 * Flips in the rings have been nuked by the reset,
2588 * so complete all pending flips so that user space
2589 * will get its events and not get stuck.
2590 *
2591 * Also update the base address of all primary
2592 * planes to the the last fb to make sure we're
2593 * showing the correct fb after a reset.
2594 *
2595 * Need to make two loops over the crtcs so that we
2596 * don't try to grab a crtc mutex before the
2597 * pending_flip_queue really got woken up.
2598 */
2599
2600 for_each_crtc(dev, crtc) {
2601 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2602 enum plane plane = intel_crtc->plane;
2603
2604 intel_prepare_page_flip(dev, plane);
2605 intel_finish_page_flip_plane(dev, plane);
2606 }
2607
2608 for_each_crtc(dev, crtc) {
2609 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2610
2611 drm_modeset_lock(&crtc->mutex, NULL);
2612 /*
2613 * FIXME: Once we have proper support for primary planes (and
2614 * disabling them without disabling the entire crtc) allow again
2615 * a NULL crtc->primary->fb.
2616 */
2617 if (intel_crtc->active && crtc->primary->fb)
2618 dev_priv->display.update_primary_plane(crtc,
2619 crtc->primary->fb,
2620 crtc->x,
2621 crtc->y);
2622 drm_modeset_unlock(&crtc->mutex);
2623 }
2624 }
2625
2626 static int
2627 intel_finish_fb(struct drm_framebuffer *old_fb)
2628 {
2629 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2630 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2631 bool was_interruptible = dev_priv->mm.interruptible;
2632 int ret;
2633
2634 /* Big Hammer, we also need to ensure that any pending
2635 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2636 * current scanout is retired before unpinning the old
2637 * framebuffer.
2638 *
2639 * This should only fail upon a hung GPU, in which case we
2640 * can safely continue.
2641 */
2642 dev_priv->mm.interruptible = false;
2643 ret = i915_gem_object_finish_gpu(obj);
2644 dev_priv->mm.interruptible = was_interruptible;
2645
2646 return ret;
2647 }
2648
2649 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2650 {
2651 struct drm_device *dev = crtc->dev;
2652 struct drm_i915_private *dev_priv = dev->dev_private;
2653 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2654 unsigned long flags;
2655 bool pending;
2656
2657 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2658 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2659 return false;
2660
2661 spin_lock_irqsave(&dev->event_lock, flags);
2662 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2663 spin_unlock_irqrestore(&dev->event_lock, flags);
2664
2665 return pending;
2666 }
2667
2668 static int
2669 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2670 struct drm_framebuffer *fb)
2671 {
2672 struct drm_device *dev = crtc->dev;
2673 struct drm_i915_private *dev_priv = dev->dev_private;
2674 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2675 enum pipe pipe = intel_crtc->pipe;
2676 struct drm_framebuffer *old_fb = crtc->primary->fb;
2677 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2678 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
2679 int ret;
2680
2681 if (intel_crtc_has_pending_flip(crtc)) {
2682 DRM_ERROR("pipe is still busy with an old pageflip\n");
2683 return -EBUSY;
2684 }
2685
2686 /* no fb bound */
2687 if (!fb) {
2688 DRM_ERROR("No FB bound\n");
2689 return 0;
2690 }
2691
2692 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2693 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2694 plane_name(intel_crtc->plane),
2695 INTEL_INFO(dev)->num_pipes);
2696 return -EINVAL;
2697 }
2698
2699 mutex_lock(&dev->struct_mutex);
2700 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
2701 if (ret == 0)
2702 i915_gem_track_fb(old_obj, obj,
2703 INTEL_FRONTBUFFER_PRIMARY(pipe));
2704 mutex_unlock(&dev->struct_mutex);
2705 if (ret != 0) {
2706 DRM_ERROR("pin & fence failed\n");
2707 return ret;
2708 }
2709
2710 /*
2711 * Update pipe size and adjust fitter if needed: the reason for this is
2712 * that in compute_mode_changes we check the native mode (not the pfit
2713 * mode) to see if we can flip rather than do a full mode set. In the
2714 * fastboot case, we'll flip, but if we don't update the pipesrc and
2715 * pfit state, we'll end up with a big fb scanned out into the wrong
2716 * sized surface.
2717 *
2718 * To fix this properly, we need to hoist the checks up into
2719 * compute_mode_changes (or above), check the actual pfit state and
2720 * whether the platform allows pfit disable with pipe active, and only
2721 * then update the pipesrc and pfit state, even on the flip path.
2722 */
2723 if (i915.fastboot) {
2724 const struct drm_display_mode *adjusted_mode =
2725 &intel_crtc->config.adjusted_mode;
2726
2727 I915_WRITE(PIPESRC(intel_crtc->pipe),
2728 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2729 (adjusted_mode->crtc_vdisplay - 1));
2730 if (!intel_crtc->config.pch_pfit.enabled &&
2731 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2732 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2733 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2734 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2735 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2736 }
2737 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2738 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2739 }
2740
2741 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2742
2743 if (intel_crtc->active)
2744 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2745
2746 crtc->primary->fb = fb;
2747 crtc->x = x;
2748 crtc->y = y;
2749
2750 if (old_fb) {
2751 if (intel_crtc->active && old_fb != fb)
2752 intel_wait_for_vblank(dev, intel_crtc->pipe);
2753 mutex_lock(&dev->struct_mutex);
2754 intel_unpin_fb_obj(old_obj);
2755 mutex_unlock(&dev->struct_mutex);
2756 }
2757
2758 mutex_lock(&dev->struct_mutex);
2759 intel_update_fbc(dev);
2760 mutex_unlock(&dev->struct_mutex);
2761
2762 return 0;
2763 }
2764
2765 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2766 {
2767 struct drm_device *dev = crtc->dev;
2768 struct drm_i915_private *dev_priv = dev->dev_private;
2769 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2770 int pipe = intel_crtc->pipe;
2771 u32 reg, temp;
2772
2773 /* enable normal train */
2774 reg = FDI_TX_CTL(pipe);
2775 temp = I915_READ(reg);
2776 if (IS_IVYBRIDGE(dev)) {
2777 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2778 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2779 } else {
2780 temp &= ~FDI_LINK_TRAIN_NONE;
2781 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2782 }
2783 I915_WRITE(reg, temp);
2784
2785 reg = FDI_RX_CTL(pipe);
2786 temp = I915_READ(reg);
2787 if (HAS_PCH_CPT(dev)) {
2788 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2789 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2790 } else {
2791 temp &= ~FDI_LINK_TRAIN_NONE;
2792 temp |= FDI_LINK_TRAIN_NONE;
2793 }
2794 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2795
2796 /* wait one idle pattern time */
2797 POSTING_READ(reg);
2798 udelay(1000);
2799
2800 /* IVB wants error correction enabled */
2801 if (IS_IVYBRIDGE(dev))
2802 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2803 FDI_FE_ERRC_ENABLE);
2804 }
2805
2806 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2807 {
2808 return crtc->base.enabled && crtc->active &&
2809 crtc->config.has_pch_encoder;
2810 }
2811
2812 static void ivb_modeset_global_resources(struct drm_device *dev)
2813 {
2814 struct drm_i915_private *dev_priv = dev->dev_private;
2815 struct intel_crtc *pipe_B_crtc =
2816 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2817 struct intel_crtc *pipe_C_crtc =
2818 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2819 uint32_t temp;
2820
2821 /*
2822 * When everything is off disable fdi C so that we could enable fdi B
2823 * with all lanes. Note that we don't care about enabled pipes without
2824 * an enabled pch encoder.
2825 */
2826 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2827 !pipe_has_enabled_pch(pipe_C_crtc)) {
2828 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2829 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2830
2831 temp = I915_READ(SOUTH_CHICKEN1);
2832 temp &= ~FDI_BC_BIFURCATION_SELECT;
2833 DRM_DEBUG_KMS("disabling fdi C rx\n");
2834 I915_WRITE(SOUTH_CHICKEN1, temp);
2835 }
2836 }
2837
2838 /* The FDI link training functions for ILK/Ibexpeak. */
2839 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2840 {
2841 struct drm_device *dev = crtc->dev;
2842 struct drm_i915_private *dev_priv = dev->dev_private;
2843 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2844 int pipe = intel_crtc->pipe;
2845 u32 reg, temp, tries;
2846
2847 /* FDI needs bits from pipe first */
2848 assert_pipe_enabled(dev_priv, pipe);
2849
2850 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2851 for train result */
2852 reg = FDI_RX_IMR(pipe);
2853 temp = I915_READ(reg);
2854 temp &= ~FDI_RX_SYMBOL_LOCK;
2855 temp &= ~FDI_RX_BIT_LOCK;
2856 I915_WRITE(reg, temp);
2857 I915_READ(reg);
2858 udelay(150);
2859
2860 /* enable CPU FDI TX and PCH FDI RX */
2861 reg = FDI_TX_CTL(pipe);
2862 temp = I915_READ(reg);
2863 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2864 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2865 temp &= ~FDI_LINK_TRAIN_NONE;
2866 temp |= FDI_LINK_TRAIN_PATTERN_1;
2867 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2868
2869 reg = FDI_RX_CTL(pipe);
2870 temp = I915_READ(reg);
2871 temp &= ~FDI_LINK_TRAIN_NONE;
2872 temp |= FDI_LINK_TRAIN_PATTERN_1;
2873 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2874
2875 POSTING_READ(reg);
2876 udelay(150);
2877
2878 /* Ironlake workaround, enable clock pointer after FDI enable*/
2879 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2880 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2881 FDI_RX_PHASE_SYNC_POINTER_EN);
2882
2883 reg = FDI_RX_IIR(pipe);
2884 for (tries = 0; tries < 5; tries++) {
2885 temp = I915_READ(reg);
2886 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2887
2888 if ((temp & FDI_RX_BIT_LOCK)) {
2889 DRM_DEBUG_KMS("FDI train 1 done.\n");
2890 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2891 break;
2892 }
2893 }
2894 if (tries == 5)
2895 DRM_ERROR("FDI train 1 fail!\n");
2896
2897 /* Train 2 */
2898 reg = FDI_TX_CTL(pipe);
2899 temp = I915_READ(reg);
2900 temp &= ~FDI_LINK_TRAIN_NONE;
2901 temp |= FDI_LINK_TRAIN_PATTERN_2;
2902 I915_WRITE(reg, temp);
2903
2904 reg = FDI_RX_CTL(pipe);
2905 temp = I915_READ(reg);
2906 temp &= ~FDI_LINK_TRAIN_NONE;
2907 temp |= FDI_LINK_TRAIN_PATTERN_2;
2908 I915_WRITE(reg, temp);
2909
2910 POSTING_READ(reg);
2911 udelay(150);
2912
2913 reg = FDI_RX_IIR(pipe);
2914 for (tries = 0; tries < 5; tries++) {
2915 temp = I915_READ(reg);
2916 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2917
2918 if (temp & FDI_RX_SYMBOL_LOCK) {
2919 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2920 DRM_DEBUG_KMS("FDI train 2 done.\n");
2921 break;
2922 }
2923 }
2924 if (tries == 5)
2925 DRM_ERROR("FDI train 2 fail!\n");
2926
2927 DRM_DEBUG_KMS("FDI train done\n");
2928
2929 }
2930
2931 static const int snb_b_fdi_train_param[] = {
2932 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2933 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2934 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2935 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2936 };
2937
2938 /* The FDI link training functions for SNB/Cougarpoint. */
2939 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2940 {
2941 struct drm_device *dev = crtc->dev;
2942 struct drm_i915_private *dev_priv = dev->dev_private;
2943 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2944 int pipe = intel_crtc->pipe;
2945 u32 reg, temp, i, retry;
2946
2947 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2948 for train result */
2949 reg = FDI_RX_IMR(pipe);
2950 temp = I915_READ(reg);
2951 temp &= ~FDI_RX_SYMBOL_LOCK;
2952 temp &= ~FDI_RX_BIT_LOCK;
2953 I915_WRITE(reg, temp);
2954
2955 POSTING_READ(reg);
2956 udelay(150);
2957
2958 /* enable CPU FDI TX and PCH FDI RX */
2959 reg = FDI_TX_CTL(pipe);
2960 temp = I915_READ(reg);
2961 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2962 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2963 temp &= ~FDI_LINK_TRAIN_NONE;
2964 temp |= FDI_LINK_TRAIN_PATTERN_1;
2965 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2966 /* SNB-B */
2967 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2968 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2969
2970 I915_WRITE(FDI_RX_MISC(pipe),
2971 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2972
2973 reg = FDI_RX_CTL(pipe);
2974 temp = I915_READ(reg);
2975 if (HAS_PCH_CPT(dev)) {
2976 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2977 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2978 } else {
2979 temp &= ~FDI_LINK_TRAIN_NONE;
2980 temp |= FDI_LINK_TRAIN_PATTERN_1;
2981 }
2982 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2983
2984 POSTING_READ(reg);
2985 udelay(150);
2986
2987 for (i = 0; i < 4; i++) {
2988 reg = FDI_TX_CTL(pipe);
2989 temp = I915_READ(reg);
2990 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2991 temp |= snb_b_fdi_train_param[i];
2992 I915_WRITE(reg, temp);
2993
2994 POSTING_READ(reg);
2995 udelay(500);
2996
2997 for (retry = 0; retry < 5; retry++) {
2998 reg = FDI_RX_IIR(pipe);
2999 temp = I915_READ(reg);
3000 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3001 if (temp & FDI_RX_BIT_LOCK) {
3002 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3003 DRM_DEBUG_KMS("FDI train 1 done.\n");
3004 break;
3005 }
3006 udelay(50);
3007 }
3008 if (retry < 5)
3009 break;
3010 }
3011 if (i == 4)
3012 DRM_ERROR("FDI train 1 fail!\n");
3013
3014 /* Train 2 */
3015 reg = FDI_TX_CTL(pipe);
3016 temp = I915_READ(reg);
3017 temp &= ~FDI_LINK_TRAIN_NONE;
3018 temp |= FDI_LINK_TRAIN_PATTERN_2;
3019 if (IS_GEN6(dev)) {
3020 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3021 /* SNB-B */
3022 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3023 }
3024 I915_WRITE(reg, temp);
3025
3026 reg = FDI_RX_CTL(pipe);
3027 temp = I915_READ(reg);
3028 if (HAS_PCH_CPT(dev)) {
3029 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3030 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3031 } else {
3032 temp &= ~FDI_LINK_TRAIN_NONE;
3033 temp |= FDI_LINK_TRAIN_PATTERN_2;
3034 }
3035 I915_WRITE(reg, temp);
3036
3037 POSTING_READ(reg);
3038 udelay(150);
3039
3040 for (i = 0; i < 4; i++) {
3041 reg = FDI_TX_CTL(pipe);
3042 temp = I915_READ(reg);
3043 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3044 temp |= snb_b_fdi_train_param[i];
3045 I915_WRITE(reg, temp);
3046
3047 POSTING_READ(reg);
3048 udelay(500);
3049
3050 for (retry = 0; retry < 5; retry++) {
3051 reg = FDI_RX_IIR(pipe);
3052 temp = I915_READ(reg);
3053 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3054 if (temp & FDI_RX_SYMBOL_LOCK) {
3055 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3056 DRM_DEBUG_KMS("FDI train 2 done.\n");
3057 break;
3058 }
3059 udelay(50);
3060 }
3061 if (retry < 5)
3062 break;
3063 }
3064 if (i == 4)
3065 DRM_ERROR("FDI train 2 fail!\n");
3066
3067 DRM_DEBUG_KMS("FDI train done.\n");
3068 }
3069
3070 /* Manual link training for Ivy Bridge A0 parts */
3071 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3072 {
3073 struct drm_device *dev = crtc->dev;
3074 struct drm_i915_private *dev_priv = dev->dev_private;
3075 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3076 int pipe = intel_crtc->pipe;
3077 u32 reg, temp, i, j;
3078
3079 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3080 for train result */
3081 reg = FDI_RX_IMR(pipe);
3082 temp = I915_READ(reg);
3083 temp &= ~FDI_RX_SYMBOL_LOCK;
3084 temp &= ~FDI_RX_BIT_LOCK;
3085 I915_WRITE(reg, temp);
3086
3087 POSTING_READ(reg);
3088 udelay(150);
3089
3090 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3091 I915_READ(FDI_RX_IIR(pipe)));
3092
3093 /* Try each vswing and preemphasis setting twice before moving on */
3094 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3095 /* disable first in case we need to retry */
3096 reg = FDI_TX_CTL(pipe);
3097 temp = I915_READ(reg);
3098 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3099 temp &= ~FDI_TX_ENABLE;
3100 I915_WRITE(reg, temp);
3101
3102 reg = FDI_RX_CTL(pipe);
3103 temp = I915_READ(reg);
3104 temp &= ~FDI_LINK_TRAIN_AUTO;
3105 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3106 temp &= ~FDI_RX_ENABLE;
3107 I915_WRITE(reg, temp);
3108
3109 /* enable CPU FDI TX and PCH FDI RX */
3110 reg = FDI_TX_CTL(pipe);
3111 temp = I915_READ(reg);
3112 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3113 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3114 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3115 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3116 temp |= snb_b_fdi_train_param[j/2];
3117 temp |= FDI_COMPOSITE_SYNC;
3118 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3119
3120 I915_WRITE(FDI_RX_MISC(pipe),
3121 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3122
3123 reg = FDI_RX_CTL(pipe);
3124 temp = I915_READ(reg);
3125 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3126 temp |= FDI_COMPOSITE_SYNC;
3127 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3128
3129 POSTING_READ(reg);
3130 udelay(1); /* should be 0.5us */
3131
3132 for (i = 0; i < 4; i++) {
3133 reg = FDI_RX_IIR(pipe);
3134 temp = I915_READ(reg);
3135 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3136
3137 if (temp & FDI_RX_BIT_LOCK ||
3138 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3139 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3140 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3141 i);
3142 break;
3143 }
3144 udelay(1); /* should be 0.5us */
3145 }
3146 if (i == 4) {
3147 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3148 continue;
3149 }
3150
3151 /* Train 2 */
3152 reg = FDI_TX_CTL(pipe);
3153 temp = I915_READ(reg);
3154 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3155 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3156 I915_WRITE(reg, temp);
3157
3158 reg = FDI_RX_CTL(pipe);
3159 temp = I915_READ(reg);
3160 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3161 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3162 I915_WRITE(reg, temp);
3163
3164 POSTING_READ(reg);
3165 udelay(2); /* should be 1.5us */
3166
3167 for (i = 0; i < 4; i++) {
3168 reg = FDI_RX_IIR(pipe);
3169 temp = I915_READ(reg);
3170 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3171
3172 if (temp & FDI_RX_SYMBOL_LOCK ||
3173 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3174 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3175 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3176 i);
3177 goto train_done;
3178 }
3179 udelay(2); /* should be 1.5us */
3180 }
3181 if (i == 4)
3182 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3183 }
3184
3185 train_done:
3186 DRM_DEBUG_KMS("FDI train done.\n");
3187 }
3188
3189 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3190 {
3191 struct drm_device *dev = intel_crtc->base.dev;
3192 struct drm_i915_private *dev_priv = dev->dev_private;
3193 int pipe = intel_crtc->pipe;
3194 u32 reg, temp;
3195
3196
3197 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3198 reg = FDI_RX_CTL(pipe);
3199 temp = I915_READ(reg);
3200 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3201 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3202 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3203 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3204
3205 POSTING_READ(reg);
3206 udelay(200);
3207
3208 /* Switch from Rawclk to PCDclk */
3209 temp = I915_READ(reg);
3210 I915_WRITE(reg, temp | FDI_PCDCLK);
3211
3212 POSTING_READ(reg);
3213 udelay(200);
3214
3215 /* Enable CPU FDI TX PLL, always on for Ironlake */
3216 reg = FDI_TX_CTL(pipe);
3217 temp = I915_READ(reg);
3218 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3219 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3220
3221 POSTING_READ(reg);
3222 udelay(100);
3223 }
3224 }
3225
3226 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3227 {
3228 struct drm_device *dev = intel_crtc->base.dev;
3229 struct drm_i915_private *dev_priv = dev->dev_private;
3230 int pipe = intel_crtc->pipe;
3231 u32 reg, temp;
3232
3233 /* Switch from PCDclk to Rawclk */
3234 reg = FDI_RX_CTL(pipe);
3235 temp = I915_READ(reg);
3236 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3237
3238 /* Disable CPU FDI TX PLL */
3239 reg = FDI_TX_CTL(pipe);
3240 temp = I915_READ(reg);
3241 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3242
3243 POSTING_READ(reg);
3244 udelay(100);
3245
3246 reg = FDI_RX_CTL(pipe);
3247 temp = I915_READ(reg);
3248 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3249
3250 /* Wait for the clocks to turn off. */
3251 POSTING_READ(reg);
3252 udelay(100);
3253 }
3254
3255 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3256 {
3257 struct drm_device *dev = crtc->dev;
3258 struct drm_i915_private *dev_priv = dev->dev_private;
3259 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3260 int pipe = intel_crtc->pipe;
3261 u32 reg, temp;
3262
3263 /* disable CPU FDI tx and PCH FDI rx */
3264 reg = FDI_TX_CTL(pipe);
3265 temp = I915_READ(reg);
3266 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3267 POSTING_READ(reg);
3268
3269 reg = FDI_RX_CTL(pipe);
3270 temp = I915_READ(reg);
3271 temp &= ~(0x7 << 16);
3272 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3273 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3274
3275 POSTING_READ(reg);
3276 udelay(100);
3277
3278 /* Ironlake workaround, disable clock pointer after downing FDI */
3279 if (HAS_PCH_IBX(dev))
3280 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3281
3282 /* still set train pattern 1 */
3283 reg = FDI_TX_CTL(pipe);
3284 temp = I915_READ(reg);
3285 temp &= ~FDI_LINK_TRAIN_NONE;
3286 temp |= FDI_LINK_TRAIN_PATTERN_1;
3287 I915_WRITE(reg, temp);
3288
3289 reg = FDI_RX_CTL(pipe);
3290 temp = I915_READ(reg);
3291 if (HAS_PCH_CPT(dev)) {
3292 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3293 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3294 } else {
3295 temp &= ~FDI_LINK_TRAIN_NONE;
3296 temp |= FDI_LINK_TRAIN_PATTERN_1;
3297 }
3298 /* BPC in FDI rx is consistent with that in PIPECONF */
3299 temp &= ~(0x07 << 16);
3300 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3301 I915_WRITE(reg, temp);
3302
3303 POSTING_READ(reg);
3304 udelay(100);
3305 }
3306
3307 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3308 {
3309 struct intel_crtc *crtc;
3310
3311 /* Note that we don't need to be called with mode_config.lock here
3312 * as our list of CRTC objects is static for the lifetime of the
3313 * device and so cannot disappear as we iterate. Similarly, we can
3314 * happily treat the predicates as racy, atomic checks as userspace
3315 * cannot claim and pin a new fb without at least acquring the
3316 * struct_mutex and so serialising with us.
3317 */
3318 for_each_intel_crtc(dev, crtc) {
3319 if (atomic_read(&crtc->unpin_work_count) == 0)
3320 continue;
3321
3322 if (crtc->unpin_work)
3323 intel_wait_for_vblank(dev, crtc->pipe);
3324
3325 return true;
3326 }
3327
3328 return false;
3329 }
3330
3331 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3332 {
3333 struct drm_device *dev = crtc->dev;
3334 struct drm_i915_private *dev_priv = dev->dev_private;
3335
3336 if (crtc->primary->fb == NULL)
3337 return;
3338
3339 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3340
3341 WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3342 !intel_crtc_has_pending_flip(crtc),
3343 60*HZ) == 0);
3344
3345 mutex_lock(&dev->struct_mutex);
3346 intel_finish_fb(crtc->primary->fb);
3347 mutex_unlock(&dev->struct_mutex);
3348 }
3349
3350 /* Program iCLKIP clock to the desired frequency */
3351 static void lpt_program_iclkip(struct drm_crtc *crtc)
3352 {
3353 struct drm_device *dev = crtc->dev;
3354 struct drm_i915_private *dev_priv = dev->dev_private;
3355 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3356 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3357 u32 temp;
3358
3359 mutex_lock(&dev_priv->dpio_lock);
3360
3361 /* It is necessary to ungate the pixclk gate prior to programming
3362 * the divisors, and gate it back when it is done.
3363 */
3364 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3365
3366 /* Disable SSCCTL */
3367 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3368 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3369 SBI_SSCCTL_DISABLE,
3370 SBI_ICLK);
3371
3372 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3373 if (clock == 20000) {
3374 auxdiv = 1;
3375 divsel = 0x41;
3376 phaseinc = 0x20;
3377 } else {
3378 /* The iCLK virtual clock root frequency is in MHz,
3379 * but the adjusted_mode->crtc_clock in in KHz. To get the
3380 * divisors, it is necessary to divide one by another, so we
3381 * convert the virtual clock precision to KHz here for higher
3382 * precision.
3383 */
3384 u32 iclk_virtual_root_freq = 172800 * 1000;
3385 u32 iclk_pi_range = 64;
3386 u32 desired_divisor, msb_divisor_value, pi_value;
3387
3388 desired_divisor = (iclk_virtual_root_freq / clock);
3389 msb_divisor_value = desired_divisor / iclk_pi_range;
3390 pi_value = desired_divisor % iclk_pi_range;
3391
3392 auxdiv = 0;
3393 divsel = msb_divisor_value - 2;
3394 phaseinc = pi_value;
3395 }
3396
3397 /* This should not happen with any sane values */
3398 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3399 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3400 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3401 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3402
3403 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3404 clock,
3405 auxdiv,
3406 divsel,
3407 phasedir,
3408 phaseinc);
3409
3410 /* Program SSCDIVINTPHASE6 */
3411 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3412 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3413 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3414 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3415 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3416 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3417 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3418 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3419
3420 /* Program SSCAUXDIV */
3421 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3422 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3423 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3424 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3425
3426 /* Enable modulator and associated divider */
3427 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3428 temp &= ~SBI_SSCCTL_DISABLE;
3429 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3430
3431 /* Wait for initialization time */
3432 udelay(24);
3433
3434 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3435
3436 mutex_unlock(&dev_priv->dpio_lock);
3437 }
3438
3439 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3440 enum pipe pch_transcoder)
3441 {
3442 struct drm_device *dev = crtc->base.dev;
3443 struct drm_i915_private *dev_priv = dev->dev_private;
3444 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3445
3446 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3447 I915_READ(HTOTAL(cpu_transcoder)));
3448 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3449 I915_READ(HBLANK(cpu_transcoder)));
3450 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3451 I915_READ(HSYNC(cpu_transcoder)));
3452
3453 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3454 I915_READ(VTOTAL(cpu_transcoder)));
3455 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3456 I915_READ(VBLANK(cpu_transcoder)));
3457 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3458 I915_READ(VSYNC(cpu_transcoder)));
3459 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3460 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3461 }
3462
3463 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3464 {
3465 struct drm_i915_private *dev_priv = dev->dev_private;
3466 uint32_t temp;
3467
3468 temp = I915_READ(SOUTH_CHICKEN1);
3469 if (temp & FDI_BC_BIFURCATION_SELECT)
3470 return;
3471
3472 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3473 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3474
3475 temp |= FDI_BC_BIFURCATION_SELECT;
3476 DRM_DEBUG_KMS("enabling fdi C rx\n");
3477 I915_WRITE(SOUTH_CHICKEN1, temp);
3478 POSTING_READ(SOUTH_CHICKEN1);
3479 }
3480
3481 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3482 {
3483 struct drm_device *dev = intel_crtc->base.dev;
3484 struct drm_i915_private *dev_priv = dev->dev_private;
3485
3486 switch (intel_crtc->pipe) {
3487 case PIPE_A:
3488 break;
3489 case PIPE_B:
3490 if (intel_crtc->config.fdi_lanes > 2)
3491 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3492 else
3493 cpt_enable_fdi_bc_bifurcation(dev);
3494
3495 break;
3496 case PIPE_C:
3497 cpt_enable_fdi_bc_bifurcation(dev);
3498
3499 break;
3500 default:
3501 BUG();
3502 }
3503 }
3504
3505 /*
3506 * Enable PCH resources required for PCH ports:
3507 * - PCH PLLs
3508 * - FDI training & RX/TX
3509 * - update transcoder timings
3510 * - DP transcoding bits
3511 * - transcoder
3512 */
3513 static void ironlake_pch_enable(struct drm_crtc *crtc)
3514 {
3515 struct drm_device *dev = crtc->dev;
3516 struct drm_i915_private *dev_priv = dev->dev_private;
3517 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3518 int pipe = intel_crtc->pipe;
3519 u32 reg, temp;
3520
3521 assert_pch_transcoder_disabled(dev_priv, pipe);
3522
3523 if (IS_IVYBRIDGE(dev))
3524 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3525
3526 /* Write the TU size bits before fdi link training, so that error
3527 * detection works. */
3528 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3529 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3530
3531 /* For PCH output, training FDI link */
3532 dev_priv->display.fdi_link_train(crtc);
3533
3534 /* We need to program the right clock selection before writing the pixel
3535 * mutliplier into the DPLL. */
3536 if (HAS_PCH_CPT(dev)) {
3537 u32 sel;
3538
3539 temp = I915_READ(PCH_DPLL_SEL);
3540 temp |= TRANS_DPLL_ENABLE(pipe);
3541 sel = TRANS_DPLLB_SEL(pipe);
3542 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3543 temp |= sel;
3544 else
3545 temp &= ~sel;
3546 I915_WRITE(PCH_DPLL_SEL, temp);
3547 }
3548
3549 /* XXX: pch pll's can be enabled any time before we enable the PCH
3550 * transcoder, and we actually should do this to not upset any PCH
3551 * transcoder that already use the clock when we share it.
3552 *
3553 * Note that enable_shared_dpll tries to do the right thing, but
3554 * get_shared_dpll unconditionally resets the pll - we need that to have
3555 * the right LVDS enable sequence. */
3556 intel_enable_shared_dpll(intel_crtc);
3557
3558 /* set transcoder timing, panel must allow it */
3559 assert_panel_unlocked(dev_priv, pipe);
3560 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3561
3562 intel_fdi_normal_train(crtc);
3563
3564 /* For PCH DP, enable TRANS_DP_CTL */
3565 if (HAS_PCH_CPT(dev) &&
3566 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3567 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3568 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3569 reg = TRANS_DP_CTL(pipe);
3570 temp = I915_READ(reg);
3571 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3572 TRANS_DP_SYNC_MASK |
3573 TRANS_DP_BPC_MASK);
3574 temp |= (TRANS_DP_OUTPUT_ENABLE |
3575 TRANS_DP_ENH_FRAMING);
3576 temp |= bpc << 9; /* same format but at 11:9 */
3577
3578 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3579 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3580 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3581 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3582
3583 switch (intel_trans_dp_port_sel(crtc)) {
3584 case PCH_DP_B:
3585 temp |= TRANS_DP_PORT_SEL_B;
3586 break;
3587 case PCH_DP_C:
3588 temp |= TRANS_DP_PORT_SEL_C;
3589 break;
3590 case PCH_DP_D:
3591 temp |= TRANS_DP_PORT_SEL_D;
3592 break;
3593 default:
3594 BUG();
3595 }
3596
3597 I915_WRITE(reg, temp);
3598 }
3599
3600 ironlake_enable_pch_transcoder(dev_priv, pipe);
3601 }
3602
3603 static void lpt_pch_enable(struct drm_crtc *crtc)
3604 {
3605 struct drm_device *dev = crtc->dev;
3606 struct drm_i915_private *dev_priv = dev->dev_private;
3607 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3608 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3609
3610 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3611
3612 lpt_program_iclkip(crtc);
3613
3614 /* Set transcoder timing. */
3615 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3616
3617 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3618 }
3619
3620 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3621 {
3622 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3623
3624 if (pll == NULL)
3625 return;
3626
3627 if (pll->refcount == 0) {
3628 WARN(1, "bad %s refcount\n", pll->name);
3629 return;
3630 }
3631
3632 if (--pll->refcount == 0) {
3633 WARN_ON(pll->on);
3634 WARN_ON(pll->active);
3635 }
3636
3637 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3638 }
3639
3640 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3641 {
3642 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3643 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3644 enum intel_dpll_id i;
3645
3646 if (pll) {
3647 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3648 crtc->base.base.id, pll->name);
3649 intel_put_shared_dpll(crtc);
3650 }
3651
3652 if (HAS_PCH_IBX(dev_priv->dev)) {
3653 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3654 i = (enum intel_dpll_id) crtc->pipe;
3655 pll = &dev_priv->shared_dplls[i];
3656
3657 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3658 crtc->base.base.id, pll->name);
3659
3660 WARN_ON(pll->refcount);
3661
3662 goto found;
3663 }
3664
3665 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3666 pll = &dev_priv->shared_dplls[i];
3667
3668 /* Only want to check enabled timings first */
3669 if (pll->refcount == 0)
3670 continue;
3671
3672 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3673 sizeof(pll->hw_state)) == 0) {
3674 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3675 crtc->base.base.id,
3676 pll->name, pll->refcount, pll->active);
3677
3678 goto found;
3679 }
3680 }
3681
3682 /* Ok no matching timings, maybe there's a free one? */
3683 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3684 pll = &dev_priv->shared_dplls[i];
3685 if (pll->refcount == 0) {
3686 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3687 crtc->base.base.id, pll->name);
3688 goto found;
3689 }
3690 }
3691
3692 return NULL;
3693
3694 found:
3695 if (pll->refcount == 0)
3696 pll->hw_state = crtc->config.dpll_hw_state;
3697
3698 crtc->config.shared_dpll = i;
3699 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3700 pipe_name(crtc->pipe));
3701
3702 pll->refcount++;
3703
3704 return pll;
3705 }
3706
3707 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3708 {
3709 struct drm_i915_private *dev_priv = dev->dev_private;
3710 int dslreg = PIPEDSL(pipe);
3711 u32 temp;
3712
3713 temp = I915_READ(dslreg);
3714 udelay(500);
3715 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3716 if (wait_for(I915_READ(dslreg) != temp, 5))
3717 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3718 }
3719 }
3720
3721 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3722 {
3723 struct drm_device *dev = crtc->base.dev;
3724 struct drm_i915_private *dev_priv = dev->dev_private;
3725 int pipe = crtc->pipe;
3726
3727 if (crtc->config.pch_pfit.enabled) {
3728 /* Force use of hard-coded filter coefficients
3729 * as some pre-programmed values are broken,
3730 * e.g. x201.
3731 */
3732 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3733 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3734 PF_PIPE_SEL_IVB(pipe));
3735 else
3736 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3737 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3738 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3739 }
3740 }
3741
3742 static void intel_enable_planes(struct drm_crtc *crtc)
3743 {
3744 struct drm_device *dev = crtc->dev;
3745 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3746 struct drm_plane *plane;
3747 struct intel_plane *intel_plane;
3748
3749 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3750 intel_plane = to_intel_plane(plane);
3751 if (intel_plane->pipe == pipe)
3752 intel_plane_restore(&intel_plane->base);
3753 }
3754 }
3755
3756 static void intel_disable_planes(struct drm_crtc *crtc)
3757 {
3758 struct drm_device *dev = crtc->dev;
3759 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3760 struct drm_plane *plane;
3761 struct intel_plane *intel_plane;
3762
3763 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3764 intel_plane = to_intel_plane(plane);
3765 if (intel_plane->pipe == pipe)
3766 intel_plane_disable(&intel_plane->base);
3767 }
3768 }
3769
3770 void hsw_enable_ips(struct intel_crtc *crtc)
3771 {
3772 struct drm_device *dev = crtc->base.dev;
3773 struct drm_i915_private *dev_priv = dev->dev_private;
3774
3775 if (!crtc->config.ips_enabled)
3776 return;
3777
3778 /* We can only enable IPS after we enable a plane and wait for a vblank */
3779 intel_wait_for_vblank(dev, crtc->pipe);
3780
3781 assert_plane_enabled(dev_priv, crtc->plane);
3782 if (IS_BROADWELL(dev)) {
3783 mutex_lock(&dev_priv->rps.hw_lock);
3784 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3785 mutex_unlock(&dev_priv->rps.hw_lock);
3786 /* Quoting Art Runyan: "its not safe to expect any particular
3787 * value in IPS_CTL bit 31 after enabling IPS through the
3788 * mailbox." Moreover, the mailbox may return a bogus state,
3789 * so we need to just enable it and continue on.
3790 */
3791 } else {
3792 I915_WRITE(IPS_CTL, IPS_ENABLE);
3793 /* The bit only becomes 1 in the next vblank, so this wait here
3794 * is essentially intel_wait_for_vblank. If we don't have this
3795 * and don't wait for vblanks until the end of crtc_enable, then
3796 * the HW state readout code will complain that the expected
3797 * IPS_CTL value is not the one we read. */
3798 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3799 DRM_ERROR("Timed out waiting for IPS enable\n");
3800 }
3801 }
3802
3803 void hsw_disable_ips(struct intel_crtc *crtc)
3804 {
3805 struct drm_device *dev = crtc->base.dev;
3806 struct drm_i915_private *dev_priv = dev->dev_private;
3807
3808 if (!crtc->config.ips_enabled)
3809 return;
3810
3811 assert_plane_enabled(dev_priv, crtc->plane);
3812 if (IS_BROADWELL(dev)) {
3813 mutex_lock(&dev_priv->rps.hw_lock);
3814 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3815 mutex_unlock(&dev_priv->rps.hw_lock);
3816 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3817 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3818 DRM_ERROR("Timed out waiting for IPS disable\n");
3819 } else {
3820 I915_WRITE(IPS_CTL, 0);
3821 POSTING_READ(IPS_CTL);
3822 }
3823
3824 /* We need to wait for a vblank before we can disable the plane. */
3825 intel_wait_for_vblank(dev, crtc->pipe);
3826 }
3827
3828 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3829 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3830 {
3831 struct drm_device *dev = crtc->dev;
3832 struct drm_i915_private *dev_priv = dev->dev_private;
3833 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3834 enum pipe pipe = intel_crtc->pipe;
3835 int palreg = PALETTE(pipe);
3836 int i;
3837 bool reenable_ips = false;
3838
3839 /* The clocks have to be on to load the palette. */
3840 if (!crtc->enabled || !intel_crtc->active)
3841 return;
3842
3843 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3844 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3845 assert_dsi_pll_enabled(dev_priv);
3846 else
3847 assert_pll_enabled(dev_priv, pipe);
3848 }
3849
3850 /* use legacy palette for Ironlake */
3851 if (HAS_PCH_SPLIT(dev))
3852 palreg = LGC_PALETTE(pipe);
3853
3854 /* Workaround : Do not read or write the pipe palette/gamma data while
3855 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3856 */
3857 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3858 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3859 GAMMA_MODE_MODE_SPLIT)) {
3860 hsw_disable_ips(intel_crtc);
3861 reenable_ips = true;
3862 }
3863
3864 for (i = 0; i < 256; i++) {
3865 I915_WRITE(palreg + 4 * i,
3866 (intel_crtc->lut_r[i] << 16) |
3867 (intel_crtc->lut_g[i] << 8) |
3868 intel_crtc->lut_b[i]);
3869 }
3870
3871 if (reenable_ips)
3872 hsw_enable_ips(intel_crtc);
3873 }
3874
3875 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3876 {
3877 if (!enable && intel_crtc->overlay) {
3878 struct drm_device *dev = intel_crtc->base.dev;
3879 struct drm_i915_private *dev_priv = dev->dev_private;
3880
3881 mutex_lock(&dev->struct_mutex);
3882 dev_priv->mm.interruptible = false;
3883 (void) intel_overlay_switch_off(intel_crtc->overlay);
3884 dev_priv->mm.interruptible = true;
3885 mutex_unlock(&dev->struct_mutex);
3886 }
3887
3888 /* Let userspace switch the overlay on again. In most cases userspace
3889 * has to recompute where to put it anyway.
3890 */
3891 }
3892
3893 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
3894 {
3895 struct drm_device *dev = crtc->dev;
3896 struct drm_i915_private *dev_priv = dev->dev_private;
3897 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3898 int pipe = intel_crtc->pipe;
3899 int plane = intel_crtc->plane;
3900
3901 drm_vblank_on(dev, pipe);
3902
3903 intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3904 intel_enable_planes(crtc);
3905 intel_crtc_update_cursor(crtc, true);
3906 intel_crtc_dpms_overlay(intel_crtc, true);
3907
3908 hsw_enable_ips(intel_crtc);
3909
3910 mutex_lock(&dev->struct_mutex);
3911 intel_update_fbc(dev);
3912 mutex_unlock(&dev->struct_mutex);
3913
3914 /*
3915 * FIXME: Once we grow proper nuclear flip support out of this we need
3916 * to compute the mask of flip planes precisely. For the time being
3917 * consider this a flip from a NULL plane.
3918 */
3919 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
3920 }
3921
3922 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
3923 {
3924 struct drm_device *dev = crtc->dev;
3925 struct drm_i915_private *dev_priv = dev->dev_private;
3926 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3927 int pipe = intel_crtc->pipe;
3928 int plane = intel_crtc->plane;
3929
3930 intel_crtc_wait_for_pending_flips(crtc);
3931
3932 if (dev_priv->fbc.plane == plane)
3933 intel_disable_fbc(dev);
3934
3935 hsw_disable_ips(intel_crtc);
3936
3937 intel_crtc_dpms_overlay(intel_crtc, false);
3938 intel_crtc_update_cursor(crtc, false);
3939 intel_disable_planes(crtc);
3940 intel_disable_primary_hw_plane(dev_priv, plane, pipe);
3941
3942 /*
3943 * FIXME: Once we grow proper nuclear flip support out of this we need
3944 * to compute the mask of flip planes precisely. For the time being
3945 * consider this a flip to a NULL plane.
3946 */
3947 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
3948
3949 drm_vblank_off(dev, pipe);
3950 }
3951
3952 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3953 {
3954 struct drm_device *dev = crtc->dev;
3955 struct drm_i915_private *dev_priv = dev->dev_private;
3956 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3957 struct intel_encoder *encoder;
3958 int pipe = intel_crtc->pipe;
3959 enum plane plane = intel_crtc->plane;
3960
3961 WARN_ON(!crtc->enabled);
3962
3963 if (intel_crtc->active)
3964 return;
3965
3966 if (intel_crtc->config.has_pch_encoder)
3967 intel_prepare_shared_dpll(intel_crtc);
3968
3969 if (intel_crtc->config.has_dp_encoder)
3970 intel_dp_set_m_n(intel_crtc);
3971
3972 intel_set_pipe_timings(intel_crtc);
3973
3974 if (intel_crtc->config.has_pch_encoder) {
3975 intel_cpu_transcoder_set_m_n(intel_crtc,
3976 &intel_crtc->config.fdi_m_n);
3977 }
3978
3979 ironlake_set_pipeconf(crtc);
3980
3981 /* Set up the display plane register */
3982 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
3983 POSTING_READ(DSPCNTR(plane));
3984
3985 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
3986 crtc->x, crtc->y);
3987
3988 intel_crtc->active = true;
3989
3990 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3991 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3992
3993 for_each_encoder_on_crtc(dev, crtc, encoder)
3994 if (encoder->pre_enable)
3995 encoder->pre_enable(encoder);
3996
3997 if (intel_crtc->config.has_pch_encoder) {
3998 /* Note: FDI PLL enabling _must_ be done before we enable the
3999 * cpu pipes, hence this is separate from all the other fdi/pch
4000 * enabling. */
4001 ironlake_fdi_pll_enable(intel_crtc);
4002 } else {
4003 assert_fdi_tx_disabled(dev_priv, pipe);
4004 assert_fdi_rx_disabled(dev_priv, pipe);
4005 }
4006
4007 ironlake_pfit_enable(intel_crtc);
4008
4009 /*
4010 * On ILK+ LUT must be loaded before the pipe is running but with
4011 * clocks enabled
4012 */
4013 intel_crtc_load_lut(crtc);
4014
4015 intel_update_watermarks(crtc);
4016 intel_enable_pipe(intel_crtc);
4017
4018 if (intel_crtc->config.has_pch_encoder)
4019 ironlake_pch_enable(crtc);
4020
4021 for_each_encoder_on_crtc(dev, crtc, encoder)
4022 encoder->enable(encoder);
4023
4024 if (HAS_PCH_CPT(dev))
4025 cpt_verify_modeset(dev, intel_crtc->pipe);
4026
4027 intel_crtc_enable_planes(crtc);
4028 }
4029
4030 /* IPS only exists on ULT machines and is tied to pipe A. */
4031 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4032 {
4033 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4034 }
4035
4036 /*
4037 * This implements the workaround described in the "notes" section of the mode
4038 * set sequence documentation. When going from no pipes or single pipe to
4039 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4040 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4041 */
4042 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4043 {
4044 struct drm_device *dev = crtc->base.dev;
4045 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4046
4047 /* We want to get the other_active_crtc only if there's only 1 other
4048 * active crtc. */
4049 for_each_intel_crtc(dev, crtc_it) {
4050 if (!crtc_it->active || crtc_it == crtc)
4051 continue;
4052
4053 if (other_active_crtc)
4054 return;
4055
4056 other_active_crtc = crtc_it;
4057 }
4058 if (!other_active_crtc)
4059 return;
4060
4061 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4062 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4063 }
4064
4065 static void haswell_crtc_enable(struct drm_crtc *crtc)
4066 {
4067 struct drm_device *dev = crtc->dev;
4068 struct drm_i915_private *dev_priv = dev->dev_private;
4069 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4070 struct intel_encoder *encoder;
4071 int pipe = intel_crtc->pipe;
4072 enum plane plane = intel_crtc->plane;
4073
4074 WARN_ON(!crtc->enabled);
4075
4076 if (intel_crtc->active)
4077 return;
4078
4079 if (intel_crtc->config.has_dp_encoder)
4080 intel_dp_set_m_n(intel_crtc);
4081
4082 intel_set_pipe_timings(intel_crtc);
4083
4084 if (intel_crtc->config.has_pch_encoder) {
4085 intel_cpu_transcoder_set_m_n(intel_crtc,
4086 &intel_crtc->config.fdi_m_n);
4087 }
4088
4089 haswell_set_pipeconf(crtc);
4090
4091 intel_set_pipe_csc(crtc);
4092
4093 /* Set up the display plane register */
4094 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
4095 POSTING_READ(DSPCNTR(plane));
4096
4097 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4098 crtc->x, crtc->y);
4099
4100 intel_crtc->active = true;
4101
4102 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4103 for_each_encoder_on_crtc(dev, crtc, encoder)
4104 if (encoder->pre_enable)
4105 encoder->pre_enable(encoder);
4106
4107 if (intel_crtc->config.has_pch_encoder) {
4108 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4109 dev_priv->display.fdi_link_train(crtc);
4110 }
4111
4112 intel_ddi_enable_pipe_clock(intel_crtc);
4113
4114 ironlake_pfit_enable(intel_crtc);
4115
4116 /*
4117 * On ILK+ LUT must be loaded before the pipe is running but with
4118 * clocks enabled
4119 */
4120 intel_crtc_load_lut(crtc);
4121
4122 intel_ddi_set_pipe_settings(crtc);
4123 intel_ddi_enable_transcoder_func(crtc);
4124
4125 intel_update_watermarks(crtc);
4126 intel_enable_pipe(intel_crtc);
4127
4128 if (intel_crtc->config.has_pch_encoder)
4129 lpt_pch_enable(crtc);
4130
4131 for_each_encoder_on_crtc(dev, crtc, encoder) {
4132 encoder->enable(encoder);
4133 intel_opregion_notify_encoder(encoder, true);
4134 }
4135
4136 /* If we change the relative order between pipe/planes enabling, we need
4137 * to change the workaround. */
4138 haswell_mode_set_planes_workaround(intel_crtc);
4139 intel_crtc_enable_planes(crtc);
4140 }
4141
4142 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4143 {
4144 struct drm_device *dev = crtc->base.dev;
4145 struct drm_i915_private *dev_priv = dev->dev_private;
4146 int pipe = crtc->pipe;
4147
4148 /* To avoid upsetting the power well on haswell only disable the pfit if
4149 * it's in use. The hw state code will make sure we get this right. */
4150 if (crtc->config.pch_pfit.enabled) {
4151 I915_WRITE(PF_CTL(pipe), 0);
4152 I915_WRITE(PF_WIN_POS(pipe), 0);
4153 I915_WRITE(PF_WIN_SZ(pipe), 0);
4154 }
4155 }
4156
4157 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4158 {
4159 struct drm_device *dev = crtc->dev;
4160 struct drm_i915_private *dev_priv = dev->dev_private;
4161 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4162 struct intel_encoder *encoder;
4163 int pipe = intel_crtc->pipe;
4164 u32 reg, temp;
4165
4166 if (!intel_crtc->active)
4167 return;
4168
4169 intel_crtc_disable_planes(crtc);
4170
4171 for_each_encoder_on_crtc(dev, crtc, encoder)
4172 encoder->disable(encoder);
4173
4174 if (intel_crtc->config.has_pch_encoder)
4175 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4176
4177 intel_disable_pipe(dev_priv, pipe);
4178
4179 ironlake_pfit_disable(intel_crtc);
4180
4181 for_each_encoder_on_crtc(dev, crtc, encoder)
4182 if (encoder->post_disable)
4183 encoder->post_disable(encoder);
4184
4185 if (intel_crtc->config.has_pch_encoder) {
4186 ironlake_fdi_disable(crtc);
4187
4188 ironlake_disable_pch_transcoder(dev_priv, pipe);
4189 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4190
4191 if (HAS_PCH_CPT(dev)) {
4192 /* disable TRANS_DP_CTL */
4193 reg = TRANS_DP_CTL(pipe);
4194 temp = I915_READ(reg);
4195 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4196 TRANS_DP_PORT_SEL_MASK);
4197 temp |= TRANS_DP_PORT_SEL_NONE;
4198 I915_WRITE(reg, temp);
4199
4200 /* disable DPLL_SEL */
4201 temp = I915_READ(PCH_DPLL_SEL);
4202 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4203 I915_WRITE(PCH_DPLL_SEL, temp);
4204 }
4205
4206 /* disable PCH DPLL */
4207 intel_disable_shared_dpll(intel_crtc);
4208
4209 ironlake_fdi_pll_disable(intel_crtc);
4210 }
4211
4212 intel_crtc->active = false;
4213 intel_update_watermarks(crtc);
4214
4215 mutex_lock(&dev->struct_mutex);
4216 intel_update_fbc(dev);
4217 mutex_unlock(&dev->struct_mutex);
4218 }
4219
4220 static void haswell_crtc_disable(struct drm_crtc *crtc)
4221 {
4222 struct drm_device *dev = crtc->dev;
4223 struct drm_i915_private *dev_priv = dev->dev_private;
4224 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4225 struct intel_encoder *encoder;
4226 int pipe = intel_crtc->pipe;
4227 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4228
4229 if (!intel_crtc->active)
4230 return;
4231
4232 intel_crtc_disable_planes(crtc);
4233
4234 for_each_encoder_on_crtc(dev, crtc, encoder) {
4235 intel_opregion_notify_encoder(encoder, false);
4236 encoder->disable(encoder);
4237 }
4238
4239 if (intel_crtc->config.has_pch_encoder)
4240 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4241 intel_disable_pipe(dev_priv, pipe);
4242
4243 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4244
4245 ironlake_pfit_disable(intel_crtc);
4246
4247 intel_ddi_disable_pipe_clock(intel_crtc);
4248
4249 for_each_encoder_on_crtc(dev, crtc, encoder)
4250 if (encoder->post_disable)
4251 encoder->post_disable(encoder);
4252
4253 if (intel_crtc->config.has_pch_encoder) {
4254 lpt_disable_pch_transcoder(dev_priv);
4255 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4256 intel_ddi_fdi_disable(crtc);
4257 }
4258
4259 intel_crtc->active = false;
4260 intel_update_watermarks(crtc);
4261
4262 mutex_lock(&dev->struct_mutex);
4263 intel_update_fbc(dev);
4264 mutex_unlock(&dev->struct_mutex);
4265 }
4266
4267 static void ironlake_crtc_off(struct drm_crtc *crtc)
4268 {
4269 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4270 intel_put_shared_dpll(intel_crtc);
4271 }
4272
4273 static void haswell_crtc_off(struct drm_crtc *crtc)
4274 {
4275 intel_ddi_put_crtc_pll(crtc);
4276 }
4277
4278 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4279 {
4280 struct drm_device *dev = crtc->base.dev;
4281 struct drm_i915_private *dev_priv = dev->dev_private;
4282 struct intel_crtc_config *pipe_config = &crtc->config;
4283
4284 if (!crtc->config.gmch_pfit.control)
4285 return;
4286
4287 /*
4288 * The panel fitter should only be adjusted whilst the pipe is disabled,
4289 * according to register description and PRM.
4290 */
4291 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4292 assert_pipe_disabled(dev_priv, crtc->pipe);
4293
4294 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4295 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4296
4297 /* Border color in case we don't scale up to the full screen. Black by
4298 * default, change to something else for debugging. */
4299 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4300 }
4301
4302 #define for_each_power_domain(domain, mask) \
4303 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4304 if ((1 << (domain)) & (mask))
4305
4306 enum intel_display_power_domain
4307 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4308 {
4309 struct drm_device *dev = intel_encoder->base.dev;
4310 struct intel_digital_port *intel_dig_port;
4311
4312 switch (intel_encoder->type) {
4313 case INTEL_OUTPUT_UNKNOWN:
4314 /* Only DDI platforms should ever use this output type */
4315 WARN_ON_ONCE(!HAS_DDI(dev));
4316 case INTEL_OUTPUT_DISPLAYPORT:
4317 case INTEL_OUTPUT_HDMI:
4318 case INTEL_OUTPUT_EDP:
4319 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4320 switch (intel_dig_port->port) {
4321 case PORT_A:
4322 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4323 case PORT_B:
4324 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4325 case PORT_C:
4326 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4327 case PORT_D:
4328 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4329 default:
4330 WARN_ON_ONCE(1);
4331 return POWER_DOMAIN_PORT_OTHER;
4332 }
4333 case INTEL_OUTPUT_ANALOG:
4334 return POWER_DOMAIN_PORT_CRT;
4335 case INTEL_OUTPUT_DSI:
4336 return POWER_DOMAIN_PORT_DSI;
4337 default:
4338 return POWER_DOMAIN_PORT_OTHER;
4339 }
4340 }
4341
4342 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4343 {
4344 struct drm_device *dev = crtc->dev;
4345 struct intel_encoder *intel_encoder;
4346 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4347 enum pipe pipe = intel_crtc->pipe;
4348 unsigned long mask;
4349 enum transcoder transcoder;
4350
4351 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4352
4353 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4354 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4355 if (intel_crtc->config.pch_pfit.enabled ||
4356 intel_crtc->config.pch_pfit.force_thru)
4357 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4358
4359 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4360 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4361
4362 return mask;
4363 }
4364
4365 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4366 bool enable)
4367 {
4368 if (dev_priv->power_domains.init_power_on == enable)
4369 return;
4370
4371 if (enable)
4372 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4373 else
4374 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4375
4376 dev_priv->power_domains.init_power_on = enable;
4377 }
4378
4379 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4380 {
4381 struct drm_i915_private *dev_priv = dev->dev_private;
4382 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4383 struct intel_crtc *crtc;
4384
4385 /*
4386 * First get all needed power domains, then put all unneeded, to avoid
4387 * any unnecessary toggling of the power wells.
4388 */
4389 for_each_intel_crtc(dev, crtc) {
4390 enum intel_display_power_domain domain;
4391
4392 if (!crtc->base.enabled)
4393 continue;
4394
4395 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4396
4397 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4398 intel_display_power_get(dev_priv, domain);
4399 }
4400
4401 for_each_intel_crtc(dev, crtc) {
4402 enum intel_display_power_domain domain;
4403
4404 for_each_power_domain(domain, crtc->enabled_power_domains)
4405 intel_display_power_put(dev_priv, domain);
4406
4407 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4408 }
4409
4410 intel_display_set_init_power(dev_priv, false);
4411 }
4412
4413 /* returns HPLL frequency in kHz */
4414 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4415 {
4416 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4417
4418 /* Obtain SKU information */
4419 mutex_lock(&dev_priv->dpio_lock);
4420 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4421 CCK_FUSE_HPLL_FREQ_MASK;
4422 mutex_unlock(&dev_priv->dpio_lock);
4423
4424 return vco_freq[hpll_freq] * 1000;
4425 }
4426
4427 static void vlv_update_cdclk(struct drm_device *dev)
4428 {
4429 struct drm_i915_private *dev_priv = dev->dev_private;
4430
4431 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4432 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz",
4433 dev_priv->vlv_cdclk_freq);
4434
4435 /*
4436 * Program the gmbus_freq based on the cdclk frequency.
4437 * BSpec erroneously claims we should aim for 4MHz, but
4438 * in fact 1MHz is the correct frequency.
4439 */
4440 I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
4441 }
4442
4443 /* Adjust CDclk dividers to allow high res or save power if possible */
4444 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4445 {
4446 struct drm_i915_private *dev_priv = dev->dev_private;
4447 u32 val, cmd;
4448
4449 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4450
4451 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4452 cmd = 2;
4453 else if (cdclk == 266667)
4454 cmd = 1;
4455 else
4456 cmd = 0;
4457
4458 mutex_lock(&dev_priv->rps.hw_lock);
4459 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4460 val &= ~DSPFREQGUAR_MASK;
4461 val |= (cmd << DSPFREQGUAR_SHIFT);
4462 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4463 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4464 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4465 50)) {
4466 DRM_ERROR("timed out waiting for CDclk change\n");
4467 }
4468 mutex_unlock(&dev_priv->rps.hw_lock);
4469
4470 if (cdclk == 400000) {
4471 u32 divider, vco;
4472
4473 vco = valleyview_get_vco(dev_priv);
4474 divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1;
4475
4476 mutex_lock(&dev_priv->dpio_lock);
4477 /* adjust cdclk divider */
4478 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4479 val &= ~DISPLAY_FREQUENCY_VALUES;
4480 val |= divider;
4481 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4482
4483 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4484 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4485 50))
4486 DRM_ERROR("timed out waiting for CDclk change\n");
4487 mutex_unlock(&dev_priv->dpio_lock);
4488 }
4489
4490 mutex_lock(&dev_priv->dpio_lock);
4491 /* adjust self-refresh exit latency value */
4492 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4493 val &= ~0x7f;
4494
4495 /*
4496 * For high bandwidth configs, we set a higher latency in the bunit
4497 * so that the core display fetch happens in time to avoid underruns.
4498 */
4499 if (cdclk == 400000)
4500 val |= 4500 / 250; /* 4.5 usec */
4501 else
4502 val |= 3000 / 250; /* 3.0 usec */
4503 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4504 mutex_unlock(&dev_priv->dpio_lock);
4505
4506 vlv_update_cdclk(dev);
4507 }
4508
4509 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4510 int max_pixclk)
4511 {
4512 int vco = valleyview_get_vco(dev_priv);
4513 int freq_320 = (vco << 1) % 320000 != 0 ? 333333 : 320000;
4514
4515 /*
4516 * Really only a few cases to deal with, as only 4 CDclks are supported:
4517 * 200MHz
4518 * 267MHz
4519 * 320/333MHz (depends on HPLL freq)
4520 * 400MHz
4521 * So we check to see whether we're above 90% of the lower bin and
4522 * adjust if needed.
4523 *
4524 * We seem to get an unstable or solid color picture at 200MHz.
4525 * Not sure what's wrong. For now use 200MHz only when all pipes
4526 * are off.
4527 */
4528 if (max_pixclk > freq_320*9/10)
4529 return 400000;
4530 else if (max_pixclk > 266667*9/10)
4531 return freq_320;
4532 else if (max_pixclk > 0)
4533 return 266667;
4534 else
4535 return 200000;
4536 }
4537
4538 /* compute the max pixel clock for new configuration */
4539 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4540 {
4541 struct drm_device *dev = dev_priv->dev;
4542 struct intel_crtc *intel_crtc;
4543 int max_pixclk = 0;
4544
4545 for_each_intel_crtc(dev, intel_crtc) {
4546 if (intel_crtc->new_enabled)
4547 max_pixclk = max(max_pixclk,
4548 intel_crtc->new_config->adjusted_mode.crtc_clock);
4549 }
4550
4551 return max_pixclk;
4552 }
4553
4554 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4555 unsigned *prepare_pipes)
4556 {
4557 struct drm_i915_private *dev_priv = dev->dev_private;
4558 struct intel_crtc *intel_crtc;
4559 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4560
4561 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4562 dev_priv->vlv_cdclk_freq)
4563 return;
4564
4565 /* disable/enable all currently active pipes while we change cdclk */
4566 for_each_intel_crtc(dev, intel_crtc)
4567 if (intel_crtc->base.enabled)
4568 *prepare_pipes |= (1 << intel_crtc->pipe);
4569 }
4570
4571 static void valleyview_modeset_global_resources(struct drm_device *dev)
4572 {
4573 struct drm_i915_private *dev_priv = dev->dev_private;
4574 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4575 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4576
4577 if (req_cdclk != dev_priv->vlv_cdclk_freq)
4578 valleyview_set_cdclk(dev, req_cdclk);
4579 modeset_update_crtc_power_domains(dev);
4580 }
4581
4582 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4583 {
4584 struct drm_device *dev = crtc->dev;
4585 struct drm_i915_private *dev_priv = dev->dev_private;
4586 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4587 struct intel_encoder *encoder;
4588 int pipe = intel_crtc->pipe;
4589 int plane = intel_crtc->plane;
4590 bool is_dsi;
4591 u32 dspcntr;
4592
4593 WARN_ON(!crtc->enabled);
4594
4595 if (intel_crtc->active)
4596 return;
4597
4598 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4599
4600 if (!is_dsi && !IS_CHERRYVIEW(dev))
4601 vlv_prepare_pll(intel_crtc);
4602
4603 /* Set up the display plane register */
4604 dspcntr = DISPPLANE_GAMMA_ENABLE;
4605
4606 if (intel_crtc->config.has_dp_encoder)
4607 intel_dp_set_m_n(intel_crtc);
4608
4609 intel_set_pipe_timings(intel_crtc);
4610
4611 /* pipesrc and dspsize control the size that is scaled from,
4612 * which should always be the user's requested size.
4613 */
4614 I915_WRITE(DSPSIZE(plane),
4615 ((intel_crtc->config.pipe_src_h - 1) << 16) |
4616 (intel_crtc->config.pipe_src_w - 1));
4617 I915_WRITE(DSPPOS(plane), 0);
4618
4619 i9xx_set_pipeconf(intel_crtc);
4620
4621 I915_WRITE(DSPCNTR(plane), dspcntr);
4622 POSTING_READ(DSPCNTR(plane));
4623
4624 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4625 crtc->x, crtc->y);
4626
4627 intel_crtc->active = true;
4628
4629 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4630
4631 for_each_encoder_on_crtc(dev, crtc, encoder)
4632 if (encoder->pre_pll_enable)
4633 encoder->pre_pll_enable(encoder);
4634
4635 if (!is_dsi) {
4636 if (IS_CHERRYVIEW(dev))
4637 chv_enable_pll(intel_crtc);
4638 else
4639 vlv_enable_pll(intel_crtc);
4640 }
4641
4642 for_each_encoder_on_crtc(dev, crtc, encoder)
4643 if (encoder->pre_enable)
4644 encoder->pre_enable(encoder);
4645
4646 i9xx_pfit_enable(intel_crtc);
4647
4648 intel_crtc_load_lut(crtc);
4649
4650 intel_update_watermarks(crtc);
4651 intel_enable_pipe(intel_crtc);
4652
4653 for_each_encoder_on_crtc(dev, crtc, encoder)
4654 encoder->enable(encoder);
4655
4656 intel_crtc_enable_planes(crtc);
4657
4658 /* Underruns don't raise interrupts, so check manually. */
4659 i9xx_check_fifo_underruns(dev);
4660 }
4661
4662 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4663 {
4664 struct drm_device *dev = crtc->base.dev;
4665 struct drm_i915_private *dev_priv = dev->dev_private;
4666
4667 I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4668 I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4669 }
4670
4671 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4672 {
4673 struct drm_device *dev = crtc->dev;
4674 struct drm_i915_private *dev_priv = dev->dev_private;
4675 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4676 struct intel_encoder *encoder;
4677 int pipe = intel_crtc->pipe;
4678 int plane = intel_crtc->plane;
4679 u32 dspcntr;
4680
4681 WARN_ON(!crtc->enabled);
4682
4683 if (intel_crtc->active)
4684 return;
4685
4686 i9xx_set_pll_dividers(intel_crtc);
4687
4688 /* Set up the display plane register */
4689 dspcntr = DISPPLANE_GAMMA_ENABLE;
4690
4691 if (pipe == 0)
4692 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4693 else
4694 dspcntr |= DISPPLANE_SEL_PIPE_B;
4695
4696 if (intel_crtc->config.has_dp_encoder)
4697 intel_dp_set_m_n(intel_crtc);
4698
4699 intel_set_pipe_timings(intel_crtc);
4700
4701 /* pipesrc and dspsize control the size that is scaled from,
4702 * which should always be the user's requested size.
4703 */
4704 I915_WRITE(DSPSIZE(plane),
4705 ((intel_crtc->config.pipe_src_h - 1) << 16) |
4706 (intel_crtc->config.pipe_src_w - 1));
4707 I915_WRITE(DSPPOS(plane), 0);
4708
4709 i9xx_set_pipeconf(intel_crtc);
4710
4711 I915_WRITE(DSPCNTR(plane), dspcntr);
4712 POSTING_READ(DSPCNTR(plane));
4713
4714 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4715 crtc->x, crtc->y);
4716
4717 intel_crtc->active = true;
4718
4719 if (!IS_GEN2(dev))
4720 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4721
4722 for_each_encoder_on_crtc(dev, crtc, encoder)
4723 if (encoder->pre_enable)
4724 encoder->pre_enable(encoder);
4725
4726 i9xx_enable_pll(intel_crtc);
4727
4728 i9xx_pfit_enable(intel_crtc);
4729
4730 intel_crtc_load_lut(crtc);
4731
4732 intel_update_watermarks(crtc);
4733 intel_enable_pipe(intel_crtc);
4734
4735 for_each_encoder_on_crtc(dev, crtc, encoder)
4736 encoder->enable(encoder);
4737
4738 intel_crtc_enable_planes(crtc);
4739
4740 /*
4741 * Gen2 reports pipe underruns whenever all planes are disabled.
4742 * So don't enable underrun reporting before at least some planes
4743 * are enabled.
4744 * FIXME: Need to fix the logic to work when we turn off all planes
4745 * but leave the pipe running.
4746 */
4747 if (IS_GEN2(dev))
4748 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4749
4750 /* Underruns don't raise interrupts, so check manually. */
4751 i9xx_check_fifo_underruns(dev);
4752 }
4753
4754 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4755 {
4756 struct drm_device *dev = crtc->base.dev;
4757 struct drm_i915_private *dev_priv = dev->dev_private;
4758
4759 if (!crtc->config.gmch_pfit.control)
4760 return;
4761
4762 assert_pipe_disabled(dev_priv, crtc->pipe);
4763
4764 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4765 I915_READ(PFIT_CONTROL));
4766 I915_WRITE(PFIT_CONTROL, 0);
4767 }
4768
4769 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4770 {
4771 struct drm_device *dev = crtc->dev;
4772 struct drm_i915_private *dev_priv = dev->dev_private;
4773 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4774 struct intel_encoder *encoder;
4775 int pipe = intel_crtc->pipe;
4776
4777 if (!intel_crtc->active)
4778 return;
4779
4780 /*
4781 * Gen2 reports pipe underruns whenever all planes are disabled.
4782 * So diasble underrun reporting before all the planes get disabled.
4783 * FIXME: Need to fix the logic to work when we turn off all planes
4784 * but leave the pipe running.
4785 */
4786 if (IS_GEN2(dev))
4787 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4788
4789 /*
4790 * Vblank time updates from the shadow to live plane control register
4791 * are blocked if the memory self-refresh mode is active at that
4792 * moment. So to make sure the plane gets truly disabled, disable
4793 * first the self-refresh mode. The self-refresh enable bit in turn
4794 * will be checked/applied by the HW only at the next frame start
4795 * event which is after the vblank start event, so we need to have a
4796 * wait-for-vblank between disabling the plane and the pipe.
4797 */
4798 intel_set_memory_cxsr(dev_priv, false);
4799 intel_crtc_disable_planes(crtc);
4800
4801 for_each_encoder_on_crtc(dev, crtc, encoder)
4802 encoder->disable(encoder);
4803
4804 /*
4805 * On gen2 planes are double buffered but the pipe isn't, so we must
4806 * wait for planes to fully turn off before disabling the pipe.
4807 * We also need to wait on all gmch platforms because of the
4808 * self-refresh mode constraint explained above.
4809 */
4810 intel_wait_for_vblank(dev, pipe);
4811
4812 intel_disable_pipe(dev_priv, pipe);
4813
4814 i9xx_pfit_disable(intel_crtc);
4815
4816 for_each_encoder_on_crtc(dev, crtc, encoder)
4817 if (encoder->post_disable)
4818 encoder->post_disable(encoder);
4819
4820 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4821 if (IS_CHERRYVIEW(dev))
4822 chv_disable_pll(dev_priv, pipe);
4823 else if (IS_VALLEYVIEW(dev))
4824 vlv_disable_pll(dev_priv, pipe);
4825 else
4826 i9xx_disable_pll(dev_priv, pipe);
4827 }
4828
4829 if (!IS_GEN2(dev))
4830 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4831
4832 intel_crtc->active = false;
4833 intel_update_watermarks(crtc);
4834
4835 mutex_lock(&dev->struct_mutex);
4836 intel_update_fbc(dev);
4837 mutex_unlock(&dev->struct_mutex);
4838 }
4839
4840 static void i9xx_crtc_off(struct drm_crtc *crtc)
4841 {
4842 }
4843
4844 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4845 bool enabled)
4846 {
4847 struct drm_device *dev = crtc->dev;
4848 struct drm_i915_master_private *master_priv;
4849 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4850 int pipe = intel_crtc->pipe;
4851
4852 if (!dev->primary->master)
4853 return;
4854
4855 master_priv = dev->primary->master->driver_priv;
4856 if (!master_priv->sarea_priv)
4857 return;
4858
4859 switch (pipe) {
4860 case 0:
4861 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4862 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4863 break;
4864 case 1:
4865 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4866 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4867 break;
4868 default:
4869 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4870 break;
4871 }
4872 }
4873
4874 /**
4875 * Sets the power management mode of the pipe and plane.
4876 */
4877 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4878 {
4879 struct drm_device *dev = crtc->dev;
4880 struct drm_i915_private *dev_priv = dev->dev_private;
4881 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4882 struct intel_encoder *intel_encoder;
4883 enum intel_display_power_domain domain;
4884 unsigned long domains;
4885 bool enable = false;
4886
4887 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4888 enable |= intel_encoder->connectors_active;
4889
4890 if (enable) {
4891 if (!intel_crtc->active) {
4892 /*
4893 * FIXME: DDI plls and relevant code isn't converted
4894 * yet, so do runtime PM for DPMS only for all other
4895 * platforms for now.
4896 */
4897 if (!HAS_DDI(dev)) {
4898 domains = get_crtc_power_domains(crtc);
4899 for_each_power_domain(domain, domains)
4900 intel_display_power_get(dev_priv, domain);
4901 intel_crtc->enabled_power_domains = domains;
4902 }
4903
4904 dev_priv->display.crtc_enable(crtc);
4905 }
4906 } else {
4907 if (intel_crtc->active) {
4908 dev_priv->display.crtc_disable(crtc);
4909
4910 if (!HAS_DDI(dev)) {
4911 domains = intel_crtc->enabled_power_domains;
4912 for_each_power_domain(domain, domains)
4913 intel_display_power_put(dev_priv, domain);
4914 intel_crtc->enabled_power_domains = 0;
4915 }
4916 }
4917 }
4918
4919 intel_crtc_update_sarea(crtc, enable);
4920 }
4921
4922 static void intel_crtc_disable(struct drm_crtc *crtc)
4923 {
4924 struct drm_device *dev = crtc->dev;
4925 struct drm_connector *connector;
4926 struct drm_i915_private *dev_priv = dev->dev_private;
4927 struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
4928 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4929
4930 /* crtc should still be enabled when we disable it. */
4931 WARN_ON(!crtc->enabled);
4932
4933 dev_priv->display.crtc_disable(crtc);
4934 intel_crtc_update_sarea(crtc, false);
4935 dev_priv->display.off(crtc);
4936
4937 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4938 assert_cursor_disabled(dev_priv, pipe);
4939 assert_pipe_disabled(dev->dev_private, pipe);
4940
4941 if (crtc->primary->fb) {
4942 mutex_lock(&dev->struct_mutex);
4943 intel_unpin_fb_obj(old_obj);
4944 i915_gem_track_fb(old_obj, NULL,
4945 INTEL_FRONTBUFFER_PRIMARY(pipe));
4946 mutex_unlock(&dev->struct_mutex);
4947 crtc->primary->fb = NULL;
4948 }
4949
4950 /* Update computed state. */
4951 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4952 if (!connector->encoder || !connector->encoder->crtc)
4953 continue;
4954
4955 if (connector->encoder->crtc != crtc)
4956 continue;
4957
4958 connector->dpms = DRM_MODE_DPMS_OFF;
4959 to_intel_encoder(connector->encoder)->connectors_active = false;
4960 }
4961 }
4962
4963 void intel_encoder_destroy(struct drm_encoder *encoder)
4964 {
4965 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4966
4967 drm_encoder_cleanup(encoder);
4968 kfree(intel_encoder);
4969 }
4970
4971 /* Simple dpms helper for encoders with just one connector, no cloning and only
4972 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4973 * state of the entire output pipe. */
4974 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4975 {
4976 if (mode == DRM_MODE_DPMS_ON) {
4977 encoder->connectors_active = true;
4978
4979 intel_crtc_update_dpms(encoder->base.crtc);
4980 } else {
4981 encoder->connectors_active = false;
4982
4983 intel_crtc_update_dpms(encoder->base.crtc);
4984 }
4985 }
4986
4987 /* Cross check the actual hw state with our own modeset state tracking (and it's
4988 * internal consistency). */
4989 static void intel_connector_check_state(struct intel_connector *connector)
4990 {
4991 if (connector->get_hw_state(connector)) {
4992 struct intel_encoder *encoder = connector->encoder;
4993 struct drm_crtc *crtc;
4994 bool encoder_enabled;
4995 enum pipe pipe;
4996
4997 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4998 connector->base.base.id,
4999 connector->base.name);
5000
5001 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5002 "wrong connector dpms state\n");
5003 WARN(connector->base.encoder != &encoder->base,
5004 "active connector not linked to encoder\n");
5005 WARN(!encoder->connectors_active,
5006 "encoder->connectors_active not set\n");
5007
5008 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5009 WARN(!encoder_enabled, "encoder not enabled\n");
5010 if (WARN_ON(!encoder->base.crtc))
5011 return;
5012
5013 crtc = encoder->base.crtc;
5014
5015 WARN(!crtc->enabled, "crtc not enabled\n");
5016 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5017 WARN(pipe != to_intel_crtc(crtc)->pipe,
5018 "encoder active on the wrong pipe\n");
5019 }
5020 }
5021
5022 /* Even simpler default implementation, if there's really no special case to
5023 * consider. */
5024 void intel_connector_dpms(struct drm_connector *connector, int mode)
5025 {
5026 /* All the simple cases only support two dpms states. */
5027 if (mode != DRM_MODE_DPMS_ON)
5028 mode = DRM_MODE_DPMS_OFF;
5029
5030 if (mode == connector->dpms)
5031 return;
5032
5033 connector->dpms = mode;
5034
5035 /* Only need to change hw state when actually enabled */
5036 if (connector->encoder)
5037 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5038
5039 intel_modeset_check_state(connector->dev);
5040 }
5041
5042 /* Simple connector->get_hw_state implementation for encoders that support only
5043 * one connector and no cloning and hence the encoder state determines the state
5044 * of the connector. */
5045 bool intel_connector_get_hw_state(struct intel_connector *connector)
5046 {
5047 enum pipe pipe = 0;
5048 struct intel_encoder *encoder = connector->encoder;
5049
5050 return encoder->get_hw_state(encoder, &pipe);
5051 }
5052
5053 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5054 struct intel_crtc_config *pipe_config)
5055 {
5056 struct drm_i915_private *dev_priv = dev->dev_private;
5057 struct intel_crtc *pipe_B_crtc =
5058 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5059
5060 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5061 pipe_name(pipe), pipe_config->fdi_lanes);
5062 if (pipe_config->fdi_lanes > 4) {
5063 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5064 pipe_name(pipe), pipe_config->fdi_lanes);
5065 return false;
5066 }
5067
5068 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5069 if (pipe_config->fdi_lanes > 2) {
5070 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5071 pipe_config->fdi_lanes);
5072 return false;
5073 } else {
5074 return true;
5075 }
5076 }
5077
5078 if (INTEL_INFO(dev)->num_pipes == 2)
5079 return true;
5080
5081 /* Ivybridge 3 pipe is really complicated */
5082 switch (pipe) {
5083 case PIPE_A:
5084 return true;
5085 case PIPE_B:
5086 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5087 pipe_config->fdi_lanes > 2) {
5088 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5089 pipe_name(pipe), pipe_config->fdi_lanes);
5090 return false;
5091 }
5092 return true;
5093 case PIPE_C:
5094 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5095 pipe_B_crtc->config.fdi_lanes <= 2) {
5096 if (pipe_config->fdi_lanes > 2) {
5097 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5098 pipe_name(pipe), pipe_config->fdi_lanes);
5099 return false;
5100 }
5101 } else {
5102 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5103 return false;
5104 }
5105 return true;
5106 default:
5107 BUG();
5108 }
5109 }
5110
5111 #define RETRY 1
5112 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5113 struct intel_crtc_config *pipe_config)
5114 {
5115 struct drm_device *dev = intel_crtc->base.dev;
5116 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5117 int lane, link_bw, fdi_dotclock;
5118 bool setup_ok, needs_recompute = false;
5119
5120 retry:
5121 /* FDI is a binary signal running at ~2.7GHz, encoding
5122 * each output octet as 10 bits. The actual frequency
5123 * is stored as a divider into a 100MHz clock, and the
5124 * mode pixel clock is stored in units of 1KHz.
5125 * Hence the bw of each lane in terms of the mode signal
5126 * is:
5127 */
5128 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5129
5130 fdi_dotclock = adjusted_mode->crtc_clock;
5131
5132 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5133 pipe_config->pipe_bpp);
5134
5135 pipe_config->fdi_lanes = lane;
5136
5137 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5138 link_bw, &pipe_config->fdi_m_n);
5139
5140 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5141 intel_crtc->pipe, pipe_config);
5142 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5143 pipe_config->pipe_bpp -= 2*3;
5144 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5145 pipe_config->pipe_bpp);
5146 needs_recompute = true;
5147 pipe_config->bw_constrained = true;
5148
5149 goto retry;
5150 }
5151
5152 if (needs_recompute)
5153 return RETRY;
5154
5155 return setup_ok ? 0 : -EINVAL;
5156 }
5157
5158 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5159 struct intel_crtc_config *pipe_config)
5160 {
5161 pipe_config->ips_enabled = i915.enable_ips &&
5162 hsw_crtc_supports_ips(crtc) &&
5163 pipe_config->pipe_bpp <= 24;
5164 }
5165
5166 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5167 struct intel_crtc_config *pipe_config)
5168 {
5169 struct drm_device *dev = crtc->base.dev;
5170 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5171
5172 /* FIXME should check pixel clock limits on all platforms */
5173 if (INTEL_INFO(dev)->gen < 4) {
5174 struct drm_i915_private *dev_priv = dev->dev_private;
5175 int clock_limit =
5176 dev_priv->display.get_display_clock_speed(dev);
5177
5178 /*
5179 * Enable pixel doubling when the dot clock
5180 * is > 90% of the (display) core speed.
5181 *
5182 * GDG double wide on either pipe,
5183 * otherwise pipe A only.
5184 */
5185 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5186 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5187 clock_limit *= 2;
5188 pipe_config->double_wide = true;
5189 }
5190
5191 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5192 return -EINVAL;
5193 }
5194
5195 /*
5196 * Pipe horizontal size must be even in:
5197 * - DVO ganged mode
5198 * - LVDS dual channel mode
5199 * - Double wide pipe
5200 */
5201 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5202 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5203 pipe_config->pipe_src_w &= ~1;
5204
5205 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5206 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5207 */
5208 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5209 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5210 return -EINVAL;
5211
5212 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5213 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5214 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5215 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5216 * for lvds. */
5217 pipe_config->pipe_bpp = 8*3;
5218 }
5219
5220 if (HAS_IPS(dev))
5221 hsw_compute_ips_config(crtc, pipe_config);
5222
5223 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
5224 * clock survives for now. */
5225 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5226 pipe_config->shared_dpll = crtc->config.shared_dpll;
5227
5228 if (pipe_config->has_pch_encoder)
5229 return ironlake_fdi_compute_config(crtc, pipe_config);
5230
5231 return 0;
5232 }
5233
5234 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5235 {
5236 struct drm_i915_private *dev_priv = dev->dev_private;
5237 int vco = valleyview_get_vco(dev_priv);
5238 u32 val;
5239 int divider;
5240
5241 mutex_lock(&dev_priv->dpio_lock);
5242 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5243 mutex_unlock(&dev_priv->dpio_lock);
5244
5245 divider = val & DISPLAY_FREQUENCY_VALUES;
5246
5247 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5248 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5249 "cdclk change in progress\n");
5250
5251 return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
5252 }
5253
5254 static int i945_get_display_clock_speed(struct drm_device *dev)
5255 {
5256 return 400000;
5257 }
5258
5259 static int i915_get_display_clock_speed(struct drm_device *dev)
5260 {
5261 return 333000;
5262 }
5263
5264 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5265 {
5266 return 200000;
5267 }
5268
5269 static int pnv_get_display_clock_speed(struct drm_device *dev)
5270 {
5271 u16 gcfgc = 0;
5272
5273 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5274
5275 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5276 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5277 return 267000;
5278 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5279 return 333000;
5280 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5281 return 444000;
5282 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5283 return 200000;
5284 default:
5285 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5286 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5287 return 133000;
5288 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5289 return 167000;
5290 }
5291 }
5292
5293 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5294 {
5295 u16 gcfgc = 0;
5296
5297 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5298
5299 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5300 return 133000;
5301 else {
5302 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5303 case GC_DISPLAY_CLOCK_333_MHZ:
5304 return 333000;
5305 default:
5306 case GC_DISPLAY_CLOCK_190_200_MHZ:
5307 return 190000;
5308 }
5309 }
5310 }
5311
5312 static int i865_get_display_clock_speed(struct drm_device *dev)
5313 {
5314 return 266000;
5315 }
5316
5317 static int i855_get_display_clock_speed(struct drm_device *dev)
5318 {
5319 u16 hpllcc = 0;
5320 /* Assume that the hardware is in the high speed state. This
5321 * should be the default.
5322 */
5323 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5324 case GC_CLOCK_133_200:
5325 case GC_CLOCK_100_200:
5326 return 200000;
5327 case GC_CLOCK_166_250:
5328 return 250000;
5329 case GC_CLOCK_100_133:
5330 return 133000;
5331 }
5332
5333 /* Shouldn't happen */
5334 return 0;
5335 }
5336
5337 static int i830_get_display_clock_speed(struct drm_device *dev)
5338 {
5339 return 133000;
5340 }
5341
5342 static void
5343 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5344 {
5345 while (*num > DATA_LINK_M_N_MASK ||
5346 *den > DATA_LINK_M_N_MASK) {
5347 *num >>= 1;
5348 *den >>= 1;
5349 }
5350 }
5351
5352 static void compute_m_n(unsigned int m, unsigned int n,
5353 uint32_t *ret_m, uint32_t *ret_n)
5354 {
5355 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5356 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5357 intel_reduce_m_n_ratio(ret_m, ret_n);
5358 }
5359
5360 void
5361 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5362 int pixel_clock, int link_clock,
5363 struct intel_link_m_n *m_n)
5364 {
5365 m_n->tu = 64;
5366
5367 compute_m_n(bits_per_pixel * pixel_clock,
5368 link_clock * nlanes * 8,
5369 &m_n->gmch_m, &m_n->gmch_n);
5370
5371 compute_m_n(pixel_clock, link_clock,
5372 &m_n->link_m, &m_n->link_n);
5373 }
5374
5375 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5376 {
5377 if (i915.panel_use_ssc >= 0)
5378 return i915.panel_use_ssc != 0;
5379 return dev_priv->vbt.lvds_use_ssc
5380 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5381 }
5382
5383 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5384 {
5385 struct drm_device *dev = crtc->dev;
5386 struct drm_i915_private *dev_priv = dev->dev_private;
5387 int refclk;
5388
5389 if (IS_VALLEYVIEW(dev)) {
5390 refclk = 100000;
5391 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5392 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5393 refclk = dev_priv->vbt.lvds_ssc_freq;
5394 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5395 } else if (!IS_GEN2(dev)) {
5396 refclk = 96000;
5397 } else {
5398 refclk = 48000;
5399 }
5400
5401 return refclk;
5402 }
5403
5404 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5405 {
5406 return (1 << dpll->n) << 16 | dpll->m2;
5407 }
5408
5409 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5410 {
5411 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5412 }
5413
5414 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5415 intel_clock_t *reduced_clock)
5416 {
5417 struct drm_device *dev = crtc->base.dev;
5418 u32 fp, fp2 = 0;
5419
5420 if (IS_PINEVIEW(dev)) {
5421 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5422 if (reduced_clock)
5423 fp2 = pnv_dpll_compute_fp(reduced_clock);
5424 } else {
5425 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5426 if (reduced_clock)
5427 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5428 }
5429
5430 crtc->config.dpll_hw_state.fp0 = fp;
5431
5432 crtc->lowfreq_avail = false;
5433 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5434 reduced_clock && i915.powersave) {
5435 crtc->config.dpll_hw_state.fp1 = fp2;
5436 crtc->lowfreq_avail = true;
5437 } else {
5438 crtc->config.dpll_hw_state.fp1 = fp;
5439 }
5440 }
5441
5442 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5443 pipe)
5444 {
5445 u32 reg_val;
5446
5447 /*
5448 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5449 * and set it to a reasonable value instead.
5450 */
5451 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5452 reg_val &= 0xffffff00;
5453 reg_val |= 0x00000030;
5454 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5455
5456 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5457 reg_val &= 0x8cffffff;
5458 reg_val = 0x8c000000;
5459 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5460
5461 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5462 reg_val &= 0xffffff00;
5463 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5464
5465 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5466 reg_val &= 0x00ffffff;
5467 reg_val |= 0xb0000000;
5468 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5469 }
5470
5471 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5472 struct intel_link_m_n *m_n)
5473 {
5474 struct drm_device *dev = crtc->base.dev;
5475 struct drm_i915_private *dev_priv = dev->dev_private;
5476 int pipe = crtc->pipe;
5477
5478 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5479 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5480 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5481 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5482 }
5483
5484 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5485 struct intel_link_m_n *m_n)
5486 {
5487 struct drm_device *dev = crtc->base.dev;
5488 struct drm_i915_private *dev_priv = dev->dev_private;
5489 int pipe = crtc->pipe;
5490 enum transcoder transcoder = crtc->config.cpu_transcoder;
5491
5492 if (INTEL_INFO(dev)->gen >= 5) {
5493 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5494 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5495 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5496 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5497 } else {
5498 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5499 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5500 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5501 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5502 }
5503 }
5504
5505 static void intel_dp_set_m_n(struct intel_crtc *crtc)
5506 {
5507 if (crtc->config.has_pch_encoder)
5508 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5509 else
5510 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5511 }
5512
5513 static void vlv_update_pll(struct intel_crtc *crtc)
5514 {
5515 u32 dpll, dpll_md;
5516
5517 /*
5518 * Enable DPIO clock input. We should never disable the reference
5519 * clock for pipe B, since VGA hotplug / manual detection depends
5520 * on it.
5521 */
5522 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5523 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5524 /* We should never disable this, set it here for state tracking */
5525 if (crtc->pipe == PIPE_B)
5526 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5527 dpll |= DPLL_VCO_ENABLE;
5528 crtc->config.dpll_hw_state.dpll = dpll;
5529
5530 dpll_md = (crtc->config.pixel_multiplier - 1)
5531 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5532 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5533 }
5534
5535 static void vlv_prepare_pll(struct intel_crtc *crtc)
5536 {
5537 struct drm_device *dev = crtc->base.dev;
5538 struct drm_i915_private *dev_priv = dev->dev_private;
5539 int pipe = crtc->pipe;
5540 u32 mdiv;
5541 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5542 u32 coreclk, reg_val;
5543
5544 mutex_lock(&dev_priv->dpio_lock);
5545
5546 bestn = crtc->config.dpll.n;
5547 bestm1 = crtc->config.dpll.m1;
5548 bestm2 = crtc->config.dpll.m2;
5549 bestp1 = crtc->config.dpll.p1;
5550 bestp2 = crtc->config.dpll.p2;
5551
5552 /* See eDP HDMI DPIO driver vbios notes doc */
5553
5554 /* PLL B needs special handling */
5555 if (pipe == PIPE_B)
5556 vlv_pllb_recal_opamp(dev_priv, pipe);
5557
5558 /* Set up Tx target for periodic Rcomp update */
5559 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5560
5561 /* Disable target IRef on PLL */
5562 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5563 reg_val &= 0x00ffffff;
5564 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5565
5566 /* Disable fast lock */
5567 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5568
5569 /* Set idtafcrecal before PLL is enabled */
5570 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5571 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5572 mdiv |= ((bestn << DPIO_N_SHIFT));
5573 mdiv |= (1 << DPIO_K_SHIFT);
5574
5575 /*
5576 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5577 * but we don't support that).
5578 * Note: don't use the DAC post divider as it seems unstable.
5579 */
5580 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5581 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5582
5583 mdiv |= DPIO_ENABLE_CALIBRATION;
5584 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5585
5586 /* Set HBR and RBR LPF coefficients */
5587 if (crtc->config.port_clock == 162000 ||
5588 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5589 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5590 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5591 0x009f0003);
5592 else
5593 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5594 0x00d0000f);
5595
5596 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5597 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5598 /* Use SSC source */
5599 if (pipe == PIPE_A)
5600 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5601 0x0df40000);
5602 else
5603 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5604 0x0df70000);
5605 } else { /* HDMI or VGA */
5606 /* Use bend source */
5607 if (pipe == PIPE_A)
5608 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5609 0x0df70000);
5610 else
5611 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5612 0x0df40000);
5613 }
5614
5615 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5616 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5617 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5618 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5619 coreclk |= 0x01000000;
5620 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5621
5622 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5623 mutex_unlock(&dev_priv->dpio_lock);
5624 }
5625
5626 static void chv_update_pll(struct intel_crtc *crtc)
5627 {
5628 struct drm_device *dev = crtc->base.dev;
5629 struct drm_i915_private *dev_priv = dev->dev_private;
5630 int pipe = crtc->pipe;
5631 int dpll_reg = DPLL(crtc->pipe);
5632 enum dpio_channel port = vlv_pipe_to_channel(pipe);
5633 u32 loopfilter, intcoeff;
5634 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5635 int refclk;
5636
5637 crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5638 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5639 DPLL_VCO_ENABLE;
5640 if (pipe != PIPE_A)
5641 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5642
5643 crtc->config.dpll_hw_state.dpll_md =
5644 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5645
5646 bestn = crtc->config.dpll.n;
5647 bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5648 bestm1 = crtc->config.dpll.m1;
5649 bestm2 = crtc->config.dpll.m2 >> 22;
5650 bestp1 = crtc->config.dpll.p1;
5651 bestp2 = crtc->config.dpll.p2;
5652
5653 /*
5654 * Enable Refclk and SSC
5655 */
5656 I915_WRITE(dpll_reg,
5657 crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5658
5659 mutex_lock(&dev_priv->dpio_lock);
5660
5661 /* p1 and p2 divider */
5662 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5663 5 << DPIO_CHV_S1_DIV_SHIFT |
5664 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5665 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5666 1 << DPIO_CHV_K_DIV_SHIFT);
5667
5668 /* Feedback post-divider - m2 */
5669 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5670
5671 /* Feedback refclk divider - n and m1 */
5672 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5673 DPIO_CHV_M1_DIV_BY_2 |
5674 1 << DPIO_CHV_N_DIV_SHIFT);
5675
5676 /* M2 fraction division */
5677 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5678
5679 /* M2 fraction division enable */
5680 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5681 DPIO_CHV_FRAC_DIV_EN |
5682 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5683
5684 /* Loop filter */
5685 refclk = i9xx_get_refclk(&crtc->base, 0);
5686 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5687 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5688 if (refclk == 100000)
5689 intcoeff = 11;
5690 else if (refclk == 38400)
5691 intcoeff = 10;
5692 else
5693 intcoeff = 9;
5694 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5695 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5696
5697 /* AFC Recal */
5698 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5699 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5700 DPIO_AFC_RECAL);
5701
5702 mutex_unlock(&dev_priv->dpio_lock);
5703 }
5704
5705 static void i9xx_update_pll(struct intel_crtc *crtc,
5706 intel_clock_t *reduced_clock,
5707 int num_connectors)
5708 {
5709 struct drm_device *dev = crtc->base.dev;
5710 struct drm_i915_private *dev_priv = dev->dev_private;
5711 u32 dpll;
5712 bool is_sdvo;
5713 struct dpll *clock = &crtc->config.dpll;
5714
5715 i9xx_update_pll_dividers(crtc, reduced_clock);
5716
5717 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5718 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5719
5720 dpll = DPLL_VGA_MODE_DIS;
5721
5722 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5723 dpll |= DPLLB_MODE_LVDS;
5724 else
5725 dpll |= DPLLB_MODE_DAC_SERIAL;
5726
5727 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5728 dpll |= (crtc->config.pixel_multiplier - 1)
5729 << SDVO_MULTIPLIER_SHIFT_HIRES;
5730 }
5731
5732 if (is_sdvo)
5733 dpll |= DPLL_SDVO_HIGH_SPEED;
5734
5735 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5736 dpll |= DPLL_SDVO_HIGH_SPEED;
5737
5738 /* compute bitmask from p1 value */
5739 if (IS_PINEVIEW(dev))
5740 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5741 else {
5742 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5743 if (IS_G4X(dev) && reduced_clock)
5744 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5745 }
5746 switch (clock->p2) {
5747 case 5:
5748 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5749 break;
5750 case 7:
5751 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5752 break;
5753 case 10:
5754 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5755 break;
5756 case 14:
5757 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5758 break;
5759 }
5760 if (INTEL_INFO(dev)->gen >= 4)
5761 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5762
5763 if (crtc->config.sdvo_tv_clock)
5764 dpll |= PLL_REF_INPUT_TVCLKINBC;
5765 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5766 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5767 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5768 else
5769 dpll |= PLL_REF_INPUT_DREFCLK;
5770
5771 dpll |= DPLL_VCO_ENABLE;
5772 crtc->config.dpll_hw_state.dpll = dpll;
5773
5774 if (INTEL_INFO(dev)->gen >= 4) {
5775 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5776 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5777 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5778 }
5779 }
5780
5781 static void i8xx_update_pll(struct intel_crtc *crtc,
5782 intel_clock_t *reduced_clock,
5783 int num_connectors)
5784 {
5785 struct drm_device *dev = crtc->base.dev;
5786 struct drm_i915_private *dev_priv = dev->dev_private;
5787 u32 dpll;
5788 struct dpll *clock = &crtc->config.dpll;
5789
5790 i9xx_update_pll_dividers(crtc, reduced_clock);
5791
5792 dpll = DPLL_VGA_MODE_DIS;
5793
5794 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5795 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5796 } else {
5797 if (clock->p1 == 2)
5798 dpll |= PLL_P1_DIVIDE_BY_TWO;
5799 else
5800 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5801 if (clock->p2 == 4)
5802 dpll |= PLL_P2_DIVIDE_BY_4;
5803 }
5804
5805 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5806 dpll |= DPLL_DVO_2X_MODE;
5807
5808 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5809 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5810 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5811 else
5812 dpll |= PLL_REF_INPUT_DREFCLK;
5813
5814 dpll |= DPLL_VCO_ENABLE;
5815 crtc->config.dpll_hw_state.dpll = dpll;
5816 }
5817
5818 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5819 {
5820 struct drm_device *dev = intel_crtc->base.dev;
5821 struct drm_i915_private *dev_priv = dev->dev_private;
5822 enum pipe pipe = intel_crtc->pipe;
5823 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5824 struct drm_display_mode *adjusted_mode =
5825 &intel_crtc->config.adjusted_mode;
5826 uint32_t crtc_vtotal, crtc_vblank_end;
5827 int vsyncshift = 0;
5828
5829 /* We need to be careful not to changed the adjusted mode, for otherwise
5830 * the hw state checker will get angry at the mismatch. */
5831 crtc_vtotal = adjusted_mode->crtc_vtotal;
5832 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5833
5834 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5835 /* the chip adds 2 halflines automatically */
5836 crtc_vtotal -= 1;
5837 crtc_vblank_end -= 1;
5838
5839 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5840 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5841 else
5842 vsyncshift = adjusted_mode->crtc_hsync_start -
5843 adjusted_mode->crtc_htotal / 2;
5844 if (vsyncshift < 0)
5845 vsyncshift += adjusted_mode->crtc_htotal;
5846 }
5847
5848 if (INTEL_INFO(dev)->gen > 3)
5849 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5850
5851 I915_WRITE(HTOTAL(cpu_transcoder),
5852 (adjusted_mode->crtc_hdisplay - 1) |
5853 ((adjusted_mode->crtc_htotal - 1) << 16));
5854 I915_WRITE(HBLANK(cpu_transcoder),
5855 (adjusted_mode->crtc_hblank_start - 1) |
5856 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5857 I915_WRITE(HSYNC(cpu_transcoder),
5858 (adjusted_mode->crtc_hsync_start - 1) |
5859 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5860
5861 I915_WRITE(VTOTAL(cpu_transcoder),
5862 (adjusted_mode->crtc_vdisplay - 1) |
5863 ((crtc_vtotal - 1) << 16));
5864 I915_WRITE(VBLANK(cpu_transcoder),
5865 (adjusted_mode->crtc_vblank_start - 1) |
5866 ((crtc_vblank_end - 1) << 16));
5867 I915_WRITE(VSYNC(cpu_transcoder),
5868 (adjusted_mode->crtc_vsync_start - 1) |
5869 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5870
5871 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5872 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5873 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5874 * bits. */
5875 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5876 (pipe == PIPE_B || pipe == PIPE_C))
5877 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5878
5879 /* pipesrc controls the size that is scaled from, which should
5880 * always be the user's requested size.
5881 */
5882 I915_WRITE(PIPESRC(pipe),
5883 ((intel_crtc->config.pipe_src_w - 1) << 16) |
5884 (intel_crtc->config.pipe_src_h - 1));
5885 }
5886
5887 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5888 struct intel_crtc_config *pipe_config)
5889 {
5890 struct drm_device *dev = crtc->base.dev;
5891 struct drm_i915_private *dev_priv = dev->dev_private;
5892 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5893 uint32_t tmp;
5894
5895 tmp = I915_READ(HTOTAL(cpu_transcoder));
5896 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5897 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5898 tmp = I915_READ(HBLANK(cpu_transcoder));
5899 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5900 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5901 tmp = I915_READ(HSYNC(cpu_transcoder));
5902 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5903 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5904
5905 tmp = I915_READ(VTOTAL(cpu_transcoder));
5906 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5907 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5908 tmp = I915_READ(VBLANK(cpu_transcoder));
5909 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5910 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5911 tmp = I915_READ(VSYNC(cpu_transcoder));
5912 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5913 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5914
5915 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5916 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5917 pipe_config->adjusted_mode.crtc_vtotal += 1;
5918 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5919 }
5920
5921 tmp = I915_READ(PIPESRC(crtc->pipe));
5922 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5923 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5924
5925 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5926 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5927 }
5928
5929 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5930 struct intel_crtc_config *pipe_config)
5931 {
5932 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5933 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5934 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5935 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5936
5937 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5938 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5939 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5940 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5941
5942 mode->flags = pipe_config->adjusted_mode.flags;
5943
5944 mode->clock = pipe_config->adjusted_mode.crtc_clock;
5945 mode->flags |= pipe_config->adjusted_mode.flags;
5946 }
5947
5948 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5949 {
5950 struct drm_device *dev = intel_crtc->base.dev;
5951 struct drm_i915_private *dev_priv = dev->dev_private;
5952 uint32_t pipeconf;
5953
5954 pipeconf = 0;
5955
5956 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5957 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5958 pipeconf |= PIPECONF_ENABLE;
5959
5960 if (intel_crtc->config.double_wide)
5961 pipeconf |= PIPECONF_DOUBLE_WIDE;
5962
5963 /* only g4x and later have fancy bpc/dither controls */
5964 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5965 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5966 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5967 pipeconf |= PIPECONF_DITHER_EN |
5968 PIPECONF_DITHER_TYPE_SP;
5969
5970 switch (intel_crtc->config.pipe_bpp) {
5971 case 18:
5972 pipeconf |= PIPECONF_6BPC;
5973 break;
5974 case 24:
5975 pipeconf |= PIPECONF_8BPC;
5976 break;
5977 case 30:
5978 pipeconf |= PIPECONF_10BPC;
5979 break;
5980 default:
5981 /* Case prevented by intel_choose_pipe_bpp_dither. */
5982 BUG();
5983 }
5984 }
5985
5986 if (HAS_PIPE_CXSR(dev)) {
5987 if (intel_crtc->lowfreq_avail) {
5988 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5989 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5990 } else {
5991 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5992 }
5993 }
5994
5995 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
5996 if (INTEL_INFO(dev)->gen < 4 ||
5997 intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5998 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5999 else
6000 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6001 } else
6002 pipeconf |= PIPECONF_PROGRESSIVE;
6003
6004 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6005 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6006
6007 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6008 POSTING_READ(PIPECONF(intel_crtc->pipe));
6009 }
6010
6011 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
6012 int x, int y,
6013 struct drm_framebuffer *fb)
6014 {
6015 struct drm_device *dev = crtc->dev;
6016 struct drm_i915_private *dev_priv = dev->dev_private;
6017 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6018 int refclk, num_connectors = 0;
6019 intel_clock_t clock, reduced_clock;
6020 bool ok, has_reduced_clock = false;
6021 bool is_lvds = false, is_dsi = false;
6022 struct intel_encoder *encoder;
6023 const intel_limit_t *limit;
6024
6025 for_each_encoder_on_crtc(dev, crtc, encoder) {
6026 switch (encoder->type) {
6027 case INTEL_OUTPUT_LVDS:
6028 is_lvds = true;
6029 break;
6030 case INTEL_OUTPUT_DSI:
6031 is_dsi = true;
6032 break;
6033 }
6034
6035 num_connectors++;
6036 }
6037
6038 if (is_dsi)
6039 return 0;
6040
6041 if (!intel_crtc->config.clock_set) {
6042 refclk = i9xx_get_refclk(crtc, num_connectors);
6043
6044 /*
6045 * Returns a set of divisors for the desired target clock with
6046 * the given refclk, or FALSE. The returned values represent
6047 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6048 * 2) / p1 / p2.
6049 */
6050 limit = intel_limit(crtc, refclk);
6051 ok = dev_priv->display.find_dpll(limit, crtc,
6052 intel_crtc->config.port_clock,
6053 refclk, NULL, &clock);
6054 if (!ok) {
6055 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6056 return -EINVAL;
6057 }
6058
6059 if (is_lvds && dev_priv->lvds_downclock_avail) {
6060 /*
6061 * Ensure we match the reduced clock's P to the target
6062 * clock. If the clocks don't match, we can't switch
6063 * the display clock by using the FP0/FP1. In such case
6064 * we will disable the LVDS downclock feature.
6065 */
6066 has_reduced_clock =
6067 dev_priv->display.find_dpll(limit, crtc,
6068 dev_priv->lvds_downclock,
6069 refclk, &clock,
6070 &reduced_clock);
6071 }
6072 /* Compat-code for transition, will disappear. */
6073 intel_crtc->config.dpll.n = clock.n;
6074 intel_crtc->config.dpll.m1 = clock.m1;
6075 intel_crtc->config.dpll.m2 = clock.m2;
6076 intel_crtc->config.dpll.p1 = clock.p1;
6077 intel_crtc->config.dpll.p2 = clock.p2;
6078 }
6079
6080 if (IS_GEN2(dev)) {
6081 i8xx_update_pll(intel_crtc,
6082 has_reduced_clock ? &reduced_clock : NULL,
6083 num_connectors);
6084 } else if (IS_CHERRYVIEW(dev)) {
6085 chv_update_pll(intel_crtc);
6086 } else if (IS_VALLEYVIEW(dev)) {
6087 vlv_update_pll(intel_crtc);
6088 } else {
6089 i9xx_update_pll(intel_crtc,
6090 has_reduced_clock ? &reduced_clock : NULL,
6091 num_connectors);
6092 }
6093
6094 return 0;
6095 }
6096
6097 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6098 struct intel_crtc_config *pipe_config)
6099 {
6100 struct drm_device *dev = crtc->base.dev;
6101 struct drm_i915_private *dev_priv = dev->dev_private;
6102 uint32_t tmp;
6103
6104 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6105 return;
6106
6107 tmp = I915_READ(PFIT_CONTROL);
6108 if (!(tmp & PFIT_ENABLE))
6109 return;
6110
6111 /* Check whether the pfit is attached to our pipe. */
6112 if (INTEL_INFO(dev)->gen < 4) {
6113 if (crtc->pipe != PIPE_B)
6114 return;
6115 } else {
6116 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6117 return;
6118 }
6119
6120 pipe_config->gmch_pfit.control = tmp;
6121 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6122 if (INTEL_INFO(dev)->gen < 5)
6123 pipe_config->gmch_pfit.lvds_border_bits =
6124 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6125 }
6126
6127 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6128 struct intel_crtc_config *pipe_config)
6129 {
6130 struct drm_device *dev = crtc->base.dev;
6131 struct drm_i915_private *dev_priv = dev->dev_private;
6132 int pipe = pipe_config->cpu_transcoder;
6133 intel_clock_t clock;
6134 u32 mdiv;
6135 int refclk = 100000;
6136
6137 mutex_lock(&dev_priv->dpio_lock);
6138 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6139 mutex_unlock(&dev_priv->dpio_lock);
6140
6141 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6142 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6143 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6144 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6145 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6146
6147 vlv_clock(refclk, &clock);
6148
6149 /* clock.dot is the fast clock */
6150 pipe_config->port_clock = clock.dot / 5;
6151 }
6152
6153 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6154 struct intel_plane_config *plane_config)
6155 {
6156 struct drm_device *dev = crtc->base.dev;
6157 struct drm_i915_private *dev_priv = dev->dev_private;
6158 u32 val, base, offset;
6159 int pipe = crtc->pipe, plane = crtc->plane;
6160 int fourcc, pixel_format;
6161 int aligned_height;
6162
6163 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6164 if (!crtc->base.primary->fb) {
6165 DRM_DEBUG_KMS("failed to alloc fb\n");
6166 return;
6167 }
6168
6169 val = I915_READ(DSPCNTR(plane));
6170
6171 if (INTEL_INFO(dev)->gen >= 4)
6172 if (val & DISPPLANE_TILED)
6173 plane_config->tiled = true;
6174
6175 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6176 fourcc = intel_format_to_fourcc(pixel_format);
6177 crtc->base.primary->fb->pixel_format = fourcc;
6178 crtc->base.primary->fb->bits_per_pixel =
6179 drm_format_plane_cpp(fourcc, 0) * 8;
6180
6181 if (INTEL_INFO(dev)->gen >= 4) {
6182 if (plane_config->tiled)
6183 offset = I915_READ(DSPTILEOFF(plane));
6184 else
6185 offset = I915_READ(DSPLINOFF(plane));
6186 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6187 } else {
6188 base = I915_READ(DSPADDR(plane));
6189 }
6190 plane_config->base = base;
6191
6192 val = I915_READ(PIPESRC(pipe));
6193 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6194 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6195
6196 val = I915_READ(DSPSTRIDE(pipe));
6197 crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
6198
6199 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6200 plane_config->tiled);
6201
6202 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6203 aligned_height);
6204
6205 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6206 pipe, plane, crtc->base.primary->fb->width,
6207 crtc->base.primary->fb->height,
6208 crtc->base.primary->fb->bits_per_pixel, base,
6209 crtc->base.primary->fb->pitches[0],
6210 plane_config->size);
6211
6212 }
6213
6214 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6215 struct intel_crtc_config *pipe_config)
6216 {
6217 struct drm_device *dev = crtc->base.dev;
6218 struct drm_i915_private *dev_priv = dev->dev_private;
6219 int pipe = pipe_config->cpu_transcoder;
6220 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6221 intel_clock_t clock;
6222 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6223 int refclk = 100000;
6224
6225 mutex_lock(&dev_priv->dpio_lock);
6226 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6227 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6228 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6229 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6230 mutex_unlock(&dev_priv->dpio_lock);
6231
6232 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6233 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6234 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6235 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6236 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6237
6238 chv_clock(refclk, &clock);
6239
6240 /* clock.dot is the fast clock */
6241 pipe_config->port_clock = clock.dot / 5;
6242 }
6243
6244 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6245 struct intel_crtc_config *pipe_config)
6246 {
6247 struct drm_device *dev = crtc->base.dev;
6248 struct drm_i915_private *dev_priv = dev->dev_private;
6249 uint32_t tmp;
6250
6251 if (!intel_display_power_enabled(dev_priv,
6252 POWER_DOMAIN_PIPE(crtc->pipe)))
6253 return false;
6254
6255 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6256 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6257
6258 tmp = I915_READ(PIPECONF(crtc->pipe));
6259 if (!(tmp & PIPECONF_ENABLE))
6260 return false;
6261
6262 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6263 switch (tmp & PIPECONF_BPC_MASK) {
6264 case PIPECONF_6BPC:
6265 pipe_config->pipe_bpp = 18;
6266 break;
6267 case PIPECONF_8BPC:
6268 pipe_config->pipe_bpp = 24;
6269 break;
6270 case PIPECONF_10BPC:
6271 pipe_config->pipe_bpp = 30;
6272 break;
6273 default:
6274 break;
6275 }
6276 }
6277
6278 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6279 pipe_config->limited_color_range = true;
6280
6281 if (INTEL_INFO(dev)->gen < 4)
6282 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6283
6284 intel_get_pipe_timings(crtc, pipe_config);
6285
6286 i9xx_get_pfit_config(crtc, pipe_config);
6287
6288 if (INTEL_INFO(dev)->gen >= 4) {
6289 tmp = I915_READ(DPLL_MD(crtc->pipe));
6290 pipe_config->pixel_multiplier =
6291 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6292 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6293 pipe_config->dpll_hw_state.dpll_md = tmp;
6294 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6295 tmp = I915_READ(DPLL(crtc->pipe));
6296 pipe_config->pixel_multiplier =
6297 ((tmp & SDVO_MULTIPLIER_MASK)
6298 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6299 } else {
6300 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6301 * port and will be fixed up in the encoder->get_config
6302 * function. */
6303 pipe_config->pixel_multiplier = 1;
6304 }
6305 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6306 if (!IS_VALLEYVIEW(dev)) {
6307 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6308 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6309 } else {
6310 /* Mask out read-only status bits. */
6311 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6312 DPLL_PORTC_READY_MASK |
6313 DPLL_PORTB_READY_MASK);
6314 }
6315
6316 if (IS_CHERRYVIEW(dev))
6317 chv_crtc_clock_get(crtc, pipe_config);
6318 else if (IS_VALLEYVIEW(dev))
6319 vlv_crtc_clock_get(crtc, pipe_config);
6320 else
6321 i9xx_crtc_clock_get(crtc, pipe_config);
6322
6323 return true;
6324 }
6325
6326 static void ironlake_init_pch_refclk(struct drm_device *dev)
6327 {
6328 struct drm_i915_private *dev_priv = dev->dev_private;
6329 struct drm_mode_config *mode_config = &dev->mode_config;
6330 struct intel_encoder *encoder;
6331 u32 val, final;
6332 bool has_lvds = false;
6333 bool has_cpu_edp = false;
6334 bool has_panel = false;
6335 bool has_ck505 = false;
6336 bool can_ssc = false;
6337
6338 /* We need to take the global config into account */
6339 list_for_each_entry(encoder, &mode_config->encoder_list,
6340 base.head) {
6341 switch (encoder->type) {
6342 case INTEL_OUTPUT_LVDS:
6343 has_panel = true;
6344 has_lvds = true;
6345 break;
6346 case INTEL_OUTPUT_EDP:
6347 has_panel = true;
6348 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6349 has_cpu_edp = true;
6350 break;
6351 }
6352 }
6353
6354 if (HAS_PCH_IBX(dev)) {
6355 has_ck505 = dev_priv->vbt.display_clock_mode;
6356 can_ssc = has_ck505;
6357 } else {
6358 has_ck505 = false;
6359 can_ssc = true;
6360 }
6361
6362 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6363 has_panel, has_lvds, has_ck505);
6364
6365 /* Ironlake: try to setup display ref clock before DPLL
6366 * enabling. This is only under driver's control after
6367 * PCH B stepping, previous chipset stepping should be
6368 * ignoring this setting.
6369 */
6370 val = I915_READ(PCH_DREF_CONTROL);
6371
6372 /* As we must carefully and slowly disable/enable each source in turn,
6373 * compute the final state we want first and check if we need to
6374 * make any changes at all.
6375 */
6376 final = val;
6377 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6378 if (has_ck505)
6379 final |= DREF_NONSPREAD_CK505_ENABLE;
6380 else
6381 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6382
6383 final &= ~DREF_SSC_SOURCE_MASK;
6384 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6385 final &= ~DREF_SSC1_ENABLE;
6386
6387 if (has_panel) {
6388 final |= DREF_SSC_SOURCE_ENABLE;
6389
6390 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6391 final |= DREF_SSC1_ENABLE;
6392
6393 if (has_cpu_edp) {
6394 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6395 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6396 else
6397 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6398 } else
6399 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6400 } else {
6401 final |= DREF_SSC_SOURCE_DISABLE;
6402 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6403 }
6404
6405 if (final == val)
6406 return;
6407
6408 /* Always enable nonspread source */
6409 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6410
6411 if (has_ck505)
6412 val |= DREF_NONSPREAD_CK505_ENABLE;
6413 else
6414 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6415
6416 if (has_panel) {
6417 val &= ~DREF_SSC_SOURCE_MASK;
6418 val |= DREF_SSC_SOURCE_ENABLE;
6419
6420 /* SSC must be turned on before enabling the CPU output */
6421 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6422 DRM_DEBUG_KMS("Using SSC on panel\n");
6423 val |= DREF_SSC1_ENABLE;
6424 } else
6425 val &= ~DREF_SSC1_ENABLE;
6426
6427 /* Get SSC going before enabling the outputs */
6428 I915_WRITE(PCH_DREF_CONTROL, val);
6429 POSTING_READ(PCH_DREF_CONTROL);
6430 udelay(200);
6431
6432 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6433
6434 /* Enable CPU source on CPU attached eDP */
6435 if (has_cpu_edp) {
6436 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6437 DRM_DEBUG_KMS("Using SSC on eDP\n");
6438 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6439 } else
6440 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6441 } else
6442 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6443
6444 I915_WRITE(PCH_DREF_CONTROL, val);
6445 POSTING_READ(PCH_DREF_CONTROL);
6446 udelay(200);
6447 } else {
6448 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6449
6450 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6451
6452 /* Turn off CPU output */
6453 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6454
6455 I915_WRITE(PCH_DREF_CONTROL, val);
6456 POSTING_READ(PCH_DREF_CONTROL);
6457 udelay(200);
6458
6459 /* Turn off the SSC source */
6460 val &= ~DREF_SSC_SOURCE_MASK;
6461 val |= DREF_SSC_SOURCE_DISABLE;
6462
6463 /* Turn off SSC1 */
6464 val &= ~DREF_SSC1_ENABLE;
6465
6466 I915_WRITE(PCH_DREF_CONTROL, val);
6467 POSTING_READ(PCH_DREF_CONTROL);
6468 udelay(200);
6469 }
6470
6471 BUG_ON(val != final);
6472 }
6473
6474 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6475 {
6476 uint32_t tmp;
6477
6478 tmp = I915_READ(SOUTH_CHICKEN2);
6479 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6480 I915_WRITE(SOUTH_CHICKEN2, tmp);
6481
6482 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6483 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6484 DRM_ERROR("FDI mPHY reset assert timeout\n");
6485
6486 tmp = I915_READ(SOUTH_CHICKEN2);
6487 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6488 I915_WRITE(SOUTH_CHICKEN2, tmp);
6489
6490 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6491 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6492 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6493 }
6494
6495 /* WaMPhyProgramming:hsw */
6496 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6497 {
6498 uint32_t tmp;
6499
6500 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6501 tmp &= ~(0xFF << 24);
6502 tmp |= (0x12 << 24);
6503 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6504
6505 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6506 tmp |= (1 << 11);
6507 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6508
6509 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6510 tmp |= (1 << 11);
6511 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6512
6513 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6514 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6515 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6516
6517 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6518 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6519 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6520
6521 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6522 tmp &= ~(7 << 13);
6523 tmp |= (5 << 13);
6524 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6525
6526 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6527 tmp &= ~(7 << 13);
6528 tmp |= (5 << 13);
6529 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6530
6531 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6532 tmp &= ~0xFF;
6533 tmp |= 0x1C;
6534 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6535
6536 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6537 tmp &= ~0xFF;
6538 tmp |= 0x1C;
6539 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6540
6541 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6542 tmp &= ~(0xFF << 16);
6543 tmp |= (0x1C << 16);
6544 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6545
6546 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6547 tmp &= ~(0xFF << 16);
6548 tmp |= (0x1C << 16);
6549 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6550
6551 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6552 tmp |= (1 << 27);
6553 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6554
6555 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6556 tmp |= (1 << 27);
6557 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6558
6559 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6560 tmp &= ~(0xF << 28);
6561 tmp |= (4 << 28);
6562 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6563
6564 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6565 tmp &= ~(0xF << 28);
6566 tmp |= (4 << 28);
6567 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6568 }
6569
6570 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6571 * Programming" based on the parameters passed:
6572 * - Sequence to enable CLKOUT_DP
6573 * - Sequence to enable CLKOUT_DP without spread
6574 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6575 */
6576 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6577 bool with_fdi)
6578 {
6579 struct drm_i915_private *dev_priv = dev->dev_private;
6580 uint32_t reg, tmp;
6581
6582 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6583 with_spread = true;
6584 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6585 with_fdi, "LP PCH doesn't have FDI\n"))
6586 with_fdi = false;
6587
6588 mutex_lock(&dev_priv->dpio_lock);
6589
6590 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6591 tmp &= ~SBI_SSCCTL_DISABLE;
6592 tmp |= SBI_SSCCTL_PATHALT;
6593 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6594
6595 udelay(24);
6596
6597 if (with_spread) {
6598 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6599 tmp &= ~SBI_SSCCTL_PATHALT;
6600 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6601
6602 if (with_fdi) {
6603 lpt_reset_fdi_mphy(dev_priv);
6604 lpt_program_fdi_mphy(dev_priv);
6605 }
6606 }
6607
6608 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6609 SBI_GEN0 : SBI_DBUFF0;
6610 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6611 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6612 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6613
6614 mutex_unlock(&dev_priv->dpio_lock);
6615 }
6616
6617 /* Sequence to disable CLKOUT_DP */
6618 static void lpt_disable_clkout_dp(struct drm_device *dev)
6619 {
6620 struct drm_i915_private *dev_priv = dev->dev_private;
6621 uint32_t reg, tmp;
6622
6623 mutex_lock(&dev_priv->dpio_lock);
6624
6625 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6626 SBI_GEN0 : SBI_DBUFF0;
6627 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6628 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6629 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6630
6631 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6632 if (!(tmp & SBI_SSCCTL_DISABLE)) {
6633 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6634 tmp |= SBI_SSCCTL_PATHALT;
6635 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6636 udelay(32);
6637 }
6638 tmp |= SBI_SSCCTL_DISABLE;
6639 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6640 }
6641
6642 mutex_unlock(&dev_priv->dpio_lock);
6643 }
6644
6645 static void lpt_init_pch_refclk(struct drm_device *dev)
6646 {
6647 struct drm_mode_config *mode_config = &dev->mode_config;
6648 struct intel_encoder *encoder;
6649 bool has_vga = false;
6650
6651 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
6652 switch (encoder->type) {
6653 case INTEL_OUTPUT_ANALOG:
6654 has_vga = true;
6655 break;
6656 }
6657 }
6658
6659 if (has_vga)
6660 lpt_enable_clkout_dp(dev, true, true);
6661 else
6662 lpt_disable_clkout_dp(dev);
6663 }
6664
6665 /*
6666 * Initialize reference clocks when the driver loads
6667 */
6668 void intel_init_pch_refclk(struct drm_device *dev)
6669 {
6670 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6671 ironlake_init_pch_refclk(dev);
6672 else if (HAS_PCH_LPT(dev))
6673 lpt_init_pch_refclk(dev);
6674 }
6675
6676 static int ironlake_get_refclk(struct drm_crtc *crtc)
6677 {
6678 struct drm_device *dev = crtc->dev;
6679 struct drm_i915_private *dev_priv = dev->dev_private;
6680 struct intel_encoder *encoder;
6681 int num_connectors = 0;
6682 bool is_lvds = false;
6683
6684 for_each_encoder_on_crtc(dev, crtc, encoder) {
6685 switch (encoder->type) {
6686 case INTEL_OUTPUT_LVDS:
6687 is_lvds = true;
6688 break;
6689 }
6690 num_connectors++;
6691 }
6692
6693 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6694 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6695 dev_priv->vbt.lvds_ssc_freq);
6696 return dev_priv->vbt.lvds_ssc_freq;
6697 }
6698
6699 return 120000;
6700 }
6701
6702 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6703 {
6704 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6705 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6706 int pipe = intel_crtc->pipe;
6707 uint32_t val;
6708
6709 val = 0;
6710
6711 switch (intel_crtc->config.pipe_bpp) {
6712 case 18:
6713 val |= PIPECONF_6BPC;
6714 break;
6715 case 24:
6716 val |= PIPECONF_8BPC;
6717 break;
6718 case 30:
6719 val |= PIPECONF_10BPC;
6720 break;
6721 case 36:
6722 val |= PIPECONF_12BPC;
6723 break;
6724 default:
6725 /* Case prevented by intel_choose_pipe_bpp_dither. */
6726 BUG();
6727 }
6728
6729 if (intel_crtc->config.dither)
6730 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6731
6732 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6733 val |= PIPECONF_INTERLACED_ILK;
6734 else
6735 val |= PIPECONF_PROGRESSIVE;
6736
6737 if (intel_crtc->config.limited_color_range)
6738 val |= PIPECONF_COLOR_RANGE_SELECT;
6739
6740 I915_WRITE(PIPECONF(pipe), val);
6741 POSTING_READ(PIPECONF(pipe));
6742 }
6743
6744 /*
6745 * Set up the pipe CSC unit.
6746 *
6747 * Currently only full range RGB to limited range RGB conversion
6748 * is supported, but eventually this should handle various
6749 * RGB<->YCbCr scenarios as well.
6750 */
6751 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6752 {
6753 struct drm_device *dev = crtc->dev;
6754 struct drm_i915_private *dev_priv = dev->dev_private;
6755 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6756 int pipe = intel_crtc->pipe;
6757 uint16_t coeff = 0x7800; /* 1.0 */
6758
6759 /*
6760 * TODO: Check what kind of values actually come out of the pipe
6761 * with these coeff/postoff values and adjust to get the best
6762 * accuracy. Perhaps we even need to take the bpc value into
6763 * consideration.
6764 */
6765
6766 if (intel_crtc->config.limited_color_range)
6767 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6768
6769 /*
6770 * GY/GU and RY/RU should be the other way around according
6771 * to BSpec, but reality doesn't agree. Just set them up in
6772 * a way that results in the correct picture.
6773 */
6774 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6775 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6776
6777 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6778 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6779
6780 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6781 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6782
6783 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6784 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6785 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6786
6787 if (INTEL_INFO(dev)->gen > 6) {
6788 uint16_t postoff = 0;
6789
6790 if (intel_crtc->config.limited_color_range)
6791 postoff = (16 * (1 << 12) / 255) & 0x1fff;
6792
6793 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6794 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6795 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6796
6797 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6798 } else {
6799 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6800
6801 if (intel_crtc->config.limited_color_range)
6802 mode |= CSC_BLACK_SCREEN_OFFSET;
6803
6804 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6805 }
6806 }
6807
6808 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6809 {
6810 struct drm_device *dev = crtc->dev;
6811 struct drm_i915_private *dev_priv = dev->dev_private;
6812 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6813 enum pipe pipe = intel_crtc->pipe;
6814 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6815 uint32_t val;
6816
6817 val = 0;
6818
6819 if (IS_HASWELL(dev) && intel_crtc->config.dither)
6820 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6821
6822 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6823 val |= PIPECONF_INTERLACED_ILK;
6824 else
6825 val |= PIPECONF_PROGRESSIVE;
6826
6827 I915_WRITE(PIPECONF(cpu_transcoder), val);
6828 POSTING_READ(PIPECONF(cpu_transcoder));
6829
6830 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6831 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6832
6833 if (IS_BROADWELL(dev)) {
6834 val = 0;
6835
6836 switch (intel_crtc->config.pipe_bpp) {
6837 case 18:
6838 val |= PIPEMISC_DITHER_6_BPC;
6839 break;
6840 case 24:
6841 val |= PIPEMISC_DITHER_8_BPC;
6842 break;
6843 case 30:
6844 val |= PIPEMISC_DITHER_10_BPC;
6845 break;
6846 case 36:
6847 val |= PIPEMISC_DITHER_12_BPC;
6848 break;
6849 default:
6850 /* Case prevented by pipe_config_set_bpp. */
6851 BUG();
6852 }
6853
6854 if (intel_crtc->config.dither)
6855 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6856
6857 I915_WRITE(PIPEMISC(pipe), val);
6858 }
6859 }
6860
6861 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6862 intel_clock_t *clock,
6863 bool *has_reduced_clock,
6864 intel_clock_t *reduced_clock)
6865 {
6866 struct drm_device *dev = crtc->dev;
6867 struct drm_i915_private *dev_priv = dev->dev_private;
6868 struct intel_encoder *intel_encoder;
6869 int refclk;
6870 const intel_limit_t *limit;
6871 bool ret, is_lvds = false;
6872
6873 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6874 switch (intel_encoder->type) {
6875 case INTEL_OUTPUT_LVDS:
6876 is_lvds = true;
6877 break;
6878 }
6879 }
6880
6881 refclk = ironlake_get_refclk(crtc);
6882
6883 /*
6884 * Returns a set of divisors for the desired target clock with the given
6885 * refclk, or FALSE. The returned values represent the clock equation:
6886 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6887 */
6888 limit = intel_limit(crtc, refclk);
6889 ret = dev_priv->display.find_dpll(limit, crtc,
6890 to_intel_crtc(crtc)->config.port_clock,
6891 refclk, NULL, clock);
6892 if (!ret)
6893 return false;
6894
6895 if (is_lvds && dev_priv->lvds_downclock_avail) {
6896 /*
6897 * Ensure we match the reduced clock's P to the target clock.
6898 * If the clocks don't match, we can't switch the display clock
6899 * by using the FP0/FP1. In such case we will disable the LVDS
6900 * downclock feature.
6901 */
6902 *has_reduced_clock =
6903 dev_priv->display.find_dpll(limit, crtc,
6904 dev_priv->lvds_downclock,
6905 refclk, clock,
6906 reduced_clock);
6907 }
6908
6909 return true;
6910 }
6911
6912 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6913 {
6914 /*
6915 * Account for spread spectrum to avoid
6916 * oversubscribing the link. Max center spread
6917 * is 2.5%; use 5% for safety's sake.
6918 */
6919 u32 bps = target_clock * bpp * 21 / 20;
6920 return DIV_ROUND_UP(bps, link_bw * 8);
6921 }
6922
6923 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6924 {
6925 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6926 }
6927
6928 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6929 u32 *fp,
6930 intel_clock_t *reduced_clock, u32 *fp2)
6931 {
6932 struct drm_crtc *crtc = &intel_crtc->base;
6933 struct drm_device *dev = crtc->dev;
6934 struct drm_i915_private *dev_priv = dev->dev_private;
6935 struct intel_encoder *intel_encoder;
6936 uint32_t dpll;
6937 int factor, num_connectors = 0;
6938 bool is_lvds = false, is_sdvo = false;
6939
6940 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6941 switch (intel_encoder->type) {
6942 case INTEL_OUTPUT_LVDS:
6943 is_lvds = true;
6944 break;
6945 case INTEL_OUTPUT_SDVO:
6946 case INTEL_OUTPUT_HDMI:
6947 is_sdvo = true;
6948 break;
6949 }
6950
6951 num_connectors++;
6952 }
6953
6954 /* Enable autotuning of the PLL clock (if permissible) */
6955 factor = 21;
6956 if (is_lvds) {
6957 if ((intel_panel_use_ssc(dev_priv) &&
6958 dev_priv->vbt.lvds_ssc_freq == 100000) ||
6959 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6960 factor = 25;
6961 } else if (intel_crtc->config.sdvo_tv_clock)
6962 factor = 20;
6963
6964 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6965 *fp |= FP_CB_TUNE;
6966
6967 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6968 *fp2 |= FP_CB_TUNE;
6969
6970 dpll = 0;
6971
6972 if (is_lvds)
6973 dpll |= DPLLB_MODE_LVDS;
6974 else
6975 dpll |= DPLLB_MODE_DAC_SERIAL;
6976
6977 dpll |= (intel_crtc->config.pixel_multiplier - 1)
6978 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6979
6980 if (is_sdvo)
6981 dpll |= DPLL_SDVO_HIGH_SPEED;
6982 if (intel_crtc->config.has_dp_encoder)
6983 dpll |= DPLL_SDVO_HIGH_SPEED;
6984
6985 /* compute bitmask from p1 value */
6986 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6987 /* also FPA1 */
6988 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6989
6990 switch (intel_crtc->config.dpll.p2) {
6991 case 5:
6992 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6993 break;
6994 case 7:
6995 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6996 break;
6997 case 10:
6998 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6999 break;
7000 case 14:
7001 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7002 break;
7003 }
7004
7005 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7006 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7007 else
7008 dpll |= PLL_REF_INPUT_DREFCLK;
7009
7010 return dpll | DPLL_VCO_ENABLE;
7011 }
7012
7013 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
7014 int x, int y,
7015 struct drm_framebuffer *fb)
7016 {
7017 struct drm_device *dev = crtc->dev;
7018 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7019 int num_connectors = 0;
7020 intel_clock_t clock, reduced_clock;
7021 u32 dpll = 0, fp = 0, fp2 = 0;
7022 bool ok, has_reduced_clock = false;
7023 bool is_lvds = false;
7024 struct intel_encoder *encoder;
7025 struct intel_shared_dpll *pll;
7026
7027 for_each_encoder_on_crtc(dev, crtc, encoder) {
7028 switch (encoder->type) {
7029 case INTEL_OUTPUT_LVDS:
7030 is_lvds = true;
7031 break;
7032 }
7033
7034 num_connectors++;
7035 }
7036
7037 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7038 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7039
7040 ok = ironlake_compute_clocks(crtc, &clock,
7041 &has_reduced_clock, &reduced_clock);
7042 if (!ok && !intel_crtc->config.clock_set) {
7043 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7044 return -EINVAL;
7045 }
7046 /* Compat-code for transition, will disappear. */
7047 if (!intel_crtc->config.clock_set) {
7048 intel_crtc->config.dpll.n = clock.n;
7049 intel_crtc->config.dpll.m1 = clock.m1;
7050 intel_crtc->config.dpll.m2 = clock.m2;
7051 intel_crtc->config.dpll.p1 = clock.p1;
7052 intel_crtc->config.dpll.p2 = clock.p2;
7053 }
7054
7055 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7056 if (intel_crtc->config.has_pch_encoder) {
7057 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
7058 if (has_reduced_clock)
7059 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7060
7061 dpll = ironlake_compute_dpll(intel_crtc,
7062 &fp, &reduced_clock,
7063 has_reduced_clock ? &fp2 : NULL);
7064
7065 intel_crtc->config.dpll_hw_state.dpll = dpll;
7066 intel_crtc->config.dpll_hw_state.fp0 = fp;
7067 if (has_reduced_clock)
7068 intel_crtc->config.dpll_hw_state.fp1 = fp2;
7069 else
7070 intel_crtc->config.dpll_hw_state.fp1 = fp;
7071
7072 pll = intel_get_shared_dpll(intel_crtc);
7073 if (pll == NULL) {
7074 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7075 pipe_name(intel_crtc->pipe));
7076 return -EINVAL;
7077 }
7078 } else
7079 intel_put_shared_dpll(intel_crtc);
7080
7081 if (is_lvds && has_reduced_clock && i915.powersave)
7082 intel_crtc->lowfreq_avail = true;
7083 else
7084 intel_crtc->lowfreq_avail = false;
7085
7086 return 0;
7087 }
7088
7089 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7090 struct intel_link_m_n *m_n)
7091 {
7092 struct drm_device *dev = crtc->base.dev;
7093 struct drm_i915_private *dev_priv = dev->dev_private;
7094 enum pipe pipe = crtc->pipe;
7095
7096 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7097 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7098 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7099 & ~TU_SIZE_MASK;
7100 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7101 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7102 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7103 }
7104
7105 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7106 enum transcoder transcoder,
7107 struct intel_link_m_n *m_n)
7108 {
7109 struct drm_device *dev = crtc->base.dev;
7110 struct drm_i915_private *dev_priv = dev->dev_private;
7111 enum pipe pipe = crtc->pipe;
7112
7113 if (INTEL_INFO(dev)->gen >= 5) {
7114 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7115 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7116 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7117 & ~TU_SIZE_MASK;
7118 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7119 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7120 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7121 } else {
7122 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7123 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7124 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7125 & ~TU_SIZE_MASK;
7126 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7127 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7128 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7129 }
7130 }
7131
7132 void intel_dp_get_m_n(struct intel_crtc *crtc,
7133 struct intel_crtc_config *pipe_config)
7134 {
7135 if (crtc->config.has_pch_encoder)
7136 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7137 else
7138 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7139 &pipe_config->dp_m_n);
7140 }
7141
7142 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7143 struct intel_crtc_config *pipe_config)
7144 {
7145 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7146 &pipe_config->fdi_m_n);
7147 }
7148
7149 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7150 struct intel_crtc_config *pipe_config)
7151 {
7152 struct drm_device *dev = crtc->base.dev;
7153 struct drm_i915_private *dev_priv = dev->dev_private;
7154 uint32_t tmp;
7155
7156 tmp = I915_READ(PF_CTL(crtc->pipe));
7157
7158 if (tmp & PF_ENABLE) {
7159 pipe_config->pch_pfit.enabled = true;
7160 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7161 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7162
7163 /* We currently do not free assignements of panel fitters on
7164 * ivb/hsw (since we don't use the higher upscaling modes which
7165 * differentiates them) so just WARN about this case for now. */
7166 if (IS_GEN7(dev)) {
7167 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7168 PF_PIPE_SEL_IVB(crtc->pipe));
7169 }
7170 }
7171 }
7172
7173 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7174 struct intel_plane_config *plane_config)
7175 {
7176 struct drm_device *dev = crtc->base.dev;
7177 struct drm_i915_private *dev_priv = dev->dev_private;
7178 u32 val, base, offset;
7179 int pipe = crtc->pipe, plane = crtc->plane;
7180 int fourcc, pixel_format;
7181 int aligned_height;
7182
7183 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7184 if (!crtc->base.primary->fb) {
7185 DRM_DEBUG_KMS("failed to alloc fb\n");
7186 return;
7187 }
7188
7189 val = I915_READ(DSPCNTR(plane));
7190
7191 if (INTEL_INFO(dev)->gen >= 4)
7192 if (val & DISPPLANE_TILED)
7193 plane_config->tiled = true;
7194
7195 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7196 fourcc = intel_format_to_fourcc(pixel_format);
7197 crtc->base.primary->fb->pixel_format = fourcc;
7198 crtc->base.primary->fb->bits_per_pixel =
7199 drm_format_plane_cpp(fourcc, 0) * 8;
7200
7201 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7202 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7203 offset = I915_READ(DSPOFFSET(plane));
7204 } else {
7205 if (plane_config->tiled)
7206 offset = I915_READ(DSPTILEOFF(plane));
7207 else
7208 offset = I915_READ(DSPLINOFF(plane));
7209 }
7210 plane_config->base = base;
7211
7212 val = I915_READ(PIPESRC(pipe));
7213 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7214 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7215
7216 val = I915_READ(DSPSTRIDE(pipe));
7217 crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
7218
7219 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7220 plane_config->tiled);
7221
7222 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7223 aligned_height);
7224
7225 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7226 pipe, plane, crtc->base.primary->fb->width,
7227 crtc->base.primary->fb->height,
7228 crtc->base.primary->fb->bits_per_pixel, base,
7229 crtc->base.primary->fb->pitches[0],
7230 plane_config->size);
7231 }
7232
7233 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7234 struct intel_crtc_config *pipe_config)
7235 {
7236 struct drm_device *dev = crtc->base.dev;
7237 struct drm_i915_private *dev_priv = dev->dev_private;
7238 uint32_t tmp;
7239
7240 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7241 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7242
7243 tmp = I915_READ(PIPECONF(crtc->pipe));
7244 if (!(tmp & PIPECONF_ENABLE))
7245 return false;
7246
7247 switch (tmp & PIPECONF_BPC_MASK) {
7248 case PIPECONF_6BPC:
7249 pipe_config->pipe_bpp = 18;
7250 break;
7251 case PIPECONF_8BPC:
7252 pipe_config->pipe_bpp = 24;
7253 break;
7254 case PIPECONF_10BPC:
7255 pipe_config->pipe_bpp = 30;
7256 break;
7257 case PIPECONF_12BPC:
7258 pipe_config->pipe_bpp = 36;
7259 break;
7260 default:
7261 break;
7262 }
7263
7264 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7265 pipe_config->limited_color_range = true;
7266
7267 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7268 struct intel_shared_dpll *pll;
7269
7270 pipe_config->has_pch_encoder = true;
7271
7272 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7273 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7274 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7275
7276 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7277
7278 if (HAS_PCH_IBX(dev_priv->dev)) {
7279 pipe_config->shared_dpll =
7280 (enum intel_dpll_id) crtc->pipe;
7281 } else {
7282 tmp = I915_READ(PCH_DPLL_SEL);
7283 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7284 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7285 else
7286 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7287 }
7288
7289 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7290
7291 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7292 &pipe_config->dpll_hw_state));
7293
7294 tmp = pipe_config->dpll_hw_state.dpll;
7295 pipe_config->pixel_multiplier =
7296 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7297 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7298
7299 ironlake_pch_clock_get(crtc, pipe_config);
7300 } else {
7301 pipe_config->pixel_multiplier = 1;
7302 }
7303
7304 intel_get_pipe_timings(crtc, pipe_config);
7305
7306 ironlake_get_pfit_config(crtc, pipe_config);
7307
7308 return true;
7309 }
7310
7311 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7312 {
7313 struct drm_device *dev = dev_priv->dev;
7314 struct intel_crtc *crtc;
7315
7316 for_each_intel_crtc(dev, crtc)
7317 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7318 pipe_name(crtc->pipe));
7319
7320 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7321 WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7322 WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7323 WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7324 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7325 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7326 "CPU PWM1 enabled\n");
7327 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7328 "CPU PWM2 enabled\n");
7329 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7330 "PCH PWM1 enabled\n");
7331 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7332 "Utility pin enabled\n");
7333 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7334
7335 /*
7336 * In theory we can still leave IRQs enabled, as long as only the HPD
7337 * interrupts remain enabled. We used to check for that, but since it's
7338 * gen-specific and since we only disable LCPLL after we fully disable
7339 * the interrupts, the check below should be enough.
7340 */
7341 WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n");
7342 }
7343
7344 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7345 {
7346 struct drm_device *dev = dev_priv->dev;
7347
7348 if (IS_HASWELL(dev))
7349 return I915_READ(D_COMP_HSW);
7350 else
7351 return I915_READ(D_COMP_BDW);
7352 }
7353
7354 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7355 {
7356 struct drm_device *dev = dev_priv->dev;
7357
7358 if (IS_HASWELL(dev)) {
7359 mutex_lock(&dev_priv->rps.hw_lock);
7360 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7361 val))
7362 DRM_ERROR("Failed to write to D_COMP\n");
7363 mutex_unlock(&dev_priv->rps.hw_lock);
7364 } else {
7365 I915_WRITE(D_COMP_BDW, val);
7366 POSTING_READ(D_COMP_BDW);
7367 }
7368 }
7369
7370 /*
7371 * This function implements pieces of two sequences from BSpec:
7372 * - Sequence for display software to disable LCPLL
7373 * - Sequence for display software to allow package C8+
7374 * The steps implemented here are just the steps that actually touch the LCPLL
7375 * register. Callers should take care of disabling all the display engine
7376 * functions, doing the mode unset, fixing interrupts, etc.
7377 */
7378 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7379 bool switch_to_fclk, bool allow_power_down)
7380 {
7381 uint32_t val;
7382
7383 assert_can_disable_lcpll(dev_priv);
7384
7385 val = I915_READ(LCPLL_CTL);
7386
7387 if (switch_to_fclk) {
7388 val |= LCPLL_CD_SOURCE_FCLK;
7389 I915_WRITE(LCPLL_CTL, val);
7390
7391 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7392 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7393 DRM_ERROR("Switching to FCLK failed\n");
7394
7395 val = I915_READ(LCPLL_CTL);
7396 }
7397
7398 val |= LCPLL_PLL_DISABLE;
7399 I915_WRITE(LCPLL_CTL, val);
7400 POSTING_READ(LCPLL_CTL);
7401
7402 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7403 DRM_ERROR("LCPLL still locked\n");
7404
7405 val = hsw_read_dcomp(dev_priv);
7406 val |= D_COMP_COMP_DISABLE;
7407 hsw_write_dcomp(dev_priv, val);
7408 ndelay(100);
7409
7410 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7411 1))
7412 DRM_ERROR("D_COMP RCOMP still in progress\n");
7413
7414 if (allow_power_down) {
7415 val = I915_READ(LCPLL_CTL);
7416 val |= LCPLL_POWER_DOWN_ALLOW;
7417 I915_WRITE(LCPLL_CTL, val);
7418 POSTING_READ(LCPLL_CTL);
7419 }
7420 }
7421
7422 /*
7423 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7424 * source.
7425 */
7426 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7427 {
7428 uint32_t val;
7429 unsigned long irqflags;
7430
7431 val = I915_READ(LCPLL_CTL);
7432
7433 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7434 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7435 return;
7436
7437 /*
7438 * Make sure we're not on PC8 state before disabling PC8, otherwise
7439 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7440 *
7441 * The other problem is that hsw_restore_lcpll() is called as part of
7442 * the runtime PM resume sequence, so we can't just call
7443 * gen6_gt_force_wake_get() because that function calls
7444 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7445 * while we are on the resume sequence. So to solve this problem we have
7446 * to call special forcewake code that doesn't touch runtime PM and
7447 * doesn't enable the forcewake delayed work.
7448 */
7449 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7450 if (dev_priv->uncore.forcewake_count++ == 0)
7451 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7452 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7453
7454 if (val & LCPLL_POWER_DOWN_ALLOW) {
7455 val &= ~LCPLL_POWER_DOWN_ALLOW;
7456 I915_WRITE(LCPLL_CTL, val);
7457 POSTING_READ(LCPLL_CTL);
7458 }
7459
7460 val = hsw_read_dcomp(dev_priv);
7461 val |= D_COMP_COMP_FORCE;
7462 val &= ~D_COMP_COMP_DISABLE;
7463 hsw_write_dcomp(dev_priv, val);
7464
7465 val = I915_READ(LCPLL_CTL);
7466 val &= ~LCPLL_PLL_DISABLE;
7467 I915_WRITE(LCPLL_CTL, val);
7468
7469 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7470 DRM_ERROR("LCPLL not locked yet\n");
7471
7472 if (val & LCPLL_CD_SOURCE_FCLK) {
7473 val = I915_READ(LCPLL_CTL);
7474 val &= ~LCPLL_CD_SOURCE_FCLK;
7475 I915_WRITE(LCPLL_CTL, val);
7476
7477 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7478 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7479 DRM_ERROR("Switching back to LCPLL failed\n");
7480 }
7481
7482 /* See the big comment above. */
7483 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7484 if (--dev_priv->uncore.forcewake_count == 0)
7485 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7486 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7487 }
7488
7489 /*
7490 * Package states C8 and deeper are really deep PC states that can only be
7491 * reached when all the devices on the system allow it, so even if the graphics
7492 * device allows PC8+, it doesn't mean the system will actually get to these
7493 * states. Our driver only allows PC8+ when going into runtime PM.
7494 *
7495 * The requirements for PC8+ are that all the outputs are disabled, the power
7496 * well is disabled and most interrupts are disabled, and these are also
7497 * requirements for runtime PM. When these conditions are met, we manually do
7498 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7499 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7500 * hang the machine.
7501 *
7502 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7503 * the state of some registers, so when we come back from PC8+ we need to
7504 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7505 * need to take care of the registers kept by RC6. Notice that this happens even
7506 * if we don't put the device in PCI D3 state (which is what currently happens
7507 * because of the runtime PM support).
7508 *
7509 * For more, read "Display Sequences for Package C8" on the hardware
7510 * documentation.
7511 */
7512 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7513 {
7514 struct drm_device *dev = dev_priv->dev;
7515 uint32_t val;
7516
7517 DRM_DEBUG_KMS("Enabling package C8+\n");
7518
7519 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7520 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7521 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7522 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7523 }
7524
7525 lpt_disable_clkout_dp(dev);
7526 hsw_disable_lcpll(dev_priv, true, true);
7527 }
7528
7529 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7530 {
7531 struct drm_device *dev = dev_priv->dev;
7532 uint32_t val;
7533
7534 DRM_DEBUG_KMS("Disabling package C8+\n");
7535
7536 hsw_restore_lcpll(dev_priv);
7537 lpt_init_pch_refclk(dev);
7538
7539 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7540 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7541 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7542 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7543 }
7544
7545 intel_prepare_ddi(dev);
7546 }
7547
7548 static void snb_modeset_global_resources(struct drm_device *dev)
7549 {
7550 modeset_update_crtc_power_domains(dev);
7551 }
7552
7553 static void haswell_modeset_global_resources(struct drm_device *dev)
7554 {
7555 modeset_update_crtc_power_domains(dev);
7556 }
7557
7558 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7559 int x, int y,
7560 struct drm_framebuffer *fb)
7561 {
7562 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7563
7564 if (!intel_ddi_pll_select(intel_crtc))
7565 return -EINVAL;
7566 intel_ddi_pll_enable(intel_crtc);
7567
7568 intel_crtc->lowfreq_avail = false;
7569
7570 return 0;
7571 }
7572
7573 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7574 struct intel_crtc_config *pipe_config)
7575 {
7576 struct drm_device *dev = crtc->base.dev;
7577 struct drm_i915_private *dev_priv = dev->dev_private;
7578 enum intel_display_power_domain pfit_domain;
7579 uint32_t tmp;
7580
7581 if (!intel_display_power_enabled(dev_priv,
7582 POWER_DOMAIN_PIPE(crtc->pipe)))
7583 return false;
7584
7585 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7586 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7587
7588 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7589 if (tmp & TRANS_DDI_FUNC_ENABLE) {
7590 enum pipe trans_edp_pipe;
7591 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7592 default:
7593 WARN(1, "unknown pipe linked to edp transcoder\n");
7594 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7595 case TRANS_DDI_EDP_INPUT_A_ON:
7596 trans_edp_pipe = PIPE_A;
7597 break;
7598 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7599 trans_edp_pipe = PIPE_B;
7600 break;
7601 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7602 trans_edp_pipe = PIPE_C;
7603 break;
7604 }
7605
7606 if (trans_edp_pipe == crtc->pipe)
7607 pipe_config->cpu_transcoder = TRANSCODER_EDP;
7608 }
7609
7610 if (!intel_display_power_enabled(dev_priv,
7611 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7612 return false;
7613
7614 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7615 if (!(tmp & PIPECONF_ENABLE))
7616 return false;
7617
7618 /*
7619 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7620 * DDI E. So just check whether this pipe is wired to DDI E and whether
7621 * the PCH transcoder is on.
7622 */
7623 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7624 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
7625 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7626 pipe_config->has_pch_encoder = true;
7627
7628 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7629 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7630 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7631
7632 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7633 }
7634
7635 intel_get_pipe_timings(crtc, pipe_config);
7636
7637 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7638 if (intel_display_power_enabled(dev_priv, pfit_domain))
7639 ironlake_get_pfit_config(crtc, pipe_config);
7640
7641 if (IS_HASWELL(dev))
7642 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7643 (I915_READ(IPS_CTL) & IPS_ENABLE);
7644
7645 pipe_config->pixel_multiplier = 1;
7646
7647 return true;
7648 }
7649
7650 static struct {
7651 int clock;
7652 u32 config;
7653 } hdmi_audio_clock[] = {
7654 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7655 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7656 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7657 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7658 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7659 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7660 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7661 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7662 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7663 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7664 };
7665
7666 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7667 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7668 {
7669 int i;
7670
7671 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7672 if (mode->clock == hdmi_audio_clock[i].clock)
7673 break;
7674 }
7675
7676 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7677 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7678 i = 1;
7679 }
7680
7681 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7682 hdmi_audio_clock[i].clock,
7683 hdmi_audio_clock[i].config);
7684
7685 return hdmi_audio_clock[i].config;
7686 }
7687
7688 static bool intel_eld_uptodate(struct drm_connector *connector,
7689 int reg_eldv, uint32_t bits_eldv,
7690 int reg_elda, uint32_t bits_elda,
7691 int reg_edid)
7692 {
7693 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7694 uint8_t *eld = connector->eld;
7695 uint32_t i;
7696
7697 i = I915_READ(reg_eldv);
7698 i &= bits_eldv;
7699
7700 if (!eld[0])
7701 return !i;
7702
7703 if (!i)
7704 return false;
7705
7706 i = I915_READ(reg_elda);
7707 i &= ~bits_elda;
7708 I915_WRITE(reg_elda, i);
7709
7710 for (i = 0; i < eld[2]; i++)
7711 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7712 return false;
7713
7714 return true;
7715 }
7716
7717 static void g4x_write_eld(struct drm_connector *connector,
7718 struct drm_crtc *crtc,
7719 struct drm_display_mode *mode)
7720 {
7721 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7722 uint8_t *eld = connector->eld;
7723 uint32_t eldv;
7724 uint32_t len;
7725 uint32_t i;
7726
7727 i = I915_READ(G4X_AUD_VID_DID);
7728
7729 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7730 eldv = G4X_ELDV_DEVCL_DEVBLC;
7731 else
7732 eldv = G4X_ELDV_DEVCTG;
7733
7734 if (intel_eld_uptodate(connector,
7735 G4X_AUD_CNTL_ST, eldv,
7736 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7737 G4X_HDMIW_HDMIEDID))
7738 return;
7739
7740 i = I915_READ(G4X_AUD_CNTL_ST);
7741 i &= ~(eldv | G4X_ELD_ADDR);
7742 len = (i >> 9) & 0x1f; /* ELD buffer size */
7743 I915_WRITE(G4X_AUD_CNTL_ST, i);
7744
7745 if (!eld[0])
7746 return;
7747
7748 len = min_t(uint8_t, eld[2], len);
7749 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7750 for (i = 0; i < len; i++)
7751 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7752
7753 i = I915_READ(G4X_AUD_CNTL_ST);
7754 i |= eldv;
7755 I915_WRITE(G4X_AUD_CNTL_ST, i);
7756 }
7757
7758 static void haswell_write_eld(struct drm_connector *connector,
7759 struct drm_crtc *crtc,
7760 struct drm_display_mode *mode)
7761 {
7762 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7763 uint8_t *eld = connector->eld;
7764 uint32_t eldv;
7765 uint32_t i;
7766 int len;
7767 int pipe = to_intel_crtc(crtc)->pipe;
7768 int tmp;
7769
7770 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7771 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7772 int aud_config = HSW_AUD_CFG(pipe);
7773 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7774
7775 /* Audio output enable */
7776 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7777 tmp = I915_READ(aud_cntrl_st2);
7778 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7779 I915_WRITE(aud_cntrl_st2, tmp);
7780 POSTING_READ(aud_cntrl_st2);
7781
7782 assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
7783
7784 /* Set ELD valid state */
7785 tmp = I915_READ(aud_cntrl_st2);
7786 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7787 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7788 I915_WRITE(aud_cntrl_st2, tmp);
7789 tmp = I915_READ(aud_cntrl_st2);
7790 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7791
7792 /* Enable HDMI mode */
7793 tmp = I915_READ(aud_config);
7794 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7795 /* clear N_programing_enable and N_value_index */
7796 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7797 I915_WRITE(aud_config, tmp);
7798
7799 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7800
7801 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7802
7803 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7804 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7805 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7806 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7807 } else {
7808 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7809 }
7810
7811 if (intel_eld_uptodate(connector,
7812 aud_cntrl_st2, eldv,
7813 aud_cntl_st, IBX_ELD_ADDRESS,
7814 hdmiw_hdmiedid))
7815 return;
7816
7817 i = I915_READ(aud_cntrl_st2);
7818 i &= ~eldv;
7819 I915_WRITE(aud_cntrl_st2, i);
7820
7821 if (!eld[0])
7822 return;
7823
7824 i = I915_READ(aud_cntl_st);
7825 i &= ~IBX_ELD_ADDRESS;
7826 I915_WRITE(aud_cntl_st, i);
7827 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
7828 DRM_DEBUG_DRIVER("port num:%d\n", i);
7829
7830 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7831 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7832 for (i = 0; i < len; i++)
7833 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7834
7835 i = I915_READ(aud_cntrl_st2);
7836 i |= eldv;
7837 I915_WRITE(aud_cntrl_st2, i);
7838
7839 }
7840
7841 static void ironlake_write_eld(struct drm_connector *connector,
7842 struct drm_crtc *crtc,
7843 struct drm_display_mode *mode)
7844 {
7845 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7846 uint8_t *eld = connector->eld;
7847 uint32_t eldv;
7848 uint32_t i;
7849 int len;
7850 int hdmiw_hdmiedid;
7851 int aud_config;
7852 int aud_cntl_st;
7853 int aud_cntrl_st2;
7854 int pipe = to_intel_crtc(crtc)->pipe;
7855
7856 if (HAS_PCH_IBX(connector->dev)) {
7857 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7858 aud_config = IBX_AUD_CFG(pipe);
7859 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7860 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7861 } else if (IS_VALLEYVIEW(connector->dev)) {
7862 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7863 aud_config = VLV_AUD_CFG(pipe);
7864 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7865 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7866 } else {
7867 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7868 aud_config = CPT_AUD_CFG(pipe);
7869 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7870 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7871 }
7872
7873 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7874
7875 if (IS_VALLEYVIEW(connector->dev)) {
7876 struct intel_encoder *intel_encoder;
7877 struct intel_digital_port *intel_dig_port;
7878
7879 intel_encoder = intel_attached_encoder(connector);
7880 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7881 i = intel_dig_port->port;
7882 } else {
7883 i = I915_READ(aud_cntl_st);
7884 i = (i >> 29) & DIP_PORT_SEL_MASK;
7885 /* DIP_Port_Select, 0x1 = PortB */
7886 }
7887
7888 if (!i) {
7889 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7890 /* operate blindly on all ports */
7891 eldv = IBX_ELD_VALIDB;
7892 eldv |= IBX_ELD_VALIDB << 4;
7893 eldv |= IBX_ELD_VALIDB << 8;
7894 } else {
7895 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7896 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7897 }
7898
7899 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7900 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7901 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7902 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7903 } else {
7904 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7905 }
7906
7907 if (intel_eld_uptodate(connector,
7908 aud_cntrl_st2, eldv,
7909 aud_cntl_st, IBX_ELD_ADDRESS,
7910 hdmiw_hdmiedid))
7911 return;
7912
7913 i = I915_READ(aud_cntrl_st2);
7914 i &= ~eldv;
7915 I915_WRITE(aud_cntrl_st2, i);
7916
7917 if (!eld[0])
7918 return;
7919
7920 i = I915_READ(aud_cntl_st);
7921 i &= ~IBX_ELD_ADDRESS;
7922 I915_WRITE(aud_cntl_st, i);
7923
7924 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7925 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7926 for (i = 0; i < len; i++)
7927 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7928
7929 i = I915_READ(aud_cntrl_st2);
7930 i |= eldv;
7931 I915_WRITE(aud_cntrl_st2, i);
7932 }
7933
7934 void intel_write_eld(struct drm_encoder *encoder,
7935 struct drm_display_mode *mode)
7936 {
7937 struct drm_crtc *crtc = encoder->crtc;
7938 struct drm_connector *connector;
7939 struct drm_device *dev = encoder->dev;
7940 struct drm_i915_private *dev_priv = dev->dev_private;
7941
7942 connector = drm_select_eld(encoder, mode);
7943 if (!connector)
7944 return;
7945
7946 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7947 connector->base.id,
7948 connector->name,
7949 connector->encoder->base.id,
7950 connector->encoder->name);
7951
7952 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7953
7954 if (dev_priv->display.write_eld)
7955 dev_priv->display.write_eld(connector, crtc, mode);
7956 }
7957
7958 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7959 {
7960 struct drm_device *dev = crtc->dev;
7961 struct drm_i915_private *dev_priv = dev->dev_private;
7962 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7963 uint32_t cntl;
7964
7965 if (base != intel_crtc->cursor_base) {
7966 /* On these chipsets we can only modify the base whilst
7967 * the cursor is disabled.
7968 */
7969 if (intel_crtc->cursor_cntl) {
7970 I915_WRITE(_CURACNTR, 0);
7971 POSTING_READ(_CURACNTR);
7972 intel_crtc->cursor_cntl = 0;
7973 }
7974
7975 I915_WRITE(_CURABASE, base);
7976 POSTING_READ(_CURABASE);
7977 }
7978
7979 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7980 cntl = 0;
7981 if (base)
7982 cntl = (CURSOR_ENABLE |
7983 CURSOR_GAMMA_ENABLE |
7984 CURSOR_FORMAT_ARGB);
7985 if (intel_crtc->cursor_cntl != cntl) {
7986 I915_WRITE(_CURACNTR, cntl);
7987 POSTING_READ(_CURACNTR);
7988 intel_crtc->cursor_cntl = cntl;
7989 }
7990 }
7991
7992 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7993 {
7994 struct drm_device *dev = crtc->dev;
7995 struct drm_i915_private *dev_priv = dev->dev_private;
7996 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7997 int pipe = intel_crtc->pipe;
7998 uint32_t cntl;
7999
8000 cntl = 0;
8001 if (base) {
8002 cntl = MCURSOR_GAMMA_ENABLE;
8003 switch (intel_crtc->cursor_width) {
8004 case 64:
8005 cntl |= CURSOR_MODE_64_ARGB_AX;
8006 break;
8007 case 128:
8008 cntl |= CURSOR_MODE_128_ARGB_AX;
8009 break;
8010 case 256:
8011 cntl |= CURSOR_MODE_256_ARGB_AX;
8012 break;
8013 default:
8014 WARN_ON(1);
8015 return;
8016 }
8017 cntl |= pipe << 28; /* Connect to correct pipe */
8018 }
8019 if (intel_crtc->cursor_cntl != cntl) {
8020 I915_WRITE(CURCNTR(pipe), cntl);
8021 POSTING_READ(CURCNTR(pipe));
8022 intel_crtc->cursor_cntl = cntl;
8023 }
8024
8025 /* and commit changes on next vblank */
8026 I915_WRITE(CURBASE(pipe), base);
8027 POSTING_READ(CURBASE(pipe));
8028 }
8029
8030 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
8031 {
8032 struct drm_device *dev = crtc->dev;
8033 struct drm_i915_private *dev_priv = dev->dev_private;
8034 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8035 int pipe = intel_crtc->pipe;
8036 uint32_t cntl;
8037
8038 cntl = 0;
8039 if (base) {
8040 cntl = MCURSOR_GAMMA_ENABLE;
8041 switch (intel_crtc->cursor_width) {
8042 case 64:
8043 cntl |= CURSOR_MODE_64_ARGB_AX;
8044 break;
8045 case 128:
8046 cntl |= CURSOR_MODE_128_ARGB_AX;
8047 break;
8048 case 256:
8049 cntl |= CURSOR_MODE_256_ARGB_AX;
8050 break;
8051 default:
8052 WARN_ON(1);
8053 return;
8054 }
8055 }
8056 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8057 cntl |= CURSOR_PIPE_CSC_ENABLE;
8058
8059 if (intel_crtc->cursor_cntl != cntl) {
8060 I915_WRITE(CURCNTR(pipe), cntl);
8061 POSTING_READ(CURCNTR(pipe));
8062 intel_crtc->cursor_cntl = cntl;
8063 }
8064
8065 /* and commit changes on next vblank */
8066 I915_WRITE(CURBASE(pipe), base);
8067 POSTING_READ(CURBASE(pipe));
8068 }
8069
8070 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8071 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8072 bool on)
8073 {
8074 struct drm_device *dev = crtc->dev;
8075 struct drm_i915_private *dev_priv = dev->dev_private;
8076 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8077 int pipe = intel_crtc->pipe;
8078 int x = crtc->cursor_x;
8079 int y = crtc->cursor_y;
8080 u32 base = 0, pos = 0;
8081
8082 if (on)
8083 base = intel_crtc->cursor_addr;
8084
8085 if (x >= intel_crtc->config.pipe_src_w)
8086 base = 0;
8087
8088 if (y >= intel_crtc->config.pipe_src_h)
8089 base = 0;
8090
8091 if (x < 0) {
8092 if (x + intel_crtc->cursor_width <= 0)
8093 base = 0;
8094
8095 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8096 x = -x;
8097 }
8098 pos |= x << CURSOR_X_SHIFT;
8099
8100 if (y < 0) {
8101 if (y + intel_crtc->cursor_height <= 0)
8102 base = 0;
8103
8104 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8105 y = -y;
8106 }
8107 pos |= y << CURSOR_Y_SHIFT;
8108
8109 if (base == 0 && intel_crtc->cursor_base == 0)
8110 return;
8111
8112 I915_WRITE(CURPOS(pipe), pos);
8113
8114 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev))
8115 ivb_update_cursor(crtc, base);
8116 else if (IS_845G(dev) || IS_I865G(dev))
8117 i845_update_cursor(crtc, base);
8118 else
8119 i9xx_update_cursor(crtc, base);
8120 intel_crtc->cursor_base = base;
8121 }
8122
8123 /*
8124 * intel_crtc_cursor_set_obj - Set cursor to specified GEM object
8125 *
8126 * Note that the object's reference will be consumed if the update fails. If
8127 * the update succeeds, the reference of the old object (if any) will be
8128 * consumed.
8129 */
8130 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8131 struct drm_i915_gem_object *obj,
8132 uint32_t width, uint32_t height)
8133 {
8134 struct drm_device *dev = crtc->dev;
8135 struct drm_i915_private *dev_priv = dev->dev_private;
8136 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8137 enum pipe pipe = intel_crtc->pipe;
8138 unsigned old_width;
8139 uint32_t addr;
8140 int ret;
8141
8142 /* if we want to turn off the cursor ignore width and height */
8143 if (!obj) {
8144 DRM_DEBUG_KMS("cursor off\n");
8145 addr = 0;
8146 obj = NULL;
8147 mutex_lock(&dev->struct_mutex);
8148 goto finish;
8149 }
8150
8151 /* Check for which cursor types we support */
8152 if (!((width == 64 && height == 64) ||
8153 (width == 128 && height == 128 && !IS_GEN2(dev)) ||
8154 (width == 256 && height == 256 && !IS_GEN2(dev)))) {
8155 DRM_DEBUG("Cursor dimension not supported\n");
8156 return -EINVAL;
8157 }
8158
8159 if (obj->base.size < width * height * 4) {
8160 DRM_DEBUG_KMS("buffer is too small\n");
8161 ret = -ENOMEM;
8162 goto fail;
8163 }
8164
8165 /* we only need to pin inside GTT if cursor is non-phy */
8166 mutex_lock(&dev->struct_mutex);
8167 if (!INTEL_INFO(dev)->cursor_needs_physical) {
8168 unsigned alignment;
8169
8170 if (obj->tiling_mode) {
8171 DRM_DEBUG_KMS("cursor cannot be tiled\n");
8172 ret = -EINVAL;
8173 goto fail_locked;
8174 }
8175
8176 /* Note that the w/a also requires 2 PTE of padding following
8177 * the bo. We currently fill all unused PTE with the shadow
8178 * page and so we should always have valid PTE following the
8179 * cursor preventing the VT-d warning.
8180 */
8181 alignment = 0;
8182 if (need_vtd_wa(dev))
8183 alignment = 64*1024;
8184
8185 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8186 if (ret) {
8187 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8188 goto fail_locked;
8189 }
8190
8191 ret = i915_gem_object_put_fence(obj);
8192 if (ret) {
8193 DRM_DEBUG_KMS("failed to release fence for cursor");
8194 goto fail_unpin;
8195 }
8196
8197 addr = i915_gem_obj_ggtt_offset(obj);
8198 } else {
8199 int align = IS_I830(dev) ? 16 * 1024 : 256;
8200 ret = i915_gem_object_attach_phys(obj, align);
8201 if (ret) {
8202 DRM_DEBUG_KMS("failed to attach phys object\n");
8203 goto fail_locked;
8204 }
8205 addr = obj->phys_handle->busaddr;
8206 }
8207
8208 if (IS_GEN2(dev))
8209 I915_WRITE(CURSIZE, (height << 12) | width);
8210
8211 finish:
8212 if (intel_crtc->cursor_bo) {
8213 if (!INTEL_INFO(dev)->cursor_needs_physical)
8214 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8215 }
8216
8217 i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8218 INTEL_FRONTBUFFER_CURSOR(pipe));
8219 mutex_unlock(&dev->struct_mutex);
8220
8221 old_width = intel_crtc->cursor_width;
8222
8223 intel_crtc->cursor_addr = addr;
8224 intel_crtc->cursor_bo = obj;
8225 intel_crtc->cursor_width = width;
8226 intel_crtc->cursor_height = height;
8227
8228 if (intel_crtc->active) {
8229 if (old_width != width)
8230 intel_update_watermarks(crtc);
8231 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8232 }
8233
8234 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8235
8236 return 0;
8237 fail_unpin:
8238 i915_gem_object_unpin_from_display_plane(obj);
8239 fail_locked:
8240 mutex_unlock(&dev->struct_mutex);
8241 fail:
8242 drm_gem_object_unreference_unlocked(&obj->base);
8243 return ret;
8244 }
8245
8246 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8247 u16 *blue, uint32_t start, uint32_t size)
8248 {
8249 int end = (start + size > 256) ? 256 : start + size, i;
8250 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8251
8252 for (i = start; i < end; i++) {
8253 intel_crtc->lut_r[i] = red[i] >> 8;
8254 intel_crtc->lut_g[i] = green[i] >> 8;
8255 intel_crtc->lut_b[i] = blue[i] >> 8;
8256 }
8257
8258 intel_crtc_load_lut(crtc);
8259 }
8260
8261 /* VESA 640x480x72Hz mode to set on the pipe */
8262 static struct drm_display_mode load_detect_mode = {
8263 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8264 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8265 };
8266
8267 struct drm_framebuffer *
8268 __intel_framebuffer_create(struct drm_device *dev,
8269 struct drm_mode_fb_cmd2 *mode_cmd,
8270 struct drm_i915_gem_object *obj)
8271 {
8272 struct intel_framebuffer *intel_fb;
8273 int ret;
8274
8275 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8276 if (!intel_fb) {
8277 drm_gem_object_unreference_unlocked(&obj->base);
8278 return ERR_PTR(-ENOMEM);
8279 }
8280
8281 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8282 if (ret)
8283 goto err;
8284
8285 return &intel_fb->base;
8286 err:
8287 drm_gem_object_unreference_unlocked(&obj->base);
8288 kfree(intel_fb);
8289
8290 return ERR_PTR(ret);
8291 }
8292
8293 static struct drm_framebuffer *
8294 intel_framebuffer_create(struct drm_device *dev,
8295 struct drm_mode_fb_cmd2 *mode_cmd,
8296 struct drm_i915_gem_object *obj)
8297 {
8298 struct drm_framebuffer *fb;
8299 int ret;
8300
8301 ret = i915_mutex_lock_interruptible(dev);
8302 if (ret)
8303 return ERR_PTR(ret);
8304 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8305 mutex_unlock(&dev->struct_mutex);
8306
8307 return fb;
8308 }
8309
8310 static u32
8311 intel_framebuffer_pitch_for_width(int width, int bpp)
8312 {
8313 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8314 return ALIGN(pitch, 64);
8315 }
8316
8317 static u32
8318 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8319 {
8320 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8321 return PAGE_ALIGN(pitch * mode->vdisplay);
8322 }
8323
8324 static struct drm_framebuffer *
8325 intel_framebuffer_create_for_mode(struct drm_device *dev,
8326 struct drm_display_mode *mode,
8327 int depth, int bpp)
8328 {
8329 struct drm_i915_gem_object *obj;
8330 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8331
8332 obj = i915_gem_alloc_object(dev,
8333 intel_framebuffer_size_for_mode(mode, bpp));
8334 if (obj == NULL)
8335 return ERR_PTR(-ENOMEM);
8336
8337 mode_cmd.width = mode->hdisplay;
8338 mode_cmd.height = mode->vdisplay;
8339 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8340 bpp);
8341 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8342
8343 return intel_framebuffer_create(dev, &mode_cmd, obj);
8344 }
8345
8346 static struct drm_framebuffer *
8347 mode_fits_in_fbdev(struct drm_device *dev,
8348 struct drm_display_mode *mode)
8349 {
8350 #ifdef CONFIG_DRM_I915_FBDEV
8351 struct drm_i915_private *dev_priv = dev->dev_private;
8352 struct drm_i915_gem_object *obj;
8353 struct drm_framebuffer *fb;
8354
8355 if (!dev_priv->fbdev)
8356 return NULL;
8357
8358 if (!dev_priv->fbdev->fb)
8359 return NULL;
8360
8361 obj = dev_priv->fbdev->fb->obj;
8362 BUG_ON(!obj);
8363
8364 fb = &dev_priv->fbdev->fb->base;
8365 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8366 fb->bits_per_pixel))
8367 return NULL;
8368
8369 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8370 return NULL;
8371
8372 return fb;
8373 #else
8374 return NULL;
8375 #endif
8376 }
8377
8378 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8379 struct drm_display_mode *mode,
8380 struct intel_load_detect_pipe *old,
8381 struct drm_modeset_acquire_ctx *ctx)
8382 {
8383 struct intel_crtc *intel_crtc;
8384 struct intel_encoder *intel_encoder =
8385 intel_attached_encoder(connector);
8386 struct drm_crtc *possible_crtc;
8387 struct drm_encoder *encoder = &intel_encoder->base;
8388 struct drm_crtc *crtc = NULL;
8389 struct drm_device *dev = encoder->dev;
8390 struct drm_framebuffer *fb;
8391 struct drm_mode_config *config = &dev->mode_config;
8392 int ret, i = -1;
8393
8394 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8395 connector->base.id, connector->name,
8396 encoder->base.id, encoder->name);
8397
8398 drm_modeset_acquire_init(ctx, 0);
8399
8400 retry:
8401 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8402 if (ret)
8403 goto fail_unlock;
8404
8405 /*
8406 * Algorithm gets a little messy:
8407 *
8408 * - if the connector already has an assigned crtc, use it (but make
8409 * sure it's on first)
8410 *
8411 * - try to find the first unused crtc that can drive this connector,
8412 * and use that if we find one
8413 */
8414
8415 /* See if we already have a CRTC for this connector */
8416 if (encoder->crtc) {
8417 crtc = encoder->crtc;
8418
8419 ret = drm_modeset_lock(&crtc->mutex, ctx);
8420 if (ret)
8421 goto fail_unlock;
8422
8423 old->dpms_mode = connector->dpms;
8424 old->load_detect_temp = false;
8425
8426 /* Make sure the crtc and connector are running */
8427 if (connector->dpms != DRM_MODE_DPMS_ON)
8428 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8429
8430 return true;
8431 }
8432
8433 /* Find an unused one (if possible) */
8434 for_each_crtc(dev, possible_crtc) {
8435 i++;
8436 if (!(encoder->possible_crtcs & (1 << i)))
8437 continue;
8438 if (!possible_crtc->enabled) {
8439 crtc = possible_crtc;
8440 break;
8441 }
8442 }
8443
8444 /*
8445 * If we didn't find an unused CRTC, don't use any.
8446 */
8447 if (!crtc) {
8448 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8449 goto fail_unlock;
8450 }
8451
8452 ret = drm_modeset_lock(&crtc->mutex, ctx);
8453 if (ret)
8454 goto fail_unlock;
8455 intel_encoder->new_crtc = to_intel_crtc(crtc);
8456 to_intel_connector(connector)->new_encoder = intel_encoder;
8457
8458 intel_crtc = to_intel_crtc(crtc);
8459 intel_crtc->new_enabled = true;
8460 intel_crtc->new_config = &intel_crtc->config;
8461 old->dpms_mode = connector->dpms;
8462 old->load_detect_temp = true;
8463 old->release_fb = NULL;
8464
8465 if (!mode)
8466 mode = &load_detect_mode;
8467
8468 /* We need a framebuffer large enough to accommodate all accesses
8469 * that the plane may generate whilst we perform load detection.
8470 * We can not rely on the fbcon either being present (we get called
8471 * during its initialisation to detect all boot displays, or it may
8472 * not even exist) or that it is large enough to satisfy the
8473 * requested mode.
8474 */
8475 fb = mode_fits_in_fbdev(dev, mode);
8476 if (fb == NULL) {
8477 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8478 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8479 old->release_fb = fb;
8480 } else
8481 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8482 if (IS_ERR(fb)) {
8483 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8484 goto fail;
8485 }
8486
8487 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8488 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8489 if (old->release_fb)
8490 old->release_fb->funcs->destroy(old->release_fb);
8491 goto fail;
8492 }
8493
8494 /* let the connector get through one full cycle before testing */
8495 intel_wait_for_vblank(dev, intel_crtc->pipe);
8496 return true;
8497
8498 fail:
8499 intel_crtc->new_enabled = crtc->enabled;
8500 if (intel_crtc->new_enabled)
8501 intel_crtc->new_config = &intel_crtc->config;
8502 else
8503 intel_crtc->new_config = NULL;
8504 fail_unlock:
8505 if (ret == -EDEADLK) {
8506 drm_modeset_backoff(ctx);
8507 goto retry;
8508 }
8509
8510 drm_modeset_drop_locks(ctx);
8511 drm_modeset_acquire_fini(ctx);
8512
8513 return false;
8514 }
8515
8516 void intel_release_load_detect_pipe(struct drm_connector *connector,
8517 struct intel_load_detect_pipe *old,
8518 struct drm_modeset_acquire_ctx *ctx)
8519 {
8520 struct intel_encoder *intel_encoder =
8521 intel_attached_encoder(connector);
8522 struct drm_encoder *encoder = &intel_encoder->base;
8523 struct drm_crtc *crtc = encoder->crtc;
8524 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8525
8526 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8527 connector->base.id, connector->name,
8528 encoder->base.id, encoder->name);
8529
8530 if (old->load_detect_temp) {
8531 to_intel_connector(connector)->new_encoder = NULL;
8532 intel_encoder->new_crtc = NULL;
8533 intel_crtc->new_enabled = false;
8534 intel_crtc->new_config = NULL;
8535 intel_set_mode(crtc, NULL, 0, 0, NULL);
8536
8537 if (old->release_fb) {
8538 drm_framebuffer_unregister_private(old->release_fb);
8539 drm_framebuffer_unreference(old->release_fb);
8540 }
8541
8542 goto unlock;
8543 return;
8544 }
8545
8546 /* Switch crtc and encoder back off if necessary */
8547 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8548 connector->funcs->dpms(connector, old->dpms_mode);
8549
8550 unlock:
8551 drm_modeset_drop_locks(ctx);
8552 drm_modeset_acquire_fini(ctx);
8553 }
8554
8555 static int i9xx_pll_refclk(struct drm_device *dev,
8556 const struct intel_crtc_config *pipe_config)
8557 {
8558 struct drm_i915_private *dev_priv = dev->dev_private;
8559 u32 dpll = pipe_config->dpll_hw_state.dpll;
8560
8561 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8562 return dev_priv->vbt.lvds_ssc_freq;
8563 else if (HAS_PCH_SPLIT(dev))
8564 return 120000;
8565 else if (!IS_GEN2(dev))
8566 return 96000;
8567 else
8568 return 48000;
8569 }
8570
8571 /* Returns the clock of the currently programmed mode of the given pipe. */
8572 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8573 struct intel_crtc_config *pipe_config)
8574 {
8575 struct drm_device *dev = crtc->base.dev;
8576 struct drm_i915_private *dev_priv = dev->dev_private;
8577 int pipe = pipe_config->cpu_transcoder;
8578 u32 dpll = pipe_config->dpll_hw_state.dpll;
8579 u32 fp;
8580 intel_clock_t clock;
8581 int refclk = i9xx_pll_refclk(dev, pipe_config);
8582
8583 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8584 fp = pipe_config->dpll_hw_state.fp0;
8585 else
8586 fp = pipe_config->dpll_hw_state.fp1;
8587
8588 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8589 if (IS_PINEVIEW(dev)) {
8590 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8591 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8592 } else {
8593 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8594 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8595 }
8596
8597 if (!IS_GEN2(dev)) {
8598 if (IS_PINEVIEW(dev))
8599 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8600 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8601 else
8602 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8603 DPLL_FPA01_P1_POST_DIV_SHIFT);
8604
8605 switch (dpll & DPLL_MODE_MASK) {
8606 case DPLLB_MODE_DAC_SERIAL:
8607 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8608 5 : 10;
8609 break;
8610 case DPLLB_MODE_LVDS:
8611 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8612 7 : 14;
8613 break;
8614 default:
8615 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8616 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8617 return;
8618 }
8619
8620 if (IS_PINEVIEW(dev))
8621 pineview_clock(refclk, &clock);
8622 else
8623 i9xx_clock(refclk, &clock);
8624 } else {
8625 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8626 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8627
8628 if (is_lvds) {
8629 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8630 DPLL_FPA01_P1_POST_DIV_SHIFT);
8631
8632 if (lvds & LVDS_CLKB_POWER_UP)
8633 clock.p2 = 7;
8634 else
8635 clock.p2 = 14;
8636 } else {
8637 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8638 clock.p1 = 2;
8639 else {
8640 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8641 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8642 }
8643 if (dpll & PLL_P2_DIVIDE_BY_4)
8644 clock.p2 = 4;
8645 else
8646 clock.p2 = 2;
8647 }
8648
8649 i9xx_clock(refclk, &clock);
8650 }
8651
8652 /*
8653 * This value includes pixel_multiplier. We will use
8654 * port_clock to compute adjusted_mode.crtc_clock in the
8655 * encoder's get_config() function.
8656 */
8657 pipe_config->port_clock = clock.dot;
8658 }
8659
8660 int intel_dotclock_calculate(int link_freq,
8661 const struct intel_link_m_n *m_n)
8662 {
8663 /*
8664 * The calculation for the data clock is:
8665 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8666 * But we want to avoid losing precison if possible, so:
8667 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8668 *
8669 * and the link clock is simpler:
8670 * link_clock = (m * link_clock) / n
8671 */
8672
8673 if (!m_n->link_n)
8674 return 0;
8675
8676 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8677 }
8678
8679 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8680 struct intel_crtc_config *pipe_config)
8681 {
8682 struct drm_device *dev = crtc->base.dev;
8683
8684 /* read out port_clock from the DPLL */
8685 i9xx_crtc_clock_get(crtc, pipe_config);
8686
8687 /*
8688 * This value does not include pixel_multiplier.
8689 * We will check that port_clock and adjusted_mode.crtc_clock
8690 * agree once we know their relationship in the encoder's
8691 * get_config() function.
8692 */
8693 pipe_config->adjusted_mode.crtc_clock =
8694 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8695 &pipe_config->fdi_m_n);
8696 }
8697
8698 /** Returns the currently programmed mode of the given pipe. */
8699 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8700 struct drm_crtc *crtc)
8701 {
8702 struct drm_i915_private *dev_priv = dev->dev_private;
8703 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8704 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8705 struct drm_display_mode *mode;
8706 struct intel_crtc_config pipe_config;
8707 int htot = I915_READ(HTOTAL(cpu_transcoder));
8708 int hsync = I915_READ(HSYNC(cpu_transcoder));
8709 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8710 int vsync = I915_READ(VSYNC(cpu_transcoder));
8711 enum pipe pipe = intel_crtc->pipe;
8712
8713 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8714 if (!mode)
8715 return NULL;
8716
8717 /*
8718 * Construct a pipe_config sufficient for getting the clock info
8719 * back out of crtc_clock_get.
8720 *
8721 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8722 * to use a real value here instead.
8723 */
8724 pipe_config.cpu_transcoder = (enum transcoder) pipe;
8725 pipe_config.pixel_multiplier = 1;
8726 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8727 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8728 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8729 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8730
8731 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8732 mode->hdisplay = (htot & 0xffff) + 1;
8733 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8734 mode->hsync_start = (hsync & 0xffff) + 1;
8735 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8736 mode->vdisplay = (vtot & 0xffff) + 1;
8737 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8738 mode->vsync_start = (vsync & 0xffff) + 1;
8739 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8740
8741 drm_mode_set_name(mode);
8742
8743 return mode;
8744 }
8745
8746 static void intel_increase_pllclock(struct drm_device *dev,
8747 enum pipe pipe)
8748 {
8749 struct drm_i915_private *dev_priv = dev->dev_private;
8750 int dpll_reg = DPLL(pipe);
8751 int dpll;
8752
8753 if (HAS_PCH_SPLIT(dev))
8754 return;
8755
8756 if (!dev_priv->lvds_downclock_avail)
8757 return;
8758
8759 dpll = I915_READ(dpll_reg);
8760 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8761 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8762
8763 assert_panel_unlocked(dev_priv, pipe);
8764
8765 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8766 I915_WRITE(dpll_reg, dpll);
8767 intel_wait_for_vblank(dev, pipe);
8768
8769 dpll = I915_READ(dpll_reg);
8770 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8771 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8772 }
8773 }
8774
8775 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8776 {
8777 struct drm_device *dev = crtc->dev;
8778 struct drm_i915_private *dev_priv = dev->dev_private;
8779 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8780
8781 if (HAS_PCH_SPLIT(dev))
8782 return;
8783
8784 if (!dev_priv->lvds_downclock_avail)
8785 return;
8786
8787 /*
8788 * Since this is called by a timer, we should never get here in
8789 * the manual case.
8790 */
8791 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8792 int pipe = intel_crtc->pipe;
8793 int dpll_reg = DPLL(pipe);
8794 int dpll;
8795
8796 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8797
8798 assert_panel_unlocked(dev_priv, pipe);
8799
8800 dpll = I915_READ(dpll_reg);
8801 dpll |= DISPLAY_RATE_SELECT_FPA1;
8802 I915_WRITE(dpll_reg, dpll);
8803 intel_wait_for_vblank(dev, pipe);
8804 dpll = I915_READ(dpll_reg);
8805 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8806 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8807 }
8808
8809 }
8810
8811 void intel_mark_busy(struct drm_device *dev)
8812 {
8813 struct drm_i915_private *dev_priv = dev->dev_private;
8814
8815 if (dev_priv->mm.busy)
8816 return;
8817
8818 intel_runtime_pm_get(dev_priv);
8819 i915_update_gfx_val(dev_priv);
8820 dev_priv->mm.busy = true;
8821 }
8822
8823 void intel_mark_idle(struct drm_device *dev)
8824 {
8825 struct drm_i915_private *dev_priv = dev->dev_private;
8826 struct drm_crtc *crtc;
8827
8828 if (!dev_priv->mm.busy)
8829 return;
8830
8831 dev_priv->mm.busy = false;
8832
8833 if (!i915.powersave)
8834 goto out;
8835
8836 for_each_crtc(dev, crtc) {
8837 if (!crtc->primary->fb)
8838 continue;
8839
8840 intel_decrease_pllclock(crtc);
8841 }
8842
8843 if (INTEL_INFO(dev)->gen >= 6)
8844 gen6_rps_idle(dev->dev_private);
8845
8846 out:
8847 intel_runtime_pm_put(dev_priv);
8848 }
8849
8850
8851 /**
8852 * intel_mark_fb_busy - mark given planes as busy
8853 * @dev: DRM device
8854 * @frontbuffer_bits: bits for the affected planes
8855 * @ring: optional ring for asynchronous commands
8856 *
8857 * This function gets called every time the screen contents change. It can be
8858 * used to keep e.g. the update rate at the nominal refresh rate with DRRS.
8859 */
8860 static void intel_mark_fb_busy(struct drm_device *dev,
8861 unsigned frontbuffer_bits,
8862 struct intel_engine_cs *ring)
8863 {
8864 enum pipe pipe;
8865
8866 if (!i915.powersave)
8867 return;
8868
8869 for_each_pipe(pipe) {
8870 if (!(frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe)))
8871 continue;
8872
8873 intel_increase_pllclock(dev, pipe);
8874 if (ring && intel_fbc_enabled(dev))
8875 ring->fbc_dirty = true;
8876 }
8877 }
8878
8879 /**
8880 * intel_fb_obj_invalidate - invalidate frontbuffer object
8881 * @obj: GEM object to invalidate
8882 * @ring: set for asynchronous rendering
8883 *
8884 * This function gets called every time rendering on the given object starts and
8885 * frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must
8886 * be invalidated. If @ring is non-NULL any subsequent invalidation will be delayed
8887 * until the rendering completes or a flip on this frontbuffer plane is
8888 * scheduled.
8889 */
8890 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
8891 struct intel_engine_cs *ring)
8892 {
8893 struct drm_device *dev = obj->base.dev;
8894 struct drm_i915_private *dev_priv = dev->dev_private;
8895
8896 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
8897
8898 if (!obj->frontbuffer_bits)
8899 return;
8900
8901 if (ring) {
8902 mutex_lock(&dev_priv->fb_tracking.lock);
8903 dev_priv->fb_tracking.busy_bits
8904 |= obj->frontbuffer_bits;
8905 dev_priv->fb_tracking.flip_bits
8906 &= ~obj->frontbuffer_bits;
8907 mutex_unlock(&dev_priv->fb_tracking.lock);
8908 }
8909
8910 intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring);
8911
8912 intel_edp_psr_exit(dev);
8913 }
8914
8915 /**
8916 * intel_frontbuffer_flush - flush frontbuffer
8917 * @dev: DRM device
8918 * @frontbuffer_bits: frontbuffer plane tracking bits
8919 *
8920 * This function gets called every time rendering on the given planes has
8921 * completed and frontbuffer caching can be started again. Flushes will get
8922 * delayed if they're blocked by some oustanding asynchronous rendering.
8923 *
8924 * Can be called without any locks held.
8925 */
8926 void intel_frontbuffer_flush(struct drm_device *dev,
8927 unsigned frontbuffer_bits)
8928 {
8929 struct drm_i915_private *dev_priv = dev->dev_private;
8930
8931 /* Delay flushing when rings are still busy.*/
8932 mutex_lock(&dev_priv->fb_tracking.lock);
8933 frontbuffer_bits &= ~dev_priv->fb_tracking.busy_bits;
8934 mutex_unlock(&dev_priv->fb_tracking.lock);
8935
8936 intel_mark_fb_busy(dev, frontbuffer_bits, NULL);
8937
8938 intel_edp_psr_exit(dev);
8939 }
8940
8941 /**
8942 * intel_fb_obj_flush - flush frontbuffer object
8943 * @obj: GEM object to flush
8944 * @retire: set when retiring asynchronous rendering
8945 *
8946 * This function gets called every time rendering on the given object has
8947 * completed and frontbuffer caching can be started again. If @retire is true
8948 * then any delayed flushes will be unblocked.
8949 */
8950 void intel_fb_obj_flush(struct drm_i915_gem_object *obj,
8951 bool retire)
8952 {
8953 struct drm_device *dev = obj->base.dev;
8954 struct drm_i915_private *dev_priv = dev->dev_private;
8955 unsigned frontbuffer_bits;
8956
8957 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
8958
8959 if (!obj->frontbuffer_bits)
8960 return;
8961
8962 frontbuffer_bits = obj->frontbuffer_bits;
8963
8964 if (retire) {
8965 mutex_lock(&dev_priv->fb_tracking.lock);
8966 /* Filter out new bits since rendering started. */
8967 frontbuffer_bits &= dev_priv->fb_tracking.busy_bits;
8968
8969 dev_priv->fb_tracking.busy_bits &= ~frontbuffer_bits;
8970 mutex_unlock(&dev_priv->fb_tracking.lock);
8971 }
8972
8973 intel_frontbuffer_flush(dev, frontbuffer_bits);
8974 }
8975
8976 /**
8977 * intel_frontbuffer_flip_prepare - prepare asnychronous frontbuffer flip
8978 * @dev: DRM device
8979 * @frontbuffer_bits: frontbuffer plane tracking bits
8980 *
8981 * This function gets called after scheduling a flip on @obj. The actual
8982 * frontbuffer flushing will be delayed until completion is signalled with
8983 * intel_frontbuffer_flip_complete. If an invalidate happens in between this
8984 * flush will be cancelled.
8985 *
8986 * Can be called without any locks held.
8987 */
8988 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
8989 unsigned frontbuffer_bits)
8990 {
8991 struct drm_i915_private *dev_priv = dev->dev_private;
8992
8993 mutex_lock(&dev_priv->fb_tracking.lock);
8994 dev_priv->fb_tracking.flip_bits
8995 |= frontbuffer_bits;
8996 mutex_unlock(&dev_priv->fb_tracking.lock);
8997 }
8998
8999 /**
9000 * intel_frontbuffer_flip_complete - complete asynchronous frontbuffer flush
9001 * @dev: DRM device
9002 * @frontbuffer_bits: frontbuffer plane tracking bits
9003 *
9004 * This function gets called after the flip has been latched and will complete
9005 * on the next vblank. It will execute the fush if it hasn't been cancalled yet.
9006 *
9007 * Can be called without any locks held.
9008 */
9009 void intel_frontbuffer_flip_complete(struct drm_device *dev,
9010 unsigned frontbuffer_bits)
9011 {
9012 struct drm_i915_private *dev_priv = dev->dev_private;
9013
9014 mutex_lock(&dev_priv->fb_tracking.lock);
9015 /* Mask any cancelled flips. */
9016 frontbuffer_bits &= dev_priv->fb_tracking.flip_bits;
9017 dev_priv->fb_tracking.flip_bits &= ~frontbuffer_bits;
9018 mutex_unlock(&dev_priv->fb_tracking.lock);
9019
9020 intel_frontbuffer_flush(dev, frontbuffer_bits);
9021 }
9022
9023 static void intel_crtc_destroy(struct drm_crtc *crtc)
9024 {
9025 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9026 struct drm_device *dev = crtc->dev;
9027 struct intel_unpin_work *work;
9028 unsigned long flags;
9029
9030 spin_lock_irqsave(&dev->event_lock, flags);
9031 work = intel_crtc->unpin_work;
9032 intel_crtc->unpin_work = NULL;
9033 spin_unlock_irqrestore(&dev->event_lock, flags);
9034
9035 if (work) {
9036 cancel_work_sync(&work->work);
9037 kfree(work);
9038 }
9039
9040 drm_crtc_cleanup(crtc);
9041
9042 kfree(intel_crtc);
9043 }
9044
9045 static void intel_unpin_work_fn(struct work_struct *__work)
9046 {
9047 struct intel_unpin_work *work =
9048 container_of(__work, struct intel_unpin_work, work);
9049 struct drm_device *dev = work->crtc->dev;
9050 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9051
9052 mutex_lock(&dev->struct_mutex);
9053 intel_unpin_fb_obj(work->old_fb_obj);
9054 drm_gem_object_unreference(&work->pending_flip_obj->base);
9055 drm_gem_object_unreference(&work->old_fb_obj->base);
9056
9057 intel_update_fbc(dev);
9058 mutex_unlock(&dev->struct_mutex);
9059
9060 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9061
9062 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9063 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9064
9065 kfree(work);
9066 }
9067
9068 static void do_intel_finish_page_flip(struct drm_device *dev,
9069 struct drm_crtc *crtc)
9070 {
9071 struct drm_i915_private *dev_priv = dev->dev_private;
9072 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9073 struct intel_unpin_work *work;
9074 unsigned long flags;
9075
9076 /* Ignore early vblank irqs */
9077 if (intel_crtc == NULL)
9078 return;
9079
9080 spin_lock_irqsave(&dev->event_lock, flags);
9081 work = intel_crtc->unpin_work;
9082
9083 /* Ensure we don't miss a work->pending update ... */
9084 smp_rmb();
9085
9086 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9087 spin_unlock_irqrestore(&dev->event_lock, flags);
9088 return;
9089 }
9090
9091 /* and that the unpin work is consistent wrt ->pending. */
9092 smp_rmb();
9093
9094 intel_crtc->unpin_work = NULL;
9095
9096 if (work->event)
9097 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
9098
9099 drm_crtc_vblank_put(crtc);
9100
9101 spin_unlock_irqrestore(&dev->event_lock, flags);
9102
9103 wake_up_all(&dev_priv->pending_flip_queue);
9104
9105 queue_work(dev_priv->wq, &work->work);
9106
9107 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
9108 }
9109
9110 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9111 {
9112 struct drm_i915_private *dev_priv = dev->dev_private;
9113 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9114
9115 do_intel_finish_page_flip(dev, crtc);
9116 }
9117
9118 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9119 {
9120 struct drm_i915_private *dev_priv = dev->dev_private;
9121 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9122
9123 do_intel_finish_page_flip(dev, crtc);
9124 }
9125
9126 /* Is 'a' after or equal to 'b'? */
9127 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9128 {
9129 return !((a - b) & 0x80000000);
9130 }
9131
9132 static bool page_flip_finished(struct intel_crtc *crtc)
9133 {
9134 struct drm_device *dev = crtc->base.dev;
9135 struct drm_i915_private *dev_priv = dev->dev_private;
9136
9137 /*
9138 * The relevant registers doen't exist on pre-ctg.
9139 * As the flip done interrupt doesn't trigger for mmio
9140 * flips on gmch platforms, a flip count check isn't
9141 * really needed there. But since ctg has the registers,
9142 * include it in the check anyway.
9143 */
9144 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9145 return true;
9146
9147 /*
9148 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9149 * used the same base address. In that case the mmio flip might
9150 * have completed, but the CS hasn't even executed the flip yet.
9151 *
9152 * A flip count check isn't enough as the CS might have updated
9153 * the base address just after start of vblank, but before we
9154 * managed to process the interrupt. This means we'd complete the
9155 * CS flip too soon.
9156 *
9157 * Combining both checks should get us a good enough result. It may
9158 * still happen that the CS flip has been executed, but has not
9159 * yet actually completed. But in case the base address is the same
9160 * anyway, we don't really care.
9161 */
9162 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9163 crtc->unpin_work->gtt_offset &&
9164 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9165 crtc->unpin_work->flip_count);
9166 }
9167
9168 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9169 {
9170 struct drm_i915_private *dev_priv = dev->dev_private;
9171 struct intel_crtc *intel_crtc =
9172 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9173 unsigned long flags;
9174
9175 /* NB: An MMIO update of the plane base pointer will also
9176 * generate a page-flip completion irq, i.e. every modeset
9177 * is also accompanied by a spurious intel_prepare_page_flip().
9178 */
9179 spin_lock_irqsave(&dev->event_lock, flags);
9180 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9181 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9182 spin_unlock_irqrestore(&dev->event_lock, flags);
9183 }
9184
9185 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9186 {
9187 /* Ensure that the work item is consistent when activating it ... */
9188 smp_wmb();
9189 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9190 /* and that it is marked active as soon as the irq could fire. */
9191 smp_wmb();
9192 }
9193
9194 static int intel_gen2_queue_flip(struct drm_device *dev,
9195 struct drm_crtc *crtc,
9196 struct drm_framebuffer *fb,
9197 struct drm_i915_gem_object *obj,
9198 struct intel_engine_cs *ring,
9199 uint32_t flags)
9200 {
9201 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9202 u32 flip_mask;
9203 int ret;
9204
9205 ret = intel_ring_begin(ring, 6);
9206 if (ret)
9207 return ret;
9208
9209 /* Can't queue multiple flips, so wait for the previous
9210 * one to finish before executing the next.
9211 */
9212 if (intel_crtc->plane)
9213 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9214 else
9215 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9216 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9217 intel_ring_emit(ring, MI_NOOP);
9218 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9219 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9220 intel_ring_emit(ring, fb->pitches[0]);
9221 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9222 intel_ring_emit(ring, 0); /* aux display base address, unused */
9223
9224 intel_mark_page_flip_active(intel_crtc);
9225 __intel_ring_advance(ring);
9226 return 0;
9227 }
9228
9229 static int intel_gen3_queue_flip(struct drm_device *dev,
9230 struct drm_crtc *crtc,
9231 struct drm_framebuffer *fb,
9232 struct drm_i915_gem_object *obj,
9233 struct intel_engine_cs *ring,
9234 uint32_t flags)
9235 {
9236 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9237 u32 flip_mask;
9238 int ret;
9239
9240 ret = intel_ring_begin(ring, 6);
9241 if (ret)
9242 return ret;
9243
9244 if (intel_crtc->plane)
9245 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9246 else
9247 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9248 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9249 intel_ring_emit(ring, MI_NOOP);
9250 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9251 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9252 intel_ring_emit(ring, fb->pitches[0]);
9253 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9254 intel_ring_emit(ring, MI_NOOP);
9255
9256 intel_mark_page_flip_active(intel_crtc);
9257 __intel_ring_advance(ring);
9258 return 0;
9259 }
9260
9261 static int intel_gen4_queue_flip(struct drm_device *dev,
9262 struct drm_crtc *crtc,
9263 struct drm_framebuffer *fb,
9264 struct drm_i915_gem_object *obj,
9265 struct intel_engine_cs *ring,
9266 uint32_t flags)
9267 {
9268 struct drm_i915_private *dev_priv = dev->dev_private;
9269 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9270 uint32_t pf, pipesrc;
9271 int ret;
9272
9273 ret = intel_ring_begin(ring, 4);
9274 if (ret)
9275 return ret;
9276
9277 /* i965+ uses the linear or tiled offsets from the
9278 * Display Registers (which do not change across a page-flip)
9279 * so we need only reprogram the base address.
9280 */
9281 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9282 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9283 intel_ring_emit(ring, fb->pitches[0]);
9284 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9285 obj->tiling_mode);
9286
9287 /* XXX Enabling the panel-fitter across page-flip is so far
9288 * untested on non-native modes, so ignore it for now.
9289 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9290 */
9291 pf = 0;
9292 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9293 intel_ring_emit(ring, pf | pipesrc);
9294
9295 intel_mark_page_flip_active(intel_crtc);
9296 __intel_ring_advance(ring);
9297 return 0;
9298 }
9299
9300 static int intel_gen6_queue_flip(struct drm_device *dev,
9301 struct drm_crtc *crtc,
9302 struct drm_framebuffer *fb,
9303 struct drm_i915_gem_object *obj,
9304 struct intel_engine_cs *ring,
9305 uint32_t flags)
9306 {
9307 struct drm_i915_private *dev_priv = dev->dev_private;
9308 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9309 uint32_t pf, pipesrc;
9310 int ret;
9311
9312 ret = intel_ring_begin(ring, 4);
9313 if (ret)
9314 return ret;
9315
9316 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9317 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9318 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9319 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9320
9321 /* Contrary to the suggestions in the documentation,
9322 * "Enable Panel Fitter" does not seem to be required when page
9323 * flipping with a non-native mode, and worse causes a normal
9324 * modeset to fail.
9325 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9326 */
9327 pf = 0;
9328 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9329 intel_ring_emit(ring, pf | pipesrc);
9330
9331 intel_mark_page_flip_active(intel_crtc);
9332 __intel_ring_advance(ring);
9333 return 0;
9334 }
9335
9336 static int intel_gen7_queue_flip(struct drm_device *dev,
9337 struct drm_crtc *crtc,
9338 struct drm_framebuffer *fb,
9339 struct drm_i915_gem_object *obj,
9340 struct intel_engine_cs *ring,
9341 uint32_t flags)
9342 {
9343 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9344 uint32_t plane_bit = 0;
9345 int len, ret;
9346
9347 switch (intel_crtc->plane) {
9348 case PLANE_A:
9349 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9350 break;
9351 case PLANE_B:
9352 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9353 break;
9354 case PLANE_C:
9355 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9356 break;
9357 default:
9358 WARN_ONCE(1, "unknown plane in flip command\n");
9359 return -ENODEV;
9360 }
9361
9362 len = 4;
9363 if (ring->id == RCS) {
9364 len += 6;
9365 /*
9366 * On Gen 8, SRM is now taking an extra dword to accommodate
9367 * 48bits addresses, and we need a NOOP for the batch size to
9368 * stay even.
9369 */
9370 if (IS_GEN8(dev))
9371 len += 2;
9372 }
9373
9374 /*
9375 * BSpec MI_DISPLAY_FLIP for IVB:
9376 * "The full packet must be contained within the same cache line."
9377 *
9378 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9379 * cacheline, if we ever start emitting more commands before
9380 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9381 * then do the cacheline alignment, and finally emit the
9382 * MI_DISPLAY_FLIP.
9383 */
9384 ret = intel_ring_cacheline_align(ring);
9385 if (ret)
9386 return ret;
9387
9388 ret = intel_ring_begin(ring, len);
9389 if (ret)
9390 return ret;
9391
9392 /* Unmask the flip-done completion message. Note that the bspec says that
9393 * we should do this for both the BCS and RCS, and that we must not unmask
9394 * more than one flip event at any time (or ensure that one flip message
9395 * can be sent by waiting for flip-done prior to queueing new flips).
9396 * Experimentation says that BCS works despite DERRMR masking all
9397 * flip-done completion events and that unmasking all planes at once
9398 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9399 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9400 */
9401 if (ring->id == RCS) {
9402 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9403 intel_ring_emit(ring, DERRMR);
9404 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9405 DERRMR_PIPEB_PRI_FLIP_DONE |
9406 DERRMR_PIPEC_PRI_FLIP_DONE));
9407 if (IS_GEN8(dev))
9408 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9409 MI_SRM_LRM_GLOBAL_GTT);
9410 else
9411 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9412 MI_SRM_LRM_GLOBAL_GTT);
9413 intel_ring_emit(ring, DERRMR);
9414 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9415 if (IS_GEN8(dev)) {
9416 intel_ring_emit(ring, 0);
9417 intel_ring_emit(ring, MI_NOOP);
9418 }
9419 }
9420
9421 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9422 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9423 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9424 intel_ring_emit(ring, (MI_NOOP));
9425
9426 intel_mark_page_flip_active(intel_crtc);
9427 __intel_ring_advance(ring);
9428 return 0;
9429 }
9430
9431 static bool use_mmio_flip(struct intel_engine_cs *ring,
9432 struct drm_i915_gem_object *obj)
9433 {
9434 /*
9435 * This is not being used for older platforms, because
9436 * non-availability of flip done interrupt forces us to use
9437 * CS flips. Older platforms derive flip done using some clever
9438 * tricks involving the flip_pending status bits and vblank irqs.
9439 * So using MMIO flips there would disrupt this mechanism.
9440 */
9441
9442 if (ring == NULL)
9443 return true;
9444
9445 if (INTEL_INFO(ring->dev)->gen < 5)
9446 return false;
9447
9448 if (i915.use_mmio_flip < 0)
9449 return false;
9450 else if (i915.use_mmio_flip > 0)
9451 return true;
9452 else
9453 return ring != obj->ring;
9454 }
9455
9456 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9457 {
9458 struct drm_device *dev = intel_crtc->base.dev;
9459 struct drm_i915_private *dev_priv = dev->dev_private;
9460 struct intel_framebuffer *intel_fb =
9461 to_intel_framebuffer(intel_crtc->base.primary->fb);
9462 struct drm_i915_gem_object *obj = intel_fb->obj;
9463 u32 dspcntr;
9464 u32 reg;
9465
9466 intel_mark_page_flip_active(intel_crtc);
9467
9468 reg = DSPCNTR(intel_crtc->plane);
9469 dspcntr = I915_READ(reg);
9470
9471 if (INTEL_INFO(dev)->gen >= 4) {
9472 if (obj->tiling_mode != I915_TILING_NONE)
9473 dspcntr |= DISPPLANE_TILED;
9474 else
9475 dspcntr &= ~DISPPLANE_TILED;
9476 }
9477 I915_WRITE(reg, dspcntr);
9478
9479 I915_WRITE(DSPSURF(intel_crtc->plane),
9480 intel_crtc->unpin_work->gtt_offset);
9481 POSTING_READ(DSPSURF(intel_crtc->plane));
9482 }
9483
9484 static int intel_postpone_flip(struct drm_i915_gem_object *obj)
9485 {
9486 struct intel_engine_cs *ring;
9487 int ret;
9488
9489 lockdep_assert_held(&obj->base.dev->struct_mutex);
9490
9491 if (!obj->last_write_seqno)
9492 return 0;
9493
9494 ring = obj->ring;
9495
9496 if (i915_seqno_passed(ring->get_seqno(ring, true),
9497 obj->last_write_seqno))
9498 return 0;
9499
9500 ret = i915_gem_check_olr(ring, obj->last_write_seqno);
9501 if (ret)
9502 return ret;
9503
9504 if (WARN_ON(!ring->irq_get(ring)))
9505 return 0;
9506
9507 return 1;
9508 }
9509
9510 void intel_notify_mmio_flip(struct intel_engine_cs *ring)
9511 {
9512 struct drm_i915_private *dev_priv = to_i915(ring->dev);
9513 struct intel_crtc *intel_crtc;
9514 unsigned long irq_flags;
9515 u32 seqno;
9516
9517 seqno = ring->get_seqno(ring, false);
9518
9519 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9520 for_each_intel_crtc(ring->dev, intel_crtc) {
9521 struct intel_mmio_flip *mmio_flip;
9522
9523 mmio_flip = &intel_crtc->mmio_flip;
9524 if (mmio_flip->seqno == 0)
9525 continue;
9526
9527 if (ring->id != mmio_flip->ring_id)
9528 continue;
9529
9530 if (i915_seqno_passed(seqno, mmio_flip->seqno)) {
9531 intel_do_mmio_flip(intel_crtc);
9532 mmio_flip->seqno = 0;
9533 ring->irq_put(ring);
9534 }
9535 }
9536 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9537 }
9538
9539 static int intel_queue_mmio_flip(struct drm_device *dev,
9540 struct drm_crtc *crtc,
9541 struct drm_framebuffer *fb,
9542 struct drm_i915_gem_object *obj,
9543 struct intel_engine_cs *ring,
9544 uint32_t flags)
9545 {
9546 struct drm_i915_private *dev_priv = dev->dev_private;
9547 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9548 unsigned long irq_flags;
9549 int ret;
9550
9551 if (WARN_ON(intel_crtc->mmio_flip.seqno))
9552 return -EBUSY;
9553
9554 ret = intel_postpone_flip(obj);
9555 if (ret < 0)
9556 return ret;
9557 if (ret == 0) {
9558 intel_do_mmio_flip(intel_crtc);
9559 return 0;
9560 }
9561
9562 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9563 intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9564 intel_crtc->mmio_flip.ring_id = obj->ring->id;
9565 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9566
9567 /*
9568 * Double check to catch cases where irq fired before
9569 * mmio flip data was ready
9570 */
9571 intel_notify_mmio_flip(obj->ring);
9572 return 0;
9573 }
9574
9575 static int intel_default_queue_flip(struct drm_device *dev,
9576 struct drm_crtc *crtc,
9577 struct drm_framebuffer *fb,
9578 struct drm_i915_gem_object *obj,
9579 struct intel_engine_cs *ring,
9580 uint32_t flags)
9581 {
9582 return -ENODEV;
9583 }
9584
9585 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9586 struct drm_framebuffer *fb,
9587 struct drm_pending_vblank_event *event,
9588 uint32_t page_flip_flags)
9589 {
9590 struct drm_device *dev = crtc->dev;
9591 struct drm_i915_private *dev_priv = dev->dev_private;
9592 struct drm_framebuffer *old_fb = crtc->primary->fb;
9593 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9594 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9595 enum pipe pipe = intel_crtc->pipe;
9596 struct intel_unpin_work *work;
9597 struct intel_engine_cs *ring;
9598 unsigned long flags;
9599 int ret;
9600
9601 /*
9602 * drm_mode_page_flip_ioctl() should already catch this, but double
9603 * check to be safe. In the future we may enable pageflipping from
9604 * a disabled primary plane.
9605 */
9606 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9607 return -EBUSY;
9608
9609 /* Can't change pixel format via MI display flips. */
9610 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9611 return -EINVAL;
9612
9613 /*
9614 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9615 * Note that pitch changes could also affect these register.
9616 */
9617 if (INTEL_INFO(dev)->gen > 3 &&
9618 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9619 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9620 return -EINVAL;
9621
9622 if (i915_terminally_wedged(&dev_priv->gpu_error))
9623 goto out_hang;
9624
9625 work = kzalloc(sizeof(*work), GFP_KERNEL);
9626 if (work == NULL)
9627 return -ENOMEM;
9628
9629 work->event = event;
9630 work->crtc = crtc;
9631 work->old_fb_obj = intel_fb_obj(old_fb);
9632 INIT_WORK(&work->work, intel_unpin_work_fn);
9633
9634 ret = drm_crtc_vblank_get(crtc);
9635 if (ret)
9636 goto free_work;
9637
9638 /* We borrow the event spin lock for protecting unpin_work */
9639 spin_lock_irqsave(&dev->event_lock, flags);
9640 if (intel_crtc->unpin_work) {
9641 spin_unlock_irqrestore(&dev->event_lock, flags);
9642 kfree(work);
9643 drm_crtc_vblank_put(crtc);
9644
9645 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9646 return -EBUSY;
9647 }
9648 intel_crtc->unpin_work = work;
9649 spin_unlock_irqrestore(&dev->event_lock, flags);
9650
9651 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9652 flush_workqueue(dev_priv->wq);
9653
9654 ret = i915_mutex_lock_interruptible(dev);
9655 if (ret)
9656 goto cleanup;
9657
9658 /* Reference the objects for the scheduled work. */
9659 drm_gem_object_reference(&work->old_fb_obj->base);
9660 drm_gem_object_reference(&obj->base);
9661
9662 crtc->primary->fb = fb;
9663
9664 work->pending_flip_obj = obj;
9665
9666 work->enable_stall_check = true;
9667
9668 atomic_inc(&intel_crtc->unpin_work_count);
9669 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9670
9671 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9672 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9673
9674 if (IS_VALLEYVIEW(dev)) {
9675 ring = &dev_priv->ring[BCS];
9676 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9677 /* vlv: DISPLAY_FLIP fails to change tiling */
9678 ring = NULL;
9679 } else if (IS_IVYBRIDGE(dev)) {
9680 ring = &dev_priv->ring[BCS];
9681 } else if (INTEL_INFO(dev)->gen >= 7) {
9682 ring = obj->ring;
9683 if (ring == NULL || ring->id != RCS)
9684 ring = &dev_priv->ring[BCS];
9685 } else {
9686 ring = &dev_priv->ring[RCS];
9687 }
9688
9689 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9690 if (ret)
9691 goto cleanup_pending;
9692
9693 work->gtt_offset =
9694 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9695
9696 if (use_mmio_flip(ring, obj))
9697 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9698 page_flip_flags);
9699 else
9700 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9701 page_flip_flags);
9702 if (ret)
9703 goto cleanup_unpin;
9704
9705 i915_gem_track_fb(work->old_fb_obj, obj,
9706 INTEL_FRONTBUFFER_PRIMARY(pipe));
9707
9708 intel_disable_fbc(dev);
9709 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9710 mutex_unlock(&dev->struct_mutex);
9711
9712 trace_i915_flip_request(intel_crtc->plane, obj);
9713
9714 return 0;
9715
9716 cleanup_unpin:
9717 intel_unpin_fb_obj(obj);
9718 cleanup_pending:
9719 atomic_dec(&intel_crtc->unpin_work_count);
9720 crtc->primary->fb = old_fb;
9721 drm_gem_object_unreference(&work->old_fb_obj->base);
9722 drm_gem_object_unreference(&obj->base);
9723 mutex_unlock(&dev->struct_mutex);
9724
9725 cleanup:
9726 spin_lock_irqsave(&dev->event_lock, flags);
9727 intel_crtc->unpin_work = NULL;
9728 spin_unlock_irqrestore(&dev->event_lock, flags);
9729
9730 drm_crtc_vblank_put(crtc);
9731 free_work:
9732 kfree(work);
9733
9734 if (ret == -EIO) {
9735 out_hang:
9736 intel_crtc_wait_for_pending_flips(crtc);
9737 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9738 if (ret == 0 && event)
9739 drm_send_vblank_event(dev, pipe, event);
9740 }
9741 return ret;
9742 }
9743
9744 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9745 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9746 .load_lut = intel_crtc_load_lut,
9747 };
9748
9749 /**
9750 * intel_modeset_update_staged_output_state
9751 *
9752 * Updates the staged output configuration state, e.g. after we've read out the
9753 * current hw state.
9754 */
9755 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9756 {
9757 struct intel_crtc *crtc;
9758 struct intel_encoder *encoder;
9759 struct intel_connector *connector;
9760
9761 list_for_each_entry(connector, &dev->mode_config.connector_list,
9762 base.head) {
9763 connector->new_encoder =
9764 to_intel_encoder(connector->base.encoder);
9765 }
9766
9767 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9768 base.head) {
9769 encoder->new_crtc =
9770 to_intel_crtc(encoder->base.crtc);
9771 }
9772
9773 for_each_intel_crtc(dev, crtc) {
9774 crtc->new_enabled = crtc->base.enabled;
9775
9776 if (crtc->new_enabled)
9777 crtc->new_config = &crtc->config;
9778 else
9779 crtc->new_config = NULL;
9780 }
9781 }
9782
9783 /**
9784 * intel_modeset_commit_output_state
9785 *
9786 * This function copies the stage display pipe configuration to the real one.
9787 */
9788 static void intel_modeset_commit_output_state(struct drm_device *dev)
9789 {
9790 struct intel_crtc *crtc;
9791 struct intel_encoder *encoder;
9792 struct intel_connector *connector;
9793
9794 list_for_each_entry(connector, &dev->mode_config.connector_list,
9795 base.head) {
9796 connector->base.encoder = &connector->new_encoder->base;
9797 }
9798
9799 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9800 base.head) {
9801 encoder->base.crtc = &encoder->new_crtc->base;
9802 }
9803
9804 for_each_intel_crtc(dev, crtc) {
9805 crtc->base.enabled = crtc->new_enabled;
9806 }
9807 }
9808
9809 static void
9810 connected_sink_compute_bpp(struct intel_connector *connector,
9811 struct intel_crtc_config *pipe_config)
9812 {
9813 int bpp = pipe_config->pipe_bpp;
9814
9815 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9816 connector->base.base.id,
9817 connector->base.name);
9818
9819 /* Don't use an invalid EDID bpc value */
9820 if (connector->base.display_info.bpc &&
9821 connector->base.display_info.bpc * 3 < bpp) {
9822 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9823 bpp, connector->base.display_info.bpc*3);
9824 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9825 }
9826
9827 /* Clamp bpp to 8 on screens without EDID 1.4 */
9828 if (connector->base.display_info.bpc == 0 && bpp > 24) {
9829 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9830 bpp);
9831 pipe_config->pipe_bpp = 24;
9832 }
9833 }
9834
9835 static int
9836 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9837 struct drm_framebuffer *fb,
9838 struct intel_crtc_config *pipe_config)
9839 {
9840 struct drm_device *dev = crtc->base.dev;
9841 struct intel_connector *connector;
9842 int bpp;
9843
9844 switch (fb->pixel_format) {
9845 case DRM_FORMAT_C8:
9846 bpp = 8*3; /* since we go through a colormap */
9847 break;
9848 case DRM_FORMAT_XRGB1555:
9849 case DRM_FORMAT_ARGB1555:
9850 /* checked in intel_framebuffer_init already */
9851 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9852 return -EINVAL;
9853 case DRM_FORMAT_RGB565:
9854 bpp = 6*3; /* min is 18bpp */
9855 break;
9856 case DRM_FORMAT_XBGR8888:
9857 case DRM_FORMAT_ABGR8888:
9858 /* checked in intel_framebuffer_init already */
9859 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9860 return -EINVAL;
9861 case DRM_FORMAT_XRGB8888:
9862 case DRM_FORMAT_ARGB8888:
9863 bpp = 8*3;
9864 break;
9865 case DRM_FORMAT_XRGB2101010:
9866 case DRM_FORMAT_ARGB2101010:
9867 case DRM_FORMAT_XBGR2101010:
9868 case DRM_FORMAT_ABGR2101010:
9869 /* checked in intel_framebuffer_init already */
9870 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9871 return -EINVAL;
9872 bpp = 10*3;
9873 break;
9874 /* TODO: gen4+ supports 16 bpc floating point, too. */
9875 default:
9876 DRM_DEBUG_KMS("unsupported depth\n");
9877 return -EINVAL;
9878 }
9879
9880 pipe_config->pipe_bpp = bpp;
9881
9882 /* Clamp display bpp to EDID value */
9883 list_for_each_entry(connector, &dev->mode_config.connector_list,
9884 base.head) {
9885 if (!connector->new_encoder ||
9886 connector->new_encoder->new_crtc != crtc)
9887 continue;
9888
9889 connected_sink_compute_bpp(connector, pipe_config);
9890 }
9891
9892 return bpp;
9893 }
9894
9895 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9896 {
9897 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9898 "type: 0x%x flags: 0x%x\n",
9899 mode->crtc_clock,
9900 mode->crtc_hdisplay, mode->crtc_hsync_start,
9901 mode->crtc_hsync_end, mode->crtc_htotal,
9902 mode->crtc_vdisplay, mode->crtc_vsync_start,
9903 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9904 }
9905
9906 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9907 struct intel_crtc_config *pipe_config,
9908 const char *context)
9909 {
9910 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9911 context, pipe_name(crtc->pipe));
9912
9913 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9914 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9915 pipe_config->pipe_bpp, pipe_config->dither);
9916 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9917 pipe_config->has_pch_encoder,
9918 pipe_config->fdi_lanes,
9919 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9920 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9921 pipe_config->fdi_m_n.tu);
9922 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9923 pipe_config->has_dp_encoder,
9924 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9925 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9926 pipe_config->dp_m_n.tu);
9927 DRM_DEBUG_KMS("requested mode:\n");
9928 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9929 DRM_DEBUG_KMS("adjusted mode:\n");
9930 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9931 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9932 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9933 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9934 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9935 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9936 pipe_config->gmch_pfit.control,
9937 pipe_config->gmch_pfit.pgm_ratios,
9938 pipe_config->gmch_pfit.lvds_border_bits);
9939 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9940 pipe_config->pch_pfit.pos,
9941 pipe_config->pch_pfit.size,
9942 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9943 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9944 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
9945 }
9946
9947 static bool encoders_cloneable(const struct intel_encoder *a,
9948 const struct intel_encoder *b)
9949 {
9950 /* masks could be asymmetric, so check both ways */
9951 return a == b || (a->cloneable & (1 << b->type) &&
9952 b->cloneable & (1 << a->type));
9953 }
9954
9955 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9956 struct intel_encoder *encoder)
9957 {
9958 struct drm_device *dev = crtc->base.dev;
9959 struct intel_encoder *source_encoder;
9960
9961 list_for_each_entry(source_encoder,
9962 &dev->mode_config.encoder_list, base.head) {
9963 if (source_encoder->new_crtc != crtc)
9964 continue;
9965
9966 if (!encoders_cloneable(encoder, source_encoder))
9967 return false;
9968 }
9969
9970 return true;
9971 }
9972
9973 static bool check_encoder_cloning(struct intel_crtc *crtc)
9974 {
9975 struct drm_device *dev = crtc->base.dev;
9976 struct intel_encoder *encoder;
9977
9978 list_for_each_entry(encoder,
9979 &dev->mode_config.encoder_list, base.head) {
9980 if (encoder->new_crtc != crtc)
9981 continue;
9982
9983 if (!check_single_encoder_cloning(crtc, encoder))
9984 return false;
9985 }
9986
9987 return true;
9988 }
9989
9990 static struct intel_crtc_config *
9991 intel_modeset_pipe_config(struct drm_crtc *crtc,
9992 struct drm_framebuffer *fb,
9993 struct drm_display_mode *mode)
9994 {
9995 struct drm_device *dev = crtc->dev;
9996 struct intel_encoder *encoder;
9997 struct intel_crtc_config *pipe_config;
9998 int plane_bpp, ret = -EINVAL;
9999 bool retry = true;
10000
10001 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10002 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10003 return ERR_PTR(-EINVAL);
10004 }
10005
10006 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10007 if (!pipe_config)
10008 return ERR_PTR(-ENOMEM);
10009
10010 drm_mode_copy(&pipe_config->adjusted_mode, mode);
10011 drm_mode_copy(&pipe_config->requested_mode, mode);
10012
10013 pipe_config->cpu_transcoder =
10014 (enum transcoder) to_intel_crtc(crtc)->pipe;
10015 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10016
10017 /*
10018 * Sanitize sync polarity flags based on requested ones. If neither
10019 * positive or negative polarity is requested, treat this as meaning
10020 * negative polarity.
10021 */
10022 if (!(pipe_config->adjusted_mode.flags &
10023 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10024 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10025
10026 if (!(pipe_config->adjusted_mode.flags &
10027 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10028 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10029
10030 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10031 * plane pixel format and any sink constraints into account. Returns the
10032 * source plane bpp so that dithering can be selected on mismatches
10033 * after encoders and crtc also have had their say. */
10034 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10035 fb, pipe_config);
10036 if (plane_bpp < 0)
10037 goto fail;
10038
10039 /*
10040 * Determine the real pipe dimensions. Note that stereo modes can
10041 * increase the actual pipe size due to the frame doubling and
10042 * insertion of additional space for blanks between the frame. This
10043 * is stored in the crtc timings. We use the requested mode to do this
10044 * computation to clearly distinguish it from the adjusted mode, which
10045 * can be changed by the connectors in the below retry loop.
10046 */
10047 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10048 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10049 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10050
10051 encoder_retry:
10052 /* Ensure the port clock defaults are reset when retrying. */
10053 pipe_config->port_clock = 0;
10054 pipe_config->pixel_multiplier = 1;
10055
10056 /* Fill in default crtc timings, allow encoders to overwrite them. */
10057 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
10058
10059 /* Pass our mode to the connectors and the CRTC to give them a chance to
10060 * adjust it according to limitations or connector properties, and also
10061 * a chance to reject the mode entirely.
10062 */
10063 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10064 base.head) {
10065
10066 if (&encoder->new_crtc->base != crtc)
10067 continue;
10068
10069 if (!(encoder->compute_config(encoder, pipe_config))) {
10070 DRM_DEBUG_KMS("Encoder config failure\n");
10071 goto fail;
10072 }
10073 }
10074
10075 /* Set default port clock if not overwritten by the encoder. Needs to be
10076 * done afterwards in case the encoder adjusts the mode. */
10077 if (!pipe_config->port_clock)
10078 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10079 * pipe_config->pixel_multiplier;
10080
10081 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10082 if (ret < 0) {
10083 DRM_DEBUG_KMS("CRTC fixup failed\n");
10084 goto fail;
10085 }
10086
10087 if (ret == RETRY) {
10088 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10089 ret = -EINVAL;
10090 goto fail;
10091 }
10092
10093 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10094 retry = false;
10095 goto encoder_retry;
10096 }
10097
10098 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10099 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10100 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10101
10102 return pipe_config;
10103 fail:
10104 kfree(pipe_config);
10105 return ERR_PTR(ret);
10106 }
10107
10108 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10109 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10110 static void
10111 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10112 unsigned *prepare_pipes, unsigned *disable_pipes)
10113 {
10114 struct intel_crtc *intel_crtc;
10115 struct drm_device *dev = crtc->dev;
10116 struct intel_encoder *encoder;
10117 struct intel_connector *connector;
10118 struct drm_crtc *tmp_crtc;
10119
10120 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10121
10122 /* Check which crtcs have changed outputs connected to them, these need
10123 * to be part of the prepare_pipes mask. We don't (yet) support global
10124 * modeset across multiple crtcs, so modeset_pipes will only have one
10125 * bit set at most. */
10126 list_for_each_entry(connector, &dev->mode_config.connector_list,
10127 base.head) {
10128 if (connector->base.encoder == &connector->new_encoder->base)
10129 continue;
10130
10131 if (connector->base.encoder) {
10132 tmp_crtc = connector->base.encoder->crtc;
10133
10134 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10135 }
10136
10137 if (connector->new_encoder)
10138 *prepare_pipes |=
10139 1 << connector->new_encoder->new_crtc->pipe;
10140 }
10141
10142 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10143 base.head) {
10144 if (encoder->base.crtc == &encoder->new_crtc->base)
10145 continue;
10146
10147 if (encoder->base.crtc) {
10148 tmp_crtc = encoder->base.crtc;
10149
10150 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10151 }
10152
10153 if (encoder->new_crtc)
10154 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10155 }
10156
10157 /* Check for pipes that will be enabled/disabled ... */
10158 for_each_intel_crtc(dev, intel_crtc) {
10159 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10160 continue;
10161
10162 if (!intel_crtc->new_enabled)
10163 *disable_pipes |= 1 << intel_crtc->pipe;
10164 else
10165 *prepare_pipes |= 1 << intel_crtc->pipe;
10166 }
10167
10168
10169 /* set_mode is also used to update properties on life display pipes. */
10170 intel_crtc = to_intel_crtc(crtc);
10171 if (intel_crtc->new_enabled)
10172 *prepare_pipes |= 1 << intel_crtc->pipe;
10173
10174 /*
10175 * For simplicity do a full modeset on any pipe where the output routing
10176 * changed. We could be more clever, but that would require us to be
10177 * more careful with calling the relevant encoder->mode_set functions.
10178 */
10179 if (*prepare_pipes)
10180 *modeset_pipes = *prepare_pipes;
10181
10182 /* ... and mask these out. */
10183 *modeset_pipes &= ~(*disable_pipes);
10184 *prepare_pipes &= ~(*disable_pipes);
10185
10186 /*
10187 * HACK: We don't (yet) fully support global modesets. intel_set_config
10188 * obies this rule, but the modeset restore mode of
10189 * intel_modeset_setup_hw_state does not.
10190 */
10191 *modeset_pipes &= 1 << intel_crtc->pipe;
10192 *prepare_pipes &= 1 << intel_crtc->pipe;
10193
10194 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10195 *modeset_pipes, *prepare_pipes, *disable_pipes);
10196 }
10197
10198 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10199 {
10200 struct drm_encoder *encoder;
10201 struct drm_device *dev = crtc->dev;
10202
10203 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10204 if (encoder->crtc == crtc)
10205 return true;
10206
10207 return false;
10208 }
10209
10210 static void
10211 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10212 {
10213 struct intel_encoder *intel_encoder;
10214 struct intel_crtc *intel_crtc;
10215 struct drm_connector *connector;
10216
10217 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
10218 base.head) {
10219 if (!intel_encoder->base.crtc)
10220 continue;
10221
10222 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10223
10224 if (prepare_pipes & (1 << intel_crtc->pipe))
10225 intel_encoder->connectors_active = false;
10226 }
10227
10228 intel_modeset_commit_output_state(dev);
10229
10230 /* Double check state. */
10231 for_each_intel_crtc(dev, intel_crtc) {
10232 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10233 WARN_ON(intel_crtc->new_config &&
10234 intel_crtc->new_config != &intel_crtc->config);
10235 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10236 }
10237
10238 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10239 if (!connector->encoder || !connector->encoder->crtc)
10240 continue;
10241
10242 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10243
10244 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10245 struct drm_property *dpms_property =
10246 dev->mode_config.dpms_property;
10247
10248 connector->dpms = DRM_MODE_DPMS_ON;
10249 drm_object_property_set_value(&connector->base,
10250 dpms_property,
10251 DRM_MODE_DPMS_ON);
10252
10253 intel_encoder = to_intel_encoder(connector->encoder);
10254 intel_encoder->connectors_active = true;
10255 }
10256 }
10257
10258 }
10259
10260 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10261 {
10262 int diff;
10263
10264 if (clock1 == clock2)
10265 return true;
10266
10267 if (!clock1 || !clock2)
10268 return false;
10269
10270 diff = abs(clock1 - clock2);
10271
10272 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10273 return true;
10274
10275 return false;
10276 }
10277
10278 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10279 list_for_each_entry((intel_crtc), \
10280 &(dev)->mode_config.crtc_list, \
10281 base.head) \
10282 if (mask & (1 <<(intel_crtc)->pipe))
10283
10284 static bool
10285 intel_pipe_config_compare(struct drm_device *dev,
10286 struct intel_crtc_config *current_config,
10287 struct intel_crtc_config *pipe_config)
10288 {
10289 #define PIPE_CONF_CHECK_X(name) \
10290 if (current_config->name != pipe_config->name) { \
10291 DRM_ERROR("mismatch in " #name " " \
10292 "(expected 0x%08x, found 0x%08x)\n", \
10293 current_config->name, \
10294 pipe_config->name); \
10295 return false; \
10296 }
10297
10298 #define PIPE_CONF_CHECK_I(name) \
10299 if (current_config->name != pipe_config->name) { \
10300 DRM_ERROR("mismatch in " #name " " \
10301 "(expected %i, found %i)\n", \
10302 current_config->name, \
10303 pipe_config->name); \
10304 return false; \
10305 }
10306
10307 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10308 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10309 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10310 "(expected %i, found %i)\n", \
10311 current_config->name & (mask), \
10312 pipe_config->name & (mask)); \
10313 return false; \
10314 }
10315
10316 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10317 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10318 DRM_ERROR("mismatch in " #name " " \
10319 "(expected %i, found %i)\n", \
10320 current_config->name, \
10321 pipe_config->name); \
10322 return false; \
10323 }
10324
10325 #define PIPE_CONF_QUIRK(quirk) \
10326 ((current_config->quirks | pipe_config->quirks) & (quirk))
10327
10328 PIPE_CONF_CHECK_I(cpu_transcoder);
10329
10330 PIPE_CONF_CHECK_I(has_pch_encoder);
10331 PIPE_CONF_CHECK_I(fdi_lanes);
10332 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10333 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10334 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10335 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10336 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10337
10338 PIPE_CONF_CHECK_I(has_dp_encoder);
10339 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10340 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10341 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10342 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10343 PIPE_CONF_CHECK_I(dp_m_n.tu);
10344
10345 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10346 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10347 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10348 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10349 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10350 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10351
10352 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10353 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10354 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10355 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10356 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10357 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10358
10359 PIPE_CONF_CHECK_I(pixel_multiplier);
10360 PIPE_CONF_CHECK_I(has_hdmi_sink);
10361 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10362 IS_VALLEYVIEW(dev))
10363 PIPE_CONF_CHECK_I(limited_color_range);
10364
10365 PIPE_CONF_CHECK_I(has_audio);
10366
10367 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10368 DRM_MODE_FLAG_INTERLACE);
10369
10370 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10371 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10372 DRM_MODE_FLAG_PHSYNC);
10373 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10374 DRM_MODE_FLAG_NHSYNC);
10375 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10376 DRM_MODE_FLAG_PVSYNC);
10377 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10378 DRM_MODE_FLAG_NVSYNC);
10379 }
10380
10381 PIPE_CONF_CHECK_I(pipe_src_w);
10382 PIPE_CONF_CHECK_I(pipe_src_h);
10383
10384 /*
10385 * FIXME: BIOS likes to set up a cloned config with lvds+external
10386 * screen. Since we don't yet re-compute the pipe config when moving
10387 * just the lvds port away to another pipe the sw tracking won't match.
10388 *
10389 * Proper atomic modesets with recomputed global state will fix this.
10390 * Until then just don't check gmch state for inherited modes.
10391 */
10392 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10393 PIPE_CONF_CHECK_I(gmch_pfit.control);
10394 /* pfit ratios are autocomputed by the hw on gen4+ */
10395 if (INTEL_INFO(dev)->gen < 4)
10396 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10397 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10398 }
10399
10400 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10401 if (current_config->pch_pfit.enabled) {
10402 PIPE_CONF_CHECK_I(pch_pfit.pos);
10403 PIPE_CONF_CHECK_I(pch_pfit.size);
10404 }
10405
10406 /* BDW+ don't expose a synchronous way to read the state */
10407 if (IS_HASWELL(dev))
10408 PIPE_CONF_CHECK_I(ips_enabled);
10409
10410 PIPE_CONF_CHECK_I(double_wide);
10411
10412 PIPE_CONF_CHECK_I(shared_dpll);
10413 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10414 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10415 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10416 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10417
10418 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10419 PIPE_CONF_CHECK_I(pipe_bpp);
10420
10421 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10422 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10423
10424 #undef PIPE_CONF_CHECK_X
10425 #undef PIPE_CONF_CHECK_I
10426 #undef PIPE_CONF_CHECK_FLAGS
10427 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10428 #undef PIPE_CONF_QUIRK
10429
10430 return true;
10431 }
10432
10433 static void
10434 check_connector_state(struct drm_device *dev)
10435 {
10436 struct intel_connector *connector;
10437
10438 list_for_each_entry(connector, &dev->mode_config.connector_list,
10439 base.head) {
10440 /* This also checks the encoder/connector hw state with the
10441 * ->get_hw_state callbacks. */
10442 intel_connector_check_state(connector);
10443
10444 WARN(&connector->new_encoder->base != connector->base.encoder,
10445 "connector's staged encoder doesn't match current encoder\n");
10446 }
10447 }
10448
10449 static void
10450 check_encoder_state(struct drm_device *dev)
10451 {
10452 struct intel_encoder *encoder;
10453 struct intel_connector *connector;
10454
10455 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10456 base.head) {
10457 bool enabled = false;
10458 bool active = false;
10459 enum pipe pipe, tracked_pipe;
10460
10461 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10462 encoder->base.base.id,
10463 encoder->base.name);
10464
10465 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10466 "encoder's stage crtc doesn't match current crtc\n");
10467 WARN(encoder->connectors_active && !encoder->base.crtc,
10468 "encoder's active_connectors set, but no crtc\n");
10469
10470 list_for_each_entry(connector, &dev->mode_config.connector_list,
10471 base.head) {
10472 if (connector->base.encoder != &encoder->base)
10473 continue;
10474 enabled = true;
10475 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10476 active = true;
10477 }
10478 WARN(!!encoder->base.crtc != enabled,
10479 "encoder's enabled state mismatch "
10480 "(expected %i, found %i)\n",
10481 !!encoder->base.crtc, enabled);
10482 WARN(active && !encoder->base.crtc,
10483 "active encoder with no crtc\n");
10484
10485 WARN(encoder->connectors_active != active,
10486 "encoder's computed active state doesn't match tracked active state "
10487 "(expected %i, found %i)\n", active, encoder->connectors_active);
10488
10489 active = encoder->get_hw_state(encoder, &pipe);
10490 WARN(active != encoder->connectors_active,
10491 "encoder's hw state doesn't match sw tracking "
10492 "(expected %i, found %i)\n",
10493 encoder->connectors_active, active);
10494
10495 if (!encoder->base.crtc)
10496 continue;
10497
10498 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10499 WARN(active && pipe != tracked_pipe,
10500 "active encoder's pipe doesn't match"
10501 "(expected %i, found %i)\n",
10502 tracked_pipe, pipe);
10503
10504 }
10505 }
10506
10507 static void
10508 check_crtc_state(struct drm_device *dev)
10509 {
10510 struct drm_i915_private *dev_priv = dev->dev_private;
10511 struct intel_crtc *crtc;
10512 struct intel_encoder *encoder;
10513 struct intel_crtc_config pipe_config;
10514
10515 for_each_intel_crtc(dev, crtc) {
10516 bool enabled = false;
10517 bool active = false;
10518
10519 memset(&pipe_config, 0, sizeof(pipe_config));
10520
10521 DRM_DEBUG_KMS("[CRTC:%d]\n",
10522 crtc->base.base.id);
10523
10524 WARN(crtc->active && !crtc->base.enabled,
10525 "active crtc, but not enabled in sw tracking\n");
10526
10527 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10528 base.head) {
10529 if (encoder->base.crtc != &crtc->base)
10530 continue;
10531 enabled = true;
10532 if (encoder->connectors_active)
10533 active = true;
10534 }
10535
10536 WARN(active != crtc->active,
10537 "crtc's computed active state doesn't match tracked active state "
10538 "(expected %i, found %i)\n", active, crtc->active);
10539 WARN(enabled != crtc->base.enabled,
10540 "crtc's computed enabled state doesn't match tracked enabled state "
10541 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10542
10543 active = dev_priv->display.get_pipe_config(crtc,
10544 &pipe_config);
10545
10546 /* hw state is inconsistent with the pipe A quirk */
10547 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
10548 active = crtc->active;
10549
10550 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10551 base.head) {
10552 enum pipe pipe;
10553 if (encoder->base.crtc != &crtc->base)
10554 continue;
10555 if (encoder->get_hw_state(encoder, &pipe))
10556 encoder->get_config(encoder, &pipe_config);
10557 }
10558
10559 WARN(crtc->active != active,
10560 "crtc active state doesn't match with hw state "
10561 "(expected %i, found %i)\n", crtc->active, active);
10562
10563 if (active &&
10564 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10565 WARN(1, "pipe state doesn't match!\n");
10566 intel_dump_pipe_config(crtc, &pipe_config,
10567 "[hw state]");
10568 intel_dump_pipe_config(crtc, &crtc->config,
10569 "[sw state]");
10570 }
10571 }
10572 }
10573
10574 static void
10575 check_shared_dpll_state(struct drm_device *dev)
10576 {
10577 struct drm_i915_private *dev_priv = dev->dev_private;
10578 struct intel_crtc *crtc;
10579 struct intel_dpll_hw_state dpll_hw_state;
10580 int i;
10581
10582 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10583 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10584 int enabled_crtcs = 0, active_crtcs = 0;
10585 bool active;
10586
10587 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10588
10589 DRM_DEBUG_KMS("%s\n", pll->name);
10590
10591 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10592
10593 WARN(pll->active > pll->refcount,
10594 "more active pll users than references: %i vs %i\n",
10595 pll->active, pll->refcount);
10596 WARN(pll->active && !pll->on,
10597 "pll in active use but not on in sw tracking\n");
10598 WARN(pll->on && !pll->active,
10599 "pll in on but not on in use in sw tracking\n");
10600 WARN(pll->on != active,
10601 "pll on state mismatch (expected %i, found %i)\n",
10602 pll->on, active);
10603
10604 for_each_intel_crtc(dev, crtc) {
10605 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10606 enabled_crtcs++;
10607 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10608 active_crtcs++;
10609 }
10610 WARN(pll->active != active_crtcs,
10611 "pll active crtcs mismatch (expected %i, found %i)\n",
10612 pll->active, active_crtcs);
10613 WARN(pll->refcount != enabled_crtcs,
10614 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10615 pll->refcount, enabled_crtcs);
10616
10617 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10618 sizeof(dpll_hw_state)),
10619 "pll hw state mismatch\n");
10620 }
10621 }
10622
10623 void
10624 intel_modeset_check_state(struct drm_device *dev)
10625 {
10626 check_connector_state(dev);
10627 check_encoder_state(dev);
10628 check_crtc_state(dev);
10629 check_shared_dpll_state(dev);
10630 }
10631
10632 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10633 int dotclock)
10634 {
10635 /*
10636 * FDI already provided one idea for the dotclock.
10637 * Yell if the encoder disagrees.
10638 */
10639 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10640 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10641 pipe_config->adjusted_mode.crtc_clock, dotclock);
10642 }
10643
10644 static void update_scanline_offset(struct intel_crtc *crtc)
10645 {
10646 struct drm_device *dev = crtc->base.dev;
10647
10648 /*
10649 * The scanline counter increments at the leading edge of hsync.
10650 *
10651 * On most platforms it starts counting from vtotal-1 on the
10652 * first active line. That means the scanline counter value is
10653 * always one less than what we would expect. Ie. just after
10654 * start of vblank, which also occurs at start of hsync (on the
10655 * last active line), the scanline counter will read vblank_start-1.
10656 *
10657 * On gen2 the scanline counter starts counting from 1 instead
10658 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10659 * to keep the value positive), instead of adding one.
10660 *
10661 * On HSW+ the behaviour of the scanline counter depends on the output
10662 * type. For DP ports it behaves like most other platforms, but on HDMI
10663 * there's an extra 1 line difference. So we need to add two instead of
10664 * one to the value.
10665 */
10666 if (IS_GEN2(dev)) {
10667 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10668 int vtotal;
10669
10670 vtotal = mode->crtc_vtotal;
10671 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10672 vtotal /= 2;
10673
10674 crtc->scanline_offset = vtotal - 1;
10675 } else if (HAS_DDI(dev) &&
10676 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
10677 crtc->scanline_offset = 2;
10678 } else
10679 crtc->scanline_offset = 1;
10680 }
10681
10682 static int __intel_set_mode(struct drm_crtc *crtc,
10683 struct drm_display_mode *mode,
10684 int x, int y, struct drm_framebuffer *fb)
10685 {
10686 struct drm_device *dev = crtc->dev;
10687 struct drm_i915_private *dev_priv = dev->dev_private;
10688 struct drm_display_mode *saved_mode;
10689 struct intel_crtc_config *pipe_config = NULL;
10690 struct intel_crtc *intel_crtc;
10691 unsigned disable_pipes, prepare_pipes, modeset_pipes;
10692 int ret = 0;
10693
10694 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10695 if (!saved_mode)
10696 return -ENOMEM;
10697
10698 intel_modeset_affected_pipes(crtc, &modeset_pipes,
10699 &prepare_pipes, &disable_pipes);
10700
10701 *saved_mode = crtc->mode;
10702
10703 /* Hack: Because we don't (yet) support global modeset on multiple
10704 * crtcs, we don't keep track of the new mode for more than one crtc.
10705 * Hence simply check whether any bit is set in modeset_pipes in all the
10706 * pieces of code that are not yet converted to deal with mutliple crtcs
10707 * changing their mode at the same time. */
10708 if (modeset_pipes) {
10709 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10710 if (IS_ERR(pipe_config)) {
10711 ret = PTR_ERR(pipe_config);
10712 pipe_config = NULL;
10713
10714 goto out;
10715 }
10716 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10717 "[modeset]");
10718 to_intel_crtc(crtc)->new_config = pipe_config;
10719 }
10720
10721 /*
10722 * See if the config requires any additional preparation, e.g.
10723 * to adjust global state with pipes off. We need to do this
10724 * here so we can get the modeset_pipe updated config for the new
10725 * mode set on this crtc. For other crtcs we need to use the
10726 * adjusted_mode bits in the crtc directly.
10727 */
10728 if (IS_VALLEYVIEW(dev)) {
10729 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10730
10731 /* may have added more to prepare_pipes than we should */
10732 prepare_pipes &= ~disable_pipes;
10733 }
10734
10735 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10736 intel_crtc_disable(&intel_crtc->base);
10737
10738 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10739 if (intel_crtc->base.enabled)
10740 dev_priv->display.crtc_disable(&intel_crtc->base);
10741 }
10742
10743 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10744 * to set it here already despite that we pass it down the callchain.
10745 */
10746 if (modeset_pipes) {
10747 crtc->mode = *mode;
10748 /* mode_set/enable/disable functions rely on a correct pipe
10749 * config. */
10750 to_intel_crtc(crtc)->config = *pipe_config;
10751 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10752
10753 /*
10754 * Calculate and store various constants which
10755 * are later needed by vblank and swap-completion
10756 * timestamping. They are derived from true hwmode.
10757 */
10758 drm_calc_timestamping_constants(crtc,
10759 &pipe_config->adjusted_mode);
10760 }
10761
10762 /* Only after disabling all output pipelines that will be changed can we
10763 * update the the output configuration. */
10764 intel_modeset_update_state(dev, prepare_pipes);
10765
10766 if (dev_priv->display.modeset_global_resources)
10767 dev_priv->display.modeset_global_resources(dev);
10768
10769 /* Set up the DPLL and any encoders state that needs to adjust or depend
10770 * on the DPLL.
10771 */
10772 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10773 struct drm_framebuffer *old_fb = crtc->primary->fb;
10774 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
10775 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10776
10777 mutex_lock(&dev->struct_mutex);
10778 ret = intel_pin_and_fence_fb_obj(dev,
10779 obj,
10780 NULL);
10781 if (ret != 0) {
10782 DRM_ERROR("pin & fence failed\n");
10783 mutex_unlock(&dev->struct_mutex);
10784 goto done;
10785 }
10786 if (old_fb)
10787 intel_unpin_fb_obj(old_obj);
10788 i915_gem_track_fb(old_obj, obj,
10789 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
10790 mutex_unlock(&dev->struct_mutex);
10791
10792 crtc->primary->fb = fb;
10793 crtc->x = x;
10794 crtc->y = y;
10795
10796 ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
10797 x, y, fb);
10798 if (ret)
10799 goto done;
10800 }
10801
10802 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10803 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10804 update_scanline_offset(intel_crtc);
10805
10806 dev_priv->display.crtc_enable(&intel_crtc->base);
10807 }
10808
10809 /* FIXME: add subpixel order */
10810 done:
10811 if (ret && crtc->enabled)
10812 crtc->mode = *saved_mode;
10813
10814 out:
10815 kfree(pipe_config);
10816 kfree(saved_mode);
10817 return ret;
10818 }
10819
10820 static int intel_set_mode(struct drm_crtc *crtc,
10821 struct drm_display_mode *mode,
10822 int x, int y, struct drm_framebuffer *fb)
10823 {
10824 int ret;
10825
10826 ret = __intel_set_mode(crtc, mode, x, y, fb);
10827
10828 if (ret == 0)
10829 intel_modeset_check_state(crtc->dev);
10830
10831 return ret;
10832 }
10833
10834 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10835 {
10836 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10837 }
10838
10839 #undef for_each_intel_crtc_masked
10840
10841 static void intel_set_config_free(struct intel_set_config *config)
10842 {
10843 if (!config)
10844 return;
10845
10846 kfree(config->save_connector_encoders);
10847 kfree(config->save_encoder_crtcs);
10848 kfree(config->save_crtc_enabled);
10849 kfree(config);
10850 }
10851
10852 static int intel_set_config_save_state(struct drm_device *dev,
10853 struct intel_set_config *config)
10854 {
10855 struct drm_crtc *crtc;
10856 struct drm_encoder *encoder;
10857 struct drm_connector *connector;
10858 int count;
10859
10860 config->save_crtc_enabled =
10861 kcalloc(dev->mode_config.num_crtc,
10862 sizeof(bool), GFP_KERNEL);
10863 if (!config->save_crtc_enabled)
10864 return -ENOMEM;
10865
10866 config->save_encoder_crtcs =
10867 kcalloc(dev->mode_config.num_encoder,
10868 sizeof(struct drm_crtc *), GFP_KERNEL);
10869 if (!config->save_encoder_crtcs)
10870 return -ENOMEM;
10871
10872 config->save_connector_encoders =
10873 kcalloc(dev->mode_config.num_connector,
10874 sizeof(struct drm_encoder *), GFP_KERNEL);
10875 if (!config->save_connector_encoders)
10876 return -ENOMEM;
10877
10878 /* Copy data. Note that driver private data is not affected.
10879 * Should anything bad happen only the expected state is
10880 * restored, not the drivers personal bookkeeping.
10881 */
10882 count = 0;
10883 for_each_crtc(dev, crtc) {
10884 config->save_crtc_enabled[count++] = crtc->enabled;
10885 }
10886
10887 count = 0;
10888 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10889 config->save_encoder_crtcs[count++] = encoder->crtc;
10890 }
10891
10892 count = 0;
10893 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10894 config->save_connector_encoders[count++] = connector->encoder;
10895 }
10896
10897 return 0;
10898 }
10899
10900 static void intel_set_config_restore_state(struct drm_device *dev,
10901 struct intel_set_config *config)
10902 {
10903 struct intel_crtc *crtc;
10904 struct intel_encoder *encoder;
10905 struct intel_connector *connector;
10906 int count;
10907
10908 count = 0;
10909 for_each_intel_crtc(dev, crtc) {
10910 crtc->new_enabled = config->save_crtc_enabled[count++];
10911
10912 if (crtc->new_enabled)
10913 crtc->new_config = &crtc->config;
10914 else
10915 crtc->new_config = NULL;
10916 }
10917
10918 count = 0;
10919 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10920 encoder->new_crtc =
10921 to_intel_crtc(config->save_encoder_crtcs[count++]);
10922 }
10923
10924 count = 0;
10925 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10926 connector->new_encoder =
10927 to_intel_encoder(config->save_connector_encoders[count++]);
10928 }
10929 }
10930
10931 static bool
10932 is_crtc_connector_off(struct drm_mode_set *set)
10933 {
10934 int i;
10935
10936 if (set->num_connectors == 0)
10937 return false;
10938
10939 if (WARN_ON(set->connectors == NULL))
10940 return false;
10941
10942 for (i = 0; i < set->num_connectors; i++)
10943 if (set->connectors[i]->encoder &&
10944 set->connectors[i]->encoder->crtc == set->crtc &&
10945 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
10946 return true;
10947
10948 return false;
10949 }
10950
10951 static void
10952 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
10953 struct intel_set_config *config)
10954 {
10955
10956 /* We should be able to check here if the fb has the same properties
10957 * and then just flip_or_move it */
10958 if (is_crtc_connector_off(set)) {
10959 config->mode_changed = true;
10960 } else if (set->crtc->primary->fb != set->fb) {
10961 /*
10962 * If we have no fb, we can only flip as long as the crtc is
10963 * active, otherwise we need a full mode set. The crtc may
10964 * be active if we've only disabled the primary plane, or
10965 * in fastboot situations.
10966 */
10967 if (set->crtc->primary->fb == NULL) {
10968 struct intel_crtc *intel_crtc =
10969 to_intel_crtc(set->crtc);
10970
10971 if (intel_crtc->active) {
10972 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
10973 config->fb_changed = true;
10974 } else {
10975 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
10976 config->mode_changed = true;
10977 }
10978 } else if (set->fb == NULL) {
10979 config->mode_changed = true;
10980 } else if (set->fb->pixel_format !=
10981 set->crtc->primary->fb->pixel_format) {
10982 config->mode_changed = true;
10983 } else {
10984 config->fb_changed = true;
10985 }
10986 }
10987
10988 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
10989 config->fb_changed = true;
10990
10991 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
10992 DRM_DEBUG_KMS("modes are different, full mode set\n");
10993 drm_mode_debug_printmodeline(&set->crtc->mode);
10994 drm_mode_debug_printmodeline(set->mode);
10995 config->mode_changed = true;
10996 }
10997
10998 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
10999 set->crtc->base.id, config->mode_changed, config->fb_changed);
11000 }
11001
11002 static int
11003 intel_modeset_stage_output_state(struct drm_device *dev,
11004 struct drm_mode_set *set,
11005 struct intel_set_config *config)
11006 {
11007 struct intel_connector *connector;
11008 struct intel_encoder *encoder;
11009 struct intel_crtc *crtc;
11010 int ro;
11011
11012 /* The upper layers ensure that we either disable a crtc or have a list
11013 * of connectors. For paranoia, double-check this. */
11014 WARN_ON(!set->fb && (set->num_connectors != 0));
11015 WARN_ON(set->fb && (set->num_connectors == 0));
11016
11017 list_for_each_entry(connector, &dev->mode_config.connector_list,
11018 base.head) {
11019 /* Otherwise traverse passed in connector list and get encoders
11020 * for them. */
11021 for (ro = 0; ro < set->num_connectors; ro++) {
11022 if (set->connectors[ro] == &connector->base) {
11023 connector->new_encoder = connector->encoder;
11024 break;
11025 }
11026 }
11027
11028 /* If we disable the crtc, disable all its connectors. Also, if
11029 * the connector is on the changing crtc but not on the new
11030 * connector list, disable it. */
11031 if ((!set->fb || ro == set->num_connectors) &&
11032 connector->base.encoder &&
11033 connector->base.encoder->crtc == set->crtc) {
11034 connector->new_encoder = NULL;
11035
11036 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11037 connector->base.base.id,
11038 connector->base.name);
11039 }
11040
11041
11042 if (&connector->new_encoder->base != connector->base.encoder) {
11043 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11044 config->mode_changed = true;
11045 }
11046 }
11047 /* connector->new_encoder is now updated for all connectors. */
11048
11049 /* Update crtc of enabled connectors. */
11050 list_for_each_entry(connector, &dev->mode_config.connector_list,
11051 base.head) {
11052 struct drm_crtc *new_crtc;
11053
11054 if (!connector->new_encoder)
11055 continue;
11056
11057 new_crtc = connector->new_encoder->base.crtc;
11058
11059 for (ro = 0; ro < set->num_connectors; ro++) {
11060 if (set->connectors[ro] == &connector->base)
11061 new_crtc = set->crtc;
11062 }
11063
11064 /* Make sure the new CRTC will work with the encoder */
11065 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11066 new_crtc)) {
11067 return -EINVAL;
11068 }
11069 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
11070
11071 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11072 connector->base.base.id,
11073 connector->base.name,
11074 new_crtc->base.id);
11075 }
11076
11077 /* Check for any encoders that needs to be disabled. */
11078 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11079 base.head) {
11080 int num_connectors = 0;
11081 list_for_each_entry(connector,
11082 &dev->mode_config.connector_list,
11083 base.head) {
11084 if (connector->new_encoder == encoder) {
11085 WARN_ON(!connector->new_encoder->new_crtc);
11086 num_connectors++;
11087 }
11088 }
11089
11090 if (num_connectors == 0)
11091 encoder->new_crtc = NULL;
11092 else if (num_connectors > 1)
11093 return -EINVAL;
11094
11095 /* Only now check for crtc changes so we don't miss encoders
11096 * that will be disabled. */
11097 if (&encoder->new_crtc->base != encoder->base.crtc) {
11098 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11099 config->mode_changed = true;
11100 }
11101 }
11102 /* Now we've also updated encoder->new_crtc for all encoders. */
11103
11104 for_each_intel_crtc(dev, crtc) {
11105 crtc->new_enabled = false;
11106
11107 list_for_each_entry(encoder,
11108 &dev->mode_config.encoder_list,
11109 base.head) {
11110 if (encoder->new_crtc == crtc) {
11111 crtc->new_enabled = true;
11112 break;
11113 }
11114 }
11115
11116 if (crtc->new_enabled != crtc->base.enabled) {
11117 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11118 crtc->new_enabled ? "en" : "dis");
11119 config->mode_changed = true;
11120 }
11121
11122 if (crtc->new_enabled)
11123 crtc->new_config = &crtc->config;
11124 else
11125 crtc->new_config = NULL;
11126 }
11127
11128 return 0;
11129 }
11130
11131 static void disable_crtc_nofb(struct intel_crtc *crtc)
11132 {
11133 struct drm_device *dev = crtc->base.dev;
11134 struct intel_encoder *encoder;
11135 struct intel_connector *connector;
11136
11137 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11138 pipe_name(crtc->pipe));
11139
11140 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11141 if (connector->new_encoder &&
11142 connector->new_encoder->new_crtc == crtc)
11143 connector->new_encoder = NULL;
11144 }
11145
11146 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
11147 if (encoder->new_crtc == crtc)
11148 encoder->new_crtc = NULL;
11149 }
11150
11151 crtc->new_enabled = false;
11152 crtc->new_config = NULL;
11153 }
11154
11155 static int intel_crtc_set_config(struct drm_mode_set *set)
11156 {
11157 struct drm_device *dev;
11158 struct drm_mode_set save_set;
11159 struct intel_set_config *config;
11160 int ret;
11161
11162 BUG_ON(!set);
11163 BUG_ON(!set->crtc);
11164 BUG_ON(!set->crtc->helper_private);
11165
11166 /* Enforce sane interface api - has been abused by the fb helper. */
11167 BUG_ON(!set->mode && set->fb);
11168 BUG_ON(set->fb && set->num_connectors == 0);
11169
11170 if (set->fb) {
11171 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11172 set->crtc->base.id, set->fb->base.id,
11173 (int)set->num_connectors, set->x, set->y);
11174 } else {
11175 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11176 }
11177
11178 dev = set->crtc->dev;
11179
11180 ret = -ENOMEM;
11181 config = kzalloc(sizeof(*config), GFP_KERNEL);
11182 if (!config)
11183 goto out_config;
11184
11185 ret = intel_set_config_save_state(dev, config);
11186 if (ret)
11187 goto out_config;
11188
11189 save_set.crtc = set->crtc;
11190 save_set.mode = &set->crtc->mode;
11191 save_set.x = set->crtc->x;
11192 save_set.y = set->crtc->y;
11193 save_set.fb = set->crtc->primary->fb;
11194
11195 /* Compute whether we need a full modeset, only an fb base update or no
11196 * change at all. In the future we might also check whether only the
11197 * mode changed, e.g. for LVDS where we only change the panel fitter in
11198 * such cases. */
11199 intel_set_config_compute_mode_changes(set, config);
11200
11201 ret = intel_modeset_stage_output_state(dev, set, config);
11202 if (ret)
11203 goto fail;
11204
11205 if (config->mode_changed) {
11206 ret = intel_set_mode(set->crtc, set->mode,
11207 set->x, set->y, set->fb);
11208 } else if (config->fb_changed) {
11209 struct drm_i915_private *dev_priv = dev->dev_private;
11210 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11211
11212 intel_crtc_wait_for_pending_flips(set->crtc);
11213
11214 ret = intel_pipe_set_base(set->crtc,
11215 set->x, set->y, set->fb);
11216
11217 /*
11218 * We need to make sure the primary plane is re-enabled if it
11219 * has previously been turned off.
11220 */
11221 if (!intel_crtc->primary_enabled && ret == 0) {
11222 WARN_ON(!intel_crtc->active);
11223 intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane,
11224 intel_crtc->pipe);
11225 }
11226
11227 /*
11228 * In the fastboot case this may be our only check of the
11229 * state after boot. It would be better to only do it on
11230 * the first update, but we don't have a nice way of doing that
11231 * (and really, set_config isn't used much for high freq page
11232 * flipping, so increasing its cost here shouldn't be a big
11233 * deal).
11234 */
11235 if (i915.fastboot && ret == 0)
11236 intel_modeset_check_state(set->crtc->dev);
11237 }
11238
11239 if (ret) {
11240 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11241 set->crtc->base.id, ret);
11242 fail:
11243 intel_set_config_restore_state(dev, config);
11244
11245 /*
11246 * HACK: if the pipe was on, but we didn't have a framebuffer,
11247 * force the pipe off to avoid oopsing in the modeset code
11248 * due to fb==NULL. This should only happen during boot since
11249 * we don't yet reconstruct the FB from the hardware state.
11250 */
11251 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11252 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11253
11254 /* Try to restore the config */
11255 if (config->mode_changed &&
11256 intel_set_mode(save_set.crtc, save_set.mode,
11257 save_set.x, save_set.y, save_set.fb))
11258 DRM_ERROR("failed to restore config after modeset failure\n");
11259 }
11260
11261 out_config:
11262 intel_set_config_free(config);
11263 return ret;
11264 }
11265
11266 static const struct drm_crtc_funcs intel_crtc_funcs = {
11267 .gamma_set = intel_crtc_gamma_set,
11268 .set_config = intel_crtc_set_config,
11269 .destroy = intel_crtc_destroy,
11270 .page_flip = intel_crtc_page_flip,
11271 };
11272
11273 static void intel_cpu_pll_init(struct drm_device *dev)
11274 {
11275 if (HAS_DDI(dev))
11276 intel_ddi_pll_init(dev);
11277 }
11278
11279 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11280 struct intel_shared_dpll *pll,
11281 struct intel_dpll_hw_state *hw_state)
11282 {
11283 uint32_t val;
11284
11285 val = I915_READ(PCH_DPLL(pll->id));
11286 hw_state->dpll = val;
11287 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11288 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11289
11290 return val & DPLL_VCO_ENABLE;
11291 }
11292
11293 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11294 struct intel_shared_dpll *pll)
11295 {
11296 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
11297 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
11298 }
11299
11300 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11301 struct intel_shared_dpll *pll)
11302 {
11303 /* PCH refclock must be enabled first */
11304 ibx_assert_pch_refclk_enabled(dev_priv);
11305
11306 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11307
11308 /* Wait for the clocks to stabilize. */
11309 POSTING_READ(PCH_DPLL(pll->id));
11310 udelay(150);
11311
11312 /* The pixel multiplier can only be updated once the
11313 * DPLL is enabled and the clocks are stable.
11314 *
11315 * So write it again.
11316 */
11317 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11318 POSTING_READ(PCH_DPLL(pll->id));
11319 udelay(200);
11320 }
11321
11322 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11323 struct intel_shared_dpll *pll)
11324 {
11325 struct drm_device *dev = dev_priv->dev;
11326 struct intel_crtc *crtc;
11327
11328 /* Make sure no transcoder isn't still depending on us. */
11329 for_each_intel_crtc(dev, crtc) {
11330 if (intel_crtc_to_shared_dpll(crtc) == pll)
11331 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11332 }
11333
11334 I915_WRITE(PCH_DPLL(pll->id), 0);
11335 POSTING_READ(PCH_DPLL(pll->id));
11336 udelay(200);
11337 }
11338
11339 static char *ibx_pch_dpll_names[] = {
11340 "PCH DPLL A",
11341 "PCH DPLL B",
11342 };
11343
11344 static void ibx_pch_dpll_init(struct drm_device *dev)
11345 {
11346 struct drm_i915_private *dev_priv = dev->dev_private;
11347 int i;
11348
11349 dev_priv->num_shared_dpll = 2;
11350
11351 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11352 dev_priv->shared_dplls[i].id = i;
11353 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11354 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11355 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11356 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11357 dev_priv->shared_dplls[i].get_hw_state =
11358 ibx_pch_dpll_get_hw_state;
11359 }
11360 }
11361
11362 static void intel_shared_dpll_init(struct drm_device *dev)
11363 {
11364 struct drm_i915_private *dev_priv = dev->dev_private;
11365
11366 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11367 ibx_pch_dpll_init(dev);
11368 else
11369 dev_priv->num_shared_dpll = 0;
11370
11371 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11372 }
11373
11374 static int
11375 intel_primary_plane_disable(struct drm_plane *plane)
11376 {
11377 struct drm_device *dev = plane->dev;
11378 struct drm_i915_private *dev_priv = dev->dev_private;
11379 struct intel_plane *intel_plane = to_intel_plane(plane);
11380 struct intel_crtc *intel_crtc;
11381
11382 if (!plane->fb)
11383 return 0;
11384
11385 BUG_ON(!plane->crtc);
11386
11387 intel_crtc = to_intel_crtc(plane->crtc);
11388
11389 /*
11390 * Even though we checked plane->fb above, it's still possible that
11391 * the primary plane has been implicitly disabled because the crtc
11392 * coordinates given weren't visible, or because we detected
11393 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11394 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11395 * In either case, we need to unpin the FB and let the fb pointer get
11396 * updated, but otherwise we don't need to touch the hardware.
11397 */
11398 if (!intel_crtc->primary_enabled)
11399 goto disable_unpin;
11400
11401 intel_crtc_wait_for_pending_flips(plane->crtc);
11402 intel_disable_primary_hw_plane(dev_priv, intel_plane->plane,
11403 intel_plane->pipe);
11404 disable_unpin:
11405 mutex_lock(&dev->struct_mutex);
11406 i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
11407 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11408 intel_unpin_fb_obj(intel_fb_obj(plane->fb));
11409 mutex_unlock(&dev->struct_mutex);
11410 plane->fb = NULL;
11411
11412 return 0;
11413 }
11414
11415 static int
11416 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11417 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11418 unsigned int crtc_w, unsigned int crtc_h,
11419 uint32_t src_x, uint32_t src_y,
11420 uint32_t src_w, uint32_t src_h)
11421 {
11422 struct drm_device *dev = crtc->dev;
11423 struct drm_i915_private *dev_priv = dev->dev_private;
11424 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11425 struct intel_plane *intel_plane = to_intel_plane(plane);
11426 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11427 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11428 struct drm_rect dest = {
11429 /* integer pixels */
11430 .x1 = crtc_x,
11431 .y1 = crtc_y,
11432 .x2 = crtc_x + crtc_w,
11433 .y2 = crtc_y + crtc_h,
11434 };
11435 struct drm_rect src = {
11436 /* 16.16 fixed point */
11437 .x1 = src_x,
11438 .y1 = src_y,
11439 .x2 = src_x + src_w,
11440 .y2 = src_y + src_h,
11441 };
11442 const struct drm_rect clip = {
11443 /* integer pixels */
11444 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
11445 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
11446 };
11447 bool visible;
11448 int ret;
11449
11450 ret = drm_plane_helper_check_update(plane, crtc, fb,
11451 &src, &dest, &clip,
11452 DRM_PLANE_HELPER_NO_SCALING,
11453 DRM_PLANE_HELPER_NO_SCALING,
11454 false, true, &visible);
11455
11456 if (ret)
11457 return ret;
11458
11459 /*
11460 * If the CRTC isn't enabled, we're just pinning the framebuffer,
11461 * updating the fb pointer, and returning without touching the
11462 * hardware. This allows us to later do a drmModeSetCrtc with fb=-1 to
11463 * turn on the display with all planes setup as desired.
11464 */
11465 if (!crtc->enabled) {
11466 mutex_lock(&dev->struct_mutex);
11467
11468 /*
11469 * If we already called setplane while the crtc was disabled,
11470 * we may have an fb pinned; unpin it.
11471 */
11472 if (plane->fb)
11473 intel_unpin_fb_obj(old_obj);
11474
11475 i915_gem_track_fb(old_obj, obj,
11476 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11477
11478 /* Pin and return without programming hardware */
11479 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11480 mutex_unlock(&dev->struct_mutex);
11481
11482 return ret;
11483 }
11484
11485 intel_crtc_wait_for_pending_flips(crtc);
11486
11487 /*
11488 * If clipping results in a non-visible primary plane, we'll disable
11489 * the primary plane. Note that this is a bit different than what
11490 * happens if userspace explicitly disables the plane by passing fb=0
11491 * because plane->fb still gets set and pinned.
11492 */
11493 if (!visible) {
11494 mutex_lock(&dev->struct_mutex);
11495
11496 /*
11497 * Try to pin the new fb first so that we can bail out if we
11498 * fail.
11499 */
11500 if (plane->fb != fb) {
11501 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11502 if (ret) {
11503 mutex_unlock(&dev->struct_mutex);
11504 return ret;
11505 }
11506 }
11507
11508 i915_gem_track_fb(old_obj, obj,
11509 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11510
11511 if (intel_crtc->primary_enabled)
11512 intel_disable_primary_hw_plane(dev_priv,
11513 intel_plane->plane,
11514 intel_plane->pipe);
11515
11516
11517 if (plane->fb != fb)
11518 if (plane->fb)
11519 intel_unpin_fb_obj(old_obj);
11520
11521 mutex_unlock(&dev->struct_mutex);
11522
11523 return 0;
11524 }
11525
11526 ret = intel_pipe_set_base(crtc, src.x1, src.y1, fb);
11527 if (ret)
11528 return ret;
11529
11530 if (!intel_crtc->primary_enabled)
11531 intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane,
11532 intel_crtc->pipe);
11533
11534 return 0;
11535 }
11536
11537 /* Common destruction function for both primary and cursor planes */
11538 static void intel_plane_destroy(struct drm_plane *plane)
11539 {
11540 struct intel_plane *intel_plane = to_intel_plane(plane);
11541 drm_plane_cleanup(plane);
11542 kfree(intel_plane);
11543 }
11544
11545 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11546 .update_plane = intel_primary_plane_setplane,
11547 .disable_plane = intel_primary_plane_disable,
11548 .destroy = intel_plane_destroy,
11549 };
11550
11551 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11552 int pipe)
11553 {
11554 struct intel_plane *primary;
11555 const uint32_t *intel_primary_formats;
11556 int num_formats;
11557
11558 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11559 if (primary == NULL)
11560 return NULL;
11561
11562 primary->can_scale = false;
11563 primary->max_downscale = 1;
11564 primary->pipe = pipe;
11565 primary->plane = pipe;
11566 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11567 primary->plane = !pipe;
11568
11569 if (INTEL_INFO(dev)->gen <= 3) {
11570 intel_primary_formats = intel_primary_formats_gen2;
11571 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11572 } else {
11573 intel_primary_formats = intel_primary_formats_gen4;
11574 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11575 }
11576
11577 drm_universal_plane_init(dev, &primary->base, 0,
11578 &intel_primary_plane_funcs,
11579 intel_primary_formats, num_formats,
11580 DRM_PLANE_TYPE_PRIMARY);
11581 return &primary->base;
11582 }
11583
11584 static int
11585 intel_cursor_plane_disable(struct drm_plane *plane)
11586 {
11587 if (!plane->fb)
11588 return 0;
11589
11590 BUG_ON(!plane->crtc);
11591
11592 return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
11593 }
11594
11595 static int
11596 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
11597 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11598 unsigned int crtc_w, unsigned int crtc_h,
11599 uint32_t src_x, uint32_t src_y,
11600 uint32_t src_w, uint32_t src_h)
11601 {
11602 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11603 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11604 struct drm_i915_gem_object *obj = intel_fb->obj;
11605 struct drm_rect dest = {
11606 /* integer pixels */
11607 .x1 = crtc_x,
11608 .y1 = crtc_y,
11609 .x2 = crtc_x + crtc_w,
11610 .y2 = crtc_y + crtc_h,
11611 };
11612 struct drm_rect src = {
11613 /* 16.16 fixed point */
11614 .x1 = src_x,
11615 .y1 = src_y,
11616 .x2 = src_x + src_w,
11617 .y2 = src_y + src_h,
11618 };
11619 const struct drm_rect clip = {
11620 /* integer pixels */
11621 .x2 = intel_crtc->config.pipe_src_w,
11622 .y2 = intel_crtc->config.pipe_src_h,
11623 };
11624 bool visible;
11625 int ret;
11626
11627 ret = drm_plane_helper_check_update(plane, crtc, fb,
11628 &src, &dest, &clip,
11629 DRM_PLANE_HELPER_NO_SCALING,
11630 DRM_PLANE_HELPER_NO_SCALING,
11631 true, true, &visible);
11632 if (ret)
11633 return ret;
11634
11635 crtc->cursor_x = crtc_x;
11636 crtc->cursor_y = crtc_y;
11637 if (fb != crtc->cursor->fb) {
11638 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
11639 } else {
11640 intel_crtc_update_cursor(crtc, visible);
11641 return 0;
11642 }
11643 }
11644 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
11645 .update_plane = intel_cursor_plane_update,
11646 .disable_plane = intel_cursor_plane_disable,
11647 .destroy = intel_plane_destroy,
11648 };
11649
11650 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
11651 int pipe)
11652 {
11653 struct intel_plane *cursor;
11654
11655 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
11656 if (cursor == NULL)
11657 return NULL;
11658
11659 cursor->can_scale = false;
11660 cursor->max_downscale = 1;
11661 cursor->pipe = pipe;
11662 cursor->plane = pipe;
11663
11664 drm_universal_plane_init(dev, &cursor->base, 0,
11665 &intel_cursor_plane_funcs,
11666 intel_cursor_formats,
11667 ARRAY_SIZE(intel_cursor_formats),
11668 DRM_PLANE_TYPE_CURSOR);
11669 return &cursor->base;
11670 }
11671
11672 static void intel_crtc_init(struct drm_device *dev, int pipe)
11673 {
11674 struct drm_i915_private *dev_priv = dev->dev_private;
11675 struct intel_crtc *intel_crtc;
11676 struct drm_plane *primary = NULL;
11677 struct drm_plane *cursor = NULL;
11678 int i, ret;
11679
11680 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
11681 if (intel_crtc == NULL)
11682 return;
11683
11684 primary = intel_primary_plane_create(dev, pipe);
11685 if (!primary)
11686 goto fail;
11687
11688 cursor = intel_cursor_plane_create(dev, pipe);
11689 if (!cursor)
11690 goto fail;
11691
11692 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
11693 cursor, &intel_crtc_funcs);
11694 if (ret)
11695 goto fail;
11696
11697 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
11698 for (i = 0; i < 256; i++) {
11699 intel_crtc->lut_r[i] = i;
11700 intel_crtc->lut_g[i] = i;
11701 intel_crtc->lut_b[i] = i;
11702 }
11703
11704 /*
11705 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
11706 * is hooked to pipe B. Hence we want plane A feeding pipe B.
11707 */
11708 intel_crtc->pipe = pipe;
11709 intel_crtc->plane = pipe;
11710 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
11711 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
11712 intel_crtc->plane = !pipe;
11713 }
11714
11715 intel_crtc->cursor_base = ~0;
11716 intel_crtc->cursor_cntl = ~0;
11717
11718 init_waitqueue_head(&intel_crtc->vbl_wait);
11719
11720 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
11721 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
11722 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
11723 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
11724
11725 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
11726
11727 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
11728 return;
11729
11730 fail:
11731 if (primary)
11732 drm_plane_cleanup(primary);
11733 if (cursor)
11734 drm_plane_cleanup(cursor);
11735 kfree(intel_crtc);
11736 }
11737
11738 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
11739 {
11740 struct drm_encoder *encoder = connector->base.encoder;
11741 struct drm_device *dev = connector->base.dev;
11742
11743 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
11744
11745 if (!encoder)
11746 return INVALID_PIPE;
11747
11748 return to_intel_crtc(encoder->crtc)->pipe;
11749 }
11750
11751 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
11752 struct drm_file *file)
11753 {
11754 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
11755 struct drm_mode_object *drmmode_obj;
11756 struct intel_crtc *crtc;
11757
11758 if (!drm_core_check_feature(dev, DRIVER_MODESET))
11759 return -ENODEV;
11760
11761 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
11762 DRM_MODE_OBJECT_CRTC);
11763
11764 if (!drmmode_obj) {
11765 DRM_ERROR("no such CRTC id\n");
11766 return -ENOENT;
11767 }
11768
11769 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
11770 pipe_from_crtc_id->pipe = crtc->pipe;
11771
11772 return 0;
11773 }
11774
11775 static int intel_encoder_clones(struct intel_encoder *encoder)
11776 {
11777 struct drm_device *dev = encoder->base.dev;
11778 struct intel_encoder *source_encoder;
11779 int index_mask = 0;
11780 int entry = 0;
11781
11782 list_for_each_entry(source_encoder,
11783 &dev->mode_config.encoder_list, base.head) {
11784 if (encoders_cloneable(encoder, source_encoder))
11785 index_mask |= (1 << entry);
11786
11787 entry++;
11788 }
11789
11790 return index_mask;
11791 }
11792
11793 static bool has_edp_a(struct drm_device *dev)
11794 {
11795 struct drm_i915_private *dev_priv = dev->dev_private;
11796
11797 if (!IS_MOBILE(dev))
11798 return false;
11799
11800 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
11801 return false;
11802
11803 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
11804 return false;
11805
11806 return true;
11807 }
11808
11809 const char *intel_output_name(int output)
11810 {
11811 static const char *names[] = {
11812 [INTEL_OUTPUT_UNUSED] = "Unused",
11813 [INTEL_OUTPUT_ANALOG] = "Analog",
11814 [INTEL_OUTPUT_DVO] = "DVO",
11815 [INTEL_OUTPUT_SDVO] = "SDVO",
11816 [INTEL_OUTPUT_LVDS] = "LVDS",
11817 [INTEL_OUTPUT_TVOUT] = "TV",
11818 [INTEL_OUTPUT_HDMI] = "HDMI",
11819 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
11820 [INTEL_OUTPUT_EDP] = "eDP",
11821 [INTEL_OUTPUT_DSI] = "DSI",
11822 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
11823 };
11824
11825 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
11826 return "Invalid";
11827
11828 return names[output];
11829 }
11830
11831 static bool intel_crt_present(struct drm_device *dev)
11832 {
11833 struct drm_i915_private *dev_priv = dev->dev_private;
11834
11835 if (IS_ULT(dev))
11836 return false;
11837
11838 if (IS_CHERRYVIEW(dev))
11839 return false;
11840
11841 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
11842 return false;
11843
11844 return true;
11845 }
11846
11847 static void intel_setup_outputs(struct drm_device *dev)
11848 {
11849 struct drm_i915_private *dev_priv = dev->dev_private;
11850 struct intel_encoder *encoder;
11851 bool dpd_is_edp = false;
11852
11853 intel_lvds_init(dev);
11854
11855 if (intel_crt_present(dev))
11856 intel_crt_init(dev);
11857
11858 if (HAS_DDI(dev)) {
11859 int found;
11860
11861 /* Haswell uses DDI functions to detect digital outputs */
11862 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
11863 /* DDI A only supports eDP */
11864 if (found)
11865 intel_ddi_init(dev, PORT_A);
11866
11867 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
11868 * register */
11869 found = I915_READ(SFUSE_STRAP);
11870
11871 if (found & SFUSE_STRAP_DDIB_DETECTED)
11872 intel_ddi_init(dev, PORT_B);
11873 if (found & SFUSE_STRAP_DDIC_DETECTED)
11874 intel_ddi_init(dev, PORT_C);
11875 if (found & SFUSE_STRAP_DDID_DETECTED)
11876 intel_ddi_init(dev, PORT_D);
11877 } else if (HAS_PCH_SPLIT(dev)) {
11878 int found;
11879 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
11880
11881 if (has_edp_a(dev))
11882 intel_dp_init(dev, DP_A, PORT_A);
11883
11884 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
11885 /* PCH SDVOB multiplex with HDMIB */
11886 found = intel_sdvo_init(dev, PCH_SDVOB, true);
11887 if (!found)
11888 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
11889 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
11890 intel_dp_init(dev, PCH_DP_B, PORT_B);
11891 }
11892
11893 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
11894 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
11895
11896 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
11897 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
11898
11899 if (I915_READ(PCH_DP_C) & DP_DETECTED)
11900 intel_dp_init(dev, PCH_DP_C, PORT_C);
11901
11902 if (I915_READ(PCH_DP_D) & DP_DETECTED)
11903 intel_dp_init(dev, PCH_DP_D, PORT_D);
11904 } else if (IS_VALLEYVIEW(dev)) {
11905 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
11906 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
11907 PORT_B);
11908 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
11909 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
11910 }
11911
11912 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
11913 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
11914 PORT_C);
11915 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
11916 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
11917 }
11918
11919 if (IS_CHERRYVIEW(dev)) {
11920 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) {
11921 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
11922 PORT_D);
11923 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
11924 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
11925 }
11926 }
11927
11928 intel_dsi_init(dev);
11929 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
11930 bool found = false;
11931
11932 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
11933 DRM_DEBUG_KMS("probing SDVOB\n");
11934 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
11935 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
11936 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
11937 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
11938 }
11939
11940 if (!found && SUPPORTS_INTEGRATED_DP(dev))
11941 intel_dp_init(dev, DP_B, PORT_B);
11942 }
11943
11944 /* Before G4X SDVOC doesn't have its own detect register */
11945
11946 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
11947 DRM_DEBUG_KMS("probing SDVOC\n");
11948 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
11949 }
11950
11951 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
11952
11953 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
11954 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
11955 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
11956 }
11957 if (SUPPORTS_INTEGRATED_DP(dev))
11958 intel_dp_init(dev, DP_C, PORT_C);
11959 }
11960
11961 if (SUPPORTS_INTEGRATED_DP(dev) &&
11962 (I915_READ(DP_D) & DP_DETECTED))
11963 intel_dp_init(dev, DP_D, PORT_D);
11964 } else if (IS_GEN2(dev))
11965 intel_dvo_init(dev);
11966
11967 if (SUPPORTS_TV(dev))
11968 intel_tv_init(dev);
11969
11970 intel_edp_psr_init(dev);
11971
11972 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
11973 encoder->base.possible_crtcs = encoder->crtc_mask;
11974 encoder->base.possible_clones =
11975 intel_encoder_clones(encoder);
11976 }
11977
11978 intel_init_pch_refclk(dev);
11979
11980 drm_helper_move_panel_connectors_to_head(dev);
11981 }
11982
11983 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
11984 {
11985 struct drm_device *dev = fb->dev;
11986 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11987
11988 drm_framebuffer_cleanup(fb);
11989 mutex_lock(&dev->struct_mutex);
11990 WARN_ON(!intel_fb->obj->framebuffer_references--);
11991 drm_gem_object_unreference(&intel_fb->obj->base);
11992 mutex_unlock(&dev->struct_mutex);
11993 kfree(intel_fb);
11994 }
11995
11996 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
11997 struct drm_file *file,
11998 unsigned int *handle)
11999 {
12000 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12001 struct drm_i915_gem_object *obj = intel_fb->obj;
12002
12003 return drm_gem_handle_create(file, &obj->base, handle);
12004 }
12005
12006 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12007 .destroy = intel_user_framebuffer_destroy,
12008 .create_handle = intel_user_framebuffer_create_handle,
12009 };
12010
12011 static int intel_framebuffer_init(struct drm_device *dev,
12012 struct intel_framebuffer *intel_fb,
12013 struct drm_mode_fb_cmd2 *mode_cmd,
12014 struct drm_i915_gem_object *obj)
12015 {
12016 int aligned_height;
12017 int pitch_limit;
12018 int ret;
12019
12020 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12021
12022 if (obj->tiling_mode == I915_TILING_Y) {
12023 DRM_DEBUG("hardware does not support tiling Y\n");
12024 return -EINVAL;
12025 }
12026
12027 if (mode_cmd->pitches[0] & 63) {
12028 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12029 mode_cmd->pitches[0]);
12030 return -EINVAL;
12031 }
12032
12033 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12034 pitch_limit = 32*1024;
12035 } else if (INTEL_INFO(dev)->gen >= 4) {
12036 if (obj->tiling_mode)
12037 pitch_limit = 16*1024;
12038 else
12039 pitch_limit = 32*1024;
12040 } else if (INTEL_INFO(dev)->gen >= 3) {
12041 if (obj->tiling_mode)
12042 pitch_limit = 8*1024;
12043 else
12044 pitch_limit = 16*1024;
12045 } else
12046 /* XXX DSPC is limited to 4k tiled */
12047 pitch_limit = 8*1024;
12048
12049 if (mode_cmd->pitches[0] > pitch_limit) {
12050 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12051 obj->tiling_mode ? "tiled" : "linear",
12052 mode_cmd->pitches[0], pitch_limit);
12053 return -EINVAL;
12054 }
12055
12056 if (obj->tiling_mode != I915_TILING_NONE &&
12057 mode_cmd->pitches[0] != obj->stride) {
12058 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12059 mode_cmd->pitches[0], obj->stride);
12060 return -EINVAL;
12061 }
12062
12063 /* Reject formats not supported by any plane early. */
12064 switch (mode_cmd->pixel_format) {
12065 case DRM_FORMAT_C8:
12066 case DRM_FORMAT_RGB565:
12067 case DRM_FORMAT_XRGB8888:
12068 case DRM_FORMAT_ARGB8888:
12069 break;
12070 case DRM_FORMAT_XRGB1555:
12071 case DRM_FORMAT_ARGB1555:
12072 if (INTEL_INFO(dev)->gen > 3) {
12073 DRM_DEBUG("unsupported pixel format: %s\n",
12074 drm_get_format_name(mode_cmd->pixel_format));
12075 return -EINVAL;
12076 }
12077 break;
12078 case DRM_FORMAT_XBGR8888:
12079 case DRM_FORMAT_ABGR8888:
12080 case DRM_FORMAT_XRGB2101010:
12081 case DRM_FORMAT_ARGB2101010:
12082 case DRM_FORMAT_XBGR2101010:
12083 case DRM_FORMAT_ABGR2101010:
12084 if (INTEL_INFO(dev)->gen < 4) {
12085 DRM_DEBUG("unsupported pixel format: %s\n",
12086 drm_get_format_name(mode_cmd->pixel_format));
12087 return -EINVAL;
12088 }
12089 break;
12090 case DRM_FORMAT_YUYV:
12091 case DRM_FORMAT_UYVY:
12092 case DRM_FORMAT_YVYU:
12093 case DRM_FORMAT_VYUY:
12094 if (INTEL_INFO(dev)->gen < 5) {
12095 DRM_DEBUG("unsupported pixel format: %s\n",
12096 drm_get_format_name(mode_cmd->pixel_format));
12097 return -EINVAL;
12098 }
12099 break;
12100 default:
12101 DRM_DEBUG("unsupported pixel format: %s\n",
12102 drm_get_format_name(mode_cmd->pixel_format));
12103 return -EINVAL;
12104 }
12105
12106 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12107 if (mode_cmd->offsets[0] != 0)
12108 return -EINVAL;
12109
12110 aligned_height = intel_align_height(dev, mode_cmd->height,
12111 obj->tiling_mode);
12112 /* FIXME drm helper for size checks (especially planar formats)? */
12113 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12114 return -EINVAL;
12115
12116 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12117 intel_fb->obj = obj;
12118 intel_fb->obj->framebuffer_references++;
12119
12120 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12121 if (ret) {
12122 DRM_ERROR("framebuffer init failed %d\n", ret);
12123 return ret;
12124 }
12125
12126 return 0;
12127 }
12128
12129 static struct drm_framebuffer *
12130 intel_user_framebuffer_create(struct drm_device *dev,
12131 struct drm_file *filp,
12132 struct drm_mode_fb_cmd2 *mode_cmd)
12133 {
12134 struct drm_i915_gem_object *obj;
12135
12136 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12137 mode_cmd->handles[0]));
12138 if (&obj->base == NULL)
12139 return ERR_PTR(-ENOENT);
12140
12141 return intel_framebuffer_create(dev, mode_cmd, obj);
12142 }
12143
12144 #ifndef CONFIG_DRM_I915_FBDEV
12145 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12146 {
12147 }
12148 #endif
12149
12150 static const struct drm_mode_config_funcs intel_mode_funcs = {
12151 .fb_create = intel_user_framebuffer_create,
12152 .output_poll_changed = intel_fbdev_output_poll_changed,
12153 };
12154
12155 /* Set up chip specific display functions */
12156 static void intel_init_display(struct drm_device *dev)
12157 {
12158 struct drm_i915_private *dev_priv = dev->dev_private;
12159
12160 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12161 dev_priv->display.find_dpll = g4x_find_best_dpll;
12162 else if (IS_CHERRYVIEW(dev))
12163 dev_priv->display.find_dpll = chv_find_best_dpll;
12164 else if (IS_VALLEYVIEW(dev))
12165 dev_priv->display.find_dpll = vlv_find_best_dpll;
12166 else if (IS_PINEVIEW(dev))
12167 dev_priv->display.find_dpll = pnv_find_best_dpll;
12168 else
12169 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12170
12171 if (HAS_DDI(dev)) {
12172 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12173 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12174 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
12175 dev_priv->display.crtc_enable = haswell_crtc_enable;
12176 dev_priv->display.crtc_disable = haswell_crtc_disable;
12177 dev_priv->display.off = haswell_crtc_off;
12178 dev_priv->display.update_primary_plane =
12179 ironlake_update_primary_plane;
12180 } else if (HAS_PCH_SPLIT(dev)) {
12181 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12182 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12183 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
12184 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12185 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12186 dev_priv->display.off = ironlake_crtc_off;
12187 dev_priv->display.update_primary_plane =
12188 ironlake_update_primary_plane;
12189 } else if (IS_VALLEYVIEW(dev)) {
12190 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12191 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12192 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12193 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12194 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12195 dev_priv->display.off = i9xx_crtc_off;
12196 dev_priv->display.update_primary_plane =
12197 i9xx_update_primary_plane;
12198 } else {
12199 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12200 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12201 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12202 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12203 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12204 dev_priv->display.off = i9xx_crtc_off;
12205 dev_priv->display.update_primary_plane =
12206 i9xx_update_primary_plane;
12207 }
12208
12209 /* Returns the core display clock speed */
12210 if (IS_VALLEYVIEW(dev))
12211 dev_priv->display.get_display_clock_speed =
12212 valleyview_get_display_clock_speed;
12213 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12214 dev_priv->display.get_display_clock_speed =
12215 i945_get_display_clock_speed;
12216 else if (IS_I915G(dev))
12217 dev_priv->display.get_display_clock_speed =
12218 i915_get_display_clock_speed;
12219 else if (IS_I945GM(dev) || IS_845G(dev))
12220 dev_priv->display.get_display_clock_speed =
12221 i9xx_misc_get_display_clock_speed;
12222 else if (IS_PINEVIEW(dev))
12223 dev_priv->display.get_display_clock_speed =
12224 pnv_get_display_clock_speed;
12225 else if (IS_I915GM(dev))
12226 dev_priv->display.get_display_clock_speed =
12227 i915gm_get_display_clock_speed;
12228 else if (IS_I865G(dev))
12229 dev_priv->display.get_display_clock_speed =
12230 i865_get_display_clock_speed;
12231 else if (IS_I85X(dev))
12232 dev_priv->display.get_display_clock_speed =
12233 i855_get_display_clock_speed;
12234 else /* 852, 830 */
12235 dev_priv->display.get_display_clock_speed =
12236 i830_get_display_clock_speed;
12237
12238 if (HAS_PCH_SPLIT(dev)) {
12239 if (IS_GEN5(dev)) {
12240 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12241 dev_priv->display.write_eld = ironlake_write_eld;
12242 } else if (IS_GEN6(dev)) {
12243 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12244 dev_priv->display.write_eld = ironlake_write_eld;
12245 dev_priv->display.modeset_global_resources =
12246 snb_modeset_global_resources;
12247 } else if (IS_IVYBRIDGE(dev)) {
12248 /* FIXME: detect B0+ stepping and use auto training */
12249 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12250 dev_priv->display.write_eld = ironlake_write_eld;
12251 dev_priv->display.modeset_global_resources =
12252 ivb_modeset_global_resources;
12253 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
12254 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12255 dev_priv->display.write_eld = haswell_write_eld;
12256 dev_priv->display.modeset_global_resources =
12257 haswell_modeset_global_resources;
12258 }
12259 } else if (IS_G4X(dev)) {
12260 dev_priv->display.write_eld = g4x_write_eld;
12261 } else if (IS_VALLEYVIEW(dev)) {
12262 dev_priv->display.modeset_global_resources =
12263 valleyview_modeset_global_resources;
12264 dev_priv->display.write_eld = ironlake_write_eld;
12265 }
12266
12267 /* Default just returns -ENODEV to indicate unsupported */
12268 dev_priv->display.queue_flip = intel_default_queue_flip;
12269
12270 switch (INTEL_INFO(dev)->gen) {
12271 case 2:
12272 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12273 break;
12274
12275 case 3:
12276 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12277 break;
12278
12279 case 4:
12280 case 5:
12281 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12282 break;
12283
12284 case 6:
12285 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12286 break;
12287 case 7:
12288 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12289 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12290 break;
12291 }
12292
12293 intel_panel_init_backlight_funcs(dev);
12294 }
12295
12296 /*
12297 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12298 * resume, or other times. This quirk makes sure that's the case for
12299 * affected systems.
12300 */
12301 static void quirk_pipea_force(struct drm_device *dev)
12302 {
12303 struct drm_i915_private *dev_priv = dev->dev_private;
12304
12305 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12306 DRM_INFO("applying pipe a force quirk\n");
12307 }
12308
12309 /*
12310 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12311 */
12312 static void quirk_ssc_force_disable(struct drm_device *dev)
12313 {
12314 struct drm_i915_private *dev_priv = dev->dev_private;
12315 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12316 DRM_INFO("applying lvds SSC disable quirk\n");
12317 }
12318
12319 /*
12320 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12321 * brightness value
12322 */
12323 static void quirk_invert_brightness(struct drm_device *dev)
12324 {
12325 struct drm_i915_private *dev_priv = dev->dev_private;
12326 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12327 DRM_INFO("applying inverted panel brightness quirk\n");
12328 }
12329
12330 struct intel_quirk {
12331 int device;
12332 int subsystem_vendor;
12333 int subsystem_device;
12334 void (*hook)(struct drm_device *dev);
12335 };
12336
12337 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12338 struct intel_dmi_quirk {
12339 void (*hook)(struct drm_device *dev);
12340 const struct dmi_system_id (*dmi_id_list)[];
12341 };
12342
12343 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12344 {
12345 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12346 return 1;
12347 }
12348
12349 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12350 {
12351 .dmi_id_list = &(const struct dmi_system_id[]) {
12352 {
12353 .callback = intel_dmi_reverse_brightness,
12354 .ident = "NCR Corporation",
12355 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12356 DMI_MATCH(DMI_PRODUCT_NAME, ""),
12357 },
12358 },
12359 { } /* terminating entry */
12360 },
12361 .hook = quirk_invert_brightness,
12362 },
12363 };
12364
12365 static struct intel_quirk intel_quirks[] = {
12366 /* HP Mini needs pipe A force quirk (LP: #322104) */
12367 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12368
12369 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12370 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12371
12372 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12373 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12374
12375 /* Lenovo U160 cannot use SSC on LVDS */
12376 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12377
12378 /* Sony Vaio Y cannot use SSC on LVDS */
12379 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12380
12381 /* Acer Aspire 5734Z must invert backlight brightness */
12382 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12383
12384 /* Acer/eMachines G725 */
12385 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12386
12387 /* Acer/eMachines e725 */
12388 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12389
12390 /* Acer/Packard Bell NCL20 */
12391 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12392
12393 /* Acer Aspire 4736Z */
12394 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12395
12396 /* Acer Aspire 5336 */
12397 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12398 };
12399
12400 static void intel_init_quirks(struct drm_device *dev)
12401 {
12402 struct pci_dev *d = dev->pdev;
12403 int i;
12404
12405 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12406 struct intel_quirk *q = &intel_quirks[i];
12407
12408 if (d->device == q->device &&
12409 (d->subsystem_vendor == q->subsystem_vendor ||
12410 q->subsystem_vendor == PCI_ANY_ID) &&
12411 (d->subsystem_device == q->subsystem_device ||
12412 q->subsystem_device == PCI_ANY_ID))
12413 q->hook(dev);
12414 }
12415 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12416 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12417 intel_dmi_quirks[i].hook(dev);
12418 }
12419 }
12420
12421 /* Disable the VGA plane that we never use */
12422 static void i915_disable_vga(struct drm_device *dev)
12423 {
12424 struct drm_i915_private *dev_priv = dev->dev_private;
12425 u8 sr1;
12426 u32 vga_reg = i915_vgacntrl_reg(dev);
12427
12428 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12429 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12430 outb(SR01, VGA_SR_INDEX);
12431 sr1 = inb(VGA_SR_DATA);
12432 outb(sr1 | 1<<5, VGA_SR_DATA);
12433 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12434 udelay(300);
12435
12436 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
12437 POSTING_READ(vga_reg);
12438 }
12439
12440 void intel_modeset_init_hw(struct drm_device *dev)
12441 {
12442 intel_prepare_ddi(dev);
12443
12444 if (IS_VALLEYVIEW(dev))
12445 vlv_update_cdclk(dev);
12446
12447 intel_init_clock_gating(dev);
12448
12449 intel_reset_dpio(dev);
12450
12451 intel_enable_gt_powersave(dev);
12452 }
12453
12454 void intel_modeset_suspend_hw(struct drm_device *dev)
12455 {
12456 intel_suspend_hw(dev);
12457 }
12458
12459 void intel_modeset_init(struct drm_device *dev)
12460 {
12461 struct drm_i915_private *dev_priv = dev->dev_private;
12462 int sprite, ret;
12463 enum pipe pipe;
12464 struct intel_crtc *crtc;
12465
12466 drm_mode_config_init(dev);
12467
12468 dev->mode_config.min_width = 0;
12469 dev->mode_config.min_height = 0;
12470
12471 dev->mode_config.preferred_depth = 24;
12472 dev->mode_config.prefer_shadow = 1;
12473
12474 dev->mode_config.funcs = &intel_mode_funcs;
12475
12476 intel_init_quirks(dev);
12477
12478 intel_init_pm(dev);
12479
12480 if (INTEL_INFO(dev)->num_pipes == 0)
12481 return;
12482
12483 intel_init_display(dev);
12484
12485 if (IS_GEN2(dev)) {
12486 dev->mode_config.max_width = 2048;
12487 dev->mode_config.max_height = 2048;
12488 } else if (IS_GEN3(dev)) {
12489 dev->mode_config.max_width = 4096;
12490 dev->mode_config.max_height = 4096;
12491 } else {
12492 dev->mode_config.max_width = 8192;
12493 dev->mode_config.max_height = 8192;
12494 }
12495
12496 if (IS_GEN2(dev)) {
12497 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12498 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12499 } else {
12500 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
12501 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
12502 }
12503
12504 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
12505
12506 DRM_DEBUG_KMS("%d display pipe%s available.\n",
12507 INTEL_INFO(dev)->num_pipes,
12508 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
12509
12510 for_each_pipe(pipe) {
12511 intel_crtc_init(dev, pipe);
12512 for_each_sprite(pipe, sprite) {
12513 ret = intel_plane_init(dev, pipe, sprite);
12514 if (ret)
12515 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12516 pipe_name(pipe), sprite_name(pipe, sprite), ret);
12517 }
12518 }
12519
12520 intel_init_dpio(dev);
12521 intel_reset_dpio(dev);
12522
12523 intel_cpu_pll_init(dev);
12524 intel_shared_dpll_init(dev);
12525
12526 /* Just disable it once at startup */
12527 i915_disable_vga(dev);
12528 intel_setup_outputs(dev);
12529
12530 /* Just in case the BIOS is doing something questionable. */
12531 intel_disable_fbc(dev);
12532
12533 drm_modeset_lock_all(dev);
12534 intel_modeset_setup_hw_state(dev, false);
12535 drm_modeset_unlock_all(dev);
12536
12537 for_each_intel_crtc(dev, crtc) {
12538 if (!crtc->active)
12539 continue;
12540
12541 /*
12542 * Note that reserving the BIOS fb up front prevents us
12543 * from stuffing other stolen allocations like the ring
12544 * on top. This prevents some ugliness at boot time, and
12545 * can even allow for smooth boot transitions if the BIOS
12546 * fb is large enough for the active pipe configuration.
12547 */
12548 if (dev_priv->display.get_plane_config) {
12549 dev_priv->display.get_plane_config(crtc,
12550 &crtc->plane_config);
12551 /*
12552 * If the fb is shared between multiple heads, we'll
12553 * just get the first one.
12554 */
12555 intel_find_plane_obj(crtc, &crtc->plane_config);
12556 }
12557 }
12558 }
12559
12560 static void intel_enable_pipe_a(struct drm_device *dev)
12561 {
12562 struct intel_connector *connector;
12563 struct drm_connector *crt = NULL;
12564 struct intel_load_detect_pipe load_detect_temp;
12565 struct drm_modeset_acquire_ctx ctx;
12566
12567 /* We can't just switch on the pipe A, we need to set things up with a
12568 * proper mode and output configuration. As a gross hack, enable pipe A
12569 * by enabling the load detect pipe once. */
12570 list_for_each_entry(connector,
12571 &dev->mode_config.connector_list,
12572 base.head) {
12573 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
12574 crt = &connector->base;
12575 break;
12576 }
12577 }
12578
12579 if (!crt)
12580 return;
12581
12582 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, &ctx))
12583 intel_release_load_detect_pipe(crt, &load_detect_temp, &ctx);
12584
12585
12586 }
12587
12588 static bool
12589 intel_check_plane_mapping(struct intel_crtc *crtc)
12590 {
12591 struct drm_device *dev = crtc->base.dev;
12592 struct drm_i915_private *dev_priv = dev->dev_private;
12593 u32 reg, val;
12594
12595 if (INTEL_INFO(dev)->num_pipes == 1)
12596 return true;
12597
12598 reg = DSPCNTR(!crtc->plane);
12599 val = I915_READ(reg);
12600
12601 if ((val & DISPLAY_PLANE_ENABLE) &&
12602 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
12603 return false;
12604
12605 return true;
12606 }
12607
12608 static void intel_sanitize_crtc(struct intel_crtc *crtc)
12609 {
12610 struct drm_device *dev = crtc->base.dev;
12611 struct drm_i915_private *dev_priv = dev->dev_private;
12612 u32 reg;
12613
12614 /* Clear any frame start delays used for debugging left by the BIOS */
12615 reg = PIPECONF(crtc->config.cpu_transcoder);
12616 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
12617
12618 /* restore vblank interrupts to correct state */
12619 if (crtc->active)
12620 drm_vblank_on(dev, crtc->pipe);
12621 else
12622 drm_vblank_off(dev, crtc->pipe);
12623
12624 /* We need to sanitize the plane -> pipe mapping first because this will
12625 * disable the crtc (and hence change the state) if it is wrong. Note
12626 * that gen4+ has a fixed plane -> pipe mapping. */
12627 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
12628 struct intel_connector *connector;
12629 bool plane;
12630
12631 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
12632 crtc->base.base.id);
12633
12634 /* Pipe has the wrong plane attached and the plane is active.
12635 * Temporarily change the plane mapping and disable everything
12636 * ... */
12637 plane = crtc->plane;
12638 crtc->plane = !plane;
12639 dev_priv->display.crtc_disable(&crtc->base);
12640 crtc->plane = plane;
12641
12642 /* ... and break all links. */
12643 list_for_each_entry(connector, &dev->mode_config.connector_list,
12644 base.head) {
12645 if (connector->encoder->base.crtc != &crtc->base)
12646 continue;
12647
12648 connector->base.dpms = DRM_MODE_DPMS_OFF;
12649 connector->base.encoder = NULL;
12650 }
12651 /* multiple connectors may have the same encoder:
12652 * handle them and break crtc link separately */
12653 list_for_each_entry(connector, &dev->mode_config.connector_list,
12654 base.head)
12655 if (connector->encoder->base.crtc == &crtc->base) {
12656 connector->encoder->base.crtc = NULL;
12657 connector->encoder->connectors_active = false;
12658 }
12659
12660 WARN_ON(crtc->active);
12661 crtc->base.enabled = false;
12662 }
12663
12664 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
12665 crtc->pipe == PIPE_A && !crtc->active) {
12666 /* BIOS forgot to enable pipe A, this mostly happens after
12667 * resume. Force-enable the pipe to fix this, the update_dpms
12668 * call below we restore the pipe to the right state, but leave
12669 * the required bits on. */
12670 intel_enable_pipe_a(dev);
12671 }
12672
12673 /* Adjust the state of the output pipe according to whether we
12674 * have active connectors/encoders. */
12675 intel_crtc_update_dpms(&crtc->base);
12676
12677 if (crtc->active != crtc->base.enabled) {
12678 struct intel_encoder *encoder;
12679
12680 /* This can happen either due to bugs in the get_hw_state
12681 * functions or because the pipe is force-enabled due to the
12682 * pipe A quirk. */
12683 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
12684 crtc->base.base.id,
12685 crtc->base.enabled ? "enabled" : "disabled",
12686 crtc->active ? "enabled" : "disabled");
12687
12688 crtc->base.enabled = crtc->active;
12689
12690 /* Because we only establish the connector -> encoder ->
12691 * crtc links if something is active, this means the
12692 * crtc is now deactivated. Break the links. connector
12693 * -> encoder links are only establish when things are
12694 * actually up, hence no need to break them. */
12695 WARN_ON(crtc->active);
12696
12697 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
12698 WARN_ON(encoder->connectors_active);
12699 encoder->base.crtc = NULL;
12700 }
12701 }
12702
12703 if (crtc->active || IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen < 5) {
12704 /*
12705 * We start out with underrun reporting disabled to avoid races.
12706 * For correct bookkeeping mark this on active crtcs.
12707 *
12708 * Also on gmch platforms we dont have any hardware bits to
12709 * disable the underrun reporting. Which means we need to start
12710 * out with underrun reporting disabled also on inactive pipes,
12711 * since otherwise we'll complain about the garbage we read when
12712 * e.g. coming up after runtime pm.
12713 *
12714 * No protection against concurrent access is required - at
12715 * worst a fifo underrun happens which also sets this to false.
12716 */
12717 crtc->cpu_fifo_underrun_disabled = true;
12718 crtc->pch_fifo_underrun_disabled = true;
12719
12720 update_scanline_offset(crtc);
12721 }
12722 }
12723
12724 static void intel_sanitize_encoder(struct intel_encoder *encoder)
12725 {
12726 struct intel_connector *connector;
12727 struct drm_device *dev = encoder->base.dev;
12728
12729 /* We need to check both for a crtc link (meaning that the
12730 * encoder is active and trying to read from a pipe) and the
12731 * pipe itself being active. */
12732 bool has_active_crtc = encoder->base.crtc &&
12733 to_intel_crtc(encoder->base.crtc)->active;
12734
12735 if (encoder->connectors_active && !has_active_crtc) {
12736 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
12737 encoder->base.base.id,
12738 encoder->base.name);
12739
12740 /* Connector is active, but has no active pipe. This is
12741 * fallout from our resume register restoring. Disable
12742 * the encoder manually again. */
12743 if (encoder->base.crtc) {
12744 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
12745 encoder->base.base.id,
12746 encoder->base.name);
12747 encoder->disable(encoder);
12748 }
12749 encoder->base.crtc = NULL;
12750 encoder->connectors_active = false;
12751
12752 /* Inconsistent output/port/pipe state happens presumably due to
12753 * a bug in one of the get_hw_state functions. Or someplace else
12754 * in our code, like the register restore mess on resume. Clamp
12755 * things to off as a safer default. */
12756 list_for_each_entry(connector,
12757 &dev->mode_config.connector_list,
12758 base.head) {
12759 if (connector->encoder != encoder)
12760 continue;
12761 connector->base.dpms = DRM_MODE_DPMS_OFF;
12762 connector->base.encoder = NULL;
12763 }
12764 }
12765 /* Enabled encoders without active connectors will be fixed in
12766 * the crtc fixup. */
12767 }
12768
12769 void i915_redisable_vga_power_on(struct drm_device *dev)
12770 {
12771 struct drm_i915_private *dev_priv = dev->dev_private;
12772 u32 vga_reg = i915_vgacntrl_reg(dev);
12773
12774 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
12775 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
12776 i915_disable_vga(dev);
12777 }
12778 }
12779
12780 void i915_redisable_vga(struct drm_device *dev)
12781 {
12782 struct drm_i915_private *dev_priv = dev->dev_private;
12783
12784 /* This function can be called both from intel_modeset_setup_hw_state or
12785 * at a very early point in our resume sequence, where the power well
12786 * structures are not yet restored. Since this function is at a very
12787 * paranoid "someone might have enabled VGA while we were not looking"
12788 * level, just check if the power well is enabled instead of trying to
12789 * follow the "don't touch the power well if we don't need it" policy
12790 * the rest of the driver uses. */
12791 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
12792 return;
12793
12794 i915_redisable_vga_power_on(dev);
12795 }
12796
12797 static bool primary_get_hw_state(struct intel_crtc *crtc)
12798 {
12799 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
12800
12801 if (!crtc->active)
12802 return false;
12803
12804 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
12805 }
12806
12807 static void intel_modeset_readout_hw_state(struct drm_device *dev)
12808 {
12809 struct drm_i915_private *dev_priv = dev->dev_private;
12810 enum pipe pipe;
12811 struct intel_crtc *crtc;
12812 struct intel_encoder *encoder;
12813 struct intel_connector *connector;
12814 int i;
12815
12816 for_each_intel_crtc(dev, crtc) {
12817 memset(&crtc->config, 0, sizeof(crtc->config));
12818
12819 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
12820
12821 crtc->active = dev_priv->display.get_pipe_config(crtc,
12822 &crtc->config);
12823
12824 crtc->base.enabled = crtc->active;
12825 crtc->primary_enabled = primary_get_hw_state(crtc);
12826
12827 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
12828 crtc->base.base.id,
12829 crtc->active ? "enabled" : "disabled");
12830 }
12831
12832 /* FIXME: Smash this into the new shared dpll infrastructure. */
12833 if (HAS_DDI(dev))
12834 intel_ddi_setup_hw_pll_state(dev);
12835
12836 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12837 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12838
12839 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
12840 pll->active = 0;
12841 for_each_intel_crtc(dev, crtc) {
12842 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12843 pll->active++;
12844 }
12845 pll->refcount = pll->active;
12846
12847 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
12848 pll->name, pll->refcount, pll->on);
12849 }
12850
12851 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
12852 base.head) {
12853 pipe = 0;
12854
12855 if (encoder->get_hw_state(encoder, &pipe)) {
12856 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
12857 encoder->base.crtc = &crtc->base;
12858 encoder->get_config(encoder, &crtc->config);
12859 } else {
12860 encoder->base.crtc = NULL;
12861 }
12862
12863 encoder->connectors_active = false;
12864 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
12865 encoder->base.base.id,
12866 encoder->base.name,
12867 encoder->base.crtc ? "enabled" : "disabled",
12868 pipe_name(pipe));
12869 }
12870
12871 list_for_each_entry(connector, &dev->mode_config.connector_list,
12872 base.head) {
12873 if (connector->get_hw_state(connector)) {
12874 connector->base.dpms = DRM_MODE_DPMS_ON;
12875 connector->encoder->connectors_active = true;
12876 connector->base.encoder = &connector->encoder->base;
12877 } else {
12878 connector->base.dpms = DRM_MODE_DPMS_OFF;
12879 connector->base.encoder = NULL;
12880 }
12881 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
12882 connector->base.base.id,
12883 connector->base.name,
12884 connector->base.encoder ? "enabled" : "disabled");
12885 }
12886 }
12887
12888 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
12889 * and i915 state tracking structures. */
12890 void intel_modeset_setup_hw_state(struct drm_device *dev,
12891 bool force_restore)
12892 {
12893 struct drm_i915_private *dev_priv = dev->dev_private;
12894 enum pipe pipe;
12895 struct intel_crtc *crtc;
12896 struct intel_encoder *encoder;
12897 int i;
12898
12899 intel_modeset_readout_hw_state(dev);
12900
12901 /*
12902 * Now that we have the config, copy it to each CRTC struct
12903 * Note that this could go away if we move to using crtc_config
12904 * checking everywhere.
12905 */
12906 for_each_intel_crtc(dev, crtc) {
12907 if (crtc->active && i915.fastboot) {
12908 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
12909 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
12910 crtc->base.base.id);
12911 drm_mode_debug_printmodeline(&crtc->base.mode);
12912 }
12913 }
12914
12915 /* HW state is read out, now we need to sanitize this mess. */
12916 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
12917 base.head) {
12918 intel_sanitize_encoder(encoder);
12919 }
12920
12921 for_each_pipe(pipe) {
12922 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
12923 intel_sanitize_crtc(crtc);
12924 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
12925 }
12926
12927 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12928 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12929
12930 if (!pll->on || pll->active)
12931 continue;
12932
12933 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
12934
12935 pll->disable(dev_priv, pll);
12936 pll->on = false;
12937 }
12938
12939 if (HAS_PCH_SPLIT(dev))
12940 ilk_wm_get_hw_state(dev);
12941
12942 if (force_restore) {
12943 i915_redisable_vga(dev);
12944
12945 /*
12946 * We need to use raw interfaces for restoring state to avoid
12947 * checking (bogus) intermediate states.
12948 */
12949 for_each_pipe(pipe) {
12950 struct drm_crtc *crtc =
12951 dev_priv->pipe_to_crtc_mapping[pipe];
12952
12953 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
12954 crtc->primary->fb);
12955 }
12956 } else {
12957 intel_modeset_update_staged_output_state(dev);
12958 }
12959
12960 intel_modeset_check_state(dev);
12961 }
12962
12963 void intel_modeset_gem_init(struct drm_device *dev)
12964 {
12965 struct drm_crtc *c;
12966 struct drm_i915_gem_object *obj;
12967
12968 mutex_lock(&dev->struct_mutex);
12969 intel_init_gt_powersave(dev);
12970 mutex_unlock(&dev->struct_mutex);
12971
12972 intel_modeset_init_hw(dev);
12973
12974 intel_setup_overlay(dev);
12975
12976 /*
12977 * Make sure any fbs we allocated at startup are properly
12978 * pinned & fenced. When we do the allocation it's too early
12979 * for this.
12980 */
12981 mutex_lock(&dev->struct_mutex);
12982 for_each_crtc(dev, c) {
12983 obj = intel_fb_obj(c->primary->fb);
12984 if (obj == NULL)
12985 continue;
12986
12987 if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) {
12988 DRM_ERROR("failed to pin boot fb on pipe %d\n",
12989 to_intel_crtc(c)->pipe);
12990 drm_framebuffer_unreference(c->primary->fb);
12991 c->primary->fb = NULL;
12992 }
12993 }
12994 mutex_unlock(&dev->struct_mutex);
12995 }
12996
12997 void intel_connector_unregister(struct intel_connector *intel_connector)
12998 {
12999 struct drm_connector *connector = &intel_connector->base;
13000
13001 intel_panel_destroy_backlight(connector);
13002 drm_sysfs_connector_remove(connector);
13003 }
13004
13005 void intel_modeset_cleanup(struct drm_device *dev)
13006 {
13007 struct drm_i915_private *dev_priv = dev->dev_private;
13008 struct drm_connector *connector;
13009
13010 /*
13011 * Interrupts and polling as the first thing to avoid creating havoc.
13012 * Too much stuff here (turning of rps, connectors, ...) would
13013 * experience fancy races otherwise.
13014 */
13015 drm_irq_uninstall(dev);
13016 cancel_work_sync(&dev_priv->hotplug_work);
13017 /*
13018 * Due to the hpd irq storm handling the hotplug work can re-arm the
13019 * poll handlers. Hence disable polling after hpd handling is shut down.
13020 */
13021 drm_kms_helper_poll_fini(dev);
13022
13023 mutex_lock(&dev->struct_mutex);
13024
13025 intel_unregister_dsm_handler();
13026
13027 intel_disable_fbc(dev);
13028
13029 intel_disable_gt_powersave(dev);
13030
13031 ironlake_teardown_rc6(dev);
13032
13033 mutex_unlock(&dev->struct_mutex);
13034
13035 /* flush any delayed tasks or pending work */
13036 flush_scheduled_work();
13037
13038 /* destroy the backlight and sysfs files before encoders/connectors */
13039 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13040 struct intel_connector *intel_connector;
13041
13042 intel_connector = to_intel_connector(connector);
13043 intel_connector->unregister(intel_connector);
13044 }
13045
13046 drm_mode_config_cleanup(dev);
13047
13048 intel_cleanup_overlay(dev);
13049
13050 mutex_lock(&dev->struct_mutex);
13051 intel_cleanup_gt_powersave(dev);
13052 mutex_unlock(&dev->struct_mutex);
13053 }
13054
13055 /*
13056 * Return which encoder is currently attached for connector.
13057 */
13058 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13059 {
13060 return &intel_attached_encoder(connector)->base;
13061 }
13062
13063 void intel_connector_attach_encoder(struct intel_connector *connector,
13064 struct intel_encoder *encoder)
13065 {
13066 connector->encoder = encoder;
13067 drm_mode_connector_attach_encoder(&connector->base,
13068 &encoder->base);
13069 }
13070
13071 /*
13072 * set vga decode state - true == enable VGA decode
13073 */
13074 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13075 {
13076 struct drm_i915_private *dev_priv = dev->dev_private;
13077 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13078 u16 gmch_ctrl;
13079
13080 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13081 DRM_ERROR("failed to read control word\n");
13082 return -EIO;
13083 }
13084
13085 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13086 return 0;
13087
13088 if (state)
13089 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13090 else
13091 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13092
13093 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13094 DRM_ERROR("failed to write control word\n");
13095 return -EIO;
13096 }
13097
13098 return 0;
13099 }
13100
13101 struct intel_display_error_state {
13102
13103 u32 power_well_driver;
13104
13105 int num_transcoders;
13106
13107 struct intel_cursor_error_state {
13108 u32 control;
13109 u32 position;
13110 u32 base;
13111 u32 size;
13112 } cursor[I915_MAX_PIPES];
13113
13114 struct intel_pipe_error_state {
13115 bool power_domain_on;
13116 u32 source;
13117 u32 stat;
13118 } pipe[I915_MAX_PIPES];
13119
13120 struct intel_plane_error_state {
13121 u32 control;
13122 u32 stride;
13123 u32 size;
13124 u32 pos;
13125 u32 addr;
13126 u32 surface;
13127 u32 tile_offset;
13128 } plane[I915_MAX_PIPES];
13129
13130 struct intel_transcoder_error_state {
13131 bool power_domain_on;
13132 enum transcoder cpu_transcoder;
13133
13134 u32 conf;
13135
13136 u32 htotal;
13137 u32 hblank;
13138 u32 hsync;
13139 u32 vtotal;
13140 u32 vblank;
13141 u32 vsync;
13142 } transcoder[4];
13143 };
13144
13145 struct intel_display_error_state *
13146 intel_display_capture_error_state(struct drm_device *dev)
13147 {
13148 struct drm_i915_private *dev_priv = dev->dev_private;
13149 struct intel_display_error_state *error;
13150 int transcoders[] = {
13151 TRANSCODER_A,
13152 TRANSCODER_B,
13153 TRANSCODER_C,
13154 TRANSCODER_EDP,
13155 };
13156 int i;
13157
13158 if (INTEL_INFO(dev)->num_pipes == 0)
13159 return NULL;
13160
13161 error = kzalloc(sizeof(*error), GFP_ATOMIC);
13162 if (error == NULL)
13163 return NULL;
13164
13165 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13166 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13167
13168 for_each_pipe(i) {
13169 error->pipe[i].power_domain_on =
13170 intel_display_power_enabled_unlocked(dev_priv,
13171 POWER_DOMAIN_PIPE(i));
13172 if (!error->pipe[i].power_domain_on)
13173 continue;
13174
13175 error->cursor[i].control = I915_READ(CURCNTR(i));
13176 error->cursor[i].position = I915_READ(CURPOS(i));
13177 error->cursor[i].base = I915_READ(CURBASE(i));
13178
13179 error->plane[i].control = I915_READ(DSPCNTR(i));
13180 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13181 if (INTEL_INFO(dev)->gen <= 3) {
13182 error->plane[i].size = I915_READ(DSPSIZE(i));
13183 error->plane[i].pos = I915_READ(DSPPOS(i));
13184 }
13185 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13186 error->plane[i].addr = I915_READ(DSPADDR(i));
13187 if (INTEL_INFO(dev)->gen >= 4) {
13188 error->plane[i].surface = I915_READ(DSPSURF(i));
13189 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13190 }
13191
13192 error->pipe[i].source = I915_READ(PIPESRC(i));
13193
13194 if (!HAS_PCH_SPLIT(dev))
13195 error->pipe[i].stat = I915_READ(PIPESTAT(i));
13196 }
13197
13198 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13199 if (HAS_DDI(dev_priv->dev))
13200 error->num_transcoders++; /* Account for eDP. */
13201
13202 for (i = 0; i < error->num_transcoders; i++) {
13203 enum transcoder cpu_transcoder = transcoders[i];
13204
13205 error->transcoder[i].power_domain_on =
13206 intel_display_power_enabled_unlocked(dev_priv,
13207 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13208 if (!error->transcoder[i].power_domain_on)
13209 continue;
13210
13211 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13212
13213 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13214 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13215 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13216 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13217 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13218 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13219 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13220 }
13221
13222 return error;
13223 }
13224
13225 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13226
13227 void
13228 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13229 struct drm_device *dev,
13230 struct intel_display_error_state *error)
13231 {
13232 int i;
13233
13234 if (!error)
13235 return;
13236
13237 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13238 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13239 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13240 error->power_well_driver);
13241 for_each_pipe(i) {
13242 err_printf(m, "Pipe [%d]:\n", i);
13243 err_printf(m, " Power: %s\n",
13244 error->pipe[i].power_domain_on ? "on" : "off");
13245 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
13246 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
13247
13248 err_printf(m, "Plane [%d]:\n", i);
13249 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
13250 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
13251 if (INTEL_INFO(dev)->gen <= 3) {
13252 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
13253 err_printf(m, " POS: %08x\n", error->plane[i].pos);
13254 }
13255 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13256 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
13257 if (INTEL_INFO(dev)->gen >= 4) {
13258 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
13259 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
13260 }
13261
13262 err_printf(m, "Cursor [%d]:\n", i);
13263 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
13264 err_printf(m, " POS: %08x\n", error->cursor[i].position);
13265 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
13266 }
13267
13268 for (i = 0; i < error->num_transcoders; i++) {
13269 err_printf(m, "CPU transcoder: %c\n",
13270 transcoder_name(error->transcoder[i].cpu_transcoder));
13271 err_printf(m, " Power: %s\n",
13272 error->transcoder[i].power_domain_on ? "on" : "off");
13273 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
13274 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
13275 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
13276 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
13277 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
13278 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
13279 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
13280 }
13281 }
Linux kernel - Deliverables
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