2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
);
45 static void intel_increase_pllclock(struct drm_crtc
*crtc
);
46 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
57 #define INTEL_P2_NUM 2
58 typedef struct intel_limit intel_limit_t
;
60 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
63 * find_pll() - Find the best values for the PLL
64 * @limit: limits for the PLL
66 * @target: target frequency in kHz
67 * @refclk: reference clock frequency in kHz
68 * @match_clock: if provided, @best_clock P divider must
69 * match the P divider from @match_clock
70 * used for LVDS downclocking
71 * @best_clock: best PLL values found
73 * Returns true on success, false on failure.
75 bool (*find_pll
)(const intel_limit_t
*limit
,
76 struct drm_crtc
*crtc
,
77 int target
, int refclk
,
78 intel_clock_t
*match_clock
,
79 intel_clock_t
*best_clock
);
83 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
86 intel_pch_rawclk(struct drm_device
*dev
)
88 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
90 WARN_ON(!HAS_PCH_SPLIT(dev
));
92 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
96 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
97 int target
, int refclk
, intel_clock_t
*match_clock
,
98 intel_clock_t
*best_clock
);
100 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
101 int target
, int refclk
, intel_clock_t
*match_clock
,
102 intel_clock_t
*best_clock
);
105 intel_find_pll_g4x_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
106 int target
, int refclk
, intel_clock_t
*match_clock
,
107 intel_clock_t
*best_clock
);
109 intel_find_pll_ironlake_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
110 int target
, int refclk
, intel_clock_t
*match_clock
,
111 intel_clock_t
*best_clock
);
114 intel_vlv_find_best_pll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
115 int target
, int refclk
, intel_clock_t
*match_clock
,
116 intel_clock_t
*best_clock
);
118 static inline u32
/* units of 100MHz */
119 intel_fdi_link_freq(struct drm_device
*dev
)
122 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
123 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
128 static const intel_limit_t intel_limits_i8xx_dvo
= {
129 .dot
= { .min
= 25000, .max
= 350000 },
130 .vco
= { .min
= 930000, .max
= 1400000 },
131 .n
= { .min
= 3, .max
= 16 },
132 .m
= { .min
= 96, .max
= 140 },
133 .m1
= { .min
= 18, .max
= 26 },
134 .m2
= { .min
= 6, .max
= 16 },
135 .p
= { .min
= 4, .max
= 128 },
136 .p1
= { .min
= 2, .max
= 33 },
137 .p2
= { .dot_limit
= 165000,
138 .p2_slow
= 4, .p2_fast
= 2 },
139 .find_pll
= intel_find_best_PLL
,
142 static const intel_limit_t intel_limits_i8xx_lvds
= {
143 .dot
= { .min
= 25000, .max
= 350000 },
144 .vco
= { .min
= 930000, .max
= 1400000 },
145 .n
= { .min
= 3, .max
= 16 },
146 .m
= { .min
= 96, .max
= 140 },
147 .m1
= { .min
= 18, .max
= 26 },
148 .m2
= { .min
= 6, .max
= 16 },
149 .p
= { .min
= 4, .max
= 128 },
150 .p1
= { .min
= 1, .max
= 6 },
151 .p2
= { .dot_limit
= 165000,
152 .p2_slow
= 14, .p2_fast
= 7 },
153 .find_pll
= intel_find_best_PLL
,
156 static const intel_limit_t intel_limits_i9xx_sdvo
= {
157 .dot
= { .min
= 20000, .max
= 400000 },
158 .vco
= { .min
= 1400000, .max
= 2800000 },
159 .n
= { .min
= 1, .max
= 6 },
160 .m
= { .min
= 70, .max
= 120 },
161 .m1
= { .min
= 8, .max
= 18 },
162 .m2
= { .min
= 3, .max
= 7 },
163 .p
= { .min
= 5, .max
= 80 },
164 .p1
= { .min
= 1, .max
= 8 },
165 .p2
= { .dot_limit
= 200000,
166 .p2_slow
= 10, .p2_fast
= 5 },
167 .find_pll
= intel_find_best_PLL
,
170 static const intel_limit_t intel_limits_i9xx_lvds
= {
171 .dot
= { .min
= 20000, .max
= 400000 },
172 .vco
= { .min
= 1400000, .max
= 2800000 },
173 .n
= { .min
= 1, .max
= 6 },
174 .m
= { .min
= 70, .max
= 120 },
175 .m1
= { .min
= 8, .max
= 18 },
176 .m2
= { .min
= 3, .max
= 7 },
177 .p
= { .min
= 7, .max
= 98 },
178 .p1
= { .min
= 1, .max
= 8 },
179 .p2
= { .dot_limit
= 112000,
180 .p2_slow
= 14, .p2_fast
= 7 },
181 .find_pll
= intel_find_best_PLL
,
185 static const intel_limit_t intel_limits_g4x_sdvo
= {
186 .dot
= { .min
= 25000, .max
= 270000 },
187 .vco
= { .min
= 1750000, .max
= 3500000},
188 .n
= { .min
= 1, .max
= 4 },
189 .m
= { .min
= 104, .max
= 138 },
190 .m1
= { .min
= 17, .max
= 23 },
191 .m2
= { .min
= 5, .max
= 11 },
192 .p
= { .min
= 10, .max
= 30 },
193 .p1
= { .min
= 1, .max
= 3},
194 .p2
= { .dot_limit
= 270000,
198 .find_pll
= intel_g4x_find_best_PLL
,
201 static const intel_limit_t intel_limits_g4x_hdmi
= {
202 .dot
= { .min
= 22000, .max
= 400000 },
203 .vco
= { .min
= 1750000, .max
= 3500000},
204 .n
= { .min
= 1, .max
= 4 },
205 .m
= { .min
= 104, .max
= 138 },
206 .m1
= { .min
= 16, .max
= 23 },
207 .m2
= { .min
= 5, .max
= 11 },
208 .p
= { .min
= 5, .max
= 80 },
209 .p1
= { .min
= 1, .max
= 8},
210 .p2
= { .dot_limit
= 165000,
211 .p2_slow
= 10, .p2_fast
= 5 },
212 .find_pll
= intel_g4x_find_best_PLL
,
215 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
216 .dot
= { .min
= 20000, .max
= 115000 },
217 .vco
= { .min
= 1750000, .max
= 3500000 },
218 .n
= { .min
= 1, .max
= 3 },
219 .m
= { .min
= 104, .max
= 138 },
220 .m1
= { .min
= 17, .max
= 23 },
221 .m2
= { .min
= 5, .max
= 11 },
222 .p
= { .min
= 28, .max
= 112 },
223 .p1
= { .min
= 2, .max
= 8 },
224 .p2
= { .dot_limit
= 0,
225 .p2_slow
= 14, .p2_fast
= 14
227 .find_pll
= intel_g4x_find_best_PLL
,
230 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
231 .dot
= { .min
= 80000, .max
= 224000 },
232 .vco
= { .min
= 1750000, .max
= 3500000 },
233 .n
= { .min
= 1, .max
= 3 },
234 .m
= { .min
= 104, .max
= 138 },
235 .m1
= { .min
= 17, .max
= 23 },
236 .m2
= { .min
= 5, .max
= 11 },
237 .p
= { .min
= 14, .max
= 42 },
238 .p1
= { .min
= 2, .max
= 6 },
239 .p2
= { .dot_limit
= 0,
240 .p2_slow
= 7, .p2_fast
= 7
242 .find_pll
= intel_g4x_find_best_PLL
,
245 static const intel_limit_t intel_limits_g4x_display_port
= {
246 .dot
= { .min
= 161670, .max
= 227000 },
247 .vco
= { .min
= 1750000, .max
= 3500000},
248 .n
= { .min
= 1, .max
= 2 },
249 .m
= { .min
= 97, .max
= 108 },
250 .m1
= { .min
= 0x10, .max
= 0x12 },
251 .m2
= { .min
= 0x05, .max
= 0x06 },
252 .p
= { .min
= 10, .max
= 20 },
253 .p1
= { .min
= 1, .max
= 2},
254 .p2
= { .dot_limit
= 0,
255 .p2_slow
= 10, .p2_fast
= 10 },
256 .find_pll
= intel_find_pll_g4x_dp
,
259 static const intel_limit_t intel_limits_pineview_sdvo
= {
260 .dot
= { .min
= 20000, .max
= 400000},
261 .vco
= { .min
= 1700000, .max
= 3500000 },
262 /* Pineview's Ncounter is a ring counter */
263 .n
= { .min
= 3, .max
= 6 },
264 .m
= { .min
= 2, .max
= 256 },
265 /* Pineview only has one combined m divider, which we treat as m2. */
266 .m1
= { .min
= 0, .max
= 0 },
267 .m2
= { .min
= 0, .max
= 254 },
268 .p
= { .min
= 5, .max
= 80 },
269 .p1
= { .min
= 1, .max
= 8 },
270 .p2
= { .dot_limit
= 200000,
271 .p2_slow
= 10, .p2_fast
= 5 },
272 .find_pll
= intel_find_best_PLL
,
275 static const intel_limit_t intel_limits_pineview_lvds
= {
276 .dot
= { .min
= 20000, .max
= 400000 },
277 .vco
= { .min
= 1700000, .max
= 3500000 },
278 .n
= { .min
= 3, .max
= 6 },
279 .m
= { .min
= 2, .max
= 256 },
280 .m1
= { .min
= 0, .max
= 0 },
281 .m2
= { .min
= 0, .max
= 254 },
282 .p
= { .min
= 7, .max
= 112 },
283 .p1
= { .min
= 1, .max
= 8 },
284 .p2
= { .dot_limit
= 112000,
285 .p2_slow
= 14, .p2_fast
= 14 },
286 .find_pll
= intel_find_best_PLL
,
289 /* Ironlake / Sandybridge
291 * We calculate clock using (register_value + 2) for N/M1/M2, so here
292 * the range value for them is (actual_value - 2).
294 static const intel_limit_t intel_limits_ironlake_dac
= {
295 .dot
= { .min
= 25000, .max
= 350000 },
296 .vco
= { .min
= 1760000, .max
= 3510000 },
297 .n
= { .min
= 1, .max
= 5 },
298 .m
= { .min
= 79, .max
= 127 },
299 .m1
= { .min
= 12, .max
= 22 },
300 .m2
= { .min
= 5, .max
= 9 },
301 .p
= { .min
= 5, .max
= 80 },
302 .p1
= { .min
= 1, .max
= 8 },
303 .p2
= { .dot_limit
= 225000,
304 .p2_slow
= 10, .p2_fast
= 5 },
305 .find_pll
= intel_g4x_find_best_PLL
,
308 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
309 .dot
= { .min
= 25000, .max
= 350000 },
310 .vco
= { .min
= 1760000, .max
= 3510000 },
311 .n
= { .min
= 1, .max
= 3 },
312 .m
= { .min
= 79, .max
= 118 },
313 .m1
= { .min
= 12, .max
= 22 },
314 .m2
= { .min
= 5, .max
= 9 },
315 .p
= { .min
= 28, .max
= 112 },
316 .p1
= { .min
= 2, .max
= 8 },
317 .p2
= { .dot_limit
= 225000,
318 .p2_slow
= 14, .p2_fast
= 14 },
319 .find_pll
= intel_g4x_find_best_PLL
,
322 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
323 .dot
= { .min
= 25000, .max
= 350000 },
324 .vco
= { .min
= 1760000, .max
= 3510000 },
325 .n
= { .min
= 1, .max
= 3 },
326 .m
= { .min
= 79, .max
= 127 },
327 .m1
= { .min
= 12, .max
= 22 },
328 .m2
= { .min
= 5, .max
= 9 },
329 .p
= { .min
= 14, .max
= 56 },
330 .p1
= { .min
= 2, .max
= 8 },
331 .p2
= { .dot_limit
= 225000,
332 .p2_slow
= 7, .p2_fast
= 7 },
333 .find_pll
= intel_g4x_find_best_PLL
,
336 /* LVDS 100mhz refclk limits. */
337 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
338 .dot
= { .min
= 25000, .max
= 350000 },
339 .vco
= { .min
= 1760000, .max
= 3510000 },
340 .n
= { .min
= 1, .max
= 2 },
341 .m
= { .min
= 79, .max
= 126 },
342 .m1
= { .min
= 12, .max
= 22 },
343 .m2
= { .min
= 5, .max
= 9 },
344 .p
= { .min
= 28, .max
= 112 },
345 .p1
= { .min
= 2, .max
= 8 },
346 .p2
= { .dot_limit
= 225000,
347 .p2_slow
= 14, .p2_fast
= 14 },
348 .find_pll
= intel_g4x_find_best_PLL
,
351 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
352 .dot
= { .min
= 25000, .max
= 350000 },
353 .vco
= { .min
= 1760000, .max
= 3510000 },
354 .n
= { .min
= 1, .max
= 3 },
355 .m
= { .min
= 79, .max
= 126 },
356 .m1
= { .min
= 12, .max
= 22 },
357 .m2
= { .min
= 5, .max
= 9 },
358 .p
= { .min
= 14, .max
= 42 },
359 .p1
= { .min
= 2, .max
= 6 },
360 .p2
= { .dot_limit
= 225000,
361 .p2_slow
= 7, .p2_fast
= 7 },
362 .find_pll
= intel_g4x_find_best_PLL
,
365 static const intel_limit_t intel_limits_ironlake_display_port
= {
366 .dot
= { .min
= 25000, .max
= 350000 },
367 .vco
= { .min
= 1760000, .max
= 3510000},
368 .n
= { .min
= 1, .max
= 2 },
369 .m
= { .min
= 81, .max
= 90 },
370 .m1
= { .min
= 12, .max
= 22 },
371 .m2
= { .min
= 5, .max
= 9 },
372 .p
= { .min
= 10, .max
= 20 },
373 .p1
= { .min
= 1, .max
= 2},
374 .p2
= { .dot_limit
= 0,
375 .p2_slow
= 10, .p2_fast
= 10 },
376 .find_pll
= intel_find_pll_ironlake_dp
,
379 static const intel_limit_t intel_limits_vlv_dac
= {
380 .dot
= { .min
= 25000, .max
= 270000 },
381 .vco
= { .min
= 4000000, .max
= 6000000 },
382 .n
= { .min
= 1, .max
= 7 },
383 .m
= { .min
= 22, .max
= 450 }, /* guess */
384 .m1
= { .min
= 2, .max
= 3 },
385 .m2
= { .min
= 11, .max
= 156 },
386 .p
= { .min
= 10, .max
= 30 },
387 .p1
= { .min
= 1, .max
= 3 },
388 .p2
= { .dot_limit
= 270000,
389 .p2_slow
= 2, .p2_fast
= 20 },
390 .find_pll
= intel_vlv_find_best_pll
,
393 static const intel_limit_t intel_limits_vlv_hdmi
= {
394 .dot
= { .min
= 25000, .max
= 270000 },
395 .vco
= { .min
= 4000000, .max
= 6000000 },
396 .n
= { .min
= 1, .max
= 7 },
397 .m
= { .min
= 60, .max
= 300 }, /* guess */
398 .m1
= { .min
= 2, .max
= 3 },
399 .m2
= { .min
= 11, .max
= 156 },
400 .p
= { .min
= 10, .max
= 30 },
401 .p1
= { .min
= 2, .max
= 3 },
402 .p2
= { .dot_limit
= 270000,
403 .p2_slow
= 2, .p2_fast
= 20 },
404 .find_pll
= intel_vlv_find_best_pll
,
407 static const intel_limit_t intel_limits_vlv_dp
= {
408 .dot
= { .min
= 25000, .max
= 270000 },
409 .vco
= { .min
= 4000000, .max
= 6000000 },
410 .n
= { .min
= 1, .max
= 7 },
411 .m
= { .min
= 22, .max
= 450 },
412 .m1
= { .min
= 2, .max
= 3 },
413 .m2
= { .min
= 11, .max
= 156 },
414 .p
= { .min
= 10, .max
= 30 },
415 .p1
= { .min
= 1, .max
= 3 },
416 .p2
= { .dot_limit
= 270000,
417 .p2_slow
= 2, .p2_fast
= 20 },
418 .find_pll
= intel_vlv_find_best_pll
,
421 u32
intel_dpio_read(struct drm_i915_private
*dev_priv
, int reg
)
423 WARN_ON(!mutex_is_locked(&dev_priv
->dpio_lock
));
425 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
426 DRM_ERROR("DPIO idle wait timed out\n");
430 I915_WRITE(DPIO_REG
, reg
);
431 I915_WRITE(DPIO_PKT
, DPIO_RID
| DPIO_OP_READ
| DPIO_PORTID
|
433 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
434 DRM_ERROR("DPIO read wait timed out\n");
438 return I915_READ(DPIO_DATA
);
441 void intel_dpio_write(struct drm_i915_private
*dev_priv
, int reg
, u32 val
)
443 WARN_ON(!mutex_is_locked(&dev_priv
->dpio_lock
));
445 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
446 DRM_ERROR("DPIO idle wait timed out\n");
450 I915_WRITE(DPIO_DATA
, val
);
451 I915_WRITE(DPIO_REG
, reg
);
452 I915_WRITE(DPIO_PKT
, DPIO_RID
| DPIO_OP_WRITE
| DPIO_PORTID
|
454 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100))
455 DRM_ERROR("DPIO write wait timed out\n");
458 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
,
461 struct drm_device
*dev
= crtc
->dev
;
462 const intel_limit_t
*limit
;
464 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
465 if (intel_is_dual_link_lvds(dev
)) {
466 if (refclk
== 100000)
467 limit
= &intel_limits_ironlake_dual_lvds_100m
;
469 limit
= &intel_limits_ironlake_dual_lvds
;
471 if (refclk
== 100000)
472 limit
= &intel_limits_ironlake_single_lvds_100m
;
474 limit
= &intel_limits_ironlake_single_lvds
;
476 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
477 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))
478 limit
= &intel_limits_ironlake_display_port
;
480 limit
= &intel_limits_ironlake_dac
;
485 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
487 struct drm_device
*dev
= crtc
->dev
;
488 const intel_limit_t
*limit
;
490 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
491 if (intel_is_dual_link_lvds(dev
))
492 limit
= &intel_limits_g4x_dual_channel_lvds
;
494 limit
= &intel_limits_g4x_single_channel_lvds
;
495 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
496 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
497 limit
= &intel_limits_g4x_hdmi
;
498 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
499 limit
= &intel_limits_g4x_sdvo
;
500 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
501 limit
= &intel_limits_g4x_display_port
;
502 } else /* The option is for other outputs */
503 limit
= &intel_limits_i9xx_sdvo
;
508 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
, int refclk
)
510 struct drm_device
*dev
= crtc
->dev
;
511 const intel_limit_t
*limit
;
513 if (HAS_PCH_SPLIT(dev
))
514 limit
= intel_ironlake_limit(crtc
, refclk
);
515 else if (IS_G4X(dev
)) {
516 limit
= intel_g4x_limit(crtc
);
517 } else if (IS_PINEVIEW(dev
)) {
518 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
519 limit
= &intel_limits_pineview_lvds
;
521 limit
= &intel_limits_pineview_sdvo
;
522 } else if (IS_VALLEYVIEW(dev
)) {
523 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
))
524 limit
= &intel_limits_vlv_dac
;
525 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
526 limit
= &intel_limits_vlv_hdmi
;
528 limit
= &intel_limits_vlv_dp
;
529 } else if (!IS_GEN2(dev
)) {
530 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
531 limit
= &intel_limits_i9xx_lvds
;
533 limit
= &intel_limits_i9xx_sdvo
;
535 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
536 limit
= &intel_limits_i8xx_lvds
;
538 limit
= &intel_limits_i8xx_dvo
;
543 /* m1 is reserved as 0 in Pineview, n is a ring counter */
544 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
546 clock
->m
= clock
->m2
+ 2;
547 clock
->p
= clock
->p1
* clock
->p2
;
548 clock
->vco
= refclk
* clock
->m
/ clock
->n
;
549 clock
->dot
= clock
->vco
/ clock
->p
;
552 static void intel_clock(struct drm_device
*dev
, int refclk
, intel_clock_t
*clock
)
554 if (IS_PINEVIEW(dev
)) {
555 pineview_clock(refclk
, clock
);
558 clock
->m
= 5 * (clock
->m1
+ 2) + (clock
->m2
+ 2);
559 clock
->p
= clock
->p1
* clock
->p2
;
560 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
561 clock
->dot
= clock
->vco
/ clock
->p
;
565 * Returns whether any output on the specified pipe is of the specified type
567 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
569 struct drm_device
*dev
= crtc
->dev
;
570 struct intel_encoder
*encoder
;
572 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
573 if (encoder
->type
== type
)
579 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
581 * Returns whether the given set of divisors are valid for a given refclk with
582 * the given connectors.
585 static bool intel_PLL_is_valid(struct drm_device
*dev
,
586 const intel_limit_t
*limit
,
587 const intel_clock_t
*clock
)
589 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
590 INTELPllInvalid("p1 out of range\n");
591 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
592 INTELPllInvalid("p out of range\n");
593 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
594 INTELPllInvalid("m2 out of range\n");
595 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
596 INTELPllInvalid("m1 out of range\n");
597 if (clock
->m1
<= clock
->m2
&& !IS_PINEVIEW(dev
))
598 INTELPllInvalid("m1 <= m2\n");
599 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
600 INTELPllInvalid("m out of range\n");
601 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
602 INTELPllInvalid("n out of range\n");
603 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
604 INTELPllInvalid("vco out of range\n");
605 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
606 * connector, etc., rather than just a single range.
608 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
609 INTELPllInvalid("dot out of range\n");
615 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
616 int target
, int refclk
, intel_clock_t
*match_clock
,
617 intel_clock_t
*best_clock
)
620 struct drm_device
*dev
= crtc
->dev
;
624 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
626 * For LVDS just rely on its current settings for dual-channel.
627 * We haven't figured out how to reliably set up different
628 * single/dual channel state, if we even can.
630 if (intel_is_dual_link_lvds(dev
))
631 clock
.p2
= limit
->p2
.p2_fast
;
633 clock
.p2
= limit
->p2
.p2_slow
;
635 if (target
< limit
->p2
.dot_limit
)
636 clock
.p2
= limit
->p2
.p2_slow
;
638 clock
.p2
= limit
->p2
.p2_fast
;
641 memset(best_clock
, 0, sizeof(*best_clock
));
643 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
645 for (clock
.m2
= limit
->m2
.min
;
646 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
647 /* m1 is always 0 in Pineview */
648 if (clock
.m2
>= clock
.m1
&& !IS_PINEVIEW(dev
))
650 for (clock
.n
= limit
->n
.min
;
651 clock
.n
<= limit
->n
.max
; clock
.n
++) {
652 for (clock
.p1
= limit
->p1
.min
;
653 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
656 intel_clock(dev
, refclk
, &clock
);
657 if (!intel_PLL_is_valid(dev
, limit
,
661 clock
.p
!= match_clock
->p
)
664 this_err
= abs(clock
.dot
- target
);
665 if (this_err
< err
) {
674 return (err
!= target
);
678 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
679 int target
, int refclk
, intel_clock_t
*match_clock
,
680 intel_clock_t
*best_clock
)
682 struct drm_device
*dev
= crtc
->dev
;
686 /* approximately equals target * 0.00585 */
687 int err_most
= (target
>> 8) + (target
>> 9);
690 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
693 if (HAS_PCH_SPLIT(dev
))
697 if (intel_is_dual_link_lvds(dev
))
698 clock
.p2
= limit
->p2
.p2_fast
;
700 clock
.p2
= limit
->p2
.p2_slow
;
702 if (target
< limit
->p2
.dot_limit
)
703 clock
.p2
= limit
->p2
.p2_slow
;
705 clock
.p2
= limit
->p2
.p2_fast
;
708 memset(best_clock
, 0, sizeof(*best_clock
));
709 max_n
= limit
->n
.max
;
710 /* based on hardware requirement, prefer smaller n to precision */
711 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
712 /* based on hardware requirement, prefere larger m1,m2 */
713 for (clock
.m1
= limit
->m1
.max
;
714 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
715 for (clock
.m2
= limit
->m2
.max
;
716 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
717 for (clock
.p1
= limit
->p1
.max
;
718 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
721 intel_clock(dev
, refclk
, &clock
);
722 if (!intel_PLL_is_valid(dev
, limit
,
726 clock
.p
!= match_clock
->p
)
729 this_err
= abs(clock
.dot
- target
);
730 if (this_err
< err_most
) {
744 intel_find_pll_ironlake_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
745 int target
, int refclk
, intel_clock_t
*match_clock
,
746 intel_clock_t
*best_clock
)
748 struct drm_device
*dev
= crtc
->dev
;
751 if (target
< 200000) {
764 intel_clock(dev
, refclk
, &clock
);
765 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
769 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
771 intel_find_pll_g4x_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
772 int target
, int refclk
, intel_clock_t
*match_clock
,
773 intel_clock_t
*best_clock
)
776 if (target
< 200000) {
789 clock
.m
= 5 * (clock
.m1
+ 2) + (clock
.m2
+ 2);
790 clock
.p
= (clock
.p1
* clock
.p2
);
791 clock
.dot
= 96000 * clock
.m
/ (clock
.n
+ 2) / clock
.p
;
793 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
797 intel_vlv_find_best_pll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
798 int target
, int refclk
, intel_clock_t
*match_clock
,
799 intel_clock_t
*best_clock
)
801 u32 p1
, p2
, m1
, m2
, vco
, bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
803 u32 updrate
, minupdate
, fracbits
, p
;
804 unsigned long bestppm
, ppm
, absppm
;
808 dotclk
= target
* 1000;
811 fastclk
= dotclk
/ (2*100);
815 n
= p
= p1
= p2
= m
= m1
= m2
= vco
= bestn
= 0;
816 bestm1
= bestm2
= bestp1
= bestp2
= 0;
818 /* based on hardware requirement, prefer smaller n to precision */
819 for (n
= limit
->n
.min
; n
<= ((refclk
) / minupdate
); n
++) {
820 updrate
= refclk
/ n
;
821 for (p1
= limit
->p1
.max
; p1
> limit
->p1
.min
; p1
--) {
822 for (p2
= limit
->p2
.p2_fast
+1; p2
> 0; p2
--) {
826 /* based on hardware requirement, prefer bigger m1,m2 values */
827 for (m1
= limit
->m1
.min
; m1
<= limit
->m1
.max
; m1
++) {
828 m2
= (((2*(fastclk
* p
* n
/ m1
)) +
829 refclk
) / (2*refclk
));
832 if (vco
>= limit
->vco
.min
&& vco
< limit
->vco
.max
) {
833 ppm
= 1000000 * ((vco
/ p
) - fastclk
) / fastclk
;
834 absppm
= (ppm
> 0) ? ppm
: (-ppm
);
835 if (absppm
< 100 && ((p1
* p2
) > (bestp1
* bestp2
))) {
839 if (absppm
< bestppm
- 10) {
856 best_clock
->n
= bestn
;
857 best_clock
->m1
= bestm1
;
858 best_clock
->m2
= bestm2
;
859 best_clock
->p1
= bestp1
;
860 best_clock
->p2
= bestp2
;
865 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
868 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
869 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
871 return intel_crtc
->config
.cpu_transcoder
;
874 static void ironlake_wait_for_vblank(struct drm_device
*dev
, int pipe
)
876 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
877 u32 frame
, frame_reg
= PIPEFRAME(pipe
);
879 frame
= I915_READ(frame_reg
);
881 if (wait_for(I915_READ_NOTRACE(frame_reg
) != frame
, 50))
882 DRM_DEBUG_KMS("vblank wait timed out\n");
886 * intel_wait_for_vblank - wait for vblank on a given pipe
888 * @pipe: pipe to wait for
890 * Wait for vblank to occur on a given pipe. Needed for various bits of
893 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
895 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
896 int pipestat_reg
= PIPESTAT(pipe
);
898 if (INTEL_INFO(dev
)->gen
>= 5) {
899 ironlake_wait_for_vblank(dev
, pipe
);
903 /* Clear existing vblank status. Note this will clear any other
904 * sticky status fields as well.
906 * This races with i915_driver_irq_handler() with the result
907 * that either function could miss a vblank event. Here it is not
908 * fatal, as we will either wait upon the next vblank interrupt or
909 * timeout. Generally speaking intel_wait_for_vblank() is only
910 * called during modeset at which time the GPU should be idle and
911 * should *not* be performing page flips and thus not waiting on
913 * Currently, the result of us stealing a vblank from the irq
914 * handler is that a single frame will be skipped during swapbuffers.
916 I915_WRITE(pipestat_reg
,
917 I915_READ(pipestat_reg
) | PIPE_VBLANK_INTERRUPT_STATUS
);
919 /* Wait for vblank interrupt bit to set */
920 if (wait_for(I915_READ(pipestat_reg
) &
921 PIPE_VBLANK_INTERRUPT_STATUS
,
923 DRM_DEBUG_KMS("vblank wait timed out\n");
927 * intel_wait_for_pipe_off - wait for pipe to turn off
929 * @pipe: pipe to wait for
931 * After disabling a pipe, we can't wait for vblank in the usual way,
932 * spinning on the vblank interrupt status bit, since we won't actually
933 * see an interrupt when the pipe is disabled.
936 * wait for the pipe register state bit to turn off
939 * wait for the display line value to settle (it usually
940 * ends up stopping at the start of the next frame).
943 void intel_wait_for_pipe_off(struct drm_device
*dev
, int pipe
)
945 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
946 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
949 if (INTEL_INFO(dev
)->gen
>= 4) {
950 int reg
= PIPECONF(cpu_transcoder
);
952 /* Wait for the Pipe State to go off */
953 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
955 WARN(1, "pipe_off wait timed out\n");
957 u32 last_line
, line_mask
;
958 int reg
= PIPEDSL(pipe
);
959 unsigned long timeout
= jiffies
+ msecs_to_jiffies(100);
962 line_mask
= DSL_LINEMASK_GEN2
;
964 line_mask
= DSL_LINEMASK_GEN3
;
966 /* Wait for the display line to settle */
968 last_line
= I915_READ(reg
) & line_mask
;
970 } while (((I915_READ(reg
) & line_mask
) != last_line
) &&
971 time_after(timeout
, jiffies
));
972 if (time_after(jiffies
, timeout
))
973 WARN(1, "pipe_off wait timed out\n");
978 * ibx_digital_port_connected - is the specified port connected?
979 * @dev_priv: i915 private structure
980 * @port: the port to test
982 * Returns true if @port is connected, false otherwise.
984 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
985 struct intel_digital_port
*port
)
989 if (HAS_PCH_IBX(dev_priv
->dev
)) {
992 bit
= SDE_PORTB_HOTPLUG
;
995 bit
= SDE_PORTC_HOTPLUG
;
998 bit
= SDE_PORTD_HOTPLUG
;
1004 switch(port
->port
) {
1006 bit
= SDE_PORTB_HOTPLUG_CPT
;
1009 bit
= SDE_PORTC_HOTPLUG_CPT
;
1012 bit
= SDE_PORTD_HOTPLUG_CPT
;
1019 return I915_READ(SDEISR
) & bit
;
1022 static const char *state_string(bool enabled
)
1024 return enabled
? "on" : "off";
1027 /* Only for pre-ILK configs */
1028 static void assert_pll(struct drm_i915_private
*dev_priv
,
1029 enum pipe pipe
, bool state
)
1036 val
= I915_READ(reg
);
1037 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1038 WARN(cur_state
!= state
,
1039 "PLL state assertion failure (expected %s, current %s)\n",
1040 state_string(state
), state_string(cur_state
));
1042 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1043 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1046 static void assert_pch_pll(struct drm_i915_private
*dev_priv
,
1047 struct intel_pch_pll
*pll
,
1048 struct intel_crtc
*crtc
,
1054 if (HAS_PCH_LPT(dev_priv
->dev
)) {
1055 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1060 "asserting PCH PLL %s with no PLL\n", state_string(state
)))
1063 val
= I915_READ(pll
->pll_reg
);
1064 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1065 WARN(cur_state
!= state
,
1066 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1067 pll
->pll_reg
, state_string(state
), state_string(cur_state
), val
);
1069 /* Make sure the selected PLL is correctly attached to the transcoder */
1070 if (crtc
&& HAS_PCH_CPT(dev_priv
->dev
)) {
1073 pch_dpll
= I915_READ(PCH_DPLL_SEL
);
1074 cur_state
= pll
->pll_reg
== _PCH_DPLL_B
;
1075 if (!WARN(((pch_dpll
>> (4 * crtc
->pipe
)) & 1) != cur_state
,
1076 "PLL[%d] not attached to this transcoder %c: %08x\n",
1077 cur_state
, pipe_name(crtc
->pipe
), pch_dpll
)) {
1078 cur_state
= !!(val
>> (4*crtc
->pipe
+ 3));
1079 WARN(cur_state
!= state
,
1080 "PLL[%d] not %s on this transcoder %c: %08x\n",
1081 pll
->pll_reg
== _PCH_DPLL_B
,
1082 state_string(state
),
1083 pipe_name(crtc
->pipe
),
1088 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1089 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1091 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1092 enum pipe pipe
, bool state
)
1097 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1100 if (HAS_DDI(dev_priv
->dev
)) {
1101 /* DDI does not have a specific FDI_TX register */
1102 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1103 val
= I915_READ(reg
);
1104 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1106 reg
= FDI_TX_CTL(pipe
);
1107 val
= I915_READ(reg
);
1108 cur_state
= !!(val
& FDI_TX_ENABLE
);
1110 WARN(cur_state
!= state
,
1111 "FDI TX state assertion failure (expected %s, current %s)\n",
1112 state_string(state
), state_string(cur_state
));
1114 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1115 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1117 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1118 enum pipe pipe
, bool state
)
1124 reg
= FDI_RX_CTL(pipe
);
1125 val
= I915_READ(reg
);
1126 cur_state
= !!(val
& FDI_RX_ENABLE
);
1127 WARN(cur_state
!= state
,
1128 "FDI RX state assertion failure (expected %s, current %s)\n",
1129 state_string(state
), state_string(cur_state
));
1131 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1132 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1134 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1140 /* ILK FDI PLL is always enabled */
1141 if (dev_priv
->info
->gen
== 5)
1144 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1145 if (HAS_DDI(dev_priv
->dev
))
1148 reg
= FDI_TX_CTL(pipe
);
1149 val
= I915_READ(reg
);
1150 WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1153 static void assert_fdi_rx_pll_enabled(struct drm_i915_private
*dev_priv
,
1159 reg
= FDI_RX_CTL(pipe
);
1160 val
= I915_READ(reg
);
1161 WARN(!(val
& FDI_RX_PLL_ENABLE
), "FDI RX PLL assertion failure, should be active but is disabled\n");
1164 static void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1167 int pp_reg
, lvds_reg
;
1169 enum pipe panel_pipe
= PIPE_A
;
1172 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
1173 pp_reg
= PCH_PP_CONTROL
;
1174 lvds_reg
= PCH_LVDS
;
1176 pp_reg
= PP_CONTROL
;
1180 val
= I915_READ(pp_reg
);
1181 if (!(val
& PANEL_POWER_ON
) ||
1182 ((val
& PANEL_UNLOCK_REGS
) == PANEL_UNLOCK_REGS
))
1185 if (I915_READ(lvds_reg
) & LVDS_PIPEB_SELECT
)
1186 panel_pipe
= PIPE_B
;
1188 WARN(panel_pipe
== pipe
&& locked
,
1189 "panel assertion failure, pipe %c regs locked\n",
1193 void assert_pipe(struct drm_i915_private
*dev_priv
,
1194 enum pipe pipe
, bool state
)
1199 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1202 /* if we need the pipe A quirk it must be always on */
1203 if (pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
1206 if (!intel_using_power_well(dev_priv
->dev
) &&
1207 cpu_transcoder
!= TRANSCODER_EDP
) {
1210 reg
= PIPECONF(cpu_transcoder
);
1211 val
= I915_READ(reg
);
1212 cur_state
= !!(val
& PIPECONF_ENABLE
);
1215 WARN(cur_state
!= state
,
1216 "pipe %c assertion failure (expected %s, current %s)\n",
1217 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1220 static void assert_plane(struct drm_i915_private
*dev_priv
,
1221 enum plane plane
, bool state
)
1227 reg
= DSPCNTR(plane
);
1228 val
= I915_READ(reg
);
1229 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1230 WARN(cur_state
!= state
,
1231 "plane %c assertion failure (expected %s, current %s)\n",
1232 plane_name(plane
), state_string(state
), state_string(cur_state
));
1235 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1236 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1238 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1245 /* Planes are fixed to pipes on ILK+ */
1246 if (HAS_PCH_SPLIT(dev_priv
->dev
) || IS_VALLEYVIEW(dev_priv
->dev
)) {
1247 reg
= DSPCNTR(pipe
);
1248 val
= I915_READ(reg
);
1249 WARN((val
& DISPLAY_PLANE_ENABLE
),
1250 "plane %c assertion failure, should be disabled but not\n",
1255 /* Need to check both planes against the pipe */
1256 for (i
= 0; i
< 2; i
++) {
1258 val
= I915_READ(reg
);
1259 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1260 DISPPLANE_SEL_PIPE_SHIFT
;
1261 WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1262 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1263 plane_name(i
), pipe_name(pipe
));
1267 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1273 if (!IS_VALLEYVIEW(dev_priv
->dev
))
1276 /* Need to check both planes against the pipe */
1277 for (i
= 0; i
< dev_priv
->num_plane
; i
++) {
1278 reg
= SPCNTR(pipe
, i
);
1279 val
= I915_READ(reg
);
1280 WARN((val
& SP_ENABLE
),
1281 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1282 sprite_name(pipe
, i
), pipe_name(pipe
));
1286 static void assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1291 if (HAS_PCH_LPT(dev_priv
->dev
)) {
1292 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1296 val
= I915_READ(PCH_DREF_CONTROL
);
1297 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1298 DREF_SUPERSPREAD_SOURCE_MASK
));
1299 WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1302 static void assert_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1309 reg
= TRANSCONF(pipe
);
1310 val
= I915_READ(reg
);
1311 enabled
= !!(val
& TRANS_ENABLE
);
1313 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1317 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1318 enum pipe pipe
, u32 port_sel
, u32 val
)
1320 if ((val
& DP_PORT_EN
) == 0)
1323 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1324 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1325 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1326 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1329 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1335 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1336 enum pipe pipe
, u32 val
)
1338 if ((val
& SDVO_ENABLE
) == 0)
1341 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1342 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1345 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1351 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1352 enum pipe pipe
, u32 val
)
1354 if ((val
& LVDS_PORT_EN
) == 0)
1357 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1358 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1361 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1367 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1368 enum pipe pipe
, u32 val
)
1370 if ((val
& ADPA_DAC_ENABLE
) == 0)
1372 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1373 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1376 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1382 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1383 enum pipe pipe
, int reg
, u32 port_sel
)
1385 u32 val
= I915_READ(reg
);
1386 WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1387 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1388 reg
, pipe_name(pipe
));
1390 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1391 && (val
& DP_PIPEB_SELECT
),
1392 "IBX PCH dp port still using transcoder B\n");
1395 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1396 enum pipe pipe
, int reg
)
1398 u32 val
= I915_READ(reg
);
1399 WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1400 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1401 reg
, pipe_name(pipe
));
1403 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_ENABLE
) == 0
1404 && (val
& SDVO_PIPE_B_SELECT
),
1405 "IBX PCH hdmi port still using transcoder B\n");
1408 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1414 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1415 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1416 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1419 val
= I915_READ(reg
);
1420 WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1421 "PCH VGA enabled on transcoder %c, should be disabled\n",
1425 val
= I915_READ(reg
);
1426 WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1427 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1430 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1431 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1432 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1436 * intel_enable_pll - enable a PLL
1437 * @dev_priv: i915 private structure
1438 * @pipe: pipe PLL to enable
1440 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1441 * make sure the PLL reg is writable first though, since the panel write
1442 * protect mechanism may be enabled.
1444 * Note! This is for pre-ILK only.
1446 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1448 static void intel_enable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1453 assert_pipe_disabled(dev_priv
, pipe
);
1455 /* No really, not for ILK+ */
1456 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
) && dev_priv
->info
->gen
>= 5);
1458 /* PLL is protected by panel, make sure we can write it */
1459 if (IS_MOBILE(dev_priv
->dev
) && !IS_I830(dev_priv
->dev
))
1460 assert_panel_unlocked(dev_priv
, pipe
);
1463 val
= I915_READ(reg
);
1464 val
|= DPLL_VCO_ENABLE
;
1466 /* We do this three times for luck */
1467 I915_WRITE(reg
, val
);
1469 udelay(150); /* wait for warmup */
1470 I915_WRITE(reg
, val
);
1472 udelay(150); /* wait for warmup */
1473 I915_WRITE(reg
, val
);
1475 udelay(150); /* wait for warmup */
1479 * intel_disable_pll - disable a PLL
1480 * @dev_priv: i915 private structure
1481 * @pipe: pipe PLL to disable
1483 * Disable the PLL for @pipe, making sure the pipe is off first.
1485 * Note! This is for pre-ILK only.
1487 static void intel_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1492 /* Don't disable pipe A or pipe A PLLs if needed */
1493 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1496 /* Make sure the pipe isn't still relying on us */
1497 assert_pipe_disabled(dev_priv
, pipe
);
1500 val
= I915_READ(reg
);
1501 val
&= ~DPLL_VCO_ENABLE
;
1502 I915_WRITE(reg
, val
);
1508 intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
1509 enum intel_sbi_destination destination
)
1513 WARN_ON(!mutex_is_locked(&dev_priv
->dpio_lock
));
1515 if (wait_for((I915_READ(SBI_CTL_STAT
) & SBI_BUSY
) == 0,
1517 DRM_ERROR("timeout waiting for SBI to become ready\n");
1521 I915_WRITE(SBI_ADDR
, (reg
<< 16));
1522 I915_WRITE(SBI_DATA
, value
);
1524 if (destination
== SBI_ICLK
)
1525 tmp
= SBI_CTL_DEST_ICLK
| SBI_CTL_OP_CRWR
;
1527 tmp
= SBI_CTL_DEST_MPHY
| SBI_CTL_OP_IOWR
;
1528 I915_WRITE(SBI_CTL_STAT
, SBI_BUSY
| tmp
);
1530 if (wait_for((I915_READ(SBI_CTL_STAT
) & (SBI_BUSY
| SBI_RESPONSE_FAIL
)) == 0,
1532 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1538 intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
1539 enum intel_sbi_destination destination
)
1542 WARN_ON(!mutex_is_locked(&dev_priv
->dpio_lock
));
1544 if (wait_for((I915_READ(SBI_CTL_STAT
) & SBI_BUSY
) == 0,
1546 DRM_ERROR("timeout waiting for SBI to become ready\n");
1550 I915_WRITE(SBI_ADDR
, (reg
<< 16));
1552 if (destination
== SBI_ICLK
)
1553 value
= SBI_CTL_DEST_ICLK
| SBI_CTL_OP_CRRD
;
1555 value
= SBI_CTL_DEST_MPHY
| SBI_CTL_OP_IORD
;
1556 I915_WRITE(SBI_CTL_STAT
, value
| SBI_BUSY
);
1558 if (wait_for((I915_READ(SBI_CTL_STAT
) & (SBI_BUSY
| SBI_RESPONSE_FAIL
)) == 0,
1560 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1564 return I915_READ(SBI_DATA
);
1567 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
, int port
)
1572 port_mask
= DPLL_PORTB_READY_MASK
;
1574 port_mask
= DPLL_PORTC_READY_MASK
;
1576 if (wait_for((I915_READ(DPLL(0)) & port_mask
) == 0, 1000))
1577 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1578 'B' + port
, I915_READ(DPLL(0)));
1582 * ironlake_enable_pch_pll - enable PCH PLL
1583 * @dev_priv: i915 private structure
1584 * @pipe: pipe PLL to enable
1586 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1587 * drives the transcoder clock.
1589 static void ironlake_enable_pch_pll(struct intel_crtc
*intel_crtc
)
1591 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
1592 struct intel_pch_pll
*pll
;
1596 /* PCH PLLs only available on ILK, SNB and IVB */
1597 BUG_ON(dev_priv
->info
->gen
< 5);
1598 pll
= intel_crtc
->pch_pll
;
1602 if (WARN_ON(pll
->refcount
== 0))
1605 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1606 pll
->pll_reg
, pll
->active
, pll
->on
,
1607 intel_crtc
->base
.base
.id
);
1609 /* PCH refclock must be enabled first */
1610 assert_pch_refclk_enabled(dev_priv
);
1612 if (pll
->active
++ && pll
->on
) {
1613 assert_pch_pll_enabled(dev_priv
, pll
, NULL
);
1617 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll
->pll_reg
);
1620 val
= I915_READ(reg
);
1621 val
|= DPLL_VCO_ENABLE
;
1622 I915_WRITE(reg
, val
);
1629 static void intel_disable_pch_pll(struct intel_crtc
*intel_crtc
)
1631 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
1632 struct intel_pch_pll
*pll
= intel_crtc
->pch_pll
;
1636 /* PCH only available on ILK+ */
1637 BUG_ON(dev_priv
->info
->gen
< 5);
1641 if (WARN_ON(pll
->refcount
== 0))
1644 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1645 pll
->pll_reg
, pll
->active
, pll
->on
,
1646 intel_crtc
->base
.base
.id
);
1648 if (WARN_ON(pll
->active
== 0)) {
1649 assert_pch_pll_disabled(dev_priv
, pll
, NULL
);
1653 if (--pll
->active
) {
1654 assert_pch_pll_enabled(dev_priv
, pll
, NULL
);
1658 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll
->pll_reg
);
1660 /* Make sure transcoder isn't still depending on us */
1661 assert_transcoder_disabled(dev_priv
, intel_crtc
->pipe
);
1664 val
= I915_READ(reg
);
1665 val
&= ~DPLL_VCO_ENABLE
;
1666 I915_WRITE(reg
, val
);
1673 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1676 struct drm_device
*dev
= dev_priv
->dev
;
1677 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1678 uint32_t reg
, val
, pipeconf_val
;
1680 /* PCH only available on ILK+ */
1681 BUG_ON(dev_priv
->info
->gen
< 5);
1683 /* Make sure PCH DPLL is enabled */
1684 assert_pch_pll_enabled(dev_priv
,
1685 to_intel_crtc(crtc
)->pch_pll
,
1686 to_intel_crtc(crtc
));
1688 /* FDI must be feeding us bits for PCH ports */
1689 assert_fdi_tx_enabled(dev_priv
, pipe
);
1690 assert_fdi_rx_enabled(dev_priv
, pipe
);
1692 if (HAS_PCH_CPT(dev
)) {
1693 /* Workaround: Set the timing override bit before enabling the
1694 * pch transcoder. */
1695 reg
= TRANS_CHICKEN2(pipe
);
1696 val
= I915_READ(reg
);
1697 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1698 I915_WRITE(reg
, val
);
1701 reg
= TRANSCONF(pipe
);
1702 val
= I915_READ(reg
);
1703 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1705 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1707 * make the BPC in transcoder be consistent with
1708 * that in pipeconf reg.
1710 val
&= ~PIPECONF_BPC_MASK
;
1711 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1714 val
&= ~TRANS_INTERLACE_MASK
;
1715 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1716 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1717 intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
))
1718 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1720 val
|= TRANS_INTERLACED
;
1722 val
|= TRANS_PROGRESSIVE
;
1724 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1725 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1726 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
1729 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1730 enum transcoder cpu_transcoder
)
1732 u32 val
, pipeconf_val
;
1734 /* PCH only available on ILK+ */
1735 BUG_ON(dev_priv
->info
->gen
< 5);
1737 /* FDI must be feeding us bits for PCH ports */
1738 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1739 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
1741 /* Workaround: set timing override bit. */
1742 val
= I915_READ(_TRANSA_CHICKEN2
);
1743 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1744 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1747 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1749 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1750 PIPECONF_INTERLACED_ILK
)
1751 val
|= TRANS_INTERLACED
;
1753 val
|= TRANS_PROGRESSIVE
;
1755 I915_WRITE(TRANSCONF(TRANSCODER_A
), val
);
1756 if (wait_for(I915_READ(_TRANSACONF
) & TRANS_STATE_ENABLE
, 100))
1757 DRM_ERROR("Failed to enable PCH transcoder\n");
1760 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1763 struct drm_device
*dev
= dev_priv
->dev
;
1766 /* FDI relies on the transcoder */
1767 assert_fdi_tx_disabled(dev_priv
, pipe
);
1768 assert_fdi_rx_disabled(dev_priv
, pipe
);
1770 /* Ports must be off as well */
1771 assert_pch_ports_disabled(dev_priv
, pipe
);
1773 reg
= TRANSCONF(pipe
);
1774 val
= I915_READ(reg
);
1775 val
&= ~TRANS_ENABLE
;
1776 I915_WRITE(reg
, val
);
1777 /* wait for PCH transcoder off, transcoder state */
1778 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1779 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
1781 if (!HAS_PCH_IBX(dev
)) {
1782 /* Workaround: Clear the timing override chicken bit again. */
1783 reg
= TRANS_CHICKEN2(pipe
);
1784 val
= I915_READ(reg
);
1785 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1786 I915_WRITE(reg
, val
);
1790 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1794 val
= I915_READ(_TRANSACONF
);
1795 val
&= ~TRANS_ENABLE
;
1796 I915_WRITE(_TRANSACONF
, val
);
1797 /* wait for PCH transcoder off, transcoder state */
1798 if (wait_for((I915_READ(_TRANSACONF
) & TRANS_STATE_ENABLE
) == 0, 50))
1799 DRM_ERROR("Failed to disable PCH transcoder\n");
1801 /* Workaround: clear timing override bit. */
1802 val
= I915_READ(_TRANSA_CHICKEN2
);
1803 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1804 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1808 * intel_enable_pipe - enable a pipe, asserting requirements
1809 * @dev_priv: i915 private structure
1810 * @pipe: pipe to enable
1811 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1813 * Enable @pipe, making sure that various hardware specific requirements
1814 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1816 * @pipe should be %PIPE_A or %PIPE_B.
1818 * Will wait until the pipe is actually running (i.e. first vblank) before
1821 static void intel_enable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
1824 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1826 enum pipe pch_transcoder
;
1830 assert_planes_disabled(dev_priv
, pipe
);
1831 assert_sprites_disabled(dev_priv
, pipe
);
1833 if (HAS_PCH_LPT(dev_priv
->dev
))
1834 pch_transcoder
= TRANSCODER_A
;
1836 pch_transcoder
= pipe
;
1839 * A pipe without a PLL won't actually be able to drive bits from
1840 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1843 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
1844 assert_pll_enabled(dev_priv
, pipe
);
1847 /* if driving the PCH, we need FDI enabled */
1848 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
1849 assert_fdi_tx_pll_enabled(dev_priv
,
1850 (enum pipe
) cpu_transcoder
);
1852 /* FIXME: assert CPU port conditions for SNB+ */
1855 reg
= PIPECONF(cpu_transcoder
);
1856 val
= I915_READ(reg
);
1857 if (val
& PIPECONF_ENABLE
)
1860 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
1861 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1865 * intel_disable_pipe - disable a pipe, asserting requirements
1866 * @dev_priv: i915 private structure
1867 * @pipe: pipe to disable
1869 * Disable @pipe, making sure that various hardware specific requirements
1870 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1872 * @pipe should be %PIPE_A or %PIPE_B.
1874 * Will wait until the pipe has shut down before returning.
1876 static void intel_disable_pipe(struct drm_i915_private
*dev_priv
,
1879 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1885 * Make sure planes won't keep trying to pump pixels to us,
1886 * or we might hang the display.
1888 assert_planes_disabled(dev_priv
, pipe
);
1889 assert_sprites_disabled(dev_priv
, pipe
);
1891 /* Don't disable pipe A or pipe A PLLs if needed */
1892 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1895 reg
= PIPECONF(cpu_transcoder
);
1896 val
= I915_READ(reg
);
1897 if ((val
& PIPECONF_ENABLE
) == 0)
1900 I915_WRITE(reg
, val
& ~PIPECONF_ENABLE
);
1901 intel_wait_for_pipe_off(dev_priv
->dev
, pipe
);
1905 * Plane regs are double buffered, going from enabled->disabled needs a
1906 * trigger in order to latch. The display address reg provides this.
1908 void intel_flush_display_plane(struct drm_i915_private
*dev_priv
,
1911 if (dev_priv
->info
->gen
>= 4)
1912 I915_WRITE(DSPSURF(plane
), I915_READ(DSPSURF(plane
)));
1914 I915_WRITE(DSPADDR(plane
), I915_READ(DSPADDR(plane
)));
1918 * intel_enable_plane - enable a display plane on a given pipe
1919 * @dev_priv: i915 private structure
1920 * @plane: plane to enable
1921 * @pipe: pipe being fed
1923 * Enable @plane on @pipe, making sure that @pipe is running first.
1925 static void intel_enable_plane(struct drm_i915_private
*dev_priv
,
1926 enum plane plane
, enum pipe pipe
)
1931 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1932 assert_pipe_enabled(dev_priv
, pipe
);
1934 reg
= DSPCNTR(plane
);
1935 val
= I915_READ(reg
);
1936 if (val
& DISPLAY_PLANE_ENABLE
)
1939 I915_WRITE(reg
, val
| DISPLAY_PLANE_ENABLE
);
1940 intel_flush_display_plane(dev_priv
, plane
);
1941 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1945 * intel_disable_plane - disable a display plane
1946 * @dev_priv: i915 private structure
1947 * @plane: plane to disable
1948 * @pipe: pipe consuming the data
1950 * Disable @plane; should be an independent operation.
1952 static void intel_disable_plane(struct drm_i915_private
*dev_priv
,
1953 enum plane plane
, enum pipe pipe
)
1958 reg
= DSPCNTR(plane
);
1959 val
= I915_READ(reg
);
1960 if ((val
& DISPLAY_PLANE_ENABLE
) == 0)
1963 I915_WRITE(reg
, val
& ~DISPLAY_PLANE_ENABLE
);
1964 intel_flush_display_plane(dev_priv
, plane
);
1965 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1968 static bool need_vtd_wa(struct drm_device
*dev
)
1970 #ifdef CONFIG_INTEL_IOMMU
1971 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
1978 intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
1979 struct drm_i915_gem_object
*obj
,
1980 struct intel_ring_buffer
*pipelined
)
1982 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1986 switch (obj
->tiling_mode
) {
1987 case I915_TILING_NONE
:
1988 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
1989 alignment
= 128 * 1024;
1990 else if (INTEL_INFO(dev
)->gen
>= 4)
1991 alignment
= 4 * 1024;
1993 alignment
= 64 * 1024;
1996 /* pin() will align the object as required by fence */
2000 /* Despite that we check this in framebuffer_init userspace can
2001 * screw us over and change the tiling after the fact. Only
2002 * pinned buffers can't change their tiling. */
2003 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
2009 /* Note that the w/a also requires 64 PTE of padding following the
2010 * bo. We currently fill all unused PTE with the shadow page and so
2011 * we should always have valid PTE following the scanout preventing
2014 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
2015 alignment
= 256 * 1024;
2017 dev_priv
->mm
.interruptible
= false;
2018 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
);
2020 goto err_interruptible
;
2022 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2023 * fence, whereas 965+ only requires a fence if using
2024 * framebuffer compression. For simplicity, we always install
2025 * a fence as the cost is not that onerous.
2027 ret
= i915_gem_object_get_fence(obj
);
2031 i915_gem_object_pin_fence(obj
);
2033 dev_priv
->mm
.interruptible
= true;
2037 i915_gem_object_unpin(obj
);
2039 dev_priv
->mm
.interruptible
= true;
2043 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
)
2045 i915_gem_object_unpin_fence(obj
);
2046 i915_gem_object_unpin(obj
);
2049 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2050 * is assumed to be a power-of-two. */
2051 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
2052 unsigned int tiling_mode
,
2056 if (tiling_mode
!= I915_TILING_NONE
) {
2057 unsigned int tile_rows
, tiles
;
2062 tiles
= *x
/ (512/cpp
);
2065 return tile_rows
* pitch
* 8 + tiles
* 4096;
2067 unsigned int offset
;
2069 offset
= *y
* pitch
+ *x
* cpp
;
2071 *x
= (offset
& 4095) / cpp
;
2072 return offset
& -4096;
2076 static int i9xx_update_plane(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2079 struct drm_device
*dev
= crtc
->dev
;
2080 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2081 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2082 struct intel_framebuffer
*intel_fb
;
2083 struct drm_i915_gem_object
*obj
;
2084 int plane
= intel_crtc
->plane
;
2085 unsigned long linear_offset
;
2094 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane
));
2098 intel_fb
= to_intel_framebuffer(fb
);
2099 obj
= intel_fb
->obj
;
2101 reg
= DSPCNTR(plane
);
2102 dspcntr
= I915_READ(reg
);
2103 /* Mask out pixel format bits in case we change it */
2104 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2105 switch (fb
->pixel_format
) {
2107 dspcntr
|= DISPPLANE_8BPP
;
2109 case DRM_FORMAT_XRGB1555
:
2110 case DRM_FORMAT_ARGB1555
:
2111 dspcntr
|= DISPPLANE_BGRX555
;
2113 case DRM_FORMAT_RGB565
:
2114 dspcntr
|= DISPPLANE_BGRX565
;
2116 case DRM_FORMAT_XRGB8888
:
2117 case DRM_FORMAT_ARGB8888
:
2118 dspcntr
|= DISPPLANE_BGRX888
;
2120 case DRM_FORMAT_XBGR8888
:
2121 case DRM_FORMAT_ABGR8888
:
2122 dspcntr
|= DISPPLANE_RGBX888
;
2124 case DRM_FORMAT_XRGB2101010
:
2125 case DRM_FORMAT_ARGB2101010
:
2126 dspcntr
|= DISPPLANE_BGRX101010
;
2128 case DRM_FORMAT_XBGR2101010
:
2129 case DRM_FORMAT_ABGR2101010
:
2130 dspcntr
|= DISPPLANE_RGBX101010
;
2136 if (INTEL_INFO(dev
)->gen
>= 4) {
2137 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2138 dspcntr
|= DISPPLANE_TILED
;
2140 dspcntr
&= ~DISPPLANE_TILED
;
2143 I915_WRITE(reg
, dspcntr
);
2145 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2147 if (INTEL_INFO(dev
)->gen
>= 4) {
2148 intel_crtc
->dspaddr_offset
=
2149 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2150 fb
->bits_per_pixel
/ 8,
2152 linear_offset
-= intel_crtc
->dspaddr_offset
;
2154 intel_crtc
->dspaddr_offset
= linear_offset
;
2157 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2158 obj
->gtt_offset
, linear_offset
, x
, y
, fb
->pitches
[0]);
2159 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2160 if (INTEL_INFO(dev
)->gen
>= 4) {
2161 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2162 obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
2163 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2164 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2166 I915_WRITE(DSPADDR(plane
), obj
->gtt_offset
+ linear_offset
);
2172 static int ironlake_update_plane(struct drm_crtc
*crtc
,
2173 struct drm_framebuffer
*fb
, int x
, int y
)
2175 struct drm_device
*dev
= crtc
->dev
;
2176 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2177 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2178 struct intel_framebuffer
*intel_fb
;
2179 struct drm_i915_gem_object
*obj
;
2180 int plane
= intel_crtc
->plane
;
2181 unsigned long linear_offset
;
2191 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane
));
2195 intel_fb
= to_intel_framebuffer(fb
);
2196 obj
= intel_fb
->obj
;
2198 reg
= DSPCNTR(plane
);
2199 dspcntr
= I915_READ(reg
);
2200 /* Mask out pixel format bits in case we change it */
2201 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2202 switch (fb
->pixel_format
) {
2204 dspcntr
|= DISPPLANE_8BPP
;
2206 case DRM_FORMAT_RGB565
:
2207 dspcntr
|= DISPPLANE_BGRX565
;
2209 case DRM_FORMAT_XRGB8888
:
2210 case DRM_FORMAT_ARGB8888
:
2211 dspcntr
|= DISPPLANE_BGRX888
;
2213 case DRM_FORMAT_XBGR8888
:
2214 case DRM_FORMAT_ABGR8888
:
2215 dspcntr
|= DISPPLANE_RGBX888
;
2217 case DRM_FORMAT_XRGB2101010
:
2218 case DRM_FORMAT_ARGB2101010
:
2219 dspcntr
|= DISPPLANE_BGRX101010
;
2221 case DRM_FORMAT_XBGR2101010
:
2222 case DRM_FORMAT_ABGR2101010
:
2223 dspcntr
|= DISPPLANE_RGBX101010
;
2229 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2230 dspcntr
|= DISPPLANE_TILED
;
2232 dspcntr
&= ~DISPPLANE_TILED
;
2235 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2237 I915_WRITE(reg
, dspcntr
);
2239 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2240 intel_crtc
->dspaddr_offset
=
2241 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2242 fb
->bits_per_pixel
/ 8,
2244 linear_offset
-= intel_crtc
->dspaddr_offset
;
2246 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2247 obj
->gtt_offset
, linear_offset
, x
, y
, fb
->pitches
[0]);
2248 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2249 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2250 obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
2251 if (IS_HASWELL(dev
)) {
2252 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2254 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2255 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2262 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2264 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2265 int x
, int y
, enum mode_set_atomic state
)
2267 struct drm_device
*dev
= crtc
->dev
;
2268 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2270 if (dev_priv
->display
.disable_fbc
)
2271 dev_priv
->display
.disable_fbc(dev
);
2272 intel_increase_pllclock(crtc
);
2274 return dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2277 void intel_display_handle_reset(struct drm_device
*dev
)
2279 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2280 struct drm_crtc
*crtc
;
2283 * Flips in the rings have been nuked by the reset,
2284 * so complete all pending flips so that user space
2285 * will get its events and not get stuck.
2287 * Also update the base address of all primary
2288 * planes to the the last fb to make sure we're
2289 * showing the correct fb after a reset.
2291 * Need to make two loops over the crtcs so that we
2292 * don't try to grab a crtc mutex before the
2293 * pending_flip_queue really got woken up.
2296 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2297 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2298 enum plane plane
= intel_crtc
->plane
;
2300 intel_prepare_page_flip(dev
, plane
);
2301 intel_finish_page_flip_plane(dev
, plane
);
2304 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2305 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2307 mutex_lock(&crtc
->mutex
);
2308 if (intel_crtc
->active
)
2309 dev_priv
->display
.update_plane(crtc
, crtc
->fb
,
2311 mutex_unlock(&crtc
->mutex
);
2316 intel_finish_fb(struct drm_framebuffer
*old_fb
)
2318 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(old_fb
)->obj
;
2319 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2320 bool was_interruptible
= dev_priv
->mm
.interruptible
;
2323 /* Big Hammer, we also need to ensure that any pending
2324 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2325 * current scanout is retired before unpinning the old
2328 * This should only fail upon a hung GPU, in which case we
2329 * can safely continue.
2331 dev_priv
->mm
.interruptible
= false;
2332 ret
= i915_gem_object_finish_gpu(obj
);
2333 dev_priv
->mm
.interruptible
= was_interruptible
;
2338 static void intel_crtc_update_sarea_pos(struct drm_crtc
*crtc
, int x
, int y
)
2340 struct drm_device
*dev
= crtc
->dev
;
2341 struct drm_i915_master_private
*master_priv
;
2342 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2344 if (!dev
->primary
->master
)
2347 master_priv
= dev
->primary
->master
->driver_priv
;
2348 if (!master_priv
->sarea_priv
)
2351 switch (intel_crtc
->pipe
) {
2353 master_priv
->sarea_priv
->pipeA_x
= x
;
2354 master_priv
->sarea_priv
->pipeA_y
= y
;
2357 master_priv
->sarea_priv
->pipeB_x
= x
;
2358 master_priv
->sarea_priv
->pipeB_y
= y
;
2366 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2367 struct drm_framebuffer
*fb
)
2369 struct drm_device
*dev
= crtc
->dev
;
2370 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2371 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2372 struct drm_framebuffer
*old_fb
;
2377 DRM_ERROR("No FB bound\n");
2381 if (intel_crtc
->plane
> INTEL_INFO(dev
)->num_pipes
) {
2382 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2383 plane_name(intel_crtc
->plane
),
2384 INTEL_INFO(dev
)->num_pipes
);
2388 mutex_lock(&dev
->struct_mutex
);
2389 ret
= intel_pin_and_fence_fb_obj(dev
,
2390 to_intel_framebuffer(fb
)->obj
,
2393 mutex_unlock(&dev
->struct_mutex
);
2394 DRM_ERROR("pin & fence failed\n");
2398 ret
= dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2400 intel_unpin_fb_obj(to_intel_framebuffer(fb
)->obj
);
2401 mutex_unlock(&dev
->struct_mutex
);
2402 DRM_ERROR("failed to update base address\n");
2412 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2413 intel_unpin_fb_obj(to_intel_framebuffer(old_fb
)->obj
);
2416 intel_update_fbc(dev
);
2417 mutex_unlock(&dev
->struct_mutex
);
2419 intel_crtc_update_sarea_pos(crtc
, x
, y
);
2424 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
2426 struct drm_device
*dev
= crtc
->dev
;
2427 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2428 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2429 int pipe
= intel_crtc
->pipe
;
2432 /* enable normal train */
2433 reg
= FDI_TX_CTL(pipe
);
2434 temp
= I915_READ(reg
);
2435 if (IS_IVYBRIDGE(dev
)) {
2436 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2437 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2439 temp
&= ~FDI_LINK_TRAIN_NONE
;
2440 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2442 I915_WRITE(reg
, temp
);
2444 reg
= FDI_RX_CTL(pipe
);
2445 temp
= I915_READ(reg
);
2446 if (HAS_PCH_CPT(dev
)) {
2447 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2448 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2450 temp
&= ~FDI_LINK_TRAIN_NONE
;
2451 temp
|= FDI_LINK_TRAIN_NONE
;
2453 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2455 /* wait one idle pattern time */
2459 /* IVB wants error correction enabled */
2460 if (IS_IVYBRIDGE(dev
))
2461 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
2462 FDI_FE_ERRC_ENABLE
);
2465 static void ivb_modeset_global_resources(struct drm_device
*dev
)
2467 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2468 struct intel_crtc
*pipe_B_crtc
=
2469 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
2470 struct intel_crtc
*pipe_C_crtc
=
2471 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]);
2474 /* When everything is off disable fdi C so that we could enable fdi B
2475 * with all lanes. XXX: This misses the case where a pipe is not using
2476 * any pch resources and so doesn't need any fdi lanes. */
2477 if (!pipe_B_crtc
->base
.enabled
&& !pipe_C_crtc
->base
.enabled
) {
2478 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
2479 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
2481 temp
= I915_READ(SOUTH_CHICKEN1
);
2482 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
2483 DRM_DEBUG_KMS("disabling fdi C rx\n");
2484 I915_WRITE(SOUTH_CHICKEN1
, temp
);
2488 /* The FDI link training functions for ILK/Ibexpeak. */
2489 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
2491 struct drm_device
*dev
= crtc
->dev
;
2492 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2493 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2494 int pipe
= intel_crtc
->pipe
;
2495 int plane
= intel_crtc
->plane
;
2496 u32 reg
, temp
, tries
;
2498 /* FDI needs bits from pipe & plane first */
2499 assert_pipe_enabled(dev_priv
, pipe
);
2500 assert_plane_enabled(dev_priv
, plane
);
2502 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2504 reg
= FDI_RX_IMR(pipe
);
2505 temp
= I915_READ(reg
);
2506 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2507 temp
&= ~FDI_RX_BIT_LOCK
;
2508 I915_WRITE(reg
, temp
);
2512 /* enable CPU FDI TX and PCH FDI RX */
2513 reg
= FDI_TX_CTL(pipe
);
2514 temp
= I915_READ(reg
);
2516 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2517 temp
&= ~FDI_LINK_TRAIN_NONE
;
2518 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2519 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2521 reg
= FDI_RX_CTL(pipe
);
2522 temp
= I915_READ(reg
);
2523 temp
&= ~FDI_LINK_TRAIN_NONE
;
2524 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2525 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2530 /* Ironlake workaround, enable clock pointer after FDI enable*/
2531 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2532 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
2533 FDI_RX_PHASE_SYNC_POINTER_EN
);
2535 reg
= FDI_RX_IIR(pipe
);
2536 for (tries
= 0; tries
< 5; tries
++) {
2537 temp
= I915_READ(reg
);
2538 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2540 if ((temp
& FDI_RX_BIT_LOCK
)) {
2541 DRM_DEBUG_KMS("FDI train 1 done.\n");
2542 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2547 DRM_ERROR("FDI train 1 fail!\n");
2550 reg
= FDI_TX_CTL(pipe
);
2551 temp
= I915_READ(reg
);
2552 temp
&= ~FDI_LINK_TRAIN_NONE
;
2553 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2554 I915_WRITE(reg
, temp
);
2556 reg
= FDI_RX_CTL(pipe
);
2557 temp
= I915_READ(reg
);
2558 temp
&= ~FDI_LINK_TRAIN_NONE
;
2559 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2560 I915_WRITE(reg
, temp
);
2565 reg
= FDI_RX_IIR(pipe
);
2566 for (tries
= 0; tries
< 5; tries
++) {
2567 temp
= I915_READ(reg
);
2568 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2570 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2571 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2572 DRM_DEBUG_KMS("FDI train 2 done.\n");
2577 DRM_ERROR("FDI train 2 fail!\n");
2579 DRM_DEBUG_KMS("FDI train done\n");
2583 static const int snb_b_fdi_train_param
[] = {
2584 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
2585 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
2586 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
2587 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
2590 /* The FDI link training functions for SNB/Cougarpoint. */
2591 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
2593 struct drm_device
*dev
= crtc
->dev
;
2594 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2595 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2596 int pipe
= intel_crtc
->pipe
;
2597 u32 reg
, temp
, i
, retry
;
2599 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2601 reg
= FDI_RX_IMR(pipe
);
2602 temp
= I915_READ(reg
);
2603 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2604 temp
&= ~FDI_RX_BIT_LOCK
;
2605 I915_WRITE(reg
, temp
);
2610 /* enable CPU FDI TX and PCH FDI RX */
2611 reg
= FDI_TX_CTL(pipe
);
2612 temp
= I915_READ(reg
);
2614 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2615 temp
&= ~FDI_LINK_TRAIN_NONE
;
2616 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2617 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2619 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2620 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2622 I915_WRITE(FDI_RX_MISC(pipe
),
2623 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2625 reg
= FDI_RX_CTL(pipe
);
2626 temp
= I915_READ(reg
);
2627 if (HAS_PCH_CPT(dev
)) {
2628 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2629 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2631 temp
&= ~FDI_LINK_TRAIN_NONE
;
2632 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2634 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2639 for (i
= 0; i
< 4; i
++) {
2640 reg
= FDI_TX_CTL(pipe
);
2641 temp
= I915_READ(reg
);
2642 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2643 temp
|= snb_b_fdi_train_param
[i
];
2644 I915_WRITE(reg
, temp
);
2649 for (retry
= 0; retry
< 5; retry
++) {
2650 reg
= FDI_RX_IIR(pipe
);
2651 temp
= I915_READ(reg
);
2652 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2653 if (temp
& FDI_RX_BIT_LOCK
) {
2654 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2655 DRM_DEBUG_KMS("FDI train 1 done.\n");
2664 DRM_ERROR("FDI train 1 fail!\n");
2667 reg
= FDI_TX_CTL(pipe
);
2668 temp
= I915_READ(reg
);
2669 temp
&= ~FDI_LINK_TRAIN_NONE
;
2670 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2672 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2674 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2676 I915_WRITE(reg
, temp
);
2678 reg
= FDI_RX_CTL(pipe
);
2679 temp
= I915_READ(reg
);
2680 if (HAS_PCH_CPT(dev
)) {
2681 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2682 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2684 temp
&= ~FDI_LINK_TRAIN_NONE
;
2685 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2687 I915_WRITE(reg
, temp
);
2692 for (i
= 0; i
< 4; i
++) {
2693 reg
= FDI_TX_CTL(pipe
);
2694 temp
= I915_READ(reg
);
2695 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2696 temp
|= snb_b_fdi_train_param
[i
];
2697 I915_WRITE(reg
, temp
);
2702 for (retry
= 0; retry
< 5; retry
++) {
2703 reg
= FDI_RX_IIR(pipe
);
2704 temp
= I915_READ(reg
);
2705 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2706 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2707 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2708 DRM_DEBUG_KMS("FDI train 2 done.\n");
2717 DRM_ERROR("FDI train 2 fail!\n");
2719 DRM_DEBUG_KMS("FDI train done.\n");
2722 /* Manual link training for Ivy Bridge A0 parts */
2723 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
2725 struct drm_device
*dev
= crtc
->dev
;
2726 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2727 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2728 int pipe
= intel_crtc
->pipe
;
2731 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2733 reg
= FDI_RX_IMR(pipe
);
2734 temp
= I915_READ(reg
);
2735 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2736 temp
&= ~FDI_RX_BIT_LOCK
;
2737 I915_WRITE(reg
, temp
);
2742 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2743 I915_READ(FDI_RX_IIR(pipe
)));
2745 /* enable CPU FDI TX and PCH FDI RX */
2746 reg
= FDI_TX_CTL(pipe
);
2747 temp
= I915_READ(reg
);
2749 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2750 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
2751 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
2752 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2753 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2754 temp
|= FDI_COMPOSITE_SYNC
;
2755 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2757 I915_WRITE(FDI_RX_MISC(pipe
),
2758 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2760 reg
= FDI_RX_CTL(pipe
);
2761 temp
= I915_READ(reg
);
2762 temp
&= ~FDI_LINK_TRAIN_AUTO
;
2763 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2764 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2765 temp
|= FDI_COMPOSITE_SYNC
;
2766 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2771 for (i
= 0; i
< 4; i
++) {
2772 reg
= FDI_TX_CTL(pipe
);
2773 temp
= I915_READ(reg
);
2774 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2775 temp
|= snb_b_fdi_train_param
[i
];
2776 I915_WRITE(reg
, temp
);
2781 reg
= FDI_RX_IIR(pipe
);
2782 temp
= I915_READ(reg
);
2783 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2785 if (temp
& FDI_RX_BIT_LOCK
||
2786 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
2787 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2788 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i
);
2793 DRM_ERROR("FDI train 1 fail!\n");
2796 reg
= FDI_TX_CTL(pipe
);
2797 temp
= I915_READ(reg
);
2798 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2799 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
2800 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2801 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2802 I915_WRITE(reg
, temp
);
2804 reg
= FDI_RX_CTL(pipe
);
2805 temp
= I915_READ(reg
);
2806 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2807 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2808 I915_WRITE(reg
, temp
);
2813 for (i
= 0; i
< 4; i
++) {
2814 reg
= FDI_TX_CTL(pipe
);
2815 temp
= I915_READ(reg
);
2816 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2817 temp
|= snb_b_fdi_train_param
[i
];
2818 I915_WRITE(reg
, temp
);
2823 reg
= FDI_RX_IIR(pipe
);
2824 temp
= I915_READ(reg
);
2825 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2827 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2828 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2829 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i
);
2834 DRM_ERROR("FDI train 2 fail!\n");
2836 DRM_DEBUG_KMS("FDI train done.\n");
2839 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
2841 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2842 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2843 int pipe
= intel_crtc
->pipe
;
2847 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2848 reg
= FDI_RX_CTL(pipe
);
2849 temp
= I915_READ(reg
);
2850 temp
&= ~((0x7 << 19) | (0x7 << 16));
2851 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2852 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2853 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
2858 /* Switch from Rawclk to PCDclk */
2859 temp
= I915_READ(reg
);
2860 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
2865 /* Enable CPU FDI TX PLL, always on for Ironlake */
2866 reg
= FDI_TX_CTL(pipe
);
2867 temp
= I915_READ(reg
);
2868 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
2869 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
2876 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
2878 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2879 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2880 int pipe
= intel_crtc
->pipe
;
2883 /* Switch from PCDclk to Rawclk */
2884 reg
= FDI_RX_CTL(pipe
);
2885 temp
= I915_READ(reg
);
2886 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
2888 /* Disable CPU FDI TX PLL */
2889 reg
= FDI_TX_CTL(pipe
);
2890 temp
= I915_READ(reg
);
2891 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
2896 reg
= FDI_RX_CTL(pipe
);
2897 temp
= I915_READ(reg
);
2898 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
2900 /* Wait for the clocks to turn off. */
2905 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
2907 struct drm_device
*dev
= crtc
->dev
;
2908 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2909 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2910 int pipe
= intel_crtc
->pipe
;
2913 /* disable CPU FDI tx and PCH FDI rx */
2914 reg
= FDI_TX_CTL(pipe
);
2915 temp
= I915_READ(reg
);
2916 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
2919 reg
= FDI_RX_CTL(pipe
);
2920 temp
= I915_READ(reg
);
2921 temp
&= ~(0x7 << 16);
2922 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2923 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
2928 /* Ironlake workaround, disable clock pointer after downing FDI */
2929 if (HAS_PCH_IBX(dev
)) {
2930 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2933 /* still set train pattern 1 */
2934 reg
= FDI_TX_CTL(pipe
);
2935 temp
= I915_READ(reg
);
2936 temp
&= ~FDI_LINK_TRAIN_NONE
;
2937 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2938 I915_WRITE(reg
, temp
);
2940 reg
= FDI_RX_CTL(pipe
);
2941 temp
= I915_READ(reg
);
2942 if (HAS_PCH_CPT(dev
)) {
2943 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2944 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2946 temp
&= ~FDI_LINK_TRAIN_NONE
;
2947 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2949 /* BPC in FDI rx is consistent with that in PIPECONF */
2950 temp
&= ~(0x07 << 16);
2951 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2952 I915_WRITE(reg
, temp
);
2958 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
2960 struct drm_device
*dev
= crtc
->dev
;
2961 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2962 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2963 unsigned long flags
;
2966 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
2967 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
2970 spin_lock_irqsave(&dev
->event_lock
, flags
);
2971 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
2972 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2977 static void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
2979 struct drm_device
*dev
= crtc
->dev
;
2980 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2982 if (crtc
->fb
== NULL
)
2985 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
2987 wait_event(dev_priv
->pending_flip_queue
,
2988 !intel_crtc_has_pending_flip(crtc
));
2990 mutex_lock(&dev
->struct_mutex
);
2991 intel_finish_fb(crtc
->fb
);
2992 mutex_unlock(&dev
->struct_mutex
);
2995 /* Program iCLKIP clock to the desired frequency */
2996 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
2998 struct drm_device
*dev
= crtc
->dev
;
2999 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3000 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
3003 mutex_lock(&dev_priv
->dpio_lock
);
3005 /* It is necessary to ungate the pixclk gate prior to programming
3006 * the divisors, and gate it back when it is done.
3008 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
3010 /* Disable SSCCTL */
3011 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
3012 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
3016 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3017 if (crtc
->mode
.clock
== 20000) {
3022 /* The iCLK virtual clock root frequency is in MHz,
3023 * but the crtc->mode.clock in in KHz. To get the divisors,
3024 * it is necessary to divide one by another, so we
3025 * convert the virtual clock precision to KHz here for higher
3028 u32 iclk_virtual_root_freq
= 172800 * 1000;
3029 u32 iclk_pi_range
= 64;
3030 u32 desired_divisor
, msb_divisor_value
, pi_value
;
3032 desired_divisor
= (iclk_virtual_root_freq
/ crtc
->mode
.clock
);
3033 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
3034 pi_value
= desired_divisor
% iclk_pi_range
;
3037 divsel
= msb_divisor_value
- 2;
3038 phaseinc
= pi_value
;
3041 /* This should not happen with any sane values */
3042 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
3043 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
3044 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
3045 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
3047 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3054 /* Program SSCDIVINTPHASE6 */
3055 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
3056 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
3057 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
3058 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
3059 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
3060 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
3061 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
3062 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
3064 /* Program SSCAUXDIV */
3065 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
3066 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3067 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
3068 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
3070 /* Enable modulator and associated divider */
3071 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
3072 temp
&= ~SBI_SSCCTL_DISABLE
;
3073 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
3075 /* Wait for initialization time */
3078 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
3080 mutex_unlock(&dev_priv
->dpio_lock
);
3084 * Enable PCH resources required for PCH ports:
3086 * - FDI training & RX/TX
3087 * - update transcoder timings
3088 * - DP transcoding bits
3091 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
3093 struct drm_device
*dev
= crtc
->dev
;
3094 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3095 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3096 int pipe
= intel_crtc
->pipe
;
3099 assert_transcoder_disabled(dev_priv
, pipe
);
3101 /* Write the TU size bits before fdi link training, so that error
3102 * detection works. */
3103 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
3104 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
3106 /* For PCH output, training FDI link */
3107 dev_priv
->display
.fdi_link_train(crtc
);
3109 /* XXX: pch pll's can be enabled any time before we enable the PCH
3110 * transcoder, and we actually should do this to not upset any PCH
3111 * transcoder that already use the clock when we share it.
3113 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3114 * unconditionally resets the pll - we need that to have the right LVDS
3115 * enable sequence. */
3116 ironlake_enable_pch_pll(intel_crtc
);
3118 if (HAS_PCH_CPT(dev
)) {
3121 temp
= I915_READ(PCH_DPLL_SEL
);
3125 temp
|= TRANSA_DPLL_ENABLE
;
3126 sel
= TRANSA_DPLLB_SEL
;
3129 temp
|= TRANSB_DPLL_ENABLE
;
3130 sel
= TRANSB_DPLLB_SEL
;
3133 temp
|= TRANSC_DPLL_ENABLE
;
3134 sel
= TRANSC_DPLLB_SEL
;
3137 if (intel_crtc
->pch_pll
->pll_reg
== _PCH_DPLL_B
)
3141 I915_WRITE(PCH_DPLL_SEL
, temp
);
3144 /* set transcoder timing, panel must allow it */
3145 assert_panel_unlocked(dev_priv
, pipe
);
3146 I915_WRITE(TRANS_HTOTAL(pipe
), I915_READ(HTOTAL(pipe
)));
3147 I915_WRITE(TRANS_HBLANK(pipe
), I915_READ(HBLANK(pipe
)));
3148 I915_WRITE(TRANS_HSYNC(pipe
), I915_READ(HSYNC(pipe
)));
3150 I915_WRITE(TRANS_VTOTAL(pipe
), I915_READ(VTOTAL(pipe
)));
3151 I915_WRITE(TRANS_VBLANK(pipe
), I915_READ(VBLANK(pipe
)));
3152 I915_WRITE(TRANS_VSYNC(pipe
), I915_READ(VSYNC(pipe
)));
3153 I915_WRITE(TRANS_VSYNCSHIFT(pipe
), I915_READ(VSYNCSHIFT(pipe
)));
3155 intel_fdi_normal_train(crtc
);
3157 /* For PCH DP, enable TRANS_DP_CTL */
3158 if (HAS_PCH_CPT(dev
) &&
3159 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
3160 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3161 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
3162 reg
= TRANS_DP_CTL(pipe
);
3163 temp
= I915_READ(reg
);
3164 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
3165 TRANS_DP_SYNC_MASK
|
3167 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
3168 TRANS_DP_ENH_FRAMING
);
3169 temp
|= bpc
<< 9; /* same format but at 11:9 */
3171 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
3172 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
3173 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
3174 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
3176 switch (intel_trans_dp_port_sel(crtc
)) {
3178 temp
|= TRANS_DP_PORT_SEL_B
;
3181 temp
|= TRANS_DP_PORT_SEL_C
;
3184 temp
|= TRANS_DP_PORT_SEL_D
;
3190 I915_WRITE(reg
, temp
);
3193 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
3196 static void lpt_pch_enable(struct drm_crtc
*crtc
)
3198 struct drm_device
*dev
= crtc
->dev
;
3199 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3200 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3201 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
3203 assert_transcoder_disabled(dev_priv
, TRANSCODER_A
);
3205 lpt_program_iclkip(crtc
);
3207 /* Set transcoder timing. */
3208 I915_WRITE(_TRANS_HTOTAL_A
, I915_READ(HTOTAL(cpu_transcoder
)));
3209 I915_WRITE(_TRANS_HBLANK_A
, I915_READ(HBLANK(cpu_transcoder
)));
3210 I915_WRITE(_TRANS_HSYNC_A
, I915_READ(HSYNC(cpu_transcoder
)));
3212 I915_WRITE(_TRANS_VTOTAL_A
, I915_READ(VTOTAL(cpu_transcoder
)));
3213 I915_WRITE(_TRANS_VBLANK_A
, I915_READ(VBLANK(cpu_transcoder
)));
3214 I915_WRITE(_TRANS_VSYNC_A
, I915_READ(VSYNC(cpu_transcoder
)));
3215 I915_WRITE(_TRANS_VSYNCSHIFT_A
, I915_READ(VSYNCSHIFT(cpu_transcoder
)));
3217 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
3220 static void intel_put_pch_pll(struct intel_crtc
*intel_crtc
)
3222 struct intel_pch_pll
*pll
= intel_crtc
->pch_pll
;
3227 if (pll
->refcount
== 0) {
3228 WARN(1, "bad PCH PLL refcount\n");
3233 intel_crtc
->pch_pll
= NULL
;
3236 static struct intel_pch_pll
*intel_get_pch_pll(struct intel_crtc
*intel_crtc
, u32 dpll
, u32 fp
)
3238 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
3239 struct intel_pch_pll
*pll
;
3242 pll
= intel_crtc
->pch_pll
;
3244 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3245 intel_crtc
->base
.base
.id
, pll
->pll_reg
);
3249 if (HAS_PCH_IBX(dev_priv
->dev
)) {
3250 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3251 i
= intel_crtc
->pipe
;
3252 pll
= &dev_priv
->pch_plls
[i
];
3254 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3255 intel_crtc
->base
.base
.id
, pll
->pll_reg
);
3260 for (i
= 0; i
< dev_priv
->num_pch_pll
; i
++) {
3261 pll
= &dev_priv
->pch_plls
[i
];
3263 /* Only want to check enabled timings first */
3264 if (pll
->refcount
== 0)
3267 if (dpll
== (I915_READ(pll
->pll_reg
) & 0x7fffffff) &&
3268 fp
== I915_READ(pll
->fp0_reg
)) {
3269 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3270 intel_crtc
->base
.base
.id
,
3271 pll
->pll_reg
, pll
->refcount
, pll
->active
);
3277 /* Ok no matching timings, maybe there's a free one? */
3278 for (i
= 0; i
< dev_priv
->num_pch_pll
; i
++) {
3279 pll
= &dev_priv
->pch_plls
[i
];
3280 if (pll
->refcount
== 0) {
3281 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3282 intel_crtc
->base
.base
.id
, pll
->pll_reg
);
3290 intel_crtc
->pch_pll
= pll
;
3292 DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i
, pipe_name(intel_crtc
->pipe
));
3293 prepare
: /* separate function? */
3294 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll
->pll_reg
);
3296 /* Wait for the clocks to stabilize before rewriting the regs */
3297 I915_WRITE(pll
->pll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
3298 POSTING_READ(pll
->pll_reg
);
3301 I915_WRITE(pll
->fp0_reg
, fp
);
3302 I915_WRITE(pll
->pll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
3307 void intel_cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
3309 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3310 int dslreg
= PIPEDSL(pipe
);
3313 temp
= I915_READ(dslreg
);
3315 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
3316 if (wait_for(I915_READ(dslreg
) != temp
, 5))
3317 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
3321 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
3323 struct drm_device
*dev
= crtc
->dev
;
3324 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3325 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3326 struct intel_encoder
*encoder
;
3327 int pipe
= intel_crtc
->pipe
;
3328 int plane
= intel_crtc
->plane
;
3331 WARN_ON(!crtc
->enabled
);
3333 if (intel_crtc
->active
)
3336 intel_crtc
->active
= true;
3338 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
3339 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
3341 intel_update_watermarks(dev
);
3343 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
3344 temp
= I915_READ(PCH_LVDS
);
3345 if ((temp
& LVDS_PORT_EN
) == 0)
3346 I915_WRITE(PCH_LVDS
, temp
| LVDS_PORT_EN
);
3350 if (intel_crtc
->config
.has_pch_encoder
) {
3351 /* Note: FDI PLL enabling _must_ be done before we enable the
3352 * cpu pipes, hence this is separate from all the other fdi/pch
3354 ironlake_fdi_pll_enable(intel_crtc
);
3356 assert_fdi_tx_disabled(dev_priv
, pipe
);
3357 assert_fdi_rx_disabled(dev_priv
, pipe
);
3360 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3361 if (encoder
->pre_enable
)
3362 encoder
->pre_enable(encoder
);
3364 /* Enable panel fitting for LVDS */
3365 if (dev_priv
->pch_pf_size
&&
3366 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) ||
3367 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3368 /* Force use of hard-coded filter coefficients
3369 * as some pre-programmed values are broken,
3372 if (IS_IVYBRIDGE(dev
))
3373 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
3374 PF_PIPE_SEL_IVB(pipe
));
3376 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
3377 I915_WRITE(PF_WIN_POS(pipe
), dev_priv
->pch_pf_pos
);
3378 I915_WRITE(PF_WIN_SZ(pipe
), dev_priv
->pch_pf_size
);
3382 * On ILK+ LUT must be loaded before the pipe is running but with
3385 intel_crtc_load_lut(crtc
);
3387 intel_enable_pipe(dev_priv
, pipe
,
3388 intel_crtc
->config
.has_pch_encoder
);
3389 intel_enable_plane(dev_priv
, plane
, pipe
);
3391 if (intel_crtc
->config
.has_pch_encoder
)
3392 ironlake_pch_enable(crtc
);
3394 mutex_lock(&dev
->struct_mutex
);
3395 intel_update_fbc(dev
);
3396 mutex_unlock(&dev
->struct_mutex
);
3398 intel_crtc_update_cursor(crtc
, true);
3400 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3401 encoder
->enable(encoder
);
3403 if (HAS_PCH_CPT(dev
))
3404 intel_cpt_verify_modeset(dev
, intel_crtc
->pipe
);
3407 * There seems to be a race in PCH platform hw (at least on some
3408 * outputs) where an enabled pipe still completes any pageflip right
3409 * away (as if the pipe is off) instead of waiting for vblank. As soon
3410 * as the first vblank happend, everything works as expected. Hence just
3411 * wait for one vblank before returning to avoid strange things
3414 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3417 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
3419 struct drm_device
*dev
= crtc
->dev
;
3420 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3421 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3422 struct intel_encoder
*encoder
;
3423 int pipe
= intel_crtc
->pipe
;
3424 int plane
= intel_crtc
->plane
;
3426 WARN_ON(!crtc
->enabled
);
3428 if (intel_crtc
->active
)
3431 intel_crtc
->active
= true;
3433 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
3434 if (intel_crtc
->config
.has_pch_encoder
)
3435 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
3437 intel_update_watermarks(dev
);
3439 if (intel_crtc
->config
.has_pch_encoder
)
3440 dev_priv
->display
.fdi_link_train(crtc
);
3442 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3443 if (encoder
->pre_enable
)
3444 encoder
->pre_enable(encoder
);
3446 intel_ddi_enable_pipe_clock(intel_crtc
);
3448 /* Enable panel fitting for eDP */
3449 if (dev_priv
->pch_pf_size
&&
3450 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
)) {
3451 /* Force use of hard-coded filter coefficients
3452 * as some pre-programmed values are broken,
3455 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
3456 PF_PIPE_SEL_IVB(pipe
));
3457 I915_WRITE(PF_WIN_POS(pipe
), dev_priv
->pch_pf_pos
);
3458 I915_WRITE(PF_WIN_SZ(pipe
), dev_priv
->pch_pf_size
);
3462 * On ILK+ LUT must be loaded before the pipe is running but with
3465 intel_crtc_load_lut(crtc
);
3467 intel_ddi_set_pipe_settings(crtc
);
3468 intel_ddi_enable_transcoder_func(crtc
);
3470 intel_enable_pipe(dev_priv
, pipe
,
3471 intel_crtc
->config
.has_pch_encoder
);
3472 intel_enable_plane(dev_priv
, plane
, pipe
);
3474 if (intel_crtc
->config
.has_pch_encoder
)
3475 lpt_pch_enable(crtc
);
3477 mutex_lock(&dev
->struct_mutex
);
3478 intel_update_fbc(dev
);
3479 mutex_unlock(&dev
->struct_mutex
);
3481 intel_crtc_update_cursor(crtc
, true);
3483 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3484 encoder
->enable(encoder
);
3487 * There seems to be a race in PCH platform hw (at least on some
3488 * outputs) where an enabled pipe still completes any pageflip right
3489 * away (as if the pipe is off) instead of waiting for vblank. As soon
3490 * as the first vblank happend, everything works as expected. Hence just
3491 * wait for one vblank before returning to avoid strange things
3494 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3497 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
3499 struct drm_device
*dev
= crtc
->dev
;
3500 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3501 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3502 struct intel_encoder
*encoder
;
3503 int pipe
= intel_crtc
->pipe
;
3504 int plane
= intel_crtc
->plane
;
3508 if (!intel_crtc
->active
)
3511 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3512 encoder
->disable(encoder
);
3514 intel_crtc_wait_for_pending_flips(crtc
);
3515 drm_vblank_off(dev
, pipe
);
3516 intel_crtc_update_cursor(crtc
, false);
3518 intel_disable_plane(dev_priv
, plane
, pipe
);
3520 if (dev_priv
->cfb_plane
== plane
)
3521 intel_disable_fbc(dev
);
3523 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, false);
3524 intel_disable_pipe(dev_priv
, pipe
);
3527 I915_WRITE(PF_CTL(pipe
), 0);
3528 I915_WRITE(PF_WIN_SZ(pipe
), 0);
3530 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3531 if (encoder
->post_disable
)
3532 encoder
->post_disable(encoder
);
3534 ironlake_fdi_disable(crtc
);
3536 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
3537 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
3539 if (HAS_PCH_CPT(dev
)) {
3540 /* disable TRANS_DP_CTL */
3541 reg
= TRANS_DP_CTL(pipe
);
3542 temp
= I915_READ(reg
);
3543 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
| TRANS_DP_PORT_SEL_MASK
);
3544 temp
|= TRANS_DP_PORT_SEL_NONE
;
3545 I915_WRITE(reg
, temp
);
3547 /* disable DPLL_SEL */
3548 temp
= I915_READ(PCH_DPLL_SEL
);
3551 temp
&= ~(TRANSA_DPLL_ENABLE
| TRANSA_DPLLB_SEL
);
3554 temp
&= ~(TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
);
3557 /* C shares PLL A or B */
3558 temp
&= ~(TRANSC_DPLL_ENABLE
| TRANSC_DPLLB_SEL
);
3563 I915_WRITE(PCH_DPLL_SEL
, temp
);
3566 /* disable PCH DPLL */
3567 intel_disable_pch_pll(intel_crtc
);
3569 ironlake_fdi_pll_disable(intel_crtc
);
3571 intel_crtc
->active
= false;
3572 intel_update_watermarks(dev
);
3574 mutex_lock(&dev
->struct_mutex
);
3575 intel_update_fbc(dev
);
3576 mutex_unlock(&dev
->struct_mutex
);
3579 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
3581 struct drm_device
*dev
= crtc
->dev
;
3582 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3583 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3584 struct intel_encoder
*encoder
;
3585 int pipe
= intel_crtc
->pipe
;
3586 int plane
= intel_crtc
->plane
;
3587 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
3589 if (!intel_crtc
->active
)
3592 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3593 encoder
->disable(encoder
);
3595 intel_crtc_wait_for_pending_flips(crtc
);
3596 drm_vblank_off(dev
, pipe
);
3597 intel_crtc_update_cursor(crtc
, false);
3599 intel_disable_plane(dev_priv
, plane
, pipe
);
3601 if (dev_priv
->cfb_plane
== plane
)
3602 intel_disable_fbc(dev
);
3604 if (intel_crtc
->config
.has_pch_encoder
)
3605 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, false);
3606 intel_disable_pipe(dev_priv
, pipe
);
3608 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
3610 /* XXX: Once we have proper panel fitter state tracking implemented with
3611 * hardware state read/check support we should switch to only disable
3612 * the panel fitter when we know it's used. */
3613 if (intel_using_power_well(dev
)) {
3614 I915_WRITE(PF_CTL(pipe
), 0);
3615 I915_WRITE(PF_WIN_SZ(pipe
), 0);
3618 intel_ddi_disable_pipe_clock(intel_crtc
);
3620 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3621 if (encoder
->post_disable
)
3622 encoder
->post_disable(encoder
);
3624 if (intel_crtc
->config
.has_pch_encoder
) {
3625 lpt_disable_pch_transcoder(dev_priv
);
3626 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
3627 intel_ddi_fdi_disable(crtc
);
3630 intel_crtc
->active
= false;
3631 intel_update_watermarks(dev
);
3633 mutex_lock(&dev
->struct_mutex
);
3634 intel_update_fbc(dev
);
3635 mutex_unlock(&dev
->struct_mutex
);
3638 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
3640 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3641 intel_put_pch_pll(intel_crtc
);
3644 static void haswell_crtc_off(struct drm_crtc
*crtc
)
3646 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3648 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3649 * start using it. */
3650 intel_crtc
->config
.cpu_transcoder
= (enum transcoder
) intel_crtc
->pipe
;
3652 intel_ddi_put_crtc_pll(crtc
);
3655 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
3657 if (!enable
&& intel_crtc
->overlay
) {
3658 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3659 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3661 mutex_lock(&dev
->struct_mutex
);
3662 dev_priv
->mm
.interruptible
= false;
3663 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
3664 dev_priv
->mm
.interruptible
= true;
3665 mutex_unlock(&dev
->struct_mutex
);
3668 /* Let userspace switch the overlay on again. In most cases userspace
3669 * has to recompute where to put it anyway.
3674 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3675 * cursor plane briefly if not already running after enabling the display
3677 * This workaround avoids occasional blank screens when self refresh is
3681 g4x_fixup_plane(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
3683 u32 cntl
= I915_READ(CURCNTR(pipe
));
3685 if ((cntl
& CURSOR_MODE
) == 0) {
3686 u32 fw_bcl_self
= I915_READ(FW_BLC_SELF
);
3688 I915_WRITE(FW_BLC_SELF
, fw_bcl_self
& ~FW_BLC_SELF_EN
);
3689 I915_WRITE(CURCNTR(pipe
), CURSOR_MODE_64_ARGB_AX
);
3690 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
3691 I915_WRITE(CURCNTR(pipe
), cntl
);
3692 I915_WRITE(CURBASE(pipe
), I915_READ(CURBASE(pipe
)));
3693 I915_WRITE(FW_BLC_SELF
, fw_bcl_self
);
3697 static void valleyview_crtc_enable(struct drm_crtc
*crtc
)
3699 struct drm_device
*dev
= crtc
->dev
;
3700 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3701 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3702 struct intel_encoder
*encoder
;
3703 int pipe
= intel_crtc
->pipe
;
3704 int plane
= intel_crtc
->plane
;
3706 WARN_ON(!crtc
->enabled
);
3708 if (intel_crtc
->active
)
3711 intel_crtc
->active
= true;
3712 intel_update_watermarks(dev
);
3714 mutex_lock(&dev_priv
->dpio_lock
);
3716 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3717 if (encoder
->pre_pll_enable
)
3718 encoder
->pre_pll_enable(encoder
);
3720 intel_enable_pll(dev_priv
, pipe
);
3722 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3723 if (encoder
->pre_enable
)
3724 encoder
->pre_enable(encoder
);
3726 /* VLV wants encoder enabling _before_ the pipe is up. */
3727 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3728 encoder
->enable(encoder
);
3730 intel_enable_pipe(dev_priv
, pipe
, false);
3731 intel_enable_plane(dev_priv
, plane
, pipe
);
3733 intel_crtc_load_lut(crtc
);
3734 intel_update_fbc(dev
);
3736 /* Give the overlay scaler a chance to enable if it's on this pipe */
3737 intel_crtc_dpms_overlay(intel_crtc
, true);
3738 intel_crtc_update_cursor(crtc
, true);
3740 mutex_unlock(&dev_priv
->dpio_lock
);
3743 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
3745 struct drm_device
*dev
= crtc
->dev
;
3746 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3747 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3748 struct intel_encoder
*encoder
;
3749 int pipe
= intel_crtc
->pipe
;
3750 int plane
= intel_crtc
->plane
;
3752 WARN_ON(!crtc
->enabled
);
3754 if (intel_crtc
->active
)
3757 intel_crtc
->active
= true;
3758 intel_update_watermarks(dev
);
3760 intel_enable_pll(dev_priv
, pipe
);
3762 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3763 if (encoder
->pre_enable
)
3764 encoder
->pre_enable(encoder
);
3766 intel_enable_pipe(dev_priv
, pipe
, false);
3767 intel_enable_plane(dev_priv
, plane
, pipe
);
3769 g4x_fixup_plane(dev_priv
, pipe
);
3771 intel_crtc_load_lut(crtc
);
3772 intel_update_fbc(dev
);
3774 /* Give the overlay scaler a chance to enable if it's on this pipe */
3775 intel_crtc_dpms_overlay(intel_crtc
, true);
3776 intel_crtc_update_cursor(crtc
, true);
3778 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3779 encoder
->enable(encoder
);
3782 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
3784 struct drm_device
*dev
= crtc
->base
.dev
;
3785 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3787 uint32_t pctl
= I915_READ(PFIT_CONTROL
);
3789 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
3791 if (INTEL_INFO(dev
)->gen
>= 4)
3792 pipe
= (pctl
& PFIT_PIPE_MASK
) >> PFIT_PIPE_SHIFT
;
3796 if (pipe
== crtc
->pipe
) {
3797 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", pctl
);
3798 I915_WRITE(PFIT_CONTROL
, 0);
3802 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
3804 struct drm_device
*dev
= crtc
->dev
;
3805 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3806 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3807 struct intel_encoder
*encoder
;
3808 int pipe
= intel_crtc
->pipe
;
3809 int plane
= intel_crtc
->plane
;
3811 if (!intel_crtc
->active
)
3814 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3815 encoder
->disable(encoder
);
3817 /* Give the overlay scaler a chance to disable if it's on this pipe */
3818 intel_crtc_wait_for_pending_flips(crtc
);
3819 drm_vblank_off(dev
, pipe
);
3820 intel_crtc_dpms_overlay(intel_crtc
, false);
3821 intel_crtc_update_cursor(crtc
, false);
3823 if (dev_priv
->cfb_plane
== plane
)
3824 intel_disable_fbc(dev
);
3826 intel_disable_plane(dev_priv
, plane
, pipe
);
3827 intel_disable_pipe(dev_priv
, pipe
);
3829 i9xx_pfit_disable(intel_crtc
);
3831 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3832 if (encoder
->post_disable
)
3833 encoder
->post_disable(encoder
);
3835 intel_disable_pll(dev_priv
, pipe
);
3837 intel_crtc
->active
= false;
3838 intel_update_fbc(dev
);
3839 intel_update_watermarks(dev
);
3842 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
3846 static void intel_crtc_update_sarea(struct drm_crtc
*crtc
,
3849 struct drm_device
*dev
= crtc
->dev
;
3850 struct drm_i915_master_private
*master_priv
;
3851 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3852 int pipe
= intel_crtc
->pipe
;
3854 if (!dev
->primary
->master
)
3857 master_priv
= dev
->primary
->master
->driver_priv
;
3858 if (!master_priv
->sarea_priv
)
3863 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3864 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3867 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3868 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3871 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe
));
3877 * Sets the power management mode of the pipe and plane.
3879 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
3881 struct drm_device
*dev
= crtc
->dev
;
3882 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3883 struct intel_encoder
*intel_encoder
;
3884 bool enable
= false;
3886 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
3887 enable
|= intel_encoder
->connectors_active
;
3890 dev_priv
->display
.crtc_enable(crtc
);
3892 dev_priv
->display
.crtc_disable(crtc
);
3894 intel_crtc_update_sarea(crtc
, enable
);
3897 static void intel_crtc_disable(struct drm_crtc
*crtc
)
3899 struct drm_device
*dev
= crtc
->dev
;
3900 struct drm_connector
*connector
;
3901 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3902 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3904 /* crtc should still be enabled when we disable it. */
3905 WARN_ON(!crtc
->enabled
);
3907 intel_crtc
->eld_vld
= false;
3908 dev_priv
->display
.crtc_disable(crtc
);
3909 intel_crtc_update_sarea(crtc
, false);
3910 dev_priv
->display
.off(crtc
);
3912 assert_plane_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->plane
);
3913 assert_pipe_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->pipe
);
3916 mutex_lock(&dev
->struct_mutex
);
3917 intel_unpin_fb_obj(to_intel_framebuffer(crtc
->fb
)->obj
);
3918 mutex_unlock(&dev
->struct_mutex
);
3922 /* Update computed state. */
3923 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
3924 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
3927 if (connector
->encoder
->crtc
!= crtc
)
3930 connector
->dpms
= DRM_MODE_DPMS_OFF
;
3931 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
3935 void intel_modeset_disable(struct drm_device
*dev
)
3937 struct drm_crtc
*crtc
;
3939 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
3941 intel_crtc_disable(crtc
);
3945 void intel_encoder_destroy(struct drm_encoder
*encoder
)
3947 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
3949 drm_encoder_cleanup(encoder
);
3950 kfree(intel_encoder
);
3953 /* Simple dpms helper for encodres with just one connector, no cloning and only
3954 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3955 * state of the entire output pipe. */
3956 void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
3958 if (mode
== DRM_MODE_DPMS_ON
) {
3959 encoder
->connectors_active
= true;
3961 intel_crtc_update_dpms(encoder
->base
.crtc
);
3963 encoder
->connectors_active
= false;
3965 intel_crtc_update_dpms(encoder
->base
.crtc
);
3969 /* Cross check the actual hw state with our own modeset state tracking (and it's
3970 * internal consistency). */
3971 static void intel_connector_check_state(struct intel_connector
*connector
)
3973 if (connector
->get_hw_state(connector
)) {
3974 struct intel_encoder
*encoder
= connector
->encoder
;
3975 struct drm_crtc
*crtc
;
3976 bool encoder_enabled
;
3979 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3980 connector
->base
.base
.id
,
3981 drm_get_connector_name(&connector
->base
));
3983 WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
3984 "wrong connector dpms state\n");
3985 WARN(connector
->base
.encoder
!= &encoder
->base
,
3986 "active connector not linked to encoder\n");
3987 WARN(!encoder
->connectors_active
,
3988 "encoder->connectors_active not set\n");
3990 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
3991 WARN(!encoder_enabled
, "encoder not enabled\n");
3992 if (WARN_ON(!encoder
->base
.crtc
))
3995 crtc
= encoder
->base
.crtc
;
3997 WARN(!crtc
->enabled
, "crtc not enabled\n");
3998 WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
3999 WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
4000 "encoder active on the wrong pipe\n");
4004 /* Even simpler default implementation, if there's really no special case to
4006 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
4008 struct intel_encoder
*encoder
= intel_attached_encoder(connector
);
4010 /* All the simple cases only support two dpms states. */
4011 if (mode
!= DRM_MODE_DPMS_ON
)
4012 mode
= DRM_MODE_DPMS_OFF
;
4014 if (mode
== connector
->dpms
)
4017 connector
->dpms
= mode
;
4019 /* Only need to change hw state when actually enabled */
4020 if (encoder
->base
.crtc
)
4021 intel_encoder_dpms(encoder
, mode
);
4023 WARN_ON(encoder
->connectors_active
!= false);
4025 intel_modeset_check_state(connector
->dev
);
4028 /* Simple connector->get_hw_state implementation for encoders that support only
4029 * one connector and no cloning and hence the encoder state determines the state
4030 * of the connector. */
4031 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
4034 struct intel_encoder
*encoder
= connector
->encoder
;
4036 return encoder
->get_hw_state(encoder
, &pipe
);
4039 static bool intel_crtc_compute_config(struct drm_crtc
*crtc
,
4040 struct intel_crtc_config
*pipe_config
)
4042 struct drm_device
*dev
= crtc
->dev
;
4043 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
4045 if (HAS_PCH_SPLIT(dev
)) {
4046 /* FDI link clock is fixed at 2.7G */
4047 if (pipe_config
->requested_mode
.clock
* 3
4048 > IRONLAKE_FDI_FREQ
* 4)
4052 /* All interlaced capable intel hw wants timings in frames. Note though
4053 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4054 * timings, so we need to be careful not to clobber these.*/
4055 if (!pipe_config
->timings_set
)
4056 drm_mode_set_crtcinfo(adjusted_mode
, 0);
4058 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
4059 * with a hsync front porch of 0.
4061 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
4062 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
4065 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) && pipe_config
->pipe_bpp
> 10*3) {
4066 pipe_config
->pipe_bpp
= 10*3; /* 12bpc is gen5+ */
4067 } else if (INTEL_INFO(dev
)->gen
<= 4 && pipe_config
->pipe_bpp
> 8*3) {
4068 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4070 pipe_config
->pipe_bpp
= 8*3;
4076 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
4078 return 400000; /* FIXME */
4081 static int i945_get_display_clock_speed(struct drm_device
*dev
)
4086 static int i915_get_display_clock_speed(struct drm_device
*dev
)
4091 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
4096 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
4100 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
4102 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
4105 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
4106 case GC_DISPLAY_CLOCK_333_MHZ
:
4109 case GC_DISPLAY_CLOCK_190_200_MHZ
:
4115 static int i865_get_display_clock_speed(struct drm_device
*dev
)
4120 static int i855_get_display_clock_speed(struct drm_device
*dev
)
4123 /* Assume that the hardware is in the high speed state. This
4124 * should be the default.
4126 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
4127 case GC_CLOCK_133_200
:
4128 case GC_CLOCK_100_200
:
4130 case GC_CLOCK_166_250
:
4132 case GC_CLOCK_100_133
:
4136 /* Shouldn't happen */
4140 static int i830_get_display_clock_speed(struct drm_device
*dev
)
4146 intel_reduce_ratio(uint32_t *num
, uint32_t *den
)
4148 while (*num
> 0xffffff || *den
> 0xffffff) {
4155 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
4156 int pixel_clock
, int link_clock
,
4157 struct intel_link_m_n
*m_n
)
4160 m_n
->gmch_m
= bits_per_pixel
* pixel_clock
;
4161 m_n
->gmch_n
= link_clock
* nlanes
* 8;
4162 intel_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
4163 m_n
->link_m
= pixel_clock
;
4164 m_n
->link_n
= link_clock
;
4165 intel_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
4168 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
4170 if (i915_panel_use_ssc
>= 0)
4171 return i915_panel_use_ssc
!= 0;
4172 return dev_priv
->lvds_use_ssc
4173 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
4176 static int vlv_get_refclk(struct drm_crtc
*crtc
)
4178 struct drm_device
*dev
= crtc
->dev
;
4179 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4180 int refclk
= 27000; /* for DP & HDMI */
4182 return 100000; /* only one validated so far */
4184 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
4186 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
4187 if (intel_panel_use_ssc(dev_priv
))
4191 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
)) {
4198 static int i9xx_get_refclk(struct drm_crtc
*crtc
, int num_connectors
)
4200 struct drm_device
*dev
= crtc
->dev
;
4201 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4204 if (IS_VALLEYVIEW(dev
)) {
4205 refclk
= vlv_get_refclk(crtc
);
4206 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4207 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
4208 refclk
= dev_priv
->lvds_ssc_freq
* 1000;
4209 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4211 } else if (!IS_GEN2(dev
)) {
4220 static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc
*crtc
)
4222 unsigned dotclock
= crtc
->config
.adjusted_mode
.clock
;
4223 struct dpll
*clock
= &crtc
->config
.dpll
;
4225 /* SDVO TV has fixed PLL values depend on its clock range,
4226 this mirrors vbios setting. */
4227 if (dotclock
>= 100000 && dotclock
< 140500) {
4233 } else if (dotclock
>= 140500 && dotclock
<= 200000) {
4241 crtc
->config
.clock_set
= true;
4244 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
4245 intel_clock_t
*reduced_clock
)
4247 struct drm_device
*dev
= crtc
->base
.dev
;
4248 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4249 int pipe
= crtc
->pipe
;
4251 struct dpll
*clock
= &crtc
->config
.dpll
;
4253 if (IS_PINEVIEW(dev
)) {
4254 fp
= (1 << clock
->n
) << 16 | clock
->m1
<< 8 | clock
->m2
;
4256 fp2
= (1 << reduced_clock
->n
) << 16 |
4257 reduced_clock
->m1
<< 8 | reduced_clock
->m2
;
4259 fp
= clock
->n
<< 16 | clock
->m1
<< 8 | clock
->m2
;
4261 fp2
= reduced_clock
->n
<< 16 | reduced_clock
->m1
<< 8 |
4265 I915_WRITE(FP0(pipe
), fp
);
4267 crtc
->lowfreq_avail
= false;
4268 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4269 reduced_clock
&& i915_powersave
) {
4270 I915_WRITE(FP1(pipe
), fp2
);
4271 crtc
->lowfreq_avail
= true;
4273 I915_WRITE(FP1(pipe
), fp
);
4277 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
)
4282 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4283 * and set it to a reasonable value instead.
4285 reg_val
= intel_dpio_read(dev_priv
, DPIO_IREF(1));
4286 reg_val
&= 0xffffff00;
4287 reg_val
|= 0x00000030;
4288 intel_dpio_write(dev_priv
, DPIO_IREF(1), reg_val
);
4290 reg_val
= intel_dpio_read(dev_priv
, DPIO_CALIBRATION
);
4291 reg_val
&= 0x8cffffff;
4292 reg_val
= 0x8c000000;
4293 intel_dpio_write(dev_priv
, DPIO_CALIBRATION
, reg_val
);
4295 reg_val
= intel_dpio_read(dev_priv
, DPIO_IREF(1));
4296 reg_val
&= 0xffffff00;
4297 intel_dpio_write(dev_priv
, DPIO_IREF(1), reg_val
);
4299 reg_val
= intel_dpio_read(dev_priv
, DPIO_CALIBRATION
);
4300 reg_val
&= 0x00ffffff;
4301 reg_val
|= 0xb0000000;
4302 intel_dpio_write(dev_priv
, DPIO_CALIBRATION
, reg_val
);
4305 static void intel_dp_set_m_n(struct intel_crtc
*crtc
)
4307 if (crtc
->config
.has_pch_encoder
)
4308 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
4310 intel_cpu_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
4313 static void vlv_update_pll(struct intel_crtc
*crtc
)
4315 struct drm_device
*dev
= crtc
->base
.dev
;
4316 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4317 struct drm_display_mode
*adjusted_mode
=
4318 &crtc
->config
.adjusted_mode
;
4319 struct intel_encoder
*encoder
;
4320 int pipe
= crtc
->pipe
;
4322 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
4324 u32 coreclk
, reg_val
, temp
;
4326 mutex_lock(&dev_priv
->dpio_lock
);
4328 is_hdmi
= intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
);
4330 bestn
= crtc
->config
.dpll
.n
;
4331 bestm1
= crtc
->config
.dpll
.m1
;
4332 bestm2
= crtc
->config
.dpll
.m2
;
4333 bestp1
= crtc
->config
.dpll
.p1
;
4334 bestp2
= crtc
->config
.dpll
.p2
;
4336 /* See eDP HDMI DPIO driver vbios notes doc */
4338 /* PLL B needs special handling */
4340 vlv_pllb_recal_opamp(dev_priv
);
4342 /* Set up Tx target for periodic Rcomp update */
4343 intel_dpio_write(dev_priv
, DPIO_IREF_BCAST
, 0x0100000f);
4345 /* Disable target IRef on PLL */
4346 reg_val
= intel_dpio_read(dev_priv
, DPIO_IREF_CTL(pipe
));
4347 reg_val
&= 0x00ffffff;
4348 intel_dpio_write(dev_priv
, DPIO_IREF_CTL(pipe
), reg_val
);
4350 /* Disable fast lock */
4351 intel_dpio_write(dev_priv
, DPIO_FASTCLK_DISABLE
, 0x610);
4353 /* Set idtafcrecal before PLL is enabled */
4354 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
4355 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
4356 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
4357 mdiv
|= (1 << DPIO_K_SHIFT
);
4358 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
) ||
4359 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
) ||
4360 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
))
4361 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
4362 intel_dpio_write(dev_priv
, DPIO_DIV(pipe
), mdiv
);
4364 mdiv
|= DPIO_ENABLE_CALIBRATION
;
4365 intel_dpio_write(dev_priv
, DPIO_DIV(pipe
), mdiv
);
4367 /* Set HBR and RBR LPF coefficients */
4368 if (adjusted_mode
->clock
== 162000 ||
4369 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
))
4370 intel_dpio_write(dev_priv
, DPIO_LFP_COEFF(pipe
),
4373 intel_dpio_write(dev_priv
, DPIO_LFP_COEFF(pipe
),
4376 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
) ||
4377 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
)) {
4378 /* Use SSC source */
4380 intel_dpio_write(dev_priv
, DPIO_REFSFR(pipe
),
4383 intel_dpio_write(dev_priv
, DPIO_REFSFR(pipe
),
4385 } else { /* HDMI or VGA */
4386 /* Use bend source */
4388 intel_dpio_write(dev_priv
, DPIO_REFSFR(pipe
),
4391 intel_dpio_write(dev_priv
, DPIO_REFSFR(pipe
),
4395 coreclk
= intel_dpio_read(dev_priv
, DPIO_CORE_CLK(pipe
));
4396 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
4397 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
) ||
4398 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
))
4399 coreclk
|= 0x01000000;
4400 intel_dpio_write(dev_priv
, DPIO_CORE_CLK(pipe
), coreclk
);
4402 intel_dpio_write(dev_priv
, DPIO_PLL_CML(pipe
), 0x87871000);
4404 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
4405 if (encoder
->pre_pll_enable
)
4406 encoder
->pre_pll_enable(encoder
);
4408 /* Enable DPIO clock input */
4409 dpll
= DPLL_EXT_BUFFER_ENABLE_VLV
| DPLL_REFA_CLK_ENABLE_VLV
|
4410 DPLL_VGA_MODE_DIS
| DPLL_INTEGRATED_CLOCK_VLV
;
4412 dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
4414 dpll
|= DPLL_VCO_ENABLE
;
4415 I915_WRITE(DPLL(pipe
), dpll
);
4416 POSTING_READ(DPLL(pipe
));
4419 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
4420 DRM_ERROR("DPLL %d failed to lock\n", pipe
);
4424 if (crtc
->config
.pixel_multiplier
> 1) {
4425 temp
= (crtc
->config
.pixel_multiplier
- 1)
4426 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4429 I915_WRITE(DPLL_MD(pipe
), temp
);
4430 POSTING_READ(DPLL_MD(pipe
));
4433 if (crtc
->config
.has_dp_encoder
)
4434 intel_dp_set_m_n(crtc
);
4436 mutex_unlock(&dev_priv
->dpio_lock
);
4439 static void i9xx_update_pll(struct intel_crtc
*crtc
,
4440 intel_clock_t
*reduced_clock
,
4443 struct drm_device
*dev
= crtc
->base
.dev
;
4444 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4445 struct intel_encoder
*encoder
;
4446 int pipe
= crtc
->pipe
;
4449 struct dpll
*clock
= &crtc
->config
.dpll
;
4451 i9xx_update_pll_dividers(crtc
, reduced_clock
);
4453 is_sdvo
= intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_SDVO
) ||
4454 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
);
4456 dpll
= DPLL_VGA_MODE_DIS
;
4458 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
))
4459 dpll
|= DPLLB_MODE_LVDS
;
4461 dpll
|= DPLLB_MODE_DAC_SERIAL
;
4464 if ((crtc
->config
.pixel_multiplier
> 1) &&
4465 (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))) {
4466 dpll
|= (crtc
->config
.pixel_multiplier
- 1)
4467 << SDVO_MULTIPLIER_SHIFT_HIRES
;
4469 dpll
|= DPLL_DVO_HIGH_SPEED
;
4471 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
))
4472 dpll
|= DPLL_DVO_HIGH_SPEED
;
4474 /* compute bitmask from p1 value */
4475 if (IS_PINEVIEW(dev
))
4476 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
4478 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4479 if (IS_G4X(dev
) && reduced_clock
)
4480 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
4482 switch (clock
->p2
) {
4484 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
4487 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
4490 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
4493 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
4496 if (INTEL_INFO(dev
)->gen
>= 4)
4497 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
4499 if (is_sdvo
&& intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_TVOUT
))
4500 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
4501 else if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_TVOUT
))
4502 /* XXX: just matching BIOS for now */
4503 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4505 else if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4506 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4507 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4509 dpll
|= PLL_REF_INPUT_DREFCLK
;
4511 dpll
|= DPLL_VCO_ENABLE
;
4512 I915_WRITE(DPLL(pipe
), dpll
& ~DPLL_VCO_ENABLE
);
4513 POSTING_READ(DPLL(pipe
));
4516 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
4517 if (encoder
->pre_pll_enable
)
4518 encoder
->pre_pll_enable(encoder
);
4520 if (crtc
->config
.has_dp_encoder
)
4521 intel_dp_set_m_n(crtc
);
4523 I915_WRITE(DPLL(pipe
), dpll
);
4525 /* Wait for the clocks to stabilize. */
4526 POSTING_READ(DPLL(pipe
));
4529 if (INTEL_INFO(dev
)->gen
>= 4) {
4533 if (crtc
->config
.pixel_multiplier
> 1) {
4534 temp
= (crtc
->config
.pixel_multiplier
- 1)
4535 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4538 I915_WRITE(DPLL_MD(pipe
), temp
);
4540 /* The pixel multiplier can only be updated once the
4541 * DPLL is enabled and the clocks are stable.
4543 * So write it again.
4545 I915_WRITE(DPLL(pipe
), dpll
);
4549 static void i8xx_update_pll(struct intel_crtc
*crtc
,
4550 struct drm_display_mode
*adjusted_mode
,
4551 intel_clock_t
*reduced_clock
,
4554 struct drm_device
*dev
= crtc
->base
.dev
;
4555 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4556 struct intel_encoder
*encoder
;
4557 int pipe
= crtc
->pipe
;
4559 struct dpll
*clock
= &crtc
->config
.dpll
;
4561 i9xx_update_pll_dividers(crtc
, reduced_clock
);
4563 dpll
= DPLL_VGA_MODE_DIS
;
4565 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
)) {
4566 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4569 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
4571 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4573 dpll
|= PLL_P2_DIVIDE_BY_4
;
4576 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4577 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4578 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4580 dpll
|= PLL_REF_INPUT_DREFCLK
;
4582 dpll
|= DPLL_VCO_ENABLE
;
4583 I915_WRITE(DPLL(pipe
), dpll
& ~DPLL_VCO_ENABLE
);
4584 POSTING_READ(DPLL(pipe
));
4587 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
4588 if (encoder
->pre_pll_enable
)
4589 encoder
->pre_pll_enable(encoder
);
4591 I915_WRITE(DPLL(pipe
), dpll
);
4593 /* Wait for the clocks to stabilize. */
4594 POSTING_READ(DPLL(pipe
));
4597 /* The pixel multiplier can only be updated once the
4598 * DPLL is enabled and the clocks are stable.
4600 * So write it again.
4602 I915_WRITE(DPLL(pipe
), dpll
);
4605 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
,
4606 struct drm_display_mode
*mode
,
4607 struct drm_display_mode
*adjusted_mode
)
4609 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4610 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4611 enum pipe pipe
= intel_crtc
->pipe
;
4612 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
4613 uint32_t vsyncshift
;
4615 if (!IS_GEN2(dev
) && adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
4616 /* the chip adds 2 halflines automatically */
4617 adjusted_mode
->crtc_vtotal
-= 1;
4618 adjusted_mode
->crtc_vblank_end
-= 1;
4619 vsyncshift
= adjusted_mode
->crtc_hsync_start
4620 - adjusted_mode
->crtc_htotal
/ 2;
4625 if (INTEL_INFO(dev
)->gen
> 3)
4626 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
4628 I915_WRITE(HTOTAL(cpu_transcoder
),
4629 (adjusted_mode
->crtc_hdisplay
- 1) |
4630 ((adjusted_mode
->crtc_htotal
- 1) << 16));
4631 I915_WRITE(HBLANK(cpu_transcoder
),
4632 (adjusted_mode
->crtc_hblank_start
- 1) |
4633 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
4634 I915_WRITE(HSYNC(cpu_transcoder
),
4635 (adjusted_mode
->crtc_hsync_start
- 1) |
4636 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
4638 I915_WRITE(VTOTAL(cpu_transcoder
),
4639 (adjusted_mode
->crtc_vdisplay
- 1) |
4640 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
4641 I915_WRITE(VBLANK(cpu_transcoder
),
4642 (adjusted_mode
->crtc_vblank_start
- 1) |
4643 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
4644 I915_WRITE(VSYNC(cpu_transcoder
),
4645 (adjusted_mode
->crtc_vsync_start
- 1) |
4646 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
4648 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4649 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4650 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4652 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
4653 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
4654 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
4656 /* pipesrc controls the size that is scaled from, which should
4657 * always be the user's requested size.
4659 I915_WRITE(PIPESRC(pipe
),
4660 ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
4663 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
4665 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4666 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4669 pipeconf
= I915_READ(PIPECONF(intel_crtc
->pipe
));
4671 if (intel_crtc
->pipe
== 0 && INTEL_INFO(dev
)->gen
< 4) {
4672 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4675 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4678 if (intel_crtc
->config
.requested_mode
.clock
>
4679 dev_priv
->display
.get_display_clock_speed(dev
) * 9 / 10)
4680 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
4682 pipeconf
&= ~PIPECONF_DOUBLE_WIDE
;
4685 /* default to 8bpc */
4686 pipeconf
&= ~(PIPECONF_BPC_MASK
| PIPECONF_DITHER_EN
);
4687 if (intel_crtc
->config
.has_dp_encoder
) {
4688 if (intel_crtc
->config
.dither
) {
4689 pipeconf
|= PIPECONF_6BPC
|
4690 PIPECONF_DITHER_EN
|
4691 PIPECONF_DITHER_TYPE_SP
;
4695 if (IS_VALLEYVIEW(dev
) && intel_pipe_has_type(&intel_crtc
->base
,
4696 INTEL_OUTPUT_EDP
)) {
4697 if (intel_crtc
->config
.dither
) {
4698 pipeconf
|= PIPECONF_6BPC
|
4700 I965_PIPECONF_ACTIVE
;
4704 if (HAS_PIPE_CXSR(dev
)) {
4705 if (intel_crtc
->lowfreq_avail
) {
4706 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4707 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
4709 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4710 pipeconf
&= ~PIPECONF_CXSR_DOWNCLOCK
;
4714 pipeconf
&= ~PIPECONF_INTERLACE_MASK
;
4715 if (!IS_GEN2(dev
) &&
4716 intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
4717 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
4719 pipeconf
|= PIPECONF_PROGRESSIVE
;
4721 if (IS_VALLEYVIEW(dev
)) {
4722 if (intel_crtc
->config
.limited_color_range
)
4723 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
4725 pipeconf
&= ~PIPECONF_COLOR_RANGE_SELECT
;
4728 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
4729 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
4732 static int i9xx_crtc_mode_set(struct drm_crtc
*crtc
,
4734 struct drm_framebuffer
*fb
)
4736 struct drm_device
*dev
= crtc
->dev
;
4737 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4738 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4739 struct drm_display_mode
*adjusted_mode
=
4740 &intel_crtc
->config
.adjusted_mode
;
4741 struct drm_display_mode
*mode
= &intel_crtc
->config
.requested_mode
;
4742 int pipe
= intel_crtc
->pipe
;
4743 int plane
= intel_crtc
->plane
;
4744 int refclk
, num_connectors
= 0;
4745 intel_clock_t clock
, reduced_clock
;
4747 bool ok
, has_reduced_clock
= false, is_sdvo
= false;
4748 bool is_lvds
= false, is_tv
= false;
4749 struct intel_encoder
*encoder
;
4750 const intel_limit_t
*limit
;
4753 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4754 switch (encoder
->type
) {
4755 case INTEL_OUTPUT_LVDS
:
4758 case INTEL_OUTPUT_SDVO
:
4759 case INTEL_OUTPUT_HDMI
:
4761 if (encoder
->needs_tv_clock
)
4764 case INTEL_OUTPUT_TVOUT
:
4772 refclk
= i9xx_get_refclk(crtc
, num_connectors
);
4775 * Returns a set of divisors for the desired target clock with the given
4776 * refclk, or FALSE. The returned values represent the clock equation:
4777 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4779 limit
= intel_limit(crtc
, refclk
);
4780 ok
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, NULL
,
4783 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4787 /* Ensure that the cursor is valid for the new mode before changing... */
4788 intel_crtc_update_cursor(crtc
, true);
4790 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
4792 * Ensure we match the reduced clock's P to the target clock.
4793 * If the clocks don't match, we can't switch the display clock
4794 * by using the FP0/FP1. In such case we will disable the LVDS
4795 * downclock feature.
4797 has_reduced_clock
= limit
->find_pll(limit
, crtc
,
4798 dev_priv
->lvds_downclock
,
4803 /* Compat-code for transition, will disappear. */
4804 if (!intel_crtc
->config
.clock_set
) {
4805 intel_crtc
->config
.dpll
.n
= clock
.n
;
4806 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
4807 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
4808 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
4809 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
4812 if (is_sdvo
&& is_tv
)
4813 i9xx_adjust_sdvo_tv_clock(intel_crtc
);
4816 i8xx_update_pll(intel_crtc
, adjusted_mode
,
4817 has_reduced_clock
? &reduced_clock
: NULL
,
4819 else if (IS_VALLEYVIEW(dev
))
4820 vlv_update_pll(intel_crtc
);
4822 i9xx_update_pll(intel_crtc
,
4823 has_reduced_clock
? &reduced_clock
: NULL
,
4826 /* Set up the display plane register */
4827 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
4829 if (!IS_VALLEYVIEW(dev
)) {
4831 dspcntr
&= ~DISPPLANE_SEL_PIPE_MASK
;
4833 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
4836 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe
));
4837 drm_mode_debug_printmodeline(mode
);
4839 intel_set_pipe_timings(intel_crtc
, mode
, adjusted_mode
);
4841 /* pipesrc and dspsize control the size that is scaled from,
4842 * which should always be the user's requested size.
4844 I915_WRITE(DSPSIZE(plane
),
4845 ((mode
->vdisplay
- 1) << 16) |
4846 (mode
->hdisplay
- 1));
4847 I915_WRITE(DSPPOS(plane
), 0);
4849 i9xx_set_pipeconf(intel_crtc
);
4851 I915_WRITE(DSPCNTR(plane
), dspcntr
);
4852 POSTING_READ(DSPCNTR(plane
));
4854 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
4856 intel_update_watermarks(dev
);
4861 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
4862 struct intel_crtc_config
*pipe_config
)
4864 struct drm_device
*dev
= crtc
->base
.dev
;
4865 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4868 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
4869 if (!(tmp
& PIPECONF_ENABLE
))
4875 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
4877 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4878 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
4879 struct intel_encoder
*encoder
;
4881 bool has_lvds
= false;
4882 bool has_cpu_edp
= false;
4883 bool has_pch_edp
= false;
4884 bool has_panel
= false;
4885 bool has_ck505
= false;
4886 bool can_ssc
= false;
4888 /* We need to take the global config into account */
4889 list_for_each_entry(encoder
, &mode_config
->encoder_list
,
4891 switch (encoder
->type
) {
4892 case INTEL_OUTPUT_LVDS
:
4896 case INTEL_OUTPUT_EDP
:
4898 if (intel_encoder_is_pch_edp(&encoder
->base
))
4906 if (HAS_PCH_IBX(dev
)) {
4907 has_ck505
= dev_priv
->display_clock_mode
;
4908 can_ssc
= has_ck505
;
4914 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4915 has_panel
, has_lvds
, has_pch_edp
, has_cpu_edp
,
4918 /* Ironlake: try to setup display ref clock before DPLL
4919 * enabling. This is only under driver's control after
4920 * PCH B stepping, previous chipset stepping should be
4921 * ignoring this setting.
4923 val
= I915_READ(PCH_DREF_CONTROL
);
4925 /* As we must carefully and slowly disable/enable each source in turn,
4926 * compute the final state we want first and check if we need to
4927 * make any changes at all.
4930 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
4932 final
|= DREF_NONSPREAD_CK505_ENABLE
;
4934 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
4936 final
&= ~DREF_SSC_SOURCE_MASK
;
4937 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
4938 final
&= ~DREF_SSC1_ENABLE
;
4941 final
|= DREF_SSC_SOURCE_ENABLE
;
4943 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
4944 final
|= DREF_SSC1_ENABLE
;
4947 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
4948 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
4950 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
4952 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
4954 final
|= DREF_SSC_SOURCE_DISABLE
;
4955 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
4961 /* Always enable nonspread source */
4962 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
4965 val
|= DREF_NONSPREAD_CK505_ENABLE
;
4967 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
4970 val
&= ~DREF_SSC_SOURCE_MASK
;
4971 val
|= DREF_SSC_SOURCE_ENABLE
;
4973 /* SSC must be turned on before enabling the CPU output */
4974 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
4975 DRM_DEBUG_KMS("Using SSC on panel\n");
4976 val
|= DREF_SSC1_ENABLE
;
4978 val
&= ~DREF_SSC1_ENABLE
;
4980 /* Get SSC going before enabling the outputs */
4981 I915_WRITE(PCH_DREF_CONTROL
, val
);
4982 POSTING_READ(PCH_DREF_CONTROL
);
4985 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
4987 /* Enable CPU source on CPU attached eDP */
4989 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
4990 DRM_DEBUG_KMS("Using SSC on eDP\n");
4991 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
4994 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
4996 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
4998 I915_WRITE(PCH_DREF_CONTROL
, val
);
4999 POSTING_READ(PCH_DREF_CONTROL
);
5002 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5004 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
5006 /* Turn off CPU output */
5007 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5009 I915_WRITE(PCH_DREF_CONTROL
, val
);
5010 POSTING_READ(PCH_DREF_CONTROL
);
5013 /* Turn off the SSC source */
5014 val
&= ~DREF_SSC_SOURCE_MASK
;
5015 val
|= DREF_SSC_SOURCE_DISABLE
;
5018 val
&= ~DREF_SSC1_ENABLE
;
5020 I915_WRITE(PCH_DREF_CONTROL
, val
);
5021 POSTING_READ(PCH_DREF_CONTROL
);
5025 BUG_ON(val
!= final
);
5028 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5029 static void lpt_init_pch_refclk(struct drm_device
*dev
)
5031 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5032 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
5033 struct intel_encoder
*encoder
;
5034 bool has_vga
= false;
5035 bool is_sdv
= false;
5038 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
) {
5039 switch (encoder
->type
) {
5040 case INTEL_OUTPUT_ANALOG
:
5049 mutex_lock(&dev_priv
->dpio_lock
);
5051 /* XXX: Rip out SDV support once Haswell ships for real. */
5052 if (IS_HASWELL(dev
) && (dev
->pci_device
& 0xFF00) == 0x0C00)
5055 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
5056 tmp
&= ~SBI_SSCCTL_DISABLE
;
5057 tmp
|= SBI_SSCCTL_PATHALT
;
5058 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5062 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
5063 tmp
&= ~SBI_SSCCTL_PATHALT
;
5064 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5067 tmp
= I915_READ(SOUTH_CHICKEN2
);
5068 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
5069 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
5071 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
5072 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
5073 DRM_ERROR("FDI mPHY reset assert timeout\n");
5075 tmp
= I915_READ(SOUTH_CHICKEN2
);
5076 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
5077 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
5079 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
5080 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0,
5082 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5085 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
5086 tmp
&= ~(0xFF << 24);
5087 tmp
|= (0x12 << 24);
5088 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
5091 tmp
= intel_sbi_read(dev_priv
, 0x800C, SBI_MPHY
);
5093 intel_sbi_write(dev_priv
, 0x800C, tmp
, SBI_MPHY
);
5096 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
5098 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
5100 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
5102 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
5105 tmp
= intel_sbi_read(dev_priv
, 0x2038, SBI_MPHY
);
5106 tmp
|= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5107 intel_sbi_write(dev_priv
, 0x2038, tmp
, SBI_MPHY
);
5109 tmp
= intel_sbi_read(dev_priv
, 0x2138, SBI_MPHY
);
5110 tmp
|= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5111 intel_sbi_write(dev_priv
, 0x2138, tmp
, SBI_MPHY
);
5113 tmp
= intel_sbi_read(dev_priv
, 0x203C, SBI_MPHY
);
5115 intel_sbi_write(dev_priv
, 0x203C, tmp
, SBI_MPHY
);
5117 tmp
= intel_sbi_read(dev_priv
, 0x213C, SBI_MPHY
);
5119 intel_sbi_write(dev_priv
, 0x213C, tmp
, SBI_MPHY
);
5122 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
5123 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
5124 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
5126 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
5127 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
5128 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
5131 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
5134 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
5136 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
5139 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
5142 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
5145 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
5147 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
5150 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
5152 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
5153 tmp
&= ~(0xFF << 16);
5154 tmp
|= (0x1C << 16);
5155 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
5157 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
5158 tmp
&= ~(0xFF << 16);
5159 tmp
|= (0x1C << 16);
5160 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
5163 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
5165 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
5167 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
5169 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
5171 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
5172 tmp
&= ~(0xF << 28);
5174 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
5176 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
5177 tmp
&= ~(0xF << 28);
5179 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
5182 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5183 tmp
= intel_sbi_read(dev_priv
, SBI_DBUFF0
, SBI_ICLK
);
5184 tmp
|= SBI_DBUFF0_ENABLE
;
5185 intel_sbi_write(dev_priv
, SBI_DBUFF0
, tmp
, SBI_ICLK
);
5187 mutex_unlock(&dev_priv
->dpio_lock
);
5191 * Initialize reference clocks when the driver loads
5193 void intel_init_pch_refclk(struct drm_device
*dev
)
5195 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
5196 ironlake_init_pch_refclk(dev
);
5197 else if (HAS_PCH_LPT(dev
))
5198 lpt_init_pch_refclk(dev
);
5201 static int ironlake_get_refclk(struct drm_crtc
*crtc
)
5203 struct drm_device
*dev
= crtc
->dev
;
5204 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5205 struct intel_encoder
*encoder
;
5206 struct intel_encoder
*edp_encoder
= NULL
;
5207 int num_connectors
= 0;
5208 bool is_lvds
= false;
5210 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5211 switch (encoder
->type
) {
5212 case INTEL_OUTPUT_LVDS
:
5215 case INTEL_OUTPUT_EDP
:
5216 edp_encoder
= encoder
;
5222 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
5223 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5224 dev_priv
->lvds_ssc_freq
);
5225 return dev_priv
->lvds_ssc_freq
* 1000;
5231 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
,
5232 struct drm_display_mode
*adjusted_mode
,
5235 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
5236 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5237 int pipe
= intel_crtc
->pipe
;
5240 val
= I915_READ(PIPECONF(pipe
));
5242 val
&= ~PIPECONF_BPC_MASK
;
5243 switch (intel_crtc
->config
.pipe_bpp
) {
5245 val
|= PIPECONF_6BPC
;
5248 val
|= PIPECONF_8BPC
;
5251 val
|= PIPECONF_10BPC
;
5254 val
|= PIPECONF_12BPC
;
5257 /* Case prevented by intel_choose_pipe_bpp_dither. */
5261 val
&= ~(PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_MASK
);
5263 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
5265 val
&= ~PIPECONF_INTERLACE_MASK
;
5266 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
5267 val
|= PIPECONF_INTERLACED_ILK
;
5269 val
|= PIPECONF_PROGRESSIVE
;
5271 if (intel_crtc
->config
.limited_color_range
)
5272 val
|= PIPECONF_COLOR_RANGE_SELECT
;
5274 val
&= ~PIPECONF_COLOR_RANGE_SELECT
;
5276 I915_WRITE(PIPECONF(pipe
), val
);
5277 POSTING_READ(PIPECONF(pipe
));
5281 * Set up the pipe CSC unit.
5283 * Currently only full range RGB to limited range RGB conversion
5284 * is supported, but eventually this should handle various
5285 * RGB<->YCbCr scenarios as well.
5287 static void intel_set_pipe_csc(struct drm_crtc
*crtc
)
5289 struct drm_device
*dev
= crtc
->dev
;
5290 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5291 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5292 int pipe
= intel_crtc
->pipe
;
5293 uint16_t coeff
= 0x7800; /* 1.0 */
5296 * TODO: Check what kind of values actually come out of the pipe
5297 * with these coeff/postoff values and adjust to get the best
5298 * accuracy. Perhaps we even need to take the bpc value into
5302 if (intel_crtc
->config
.limited_color_range
)
5303 coeff
= ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5306 * GY/GU and RY/RU should be the other way around according
5307 * to BSpec, but reality doesn't agree. Just set them up in
5308 * a way that results in the correct picture.
5310 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeff
<< 16);
5311 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), 0);
5313 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeff
);
5314 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), 0);
5316 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), 0);
5317 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeff
<< 16);
5319 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
5320 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
5321 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
5323 if (INTEL_INFO(dev
)->gen
> 6) {
5324 uint16_t postoff
= 0;
5326 if (intel_crtc
->config
.limited_color_range
)
5327 postoff
= (16 * (1 << 13) / 255) & 0x1fff;
5329 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
5330 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
5331 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
5333 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
5335 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
5337 if (intel_crtc
->config
.limited_color_range
)
5338 mode
|= CSC_BLACK_SCREEN_OFFSET
;
5340 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
5344 static void haswell_set_pipeconf(struct drm_crtc
*crtc
,
5345 struct drm_display_mode
*adjusted_mode
,
5348 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
5349 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5350 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
5353 val
= I915_READ(PIPECONF(cpu_transcoder
));
5355 val
&= ~(PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_MASK
);
5357 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
5359 val
&= ~PIPECONF_INTERLACE_MASK_HSW
;
5360 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
5361 val
|= PIPECONF_INTERLACED_ILK
;
5363 val
|= PIPECONF_PROGRESSIVE
;
5365 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
5366 POSTING_READ(PIPECONF(cpu_transcoder
));
5369 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
5370 struct drm_display_mode
*adjusted_mode
,
5371 intel_clock_t
*clock
,
5372 bool *has_reduced_clock
,
5373 intel_clock_t
*reduced_clock
)
5375 struct drm_device
*dev
= crtc
->dev
;
5376 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5377 struct intel_encoder
*intel_encoder
;
5379 const intel_limit_t
*limit
;
5380 bool ret
, is_sdvo
= false, is_tv
= false, is_lvds
= false;
5382 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5383 switch (intel_encoder
->type
) {
5384 case INTEL_OUTPUT_LVDS
:
5387 case INTEL_OUTPUT_SDVO
:
5388 case INTEL_OUTPUT_HDMI
:
5390 if (intel_encoder
->needs_tv_clock
)
5393 case INTEL_OUTPUT_TVOUT
:
5399 refclk
= ironlake_get_refclk(crtc
);
5402 * Returns a set of divisors for the desired target clock with the given
5403 * refclk, or FALSE. The returned values represent the clock equation:
5404 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5406 limit
= intel_limit(crtc
, refclk
);
5407 ret
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, NULL
,
5412 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
5414 * Ensure we match the reduced clock's P to the target clock.
5415 * If the clocks don't match, we can't switch the display clock
5416 * by using the FP0/FP1. In such case we will disable the LVDS
5417 * downclock feature.
5419 *has_reduced_clock
= limit
->find_pll(limit
, crtc
,
5420 dev_priv
->lvds_downclock
,
5426 if (is_sdvo
&& is_tv
)
5427 i9xx_adjust_sdvo_tv_clock(to_intel_crtc(crtc
));
5432 static void cpt_enable_fdi_bc_bifurcation(struct drm_device
*dev
)
5434 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5437 temp
= I915_READ(SOUTH_CHICKEN1
);
5438 if (temp
& FDI_BC_BIFURCATION_SELECT
)
5441 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
5442 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
5444 temp
|= FDI_BC_BIFURCATION_SELECT
;
5445 DRM_DEBUG_KMS("enabling fdi C rx\n");
5446 I915_WRITE(SOUTH_CHICKEN1
, temp
);
5447 POSTING_READ(SOUTH_CHICKEN1
);
5450 static bool ironlake_check_fdi_lanes(struct intel_crtc
*intel_crtc
)
5452 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5453 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5454 struct intel_crtc
*pipe_B_crtc
=
5455 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
5457 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5458 pipe_name(intel_crtc
->pipe
), intel_crtc
->fdi_lanes
);
5459 if (intel_crtc
->fdi_lanes
> 4) {
5460 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5461 pipe_name(intel_crtc
->pipe
), intel_crtc
->fdi_lanes
);
5462 /* Clamp lanes to avoid programming the hw with bogus values. */
5463 intel_crtc
->fdi_lanes
= 4;
5468 if (INTEL_INFO(dev
)->num_pipes
== 2)
5471 switch (intel_crtc
->pipe
) {
5475 if (dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]->enabled
&&
5476 intel_crtc
->fdi_lanes
> 2) {
5477 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5478 pipe_name(intel_crtc
->pipe
), intel_crtc
->fdi_lanes
);
5479 /* Clamp lanes to avoid programming the hw with bogus values. */
5480 intel_crtc
->fdi_lanes
= 2;
5485 if (intel_crtc
->fdi_lanes
> 2)
5486 WARN_ON(I915_READ(SOUTH_CHICKEN1
) & FDI_BC_BIFURCATION_SELECT
);
5488 cpt_enable_fdi_bc_bifurcation(dev
);
5492 if (!pipe_B_crtc
->base
.enabled
|| pipe_B_crtc
->fdi_lanes
<= 2) {
5493 if (intel_crtc
->fdi_lanes
> 2) {
5494 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5495 pipe_name(intel_crtc
->pipe
), intel_crtc
->fdi_lanes
);
5496 /* Clamp lanes to avoid programming the hw with bogus values. */
5497 intel_crtc
->fdi_lanes
= 2;
5502 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5506 cpt_enable_fdi_bc_bifurcation(dev
);
5514 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
5517 * Account for spread spectrum to avoid
5518 * oversubscribing the link. Max center spread
5519 * is 2.5%; use 5% for safety's sake.
5521 u32 bps
= target_clock
* bpp
* 21 / 20;
5522 return bps
/ (link_bw
* 8) + 1;
5525 void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
5526 struct intel_link_m_n
*m_n
)
5528 struct drm_device
*dev
= crtc
->base
.dev
;
5529 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5530 int pipe
= crtc
->pipe
;
5532 I915_WRITE(TRANSDATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5533 I915_WRITE(TRANSDATA_N1(pipe
), m_n
->gmch_n
);
5534 I915_WRITE(TRANSDPLINK_M1(pipe
), m_n
->link_m
);
5535 I915_WRITE(TRANSDPLINK_N1(pipe
), m_n
->link_n
);
5538 void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
5539 struct intel_link_m_n
*m_n
)
5541 struct drm_device
*dev
= crtc
->base
.dev
;
5542 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5543 int pipe
= crtc
->pipe
;
5544 enum transcoder transcoder
= crtc
->config
.cpu_transcoder
;
5546 if (INTEL_INFO(dev
)->gen
>= 5) {
5547 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5548 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
5549 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
5550 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
5552 I915_WRITE(PIPE_GMCH_DATA_M(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5553 I915_WRITE(PIPE_GMCH_DATA_N(pipe
), m_n
->gmch_n
);
5554 I915_WRITE(PIPE_DP_LINK_M(pipe
), m_n
->link_m
);
5555 I915_WRITE(PIPE_DP_LINK_N(pipe
), m_n
->link_n
);
5559 static void ironlake_fdi_set_m_n(struct drm_crtc
*crtc
)
5561 struct drm_device
*dev
= crtc
->dev
;
5562 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5563 struct drm_display_mode
*adjusted_mode
=
5564 &intel_crtc
->config
.adjusted_mode
;
5565 struct intel_link_m_n m_n
= {0};
5566 int target_clock
, lane
, link_bw
;
5568 /* FDI is a binary signal running at ~2.7GHz, encoding
5569 * each output octet as 10 bits. The actual frequency
5570 * is stored as a divider into a 100MHz clock, and the
5571 * mode pixel clock is stored in units of 1KHz.
5572 * Hence the bw of each lane in terms of the mode signal
5575 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
5577 if (intel_crtc
->config
.pixel_target_clock
)
5578 target_clock
= intel_crtc
->config
.pixel_target_clock
;
5580 target_clock
= adjusted_mode
->clock
;
5582 lane
= ironlake_get_lanes_required(target_clock
, link_bw
,
5583 intel_crtc
->config
.pipe_bpp
);
5585 intel_crtc
->fdi_lanes
= lane
;
5587 if (intel_crtc
->config
.pixel_multiplier
> 1)
5588 link_bw
*= intel_crtc
->config
.pixel_multiplier
;
5589 intel_link_compute_m_n(intel_crtc
->config
.pipe_bpp
, lane
, target_clock
,
5592 intel_cpu_transcoder_set_m_n(intel_crtc
, &m_n
);
5595 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
5596 intel_clock_t
*clock
, u32
*fp
,
5597 intel_clock_t
*reduced_clock
, u32
*fp2
)
5599 struct drm_crtc
*crtc
= &intel_crtc
->base
;
5600 struct drm_device
*dev
= crtc
->dev
;
5601 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5602 struct intel_encoder
*intel_encoder
;
5604 int factor
, num_connectors
= 0;
5605 bool is_lvds
= false, is_sdvo
= false, is_tv
= false;
5607 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5608 switch (intel_encoder
->type
) {
5609 case INTEL_OUTPUT_LVDS
:
5612 case INTEL_OUTPUT_SDVO
:
5613 case INTEL_OUTPUT_HDMI
:
5615 if (intel_encoder
->needs_tv_clock
)
5618 case INTEL_OUTPUT_TVOUT
:
5626 /* Enable autotuning of the PLL clock (if permissible) */
5629 if ((intel_panel_use_ssc(dev_priv
) &&
5630 dev_priv
->lvds_ssc_freq
== 100) ||
5631 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
5633 } else if (is_sdvo
&& is_tv
)
5636 if (clock
->m
< factor
* clock
->n
)
5639 if (fp2
&& (reduced_clock
->m
< factor
* reduced_clock
->n
))
5645 dpll
|= DPLLB_MODE_LVDS
;
5647 dpll
|= DPLLB_MODE_DAC_SERIAL
;
5649 if (intel_crtc
->config
.pixel_multiplier
> 1) {
5650 dpll
|= (intel_crtc
->config
.pixel_multiplier
- 1)
5651 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
5653 dpll
|= DPLL_DVO_HIGH_SPEED
;
5655 if (intel_crtc
->config
.has_dp_encoder
&&
5656 intel_crtc
->config
.has_pch_encoder
)
5657 dpll
|= DPLL_DVO_HIGH_SPEED
;
5659 /* compute bitmask from p1 value */
5660 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5662 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
5664 switch (clock
->p2
) {
5666 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
5669 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
5672 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
5675 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
5679 if (is_sdvo
&& is_tv
)
5680 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
5682 /* XXX: just matching BIOS for now */
5683 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5685 else if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
5686 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
5688 dpll
|= PLL_REF_INPUT_DREFCLK
;
5693 static int ironlake_crtc_mode_set(struct drm_crtc
*crtc
,
5695 struct drm_framebuffer
*fb
)
5697 struct drm_device
*dev
= crtc
->dev
;
5698 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5699 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5700 struct drm_display_mode
*adjusted_mode
=
5701 &intel_crtc
->config
.adjusted_mode
;
5702 struct drm_display_mode
*mode
= &intel_crtc
->config
.requested_mode
;
5703 int pipe
= intel_crtc
->pipe
;
5704 int plane
= intel_crtc
->plane
;
5705 int num_connectors
= 0;
5706 intel_clock_t clock
, reduced_clock
;
5707 u32 dpll
= 0, fp
= 0, fp2
= 0;
5708 bool ok
, has_reduced_clock
= false;
5709 bool is_lvds
= false;
5710 struct intel_encoder
*encoder
;
5712 bool dither
, fdi_config_ok
;
5714 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5715 switch (encoder
->type
) {
5716 case INTEL_OUTPUT_LVDS
:
5724 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
5725 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
5727 intel_crtc
->config
.cpu_transcoder
= pipe
;
5729 ok
= ironlake_compute_clocks(crtc
, adjusted_mode
, &clock
,
5730 &has_reduced_clock
, &reduced_clock
);
5732 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5735 /* Compat-code for transition, will disappear. */
5736 if (!intel_crtc
->config
.clock_set
) {
5737 intel_crtc
->config
.dpll
.n
= clock
.n
;
5738 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
5739 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
5740 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
5741 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
5744 /* Ensure that the cursor is valid for the new mode before changing... */
5745 intel_crtc_update_cursor(crtc
, true);
5747 /* determine panel color depth */
5748 dither
= intel_crtc
->config
.dither
;
5749 if (is_lvds
&& dev_priv
->lvds_dither
)
5752 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe
));
5753 drm_mode_debug_printmodeline(mode
);
5755 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5756 if (intel_crtc
->config
.has_pch_encoder
) {
5757 struct intel_pch_pll
*pll
;
5759 fp
= clock
.n
<< 16 | clock
.m1
<< 8 | clock
.m2
;
5760 if (has_reduced_clock
)
5761 fp2
= reduced_clock
.n
<< 16 | reduced_clock
.m1
<< 8 |
5764 dpll
= ironlake_compute_dpll(intel_crtc
, &clock
,
5765 &fp
, &reduced_clock
,
5766 has_reduced_clock
? &fp2
: NULL
);
5768 pll
= intel_get_pch_pll(intel_crtc
, dpll
, fp
);
5770 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5775 intel_put_pch_pll(intel_crtc
);
5777 if (intel_crtc
->config
.has_dp_encoder
)
5778 intel_dp_set_m_n(intel_crtc
);
5780 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5781 if (encoder
->pre_pll_enable
)
5782 encoder
->pre_pll_enable(encoder
);
5784 if (intel_crtc
->pch_pll
) {
5785 I915_WRITE(intel_crtc
->pch_pll
->pll_reg
, dpll
);
5787 /* Wait for the clocks to stabilize. */
5788 POSTING_READ(intel_crtc
->pch_pll
->pll_reg
);
5791 /* The pixel multiplier can only be updated once the
5792 * DPLL is enabled and the clocks are stable.
5794 * So write it again.
5796 I915_WRITE(intel_crtc
->pch_pll
->pll_reg
, dpll
);
5799 intel_crtc
->lowfreq_avail
= false;
5800 if (intel_crtc
->pch_pll
) {
5801 if (is_lvds
&& has_reduced_clock
&& i915_powersave
) {
5802 I915_WRITE(intel_crtc
->pch_pll
->fp1_reg
, fp2
);
5803 intel_crtc
->lowfreq_avail
= true;
5805 I915_WRITE(intel_crtc
->pch_pll
->fp1_reg
, fp
);
5809 intel_set_pipe_timings(intel_crtc
, mode
, adjusted_mode
);
5811 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5812 * ironlake_check_fdi_lanes. */
5813 intel_crtc
->fdi_lanes
= 0;
5814 if (intel_crtc
->config
.has_pch_encoder
)
5815 ironlake_fdi_set_m_n(crtc
);
5817 fdi_config_ok
= ironlake_check_fdi_lanes(intel_crtc
);
5819 ironlake_set_pipeconf(crtc
, adjusted_mode
, dither
);
5821 /* Set up the display plane register */
5822 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
);
5823 POSTING_READ(DSPCNTR(plane
));
5825 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
5827 intel_update_watermarks(dev
);
5829 intel_update_linetime_watermarks(dev
, pipe
, adjusted_mode
);
5831 return fdi_config_ok
? ret
: -EINVAL
;
5834 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
5835 struct intel_crtc_config
*pipe_config
)
5837 struct drm_device
*dev
= crtc
->base
.dev
;
5838 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5841 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
5842 if (!(tmp
& PIPECONF_ENABLE
))
5845 if (I915_READ(TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
)
5846 pipe_config
->has_pch_encoder
= true;
5851 static void haswell_modeset_global_resources(struct drm_device
*dev
)
5853 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5854 bool enable
= false;
5855 struct intel_crtc
*crtc
;
5856 struct intel_encoder
*encoder
;
5858 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
5859 if (crtc
->pipe
!= PIPE_A
&& crtc
->base
.enabled
)
5861 /* XXX: Should check for edp transcoder here, but thanks to init
5862 * sequence that's not yet available. Just in case desktop eDP
5863 * on PORT D is possible on haswell, too. */
5866 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
5868 if (encoder
->type
!= INTEL_OUTPUT_EDP
&&
5869 encoder
->connectors_active
)
5873 /* Even the eDP panel fitter is outside the always-on well. */
5874 if (dev_priv
->pch_pf_size
)
5877 intel_set_power_well(dev
, enable
);
5880 static int haswell_crtc_mode_set(struct drm_crtc
*crtc
,
5882 struct drm_framebuffer
*fb
)
5884 struct drm_device
*dev
= crtc
->dev
;
5885 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5886 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5887 struct drm_display_mode
*adjusted_mode
=
5888 &intel_crtc
->config
.adjusted_mode
;
5889 struct drm_display_mode
*mode
= &intel_crtc
->config
.requested_mode
;
5890 int pipe
= intel_crtc
->pipe
;
5891 int plane
= intel_crtc
->plane
;
5892 int num_connectors
= 0;
5893 bool is_cpu_edp
= false;
5894 struct intel_encoder
*encoder
;
5898 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5899 switch (encoder
->type
) {
5900 case INTEL_OUTPUT_EDP
:
5901 if (!intel_encoder_is_pch_edp(&encoder
->base
))
5910 intel_crtc
->config
.cpu_transcoder
= TRANSCODER_EDP
;
5912 intel_crtc
->config
.cpu_transcoder
= pipe
;
5914 /* We are not sure yet this won't happen. */
5915 WARN(!HAS_PCH_LPT(dev
), "Unexpected PCH type %d\n",
5916 INTEL_PCH_TYPE(dev
));
5918 WARN(num_connectors
!= 1, "%d connectors attached to pipe %c\n",
5919 num_connectors
, pipe_name(pipe
));
5921 WARN_ON(I915_READ(PIPECONF(intel_crtc
->config
.cpu_transcoder
)) &
5922 (PIPECONF_ENABLE
| I965_PIPECONF_ACTIVE
));
5924 WARN_ON(I915_READ(DSPCNTR(plane
)) & DISPLAY_PLANE_ENABLE
);
5926 if (!intel_ddi_pll_mode_set(crtc
, adjusted_mode
->clock
))
5929 /* Ensure that the cursor is valid for the new mode before changing... */
5930 intel_crtc_update_cursor(crtc
, true);
5932 /* determine panel color depth */
5933 dither
= intel_crtc
->config
.dither
;
5935 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe
));
5936 drm_mode_debug_printmodeline(mode
);
5938 if (intel_crtc
->config
.has_dp_encoder
)
5939 intel_dp_set_m_n(intel_crtc
);
5941 intel_crtc
->lowfreq_avail
= false;
5943 intel_set_pipe_timings(intel_crtc
, mode
, adjusted_mode
);
5945 if (intel_crtc
->config
.has_pch_encoder
)
5946 ironlake_fdi_set_m_n(crtc
);
5948 haswell_set_pipeconf(crtc
, adjusted_mode
, dither
);
5950 intel_set_pipe_csc(crtc
);
5952 /* Set up the display plane register */
5953 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
| DISPPLANE_PIPE_CSC_ENABLE
);
5954 POSTING_READ(DSPCNTR(plane
));
5956 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
5958 intel_update_watermarks(dev
);
5960 intel_update_linetime_watermarks(dev
, pipe
, adjusted_mode
);
5965 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
5966 struct intel_crtc_config
*pipe_config
)
5968 struct drm_device
*dev
= crtc
->base
.dev
;
5969 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5970 enum transcoder cpu_transcoder
= crtc
->config
.cpu_transcoder
;
5973 if (!intel_using_power_well(dev_priv
->dev
) &&
5974 cpu_transcoder
!= TRANSCODER_EDP
)
5977 tmp
= I915_READ(PIPECONF(cpu_transcoder
));
5978 if (!(tmp
& PIPECONF_ENABLE
))
5982 * Haswell has only FDI/PCH transcoder A. It is which is connected to
5983 * DDI E. So just check whether this pipe is wired to DDI E and whether
5984 * the PCH transcoder is on.
5986 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
5987 if ((tmp
& TRANS_DDI_PORT_MASK
) == TRANS_DDI_SELECT_PORT(PORT_E
) &&
5988 I915_READ(TRANSCONF(PIPE_A
)) & TRANS_ENABLE
)
5989 pipe_config
->has_pch_encoder
= true;
5994 static int intel_crtc_mode_set(struct drm_crtc
*crtc
,
5996 struct drm_framebuffer
*fb
)
5998 struct drm_device
*dev
= crtc
->dev
;
5999 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6000 struct drm_encoder_helper_funcs
*encoder_funcs
;
6001 struct intel_encoder
*encoder
;
6002 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6003 struct drm_display_mode
*adjusted_mode
=
6004 &intel_crtc
->config
.adjusted_mode
;
6005 struct drm_display_mode
*mode
= &intel_crtc
->config
.requested_mode
;
6006 int pipe
= intel_crtc
->pipe
;
6009 drm_vblank_pre_modeset(dev
, pipe
);
6011 ret
= dev_priv
->display
.crtc_mode_set(crtc
, x
, y
, fb
);
6013 drm_vblank_post_modeset(dev
, pipe
);
6018 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
6019 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6020 encoder
->base
.base
.id
,
6021 drm_get_encoder_name(&encoder
->base
),
6022 mode
->base
.id
, mode
->name
);
6023 if (encoder
->mode_set
) {
6024 encoder
->mode_set(encoder
);
6026 encoder_funcs
= encoder
->base
.helper_private
;
6027 encoder_funcs
->mode_set(&encoder
->base
, mode
, adjusted_mode
);
6034 static bool intel_eld_uptodate(struct drm_connector
*connector
,
6035 int reg_eldv
, uint32_t bits_eldv
,
6036 int reg_elda
, uint32_t bits_elda
,
6039 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6040 uint8_t *eld
= connector
->eld
;
6043 i
= I915_READ(reg_eldv
);
6052 i
= I915_READ(reg_elda
);
6054 I915_WRITE(reg_elda
, i
);
6056 for (i
= 0; i
< eld
[2]; i
++)
6057 if (I915_READ(reg_edid
) != *((uint32_t *)eld
+ i
))
6063 static void g4x_write_eld(struct drm_connector
*connector
,
6064 struct drm_crtc
*crtc
)
6066 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6067 uint8_t *eld
= connector
->eld
;
6072 i
= I915_READ(G4X_AUD_VID_DID
);
6074 if (i
== INTEL_AUDIO_DEVBLC
|| i
== INTEL_AUDIO_DEVCL
)
6075 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
6077 eldv
= G4X_ELDV_DEVCTG
;
6079 if (intel_eld_uptodate(connector
,
6080 G4X_AUD_CNTL_ST
, eldv
,
6081 G4X_AUD_CNTL_ST
, G4X_ELD_ADDR
,
6082 G4X_HDMIW_HDMIEDID
))
6085 i
= I915_READ(G4X_AUD_CNTL_ST
);
6086 i
&= ~(eldv
| G4X_ELD_ADDR
);
6087 len
= (i
>> 9) & 0x1f; /* ELD buffer size */
6088 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
6093 len
= min_t(uint8_t, eld
[2], len
);
6094 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6095 for (i
= 0; i
< len
; i
++)
6096 I915_WRITE(G4X_HDMIW_HDMIEDID
, *((uint32_t *)eld
+ i
));
6098 i
= I915_READ(G4X_AUD_CNTL_ST
);
6100 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
6103 static void haswell_write_eld(struct drm_connector
*connector
,
6104 struct drm_crtc
*crtc
)
6106 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6107 uint8_t *eld
= connector
->eld
;
6108 struct drm_device
*dev
= crtc
->dev
;
6109 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6113 int pipe
= to_intel_crtc(crtc
)->pipe
;
6116 int hdmiw_hdmiedid
= HSW_AUD_EDID_DATA(pipe
);
6117 int aud_cntl_st
= HSW_AUD_DIP_ELD_CTRL(pipe
);
6118 int aud_config
= HSW_AUD_CFG(pipe
);
6119 int aud_cntrl_st2
= HSW_AUD_PIN_ELD_CP_VLD
;
6122 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6124 /* Audio output enable */
6125 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6126 tmp
= I915_READ(aud_cntrl_st2
);
6127 tmp
|= (AUDIO_OUTPUT_ENABLE_A
<< (pipe
* 4));
6128 I915_WRITE(aud_cntrl_st2
, tmp
);
6130 /* Wait for 1 vertical blank */
6131 intel_wait_for_vblank(dev
, pipe
);
6133 /* Set ELD valid state */
6134 tmp
= I915_READ(aud_cntrl_st2
);
6135 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp
);
6136 tmp
|= (AUDIO_ELD_VALID_A
<< (pipe
* 4));
6137 I915_WRITE(aud_cntrl_st2
, tmp
);
6138 tmp
= I915_READ(aud_cntrl_st2
);
6139 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp
);
6141 /* Enable HDMI mode */
6142 tmp
= I915_READ(aud_config
);
6143 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp
);
6144 /* clear N_programing_enable and N_value_index */
6145 tmp
&= ~(AUD_CONFIG_N_VALUE_INDEX
| AUD_CONFIG_N_PROG_ENABLE
);
6146 I915_WRITE(aud_config
, tmp
);
6148 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
6150 eldv
= AUDIO_ELD_VALID_A
<< (pipe
* 4);
6151 intel_crtc
->eld_vld
= true;
6153 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
6154 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6155 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6156 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
6158 I915_WRITE(aud_config
, 0);
6160 if (intel_eld_uptodate(connector
,
6161 aud_cntrl_st2
, eldv
,
6162 aud_cntl_st
, IBX_ELD_ADDRESS
,
6166 i
= I915_READ(aud_cntrl_st2
);
6168 I915_WRITE(aud_cntrl_st2
, i
);
6173 i
= I915_READ(aud_cntl_st
);
6174 i
&= ~IBX_ELD_ADDRESS
;
6175 I915_WRITE(aud_cntl_st
, i
);
6176 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
6177 DRM_DEBUG_DRIVER("port num:%d\n", i
);
6179 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
6180 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6181 for (i
= 0; i
< len
; i
++)
6182 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
6184 i
= I915_READ(aud_cntrl_st2
);
6186 I915_WRITE(aud_cntrl_st2
, i
);
6190 static void ironlake_write_eld(struct drm_connector
*connector
,
6191 struct drm_crtc
*crtc
)
6193 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6194 uint8_t *eld
= connector
->eld
;
6202 int pipe
= to_intel_crtc(crtc
)->pipe
;
6204 if (HAS_PCH_IBX(connector
->dev
)) {
6205 hdmiw_hdmiedid
= IBX_HDMIW_HDMIEDID(pipe
);
6206 aud_config
= IBX_AUD_CFG(pipe
);
6207 aud_cntl_st
= IBX_AUD_CNTL_ST(pipe
);
6208 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
6210 hdmiw_hdmiedid
= CPT_HDMIW_HDMIEDID(pipe
);
6211 aud_config
= CPT_AUD_CFG(pipe
);
6212 aud_cntl_st
= CPT_AUD_CNTL_ST(pipe
);
6213 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
6216 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
6218 i
= I915_READ(aud_cntl_st
);
6219 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
6221 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6222 /* operate blindly on all ports */
6223 eldv
= IBX_ELD_VALIDB
;
6224 eldv
|= IBX_ELD_VALIDB
<< 4;
6225 eldv
|= IBX_ELD_VALIDB
<< 8;
6227 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i
));
6228 eldv
= IBX_ELD_VALIDB
<< ((i
- 1) * 4);
6231 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
6232 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6233 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6234 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
6236 I915_WRITE(aud_config
, 0);
6238 if (intel_eld_uptodate(connector
,
6239 aud_cntrl_st2
, eldv
,
6240 aud_cntl_st
, IBX_ELD_ADDRESS
,
6244 i
= I915_READ(aud_cntrl_st2
);
6246 I915_WRITE(aud_cntrl_st2
, i
);
6251 i
= I915_READ(aud_cntl_st
);
6252 i
&= ~IBX_ELD_ADDRESS
;
6253 I915_WRITE(aud_cntl_st
, i
);
6255 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
6256 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6257 for (i
= 0; i
< len
; i
++)
6258 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
6260 i
= I915_READ(aud_cntrl_st2
);
6262 I915_WRITE(aud_cntrl_st2
, i
);
6265 void intel_write_eld(struct drm_encoder
*encoder
,
6266 struct drm_display_mode
*mode
)
6268 struct drm_crtc
*crtc
= encoder
->crtc
;
6269 struct drm_connector
*connector
;
6270 struct drm_device
*dev
= encoder
->dev
;
6271 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6273 connector
= drm_select_eld(encoder
, mode
);
6277 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6279 drm_get_connector_name(connector
),
6280 connector
->encoder
->base
.id
,
6281 drm_get_encoder_name(connector
->encoder
));
6283 connector
->eld
[6] = drm_av_sync_delay(connector
, mode
) / 2;
6285 if (dev_priv
->display
.write_eld
)
6286 dev_priv
->display
.write_eld(connector
, crtc
);
6289 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6290 void intel_crtc_load_lut(struct drm_crtc
*crtc
)
6292 struct drm_device
*dev
= crtc
->dev
;
6293 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6294 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6295 int palreg
= PALETTE(intel_crtc
->pipe
);
6298 /* The clocks have to be on to load the palette. */
6299 if (!crtc
->enabled
|| !intel_crtc
->active
)
6302 /* use legacy palette for Ironlake */
6303 if (HAS_PCH_SPLIT(dev
))
6304 palreg
= LGC_PALETTE(intel_crtc
->pipe
);
6306 for (i
= 0; i
< 256; i
++) {
6307 I915_WRITE(palreg
+ 4 * i
,
6308 (intel_crtc
->lut_r
[i
] << 16) |
6309 (intel_crtc
->lut_g
[i
] << 8) |
6310 intel_crtc
->lut_b
[i
]);
6314 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6316 struct drm_device
*dev
= crtc
->dev
;
6317 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6318 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6319 bool visible
= base
!= 0;
6322 if (intel_crtc
->cursor_visible
== visible
)
6325 cntl
= I915_READ(_CURACNTR
);
6327 /* On these chipsets we can only modify the base whilst
6328 * the cursor is disabled.
6330 I915_WRITE(_CURABASE
, base
);
6332 cntl
&= ~(CURSOR_FORMAT_MASK
);
6333 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6334 cntl
|= CURSOR_ENABLE
|
6335 CURSOR_GAMMA_ENABLE
|
6338 cntl
&= ~(CURSOR_ENABLE
| CURSOR_GAMMA_ENABLE
);
6339 I915_WRITE(_CURACNTR
, cntl
);
6341 intel_crtc
->cursor_visible
= visible
;
6344 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6346 struct drm_device
*dev
= crtc
->dev
;
6347 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6348 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6349 int pipe
= intel_crtc
->pipe
;
6350 bool visible
= base
!= 0;
6352 if (intel_crtc
->cursor_visible
!= visible
) {
6353 uint32_t cntl
= I915_READ(CURCNTR(pipe
));
6355 cntl
&= ~(CURSOR_MODE
| MCURSOR_PIPE_SELECT
);
6356 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
6357 cntl
|= pipe
<< 28; /* Connect to correct pipe */
6359 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
6360 cntl
|= CURSOR_MODE_DISABLE
;
6362 I915_WRITE(CURCNTR(pipe
), cntl
);
6364 intel_crtc
->cursor_visible
= visible
;
6366 /* and commit changes on next vblank */
6367 I915_WRITE(CURBASE(pipe
), base
);
6370 static void ivb_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6372 struct drm_device
*dev
= crtc
->dev
;
6373 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6374 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6375 int pipe
= intel_crtc
->pipe
;
6376 bool visible
= base
!= 0;
6378 if (intel_crtc
->cursor_visible
!= visible
) {
6379 uint32_t cntl
= I915_READ(CURCNTR_IVB(pipe
));
6381 cntl
&= ~CURSOR_MODE
;
6382 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
6384 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
6385 cntl
|= CURSOR_MODE_DISABLE
;
6387 if (IS_HASWELL(dev
))
6388 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
6389 I915_WRITE(CURCNTR_IVB(pipe
), cntl
);
6391 intel_crtc
->cursor_visible
= visible
;
6393 /* and commit changes on next vblank */
6394 I915_WRITE(CURBASE_IVB(pipe
), base
);
6397 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6398 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
6401 struct drm_device
*dev
= crtc
->dev
;
6402 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6403 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6404 int pipe
= intel_crtc
->pipe
;
6405 int x
= intel_crtc
->cursor_x
;
6406 int y
= intel_crtc
->cursor_y
;
6412 if (on
&& crtc
->enabled
&& crtc
->fb
) {
6413 base
= intel_crtc
->cursor_addr
;
6414 if (x
> (int) crtc
->fb
->width
)
6417 if (y
> (int) crtc
->fb
->height
)
6423 if (x
+ intel_crtc
->cursor_width
< 0)
6426 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
6429 pos
|= x
<< CURSOR_X_SHIFT
;
6432 if (y
+ intel_crtc
->cursor_height
< 0)
6435 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
6438 pos
|= y
<< CURSOR_Y_SHIFT
;
6440 visible
= base
!= 0;
6441 if (!visible
&& !intel_crtc
->cursor_visible
)
6444 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
6445 I915_WRITE(CURPOS_IVB(pipe
), pos
);
6446 ivb_update_cursor(crtc
, base
);
6448 I915_WRITE(CURPOS(pipe
), pos
);
6449 if (IS_845G(dev
) || IS_I865G(dev
))
6450 i845_update_cursor(crtc
, base
);
6452 i9xx_update_cursor(crtc
, base
);
6456 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
6457 struct drm_file
*file
,
6459 uint32_t width
, uint32_t height
)
6461 struct drm_device
*dev
= crtc
->dev
;
6462 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6463 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6464 struct drm_i915_gem_object
*obj
;
6468 /* if we want to turn off the cursor ignore width and height */
6470 DRM_DEBUG_KMS("cursor off\n");
6473 mutex_lock(&dev
->struct_mutex
);
6477 /* Currently we only support 64x64 cursors */
6478 if (width
!= 64 || height
!= 64) {
6479 DRM_ERROR("we currently only support 64x64 cursors\n");
6483 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
6484 if (&obj
->base
== NULL
)
6487 if (obj
->base
.size
< width
* height
* 4) {
6488 DRM_ERROR("buffer is to small\n");
6493 /* we only need to pin inside GTT if cursor is non-phy */
6494 mutex_lock(&dev
->struct_mutex
);
6495 if (!dev_priv
->info
->cursor_needs_physical
) {
6498 if (obj
->tiling_mode
) {
6499 DRM_ERROR("cursor cannot be tiled\n");
6504 /* Note that the w/a also requires 2 PTE of padding following
6505 * the bo. We currently fill all unused PTE with the shadow
6506 * page and so we should always have valid PTE following the
6507 * cursor preventing the VT-d warning.
6510 if (need_vtd_wa(dev
))
6511 alignment
= 64*1024;
6513 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, NULL
);
6515 DRM_ERROR("failed to move cursor bo into the GTT\n");
6519 ret
= i915_gem_object_put_fence(obj
);
6521 DRM_ERROR("failed to release fence for cursor");
6525 addr
= obj
->gtt_offset
;
6527 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
6528 ret
= i915_gem_attach_phys_object(dev
, obj
,
6529 (intel_crtc
->pipe
== 0) ? I915_GEM_PHYS_CURSOR_0
: I915_GEM_PHYS_CURSOR_1
,
6532 DRM_ERROR("failed to attach phys object\n");
6535 addr
= obj
->phys_obj
->handle
->busaddr
;
6539 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
6542 if (intel_crtc
->cursor_bo
) {
6543 if (dev_priv
->info
->cursor_needs_physical
) {
6544 if (intel_crtc
->cursor_bo
!= obj
)
6545 i915_gem_detach_phys_object(dev
, intel_crtc
->cursor_bo
);
6547 i915_gem_object_unpin(intel_crtc
->cursor_bo
);
6548 drm_gem_object_unreference(&intel_crtc
->cursor_bo
->base
);
6551 mutex_unlock(&dev
->struct_mutex
);
6553 intel_crtc
->cursor_addr
= addr
;
6554 intel_crtc
->cursor_bo
= obj
;
6555 intel_crtc
->cursor_width
= width
;
6556 intel_crtc
->cursor_height
= height
;
6558 intel_crtc_update_cursor(crtc
, true);
6562 i915_gem_object_unpin(obj
);
6564 mutex_unlock(&dev
->struct_mutex
);
6566 drm_gem_object_unreference_unlocked(&obj
->base
);
6570 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
6572 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6574 intel_crtc
->cursor_x
= x
;
6575 intel_crtc
->cursor_y
= y
;
6577 intel_crtc_update_cursor(crtc
, true);
6582 /** Sets the color ramps on behalf of RandR */
6583 void intel_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
6584 u16 blue
, int regno
)
6586 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6588 intel_crtc
->lut_r
[regno
] = red
>> 8;
6589 intel_crtc
->lut_g
[regno
] = green
>> 8;
6590 intel_crtc
->lut_b
[regno
] = blue
>> 8;
6593 void intel_crtc_fb_gamma_get(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
6594 u16
*blue
, int regno
)
6596 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6598 *red
= intel_crtc
->lut_r
[regno
] << 8;
6599 *green
= intel_crtc
->lut_g
[regno
] << 8;
6600 *blue
= intel_crtc
->lut_b
[regno
] << 8;
6603 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
6604 u16
*blue
, uint32_t start
, uint32_t size
)
6606 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
6607 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6609 for (i
= start
; i
< end
; i
++) {
6610 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
6611 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
6612 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
6615 intel_crtc_load_lut(crtc
);
6618 /* VESA 640x480x72Hz mode to set on the pipe */
6619 static struct drm_display_mode load_detect_mode
= {
6620 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
6621 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
6624 static struct drm_framebuffer
*
6625 intel_framebuffer_create(struct drm_device
*dev
,
6626 struct drm_mode_fb_cmd2
*mode_cmd
,
6627 struct drm_i915_gem_object
*obj
)
6629 struct intel_framebuffer
*intel_fb
;
6632 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
6634 drm_gem_object_unreference_unlocked(&obj
->base
);
6635 return ERR_PTR(-ENOMEM
);
6638 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
6640 drm_gem_object_unreference_unlocked(&obj
->base
);
6642 return ERR_PTR(ret
);
6645 return &intel_fb
->base
;
6649 intel_framebuffer_pitch_for_width(int width
, int bpp
)
6651 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
6652 return ALIGN(pitch
, 64);
6656 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
6658 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
6659 return ALIGN(pitch
* mode
->vdisplay
, PAGE_SIZE
);
6662 static struct drm_framebuffer
*
6663 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
6664 struct drm_display_mode
*mode
,
6667 struct drm_i915_gem_object
*obj
;
6668 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
6670 obj
= i915_gem_alloc_object(dev
,
6671 intel_framebuffer_size_for_mode(mode
, bpp
));
6673 return ERR_PTR(-ENOMEM
);
6675 mode_cmd
.width
= mode
->hdisplay
;
6676 mode_cmd
.height
= mode
->vdisplay
;
6677 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
6679 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
6681 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
6684 static struct drm_framebuffer
*
6685 mode_fits_in_fbdev(struct drm_device
*dev
,
6686 struct drm_display_mode
*mode
)
6688 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6689 struct drm_i915_gem_object
*obj
;
6690 struct drm_framebuffer
*fb
;
6692 if (dev_priv
->fbdev
== NULL
)
6695 obj
= dev_priv
->fbdev
->ifb
.obj
;
6699 fb
= &dev_priv
->fbdev
->ifb
.base
;
6700 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
6701 fb
->bits_per_pixel
))
6704 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
6710 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
6711 struct drm_display_mode
*mode
,
6712 struct intel_load_detect_pipe
*old
)
6714 struct intel_crtc
*intel_crtc
;
6715 struct intel_encoder
*intel_encoder
=
6716 intel_attached_encoder(connector
);
6717 struct drm_crtc
*possible_crtc
;
6718 struct drm_encoder
*encoder
= &intel_encoder
->base
;
6719 struct drm_crtc
*crtc
= NULL
;
6720 struct drm_device
*dev
= encoder
->dev
;
6721 struct drm_framebuffer
*fb
;
6724 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6725 connector
->base
.id
, drm_get_connector_name(connector
),
6726 encoder
->base
.id
, drm_get_encoder_name(encoder
));
6729 * Algorithm gets a little messy:
6731 * - if the connector already has an assigned crtc, use it (but make
6732 * sure it's on first)
6734 * - try to find the first unused crtc that can drive this connector,
6735 * and use that if we find one
6738 /* See if we already have a CRTC for this connector */
6739 if (encoder
->crtc
) {
6740 crtc
= encoder
->crtc
;
6742 mutex_lock(&crtc
->mutex
);
6744 old
->dpms_mode
= connector
->dpms
;
6745 old
->load_detect_temp
= false;
6747 /* Make sure the crtc and connector are running */
6748 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
6749 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
6754 /* Find an unused one (if possible) */
6755 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
6757 if (!(encoder
->possible_crtcs
& (1 << i
)))
6759 if (!possible_crtc
->enabled
) {
6760 crtc
= possible_crtc
;
6766 * If we didn't find an unused CRTC, don't use any.
6769 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6773 mutex_lock(&crtc
->mutex
);
6774 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
6775 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
6777 intel_crtc
= to_intel_crtc(crtc
);
6778 old
->dpms_mode
= connector
->dpms
;
6779 old
->load_detect_temp
= true;
6780 old
->release_fb
= NULL
;
6783 mode
= &load_detect_mode
;
6785 /* We need a framebuffer large enough to accommodate all accesses
6786 * that the plane may generate whilst we perform load detection.
6787 * We can not rely on the fbcon either being present (we get called
6788 * during its initialisation to detect all boot displays, or it may
6789 * not even exist) or that it is large enough to satisfy the
6792 fb
= mode_fits_in_fbdev(dev
, mode
);
6794 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6795 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
6796 old
->release_fb
= fb
;
6798 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6800 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6801 mutex_unlock(&crtc
->mutex
);
6805 if (intel_set_mode(crtc
, mode
, 0, 0, fb
)) {
6806 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6807 if (old
->release_fb
)
6808 old
->release_fb
->funcs
->destroy(old
->release_fb
);
6809 mutex_unlock(&crtc
->mutex
);
6813 /* let the connector get through one full cycle before testing */
6814 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
6818 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
6819 struct intel_load_detect_pipe
*old
)
6821 struct intel_encoder
*intel_encoder
=
6822 intel_attached_encoder(connector
);
6823 struct drm_encoder
*encoder
= &intel_encoder
->base
;
6824 struct drm_crtc
*crtc
= encoder
->crtc
;
6826 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6827 connector
->base
.id
, drm_get_connector_name(connector
),
6828 encoder
->base
.id
, drm_get_encoder_name(encoder
));
6830 if (old
->load_detect_temp
) {
6831 to_intel_connector(connector
)->new_encoder
= NULL
;
6832 intel_encoder
->new_crtc
= NULL
;
6833 intel_set_mode(crtc
, NULL
, 0, 0, NULL
);
6835 if (old
->release_fb
) {
6836 drm_framebuffer_unregister_private(old
->release_fb
);
6837 drm_framebuffer_unreference(old
->release_fb
);
6840 mutex_unlock(&crtc
->mutex
);
6844 /* Switch crtc and encoder back off if necessary */
6845 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
6846 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
6848 mutex_unlock(&crtc
->mutex
);
6851 /* Returns the clock of the currently programmed mode of the given pipe. */
6852 static int intel_crtc_clock_get(struct drm_device
*dev
, struct drm_crtc
*crtc
)
6854 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6855 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6856 int pipe
= intel_crtc
->pipe
;
6857 u32 dpll
= I915_READ(DPLL(pipe
));
6859 intel_clock_t clock
;
6861 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
6862 fp
= I915_READ(FP0(pipe
));
6864 fp
= I915_READ(FP1(pipe
));
6866 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
6867 if (IS_PINEVIEW(dev
)) {
6868 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
6869 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
6871 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
6872 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
6875 if (!IS_GEN2(dev
)) {
6876 if (IS_PINEVIEW(dev
))
6877 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
6878 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
6880 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
6881 DPLL_FPA01_P1_POST_DIV_SHIFT
);
6883 switch (dpll
& DPLL_MODE_MASK
) {
6884 case DPLLB_MODE_DAC_SERIAL
:
6885 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
6888 case DPLLB_MODE_LVDS
:
6889 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
6893 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6894 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
6898 /* XXX: Handle the 100Mhz refclk */
6899 intel_clock(dev
, 96000, &clock
);
6901 bool is_lvds
= (pipe
== 1) && (I915_READ(LVDS
) & LVDS_PORT_EN
);
6904 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
6905 DPLL_FPA01_P1_POST_DIV_SHIFT
);
6908 if ((dpll
& PLL_REF_INPUT_MASK
) ==
6909 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
6910 /* XXX: might not be 66MHz */
6911 intel_clock(dev
, 66000, &clock
);
6913 intel_clock(dev
, 48000, &clock
);
6915 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
6918 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
6919 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
6921 if (dpll
& PLL_P2_DIVIDE_BY_4
)
6926 intel_clock(dev
, 48000, &clock
);
6930 /* XXX: It would be nice to validate the clocks, but we can't reuse
6931 * i830PllIsValid() because it relies on the xf86_config connector
6932 * configuration being accurate, which it isn't necessarily.
6938 /** Returns the currently programmed mode of the given pipe. */
6939 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
6940 struct drm_crtc
*crtc
)
6942 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6943 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6944 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
6945 struct drm_display_mode
*mode
;
6946 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
6947 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
6948 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
6949 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
6951 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
6955 mode
->clock
= intel_crtc_clock_get(dev
, crtc
);
6956 mode
->hdisplay
= (htot
& 0xffff) + 1;
6957 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
6958 mode
->hsync_start
= (hsync
& 0xffff) + 1;
6959 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
6960 mode
->vdisplay
= (vtot
& 0xffff) + 1;
6961 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
6962 mode
->vsync_start
= (vsync
& 0xffff) + 1;
6963 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
6965 drm_mode_set_name(mode
);
6970 static void intel_increase_pllclock(struct drm_crtc
*crtc
)
6972 struct drm_device
*dev
= crtc
->dev
;
6973 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6974 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6975 int pipe
= intel_crtc
->pipe
;
6976 int dpll_reg
= DPLL(pipe
);
6979 if (HAS_PCH_SPLIT(dev
))
6982 if (!dev_priv
->lvds_downclock_avail
)
6985 dpll
= I915_READ(dpll_reg
);
6986 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
6987 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6989 assert_panel_unlocked(dev_priv
, pipe
);
6991 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
6992 I915_WRITE(dpll_reg
, dpll
);
6993 intel_wait_for_vblank(dev
, pipe
);
6995 dpll
= I915_READ(dpll_reg
);
6996 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
6997 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7001 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
7003 struct drm_device
*dev
= crtc
->dev
;
7004 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7005 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7007 if (HAS_PCH_SPLIT(dev
))
7010 if (!dev_priv
->lvds_downclock_avail
)
7014 * Since this is called by a timer, we should never get here in
7017 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
7018 int pipe
= intel_crtc
->pipe
;
7019 int dpll_reg
= DPLL(pipe
);
7022 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7024 assert_panel_unlocked(dev_priv
, pipe
);
7026 dpll
= I915_READ(dpll_reg
);
7027 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
7028 I915_WRITE(dpll_reg
, dpll
);
7029 intel_wait_for_vblank(dev
, pipe
);
7030 dpll
= I915_READ(dpll_reg
);
7031 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
7032 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7037 void intel_mark_busy(struct drm_device
*dev
)
7039 i915_update_gfx_val(dev
->dev_private
);
7042 void intel_mark_idle(struct drm_device
*dev
)
7044 struct drm_crtc
*crtc
;
7046 if (!i915_powersave
)
7049 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
7053 intel_decrease_pllclock(crtc
);
7057 void intel_mark_fb_busy(struct drm_i915_gem_object
*obj
)
7059 struct drm_device
*dev
= obj
->base
.dev
;
7060 struct drm_crtc
*crtc
;
7062 if (!i915_powersave
)
7065 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
7069 if (to_intel_framebuffer(crtc
->fb
)->obj
== obj
)
7070 intel_increase_pllclock(crtc
);
7074 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
7076 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7077 struct drm_device
*dev
= crtc
->dev
;
7078 struct intel_unpin_work
*work
;
7079 unsigned long flags
;
7081 spin_lock_irqsave(&dev
->event_lock
, flags
);
7082 work
= intel_crtc
->unpin_work
;
7083 intel_crtc
->unpin_work
= NULL
;
7084 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7087 cancel_work_sync(&work
->work
);
7091 drm_crtc_cleanup(crtc
);
7096 static void intel_unpin_work_fn(struct work_struct
*__work
)
7098 struct intel_unpin_work
*work
=
7099 container_of(__work
, struct intel_unpin_work
, work
);
7100 struct drm_device
*dev
= work
->crtc
->dev
;
7102 mutex_lock(&dev
->struct_mutex
);
7103 intel_unpin_fb_obj(work
->old_fb_obj
);
7104 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
7105 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
7107 intel_update_fbc(dev
);
7108 mutex_unlock(&dev
->struct_mutex
);
7110 BUG_ON(atomic_read(&to_intel_crtc(work
->crtc
)->unpin_work_count
) == 0);
7111 atomic_dec(&to_intel_crtc(work
->crtc
)->unpin_work_count
);
7116 static void do_intel_finish_page_flip(struct drm_device
*dev
,
7117 struct drm_crtc
*crtc
)
7119 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7120 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7121 struct intel_unpin_work
*work
;
7122 unsigned long flags
;
7124 /* Ignore early vblank irqs */
7125 if (intel_crtc
== NULL
)
7128 spin_lock_irqsave(&dev
->event_lock
, flags
);
7129 work
= intel_crtc
->unpin_work
;
7131 /* Ensure we don't miss a work->pending update ... */
7134 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
7135 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7139 /* and that the unpin work is consistent wrt ->pending. */
7142 intel_crtc
->unpin_work
= NULL
;
7145 drm_send_vblank_event(dev
, intel_crtc
->pipe
, work
->event
);
7147 drm_vblank_put(dev
, intel_crtc
->pipe
);
7149 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7151 wake_up_all(&dev_priv
->pending_flip_queue
);
7153 queue_work(dev_priv
->wq
, &work
->work
);
7155 trace_i915_flip_complete(intel_crtc
->plane
, work
->pending_flip_obj
);
7158 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
7160 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7161 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
7163 do_intel_finish_page_flip(dev
, crtc
);
7166 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
7168 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7169 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
7171 do_intel_finish_page_flip(dev
, crtc
);
7174 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
7176 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7177 struct intel_crtc
*intel_crtc
=
7178 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
7179 unsigned long flags
;
7181 /* NB: An MMIO update of the plane base pointer will also
7182 * generate a page-flip completion irq, i.e. every modeset
7183 * is also accompanied by a spurious intel_prepare_page_flip().
7185 spin_lock_irqsave(&dev
->event_lock
, flags
);
7186 if (intel_crtc
->unpin_work
)
7187 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
7188 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7191 inline static void intel_mark_page_flip_active(struct intel_crtc
*intel_crtc
)
7193 /* Ensure that the work item is consistent when activating it ... */
7195 atomic_set(&intel_crtc
->unpin_work
->pending
, INTEL_FLIP_PENDING
);
7196 /* and that it is marked active as soon as the irq could fire. */
7200 static int intel_gen2_queue_flip(struct drm_device
*dev
,
7201 struct drm_crtc
*crtc
,
7202 struct drm_framebuffer
*fb
,
7203 struct drm_i915_gem_object
*obj
)
7205 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7206 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7208 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7211 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7215 ret
= intel_ring_begin(ring
, 6);
7219 /* Can't queue multiple flips, so wait for the previous
7220 * one to finish before executing the next.
7222 if (intel_crtc
->plane
)
7223 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
7225 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
7226 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
7227 intel_ring_emit(ring
, MI_NOOP
);
7228 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7229 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7230 intel_ring_emit(ring
, fb
->pitches
[0]);
7231 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
7232 intel_ring_emit(ring
, 0); /* aux display base address, unused */
7234 intel_mark_page_flip_active(intel_crtc
);
7235 intel_ring_advance(ring
);
7239 intel_unpin_fb_obj(obj
);
7244 static int intel_gen3_queue_flip(struct drm_device
*dev
,
7245 struct drm_crtc
*crtc
,
7246 struct drm_framebuffer
*fb
,
7247 struct drm_i915_gem_object
*obj
)
7249 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7250 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7252 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7255 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7259 ret
= intel_ring_begin(ring
, 6);
7263 if (intel_crtc
->plane
)
7264 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
7266 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
7267 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
7268 intel_ring_emit(ring
, MI_NOOP
);
7269 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
7270 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7271 intel_ring_emit(ring
, fb
->pitches
[0]);
7272 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
7273 intel_ring_emit(ring
, MI_NOOP
);
7275 intel_mark_page_flip_active(intel_crtc
);
7276 intel_ring_advance(ring
);
7280 intel_unpin_fb_obj(obj
);
7285 static int intel_gen4_queue_flip(struct drm_device
*dev
,
7286 struct drm_crtc
*crtc
,
7287 struct drm_framebuffer
*fb
,
7288 struct drm_i915_gem_object
*obj
)
7290 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7291 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7292 uint32_t pf
, pipesrc
;
7293 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7296 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7300 ret
= intel_ring_begin(ring
, 4);
7304 /* i965+ uses the linear or tiled offsets from the
7305 * Display Registers (which do not change across a page-flip)
7306 * so we need only reprogram the base address.
7308 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7309 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7310 intel_ring_emit(ring
, fb
->pitches
[0]);
7311 intel_ring_emit(ring
,
7312 (obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
) |
7315 /* XXX Enabling the panel-fitter across page-flip is so far
7316 * untested on non-native modes, so ignore it for now.
7317 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7320 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
7321 intel_ring_emit(ring
, pf
| pipesrc
);
7323 intel_mark_page_flip_active(intel_crtc
);
7324 intel_ring_advance(ring
);
7328 intel_unpin_fb_obj(obj
);
7333 static int intel_gen6_queue_flip(struct drm_device
*dev
,
7334 struct drm_crtc
*crtc
,
7335 struct drm_framebuffer
*fb
,
7336 struct drm_i915_gem_object
*obj
)
7338 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7339 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7340 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7341 uint32_t pf
, pipesrc
;
7344 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7348 ret
= intel_ring_begin(ring
, 4);
7352 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7353 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7354 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
7355 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
7357 /* Contrary to the suggestions in the documentation,
7358 * "Enable Panel Fitter" does not seem to be required when page
7359 * flipping with a non-native mode, and worse causes a normal
7361 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7364 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
7365 intel_ring_emit(ring
, pf
| pipesrc
);
7367 intel_mark_page_flip_active(intel_crtc
);
7368 intel_ring_advance(ring
);
7372 intel_unpin_fb_obj(obj
);
7378 * On gen7 we currently use the blit ring because (in early silicon at least)
7379 * the render ring doesn't give us interrpts for page flip completion, which
7380 * means clients will hang after the first flip is queued. Fortunately the
7381 * blit ring generates interrupts properly, so use it instead.
7383 static int intel_gen7_queue_flip(struct drm_device
*dev
,
7384 struct drm_crtc
*crtc
,
7385 struct drm_framebuffer
*fb
,
7386 struct drm_i915_gem_object
*obj
)
7388 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7389 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7390 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[BCS
];
7391 uint32_t plane_bit
= 0;
7394 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7398 switch(intel_crtc
->plane
) {
7400 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
7403 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
7406 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
7409 WARN_ONCE(1, "unknown plane in flip command\n");
7414 ret
= intel_ring_begin(ring
, 4);
7418 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
7419 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
7420 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
7421 intel_ring_emit(ring
, (MI_NOOP
));
7423 intel_mark_page_flip_active(intel_crtc
);
7424 intel_ring_advance(ring
);
7428 intel_unpin_fb_obj(obj
);
7433 static int intel_default_queue_flip(struct drm_device
*dev
,
7434 struct drm_crtc
*crtc
,
7435 struct drm_framebuffer
*fb
,
7436 struct drm_i915_gem_object
*obj
)
7441 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
7442 struct drm_framebuffer
*fb
,
7443 struct drm_pending_vblank_event
*event
)
7445 struct drm_device
*dev
= crtc
->dev
;
7446 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7447 struct drm_framebuffer
*old_fb
= crtc
->fb
;
7448 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(fb
)->obj
;
7449 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7450 struct intel_unpin_work
*work
;
7451 unsigned long flags
;
7454 /* Can't change pixel format via MI display flips. */
7455 if (fb
->pixel_format
!= crtc
->fb
->pixel_format
)
7459 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7460 * Note that pitch changes could also affect these register.
7462 if (INTEL_INFO(dev
)->gen
> 3 &&
7463 (fb
->offsets
[0] != crtc
->fb
->offsets
[0] ||
7464 fb
->pitches
[0] != crtc
->fb
->pitches
[0]))
7467 work
= kzalloc(sizeof *work
, GFP_KERNEL
);
7471 work
->event
= event
;
7473 work
->old_fb_obj
= to_intel_framebuffer(old_fb
)->obj
;
7474 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
7476 ret
= drm_vblank_get(dev
, intel_crtc
->pipe
);
7480 /* We borrow the event spin lock for protecting unpin_work */
7481 spin_lock_irqsave(&dev
->event_lock
, flags
);
7482 if (intel_crtc
->unpin_work
) {
7483 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7485 drm_vblank_put(dev
, intel_crtc
->pipe
);
7487 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7490 intel_crtc
->unpin_work
= work
;
7491 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7493 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
7494 flush_workqueue(dev_priv
->wq
);
7496 ret
= i915_mutex_lock_interruptible(dev
);
7500 /* Reference the objects for the scheduled work. */
7501 drm_gem_object_reference(&work
->old_fb_obj
->base
);
7502 drm_gem_object_reference(&obj
->base
);
7506 work
->pending_flip_obj
= obj
;
7508 work
->enable_stall_check
= true;
7510 atomic_inc(&intel_crtc
->unpin_work_count
);
7511 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
7513 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
);
7515 goto cleanup_pending
;
7517 intel_disable_fbc(dev
);
7518 intel_mark_fb_busy(obj
);
7519 mutex_unlock(&dev
->struct_mutex
);
7521 trace_i915_flip_request(intel_crtc
->plane
, obj
);
7526 atomic_dec(&intel_crtc
->unpin_work_count
);
7528 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
7529 drm_gem_object_unreference(&obj
->base
);
7530 mutex_unlock(&dev
->struct_mutex
);
7533 spin_lock_irqsave(&dev
->event_lock
, flags
);
7534 intel_crtc
->unpin_work
= NULL
;
7535 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7537 drm_vblank_put(dev
, intel_crtc
->pipe
);
7544 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
7545 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
7546 .load_lut
= intel_crtc_load_lut
,
7549 bool intel_encoder_check_is_cloned(struct intel_encoder
*encoder
)
7551 struct intel_encoder
*other_encoder
;
7552 struct drm_crtc
*crtc
= &encoder
->new_crtc
->base
;
7557 list_for_each_entry(other_encoder
,
7558 &crtc
->dev
->mode_config
.encoder_list
,
7561 if (&other_encoder
->new_crtc
->base
!= crtc
||
7562 encoder
== other_encoder
)
7571 static bool intel_encoder_crtc_ok(struct drm_encoder
*encoder
,
7572 struct drm_crtc
*crtc
)
7574 struct drm_device
*dev
;
7575 struct drm_crtc
*tmp
;
7578 WARN(!crtc
, "checking null crtc?\n");
7582 list_for_each_entry(tmp
, &dev
->mode_config
.crtc_list
, head
) {
7588 if (encoder
->possible_crtcs
& crtc_mask
)
7594 * intel_modeset_update_staged_output_state
7596 * Updates the staged output configuration state, e.g. after we've read out the
7599 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
7601 struct intel_encoder
*encoder
;
7602 struct intel_connector
*connector
;
7604 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7606 connector
->new_encoder
=
7607 to_intel_encoder(connector
->base
.encoder
);
7610 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7613 to_intel_crtc(encoder
->base
.crtc
);
7618 * intel_modeset_commit_output_state
7620 * This function copies the stage display pipe configuration to the real one.
7622 static void intel_modeset_commit_output_state(struct drm_device
*dev
)
7624 struct intel_encoder
*encoder
;
7625 struct intel_connector
*connector
;
7627 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7629 connector
->base
.encoder
= &connector
->new_encoder
->base
;
7632 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7634 encoder
->base
.crtc
= &encoder
->new_crtc
->base
;
7639 pipe_config_set_bpp(struct drm_crtc
*crtc
,
7640 struct drm_framebuffer
*fb
,
7641 struct intel_crtc_config
*pipe_config
)
7643 struct drm_device
*dev
= crtc
->dev
;
7644 struct drm_connector
*connector
;
7647 switch (fb
->pixel_format
) {
7649 bpp
= 8*3; /* since we go through a colormap */
7651 case DRM_FORMAT_XRGB1555
:
7652 case DRM_FORMAT_ARGB1555
:
7653 /* checked in intel_framebuffer_init already */
7654 if (WARN_ON(INTEL_INFO(dev
)->gen
> 3))
7656 case DRM_FORMAT_RGB565
:
7657 bpp
= 6*3; /* min is 18bpp */
7659 case DRM_FORMAT_XBGR8888
:
7660 case DRM_FORMAT_ABGR8888
:
7661 /* checked in intel_framebuffer_init already */
7662 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
7664 case DRM_FORMAT_XRGB8888
:
7665 case DRM_FORMAT_ARGB8888
:
7668 case DRM_FORMAT_XRGB2101010
:
7669 case DRM_FORMAT_ARGB2101010
:
7670 case DRM_FORMAT_XBGR2101010
:
7671 case DRM_FORMAT_ABGR2101010
:
7672 /* checked in intel_framebuffer_init already */
7673 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
7677 /* TODO: gen4+ supports 16 bpc floating point, too. */
7679 DRM_DEBUG_KMS("unsupported depth\n");
7683 pipe_config
->pipe_bpp
= bpp
;
7685 /* Clamp display bpp to EDID value */
7686 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7688 if (connector
->encoder
&& connector
->encoder
->crtc
!= crtc
)
7691 /* Don't use an invalid EDID bpc value */
7692 if (connector
->display_info
.bpc
&&
7693 connector
->display_info
.bpc
* 3 < bpp
) {
7694 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7695 bpp
, connector
->display_info
.bpc
*3);
7696 pipe_config
->pipe_bpp
= connector
->display_info
.bpc
*3;
7699 /* Clamp bpp to 8 on screens without EDID 1.4 */
7700 if (connector
->display_info
.bpc
== 0 && bpp
> 24) {
7701 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7703 pipe_config
->pipe_bpp
= 24;
7710 static struct intel_crtc_config
*
7711 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
7712 struct drm_framebuffer
*fb
,
7713 struct drm_display_mode
*mode
)
7715 struct drm_device
*dev
= crtc
->dev
;
7716 struct drm_encoder_helper_funcs
*encoder_funcs
;
7717 struct intel_encoder
*encoder
;
7718 struct intel_crtc_config
*pipe_config
;
7721 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
7723 return ERR_PTR(-ENOMEM
);
7725 drm_mode_copy(&pipe_config
->adjusted_mode
, mode
);
7726 drm_mode_copy(&pipe_config
->requested_mode
, mode
);
7728 plane_bpp
= pipe_config_set_bpp(crtc
, fb
, pipe_config
);
7732 /* Pass our mode to the connectors and the CRTC to give them a chance to
7733 * adjust it according to limitations or connector properties, and also
7734 * a chance to reject the mode entirely.
7736 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7739 if (&encoder
->new_crtc
->base
!= crtc
)
7742 if (encoder
->compute_config
) {
7743 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
7744 DRM_DEBUG_KMS("Encoder config failure\n");
7751 encoder_funcs
= encoder
->base
.helper_private
;
7752 if (!(encoder_funcs
->mode_fixup(&encoder
->base
,
7753 &pipe_config
->requested_mode
,
7754 &pipe_config
->adjusted_mode
))) {
7755 DRM_DEBUG_KMS("Encoder fixup failed\n");
7760 if (!(intel_crtc_compute_config(crtc
, pipe_config
))) {
7761 DRM_DEBUG_KMS("CRTC fixup failed\n");
7764 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc
->base
.id
);
7766 pipe_config
->dither
= pipe_config
->pipe_bpp
!= plane_bpp
;
7767 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7768 plane_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
7773 return ERR_PTR(-EINVAL
);
7776 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7777 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7779 intel_modeset_affected_pipes(struct drm_crtc
*crtc
, unsigned *modeset_pipes
,
7780 unsigned *prepare_pipes
, unsigned *disable_pipes
)
7782 struct intel_crtc
*intel_crtc
;
7783 struct drm_device
*dev
= crtc
->dev
;
7784 struct intel_encoder
*encoder
;
7785 struct intel_connector
*connector
;
7786 struct drm_crtc
*tmp_crtc
;
7788 *disable_pipes
= *modeset_pipes
= *prepare_pipes
= 0;
7790 /* Check which crtcs have changed outputs connected to them, these need
7791 * to be part of the prepare_pipes mask. We don't (yet) support global
7792 * modeset across multiple crtcs, so modeset_pipes will only have one
7793 * bit set at most. */
7794 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7796 if (connector
->base
.encoder
== &connector
->new_encoder
->base
)
7799 if (connector
->base
.encoder
) {
7800 tmp_crtc
= connector
->base
.encoder
->crtc
;
7802 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
7805 if (connector
->new_encoder
)
7807 1 << connector
->new_encoder
->new_crtc
->pipe
;
7810 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7812 if (encoder
->base
.crtc
== &encoder
->new_crtc
->base
)
7815 if (encoder
->base
.crtc
) {
7816 tmp_crtc
= encoder
->base
.crtc
;
7818 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
7821 if (encoder
->new_crtc
)
7822 *prepare_pipes
|= 1 << encoder
->new_crtc
->pipe
;
7825 /* Check for any pipes that will be fully disabled ... */
7826 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
7830 /* Don't try to disable disabled crtcs. */
7831 if (!intel_crtc
->base
.enabled
)
7834 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7836 if (encoder
->new_crtc
== intel_crtc
)
7841 *disable_pipes
|= 1 << intel_crtc
->pipe
;
7845 /* set_mode is also used to update properties on life display pipes. */
7846 intel_crtc
= to_intel_crtc(crtc
);
7848 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
7851 * For simplicity do a full modeset on any pipe where the output routing
7852 * changed. We could be more clever, but that would require us to be
7853 * more careful with calling the relevant encoder->mode_set functions.
7856 *modeset_pipes
= *prepare_pipes
;
7858 /* ... and mask these out. */
7859 *modeset_pipes
&= ~(*disable_pipes
);
7860 *prepare_pipes
&= ~(*disable_pipes
);
7863 * HACK: We don't (yet) fully support global modesets. intel_set_config
7864 * obies this rule, but the modeset restore mode of
7865 * intel_modeset_setup_hw_state does not.
7867 *modeset_pipes
&= 1 << intel_crtc
->pipe
;
7868 *prepare_pipes
&= 1 << intel_crtc
->pipe
;
7870 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7871 *modeset_pipes
, *prepare_pipes
, *disable_pipes
);
7874 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
7876 struct drm_encoder
*encoder
;
7877 struct drm_device
*dev
= crtc
->dev
;
7879 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
7880 if (encoder
->crtc
== crtc
)
7887 intel_modeset_update_state(struct drm_device
*dev
, unsigned prepare_pipes
)
7889 struct intel_encoder
*intel_encoder
;
7890 struct intel_crtc
*intel_crtc
;
7891 struct drm_connector
*connector
;
7893 list_for_each_entry(intel_encoder
, &dev
->mode_config
.encoder_list
,
7895 if (!intel_encoder
->base
.crtc
)
7898 intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
7900 if (prepare_pipes
& (1 << intel_crtc
->pipe
))
7901 intel_encoder
->connectors_active
= false;
7904 intel_modeset_commit_output_state(dev
);
7906 /* Update computed state. */
7907 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
7909 intel_crtc
->base
.enabled
= intel_crtc_in_use(&intel_crtc
->base
);
7912 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
7913 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
7916 intel_crtc
= to_intel_crtc(connector
->encoder
->crtc
);
7918 if (prepare_pipes
& (1 << intel_crtc
->pipe
)) {
7919 struct drm_property
*dpms_property
=
7920 dev
->mode_config
.dpms_property
;
7922 connector
->dpms
= DRM_MODE_DPMS_ON
;
7923 drm_object_property_set_value(&connector
->base
,
7927 intel_encoder
= to_intel_encoder(connector
->encoder
);
7928 intel_encoder
->connectors_active
= true;
7934 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7935 list_for_each_entry((intel_crtc), \
7936 &(dev)->mode_config.crtc_list, \
7938 if (mask & (1 <<(intel_crtc)->pipe)) \
7941 intel_pipe_config_compare(struct intel_crtc_config
*current_config
,
7942 struct intel_crtc_config
*pipe_config
)
7944 if (current_config
->has_pch_encoder
!= pipe_config
->has_pch_encoder
) {
7945 DRM_ERROR("mismatch in has_pch_encoder "
7946 "(expected %i, found %i)\n",
7947 current_config
->has_pch_encoder
,
7948 pipe_config
->has_pch_encoder
);
7956 intel_modeset_check_state(struct drm_device
*dev
)
7958 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7959 struct intel_crtc
*crtc
;
7960 struct intel_encoder
*encoder
;
7961 struct intel_connector
*connector
;
7962 struct intel_crtc_config pipe_config
;
7964 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7966 /* This also checks the encoder/connector hw state with the
7967 * ->get_hw_state callbacks. */
7968 intel_connector_check_state(connector
);
7970 WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
7971 "connector's staged encoder doesn't match current encoder\n");
7974 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7976 bool enabled
= false;
7977 bool active
= false;
7978 enum pipe pipe
, tracked_pipe
;
7980 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7981 encoder
->base
.base
.id
,
7982 drm_get_encoder_name(&encoder
->base
));
7984 WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
7985 "encoder's stage crtc doesn't match current crtc\n");
7986 WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
7987 "encoder's active_connectors set, but no crtc\n");
7989 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7991 if (connector
->base
.encoder
!= &encoder
->base
)
7994 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
7997 WARN(!!encoder
->base
.crtc
!= enabled
,
7998 "encoder's enabled state mismatch "
7999 "(expected %i, found %i)\n",
8000 !!encoder
->base
.crtc
, enabled
);
8001 WARN(active
&& !encoder
->base
.crtc
,
8002 "active encoder with no crtc\n");
8004 WARN(encoder
->connectors_active
!= active
,
8005 "encoder's computed active state doesn't match tracked active state "
8006 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
8008 active
= encoder
->get_hw_state(encoder
, &pipe
);
8009 WARN(active
!= encoder
->connectors_active
,
8010 "encoder's hw state doesn't match sw tracking "
8011 "(expected %i, found %i)\n",
8012 encoder
->connectors_active
, active
);
8014 if (!encoder
->base
.crtc
)
8017 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
8018 WARN(active
&& pipe
!= tracked_pipe
,
8019 "active encoder's pipe doesn't match"
8020 "(expected %i, found %i)\n",
8021 tracked_pipe
, pipe
);
8025 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
8027 bool enabled
= false;
8028 bool active
= false;
8030 DRM_DEBUG_KMS("[CRTC:%d]\n",
8031 crtc
->base
.base
.id
);
8033 WARN(crtc
->active
&& !crtc
->base
.enabled
,
8034 "active crtc, but not enabled in sw tracking\n");
8036 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8038 if (encoder
->base
.crtc
!= &crtc
->base
)
8041 if (encoder
->connectors_active
)
8044 WARN(active
!= crtc
->active
,
8045 "crtc's computed active state doesn't match tracked active state "
8046 "(expected %i, found %i)\n", active
, crtc
->active
);
8047 WARN(enabled
!= crtc
->base
.enabled
,
8048 "crtc's computed enabled state doesn't match tracked enabled state "
8049 "(expected %i, found %i)\n", enabled
, crtc
->base
.enabled
);
8051 memset(&pipe_config
, 0, sizeof(pipe_config
));
8052 active
= dev_priv
->display
.get_pipe_config(crtc
,
8054 WARN(crtc
->active
!= active
,
8055 "crtc active state doesn't match with hw state "
8056 "(expected %i, found %i)\n", crtc
->active
, active
);
8059 !intel_pipe_config_compare(&crtc
->config
, &pipe_config
),
8060 "pipe state doesn't match!\n");
8064 static int __intel_set_mode(struct drm_crtc
*crtc
,
8065 struct drm_display_mode
*mode
,
8066 int x
, int y
, struct drm_framebuffer
*fb
)
8068 struct drm_device
*dev
= crtc
->dev
;
8069 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8070 struct drm_display_mode
*saved_mode
, *saved_hwmode
;
8071 struct intel_crtc_config
*pipe_config
= NULL
;
8072 struct intel_crtc
*intel_crtc
;
8073 unsigned disable_pipes
, prepare_pipes
, modeset_pipes
;
8076 saved_mode
= kmalloc(2 * sizeof(*saved_mode
), GFP_KERNEL
);
8079 saved_hwmode
= saved_mode
+ 1;
8081 intel_modeset_affected_pipes(crtc
, &modeset_pipes
,
8082 &prepare_pipes
, &disable_pipes
);
8084 *saved_hwmode
= crtc
->hwmode
;
8085 *saved_mode
= crtc
->mode
;
8087 /* Hack: Because we don't (yet) support global modeset on multiple
8088 * crtcs, we don't keep track of the new mode for more than one crtc.
8089 * Hence simply check whether any bit is set in modeset_pipes in all the
8090 * pieces of code that are not yet converted to deal with mutliple crtcs
8091 * changing their mode at the same time. */
8092 if (modeset_pipes
) {
8093 pipe_config
= intel_modeset_pipe_config(crtc
, fb
, mode
);
8094 if (IS_ERR(pipe_config
)) {
8095 ret
= PTR_ERR(pipe_config
);
8102 for_each_intel_crtc_masked(dev
, disable_pipes
, intel_crtc
)
8103 intel_crtc_disable(&intel_crtc
->base
);
8105 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
8106 if (intel_crtc
->base
.enabled
)
8107 dev_priv
->display
.crtc_disable(&intel_crtc
->base
);
8110 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8111 * to set it here already despite that we pass it down the callchain.
8113 if (modeset_pipes
) {
8114 enum transcoder tmp
= to_intel_crtc(crtc
)->config
.cpu_transcoder
;
8116 /* mode_set/enable/disable functions rely on a correct pipe
8118 to_intel_crtc(crtc
)->config
= *pipe_config
;
8119 to_intel_crtc(crtc
)->config
.cpu_transcoder
= tmp
;
8122 /* Only after disabling all output pipelines that will be changed can we
8123 * update the the output configuration. */
8124 intel_modeset_update_state(dev
, prepare_pipes
);
8126 if (dev_priv
->display
.modeset_global_resources
)
8127 dev_priv
->display
.modeset_global_resources(dev
);
8129 /* Set up the DPLL and any encoders state that needs to adjust or depend
8132 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
8133 ret
= intel_crtc_mode_set(&intel_crtc
->base
,
8139 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8140 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
)
8141 dev_priv
->display
.crtc_enable(&intel_crtc
->base
);
8143 if (modeset_pipes
) {
8144 /* Store real post-adjustment hardware mode. */
8145 crtc
->hwmode
= pipe_config
->adjusted_mode
;
8147 /* Calculate and store various constants which
8148 * are later needed by vblank and swap-completion
8149 * timestamping. They are derived from true hwmode.
8151 drm_calc_timestamping_constants(crtc
);
8154 /* FIXME: add subpixel order */
8156 if (ret
&& crtc
->enabled
) {
8157 crtc
->hwmode
= *saved_hwmode
;
8158 crtc
->mode
= *saved_mode
;
8167 int intel_set_mode(struct drm_crtc
*crtc
,
8168 struct drm_display_mode
*mode
,
8169 int x
, int y
, struct drm_framebuffer
*fb
)
8173 ret
= __intel_set_mode(crtc
, mode
, x
, y
, fb
);
8176 intel_modeset_check_state(crtc
->dev
);
8181 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
8183 intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
, crtc
->fb
);
8186 #undef for_each_intel_crtc_masked
8188 static void intel_set_config_free(struct intel_set_config
*config
)
8193 kfree(config
->save_connector_encoders
);
8194 kfree(config
->save_encoder_crtcs
);
8198 static int intel_set_config_save_state(struct drm_device
*dev
,
8199 struct intel_set_config
*config
)
8201 struct drm_encoder
*encoder
;
8202 struct drm_connector
*connector
;
8205 config
->save_encoder_crtcs
=
8206 kcalloc(dev
->mode_config
.num_encoder
,
8207 sizeof(struct drm_crtc
*), GFP_KERNEL
);
8208 if (!config
->save_encoder_crtcs
)
8211 config
->save_connector_encoders
=
8212 kcalloc(dev
->mode_config
.num_connector
,
8213 sizeof(struct drm_encoder
*), GFP_KERNEL
);
8214 if (!config
->save_connector_encoders
)
8217 /* Copy data. Note that driver private data is not affected.
8218 * Should anything bad happen only the expected state is
8219 * restored, not the drivers personal bookkeeping.
8222 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
8223 config
->save_encoder_crtcs
[count
++] = encoder
->crtc
;
8227 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
8228 config
->save_connector_encoders
[count
++] = connector
->encoder
;
8234 static void intel_set_config_restore_state(struct drm_device
*dev
,
8235 struct intel_set_config
*config
)
8237 struct intel_encoder
*encoder
;
8238 struct intel_connector
*connector
;
8242 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
8244 to_intel_crtc(config
->save_encoder_crtcs
[count
++]);
8248 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
8249 connector
->new_encoder
=
8250 to_intel_encoder(config
->save_connector_encoders
[count
++]);
8255 intel_set_config_compute_mode_changes(struct drm_mode_set
*set
,
8256 struct intel_set_config
*config
)
8259 /* We should be able to check here if the fb has the same properties
8260 * and then just flip_or_move it */
8261 if (set
->crtc
->fb
!= set
->fb
) {
8262 /* If we have no fb then treat it as a full mode set */
8263 if (set
->crtc
->fb
== NULL
) {
8264 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8265 config
->mode_changed
= true;
8266 } else if (set
->fb
== NULL
) {
8267 config
->mode_changed
= true;
8268 } else if (set
->fb
->pixel_format
!=
8269 set
->crtc
->fb
->pixel_format
) {
8270 config
->mode_changed
= true;
8272 config
->fb_changed
= true;
8275 if (set
->fb
&& (set
->x
!= set
->crtc
->x
|| set
->y
!= set
->crtc
->y
))
8276 config
->fb_changed
= true;
8278 if (set
->mode
&& !drm_mode_equal(set
->mode
, &set
->crtc
->mode
)) {
8279 DRM_DEBUG_KMS("modes are different, full mode set\n");
8280 drm_mode_debug_printmodeline(&set
->crtc
->mode
);
8281 drm_mode_debug_printmodeline(set
->mode
);
8282 config
->mode_changed
= true;
8287 intel_modeset_stage_output_state(struct drm_device
*dev
,
8288 struct drm_mode_set
*set
,
8289 struct intel_set_config
*config
)
8291 struct drm_crtc
*new_crtc
;
8292 struct intel_connector
*connector
;
8293 struct intel_encoder
*encoder
;
8296 /* The upper layers ensure that we either disable a crtc or have a list
8297 * of connectors. For paranoia, double-check this. */
8298 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
8299 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
8302 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8304 /* Otherwise traverse passed in connector list and get encoders
8306 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
8307 if (set
->connectors
[ro
] == &connector
->base
) {
8308 connector
->new_encoder
= connector
->encoder
;
8313 /* If we disable the crtc, disable all its connectors. Also, if
8314 * the connector is on the changing crtc but not on the new
8315 * connector list, disable it. */
8316 if ((!set
->fb
|| ro
== set
->num_connectors
) &&
8317 connector
->base
.encoder
&&
8318 connector
->base
.encoder
->crtc
== set
->crtc
) {
8319 connector
->new_encoder
= NULL
;
8321 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8322 connector
->base
.base
.id
,
8323 drm_get_connector_name(&connector
->base
));
8327 if (&connector
->new_encoder
->base
!= connector
->base
.encoder
) {
8328 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8329 config
->mode_changed
= true;
8332 /* connector->new_encoder is now updated for all connectors. */
8334 /* Update crtc of enabled connectors. */
8336 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8338 if (!connector
->new_encoder
)
8341 new_crtc
= connector
->new_encoder
->base
.crtc
;
8343 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
8344 if (set
->connectors
[ro
] == &connector
->base
)
8345 new_crtc
= set
->crtc
;
8348 /* Make sure the new CRTC will work with the encoder */
8349 if (!intel_encoder_crtc_ok(&connector
->new_encoder
->base
,
8353 connector
->encoder
->new_crtc
= to_intel_crtc(new_crtc
);
8355 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8356 connector
->base
.base
.id
,
8357 drm_get_connector_name(&connector
->base
),
8361 /* Check for any encoders that needs to be disabled. */
8362 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8364 list_for_each_entry(connector
,
8365 &dev
->mode_config
.connector_list
,
8367 if (connector
->new_encoder
== encoder
) {
8368 WARN_ON(!connector
->new_encoder
->new_crtc
);
8373 encoder
->new_crtc
= NULL
;
8375 /* Only now check for crtc changes so we don't miss encoders
8376 * that will be disabled. */
8377 if (&encoder
->new_crtc
->base
!= encoder
->base
.crtc
) {
8378 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8379 config
->mode_changed
= true;
8382 /* Now we've also updated encoder->new_crtc for all encoders. */
8387 static int intel_crtc_set_config(struct drm_mode_set
*set
)
8389 struct drm_device
*dev
;
8390 struct drm_mode_set save_set
;
8391 struct intel_set_config
*config
;
8396 BUG_ON(!set
->crtc
->helper_private
);
8398 /* Enforce sane interface api - has been abused by the fb helper. */
8399 BUG_ON(!set
->mode
&& set
->fb
);
8400 BUG_ON(set
->fb
&& set
->num_connectors
== 0);
8403 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8404 set
->crtc
->base
.id
, set
->fb
->base
.id
,
8405 (int)set
->num_connectors
, set
->x
, set
->y
);
8407 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
8410 dev
= set
->crtc
->dev
;
8413 config
= kzalloc(sizeof(*config
), GFP_KERNEL
);
8417 ret
= intel_set_config_save_state(dev
, config
);
8421 save_set
.crtc
= set
->crtc
;
8422 save_set
.mode
= &set
->crtc
->mode
;
8423 save_set
.x
= set
->crtc
->x
;
8424 save_set
.y
= set
->crtc
->y
;
8425 save_set
.fb
= set
->crtc
->fb
;
8427 /* Compute whether we need a full modeset, only an fb base update or no
8428 * change at all. In the future we might also check whether only the
8429 * mode changed, e.g. for LVDS where we only change the panel fitter in
8431 intel_set_config_compute_mode_changes(set
, config
);
8433 ret
= intel_modeset_stage_output_state(dev
, set
, config
);
8437 if (config
->mode_changed
) {
8439 DRM_DEBUG_KMS("attempting to set mode from"
8441 drm_mode_debug_printmodeline(set
->mode
);
8444 ret
= intel_set_mode(set
->crtc
, set
->mode
,
8445 set
->x
, set
->y
, set
->fb
);
8447 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8448 set
->crtc
->base
.id
, ret
);
8451 } else if (config
->fb_changed
) {
8452 intel_crtc_wait_for_pending_flips(set
->crtc
);
8454 ret
= intel_pipe_set_base(set
->crtc
,
8455 set
->x
, set
->y
, set
->fb
);
8458 intel_set_config_free(config
);
8463 intel_set_config_restore_state(dev
, config
);
8465 /* Try to restore the config */
8466 if (config
->mode_changed
&&
8467 intel_set_mode(save_set
.crtc
, save_set
.mode
,
8468 save_set
.x
, save_set
.y
, save_set
.fb
))
8469 DRM_ERROR("failed to restore config after modeset failure\n");
8472 intel_set_config_free(config
);
8476 static const struct drm_crtc_funcs intel_crtc_funcs
= {
8477 .cursor_set
= intel_crtc_cursor_set
,
8478 .cursor_move
= intel_crtc_cursor_move
,
8479 .gamma_set
= intel_crtc_gamma_set
,
8480 .set_config
= intel_crtc_set_config
,
8481 .destroy
= intel_crtc_destroy
,
8482 .page_flip
= intel_crtc_page_flip
,
8485 static void intel_cpu_pll_init(struct drm_device
*dev
)
8488 intel_ddi_pll_init(dev
);
8491 static void intel_pch_pll_init(struct drm_device
*dev
)
8493 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8496 if (dev_priv
->num_pch_pll
== 0) {
8497 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8501 for (i
= 0; i
< dev_priv
->num_pch_pll
; i
++) {
8502 dev_priv
->pch_plls
[i
].pll_reg
= _PCH_DPLL(i
);
8503 dev_priv
->pch_plls
[i
].fp0_reg
= _PCH_FP0(i
);
8504 dev_priv
->pch_plls
[i
].fp1_reg
= _PCH_FP1(i
);
8508 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
8510 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8511 struct intel_crtc
*intel_crtc
;
8514 intel_crtc
= kzalloc(sizeof(struct intel_crtc
) + (INTELFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
8515 if (intel_crtc
== NULL
)
8518 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
8520 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
8521 for (i
= 0; i
< 256; i
++) {
8522 intel_crtc
->lut_r
[i
] = i
;
8523 intel_crtc
->lut_g
[i
] = i
;
8524 intel_crtc
->lut_b
[i
] = i
;
8527 /* Swap pipes & planes for FBC on pre-965 */
8528 intel_crtc
->pipe
= pipe
;
8529 intel_crtc
->plane
= pipe
;
8530 intel_crtc
->config
.cpu_transcoder
= pipe
;
8531 if (IS_MOBILE(dev
) && IS_GEN3(dev
)) {
8532 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8533 intel_crtc
->plane
= !pipe
;
8536 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
8537 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
8538 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
8539 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
8541 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
8544 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
8545 struct drm_file
*file
)
8547 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
8548 struct drm_mode_object
*drmmode_obj
;
8549 struct intel_crtc
*crtc
;
8551 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
8554 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
8555 DRM_MODE_OBJECT_CRTC
);
8558 DRM_ERROR("no such CRTC id\n");
8562 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
8563 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
8568 static int intel_encoder_clones(struct intel_encoder
*encoder
)
8570 struct drm_device
*dev
= encoder
->base
.dev
;
8571 struct intel_encoder
*source_encoder
;
8575 list_for_each_entry(source_encoder
,
8576 &dev
->mode_config
.encoder_list
, base
.head
) {
8578 if (encoder
== source_encoder
)
8579 index_mask
|= (1 << entry
);
8581 /* Intel hw has only one MUX where enocoders could be cloned. */
8582 if (encoder
->cloneable
&& source_encoder
->cloneable
)
8583 index_mask
|= (1 << entry
);
8591 static bool has_edp_a(struct drm_device
*dev
)
8593 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8595 if (!IS_MOBILE(dev
))
8598 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
8602 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES
) & ILK_eDP_A_DISABLE
))
8608 static void intel_setup_outputs(struct drm_device
*dev
)
8610 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8611 struct intel_encoder
*encoder
;
8612 bool dpd_is_edp
= false;
8615 has_lvds
= intel_lvds_init(dev
);
8616 if (!has_lvds
&& !HAS_PCH_SPLIT(dev
)) {
8617 /* disable the panel fitter on everything but LVDS */
8618 I915_WRITE(PFIT_CONTROL
, 0);
8622 intel_crt_init(dev
);
8627 /* Haswell uses DDI functions to detect digital outputs */
8628 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
8629 /* DDI A only supports eDP */
8631 intel_ddi_init(dev
, PORT_A
);
8633 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8635 found
= I915_READ(SFUSE_STRAP
);
8637 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
8638 intel_ddi_init(dev
, PORT_B
);
8639 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
8640 intel_ddi_init(dev
, PORT_C
);
8641 if (found
& SFUSE_STRAP_DDID_DETECTED
)
8642 intel_ddi_init(dev
, PORT_D
);
8643 } else if (HAS_PCH_SPLIT(dev
)) {
8645 dpd_is_edp
= intel_dpd_is_edp(dev
);
8648 intel_dp_init(dev
, DP_A
, PORT_A
);
8650 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
8651 /* PCH SDVOB multiplex with HDMIB */
8652 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
8654 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
8655 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
8656 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
8659 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
8660 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
8662 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
8663 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
8665 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
8666 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
8668 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
8669 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
8670 } else if (IS_VALLEYVIEW(dev
)) {
8671 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8672 if (I915_READ(VLV_DISPLAY_BASE
+ DP_C
) & DP_DETECTED
)
8673 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_C
, PORT_C
);
8675 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIB
) & SDVO_DETECTED
) {
8676 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIB
,
8678 if (I915_READ(VLV_DISPLAY_BASE
+ DP_B
) & DP_DETECTED
)
8679 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_B
, PORT_B
);
8681 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
8684 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
8685 DRM_DEBUG_KMS("probing SDVOB\n");
8686 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, true);
8687 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
8688 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8689 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
8692 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
)) {
8693 DRM_DEBUG_KMS("probing DP_B\n");
8694 intel_dp_init(dev
, DP_B
, PORT_B
);
8698 /* Before G4X SDVOC doesn't have its own detect register */
8700 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
8701 DRM_DEBUG_KMS("probing SDVOC\n");
8702 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, false);
8705 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
8707 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
8708 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8709 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
8711 if (SUPPORTS_INTEGRATED_DP(dev
)) {
8712 DRM_DEBUG_KMS("probing DP_C\n");
8713 intel_dp_init(dev
, DP_C
, PORT_C
);
8717 if (SUPPORTS_INTEGRATED_DP(dev
) &&
8718 (I915_READ(DP_D
) & DP_DETECTED
)) {
8719 DRM_DEBUG_KMS("probing DP_D\n");
8720 intel_dp_init(dev
, DP_D
, PORT_D
);
8722 } else if (IS_GEN2(dev
))
8723 intel_dvo_init(dev
);
8725 if (SUPPORTS_TV(dev
))
8728 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
8729 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
8730 encoder
->base
.possible_clones
=
8731 intel_encoder_clones(encoder
);
8734 intel_init_pch_refclk(dev
);
8736 drm_helper_move_panel_connectors_to_head(dev
);
8739 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
8741 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
8743 drm_framebuffer_cleanup(fb
);
8744 drm_gem_object_unreference_unlocked(&intel_fb
->obj
->base
);
8749 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
8750 struct drm_file
*file
,
8751 unsigned int *handle
)
8753 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
8754 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
8756 return drm_gem_handle_create(file
, &obj
->base
, handle
);
8759 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
8760 .destroy
= intel_user_framebuffer_destroy
,
8761 .create_handle
= intel_user_framebuffer_create_handle
,
8764 int intel_framebuffer_init(struct drm_device
*dev
,
8765 struct intel_framebuffer
*intel_fb
,
8766 struct drm_mode_fb_cmd2
*mode_cmd
,
8767 struct drm_i915_gem_object
*obj
)
8771 if (obj
->tiling_mode
== I915_TILING_Y
) {
8772 DRM_DEBUG("hardware does not support tiling Y\n");
8776 if (mode_cmd
->pitches
[0] & 63) {
8777 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8778 mode_cmd
->pitches
[0]);
8782 /* FIXME <= Gen4 stride limits are bit unclear */
8783 if (mode_cmd
->pitches
[0] > 32768) {
8784 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8785 mode_cmd
->pitches
[0]);
8789 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
8790 mode_cmd
->pitches
[0] != obj
->stride
) {
8791 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8792 mode_cmd
->pitches
[0], obj
->stride
);
8796 /* Reject formats not supported by any plane early. */
8797 switch (mode_cmd
->pixel_format
) {
8799 case DRM_FORMAT_RGB565
:
8800 case DRM_FORMAT_XRGB8888
:
8801 case DRM_FORMAT_ARGB8888
:
8803 case DRM_FORMAT_XRGB1555
:
8804 case DRM_FORMAT_ARGB1555
:
8805 if (INTEL_INFO(dev
)->gen
> 3) {
8806 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd
->pixel_format
);
8810 case DRM_FORMAT_XBGR8888
:
8811 case DRM_FORMAT_ABGR8888
:
8812 case DRM_FORMAT_XRGB2101010
:
8813 case DRM_FORMAT_ARGB2101010
:
8814 case DRM_FORMAT_XBGR2101010
:
8815 case DRM_FORMAT_ABGR2101010
:
8816 if (INTEL_INFO(dev
)->gen
< 4) {
8817 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd
->pixel_format
);
8821 case DRM_FORMAT_YUYV
:
8822 case DRM_FORMAT_UYVY
:
8823 case DRM_FORMAT_YVYU
:
8824 case DRM_FORMAT_VYUY
:
8825 if (INTEL_INFO(dev
)->gen
< 5) {
8826 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd
->pixel_format
);
8831 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd
->pixel_format
);
8835 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8836 if (mode_cmd
->offsets
[0] != 0)
8839 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
8840 intel_fb
->obj
= obj
;
8842 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
8844 DRM_ERROR("framebuffer init failed %d\n", ret
);
8851 static struct drm_framebuffer
*
8852 intel_user_framebuffer_create(struct drm_device
*dev
,
8853 struct drm_file
*filp
,
8854 struct drm_mode_fb_cmd2
*mode_cmd
)
8856 struct drm_i915_gem_object
*obj
;
8858 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
8859 mode_cmd
->handles
[0]));
8860 if (&obj
->base
== NULL
)
8861 return ERR_PTR(-ENOENT
);
8863 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
8866 static const struct drm_mode_config_funcs intel_mode_funcs
= {
8867 .fb_create
= intel_user_framebuffer_create
,
8868 .output_poll_changed
= intel_fb_output_poll_changed
,
8871 /* Set up chip specific display functions */
8872 static void intel_init_display(struct drm_device
*dev
)
8874 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8877 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
8878 dev_priv
->display
.crtc_mode_set
= haswell_crtc_mode_set
;
8879 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
8880 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
8881 dev_priv
->display
.off
= haswell_crtc_off
;
8882 dev_priv
->display
.update_plane
= ironlake_update_plane
;
8883 } else if (HAS_PCH_SPLIT(dev
)) {
8884 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
8885 dev_priv
->display
.crtc_mode_set
= ironlake_crtc_mode_set
;
8886 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
8887 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
8888 dev_priv
->display
.off
= ironlake_crtc_off
;
8889 dev_priv
->display
.update_plane
= ironlake_update_plane
;
8890 } else if (IS_VALLEYVIEW(dev
)) {
8891 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
8892 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
8893 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
8894 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
8895 dev_priv
->display
.off
= i9xx_crtc_off
;
8896 dev_priv
->display
.update_plane
= i9xx_update_plane
;
8898 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
8899 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
8900 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
8901 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
8902 dev_priv
->display
.off
= i9xx_crtc_off
;
8903 dev_priv
->display
.update_plane
= i9xx_update_plane
;
8906 /* Returns the core display clock speed */
8907 if (IS_VALLEYVIEW(dev
))
8908 dev_priv
->display
.get_display_clock_speed
=
8909 valleyview_get_display_clock_speed
;
8910 else if (IS_I945G(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
8911 dev_priv
->display
.get_display_clock_speed
=
8912 i945_get_display_clock_speed
;
8913 else if (IS_I915G(dev
))
8914 dev_priv
->display
.get_display_clock_speed
=
8915 i915_get_display_clock_speed
;
8916 else if (IS_I945GM(dev
) || IS_845G(dev
) || IS_PINEVIEW_M(dev
))
8917 dev_priv
->display
.get_display_clock_speed
=
8918 i9xx_misc_get_display_clock_speed
;
8919 else if (IS_I915GM(dev
))
8920 dev_priv
->display
.get_display_clock_speed
=
8921 i915gm_get_display_clock_speed
;
8922 else if (IS_I865G(dev
))
8923 dev_priv
->display
.get_display_clock_speed
=
8924 i865_get_display_clock_speed
;
8925 else if (IS_I85X(dev
))
8926 dev_priv
->display
.get_display_clock_speed
=
8927 i855_get_display_clock_speed
;
8929 dev_priv
->display
.get_display_clock_speed
=
8930 i830_get_display_clock_speed
;
8932 if (HAS_PCH_SPLIT(dev
)) {
8934 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
8935 dev_priv
->display
.write_eld
= ironlake_write_eld
;
8936 } else if (IS_GEN6(dev
)) {
8937 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
8938 dev_priv
->display
.write_eld
= ironlake_write_eld
;
8939 } else if (IS_IVYBRIDGE(dev
)) {
8940 /* FIXME: detect B0+ stepping and use auto training */
8941 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
8942 dev_priv
->display
.write_eld
= ironlake_write_eld
;
8943 dev_priv
->display
.modeset_global_resources
=
8944 ivb_modeset_global_resources
;
8945 } else if (IS_HASWELL(dev
)) {
8946 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
8947 dev_priv
->display
.write_eld
= haswell_write_eld
;
8948 dev_priv
->display
.modeset_global_resources
=
8949 haswell_modeset_global_resources
;
8951 } else if (IS_G4X(dev
)) {
8952 dev_priv
->display
.write_eld
= g4x_write_eld
;
8955 /* Default just returns -ENODEV to indicate unsupported */
8956 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
8958 switch (INTEL_INFO(dev
)->gen
) {
8960 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
8964 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
8969 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
8973 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
8976 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
8982 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8983 * resume, or other times. This quirk makes sure that's the case for
8986 static void quirk_pipea_force(struct drm_device
*dev
)
8988 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8990 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
8991 DRM_INFO("applying pipe a force quirk\n");
8995 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8997 static void quirk_ssc_force_disable(struct drm_device
*dev
)
8999 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9000 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
9001 DRM_INFO("applying lvds SSC disable quirk\n");
9005 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9008 static void quirk_invert_brightness(struct drm_device
*dev
)
9010 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9011 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
9012 DRM_INFO("applying inverted panel brightness quirk\n");
9015 struct intel_quirk
{
9017 int subsystem_vendor
;
9018 int subsystem_device
;
9019 void (*hook
)(struct drm_device
*dev
);
9022 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9023 struct intel_dmi_quirk
{
9024 void (*hook
)(struct drm_device
*dev
);
9025 const struct dmi_system_id (*dmi_id_list
)[];
9028 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
9030 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
9034 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
9036 .dmi_id_list
= &(const struct dmi_system_id
[]) {
9038 .callback
= intel_dmi_reverse_brightness
,
9039 .ident
= "NCR Corporation",
9040 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
9041 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
9044 { } /* terminating entry */
9046 .hook
= quirk_invert_brightness
,
9050 static struct intel_quirk intel_quirks
[] = {
9051 /* HP Mini needs pipe A force quirk (LP: #322104) */
9052 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
9054 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9055 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
9057 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9058 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
9060 /* 830/845 need to leave pipe A & dpll A up */
9061 { 0x2562, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
9062 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
9064 /* Lenovo U160 cannot use SSC on LVDS */
9065 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
9067 /* Sony Vaio Y cannot use SSC on LVDS */
9068 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
9070 /* Acer Aspire 5734Z must invert backlight brightness */
9071 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
9073 /* Acer/eMachines G725 */
9074 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
9076 /* Acer/eMachines e725 */
9077 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
9079 /* Acer/Packard Bell NCL20 */
9080 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
9082 /* Acer Aspire 4736Z */
9083 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
9086 static void intel_init_quirks(struct drm_device
*dev
)
9088 struct pci_dev
*d
= dev
->pdev
;
9091 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
9092 struct intel_quirk
*q
= &intel_quirks
[i
];
9094 if (d
->device
== q
->device
&&
9095 (d
->subsystem_vendor
== q
->subsystem_vendor
||
9096 q
->subsystem_vendor
== PCI_ANY_ID
) &&
9097 (d
->subsystem_device
== q
->subsystem_device
||
9098 q
->subsystem_device
== PCI_ANY_ID
))
9101 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
9102 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
9103 intel_dmi_quirks
[i
].hook(dev
);
9107 /* Disable the VGA plane that we never use */
9108 static void i915_disable_vga(struct drm_device
*dev
)
9110 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9112 u32 vga_reg
= i915_vgacntrl_reg(dev
);
9114 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
9115 outb(SR01
, VGA_SR_INDEX
);
9116 sr1
= inb(VGA_SR_DATA
);
9117 outb(sr1
| 1<<5, VGA_SR_DATA
);
9118 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
9121 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
9122 POSTING_READ(vga_reg
);
9125 void intel_modeset_init_hw(struct drm_device
*dev
)
9127 intel_init_power_well(dev
);
9129 intel_prepare_ddi(dev
);
9131 intel_init_clock_gating(dev
);
9133 mutex_lock(&dev
->struct_mutex
);
9134 intel_enable_gt_powersave(dev
);
9135 mutex_unlock(&dev
->struct_mutex
);
9138 void intel_modeset_init(struct drm_device
*dev
)
9140 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9143 drm_mode_config_init(dev
);
9145 dev
->mode_config
.min_width
= 0;
9146 dev
->mode_config
.min_height
= 0;
9148 dev
->mode_config
.preferred_depth
= 24;
9149 dev
->mode_config
.prefer_shadow
= 1;
9151 dev
->mode_config
.funcs
= &intel_mode_funcs
;
9153 intel_init_quirks(dev
);
9157 if (INTEL_INFO(dev
)->num_pipes
== 0)
9160 intel_init_display(dev
);
9163 dev
->mode_config
.max_width
= 2048;
9164 dev
->mode_config
.max_height
= 2048;
9165 } else if (IS_GEN3(dev
)) {
9166 dev
->mode_config
.max_width
= 4096;
9167 dev
->mode_config
.max_height
= 4096;
9169 dev
->mode_config
.max_width
= 8192;
9170 dev
->mode_config
.max_height
= 8192;
9172 dev
->mode_config
.fb_base
= dev_priv
->gtt
.mappable_base
;
9174 DRM_DEBUG_KMS("%d display pipe%s available.\n",
9175 INTEL_INFO(dev
)->num_pipes
,
9176 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
9178 for (i
= 0; i
< INTEL_INFO(dev
)->num_pipes
; i
++) {
9179 intel_crtc_init(dev
, i
);
9180 for (j
= 0; j
< dev_priv
->num_plane
; j
++) {
9181 ret
= intel_plane_init(dev
, i
, j
);
9183 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9184 pipe_name(i
), sprite_name(i
, j
), ret
);
9188 intel_cpu_pll_init(dev
);
9189 intel_pch_pll_init(dev
);
9191 /* Just disable it once at startup */
9192 i915_disable_vga(dev
);
9193 intel_setup_outputs(dev
);
9195 /* Just in case the BIOS is doing something questionable. */
9196 intel_disable_fbc(dev
);
9200 intel_connector_break_all_links(struct intel_connector
*connector
)
9202 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
9203 connector
->base
.encoder
= NULL
;
9204 connector
->encoder
->connectors_active
= false;
9205 connector
->encoder
->base
.crtc
= NULL
;
9208 static void intel_enable_pipe_a(struct drm_device
*dev
)
9210 struct intel_connector
*connector
;
9211 struct drm_connector
*crt
= NULL
;
9212 struct intel_load_detect_pipe load_detect_temp
;
9214 /* We can't just switch on the pipe A, we need to set things up with a
9215 * proper mode and output configuration. As a gross hack, enable pipe A
9216 * by enabling the load detect pipe once. */
9217 list_for_each_entry(connector
,
9218 &dev
->mode_config
.connector_list
,
9220 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
9221 crt
= &connector
->base
;
9229 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
))
9230 intel_release_load_detect_pipe(crt
, &load_detect_temp
);
9236 intel_check_plane_mapping(struct intel_crtc
*crtc
)
9238 struct drm_device
*dev
= crtc
->base
.dev
;
9239 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9242 if (INTEL_INFO(dev
)->num_pipes
== 1)
9245 reg
= DSPCNTR(!crtc
->plane
);
9246 val
= I915_READ(reg
);
9248 if ((val
& DISPLAY_PLANE_ENABLE
) &&
9249 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
9255 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
9257 struct drm_device
*dev
= crtc
->base
.dev
;
9258 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9261 /* Clear any frame start delays used for debugging left by the BIOS */
9262 reg
= PIPECONF(crtc
->config
.cpu_transcoder
);
9263 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
9265 /* We need to sanitize the plane -> pipe mapping first because this will
9266 * disable the crtc (and hence change the state) if it is wrong. Note
9267 * that gen4+ has a fixed plane -> pipe mapping. */
9268 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
9269 struct intel_connector
*connector
;
9272 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9273 crtc
->base
.base
.id
);
9275 /* Pipe has the wrong plane attached and the plane is active.
9276 * Temporarily change the plane mapping and disable everything
9278 plane
= crtc
->plane
;
9279 crtc
->plane
= !plane
;
9280 dev_priv
->display
.crtc_disable(&crtc
->base
);
9281 crtc
->plane
= plane
;
9283 /* ... and break all links. */
9284 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9286 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
9289 intel_connector_break_all_links(connector
);
9292 WARN_ON(crtc
->active
);
9293 crtc
->base
.enabled
= false;
9296 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
9297 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
9298 /* BIOS forgot to enable pipe A, this mostly happens after
9299 * resume. Force-enable the pipe to fix this, the update_dpms
9300 * call below we restore the pipe to the right state, but leave
9301 * the required bits on. */
9302 intel_enable_pipe_a(dev
);
9305 /* Adjust the state of the output pipe according to whether we
9306 * have active connectors/encoders. */
9307 intel_crtc_update_dpms(&crtc
->base
);
9309 if (crtc
->active
!= crtc
->base
.enabled
) {
9310 struct intel_encoder
*encoder
;
9312 /* This can happen either due to bugs in the get_hw_state
9313 * functions or because the pipe is force-enabled due to the
9315 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9317 crtc
->base
.enabled
? "enabled" : "disabled",
9318 crtc
->active
? "enabled" : "disabled");
9320 crtc
->base
.enabled
= crtc
->active
;
9322 /* Because we only establish the connector -> encoder ->
9323 * crtc links if something is active, this means the
9324 * crtc is now deactivated. Break the links. connector
9325 * -> encoder links are only establish when things are
9326 * actually up, hence no need to break them. */
9327 WARN_ON(crtc
->active
);
9329 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
9330 WARN_ON(encoder
->connectors_active
);
9331 encoder
->base
.crtc
= NULL
;
9336 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
9338 struct intel_connector
*connector
;
9339 struct drm_device
*dev
= encoder
->base
.dev
;
9341 /* We need to check both for a crtc link (meaning that the
9342 * encoder is active and trying to read from a pipe) and the
9343 * pipe itself being active. */
9344 bool has_active_crtc
= encoder
->base
.crtc
&&
9345 to_intel_crtc(encoder
->base
.crtc
)->active
;
9347 if (encoder
->connectors_active
&& !has_active_crtc
) {
9348 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9349 encoder
->base
.base
.id
,
9350 drm_get_encoder_name(&encoder
->base
));
9352 /* Connector is active, but has no active pipe. This is
9353 * fallout from our resume register restoring. Disable
9354 * the encoder manually again. */
9355 if (encoder
->base
.crtc
) {
9356 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9357 encoder
->base
.base
.id
,
9358 drm_get_encoder_name(&encoder
->base
));
9359 encoder
->disable(encoder
);
9362 /* Inconsistent output/port/pipe state happens presumably due to
9363 * a bug in one of the get_hw_state functions. Or someplace else
9364 * in our code, like the register restore mess on resume. Clamp
9365 * things to off as a safer default. */
9366 list_for_each_entry(connector
,
9367 &dev
->mode_config
.connector_list
,
9369 if (connector
->encoder
!= encoder
)
9372 intel_connector_break_all_links(connector
);
9375 /* Enabled encoders without active connectors will be fixed in
9376 * the crtc fixup. */
9379 void i915_redisable_vga(struct drm_device
*dev
)
9381 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9382 u32 vga_reg
= i915_vgacntrl_reg(dev
);
9384 if (I915_READ(vga_reg
) != VGA_DISP_DISABLE
) {
9385 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9386 i915_disable_vga(dev
);
9390 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9391 * and i915 state tracking structures. */
9392 void intel_modeset_setup_hw_state(struct drm_device
*dev
,
9395 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9398 struct drm_plane
*plane
;
9399 struct intel_crtc
*crtc
;
9400 struct intel_encoder
*encoder
;
9401 struct intel_connector
*connector
;
9404 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
9406 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
9407 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
9408 case TRANS_DDI_EDP_INPUT_A_ON
:
9409 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
9412 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
9415 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
9419 /* A bogus value has been programmed, disable
9421 WARN(1, "Bogus eDP source %08x\n", tmp
);
9422 intel_ddi_disable_transcoder_func(dev_priv
,
9427 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
9428 crtc
->config
.cpu_transcoder
= TRANSCODER_EDP
;
9430 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9436 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
9438 enum transcoder tmp
= crtc
->config
.cpu_transcoder
;
9439 memset(&crtc
->config
, 0, sizeof(crtc
->config
));
9440 crtc
->config
.cpu_transcoder
= tmp
;
9442 crtc
->active
= dev_priv
->display
.get_pipe_config(crtc
,
9445 crtc
->base
.enabled
= crtc
->active
;
9447 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9449 crtc
->active
? "enabled" : "disabled");
9453 intel_ddi_setup_hw_pll_state(dev
);
9455 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9459 if (encoder
->get_hw_state(encoder
, &pipe
)) {
9460 encoder
->base
.crtc
=
9461 dev_priv
->pipe_to_crtc_mapping
[pipe
];
9463 encoder
->base
.crtc
= NULL
;
9466 encoder
->connectors_active
= false;
9467 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9468 encoder
->base
.base
.id
,
9469 drm_get_encoder_name(&encoder
->base
),
9470 encoder
->base
.crtc
? "enabled" : "disabled",
9474 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9476 if (connector
->get_hw_state(connector
)) {
9477 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
9478 connector
->encoder
->connectors_active
= true;
9479 connector
->base
.encoder
= &connector
->encoder
->base
;
9481 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
9482 connector
->base
.encoder
= NULL
;
9484 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9485 connector
->base
.base
.id
,
9486 drm_get_connector_name(&connector
->base
),
9487 connector
->base
.encoder
? "enabled" : "disabled");
9490 /* HW state is read out, now we need to sanitize this mess. */
9491 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9493 intel_sanitize_encoder(encoder
);
9496 for_each_pipe(pipe
) {
9497 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
9498 intel_sanitize_crtc(crtc
);
9501 if (force_restore
) {
9503 * We need to use raw interfaces for restoring state to avoid
9504 * checking (bogus) intermediate states.
9506 for_each_pipe(pipe
) {
9507 struct drm_crtc
*crtc
=
9508 dev_priv
->pipe_to_crtc_mapping
[pipe
];
9510 __intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
,
9513 list_for_each_entry(plane
, &dev
->mode_config
.plane_list
, head
)
9514 intel_plane_restore(plane
);
9516 i915_redisable_vga(dev
);
9518 intel_modeset_update_staged_output_state(dev
);
9521 intel_modeset_check_state(dev
);
9523 drm_mode_config_reset(dev
);
9526 void intel_modeset_gem_init(struct drm_device
*dev
)
9528 intel_modeset_init_hw(dev
);
9530 intel_setup_overlay(dev
);
9532 intel_modeset_setup_hw_state(dev
, false);
9535 void intel_modeset_cleanup(struct drm_device
*dev
)
9537 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9538 struct drm_crtc
*crtc
;
9539 struct intel_crtc
*intel_crtc
;
9542 * Interrupts and polling as the first thing to avoid creating havoc.
9543 * Too much stuff here (turning of rps, connectors, ...) would
9544 * experience fancy races otherwise.
9546 drm_irq_uninstall(dev
);
9547 cancel_work_sync(&dev_priv
->hotplug_work
);
9549 * Due to the hpd irq storm handling the hotplug work can re-arm the
9550 * poll handlers. Hence disable polling after hpd handling is shut down.
9552 drm_kms_helper_poll_fini(dev
);
9554 mutex_lock(&dev
->struct_mutex
);
9556 intel_unregister_dsm_handler();
9558 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
9559 /* Skip inactive CRTCs */
9563 intel_crtc
= to_intel_crtc(crtc
);
9564 intel_increase_pllclock(crtc
);
9567 intel_disable_fbc(dev
);
9569 intel_disable_gt_powersave(dev
);
9571 ironlake_teardown_rc6(dev
);
9573 mutex_unlock(&dev
->struct_mutex
);
9575 /* flush any delayed tasks or pending work */
9576 flush_scheduled_work();
9578 /* destroy backlight, if any, before the connectors */
9579 intel_panel_destroy_backlight(dev
);
9581 drm_mode_config_cleanup(dev
);
9583 intel_cleanup_overlay(dev
);
9587 * Return which encoder is currently attached for connector.
9589 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
9591 return &intel_attached_encoder(connector
)->base
;
9594 void intel_connector_attach_encoder(struct intel_connector
*connector
,
9595 struct intel_encoder
*encoder
)
9597 connector
->encoder
= encoder
;
9598 drm_mode_connector_attach_encoder(&connector
->base
,
9603 * set vga decode state - true == enable VGA decode
9605 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
9607 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9610 pci_read_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, &gmch_ctrl
);
9612 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
9614 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
9615 pci_write_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, gmch_ctrl
);
9619 #ifdef CONFIG_DEBUG_FS
9620 #include <linux/seq_file.h>
9622 struct intel_display_error_state
{
9623 struct intel_cursor_error_state
{
9628 } cursor
[I915_MAX_PIPES
];
9630 struct intel_pipe_error_state
{
9640 } pipe
[I915_MAX_PIPES
];
9642 struct intel_plane_error_state
{
9650 } plane
[I915_MAX_PIPES
];
9653 struct intel_display_error_state
*
9654 intel_display_capture_error_state(struct drm_device
*dev
)
9656 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
9657 struct intel_display_error_state
*error
;
9658 enum transcoder cpu_transcoder
;
9661 error
= kmalloc(sizeof(*error
), GFP_ATOMIC
);
9666 cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
, i
);
9668 if (INTEL_INFO(dev
)->gen
<= 6 || IS_VALLEYVIEW(dev
)) {
9669 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
9670 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
9671 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
9673 error
->cursor
[i
].control
= I915_READ(CURCNTR_IVB(i
));
9674 error
->cursor
[i
].position
= I915_READ(CURPOS_IVB(i
));
9675 error
->cursor
[i
].base
= I915_READ(CURBASE_IVB(i
));
9678 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
9679 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
9680 if (INTEL_INFO(dev
)->gen
<= 3) {
9681 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
9682 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
9684 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
9685 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
9686 if (INTEL_INFO(dev
)->gen
>= 4) {
9687 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
9688 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
9691 error
->pipe
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
9692 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
9693 error
->pipe
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
9694 error
->pipe
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
9695 error
->pipe
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
9696 error
->pipe
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
9697 error
->pipe
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
9698 error
->pipe
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
9705 intel_display_print_error_state(struct seq_file
*m
,
9706 struct drm_device
*dev
,
9707 struct intel_display_error_state
*error
)
9711 seq_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
9713 seq_printf(m
, "Pipe [%d]:\n", i
);
9714 seq_printf(m
, " CONF: %08x\n", error
->pipe
[i
].conf
);
9715 seq_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
9716 seq_printf(m
, " HTOTAL: %08x\n", error
->pipe
[i
].htotal
);
9717 seq_printf(m
, " HBLANK: %08x\n", error
->pipe
[i
].hblank
);
9718 seq_printf(m
, " HSYNC: %08x\n", error
->pipe
[i
].hsync
);
9719 seq_printf(m
, " VTOTAL: %08x\n", error
->pipe
[i
].vtotal
);
9720 seq_printf(m
, " VBLANK: %08x\n", error
->pipe
[i
].vblank
);
9721 seq_printf(m
, " VSYNC: %08x\n", error
->pipe
[i
].vsync
);
9723 seq_printf(m
, "Plane [%d]:\n", i
);
9724 seq_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
9725 seq_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
9726 if (INTEL_INFO(dev
)->gen
<= 3) {
9727 seq_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
9728 seq_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
9730 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
9731 seq_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
9732 if (INTEL_INFO(dev
)->gen
>= 4) {
9733 seq_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
9734 seq_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
9737 seq_printf(m
, "Cursor [%d]:\n", i
);
9738 seq_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
9739 seq_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
9740 seq_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);