2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
32 #include "intel_drv.h"
35 #include "drm_dp_helper.h"
37 #include "drm_crtc_helper.h"
39 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
41 bool intel_pipe_has_type (struct drm_crtc
*crtc
, int type
);
42 static void intel_update_watermarks(struct drm_device
*dev
);
43 static void intel_increase_pllclock(struct drm_crtc
*crtc
, bool schedule
);
66 #define INTEL_P2_NUM 2
67 typedef struct intel_limit intel_limit_t
;
69 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
71 bool (* find_pll
)(const intel_limit_t
*, struct drm_crtc
*,
72 int, int, intel_clock_t
*);
75 #define I8XX_DOT_MIN 25000
76 #define I8XX_DOT_MAX 350000
77 #define I8XX_VCO_MIN 930000
78 #define I8XX_VCO_MAX 1400000
82 #define I8XX_M_MAX 140
83 #define I8XX_M1_MIN 18
84 #define I8XX_M1_MAX 26
86 #define I8XX_M2_MAX 16
88 #define I8XX_P_MAX 128
90 #define I8XX_P1_MAX 33
91 #define I8XX_P1_LVDS_MIN 1
92 #define I8XX_P1_LVDS_MAX 6
93 #define I8XX_P2_SLOW 4
94 #define I8XX_P2_FAST 2
95 #define I8XX_P2_LVDS_SLOW 14
96 #define I8XX_P2_LVDS_FAST 7
97 #define I8XX_P2_SLOW_LIMIT 165000
99 #define I9XX_DOT_MIN 20000
100 #define I9XX_DOT_MAX 400000
101 #define I9XX_VCO_MIN 1400000
102 #define I9XX_VCO_MAX 2800000
103 #define PINEVIEW_VCO_MIN 1700000
104 #define PINEVIEW_VCO_MAX 3500000
107 /* Pineview's Ncounter is a ring counter */
108 #define PINEVIEW_N_MIN 3
109 #define PINEVIEW_N_MAX 6
110 #define I9XX_M_MIN 70
111 #define I9XX_M_MAX 120
112 #define PINEVIEW_M_MIN 2
113 #define PINEVIEW_M_MAX 256
114 #define I9XX_M1_MIN 10
115 #define I9XX_M1_MAX 22
116 #define I9XX_M2_MIN 5
117 #define I9XX_M2_MAX 9
118 /* Pineview M1 is reserved, and must be 0 */
119 #define PINEVIEW_M1_MIN 0
120 #define PINEVIEW_M1_MAX 0
121 #define PINEVIEW_M2_MIN 0
122 #define PINEVIEW_M2_MAX 254
123 #define I9XX_P_SDVO_DAC_MIN 5
124 #define I9XX_P_SDVO_DAC_MAX 80
125 #define I9XX_P_LVDS_MIN 7
126 #define I9XX_P_LVDS_MAX 98
127 #define PINEVIEW_P_LVDS_MIN 7
128 #define PINEVIEW_P_LVDS_MAX 112
129 #define I9XX_P1_MIN 1
130 #define I9XX_P1_MAX 8
131 #define I9XX_P2_SDVO_DAC_SLOW 10
132 #define I9XX_P2_SDVO_DAC_FAST 5
133 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
134 #define I9XX_P2_LVDS_SLOW 14
135 #define I9XX_P2_LVDS_FAST 7
136 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
138 /*The parameter is for SDVO on G4x platform*/
139 #define G4X_DOT_SDVO_MIN 25000
140 #define G4X_DOT_SDVO_MAX 270000
141 #define G4X_VCO_MIN 1750000
142 #define G4X_VCO_MAX 3500000
143 #define G4X_N_SDVO_MIN 1
144 #define G4X_N_SDVO_MAX 4
145 #define G4X_M_SDVO_MIN 104
146 #define G4X_M_SDVO_MAX 138
147 #define G4X_M1_SDVO_MIN 17
148 #define G4X_M1_SDVO_MAX 23
149 #define G4X_M2_SDVO_MIN 5
150 #define G4X_M2_SDVO_MAX 11
151 #define G4X_P_SDVO_MIN 10
152 #define G4X_P_SDVO_MAX 30
153 #define G4X_P1_SDVO_MIN 1
154 #define G4X_P1_SDVO_MAX 3
155 #define G4X_P2_SDVO_SLOW 10
156 #define G4X_P2_SDVO_FAST 10
157 #define G4X_P2_SDVO_LIMIT 270000
159 /*The parameter is for HDMI_DAC on G4x platform*/
160 #define G4X_DOT_HDMI_DAC_MIN 22000
161 #define G4X_DOT_HDMI_DAC_MAX 400000
162 #define G4X_N_HDMI_DAC_MIN 1
163 #define G4X_N_HDMI_DAC_MAX 4
164 #define G4X_M_HDMI_DAC_MIN 104
165 #define G4X_M_HDMI_DAC_MAX 138
166 #define G4X_M1_HDMI_DAC_MIN 16
167 #define G4X_M1_HDMI_DAC_MAX 23
168 #define G4X_M2_HDMI_DAC_MIN 5
169 #define G4X_M2_HDMI_DAC_MAX 11
170 #define G4X_P_HDMI_DAC_MIN 5
171 #define G4X_P_HDMI_DAC_MAX 80
172 #define G4X_P1_HDMI_DAC_MIN 1
173 #define G4X_P1_HDMI_DAC_MAX 8
174 #define G4X_P2_HDMI_DAC_SLOW 10
175 #define G4X_P2_HDMI_DAC_FAST 5
176 #define G4X_P2_HDMI_DAC_LIMIT 165000
178 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
179 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
180 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
181 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
182 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
183 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
184 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
185 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
186 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
187 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
188 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
189 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
190 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
191 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
192 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
193 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
194 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
195 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
197 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
198 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
199 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
200 #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
201 #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
202 #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
203 #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
204 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
205 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
206 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
207 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
208 #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
209 #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
210 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
211 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
212 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
213 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
214 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
216 /*The parameter is for DISPLAY PORT on G4x platform*/
217 #define G4X_DOT_DISPLAY_PORT_MIN 161670
218 #define G4X_DOT_DISPLAY_PORT_MAX 227000
219 #define G4X_N_DISPLAY_PORT_MIN 1
220 #define G4X_N_DISPLAY_PORT_MAX 2
221 #define G4X_M_DISPLAY_PORT_MIN 97
222 #define G4X_M_DISPLAY_PORT_MAX 108
223 #define G4X_M1_DISPLAY_PORT_MIN 0x10
224 #define G4X_M1_DISPLAY_PORT_MAX 0x12
225 #define G4X_M2_DISPLAY_PORT_MIN 0x05
226 #define G4X_M2_DISPLAY_PORT_MAX 0x06
227 #define G4X_P_DISPLAY_PORT_MIN 10
228 #define G4X_P_DISPLAY_PORT_MAX 20
229 #define G4X_P1_DISPLAY_PORT_MIN 1
230 #define G4X_P1_DISPLAY_PORT_MAX 2
231 #define G4X_P2_DISPLAY_PORT_SLOW 10
232 #define G4X_P2_DISPLAY_PORT_FAST 10
233 #define G4X_P2_DISPLAY_PORT_LIMIT 0
236 /* as we calculate clock using (register_value + 2) for
237 N/M1/M2, so here the range value for them is (actual_value-2).
239 #define IRONLAKE_DOT_MIN 25000
240 #define IRONLAKE_DOT_MAX 350000
241 #define IRONLAKE_VCO_MIN 1760000
242 #define IRONLAKE_VCO_MAX 3510000
243 #define IRONLAKE_N_MIN 1
244 #define IRONLAKE_N_MAX 6
245 #define IRONLAKE_M_MIN 79
246 #define IRONLAKE_M_MAX 127
247 #define IRONLAKE_M1_MIN 12
248 #define IRONLAKE_M1_MAX 22
249 #define IRONLAKE_M2_MIN 5
250 #define IRONLAKE_M2_MAX 9
251 #define IRONLAKE_P_SDVO_DAC_MIN 5
252 #define IRONLAKE_P_SDVO_DAC_MAX 80
253 #define IRONLAKE_P_LVDS_MIN 28
254 #define IRONLAKE_P_LVDS_MAX 112
255 #define IRONLAKE_P1_MIN 1
256 #define IRONLAKE_P1_MAX 8
257 #define IRONLAKE_P2_SDVO_DAC_SLOW 10
258 #define IRONLAKE_P2_SDVO_DAC_FAST 5
259 #define IRONLAKE_P2_LVDS_SLOW 14 /* single channel */
260 #define IRONLAKE_P2_LVDS_FAST 7 /* double channel */
261 #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
263 #define IRONLAKE_P_DISPLAY_PORT_MIN 10
264 #define IRONLAKE_P_DISPLAY_PORT_MAX 20
265 #define IRONLAKE_P2_DISPLAY_PORT_FAST 10
266 #define IRONLAKE_P2_DISPLAY_PORT_SLOW 10
267 #define IRONLAKE_P2_DISPLAY_PORT_LIMIT 0
268 #define IRONLAKE_P1_DISPLAY_PORT_MIN 1
269 #define IRONLAKE_P1_DISPLAY_PORT_MAX 2
272 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
273 int target
, int refclk
, intel_clock_t
*best_clock
);
275 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
276 int target
, int refclk
, intel_clock_t
*best_clock
);
279 intel_find_pll_g4x_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
280 int target
, int refclk
, intel_clock_t
*best_clock
);
282 intel_find_pll_ironlake_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
283 int target
, int refclk
, intel_clock_t
*best_clock
);
285 static const intel_limit_t intel_limits_i8xx_dvo
= {
286 .dot
= { .min
= I8XX_DOT_MIN
, .max
= I8XX_DOT_MAX
},
287 .vco
= { .min
= I8XX_VCO_MIN
, .max
= I8XX_VCO_MAX
},
288 .n
= { .min
= I8XX_N_MIN
, .max
= I8XX_N_MAX
},
289 .m
= { .min
= I8XX_M_MIN
, .max
= I8XX_M_MAX
},
290 .m1
= { .min
= I8XX_M1_MIN
, .max
= I8XX_M1_MAX
},
291 .m2
= { .min
= I8XX_M2_MIN
, .max
= I8XX_M2_MAX
},
292 .p
= { .min
= I8XX_P_MIN
, .max
= I8XX_P_MAX
},
293 .p1
= { .min
= I8XX_P1_MIN
, .max
= I8XX_P1_MAX
},
294 .p2
= { .dot_limit
= I8XX_P2_SLOW_LIMIT
,
295 .p2_slow
= I8XX_P2_SLOW
, .p2_fast
= I8XX_P2_FAST
},
296 .find_pll
= intel_find_best_PLL
,
299 static const intel_limit_t intel_limits_i8xx_lvds
= {
300 .dot
= { .min
= I8XX_DOT_MIN
, .max
= I8XX_DOT_MAX
},
301 .vco
= { .min
= I8XX_VCO_MIN
, .max
= I8XX_VCO_MAX
},
302 .n
= { .min
= I8XX_N_MIN
, .max
= I8XX_N_MAX
},
303 .m
= { .min
= I8XX_M_MIN
, .max
= I8XX_M_MAX
},
304 .m1
= { .min
= I8XX_M1_MIN
, .max
= I8XX_M1_MAX
},
305 .m2
= { .min
= I8XX_M2_MIN
, .max
= I8XX_M2_MAX
},
306 .p
= { .min
= I8XX_P_MIN
, .max
= I8XX_P_MAX
},
307 .p1
= { .min
= I8XX_P1_LVDS_MIN
, .max
= I8XX_P1_LVDS_MAX
},
308 .p2
= { .dot_limit
= I8XX_P2_SLOW_LIMIT
,
309 .p2_slow
= I8XX_P2_LVDS_SLOW
, .p2_fast
= I8XX_P2_LVDS_FAST
},
310 .find_pll
= intel_find_best_PLL
,
313 static const intel_limit_t intel_limits_i9xx_sdvo
= {
314 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
315 .vco
= { .min
= I9XX_VCO_MIN
, .max
= I9XX_VCO_MAX
},
316 .n
= { .min
= I9XX_N_MIN
, .max
= I9XX_N_MAX
},
317 .m
= { .min
= I9XX_M_MIN
, .max
= I9XX_M_MAX
},
318 .m1
= { .min
= I9XX_M1_MIN
, .max
= I9XX_M1_MAX
},
319 .m2
= { .min
= I9XX_M2_MIN
, .max
= I9XX_M2_MAX
},
320 .p
= { .min
= I9XX_P_SDVO_DAC_MIN
, .max
= I9XX_P_SDVO_DAC_MAX
},
321 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
322 .p2
= { .dot_limit
= I9XX_P2_SDVO_DAC_SLOW_LIMIT
,
323 .p2_slow
= I9XX_P2_SDVO_DAC_SLOW
, .p2_fast
= I9XX_P2_SDVO_DAC_FAST
},
324 .find_pll
= intel_find_best_PLL
,
327 static const intel_limit_t intel_limits_i9xx_lvds
= {
328 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
329 .vco
= { .min
= I9XX_VCO_MIN
, .max
= I9XX_VCO_MAX
},
330 .n
= { .min
= I9XX_N_MIN
, .max
= I9XX_N_MAX
},
331 .m
= { .min
= I9XX_M_MIN
, .max
= I9XX_M_MAX
},
332 .m1
= { .min
= I9XX_M1_MIN
, .max
= I9XX_M1_MAX
},
333 .m2
= { .min
= I9XX_M2_MIN
, .max
= I9XX_M2_MAX
},
334 .p
= { .min
= I9XX_P_LVDS_MIN
, .max
= I9XX_P_LVDS_MAX
},
335 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
336 /* The single-channel range is 25-112Mhz, and dual-channel
337 * is 80-224Mhz. Prefer single channel as much as possible.
339 .p2
= { .dot_limit
= I9XX_P2_LVDS_SLOW_LIMIT
,
340 .p2_slow
= I9XX_P2_LVDS_SLOW
, .p2_fast
= I9XX_P2_LVDS_FAST
},
341 .find_pll
= intel_find_best_PLL
,
344 /* below parameter and function is for G4X Chipset Family*/
345 static const intel_limit_t intel_limits_g4x_sdvo
= {
346 .dot
= { .min
= G4X_DOT_SDVO_MIN
, .max
= G4X_DOT_SDVO_MAX
},
347 .vco
= { .min
= G4X_VCO_MIN
, .max
= G4X_VCO_MAX
},
348 .n
= { .min
= G4X_N_SDVO_MIN
, .max
= G4X_N_SDVO_MAX
},
349 .m
= { .min
= G4X_M_SDVO_MIN
, .max
= G4X_M_SDVO_MAX
},
350 .m1
= { .min
= G4X_M1_SDVO_MIN
, .max
= G4X_M1_SDVO_MAX
},
351 .m2
= { .min
= G4X_M2_SDVO_MIN
, .max
= G4X_M2_SDVO_MAX
},
352 .p
= { .min
= G4X_P_SDVO_MIN
, .max
= G4X_P_SDVO_MAX
},
353 .p1
= { .min
= G4X_P1_SDVO_MIN
, .max
= G4X_P1_SDVO_MAX
},
354 .p2
= { .dot_limit
= G4X_P2_SDVO_LIMIT
,
355 .p2_slow
= G4X_P2_SDVO_SLOW
,
356 .p2_fast
= G4X_P2_SDVO_FAST
358 .find_pll
= intel_g4x_find_best_PLL
,
361 static const intel_limit_t intel_limits_g4x_hdmi
= {
362 .dot
= { .min
= G4X_DOT_HDMI_DAC_MIN
, .max
= G4X_DOT_HDMI_DAC_MAX
},
363 .vco
= { .min
= G4X_VCO_MIN
, .max
= G4X_VCO_MAX
},
364 .n
= { .min
= G4X_N_HDMI_DAC_MIN
, .max
= G4X_N_HDMI_DAC_MAX
},
365 .m
= { .min
= G4X_M_HDMI_DAC_MIN
, .max
= G4X_M_HDMI_DAC_MAX
},
366 .m1
= { .min
= G4X_M1_HDMI_DAC_MIN
, .max
= G4X_M1_HDMI_DAC_MAX
},
367 .m2
= { .min
= G4X_M2_HDMI_DAC_MIN
, .max
= G4X_M2_HDMI_DAC_MAX
},
368 .p
= { .min
= G4X_P_HDMI_DAC_MIN
, .max
= G4X_P_HDMI_DAC_MAX
},
369 .p1
= { .min
= G4X_P1_HDMI_DAC_MIN
, .max
= G4X_P1_HDMI_DAC_MAX
},
370 .p2
= { .dot_limit
= G4X_P2_HDMI_DAC_LIMIT
,
371 .p2_slow
= G4X_P2_HDMI_DAC_SLOW
,
372 .p2_fast
= G4X_P2_HDMI_DAC_FAST
374 .find_pll
= intel_g4x_find_best_PLL
,
377 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
378 .dot
= { .min
= G4X_DOT_SINGLE_CHANNEL_LVDS_MIN
,
379 .max
= G4X_DOT_SINGLE_CHANNEL_LVDS_MAX
},
380 .vco
= { .min
= G4X_VCO_MIN
,
381 .max
= G4X_VCO_MAX
},
382 .n
= { .min
= G4X_N_SINGLE_CHANNEL_LVDS_MIN
,
383 .max
= G4X_N_SINGLE_CHANNEL_LVDS_MAX
},
384 .m
= { .min
= G4X_M_SINGLE_CHANNEL_LVDS_MIN
,
385 .max
= G4X_M_SINGLE_CHANNEL_LVDS_MAX
},
386 .m1
= { .min
= G4X_M1_SINGLE_CHANNEL_LVDS_MIN
,
387 .max
= G4X_M1_SINGLE_CHANNEL_LVDS_MAX
},
388 .m2
= { .min
= G4X_M2_SINGLE_CHANNEL_LVDS_MIN
,
389 .max
= G4X_M2_SINGLE_CHANNEL_LVDS_MAX
},
390 .p
= { .min
= G4X_P_SINGLE_CHANNEL_LVDS_MIN
,
391 .max
= G4X_P_SINGLE_CHANNEL_LVDS_MAX
},
392 .p1
= { .min
= G4X_P1_SINGLE_CHANNEL_LVDS_MIN
,
393 .max
= G4X_P1_SINGLE_CHANNEL_LVDS_MAX
},
394 .p2
= { .dot_limit
= G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT
,
395 .p2_slow
= G4X_P2_SINGLE_CHANNEL_LVDS_SLOW
,
396 .p2_fast
= G4X_P2_SINGLE_CHANNEL_LVDS_FAST
398 .find_pll
= intel_g4x_find_best_PLL
,
401 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
402 .dot
= { .min
= G4X_DOT_DUAL_CHANNEL_LVDS_MIN
,
403 .max
= G4X_DOT_DUAL_CHANNEL_LVDS_MAX
},
404 .vco
= { .min
= G4X_VCO_MIN
,
405 .max
= G4X_VCO_MAX
},
406 .n
= { .min
= G4X_N_DUAL_CHANNEL_LVDS_MIN
,
407 .max
= G4X_N_DUAL_CHANNEL_LVDS_MAX
},
408 .m
= { .min
= G4X_M_DUAL_CHANNEL_LVDS_MIN
,
409 .max
= G4X_M_DUAL_CHANNEL_LVDS_MAX
},
410 .m1
= { .min
= G4X_M1_DUAL_CHANNEL_LVDS_MIN
,
411 .max
= G4X_M1_DUAL_CHANNEL_LVDS_MAX
},
412 .m2
= { .min
= G4X_M2_DUAL_CHANNEL_LVDS_MIN
,
413 .max
= G4X_M2_DUAL_CHANNEL_LVDS_MAX
},
414 .p
= { .min
= G4X_P_DUAL_CHANNEL_LVDS_MIN
,
415 .max
= G4X_P_DUAL_CHANNEL_LVDS_MAX
},
416 .p1
= { .min
= G4X_P1_DUAL_CHANNEL_LVDS_MIN
,
417 .max
= G4X_P1_DUAL_CHANNEL_LVDS_MAX
},
418 .p2
= { .dot_limit
= G4X_P2_DUAL_CHANNEL_LVDS_LIMIT
,
419 .p2_slow
= G4X_P2_DUAL_CHANNEL_LVDS_SLOW
,
420 .p2_fast
= G4X_P2_DUAL_CHANNEL_LVDS_FAST
422 .find_pll
= intel_g4x_find_best_PLL
,
425 static const intel_limit_t intel_limits_g4x_display_port
= {
426 .dot
= { .min
= G4X_DOT_DISPLAY_PORT_MIN
,
427 .max
= G4X_DOT_DISPLAY_PORT_MAX
},
428 .vco
= { .min
= G4X_VCO_MIN
,
430 .n
= { .min
= G4X_N_DISPLAY_PORT_MIN
,
431 .max
= G4X_N_DISPLAY_PORT_MAX
},
432 .m
= { .min
= G4X_M_DISPLAY_PORT_MIN
,
433 .max
= G4X_M_DISPLAY_PORT_MAX
},
434 .m1
= { .min
= G4X_M1_DISPLAY_PORT_MIN
,
435 .max
= G4X_M1_DISPLAY_PORT_MAX
},
436 .m2
= { .min
= G4X_M2_DISPLAY_PORT_MIN
,
437 .max
= G4X_M2_DISPLAY_PORT_MAX
},
438 .p
= { .min
= G4X_P_DISPLAY_PORT_MIN
,
439 .max
= G4X_P_DISPLAY_PORT_MAX
},
440 .p1
= { .min
= G4X_P1_DISPLAY_PORT_MIN
,
441 .max
= G4X_P1_DISPLAY_PORT_MAX
},
442 .p2
= { .dot_limit
= G4X_P2_DISPLAY_PORT_LIMIT
,
443 .p2_slow
= G4X_P2_DISPLAY_PORT_SLOW
,
444 .p2_fast
= G4X_P2_DISPLAY_PORT_FAST
},
445 .find_pll
= intel_find_pll_g4x_dp
,
448 static const intel_limit_t intel_limits_pineview_sdvo
= {
449 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
450 .vco
= { .min
= PINEVIEW_VCO_MIN
, .max
= PINEVIEW_VCO_MAX
},
451 .n
= { .min
= PINEVIEW_N_MIN
, .max
= PINEVIEW_N_MAX
},
452 .m
= { .min
= PINEVIEW_M_MIN
, .max
= PINEVIEW_M_MAX
},
453 .m1
= { .min
= PINEVIEW_M1_MIN
, .max
= PINEVIEW_M1_MAX
},
454 .m2
= { .min
= PINEVIEW_M2_MIN
, .max
= PINEVIEW_M2_MAX
},
455 .p
= { .min
= I9XX_P_SDVO_DAC_MIN
, .max
= I9XX_P_SDVO_DAC_MAX
},
456 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
457 .p2
= { .dot_limit
= I9XX_P2_SDVO_DAC_SLOW_LIMIT
,
458 .p2_slow
= I9XX_P2_SDVO_DAC_SLOW
, .p2_fast
= I9XX_P2_SDVO_DAC_FAST
},
459 .find_pll
= intel_find_best_PLL
,
462 static const intel_limit_t intel_limits_pineview_lvds
= {
463 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
464 .vco
= { .min
= PINEVIEW_VCO_MIN
, .max
= PINEVIEW_VCO_MAX
},
465 .n
= { .min
= PINEVIEW_N_MIN
, .max
= PINEVIEW_N_MAX
},
466 .m
= { .min
= PINEVIEW_M_MIN
, .max
= PINEVIEW_M_MAX
},
467 .m1
= { .min
= PINEVIEW_M1_MIN
, .max
= PINEVIEW_M1_MAX
},
468 .m2
= { .min
= PINEVIEW_M2_MIN
, .max
= PINEVIEW_M2_MAX
},
469 .p
= { .min
= PINEVIEW_P_LVDS_MIN
, .max
= PINEVIEW_P_LVDS_MAX
},
470 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
471 /* Pineview only supports single-channel mode. */
472 .p2
= { .dot_limit
= I9XX_P2_LVDS_SLOW_LIMIT
,
473 .p2_slow
= I9XX_P2_LVDS_SLOW
, .p2_fast
= I9XX_P2_LVDS_SLOW
},
474 .find_pll
= intel_find_best_PLL
,
477 static const intel_limit_t intel_limits_ironlake_sdvo
= {
478 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
479 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
480 .n
= { .min
= IRONLAKE_N_MIN
, .max
= IRONLAKE_N_MAX
},
481 .m
= { .min
= IRONLAKE_M_MIN
, .max
= IRONLAKE_M_MAX
},
482 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
483 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
484 .p
= { .min
= IRONLAKE_P_SDVO_DAC_MIN
, .max
= IRONLAKE_P_SDVO_DAC_MAX
},
485 .p1
= { .min
= IRONLAKE_P1_MIN
, .max
= IRONLAKE_P1_MAX
},
486 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
487 .p2_slow
= IRONLAKE_P2_SDVO_DAC_SLOW
,
488 .p2_fast
= IRONLAKE_P2_SDVO_DAC_FAST
},
489 .find_pll
= intel_g4x_find_best_PLL
,
492 static const intel_limit_t intel_limits_ironlake_lvds
= {
493 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
494 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
495 .n
= { .min
= IRONLAKE_N_MIN
, .max
= IRONLAKE_N_MAX
},
496 .m
= { .min
= IRONLAKE_M_MIN
, .max
= IRONLAKE_M_MAX
},
497 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
498 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
499 .p
= { .min
= IRONLAKE_P_LVDS_MIN
, .max
= IRONLAKE_P_LVDS_MAX
},
500 .p1
= { .min
= IRONLAKE_P1_MIN
, .max
= IRONLAKE_P1_MAX
},
501 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
502 .p2_slow
= IRONLAKE_P2_LVDS_SLOW
,
503 .p2_fast
= IRONLAKE_P2_LVDS_FAST
},
504 .find_pll
= intel_g4x_find_best_PLL
,
507 static const intel_limit_t intel_limits_ironlake_display_port
= {
508 .dot
= { .min
= IRONLAKE_DOT_MIN
,
509 .max
= IRONLAKE_DOT_MAX
},
510 .vco
= { .min
= IRONLAKE_VCO_MIN
,
511 .max
= IRONLAKE_VCO_MAX
},
512 .n
= { .min
= IRONLAKE_N_MIN
,
513 .max
= IRONLAKE_N_MAX
},
514 .m
= { .min
= IRONLAKE_M_MIN
,
515 .max
= IRONLAKE_M_MAX
},
516 .m1
= { .min
= IRONLAKE_M1_MIN
,
517 .max
= IRONLAKE_M1_MAX
},
518 .m2
= { .min
= IRONLAKE_M2_MIN
,
519 .max
= IRONLAKE_M2_MAX
},
520 .p
= { .min
= IRONLAKE_P_DISPLAY_PORT_MIN
,
521 .max
= IRONLAKE_P_DISPLAY_PORT_MAX
},
522 .p1
= { .min
= IRONLAKE_P1_DISPLAY_PORT_MIN
,
523 .max
= IRONLAKE_P1_DISPLAY_PORT_MAX
},
524 .p2
= { .dot_limit
= IRONLAKE_P2_DISPLAY_PORT_LIMIT
,
525 .p2_slow
= IRONLAKE_P2_DISPLAY_PORT_SLOW
,
526 .p2_fast
= IRONLAKE_P2_DISPLAY_PORT_FAST
},
527 .find_pll
= intel_find_pll_ironlake_dp
,
530 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
)
532 const intel_limit_t
*limit
;
533 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
534 limit
= &intel_limits_ironlake_lvds
;
535 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
537 limit
= &intel_limits_ironlake_display_port
;
539 limit
= &intel_limits_ironlake_sdvo
;
544 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
546 struct drm_device
*dev
= crtc
->dev
;
547 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
548 const intel_limit_t
*limit
;
550 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
551 if ((I915_READ(LVDS
) & LVDS_CLKB_POWER_MASK
) ==
553 /* LVDS with dual channel */
554 limit
= &intel_limits_g4x_dual_channel_lvds
;
556 /* LVDS with dual channel */
557 limit
= &intel_limits_g4x_single_channel_lvds
;
558 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
559 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
560 limit
= &intel_limits_g4x_hdmi
;
561 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
562 limit
= &intel_limits_g4x_sdvo
;
563 } else if (intel_pipe_has_type (crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
564 limit
= &intel_limits_g4x_display_port
;
565 } else /* The option is for other outputs */
566 limit
= &intel_limits_i9xx_sdvo
;
571 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
)
573 struct drm_device
*dev
= crtc
->dev
;
574 const intel_limit_t
*limit
;
576 if (IS_IRONLAKE(dev
))
577 limit
= intel_ironlake_limit(crtc
);
578 else if (IS_G4X(dev
)) {
579 limit
= intel_g4x_limit(crtc
);
580 } else if (IS_I9XX(dev
) && !IS_PINEVIEW(dev
)) {
581 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
582 limit
= &intel_limits_i9xx_lvds
;
584 limit
= &intel_limits_i9xx_sdvo
;
585 } else if (IS_PINEVIEW(dev
)) {
586 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
587 limit
= &intel_limits_pineview_lvds
;
589 limit
= &intel_limits_pineview_sdvo
;
591 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
592 limit
= &intel_limits_i8xx_lvds
;
594 limit
= &intel_limits_i8xx_dvo
;
599 /* m1 is reserved as 0 in Pineview, n is a ring counter */
600 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
602 clock
->m
= clock
->m2
+ 2;
603 clock
->p
= clock
->p1
* clock
->p2
;
604 clock
->vco
= refclk
* clock
->m
/ clock
->n
;
605 clock
->dot
= clock
->vco
/ clock
->p
;
608 static void intel_clock(struct drm_device
*dev
, int refclk
, intel_clock_t
*clock
)
610 if (IS_PINEVIEW(dev
)) {
611 pineview_clock(refclk
, clock
);
614 clock
->m
= 5 * (clock
->m1
+ 2) + (clock
->m2
+ 2);
615 clock
->p
= clock
->p1
* clock
->p2
;
616 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
617 clock
->dot
= clock
->vco
/ clock
->p
;
621 * Returns whether any output on the specified pipe is of the specified type
623 bool intel_pipe_has_type (struct drm_crtc
*crtc
, int type
)
625 struct drm_device
*dev
= crtc
->dev
;
626 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
627 struct drm_connector
*l_entry
;
629 list_for_each_entry(l_entry
, &mode_config
->connector_list
, head
) {
630 if (l_entry
->encoder
&&
631 l_entry
->encoder
->crtc
== crtc
) {
632 struct intel_output
*intel_output
= to_intel_output(l_entry
);
633 if (intel_output
->type
== type
)
640 struct drm_connector
*
641 intel_pipe_get_output (struct drm_crtc
*crtc
)
643 struct drm_device
*dev
= crtc
->dev
;
644 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
645 struct drm_connector
*l_entry
, *ret
= NULL
;
647 list_for_each_entry(l_entry
, &mode_config
->connector_list
, head
) {
648 if (l_entry
->encoder
&&
649 l_entry
->encoder
->crtc
== crtc
) {
657 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
659 * Returns whether the given set of divisors are valid for a given refclk with
660 * the given connectors.
663 static bool intel_PLL_is_valid(struct drm_crtc
*crtc
, intel_clock_t
*clock
)
665 const intel_limit_t
*limit
= intel_limit (crtc
);
666 struct drm_device
*dev
= crtc
->dev
;
668 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
669 INTELPllInvalid ("p1 out of range\n");
670 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
671 INTELPllInvalid ("p out of range\n");
672 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
673 INTELPllInvalid ("m2 out of range\n");
674 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
675 INTELPllInvalid ("m1 out of range\n");
676 if (clock
->m1
<= clock
->m2
&& !IS_PINEVIEW(dev
))
677 INTELPllInvalid ("m1 <= m2\n");
678 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
679 INTELPllInvalid ("m out of range\n");
680 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
681 INTELPllInvalid ("n out of range\n");
682 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
683 INTELPllInvalid ("vco out of range\n");
684 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
685 * connector, etc., rather than just a single range.
687 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
688 INTELPllInvalid ("dot out of range\n");
694 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
695 int target
, int refclk
, intel_clock_t
*best_clock
)
698 struct drm_device
*dev
= crtc
->dev
;
699 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
703 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
704 (I915_READ(LVDS
)) != 0) {
706 * For LVDS, if the panel is on, just rely on its current
707 * settings for dual-channel. We haven't figured out how to
708 * reliably set up different single/dual channel state, if we
711 if ((I915_READ(LVDS
) & LVDS_CLKB_POWER_MASK
) ==
713 clock
.p2
= limit
->p2
.p2_fast
;
715 clock
.p2
= limit
->p2
.p2_slow
;
717 if (target
< limit
->p2
.dot_limit
)
718 clock
.p2
= limit
->p2
.p2_slow
;
720 clock
.p2
= limit
->p2
.p2_fast
;
723 memset (best_clock
, 0, sizeof (*best_clock
));
725 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
727 for (clock
.m2
= limit
->m2
.min
;
728 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
729 /* m1 is always 0 in Pineview */
730 if (clock
.m2
>= clock
.m1
&& !IS_PINEVIEW(dev
))
732 for (clock
.n
= limit
->n
.min
;
733 clock
.n
<= limit
->n
.max
; clock
.n
++) {
734 for (clock
.p1
= limit
->p1
.min
;
735 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
738 intel_clock(dev
, refclk
, &clock
);
740 if (!intel_PLL_is_valid(crtc
, &clock
))
743 this_err
= abs(clock
.dot
- target
);
744 if (this_err
< err
) {
753 return (err
!= target
);
757 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
758 int target
, int refclk
, intel_clock_t
*best_clock
)
760 struct drm_device
*dev
= crtc
->dev
;
761 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
765 /* approximately equals target * 0.00488 */
766 int err_most
= (target
>> 8) + (target
>> 10);
769 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
772 if (IS_IRONLAKE(dev
))
776 if ((I915_READ(lvds_reg
) & LVDS_CLKB_POWER_MASK
) ==
778 clock
.p2
= limit
->p2
.p2_fast
;
780 clock
.p2
= limit
->p2
.p2_slow
;
782 if (target
< limit
->p2
.dot_limit
)
783 clock
.p2
= limit
->p2
.p2_slow
;
785 clock
.p2
= limit
->p2
.p2_fast
;
788 memset(best_clock
, 0, sizeof(*best_clock
));
789 max_n
= limit
->n
.max
;
790 /* based on hardware requriment prefer smaller n to precision */
791 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
792 /* based on hardware requirment prefere larger m1,m2 */
793 for (clock
.m1
= limit
->m1
.max
;
794 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
795 for (clock
.m2
= limit
->m2
.max
;
796 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
797 for (clock
.p1
= limit
->p1
.max
;
798 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
801 intel_clock(dev
, refclk
, &clock
);
802 if (!intel_PLL_is_valid(crtc
, &clock
))
804 this_err
= abs(clock
.dot
- target
) ;
805 if (this_err
< err_most
) {
819 intel_find_pll_ironlake_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
820 int target
, int refclk
, intel_clock_t
*best_clock
)
822 struct drm_device
*dev
= crtc
->dev
;
825 /* return directly when it is eDP */
829 if (target
< 200000) {
842 intel_clock(dev
, refclk
, &clock
);
843 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
847 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
849 intel_find_pll_g4x_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
850 int target
, int refclk
, intel_clock_t
*best_clock
)
853 if (target
< 200000) {
866 clock
.m
= 5 * (clock
.m1
+ 2) + (clock
.m2
+ 2);
867 clock
.p
= (clock
.p1
* clock
.p2
);
868 clock
.dot
= 96000 * clock
.m
/ (clock
.n
+ 2) / clock
.p
;
870 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
875 intel_wait_for_vblank(struct drm_device
*dev
)
877 /* Wait for 20ms, i.e. one cycle at 50hz. */
881 /* Parameters have changed, update FBC info */
882 static void i8xx_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
884 struct drm_device
*dev
= crtc
->dev
;
885 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
886 struct drm_framebuffer
*fb
= crtc
->fb
;
887 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
888 struct drm_i915_gem_object
*obj_priv
= intel_fb
->obj
->driver_private
;
889 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
891 u32 fbc_ctl
, fbc_ctl2
;
893 dev_priv
->cfb_pitch
= dev_priv
->cfb_size
/ FBC_LL_SIZE
;
895 if (fb
->pitch
< dev_priv
->cfb_pitch
)
896 dev_priv
->cfb_pitch
= fb
->pitch
;
898 /* FBC_CTL wants 64B units */
899 dev_priv
->cfb_pitch
= (dev_priv
->cfb_pitch
/ 64) - 1;
900 dev_priv
->cfb_fence
= obj_priv
->fence_reg
;
901 dev_priv
->cfb_plane
= intel_crtc
->plane
;
902 plane
= dev_priv
->cfb_plane
== 0 ? FBC_CTL_PLANEA
: FBC_CTL_PLANEB
;
905 for (i
= 0; i
< (FBC_LL_SIZE
/ 32) + 1; i
++)
906 I915_WRITE(FBC_TAG
+ (i
* 4), 0);
909 fbc_ctl2
= FBC_CTL_FENCE_DBL
| FBC_CTL_IDLE_IMM
| plane
;
910 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
911 fbc_ctl2
|= FBC_CTL_CPU_FENCE
;
912 I915_WRITE(FBC_CONTROL2
, fbc_ctl2
);
913 I915_WRITE(FBC_FENCE_OFF
, crtc
->y
);
916 fbc_ctl
= FBC_CTL_EN
| FBC_CTL_PERIODIC
;
917 fbc_ctl
|= (dev_priv
->cfb_pitch
& 0xff) << FBC_CTL_STRIDE_SHIFT
;
918 fbc_ctl
|= (interval
& 0x2fff) << FBC_CTL_INTERVAL_SHIFT
;
919 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
920 fbc_ctl
|= dev_priv
->cfb_fence
;
921 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
923 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
924 dev_priv
->cfb_pitch
, crtc
->y
, dev_priv
->cfb_plane
);
927 void i8xx_disable_fbc(struct drm_device
*dev
)
929 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
932 if (!I915_HAS_FBC(dev
))
935 /* Disable compression */
936 fbc_ctl
= I915_READ(FBC_CONTROL
);
937 fbc_ctl
&= ~FBC_CTL_EN
;
938 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
940 /* Wait for compressing bit to clear */
941 while (I915_READ(FBC_STATUS
) & FBC_STAT_COMPRESSING
)
944 intel_wait_for_vblank(dev
);
946 DRM_DEBUG_KMS("disabled FBC\n");
949 static bool i8xx_fbc_enabled(struct drm_crtc
*crtc
)
951 struct drm_device
*dev
= crtc
->dev
;
952 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
954 return I915_READ(FBC_CONTROL
) & FBC_CTL_EN
;
957 static void g4x_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
959 struct drm_device
*dev
= crtc
->dev
;
960 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
961 struct drm_framebuffer
*fb
= crtc
->fb
;
962 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
963 struct drm_i915_gem_object
*obj_priv
= intel_fb
->obj
->driver_private
;
964 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
965 int plane
= (intel_crtc
->plane
== 0 ? DPFC_CTL_PLANEA
:
967 unsigned long stall_watermark
= 200;
970 dev_priv
->cfb_pitch
= (dev_priv
->cfb_pitch
/ 64) - 1;
971 dev_priv
->cfb_fence
= obj_priv
->fence_reg
;
972 dev_priv
->cfb_plane
= intel_crtc
->plane
;
974 dpfc_ctl
= plane
| DPFC_SR_EN
| DPFC_CTL_LIMIT_1X
;
975 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
976 dpfc_ctl
|= DPFC_CTL_FENCE_EN
| dev_priv
->cfb_fence
;
977 I915_WRITE(DPFC_CHICKEN
, DPFC_HT_MODIFY
);
979 I915_WRITE(DPFC_CHICKEN
, ~DPFC_HT_MODIFY
);
982 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
);
983 I915_WRITE(DPFC_RECOMP_CTL
, DPFC_RECOMP_STALL_EN
|
984 (stall_watermark
<< DPFC_RECOMP_STALL_WM_SHIFT
) |
985 (interval
<< DPFC_RECOMP_TIMER_COUNT_SHIFT
));
986 I915_WRITE(DPFC_FENCE_YOFF
, crtc
->y
);
989 I915_WRITE(DPFC_CONTROL
, I915_READ(DPFC_CONTROL
) | DPFC_CTL_EN
);
991 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc
->plane
);
994 void g4x_disable_fbc(struct drm_device
*dev
)
996 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
999 /* Disable compression */
1000 dpfc_ctl
= I915_READ(DPFC_CONTROL
);
1001 dpfc_ctl
&= ~DPFC_CTL_EN
;
1002 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
);
1003 intel_wait_for_vblank(dev
);
1005 DRM_DEBUG_KMS("disabled FBC\n");
1008 static bool g4x_fbc_enabled(struct drm_crtc
*crtc
)
1010 struct drm_device
*dev
= crtc
->dev
;
1011 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1013 return I915_READ(DPFC_CONTROL
) & DPFC_CTL_EN
;
1017 * intel_update_fbc - enable/disable FBC as needed
1018 * @crtc: CRTC to point the compressor at
1019 * @mode: mode in use
1021 * Set up the framebuffer compression hardware at mode set time. We
1022 * enable it if possible:
1023 * - plane A only (on pre-965)
1024 * - no pixel mulitply/line duplication
1025 * - no alpha buffer discard
1027 * - framebuffer <= 2048 in width, 1536 in height
1029 * We can't assume that any compression will take place (worst case),
1030 * so the compressed buffer has to be the same size as the uncompressed
1031 * one. It also must reside (along with the line length buffer) in
1034 * We need to enable/disable FBC on a global basis.
1036 static void intel_update_fbc(struct drm_crtc
*crtc
,
1037 struct drm_display_mode
*mode
)
1039 struct drm_device
*dev
= crtc
->dev
;
1040 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1041 struct drm_framebuffer
*fb
= crtc
->fb
;
1042 struct intel_framebuffer
*intel_fb
;
1043 struct drm_i915_gem_object
*obj_priv
;
1044 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1045 int plane
= intel_crtc
->plane
;
1047 if (!i915_powersave
)
1050 if (!dev_priv
->display
.fbc_enabled
||
1051 !dev_priv
->display
.enable_fbc
||
1052 !dev_priv
->display
.disable_fbc
)
1058 intel_fb
= to_intel_framebuffer(fb
);
1059 obj_priv
= intel_fb
->obj
->driver_private
;
1062 * If FBC is already on, we just have to verify that we can
1063 * keep it that way...
1064 * Need to disable if:
1065 * - changing FBC params (stride, fence, mode)
1066 * - new fb is too large to fit in compressed buffer
1067 * - going to an unsupported config (interlace, pixel multiply, etc.)
1069 if (intel_fb
->obj
->size
> dev_priv
->cfb_size
) {
1070 DRM_DEBUG_KMS("framebuffer too large, disabling "
1074 if ((mode
->flags
& DRM_MODE_FLAG_INTERLACE
) ||
1075 (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)) {
1076 DRM_DEBUG_KMS("mode incompatible with compression, "
1080 if ((mode
->hdisplay
> 2048) ||
1081 (mode
->vdisplay
> 1536)) {
1082 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1085 if ((IS_I915GM(dev
) || IS_I945GM(dev
)) && plane
!= 0) {
1086 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1089 if (obj_priv
->tiling_mode
!= I915_TILING_X
) {
1090 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1094 if (dev_priv
->display
.fbc_enabled(crtc
)) {
1095 /* We can re-enable it in this case, but need to update pitch */
1096 if (fb
->pitch
> dev_priv
->cfb_pitch
)
1097 dev_priv
->display
.disable_fbc(dev
);
1098 if (obj_priv
->fence_reg
!= dev_priv
->cfb_fence
)
1099 dev_priv
->display
.disable_fbc(dev
);
1100 if (plane
!= dev_priv
->cfb_plane
)
1101 dev_priv
->display
.disable_fbc(dev
);
1104 if (!dev_priv
->display
.fbc_enabled(crtc
)) {
1105 /* Now try to turn it back on if possible */
1106 dev_priv
->display
.enable_fbc(crtc
, 500);
1112 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1113 /* Multiple disables should be harmless */
1114 if (dev_priv
->display
.fbc_enabled(crtc
))
1115 dev_priv
->display
.disable_fbc(dev
);
1119 intel_pin_and_fence_fb_obj(struct drm_device
*dev
, struct drm_gem_object
*obj
)
1121 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1125 switch (obj_priv
->tiling_mode
) {
1126 case I915_TILING_NONE
:
1127 alignment
= 64 * 1024;
1130 /* pin() will align the object as required by fence */
1134 /* FIXME: Is this true? */
1135 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1141 ret
= i915_gem_object_pin(obj
, alignment
);
1145 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1146 * fence, whereas 965+ only requires a fence if using
1147 * framebuffer compression. For simplicity, we always install
1148 * a fence as the cost is not that onerous.
1150 if (obj_priv
->fence_reg
== I915_FENCE_REG_NONE
&&
1151 obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1152 ret
= i915_gem_object_get_fence_reg(obj
);
1154 i915_gem_object_unpin(obj
);
1163 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
1164 struct drm_framebuffer
*old_fb
)
1166 struct drm_device
*dev
= crtc
->dev
;
1167 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1168 struct drm_i915_master_private
*master_priv
;
1169 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1170 struct intel_framebuffer
*intel_fb
;
1171 struct drm_i915_gem_object
*obj_priv
;
1172 struct drm_gem_object
*obj
;
1173 int pipe
= intel_crtc
->pipe
;
1174 int plane
= intel_crtc
->plane
;
1175 unsigned long Start
, Offset
;
1176 int dspbase
= (plane
== 0 ? DSPAADDR
: DSPBADDR
);
1177 int dspsurf
= (plane
== 0 ? DSPASURF
: DSPBSURF
);
1178 int dspstride
= (plane
== 0) ? DSPASTRIDE
: DSPBSTRIDE
;
1179 int dsptileoff
= (plane
== 0 ? DSPATILEOFF
: DSPBTILEOFF
);
1180 int dspcntr_reg
= (plane
== 0) ? DSPACNTR
: DSPBCNTR
;
1186 DRM_DEBUG_KMS("No FB bound\n");
1195 DRM_ERROR("Can't update plane %d in SAREA\n", plane
);
1199 intel_fb
= to_intel_framebuffer(crtc
->fb
);
1200 obj
= intel_fb
->obj
;
1201 obj_priv
= obj
->driver_private
;
1203 mutex_lock(&dev
->struct_mutex
);
1204 ret
= intel_pin_and_fence_fb_obj(dev
, obj
);
1206 mutex_unlock(&dev
->struct_mutex
);
1210 ret
= i915_gem_object_set_to_display_plane(obj
);
1212 i915_gem_object_unpin(obj
);
1213 mutex_unlock(&dev
->struct_mutex
);
1217 dspcntr
= I915_READ(dspcntr_reg
);
1218 /* Mask out pixel format bits in case we change it */
1219 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
1220 switch (crtc
->fb
->bits_per_pixel
) {
1222 dspcntr
|= DISPPLANE_8BPP
;
1225 if (crtc
->fb
->depth
== 15)
1226 dspcntr
|= DISPPLANE_15_16BPP
;
1228 dspcntr
|= DISPPLANE_16BPP
;
1232 if (crtc
->fb
->depth
== 30)
1233 dspcntr
|= DISPPLANE_32BPP_30BIT_NO_ALPHA
;
1235 dspcntr
|= DISPPLANE_32BPP_NO_ALPHA
;
1238 DRM_ERROR("Unknown color depth\n");
1239 i915_gem_object_unpin(obj
);
1240 mutex_unlock(&dev
->struct_mutex
);
1243 if (IS_I965G(dev
)) {
1244 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1245 dspcntr
|= DISPPLANE_TILED
;
1247 dspcntr
&= ~DISPPLANE_TILED
;
1250 if (IS_IRONLAKE(dev
))
1252 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
1254 I915_WRITE(dspcntr_reg
, dspcntr
);
1256 Start
= obj_priv
->gtt_offset
;
1257 Offset
= y
* crtc
->fb
->pitch
+ x
* (crtc
->fb
->bits_per_pixel
/ 8);
1259 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d\n", Start
, Offset
, x
, y
);
1260 I915_WRITE(dspstride
, crtc
->fb
->pitch
);
1261 if (IS_I965G(dev
)) {
1262 I915_WRITE(dspbase
, Offset
);
1264 I915_WRITE(dspsurf
, Start
);
1266 I915_WRITE(dsptileoff
, (y
<< 16) | x
);
1268 I915_WRITE(dspbase
, Start
+ Offset
);
1272 if ((IS_I965G(dev
) || plane
== 0))
1273 intel_update_fbc(crtc
, &crtc
->mode
);
1275 intel_wait_for_vblank(dev
);
1278 intel_fb
= to_intel_framebuffer(old_fb
);
1279 obj_priv
= intel_fb
->obj
->driver_private
;
1280 i915_gem_object_unpin(intel_fb
->obj
);
1282 intel_increase_pllclock(crtc
, true);
1284 mutex_unlock(&dev
->struct_mutex
);
1286 if (!dev
->primary
->master
)
1289 master_priv
= dev
->primary
->master
->driver_priv
;
1290 if (!master_priv
->sarea_priv
)
1294 master_priv
->sarea_priv
->pipeB_x
= x
;
1295 master_priv
->sarea_priv
->pipeB_y
= y
;
1297 master_priv
->sarea_priv
->pipeA_x
= x
;
1298 master_priv
->sarea_priv
->pipeA_y
= y
;
1304 /* Disable the VGA plane that we never use */
1305 static void i915_disable_vga (struct drm_device
*dev
)
1307 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1311 if (IS_IRONLAKE(dev
))
1312 vga_reg
= CPU_VGACNTRL
;
1316 if (I915_READ(vga_reg
) & VGA_DISP_DISABLE
)
1319 I915_WRITE8(VGA_SR_INDEX
, 1);
1320 sr1
= I915_READ8(VGA_SR_DATA
);
1321 I915_WRITE8(VGA_SR_DATA
, sr1
| (1 << 5));
1324 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
1327 static void ironlake_disable_pll_edp (struct drm_crtc
*crtc
)
1329 struct drm_device
*dev
= crtc
->dev
;
1330 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1333 DRM_DEBUG_KMS("\n");
1334 dpa_ctl
= I915_READ(DP_A
);
1335 dpa_ctl
&= ~DP_PLL_ENABLE
;
1336 I915_WRITE(DP_A
, dpa_ctl
);
1339 static void ironlake_enable_pll_edp (struct drm_crtc
*crtc
)
1341 struct drm_device
*dev
= crtc
->dev
;
1342 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1345 dpa_ctl
= I915_READ(DP_A
);
1346 dpa_ctl
|= DP_PLL_ENABLE
;
1347 I915_WRITE(DP_A
, dpa_ctl
);
1352 static void ironlake_set_pll_edp (struct drm_crtc
*crtc
, int clock
)
1354 struct drm_device
*dev
= crtc
->dev
;
1355 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1358 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock
);
1359 dpa_ctl
= I915_READ(DP_A
);
1360 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
1362 if (clock
< 200000) {
1364 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
1365 /* workaround for 160Mhz:
1366 1) program 0x4600c bits 15:0 = 0x8124
1367 2) program 0x46010 bit 0 = 1
1368 3) program 0x46034 bit 24 = 1
1369 4) program 0x64000 bit 14 = 1
1371 temp
= I915_READ(0x4600c);
1373 I915_WRITE(0x4600c, temp
| 0x8124);
1375 temp
= I915_READ(0x46010);
1376 I915_WRITE(0x46010, temp
| 1);
1378 temp
= I915_READ(0x46034);
1379 I915_WRITE(0x46034, temp
| (1 << 24));
1381 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
1383 I915_WRITE(DP_A
, dpa_ctl
);
1388 static void ironlake_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
1390 struct drm_device
*dev
= crtc
->dev
;
1391 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1392 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1393 int pipe
= intel_crtc
->pipe
;
1394 int plane
= intel_crtc
->plane
;
1395 int pch_dpll_reg
= (pipe
== 0) ? PCH_DPLL_A
: PCH_DPLL_B
;
1396 int pipeconf_reg
= (pipe
== 0) ? PIPEACONF
: PIPEBCONF
;
1397 int dspcntr_reg
= (plane
== 0) ? DSPACNTR
: DSPBCNTR
;
1398 int dspbase_reg
= (plane
== 0) ? DSPAADDR
: DSPBADDR
;
1399 int fdi_tx_reg
= (pipe
== 0) ? FDI_TXA_CTL
: FDI_TXB_CTL
;
1400 int fdi_rx_reg
= (pipe
== 0) ? FDI_RXA_CTL
: FDI_RXB_CTL
;
1401 int fdi_rx_iir_reg
= (pipe
== 0) ? FDI_RXA_IIR
: FDI_RXB_IIR
;
1402 int fdi_rx_imr_reg
= (pipe
== 0) ? FDI_RXA_IMR
: FDI_RXB_IMR
;
1403 int transconf_reg
= (pipe
== 0) ? TRANSACONF
: TRANSBCONF
;
1404 int pf_ctl_reg
= (pipe
== 0) ? PFA_CTL_1
: PFB_CTL_1
;
1405 int pf_win_size
= (pipe
== 0) ? PFA_WIN_SZ
: PFB_WIN_SZ
;
1406 int pf_win_pos
= (pipe
== 0) ? PFA_WIN_POS
: PFB_WIN_POS
;
1407 int cpu_htot_reg
= (pipe
== 0) ? HTOTAL_A
: HTOTAL_B
;
1408 int cpu_hblank_reg
= (pipe
== 0) ? HBLANK_A
: HBLANK_B
;
1409 int cpu_hsync_reg
= (pipe
== 0) ? HSYNC_A
: HSYNC_B
;
1410 int cpu_vtot_reg
= (pipe
== 0) ? VTOTAL_A
: VTOTAL_B
;
1411 int cpu_vblank_reg
= (pipe
== 0) ? VBLANK_A
: VBLANK_B
;
1412 int cpu_vsync_reg
= (pipe
== 0) ? VSYNC_A
: VSYNC_B
;
1413 int trans_htot_reg
= (pipe
== 0) ? TRANS_HTOTAL_A
: TRANS_HTOTAL_B
;
1414 int trans_hblank_reg
= (pipe
== 0) ? TRANS_HBLANK_A
: TRANS_HBLANK_B
;
1415 int trans_hsync_reg
= (pipe
== 0) ? TRANS_HSYNC_A
: TRANS_HSYNC_B
;
1416 int trans_vtot_reg
= (pipe
== 0) ? TRANS_VTOTAL_A
: TRANS_VTOTAL_B
;
1417 int trans_vblank_reg
= (pipe
== 0) ? TRANS_VBLANK_A
: TRANS_VBLANK_B
;
1418 int trans_vsync_reg
= (pipe
== 0) ? TRANS_VSYNC_A
: TRANS_VSYNC_B
;
1420 int tries
= 5, j
, n
;
1423 temp
= I915_READ(pipeconf_reg
);
1424 pipe_bpc
= temp
& PIPE_BPC_MASK
;
1426 /* XXX: When our outputs are all unaware of DPMS modes other than off
1427 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1430 case DRM_MODE_DPMS_ON
:
1431 case DRM_MODE_DPMS_STANDBY
:
1432 case DRM_MODE_DPMS_SUSPEND
:
1433 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe
);
1435 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
1436 temp
= I915_READ(PCH_LVDS
);
1437 if ((temp
& LVDS_PORT_EN
) == 0) {
1438 I915_WRITE(PCH_LVDS
, temp
| LVDS_PORT_EN
);
1439 POSTING_READ(PCH_LVDS
);
1444 /* enable eDP PLL */
1445 ironlake_enable_pll_edp(crtc
);
1447 /* enable PCH DPLL */
1448 temp
= I915_READ(pch_dpll_reg
);
1449 if ((temp
& DPLL_VCO_ENABLE
) == 0) {
1450 I915_WRITE(pch_dpll_reg
, temp
| DPLL_VCO_ENABLE
);
1451 I915_READ(pch_dpll_reg
);
1454 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1455 temp
= I915_READ(fdi_rx_reg
);
1457 * make the BPC in FDI Rx be consistent with that in
1460 temp
&= ~(0x7 << 16);
1461 temp
|= (pipe_bpc
<< 11);
1462 I915_WRITE(fdi_rx_reg
, temp
| FDI_RX_PLL_ENABLE
|
1464 FDI_DP_PORT_WIDTH_X4
); /* default 4 lanes */
1465 I915_READ(fdi_rx_reg
);
1468 /* Enable CPU FDI TX PLL, always on for Ironlake */
1469 temp
= I915_READ(fdi_tx_reg
);
1470 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
1471 I915_WRITE(fdi_tx_reg
, temp
| FDI_TX_PLL_ENABLE
);
1472 I915_READ(fdi_tx_reg
);
1477 /* Enable panel fitting for LVDS */
1478 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
1479 temp
= I915_READ(pf_ctl_reg
);
1480 I915_WRITE(pf_ctl_reg
, temp
| PF_ENABLE
| PF_FILTER_MED_3x3
);
1482 /* currently full aspect */
1483 I915_WRITE(pf_win_pos
, 0);
1485 I915_WRITE(pf_win_size
,
1486 (dev_priv
->panel_fixed_mode
->hdisplay
<< 16) |
1487 (dev_priv
->panel_fixed_mode
->vdisplay
));
1490 /* Enable CPU pipe */
1491 temp
= I915_READ(pipeconf_reg
);
1492 if ((temp
& PIPEACONF_ENABLE
) == 0) {
1493 I915_WRITE(pipeconf_reg
, temp
| PIPEACONF_ENABLE
);
1494 I915_READ(pipeconf_reg
);
1498 /* configure and enable CPU plane */
1499 temp
= I915_READ(dspcntr_reg
);
1500 if ((temp
& DISPLAY_PLANE_ENABLE
) == 0) {
1501 I915_WRITE(dspcntr_reg
, temp
| DISPLAY_PLANE_ENABLE
);
1502 /* Flush the plane changes */
1503 I915_WRITE(dspbase_reg
, I915_READ(dspbase_reg
));
1507 /* enable CPU FDI TX and PCH FDI RX */
1508 temp
= I915_READ(fdi_tx_reg
);
1509 temp
|= FDI_TX_ENABLE
;
1510 temp
|= FDI_DP_PORT_WIDTH_X4
; /* default */
1511 temp
&= ~FDI_LINK_TRAIN_NONE
;
1512 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
1513 I915_WRITE(fdi_tx_reg
, temp
);
1514 I915_READ(fdi_tx_reg
);
1516 temp
= I915_READ(fdi_rx_reg
);
1517 temp
&= ~FDI_LINK_TRAIN_NONE
;
1518 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
1519 I915_WRITE(fdi_rx_reg
, temp
| FDI_RX_ENABLE
);
1520 I915_READ(fdi_rx_reg
);
1525 /* umask FDI RX Interrupt symbol_lock and bit_lock bit
1527 temp
= I915_READ(fdi_rx_imr_reg
);
1528 temp
&= ~FDI_RX_SYMBOL_LOCK
;
1529 temp
&= ~FDI_RX_BIT_LOCK
;
1530 I915_WRITE(fdi_rx_imr_reg
, temp
);
1531 I915_READ(fdi_rx_imr_reg
);
1534 temp
= I915_READ(fdi_rx_iir_reg
);
1535 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
1537 if ((temp
& FDI_RX_BIT_LOCK
) == 0) {
1538 for (j
= 0; j
< tries
; j
++) {
1539 temp
= I915_READ(fdi_rx_iir_reg
);
1540 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
1542 if (temp
& FDI_RX_BIT_LOCK
)
1547 I915_WRITE(fdi_rx_iir_reg
,
1548 temp
| FDI_RX_BIT_LOCK
);
1550 DRM_DEBUG_KMS("train 1 fail\n");
1552 I915_WRITE(fdi_rx_iir_reg
,
1553 temp
| FDI_RX_BIT_LOCK
);
1554 DRM_DEBUG_KMS("train 1 ok 2!\n");
1556 temp
= I915_READ(fdi_tx_reg
);
1557 temp
&= ~FDI_LINK_TRAIN_NONE
;
1558 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
1559 I915_WRITE(fdi_tx_reg
, temp
);
1561 temp
= I915_READ(fdi_rx_reg
);
1562 temp
&= ~FDI_LINK_TRAIN_NONE
;
1563 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
1564 I915_WRITE(fdi_rx_reg
, temp
);
1568 temp
= I915_READ(fdi_rx_iir_reg
);
1569 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
1571 if ((temp
& FDI_RX_SYMBOL_LOCK
) == 0) {
1572 for (j
= 0; j
< tries
; j
++) {
1573 temp
= I915_READ(fdi_rx_iir_reg
);
1574 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
1576 if (temp
& FDI_RX_SYMBOL_LOCK
)
1581 I915_WRITE(fdi_rx_iir_reg
,
1582 temp
| FDI_RX_SYMBOL_LOCK
);
1583 DRM_DEBUG_KMS("train 2 ok 1!\n");
1585 DRM_DEBUG_KMS("train 2 fail\n");
1587 I915_WRITE(fdi_rx_iir_reg
,
1588 temp
| FDI_RX_SYMBOL_LOCK
);
1589 DRM_DEBUG_KMS("train 2 ok 2!\n");
1591 DRM_DEBUG_KMS("train done\n");
1593 /* set transcoder timing */
1594 I915_WRITE(trans_htot_reg
, I915_READ(cpu_htot_reg
));
1595 I915_WRITE(trans_hblank_reg
, I915_READ(cpu_hblank_reg
));
1596 I915_WRITE(trans_hsync_reg
, I915_READ(cpu_hsync_reg
));
1598 I915_WRITE(trans_vtot_reg
, I915_READ(cpu_vtot_reg
));
1599 I915_WRITE(trans_vblank_reg
, I915_READ(cpu_vblank_reg
));
1600 I915_WRITE(trans_vsync_reg
, I915_READ(cpu_vsync_reg
));
1602 /* enable PCH transcoder */
1603 temp
= I915_READ(transconf_reg
);
1605 * make the BPC in transcoder be consistent with
1606 * that in pipeconf reg.
1608 temp
&= ~PIPE_BPC_MASK
;
1610 I915_WRITE(transconf_reg
, temp
| TRANS_ENABLE
);
1611 I915_READ(transconf_reg
);
1613 while ((I915_READ(transconf_reg
) & TRANS_STATE_ENABLE
) == 0)
1618 temp
= I915_READ(fdi_tx_reg
);
1619 temp
&= ~FDI_LINK_TRAIN_NONE
;
1620 I915_WRITE(fdi_tx_reg
, temp
| FDI_LINK_TRAIN_NONE
|
1621 FDI_TX_ENHANCE_FRAME_ENABLE
);
1622 I915_READ(fdi_tx_reg
);
1624 temp
= I915_READ(fdi_rx_reg
);
1625 temp
&= ~FDI_LINK_TRAIN_NONE
;
1626 I915_WRITE(fdi_rx_reg
, temp
| FDI_LINK_TRAIN_NONE
|
1627 FDI_RX_ENHANCE_FRAME_ENABLE
);
1628 I915_READ(fdi_rx_reg
);
1630 /* wait one idle pattern time */
1635 intel_crtc_load_lut(crtc
);
1638 case DRM_MODE_DPMS_OFF
:
1639 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe
);
1641 drm_vblank_off(dev
, pipe
);
1642 /* Disable display plane */
1643 temp
= I915_READ(dspcntr_reg
);
1644 if ((temp
& DISPLAY_PLANE_ENABLE
) != 0) {
1645 I915_WRITE(dspcntr_reg
, temp
& ~DISPLAY_PLANE_ENABLE
);
1646 /* Flush the plane changes */
1647 I915_WRITE(dspbase_reg
, I915_READ(dspbase_reg
));
1648 I915_READ(dspbase_reg
);
1651 i915_disable_vga(dev
);
1653 /* disable cpu pipe, disable after all planes disabled */
1654 temp
= I915_READ(pipeconf_reg
);
1655 if ((temp
& PIPEACONF_ENABLE
) != 0) {
1656 I915_WRITE(pipeconf_reg
, temp
& ~PIPEACONF_ENABLE
);
1657 I915_READ(pipeconf_reg
);
1659 /* wait for cpu pipe off, pipe state */
1660 while ((I915_READ(pipeconf_reg
) & I965_PIPECONF_ACTIVE
) != 0) {
1666 DRM_DEBUG_KMS("pipe %d off delay\n",
1672 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe
);
1677 temp
= I915_READ(pf_ctl_reg
);
1678 if ((temp
& PF_ENABLE
) != 0) {
1679 I915_WRITE(pf_ctl_reg
, temp
& ~PF_ENABLE
);
1680 I915_READ(pf_ctl_reg
);
1682 I915_WRITE(pf_win_size
, 0);
1684 /* disable CPU FDI tx and PCH FDI rx */
1685 temp
= I915_READ(fdi_tx_reg
);
1686 I915_WRITE(fdi_tx_reg
, temp
& ~FDI_TX_ENABLE
);
1687 I915_READ(fdi_tx_reg
);
1689 temp
= I915_READ(fdi_rx_reg
);
1690 /* BPC in FDI rx is consistent with that in pipeconf */
1691 temp
&= ~(0x07 << 16);
1692 temp
|= (pipe_bpc
<< 11);
1693 I915_WRITE(fdi_rx_reg
, temp
& ~FDI_RX_ENABLE
);
1694 I915_READ(fdi_rx_reg
);
1698 /* still set train pattern 1 */
1699 temp
= I915_READ(fdi_tx_reg
);
1700 temp
&= ~FDI_LINK_TRAIN_NONE
;
1701 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
1702 I915_WRITE(fdi_tx_reg
, temp
);
1704 temp
= I915_READ(fdi_rx_reg
);
1705 temp
&= ~FDI_LINK_TRAIN_NONE
;
1706 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
1707 I915_WRITE(fdi_rx_reg
, temp
);
1711 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
1712 temp
= I915_READ(PCH_LVDS
);
1713 I915_WRITE(PCH_LVDS
, temp
& ~LVDS_PORT_EN
);
1714 I915_READ(PCH_LVDS
);
1718 /* disable PCH transcoder */
1719 temp
= I915_READ(transconf_reg
);
1720 if ((temp
& TRANS_ENABLE
) != 0) {
1721 I915_WRITE(transconf_reg
, temp
& ~TRANS_ENABLE
);
1722 I915_READ(transconf_reg
);
1724 /* wait for PCH transcoder off, transcoder state */
1725 while ((I915_READ(transconf_reg
) & TRANS_STATE_ENABLE
) != 0) {
1731 DRM_DEBUG_KMS("transcoder %d off "
1737 temp
= I915_READ(transconf_reg
);
1738 /* BPC in transcoder is consistent with that in pipeconf */
1739 temp
&= ~PIPE_BPC_MASK
;
1741 I915_WRITE(transconf_reg
, temp
);
1742 I915_READ(transconf_reg
);
1745 /* disable PCH DPLL */
1746 temp
= I915_READ(pch_dpll_reg
);
1747 if ((temp
& DPLL_VCO_ENABLE
) != 0) {
1748 I915_WRITE(pch_dpll_reg
, temp
& ~DPLL_VCO_ENABLE
);
1749 I915_READ(pch_dpll_reg
);
1753 ironlake_disable_pll_edp(crtc
);
1756 temp
= I915_READ(fdi_rx_reg
);
1757 temp
&= ~FDI_SEL_PCDCLK
;
1758 I915_WRITE(fdi_rx_reg
, temp
);
1759 I915_READ(fdi_rx_reg
);
1761 temp
= I915_READ(fdi_rx_reg
);
1762 temp
&= ~FDI_RX_PLL_ENABLE
;
1763 I915_WRITE(fdi_rx_reg
, temp
);
1764 I915_READ(fdi_rx_reg
);
1766 /* Disable CPU FDI TX PLL */
1767 temp
= I915_READ(fdi_tx_reg
);
1768 if ((temp
& FDI_TX_PLL_ENABLE
) != 0) {
1769 I915_WRITE(fdi_tx_reg
, temp
& ~FDI_TX_PLL_ENABLE
);
1770 I915_READ(fdi_tx_reg
);
1774 /* Wait for the clocks to turn off. */
1780 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
1782 struct intel_overlay
*overlay
;
1785 if (!enable
&& intel_crtc
->overlay
) {
1786 overlay
= intel_crtc
->overlay
;
1787 mutex_lock(&overlay
->dev
->struct_mutex
);
1789 ret
= intel_overlay_switch_off(overlay
);
1793 ret
= intel_overlay_recover_from_interrupt(overlay
, 0);
1795 /* overlay doesn't react anymore. Usually
1796 * results in a black screen and an unkillable
1799 overlay
->hw_wedged
= HW_WEDGED
;
1803 mutex_unlock(&overlay
->dev
->struct_mutex
);
1805 /* Let userspace switch the overlay on again. In most cases userspace
1806 * has to recompute where to put it anyway. */
1811 static void i9xx_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
1813 struct drm_device
*dev
= crtc
->dev
;
1814 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1815 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1816 int pipe
= intel_crtc
->pipe
;
1817 int plane
= intel_crtc
->plane
;
1818 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
1819 int dspcntr_reg
= (plane
== 0) ? DSPACNTR
: DSPBCNTR
;
1820 int dspbase_reg
= (plane
== 0) ? DSPAADDR
: DSPBADDR
;
1821 int pipeconf_reg
= (pipe
== 0) ? PIPEACONF
: PIPEBCONF
;
1824 /* XXX: When our outputs are all unaware of DPMS modes other than off
1825 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1828 case DRM_MODE_DPMS_ON
:
1829 case DRM_MODE_DPMS_STANDBY
:
1830 case DRM_MODE_DPMS_SUSPEND
:
1831 intel_update_watermarks(dev
);
1833 /* Enable the DPLL */
1834 temp
= I915_READ(dpll_reg
);
1835 if ((temp
& DPLL_VCO_ENABLE
) == 0) {
1836 I915_WRITE(dpll_reg
, temp
);
1837 I915_READ(dpll_reg
);
1838 /* Wait for the clocks to stabilize. */
1840 I915_WRITE(dpll_reg
, temp
| DPLL_VCO_ENABLE
);
1841 I915_READ(dpll_reg
);
1842 /* Wait for the clocks to stabilize. */
1844 I915_WRITE(dpll_reg
, temp
| DPLL_VCO_ENABLE
);
1845 I915_READ(dpll_reg
);
1846 /* Wait for the clocks to stabilize. */
1850 /* Enable the pipe */
1851 temp
= I915_READ(pipeconf_reg
);
1852 if ((temp
& PIPEACONF_ENABLE
) == 0)
1853 I915_WRITE(pipeconf_reg
, temp
| PIPEACONF_ENABLE
);
1855 /* Enable the plane */
1856 temp
= I915_READ(dspcntr_reg
);
1857 if ((temp
& DISPLAY_PLANE_ENABLE
) == 0) {
1858 I915_WRITE(dspcntr_reg
, temp
| DISPLAY_PLANE_ENABLE
);
1859 /* Flush the plane changes */
1860 I915_WRITE(dspbase_reg
, I915_READ(dspbase_reg
));
1863 intel_crtc_load_lut(crtc
);
1865 if ((IS_I965G(dev
) || plane
== 0))
1866 intel_update_fbc(crtc
, &crtc
->mode
);
1868 /* Give the overlay scaler a chance to enable if it's on this pipe */
1869 intel_crtc_dpms_overlay(intel_crtc
, true);
1871 case DRM_MODE_DPMS_OFF
:
1872 intel_update_watermarks(dev
);
1874 /* Give the overlay scaler a chance to disable if it's on this pipe */
1875 intel_crtc_dpms_overlay(intel_crtc
, false);
1876 drm_vblank_off(dev
, pipe
);
1878 if (dev_priv
->cfb_plane
== plane
&&
1879 dev_priv
->display
.disable_fbc
)
1880 dev_priv
->display
.disable_fbc(dev
);
1882 /* Disable the VGA plane that we never use */
1883 i915_disable_vga(dev
);
1885 /* Disable display plane */
1886 temp
= I915_READ(dspcntr_reg
);
1887 if ((temp
& DISPLAY_PLANE_ENABLE
) != 0) {
1888 I915_WRITE(dspcntr_reg
, temp
& ~DISPLAY_PLANE_ENABLE
);
1889 /* Flush the plane changes */
1890 I915_WRITE(dspbase_reg
, I915_READ(dspbase_reg
));
1891 I915_READ(dspbase_reg
);
1894 if (!IS_I9XX(dev
)) {
1895 /* Wait for vblank for the disable to take effect */
1896 intel_wait_for_vblank(dev
);
1899 /* Next, disable display pipes */
1900 temp
= I915_READ(pipeconf_reg
);
1901 if ((temp
& PIPEACONF_ENABLE
) != 0) {
1902 I915_WRITE(pipeconf_reg
, temp
& ~PIPEACONF_ENABLE
);
1903 I915_READ(pipeconf_reg
);
1906 /* Wait for vblank for the disable to take effect. */
1907 intel_wait_for_vblank(dev
);
1909 temp
= I915_READ(dpll_reg
);
1910 if ((temp
& DPLL_VCO_ENABLE
) != 0) {
1911 I915_WRITE(dpll_reg
, temp
& ~DPLL_VCO_ENABLE
);
1912 I915_READ(dpll_reg
);
1915 /* Wait for the clocks to turn off. */
1922 * Sets the power management mode of the pipe and plane.
1924 * This code should probably grow support for turning the cursor off and back
1925 * on appropriately at the same time as we're turning the pipe off/on.
1927 static void intel_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
1929 struct drm_device
*dev
= crtc
->dev
;
1930 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1931 struct drm_i915_master_private
*master_priv
;
1932 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1933 int pipe
= intel_crtc
->pipe
;
1936 dev_priv
->display
.dpms(crtc
, mode
);
1938 intel_crtc
->dpms_mode
= mode
;
1940 if (!dev
->primary
->master
)
1943 master_priv
= dev
->primary
->master
->driver_priv
;
1944 if (!master_priv
->sarea_priv
)
1947 enabled
= crtc
->enabled
&& mode
!= DRM_MODE_DPMS_OFF
;
1951 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
1952 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
1955 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
1956 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
1959 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe
);
1964 static void intel_crtc_prepare (struct drm_crtc
*crtc
)
1966 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
1967 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_OFF
);
1970 static void intel_crtc_commit (struct drm_crtc
*crtc
)
1972 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
1973 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
1976 void intel_encoder_prepare (struct drm_encoder
*encoder
)
1978 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
1979 /* lvds has its own version of prepare see intel_lvds_prepare */
1980 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_OFF
);
1983 void intel_encoder_commit (struct drm_encoder
*encoder
)
1985 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
1986 /* lvds has its own version of commit see intel_lvds_commit */
1987 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
1990 static bool intel_crtc_mode_fixup(struct drm_crtc
*crtc
,
1991 struct drm_display_mode
*mode
,
1992 struct drm_display_mode
*adjusted_mode
)
1994 struct drm_device
*dev
= crtc
->dev
;
1995 if (IS_IRONLAKE(dev
)) {
1996 /* FDI link clock is fixed at 2.7G */
1997 if (mode
->clock
* 3 > 27000 * 4)
1998 return MODE_CLOCK_HIGH
;
2003 static int i945_get_display_clock_speed(struct drm_device
*dev
)
2008 static int i915_get_display_clock_speed(struct drm_device
*dev
)
2013 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
2018 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
2022 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
2024 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
2027 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
2028 case GC_DISPLAY_CLOCK_333_MHZ
:
2031 case GC_DISPLAY_CLOCK_190_200_MHZ
:
2037 static int i865_get_display_clock_speed(struct drm_device
*dev
)
2042 static int i855_get_display_clock_speed(struct drm_device
*dev
)
2045 /* Assume that the hardware is in the high speed state. This
2046 * should be the default.
2048 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
2049 case GC_CLOCK_133_200
:
2050 case GC_CLOCK_100_200
:
2052 case GC_CLOCK_166_250
:
2054 case GC_CLOCK_100_133
:
2058 /* Shouldn't happen */
2062 static int i830_get_display_clock_speed(struct drm_device
*dev
)
2068 * Return the pipe currently connected to the panel fitter,
2069 * or -1 if the panel fitter is not present or not in use
2071 int intel_panel_fitter_pipe (struct drm_device
*dev
)
2073 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2076 /* i830 doesn't have a panel fitter */
2080 pfit_control
= I915_READ(PFIT_CONTROL
);
2082 /* See if the panel fitter is in use */
2083 if ((pfit_control
& PFIT_ENABLE
) == 0)
2086 /* 965 can place panel fitter on either pipe */
2088 return (pfit_control
>> 29) & 0x3;
2090 /* older chips can only use pipe 1 */
2103 fdi_reduce_ratio(u32
*num
, u32
*den
)
2105 while (*num
> 0xffffff || *den
> 0xffffff) {
2111 #define DATA_N 0x800000
2112 #define LINK_N 0x80000
2115 ironlake_compute_m_n(int bits_per_pixel
, int nlanes
, int pixel_clock
,
2116 int link_clock
, struct fdi_m_n
*m_n
)
2120 m_n
->tu
= 64; /* default size */
2122 temp
= (u64
) DATA_N
* pixel_clock
;
2123 temp
= div_u64(temp
, link_clock
);
2124 m_n
->gmch_m
= div_u64(temp
* bits_per_pixel
, nlanes
);
2125 m_n
->gmch_m
>>= 3; /* convert to bytes_per_pixel */
2126 m_n
->gmch_n
= DATA_N
;
2127 fdi_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
2129 temp
= (u64
) LINK_N
* pixel_clock
;
2130 m_n
->link_m
= div_u64(temp
, link_clock
);
2131 m_n
->link_n
= LINK_N
;
2132 fdi_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
2136 struct intel_watermark_params
{
2137 unsigned long fifo_size
;
2138 unsigned long max_wm
;
2139 unsigned long default_wm
;
2140 unsigned long guard_size
;
2141 unsigned long cacheline_size
;
2144 /* Pineview has different values for various configs */
2145 static struct intel_watermark_params pineview_display_wm
= {
2146 PINEVIEW_DISPLAY_FIFO
,
2150 PINEVIEW_FIFO_LINE_SIZE
2152 static struct intel_watermark_params pineview_display_hplloff_wm
= {
2153 PINEVIEW_DISPLAY_FIFO
,
2155 PINEVIEW_DFT_HPLLOFF_WM
,
2157 PINEVIEW_FIFO_LINE_SIZE
2159 static struct intel_watermark_params pineview_cursor_wm
= {
2160 PINEVIEW_CURSOR_FIFO
,
2161 PINEVIEW_CURSOR_MAX_WM
,
2162 PINEVIEW_CURSOR_DFT_WM
,
2163 PINEVIEW_CURSOR_GUARD_WM
,
2164 PINEVIEW_FIFO_LINE_SIZE
,
2166 static struct intel_watermark_params pineview_cursor_hplloff_wm
= {
2167 PINEVIEW_CURSOR_FIFO
,
2168 PINEVIEW_CURSOR_MAX_WM
,
2169 PINEVIEW_CURSOR_DFT_WM
,
2170 PINEVIEW_CURSOR_GUARD_WM
,
2171 PINEVIEW_FIFO_LINE_SIZE
2173 static struct intel_watermark_params g4x_wm_info
= {
2180 static struct intel_watermark_params i945_wm_info
= {
2187 static struct intel_watermark_params i915_wm_info
= {
2194 static struct intel_watermark_params i855_wm_info
= {
2201 static struct intel_watermark_params i830_wm_info
= {
2210 * intel_calculate_wm - calculate watermark level
2211 * @clock_in_khz: pixel clock
2212 * @wm: chip FIFO params
2213 * @pixel_size: display pixel size
2214 * @latency_ns: memory latency for the platform
2216 * Calculate the watermark level (the level at which the display plane will
2217 * start fetching from memory again). Each chip has a different display
2218 * FIFO size and allocation, so the caller needs to figure that out and pass
2219 * in the correct intel_watermark_params structure.
2221 * As the pixel clock runs, the FIFO will be drained at a rate that depends
2222 * on the pixel size. When it reaches the watermark level, it'll start
2223 * fetching FIFO line sized based chunks from memory until the FIFO fills
2224 * past the watermark point. If the FIFO drains completely, a FIFO underrun
2225 * will occur, and a display engine hang could result.
2227 static unsigned long intel_calculate_wm(unsigned long clock_in_khz
,
2228 struct intel_watermark_params
*wm
,
2230 unsigned long latency_ns
)
2232 long entries_required
, wm_size
;
2235 * Note: we need to make sure we don't overflow for various clock &
2237 * clocks go from a few thousand to several hundred thousand.
2238 * latency is usually a few thousand
2240 entries_required
= ((clock_in_khz
/ 1000) * pixel_size
* latency_ns
) /
2242 entries_required
/= wm
->cacheline_size
;
2244 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required
);
2246 wm_size
= wm
->fifo_size
- (entries_required
+ wm
->guard_size
);
2248 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size
);
2250 /* Don't promote wm_size to unsigned... */
2251 if (wm_size
> (long)wm
->max_wm
)
2252 wm_size
= wm
->max_wm
;
2254 wm_size
= wm
->default_wm
;
2258 struct cxsr_latency
{
2260 unsigned long fsb_freq
;
2261 unsigned long mem_freq
;
2262 unsigned long display_sr
;
2263 unsigned long display_hpll_disable
;
2264 unsigned long cursor_sr
;
2265 unsigned long cursor_hpll_disable
;
2268 static struct cxsr_latency cxsr_latency_table
[] = {
2269 {1, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
2270 {1, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
2271 {1, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
2273 {1, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
2274 {1, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
2275 {1, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
2277 {1, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
2278 {1, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
2279 {1, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
2281 {0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
2282 {0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
2283 {0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
2285 {0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
2286 {0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
2287 {0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
2289 {0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
2290 {0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
2291 {0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
2294 static struct cxsr_latency
*intel_get_cxsr_latency(int is_desktop
, int fsb
,
2298 struct cxsr_latency
*latency
;
2300 if (fsb
== 0 || mem
== 0)
2303 for (i
= 0; i
< ARRAY_SIZE(cxsr_latency_table
); i
++) {
2304 latency
= &cxsr_latency_table
[i
];
2305 if (is_desktop
== latency
->is_desktop
&&
2306 fsb
== latency
->fsb_freq
&& mem
== latency
->mem_freq
)
2310 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2315 static void pineview_disable_cxsr(struct drm_device
*dev
)
2317 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2320 /* deactivate cxsr */
2321 reg
= I915_READ(DSPFW3
);
2322 reg
&= ~(PINEVIEW_SELF_REFRESH_EN
);
2323 I915_WRITE(DSPFW3
, reg
);
2324 DRM_INFO("Big FIFO is disabled\n");
2327 static void pineview_enable_cxsr(struct drm_device
*dev
, unsigned long clock
,
2330 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2333 struct cxsr_latency
*latency
;
2335 latency
= intel_get_cxsr_latency(IS_PINEVIEW_G(dev
), dev_priv
->fsb_freq
,
2336 dev_priv
->mem_freq
);
2338 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2339 pineview_disable_cxsr(dev
);
2344 wm
= intel_calculate_wm(clock
, &pineview_display_wm
, pixel_size
,
2345 latency
->display_sr
);
2346 reg
= I915_READ(DSPFW1
);
2349 I915_WRITE(DSPFW1
, reg
);
2350 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg
);
2353 wm
= intel_calculate_wm(clock
, &pineview_cursor_wm
, pixel_size
,
2354 latency
->cursor_sr
);
2355 reg
= I915_READ(DSPFW3
);
2356 reg
&= ~(0x3f << 24);
2357 reg
|= (wm
& 0x3f) << 24;
2358 I915_WRITE(DSPFW3
, reg
);
2360 /* Display HPLL off SR */
2361 wm
= intel_calculate_wm(clock
, &pineview_display_hplloff_wm
,
2362 latency
->display_hpll_disable
, I915_FIFO_LINE_SIZE
);
2363 reg
= I915_READ(DSPFW3
);
2366 I915_WRITE(DSPFW3
, reg
);
2368 /* cursor HPLL off SR */
2369 wm
= intel_calculate_wm(clock
, &pineview_cursor_hplloff_wm
, pixel_size
,
2370 latency
->cursor_hpll_disable
);
2371 reg
= I915_READ(DSPFW3
);
2372 reg
&= ~(0x3f << 16);
2373 reg
|= (wm
& 0x3f) << 16;
2374 I915_WRITE(DSPFW3
, reg
);
2375 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg
);
2378 reg
= I915_READ(DSPFW3
);
2379 reg
|= PINEVIEW_SELF_REFRESH_EN
;
2380 I915_WRITE(DSPFW3
, reg
);
2382 DRM_INFO("Big FIFO is enabled\n");
2388 * Latency for FIFO fetches is dependent on several factors:
2389 * - memory configuration (speed, channels)
2391 * - current MCH state
2392 * It can be fairly high in some situations, so here we assume a fairly
2393 * pessimal value. It's a tradeoff between extra memory fetches (if we
2394 * set this value too high, the FIFO will fetch frequently to stay full)
2395 * and power consumption (set it too low to save power and we might see
2396 * FIFO underruns and display "flicker").
2398 * A value of 5us seems to be a good balance; safe for very low end
2399 * platforms but not overly aggressive on lower latency configs.
2401 static const int latency_ns
= 5000;
2403 static int i9xx_get_fifo_size(struct drm_device
*dev
, int plane
)
2405 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2406 uint32_t dsparb
= I915_READ(DSPARB
);
2410 size
= dsparb
& 0x7f;
2412 size
= ((dsparb
>> DSPARB_CSTART_SHIFT
) & 0x7f) -
2415 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
2416 plane
? "B" : "A", size
);
2421 static int i85x_get_fifo_size(struct drm_device
*dev
, int plane
)
2423 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2424 uint32_t dsparb
= I915_READ(DSPARB
);
2428 size
= dsparb
& 0x1ff;
2430 size
= ((dsparb
>> DSPARB_BEND_SHIFT
) & 0x1ff) -
2432 size
>>= 1; /* Convert to cachelines */
2434 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
2435 plane
? "B" : "A", size
);
2440 static int i845_get_fifo_size(struct drm_device
*dev
, int plane
)
2442 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2443 uint32_t dsparb
= I915_READ(DSPARB
);
2446 size
= dsparb
& 0x7f;
2447 size
>>= 2; /* Convert to cachelines */
2449 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
2456 static int i830_get_fifo_size(struct drm_device
*dev
, int plane
)
2458 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2459 uint32_t dsparb
= I915_READ(DSPARB
);
2462 size
= dsparb
& 0x7f;
2463 size
>>= 1; /* Convert to cachelines */
2465 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
2466 plane
? "B" : "A", size
);
2471 static void g4x_update_wm(struct drm_device
*dev
, int planea_clock
,
2472 int planeb_clock
, int sr_hdisplay
, int pixel_size
)
2474 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2475 int total_size
, cacheline_size
;
2476 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
, cursor_sr
;
2477 struct intel_watermark_params planea_params
, planeb_params
;
2478 unsigned long line_time_us
;
2479 int sr_clock
, sr_entries
= 0, entries_required
;
2481 /* Create copies of the base settings for each pipe */
2482 planea_params
= planeb_params
= g4x_wm_info
;
2484 /* Grab a couple of global values before we overwrite them */
2485 total_size
= planea_params
.fifo_size
;
2486 cacheline_size
= planea_params
.cacheline_size
;
2489 * Note: we need to make sure we don't overflow for various clock &
2491 * clocks go from a few thousand to several hundred thousand.
2492 * latency is usually a few thousand
2494 entries_required
= ((planea_clock
/ 1000) * pixel_size
* latency_ns
) /
2496 entries_required
/= G4X_FIFO_LINE_SIZE
;
2497 planea_wm
= entries_required
+ planea_params
.guard_size
;
2499 entries_required
= ((planeb_clock
/ 1000) * pixel_size
* latency_ns
) /
2501 entries_required
/= G4X_FIFO_LINE_SIZE
;
2502 planeb_wm
= entries_required
+ planeb_params
.guard_size
;
2504 cursora_wm
= cursorb_wm
= 16;
2507 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
2509 /* Calc sr entries for one plane configs */
2510 if (sr_hdisplay
&& (!planea_clock
|| !planeb_clock
)) {
2511 /* self-refresh has much higher latency */
2512 static const int sr_latency_ns
= 12000;
2514 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
2515 line_time_us
= ((sr_hdisplay
* 1000) / sr_clock
);
2517 /* Use ns/us then divide to preserve precision */
2518 sr_entries
= (((sr_latency_ns
/ line_time_us
) + 1) *
2519 pixel_size
* sr_hdisplay
) / 1000;
2520 sr_entries
= roundup(sr_entries
/ cacheline_size
, 1);
2521 DRM_DEBUG("self-refresh entries: %d\n", sr_entries
);
2522 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN
);
2524 /* Turn off self refresh if both pipes are enabled */
2525 I915_WRITE(FW_BLC_SELF
, I915_READ(FW_BLC_SELF
)
2529 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
2530 planea_wm
, planeb_wm
, sr_entries
);
2535 I915_WRITE(DSPFW1
, (sr_entries
<< DSPFW_SR_SHIFT
) |
2536 (cursorb_wm
<< DSPFW_CURSORB_SHIFT
) |
2537 (planeb_wm
<< DSPFW_PLANEB_SHIFT
) | planea_wm
);
2538 I915_WRITE(DSPFW2
, (I915_READ(DSPFW2
) & DSPFW_CURSORA_MASK
) |
2539 (cursora_wm
<< DSPFW_CURSORA_SHIFT
));
2540 /* HPLL off in SR has some issues on G4x... disable it */
2541 I915_WRITE(DSPFW3
, (I915_READ(DSPFW3
) & ~DSPFW_HPLL_SR_EN
) |
2542 (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
2545 static void i965_update_wm(struct drm_device
*dev
, int planea_clock
,
2546 int planeb_clock
, int sr_hdisplay
, int pixel_size
)
2548 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2549 unsigned long line_time_us
;
2550 int sr_clock
, sr_entries
, srwm
= 1;
2552 /* Calc sr entries for one plane configs */
2553 if (sr_hdisplay
&& (!planea_clock
|| !planeb_clock
)) {
2554 /* self-refresh has much higher latency */
2555 static const int sr_latency_ns
= 12000;
2557 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
2558 line_time_us
= ((sr_hdisplay
* 1000) / sr_clock
);
2560 /* Use ns/us then divide to preserve precision */
2561 sr_entries
= (((sr_latency_ns
/ line_time_us
) + 1) *
2562 pixel_size
* sr_hdisplay
) / 1000;
2563 sr_entries
= roundup(sr_entries
/ I915_FIFO_LINE_SIZE
, 1);
2564 DRM_DEBUG("self-refresh entries: %d\n", sr_entries
);
2565 srwm
= I945_FIFO_SIZE
- sr_entries
;
2569 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN
);
2571 /* Turn off self refresh if both pipes are enabled */
2572 I915_WRITE(FW_BLC_SELF
, I915_READ(FW_BLC_SELF
)
2576 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2579 /* 965 has limitations... */
2580 I915_WRITE(DSPFW1
, (srwm
<< DSPFW_SR_SHIFT
) | (8 << 16) | (8 << 8) |
2582 I915_WRITE(DSPFW2
, (8 << 8) | (8 << 0));
2585 static void i9xx_update_wm(struct drm_device
*dev
, int planea_clock
,
2586 int planeb_clock
, int sr_hdisplay
, int pixel_size
)
2588 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2591 int total_size
, cacheline_size
, cwm
, srwm
= 1;
2592 int planea_wm
, planeb_wm
;
2593 struct intel_watermark_params planea_params
, planeb_params
;
2594 unsigned long line_time_us
;
2595 int sr_clock
, sr_entries
= 0;
2597 /* Create copies of the base settings for each pipe */
2598 if (IS_I965GM(dev
) || IS_I945GM(dev
))
2599 planea_params
= planeb_params
= i945_wm_info
;
2600 else if (IS_I9XX(dev
))
2601 planea_params
= planeb_params
= i915_wm_info
;
2603 planea_params
= planeb_params
= i855_wm_info
;
2605 /* Grab a couple of global values before we overwrite them */
2606 total_size
= planea_params
.fifo_size
;
2607 cacheline_size
= planea_params
.cacheline_size
;
2609 /* Update per-plane FIFO sizes */
2610 planea_params
.fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 0);
2611 planeb_params
.fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 1);
2613 planea_wm
= intel_calculate_wm(planea_clock
, &planea_params
,
2614 pixel_size
, latency_ns
);
2615 planeb_wm
= intel_calculate_wm(planeb_clock
, &planeb_params
,
2616 pixel_size
, latency_ns
);
2617 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
2620 * Overlay gets an aggressive default since video jitter is bad.
2624 /* Calc sr entries for one plane configs */
2625 if (HAS_FW_BLC(dev
) && sr_hdisplay
&&
2626 (!planea_clock
|| !planeb_clock
)) {
2627 /* self-refresh has much higher latency */
2628 static const int sr_latency_ns
= 6000;
2630 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
2631 line_time_us
= ((sr_hdisplay
* 1000) / sr_clock
);
2633 /* Use ns/us then divide to preserve precision */
2634 sr_entries
= (((sr_latency_ns
/ line_time_us
) + 1) *
2635 pixel_size
* sr_hdisplay
) / 1000;
2636 sr_entries
= roundup(sr_entries
/ cacheline_size
, 1);
2637 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries
);
2638 srwm
= total_size
- sr_entries
;
2641 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN
| (srwm
& 0x3f));
2643 /* Turn off self refresh if both pipes are enabled */
2644 I915_WRITE(FW_BLC_SELF
, I915_READ(FW_BLC_SELF
)
2648 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2649 planea_wm
, planeb_wm
, cwm
, srwm
);
2651 fwater_lo
= ((planeb_wm
& 0x3f) << 16) | (planea_wm
& 0x3f);
2652 fwater_hi
= (cwm
& 0x1f);
2654 /* Set request length to 8 cachelines per fetch */
2655 fwater_lo
= fwater_lo
| (1 << 24) | (1 << 8);
2656 fwater_hi
= fwater_hi
| (1 << 8);
2658 I915_WRITE(FW_BLC
, fwater_lo
);
2659 I915_WRITE(FW_BLC2
, fwater_hi
);
2662 static void i830_update_wm(struct drm_device
*dev
, int planea_clock
, int unused
,
2663 int unused2
, int pixel_size
)
2665 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2666 uint32_t fwater_lo
= I915_READ(FW_BLC
) & ~0xfff;
2669 i830_wm_info
.fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 0);
2671 planea_wm
= intel_calculate_wm(planea_clock
, &i830_wm_info
,
2672 pixel_size
, latency_ns
);
2673 fwater_lo
|= (3<<8) | planea_wm
;
2675 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm
);
2677 I915_WRITE(FW_BLC
, fwater_lo
);
2681 * intel_update_watermarks - update FIFO watermark values based on current modes
2683 * Calculate watermark values for the various WM regs based on current mode
2684 * and plane configuration.
2686 * There are several cases to deal with here:
2687 * - normal (i.e. non-self-refresh)
2688 * - self-refresh (SR) mode
2689 * - lines are large relative to FIFO size (buffer can hold up to 2)
2690 * - lines are small relative to FIFO size (buffer can hold more than 2
2691 * lines), so need to account for TLB latency
2693 * The normal calculation is:
2694 * watermark = dotclock * bytes per pixel * latency
2695 * where latency is platform & configuration dependent (we assume pessimal
2698 * The SR calculation is:
2699 * watermark = (trunc(latency/line time)+1) * surface width *
2702 * line time = htotal / dotclock
2703 * and latency is assumed to be high, as above.
2705 * The final value programmed to the register should always be rounded up,
2706 * and include an extra 2 entries to account for clock crossings.
2708 * We don't use the sprite, so we can ignore that. And on Crestline we have
2709 * to set the non-SR watermarks to 8.
2711 static void intel_update_watermarks(struct drm_device
*dev
)
2713 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2714 struct drm_crtc
*crtc
;
2715 struct intel_crtc
*intel_crtc
;
2716 int sr_hdisplay
= 0;
2717 unsigned long planea_clock
= 0, planeb_clock
= 0, sr_clock
= 0;
2718 int enabled
= 0, pixel_size
= 0;
2720 if (!dev_priv
->display
.update_wm
)
2723 /* Get the clock config from both planes */
2724 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2725 intel_crtc
= to_intel_crtc(crtc
);
2726 if (crtc
->enabled
) {
2728 if (intel_crtc
->plane
== 0) {
2729 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
2730 intel_crtc
->pipe
, crtc
->mode
.clock
);
2731 planea_clock
= crtc
->mode
.clock
;
2733 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
2734 intel_crtc
->pipe
, crtc
->mode
.clock
);
2735 planeb_clock
= crtc
->mode
.clock
;
2737 sr_hdisplay
= crtc
->mode
.hdisplay
;
2738 sr_clock
= crtc
->mode
.clock
;
2740 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
2742 pixel_size
= 4; /* by default */
2749 /* Single plane configs can enable self refresh */
2750 if (enabled
== 1 && IS_PINEVIEW(dev
))
2751 pineview_enable_cxsr(dev
, sr_clock
, pixel_size
);
2752 else if (IS_PINEVIEW(dev
))
2753 pineview_disable_cxsr(dev
);
2755 dev_priv
->display
.update_wm(dev
, planea_clock
, planeb_clock
,
2756 sr_hdisplay
, pixel_size
);
2759 static int intel_crtc_mode_set(struct drm_crtc
*crtc
,
2760 struct drm_display_mode
*mode
,
2761 struct drm_display_mode
*adjusted_mode
,
2763 struct drm_framebuffer
*old_fb
)
2765 struct drm_device
*dev
= crtc
->dev
;
2766 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2767 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2768 int pipe
= intel_crtc
->pipe
;
2769 int plane
= intel_crtc
->plane
;
2770 int fp_reg
= (pipe
== 0) ? FPA0
: FPB0
;
2771 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
2772 int dpll_md_reg
= (intel_crtc
->pipe
== 0) ? DPLL_A_MD
: DPLL_B_MD
;
2773 int dspcntr_reg
= (plane
== 0) ? DSPACNTR
: DSPBCNTR
;
2774 int pipeconf_reg
= (pipe
== 0) ? PIPEACONF
: PIPEBCONF
;
2775 int htot_reg
= (pipe
== 0) ? HTOTAL_A
: HTOTAL_B
;
2776 int hblank_reg
= (pipe
== 0) ? HBLANK_A
: HBLANK_B
;
2777 int hsync_reg
= (pipe
== 0) ? HSYNC_A
: HSYNC_B
;
2778 int vtot_reg
= (pipe
== 0) ? VTOTAL_A
: VTOTAL_B
;
2779 int vblank_reg
= (pipe
== 0) ? VBLANK_A
: VBLANK_B
;
2780 int vsync_reg
= (pipe
== 0) ? VSYNC_A
: VSYNC_B
;
2781 int dspsize_reg
= (plane
== 0) ? DSPASIZE
: DSPBSIZE
;
2782 int dsppos_reg
= (plane
== 0) ? DSPAPOS
: DSPBPOS
;
2783 int pipesrc_reg
= (pipe
== 0) ? PIPEASRC
: PIPEBSRC
;
2784 int refclk
, num_outputs
= 0;
2785 intel_clock_t clock
, reduced_clock
;
2786 u32 dpll
= 0, fp
= 0, fp2
= 0, dspcntr
, pipeconf
;
2787 bool ok
, has_reduced_clock
= false, is_sdvo
= false, is_dvo
= false;
2788 bool is_crt
= false, is_lvds
= false, is_tv
= false, is_dp
= false;
2789 bool is_edp
= false;
2790 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
2791 struct drm_connector
*connector
;
2792 const intel_limit_t
*limit
;
2794 struct fdi_m_n m_n
= {0};
2795 int data_m1_reg
= (pipe
== 0) ? PIPEA_DATA_M1
: PIPEB_DATA_M1
;
2796 int data_n1_reg
= (pipe
== 0) ? PIPEA_DATA_N1
: PIPEB_DATA_N1
;
2797 int link_m1_reg
= (pipe
== 0) ? PIPEA_LINK_M1
: PIPEB_LINK_M1
;
2798 int link_n1_reg
= (pipe
== 0) ? PIPEA_LINK_N1
: PIPEB_LINK_N1
;
2799 int pch_fp_reg
= (pipe
== 0) ? PCH_FPA0
: PCH_FPB0
;
2800 int pch_dpll_reg
= (pipe
== 0) ? PCH_DPLL_A
: PCH_DPLL_B
;
2801 int fdi_rx_reg
= (pipe
== 0) ? FDI_RXA_CTL
: FDI_RXB_CTL
;
2802 int lvds_reg
= LVDS
;
2804 int sdvo_pixel_multiply
;
2807 drm_vblank_pre_modeset(dev
, pipe
);
2809 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
2810 struct intel_output
*intel_output
= to_intel_output(connector
);
2812 if (!connector
->encoder
|| connector
->encoder
->crtc
!= crtc
)
2815 switch (intel_output
->type
) {
2816 case INTEL_OUTPUT_LVDS
:
2819 case INTEL_OUTPUT_SDVO
:
2820 case INTEL_OUTPUT_HDMI
:
2822 if (intel_output
->needs_tv_clock
)
2825 case INTEL_OUTPUT_DVO
:
2828 case INTEL_OUTPUT_TVOUT
:
2831 case INTEL_OUTPUT_ANALOG
:
2834 case INTEL_OUTPUT_DISPLAYPORT
:
2837 case INTEL_OUTPUT_EDP
:
2845 if (is_lvds
&& dev_priv
->lvds_use_ssc
&& num_outputs
< 2) {
2846 refclk
= dev_priv
->lvds_ssc_freq
* 1000;
2847 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
2849 } else if (IS_I9XX(dev
)) {
2851 if (IS_IRONLAKE(dev
))
2852 refclk
= 120000; /* 120Mhz refclk */
2859 * Returns a set of divisors for the desired target clock with the given
2860 * refclk, or FALSE. The returned values represent the clock equation:
2861 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
2863 limit
= intel_limit(crtc
);
2864 ok
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, &clock
);
2866 DRM_ERROR("Couldn't find PLL settings for mode!\n");
2867 drm_vblank_post_modeset(dev
, pipe
);
2871 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
2872 has_reduced_clock
= limit
->find_pll(limit
, crtc
,
2873 dev_priv
->lvds_downclock
,
2876 if (has_reduced_clock
&& (clock
.p
!= reduced_clock
.p
)) {
2878 * If the different P is found, it means that we can't
2879 * switch the display clock by using the FP0/FP1.
2880 * In such case we will disable the LVDS downclock
2883 DRM_DEBUG_KMS("Different P is found for "
2884 "LVDS clock/downclock\n");
2885 has_reduced_clock
= 0;
2888 /* SDVO TV has fixed PLL values depend on its clock range,
2889 this mirrors vbios setting. */
2890 if (is_sdvo
&& is_tv
) {
2891 if (adjusted_mode
->clock
>= 100000
2892 && adjusted_mode
->clock
< 140500) {
2898 } else if (adjusted_mode
->clock
>= 140500
2899 && adjusted_mode
->clock
<= 200000) {
2909 if (IS_IRONLAKE(dev
)) {
2910 int lane
, link_bw
, bpp
;
2911 /* eDP doesn't require FDI link, so just set DP M/N
2912 according to current link config */
2914 struct drm_connector
*edp
;
2915 target_clock
= mode
->clock
;
2916 edp
= intel_pipe_get_output(crtc
);
2917 intel_edp_link_config(to_intel_output(edp
),
2920 /* DP over FDI requires target mode clock
2921 instead of link clock */
2923 target_clock
= mode
->clock
;
2925 target_clock
= adjusted_mode
->clock
;
2930 /* determine panel color depth */
2931 temp
= I915_READ(pipeconf_reg
);
2932 temp
&= ~PIPE_BPC_MASK
;
2934 int lvds_reg
= I915_READ(PCH_LVDS
);
2935 /* the BPC will be 6 if it is 18-bit LVDS panel */
2936 if ((lvds_reg
& LVDS_A3_POWER_MASK
) == LVDS_A3_POWER_UP
)
2940 } else if (is_edp
) {
2941 switch (dev_priv
->edp_bpp
/3) {
2957 I915_WRITE(pipeconf_reg
, temp
);
2958 I915_READ(pipeconf_reg
);
2960 switch (temp
& PIPE_BPC_MASK
) {
2974 DRM_ERROR("unknown pipe bpc value\n");
2978 ironlake_compute_m_n(bpp
, lane
, target_clock
, link_bw
, &m_n
);
2981 /* Ironlake: try to setup display ref clock before DPLL
2982 * enabling. This is only under driver's control after
2983 * PCH B stepping, previous chipset stepping should be
2984 * ignoring this setting.
2986 if (IS_IRONLAKE(dev
)) {
2987 temp
= I915_READ(PCH_DREF_CONTROL
);
2988 /* Always enable nonspread source */
2989 temp
&= ~DREF_NONSPREAD_SOURCE_MASK
;
2990 temp
|= DREF_NONSPREAD_SOURCE_ENABLE
;
2991 I915_WRITE(PCH_DREF_CONTROL
, temp
);
2992 POSTING_READ(PCH_DREF_CONTROL
);
2994 temp
&= ~DREF_SSC_SOURCE_MASK
;
2995 temp
|= DREF_SSC_SOURCE_ENABLE
;
2996 I915_WRITE(PCH_DREF_CONTROL
, temp
);
2997 POSTING_READ(PCH_DREF_CONTROL
);
3002 if (dev_priv
->lvds_use_ssc
) {
3003 temp
|= DREF_SSC1_ENABLE
;
3004 I915_WRITE(PCH_DREF_CONTROL
, temp
);
3005 POSTING_READ(PCH_DREF_CONTROL
);
3009 temp
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
3010 temp
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
3011 I915_WRITE(PCH_DREF_CONTROL
, temp
);
3012 POSTING_READ(PCH_DREF_CONTROL
);
3014 temp
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
3015 I915_WRITE(PCH_DREF_CONTROL
, temp
);
3016 POSTING_READ(PCH_DREF_CONTROL
);
3021 if (IS_PINEVIEW(dev
)) {
3022 fp
= (1 << clock
.n
) << 16 | clock
.m1
<< 8 | clock
.m2
;
3023 if (has_reduced_clock
)
3024 fp2
= (1 << reduced_clock
.n
) << 16 |
3025 reduced_clock
.m1
<< 8 | reduced_clock
.m2
;
3027 fp
= clock
.n
<< 16 | clock
.m1
<< 8 | clock
.m2
;
3028 if (has_reduced_clock
)
3029 fp2
= reduced_clock
.n
<< 16 | reduced_clock
.m1
<< 8 |
3033 if (!IS_IRONLAKE(dev
))
3034 dpll
= DPLL_VGA_MODE_DIS
;
3038 dpll
|= DPLLB_MODE_LVDS
;
3040 dpll
|= DPLLB_MODE_DAC_SERIAL
;
3042 dpll
|= DPLL_DVO_HIGH_SPEED
;
3043 sdvo_pixel_multiply
= adjusted_mode
->clock
/ mode
->clock
;
3044 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
3045 dpll
|= (sdvo_pixel_multiply
- 1) << SDVO_MULTIPLIER_SHIFT_HIRES
;
3046 else if (IS_IRONLAKE(dev
))
3047 dpll
|= (sdvo_pixel_multiply
- 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
3050 dpll
|= DPLL_DVO_HIGH_SPEED
;
3052 /* compute bitmask from p1 value */
3053 if (IS_PINEVIEW(dev
))
3054 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
3056 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
3058 if (IS_IRONLAKE(dev
))
3059 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
3060 if (IS_G4X(dev
) && has_reduced_clock
)
3061 dpll
|= (1 << (reduced_clock
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
3065 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
3068 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
3071 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
3074 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
3077 if (IS_I965G(dev
) && !IS_IRONLAKE(dev
))
3078 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
3081 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
3084 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
3086 dpll
|= (clock
.p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
3088 dpll
|= PLL_P2_DIVIDE_BY_4
;
3092 if (is_sdvo
&& is_tv
)
3093 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
3095 /* XXX: just matching BIOS for now */
3096 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3098 else if (is_lvds
&& dev_priv
->lvds_use_ssc
&& num_outputs
< 2)
3099 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
3101 dpll
|= PLL_REF_INPUT_DREFCLK
;
3103 /* setup pipeconf */
3104 pipeconf
= I915_READ(pipeconf_reg
);
3106 /* Set up the display plane register */
3107 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
3109 /* Ironlake's plane is forced to pipe, bit 24 is to
3110 enable color space conversion */
3111 if (!IS_IRONLAKE(dev
)) {
3113 dspcntr
&= ~DISPPLANE_SEL_PIPE_MASK
;
3115 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
3118 if (pipe
== 0 && !IS_I965G(dev
)) {
3119 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3122 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3126 dev_priv
->display
.get_display_clock_speed(dev
) * 9 / 10)
3127 pipeconf
|= PIPEACONF_DOUBLE_WIDE
;
3129 pipeconf
&= ~PIPEACONF_DOUBLE_WIDE
;
3132 dspcntr
|= DISPLAY_PLANE_ENABLE
;
3133 pipeconf
|= PIPEACONF_ENABLE
;
3134 dpll
|= DPLL_VCO_ENABLE
;
3137 /* Disable the panel fitter if it was on our pipe */
3138 if (!IS_IRONLAKE(dev
) && intel_panel_fitter_pipe(dev
) == pipe
)
3139 I915_WRITE(PFIT_CONTROL
, 0);
3141 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe
== 0 ? 'A' : 'B');
3142 drm_mode_debug_printmodeline(mode
);
3144 /* assign to Ironlake registers */
3145 if (IS_IRONLAKE(dev
)) {
3146 fp_reg
= pch_fp_reg
;
3147 dpll_reg
= pch_dpll_reg
;
3151 ironlake_disable_pll_edp(crtc
);
3152 } else if ((dpll
& DPLL_VCO_ENABLE
)) {
3153 I915_WRITE(fp_reg
, fp
);
3154 I915_WRITE(dpll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
3155 I915_READ(dpll_reg
);
3159 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3160 * This is an exception to the general rule that mode_set doesn't turn
3166 if (IS_IRONLAKE(dev
))
3167 lvds_reg
= PCH_LVDS
;
3169 lvds
= I915_READ(lvds_reg
);
3170 lvds
|= LVDS_PORT_EN
| LVDS_A0A2_CLKA_POWER_UP
| LVDS_PIPEB_SELECT
;
3171 /* set the corresponsding LVDS_BORDER bit */
3172 lvds
|= dev_priv
->lvds_border_bits
;
3173 /* Set the B0-B3 data pairs corresponding to whether we're going to
3174 * set the DPLLs for dual-channel mode or not.
3177 lvds
|= LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
;
3179 lvds
&= ~(LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
);
3181 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3182 * appropriately here, but we need to look more thoroughly into how
3183 * panels behave in the two modes.
3185 /* set the dithering flag */
3186 if (IS_I965G(dev
)) {
3187 if (dev_priv
->lvds_dither
) {
3188 if (IS_IRONLAKE(dev
))
3189 pipeconf
|= PIPE_ENABLE_DITHER
;
3191 lvds
|= LVDS_ENABLE_DITHER
;
3193 if (IS_IRONLAKE(dev
))
3194 pipeconf
&= ~PIPE_ENABLE_DITHER
;
3196 lvds
&= ~LVDS_ENABLE_DITHER
;
3199 I915_WRITE(lvds_reg
, lvds
);
3200 I915_READ(lvds_reg
);
3203 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
3206 I915_WRITE(fp_reg
, fp
);
3207 I915_WRITE(dpll_reg
, dpll
);
3208 I915_READ(dpll_reg
);
3209 /* Wait for the clocks to stabilize. */
3212 if (IS_I965G(dev
) && !IS_IRONLAKE(dev
)) {
3214 sdvo_pixel_multiply
= adjusted_mode
->clock
/ mode
->clock
;
3215 I915_WRITE(dpll_md_reg
, (0 << DPLL_MD_UDI_DIVIDER_SHIFT
) |
3216 ((sdvo_pixel_multiply
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
));
3218 I915_WRITE(dpll_md_reg
, 0);
3220 /* write it again -- the BIOS does, after all */
3221 I915_WRITE(dpll_reg
, dpll
);
3223 I915_READ(dpll_reg
);
3224 /* Wait for the clocks to stabilize. */
3228 if (is_lvds
&& has_reduced_clock
&& i915_powersave
) {
3229 I915_WRITE(fp_reg
+ 4, fp2
);
3230 intel_crtc
->lowfreq_avail
= true;
3231 if (HAS_PIPE_CXSR(dev
)) {
3232 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3233 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
3236 I915_WRITE(fp_reg
+ 4, fp
);
3237 intel_crtc
->lowfreq_avail
= false;
3238 if (HAS_PIPE_CXSR(dev
)) {
3239 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3240 pipeconf
&= ~PIPECONF_CXSR_DOWNCLOCK
;
3244 I915_WRITE(htot_reg
, (adjusted_mode
->crtc_hdisplay
- 1) |
3245 ((adjusted_mode
->crtc_htotal
- 1) << 16));
3246 I915_WRITE(hblank_reg
, (adjusted_mode
->crtc_hblank_start
- 1) |
3247 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
3248 I915_WRITE(hsync_reg
, (adjusted_mode
->crtc_hsync_start
- 1) |
3249 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
3250 I915_WRITE(vtot_reg
, (adjusted_mode
->crtc_vdisplay
- 1) |
3251 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
3252 I915_WRITE(vblank_reg
, (adjusted_mode
->crtc_vblank_start
- 1) |
3253 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
3254 I915_WRITE(vsync_reg
, (adjusted_mode
->crtc_vsync_start
- 1) |
3255 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
3256 /* pipesrc and dspsize control the size that is scaled from, which should
3257 * always be the user's requested size.
3259 if (!IS_IRONLAKE(dev
)) {
3260 I915_WRITE(dspsize_reg
, ((mode
->vdisplay
- 1) << 16) |
3261 (mode
->hdisplay
- 1));
3262 I915_WRITE(dsppos_reg
, 0);
3264 I915_WRITE(pipesrc_reg
, ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
3266 if (IS_IRONLAKE(dev
)) {
3267 I915_WRITE(data_m1_reg
, TU_SIZE(m_n
.tu
) | m_n
.gmch_m
);
3268 I915_WRITE(data_n1_reg
, TU_SIZE(m_n
.tu
) | m_n
.gmch_n
);
3269 I915_WRITE(link_m1_reg
, m_n
.link_m
);
3270 I915_WRITE(link_n1_reg
, m_n
.link_n
);
3273 ironlake_set_pll_edp(crtc
, adjusted_mode
->clock
);
3275 /* enable FDI RX PLL too */
3276 temp
= I915_READ(fdi_rx_reg
);
3277 I915_WRITE(fdi_rx_reg
, temp
| FDI_RX_PLL_ENABLE
);
3282 I915_WRITE(pipeconf_reg
, pipeconf
);
3283 I915_READ(pipeconf_reg
);
3285 intel_wait_for_vblank(dev
);
3287 if (IS_IRONLAKE(dev
)) {
3288 /* enable address swizzle for tiling buffer */
3289 temp
= I915_READ(DISP_ARB_CTL
);
3290 I915_WRITE(DISP_ARB_CTL
, temp
| DISP_TILE_SURFACE_SWIZZLING
);
3293 I915_WRITE(dspcntr_reg
, dspcntr
);
3295 /* Flush the plane changes */
3296 ret
= intel_pipe_set_base(crtc
, x
, y
, old_fb
);
3298 if ((IS_I965G(dev
) || plane
== 0))
3299 intel_update_fbc(crtc
, &crtc
->mode
);
3301 intel_update_watermarks(dev
);
3303 drm_vblank_post_modeset(dev
, pipe
);
3308 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3309 void intel_crtc_load_lut(struct drm_crtc
*crtc
)
3311 struct drm_device
*dev
= crtc
->dev
;
3312 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3313 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3314 int palreg
= (intel_crtc
->pipe
== 0) ? PALETTE_A
: PALETTE_B
;
3317 /* The clocks have to be on to load the palette. */
3321 /* use legacy palette for Ironlake */
3322 if (IS_IRONLAKE(dev
))
3323 palreg
= (intel_crtc
->pipe
== 0) ? LGC_PALETTE_A
:
3326 for (i
= 0; i
< 256; i
++) {
3327 I915_WRITE(palreg
+ 4 * i
,
3328 (intel_crtc
->lut_r
[i
] << 16) |
3329 (intel_crtc
->lut_g
[i
] << 8) |
3330 intel_crtc
->lut_b
[i
]);
3334 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
3335 struct drm_file
*file_priv
,
3337 uint32_t width
, uint32_t height
)
3339 struct drm_device
*dev
= crtc
->dev
;
3340 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3341 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3342 struct drm_gem_object
*bo
;
3343 struct drm_i915_gem_object
*obj_priv
;
3344 int pipe
= intel_crtc
->pipe
;
3345 uint32_t control
= (pipe
== 0) ? CURACNTR
: CURBCNTR
;
3346 uint32_t base
= (pipe
== 0) ? CURABASE
: CURBBASE
;
3347 uint32_t temp
= I915_READ(control
);
3351 DRM_DEBUG_KMS("\n");
3353 /* if we want to turn off the cursor ignore width and height */
3355 DRM_DEBUG_KMS("cursor off\n");
3356 if (IS_MOBILE(dev
) || IS_I9XX(dev
)) {
3357 temp
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
3358 temp
|= CURSOR_MODE_DISABLE
;
3360 temp
&= ~(CURSOR_ENABLE
| CURSOR_GAMMA_ENABLE
);
3364 mutex_lock(&dev
->struct_mutex
);
3368 /* Currently we only support 64x64 cursors */
3369 if (width
!= 64 || height
!= 64) {
3370 DRM_ERROR("we currently only support 64x64 cursors\n");
3374 bo
= drm_gem_object_lookup(dev
, file_priv
, handle
);
3378 obj_priv
= bo
->driver_private
;
3380 if (bo
->size
< width
* height
* 4) {
3381 DRM_ERROR("buffer is to small\n");
3386 /* we only need to pin inside GTT if cursor is non-phy */
3387 mutex_lock(&dev
->struct_mutex
);
3388 if (!dev_priv
->info
->cursor_needs_physical
) {
3389 ret
= i915_gem_object_pin(bo
, PAGE_SIZE
);
3391 DRM_ERROR("failed to pin cursor bo\n");
3394 addr
= obj_priv
->gtt_offset
;
3396 ret
= i915_gem_attach_phys_object(dev
, bo
, (pipe
== 0) ? I915_GEM_PHYS_CURSOR_0
: I915_GEM_PHYS_CURSOR_1
);
3398 DRM_ERROR("failed to attach phys object\n");
3401 addr
= obj_priv
->phys_obj
->handle
->busaddr
;
3405 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
3407 /* Hooray for CUR*CNTR differences */
3408 if (IS_MOBILE(dev
) || IS_I9XX(dev
)) {
3409 temp
&= ~(CURSOR_MODE
| MCURSOR_PIPE_SELECT
);
3410 temp
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
3411 temp
|= (pipe
<< 28); /* Connect to correct pipe */
3413 temp
&= ~(CURSOR_FORMAT_MASK
);
3414 temp
|= CURSOR_ENABLE
;
3415 temp
|= CURSOR_FORMAT_ARGB
| CURSOR_GAMMA_ENABLE
;
3419 I915_WRITE(control
, temp
);
3420 I915_WRITE(base
, addr
);
3422 if (intel_crtc
->cursor_bo
) {
3423 if (dev_priv
->info
->cursor_needs_physical
) {
3424 if (intel_crtc
->cursor_bo
!= bo
)
3425 i915_gem_detach_phys_object(dev
, intel_crtc
->cursor_bo
);
3427 i915_gem_object_unpin(intel_crtc
->cursor_bo
);
3428 drm_gem_object_unreference(intel_crtc
->cursor_bo
);
3431 mutex_unlock(&dev
->struct_mutex
);
3433 intel_crtc
->cursor_addr
= addr
;
3434 intel_crtc
->cursor_bo
= bo
;
3438 mutex_unlock(&dev
->struct_mutex
);
3440 drm_gem_object_unreference_unlocked(bo
);
3444 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
3446 struct drm_device
*dev
= crtc
->dev
;
3447 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3448 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3449 struct intel_framebuffer
*intel_fb
;
3450 int pipe
= intel_crtc
->pipe
;
3455 intel_fb
= to_intel_framebuffer(crtc
->fb
);
3456 intel_mark_busy(dev
, intel_fb
->obj
);
3460 temp
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
3464 temp
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
3468 temp
|= x
<< CURSOR_X_SHIFT
;
3469 temp
|= y
<< CURSOR_Y_SHIFT
;
3471 adder
= intel_crtc
->cursor_addr
;
3472 I915_WRITE((pipe
== 0) ? CURAPOS
: CURBPOS
, temp
);
3473 I915_WRITE((pipe
== 0) ? CURABASE
: CURBBASE
, adder
);
3478 /** Sets the color ramps on behalf of RandR */
3479 void intel_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
3480 u16 blue
, int regno
)
3482 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3484 intel_crtc
->lut_r
[regno
] = red
>> 8;
3485 intel_crtc
->lut_g
[regno
] = green
>> 8;
3486 intel_crtc
->lut_b
[regno
] = blue
>> 8;
3489 void intel_crtc_fb_gamma_get(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
3490 u16
*blue
, int regno
)
3492 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3494 *red
= intel_crtc
->lut_r
[regno
] << 8;
3495 *green
= intel_crtc
->lut_g
[regno
] << 8;
3496 *blue
= intel_crtc
->lut_b
[regno
] << 8;
3499 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
3500 u16
*blue
, uint32_t size
)
3502 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3508 for (i
= 0; i
< 256; i
++) {
3509 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
3510 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
3511 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
3514 intel_crtc_load_lut(crtc
);
3518 * Get a pipe with a simple mode set on it for doing load-based monitor
3521 * It will be up to the load-detect code to adjust the pipe as appropriate for
3522 * its requirements. The pipe will be connected to no other outputs.
3524 * Currently this code will only succeed if there is a pipe with no outputs
3525 * configured for it. In the future, it could choose to temporarily disable
3526 * some outputs to free up a pipe for its use.
3528 * \return crtc, or NULL if no pipes are available.
3531 /* VESA 640x480x72Hz mode to set on the pipe */
3532 static struct drm_display_mode load_detect_mode
= {
3533 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
3534 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
3537 struct drm_crtc
*intel_get_load_detect_pipe(struct intel_output
*intel_output
,
3538 struct drm_display_mode
*mode
,
3541 struct intel_crtc
*intel_crtc
;
3542 struct drm_crtc
*possible_crtc
;
3543 struct drm_crtc
*supported_crtc
=NULL
;
3544 struct drm_encoder
*encoder
= &intel_output
->enc
;
3545 struct drm_crtc
*crtc
= NULL
;
3546 struct drm_device
*dev
= encoder
->dev
;
3547 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
3548 struct drm_crtc_helper_funcs
*crtc_funcs
;
3552 * Algorithm gets a little messy:
3553 * - if the connector already has an assigned crtc, use it (but make
3554 * sure it's on first)
3555 * - try to find the first unused crtc that can drive this connector,
3556 * and use that if we find one
3557 * - if there are no unused crtcs available, try to use the first
3558 * one we found that supports the connector
3561 /* See if we already have a CRTC for this connector */
3562 if (encoder
->crtc
) {
3563 crtc
= encoder
->crtc
;
3564 /* Make sure the crtc and connector are running */
3565 intel_crtc
= to_intel_crtc(crtc
);
3566 *dpms_mode
= intel_crtc
->dpms_mode
;
3567 if (intel_crtc
->dpms_mode
!= DRM_MODE_DPMS_ON
) {
3568 crtc_funcs
= crtc
->helper_private
;
3569 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
3570 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
3575 /* Find an unused one (if possible) */
3576 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
3578 if (!(encoder
->possible_crtcs
& (1 << i
)))
3580 if (!possible_crtc
->enabled
) {
3581 crtc
= possible_crtc
;
3584 if (!supported_crtc
)
3585 supported_crtc
= possible_crtc
;
3589 * If we didn't find an unused CRTC, don't use any.
3595 encoder
->crtc
= crtc
;
3596 intel_output
->base
.encoder
= encoder
;
3597 intel_output
->load_detect_temp
= true;
3599 intel_crtc
= to_intel_crtc(crtc
);
3600 *dpms_mode
= intel_crtc
->dpms_mode
;
3602 if (!crtc
->enabled
) {
3604 mode
= &load_detect_mode
;
3605 drm_crtc_helper_set_mode(crtc
, mode
, 0, 0, crtc
->fb
);
3607 if (intel_crtc
->dpms_mode
!= DRM_MODE_DPMS_ON
) {
3608 crtc_funcs
= crtc
->helper_private
;
3609 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
3612 /* Add this connector to the crtc */
3613 encoder_funcs
->mode_set(encoder
, &crtc
->mode
, &crtc
->mode
);
3614 encoder_funcs
->commit(encoder
);
3616 /* let the connector get through one full cycle before testing */
3617 intel_wait_for_vblank(dev
);
3622 void intel_release_load_detect_pipe(struct intel_output
*intel_output
, int dpms_mode
)
3624 struct drm_encoder
*encoder
= &intel_output
->enc
;
3625 struct drm_device
*dev
= encoder
->dev
;
3626 struct drm_crtc
*crtc
= encoder
->crtc
;
3627 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
3628 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
3630 if (intel_output
->load_detect_temp
) {
3631 encoder
->crtc
= NULL
;
3632 intel_output
->base
.encoder
= NULL
;
3633 intel_output
->load_detect_temp
= false;
3634 crtc
->enabled
= drm_helper_crtc_in_use(crtc
);
3635 drm_helper_disable_unused_functions(dev
);
3638 /* Switch crtc and output back off if necessary */
3639 if (crtc
->enabled
&& dpms_mode
!= DRM_MODE_DPMS_ON
) {
3640 if (encoder
->crtc
== crtc
)
3641 encoder_funcs
->dpms(encoder
, dpms_mode
);
3642 crtc_funcs
->dpms(crtc
, dpms_mode
);
3646 /* Returns the clock of the currently programmed mode of the given pipe. */
3647 static int intel_crtc_clock_get(struct drm_device
*dev
, struct drm_crtc
*crtc
)
3649 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3650 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3651 int pipe
= intel_crtc
->pipe
;
3652 u32 dpll
= I915_READ((pipe
== 0) ? DPLL_A
: DPLL_B
);
3654 intel_clock_t clock
;
3656 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
3657 fp
= I915_READ((pipe
== 0) ? FPA0
: FPB0
);
3659 fp
= I915_READ((pipe
== 0) ? FPA1
: FPB1
);
3661 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
3662 if (IS_PINEVIEW(dev
)) {
3663 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
3664 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
3666 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
3667 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
3671 if (IS_PINEVIEW(dev
))
3672 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
3673 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
3675 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
3676 DPLL_FPA01_P1_POST_DIV_SHIFT
);
3678 switch (dpll
& DPLL_MODE_MASK
) {
3679 case DPLLB_MODE_DAC_SERIAL
:
3680 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
3683 case DPLLB_MODE_LVDS
:
3684 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
3688 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
3689 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
3693 /* XXX: Handle the 100Mhz refclk */
3694 intel_clock(dev
, 96000, &clock
);
3696 bool is_lvds
= (pipe
== 1) && (I915_READ(LVDS
) & LVDS_PORT_EN
);
3699 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
3700 DPLL_FPA01_P1_POST_DIV_SHIFT
);
3703 if ((dpll
& PLL_REF_INPUT_MASK
) ==
3704 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
3705 /* XXX: might not be 66MHz */
3706 intel_clock(dev
, 66000, &clock
);
3708 intel_clock(dev
, 48000, &clock
);
3710 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
3713 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
3714 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
3716 if (dpll
& PLL_P2_DIVIDE_BY_4
)
3721 intel_clock(dev
, 48000, &clock
);
3725 /* XXX: It would be nice to validate the clocks, but we can't reuse
3726 * i830PllIsValid() because it relies on the xf86_config connector
3727 * configuration being accurate, which it isn't necessarily.
3733 /** Returns the currently programmed mode of the given pipe. */
3734 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
3735 struct drm_crtc
*crtc
)
3737 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3738 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3739 int pipe
= intel_crtc
->pipe
;
3740 struct drm_display_mode
*mode
;
3741 int htot
= I915_READ((pipe
== 0) ? HTOTAL_A
: HTOTAL_B
);
3742 int hsync
= I915_READ((pipe
== 0) ? HSYNC_A
: HSYNC_B
);
3743 int vtot
= I915_READ((pipe
== 0) ? VTOTAL_A
: VTOTAL_B
);
3744 int vsync
= I915_READ((pipe
== 0) ? VSYNC_A
: VSYNC_B
);
3746 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
3750 mode
->clock
= intel_crtc_clock_get(dev
, crtc
);
3751 mode
->hdisplay
= (htot
& 0xffff) + 1;
3752 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
3753 mode
->hsync_start
= (hsync
& 0xffff) + 1;
3754 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
3755 mode
->vdisplay
= (vtot
& 0xffff) + 1;
3756 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
3757 mode
->vsync_start
= (vsync
& 0xffff) + 1;
3758 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
3760 drm_mode_set_name(mode
);
3761 drm_mode_set_crtcinfo(mode
, 0);
3766 #define GPU_IDLE_TIMEOUT 500 /* ms */
3768 /* When this timer fires, we've been idle for awhile */
3769 static void intel_gpu_idle_timer(unsigned long arg
)
3771 struct drm_device
*dev
= (struct drm_device
*)arg
;
3772 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3774 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
3776 dev_priv
->busy
= false;
3778 queue_work(dev_priv
->wq
, &dev_priv
->idle_work
);
3781 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
3783 static void intel_crtc_idle_timer(unsigned long arg
)
3785 struct intel_crtc
*intel_crtc
= (struct intel_crtc
*)arg
;
3786 struct drm_crtc
*crtc
= &intel_crtc
->base
;
3787 drm_i915_private_t
*dev_priv
= crtc
->dev
->dev_private
;
3789 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
3791 intel_crtc
->busy
= false;
3793 queue_work(dev_priv
->wq
, &dev_priv
->idle_work
);
3796 static void intel_increase_pllclock(struct drm_crtc
*crtc
, bool schedule
)
3798 struct drm_device
*dev
= crtc
->dev
;
3799 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3800 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3801 int pipe
= intel_crtc
->pipe
;
3802 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
3803 int dpll
= I915_READ(dpll_reg
);
3805 if (IS_IRONLAKE(dev
))
3808 if (!dev_priv
->lvds_downclock_avail
)
3811 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
3812 DRM_DEBUG_DRIVER("upclocking LVDS\n");
3814 /* Unlock panel regs */
3815 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) | (0xabcd << 16));
3817 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
3818 I915_WRITE(dpll_reg
, dpll
);
3819 dpll
= I915_READ(dpll_reg
);
3820 intel_wait_for_vblank(dev
);
3821 dpll
= I915_READ(dpll_reg
);
3822 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
3823 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
3825 /* ...and lock them again */
3826 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) & 0x3);
3829 /* Schedule downclock */
3831 mod_timer(&intel_crtc
->idle_timer
, jiffies
+
3832 msecs_to_jiffies(CRTC_IDLE_TIMEOUT
));
3835 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
3837 struct drm_device
*dev
= crtc
->dev
;
3838 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3839 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3840 int pipe
= intel_crtc
->pipe
;
3841 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
3842 int dpll
= I915_READ(dpll_reg
);
3844 if (IS_IRONLAKE(dev
))
3847 if (!dev_priv
->lvds_downclock_avail
)
3851 * Since this is called by a timer, we should never get here in
3854 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
3855 DRM_DEBUG_DRIVER("downclocking LVDS\n");
3857 /* Unlock panel regs */
3858 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) | (0xabcd << 16));
3860 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
3861 I915_WRITE(dpll_reg
, dpll
);
3862 dpll
= I915_READ(dpll_reg
);
3863 intel_wait_for_vblank(dev
);
3864 dpll
= I915_READ(dpll_reg
);
3865 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
3866 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
3868 /* ...and lock them again */
3869 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) & 0x3);
3875 * intel_idle_update - adjust clocks for idleness
3876 * @work: work struct
3878 * Either the GPU or display (or both) went idle. Check the busy status
3879 * here and adjust the CRTC and GPU clocks as necessary.
3881 static void intel_idle_update(struct work_struct
*work
)
3883 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
3885 struct drm_device
*dev
= dev_priv
->dev
;
3886 struct drm_crtc
*crtc
;
3887 struct intel_crtc
*intel_crtc
;
3889 if (!i915_powersave
)
3892 mutex_lock(&dev
->struct_mutex
);
3894 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
3895 /* Skip inactive CRTCs */
3899 intel_crtc
= to_intel_crtc(crtc
);
3900 if (!intel_crtc
->busy
)
3901 intel_decrease_pllclock(crtc
);
3904 mutex_unlock(&dev
->struct_mutex
);
3908 * intel_mark_busy - mark the GPU and possibly the display busy
3910 * @obj: object we're operating on
3912 * Callers can use this function to indicate that the GPU is busy processing
3913 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
3914 * buffer), we'll also mark the display as busy, so we know to increase its
3917 void intel_mark_busy(struct drm_device
*dev
, struct drm_gem_object
*obj
)
3919 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3920 struct drm_crtc
*crtc
= NULL
;
3921 struct intel_framebuffer
*intel_fb
;
3922 struct intel_crtc
*intel_crtc
;
3924 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
3927 if (!dev_priv
->busy
)
3928 dev_priv
->busy
= true;
3930 mod_timer(&dev_priv
->idle_timer
, jiffies
+
3931 msecs_to_jiffies(GPU_IDLE_TIMEOUT
));
3933 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
3937 intel_crtc
= to_intel_crtc(crtc
);
3938 intel_fb
= to_intel_framebuffer(crtc
->fb
);
3939 if (intel_fb
->obj
== obj
) {
3940 if (!intel_crtc
->busy
) {
3941 /* Non-busy -> busy, upclock */
3942 intel_increase_pllclock(crtc
, true);
3943 intel_crtc
->busy
= true;
3945 /* Busy -> busy, put off timer */
3946 mod_timer(&intel_crtc
->idle_timer
, jiffies
+
3947 msecs_to_jiffies(CRTC_IDLE_TIMEOUT
));
3953 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
3955 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3957 drm_crtc_cleanup(crtc
);
3961 struct intel_unpin_work
{
3962 struct work_struct work
;
3963 struct drm_device
*dev
;
3964 struct drm_gem_object
*obj
;
3965 struct drm_pending_vblank_event
*event
;
3969 static void intel_unpin_work_fn(struct work_struct
*__work
)
3971 struct intel_unpin_work
*work
=
3972 container_of(__work
, struct intel_unpin_work
, work
);
3974 mutex_lock(&work
->dev
->struct_mutex
);
3975 i915_gem_object_unpin(work
->obj
);
3976 drm_gem_object_unreference(work
->obj
);
3977 mutex_unlock(&work
->dev
->struct_mutex
);
3981 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
3983 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3984 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
3985 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3986 struct intel_unpin_work
*work
;
3987 struct drm_i915_gem_object
*obj_priv
;
3988 struct drm_pending_vblank_event
*e
;
3990 unsigned long flags
;
3992 /* Ignore early vblank irqs */
3993 if (intel_crtc
== NULL
)
3996 spin_lock_irqsave(&dev
->event_lock
, flags
);
3997 work
= intel_crtc
->unpin_work
;
3998 if (work
== NULL
|| !work
->pending
) {
3999 if (work
&& !work
->pending
) {
4000 obj_priv
= work
->obj
->driver_private
;
4001 DRM_DEBUG_DRIVER("flip finish: %p (%d) not pending?\n",
4003 atomic_read(&obj_priv
->pending_flip
));
4005 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
4009 intel_crtc
->unpin_work
= NULL
;
4010 drm_vblank_put(dev
, intel_crtc
->pipe
);
4014 do_gettimeofday(&now
);
4015 e
->event
.sequence
= drm_vblank_count(dev
, intel_crtc
->pipe
);
4016 e
->event
.tv_sec
= now
.tv_sec
;
4017 e
->event
.tv_usec
= now
.tv_usec
;
4018 list_add_tail(&e
->base
.link
,
4019 &e
->base
.file_priv
->event_list
);
4020 wake_up_interruptible(&e
->base
.file_priv
->event_wait
);
4023 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
4025 obj_priv
= work
->obj
->driver_private
;
4027 /* Initial scanout buffer will have a 0 pending flip count */
4028 if ((atomic_read(&obj_priv
->pending_flip
) == 0) ||
4029 atomic_dec_and_test(&obj_priv
->pending_flip
))
4030 DRM_WAKEUP(&dev_priv
->pending_flip_queue
);
4031 schedule_work(&work
->work
);
4034 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
4036 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4037 struct intel_crtc
*intel_crtc
=
4038 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
4039 unsigned long flags
;
4041 spin_lock_irqsave(&dev
->event_lock
, flags
);
4042 if (intel_crtc
->unpin_work
) {
4043 intel_crtc
->unpin_work
->pending
= 1;
4045 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
4047 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
4050 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
4051 struct drm_framebuffer
*fb
,
4052 struct drm_pending_vblank_event
*event
)
4054 struct drm_device
*dev
= crtc
->dev
;
4055 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4056 struct intel_framebuffer
*intel_fb
;
4057 struct drm_i915_gem_object
*obj_priv
;
4058 struct drm_gem_object
*obj
;
4059 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4060 struct intel_unpin_work
*work
;
4061 unsigned long flags
;
4065 work
= kzalloc(sizeof *work
, GFP_KERNEL
);
4069 mutex_lock(&dev
->struct_mutex
);
4071 work
->event
= event
;
4072 work
->dev
= crtc
->dev
;
4073 intel_fb
= to_intel_framebuffer(crtc
->fb
);
4074 work
->obj
= intel_fb
->obj
;
4075 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
4077 /* We borrow the event spin lock for protecting unpin_work */
4078 spin_lock_irqsave(&dev
->event_lock
, flags
);
4079 if (intel_crtc
->unpin_work
) {
4080 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
4081 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
4083 mutex_unlock(&dev
->struct_mutex
);
4086 intel_crtc
->unpin_work
= work
;
4087 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
4089 intel_fb
= to_intel_framebuffer(fb
);
4090 obj
= intel_fb
->obj
;
4092 ret
= intel_pin_and_fence_fb_obj(dev
, obj
);
4094 DRM_DEBUG_DRIVER("flip queue: %p pin & fence failed\n",
4095 obj
->driver_private
);
4097 intel_crtc
->unpin_work
= NULL
;
4098 mutex_unlock(&dev
->struct_mutex
);
4102 /* Reference the old fb object for the scheduled work. */
4103 drm_gem_object_reference(work
->obj
);
4106 i915_gem_object_flush_write_domain(obj
);
4107 drm_vblank_get(dev
, intel_crtc
->pipe
);
4108 obj_priv
= obj
->driver_private
;
4109 atomic_inc(&obj_priv
->pending_flip
);
4112 OUT_RING(MI_DISPLAY_FLIP
|
4113 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
4114 OUT_RING(fb
->pitch
);
4115 if (IS_I965G(dev
)) {
4116 OUT_RING(obj_priv
->gtt_offset
| obj_priv
->tiling_mode
);
4117 OUT_RING((fb
->width
<< 16) | fb
->height
);
4119 OUT_RING(obj_priv
->gtt_offset
);
4124 mutex_unlock(&dev
->struct_mutex
);
4129 static const struct drm_crtc_helper_funcs intel_helper_funcs
= {
4130 .dpms
= intel_crtc_dpms
,
4131 .mode_fixup
= intel_crtc_mode_fixup
,
4132 .mode_set
= intel_crtc_mode_set
,
4133 .mode_set_base
= intel_pipe_set_base
,
4134 .prepare
= intel_crtc_prepare
,
4135 .commit
= intel_crtc_commit
,
4136 .load_lut
= intel_crtc_load_lut
,
4139 static const struct drm_crtc_funcs intel_crtc_funcs
= {
4140 .cursor_set
= intel_crtc_cursor_set
,
4141 .cursor_move
= intel_crtc_cursor_move
,
4142 .gamma_set
= intel_crtc_gamma_set
,
4143 .set_config
= drm_crtc_helper_set_config
,
4144 .destroy
= intel_crtc_destroy
,
4145 .page_flip
= intel_crtc_page_flip
,
4149 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
4151 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4152 struct intel_crtc
*intel_crtc
;
4155 intel_crtc
= kzalloc(sizeof(struct intel_crtc
) + (INTELFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
4156 if (intel_crtc
== NULL
)
4159 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
4161 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
4162 intel_crtc
->pipe
= pipe
;
4163 intel_crtc
->plane
= pipe
;
4164 for (i
= 0; i
< 256; i
++) {
4165 intel_crtc
->lut_r
[i
] = i
;
4166 intel_crtc
->lut_g
[i
] = i
;
4167 intel_crtc
->lut_b
[i
] = i
;
4170 /* Swap pipes & planes for FBC on pre-965 */
4171 intel_crtc
->pipe
= pipe
;
4172 intel_crtc
->plane
= pipe
;
4173 if (IS_MOBILE(dev
) && (IS_I9XX(dev
) && !IS_I965G(dev
))) {
4174 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
4175 intel_crtc
->plane
= ((pipe
== 0) ? 1 : 0);
4178 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
4179 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
4180 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
4181 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
4183 intel_crtc
->cursor_addr
= 0;
4184 intel_crtc
->dpms_mode
= DRM_MODE_DPMS_OFF
;
4185 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
4187 intel_crtc
->busy
= false;
4189 setup_timer(&intel_crtc
->idle_timer
, intel_crtc_idle_timer
,
4190 (unsigned long)intel_crtc
);
4193 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
4194 struct drm_file
*file_priv
)
4196 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4197 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
4198 struct drm_mode_object
*drmmode_obj
;
4199 struct intel_crtc
*crtc
;
4202 DRM_ERROR("called with no initialization\n");
4206 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
4207 DRM_MODE_OBJECT_CRTC
);
4210 DRM_ERROR("no such CRTC id\n");
4214 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
4215 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
4220 struct drm_crtc
*intel_get_crtc_from_pipe(struct drm_device
*dev
, int pipe
)
4222 struct drm_crtc
*crtc
= NULL
;
4224 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
4225 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4226 if (intel_crtc
->pipe
== pipe
)
4232 static int intel_connector_clones(struct drm_device
*dev
, int type_mask
)
4235 struct drm_connector
*connector
;
4238 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
4239 struct intel_output
*intel_output
= to_intel_output(connector
);
4240 if (type_mask
& intel_output
->clone_mask
)
4241 index_mask
|= (1 << entry
);
4248 static void intel_setup_outputs(struct drm_device
*dev
)
4250 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4251 struct drm_connector
*connector
;
4253 intel_crt_init(dev
);
4255 /* Set up integrated LVDS */
4256 if (IS_MOBILE(dev
) && !IS_I830(dev
))
4257 intel_lvds_init(dev
);
4259 if (IS_IRONLAKE(dev
)) {
4262 if (IS_MOBILE(dev
) && (I915_READ(DP_A
) & DP_DETECTED
))
4263 intel_dp_init(dev
, DP_A
);
4265 if (I915_READ(HDMIB
) & PORT_DETECTED
) {
4267 /* found = intel_sdvo_init(dev, HDMIB); */
4270 intel_hdmi_init(dev
, HDMIB
);
4271 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
4272 intel_dp_init(dev
, PCH_DP_B
);
4275 if (I915_READ(HDMIC
) & PORT_DETECTED
)
4276 intel_hdmi_init(dev
, HDMIC
);
4278 if (I915_READ(HDMID
) & PORT_DETECTED
)
4279 intel_hdmi_init(dev
, HDMID
);
4281 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
4282 intel_dp_init(dev
, PCH_DP_C
);
4284 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
4285 intel_dp_init(dev
, PCH_DP_D
);
4287 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
4290 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
4291 DRM_DEBUG_KMS("probing SDVOB\n");
4292 found
= intel_sdvo_init(dev
, SDVOB
);
4293 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
4294 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
4295 intel_hdmi_init(dev
, SDVOB
);
4298 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
)) {
4299 DRM_DEBUG_KMS("probing DP_B\n");
4300 intel_dp_init(dev
, DP_B
);
4304 /* Before G4X SDVOC doesn't have its own detect register */
4306 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
4307 DRM_DEBUG_KMS("probing SDVOC\n");
4308 found
= intel_sdvo_init(dev
, SDVOC
);
4311 if (!found
&& (I915_READ(SDVOC
) & SDVO_DETECTED
)) {
4313 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
4314 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
4315 intel_hdmi_init(dev
, SDVOC
);
4317 if (SUPPORTS_INTEGRATED_DP(dev
)) {
4318 DRM_DEBUG_KMS("probing DP_C\n");
4319 intel_dp_init(dev
, DP_C
);
4323 if (SUPPORTS_INTEGRATED_DP(dev
) &&
4324 (I915_READ(DP_D
) & DP_DETECTED
)) {
4325 DRM_DEBUG_KMS("probing DP_D\n");
4326 intel_dp_init(dev
, DP_D
);
4328 } else if (IS_I8XX(dev
))
4329 intel_dvo_init(dev
);
4331 if (SUPPORTS_TV(dev
))
4334 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
4335 struct intel_output
*intel_output
= to_intel_output(connector
);
4336 struct drm_encoder
*encoder
= &intel_output
->enc
;
4338 encoder
->possible_crtcs
= intel_output
->crtc_mask
;
4339 encoder
->possible_clones
= intel_connector_clones(dev
,
4340 intel_output
->clone_mask
);
4344 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
4346 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
4347 struct drm_device
*dev
= fb
->dev
;
4350 intelfb_remove(dev
, fb
);
4352 drm_framebuffer_cleanup(fb
);
4353 drm_gem_object_unreference_unlocked(intel_fb
->obj
);
4358 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
4359 struct drm_file
*file_priv
,
4360 unsigned int *handle
)
4362 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
4363 struct drm_gem_object
*object
= intel_fb
->obj
;
4365 return drm_gem_handle_create(file_priv
, object
, handle
);
4368 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
4369 .destroy
= intel_user_framebuffer_destroy
,
4370 .create_handle
= intel_user_framebuffer_create_handle
,
4373 int intel_framebuffer_create(struct drm_device
*dev
,
4374 struct drm_mode_fb_cmd
*mode_cmd
,
4375 struct drm_framebuffer
**fb
,
4376 struct drm_gem_object
*obj
)
4378 struct intel_framebuffer
*intel_fb
;
4381 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
4385 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
4387 DRM_ERROR("framebuffer init failed %d\n", ret
);
4391 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
4393 intel_fb
->obj
= obj
;
4395 *fb
= &intel_fb
->base
;
4401 static struct drm_framebuffer
*
4402 intel_user_framebuffer_create(struct drm_device
*dev
,
4403 struct drm_file
*filp
,
4404 struct drm_mode_fb_cmd
*mode_cmd
)
4406 struct drm_gem_object
*obj
;
4407 struct drm_framebuffer
*fb
;
4410 obj
= drm_gem_object_lookup(dev
, filp
, mode_cmd
->handle
);
4414 ret
= intel_framebuffer_create(dev
, mode_cmd
, &fb
, obj
);
4416 drm_gem_object_unreference_unlocked(obj
);
4423 static const struct drm_mode_config_funcs intel_mode_funcs
= {
4424 .fb_create
= intel_user_framebuffer_create
,
4425 .fb_changed
= intelfb_probe
,
4428 static struct drm_gem_object
*
4429 intel_alloc_power_context(struct drm_device
*dev
)
4431 struct drm_gem_object
*pwrctx
;
4434 pwrctx
= drm_gem_object_alloc(dev
, 4096);
4436 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
4440 mutex_lock(&dev
->struct_mutex
);
4441 ret
= i915_gem_object_pin(pwrctx
, 4096);
4443 DRM_ERROR("failed to pin power context: %d\n", ret
);
4447 ret
= i915_gem_object_set_to_gtt_domain(pwrctx
, 1);
4449 DRM_ERROR("failed to set-domain on power context: %d\n", ret
);
4452 mutex_unlock(&dev
->struct_mutex
);
4457 i915_gem_object_unpin(pwrctx
);
4459 drm_gem_object_unreference(pwrctx
);
4460 mutex_unlock(&dev
->struct_mutex
);
4464 void intel_init_clock_gating(struct drm_device
*dev
)
4466 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4469 * Disable clock gating reported to work incorrectly according to the
4470 * specs, but enable as much else as we can.
4472 if (IS_IRONLAKE(dev
)) {
4474 } else if (IS_G4X(dev
)) {
4475 uint32_t dspclk_gate
;
4476 I915_WRITE(RENCLK_GATE_D1
, 0);
4477 I915_WRITE(RENCLK_GATE_D2
, VF_UNIT_CLOCK_GATE_DISABLE
|
4478 GS_UNIT_CLOCK_GATE_DISABLE
|
4479 CL_UNIT_CLOCK_GATE_DISABLE
);
4480 I915_WRITE(RAMCLK_GATE_D
, 0);
4481 dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
|
4482 OVRUNIT_CLOCK_GATE_DISABLE
|
4483 OVCUNIT_CLOCK_GATE_DISABLE
;
4485 dspclk_gate
|= DSSUNIT_CLOCK_GATE_DISABLE
;
4486 I915_WRITE(DSPCLK_GATE_D
, dspclk_gate
);
4487 } else if (IS_I965GM(dev
)) {
4488 I915_WRITE(RENCLK_GATE_D1
, I965_RCC_CLOCK_GATE_DISABLE
);
4489 I915_WRITE(RENCLK_GATE_D2
, 0);
4490 I915_WRITE(DSPCLK_GATE_D
, 0);
4491 I915_WRITE(RAMCLK_GATE_D
, 0);
4492 I915_WRITE16(DEUC
, 0);
4493 } else if (IS_I965G(dev
)) {
4494 I915_WRITE(RENCLK_GATE_D1
, I965_RCZ_CLOCK_GATE_DISABLE
|
4495 I965_RCC_CLOCK_GATE_DISABLE
|
4496 I965_RCPB_CLOCK_GATE_DISABLE
|
4497 I965_ISC_CLOCK_GATE_DISABLE
|
4498 I965_FBC_CLOCK_GATE_DISABLE
);
4499 I915_WRITE(RENCLK_GATE_D2
, 0);
4500 } else if (IS_I9XX(dev
)) {
4501 u32 dstate
= I915_READ(D_STATE
);
4503 dstate
|= DSTATE_PLL_D3_OFF
| DSTATE_GFX_CLOCK_GATING
|
4504 DSTATE_DOT_CLOCK_GATING
;
4505 I915_WRITE(D_STATE
, dstate
);
4506 } else if (IS_I85X(dev
) || IS_I865G(dev
)) {
4507 I915_WRITE(RENCLK_GATE_D1
, SV_CLOCK_GATE_DISABLE
);
4508 } else if (IS_I830(dev
)) {
4509 I915_WRITE(DSPCLK_GATE_D
, OVRUNIT_CLOCK_GATE_DISABLE
);
4513 * GPU can automatically power down the render unit if given a page
4516 if (I915_HAS_RC6(dev
) && drm_core_check_feature(dev
, DRIVER_MODESET
)) {
4517 struct drm_i915_gem_object
*obj_priv
= NULL
;
4519 if (dev_priv
->pwrctx
) {
4520 obj_priv
= dev_priv
->pwrctx
->driver_private
;
4522 struct drm_gem_object
*pwrctx
;
4524 pwrctx
= intel_alloc_power_context(dev
);
4526 dev_priv
->pwrctx
= pwrctx
;
4527 obj_priv
= pwrctx
->driver_private
;
4532 I915_WRITE(PWRCTXA
, obj_priv
->gtt_offset
| PWRCTX_EN
);
4533 I915_WRITE(MCHBAR_RENDER_STANDBY
,
4534 I915_READ(MCHBAR_RENDER_STANDBY
) & ~RCX_SW_EXIT
);
4539 /* Set up chip specific display functions */
4540 static void intel_init_display(struct drm_device
*dev
)
4542 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4544 /* We always want a DPMS function */
4545 if (IS_IRONLAKE(dev
))
4546 dev_priv
->display
.dpms
= ironlake_crtc_dpms
;
4548 dev_priv
->display
.dpms
= i9xx_crtc_dpms
;
4550 /* Only mobile has FBC, leave pointers NULL for other chips */
4551 if (IS_MOBILE(dev
)) {
4553 dev_priv
->display
.fbc_enabled
= g4x_fbc_enabled
;
4554 dev_priv
->display
.enable_fbc
= g4x_enable_fbc
;
4555 dev_priv
->display
.disable_fbc
= g4x_disable_fbc
;
4556 } else if (IS_I965GM(dev
) || IS_I945GM(dev
) || IS_I915GM(dev
)) {
4557 dev_priv
->display
.fbc_enabled
= i8xx_fbc_enabled
;
4558 dev_priv
->display
.enable_fbc
= i8xx_enable_fbc
;
4559 dev_priv
->display
.disable_fbc
= i8xx_disable_fbc
;
4561 /* 855GM needs testing */
4564 /* Returns the core display clock speed */
4565 if (IS_I945G(dev
) || (IS_G33(dev
) && ! IS_PINEVIEW_M(dev
)))
4566 dev_priv
->display
.get_display_clock_speed
=
4567 i945_get_display_clock_speed
;
4568 else if (IS_I915G(dev
))
4569 dev_priv
->display
.get_display_clock_speed
=
4570 i915_get_display_clock_speed
;
4571 else if (IS_I945GM(dev
) || IS_845G(dev
) || IS_PINEVIEW_M(dev
))
4572 dev_priv
->display
.get_display_clock_speed
=
4573 i9xx_misc_get_display_clock_speed
;
4574 else if (IS_I915GM(dev
))
4575 dev_priv
->display
.get_display_clock_speed
=
4576 i915gm_get_display_clock_speed
;
4577 else if (IS_I865G(dev
))
4578 dev_priv
->display
.get_display_clock_speed
=
4579 i865_get_display_clock_speed
;
4580 else if (IS_I85X(dev
))
4581 dev_priv
->display
.get_display_clock_speed
=
4582 i855_get_display_clock_speed
;
4584 dev_priv
->display
.get_display_clock_speed
=
4585 i830_get_display_clock_speed
;
4587 /* For FIFO watermark updates */
4588 if (IS_IRONLAKE(dev
))
4589 dev_priv
->display
.update_wm
= NULL
;
4590 else if (IS_G4X(dev
))
4591 dev_priv
->display
.update_wm
= g4x_update_wm
;
4592 else if (IS_I965G(dev
))
4593 dev_priv
->display
.update_wm
= i965_update_wm
;
4594 else if (IS_I9XX(dev
) || IS_MOBILE(dev
)) {
4595 dev_priv
->display
.update_wm
= i9xx_update_wm
;
4596 dev_priv
->display
.get_fifo_size
= i9xx_get_fifo_size
;
4599 dev_priv
->display
.get_fifo_size
= i85x_get_fifo_size
;
4600 else if (IS_845G(dev
))
4601 dev_priv
->display
.get_fifo_size
= i845_get_fifo_size
;
4603 dev_priv
->display
.get_fifo_size
= i830_get_fifo_size
;
4604 dev_priv
->display
.update_wm
= i830_update_wm
;
4608 void intel_modeset_init(struct drm_device
*dev
)
4610 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4614 drm_mode_config_init(dev
);
4616 dev
->mode_config
.min_width
= 0;
4617 dev
->mode_config
.min_height
= 0;
4619 dev
->mode_config
.funcs
= (void *)&intel_mode_funcs
;
4621 intel_init_display(dev
);
4623 if (IS_I965G(dev
)) {
4624 dev
->mode_config
.max_width
= 8192;
4625 dev
->mode_config
.max_height
= 8192;
4626 } else if (IS_I9XX(dev
)) {
4627 dev
->mode_config
.max_width
= 4096;
4628 dev
->mode_config
.max_height
= 4096;
4630 dev
->mode_config
.max_width
= 2048;
4631 dev
->mode_config
.max_height
= 2048;
4634 /* set memory base */
4636 dev
->mode_config
.fb_base
= pci_resource_start(dev
->pdev
, 2);
4638 dev
->mode_config
.fb_base
= pci_resource_start(dev
->pdev
, 0);
4640 if (IS_MOBILE(dev
) || IS_I9XX(dev
))
4644 DRM_DEBUG_KMS("%d display pipe%s available.\n",
4645 num_pipe
, num_pipe
> 1 ? "s" : "");
4648 pci_read_config_word(dev
->pdev
, HPLLCC
, &dev_priv
->orig_clock
);
4649 else if (IS_I9XX(dev
) || IS_G4X(dev
))
4650 pci_read_config_word(dev
->pdev
, GCFGC
, &dev_priv
->orig_clock
);
4652 for (i
= 0; i
< num_pipe
; i
++) {
4653 intel_crtc_init(dev
, i
);
4656 intel_setup_outputs(dev
);
4658 intel_init_clock_gating(dev
);
4660 INIT_WORK(&dev_priv
->idle_work
, intel_idle_update
);
4661 setup_timer(&dev_priv
->idle_timer
, intel_gpu_idle_timer
,
4662 (unsigned long)dev
);
4664 intel_setup_overlay(dev
);
4666 if (IS_PINEVIEW(dev
) && !intel_get_cxsr_latency(IS_PINEVIEW_G(dev
),
4668 dev_priv
->mem_freq
))
4669 DRM_INFO("failed to find known CxSR latency "
4670 "(found fsb freq %d, mem freq %d), disabling CxSR\n",
4671 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
4674 void intel_modeset_cleanup(struct drm_device
*dev
)
4676 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4677 struct drm_crtc
*crtc
;
4678 struct intel_crtc
*intel_crtc
;
4680 mutex_lock(&dev
->struct_mutex
);
4682 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
4683 /* Skip inactive CRTCs */
4687 intel_crtc
= to_intel_crtc(crtc
);
4688 intel_increase_pllclock(crtc
, false);
4689 del_timer_sync(&intel_crtc
->idle_timer
);
4692 del_timer_sync(&dev_priv
->idle_timer
);
4694 if (dev_priv
->display
.disable_fbc
)
4695 dev_priv
->display
.disable_fbc(dev
);
4697 if (dev_priv
->pwrctx
) {
4698 struct drm_i915_gem_object
*obj_priv
;
4700 obj_priv
= dev_priv
->pwrctx
->driver_private
;
4701 I915_WRITE(PWRCTXA
, obj_priv
->gtt_offset
&~ PWRCTX_EN
);
4703 i915_gem_object_unpin(dev_priv
->pwrctx
);
4704 drm_gem_object_unreference(dev_priv
->pwrctx
);
4707 mutex_unlock(&dev
->struct_mutex
);
4709 drm_mode_config_cleanup(dev
);
4713 /* current intel driver doesn't take advantage of encoders
4714 always give back the encoder for the connector
4716 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
4718 struct intel_output
*intel_output
= to_intel_output(connector
);
4720 return &intel_output
->enc
;
4724 * set vga decode state - true == enable VGA decode
4726 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
4728 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4731 pci_read_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, &gmch_ctrl
);
4733 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
4735 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
4736 pci_write_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, gmch_ctrl
);