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drm/i915: Use a common function for computing the fb height alignment
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_rect.h>
44 #include <linux/dma_remapping.h>
45
46 /* Primary plane formats supported by all gen */
47 #define COMMON_PRIMARY_FORMATS \
48 DRM_FORMAT_C8, \
49 DRM_FORMAT_RGB565, \
50 DRM_FORMAT_XRGB8888, \
51 DRM_FORMAT_ARGB8888
52
53 /* Primary plane formats for gen <= 3 */
54 static const uint32_t intel_primary_formats_gen2[] = {
55 COMMON_PRIMARY_FORMATS,
56 DRM_FORMAT_XRGB1555,
57 DRM_FORMAT_ARGB1555,
58 };
59
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t intel_primary_formats_gen4[] = {
62 COMMON_PRIMARY_FORMATS, \
63 DRM_FORMAT_XBGR8888,
64 DRM_FORMAT_ABGR8888,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_ARGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 DRM_FORMAT_ABGR2101010,
69 };
70
71 /* Cursor formats */
72 static const uint32_t intel_cursor_formats[] = {
73 DRM_FORMAT_ARGB8888,
74 };
75
76 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
77
78 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
79 struct intel_crtc_state *pipe_config);
80 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
81 struct intel_crtc_state *pipe_config);
82
83 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
84 int x, int y, struct drm_framebuffer *old_fb);
85 static int intel_framebuffer_init(struct drm_device *dev,
86 struct intel_framebuffer *ifb,
87 struct drm_mode_fb_cmd2 *mode_cmd,
88 struct drm_i915_gem_object *obj);
89 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
90 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
91 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
92 struct intel_link_m_n *m_n,
93 struct intel_link_m_n *m2_n2);
94 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
95 static void haswell_set_pipeconf(struct drm_crtc *crtc);
96 static void intel_set_pipe_csc(struct drm_crtc *crtc);
97 static void vlv_prepare_pll(struct intel_crtc *crtc,
98 const struct intel_crtc_state *pipe_config);
99 static void chv_prepare_pll(struct intel_crtc *crtc,
100 const struct intel_crtc_state *pipe_config);
101 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
102 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
103
104 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
105 {
106 if (!connector->mst_port)
107 return connector->encoder;
108 else
109 return &connector->mst_port->mst_encoders[pipe]->base;
110 }
111
112 typedef struct {
113 int min, max;
114 } intel_range_t;
115
116 typedef struct {
117 int dot_limit;
118 int p2_slow, p2_fast;
119 } intel_p2_t;
120
121 typedef struct intel_limit intel_limit_t;
122 struct intel_limit {
123 intel_range_t dot, vco, n, m, m1, m2, p, p1;
124 intel_p2_t p2;
125 };
126
127 int
128 intel_pch_rawclk(struct drm_device *dev)
129 {
130 struct drm_i915_private *dev_priv = dev->dev_private;
131
132 WARN_ON(!HAS_PCH_SPLIT(dev));
133
134 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
135 }
136
137 static inline u32 /* units of 100MHz */
138 intel_fdi_link_freq(struct drm_device *dev)
139 {
140 if (IS_GEN5(dev)) {
141 struct drm_i915_private *dev_priv = dev->dev_private;
142 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
143 } else
144 return 27;
145 }
146
147 static const intel_limit_t intel_limits_i8xx_dac = {
148 .dot = { .min = 25000, .max = 350000 },
149 .vco = { .min = 908000, .max = 1512000 },
150 .n = { .min = 2, .max = 16 },
151 .m = { .min = 96, .max = 140 },
152 .m1 = { .min = 18, .max = 26 },
153 .m2 = { .min = 6, .max = 16 },
154 .p = { .min = 4, .max = 128 },
155 .p1 = { .min = 2, .max = 33 },
156 .p2 = { .dot_limit = 165000,
157 .p2_slow = 4, .p2_fast = 2 },
158 };
159
160 static const intel_limit_t intel_limits_i8xx_dvo = {
161 .dot = { .min = 25000, .max = 350000 },
162 .vco = { .min = 908000, .max = 1512000 },
163 .n = { .min = 2, .max = 16 },
164 .m = { .min = 96, .max = 140 },
165 .m1 = { .min = 18, .max = 26 },
166 .m2 = { .min = 6, .max = 16 },
167 .p = { .min = 4, .max = 128 },
168 .p1 = { .min = 2, .max = 33 },
169 .p2 = { .dot_limit = 165000,
170 .p2_slow = 4, .p2_fast = 4 },
171 };
172
173 static const intel_limit_t intel_limits_i8xx_lvds = {
174 .dot = { .min = 25000, .max = 350000 },
175 .vco = { .min = 908000, .max = 1512000 },
176 .n = { .min = 2, .max = 16 },
177 .m = { .min = 96, .max = 140 },
178 .m1 = { .min = 18, .max = 26 },
179 .m2 = { .min = 6, .max = 16 },
180 .p = { .min = 4, .max = 128 },
181 .p1 = { .min = 1, .max = 6 },
182 .p2 = { .dot_limit = 165000,
183 .p2_slow = 14, .p2_fast = 7 },
184 };
185
186 static const intel_limit_t intel_limits_i9xx_sdvo = {
187 .dot = { .min = 20000, .max = 400000 },
188 .vco = { .min = 1400000, .max = 2800000 },
189 .n = { .min = 1, .max = 6 },
190 .m = { .min = 70, .max = 120 },
191 .m1 = { .min = 8, .max = 18 },
192 .m2 = { .min = 3, .max = 7 },
193 .p = { .min = 5, .max = 80 },
194 .p1 = { .min = 1, .max = 8 },
195 .p2 = { .dot_limit = 200000,
196 .p2_slow = 10, .p2_fast = 5 },
197 };
198
199 static const intel_limit_t intel_limits_i9xx_lvds = {
200 .dot = { .min = 20000, .max = 400000 },
201 .vco = { .min = 1400000, .max = 2800000 },
202 .n = { .min = 1, .max = 6 },
203 .m = { .min = 70, .max = 120 },
204 .m1 = { .min = 8, .max = 18 },
205 .m2 = { .min = 3, .max = 7 },
206 .p = { .min = 7, .max = 98 },
207 .p1 = { .min = 1, .max = 8 },
208 .p2 = { .dot_limit = 112000,
209 .p2_slow = 14, .p2_fast = 7 },
210 };
211
212
213 static const intel_limit_t intel_limits_g4x_sdvo = {
214 .dot = { .min = 25000, .max = 270000 },
215 .vco = { .min = 1750000, .max = 3500000},
216 .n = { .min = 1, .max = 4 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 17, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 10, .max = 30 },
221 .p1 = { .min = 1, .max = 3},
222 .p2 = { .dot_limit = 270000,
223 .p2_slow = 10,
224 .p2_fast = 10
225 },
226 };
227
228 static const intel_limit_t intel_limits_g4x_hdmi = {
229 .dot = { .min = 22000, .max = 400000 },
230 .vco = { .min = 1750000, .max = 3500000},
231 .n = { .min = 1, .max = 4 },
232 .m = { .min = 104, .max = 138 },
233 .m1 = { .min = 16, .max = 23 },
234 .m2 = { .min = 5, .max = 11 },
235 .p = { .min = 5, .max = 80 },
236 .p1 = { .min = 1, .max = 8},
237 .p2 = { .dot_limit = 165000,
238 .p2_slow = 10, .p2_fast = 5 },
239 };
240
241 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
242 .dot = { .min = 20000, .max = 115000 },
243 .vco = { .min = 1750000, .max = 3500000 },
244 .n = { .min = 1, .max = 3 },
245 .m = { .min = 104, .max = 138 },
246 .m1 = { .min = 17, .max = 23 },
247 .m2 = { .min = 5, .max = 11 },
248 .p = { .min = 28, .max = 112 },
249 .p1 = { .min = 2, .max = 8 },
250 .p2 = { .dot_limit = 0,
251 .p2_slow = 14, .p2_fast = 14
252 },
253 };
254
255 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
256 .dot = { .min = 80000, .max = 224000 },
257 .vco = { .min = 1750000, .max = 3500000 },
258 .n = { .min = 1, .max = 3 },
259 .m = { .min = 104, .max = 138 },
260 .m1 = { .min = 17, .max = 23 },
261 .m2 = { .min = 5, .max = 11 },
262 .p = { .min = 14, .max = 42 },
263 .p1 = { .min = 2, .max = 6 },
264 .p2 = { .dot_limit = 0,
265 .p2_slow = 7, .p2_fast = 7
266 },
267 };
268
269 static const intel_limit_t intel_limits_pineview_sdvo = {
270 .dot = { .min = 20000, .max = 400000},
271 .vco = { .min = 1700000, .max = 3500000 },
272 /* Pineview's Ncounter is a ring counter */
273 .n = { .min = 3, .max = 6 },
274 .m = { .min = 2, .max = 256 },
275 /* Pineview only has one combined m divider, which we treat as m2. */
276 .m1 = { .min = 0, .max = 0 },
277 .m2 = { .min = 0, .max = 254 },
278 .p = { .min = 5, .max = 80 },
279 .p1 = { .min = 1, .max = 8 },
280 .p2 = { .dot_limit = 200000,
281 .p2_slow = 10, .p2_fast = 5 },
282 };
283
284 static const intel_limit_t intel_limits_pineview_lvds = {
285 .dot = { .min = 20000, .max = 400000 },
286 .vco = { .min = 1700000, .max = 3500000 },
287 .n = { .min = 3, .max = 6 },
288 .m = { .min = 2, .max = 256 },
289 .m1 = { .min = 0, .max = 0 },
290 .m2 = { .min = 0, .max = 254 },
291 .p = { .min = 7, .max = 112 },
292 .p1 = { .min = 1, .max = 8 },
293 .p2 = { .dot_limit = 112000,
294 .p2_slow = 14, .p2_fast = 14 },
295 };
296
297 /* Ironlake / Sandybridge
298 *
299 * We calculate clock using (register_value + 2) for N/M1/M2, so here
300 * the range value for them is (actual_value - 2).
301 */
302 static const intel_limit_t intel_limits_ironlake_dac = {
303 .dot = { .min = 25000, .max = 350000 },
304 .vco = { .min = 1760000, .max = 3510000 },
305 .n = { .min = 1, .max = 5 },
306 .m = { .min = 79, .max = 127 },
307 .m1 = { .min = 12, .max = 22 },
308 .m2 = { .min = 5, .max = 9 },
309 .p = { .min = 5, .max = 80 },
310 .p1 = { .min = 1, .max = 8 },
311 .p2 = { .dot_limit = 225000,
312 .p2_slow = 10, .p2_fast = 5 },
313 };
314
315 static const intel_limit_t intel_limits_ironlake_single_lvds = {
316 .dot = { .min = 25000, .max = 350000 },
317 .vco = { .min = 1760000, .max = 3510000 },
318 .n = { .min = 1, .max = 3 },
319 .m = { .min = 79, .max = 118 },
320 .m1 = { .min = 12, .max = 22 },
321 .m2 = { .min = 5, .max = 9 },
322 .p = { .min = 28, .max = 112 },
323 .p1 = { .min = 2, .max = 8 },
324 .p2 = { .dot_limit = 225000,
325 .p2_slow = 14, .p2_fast = 14 },
326 };
327
328 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
329 .dot = { .min = 25000, .max = 350000 },
330 .vco = { .min = 1760000, .max = 3510000 },
331 .n = { .min = 1, .max = 3 },
332 .m = { .min = 79, .max = 127 },
333 .m1 = { .min = 12, .max = 22 },
334 .m2 = { .min = 5, .max = 9 },
335 .p = { .min = 14, .max = 56 },
336 .p1 = { .min = 2, .max = 8 },
337 .p2 = { .dot_limit = 225000,
338 .p2_slow = 7, .p2_fast = 7 },
339 };
340
341 /* LVDS 100mhz refclk limits. */
342 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
343 .dot = { .min = 25000, .max = 350000 },
344 .vco = { .min = 1760000, .max = 3510000 },
345 .n = { .min = 1, .max = 2 },
346 .m = { .min = 79, .max = 126 },
347 .m1 = { .min = 12, .max = 22 },
348 .m2 = { .min = 5, .max = 9 },
349 .p = { .min = 28, .max = 112 },
350 .p1 = { .min = 2, .max = 8 },
351 .p2 = { .dot_limit = 225000,
352 .p2_slow = 14, .p2_fast = 14 },
353 };
354
355 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
356 .dot = { .min = 25000, .max = 350000 },
357 .vco = { .min = 1760000, .max = 3510000 },
358 .n = { .min = 1, .max = 3 },
359 .m = { .min = 79, .max = 126 },
360 .m1 = { .min = 12, .max = 22 },
361 .m2 = { .min = 5, .max = 9 },
362 .p = { .min = 14, .max = 42 },
363 .p1 = { .min = 2, .max = 6 },
364 .p2 = { .dot_limit = 225000,
365 .p2_slow = 7, .p2_fast = 7 },
366 };
367
368 static const intel_limit_t intel_limits_vlv = {
369 /*
370 * These are the data rate limits (measured in fast clocks)
371 * since those are the strictest limits we have. The fast
372 * clock and actual rate limits are more relaxed, so checking
373 * them would make no difference.
374 */
375 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
376 .vco = { .min = 4000000, .max = 6000000 },
377 .n = { .min = 1, .max = 7 },
378 .m1 = { .min = 2, .max = 3 },
379 .m2 = { .min = 11, .max = 156 },
380 .p1 = { .min = 2, .max = 3 },
381 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
382 };
383
384 static const intel_limit_t intel_limits_chv = {
385 /*
386 * These are the data rate limits (measured in fast clocks)
387 * since those are the strictest limits we have. The fast
388 * clock and actual rate limits are more relaxed, so checking
389 * them would make no difference.
390 */
391 .dot = { .min = 25000 * 5, .max = 540000 * 5},
392 .vco = { .min = 4860000, .max = 6700000 },
393 .n = { .min = 1, .max = 1 },
394 .m1 = { .min = 2, .max = 2 },
395 .m2 = { .min = 24 << 22, .max = 175 << 22 },
396 .p1 = { .min = 2, .max = 4 },
397 .p2 = { .p2_slow = 1, .p2_fast = 14 },
398 };
399
400 static void vlv_clock(int refclk, intel_clock_t *clock)
401 {
402 clock->m = clock->m1 * clock->m2;
403 clock->p = clock->p1 * clock->p2;
404 if (WARN_ON(clock->n == 0 || clock->p == 0))
405 return;
406 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
407 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
408 }
409
410 /**
411 * Returns whether any output on the specified pipe is of the specified type
412 */
413 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
414 {
415 struct drm_device *dev = crtc->base.dev;
416 struct intel_encoder *encoder;
417
418 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
419 if (encoder->type == type)
420 return true;
421
422 return false;
423 }
424
425 /**
426 * Returns whether any output on the specified pipe will have the specified
427 * type after a staged modeset is complete, i.e., the same as
428 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
429 * encoder->crtc.
430 */
431 static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
432 {
433 struct drm_device *dev = crtc->base.dev;
434 struct intel_encoder *encoder;
435
436 for_each_intel_encoder(dev, encoder)
437 if (encoder->new_crtc == crtc && encoder->type == type)
438 return true;
439
440 return false;
441 }
442
443 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
444 int refclk)
445 {
446 struct drm_device *dev = crtc->base.dev;
447 const intel_limit_t *limit;
448
449 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
450 if (intel_is_dual_link_lvds(dev)) {
451 if (refclk == 100000)
452 limit = &intel_limits_ironlake_dual_lvds_100m;
453 else
454 limit = &intel_limits_ironlake_dual_lvds;
455 } else {
456 if (refclk == 100000)
457 limit = &intel_limits_ironlake_single_lvds_100m;
458 else
459 limit = &intel_limits_ironlake_single_lvds;
460 }
461 } else
462 limit = &intel_limits_ironlake_dac;
463
464 return limit;
465 }
466
467 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
468 {
469 struct drm_device *dev = crtc->base.dev;
470 const intel_limit_t *limit;
471
472 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
473 if (intel_is_dual_link_lvds(dev))
474 limit = &intel_limits_g4x_dual_channel_lvds;
475 else
476 limit = &intel_limits_g4x_single_channel_lvds;
477 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
478 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
479 limit = &intel_limits_g4x_hdmi;
480 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
481 limit = &intel_limits_g4x_sdvo;
482 } else /* The option is for other outputs */
483 limit = &intel_limits_i9xx_sdvo;
484
485 return limit;
486 }
487
488 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
489 {
490 struct drm_device *dev = crtc->base.dev;
491 const intel_limit_t *limit;
492
493 if (HAS_PCH_SPLIT(dev))
494 limit = intel_ironlake_limit(crtc, refclk);
495 else if (IS_G4X(dev)) {
496 limit = intel_g4x_limit(crtc);
497 } else if (IS_PINEVIEW(dev)) {
498 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
499 limit = &intel_limits_pineview_lvds;
500 else
501 limit = &intel_limits_pineview_sdvo;
502 } else if (IS_CHERRYVIEW(dev)) {
503 limit = &intel_limits_chv;
504 } else if (IS_VALLEYVIEW(dev)) {
505 limit = &intel_limits_vlv;
506 } else if (!IS_GEN2(dev)) {
507 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
508 limit = &intel_limits_i9xx_lvds;
509 else
510 limit = &intel_limits_i9xx_sdvo;
511 } else {
512 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
513 limit = &intel_limits_i8xx_lvds;
514 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
515 limit = &intel_limits_i8xx_dvo;
516 else
517 limit = &intel_limits_i8xx_dac;
518 }
519 return limit;
520 }
521
522 /* m1 is reserved as 0 in Pineview, n is a ring counter */
523 static void pineview_clock(int refclk, intel_clock_t *clock)
524 {
525 clock->m = clock->m2 + 2;
526 clock->p = clock->p1 * clock->p2;
527 if (WARN_ON(clock->n == 0 || clock->p == 0))
528 return;
529 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
530 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
531 }
532
533 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
534 {
535 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
536 }
537
538 static void i9xx_clock(int refclk, intel_clock_t *clock)
539 {
540 clock->m = i9xx_dpll_compute_m(clock);
541 clock->p = clock->p1 * clock->p2;
542 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
543 return;
544 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
545 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
546 }
547
548 static void chv_clock(int refclk, intel_clock_t *clock)
549 {
550 clock->m = clock->m1 * clock->m2;
551 clock->p = clock->p1 * clock->p2;
552 if (WARN_ON(clock->n == 0 || clock->p == 0))
553 return;
554 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
555 clock->n << 22);
556 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
557 }
558
559 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
560 /**
561 * Returns whether the given set of divisors are valid for a given refclk with
562 * the given connectors.
563 */
564
565 static bool intel_PLL_is_valid(struct drm_device *dev,
566 const intel_limit_t *limit,
567 const intel_clock_t *clock)
568 {
569 if (clock->n < limit->n.min || limit->n.max < clock->n)
570 INTELPllInvalid("n out of range\n");
571 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
572 INTELPllInvalid("p1 out of range\n");
573 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
574 INTELPllInvalid("m2 out of range\n");
575 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
576 INTELPllInvalid("m1 out of range\n");
577
578 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
579 if (clock->m1 <= clock->m2)
580 INTELPllInvalid("m1 <= m2\n");
581
582 if (!IS_VALLEYVIEW(dev)) {
583 if (clock->p < limit->p.min || limit->p.max < clock->p)
584 INTELPllInvalid("p out of range\n");
585 if (clock->m < limit->m.min || limit->m.max < clock->m)
586 INTELPllInvalid("m out of range\n");
587 }
588
589 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
590 INTELPllInvalid("vco out of range\n");
591 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
592 * connector, etc., rather than just a single range.
593 */
594 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
595 INTELPllInvalid("dot out of range\n");
596
597 return true;
598 }
599
600 static bool
601 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
602 int target, int refclk, intel_clock_t *match_clock,
603 intel_clock_t *best_clock)
604 {
605 struct drm_device *dev = crtc->base.dev;
606 intel_clock_t clock;
607 int err = target;
608
609 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
610 /*
611 * For LVDS just rely on its current settings for dual-channel.
612 * We haven't figured out how to reliably set up different
613 * single/dual channel state, if we even can.
614 */
615 if (intel_is_dual_link_lvds(dev))
616 clock.p2 = limit->p2.p2_fast;
617 else
618 clock.p2 = limit->p2.p2_slow;
619 } else {
620 if (target < limit->p2.dot_limit)
621 clock.p2 = limit->p2.p2_slow;
622 else
623 clock.p2 = limit->p2.p2_fast;
624 }
625
626 memset(best_clock, 0, sizeof(*best_clock));
627
628 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
629 clock.m1++) {
630 for (clock.m2 = limit->m2.min;
631 clock.m2 <= limit->m2.max; clock.m2++) {
632 if (clock.m2 >= clock.m1)
633 break;
634 for (clock.n = limit->n.min;
635 clock.n <= limit->n.max; clock.n++) {
636 for (clock.p1 = limit->p1.min;
637 clock.p1 <= limit->p1.max; clock.p1++) {
638 int this_err;
639
640 i9xx_clock(refclk, &clock);
641 if (!intel_PLL_is_valid(dev, limit,
642 &clock))
643 continue;
644 if (match_clock &&
645 clock.p != match_clock->p)
646 continue;
647
648 this_err = abs(clock.dot - target);
649 if (this_err < err) {
650 *best_clock = clock;
651 err = this_err;
652 }
653 }
654 }
655 }
656 }
657
658 return (err != target);
659 }
660
661 static bool
662 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
663 int target, int refclk, intel_clock_t *match_clock,
664 intel_clock_t *best_clock)
665 {
666 struct drm_device *dev = crtc->base.dev;
667 intel_clock_t clock;
668 int err = target;
669
670 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
671 /*
672 * For LVDS just rely on its current settings for dual-channel.
673 * We haven't figured out how to reliably set up different
674 * single/dual channel state, if we even can.
675 */
676 if (intel_is_dual_link_lvds(dev))
677 clock.p2 = limit->p2.p2_fast;
678 else
679 clock.p2 = limit->p2.p2_slow;
680 } else {
681 if (target < limit->p2.dot_limit)
682 clock.p2 = limit->p2.p2_slow;
683 else
684 clock.p2 = limit->p2.p2_fast;
685 }
686
687 memset(best_clock, 0, sizeof(*best_clock));
688
689 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
690 clock.m1++) {
691 for (clock.m2 = limit->m2.min;
692 clock.m2 <= limit->m2.max; clock.m2++) {
693 for (clock.n = limit->n.min;
694 clock.n <= limit->n.max; clock.n++) {
695 for (clock.p1 = limit->p1.min;
696 clock.p1 <= limit->p1.max; clock.p1++) {
697 int this_err;
698
699 pineview_clock(refclk, &clock);
700 if (!intel_PLL_is_valid(dev, limit,
701 &clock))
702 continue;
703 if (match_clock &&
704 clock.p != match_clock->p)
705 continue;
706
707 this_err = abs(clock.dot - target);
708 if (this_err < err) {
709 *best_clock = clock;
710 err = this_err;
711 }
712 }
713 }
714 }
715 }
716
717 return (err != target);
718 }
719
720 static bool
721 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
722 int target, int refclk, intel_clock_t *match_clock,
723 intel_clock_t *best_clock)
724 {
725 struct drm_device *dev = crtc->base.dev;
726 intel_clock_t clock;
727 int max_n;
728 bool found;
729 /* approximately equals target * 0.00585 */
730 int err_most = (target >> 8) + (target >> 9);
731 found = false;
732
733 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
734 if (intel_is_dual_link_lvds(dev))
735 clock.p2 = limit->p2.p2_fast;
736 else
737 clock.p2 = limit->p2.p2_slow;
738 } else {
739 if (target < limit->p2.dot_limit)
740 clock.p2 = limit->p2.p2_slow;
741 else
742 clock.p2 = limit->p2.p2_fast;
743 }
744
745 memset(best_clock, 0, sizeof(*best_clock));
746 max_n = limit->n.max;
747 /* based on hardware requirement, prefer smaller n to precision */
748 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
749 /* based on hardware requirement, prefere larger m1,m2 */
750 for (clock.m1 = limit->m1.max;
751 clock.m1 >= limit->m1.min; clock.m1--) {
752 for (clock.m2 = limit->m2.max;
753 clock.m2 >= limit->m2.min; clock.m2--) {
754 for (clock.p1 = limit->p1.max;
755 clock.p1 >= limit->p1.min; clock.p1--) {
756 int this_err;
757
758 i9xx_clock(refclk, &clock);
759 if (!intel_PLL_is_valid(dev, limit,
760 &clock))
761 continue;
762
763 this_err = abs(clock.dot - target);
764 if (this_err < err_most) {
765 *best_clock = clock;
766 err_most = this_err;
767 max_n = clock.n;
768 found = true;
769 }
770 }
771 }
772 }
773 }
774 return found;
775 }
776
777 static bool
778 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
779 int target, int refclk, intel_clock_t *match_clock,
780 intel_clock_t *best_clock)
781 {
782 struct drm_device *dev = crtc->base.dev;
783 intel_clock_t clock;
784 unsigned int bestppm = 1000000;
785 /* min update 19.2 MHz */
786 int max_n = min(limit->n.max, refclk / 19200);
787 bool found = false;
788
789 target *= 5; /* fast clock */
790
791 memset(best_clock, 0, sizeof(*best_clock));
792
793 /* based on hardware requirement, prefer smaller n to precision */
794 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
795 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
796 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
797 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
798 clock.p = clock.p1 * clock.p2;
799 /* based on hardware requirement, prefer bigger m1,m2 values */
800 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
801 unsigned int ppm, diff;
802
803 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
804 refclk * clock.m1);
805
806 vlv_clock(refclk, &clock);
807
808 if (!intel_PLL_is_valid(dev, limit,
809 &clock))
810 continue;
811
812 diff = abs(clock.dot - target);
813 ppm = div_u64(1000000ULL * diff, target);
814
815 if (ppm < 100 && clock.p > best_clock->p) {
816 bestppm = 0;
817 *best_clock = clock;
818 found = true;
819 }
820
821 if (bestppm >= 10 && ppm < bestppm - 10) {
822 bestppm = ppm;
823 *best_clock = clock;
824 found = true;
825 }
826 }
827 }
828 }
829 }
830
831 return found;
832 }
833
834 static bool
835 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
836 int target, int refclk, intel_clock_t *match_clock,
837 intel_clock_t *best_clock)
838 {
839 struct drm_device *dev = crtc->base.dev;
840 intel_clock_t clock;
841 uint64_t m2;
842 int found = false;
843
844 memset(best_clock, 0, sizeof(*best_clock));
845
846 /*
847 * Based on hardware doc, the n always set to 1, and m1 always
848 * set to 2. If requires to support 200Mhz refclk, we need to
849 * revisit this because n may not 1 anymore.
850 */
851 clock.n = 1, clock.m1 = 2;
852 target *= 5; /* fast clock */
853
854 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
855 for (clock.p2 = limit->p2.p2_fast;
856 clock.p2 >= limit->p2.p2_slow;
857 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
858
859 clock.p = clock.p1 * clock.p2;
860
861 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
862 clock.n) << 22, refclk * clock.m1);
863
864 if (m2 > INT_MAX/clock.m1)
865 continue;
866
867 clock.m2 = m2;
868
869 chv_clock(refclk, &clock);
870
871 if (!intel_PLL_is_valid(dev, limit, &clock))
872 continue;
873
874 /* based on hardware requirement, prefer bigger p
875 */
876 if (clock.p > best_clock->p) {
877 *best_clock = clock;
878 found = true;
879 }
880 }
881 }
882
883 return found;
884 }
885
886 bool intel_crtc_active(struct drm_crtc *crtc)
887 {
888 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
889
890 /* Be paranoid as we can arrive here with only partial
891 * state retrieved from the hardware during setup.
892 *
893 * We can ditch the adjusted_mode.crtc_clock check as soon
894 * as Haswell has gained clock readout/fastboot support.
895 *
896 * We can ditch the crtc->primary->fb check as soon as we can
897 * properly reconstruct framebuffers.
898 */
899 return intel_crtc->active && crtc->primary->fb &&
900 intel_crtc->config->base.adjusted_mode.crtc_clock;
901 }
902
903 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
904 enum pipe pipe)
905 {
906 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
907 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
908
909 return intel_crtc->config->cpu_transcoder;
910 }
911
912 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
913 {
914 struct drm_i915_private *dev_priv = dev->dev_private;
915 u32 reg = PIPEDSL(pipe);
916 u32 line1, line2;
917 u32 line_mask;
918
919 if (IS_GEN2(dev))
920 line_mask = DSL_LINEMASK_GEN2;
921 else
922 line_mask = DSL_LINEMASK_GEN3;
923
924 line1 = I915_READ(reg) & line_mask;
925 mdelay(5);
926 line2 = I915_READ(reg) & line_mask;
927
928 return line1 == line2;
929 }
930
931 /*
932 * intel_wait_for_pipe_off - wait for pipe to turn off
933 * @crtc: crtc whose pipe to wait for
934 *
935 * After disabling a pipe, we can't wait for vblank in the usual way,
936 * spinning on the vblank interrupt status bit, since we won't actually
937 * see an interrupt when the pipe is disabled.
938 *
939 * On Gen4 and above:
940 * wait for the pipe register state bit to turn off
941 *
942 * Otherwise:
943 * wait for the display line value to settle (it usually
944 * ends up stopping at the start of the next frame).
945 *
946 */
947 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
948 {
949 struct drm_device *dev = crtc->base.dev;
950 struct drm_i915_private *dev_priv = dev->dev_private;
951 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
952 enum pipe pipe = crtc->pipe;
953
954 if (INTEL_INFO(dev)->gen >= 4) {
955 int reg = PIPECONF(cpu_transcoder);
956
957 /* Wait for the Pipe State to go off */
958 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
959 100))
960 WARN(1, "pipe_off wait timed out\n");
961 } else {
962 /* Wait for the display line to settle */
963 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
964 WARN(1, "pipe_off wait timed out\n");
965 }
966 }
967
968 /*
969 * ibx_digital_port_connected - is the specified port connected?
970 * @dev_priv: i915 private structure
971 * @port: the port to test
972 *
973 * Returns true if @port is connected, false otherwise.
974 */
975 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
976 struct intel_digital_port *port)
977 {
978 u32 bit;
979
980 if (HAS_PCH_IBX(dev_priv->dev)) {
981 switch (port->port) {
982 case PORT_B:
983 bit = SDE_PORTB_HOTPLUG;
984 break;
985 case PORT_C:
986 bit = SDE_PORTC_HOTPLUG;
987 break;
988 case PORT_D:
989 bit = SDE_PORTD_HOTPLUG;
990 break;
991 default:
992 return true;
993 }
994 } else {
995 switch (port->port) {
996 case PORT_B:
997 bit = SDE_PORTB_HOTPLUG_CPT;
998 break;
999 case PORT_C:
1000 bit = SDE_PORTC_HOTPLUG_CPT;
1001 break;
1002 case PORT_D:
1003 bit = SDE_PORTD_HOTPLUG_CPT;
1004 break;
1005 default:
1006 return true;
1007 }
1008 }
1009
1010 return I915_READ(SDEISR) & bit;
1011 }
1012
1013 static const char *state_string(bool enabled)
1014 {
1015 return enabled ? "on" : "off";
1016 }
1017
1018 /* Only for pre-ILK configs */
1019 void assert_pll(struct drm_i915_private *dev_priv,
1020 enum pipe pipe, bool state)
1021 {
1022 int reg;
1023 u32 val;
1024 bool cur_state;
1025
1026 reg = DPLL(pipe);
1027 val = I915_READ(reg);
1028 cur_state = !!(val & DPLL_VCO_ENABLE);
1029 I915_STATE_WARN(cur_state != state,
1030 "PLL state assertion failure (expected %s, current %s)\n",
1031 state_string(state), state_string(cur_state));
1032 }
1033
1034 /* XXX: the dsi pll is shared between MIPI DSI ports */
1035 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1036 {
1037 u32 val;
1038 bool cur_state;
1039
1040 mutex_lock(&dev_priv->dpio_lock);
1041 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1042 mutex_unlock(&dev_priv->dpio_lock);
1043
1044 cur_state = val & DSI_PLL_VCO_EN;
1045 I915_STATE_WARN(cur_state != state,
1046 "DSI PLL state assertion failure (expected %s, current %s)\n",
1047 state_string(state), state_string(cur_state));
1048 }
1049 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1050 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1051
1052 struct intel_shared_dpll *
1053 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1054 {
1055 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1056
1057 if (crtc->config->shared_dpll < 0)
1058 return NULL;
1059
1060 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1061 }
1062
1063 /* For ILK+ */
1064 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1065 struct intel_shared_dpll *pll,
1066 bool state)
1067 {
1068 bool cur_state;
1069 struct intel_dpll_hw_state hw_state;
1070
1071 if (WARN (!pll,
1072 "asserting DPLL %s with no DPLL\n", state_string(state)))
1073 return;
1074
1075 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1076 I915_STATE_WARN(cur_state != state,
1077 "%s assertion failure (expected %s, current %s)\n",
1078 pll->name, state_string(state), state_string(cur_state));
1079 }
1080
1081 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1082 enum pipe pipe, bool state)
1083 {
1084 int reg;
1085 u32 val;
1086 bool cur_state;
1087 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1088 pipe);
1089
1090 if (HAS_DDI(dev_priv->dev)) {
1091 /* DDI does not have a specific FDI_TX register */
1092 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1093 val = I915_READ(reg);
1094 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1095 } else {
1096 reg = FDI_TX_CTL(pipe);
1097 val = I915_READ(reg);
1098 cur_state = !!(val & FDI_TX_ENABLE);
1099 }
1100 I915_STATE_WARN(cur_state != state,
1101 "FDI TX state assertion failure (expected %s, current %s)\n",
1102 state_string(state), state_string(cur_state));
1103 }
1104 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1105 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1106
1107 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1108 enum pipe pipe, bool state)
1109 {
1110 int reg;
1111 u32 val;
1112 bool cur_state;
1113
1114 reg = FDI_RX_CTL(pipe);
1115 val = I915_READ(reg);
1116 cur_state = !!(val & FDI_RX_ENABLE);
1117 I915_STATE_WARN(cur_state != state,
1118 "FDI RX state assertion failure (expected %s, current %s)\n",
1119 state_string(state), state_string(cur_state));
1120 }
1121 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1122 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1123
1124 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1125 enum pipe pipe)
1126 {
1127 int reg;
1128 u32 val;
1129
1130 /* ILK FDI PLL is always enabled */
1131 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1132 return;
1133
1134 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1135 if (HAS_DDI(dev_priv->dev))
1136 return;
1137
1138 reg = FDI_TX_CTL(pipe);
1139 val = I915_READ(reg);
1140 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1141 }
1142
1143 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1144 enum pipe pipe, bool state)
1145 {
1146 int reg;
1147 u32 val;
1148 bool cur_state;
1149
1150 reg = FDI_RX_CTL(pipe);
1151 val = I915_READ(reg);
1152 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1153 I915_STATE_WARN(cur_state != state,
1154 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1155 state_string(state), state_string(cur_state));
1156 }
1157
1158 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1159 enum pipe pipe)
1160 {
1161 struct drm_device *dev = dev_priv->dev;
1162 int pp_reg;
1163 u32 val;
1164 enum pipe panel_pipe = PIPE_A;
1165 bool locked = true;
1166
1167 if (WARN_ON(HAS_DDI(dev)))
1168 return;
1169
1170 if (HAS_PCH_SPLIT(dev)) {
1171 u32 port_sel;
1172
1173 pp_reg = PCH_PP_CONTROL;
1174 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1175
1176 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1177 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1178 panel_pipe = PIPE_B;
1179 /* XXX: else fix for eDP */
1180 } else if (IS_VALLEYVIEW(dev)) {
1181 /* presumably write lock depends on pipe, not port select */
1182 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1183 panel_pipe = pipe;
1184 } else {
1185 pp_reg = PP_CONTROL;
1186 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1187 panel_pipe = PIPE_B;
1188 }
1189
1190 val = I915_READ(pp_reg);
1191 if (!(val & PANEL_POWER_ON) ||
1192 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1193 locked = false;
1194
1195 I915_STATE_WARN(panel_pipe == pipe && locked,
1196 "panel assertion failure, pipe %c regs locked\n",
1197 pipe_name(pipe));
1198 }
1199
1200 static void assert_cursor(struct drm_i915_private *dev_priv,
1201 enum pipe pipe, bool state)
1202 {
1203 struct drm_device *dev = dev_priv->dev;
1204 bool cur_state;
1205
1206 if (IS_845G(dev) || IS_I865G(dev))
1207 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1208 else
1209 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1210
1211 I915_STATE_WARN(cur_state != state,
1212 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1213 pipe_name(pipe), state_string(state), state_string(cur_state));
1214 }
1215 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1216 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1217
1218 void assert_pipe(struct drm_i915_private *dev_priv,
1219 enum pipe pipe, bool state)
1220 {
1221 int reg;
1222 u32 val;
1223 bool cur_state;
1224 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1225 pipe);
1226
1227 /* if we need the pipe quirk it must be always on */
1228 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1229 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1230 state = true;
1231
1232 if (!intel_display_power_is_enabled(dev_priv,
1233 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1234 cur_state = false;
1235 } else {
1236 reg = PIPECONF(cpu_transcoder);
1237 val = I915_READ(reg);
1238 cur_state = !!(val & PIPECONF_ENABLE);
1239 }
1240
1241 I915_STATE_WARN(cur_state != state,
1242 "pipe %c assertion failure (expected %s, current %s)\n",
1243 pipe_name(pipe), state_string(state), state_string(cur_state));
1244 }
1245
1246 static void assert_plane(struct drm_i915_private *dev_priv,
1247 enum plane plane, bool state)
1248 {
1249 int reg;
1250 u32 val;
1251 bool cur_state;
1252
1253 reg = DSPCNTR(plane);
1254 val = I915_READ(reg);
1255 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1256 I915_STATE_WARN(cur_state != state,
1257 "plane %c assertion failure (expected %s, current %s)\n",
1258 plane_name(plane), state_string(state), state_string(cur_state));
1259 }
1260
1261 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1262 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1263
1264 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1265 enum pipe pipe)
1266 {
1267 struct drm_device *dev = dev_priv->dev;
1268 int reg, i;
1269 u32 val;
1270 int cur_pipe;
1271
1272 /* Primary planes are fixed to pipes on gen4+ */
1273 if (INTEL_INFO(dev)->gen >= 4) {
1274 reg = DSPCNTR(pipe);
1275 val = I915_READ(reg);
1276 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1277 "plane %c assertion failure, should be disabled but not\n",
1278 plane_name(pipe));
1279 return;
1280 }
1281
1282 /* Need to check both planes against the pipe */
1283 for_each_pipe(dev_priv, i) {
1284 reg = DSPCNTR(i);
1285 val = I915_READ(reg);
1286 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1287 DISPPLANE_SEL_PIPE_SHIFT;
1288 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1289 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1290 plane_name(i), pipe_name(pipe));
1291 }
1292 }
1293
1294 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1295 enum pipe pipe)
1296 {
1297 struct drm_device *dev = dev_priv->dev;
1298 int reg, sprite;
1299 u32 val;
1300
1301 if (INTEL_INFO(dev)->gen >= 9) {
1302 for_each_sprite(pipe, sprite) {
1303 val = I915_READ(PLANE_CTL(pipe, sprite));
1304 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1305 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1306 sprite, pipe_name(pipe));
1307 }
1308 } else if (IS_VALLEYVIEW(dev)) {
1309 for_each_sprite(pipe, sprite) {
1310 reg = SPCNTR(pipe, sprite);
1311 val = I915_READ(reg);
1312 I915_STATE_WARN(val & SP_ENABLE,
1313 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1314 sprite_name(pipe, sprite), pipe_name(pipe));
1315 }
1316 } else if (INTEL_INFO(dev)->gen >= 7) {
1317 reg = SPRCTL(pipe);
1318 val = I915_READ(reg);
1319 I915_STATE_WARN(val & SPRITE_ENABLE,
1320 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1321 plane_name(pipe), pipe_name(pipe));
1322 } else if (INTEL_INFO(dev)->gen >= 5) {
1323 reg = DVSCNTR(pipe);
1324 val = I915_READ(reg);
1325 I915_STATE_WARN(val & DVS_ENABLE,
1326 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1327 plane_name(pipe), pipe_name(pipe));
1328 }
1329 }
1330
1331 static void assert_vblank_disabled(struct drm_crtc *crtc)
1332 {
1333 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1334 drm_crtc_vblank_put(crtc);
1335 }
1336
1337 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1338 {
1339 u32 val;
1340 bool enabled;
1341
1342 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1343
1344 val = I915_READ(PCH_DREF_CONTROL);
1345 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1346 DREF_SUPERSPREAD_SOURCE_MASK));
1347 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1348 }
1349
1350 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1351 enum pipe pipe)
1352 {
1353 int reg;
1354 u32 val;
1355 bool enabled;
1356
1357 reg = PCH_TRANSCONF(pipe);
1358 val = I915_READ(reg);
1359 enabled = !!(val & TRANS_ENABLE);
1360 I915_STATE_WARN(enabled,
1361 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1362 pipe_name(pipe));
1363 }
1364
1365 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1366 enum pipe pipe, u32 port_sel, u32 val)
1367 {
1368 if ((val & DP_PORT_EN) == 0)
1369 return false;
1370
1371 if (HAS_PCH_CPT(dev_priv->dev)) {
1372 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1373 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1374 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1375 return false;
1376 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1377 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1378 return false;
1379 } else {
1380 if ((val & DP_PIPE_MASK) != (pipe << 30))
1381 return false;
1382 }
1383 return true;
1384 }
1385
1386 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1387 enum pipe pipe, u32 val)
1388 {
1389 if ((val & SDVO_ENABLE) == 0)
1390 return false;
1391
1392 if (HAS_PCH_CPT(dev_priv->dev)) {
1393 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1394 return false;
1395 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1396 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1397 return false;
1398 } else {
1399 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1400 return false;
1401 }
1402 return true;
1403 }
1404
1405 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1406 enum pipe pipe, u32 val)
1407 {
1408 if ((val & LVDS_PORT_EN) == 0)
1409 return false;
1410
1411 if (HAS_PCH_CPT(dev_priv->dev)) {
1412 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1413 return false;
1414 } else {
1415 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1416 return false;
1417 }
1418 return true;
1419 }
1420
1421 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1422 enum pipe pipe, u32 val)
1423 {
1424 if ((val & ADPA_DAC_ENABLE) == 0)
1425 return false;
1426 if (HAS_PCH_CPT(dev_priv->dev)) {
1427 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1428 return false;
1429 } else {
1430 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1431 return false;
1432 }
1433 return true;
1434 }
1435
1436 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1437 enum pipe pipe, int reg, u32 port_sel)
1438 {
1439 u32 val = I915_READ(reg);
1440 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1441 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1442 reg, pipe_name(pipe));
1443
1444 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1445 && (val & DP_PIPEB_SELECT),
1446 "IBX PCH dp port still using transcoder B\n");
1447 }
1448
1449 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1450 enum pipe pipe, int reg)
1451 {
1452 u32 val = I915_READ(reg);
1453 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1454 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1455 reg, pipe_name(pipe));
1456
1457 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1458 && (val & SDVO_PIPE_B_SELECT),
1459 "IBX PCH hdmi port still using transcoder B\n");
1460 }
1461
1462 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1463 enum pipe pipe)
1464 {
1465 int reg;
1466 u32 val;
1467
1468 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1469 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1470 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1471
1472 reg = PCH_ADPA;
1473 val = I915_READ(reg);
1474 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1475 "PCH VGA enabled on transcoder %c, should be disabled\n",
1476 pipe_name(pipe));
1477
1478 reg = PCH_LVDS;
1479 val = I915_READ(reg);
1480 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1481 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1482 pipe_name(pipe));
1483
1484 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1485 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1486 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1487 }
1488
1489 static void intel_init_dpio(struct drm_device *dev)
1490 {
1491 struct drm_i915_private *dev_priv = dev->dev_private;
1492
1493 if (!IS_VALLEYVIEW(dev))
1494 return;
1495
1496 /*
1497 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1498 * CHV x1 PHY (DP/HDMI D)
1499 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1500 */
1501 if (IS_CHERRYVIEW(dev)) {
1502 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1503 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1504 } else {
1505 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1506 }
1507 }
1508
1509 static void vlv_enable_pll(struct intel_crtc *crtc,
1510 const struct intel_crtc_state *pipe_config)
1511 {
1512 struct drm_device *dev = crtc->base.dev;
1513 struct drm_i915_private *dev_priv = dev->dev_private;
1514 int reg = DPLL(crtc->pipe);
1515 u32 dpll = pipe_config->dpll_hw_state.dpll;
1516
1517 assert_pipe_disabled(dev_priv, crtc->pipe);
1518
1519 /* No really, not for ILK+ */
1520 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1521
1522 /* PLL is protected by panel, make sure we can write it */
1523 if (IS_MOBILE(dev_priv->dev))
1524 assert_panel_unlocked(dev_priv, crtc->pipe);
1525
1526 I915_WRITE(reg, dpll);
1527 POSTING_READ(reg);
1528 udelay(150);
1529
1530 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1531 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1532
1533 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1534 POSTING_READ(DPLL_MD(crtc->pipe));
1535
1536 /* We do this three times for luck */
1537 I915_WRITE(reg, dpll);
1538 POSTING_READ(reg);
1539 udelay(150); /* wait for warmup */
1540 I915_WRITE(reg, dpll);
1541 POSTING_READ(reg);
1542 udelay(150); /* wait for warmup */
1543 I915_WRITE(reg, dpll);
1544 POSTING_READ(reg);
1545 udelay(150); /* wait for warmup */
1546 }
1547
1548 static void chv_enable_pll(struct intel_crtc *crtc,
1549 const struct intel_crtc_state *pipe_config)
1550 {
1551 struct drm_device *dev = crtc->base.dev;
1552 struct drm_i915_private *dev_priv = dev->dev_private;
1553 int pipe = crtc->pipe;
1554 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1555 u32 tmp;
1556
1557 assert_pipe_disabled(dev_priv, crtc->pipe);
1558
1559 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1560
1561 mutex_lock(&dev_priv->dpio_lock);
1562
1563 /* Enable back the 10bit clock to display controller */
1564 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1565 tmp |= DPIO_DCLKP_EN;
1566 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1567
1568 /*
1569 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1570 */
1571 udelay(1);
1572
1573 /* Enable PLL */
1574 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1575
1576 /* Check PLL is locked */
1577 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1578 DRM_ERROR("PLL %d failed to lock\n", pipe);
1579
1580 /* not sure when this should be written */
1581 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1582 POSTING_READ(DPLL_MD(pipe));
1583
1584 mutex_unlock(&dev_priv->dpio_lock);
1585 }
1586
1587 static int intel_num_dvo_pipes(struct drm_device *dev)
1588 {
1589 struct intel_crtc *crtc;
1590 int count = 0;
1591
1592 for_each_intel_crtc(dev, crtc)
1593 count += crtc->active &&
1594 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1595
1596 return count;
1597 }
1598
1599 static void i9xx_enable_pll(struct intel_crtc *crtc)
1600 {
1601 struct drm_device *dev = crtc->base.dev;
1602 struct drm_i915_private *dev_priv = dev->dev_private;
1603 int reg = DPLL(crtc->pipe);
1604 u32 dpll = crtc->config->dpll_hw_state.dpll;
1605
1606 assert_pipe_disabled(dev_priv, crtc->pipe);
1607
1608 /* No really, not for ILK+ */
1609 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1610
1611 /* PLL is protected by panel, make sure we can write it */
1612 if (IS_MOBILE(dev) && !IS_I830(dev))
1613 assert_panel_unlocked(dev_priv, crtc->pipe);
1614
1615 /* Enable DVO 2x clock on both PLLs if necessary */
1616 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1617 /*
1618 * It appears to be important that we don't enable this
1619 * for the current pipe before otherwise configuring the
1620 * PLL. No idea how this should be handled if multiple
1621 * DVO outputs are enabled simultaneosly.
1622 */
1623 dpll |= DPLL_DVO_2X_MODE;
1624 I915_WRITE(DPLL(!crtc->pipe),
1625 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1626 }
1627
1628 /* Wait for the clocks to stabilize. */
1629 POSTING_READ(reg);
1630 udelay(150);
1631
1632 if (INTEL_INFO(dev)->gen >= 4) {
1633 I915_WRITE(DPLL_MD(crtc->pipe),
1634 crtc->config->dpll_hw_state.dpll_md);
1635 } else {
1636 /* The pixel multiplier can only be updated once the
1637 * DPLL is enabled and the clocks are stable.
1638 *
1639 * So write it again.
1640 */
1641 I915_WRITE(reg, dpll);
1642 }
1643
1644 /* We do this three times for luck */
1645 I915_WRITE(reg, dpll);
1646 POSTING_READ(reg);
1647 udelay(150); /* wait for warmup */
1648 I915_WRITE(reg, dpll);
1649 POSTING_READ(reg);
1650 udelay(150); /* wait for warmup */
1651 I915_WRITE(reg, dpll);
1652 POSTING_READ(reg);
1653 udelay(150); /* wait for warmup */
1654 }
1655
1656 /**
1657 * i9xx_disable_pll - disable a PLL
1658 * @dev_priv: i915 private structure
1659 * @pipe: pipe PLL to disable
1660 *
1661 * Disable the PLL for @pipe, making sure the pipe is off first.
1662 *
1663 * Note! This is for pre-ILK only.
1664 */
1665 static void i9xx_disable_pll(struct intel_crtc *crtc)
1666 {
1667 struct drm_device *dev = crtc->base.dev;
1668 struct drm_i915_private *dev_priv = dev->dev_private;
1669 enum pipe pipe = crtc->pipe;
1670
1671 /* Disable DVO 2x clock on both PLLs if necessary */
1672 if (IS_I830(dev) &&
1673 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1674 intel_num_dvo_pipes(dev) == 1) {
1675 I915_WRITE(DPLL(PIPE_B),
1676 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1677 I915_WRITE(DPLL(PIPE_A),
1678 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1679 }
1680
1681 /* Don't disable pipe or pipe PLLs if needed */
1682 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1683 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1684 return;
1685
1686 /* Make sure the pipe isn't still relying on us */
1687 assert_pipe_disabled(dev_priv, pipe);
1688
1689 I915_WRITE(DPLL(pipe), 0);
1690 POSTING_READ(DPLL(pipe));
1691 }
1692
1693 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1694 {
1695 u32 val = 0;
1696
1697 /* Make sure the pipe isn't still relying on us */
1698 assert_pipe_disabled(dev_priv, pipe);
1699
1700 /*
1701 * Leave integrated clock source and reference clock enabled for pipe B.
1702 * The latter is needed for VGA hotplug / manual detection.
1703 */
1704 if (pipe == PIPE_B)
1705 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1706 I915_WRITE(DPLL(pipe), val);
1707 POSTING_READ(DPLL(pipe));
1708
1709 }
1710
1711 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1712 {
1713 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1714 u32 val;
1715
1716 /* Make sure the pipe isn't still relying on us */
1717 assert_pipe_disabled(dev_priv, pipe);
1718
1719 /* Set PLL en = 0 */
1720 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1721 if (pipe != PIPE_A)
1722 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1723 I915_WRITE(DPLL(pipe), val);
1724 POSTING_READ(DPLL(pipe));
1725
1726 mutex_lock(&dev_priv->dpio_lock);
1727
1728 /* Disable 10bit clock to display controller */
1729 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1730 val &= ~DPIO_DCLKP_EN;
1731 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1732
1733 /* disable left/right clock distribution */
1734 if (pipe != PIPE_B) {
1735 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1736 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1737 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1738 } else {
1739 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1740 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1741 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1742 }
1743
1744 mutex_unlock(&dev_priv->dpio_lock);
1745 }
1746
1747 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1748 struct intel_digital_port *dport)
1749 {
1750 u32 port_mask;
1751 int dpll_reg;
1752
1753 switch (dport->port) {
1754 case PORT_B:
1755 port_mask = DPLL_PORTB_READY_MASK;
1756 dpll_reg = DPLL(0);
1757 break;
1758 case PORT_C:
1759 port_mask = DPLL_PORTC_READY_MASK;
1760 dpll_reg = DPLL(0);
1761 break;
1762 case PORT_D:
1763 port_mask = DPLL_PORTD_READY_MASK;
1764 dpll_reg = DPIO_PHY_STATUS;
1765 break;
1766 default:
1767 BUG();
1768 }
1769
1770 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1771 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1772 port_name(dport->port), I915_READ(dpll_reg));
1773 }
1774
1775 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1776 {
1777 struct drm_device *dev = crtc->base.dev;
1778 struct drm_i915_private *dev_priv = dev->dev_private;
1779 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1780
1781 if (WARN_ON(pll == NULL))
1782 return;
1783
1784 WARN_ON(!pll->config.crtc_mask);
1785 if (pll->active == 0) {
1786 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1787 WARN_ON(pll->on);
1788 assert_shared_dpll_disabled(dev_priv, pll);
1789
1790 pll->mode_set(dev_priv, pll);
1791 }
1792 }
1793
1794 /**
1795 * intel_enable_shared_dpll - enable PCH PLL
1796 * @dev_priv: i915 private structure
1797 * @pipe: pipe PLL to enable
1798 *
1799 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1800 * drives the transcoder clock.
1801 */
1802 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1803 {
1804 struct drm_device *dev = crtc->base.dev;
1805 struct drm_i915_private *dev_priv = dev->dev_private;
1806 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1807
1808 if (WARN_ON(pll == NULL))
1809 return;
1810
1811 if (WARN_ON(pll->config.crtc_mask == 0))
1812 return;
1813
1814 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1815 pll->name, pll->active, pll->on,
1816 crtc->base.base.id);
1817
1818 if (pll->active++) {
1819 WARN_ON(!pll->on);
1820 assert_shared_dpll_enabled(dev_priv, pll);
1821 return;
1822 }
1823 WARN_ON(pll->on);
1824
1825 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1826
1827 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1828 pll->enable(dev_priv, pll);
1829 pll->on = true;
1830 }
1831
1832 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1833 {
1834 struct drm_device *dev = crtc->base.dev;
1835 struct drm_i915_private *dev_priv = dev->dev_private;
1836 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1837
1838 /* PCH only available on ILK+ */
1839 BUG_ON(INTEL_INFO(dev)->gen < 5);
1840 if (WARN_ON(pll == NULL))
1841 return;
1842
1843 if (WARN_ON(pll->config.crtc_mask == 0))
1844 return;
1845
1846 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1847 pll->name, pll->active, pll->on,
1848 crtc->base.base.id);
1849
1850 if (WARN_ON(pll->active == 0)) {
1851 assert_shared_dpll_disabled(dev_priv, pll);
1852 return;
1853 }
1854
1855 assert_shared_dpll_enabled(dev_priv, pll);
1856 WARN_ON(!pll->on);
1857 if (--pll->active)
1858 return;
1859
1860 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1861 pll->disable(dev_priv, pll);
1862 pll->on = false;
1863
1864 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1865 }
1866
1867 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1868 enum pipe pipe)
1869 {
1870 struct drm_device *dev = dev_priv->dev;
1871 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1872 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1873 uint32_t reg, val, pipeconf_val;
1874
1875 /* PCH only available on ILK+ */
1876 BUG_ON(!HAS_PCH_SPLIT(dev));
1877
1878 /* Make sure PCH DPLL is enabled */
1879 assert_shared_dpll_enabled(dev_priv,
1880 intel_crtc_to_shared_dpll(intel_crtc));
1881
1882 /* FDI must be feeding us bits for PCH ports */
1883 assert_fdi_tx_enabled(dev_priv, pipe);
1884 assert_fdi_rx_enabled(dev_priv, pipe);
1885
1886 if (HAS_PCH_CPT(dev)) {
1887 /* Workaround: Set the timing override bit before enabling the
1888 * pch transcoder. */
1889 reg = TRANS_CHICKEN2(pipe);
1890 val = I915_READ(reg);
1891 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1892 I915_WRITE(reg, val);
1893 }
1894
1895 reg = PCH_TRANSCONF(pipe);
1896 val = I915_READ(reg);
1897 pipeconf_val = I915_READ(PIPECONF(pipe));
1898
1899 if (HAS_PCH_IBX(dev_priv->dev)) {
1900 /*
1901 * make the BPC in transcoder be consistent with
1902 * that in pipeconf reg.
1903 */
1904 val &= ~PIPECONF_BPC_MASK;
1905 val |= pipeconf_val & PIPECONF_BPC_MASK;
1906 }
1907
1908 val &= ~TRANS_INTERLACE_MASK;
1909 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1910 if (HAS_PCH_IBX(dev_priv->dev) &&
1911 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1912 val |= TRANS_LEGACY_INTERLACED_ILK;
1913 else
1914 val |= TRANS_INTERLACED;
1915 else
1916 val |= TRANS_PROGRESSIVE;
1917
1918 I915_WRITE(reg, val | TRANS_ENABLE);
1919 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1920 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1921 }
1922
1923 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1924 enum transcoder cpu_transcoder)
1925 {
1926 u32 val, pipeconf_val;
1927
1928 /* PCH only available on ILK+ */
1929 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1930
1931 /* FDI must be feeding us bits for PCH ports */
1932 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1933 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1934
1935 /* Workaround: set timing override bit. */
1936 val = I915_READ(_TRANSA_CHICKEN2);
1937 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1938 I915_WRITE(_TRANSA_CHICKEN2, val);
1939
1940 val = TRANS_ENABLE;
1941 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1942
1943 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1944 PIPECONF_INTERLACED_ILK)
1945 val |= TRANS_INTERLACED;
1946 else
1947 val |= TRANS_PROGRESSIVE;
1948
1949 I915_WRITE(LPT_TRANSCONF, val);
1950 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1951 DRM_ERROR("Failed to enable PCH transcoder\n");
1952 }
1953
1954 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1955 enum pipe pipe)
1956 {
1957 struct drm_device *dev = dev_priv->dev;
1958 uint32_t reg, val;
1959
1960 /* FDI relies on the transcoder */
1961 assert_fdi_tx_disabled(dev_priv, pipe);
1962 assert_fdi_rx_disabled(dev_priv, pipe);
1963
1964 /* Ports must be off as well */
1965 assert_pch_ports_disabled(dev_priv, pipe);
1966
1967 reg = PCH_TRANSCONF(pipe);
1968 val = I915_READ(reg);
1969 val &= ~TRANS_ENABLE;
1970 I915_WRITE(reg, val);
1971 /* wait for PCH transcoder off, transcoder state */
1972 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1973 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1974
1975 if (!HAS_PCH_IBX(dev)) {
1976 /* Workaround: Clear the timing override chicken bit again. */
1977 reg = TRANS_CHICKEN2(pipe);
1978 val = I915_READ(reg);
1979 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1980 I915_WRITE(reg, val);
1981 }
1982 }
1983
1984 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1985 {
1986 u32 val;
1987
1988 val = I915_READ(LPT_TRANSCONF);
1989 val &= ~TRANS_ENABLE;
1990 I915_WRITE(LPT_TRANSCONF, val);
1991 /* wait for PCH transcoder off, transcoder state */
1992 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1993 DRM_ERROR("Failed to disable PCH transcoder\n");
1994
1995 /* Workaround: clear timing override bit. */
1996 val = I915_READ(_TRANSA_CHICKEN2);
1997 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1998 I915_WRITE(_TRANSA_CHICKEN2, val);
1999 }
2000
2001 /**
2002 * intel_enable_pipe - enable a pipe, asserting requirements
2003 * @crtc: crtc responsible for the pipe
2004 *
2005 * Enable @crtc's pipe, making sure that various hardware specific requirements
2006 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2007 */
2008 static void intel_enable_pipe(struct intel_crtc *crtc)
2009 {
2010 struct drm_device *dev = crtc->base.dev;
2011 struct drm_i915_private *dev_priv = dev->dev_private;
2012 enum pipe pipe = crtc->pipe;
2013 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2014 pipe);
2015 enum pipe pch_transcoder;
2016 int reg;
2017 u32 val;
2018
2019 assert_planes_disabled(dev_priv, pipe);
2020 assert_cursor_disabled(dev_priv, pipe);
2021 assert_sprites_disabled(dev_priv, pipe);
2022
2023 if (HAS_PCH_LPT(dev_priv->dev))
2024 pch_transcoder = TRANSCODER_A;
2025 else
2026 pch_transcoder = pipe;
2027
2028 /*
2029 * A pipe without a PLL won't actually be able to drive bits from
2030 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2031 * need the check.
2032 */
2033 if (!HAS_PCH_SPLIT(dev_priv->dev))
2034 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2035 assert_dsi_pll_enabled(dev_priv);
2036 else
2037 assert_pll_enabled(dev_priv, pipe);
2038 else {
2039 if (crtc->config->has_pch_encoder) {
2040 /* if driving the PCH, we need FDI enabled */
2041 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2042 assert_fdi_tx_pll_enabled(dev_priv,
2043 (enum pipe) cpu_transcoder);
2044 }
2045 /* FIXME: assert CPU port conditions for SNB+ */
2046 }
2047
2048 reg = PIPECONF(cpu_transcoder);
2049 val = I915_READ(reg);
2050 if (val & PIPECONF_ENABLE) {
2051 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2052 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2053 return;
2054 }
2055
2056 I915_WRITE(reg, val | PIPECONF_ENABLE);
2057 POSTING_READ(reg);
2058 }
2059
2060 /**
2061 * intel_disable_pipe - disable a pipe, asserting requirements
2062 * @crtc: crtc whose pipes is to be disabled
2063 *
2064 * Disable the pipe of @crtc, making sure that various hardware
2065 * specific requirements are met, if applicable, e.g. plane
2066 * disabled, panel fitter off, etc.
2067 *
2068 * Will wait until the pipe has shut down before returning.
2069 */
2070 static void intel_disable_pipe(struct intel_crtc *crtc)
2071 {
2072 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2073 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2074 enum pipe pipe = crtc->pipe;
2075 int reg;
2076 u32 val;
2077
2078 /*
2079 * Make sure planes won't keep trying to pump pixels to us,
2080 * or we might hang the display.
2081 */
2082 assert_planes_disabled(dev_priv, pipe);
2083 assert_cursor_disabled(dev_priv, pipe);
2084 assert_sprites_disabled(dev_priv, pipe);
2085
2086 reg = PIPECONF(cpu_transcoder);
2087 val = I915_READ(reg);
2088 if ((val & PIPECONF_ENABLE) == 0)
2089 return;
2090
2091 /*
2092 * Double wide has implications for planes
2093 * so best keep it disabled when not needed.
2094 */
2095 if (crtc->config->double_wide)
2096 val &= ~PIPECONF_DOUBLE_WIDE;
2097
2098 /* Don't disable pipe or pipe PLLs if needed */
2099 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2100 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2101 val &= ~PIPECONF_ENABLE;
2102
2103 I915_WRITE(reg, val);
2104 if ((val & PIPECONF_ENABLE) == 0)
2105 intel_wait_for_pipe_off(crtc);
2106 }
2107
2108 /*
2109 * Plane regs are double buffered, going from enabled->disabled needs a
2110 * trigger in order to latch. The display address reg provides this.
2111 */
2112 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2113 enum plane plane)
2114 {
2115 struct drm_device *dev = dev_priv->dev;
2116 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2117
2118 I915_WRITE(reg, I915_READ(reg));
2119 POSTING_READ(reg);
2120 }
2121
2122 /**
2123 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2124 * @plane: plane to be enabled
2125 * @crtc: crtc for the plane
2126 *
2127 * Enable @plane on @crtc, making sure that the pipe is running first.
2128 */
2129 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2130 struct drm_crtc *crtc)
2131 {
2132 struct drm_device *dev = plane->dev;
2133 struct drm_i915_private *dev_priv = dev->dev_private;
2134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2135
2136 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2137 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2138
2139 if (intel_crtc->primary_enabled)
2140 return;
2141
2142 intel_crtc->primary_enabled = true;
2143
2144 dev_priv->display.update_primary_plane(crtc, plane->fb,
2145 crtc->x, crtc->y);
2146
2147 /*
2148 * BDW signals flip done immediately if the plane
2149 * is disabled, even if the plane enable is already
2150 * armed to occur at the next vblank :(
2151 */
2152 if (IS_BROADWELL(dev))
2153 intel_wait_for_vblank(dev, intel_crtc->pipe);
2154 }
2155
2156 /**
2157 * intel_disable_primary_hw_plane - disable the primary hardware plane
2158 * @plane: plane to be disabled
2159 * @crtc: crtc for the plane
2160 *
2161 * Disable @plane on @crtc, making sure that the pipe is running first.
2162 */
2163 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2164 struct drm_crtc *crtc)
2165 {
2166 struct drm_device *dev = plane->dev;
2167 struct drm_i915_private *dev_priv = dev->dev_private;
2168 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2169
2170 if (WARN_ON(!intel_crtc->active))
2171 return;
2172
2173 if (!intel_crtc->primary_enabled)
2174 return;
2175
2176 intel_crtc->primary_enabled = false;
2177
2178 dev_priv->display.update_primary_plane(crtc, plane->fb,
2179 crtc->x, crtc->y);
2180 }
2181
2182 static bool need_vtd_wa(struct drm_device *dev)
2183 {
2184 #ifdef CONFIG_INTEL_IOMMU
2185 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2186 return true;
2187 #endif
2188 return false;
2189 }
2190
2191 int
2192 intel_fb_align_height(struct drm_device *dev, int height, unsigned int tiling)
2193 {
2194 int tile_height;
2195
2196 tile_height = tiling ? (IS_GEN2(dev) ? 16 : 8) : 1;
2197 return ALIGN(height, tile_height);
2198 }
2199
2200 int
2201 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2202 struct drm_framebuffer *fb,
2203 struct intel_engine_cs *pipelined)
2204 {
2205 struct drm_device *dev = fb->dev;
2206 struct drm_i915_private *dev_priv = dev->dev_private;
2207 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2208 u32 alignment;
2209 int ret;
2210
2211 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2212
2213 switch (obj->tiling_mode) {
2214 case I915_TILING_NONE:
2215 if (INTEL_INFO(dev)->gen >= 9)
2216 alignment = 256 * 1024;
2217 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2218 alignment = 128 * 1024;
2219 else if (INTEL_INFO(dev)->gen >= 4)
2220 alignment = 4 * 1024;
2221 else
2222 alignment = 64 * 1024;
2223 break;
2224 case I915_TILING_X:
2225 if (INTEL_INFO(dev)->gen >= 9)
2226 alignment = 256 * 1024;
2227 else {
2228 /* pin() will align the object as required by fence */
2229 alignment = 0;
2230 }
2231 break;
2232 case I915_TILING_Y:
2233 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2234 return -EINVAL;
2235 default:
2236 BUG();
2237 }
2238
2239 /* Note that the w/a also requires 64 PTE of padding following the
2240 * bo. We currently fill all unused PTE with the shadow page and so
2241 * we should always have valid PTE following the scanout preventing
2242 * the VT-d warning.
2243 */
2244 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2245 alignment = 256 * 1024;
2246
2247 /*
2248 * Global gtt pte registers are special registers which actually forward
2249 * writes to a chunk of system memory. Which means that there is no risk
2250 * that the register values disappear as soon as we call
2251 * intel_runtime_pm_put(), so it is correct to wrap only the
2252 * pin/unpin/fence and not more.
2253 */
2254 intel_runtime_pm_get(dev_priv);
2255
2256 dev_priv->mm.interruptible = false;
2257 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2258 if (ret)
2259 goto err_interruptible;
2260
2261 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2262 * fence, whereas 965+ only requires a fence if using
2263 * framebuffer compression. For simplicity, we always install
2264 * a fence as the cost is not that onerous.
2265 */
2266 ret = i915_gem_object_get_fence(obj);
2267 if (ret)
2268 goto err_unpin;
2269
2270 i915_gem_object_pin_fence(obj);
2271
2272 dev_priv->mm.interruptible = true;
2273 intel_runtime_pm_put(dev_priv);
2274 return 0;
2275
2276 err_unpin:
2277 i915_gem_object_unpin_from_display_plane(obj);
2278 err_interruptible:
2279 dev_priv->mm.interruptible = true;
2280 intel_runtime_pm_put(dev_priv);
2281 return ret;
2282 }
2283
2284 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2285 {
2286 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2287
2288 i915_gem_object_unpin_fence(obj);
2289 i915_gem_object_unpin_from_display_plane(obj);
2290 }
2291
2292 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2293 * is assumed to be a power-of-two. */
2294 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2295 unsigned int tiling_mode,
2296 unsigned int cpp,
2297 unsigned int pitch)
2298 {
2299 if (tiling_mode != I915_TILING_NONE) {
2300 unsigned int tile_rows, tiles;
2301
2302 tile_rows = *y / 8;
2303 *y %= 8;
2304
2305 tiles = *x / (512/cpp);
2306 *x %= 512/cpp;
2307
2308 return tile_rows * pitch * 8 + tiles * 4096;
2309 } else {
2310 unsigned int offset;
2311
2312 offset = *y * pitch + *x * cpp;
2313 *y = 0;
2314 *x = (offset & 4095) / cpp;
2315 return offset & -4096;
2316 }
2317 }
2318
2319 int intel_format_to_fourcc(int format)
2320 {
2321 switch (format) {
2322 case DISPPLANE_8BPP:
2323 return DRM_FORMAT_C8;
2324 case DISPPLANE_BGRX555:
2325 return DRM_FORMAT_XRGB1555;
2326 case DISPPLANE_BGRX565:
2327 return DRM_FORMAT_RGB565;
2328 default:
2329 case DISPPLANE_BGRX888:
2330 return DRM_FORMAT_XRGB8888;
2331 case DISPPLANE_RGBX888:
2332 return DRM_FORMAT_XBGR8888;
2333 case DISPPLANE_BGRX101010:
2334 return DRM_FORMAT_XRGB2101010;
2335 case DISPPLANE_RGBX101010:
2336 return DRM_FORMAT_XBGR2101010;
2337 }
2338 }
2339
2340 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2341 struct intel_plane_config *plane_config)
2342 {
2343 struct drm_device *dev = crtc->base.dev;
2344 struct drm_i915_gem_object *obj = NULL;
2345 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2346 u32 base = plane_config->base;
2347
2348 if (plane_config->size == 0)
2349 return false;
2350
2351 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2352 plane_config->size);
2353 if (!obj)
2354 return false;
2355
2356 obj->tiling_mode = plane_config->tiling;
2357 if (obj->tiling_mode == I915_TILING_X)
2358 obj->stride = crtc->base.primary->fb->pitches[0];
2359
2360 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2361 mode_cmd.width = crtc->base.primary->fb->width;
2362 mode_cmd.height = crtc->base.primary->fb->height;
2363 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2364
2365 mutex_lock(&dev->struct_mutex);
2366
2367 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2368 &mode_cmd, obj)) {
2369 DRM_DEBUG_KMS("intel fb init failed\n");
2370 goto out_unref_obj;
2371 }
2372
2373 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2374 mutex_unlock(&dev->struct_mutex);
2375
2376 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2377 return true;
2378
2379 out_unref_obj:
2380 drm_gem_object_unreference(&obj->base);
2381 mutex_unlock(&dev->struct_mutex);
2382 return false;
2383 }
2384
2385 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2386 struct intel_plane_config *plane_config)
2387 {
2388 struct drm_device *dev = intel_crtc->base.dev;
2389 struct drm_i915_private *dev_priv = dev->dev_private;
2390 struct drm_crtc *c;
2391 struct intel_crtc *i;
2392 struct drm_i915_gem_object *obj;
2393
2394 if (!intel_crtc->base.primary->fb)
2395 return;
2396
2397 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2398 return;
2399
2400 kfree(intel_crtc->base.primary->fb);
2401 intel_crtc->base.primary->fb = NULL;
2402
2403 /*
2404 * Failed to alloc the obj, check to see if we should share
2405 * an fb with another CRTC instead
2406 */
2407 for_each_crtc(dev, c) {
2408 i = to_intel_crtc(c);
2409
2410 if (c == &intel_crtc->base)
2411 continue;
2412
2413 if (!i->active)
2414 continue;
2415
2416 obj = intel_fb_obj(c->primary->fb);
2417 if (obj == NULL)
2418 continue;
2419
2420 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2421 if (obj->tiling_mode != I915_TILING_NONE)
2422 dev_priv->preserve_bios_swizzle = true;
2423
2424 drm_framebuffer_reference(c->primary->fb);
2425 intel_crtc->base.primary->fb = c->primary->fb;
2426 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2427 break;
2428 }
2429 }
2430 }
2431
2432 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2433 struct drm_framebuffer *fb,
2434 int x, int y)
2435 {
2436 struct drm_device *dev = crtc->dev;
2437 struct drm_i915_private *dev_priv = dev->dev_private;
2438 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2439 struct drm_i915_gem_object *obj;
2440 int plane = intel_crtc->plane;
2441 unsigned long linear_offset;
2442 u32 dspcntr;
2443 u32 reg = DSPCNTR(plane);
2444 int pixel_size;
2445
2446 if (!intel_crtc->primary_enabled) {
2447 I915_WRITE(reg, 0);
2448 if (INTEL_INFO(dev)->gen >= 4)
2449 I915_WRITE(DSPSURF(plane), 0);
2450 else
2451 I915_WRITE(DSPADDR(plane), 0);
2452 POSTING_READ(reg);
2453 return;
2454 }
2455
2456 obj = intel_fb_obj(fb);
2457 if (WARN_ON(obj == NULL))
2458 return;
2459
2460 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2461
2462 dspcntr = DISPPLANE_GAMMA_ENABLE;
2463
2464 dspcntr |= DISPLAY_PLANE_ENABLE;
2465
2466 if (INTEL_INFO(dev)->gen < 4) {
2467 if (intel_crtc->pipe == PIPE_B)
2468 dspcntr |= DISPPLANE_SEL_PIPE_B;
2469
2470 /* pipesrc and dspsize control the size that is scaled from,
2471 * which should always be the user's requested size.
2472 */
2473 I915_WRITE(DSPSIZE(plane),
2474 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2475 (intel_crtc->config->pipe_src_w - 1));
2476 I915_WRITE(DSPPOS(plane), 0);
2477 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2478 I915_WRITE(PRIMSIZE(plane),
2479 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2480 (intel_crtc->config->pipe_src_w - 1));
2481 I915_WRITE(PRIMPOS(plane), 0);
2482 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2483 }
2484
2485 switch (fb->pixel_format) {
2486 case DRM_FORMAT_C8:
2487 dspcntr |= DISPPLANE_8BPP;
2488 break;
2489 case DRM_FORMAT_XRGB1555:
2490 case DRM_FORMAT_ARGB1555:
2491 dspcntr |= DISPPLANE_BGRX555;
2492 break;
2493 case DRM_FORMAT_RGB565:
2494 dspcntr |= DISPPLANE_BGRX565;
2495 break;
2496 case DRM_FORMAT_XRGB8888:
2497 case DRM_FORMAT_ARGB8888:
2498 dspcntr |= DISPPLANE_BGRX888;
2499 break;
2500 case DRM_FORMAT_XBGR8888:
2501 case DRM_FORMAT_ABGR8888:
2502 dspcntr |= DISPPLANE_RGBX888;
2503 break;
2504 case DRM_FORMAT_XRGB2101010:
2505 case DRM_FORMAT_ARGB2101010:
2506 dspcntr |= DISPPLANE_BGRX101010;
2507 break;
2508 case DRM_FORMAT_XBGR2101010:
2509 case DRM_FORMAT_ABGR2101010:
2510 dspcntr |= DISPPLANE_RGBX101010;
2511 break;
2512 default:
2513 BUG();
2514 }
2515
2516 if (INTEL_INFO(dev)->gen >= 4 &&
2517 obj->tiling_mode != I915_TILING_NONE)
2518 dspcntr |= DISPPLANE_TILED;
2519
2520 if (IS_G4X(dev))
2521 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2522
2523 linear_offset = y * fb->pitches[0] + x * pixel_size;
2524
2525 if (INTEL_INFO(dev)->gen >= 4) {
2526 intel_crtc->dspaddr_offset =
2527 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2528 pixel_size,
2529 fb->pitches[0]);
2530 linear_offset -= intel_crtc->dspaddr_offset;
2531 } else {
2532 intel_crtc->dspaddr_offset = linear_offset;
2533 }
2534
2535 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2536 dspcntr |= DISPPLANE_ROTATE_180;
2537
2538 x += (intel_crtc->config->pipe_src_w - 1);
2539 y += (intel_crtc->config->pipe_src_h - 1);
2540
2541 /* Finding the last pixel of the last line of the display
2542 data and adding to linear_offset*/
2543 linear_offset +=
2544 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2545 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2546 }
2547
2548 I915_WRITE(reg, dspcntr);
2549
2550 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2551 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2552 fb->pitches[0]);
2553 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2554 if (INTEL_INFO(dev)->gen >= 4) {
2555 I915_WRITE(DSPSURF(plane),
2556 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2557 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2558 I915_WRITE(DSPLINOFF(plane), linear_offset);
2559 } else
2560 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2561 POSTING_READ(reg);
2562 }
2563
2564 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2565 struct drm_framebuffer *fb,
2566 int x, int y)
2567 {
2568 struct drm_device *dev = crtc->dev;
2569 struct drm_i915_private *dev_priv = dev->dev_private;
2570 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2571 struct drm_i915_gem_object *obj;
2572 int plane = intel_crtc->plane;
2573 unsigned long linear_offset;
2574 u32 dspcntr;
2575 u32 reg = DSPCNTR(plane);
2576 int pixel_size;
2577
2578 if (!intel_crtc->primary_enabled) {
2579 I915_WRITE(reg, 0);
2580 I915_WRITE(DSPSURF(plane), 0);
2581 POSTING_READ(reg);
2582 return;
2583 }
2584
2585 obj = intel_fb_obj(fb);
2586 if (WARN_ON(obj == NULL))
2587 return;
2588
2589 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2590
2591 dspcntr = DISPPLANE_GAMMA_ENABLE;
2592
2593 dspcntr |= DISPLAY_PLANE_ENABLE;
2594
2595 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2596 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2597
2598 switch (fb->pixel_format) {
2599 case DRM_FORMAT_C8:
2600 dspcntr |= DISPPLANE_8BPP;
2601 break;
2602 case DRM_FORMAT_RGB565:
2603 dspcntr |= DISPPLANE_BGRX565;
2604 break;
2605 case DRM_FORMAT_XRGB8888:
2606 case DRM_FORMAT_ARGB8888:
2607 dspcntr |= DISPPLANE_BGRX888;
2608 break;
2609 case DRM_FORMAT_XBGR8888:
2610 case DRM_FORMAT_ABGR8888:
2611 dspcntr |= DISPPLANE_RGBX888;
2612 break;
2613 case DRM_FORMAT_XRGB2101010:
2614 case DRM_FORMAT_ARGB2101010:
2615 dspcntr |= DISPPLANE_BGRX101010;
2616 break;
2617 case DRM_FORMAT_XBGR2101010:
2618 case DRM_FORMAT_ABGR2101010:
2619 dspcntr |= DISPPLANE_RGBX101010;
2620 break;
2621 default:
2622 BUG();
2623 }
2624
2625 if (obj->tiling_mode != I915_TILING_NONE)
2626 dspcntr |= DISPPLANE_TILED;
2627
2628 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2629 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2630
2631 linear_offset = y * fb->pitches[0] + x * pixel_size;
2632 intel_crtc->dspaddr_offset =
2633 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2634 pixel_size,
2635 fb->pitches[0]);
2636 linear_offset -= intel_crtc->dspaddr_offset;
2637 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2638 dspcntr |= DISPPLANE_ROTATE_180;
2639
2640 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2641 x += (intel_crtc->config->pipe_src_w - 1);
2642 y += (intel_crtc->config->pipe_src_h - 1);
2643
2644 /* Finding the last pixel of the last line of the display
2645 data and adding to linear_offset*/
2646 linear_offset +=
2647 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2648 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2649 }
2650 }
2651
2652 I915_WRITE(reg, dspcntr);
2653
2654 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2655 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2656 fb->pitches[0]);
2657 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2658 I915_WRITE(DSPSURF(plane),
2659 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2660 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2661 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2662 } else {
2663 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2664 I915_WRITE(DSPLINOFF(plane), linear_offset);
2665 }
2666 POSTING_READ(reg);
2667 }
2668
2669 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2670 struct drm_framebuffer *fb,
2671 int x, int y)
2672 {
2673 struct drm_device *dev = crtc->dev;
2674 struct drm_i915_private *dev_priv = dev->dev_private;
2675 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2676 struct intel_framebuffer *intel_fb;
2677 struct drm_i915_gem_object *obj;
2678 int pipe = intel_crtc->pipe;
2679 u32 plane_ctl, stride;
2680
2681 if (!intel_crtc->primary_enabled) {
2682 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2683 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2684 POSTING_READ(PLANE_CTL(pipe, 0));
2685 return;
2686 }
2687
2688 plane_ctl = PLANE_CTL_ENABLE |
2689 PLANE_CTL_PIPE_GAMMA_ENABLE |
2690 PLANE_CTL_PIPE_CSC_ENABLE;
2691
2692 switch (fb->pixel_format) {
2693 case DRM_FORMAT_RGB565:
2694 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2695 break;
2696 case DRM_FORMAT_XRGB8888:
2697 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2698 break;
2699 case DRM_FORMAT_XBGR8888:
2700 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2701 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2702 break;
2703 case DRM_FORMAT_XRGB2101010:
2704 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2705 break;
2706 case DRM_FORMAT_XBGR2101010:
2707 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2708 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2709 break;
2710 default:
2711 BUG();
2712 }
2713
2714 intel_fb = to_intel_framebuffer(fb);
2715 obj = intel_fb->obj;
2716
2717 /*
2718 * The stride is either expressed as a multiple of 64 bytes chunks for
2719 * linear buffers or in number of tiles for tiled buffers.
2720 */
2721 switch (obj->tiling_mode) {
2722 case I915_TILING_NONE:
2723 stride = fb->pitches[0] >> 6;
2724 break;
2725 case I915_TILING_X:
2726 plane_ctl |= PLANE_CTL_TILED_X;
2727 stride = fb->pitches[0] >> 9;
2728 break;
2729 default:
2730 BUG();
2731 }
2732
2733 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2734 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180))
2735 plane_ctl |= PLANE_CTL_ROTATE_180;
2736
2737 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2738
2739 DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2740 i915_gem_obj_ggtt_offset(obj),
2741 x, y, fb->width, fb->height,
2742 fb->pitches[0]);
2743
2744 I915_WRITE(PLANE_POS(pipe, 0), 0);
2745 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2746 I915_WRITE(PLANE_SIZE(pipe, 0),
2747 (intel_crtc->config->pipe_src_h - 1) << 16 |
2748 (intel_crtc->config->pipe_src_w - 1));
2749 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
2750 I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2751
2752 POSTING_READ(PLANE_SURF(pipe, 0));
2753 }
2754
2755 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2756 static int
2757 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2758 int x, int y, enum mode_set_atomic state)
2759 {
2760 struct drm_device *dev = crtc->dev;
2761 struct drm_i915_private *dev_priv = dev->dev_private;
2762
2763 if (dev_priv->display.disable_fbc)
2764 dev_priv->display.disable_fbc(dev);
2765
2766 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2767
2768 return 0;
2769 }
2770
2771 static void intel_complete_page_flips(struct drm_device *dev)
2772 {
2773 struct drm_crtc *crtc;
2774
2775 for_each_crtc(dev, crtc) {
2776 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2777 enum plane plane = intel_crtc->plane;
2778
2779 intel_prepare_page_flip(dev, plane);
2780 intel_finish_page_flip_plane(dev, plane);
2781 }
2782 }
2783
2784 static void intel_update_primary_planes(struct drm_device *dev)
2785 {
2786 struct drm_i915_private *dev_priv = dev->dev_private;
2787 struct drm_crtc *crtc;
2788
2789 for_each_crtc(dev, crtc) {
2790 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2791
2792 drm_modeset_lock(&crtc->mutex, NULL);
2793 /*
2794 * FIXME: Once we have proper support for primary planes (and
2795 * disabling them without disabling the entire crtc) allow again
2796 * a NULL crtc->primary->fb.
2797 */
2798 if (intel_crtc->active && crtc->primary->fb)
2799 dev_priv->display.update_primary_plane(crtc,
2800 crtc->primary->fb,
2801 crtc->x,
2802 crtc->y);
2803 drm_modeset_unlock(&crtc->mutex);
2804 }
2805 }
2806
2807 void intel_prepare_reset(struct drm_device *dev)
2808 {
2809 struct drm_i915_private *dev_priv = to_i915(dev);
2810 struct intel_crtc *crtc;
2811
2812 /* no reset support for gen2 */
2813 if (IS_GEN2(dev))
2814 return;
2815
2816 /* reset doesn't touch the display */
2817 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
2818 return;
2819
2820 drm_modeset_lock_all(dev);
2821
2822 /*
2823 * Disabling the crtcs gracefully seems nicer. Also the
2824 * g33 docs say we should at least disable all the planes.
2825 */
2826 for_each_intel_crtc(dev, crtc) {
2827 if (crtc->active)
2828 dev_priv->display.crtc_disable(&crtc->base);
2829 }
2830 }
2831
2832 void intel_finish_reset(struct drm_device *dev)
2833 {
2834 struct drm_i915_private *dev_priv = to_i915(dev);
2835
2836 /*
2837 * Flips in the rings will be nuked by the reset,
2838 * so complete all pending flips so that user space
2839 * will get its events and not get stuck.
2840 */
2841 intel_complete_page_flips(dev);
2842
2843 /* no reset support for gen2 */
2844 if (IS_GEN2(dev))
2845 return;
2846
2847 /* reset doesn't touch the display */
2848 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
2849 /*
2850 * Flips in the rings have been nuked by the reset,
2851 * so update the base address of all primary
2852 * planes to the the last fb to make sure we're
2853 * showing the correct fb after a reset.
2854 */
2855 intel_update_primary_planes(dev);
2856 return;
2857 }
2858
2859 /*
2860 * The display has been reset as well,
2861 * so need a full re-initialization.
2862 */
2863 intel_runtime_pm_disable_interrupts(dev_priv);
2864 intel_runtime_pm_enable_interrupts(dev_priv);
2865
2866 intel_modeset_init_hw(dev);
2867
2868 spin_lock_irq(&dev_priv->irq_lock);
2869 if (dev_priv->display.hpd_irq_setup)
2870 dev_priv->display.hpd_irq_setup(dev);
2871 spin_unlock_irq(&dev_priv->irq_lock);
2872
2873 intel_modeset_setup_hw_state(dev, true);
2874
2875 intel_hpd_init(dev_priv);
2876
2877 drm_modeset_unlock_all(dev);
2878 }
2879
2880 static int
2881 intel_finish_fb(struct drm_framebuffer *old_fb)
2882 {
2883 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2884 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2885 bool was_interruptible = dev_priv->mm.interruptible;
2886 int ret;
2887
2888 /* Big Hammer, we also need to ensure that any pending
2889 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2890 * current scanout is retired before unpinning the old
2891 * framebuffer.
2892 *
2893 * This should only fail upon a hung GPU, in which case we
2894 * can safely continue.
2895 */
2896 dev_priv->mm.interruptible = false;
2897 ret = i915_gem_object_finish_gpu(obj);
2898 dev_priv->mm.interruptible = was_interruptible;
2899
2900 return ret;
2901 }
2902
2903 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2904 {
2905 struct drm_device *dev = crtc->dev;
2906 struct drm_i915_private *dev_priv = dev->dev_private;
2907 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2908 bool pending;
2909
2910 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2911 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2912 return false;
2913
2914 spin_lock_irq(&dev->event_lock);
2915 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2916 spin_unlock_irq(&dev->event_lock);
2917
2918 return pending;
2919 }
2920
2921 static void intel_update_pipe_size(struct intel_crtc *crtc)
2922 {
2923 struct drm_device *dev = crtc->base.dev;
2924 struct drm_i915_private *dev_priv = dev->dev_private;
2925 const struct drm_display_mode *adjusted_mode;
2926
2927 if (!i915.fastboot)
2928 return;
2929
2930 /*
2931 * Update pipe size and adjust fitter if needed: the reason for this is
2932 * that in compute_mode_changes we check the native mode (not the pfit
2933 * mode) to see if we can flip rather than do a full mode set. In the
2934 * fastboot case, we'll flip, but if we don't update the pipesrc and
2935 * pfit state, we'll end up with a big fb scanned out into the wrong
2936 * sized surface.
2937 *
2938 * To fix this properly, we need to hoist the checks up into
2939 * compute_mode_changes (or above), check the actual pfit state and
2940 * whether the platform allows pfit disable with pipe active, and only
2941 * then update the pipesrc and pfit state, even on the flip path.
2942 */
2943
2944 adjusted_mode = &crtc->config->base.adjusted_mode;
2945
2946 I915_WRITE(PIPESRC(crtc->pipe),
2947 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2948 (adjusted_mode->crtc_vdisplay - 1));
2949 if (!crtc->config->pch_pfit.enabled &&
2950 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2951 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2952 I915_WRITE(PF_CTL(crtc->pipe), 0);
2953 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
2954 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
2955 }
2956 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
2957 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
2958 }
2959
2960 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2961 {
2962 struct drm_device *dev = crtc->dev;
2963 struct drm_i915_private *dev_priv = dev->dev_private;
2964 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2965 int pipe = intel_crtc->pipe;
2966 u32 reg, temp;
2967
2968 /* enable normal train */
2969 reg = FDI_TX_CTL(pipe);
2970 temp = I915_READ(reg);
2971 if (IS_IVYBRIDGE(dev)) {
2972 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2973 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2974 } else {
2975 temp &= ~FDI_LINK_TRAIN_NONE;
2976 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2977 }
2978 I915_WRITE(reg, temp);
2979
2980 reg = FDI_RX_CTL(pipe);
2981 temp = I915_READ(reg);
2982 if (HAS_PCH_CPT(dev)) {
2983 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2984 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2985 } else {
2986 temp &= ~FDI_LINK_TRAIN_NONE;
2987 temp |= FDI_LINK_TRAIN_NONE;
2988 }
2989 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2990
2991 /* wait one idle pattern time */
2992 POSTING_READ(reg);
2993 udelay(1000);
2994
2995 /* IVB wants error correction enabled */
2996 if (IS_IVYBRIDGE(dev))
2997 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2998 FDI_FE_ERRC_ENABLE);
2999 }
3000
3001 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
3002 {
3003 return crtc->base.enabled && crtc->active &&
3004 crtc->config->has_pch_encoder;
3005 }
3006
3007 static void ivb_modeset_global_resources(struct drm_device *dev)
3008 {
3009 struct drm_i915_private *dev_priv = dev->dev_private;
3010 struct intel_crtc *pipe_B_crtc =
3011 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3012 struct intel_crtc *pipe_C_crtc =
3013 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
3014 uint32_t temp;
3015
3016 /*
3017 * When everything is off disable fdi C so that we could enable fdi B
3018 * with all lanes. Note that we don't care about enabled pipes without
3019 * an enabled pch encoder.
3020 */
3021 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
3022 !pipe_has_enabled_pch(pipe_C_crtc)) {
3023 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3024 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3025
3026 temp = I915_READ(SOUTH_CHICKEN1);
3027 temp &= ~FDI_BC_BIFURCATION_SELECT;
3028 DRM_DEBUG_KMS("disabling fdi C rx\n");
3029 I915_WRITE(SOUTH_CHICKEN1, temp);
3030 }
3031 }
3032
3033 /* The FDI link training functions for ILK/Ibexpeak. */
3034 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3035 {
3036 struct drm_device *dev = crtc->dev;
3037 struct drm_i915_private *dev_priv = dev->dev_private;
3038 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3039 int pipe = intel_crtc->pipe;
3040 u32 reg, temp, tries;
3041
3042 /* FDI needs bits from pipe first */
3043 assert_pipe_enabled(dev_priv, pipe);
3044
3045 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3046 for train result */
3047 reg = FDI_RX_IMR(pipe);
3048 temp = I915_READ(reg);
3049 temp &= ~FDI_RX_SYMBOL_LOCK;
3050 temp &= ~FDI_RX_BIT_LOCK;
3051 I915_WRITE(reg, temp);
3052 I915_READ(reg);
3053 udelay(150);
3054
3055 /* enable CPU FDI TX and PCH FDI RX */
3056 reg = FDI_TX_CTL(pipe);
3057 temp = I915_READ(reg);
3058 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3059 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3060 temp &= ~FDI_LINK_TRAIN_NONE;
3061 temp |= FDI_LINK_TRAIN_PATTERN_1;
3062 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3063
3064 reg = FDI_RX_CTL(pipe);
3065 temp = I915_READ(reg);
3066 temp &= ~FDI_LINK_TRAIN_NONE;
3067 temp |= FDI_LINK_TRAIN_PATTERN_1;
3068 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3069
3070 POSTING_READ(reg);
3071 udelay(150);
3072
3073 /* Ironlake workaround, enable clock pointer after FDI enable*/
3074 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3075 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3076 FDI_RX_PHASE_SYNC_POINTER_EN);
3077
3078 reg = FDI_RX_IIR(pipe);
3079 for (tries = 0; tries < 5; tries++) {
3080 temp = I915_READ(reg);
3081 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3082
3083 if ((temp & FDI_RX_BIT_LOCK)) {
3084 DRM_DEBUG_KMS("FDI train 1 done.\n");
3085 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3086 break;
3087 }
3088 }
3089 if (tries == 5)
3090 DRM_ERROR("FDI train 1 fail!\n");
3091
3092 /* Train 2 */
3093 reg = FDI_TX_CTL(pipe);
3094 temp = I915_READ(reg);
3095 temp &= ~FDI_LINK_TRAIN_NONE;
3096 temp |= FDI_LINK_TRAIN_PATTERN_2;
3097 I915_WRITE(reg, temp);
3098
3099 reg = FDI_RX_CTL(pipe);
3100 temp = I915_READ(reg);
3101 temp &= ~FDI_LINK_TRAIN_NONE;
3102 temp |= FDI_LINK_TRAIN_PATTERN_2;
3103 I915_WRITE(reg, temp);
3104
3105 POSTING_READ(reg);
3106 udelay(150);
3107
3108 reg = FDI_RX_IIR(pipe);
3109 for (tries = 0; tries < 5; tries++) {
3110 temp = I915_READ(reg);
3111 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3112
3113 if (temp & FDI_RX_SYMBOL_LOCK) {
3114 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3115 DRM_DEBUG_KMS("FDI train 2 done.\n");
3116 break;
3117 }
3118 }
3119 if (tries == 5)
3120 DRM_ERROR("FDI train 2 fail!\n");
3121
3122 DRM_DEBUG_KMS("FDI train done\n");
3123
3124 }
3125
3126 static const int snb_b_fdi_train_param[] = {
3127 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3128 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3129 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3130 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3131 };
3132
3133 /* The FDI link training functions for SNB/Cougarpoint. */
3134 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3135 {
3136 struct drm_device *dev = crtc->dev;
3137 struct drm_i915_private *dev_priv = dev->dev_private;
3138 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3139 int pipe = intel_crtc->pipe;
3140 u32 reg, temp, i, retry;
3141
3142 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3143 for train result */
3144 reg = FDI_RX_IMR(pipe);
3145 temp = I915_READ(reg);
3146 temp &= ~FDI_RX_SYMBOL_LOCK;
3147 temp &= ~FDI_RX_BIT_LOCK;
3148 I915_WRITE(reg, temp);
3149
3150 POSTING_READ(reg);
3151 udelay(150);
3152
3153 /* enable CPU FDI TX and PCH FDI RX */
3154 reg = FDI_TX_CTL(pipe);
3155 temp = I915_READ(reg);
3156 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3157 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3158 temp &= ~FDI_LINK_TRAIN_NONE;
3159 temp |= FDI_LINK_TRAIN_PATTERN_1;
3160 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3161 /* SNB-B */
3162 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3163 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3164
3165 I915_WRITE(FDI_RX_MISC(pipe),
3166 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3167
3168 reg = FDI_RX_CTL(pipe);
3169 temp = I915_READ(reg);
3170 if (HAS_PCH_CPT(dev)) {
3171 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3172 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3173 } else {
3174 temp &= ~FDI_LINK_TRAIN_NONE;
3175 temp |= FDI_LINK_TRAIN_PATTERN_1;
3176 }
3177 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3178
3179 POSTING_READ(reg);
3180 udelay(150);
3181
3182 for (i = 0; i < 4; i++) {
3183 reg = FDI_TX_CTL(pipe);
3184 temp = I915_READ(reg);
3185 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3186 temp |= snb_b_fdi_train_param[i];
3187 I915_WRITE(reg, temp);
3188
3189 POSTING_READ(reg);
3190 udelay(500);
3191
3192 for (retry = 0; retry < 5; retry++) {
3193 reg = FDI_RX_IIR(pipe);
3194 temp = I915_READ(reg);
3195 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3196 if (temp & FDI_RX_BIT_LOCK) {
3197 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3198 DRM_DEBUG_KMS("FDI train 1 done.\n");
3199 break;
3200 }
3201 udelay(50);
3202 }
3203 if (retry < 5)
3204 break;
3205 }
3206 if (i == 4)
3207 DRM_ERROR("FDI train 1 fail!\n");
3208
3209 /* Train 2 */
3210 reg = FDI_TX_CTL(pipe);
3211 temp = I915_READ(reg);
3212 temp &= ~FDI_LINK_TRAIN_NONE;
3213 temp |= FDI_LINK_TRAIN_PATTERN_2;
3214 if (IS_GEN6(dev)) {
3215 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3216 /* SNB-B */
3217 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3218 }
3219 I915_WRITE(reg, temp);
3220
3221 reg = FDI_RX_CTL(pipe);
3222 temp = I915_READ(reg);
3223 if (HAS_PCH_CPT(dev)) {
3224 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3225 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3226 } else {
3227 temp &= ~FDI_LINK_TRAIN_NONE;
3228 temp |= FDI_LINK_TRAIN_PATTERN_2;
3229 }
3230 I915_WRITE(reg, temp);
3231
3232 POSTING_READ(reg);
3233 udelay(150);
3234
3235 for (i = 0; i < 4; i++) {
3236 reg = FDI_TX_CTL(pipe);
3237 temp = I915_READ(reg);
3238 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3239 temp |= snb_b_fdi_train_param[i];
3240 I915_WRITE(reg, temp);
3241
3242 POSTING_READ(reg);
3243 udelay(500);
3244
3245 for (retry = 0; retry < 5; retry++) {
3246 reg = FDI_RX_IIR(pipe);
3247 temp = I915_READ(reg);
3248 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3249 if (temp & FDI_RX_SYMBOL_LOCK) {
3250 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3251 DRM_DEBUG_KMS("FDI train 2 done.\n");
3252 break;
3253 }
3254 udelay(50);
3255 }
3256 if (retry < 5)
3257 break;
3258 }
3259 if (i == 4)
3260 DRM_ERROR("FDI train 2 fail!\n");
3261
3262 DRM_DEBUG_KMS("FDI train done.\n");
3263 }
3264
3265 /* Manual link training for Ivy Bridge A0 parts */
3266 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3267 {
3268 struct drm_device *dev = crtc->dev;
3269 struct drm_i915_private *dev_priv = dev->dev_private;
3270 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3271 int pipe = intel_crtc->pipe;
3272 u32 reg, temp, i, j;
3273
3274 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3275 for train result */
3276 reg = FDI_RX_IMR(pipe);
3277 temp = I915_READ(reg);
3278 temp &= ~FDI_RX_SYMBOL_LOCK;
3279 temp &= ~FDI_RX_BIT_LOCK;
3280 I915_WRITE(reg, temp);
3281
3282 POSTING_READ(reg);
3283 udelay(150);
3284
3285 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3286 I915_READ(FDI_RX_IIR(pipe)));
3287
3288 /* Try each vswing and preemphasis setting twice before moving on */
3289 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3290 /* disable first in case we need to retry */
3291 reg = FDI_TX_CTL(pipe);
3292 temp = I915_READ(reg);
3293 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3294 temp &= ~FDI_TX_ENABLE;
3295 I915_WRITE(reg, temp);
3296
3297 reg = FDI_RX_CTL(pipe);
3298 temp = I915_READ(reg);
3299 temp &= ~FDI_LINK_TRAIN_AUTO;
3300 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3301 temp &= ~FDI_RX_ENABLE;
3302 I915_WRITE(reg, temp);
3303
3304 /* enable CPU FDI TX and PCH FDI RX */
3305 reg = FDI_TX_CTL(pipe);
3306 temp = I915_READ(reg);
3307 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3308 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3309 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3310 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3311 temp |= snb_b_fdi_train_param[j/2];
3312 temp |= FDI_COMPOSITE_SYNC;
3313 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3314
3315 I915_WRITE(FDI_RX_MISC(pipe),
3316 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3317
3318 reg = FDI_RX_CTL(pipe);
3319 temp = I915_READ(reg);
3320 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3321 temp |= FDI_COMPOSITE_SYNC;
3322 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3323
3324 POSTING_READ(reg);
3325 udelay(1); /* should be 0.5us */
3326
3327 for (i = 0; i < 4; i++) {
3328 reg = FDI_RX_IIR(pipe);
3329 temp = I915_READ(reg);
3330 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3331
3332 if (temp & FDI_RX_BIT_LOCK ||
3333 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3334 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3335 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3336 i);
3337 break;
3338 }
3339 udelay(1); /* should be 0.5us */
3340 }
3341 if (i == 4) {
3342 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3343 continue;
3344 }
3345
3346 /* Train 2 */
3347 reg = FDI_TX_CTL(pipe);
3348 temp = I915_READ(reg);
3349 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3350 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3351 I915_WRITE(reg, temp);
3352
3353 reg = FDI_RX_CTL(pipe);
3354 temp = I915_READ(reg);
3355 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3356 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3357 I915_WRITE(reg, temp);
3358
3359 POSTING_READ(reg);
3360 udelay(2); /* should be 1.5us */
3361
3362 for (i = 0; i < 4; i++) {
3363 reg = FDI_RX_IIR(pipe);
3364 temp = I915_READ(reg);
3365 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3366
3367 if (temp & FDI_RX_SYMBOL_LOCK ||
3368 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3369 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3370 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3371 i);
3372 goto train_done;
3373 }
3374 udelay(2); /* should be 1.5us */
3375 }
3376 if (i == 4)
3377 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3378 }
3379
3380 train_done:
3381 DRM_DEBUG_KMS("FDI train done.\n");
3382 }
3383
3384 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3385 {
3386 struct drm_device *dev = intel_crtc->base.dev;
3387 struct drm_i915_private *dev_priv = dev->dev_private;
3388 int pipe = intel_crtc->pipe;
3389 u32 reg, temp;
3390
3391
3392 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3393 reg = FDI_RX_CTL(pipe);
3394 temp = I915_READ(reg);
3395 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3396 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3397 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3398 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3399
3400 POSTING_READ(reg);
3401 udelay(200);
3402
3403 /* Switch from Rawclk to PCDclk */
3404 temp = I915_READ(reg);
3405 I915_WRITE(reg, temp | FDI_PCDCLK);
3406
3407 POSTING_READ(reg);
3408 udelay(200);
3409
3410 /* Enable CPU FDI TX PLL, always on for Ironlake */
3411 reg = FDI_TX_CTL(pipe);
3412 temp = I915_READ(reg);
3413 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3414 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3415
3416 POSTING_READ(reg);
3417 udelay(100);
3418 }
3419 }
3420
3421 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3422 {
3423 struct drm_device *dev = intel_crtc->base.dev;
3424 struct drm_i915_private *dev_priv = dev->dev_private;
3425 int pipe = intel_crtc->pipe;
3426 u32 reg, temp;
3427
3428 /* Switch from PCDclk to Rawclk */
3429 reg = FDI_RX_CTL(pipe);
3430 temp = I915_READ(reg);
3431 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3432
3433 /* Disable CPU FDI TX PLL */
3434 reg = FDI_TX_CTL(pipe);
3435 temp = I915_READ(reg);
3436 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3437
3438 POSTING_READ(reg);
3439 udelay(100);
3440
3441 reg = FDI_RX_CTL(pipe);
3442 temp = I915_READ(reg);
3443 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3444
3445 /* Wait for the clocks to turn off. */
3446 POSTING_READ(reg);
3447 udelay(100);
3448 }
3449
3450 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3451 {
3452 struct drm_device *dev = crtc->dev;
3453 struct drm_i915_private *dev_priv = dev->dev_private;
3454 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3455 int pipe = intel_crtc->pipe;
3456 u32 reg, temp;
3457
3458 /* disable CPU FDI tx and PCH FDI rx */
3459 reg = FDI_TX_CTL(pipe);
3460 temp = I915_READ(reg);
3461 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3462 POSTING_READ(reg);
3463
3464 reg = FDI_RX_CTL(pipe);
3465 temp = I915_READ(reg);
3466 temp &= ~(0x7 << 16);
3467 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3468 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3469
3470 POSTING_READ(reg);
3471 udelay(100);
3472
3473 /* Ironlake workaround, disable clock pointer after downing FDI */
3474 if (HAS_PCH_IBX(dev))
3475 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3476
3477 /* still set train pattern 1 */
3478 reg = FDI_TX_CTL(pipe);
3479 temp = I915_READ(reg);
3480 temp &= ~FDI_LINK_TRAIN_NONE;
3481 temp |= FDI_LINK_TRAIN_PATTERN_1;
3482 I915_WRITE(reg, temp);
3483
3484 reg = FDI_RX_CTL(pipe);
3485 temp = I915_READ(reg);
3486 if (HAS_PCH_CPT(dev)) {
3487 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3488 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3489 } else {
3490 temp &= ~FDI_LINK_TRAIN_NONE;
3491 temp |= FDI_LINK_TRAIN_PATTERN_1;
3492 }
3493 /* BPC in FDI rx is consistent with that in PIPECONF */
3494 temp &= ~(0x07 << 16);
3495 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3496 I915_WRITE(reg, temp);
3497
3498 POSTING_READ(reg);
3499 udelay(100);
3500 }
3501
3502 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3503 {
3504 struct intel_crtc *crtc;
3505
3506 /* Note that we don't need to be called with mode_config.lock here
3507 * as our list of CRTC objects is static for the lifetime of the
3508 * device and so cannot disappear as we iterate. Similarly, we can
3509 * happily treat the predicates as racy, atomic checks as userspace
3510 * cannot claim and pin a new fb without at least acquring the
3511 * struct_mutex and so serialising with us.
3512 */
3513 for_each_intel_crtc(dev, crtc) {
3514 if (atomic_read(&crtc->unpin_work_count) == 0)
3515 continue;
3516
3517 if (crtc->unpin_work)
3518 intel_wait_for_vblank(dev, crtc->pipe);
3519
3520 return true;
3521 }
3522
3523 return false;
3524 }
3525
3526 static void page_flip_completed(struct intel_crtc *intel_crtc)
3527 {
3528 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3529 struct intel_unpin_work *work = intel_crtc->unpin_work;
3530
3531 /* ensure that the unpin work is consistent wrt ->pending. */
3532 smp_rmb();
3533 intel_crtc->unpin_work = NULL;
3534
3535 if (work->event)
3536 drm_send_vblank_event(intel_crtc->base.dev,
3537 intel_crtc->pipe,
3538 work->event);
3539
3540 drm_crtc_vblank_put(&intel_crtc->base);
3541
3542 wake_up_all(&dev_priv->pending_flip_queue);
3543 queue_work(dev_priv->wq, &work->work);
3544
3545 trace_i915_flip_complete(intel_crtc->plane,
3546 work->pending_flip_obj);
3547 }
3548
3549 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3550 {
3551 struct drm_device *dev = crtc->dev;
3552 struct drm_i915_private *dev_priv = dev->dev_private;
3553
3554 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3555 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3556 !intel_crtc_has_pending_flip(crtc),
3557 60*HZ) == 0)) {
3558 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3559
3560 spin_lock_irq(&dev->event_lock);
3561 if (intel_crtc->unpin_work) {
3562 WARN_ONCE(1, "Removing stuck page flip\n");
3563 page_flip_completed(intel_crtc);
3564 }
3565 spin_unlock_irq(&dev->event_lock);
3566 }
3567
3568 if (crtc->primary->fb) {
3569 mutex_lock(&dev->struct_mutex);
3570 intel_finish_fb(crtc->primary->fb);
3571 mutex_unlock(&dev->struct_mutex);
3572 }
3573 }
3574
3575 /* Program iCLKIP clock to the desired frequency */
3576 static void lpt_program_iclkip(struct drm_crtc *crtc)
3577 {
3578 struct drm_device *dev = crtc->dev;
3579 struct drm_i915_private *dev_priv = dev->dev_private;
3580 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3581 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3582 u32 temp;
3583
3584 mutex_lock(&dev_priv->dpio_lock);
3585
3586 /* It is necessary to ungate the pixclk gate prior to programming
3587 * the divisors, and gate it back when it is done.
3588 */
3589 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3590
3591 /* Disable SSCCTL */
3592 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3593 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3594 SBI_SSCCTL_DISABLE,
3595 SBI_ICLK);
3596
3597 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3598 if (clock == 20000) {
3599 auxdiv = 1;
3600 divsel = 0x41;
3601 phaseinc = 0x20;
3602 } else {
3603 /* The iCLK virtual clock root frequency is in MHz,
3604 * but the adjusted_mode->crtc_clock in in KHz. To get the
3605 * divisors, it is necessary to divide one by another, so we
3606 * convert the virtual clock precision to KHz here for higher
3607 * precision.
3608 */
3609 u32 iclk_virtual_root_freq = 172800 * 1000;
3610 u32 iclk_pi_range = 64;
3611 u32 desired_divisor, msb_divisor_value, pi_value;
3612
3613 desired_divisor = (iclk_virtual_root_freq / clock);
3614 msb_divisor_value = desired_divisor / iclk_pi_range;
3615 pi_value = desired_divisor % iclk_pi_range;
3616
3617 auxdiv = 0;
3618 divsel = msb_divisor_value - 2;
3619 phaseinc = pi_value;
3620 }
3621
3622 /* This should not happen with any sane values */
3623 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3624 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3625 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3626 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3627
3628 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3629 clock,
3630 auxdiv,
3631 divsel,
3632 phasedir,
3633 phaseinc);
3634
3635 /* Program SSCDIVINTPHASE6 */
3636 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3637 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3638 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3639 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3640 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3641 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3642 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3643 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3644
3645 /* Program SSCAUXDIV */
3646 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3647 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3648 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3649 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3650
3651 /* Enable modulator and associated divider */
3652 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3653 temp &= ~SBI_SSCCTL_DISABLE;
3654 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3655
3656 /* Wait for initialization time */
3657 udelay(24);
3658
3659 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3660
3661 mutex_unlock(&dev_priv->dpio_lock);
3662 }
3663
3664 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3665 enum pipe pch_transcoder)
3666 {
3667 struct drm_device *dev = crtc->base.dev;
3668 struct drm_i915_private *dev_priv = dev->dev_private;
3669 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3670
3671 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3672 I915_READ(HTOTAL(cpu_transcoder)));
3673 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3674 I915_READ(HBLANK(cpu_transcoder)));
3675 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3676 I915_READ(HSYNC(cpu_transcoder)));
3677
3678 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3679 I915_READ(VTOTAL(cpu_transcoder)));
3680 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3681 I915_READ(VBLANK(cpu_transcoder)));
3682 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3683 I915_READ(VSYNC(cpu_transcoder)));
3684 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3685 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3686 }
3687
3688 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3689 {
3690 struct drm_i915_private *dev_priv = dev->dev_private;
3691 uint32_t temp;
3692
3693 temp = I915_READ(SOUTH_CHICKEN1);
3694 if (temp & FDI_BC_BIFURCATION_SELECT)
3695 return;
3696
3697 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3698 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3699
3700 temp |= FDI_BC_BIFURCATION_SELECT;
3701 DRM_DEBUG_KMS("enabling fdi C rx\n");
3702 I915_WRITE(SOUTH_CHICKEN1, temp);
3703 POSTING_READ(SOUTH_CHICKEN1);
3704 }
3705
3706 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3707 {
3708 struct drm_device *dev = intel_crtc->base.dev;
3709 struct drm_i915_private *dev_priv = dev->dev_private;
3710
3711 switch (intel_crtc->pipe) {
3712 case PIPE_A:
3713 break;
3714 case PIPE_B:
3715 if (intel_crtc->config->fdi_lanes > 2)
3716 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3717 else
3718 cpt_enable_fdi_bc_bifurcation(dev);
3719
3720 break;
3721 case PIPE_C:
3722 cpt_enable_fdi_bc_bifurcation(dev);
3723
3724 break;
3725 default:
3726 BUG();
3727 }
3728 }
3729
3730 /*
3731 * Enable PCH resources required for PCH ports:
3732 * - PCH PLLs
3733 * - FDI training & RX/TX
3734 * - update transcoder timings
3735 * - DP transcoding bits
3736 * - transcoder
3737 */
3738 static void ironlake_pch_enable(struct drm_crtc *crtc)
3739 {
3740 struct drm_device *dev = crtc->dev;
3741 struct drm_i915_private *dev_priv = dev->dev_private;
3742 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3743 int pipe = intel_crtc->pipe;
3744 u32 reg, temp;
3745
3746 assert_pch_transcoder_disabled(dev_priv, pipe);
3747
3748 if (IS_IVYBRIDGE(dev))
3749 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3750
3751 /* Write the TU size bits before fdi link training, so that error
3752 * detection works. */
3753 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3754 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3755
3756 /* For PCH output, training FDI link */
3757 dev_priv->display.fdi_link_train(crtc);
3758
3759 /* We need to program the right clock selection before writing the pixel
3760 * mutliplier into the DPLL. */
3761 if (HAS_PCH_CPT(dev)) {
3762 u32 sel;
3763
3764 temp = I915_READ(PCH_DPLL_SEL);
3765 temp |= TRANS_DPLL_ENABLE(pipe);
3766 sel = TRANS_DPLLB_SEL(pipe);
3767 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
3768 temp |= sel;
3769 else
3770 temp &= ~sel;
3771 I915_WRITE(PCH_DPLL_SEL, temp);
3772 }
3773
3774 /* XXX: pch pll's can be enabled any time before we enable the PCH
3775 * transcoder, and we actually should do this to not upset any PCH
3776 * transcoder that already use the clock when we share it.
3777 *
3778 * Note that enable_shared_dpll tries to do the right thing, but
3779 * get_shared_dpll unconditionally resets the pll - we need that to have
3780 * the right LVDS enable sequence. */
3781 intel_enable_shared_dpll(intel_crtc);
3782
3783 /* set transcoder timing, panel must allow it */
3784 assert_panel_unlocked(dev_priv, pipe);
3785 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3786
3787 intel_fdi_normal_train(crtc);
3788
3789 /* For PCH DP, enable TRANS_DP_CTL */
3790 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
3791 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3792 reg = TRANS_DP_CTL(pipe);
3793 temp = I915_READ(reg);
3794 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3795 TRANS_DP_SYNC_MASK |
3796 TRANS_DP_BPC_MASK);
3797 temp |= (TRANS_DP_OUTPUT_ENABLE |
3798 TRANS_DP_ENH_FRAMING);
3799 temp |= bpc << 9; /* same format but at 11:9 */
3800
3801 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3802 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3803 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3804 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3805
3806 switch (intel_trans_dp_port_sel(crtc)) {
3807 case PCH_DP_B:
3808 temp |= TRANS_DP_PORT_SEL_B;
3809 break;
3810 case PCH_DP_C:
3811 temp |= TRANS_DP_PORT_SEL_C;
3812 break;
3813 case PCH_DP_D:
3814 temp |= TRANS_DP_PORT_SEL_D;
3815 break;
3816 default:
3817 BUG();
3818 }
3819
3820 I915_WRITE(reg, temp);
3821 }
3822
3823 ironlake_enable_pch_transcoder(dev_priv, pipe);
3824 }
3825
3826 static void lpt_pch_enable(struct drm_crtc *crtc)
3827 {
3828 struct drm_device *dev = crtc->dev;
3829 struct drm_i915_private *dev_priv = dev->dev_private;
3830 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3831 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
3832
3833 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3834
3835 lpt_program_iclkip(crtc);
3836
3837 /* Set transcoder timing. */
3838 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3839
3840 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3841 }
3842
3843 void intel_put_shared_dpll(struct intel_crtc *crtc)
3844 {
3845 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3846
3847 if (pll == NULL)
3848 return;
3849
3850 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
3851 WARN(1, "bad %s crtc mask\n", pll->name);
3852 return;
3853 }
3854
3855 pll->config.crtc_mask &= ~(1 << crtc->pipe);
3856 if (pll->config.crtc_mask == 0) {
3857 WARN_ON(pll->on);
3858 WARN_ON(pll->active);
3859 }
3860
3861 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
3862 }
3863
3864 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
3865 struct intel_crtc_state *crtc_state)
3866 {
3867 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3868 struct intel_shared_dpll *pll;
3869 enum intel_dpll_id i;
3870
3871 if (HAS_PCH_IBX(dev_priv->dev)) {
3872 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3873 i = (enum intel_dpll_id) crtc->pipe;
3874 pll = &dev_priv->shared_dplls[i];
3875
3876 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3877 crtc->base.base.id, pll->name);
3878
3879 WARN_ON(pll->new_config->crtc_mask);
3880
3881 goto found;
3882 }
3883
3884 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3885 pll = &dev_priv->shared_dplls[i];
3886
3887 /* Only want to check enabled timings first */
3888 if (pll->new_config->crtc_mask == 0)
3889 continue;
3890
3891 if (memcmp(&crtc_state->dpll_hw_state,
3892 &pll->new_config->hw_state,
3893 sizeof(pll->new_config->hw_state)) == 0) {
3894 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
3895 crtc->base.base.id, pll->name,
3896 pll->new_config->crtc_mask,
3897 pll->active);
3898 goto found;
3899 }
3900 }
3901
3902 /* Ok no matching timings, maybe there's a free one? */
3903 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3904 pll = &dev_priv->shared_dplls[i];
3905 if (pll->new_config->crtc_mask == 0) {
3906 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3907 crtc->base.base.id, pll->name);
3908 goto found;
3909 }
3910 }
3911
3912 return NULL;
3913
3914 found:
3915 if (pll->new_config->crtc_mask == 0)
3916 pll->new_config->hw_state = crtc_state->dpll_hw_state;
3917
3918 crtc_state->shared_dpll = i;
3919 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3920 pipe_name(crtc->pipe));
3921
3922 pll->new_config->crtc_mask |= 1 << crtc->pipe;
3923
3924 return pll;
3925 }
3926
3927 /**
3928 * intel_shared_dpll_start_config - start a new PLL staged config
3929 * @dev_priv: DRM device
3930 * @clear_pipes: mask of pipes that will have their PLLs freed
3931 *
3932 * Starts a new PLL staged config, copying the current config but
3933 * releasing the references of pipes specified in clear_pipes.
3934 */
3935 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
3936 unsigned clear_pipes)
3937 {
3938 struct intel_shared_dpll *pll;
3939 enum intel_dpll_id i;
3940
3941 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3942 pll = &dev_priv->shared_dplls[i];
3943
3944 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
3945 GFP_KERNEL);
3946 if (!pll->new_config)
3947 goto cleanup;
3948
3949 pll->new_config->crtc_mask &= ~clear_pipes;
3950 }
3951
3952 return 0;
3953
3954 cleanup:
3955 while (--i >= 0) {
3956 pll = &dev_priv->shared_dplls[i];
3957 kfree(pll->new_config);
3958 pll->new_config = NULL;
3959 }
3960
3961 return -ENOMEM;
3962 }
3963
3964 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
3965 {
3966 struct intel_shared_dpll *pll;
3967 enum intel_dpll_id i;
3968
3969 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3970 pll = &dev_priv->shared_dplls[i];
3971
3972 WARN_ON(pll->new_config == &pll->config);
3973
3974 pll->config = *pll->new_config;
3975 kfree(pll->new_config);
3976 pll->new_config = NULL;
3977 }
3978 }
3979
3980 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
3981 {
3982 struct intel_shared_dpll *pll;
3983 enum intel_dpll_id i;
3984
3985 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3986 pll = &dev_priv->shared_dplls[i];
3987
3988 WARN_ON(pll->new_config == &pll->config);
3989
3990 kfree(pll->new_config);
3991 pll->new_config = NULL;
3992 }
3993 }
3994
3995 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3996 {
3997 struct drm_i915_private *dev_priv = dev->dev_private;
3998 int dslreg = PIPEDSL(pipe);
3999 u32 temp;
4000
4001 temp = I915_READ(dslreg);
4002 udelay(500);
4003 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4004 if (wait_for(I915_READ(dslreg) != temp, 5))
4005 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4006 }
4007 }
4008
4009 static void skylake_pfit_enable(struct intel_crtc *crtc)
4010 {
4011 struct drm_device *dev = crtc->base.dev;
4012 struct drm_i915_private *dev_priv = dev->dev_private;
4013 int pipe = crtc->pipe;
4014
4015 if (crtc->config->pch_pfit.enabled) {
4016 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
4017 I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4018 I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4019 }
4020 }
4021
4022 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4023 {
4024 struct drm_device *dev = crtc->base.dev;
4025 struct drm_i915_private *dev_priv = dev->dev_private;
4026 int pipe = crtc->pipe;
4027
4028 if (crtc->config->pch_pfit.enabled) {
4029 /* Force use of hard-coded filter coefficients
4030 * as some pre-programmed values are broken,
4031 * e.g. x201.
4032 */
4033 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4034 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4035 PF_PIPE_SEL_IVB(pipe));
4036 else
4037 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4038 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4039 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4040 }
4041 }
4042
4043 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4044 {
4045 struct drm_device *dev = crtc->dev;
4046 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4047 struct drm_plane *plane;
4048 struct intel_plane *intel_plane;
4049
4050 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4051 intel_plane = to_intel_plane(plane);
4052 if (intel_plane->pipe == pipe)
4053 intel_plane_restore(&intel_plane->base);
4054 }
4055 }
4056
4057 static void intel_disable_sprite_planes(struct drm_crtc *crtc)
4058 {
4059 struct drm_device *dev = crtc->dev;
4060 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4061 struct drm_plane *plane;
4062 struct intel_plane *intel_plane;
4063
4064 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4065 intel_plane = to_intel_plane(plane);
4066 if (intel_plane->pipe == pipe)
4067 plane->funcs->disable_plane(plane);
4068 }
4069 }
4070
4071 void hsw_enable_ips(struct intel_crtc *crtc)
4072 {
4073 struct drm_device *dev = crtc->base.dev;
4074 struct drm_i915_private *dev_priv = dev->dev_private;
4075
4076 if (!crtc->config->ips_enabled)
4077 return;
4078
4079 /* We can only enable IPS after we enable a plane and wait for a vblank */
4080 intel_wait_for_vblank(dev, crtc->pipe);
4081
4082 assert_plane_enabled(dev_priv, crtc->plane);
4083 if (IS_BROADWELL(dev)) {
4084 mutex_lock(&dev_priv->rps.hw_lock);
4085 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4086 mutex_unlock(&dev_priv->rps.hw_lock);
4087 /* Quoting Art Runyan: "its not safe to expect any particular
4088 * value in IPS_CTL bit 31 after enabling IPS through the
4089 * mailbox." Moreover, the mailbox may return a bogus state,
4090 * so we need to just enable it and continue on.
4091 */
4092 } else {
4093 I915_WRITE(IPS_CTL, IPS_ENABLE);
4094 /* The bit only becomes 1 in the next vblank, so this wait here
4095 * is essentially intel_wait_for_vblank. If we don't have this
4096 * and don't wait for vblanks until the end of crtc_enable, then
4097 * the HW state readout code will complain that the expected
4098 * IPS_CTL value is not the one we read. */
4099 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4100 DRM_ERROR("Timed out waiting for IPS enable\n");
4101 }
4102 }
4103
4104 void hsw_disable_ips(struct intel_crtc *crtc)
4105 {
4106 struct drm_device *dev = crtc->base.dev;
4107 struct drm_i915_private *dev_priv = dev->dev_private;
4108
4109 if (!crtc->config->ips_enabled)
4110 return;
4111
4112 assert_plane_enabled(dev_priv, crtc->plane);
4113 if (IS_BROADWELL(dev)) {
4114 mutex_lock(&dev_priv->rps.hw_lock);
4115 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4116 mutex_unlock(&dev_priv->rps.hw_lock);
4117 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4118 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4119 DRM_ERROR("Timed out waiting for IPS disable\n");
4120 } else {
4121 I915_WRITE(IPS_CTL, 0);
4122 POSTING_READ(IPS_CTL);
4123 }
4124
4125 /* We need to wait for a vblank before we can disable the plane. */
4126 intel_wait_for_vblank(dev, crtc->pipe);
4127 }
4128
4129 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4130 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4131 {
4132 struct drm_device *dev = crtc->dev;
4133 struct drm_i915_private *dev_priv = dev->dev_private;
4134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4135 enum pipe pipe = intel_crtc->pipe;
4136 int palreg = PALETTE(pipe);
4137 int i;
4138 bool reenable_ips = false;
4139
4140 /* The clocks have to be on to load the palette. */
4141 if (!crtc->enabled || !intel_crtc->active)
4142 return;
4143
4144 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4145 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4146 assert_dsi_pll_enabled(dev_priv);
4147 else
4148 assert_pll_enabled(dev_priv, pipe);
4149 }
4150
4151 /* use legacy palette for Ironlake */
4152 if (!HAS_GMCH_DISPLAY(dev))
4153 palreg = LGC_PALETTE(pipe);
4154
4155 /* Workaround : Do not read or write the pipe palette/gamma data while
4156 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4157 */
4158 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4159 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4160 GAMMA_MODE_MODE_SPLIT)) {
4161 hsw_disable_ips(intel_crtc);
4162 reenable_ips = true;
4163 }
4164
4165 for (i = 0; i < 256; i++) {
4166 I915_WRITE(palreg + 4 * i,
4167 (intel_crtc->lut_r[i] << 16) |
4168 (intel_crtc->lut_g[i] << 8) |
4169 intel_crtc->lut_b[i]);
4170 }
4171
4172 if (reenable_ips)
4173 hsw_enable_ips(intel_crtc);
4174 }
4175
4176 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4177 {
4178 if (!enable && intel_crtc->overlay) {
4179 struct drm_device *dev = intel_crtc->base.dev;
4180 struct drm_i915_private *dev_priv = dev->dev_private;
4181
4182 mutex_lock(&dev->struct_mutex);
4183 dev_priv->mm.interruptible = false;
4184 (void) intel_overlay_switch_off(intel_crtc->overlay);
4185 dev_priv->mm.interruptible = true;
4186 mutex_unlock(&dev->struct_mutex);
4187 }
4188
4189 /* Let userspace switch the overlay on again. In most cases userspace
4190 * has to recompute where to put it anyway.
4191 */
4192 }
4193
4194 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4195 {
4196 struct drm_device *dev = crtc->dev;
4197 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4198 int pipe = intel_crtc->pipe;
4199
4200 intel_enable_primary_hw_plane(crtc->primary, crtc);
4201 intel_enable_sprite_planes(crtc);
4202 intel_crtc_update_cursor(crtc, true);
4203 intel_crtc_dpms_overlay(intel_crtc, true);
4204
4205 hsw_enable_ips(intel_crtc);
4206
4207 mutex_lock(&dev->struct_mutex);
4208 intel_fbc_update(dev);
4209 mutex_unlock(&dev->struct_mutex);
4210
4211 /*
4212 * FIXME: Once we grow proper nuclear flip support out of this we need
4213 * to compute the mask of flip planes precisely. For the time being
4214 * consider this a flip from a NULL plane.
4215 */
4216 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4217 }
4218
4219 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4220 {
4221 struct drm_device *dev = crtc->dev;
4222 struct drm_i915_private *dev_priv = dev->dev_private;
4223 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4224 int pipe = intel_crtc->pipe;
4225 int plane = intel_crtc->plane;
4226
4227 intel_crtc_wait_for_pending_flips(crtc);
4228
4229 if (dev_priv->fbc.plane == plane)
4230 intel_fbc_disable(dev);
4231
4232 hsw_disable_ips(intel_crtc);
4233
4234 intel_crtc_dpms_overlay(intel_crtc, false);
4235 intel_crtc_update_cursor(crtc, false);
4236 intel_disable_sprite_planes(crtc);
4237 intel_disable_primary_hw_plane(crtc->primary, crtc);
4238
4239 /*
4240 * FIXME: Once we grow proper nuclear flip support out of this we need
4241 * to compute the mask of flip planes precisely. For the time being
4242 * consider this a flip to a NULL plane.
4243 */
4244 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4245 }
4246
4247 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4248 {
4249 struct drm_device *dev = crtc->dev;
4250 struct drm_i915_private *dev_priv = dev->dev_private;
4251 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4252 struct intel_encoder *encoder;
4253 int pipe = intel_crtc->pipe;
4254
4255 WARN_ON(!crtc->enabled);
4256
4257 if (intel_crtc->active)
4258 return;
4259
4260 if (intel_crtc->config->has_pch_encoder)
4261 intel_prepare_shared_dpll(intel_crtc);
4262
4263 if (intel_crtc->config->has_dp_encoder)
4264 intel_dp_set_m_n(intel_crtc);
4265
4266 intel_set_pipe_timings(intel_crtc);
4267
4268 if (intel_crtc->config->has_pch_encoder) {
4269 intel_cpu_transcoder_set_m_n(intel_crtc,
4270 &intel_crtc->config->fdi_m_n, NULL);
4271 }
4272
4273 ironlake_set_pipeconf(crtc);
4274
4275 intel_crtc->active = true;
4276
4277 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4278 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4279
4280 for_each_encoder_on_crtc(dev, crtc, encoder)
4281 if (encoder->pre_enable)
4282 encoder->pre_enable(encoder);
4283
4284 if (intel_crtc->config->has_pch_encoder) {
4285 /* Note: FDI PLL enabling _must_ be done before we enable the
4286 * cpu pipes, hence this is separate from all the other fdi/pch
4287 * enabling. */
4288 ironlake_fdi_pll_enable(intel_crtc);
4289 } else {
4290 assert_fdi_tx_disabled(dev_priv, pipe);
4291 assert_fdi_rx_disabled(dev_priv, pipe);
4292 }
4293
4294 ironlake_pfit_enable(intel_crtc);
4295
4296 /*
4297 * On ILK+ LUT must be loaded before the pipe is running but with
4298 * clocks enabled
4299 */
4300 intel_crtc_load_lut(crtc);
4301
4302 intel_update_watermarks(crtc);
4303 intel_enable_pipe(intel_crtc);
4304
4305 if (intel_crtc->config->has_pch_encoder)
4306 ironlake_pch_enable(crtc);
4307
4308 assert_vblank_disabled(crtc);
4309 drm_crtc_vblank_on(crtc);
4310
4311 for_each_encoder_on_crtc(dev, crtc, encoder)
4312 encoder->enable(encoder);
4313
4314 if (HAS_PCH_CPT(dev))
4315 cpt_verify_modeset(dev, intel_crtc->pipe);
4316
4317 intel_crtc_enable_planes(crtc);
4318 }
4319
4320 /* IPS only exists on ULT machines and is tied to pipe A. */
4321 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4322 {
4323 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4324 }
4325
4326 /*
4327 * This implements the workaround described in the "notes" section of the mode
4328 * set sequence documentation. When going from no pipes or single pipe to
4329 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4330 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4331 */
4332 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4333 {
4334 struct drm_device *dev = crtc->base.dev;
4335 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4336
4337 /* We want to get the other_active_crtc only if there's only 1 other
4338 * active crtc. */
4339 for_each_intel_crtc(dev, crtc_it) {
4340 if (!crtc_it->active || crtc_it == crtc)
4341 continue;
4342
4343 if (other_active_crtc)
4344 return;
4345
4346 other_active_crtc = crtc_it;
4347 }
4348 if (!other_active_crtc)
4349 return;
4350
4351 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4352 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4353 }
4354
4355 static void haswell_crtc_enable(struct drm_crtc *crtc)
4356 {
4357 struct drm_device *dev = crtc->dev;
4358 struct drm_i915_private *dev_priv = dev->dev_private;
4359 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4360 struct intel_encoder *encoder;
4361 int pipe = intel_crtc->pipe;
4362
4363 WARN_ON(!crtc->enabled);
4364
4365 if (intel_crtc->active)
4366 return;
4367
4368 if (intel_crtc_to_shared_dpll(intel_crtc))
4369 intel_enable_shared_dpll(intel_crtc);
4370
4371 if (intel_crtc->config->has_dp_encoder)
4372 intel_dp_set_m_n(intel_crtc);
4373
4374 intel_set_pipe_timings(intel_crtc);
4375
4376 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4377 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4378 intel_crtc->config->pixel_multiplier - 1);
4379 }
4380
4381 if (intel_crtc->config->has_pch_encoder) {
4382 intel_cpu_transcoder_set_m_n(intel_crtc,
4383 &intel_crtc->config->fdi_m_n, NULL);
4384 }
4385
4386 haswell_set_pipeconf(crtc);
4387
4388 intel_set_pipe_csc(crtc);
4389
4390 intel_crtc->active = true;
4391
4392 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4393 for_each_encoder_on_crtc(dev, crtc, encoder)
4394 if (encoder->pre_enable)
4395 encoder->pre_enable(encoder);
4396
4397 if (intel_crtc->config->has_pch_encoder) {
4398 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4399 true);
4400 dev_priv->display.fdi_link_train(crtc);
4401 }
4402
4403 intel_ddi_enable_pipe_clock(intel_crtc);
4404
4405 if (IS_SKYLAKE(dev))
4406 skylake_pfit_enable(intel_crtc);
4407 else
4408 ironlake_pfit_enable(intel_crtc);
4409
4410 /*
4411 * On ILK+ LUT must be loaded before the pipe is running but with
4412 * clocks enabled
4413 */
4414 intel_crtc_load_lut(crtc);
4415
4416 intel_ddi_set_pipe_settings(crtc);
4417 intel_ddi_enable_transcoder_func(crtc);
4418
4419 intel_update_watermarks(crtc);
4420 intel_enable_pipe(intel_crtc);
4421
4422 if (intel_crtc->config->has_pch_encoder)
4423 lpt_pch_enable(crtc);
4424
4425 if (intel_crtc->config->dp_encoder_is_mst)
4426 intel_ddi_set_vc_payload_alloc(crtc, true);
4427
4428 assert_vblank_disabled(crtc);
4429 drm_crtc_vblank_on(crtc);
4430
4431 for_each_encoder_on_crtc(dev, crtc, encoder) {
4432 encoder->enable(encoder);
4433 intel_opregion_notify_encoder(encoder, true);
4434 }
4435
4436 /* If we change the relative order between pipe/planes enabling, we need
4437 * to change the workaround. */
4438 haswell_mode_set_planes_workaround(intel_crtc);
4439 intel_crtc_enable_planes(crtc);
4440 }
4441
4442 static void skylake_pfit_disable(struct intel_crtc *crtc)
4443 {
4444 struct drm_device *dev = crtc->base.dev;
4445 struct drm_i915_private *dev_priv = dev->dev_private;
4446 int pipe = crtc->pipe;
4447
4448 /* To avoid upsetting the power well on haswell only disable the pfit if
4449 * it's in use. The hw state code will make sure we get this right. */
4450 if (crtc->config->pch_pfit.enabled) {
4451 I915_WRITE(PS_CTL(pipe), 0);
4452 I915_WRITE(PS_WIN_POS(pipe), 0);
4453 I915_WRITE(PS_WIN_SZ(pipe), 0);
4454 }
4455 }
4456
4457 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4458 {
4459 struct drm_device *dev = crtc->base.dev;
4460 struct drm_i915_private *dev_priv = dev->dev_private;
4461 int pipe = crtc->pipe;
4462
4463 /* To avoid upsetting the power well on haswell only disable the pfit if
4464 * it's in use. The hw state code will make sure we get this right. */
4465 if (crtc->config->pch_pfit.enabled) {
4466 I915_WRITE(PF_CTL(pipe), 0);
4467 I915_WRITE(PF_WIN_POS(pipe), 0);
4468 I915_WRITE(PF_WIN_SZ(pipe), 0);
4469 }
4470 }
4471
4472 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4473 {
4474 struct drm_device *dev = crtc->dev;
4475 struct drm_i915_private *dev_priv = dev->dev_private;
4476 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4477 struct intel_encoder *encoder;
4478 int pipe = intel_crtc->pipe;
4479 u32 reg, temp;
4480
4481 if (!intel_crtc->active)
4482 return;
4483
4484 intel_crtc_disable_planes(crtc);
4485
4486 for_each_encoder_on_crtc(dev, crtc, encoder)
4487 encoder->disable(encoder);
4488
4489 drm_crtc_vblank_off(crtc);
4490 assert_vblank_disabled(crtc);
4491
4492 if (intel_crtc->config->has_pch_encoder)
4493 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4494
4495 intel_disable_pipe(intel_crtc);
4496
4497 ironlake_pfit_disable(intel_crtc);
4498
4499 for_each_encoder_on_crtc(dev, crtc, encoder)
4500 if (encoder->post_disable)
4501 encoder->post_disable(encoder);
4502
4503 if (intel_crtc->config->has_pch_encoder) {
4504 ironlake_fdi_disable(crtc);
4505
4506 ironlake_disable_pch_transcoder(dev_priv, pipe);
4507
4508 if (HAS_PCH_CPT(dev)) {
4509 /* disable TRANS_DP_CTL */
4510 reg = TRANS_DP_CTL(pipe);
4511 temp = I915_READ(reg);
4512 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4513 TRANS_DP_PORT_SEL_MASK);
4514 temp |= TRANS_DP_PORT_SEL_NONE;
4515 I915_WRITE(reg, temp);
4516
4517 /* disable DPLL_SEL */
4518 temp = I915_READ(PCH_DPLL_SEL);
4519 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4520 I915_WRITE(PCH_DPLL_SEL, temp);
4521 }
4522
4523 /* disable PCH DPLL */
4524 intel_disable_shared_dpll(intel_crtc);
4525
4526 ironlake_fdi_pll_disable(intel_crtc);
4527 }
4528
4529 intel_crtc->active = false;
4530 intel_update_watermarks(crtc);
4531
4532 mutex_lock(&dev->struct_mutex);
4533 intel_fbc_update(dev);
4534 mutex_unlock(&dev->struct_mutex);
4535 }
4536
4537 static void haswell_crtc_disable(struct drm_crtc *crtc)
4538 {
4539 struct drm_device *dev = crtc->dev;
4540 struct drm_i915_private *dev_priv = dev->dev_private;
4541 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4542 struct intel_encoder *encoder;
4543 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4544
4545 if (!intel_crtc->active)
4546 return;
4547
4548 intel_crtc_disable_planes(crtc);
4549
4550 for_each_encoder_on_crtc(dev, crtc, encoder) {
4551 intel_opregion_notify_encoder(encoder, false);
4552 encoder->disable(encoder);
4553 }
4554
4555 drm_crtc_vblank_off(crtc);
4556 assert_vblank_disabled(crtc);
4557
4558 if (intel_crtc->config->has_pch_encoder)
4559 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4560 false);
4561 intel_disable_pipe(intel_crtc);
4562
4563 if (intel_crtc->config->dp_encoder_is_mst)
4564 intel_ddi_set_vc_payload_alloc(crtc, false);
4565
4566 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4567
4568 if (IS_SKYLAKE(dev))
4569 skylake_pfit_disable(intel_crtc);
4570 else
4571 ironlake_pfit_disable(intel_crtc);
4572
4573 intel_ddi_disable_pipe_clock(intel_crtc);
4574
4575 if (intel_crtc->config->has_pch_encoder) {
4576 lpt_disable_pch_transcoder(dev_priv);
4577 intel_ddi_fdi_disable(crtc);
4578 }
4579
4580 for_each_encoder_on_crtc(dev, crtc, encoder)
4581 if (encoder->post_disable)
4582 encoder->post_disable(encoder);
4583
4584 intel_crtc->active = false;
4585 intel_update_watermarks(crtc);
4586
4587 mutex_lock(&dev->struct_mutex);
4588 intel_fbc_update(dev);
4589 mutex_unlock(&dev->struct_mutex);
4590
4591 if (intel_crtc_to_shared_dpll(intel_crtc))
4592 intel_disable_shared_dpll(intel_crtc);
4593 }
4594
4595 static void ironlake_crtc_off(struct drm_crtc *crtc)
4596 {
4597 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4598 intel_put_shared_dpll(intel_crtc);
4599 }
4600
4601
4602 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4603 {
4604 struct drm_device *dev = crtc->base.dev;
4605 struct drm_i915_private *dev_priv = dev->dev_private;
4606 struct intel_crtc_state *pipe_config = crtc->config;
4607
4608 if (!pipe_config->gmch_pfit.control)
4609 return;
4610
4611 /*
4612 * The panel fitter should only be adjusted whilst the pipe is disabled,
4613 * according to register description and PRM.
4614 */
4615 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4616 assert_pipe_disabled(dev_priv, crtc->pipe);
4617
4618 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4619 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4620
4621 /* Border color in case we don't scale up to the full screen. Black by
4622 * default, change to something else for debugging. */
4623 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4624 }
4625
4626 static enum intel_display_power_domain port_to_power_domain(enum port port)
4627 {
4628 switch (port) {
4629 case PORT_A:
4630 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4631 case PORT_B:
4632 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4633 case PORT_C:
4634 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4635 case PORT_D:
4636 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4637 default:
4638 WARN_ON_ONCE(1);
4639 return POWER_DOMAIN_PORT_OTHER;
4640 }
4641 }
4642
4643 #define for_each_power_domain(domain, mask) \
4644 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4645 if ((1 << (domain)) & (mask))
4646
4647 enum intel_display_power_domain
4648 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4649 {
4650 struct drm_device *dev = intel_encoder->base.dev;
4651 struct intel_digital_port *intel_dig_port;
4652
4653 switch (intel_encoder->type) {
4654 case INTEL_OUTPUT_UNKNOWN:
4655 /* Only DDI platforms should ever use this output type */
4656 WARN_ON_ONCE(!HAS_DDI(dev));
4657 case INTEL_OUTPUT_DISPLAYPORT:
4658 case INTEL_OUTPUT_HDMI:
4659 case INTEL_OUTPUT_EDP:
4660 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4661 return port_to_power_domain(intel_dig_port->port);
4662 case INTEL_OUTPUT_DP_MST:
4663 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4664 return port_to_power_domain(intel_dig_port->port);
4665 case INTEL_OUTPUT_ANALOG:
4666 return POWER_DOMAIN_PORT_CRT;
4667 case INTEL_OUTPUT_DSI:
4668 return POWER_DOMAIN_PORT_DSI;
4669 default:
4670 return POWER_DOMAIN_PORT_OTHER;
4671 }
4672 }
4673
4674 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4675 {
4676 struct drm_device *dev = crtc->dev;
4677 struct intel_encoder *intel_encoder;
4678 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4679 enum pipe pipe = intel_crtc->pipe;
4680 unsigned long mask;
4681 enum transcoder transcoder;
4682
4683 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4684
4685 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4686 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4687 if (intel_crtc->config->pch_pfit.enabled ||
4688 intel_crtc->config->pch_pfit.force_thru)
4689 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4690
4691 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4692 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4693
4694 return mask;
4695 }
4696
4697 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4698 {
4699 struct drm_i915_private *dev_priv = dev->dev_private;
4700 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4701 struct intel_crtc *crtc;
4702
4703 /*
4704 * First get all needed power domains, then put all unneeded, to avoid
4705 * any unnecessary toggling of the power wells.
4706 */
4707 for_each_intel_crtc(dev, crtc) {
4708 enum intel_display_power_domain domain;
4709
4710 if (!crtc->base.enabled)
4711 continue;
4712
4713 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4714
4715 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4716 intel_display_power_get(dev_priv, domain);
4717 }
4718
4719 if (dev_priv->display.modeset_global_resources)
4720 dev_priv->display.modeset_global_resources(dev);
4721
4722 for_each_intel_crtc(dev, crtc) {
4723 enum intel_display_power_domain domain;
4724
4725 for_each_power_domain(domain, crtc->enabled_power_domains)
4726 intel_display_power_put(dev_priv, domain);
4727
4728 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4729 }
4730
4731 intel_display_set_init_power(dev_priv, false);
4732 }
4733
4734 /* returns HPLL frequency in kHz */
4735 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4736 {
4737 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4738
4739 /* Obtain SKU information */
4740 mutex_lock(&dev_priv->dpio_lock);
4741 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4742 CCK_FUSE_HPLL_FREQ_MASK;
4743 mutex_unlock(&dev_priv->dpio_lock);
4744
4745 return vco_freq[hpll_freq] * 1000;
4746 }
4747
4748 static void vlv_update_cdclk(struct drm_device *dev)
4749 {
4750 struct drm_i915_private *dev_priv = dev->dev_private;
4751
4752 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4753 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4754 dev_priv->vlv_cdclk_freq);
4755
4756 /*
4757 * Program the gmbus_freq based on the cdclk frequency.
4758 * BSpec erroneously claims we should aim for 4MHz, but
4759 * in fact 1MHz is the correct frequency.
4760 */
4761 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
4762 }
4763
4764 /* Adjust CDclk dividers to allow high res or save power if possible */
4765 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4766 {
4767 struct drm_i915_private *dev_priv = dev->dev_private;
4768 u32 val, cmd;
4769
4770 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4771
4772 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4773 cmd = 2;
4774 else if (cdclk == 266667)
4775 cmd = 1;
4776 else
4777 cmd = 0;
4778
4779 mutex_lock(&dev_priv->rps.hw_lock);
4780 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4781 val &= ~DSPFREQGUAR_MASK;
4782 val |= (cmd << DSPFREQGUAR_SHIFT);
4783 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4784 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4785 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4786 50)) {
4787 DRM_ERROR("timed out waiting for CDclk change\n");
4788 }
4789 mutex_unlock(&dev_priv->rps.hw_lock);
4790
4791 if (cdclk == 400000) {
4792 u32 divider;
4793
4794 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
4795
4796 mutex_lock(&dev_priv->dpio_lock);
4797 /* adjust cdclk divider */
4798 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4799 val &= ~DISPLAY_FREQUENCY_VALUES;
4800 val |= divider;
4801 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4802
4803 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4804 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4805 50))
4806 DRM_ERROR("timed out waiting for CDclk change\n");
4807 mutex_unlock(&dev_priv->dpio_lock);
4808 }
4809
4810 mutex_lock(&dev_priv->dpio_lock);
4811 /* adjust self-refresh exit latency value */
4812 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4813 val &= ~0x7f;
4814
4815 /*
4816 * For high bandwidth configs, we set a higher latency in the bunit
4817 * so that the core display fetch happens in time to avoid underruns.
4818 */
4819 if (cdclk == 400000)
4820 val |= 4500 / 250; /* 4.5 usec */
4821 else
4822 val |= 3000 / 250; /* 3.0 usec */
4823 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4824 mutex_unlock(&dev_priv->dpio_lock);
4825
4826 vlv_update_cdclk(dev);
4827 }
4828
4829 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4830 {
4831 struct drm_i915_private *dev_priv = dev->dev_private;
4832 u32 val, cmd;
4833
4834 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4835
4836 switch (cdclk) {
4837 case 400000:
4838 cmd = 3;
4839 break;
4840 case 333333:
4841 case 320000:
4842 cmd = 2;
4843 break;
4844 case 266667:
4845 cmd = 1;
4846 break;
4847 case 200000:
4848 cmd = 0;
4849 break;
4850 default:
4851 MISSING_CASE(cdclk);
4852 return;
4853 }
4854
4855 mutex_lock(&dev_priv->rps.hw_lock);
4856 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4857 val &= ~DSPFREQGUAR_MASK_CHV;
4858 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4859 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4860 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4861 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4862 50)) {
4863 DRM_ERROR("timed out waiting for CDclk change\n");
4864 }
4865 mutex_unlock(&dev_priv->rps.hw_lock);
4866
4867 vlv_update_cdclk(dev);
4868 }
4869
4870 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4871 int max_pixclk)
4872 {
4873 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
4874
4875 /* FIXME: Punit isn't quite ready yet */
4876 if (IS_CHERRYVIEW(dev_priv->dev))
4877 return 400000;
4878
4879 /*
4880 * Really only a few cases to deal with, as only 4 CDclks are supported:
4881 * 200MHz
4882 * 267MHz
4883 * 320/333MHz (depends on HPLL freq)
4884 * 400MHz
4885 * So we check to see whether we're above 90% of the lower bin and
4886 * adjust if needed.
4887 *
4888 * We seem to get an unstable or solid color picture at 200MHz.
4889 * Not sure what's wrong. For now use 200MHz only when all pipes
4890 * are off.
4891 */
4892 if (max_pixclk > freq_320*9/10)
4893 return 400000;
4894 else if (max_pixclk > 266667*9/10)
4895 return freq_320;
4896 else if (max_pixclk > 0)
4897 return 266667;
4898 else
4899 return 200000;
4900 }
4901
4902 /* compute the max pixel clock for new configuration */
4903 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4904 {
4905 struct drm_device *dev = dev_priv->dev;
4906 struct intel_crtc *intel_crtc;
4907 int max_pixclk = 0;
4908
4909 for_each_intel_crtc(dev, intel_crtc) {
4910 if (intel_crtc->new_enabled)
4911 max_pixclk = max(max_pixclk,
4912 intel_crtc->new_config->base.adjusted_mode.crtc_clock);
4913 }
4914
4915 return max_pixclk;
4916 }
4917
4918 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4919 unsigned *prepare_pipes)
4920 {
4921 struct drm_i915_private *dev_priv = dev->dev_private;
4922 struct intel_crtc *intel_crtc;
4923 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4924
4925 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4926 dev_priv->vlv_cdclk_freq)
4927 return;
4928
4929 /* disable/enable all currently active pipes while we change cdclk */
4930 for_each_intel_crtc(dev, intel_crtc)
4931 if (intel_crtc->base.enabled)
4932 *prepare_pipes |= (1 << intel_crtc->pipe);
4933 }
4934
4935 static void valleyview_modeset_global_resources(struct drm_device *dev)
4936 {
4937 struct drm_i915_private *dev_priv = dev->dev_private;
4938 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4939 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4940
4941 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4942 /*
4943 * FIXME: We can end up here with all power domains off, yet
4944 * with a CDCLK frequency other than the minimum. To account
4945 * for this take the PIPE-A power domain, which covers the HW
4946 * blocks needed for the following programming. This can be
4947 * removed once it's guaranteed that we get here either with
4948 * the minimum CDCLK set, or the required power domains
4949 * enabled.
4950 */
4951 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
4952
4953 if (IS_CHERRYVIEW(dev))
4954 cherryview_set_cdclk(dev, req_cdclk);
4955 else
4956 valleyview_set_cdclk(dev, req_cdclk);
4957
4958 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
4959 }
4960 }
4961
4962 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4963 {
4964 struct drm_device *dev = crtc->dev;
4965 struct drm_i915_private *dev_priv = to_i915(dev);
4966 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4967 struct intel_encoder *encoder;
4968 int pipe = intel_crtc->pipe;
4969 bool is_dsi;
4970
4971 WARN_ON(!crtc->enabled);
4972
4973 if (intel_crtc->active)
4974 return;
4975
4976 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
4977
4978 if (!is_dsi) {
4979 if (IS_CHERRYVIEW(dev))
4980 chv_prepare_pll(intel_crtc, intel_crtc->config);
4981 else
4982 vlv_prepare_pll(intel_crtc, intel_crtc->config);
4983 }
4984
4985 if (intel_crtc->config->has_dp_encoder)
4986 intel_dp_set_m_n(intel_crtc);
4987
4988 intel_set_pipe_timings(intel_crtc);
4989
4990 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
4991 struct drm_i915_private *dev_priv = dev->dev_private;
4992
4993 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
4994 I915_WRITE(CHV_CANVAS(pipe), 0);
4995 }
4996
4997 i9xx_set_pipeconf(intel_crtc);
4998
4999 intel_crtc->active = true;
5000
5001 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5002
5003 for_each_encoder_on_crtc(dev, crtc, encoder)
5004 if (encoder->pre_pll_enable)
5005 encoder->pre_pll_enable(encoder);
5006
5007 if (!is_dsi) {
5008 if (IS_CHERRYVIEW(dev))
5009 chv_enable_pll(intel_crtc, intel_crtc->config);
5010 else
5011 vlv_enable_pll(intel_crtc, intel_crtc->config);
5012 }
5013
5014 for_each_encoder_on_crtc(dev, crtc, encoder)
5015 if (encoder->pre_enable)
5016 encoder->pre_enable(encoder);
5017
5018 i9xx_pfit_enable(intel_crtc);
5019
5020 intel_crtc_load_lut(crtc);
5021
5022 intel_update_watermarks(crtc);
5023 intel_enable_pipe(intel_crtc);
5024
5025 assert_vblank_disabled(crtc);
5026 drm_crtc_vblank_on(crtc);
5027
5028 for_each_encoder_on_crtc(dev, crtc, encoder)
5029 encoder->enable(encoder);
5030
5031 intel_crtc_enable_planes(crtc);
5032
5033 /* Underruns don't raise interrupts, so check manually. */
5034 i9xx_check_fifo_underruns(dev_priv);
5035 }
5036
5037 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5038 {
5039 struct drm_device *dev = crtc->base.dev;
5040 struct drm_i915_private *dev_priv = dev->dev_private;
5041
5042 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5043 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5044 }
5045
5046 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5047 {
5048 struct drm_device *dev = crtc->dev;
5049 struct drm_i915_private *dev_priv = to_i915(dev);
5050 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5051 struct intel_encoder *encoder;
5052 int pipe = intel_crtc->pipe;
5053
5054 WARN_ON(!crtc->enabled);
5055
5056 if (intel_crtc->active)
5057 return;
5058
5059 i9xx_set_pll_dividers(intel_crtc);
5060
5061 if (intel_crtc->config->has_dp_encoder)
5062 intel_dp_set_m_n(intel_crtc);
5063
5064 intel_set_pipe_timings(intel_crtc);
5065
5066 i9xx_set_pipeconf(intel_crtc);
5067
5068 intel_crtc->active = true;
5069
5070 if (!IS_GEN2(dev))
5071 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5072
5073 for_each_encoder_on_crtc(dev, crtc, encoder)
5074 if (encoder->pre_enable)
5075 encoder->pre_enable(encoder);
5076
5077 i9xx_enable_pll(intel_crtc);
5078
5079 i9xx_pfit_enable(intel_crtc);
5080
5081 intel_crtc_load_lut(crtc);
5082
5083 intel_update_watermarks(crtc);
5084 intel_enable_pipe(intel_crtc);
5085
5086 assert_vblank_disabled(crtc);
5087 drm_crtc_vblank_on(crtc);
5088
5089 for_each_encoder_on_crtc(dev, crtc, encoder)
5090 encoder->enable(encoder);
5091
5092 intel_crtc_enable_planes(crtc);
5093
5094 /*
5095 * Gen2 reports pipe underruns whenever all planes are disabled.
5096 * So don't enable underrun reporting before at least some planes
5097 * are enabled.
5098 * FIXME: Need to fix the logic to work when we turn off all planes
5099 * but leave the pipe running.
5100 */
5101 if (IS_GEN2(dev))
5102 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5103
5104 /* Underruns don't raise interrupts, so check manually. */
5105 i9xx_check_fifo_underruns(dev_priv);
5106 }
5107
5108 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5109 {
5110 struct drm_device *dev = crtc->base.dev;
5111 struct drm_i915_private *dev_priv = dev->dev_private;
5112
5113 if (!crtc->config->gmch_pfit.control)
5114 return;
5115
5116 assert_pipe_disabled(dev_priv, crtc->pipe);
5117
5118 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5119 I915_READ(PFIT_CONTROL));
5120 I915_WRITE(PFIT_CONTROL, 0);
5121 }
5122
5123 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5124 {
5125 struct drm_device *dev = crtc->dev;
5126 struct drm_i915_private *dev_priv = dev->dev_private;
5127 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5128 struct intel_encoder *encoder;
5129 int pipe = intel_crtc->pipe;
5130
5131 if (!intel_crtc->active)
5132 return;
5133
5134 /*
5135 * Gen2 reports pipe underruns whenever all planes are disabled.
5136 * So diasble underrun reporting before all the planes get disabled.
5137 * FIXME: Need to fix the logic to work when we turn off all planes
5138 * but leave the pipe running.
5139 */
5140 if (IS_GEN2(dev))
5141 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5142
5143 /*
5144 * Vblank time updates from the shadow to live plane control register
5145 * are blocked if the memory self-refresh mode is active at that
5146 * moment. So to make sure the plane gets truly disabled, disable
5147 * first the self-refresh mode. The self-refresh enable bit in turn
5148 * will be checked/applied by the HW only at the next frame start
5149 * event which is after the vblank start event, so we need to have a
5150 * wait-for-vblank between disabling the plane and the pipe.
5151 */
5152 intel_set_memory_cxsr(dev_priv, false);
5153 intel_crtc_disable_planes(crtc);
5154
5155 /*
5156 * On gen2 planes are double buffered but the pipe isn't, so we must
5157 * wait for planes to fully turn off before disabling the pipe.
5158 * We also need to wait on all gmch platforms because of the
5159 * self-refresh mode constraint explained above.
5160 */
5161 intel_wait_for_vblank(dev, pipe);
5162
5163 for_each_encoder_on_crtc(dev, crtc, encoder)
5164 encoder->disable(encoder);
5165
5166 drm_crtc_vblank_off(crtc);
5167 assert_vblank_disabled(crtc);
5168
5169 intel_disable_pipe(intel_crtc);
5170
5171 i9xx_pfit_disable(intel_crtc);
5172
5173 for_each_encoder_on_crtc(dev, crtc, encoder)
5174 if (encoder->post_disable)
5175 encoder->post_disable(encoder);
5176
5177 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5178 if (IS_CHERRYVIEW(dev))
5179 chv_disable_pll(dev_priv, pipe);
5180 else if (IS_VALLEYVIEW(dev))
5181 vlv_disable_pll(dev_priv, pipe);
5182 else
5183 i9xx_disable_pll(intel_crtc);
5184 }
5185
5186 if (!IS_GEN2(dev))
5187 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5188
5189 intel_crtc->active = false;
5190 intel_update_watermarks(crtc);
5191
5192 mutex_lock(&dev->struct_mutex);
5193 intel_fbc_update(dev);
5194 mutex_unlock(&dev->struct_mutex);
5195 }
5196
5197 static void i9xx_crtc_off(struct drm_crtc *crtc)
5198 {
5199 }
5200
5201 /* Master function to enable/disable CRTC and corresponding power wells */
5202 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5203 {
5204 struct drm_device *dev = crtc->dev;
5205 struct drm_i915_private *dev_priv = dev->dev_private;
5206 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5207 enum intel_display_power_domain domain;
5208 unsigned long domains;
5209
5210 if (enable) {
5211 if (!intel_crtc->active) {
5212 domains = get_crtc_power_domains(crtc);
5213 for_each_power_domain(domain, domains)
5214 intel_display_power_get(dev_priv, domain);
5215 intel_crtc->enabled_power_domains = domains;
5216
5217 dev_priv->display.crtc_enable(crtc);
5218 }
5219 } else {
5220 if (intel_crtc->active) {
5221 dev_priv->display.crtc_disable(crtc);
5222
5223 domains = intel_crtc->enabled_power_domains;
5224 for_each_power_domain(domain, domains)
5225 intel_display_power_put(dev_priv, domain);
5226 intel_crtc->enabled_power_domains = 0;
5227 }
5228 }
5229 }
5230
5231 /**
5232 * Sets the power management mode of the pipe and plane.
5233 */
5234 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5235 {
5236 struct drm_device *dev = crtc->dev;
5237 struct intel_encoder *intel_encoder;
5238 bool enable = false;
5239
5240 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5241 enable |= intel_encoder->connectors_active;
5242
5243 intel_crtc_control(crtc, enable);
5244 }
5245
5246 static void intel_crtc_disable(struct drm_crtc *crtc)
5247 {
5248 struct drm_device *dev = crtc->dev;
5249 struct drm_connector *connector;
5250 struct drm_i915_private *dev_priv = dev->dev_private;
5251
5252 /* crtc should still be enabled when we disable it. */
5253 WARN_ON(!crtc->enabled);
5254
5255 dev_priv->display.crtc_disable(crtc);
5256 dev_priv->display.off(crtc);
5257
5258 crtc->primary->funcs->disable_plane(crtc->primary);
5259
5260 /* Update computed state. */
5261 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5262 if (!connector->encoder || !connector->encoder->crtc)
5263 continue;
5264
5265 if (connector->encoder->crtc != crtc)
5266 continue;
5267
5268 connector->dpms = DRM_MODE_DPMS_OFF;
5269 to_intel_encoder(connector->encoder)->connectors_active = false;
5270 }
5271 }
5272
5273 void intel_encoder_destroy(struct drm_encoder *encoder)
5274 {
5275 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5276
5277 drm_encoder_cleanup(encoder);
5278 kfree(intel_encoder);
5279 }
5280
5281 /* Simple dpms helper for encoders with just one connector, no cloning and only
5282 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5283 * state of the entire output pipe. */
5284 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5285 {
5286 if (mode == DRM_MODE_DPMS_ON) {
5287 encoder->connectors_active = true;
5288
5289 intel_crtc_update_dpms(encoder->base.crtc);
5290 } else {
5291 encoder->connectors_active = false;
5292
5293 intel_crtc_update_dpms(encoder->base.crtc);
5294 }
5295 }
5296
5297 /* Cross check the actual hw state with our own modeset state tracking (and it's
5298 * internal consistency). */
5299 static void intel_connector_check_state(struct intel_connector *connector)
5300 {
5301 if (connector->get_hw_state(connector)) {
5302 struct intel_encoder *encoder = connector->encoder;
5303 struct drm_crtc *crtc;
5304 bool encoder_enabled;
5305 enum pipe pipe;
5306
5307 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5308 connector->base.base.id,
5309 connector->base.name);
5310
5311 /* there is no real hw state for MST connectors */
5312 if (connector->mst_port)
5313 return;
5314
5315 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5316 "wrong connector dpms state\n");
5317 I915_STATE_WARN(connector->base.encoder != &encoder->base,
5318 "active connector not linked to encoder\n");
5319
5320 if (encoder) {
5321 I915_STATE_WARN(!encoder->connectors_active,
5322 "encoder->connectors_active not set\n");
5323
5324 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5325 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
5326 if (I915_STATE_WARN_ON(!encoder->base.crtc))
5327 return;
5328
5329 crtc = encoder->base.crtc;
5330
5331 I915_STATE_WARN(!crtc->enabled, "crtc not enabled\n");
5332 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5333 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
5334 "encoder active on the wrong pipe\n");
5335 }
5336 }
5337 }
5338
5339 /* Even simpler default implementation, if there's really no special case to
5340 * consider. */
5341 void intel_connector_dpms(struct drm_connector *connector, int mode)
5342 {
5343 /* All the simple cases only support two dpms states. */
5344 if (mode != DRM_MODE_DPMS_ON)
5345 mode = DRM_MODE_DPMS_OFF;
5346
5347 if (mode == connector->dpms)
5348 return;
5349
5350 connector->dpms = mode;
5351
5352 /* Only need to change hw state when actually enabled */
5353 if (connector->encoder)
5354 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5355
5356 intel_modeset_check_state(connector->dev);
5357 }
5358
5359 /* Simple connector->get_hw_state implementation for encoders that support only
5360 * one connector and no cloning and hence the encoder state determines the state
5361 * of the connector. */
5362 bool intel_connector_get_hw_state(struct intel_connector *connector)
5363 {
5364 enum pipe pipe = 0;
5365 struct intel_encoder *encoder = connector->encoder;
5366
5367 return encoder->get_hw_state(encoder, &pipe);
5368 }
5369
5370 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5371 struct intel_crtc_state *pipe_config)
5372 {
5373 struct drm_i915_private *dev_priv = dev->dev_private;
5374 struct intel_crtc *pipe_B_crtc =
5375 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5376
5377 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5378 pipe_name(pipe), pipe_config->fdi_lanes);
5379 if (pipe_config->fdi_lanes > 4) {
5380 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5381 pipe_name(pipe), pipe_config->fdi_lanes);
5382 return false;
5383 }
5384
5385 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5386 if (pipe_config->fdi_lanes > 2) {
5387 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5388 pipe_config->fdi_lanes);
5389 return false;
5390 } else {
5391 return true;
5392 }
5393 }
5394
5395 if (INTEL_INFO(dev)->num_pipes == 2)
5396 return true;
5397
5398 /* Ivybridge 3 pipe is really complicated */
5399 switch (pipe) {
5400 case PIPE_A:
5401 return true;
5402 case PIPE_B:
5403 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5404 pipe_config->fdi_lanes > 2) {
5405 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5406 pipe_name(pipe), pipe_config->fdi_lanes);
5407 return false;
5408 }
5409 return true;
5410 case PIPE_C:
5411 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5412 pipe_B_crtc->config->fdi_lanes <= 2) {
5413 if (pipe_config->fdi_lanes > 2) {
5414 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5415 pipe_name(pipe), pipe_config->fdi_lanes);
5416 return false;
5417 }
5418 } else {
5419 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5420 return false;
5421 }
5422 return true;
5423 default:
5424 BUG();
5425 }
5426 }
5427
5428 #define RETRY 1
5429 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5430 struct intel_crtc_state *pipe_config)
5431 {
5432 struct drm_device *dev = intel_crtc->base.dev;
5433 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5434 int lane, link_bw, fdi_dotclock;
5435 bool setup_ok, needs_recompute = false;
5436
5437 retry:
5438 /* FDI is a binary signal running at ~2.7GHz, encoding
5439 * each output octet as 10 bits. The actual frequency
5440 * is stored as a divider into a 100MHz clock, and the
5441 * mode pixel clock is stored in units of 1KHz.
5442 * Hence the bw of each lane in terms of the mode signal
5443 * is:
5444 */
5445 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5446
5447 fdi_dotclock = adjusted_mode->crtc_clock;
5448
5449 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5450 pipe_config->pipe_bpp);
5451
5452 pipe_config->fdi_lanes = lane;
5453
5454 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5455 link_bw, &pipe_config->fdi_m_n);
5456
5457 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5458 intel_crtc->pipe, pipe_config);
5459 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5460 pipe_config->pipe_bpp -= 2*3;
5461 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5462 pipe_config->pipe_bpp);
5463 needs_recompute = true;
5464 pipe_config->bw_constrained = true;
5465
5466 goto retry;
5467 }
5468
5469 if (needs_recompute)
5470 return RETRY;
5471
5472 return setup_ok ? 0 : -EINVAL;
5473 }
5474
5475 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5476 struct intel_crtc_state *pipe_config)
5477 {
5478 pipe_config->ips_enabled = i915.enable_ips &&
5479 hsw_crtc_supports_ips(crtc) &&
5480 pipe_config->pipe_bpp <= 24;
5481 }
5482
5483 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5484 struct intel_crtc_state *pipe_config)
5485 {
5486 struct drm_device *dev = crtc->base.dev;
5487 struct drm_i915_private *dev_priv = dev->dev_private;
5488 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5489
5490 /* FIXME should check pixel clock limits on all platforms */
5491 if (INTEL_INFO(dev)->gen < 4) {
5492 int clock_limit =
5493 dev_priv->display.get_display_clock_speed(dev);
5494
5495 /*
5496 * Enable pixel doubling when the dot clock
5497 * is > 90% of the (display) core speed.
5498 *
5499 * GDG double wide on either pipe,
5500 * otherwise pipe A only.
5501 */
5502 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5503 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5504 clock_limit *= 2;
5505 pipe_config->double_wide = true;
5506 }
5507
5508 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5509 return -EINVAL;
5510 }
5511
5512 /*
5513 * Pipe horizontal size must be even in:
5514 * - DVO ganged mode
5515 * - LVDS dual channel mode
5516 * - Double wide pipe
5517 */
5518 if ((intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5519 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5520 pipe_config->pipe_src_w &= ~1;
5521
5522 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5523 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5524 */
5525 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5526 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5527 return -EINVAL;
5528
5529 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5530 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5531 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5532 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5533 * for lvds. */
5534 pipe_config->pipe_bpp = 8*3;
5535 }
5536
5537 if (HAS_IPS(dev))
5538 hsw_compute_ips_config(crtc, pipe_config);
5539
5540 if (pipe_config->has_pch_encoder)
5541 return ironlake_fdi_compute_config(crtc, pipe_config);
5542
5543 return 0;
5544 }
5545
5546 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5547 {
5548 struct drm_i915_private *dev_priv = dev->dev_private;
5549 u32 val;
5550 int divider;
5551
5552 /* FIXME: Punit isn't quite ready yet */
5553 if (IS_CHERRYVIEW(dev))
5554 return 400000;
5555
5556 if (dev_priv->hpll_freq == 0)
5557 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5558
5559 mutex_lock(&dev_priv->dpio_lock);
5560 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5561 mutex_unlock(&dev_priv->dpio_lock);
5562
5563 divider = val & DISPLAY_FREQUENCY_VALUES;
5564
5565 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5566 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5567 "cdclk change in progress\n");
5568
5569 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
5570 }
5571
5572 static int i945_get_display_clock_speed(struct drm_device *dev)
5573 {
5574 return 400000;
5575 }
5576
5577 static int i915_get_display_clock_speed(struct drm_device *dev)
5578 {
5579 return 333000;
5580 }
5581
5582 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5583 {
5584 return 200000;
5585 }
5586
5587 static int pnv_get_display_clock_speed(struct drm_device *dev)
5588 {
5589 u16 gcfgc = 0;
5590
5591 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5592
5593 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5594 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5595 return 267000;
5596 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5597 return 333000;
5598 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5599 return 444000;
5600 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5601 return 200000;
5602 default:
5603 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5604 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5605 return 133000;
5606 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5607 return 167000;
5608 }
5609 }
5610
5611 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5612 {
5613 u16 gcfgc = 0;
5614
5615 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5616
5617 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5618 return 133000;
5619 else {
5620 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5621 case GC_DISPLAY_CLOCK_333_MHZ:
5622 return 333000;
5623 default:
5624 case GC_DISPLAY_CLOCK_190_200_MHZ:
5625 return 190000;
5626 }
5627 }
5628 }
5629
5630 static int i865_get_display_clock_speed(struct drm_device *dev)
5631 {
5632 return 266000;
5633 }
5634
5635 static int i855_get_display_clock_speed(struct drm_device *dev)
5636 {
5637 u16 hpllcc = 0;
5638 /* Assume that the hardware is in the high speed state. This
5639 * should be the default.
5640 */
5641 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5642 case GC_CLOCK_133_200:
5643 case GC_CLOCK_100_200:
5644 return 200000;
5645 case GC_CLOCK_166_250:
5646 return 250000;
5647 case GC_CLOCK_100_133:
5648 return 133000;
5649 }
5650
5651 /* Shouldn't happen */
5652 return 0;
5653 }
5654
5655 static int i830_get_display_clock_speed(struct drm_device *dev)
5656 {
5657 return 133000;
5658 }
5659
5660 static void
5661 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5662 {
5663 while (*num > DATA_LINK_M_N_MASK ||
5664 *den > DATA_LINK_M_N_MASK) {
5665 *num >>= 1;
5666 *den >>= 1;
5667 }
5668 }
5669
5670 static void compute_m_n(unsigned int m, unsigned int n,
5671 uint32_t *ret_m, uint32_t *ret_n)
5672 {
5673 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5674 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5675 intel_reduce_m_n_ratio(ret_m, ret_n);
5676 }
5677
5678 void
5679 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5680 int pixel_clock, int link_clock,
5681 struct intel_link_m_n *m_n)
5682 {
5683 m_n->tu = 64;
5684
5685 compute_m_n(bits_per_pixel * pixel_clock,
5686 link_clock * nlanes * 8,
5687 &m_n->gmch_m, &m_n->gmch_n);
5688
5689 compute_m_n(pixel_clock, link_clock,
5690 &m_n->link_m, &m_n->link_n);
5691 }
5692
5693 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5694 {
5695 if (i915.panel_use_ssc >= 0)
5696 return i915.panel_use_ssc != 0;
5697 return dev_priv->vbt.lvds_use_ssc
5698 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5699 }
5700
5701 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5702 {
5703 struct drm_device *dev = crtc->base.dev;
5704 struct drm_i915_private *dev_priv = dev->dev_private;
5705 int refclk;
5706
5707 if (IS_VALLEYVIEW(dev)) {
5708 refclk = 100000;
5709 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5710 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5711 refclk = dev_priv->vbt.lvds_ssc_freq;
5712 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5713 } else if (!IS_GEN2(dev)) {
5714 refclk = 96000;
5715 } else {
5716 refclk = 48000;
5717 }
5718
5719 return refclk;
5720 }
5721
5722 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5723 {
5724 return (1 << dpll->n) << 16 | dpll->m2;
5725 }
5726
5727 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5728 {
5729 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5730 }
5731
5732 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5733 struct intel_crtc_state *crtc_state,
5734 intel_clock_t *reduced_clock)
5735 {
5736 struct drm_device *dev = crtc->base.dev;
5737 u32 fp, fp2 = 0;
5738
5739 if (IS_PINEVIEW(dev)) {
5740 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
5741 if (reduced_clock)
5742 fp2 = pnv_dpll_compute_fp(reduced_clock);
5743 } else {
5744 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
5745 if (reduced_clock)
5746 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5747 }
5748
5749 crtc_state->dpll_hw_state.fp0 = fp;
5750
5751 crtc->lowfreq_avail = false;
5752 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5753 reduced_clock && i915.powersave) {
5754 crtc_state->dpll_hw_state.fp1 = fp2;
5755 crtc->lowfreq_avail = true;
5756 } else {
5757 crtc_state->dpll_hw_state.fp1 = fp;
5758 }
5759 }
5760
5761 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5762 pipe)
5763 {
5764 u32 reg_val;
5765
5766 /*
5767 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5768 * and set it to a reasonable value instead.
5769 */
5770 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5771 reg_val &= 0xffffff00;
5772 reg_val |= 0x00000030;
5773 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5774
5775 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5776 reg_val &= 0x8cffffff;
5777 reg_val = 0x8c000000;
5778 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5779
5780 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5781 reg_val &= 0xffffff00;
5782 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5783
5784 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5785 reg_val &= 0x00ffffff;
5786 reg_val |= 0xb0000000;
5787 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5788 }
5789
5790 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5791 struct intel_link_m_n *m_n)
5792 {
5793 struct drm_device *dev = crtc->base.dev;
5794 struct drm_i915_private *dev_priv = dev->dev_private;
5795 int pipe = crtc->pipe;
5796
5797 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5798 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5799 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5800 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5801 }
5802
5803 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5804 struct intel_link_m_n *m_n,
5805 struct intel_link_m_n *m2_n2)
5806 {
5807 struct drm_device *dev = crtc->base.dev;
5808 struct drm_i915_private *dev_priv = dev->dev_private;
5809 int pipe = crtc->pipe;
5810 enum transcoder transcoder = crtc->config->cpu_transcoder;
5811
5812 if (INTEL_INFO(dev)->gen >= 5) {
5813 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5814 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5815 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5816 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5817 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5818 * for gen < 8) and if DRRS is supported (to make sure the
5819 * registers are not unnecessarily accessed).
5820 */
5821 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5822 crtc->config->has_drrs) {
5823 I915_WRITE(PIPE_DATA_M2(transcoder),
5824 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5825 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5826 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5827 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5828 }
5829 } else {
5830 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5831 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5832 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5833 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5834 }
5835 }
5836
5837 void intel_dp_set_m_n(struct intel_crtc *crtc)
5838 {
5839 if (crtc->config->has_pch_encoder)
5840 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
5841 else
5842 intel_cpu_transcoder_set_m_n(crtc, &crtc->config->dp_m_n,
5843 &crtc->config->dp_m2_n2);
5844 }
5845
5846 static void vlv_update_pll(struct intel_crtc *crtc,
5847 struct intel_crtc_state *pipe_config)
5848 {
5849 u32 dpll, dpll_md;
5850
5851 /*
5852 * Enable DPIO clock input. We should never disable the reference
5853 * clock for pipe B, since VGA hotplug / manual detection depends
5854 * on it.
5855 */
5856 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5857 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5858 /* We should never disable this, set it here for state tracking */
5859 if (crtc->pipe == PIPE_B)
5860 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5861 dpll |= DPLL_VCO_ENABLE;
5862 pipe_config->dpll_hw_state.dpll = dpll;
5863
5864 dpll_md = (pipe_config->pixel_multiplier - 1)
5865 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5866 pipe_config->dpll_hw_state.dpll_md = dpll_md;
5867 }
5868
5869 static void vlv_prepare_pll(struct intel_crtc *crtc,
5870 const struct intel_crtc_state *pipe_config)
5871 {
5872 struct drm_device *dev = crtc->base.dev;
5873 struct drm_i915_private *dev_priv = dev->dev_private;
5874 int pipe = crtc->pipe;
5875 u32 mdiv;
5876 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5877 u32 coreclk, reg_val;
5878
5879 mutex_lock(&dev_priv->dpio_lock);
5880
5881 bestn = pipe_config->dpll.n;
5882 bestm1 = pipe_config->dpll.m1;
5883 bestm2 = pipe_config->dpll.m2;
5884 bestp1 = pipe_config->dpll.p1;
5885 bestp2 = pipe_config->dpll.p2;
5886
5887 /* See eDP HDMI DPIO driver vbios notes doc */
5888
5889 /* PLL B needs special handling */
5890 if (pipe == PIPE_B)
5891 vlv_pllb_recal_opamp(dev_priv, pipe);
5892
5893 /* Set up Tx target for periodic Rcomp update */
5894 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5895
5896 /* Disable target IRef on PLL */
5897 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5898 reg_val &= 0x00ffffff;
5899 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5900
5901 /* Disable fast lock */
5902 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5903
5904 /* Set idtafcrecal before PLL is enabled */
5905 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5906 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5907 mdiv |= ((bestn << DPIO_N_SHIFT));
5908 mdiv |= (1 << DPIO_K_SHIFT);
5909
5910 /*
5911 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5912 * but we don't support that).
5913 * Note: don't use the DAC post divider as it seems unstable.
5914 */
5915 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5916 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5917
5918 mdiv |= DPIO_ENABLE_CALIBRATION;
5919 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5920
5921 /* Set HBR and RBR LPF coefficients */
5922 if (pipe_config->port_clock == 162000 ||
5923 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
5924 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
5925 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5926 0x009f0003);
5927 else
5928 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5929 0x00d0000f);
5930
5931 if (pipe_config->has_dp_encoder) {
5932 /* Use SSC source */
5933 if (pipe == PIPE_A)
5934 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5935 0x0df40000);
5936 else
5937 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5938 0x0df70000);
5939 } else { /* HDMI or VGA */
5940 /* Use bend source */
5941 if (pipe == PIPE_A)
5942 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5943 0x0df70000);
5944 else
5945 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5946 0x0df40000);
5947 }
5948
5949 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5950 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5951 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
5952 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5953 coreclk |= 0x01000000;
5954 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5955
5956 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5957 mutex_unlock(&dev_priv->dpio_lock);
5958 }
5959
5960 static void chv_update_pll(struct intel_crtc *crtc,
5961 struct intel_crtc_state *pipe_config)
5962 {
5963 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5964 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5965 DPLL_VCO_ENABLE;
5966 if (crtc->pipe != PIPE_A)
5967 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5968
5969 pipe_config->dpll_hw_state.dpll_md =
5970 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5971 }
5972
5973 static void chv_prepare_pll(struct intel_crtc *crtc,
5974 const struct intel_crtc_state *pipe_config)
5975 {
5976 struct drm_device *dev = crtc->base.dev;
5977 struct drm_i915_private *dev_priv = dev->dev_private;
5978 int pipe = crtc->pipe;
5979 int dpll_reg = DPLL(crtc->pipe);
5980 enum dpio_channel port = vlv_pipe_to_channel(pipe);
5981 u32 loopfilter, intcoeff;
5982 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5983 int refclk;
5984
5985 bestn = pipe_config->dpll.n;
5986 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
5987 bestm1 = pipe_config->dpll.m1;
5988 bestm2 = pipe_config->dpll.m2 >> 22;
5989 bestp1 = pipe_config->dpll.p1;
5990 bestp2 = pipe_config->dpll.p2;
5991
5992 /*
5993 * Enable Refclk and SSC
5994 */
5995 I915_WRITE(dpll_reg,
5996 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5997
5998 mutex_lock(&dev_priv->dpio_lock);
5999
6000 /* p1 and p2 divider */
6001 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6002 5 << DPIO_CHV_S1_DIV_SHIFT |
6003 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6004 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6005 1 << DPIO_CHV_K_DIV_SHIFT);
6006
6007 /* Feedback post-divider - m2 */
6008 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6009
6010 /* Feedback refclk divider - n and m1 */
6011 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6012 DPIO_CHV_M1_DIV_BY_2 |
6013 1 << DPIO_CHV_N_DIV_SHIFT);
6014
6015 /* M2 fraction division */
6016 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6017
6018 /* M2 fraction division enable */
6019 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
6020 DPIO_CHV_FRAC_DIV_EN |
6021 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
6022
6023 /* Loop filter */
6024 refclk = i9xx_get_refclk(crtc, 0);
6025 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
6026 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
6027 if (refclk == 100000)
6028 intcoeff = 11;
6029 else if (refclk == 38400)
6030 intcoeff = 10;
6031 else
6032 intcoeff = 9;
6033 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
6034 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6035
6036 /* AFC Recal */
6037 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6038 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6039 DPIO_AFC_RECAL);
6040
6041 mutex_unlock(&dev_priv->dpio_lock);
6042 }
6043
6044 /**
6045 * vlv_force_pll_on - forcibly enable just the PLL
6046 * @dev_priv: i915 private structure
6047 * @pipe: pipe PLL to enable
6048 * @dpll: PLL configuration
6049 *
6050 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6051 * in cases where we need the PLL enabled even when @pipe is not going to
6052 * be enabled.
6053 */
6054 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6055 const struct dpll *dpll)
6056 {
6057 struct intel_crtc *crtc =
6058 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6059 struct intel_crtc_state pipe_config = {
6060 .pixel_multiplier = 1,
6061 .dpll = *dpll,
6062 };
6063
6064 if (IS_CHERRYVIEW(dev)) {
6065 chv_update_pll(crtc, &pipe_config);
6066 chv_prepare_pll(crtc, &pipe_config);
6067 chv_enable_pll(crtc, &pipe_config);
6068 } else {
6069 vlv_update_pll(crtc, &pipe_config);
6070 vlv_prepare_pll(crtc, &pipe_config);
6071 vlv_enable_pll(crtc, &pipe_config);
6072 }
6073 }
6074
6075 /**
6076 * vlv_force_pll_off - forcibly disable just the PLL
6077 * @dev_priv: i915 private structure
6078 * @pipe: pipe PLL to disable
6079 *
6080 * Disable the PLL for @pipe. To be used in cases where we need
6081 * the PLL enabled even when @pipe is not going to be enabled.
6082 */
6083 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6084 {
6085 if (IS_CHERRYVIEW(dev))
6086 chv_disable_pll(to_i915(dev), pipe);
6087 else
6088 vlv_disable_pll(to_i915(dev), pipe);
6089 }
6090
6091 static void i9xx_update_pll(struct intel_crtc *crtc,
6092 struct intel_crtc_state *crtc_state,
6093 intel_clock_t *reduced_clock,
6094 int num_connectors)
6095 {
6096 struct drm_device *dev = crtc->base.dev;
6097 struct drm_i915_private *dev_priv = dev->dev_private;
6098 u32 dpll;
6099 bool is_sdvo;
6100 struct dpll *clock = &crtc_state->dpll;
6101
6102 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6103
6104 is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6105 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6106
6107 dpll = DPLL_VGA_MODE_DIS;
6108
6109 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6110 dpll |= DPLLB_MODE_LVDS;
6111 else
6112 dpll |= DPLLB_MODE_DAC_SERIAL;
6113
6114 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6115 dpll |= (crtc_state->pixel_multiplier - 1)
6116 << SDVO_MULTIPLIER_SHIFT_HIRES;
6117 }
6118
6119 if (is_sdvo)
6120 dpll |= DPLL_SDVO_HIGH_SPEED;
6121
6122 if (crtc_state->has_dp_encoder)
6123 dpll |= DPLL_SDVO_HIGH_SPEED;
6124
6125 /* compute bitmask from p1 value */
6126 if (IS_PINEVIEW(dev))
6127 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6128 else {
6129 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6130 if (IS_G4X(dev) && reduced_clock)
6131 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6132 }
6133 switch (clock->p2) {
6134 case 5:
6135 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6136 break;
6137 case 7:
6138 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6139 break;
6140 case 10:
6141 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6142 break;
6143 case 14:
6144 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6145 break;
6146 }
6147 if (INTEL_INFO(dev)->gen >= 4)
6148 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6149
6150 if (crtc_state->sdvo_tv_clock)
6151 dpll |= PLL_REF_INPUT_TVCLKINBC;
6152 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6153 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6154 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6155 else
6156 dpll |= PLL_REF_INPUT_DREFCLK;
6157
6158 dpll |= DPLL_VCO_ENABLE;
6159 crtc_state->dpll_hw_state.dpll = dpll;
6160
6161 if (INTEL_INFO(dev)->gen >= 4) {
6162 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6163 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6164 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6165 }
6166 }
6167
6168 static void i8xx_update_pll(struct intel_crtc *crtc,
6169 struct intel_crtc_state *crtc_state,
6170 intel_clock_t *reduced_clock,
6171 int num_connectors)
6172 {
6173 struct drm_device *dev = crtc->base.dev;
6174 struct drm_i915_private *dev_priv = dev->dev_private;
6175 u32 dpll;
6176 struct dpll *clock = &crtc_state->dpll;
6177
6178 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6179
6180 dpll = DPLL_VGA_MODE_DIS;
6181
6182 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6183 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6184 } else {
6185 if (clock->p1 == 2)
6186 dpll |= PLL_P1_DIVIDE_BY_TWO;
6187 else
6188 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6189 if (clock->p2 == 4)
6190 dpll |= PLL_P2_DIVIDE_BY_4;
6191 }
6192
6193 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6194 dpll |= DPLL_DVO_2X_MODE;
6195
6196 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6197 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6198 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6199 else
6200 dpll |= PLL_REF_INPUT_DREFCLK;
6201
6202 dpll |= DPLL_VCO_ENABLE;
6203 crtc_state->dpll_hw_state.dpll = dpll;
6204 }
6205
6206 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6207 {
6208 struct drm_device *dev = intel_crtc->base.dev;
6209 struct drm_i915_private *dev_priv = dev->dev_private;
6210 enum pipe pipe = intel_crtc->pipe;
6211 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6212 struct drm_display_mode *adjusted_mode =
6213 &intel_crtc->config->base.adjusted_mode;
6214 uint32_t crtc_vtotal, crtc_vblank_end;
6215 int vsyncshift = 0;
6216
6217 /* We need to be careful not to changed the adjusted mode, for otherwise
6218 * the hw state checker will get angry at the mismatch. */
6219 crtc_vtotal = adjusted_mode->crtc_vtotal;
6220 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6221
6222 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6223 /* the chip adds 2 halflines automatically */
6224 crtc_vtotal -= 1;
6225 crtc_vblank_end -= 1;
6226
6227 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6228 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6229 else
6230 vsyncshift = adjusted_mode->crtc_hsync_start -
6231 adjusted_mode->crtc_htotal / 2;
6232 if (vsyncshift < 0)
6233 vsyncshift += adjusted_mode->crtc_htotal;
6234 }
6235
6236 if (INTEL_INFO(dev)->gen > 3)
6237 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6238
6239 I915_WRITE(HTOTAL(cpu_transcoder),
6240 (adjusted_mode->crtc_hdisplay - 1) |
6241 ((adjusted_mode->crtc_htotal - 1) << 16));
6242 I915_WRITE(HBLANK(cpu_transcoder),
6243 (adjusted_mode->crtc_hblank_start - 1) |
6244 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6245 I915_WRITE(HSYNC(cpu_transcoder),
6246 (adjusted_mode->crtc_hsync_start - 1) |
6247 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6248
6249 I915_WRITE(VTOTAL(cpu_transcoder),
6250 (adjusted_mode->crtc_vdisplay - 1) |
6251 ((crtc_vtotal - 1) << 16));
6252 I915_WRITE(VBLANK(cpu_transcoder),
6253 (adjusted_mode->crtc_vblank_start - 1) |
6254 ((crtc_vblank_end - 1) << 16));
6255 I915_WRITE(VSYNC(cpu_transcoder),
6256 (adjusted_mode->crtc_vsync_start - 1) |
6257 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6258
6259 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6260 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6261 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6262 * bits. */
6263 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6264 (pipe == PIPE_B || pipe == PIPE_C))
6265 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6266
6267 /* pipesrc controls the size that is scaled from, which should
6268 * always be the user's requested size.
6269 */
6270 I915_WRITE(PIPESRC(pipe),
6271 ((intel_crtc->config->pipe_src_w - 1) << 16) |
6272 (intel_crtc->config->pipe_src_h - 1));
6273 }
6274
6275 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6276 struct intel_crtc_state *pipe_config)
6277 {
6278 struct drm_device *dev = crtc->base.dev;
6279 struct drm_i915_private *dev_priv = dev->dev_private;
6280 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6281 uint32_t tmp;
6282
6283 tmp = I915_READ(HTOTAL(cpu_transcoder));
6284 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6285 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6286 tmp = I915_READ(HBLANK(cpu_transcoder));
6287 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6288 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6289 tmp = I915_READ(HSYNC(cpu_transcoder));
6290 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6291 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6292
6293 tmp = I915_READ(VTOTAL(cpu_transcoder));
6294 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6295 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6296 tmp = I915_READ(VBLANK(cpu_transcoder));
6297 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6298 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6299 tmp = I915_READ(VSYNC(cpu_transcoder));
6300 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6301 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6302
6303 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6304 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6305 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6306 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6307 }
6308
6309 tmp = I915_READ(PIPESRC(crtc->pipe));
6310 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6311 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6312
6313 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6314 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
6315 }
6316
6317 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6318 struct intel_crtc_state *pipe_config)
6319 {
6320 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6321 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6322 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
6323 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
6324
6325 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
6326 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
6327 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
6328 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
6329
6330 mode->flags = pipe_config->base.adjusted_mode.flags;
6331
6332 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
6333 mode->flags |= pipe_config->base.adjusted_mode.flags;
6334 }
6335
6336 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6337 {
6338 struct drm_device *dev = intel_crtc->base.dev;
6339 struct drm_i915_private *dev_priv = dev->dev_private;
6340 uint32_t pipeconf;
6341
6342 pipeconf = 0;
6343
6344 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6345 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6346 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6347
6348 if (intel_crtc->config->double_wide)
6349 pipeconf |= PIPECONF_DOUBLE_WIDE;
6350
6351 /* only g4x and later have fancy bpc/dither controls */
6352 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6353 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6354 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
6355 pipeconf |= PIPECONF_DITHER_EN |
6356 PIPECONF_DITHER_TYPE_SP;
6357
6358 switch (intel_crtc->config->pipe_bpp) {
6359 case 18:
6360 pipeconf |= PIPECONF_6BPC;
6361 break;
6362 case 24:
6363 pipeconf |= PIPECONF_8BPC;
6364 break;
6365 case 30:
6366 pipeconf |= PIPECONF_10BPC;
6367 break;
6368 default:
6369 /* Case prevented by intel_choose_pipe_bpp_dither. */
6370 BUG();
6371 }
6372 }
6373
6374 if (HAS_PIPE_CXSR(dev)) {
6375 if (intel_crtc->lowfreq_avail) {
6376 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6377 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6378 } else {
6379 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6380 }
6381 }
6382
6383 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6384 if (INTEL_INFO(dev)->gen < 4 ||
6385 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6386 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6387 else
6388 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6389 } else
6390 pipeconf |= PIPECONF_PROGRESSIVE;
6391
6392 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
6393 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6394
6395 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6396 POSTING_READ(PIPECONF(intel_crtc->pipe));
6397 }
6398
6399 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
6400 struct intel_crtc_state *crtc_state)
6401 {
6402 struct drm_device *dev = crtc->base.dev;
6403 struct drm_i915_private *dev_priv = dev->dev_private;
6404 int refclk, num_connectors = 0;
6405 intel_clock_t clock, reduced_clock;
6406 bool ok, has_reduced_clock = false;
6407 bool is_lvds = false, is_dsi = false;
6408 struct intel_encoder *encoder;
6409 const intel_limit_t *limit;
6410
6411 for_each_intel_encoder(dev, encoder) {
6412 if (encoder->new_crtc != crtc)
6413 continue;
6414
6415 switch (encoder->type) {
6416 case INTEL_OUTPUT_LVDS:
6417 is_lvds = true;
6418 break;
6419 case INTEL_OUTPUT_DSI:
6420 is_dsi = true;
6421 break;
6422 default:
6423 break;
6424 }
6425
6426 num_connectors++;
6427 }
6428
6429 if (is_dsi)
6430 return 0;
6431
6432 if (!crtc_state->clock_set) {
6433 refclk = i9xx_get_refclk(crtc, num_connectors);
6434
6435 /*
6436 * Returns a set of divisors for the desired target clock with
6437 * the given refclk, or FALSE. The returned values represent
6438 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6439 * 2) / p1 / p2.
6440 */
6441 limit = intel_limit(crtc, refclk);
6442 ok = dev_priv->display.find_dpll(limit, crtc,
6443 crtc_state->port_clock,
6444 refclk, NULL, &clock);
6445 if (!ok) {
6446 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6447 return -EINVAL;
6448 }
6449
6450 if (is_lvds && dev_priv->lvds_downclock_avail) {
6451 /*
6452 * Ensure we match the reduced clock's P to the target
6453 * clock. If the clocks don't match, we can't switch
6454 * the display clock by using the FP0/FP1. In such case
6455 * we will disable the LVDS downclock feature.
6456 */
6457 has_reduced_clock =
6458 dev_priv->display.find_dpll(limit, crtc,
6459 dev_priv->lvds_downclock,
6460 refclk, &clock,
6461 &reduced_clock);
6462 }
6463 /* Compat-code for transition, will disappear. */
6464 crtc_state->dpll.n = clock.n;
6465 crtc_state->dpll.m1 = clock.m1;
6466 crtc_state->dpll.m2 = clock.m2;
6467 crtc_state->dpll.p1 = clock.p1;
6468 crtc_state->dpll.p2 = clock.p2;
6469 }
6470
6471 if (IS_GEN2(dev)) {
6472 i8xx_update_pll(crtc, crtc_state,
6473 has_reduced_clock ? &reduced_clock : NULL,
6474 num_connectors);
6475 } else if (IS_CHERRYVIEW(dev)) {
6476 chv_update_pll(crtc, crtc_state);
6477 } else if (IS_VALLEYVIEW(dev)) {
6478 vlv_update_pll(crtc, crtc_state);
6479 } else {
6480 i9xx_update_pll(crtc, crtc_state,
6481 has_reduced_clock ? &reduced_clock : NULL,
6482 num_connectors);
6483 }
6484
6485 return 0;
6486 }
6487
6488 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6489 struct intel_crtc_state *pipe_config)
6490 {
6491 struct drm_device *dev = crtc->base.dev;
6492 struct drm_i915_private *dev_priv = dev->dev_private;
6493 uint32_t tmp;
6494
6495 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6496 return;
6497
6498 tmp = I915_READ(PFIT_CONTROL);
6499 if (!(tmp & PFIT_ENABLE))
6500 return;
6501
6502 /* Check whether the pfit is attached to our pipe. */
6503 if (INTEL_INFO(dev)->gen < 4) {
6504 if (crtc->pipe != PIPE_B)
6505 return;
6506 } else {
6507 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6508 return;
6509 }
6510
6511 pipe_config->gmch_pfit.control = tmp;
6512 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6513 if (INTEL_INFO(dev)->gen < 5)
6514 pipe_config->gmch_pfit.lvds_border_bits =
6515 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6516 }
6517
6518 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6519 struct intel_crtc_state *pipe_config)
6520 {
6521 struct drm_device *dev = crtc->base.dev;
6522 struct drm_i915_private *dev_priv = dev->dev_private;
6523 int pipe = pipe_config->cpu_transcoder;
6524 intel_clock_t clock;
6525 u32 mdiv;
6526 int refclk = 100000;
6527
6528 /* In case of MIPI DPLL will not even be used */
6529 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6530 return;
6531
6532 mutex_lock(&dev_priv->dpio_lock);
6533 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6534 mutex_unlock(&dev_priv->dpio_lock);
6535
6536 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6537 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6538 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6539 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6540 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6541
6542 vlv_clock(refclk, &clock);
6543
6544 /* clock.dot is the fast clock */
6545 pipe_config->port_clock = clock.dot / 5;
6546 }
6547
6548 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6549 struct intel_plane_config *plane_config)
6550 {
6551 struct drm_device *dev = crtc->base.dev;
6552 struct drm_i915_private *dev_priv = dev->dev_private;
6553 u32 val, base, offset;
6554 int pipe = crtc->pipe, plane = crtc->plane;
6555 int fourcc, pixel_format;
6556 int aligned_height;
6557
6558 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6559 if (!crtc->base.primary->fb) {
6560 DRM_DEBUG_KMS("failed to alloc fb\n");
6561 return;
6562 }
6563
6564 val = I915_READ(DSPCNTR(plane));
6565
6566 if (INTEL_INFO(dev)->gen >= 4)
6567 if (val & DISPPLANE_TILED)
6568 plane_config->tiling = I915_TILING_X;
6569
6570 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6571 fourcc = intel_format_to_fourcc(pixel_format);
6572 crtc->base.primary->fb->pixel_format = fourcc;
6573 crtc->base.primary->fb->bits_per_pixel =
6574 drm_format_plane_cpp(fourcc, 0) * 8;
6575
6576 if (INTEL_INFO(dev)->gen >= 4) {
6577 if (plane_config->tiling)
6578 offset = I915_READ(DSPTILEOFF(plane));
6579 else
6580 offset = I915_READ(DSPLINOFF(plane));
6581 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6582 } else {
6583 base = I915_READ(DSPADDR(plane));
6584 }
6585 plane_config->base = base;
6586
6587 val = I915_READ(PIPESRC(pipe));
6588 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6589 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6590
6591 val = I915_READ(DSPSTRIDE(pipe));
6592 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
6593
6594 aligned_height = intel_fb_align_height(dev,
6595 crtc->base.primary->fb->height,
6596 plane_config->tiling);
6597
6598 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6599 aligned_height);
6600
6601 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6602 pipe, plane, crtc->base.primary->fb->width,
6603 crtc->base.primary->fb->height,
6604 crtc->base.primary->fb->bits_per_pixel, base,
6605 crtc->base.primary->fb->pitches[0],
6606 plane_config->size);
6607
6608 }
6609
6610 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6611 struct intel_crtc_state *pipe_config)
6612 {
6613 struct drm_device *dev = crtc->base.dev;
6614 struct drm_i915_private *dev_priv = dev->dev_private;
6615 int pipe = pipe_config->cpu_transcoder;
6616 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6617 intel_clock_t clock;
6618 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6619 int refclk = 100000;
6620
6621 mutex_lock(&dev_priv->dpio_lock);
6622 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6623 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6624 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6625 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6626 mutex_unlock(&dev_priv->dpio_lock);
6627
6628 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6629 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6630 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6631 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6632 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6633
6634 chv_clock(refclk, &clock);
6635
6636 /* clock.dot is the fast clock */
6637 pipe_config->port_clock = clock.dot / 5;
6638 }
6639
6640 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6641 struct intel_crtc_state *pipe_config)
6642 {
6643 struct drm_device *dev = crtc->base.dev;
6644 struct drm_i915_private *dev_priv = dev->dev_private;
6645 uint32_t tmp;
6646
6647 if (!intel_display_power_is_enabled(dev_priv,
6648 POWER_DOMAIN_PIPE(crtc->pipe)))
6649 return false;
6650
6651 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6652 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6653
6654 tmp = I915_READ(PIPECONF(crtc->pipe));
6655 if (!(tmp & PIPECONF_ENABLE))
6656 return false;
6657
6658 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6659 switch (tmp & PIPECONF_BPC_MASK) {
6660 case PIPECONF_6BPC:
6661 pipe_config->pipe_bpp = 18;
6662 break;
6663 case PIPECONF_8BPC:
6664 pipe_config->pipe_bpp = 24;
6665 break;
6666 case PIPECONF_10BPC:
6667 pipe_config->pipe_bpp = 30;
6668 break;
6669 default:
6670 break;
6671 }
6672 }
6673
6674 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6675 pipe_config->limited_color_range = true;
6676
6677 if (INTEL_INFO(dev)->gen < 4)
6678 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6679
6680 intel_get_pipe_timings(crtc, pipe_config);
6681
6682 i9xx_get_pfit_config(crtc, pipe_config);
6683
6684 if (INTEL_INFO(dev)->gen >= 4) {
6685 tmp = I915_READ(DPLL_MD(crtc->pipe));
6686 pipe_config->pixel_multiplier =
6687 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6688 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6689 pipe_config->dpll_hw_state.dpll_md = tmp;
6690 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6691 tmp = I915_READ(DPLL(crtc->pipe));
6692 pipe_config->pixel_multiplier =
6693 ((tmp & SDVO_MULTIPLIER_MASK)
6694 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6695 } else {
6696 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6697 * port and will be fixed up in the encoder->get_config
6698 * function. */
6699 pipe_config->pixel_multiplier = 1;
6700 }
6701 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6702 if (!IS_VALLEYVIEW(dev)) {
6703 /*
6704 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6705 * on 830. Filter it out here so that we don't
6706 * report errors due to that.
6707 */
6708 if (IS_I830(dev))
6709 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6710
6711 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6712 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6713 } else {
6714 /* Mask out read-only status bits. */
6715 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6716 DPLL_PORTC_READY_MASK |
6717 DPLL_PORTB_READY_MASK);
6718 }
6719
6720 if (IS_CHERRYVIEW(dev))
6721 chv_crtc_clock_get(crtc, pipe_config);
6722 else if (IS_VALLEYVIEW(dev))
6723 vlv_crtc_clock_get(crtc, pipe_config);
6724 else
6725 i9xx_crtc_clock_get(crtc, pipe_config);
6726
6727 return true;
6728 }
6729
6730 static void ironlake_init_pch_refclk(struct drm_device *dev)
6731 {
6732 struct drm_i915_private *dev_priv = dev->dev_private;
6733 struct intel_encoder *encoder;
6734 u32 val, final;
6735 bool has_lvds = false;
6736 bool has_cpu_edp = false;
6737 bool has_panel = false;
6738 bool has_ck505 = false;
6739 bool can_ssc = false;
6740
6741 /* We need to take the global config into account */
6742 for_each_intel_encoder(dev, encoder) {
6743 switch (encoder->type) {
6744 case INTEL_OUTPUT_LVDS:
6745 has_panel = true;
6746 has_lvds = true;
6747 break;
6748 case INTEL_OUTPUT_EDP:
6749 has_panel = true;
6750 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6751 has_cpu_edp = true;
6752 break;
6753 default:
6754 break;
6755 }
6756 }
6757
6758 if (HAS_PCH_IBX(dev)) {
6759 has_ck505 = dev_priv->vbt.display_clock_mode;
6760 can_ssc = has_ck505;
6761 } else {
6762 has_ck505 = false;
6763 can_ssc = true;
6764 }
6765
6766 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6767 has_panel, has_lvds, has_ck505);
6768
6769 /* Ironlake: try to setup display ref clock before DPLL
6770 * enabling. This is only under driver's control after
6771 * PCH B stepping, previous chipset stepping should be
6772 * ignoring this setting.
6773 */
6774 val = I915_READ(PCH_DREF_CONTROL);
6775
6776 /* As we must carefully and slowly disable/enable each source in turn,
6777 * compute the final state we want first and check if we need to
6778 * make any changes at all.
6779 */
6780 final = val;
6781 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6782 if (has_ck505)
6783 final |= DREF_NONSPREAD_CK505_ENABLE;
6784 else
6785 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6786
6787 final &= ~DREF_SSC_SOURCE_MASK;
6788 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6789 final &= ~DREF_SSC1_ENABLE;
6790
6791 if (has_panel) {
6792 final |= DREF_SSC_SOURCE_ENABLE;
6793
6794 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6795 final |= DREF_SSC1_ENABLE;
6796
6797 if (has_cpu_edp) {
6798 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6799 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6800 else
6801 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6802 } else
6803 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6804 } else {
6805 final |= DREF_SSC_SOURCE_DISABLE;
6806 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6807 }
6808
6809 if (final == val)
6810 return;
6811
6812 /* Always enable nonspread source */
6813 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6814
6815 if (has_ck505)
6816 val |= DREF_NONSPREAD_CK505_ENABLE;
6817 else
6818 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6819
6820 if (has_panel) {
6821 val &= ~DREF_SSC_SOURCE_MASK;
6822 val |= DREF_SSC_SOURCE_ENABLE;
6823
6824 /* SSC must be turned on before enabling the CPU output */
6825 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6826 DRM_DEBUG_KMS("Using SSC on panel\n");
6827 val |= DREF_SSC1_ENABLE;
6828 } else
6829 val &= ~DREF_SSC1_ENABLE;
6830
6831 /* Get SSC going before enabling the outputs */
6832 I915_WRITE(PCH_DREF_CONTROL, val);
6833 POSTING_READ(PCH_DREF_CONTROL);
6834 udelay(200);
6835
6836 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6837
6838 /* Enable CPU source on CPU attached eDP */
6839 if (has_cpu_edp) {
6840 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6841 DRM_DEBUG_KMS("Using SSC on eDP\n");
6842 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6843 } else
6844 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6845 } else
6846 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6847
6848 I915_WRITE(PCH_DREF_CONTROL, val);
6849 POSTING_READ(PCH_DREF_CONTROL);
6850 udelay(200);
6851 } else {
6852 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6853
6854 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6855
6856 /* Turn off CPU output */
6857 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6858
6859 I915_WRITE(PCH_DREF_CONTROL, val);
6860 POSTING_READ(PCH_DREF_CONTROL);
6861 udelay(200);
6862
6863 /* Turn off the SSC source */
6864 val &= ~DREF_SSC_SOURCE_MASK;
6865 val |= DREF_SSC_SOURCE_DISABLE;
6866
6867 /* Turn off SSC1 */
6868 val &= ~DREF_SSC1_ENABLE;
6869
6870 I915_WRITE(PCH_DREF_CONTROL, val);
6871 POSTING_READ(PCH_DREF_CONTROL);
6872 udelay(200);
6873 }
6874
6875 BUG_ON(val != final);
6876 }
6877
6878 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6879 {
6880 uint32_t tmp;
6881
6882 tmp = I915_READ(SOUTH_CHICKEN2);
6883 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6884 I915_WRITE(SOUTH_CHICKEN2, tmp);
6885
6886 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6887 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6888 DRM_ERROR("FDI mPHY reset assert timeout\n");
6889
6890 tmp = I915_READ(SOUTH_CHICKEN2);
6891 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6892 I915_WRITE(SOUTH_CHICKEN2, tmp);
6893
6894 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6895 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6896 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6897 }
6898
6899 /* WaMPhyProgramming:hsw */
6900 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6901 {
6902 uint32_t tmp;
6903
6904 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6905 tmp &= ~(0xFF << 24);
6906 tmp |= (0x12 << 24);
6907 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6908
6909 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6910 tmp |= (1 << 11);
6911 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6912
6913 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6914 tmp |= (1 << 11);
6915 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6916
6917 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6918 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6919 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6920
6921 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6922 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6923 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6924
6925 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6926 tmp &= ~(7 << 13);
6927 tmp |= (5 << 13);
6928 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6929
6930 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6931 tmp &= ~(7 << 13);
6932 tmp |= (5 << 13);
6933 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6934
6935 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6936 tmp &= ~0xFF;
6937 tmp |= 0x1C;
6938 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6939
6940 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6941 tmp &= ~0xFF;
6942 tmp |= 0x1C;
6943 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6944
6945 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6946 tmp &= ~(0xFF << 16);
6947 tmp |= (0x1C << 16);
6948 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6949
6950 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6951 tmp &= ~(0xFF << 16);
6952 tmp |= (0x1C << 16);
6953 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6954
6955 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6956 tmp |= (1 << 27);
6957 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6958
6959 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6960 tmp |= (1 << 27);
6961 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6962
6963 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6964 tmp &= ~(0xF << 28);
6965 tmp |= (4 << 28);
6966 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6967
6968 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6969 tmp &= ~(0xF << 28);
6970 tmp |= (4 << 28);
6971 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6972 }
6973
6974 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6975 * Programming" based on the parameters passed:
6976 * - Sequence to enable CLKOUT_DP
6977 * - Sequence to enable CLKOUT_DP without spread
6978 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6979 */
6980 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6981 bool with_fdi)
6982 {
6983 struct drm_i915_private *dev_priv = dev->dev_private;
6984 uint32_t reg, tmp;
6985
6986 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6987 with_spread = true;
6988 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6989 with_fdi, "LP PCH doesn't have FDI\n"))
6990 with_fdi = false;
6991
6992 mutex_lock(&dev_priv->dpio_lock);
6993
6994 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6995 tmp &= ~SBI_SSCCTL_DISABLE;
6996 tmp |= SBI_SSCCTL_PATHALT;
6997 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6998
6999 udelay(24);
7000
7001 if (with_spread) {
7002 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7003 tmp &= ~SBI_SSCCTL_PATHALT;
7004 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7005
7006 if (with_fdi) {
7007 lpt_reset_fdi_mphy(dev_priv);
7008 lpt_program_fdi_mphy(dev_priv);
7009 }
7010 }
7011
7012 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7013 SBI_GEN0 : SBI_DBUFF0;
7014 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7015 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7016 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7017
7018 mutex_unlock(&dev_priv->dpio_lock);
7019 }
7020
7021 /* Sequence to disable CLKOUT_DP */
7022 static void lpt_disable_clkout_dp(struct drm_device *dev)
7023 {
7024 struct drm_i915_private *dev_priv = dev->dev_private;
7025 uint32_t reg, tmp;
7026
7027 mutex_lock(&dev_priv->dpio_lock);
7028
7029 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7030 SBI_GEN0 : SBI_DBUFF0;
7031 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7032 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7033 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7034
7035 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7036 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7037 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7038 tmp |= SBI_SSCCTL_PATHALT;
7039 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7040 udelay(32);
7041 }
7042 tmp |= SBI_SSCCTL_DISABLE;
7043 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7044 }
7045
7046 mutex_unlock(&dev_priv->dpio_lock);
7047 }
7048
7049 static void lpt_init_pch_refclk(struct drm_device *dev)
7050 {
7051 struct intel_encoder *encoder;
7052 bool has_vga = false;
7053
7054 for_each_intel_encoder(dev, encoder) {
7055 switch (encoder->type) {
7056 case INTEL_OUTPUT_ANALOG:
7057 has_vga = true;
7058 break;
7059 default:
7060 break;
7061 }
7062 }
7063
7064 if (has_vga)
7065 lpt_enable_clkout_dp(dev, true, true);
7066 else
7067 lpt_disable_clkout_dp(dev);
7068 }
7069
7070 /*
7071 * Initialize reference clocks when the driver loads
7072 */
7073 void intel_init_pch_refclk(struct drm_device *dev)
7074 {
7075 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7076 ironlake_init_pch_refclk(dev);
7077 else if (HAS_PCH_LPT(dev))
7078 lpt_init_pch_refclk(dev);
7079 }
7080
7081 static int ironlake_get_refclk(struct drm_crtc *crtc)
7082 {
7083 struct drm_device *dev = crtc->dev;
7084 struct drm_i915_private *dev_priv = dev->dev_private;
7085 struct intel_encoder *encoder;
7086 int num_connectors = 0;
7087 bool is_lvds = false;
7088
7089 for_each_intel_encoder(dev, encoder) {
7090 if (encoder->new_crtc != to_intel_crtc(crtc))
7091 continue;
7092
7093 switch (encoder->type) {
7094 case INTEL_OUTPUT_LVDS:
7095 is_lvds = true;
7096 break;
7097 default:
7098 break;
7099 }
7100 num_connectors++;
7101 }
7102
7103 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7104 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7105 dev_priv->vbt.lvds_ssc_freq);
7106 return dev_priv->vbt.lvds_ssc_freq;
7107 }
7108
7109 return 120000;
7110 }
7111
7112 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7113 {
7114 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7115 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7116 int pipe = intel_crtc->pipe;
7117 uint32_t val;
7118
7119 val = 0;
7120
7121 switch (intel_crtc->config->pipe_bpp) {
7122 case 18:
7123 val |= PIPECONF_6BPC;
7124 break;
7125 case 24:
7126 val |= PIPECONF_8BPC;
7127 break;
7128 case 30:
7129 val |= PIPECONF_10BPC;
7130 break;
7131 case 36:
7132 val |= PIPECONF_12BPC;
7133 break;
7134 default:
7135 /* Case prevented by intel_choose_pipe_bpp_dither. */
7136 BUG();
7137 }
7138
7139 if (intel_crtc->config->dither)
7140 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7141
7142 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7143 val |= PIPECONF_INTERLACED_ILK;
7144 else
7145 val |= PIPECONF_PROGRESSIVE;
7146
7147 if (intel_crtc->config->limited_color_range)
7148 val |= PIPECONF_COLOR_RANGE_SELECT;
7149
7150 I915_WRITE(PIPECONF(pipe), val);
7151 POSTING_READ(PIPECONF(pipe));
7152 }
7153
7154 /*
7155 * Set up the pipe CSC unit.
7156 *
7157 * Currently only full range RGB to limited range RGB conversion
7158 * is supported, but eventually this should handle various
7159 * RGB<->YCbCr scenarios as well.
7160 */
7161 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7162 {
7163 struct drm_device *dev = crtc->dev;
7164 struct drm_i915_private *dev_priv = dev->dev_private;
7165 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7166 int pipe = intel_crtc->pipe;
7167 uint16_t coeff = 0x7800; /* 1.0 */
7168
7169 /*
7170 * TODO: Check what kind of values actually come out of the pipe
7171 * with these coeff/postoff values and adjust to get the best
7172 * accuracy. Perhaps we even need to take the bpc value into
7173 * consideration.
7174 */
7175
7176 if (intel_crtc->config->limited_color_range)
7177 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7178
7179 /*
7180 * GY/GU and RY/RU should be the other way around according
7181 * to BSpec, but reality doesn't agree. Just set them up in
7182 * a way that results in the correct picture.
7183 */
7184 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7185 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7186
7187 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7188 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7189
7190 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7191 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7192
7193 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7194 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7195 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7196
7197 if (INTEL_INFO(dev)->gen > 6) {
7198 uint16_t postoff = 0;
7199
7200 if (intel_crtc->config->limited_color_range)
7201 postoff = (16 * (1 << 12) / 255) & 0x1fff;
7202
7203 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7204 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7205 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7206
7207 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7208 } else {
7209 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7210
7211 if (intel_crtc->config->limited_color_range)
7212 mode |= CSC_BLACK_SCREEN_OFFSET;
7213
7214 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7215 }
7216 }
7217
7218 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7219 {
7220 struct drm_device *dev = crtc->dev;
7221 struct drm_i915_private *dev_priv = dev->dev_private;
7222 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7223 enum pipe pipe = intel_crtc->pipe;
7224 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7225 uint32_t val;
7226
7227 val = 0;
7228
7229 if (IS_HASWELL(dev) && intel_crtc->config->dither)
7230 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7231
7232 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7233 val |= PIPECONF_INTERLACED_ILK;
7234 else
7235 val |= PIPECONF_PROGRESSIVE;
7236
7237 I915_WRITE(PIPECONF(cpu_transcoder), val);
7238 POSTING_READ(PIPECONF(cpu_transcoder));
7239
7240 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7241 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7242
7243 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7244 val = 0;
7245
7246 switch (intel_crtc->config->pipe_bpp) {
7247 case 18:
7248 val |= PIPEMISC_DITHER_6_BPC;
7249 break;
7250 case 24:
7251 val |= PIPEMISC_DITHER_8_BPC;
7252 break;
7253 case 30:
7254 val |= PIPEMISC_DITHER_10_BPC;
7255 break;
7256 case 36:
7257 val |= PIPEMISC_DITHER_12_BPC;
7258 break;
7259 default:
7260 /* Case prevented by pipe_config_set_bpp. */
7261 BUG();
7262 }
7263
7264 if (intel_crtc->config->dither)
7265 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7266
7267 I915_WRITE(PIPEMISC(pipe), val);
7268 }
7269 }
7270
7271 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7272 struct intel_crtc_state *crtc_state,
7273 intel_clock_t *clock,
7274 bool *has_reduced_clock,
7275 intel_clock_t *reduced_clock)
7276 {
7277 struct drm_device *dev = crtc->dev;
7278 struct drm_i915_private *dev_priv = dev->dev_private;
7279 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7280 int refclk;
7281 const intel_limit_t *limit;
7282 bool ret, is_lvds = false;
7283
7284 is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
7285
7286 refclk = ironlake_get_refclk(crtc);
7287
7288 /*
7289 * Returns a set of divisors for the desired target clock with the given
7290 * refclk, or FALSE. The returned values represent the clock equation:
7291 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7292 */
7293 limit = intel_limit(intel_crtc, refclk);
7294 ret = dev_priv->display.find_dpll(limit, intel_crtc,
7295 crtc_state->port_clock,
7296 refclk, NULL, clock);
7297 if (!ret)
7298 return false;
7299
7300 if (is_lvds && dev_priv->lvds_downclock_avail) {
7301 /*
7302 * Ensure we match the reduced clock's P to the target clock.
7303 * If the clocks don't match, we can't switch the display clock
7304 * by using the FP0/FP1. In such case we will disable the LVDS
7305 * downclock feature.
7306 */
7307 *has_reduced_clock =
7308 dev_priv->display.find_dpll(limit, intel_crtc,
7309 dev_priv->lvds_downclock,
7310 refclk, clock,
7311 reduced_clock);
7312 }
7313
7314 return true;
7315 }
7316
7317 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7318 {
7319 /*
7320 * Account for spread spectrum to avoid
7321 * oversubscribing the link. Max center spread
7322 * is 2.5%; use 5% for safety's sake.
7323 */
7324 u32 bps = target_clock * bpp * 21 / 20;
7325 return DIV_ROUND_UP(bps, link_bw * 8);
7326 }
7327
7328 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7329 {
7330 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7331 }
7332
7333 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7334 struct intel_crtc_state *crtc_state,
7335 u32 *fp,
7336 intel_clock_t *reduced_clock, u32 *fp2)
7337 {
7338 struct drm_crtc *crtc = &intel_crtc->base;
7339 struct drm_device *dev = crtc->dev;
7340 struct drm_i915_private *dev_priv = dev->dev_private;
7341 struct intel_encoder *intel_encoder;
7342 uint32_t dpll;
7343 int factor, num_connectors = 0;
7344 bool is_lvds = false, is_sdvo = false;
7345
7346 for_each_intel_encoder(dev, intel_encoder) {
7347 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7348 continue;
7349
7350 switch (intel_encoder->type) {
7351 case INTEL_OUTPUT_LVDS:
7352 is_lvds = true;
7353 break;
7354 case INTEL_OUTPUT_SDVO:
7355 case INTEL_OUTPUT_HDMI:
7356 is_sdvo = true;
7357 break;
7358 default:
7359 break;
7360 }
7361
7362 num_connectors++;
7363 }
7364
7365 /* Enable autotuning of the PLL clock (if permissible) */
7366 factor = 21;
7367 if (is_lvds) {
7368 if ((intel_panel_use_ssc(dev_priv) &&
7369 dev_priv->vbt.lvds_ssc_freq == 100000) ||
7370 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7371 factor = 25;
7372 } else if (crtc_state->sdvo_tv_clock)
7373 factor = 20;
7374
7375 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7376 *fp |= FP_CB_TUNE;
7377
7378 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7379 *fp2 |= FP_CB_TUNE;
7380
7381 dpll = 0;
7382
7383 if (is_lvds)
7384 dpll |= DPLLB_MODE_LVDS;
7385 else
7386 dpll |= DPLLB_MODE_DAC_SERIAL;
7387
7388 dpll |= (crtc_state->pixel_multiplier - 1)
7389 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7390
7391 if (is_sdvo)
7392 dpll |= DPLL_SDVO_HIGH_SPEED;
7393 if (crtc_state->has_dp_encoder)
7394 dpll |= DPLL_SDVO_HIGH_SPEED;
7395
7396 /* compute bitmask from p1 value */
7397 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7398 /* also FPA1 */
7399 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7400
7401 switch (crtc_state->dpll.p2) {
7402 case 5:
7403 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7404 break;
7405 case 7:
7406 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7407 break;
7408 case 10:
7409 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7410 break;
7411 case 14:
7412 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7413 break;
7414 }
7415
7416 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7417 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7418 else
7419 dpll |= PLL_REF_INPUT_DREFCLK;
7420
7421 return dpll | DPLL_VCO_ENABLE;
7422 }
7423
7424 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
7425 struct intel_crtc_state *crtc_state)
7426 {
7427 struct drm_device *dev = crtc->base.dev;
7428 intel_clock_t clock, reduced_clock;
7429 u32 dpll = 0, fp = 0, fp2 = 0;
7430 bool ok, has_reduced_clock = false;
7431 bool is_lvds = false;
7432 struct intel_shared_dpll *pll;
7433
7434 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7435
7436 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7437 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7438
7439 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
7440 &has_reduced_clock, &reduced_clock);
7441 if (!ok && !crtc_state->clock_set) {
7442 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7443 return -EINVAL;
7444 }
7445 /* Compat-code for transition, will disappear. */
7446 if (!crtc_state->clock_set) {
7447 crtc_state->dpll.n = clock.n;
7448 crtc_state->dpll.m1 = clock.m1;
7449 crtc_state->dpll.m2 = clock.m2;
7450 crtc_state->dpll.p1 = clock.p1;
7451 crtc_state->dpll.p2 = clock.p2;
7452 }
7453
7454 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7455 if (crtc_state->has_pch_encoder) {
7456 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7457 if (has_reduced_clock)
7458 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7459
7460 dpll = ironlake_compute_dpll(crtc, crtc_state,
7461 &fp, &reduced_clock,
7462 has_reduced_clock ? &fp2 : NULL);
7463
7464 crtc_state->dpll_hw_state.dpll = dpll;
7465 crtc_state->dpll_hw_state.fp0 = fp;
7466 if (has_reduced_clock)
7467 crtc_state->dpll_hw_state.fp1 = fp2;
7468 else
7469 crtc_state->dpll_hw_state.fp1 = fp;
7470
7471 pll = intel_get_shared_dpll(crtc, crtc_state);
7472 if (pll == NULL) {
7473 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7474 pipe_name(crtc->pipe));
7475 return -EINVAL;
7476 }
7477 }
7478
7479 if (is_lvds && has_reduced_clock && i915.powersave)
7480 crtc->lowfreq_avail = true;
7481 else
7482 crtc->lowfreq_avail = false;
7483
7484 return 0;
7485 }
7486
7487 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7488 struct intel_link_m_n *m_n)
7489 {
7490 struct drm_device *dev = crtc->base.dev;
7491 struct drm_i915_private *dev_priv = dev->dev_private;
7492 enum pipe pipe = crtc->pipe;
7493
7494 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7495 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7496 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7497 & ~TU_SIZE_MASK;
7498 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7499 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7500 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7501 }
7502
7503 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7504 enum transcoder transcoder,
7505 struct intel_link_m_n *m_n,
7506 struct intel_link_m_n *m2_n2)
7507 {
7508 struct drm_device *dev = crtc->base.dev;
7509 struct drm_i915_private *dev_priv = dev->dev_private;
7510 enum pipe pipe = crtc->pipe;
7511
7512 if (INTEL_INFO(dev)->gen >= 5) {
7513 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7514 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7515 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7516 & ~TU_SIZE_MASK;
7517 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7518 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7519 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7520 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7521 * gen < 8) and if DRRS is supported (to make sure the
7522 * registers are not unnecessarily read).
7523 */
7524 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7525 crtc->config->has_drrs) {
7526 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7527 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7528 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7529 & ~TU_SIZE_MASK;
7530 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7531 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7532 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7533 }
7534 } else {
7535 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7536 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7537 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7538 & ~TU_SIZE_MASK;
7539 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7540 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7541 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7542 }
7543 }
7544
7545 void intel_dp_get_m_n(struct intel_crtc *crtc,
7546 struct intel_crtc_state *pipe_config)
7547 {
7548 if (pipe_config->has_pch_encoder)
7549 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7550 else
7551 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7552 &pipe_config->dp_m_n,
7553 &pipe_config->dp_m2_n2);
7554 }
7555
7556 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7557 struct intel_crtc_state *pipe_config)
7558 {
7559 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7560 &pipe_config->fdi_m_n, NULL);
7561 }
7562
7563 static void skylake_get_pfit_config(struct intel_crtc *crtc,
7564 struct intel_crtc_state *pipe_config)
7565 {
7566 struct drm_device *dev = crtc->base.dev;
7567 struct drm_i915_private *dev_priv = dev->dev_private;
7568 uint32_t tmp;
7569
7570 tmp = I915_READ(PS_CTL(crtc->pipe));
7571
7572 if (tmp & PS_ENABLE) {
7573 pipe_config->pch_pfit.enabled = true;
7574 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
7575 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
7576 }
7577 }
7578
7579 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7580 struct intel_crtc_state *pipe_config)
7581 {
7582 struct drm_device *dev = crtc->base.dev;
7583 struct drm_i915_private *dev_priv = dev->dev_private;
7584 uint32_t tmp;
7585
7586 tmp = I915_READ(PF_CTL(crtc->pipe));
7587
7588 if (tmp & PF_ENABLE) {
7589 pipe_config->pch_pfit.enabled = true;
7590 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7591 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7592
7593 /* We currently do not free assignements of panel fitters on
7594 * ivb/hsw (since we don't use the higher upscaling modes which
7595 * differentiates them) so just WARN about this case for now. */
7596 if (IS_GEN7(dev)) {
7597 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7598 PF_PIPE_SEL_IVB(crtc->pipe));
7599 }
7600 }
7601 }
7602
7603 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7604 struct intel_plane_config *plane_config)
7605 {
7606 struct drm_device *dev = crtc->base.dev;
7607 struct drm_i915_private *dev_priv = dev->dev_private;
7608 u32 val, base, offset;
7609 int pipe = crtc->pipe, plane = crtc->plane;
7610 int fourcc, pixel_format;
7611 int aligned_height;
7612
7613 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7614 if (!crtc->base.primary->fb) {
7615 DRM_DEBUG_KMS("failed to alloc fb\n");
7616 return;
7617 }
7618
7619 val = I915_READ(DSPCNTR(plane));
7620
7621 if (INTEL_INFO(dev)->gen >= 4)
7622 if (val & DISPPLANE_TILED)
7623 plane_config->tiling = I915_TILING_X;
7624
7625 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7626 fourcc = intel_format_to_fourcc(pixel_format);
7627 crtc->base.primary->fb->pixel_format = fourcc;
7628 crtc->base.primary->fb->bits_per_pixel =
7629 drm_format_plane_cpp(fourcc, 0) * 8;
7630
7631 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7632 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7633 offset = I915_READ(DSPOFFSET(plane));
7634 } else {
7635 if (plane_config->tiling)
7636 offset = I915_READ(DSPTILEOFF(plane));
7637 else
7638 offset = I915_READ(DSPLINOFF(plane));
7639 }
7640 plane_config->base = base;
7641
7642 val = I915_READ(PIPESRC(pipe));
7643 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7644 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7645
7646 val = I915_READ(DSPSTRIDE(pipe));
7647 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
7648
7649 aligned_height = intel_fb_align_height(dev,
7650 crtc->base.primary->fb->height,
7651 plane_config->tiling);
7652
7653 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7654 aligned_height);
7655
7656 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7657 pipe, plane, crtc->base.primary->fb->width,
7658 crtc->base.primary->fb->height,
7659 crtc->base.primary->fb->bits_per_pixel, base,
7660 crtc->base.primary->fb->pitches[0],
7661 plane_config->size);
7662 }
7663
7664 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7665 struct intel_crtc_state *pipe_config)
7666 {
7667 struct drm_device *dev = crtc->base.dev;
7668 struct drm_i915_private *dev_priv = dev->dev_private;
7669 uint32_t tmp;
7670
7671 if (!intel_display_power_is_enabled(dev_priv,
7672 POWER_DOMAIN_PIPE(crtc->pipe)))
7673 return false;
7674
7675 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7676 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7677
7678 tmp = I915_READ(PIPECONF(crtc->pipe));
7679 if (!(tmp & PIPECONF_ENABLE))
7680 return false;
7681
7682 switch (tmp & PIPECONF_BPC_MASK) {
7683 case PIPECONF_6BPC:
7684 pipe_config->pipe_bpp = 18;
7685 break;
7686 case PIPECONF_8BPC:
7687 pipe_config->pipe_bpp = 24;
7688 break;
7689 case PIPECONF_10BPC:
7690 pipe_config->pipe_bpp = 30;
7691 break;
7692 case PIPECONF_12BPC:
7693 pipe_config->pipe_bpp = 36;
7694 break;
7695 default:
7696 break;
7697 }
7698
7699 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7700 pipe_config->limited_color_range = true;
7701
7702 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7703 struct intel_shared_dpll *pll;
7704
7705 pipe_config->has_pch_encoder = true;
7706
7707 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7708 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7709 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7710
7711 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7712
7713 if (HAS_PCH_IBX(dev_priv->dev)) {
7714 pipe_config->shared_dpll =
7715 (enum intel_dpll_id) crtc->pipe;
7716 } else {
7717 tmp = I915_READ(PCH_DPLL_SEL);
7718 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7719 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7720 else
7721 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7722 }
7723
7724 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7725
7726 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7727 &pipe_config->dpll_hw_state));
7728
7729 tmp = pipe_config->dpll_hw_state.dpll;
7730 pipe_config->pixel_multiplier =
7731 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7732 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7733
7734 ironlake_pch_clock_get(crtc, pipe_config);
7735 } else {
7736 pipe_config->pixel_multiplier = 1;
7737 }
7738
7739 intel_get_pipe_timings(crtc, pipe_config);
7740
7741 ironlake_get_pfit_config(crtc, pipe_config);
7742
7743 return true;
7744 }
7745
7746 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7747 {
7748 struct drm_device *dev = dev_priv->dev;
7749 struct intel_crtc *crtc;
7750
7751 for_each_intel_crtc(dev, crtc)
7752 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
7753 pipe_name(crtc->pipe));
7754
7755 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7756 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7757 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7758 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7759 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7760 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7761 "CPU PWM1 enabled\n");
7762 if (IS_HASWELL(dev))
7763 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7764 "CPU PWM2 enabled\n");
7765 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7766 "PCH PWM1 enabled\n");
7767 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7768 "Utility pin enabled\n");
7769 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7770
7771 /*
7772 * In theory we can still leave IRQs enabled, as long as only the HPD
7773 * interrupts remain enabled. We used to check for that, but since it's
7774 * gen-specific and since we only disable LCPLL after we fully disable
7775 * the interrupts, the check below should be enough.
7776 */
7777 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7778 }
7779
7780 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7781 {
7782 struct drm_device *dev = dev_priv->dev;
7783
7784 if (IS_HASWELL(dev))
7785 return I915_READ(D_COMP_HSW);
7786 else
7787 return I915_READ(D_COMP_BDW);
7788 }
7789
7790 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7791 {
7792 struct drm_device *dev = dev_priv->dev;
7793
7794 if (IS_HASWELL(dev)) {
7795 mutex_lock(&dev_priv->rps.hw_lock);
7796 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7797 val))
7798 DRM_ERROR("Failed to write to D_COMP\n");
7799 mutex_unlock(&dev_priv->rps.hw_lock);
7800 } else {
7801 I915_WRITE(D_COMP_BDW, val);
7802 POSTING_READ(D_COMP_BDW);
7803 }
7804 }
7805
7806 /*
7807 * This function implements pieces of two sequences from BSpec:
7808 * - Sequence for display software to disable LCPLL
7809 * - Sequence for display software to allow package C8+
7810 * The steps implemented here are just the steps that actually touch the LCPLL
7811 * register. Callers should take care of disabling all the display engine
7812 * functions, doing the mode unset, fixing interrupts, etc.
7813 */
7814 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7815 bool switch_to_fclk, bool allow_power_down)
7816 {
7817 uint32_t val;
7818
7819 assert_can_disable_lcpll(dev_priv);
7820
7821 val = I915_READ(LCPLL_CTL);
7822
7823 if (switch_to_fclk) {
7824 val |= LCPLL_CD_SOURCE_FCLK;
7825 I915_WRITE(LCPLL_CTL, val);
7826
7827 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7828 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7829 DRM_ERROR("Switching to FCLK failed\n");
7830
7831 val = I915_READ(LCPLL_CTL);
7832 }
7833
7834 val |= LCPLL_PLL_DISABLE;
7835 I915_WRITE(LCPLL_CTL, val);
7836 POSTING_READ(LCPLL_CTL);
7837
7838 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7839 DRM_ERROR("LCPLL still locked\n");
7840
7841 val = hsw_read_dcomp(dev_priv);
7842 val |= D_COMP_COMP_DISABLE;
7843 hsw_write_dcomp(dev_priv, val);
7844 ndelay(100);
7845
7846 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7847 1))
7848 DRM_ERROR("D_COMP RCOMP still in progress\n");
7849
7850 if (allow_power_down) {
7851 val = I915_READ(LCPLL_CTL);
7852 val |= LCPLL_POWER_DOWN_ALLOW;
7853 I915_WRITE(LCPLL_CTL, val);
7854 POSTING_READ(LCPLL_CTL);
7855 }
7856 }
7857
7858 /*
7859 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7860 * source.
7861 */
7862 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7863 {
7864 uint32_t val;
7865
7866 val = I915_READ(LCPLL_CTL);
7867
7868 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7869 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7870 return;
7871
7872 /*
7873 * Make sure we're not on PC8 state before disabling PC8, otherwise
7874 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7875 */
7876 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
7877
7878 if (val & LCPLL_POWER_DOWN_ALLOW) {
7879 val &= ~LCPLL_POWER_DOWN_ALLOW;
7880 I915_WRITE(LCPLL_CTL, val);
7881 POSTING_READ(LCPLL_CTL);
7882 }
7883
7884 val = hsw_read_dcomp(dev_priv);
7885 val |= D_COMP_COMP_FORCE;
7886 val &= ~D_COMP_COMP_DISABLE;
7887 hsw_write_dcomp(dev_priv, val);
7888
7889 val = I915_READ(LCPLL_CTL);
7890 val &= ~LCPLL_PLL_DISABLE;
7891 I915_WRITE(LCPLL_CTL, val);
7892
7893 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7894 DRM_ERROR("LCPLL not locked yet\n");
7895
7896 if (val & LCPLL_CD_SOURCE_FCLK) {
7897 val = I915_READ(LCPLL_CTL);
7898 val &= ~LCPLL_CD_SOURCE_FCLK;
7899 I915_WRITE(LCPLL_CTL, val);
7900
7901 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7902 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7903 DRM_ERROR("Switching back to LCPLL failed\n");
7904 }
7905
7906 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
7907 }
7908
7909 /*
7910 * Package states C8 and deeper are really deep PC states that can only be
7911 * reached when all the devices on the system allow it, so even if the graphics
7912 * device allows PC8+, it doesn't mean the system will actually get to these
7913 * states. Our driver only allows PC8+ when going into runtime PM.
7914 *
7915 * The requirements for PC8+ are that all the outputs are disabled, the power
7916 * well is disabled and most interrupts are disabled, and these are also
7917 * requirements for runtime PM. When these conditions are met, we manually do
7918 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7919 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7920 * hang the machine.
7921 *
7922 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7923 * the state of some registers, so when we come back from PC8+ we need to
7924 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7925 * need to take care of the registers kept by RC6. Notice that this happens even
7926 * if we don't put the device in PCI D3 state (which is what currently happens
7927 * because of the runtime PM support).
7928 *
7929 * For more, read "Display Sequences for Package C8" on the hardware
7930 * documentation.
7931 */
7932 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7933 {
7934 struct drm_device *dev = dev_priv->dev;
7935 uint32_t val;
7936
7937 DRM_DEBUG_KMS("Enabling package C8+\n");
7938
7939 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7940 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7941 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7942 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7943 }
7944
7945 lpt_disable_clkout_dp(dev);
7946 hsw_disable_lcpll(dev_priv, true, true);
7947 }
7948
7949 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7950 {
7951 struct drm_device *dev = dev_priv->dev;
7952 uint32_t val;
7953
7954 DRM_DEBUG_KMS("Disabling package C8+\n");
7955
7956 hsw_restore_lcpll(dev_priv);
7957 lpt_init_pch_refclk(dev);
7958
7959 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7960 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7961 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7962 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7963 }
7964
7965 intel_prepare_ddi(dev);
7966 }
7967
7968 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
7969 struct intel_crtc_state *crtc_state)
7970 {
7971 if (!intel_ddi_pll_select(crtc, crtc_state))
7972 return -EINVAL;
7973
7974 crtc->lowfreq_avail = false;
7975
7976 return 0;
7977 }
7978
7979 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
7980 enum port port,
7981 struct intel_crtc_state *pipe_config)
7982 {
7983 u32 temp, dpll_ctl1;
7984
7985 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
7986 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
7987
7988 switch (pipe_config->ddi_pll_sel) {
7989 case SKL_DPLL0:
7990 /*
7991 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
7992 * of the shared DPLL framework and thus needs to be read out
7993 * separately
7994 */
7995 dpll_ctl1 = I915_READ(DPLL_CTRL1);
7996 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
7997 break;
7998 case SKL_DPLL1:
7999 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
8000 break;
8001 case SKL_DPLL2:
8002 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
8003 break;
8004 case SKL_DPLL3:
8005 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8006 break;
8007 }
8008 }
8009
8010 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8011 enum port port,
8012 struct intel_crtc_state *pipe_config)
8013 {
8014 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8015
8016 switch (pipe_config->ddi_pll_sel) {
8017 case PORT_CLK_SEL_WRPLL1:
8018 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8019 break;
8020 case PORT_CLK_SEL_WRPLL2:
8021 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8022 break;
8023 }
8024 }
8025
8026 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
8027 struct intel_crtc_state *pipe_config)
8028 {
8029 struct drm_device *dev = crtc->base.dev;
8030 struct drm_i915_private *dev_priv = dev->dev_private;
8031 struct intel_shared_dpll *pll;
8032 enum port port;
8033 uint32_t tmp;
8034
8035 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8036
8037 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8038
8039 if (IS_SKYLAKE(dev))
8040 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8041 else
8042 haswell_get_ddi_pll(dev_priv, port, pipe_config);
8043
8044 if (pipe_config->shared_dpll >= 0) {
8045 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8046
8047 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8048 &pipe_config->dpll_hw_state));
8049 }
8050
8051 /*
8052 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8053 * DDI E. So just check whether this pipe is wired to DDI E and whether
8054 * the PCH transcoder is on.
8055 */
8056 if (INTEL_INFO(dev)->gen < 9 &&
8057 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8058 pipe_config->has_pch_encoder = true;
8059
8060 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8061 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8062 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8063
8064 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8065 }
8066 }
8067
8068 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8069 struct intel_crtc_state *pipe_config)
8070 {
8071 struct drm_device *dev = crtc->base.dev;
8072 struct drm_i915_private *dev_priv = dev->dev_private;
8073 enum intel_display_power_domain pfit_domain;
8074 uint32_t tmp;
8075
8076 if (!intel_display_power_is_enabled(dev_priv,
8077 POWER_DOMAIN_PIPE(crtc->pipe)))
8078 return false;
8079
8080 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8081 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8082
8083 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8084 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8085 enum pipe trans_edp_pipe;
8086 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8087 default:
8088 WARN(1, "unknown pipe linked to edp transcoder\n");
8089 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8090 case TRANS_DDI_EDP_INPUT_A_ON:
8091 trans_edp_pipe = PIPE_A;
8092 break;
8093 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8094 trans_edp_pipe = PIPE_B;
8095 break;
8096 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8097 trans_edp_pipe = PIPE_C;
8098 break;
8099 }
8100
8101 if (trans_edp_pipe == crtc->pipe)
8102 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8103 }
8104
8105 if (!intel_display_power_is_enabled(dev_priv,
8106 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8107 return false;
8108
8109 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8110 if (!(tmp & PIPECONF_ENABLE))
8111 return false;
8112
8113 haswell_get_ddi_port_state(crtc, pipe_config);
8114
8115 intel_get_pipe_timings(crtc, pipe_config);
8116
8117 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8118 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8119 if (IS_SKYLAKE(dev))
8120 skylake_get_pfit_config(crtc, pipe_config);
8121 else
8122 ironlake_get_pfit_config(crtc, pipe_config);
8123 }
8124
8125 if (IS_HASWELL(dev))
8126 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8127 (I915_READ(IPS_CTL) & IPS_ENABLE);
8128
8129 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8130 pipe_config->pixel_multiplier =
8131 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8132 } else {
8133 pipe_config->pixel_multiplier = 1;
8134 }
8135
8136 return true;
8137 }
8138
8139 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8140 {
8141 struct drm_device *dev = crtc->dev;
8142 struct drm_i915_private *dev_priv = dev->dev_private;
8143 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8144 uint32_t cntl = 0, size = 0;
8145
8146 if (base) {
8147 unsigned int width = intel_crtc->cursor_width;
8148 unsigned int height = intel_crtc->cursor_height;
8149 unsigned int stride = roundup_pow_of_two(width) * 4;
8150
8151 switch (stride) {
8152 default:
8153 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8154 width, stride);
8155 stride = 256;
8156 /* fallthrough */
8157 case 256:
8158 case 512:
8159 case 1024:
8160 case 2048:
8161 break;
8162 }
8163
8164 cntl |= CURSOR_ENABLE |
8165 CURSOR_GAMMA_ENABLE |
8166 CURSOR_FORMAT_ARGB |
8167 CURSOR_STRIDE(stride);
8168
8169 size = (height << 12) | width;
8170 }
8171
8172 if (intel_crtc->cursor_cntl != 0 &&
8173 (intel_crtc->cursor_base != base ||
8174 intel_crtc->cursor_size != size ||
8175 intel_crtc->cursor_cntl != cntl)) {
8176 /* On these chipsets we can only modify the base/size/stride
8177 * whilst the cursor is disabled.
8178 */
8179 I915_WRITE(_CURACNTR, 0);
8180 POSTING_READ(_CURACNTR);
8181 intel_crtc->cursor_cntl = 0;
8182 }
8183
8184 if (intel_crtc->cursor_base != base) {
8185 I915_WRITE(_CURABASE, base);
8186 intel_crtc->cursor_base = base;
8187 }
8188
8189 if (intel_crtc->cursor_size != size) {
8190 I915_WRITE(CURSIZE, size);
8191 intel_crtc->cursor_size = size;
8192 }
8193
8194 if (intel_crtc->cursor_cntl != cntl) {
8195 I915_WRITE(_CURACNTR, cntl);
8196 POSTING_READ(_CURACNTR);
8197 intel_crtc->cursor_cntl = cntl;
8198 }
8199 }
8200
8201 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8202 {
8203 struct drm_device *dev = crtc->dev;
8204 struct drm_i915_private *dev_priv = dev->dev_private;
8205 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8206 int pipe = intel_crtc->pipe;
8207 uint32_t cntl;
8208
8209 cntl = 0;
8210 if (base) {
8211 cntl = MCURSOR_GAMMA_ENABLE;
8212 switch (intel_crtc->cursor_width) {
8213 case 64:
8214 cntl |= CURSOR_MODE_64_ARGB_AX;
8215 break;
8216 case 128:
8217 cntl |= CURSOR_MODE_128_ARGB_AX;
8218 break;
8219 case 256:
8220 cntl |= CURSOR_MODE_256_ARGB_AX;
8221 break;
8222 default:
8223 MISSING_CASE(intel_crtc->cursor_width);
8224 return;
8225 }
8226 cntl |= pipe << 28; /* Connect to correct pipe */
8227
8228 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8229 cntl |= CURSOR_PIPE_CSC_ENABLE;
8230 }
8231
8232 if (to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180))
8233 cntl |= CURSOR_ROTATE_180;
8234
8235 if (intel_crtc->cursor_cntl != cntl) {
8236 I915_WRITE(CURCNTR(pipe), cntl);
8237 POSTING_READ(CURCNTR(pipe));
8238 intel_crtc->cursor_cntl = cntl;
8239 }
8240
8241 /* and commit changes on next vblank */
8242 I915_WRITE(CURBASE(pipe), base);
8243 POSTING_READ(CURBASE(pipe));
8244
8245 intel_crtc->cursor_base = base;
8246 }
8247
8248 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8249 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8250 bool on)
8251 {
8252 struct drm_device *dev = crtc->dev;
8253 struct drm_i915_private *dev_priv = dev->dev_private;
8254 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8255 int pipe = intel_crtc->pipe;
8256 int x = crtc->cursor_x;
8257 int y = crtc->cursor_y;
8258 u32 base = 0, pos = 0;
8259
8260 if (on)
8261 base = intel_crtc->cursor_addr;
8262
8263 if (x >= intel_crtc->config->pipe_src_w)
8264 base = 0;
8265
8266 if (y >= intel_crtc->config->pipe_src_h)
8267 base = 0;
8268
8269 if (x < 0) {
8270 if (x + intel_crtc->cursor_width <= 0)
8271 base = 0;
8272
8273 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8274 x = -x;
8275 }
8276 pos |= x << CURSOR_X_SHIFT;
8277
8278 if (y < 0) {
8279 if (y + intel_crtc->cursor_height <= 0)
8280 base = 0;
8281
8282 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8283 y = -y;
8284 }
8285 pos |= y << CURSOR_Y_SHIFT;
8286
8287 if (base == 0 && intel_crtc->cursor_base == 0)
8288 return;
8289
8290 I915_WRITE(CURPOS(pipe), pos);
8291
8292 /* ILK+ do this automagically */
8293 if (HAS_GMCH_DISPLAY(dev) &&
8294 to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180)) {
8295 base += (intel_crtc->cursor_height *
8296 intel_crtc->cursor_width - 1) * 4;
8297 }
8298
8299 if (IS_845G(dev) || IS_I865G(dev))
8300 i845_update_cursor(crtc, base);
8301 else
8302 i9xx_update_cursor(crtc, base);
8303 }
8304
8305 static bool cursor_size_ok(struct drm_device *dev,
8306 uint32_t width, uint32_t height)
8307 {
8308 if (width == 0 || height == 0)
8309 return false;
8310
8311 /*
8312 * 845g/865g are special in that they are only limited by
8313 * the width of their cursors, the height is arbitrary up to
8314 * the precision of the register. Everything else requires
8315 * square cursors, limited to a few power-of-two sizes.
8316 */
8317 if (IS_845G(dev) || IS_I865G(dev)) {
8318 if ((width & 63) != 0)
8319 return false;
8320
8321 if (width > (IS_845G(dev) ? 64 : 512))
8322 return false;
8323
8324 if (height > 1023)
8325 return false;
8326 } else {
8327 switch (width | height) {
8328 case 256:
8329 case 128:
8330 if (IS_GEN2(dev))
8331 return false;
8332 case 64:
8333 break;
8334 default:
8335 return false;
8336 }
8337 }
8338
8339 return true;
8340 }
8341
8342 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8343 u16 *blue, uint32_t start, uint32_t size)
8344 {
8345 int end = (start + size > 256) ? 256 : start + size, i;
8346 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8347
8348 for (i = start; i < end; i++) {
8349 intel_crtc->lut_r[i] = red[i] >> 8;
8350 intel_crtc->lut_g[i] = green[i] >> 8;
8351 intel_crtc->lut_b[i] = blue[i] >> 8;
8352 }
8353
8354 intel_crtc_load_lut(crtc);
8355 }
8356
8357 /* VESA 640x480x72Hz mode to set on the pipe */
8358 static struct drm_display_mode load_detect_mode = {
8359 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8360 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8361 };
8362
8363 struct drm_framebuffer *
8364 __intel_framebuffer_create(struct drm_device *dev,
8365 struct drm_mode_fb_cmd2 *mode_cmd,
8366 struct drm_i915_gem_object *obj)
8367 {
8368 struct intel_framebuffer *intel_fb;
8369 int ret;
8370
8371 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8372 if (!intel_fb) {
8373 drm_gem_object_unreference(&obj->base);
8374 return ERR_PTR(-ENOMEM);
8375 }
8376
8377 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8378 if (ret)
8379 goto err;
8380
8381 return &intel_fb->base;
8382 err:
8383 drm_gem_object_unreference(&obj->base);
8384 kfree(intel_fb);
8385
8386 return ERR_PTR(ret);
8387 }
8388
8389 static struct drm_framebuffer *
8390 intel_framebuffer_create(struct drm_device *dev,
8391 struct drm_mode_fb_cmd2 *mode_cmd,
8392 struct drm_i915_gem_object *obj)
8393 {
8394 struct drm_framebuffer *fb;
8395 int ret;
8396
8397 ret = i915_mutex_lock_interruptible(dev);
8398 if (ret)
8399 return ERR_PTR(ret);
8400 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8401 mutex_unlock(&dev->struct_mutex);
8402
8403 return fb;
8404 }
8405
8406 static u32
8407 intel_framebuffer_pitch_for_width(int width, int bpp)
8408 {
8409 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8410 return ALIGN(pitch, 64);
8411 }
8412
8413 static u32
8414 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8415 {
8416 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8417 return PAGE_ALIGN(pitch * mode->vdisplay);
8418 }
8419
8420 static struct drm_framebuffer *
8421 intel_framebuffer_create_for_mode(struct drm_device *dev,
8422 struct drm_display_mode *mode,
8423 int depth, int bpp)
8424 {
8425 struct drm_i915_gem_object *obj;
8426 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8427
8428 obj = i915_gem_alloc_object(dev,
8429 intel_framebuffer_size_for_mode(mode, bpp));
8430 if (obj == NULL)
8431 return ERR_PTR(-ENOMEM);
8432
8433 mode_cmd.width = mode->hdisplay;
8434 mode_cmd.height = mode->vdisplay;
8435 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8436 bpp);
8437 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8438
8439 return intel_framebuffer_create(dev, &mode_cmd, obj);
8440 }
8441
8442 static struct drm_framebuffer *
8443 mode_fits_in_fbdev(struct drm_device *dev,
8444 struct drm_display_mode *mode)
8445 {
8446 #ifdef CONFIG_DRM_I915_FBDEV
8447 struct drm_i915_private *dev_priv = dev->dev_private;
8448 struct drm_i915_gem_object *obj;
8449 struct drm_framebuffer *fb;
8450
8451 if (!dev_priv->fbdev)
8452 return NULL;
8453
8454 if (!dev_priv->fbdev->fb)
8455 return NULL;
8456
8457 obj = dev_priv->fbdev->fb->obj;
8458 BUG_ON(!obj);
8459
8460 fb = &dev_priv->fbdev->fb->base;
8461 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8462 fb->bits_per_pixel))
8463 return NULL;
8464
8465 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8466 return NULL;
8467
8468 return fb;
8469 #else
8470 return NULL;
8471 #endif
8472 }
8473
8474 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8475 struct drm_display_mode *mode,
8476 struct intel_load_detect_pipe *old,
8477 struct drm_modeset_acquire_ctx *ctx)
8478 {
8479 struct intel_crtc *intel_crtc;
8480 struct intel_encoder *intel_encoder =
8481 intel_attached_encoder(connector);
8482 struct drm_crtc *possible_crtc;
8483 struct drm_encoder *encoder = &intel_encoder->base;
8484 struct drm_crtc *crtc = NULL;
8485 struct drm_device *dev = encoder->dev;
8486 struct drm_framebuffer *fb;
8487 struct drm_mode_config *config = &dev->mode_config;
8488 int ret, i = -1;
8489
8490 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8491 connector->base.id, connector->name,
8492 encoder->base.id, encoder->name);
8493
8494 retry:
8495 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8496 if (ret)
8497 goto fail_unlock;
8498
8499 /*
8500 * Algorithm gets a little messy:
8501 *
8502 * - if the connector already has an assigned crtc, use it (but make
8503 * sure it's on first)
8504 *
8505 * - try to find the first unused crtc that can drive this connector,
8506 * and use that if we find one
8507 */
8508
8509 /* See if we already have a CRTC for this connector */
8510 if (encoder->crtc) {
8511 crtc = encoder->crtc;
8512
8513 ret = drm_modeset_lock(&crtc->mutex, ctx);
8514 if (ret)
8515 goto fail_unlock;
8516 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8517 if (ret)
8518 goto fail_unlock;
8519
8520 old->dpms_mode = connector->dpms;
8521 old->load_detect_temp = false;
8522
8523 /* Make sure the crtc and connector are running */
8524 if (connector->dpms != DRM_MODE_DPMS_ON)
8525 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8526
8527 return true;
8528 }
8529
8530 /* Find an unused one (if possible) */
8531 for_each_crtc(dev, possible_crtc) {
8532 i++;
8533 if (!(encoder->possible_crtcs & (1 << i)))
8534 continue;
8535 if (possible_crtc->enabled)
8536 continue;
8537 /* This can occur when applying the pipe A quirk on resume. */
8538 if (to_intel_crtc(possible_crtc)->new_enabled)
8539 continue;
8540
8541 crtc = possible_crtc;
8542 break;
8543 }
8544
8545 /*
8546 * If we didn't find an unused CRTC, don't use any.
8547 */
8548 if (!crtc) {
8549 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8550 goto fail_unlock;
8551 }
8552
8553 ret = drm_modeset_lock(&crtc->mutex, ctx);
8554 if (ret)
8555 goto fail_unlock;
8556 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8557 if (ret)
8558 goto fail_unlock;
8559 intel_encoder->new_crtc = to_intel_crtc(crtc);
8560 to_intel_connector(connector)->new_encoder = intel_encoder;
8561
8562 intel_crtc = to_intel_crtc(crtc);
8563 intel_crtc->new_enabled = true;
8564 intel_crtc->new_config = intel_crtc->config;
8565 old->dpms_mode = connector->dpms;
8566 old->load_detect_temp = true;
8567 old->release_fb = NULL;
8568
8569 if (!mode)
8570 mode = &load_detect_mode;
8571
8572 /* We need a framebuffer large enough to accommodate all accesses
8573 * that the plane may generate whilst we perform load detection.
8574 * We can not rely on the fbcon either being present (we get called
8575 * during its initialisation to detect all boot displays, or it may
8576 * not even exist) or that it is large enough to satisfy the
8577 * requested mode.
8578 */
8579 fb = mode_fits_in_fbdev(dev, mode);
8580 if (fb == NULL) {
8581 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8582 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8583 old->release_fb = fb;
8584 } else
8585 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8586 if (IS_ERR(fb)) {
8587 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8588 goto fail;
8589 }
8590
8591 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8592 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8593 if (old->release_fb)
8594 old->release_fb->funcs->destroy(old->release_fb);
8595 goto fail;
8596 }
8597
8598 /* let the connector get through one full cycle before testing */
8599 intel_wait_for_vblank(dev, intel_crtc->pipe);
8600 return true;
8601
8602 fail:
8603 intel_crtc->new_enabled = crtc->enabled;
8604 if (intel_crtc->new_enabled)
8605 intel_crtc->new_config = intel_crtc->config;
8606 else
8607 intel_crtc->new_config = NULL;
8608 fail_unlock:
8609 if (ret == -EDEADLK) {
8610 drm_modeset_backoff(ctx);
8611 goto retry;
8612 }
8613
8614 return false;
8615 }
8616
8617 void intel_release_load_detect_pipe(struct drm_connector *connector,
8618 struct intel_load_detect_pipe *old)
8619 {
8620 struct intel_encoder *intel_encoder =
8621 intel_attached_encoder(connector);
8622 struct drm_encoder *encoder = &intel_encoder->base;
8623 struct drm_crtc *crtc = encoder->crtc;
8624 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8625
8626 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8627 connector->base.id, connector->name,
8628 encoder->base.id, encoder->name);
8629
8630 if (old->load_detect_temp) {
8631 to_intel_connector(connector)->new_encoder = NULL;
8632 intel_encoder->new_crtc = NULL;
8633 intel_crtc->new_enabled = false;
8634 intel_crtc->new_config = NULL;
8635 intel_set_mode(crtc, NULL, 0, 0, NULL);
8636
8637 if (old->release_fb) {
8638 drm_framebuffer_unregister_private(old->release_fb);
8639 drm_framebuffer_unreference(old->release_fb);
8640 }
8641
8642 return;
8643 }
8644
8645 /* Switch crtc and encoder back off if necessary */
8646 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8647 connector->funcs->dpms(connector, old->dpms_mode);
8648 }
8649
8650 static int i9xx_pll_refclk(struct drm_device *dev,
8651 const struct intel_crtc_state *pipe_config)
8652 {
8653 struct drm_i915_private *dev_priv = dev->dev_private;
8654 u32 dpll = pipe_config->dpll_hw_state.dpll;
8655
8656 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8657 return dev_priv->vbt.lvds_ssc_freq;
8658 else if (HAS_PCH_SPLIT(dev))
8659 return 120000;
8660 else if (!IS_GEN2(dev))
8661 return 96000;
8662 else
8663 return 48000;
8664 }
8665
8666 /* Returns the clock of the currently programmed mode of the given pipe. */
8667 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8668 struct intel_crtc_state *pipe_config)
8669 {
8670 struct drm_device *dev = crtc->base.dev;
8671 struct drm_i915_private *dev_priv = dev->dev_private;
8672 int pipe = pipe_config->cpu_transcoder;
8673 u32 dpll = pipe_config->dpll_hw_state.dpll;
8674 u32 fp;
8675 intel_clock_t clock;
8676 int refclk = i9xx_pll_refclk(dev, pipe_config);
8677
8678 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8679 fp = pipe_config->dpll_hw_state.fp0;
8680 else
8681 fp = pipe_config->dpll_hw_state.fp1;
8682
8683 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8684 if (IS_PINEVIEW(dev)) {
8685 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8686 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8687 } else {
8688 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8689 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8690 }
8691
8692 if (!IS_GEN2(dev)) {
8693 if (IS_PINEVIEW(dev))
8694 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8695 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8696 else
8697 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8698 DPLL_FPA01_P1_POST_DIV_SHIFT);
8699
8700 switch (dpll & DPLL_MODE_MASK) {
8701 case DPLLB_MODE_DAC_SERIAL:
8702 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8703 5 : 10;
8704 break;
8705 case DPLLB_MODE_LVDS:
8706 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8707 7 : 14;
8708 break;
8709 default:
8710 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8711 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8712 return;
8713 }
8714
8715 if (IS_PINEVIEW(dev))
8716 pineview_clock(refclk, &clock);
8717 else
8718 i9xx_clock(refclk, &clock);
8719 } else {
8720 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8721 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8722
8723 if (is_lvds) {
8724 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8725 DPLL_FPA01_P1_POST_DIV_SHIFT);
8726
8727 if (lvds & LVDS_CLKB_POWER_UP)
8728 clock.p2 = 7;
8729 else
8730 clock.p2 = 14;
8731 } else {
8732 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8733 clock.p1 = 2;
8734 else {
8735 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8736 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8737 }
8738 if (dpll & PLL_P2_DIVIDE_BY_4)
8739 clock.p2 = 4;
8740 else
8741 clock.p2 = 2;
8742 }
8743
8744 i9xx_clock(refclk, &clock);
8745 }
8746
8747 /*
8748 * This value includes pixel_multiplier. We will use
8749 * port_clock to compute adjusted_mode.crtc_clock in the
8750 * encoder's get_config() function.
8751 */
8752 pipe_config->port_clock = clock.dot;
8753 }
8754
8755 int intel_dotclock_calculate(int link_freq,
8756 const struct intel_link_m_n *m_n)
8757 {
8758 /*
8759 * The calculation for the data clock is:
8760 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8761 * But we want to avoid losing precison if possible, so:
8762 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8763 *
8764 * and the link clock is simpler:
8765 * link_clock = (m * link_clock) / n
8766 */
8767
8768 if (!m_n->link_n)
8769 return 0;
8770
8771 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8772 }
8773
8774 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8775 struct intel_crtc_state *pipe_config)
8776 {
8777 struct drm_device *dev = crtc->base.dev;
8778
8779 /* read out port_clock from the DPLL */
8780 i9xx_crtc_clock_get(crtc, pipe_config);
8781
8782 /*
8783 * This value does not include pixel_multiplier.
8784 * We will check that port_clock and adjusted_mode.crtc_clock
8785 * agree once we know their relationship in the encoder's
8786 * get_config() function.
8787 */
8788 pipe_config->base.adjusted_mode.crtc_clock =
8789 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8790 &pipe_config->fdi_m_n);
8791 }
8792
8793 /** Returns the currently programmed mode of the given pipe. */
8794 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8795 struct drm_crtc *crtc)
8796 {
8797 struct drm_i915_private *dev_priv = dev->dev_private;
8798 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8799 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8800 struct drm_display_mode *mode;
8801 struct intel_crtc_state pipe_config;
8802 int htot = I915_READ(HTOTAL(cpu_transcoder));
8803 int hsync = I915_READ(HSYNC(cpu_transcoder));
8804 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8805 int vsync = I915_READ(VSYNC(cpu_transcoder));
8806 enum pipe pipe = intel_crtc->pipe;
8807
8808 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8809 if (!mode)
8810 return NULL;
8811
8812 /*
8813 * Construct a pipe_config sufficient for getting the clock info
8814 * back out of crtc_clock_get.
8815 *
8816 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8817 * to use a real value here instead.
8818 */
8819 pipe_config.cpu_transcoder = (enum transcoder) pipe;
8820 pipe_config.pixel_multiplier = 1;
8821 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8822 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8823 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8824 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8825
8826 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8827 mode->hdisplay = (htot & 0xffff) + 1;
8828 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8829 mode->hsync_start = (hsync & 0xffff) + 1;
8830 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8831 mode->vdisplay = (vtot & 0xffff) + 1;
8832 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8833 mode->vsync_start = (vsync & 0xffff) + 1;
8834 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8835
8836 drm_mode_set_name(mode);
8837
8838 return mode;
8839 }
8840
8841 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8842 {
8843 struct drm_device *dev = crtc->dev;
8844 struct drm_i915_private *dev_priv = dev->dev_private;
8845 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8846
8847 if (!HAS_GMCH_DISPLAY(dev))
8848 return;
8849
8850 if (!dev_priv->lvds_downclock_avail)
8851 return;
8852
8853 /*
8854 * Since this is called by a timer, we should never get here in
8855 * the manual case.
8856 */
8857 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8858 int pipe = intel_crtc->pipe;
8859 int dpll_reg = DPLL(pipe);
8860 int dpll;
8861
8862 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8863
8864 assert_panel_unlocked(dev_priv, pipe);
8865
8866 dpll = I915_READ(dpll_reg);
8867 dpll |= DISPLAY_RATE_SELECT_FPA1;
8868 I915_WRITE(dpll_reg, dpll);
8869 intel_wait_for_vblank(dev, pipe);
8870 dpll = I915_READ(dpll_reg);
8871 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8872 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8873 }
8874
8875 }
8876
8877 void intel_mark_busy(struct drm_device *dev)
8878 {
8879 struct drm_i915_private *dev_priv = dev->dev_private;
8880
8881 if (dev_priv->mm.busy)
8882 return;
8883
8884 intel_runtime_pm_get(dev_priv);
8885 i915_update_gfx_val(dev_priv);
8886 dev_priv->mm.busy = true;
8887 }
8888
8889 void intel_mark_idle(struct drm_device *dev)
8890 {
8891 struct drm_i915_private *dev_priv = dev->dev_private;
8892 struct drm_crtc *crtc;
8893
8894 if (!dev_priv->mm.busy)
8895 return;
8896
8897 dev_priv->mm.busy = false;
8898
8899 if (!i915.powersave)
8900 goto out;
8901
8902 for_each_crtc(dev, crtc) {
8903 if (!crtc->primary->fb)
8904 continue;
8905
8906 intel_decrease_pllclock(crtc);
8907 }
8908
8909 if (INTEL_INFO(dev)->gen >= 6)
8910 gen6_rps_idle(dev->dev_private);
8911
8912 out:
8913 intel_runtime_pm_put(dev_priv);
8914 }
8915
8916 static void intel_crtc_set_state(struct intel_crtc *crtc,
8917 struct intel_crtc_state *crtc_state)
8918 {
8919 kfree(crtc->config);
8920 crtc->config = crtc_state;
8921 crtc->base.state = &crtc_state->base;
8922 }
8923
8924 static void intel_crtc_destroy(struct drm_crtc *crtc)
8925 {
8926 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8927 struct drm_device *dev = crtc->dev;
8928 struct intel_unpin_work *work;
8929
8930 spin_lock_irq(&dev->event_lock);
8931 work = intel_crtc->unpin_work;
8932 intel_crtc->unpin_work = NULL;
8933 spin_unlock_irq(&dev->event_lock);
8934
8935 if (work) {
8936 cancel_work_sync(&work->work);
8937 kfree(work);
8938 }
8939
8940 intel_crtc_set_state(intel_crtc, NULL);
8941 drm_crtc_cleanup(crtc);
8942
8943 kfree(intel_crtc);
8944 }
8945
8946 static void intel_unpin_work_fn(struct work_struct *__work)
8947 {
8948 struct intel_unpin_work *work =
8949 container_of(__work, struct intel_unpin_work, work);
8950 struct drm_device *dev = work->crtc->dev;
8951 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
8952
8953 mutex_lock(&dev->struct_mutex);
8954 intel_unpin_fb_obj(work->old_fb_obj);
8955 drm_gem_object_unreference(&work->pending_flip_obj->base);
8956 drm_gem_object_unreference(&work->old_fb_obj->base);
8957
8958 intel_fbc_update(dev);
8959
8960 if (work->flip_queued_req)
8961 i915_gem_request_assign(&work->flip_queued_req, NULL);
8962 mutex_unlock(&dev->struct_mutex);
8963
8964 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
8965
8966 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8967 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8968
8969 kfree(work);
8970 }
8971
8972 static void do_intel_finish_page_flip(struct drm_device *dev,
8973 struct drm_crtc *crtc)
8974 {
8975 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8976 struct intel_unpin_work *work;
8977 unsigned long flags;
8978
8979 /* Ignore early vblank irqs */
8980 if (intel_crtc == NULL)
8981 return;
8982
8983 /*
8984 * This is called both by irq handlers and the reset code (to complete
8985 * lost pageflips) so needs the full irqsave spinlocks.
8986 */
8987 spin_lock_irqsave(&dev->event_lock, flags);
8988 work = intel_crtc->unpin_work;
8989
8990 /* Ensure we don't miss a work->pending update ... */
8991 smp_rmb();
8992
8993 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8994 spin_unlock_irqrestore(&dev->event_lock, flags);
8995 return;
8996 }
8997
8998 page_flip_completed(intel_crtc);
8999
9000 spin_unlock_irqrestore(&dev->event_lock, flags);
9001 }
9002
9003 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9004 {
9005 struct drm_i915_private *dev_priv = dev->dev_private;
9006 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9007
9008 do_intel_finish_page_flip(dev, crtc);
9009 }
9010
9011 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9012 {
9013 struct drm_i915_private *dev_priv = dev->dev_private;
9014 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9015
9016 do_intel_finish_page_flip(dev, crtc);
9017 }
9018
9019 /* Is 'a' after or equal to 'b'? */
9020 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9021 {
9022 return !((a - b) & 0x80000000);
9023 }
9024
9025 static bool page_flip_finished(struct intel_crtc *crtc)
9026 {
9027 struct drm_device *dev = crtc->base.dev;
9028 struct drm_i915_private *dev_priv = dev->dev_private;
9029
9030 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
9031 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
9032 return true;
9033
9034 /*
9035 * The relevant registers doen't exist on pre-ctg.
9036 * As the flip done interrupt doesn't trigger for mmio
9037 * flips on gmch platforms, a flip count check isn't
9038 * really needed there. But since ctg has the registers,
9039 * include it in the check anyway.
9040 */
9041 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9042 return true;
9043
9044 /*
9045 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9046 * used the same base address. In that case the mmio flip might
9047 * have completed, but the CS hasn't even executed the flip yet.
9048 *
9049 * A flip count check isn't enough as the CS might have updated
9050 * the base address just after start of vblank, but before we
9051 * managed to process the interrupt. This means we'd complete the
9052 * CS flip too soon.
9053 *
9054 * Combining both checks should get us a good enough result. It may
9055 * still happen that the CS flip has been executed, but has not
9056 * yet actually completed. But in case the base address is the same
9057 * anyway, we don't really care.
9058 */
9059 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9060 crtc->unpin_work->gtt_offset &&
9061 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9062 crtc->unpin_work->flip_count);
9063 }
9064
9065 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9066 {
9067 struct drm_i915_private *dev_priv = dev->dev_private;
9068 struct intel_crtc *intel_crtc =
9069 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9070 unsigned long flags;
9071
9072
9073 /*
9074 * This is called both by irq handlers and the reset code (to complete
9075 * lost pageflips) so needs the full irqsave spinlocks.
9076 *
9077 * NB: An MMIO update of the plane base pointer will also
9078 * generate a page-flip completion irq, i.e. every modeset
9079 * is also accompanied by a spurious intel_prepare_page_flip().
9080 */
9081 spin_lock_irqsave(&dev->event_lock, flags);
9082 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9083 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9084 spin_unlock_irqrestore(&dev->event_lock, flags);
9085 }
9086
9087 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9088 {
9089 /* Ensure that the work item is consistent when activating it ... */
9090 smp_wmb();
9091 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9092 /* and that it is marked active as soon as the irq could fire. */
9093 smp_wmb();
9094 }
9095
9096 static int intel_gen2_queue_flip(struct drm_device *dev,
9097 struct drm_crtc *crtc,
9098 struct drm_framebuffer *fb,
9099 struct drm_i915_gem_object *obj,
9100 struct intel_engine_cs *ring,
9101 uint32_t flags)
9102 {
9103 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9104 u32 flip_mask;
9105 int ret;
9106
9107 ret = intel_ring_begin(ring, 6);
9108 if (ret)
9109 return ret;
9110
9111 /* Can't queue multiple flips, so wait for the previous
9112 * one to finish before executing the next.
9113 */
9114 if (intel_crtc->plane)
9115 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9116 else
9117 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9118 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9119 intel_ring_emit(ring, MI_NOOP);
9120 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9121 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9122 intel_ring_emit(ring, fb->pitches[0]);
9123 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9124 intel_ring_emit(ring, 0); /* aux display base address, unused */
9125
9126 intel_mark_page_flip_active(intel_crtc);
9127 __intel_ring_advance(ring);
9128 return 0;
9129 }
9130
9131 static int intel_gen3_queue_flip(struct drm_device *dev,
9132 struct drm_crtc *crtc,
9133 struct drm_framebuffer *fb,
9134 struct drm_i915_gem_object *obj,
9135 struct intel_engine_cs *ring,
9136 uint32_t flags)
9137 {
9138 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9139 u32 flip_mask;
9140 int ret;
9141
9142 ret = intel_ring_begin(ring, 6);
9143 if (ret)
9144 return ret;
9145
9146 if (intel_crtc->plane)
9147 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9148 else
9149 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9150 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9151 intel_ring_emit(ring, MI_NOOP);
9152 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9153 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9154 intel_ring_emit(ring, fb->pitches[0]);
9155 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9156 intel_ring_emit(ring, MI_NOOP);
9157
9158 intel_mark_page_flip_active(intel_crtc);
9159 __intel_ring_advance(ring);
9160 return 0;
9161 }
9162
9163 static int intel_gen4_queue_flip(struct drm_device *dev,
9164 struct drm_crtc *crtc,
9165 struct drm_framebuffer *fb,
9166 struct drm_i915_gem_object *obj,
9167 struct intel_engine_cs *ring,
9168 uint32_t flags)
9169 {
9170 struct drm_i915_private *dev_priv = dev->dev_private;
9171 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9172 uint32_t pf, pipesrc;
9173 int ret;
9174
9175 ret = intel_ring_begin(ring, 4);
9176 if (ret)
9177 return ret;
9178
9179 /* i965+ uses the linear or tiled offsets from the
9180 * Display Registers (which do not change across a page-flip)
9181 * so we need only reprogram the base address.
9182 */
9183 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9184 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9185 intel_ring_emit(ring, fb->pitches[0]);
9186 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9187 obj->tiling_mode);
9188
9189 /* XXX Enabling the panel-fitter across page-flip is so far
9190 * untested on non-native modes, so ignore it for now.
9191 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9192 */
9193 pf = 0;
9194 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9195 intel_ring_emit(ring, pf | pipesrc);
9196
9197 intel_mark_page_flip_active(intel_crtc);
9198 __intel_ring_advance(ring);
9199 return 0;
9200 }
9201
9202 static int intel_gen6_queue_flip(struct drm_device *dev,
9203 struct drm_crtc *crtc,
9204 struct drm_framebuffer *fb,
9205 struct drm_i915_gem_object *obj,
9206 struct intel_engine_cs *ring,
9207 uint32_t flags)
9208 {
9209 struct drm_i915_private *dev_priv = dev->dev_private;
9210 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9211 uint32_t pf, pipesrc;
9212 int ret;
9213
9214 ret = intel_ring_begin(ring, 4);
9215 if (ret)
9216 return ret;
9217
9218 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9219 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9220 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9221 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9222
9223 /* Contrary to the suggestions in the documentation,
9224 * "Enable Panel Fitter" does not seem to be required when page
9225 * flipping with a non-native mode, and worse causes a normal
9226 * modeset to fail.
9227 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9228 */
9229 pf = 0;
9230 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9231 intel_ring_emit(ring, pf | pipesrc);
9232
9233 intel_mark_page_flip_active(intel_crtc);
9234 __intel_ring_advance(ring);
9235 return 0;
9236 }
9237
9238 static int intel_gen7_queue_flip(struct drm_device *dev,
9239 struct drm_crtc *crtc,
9240 struct drm_framebuffer *fb,
9241 struct drm_i915_gem_object *obj,
9242 struct intel_engine_cs *ring,
9243 uint32_t flags)
9244 {
9245 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9246 uint32_t plane_bit = 0;
9247 int len, ret;
9248
9249 switch (intel_crtc->plane) {
9250 case PLANE_A:
9251 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9252 break;
9253 case PLANE_B:
9254 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9255 break;
9256 case PLANE_C:
9257 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9258 break;
9259 default:
9260 WARN_ONCE(1, "unknown plane in flip command\n");
9261 return -ENODEV;
9262 }
9263
9264 len = 4;
9265 if (ring->id == RCS) {
9266 len += 6;
9267 /*
9268 * On Gen 8, SRM is now taking an extra dword to accommodate
9269 * 48bits addresses, and we need a NOOP for the batch size to
9270 * stay even.
9271 */
9272 if (IS_GEN8(dev))
9273 len += 2;
9274 }
9275
9276 /*
9277 * BSpec MI_DISPLAY_FLIP for IVB:
9278 * "The full packet must be contained within the same cache line."
9279 *
9280 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9281 * cacheline, if we ever start emitting more commands before
9282 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9283 * then do the cacheline alignment, and finally emit the
9284 * MI_DISPLAY_FLIP.
9285 */
9286 ret = intel_ring_cacheline_align(ring);
9287 if (ret)
9288 return ret;
9289
9290 ret = intel_ring_begin(ring, len);
9291 if (ret)
9292 return ret;
9293
9294 /* Unmask the flip-done completion message. Note that the bspec says that
9295 * we should do this for both the BCS and RCS, and that we must not unmask
9296 * more than one flip event at any time (or ensure that one flip message
9297 * can be sent by waiting for flip-done prior to queueing new flips).
9298 * Experimentation says that BCS works despite DERRMR masking all
9299 * flip-done completion events and that unmasking all planes at once
9300 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9301 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9302 */
9303 if (ring->id == RCS) {
9304 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9305 intel_ring_emit(ring, DERRMR);
9306 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9307 DERRMR_PIPEB_PRI_FLIP_DONE |
9308 DERRMR_PIPEC_PRI_FLIP_DONE));
9309 if (IS_GEN8(dev))
9310 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9311 MI_SRM_LRM_GLOBAL_GTT);
9312 else
9313 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9314 MI_SRM_LRM_GLOBAL_GTT);
9315 intel_ring_emit(ring, DERRMR);
9316 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9317 if (IS_GEN8(dev)) {
9318 intel_ring_emit(ring, 0);
9319 intel_ring_emit(ring, MI_NOOP);
9320 }
9321 }
9322
9323 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9324 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9325 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9326 intel_ring_emit(ring, (MI_NOOP));
9327
9328 intel_mark_page_flip_active(intel_crtc);
9329 __intel_ring_advance(ring);
9330 return 0;
9331 }
9332
9333 static bool use_mmio_flip(struct intel_engine_cs *ring,
9334 struct drm_i915_gem_object *obj)
9335 {
9336 /*
9337 * This is not being used for older platforms, because
9338 * non-availability of flip done interrupt forces us to use
9339 * CS flips. Older platforms derive flip done using some clever
9340 * tricks involving the flip_pending status bits and vblank irqs.
9341 * So using MMIO flips there would disrupt this mechanism.
9342 */
9343
9344 if (ring == NULL)
9345 return true;
9346
9347 if (INTEL_INFO(ring->dev)->gen < 5)
9348 return false;
9349
9350 if (i915.use_mmio_flip < 0)
9351 return false;
9352 else if (i915.use_mmio_flip > 0)
9353 return true;
9354 else if (i915.enable_execlists)
9355 return true;
9356 else
9357 return ring != i915_gem_request_get_ring(obj->last_read_req);
9358 }
9359
9360 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
9361 {
9362 struct drm_device *dev = intel_crtc->base.dev;
9363 struct drm_i915_private *dev_priv = dev->dev_private;
9364 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
9365 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9366 struct drm_i915_gem_object *obj = intel_fb->obj;
9367 const enum pipe pipe = intel_crtc->pipe;
9368 u32 ctl, stride;
9369
9370 ctl = I915_READ(PLANE_CTL(pipe, 0));
9371 ctl &= ~PLANE_CTL_TILED_MASK;
9372 if (obj->tiling_mode == I915_TILING_X)
9373 ctl |= PLANE_CTL_TILED_X;
9374
9375 /*
9376 * The stride is either expressed as a multiple of 64 bytes chunks for
9377 * linear buffers or in number of tiles for tiled buffers.
9378 */
9379 stride = fb->pitches[0] >> 6;
9380 if (obj->tiling_mode == I915_TILING_X)
9381 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
9382
9383 /*
9384 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
9385 * PLANE_SURF updates, the update is then guaranteed to be atomic.
9386 */
9387 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
9388 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
9389
9390 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
9391 POSTING_READ(PLANE_SURF(pipe, 0));
9392 }
9393
9394 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
9395 {
9396 struct drm_device *dev = intel_crtc->base.dev;
9397 struct drm_i915_private *dev_priv = dev->dev_private;
9398 struct intel_framebuffer *intel_fb =
9399 to_intel_framebuffer(intel_crtc->base.primary->fb);
9400 struct drm_i915_gem_object *obj = intel_fb->obj;
9401 u32 dspcntr;
9402 u32 reg;
9403
9404 reg = DSPCNTR(intel_crtc->plane);
9405 dspcntr = I915_READ(reg);
9406
9407 if (obj->tiling_mode != I915_TILING_NONE)
9408 dspcntr |= DISPPLANE_TILED;
9409 else
9410 dspcntr &= ~DISPPLANE_TILED;
9411
9412 I915_WRITE(reg, dspcntr);
9413
9414 I915_WRITE(DSPSURF(intel_crtc->plane),
9415 intel_crtc->unpin_work->gtt_offset);
9416 POSTING_READ(DSPSURF(intel_crtc->plane));
9417
9418 }
9419
9420 /*
9421 * XXX: This is the temporary way to update the plane registers until we get
9422 * around to using the usual plane update functions for MMIO flips
9423 */
9424 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9425 {
9426 struct drm_device *dev = intel_crtc->base.dev;
9427 bool atomic_update;
9428 u32 start_vbl_count;
9429
9430 intel_mark_page_flip_active(intel_crtc);
9431
9432 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9433
9434 if (INTEL_INFO(dev)->gen >= 9)
9435 skl_do_mmio_flip(intel_crtc);
9436 else
9437 /* use_mmio_flip() retricts MMIO flips to ilk+ */
9438 ilk_do_mmio_flip(intel_crtc);
9439
9440 if (atomic_update)
9441 intel_pipe_update_end(intel_crtc, start_vbl_count);
9442 }
9443
9444 static void intel_mmio_flip_work_func(struct work_struct *work)
9445 {
9446 struct intel_crtc *crtc =
9447 container_of(work, struct intel_crtc, mmio_flip.work);
9448 struct intel_mmio_flip *mmio_flip;
9449
9450 mmio_flip = &crtc->mmio_flip;
9451 if (mmio_flip->req)
9452 WARN_ON(__i915_wait_request(mmio_flip->req,
9453 crtc->reset_counter,
9454 false, NULL, NULL) != 0);
9455
9456 intel_do_mmio_flip(crtc);
9457 if (mmio_flip->req) {
9458 mutex_lock(&crtc->base.dev->struct_mutex);
9459 i915_gem_request_assign(&mmio_flip->req, NULL);
9460 mutex_unlock(&crtc->base.dev->struct_mutex);
9461 }
9462 }
9463
9464 static int intel_queue_mmio_flip(struct drm_device *dev,
9465 struct drm_crtc *crtc,
9466 struct drm_framebuffer *fb,
9467 struct drm_i915_gem_object *obj,
9468 struct intel_engine_cs *ring,
9469 uint32_t flags)
9470 {
9471 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9472
9473 i915_gem_request_assign(&intel_crtc->mmio_flip.req,
9474 obj->last_write_req);
9475
9476 schedule_work(&intel_crtc->mmio_flip.work);
9477
9478 return 0;
9479 }
9480
9481 static int intel_gen9_queue_flip(struct drm_device *dev,
9482 struct drm_crtc *crtc,
9483 struct drm_framebuffer *fb,
9484 struct drm_i915_gem_object *obj,
9485 struct intel_engine_cs *ring,
9486 uint32_t flags)
9487 {
9488 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9489 uint32_t plane = 0, stride;
9490 int ret;
9491
9492 switch(intel_crtc->pipe) {
9493 case PIPE_A:
9494 plane = MI_DISPLAY_FLIP_SKL_PLANE_1_A;
9495 break;
9496 case PIPE_B:
9497 plane = MI_DISPLAY_FLIP_SKL_PLANE_1_B;
9498 break;
9499 case PIPE_C:
9500 plane = MI_DISPLAY_FLIP_SKL_PLANE_1_C;
9501 break;
9502 default:
9503 WARN_ONCE(1, "unknown plane in flip command\n");
9504 return -ENODEV;
9505 }
9506
9507 switch (obj->tiling_mode) {
9508 case I915_TILING_NONE:
9509 stride = fb->pitches[0] >> 6;
9510 break;
9511 case I915_TILING_X:
9512 stride = fb->pitches[0] >> 9;
9513 break;
9514 default:
9515 WARN_ONCE(1, "unknown tiling in flip command\n");
9516 return -ENODEV;
9517 }
9518
9519 ret = intel_ring_begin(ring, 10);
9520 if (ret)
9521 return ret;
9522
9523 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9524 intel_ring_emit(ring, DERRMR);
9525 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9526 DERRMR_PIPEB_PRI_FLIP_DONE |
9527 DERRMR_PIPEC_PRI_FLIP_DONE));
9528 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9529 MI_SRM_LRM_GLOBAL_GTT);
9530 intel_ring_emit(ring, DERRMR);
9531 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9532 intel_ring_emit(ring, 0);
9533
9534 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane);
9535 intel_ring_emit(ring, stride << 6 | obj->tiling_mode);
9536 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9537
9538 intel_mark_page_flip_active(intel_crtc);
9539 __intel_ring_advance(ring);
9540
9541 return 0;
9542 }
9543
9544 static int intel_default_queue_flip(struct drm_device *dev,
9545 struct drm_crtc *crtc,
9546 struct drm_framebuffer *fb,
9547 struct drm_i915_gem_object *obj,
9548 struct intel_engine_cs *ring,
9549 uint32_t flags)
9550 {
9551 return -ENODEV;
9552 }
9553
9554 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9555 struct drm_crtc *crtc)
9556 {
9557 struct drm_i915_private *dev_priv = dev->dev_private;
9558 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9559 struct intel_unpin_work *work = intel_crtc->unpin_work;
9560 u32 addr;
9561
9562 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9563 return true;
9564
9565 if (!work->enable_stall_check)
9566 return false;
9567
9568 if (work->flip_ready_vblank == 0) {
9569 if (work->flip_queued_req &&
9570 !i915_gem_request_completed(work->flip_queued_req, true))
9571 return false;
9572
9573 work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9574 }
9575
9576 if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3)
9577 return false;
9578
9579 /* Potential stall - if we see that the flip has happened,
9580 * assume a missed interrupt. */
9581 if (INTEL_INFO(dev)->gen >= 4)
9582 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9583 else
9584 addr = I915_READ(DSPADDR(intel_crtc->plane));
9585
9586 /* There is a potential issue here with a false positive after a flip
9587 * to the same address. We could address this by checking for a
9588 * non-incrementing frame counter.
9589 */
9590 return addr == work->gtt_offset;
9591 }
9592
9593 void intel_check_page_flip(struct drm_device *dev, int pipe)
9594 {
9595 struct drm_i915_private *dev_priv = dev->dev_private;
9596 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9597 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9598
9599 WARN_ON(!in_irq());
9600
9601 if (crtc == NULL)
9602 return;
9603
9604 spin_lock(&dev->event_lock);
9605 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9606 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9607 intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe));
9608 page_flip_completed(intel_crtc);
9609 }
9610 spin_unlock(&dev->event_lock);
9611 }
9612
9613 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9614 struct drm_framebuffer *fb,
9615 struct drm_pending_vblank_event *event,
9616 uint32_t page_flip_flags)
9617 {
9618 struct drm_device *dev = crtc->dev;
9619 struct drm_i915_private *dev_priv = dev->dev_private;
9620 struct drm_framebuffer *old_fb = crtc->primary->fb;
9621 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9622 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9623 struct drm_plane *primary = crtc->primary;
9624 enum pipe pipe = intel_crtc->pipe;
9625 struct intel_unpin_work *work;
9626 struct intel_engine_cs *ring;
9627 int ret;
9628
9629 /*
9630 * drm_mode_page_flip_ioctl() should already catch this, but double
9631 * check to be safe. In the future we may enable pageflipping from
9632 * a disabled primary plane.
9633 */
9634 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9635 return -EBUSY;
9636
9637 /* Can't change pixel format via MI display flips. */
9638 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9639 return -EINVAL;
9640
9641 /*
9642 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9643 * Note that pitch changes could also affect these register.
9644 */
9645 if (INTEL_INFO(dev)->gen > 3 &&
9646 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9647 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9648 return -EINVAL;
9649
9650 if (i915_terminally_wedged(&dev_priv->gpu_error))
9651 goto out_hang;
9652
9653 work = kzalloc(sizeof(*work), GFP_KERNEL);
9654 if (work == NULL)
9655 return -ENOMEM;
9656
9657 work->event = event;
9658 work->crtc = crtc;
9659 work->old_fb_obj = intel_fb_obj(old_fb);
9660 INIT_WORK(&work->work, intel_unpin_work_fn);
9661
9662 ret = drm_crtc_vblank_get(crtc);
9663 if (ret)
9664 goto free_work;
9665
9666 /* We borrow the event spin lock for protecting unpin_work */
9667 spin_lock_irq(&dev->event_lock);
9668 if (intel_crtc->unpin_work) {
9669 /* Before declaring the flip queue wedged, check if
9670 * the hardware completed the operation behind our backs.
9671 */
9672 if (__intel_pageflip_stall_check(dev, crtc)) {
9673 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9674 page_flip_completed(intel_crtc);
9675 } else {
9676 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9677 spin_unlock_irq(&dev->event_lock);
9678
9679 drm_crtc_vblank_put(crtc);
9680 kfree(work);
9681 return -EBUSY;
9682 }
9683 }
9684 intel_crtc->unpin_work = work;
9685 spin_unlock_irq(&dev->event_lock);
9686
9687 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9688 flush_workqueue(dev_priv->wq);
9689
9690 ret = i915_mutex_lock_interruptible(dev);
9691 if (ret)
9692 goto cleanup;
9693
9694 /* Reference the objects for the scheduled work. */
9695 drm_gem_object_reference(&work->old_fb_obj->base);
9696 drm_gem_object_reference(&obj->base);
9697
9698 crtc->primary->fb = fb;
9699
9700 work->pending_flip_obj = obj;
9701
9702 atomic_inc(&intel_crtc->unpin_work_count);
9703 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9704
9705 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9706 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9707
9708 if (IS_VALLEYVIEW(dev)) {
9709 ring = &dev_priv->ring[BCS];
9710 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9711 /* vlv: DISPLAY_FLIP fails to change tiling */
9712 ring = NULL;
9713 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
9714 ring = &dev_priv->ring[BCS];
9715 } else if (INTEL_INFO(dev)->gen >= 7) {
9716 ring = i915_gem_request_get_ring(obj->last_read_req);
9717 if (ring == NULL || ring->id != RCS)
9718 ring = &dev_priv->ring[BCS];
9719 } else {
9720 ring = &dev_priv->ring[RCS];
9721 }
9722
9723 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, ring);
9724 if (ret)
9725 goto cleanup_pending;
9726
9727 work->gtt_offset =
9728 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9729
9730 if (use_mmio_flip(ring, obj)) {
9731 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9732 page_flip_flags);
9733 if (ret)
9734 goto cleanup_unpin;
9735
9736 i915_gem_request_assign(&work->flip_queued_req,
9737 obj->last_write_req);
9738 } else {
9739 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9740 page_flip_flags);
9741 if (ret)
9742 goto cleanup_unpin;
9743
9744 i915_gem_request_assign(&work->flip_queued_req,
9745 intel_ring_get_request(ring));
9746 }
9747
9748 work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9749 work->enable_stall_check = true;
9750
9751 i915_gem_track_fb(work->old_fb_obj, obj,
9752 INTEL_FRONTBUFFER_PRIMARY(pipe));
9753
9754 intel_fbc_disable(dev);
9755 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9756 mutex_unlock(&dev->struct_mutex);
9757
9758 trace_i915_flip_request(intel_crtc->plane, obj);
9759
9760 return 0;
9761
9762 cleanup_unpin:
9763 intel_unpin_fb_obj(obj);
9764 cleanup_pending:
9765 atomic_dec(&intel_crtc->unpin_work_count);
9766 crtc->primary->fb = old_fb;
9767 drm_gem_object_unreference(&work->old_fb_obj->base);
9768 drm_gem_object_unreference(&obj->base);
9769 mutex_unlock(&dev->struct_mutex);
9770
9771 cleanup:
9772 spin_lock_irq(&dev->event_lock);
9773 intel_crtc->unpin_work = NULL;
9774 spin_unlock_irq(&dev->event_lock);
9775
9776 drm_crtc_vblank_put(crtc);
9777 free_work:
9778 kfree(work);
9779
9780 if (ret == -EIO) {
9781 out_hang:
9782 ret = intel_plane_restore(primary);
9783 if (ret == 0 && event) {
9784 spin_lock_irq(&dev->event_lock);
9785 drm_send_vblank_event(dev, pipe, event);
9786 spin_unlock_irq(&dev->event_lock);
9787 }
9788 }
9789 return ret;
9790 }
9791
9792 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9793 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9794 .load_lut = intel_crtc_load_lut,
9795 .atomic_begin = intel_begin_crtc_commit,
9796 .atomic_flush = intel_finish_crtc_commit,
9797 };
9798
9799 /**
9800 * intel_modeset_update_staged_output_state
9801 *
9802 * Updates the staged output configuration state, e.g. after we've read out the
9803 * current hw state.
9804 */
9805 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9806 {
9807 struct intel_crtc *crtc;
9808 struct intel_encoder *encoder;
9809 struct intel_connector *connector;
9810
9811 list_for_each_entry(connector, &dev->mode_config.connector_list,
9812 base.head) {
9813 connector->new_encoder =
9814 to_intel_encoder(connector->base.encoder);
9815 }
9816
9817 for_each_intel_encoder(dev, encoder) {
9818 encoder->new_crtc =
9819 to_intel_crtc(encoder->base.crtc);
9820 }
9821
9822 for_each_intel_crtc(dev, crtc) {
9823 crtc->new_enabled = crtc->base.enabled;
9824
9825 if (crtc->new_enabled)
9826 crtc->new_config = crtc->config;
9827 else
9828 crtc->new_config = NULL;
9829 }
9830 }
9831
9832 /**
9833 * intel_modeset_commit_output_state
9834 *
9835 * This function copies the stage display pipe configuration to the real one.
9836 */
9837 static void intel_modeset_commit_output_state(struct drm_device *dev)
9838 {
9839 struct intel_crtc *crtc;
9840 struct intel_encoder *encoder;
9841 struct intel_connector *connector;
9842
9843 list_for_each_entry(connector, &dev->mode_config.connector_list,
9844 base.head) {
9845 connector->base.encoder = &connector->new_encoder->base;
9846 }
9847
9848 for_each_intel_encoder(dev, encoder) {
9849 encoder->base.crtc = &encoder->new_crtc->base;
9850 }
9851
9852 for_each_intel_crtc(dev, crtc) {
9853 crtc->base.enabled = crtc->new_enabled;
9854 }
9855 }
9856
9857 static void
9858 connected_sink_compute_bpp(struct intel_connector *connector,
9859 struct intel_crtc_state *pipe_config)
9860 {
9861 int bpp = pipe_config->pipe_bpp;
9862
9863 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9864 connector->base.base.id,
9865 connector->base.name);
9866
9867 /* Don't use an invalid EDID bpc value */
9868 if (connector->base.display_info.bpc &&
9869 connector->base.display_info.bpc * 3 < bpp) {
9870 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9871 bpp, connector->base.display_info.bpc*3);
9872 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9873 }
9874
9875 /* Clamp bpp to 8 on screens without EDID 1.4 */
9876 if (connector->base.display_info.bpc == 0 && bpp > 24) {
9877 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9878 bpp);
9879 pipe_config->pipe_bpp = 24;
9880 }
9881 }
9882
9883 static int
9884 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9885 struct drm_framebuffer *fb,
9886 struct intel_crtc_state *pipe_config)
9887 {
9888 struct drm_device *dev = crtc->base.dev;
9889 struct intel_connector *connector;
9890 int bpp;
9891
9892 switch (fb->pixel_format) {
9893 case DRM_FORMAT_C8:
9894 bpp = 8*3; /* since we go through a colormap */
9895 break;
9896 case DRM_FORMAT_XRGB1555:
9897 case DRM_FORMAT_ARGB1555:
9898 /* checked in intel_framebuffer_init already */
9899 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9900 return -EINVAL;
9901 case DRM_FORMAT_RGB565:
9902 bpp = 6*3; /* min is 18bpp */
9903 break;
9904 case DRM_FORMAT_XBGR8888:
9905 case DRM_FORMAT_ABGR8888:
9906 /* checked in intel_framebuffer_init already */
9907 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9908 return -EINVAL;
9909 case DRM_FORMAT_XRGB8888:
9910 case DRM_FORMAT_ARGB8888:
9911 bpp = 8*3;
9912 break;
9913 case DRM_FORMAT_XRGB2101010:
9914 case DRM_FORMAT_ARGB2101010:
9915 case DRM_FORMAT_XBGR2101010:
9916 case DRM_FORMAT_ABGR2101010:
9917 /* checked in intel_framebuffer_init already */
9918 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9919 return -EINVAL;
9920 bpp = 10*3;
9921 break;
9922 /* TODO: gen4+ supports 16 bpc floating point, too. */
9923 default:
9924 DRM_DEBUG_KMS("unsupported depth\n");
9925 return -EINVAL;
9926 }
9927
9928 pipe_config->pipe_bpp = bpp;
9929
9930 /* Clamp display bpp to EDID value */
9931 list_for_each_entry(connector, &dev->mode_config.connector_list,
9932 base.head) {
9933 if (!connector->new_encoder ||
9934 connector->new_encoder->new_crtc != crtc)
9935 continue;
9936
9937 connected_sink_compute_bpp(connector, pipe_config);
9938 }
9939
9940 return bpp;
9941 }
9942
9943 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9944 {
9945 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9946 "type: 0x%x flags: 0x%x\n",
9947 mode->crtc_clock,
9948 mode->crtc_hdisplay, mode->crtc_hsync_start,
9949 mode->crtc_hsync_end, mode->crtc_htotal,
9950 mode->crtc_vdisplay, mode->crtc_vsync_start,
9951 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9952 }
9953
9954 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9955 struct intel_crtc_state *pipe_config,
9956 const char *context)
9957 {
9958 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9959 context, pipe_name(crtc->pipe));
9960
9961 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9962 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9963 pipe_config->pipe_bpp, pipe_config->dither);
9964 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9965 pipe_config->has_pch_encoder,
9966 pipe_config->fdi_lanes,
9967 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9968 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9969 pipe_config->fdi_m_n.tu);
9970 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9971 pipe_config->has_dp_encoder,
9972 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9973 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9974 pipe_config->dp_m_n.tu);
9975
9976 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
9977 pipe_config->has_dp_encoder,
9978 pipe_config->dp_m2_n2.gmch_m,
9979 pipe_config->dp_m2_n2.gmch_n,
9980 pipe_config->dp_m2_n2.link_m,
9981 pipe_config->dp_m2_n2.link_n,
9982 pipe_config->dp_m2_n2.tu);
9983
9984 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
9985 pipe_config->has_audio,
9986 pipe_config->has_infoframe);
9987
9988 DRM_DEBUG_KMS("requested mode:\n");
9989 drm_mode_debug_printmodeline(&pipe_config->base.mode);
9990 DRM_DEBUG_KMS("adjusted mode:\n");
9991 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
9992 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
9993 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9994 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9995 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9996 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9997 pipe_config->gmch_pfit.control,
9998 pipe_config->gmch_pfit.pgm_ratios,
9999 pipe_config->gmch_pfit.lvds_border_bits);
10000 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10001 pipe_config->pch_pfit.pos,
10002 pipe_config->pch_pfit.size,
10003 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10004 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10005 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10006 }
10007
10008 static bool encoders_cloneable(const struct intel_encoder *a,
10009 const struct intel_encoder *b)
10010 {
10011 /* masks could be asymmetric, so check both ways */
10012 return a == b || (a->cloneable & (1 << b->type) &&
10013 b->cloneable & (1 << a->type));
10014 }
10015
10016 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10017 struct intel_encoder *encoder)
10018 {
10019 struct drm_device *dev = crtc->base.dev;
10020 struct intel_encoder *source_encoder;
10021
10022 for_each_intel_encoder(dev, source_encoder) {
10023 if (source_encoder->new_crtc != crtc)
10024 continue;
10025
10026 if (!encoders_cloneable(encoder, source_encoder))
10027 return false;
10028 }
10029
10030 return true;
10031 }
10032
10033 static bool check_encoder_cloning(struct intel_crtc *crtc)
10034 {
10035 struct drm_device *dev = crtc->base.dev;
10036 struct intel_encoder *encoder;
10037
10038 for_each_intel_encoder(dev, encoder) {
10039 if (encoder->new_crtc != crtc)
10040 continue;
10041
10042 if (!check_single_encoder_cloning(crtc, encoder))
10043 return false;
10044 }
10045
10046 return true;
10047 }
10048
10049 static bool check_digital_port_conflicts(struct drm_device *dev)
10050 {
10051 struct intel_connector *connector;
10052 unsigned int used_ports = 0;
10053
10054 /*
10055 * Walk the connector list instead of the encoder
10056 * list to detect the problem on ddi platforms
10057 * where there's just one encoder per digital port.
10058 */
10059 list_for_each_entry(connector,
10060 &dev->mode_config.connector_list, base.head) {
10061 struct intel_encoder *encoder = connector->new_encoder;
10062
10063 if (!encoder)
10064 continue;
10065
10066 WARN_ON(!encoder->new_crtc);
10067
10068 switch (encoder->type) {
10069 unsigned int port_mask;
10070 case INTEL_OUTPUT_UNKNOWN:
10071 if (WARN_ON(!HAS_DDI(dev)))
10072 break;
10073 case INTEL_OUTPUT_DISPLAYPORT:
10074 case INTEL_OUTPUT_HDMI:
10075 case INTEL_OUTPUT_EDP:
10076 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10077
10078 /* the same port mustn't appear more than once */
10079 if (used_ports & port_mask)
10080 return false;
10081
10082 used_ports |= port_mask;
10083 default:
10084 break;
10085 }
10086 }
10087
10088 return true;
10089 }
10090
10091 static struct intel_crtc_state *
10092 intel_modeset_pipe_config(struct drm_crtc *crtc,
10093 struct drm_framebuffer *fb,
10094 struct drm_display_mode *mode)
10095 {
10096 struct drm_device *dev = crtc->dev;
10097 struct intel_encoder *encoder;
10098 struct intel_crtc_state *pipe_config;
10099 int plane_bpp, ret = -EINVAL;
10100 bool retry = true;
10101
10102 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10103 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10104 return ERR_PTR(-EINVAL);
10105 }
10106
10107 if (!check_digital_port_conflicts(dev)) {
10108 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10109 return ERR_PTR(-EINVAL);
10110 }
10111
10112 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10113 if (!pipe_config)
10114 return ERR_PTR(-ENOMEM);
10115
10116 drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
10117 drm_mode_copy(&pipe_config->base.mode, mode);
10118
10119 pipe_config->cpu_transcoder =
10120 (enum transcoder) to_intel_crtc(crtc)->pipe;
10121 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10122
10123 /*
10124 * Sanitize sync polarity flags based on requested ones. If neither
10125 * positive or negative polarity is requested, treat this as meaning
10126 * negative polarity.
10127 */
10128 if (!(pipe_config->base.adjusted_mode.flags &
10129 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10130 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10131
10132 if (!(pipe_config->base.adjusted_mode.flags &
10133 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10134 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10135
10136 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10137 * plane pixel format and any sink constraints into account. Returns the
10138 * source plane bpp so that dithering can be selected on mismatches
10139 * after encoders and crtc also have had their say. */
10140 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10141 fb, pipe_config);
10142 if (plane_bpp < 0)
10143 goto fail;
10144
10145 /*
10146 * Determine the real pipe dimensions. Note that stereo modes can
10147 * increase the actual pipe size due to the frame doubling and
10148 * insertion of additional space for blanks between the frame. This
10149 * is stored in the crtc timings. We use the requested mode to do this
10150 * computation to clearly distinguish it from the adjusted mode, which
10151 * can be changed by the connectors in the below retry loop.
10152 */
10153 drm_crtc_get_hv_timing(&pipe_config->base.mode,
10154 &pipe_config->pipe_src_w,
10155 &pipe_config->pipe_src_h);
10156
10157 encoder_retry:
10158 /* Ensure the port clock defaults are reset when retrying. */
10159 pipe_config->port_clock = 0;
10160 pipe_config->pixel_multiplier = 1;
10161
10162 /* Fill in default crtc timings, allow encoders to overwrite them. */
10163 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10164 CRTC_STEREO_DOUBLE);
10165
10166 /* Pass our mode to the connectors and the CRTC to give them a chance to
10167 * adjust it according to limitations or connector properties, and also
10168 * a chance to reject the mode entirely.
10169 */
10170 for_each_intel_encoder(dev, encoder) {
10171
10172 if (&encoder->new_crtc->base != crtc)
10173 continue;
10174
10175 if (!(encoder->compute_config(encoder, pipe_config))) {
10176 DRM_DEBUG_KMS("Encoder config failure\n");
10177 goto fail;
10178 }
10179 }
10180
10181 /* Set default port clock if not overwritten by the encoder. Needs to be
10182 * done afterwards in case the encoder adjusts the mode. */
10183 if (!pipe_config->port_clock)
10184 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10185 * pipe_config->pixel_multiplier;
10186
10187 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10188 if (ret < 0) {
10189 DRM_DEBUG_KMS("CRTC fixup failed\n");
10190 goto fail;
10191 }
10192
10193 if (ret == RETRY) {
10194 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10195 ret = -EINVAL;
10196 goto fail;
10197 }
10198
10199 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10200 retry = false;
10201 goto encoder_retry;
10202 }
10203
10204 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10205 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10206 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10207
10208 return pipe_config;
10209 fail:
10210 kfree(pipe_config);
10211 return ERR_PTR(ret);
10212 }
10213
10214 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10215 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10216 static void
10217 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10218 unsigned *prepare_pipes, unsigned *disable_pipes)
10219 {
10220 struct intel_crtc *intel_crtc;
10221 struct drm_device *dev = crtc->dev;
10222 struct intel_encoder *encoder;
10223 struct intel_connector *connector;
10224 struct drm_crtc *tmp_crtc;
10225
10226 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10227
10228 /* Check which crtcs have changed outputs connected to them, these need
10229 * to be part of the prepare_pipes mask. We don't (yet) support global
10230 * modeset across multiple crtcs, so modeset_pipes will only have one
10231 * bit set at most. */
10232 list_for_each_entry(connector, &dev->mode_config.connector_list,
10233 base.head) {
10234 if (connector->base.encoder == &connector->new_encoder->base)
10235 continue;
10236
10237 if (connector->base.encoder) {
10238 tmp_crtc = connector->base.encoder->crtc;
10239
10240 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10241 }
10242
10243 if (connector->new_encoder)
10244 *prepare_pipes |=
10245 1 << connector->new_encoder->new_crtc->pipe;
10246 }
10247
10248 for_each_intel_encoder(dev, encoder) {
10249 if (encoder->base.crtc == &encoder->new_crtc->base)
10250 continue;
10251
10252 if (encoder->base.crtc) {
10253 tmp_crtc = encoder->base.crtc;
10254
10255 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10256 }
10257
10258 if (encoder->new_crtc)
10259 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10260 }
10261
10262 /* Check for pipes that will be enabled/disabled ... */
10263 for_each_intel_crtc(dev, intel_crtc) {
10264 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10265 continue;
10266
10267 if (!intel_crtc->new_enabled)
10268 *disable_pipes |= 1 << intel_crtc->pipe;
10269 else
10270 *prepare_pipes |= 1 << intel_crtc->pipe;
10271 }
10272
10273
10274 /* set_mode is also used to update properties on life display pipes. */
10275 intel_crtc = to_intel_crtc(crtc);
10276 if (intel_crtc->new_enabled)
10277 *prepare_pipes |= 1 << intel_crtc->pipe;
10278
10279 /*
10280 * For simplicity do a full modeset on any pipe where the output routing
10281 * changed. We could be more clever, but that would require us to be
10282 * more careful with calling the relevant encoder->mode_set functions.
10283 */
10284 if (*prepare_pipes)
10285 *modeset_pipes = *prepare_pipes;
10286
10287 /* ... and mask these out. */
10288 *modeset_pipes &= ~(*disable_pipes);
10289 *prepare_pipes &= ~(*disable_pipes);
10290
10291 /*
10292 * HACK: We don't (yet) fully support global modesets. intel_set_config
10293 * obies this rule, but the modeset restore mode of
10294 * intel_modeset_setup_hw_state does not.
10295 */
10296 *modeset_pipes &= 1 << intel_crtc->pipe;
10297 *prepare_pipes &= 1 << intel_crtc->pipe;
10298
10299 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10300 *modeset_pipes, *prepare_pipes, *disable_pipes);
10301 }
10302
10303 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10304 {
10305 struct drm_encoder *encoder;
10306 struct drm_device *dev = crtc->dev;
10307
10308 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10309 if (encoder->crtc == crtc)
10310 return true;
10311
10312 return false;
10313 }
10314
10315 static void
10316 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10317 {
10318 struct drm_i915_private *dev_priv = dev->dev_private;
10319 struct intel_encoder *intel_encoder;
10320 struct intel_crtc *intel_crtc;
10321 struct drm_connector *connector;
10322
10323 intel_shared_dpll_commit(dev_priv);
10324
10325 for_each_intel_encoder(dev, intel_encoder) {
10326 if (!intel_encoder->base.crtc)
10327 continue;
10328
10329 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10330
10331 if (prepare_pipes & (1 << intel_crtc->pipe))
10332 intel_encoder->connectors_active = false;
10333 }
10334
10335 intel_modeset_commit_output_state(dev);
10336
10337 /* Double check state. */
10338 for_each_intel_crtc(dev, intel_crtc) {
10339 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10340 WARN_ON(intel_crtc->new_config &&
10341 intel_crtc->new_config != intel_crtc->config);
10342 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10343 }
10344
10345 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10346 if (!connector->encoder || !connector->encoder->crtc)
10347 continue;
10348
10349 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10350
10351 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10352 struct drm_property *dpms_property =
10353 dev->mode_config.dpms_property;
10354
10355 connector->dpms = DRM_MODE_DPMS_ON;
10356 drm_object_property_set_value(&connector->base,
10357 dpms_property,
10358 DRM_MODE_DPMS_ON);
10359
10360 intel_encoder = to_intel_encoder(connector->encoder);
10361 intel_encoder->connectors_active = true;
10362 }
10363 }
10364
10365 }
10366
10367 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10368 {
10369 int diff;
10370
10371 if (clock1 == clock2)
10372 return true;
10373
10374 if (!clock1 || !clock2)
10375 return false;
10376
10377 diff = abs(clock1 - clock2);
10378
10379 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10380 return true;
10381
10382 return false;
10383 }
10384
10385 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10386 list_for_each_entry((intel_crtc), \
10387 &(dev)->mode_config.crtc_list, \
10388 base.head) \
10389 if (mask & (1 <<(intel_crtc)->pipe))
10390
10391 static bool
10392 intel_pipe_config_compare(struct drm_device *dev,
10393 struct intel_crtc_state *current_config,
10394 struct intel_crtc_state *pipe_config)
10395 {
10396 #define PIPE_CONF_CHECK_X(name) \
10397 if (current_config->name != pipe_config->name) { \
10398 DRM_ERROR("mismatch in " #name " " \
10399 "(expected 0x%08x, found 0x%08x)\n", \
10400 current_config->name, \
10401 pipe_config->name); \
10402 return false; \
10403 }
10404
10405 #define PIPE_CONF_CHECK_I(name) \
10406 if (current_config->name != pipe_config->name) { \
10407 DRM_ERROR("mismatch in " #name " " \
10408 "(expected %i, found %i)\n", \
10409 current_config->name, \
10410 pipe_config->name); \
10411 return false; \
10412 }
10413
10414 /* This is required for BDW+ where there is only one set of registers for
10415 * switching between high and low RR.
10416 * This macro can be used whenever a comparison has to be made between one
10417 * hw state and multiple sw state variables.
10418 */
10419 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10420 if ((current_config->name != pipe_config->name) && \
10421 (current_config->alt_name != pipe_config->name)) { \
10422 DRM_ERROR("mismatch in " #name " " \
10423 "(expected %i or %i, found %i)\n", \
10424 current_config->name, \
10425 current_config->alt_name, \
10426 pipe_config->name); \
10427 return false; \
10428 }
10429
10430 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10431 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10432 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10433 "(expected %i, found %i)\n", \
10434 current_config->name & (mask), \
10435 pipe_config->name & (mask)); \
10436 return false; \
10437 }
10438
10439 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10440 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10441 DRM_ERROR("mismatch in " #name " " \
10442 "(expected %i, found %i)\n", \
10443 current_config->name, \
10444 pipe_config->name); \
10445 return false; \
10446 }
10447
10448 #define PIPE_CONF_QUIRK(quirk) \
10449 ((current_config->quirks | pipe_config->quirks) & (quirk))
10450
10451 PIPE_CONF_CHECK_I(cpu_transcoder);
10452
10453 PIPE_CONF_CHECK_I(has_pch_encoder);
10454 PIPE_CONF_CHECK_I(fdi_lanes);
10455 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10456 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10457 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10458 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10459 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10460
10461 PIPE_CONF_CHECK_I(has_dp_encoder);
10462
10463 if (INTEL_INFO(dev)->gen < 8) {
10464 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10465 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10466 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10467 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10468 PIPE_CONF_CHECK_I(dp_m_n.tu);
10469
10470 if (current_config->has_drrs) {
10471 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10472 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10473 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10474 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10475 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10476 }
10477 } else {
10478 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10479 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10480 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10481 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10482 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10483 }
10484
10485 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
10486 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
10487 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
10488 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
10489 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
10490 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
10491
10492 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
10493 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
10494 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
10495 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
10496 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
10497 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
10498
10499 PIPE_CONF_CHECK_I(pixel_multiplier);
10500 PIPE_CONF_CHECK_I(has_hdmi_sink);
10501 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10502 IS_VALLEYVIEW(dev))
10503 PIPE_CONF_CHECK_I(limited_color_range);
10504 PIPE_CONF_CHECK_I(has_infoframe);
10505
10506 PIPE_CONF_CHECK_I(has_audio);
10507
10508 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10509 DRM_MODE_FLAG_INTERLACE);
10510
10511 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10512 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10513 DRM_MODE_FLAG_PHSYNC);
10514 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10515 DRM_MODE_FLAG_NHSYNC);
10516 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10517 DRM_MODE_FLAG_PVSYNC);
10518 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10519 DRM_MODE_FLAG_NVSYNC);
10520 }
10521
10522 PIPE_CONF_CHECK_I(pipe_src_w);
10523 PIPE_CONF_CHECK_I(pipe_src_h);
10524
10525 /*
10526 * FIXME: BIOS likes to set up a cloned config with lvds+external
10527 * screen. Since we don't yet re-compute the pipe config when moving
10528 * just the lvds port away to another pipe the sw tracking won't match.
10529 *
10530 * Proper atomic modesets with recomputed global state will fix this.
10531 * Until then just don't check gmch state for inherited modes.
10532 */
10533 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10534 PIPE_CONF_CHECK_I(gmch_pfit.control);
10535 /* pfit ratios are autocomputed by the hw on gen4+ */
10536 if (INTEL_INFO(dev)->gen < 4)
10537 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10538 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10539 }
10540
10541 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10542 if (current_config->pch_pfit.enabled) {
10543 PIPE_CONF_CHECK_I(pch_pfit.pos);
10544 PIPE_CONF_CHECK_I(pch_pfit.size);
10545 }
10546
10547 /* BDW+ don't expose a synchronous way to read the state */
10548 if (IS_HASWELL(dev))
10549 PIPE_CONF_CHECK_I(ips_enabled);
10550
10551 PIPE_CONF_CHECK_I(double_wide);
10552
10553 PIPE_CONF_CHECK_X(ddi_pll_sel);
10554
10555 PIPE_CONF_CHECK_I(shared_dpll);
10556 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10557 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10558 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10559 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10560 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10561 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
10562 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
10563 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
10564
10565 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10566 PIPE_CONF_CHECK_I(pipe_bpp);
10567
10568 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
10569 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10570
10571 #undef PIPE_CONF_CHECK_X
10572 #undef PIPE_CONF_CHECK_I
10573 #undef PIPE_CONF_CHECK_I_ALT
10574 #undef PIPE_CONF_CHECK_FLAGS
10575 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10576 #undef PIPE_CONF_QUIRK
10577
10578 return true;
10579 }
10580
10581 static void check_wm_state(struct drm_device *dev)
10582 {
10583 struct drm_i915_private *dev_priv = dev->dev_private;
10584 struct skl_ddb_allocation hw_ddb, *sw_ddb;
10585 struct intel_crtc *intel_crtc;
10586 int plane;
10587
10588 if (INTEL_INFO(dev)->gen < 9)
10589 return;
10590
10591 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
10592 sw_ddb = &dev_priv->wm.skl_hw.ddb;
10593
10594 for_each_intel_crtc(dev, intel_crtc) {
10595 struct skl_ddb_entry *hw_entry, *sw_entry;
10596 const enum pipe pipe = intel_crtc->pipe;
10597
10598 if (!intel_crtc->active)
10599 continue;
10600
10601 /* planes */
10602 for_each_plane(pipe, plane) {
10603 hw_entry = &hw_ddb.plane[pipe][plane];
10604 sw_entry = &sw_ddb->plane[pipe][plane];
10605
10606 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10607 continue;
10608
10609 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10610 "(expected (%u,%u), found (%u,%u))\n",
10611 pipe_name(pipe), plane + 1,
10612 sw_entry->start, sw_entry->end,
10613 hw_entry->start, hw_entry->end);
10614 }
10615
10616 /* cursor */
10617 hw_entry = &hw_ddb.cursor[pipe];
10618 sw_entry = &sw_ddb->cursor[pipe];
10619
10620 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10621 continue;
10622
10623 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10624 "(expected (%u,%u), found (%u,%u))\n",
10625 pipe_name(pipe),
10626 sw_entry->start, sw_entry->end,
10627 hw_entry->start, hw_entry->end);
10628 }
10629 }
10630
10631 static void
10632 check_connector_state(struct drm_device *dev)
10633 {
10634 struct intel_connector *connector;
10635
10636 list_for_each_entry(connector, &dev->mode_config.connector_list,
10637 base.head) {
10638 /* This also checks the encoder/connector hw state with the
10639 * ->get_hw_state callbacks. */
10640 intel_connector_check_state(connector);
10641
10642 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
10643 "connector's staged encoder doesn't match current encoder\n");
10644 }
10645 }
10646
10647 static void
10648 check_encoder_state(struct drm_device *dev)
10649 {
10650 struct intel_encoder *encoder;
10651 struct intel_connector *connector;
10652
10653 for_each_intel_encoder(dev, encoder) {
10654 bool enabled = false;
10655 bool active = false;
10656 enum pipe pipe, tracked_pipe;
10657
10658 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10659 encoder->base.base.id,
10660 encoder->base.name);
10661
10662 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
10663 "encoder's stage crtc doesn't match current crtc\n");
10664 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
10665 "encoder's active_connectors set, but no crtc\n");
10666
10667 list_for_each_entry(connector, &dev->mode_config.connector_list,
10668 base.head) {
10669 if (connector->base.encoder != &encoder->base)
10670 continue;
10671 enabled = true;
10672 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10673 active = true;
10674 }
10675 /*
10676 * for MST connectors if we unplug the connector is gone
10677 * away but the encoder is still connected to a crtc
10678 * until a modeset happens in response to the hotplug.
10679 */
10680 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10681 continue;
10682
10683 I915_STATE_WARN(!!encoder->base.crtc != enabled,
10684 "encoder's enabled state mismatch "
10685 "(expected %i, found %i)\n",
10686 !!encoder->base.crtc, enabled);
10687 I915_STATE_WARN(active && !encoder->base.crtc,
10688 "active encoder with no crtc\n");
10689
10690 I915_STATE_WARN(encoder->connectors_active != active,
10691 "encoder's computed active state doesn't match tracked active state "
10692 "(expected %i, found %i)\n", active, encoder->connectors_active);
10693
10694 active = encoder->get_hw_state(encoder, &pipe);
10695 I915_STATE_WARN(active != encoder->connectors_active,
10696 "encoder's hw state doesn't match sw tracking "
10697 "(expected %i, found %i)\n",
10698 encoder->connectors_active, active);
10699
10700 if (!encoder->base.crtc)
10701 continue;
10702
10703 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10704 I915_STATE_WARN(active && pipe != tracked_pipe,
10705 "active encoder's pipe doesn't match"
10706 "(expected %i, found %i)\n",
10707 tracked_pipe, pipe);
10708
10709 }
10710 }
10711
10712 static void
10713 check_crtc_state(struct drm_device *dev)
10714 {
10715 struct drm_i915_private *dev_priv = dev->dev_private;
10716 struct intel_crtc *crtc;
10717 struct intel_encoder *encoder;
10718 struct intel_crtc_state pipe_config;
10719
10720 for_each_intel_crtc(dev, crtc) {
10721 bool enabled = false;
10722 bool active = false;
10723
10724 memset(&pipe_config, 0, sizeof(pipe_config));
10725
10726 DRM_DEBUG_KMS("[CRTC:%d]\n",
10727 crtc->base.base.id);
10728
10729 I915_STATE_WARN(crtc->active && !crtc->base.enabled,
10730 "active crtc, but not enabled in sw tracking\n");
10731
10732 for_each_intel_encoder(dev, encoder) {
10733 if (encoder->base.crtc != &crtc->base)
10734 continue;
10735 enabled = true;
10736 if (encoder->connectors_active)
10737 active = true;
10738 }
10739
10740 I915_STATE_WARN(active != crtc->active,
10741 "crtc's computed active state doesn't match tracked active state "
10742 "(expected %i, found %i)\n", active, crtc->active);
10743 I915_STATE_WARN(enabled != crtc->base.enabled,
10744 "crtc's computed enabled state doesn't match tracked enabled state "
10745 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10746
10747 active = dev_priv->display.get_pipe_config(crtc,
10748 &pipe_config);
10749
10750 /* hw state is inconsistent with the pipe quirk */
10751 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10752 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10753 active = crtc->active;
10754
10755 for_each_intel_encoder(dev, encoder) {
10756 enum pipe pipe;
10757 if (encoder->base.crtc != &crtc->base)
10758 continue;
10759 if (encoder->get_hw_state(encoder, &pipe))
10760 encoder->get_config(encoder, &pipe_config);
10761 }
10762
10763 I915_STATE_WARN(crtc->active != active,
10764 "crtc active state doesn't match with hw state "
10765 "(expected %i, found %i)\n", crtc->active, active);
10766
10767 if (active &&
10768 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
10769 I915_STATE_WARN(1, "pipe state doesn't match!\n");
10770 intel_dump_pipe_config(crtc, &pipe_config,
10771 "[hw state]");
10772 intel_dump_pipe_config(crtc, crtc->config,
10773 "[sw state]");
10774 }
10775 }
10776 }
10777
10778 static void
10779 check_shared_dpll_state(struct drm_device *dev)
10780 {
10781 struct drm_i915_private *dev_priv = dev->dev_private;
10782 struct intel_crtc *crtc;
10783 struct intel_dpll_hw_state dpll_hw_state;
10784 int i;
10785
10786 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10787 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10788 int enabled_crtcs = 0, active_crtcs = 0;
10789 bool active;
10790
10791 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10792
10793 DRM_DEBUG_KMS("%s\n", pll->name);
10794
10795 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10796
10797 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
10798 "more active pll users than references: %i vs %i\n",
10799 pll->active, hweight32(pll->config.crtc_mask));
10800 I915_STATE_WARN(pll->active && !pll->on,
10801 "pll in active use but not on in sw tracking\n");
10802 I915_STATE_WARN(pll->on && !pll->active,
10803 "pll in on but not on in use in sw tracking\n");
10804 I915_STATE_WARN(pll->on != active,
10805 "pll on state mismatch (expected %i, found %i)\n",
10806 pll->on, active);
10807
10808 for_each_intel_crtc(dev, crtc) {
10809 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10810 enabled_crtcs++;
10811 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10812 active_crtcs++;
10813 }
10814 I915_STATE_WARN(pll->active != active_crtcs,
10815 "pll active crtcs mismatch (expected %i, found %i)\n",
10816 pll->active, active_crtcs);
10817 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
10818 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10819 hweight32(pll->config.crtc_mask), enabled_crtcs);
10820
10821 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
10822 sizeof(dpll_hw_state)),
10823 "pll hw state mismatch\n");
10824 }
10825 }
10826
10827 void
10828 intel_modeset_check_state(struct drm_device *dev)
10829 {
10830 check_wm_state(dev);
10831 check_connector_state(dev);
10832 check_encoder_state(dev);
10833 check_crtc_state(dev);
10834 check_shared_dpll_state(dev);
10835 }
10836
10837 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
10838 int dotclock)
10839 {
10840 /*
10841 * FDI already provided one idea for the dotclock.
10842 * Yell if the encoder disagrees.
10843 */
10844 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
10845 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10846 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
10847 }
10848
10849 static void update_scanline_offset(struct intel_crtc *crtc)
10850 {
10851 struct drm_device *dev = crtc->base.dev;
10852
10853 /*
10854 * The scanline counter increments at the leading edge of hsync.
10855 *
10856 * On most platforms it starts counting from vtotal-1 on the
10857 * first active line. That means the scanline counter value is
10858 * always one less than what we would expect. Ie. just after
10859 * start of vblank, which also occurs at start of hsync (on the
10860 * last active line), the scanline counter will read vblank_start-1.
10861 *
10862 * On gen2 the scanline counter starts counting from 1 instead
10863 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10864 * to keep the value positive), instead of adding one.
10865 *
10866 * On HSW+ the behaviour of the scanline counter depends on the output
10867 * type. For DP ports it behaves like most other platforms, but on HDMI
10868 * there's an extra 1 line difference. So we need to add two instead of
10869 * one to the value.
10870 */
10871 if (IS_GEN2(dev)) {
10872 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
10873 int vtotal;
10874
10875 vtotal = mode->crtc_vtotal;
10876 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10877 vtotal /= 2;
10878
10879 crtc->scanline_offset = vtotal - 1;
10880 } else if (HAS_DDI(dev) &&
10881 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
10882 crtc->scanline_offset = 2;
10883 } else
10884 crtc->scanline_offset = 1;
10885 }
10886
10887 static struct intel_crtc_state *
10888 intel_modeset_compute_config(struct drm_crtc *crtc,
10889 struct drm_display_mode *mode,
10890 struct drm_framebuffer *fb,
10891 unsigned *modeset_pipes,
10892 unsigned *prepare_pipes,
10893 unsigned *disable_pipes)
10894 {
10895 struct intel_crtc_state *pipe_config = NULL;
10896
10897 intel_modeset_affected_pipes(crtc, modeset_pipes,
10898 prepare_pipes, disable_pipes);
10899
10900 if ((*modeset_pipes) == 0)
10901 goto out;
10902
10903 /*
10904 * Note this needs changes when we start tracking multiple modes
10905 * and crtcs. At that point we'll need to compute the whole config
10906 * (i.e. one pipe_config for each crtc) rather than just the one
10907 * for this crtc.
10908 */
10909 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10910 if (IS_ERR(pipe_config)) {
10911 goto out;
10912 }
10913 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10914 "[modeset]");
10915
10916 out:
10917 return pipe_config;
10918 }
10919
10920 static int __intel_set_mode(struct drm_crtc *crtc,
10921 struct drm_display_mode *mode,
10922 int x, int y, struct drm_framebuffer *fb,
10923 struct intel_crtc_state *pipe_config,
10924 unsigned modeset_pipes,
10925 unsigned prepare_pipes,
10926 unsigned disable_pipes)
10927 {
10928 struct drm_device *dev = crtc->dev;
10929 struct drm_i915_private *dev_priv = dev->dev_private;
10930 struct drm_display_mode *saved_mode;
10931 struct intel_crtc *intel_crtc;
10932 int ret = 0;
10933
10934 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10935 if (!saved_mode)
10936 return -ENOMEM;
10937
10938 *saved_mode = crtc->mode;
10939
10940 if (modeset_pipes)
10941 to_intel_crtc(crtc)->new_config = pipe_config;
10942
10943 /*
10944 * See if the config requires any additional preparation, e.g.
10945 * to adjust global state with pipes off. We need to do this
10946 * here so we can get the modeset_pipe updated config for the new
10947 * mode set on this crtc. For other crtcs we need to use the
10948 * adjusted_mode bits in the crtc directly.
10949 */
10950 if (IS_VALLEYVIEW(dev)) {
10951 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10952
10953 /* may have added more to prepare_pipes than we should */
10954 prepare_pipes &= ~disable_pipes;
10955 }
10956
10957 if (dev_priv->display.crtc_compute_clock) {
10958 unsigned clear_pipes = modeset_pipes | disable_pipes;
10959
10960 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
10961 if (ret)
10962 goto done;
10963
10964 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10965 struct intel_crtc_state *state = intel_crtc->new_config;
10966 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
10967 state);
10968 if (ret) {
10969 intel_shared_dpll_abort_config(dev_priv);
10970 goto done;
10971 }
10972 }
10973 }
10974
10975 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10976 intel_crtc_disable(&intel_crtc->base);
10977
10978 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10979 if (intel_crtc->base.enabled)
10980 dev_priv->display.crtc_disable(&intel_crtc->base);
10981 }
10982
10983 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10984 * to set it here already despite that we pass it down the callchain.
10985 *
10986 * Note we'll need to fix this up when we start tracking multiple
10987 * pipes; here we assume a single modeset_pipe and only track the
10988 * single crtc and mode.
10989 */
10990 if (modeset_pipes) {
10991 crtc->mode = *mode;
10992 /* mode_set/enable/disable functions rely on a correct pipe
10993 * config. */
10994 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
10995
10996 /*
10997 * Calculate and store various constants which
10998 * are later needed by vblank and swap-completion
10999 * timestamping. They are derived from true hwmode.
11000 */
11001 drm_calc_timestamping_constants(crtc,
11002 &pipe_config->base.adjusted_mode);
11003 }
11004
11005 /* Only after disabling all output pipelines that will be changed can we
11006 * update the the output configuration. */
11007 intel_modeset_update_state(dev, prepare_pipes);
11008
11009 modeset_update_crtc_power_domains(dev);
11010
11011 /* Set up the DPLL and any encoders state that needs to adjust or depend
11012 * on the DPLL.
11013 */
11014 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11015 struct drm_plane *primary = intel_crtc->base.primary;
11016 int vdisplay, hdisplay;
11017
11018 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11019 ret = primary->funcs->update_plane(primary, &intel_crtc->base,
11020 fb, 0, 0,
11021 hdisplay, vdisplay,
11022 x << 16, y << 16,
11023 hdisplay << 16, vdisplay << 16);
11024 }
11025
11026 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11027 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11028 update_scanline_offset(intel_crtc);
11029
11030 dev_priv->display.crtc_enable(&intel_crtc->base);
11031 }
11032
11033 /* FIXME: add subpixel order */
11034 done:
11035 if (ret && crtc->enabled)
11036 crtc->mode = *saved_mode;
11037
11038 kfree(saved_mode);
11039 return ret;
11040 }
11041
11042 static int intel_set_mode_pipes(struct drm_crtc *crtc,
11043 struct drm_display_mode *mode,
11044 int x, int y, struct drm_framebuffer *fb,
11045 struct intel_crtc_state *pipe_config,
11046 unsigned modeset_pipes,
11047 unsigned prepare_pipes,
11048 unsigned disable_pipes)
11049 {
11050 int ret;
11051
11052 ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11053 prepare_pipes, disable_pipes);
11054
11055 if (ret == 0)
11056 intel_modeset_check_state(crtc->dev);
11057
11058 return ret;
11059 }
11060
11061 static int intel_set_mode(struct drm_crtc *crtc,
11062 struct drm_display_mode *mode,
11063 int x, int y, struct drm_framebuffer *fb)
11064 {
11065 struct intel_crtc_state *pipe_config;
11066 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11067
11068 pipe_config = intel_modeset_compute_config(crtc, mode, fb,
11069 &modeset_pipes,
11070 &prepare_pipes,
11071 &disable_pipes);
11072
11073 if (IS_ERR(pipe_config))
11074 return PTR_ERR(pipe_config);
11075
11076 return intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11077 modeset_pipes, prepare_pipes,
11078 disable_pipes);
11079 }
11080
11081 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11082 {
11083 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11084 }
11085
11086 #undef for_each_intel_crtc_masked
11087
11088 static void intel_set_config_free(struct intel_set_config *config)
11089 {
11090 if (!config)
11091 return;
11092
11093 kfree(config->save_connector_encoders);
11094 kfree(config->save_encoder_crtcs);
11095 kfree(config->save_crtc_enabled);
11096 kfree(config);
11097 }
11098
11099 static int intel_set_config_save_state(struct drm_device *dev,
11100 struct intel_set_config *config)
11101 {
11102 struct drm_crtc *crtc;
11103 struct drm_encoder *encoder;
11104 struct drm_connector *connector;
11105 int count;
11106
11107 config->save_crtc_enabled =
11108 kcalloc(dev->mode_config.num_crtc,
11109 sizeof(bool), GFP_KERNEL);
11110 if (!config->save_crtc_enabled)
11111 return -ENOMEM;
11112
11113 config->save_encoder_crtcs =
11114 kcalloc(dev->mode_config.num_encoder,
11115 sizeof(struct drm_crtc *), GFP_KERNEL);
11116 if (!config->save_encoder_crtcs)
11117 return -ENOMEM;
11118
11119 config->save_connector_encoders =
11120 kcalloc(dev->mode_config.num_connector,
11121 sizeof(struct drm_encoder *), GFP_KERNEL);
11122 if (!config->save_connector_encoders)
11123 return -ENOMEM;
11124
11125 /* Copy data. Note that driver private data is not affected.
11126 * Should anything bad happen only the expected state is
11127 * restored, not the drivers personal bookkeeping.
11128 */
11129 count = 0;
11130 for_each_crtc(dev, crtc) {
11131 config->save_crtc_enabled[count++] = crtc->enabled;
11132 }
11133
11134 count = 0;
11135 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11136 config->save_encoder_crtcs[count++] = encoder->crtc;
11137 }
11138
11139 count = 0;
11140 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11141 config->save_connector_encoders[count++] = connector->encoder;
11142 }
11143
11144 return 0;
11145 }
11146
11147 static void intel_set_config_restore_state(struct drm_device *dev,
11148 struct intel_set_config *config)
11149 {
11150 struct intel_crtc *crtc;
11151 struct intel_encoder *encoder;
11152 struct intel_connector *connector;
11153 int count;
11154
11155 count = 0;
11156 for_each_intel_crtc(dev, crtc) {
11157 crtc->new_enabled = config->save_crtc_enabled[count++];
11158
11159 if (crtc->new_enabled)
11160 crtc->new_config = crtc->config;
11161 else
11162 crtc->new_config = NULL;
11163 }
11164
11165 count = 0;
11166 for_each_intel_encoder(dev, encoder) {
11167 encoder->new_crtc =
11168 to_intel_crtc(config->save_encoder_crtcs[count++]);
11169 }
11170
11171 count = 0;
11172 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11173 connector->new_encoder =
11174 to_intel_encoder(config->save_connector_encoders[count++]);
11175 }
11176 }
11177
11178 static bool
11179 is_crtc_connector_off(struct drm_mode_set *set)
11180 {
11181 int i;
11182
11183 if (set->num_connectors == 0)
11184 return false;
11185
11186 if (WARN_ON(set->connectors == NULL))
11187 return false;
11188
11189 for (i = 0; i < set->num_connectors; i++)
11190 if (set->connectors[i]->encoder &&
11191 set->connectors[i]->encoder->crtc == set->crtc &&
11192 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11193 return true;
11194
11195 return false;
11196 }
11197
11198 static void
11199 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11200 struct intel_set_config *config)
11201 {
11202
11203 /* We should be able to check here if the fb has the same properties
11204 * and then just flip_or_move it */
11205 if (is_crtc_connector_off(set)) {
11206 config->mode_changed = true;
11207 } else if (set->crtc->primary->fb != set->fb) {
11208 /*
11209 * If we have no fb, we can only flip as long as the crtc is
11210 * active, otherwise we need a full mode set. The crtc may
11211 * be active if we've only disabled the primary plane, or
11212 * in fastboot situations.
11213 */
11214 if (set->crtc->primary->fb == NULL) {
11215 struct intel_crtc *intel_crtc =
11216 to_intel_crtc(set->crtc);
11217
11218 if (intel_crtc->active) {
11219 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11220 config->fb_changed = true;
11221 } else {
11222 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11223 config->mode_changed = true;
11224 }
11225 } else if (set->fb == NULL) {
11226 config->mode_changed = true;
11227 } else if (set->fb->pixel_format !=
11228 set->crtc->primary->fb->pixel_format) {
11229 config->mode_changed = true;
11230 } else {
11231 config->fb_changed = true;
11232 }
11233 }
11234
11235 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11236 config->fb_changed = true;
11237
11238 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11239 DRM_DEBUG_KMS("modes are different, full mode set\n");
11240 drm_mode_debug_printmodeline(&set->crtc->mode);
11241 drm_mode_debug_printmodeline(set->mode);
11242 config->mode_changed = true;
11243 }
11244
11245 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11246 set->crtc->base.id, config->mode_changed, config->fb_changed);
11247 }
11248
11249 static int
11250 intel_modeset_stage_output_state(struct drm_device *dev,
11251 struct drm_mode_set *set,
11252 struct intel_set_config *config)
11253 {
11254 struct intel_connector *connector;
11255 struct intel_encoder *encoder;
11256 struct intel_crtc *crtc;
11257 int ro;
11258
11259 /* The upper layers ensure that we either disable a crtc or have a list
11260 * of connectors. For paranoia, double-check this. */
11261 WARN_ON(!set->fb && (set->num_connectors != 0));
11262 WARN_ON(set->fb && (set->num_connectors == 0));
11263
11264 list_for_each_entry(connector, &dev->mode_config.connector_list,
11265 base.head) {
11266 /* Otherwise traverse passed in connector list and get encoders
11267 * for them. */
11268 for (ro = 0; ro < set->num_connectors; ro++) {
11269 if (set->connectors[ro] == &connector->base) {
11270 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11271 break;
11272 }
11273 }
11274
11275 /* If we disable the crtc, disable all its connectors. Also, if
11276 * the connector is on the changing crtc but not on the new
11277 * connector list, disable it. */
11278 if ((!set->fb || ro == set->num_connectors) &&
11279 connector->base.encoder &&
11280 connector->base.encoder->crtc == set->crtc) {
11281 connector->new_encoder = NULL;
11282
11283 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11284 connector->base.base.id,
11285 connector->base.name);
11286 }
11287
11288
11289 if (&connector->new_encoder->base != connector->base.encoder) {
11290 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11291 config->mode_changed = true;
11292 }
11293 }
11294 /* connector->new_encoder is now updated for all connectors. */
11295
11296 /* Update crtc of enabled connectors. */
11297 list_for_each_entry(connector, &dev->mode_config.connector_list,
11298 base.head) {
11299 struct drm_crtc *new_crtc;
11300
11301 if (!connector->new_encoder)
11302 continue;
11303
11304 new_crtc = connector->new_encoder->base.crtc;
11305
11306 for (ro = 0; ro < set->num_connectors; ro++) {
11307 if (set->connectors[ro] == &connector->base)
11308 new_crtc = set->crtc;
11309 }
11310
11311 /* Make sure the new CRTC will work with the encoder */
11312 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11313 new_crtc)) {
11314 return -EINVAL;
11315 }
11316 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11317
11318 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11319 connector->base.base.id,
11320 connector->base.name,
11321 new_crtc->base.id);
11322 }
11323
11324 /* Check for any encoders that needs to be disabled. */
11325 for_each_intel_encoder(dev, encoder) {
11326 int num_connectors = 0;
11327 list_for_each_entry(connector,
11328 &dev->mode_config.connector_list,
11329 base.head) {
11330 if (connector->new_encoder == encoder) {
11331 WARN_ON(!connector->new_encoder->new_crtc);
11332 num_connectors++;
11333 }
11334 }
11335
11336 if (num_connectors == 0)
11337 encoder->new_crtc = NULL;
11338 else if (num_connectors > 1)
11339 return -EINVAL;
11340
11341 /* Only now check for crtc changes so we don't miss encoders
11342 * that will be disabled. */
11343 if (&encoder->new_crtc->base != encoder->base.crtc) {
11344 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11345 config->mode_changed = true;
11346 }
11347 }
11348 /* Now we've also updated encoder->new_crtc for all encoders. */
11349 list_for_each_entry(connector, &dev->mode_config.connector_list,
11350 base.head) {
11351 if (connector->new_encoder)
11352 if (connector->new_encoder != connector->encoder)
11353 connector->encoder = connector->new_encoder;
11354 }
11355 for_each_intel_crtc(dev, crtc) {
11356 crtc->new_enabled = false;
11357
11358 for_each_intel_encoder(dev, encoder) {
11359 if (encoder->new_crtc == crtc) {
11360 crtc->new_enabled = true;
11361 break;
11362 }
11363 }
11364
11365 if (crtc->new_enabled != crtc->base.enabled) {
11366 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11367 crtc->new_enabled ? "en" : "dis");
11368 config->mode_changed = true;
11369 }
11370
11371 if (crtc->new_enabled)
11372 crtc->new_config = crtc->config;
11373 else
11374 crtc->new_config = NULL;
11375 }
11376
11377 return 0;
11378 }
11379
11380 static void disable_crtc_nofb(struct intel_crtc *crtc)
11381 {
11382 struct drm_device *dev = crtc->base.dev;
11383 struct intel_encoder *encoder;
11384 struct intel_connector *connector;
11385
11386 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11387 pipe_name(crtc->pipe));
11388
11389 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11390 if (connector->new_encoder &&
11391 connector->new_encoder->new_crtc == crtc)
11392 connector->new_encoder = NULL;
11393 }
11394
11395 for_each_intel_encoder(dev, encoder) {
11396 if (encoder->new_crtc == crtc)
11397 encoder->new_crtc = NULL;
11398 }
11399
11400 crtc->new_enabled = false;
11401 crtc->new_config = NULL;
11402 }
11403
11404 static int intel_crtc_set_config(struct drm_mode_set *set)
11405 {
11406 struct drm_device *dev;
11407 struct drm_mode_set save_set;
11408 struct intel_set_config *config;
11409 struct intel_crtc_state *pipe_config;
11410 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11411 int ret;
11412
11413 BUG_ON(!set);
11414 BUG_ON(!set->crtc);
11415 BUG_ON(!set->crtc->helper_private);
11416
11417 /* Enforce sane interface api - has been abused by the fb helper. */
11418 BUG_ON(!set->mode && set->fb);
11419 BUG_ON(set->fb && set->num_connectors == 0);
11420
11421 if (set->fb) {
11422 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11423 set->crtc->base.id, set->fb->base.id,
11424 (int)set->num_connectors, set->x, set->y);
11425 } else {
11426 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11427 }
11428
11429 dev = set->crtc->dev;
11430
11431 ret = -ENOMEM;
11432 config = kzalloc(sizeof(*config), GFP_KERNEL);
11433 if (!config)
11434 goto out_config;
11435
11436 ret = intel_set_config_save_state(dev, config);
11437 if (ret)
11438 goto out_config;
11439
11440 save_set.crtc = set->crtc;
11441 save_set.mode = &set->crtc->mode;
11442 save_set.x = set->crtc->x;
11443 save_set.y = set->crtc->y;
11444 save_set.fb = set->crtc->primary->fb;
11445
11446 /* Compute whether we need a full modeset, only an fb base update or no
11447 * change at all. In the future we might also check whether only the
11448 * mode changed, e.g. for LVDS where we only change the panel fitter in
11449 * such cases. */
11450 intel_set_config_compute_mode_changes(set, config);
11451
11452 ret = intel_modeset_stage_output_state(dev, set, config);
11453 if (ret)
11454 goto fail;
11455
11456 pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
11457 set->fb,
11458 &modeset_pipes,
11459 &prepare_pipes,
11460 &disable_pipes);
11461 if (IS_ERR(pipe_config)) {
11462 ret = PTR_ERR(pipe_config);
11463 goto fail;
11464 } else if (pipe_config) {
11465 if (pipe_config->has_audio !=
11466 to_intel_crtc(set->crtc)->config->has_audio)
11467 config->mode_changed = true;
11468
11469 /*
11470 * Note we have an issue here with infoframes: current code
11471 * only updates them on the full mode set path per hw
11472 * requirements. So here we should be checking for any
11473 * required changes and forcing a mode set.
11474 */
11475 }
11476
11477 /* set_mode will free it in the mode_changed case */
11478 if (!config->mode_changed)
11479 kfree(pipe_config);
11480
11481 intel_update_pipe_size(to_intel_crtc(set->crtc));
11482
11483 if (config->mode_changed) {
11484 ret = intel_set_mode_pipes(set->crtc, set->mode,
11485 set->x, set->y, set->fb, pipe_config,
11486 modeset_pipes, prepare_pipes,
11487 disable_pipes);
11488 } else if (config->fb_changed) {
11489 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11490 struct drm_plane *primary = set->crtc->primary;
11491 int vdisplay, hdisplay;
11492
11493 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
11494 ret = primary->funcs->update_plane(primary, set->crtc, set->fb,
11495 0, 0, hdisplay, vdisplay,
11496 set->x << 16, set->y << 16,
11497 hdisplay << 16, vdisplay << 16);
11498
11499 /*
11500 * We need to make sure the primary plane is re-enabled if it
11501 * has previously been turned off.
11502 */
11503 if (!intel_crtc->primary_enabled && ret == 0) {
11504 WARN_ON(!intel_crtc->active);
11505 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11506 }
11507
11508 /*
11509 * In the fastboot case this may be our only check of the
11510 * state after boot. It would be better to only do it on
11511 * the first update, but we don't have a nice way of doing that
11512 * (and really, set_config isn't used much for high freq page
11513 * flipping, so increasing its cost here shouldn't be a big
11514 * deal).
11515 */
11516 if (i915.fastboot && ret == 0)
11517 intel_modeset_check_state(set->crtc->dev);
11518 }
11519
11520 if (ret) {
11521 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11522 set->crtc->base.id, ret);
11523 fail:
11524 intel_set_config_restore_state(dev, config);
11525
11526 /*
11527 * HACK: if the pipe was on, but we didn't have a framebuffer,
11528 * force the pipe off to avoid oopsing in the modeset code
11529 * due to fb==NULL. This should only happen during boot since
11530 * we don't yet reconstruct the FB from the hardware state.
11531 */
11532 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11533 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11534
11535 /* Try to restore the config */
11536 if (config->mode_changed &&
11537 intel_set_mode(save_set.crtc, save_set.mode,
11538 save_set.x, save_set.y, save_set.fb))
11539 DRM_ERROR("failed to restore config after modeset failure\n");
11540 }
11541
11542 out_config:
11543 intel_set_config_free(config);
11544 return ret;
11545 }
11546
11547 static const struct drm_crtc_funcs intel_crtc_funcs = {
11548 .gamma_set = intel_crtc_gamma_set,
11549 .set_config = intel_crtc_set_config,
11550 .destroy = intel_crtc_destroy,
11551 .page_flip = intel_crtc_page_flip,
11552 };
11553
11554 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11555 struct intel_shared_dpll *pll,
11556 struct intel_dpll_hw_state *hw_state)
11557 {
11558 uint32_t val;
11559
11560 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11561 return false;
11562
11563 val = I915_READ(PCH_DPLL(pll->id));
11564 hw_state->dpll = val;
11565 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11566 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11567
11568 return val & DPLL_VCO_ENABLE;
11569 }
11570
11571 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11572 struct intel_shared_dpll *pll)
11573 {
11574 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11575 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
11576 }
11577
11578 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11579 struct intel_shared_dpll *pll)
11580 {
11581 /* PCH refclock must be enabled first */
11582 ibx_assert_pch_refclk_enabled(dev_priv);
11583
11584 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11585
11586 /* Wait for the clocks to stabilize. */
11587 POSTING_READ(PCH_DPLL(pll->id));
11588 udelay(150);
11589
11590 /* The pixel multiplier can only be updated once the
11591 * DPLL is enabled and the clocks are stable.
11592 *
11593 * So write it again.
11594 */
11595 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11596 POSTING_READ(PCH_DPLL(pll->id));
11597 udelay(200);
11598 }
11599
11600 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11601 struct intel_shared_dpll *pll)
11602 {
11603 struct drm_device *dev = dev_priv->dev;
11604 struct intel_crtc *crtc;
11605
11606 /* Make sure no transcoder isn't still depending on us. */
11607 for_each_intel_crtc(dev, crtc) {
11608 if (intel_crtc_to_shared_dpll(crtc) == pll)
11609 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11610 }
11611
11612 I915_WRITE(PCH_DPLL(pll->id), 0);
11613 POSTING_READ(PCH_DPLL(pll->id));
11614 udelay(200);
11615 }
11616
11617 static char *ibx_pch_dpll_names[] = {
11618 "PCH DPLL A",
11619 "PCH DPLL B",
11620 };
11621
11622 static void ibx_pch_dpll_init(struct drm_device *dev)
11623 {
11624 struct drm_i915_private *dev_priv = dev->dev_private;
11625 int i;
11626
11627 dev_priv->num_shared_dpll = 2;
11628
11629 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11630 dev_priv->shared_dplls[i].id = i;
11631 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11632 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11633 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11634 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11635 dev_priv->shared_dplls[i].get_hw_state =
11636 ibx_pch_dpll_get_hw_state;
11637 }
11638 }
11639
11640 static void intel_shared_dpll_init(struct drm_device *dev)
11641 {
11642 struct drm_i915_private *dev_priv = dev->dev_private;
11643
11644 if (HAS_DDI(dev))
11645 intel_ddi_pll_init(dev);
11646 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11647 ibx_pch_dpll_init(dev);
11648 else
11649 dev_priv->num_shared_dpll = 0;
11650
11651 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11652 }
11653
11654 /**
11655 * intel_prepare_plane_fb - Prepare fb for usage on plane
11656 * @plane: drm plane to prepare for
11657 * @fb: framebuffer to prepare for presentation
11658 *
11659 * Prepares a framebuffer for usage on a display plane. Generally this
11660 * involves pinning the underlying object and updating the frontbuffer tracking
11661 * bits. Some older platforms need special physical address handling for
11662 * cursor planes.
11663 *
11664 * Returns 0 on success, negative error code on failure.
11665 */
11666 int
11667 intel_prepare_plane_fb(struct drm_plane *plane,
11668 struct drm_framebuffer *fb)
11669 {
11670 struct drm_device *dev = plane->dev;
11671 struct intel_plane *intel_plane = to_intel_plane(plane);
11672 enum pipe pipe = intel_plane->pipe;
11673 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11674 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11675 unsigned frontbuffer_bits = 0;
11676 int ret = 0;
11677
11678 if (!obj)
11679 return 0;
11680
11681 switch (plane->type) {
11682 case DRM_PLANE_TYPE_PRIMARY:
11683 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
11684 break;
11685 case DRM_PLANE_TYPE_CURSOR:
11686 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
11687 break;
11688 case DRM_PLANE_TYPE_OVERLAY:
11689 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
11690 break;
11691 }
11692
11693 mutex_lock(&dev->struct_mutex);
11694
11695 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
11696 INTEL_INFO(dev)->cursor_needs_physical) {
11697 int align = IS_I830(dev) ? 16 * 1024 : 256;
11698 ret = i915_gem_object_attach_phys(obj, align);
11699 if (ret)
11700 DRM_DEBUG_KMS("failed to attach phys object\n");
11701 } else {
11702 ret = intel_pin_and_fence_fb_obj(plane, fb, NULL);
11703 }
11704
11705 if (ret == 0)
11706 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
11707
11708 mutex_unlock(&dev->struct_mutex);
11709
11710 return ret;
11711 }
11712
11713 /**
11714 * intel_cleanup_plane_fb - Cleans up an fb after plane use
11715 * @plane: drm plane to clean up for
11716 * @fb: old framebuffer that was on plane
11717 *
11718 * Cleans up a framebuffer that has just been removed from a plane.
11719 */
11720 void
11721 intel_cleanup_plane_fb(struct drm_plane *plane,
11722 struct drm_framebuffer *fb)
11723 {
11724 struct drm_device *dev = plane->dev;
11725 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11726
11727 if (WARN_ON(!obj))
11728 return;
11729
11730 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
11731 !INTEL_INFO(dev)->cursor_needs_physical) {
11732 mutex_lock(&dev->struct_mutex);
11733 intel_unpin_fb_obj(obj);
11734 mutex_unlock(&dev->struct_mutex);
11735 }
11736 }
11737
11738 static int
11739 intel_check_primary_plane(struct drm_plane *plane,
11740 struct intel_plane_state *state)
11741 {
11742 struct drm_device *dev = plane->dev;
11743 struct drm_i915_private *dev_priv = dev->dev_private;
11744 struct drm_crtc *crtc = state->base.crtc;
11745 struct intel_crtc *intel_crtc;
11746 struct intel_plane *intel_plane = to_intel_plane(plane);
11747 struct drm_framebuffer *fb = state->base.fb;
11748 struct drm_rect *dest = &state->dst;
11749 struct drm_rect *src = &state->src;
11750 const struct drm_rect *clip = &state->clip;
11751 int ret;
11752
11753 crtc = crtc ? crtc : plane->crtc;
11754 intel_crtc = to_intel_crtc(crtc);
11755
11756 ret = drm_plane_helper_check_update(plane, crtc, fb,
11757 src, dest, clip,
11758 DRM_PLANE_HELPER_NO_SCALING,
11759 DRM_PLANE_HELPER_NO_SCALING,
11760 false, true, &state->visible);
11761 if (ret)
11762 return ret;
11763
11764 if (intel_crtc->active) {
11765 intel_crtc->atomic.wait_for_flips = true;
11766
11767 /*
11768 * FBC does not work on some platforms for rotated
11769 * planes, so disable it when rotation is not 0 and
11770 * update it when rotation is set back to 0.
11771 *
11772 * FIXME: This is redundant with the fbc update done in
11773 * the primary plane enable function except that that
11774 * one is done too late. We eventually need to unify
11775 * this.
11776 */
11777 if (intel_crtc->primary_enabled &&
11778 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11779 dev_priv->fbc.plane == intel_crtc->plane &&
11780 intel_plane->rotation != BIT(DRM_ROTATE_0)) {
11781 intel_crtc->atomic.disable_fbc = true;
11782 }
11783
11784 if (state->visible) {
11785 /*
11786 * BDW signals flip done immediately if the plane
11787 * is disabled, even if the plane enable is already
11788 * armed to occur at the next vblank :(
11789 */
11790 if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
11791 intel_crtc->atomic.wait_vblank = true;
11792 }
11793
11794 intel_crtc->atomic.fb_bits |=
11795 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
11796
11797 intel_crtc->atomic.update_fbc = true;
11798 }
11799
11800 return 0;
11801 }
11802
11803 static void
11804 intel_commit_primary_plane(struct drm_plane *plane,
11805 struct intel_plane_state *state)
11806 {
11807 struct drm_crtc *crtc = state->base.crtc;
11808 struct drm_framebuffer *fb = state->base.fb;
11809 struct drm_device *dev = plane->dev;
11810 struct drm_i915_private *dev_priv = dev->dev_private;
11811 struct intel_crtc *intel_crtc;
11812 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11813 struct intel_plane *intel_plane = to_intel_plane(plane);
11814 struct drm_rect *src = &state->src;
11815
11816 crtc = crtc ? crtc : plane->crtc;
11817 intel_crtc = to_intel_crtc(crtc);
11818
11819 plane->fb = fb;
11820 crtc->x = src->x1 >> 16;
11821 crtc->y = src->y1 >> 16;
11822
11823 intel_plane->obj = obj;
11824
11825 if (intel_crtc->active) {
11826 if (state->visible) {
11827 /* FIXME: kill this fastboot hack */
11828 intel_update_pipe_size(intel_crtc);
11829
11830 intel_crtc->primary_enabled = true;
11831
11832 dev_priv->display.update_primary_plane(crtc, plane->fb,
11833 crtc->x, crtc->y);
11834 } else {
11835 /*
11836 * If clipping results in a non-visible primary plane,
11837 * we'll disable the primary plane. Note that this is
11838 * a bit different than what happens if userspace
11839 * explicitly disables the plane by passing fb=0
11840 * because plane->fb still gets set and pinned.
11841 */
11842 intel_disable_primary_hw_plane(plane, crtc);
11843 }
11844 }
11845 }
11846
11847 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
11848 {
11849 struct drm_device *dev = crtc->dev;
11850 struct drm_i915_private *dev_priv = dev->dev_private;
11851 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11852 struct intel_plane *intel_plane;
11853 struct drm_plane *p;
11854 unsigned fb_bits = 0;
11855
11856 /* Track fb's for any planes being disabled */
11857 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
11858 intel_plane = to_intel_plane(p);
11859
11860 if (intel_crtc->atomic.disabled_planes &
11861 (1 << drm_plane_index(p))) {
11862 switch (p->type) {
11863 case DRM_PLANE_TYPE_PRIMARY:
11864 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
11865 break;
11866 case DRM_PLANE_TYPE_CURSOR:
11867 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
11868 break;
11869 case DRM_PLANE_TYPE_OVERLAY:
11870 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
11871 break;
11872 }
11873
11874 mutex_lock(&dev->struct_mutex);
11875 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
11876 mutex_unlock(&dev->struct_mutex);
11877 }
11878 }
11879
11880 if (intel_crtc->atomic.wait_for_flips)
11881 intel_crtc_wait_for_pending_flips(crtc);
11882
11883 if (intel_crtc->atomic.disable_fbc)
11884 intel_fbc_disable(dev);
11885
11886 if (intel_crtc->atomic.pre_disable_primary)
11887 intel_pre_disable_primary(crtc);
11888
11889 if (intel_crtc->atomic.update_wm)
11890 intel_update_watermarks(crtc);
11891
11892 intel_runtime_pm_get(dev_priv);
11893
11894 /* Perform vblank evasion around commit operation */
11895 if (intel_crtc->active)
11896 intel_crtc->atomic.evade =
11897 intel_pipe_update_start(intel_crtc,
11898 &intel_crtc->atomic.start_vbl_count);
11899 }
11900
11901 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
11902 {
11903 struct drm_device *dev = crtc->dev;
11904 struct drm_i915_private *dev_priv = dev->dev_private;
11905 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11906 struct drm_plane *p;
11907
11908 if (intel_crtc->atomic.evade)
11909 intel_pipe_update_end(intel_crtc,
11910 intel_crtc->atomic.start_vbl_count);
11911
11912 intel_runtime_pm_put(dev_priv);
11913
11914 if (intel_crtc->atomic.wait_vblank)
11915 intel_wait_for_vblank(dev, intel_crtc->pipe);
11916
11917 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
11918
11919 if (intel_crtc->atomic.update_fbc) {
11920 mutex_lock(&dev->struct_mutex);
11921 intel_fbc_update(dev);
11922 mutex_unlock(&dev->struct_mutex);
11923 }
11924
11925 if (intel_crtc->atomic.post_enable_primary)
11926 intel_post_enable_primary(crtc);
11927
11928 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
11929 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
11930 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
11931 false, false);
11932
11933 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
11934 }
11935
11936 /**
11937 * intel_plane_destroy - destroy a plane
11938 * @plane: plane to destroy
11939 *
11940 * Common destruction function for all types of planes (primary, cursor,
11941 * sprite).
11942 */
11943 void intel_plane_destroy(struct drm_plane *plane)
11944 {
11945 struct intel_plane *intel_plane = to_intel_plane(plane);
11946 drm_plane_cleanup(plane);
11947 kfree(intel_plane);
11948 }
11949
11950 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11951 .update_plane = drm_plane_helper_update,
11952 .disable_plane = drm_plane_helper_disable,
11953 .destroy = intel_plane_destroy,
11954 .set_property = intel_plane_set_property,
11955 .atomic_duplicate_state = intel_plane_duplicate_state,
11956 .atomic_destroy_state = intel_plane_destroy_state,
11957
11958 };
11959
11960 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11961 int pipe)
11962 {
11963 struct intel_plane *primary;
11964 const uint32_t *intel_primary_formats;
11965 int num_formats;
11966
11967 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11968 if (primary == NULL)
11969 return NULL;
11970
11971 primary->base.state = intel_plane_duplicate_state(&primary->base);
11972 if (primary->base.state == NULL) {
11973 kfree(primary);
11974 return NULL;
11975 }
11976
11977 primary->can_scale = false;
11978 primary->max_downscale = 1;
11979 primary->pipe = pipe;
11980 primary->plane = pipe;
11981 primary->rotation = BIT(DRM_ROTATE_0);
11982 primary->check_plane = intel_check_primary_plane;
11983 primary->commit_plane = intel_commit_primary_plane;
11984 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11985 primary->plane = !pipe;
11986
11987 if (INTEL_INFO(dev)->gen <= 3) {
11988 intel_primary_formats = intel_primary_formats_gen2;
11989 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11990 } else {
11991 intel_primary_formats = intel_primary_formats_gen4;
11992 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11993 }
11994
11995 drm_universal_plane_init(dev, &primary->base, 0,
11996 &intel_primary_plane_funcs,
11997 intel_primary_formats, num_formats,
11998 DRM_PLANE_TYPE_PRIMARY);
11999
12000 if (INTEL_INFO(dev)->gen >= 4) {
12001 if (!dev->mode_config.rotation_property)
12002 dev->mode_config.rotation_property =
12003 drm_mode_create_rotation_property(dev,
12004 BIT(DRM_ROTATE_0) |
12005 BIT(DRM_ROTATE_180));
12006 if (dev->mode_config.rotation_property)
12007 drm_object_attach_property(&primary->base.base,
12008 dev->mode_config.rotation_property,
12009 primary->rotation);
12010 }
12011
12012 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
12013
12014 return &primary->base;
12015 }
12016
12017 static int
12018 intel_check_cursor_plane(struct drm_plane *plane,
12019 struct intel_plane_state *state)
12020 {
12021 struct drm_crtc *crtc = state->base.crtc;
12022 struct drm_device *dev = plane->dev;
12023 struct drm_framebuffer *fb = state->base.fb;
12024 struct drm_rect *dest = &state->dst;
12025 struct drm_rect *src = &state->src;
12026 const struct drm_rect *clip = &state->clip;
12027 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12028 struct intel_crtc *intel_crtc;
12029 unsigned stride;
12030 int ret;
12031
12032 crtc = crtc ? crtc : plane->crtc;
12033 intel_crtc = to_intel_crtc(crtc);
12034
12035 ret = drm_plane_helper_check_update(plane, crtc, fb,
12036 src, dest, clip,
12037 DRM_PLANE_HELPER_NO_SCALING,
12038 DRM_PLANE_HELPER_NO_SCALING,
12039 true, true, &state->visible);
12040 if (ret)
12041 return ret;
12042
12043
12044 /* if we want to turn off the cursor ignore width and height */
12045 if (!obj)
12046 goto finish;
12047
12048 /* Check for which cursor types we support */
12049 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
12050 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
12051 state->base.crtc_w, state->base.crtc_h);
12052 return -EINVAL;
12053 }
12054
12055 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
12056 if (obj->base.size < stride * state->base.crtc_h) {
12057 DRM_DEBUG_KMS("buffer is too small\n");
12058 return -ENOMEM;
12059 }
12060
12061 if (fb == crtc->cursor->fb)
12062 return 0;
12063
12064 /* we only need to pin inside GTT if cursor is non-phy */
12065 mutex_lock(&dev->struct_mutex);
12066 if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) {
12067 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12068 ret = -EINVAL;
12069 }
12070 mutex_unlock(&dev->struct_mutex);
12071
12072 finish:
12073 if (intel_crtc->active) {
12074 if (intel_crtc->cursor_width != state->base.crtc_w)
12075 intel_crtc->atomic.update_wm = true;
12076
12077 intel_crtc->atomic.fb_bits |=
12078 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
12079 }
12080
12081 return ret;
12082 }
12083
12084 static void
12085 intel_commit_cursor_plane(struct drm_plane *plane,
12086 struct intel_plane_state *state)
12087 {
12088 struct drm_crtc *crtc = state->base.crtc;
12089 struct drm_device *dev = plane->dev;
12090 struct intel_crtc *intel_crtc;
12091 struct intel_plane *intel_plane = to_intel_plane(plane);
12092 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
12093 uint32_t addr;
12094
12095 crtc = crtc ? crtc : plane->crtc;
12096 intel_crtc = to_intel_crtc(crtc);
12097
12098 plane->fb = state->base.fb;
12099 crtc->cursor_x = state->base.crtc_x;
12100 crtc->cursor_y = state->base.crtc_y;
12101
12102 intel_plane->obj = obj;
12103
12104 if (intel_crtc->cursor_bo == obj)
12105 goto update;
12106
12107 if (!obj)
12108 addr = 0;
12109 else if (!INTEL_INFO(dev)->cursor_needs_physical)
12110 addr = i915_gem_obj_ggtt_offset(obj);
12111 else
12112 addr = obj->phys_handle->busaddr;
12113
12114 intel_crtc->cursor_addr = addr;
12115 intel_crtc->cursor_bo = obj;
12116 update:
12117 intel_crtc->cursor_width = state->base.crtc_w;
12118 intel_crtc->cursor_height = state->base.crtc_h;
12119
12120 if (intel_crtc->active)
12121 intel_crtc_update_cursor(crtc, state->visible);
12122 }
12123
12124 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
12125 .update_plane = drm_plane_helper_update,
12126 .disable_plane = drm_plane_helper_disable,
12127 .destroy = intel_plane_destroy,
12128 .set_property = intel_plane_set_property,
12129 .atomic_duplicate_state = intel_plane_duplicate_state,
12130 .atomic_destroy_state = intel_plane_destroy_state,
12131 };
12132
12133 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12134 int pipe)
12135 {
12136 struct intel_plane *cursor;
12137
12138 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12139 if (cursor == NULL)
12140 return NULL;
12141
12142 cursor->base.state = intel_plane_duplicate_state(&cursor->base);
12143 if (cursor->base.state == NULL) {
12144 kfree(cursor);
12145 return NULL;
12146 }
12147
12148 cursor->can_scale = false;
12149 cursor->max_downscale = 1;
12150 cursor->pipe = pipe;
12151 cursor->plane = pipe;
12152 cursor->rotation = BIT(DRM_ROTATE_0);
12153 cursor->check_plane = intel_check_cursor_plane;
12154 cursor->commit_plane = intel_commit_cursor_plane;
12155
12156 drm_universal_plane_init(dev, &cursor->base, 0,
12157 &intel_cursor_plane_funcs,
12158 intel_cursor_formats,
12159 ARRAY_SIZE(intel_cursor_formats),
12160 DRM_PLANE_TYPE_CURSOR);
12161
12162 if (INTEL_INFO(dev)->gen >= 4) {
12163 if (!dev->mode_config.rotation_property)
12164 dev->mode_config.rotation_property =
12165 drm_mode_create_rotation_property(dev,
12166 BIT(DRM_ROTATE_0) |
12167 BIT(DRM_ROTATE_180));
12168 if (dev->mode_config.rotation_property)
12169 drm_object_attach_property(&cursor->base.base,
12170 dev->mode_config.rotation_property,
12171 cursor->rotation);
12172 }
12173
12174 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
12175
12176 return &cursor->base;
12177 }
12178
12179 static void intel_crtc_init(struct drm_device *dev, int pipe)
12180 {
12181 struct drm_i915_private *dev_priv = dev->dev_private;
12182 struct intel_crtc *intel_crtc;
12183 struct intel_crtc_state *crtc_state = NULL;
12184 struct drm_plane *primary = NULL;
12185 struct drm_plane *cursor = NULL;
12186 int i, ret;
12187
12188 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12189 if (intel_crtc == NULL)
12190 return;
12191
12192 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
12193 if (!crtc_state)
12194 goto fail;
12195 intel_crtc_set_state(intel_crtc, crtc_state);
12196
12197 primary = intel_primary_plane_create(dev, pipe);
12198 if (!primary)
12199 goto fail;
12200
12201 cursor = intel_cursor_plane_create(dev, pipe);
12202 if (!cursor)
12203 goto fail;
12204
12205 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12206 cursor, &intel_crtc_funcs);
12207 if (ret)
12208 goto fail;
12209
12210 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12211 for (i = 0; i < 256; i++) {
12212 intel_crtc->lut_r[i] = i;
12213 intel_crtc->lut_g[i] = i;
12214 intel_crtc->lut_b[i] = i;
12215 }
12216
12217 /*
12218 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12219 * is hooked to pipe B. Hence we want plane A feeding pipe B.
12220 */
12221 intel_crtc->pipe = pipe;
12222 intel_crtc->plane = pipe;
12223 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12224 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12225 intel_crtc->plane = !pipe;
12226 }
12227
12228 intel_crtc->cursor_base = ~0;
12229 intel_crtc->cursor_cntl = ~0;
12230 intel_crtc->cursor_size = ~0;
12231
12232 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12233 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12234 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12235 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12236
12237 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
12238
12239 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12240
12241 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12242 return;
12243
12244 fail:
12245 if (primary)
12246 drm_plane_cleanup(primary);
12247 if (cursor)
12248 drm_plane_cleanup(cursor);
12249 kfree(crtc_state);
12250 kfree(intel_crtc);
12251 }
12252
12253 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12254 {
12255 struct drm_encoder *encoder = connector->base.encoder;
12256 struct drm_device *dev = connector->base.dev;
12257
12258 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12259
12260 if (!encoder || WARN_ON(!encoder->crtc))
12261 return INVALID_PIPE;
12262
12263 return to_intel_crtc(encoder->crtc)->pipe;
12264 }
12265
12266 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12267 struct drm_file *file)
12268 {
12269 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12270 struct drm_crtc *drmmode_crtc;
12271 struct intel_crtc *crtc;
12272
12273 if (!drm_core_check_feature(dev, DRIVER_MODESET))
12274 return -ENODEV;
12275
12276 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12277
12278 if (!drmmode_crtc) {
12279 DRM_ERROR("no such CRTC id\n");
12280 return -ENOENT;
12281 }
12282
12283 crtc = to_intel_crtc(drmmode_crtc);
12284 pipe_from_crtc_id->pipe = crtc->pipe;
12285
12286 return 0;
12287 }
12288
12289 static int intel_encoder_clones(struct intel_encoder *encoder)
12290 {
12291 struct drm_device *dev = encoder->base.dev;
12292 struct intel_encoder *source_encoder;
12293 int index_mask = 0;
12294 int entry = 0;
12295
12296 for_each_intel_encoder(dev, source_encoder) {
12297 if (encoders_cloneable(encoder, source_encoder))
12298 index_mask |= (1 << entry);
12299
12300 entry++;
12301 }
12302
12303 return index_mask;
12304 }
12305
12306 static bool has_edp_a(struct drm_device *dev)
12307 {
12308 struct drm_i915_private *dev_priv = dev->dev_private;
12309
12310 if (!IS_MOBILE(dev))
12311 return false;
12312
12313 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12314 return false;
12315
12316 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12317 return false;
12318
12319 return true;
12320 }
12321
12322 static bool intel_crt_present(struct drm_device *dev)
12323 {
12324 struct drm_i915_private *dev_priv = dev->dev_private;
12325
12326 if (INTEL_INFO(dev)->gen >= 9)
12327 return false;
12328
12329 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12330 return false;
12331
12332 if (IS_CHERRYVIEW(dev))
12333 return false;
12334
12335 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12336 return false;
12337
12338 return true;
12339 }
12340
12341 static void intel_setup_outputs(struct drm_device *dev)
12342 {
12343 struct drm_i915_private *dev_priv = dev->dev_private;
12344 struct intel_encoder *encoder;
12345 bool dpd_is_edp = false;
12346
12347 intel_lvds_init(dev);
12348
12349 if (intel_crt_present(dev))
12350 intel_crt_init(dev);
12351
12352 if (HAS_DDI(dev)) {
12353 int found;
12354
12355 /* Haswell uses DDI functions to detect digital outputs */
12356 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12357 /* DDI A only supports eDP */
12358 if (found)
12359 intel_ddi_init(dev, PORT_A);
12360
12361 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12362 * register */
12363 found = I915_READ(SFUSE_STRAP);
12364
12365 if (found & SFUSE_STRAP_DDIB_DETECTED)
12366 intel_ddi_init(dev, PORT_B);
12367 if (found & SFUSE_STRAP_DDIC_DETECTED)
12368 intel_ddi_init(dev, PORT_C);
12369 if (found & SFUSE_STRAP_DDID_DETECTED)
12370 intel_ddi_init(dev, PORT_D);
12371 } else if (HAS_PCH_SPLIT(dev)) {
12372 int found;
12373 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12374
12375 if (has_edp_a(dev))
12376 intel_dp_init(dev, DP_A, PORT_A);
12377
12378 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12379 /* PCH SDVOB multiplex with HDMIB */
12380 found = intel_sdvo_init(dev, PCH_SDVOB, true);
12381 if (!found)
12382 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12383 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12384 intel_dp_init(dev, PCH_DP_B, PORT_B);
12385 }
12386
12387 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12388 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12389
12390 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12391 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12392
12393 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12394 intel_dp_init(dev, PCH_DP_C, PORT_C);
12395
12396 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12397 intel_dp_init(dev, PCH_DP_D, PORT_D);
12398 } else if (IS_VALLEYVIEW(dev)) {
12399 /*
12400 * The DP_DETECTED bit is the latched state of the DDC
12401 * SDA pin at boot. However since eDP doesn't require DDC
12402 * (no way to plug in a DP->HDMI dongle) the DDC pins for
12403 * eDP ports may have been muxed to an alternate function.
12404 * Thus we can't rely on the DP_DETECTED bit alone to detect
12405 * eDP ports. Consult the VBT as well as DP_DETECTED to
12406 * detect eDP ports.
12407 */
12408 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
12409 !intel_dp_is_edp(dev, PORT_B))
12410 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12411 PORT_B);
12412 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12413 intel_dp_is_edp(dev, PORT_B))
12414 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12415
12416 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
12417 !intel_dp_is_edp(dev, PORT_C))
12418 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12419 PORT_C);
12420 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12421 intel_dp_is_edp(dev, PORT_C))
12422 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12423
12424 if (IS_CHERRYVIEW(dev)) {
12425 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12426 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12427 PORT_D);
12428 /* eDP not supported on port D, so don't check VBT */
12429 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12430 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12431 }
12432
12433 intel_dsi_init(dev);
12434 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12435 bool found = false;
12436
12437 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12438 DRM_DEBUG_KMS("probing SDVOB\n");
12439 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12440 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12441 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12442 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12443 }
12444
12445 if (!found && SUPPORTS_INTEGRATED_DP(dev))
12446 intel_dp_init(dev, DP_B, PORT_B);
12447 }
12448
12449 /* Before G4X SDVOC doesn't have its own detect register */
12450
12451 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12452 DRM_DEBUG_KMS("probing SDVOC\n");
12453 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12454 }
12455
12456 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12457
12458 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12459 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12460 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12461 }
12462 if (SUPPORTS_INTEGRATED_DP(dev))
12463 intel_dp_init(dev, DP_C, PORT_C);
12464 }
12465
12466 if (SUPPORTS_INTEGRATED_DP(dev) &&
12467 (I915_READ(DP_D) & DP_DETECTED))
12468 intel_dp_init(dev, DP_D, PORT_D);
12469 } else if (IS_GEN2(dev))
12470 intel_dvo_init(dev);
12471
12472 if (SUPPORTS_TV(dev))
12473 intel_tv_init(dev);
12474
12475 intel_psr_init(dev);
12476
12477 for_each_intel_encoder(dev, encoder) {
12478 encoder->base.possible_crtcs = encoder->crtc_mask;
12479 encoder->base.possible_clones =
12480 intel_encoder_clones(encoder);
12481 }
12482
12483 intel_init_pch_refclk(dev);
12484
12485 drm_helper_move_panel_connectors_to_head(dev);
12486 }
12487
12488 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12489 {
12490 struct drm_device *dev = fb->dev;
12491 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12492
12493 drm_framebuffer_cleanup(fb);
12494 mutex_lock(&dev->struct_mutex);
12495 WARN_ON(!intel_fb->obj->framebuffer_references--);
12496 drm_gem_object_unreference(&intel_fb->obj->base);
12497 mutex_unlock(&dev->struct_mutex);
12498 kfree(intel_fb);
12499 }
12500
12501 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12502 struct drm_file *file,
12503 unsigned int *handle)
12504 {
12505 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12506 struct drm_i915_gem_object *obj = intel_fb->obj;
12507
12508 return drm_gem_handle_create(file, &obj->base, handle);
12509 }
12510
12511 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12512 .destroy = intel_user_framebuffer_destroy,
12513 .create_handle = intel_user_framebuffer_create_handle,
12514 };
12515
12516 static int intel_framebuffer_init(struct drm_device *dev,
12517 struct intel_framebuffer *intel_fb,
12518 struct drm_mode_fb_cmd2 *mode_cmd,
12519 struct drm_i915_gem_object *obj)
12520 {
12521 int aligned_height;
12522 int pitch_limit;
12523 int ret;
12524
12525 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12526
12527 if (obj->tiling_mode == I915_TILING_Y) {
12528 DRM_DEBUG("hardware does not support tiling Y\n");
12529 return -EINVAL;
12530 }
12531
12532 if (mode_cmd->pitches[0] & 63) {
12533 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12534 mode_cmd->pitches[0]);
12535 return -EINVAL;
12536 }
12537
12538 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12539 pitch_limit = 32*1024;
12540 } else if (INTEL_INFO(dev)->gen >= 4) {
12541 if (obj->tiling_mode)
12542 pitch_limit = 16*1024;
12543 else
12544 pitch_limit = 32*1024;
12545 } else if (INTEL_INFO(dev)->gen >= 3) {
12546 if (obj->tiling_mode)
12547 pitch_limit = 8*1024;
12548 else
12549 pitch_limit = 16*1024;
12550 } else
12551 /* XXX DSPC is limited to 4k tiled */
12552 pitch_limit = 8*1024;
12553
12554 if (mode_cmd->pitches[0] > pitch_limit) {
12555 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12556 obj->tiling_mode ? "tiled" : "linear",
12557 mode_cmd->pitches[0], pitch_limit);
12558 return -EINVAL;
12559 }
12560
12561 if (obj->tiling_mode != I915_TILING_NONE &&
12562 mode_cmd->pitches[0] != obj->stride) {
12563 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12564 mode_cmd->pitches[0], obj->stride);
12565 return -EINVAL;
12566 }
12567
12568 /* Reject formats not supported by any plane early. */
12569 switch (mode_cmd->pixel_format) {
12570 case DRM_FORMAT_C8:
12571 case DRM_FORMAT_RGB565:
12572 case DRM_FORMAT_XRGB8888:
12573 case DRM_FORMAT_ARGB8888:
12574 break;
12575 case DRM_FORMAT_XRGB1555:
12576 case DRM_FORMAT_ARGB1555:
12577 if (INTEL_INFO(dev)->gen > 3) {
12578 DRM_DEBUG("unsupported pixel format: %s\n",
12579 drm_get_format_name(mode_cmd->pixel_format));
12580 return -EINVAL;
12581 }
12582 break;
12583 case DRM_FORMAT_XBGR8888:
12584 case DRM_FORMAT_ABGR8888:
12585 case DRM_FORMAT_XRGB2101010:
12586 case DRM_FORMAT_ARGB2101010:
12587 case DRM_FORMAT_XBGR2101010:
12588 case DRM_FORMAT_ABGR2101010:
12589 if (INTEL_INFO(dev)->gen < 4) {
12590 DRM_DEBUG("unsupported pixel format: %s\n",
12591 drm_get_format_name(mode_cmd->pixel_format));
12592 return -EINVAL;
12593 }
12594 break;
12595 case DRM_FORMAT_YUYV:
12596 case DRM_FORMAT_UYVY:
12597 case DRM_FORMAT_YVYU:
12598 case DRM_FORMAT_VYUY:
12599 if (INTEL_INFO(dev)->gen < 5) {
12600 DRM_DEBUG("unsupported pixel format: %s\n",
12601 drm_get_format_name(mode_cmd->pixel_format));
12602 return -EINVAL;
12603 }
12604 break;
12605 default:
12606 DRM_DEBUG("unsupported pixel format: %s\n",
12607 drm_get_format_name(mode_cmd->pixel_format));
12608 return -EINVAL;
12609 }
12610
12611 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12612 if (mode_cmd->offsets[0] != 0)
12613 return -EINVAL;
12614
12615 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
12616 obj->tiling_mode);
12617 /* FIXME drm helper for size checks (especially planar formats)? */
12618 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12619 return -EINVAL;
12620
12621 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12622 intel_fb->obj = obj;
12623 intel_fb->obj->framebuffer_references++;
12624
12625 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12626 if (ret) {
12627 DRM_ERROR("framebuffer init failed %d\n", ret);
12628 return ret;
12629 }
12630
12631 return 0;
12632 }
12633
12634 static struct drm_framebuffer *
12635 intel_user_framebuffer_create(struct drm_device *dev,
12636 struct drm_file *filp,
12637 struct drm_mode_fb_cmd2 *mode_cmd)
12638 {
12639 struct drm_i915_gem_object *obj;
12640
12641 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12642 mode_cmd->handles[0]));
12643 if (&obj->base == NULL)
12644 return ERR_PTR(-ENOENT);
12645
12646 return intel_framebuffer_create(dev, mode_cmd, obj);
12647 }
12648
12649 #ifndef CONFIG_DRM_I915_FBDEV
12650 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12651 {
12652 }
12653 #endif
12654
12655 static const struct drm_mode_config_funcs intel_mode_funcs = {
12656 .fb_create = intel_user_framebuffer_create,
12657 .output_poll_changed = intel_fbdev_output_poll_changed,
12658 };
12659
12660 /* Set up chip specific display functions */
12661 static void intel_init_display(struct drm_device *dev)
12662 {
12663 struct drm_i915_private *dev_priv = dev->dev_private;
12664
12665 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12666 dev_priv->display.find_dpll = g4x_find_best_dpll;
12667 else if (IS_CHERRYVIEW(dev))
12668 dev_priv->display.find_dpll = chv_find_best_dpll;
12669 else if (IS_VALLEYVIEW(dev))
12670 dev_priv->display.find_dpll = vlv_find_best_dpll;
12671 else if (IS_PINEVIEW(dev))
12672 dev_priv->display.find_dpll = pnv_find_best_dpll;
12673 else
12674 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12675
12676 if (HAS_DDI(dev)) {
12677 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12678 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12679 dev_priv->display.crtc_compute_clock =
12680 haswell_crtc_compute_clock;
12681 dev_priv->display.crtc_enable = haswell_crtc_enable;
12682 dev_priv->display.crtc_disable = haswell_crtc_disable;
12683 dev_priv->display.off = ironlake_crtc_off;
12684 if (INTEL_INFO(dev)->gen >= 9)
12685 dev_priv->display.update_primary_plane =
12686 skylake_update_primary_plane;
12687 else
12688 dev_priv->display.update_primary_plane =
12689 ironlake_update_primary_plane;
12690 } else if (HAS_PCH_SPLIT(dev)) {
12691 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12692 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12693 dev_priv->display.crtc_compute_clock =
12694 ironlake_crtc_compute_clock;
12695 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12696 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12697 dev_priv->display.off = ironlake_crtc_off;
12698 dev_priv->display.update_primary_plane =
12699 ironlake_update_primary_plane;
12700 } else if (IS_VALLEYVIEW(dev)) {
12701 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12702 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12703 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12704 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12705 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12706 dev_priv->display.off = i9xx_crtc_off;
12707 dev_priv->display.update_primary_plane =
12708 i9xx_update_primary_plane;
12709 } else {
12710 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12711 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12712 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12713 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12714 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12715 dev_priv->display.off = i9xx_crtc_off;
12716 dev_priv->display.update_primary_plane =
12717 i9xx_update_primary_plane;
12718 }
12719
12720 /* Returns the core display clock speed */
12721 if (IS_VALLEYVIEW(dev))
12722 dev_priv->display.get_display_clock_speed =
12723 valleyview_get_display_clock_speed;
12724 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12725 dev_priv->display.get_display_clock_speed =
12726 i945_get_display_clock_speed;
12727 else if (IS_I915G(dev))
12728 dev_priv->display.get_display_clock_speed =
12729 i915_get_display_clock_speed;
12730 else if (IS_I945GM(dev) || IS_845G(dev))
12731 dev_priv->display.get_display_clock_speed =
12732 i9xx_misc_get_display_clock_speed;
12733 else if (IS_PINEVIEW(dev))
12734 dev_priv->display.get_display_clock_speed =
12735 pnv_get_display_clock_speed;
12736 else if (IS_I915GM(dev))
12737 dev_priv->display.get_display_clock_speed =
12738 i915gm_get_display_clock_speed;
12739 else if (IS_I865G(dev))
12740 dev_priv->display.get_display_clock_speed =
12741 i865_get_display_clock_speed;
12742 else if (IS_I85X(dev))
12743 dev_priv->display.get_display_clock_speed =
12744 i855_get_display_clock_speed;
12745 else /* 852, 830 */
12746 dev_priv->display.get_display_clock_speed =
12747 i830_get_display_clock_speed;
12748
12749 if (IS_GEN5(dev)) {
12750 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12751 } else if (IS_GEN6(dev)) {
12752 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12753 } else if (IS_IVYBRIDGE(dev)) {
12754 /* FIXME: detect B0+ stepping and use auto training */
12755 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12756 dev_priv->display.modeset_global_resources =
12757 ivb_modeset_global_resources;
12758 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12759 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12760 } else if (IS_VALLEYVIEW(dev)) {
12761 dev_priv->display.modeset_global_resources =
12762 valleyview_modeset_global_resources;
12763 }
12764
12765 /* Default just returns -ENODEV to indicate unsupported */
12766 dev_priv->display.queue_flip = intel_default_queue_flip;
12767
12768 switch (INTEL_INFO(dev)->gen) {
12769 case 2:
12770 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12771 break;
12772
12773 case 3:
12774 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12775 break;
12776
12777 case 4:
12778 case 5:
12779 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12780 break;
12781
12782 case 6:
12783 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12784 break;
12785 case 7:
12786 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12787 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12788 break;
12789 case 9:
12790 dev_priv->display.queue_flip = intel_gen9_queue_flip;
12791 break;
12792 }
12793
12794 intel_panel_init_backlight_funcs(dev);
12795
12796 mutex_init(&dev_priv->pps_mutex);
12797 }
12798
12799 /*
12800 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12801 * resume, or other times. This quirk makes sure that's the case for
12802 * affected systems.
12803 */
12804 static void quirk_pipea_force(struct drm_device *dev)
12805 {
12806 struct drm_i915_private *dev_priv = dev->dev_private;
12807
12808 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12809 DRM_INFO("applying pipe a force quirk\n");
12810 }
12811
12812 static void quirk_pipeb_force(struct drm_device *dev)
12813 {
12814 struct drm_i915_private *dev_priv = dev->dev_private;
12815
12816 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
12817 DRM_INFO("applying pipe b force quirk\n");
12818 }
12819
12820 /*
12821 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12822 */
12823 static void quirk_ssc_force_disable(struct drm_device *dev)
12824 {
12825 struct drm_i915_private *dev_priv = dev->dev_private;
12826 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12827 DRM_INFO("applying lvds SSC disable quirk\n");
12828 }
12829
12830 /*
12831 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12832 * brightness value
12833 */
12834 static void quirk_invert_brightness(struct drm_device *dev)
12835 {
12836 struct drm_i915_private *dev_priv = dev->dev_private;
12837 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12838 DRM_INFO("applying inverted panel brightness quirk\n");
12839 }
12840
12841 /* Some VBT's incorrectly indicate no backlight is present */
12842 static void quirk_backlight_present(struct drm_device *dev)
12843 {
12844 struct drm_i915_private *dev_priv = dev->dev_private;
12845 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12846 DRM_INFO("applying backlight present quirk\n");
12847 }
12848
12849 struct intel_quirk {
12850 int device;
12851 int subsystem_vendor;
12852 int subsystem_device;
12853 void (*hook)(struct drm_device *dev);
12854 };
12855
12856 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12857 struct intel_dmi_quirk {
12858 void (*hook)(struct drm_device *dev);
12859 const struct dmi_system_id (*dmi_id_list)[];
12860 };
12861
12862 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12863 {
12864 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12865 return 1;
12866 }
12867
12868 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12869 {
12870 .dmi_id_list = &(const struct dmi_system_id[]) {
12871 {
12872 .callback = intel_dmi_reverse_brightness,
12873 .ident = "NCR Corporation",
12874 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12875 DMI_MATCH(DMI_PRODUCT_NAME, ""),
12876 },
12877 },
12878 { } /* terminating entry */
12879 },
12880 .hook = quirk_invert_brightness,
12881 },
12882 };
12883
12884 static struct intel_quirk intel_quirks[] = {
12885 /* HP Mini needs pipe A force quirk (LP: #322104) */
12886 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12887
12888 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12889 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12890
12891 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12892 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12893
12894 /* 830 needs to leave pipe A & dpll A up */
12895 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
12896
12897 /* 830 needs to leave pipe B & dpll B up */
12898 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
12899
12900 /* Lenovo U160 cannot use SSC on LVDS */
12901 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12902
12903 /* Sony Vaio Y cannot use SSC on LVDS */
12904 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12905
12906 /* Acer Aspire 5734Z must invert backlight brightness */
12907 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12908
12909 /* Acer/eMachines G725 */
12910 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12911
12912 /* Acer/eMachines e725 */
12913 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12914
12915 /* Acer/Packard Bell NCL20 */
12916 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12917
12918 /* Acer Aspire 4736Z */
12919 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12920
12921 /* Acer Aspire 5336 */
12922 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12923
12924 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12925 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
12926
12927 /* Acer C720 Chromebook (Core i3 4005U) */
12928 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
12929
12930 /* Apple Macbook 2,1 (Core 2 T7400) */
12931 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
12932
12933 /* Toshiba CB35 Chromebook (Celeron 2955U) */
12934 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
12935
12936 /* HP Chromebook 14 (Celeron 2955U) */
12937 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
12938 };
12939
12940 static void intel_init_quirks(struct drm_device *dev)
12941 {
12942 struct pci_dev *d = dev->pdev;
12943 int i;
12944
12945 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12946 struct intel_quirk *q = &intel_quirks[i];
12947
12948 if (d->device == q->device &&
12949 (d->subsystem_vendor == q->subsystem_vendor ||
12950 q->subsystem_vendor == PCI_ANY_ID) &&
12951 (d->subsystem_device == q->subsystem_device ||
12952 q->subsystem_device == PCI_ANY_ID))
12953 q->hook(dev);
12954 }
12955 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12956 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12957 intel_dmi_quirks[i].hook(dev);
12958 }
12959 }
12960
12961 /* Disable the VGA plane that we never use */
12962 static void i915_disable_vga(struct drm_device *dev)
12963 {
12964 struct drm_i915_private *dev_priv = dev->dev_private;
12965 u8 sr1;
12966 u32 vga_reg = i915_vgacntrl_reg(dev);
12967
12968 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12969 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12970 outb(SR01, VGA_SR_INDEX);
12971 sr1 = inb(VGA_SR_DATA);
12972 outb(sr1 | 1<<5, VGA_SR_DATA);
12973 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12974 udelay(300);
12975
12976 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
12977 POSTING_READ(vga_reg);
12978 }
12979
12980 void intel_modeset_init_hw(struct drm_device *dev)
12981 {
12982 intel_prepare_ddi(dev);
12983
12984 if (IS_VALLEYVIEW(dev))
12985 vlv_update_cdclk(dev);
12986
12987 intel_init_clock_gating(dev);
12988
12989 intel_enable_gt_powersave(dev);
12990 }
12991
12992 void intel_modeset_init(struct drm_device *dev)
12993 {
12994 struct drm_i915_private *dev_priv = dev->dev_private;
12995 int sprite, ret;
12996 enum pipe pipe;
12997 struct intel_crtc *crtc;
12998
12999 drm_mode_config_init(dev);
13000
13001 dev->mode_config.min_width = 0;
13002 dev->mode_config.min_height = 0;
13003
13004 dev->mode_config.preferred_depth = 24;
13005 dev->mode_config.prefer_shadow = 1;
13006
13007 dev->mode_config.funcs = &intel_mode_funcs;
13008
13009 intel_init_quirks(dev);
13010
13011 intel_init_pm(dev);
13012
13013 if (INTEL_INFO(dev)->num_pipes == 0)
13014 return;
13015
13016 intel_init_display(dev);
13017 intel_init_audio(dev);
13018
13019 if (IS_GEN2(dev)) {
13020 dev->mode_config.max_width = 2048;
13021 dev->mode_config.max_height = 2048;
13022 } else if (IS_GEN3(dev)) {
13023 dev->mode_config.max_width = 4096;
13024 dev->mode_config.max_height = 4096;
13025 } else {
13026 dev->mode_config.max_width = 8192;
13027 dev->mode_config.max_height = 8192;
13028 }
13029
13030 if (IS_845G(dev) || IS_I865G(dev)) {
13031 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13032 dev->mode_config.cursor_height = 1023;
13033 } else if (IS_GEN2(dev)) {
13034 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13035 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13036 } else {
13037 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13038 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13039 }
13040
13041 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
13042
13043 DRM_DEBUG_KMS("%d display pipe%s available.\n",
13044 INTEL_INFO(dev)->num_pipes,
13045 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
13046
13047 for_each_pipe(dev_priv, pipe) {
13048 intel_crtc_init(dev, pipe);
13049 for_each_sprite(pipe, sprite) {
13050 ret = intel_plane_init(dev, pipe, sprite);
13051 if (ret)
13052 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13053 pipe_name(pipe), sprite_name(pipe, sprite), ret);
13054 }
13055 }
13056
13057 intel_init_dpio(dev);
13058
13059 intel_shared_dpll_init(dev);
13060
13061 /* Just disable it once at startup */
13062 i915_disable_vga(dev);
13063 intel_setup_outputs(dev);
13064
13065 /* Just in case the BIOS is doing something questionable. */
13066 intel_fbc_disable(dev);
13067
13068 drm_modeset_lock_all(dev);
13069 intel_modeset_setup_hw_state(dev, false);
13070 drm_modeset_unlock_all(dev);
13071
13072 for_each_intel_crtc(dev, crtc) {
13073 if (!crtc->active)
13074 continue;
13075
13076 /*
13077 * Note that reserving the BIOS fb up front prevents us
13078 * from stuffing other stolen allocations like the ring
13079 * on top. This prevents some ugliness at boot time, and
13080 * can even allow for smooth boot transitions if the BIOS
13081 * fb is large enough for the active pipe configuration.
13082 */
13083 if (dev_priv->display.get_plane_config) {
13084 dev_priv->display.get_plane_config(crtc,
13085 &crtc->plane_config);
13086 /*
13087 * If the fb is shared between multiple heads, we'll
13088 * just get the first one.
13089 */
13090 intel_find_plane_obj(crtc, &crtc->plane_config);
13091 }
13092 }
13093 }
13094
13095 static void intel_enable_pipe_a(struct drm_device *dev)
13096 {
13097 struct intel_connector *connector;
13098 struct drm_connector *crt = NULL;
13099 struct intel_load_detect_pipe load_detect_temp;
13100 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13101
13102 /* We can't just switch on the pipe A, we need to set things up with a
13103 * proper mode and output configuration. As a gross hack, enable pipe A
13104 * by enabling the load detect pipe once. */
13105 list_for_each_entry(connector,
13106 &dev->mode_config.connector_list,
13107 base.head) {
13108 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13109 crt = &connector->base;
13110 break;
13111 }
13112 }
13113
13114 if (!crt)
13115 return;
13116
13117 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13118 intel_release_load_detect_pipe(crt, &load_detect_temp);
13119 }
13120
13121 static bool
13122 intel_check_plane_mapping(struct intel_crtc *crtc)
13123 {
13124 struct drm_device *dev = crtc->base.dev;
13125 struct drm_i915_private *dev_priv = dev->dev_private;
13126 u32 reg, val;
13127
13128 if (INTEL_INFO(dev)->num_pipes == 1)
13129 return true;
13130
13131 reg = DSPCNTR(!crtc->plane);
13132 val = I915_READ(reg);
13133
13134 if ((val & DISPLAY_PLANE_ENABLE) &&
13135 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13136 return false;
13137
13138 return true;
13139 }
13140
13141 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13142 {
13143 struct drm_device *dev = crtc->base.dev;
13144 struct drm_i915_private *dev_priv = dev->dev_private;
13145 u32 reg;
13146
13147 /* Clear any frame start delays used for debugging left by the BIOS */
13148 reg = PIPECONF(crtc->config->cpu_transcoder);
13149 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13150
13151 /* restore vblank interrupts to correct state */
13152 if (crtc->active) {
13153 update_scanline_offset(crtc);
13154 drm_vblank_on(dev, crtc->pipe);
13155 } else
13156 drm_vblank_off(dev, crtc->pipe);
13157
13158 /* We need to sanitize the plane -> pipe mapping first because this will
13159 * disable the crtc (and hence change the state) if it is wrong. Note
13160 * that gen4+ has a fixed plane -> pipe mapping. */
13161 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13162 struct intel_connector *connector;
13163 bool plane;
13164
13165 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13166 crtc->base.base.id);
13167
13168 /* Pipe has the wrong plane attached and the plane is active.
13169 * Temporarily change the plane mapping and disable everything
13170 * ... */
13171 plane = crtc->plane;
13172 crtc->plane = !plane;
13173 crtc->primary_enabled = true;
13174 dev_priv->display.crtc_disable(&crtc->base);
13175 crtc->plane = plane;
13176
13177 /* ... and break all links. */
13178 list_for_each_entry(connector, &dev->mode_config.connector_list,
13179 base.head) {
13180 if (connector->encoder->base.crtc != &crtc->base)
13181 continue;
13182
13183 connector->base.dpms = DRM_MODE_DPMS_OFF;
13184 connector->base.encoder = NULL;
13185 }
13186 /* multiple connectors may have the same encoder:
13187 * handle them and break crtc link separately */
13188 list_for_each_entry(connector, &dev->mode_config.connector_list,
13189 base.head)
13190 if (connector->encoder->base.crtc == &crtc->base) {
13191 connector->encoder->base.crtc = NULL;
13192 connector->encoder->connectors_active = false;
13193 }
13194
13195 WARN_ON(crtc->active);
13196 crtc->base.enabled = false;
13197 }
13198
13199 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13200 crtc->pipe == PIPE_A && !crtc->active) {
13201 /* BIOS forgot to enable pipe A, this mostly happens after
13202 * resume. Force-enable the pipe to fix this, the update_dpms
13203 * call below we restore the pipe to the right state, but leave
13204 * the required bits on. */
13205 intel_enable_pipe_a(dev);
13206 }
13207
13208 /* Adjust the state of the output pipe according to whether we
13209 * have active connectors/encoders. */
13210 intel_crtc_update_dpms(&crtc->base);
13211
13212 if (crtc->active != crtc->base.enabled) {
13213 struct intel_encoder *encoder;
13214
13215 /* This can happen either due to bugs in the get_hw_state
13216 * functions or because the pipe is force-enabled due to the
13217 * pipe A quirk. */
13218 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13219 crtc->base.base.id,
13220 crtc->base.enabled ? "enabled" : "disabled",
13221 crtc->active ? "enabled" : "disabled");
13222
13223 crtc->base.enabled = crtc->active;
13224
13225 /* Because we only establish the connector -> encoder ->
13226 * crtc links if something is active, this means the
13227 * crtc is now deactivated. Break the links. connector
13228 * -> encoder links are only establish when things are
13229 * actually up, hence no need to break them. */
13230 WARN_ON(crtc->active);
13231
13232 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13233 WARN_ON(encoder->connectors_active);
13234 encoder->base.crtc = NULL;
13235 }
13236 }
13237
13238 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13239 /*
13240 * We start out with underrun reporting disabled to avoid races.
13241 * For correct bookkeeping mark this on active crtcs.
13242 *
13243 * Also on gmch platforms we dont have any hardware bits to
13244 * disable the underrun reporting. Which means we need to start
13245 * out with underrun reporting disabled also on inactive pipes,
13246 * since otherwise we'll complain about the garbage we read when
13247 * e.g. coming up after runtime pm.
13248 *
13249 * No protection against concurrent access is required - at
13250 * worst a fifo underrun happens which also sets this to false.
13251 */
13252 crtc->cpu_fifo_underrun_disabled = true;
13253 crtc->pch_fifo_underrun_disabled = true;
13254 }
13255 }
13256
13257 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13258 {
13259 struct intel_connector *connector;
13260 struct drm_device *dev = encoder->base.dev;
13261
13262 /* We need to check both for a crtc link (meaning that the
13263 * encoder is active and trying to read from a pipe) and the
13264 * pipe itself being active. */
13265 bool has_active_crtc = encoder->base.crtc &&
13266 to_intel_crtc(encoder->base.crtc)->active;
13267
13268 if (encoder->connectors_active && !has_active_crtc) {
13269 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13270 encoder->base.base.id,
13271 encoder->base.name);
13272
13273 /* Connector is active, but has no active pipe. This is
13274 * fallout from our resume register restoring. Disable
13275 * the encoder manually again. */
13276 if (encoder->base.crtc) {
13277 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13278 encoder->base.base.id,
13279 encoder->base.name);
13280 encoder->disable(encoder);
13281 if (encoder->post_disable)
13282 encoder->post_disable(encoder);
13283 }
13284 encoder->base.crtc = NULL;
13285 encoder->connectors_active = false;
13286
13287 /* Inconsistent output/port/pipe state happens presumably due to
13288 * a bug in one of the get_hw_state functions. Or someplace else
13289 * in our code, like the register restore mess on resume. Clamp
13290 * things to off as a safer default. */
13291 list_for_each_entry(connector,
13292 &dev->mode_config.connector_list,
13293 base.head) {
13294 if (connector->encoder != encoder)
13295 continue;
13296 connector->base.dpms = DRM_MODE_DPMS_OFF;
13297 connector->base.encoder = NULL;
13298 }
13299 }
13300 /* Enabled encoders without active connectors will be fixed in
13301 * the crtc fixup. */
13302 }
13303
13304 void i915_redisable_vga_power_on(struct drm_device *dev)
13305 {
13306 struct drm_i915_private *dev_priv = dev->dev_private;
13307 u32 vga_reg = i915_vgacntrl_reg(dev);
13308
13309 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13310 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13311 i915_disable_vga(dev);
13312 }
13313 }
13314
13315 void i915_redisable_vga(struct drm_device *dev)
13316 {
13317 struct drm_i915_private *dev_priv = dev->dev_private;
13318
13319 /* This function can be called both from intel_modeset_setup_hw_state or
13320 * at a very early point in our resume sequence, where the power well
13321 * structures are not yet restored. Since this function is at a very
13322 * paranoid "someone might have enabled VGA while we were not looking"
13323 * level, just check if the power well is enabled instead of trying to
13324 * follow the "don't touch the power well if we don't need it" policy
13325 * the rest of the driver uses. */
13326 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13327 return;
13328
13329 i915_redisable_vga_power_on(dev);
13330 }
13331
13332 static bool primary_get_hw_state(struct intel_crtc *crtc)
13333 {
13334 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13335
13336 if (!crtc->active)
13337 return false;
13338
13339 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13340 }
13341
13342 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13343 {
13344 struct drm_i915_private *dev_priv = dev->dev_private;
13345 enum pipe pipe;
13346 struct intel_crtc *crtc;
13347 struct intel_encoder *encoder;
13348 struct intel_connector *connector;
13349 int i;
13350
13351 for_each_intel_crtc(dev, crtc) {
13352 memset(crtc->config, 0, sizeof(*crtc->config));
13353
13354 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13355
13356 crtc->active = dev_priv->display.get_pipe_config(crtc,
13357 crtc->config);
13358
13359 crtc->base.enabled = crtc->active;
13360 crtc->primary_enabled = primary_get_hw_state(crtc);
13361
13362 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13363 crtc->base.base.id,
13364 crtc->active ? "enabled" : "disabled");
13365 }
13366
13367 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13368 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13369
13370 pll->on = pll->get_hw_state(dev_priv, pll,
13371 &pll->config.hw_state);
13372 pll->active = 0;
13373 pll->config.crtc_mask = 0;
13374 for_each_intel_crtc(dev, crtc) {
13375 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
13376 pll->active++;
13377 pll->config.crtc_mask |= 1 << crtc->pipe;
13378 }
13379 }
13380
13381 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13382 pll->name, pll->config.crtc_mask, pll->on);
13383
13384 if (pll->config.crtc_mask)
13385 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13386 }
13387
13388 for_each_intel_encoder(dev, encoder) {
13389 pipe = 0;
13390
13391 if (encoder->get_hw_state(encoder, &pipe)) {
13392 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13393 encoder->base.crtc = &crtc->base;
13394 encoder->get_config(encoder, crtc->config);
13395 } else {
13396 encoder->base.crtc = NULL;
13397 }
13398
13399 encoder->connectors_active = false;
13400 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13401 encoder->base.base.id,
13402 encoder->base.name,
13403 encoder->base.crtc ? "enabled" : "disabled",
13404 pipe_name(pipe));
13405 }
13406
13407 list_for_each_entry(connector, &dev->mode_config.connector_list,
13408 base.head) {
13409 if (connector->get_hw_state(connector)) {
13410 connector->base.dpms = DRM_MODE_DPMS_ON;
13411 connector->encoder->connectors_active = true;
13412 connector->base.encoder = &connector->encoder->base;
13413 } else {
13414 connector->base.dpms = DRM_MODE_DPMS_OFF;
13415 connector->base.encoder = NULL;
13416 }
13417 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13418 connector->base.base.id,
13419 connector->base.name,
13420 connector->base.encoder ? "enabled" : "disabled");
13421 }
13422 }
13423
13424 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13425 * and i915 state tracking structures. */
13426 void intel_modeset_setup_hw_state(struct drm_device *dev,
13427 bool force_restore)
13428 {
13429 struct drm_i915_private *dev_priv = dev->dev_private;
13430 enum pipe pipe;
13431 struct intel_crtc *crtc;
13432 struct intel_encoder *encoder;
13433 int i;
13434
13435 intel_modeset_readout_hw_state(dev);
13436
13437 /*
13438 * Now that we have the config, copy it to each CRTC struct
13439 * Note that this could go away if we move to using crtc_config
13440 * checking everywhere.
13441 */
13442 for_each_intel_crtc(dev, crtc) {
13443 if (crtc->active && i915.fastboot) {
13444 intel_mode_from_pipe_config(&crtc->base.mode,
13445 crtc->config);
13446 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13447 crtc->base.base.id);
13448 drm_mode_debug_printmodeline(&crtc->base.mode);
13449 }
13450 }
13451
13452 /* HW state is read out, now we need to sanitize this mess. */
13453 for_each_intel_encoder(dev, encoder) {
13454 intel_sanitize_encoder(encoder);
13455 }
13456
13457 for_each_pipe(dev_priv, pipe) {
13458 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13459 intel_sanitize_crtc(crtc);
13460 intel_dump_pipe_config(crtc, crtc->config,
13461 "[setup_hw_state]");
13462 }
13463
13464 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13465 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13466
13467 if (!pll->on || pll->active)
13468 continue;
13469
13470 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13471
13472 pll->disable(dev_priv, pll);
13473 pll->on = false;
13474 }
13475
13476 if (IS_GEN9(dev))
13477 skl_wm_get_hw_state(dev);
13478 else if (HAS_PCH_SPLIT(dev))
13479 ilk_wm_get_hw_state(dev);
13480
13481 if (force_restore) {
13482 i915_redisable_vga(dev);
13483
13484 /*
13485 * We need to use raw interfaces for restoring state to avoid
13486 * checking (bogus) intermediate states.
13487 */
13488 for_each_pipe(dev_priv, pipe) {
13489 struct drm_crtc *crtc =
13490 dev_priv->pipe_to_crtc_mapping[pipe];
13491
13492 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13493 crtc->primary->fb);
13494 }
13495 } else {
13496 intel_modeset_update_staged_output_state(dev);
13497 }
13498
13499 intel_modeset_check_state(dev);
13500 }
13501
13502 void intel_modeset_gem_init(struct drm_device *dev)
13503 {
13504 struct drm_i915_private *dev_priv = dev->dev_private;
13505 struct drm_crtc *c;
13506 struct drm_i915_gem_object *obj;
13507
13508 mutex_lock(&dev->struct_mutex);
13509 intel_init_gt_powersave(dev);
13510 mutex_unlock(&dev->struct_mutex);
13511
13512 /*
13513 * There may be no VBT; and if the BIOS enabled SSC we can
13514 * just keep using it to avoid unnecessary flicker. Whereas if the
13515 * BIOS isn't using it, don't assume it will work even if the VBT
13516 * indicates as much.
13517 */
13518 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13519 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
13520 DREF_SSC1_ENABLE);
13521
13522 intel_modeset_init_hw(dev);
13523
13524 intel_setup_overlay(dev);
13525
13526 /*
13527 * Make sure any fbs we allocated at startup are properly
13528 * pinned & fenced. When we do the allocation it's too early
13529 * for this.
13530 */
13531 mutex_lock(&dev->struct_mutex);
13532 for_each_crtc(dev, c) {
13533 obj = intel_fb_obj(c->primary->fb);
13534 if (obj == NULL)
13535 continue;
13536
13537 if (intel_pin_and_fence_fb_obj(c->primary,
13538 c->primary->fb,
13539 NULL)) {
13540 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13541 to_intel_crtc(c)->pipe);
13542 drm_framebuffer_unreference(c->primary->fb);
13543 c->primary->fb = NULL;
13544 }
13545 }
13546 mutex_unlock(&dev->struct_mutex);
13547
13548 intel_backlight_register(dev);
13549 }
13550
13551 void intel_connector_unregister(struct intel_connector *intel_connector)
13552 {
13553 struct drm_connector *connector = &intel_connector->base;
13554
13555 intel_panel_destroy_backlight(connector);
13556 drm_connector_unregister(connector);
13557 }
13558
13559 void intel_modeset_cleanup(struct drm_device *dev)
13560 {
13561 struct drm_i915_private *dev_priv = dev->dev_private;
13562 struct drm_connector *connector;
13563
13564 intel_disable_gt_powersave(dev);
13565
13566 intel_backlight_unregister(dev);
13567
13568 /*
13569 * Interrupts and polling as the first thing to avoid creating havoc.
13570 * Too much stuff here (turning of connectors, ...) would
13571 * experience fancy races otherwise.
13572 */
13573 intel_irq_uninstall(dev_priv);
13574
13575 /*
13576 * Due to the hpd irq storm handling the hotplug work can re-arm the
13577 * poll handlers. Hence disable polling after hpd handling is shut down.
13578 */
13579 drm_kms_helper_poll_fini(dev);
13580
13581 mutex_lock(&dev->struct_mutex);
13582
13583 intel_unregister_dsm_handler();
13584
13585 intel_fbc_disable(dev);
13586
13587 ironlake_teardown_rc6(dev);
13588
13589 mutex_unlock(&dev->struct_mutex);
13590
13591 /* flush any delayed tasks or pending work */
13592 flush_scheduled_work();
13593
13594 /* destroy the backlight and sysfs files before encoders/connectors */
13595 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13596 struct intel_connector *intel_connector;
13597
13598 intel_connector = to_intel_connector(connector);
13599 intel_connector->unregister(intel_connector);
13600 }
13601
13602 drm_mode_config_cleanup(dev);
13603
13604 intel_cleanup_overlay(dev);
13605
13606 mutex_lock(&dev->struct_mutex);
13607 intel_cleanup_gt_powersave(dev);
13608 mutex_unlock(&dev->struct_mutex);
13609 }
13610
13611 /*
13612 * Return which encoder is currently attached for connector.
13613 */
13614 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13615 {
13616 return &intel_attached_encoder(connector)->base;
13617 }
13618
13619 void intel_connector_attach_encoder(struct intel_connector *connector,
13620 struct intel_encoder *encoder)
13621 {
13622 connector->encoder = encoder;
13623 drm_mode_connector_attach_encoder(&connector->base,
13624 &encoder->base);
13625 }
13626
13627 /*
13628 * set vga decode state - true == enable VGA decode
13629 */
13630 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13631 {
13632 struct drm_i915_private *dev_priv = dev->dev_private;
13633 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13634 u16 gmch_ctrl;
13635
13636 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13637 DRM_ERROR("failed to read control word\n");
13638 return -EIO;
13639 }
13640
13641 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13642 return 0;
13643
13644 if (state)
13645 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13646 else
13647 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13648
13649 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13650 DRM_ERROR("failed to write control word\n");
13651 return -EIO;
13652 }
13653
13654 return 0;
13655 }
13656
13657 struct intel_display_error_state {
13658
13659 u32 power_well_driver;
13660
13661 int num_transcoders;
13662
13663 struct intel_cursor_error_state {
13664 u32 control;
13665 u32 position;
13666 u32 base;
13667 u32 size;
13668 } cursor[I915_MAX_PIPES];
13669
13670 struct intel_pipe_error_state {
13671 bool power_domain_on;
13672 u32 source;
13673 u32 stat;
13674 } pipe[I915_MAX_PIPES];
13675
13676 struct intel_plane_error_state {
13677 u32 control;
13678 u32 stride;
13679 u32 size;
13680 u32 pos;
13681 u32 addr;
13682 u32 surface;
13683 u32 tile_offset;
13684 } plane[I915_MAX_PIPES];
13685
13686 struct intel_transcoder_error_state {
13687 bool power_domain_on;
13688 enum transcoder cpu_transcoder;
13689
13690 u32 conf;
13691
13692 u32 htotal;
13693 u32 hblank;
13694 u32 hsync;
13695 u32 vtotal;
13696 u32 vblank;
13697 u32 vsync;
13698 } transcoder[4];
13699 };
13700
13701 struct intel_display_error_state *
13702 intel_display_capture_error_state(struct drm_device *dev)
13703 {
13704 struct drm_i915_private *dev_priv = dev->dev_private;
13705 struct intel_display_error_state *error;
13706 int transcoders[] = {
13707 TRANSCODER_A,
13708 TRANSCODER_B,
13709 TRANSCODER_C,
13710 TRANSCODER_EDP,
13711 };
13712 int i;
13713
13714 if (INTEL_INFO(dev)->num_pipes == 0)
13715 return NULL;
13716
13717 error = kzalloc(sizeof(*error), GFP_ATOMIC);
13718 if (error == NULL)
13719 return NULL;
13720
13721 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13722 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13723
13724 for_each_pipe(dev_priv, i) {
13725 error->pipe[i].power_domain_on =
13726 __intel_display_power_is_enabled(dev_priv,
13727 POWER_DOMAIN_PIPE(i));
13728 if (!error->pipe[i].power_domain_on)
13729 continue;
13730
13731 error->cursor[i].control = I915_READ(CURCNTR(i));
13732 error->cursor[i].position = I915_READ(CURPOS(i));
13733 error->cursor[i].base = I915_READ(CURBASE(i));
13734
13735 error->plane[i].control = I915_READ(DSPCNTR(i));
13736 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13737 if (INTEL_INFO(dev)->gen <= 3) {
13738 error->plane[i].size = I915_READ(DSPSIZE(i));
13739 error->plane[i].pos = I915_READ(DSPPOS(i));
13740 }
13741 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13742 error->plane[i].addr = I915_READ(DSPADDR(i));
13743 if (INTEL_INFO(dev)->gen >= 4) {
13744 error->plane[i].surface = I915_READ(DSPSURF(i));
13745 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13746 }
13747
13748 error->pipe[i].source = I915_READ(PIPESRC(i));
13749
13750 if (HAS_GMCH_DISPLAY(dev))
13751 error->pipe[i].stat = I915_READ(PIPESTAT(i));
13752 }
13753
13754 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13755 if (HAS_DDI(dev_priv->dev))
13756 error->num_transcoders++; /* Account for eDP. */
13757
13758 for (i = 0; i < error->num_transcoders; i++) {
13759 enum transcoder cpu_transcoder = transcoders[i];
13760
13761 error->transcoder[i].power_domain_on =
13762 __intel_display_power_is_enabled(dev_priv,
13763 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13764 if (!error->transcoder[i].power_domain_on)
13765 continue;
13766
13767 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13768
13769 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13770 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13771 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13772 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13773 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13774 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13775 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13776 }
13777
13778 return error;
13779 }
13780
13781 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13782
13783 void
13784 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13785 struct drm_device *dev,
13786 struct intel_display_error_state *error)
13787 {
13788 struct drm_i915_private *dev_priv = dev->dev_private;
13789 int i;
13790
13791 if (!error)
13792 return;
13793
13794 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13795 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13796 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13797 error->power_well_driver);
13798 for_each_pipe(dev_priv, i) {
13799 err_printf(m, "Pipe [%d]:\n", i);
13800 err_printf(m, " Power: %s\n",
13801 error->pipe[i].power_domain_on ? "on" : "off");
13802 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
13803 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
13804
13805 err_printf(m, "Plane [%d]:\n", i);
13806 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
13807 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
13808 if (INTEL_INFO(dev)->gen <= 3) {
13809 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
13810 err_printf(m, " POS: %08x\n", error->plane[i].pos);
13811 }
13812 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13813 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
13814 if (INTEL_INFO(dev)->gen >= 4) {
13815 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
13816 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
13817 }
13818
13819 err_printf(m, "Cursor [%d]:\n", i);
13820 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
13821 err_printf(m, " POS: %08x\n", error->cursor[i].position);
13822 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
13823 }
13824
13825 for (i = 0; i < error->num_transcoders; i++) {
13826 err_printf(m, "CPU transcoder: %c\n",
13827 transcoder_name(error->transcoder[i].cpu_transcoder));
13828 err_printf(m, " Power: %s\n",
13829 error->transcoder[i].power_domain_on ? "on" : "off");
13830 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
13831 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
13832 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
13833 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
13834 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
13835 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
13836 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
13837 }
13838 }
13839
13840 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
13841 {
13842 struct intel_crtc *crtc;
13843
13844 for_each_intel_crtc(dev, crtc) {
13845 struct intel_unpin_work *work;
13846
13847 spin_lock_irq(&dev->event_lock);
13848
13849 work = crtc->unpin_work;
13850
13851 if (work && work->event &&
13852 work->event->base.file_priv == file) {
13853 kfree(work->event);
13854 work->event = NULL;
13855 }
13856
13857 spin_unlock_irq(&dev->event_lock);
13858 }
13859 }
Linux kernel - Deliverables
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