2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
);
45 static void intel_increase_pllclock(struct drm_crtc
*crtc
);
46 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
69 #define INTEL_P2_NUM 2
70 typedef struct intel_limit intel_limit_t
;
72 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
75 * find_pll() - Find the best values for the PLL
76 * @limit: limits for the PLL
78 * @target: target frequency in kHz
79 * @refclk: reference clock frequency in kHz
80 * @match_clock: if provided, @best_clock P divider must
81 * match the P divider from @match_clock
82 * used for LVDS downclocking
83 * @best_clock: best PLL values found
85 * Returns true on success, false on failure.
87 bool (*find_pll
)(const intel_limit_t
*limit
,
88 struct drm_crtc
*crtc
,
89 int target
, int refclk
,
90 intel_clock_t
*match_clock
,
91 intel_clock_t
*best_clock
);
95 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
98 intel_pch_rawclk(struct drm_device
*dev
)
100 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
102 WARN_ON(!HAS_PCH_SPLIT(dev
));
104 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
108 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
109 int target
, int refclk
, intel_clock_t
*match_clock
,
110 intel_clock_t
*best_clock
);
112 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
113 int target
, int refclk
, intel_clock_t
*match_clock
,
114 intel_clock_t
*best_clock
);
117 intel_find_pll_g4x_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
118 int target
, int refclk
, intel_clock_t
*match_clock
,
119 intel_clock_t
*best_clock
);
121 intel_find_pll_ironlake_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
122 int target
, int refclk
, intel_clock_t
*match_clock
,
123 intel_clock_t
*best_clock
);
126 intel_vlv_find_best_pll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
127 int target
, int refclk
, intel_clock_t
*match_clock
,
128 intel_clock_t
*best_clock
);
130 static inline u32
/* units of 100MHz */
131 intel_fdi_link_freq(struct drm_device
*dev
)
134 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
135 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
140 static const intel_limit_t intel_limits_i8xx_dvo
= {
141 .dot
= { .min
= 25000, .max
= 350000 },
142 .vco
= { .min
= 930000, .max
= 1400000 },
143 .n
= { .min
= 3, .max
= 16 },
144 .m
= { .min
= 96, .max
= 140 },
145 .m1
= { .min
= 18, .max
= 26 },
146 .m2
= { .min
= 6, .max
= 16 },
147 .p
= { .min
= 4, .max
= 128 },
148 .p1
= { .min
= 2, .max
= 33 },
149 .p2
= { .dot_limit
= 165000,
150 .p2_slow
= 4, .p2_fast
= 2 },
151 .find_pll
= intel_find_best_PLL
,
154 static const intel_limit_t intel_limits_i8xx_lvds
= {
155 .dot
= { .min
= 25000, .max
= 350000 },
156 .vco
= { .min
= 930000, .max
= 1400000 },
157 .n
= { .min
= 3, .max
= 16 },
158 .m
= { .min
= 96, .max
= 140 },
159 .m1
= { .min
= 18, .max
= 26 },
160 .m2
= { .min
= 6, .max
= 16 },
161 .p
= { .min
= 4, .max
= 128 },
162 .p1
= { .min
= 1, .max
= 6 },
163 .p2
= { .dot_limit
= 165000,
164 .p2_slow
= 14, .p2_fast
= 7 },
165 .find_pll
= intel_find_best_PLL
,
168 static const intel_limit_t intel_limits_i9xx_sdvo
= {
169 .dot
= { .min
= 20000, .max
= 400000 },
170 .vco
= { .min
= 1400000, .max
= 2800000 },
171 .n
= { .min
= 1, .max
= 6 },
172 .m
= { .min
= 70, .max
= 120 },
173 .m1
= { .min
= 8, .max
= 18 },
174 .m2
= { .min
= 3, .max
= 7 },
175 .p
= { .min
= 5, .max
= 80 },
176 .p1
= { .min
= 1, .max
= 8 },
177 .p2
= { .dot_limit
= 200000,
178 .p2_slow
= 10, .p2_fast
= 5 },
179 .find_pll
= intel_find_best_PLL
,
182 static const intel_limit_t intel_limits_i9xx_lvds
= {
183 .dot
= { .min
= 20000, .max
= 400000 },
184 .vco
= { .min
= 1400000, .max
= 2800000 },
185 .n
= { .min
= 1, .max
= 6 },
186 .m
= { .min
= 70, .max
= 120 },
187 .m1
= { .min
= 8, .max
= 18 },
188 .m2
= { .min
= 3, .max
= 7 },
189 .p
= { .min
= 7, .max
= 98 },
190 .p1
= { .min
= 1, .max
= 8 },
191 .p2
= { .dot_limit
= 112000,
192 .p2_slow
= 14, .p2_fast
= 7 },
193 .find_pll
= intel_find_best_PLL
,
197 static const intel_limit_t intel_limits_g4x_sdvo
= {
198 .dot
= { .min
= 25000, .max
= 270000 },
199 .vco
= { .min
= 1750000, .max
= 3500000},
200 .n
= { .min
= 1, .max
= 4 },
201 .m
= { .min
= 104, .max
= 138 },
202 .m1
= { .min
= 17, .max
= 23 },
203 .m2
= { .min
= 5, .max
= 11 },
204 .p
= { .min
= 10, .max
= 30 },
205 .p1
= { .min
= 1, .max
= 3},
206 .p2
= { .dot_limit
= 270000,
210 .find_pll
= intel_g4x_find_best_PLL
,
213 static const intel_limit_t intel_limits_g4x_hdmi
= {
214 .dot
= { .min
= 22000, .max
= 400000 },
215 .vco
= { .min
= 1750000, .max
= 3500000},
216 .n
= { .min
= 1, .max
= 4 },
217 .m
= { .min
= 104, .max
= 138 },
218 .m1
= { .min
= 16, .max
= 23 },
219 .m2
= { .min
= 5, .max
= 11 },
220 .p
= { .min
= 5, .max
= 80 },
221 .p1
= { .min
= 1, .max
= 8},
222 .p2
= { .dot_limit
= 165000,
223 .p2_slow
= 10, .p2_fast
= 5 },
224 .find_pll
= intel_g4x_find_best_PLL
,
227 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
228 .dot
= { .min
= 20000, .max
= 115000 },
229 .vco
= { .min
= 1750000, .max
= 3500000 },
230 .n
= { .min
= 1, .max
= 3 },
231 .m
= { .min
= 104, .max
= 138 },
232 .m1
= { .min
= 17, .max
= 23 },
233 .m2
= { .min
= 5, .max
= 11 },
234 .p
= { .min
= 28, .max
= 112 },
235 .p1
= { .min
= 2, .max
= 8 },
236 .p2
= { .dot_limit
= 0,
237 .p2_slow
= 14, .p2_fast
= 14
239 .find_pll
= intel_g4x_find_best_PLL
,
242 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
243 .dot
= { .min
= 80000, .max
= 224000 },
244 .vco
= { .min
= 1750000, .max
= 3500000 },
245 .n
= { .min
= 1, .max
= 3 },
246 .m
= { .min
= 104, .max
= 138 },
247 .m1
= { .min
= 17, .max
= 23 },
248 .m2
= { .min
= 5, .max
= 11 },
249 .p
= { .min
= 14, .max
= 42 },
250 .p1
= { .min
= 2, .max
= 6 },
251 .p2
= { .dot_limit
= 0,
252 .p2_slow
= 7, .p2_fast
= 7
254 .find_pll
= intel_g4x_find_best_PLL
,
257 static const intel_limit_t intel_limits_g4x_display_port
= {
258 .dot
= { .min
= 161670, .max
= 227000 },
259 .vco
= { .min
= 1750000, .max
= 3500000},
260 .n
= { .min
= 1, .max
= 2 },
261 .m
= { .min
= 97, .max
= 108 },
262 .m1
= { .min
= 0x10, .max
= 0x12 },
263 .m2
= { .min
= 0x05, .max
= 0x06 },
264 .p
= { .min
= 10, .max
= 20 },
265 .p1
= { .min
= 1, .max
= 2},
266 .p2
= { .dot_limit
= 0,
267 .p2_slow
= 10, .p2_fast
= 10 },
268 .find_pll
= intel_find_pll_g4x_dp
,
271 static const intel_limit_t intel_limits_pineview_sdvo
= {
272 .dot
= { .min
= 20000, .max
= 400000},
273 .vco
= { .min
= 1700000, .max
= 3500000 },
274 /* Pineview's Ncounter is a ring counter */
275 .n
= { .min
= 3, .max
= 6 },
276 .m
= { .min
= 2, .max
= 256 },
277 /* Pineview only has one combined m divider, which we treat as m2. */
278 .m1
= { .min
= 0, .max
= 0 },
279 .m2
= { .min
= 0, .max
= 254 },
280 .p
= { .min
= 5, .max
= 80 },
281 .p1
= { .min
= 1, .max
= 8 },
282 .p2
= { .dot_limit
= 200000,
283 .p2_slow
= 10, .p2_fast
= 5 },
284 .find_pll
= intel_find_best_PLL
,
287 static const intel_limit_t intel_limits_pineview_lvds
= {
288 .dot
= { .min
= 20000, .max
= 400000 },
289 .vco
= { .min
= 1700000, .max
= 3500000 },
290 .n
= { .min
= 3, .max
= 6 },
291 .m
= { .min
= 2, .max
= 256 },
292 .m1
= { .min
= 0, .max
= 0 },
293 .m2
= { .min
= 0, .max
= 254 },
294 .p
= { .min
= 7, .max
= 112 },
295 .p1
= { .min
= 1, .max
= 8 },
296 .p2
= { .dot_limit
= 112000,
297 .p2_slow
= 14, .p2_fast
= 14 },
298 .find_pll
= intel_find_best_PLL
,
301 /* Ironlake / Sandybridge
303 * We calculate clock using (register_value + 2) for N/M1/M2, so here
304 * the range value for them is (actual_value - 2).
306 static const intel_limit_t intel_limits_ironlake_dac
= {
307 .dot
= { .min
= 25000, .max
= 350000 },
308 .vco
= { .min
= 1760000, .max
= 3510000 },
309 .n
= { .min
= 1, .max
= 5 },
310 .m
= { .min
= 79, .max
= 127 },
311 .m1
= { .min
= 12, .max
= 22 },
312 .m2
= { .min
= 5, .max
= 9 },
313 .p
= { .min
= 5, .max
= 80 },
314 .p1
= { .min
= 1, .max
= 8 },
315 .p2
= { .dot_limit
= 225000,
316 .p2_slow
= 10, .p2_fast
= 5 },
317 .find_pll
= intel_g4x_find_best_PLL
,
320 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
321 .dot
= { .min
= 25000, .max
= 350000 },
322 .vco
= { .min
= 1760000, .max
= 3510000 },
323 .n
= { .min
= 1, .max
= 3 },
324 .m
= { .min
= 79, .max
= 118 },
325 .m1
= { .min
= 12, .max
= 22 },
326 .m2
= { .min
= 5, .max
= 9 },
327 .p
= { .min
= 28, .max
= 112 },
328 .p1
= { .min
= 2, .max
= 8 },
329 .p2
= { .dot_limit
= 225000,
330 .p2_slow
= 14, .p2_fast
= 14 },
331 .find_pll
= intel_g4x_find_best_PLL
,
334 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
335 .dot
= { .min
= 25000, .max
= 350000 },
336 .vco
= { .min
= 1760000, .max
= 3510000 },
337 .n
= { .min
= 1, .max
= 3 },
338 .m
= { .min
= 79, .max
= 127 },
339 .m1
= { .min
= 12, .max
= 22 },
340 .m2
= { .min
= 5, .max
= 9 },
341 .p
= { .min
= 14, .max
= 56 },
342 .p1
= { .min
= 2, .max
= 8 },
343 .p2
= { .dot_limit
= 225000,
344 .p2_slow
= 7, .p2_fast
= 7 },
345 .find_pll
= intel_g4x_find_best_PLL
,
348 /* LVDS 100mhz refclk limits. */
349 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
350 .dot
= { .min
= 25000, .max
= 350000 },
351 .vco
= { .min
= 1760000, .max
= 3510000 },
352 .n
= { .min
= 1, .max
= 2 },
353 .m
= { .min
= 79, .max
= 126 },
354 .m1
= { .min
= 12, .max
= 22 },
355 .m2
= { .min
= 5, .max
= 9 },
356 .p
= { .min
= 28, .max
= 112 },
357 .p1
= { .min
= 2, .max
= 8 },
358 .p2
= { .dot_limit
= 225000,
359 .p2_slow
= 14, .p2_fast
= 14 },
360 .find_pll
= intel_g4x_find_best_PLL
,
363 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
364 .dot
= { .min
= 25000, .max
= 350000 },
365 .vco
= { .min
= 1760000, .max
= 3510000 },
366 .n
= { .min
= 1, .max
= 3 },
367 .m
= { .min
= 79, .max
= 126 },
368 .m1
= { .min
= 12, .max
= 22 },
369 .m2
= { .min
= 5, .max
= 9 },
370 .p
= { .min
= 14, .max
= 42 },
371 .p1
= { .min
= 2, .max
= 6 },
372 .p2
= { .dot_limit
= 225000,
373 .p2_slow
= 7, .p2_fast
= 7 },
374 .find_pll
= intel_g4x_find_best_PLL
,
377 static const intel_limit_t intel_limits_ironlake_display_port
= {
378 .dot
= { .min
= 25000, .max
= 350000 },
379 .vco
= { .min
= 1760000, .max
= 3510000},
380 .n
= { .min
= 1, .max
= 2 },
381 .m
= { .min
= 81, .max
= 90 },
382 .m1
= { .min
= 12, .max
= 22 },
383 .m2
= { .min
= 5, .max
= 9 },
384 .p
= { .min
= 10, .max
= 20 },
385 .p1
= { .min
= 1, .max
= 2},
386 .p2
= { .dot_limit
= 0,
387 .p2_slow
= 10, .p2_fast
= 10 },
388 .find_pll
= intel_find_pll_ironlake_dp
,
391 static const intel_limit_t intel_limits_vlv_dac
= {
392 .dot
= { .min
= 25000, .max
= 270000 },
393 .vco
= { .min
= 4000000, .max
= 6000000 },
394 .n
= { .min
= 1, .max
= 7 },
395 .m
= { .min
= 22, .max
= 450 }, /* guess */
396 .m1
= { .min
= 2, .max
= 3 },
397 .m2
= { .min
= 11, .max
= 156 },
398 .p
= { .min
= 10, .max
= 30 },
399 .p1
= { .min
= 2, .max
= 3 },
400 .p2
= { .dot_limit
= 270000,
401 .p2_slow
= 2, .p2_fast
= 20 },
402 .find_pll
= intel_vlv_find_best_pll
,
405 static const intel_limit_t intel_limits_vlv_hdmi
= {
406 .dot
= { .min
= 20000, .max
= 165000 },
407 .vco
= { .min
= 4000000, .max
= 5994000},
408 .n
= { .min
= 1, .max
= 7 },
409 .m
= { .min
= 60, .max
= 300 }, /* guess */
410 .m1
= { .min
= 2, .max
= 3 },
411 .m2
= { .min
= 11, .max
= 156 },
412 .p
= { .min
= 10, .max
= 30 },
413 .p1
= { .min
= 2, .max
= 3 },
414 .p2
= { .dot_limit
= 270000,
415 .p2_slow
= 2, .p2_fast
= 20 },
416 .find_pll
= intel_vlv_find_best_pll
,
419 static const intel_limit_t intel_limits_vlv_dp
= {
420 .dot
= { .min
= 25000, .max
= 270000 },
421 .vco
= { .min
= 4000000, .max
= 6000000 },
422 .n
= { .min
= 1, .max
= 7 },
423 .m
= { .min
= 22, .max
= 450 },
424 .m1
= { .min
= 2, .max
= 3 },
425 .m2
= { .min
= 11, .max
= 156 },
426 .p
= { .min
= 10, .max
= 30 },
427 .p1
= { .min
= 2, .max
= 3 },
428 .p2
= { .dot_limit
= 270000,
429 .p2_slow
= 2, .p2_fast
= 20 },
430 .find_pll
= intel_vlv_find_best_pll
,
433 u32
intel_dpio_read(struct drm_i915_private
*dev_priv
, int reg
)
435 WARN_ON(!mutex_is_locked(&dev_priv
->dpio_lock
));
437 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
438 DRM_ERROR("DPIO idle wait timed out\n");
442 I915_WRITE(DPIO_REG
, reg
);
443 I915_WRITE(DPIO_PKT
, DPIO_RID
| DPIO_OP_READ
| DPIO_PORTID
|
445 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
446 DRM_ERROR("DPIO read wait timed out\n");
450 return I915_READ(DPIO_DATA
);
453 static void intel_dpio_write(struct drm_i915_private
*dev_priv
, int reg
,
456 WARN_ON(!mutex_is_locked(&dev_priv
->dpio_lock
));
458 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
459 DRM_ERROR("DPIO idle wait timed out\n");
463 I915_WRITE(DPIO_DATA
, val
);
464 I915_WRITE(DPIO_REG
, reg
);
465 I915_WRITE(DPIO_PKT
, DPIO_RID
| DPIO_OP_WRITE
| DPIO_PORTID
|
467 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100))
468 DRM_ERROR("DPIO write wait timed out\n");
471 static void vlv_init_dpio(struct drm_device
*dev
)
473 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
475 /* Reset the DPIO config */
476 I915_WRITE(DPIO_CTL
, 0);
477 POSTING_READ(DPIO_CTL
);
478 I915_WRITE(DPIO_CTL
, 1);
479 POSTING_READ(DPIO_CTL
);
482 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
,
485 struct drm_device
*dev
= crtc
->dev
;
486 const intel_limit_t
*limit
;
488 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
489 if (intel_is_dual_link_lvds(dev
)) {
490 if (refclk
== 100000)
491 limit
= &intel_limits_ironlake_dual_lvds_100m
;
493 limit
= &intel_limits_ironlake_dual_lvds
;
495 if (refclk
== 100000)
496 limit
= &intel_limits_ironlake_single_lvds_100m
;
498 limit
= &intel_limits_ironlake_single_lvds
;
500 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
501 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))
502 limit
= &intel_limits_ironlake_display_port
;
504 limit
= &intel_limits_ironlake_dac
;
509 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
511 struct drm_device
*dev
= crtc
->dev
;
512 const intel_limit_t
*limit
;
514 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
515 if (intel_is_dual_link_lvds(dev
))
516 limit
= &intel_limits_g4x_dual_channel_lvds
;
518 limit
= &intel_limits_g4x_single_channel_lvds
;
519 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
520 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
521 limit
= &intel_limits_g4x_hdmi
;
522 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
523 limit
= &intel_limits_g4x_sdvo
;
524 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
525 limit
= &intel_limits_g4x_display_port
;
526 } else /* The option is for other outputs */
527 limit
= &intel_limits_i9xx_sdvo
;
532 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
, int refclk
)
534 struct drm_device
*dev
= crtc
->dev
;
535 const intel_limit_t
*limit
;
537 if (HAS_PCH_SPLIT(dev
))
538 limit
= intel_ironlake_limit(crtc
, refclk
);
539 else if (IS_G4X(dev
)) {
540 limit
= intel_g4x_limit(crtc
);
541 } else if (IS_PINEVIEW(dev
)) {
542 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
543 limit
= &intel_limits_pineview_lvds
;
545 limit
= &intel_limits_pineview_sdvo
;
546 } else if (IS_VALLEYVIEW(dev
)) {
547 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
))
548 limit
= &intel_limits_vlv_dac
;
549 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
550 limit
= &intel_limits_vlv_hdmi
;
552 limit
= &intel_limits_vlv_dp
;
553 } else if (!IS_GEN2(dev
)) {
554 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
555 limit
= &intel_limits_i9xx_lvds
;
557 limit
= &intel_limits_i9xx_sdvo
;
559 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
560 limit
= &intel_limits_i8xx_lvds
;
562 limit
= &intel_limits_i8xx_dvo
;
567 /* m1 is reserved as 0 in Pineview, n is a ring counter */
568 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
570 clock
->m
= clock
->m2
+ 2;
571 clock
->p
= clock
->p1
* clock
->p2
;
572 clock
->vco
= refclk
* clock
->m
/ clock
->n
;
573 clock
->dot
= clock
->vco
/ clock
->p
;
576 static void intel_clock(struct drm_device
*dev
, int refclk
, intel_clock_t
*clock
)
578 if (IS_PINEVIEW(dev
)) {
579 pineview_clock(refclk
, clock
);
582 clock
->m
= 5 * (clock
->m1
+ 2) + (clock
->m2
+ 2);
583 clock
->p
= clock
->p1
* clock
->p2
;
584 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
585 clock
->dot
= clock
->vco
/ clock
->p
;
589 * Returns whether any output on the specified pipe is of the specified type
591 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
593 struct drm_device
*dev
= crtc
->dev
;
594 struct intel_encoder
*encoder
;
596 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
597 if (encoder
->type
== type
)
603 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
605 * Returns whether the given set of divisors are valid for a given refclk with
606 * the given connectors.
609 static bool intel_PLL_is_valid(struct drm_device
*dev
,
610 const intel_limit_t
*limit
,
611 const intel_clock_t
*clock
)
613 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
614 INTELPllInvalid("p1 out of range\n");
615 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
616 INTELPllInvalid("p out of range\n");
617 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
618 INTELPllInvalid("m2 out of range\n");
619 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
620 INTELPllInvalid("m1 out of range\n");
621 if (clock
->m1
<= clock
->m2
&& !IS_PINEVIEW(dev
))
622 INTELPllInvalid("m1 <= m2\n");
623 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
624 INTELPllInvalid("m out of range\n");
625 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
626 INTELPllInvalid("n out of range\n");
627 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
628 INTELPllInvalid("vco out of range\n");
629 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
630 * connector, etc., rather than just a single range.
632 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
633 INTELPllInvalid("dot out of range\n");
639 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
640 int target
, int refclk
, intel_clock_t
*match_clock
,
641 intel_clock_t
*best_clock
)
644 struct drm_device
*dev
= crtc
->dev
;
648 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
650 * For LVDS just rely on its current settings for dual-channel.
651 * We haven't figured out how to reliably set up different
652 * single/dual channel state, if we even can.
654 if (intel_is_dual_link_lvds(dev
))
655 clock
.p2
= limit
->p2
.p2_fast
;
657 clock
.p2
= limit
->p2
.p2_slow
;
659 if (target
< limit
->p2
.dot_limit
)
660 clock
.p2
= limit
->p2
.p2_slow
;
662 clock
.p2
= limit
->p2
.p2_fast
;
665 memset(best_clock
, 0, sizeof(*best_clock
));
667 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
669 for (clock
.m2
= limit
->m2
.min
;
670 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
671 /* m1 is always 0 in Pineview */
672 if (clock
.m2
>= clock
.m1
&& !IS_PINEVIEW(dev
))
674 for (clock
.n
= limit
->n
.min
;
675 clock
.n
<= limit
->n
.max
; clock
.n
++) {
676 for (clock
.p1
= limit
->p1
.min
;
677 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
680 intel_clock(dev
, refclk
, &clock
);
681 if (!intel_PLL_is_valid(dev
, limit
,
685 clock
.p
!= match_clock
->p
)
688 this_err
= abs(clock
.dot
- target
);
689 if (this_err
< err
) {
698 return (err
!= target
);
702 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
703 int target
, int refclk
, intel_clock_t
*match_clock
,
704 intel_clock_t
*best_clock
)
706 struct drm_device
*dev
= crtc
->dev
;
710 /* approximately equals target * 0.00585 */
711 int err_most
= (target
>> 8) + (target
>> 9);
714 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
717 if (HAS_PCH_SPLIT(dev
))
721 if (intel_is_dual_link_lvds(dev
))
722 clock
.p2
= limit
->p2
.p2_fast
;
724 clock
.p2
= limit
->p2
.p2_slow
;
726 if (target
< limit
->p2
.dot_limit
)
727 clock
.p2
= limit
->p2
.p2_slow
;
729 clock
.p2
= limit
->p2
.p2_fast
;
732 memset(best_clock
, 0, sizeof(*best_clock
));
733 max_n
= limit
->n
.max
;
734 /* based on hardware requirement, prefer smaller n to precision */
735 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
736 /* based on hardware requirement, prefere larger m1,m2 */
737 for (clock
.m1
= limit
->m1
.max
;
738 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
739 for (clock
.m2
= limit
->m2
.max
;
740 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
741 for (clock
.p1
= limit
->p1
.max
;
742 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
745 intel_clock(dev
, refclk
, &clock
);
746 if (!intel_PLL_is_valid(dev
, limit
,
750 clock
.p
!= match_clock
->p
)
753 this_err
= abs(clock
.dot
- target
);
754 if (this_err
< err_most
) {
768 intel_find_pll_ironlake_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
769 int target
, int refclk
, intel_clock_t
*match_clock
,
770 intel_clock_t
*best_clock
)
772 struct drm_device
*dev
= crtc
->dev
;
775 if (target
< 200000) {
788 intel_clock(dev
, refclk
, &clock
);
789 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
793 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
795 intel_find_pll_g4x_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
796 int target
, int refclk
, intel_clock_t
*match_clock
,
797 intel_clock_t
*best_clock
)
800 if (target
< 200000) {
813 clock
.m
= 5 * (clock
.m1
+ 2) + (clock
.m2
+ 2);
814 clock
.p
= (clock
.p1
* clock
.p2
);
815 clock
.dot
= 96000 * clock
.m
/ (clock
.n
+ 2) / clock
.p
;
817 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
821 intel_vlv_find_best_pll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
822 int target
, int refclk
, intel_clock_t
*match_clock
,
823 intel_clock_t
*best_clock
)
825 u32 p1
, p2
, m1
, m2
, vco
, bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
827 u32 updrate
, minupdate
, fracbits
, p
;
828 unsigned long bestppm
, ppm
, absppm
;
832 dotclk
= target
* 1000;
835 fastclk
= dotclk
/ (2*100);
839 n
= p
= p1
= p2
= m
= m1
= m2
= vco
= bestn
= 0;
840 bestm1
= bestm2
= bestp1
= bestp2
= 0;
842 /* based on hardware requirement, prefer smaller n to precision */
843 for (n
= limit
->n
.min
; n
<= ((refclk
) / minupdate
); n
++) {
844 updrate
= refclk
/ n
;
845 for (p1
= limit
->p1
.max
; p1
> limit
->p1
.min
; p1
--) {
846 for (p2
= limit
->p2
.p2_fast
+1; p2
> 0; p2
--) {
850 /* based on hardware requirement, prefer bigger m1,m2 values */
851 for (m1
= limit
->m1
.min
; m1
<= limit
->m1
.max
; m1
++) {
852 m2
= (((2*(fastclk
* p
* n
/ m1
)) +
853 refclk
) / (2*refclk
));
856 if (vco
>= limit
->vco
.min
&& vco
< limit
->vco
.max
) {
857 ppm
= 1000000 * ((vco
/ p
) - fastclk
) / fastclk
;
858 absppm
= (ppm
> 0) ? ppm
: (-ppm
);
859 if (absppm
< 100 && ((p1
* p2
) > (bestp1
* bestp2
))) {
863 if (absppm
< bestppm
- 10) {
880 best_clock
->n
= bestn
;
881 best_clock
->m1
= bestm1
;
882 best_clock
->m2
= bestm2
;
883 best_clock
->p1
= bestp1
;
884 best_clock
->p2
= bestp2
;
889 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
892 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
893 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
895 return intel_crtc
->cpu_transcoder
;
898 static void ironlake_wait_for_vblank(struct drm_device
*dev
, int pipe
)
900 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
901 u32 frame
, frame_reg
= PIPEFRAME(pipe
);
903 frame
= I915_READ(frame_reg
);
905 if (wait_for(I915_READ_NOTRACE(frame_reg
) != frame
, 50))
906 DRM_DEBUG_KMS("vblank wait timed out\n");
910 * intel_wait_for_vblank - wait for vblank on a given pipe
912 * @pipe: pipe to wait for
914 * Wait for vblank to occur on a given pipe. Needed for various bits of
917 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
919 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
920 int pipestat_reg
= PIPESTAT(pipe
);
922 if (INTEL_INFO(dev
)->gen
>= 5) {
923 ironlake_wait_for_vblank(dev
, pipe
);
927 /* Clear existing vblank status. Note this will clear any other
928 * sticky status fields as well.
930 * This races with i915_driver_irq_handler() with the result
931 * that either function could miss a vblank event. Here it is not
932 * fatal, as we will either wait upon the next vblank interrupt or
933 * timeout. Generally speaking intel_wait_for_vblank() is only
934 * called during modeset at which time the GPU should be idle and
935 * should *not* be performing page flips and thus not waiting on
937 * Currently, the result of us stealing a vblank from the irq
938 * handler is that a single frame will be skipped during swapbuffers.
940 I915_WRITE(pipestat_reg
,
941 I915_READ(pipestat_reg
) | PIPE_VBLANK_INTERRUPT_STATUS
);
943 /* Wait for vblank interrupt bit to set */
944 if (wait_for(I915_READ(pipestat_reg
) &
945 PIPE_VBLANK_INTERRUPT_STATUS
,
947 DRM_DEBUG_KMS("vblank wait timed out\n");
951 * intel_wait_for_pipe_off - wait for pipe to turn off
953 * @pipe: pipe to wait for
955 * After disabling a pipe, we can't wait for vblank in the usual way,
956 * spinning on the vblank interrupt status bit, since we won't actually
957 * see an interrupt when the pipe is disabled.
960 * wait for the pipe register state bit to turn off
963 * wait for the display line value to settle (it usually
964 * ends up stopping at the start of the next frame).
967 void intel_wait_for_pipe_off(struct drm_device
*dev
, int pipe
)
969 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
970 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
973 if (INTEL_INFO(dev
)->gen
>= 4) {
974 int reg
= PIPECONF(cpu_transcoder
);
976 /* Wait for the Pipe State to go off */
977 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
979 WARN(1, "pipe_off wait timed out\n");
981 u32 last_line
, line_mask
;
982 int reg
= PIPEDSL(pipe
);
983 unsigned long timeout
= jiffies
+ msecs_to_jiffies(100);
986 line_mask
= DSL_LINEMASK_GEN2
;
988 line_mask
= DSL_LINEMASK_GEN3
;
990 /* Wait for the display line to settle */
992 last_line
= I915_READ(reg
) & line_mask
;
994 } while (((I915_READ(reg
) & line_mask
) != last_line
) &&
995 time_after(timeout
, jiffies
));
996 if (time_after(jiffies
, timeout
))
997 WARN(1, "pipe_off wait timed out\n");
1002 * ibx_digital_port_connected - is the specified port connected?
1003 * @dev_priv: i915 private structure
1004 * @port: the port to test
1006 * Returns true if @port is connected, false otherwise.
1008 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
1009 struct intel_digital_port
*port
)
1013 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1014 switch(port
->port
) {
1016 bit
= SDE_PORTB_HOTPLUG
;
1019 bit
= SDE_PORTC_HOTPLUG
;
1022 bit
= SDE_PORTD_HOTPLUG
;
1028 switch(port
->port
) {
1030 bit
= SDE_PORTB_HOTPLUG_CPT
;
1033 bit
= SDE_PORTC_HOTPLUG_CPT
;
1036 bit
= SDE_PORTD_HOTPLUG_CPT
;
1043 return I915_READ(SDEISR
) & bit
;
1046 static const char *state_string(bool enabled
)
1048 return enabled
? "on" : "off";
1051 /* Only for pre-ILK configs */
1052 static void assert_pll(struct drm_i915_private
*dev_priv
,
1053 enum pipe pipe
, bool state
)
1060 val
= I915_READ(reg
);
1061 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1062 WARN(cur_state
!= state
,
1063 "PLL state assertion failure (expected %s, current %s)\n",
1064 state_string(state
), state_string(cur_state
));
1066 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1067 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1070 static void assert_pch_pll(struct drm_i915_private
*dev_priv
,
1071 struct intel_pch_pll
*pll
,
1072 struct intel_crtc
*crtc
,
1078 if (HAS_PCH_LPT(dev_priv
->dev
)) {
1079 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1084 "asserting PCH PLL %s with no PLL\n", state_string(state
)))
1087 val
= I915_READ(pll
->pll_reg
);
1088 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1089 WARN(cur_state
!= state
,
1090 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1091 pll
->pll_reg
, state_string(state
), state_string(cur_state
), val
);
1093 /* Make sure the selected PLL is correctly attached to the transcoder */
1094 if (crtc
&& HAS_PCH_CPT(dev_priv
->dev
)) {
1097 pch_dpll
= I915_READ(PCH_DPLL_SEL
);
1098 cur_state
= pll
->pll_reg
== _PCH_DPLL_B
;
1099 if (!WARN(((pch_dpll
>> (4 * crtc
->pipe
)) & 1) != cur_state
,
1100 "PLL[%d] not attached to this transcoder %d: %08x\n",
1101 cur_state
, crtc
->pipe
, pch_dpll
)) {
1102 cur_state
= !!(val
>> (4*crtc
->pipe
+ 3));
1103 WARN(cur_state
!= state
,
1104 "PLL[%d] not %s on this transcoder %d: %08x\n",
1105 pll
->pll_reg
== _PCH_DPLL_B
,
1106 state_string(state
),
1112 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1113 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1115 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1116 enum pipe pipe
, bool state
)
1121 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1124 if (HAS_DDI(dev_priv
->dev
)) {
1125 /* DDI does not have a specific FDI_TX register */
1126 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1127 val
= I915_READ(reg
);
1128 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1130 reg
= FDI_TX_CTL(pipe
);
1131 val
= I915_READ(reg
);
1132 cur_state
= !!(val
& FDI_TX_ENABLE
);
1134 WARN(cur_state
!= state
,
1135 "FDI TX state assertion failure (expected %s, current %s)\n",
1136 state_string(state
), state_string(cur_state
));
1138 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1139 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1141 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1142 enum pipe pipe
, bool state
)
1148 reg
= FDI_RX_CTL(pipe
);
1149 val
= I915_READ(reg
);
1150 cur_state
= !!(val
& FDI_RX_ENABLE
);
1151 WARN(cur_state
!= state
,
1152 "FDI RX state assertion failure (expected %s, current %s)\n",
1153 state_string(state
), state_string(cur_state
));
1155 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1156 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1158 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1164 /* ILK FDI PLL is always enabled */
1165 if (dev_priv
->info
->gen
== 5)
1168 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1169 if (HAS_DDI(dev_priv
->dev
))
1172 reg
= FDI_TX_CTL(pipe
);
1173 val
= I915_READ(reg
);
1174 WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1177 static void assert_fdi_rx_pll_enabled(struct drm_i915_private
*dev_priv
,
1183 reg
= FDI_RX_CTL(pipe
);
1184 val
= I915_READ(reg
);
1185 WARN(!(val
& FDI_RX_PLL_ENABLE
), "FDI RX PLL assertion failure, should be active but is disabled\n");
1188 static void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1191 int pp_reg
, lvds_reg
;
1193 enum pipe panel_pipe
= PIPE_A
;
1196 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
1197 pp_reg
= PCH_PP_CONTROL
;
1198 lvds_reg
= PCH_LVDS
;
1200 pp_reg
= PP_CONTROL
;
1204 val
= I915_READ(pp_reg
);
1205 if (!(val
& PANEL_POWER_ON
) ||
1206 ((val
& PANEL_UNLOCK_REGS
) == PANEL_UNLOCK_REGS
))
1209 if (I915_READ(lvds_reg
) & LVDS_PIPEB_SELECT
)
1210 panel_pipe
= PIPE_B
;
1212 WARN(panel_pipe
== pipe
&& locked
,
1213 "panel assertion failure, pipe %c regs locked\n",
1217 void assert_pipe(struct drm_i915_private
*dev_priv
,
1218 enum pipe pipe
, bool state
)
1223 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1226 /* if we need the pipe A quirk it must be always on */
1227 if (pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
1230 if (IS_HASWELL(dev_priv
->dev
) && cpu_transcoder
!= TRANSCODER_EDP
&&
1231 !(I915_READ(HSW_PWR_WELL_DRIVER
) & HSW_PWR_WELL_ENABLE
)) {
1234 reg
= PIPECONF(cpu_transcoder
);
1235 val
= I915_READ(reg
);
1236 cur_state
= !!(val
& PIPECONF_ENABLE
);
1239 WARN(cur_state
!= state
,
1240 "pipe %c assertion failure (expected %s, current %s)\n",
1241 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1244 static void assert_plane(struct drm_i915_private
*dev_priv
,
1245 enum plane plane
, bool state
)
1251 reg
= DSPCNTR(plane
);
1252 val
= I915_READ(reg
);
1253 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1254 WARN(cur_state
!= state
,
1255 "plane %c assertion failure (expected %s, current %s)\n",
1256 plane_name(plane
), state_string(state
), state_string(cur_state
));
1259 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1262 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1269 /* Planes are fixed to pipes on ILK+ */
1270 if (HAS_PCH_SPLIT(dev_priv
->dev
) || IS_VALLEYVIEW(dev_priv
->dev
)) {
1271 reg
= DSPCNTR(pipe
);
1272 val
= I915_READ(reg
);
1273 WARN((val
& DISPLAY_PLANE_ENABLE
),
1274 "plane %c assertion failure, should be disabled but not\n",
1279 /* Need to check both planes against the pipe */
1280 for (i
= 0; i
< 2; i
++) {
1282 val
= I915_READ(reg
);
1283 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1284 DISPPLANE_SEL_PIPE_SHIFT
;
1285 WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1286 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1287 plane_name(i
), pipe_name(pipe
));
1291 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1297 if (!IS_VALLEYVIEW(dev_priv
->dev
))
1300 /* Need to check both planes against the pipe */
1301 for (i
= 0; i
< dev_priv
->num_plane
; i
++) {
1302 reg
= SPCNTR(pipe
, i
);
1303 val
= I915_READ(reg
);
1304 WARN((val
& SP_ENABLE
),
1305 "sprite %d assertion failure, should be off on pipe %c but is still active\n",
1306 pipe
* 2 + i
, pipe_name(pipe
));
1310 static void assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1315 if (HAS_PCH_LPT(dev_priv
->dev
)) {
1316 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1320 val
= I915_READ(PCH_DREF_CONTROL
);
1321 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1322 DREF_SUPERSPREAD_SOURCE_MASK
));
1323 WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1326 static void assert_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1333 reg
= TRANSCONF(pipe
);
1334 val
= I915_READ(reg
);
1335 enabled
= !!(val
& TRANS_ENABLE
);
1337 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1341 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1342 enum pipe pipe
, u32 port_sel
, u32 val
)
1344 if ((val
& DP_PORT_EN
) == 0)
1347 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1348 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1349 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1350 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1353 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1359 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1360 enum pipe pipe
, u32 val
)
1362 if ((val
& SDVO_ENABLE
) == 0)
1365 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1366 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1369 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1375 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1376 enum pipe pipe
, u32 val
)
1378 if ((val
& LVDS_PORT_EN
) == 0)
1381 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1382 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1385 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1391 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1392 enum pipe pipe
, u32 val
)
1394 if ((val
& ADPA_DAC_ENABLE
) == 0)
1396 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1397 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1400 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1406 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1407 enum pipe pipe
, int reg
, u32 port_sel
)
1409 u32 val
= I915_READ(reg
);
1410 WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1411 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1412 reg
, pipe_name(pipe
));
1414 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1415 && (val
& DP_PIPEB_SELECT
),
1416 "IBX PCH dp port still using transcoder B\n");
1419 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1420 enum pipe pipe
, int reg
)
1422 u32 val
= I915_READ(reg
);
1423 WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1424 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1425 reg
, pipe_name(pipe
));
1427 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_ENABLE
) == 0
1428 && (val
& SDVO_PIPE_B_SELECT
),
1429 "IBX PCH hdmi port still using transcoder B\n");
1432 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1438 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1439 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1440 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1443 val
= I915_READ(reg
);
1444 WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1445 "PCH VGA enabled on transcoder %c, should be disabled\n",
1449 val
= I915_READ(reg
);
1450 WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1451 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1454 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1455 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1456 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1460 * intel_enable_pll - enable a PLL
1461 * @dev_priv: i915 private structure
1462 * @pipe: pipe PLL to enable
1464 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1465 * make sure the PLL reg is writable first though, since the panel write
1466 * protect mechanism may be enabled.
1468 * Note! This is for pre-ILK only.
1470 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1472 static void intel_enable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1477 /* No really, not for ILK+ */
1478 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
) && dev_priv
->info
->gen
>= 5);
1480 /* PLL is protected by panel, make sure we can write it */
1481 if (IS_MOBILE(dev_priv
->dev
) && !IS_I830(dev_priv
->dev
))
1482 assert_panel_unlocked(dev_priv
, pipe
);
1485 val
= I915_READ(reg
);
1486 val
|= DPLL_VCO_ENABLE
;
1488 /* We do this three times for luck */
1489 I915_WRITE(reg
, val
);
1491 udelay(150); /* wait for warmup */
1492 I915_WRITE(reg
, val
);
1494 udelay(150); /* wait for warmup */
1495 I915_WRITE(reg
, val
);
1497 udelay(150); /* wait for warmup */
1501 * intel_disable_pll - disable a PLL
1502 * @dev_priv: i915 private structure
1503 * @pipe: pipe PLL to disable
1505 * Disable the PLL for @pipe, making sure the pipe is off first.
1507 * Note! This is for pre-ILK only.
1509 static void intel_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1514 /* Don't disable pipe A or pipe A PLLs if needed */
1515 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1518 /* Make sure the pipe isn't still relying on us */
1519 assert_pipe_disabled(dev_priv
, pipe
);
1522 val
= I915_READ(reg
);
1523 val
&= ~DPLL_VCO_ENABLE
;
1524 I915_WRITE(reg
, val
);
1530 intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
1531 enum intel_sbi_destination destination
)
1535 WARN_ON(!mutex_is_locked(&dev_priv
->dpio_lock
));
1537 if (wait_for((I915_READ(SBI_CTL_STAT
) & SBI_BUSY
) == 0,
1539 DRM_ERROR("timeout waiting for SBI to become ready\n");
1543 I915_WRITE(SBI_ADDR
, (reg
<< 16));
1544 I915_WRITE(SBI_DATA
, value
);
1546 if (destination
== SBI_ICLK
)
1547 tmp
= SBI_CTL_DEST_ICLK
| SBI_CTL_OP_CRWR
;
1549 tmp
= SBI_CTL_DEST_MPHY
| SBI_CTL_OP_IOWR
;
1550 I915_WRITE(SBI_CTL_STAT
, SBI_BUSY
| tmp
);
1552 if (wait_for((I915_READ(SBI_CTL_STAT
) & (SBI_BUSY
| SBI_RESPONSE_FAIL
)) == 0,
1554 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1560 intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
1561 enum intel_sbi_destination destination
)
1564 WARN_ON(!mutex_is_locked(&dev_priv
->dpio_lock
));
1566 if (wait_for((I915_READ(SBI_CTL_STAT
) & SBI_BUSY
) == 0,
1568 DRM_ERROR("timeout waiting for SBI to become ready\n");
1572 I915_WRITE(SBI_ADDR
, (reg
<< 16));
1574 if (destination
== SBI_ICLK
)
1575 value
= SBI_CTL_DEST_ICLK
| SBI_CTL_OP_CRRD
;
1577 value
= SBI_CTL_DEST_MPHY
| SBI_CTL_OP_IORD
;
1578 I915_WRITE(SBI_CTL_STAT
, value
| SBI_BUSY
);
1580 if (wait_for((I915_READ(SBI_CTL_STAT
) & (SBI_BUSY
| SBI_RESPONSE_FAIL
)) == 0,
1582 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1586 return I915_READ(SBI_DATA
);
1590 * ironlake_enable_pch_pll - enable PCH PLL
1591 * @dev_priv: i915 private structure
1592 * @pipe: pipe PLL to enable
1594 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1595 * drives the transcoder clock.
1597 static void ironlake_enable_pch_pll(struct intel_crtc
*intel_crtc
)
1599 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
1600 struct intel_pch_pll
*pll
;
1604 /* PCH PLLs only available on ILK, SNB and IVB */
1605 BUG_ON(dev_priv
->info
->gen
< 5);
1606 pll
= intel_crtc
->pch_pll
;
1610 if (WARN_ON(pll
->refcount
== 0))
1613 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1614 pll
->pll_reg
, pll
->active
, pll
->on
,
1615 intel_crtc
->base
.base
.id
);
1617 /* PCH refclock must be enabled first */
1618 assert_pch_refclk_enabled(dev_priv
);
1620 if (pll
->active
++ && pll
->on
) {
1621 assert_pch_pll_enabled(dev_priv
, pll
, NULL
);
1625 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll
->pll_reg
);
1628 val
= I915_READ(reg
);
1629 val
|= DPLL_VCO_ENABLE
;
1630 I915_WRITE(reg
, val
);
1637 static void intel_disable_pch_pll(struct intel_crtc
*intel_crtc
)
1639 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
1640 struct intel_pch_pll
*pll
= intel_crtc
->pch_pll
;
1644 /* PCH only available on ILK+ */
1645 BUG_ON(dev_priv
->info
->gen
< 5);
1649 if (WARN_ON(pll
->refcount
== 0))
1652 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1653 pll
->pll_reg
, pll
->active
, pll
->on
,
1654 intel_crtc
->base
.base
.id
);
1656 if (WARN_ON(pll
->active
== 0)) {
1657 assert_pch_pll_disabled(dev_priv
, pll
, NULL
);
1661 if (--pll
->active
) {
1662 assert_pch_pll_enabled(dev_priv
, pll
, NULL
);
1666 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll
->pll_reg
);
1668 /* Make sure transcoder isn't still depending on us */
1669 assert_transcoder_disabled(dev_priv
, intel_crtc
->pipe
);
1672 val
= I915_READ(reg
);
1673 val
&= ~DPLL_VCO_ENABLE
;
1674 I915_WRITE(reg
, val
);
1681 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1684 struct drm_device
*dev
= dev_priv
->dev
;
1685 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1686 uint32_t reg
, val
, pipeconf_val
;
1688 /* PCH only available on ILK+ */
1689 BUG_ON(dev_priv
->info
->gen
< 5);
1691 /* Make sure PCH DPLL is enabled */
1692 assert_pch_pll_enabled(dev_priv
,
1693 to_intel_crtc(crtc
)->pch_pll
,
1694 to_intel_crtc(crtc
));
1696 /* FDI must be feeding us bits for PCH ports */
1697 assert_fdi_tx_enabled(dev_priv
, pipe
);
1698 assert_fdi_rx_enabled(dev_priv
, pipe
);
1700 if (HAS_PCH_CPT(dev
)) {
1701 /* Workaround: Set the timing override bit before enabling the
1702 * pch transcoder. */
1703 reg
= TRANS_CHICKEN2(pipe
);
1704 val
= I915_READ(reg
);
1705 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1706 I915_WRITE(reg
, val
);
1709 reg
= TRANSCONF(pipe
);
1710 val
= I915_READ(reg
);
1711 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1713 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1715 * make the BPC in transcoder be consistent with
1716 * that in pipeconf reg.
1718 val
&= ~PIPECONF_BPC_MASK
;
1719 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1722 val
&= ~TRANS_INTERLACE_MASK
;
1723 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1724 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1725 intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
))
1726 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1728 val
|= TRANS_INTERLACED
;
1730 val
|= TRANS_PROGRESSIVE
;
1732 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1733 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1734 DRM_ERROR("failed to enable transcoder %d\n", pipe
);
1737 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1738 enum transcoder cpu_transcoder
)
1740 u32 val
, pipeconf_val
;
1742 /* PCH only available on ILK+ */
1743 BUG_ON(dev_priv
->info
->gen
< 5);
1745 /* FDI must be feeding us bits for PCH ports */
1746 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1747 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
1749 /* Workaround: set timing override bit. */
1750 val
= I915_READ(_TRANSA_CHICKEN2
);
1751 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1752 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1755 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1757 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1758 PIPECONF_INTERLACED_ILK
)
1759 val
|= TRANS_INTERLACED
;
1761 val
|= TRANS_PROGRESSIVE
;
1763 I915_WRITE(TRANSCONF(TRANSCODER_A
), val
);
1764 if (wait_for(I915_READ(_TRANSACONF
) & TRANS_STATE_ENABLE
, 100))
1765 DRM_ERROR("Failed to enable PCH transcoder\n");
1768 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1771 struct drm_device
*dev
= dev_priv
->dev
;
1774 /* FDI relies on the transcoder */
1775 assert_fdi_tx_disabled(dev_priv
, pipe
);
1776 assert_fdi_rx_disabled(dev_priv
, pipe
);
1778 /* Ports must be off as well */
1779 assert_pch_ports_disabled(dev_priv
, pipe
);
1781 reg
= TRANSCONF(pipe
);
1782 val
= I915_READ(reg
);
1783 val
&= ~TRANS_ENABLE
;
1784 I915_WRITE(reg
, val
);
1785 /* wait for PCH transcoder off, transcoder state */
1786 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1787 DRM_ERROR("failed to disable transcoder %d\n", pipe
);
1789 if (!HAS_PCH_IBX(dev
)) {
1790 /* Workaround: Clear the timing override chicken bit again. */
1791 reg
= TRANS_CHICKEN2(pipe
);
1792 val
= I915_READ(reg
);
1793 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1794 I915_WRITE(reg
, val
);
1798 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1802 val
= I915_READ(_TRANSACONF
);
1803 val
&= ~TRANS_ENABLE
;
1804 I915_WRITE(_TRANSACONF
, val
);
1805 /* wait for PCH transcoder off, transcoder state */
1806 if (wait_for((I915_READ(_TRANSACONF
) & TRANS_STATE_ENABLE
) == 0, 50))
1807 DRM_ERROR("Failed to disable PCH transcoder\n");
1809 /* Workaround: clear timing override bit. */
1810 val
= I915_READ(_TRANSA_CHICKEN2
);
1811 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1812 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1816 * intel_enable_pipe - enable a pipe, asserting requirements
1817 * @dev_priv: i915 private structure
1818 * @pipe: pipe to enable
1819 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1821 * Enable @pipe, making sure that various hardware specific requirements
1822 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1824 * @pipe should be %PIPE_A or %PIPE_B.
1826 * Will wait until the pipe is actually running (i.e. first vblank) before
1829 static void intel_enable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
1832 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1834 enum pipe pch_transcoder
;
1838 if (HAS_PCH_LPT(dev_priv
->dev
))
1839 pch_transcoder
= TRANSCODER_A
;
1841 pch_transcoder
= pipe
;
1844 * A pipe without a PLL won't actually be able to drive bits from
1845 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1848 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
1849 assert_pll_enabled(dev_priv
, pipe
);
1852 /* if driving the PCH, we need FDI enabled */
1853 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
1854 assert_fdi_tx_pll_enabled(dev_priv
,
1855 (enum pipe
) cpu_transcoder
);
1857 /* FIXME: assert CPU port conditions for SNB+ */
1860 reg
= PIPECONF(cpu_transcoder
);
1861 val
= I915_READ(reg
);
1862 if (val
& PIPECONF_ENABLE
)
1865 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
1866 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1870 * intel_disable_pipe - disable a pipe, asserting requirements
1871 * @dev_priv: i915 private structure
1872 * @pipe: pipe to disable
1874 * Disable @pipe, making sure that various hardware specific requirements
1875 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1877 * @pipe should be %PIPE_A or %PIPE_B.
1879 * Will wait until the pipe has shut down before returning.
1881 static void intel_disable_pipe(struct drm_i915_private
*dev_priv
,
1884 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1890 * Make sure planes won't keep trying to pump pixels to us,
1891 * or we might hang the display.
1893 assert_planes_disabled(dev_priv
, pipe
);
1894 assert_sprites_disabled(dev_priv
, pipe
);
1896 /* Don't disable pipe A or pipe A PLLs if needed */
1897 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1900 reg
= PIPECONF(cpu_transcoder
);
1901 val
= I915_READ(reg
);
1902 if ((val
& PIPECONF_ENABLE
) == 0)
1905 I915_WRITE(reg
, val
& ~PIPECONF_ENABLE
);
1906 intel_wait_for_pipe_off(dev_priv
->dev
, pipe
);
1910 * Plane regs are double buffered, going from enabled->disabled needs a
1911 * trigger in order to latch. The display address reg provides this.
1913 void intel_flush_display_plane(struct drm_i915_private
*dev_priv
,
1916 if (dev_priv
->info
->gen
>= 4)
1917 I915_WRITE(DSPSURF(plane
), I915_READ(DSPSURF(plane
)));
1919 I915_WRITE(DSPADDR(plane
), I915_READ(DSPADDR(plane
)));
1923 * intel_enable_plane - enable a display plane on a given pipe
1924 * @dev_priv: i915 private structure
1925 * @plane: plane to enable
1926 * @pipe: pipe being fed
1928 * Enable @plane on @pipe, making sure that @pipe is running first.
1930 static void intel_enable_plane(struct drm_i915_private
*dev_priv
,
1931 enum plane plane
, enum pipe pipe
)
1936 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1937 assert_pipe_enabled(dev_priv
, pipe
);
1939 reg
= DSPCNTR(plane
);
1940 val
= I915_READ(reg
);
1941 if (val
& DISPLAY_PLANE_ENABLE
)
1944 I915_WRITE(reg
, val
| DISPLAY_PLANE_ENABLE
);
1945 intel_flush_display_plane(dev_priv
, plane
);
1946 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1950 * intel_disable_plane - disable a display plane
1951 * @dev_priv: i915 private structure
1952 * @plane: plane to disable
1953 * @pipe: pipe consuming the data
1955 * Disable @plane; should be an independent operation.
1957 static void intel_disable_plane(struct drm_i915_private
*dev_priv
,
1958 enum plane plane
, enum pipe pipe
)
1963 reg
= DSPCNTR(plane
);
1964 val
= I915_READ(reg
);
1965 if ((val
& DISPLAY_PLANE_ENABLE
) == 0)
1968 I915_WRITE(reg
, val
& ~DISPLAY_PLANE_ENABLE
);
1969 intel_flush_display_plane(dev_priv
, plane
);
1970 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1973 static bool need_vtd_wa(struct drm_device
*dev
)
1975 #ifdef CONFIG_INTEL_IOMMU
1976 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
1983 intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
1984 struct drm_i915_gem_object
*obj
,
1985 struct intel_ring_buffer
*pipelined
)
1987 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1991 switch (obj
->tiling_mode
) {
1992 case I915_TILING_NONE
:
1993 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
1994 alignment
= 128 * 1024;
1995 else if (INTEL_INFO(dev
)->gen
>= 4)
1996 alignment
= 4 * 1024;
1998 alignment
= 64 * 1024;
2001 /* pin() will align the object as required by fence */
2005 /* FIXME: Is this true? */
2006 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
2012 /* Note that the w/a also requires 64 PTE of padding following the
2013 * bo. We currently fill all unused PTE with the shadow page and so
2014 * we should always have valid PTE following the scanout preventing
2017 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
2018 alignment
= 256 * 1024;
2020 dev_priv
->mm
.interruptible
= false;
2021 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
);
2023 goto err_interruptible
;
2025 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2026 * fence, whereas 965+ only requires a fence if using
2027 * framebuffer compression. For simplicity, we always install
2028 * a fence as the cost is not that onerous.
2030 ret
= i915_gem_object_get_fence(obj
);
2034 i915_gem_object_pin_fence(obj
);
2036 dev_priv
->mm
.interruptible
= true;
2040 i915_gem_object_unpin(obj
);
2042 dev_priv
->mm
.interruptible
= true;
2046 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
)
2048 i915_gem_object_unpin_fence(obj
);
2049 i915_gem_object_unpin(obj
);
2052 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2053 * is assumed to be a power-of-two. */
2054 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
2055 unsigned int tiling_mode
,
2059 if (tiling_mode
!= I915_TILING_NONE
) {
2060 unsigned int tile_rows
, tiles
;
2065 tiles
= *x
/ (512/cpp
);
2068 return tile_rows
* pitch
* 8 + tiles
* 4096;
2070 unsigned int offset
;
2072 offset
= *y
* pitch
+ *x
* cpp
;
2074 *x
= (offset
& 4095) / cpp
;
2075 return offset
& -4096;
2079 static int i9xx_update_plane(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2082 struct drm_device
*dev
= crtc
->dev
;
2083 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2084 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2085 struct intel_framebuffer
*intel_fb
;
2086 struct drm_i915_gem_object
*obj
;
2087 int plane
= intel_crtc
->plane
;
2088 unsigned long linear_offset
;
2097 DRM_ERROR("Can't update plane %d in SAREA\n", plane
);
2101 intel_fb
= to_intel_framebuffer(fb
);
2102 obj
= intel_fb
->obj
;
2104 reg
= DSPCNTR(plane
);
2105 dspcntr
= I915_READ(reg
);
2106 /* Mask out pixel format bits in case we change it */
2107 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2108 switch (fb
->pixel_format
) {
2110 dspcntr
|= DISPPLANE_8BPP
;
2112 case DRM_FORMAT_XRGB1555
:
2113 case DRM_FORMAT_ARGB1555
:
2114 dspcntr
|= DISPPLANE_BGRX555
;
2116 case DRM_FORMAT_RGB565
:
2117 dspcntr
|= DISPPLANE_BGRX565
;
2119 case DRM_FORMAT_XRGB8888
:
2120 case DRM_FORMAT_ARGB8888
:
2121 dspcntr
|= DISPPLANE_BGRX888
;
2123 case DRM_FORMAT_XBGR8888
:
2124 case DRM_FORMAT_ABGR8888
:
2125 dspcntr
|= DISPPLANE_RGBX888
;
2127 case DRM_FORMAT_XRGB2101010
:
2128 case DRM_FORMAT_ARGB2101010
:
2129 dspcntr
|= DISPPLANE_BGRX101010
;
2131 case DRM_FORMAT_XBGR2101010
:
2132 case DRM_FORMAT_ABGR2101010
:
2133 dspcntr
|= DISPPLANE_RGBX101010
;
2139 if (INTEL_INFO(dev
)->gen
>= 4) {
2140 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2141 dspcntr
|= DISPPLANE_TILED
;
2143 dspcntr
&= ~DISPPLANE_TILED
;
2146 I915_WRITE(reg
, dspcntr
);
2148 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2150 if (INTEL_INFO(dev
)->gen
>= 4) {
2151 intel_crtc
->dspaddr_offset
=
2152 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2153 fb
->bits_per_pixel
/ 8,
2155 linear_offset
-= intel_crtc
->dspaddr_offset
;
2157 intel_crtc
->dspaddr_offset
= linear_offset
;
2160 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2161 obj
->gtt_offset
, linear_offset
, x
, y
, fb
->pitches
[0]);
2162 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2163 if (INTEL_INFO(dev
)->gen
>= 4) {
2164 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2165 obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
2166 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2167 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2169 I915_WRITE(DSPADDR(plane
), obj
->gtt_offset
+ linear_offset
);
2175 static int ironlake_update_plane(struct drm_crtc
*crtc
,
2176 struct drm_framebuffer
*fb
, int x
, int y
)
2178 struct drm_device
*dev
= crtc
->dev
;
2179 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2180 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2181 struct intel_framebuffer
*intel_fb
;
2182 struct drm_i915_gem_object
*obj
;
2183 int plane
= intel_crtc
->plane
;
2184 unsigned long linear_offset
;
2194 DRM_ERROR("Can't update plane %d in SAREA\n", plane
);
2198 intel_fb
= to_intel_framebuffer(fb
);
2199 obj
= intel_fb
->obj
;
2201 reg
= DSPCNTR(plane
);
2202 dspcntr
= I915_READ(reg
);
2203 /* Mask out pixel format bits in case we change it */
2204 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2205 switch (fb
->pixel_format
) {
2207 dspcntr
|= DISPPLANE_8BPP
;
2209 case DRM_FORMAT_RGB565
:
2210 dspcntr
|= DISPPLANE_BGRX565
;
2212 case DRM_FORMAT_XRGB8888
:
2213 case DRM_FORMAT_ARGB8888
:
2214 dspcntr
|= DISPPLANE_BGRX888
;
2216 case DRM_FORMAT_XBGR8888
:
2217 case DRM_FORMAT_ABGR8888
:
2218 dspcntr
|= DISPPLANE_RGBX888
;
2220 case DRM_FORMAT_XRGB2101010
:
2221 case DRM_FORMAT_ARGB2101010
:
2222 dspcntr
|= DISPPLANE_BGRX101010
;
2224 case DRM_FORMAT_XBGR2101010
:
2225 case DRM_FORMAT_ABGR2101010
:
2226 dspcntr
|= DISPPLANE_RGBX101010
;
2232 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2233 dspcntr
|= DISPPLANE_TILED
;
2235 dspcntr
&= ~DISPPLANE_TILED
;
2238 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2240 I915_WRITE(reg
, dspcntr
);
2242 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2243 intel_crtc
->dspaddr_offset
=
2244 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2245 fb
->bits_per_pixel
/ 8,
2247 linear_offset
-= intel_crtc
->dspaddr_offset
;
2249 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2250 obj
->gtt_offset
, linear_offset
, x
, y
, fb
->pitches
[0]);
2251 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2252 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2253 obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
2254 if (IS_HASWELL(dev
)) {
2255 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2257 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2258 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2265 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2267 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2268 int x
, int y
, enum mode_set_atomic state
)
2270 struct drm_device
*dev
= crtc
->dev
;
2271 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2273 if (dev_priv
->display
.disable_fbc
)
2274 dev_priv
->display
.disable_fbc(dev
);
2275 intel_increase_pllclock(crtc
);
2277 return dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2280 void intel_display_handle_reset(struct drm_device
*dev
)
2282 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2283 struct drm_crtc
*crtc
;
2286 * Flips in the rings have been nuked by the reset,
2287 * so complete all pending flips so that user space
2288 * will get its events and not get stuck.
2290 * Also update the base address of all primary
2291 * planes to the the last fb to make sure we're
2292 * showing the correct fb after a reset.
2294 * Need to make two loops over the crtcs so that we
2295 * don't try to grab a crtc mutex before the
2296 * pending_flip_queue really got woken up.
2299 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2300 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2301 enum plane plane
= intel_crtc
->plane
;
2303 intel_prepare_page_flip(dev
, plane
);
2304 intel_finish_page_flip_plane(dev
, plane
);
2307 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2308 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2310 mutex_lock(&crtc
->mutex
);
2311 if (intel_crtc
->active
)
2312 dev_priv
->display
.update_plane(crtc
, crtc
->fb
,
2314 mutex_unlock(&crtc
->mutex
);
2319 intel_finish_fb(struct drm_framebuffer
*old_fb
)
2321 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(old_fb
)->obj
;
2322 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2323 bool was_interruptible
= dev_priv
->mm
.interruptible
;
2326 /* Big Hammer, we also need to ensure that any pending
2327 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2328 * current scanout is retired before unpinning the old
2331 * This should only fail upon a hung GPU, in which case we
2332 * can safely continue.
2334 dev_priv
->mm
.interruptible
= false;
2335 ret
= i915_gem_object_finish_gpu(obj
);
2336 dev_priv
->mm
.interruptible
= was_interruptible
;
2341 static void intel_crtc_update_sarea_pos(struct drm_crtc
*crtc
, int x
, int y
)
2343 struct drm_device
*dev
= crtc
->dev
;
2344 struct drm_i915_master_private
*master_priv
;
2345 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2347 if (!dev
->primary
->master
)
2350 master_priv
= dev
->primary
->master
->driver_priv
;
2351 if (!master_priv
->sarea_priv
)
2354 switch (intel_crtc
->pipe
) {
2356 master_priv
->sarea_priv
->pipeA_x
= x
;
2357 master_priv
->sarea_priv
->pipeA_y
= y
;
2360 master_priv
->sarea_priv
->pipeB_x
= x
;
2361 master_priv
->sarea_priv
->pipeB_y
= y
;
2369 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2370 struct drm_framebuffer
*fb
)
2372 struct drm_device
*dev
= crtc
->dev
;
2373 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2374 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2375 struct drm_framebuffer
*old_fb
;
2380 DRM_ERROR("No FB bound\n");
2384 if (intel_crtc
->plane
> INTEL_INFO(dev
)->num_pipes
) {
2385 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2387 INTEL_INFO(dev
)->num_pipes
);
2391 mutex_lock(&dev
->struct_mutex
);
2392 ret
= intel_pin_and_fence_fb_obj(dev
,
2393 to_intel_framebuffer(fb
)->obj
,
2396 mutex_unlock(&dev
->struct_mutex
);
2397 DRM_ERROR("pin & fence failed\n");
2401 ret
= dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2403 intel_unpin_fb_obj(to_intel_framebuffer(fb
)->obj
);
2404 mutex_unlock(&dev
->struct_mutex
);
2405 DRM_ERROR("failed to update base address\n");
2415 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2416 intel_unpin_fb_obj(to_intel_framebuffer(old_fb
)->obj
);
2419 intel_update_fbc(dev
);
2420 mutex_unlock(&dev
->struct_mutex
);
2422 intel_crtc_update_sarea_pos(crtc
, x
, y
);
2427 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
2429 struct drm_device
*dev
= crtc
->dev
;
2430 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2431 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2432 int pipe
= intel_crtc
->pipe
;
2435 /* enable normal train */
2436 reg
= FDI_TX_CTL(pipe
);
2437 temp
= I915_READ(reg
);
2438 if (IS_IVYBRIDGE(dev
)) {
2439 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2440 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2442 temp
&= ~FDI_LINK_TRAIN_NONE
;
2443 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2445 I915_WRITE(reg
, temp
);
2447 reg
= FDI_RX_CTL(pipe
);
2448 temp
= I915_READ(reg
);
2449 if (HAS_PCH_CPT(dev
)) {
2450 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2451 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2453 temp
&= ~FDI_LINK_TRAIN_NONE
;
2454 temp
|= FDI_LINK_TRAIN_NONE
;
2456 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2458 /* wait one idle pattern time */
2462 /* IVB wants error correction enabled */
2463 if (IS_IVYBRIDGE(dev
))
2464 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
2465 FDI_FE_ERRC_ENABLE
);
2468 static void ivb_modeset_global_resources(struct drm_device
*dev
)
2470 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2471 struct intel_crtc
*pipe_B_crtc
=
2472 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
2473 struct intel_crtc
*pipe_C_crtc
=
2474 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]);
2477 /* When everything is off disable fdi C so that we could enable fdi B
2478 * with all lanes. XXX: This misses the case where a pipe is not using
2479 * any pch resources and so doesn't need any fdi lanes. */
2480 if (!pipe_B_crtc
->base
.enabled
&& !pipe_C_crtc
->base
.enabled
) {
2481 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
2482 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
2484 temp
= I915_READ(SOUTH_CHICKEN1
);
2485 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
2486 DRM_DEBUG_KMS("disabling fdi C rx\n");
2487 I915_WRITE(SOUTH_CHICKEN1
, temp
);
2491 /* The FDI link training functions for ILK/Ibexpeak. */
2492 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
2494 struct drm_device
*dev
= crtc
->dev
;
2495 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2496 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2497 int pipe
= intel_crtc
->pipe
;
2498 int plane
= intel_crtc
->plane
;
2499 u32 reg
, temp
, tries
;
2501 /* FDI needs bits from pipe & plane first */
2502 assert_pipe_enabled(dev_priv
, pipe
);
2503 assert_plane_enabled(dev_priv
, plane
);
2505 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2507 reg
= FDI_RX_IMR(pipe
);
2508 temp
= I915_READ(reg
);
2509 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2510 temp
&= ~FDI_RX_BIT_LOCK
;
2511 I915_WRITE(reg
, temp
);
2515 /* enable CPU FDI TX and PCH FDI RX */
2516 reg
= FDI_TX_CTL(pipe
);
2517 temp
= I915_READ(reg
);
2519 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2520 temp
&= ~FDI_LINK_TRAIN_NONE
;
2521 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2522 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2524 reg
= FDI_RX_CTL(pipe
);
2525 temp
= I915_READ(reg
);
2526 temp
&= ~FDI_LINK_TRAIN_NONE
;
2527 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2528 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2533 /* Ironlake workaround, enable clock pointer after FDI enable*/
2534 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2535 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
2536 FDI_RX_PHASE_SYNC_POINTER_EN
);
2538 reg
= FDI_RX_IIR(pipe
);
2539 for (tries
= 0; tries
< 5; tries
++) {
2540 temp
= I915_READ(reg
);
2541 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2543 if ((temp
& FDI_RX_BIT_LOCK
)) {
2544 DRM_DEBUG_KMS("FDI train 1 done.\n");
2545 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2550 DRM_ERROR("FDI train 1 fail!\n");
2553 reg
= FDI_TX_CTL(pipe
);
2554 temp
= I915_READ(reg
);
2555 temp
&= ~FDI_LINK_TRAIN_NONE
;
2556 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2557 I915_WRITE(reg
, temp
);
2559 reg
= FDI_RX_CTL(pipe
);
2560 temp
= I915_READ(reg
);
2561 temp
&= ~FDI_LINK_TRAIN_NONE
;
2562 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2563 I915_WRITE(reg
, temp
);
2568 reg
= FDI_RX_IIR(pipe
);
2569 for (tries
= 0; tries
< 5; tries
++) {
2570 temp
= I915_READ(reg
);
2571 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2573 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2574 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2575 DRM_DEBUG_KMS("FDI train 2 done.\n");
2580 DRM_ERROR("FDI train 2 fail!\n");
2582 DRM_DEBUG_KMS("FDI train done\n");
2586 static const int snb_b_fdi_train_param
[] = {
2587 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
2588 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
2589 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
2590 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
2593 /* The FDI link training functions for SNB/Cougarpoint. */
2594 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
2596 struct drm_device
*dev
= crtc
->dev
;
2597 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2598 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2599 int pipe
= intel_crtc
->pipe
;
2600 u32 reg
, temp
, i
, retry
;
2602 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2604 reg
= FDI_RX_IMR(pipe
);
2605 temp
= I915_READ(reg
);
2606 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2607 temp
&= ~FDI_RX_BIT_LOCK
;
2608 I915_WRITE(reg
, temp
);
2613 /* enable CPU FDI TX and PCH FDI RX */
2614 reg
= FDI_TX_CTL(pipe
);
2615 temp
= I915_READ(reg
);
2617 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2618 temp
&= ~FDI_LINK_TRAIN_NONE
;
2619 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2620 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2622 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2623 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2625 I915_WRITE(FDI_RX_MISC(pipe
),
2626 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2628 reg
= FDI_RX_CTL(pipe
);
2629 temp
= I915_READ(reg
);
2630 if (HAS_PCH_CPT(dev
)) {
2631 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2632 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2634 temp
&= ~FDI_LINK_TRAIN_NONE
;
2635 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2637 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2642 for (i
= 0; i
< 4; i
++) {
2643 reg
= FDI_TX_CTL(pipe
);
2644 temp
= I915_READ(reg
);
2645 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2646 temp
|= snb_b_fdi_train_param
[i
];
2647 I915_WRITE(reg
, temp
);
2652 for (retry
= 0; retry
< 5; retry
++) {
2653 reg
= FDI_RX_IIR(pipe
);
2654 temp
= I915_READ(reg
);
2655 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2656 if (temp
& FDI_RX_BIT_LOCK
) {
2657 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2658 DRM_DEBUG_KMS("FDI train 1 done.\n");
2667 DRM_ERROR("FDI train 1 fail!\n");
2670 reg
= FDI_TX_CTL(pipe
);
2671 temp
= I915_READ(reg
);
2672 temp
&= ~FDI_LINK_TRAIN_NONE
;
2673 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2675 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2677 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2679 I915_WRITE(reg
, temp
);
2681 reg
= FDI_RX_CTL(pipe
);
2682 temp
= I915_READ(reg
);
2683 if (HAS_PCH_CPT(dev
)) {
2684 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2685 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2687 temp
&= ~FDI_LINK_TRAIN_NONE
;
2688 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2690 I915_WRITE(reg
, temp
);
2695 for (i
= 0; i
< 4; i
++) {
2696 reg
= FDI_TX_CTL(pipe
);
2697 temp
= I915_READ(reg
);
2698 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2699 temp
|= snb_b_fdi_train_param
[i
];
2700 I915_WRITE(reg
, temp
);
2705 for (retry
= 0; retry
< 5; retry
++) {
2706 reg
= FDI_RX_IIR(pipe
);
2707 temp
= I915_READ(reg
);
2708 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2709 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2710 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2711 DRM_DEBUG_KMS("FDI train 2 done.\n");
2720 DRM_ERROR("FDI train 2 fail!\n");
2722 DRM_DEBUG_KMS("FDI train done.\n");
2725 /* Manual link training for Ivy Bridge A0 parts */
2726 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
2728 struct drm_device
*dev
= crtc
->dev
;
2729 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2730 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2731 int pipe
= intel_crtc
->pipe
;
2734 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2736 reg
= FDI_RX_IMR(pipe
);
2737 temp
= I915_READ(reg
);
2738 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2739 temp
&= ~FDI_RX_BIT_LOCK
;
2740 I915_WRITE(reg
, temp
);
2745 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2746 I915_READ(FDI_RX_IIR(pipe
)));
2748 /* enable CPU FDI TX and PCH FDI RX */
2749 reg
= FDI_TX_CTL(pipe
);
2750 temp
= I915_READ(reg
);
2752 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2753 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
2754 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
2755 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2756 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2757 temp
|= FDI_COMPOSITE_SYNC
;
2758 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2760 I915_WRITE(FDI_RX_MISC(pipe
),
2761 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2763 reg
= FDI_RX_CTL(pipe
);
2764 temp
= I915_READ(reg
);
2765 temp
&= ~FDI_LINK_TRAIN_AUTO
;
2766 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2767 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2768 temp
|= FDI_COMPOSITE_SYNC
;
2769 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2774 for (i
= 0; i
< 4; i
++) {
2775 reg
= FDI_TX_CTL(pipe
);
2776 temp
= I915_READ(reg
);
2777 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2778 temp
|= snb_b_fdi_train_param
[i
];
2779 I915_WRITE(reg
, temp
);
2784 reg
= FDI_RX_IIR(pipe
);
2785 temp
= I915_READ(reg
);
2786 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2788 if (temp
& FDI_RX_BIT_LOCK
||
2789 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
2790 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2791 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i
);
2796 DRM_ERROR("FDI train 1 fail!\n");
2799 reg
= FDI_TX_CTL(pipe
);
2800 temp
= I915_READ(reg
);
2801 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2802 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
2803 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2804 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2805 I915_WRITE(reg
, temp
);
2807 reg
= FDI_RX_CTL(pipe
);
2808 temp
= I915_READ(reg
);
2809 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2810 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2811 I915_WRITE(reg
, temp
);
2816 for (i
= 0; i
< 4; i
++) {
2817 reg
= FDI_TX_CTL(pipe
);
2818 temp
= I915_READ(reg
);
2819 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2820 temp
|= snb_b_fdi_train_param
[i
];
2821 I915_WRITE(reg
, temp
);
2826 reg
= FDI_RX_IIR(pipe
);
2827 temp
= I915_READ(reg
);
2828 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2830 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2831 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2832 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i
);
2837 DRM_ERROR("FDI train 2 fail!\n");
2839 DRM_DEBUG_KMS("FDI train done.\n");
2842 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
2844 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2845 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2846 int pipe
= intel_crtc
->pipe
;
2850 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2851 reg
= FDI_RX_CTL(pipe
);
2852 temp
= I915_READ(reg
);
2853 temp
&= ~((0x7 << 19) | (0x7 << 16));
2854 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2855 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2856 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
2861 /* Switch from Rawclk to PCDclk */
2862 temp
= I915_READ(reg
);
2863 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
2868 /* Enable CPU FDI TX PLL, always on for Ironlake */
2869 reg
= FDI_TX_CTL(pipe
);
2870 temp
= I915_READ(reg
);
2871 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
2872 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
2879 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
2881 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2882 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2883 int pipe
= intel_crtc
->pipe
;
2886 /* Switch from PCDclk to Rawclk */
2887 reg
= FDI_RX_CTL(pipe
);
2888 temp
= I915_READ(reg
);
2889 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
2891 /* Disable CPU FDI TX PLL */
2892 reg
= FDI_TX_CTL(pipe
);
2893 temp
= I915_READ(reg
);
2894 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
2899 reg
= FDI_RX_CTL(pipe
);
2900 temp
= I915_READ(reg
);
2901 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
2903 /* Wait for the clocks to turn off. */
2908 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
2910 struct drm_device
*dev
= crtc
->dev
;
2911 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2912 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2913 int pipe
= intel_crtc
->pipe
;
2916 /* disable CPU FDI tx and PCH FDI rx */
2917 reg
= FDI_TX_CTL(pipe
);
2918 temp
= I915_READ(reg
);
2919 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
2922 reg
= FDI_RX_CTL(pipe
);
2923 temp
= I915_READ(reg
);
2924 temp
&= ~(0x7 << 16);
2925 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2926 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
2931 /* Ironlake workaround, disable clock pointer after downing FDI */
2932 if (HAS_PCH_IBX(dev
)) {
2933 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2936 /* still set train pattern 1 */
2937 reg
= FDI_TX_CTL(pipe
);
2938 temp
= I915_READ(reg
);
2939 temp
&= ~FDI_LINK_TRAIN_NONE
;
2940 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2941 I915_WRITE(reg
, temp
);
2943 reg
= FDI_RX_CTL(pipe
);
2944 temp
= I915_READ(reg
);
2945 if (HAS_PCH_CPT(dev
)) {
2946 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2947 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2949 temp
&= ~FDI_LINK_TRAIN_NONE
;
2950 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2952 /* BPC in FDI rx is consistent with that in PIPECONF */
2953 temp
&= ~(0x07 << 16);
2954 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2955 I915_WRITE(reg
, temp
);
2961 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
2963 struct drm_device
*dev
= crtc
->dev
;
2964 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2965 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2966 unsigned long flags
;
2969 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
2970 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
2973 spin_lock_irqsave(&dev
->event_lock
, flags
);
2974 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
2975 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2980 static void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
2982 struct drm_device
*dev
= crtc
->dev
;
2983 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2985 if (crtc
->fb
== NULL
)
2988 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
2990 wait_event(dev_priv
->pending_flip_queue
,
2991 !intel_crtc_has_pending_flip(crtc
));
2993 mutex_lock(&dev
->struct_mutex
);
2994 intel_finish_fb(crtc
->fb
);
2995 mutex_unlock(&dev
->struct_mutex
);
2998 /* Program iCLKIP clock to the desired frequency */
2999 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
3001 struct drm_device
*dev
= crtc
->dev
;
3002 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3003 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
3006 mutex_lock(&dev_priv
->dpio_lock
);
3008 /* It is necessary to ungate the pixclk gate prior to programming
3009 * the divisors, and gate it back when it is done.
3011 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
3013 /* Disable SSCCTL */
3014 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
3015 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
3019 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3020 if (crtc
->mode
.clock
== 20000) {
3025 /* The iCLK virtual clock root frequency is in MHz,
3026 * but the crtc->mode.clock in in KHz. To get the divisors,
3027 * it is necessary to divide one by another, so we
3028 * convert the virtual clock precision to KHz here for higher
3031 u32 iclk_virtual_root_freq
= 172800 * 1000;
3032 u32 iclk_pi_range
= 64;
3033 u32 desired_divisor
, msb_divisor_value
, pi_value
;
3035 desired_divisor
= (iclk_virtual_root_freq
/ crtc
->mode
.clock
);
3036 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
3037 pi_value
= desired_divisor
% iclk_pi_range
;
3040 divsel
= msb_divisor_value
- 2;
3041 phaseinc
= pi_value
;
3044 /* This should not happen with any sane values */
3045 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
3046 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
3047 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
3048 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
3050 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3057 /* Program SSCDIVINTPHASE6 */
3058 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
3059 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
3060 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
3061 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
3062 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
3063 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
3064 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
3065 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
3067 /* Program SSCAUXDIV */
3068 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
3069 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3070 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
3071 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
3073 /* Enable modulator and associated divider */
3074 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
3075 temp
&= ~SBI_SSCCTL_DISABLE
;
3076 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
3078 /* Wait for initialization time */
3081 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
3083 mutex_unlock(&dev_priv
->dpio_lock
);
3087 * Enable PCH resources required for PCH ports:
3089 * - FDI training & RX/TX
3090 * - update transcoder timings
3091 * - DP transcoding bits
3094 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
3096 struct drm_device
*dev
= crtc
->dev
;
3097 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3098 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3099 int pipe
= intel_crtc
->pipe
;
3102 assert_transcoder_disabled(dev_priv
, pipe
);
3104 /* Write the TU size bits before fdi link training, so that error
3105 * detection works. */
3106 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
3107 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
3109 /* For PCH output, training FDI link */
3110 dev_priv
->display
.fdi_link_train(crtc
);
3112 /* XXX: pch pll's can be enabled any time before we enable the PCH
3113 * transcoder, and we actually should do this to not upset any PCH
3114 * transcoder that already use the clock when we share it.
3116 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3117 * unconditionally resets the pll - we need that to have the right LVDS
3118 * enable sequence. */
3119 ironlake_enable_pch_pll(intel_crtc
);
3121 if (HAS_PCH_CPT(dev
)) {
3124 temp
= I915_READ(PCH_DPLL_SEL
);
3128 temp
|= TRANSA_DPLL_ENABLE
;
3129 sel
= TRANSA_DPLLB_SEL
;
3132 temp
|= TRANSB_DPLL_ENABLE
;
3133 sel
= TRANSB_DPLLB_SEL
;
3136 temp
|= TRANSC_DPLL_ENABLE
;
3137 sel
= TRANSC_DPLLB_SEL
;
3140 if (intel_crtc
->pch_pll
->pll_reg
== _PCH_DPLL_B
)
3144 I915_WRITE(PCH_DPLL_SEL
, temp
);
3147 /* set transcoder timing, panel must allow it */
3148 assert_panel_unlocked(dev_priv
, pipe
);
3149 I915_WRITE(TRANS_HTOTAL(pipe
), I915_READ(HTOTAL(pipe
)));
3150 I915_WRITE(TRANS_HBLANK(pipe
), I915_READ(HBLANK(pipe
)));
3151 I915_WRITE(TRANS_HSYNC(pipe
), I915_READ(HSYNC(pipe
)));
3153 I915_WRITE(TRANS_VTOTAL(pipe
), I915_READ(VTOTAL(pipe
)));
3154 I915_WRITE(TRANS_VBLANK(pipe
), I915_READ(VBLANK(pipe
)));
3155 I915_WRITE(TRANS_VSYNC(pipe
), I915_READ(VSYNC(pipe
)));
3156 I915_WRITE(TRANS_VSYNCSHIFT(pipe
), I915_READ(VSYNCSHIFT(pipe
)));
3158 intel_fdi_normal_train(crtc
);
3160 /* For PCH DP, enable TRANS_DP_CTL */
3161 if (HAS_PCH_CPT(dev
) &&
3162 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
3163 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3164 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
3165 reg
= TRANS_DP_CTL(pipe
);
3166 temp
= I915_READ(reg
);
3167 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
3168 TRANS_DP_SYNC_MASK
|
3170 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
3171 TRANS_DP_ENH_FRAMING
);
3172 temp
|= bpc
<< 9; /* same format but at 11:9 */
3174 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
3175 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
3176 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
3177 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
3179 switch (intel_trans_dp_port_sel(crtc
)) {
3181 temp
|= TRANS_DP_PORT_SEL_B
;
3184 temp
|= TRANS_DP_PORT_SEL_C
;
3187 temp
|= TRANS_DP_PORT_SEL_D
;
3193 I915_WRITE(reg
, temp
);
3196 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
3199 static void lpt_pch_enable(struct drm_crtc
*crtc
)
3201 struct drm_device
*dev
= crtc
->dev
;
3202 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3203 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3204 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
3206 assert_transcoder_disabled(dev_priv
, TRANSCODER_A
);
3208 lpt_program_iclkip(crtc
);
3210 /* Set transcoder timing. */
3211 I915_WRITE(_TRANS_HTOTAL_A
, I915_READ(HTOTAL(cpu_transcoder
)));
3212 I915_WRITE(_TRANS_HBLANK_A
, I915_READ(HBLANK(cpu_transcoder
)));
3213 I915_WRITE(_TRANS_HSYNC_A
, I915_READ(HSYNC(cpu_transcoder
)));
3215 I915_WRITE(_TRANS_VTOTAL_A
, I915_READ(VTOTAL(cpu_transcoder
)));
3216 I915_WRITE(_TRANS_VBLANK_A
, I915_READ(VBLANK(cpu_transcoder
)));
3217 I915_WRITE(_TRANS_VSYNC_A
, I915_READ(VSYNC(cpu_transcoder
)));
3218 I915_WRITE(_TRANS_VSYNCSHIFT_A
, I915_READ(VSYNCSHIFT(cpu_transcoder
)));
3220 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
3223 static void intel_put_pch_pll(struct intel_crtc
*intel_crtc
)
3225 struct intel_pch_pll
*pll
= intel_crtc
->pch_pll
;
3230 if (pll
->refcount
== 0) {
3231 WARN(1, "bad PCH PLL refcount\n");
3236 intel_crtc
->pch_pll
= NULL
;
3239 static struct intel_pch_pll
*intel_get_pch_pll(struct intel_crtc
*intel_crtc
, u32 dpll
, u32 fp
)
3241 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
3242 struct intel_pch_pll
*pll
;
3245 pll
= intel_crtc
->pch_pll
;
3247 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3248 intel_crtc
->base
.base
.id
, pll
->pll_reg
);
3252 if (HAS_PCH_IBX(dev_priv
->dev
)) {
3253 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3254 i
= intel_crtc
->pipe
;
3255 pll
= &dev_priv
->pch_plls
[i
];
3257 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3258 intel_crtc
->base
.base
.id
, pll
->pll_reg
);
3263 for (i
= 0; i
< dev_priv
->num_pch_pll
; i
++) {
3264 pll
= &dev_priv
->pch_plls
[i
];
3266 /* Only want to check enabled timings first */
3267 if (pll
->refcount
== 0)
3270 if (dpll
== (I915_READ(pll
->pll_reg
) & 0x7fffffff) &&
3271 fp
== I915_READ(pll
->fp0_reg
)) {
3272 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3273 intel_crtc
->base
.base
.id
,
3274 pll
->pll_reg
, pll
->refcount
, pll
->active
);
3280 /* Ok no matching timings, maybe there's a free one? */
3281 for (i
= 0; i
< dev_priv
->num_pch_pll
; i
++) {
3282 pll
= &dev_priv
->pch_plls
[i
];
3283 if (pll
->refcount
== 0) {
3284 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3285 intel_crtc
->base
.base
.id
, pll
->pll_reg
);
3293 intel_crtc
->pch_pll
= pll
;
3295 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i
, intel_crtc
->pipe
);
3296 prepare
: /* separate function? */
3297 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll
->pll_reg
);
3299 /* Wait for the clocks to stabilize before rewriting the regs */
3300 I915_WRITE(pll
->pll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
3301 POSTING_READ(pll
->pll_reg
);
3304 I915_WRITE(pll
->fp0_reg
, fp
);
3305 I915_WRITE(pll
->pll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
3310 void intel_cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
3312 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3313 int dslreg
= PIPEDSL(pipe
);
3316 temp
= I915_READ(dslreg
);
3318 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
3319 if (wait_for(I915_READ(dslreg
) != temp
, 5))
3320 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe
);
3324 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
3326 struct drm_device
*dev
= crtc
->dev
;
3327 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3328 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3329 struct intel_encoder
*encoder
;
3330 int pipe
= intel_crtc
->pipe
;
3331 int plane
= intel_crtc
->plane
;
3334 WARN_ON(!crtc
->enabled
);
3336 if (intel_crtc
->active
)
3339 intel_crtc
->active
= true;
3340 intel_update_watermarks(dev
);
3342 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
3343 temp
= I915_READ(PCH_LVDS
);
3344 if ((temp
& LVDS_PORT_EN
) == 0)
3345 I915_WRITE(PCH_LVDS
, temp
| LVDS_PORT_EN
);
3349 if (intel_crtc
->config
.has_pch_encoder
) {
3350 /* Note: FDI PLL enabling _must_ be done before we enable the
3351 * cpu pipes, hence this is separate from all the other fdi/pch
3353 ironlake_fdi_pll_enable(intel_crtc
);
3355 assert_fdi_tx_disabled(dev_priv
, pipe
);
3356 assert_fdi_rx_disabled(dev_priv
, pipe
);
3359 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3360 if (encoder
->pre_enable
)
3361 encoder
->pre_enable(encoder
);
3363 /* Enable panel fitting for LVDS */
3364 if (dev_priv
->pch_pf_size
&&
3365 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) ||
3366 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3367 /* Force use of hard-coded filter coefficients
3368 * as some pre-programmed values are broken,
3371 if (IS_IVYBRIDGE(dev
))
3372 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
3373 PF_PIPE_SEL_IVB(pipe
));
3375 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
3376 I915_WRITE(PF_WIN_POS(pipe
), dev_priv
->pch_pf_pos
);
3377 I915_WRITE(PF_WIN_SZ(pipe
), dev_priv
->pch_pf_size
);
3381 * On ILK+ LUT must be loaded before the pipe is running but with
3384 intel_crtc_load_lut(crtc
);
3386 intel_enable_pipe(dev_priv
, pipe
,
3387 intel_crtc
->config
.has_pch_encoder
);
3388 intel_enable_plane(dev_priv
, plane
, pipe
);
3390 if (intel_crtc
->config
.has_pch_encoder
)
3391 ironlake_pch_enable(crtc
);
3393 mutex_lock(&dev
->struct_mutex
);
3394 intel_update_fbc(dev
);
3395 mutex_unlock(&dev
->struct_mutex
);
3397 intel_crtc_update_cursor(crtc
, true);
3399 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3400 encoder
->enable(encoder
);
3402 if (HAS_PCH_CPT(dev
))
3403 intel_cpt_verify_modeset(dev
, intel_crtc
->pipe
);
3406 * There seems to be a race in PCH platform hw (at least on some
3407 * outputs) where an enabled pipe still completes any pageflip right
3408 * away (as if the pipe is off) instead of waiting for vblank. As soon
3409 * as the first vblank happend, everything works as expected. Hence just
3410 * wait for one vblank before returning to avoid strange things
3413 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3416 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
3418 struct drm_device
*dev
= crtc
->dev
;
3419 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3420 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3421 struct intel_encoder
*encoder
;
3422 int pipe
= intel_crtc
->pipe
;
3423 int plane
= intel_crtc
->plane
;
3425 WARN_ON(!crtc
->enabled
);
3427 if (intel_crtc
->active
)
3430 intel_crtc
->active
= true;
3431 intel_update_watermarks(dev
);
3433 if (intel_crtc
->config
.has_pch_encoder
)
3434 dev_priv
->display
.fdi_link_train(crtc
);
3436 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3437 if (encoder
->pre_enable
)
3438 encoder
->pre_enable(encoder
);
3440 intel_ddi_enable_pipe_clock(intel_crtc
);
3442 /* Enable panel fitting for eDP */
3443 if (dev_priv
->pch_pf_size
&&
3444 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
)) {
3445 /* Force use of hard-coded filter coefficients
3446 * as some pre-programmed values are broken,
3449 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
3450 PF_PIPE_SEL_IVB(pipe
));
3451 I915_WRITE(PF_WIN_POS(pipe
), dev_priv
->pch_pf_pos
);
3452 I915_WRITE(PF_WIN_SZ(pipe
), dev_priv
->pch_pf_size
);
3456 * On ILK+ LUT must be loaded before the pipe is running but with
3459 intel_crtc_load_lut(crtc
);
3461 intel_ddi_set_pipe_settings(crtc
);
3462 intel_ddi_enable_transcoder_func(crtc
);
3464 intel_enable_pipe(dev_priv
, pipe
,
3465 intel_crtc
->config
.has_pch_encoder
);
3466 intel_enable_plane(dev_priv
, plane
, pipe
);
3468 if (intel_crtc
->config
.has_pch_encoder
)
3469 lpt_pch_enable(crtc
);
3471 mutex_lock(&dev
->struct_mutex
);
3472 intel_update_fbc(dev
);
3473 mutex_unlock(&dev
->struct_mutex
);
3475 intel_crtc_update_cursor(crtc
, true);
3477 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3478 encoder
->enable(encoder
);
3481 * There seems to be a race in PCH platform hw (at least on some
3482 * outputs) where an enabled pipe still completes any pageflip right
3483 * away (as if the pipe is off) instead of waiting for vblank. As soon
3484 * as the first vblank happend, everything works as expected. Hence just
3485 * wait for one vblank before returning to avoid strange things
3488 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3491 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
3493 struct drm_device
*dev
= crtc
->dev
;
3494 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3495 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3496 struct intel_encoder
*encoder
;
3497 int pipe
= intel_crtc
->pipe
;
3498 int plane
= intel_crtc
->plane
;
3502 if (!intel_crtc
->active
)
3505 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3506 encoder
->disable(encoder
);
3508 intel_crtc_wait_for_pending_flips(crtc
);
3509 drm_vblank_off(dev
, pipe
);
3510 intel_crtc_update_cursor(crtc
, false);
3512 intel_disable_plane(dev_priv
, plane
, pipe
);
3514 if (dev_priv
->cfb_plane
== plane
)
3515 intel_disable_fbc(dev
);
3517 intel_disable_pipe(dev_priv
, pipe
);
3520 I915_WRITE(PF_CTL(pipe
), 0);
3521 I915_WRITE(PF_WIN_SZ(pipe
), 0);
3523 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3524 if (encoder
->post_disable
)
3525 encoder
->post_disable(encoder
);
3527 ironlake_fdi_disable(crtc
);
3529 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
3531 if (HAS_PCH_CPT(dev
)) {
3532 /* disable TRANS_DP_CTL */
3533 reg
= TRANS_DP_CTL(pipe
);
3534 temp
= I915_READ(reg
);
3535 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
| TRANS_DP_PORT_SEL_MASK
);
3536 temp
|= TRANS_DP_PORT_SEL_NONE
;
3537 I915_WRITE(reg
, temp
);
3539 /* disable DPLL_SEL */
3540 temp
= I915_READ(PCH_DPLL_SEL
);
3543 temp
&= ~(TRANSA_DPLL_ENABLE
| TRANSA_DPLLB_SEL
);
3546 temp
&= ~(TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
);
3549 /* C shares PLL A or B */
3550 temp
&= ~(TRANSC_DPLL_ENABLE
| TRANSC_DPLLB_SEL
);
3555 I915_WRITE(PCH_DPLL_SEL
, temp
);
3558 /* disable PCH DPLL */
3559 intel_disable_pch_pll(intel_crtc
);
3561 ironlake_fdi_pll_disable(intel_crtc
);
3563 intel_crtc
->active
= false;
3564 intel_update_watermarks(dev
);
3566 mutex_lock(&dev
->struct_mutex
);
3567 intel_update_fbc(dev
);
3568 mutex_unlock(&dev
->struct_mutex
);
3571 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
3573 struct drm_device
*dev
= crtc
->dev
;
3574 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3575 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3576 struct intel_encoder
*encoder
;
3577 int pipe
= intel_crtc
->pipe
;
3578 int plane
= intel_crtc
->plane
;
3579 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
3581 if (!intel_crtc
->active
)
3584 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3585 encoder
->disable(encoder
);
3587 intel_crtc_wait_for_pending_flips(crtc
);
3588 drm_vblank_off(dev
, pipe
);
3589 intel_crtc_update_cursor(crtc
, false);
3591 intel_disable_plane(dev_priv
, plane
, pipe
);
3593 if (dev_priv
->cfb_plane
== plane
)
3594 intel_disable_fbc(dev
);
3596 intel_disable_pipe(dev_priv
, pipe
);
3598 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
3601 I915_WRITE(PF_CTL(pipe
), 0);
3602 I915_WRITE(PF_WIN_SZ(pipe
), 0);
3604 intel_ddi_disable_pipe_clock(intel_crtc
);
3606 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3607 if (encoder
->post_disable
)
3608 encoder
->post_disable(encoder
);
3610 if (intel_crtc
->config
.has_pch_encoder
) {
3611 lpt_disable_pch_transcoder(dev_priv
);
3612 intel_ddi_fdi_disable(crtc
);
3615 intel_crtc
->active
= false;
3616 intel_update_watermarks(dev
);
3618 mutex_lock(&dev
->struct_mutex
);
3619 intel_update_fbc(dev
);
3620 mutex_unlock(&dev
->struct_mutex
);
3623 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
3625 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3626 intel_put_pch_pll(intel_crtc
);
3629 static void haswell_crtc_off(struct drm_crtc
*crtc
)
3631 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3633 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3634 * start using it. */
3635 intel_crtc
->cpu_transcoder
= (enum transcoder
) intel_crtc
->pipe
;
3637 intel_ddi_put_crtc_pll(crtc
);
3640 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
3642 if (!enable
&& intel_crtc
->overlay
) {
3643 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3644 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3646 mutex_lock(&dev
->struct_mutex
);
3647 dev_priv
->mm
.interruptible
= false;
3648 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
3649 dev_priv
->mm
.interruptible
= true;
3650 mutex_unlock(&dev
->struct_mutex
);
3653 /* Let userspace switch the overlay on again. In most cases userspace
3654 * has to recompute where to put it anyway.
3659 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3660 * cursor plane briefly if not already running after enabling the display
3662 * This workaround avoids occasional blank screens when self refresh is
3666 g4x_fixup_plane(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
3668 u32 cntl
= I915_READ(CURCNTR(pipe
));
3670 if ((cntl
& CURSOR_MODE
) == 0) {
3671 u32 fw_bcl_self
= I915_READ(FW_BLC_SELF
);
3673 I915_WRITE(FW_BLC_SELF
, fw_bcl_self
& ~FW_BLC_SELF_EN
);
3674 I915_WRITE(CURCNTR(pipe
), CURSOR_MODE_64_ARGB_AX
);
3675 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
3676 I915_WRITE(CURCNTR(pipe
), cntl
);
3677 I915_WRITE(CURBASE(pipe
), I915_READ(CURBASE(pipe
)));
3678 I915_WRITE(FW_BLC_SELF
, fw_bcl_self
);
3682 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
3684 struct drm_device
*dev
= crtc
->dev
;
3685 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3686 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3687 struct intel_encoder
*encoder
;
3688 int pipe
= intel_crtc
->pipe
;
3689 int plane
= intel_crtc
->plane
;
3691 WARN_ON(!crtc
->enabled
);
3693 if (intel_crtc
->active
)
3696 intel_crtc
->active
= true;
3697 intel_update_watermarks(dev
);
3699 intel_enable_pll(dev_priv
, pipe
);
3701 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3702 if (encoder
->pre_enable
)
3703 encoder
->pre_enable(encoder
);
3705 intel_enable_pipe(dev_priv
, pipe
, false);
3706 intel_enable_plane(dev_priv
, plane
, pipe
);
3708 g4x_fixup_plane(dev_priv
, pipe
);
3710 intel_crtc_load_lut(crtc
);
3711 intel_update_fbc(dev
);
3713 /* Give the overlay scaler a chance to enable if it's on this pipe */
3714 intel_crtc_dpms_overlay(intel_crtc
, true);
3715 intel_crtc_update_cursor(crtc
, true);
3717 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3718 encoder
->enable(encoder
);
3721 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
3723 struct drm_device
*dev
= crtc
->dev
;
3724 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3725 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3726 struct intel_encoder
*encoder
;
3727 int pipe
= intel_crtc
->pipe
;
3728 int plane
= intel_crtc
->plane
;
3732 if (!intel_crtc
->active
)
3735 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3736 encoder
->disable(encoder
);
3738 /* Give the overlay scaler a chance to disable if it's on this pipe */
3739 intel_crtc_wait_for_pending_flips(crtc
);
3740 drm_vblank_off(dev
, pipe
);
3741 intel_crtc_dpms_overlay(intel_crtc
, false);
3742 intel_crtc_update_cursor(crtc
, false);
3744 if (dev_priv
->cfb_plane
== plane
)
3745 intel_disable_fbc(dev
);
3747 intel_disable_plane(dev_priv
, plane
, pipe
);
3748 intel_disable_pipe(dev_priv
, pipe
);
3750 /* Disable pannel fitter if it is on this pipe. */
3751 pctl
= I915_READ(PFIT_CONTROL
);
3752 if ((pctl
& PFIT_ENABLE
) &&
3753 ((pctl
& PFIT_PIPE_MASK
) >> PFIT_PIPE_SHIFT
) == pipe
)
3754 I915_WRITE(PFIT_CONTROL
, 0);
3756 intel_disable_pll(dev_priv
, pipe
);
3758 intel_crtc
->active
= false;
3759 intel_update_fbc(dev
);
3760 intel_update_watermarks(dev
);
3763 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
3767 static void intel_crtc_update_sarea(struct drm_crtc
*crtc
,
3770 struct drm_device
*dev
= crtc
->dev
;
3771 struct drm_i915_master_private
*master_priv
;
3772 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3773 int pipe
= intel_crtc
->pipe
;
3775 if (!dev
->primary
->master
)
3778 master_priv
= dev
->primary
->master
->driver_priv
;
3779 if (!master_priv
->sarea_priv
)
3784 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3785 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3788 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3789 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3792 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe
));
3798 * Sets the power management mode of the pipe and plane.
3800 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
3802 struct drm_device
*dev
= crtc
->dev
;
3803 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3804 struct intel_encoder
*intel_encoder
;
3805 bool enable
= false;
3807 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
3808 enable
|= intel_encoder
->connectors_active
;
3811 dev_priv
->display
.crtc_enable(crtc
);
3813 dev_priv
->display
.crtc_disable(crtc
);
3815 intel_crtc_update_sarea(crtc
, enable
);
3818 static void intel_crtc_disable(struct drm_crtc
*crtc
)
3820 struct drm_device
*dev
= crtc
->dev
;
3821 struct drm_connector
*connector
;
3822 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3823 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3825 /* crtc should still be enabled when we disable it. */
3826 WARN_ON(!crtc
->enabled
);
3828 intel_crtc
->eld_vld
= false;
3829 dev_priv
->display
.crtc_disable(crtc
);
3830 intel_crtc_update_sarea(crtc
, false);
3831 dev_priv
->display
.off(crtc
);
3833 assert_plane_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->plane
);
3834 assert_pipe_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->pipe
);
3837 mutex_lock(&dev
->struct_mutex
);
3838 intel_unpin_fb_obj(to_intel_framebuffer(crtc
->fb
)->obj
);
3839 mutex_unlock(&dev
->struct_mutex
);
3843 /* Update computed state. */
3844 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
3845 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
3848 if (connector
->encoder
->crtc
!= crtc
)
3851 connector
->dpms
= DRM_MODE_DPMS_OFF
;
3852 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
3856 void intel_modeset_disable(struct drm_device
*dev
)
3858 struct drm_crtc
*crtc
;
3860 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
3862 intel_crtc_disable(crtc
);
3866 void intel_encoder_destroy(struct drm_encoder
*encoder
)
3868 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
3870 drm_encoder_cleanup(encoder
);
3871 kfree(intel_encoder
);
3874 /* Simple dpms helper for encodres with just one connector, no cloning and only
3875 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3876 * state of the entire output pipe. */
3877 void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
3879 if (mode
== DRM_MODE_DPMS_ON
) {
3880 encoder
->connectors_active
= true;
3882 intel_crtc_update_dpms(encoder
->base
.crtc
);
3884 encoder
->connectors_active
= false;
3886 intel_crtc_update_dpms(encoder
->base
.crtc
);
3890 /* Cross check the actual hw state with our own modeset state tracking (and it's
3891 * internal consistency). */
3892 static void intel_connector_check_state(struct intel_connector
*connector
)
3894 if (connector
->get_hw_state(connector
)) {
3895 struct intel_encoder
*encoder
= connector
->encoder
;
3896 struct drm_crtc
*crtc
;
3897 bool encoder_enabled
;
3900 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3901 connector
->base
.base
.id
,
3902 drm_get_connector_name(&connector
->base
));
3904 WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
3905 "wrong connector dpms state\n");
3906 WARN(connector
->base
.encoder
!= &encoder
->base
,
3907 "active connector not linked to encoder\n");
3908 WARN(!encoder
->connectors_active
,
3909 "encoder->connectors_active not set\n");
3911 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
3912 WARN(!encoder_enabled
, "encoder not enabled\n");
3913 if (WARN_ON(!encoder
->base
.crtc
))
3916 crtc
= encoder
->base
.crtc
;
3918 WARN(!crtc
->enabled
, "crtc not enabled\n");
3919 WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
3920 WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
3921 "encoder active on the wrong pipe\n");
3925 /* Even simpler default implementation, if there's really no special case to
3927 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
3929 struct intel_encoder
*encoder
= intel_attached_encoder(connector
);
3931 /* All the simple cases only support two dpms states. */
3932 if (mode
!= DRM_MODE_DPMS_ON
)
3933 mode
= DRM_MODE_DPMS_OFF
;
3935 if (mode
== connector
->dpms
)
3938 connector
->dpms
= mode
;
3940 /* Only need to change hw state when actually enabled */
3941 if (encoder
->base
.crtc
)
3942 intel_encoder_dpms(encoder
, mode
);
3944 WARN_ON(encoder
->connectors_active
!= false);
3946 intel_modeset_check_state(connector
->dev
);
3949 /* Simple connector->get_hw_state implementation for encoders that support only
3950 * one connector and no cloning and hence the encoder state determines the state
3951 * of the connector. */
3952 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
3955 struct intel_encoder
*encoder
= connector
->encoder
;
3957 return encoder
->get_hw_state(encoder
, &pipe
);
3960 static bool intel_crtc_compute_config(struct drm_crtc
*crtc
,
3961 struct intel_crtc_config
*pipe_config
)
3963 struct drm_device
*dev
= crtc
->dev
;
3964 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
3966 if (HAS_PCH_SPLIT(dev
)) {
3967 /* FDI link clock is fixed at 2.7G */
3968 if (pipe_config
->requested_mode
.clock
* 3
3969 > IRONLAKE_FDI_FREQ
* 4)
3973 /* All interlaced capable intel hw wants timings in frames. Note though
3974 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3975 * timings, so we need to be careful not to clobber these.*/
3976 if (!pipe_config
->timings_set
)
3977 drm_mode_set_crtcinfo(adjusted_mode
, 0);
3979 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3980 * with a hsync front porch of 0.
3982 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
3983 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
3986 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) && pipe_config
->pipe_bpp
> 10) {
3987 pipe_config
->pipe_bpp
= 10*3; /* 12bpc is gen5+ */
3988 } else if (INTEL_INFO(dev
)->gen
<= 4 && pipe_config
->pipe_bpp
> 8) {
3989 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
3991 pipe_config
->pipe_bpp
= 8*3;
3997 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
3999 return 400000; /* FIXME */
4002 static int i945_get_display_clock_speed(struct drm_device
*dev
)
4007 static int i915_get_display_clock_speed(struct drm_device
*dev
)
4012 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
4017 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
4021 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
4023 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
4026 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
4027 case GC_DISPLAY_CLOCK_333_MHZ
:
4030 case GC_DISPLAY_CLOCK_190_200_MHZ
:
4036 static int i865_get_display_clock_speed(struct drm_device
*dev
)
4041 static int i855_get_display_clock_speed(struct drm_device
*dev
)
4044 /* Assume that the hardware is in the high speed state. This
4045 * should be the default.
4047 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
4048 case GC_CLOCK_133_200
:
4049 case GC_CLOCK_100_200
:
4051 case GC_CLOCK_166_250
:
4053 case GC_CLOCK_100_133
:
4057 /* Shouldn't happen */
4061 static int i830_get_display_clock_speed(struct drm_device
*dev
)
4067 intel_reduce_ratio(uint32_t *num
, uint32_t *den
)
4069 while (*num
> 0xffffff || *den
> 0xffffff) {
4076 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
4077 int pixel_clock
, int link_clock
,
4078 struct intel_link_m_n
*m_n
)
4081 m_n
->gmch_m
= bits_per_pixel
* pixel_clock
;
4082 m_n
->gmch_n
= link_clock
* nlanes
* 8;
4083 intel_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
4084 m_n
->link_m
= pixel_clock
;
4085 m_n
->link_n
= link_clock
;
4086 intel_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
4089 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
4091 if (i915_panel_use_ssc
>= 0)
4092 return i915_panel_use_ssc
!= 0;
4093 return dev_priv
->lvds_use_ssc
4094 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
4097 static int vlv_get_refclk(struct drm_crtc
*crtc
)
4099 struct drm_device
*dev
= crtc
->dev
;
4100 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4101 int refclk
= 27000; /* for DP & HDMI */
4103 return 100000; /* only one validated so far */
4105 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
4107 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
4108 if (intel_panel_use_ssc(dev_priv
))
4112 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
)) {
4119 static int i9xx_get_refclk(struct drm_crtc
*crtc
, int num_connectors
)
4121 struct drm_device
*dev
= crtc
->dev
;
4122 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4125 if (IS_VALLEYVIEW(dev
)) {
4126 refclk
= vlv_get_refclk(crtc
);
4127 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4128 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
4129 refclk
= dev_priv
->lvds_ssc_freq
* 1000;
4130 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4132 } else if (!IS_GEN2(dev
)) {
4141 static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc
*crtc
)
4143 unsigned dotclock
= crtc
->config
.adjusted_mode
.clock
;
4144 struct dpll
*clock
= &crtc
->config
.dpll
;
4146 /* SDVO TV has fixed PLL values depend on its clock range,
4147 this mirrors vbios setting. */
4148 if (dotclock
>= 100000 && dotclock
< 140500) {
4154 } else if (dotclock
>= 140500 && dotclock
<= 200000) {
4162 crtc
->config
.clock_set
= true;
4165 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
4166 intel_clock_t
*reduced_clock
)
4168 struct drm_device
*dev
= crtc
->base
.dev
;
4169 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4170 int pipe
= crtc
->pipe
;
4172 struct dpll
*clock
= &crtc
->config
.dpll
;
4174 if (IS_PINEVIEW(dev
)) {
4175 fp
= (1 << clock
->n
) << 16 | clock
->m1
<< 8 | clock
->m2
;
4177 fp2
= (1 << reduced_clock
->n
) << 16 |
4178 reduced_clock
->m1
<< 8 | reduced_clock
->m2
;
4180 fp
= clock
->n
<< 16 | clock
->m1
<< 8 | clock
->m2
;
4182 fp2
= reduced_clock
->n
<< 16 | reduced_clock
->m1
<< 8 |
4186 I915_WRITE(FP0(pipe
), fp
);
4188 crtc
->lowfreq_avail
= false;
4189 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4190 reduced_clock
&& i915_powersave
) {
4191 I915_WRITE(FP1(pipe
), fp2
);
4192 crtc
->lowfreq_avail
= true;
4194 I915_WRITE(FP1(pipe
), fp
);
4198 static void intel_dp_set_m_n(struct intel_crtc
*crtc
)
4200 if (crtc
->config
.has_pch_encoder
)
4201 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
4203 intel_cpu_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
4206 static void vlv_update_pll(struct intel_crtc
*crtc
)
4208 struct drm_device
*dev
= crtc
->base
.dev
;
4209 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4210 int pipe
= crtc
->pipe
;
4211 u32 dpll
, mdiv
, pdiv
;
4212 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
4216 mutex_lock(&dev_priv
->dpio_lock
);
4218 is_sdvo
= intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_SDVO
) ||
4219 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
);
4221 dpll
= DPLL_VGA_MODE_DIS
;
4222 dpll
|= DPLL_EXT_BUFFER_ENABLE_VLV
;
4223 dpll
|= DPLL_REFA_CLK_ENABLE_VLV
;
4224 dpll
|= DPLL_INTEGRATED_CLOCK_VLV
;
4226 I915_WRITE(DPLL(pipe
), dpll
);
4227 POSTING_READ(DPLL(pipe
));
4229 bestn
= crtc
->config
.dpll
.n
;
4230 bestm1
= crtc
->config
.dpll
.m1
;
4231 bestm2
= crtc
->config
.dpll
.m2
;
4232 bestp1
= crtc
->config
.dpll
.p1
;
4233 bestp2
= crtc
->config
.dpll
.p2
;
4236 * In Valleyview PLL and program lane counter registers are exposed
4237 * through DPIO interface
4239 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
4240 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
4241 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
4242 mdiv
|= (1 << DPIO_POST_DIV_SHIFT
);
4243 mdiv
|= (1 << DPIO_K_SHIFT
);
4244 mdiv
|= DPIO_ENABLE_CALIBRATION
;
4245 intel_dpio_write(dev_priv
, DPIO_DIV(pipe
), mdiv
);
4247 intel_dpio_write(dev_priv
, DPIO_CORE_CLK(pipe
), 0x01000000);
4249 pdiv
= (1 << DPIO_REFSEL_OVERRIDE
) | (5 << DPIO_PLL_MODESEL_SHIFT
) |
4250 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT
) | (1<<20) |
4251 (7 << DPIO_PLL_REFCLK_SEL_SHIFT
) | (8 << DPIO_DRIVER_CTL_SHIFT
) |
4252 (5 << DPIO_CLK_BIAS_CTL_SHIFT
);
4253 intel_dpio_write(dev_priv
, DPIO_REFSFR(pipe
), pdiv
);
4255 intel_dpio_write(dev_priv
, DPIO_LFP_COEFF(pipe
), 0x005f003b);
4257 dpll
|= DPLL_VCO_ENABLE
;
4258 I915_WRITE(DPLL(pipe
), dpll
);
4259 POSTING_READ(DPLL(pipe
));
4260 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
4261 DRM_ERROR("DPLL %d failed to lock\n", pipe
);
4263 intel_dpio_write(dev_priv
, DPIO_FASTCLK_DISABLE
, 0x620);
4265 if (crtc
->config
.has_dp_encoder
)
4266 intel_dp_set_m_n(crtc
);
4268 I915_WRITE(DPLL(pipe
), dpll
);
4270 /* Wait for the clocks to stabilize. */
4271 POSTING_READ(DPLL(pipe
));
4277 if (crtc
->config
.pixel_multiplier
> 1) {
4278 temp
= (crtc
->config
.pixel_multiplier
- 1)
4279 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4282 I915_WRITE(DPLL_MD(pipe
), temp
);
4283 POSTING_READ(DPLL_MD(pipe
));
4285 /* Now program lane control registers */
4286 if(intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
)
4287 || intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
)) {
4291 intel_dpio_write(dev_priv
, DPIO_DATA_CHANNEL1
, temp
);
4294 if(intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
)) {
4298 intel_dpio_write(dev_priv
, DPIO_DATA_CHANNEL2
, temp
);
4301 mutex_unlock(&dev_priv
->dpio_lock
);
4304 static void i9xx_update_pll(struct intel_crtc
*crtc
,
4305 intel_clock_t
*reduced_clock
,
4308 struct drm_device
*dev
= crtc
->base
.dev
;
4309 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4310 struct intel_encoder
*encoder
;
4311 int pipe
= crtc
->pipe
;
4314 struct dpll
*clock
= &crtc
->config
.dpll
;
4316 i9xx_update_pll_dividers(crtc
, reduced_clock
);
4318 is_sdvo
= intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_SDVO
) ||
4319 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
);
4321 dpll
= DPLL_VGA_MODE_DIS
;
4323 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
))
4324 dpll
|= DPLLB_MODE_LVDS
;
4326 dpll
|= DPLLB_MODE_DAC_SERIAL
;
4329 if ((crtc
->config
.pixel_multiplier
> 1) &&
4330 (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))) {
4331 dpll
|= (crtc
->config
.pixel_multiplier
- 1)
4332 << SDVO_MULTIPLIER_SHIFT_HIRES
;
4334 dpll
|= DPLL_DVO_HIGH_SPEED
;
4336 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
))
4337 dpll
|= DPLL_DVO_HIGH_SPEED
;
4339 /* compute bitmask from p1 value */
4340 if (IS_PINEVIEW(dev
))
4341 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
4343 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4344 if (IS_G4X(dev
) && reduced_clock
)
4345 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
4347 switch (clock
->p2
) {
4349 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
4352 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
4355 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
4358 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
4361 if (INTEL_INFO(dev
)->gen
>= 4)
4362 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
4364 if (is_sdvo
&& intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_TVOUT
))
4365 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
4366 else if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_TVOUT
))
4367 /* XXX: just matching BIOS for now */
4368 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4370 else if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4371 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4372 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4374 dpll
|= PLL_REF_INPUT_DREFCLK
;
4376 dpll
|= DPLL_VCO_ENABLE
;
4377 I915_WRITE(DPLL(pipe
), dpll
& ~DPLL_VCO_ENABLE
);
4378 POSTING_READ(DPLL(pipe
));
4381 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
4382 if (encoder
->pre_pll_enable
)
4383 encoder
->pre_pll_enable(encoder
);
4385 if (crtc
->config
.has_dp_encoder
)
4386 intel_dp_set_m_n(crtc
);
4388 I915_WRITE(DPLL(pipe
), dpll
);
4390 /* Wait for the clocks to stabilize. */
4391 POSTING_READ(DPLL(pipe
));
4394 if (INTEL_INFO(dev
)->gen
>= 4) {
4398 if (crtc
->config
.pixel_multiplier
> 1) {
4399 temp
= (crtc
->config
.pixel_multiplier
- 1)
4400 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4403 I915_WRITE(DPLL_MD(pipe
), temp
);
4405 /* The pixel multiplier can only be updated once the
4406 * DPLL is enabled and the clocks are stable.
4408 * So write it again.
4410 I915_WRITE(DPLL(pipe
), dpll
);
4414 static void i8xx_update_pll(struct intel_crtc
*crtc
,
4415 struct drm_display_mode
*adjusted_mode
,
4416 intel_clock_t
*reduced_clock
,
4419 struct drm_device
*dev
= crtc
->base
.dev
;
4420 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4421 struct intel_encoder
*encoder
;
4422 int pipe
= crtc
->pipe
;
4424 struct dpll
*clock
= &crtc
->config
.dpll
;
4426 i9xx_update_pll_dividers(crtc
, reduced_clock
);
4428 dpll
= DPLL_VGA_MODE_DIS
;
4430 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
)) {
4431 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4434 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
4436 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4438 dpll
|= PLL_P2_DIVIDE_BY_4
;
4441 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4442 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4443 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4445 dpll
|= PLL_REF_INPUT_DREFCLK
;
4447 dpll
|= DPLL_VCO_ENABLE
;
4448 I915_WRITE(DPLL(pipe
), dpll
& ~DPLL_VCO_ENABLE
);
4449 POSTING_READ(DPLL(pipe
));
4452 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
4453 if (encoder
->pre_pll_enable
)
4454 encoder
->pre_pll_enable(encoder
);
4456 I915_WRITE(DPLL(pipe
), dpll
);
4458 /* Wait for the clocks to stabilize. */
4459 POSTING_READ(DPLL(pipe
));
4462 /* The pixel multiplier can only be updated once the
4463 * DPLL is enabled and the clocks are stable.
4465 * So write it again.
4467 I915_WRITE(DPLL(pipe
), dpll
);
4470 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
,
4471 struct drm_display_mode
*mode
,
4472 struct drm_display_mode
*adjusted_mode
)
4474 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4475 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4476 enum pipe pipe
= intel_crtc
->pipe
;
4477 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
4478 uint32_t vsyncshift
;
4480 if (!IS_GEN2(dev
) && adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
4481 /* the chip adds 2 halflines automatically */
4482 adjusted_mode
->crtc_vtotal
-= 1;
4483 adjusted_mode
->crtc_vblank_end
-= 1;
4484 vsyncshift
= adjusted_mode
->crtc_hsync_start
4485 - adjusted_mode
->crtc_htotal
/ 2;
4490 if (INTEL_INFO(dev
)->gen
> 3)
4491 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
4493 I915_WRITE(HTOTAL(cpu_transcoder
),
4494 (adjusted_mode
->crtc_hdisplay
- 1) |
4495 ((adjusted_mode
->crtc_htotal
- 1) << 16));
4496 I915_WRITE(HBLANK(cpu_transcoder
),
4497 (adjusted_mode
->crtc_hblank_start
- 1) |
4498 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
4499 I915_WRITE(HSYNC(cpu_transcoder
),
4500 (adjusted_mode
->crtc_hsync_start
- 1) |
4501 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
4503 I915_WRITE(VTOTAL(cpu_transcoder
),
4504 (adjusted_mode
->crtc_vdisplay
- 1) |
4505 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
4506 I915_WRITE(VBLANK(cpu_transcoder
),
4507 (adjusted_mode
->crtc_vblank_start
- 1) |
4508 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
4509 I915_WRITE(VSYNC(cpu_transcoder
),
4510 (adjusted_mode
->crtc_vsync_start
- 1) |
4511 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
4513 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4514 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4515 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4517 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
4518 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
4519 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
4521 /* pipesrc controls the size that is scaled from, which should
4522 * always be the user's requested size.
4524 I915_WRITE(PIPESRC(pipe
),
4525 ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
4528 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
4530 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4531 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4534 pipeconf
= I915_READ(PIPECONF(intel_crtc
->pipe
));
4536 if (intel_crtc
->pipe
== 0 && INTEL_INFO(dev
)->gen
< 4) {
4537 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4540 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4543 if (intel_crtc
->config
.requested_mode
.clock
>
4544 dev_priv
->display
.get_display_clock_speed(dev
) * 9 / 10)
4545 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
4547 pipeconf
&= ~PIPECONF_DOUBLE_WIDE
;
4550 /* default to 8bpc */
4551 pipeconf
&= ~(PIPECONF_BPC_MASK
| PIPECONF_DITHER_EN
);
4552 if (intel_crtc
->config
.has_dp_encoder
) {
4553 if (intel_crtc
->config
.dither
) {
4554 pipeconf
|= PIPECONF_6BPC
|
4555 PIPECONF_DITHER_EN
|
4556 PIPECONF_DITHER_TYPE_SP
;
4560 if (IS_VALLEYVIEW(dev
) && intel_pipe_has_type(&intel_crtc
->base
,
4561 INTEL_OUTPUT_EDP
)) {
4562 if (intel_crtc
->config
.dither
) {
4563 pipeconf
|= PIPECONF_6BPC
|
4565 I965_PIPECONF_ACTIVE
;
4569 if (HAS_PIPE_CXSR(dev
)) {
4570 if (intel_crtc
->lowfreq_avail
) {
4571 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4572 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
4574 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4575 pipeconf
&= ~PIPECONF_CXSR_DOWNCLOCK
;
4579 pipeconf
&= ~PIPECONF_INTERLACE_MASK
;
4580 if (!IS_GEN2(dev
) &&
4581 intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
4582 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
4584 pipeconf
|= PIPECONF_PROGRESSIVE
;
4586 if (IS_VALLEYVIEW(dev
)) {
4587 if (intel_crtc
->config
.limited_color_range
)
4588 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
4590 pipeconf
&= ~PIPECONF_COLOR_RANGE_SELECT
;
4593 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
4594 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
4597 static int i9xx_crtc_mode_set(struct drm_crtc
*crtc
,
4599 struct drm_framebuffer
*fb
)
4601 struct drm_device
*dev
= crtc
->dev
;
4602 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4603 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4604 struct drm_display_mode
*adjusted_mode
=
4605 &intel_crtc
->config
.adjusted_mode
;
4606 struct drm_display_mode
*mode
= &intel_crtc
->config
.requested_mode
;
4607 int pipe
= intel_crtc
->pipe
;
4608 int plane
= intel_crtc
->plane
;
4609 int refclk
, num_connectors
= 0;
4610 intel_clock_t clock
, reduced_clock
;
4612 bool ok
, has_reduced_clock
= false, is_sdvo
= false;
4613 bool is_lvds
= false, is_tv
= false;
4614 struct intel_encoder
*encoder
;
4615 const intel_limit_t
*limit
;
4618 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4619 switch (encoder
->type
) {
4620 case INTEL_OUTPUT_LVDS
:
4623 case INTEL_OUTPUT_SDVO
:
4624 case INTEL_OUTPUT_HDMI
:
4626 if (encoder
->needs_tv_clock
)
4629 case INTEL_OUTPUT_TVOUT
:
4637 refclk
= i9xx_get_refclk(crtc
, num_connectors
);
4640 * Returns a set of divisors for the desired target clock with the given
4641 * refclk, or FALSE. The returned values represent the clock equation:
4642 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4644 limit
= intel_limit(crtc
, refclk
);
4645 ok
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, NULL
,
4648 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4652 /* Ensure that the cursor is valid for the new mode before changing... */
4653 intel_crtc_update_cursor(crtc
, true);
4655 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
4657 * Ensure we match the reduced clock's P to the target clock.
4658 * If the clocks don't match, we can't switch the display clock
4659 * by using the FP0/FP1. In such case we will disable the LVDS
4660 * downclock feature.
4662 has_reduced_clock
= limit
->find_pll(limit
, crtc
,
4663 dev_priv
->lvds_downclock
,
4668 /* Compat-code for transition, will disappear. */
4669 if (!intel_crtc
->config
.clock_set
) {
4670 intel_crtc
->config
.dpll
.n
= clock
.n
;
4671 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
4672 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
4673 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
4674 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
4677 if (is_sdvo
&& is_tv
)
4678 i9xx_adjust_sdvo_tv_clock(intel_crtc
);
4681 i8xx_update_pll(intel_crtc
, adjusted_mode
,
4682 has_reduced_clock
? &reduced_clock
: NULL
,
4684 else if (IS_VALLEYVIEW(dev
))
4685 vlv_update_pll(intel_crtc
);
4687 i9xx_update_pll(intel_crtc
,
4688 has_reduced_clock
? &reduced_clock
: NULL
,
4691 /* Set up the display plane register */
4692 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
4694 if (!IS_VALLEYVIEW(dev
)) {
4696 dspcntr
&= ~DISPPLANE_SEL_PIPE_MASK
;
4698 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
4701 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe
== 0 ? 'A' : 'B');
4702 drm_mode_debug_printmodeline(mode
);
4704 intel_set_pipe_timings(intel_crtc
, mode
, adjusted_mode
);
4706 /* pipesrc and dspsize control the size that is scaled from,
4707 * which should always be the user's requested size.
4709 I915_WRITE(DSPSIZE(plane
),
4710 ((mode
->vdisplay
- 1) << 16) |
4711 (mode
->hdisplay
- 1));
4712 I915_WRITE(DSPPOS(plane
), 0);
4714 i9xx_set_pipeconf(intel_crtc
);
4716 intel_enable_pipe(dev_priv
, pipe
, false);
4718 intel_wait_for_vblank(dev
, pipe
);
4720 I915_WRITE(DSPCNTR(plane
), dspcntr
);
4721 POSTING_READ(DSPCNTR(plane
));
4723 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
4725 intel_update_watermarks(dev
);
4730 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
4731 struct intel_crtc_config
*pipe_config
)
4733 struct drm_device
*dev
= crtc
->base
.dev
;
4734 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4737 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
4738 if (!(tmp
& PIPECONF_ENABLE
))
4744 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
4746 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4747 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
4748 struct intel_encoder
*encoder
;
4750 bool has_lvds
= false;
4751 bool has_cpu_edp
= false;
4752 bool has_pch_edp
= false;
4753 bool has_panel
= false;
4754 bool has_ck505
= false;
4755 bool can_ssc
= false;
4757 /* We need to take the global config into account */
4758 list_for_each_entry(encoder
, &mode_config
->encoder_list
,
4760 switch (encoder
->type
) {
4761 case INTEL_OUTPUT_LVDS
:
4765 case INTEL_OUTPUT_EDP
:
4767 if (intel_encoder_is_pch_edp(&encoder
->base
))
4775 if (HAS_PCH_IBX(dev
)) {
4776 has_ck505
= dev_priv
->display_clock_mode
;
4777 can_ssc
= has_ck505
;
4783 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4784 has_panel
, has_lvds
, has_pch_edp
, has_cpu_edp
,
4787 /* Ironlake: try to setup display ref clock before DPLL
4788 * enabling. This is only under driver's control after
4789 * PCH B stepping, previous chipset stepping should be
4790 * ignoring this setting.
4792 val
= I915_READ(PCH_DREF_CONTROL
);
4794 /* As we must carefully and slowly disable/enable each source in turn,
4795 * compute the final state we want first and check if we need to
4796 * make any changes at all.
4799 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
4801 final
|= DREF_NONSPREAD_CK505_ENABLE
;
4803 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
4805 final
&= ~DREF_SSC_SOURCE_MASK
;
4806 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
4807 final
&= ~DREF_SSC1_ENABLE
;
4810 final
|= DREF_SSC_SOURCE_ENABLE
;
4812 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
4813 final
|= DREF_SSC1_ENABLE
;
4816 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
4817 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
4819 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
4821 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
4823 final
|= DREF_SSC_SOURCE_DISABLE
;
4824 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
4830 /* Always enable nonspread source */
4831 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
4834 val
|= DREF_NONSPREAD_CK505_ENABLE
;
4836 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
4839 val
&= ~DREF_SSC_SOURCE_MASK
;
4840 val
|= DREF_SSC_SOURCE_ENABLE
;
4842 /* SSC must be turned on before enabling the CPU output */
4843 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
4844 DRM_DEBUG_KMS("Using SSC on panel\n");
4845 val
|= DREF_SSC1_ENABLE
;
4847 val
&= ~DREF_SSC1_ENABLE
;
4849 /* Get SSC going before enabling the outputs */
4850 I915_WRITE(PCH_DREF_CONTROL
, val
);
4851 POSTING_READ(PCH_DREF_CONTROL
);
4854 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
4856 /* Enable CPU source on CPU attached eDP */
4858 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
4859 DRM_DEBUG_KMS("Using SSC on eDP\n");
4860 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
4863 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
4865 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
4867 I915_WRITE(PCH_DREF_CONTROL
, val
);
4868 POSTING_READ(PCH_DREF_CONTROL
);
4871 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4873 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
4875 /* Turn off CPU output */
4876 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
4878 I915_WRITE(PCH_DREF_CONTROL
, val
);
4879 POSTING_READ(PCH_DREF_CONTROL
);
4882 /* Turn off the SSC source */
4883 val
&= ~DREF_SSC_SOURCE_MASK
;
4884 val
|= DREF_SSC_SOURCE_DISABLE
;
4887 val
&= ~DREF_SSC1_ENABLE
;
4889 I915_WRITE(PCH_DREF_CONTROL
, val
);
4890 POSTING_READ(PCH_DREF_CONTROL
);
4894 BUG_ON(val
!= final
);
4897 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4898 static void lpt_init_pch_refclk(struct drm_device
*dev
)
4900 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4901 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
4902 struct intel_encoder
*encoder
;
4903 bool has_vga
= false;
4904 bool is_sdv
= false;
4907 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
) {
4908 switch (encoder
->type
) {
4909 case INTEL_OUTPUT_ANALOG
:
4918 mutex_lock(&dev_priv
->dpio_lock
);
4920 /* XXX: Rip out SDV support once Haswell ships for real. */
4921 if (IS_HASWELL(dev
) && (dev
->pci_device
& 0xFF00) == 0x0C00)
4924 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
4925 tmp
&= ~SBI_SSCCTL_DISABLE
;
4926 tmp
|= SBI_SSCCTL_PATHALT
;
4927 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
4931 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
4932 tmp
&= ~SBI_SSCCTL_PATHALT
;
4933 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
4936 tmp
= I915_READ(SOUTH_CHICKEN2
);
4937 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
4938 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
4940 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
4941 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
4942 DRM_ERROR("FDI mPHY reset assert timeout\n");
4944 tmp
= I915_READ(SOUTH_CHICKEN2
);
4945 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
4946 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
4948 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
4949 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0,
4951 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
4954 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
4955 tmp
&= ~(0xFF << 24);
4956 tmp
|= (0x12 << 24);
4957 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
4960 tmp
= intel_sbi_read(dev_priv
, 0x808C, SBI_MPHY
);
4962 tmp
|= (1 << 6) | (1 << 0);
4963 intel_sbi_write(dev_priv
, 0x808C, tmp
, SBI_MPHY
);
4967 tmp
= intel_sbi_read(dev_priv
, 0x800C, SBI_MPHY
);
4969 intel_sbi_write(dev_priv
, 0x800C, tmp
, SBI_MPHY
);
4972 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
4974 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
4976 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
4978 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
4981 tmp
= intel_sbi_read(dev_priv
, 0x2038, SBI_MPHY
);
4982 tmp
|= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4983 intel_sbi_write(dev_priv
, 0x2038, tmp
, SBI_MPHY
);
4985 tmp
= intel_sbi_read(dev_priv
, 0x2138, SBI_MPHY
);
4986 tmp
|= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4987 intel_sbi_write(dev_priv
, 0x2138, tmp
, SBI_MPHY
);
4989 tmp
= intel_sbi_read(dev_priv
, 0x203C, SBI_MPHY
);
4991 intel_sbi_write(dev_priv
, 0x203C, tmp
, SBI_MPHY
);
4993 tmp
= intel_sbi_read(dev_priv
, 0x213C, SBI_MPHY
);
4995 intel_sbi_write(dev_priv
, 0x213C, tmp
, SBI_MPHY
);
4998 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
4999 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
5000 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
5002 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
5003 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
5004 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
5007 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
5010 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
5012 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
5015 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
5018 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
5021 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
5023 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
5026 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
5028 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
5029 tmp
&= ~(0xFF << 16);
5030 tmp
|= (0x1C << 16);
5031 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
5033 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
5034 tmp
&= ~(0xFF << 16);
5035 tmp
|= (0x1C << 16);
5036 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
5039 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
5041 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
5043 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
5045 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
5047 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
5048 tmp
&= ~(0xF << 28);
5050 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
5052 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
5053 tmp
&= ~(0xF << 28);
5055 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
5058 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5059 tmp
= intel_sbi_read(dev_priv
, SBI_DBUFF0
, SBI_ICLK
);
5060 tmp
|= SBI_DBUFF0_ENABLE
;
5061 intel_sbi_write(dev_priv
, SBI_DBUFF0
, tmp
, SBI_ICLK
);
5063 mutex_unlock(&dev_priv
->dpio_lock
);
5067 * Initialize reference clocks when the driver loads
5069 void intel_init_pch_refclk(struct drm_device
*dev
)
5071 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
5072 ironlake_init_pch_refclk(dev
);
5073 else if (HAS_PCH_LPT(dev
))
5074 lpt_init_pch_refclk(dev
);
5077 static int ironlake_get_refclk(struct drm_crtc
*crtc
)
5079 struct drm_device
*dev
= crtc
->dev
;
5080 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5081 struct intel_encoder
*encoder
;
5082 struct intel_encoder
*edp_encoder
= NULL
;
5083 int num_connectors
= 0;
5084 bool is_lvds
= false;
5086 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5087 switch (encoder
->type
) {
5088 case INTEL_OUTPUT_LVDS
:
5091 case INTEL_OUTPUT_EDP
:
5092 edp_encoder
= encoder
;
5098 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
5099 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5100 dev_priv
->lvds_ssc_freq
);
5101 return dev_priv
->lvds_ssc_freq
* 1000;
5107 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
,
5108 struct drm_display_mode
*adjusted_mode
,
5111 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
5112 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5113 int pipe
= intel_crtc
->pipe
;
5116 val
= I915_READ(PIPECONF(pipe
));
5118 val
&= ~PIPECONF_BPC_MASK
;
5119 switch (intel_crtc
->config
.pipe_bpp
) {
5121 val
|= PIPECONF_6BPC
;
5124 val
|= PIPECONF_8BPC
;
5127 val
|= PIPECONF_10BPC
;
5130 val
|= PIPECONF_12BPC
;
5133 /* Case prevented by intel_choose_pipe_bpp_dither. */
5137 val
&= ~(PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_MASK
);
5139 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
5141 val
&= ~PIPECONF_INTERLACE_MASK
;
5142 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
5143 val
|= PIPECONF_INTERLACED_ILK
;
5145 val
|= PIPECONF_PROGRESSIVE
;
5147 if (intel_crtc
->config
.limited_color_range
)
5148 val
|= PIPECONF_COLOR_RANGE_SELECT
;
5150 val
&= ~PIPECONF_COLOR_RANGE_SELECT
;
5152 I915_WRITE(PIPECONF(pipe
), val
);
5153 POSTING_READ(PIPECONF(pipe
));
5157 * Set up the pipe CSC unit.
5159 * Currently only full range RGB to limited range RGB conversion
5160 * is supported, but eventually this should handle various
5161 * RGB<->YCbCr scenarios as well.
5163 static void intel_set_pipe_csc(struct drm_crtc
*crtc
)
5165 struct drm_device
*dev
= crtc
->dev
;
5166 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5167 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5168 int pipe
= intel_crtc
->pipe
;
5169 uint16_t coeff
= 0x7800; /* 1.0 */
5172 * TODO: Check what kind of values actually come out of the pipe
5173 * with these coeff/postoff values and adjust to get the best
5174 * accuracy. Perhaps we even need to take the bpc value into
5178 if (intel_crtc
->config
.limited_color_range
)
5179 coeff
= ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5182 * GY/GU and RY/RU should be the other way around according
5183 * to BSpec, but reality doesn't agree. Just set them up in
5184 * a way that results in the correct picture.
5186 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeff
<< 16);
5187 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), 0);
5189 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeff
);
5190 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), 0);
5192 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), 0);
5193 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeff
<< 16);
5195 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
5196 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
5197 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
5199 if (INTEL_INFO(dev
)->gen
> 6) {
5200 uint16_t postoff
= 0;
5202 if (intel_crtc
->config
.limited_color_range
)
5203 postoff
= (16 * (1 << 13) / 255) & 0x1fff;
5205 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
5206 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
5207 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
5209 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
5211 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
5213 if (intel_crtc
->config
.limited_color_range
)
5214 mode
|= CSC_BLACK_SCREEN_OFFSET
;
5216 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
5220 static void haswell_set_pipeconf(struct drm_crtc
*crtc
,
5221 struct drm_display_mode
*adjusted_mode
,
5224 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
5225 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5226 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
5229 val
= I915_READ(PIPECONF(cpu_transcoder
));
5231 val
&= ~(PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_MASK
);
5233 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
5235 val
&= ~PIPECONF_INTERLACE_MASK_HSW
;
5236 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
5237 val
|= PIPECONF_INTERLACED_ILK
;
5239 val
|= PIPECONF_PROGRESSIVE
;
5241 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
5242 POSTING_READ(PIPECONF(cpu_transcoder
));
5245 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
5246 struct drm_display_mode
*adjusted_mode
,
5247 intel_clock_t
*clock
,
5248 bool *has_reduced_clock
,
5249 intel_clock_t
*reduced_clock
)
5251 struct drm_device
*dev
= crtc
->dev
;
5252 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5253 struct intel_encoder
*intel_encoder
;
5255 const intel_limit_t
*limit
;
5256 bool ret
, is_sdvo
= false, is_tv
= false, is_lvds
= false;
5258 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5259 switch (intel_encoder
->type
) {
5260 case INTEL_OUTPUT_LVDS
:
5263 case INTEL_OUTPUT_SDVO
:
5264 case INTEL_OUTPUT_HDMI
:
5266 if (intel_encoder
->needs_tv_clock
)
5269 case INTEL_OUTPUT_TVOUT
:
5275 refclk
= ironlake_get_refclk(crtc
);
5278 * Returns a set of divisors for the desired target clock with the given
5279 * refclk, or FALSE. The returned values represent the clock equation:
5280 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5282 limit
= intel_limit(crtc
, refclk
);
5283 ret
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, NULL
,
5288 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
5290 * Ensure we match the reduced clock's P to the target clock.
5291 * If the clocks don't match, we can't switch the display clock
5292 * by using the FP0/FP1. In such case we will disable the LVDS
5293 * downclock feature.
5295 *has_reduced_clock
= limit
->find_pll(limit
, crtc
,
5296 dev_priv
->lvds_downclock
,
5302 if (is_sdvo
&& is_tv
)
5303 i9xx_adjust_sdvo_tv_clock(to_intel_crtc(crtc
));
5308 static void cpt_enable_fdi_bc_bifurcation(struct drm_device
*dev
)
5310 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5313 temp
= I915_READ(SOUTH_CHICKEN1
);
5314 if (temp
& FDI_BC_BIFURCATION_SELECT
)
5317 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
5318 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
5320 temp
|= FDI_BC_BIFURCATION_SELECT
;
5321 DRM_DEBUG_KMS("enabling fdi C rx\n");
5322 I915_WRITE(SOUTH_CHICKEN1
, temp
);
5323 POSTING_READ(SOUTH_CHICKEN1
);
5326 static bool ironlake_check_fdi_lanes(struct intel_crtc
*intel_crtc
)
5328 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5329 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5330 struct intel_crtc
*pipe_B_crtc
=
5331 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
5333 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5334 intel_crtc
->pipe
, intel_crtc
->fdi_lanes
);
5335 if (intel_crtc
->fdi_lanes
> 4) {
5336 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5337 intel_crtc
->pipe
, intel_crtc
->fdi_lanes
);
5338 /* Clamp lanes to avoid programming the hw with bogus values. */
5339 intel_crtc
->fdi_lanes
= 4;
5344 if (INTEL_INFO(dev
)->num_pipes
== 2)
5347 switch (intel_crtc
->pipe
) {
5351 if (dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]->enabled
&&
5352 intel_crtc
->fdi_lanes
> 2) {
5353 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5354 intel_crtc
->pipe
, intel_crtc
->fdi_lanes
);
5355 /* Clamp lanes to avoid programming the hw with bogus values. */
5356 intel_crtc
->fdi_lanes
= 2;
5361 if (intel_crtc
->fdi_lanes
> 2)
5362 WARN_ON(I915_READ(SOUTH_CHICKEN1
) & FDI_BC_BIFURCATION_SELECT
);
5364 cpt_enable_fdi_bc_bifurcation(dev
);
5368 if (!pipe_B_crtc
->base
.enabled
|| pipe_B_crtc
->fdi_lanes
<= 2) {
5369 if (intel_crtc
->fdi_lanes
> 2) {
5370 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5371 intel_crtc
->pipe
, intel_crtc
->fdi_lanes
);
5372 /* Clamp lanes to avoid programming the hw with bogus values. */
5373 intel_crtc
->fdi_lanes
= 2;
5378 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5382 cpt_enable_fdi_bc_bifurcation(dev
);
5390 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
5393 * Account for spread spectrum to avoid
5394 * oversubscribing the link. Max center spread
5395 * is 2.5%; use 5% for safety's sake.
5397 u32 bps
= target_clock
* bpp
* 21 / 20;
5398 return bps
/ (link_bw
* 8) + 1;
5401 void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
5402 struct intel_link_m_n
*m_n
)
5404 struct drm_device
*dev
= crtc
->base
.dev
;
5405 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5406 int pipe
= crtc
->pipe
;
5408 I915_WRITE(TRANSDATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5409 I915_WRITE(TRANSDATA_N1(pipe
), m_n
->gmch_n
);
5410 I915_WRITE(TRANSDPLINK_M1(pipe
), m_n
->link_m
);
5411 I915_WRITE(TRANSDPLINK_N1(pipe
), m_n
->link_n
);
5414 void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
5415 struct intel_link_m_n
*m_n
)
5417 struct drm_device
*dev
= crtc
->base
.dev
;
5418 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5419 int pipe
= crtc
->pipe
;
5420 enum transcoder transcoder
= crtc
->cpu_transcoder
;
5422 if (INTEL_INFO(dev
)->gen
>= 5) {
5423 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5424 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
5425 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
5426 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
5428 I915_WRITE(PIPE_GMCH_DATA_M(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5429 I915_WRITE(PIPE_GMCH_DATA_N(pipe
), m_n
->gmch_n
);
5430 I915_WRITE(PIPE_DP_LINK_M(pipe
), m_n
->link_m
);
5431 I915_WRITE(PIPE_DP_LINK_N(pipe
), m_n
->link_n
);
5435 static void ironlake_fdi_set_m_n(struct drm_crtc
*crtc
)
5437 struct drm_device
*dev
= crtc
->dev
;
5438 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5439 struct drm_display_mode
*adjusted_mode
=
5440 &intel_crtc
->config
.adjusted_mode
;
5441 struct intel_link_m_n m_n
= {0};
5442 int target_clock
, lane
, link_bw
;
5444 /* FDI is a binary signal running at ~2.7GHz, encoding
5445 * each output octet as 10 bits. The actual frequency
5446 * is stored as a divider into a 100MHz clock, and the
5447 * mode pixel clock is stored in units of 1KHz.
5448 * Hence the bw of each lane in terms of the mode signal
5451 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
5453 if (intel_crtc
->config
.pixel_target_clock
)
5454 target_clock
= intel_crtc
->config
.pixel_target_clock
;
5456 target_clock
= adjusted_mode
->clock
;
5458 lane
= ironlake_get_lanes_required(target_clock
, link_bw
,
5459 intel_crtc
->config
.pipe_bpp
);
5461 intel_crtc
->fdi_lanes
= lane
;
5463 if (intel_crtc
->config
.pixel_multiplier
> 1)
5464 link_bw
*= intel_crtc
->config
.pixel_multiplier
;
5465 intel_link_compute_m_n(intel_crtc
->config
.pipe_bpp
, lane
, target_clock
,
5468 intel_cpu_transcoder_set_m_n(intel_crtc
, &m_n
);
5471 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
5472 intel_clock_t
*clock
, u32 fp
)
5474 struct drm_crtc
*crtc
= &intel_crtc
->base
;
5475 struct drm_device
*dev
= crtc
->dev
;
5476 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5477 struct intel_encoder
*intel_encoder
;
5479 int factor
, num_connectors
= 0;
5480 bool is_lvds
= false, is_sdvo
= false, is_tv
= false;
5482 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5483 switch (intel_encoder
->type
) {
5484 case INTEL_OUTPUT_LVDS
:
5487 case INTEL_OUTPUT_SDVO
:
5488 case INTEL_OUTPUT_HDMI
:
5490 if (intel_encoder
->needs_tv_clock
)
5493 case INTEL_OUTPUT_TVOUT
:
5501 /* Enable autotuning of the PLL clock (if permissible) */
5504 if ((intel_panel_use_ssc(dev_priv
) &&
5505 dev_priv
->lvds_ssc_freq
== 100) ||
5506 intel_is_dual_link_lvds(dev
))
5508 } else if (is_sdvo
&& is_tv
)
5511 if (clock
->m
< factor
* clock
->n
)
5517 dpll
|= DPLLB_MODE_LVDS
;
5519 dpll
|= DPLLB_MODE_DAC_SERIAL
;
5521 if (intel_crtc
->config
.pixel_multiplier
> 1) {
5522 dpll
|= (intel_crtc
->config
.pixel_multiplier
- 1)
5523 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
5525 dpll
|= DPLL_DVO_HIGH_SPEED
;
5527 if (intel_crtc
->config
.has_dp_encoder
&&
5528 intel_crtc
->config
.has_pch_encoder
)
5529 dpll
|= DPLL_DVO_HIGH_SPEED
;
5531 /* compute bitmask from p1 value */
5532 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5534 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
5536 switch (clock
->p2
) {
5538 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
5541 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
5544 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
5547 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
5551 if (is_sdvo
&& is_tv
)
5552 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
5554 /* XXX: just matching BIOS for now */
5555 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5557 else if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
5558 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
5560 dpll
|= PLL_REF_INPUT_DREFCLK
;
5565 static int ironlake_crtc_mode_set(struct drm_crtc
*crtc
,
5567 struct drm_framebuffer
*fb
)
5569 struct drm_device
*dev
= crtc
->dev
;
5570 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5571 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5572 struct drm_display_mode
*adjusted_mode
=
5573 &intel_crtc
->config
.adjusted_mode
;
5574 struct drm_display_mode
*mode
= &intel_crtc
->config
.requested_mode
;
5575 int pipe
= intel_crtc
->pipe
;
5576 int plane
= intel_crtc
->plane
;
5577 int num_connectors
= 0;
5578 intel_clock_t clock
, reduced_clock
;
5579 u32 dpll
, fp
= 0, fp2
= 0;
5580 bool ok
, has_reduced_clock
= false;
5581 bool is_lvds
= false;
5582 struct intel_encoder
*encoder
;
5584 bool dither
, fdi_config_ok
;
5586 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5587 switch (encoder
->type
) {
5588 case INTEL_OUTPUT_LVDS
:
5596 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
5597 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
5599 intel_crtc
->cpu_transcoder
= pipe
;
5601 ok
= ironlake_compute_clocks(crtc
, adjusted_mode
, &clock
,
5602 &has_reduced_clock
, &reduced_clock
);
5604 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5607 /* Compat-code for transition, will disappear. */
5608 if (!intel_crtc
->config
.clock_set
) {
5609 intel_crtc
->config
.dpll
.n
= clock
.n
;
5610 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
5611 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
5612 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
5613 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
5616 /* Ensure that the cursor is valid for the new mode before changing... */
5617 intel_crtc_update_cursor(crtc
, true);
5619 /* determine panel color depth */
5620 dither
= intel_crtc
->config
.dither
;
5621 if (is_lvds
&& dev_priv
->lvds_dither
)
5624 fp
= clock
.n
<< 16 | clock
.m1
<< 8 | clock
.m2
;
5625 if (has_reduced_clock
)
5626 fp2
= reduced_clock
.n
<< 16 | reduced_clock
.m1
<< 8 |
5629 dpll
= ironlake_compute_dpll(intel_crtc
, &clock
, fp
);
5631 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe
);
5632 drm_mode_debug_printmodeline(mode
);
5634 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5635 if (intel_crtc
->config
.has_pch_encoder
) {
5636 struct intel_pch_pll
*pll
;
5638 pll
= intel_get_pch_pll(intel_crtc
, dpll
, fp
);
5640 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5645 intel_put_pch_pll(intel_crtc
);
5647 if (intel_crtc
->config
.has_dp_encoder
)
5648 intel_dp_set_m_n(intel_crtc
);
5650 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5651 if (encoder
->pre_pll_enable
)
5652 encoder
->pre_pll_enable(encoder
);
5654 if (intel_crtc
->pch_pll
) {
5655 I915_WRITE(intel_crtc
->pch_pll
->pll_reg
, dpll
);
5657 /* Wait for the clocks to stabilize. */
5658 POSTING_READ(intel_crtc
->pch_pll
->pll_reg
);
5661 /* The pixel multiplier can only be updated once the
5662 * DPLL is enabled and the clocks are stable.
5664 * So write it again.
5666 I915_WRITE(intel_crtc
->pch_pll
->pll_reg
, dpll
);
5669 intel_crtc
->lowfreq_avail
= false;
5670 if (intel_crtc
->pch_pll
) {
5671 if (is_lvds
&& has_reduced_clock
&& i915_powersave
) {
5672 I915_WRITE(intel_crtc
->pch_pll
->fp1_reg
, fp2
);
5673 intel_crtc
->lowfreq_avail
= true;
5675 I915_WRITE(intel_crtc
->pch_pll
->fp1_reg
, fp
);
5679 intel_set_pipe_timings(intel_crtc
, mode
, adjusted_mode
);
5681 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5682 * ironlake_check_fdi_lanes. */
5683 intel_crtc
->fdi_lanes
= 0;
5684 if (intel_crtc
->config
.has_pch_encoder
)
5685 ironlake_fdi_set_m_n(crtc
);
5687 fdi_config_ok
= ironlake_check_fdi_lanes(intel_crtc
);
5689 ironlake_set_pipeconf(crtc
, adjusted_mode
, dither
);
5691 intel_wait_for_vblank(dev
, pipe
);
5693 /* Set up the display plane register */
5694 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
);
5695 POSTING_READ(DSPCNTR(plane
));
5697 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
5699 intel_update_watermarks(dev
);
5701 intel_update_linetime_watermarks(dev
, pipe
, adjusted_mode
);
5703 return fdi_config_ok
? ret
: -EINVAL
;
5706 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
5707 struct intel_crtc_config
*pipe_config
)
5709 struct drm_device
*dev
= crtc
->base
.dev
;
5710 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5713 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
5714 if (!(tmp
& PIPECONF_ENABLE
))
5717 if (I915_READ(TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
)
5718 pipe_config
->has_pch_encoder
= true;
5723 static void haswell_modeset_global_resources(struct drm_device
*dev
)
5725 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5726 bool enable
= false;
5727 struct intel_crtc
*crtc
;
5728 struct intel_encoder
*encoder
;
5730 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
5731 if (crtc
->pipe
!= PIPE_A
&& crtc
->base
.enabled
)
5733 /* XXX: Should check for edp transcoder here, but thanks to init
5734 * sequence that's not yet available. Just in case desktop eDP
5735 * on PORT D is possible on haswell, too. */
5738 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
5740 if (encoder
->type
!= INTEL_OUTPUT_EDP
&&
5741 encoder
->connectors_active
)
5745 /* Even the eDP panel fitter is outside the always-on well. */
5746 if (dev_priv
->pch_pf_size
)
5749 intel_set_power_well(dev
, enable
);
5752 static int haswell_crtc_mode_set(struct drm_crtc
*crtc
,
5754 struct drm_framebuffer
*fb
)
5756 struct drm_device
*dev
= crtc
->dev
;
5757 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5758 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5759 struct drm_display_mode
*adjusted_mode
=
5760 &intel_crtc
->config
.adjusted_mode
;
5761 struct drm_display_mode
*mode
= &intel_crtc
->config
.requested_mode
;
5762 int pipe
= intel_crtc
->pipe
;
5763 int plane
= intel_crtc
->plane
;
5764 int num_connectors
= 0;
5765 bool is_cpu_edp
= false;
5766 struct intel_encoder
*encoder
;
5770 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5771 switch (encoder
->type
) {
5772 case INTEL_OUTPUT_EDP
:
5773 if (!intel_encoder_is_pch_edp(&encoder
->base
))
5782 intel_crtc
->cpu_transcoder
= TRANSCODER_EDP
;
5784 intel_crtc
->cpu_transcoder
= pipe
;
5786 /* We are not sure yet this won't happen. */
5787 WARN(!HAS_PCH_LPT(dev
), "Unexpected PCH type %d\n",
5788 INTEL_PCH_TYPE(dev
));
5790 WARN(num_connectors
!= 1, "%d connectors attached to pipe %c\n",
5791 num_connectors
, pipe_name(pipe
));
5793 WARN_ON(I915_READ(PIPECONF(intel_crtc
->cpu_transcoder
)) &
5794 (PIPECONF_ENABLE
| I965_PIPECONF_ACTIVE
));
5796 WARN_ON(I915_READ(DSPCNTR(plane
)) & DISPLAY_PLANE_ENABLE
);
5798 if (!intel_ddi_pll_mode_set(crtc
, adjusted_mode
->clock
))
5801 /* Ensure that the cursor is valid for the new mode before changing... */
5802 intel_crtc_update_cursor(crtc
, true);
5804 /* determine panel color depth */
5805 dither
= intel_crtc
->config
.dither
;
5807 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe
);
5808 drm_mode_debug_printmodeline(mode
);
5810 if (intel_crtc
->config
.has_dp_encoder
)
5811 intel_dp_set_m_n(intel_crtc
);
5813 intel_crtc
->lowfreq_avail
= false;
5815 intel_set_pipe_timings(intel_crtc
, mode
, adjusted_mode
);
5817 if (intel_crtc
->config
.has_pch_encoder
)
5818 ironlake_fdi_set_m_n(crtc
);
5820 haswell_set_pipeconf(crtc
, adjusted_mode
, dither
);
5822 intel_set_pipe_csc(crtc
);
5824 /* Set up the display plane register */
5825 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
| DISPPLANE_PIPE_CSC_ENABLE
);
5826 POSTING_READ(DSPCNTR(plane
));
5828 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
5830 intel_update_watermarks(dev
);
5832 intel_update_linetime_watermarks(dev
, pipe
, adjusted_mode
);
5837 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
5838 struct intel_crtc_config
*pipe_config
)
5840 struct drm_device
*dev
= crtc
->base
.dev
;
5841 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5844 tmp
= I915_READ(PIPECONF(crtc
->cpu_transcoder
));
5845 if (!(tmp
& PIPECONF_ENABLE
))
5849 * aswell has only FDI/PCH transcoder A. It is which is connected to
5850 * DDI E. So just check whether this pipe is wired to DDI E and whether
5851 * the PCH transcoder is on.
5853 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(crtc
->pipe
));
5854 if ((tmp
& TRANS_DDI_PORT_MASK
) == TRANS_DDI_SELECT_PORT(PORT_E
) &&
5855 I915_READ(TRANSCONF(PIPE_A
)) & TRANS_ENABLE
)
5856 pipe_config
->has_pch_encoder
= true;
5862 static int intel_crtc_mode_set(struct drm_crtc
*crtc
,
5864 struct drm_framebuffer
*fb
)
5866 struct drm_device
*dev
= crtc
->dev
;
5867 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5868 struct drm_encoder_helper_funcs
*encoder_funcs
;
5869 struct intel_encoder
*encoder
;
5870 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5871 struct drm_display_mode
*adjusted_mode
=
5872 &intel_crtc
->config
.adjusted_mode
;
5873 struct drm_display_mode
*mode
= &intel_crtc
->config
.requested_mode
;
5874 int pipe
= intel_crtc
->pipe
;
5877 drm_vblank_pre_modeset(dev
, pipe
);
5879 ret
= dev_priv
->display
.crtc_mode_set(crtc
, x
, y
, fb
);
5881 drm_vblank_post_modeset(dev
, pipe
);
5886 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5887 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5888 encoder
->base
.base
.id
,
5889 drm_get_encoder_name(&encoder
->base
),
5890 mode
->base
.id
, mode
->name
);
5891 if (encoder
->mode_set
) {
5892 encoder
->mode_set(encoder
);
5894 encoder_funcs
= encoder
->base
.helper_private
;
5895 encoder_funcs
->mode_set(&encoder
->base
, mode
, adjusted_mode
);
5902 static bool intel_eld_uptodate(struct drm_connector
*connector
,
5903 int reg_eldv
, uint32_t bits_eldv
,
5904 int reg_elda
, uint32_t bits_elda
,
5907 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
5908 uint8_t *eld
= connector
->eld
;
5911 i
= I915_READ(reg_eldv
);
5920 i
= I915_READ(reg_elda
);
5922 I915_WRITE(reg_elda
, i
);
5924 for (i
= 0; i
< eld
[2]; i
++)
5925 if (I915_READ(reg_edid
) != *((uint32_t *)eld
+ i
))
5931 static void g4x_write_eld(struct drm_connector
*connector
,
5932 struct drm_crtc
*crtc
)
5934 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
5935 uint8_t *eld
= connector
->eld
;
5940 i
= I915_READ(G4X_AUD_VID_DID
);
5942 if (i
== INTEL_AUDIO_DEVBLC
|| i
== INTEL_AUDIO_DEVCL
)
5943 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
5945 eldv
= G4X_ELDV_DEVCTG
;
5947 if (intel_eld_uptodate(connector
,
5948 G4X_AUD_CNTL_ST
, eldv
,
5949 G4X_AUD_CNTL_ST
, G4X_ELD_ADDR
,
5950 G4X_HDMIW_HDMIEDID
))
5953 i
= I915_READ(G4X_AUD_CNTL_ST
);
5954 i
&= ~(eldv
| G4X_ELD_ADDR
);
5955 len
= (i
>> 9) & 0x1f; /* ELD buffer size */
5956 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
5961 len
= min_t(uint8_t, eld
[2], len
);
5962 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
5963 for (i
= 0; i
< len
; i
++)
5964 I915_WRITE(G4X_HDMIW_HDMIEDID
, *((uint32_t *)eld
+ i
));
5966 i
= I915_READ(G4X_AUD_CNTL_ST
);
5968 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
5971 static void haswell_write_eld(struct drm_connector
*connector
,
5972 struct drm_crtc
*crtc
)
5974 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
5975 uint8_t *eld
= connector
->eld
;
5976 struct drm_device
*dev
= crtc
->dev
;
5977 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5981 int pipe
= to_intel_crtc(crtc
)->pipe
;
5984 int hdmiw_hdmiedid
= HSW_AUD_EDID_DATA(pipe
);
5985 int aud_cntl_st
= HSW_AUD_DIP_ELD_CTRL(pipe
);
5986 int aud_config
= HSW_AUD_CFG(pipe
);
5987 int aud_cntrl_st2
= HSW_AUD_PIN_ELD_CP_VLD
;
5990 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5992 /* Audio output enable */
5993 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5994 tmp
= I915_READ(aud_cntrl_st2
);
5995 tmp
|= (AUDIO_OUTPUT_ENABLE_A
<< (pipe
* 4));
5996 I915_WRITE(aud_cntrl_st2
, tmp
);
5998 /* Wait for 1 vertical blank */
5999 intel_wait_for_vblank(dev
, pipe
);
6001 /* Set ELD valid state */
6002 tmp
= I915_READ(aud_cntrl_st2
);
6003 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp
);
6004 tmp
|= (AUDIO_ELD_VALID_A
<< (pipe
* 4));
6005 I915_WRITE(aud_cntrl_st2
, tmp
);
6006 tmp
= I915_READ(aud_cntrl_st2
);
6007 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp
);
6009 /* Enable HDMI mode */
6010 tmp
= I915_READ(aud_config
);
6011 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp
);
6012 /* clear N_programing_enable and N_value_index */
6013 tmp
&= ~(AUD_CONFIG_N_VALUE_INDEX
| AUD_CONFIG_N_PROG_ENABLE
);
6014 I915_WRITE(aud_config
, tmp
);
6016 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
6018 eldv
= AUDIO_ELD_VALID_A
<< (pipe
* 4);
6019 intel_crtc
->eld_vld
= true;
6021 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
6022 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6023 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6024 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
6026 I915_WRITE(aud_config
, 0);
6028 if (intel_eld_uptodate(connector
,
6029 aud_cntrl_st2
, eldv
,
6030 aud_cntl_st
, IBX_ELD_ADDRESS
,
6034 i
= I915_READ(aud_cntrl_st2
);
6036 I915_WRITE(aud_cntrl_st2
, i
);
6041 i
= I915_READ(aud_cntl_st
);
6042 i
&= ~IBX_ELD_ADDRESS
;
6043 I915_WRITE(aud_cntl_st
, i
);
6044 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
6045 DRM_DEBUG_DRIVER("port num:%d\n", i
);
6047 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
6048 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6049 for (i
= 0; i
< len
; i
++)
6050 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
6052 i
= I915_READ(aud_cntrl_st2
);
6054 I915_WRITE(aud_cntrl_st2
, i
);
6058 static void ironlake_write_eld(struct drm_connector
*connector
,
6059 struct drm_crtc
*crtc
)
6061 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6062 uint8_t *eld
= connector
->eld
;
6070 int pipe
= to_intel_crtc(crtc
)->pipe
;
6072 if (HAS_PCH_IBX(connector
->dev
)) {
6073 hdmiw_hdmiedid
= IBX_HDMIW_HDMIEDID(pipe
);
6074 aud_config
= IBX_AUD_CFG(pipe
);
6075 aud_cntl_st
= IBX_AUD_CNTL_ST(pipe
);
6076 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
6078 hdmiw_hdmiedid
= CPT_HDMIW_HDMIEDID(pipe
);
6079 aud_config
= CPT_AUD_CFG(pipe
);
6080 aud_cntl_st
= CPT_AUD_CNTL_ST(pipe
);
6081 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
6084 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
6086 i
= I915_READ(aud_cntl_st
);
6087 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
6089 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6090 /* operate blindly on all ports */
6091 eldv
= IBX_ELD_VALIDB
;
6092 eldv
|= IBX_ELD_VALIDB
<< 4;
6093 eldv
|= IBX_ELD_VALIDB
<< 8;
6095 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i
);
6096 eldv
= IBX_ELD_VALIDB
<< ((i
- 1) * 4);
6099 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
6100 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6101 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6102 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
6104 I915_WRITE(aud_config
, 0);
6106 if (intel_eld_uptodate(connector
,
6107 aud_cntrl_st2
, eldv
,
6108 aud_cntl_st
, IBX_ELD_ADDRESS
,
6112 i
= I915_READ(aud_cntrl_st2
);
6114 I915_WRITE(aud_cntrl_st2
, i
);
6119 i
= I915_READ(aud_cntl_st
);
6120 i
&= ~IBX_ELD_ADDRESS
;
6121 I915_WRITE(aud_cntl_st
, i
);
6123 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
6124 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6125 for (i
= 0; i
< len
; i
++)
6126 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
6128 i
= I915_READ(aud_cntrl_st2
);
6130 I915_WRITE(aud_cntrl_st2
, i
);
6133 void intel_write_eld(struct drm_encoder
*encoder
,
6134 struct drm_display_mode
*mode
)
6136 struct drm_crtc
*crtc
= encoder
->crtc
;
6137 struct drm_connector
*connector
;
6138 struct drm_device
*dev
= encoder
->dev
;
6139 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6141 connector
= drm_select_eld(encoder
, mode
);
6145 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6147 drm_get_connector_name(connector
),
6148 connector
->encoder
->base
.id
,
6149 drm_get_encoder_name(connector
->encoder
));
6151 connector
->eld
[6] = drm_av_sync_delay(connector
, mode
) / 2;
6153 if (dev_priv
->display
.write_eld
)
6154 dev_priv
->display
.write_eld(connector
, crtc
);
6157 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6158 void intel_crtc_load_lut(struct drm_crtc
*crtc
)
6160 struct drm_device
*dev
= crtc
->dev
;
6161 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6162 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6163 int palreg
= PALETTE(intel_crtc
->pipe
);
6166 /* The clocks have to be on to load the palette. */
6167 if (!crtc
->enabled
|| !intel_crtc
->active
)
6170 /* use legacy palette for Ironlake */
6171 if (HAS_PCH_SPLIT(dev
))
6172 palreg
= LGC_PALETTE(intel_crtc
->pipe
);
6174 for (i
= 0; i
< 256; i
++) {
6175 I915_WRITE(palreg
+ 4 * i
,
6176 (intel_crtc
->lut_r
[i
] << 16) |
6177 (intel_crtc
->lut_g
[i
] << 8) |
6178 intel_crtc
->lut_b
[i
]);
6182 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6184 struct drm_device
*dev
= crtc
->dev
;
6185 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6186 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6187 bool visible
= base
!= 0;
6190 if (intel_crtc
->cursor_visible
== visible
)
6193 cntl
= I915_READ(_CURACNTR
);
6195 /* On these chipsets we can only modify the base whilst
6196 * the cursor is disabled.
6198 I915_WRITE(_CURABASE
, base
);
6200 cntl
&= ~(CURSOR_FORMAT_MASK
);
6201 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6202 cntl
|= CURSOR_ENABLE
|
6203 CURSOR_GAMMA_ENABLE
|
6206 cntl
&= ~(CURSOR_ENABLE
| CURSOR_GAMMA_ENABLE
);
6207 I915_WRITE(_CURACNTR
, cntl
);
6209 intel_crtc
->cursor_visible
= visible
;
6212 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6214 struct drm_device
*dev
= crtc
->dev
;
6215 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6216 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6217 int pipe
= intel_crtc
->pipe
;
6218 bool visible
= base
!= 0;
6220 if (intel_crtc
->cursor_visible
!= visible
) {
6221 uint32_t cntl
= I915_READ(CURCNTR(pipe
));
6223 cntl
&= ~(CURSOR_MODE
| MCURSOR_PIPE_SELECT
);
6224 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
6225 cntl
|= pipe
<< 28; /* Connect to correct pipe */
6227 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
6228 cntl
|= CURSOR_MODE_DISABLE
;
6230 I915_WRITE(CURCNTR(pipe
), cntl
);
6232 intel_crtc
->cursor_visible
= visible
;
6234 /* and commit changes on next vblank */
6235 I915_WRITE(CURBASE(pipe
), base
);
6238 static void ivb_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6240 struct drm_device
*dev
= crtc
->dev
;
6241 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6242 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6243 int pipe
= intel_crtc
->pipe
;
6244 bool visible
= base
!= 0;
6246 if (intel_crtc
->cursor_visible
!= visible
) {
6247 uint32_t cntl
= I915_READ(CURCNTR_IVB(pipe
));
6249 cntl
&= ~CURSOR_MODE
;
6250 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
6252 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
6253 cntl
|= CURSOR_MODE_DISABLE
;
6255 if (IS_HASWELL(dev
))
6256 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
6257 I915_WRITE(CURCNTR_IVB(pipe
), cntl
);
6259 intel_crtc
->cursor_visible
= visible
;
6261 /* and commit changes on next vblank */
6262 I915_WRITE(CURBASE_IVB(pipe
), base
);
6265 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6266 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
6269 struct drm_device
*dev
= crtc
->dev
;
6270 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6271 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6272 int pipe
= intel_crtc
->pipe
;
6273 int x
= intel_crtc
->cursor_x
;
6274 int y
= intel_crtc
->cursor_y
;
6280 if (on
&& crtc
->enabled
&& crtc
->fb
) {
6281 base
= intel_crtc
->cursor_addr
;
6282 if (x
> (int) crtc
->fb
->width
)
6285 if (y
> (int) crtc
->fb
->height
)
6291 if (x
+ intel_crtc
->cursor_width
< 0)
6294 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
6297 pos
|= x
<< CURSOR_X_SHIFT
;
6300 if (y
+ intel_crtc
->cursor_height
< 0)
6303 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
6306 pos
|= y
<< CURSOR_Y_SHIFT
;
6308 visible
= base
!= 0;
6309 if (!visible
&& !intel_crtc
->cursor_visible
)
6312 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
6313 I915_WRITE(CURPOS_IVB(pipe
), pos
);
6314 ivb_update_cursor(crtc
, base
);
6316 I915_WRITE(CURPOS(pipe
), pos
);
6317 if (IS_845G(dev
) || IS_I865G(dev
))
6318 i845_update_cursor(crtc
, base
);
6320 i9xx_update_cursor(crtc
, base
);
6324 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
6325 struct drm_file
*file
,
6327 uint32_t width
, uint32_t height
)
6329 struct drm_device
*dev
= crtc
->dev
;
6330 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6331 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6332 struct drm_i915_gem_object
*obj
;
6336 /* if we want to turn off the cursor ignore width and height */
6338 DRM_DEBUG_KMS("cursor off\n");
6341 mutex_lock(&dev
->struct_mutex
);
6345 /* Currently we only support 64x64 cursors */
6346 if (width
!= 64 || height
!= 64) {
6347 DRM_ERROR("we currently only support 64x64 cursors\n");
6351 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
6352 if (&obj
->base
== NULL
)
6355 if (obj
->base
.size
< width
* height
* 4) {
6356 DRM_ERROR("buffer is to small\n");
6361 /* we only need to pin inside GTT if cursor is non-phy */
6362 mutex_lock(&dev
->struct_mutex
);
6363 if (!dev_priv
->info
->cursor_needs_physical
) {
6366 if (obj
->tiling_mode
) {
6367 DRM_ERROR("cursor cannot be tiled\n");
6372 /* Note that the w/a also requires 2 PTE of padding following
6373 * the bo. We currently fill all unused PTE with the shadow
6374 * page and so we should always have valid PTE following the
6375 * cursor preventing the VT-d warning.
6378 if (need_vtd_wa(dev
))
6379 alignment
= 64*1024;
6381 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, NULL
);
6383 DRM_ERROR("failed to move cursor bo into the GTT\n");
6387 ret
= i915_gem_object_put_fence(obj
);
6389 DRM_ERROR("failed to release fence for cursor");
6393 addr
= obj
->gtt_offset
;
6395 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
6396 ret
= i915_gem_attach_phys_object(dev
, obj
,
6397 (intel_crtc
->pipe
== 0) ? I915_GEM_PHYS_CURSOR_0
: I915_GEM_PHYS_CURSOR_1
,
6400 DRM_ERROR("failed to attach phys object\n");
6403 addr
= obj
->phys_obj
->handle
->busaddr
;
6407 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
6410 if (intel_crtc
->cursor_bo
) {
6411 if (dev_priv
->info
->cursor_needs_physical
) {
6412 if (intel_crtc
->cursor_bo
!= obj
)
6413 i915_gem_detach_phys_object(dev
, intel_crtc
->cursor_bo
);
6415 i915_gem_object_unpin(intel_crtc
->cursor_bo
);
6416 drm_gem_object_unreference(&intel_crtc
->cursor_bo
->base
);
6419 mutex_unlock(&dev
->struct_mutex
);
6421 intel_crtc
->cursor_addr
= addr
;
6422 intel_crtc
->cursor_bo
= obj
;
6423 intel_crtc
->cursor_width
= width
;
6424 intel_crtc
->cursor_height
= height
;
6426 intel_crtc_update_cursor(crtc
, true);
6430 i915_gem_object_unpin(obj
);
6432 mutex_unlock(&dev
->struct_mutex
);
6434 drm_gem_object_unreference_unlocked(&obj
->base
);
6438 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
6440 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6442 intel_crtc
->cursor_x
= x
;
6443 intel_crtc
->cursor_y
= y
;
6445 intel_crtc_update_cursor(crtc
, true);
6450 /** Sets the color ramps on behalf of RandR */
6451 void intel_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
6452 u16 blue
, int regno
)
6454 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6456 intel_crtc
->lut_r
[regno
] = red
>> 8;
6457 intel_crtc
->lut_g
[regno
] = green
>> 8;
6458 intel_crtc
->lut_b
[regno
] = blue
>> 8;
6461 void intel_crtc_fb_gamma_get(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
6462 u16
*blue
, int regno
)
6464 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6466 *red
= intel_crtc
->lut_r
[regno
] << 8;
6467 *green
= intel_crtc
->lut_g
[regno
] << 8;
6468 *blue
= intel_crtc
->lut_b
[regno
] << 8;
6471 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
6472 u16
*blue
, uint32_t start
, uint32_t size
)
6474 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
6475 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6477 for (i
= start
; i
< end
; i
++) {
6478 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
6479 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
6480 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
6483 intel_crtc_load_lut(crtc
);
6486 /* VESA 640x480x72Hz mode to set on the pipe */
6487 static struct drm_display_mode load_detect_mode
= {
6488 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
6489 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
6492 static struct drm_framebuffer
*
6493 intel_framebuffer_create(struct drm_device
*dev
,
6494 struct drm_mode_fb_cmd2
*mode_cmd
,
6495 struct drm_i915_gem_object
*obj
)
6497 struct intel_framebuffer
*intel_fb
;
6500 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
6502 drm_gem_object_unreference_unlocked(&obj
->base
);
6503 return ERR_PTR(-ENOMEM
);
6506 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
6508 drm_gem_object_unreference_unlocked(&obj
->base
);
6510 return ERR_PTR(ret
);
6513 return &intel_fb
->base
;
6517 intel_framebuffer_pitch_for_width(int width
, int bpp
)
6519 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
6520 return ALIGN(pitch
, 64);
6524 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
6526 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
6527 return ALIGN(pitch
* mode
->vdisplay
, PAGE_SIZE
);
6530 static struct drm_framebuffer
*
6531 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
6532 struct drm_display_mode
*mode
,
6535 struct drm_i915_gem_object
*obj
;
6536 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
6538 obj
= i915_gem_alloc_object(dev
,
6539 intel_framebuffer_size_for_mode(mode
, bpp
));
6541 return ERR_PTR(-ENOMEM
);
6543 mode_cmd
.width
= mode
->hdisplay
;
6544 mode_cmd
.height
= mode
->vdisplay
;
6545 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
6547 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
6549 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
6552 static struct drm_framebuffer
*
6553 mode_fits_in_fbdev(struct drm_device
*dev
,
6554 struct drm_display_mode
*mode
)
6556 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6557 struct drm_i915_gem_object
*obj
;
6558 struct drm_framebuffer
*fb
;
6560 if (dev_priv
->fbdev
== NULL
)
6563 obj
= dev_priv
->fbdev
->ifb
.obj
;
6567 fb
= &dev_priv
->fbdev
->ifb
.base
;
6568 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
6569 fb
->bits_per_pixel
))
6572 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
6578 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
6579 struct drm_display_mode
*mode
,
6580 struct intel_load_detect_pipe
*old
)
6582 struct intel_crtc
*intel_crtc
;
6583 struct intel_encoder
*intel_encoder
=
6584 intel_attached_encoder(connector
);
6585 struct drm_crtc
*possible_crtc
;
6586 struct drm_encoder
*encoder
= &intel_encoder
->base
;
6587 struct drm_crtc
*crtc
= NULL
;
6588 struct drm_device
*dev
= encoder
->dev
;
6589 struct drm_framebuffer
*fb
;
6592 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6593 connector
->base
.id
, drm_get_connector_name(connector
),
6594 encoder
->base
.id
, drm_get_encoder_name(encoder
));
6597 * Algorithm gets a little messy:
6599 * - if the connector already has an assigned crtc, use it (but make
6600 * sure it's on first)
6602 * - try to find the first unused crtc that can drive this connector,
6603 * and use that if we find one
6606 /* See if we already have a CRTC for this connector */
6607 if (encoder
->crtc
) {
6608 crtc
= encoder
->crtc
;
6610 mutex_lock(&crtc
->mutex
);
6612 old
->dpms_mode
= connector
->dpms
;
6613 old
->load_detect_temp
= false;
6615 /* Make sure the crtc and connector are running */
6616 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
6617 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
6622 /* Find an unused one (if possible) */
6623 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
6625 if (!(encoder
->possible_crtcs
& (1 << i
)))
6627 if (!possible_crtc
->enabled
) {
6628 crtc
= possible_crtc
;
6634 * If we didn't find an unused CRTC, don't use any.
6637 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6641 mutex_lock(&crtc
->mutex
);
6642 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
6643 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
6645 intel_crtc
= to_intel_crtc(crtc
);
6646 old
->dpms_mode
= connector
->dpms
;
6647 old
->load_detect_temp
= true;
6648 old
->release_fb
= NULL
;
6651 mode
= &load_detect_mode
;
6653 /* We need a framebuffer large enough to accommodate all accesses
6654 * that the plane may generate whilst we perform load detection.
6655 * We can not rely on the fbcon either being present (we get called
6656 * during its initialisation to detect all boot displays, or it may
6657 * not even exist) or that it is large enough to satisfy the
6660 fb
= mode_fits_in_fbdev(dev
, mode
);
6662 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6663 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
6664 old
->release_fb
= fb
;
6666 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6668 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6669 mutex_unlock(&crtc
->mutex
);
6673 if (intel_set_mode(crtc
, mode
, 0, 0, fb
)) {
6674 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6675 if (old
->release_fb
)
6676 old
->release_fb
->funcs
->destroy(old
->release_fb
);
6677 mutex_unlock(&crtc
->mutex
);
6681 /* let the connector get through one full cycle before testing */
6682 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
6686 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
6687 struct intel_load_detect_pipe
*old
)
6689 struct intel_encoder
*intel_encoder
=
6690 intel_attached_encoder(connector
);
6691 struct drm_encoder
*encoder
= &intel_encoder
->base
;
6692 struct drm_crtc
*crtc
= encoder
->crtc
;
6694 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6695 connector
->base
.id
, drm_get_connector_name(connector
),
6696 encoder
->base
.id
, drm_get_encoder_name(encoder
));
6698 if (old
->load_detect_temp
) {
6699 to_intel_connector(connector
)->new_encoder
= NULL
;
6700 intel_encoder
->new_crtc
= NULL
;
6701 intel_set_mode(crtc
, NULL
, 0, 0, NULL
);
6703 if (old
->release_fb
) {
6704 drm_framebuffer_unregister_private(old
->release_fb
);
6705 drm_framebuffer_unreference(old
->release_fb
);
6708 mutex_unlock(&crtc
->mutex
);
6712 /* Switch crtc and encoder back off if necessary */
6713 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
6714 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
6716 mutex_unlock(&crtc
->mutex
);
6719 /* Returns the clock of the currently programmed mode of the given pipe. */
6720 static int intel_crtc_clock_get(struct drm_device
*dev
, struct drm_crtc
*crtc
)
6722 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6723 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6724 int pipe
= intel_crtc
->pipe
;
6725 u32 dpll
= I915_READ(DPLL(pipe
));
6727 intel_clock_t clock
;
6729 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
6730 fp
= I915_READ(FP0(pipe
));
6732 fp
= I915_READ(FP1(pipe
));
6734 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
6735 if (IS_PINEVIEW(dev
)) {
6736 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
6737 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
6739 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
6740 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
6743 if (!IS_GEN2(dev
)) {
6744 if (IS_PINEVIEW(dev
))
6745 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
6746 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
6748 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
6749 DPLL_FPA01_P1_POST_DIV_SHIFT
);
6751 switch (dpll
& DPLL_MODE_MASK
) {
6752 case DPLLB_MODE_DAC_SERIAL
:
6753 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
6756 case DPLLB_MODE_LVDS
:
6757 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
6761 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6762 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
6766 /* XXX: Handle the 100Mhz refclk */
6767 intel_clock(dev
, 96000, &clock
);
6769 bool is_lvds
= (pipe
== 1) && (I915_READ(LVDS
) & LVDS_PORT_EN
);
6772 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
6773 DPLL_FPA01_P1_POST_DIV_SHIFT
);
6776 if ((dpll
& PLL_REF_INPUT_MASK
) ==
6777 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
6778 /* XXX: might not be 66MHz */
6779 intel_clock(dev
, 66000, &clock
);
6781 intel_clock(dev
, 48000, &clock
);
6783 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
6786 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
6787 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
6789 if (dpll
& PLL_P2_DIVIDE_BY_4
)
6794 intel_clock(dev
, 48000, &clock
);
6798 /* XXX: It would be nice to validate the clocks, but we can't reuse
6799 * i830PllIsValid() because it relies on the xf86_config connector
6800 * configuration being accurate, which it isn't necessarily.
6806 /** Returns the currently programmed mode of the given pipe. */
6807 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
6808 struct drm_crtc
*crtc
)
6810 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6811 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6812 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
6813 struct drm_display_mode
*mode
;
6814 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
6815 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
6816 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
6817 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
6819 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
6823 mode
->clock
= intel_crtc_clock_get(dev
, crtc
);
6824 mode
->hdisplay
= (htot
& 0xffff) + 1;
6825 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
6826 mode
->hsync_start
= (hsync
& 0xffff) + 1;
6827 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
6828 mode
->vdisplay
= (vtot
& 0xffff) + 1;
6829 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
6830 mode
->vsync_start
= (vsync
& 0xffff) + 1;
6831 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
6833 drm_mode_set_name(mode
);
6838 static void intel_increase_pllclock(struct drm_crtc
*crtc
)
6840 struct drm_device
*dev
= crtc
->dev
;
6841 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6842 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6843 int pipe
= intel_crtc
->pipe
;
6844 int dpll_reg
= DPLL(pipe
);
6847 if (HAS_PCH_SPLIT(dev
))
6850 if (!dev_priv
->lvds_downclock_avail
)
6853 dpll
= I915_READ(dpll_reg
);
6854 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
6855 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6857 assert_panel_unlocked(dev_priv
, pipe
);
6859 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
6860 I915_WRITE(dpll_reg
, dpll
);
6861 intel_wait_for_vblank(dev
, pipe
);
6863 dpll
= I915_READ(dpll_reg
);
6864 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
6865 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6869 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
6871 struct drm_device
*dev
= crtc
->dev
;
6872 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6873 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6875 if (HAS_PCH_SPLIT(dev
))
6878 if (!dev_priv
->lvds_downclock_avail
)
6882 * Since this is called by a timer, we should never get here in
6885 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
6886 int pipe
= intel_crtc
->pipe
;
6887 int dpll_reg
= DPLL(pipe
);
6890 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6892 assert_panel_unlocked(dev_priv
, pipe
);
6894 dpll
= I915_READ(dpll_reg
);
6895 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
6896 I915_WRITE(dpll_reg
, dpll
);
6897 intel_wait_for_vblank(dev
, pipe
);
6898 dpll
= I915_READ(dpll_reg
);
6899 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
6900 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6905 void intel_mark_busy(struct drm_device
*dev
)
6907 i915_update_gfx_val(dev
->dev_private
);
6910 void intel_mark_idle(struct drm_device
*dev
)
6912 struct drm_crtc
*crtc
;
6914 if (!i915_powersave
)
6917 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
6921 intel_decrease_pllclock(crtc
);
6925 void intel_mark_fb_busy(struct drm_i915_gem_object
*obj
)
6927 struct drm_device
*dev
= obj
->base
.dev
;
6928 struct drm_crtc
*crtc
;
6930 if (!i915_powersave
)
6933 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
6937 if (to_intel_framebuffer(crtc
->fb
)->obj
== obj
)
6938 intel_increase_pllclock(crtc
);
6942 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
6944 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6945 struct drm_device
*dev
= crtc
->dev
;
6946 struct intel_unpin_work
*work
;
6947 unsigned long flags
;
6949 spin_lock_irqsave(&dev
->event_lock
, flags
);
6950 work
= intel_crtc
->unpin_work
;
6951 intel_crtc
->unpin_work
= NULL
;
6952 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6955 cancel_work_sync(&work
->work
);
6959 drm_crtc_cleanup(crtc
);
6964 static void intel_unpin_work_fn(struct work_struct
*__work
)
6966 struct intel_unpin_work
*work
=
6967 container_of(__work
, struct intel_unpin_work
, work
);
6968 struct drm_device
*dev
= work
->crtc
->dev
;
6970 mutex_lock(&dev
->struct_mutex
);
6971 intel_unpin_fb_obj(work
->old_fb_obj
);
6972 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
6973 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
6975 intel_update_fbc(dev
);
6976 mutex_unlock(&dev
->struct_mutex
);
6978 BUG_ON(atomic_read(&to_intel_crtc(work
->crtc
)->unpin_work_count
) == 0);
6979 atomic_dec(&to_intel_crtc(work
->crtc
)->unpin_work_count
);
6984 static void do_intel_finish_page_flip(struct drm_device
*dev
,
6985 struct drm_crtc
*crtc
)
6987 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6988 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6989 struct intel_unpin_work
*work
;
6990 unsigned long flags
;
6992 /* Ignore early vblank irqs */
6993 if (intel_crtc
== NULL
)
6996 spin_lock_irqsave(&dev
->event_lock
, flags
);
6997 work
= intel_crtc
->unpin_work
;
6999 /* Ensure we don't miss a work->pending update ... */
7002 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
7003 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7007 /* and that the unpin work is consistent wrt ->pending. */
7010 intel_crtc
->unpin_work
= NULL
;
7013 drm_send_vblank_event(dev
, intel_crtc
->pipe
, work
->event
);
7015 drm_vblank_put(dev
, intel_crtc
->pipe
);
7017 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7019 wake_up_all(&dev_priv
->pending_flip_queue
);
7021 queue_work(dev_priv
->wq
, &work
->work
);
7023 trace_i915_flip_complete(intel_crtc
->plane
, work
->pending_flip_obj
);
7026 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
7028 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7029 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
7031 do_intel_finish_page_flip(dev
, crtc
);
7034 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
7036 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7037 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
7039 do_intel_finish_page_flip(dev
, crtc
);
7042 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
7044 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7045 struct intel_crtc
*intel_crtc
=
7046 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
7047 unsigned long flags
;
7049 /* NB: An MMIO update of the plane base pointer will also
7050 * generate a page-flip completion irq, i.e. every modeset
7051 * is also accompanied by a spurious intel_prepare_page_flip().
7053 spin_lock_irqsave(&dev
->event_lock
, flags
);
7054 if (intel_crtc
->unpin_work
)
7055 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
7056 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7059 inline static void intel_mark_page_flip_active(struct intel_crtc
*intel_crtc
)
7061 /* Ensure that the work item is consistent when activating it ... */
7063 atomic_set(&intel_crtc
->unpin_work
->pending
, INTEL_FLIP_PENDING
);
7064 /* and that it is marked active as soon as the irq could fire. */
7068 static int intel_gen2_queue_flip(struct drm_device
*dev
,
7069 struct drm_crtc
*crtc
,
7070 struct drm_framebuffer
*fb
,
7071 struct drm_i915_gem_object
*obj
)
7073 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7074 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7076 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7079 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7083 ret
= intel_ring_begin(ring
, 6);
7087 /* Can't queue multiple flips, so wait for the previous
7088 * one to finish before executing the next.
7090 if (intel_crtc
->plane
)
7091 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
7093 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
7094 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
7095 intel_ring_emit(ring
, MI_NOOP
);
7096 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7097 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7098 intel_ring_emit(ring
, fb
->pitches
[0]);
7099 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
7100 intel_ring_emit(ring
, 0); /* aux display base address, unused */
7102 intel_mark_page_flip_active(intel_crtc
);
7103 intel_ring_advance(ring
);
7107 intel_unpin_fb_obj(obj
);
7112 static int intel_gen3_queue_flip(struct drm_device
*dev
,
7113 struct drm_crtc
*crtc
,
7114 struct drm_framebuffer
*fb
,
7115 struct drm_i915_gem_object
*obj
)
7117 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7118 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7120 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7123 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7127 ret
= intel_ring_begin(ring
, 6);
7131 if (intel_crtc
->plane
)
7132 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
7134 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
7135 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
7136 intel_ring_emit(ring
, MI_NOOP
);
7137 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
7138 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7139 intel_ring_emit(ring
, fb
->pitches
[0]);
7140 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
7141 intel_ring_emit(ring
, MI_NOOP
);
7143 intel_mark_page_flip_active(intel_crtc
);
7144 intel_ring_advance(ring
);
7148 intel_unpin_fb_obj(obj
);
7153 static int intel_gen4_queue_flip(struct drm_device
*dev
,
7154 struct drm_crtc
*crtc
,
7155 struct drm_framebuffer
*fb
,
7156 struct drm_i915_gem_object
*obj
)
7158 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7159 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7160 uint32_t pf
, pipesrc
;
7161 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7164 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7168 ret
= intel_ring_begin(ring
, 4);
7172 /* i965+ uses the linear or tiled offsets from the
7173 * Display Registers (which do not change across a page-flip)
7174 * so we need only reprogram the base address.
7176 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7177 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7178 intel_ring_emit(ring
, fb
->pitches
[0]);
7179 intel_ring_emit(ring
,
7180 (obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
) |
7183 /* XXX Enabling the panel-fitter across page-flip is so far
7184 * untested on non-native modes, so ignore it for now.
7185 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7188 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
7189 intel_ring_emit(ring
, pf
| pipesrc
);
7191 intel_mark_page_flip_active(intel_crtc
);
7192 intel_ring_advance(ring
);
7196 intel_unpin_fb_obj(obj
);
7201 static int intel_gen6_queue_flip(struct drm_device
*dev
,
7202 struct drm_crtc
*crtc
,
7203 struct drm_framebuffer
*fb
,
7204 struct drm_i915_gem_object
*obj
)
7206 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7207 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7208 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7209 uint32_t pf
, pipesrc
;
7212 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7216 ret
= intel_ring_begin(ring
, 4);
7220 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7221 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7222 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
7223 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
7225 /* Contrary to the suggestions in the documentation,
7226 * "Enable Panel Fitter" does not seem to be required when page
7227 * flipping with a non-native mode, and worse causes a normal
7229 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7232 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
7233 intel_ring_emit(ring
, pf
| pipesrc
);
7235 intel_mark_page_flip_active(intel_crtc
);
7236 intel_ring_advance(ring
);
7240 intel_unpin_fb_obj(obj
);
7246 * On gen7 we currently use the blit ring because (in early silicon at least)
7247 * the render ring doesn't give us interrpts for page flip completion, which
7248 * means clients will hang after the first flip is queued. Fortunately the
7249 * blit ring generates interrupts properly, so use it instead.
7251 static int intel_gen7_queue_flip(struct drm_device
*dev
,
7252 struct drm_crtc
*crtc
,
7253 struct drm_framebuffer
*fb
,
7254 struct drm_i915_gem_object
*obj
)
7256 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7257 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7258 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[BCS
];
7259 uint32_t plane_bit
= 0;
7262 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7266 switch(intel_crtc
->plane
) {
7268 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
7271 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
7274 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
7277 WARN_ONCE(1, "unknown plane in flip command\n");
7282 ret
= intel_ring_begin(ring
, 4);
7286 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
7287 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
7288 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
7289 intel_ring_emit(ring
, (MI_NOOP
));
7291 intel_mark_page_flip_active(intel_crtc
);
7292 intel_ring_advance(ring
);
7296 intel_unpin_fb_obj(obj
);
7301 static int intel_default_queue_flip(struct drm_device
*dev
,
7302 struct drm_crtc
*crtc
,
7303 struct drm_framebuffer
*fb
,
7304 struct drm_i915_gem_object
*obj
)
7309 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
7310 struct drm_framebuffer
*fb
,
7311 struct drm_pending_vblank_event
*event
)
7313 struct drm_device
*dev
= crtc
->dev
;
7314 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7315 struct drm_framebuffer
*old_fb
= crtc
->fb
;
7316 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(fb
)->obj
;
7317 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7318 struct intel_unpin_work
*work
;
7319 unsigned long flags
;
7322 /* Can't change pixel format via MI display flips. */
7323 if (fb
->pixel_format
!= crtc
->fb
->pixel_format
)
7327 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7328 * Note that pitch changes could also affect these register.
7330 if (INTEL_INFO(dev
)->gen
> 3 &&
7331 (fb
->offsets
[0] != crtc
->fb
->offsets
[0] ||
7332 fb
->pitches
[0] != crtc
->fb
->pitches
[0]))
7335 work
= kzalloc(sizeof *work
, GFP_KERNEL
);
7339 work
->event
= event
;
7341 work
->old_fb_obj
= to_intel_framebuffer(old_fb
)->obj
;
7342 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
7344 ret
= drm_vblank_get(dev
, intel_crtc
->pipe
);
7348 /* We borrow the event spin lock for protecting unpin_work */
7349 spin_lock_irqsave(&dev
->event_lock
, flags
);
7350 if (intel_crtc
->unpin_work
) {
7351 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7353 drm_vblank_put(dev
, intel_crtc
->pipe
);
7355 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7358 intel_crtc
->unpin_work
= work
;
7359 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7361 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
7362 flush_workqueue(dev_priv
->wq
);
7364 ret
= i915_mutex_lock_interruptible(dev
);
7368 /* Reference the objects for the scheduled work. */
7369 drm_gem_object_reference(&work
->old_fb_obj
->base
);
7370 drm_gem_object_reference(&obj
->base
);
7374 work
->pending_flip_obj
= obj
;
7376 work
->enable_stall_check
= true;
7378 atomic_inc(&intel_crtc
->unpin_work_count
);
7379 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
7381 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
);
7383 goto cleanup_pending
;
7385 intel_disable_fbc(dev
);
7386 intel_mark_fb_busy(obj
);
7387 mutex_unlock(&dev
->struct_mutex
);
7389 trace_i915_flip_request(intel_crtc
->plane
, obj
);
7394 atomic_dec(&intel_crtc
->unpin_work_count
);
7396 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
7397 drm_gem_object_unreference(&obj
->base
);
7398 mutex_unlock(&dev
->struct_mutex
);
7401 spin_lock_irqsave(&dev
->event_lock
, flags
);
7402 intel_crtc
->unpin_work
= NULL
;
7403 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7405 drm_vblank_put(dev
, intel_crtc
->pipe
);
7412 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
7413 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
7414 .load_lut
= intel_crtc_load_lut
,
7417 bool intel_encoder_check_is_cloned(struct intel_encoder
*encoder
)
7419 struct intel_encoder
*other_encoder
;
7420 struct drm_crtc
*crtc
= &encoder
->new_crtc
->base
;
7425 list_for_each_entry(other_encoder
,
7426 &crtc
->dev
->mode_config
.encoder_list
,
7429 if (&other_encoder
->new_crtc
->base
!= crtc
||
7430 encoder
== other_encoder
)
7439 static bool intel_encoder_crtc_ok(struct drm_encoder
*encoder
,
7440 struct drm_crtc
*crtc
)
7442 struct drm_device
*dev
;
7443 struct drm_crtc
*tmp
;
7446 WARN(!crtc
, "checking null crtc?\n");
7450 list_for_each_entry(tmp
, &dev
->mode_config
.crtc_list
, head
) {
7456 if (encoder
->possible_crtcs
& crtc_mask
)
7462 * intel_modeset_update_staged_output_state
7464 * Updates the staged output configuration state, e.g. after we've read out the
7467 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
7469 struct intel_encoder
*encoder
;
7470 struct intel_connector
*connector
;
7472 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7474 connector
->new_encoder
=
7475 to_intel_encoder(connector
->base
.encoder
);
7478 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7481 to_intel_crtc(encoder
->base
.crtc
);
7486 * intel_modeset_commit_output_state
7488 * This function copies the stage display pipe configuration to the real one.
7490 static void intel_modeset_commit_output_state(struct drm_device
*dev
)
7492 struct intel_encoder
*encoder
;
7493 struct intel_connector
*connector
;
7495 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7497 connector
->base
.encoder
= &connector
->new_encoder
->base
;
7500 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7502 encoder
->base
.crtc
= &encoder
->new_crtc
->base
;
7507 pipe_config_set_bpp(struct drm_crtc
*crtc
,
7508 struct drm_framebuffer
*fb
,
7509 struct intel_crtc_config
*pipe_config
)
7511 struct drm_device
*dev
= crtc
->dev
;
7512 struct drm_connector
*connector
;
7515 switch (fb
->pixel_format
) {
7517 bpp
= 8*3; /* since we go through a colormap */
7519 case DRM_FORMAT_XRGB1555
:
7520 case DRM_FORMAT_ARGB1555
:
7521 /* checked in intel_framebuffer_init already */
7522 if (WARN_ON(INTEL_INFO(dev
)->gen
> 3))
7524 case DRM_FORMAT_RGB565
:
7525 bpp
= 6*3; /* min is 18bpp */
7527 case DRM_FORMAT_XBGR8888
:
7528 case DRM_FORMAT_ABGR8888
:
7529 /* checked in intel_framebuffer_init already */
7530 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
7532 case DRM_FORMAT_XRGB8888
:
7533 case DRM_FORMAT_ARGB8888
:
7536 case DRM_FORMAT_XRGB2101010
:
7537 case DRM_FORMAT_ARGB2101010
:
7538 case DRM_FORMAT_XBGR2101010
:
7539 case DRM_FORMAT_ABGR2101010
:
7540 /* checked in intel_framebuffer_init already */
7541 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
7545 /* TODO: gen4+ supports 16 bpc floating point, too. */
7547 DRM_DEBUG_KMS("unsupported depth\n");
7551 pipe_config
->pipe_bpp
= bpp
;
7553 /* Clamp display bpp to EDID value */
7554 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7556 if (connector
->encoder
&& connector
->encoder
->crtc
!= crtc
)
7559 /* Don't use an invalid EDID bpc value */
7560 if (connector
->display_info
.bpc
&&
7561 connector
->display_info
.bpc
* 3 < bpp
) {
7562 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7563 bpp
, connector
->display_info
.bpc
*3);
7564 pipe_config
->pipe_bpp
= connector
->display_info
.bpc
*3;
7571 static struct intel_crtc_config
*
7572 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
7573 struct drm_framebuffer
*fb
,
7574 struct drm_display_mode
*mode
)
7576 struct drm_device
*dev
= crtc
->dev
;
7577 struct drm_encoder_helper_funcs
*encoder_funcs
;
7578 struct intel_encoder
*encoder
;
7579 struct intel_crtc_config
*pipe_config
;
7582 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
7584 return ERR_PTR(-ENOMEM
);
7586 drm_mode_copy(&pipe_config
->adjusted_mode
, mode
);
7587 drm_mode_copy(&pipe_config
->requested_mode
, mode
);
7589 plane_bpp
= pipe_config_set_bpp(crtc
, fb
, pipe_config
);
7593 /* Pass our mode to the connectors and the CRTC to give them a chance to
7594 * adjust it according to limitations or connector properties, and also
7595 * a chance to reject the mode entirely.
7597 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7600 if (&encoder
->new_crtc
->base
!= crtc
)
7603 if (encoder
->compute_config
) {
7604 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
7605 DRM_DEBUG_KMS("Encoder config failure\n");
7612 encoder_funcs
= encoder
->base
.helper_private
;
7613 if (!(encoder_funcs
->mode_fixup(&encoder
->base
,
7614 &pipe_config
->requested_mode
,
7615 &pipe_config
->adjusted_mode
))) {
7616 DRM_DEBUG_KMS("Encoder fixup failed\n");
7621 if (!(intel_crtc_compute_config(crtc
, pipe_config
))) {
7622 DRM_DEBUG_KMS("CRTC fixup failed\n");
7625 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc
->base
.id
);
7627 pipe_config
->dither
= pipe_config
->pipe_bpp
!= plane_bpp
;
7628 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7629 plane_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
7634 return ERR_PTR(-EINVAL
);
7637 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7638 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7640 intel_modeset_affected_pipes(struct drm_crtc
*crtc
, unsigned *modeset_pipes
,
7641 unsigned *prepare_pipes
, unsigned *disable_pipes
)
7643 struct intel_crtc
*intel_crtc
;
7644 struct drm_device
*dev
= crtc
->dev
;
7645 struct intel_encoder
*encoder
;
7646 struct intel_connector
*connector
;
7647 struct drm_crtc
*tmp_crtc
;
7649 *disable_pipes
= *modeset_pipes
= *prepare_pipes
= 0;
7651 /* Check which crtcs have changed outputs connected to them, these need
7652 * to be part of the prepare_pipes mask. We don't (yet) support global
7653 * modeset across multiple crtcs, so modeset_pipes will only have one
7654 * bit set at most. */
7655 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7657 if (connector
->base
.encoder
== &connector
->new_encoder
->base
)
7660 if (connector
->base
.encoder
) {
7661 tmp_crtc
= connector
->base
.encoder
->crtc
;
7663 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
7666 if (connector
->new_encoder
)
7668 1 << connector
->new_encoder
->new_crtc
->pipe
;
7671 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7673 if (encoder
->base
.crtc
== &encoder
->new_crtc
->base
)
7676 if (encoder
->base
.crtc
) {
7677 tmp_crtc
= encoder
->base
.crtc
;
7679 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
7682 if (encoder
->new_crtc
)
7683 *prepare_pipes
|= 1 << encoder
->new_crtc
->pipe
;
7686 /* Check for any pipes that will be fully disabled ... */
7687 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
7691 /* Don't try to disable disabled crtcs. */
7692 if (!intel_crtc
->base
.enabled
)
7695 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7697 if (encoder
->new_crtc
== intel_crtc
)
7702 *disable_pipes
|= 1 << intel_crtc
->pipe
;
7706 /* set_mode is also used to update properties on life display pipes. */
7707 intel_crtc
= to_intel_crtc(crtc
);
7709 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
7711 /* We only support modeset on one single crtc, hence we need to do that
7712 * only for the passed in crtc iff we change anything else than just
7715 * This is actually not true, to be fully compatible with the old crtc
7716 * helper we automatically disable _any_ output (i.e. doesn't need to be
7717 * connected to the crtc we're modesetting on) if it's disconnected.
7718 * Which is a rather nutty api (since changed the output configuration
7719 * without userspace's explicit request can lead to confusion), but
7720 * alas. Hence we currently need to modeset on all pipes we prepare. */
7722 *modeset_pipes
= *prepare_pipes
;
7724 /* ... and mask these out. */
7725 *modeset_pipes
&= ~(*disable_pipes
);
7726 *prepare_pipes
&= ~(*disable_pipes
);
7729 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
7731 struct drm_encoder
*encoder
;
7732 struct drm_device
*dev
= crtc
->dev
;
7734 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
7735 if (encoder
->crtc
== crtc
)
7742 intel_modeset_update_state(struct drm_device
*dev
, unsigned prepare_pipes
)
7744 struct intel_encoder
*intel_encoder
;
7745 struct intel_crtc
*intel_crtc
;
7746 struct drm_connector
*connector
;
7748 list_for_each_entry(intel_encoder
, &dev
->mode_config
.encoder_list
,
7750 if (!intel_encoder
->base
.crtc
)
7753 intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
7755 if (prepare_pipes
& (1 << intel_crtc
->pipe
))
7756 intel_encoder
->connectors_active
= false;
7759 intel_modeset_commit_output_state(dev
);
7761 /* Update computed state. */
7762 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
7764 intel_crtc
->base
.enabled
= intel_crtc_in_use(&intel_crtc
->base
);
7767 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
7768 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
7771 intel_crtc
= to_intel_crtc(connector
->encoder
->crtc
);
7773 if (prepare_pipes
& (1 << intel_crtc
->pipe
)) {
7774 struct drm_property
*dpms_property
=
7775 dev
->mode_config
.dpms_property
;
7777 connector
->dpms
= DRM_MODE_DPMS_ON
;
7778 drm_object_property_set_value(&connector
->base
,
7782 intel_encoder
= to_intel_encoder(connector
->encoder
);
7783 intel_encoder
->connectors_active
= true;
7789 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7790 list_for_each_entry((intel_crtc), \
7791 &(dev)->mode_config.crtc_list, \
7793 if (mask & (1 <<(intel_crtc)->pipe)) \
7796 intel_pipe_config_compare(struct intel_crtc_config
*current_config
,
7797 struct intel_crtc_config
*pipe_config
)
7799 if (current_config
->has_pch_encoder
!= pipe_config
->has_pch_encoder
) {
7800 DRM_ERROR("mismatch in has_pch_encoder "
7801 "(expected %i, found %i)\n",
7802 current_config
->has_pch_encoder
,
7803 pipe_config
->has_pch_encoder
);
7811 intel_modeset_check_state(struct drm_device
*dev
)
7813 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7814 struct intel_crtc
*crtc
;
7815 struct intel_encoder
*encoder
;
7816 struct intel_connector
*connector
;
7817 struct intel_crtc_config pipe_config
;
7819 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7821 /* This also checks the encoder/connector hw state with the
7822 * ->get_hw_state callbacks. */
7823 intel_connector_check_state(connector
);
7825 WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
7826 "connector's staged encoder doesn't match current encoder\n");
7829 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7831 bool enabled
= false;
7832 bool active
= false;
7833 enum pipe pipe
, tracked_pipe
;
7835 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7836 encoder
->base
.base
.id
,
7837 drm_get_encoder_name(&encoder
->base
));
7839 WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
7840 "encoder's stage crtc doesn't match current crtc\n");
7841 WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
7842 "encoder's active_connectors set, but no crtc\n");
7844 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7846 if (connector
->base
.encoder
!= &encoder
->base
)
7849 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
7852 WARN(!!encoder
->base
.crtc
!= enabled
,
7853 "encoder's enabled state mismatch "
7854 "(expected %i, found %i)\n",
7855 !!encoder
->base
.crtc
, enabled
);
7856 WARN(active
&& !encoder
->base
.crtc
,
7857 "active encoder with no crtc\n");
7859 WARN(encoder
->connectors_active
!= active
,
7860 "encoder's computed active state doesn't match tracked active state "
7861 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
7863 active
= encoder
->get_hw_state(encoder
, &pipe
);
7864 WARN(active
!= encoder
->connectors_active
,
7865 "encoder's hw state doesn't match sw tracking "
7866 "(expected %i, found %i)\n",
7867 encoder
->connectors_active
, active
);
7869 if (!encoder
->base
.crtc
)
7872 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
7873 WARN(active
&& pipe
!= tracked_pipe
,
7874 "active encoder's pipe doesn't match"
7875 "(expected %i, found %i)\n",
7876 tracked_pipe
, pipe
);
7880 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
7882 bool enabled
= false;
7883 bool active
= false;
7885 DRM_DEBUG_KMS("[CRTC:%d]\n",
7886 crtc
->base
.base
.id
);
7888 WARN(crtc
->active
&& !crtc
->base
.enabled
,
7889 "active crtc, but not enabled in sw tracking\n");
7891 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7893 if (encoder
->base
.crtc
!= &crtc
->base
)
7896 if (encoder
->connectors_active
)
7899 WARN(active
!= crtc
->active
,
7900 "crtc's computed active state doesn't match tracked active state "
7901 "(expected %i, found %i)\n", active
, crtc
->active
);
7902 WARN(enabled
!= crtc
->base
.enabled
,
7903 "crtc's computed enabled state doesn't match tracked enabled state "
7904 "(expected %i, found %i)\n", enabled
, crtc
->base
.enabled
);
7906 memset(&pipe_config
, 0, sizeof(pipe_config
));
7907 active
= dev_priv
->display
.get_pipe_config(crtc
,
7909 WARN(crtc
->active
!= active
,
7910 "crtc active state doesn't match with hw state "
7911 "(expected %i, found %i)\n", crtc
->active
, active
);
7914 !intel_pipe_config_compare(&crtc
->config
, &pipe_config
),
7915 "pipe state doesn't match!\n");
7919 int intel_set_mode(struct drm_crtc
*crtc
,
7920 struct drm_display_mode
*mode
,
7921 int x
, int y
, struct drm_framebuffer
*fb
)
7923 struct drm_device
*dev
= crtc
->dev
;
7924 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7925 struct drm_display_mode
*saved_mode
, *saved_hwmode
;
7926 struct intel_crtc_config
*pipe_config
= NULL
;
7927 struct intel_crtc
*intel_crtc
;
7928 unsigned disable_pipes
, prepare_pipes
, modeset_pipes
;
7931 saved_mode
= kmalloc(2 * sizeof(*saved_mode
), GFP_KERNEL
);
7934 saved_hwmode
= saved_mode
+ 1;
7936 intel_modeset_affected_pipes(crtc
, &modeset_pipes
,
7937 &prepare_pipes
, &disable_pipes
);
7939 *saved_hwmode
= crtc
->hwmode
;
7940 *saved_mode
= crtc
->mode
;
7942 /* Hack: Because we don't (yet) support global modeset on multiple
7943 * crtcs, we don't keep track of the new mode for more than one crtc.
7944 * Hence simply check whether any bit is set in modeset_pipes in all the
7945 * pieces of code that are not yet converted to deal with mutliple crtcs
7946 * changing their mode at the same time. */
7947 if (modeset_pipes
) {
7948 pipe_config
= intel_modeset_pipe_config(crtc
, fb
, mode
);
7949 if (IS_ERR(pipe_config
)) {
7950 ret
= PTR_ERR(pipe_config
);
7957 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7958 modeset_pipes
, prepare_pipes
, disable_pipes
);
7960 for_each_intel_crtc_masked(dev
, disable_pipes
, intel_crtc
)
7961 intel_crtc_disable(&intel_crtc
->base
);
7963 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
7964 if (intel_crtc
->base
.enabled
)
7965 dev_priv
->display
.crtc_disable(&intel_crtc
->base
);
7968 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7969 * to set it here already despite that we pass it down the callchain.
7971 if (modeset_pipes
) {
7973 /* mode_set/enable/disable functions rely on a correct pipe
7975 to_intel_crtc(crtc
)->config
= *pipe_config
;
7978 /* Only after disabling all output pipelines that will be changed can we
7979 * update the the output configuration. */
7980 intel_modeset_update_state(dev
, prepare_pipes
);
7982 if (dev_priv
->display
.modeset_global_resources
)
7983 dev_priv
->display
.modeset_global_resources(dev
);
7985 /* Set up the DPLL and any encoders state that needs to adjust or depend
7988 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
7989 ret
= intel_crtc_mode_set(&intel_crtc
->base
,
7995 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7996 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
)
7997 dev_priv
->display
.crtc_enable(&intel_crtc
->base
);
7999 if (modeset_pipes
) {
8000 /* Store real post-adjustment hardware mode. */
8001 crtc
->hwmode
= pipe_config
->adjusted_mode
;
8003 /* Calculate and store various constants which
8004 * are later needed by vblank and swap-completion
8005 * timestamping. They are derived from true hwmode.
8007 drm_calc_timestamping_constants(crtc
);
8010 /* FIXME: add subpixel order */
8012 if (ret
&& crtc
->enabled
) {
8013 crtc
->hwmode
= *saved_hwmode
;
8014 crtc
->mode
= *saved_mode
;
8016 intel_modeset_check_state(dev
);
8025 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
8027 intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
, crtc
->fb
);
8030 #undef for_each_intel_crtc_masked
8032 static void intel_set_config_free(struct intel_set_config
*config
)
8037 kfree(config
->save_connector_encoders
);
8038 kfree(config
->save_encoder_crtcs
);
8042 static int intel_set_config_save_state(struct drm_device
*dev
,
8043 struct intel_set_config
*config
)
8045 struct drm_encoder
*encoder
;
8046 struct drm_connector
*connector
;
8049 config
->save_encoder_crtcs
=
8050 kcalloc(dev
->mode_config
.num_encoder
,
8051 sizeof(struct drm_crtc
*), GFP_KERNEL
);
8052 if (!config
->save_encoder_crtcs
)
8055 config
->save_connector_encoders
=
8056 kcalloc(dev
->mode_config
.num_connector
,
8057 sizeof(struct drm_encoder
*), GFP_KERNEL
);
8058 if (!config
->save_connector_encoders
)
8061 /* Copy data. Note that driver private data is not affected.
8062 * Should anything bad happen only the expected state is
8063 * restored, not the drivers personal bookkeeping.
8066 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
8067 config
->save_encoder_crtcs
[count
++] = encoder
->crtc
;
8071 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
8072 config
->save_connector_encoders
[count
++] = connector
->encoder
;
8078 static void intel_set_config_restore_state(struct drm_device
*dev
,
8079 struct intel_set_config
*config
)
8081 struct intel_encoder
*encoder
;
8082 struct intel_connector
*connector
;
8086 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
8088 to_intel_crtc(config
->save_encoder_crtcs
[count
++]);
8092 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
8093 connector
->new_encoder
=
8094 to_intel_encoder(config
->save_connector_encoders
[count
++]);
8099 intel_set_config_compute_mode_changes(struct drm_mode_set
*set
,
8100 struct intel_set_config
*config
)
8103 /* We should be able to check here if the fb has the same properties
8104 * and then just flip_or_move it */
8105 if (set
->crtc
->fb
!= set
->fb
) {
8106 /* If we have no fb then treat it as a full mode set */
8107 if (set
->crtc
->fb
== NULL
) {
8108 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8109 config
->mode_changed
= true;
8110 } else if (set
->fb
== NULL
) {
8111 config
->mode_changed
= true;
8112 } else if (set
->fb
->pixel_format
!=
8113 set
->crtc
->fb
->pixel_format
) {
8114 config
->mode_changed
= true;
8116 config
->fb_changed
= true;
8119 if (set
->fb
&& (set
->x
!= set
->crtc
->x
|| set
->y
!= set
->crtc
->y
))
8120 config
->fb_changed
= true;
8122 if (set
->mode
&& !drm_mode_equal(set
->mode
, &set
->crtc
->mode
)) {
8123 DRM_DEBUG_KMS("modes are different, full mode set\n");
8124 drm_mode_debug_printmodeline(&set
->crtc
->mode
);
8125 drm_mode_debug_printmodeline(set
->mode
);
8126 config
->mode_changed
= true;
8131 intel_modeset_stage_output_state(struct drm_device
*dev
,
8132 struct drm_mode_set
*set
,
8133 struct intel_set_config
*config
)
8135 struct drm_crtc
*new_crtc
;
8136 struct intel_connector
*connector
;
8137 struct intel_encoder
*encoder
;
8140 /* The upper layers ensure that we either disable a crtc or have a list
8141 * of connectors. For paranoia, double-check this. */
8142 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
8143 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
8146 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8148 /* Otherwise traverse passed in connector list and get encoders
8150 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
8151 if (set
->connectors
[ro
] == &connector
->base
) {
8152 connector
->new_encoder
= connector
->encoder
;
8157 /* If we disable the crtc, disable all its connectors. Also, if
8158 * the connector is on the changing crtc but not on the new
8159 * connector list, disable it. */
8160 if ((!set
->fb
|| ro
== set
->num_connectors
) &&
8161 connector
->base
.encoder
&&
8162 connector
->base
.encoder
->crtc
== set
->crtc
) {
8163 connector
->new_encoder
= NULL
;
8165 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8166 connector
->base
.base
.id
,
8167 drm_get_connector_name(&connector
->base
));
8171 if (&connector
->new_encoder
->base
!= connector
->base
.encoder
) {
8172 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8173 config
->mode_changed
= true;
8176 /* connector->new_encoder is now updated for all connectors. */
8178 /* Update crtc of enabled connectors. */
8180 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8182 if (!connector
->new_encoder
)
8185 new_crtc
= connector
->new_encoder
->base
.crtc
;
8187 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
8188 if (set
->connectors
[ro
] == &connector
->base
)
8189 new_crtc
= set
->crtc
;
8192 /* Make sure the new CRTC will work with the encoder */
8193 if (!intel_encoder_crtc_ok(&connector
->new_encoder
->base
,
8197 connector
->encoder
->new_crtc
= to_intel_crtc(new_crtc
);
8199 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8200 connector
->base
.base
.id
,
8201 drm_get_connector_name(&connector
->base
),
8205 /* Check for any encoders that needs to be disabled. */
8206 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8208 list_for_each_entry(connector
,
8209 &dev
->mode_config
.connector_list
,
8211 if (connector
->new_encoder
== encoder
) {
8212 WARN_ON(!connector
->new_encoder
->new_crtc
);
8217 encoder
->new_crtc
= NULL
;
8219 /* Only now check for crtc changes so we don't miss encoders
8220 * that will be disabled. */
8221 if (&encoder
->new_crtc
->base
!= encoder
->base
.crtc
) {
8222 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8223 config
->mode_changed
= true;
8226 /* Now we've also updated encoder->new_crtc for all encoders. */
8231 static int intel_crtc_set_config(struct drm_mode_set
*set
)
8233 struct drm_device
*dev
;
8234 struct drm_mode_set save_set
;
8235 struct intel_set_config
*config
;
8240 BUG_ON(!set
->crtc
->helper_private
);
8242 /* Enforce sane interface api - has been abused by the fb helper. */
8243 BUG_ON(!set
->mode
&& set
->fb
);
8244 BUG_ON(set
->fb
&& set
->num_connectors
== 0);
8247 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8248 set
->crtc
->base
.id
, set
->fb
->base
.id
,
8249 (int)set
->num_connectors
, set
->x
, set
->y
);
8251 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
8254 dev
= set
->crtc
->dev
;
8257 config
= kzalloc(sizeof(*config
), GFP_KERNEL
);
8261 ret
= intel_set_config_save_state(dev
, config
);
8265 save_set
.crtc
= set
->crtc
;
8266 save_set
.mode
= &set
->crtc
->mode
;
8267 save_set
.x
= set
->crtc
->x
;
8268 save_set
.y
= set
->crtc
->y
;
8269 save_set
.fb
= set
->crtc
->fb
;
8271 /* Compute whether we need a full modeset, only an fb base update or no
8272 * change at all. In the future we might also check whether only the
8273 * mode changed, e.g. for LVDS where we only change the panel fitter in
8275 intel_set_config_compute_mode_changes(set
, config
);
8277 ret
= intel_modeset_stage_output_state(dev
, set
, config
);
8281 if (config
->mode_changed
) {
8283 DRM_DEBUG_KMS("attempting to set mode from"
8285 drm_mode_debug_printmodeline(set
->mode
);
8288 ret
= intel_set_mode(set
->crtc
, set
->mode
,
8289 set
->x
, set
->y
, set
->fb
);
8291 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8292 set
->crtc
->base
.id
, ret
);
8295 } else if (config
->fb_changed
) {
8296 intel_crtc_wait_for_pending_flips(set
->crtc
);
8298 ret
= intel_pipe_set_base(set
->crtc
,
8299 set
->x
, set
->y
, set
->fb
);
8302 intel_set_config_free(config
);
8307 intel_set_config_restore_state(dev
, config
);
8309 /* Try to restore the config */
8310 if (config
->mode_changed
&&
8311 intel_set_mode(save_set
.crtc
, save_set
.mode
,
8312 save_set
.x
, save_set
.y
, save_set
.fb
))
8313 DRM_ERROR("failed to restore config after modeset failure\n");
8316 intel_set_config_free(config
);
8320 static const struct drm_crtc_funcs intel_crtc_funcs
= {
8321 .cursor_set
= intel_crtc_cursor_set
,
8322 .cursor_move
= intel_crtc_cursor_move
,
8323 .gamma_set
= intel_crtc_gamma_set
,
8324 .set_config
= intel_crtc_set_config
,
8325 .destroy
= intel_crtc_destroy
,
8326 .page_flip
= intel_crtc_page_flip
,
8329 static void intel_cpu_pll_init(struct drm_device
*dev
)
8332 intel_ddi_pll_init(dev
);
8335 static void intel_pch_pll_init(struct drm_device
*dev
)
8337 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8340 if (dev_priv
->num_pch_pll
== 0) {
8341 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8345 for (i
= 0; i
< dev_priv
->num_pch_pll
; i
++) {
8346 dev_priv
->pch_plls
[i
].pll_reg
= _PCH_DPLL(i
);
8347 dev_priv
->pch_plls
[i
].fp0_reg
= _PCH_FP0(i
);
8348 dev_priv
->pch_plls
[i
].fp1_reg
= _PCH_FP1(i
);
8352 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
8354 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8355 struct intel_crtc
*intel_crtc
;
8358 intel_crtc
= kzalloc(sizeof(struct intel_crtc
) + (INTELFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
8359 if (intel_crtc
== NULL
)
8362 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
8364 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
8365 for (i
= 0; i
< 256; i
++) {
8366 intel_crtc
->lut_r
[i
] = i
;
8367 intel_crtc
->lut_g
[i
] = i
;
8368 intel_crtc
->lut_b
[i
] = i
;
8371 /* Swap pipes & planes for FBC on pre-965 */
8372 intel_crtc
->pipe
= pipe
;
8373 intel_crtc
->plane
= pipe
;
8374 intel_crtc
->cpu_transcoder
= pipe
;
8375 if (IS_MOBILE(dev
) && IS_GEN3(dev
)) {
8376 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8377 intel_crtc
->plane
= !pipe
;
8380 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
8381 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
8382 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
8383 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
8385 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
8388 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
8389 struct drm_file
*file
)
8391 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
8392 struct drm_mode_object
*drmmode_obj
;
8393 struct intel_crtc
*crtc
;
8395 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
8398 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
8399 DRM_MODE_OBJECT_CRTC
);
8402 DRM_ERROR("no such CRTC id\n");
8406 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
8407 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
8412 static int intel_encoder_clones(struct intel_encoder
*encoder
)
8414 struct drm_device
*dev
= encoder
->base
.dev
;
8415 struct intel_encoder
*source_encoder
;
8419 list_for_each_entry(source_encoder
,
8420 &dev
->mode_config
.encoder_list
, base
.head
) {
8422 if (encoder
== source_encoder
)
8423 index_mask
|= (1 << entry
);
8425 /* Intel hw has only one MUX where enocoders could be cloned. */
8426 if (encoder
->cloneable
&& source_encoder
->cloneable
)
8427 index_mask
|= (1 << entry
);
8435 static bool has_edp_a(struct drm_device
*dev
)
8437 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8439 if (!IS_MOBILE(dev
))
8442 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
8446 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES
) & ILK_eDP_A_DISABLE
))
8452 static void intel_setup_outputs(struct drm_device
*dev
)
8454 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8455 struct intel_encoder
*encoder
;
8456 bool dpd_is_edp
= false;
8459 has_lvds
= intel_lvds_init(dev
);
8460 if (!has_lvds
&& !HAS_PCH_SPLIT(dev
)) {
8461 /* disable the panel fitter on everything but LVDS */
8462 I915_WRITE(PFIT_CONTROL
, 0);
8465 if (!(HAS_DDI(dev
) && (I915_READ(DDI_BUF_CTL(PORT_A
)) & DDI_A_4_LANES
)))
8466 intel_crt_init(dev
);
8471 /* Haswell uses DDI functions to detect digital outputs */
8472 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
8473 /* DDI A only supports eDP */
8475 intel_ddi_init(dev
, PORT_A
);
8477 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8479 found
= I915_READ(SFUSE_STRAP
);
8481 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
8482 intel_ddi_init(dev
, PORT_B
);
8483 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
8484 intel_ddi_init(dev
, PORT_C
);
8485 if (found
& SFUSE_STRAP_DDID_DETECTED
)
8486 intel_ddi_init(dev
, PORT_D
);
8487 } else if (HAS_PCH_SPLIT(dev
)) {
8489 dpd_is_edp
= intel_dpd_is_edp(dev
);
8492 intel_dp_init(dev
, DP_A
, PORT_A
);
8494 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
8495 /* PCH SDVOB multiplex with HDMIB */
8496 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
8498 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
8499 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
8500 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
8503 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
8504 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
8506 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
8507 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
8509 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
8510 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
8512 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
8513 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
8514 } else if (IS_VALLEYVIEW(dev
)) {
8515 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8516 if (I915_READ(VLV_DISPLAY_BASE
+ DP_C
) & DP_DETECTED
)
8517 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_C
, PORT_C
);
8519 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIB
) & SDVO_DETECTED
) {
8520 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIB
,
8522 if (I915_READ(VLV_DISPLAY_BASE
+ DP_B
) & DP_DETECTED
)
8523 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_B
, PORT_B
);
8525 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
8528 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
8529 DRM_DEBUG_KMS("probing SDVOB\n");
8530 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, true);
8531 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
8532 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8533 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
8536 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
)) {
8537 DRM_DEBUG_KMS("probing DP_B\n");
8538 intel_dp_init(dev
, DP_B
, PORT_B
);
8542 /* Before G4X SDVOC doesn't have its own detect register */
8544 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
8545 DRM_DEBUG_KMS("probing SDVOC\n");
8546 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, false);
8549 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
8551 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
8552 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8553 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
8555 if (SUPPORTS_INTEGRATED_DP(dev
)) {
8556 DRM_DEBUG_KMS("probing DP_C\n");
8557 intel_dp_init(dev
, DP_C
, PORT_C
);
8561 if (SUPPORTS_INTEGRATED_DP(dev
) &&
8562 (I915_READ(DP_D
) & DP_DETECTED
)) {
8563 DRM_DEBUG_KMS("probing DP_D\n");
8564 intel_dp_init(dev
, DP_D
, PORT_D
);
8566 } else if (IS_GEN2(dev
))
8567 intel_dvo_init(dev
);
8569 if (SUPPORTS_TV(dev
))
8572 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
8573 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
8574 encoder
->base
.possible_clones
=
8575 intel_encoder_clones(encoder
);
8578 intel_init_pch_refclk(dev
);
8580 drm_helper_move_panel_connectors_to_head(dev
);
8583 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
8585 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
8587 drm_framebuffer_cleanup(fb
);
8588 drm_gem_object_unreference_unlocked(&intel_fb
->obj
->base
);
8593 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
8594 struct drm_file
*file
,
8595 unsigned int *handle
)
8597 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
8598 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
8600 return drm_gem_handle_create(file
, &obj
->base
, handle
);
8603 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
8604 .destroy
= intel_user_framebuffer_destroy
,
8605 .create_handle
= intel_user_framebuffer_create_handle
,
8608 int intel_framebuffer_init(struct drm_device
*dev
,
8609 struct intel_framebuffer
*intel_fb
,
8610 struct drm_mode_fb_cmd2
*mode_cmd
,
8611 struct drm_i915_gem_object
*obj
)
8615 if (obj
->tiling_mode
== I915_TILING_Y
) {
8616 DRM_DEBUG("hardware does not support tiling Y\n");
8620 if (mode_cmd
->pitches
[0] & 63) {
8621 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8622 mode_cmd
->pitches
[0]);
8626 /* FIXME <= Gen4 stride limits are bit unclear */
8627 if (mode_cmd
->pitches
[0] > 32768) {
8628 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8629 mode_cmd
->pitches
[0]);
8633 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
8634 mode_cmd
->pitches
[0] != obj
->stride
) {
8635 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8636 mode_cmd
->pitches
[0], obj
->stride
);
8640 /* Reject formats not supported by any plane early. */
8641 switch (mode_cmd
->pixel_format
) {
8643 case DRM_FORMAT_RGB565
:
8644 case DRM_FORMAT_XRGB8888
:
8645 case DRM_FORMAT_ARGB8888
:
8647 case DRM_FORMAT_XRGB1555
:
8648 case DRM_FORMAT_ARGB1555
:
8649 if (INTEL_INFO(dev
)->gen
> 3) {
8650 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd
->pixel_format
);
8654 case DRM_FORMAT_XBGR8888
:
8655 case DRM_FORMAT_ABGR8888
:
8656 case DRM_FORMAT_XRGB2101010
:
8657 case DRM_FORMAT_ARGB2101010
:
8658 case DRM_FORMAT_XBGR2101010
:
8659 case DRM_FORMAT_ABGR2101010
:
8660 if (INTEL_INFO(dev
)->gen
< 4) {
8661 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd
->pixel_format
);
8665 case DRM_FORMAT_YUYV
:
8666 case DRM_FORMAT_UYVY
:
8667 case DRM_FORMAT_YVYU
:
8668 case DRM_FORMAT_VYUY
:
8669 if (INTEL_INFO(dev
)->gen
< 5) {
8670 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd
->pixel_format
);
8675 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd
->pixel_format
);
8679 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8680 if (mode_cmd
->offsets
[0] != 0)
8683 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
8684 intel_fb
->obj
= obj
;
8686 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
8688 DRM_ERROR("framebuffer init failed %d\n", ret
);
8695 static struct drm_framebuffer
*
8696 intel_user_framebuffer_create(struct drm_device
*dev
,
8697 struct drm_file
*filp
,
8698 struct drm_mode_fb_cmd2
*mode_cmd
)
8700 struct drm_i915_gem_object
*obj
;
8702 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
8703 mode_cmd
->handles
[0]));
8704 if (&obj
->base
== NULL
)
8705 return ERR_PTR(-ENOENT
);
8707 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
8710 static const struct drm_mode_config_funcs intel_mode_funcs
= {
8711 .fb_create
= intel_user_framebuffer_create
,
8712 .output_poll_changed
= intel_fb_output_poll_changed
,
8715 /* Set up chip specific display functions */
8716 static void intel_init_display(struct drm_device
*dev
)
8718 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8721 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
8722 dev_priv
->display
.crtc_mode_set
= haswell_crtc_mode_set
;
8723 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
8724 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
8725 dev_priv
->display
.off
= haswell_crtc_off
;
8726 dev_priv
->display
.update_plane
= ironlake_update_plane
;
8727 } else if (HAS_PCH_SPLIT(dev
)) {
8728 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
8729 dev_priv
->display
.crtc_mode_set
= ironlake_crtc_mode_set
;
8730 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
8731 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
8732 dev_priv
->display
.off
= ironlake_crtc_off
;
8733 dev_priv
->display
.update_plane
= ironlake_update_plane
;
8735 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
8736 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
8737 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
8738 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
8739 dev_priv
->display
.off
= i9xx_crtc_off
;
8740 dev_priv
->display
.update_plane
= i9xx_update_plane
;
8743 /* Returns the core display clock speed */
8744 if (IS_VALLEYVIEW(dev
))
8745 dev_priv
->display
.get_display_clock_speed
=
8746 valleyview_get_display_clock_speed
;
8747 else if (IS_I945G(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
8748 dev_priv
->display
.get_display_clock_speed
=
8749 i945_get_display_clock_speed
;
8750 else if (IS_I915G(dev
))
8751 dev_priv
->display
.get_display_clock_speed
=
8752 i915_get_display_clock_speed
;
8753 else if (IS_I945GM(dev
) || IS_845G(dev
) || IS_PINEVIEW_M(dev
))
8754 dev_priv
->display
.get_display_clock_speed
=
8755 i9xx_misc_get_display_clock_speed
;
8756 else if (IS_I915GM(dev
))
8757 dev_priv
->display
.get_display_clock_speed
=
8758 i915gm_get_display_clock_speed
;
8759 else if (IS_I865G(dev
))
8760 dev_priv
->display
.get_display_clock_speed
=
8761 i865_get_display_clock_speed
;
8762 else if (IS_I85X(dev
))
8763 dev_priv
->display
.get_display_clock_speed
=
8764 i855_get_display_clock_speed
;
8766 dev_priv
->display
.get_display_clock_speed
=
8767 i830_get_display_clock_speed
;
8769 if (HAS_PCH_SPLIT(dev
)) {
8771 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
8772 dev_priv
->display
.write_eld
= ironlake_write_eld
;
8773 } else if (IS_GEN6(dev
)) {
8774 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
8775 dev_priv
->display
.write_eld
= ironlake_write_eld
;
8776 } else if (IS_IVYBRIDGE(dev
)) {
8777 /* FIXME: detect B0+ stepping and use auto training */
8778 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
8779 dev_priv
->display
.write_eld
= ironlake_write_eld
;
8780 dev_priv
->display
.modeset_global_resources
=
8781 ivb_modeset_global_resources
;
8782 } else if (IS_HASWELL(dev
)) {
8783 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
8784 dev_priv
->display
.write_eld
= haswell_write_eld
;
8785 dev_priv
->display
.modeset_global_resources
=
8786 haswell_modeset_global_resources
;
8788 } else if (IS_G4X(dev
)) {
8789 dev_priv
->display
.write_eld
= g4x_write_eld
;
8792 /* Default just returns -ENODEV to indicate unsupported */
8793 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
8795 switch (INTEL_INFO(dev
)->gen
) {
8797 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
8801 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
8806 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
8810 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
8813 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
8819 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8820 * resume, or other times. This quirk makes sure that's the case for
8823 static void quirk_pipea_force(struct drm_device
*dev
)
8825 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8827 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
8828 DRM_INFO("applying pipe a force quirk\n");
8832 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8834 static void quirk_ssc_force_disable(struct drm_device
*dev
)
8836 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8837 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
8838 DRM_INFO("applying lvds SSC disable quirk\n");
8842 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8845 static void quirk_invert_brightness(struct drm_device
*dev
)
8847 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8848 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
8849 DRM_INFO("applying inverted panel brightness quirk\n");
8852 struct intel_quirk
{
8854 int subsystem_vendor
;
8855 int subsystem_device
;
8856 void (*hook
)(struct drm_device
*dev
);
8859 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8860 struct intel_dmi_quirk
{
8861 void (*hook
)(struct drm_device
*dev
);
8862 const struct dmi_system_id (*dmi_id_list
)[];
8865 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
8867 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
8871 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
8873 .dmi_id_list
= &(const struct dmi_system_id
[]) {
8875 .callback
= intel_dmi_reverse_brightness
,
8876 .ident
= "NCR Corporation",
8877 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
8878 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
8881 { } /* terminating entry */
8883 .hook
= quirk_invert_brightness
,
8887 static struct intel_quirk intel_quirks
[] = {
8888 /* HP Mini needs pipe A force quirk (LP: #322104) */
8889 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
8891 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8892 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
8894 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8895 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
8897 /* 830/845 need to leave pipe A & dpll A up */
8898 { 0x2562, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
8899 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
8901 /* Lenovo U160 cannot use SSC on LVDS */
8902 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
8904 /* Sony Vaio Y cannot use SSC on LVDS */
8905 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
8907 /* Acer Aspire 5734Z must invert backlight brightness */
8908 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
8910 /* Acer/eMachines G725 */
8911 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
8913 /* Acer/eMachines e725 */
8914 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
8916 /* Acer/Packard Bell NCL20 */
8917 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
8919 /* Acer Aspire 4736Z */
8920 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
8923 static void intel_init_quirks(struct drm_device
*dev
)
8925 struct pci_dev
*d
= dev
->pdev
;
8928 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
8929 struct intel_quirk
*q
= &intel_quirks
[i
];
8931 if (d
->device
== q
->device
&&
8932 (d
->subsystem_vendor
== q
->subsystem_vendor
||
8933 q
->subsystem_vendor
== PCI_ANY_ID
) &&
8934 (d
->subsystem_device
== q
->subsystem_device
||
8935 q
->subsystem_device
== PCI_ANY_ID
))
8938 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
8939 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
8940 intel_dmi_quirks
[i
].hook(dev
);
8944 /* Disable the VGA plane that we never use */
8945 static void i915_disable_vga(struct drm_device
*dev
)
8947 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8949 u32 vga_reg
= i915_vgacntrl_reg(dev
);
8951 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
8952 outb(SR01
, VGA_SR_INDEX
);
8953 sr1
= inb(VGA_SR_DATA
);
8954 outb(sr1
| 1<<5, VGA_SR_DATA
);
8955 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
8958 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
8959 POSTING_READ(vga_reg
);
8962 void intel_modeset_init_hw(struct drm_device
*dev
)
8964 intel_init_power_well(dev
);
8966 intel_prepare_ddi(dev
);
8968 intel_init_clock_gating(dev
);
8970 mutex_lock(&dev
->struct_mutex
);
8971 intel_enable_gt_powersave(dev
);
8972 mutex_unlock(&dev
->struct_mutex
);
8975 void intel_modeset_init(struct drm_device
*dev
)
8977 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8980 drm_mode_config_init(dev
);
8982 dev
->mode_config
.min_width
= 0;
8983 dev
->mode_config
.min_height
= 0;
8985 dev
->mode_config
.preferred_depth
= 24;
8986 dev
->mode_config
.prefer_shadow
= 1;
8988 dev
->mode_config
.funcs
= &intel_mode_funcs
;
8990 intel_init_quirks(dev
);
8994 if (INTEL_INFO(dev
)->num_pipes
== 0)
8997 intel_init_display(dev
);
9000 dev
->mode_config
.max_width
= 2048;
9001 dev
->mode_config
.max_height
= 2048;
9002 } else if (IS_GEN3(dev
)) {
9003 dev
->mode_config
.max_width
= 4096;
9004 dev
->mode_config
.max_height
= 4096;
9006 dev
->mode_config
.max_width
= 8192;
9007 dev
->mode_config
.max_height
= 8192;
9009 dev
->mode_config
.fb_base
= dev_priv
->gtt
.mappable_base
;
9011 DRM_DEBUG_KMS("%d display pipe%s available.\n",
9012 INTEL_INFO(dev
)->num_pipes
,
9013 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
9015 for (i
= 0; i
< INTEL_INFO(dev
)->num_pipes
; i
++) {
9016 intel_crtc_init(dev
, i
);
9017 for (j
= 0; j
< dev_priv
->num_plane
; j
++) {
9018 ret
= intel_plane_init(dev
, i
, j
);
9020 DRM_DEBUG_KMS("pipe %d plane %d init failed: %d\n",
9025 intel_cpu_pll_init(dev
);
9026 intel_pch_pll_init(dev
);
9028 /* Just disable it once at startup */
9029 i915_disable_vga(dev
);
9030 intel_setup_outputs(dev
);
9032 /* Just in case the BIOS is doing something questionable. */
9033 intel_disable_fbc(dev
);
9037 intel_connector_break_all_links(struct intel_connector
*connector
)
9039 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
9040 connector
->base
.encoder
= NULL
;
9041 connector
->encoder
->connectors_active
= false;
9042 connector
->encoder
->base
.crtc
= NULL
;
9045 static void intel_enable_pipe_a(struct drm_device
*dev
)
9047 struct intel_connector
*connector
;
9048 struct drm_connector
*crt
= NULL
;
9049 struct intel_load_detect_pipe load_detect_temp
;
9051 /* We can't just switch on the pipe A, we need to set things up with a
9052 * proper mode and output configuration. As a gross hack, enable pipe A
9053 * by enabling the load detect pipe once. */
9054 list_for_each_entry(connector
,
9055 &dev
->mode_config
.connector_list
,
9057 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
9058 crt
= &connector
->base
;
9066 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
))
9067 intel_release_load_detect_pipe(crt
, &load_detect_temp
);
9073 intel_check_plane_mapping(struct intel_crtc
*crtc
)
9075 struct drm_device
*dev
= crtc
->base
.dev
;
9076 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9079 if (INTEL_INFO(dev
)->num_pipes
== 1)
9082 reg
= DSPCNTR(!crtc
->plane
);
9083 val
= I915_READ(reg
);
9085 if ((val
& DISPLAY_PLANE_ENABLE
) &&
9086 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
9092 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
9094 struct drm_device
*dev
= crtc
->base
.dev
;
9095 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9098 /* Clear any frame start delays used for debugging left by the BIOS */
9099 reg
= PIPECONF(crtc
->cpu_transcoder
);
9100 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
9102 /* We need to sanitize the plane -> pipe mapping first because this will
9103 * disable the crtc (and hence change the state) if it is wrong. Note
9104 * that gen4+ has a fixed plane -> pipe mapping. */
9105 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
9106 struct intel_connector
*connector
;
9109 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9110 crtc
->base
.base
.id
);
9112 /* Pipe has the wrong plane attached and the plane is active.
9113 * Temporarily change the plane mapping and disable everything
9115 plane
= crtc
->plane
;
9116 crtc
->plane
= !plane
;
9117 dev_priv
->display
.crtc_disable(&crtc
->base
);
9118 crtc
->plane
= plane
;
9120 /* ... and break all links. */
9121 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9123 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
9126 intel_connector_break_all_links(connector
);
9129 WARN_ON(crtc
->active
);
9130 crtc
->base
.enabled
= false;
9133 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
9134 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
9135 /* BIOS forgot to enable pipe A, this mostly happens after
9136 * resume. Force-enable the pipe to fix this, the update_dpms
9137 * call below we restore the pipe to the right state, but leave
9138 * the required bits on. */
9139 intel_enable_pipe_a(dev
);
9142 /* Adjust the state of the output pipe according to whether we
9143 * have active connectors/encoders. */
9144 intel_crtc_update_dpms(&crtc
->base
);
9146 if (crtc
->active
!= crtc
->base
.enabled
) {
9147 struct intel_encoder
*encoder
;
9149 /* This can happen either due to bugs in the get_hw_state
9150 * functions or because the pipe is force-enabled due to the
9152 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9154 crtc
->base
.enabled
? "enabled" : "disabled",
9155 crtc
->active
? "enabled" : "disabled");
9157 crtc
->base
.enabled
= crtc
->active
;
9159 /* Because we only establish the connector -> encoder ->
9160 * crtc links if something is active, this means the
9161 * crtc is now deactivated. Break the links. connector
9162 * -> encoder links are only establish when things are
9163 * actually up, hence no need to break them. */
9164 WARN_ON(crtc
->active
);
9166 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
9167 WARN_ON(encoder
->connectors_active
);
9168 encoder
->base
.crtc
= NULL
;
9173 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
9175 struct intel_connector
*connector
;
9176 struct drm_device
*dev
= encoder
->base
.dev
;
9178 /* We need to check both for a crtc link (meaning that the
9179 * encoder is active and trying to read from a pipe) and the
9180 * pipe itself being active. */
9181 bool has_active_crtc
= encoder
->base
.crtc
&&
9182 to_intel_crtc(encoder
->base
.crtc
)->active
;
9184 if (encoder
->connectors_active
&& !has_active_crtc
) {
9185 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9186 encoder
->base
.base
.id
,
9187 drm_get_encoder_name(&encoder
->base
));
9189 /* Connector is active, but has no active pipe. This is
9190 * fallout from our resume register restoring. Disable
9191 * the encoder manually again. */
9192 if (encoder
->base
.crtc
) {
9193 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9194 encoder
->base
.base
.id
,
9195 drm_get_encoder_name(&encoder
->base
));
9196 encoder
->disable(encoder
);
9199 /* Inconsistent output/port/pipe state happens presumably due to
9200 * a bug in one of the get_hw_state functions. Or someplace else
9201 * in our code, like the register restore mess on resume. Clamp
9202 * things to off as a safer default. */
9203 list_for_each_entry(connector
,
9204 &dev
->mode_config
.connector_list
,
9206 if (connector
->encoder
!= encoder
)
9209 intel_connector_break_all_links(connector
);
9212 /* Enabled encoders without active connectors will be fixed in
9213 * the crtc fixup. */
9216 void i915_redisable_vga(struct drm_device
*dev
)
9218 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9219 u32 vga_reg
= i915_vgacntrl_reg(dev
);
9221 if (I915_READ(vga_reg
) != VGA_DISP_DISABLE
) {
9222 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9223 i915_disable_vga(dev
);
9227 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9228 * and i915 state tracking structures. */
9229 void intel_modeset_setup_hw_state(struct drm_device
*dev
,
9232 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9235 struct drm_plane
*plane
;
9236 struct intel_crtc
*crtc
;
9237 struct intel_encoder
*encoder
;
9238 struct intel_connector
*connector
;
9241 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
9243 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
9244 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
9245 case TRANS_DDI_EDP_INPUT_A_ON
:
9246 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
9249 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
9252 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
9256 /* A bogus value has been programmed, disable
9258 WARN(1, "Bogus eDP source %08x\n", tmp
);
9259 intel_ddi_disable_transcoder_func(dev_priv
,
9264 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
9265 crtc
->cpu_transcoder
= TRANSCODER_EDP
;
9267 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9273 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
9275 memset(&crtc
->config
, 0, sizeof(crtc
->config
));
9276 crtc
->active
= dev_priv
->display
.get_pipe_config(crtc
,
9279 crtc
->base
.enabled
= crtc
->active
;
9281 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9283 crtc
->active
? "enabled" : "disabled");
9287 intel_ddi_setup_hw_pll_state(dev
);
9289 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9293 if (encoder
->get_hw_state(encoder
, &pipe
)) {
9294 encoder
->base
.crtc
=
9295 dev_priv
->pipe_to_crtc_mapping
[pipe
];
9297 encoder
->base
.crtc
= NULL
;
9300 encoder
->connectors_active
= false;
9301 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9302 encoder
->base
.base
.id
,
9303 drm_get_encoder_name(&encoder
->base
),
9304 encoder
->base
.crtc
? "enabled" : "disabled",
9308 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9310 if (connector
->get_hw_state(connector
)) {
9311 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
9312 connector
->encoder
->connectors_active
= true;
9313 connector
->base
.encoder
= &connector
->encoder
->base
;
9315 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
9316 connector
->base
.encoder
= NULL
;
9318 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9319 connector
->base
.base
.id
,
9320 drm_get_connector_name(&connector
->base
),
9321 connector
->base
.encoder
? "enabled" : "disabled");
9324 /* HW state is read out, now we need to sanitize this mess. */
9325 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9327 intel_sanitize_encoder(encoder
);
9330 for_each_pipe(pipe
) {
9331 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
9332 intel_sanitize_crtc(crtc
);
9335 if (force_restore
) {
9336 for_each_pipe(pipe
) {
9337 struct drm_crtc
*crtc
=
9338 dev_priv
->pipe_to_crtc_mapping
[pipe
];
9339 intel_crtc_restore_mode(crtc
);
9341 list_for_each_entry(plane
, &dev
->mode_config
.plane_list
, head
)
9342 intel_plane_restore(plane
);
9344 i915_redisable_vga(dev
);
9346 intel_modeset_update_staged_output_state(dev
);
9349 intel_modeset_check_state(dev
);
9351 drm_mode_config_reset(dev
);
9354 void intel_modeset_gem_init(struct drm_device
*dev
)
9356 intel_modeset_init_hw(dev
);
9358 intel_setup_overlay(dev
);
9360 intel_modeset_setup_hw_state(dev
, false);
9363 void intel_modeset_cleanup(struct drm_device
*dev
)
9365 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9366 struct drm_crtc
*crtc
;
9367 struct intel_crtc
*intel_crtc
;
9369 drm_kms_helper_poll_fini(dev
);
9370 mutex_lock(&dev
->struct_mutex
);
9372 intel_unregister_dsm_handler();
9375 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
9376 /* Skip inactive CRTCs */
9380 intel_crtc
= to_intel_crtc(crtc
);
9381 intel_increase_pllclock(crtc
);
9384 intel_disable_fbc(dev
);
9386 intel_disable_gt_powersave(dev
);
9388 ironlake_teardown_rc6(dev
);
9390 if (IS_VALLEYVIEW(dev
))
9393 mutex_unlock(&dev
->struct_mutex
);
9395 /* Disable the irq before mode object teardown, for the irq might
9396 * enqueue unpin/hotplug work. */
9397 drm_irq_uninstall(dev
);
9398 cancel_work_sync(&dev_priv
->hotplug_work
);
9399 cancel_work_sync(&dev_priv
->rps
.work
);
9401 /* flush any delayed tasks or pending work */
9402 flush_scheduled_work();
9404 drm_mode_config_cleanup(dev
);
9406 intel_cleanup_overlay(dev
);
9410 * Return which encoder is currently attached for connector.
9412 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
9414 return &intel_attached_encoder(connector
)->base
;
9417 void intel_connector_attach_encoder(struct intel_connector
*connector
,
9418 struct intel_encoder
*encoder
)
9420 connector
->encoder
= encoder
;
9421 drm_mode_connector_attach_encoder(&connector
->base
,
9426 * set vga decode state - true == enable VGA decode
9428 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
9430 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9433 pci_read_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, &gmch_ctrl
);
9435 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
9437 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
9438 pci_write_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, gmch_ctrl
);
9442 #ifdef CONFIG_DEBUG_FS
9443 #include <linux/seq_file.h>
9445 struct intel_display_error_state
{
9446 struct intel_cursor_error_state
{
9451 } cursor
[I915_MAX_PIPES
];
9453 struct intel_pipe_error_state
{
9463 } pipe
[I915_MAX_PIPES
];
9465 struct intel_plane_error_state
{
9473 } plane
[I915_MAX_PIPES
];
9476 struct intel_display_error_state
*
9477 intel_display_capture_error_state(struct drm_device
*dev
)
9479 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
9480 struct intel_display_error_state
*error
;
9481 enum transcoder cpu_transcoder
;
9484 error
= kmalloc(sizeof(*error
), GFP_ATOMIC
);
9489 cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
, i
);
9491 if (INTEL_INFO(dev
)->gen
<= 6 || IS_VALLEYVIEW(dev
)) {
9492 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
9493 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
9494 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
9496 error
->cursor
[i
].control
= I915_READ(CURCNTR_IVB(i
));
9497 error
->cursor
[i
].position
= I915_READ(CURPOS_IVB(i
));
9498 error
->cursor
[i
].base
= I915_READ(CURBASE_IVB(i
));
9501 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
9502 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
9503 if (INTEL_INFO(dev
)->gen
<= 3) {
9504 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
9505 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
9507 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
9508 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
9509 if (INTEL_INFO(dev
)->gen
>= 4) {
9510 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
9511 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
9514 error
->pipe
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
9515 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
9516 error
->pipe
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
9517 error
->pipe
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
9518 error
->pipe
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
9519 error
->pipe
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
9520 error
->pipe
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
9521 error
->pipe
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
9528 intel_display_print_error_state(struct seq_file
*m
,
9529 struct drm_device
*dev
,
9530 struct intel_display_error_state
*error
)
9534 seq_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
9536 seq_printf(m
, "Pipe [%d]:\n", i
);
9537 seq_printf(m
, " CONF: %08x\n", error
->pipe
[i
].conf
);
9538 seq_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
9539 seq_printf(m
, " HTOTAL: %08x\n", error
->pipe
[i
].htotal
);
9540 seq_printf(m
, " HBLANK: %08x\n", error
->pipe
[i
].hblank
);
9541 seq_printf(m
, " HSYNC: %08x\n", error
->pipe
[i
].hsync
);
9542 seq_printf(m
, " VTOTAL: %08x\n", error
->pipe
[i
].vtotal
);
9543 seq_printf(m
, " VBLANK: %08x\n", error
->pipe
[i
].vblank
);
9544 seq_printf(m
, " VSYNC: %08x\n", error
->pipe
[i
].vsync
);
9546 seq_printf(m
, "Plane [%d]:\n", i
);
9547 seq_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
9548 seq_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
9549 if (INTEL_INFO(dev
)->gen
<= 3) {
9550 seq_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
9551 seq_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
9553 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
9554 seq_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
9555 if (INTEL_INFO(dev
)->gen
>= 4) {
9556 seq_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
9557 seq_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
9560 seq_printf(m
, "Cursor [%d]:\n", i
);
9561 seq_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
9562 seq_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
9563 seq_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);