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drm/i915: optimize vblank waits in set_base_atomic
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
43
44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
45 static void intel_increase_pllclock(struct drm_crtc *crtc);
46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
47
48 typedef struct {
49 int min, max;
50 } intel_range_t;
51
52 typedef struct {
53 int dot_limit;
54 int p2_slow, p2_fast;
55 } intel_p2_t;
56
57 #define INTEL_P2_NUM 2
58 typedef struct intel_limit intel_limit_t;
59 struct intel_limit {
60 intel_range_t dot, vco, n, m, m1, m2, p, p1;
61 intel_p2_t p2;
62 /**
63 * find_pll() - Find the best values for the PLL
64 * @limit: limits for the PLL
65 * @crtc: current CRTC
66 * @target: target frequency in kHz
67 * @refclk: reference clock frequency in kHz
68 * @match_clock: if provided, @best_clock P divider must
69 * match the P divider from @match_clock
70 * used for LVDS downclocking
71 * @best_clock: best PLL values found
72 *
73 * Returns true on success, false on failure.
74 */
75 bool (*find_pll)(const intel_limit_t *limit,
76 struct drm_crtc *crtc,
77 int target, int refclk,
78 intel_clock_t *match_clock,
79 intel_clock_t *best_clock);
80 };
81
82 /* FDI */
83 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
84
85 int
86 intel_pch_rawclk(struct drm_device *dev)
87 {
88 struct drm_i915_private *dev_priv = dev->dev_private;
89
90 WARN_ON(!HAS_PCH_SPLIT(dev));
91
92 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
93 }
94
95 static bool
96 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
97 int target, int refclk, intel_clock_t *match_clock,
98 intel_clock_t *best_clock);
99 static bool
100 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
101 int target, int refclk, intel_clock_t *match_clock,
102 intel_clock_t *best_clock);
103
104 static bool
105 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
106 int target, int refclk, intel_clock_t *match_clock,
107 intel_clock_t *best_clock);
108
109 static inline u32 /* units of 100MHz */
110 intel_fdi_link_freq(struct drm_device *dev)
111 {
112 if (IS_GEN5(dev)) {
113 struct drm_i915_private *dev_priv = dev->dev_private;
114 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
115 } else
116 return 27;
117 }
118
119 static const intel_limit_t intel_limits_i8xx_dvo = {
120 .dot = { .min = 25000, .max = 350000 },
121 .vco = { .min = 930000, .max = 1400000 },
122 .n = { .min = 3, .max = 16 },
123 .m = { .min = 96, .max = 140 },
124 .m1 = { .min = 18, .max = 26 },
125 .m2 = { .min = 6, .max = 16 },
126 .p = { .min = 4, .max = 128 },
127 .p1 = { .min = 2, .max = 33 },
128 .p2 = { .dot_limit = 165000,
129 .p2_slow = 4, .p2_fast = 2 },
130 .find_pll = intel_find_best_PLL,
131 };
132
133 static const intel_limit_t intel_limits_i8xx_lvds = {
134 .dot = { .min = 25000, .max = 350000 },
135 .vco = { .min = 930000, .max = 1400000 },
136 .n = { .min = 3, .max = 16 },
137 .m = { .min = 96, .max = 140 },
138 .m1 = { .min = 18, .max = 26 },
139 .m2 = { .min = 6, .max = 16 },
140 .p = { .min = 4, .max = 128 },
141 .p1 = { .min = 1, .max = 6 },
142 .p2 = { .dot_limit = 165000,
143 .p2_slow = 14, .p2_fast = 7 },
144 .find_pll = intel_find_best_PLL,
145 };
146
147 static const intel_limit_t intel_limits_i9xx_sdvo = {
148 .dot = { .min = 20000, .max = 400000 },
149 .vco = { .min = 1400000, .max = 2800000 },
150 .n = { .min = 1, .max = 6 },
151 .m = { .min = 70, .max = 120 },
152 .m1 = { .min = 8, .max = 18 },
153 .m2 = { .min = 3, .max = 7 },
154 .p = { .min = 5, .max = 80 },
155 .p1 = { .min = 1, .max = 8 },
156 .p2 = { .dot_limit = 200000,
157 .p2_slow = 10, .p2_fast = 5 },
158 .find_pll = intel_find_best_PLL,
159 };
160
161 static const intel_limit_t intel_limits_i9xx_lvds = {
162 .dot = { .min = 20000, .max = 400000 },
163 .vco = { .min = 1400000, .max = 2800000 },
164 .n = { .min = 1, .max = 6 },
165 .m = { .min = 70, .max = 120 },
166 .m1 = { .min = 8, .max = 18 },
167 .m2 = { .min = 3, .max = 7 },
168 .p = { .min = 7, .max = 98 },
169 .p1 = { .min = 1, .max = 8 },
170 .p2 = { .dot_limit = 112000,
171 .p2_slow = 14, .p2_fast = 7 },
172 .find_pll = intel_find_best_PLL,
173 };
174
175
176 static const intel_limit_t intel_limits_g4x_sdvo = {
177 .dot = { .min = 25000, .max = 270000 },
178 .vco = { .min = 1750000, .max = 3500000},
179 .n = { .min = 1, .max = 4 },
180 .m = { .min = 104, .max = 138 },
181 .m1 = { .min = 17, .max = 23 },
182 .m2 = { .min = 5, .max = 11 },
183 .p = { .min = 10, .max = 30 },
184 .p1 = { .min = 1, .max = 3},
185 .p2 = { .dot_limit = 270000,
186 .p2_slow = 10,
187 .p2_fast = 10
188 },
189 .find_pll = intel_g4x_find_best_PLL,
190 };
191
192 static const intel_limit_t intel_limits_g4x_hdmi = {
193 .dot = { .min = 22000, .max = 400000 },
194 .vco = { .min = 1750000, .max = 3500000},
195 .n = { .min = 1, .max = 4 },
196 .m = { .min = 104, .max = 138 },
197 .m1 = { .min = 16, .max = 23 },
198 .m2 = { .min = 5, .max = 11 },
199 .p = { .min = 5, .max = 80 },
200 .p1 = { .min = 1, .max = 8},
201 .p2 = { .dot_limit = 165000,
202 .p2_slow = 10, .p2_fast = 5 },
203 .find_pll = intel_g4x_find_best_PLL,
204 };
205
206 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
207 .dot = { .min = 20000, .max = 115000 },
208 .vco = { .min = 1750000, .max = 3500000 },
209 .n = { .min = 1, .max = 3 },
210 .m = { .min = 104, .max = 138 },
211 .m1 = { .min = 17, .max = 23 },
212 .m2 = { .min = 5, .max = 11 },
213 .p = { .min = 28, .max = 112 },
214 .p1 = { .min = 2, .max = 8 },
215 .p2 = { .dot_limit = 0,
216 .p2_slow = 14, .p2_fast = 14
217 },
218 .find_pll = intel_g4x_find_best_PLL,
219 };
220
221 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
222 .dot = { .min = 80000, .max = 224000 },
223 .vco = { .min = 1750000, .max = 3500000 },
224 .n = { .min = 1, .max = 3 },
225 .m = { .min = 104, .max = 138 },
226 .m1 = { .min = 17, .max = 23 },
227 .m2 = { .min = 5, .max = 11 },
228 .p = { .min = 14, .max = 42 },
229 .p1 = { .min = 2, .max = 6 },
230 .p2 = { .dot_limit = 0,
231 .p2_slow = 7, .p2_fast = 7
232 },
233 .find_pll = intel_g4x_find_best_PLL,
234 };
235
236 static const intel_limit_t intel_limits_pineview_sdvo = {
237 .dot = { .min = 20000, .max = 400000},
238 .vco = { .min = 1700000, .max = 3500000 },
239 /* Pineview's Ncounter is a ring counter */
240 .n = { .min = 3, .max = 6 },
241 .m = { .min = 2, .max = 256 },
242 /* Pineview only has one combined m divider, which we treat as m2. */
243 .m1 = { .min = 0, .max = 0 },
244 .m2 = { .min = 0, .max = 254 },
245 .p = { .min = 5, .max = 80 },
246 .p1 = { .min = 1, .max = 8 },
247 .p2 = { .dot_limit = 200000,
248 .p2_slow = 10, .p2_fast = 5 },
249 .find_pll = intel_find_best_PLL,
250 };
251
252 static const intel_limit_t intel_limits_pineview_lvds = {
253 .dot = { .min = 20000, .max = 400000 },
254 .vco = { .min = 1700000, .max = 3500000 },
255 .n = { .min = 3, .max = 6 },
256 .m = { .min = 2, .max = 256 },
257 .m1 = { .min = 0, .max = 0 },
258 .m2 = { .min = 0, .max = 254 },
259 .p = { .min = 7, .max = 112 },
260 .p1 = { .min = 1, .max = 8 },
261 .p2 = { .dot_limit = 112000,
262 .p2_slow = 14, .p2_fast = 14 },
263 .find_pll = intel_find_best_PLL,
264 };
265
266 /* Ironlake / Sandybridge
267 *
268 * We calculate clock using (register_value + 2) for N/M1/M2, so here
269 * the range value for them is (actual_value - 2).
270 */
271 static const intel_limit_t intel_limits_ironlake_dac = {
272 .dot = { .min = 25000, .max = 350000 },
273 .vco = { .min = 1760000, .max = 3510000 },
274 .n = { .min = 1, .max = 5 },
275 .m = { .min = 79, .max = 127 },
276 .m1 = { .min = 12, .max = 22 },
277 .m2 = { .min = 5, .max = 9 },
278 .p = { .min = 5, .max = 80 },
279 .p1 = { .min = 1, .max = 8 },
280 .p2 = { .dot_limit = 225000,
281 .p2_slow = 10, .p2_fast = 5 },
282 .find_pll = intel_g4x_find_best_PLL,
283 };
284
285 static const intel_limit_t intel_limits_ironlake_single_lvds = {
286 .dot = { .min = 25000, .max = 350000 },
287 .vco = { .min = 1760000, .max = 3510000 },
288 .n = { .min = 1, .max = 3 },
289 .m = { .min = 79, .max = 118 },
290 .m1 = { .min = 12, .max = 22 },
291 .m2 = { .min = 5, .max = 9 },
292 .p = { .min = 28, .max = 112 },
293 .p1 = { .min = 2, .max = 8 },
294 .p2 = { .dot_limit = 225000,
295 .p2_slow = 14, .p2_fast = 14 },
296 .find_pll = intel_g4x_find_best_PLL,
297 };
298
299 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
300 .dot = { .min = 25000, .max = 350000 },
301 .vco = { .min = 1760000, .max = 3510000 },
302 .n = { .min = 1, .max = 3 },
303 .m = { .min = 79, .max = 127 },
304 .m1 = { .min = 12, .max = 22 },
305 .m2 = { .min = 5, .max = 9 },
306 .p = { .min = 14, .max = 56 },
307 .p1 = { .min = 2, .max = 8 },
308 .p2 = { .dot_limit = 225000,
309 .p2_slow = 7, .p2_fast = 7 },
310 .find_pll = intel_g4x_find_best_PLL,
311 };
312
313 /* LVDS 100mhz refclk limits. */
314 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
315 .dot = { .min = 25000, .max = 350000 },
316 .vco = { .min = 1760000, .max = 3510000 },
317 .n = { .min = 1, .max = 2 },
318 .m = { .min = 79, .max = 126 },
319 .m1 = { .min = 12, .max = 22 },
320 .m2 = { .min = 5, .max = 9 },
321 .p = { .min = 28, .max = 112 },
322 .p1 = { .min = 2, .max = 8 },
323 .p2 = { .dot_limit = 225000,
324 .p2_slow = 14, .p2_fast = 14 },
325 .find_pll = intel_g4x_find_best_PLL,
326 };
327
328 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
329 .dot = { .min = 25000, .max = 350000 },
330 .vco = { .min = 1760000, .max = 3510000 },
331 .n = { .min = 1, .max = 3 },
332 .m = { .min = 79, .max = 126 },
333 .m1 = { .min = 12, .max = 22 },
334 .m2 = { .min = 5, .max = 9 },
335 .p = { .min = 14, .max = 42 },
336 .p1 = { .min = 2, .max = 6 },
337 .p2 = { .dot_limit = 225000,
338 .p2_slow = 7, .p2_fast = 7 },
339 .find_pll = intel_g4x_find_best_PLL,
340 };
341
342 static const intel_limit_t intel_limits_vlv_dac = {
343 .dot = { .min = 25000, .max = 270000 },
344 .vco = { .min = 4000000, .max = 6000000 },
345 .n = { .min = 1, .max = 7 },
346 .m = { .min = 22, .max = 450 }, /* guess */
347 .m1 = { .min = 2, .max = 3 },
348 .m2 = { .min = 11, .max = 156 },
349 .p = { .min = 10, .max = 30 },
350 .p1 = { .min = 1, .max = 3 },
351 .p2 = { .dot_limit = 270000,
352 .p2_slow = 2, .p2_fast = 20 },
353 .find_pll = intel_vlv_find_best_pll,
354 };
355
356 static const intel_limit_t intel_limits_vlv_hdmi = {
357 .dot = { .min = 25000, .max = 270000 },
358 .vco = { .min = 4000000, .max = 6000000 },
359 .n = { .min = 1, .max = 7 },
360 .m = { .min = 60, .max = 300 }, /* guess */
361 .m1 = { .min = 2, .max = 3 },
362 .m2 = { .min = 11, .max = 156 },
363 .p = { .min = 10, .max = 30 },
364 .p1 = { .min = 2, .max = 3 },
365 .p2 = { .dot_limit = 270000,
366 .p2_slow = 2, .p2_fast = 20 },
367 .find_pll = intel_vlv_find_best_pll,
368 };
369
370 static const intel_limit_t intel_limits_vlv_dp = {
371 .dot = { .min = 25000, .max = 270000 },
372 .vco = { .min = 4000000, .max = 6000000 },
373 .n = { .min = 1, .max = 7 },
374 .m = { .min = 22, .max = 450 },
375 .m1 = { .min = 2, .max = 3 },
376 .m2 = { .min = 11, .max = 156 },
377 .p = { .min = 10, .max = 30 },
378 .p1 = { .min = 1, .max = 3 },
379 .p2 = { .dot_limit = 270000,
380 .p2_slow = 2, .p2_fast = 20 },
381 .find_pll = intel_vlv_find_best_pll,
382 };
383
384 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
385 int refclk)
386 {
387 struct drm_device *dev = crtc->dev;
388 const intel_limit_t *limit;
389
390 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
391 if (intel_is_dual_link_lvds(dev)) {
392 if (refclk == 100000)
393 limit = &intel_limits_ironlake_dual_lvds_100m;
394 else
395 limit = &intel_limits_ironlake_dual_lvds;
396 } else {
397 if (refclk == 100000)
398 limit = &intel_limits_ironlake_single_lvds_100m;
399 else
400 limit = &intel_limits_ironlake_single_lvds;
401 }
402 } else
403 limit = &intel_limits_ironlake_dac;
404
405 return limit;
406 }
407
408 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
409 {
410 struct drm_device *dev = crtc->dev;
411 const intel_limit_t *limit;
412
413 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
414 if (intel_is_dual_link_lvds(dev))
415 limit = &intel_limits_g4x_dual_channel_lvds;
416 else
417 limit = &intel_limits_g4x_single_channel_lvds;
418 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
419 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
420 limit = &intel_limits_g4x_hdmi;
421 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
422 limit = &intel_limits_g4x_sdvo;
423 } else /* The option is for other outputs */
424 limit = &intel_limits_i9xx_sdvo;
425
426 return limit;
427 }
428
429 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
430 {
431 struct drm_device *dev = crtc->dev;
432 const intel_limit_t *limit;
433
434 if (HAS_PCH_SPLIT(dev))
435 limit = intel_ironlake_limit(crtc, refclk);
436 else if (IS_G4X(dev)) {
437 limit = intel_g4x_limit(crtc);
438 } else if (IS_PINEVIEW(dev)) {
439 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
440 limit = &intel_limits_pineview_lvds;
441 else
442 limit = &intel_limits_pineview_sdvo;
443 } else if (IS_VALLEYVIEW(dev)) {
444 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
445 limit = &intel_limits_vlv_dac;
446 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
447 limit = &intel_limits_vlv_hdmi;
448 else
449 limit = &intel_limits_vlv_dp;
450 } else if (!IS_GEN2(dev)) {
451 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
452 limit = &intel_limits_i9xx_lvds;
453 else
454 limit = &intel_limits_i9xx_sdvo;
455 } else {
456 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
457 limit = &intel_limits_i8xx_lvds;
458 else
459 limit = &intel_limits_i8xx_dvo;
460 }
461 return limit;
462 }
463
464 /* m1 is reserved as 0 in Pineview, n is a ring counter */
465 static void pineview_clock(int refclk, intel_clock_t *clock)
466 {
467 clock->m = clock->m2 + 2;
468 clock->p = clock->p1 * clock->p2;
469 clock->vco = refclk * clock->m / clock->n;
470 clock->dot = clock->vco / clock->p;
471 }
472
473 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
474 {
475 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
476 }
477
478 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
479 {
480 if (IS_PINEVIEW(dev)) {
481 pineview_clock(refclk, clock);
482 return;
483 }
484 clock->m = i9xx_dpll_compute_m(clock);
485 clock->p = clock->p1 * clock->p2;
486 clock->vco = refclk * clock->m / (clock->n + 2);
487 clock->dot = clock->vco / clock->p;
488 }
489
490 /**
491 * Returns whether any output on the specified pipe is of the specified type
492 */
493 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
494 {
495 struct drm_device *dev = crtc->dev;
496 struct intel_encoder *encoder;
497
498 for_each_encoder_on_crtc(dev, crtc, encoder)
499 if (encoder->type == type)
500 return true;
501
502 return false;
503 }
504
505 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
506 /**
507 * Returns whether the given set of divisors are valid for a given refclk with
508 * the given connectors.
509 */
510
511 static bool intel_PLL_is_valid(struct drm_device *dev,
512 const intel_limit_t *limit,
513 const intel_clock_t *clock)
514 {
515 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
516 INTELPllInvalid("p1 out of range\n");
517 if (clock->p < limit->p.min || limit->p.max < clock->p)
518 INTELPllInvalid("p out of range\n");
519 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
520 INTELPllInvalid("m2 out of range\n");
521 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
522 INTELPllInvalid("m1 out of range\n");
523 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
524 INTELPllInvalid("m1 <= m2\n");
525 if (clock->m < limit->m.min || limit->m.max < clock->m)
526 INTELPllInvalid("m out of range\n");
527 if (clock->n < limit->n.min || limit->n.max < clock->n)
528 INTELPllInvalid("n out of range\n");
529 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
530 INTELPllInvalid("vco out of range\n");
531 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
532 * connector, etc., rather than just a single range.
533 */
534 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
535 INTELPllInvalid("dot out of range\n");
536
537 return true;
538 }
539
540 static bool
541 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
542 int target, int refclk, intel_clock_t *match_clock,
543 intel_clock_t *best_clock)
544
545 {
546 struct drm_device *dev = crtc->dev;
547 intel_clock_t clock;
548 int err = target;
549
550 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
551 /*
552 * For LVDS just rely on its current settings for dual-channel.
553 * We haven't figured out how to reliably set up different
554 * single/dual channel state, if we even can.
555 */
556 if (intel_is_dual_link_lvds(dev))
557 clock.p2 = limit->p2.p2_fast;
558 else
559 clock.p2 = limit->p2.p2_slow;
560 } else {
561 if (target < limit->p2.dot_limit)
562 clock.p2 = limit->p2.p2_slow;
563 else
564 clock.p2 = limit->p2.p2_fast;
565 }
566
567 memset(best_clock, 0, sizeof(*best_clock));
568
569 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
570 clock.m1++) {
571 for (clock.m2 = limit->m2.min;
572 clock.m2 <= limit->m2.max; clock.m2++) {
573 /* m1 is always 0 in Pineview */
574 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
575 break;
576 for (clock.n = limit->n.min;
577 clock.n <= limit->n.max; clock.n++) {
578 for (clock.p1 = limit->p1.min;
579 clock.p1 <= limit->p1.max; clock.p1++) {
580 int this_err;
581
582 intel_clock(dev, refclk, &clock);
583 if (!intel_PLL_is_valid(dev, limit,
584 &clock))
585 continue;
586 if (match_clock &&
587 clock.p != match_clock->p)
588 continue;
589
590 this_err = abs(clock.dot - target);
591 if (this_err < err) {
592 *best_clock = clock;
593 err = this_err;
594 }
595 }
596 }
597 }
598 }
599
600 return (err != target);
601 }
602
603 static bool
604 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
605 int target, int refclk, intel_clock_t *match_clock,
606 intel_clock_t *best_clock)
607 {
608 struct drm_device *dev = crtc->dev;
609 intel_clock_t clock;
610 int max_n;
611 bool found;
612 /* approximately equals target * 0.00585 */
613 int err_most = (target >> 8) + (target >> 9);
614 found = false;
615
616 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
617 if (intel_is_dual_link_lvds(dev))
618 clock.p2 = limit->p2.p2_fast;
619 else
620 clock.p2 = limit->p2.p2_slow;
621 } else {
622 if (target < limit->p2.dot_limit)
623 clock.p2 = limit->p2.p2_slow;
624 else
625 clock.p2 = limit->p2.p2_fast;
626 }
627
628 memset(best_clock, 0, sizeof(*best_clock));
629 max_n = limit->n.max;
630 /* based on hardware requirement, prefer smaller n to precision */
631 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
632 /* based on hardware requirement, prefere larger m1,m2 */
633 for (clock.m1 = limit->m1.max;
634 clock.m1 >= limit->m1.min; clock.m1--) {
635 for (clock.m2 = limit->m2.max;
636 clock.m2 >= limit->m2.min; clock.m2--) {
637 for (clock.p1 = limit->p1.max;
638 clock.p1 >= limit->p1.min; clock.p1--) {
639 int this_err;
640
641 intel_clock(dev, refclk, &clock);
642 if (!intel_PLL_is_valid(dev, limit,
643 &clock))
644 continue;
645
646 this_err = abs(clock.dot - target);
647 if (this_err < err_most) {
648 *best_clock = clock;
649 err_most = this_err;
650 max_n = clock.n;
651 found = true;
652 }
653 }
654 }
655 }
656 }
657 return found;
658 }
659
660 static bool
661 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
662 int target, int refclk, intel_clock_t *match_clock,
663 intel_clock_t *best_clock)
664 {
665 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
666 u32 m, n, fastclk;
667 u32 updrate, minupdate, fracbits, p;
668 unsigned long bestppm, ppm, absppm;
669 int dotclk, flag;
670
671 flag = 0;
672 dotclk = target * 1000;
673 bestppm = 1000000;
674 ppm = absppm = 0;
675 fastclk = dotclk / (2*100);
676 updrate = 0;
677 minupdate = 19200;
678 fracbits = 1;
679 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
680 bestm1 = bestm2 = bestp1 = bestp2 = 0;
681
682 /* based on hardware requirement, prefer smaller n to precision */
683 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
684 updrate = refclk / n;
685 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
686 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
687 if (p2 > 10)
688 p2 = p2 - 1;
689 p = p1 * p2;
690 /* based on hardware requirement, prefer bigger m1,m2 values */
691 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
692 m2 = (((2*(fastclk * p * n / m1 )) +
693 refclk) / (2*refclk));
694 m = m1 * m2;
695 vco = updrate * m;
696 if (vco >= limit->vco.min && vco < limit->vco.max) {
697 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
698 absppm = (ppm > 0) ? ppm : (-ppm);
699 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
700 bestppm = 0;
701 flag = 1;
702 }
703 if (absppm < bestppm - 10) {
704 bestppm = absppm;
705 flag = 1;
706 }
707 if (flag) {
708 bestn = n;
709 bestm1 = m1;
710 bestm2 = m2;
711 bestp1 = p1;
712 bestp2 = p2;
713 flag = 0;
714 }
715 }
716 }
717 }
718 }
719 }
720 best_clock->n = bestn;
721 best_clock->m1 = bestm1;
722 best_clock->m2 = bestm2;
723 best_clock->p1 = bestp1;
724 best_clock->p2 = bestp2;
725
726 return true;
727 }
728
729 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
730 enum pipe pipe)
731 {
732 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
733 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
734
735 return intel_crtc->config.cpu_transcoder;
736 }
737
738 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
739 {
740 struct drm_i915_private *dev_priv = dev->dev_private;
741 u32 frame, frame_reg = PIPEFRAME(pipe);
742
743 frame = I915_READ(frame_reg);
744
745 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
746 DRM_DEBUG_KMS("vblank wait timed out\n");
747 }
748
749 /**
750 * intel_wait_for_vblank - wait for vblank on a given pipe
751 * @dev: drm device
752 * @pipe: pipe to wait for
753 *
754 * Wait for vblank to occur on a given pipe. Needed for various bits of
755 * mode setting code.
756 */
757 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
758 {
759 struct drm_i915_private *dev_priv = dev->dev_private;
760 int pipestat_reg = PIPESTAT(pipe);
761
762 if (INTEL_INFO(dev)->gen >= 5) {
763 ironlake_wait_for_vblank(dev, pipe);
764 return;
765 }
766
767 /* Clear existing vblank status. Note this will clear any other
768 * sticky status fields as well.
769 *
770 * This races with i915_driver_irq_handler() with the result
771 * that either function could miss a vblank event. Here it is not
772 * fatal, as we will either wait upon the next vblank interrupt or
773 * timeout. Generally speaking intel_wait_for_vblank() is only
774 * called during modeset at which time the GPU should be idle and
775 * should *not* be performing page flips and thus not waiting on
776 * vblanks...
777 * Currently, the result of us stealing a vblank from the irq
778 * handler is that a single frame will be skipped during swapbuffers.
779 */
780 I915_WRITE(pipestat_reg,
781 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
782
783 /* Wait for vblank interrupt bit to set */
784 if (wait_for(I915_READ(pipestat_reg) &
785 PIPE_VBLANK_INTERRUPT_STATUS,
786 50))
787 DRM_DEBUG_KMS("vblank wait timed out\n");
788 }
789
790 /*
791 * intel_wait_for_pipe_off - wait for pipe to turn off
792 * @dev: drm device
793 * @pipe: pipe to wait for
794 *
795 * After disabling a pipe, we can't wait for vblank in the usual way,
796 * spinning on the vblank interrupt status bit, since we won't actually
797 * see an interrupt when the pipe is disabled.
798 *
799 * On Gen4 and above:
800 * wait for the pipe register state bit to turn off
801 *
802 * Otherwise:
803 * wait for the display line value to settle (it usually
804 * ends up stopping at the start of the next frame).
805 *
806 */
807 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
808 {
809 struct drm_i915_private *dev_priv = dev->dev_private;
810 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
811 pipe);
812
813 if (INTEL_INFO(dev)->gen >= 4) {
814 int reg = PIPECONF(cpu_transcoder);
815
816 /* Wait for the Pipe State to go off */
817 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
818 100))
819 WARN(1, "pipe_off wait timed out\n");
820 } else {
821 u32 last_line, line_mask;
822 int reg = PIPEDSL(pipe);
823 unsigned long timeout = jiffies + msecs_to_jiffies(100);
824
825 if (IS_GEN2(dev))
826 line_mask = DSL_LINEMASK_GEN2;
827 else
828 line_mask = DSL_LINEMASK_GEN3;
829
830 /* Wait for the display line to settle */
831 do {
832 last_line = I915_READ(reg) & line_mask;
833 mdelay(5);
834 } while (((I915_READ(reg) & line_mask) != last_line) &&
835 time_after(timeout, jiffies));
836 if (time_after(jiffies, timeout))
837 WARN(1, "pipe_off wait timed out\n");
838 }
839 }
840
841 /*
842 * ibx_digital_port_connected - is the specified port connected?
843 * @dev_priv: i915 private structure
844 * @port: the port to test
845 *
846 * Returns true if @port is connected, false otherwise.
847 */
848 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
849 struct intel_digital_port *port)
850 {
851 u32 bit;
852
853 if (HAS_PCH_IBX(dev_priv->dev)) {
854 switch(port->port) {
855 case PORT_B:
856 bit = SDE_PORTB_HOTPLUG;
857 break;
858 case PORT_C:
859 bit = SDE_PORTC_HOTPLUG;
860 break;
861 case PORT_D:
862 bit = SDE_PORTD_HOTPLUG;
863 break;
864 default:
865 return true;
866 }
867 } else {
868 switch(port->port) {
869 case PORT_B:
870 bit = SDE_PORTB_HOTPLUG_CPT;
871 break;
872 case PORT_C:
873 bit = SDE_PORTC_HOTPLUG_CPT;
874 break;
875 case PORT_D:
876 bit = SDE_PORTD_HOTPLUG_CPT;
877 break;
878 default:
879 return true;
880 }
881 }
882
883 return I915_READ(SDEISR) & bit;
884 }
885
886 static const char *state_string(bool enabled)
887 {
888 return enabled ? "on" : "off";
889 }
890
891 /* Only for pre-ILK configs */
892 static void assert_pll(struct drm_i915_private *dev_priv,
893 enum pipe pipe, bool state)
894 {
895 int reg;
896 u32 val;
897 bool cur_state;
898
899 reg = DPLL(pipe);
900 val = I915_READ(reg);
901 cur_state = !!(val & DPLL_VCO_ENABLE);
902 WARN(cur_state != state,
903 "PLL state assertion failure (expected %s, current %s)\n",
904 state_string(state), state_string(cur_state));
905 }
906 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
907 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
908
909 /* For ILK+ */
910 static void assert_pch_pll(struct drm_i915_private *dev_priv,
911 struct intel_pch_pll *pll,
912 struct intel_crtc *crtc,
913 bool state)
914 {
915 u32 val;
916 bool cur_state;
917
918 if (HAS_PCH_LPT(dev_priv->dev)) {
919 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
920 return;
921 }
922
923 if (WARN (!pll,
924 "asserting PCH PLL %s with no PLL\n", state_string(state)))
925 return;
926
927 val = I915_READ(pll->pll_reg);
928 cur_state = !!(val & DPLL_VCO_ENABLE);
929 WARN(cur_state != state,
930 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
931 pll->pll_reg, state_string(state), state_string(cur_state), val);
932
933 /* Make sure the selected PLL is correctly attached to the transcoder */
934 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
935 u32 pch_dpll;
936
937 pch_dpll = I915_READ(PCH_DPLL_SEL);
938 cur_state = pll->pll_reg == _PCH_DPLL_B;
939 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
940 "PLL[%d] not attached to this transcoder %c: %08x\n",
941 cur_state, pipe_name(crtc->pipe), pch_dpll)) {
942 cur_state = !!(val >> (4*crtc->pipe + 3));
943 WARN(cur_state != state,
944 "PLL[%d] not %s on this transcoder %c: %08x\n",
945 pll->pll_reg == _PCH_DPLL_B,
946 state_string(state),
947 pipe_name(crtc->pipe),
948 val);
949 }
950 }
951 }
952 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
953 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
954
955 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
956 enum pipe pipe, bool state)
957 {
958 int reg;
959 u32 val;
960 bool cur_state;
961 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
962 pipe);
963
964 if (HAS_DDI(dev_priv->dev)) {
965 /* DDI does not have a specific FDI_TX register */
966 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
967 val = I915_READ(reg);
968 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
969 } else {
970 reg = FDI_TX_CTL(pipe);
971 val = I915_READ(reg);
972 cur_state = !!(val & FDI_TX_ENABLE);
973 }
974 WARN(cur_state != state,
975 "FDI TX state assertion failure (expected %s, current %s)\n",
976 state_string(state), state_string(cur_state));
977 }
978 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
979 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
980
981 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
982 enum pipe pipe, bool state)
983 {
984 int reg;
985 u32 val;
986 bool cur_state;
987
988 reg = FDI_RX_CTL(pipe);
989 val = I915_READ(reg);
990 cur_state = !!(val & FDI_RX_ENABLE);
991 WARN(cur_state != state,
992 "FDI RX state assertion failure (expected %s, current %s)\n",
993 state_string(state), state_string(cur_state));
994 }
995 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
996 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
997
998 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
999 enum pipe pipe)
1000 {
1001 int reg;
1002 u32 val;
1003
1004 /* ILK FDI PLL is always enabled */
1005 if (dev_priv->info->gen == 5)
1006 return;
1007
1008 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1009 if (HAS_DDI(dev_priv->dev))
1010 return;
1011
1012 reg = FDI_TX_CTL(pipe);
1013 val = I915_READ(reg);
1014 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1015 }
1016
1017 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1018 enum pipe pipe)
1019 {
1020 int reg;
1021 u32 val;
1022
1023 reg = FDI_RX_CTL(pipe);
1024 val = I915_READ(reg);
1025 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1026 }
1027
1028 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1029 enum pipe pipe)
1030 {
1031 int pp_reg, lvds_reg;
1032 u32 val;
1033 enum pipe panel_pipe = PIPE_A;
1034 bool locked = true;
1035
1036 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1037 pp_reg = PCH_PP_CONTROL;
1038 lvds_reg = PCH_LVDS;
1039 } else {
1040 pp_reg = PP_CONTROL;
1041 lvds_reg = LVDS;
1042 }
1043
1044 val = I915_READ(pp_reg);
1045 if (!(val & PANEL_POWER_ON) ||
1046 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1047 locked = false;
1048
1049 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1050 panel_pipe = PIPE_B;
1051
1052 WARN(panel_pipe == pipe && locked,
1053 "panel assertion failure, pipe %c regs locked\n",
1054 pipe_name(pipe));
1055 }
1056
1057 void assert_pipe(struct drm_i915_private *dev_priv,
1058 enum pipe pipe, bool state)
1059 {
1060 int reg;
1061 u32 val;
1062 bool cur_state;
1063 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1064 pipe);
1065
1066 /* if we need the pipe A quirk it must be always on */
1067 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1068 state = true;
1069
1070 if (!intel_display_power_enabled(dev_priv->dev,
1071 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1072 cur_state = false;
1073 } else {
1074 reg = PIPECONF(cpu_transcoder);
1075 val = I915_READ(reg);
1076 cur_state = !!(val & PIPECONF_ENABLE);
1077 }
1078
1079 WARN(cur_state != state,
1080 "pipe %c assertion failure (expected %s, current %s)\n",
1081 pipe_name(pipe), state_string(state), state_string(cur_state));
1082 }
1083
1084 static void assert_plane(struct drm_i915_private *dev_priv,
1085 enum plane plane, bool state)
1086 {
1087 int reg;
1088 u32 val;
1089 bool cur_state;
1090
1091 reg = DSPCNTR(plane);
1092 val = I915_READ(reg);
1093 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1094 WARN(cur_state != state,
1095 "plane %c assertion failure (expected %s, current %s)\n",
1096 plane_name(plane), state_string(state), state_string(cur_state));
1097 }
1098
1099 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1100 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1101
1102 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1103 enum pipe pipe)
1104 {
1105 int reg, i;
1106 u32 val;
1107 int cur_pipe;
1108
1109 /* Planes are fixed to pipes on ILK+ */
1110 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
1111 reg = DSPCNTR(pipe);
1112 val = I915_READ(reg);
1113 WARN((val & DISPLAY_PLANE_ENABLE),
1114 "plane %c assertion failure, should be disabled but not\n",
1115 plane_name(pipe));
1116 return;
1117 }
1118
1119 /* Need to check both planes against the pipe */
1120 for (i = 0; i < 2; i++) {
1121 reg = DSPCNTR(i);
1122 val = I915_READ(reg);
1123 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1124 DISPPLANE_SEL_PIPE_SHIFT;
1125 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1126 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1127 plane_name(i), pipe_name(pipe));
1128 }
1129 }
1130
1131 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1132 enum pipe pipe)
1133 {
1134 int reg, i;
1135 u32 val;
1136
1137 if (!IS_VALLEYVIEW(dev_priv->dev))
1138 return;
1139
1140 /* Need to check both planes against the pipe */
1141 for (i = 0; i < dev_priv->num_plane; i++) {
1142 reg = SPCNTR(pipe, i);
1143 val = I915_READ(reg);
1144 WARN((val & SP_ENABLE),
1145 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1146 sprite_name(pipe, i), pipe_name(pipe));
1147 }
1148 }
1149
1150 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1151 {
1152 u32 val;
1153 bool enabled;
1154
1155 if (HAS_PCH_LPT(dev_priv->dev)) {
1156 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1157 return;
1158 }
1159
1160 val = I915_READ(PCH_DREF_CONTROL);
1161 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1162 DREF_SUPERSPREAD_SOURCE_MASK));
1163 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1164 }
1165
1166 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1167 enum pipe pipe)
1168 {
1169 int reg;
1170 u32 val;
1171 bool enabled;
1172
1173 reg = PCH_TRANSCONF(pipe);
1174 val = I915_READ(reg);
1175 enabled = !!(val & TRANS_ENABLE);
1176 WARN(enabled,
1177 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1178 pipe_name(pipe));
1179 }
1180
1181 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1182 enum pipe pipe, u32 port_sel, u32 val)
1183 {
1184 if ((val & DP_PORT_EN) == 0)
1185 return false;
1186
1187 if (HAS_PCH_CPT(dev_priv->dev)) {
1188 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1189 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1190 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1191 return false;
1192 } else {
1193 if ((val & DP_PIPE_MASK) != (pipe << 30))
1194 return false;
1195 }
1196 return true;
1197 }
1198
1199 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1200 enum pipe pipe, u32 val)
1201 {
1202 if ((val & SDVO_ENABLE) == 0)
1203 return false;
1204
1205 if (HAS_PCH_CPT(dev_priv->dev)) {
1206 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1207 return false;
1208 } else {
1209 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1210 return false;
1211 }
1212 return true;
1213 }
1214
1215 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1216 enum pipe pipe, u32 val)
1217 {
1218 if ((val & LVDS_PORT_EN) == 0)
1219 return false;
1220
1221 if (HAS_PCH_CPT(dev_priv->dev)) {
1222 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1223 return false;
1224 } else {
1225 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1226 return false;
1227 }
1228 return true;
1229 }
1230
1231 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1232 enum pipe pipe, u32 val)
1233 {
1234 if ((val & ADPA_DAC_ENABLE) == 0)
1235 return false;
1236 if (HAS_PCH_CPT(dev_priv->dev)) {
1237 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1238 return false;
1239 } else {
1240 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1241 return false;
1242 }
1243 return true;
1244 }
1245
1246 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1247 enum pipe pipe, int reg, u32 port_sel)
1248 {
1249 u32 val = I915_READ(reg);
1250 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1251 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1252 reg, pipe_name(pipe));
1253
1254 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1255 && (val & DP_PIPEB_SELECT),
1256 "IBX PCH dp port still using transcoder B\n");
1257 }
1258
1259 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1260 enum pipe pipe, int reg)
1261 {
1262 u32 val = I915_READ(reg);
1263 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1264 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1265 reg, pipe_name(pipe));
1266
1267 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1268 && (val & SDVO_PIPE_B_SELECT),
1269 "IBX PCH hdmi port still using transcoder B\n");
1270 }
1271
1272 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1273 enum pipe pipe)
1274 {
1275 int reg;
1276 u32 val;
1277
1278 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1279 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1280 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1281
1282 reg = PCH_ADPA;
1283 val = I915_READ(reg);
1284 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1285 "PCH VGA enabled on transcoder %c, should be disabled\n",
1286 pipe_name(pipe));
1287
1288 reg = PCH_LVDS;
1289 val = I915_READ(reg);
1290 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1291 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1292 pipe_name(pipe));
1293
1294 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1295 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1296 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1297 }
1298
1299 /**
1300 * intel_enable_pll - enable a PLL
1301 * @dev_priv: i915 private structure
1302 * @pipe: pipe PLL to enable
1303 *
1304 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1305 * make sure the PLL reg is writable first though, since the panel write
1306 * protect mechanism may be enabled.
1307 *
1308 * Note! This is for pre-ILK only.
1309 *
1310 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1311 */
1312 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1313 {
1314 int reg;
1315 u32 val;
1316
1317 assert_pipe_disabled(dev_priv, pipe);
1318
1319 /* No really, not for ILK+ */
1320 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1321
1322 /* PLL is protected by panel, make sure we can write it */
1323 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1324 assert_panel_unlocked(dev_priv, pipe);
1325
1326 reg = DPLL(pipe);
1327 val = I915_READ(reg);
1328 val |= DPLL_VCO_ENABLE;
1329
1330 /* We do this three times for luck */
1331 I915_WRITE(reg, val);
1332 POSTING_READ(reg);
1333 udelay(150); /* wait for warmup */
1334 I915_WRITE(reg, val);
1335 POSTING_READ(reg);
1336 udelay(150); /* wait for warmup */
1337 I915_WRITE(reg, val);
1338 POSTING_READ(reg);
1339 udelay(150); /* wait for warmup */
1340 }
1341
1342 /**
1343 * intel_disable_pll - disable a PLL
1344 * @dev_priv: i915 private structure
1345 * @pipe: pipe PLL to disable
1346 *
1347 * Disable the PLL for @pipe, making sure the pipe is off first.
1348 *
1349 * Note! This is for pre-ILK only.
1350 */
1351 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1352 {
1353 int reg;
1354 u32 val;
1355
1356 /* Don't disable pipe A or pipe A PLLs if needed */
1357 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1358 return;
1359
1360 /* Make sure the pipe isn't still relying on us */
1361 assert_pipe_disabled(dev_priv, pipe);
1362
1363 reg = DPLL(pipe);
1364 val = I915_READ(reg);
1365 val &= ~DPLL_VCO_ENABLE;
1366 I915_WRITE(reg, val);
1367 POSTING_READ(reg);
1368 }
1369
1370 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1371 {
1372 u32 port_mask;
1373
1374 if (!port)
1375 port_mask = DPLL_PORTB_READY_MASK;
1376 else
1377 port_mask = DPLL_PORTC_READY_MASK;
1378
1379 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1380 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1381 'B' + port, I915_READ(DPLL(0)));
1382 }
1383
1384 /**
1385 * ironlake_enable_pch_pll - enable PCH PLL
1386 * @dev_priv: i915 private structure
1387 * @pipe: pipe PLL to enable
1388 *
1389 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1390 * drives the transcoder clock.
1391 */
1392 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1393 {
1394 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1395 struct intel_pch_pll *pll;
1396 int reg;
1397 u32 val;
1398
1399 /* PCH PLLs only available on ILK, SNB and IVB */
1400 BUG_ON(dev_priv->info->gen < 5);
1401 pll = intel_crtc->pch_pll;
1402 if (pll == NULL)
1403 return;
1404
1405 if (WARN_ON(pll->refcount == 0))
1406 return;
1407
1408 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1409 pll->pll_reg, pll->active, pll->on,
1410 intel_crtc->base.base.id);
1411
1412 /* PCH refclock must be enabled first */
1413 assert_pch_refclk_enabled(dev_priv);
1414
1415 if (pll->active++ && pll->on) {
1416 assert_pch_pll_enabled(dev_priv, pll, NULL);
1417 return;
1418 }
1419
1420 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1421
1422 reg = pll->pll_reg;
1423 val = I915_READ(reg);
1424 val |= DPLL_VCO_ENABLE;
1425 I915_WRITE(reg, val);
1426 POSTING_READ(reg);
1427 udelay(200);
1428
1429 pll->on = true;
1430 }
1431
1432 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1433 {
1434 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1435 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1436 int reg;
1437 u32 val;
1438
1439 /* PCH only available on ILK+ */
1440 BUG_ON(dev_priv->info->gen < 5);
1441 if (pll == NULL)
1442 return;
1443
1444 if (WARN_ON(pll->refcount == 0))
1445 return;
1446
1447 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1448 pll->pll_reg, pll->active, pll->on,
1449 intel_crtc->base.base.id);
1450
1451 if (WARN_ON(pll->active == 0)) {
1452 assert_pch_pll_disabled(dev_priv, pll, NULL);
1453 return;
1454 }
1455
1456 if (--pll->active) {
1457 assert_pch_pll_enabled(dev_priv, pll, NULL);
1458 return;
1459 }
1460
1461 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1462
1463 /* Make sure transcoder isn't still depending on us */
1464 assert_pch_transcoder_disabled(dev_priv, intel_crtc->pipe);
1465
1466 reg = pll->pll_reg;
1467 val = I915_READ(reg);
1468 val &= ~DPLL_VCO_ENABLE;
1469 I915_WRITE(reg, val);
1470 POSTING_READ(reg);
1471 udelay(200);
1472
1473 pll->on = false;
1474 }
1475
1476 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1477 enum pipe pipe)
1478 {
1479 struct drm_device *dev = dev_priv->dev;
1480 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1481 uint32_t reg, val, pipeconf_val;
1482
1483 /* PCH only available on ILK+ */
1484 BUG_ON(dev_priv->info->gen < 5);
1485
1486 /* Make sure PCH DPLL is enabled */
1487 assert_pch_pll_enabled(dev_priv,
1488 to_intel_crtc(crtc)->pch_pll,
1489 to_intel_crtc(crtc));
1490
1491 /* FDI must be feeding us bits for PCH ports */
1492 assert_fdi_tx_enabled(dev_priv, pipe);
1493 assert_fdi_rx_enabled(dev_priv, pipe);
1494
1495 if (HAS_PCH_CPT(dev)) {
1496 /* Workaround: Set the timing override bit before enabling the
1497 * pch transcoder. */
1498 reg = TRANS_CHICKEN2(pipe);
1499 val = I915_READ(reg);
1500 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1501 I915_WRITE(reg, val);
1502 }
1503
1504 reg = PCH_TRANSCONF(pipe);
1505 val = I915_READ(reg);
1506 pipeconf_val = I915_READ(PIPECONF(pipe));
1507
1508 if (HAS_PCH_IBX(dev_priv->dev)) {
1509 /*
1510 * make the BPC in transcoder be consistent with
1511 * that in pipeconf reg.
1512 */
1513 val &= ~PIPECONF_BPC_MASK;
1514 val |= pipeconf_val & PIPECONF_BPC_MASK;
1515 }
1516
1517 val &= ~TRANS_INTERLACE_MASK;
1518 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1519 if (HAS_PCH_IBX(dev_priv->dev) &&
1520 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1521 val |= TRANS_LEGACY_INTERLACED_ILK;
1522 else
1523 val |= TRANS_INTERLACED;
1524 else
1525 val |= TRANS_PROGRESSIVE;
1526
1527 I915_WRITE(reg, val | TRANS_ENABLE);
1528 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1529 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1530 }
1531
1532 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1533 enum transcoder cpu_transcoder)
1534 {
1535 u32 val, pipeconf_val;
1536
1537 /* PCH only available on ILK+ */
1538 BUG_ON(dev_priv->info->gen < 5);
1539
1540 /* FDI must be feeding us bits for PCH ports */
1541 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1542 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1543
1544 /* Workaround: set timing override bit. */
1545 val = I915_READ(_TRANSA_CHICKEN2);
1546 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1547 I915_WRITE(_TRANSA_CHICKEN2, val);
1548
1549 val = TRANS_ENABLE;
1550 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1551
1552 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1553 PIPECONF_INTERLACED_ILK)
1554 val |= TRANS_INTERLACED;
1555 else
1556 val |= TRANS_PROGRESSIVE;
1557
1558 I915_WRITE(LPT_TRANSCONF, val);
1559 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1560 DRM_ERROR("Failed to enable PCH transcoder\n");
1561 }
1562
1563 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1564 enum pipe pipe)
1565 {
1566 struct drm_device *dev = dev_priv->dev;
1567 uint32_t reg, val;
1568
1569 /* FDI relies on the transcoder */
1570 assert_fdi_tx_disabled(dev_priv, pipe);
1571 assert_fdi_rx_disabled(dev_priv, pipe);
1572
1573 /* Ports must be off as well */
1574 assert_pch_ports_disabled(dev_priv, pipe);
1575
1576 reg = PCH_TRANSCONF(pipe);
1577 val = I915_READ(reg);
1578 val &= ~TRANS_ENABLE;
1579 I915_WRITE(reg, val);
1580 /* wait for PCH transcoder off, transcoder state */
1581 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1582 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1583
1584 if (!HAS_PCH_IBX(dev)) {
1585 /* Workaround: Clear the timing override chicken bit again. */
1586 reg = TRANS_CHICKEN2(pipe);
1587 val = I915_READ(reg);
1588 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1589 I915_WRITE(reg, val);
1590 }
1591 }
1592
1593 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1594 {
1595 u32 val;
1596
1597 val = I915_READ(LPT_TRANSCONF);
1598 val &= ~TRANS_ENABLE;
1599 I915_WRITE(LPT_TRANSCONF, val);
1600 /* wait for PCH transcoder off, transcoder state */
1601 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1602 DRM_ERROR("Failed to disable PCH transcoder\n");
1603
1604 /* Workaround: clear timing override bit. */
1605 val = I915_READ(_TRANSA_CHICKEN2);
1606 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1607 I915_WRITE(_TRANSA_CHICKEN2, val);
1608 }
1609
1610 /**
1611 * intel_enable_pipe - enable a pipe, asserting requirements
1612 * @dev_priv: i915 private structure
1613 * @pipe: pipe to enable
1614 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1615 *
1616 * Enable @pipe, making sure that various hardware specific requirements
1617 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1618 *
1619 * @pipe should be %PIPE_A or %PIPE_B.
1620 *
1621 * Will wait until the pipe is actually running (i.e. first vblank) before
1622 * returning.
1623 */
1624 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1625 bool pch_port)
1626 {
1627 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1628 pipe);
1629 enum pipe pch_transcoder;
1630 int reg;
1631 u32 val;
1632
1633 assert_planes_disabled(dev_priv, pipe);
1634 assert_sprites_disabled(dev_priv, pipe);
1635
1636 if (HAS_PCH_LPT(dev_priv->dev))
1637 pch_transcoder = TRANSCODER_A;
1638 else
1639 pch_transcoder = pipe;
1640
1641 /*
1642 * A pipe without a PLL won't actually be able to drive bits from
1643 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1644 * need the check.
1645 */
1646 if (!HAS_PCH_SPLIT(dev_priv->dev))
1647 assert_pll_enabled(dev_priv, pipe);
1648 else {
1649 if (pch_port) {
1650 /* if driving the PCH, we need FDI enabled */
1651 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1652 assert_fdi_tx_pll_enabled(dev_priv,
1653 (enum pipe) cpu_transcoder);
1654 }
1655 /* FIXME: assert CPU port conditions for SNB+ */
1656 }
1657
1658 reg = PIPECONF(cpu_transcoder);
1659 val = I915_READ(reg);
1660 if (val & PIPECONF_ENABLE)
1661 return;
1662
1663 I915_WRITE(reg, val | PIPECONF_ENABLE);
1664 intel_wait_for_vblank(dev_priv->dev, pipe);
1665 }
1666
1667 /**
1668 * intel_disable_pipe - disable a pipe, asserting requirements
1669 * @dev_priv: i915 private structure
1670 * @pipe: pipe to disable
1671 *
1672 * Disable @pipe, making sure that various hardware specific requirements
1673 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1674 *
1675 * @pipe should be %PIPE_A or %PIPE_B.
1676 *
1677 * Will wait until the pipe has shut down before returning.
1678 */
1679 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1680 enum pipe pipe)
1681 {
1682 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1683 pipe);
1684 int reg;
1685 u32 val;
1686
1687 /*
1688 * Make sure planes won't keep trying to pump pixels to us,
1689 * or we might hang the display.
1690 */
1691 assert_planes_disabled(dev_priv, pipe);
1692 assert_sprites_disabled(dev_priv, pipe);
1693
1694 /* Don't disable pipe A or pipe A PLLs if needed */
1695 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1696 return;
1697
1698 reg = PIPECONF(cpu_transcoder);
1699 val = I915_READ(reg);
1700 if ((val & PIPECONF_ENABLE) == 0)
1701 return;
1702
1703 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1704 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1705 }
1706
1707 /*
1708 * Plane regs are double buffered, going from enabled->disabled needs a
1709 * trigger in order to latch. The display address reg provides this.
1710 */
1711 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1712 enum plane plane)
1713 {
1714 if (dev_priv->info->gen >= 4)
1715 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1716 else
1717 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1718 }
1719
1720 /**
1721 * intel_enable_plane - enable a display plane on a given pipe
1722 * @dev_priv: i915 private structure
1723 * @plane: plane to enable
1724 * @pipe: pipe being fed
1725 *
1726 * Enable @plane on @pipe, making sure that @pipe is running first.
1727 */
1728 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1729 enum plane plane, enum pipe pipe)
1730 {
1731 int reg;
1732 u32 val;
1733
1734 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1735 assert_pipe_enabled(dev_priv, pipe);
1736
1737 reg = DSPCNTR(plane);
1738 val = I915_READ(reg);
1739 if (val & DISPLAY_PLANE_ENABLE)
1740 return;
1741
1742 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1743 intel_flush_display_plane(dev_priv, plane);
1744 intel_wait_for_vblank(dev_priv->dev, pipe);
1745 }
1746
1747 /**
1748 * intel_disable_plane - disable a display plane
1749 * @dev_priv: i915 private structure
1750 * @plane: plane to disable
1751 * @pipe: pipe consuming the data
1752 *
1753 * Disable @plane; should be an independent operation.
1754 */
1755 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1756 enum plane plane, enum pipe pipe)
1757 {
1758 int reg;
1759 u32 val;
1760
1761 reg = DSPCNTR(plane);
1762 val = I915_READ(reg);
1763 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1764 return;
1765
1766 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1767 intel_flush_display_plane(dev_priv, plane);
1768 intel_wait_for_vblank(dev_priv->dev, pipe);
1769 }
1770
1771 static bool need_vtd_wa(struct drm_device *dev)
1772 {
1773 #ifdef CONFIG_INTEL_IOMMU
1774 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1775 return true;
1776 #endif
1777 return false;
1778 }
1779
1780 int
1781 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1782 struct drm_i915_gem_object *obj,
1783 struct intel_ring_buffer *pipelined)
1784 {
1785 struct drm_i915_private *dev_priv = dev->dev_private;
1786 u32 alignment;
1787 int ret;
1788
1789 switch (obj->tiling_mode) {
1790 case I915_TILING_NONE:
1791 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1792 alignment = 128 * 1024;
1793 else if (INTEL_INFO(dev)->gen >= 4)
1794 alignment = 4 * 1024;
1795 else
1796 alignment = 64 * 1024;
1797 break;
1798 case I915_TILING_X:
1799 /* pin() will align the object as required by fence */
1800 alignment = 0;
1801 break;
1802 case I915_TILING_Y:
1803 /* Despite that we check this in framebuffer_init userspace can
1804 * screw us over and change the tiling after the fact. Only
1805 * pinned buffers can't change their tiling. */
1806 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1807 return -EINVAL;
1808 default:
1809 BUG();
1810 }
1811
1812 /* Note that the w/a also requires 64 PTE of padding following the
1813 * bo. We currently fill all unused PTE with the shadow page and so
1814 * we should always have valid PTE following the scanout preventing
1815 * the VT-d warning.
1816 */
1817 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1818 alignment = 256 * 1024;
1819
1820 dev_priv->mm.interruptible = false;
1821 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1822 if (ret)
1823 goto err_interruptible;
1824
1825 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1826 * fence, whereas 965+ only requires a fence if using
1827 * framebuffer compression. For simplicity, we always install
1828 * a fence as the cost is not that onerous.
1829 */
1830 ret = i915_gem_object_get_fence(obj);
1831 if (ret)
1832 goto err_unpin;
1833
1834 i915_gem_object_pin_fence(obj);
1835
1836 dev_priv->mm.interruptible = true;
1837 return 0;
1838
1839 err_unpin:
1840 i915_gem_object_unpin(obj);
1841 err_interruptible:
1842 dev_priv->mm.interruptible = true;
1843 return ret;
1844 }
1845
1846 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1847 {
1848 i915_gem_object_unpin_fence(obj);
1849 i915_gem_object_unpin(obj);
1850 }
1851
1852 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1853 * is assumed to be a power-of-two. */
1854 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1855 unsigned int tiling_mode,
1856 unsigned int cpp,
1857 unsigned int pitch)
1858 {
1859 if (tiling_mode != I915_TILING_NONE) {
1860 unsigned int tile_rows, tiles;
1861
1862 tile_rows = *y / 8;
1863 *y %= 8;
1864
1865 tiles = *x / (512/cpp);
1866 *x %= 512/cpp;
1867
1868 return tile_rows * pitch * 8 + tiles * 4096;
1869 } else {
1870 unsigned int offset;
1871
1872 offset = *y * pitch + *x * cpp;
1873 *y = 0;
1874 *x = (offset & 4095) / cpp;
1875 return offset & -4096;
1876 }
1877 }
1878
1879 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1880 int x, int y)
1881 {
1882 struct drm_device *dev = crtc->dev;
1883 struct drm_i915_private *dev_priv = dev->dev_private;
1884 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1885 struct intel_framebuffer *intel_fb;
1886 struct drm_i915_gem_object *obj;
1887 int plane = intel_crtc->plane;
1888 unsigned long linear_offset;
1889 u32 dspcntr;
1890 u32 reg;
1891
1892 switch (plane) {
1893 case 0:
1894 case 1:
1895 break;
1896 default:
1897 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1898 return -EINVAL;
1899 }
1900
1901 intel_fb = to_intel_framebuffer(fb);
1902 obj = intel_fb->obj;
1903
1904 reg = DSPCNTR(plane);
1905 dspcntr = I915_READ(reg);
1906 /* Mask out pixel format bits in case we change it */
1907 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1908 switch (fb->pixel_format) {
1909 case DRM_FORMAT_C8:
1910 dspcntr |= DISPPLANE_8BPP;
1911 break;
1912 case DRM_FORMAT_XRGB1555:
1913 case DRM_FORMAT_ARGB1555:
1914 dspcntr |= DISPPLANE_BGRX555;
1915 break;
1916 case DRM_FORMAT_RGB565:
1917 dspcntr |= DISPPLANE_BGRX565;
1918 break;
1919 case DRM_FORMAT_XRGB8888:
1920 case DRM_FORMAT_ARGB8888:
1921 dspcntr |= DISPPLANE_BGRX888;
1922 break;
1923 case DRM_FORMAT_XBGR8888:
1924 case DRM_FORMAT_ABGR8888:
1925 dspcntr |= DISPPLANE_RGBX888;
1926 break;
1927 case DRM_FORMAT_XRGB2101010:
1928 case DRM_FORMAT_ARGB2101010:
1929 dspcntr |= DISPPLANE_BGRX101010;
1930 break;
1931 case DRM_FORMAT_XBGR2101010:
1932 case DRM_FORMAT_ABGR2101010:
1933 dspcntr |= DISPPLANE_RGBX101010;
1934 break;
1935 default:
1936 BUG();
1937 }
1938
1939 if (INTEL_INFO(dev)->gen >= 4) {
1940 if (obj->tiling_mode != I915_TILING_NONE)
1941 dspcntr |= DISPPLANE_TILED;
1942 else
1943 dspcntr &= ~DISPPLANE_TILED;
1944 }
1945
1946 I915_WRITE(reg, dspcntr);
1947
1948 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1949
1950 if (INTEL_INFO(dev)->gen >= 4) {
1951 intel_crtc->dspaddr_offset =
1952 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1953 fb->bits_per_pixel / 8,
1954 fb->pitches[0]);
1955 linear_offset -= intel_crtc->dspaddr_offset;
1956 } else {
1957 intel_crtc->dspaddr_offset = linear_offset;
1958 }
1959
1960 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
1961 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
1962 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1963 if (INTEL_INFO(dev)->gen >= 4) {
1964 I915_MODIFY_DISPBASE(DSPSURF(plane),
1965 obj->gtt_offset + intel_crtc->dspaddr_offset);
1966 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1967 I915_WRITE(DSPLINOFF(plane), linear_offset);
1968 } else
1969 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
1970 POSTING_READ(reg);
1971
1972 return 0;
1973 }
1974
1975 static int ironlake_update_plane(struct drm_crtc *crtc,
1976 struct drm_framebuffer *fb, int x, int y)
1977 {
1978 struct drm_device *dev = crtc->dev;
1979 struct drm_i915_private *dev_priv = dev->dev_private;
1980 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1981 struct intel_framebuffer *intel_fb;
1982 struct drm_i915_gem_object *obj;
1983 int plane = intel_crtc->plane;
1984 unsigned long linear_offset;
1985 u32 dspcntr;
1986 u32 reg;
1987
1988 switch (plane) {
1989 case 0:
1990 case 1:
1991 case 2:
1992 break;
1993 default:
1994 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1995 return -EINVAL;
1996 }
1997
1998 intel_fb = to_intel_framebuffer(fb);
1999 obj = intel_fb->obj;
2000
2001 reg = DSPCNTR(plane);
2002 dspcntr = I915_READ(reg);
2003 /* Mask out pixel format bits in case we change it */
2004 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2005 switch (fb->pixel_format) {
2006 case DRM_FORMAT_C8:
2007 dspcntr |= DISPPLANE_8BPP;
2008 break;
2009 case DRM_FORMAT_RGB565:
2010 dspcntr |= DISPPLANE_BGRX565;
2011 break;
2012 case DRM_FORMAT_XRGB8888:
2013 case DRM_FORMAT_ARGB8888:
2014 dspcntr |= DISPPLANE_BGRX888;
2015 break;
2016 case DRM_FORMAT_XBGR8888:
2017 case DRM_FORMAT_ABGR8888:
2018 dspcntr |= DISPPLANE_RGBX888;
2019 break;
2020 case DRM_FORMAT_XRGB2101010:
2021 case DRM_FORMAT_ARGB2101010:
2022 dspcntr |= DISPPLANE_BGRX101010;
2023 break;
2024 case DRM_FORMAT_XBGR2101010:
2025 case DRM_FORMAT_ABGR2101010:
2026 dspcntr |= DISPPLANE_RGBX101010;
2027 break;
2028 default:
2029 BUG();
2030 }
2031
2032 if (obj->tiling_mode != I915_TILING_NONE)
2033 dspcntr |= DISPPLANE_TILED;
2034 else
2035 dspcntr &= ~DISPPLANE_TILED;
2036
2037 /* must disable */
2038 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2039
2040 I915_WRITE(reg, dspcntr);
2041
2042 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2043 intel_crtc->dspaddr_offset =
2044 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2045 fb->bits_per_pixel / 8,
2046 fb->pitches[0]);
2047 linear_offset -= intel_crtc->dspaddr_offset;
2048
2049 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2050 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2051 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2052 I915_MODIFY_DISPBASE(DSPSURF(plane),
2053 obj->gtt_offset + intel_crtc->dspaddr_offset);
2054 if (IS_HASWELL(dev)) {
2055 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2056 } else {
2057 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2058 I915_WRITE(DSPLINOFF(plane), linear_offset);
2059 }
2060 POSTING_READ(reg);
2061
2062 return 0;
2063 }
2064
2065 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2066 static int
2067 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2068 int x, int y, enum mode_set_atomic state)
2069 {
2070 struct drm_device *dev = crtc->dev;
2071 struct drm_i915_private *dev_priv = dev->dev_private;
2072
2073 if (dev_priv->display.disable_fbc)
2074 dev_priv->display.disable_fbc(dev);
2075 intel_increase_pllclock(crtc);
2076
2077 return dev_priv->display.update_plane(crtc, fb, x, y);
2078 }
2079
2080 void intel_display_handle_reset(struct drm_device *dev)
2081 {
2082 struct drm_i915_private *dev_priv = dev->dev_private;
2083 struct drm_crtc *crtc;
2084
2085 /*
2086 * Flips in the rings have been nuked by the reset,
2087 * so complete all pending flips so that user space
2088 * will get its events and not get stuck.
2089 *
2090 * Also update the base address of all primary
2091 * planes to the the last fb to make sure we're
2092 * showing the correct fb after a reset.
2093 *
2094 * Need to make two loops over the crtcs so that we
2095 * don't try to grab a crtc mutex before the
2096 * pending_flip_queue really got woken up.
2097 */
2098
2099 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2100 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2101 enum plane plane = intel_crtc->plane;
2102
2103 intel_prepare_page_flip(dev, plane);
2104 intel_finish_page_flip_plane(dev, plane);
2105 }
2106
2107 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2108 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2109
2110 mutex_lock(&crtc->mutex);
2111 if (intel_crtc->active)
2112 dev_priv->display.update_plane(crtc, crtc->fb,
2113 crtc->x, crtc->y);
2114 mutex_unlock(&crtc->mutex);
2115 }
2116 }
2117
2118 static int
2119 intel_finish_fb(struct drm_framebuffer *old_fb)
2120 {
2121 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2122 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2123 bool was_interruptible = dev_priv->mm.interruptible;
2124 int ret;
2125
2126 /* Big Hammer, we also need to ensure that any pending
2127 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2128 * current scanout is retired before unpinning the old
2129 * framebuffer.
2130 *
2131 * This should only fail upon a hung GPU, in which case we
2132 * can safely continue.
2133 */
2134 dev_priv->mm.interruptible = false;
2135 ret = i915_gem_object_finish_gpu(obj);
2136 dev_priv->mm.interruptible = was_interruptible;
2137
2138 return ret;
2139 }
2140
2141 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2142 {
2143 struct drm_device *dev = crtc->dev;
2144 struct drm_i915_master_private *master_priv;
2145 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2146
2147 if (!dev->primary->master)
2148 return;
2149
2150 master_priv = dev->primary->master->driver_priv;
2151 if (!master_priv->sarea_priv)
2152 return;
2153
2154 switch (intel_crtc->pipe) {
2155 case 0:
2156 master_priv->sarea_priv->pipeA_x = x;
2157 master_priv->sarea_priv->pipeA_y = y;
2158 break;
2159 case 1:
2160 master_priv->sarea_priv->pipeB_x = x;
2161 master_priv->sarea_priv->pipeB_y = y;
2162 break;
2163 default:
2164 break;
2165 }
2166 }
2167
2168 static int
2169 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2170 struct drm_framebuffer *fb)
2171 {
2172 struct drm_device *dev = crtc->dev;
2173 struct drm_i915_private *dev_priv = dev->dev_private;
2174 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2175 struct drm_framebuffer *old_fb;
2176 int ret;
2177
2178 /* no fb bound */
2179 if (!fb) {
2180 DRM_ERROR("No FB bound\n");
2181 return 0;
2182 }
2183
2184 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2185 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2186 plane_name(intel_crtc->plane),
2187 INTEL_INFO(dev)->num_pipes);
2188 return -EINVAL;
2189 }
2190
2191 mutex_lock(&dev->struct_mutex);
2192 ret = intel_pin_and_fence_fb_obj(dev,
2193 to_intel_framebuffer(fb)->obj,
2194 NULL);
2195 if (ret != 0) {
2196 mutex_unlock(&dev->struct_mutex);
2197 DRM_ERROR("pin & fence failed\n");
2198 return ret;
2199 }
2200
2201 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2202 if (ret) {
2203 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2204 mutex_unlock(&dev->struct_mutex);
2205 DRM_ERROR("failed to update base address\n");
2206 return ret;
2207 }
2208
2209 old_fb = crtc->fb;
2210 crtc->fb = fb;
2211 crtc->x = x;
2212 crtc->y = y;
2213
2214 if (old_fb) {
2215 if (intel_crtc->active && old_fb != fb)
2216 intel_wait_for_vblank(dev, intel_crtc->pipe);
2217 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2218 }
2219
2220 intel_update_fbc(dev);
2221 mutex_unlock(&dev->struct_mutex);
2222
2223 intel_crtc_update_sarea_pos(crtc, x, y);
2224
2225 return 0;
2226 }
2227
2228 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2229 {
2230 struct drm_device *dev = crtc->dev;
2231 struct drm_i915_private *dev_priv = dev->dev_private;
2232 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2233 int pipe = intel_crtc->pipe;
2234 u32 reg, temp;
2235
2236 /* enable normal train */
2237 reg = FDI_TX_CTL(pipe);
2238 temp = I915_READ(reg);
2239 if (IS_IVYBRIDGE(dev)) {
2240 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2241 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2242 } else {
2243 temp &= ~FDI_LINK_TRAIN_NONE;
2244 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2245 }
2246 I915_WRITE(reg, temp);
2247
2248 reg = FDI_RX_CTL(pipe);
2249 temp = I915_READ(reg);
2250 if (HAS_PCH_CPT(dev)) {
2251 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2252 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2253 } else {
2254 temp &= ~FDI_LINK_TRAIN_NONE;
2255 temp |= FDI_LINK_TRAIN_NONE;
2256 }
2257 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2258
2259 /* wait one idle pattern time */
2260 POSTING_READ(reg);
2261 udelay(1000);
2262
2263 /* IVB wants error correction enabled */
2264 if (IS_IVYBRIDGE(dev))
2265 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2266 FDI_FE_ERRC_ENABLE);
2267 }
2268
2269 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2270 {
2271 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2272 }
2273
2274 static void ivb_modeset_global_resources(struct drm_device *dev)
2275 {
2276 struct drm_i915_private *dev_priv = dev->dev_private;
2277 struct intel_crtc *pipe_B_crtc =
2278 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2279 struct intel_crtc *pipe_C_crtc =
2280 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2281 uint32_t temp;
2282
2283 /*
2284 * When everything is off disable fdi C so that we could enable fdi B
2285 * with all lanes. Note that we don't care about enabled pipes without
2286 * an enabled pch encoder.
2287 */
2288 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2289 !pipe_has_enabled_pch(pipe_C_crtc)) {
2290 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2291 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2292
2293 temp = I915_READ(SOUTH_CHICKEN1);
2294 temp &= ~FDI_BC_BIFURCATION_SELECT;
2295 DRM_DEBUG_KMS("disabling fdi C rx\n");
2296 I915_WRITE(SOUTH_CHICKEN1, temp);
2297 }
2298 }
2299
2300 /* The FDI link training functions for ILK/Ibexpeak. */
2301 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2302 {
2303 struct drm_device *dev = crtc->dev;
2304 struct drm_i915_private *dev_priv = dev->dev_private;
2305 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2306 int pipe = intel_crtc->pipe;
2307 int plane = intel_crtc->plane;
2308 u32 reg, temp, tries;
2309
2310 /* FDI needs bits from pipe & plane first */
2311 assert_pipe_enabled(dev_priv, pipe);
2312 assert_plane_enabled(dev_priv, plane);
2313
2314 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2315 for train result */
2316 reg = FDI_RX_IMR(pipe);
2317 temp = I915_READ(reg);
2318 temp &= ~FDI_RX_SYMBOL_LOCK;
2319 temp &= ~FDI_RX_BIT_LOCK;
2320 I915_WRITE(reg, temp);
2321 I915_READ(reg);
2322 udelay(150);
2323
2324 /* enable CPU FDI TX and PCH FDI RX */
2325 reg = FDI_TX_CTL(pipe);
2326 temp = I915_READ(reg);
2327 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2328 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2329 temp &= ~FDI_LINK_TRAIN_NONE;
2330 temp |= FDI_LINK_TRAIN_PATTERN_1;
2331 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2332
2333 reg = FDI_RX_CTL(pipe);
2334 temp = I915_READ(reg);
2335 temp &= ~FDI_LINK_TRAIN_NONE;
2336 temp |= FDI_LINK_TRAIN_PATTERN_1;
2337 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2338
2339 POSTING_READ(reg);
2340 udelay(150);
2341
2342 /* Ironlake workaround, enable clock pointer after FDI enable*/
2343 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2344 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2345 FDI_RX_PHASE_SYNC_POINTER_EN);
2346
2347 reg = FDI_RX_IIR(pipe);
2348 for (tries = 0; tries < 5; tries++) {
2349 temp = I915_READ(reg);
2350 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2351
2352 if ((temp & FDI_RX_BIT_LOCK)) {
2353 DRM_DEBUG_KMS("FDI train 1 done.\n");
2354 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2355 break;
2356 }
2357 }
2358 if (tries == 5)
2359 DRM_ERROR("FDI train 1 fail!\n");
2360
2361 /* Train 2 */
2362 reg = FDI_TX_CTL(pipe);
2363 temp = I915_READ(reg);
2364 temp &= ~FDI_LINK_TRAIN_NONE;
2365 temp |= FDI_LINK_TRAIN_PATTERN_2;
2366 I915_WRITE(reg, temp);
2367
2368 reg = FDI_RX_CTL(pipe);
2369 temp = I915_READ(reg);
2370 temp &= ~FDI_LINK_TRAIN_NONE;
2371 temp |= FDI_LINK_TRAIN_PATTERN_2;
2372 I915_WRITE(reg, temp);
2373
2374 POSTING_READ(reg);
2375 udelay(150);
2376
2377 reg = FDI_RX_IIR(pipe);
2378 for (tries = 0; tries < 5; tries++) {
2379 temp = I915_READ(reg);
2380 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2381
2382 if (temp & FDI_RX_SYMBOL_LOCK) {
2383 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2384 DRM_DEBUG_KMS("FDI train 2 done.\n");
2385 break;
2386 }
2387 }
2388 if (tries == 5)
2389 DRM_ERROR("FDI train 2 fail!\n");
2390
2391 DRM_DEBUG_KMS("FDI train done\n");
2392
2393 }
2394
2395 static const int snb_b_fdi_train_param[] = {
2396 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2397 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2398 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2399 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2400 };
2401
2402 /* The FDI link training functions for SNB/Cougarpoint. */
2403 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2404 {
2405 struct drm_device *dev = crtc->dev;
2406 struct drm_i915_private *dev_priv = dev->dev_private;
2407 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2408 int pipe = intel_crtc->pipe;
2409 u32 reg, temp, i, retry;
2410
2411 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2412 for train result */
2413 reg = FDI_RX_IMR(pipe);
2414 temp = I915_READ(reg);
2415 temp &= ~FDI_RX_SYMBOL_LOCK;
2416 temp &= ~FDI_RX_BIT_LOCK;
2417 I915_WRITE(reg, temp);
2418
2419 POSTING_READ(reg);
2420 udelay(150);
2421
2422 /* enable CPU FDI TX and PCH FDI RX */
2423 reg = FDI_TX_CTL(pipe);
2424 temp = I915_READ(reg);
2425 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2426 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2427 temp &= ~FDI_LINK_TRAIN_NONE;
2428 temp |= FDI_LINK_TRAIN_PATTERN_1;
2429 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2430 /* SNB-B */
2431 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2432 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2433
2434 I915_WRITE(FDI_RX_MISC(pipe),
2435 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2436
2437 reg = FDI_RX_CTL(pipe);
2438 temp = I915_READ(reg);
2439 if (HAS_PCH_CPT(dev)) {
2440 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2441 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2442 } else {
2443 temp &= ~FDI_LINK_TRAIN_NONE;
2444 temp |= FDI_LINK_TRAIN_PATTERN_1;
2445 }
2446 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2447
2448 POSTING_READ(reg);
2449 udelay(150);
2450
2451 for (i = 0; i < 4; i++) {
2452 reg = FDI_TX_CTL(pipe);
2453 temp = I915_READ(reg);
2454 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2455 temp |= snb_b_fdi_train_param[i];
2456 I915_WRITE(reg, temp);
2457
2458 POSTING_READ(reg);
2459 udelay(500);
2460
2461 for (retry = 0; retry < 5; retry++) {
2462 reg = FDI_RX_IIR(pipe);
2463 temp = I915_READ(reg);
2464 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2465 if (temp & FDI_RX_BIT_LOCK) {
2466 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2467 DRM_DEBUG_KMS("FDI train 1 done.\n");
2468 break;
2469 }
2470 udelay(50);
2471 }
2472 if (retry < 5)
2473 break;
2474 }
2475 if (i == 4)
2476 DRM_ERROR("FDI train 1 fail!\n");
2477
2478 /* Train 2 */
2479 reg = FDI_TX_CTL(pipe);
2480 temp = I915_READ(reg);
2481 temp &= ~FDI_LINK_TRAIN_NONE;
2482 temp |= FDI_LINK_TRAIN_PATTERN_2;
2483 if (IS_GEN6(dev)) {
2484 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2485 /* SNB-B */
2486 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2487 }
2488 I915_WRITE(reg, temp);
2489
2490 reg = FDI_RX_CTL(pipe);
2491 temp = I915_READ(reg);
2492 if (HAS_PCH_CPT(dev)) {
2493 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2494 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2495 } else {
2496 temp &= ~FDI_LINK_TRAIN_NONE;
2497 temp |= FDI_LINK_TRAIN_PATTERN_2;
2498 }
2499 I915_WRITE(reg, temp);
2500
2501 POSTING_READ(reg);
2502 udelay(150);
2503
2504 for (i = 0; i < 4; i++) {
2505 reg = FDI_TX_CTL(pipe);
2506 temp = I915_READ(reg);
2507 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2508 temp |= snb_b_fdi_train_param[i];
2509 I915_WRITE(reg, temp);
2510
2511 POSTING_READ(reg);
2512 udelay(500);
2513
2514 for (retry = 0; retry < 5; retry++) {
2515 reg = FDI_RX_IIR(pipe);
2516 temp = I915_READ(reg);
2517 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2518 if (temp & FDI_RX_SYMBOL_LOCK) {
2519 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2520 DRM_DEBUG_KMS("FDI train 2 done.\n");
2521 break;
2522 }
2523 udelay(50);
2524 }
2525 if (retry < 5)
2526 break;
2527 }
2528 if (i == 4)
2529 DRM_ERROR("FDI train 2 fail!\n");
2530
2531 DRM_DEBUG_KMS("FDI train done.\n");
2532 }
2533
2534 /* Manual link training for Ivy Bridge A0 parts */
2535 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2536 {
2537 struct drm_device *dev = crtc->dev;
2538 struct drm_i915_private *dev_priv = dev->dev_private;
2539 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2540 int pipe = intel_crtc->pipe;
2541 u32 reg, temp, i;
2542
2543 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2544 for train result */
2545 reg = FDI_RX_IMR(pipe);
2546 temp = I915_READ(reg);
2547 temp &= ~FDI_RX_SYMBOL_LOCK;
2548 temp &= ~FDI_RX_BIT_LOCK;
2549 I915_WRITE(reg, temp);
2550
2551 POSTING_READ(reg);
2552 udelay(150);
2553
2554 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2555 I915_READ(FDI_RX_IIR(pipe)));
2556
2557 /* enable CPU FDI TX and PCH FDI RX */
2558 reg = FDI_TX_CTL(pipe);
2559 temp = I915_READ(reg);
2560 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2561 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2562 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2563 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2564 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2565 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2566 temp |= FDI_COMPOSITE_SYNC;
2567 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2568
2569 I915_WRITE(FDI_RX_MISC(pipe),
2570 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2571
2572 reg = FDI_RX_CTL(pipe);
2573 temp = I915_READ(reg);
2574 temp &= ~FDI_LINK_TRAIN_AUTO;
2575 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2576 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2577 temp |= FDI_COMPOSITE_SYNC;
2578 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2579
2580 POSTING_READ(reg);
2581 udelay(150);
2582
2583 for (i = 0; i < 4; i++) {
2584 reg = FDI_TX_CTL(pipe);
2585 temp = I915_READ(reg);
2586 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2587 temp |= snb_b_fdi_train_param[i];
2588 I915_WRITE(reg, temp);
2589
2590 POSTING_READ(reg);
2591 udelay(500);
2592
2593 reg = FDI_RX_IIR(pipe);
2594 temp = I915_READ(reg);
2595 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2596
2597 if (temp & FDI_RX_BIT_LOCK ||
2598 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2599 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2600 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2601 break;
2602 }
2603 }
2604 if (i == 4)
2605 DRM_ERROR("FDI train 1 fail!\n");
2606
2607 /* Train 2 */
2608 reg = FDI_TX_CTL(pipe);
2609 temp = I915_READ(reg);
2610 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2611 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2612 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2613 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2614 I915_WRITE(reg, temp);
2615
2616 reg = FDI_RX_CTL(pipe);
2617 temp = I915_READ(reg);
2618 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2619 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2620 I915_WRITE(reg, temp);
2621
2622 POSTING_READ(reg);
2623 udelay(150);
2624
2625 for (i = 0; i < 4; i++) {
2626 reg = FDI_TX_CTL(pipe);
2627 temp = I915_READ(reg);
2628 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2629 temp |= snb_b_fdi_train_param[i];
2630 I915_WRITE(reg, temp);
2631
2632 POSTING_READ(reg);
2633 udelay(500);
2634
2635 reg = FDI_RX_IIR(pipe);
2636 temp = I915_READ(reg);
2637 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2638
2639 if (temp & FDI_RX_SYMBOL_LOCK) {
2640 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2641 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2642 break;
2643 }
2644 }
2645 if (i == 4)
2646 DRM_ERROR("FDI train 2 fail!\n");
2647
2648 DRM_DEBUG_KMS("FDI train done.\n");
2649 }
2650
2651 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2652 {
2653 struct drm_device *dev = intel_crtc->base.dev;
2654 struct drm_i915_private *dev_priv = dev->dev_private;
2655 int pipe = intel_crtc->pipe;
2656 u32 reg, temp;
2657
2658
2659 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2660 reg = FDI_RX_CTL(pipe);
2661 temp = I915_READ(reg);
2662 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2663 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2664 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2665 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2666
2667 POSTING_READ(reg);
2668 udelay(200);
2669
2670 /* Switch from Rawclk to PCDclk */
2671 temp = I915_READ(reg);
2672 I915_WRITE(reg, temp | FDI_PCDCLK);
2673
2674 POSTING_READ(reg);
2675 udelay(200);
2676
2677 /* Enable CPU FDI TX PLL, always on for Ironlake */
2678 reg = FDI_TX_CTL(pipe);
2679 temp = I915_READ(reg);
2680 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2681 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2682
2683 POSTING_READ(reg);
2684 udelay(100);
2685 }
2686 }
2687
2688 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2689 {
2690 struct drm_device *dev = intel_crtc->base.dev;
2691 struct drm_i915_private *dev_priv = dev->dev_private;
2692 int pipe = intel_crtc->pipe;
2693 u32 reg, temp;
2694
2695 /* Switch from PCDclk to Rawclk */
2696 reg = FDI_RX_CTL(pipe);
2697 temp = I915_READ(reg);
2698 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2699
2700 /* Disable CPU FDI TX PLL */
2701 reg = FDI_TX_CTL(pipe);
2702 temp = I915_READ(reg);
2703 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2704
2705 POSTING_READ(reg);
2706 udelay(100);
2707
2708 reg = FDI_RX_CTL(pipe);
2709 temp = I915_READ(reg);
2710 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2711
2712 /* Wait for the clocks to turn off. */
2713 POSTING_READ(reg);
2714 udelay(100);
2715 }
2716
2717 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2718 {
2719 struct drm_device *dev = crtc->dev;
2720 struct drm_i915_private *dev_priv = dev->dev_private;
2721 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2722 int pipe = intel_crtc->pipe;
2723 u32 reg, temp;
2724
2725 /* disable CPU FDI tx and PCH FDI rx */
2726 reg = FDI_TX_CTL(pipe);
2727 temp = I915_READ(reg);
2728 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2729 POSTING_READ(reg);
2730
2731 reg = FDI_RX_CTL(pipe);
2732 temp = I915_READ(reg);
2733 temp &= ~(0x7 << 16);
2734 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2735 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2736
2737 POSTING_READ(reg);
2738 udelay(100);
2739
2740 /* Ironlake workaround, disable clock pointer after downing FDI */
2741 if (HAS_PCH_IBX(dev)) {
2742 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2743 }
2744
2745 /* still set train pattern 1 */
2746 reg = FDI_TX_CTL(pipe);
2747 temp = I915_READ(reg);
2748 temp &= ~FDI_LINK_TRAIN_NONE;
2749 temp |= FDI_LINK_TRAIN_PATTERN_1;
2750 I915_WRITE(reg, temp);
2751
2752 reg = FDI_RX_CTL(pipe);
2753 temp = I915_READ(reg);
2754 if (HAS_PCH_CPT(dev)) {
2755 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2756 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2757 } else {
2758 temp &= ~FDI_LINK_TRAIN_NONE;
2759 temp |= FDI_LINK_TRAIN_PATTERN_1;
2760 }
2761 /* BPC in FDI rx is consistent with that in PIPECONF */
2762 temp &= ~(0x07 << 16);
2763 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2764 I915_WRITE(reg, temp);
2765
2766 POSTING_READ(reg);
2767 udelay(100);
2768 }
2769
2770 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2771 {
2772 struct drm_device *dev = crtc->dev;
2773 struct drm_i915_private *dev_priv = dev->dev_private;
2774 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2775 unsigned long flags;
2776 bool pending;
2777
2778 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2779 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2780 return false;
2781
2782 spin_lock_irqsave(&dev->event_lock, flags);
2783 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2784 spin_unlock_irqrestore(&dev->event_lock, flags);
2785
2786 return pending;
2787 }
2788
2789 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2790 {
2791 struct drm_device *dev = crtc->dev;
2792 struct drm_i915_private *dev_priv = dev->dev_private;
2793
2794 if (crtc->fb == NULL)
2795 return;
2796
2797 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2798
2799 wait_event(dev_priv->pending_flip_queue,
2800 !intel_crtc_has_pending_flip(crtc));
2801
2802 mutex_lock(&dev->struct_mutex);
2803 intel_finish_fb(crtc->fb);
2804 mutex_unlock(&dev->struct_mutex);
2805 }
2806
2807 /* Program iCLKIP clock to the desired frequency */
2808 static void lpt_program_iclkip(struct drm_crtc *crtc)
2809 {
2810 struct drm_device *dev = crtc->dev;
2811 struct drm_i915_private *dev_priv = dev->dev_private;
2812 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2813 u32 temp;
2814
2815 mutex_lock(&dev_priv->dpio_lock);
2816
2817 /* It is necessary to ungate the pixclk gate prior to programming
2818 * the divisors, and gate it back when it is done.
2819 */
2820 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2821
2822 /* Disable SSCCTL */
2823 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2824 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2825 SBI_SSCCTL_DISABLE,
2826 SBI_ICLK);
2827
2828 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2829 if (crtc->mode.clock == 20000) {
2830 auxdiv = 1;
2831 divsel = 0x41;
2832 phaseinc = 0x20;
2833 } else {
2834 /* The iCLK virtual clock root frequency is in MHz,
2835 * but the crtc->mode.clock in in KHz. To get the divisors,
2836 * it is necessary to divide one by another, so we
2837 * convert the virtual clock precision to KHz here for higher
2838 * precision.
2839 */
2840 u32 iclk_virtual_root_freq = 172800 * 1000;
2841 u32 iclk_pi_range = 64;
2842 u32 desired_divisor, msb_divisor_value, pi_value;
2843
2844 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2845 msb_divisor_value = desired_divisor / iclk_pi_range;
2846 pi_value = desired_divisor % iclk_pi_range;
2847
2848 auxdiv = 0;
2849 divsel = msb_divisor_value - 2;
2850 phaseinc = pi_value;
2851 }
2852
2853 /* This should not happen with any sane values */
2854 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2855 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2856 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2857 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2858
2859 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2860 crtc->mode.clock,
2861 auxdiv,
2862 divsel,
2863 phasedir,
2864 phaseinc);
2865
2866 /* Program SSCDIVINTPHASE6 */
2867 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2868 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2869 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2870 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2871 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2872 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2873 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2874 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2875
2876 /* Program SSCAUXDIV */
2877 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2878 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2879 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2880 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2881
2882 /* Enable modulator and associated divider */
2883 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2884 temp &= ~SBI_SSCCTL_DISABLE;
2885 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2886
2887 /* Wait for initialization time */
2888 udelay(24);
2889
2890 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2891
2892 mutex_unlock(&dev_priv->dpio_lock);
2893 }
2894
2895 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2896 enum pipe pch_transcoder)
2897 {
2898 struct drm_device *dev = crtc->base.dev;
2899 struct drm_i915_private *dev_priv = dev->dev_private;
2900 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2901
2902 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2903 I915_READ(HTOTAL(cpu_transcoder)));
2904 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2905 I915_READ(HBLANK(cpu_transcoder)));
2906 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2907 I915_READ(HSYNC(cpu_transcoder)));
2908
2909 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2910 I915_READ(VTOTAL(cpu_transcoder)));
2911 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2912 I915_READ(VBLANK(cpu_transcoder)));
2913 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2914 I915_READ(VSYNC(cpu_transcoder)));
2915 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2916 I915_READ(VSYNCSHIFT(cpu_transcoder)));
2917 }
2918
2919 /*
2920 * Enable PCH resources required for PCH ports:
2921 * - PCH PLLs
2922 * - FDI training & RX/TX
2923 * - update transcoder timings
2924 * - DP transcoding bits
2925 * - transcoder
2926 */
2927 static void ironlake_pch_enable(struct drm_crtc *crtc)
2928 {
2929 struct drm_device *dev = crtc->dev;
2930 struct drm_i915_private *dev_priv = dev->dev_private;
2931 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2932 int pipe = intel_crtc->pipe;
2933 u32 reg, temp;
2934
2935 assert_pch_transcoder_disabled(dev_priv, pipe);
2936
2937 /* Write the TU size bits before fdi link training, so that error
2938 * detection works. */
2939 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2940 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2941
2942 /* For PCH output, training FDI link */
2943 dev_priv->display.fdi_link_train(crtc);
2944
2945 /* XXX: pch pll's can be enabled any time before we enable the PCH
2946 * transcoder, and we actually should do this to not upset any PCH
2947 * transcoder that already use the clock when we share it.
2948 *
2949 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
2950 * unconditionally resets the pll - we need that to have the right LVDS
2951 * enable sequence. */
2952 ironlake_enable_pch_pll(intel_crtc);
2953
2954 if (HAS_PCH_CPT(dev)) {
2955 u32 sel;
2956
2957 temp = I915_READ(PCH_DPLL_SEL);
2958 switch (pipe) {
2959 default:
2960 case 0:
2961 temp |= TRANSA_DPLL_ENABLE;
2962 sel = TRANSA_DPLLB_SEL;
2963 break;
2964 case 1:
2965 temp |= TRANSB_DPLL_ENABLE;
2966 sel = TRANSB_DPLLB_SEL;
2967 break;
2968 case 2:
2969 temp |= TRANSC_DPLL_ENABLE;
2970 sel = TRANSC_DPLLB_SEL;
2971 break;
2972 }
2973 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2974 temp |= sel;
2975 else
2976 temp &= ~sel;
2977 I915_WRITE(PCH_DPLL_SEL, temp);
2978 }
2979
2980 /* set transcoder timing, panel must allow it */
2981 assert_panel_unlocked(dev_priv, pipe);
2982 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
2983
2984 intel_fdi_normal_train(crtc);
2985
2986 /* For PCH DP, enable TRANS_DP_CTL */
2987 if (HAS_PCH_CPT(dev) &&
2988 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2989 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2990 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
2991 reg = TRANS_DP_CTL(pipe);
2992 temp = I915_READ(reg);
2993 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2994 TRANS_DP_SYNC_MASK |
2995 TRANS_DP_BPC_MASK);
2996 temp |= (TRANS_DP_OUTPUT_ENABLE |
2997 TRANS_DP_ENH_FRAMING);
2998 temp |= bpc << 9; /* same format but at 11:9 */
2999
3000 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3001 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3002 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3003 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3004
3005 switch (intel_trans_dp_port_sel(crtc)) {
3006 case PCH_DP_B:
3007 temp |= TRANS_DP_PORT_SEL_B;
3008 break;
3009 case PCH_DP_C:
3010 temp |= TRANS_DP_PORT_SEL_C;
3011 break;
3012 case PCH_DP_D:
3013 temp |= TRANS_DP_PORT_SEL_D;
3014 break;
3015 default:
3016 BUG();
3017 }
3018
3019 I915_WRITE(reg, temp);
3020 }
3021
3022 ironlake_enable_pch_transcoder(dev_priv, pipe);
3023 }
3024
3025 static void lpt_pch_enable(struct drm_crtc *crtc)
3026 {
3027 struct drm_device *dev = crtc->dev;
3028 struct drm_i915_private *dev_priv = dev->dev_private;
3029 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3030 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3031
3032 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3033
3034 lpt_program_iclkip(crtc);
3035
3036 /* Set transcoder timing. */
3037 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3038
3039 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3040 }
3041
3042 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3043 {
3044 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3045
3046 if (pll == NULL)
3047 return;
3048
3049 if (pll->refcount == 0) {
3050 WARN(1, "bad PCH PLL refcount\n");
3051 return;
3052 }
3053
3054 --pll->refcount;
3055 intel_crtc->pch_pll = NULL;
3056 }
3057
3058 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3059 {
3060 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3061 struct intel_pch_pll *pll;
3062 int i;
3063
3064 pll = intel_crtc->pch_pll;
3065 if (pll) {
3066 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3067 intel_crtc->base.base.id, pll->pll_reg);
3068 goto prepare;
3069 }
3070
3071 if (HAS_PCH_IBX(dev_priv->dev)) {
3072 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3073 i = intel_crtc->pipe;
3074 pll = &dev_priv->pch_plls[i];
3075
3076 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3077 intel_crtc->base.base.id, pll->pll_reg);
3078
3079 goto found;
3080 }
3081
3082 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3083 pll = &dev_priv->pch_plls[i];
3084
3085 /* Only want to check enabled timings first */
3086 if (pll->refcount == 0)
3087 continue;
3088
3089 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3090 fp == I915_READ(pll->fp0_reg)) {
3091 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3092 intel_crtc->base.base.id,
3093 pll->pll_reg, pll->refcount, pll->active);
3094
3095 goto found;
3096 }
3097 }
3098
3099 /* Ok no matching timings, maybe there's a free one? */
3100 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3101 pll = &dev_priv->pch_plls[i];
3102 if (pll->refcount == 0) {
3103 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3104 intel_crtc->base.base.id, pll->pll_reg);
3105 goto found;
3106 }
3107 }
3108
3109 return NULL;
3110
3111 found:
3112 intel_crtc->pch_pll = pll;
3113 pll->refcount++;
3114 DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
3115 prepare: /* separate function? */
3116 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3117
3118 /* Wait for the clocks to stabilize before rewriting the regs */
3119 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3120 POSTING_READ(pll->pll_reg);
3121 udelay(150);
3122
3123 I915_WRITE(pll->fp0_reg, fp);
3124 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3125 pll->on = false;
3126 return pll;
3127 }
3128
3129 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3130 {
3131 struct drm_i915_private *dev_priv = dev->dev_private;
3132 int dslreg = PIPEDSL(pipe);
3133 u32 temp;
3134
3135 temp = I915_READ(dslreg);
3136 udelay(500);
3137 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3138 if (wait_for(I915_READ(dslreg) != temp, 5))
3139 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3140 }
3141 }
3142
3143 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3144 {
3145 struct drm_device *dev = crtc->base.dev;
3146 struct drm_i915_private *dev_priv = dev->dev_private;
3147 int pipe = crtc->pipe;
3148
3149 if (crtc->config.pch_pfit.size) {
3150 /* Force use of hard-coded filter coefficients
3151 * as some pre-programmed values are broken,
3152 * e.g. x201.
3153 */
3154 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3155 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3156 PF_PIPE_SEL_IVB(pipe));
3157 else
3158 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3159 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3160 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3161 }
3162 }
3163
3164 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3165 {
3166 struct drm_device *dev = crtc->dev;
3167 struct drm_i915_private *dev_priv = dev->dev_private;
3168 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3169 struct intel_encoder *encoder;
3170 int pipe = intel_crtc->pipe;
3171 int plane = intel_crtc->plane;
3172 u32 temp;
3173
3174 WARN_ON(!crtc->enabled);
3175
3176 if (intel_crtc->active)
3177 return;
3178
3179 intel_crtc->active = true;
3180
3181 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3182 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3183
3184 intel_update_watermarks(dev);
3185
3186 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3187 temp = I915_READ(PCH_LVDS);
3188 if ((temp & LVDS_PORT_EN) == 0)
3189 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3190 }
3191
3192
3193 if (intel_crtc->config.has_pch_encoder) {
3194 /* Note: FDI PLL enabling _must_ be done before we enable the
3195 * cpu pipes, hence this is separate from all the other fdi/pch
3196 * enabling. */
3197 ironlake_fdi_pll_enable(intel_crtc);
3198 } else {
3199 assert_fdi_tx_disabled(dev_priv, pipe);
3200 assert_fdi_rx_disabled(dev_priv, pipe);
3201 }
3202
3203 for_each_encoder_on_crtc(dev, crtc, encoder)
3204 if (encoder->pre_enable)
3205 encoder->pre_enable(encoder);
3206
3207 /* Enable panel fitting for LVDS */
3208 ironlake_pfit_enable(intel_crtc);
3209
3210 /*
3211 * On ILK+ LUT must be loaded before the pipe is running but with
3212 * clocks enabled
3213 */
3214 intel_crtc_load_lut(crtc);
3215
3216 intel_enable_pipe(dev_priv, pipe,
3217 intel_crtc->config.has_pch_encoder);
3218 intel_enable_plane(dev_priv, plane, pipe);
3219
3220 if (intel_crtc->config.has_pch_encoder)
3221 ironlake_pch_enable(crtc);
3222
3223 mutex_lock(&dev->struct_mutex);
3224 intel_update_fbc(dev);
3225 mutex_unlock(&dev->struct_mutex);
3226
3227 intel_crtc_update_cursor(crtc, true);
3228
3229 for_each_encoder_on_crtc(dev, crtc, encoder)
3230 encoder->enable(encoder);
3231
3232 if (HAS_PCH_CPT(dev))
3233 cpt_verify_modeset(dev, intel_crtc->pipe);
3234
3235 /*
3236 * There seems to be a race in PCH platform hw (at least on some
3237 * outputs) where an enabled pipe still completes any pageflip right
3238 * away (as if the pipe is off) instead of waiting for vblank. As soon
3239 * as the first vblank happend, everything works as expected. Hence just
3240 * wait for one vblank before returning to avoid strange things
3241 * happening.
3242 */
3243 intel_wait_for_vblank(dev, intel_crtc->pipe);
3244 }
3245
3246 /* IPS only exists on ULT machines and is tied to pipe A. */
3247 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3248 {
3249 return IS_ULT(crtc->base.dev) && crtc->pipe == PIPE_A;
3250 }
3251
3252 static void hsw_enable_ips(struct intel_crtc *crtc)
3253 {
3254 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3255
3256 if (!crtc->config.ips_enabled)
3257 return;
3258
3259 /* We can only enable IPS after we enable a plane and wait for a vblank.
3260 * We guarantee that the plane is enabled by calling intel_enable_ips
3261 * only after intel_enable_plane. And intel_enable_plane already waits
3262 * for a vblank, so all we need to do here is to enable the IPS bit. */
3263 assert_plane_enabled(dev_priv, crtc->plane);
3264 I915_WRITE(IPS_CTL, IPS_ENABLE);
3265 }
3266
3267 static void hsw_disable_ips(struct intel_crtc *crtc)
3268 {
3269 struct drm_device *dev = crtc->base.dev;
3270 struct drm_i915_private *dev_priv = dev->dev_private;
3271
3272 if (!crtc->config.ips_enabled)
3273 return;
3274
3275 assert_plane_enabled(dev_priv, crtc->plane);
3276 I915_WRITE(IPS_CTL, 0);
3277
3278 /* We need to wait for a vblank before we can disable the plane. */
3279 intel_wait_for_vblank(dev, crtc->pipe);
3280 }
3281
3282 static void haswell_crtc_enable(struct drm_crtc *crtc)
3283 {
3284 struct drm_device *dev = crtc->dev;
3285 struct drm_i915_private *dev_priv = dev->dev_private;
3286 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3287 struct intel_encoder *encoder;
3288 int pipe = intel_crtc->pipe;
3289 int plane = intel_crtc->plane;
3290
3291 WARN_ON(!crtc->enabled);
3292
3293 if (intel_crtc->active)
3294 return;
3295
3296 intel_crtc->active = true;
3297
3298 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3299 if (intel_crtc->config.has_pch_encoder)
3300 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3301
3302 intel_update_watermarks(dev);
3303
3304 if (intel_crtc->config.has_pch_encoder)
3305 dev_priv->display.fdi_link_train(crtc);
3306
3307 for_each_encoder_on_crtc(dev, crtc, encoder)
3308 if (encoder->pre_enable)
3309 encoder->pre_enable(encoder);
3310
3311 intel_ddi_enable_pipe_clock(intel_crtc);
3312
3313 /* Enable panel fitting for eDP */
3314 ironlake_pfit_enable(intel_crtc);
3315
3316 /*
3317 * On ILK+ LUT must be loaded before the pipe is running but with
3318 * clocks enabled
3319 */
3320 intel_crtc_load_lut(crtc);
3321
3322 intel_ddi_set_pipe_settings(crtc);
3323 intel_ddi_enable_transcoder_func(crtc);
3324
3325 intel_enable_pipe(dev_priv, pipe,
3326 intel_crtc->config.has_pch_encoder);
3327 intel_enable_plane(dev_priv, plane, pipe);
3328
3329 hsw_enable_ips(intel_crtc);
3330
3331 if (intel_crtc->config.has_pch_encoder)
3332 lpt_pch_enable(crtc);
3333
3334 mutex_lock(&dev->struct_mutex);
3335 intel_update_fbc(dev);
3336 mutex_unlock(&dev->struct_mutex);
3337
3338 intel_crtc_update_cursor(crtc, true);
3339
3340 for_each_encoder_on_crtc(dev, crtc, encoder)
3341 encoder->enable(encoder);
3342
3343 /*
3344 * There seems to be a race in PCH platform hw (at least on some
3345 * outputs) where an enabled pipe still completes any pageflip right
3346 * away (as if the pipe is off) instead of waiting for vblank. As soon
3347 * as the first vblank happend, everything works as expected. Hence just
3348 * wait for one vblank before returning to avoid strange things
3349 * happening.
3350 */
3351 intel_wait_for_vblank(dev, intel_crtc->pipe);
3352 }
3353
3354 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3355 {
3356 struct drm_device *dev = crtc->base.dev;
3357 struct drm_i915_private *dev_priv = dev->dev_private;
3358 int pipe = crtc->pipe;
3359
3360 /* To avoid upsetting the power well on haswell only disable the pfit if
3361 * it's in use. The hw state code will make sure we get this right. */
3362 if (crtc->config.pch_pfit.size) {
3363 I915_WRITE(PF_CTL(pipe), 0);
3364 I915_WRITE(PF_WIN_POS(pipe), 0);
3365 I915_WRITE(PF_WIN_SZ(pipe), 0);
3366 }
3367 }
3368
3369 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3370 {
3371 struct drm_device *dev = crtc->dev;
3372 struct drm_i915_private *dev_priv = dev->dev_private;
3373 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3374 struct intel_encoder *encoder;
3375 int pipe = intel_crtc->pipe;
3376 int plane = intel_crtc->plane;
3377 u32 reg, temp;
3378
3379
3380 if (!intel_crtc->active)
3381 return;
3382
3383 for_each_encoder_on_crtc(dev, crtc, encoder)
3384 encoder->disable(encoder);
3385
3386 intel_crtc_wait_for_pending_flips(crtc);
3387 drm_vblank_off(dev, pipe);
3388 intel_crtc_update_cursor(crtc, false);
3389
3390 intel_disable_plane(dev_priv, plane, pipe);
3391
3392 if (dev_priv->cfb_plane == plane)
3393 intel_disable_fbc(dev);
3394
3395 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3396 intel_disable_pipe(dev_priv, pipe);
3397
3398 ironlake_pfit_disable(intel_crtc);
3399
3400 for_each_encoder_on_crtc(dev, crtc, encoder)
3401 if (encoder->post_disable)
3402 encoder->post_disable(encoder);
3403
3404 ironlake_fdi_disable(crtc);
3405
3406 ironlake_disable_pch_transcoder(dev_priv, pipe);
3407 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3408
3409 if (HAS_PCH_CPT(dev)) {
3410 /* disable TRANS_DP_CTL */
3411 reg = TRANS_DP_CTL(pipe);
3412 temp = I915_READ(reg);
3413 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3414 temp |= TRANS_DP_PORT_SEL_NONE;
3415 I915_WRITE(reg, temp);
3416
3417 /* disable DPLL_SEL */
3418 temp = I915_READ(PCH_DPLL_SEL);
3419 switch (pipe) {
3420 case 0:
3421 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3422 break;
3423 case 1:
3424 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3425 break;
3426 case 2:
3427 /* C shares PLL A or B */
3428 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3429 break;
3430 default:
3431 BUG(); /* wtf */
3432 }
3433 I915_WRITE(PCH_DPLL_SEL, temp);
3434 }
3435
3436 /* disable PCH DPLL */
3437 intel_disable_pch_pll(intel_crtc);
3438
3439 ironlake_fdi_pll_disable(intel_crtc);
3440
3441 intel_crtc->active = false;
3442 intel_update_watermarks(dev);
3443
3444 mutex_lock(&dev->struct_mutex);
3445 intel_update_fbc(dev);
3446 mutex_unlock(&dev->struct_mutex);
3447 }
3448
3449 static void haswell_crtc_disable(struct drm_crtc *crtc)
3450 {
3451 struct drm_device *dev = crtc->dev;
3452 struct drm_i915_private *dev_priv = dev->dev_private;
3453 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3454 struct intel_encoder *encoder;
3455 int pipe = intel_crtc->pipe;
3456 int plane = intel_crtc->plane;
3457 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3458
3459 if (!intel_crtc->active)
3460 return;
3461
3462 for_each_encoder_on_crtc(dev, crtc, encoder)
3463 encoder->disable(encoder);
3464
3465 intel_crtc_wait_for_pending_flips(crtc);
3466 drm_vblank_off(dev, pipe);
3467 intel_crtc_update_cursor(crtc, false);
3468
3469 /* FBC must be disabled before disabling the plane on HSW. */
3470 if (dev_priv->cfb_plane == plane)
3471 intel_disable_fbc(dev);
3472
3473 hsw_disable_ips(intel_crtc);
3474
3475 intel_disable_plane(dev_priv, plane, pipe);
3476
3477 if (intel_crtc->config.has_pch_encoder)
3478 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3479 intel_disable_pipe(dev_priv, pipe);
3480
3481 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3482
3483 ironlake_pfit_disable(intel_crtc);
3484
3485 intel_ddi_disable_pipe_clock(intel_crtc);
3486
3487 for_each_encoder_on_crtc(dev, crtc, encoder)
3488 if (encoder->post_disable)
3489 encoder->post_disable(encoder);
3490
3491 if (intel_crtc->config.has_pch_encoder) {
3492 lpt_disable_pch_transcoder(dev_priv);
3493 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3494 intel_ddi_fdi_disable(crtc);
3495 }
3496
3497 intel_crtc->active = false;
3498 intel_update_watermarks(dev);
3499
3500 mutex_lock(&dev->struct_mutex);
3501 intel_update_fbc(dev);
3502 mutex_unlock(&dev->struct_mutex);
3503 }
3504
3505 static void ironlake_crtc_off(struct drm_crtc *crtc)
3506 {
3507 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3508 intel_put_pch_pll(intel_crtc);
3509 }
3510
3511 static void haswell_crtc_off(struct drm_crtc *crtc)
3512 {
3513 intel_ddi_put_crtc_pll(crtc);
3514 }
3515
3516 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3517 {
3518 if (!enable && intel_crtc->overlay) {
3519 struct drm_device *dev = intel_crtc->base.dev;
3520 struct drm_i915_private *dev_priv = dev->dev_private;
3521
3522 mutex_lock(&dev->struct_mutex);
3523 dev_priv->mm.interruptible = false;
3524 (void) intel_overlay_switch_off(intel_crtc->overlay);
3525 dev_priv->mm.interruptible = true;
3526 mutex_unlock(&dev->struct_mutex);
3527 }
3528
3529 /* Let userspace switch the overlay on again. In most cases userspace
3530 * has to recompute where to put it anyway.
3531 */
3532 }
3533
3534 /**
3535 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3536 * cursor plane briefly if not already running after enabling the display
3537 * plane.
3538 * This workaround avoids occasional blank screens when self refresh is
3539 * enabled.
3540 */
3541 static void
3542 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3543 {
3544 u32 cntl = I915_READ(CURCNTR(pipe));
3545
3546 if ((cntl & CURSOR_MODE) == 0) {
3547 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3548
3549 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3550 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3551 intel_wait_for_vblank(dev_priv->dev, pipe);
3552 I915_WRITE(CURCNTR(pipe), cntl);
3553 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3554 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3555 }
3556 }
3557
3558 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3559 {
3560 struct drm_device *dev = crtc->base.dev;
3561 struct drm_i915_private *dev_priv = dev->dev_private;
3562 struct intel_crtc_config *pipe_config = &crtc->config;
3563
3564 if (!crtc->config.gmch_pfit.control)
3565 return;
3566
3567 /*
3568 * The panel fitter should only be adjusted whilst the pipe is disabled,
3569 * according to register description and PRM.
3570 */
3571 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3572 assert_pipe_disabled(dev_priv, crtc->pipe);
3573
3574 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3575 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3576
3577 /* Border color in case we don't scale up to the full screen. Black by
3578 * default, change to something else for debugging. */
3579 I915_WRITE(BCLRPAT(crtc->pipe), 0);
3580 }
3581
3582 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3583 {
3584 struct drm_device *dev = crtc->dev;
3585 struct drm_i915_private *dev_priv = dev->dev_private;
3586 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3587 struct intel_encoder *encoder;
3588 int pipe = intel_crtc->pipe;
3589 int plane = intel_crtc->plane;
3590
3591 WARN_ON(!crtc->enabled);
3592
3593 if (intel_crtc->active)
3594 return;
3595
3596 intel_crtc->active = true;
3597 intel_update_watermarks(dev);
3598
3599 mutex_lock(&dev_priv->dpio_lock);
3600
3601 for_each_encoder_on_crtc(dev, crtc, encoder)
3602 if (encoder->pre_pll_enable)
3603 encoder->pre_pll_enable(encoder);
3604
3605 intel_enable_pll(dev_priv, pipe);
3606
3607 for_each_encoder_on_crtc(dev, crtc, encoder)
3608 if (encoder->pre_enable)
3609 encoder->pre_enable(encoder);
3610
3611 /* VLV wants encoder enabling _before_ the pipe is up. */
3612 for_each_encoder_on_crtc(dev, crtc, encoder)
3613 encoder->enable(encoder);
3614
3615 /* Enable panel fitting for eDP */
3616 i9xx_pfit_enable(intel_crtc);
3617
3618 intel_enable_pipe(dev_priv, pipe, false);
3619 intel_enable_plane(dev_priv, plane, pipe);
3620
3621 intel_crtc_load_lut(crtc);
3622 intel_update_fbc(dev);
3623
3624 /* Give the overlay scaler a chance to enable if it's on this pipe */
3625 intel_crtc_dpms_overlay(intel_crtc, true);
3626 intel_crtc_update_cursor(crtc, true);
3627
3628 mutex_unlock(&dev_priv->dpio_lock);
3629 }
3630
3631 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3632 {
3633 struct drm_device *dev = crtc->dev;
3634 struct drm_i915_private *dev_priv = dev->dev_private;
3635 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3636 struct intel_encoder *encoder;
3637 int pipe = intel_crtc->pipe;
3638 int plane = intel_crtc->plane;
3639
3640 WARN_ON(!crtc->enabled);
3641
3642 if (intel_crtc->active)
3643 return;
3644
3645 intel_crtc->active = true;
3646 intel_update_watermarks(dev);
3647
3648 intel_enable_pll(dev_priv, pipe);
3649
3650 for_each_encoder_on_crtc(dev, crtc, encoder)
3651 if (encoder->pre_enable)
3652 encoder->pre_enable(encoder);
3653
3654 /* Enable panel fitting for LVDS */
3655 i9xx_pfit_enable(intel_crtc);
3656
3657 intel_enable_pipe(dev_priv, pipe, false);
3658 intel_enable_plane(dev_priv, plane, pipe);
3659 if (IS_G4X(dev))
3660 g4x_fixup_plane(dev_priv, pipe);
3661
3662 intel_crtc_load_lut(crtc);
3663 intel_update_fbc(dev);
3664
3665 /* Give the overlay scaler a chance to enable if it's on this pipe */
3666 intel_crtc_dpms_overlay(intel_crtc, true);
3667 intel_crtc_update_cursor(crtc, true);
3668
3669 for_each_encoder_on_crtc(dev, crtc, encoder)
3670 encoder->enable(encoder);
3671 }
3672
3673 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3674 {
3675 struct drm_device *dev = crtc->base.dev;
3676 struct drm_i915_private *dev_priv = dev->dev_private;
3677
3678 if (!crtc->config.gmch_pfit.control)
3679 return;
3680
3681 assert_pipe_disabled(dev_priv, crtc->pipe);
3682
3683 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3684 I915_READ(PFIT_CONTROL));
3685 I915_WRITE(PFIT_CONTROL, 0);
3686 }
3687
3688 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3689 {
3690 struct drm_device *dev = crtc->dev;
3691 struct drm_i915_private *dev_priv = dev->dev_private;
3692 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3693 struct intel_encoder *encoder;
3694 int pipe = intel_crtc->pipe;
3695 int plane = intel_crtc->plane;
3696
3697 if (!intel_crtc->active)
3698 return;
3699
3700 for_each_encoder_on_crtc(dev, crtc, encoder)
3701 encoder->disable(encoder);
3702
3703 /* Give the overlay scaler a chance to disable if it's on this pipe */
3704 intel_crtc_wait_for_pending_flips(crtc);
3705 drm_vblank_off(dev, pipe);
3706 intel_crtc_dpms_overlay(intel_crtc, false);
3707 intel_crtc_update_cursor(crtc, false);
3708
3709 if (dev_priv->cfb_plane == plane)
3710 intel_disable_fbc(dev);
3711
3712 intel_disable_plane(dev_priv, plane, pipe);
3713 intel_disable_pipe(dev_priv, pipe);
3714
3715 i9xx_pfit_disable(intel_crtc);
3716
3717 for_each_encoder_on_crtc(dev, crtc, encoder)
3718 if (encoder->post_disable)
3719 encoder->post_disable(encoder);
3720
3721 intel_disable_pll(dev_priv, pipe);
3722
3723 intel_crtc->active = false;
3724 intel_update_fbc(dev);
3725 intel_update_watermarks(dev);
3726 }
3727
3728 static void i9xx_crtc_off(struct drm_crtc *crtc)
3729 {
3730 }
3731
3732 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3733 bool enabled)
3734 {
3735 struct drm_device *dev = crtc->dev;
3736 struct drm_i915_master_private *master_priv;
3737 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3738 int pipe = intel_crtc->pipe;
3739
3740 if (!dev->primary->master)
3741 return;
3742
3743 master_priv = dev->primary->master->driver_priv;
3744 if (!master_priv->sarea_priv)
3745 return;
3746
3747 switch (pipe) {
3748 case 0:
3749 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3750 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3751 break;
3752 case 1:
3753 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3754 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3755 break;
3756 default:
3757 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3758 break;
3759 }
3760 }
3761
3762 /**
3763 * Sets the power management mode of the pipe and plane.
3764 */
3765 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3766 {
3767 struct drm_device *dev = crtc->dev;
3768 struct drm_i915_private *dev_priv = dev->dev_private;
3769 struct intel_encoder *intel_encoder;
3770 bool enable = false;
3771
3772 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3773 enable |= intel_encoder->connectors_active;
3774
3775 if (enable)
3776 dev_priv->display.crtc_enable(crtc);
3777 else
3778 dev_priv->display.crtc_disable(crtc);
3779
3780 intel_crtc_update_sarea(crtc, enable);
3781 }
3782
3783 static void intel_crtc_disable(struct drm_crtc *crtc)
3784 {
3785 struct drm_device *dev = crtc->dev;
3786 struct drm_connector *connector;
3787 struct drm_i915_private *dev_priv = dev->dev_private;
3788 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3789
3790 /* crtc should still be enabled when we disable it. */
3791 WARN_ON(!crtc->enabled);
3792
3793 dev_priv->display.crtc_disable(crtc);
3794 intel_crtc->eld_vld = false;
3795 intel_crtc_update_sarea(crtc, false);
3796 dev_priv->display.off(crtc);
3797
3798 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3799 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3800
3801 if (crtc->fb) {
3802 mutex_lock(&dev->struct_mutex);
3803 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3804 mutex_unlock(&dev->struct_mutex);
3805 crtc->fb = NULL;
3806 }
3807
3808 /* Update computed state. */
3809 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3810 if (!connector->encoder || !connector->encoder->crtc)
3811 continue;
3812
3813 if (connector->encoder->crtc != crtc)
3814 continue;
3815
3816 connector->dpms = DRM_MODE_DPMS_OFF;
3817 to_intel_encoder(connector->encoder)->connectors_active = false;
3818 }
3819 }
3820
3821 void intel_modeset_disable(struct drm_device *dev)
3822 {
3823 struct drm_crtc *crtc;
3824
3825 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3826 if (crtc->enabled)
3827 intel_crtc_disable(crtc);
3828 }
3829 }
3830
3831 void intel_encoder_destroy(struct drm_encoder *encoder)
3832 {
3833 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3834
3835 drm_encoder_cleanup(encoder);
3836 kfree(intel_encoder);
3837 }
3838
3839 /* Simple dpms helper for encodres with just one connector, no cloning and only
3840 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3841 * state of the entire output pipe. */
3842 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3843 {
3844 if (mode == DRM_MODE_DPMS_ON) {
3845 encoder->connectors_active = true;
3846
3847 intel_crtc_update_dpms(encoder->base.crtc);
3848 } else {
3849 encoder->connectors_active = false;
3850
3851 intel_crtc_update_dpms(encoder->base.crtc);
3852 }
3853 }
3854
3855 /* Cross check the actual hw state with our own modeset state tracking (and it's
3856 * internal consistency). */
3857 static void intel_connector_check_state(struct intel_connector *connector)
3858 {
3859 if (connector->get_hw_state(connector)) {
3860 struct intel_encoder *encoder = connector->encoder;
3861 struct drm_crtc *crtc;
3862 bool encoder_enabled;
3863 enum pipe pipe;
3864
3865 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3866 connector->base.base.id,
3867 drm_get_connector_name(&connector->base));
3868
3869 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3870 "wrong connector dpms state\n");
3871 WARN(connector->base.encoder != &encoder->base,
3872 "active connector not linked to encoder\n");
3873 WARN(!encoder->connectors_active,
3874 "encoder->connectors_active not set\n");
3875
3876 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3877 WARN(!encoder_enabled, "encoder not enabled\n");
3878 if (WARN_ON(!encoder->base.crtc))
3879 return;
3880
3881 crtc = encoder->base.crtc;
3882
3883 WARN(!crtc->enabled, "crtc not enabled\n");
3884 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3885 WARN(pipe != to_intel_crtc(crtc)->pipe,
3886 "encoder active on the wrong pipe\n");
3887 }
3888 }
3889
3890 /* Even simpler default implementation, if there's really no special case to
3891 * consider. */
3892 void intel_connector_dpms(struct drm_connector *connector, int mode)
3893 {
3894 struct intel_encoder *encoder = intel_attached_encoder(connector);
3895
3896 /* All the simple cases only support two dpms states. */
3897 if (mode != DRM_MODE_DPMS_ON)
3898 mode = DRM_MODE_DPMS_OFF;
3899
3900 if (mode == connector->dpms)
3901 return;
3902
3903 connector->dpms = mode;
3904
3905 /* Only need to change hw state when actually enabled */
3906 if (encoder->base.crtc)
3907 intel_encoder_dpms(encoder, mode);
3908 else
3909 WARN_ON(encoder->connectors_active != false);
3910
3911 intel_modeset_check_state(connector->dev);
3912 }
3913
3914 /* Simple connector->get_hw_state implementation for encoders that support only
3915 * one connector and no cloning and hence the encoder state determines the state
3916 * of the connector. */
3917 bool intel_connector_get_hw_state(struct intel_connector *connector)
3918 {
3919 enum pipe pipe = 0;
3920 struct intel_encoder *encoder = connector->encoder;
3921
3922 return encoder->get_hw_state(encoder, &pipe);
3923 }
3924
3925 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3926 struct intel_crtc_config *pipe_config)
3927 {
3928 struct drm_i915_private *dev_priv = dev->dev_private;
3929 struct intel_crtc *pipe_B_crtc =
3930 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3931
3932 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3933 pipe_name(pipe), pipe_config->fdi_lanes);
3934 if (pipe_config->fdi_lanes > 4) {
3935 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3936 pipe_name(pipe), pipe_config->fdi_lanes);
3937 return false;
3938 }
3939
3940 if (IS_HASWELL(dev)) {
3941 if (pipe_config->fdi_lanes > 2) {
3942 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3943 pipe_config->fdi_lanes);
3944 return false;
3945 } else {
3946 return true;
3947 }
3948 }
3949
3950 if (INTEL_INFO(dev)->num_pipes == 2)
3951 return true;
3952
3953 /* Ivybridge 3 pipe is really complicated */
3954 switch (pipe) {
3955 case PIPE_A:
3956 return true;
3957 case PIPE_B:
3958 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
3959 pipe_config->fdi_lanes > 2) {
3960 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3961 pipe_name(pipe), pipe_config->fdi_lanes);
3962 return false;
3963 }
3964 return true;
3965 case PIPE_C:
3966 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
3967 pipe_B_crtc->config.fdi_lanes <= 2) {
3968 if (pipe_config->fdi_lanes > 2) {
3969 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3970 pipe_name(pipe), pipe_config->fdi_lanes);
3971 return false;
3972 }
3973 } else {
3974 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
3975 return false;
3976 }
3977 return true;
3978 default:
3979 BUG();
3980 }
3981 }
3982
3983 #define RETRY 1
3984 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
3985 struct intel_crtc_config *pipe_config)
3986 {
3987 struct drm_device *dev = intel_crtc->base.dev;
3988 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
3989 int target_clock, lane, link_bw;
3990 bool setup_ok, needs_recompute = false;
3991
3992 retry:
3993 /* FDI is a binary signal running at ~2.7GHz, encoding
3994 * each output octet as 10 bits. The actual frequency
3995 * is stored as a divider into a 100MHz clock, and the
3996 * mode pixel clock is stored in units of 1KHz.
3997 * Hence the bw of each lane in terms of the mode signal
3998 * is:
3999 */
4000 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4001
4002 if (pipe_config->pixel_target_clock)
4003 target_clock = pipe_config->pixel_target_clock;
4004 else
4005 target_clock = adjusted_mode->clock;
4006
4007 lane = ironlake_get_lanes_required(target_clock, link_bw,
4008 pipe_config->pipe_bpp);
4009
4010 pipe_config->fdi_lanes = lane;
4011
4012 if (pipe_config->pixel_multiplier > 1)
4013 link_bw *= pipe_config->pixel_multiplier;
4014 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, target_clock,
4015 link_bw, &pipe_config->fdi_m_n);
4016
4017 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4018 intel_crtc->pipe, pipe_config);
4019 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4020 pipe_config->pipe_bpp -= 2*3;
4021 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4022 pipe_config->pipe_bpp);
4023 needs_recompute = true;
4024 pipe_config->bw_constrained = true;
4025
4026 goto retry;
4027 }
4028
4029 if (needs_recompute)
4030 return RETRY;
4031
4032 return setup_ok ? 0 : -EINVAL;
4033 }
4034
4035 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4036 struct intel_crtc_config *pipe_config)
4037 {
4038 pipe_config->ips_enabled = i915_enable_ips &&
4039 hsw_crtc_supports_ips(crtc) &&
4040 pipe_config->pipe_bpp == 24;
4041 }
4042
4043 static int intel_crtc_compute_config(struct drm_crtc *crtc,
4044 struct intel_crtc_config *pipe_config)
4045 {
4046 struct drm_device *dev = crtc->dev;
4047 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4048 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4049
4050 if (HAS_PCH_SPLIT(dev)) {
4051 /* FDI link clock is fixed at 2.7G */
4052 if (pipe_config->requested_mode.clock * 3
4053 > IRONLAKE_FDI_FREQ * 4)
4054 return -EINVAL;
4055 }
4056
4057 /* All interlaced capable intel hw wants timings in frames. Note though
4058 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4059 * timings, so we need to be careful not to clobber these.*/
4060 if (!pipe_config->timings_set)
4061 drm_mode_set_crtcinfo(adjusted_mode, 0);
4062
4063 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4064 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4065 */
4066 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4067 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4068 return -EINVAL;
4069
4070 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4071 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4072 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4073 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4074 * for lvds. */
4075 pipe_config->pipe_bpp = 8*3;
4076 }
4077
4078 if (IS_HASWELL(dev))
4079 hsw_compute_ips_config(intel_crtc, pipe_config);
4080
4081 if (pipe_config->has_pch_encoder)
4082 return ironlake_fdi_compute_config(intel_crtc, pipe_config);
4083
4084 return 0;
4085 }
4086
4087 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4088 {
4089 return 400000; /* FIXME */
4090 }
4091
4092 static int i945_get_display_clock_speed(struct drm_device *dev)
4093 {
4094 return 400000;
4095 }
4096
4097 static int i915_get_display_clock_speed(struct drm_device *dev)
4098 {
4099 return 333000;
4100 }
4101
4102 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4103 {
4104 return 200000;
4105 }
4106
4107 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4108 {
4109 u16 gcfgc = 0;
4110
4111 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4112
4113 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4114 return 133000;
4115 else {
4116 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4117 case GC_DISPLAY_CLOCK_333_MHZ:
4118 return 333000;
4119 default:
4120 case GC_DISPLAY_CLOCK_190_200_MHZ:
4121 return 190000;
4122 }
4123 }
4124 }
4125
4126 static int i865_get_display_clock_speed(struct drm_device *dev)
4127 {
4128 return 266000;
4129 }
4130
4131 static int i855_get_display_clock_speed(struct drm_device *dev)
4132 {
4133 u16 hpllcc = 0;
4134 /* Assume that the hardware is in the high speed state. This
4135 * should be the default.
4136 */
4137 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4138 case GC_CLOCK_133_200:
4139 case GC_CLOCK_100_200:
4140 return 200000;
4141 case GC_CLOCK_166_250:
4142 return 250000;
4143 case GC_CLOCK_100_133:
4144 return 133000;
4145 }
4146
4147 /* Shouldn't happen */
4148 return 0;
4149 }
4150
4151 static int i830_get_display_clock_speed(struct drm_device *dev)
4152 {
4153 return 133000;
4154 }
4155
4156 static void
4157 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4158 {
4159 while (*num > DATA_LINK_M_N_MASK ||
4160 *den > DATA_LINK_M_N_MASK) {
4161 *num >>= 1;
4162 *den >>= 1;
4163 }
4164 }
4165
4166 static void compute_m_n(unsigned int m, unsigned int n,
4167 uint32_t *ret_m, uint32_t *ret_n)
4168 {
4169 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4170 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4171 intel_reduce_m_n_ratio(ret_m, ret_n);
4172 }
4173
4174 void
4175 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4176 int pixel_clock, int link_clock,
4177 struct intel_link_m_n *m_n)
4178 {
4179 m_n->tu = 64;
4180
4181 compute_m_n(bits_per_pixel * pixel_clock,
4182 link_clock * nlanes * 8,
4183 &m_n->gmch_m, &m_n->gmch_n);
4184
4185 compute_m_n(pixel_clock, link_clock,
4186 &m_n->link_m, &m_n->link_n);
4187 }
4188
4189 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4190 {
4191 if (i915_panel_use_ssc >= 0)
4192 return i915_panel_use_ssc != 0;
4193 return dev_priv->vbt.lvds_use_ssc
4194 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4195 }
4196
4197 static int vlv_get_refclk(struct drm_crtc *crtc)
4198 {
4199 struct drm_device *dev = crtc->dev;
4200 struct drm_i915_private *dev_priv = dev->dev_private;
4201 int refclk = 27000; /* for DP & HDMI */
4202
4203 return 100000; /* only one validated so far */
4204
4205 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4206 refclk = 96000;
4207 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4208 if (intel_panel_use_ssc(dev_priv))
4209 refclk = 100000;
4210 else
4211 refclk = 96000;
4212 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4213 refclk = 100000;
4214 }
4215
4216 return refclk;
4217 }
4218
4219 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4220 {
4221 struct drm_device *dev = crtc->dev;
4222 struct drm_i915_private *dev_priv = dev->dev_private;
4223 int refclk;
4224
4225 if (IS_VALLEYVIEW(dev)) {
4226 refclk = vlv_get_refclk(crtc);
4227 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4228 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4229 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4230 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4231 refclk / 1000);
4232 } else if (!IS_GEN2(dev)) {
4233 refclk = 96000;
4234 } else {
4235 refclk = 48000;
4236 }
4237
4238 return refclk;
4239 }
4240
4241 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4242 {
4243 return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2;
4244 }
4245
4246 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4247 {
4248 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4249 }
4250
4251 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4252 intel_clock_t *reduced_clock)
4253 {
4254 struct drm_device *dev = crtc->base.dev;
4255 struct drm_i915_private *dev_priv = dev->dev_private;
4256 int pipe = crtc->pipe;
4257 u32 fp, fp2 = 0;
4258
4259 if (IS_PINEVIEW(dev)) {
4260 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4261 if (reduced_clock)
4262 fp2 = pnv_dpll_compute_fp(reduced_clock);
4263 } else {
4264 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4265 if (reduced_clock)
4266 fp2 = i9xx_dpll_compute_fp(reduced_clock);
4267 }
4268
4269 I915_WRITE(FP0(pipe), fp);
4270
4271 crtc->lowfreq_avail = false;
4272 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4273 reduced_clock && i915_powersave) {
4274 I915_WRITE(FP1(pipe), fp2);
4275 crtc->lowfreq_avail = true;
4276 } else {
4277 I915_WRITE(FP1(pipe), fp);
4278 }
4279 }
4280
4281 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4282 {
4283 u32 reg_val;
4284
4285 /*
4286 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4287 * and set it to a reasonable value instead.
4288 */
4289 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4290 reg_val &= 0xffffff00;
4291 reg_val |= 0x00000030;
4292 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4293
4294 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4295 reg_val &= 0x8cffffff;
4296 reg_val = 0x8c000000;
4297 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4298
4299 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4300 reg_val &= 0xffffff00;
4301 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4302
4303 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4304 reg_val &= 0x00ffffff;
4305 reg_val |= 0xb0000000;
4306 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4307 }
4308
4309 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4310 struct intel_link_m_n *m_n)
4311 {
4312 struct drm_device *dev = crtc->base.dev;
4313 struct drm_i915_private *dev_priv = dev->dev_private;
4314 int pipe = crtc->pipe;
4315
4316 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4317 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4318 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4319 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4320 }
4321
4322 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4323 struct intel_link_m_n *m_n)
4324 {
4325 struct drm_device *dev = crtc->base.dev;
4326 struct drm_i915_private *dev_priv = dev->dev_private;
4327 int pipe = crtc->pipe;
4328 enum transcoder transcoder = crtc->config.cpu_transcoder;
4329
4330 if (INTEL_INFO(dev)->gen >= 5) {
4331 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4332 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4333 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4334 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4335 } else {
4336 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4337 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4338 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4339 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4340 }
4341 }
4342
4343 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4344 {
4345 if (crtc->config.has_pch_encoder)
4346 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4347 else
4348 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4349 }
4350
4351 static void vlv_update_pll(struct intel_crtc *crtc)
4352 {
4353 struct drm_device *dev = crtc->base.dev;
4354 struct drm_i915_private *dev_priv = dev->dev_private;
4355 struct drm_display_mode *adjusted_mode =
4356 &crtc->config.adjusted_mode;
4357 struct intel_encoder *encoder;
4358 int pipe = crtc->pipe;
4359 u32 dpll, mdiv;
4360 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4361 bool is_hdmi;
4362 u32 coreclk, reg_val, dpll_md;
4363
4364 mutex_lock(&dev_priv->dpio_lock);
4365
4366 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4367
4368 bestn = crtc->config.dpll.n;
4369 bestm1 = crtc->config.dpll.m1;
4370 bestm2 = crtc->config.dpll.m2;
4371 bestp1 = crtc->config.dpll.p1;
4372 bestp2 = crtc->config.dpll.p2;
4373
4374 /* See eDP HDMI DPIO driver vbios notes doc */
4375
4376 /* PLL B needs special handling */
4377 if (pipe)
4378 vlv_pllb_recal_opamp(dev_priv);
4379
4380 /* Set up Tx target for periodic Rcomp update */
4381 vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4382
4383 /* Disable target IRef on PLL */
4384 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4385 reg_val &= 0x00ffffff;
4386 vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4387
4388 /* Disable fast lock */
4389 vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4390
4391 /* Set idtafcrecal before PLL is enabled */
4392 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4393 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4394 mdiv |= ((bestn << DPIO_N_SHIFT));
4395 mdiv |= (1 << DPIO_K_SHIFT);
4396
4397 /*
4398 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4399 * but we don't support that).
4400 * Note: don't use the DAC post divider as it seems unstable.
4401 */
4402 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4403 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4404
4405 mdiv |= DPIO_ENABLE_CALIBRATION;
4406 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4407
4408 /* Set HBR and RBR LPF coefficients */
4409 if (adjusted_mode->clock == 162000 ||
4410 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4411 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4412 0x005f0021);
4413 else
4414 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4415 0x00d0000f);
4416
4417 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4418 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4419 /* Use SSC source */
4420 if (!pipe)
4421 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4422 0x0df40000);
4423 else
4424 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4425 0x0df70000);
4426 } else { /* HDMI or VGA */
4427 /* Use bend source */
4428 if (!pipe)
4429 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4430 0x0df70000);
4431 else
4432 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4433 0x0df40000);
4434 }
4435
4436 coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4437 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4438 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4439 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4440 coreclk |= 0x01000000;
4441 vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4442
4443 vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4444
4445 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4446 if (encoder->pre_pll_enable)
4447 encoder->pre_pll_enable(encoder);
4448
4449 /* Enable DPIO clock input */
4450 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4451 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4452 if (pipe)
4453 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4454
4455 dpll |= DPLL_VCO_ENABLE;
4456 I915_WRITE(DPLL(pipe), dpll);
4457 POSTING_READ(DPLL(pipe));
4458 udelay(150);
4459
4460 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4461 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4462
4463 dpll_md = 0;
4464 if (crtc->config.pixel_multiplier > 1) {
4465 dpll_md = (crtc->config.pixel_multiplier - 1)
4466 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4467 }
4468 I915_WRITE(DPLL_MD(pipe), dpll_md);
4469 POSTING_READ(DPLL_MD(pipe));
4470
4471 if (crtc->config.has_dp_encoder)
4472 intel_dp_set_m_n(crtc);
4473
4474 mutex_unlock(&dev_priv->dpio_lock);
4475 }
4476
4477 static void i9xx_update_pll(struct intel_crtc *crtc,
4478 intel_clock_t *reduced_clock,
4479 int num_connectors)
4480 {
4481 struct drm_device *dev = crtc->base.dev;
4482 struct drm_i915_private *dev_priv = dev->dev_private;
4483 struct intel_encoder *encoder;
4484 int pipe = crtc->pipe;
4485 u32 dpll;
4486 bool is_sdvo;
4487 struct dpll *clock = &crtc->config.dpll;
4488
4489 i9xx_update_pll_dividers(crtc, reduced_clock);
4490
4491 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4492 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4493
4494 dpll = DPLL_VGA_MODE_DIS;
4495
4496 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4497 dpll |= DPLLB_MODE_LVDS;
4498 else
4499 dpll |= DPLLB_MODE_DAC_SERIAL;
4500
4501 if ((crtc->config.pixel_multiplier > 1) &&
4502 (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
4503 dpll |= (crtc->config.pixel_multiplier - 1)
4504 << SDVO_MULTIPLIER_SHIFT_HIRES;
4505 }
4506
4507 if (is_sdvo)
4508 dpll |= DPLL_DVO_HIGH_SPEED;
4509
4510 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4511 dpll |= DPLL_DVO_HIGH_SPEED;
4512
4513 /* compute bitmask from p1 value */
4514 if (IS_PINEVIEW(dev))
4515 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4516 else {
4517 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4518 if (IS_G4X(dev) && reduced_clock)
4519 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4520 }
4521 switch (clock->p2) {
4522 case 5:
4523 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4524 break;
4525 case 7:
4526 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4527 break;
4528 case 10:
4529 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4530 break;
4531 case 14:
4532 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4533 break;
4534 }
4535 if (INTEL_INFO(dev)->gen >= 4)
4536 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4537
4538 if (crtc->config.sdvo_tv_clock)
4539 dpll |= PLL_REF_INPUT_TVCLKINBC;
4540 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4541 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4542 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4543 else
4544 dpll |= PLL_REF_INPUT_DREFCLK;
4545
4546 dpll |= DPLL_VCO_ENABLE;
4547 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4548 POSTING_READ(DPLL(pipe));
4549 udelay(150);
4550
4551 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4552 if (encoder->pre_pll_enable)
4553 encoder->pre_pll_enable(encoder);
4554
4555 if (crtc->config.has_dp_encoder)
4556 intel_dp_set_m_n(crtc);
4557
4558 I915_WRITE(DPLL(pipe), dpll);
4559
4560 /* Wait for the clocks to stabilize. */
4561 POSTING_READ(DPLL(pipe));
4562 udelay(150);
4563
4564 if (INTEL_INFO(dev)->gen >= 4) {
4565 u32 dpll_md = 0;
4566 if (crtc->config.pixel_multiplier > 1) {
4567 dpll_md = (crtc->config.pixel_multiplier - 1)
4568 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4569 }
4570 I915_WRITE(DPLL_MD(pipe), dpll_md);
4571 } else {
4572 /* The pixel multiplier can only be updated once the
4573 * DPLL is enabled and the clocks are stable.
4574 *
4575 * So write it again.
4576 */
4577 I915_WRITE(DPLL(pipe), dpll);
4578 }
4579 }
4580
4581 static void i8xx_update_pll(struct intel_crtc *crtc,
4582 struct drm_display_mode *adjusted_mode,
4583 intel_clock_t *reduced_clock,
4584 int num_connectors)
4585 {
4586 struct drm_device *dev = crtc->base.dev;
4587 struct drm_i915_private *dev_priv = dev->dev_private;
4588 struct intel_encoder *encoder;
4589 int pipe = crtc->pipe;
4590 u32 dpll;
4591 struct dpll *clock = &crtc->config.dpll;
4592
4593 i9xx_update_pll_dividers(crtc, reduced_clock);
4594
4595 dpll = DPLL_VGA_MODE_DIS;
4596
4597 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4598 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4599 } else {
4600 if (clock->p1 == 2)
4601 dpll |= PLL_P1_DIVIDE_BY_TWO;
4602 else
4603 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4604 if (clock->p2 == 4)
4605 dpll |= PLL_P2_DIVIDE_BY_4;
4606 }
4607
4608 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4609 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4610 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4611 else
4612 dpll |= PLL_REF_INPUT_DREFCLK;
4613
4614 dpll |= DPLL_VCO_ENABLE;
4615 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4616 POSTING_READ(DPLL(pipe));
4617 udelay(150);
4618
4619 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4620 if (encoder->pre_pll_enable)
4621 encoder->pre_pll_enable(encoder);
4622
4623 I915_WRITE(DPLL(pipe), dpll);
4624
4625 /* Wait for the clocks to stabilize. */
4626 POSTING_READ(DPLL(pipe));
4627 udelay(150);
4628
4629 /* The pixel multiplier can only be updated once the
4630 * DPLL is enabled and the clocks are stable.
4631 *
4632 * So write it again.
4633 */
4634 I915_WRITE(DPLL(pipe), dpll);
4635 }
4636
4637 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4638 struct drm_display_mode *mode,
4639 struct drm_display_mode *adjusted_mode)
4640 {
4641 struct drm_device *dev = intel_crtc->base.dev;
4642 struct drm_i915_private *dev_priv = dev->dev_private;
4643 enum pipe pipe = intel_crtc->pipe;
4644 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4645 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4646
4647 /* We need to be careful not to changed the adjusted mode, for otherwise
4648 * the hw state checker will get angry at the mismatch. */
4649 crtc_vtotal = adjusted_mode->crtc_vtotal;
4650 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4651
4652 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4653 /* the chip adds 2 halflines automatically */
4654 crtc_vtotal -= 1;
4655 crtc_vblank_end -= 1;
4656 vsyncshift = adjusted_mode->crtc_hsync_start
4657 - adjusted_mode->crtc_htotal / 2;
4658 } else {
4659 vsyncshift = 0;
4660 }
4661
4662 if (INTEL_INFO(dev)->gen > 3)
4663 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4664
4665 I915_WRITE(HTOTAL(cpu_transcoder),
4666 (adjusted_mode->crtc_hdisplay - 1) |
4667 ((adjusted_mode->crtc_htotal - 1) << 16));
4668 I915_WRITE(HBLANK(cpu_transcoder),
4669 (adjusted_mode->crtc_hblank_start - 1) |
4670 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4671 I915_WRITE(HSYNC(cpu_transcoder),
4672 (adjusted_mode->crtc_hsync_start - 1) |
4673 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4674
4675 I915_WRITE(VTOTAL(cpu_transcoder),
4676 (adjusted_mode->crtc_vdisplay - 1) |
4677 ((crtc_vtotal - 1) << 16));
4678 I915_WRITE(VBLANK(cpu_transcoder),
4679 (adjusted_mode->crtc_vblank_start - 1) |
4680 ((crtc_vblank_end - 1) << 16));
4681 I915_WRITE(VSYNC(cpu_transcoder),
4682 (adjusted_mode->crtc_vsync_start - 1) |
4683 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4684
4685 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4686 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4687 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4688 * bits. */
4689 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4690 (pipe == PIPE_B || pipe == PIPE_C))
4691 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4692
4693 /* pipesrc controls the size that is scaled from, which should
4694 * always be the user's requested size.
4695 */
4696 I915_WRITE(PIPESRC(pipe),
4697 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4698 }
4699
4700 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4701 struct intel_crtc_config *pipe_config)
4702 {
4703 struct drm_device *dev = crtc->base.dev;
4704 struct drm_i915_private *dev_priv = dev->dev_private;
4705 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4706 uint32_t tmp;
4707
4708 tmp = I915_READ(HTOTAL(cpu_transcoder));
4709 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4710 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4711 tmp = I915_READ(HBLANK(cpu_transcoder));
4712 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4713 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4714 tmp = I915_READ(HSYNC(cpu_transcoder));
4715 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4716 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4717
4718 tmp = I915_READ(VTOTAL(cpu_transcoder));
4719 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4720 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4721 tmp = I915_READ(VBLANK(cpu_transcoder));
4722 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4723 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4724 tmp = I915_READ(VSYNC(cpu_transcoder));
4725 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4726 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4727
4728 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4729 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4730 pipe_config->adjusted_mode.crtc_vtotal += 1;
4731 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4732 }
4733
4734 tmp = I915_READ(PIPESRC(crtc->pipe));
4735 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4736 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4737 }
4738
4739 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4740 {
4741 struct drm_device *dev = intel_crtc->base.dev;
4742 struct drm_i915_private *dev_priv = dev->dev_private;
4743 uint32_t pipeconf;
4744
4745 pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4746
4747 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4748 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4749 * core speed.
4750 *
4751 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4752 * pipe == 0 check?
4753 */
4754 if (intel_crtc->config.requested_mode.clock >
4755 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4756 pipeconf |= PIPECONF_DOUBLE_WIDE;
4757 else
4758 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4759 }
4760
4761 /* only g4x and later have fancy bpc/dither controls */
4762 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4763 pipeconf &= ~(PIPECONF_BPC_MASK |
4764 PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4765
4766 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4767 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4768 pipeconf |= PIPECONF_DITHER_EN |
4769 PIPECONF_DITHER_TYPE_SP;
4770
4771 switch (intel_crtc->config.pipe_bpp) {
4772 case 18:
4773 pipeconf |= PIPECONF_6BPC;
4774 break;
4775 case 24:
4776 pipeconf |= PIPECONF_8BPC;
4777 break;
4778 case 30:
4779 pipeconf |= PIPECONF_10BPC;
4780 break;
4781 default:
4782 /* Case prevented by intel_choose_pipe_bpp_dither. */
4783 BUG();
4784 }
4785 }
4786
4787 if (HAS_PIPE_CXSR(dev)) {
4788 if (intel_crtc->lowfreq_avail) {
4789 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4790 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4791 } else {
4792 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4793 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4794 }
4795 }
4796
4797 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4798 if (!IS_GEN2(dev) &&
4799 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4800 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4801 else
4802 pipeconf |= PIPECONF_PROGRESSIVE;
4803
4804 if (IS_VALLEYVIEW(dev)) {
4805 if (intel_crtc->config.limited_color_range)
4806 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4807 else
4808 pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4809 }
4810
4811 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4812 POSTING_READ(PIPECONF(intel_crtc->pipe));
4813 }
4814
4815 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4816 int x, int y,
4817 struct drm_framebuffer *fb)
4818 {
4819 struct drm_device *dev = crtc->dev;
4820 struct drm_i915_private *dev_priv = dev->dev_private;
4821 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4822 struct drm_display_mode *adjusted_mode =
4823 &intel_crtc->config.adjusted_mode;
4824 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4825 int pipe = intel_crtc->pipe;
4826 int plane = intel_crtc->plane;
4827 int refclk, num_connectors = 0;
4828 intel_clock_t clock, reduced_clock;
4829 u32 dspcntr;
4830 bool ok, has_reduced_clock = false;
4831 bool is_lvds = false;
4832 struct intel_encoder *encoder;
4833 const intel_limit_t *limit;
4834 int ret;
4835
4836 for_each_encoder_on_crtc(dev, crtc, encoder) {
4837 switch (encoder->type) {
4838 case INTEL_OUTPUT_LVDS:
4839 is_lvds = true;
4840 break;
4841 }
4842
4843 num_connectors++;
4844 }
4845
4846 refclk = i9xx_get_refclk(crtc, num_connectors);
4847
4848 /*
4849 * Returns a set of divisors for the desired target clock with the given
4850 * refclk, or FALSE. The returned values represent the clock equation:
4851 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4852 */
4853 limit = intel_limit(crtc, refclk);
4854 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4855 &clock);
4856 if (!ok) {
4857 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4858 return -EINVAL;
4859 }
4860
4861 /* Ensure that the cursor is valid for the new mode before changing... */
4862 intel_crtc_update_cursor(crtc, true);
4863
4864 if (is_lvds && dev_priv->lvds_downclock_avail) {
4865 /*
4866 * Ensure we match the reduced clock's P to the target clock.
4867 * If the clocks don't match, we can't switch the display clock
4868 * by using the FP0/FP1. In such case we will disable the LVDS
4869 * downclock feature.
4870 */
4871 has_reduced_clock = limit->find_pll(limit, crtc,
4872 dev_priv->lvds_downclock,
4873 refclk,
4874 &clock,
4875 &reduced_clock);
4876 }
4877 /* Compat-code for transition, will disappear. */
4878 if (!intel_crtc->config.clock_set) {
4879 intel_crtc->config.dpll.n = clock.n;
4880 intel_crtc->config.dpll.m1 = clock.m1;
4881 intel_crtc->config.dpll.m2 = clock.m2;
4882 intel_crtc->config.dpll.p1 = clock.p1;
4883 intel_crtc->config.dpll.p2 = clock.p2;
4884 }
4885
4886 if (IS_GEN2(dev))
4887 i8xx_update_pll(intel_crtc, adjusted_mode,
4888 has_reduced_clock ? &reduced_clock : NULL,
4889 num_connectors);
4890 else if (IS_VALLEYVIEW(dev))
4891 vlv_update_pll(intel_crtc);
4892 else
4893 i9xx_update_pll(intel_crtc,
4894 has_reduced_clock ? &reduced_clock : NULL,
4895 num_connectors);
4896
4897 /* Set up the display plane register */
4898 dspcntr = DISPPLANE_GAMMA_ENABLE;
4899
4900 if (!IS_VALLEYVIEW(dev)) {
4901 if (pipe == 0)
4902 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4903 else
4904 dspcntr |= DISPPLANE_SEL_PIPE_B;
4905 }
4906
4907 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4908
4909 /* pipesrc and dspsize control the size that is scaled from,
4910 * which should always be the user's requested size.
4911 */
4912 I915_WRITE(DSPSIZE(plane),
4913 ((mode->vdisplay - 1) << 16) |
4914 (mode->hdisplay - 1));
4915 I915_WRITE(DSPPOS(plane), 0);
4916
4917 i9xx_set_pipeconf(intel_crtc);
4918
4919 I915_WRITE(DSPCNTR(plane), dspcntr);
4920 POSTING_READ(DSPCNTR(plane));
4921
4922 ret = intel_pipe_set_base(crtc, x, y, fb);
4923
4924 intel_update_watermarks(dev);
4925
4926 return ret;
4927 }
4928
4929 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4930 struct intel_crtc_config *pipe_config)
4931 {
4932 struct drm_device *dev = crtc->base.dev;
4933 struct drm_i915_private *dev_priv = dev->dev_private;
4934 uint32_t tmp;
4935
4936 tmp = I915_READ(PFIT_CONTROL);
4937
4938 if (INTEL_INFO(dev)->gen < 4) {
4939 if (crtc->pipe != PIPE_B)
4940 return;
4941
4942 /* gen2/3 store dither state in pfit control, needs to match */
4943 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
4944 } else {
4945 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4946 return;
4947 }
4948
4949 if (!(tmp & PFIT_ENABLE))
4950 return;
4951
4952 pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
4953 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4954 if (INTEL_INFO(dev)->gen < 5)
4955 pipe_config->gmch_pfit.lvds_border_bits =
4956 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4957 }
4958
4959 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4960 struct intel_crtc_config *pipe_config)
4961 {
4962 struct drm_device *dev = crtc->base.dev;
4963 struct drm_i915_private *dev_priv = dev->dev_private;
4964 uint32_t tmp;
4965
4966 pipe_config->cpu_transcoder = crtc->pipe;
4967
4968 tmp = I915_READ(PIPECONF(crtc->pipe));
4969 if (!(tmp & PIPECONF_ENABLE))
4970 return false;
4971
4972 intel_get_pipe_timings(crtc, pipe_config);
4973
4974 i9xx_get_pfit_config(crtc, pipe_config);
4975
4976 return true;
4977 }
4978
4979 static void ironlake_init_pch_refclk(struct drm_device *dev)
4980 {
4981 struct drm_i915_private *dev_priv = dev->dev_private;
4982 struct drm_mode_config *mode_config = &dev->mode_config;
4983 struct intel_encoder *encoder;
4984 u32 val, final;
4985 bool has_lvds = false;
4986 bool has_cpu_edp = false;
4987 bool has_panel = false;
4988 bool has_ck505 = false;
4989 bool can_ssc = false;
4990
4991 /* We need to take the global config into account */
4992 list_for_each_entry(encoder, &mode_config->encoder_list,
4993 base.head) {
4994 switch (encoder->type) {
4995 case INTEL_OUTPUT_LVDS:
4996 has_panel = true;
4997 has_lvds = true;
4998 break;
4999 case INTEL_OUTPUT_EDP:
5000 has_panel = true;
5001 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5002 has_cpu_edp = true;
5003 break;
5004 }
5005 }
5006
5007 if (HAS_PCH_IBX(dev)) {
5008 has_ck505 = dev_priv->vbt.display_clock_mode;
5009 can_ssc = has_ck505;
5010 } else {
5011 has_ck505 = false;
5012 can_ssc = true;
5013 }
5014
5015 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5016 has_panel, has_lvds, has_ck505);
5017
5018 /* Ironlake: try to setup display ref clock before DPLL
5019 * enabling. This is only under driver's control after
5020 * PCH B stepping, previous chipset stepping should be
5021 * ignoring this setting.
5022 */
5023 val = I915_READ(PCH_DREF_CONTROL);
5024
5025 /* As we must carefully and slowly disable/enable each source in turn,
5026 * compute the final state we want first and check if we need to
5027 * make any changes at all.
5028 */
5029 final = val;
5030 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5031 if (has_ck505)
5032 final |= DREF_NONSPREAD_CK505_ENABLE;
5033 else
5034 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5035
5036 final &= ~DREF_SSC_SOURCE_MASK;
5037 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5038 final &= ~DREF_SSC1_ENABLE;
5039
5040 if (has_panel) {
5041 final |= DREF_SSC_SOURCE_ENABLE;
5042
5043 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5044 final |= DREF_SSC1_ENABLE;
5045
5046 if (has_cpu_edp) {
5047 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5048 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5049 else
5050 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5051 } else
5052 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5053 } else {
5054 final |= DREF_SSC_SOURCE_DISABLE;
5055 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5056 }
5057
5058 if (final == val)
5059 return;
5060
5061 /* Always enable nonspread source */
5062 val &= ~DREF_NONSPREAD_SOURCE_MASK;
5063
5064 if (has_ck505)
5065 val |= DREF_NONSPREAD_CK505_ENABLE;
5066 else
5067 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5068
5069 if (has_panel) {
5070 val &= ~DREF_SSC_SOURCE_MASK;
5071 val |= DREF_SSC_SOURCE_ENABLE;
5072
5073 /* SSC must be turned on before enabling the CPU output */
5074 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5075 DRM_DEBUG_KMS("Using SSC on panel\n");
5076 val |= DREF_SSC1_ENABLE;
5077 } else
5078 val &= ~DREF_SSC1_ENABLE;
5079
5080 /* Get SSC going before enabling the outputs */
5081 I915_WRITE(PCH_DREF_CONTROL, val);
5082 POSTING_READ(PCH_DREF_CONTROL);
5083 udelay(200);
5084
5085 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5086
5087 /* Enable CPU source on CPU attached eDP */
5088 if (has_cpu_edp) {
5089 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5090 DRM_DEBUG_KMS("Using SSC on eDP\n");
5091 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5092 }
5093 else
5094 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5095 } else
5096 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5097
5098 I915_WRITE(PCH_DREF_CONTROL, val);
5099 POSTING_READ(PCH_DREF_CONTROL);
5100 udelay(200);
5101 } else {
5102 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5103
5104 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5105
5106 /* Turn off CPU output */
5107 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5108
5109 I915_WRITE(PCH_DREF_CONTROL, val);
5110 POSTING_READ(PCH_DREF_CONTROL);
5111 udelay(200);
5112
5113 /* Turn off the SSC source */
5114 val &= ~DREF_SSC_SOURCE_MASK;
5115 val |= DREF_SSC_SOURCE_DISABLE;
5116
5117 /* Turn off SSC1 */
5118 val &= ~DREF_SSC1_ENABLE;
5119
5120 I915_WRITE(PCH_DREF_CONTROL, val);
5121 POSTING_READ(PCH_DREF_CONTROL);
5122 udelay(200);
5123 }
5124
5125 BUG_ON(val != final);
5126 }
5127
5128 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5129 static void lpt_init_pch_refclk(struct drm_device *dev)
5130 {
5131 struct drm_i915_private *dev_priv = dev->dev_private;
5132 struct drm_mode_config *mode_config = &dev->mode_config;
5133 struct intel_encoder *encoder;
5134 bool has_vga = false;
5135 bool is_sdv = false;
5136 u32 tmp;
5137
5138 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5139 switch (encoder->type) {
5140 case INTEL_OUTPUT_ANALOG:
5141 has_vga = true;
5142 break;
5143 }
5144 }
5145
5146 if (!has_vga)
5147 return;
5148
5149 mutex_lock(&dev_priv->dpio_lock);
5150
5151 /* XXX: Rip out SDV support once Haswell ships for real. */
5152 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5153 is_sdv = true;
5154
5155 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5156 tmp &= ~SBI_SSCCTL_DISABLE;
5157 tmp |= SBI_SSCCTL_PATHALT;
5158 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5159
5160 udelay(24);
5161
5162 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5163 tmp &= ~SBI_SSCCTL_PATHALT;
5164 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5165
5166 if (!is_sdv) {
5167 tmp = I915_READ(SOUTH_CHICKEN2);
5168 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5169 I915_WRITE(SOUTH_CHICKEN2, tmp);
5170
5171 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5172 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5173 DRM_ERROR("FDI mPHY reset assert timeout\n");
5174
5175 tmp = I915_READ(SOUTH_CHICKEN2);
5176 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5177 I915_WRITE(SOUTH_CHICKEN2, tmp);
5178
5179 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5180 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5181 100))
5182 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5183 }
5184
5185 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5186 tmp &= ~(0xFF << 24);
5187 tmp |= (0x12 << 24);
5188 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5189
5190 if (is_sdv) {
5191 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5192 tmp |= 0x7FFF;
5193 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5194 }
5195
5196 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5197 tmp |= (1 << 11);
5198 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5199
5200 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5201 tmp |= (1 << 11);
5202 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5203
5204 if (is_sdv) {
5205 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5206 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5207 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5208
5209 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5210 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5211 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5212
5213 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5214 tmp |= (0x3F << 8);
5215 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5216
5217 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5218 tmp |= (0x3F << 8);
5219 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5220 }
5221
5222 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5223 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5224 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5225
5226 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5227 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5228 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5229
5230 if (!is_sdv) {
5231 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5232 tmp &= ~(7 << 13);
5233 tmp |= (5 << 13);
5234 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5235
5236 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5237 tmp &= ~(7 << 13);
5238 tmp |= (5 << 13);
5239 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5240 }
5241
5242 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5243 tmp &= ~0xFF;
5244 tmp |= 0x1C;
5245 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5246
5247 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5248 tmp &= ~0xFF;
5249 tmp |= 0x1C;
5250 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5251
5252 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5253 tmp &= ~(0xFF << 16);
5254 tmp |= (0x1C << 16);
5255 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5256
5257 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5258 tmp &= ~(0xFF << 16);
5259 tmp |= (0x1C << 16);
5260 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5261
5262 if (!is_sdv) {
5263 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5264 tmp |= (1 << 27);
5265 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5266
5267 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5268 tmp |= (1 << 27);
5269 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5270
5271 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5272 tmp &= ~(0xF << 28);
5273 tmp |= (4 << 28);
5274 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5275
5276 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5277 tmp &= ~(0xF << 28);
5278 tmp |= (4 << 28);
5279 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5280 }
5281
5282 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5283 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5284 tmp |= SBI_DBUFF0_ENABLE;
5285 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5286
5287 mutex_unlock(&dev_priv->dpio_lock);
5288 }
5289
5290 /*
5291 * Initialize reference clocks when the driver loads
5292 */
5293 void intel_init_pch_refclk(struct drm_device *dev)
5294 {
5295 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5296 ironlake_init_pch_refclk(dev);
5297 else if (HAS_PCH_LPT(dev))
5298 lpt_init_pch_refclk(dev);
5299 }
5300
5301 static int ironlake_get_refclk(struct drm_crtc *crtc)
5302 {
5303 struct drm_device *dev = crtc->dev;
5304 struct drm_i915_private *dev_priv = dev->dev_private;
5305 struct intel_encoder *encoder;
5306 int num_connectors = 0;
5307 bool is_lvds = false;
5308
5309 for_each_encoder_on_crtc(dev, crtc, encoder) {
5310 switch (encoder->type) {
5311 case INTEL_OUTPUT_LVDS:
5312 is_lvds = true;
5313 break;
5314 }
5315 num_connectors++;
5316 }
5317
5318 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5319 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5320 dev_priv->vbt.lvds_ssc_freq);
5321 return dev_priv->vbt.lvds_ssc_freq * 1000;
5322 }
5323
5324 return 120000;
5325 }
5326
5327 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5328 {
5329 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5330 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5331 int pipe = intel_crtc->pipe;
5332 uint32_t val;
5333
5334 val = I915_READ(PIPECONF(pipe));
5335
5336 val &= ~PIPECONF_BPC_MASK;
5337 switch (intel_crtc->config.pipe_bpp) {
5338 case 18:
5339 val |= PIPECONF_6BPC;
5340 break;
5341 case 24:
5342 val |= PIPECONF_8BPC;
5343 break;
5344 case 30:
5345 val |= PIPECONF_10BPC;
5346 break;
5347 case 36:
5348 val |= PIPECONF_12BPC;
5349 break;
5350 default:
5351 /* Case prevented by intel_choose_pipe_bpp_dither. */
5352 BUG();
5353 }
5354
5355 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5356 if (intel_crtc->config.dither)
5357 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5358
5359 val &= ~PIPECONF_INTERLACE_MASK;
5360 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5361 val |= PIPECONF_INTERLACED_ILK;
5362 else
5363 val |= PIPECONF_PROGRESSIVE;
5364
5365 if (intel_crtc->config.limited_color_range)
5366 val |= PIPECONF_COLOR_RANGE_SELECT;
5367 else
5368 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5369
5370 I915_WRITE(PIPECONF(pipe), val);
5371 POSTING_READ(PIPECONF(pipe));
5372 }
5373
5374 /*
5375 * Set up the pipe CSC unit.
5376 *
5377 * Currently only full range RGB to limited range RGB conversion
5378 * is supported, but eventually this should handle various
5379 * RGB<->YCbCr scenarios as well.
5380 */
5381 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5382 {
5383 struct drm_device *dev = crtc->dev;
5384 struct drm_i915_private *dev_priv = dev->dev_private;
5385 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5386 int pipe = intel_crtc->pipe;
5387 uint16_t coeff = 0x7800; /* 1.0 */
5388
5389 /*
5390 * TODO: Check what kind of values actually come out of the pipe
5391 * with these coeff/postoff values and adjust to get the best
5392 * accuracy. Perhaps we even need to take the bpc value into
5393 * consideration.
5394 */
5395
5396 if (intel_crtc->config.limited_color_range)
5397 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5398
5399 /*
5400 * GY/GU and RY/RU should be the other way around according
5401 * to BSpec, but reality doesn't agree. Just set them up in
5402 * a way that results in the correct picture.
5403 */
5404 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5405 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5406
5407 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5408 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5409
5410 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5411 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5412
5413 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5414 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5415 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5416
5417 if (INTEL_INFO(dev)->gen > 6) {
5418 uint16_t postoff = 0;
5419
5420 if (intel_crtc->config.limited_color_range)
5421 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5422
5423 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5424 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5425 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5426
5427 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5428 } else {
5429 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5430
5431 if (intel_crtc->config.limited_color_range)
5432 mode |= CSC_BLACK_SCREEN_OFFSET;
5433
5434 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5435 }
5436 }
5437
5438 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5439 {
5440 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5441 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5442 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5443 uint32_t val;
5444
5445 val = I915_READ(PIPECONF(cpu_transcoder));
5446
5447 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5448 if (intel_crtc->config.dither)
5449 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5450
5451 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5452 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5453 val |= PIPECONF_INTERLACED_ILK;
5454 else
5455 val |= PIPECONF_PROGRESSIVE;
5456
5457 I915_WRITE(PIPECONF(cpu_transcoder), val);
5458 POSTING_READ(PIPECONF(cpu_transcoder));
5459 }
5460
5461 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5462 struct drm_display_mode *adjusted_mode,
5463 intel_clock_t *clock,
5464 bool *has_reduced_clock,
5465 intel_clock_t *reduced_clock)
5466 {
5467 struct drm_device *dev = crtc->dev;
5468 struct drm_i915_private *dev_priv = dev->dev_private;
5469 struct intel_encoder *intel_encoder;
5470 int refclk;
5471 const intel_limit_t *limit;
5472 bool ret, is_lvds = false;
5473
5474 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5475 switch (intel_encoder->type) {
5476 case INTEL_OUTPUT_LVDS:
5477 is_lvds = true;
5478 break;
5479 }
5480 }
5481
5482 refclk = ironlake_get_refclk(crtc);
5483
5484 /*
5485 * Returns a set of divisors for the desired target clock with the given
5486 * refclk, or FALSE. The returned values represent the clock equation:
5487 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5488 */
5489 limit = intel_limit(crtc, refclk);
5490 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5491 clock);
5492 if (!ret)
5493 return false;
5494
5495 if (is_lvds && dev_priv->lvds_downclock_avail) {
5496 /*
5497 * Ensure we match the reduced clock's P to the target clock.
5498 * If the clocks don't match, we can't switch the display clock
5499 * by using the FP0/FP1. In such case we will disable the LVDS
5500 * downclock feature.
5501 */
5502 *has_reduced_clock = limit->find_pll(limit, crtc,
5503 dev_priv->lvds_downclock,
5504 refclk,
5505 clock,
5506 reduced_clock);
5507 }
5508
5509 return true;
5510 }
5511
5512 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5513 {
5514 struct drm_i915_private *dev_priv = dev->dev_private;
5515 uint32_t temp;
5516
5517 temp = I915_READ(SOUTH_CHICKEN1);
5518 if (temp & FDI_BC_BIFURCATION_SELECT)
5519 return;
5520
5521 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5522 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5523
5524 temp |= FDI_BC_BIFURCATION_SELECT;
5525 DRM_DEBUG_KMS("enabling fdi C rx\n");
5526 I915_WRITE(SOUTH_CHICKEN1, temp);
5527 POSTING_READ(SOUTH_CHICKEN1);
5528 }
5529
5530 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5531 {
5532 struct drm_device *dev = intel_crtc->base.dev;
5533 struct drm_i915_private *dev_priv = dev->dev_private;
5534
5535 switch (intel_crtc->pipe) {
5536 case PIPE_A:
5537 break;
5538 case PIPE_B:
5539 if (intel_crtc->config.fdi_lanes > 2)
5540 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5541 else
5542 cpt_enable_fdi_bc_bifurcation(dev);
5543
5544 break;
5545 case PIPE_C:
5546 cpt_enable_fdi_bc_bifurcation(dev);
5547
5548 break;
5549 default:
5550 BUG();
5551 }
5552 }
5553
5554 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5555 {
5556 /*
5557 * Account for spread spectrum to avoid
5558 * oversubscribing the link. Max center spread
5559 * is 2.5%; use 5% for safety's sake.
5560 */
5561 u32 bps = target_clock * bpp * 21 / 20;
5562 return bps / (link_bw * 8) + 1;
5563 }
5564
5565 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5566 {
5567 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5568 }
5569
5570 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5571 u32 *fp,
5572 intel_clock_t *reduced_clock, u32 *fp2)
5573 {
5574 struct drm_crtc *crtc = &intel_crtc->base;
5575 struct drm_device *dev = crtc->dev;
5576 struct drm_i915_private *dev_priv = dev->dev_private;
5577 struct intel_encoder *intel_encoder;
5578 uint32_t dpll;
5579 int factor, num_connectors = 0;
5580 bool is_lvds = false, is_sdvo = false;
5581
5582 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5583 switch (intel_encoder->type) {
5584 case INTEL_OUTPUT_LVDS:
5585 is_lvds = true;
5586 break;
5587 case INTEL_OUTPUT_SDVO:
5588 case INTEL_OUTPUT_HDMI:
5589 is_sdvo = true;
5590 break;
5591 }
5592
5593 num_connectors++;
5594 }
5595
5596 /* Enable autotuning of the PLL clock (if permissible) */
5597 factor = 21;
5598 if (is_lvds) {
5599 if ((intel_panel_use_ssc(dev_priv) &&
5600 dev_priv->vbt.lvds_ssc_freq == 100) ||
5601 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5602 factor = 25;
5603 } else if (intel_crtc->config.sdvo_tv_clock)
5604 factor = 20;
5605
5606 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5607 *fp |= FP_CB_TUNE;
5608
5609 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5610 *fp2 |= FP_CB_TUNE;
5611
5612 dpll = 0;
5613
5614 if (is_lvds)
5615 dpll |= DPLLB_MODE_LVDS;
5616 else
5617 dpll |= DPLLB_MODE_DAC_SERIAL;
5618
5619 if (intel_crtc->config.pixel_multiplier > 1) {
5620 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5621 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5622 }
5623
5624 if (is_sdvo)
5625 dpll |= DPLL_DVO_HIGH_SPEED;
5626 if (intel_crtc->config.has_dp_encoder)
5627 dpll |= DPLL_DVO_HIGH_SPEED;
5628
5629 /* compute bitmask from p1 value */
5630 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5631 /* also FPA1 */
5632 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5633
5634 switch (intel_crtc->config.dpll.p2) {
5635 case 5:
5636 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5637 break;
5638 case 7:
5639 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5640 break;
5641 case 10:
5642 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5643 break;
5644 case 14:
5645 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5646 break;
5647 }
5648
5649 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5650 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5651 else
5652 dpll |= PLL_REF_INPUT_DREFCLK;
5653
5654 return dpll;
5655 }
5656
5657 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5658 int x, int y,
5659 struct drm_framebuffer *fb)
5660 {
5661 struct drm_device *dev = crtc->dev;
5662 struct drm_i915_private *dev_priv = dev->dev_private;
5663 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5664 struct drm_display_mode *adjusted_mode =
5665 &intel_crtc->config.adjusted_mode;
5666 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5667 int pipe = intel_crtc->pipe;
5668 int plane = intel_crtc->plane;
5669 int num_connectors = 0;
5670 intel_clock_t clock, reduced_clock;
5671 u32 dpll = 0, fp = 0, fp2 = 0;
5672 bool ok, has_reduced_clock = false;
5673 bool is_lvds = false;
5674 struct intel_encoder *encoder;
5675 int ret;
5676
5677 for_each_encoder_on_crtc(dev, crtc, encoder) {
5678 switch (encoder->type) {
5679 case INTEL_OUTPUT_LVDS:
5680 is_lvds = true;
5681 break;
5682 }
5683
5684 num_connectors++;
5685 }
5686
5687 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5688 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5689
5690 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5691 &has_reduced_clock, &reduced_clock);
5692 if (!ok) {
5693 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5694 return -EINVAL;
5695 }
5696 /* Compat-code for transition, will disappear. */
5697 if (!intel_crtc->config.clock_set) {
5698 intel_crtc->config.dpll.n = clock.n;
5699 intel_crtc->config.dpll.m1 = clock.m1;
5700 intel_crtc->config.dpll.m2 = clock.m2;
5701 intel_crtc->config.dpll.p1 = clock.p1;
5702 intel_crtc->config.dpll.p2 = clock.p2;
5703 }
5704
5705 /* Ensure that the cursor is valid for the new mode before changing... */
5706 intel_crtc_update_cursor(crtc, true);
5707
5708 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5709 if (intel_crtc->config.has_pch_encoder) {
5710 struct intel_pch_pll *pll;
5711
5712 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5713 if (has_reduced_clock)
5714 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5715
5716 dpll = ironlake_compute_dpll(intel_crtc,
5717 &fp, &reduced_clock,
5718 has_reduced_clock ? &fp2 : NULL);
5719
5720 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5721 if (pll == NULL) {
5722 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5723 pipe_name(pipe));
5724 return -EINVAL;
5725 }
5726 } else
5727 intel_put_pch_pll(intel_crtc);
5728
5729 if (intel_crtc->config.has_dp_encoder)
5730 intel_dp_set_m_n(intel_crtc);
5731
5732 for_each_encoder_on_crtc(dev, crtc, encoder)
5733 if (encoder->pre_pll_enable)
5734 encoder->pre_pll_enable(encoder);
5735
5736 if (intel_crtc->pch_pll) {
5737 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5738
5739 /* Wait for the clocks to stabilize. */
5740 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5741 udelay(150);
5742
5743 /* The pixel multiplier can only be updated once the
5744 * DPLL is enabled and the clocks are stable.
5745 *
5746 * So write it again.
5747 */
5748 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5749 }
5750
5751 intel_crtc->lowfreq_avail = false;
5752 if (intel_crtc->pch_pll) {
5753 if (is_lvds && has_reduced_clock && i915_powersave) {
5754 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5755 intel_crtc->lowfreq_avail = true;
5756 } else {
5757 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5758 }
5759 }
5760
5761 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5762
5763 if (intel_crtc->config.has_pch_encoder) {
5764 intel_cpu_transcoder_set_m_n(intel_crtc,
5765 &intel_crtc->config.fdi_m_n);
5766 }
5767
5768 if (IS_IVYBRIDGE(dev))
5769 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5770
5771 ironlake_set_pipeconf(crtc);
5772
5773 /* Set up the display plane register */
5774 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5775 POSTING_READ(DSPCNTR(plane));
5776
5777 ret = intel_pipe_set_base(crtc, x, y, fb);
5778
5779 intel_update_watermarks(dev);
5780
5781 return ret;
5782 }
5783
5784 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5785 struct intel_crtc_config *pipe_config)
5786 {
5787 struct drm_device *dev = crtc->base.dev;
5788 struct drm_i915_private *dev_priv = dev->dev_private;
5789 enum transcoder transcoder = pipe_config->cpu_transcoder;
5790
5791 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5792 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5793 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5794 & ~TU_SIZE_MASK;
5795 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5796 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5797 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5798 }
5799
5800 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5801 struct intel_crtc_config *pipe_config)
5802 {
5803 struct drm_device *dev = crtc->base.dev;
5804 struct drm_i915_private *dev_priv = dev->dev_private;
5805 uint32_t tmp;
5806
5807 tmp = I915_READ(PF_CTL(crtc->pipe));
5808
5809 if (tmp & PF_ENABLE) {
5810 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5811 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5812 }
5813 }
5814
5815 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5816 struct intel_crtc_config *pipe_config)
5817 {
5818 struct drm_device *dev = crtc->base.dev;
5819 struct drm_i915_private *dev_priv = dev->dev_private;
5820 uint32_t tmp;
5821
5822 pipe_config->cpu_transcoder = crtc->pipe;
5823
5824 tmp = I915_READ(PIPECONF(crtc->pipe));
5825 if (!(tmp & PIPECONF_ENABLE))
5826 return false;
5827
5828 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5829 pipe_config->has_pch_encoder = true;
5830
5831 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5832 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5833 FDI_DP_PORT_WIDTH_SHIFT) + 1;
5834
5835 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5836 }
5837
5838 intel_get_pipe_timings(crtc, pipe_config);
5839
5840 ironlake_get_pfit_config(crtc, pipe_config);
5841
5842 return true;
5843 }
5844
5845 static void haswell_modeset_global_resources(struct drm_device *dev)
5846 {
5847 bool enable = false;
5848 struct intel_crtc *crtc;
5849
5850 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5851 if (!crtc->base.enabled)
5852 continue;
5853
5854 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5855 crtc->config.cpu_transcoder != TRANSCODER_EDP)
5856 enable = true;
5857 }
5858
5859 intel_set_power_well(dev, enable);
5860 }
5861
5862 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5863 int x, int y,
5864 struct drm_framebuffer *fb)
5865 {
5866 struct drm_device *dev = crtc->dev;
5867 struct drm_i915_private *dev_priv = dev->dev_private;
5868 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5869 struct drm_display_mode *adjusted_mode =
5870 &intel_crtc->config.adjusted_mode;
5871 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5872 int pipe = intel_crtc->pipe;
5873 int plane = intel_crtc->plane;
5874 int num_connectors = 0;
5875 bool is_cpu_edp = false;
5876 struct intel_encoder *encoder;
5877 int ret;
5878
5879 for_each_encoder_on_crtc(dev, crtc, encoder) {
5880 switch (encoder->type) {
5881 case INTEL_OUTPUT_EDP:
5882 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5883 is_cpu_edp = true;
5884 break;
5885 }
5886
5887 num_connectors++;
5888 }
5889
5890 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5891 num_connectors, pipe_name(pipe));
5892
5893 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5894 return -EINVAL;
5895
5896 /* Ensure that the cursor is valid for the new mode before changing... */
5897 intel_crtc_update_cursor(crtc, true);
5898
5899 if (intel_crtc->config.has_dp_encoder)
5900 intel_dp_set_m_n(intel_crtc);
5901
5902 intel_crtc->lowfreq_avail = false;
5903
5904 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5905
5906 if (intel_crtc->config.has_pch_encoder) {
5907 intel_cpu_transcoder_set_m_n(intel_crtc,
5908 &intel_crtc->config.fdi_m_n);
5909 }
5910
5911 haswell_set_pipeconf(crtc);
5912
5913 intel_set_pipe_csc(crtc);
5914
5915 /* Set up the display plane register */
5916 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
5917 POSTING_READ(DSPCNTR(plane));
5918
5919 ret = intel_pipe_set_base(crtc, x, y, fb);
5920
5921 intel_update_watermarks(dev);
5922
5923 return ret;
5924 }
5925
5926 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5927 struct intel_crtc_config *pipe_config)
5928 {
5929 struct drm_device *dev = crtc->base.dev;
5930 struct drm_i915_private *dev_priv = dev->dev_private;
5931 enum intel_display_power_domain pfit_domain;
5932 uint32_t tmp;
5933
5934 pipe_config->cpu_transcoder = crtc->pipe;
5935 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5936 if (tmp & TRANS_DDI_FUNC_ENABLE) {
5937 enum pipe trans_edp_pipe;
5938 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
5939 default:
5940 WARN(1, "unknown pipe linked to edp transcoder\n");
5941 case TRANS_DDI_EDP_INPUT_A_ONOFF:
5942 case TRANS_DDI_EDP_INPUT_A_ON:
5943 trans_edp_pipe = PIPE_A;
5944 break;
5945 case TRANS_DDI_EDP_INPUT_B_ONOFF:
5946 trans_edp_pipe = PIPE_B;
5947 break;
5948 case TRANS_DDI_EDP_INPUT_C_ONOFF:
5949 trans_edp_pipe = PIPE_C;
5950 break;
5951 }
5952
5953 if (trans_edp_pipe == crtc->pipe)
5954 pipe_config->cpu_transcoder = TRANSCODER_EDP;
5955 }
5956
5957 if (!intel_display_power_enabled(dev,
5958 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
5959 return false;
5960
5961 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
5962 if (!(tmp & PIPECONF_ENABLE))
5963 return false;
5964
5965 /*
5966 * Haswell has only FDI/PCH transcoder A. It is which is connected to
5967 * DDI E. So just check whether this pipe is wired to DDI E and whether
5968 * the PCH transcoder is on.
5969 */
5970 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
5971 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
5972 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
5973 pipe_config->has_pch_encoder = true;
5974
5975 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
5976 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5977 FDI_DP_PORT_WIDTH_SHIFT) + 1;
5978
5979 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5980 }
5981
5982 intel_get_pipe_timings(crtc, pipe_config);
5983
5984 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
5985 if (intel_display_power_enabled(dev, pfit_domain))
5986 ironlake_get_pfit_config(crtc, pipe_config);
5987
5988 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
5989 (I915_READ(IPS_CTL) & IPS_ENABLE);
5990
5991 return true;
5992 }
5993
5994 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5995 int x, int y,
5996 struct drm_framebuffer *fb)
5997 {
5998 struct drm_device *dev = crtc->dev;
5999 struct drm_i915_private *dev_priv = dev->dev_private;
6000 struct drm_encoder_helper_funcs *encoder_funcs;
6001 struct intel_encoder *encoder;
6002 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6003 struct drm_display_mode *adjusted_mode =
6004 &intel_crtc->config.adjusted_mode;
6005 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6006 int pipe = intel_crtc->pipe;
6007 int ret;
6008
6009 drm_vblank_pre_modeset(dev, pipe);
6010
6011 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6012
6013 drm_vblank_post_modeset(dev, pipe);
6014
6015 if (ret != 0)
6016 return ret;
6017
6018 for_each_encoder_on_crtc(dev, crtc, encoder) {
6019 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6020 encoder->base.base.id,
6021 drm_get_encoder_name(&encoder->base),
6022 mode->base.id, mode->name);
6023 if (encoder->mode_set) {
6024 encoder->mode_set(encoder);
6025 } else {
6026 encoder_funcs = encoder->base.helper_private;
6027 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6028 }
6029 }
6030
6031 return 0;
6032 }
6033
6034 static bool intel_eld_uptodate(struct drm_connector *connector,
6035 int reg_eldv, uint32_t bits_eldv,
6036 int reg_elda, uint32_t bits_elda,
6037 int reg_edid)
6038 {
6039 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6040 uint8_t *eld = connector->eld;
6041 uint32_t i;
6042
6043 i = I915_READ(reg_eldv);
6044 i &= bits_eldv;
6045
6046 if (!eld[0])
6047 return !i;
6048
6049 if (!i)
6050 return false;
6051
6052 i = I915_READ(reg_elda);
6053 i &= ~bits_elda;
6054 I915_WRITE(reg_elda, i);
6055
6056 for (i = 0; i < eld[2]; i++)
6057 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6058 return false;
6059
6060 return true;
6061 }
6062
6063 static void g4x_write_eld(struct drm_connector *connector,
6064 struct drm_crtc *crtc)
6065 {
6066 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6067 uint8_t *eld = connector->eld;
6068 uint32_t eldv;
6069 uint32_t len;
6070 uint32_t i;
6071
6072 i = I915_READ(G4X_AUD_VID_DID);
6073
6074 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6075 eldv = G4X_ELDV_DEVCL_DEVBLC;
6076 else
6077 eldv = G4X_ELDV_DEVCTG;
6078
6079 if (intel_eld_uptodate(connector,
6080 G4X_AUD_CNTL_ST, eldv,
6081 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6082 G4X_HDMIW_HDMIEDID))
6083 return;
6084
6085 i = I915_READ(G4X_AUD_CNTL_ST);
6086 i &= ~(eldv | G4X_ELD_ADDR);
6087 len = (i >> 9) & 0x1f; /* ELD buffer size */
6088 I915_WRITE(G4X_AUD_CNTL_ST, i);
6089
6090 if (!eld[0])
6091 return;
6092
6093 len = min_t(uint8_t, eld[2], len);
6094 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6095 for (i = 0; i < len; i++)
6096 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6097
6098 i = I915_READ(G4X_AUD_CNTL_ST);
6099 i |= eldv;
6100 I915_WRITE(G4X_AUD_CNTL_ST, i);
6101 }
6102
6103 static void haswell_write_eld(struct drm_connector *connector,
6104 struct drm_crtc *crtc)
6105 {
6106 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6107 uint8_t *eld = connector->eld;
6108 struct drm_device *dev = crtc->dev;
6109 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6110 uint32_t eldv;
6111 uint32_t i;
6112 int len;
6113 int pipe = to_intel_crtc(crtc)->pipe;
6114 int tmp;
6115
6116 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6117 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6118 int aud_config = HSW_AUD_CFG(pipe);
6119 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6120
6121
6122 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6123
6124 /* Audio output enable */
6125 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6126 tmp = I915_READ(aud_cntrl_st2);
6127 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6128 I915_WRITE(aud_cntrl_st2, tmp);
6129
6130 /* Wait for 1 vertical blank */
6131 intel_wait_for_vblank(dev, pipe);
6132
6133 /* Set ELD valid state */
6134 tmp = I915_READ(aud_cntrl_st2);
6135 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6136 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6137 I915_WRITE(aud_cntrl_st2, tmp);
6138 tmp = I915_READ(aud_cntrl_st2);
6139 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6140
6141 /* Enable HDMI mode */
6142 tmp = I915_READ(aud_config);
6143 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6144 /* clear N_programing_enable and N_value_index */
6145 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6146 I915_WRITE(aud_config, tmp);
6147
6148 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6149
6150 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6151 intel_crtc->eld_vld = true;
6152
6153 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6154 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6155 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6156 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6157 } else
6158 I915_WRITE(aud_config, 0);
6159
6160 if (intel_eld_uptodate(connector,
6161 aud_cntrl_st2, eldv,
6162 aud_cntl_st, IBX_ELD_ADDRESS,
6163 hdmiw_hdmiedid))
6164 return;
6165
6166 i = I915_READ(aud_cntrl_st2);
6167 i &= ~eldv;
6168 I915_WRITE(aud_cntrl_st2, i);
6169
6170 if (!eld[0])
6171 return;
6172
6173 i = I915_READ(aud_cntl_st);
6174 i &= ~IBX_ELD_ADDRESS;
6175 I915_WRITE(aud_cntl_st, i);
6176 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6177 DRM_DEBUG_DRIVER("port num:%d\n", i);
6178
6179 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6180 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6181 for (i = 0; i < len; i++)
6182 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6183
6184 i = I915_READ(aud_cntrl_st2);
6185 i |= eldv;
6186 I915_WRITE(aud_cntrl_st2, i);
6187
6188 }
6189
6190 static void ironlake_write_eld(struct drm_connector *connector,
6191 struct drm_crtc *crtc)
6192 {
6193 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6194 uint8_t *eld = connector->eld;
6195 uint32_t eldv;
6196 uint32_t i;
6197 int len;
6198 int hdmiw_hdmiedid;
6199 int aud_config;
6200 int aud_cntl_st;
6201 int aud_cntrl_st2;
6202 int pipe = to_intel_crtc(crtc)->pipe;
6203
6204 if (HAS_PCH_IBX(connector->dev)) {
6205 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6206 aud_config = IBX_AUD_CFG(pipe);
6207 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6208 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6209 } else {
6210 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6211 aud_config = CPT_AUD_CFG(pipe);
6212 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6213 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6214 }
6215
6216 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6217
6218 i = I915_READ(aud_cntl_st);
6219 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6220 if (!i) {
6221 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6222 /* operate blindly on all ports */
6223 eldv = IBX_ELD_VALIDB;
6224 eldv |= IBX_ELD_VALIDB << 4;
6225 eldv |= IBX_ELD_VALIDB << 8;
6226 } else {
6227 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6228 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6229 }
6230
6231 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6232 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6233 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6234 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6235 } else
6236 I915_WRITE(aud_config, 0);
6237
6238 if (intel_eld_uptodate(connector,
6239 aud_cntrl_st2, eldv,
6240 aud_cntl_st, IBX_ELD_ADDRESS,
6241 hdmiw_hdmiedid))
6242 return;
6243
6244 i = I915_READ(aud_cntrl_st2);
6245 i &= ~eldv;
6246 I915_WRITE(aud_cntrl_st2, i);
6247
6248 if (!eld[0])
6249 return;
6250
6251 i = I915_READ(aud_cntl_st);
6252 i &= ~IBX_ELD_ADDRESS;
6253 I915_WRITE(aud_cntl_st, i);
6254
6255 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6256 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6257 for (i = 0; i < len; i++)
6258 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6259
6260 i = I915_READ(aud_cntrl_st2);
6261 i |= eldv;
6262 I915_WRITE(aud_cntrl_st2, i);
6263 }
6264
6265 void intel_write_eld(struct drm_encoder *encoder,
6266 struct drm_display_mode *mode)
6267 {
6268 struct drm_crtc *crtc = encoder->crtc;
6269 struct drm_connector *connector;
6270 struct drm_device *dev = encoder->dev;
6271 struct drm_i915_private *dev_priv = dev->dev_private;
6272
6273 connector = drm_select_eld(encoder, mode);
6274 if (!connector)
6275 return;
6276
6277 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6278 connector->base.id,
6279 drm_get_connector_name(connector),
6280 connector->encoder->base.id,
6281 drm_get_encoder_name(connector->encoder));
6282
6283 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6284
6285 if (dev_priv->display.write_eld)
6286 dev_priv->display.write_eld(connector, crtc);
6287 }
6288
6289 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6290 void intel_crtc_load_lut(struct drm_crtc *crtc)
6291 {
6292 struct drm_device *dev = crtc->dev;
6293 struct drm_i915_private *dev_priv = dev->dev_private;
6294 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6295 enum pipe pipe = intel_crtc->pipe;
6296 int palreg = PALETTE(pipe);
6297 int i;
6298 bool reenable_ips = false;
6299
6300 /* The clocks have to be on to load the palette. */
6301 if (!crtc->enabled || !intel_crtc->active)
6302 return;
6303
6304 /* use legacy palette for Ironlake */
6305 if (HAS_PCH_SPLIT(dev))
6306 palreg = LGC_PALETTE(pipe);
6307
6308 /* Workaround : Do not read or write the pipe palette/gamma data while
6309 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6310 */
6311 if (intel_crtc->config.ips_enabled &&
6312 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6313 GAMMA_MODE_MODE_SPLIT)) {
6314 hsw_disable_ips(intel_crtc);
6315 reenable_ips = true;
6316 }
6317
6318 for (i = 0; i < 256; i++) {
6319 I915_WRITE(palreg + 4 * i,
6320 (intel_crtc->lut_r[i] << 16) |
6321 (intel_crtc->lut_g[i] << 8) |
6322 intel_crtc->lut_b[i]);
6323 }
6324
6325 if (reenable_ips)
6326 hsw_enable_ips(intel_crtc);
6327 }
6328
6329 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6330 {
6331 struct drm_device *dev = crtc->dev;
6332 struct drm_i915_private *dev_priv = dev->dev_private;
6333 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6334 bool visible = base != 0;
6335 u32 cntl;
6336
6337 if (intel_crtc->cursor_visible == visible)
6338 return;
6339
6340 cntl = I915_READ(_CURACNTR);
6341 if (visible) {
6342 /* On these chipsets we can only modify the base whilst
6343 * the cursor is disabled.
6344 */
6345 I915_WRITE(_CURABASE, base);
6346
6347 cntl &= ~(CURSOR_FORMAT_MASK);
6348 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6349 cntl |= CURSOR_ENABLE |
6350 CURSOR_GAMMA_ENABLE |
6351 CURSOR_FORMAT_ARGB;
6352 } else
6353 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6354 I915_WRITE(_CURACNTR, cntl);
6355
6356 intel_crtc->cursor_visible = visible;
6357 }
6358
6359 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6360 {
6361 struct drm_device *dev = crtc->dev;
6362 struct drm_i915_private *dev_priv = dev->dev_private;
6363 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6364 int pipe = intel_crtc->pipe;
6365 bool visible = base != 0;
6366
6367 if (intel_crtc->cursor_visible != visible) {
6368 uint32_t cntl = I915_READ(CURCNTR(pipe));
6369 if (base) {
6370 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6371 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6372 cntl |= pipe << 28; /* Connect to correct pipe */
6373 } else {
6374 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6375 cntl |= CURSOR_MODE_DISABLE;
6376 }
6377 I915_WRITE(CURCNTR(pipe), cntl);
6378
6379 intel_crtc->cursor_visible = visible;
6380 }
6381 /* and commit changes on next vblank */
6382 I915_WRITE(CURBASE(pipe), base);
6383 }
6384
6385 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6386 {
6387 struct drm_device *dev = crtc->dev;
6388 struct drm_i915_private *dev_priv = dev->dev_private;
6389 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6390 int pipe = intel_crtc->pipe;
6391 bool visible = base != 0;
6392
6393 if (intel_crtc->cursor_visible != visible) {
6394 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6395 if (base) {
6396 cntl &= ~CURSOR_MODE;
6397 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6398 } else {
6399 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6400 cntl |= CURSOR_MODE_DISABLE;
6401 }
6402 if (IS_HASWELL(dev))
6403 cntl |= CURSOR_PIPE_CSC_ENABLE;
6404 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6405
6406 intel_crtc->cursor_visible = visible;
6407 }
6408 /* and commit changes on next vblank */
6409 I915_WRITE(CURBASE_IVB(pipe), base);
6410 }
6411
6412 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6413 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6414 bool on)
6415 {
6416 struct drm_device *dev = crtc->dev;
6417 struct drm_i915_private *dev_priv = dev->dev_private;
6418 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6419 int pipe = intel_crtc->pipe;
6420 int x = intel_crtc->cursor_x;
6421 int y = intel_crtc->cursor_y;
6422 u32 base, pos;
6423 bool visible;
6424
6425 pos = 0;
6426
6427 if (on && crtc->enabled && crtc->fb) {
6428 base = intel_crtc->cursor_addr;
6429 if (x > (int) crtc->fb->width)
6430 base = 0;
6431
6432 if (y > (int) crtc->fb->height)
6433 base = 0;
6434 } else
6435 base = 0;
6436
6437 if (x < 0) {
6438 if (x + intel_crtc->cursor_width < 0)
6439 base = 0;
6440
6441 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6442 x = -x;
6443 }
6444 pos |= x << CURSOR_X_SHIFT;
6445
6446 if (y < 0) {
6447 if (y + intel_crtc->cursor_height < 0)
6448 base = 0;
6449
6450 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6451 y = -y;
6452 }
6453 pos |= y << CURSOR_Y_SHIFT;
6454
6455 visible = base != 0;
6456 if (!visible && !intel_crtc->cursor_visible)
6457 return;
6458
6459 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6460 I915_WRITE(CURPOS_IVB(pipe), pos);
6461 ivb_update_cursor(crtc, base);
6462 } else {
6463 I915_WRITE(CURPOS(pipe), pos);
6464 if (IS_845G(dev) || IS_I865G(dev))
6465 i845_update_cursor(crtc, base);
6466 else
6467 i9xx_update_cursor(crtc, base);
6468 }
6469 }
6470
6471 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6472 struct drm_file *file,
6473 uint32_t handle,
6474 uint32_t width, uint32_t height)
6475 {
6476 struct drm_device *dev = crtc->dev;
6477 struct drm_i915_private *dev_priv = dev->dev_private;
6478 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6479 struct drm_i915_gem_object *obj;
6480 uint32_t addr;
6481 int ret;
6482
6483 /* if we want to turn off the cursor ignore width and height */
6484 if (!handle) {
6485 DRM_DEBUG_KMS("cursor off\n");
6486 addr = 0;
6487 obj = NULL;
6488 mutex_lock(&dev->struct_mutex);
6489 goto finish;
6490 }
6491
6492 /* Currently we only support 64x64 cursors */
6493 if (width != 64 || height != 64) {
6494 DRM_ERROR("we currently only support 64x64 cursors\n");
6495 return -EINVAL;
6496 }
6497
6498 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6499 if (&obj->base == NULL)
6500 return -ENOENT;
6501
6502 if (obj->base.size < width * height * 4) {
6503 DRM_ERROR("buffer is to small\n");
6504 ret = -ENOMEM;
6505 goto fail;
6506 }
6507
6508 /* we only need to pin inside GTT if cursor is non-phy */
6509 mutex_lock(&dev->struct_mutex);
6510 if (!dev_priv->info->cursor_needs_physical) {
6511 unsigned alignment;
6512
6513 if (obj->tiling_mode) {
6514 DRM_ERROR("cursor cannot be tiled\n");
6515 ret = -EINVAL;
6516 goto fail_locked;
6517 }
6518
6519 /* Note that the w/a also requires 2 PTE of padding following
6520 * the bo. We currently fill all unused PTE with the shadow
6521 * page and so we should always have valid PTE following the
6522 * cursor preventing the VT-d warning.
6523 */
6524 alignment = 0;
6525 if (need_vtd_wa(dev))
6526 alignment = 64*1024;
6527
6528 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6529 if (ret) {
6530 DRM_ERROR("failed to move cursor bo into the GTT\n");
6531 goto fail_locked;
6532 }
6533
6534 ret = i915_gem_object_put_fence(obj);
6535 if (ret) {
6536 DRM_ERROR("failed to release fence for cursor");
6537 goto fail_unpin;
6538 }
6539
6540 addr = obj->gtt_offset;
6541 } else {
6542 int align = IS_I830(dev) ? 16 * 1024 : 256;
6543 ret = i915_gem_attach_phys_object(dev, obj,
6544 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6545 align);
6546 if (ret) {
6547 DRM_ERROR("failed to attach phys object\n");
6548 goto fail_locked;
6549 }
6550 addr = obj->phys_obj->handle->busaddr;
6551 }
6552
6553 if (IS_GEN2(dev))
6554 I915_WRITE(CURSIZE, (height << 12) | width);
6555
6556 finish:
6557 if (intel_crtc->cursor_bo) {
6558 if (dev_priv->info->cursor_needs_physical) {
6559 if (intel_crtc->cursor_bo != obj)
6560 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6561 } else
6562 i915_gem_object_unpin(intel_crtc->cursor_bo);
6563 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6564 }
6565
6566 mutex_unlock(&dev->struct_mutex);
6567
6568 intel_crtc->cursor_addr = addr;
6569 intel_crtc->cursor_bo = obj;
6570 intel_crtc->cursor_width = width;
6571 intel_crtc->cursor_height = height;
6572
6573 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6574
6575 return 0;
6576 fail_unpin:
6577 i915_gem_object_unpin(obj);
6578 fail_locked:
6579 mutex_unlock(&dev->struct_mutex);
6580 fail:
6581 drm_gem_object_unreference_unlocked(&obj->base);
6582 return ret;
6583 }
6584
6585 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6586 {
6587 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6588
6589 intel_crtc->cursor_x = x;
6590 intel_crtc->cursor_y = y;
6591
6592 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6593
6594 return 0;
6595 }
6596
6597 /** Sets the color ramps on behalf of RandR */
6598 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6599 u16 blue, int regno)
6600 {
6601 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6602
6603 intel_crtc->lut_r[regno] = red >> 8;
6604 intel_crtc->lut_g[regno] = green >> 8;
6605 intel_crtc->lut_b[regno] = blue >> 8;
6606 }
6607
6608 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6609 u16 *blue, int regno)
6610 {
6611 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6612
6613 *red = intel_crtc->lut_r[regno] << 8;
6614 *green = intel_crtc->lut_g[regno] << 8;
6615 *blue = intel_crtc->lut_b[regno] << 8;
6616 }
6617
6618 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6619 u16 *blue, uint32_t start, uint32_t size)
6620 {
6621 int end = (start + size > 256) ? 256 : start + size, i;
6622 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6623
6624 for (i = start; i < end; i++) {
6625 intel_crtc->lut_r[i] = red[i] >> 8;
6626 intel_crtc->lut_g[i] = green[i] >> 8;
6627 intel_crtc->lut_b[i] = blue[i] >> 8;
6628 }
6629
6630 intel_crtc_load_lut(crtc);
6631 }
6632
6633 /* VESA 640x480x72Hz mode to set on the pipe */
6634 static struct drm_display_mode load_detect_mode = {
6635 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6636 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6637 };
6638
6639 static struct drm_framebuffer *
6640 intel_framebuffer_create(struct drm_device *dev,
6641 struct drm_mode_fb_cmd2 *mode_cmd,
6642 struct drm_i915_gem_object *obj)
6643 {
6644 struct intel_framebuffer *intel_fb;
6645 int ret;
6646
6647 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6648 if (!intel_fb) {
6649 drm_gem_object_unreference_unlocked(&obj->base);
6650 return ERR_PTR(-ENOMEM);
6651 }
6652
6653 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6654 if (ret) {
6655 drm_gem_object_unreference_unlocked(&obj->base);
6656 kfree(intel_fb);
6657 return ERR_PTR(ret);
6658 }
6659
6660 return &intel_fb->base;
6661 }
6662
6663 static u32
6664 intel_framebuffer_pitch_for_width(int width, int bpp)
6665 {
6666 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6667 return ALIGN(pitch, 64);
6668 }
6669
6670 static u32
6671 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6672 {
6673 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6674 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6675 }
6676
6677 static struct drm_framebuffer *
6678 intel_framebuffer_create_for_mode(struct drm_device *dev,
6679 struct drm_display_mode *mode,
6680 int depth, int bpp)
6681 {
6682 struct drm_i915_gem_object *obj;
6683 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6684
6685 obj = i915_gem_alloc_object(dev,
6686 intel_framebuffer_size_for_mode(mode, bpp));
6687 if (obj == NULL)
6688 return ERR_PTR(-ENOMEM);
6689
6690 mode_cmd.width = mode->hdisplay;
6691 mode_cmd.height = mode->vdisplay;
6692 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6693 bpp);
6694 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6695
6696 return intel_framebuffer_create(dev, &mode_cmd, obj);
6697 }
6698
6699 static struct drm_framebuffer *
6700 mode_fits_in_fbdev(struct drm_device *dev,
6701 struct drm_display_mode *mode)
6702 {
6703 struct drm_i915_private *dev_priv = dev->dev_private;
6704 struct drm_i915_gem_object *obj;
6705 struct drm_framebuffer *fb;
6706
6707 if (dev_priv->fbdev == NULL)
6708 return NULL;
6709
6710 obj = dev_priv->fbdev->ifb.obj;
6711 if (obj == NULL)
6712 return NULL;
6713
6714 fb = &dev_priv->fbdev->ifb.base;
6715 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6716 fb->bits_per_pixel))
6717 return NULL;
6718
6719 if (obj->base.size < mode->vdisplay * fb->pitches[0])
6720 return NULL;
6721
6722 return fb;
6723 }
6724
6725 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6726 struct drm_display_mode *mode,
6727 struct intel_load_detect_pipe *old)
6728 {
6729 struct intel_crtc *intel_crtc;
6730 struct intel_encoder *intel_encoder =
6731 intel_attached_encoder(connector);
6732 struct drm_crtc *possible_crtc;
6733 struct drm_encoder *encoder = &intel_encoder->base;
6734 struct drm_crtc *crtc = NULL;
6735 struct drm_device *dev = encoder->dev;
6736 struct drm_framebuffer *fb;
6737 int i = -1;
6738
6739 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6740 connector->base.id, drm_get_connector_name(connector),
6741 encoder->base.id, drm_get_encoder_name(encoder));
6742
6743 /*
6744 * Algorithm gets a little messy:
6745 *
6746 * - if the connector already has an assigned crtc, use it (but make
6747 * sure it's on first)
6748 *
6749 * - try to find the first unused crtc that can drive this connector,
6750 * and use that if we find one
6751 */
6752
6753 /* See if we already have a CRTC for this connector */
6754 if (encoder->crtc) {
6755 crtc = encoder->crtc;
6756
6757 mutex_lock(&crtc->mutex);
6758
6759 old->dpms_mode = connector->dpms;
6760 old->load_detect_temp = false;
6761
6762 /* Make sure the crtc and connector are running */
6763 if (connector->dpms != DRM_MODE_DPMS_ON)
6764 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6765
6766 return true;
6767 }
6768
6769 /* Find an unused one (if possible) */
6770 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6771 i++;
6772 if (!(encoder->possible_crtcs & (1 << i)))
6773 continue;
6774 if (!possible_crtc->enabled) {
6775 crtc = possible_crtc;
6776 break;
6777 }
6778 }
6779
6780 /*
6781 * If we didn't find an unused CRTC, don't use any.
6782 */
6783 if (!crtc) {
6784 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6785 return false;
6786 }
6787
6788 mutex_lock(&crtc->mutex);
6789 intel_encoder->new_crtc = to_intel_crtc(crtc);
6790 to_intel_connector(connector)->new_encoder = intel_encoder;
6791
6792 intel_crtc = to_intel_crtc(crtc);
6793 old->dpms_mode = connector->dpms;
6794 old->load_detect_temp = true;
6795 old->release_fb = NULL;
6796
6797 if (!mode)
6798 mode = &load_detect_mode;
6799
6800 /* We need a framebuffer large enough to accommodate all accesses
6801 * that the plane may generate whilst we perform load detection.
6802 * We can not rely on the fbcon either being present (we get called
6803 * during its initialisation to detect all boot displays, or it may
6804 * not even exist) or that it is large enough to satisfy the
6805 * requested mode.
6806 */
6807 fb = mode_fits_in_fbdev(dev, mode);
6808 if (fb == NULL) {
6809 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6810 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6811 old->release_fb = fb;
6812 } else
6813 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6814 if (IS_ERR(fb)) {
6815 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6816 mutex_unlock(&crtc->mutex);
6817 return false;
6818 }
6819
6820 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6821 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6822 if (old->release_fb)
6823 old->release_fb->funcs->destroy(old->release_fb);
6824 mutex_unlock(&crtc->mutex);
6825 return false;
6826 }
6827
6828 /* let the connector get through one full cycle before testing */
6829 intel_wait_for_vblank(dev, intel_crtc->pipe);
6830 return true;
6831 }
6832
6833 void intel_release_load_detect_pipe(struct drm_connector *connector,
6834 struct intel_load_detect_pipe *old)
6835 {
6836 struct intel_encoder *intel_encoder =
6837 intel_attached_encoder(connector);
6838 struct drm_encoder *encoder = &intel_encoder->base;
6839 struct drm_crtc *crtc = encoder->crtc;
6840
6841 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6842 connector->base.id, drm_get_connector_name(connector),
6843 encoder->base.id, drm_get_encoder_name(encoder));
6844
6845 if (old->load_detect_temp) {
6846 to_intel_connector(connector)->new_encoder = NULL;
6847 intel_encoder->new_crtc = NULL;
6848 intel_set_mode(crtc, NULL, 0, 0, NULL);
6849
6850 if (old->release_fb) {
6851 drm_framebuffer_unregister_private(old->release_fb);
6852 drm_framebuffer_unreference(old->release_fb);
6853 }
6854
6855 mutex_unlock(&crtc->mutex);
6856 return;
6857 }
6858
6859 /* Switch crtc and encoder back off if necessary */
6860 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6861 connector->funcs->dpms(connector, old->dpms_mode);
6862
6863 mutex_unlock(&crtc->mutex);
6864 }
6865
6866 /* Returns the clock of the currently programmed mode of the given pipe. */
6867 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6868 {
6869 struct drm_i915_private *dev_priv = dev->dev_private;
6870 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6871 int pipe = intel_crtc->pipe;
6872 u32 dpll = I915_READ(DPLL(pipe));
6873 u32 fp;
6874 intel_clock_t clock;
6875
6876 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6877 fp = I915_READ(FP0(pipe));
6878 else
6879 fp = I915_READ(FP1(pipe));
6880
6881 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6882 if (IS_PINEVIEW(dev)) {
6883 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6884 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6885 } else {
6886 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6887 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6888 }
6889
6890 if (!IS_GEN2(dev)) {
6891 if (IS_PINEVIEW(dev))
6892 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6893 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6894 else
6895 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6896 DPLL_FPA01_P1_POST_DIV_SHIFT);
6897
6898 switch (dpll & DPLL_MODE_MASK) {
6899 case DPLLB_MODE_DAC_SERIAL:
6900 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6901 5 : 10;
6902 break;
6903 case DPLLB_MODE_LVDS:
6904 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6905 7 : 14;
6906 break;
6907 default:
6908 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6909 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6910 return 0;
6911 }
6912
6913 /* XXX: Handle the 100Mhz refclk */
6914 intel_clock(dev, 96000, &clock);
6915 } else {
6916 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6917
6918 if (is_lvds) {
6919 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6920 DPLL_FPA01_P1_POST_DIV_SHIFT);
6921 clock.p2 = 14;
6922
6923 if ((dpll & PLL_REF_INPUT_MASK) ==
6924 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6925 /* XXX: might not be 66MHz */
6926 intel_clock(dev, 66000, &clock);
6927 } else
6928 intel_clock(dev, 48000, &clock);
6929 } else {
6930 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6931 clock.p1 = 2;
6932 else {
6933 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6934 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6935 }
6936 if (dpll & PLL_P2_DIVIDE_BY_4)
6937 clock.p2 = 4;
6938 else
6939 clock.p2 = 2;
6940
6941 intel_clock(dev, 48000, &clock);
6942 }
6943 }
6944
6945 /* XXX: It would be nice to validate the clocks, but we can't reuse
6946 * i830PllIsValid() because it relies on the xf86_config connector
6947 * configuration being accurate, which it isn't necessarily.
6948 */
6949
6950 return clock.dot;
6951 }
6952
6953 /** Returns the currently programmed mode of the given pipe. */
6954 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6955 struct drm_crtc *crtc)
6956 {
6957 struct drm_i915_private *dev_priv = dev->dev_private;
6958 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6959 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6960 struct drm_display_mode *mode;
6961 int htot = I915_READ(HTOTAL(cpu_transcoder));
6962 int hsync = I915_READ(HSYNC(cpu_transcoder));
6963 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6964 int vsync = I915_READ(VSYNC(cpu_transcoder));
6965
6966 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6967 if (!mode)
6968 return NULL;
6969
6970 mode->clock = intel_crtc_clock_get(dev, crtc);
6971 mode->hdisplay = (htot & 0xffff) + 1;
6972 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6973 mode->hsync_start = (hsync & 0xffff) + 1;
6974 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6975 mode->vdisplay = (vtot & 0xffff) + 1;
6976 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6977 mode->vsync_start = (vsync & 0xffff) + 1;
6978 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6979
6980 drm_mode_set_name(mode);
6981
6982 return mode;
6983 }
6984
6985 static void intel_increase_pllclock(struct drm_crtc *crtc)
6986 {
6987 struct drm_device *dev = crtc->dev;
6988 drm_i915_private_t *dev_priv = dev->dev_private;
6989 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6990 int pipe = intel_crtc->pipe;
6991 int dpll_reg = DPLL(pipe);
6992 int dpll;
6993
6994 if (HAS_PCH_SPLIT(dev))
6995 return;
6996
6997 if (!dev_priv->lvds_downclock_avail)
6998 return;
6999
7000 dpll = I915_READ(dpll_reg);
7001 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7002 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7003
7004 assert_panel_unlocked(dev_priv, pipe);
7005
7006 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7007 I915_WRITE(dpll_reg, dpll);
7008 intel_wait_for_vblank(dev, pipe);
7009
7010 dpll = I915_READ(dpll_reg);
7011 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7012 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7013 }
7014 }
7015
7016 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7017 {
7018 struct drm_device *dev = crtc->dev;
7019 drm_i915_private_t *dev_priv = dev->dev_private;
7020 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7021
7022 if (HAS_PCH_SPLIT(dev))
7023 return;
7024
7025 if (!dev_priv->lvds_downclock_avail)
7026 return;
7027
7028 /*
7029 * Since this is called by a timer, we should never get here in
7030 * the manual case.
7031 */
7032 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7033 int pipe = intel_crtc->pipe;
7034 int dpll_reg = DPLL(pipe);
7035 int dpll;
7036
7037 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7038
7039 assert_panel_unlocked(dev_priv, pipe);
7040
7041 dpll = I915_READ(dpll_reg);
7042 dpll |= DISPLAY_RATE_SELECT_FPA1;
7043 I915_WRITE(dpll_reg, dpll);
7044 intel_wait_for_vblank(dev, pipe);
7045 dpll = I915_READ(dpll_reg);
7046 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7047 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7048 }
7049
7050 }
7051
7052 void intel_mark_busy(struct drm_device *dev)
7053 {
7054 i915_update_gfx_val(dev->dev_private);
7055 }
7056
7057 void intel_mark_idle(struct drm_device *dev)
7058 {
7059 struct drm_crtc *crtc;
7060
7061 if (!i915_powersave)
7062 return;
7063
7064 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7065 if (!crtc->fb)
7066 continue;
7067
7068 intel_decrease_pllclock(crtc);
7069 }
7070 }
7071
7072 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
7073 {
7074 struct drm_device *dev = obj->base.dev;
7075 struct drm_crtc *crtc;
7076
7077 if (!i915_powersave)
7078 return;
7079
7080 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7081 if (!crtc->fb)
7082 continue;
7083
7084 if (to_intel_framebuffer(crtc->fb)->obj == obj)
7085 intel_increase_pllclock(crtc);
7086 }
7087 }
7088
7089 static void intel_crtc_destroy(struct drm_crtc *crtc)
7090 {
7091 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7092 struct drm_device *dev = crtc->dev;
7093 struct intel_unpin_work *work;
7094 unsigned long flags;
7095
7096 spin_lock_irqsave(&dev->event_lock, flags);
7097 work = intel_crtc->unpin_work;
7098 intel_crtc->unpin_work = NULL;
7099 spin_unlock_irqrestore(&dev->event_lock, flags);
7100
7101 if (work) {
7102 cancel_work_sync(&work->work);
7103 kfree(work);
7104 }
7105
7106 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7107
7108 drm_crtc_cleanup(crtc);
7109
7110 kfree(intel_crtc);
7111 }
7112
7113 static void intel_unpin_work_fn(struct work_struct *__work)
7114 {
7115 struct intel_unpin_work *work =
7116 container_of(__work, struct intel_unpin_work, work);
7117 struct drm_device *dev = work->crtc->dev;
7118
7119 mutex_lock(&dev->struct_mutex);
7120 intel_unpin_fb_obj(work->old_fb_obj);
7121 drm_gem_object_unreference(&work->pending_flip_obj->base);
7122 drm_gem_object_unreference(&work->old_fb_obj->base);
7123
7124 intel_update_fbc(dev);
7125 mutex_unlock(&dev->struct_mutex);
7126
7127 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7128 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7129
7130 kfree(work);
7131 }
7132
7133 static void do_intel_finish_page_flip(struct drm_device *dev,
7134 struct drm_crtc *crtc)
7135 {
7136 drm_i915_private_t *dev_priv = dev->dev_private;
7137 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7138 struct intel_unpin_work *work;
7139 unsigned long flags;
7140
7141 /* Ignore early vblank irqs */
7142 if (intel_crtc == NULL)
7143 return;
7144
7145 spin_lock_irqsave(&dev->event_lock, flags);
7146 work = intel_crtc->unpin_work;
7147
7148 /* Ensure we don't miss a work->pending update ... */
7149 smp_rmb();
7150
7151 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7152 spin_unlock_irqrestore(&dev->event_lock, flags);
7153 return;
7154 }
7155
7156 /* and that the unpin work is consistent wrt ->pending. */
7157 smp_rmb();
7158
7159 intel_crtc->unpin_work = NULL;
7160
7161 if (work->event)
7162 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7163
7164 drm_vblank_put(dev, intel_crtc->pipe);
7165
7166 spin_unlock_irqrestore(&dev->event_lock, flags);
7167
7168 wake_up_all(&dev_priv->pending_flip_queue);
7169
7170 queue_work(dev_priv->wq, &work->work);
7171
7172 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7173 }
7174
7175 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7176 {
7177 drm_i915_private_t *dev_priv = dev->dev_private;
7178 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7179
7180 do_intel_finish_page_flip(dev, crtc);
7181 }
7182
7183 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7184 {
7185 drm_i915_private_t *dev_priv = dev->dev_private;
7186 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7187
7188 do_intel_finish_page_flip(dev, crtc);
7189 }
7190
7191 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7192 {
7193 drm_i915_private_t *dev_priv = dev->dev_private;
7194 struct intel_crtc *intel_crtc =
7195 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7196 unsigned long flags;
7197
7198 /* NB: An MMIO update of the plane base pointer will also
7199 * generate a page-flip completion irq, i.e. every modeset
7200 * is also accompanied by a spurious intel_prepare_page_flip().
7201 */
7202 spin_lock_irqsave(&dev->event_lock, flags);
7203 if (intel_crtc->unpin_work)
7204 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7205 spin_unlock_irqrestore(&dev->event_lock, flags);
7206 }
7207
7208 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7209 {
7210 /* Ensure that the work item is consistent when activating it ... */
7211 smp_wmb();
7212 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7213 /* and that it is marked active as soon as the irq could fire. */
7214 smp_wmb();
7215 }
7216
7217 static int intel_gen2_queue_flip(struct drm_device *dev,
7218 struct drm_crtc *crtc,
7219 struct drm_framebuffer *fb,
7220 struct drm_i915_gem_object *obj)
7221 {
7222 struct drm_i915_private *dev_priv = dev->dev_private;
7223 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7224 u32 flip_mask;
7225 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7226 int ret;
7227
7228 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7229 if (ret)
7230 goto err;
7231
7232 ret = intel_ring_begin(ring, 6);
7233 if (ret)
7234 goto err_unpin;
7235
7236 /* Can't queue multiple flips, so wait for the previous
7237 * one to finish before executing the next.
7238 */
7239 if (intel_crtc->plane)
7240 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7241 else
7242 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7243 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7244 intel_ring_emit(ring, MI_NOOP);
7245 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7246 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7247 intel_ring_emit(ring, fb->pitches[0]);
7248 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7249 intel_ring_emit(ring, 0); /* aux display base address, unused */
7250
7251 intel_mark_page_flip_active(intel_crtc);
7252 intel_ring_advance(ring);
7253 return 0;
7254
7255 err_unpin:
7256 intel_unpin_fb_obj(obj);
7257 err:
7258 return ret;
7259 }
7260
7261 static int intel_gen3_queue_flip(struct drm_device *dev,
7262 struct drm_crtc *crtc,
7263 struct drm_framebuffer *fb,
7264 struct drm_i915_gem_object *obj)
7265 {
7266 struct drm_i915_private *dev_priv = dev->dev_private;
7267 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7268 u32 flip_mask;
7269 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7270 int ret;
7271
7272 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7273 if (ret)
7274 goto err;
7275
7276 ret = intel_ring_begin(ring, 6);
7277 if (ret)
7278 goto err_unpin;
7279
7280 if (intel_crtc->plane)
7281 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7282 else
7283 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7284 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7285 intel_ring_emit(ring, MI_NOOP);
7286 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7287 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7288 intel_ring_emit(ring, fb->pitches[0]);
7289 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7290 intel_ring_emit(ring, MI_NOOP);
7291
7292 intel_mark_page_flip_active(intel_crtc);
7293 intel_ring_advance(ring);
7294 return 0;
7295
7296 err_unpin:
7297 intel_unpin_fb_obj(obj);
7298 err:
7299 return ret;
7300 }
7301
7302 static int intel_gen4_queue_flip(struct drm_device *dev,
7303 struct drm_crtc *crtc,
7304 struct drm_framebuffer *fb,
7305 struct drm_i915_gem_object *obj)
7306 {
7307 struct drm_i915_private *dev_priv = dev->dev_private;
7308 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7309 uint32_t pf, pipesrc;
7310 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7311 int ret;
7312
7313 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7314 if (ret)
7315 goto err;
7316
7317 ret = intel_ring_begin(ring, 4);
7318 if (ret)
7319 goto err_unpin;
7320
7321 /* i965+ uses the linear or tiled offsets from the
7322 * Display Registers (which do not change across a page-flip)
7323 * so we need only reprogram the base address.
7324 */
7325 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7326 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7327 intel_ring_emit(ring, fb->pitches[0]);
7328 intel_ring_emit(ring,
7329 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7330 obj->tiling_mode);
7331
7332 /* XXX Enabling the panel-fitter across page-flip is so far
7333 * untested on non-native modes, so ignore it for now.
7334 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7335 */
7336 pf = 0;
7337 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7338 intel_ring_emit(ring, pf | pipesrc);
7339
7340 intel_mark_page_flip_active(intel_crtc);
7341 intel_ring_advance(ring);
7342 return 0;
7343
7344 err_unpin:
7345 intel_unpin_fb_obj(obj);
7346 err:
7347 return ret;
7348 }
7349
7350 static int intel_gen6_queue_flip(struct drm_device *dev,
7351 struct drm_crtc *crtc,
7352 struct drm_framebuffer *fb,
7353 struct drm_i915_gem_object *obj)
7354 {
7355 struct drm_i915_private *dev_priv = dev->dev_private;
7356 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7357 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7358 uint32_t pf, pipesrc;
7359 int ret;
7360
7361 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7362 if (ret)
7363 goto err;
7364
7365 ret = intel_ring_begin(ring, 4);
7366 if (ret)
7367 goto err_unpin;
7368
7369 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7370 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7371 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7372 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7373
7374 /* Contrary to the suggestions in the documentation,
7375 * "Enable Panel Fitter" does not seem to be required when page
7376 * flipping with a non-native mode, and worse causes a normal
7377 * modeset to fail.
7378 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7379 */
7380 pf = 0;
7381 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7382 intel_ring_emit(ring, pf | pipesrc);
7383
7384 intel_mark_page_flip_active(intel_crtc);
7385 intel_ring_advance(ring);
7386 return 0;
7387
7388 err_unpin:
7389 intel_unpin_fb_obj(obj);
7390 err:
7391 return ret;
7392 }
7393
7394 /*
7395 * On gen7 we currently use the blit ring because (in early silicon at least)
7396 * the render ring doesn't give us interrpts for page flip completion, which
7397 * means clients will hang after the first flip is queued. Fortunately the
7398 * blit ring generates interrupts properly, so use it instead.
7399 */
7400 static int intel_gen7_queue_flip(struct drm_device *dev,
7401 struct drm_crtc *crtc,
7402 struct drm_framebuffer *fb,
7403 struct drm_i915_gem_object *obj)
7404 {
7405 struct drm_i915_private *dev_priv = dev->dev_private;
7406 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7407 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7408 uint32_t plane_bit = 0;
7409 int ret;
7410
7411 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7412 if (ret)
7413 goto err;
7414
7415 switch(intel_crtc->plane) {
7416 case PLANE_A:
7417 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7418 break;
7419 case PLANE_B:
7420 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7421 break;
7422 case PLANE_C:
7423 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7424 break;
7425 default:
7426 WARN_ONCE(1, "unknown plane in flip command\n");
7427 ret = -ENODEV;
7428 goto err_unpin;
7429 }
7430
7431 ret = intel_ring_begin(ring, 4);
7432 if (ret)
7433 goto err_unpin;
7434
7435 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7436 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7437 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7438 intel_ring_emit(ring, (MI_NOOP));
7439
7440 intel_mark_page_flip_active(intel_crtc);
7441 intel_ring_advance(ring);
7442 return 0;
7443
7444 err_unpin:
7445 intel_unpin_fb_obj(obj);
7446 err:
7447 return ret;
7448 }
7449
7450 static int intel_default_queue_flip(struct drm_device *dev,
7451 struct drm_crtc *crtc,
7452 struct drm_framebuffer *fb,
7453 struct drm_i915_gem_object *obj)
7454 {
7455 return -ENODEV;
7456 }
7457
7458 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7459 struct drm_framebuffer *fb,
7460 struct drm_pending_vblank_event *event)
7461 {
7462 struct drm_device *dev = crtc->dev;
7463 struct drm_i915_private *dev_priv = dev->dev_private;
7464 struct drm_framebuffer *old_fb = crtc->fb;
7465 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7466 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7467 struct intel_unpin_work *work;
7468 unsigned long flags;
7469 int ret;
7470
7471 /* Can't change pixel format via MI display flips. */
7472 if (fb->pixel_format != crtc->fb->pixel_format)
7473 return -EINVAL;
7474
7475 /*
7476 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7477 * Note that pitch changes could also affect these register.
7478 */
7479 if (INTEL_INFO(dev)->gen > 3 &&
7480 (fb->offsets[0] != crtc->fb->offsets[0] ||
7481 fb->pitches[0] != crtc->fb->pitches[0]))
7482 return -EINVAL;
7483
7484 work = kzalloc(sizeof *work, GFP_KERNEL);
7485 if (work == NULL)
7486 return -ENOMEM;
7487
7488 work->event = event;
7489 work->crtc = crtc;
7490 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7491 INIT_WORK(&work->work, intel_unpin_work_fn);
7492
7493 ret = drm_vblank_get(dev, intel_crtc->pipe);
7494 if (ret)
7495 goto free_work;
7496
7497 /* We borrow the event spin lock for protecting unpin_work */
7498 spin_lock_irqsave(&dev->event_lock, flags);
7499 if (intel_crtc->unpin_work) {
7500 spin_unlock_irqrestore(&dev->event_lock, flags);
7501 kfree(work);
7502 drm_vblank_put(dev, intel_crtc->pipe);
7503
7504 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7505 return -EBUSY;
7506 }
7507 intel_crtc->unpin_work = work;
7508 spin_unlock_irqrestore(&dev->event_lock, flags);
7509
7510 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7511 flush_workqueue(dev_priv->wq);
7512
7513 ret = i915_mutex_lock_interruptible(dev);
7514 if (ret)
7515 goto cleanup;
7516
7517 /* Reference the objects for the scheduled work. */
7518 drm_gem_object_reference(&work->old_fb_obj->base);
7519 drm_gem_object_reference(&obj->base);
7520
7521 crtc->fb = fb;
7522
7523 work->pending_flip_obj = obj;
7524
7525 work->enable_stall_check = true;
7526
7527 atomic_inc(&intel_crtc->unpin_work_count);
7528 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7529
7530 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7531 if (ret)
7532 goto cleanup_pending;
7533
7534 intel_disable_fbc(dev);
7535 intel_mark_fb_busy(obj);
7536 mutex_unlock(&dev->struct_mutex);
7537
7538 trace_i915_flip_request(intel_crtc->plane, obj);
7539
7540 return 0;
7541
7542 cleanup_pending:
7543 atomic_dec(&intel_crtc->unpin_work_count);
7544 crtc->fb = old_fb;
7545 drm_gem_object_unreference(&work->old_fb_obj->base);
7546 drm_gem_object_unreference(&obj->base);
7547 mutex_unlock(&dev->struct_mutex);
7548
7549 cleanup:
7550 spin_lock_irqsave(&dev->event_lock, flags);
7551 intel_crtc->unpin_work = NULL;
7552 spin_unlock_irqrestore(&dev->event_lock, flags);
7553
7554 drm_vblank_put(dev, intel_crtc->pipe);
7555 free_work:
7556 kfree(work);
7557
7558 return ret;
7559 }
7560
7561 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7562 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7563 .load_lut = intel_crtc_load_lut,
7564 };
7565
7566 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7567 {
7568 struct intel_encoder *other_encoder;
7569 struct drm_crtc *crtc = &encoder->new_crtc->base;
7570
7571 if (WARN_ON(!crtc))
7572 return false;
7573
7574 list_for_each_entry(other_encoder,
7575 &crtc->dev->mode_config.encoder_list,
7576 base.head) {
7577
7578 if (&other_encoder->new_crtc->base != crtc ||
7579 encoder == other_encoder)
7580 continue;
7581 else
7582 return true;
7583 }
7584
7585 return false;
7586 }
7587
7588 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7589 struct drm_crtc *crtc)
7590 {
7591 struct drm_device *dev;
7592 struct drm_crtc *tmp;
7593 int crtc_mask = 1;
7594
7595 WARN(!crtc, "checking null crtc?\n");
7596
7597 dev = crtc->dev;
7598
7599 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7600 if (tmp == crtc)
7601 break;
7602 crtc_mask <<= 1;
7603 }
7604
7605 if (encoder->possible_crtcs & crtc_mask)
7606 return true;
7607 return false;
7608 }
7609
7610 /**
7611 * intel_modeset_update_staged_output_state
7612 *
7613 * Updates the staged output configuration state, e.g. after we've read out the
7614 * current hw state.
7615 */
7616 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7617 {
7618 struct intel_encoder *encoder;
7619 struct intel_connector *connector;
7620
7621 list_for_each_entry(connector, &dev->mode_config.connector_list,
7622 base.head) {
7623 connector->new_encoder =
7624 to_intel_encoder(connector->base.encoder);
7625 }
7626
7627 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7628 base.head) {
7629 encoder->new_crtc =
7630 to_intel_crtc(encoder->base.crtc);
7631 }
7632 }
7633
7634 /**
7635 * intel_modeset_commit_output_state
7636 *
7637 * This function copies the stage display pipe configuration to the real one.
7638 */
7639 static void intel_modeset_commit_output_state(struct drm_device *dev)
7640 {
7641 struct intel_encoder *encoder;
7642 struct intel_connector *connector;
7643
7644 list_for_each_entry(connector, &dev->mode_config.connector_list,
7645 base.head) {
7646 connector->base.encoder = &connector->new_encoder->base;
7647 }
7648
7649 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7650 base.head) {
7651 encoder->base.crtc = &encoder->new_crtc->base;
7652 }
7653 }
7654
7655 static int
7656 pipe_config_set_bpp(struct drm_crtc *crtc,
7657 struct drm_framebuffer *fb,
7658 struct intel_crtc_config *pipe_config)
7659 {
7660 struct drm_device *dev = crtc->dev;
7661 struct drm_connector *connector;
7662 int bpp;
7663
7664 switch (fb->pixel_format) {
7665 case DRM_FORMAT_C8:
7666 bpp = 8*3; /* since we go through a colormap */
7667 break;
7668 case DRM_FORMAT_XRGB1555:
7669 case DRM_FORMAT_ARGB1555:
7670 /* checked in intel_framebuffer_init already */
7671 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7672 return -EINVAL;
7673 case DRM_FORMAT_RGB565:
7674 bpp = 6*3; /* min is 18bpp */
7675 break;
7676 case DRM_FORMAT_XBGR8888:
7677 case DRM_FORMAT_ABGR8888:
7678 /* checked in intel_framebuffer_init already */
7679 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7680 return -EINVAL;
7681 case DRM_FORMAT_XRGB8888:
7682 case DRM_FORMAT_ARGB8888:
7683 bpp = 8*3;
7684 break;
7685 case DRM_FORMAT_XRGB2101010:
7686 case DRM_FORMAT_ARGB2101010:
7687 case DRM_FORMAT_XBGR2101010:
7688 case DRM_FORMAT_ABGR2101010:
7689 /* checked in intel_framebuffer_init already */
7690 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7691 return -EINVAL;
7692 bpp = 10*3;
7693 break;
7694 /* TODO: gen4+ supports 16 bpc floating point, too. */
7695 default:
7696 DRM_DEBUG_KMS("unsupported depth\n");
7697 return -EINVAL;
7698 }
7699
7700 pipe_config->pipe_bpp = bpp;
7701
7702 /* Clamp display bpp to EDID value */
7703 list_for_each_entry(connector, &dev->mode_config.connector_list,
7704 head) {
7705 if (connector->encoder && connector->encoder->crtc != crtc)
7706 continue;
7707
7708 /* Don't use an invalid EDID bpc value */
7709 if (connector->display_info.bpc &&
7710 connector->display_info.bpc * 3 < bpp) {
7711 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7712 bpp, connector->display_info.bpc*3);
7713 pipe_config->pipe_bpp = connector->display_info.bpc*3;
7714 }
7715
7716 /* Clamp bpp to 8 on screens without EDID 1.4 */
7717 if (connector->display_info.bpc == 0 && bpp > 24) {
7718 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7719 bpp);
7720 pipe_config->pipe_bpp = 24;
7721 }
7722 }
7723
7724 return bpp;
7725 }
7726
7727 static void intel_dump_pipe_config(struct intel_crtc *crtc,
7728 struct intel_crtc_config *pipe_config,
7729 const char *context)
7730 {
7731 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7732 context, pipe_name(crtc->pipe));
7733
7734 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7735 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7736 pipe_config->pipe_bpp, pipe_config->dither);
7737 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7738 pipe_config->has_pch_encoder,
7739 pipe_config->fdi_lanes,
7740 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7741 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7742 pipe_config->fdi_m_n.tu);
7743 DRM_DEBUG_KMS("requested mode:\n");
7744 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7745 DRM_DEBUG_KMS("adjusted mode:\n");
7746 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7747 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7748 pipe_config->gmch_pfit.control,
7749 pipe_config->gmch_pfit.pgm_ratios,
7750 pipe_config->gmch_pfit.lvds_border_bits);
7751 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7752 pipe_config->pch_pfit.pos,
7753 pipe_config->pch_pfit.size);
7754 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
7755 }
7756
7757 static struct intel_crtc_config *
7758 intel_modeset_pipe_config(struct drm_crtc *crtc,
7759 struct drm_framebuffer *fb,
7760 struct drm_display_mode *mode)
7761 {
7762 struct drm_device *dev = crtc->dev;
7763 struct drm_encoder_helper_funcs *encoder_funcs;
7764 struct intel_encoder *encoder;
7765 struct intel_crtc_config *pipe_config;
7766 int plane_bpp, ret = -EINVAL;
7767 bool retry = true;
7768
7769 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7770 if (!pipe_config)
7771 return ERR_PTR(-ENOMEM);
7772
7773 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7774 drm_mode_copy(&pipe_config->requested_mode, mode);
7775 pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe;
7776
7777 plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
7778 if (plane_bpp < 0)
7779 goto fail;
7780
7781 encoder_retry:
7782 /* Pass our mode to the connectors and the CRTC to give them a chance to
7783 * adjust it according to limitations or connector properties, and also
7784 * a chance to reject the mode entirely.
7785 */
7786 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7787 base.head) {
7788
7789 if (&encoder->new_crtc->base != crtc)
7790 continue;
7791
7792 if (encoder->compute_config) {
7793 if (!(encoder->compute_config(encoder, pipe_config))) {
7794 DRM_DEBUG_KMS("Encoder config failure\n");
7795 goto fail;
7796 }
7797
7798 continue;
7799 }
7800
7801 encoder_funcs = encoder->base.helper_private;
7802 if (!(encoder_funcs->mode_fixup(&encoder->base,
7803 &pipe_config->requested_mode,
7804 &pipe_config->adjusted_mode))) {
7805 DRM_DEBUG_KMS("Encoder fixup failed\n");
7806 goto fail;
7807 }
7808 }
7809
7810 ret = intel_crtc_compute_config(crtc, pipe_config);
7811 if (ret < 0) {
7812 DRM_DEBUG_KMS("CRTC fixup failed\n");
7813 goto fail;
7814 }
7815
7816 if (ret == RETRY) {
7817 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7818 ret = -EINVAL;
7819 goto fail;
7820 }
7821
7822 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7823 retry = false;
7824 goto encoder_retry;
7825 }
7826
7827 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7828 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7829 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7830
7831 return pipe_config;
7832 fail:
7833 kfree(pipe_config);
7834 return ERR_PTR(ret);
7835 }
7836
7837 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7838 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7839 static void
7840 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7841 unsigned *prepare_pipes, unsigned *disable_pipes)
7842 {
7843 struct intel_crtc *intel_crtc;
7844 struct drm_device *dev = crtc->dev;
7845 struct intel_encoder *encoder;
7846 struct intel_connector *connector;
7847 struct drm_crtc *tmp_crtc;
7848
7849 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7850
7851 /* Check which crtcs have changed outputs connected to them, these need
7852 * to be part of the prepare_pipes mask. We don't (yet) support global
7853 * modeset across multiple crtcs, so modeset_pipes will only have one
7854 * bit set at most. */
7855 list_for_each_entry(connector, &dev->mode_config.connector_list,
7856 base.head) {
7857 if (connector->base.encoder == &connector->new_encoder->base)
7858 continue;
7859
7860 if (connector->base.encoder) {
7861 tmp_crtc = connector->base.encoder->crtc;
7862
7863 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7864 }
7865
7866 if (connector->new_encoder)
7867 *prepare_pipes |=
7868 1 << connector->new_encoder->new_crtc->pipe;
7869 }
7870
7871 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7872 base.head) {
7873 if (encoder->base.crtc == &encoder->new_crtc->base)
7874 continue;
7875
7876 if (encoder->base.crtc) {
7877 tmp_crtc = encoder->base.crtc;
7878
7879 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7880 }
7881
7882 if (encoder->new_crtc)
7883 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7884 }
7885
7886 /* Check for any pipes that will be fully disabled ... */
7887 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7888 base.head) {
7889 bool used = false;
7890
7891 /* Don't try to disable disabled crtcs. */
7892 if (!intel_crtc->base.enabled)
7893 continue;
7894
7895 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7896 base.head) {
7897 if (encoder->new_crtc == intel_crtc)
7898 used = true;
7899 }
7900
7901 if (!used)
7902 *disable_pipes |= 1 << intel_crtc->pipe;
7903 }
7904
7905
7906 /* set_mode is also used to update properties on life display pipes. */
7907 intel_crtc = to_intel_crtc(crtc);
7908 if (crtc->enabled)
7909 *prepare_pipes |= 1 << intel_crtc->pipe;
7910
7911 /*
7912 * For simplicity do a full modeset on any pipe where the output routing
7913 * changed. We could be more clever, but that would require us to be
7914 * more careful with calling the relevant encoder->mode_set functions.
7915 */
7916 if (*prepare_pipes)
7917 *modeset_pipes = *prepare_pipes;
7918
7919 /* ... and mask these out. */
7920 *modeset_pipes &= ~(*disable_pipes);
7921 *prepare_pipes &= ~(*disable_pipes);
7922
7923 /*
7924 * HACK: We don't (yet) fully support global modesets. intel_set_config
7925 * obies this rule, but the modeset restore mode of
7926 * intel_modeset_setup_hw_state does not.
7927 */
7928 *modeset_pipes &= 1 << intel_crtc->pipe;
7929 *prepare_pipes &= 1 << intel_crtc->pipe;
7930
7931 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7932 *modeset_pipes, *prepare_pipes, *disable_pipes);
7933 }
7934
7935 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7936 {
7937 struct drm_encoder *encoder;
7938 struct drm_device *dev = crtc->dev;
7939
7940 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7941 if (encoder->crtc == crtc)
7942 return true;
7943
7944 return false;
7945 }
7946
7947 static void
7948 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7949 {
7950 struct intel_encoder *intel_encoder;
7951 struct intel_crtc *intel_crtc;
7952 struct drm_connector *connector;
7953
7954 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7955 base.head) {
7956 if (!intel_encoder->base.crtc)
7957 continue;
7958
7959 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7960
7961 if (prepare_pipes & (1 << intel_crtc->pipe))
7962 intel_encoder->connectors_active = false;
7963 }
7964
7965 intel_modeset_commit_output_state(dev);
7966
7967 /* Update computed state. */
7968 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7969 base.head) {
7970 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7971 }
7972
7973 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7974 if (!connector->encoder || !connector->encoder->crtc)
7975 continue;
7976
7977 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7978
7979 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7980 struct drm_property *dpms_property =
7981 dev->mode_config.dpms_property;
7982
7983 connector->dpms = DRM_MODE_DPMS_ON;
7984 drm_object_property_set_value(&connector->base,
7985 dpms_property,
7986 DRM_MODE_DPMS_ON);
7987
7988 intel_encoder = to_intel_encoder(connector->encoder);
7989 intel_encoder->connectors_active = true;
7990 }
7991 }
7992
7993 }
7994
7995 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7996 list_for_each_entry((intel_crtc), \
7997 &(dev)->mode_config.crtc_list, \
7998 base.head) \
7999 if (mask & (1 <<(intel_crtc)->pipe))
8000
8001 static bool
8002 intel_pipe_config_compare(struct drm_device *dev,
8003 struct intel_crtc_config *current_config,
8004 struct intel_crtc_config *pipe_config)
8005 {
8006 #define PIPE_CONF_CHECK_I(name) \
8007 if (current_config->name != pipe_config->name) { \
8008 DRM_ERROR("mismatch in " #name " " \
8009 "(expected %i, found %i)\n", \
8010 current_config->name, \
8011 pipe_config->name); \
8012 return false; \
8013 }
8014
8015 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
8016 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8017 DRM_ERROR("mismatch in " #name " " \
8018 "(expected %i, found %i)\n", \
8019 current_config->name & (mask), \
8020 pipe_config->name & (mask)); \
8021 return false; \
8022 }
8023
8024 PIPE_CONF_CHECK_I(cpu_transcoder);
8025
8026 PIPE_CONF_CHECK_I(has_pch_encoder);
8027 PIPE_CONF_CHECK_I(fdi_lanes);
8028 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8029 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8030 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8031 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8032 PIPE_CONF_CHECK_I(fdi_m_n.tu);
8033
8034 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8035 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8036 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8037 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8038 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8039 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8040
8041 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8042 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8043 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8044 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8045 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8046 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8047
8048 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8049 DRM_MODE_FLAG_INTERLACE);
8050
8051 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8052 DRM_MODE_FLAG_PHSYNC);
8053 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8054 DRM_MODE_FLAG_NHSYNC);
8055 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8056 DRM_MODE_FLAG_PVSYNC);
8057 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8058 DRM_MODE_FLAG_NVSYNC);
8059
8060 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8061 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8062
8063 PIPE_CONF_CHECK_I(gmch_pfit.control);
8064 /* pfit ratios are autocomputed by the hw on gen4+ */
8065 if (INTEL_INFO(dev)->gen < 4)
8066 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8067 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8068 PIPE_CONF_CHECK_I(pch_pfit.pos);
8069 PIPE_CONF_CHECK_I(pch_pfit.size);
8070
8071 PIPE_CONF_CHECK_I(ips_enabled);
8072
8073 #undef PIPE_CONF_CHECK_I
8074 #undef PIPE_CONF_CHECK_FLAGS
8075
8076 return true;
8077 }
8078
8079 void
8080 intel_modeset_check_state(struct drm_device *dev)
8081 {
8082 drm_i915_private_t *dev_priv = dev->dev_private;
8083 struct intel_crtc *crtc;
8084 struct intel_encoder *encoder;
8085 struct intel_connector *connector;
8086 struct intel_crtc_config pipe_config;
8087
8088 list_for_each_entry(connector, &dev->mode_config.connector_list,
8089 base.head) {
8090 /* This also checks the encoder/connector hw state with the
8091 * ->get_hw_state callbacks. */
8092 intel_connector_check_state(connector);
8093
8094 WARN(&connector->new_encoder->base != connector->base.encoder,
8095 "connector's staged encoder doesn't match current encoder\n");
8096 }
8097
8098 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8099 base.head) {
8100 bool enabled = false;
8101 bool active = false;
8102 enum pipe pipe, tracked_pipe;
8103
8104 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8105 encoder->base.base.id,
8106 drm_get_encoder_name(&encoder->base));
8107
8108 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8109 "encoder's stage crtc doesn't match current crtc\n");
8110 WARN(encoder->connectors_active && !encoder->base.crtc,
8111 "encoder's active_connectors set, but no crtc\n");
8112
8113 list_for_each_entry(connector, &dev->mode_config.connector_list,
8114 base.head) {
8115 if (connector->base.encoder != &encoder->base)
8116 continue;
8117 enabled = true;
8118 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8119 active = true;
8120 }
8121 WARN(!!encoder->base.crtc != enabled,
8122 "encoder's enabled state mismatch "
8123 "(expected %i, found %i)\n",
8124 !!encoder->base.crtc, enabled);
8125 WARN(active && !encoder->base.crtc,
8126 "active encoder with no crtc\n");
8127
8128 WARN(encoder->connectors_active != active,
8129 "encoder's computed active state doesn't match tracked active state "
8130 "(expected %i, found %i)\n", active, encoder->connectors_active);
8131
8132 active = encoder->get_hw_state(encoder, &pipe);
8133 WARN(active != encoder->connectors_active,
8134 "encoder's hw state doesn't match sw tracking "
8135 "(expected %i, found %i)\n",
8136 encoder->connectors_active, active);
8137
8138 if (!encoder->base.crtc)
8139 continue;
8140
8141 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8142 WARN(active && pipe != tracked_pipe,
8143 "active encoder's pipe doesn't match"
8144 "(expected %i, found %i)\n",
8145 tracked_pipe, pipe);
8146
8147 }
8148
8149 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8150 base.head) {
8151 bool enabled = false;
8152 bool active = false;
8153
8154 memset(&pipe_config, 0, sizeof(pipe_config));
8155
8156 DRM_DEBUG_KMS("[CRTC:%d]\n",
8157 crtc->base.base.id);
8158
8159 WARN(crtc->active && !crtc->base.enabled,
8160 "active crtc, but not enabled in sw tracking\n");
8161
8162 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8163 base.head) {
8164 if (encoder->base.crtc != &crtc->base)
8165 continue;
8166 enabled = true;
8167 if (encoder->connectors_active)
8168 active = true;
8169 if (encoder->get_config)
8170 encoder->get_config(encoder, &pipe_config);
8171 }
8172 WARN(active != crtc->active,
8173 "crtc's computed active state doesn't match tracked active state "
8174 "(expected %i, found %i)\n", active, crtc->active);
8175 WARN(enabled != crtc->base.enabled,
8176 "crtc's computed enabled state doesn't match tracked enabled state "
8177 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8178
8179 active = dev_priv->display.get_pipe_config(crtc,
8180 &pipe_config);
8181 WARN(crtc->active != active,
8182 "crtc active state doesn't match with hw state "
8183 "(expected %i, found %i)\n", crtc->active, active);
8184
8185 if (active &&
8186 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8187 WARN(1, "pipe state doesn't match!\n");
8188 intel_dump_pipe_config(crtc, &pipe_config,
8189 "[hw state]");
8190 intel_dump_pipe_config(crtc, &crtc->config,
8191 "[sw state]");
8192 }
8193 }
8194 }
8195
8196 static int __intel_set_mode(struct drm_crtc *crtc,
8197 struct drm_display_mode *mode,
8198 int x, int y, struct drm_framebuffer *fb)
8199 {
8200 struct drm_device *dev = crtc->dev;
8201 drm_i915_private_t *dev_priv = dev->dev_private;
8202 struct drm_display_mode *saved_mode, *saved_hwmode;
8203 struct intel_crtc_config *pipe_config = NULL;
8204 struct intel_crtc *intel_crtc;
8205 unsigned disable_pipes, prepare_pipes, modeset_pipes;
8206 int ret = 0;
8207
8208 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
8209 if (!saved_mode)
8210 return -ENOMEM;
8211 saved_hwmode = saved_mode + 1;
8212
8213 intel_modeset_affected_pipes(crtc, &modeset_pipes,
8214 &prepare_pipes, &disable_pipes);
8215
8216 *saved_hwmode = crtc->hwmode;
8217 *saved_mode = crtc->mode;
8218
8219 /* Hack: Because we don't (yet) support global modeset on multiple
8220 * crtcs, we don't keep track of the new mode for more than one crtc.
8221 * Hence simply check whether any bit is set in modeset_pipes in all the
8222 * pieces of code that are not yet converted to deal with mutliple crtcs
8223 * changing their mode at the same time. */
8224 if (modeset_pipes) {
8225 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8226 if (IS_ERR(pipe_config)) {
8227 ret = PTR_ERR(pipe_config);
8228 pipe_config = NULL;
8229
8230 goto out;
8231 }
8232 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8233 "[modeset]");
8234 }
8235
8236 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8237 intel_crtc_disable(&intel_crtc->base);
8238
8239 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8240 if (intel_crtc->base.enabled)
8241 dev_priv->display.crtc_disable(&intel_crtc->base);
8242 }
8243
8244 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8245 * to set it here already despite that we pass it down the callchain.
8246 */
8247 if (modeset_pipes) {
8248 crtc->mode = *mode;
8249 /* mode_set/enable/disable functions rely on a correct pipe
8250 * config. */
8251 to_intel_crtc(crtc)->config = *pipe_config;
8252 }
8253
8254 /* Only after disabling all output pipelines that will be changed can we
8255 * update the the output configuration. */
8256 intel_modeset_update_state(dev, prepare_pipes);
8257
8258 if (dev_priv->display.modeset_global_resources)
8259 dev_priv->display.modeset_global_resources(dev);
8260
8261 /* Set up the DPLL and any encoders state that needs to adjust or depend
8262 * on the DPLL.
8263 */
8264 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8265 ret = intel_crtc_mode_set(&intel_crtc->base,
8266 x, y, fb);
8267 if (ret)
8268 goto done;
8269 }
8270
8271 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8272 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8273 dev_priv->display.crtc_enable(&intel_crtc->base);
8274
8275 if (modeset_pipes) {
8276 /* Store real post-adjustment hardware mode. */
8277 crtc->hwmode = pipe_config->adjusted_mode;
8278
8279 /* Calculate and store various constants which
8280 * are later needed by vblank and swap-completion
8281 * timestamping. They are derived from true hwmode.
8282 */
8283 drm_calc_timestamping_constants(crtc);
8284 }
8285
8286 /* FIXME: add subpixel order */
8287 done:
8288 if (ret && crtc->enabled) {
8289 crtc->hwmode = *saved_hwmode;
8290 crtc->mode = *saved_mode;
8291 }
8292
8293 out:
8294 kfree(pipe_config);
8295 kfree(saved_mode);
8296 return ret;
8297 }
8298
8299 int intel_set_mode(struct drm_crtc *crtc,
8300 struct drm_display_mode *mode,
8301 int x, int y, struct drm_framebuffer *fb)
8302 {
8303 int ret;
8304
8305 ret = __intel_set_mode(crtc, mode, x, y, fb);
8306
8307 if (ret == 0)
8308 intel_modeset_check_state(crtc->dev);
8309
8310 return ret;
8311 }
8312
8313 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8314 {
8315 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8316 }
8317
8318 #undef for_each_intel_crtc_masked
8319
8320 static void intel_set_config_free(struct intel_set_config *config)
8321 {
8322 if (!config)
8323 return;
8324
8325 kfree(config->save_connector_encoders);
8326 kfree(config->save_encoder_crtcs);
8327 kfree(config);
8328 }
8329
8330 static int intel_set_config_save_state(struct drm_device *dev,
8331 struct intel_set_config *config)
8332 {
8333 struct drm_encoder *encoder;
8334 struct drm_connector *connector;
8335 int count;
8336
8337 config->save_encoder_crtcs =
8338 kcalloc(dev->mode_config.num_encoder,
8339 sizeof(struct drm_crtc *), GFP_KERNEL);
8340 if (!config->save_encoder_crtcs)
8341 return -ENOMEM;
8342
8343 config->save_connector_encoders =
8344 kcalloc(dev->mode_config.num_connector,
8345 sizeof(struct drm_encoder *), GFP_KERNEL);
8346 if (!config->save_connector_encoders)
8347 return -ENOMEM;
8348
8349 /* Copy data. Note that driver private data is not affected.
8350 * Should anything bad happen only the expected state is
8351 * restored, not the drivers personal bookkeeping.
8352 */
8353 count = 0;
8354 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8355 config->save_encoder_crtcs[count++] = encoder->crtc;
8356 }
8357
8358 count = 0;
8359 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8360 config->save_connector_encoders[count++] = connector->encoder;
8361 }
8362
8363 return 0;
8364 }
8365
8366 static void intel_set_config_restore_state(struct drm_device *dev,
8367 struct intel_set_config *config)
8368 {
8369 struct intel_encoder *encoder;
8370 struct intel_connector *connector;
8371 int count;
8372
8373 count = 0;
8374 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8375 encoder->new_crtc =
8376 to_intel_crtc(config->save_encoder_crtcs[count++]);
8377 }
8378
8379 count = 0;
8380 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8381 connector->new_encoder =
8382 to_intel_encoder(config->save_connector_encoders[count++]);
8383 }
8384 }
8385
8386 static void
8387 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8388 struct intel_set_config *config)
8389 {
8390
8391 /* We should be able to check here if the fb has the same properties
8392 * and then just flip_or_move it */
8393 if (set->crtc->fb != set->fb) {
8394 /* If we have no fb then treat it as a full mode set */
8395 if (set->crtc->fb == NULL) {
8396 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8397 config->mode_changed = true;
8398 } else if (set->fb == NULL) {
8399 config->mode_changed = true;
8400 } else if (set->fb->pixel_format !=
8401 set->crtc->fb->pixel_format) {
8402 config->mode_changed = true;
8403 } else
8404 config->fb_changed = true;
8405 }
8406
8407 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8408 config->fb_changed = true;
8409
8410 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8411 DRM_DEBUG_KMS("modes are different, full mode set\n");
8412 drm_mode_debug_printmodeline(&set->crtc->mode);
8413 drm_mode_debug_printmodeline(set->mode);
8414 config->mode_changed = true;
8415 }
8416 }
8417
8418 static int
8419 intel_modeset_stage_output_state(struct drm_device *dev,
8420 struct drm_mode_set *set,
8421 struct intel_set_config *config)
8422 {
8423 struct drm_crtc *new_crtc;
8424 struct intel_connector *connector;
8425 struct intel_encoder *encoder;
8426 int count, ro;
8427
8428 /* The upper layers ensure that we either disable a crtc or have a list
8429 * of connectors. For paranoia, double-check this. */
8430 WARN_ON(!set->fb && (set->num_connectors != 0));
8431 WARN_ON(set->fb && (set->num_connectors == 0));
8432
8433 count = 0;
8434 list_for_each_entry(connector, &dev->mode_config.connector_list,
8435 base.head) {
8436 /* Otherwise traverse passed in connector list and get encoders
8437 * for them. */
8438 for (ro = 0; ro < set->num_connectors; ro++) {
8439 if (set->connectors[ro] == &connector->base) {
8440 connector->new_encoder = connector->encoder;
8441 break;
8442 }
8443 }
8444
8445 /* If we disable the crtc, disable all its connectors. Also, if
8446 * the connector is on the changing crtc but not on the new
8447 * connector list, disable it. */
8448 if ((!set->fb || ro == set->num_connectors) &&
8449 connector->base.encoder &&
8450 connector->base.encoder->crtc == set->crtc) {
8451 connector->new_encoder = NULL;
8452
8453 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8454 connector->base.base.id,
8455 drm_get_connector_name(&connector->base));
8456 }
8457
8458
8459 if (&connector->new_encoder->base != connector->base.encoder) {
8460 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8461 config->mode_changed = true;
8462 }
8463 }
8464 /* connector->new_encoder is now updated for all connectors. */
8465
8466 /* Update crtc of enabled connectors. */
8467 count = 0;
8468 list_for_each_entry(connector, &dev->mode_config.connector_list,
8469 base.head) {
8470 if (!connector->new_encoder)
8471 continue;
8472
8473 new_crtc = connector->new_encoder->base.crtc;
8474
8475 for (ro = 0; ro < set->num_connectors; ro++) {
8476 if (set->connectors[ro] == &connector->base)
8477 new_crtc = set->crtc;
8478 }
8479
8480 /* Make sure the new CRTC will work with the encoder */
8481 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8482 new_crtc)) {
8483 return -EINVAL;
8484 }
8485 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8486
8487 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8488 connector->base.base.id,
8489 drm_get_connector_name(&connector->base),
8490 new_crtc->base.id);
8491 }
8492
8493 /* Check for any encoders that needs to be disabled. */
8494 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8495 base.head) {
8496 list_for_each_entry(connector,
8497 &dev->mode_config.connector_list,
8498 base.head) {
8499 if (connector->new_encoder == encoder) {
8500 WARN_ON(!connector->new_encoder->new_crtc);
8501
8502 goto next_encoder;
8503 }
8504 }
8505 encoder->new_crtc = NULL;
8506 next_encoder:
8507 /* Only now check for crtc changes so we don't miss encoders
8508 * that will be disabled. */
8509 if (&encoder->new_crtc->base != encoder->base.crtc) {
8510 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8511 config->mode_changed = true;
8512 }
8513 }
8514 /* Now we've also updated encoder->new_crtc for all encoders. */
8515
8516 return 0;
8517 }
8518
8519 static int intel_crtc_set_config(struct drm_mode_set *set)
8520 {
8521 struct drm_device *dev;
8522 struct drm_mode_set save_set;
8523 struct intel_set_config *config;
8524 int ret;
8525
8526 BUG_ON(!set);
8527 BUG_ON(!set->crtc);
8528 BUG_ON(!set->crtc->helper_private);
8529
8530 /* Enforce sane interface api - has been abused by the fb helper. */
8531 BUG_ON(!set->mode && set->fb);
8532 BUG_ON(set->fb && set->num_connectors == 0);
8533
8534 if (set->fb) {
8535 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8536 set->crtc->base.id, set->fb->base.id,
8537 (int)set->num_connectors, set->x, set->y);
8538 } else {
8539 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8540 }
8541
8542 dev = set->crtc->dev;
8543
8544 ret = -ENOMEM;
8545 config = kzalloc(sizeof(*config), GFP_KERNEL);
8546 if (!config)
8547 goto out_config;
8548
8549 ret = intel_set_config_save_state(dev, config);
8550 if (ret)
8551 goto out_config;
8552
8553 save_set.crtc = set->crtc;
8554 save_set.mode = &set->crtc->mode;
8555 save_set.x = set->crtc->x;
8556 save_set.y = set->crtc->y;
8557 save_set.fb = set->crtc->fb;
8558
8559 /* Compute whether we need a full modeset, only an fb base update or no
8560 * change at all. In the future we might also check whether only the
8561 * mode changed, e.g. for LVDS where we only change the panel fitter in
8562 * such cases. */
8563 intel_set_config_compute_mode_changes(set, config);
8564
8565 ret = intel_modeset_stage_output_state(dev, set, config);
8566 if (ret)
8567 goto fail;
8568
8569 if (config->mode_changed) {
8570 ret = intel_set_mode(set->crtc, set->mode,
8571 set->x, set->y, set->fb);
8572 if (ret) {
8573 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8574 set->crtc->base.id, ret);
8575 goto fail;
8576 }
8577 } else if (config->fb_changed) {
8578 intel_crtc_wait_for_pending_flips(set->crtc);
8579
8580 ret = intel_pipe_set_base(set->crtc,
8581 set->x, set->y, set->fb);
8582 }
8583
8584 intel_set_config_free(config);
8585
8586 return 0;
8587
8588 fail:
8589 intel_set_config_restore_state(dev, config);
8590
8591 /* Try to restore the config */
8592 if (config->mode_changed &&
8593 intel_set_mode(save_set.crtc, save_set.mode,
8594 save_set.x, save_set.y, save_set.fb))
8595 DRM_ERROR("failed to restore config after modeset failure\n");
8596
8597 out_config:
8598 intel_set_config_free(config);
8599 return ret;
8600 }
8601
8602 static const struct drm_crtc_funcs intel_crtc_funcs = {
8603 .cursor_set = intel_crtc_cursor_set,
8604 .cursor_move = intel_crtc_cursor_move,
8605 .gamma_set = intel_crtc_gamma_set,
8606 .set_config = intel_crtc_set_config,
8607 .destroy = intel_crtc_destroy,
8608 .page_flip = intel_crtc_page_flip,
8609 };
8610
8611 static void intel_cpu_pll_init(struct drm_device *dev)
8612 {
8613 if (HAS_DDI(dev))
8614 intel_ddi_pll_init(dev);
8615 }
8616
8617 static void intel_pch_pll_init(struct drm_device *dev)
8618 {
8619 drm_i915_private_t *dev_priv = dev->dev_private;
8620 int i;
8621
8622 if (dev_priv->num_pch_pll == 0) {
8623 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8624 return;
8625 }
8626
8627 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8628 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8629 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8630 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8631 }
8632 }
8633
8634 static void intel_crtc_init(struct drm_device *dev, int pipe)
8635 {
8636 drm_i915_private_t *dev_priv = dev->dev_private;
8637 struct intel_crtc *intel_crtc;
8638 int i;
8639
8640 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8641 if (intel_crtc == NULL)
8642 return;
8643
8644 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8645
8646 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8647 for (i = 0; i < 256; i++) {
8648 intel_crtc->lut_r[i] = i;
8649 intel_crtc->lut_g[i] = i;
8650 intel_crtc->lut_b[i] = i;
8651 }
8652
8653 /* Swap pipes & planes for FBC on pre-965 */
8654 intel_crtc->pipe = pipe;
8655 intel_crtc->plane = pipe;
8656 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8657 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8658 intel_crtc->plane = !pipe;
8659 }
8660
8661 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8662 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8663 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8664 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8665
8666 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8667 }
8668
8669 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8670 struct drm_file *file)
8671 {
8672 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8673 struct drm_mode_object *drmmode_obj;
8674 struct intel_crtc *crtc;
8675
8676 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8677 return -ENODEV;
8678
8679 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8680 DRM_MODE_OBJECT_CRTC);
8681
8682 if (!drmmode_obj) {
8683 DRM_ERROR("no such CRTC id\n");
8684 return -EINVAL;
8685 }
8686
8687 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8688 pipe_from_crtc_id->pipe = crtc->pipe;
8689
8690 return 0;
8691 }
8692
8693 static int intel_encoder_clones(struct intel_encoder *encoder)
8694 {
8695 struct drm_device *dev = encoder->base.dev;
8696 struct intel_encoder *source_encoder;
8697 int index_mask = 0;
8698 int entry = 0;
8699
8700 list_for_each_entry(source_encoder,
8701 &dev->mode_config.encoder_list, base.head) {
8702
8703 if (encoder == source_encoder)
8704 index_mask |= (1 << entry);
8705
8706 /* Intel hw has only one MUX where enocoders could be cloned. */
8707 if (encoder->cloneable && source_encoder->cloneable)
8708 index_mask |= (1 << entry);
8709
8710 entry++;
8711 }
8712
8713 return index_mask;
8714 }
8715
8716 static bool has_edp_a(struct drm_device *dev)
8717 {
8718 struct drm_i915_private *dev_priv = dev->dev_private;
8719
8720 if (!IS_MOBILE(dev))
8721 return false;
8722
8723 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8724 return false;
8725
8726 if (IS_GEN5(dev) &&
8727 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8728 return false;
8729
8730 return true;
8731 }
8732
8733 static void intel_setup_outputs(struct drm_device *dev)
8734 {
8735 struct drm_i915_private *dev_priv = dev->dev_private;
8736 struct intel_encoder *encoder;
8737 bool dpd_is_edp = false;
8738 bool has_lvds;
8739
8740 has_lvds = intel_lvds_init(dev);
8741 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8742 /* disable the panel fitter on everything but LVDS */
8743 I915_WRITE(PFIT_CONTROL, 0);
8744 }
8745
8746 if (!IS_ULT(dev))
8747 intel_crt_init(dev);
8748
8749 if (HAS_DDI(dev)) {
8750 int found;
8751
8752 /* Haswell uses DDI functions to detect digital outputs */
8753 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8754 /* DDI A only supports eDP */
8755 if (found)
8756 intel_ddi_init(dev, PORT_A);
8757
8758 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8759 * register */
8760 found = I915_READ(SFUSE_STRAP);
8761
8762 if (found & SFUSE_STRAP_DDIB_DETECTED)
8763 intel_ddi_init(dev, PORT_B);
8764 if (found & SFUSE_STRAP_DDIC_DETECTED)
8765 intel_ddi_init(dev, PORT_C);
8766 if (found & SFUSE_STRAP_DDID_DETECTED)
8767 intel_ddi_init(dev, PORT_D);
8768 } else if (HAS_PCH_SPLIT(dev)) {
8769 int found;
8770 dpd_is_edp = intel_dpd_is_edp(dev);
8771
8772 if (has_edp_a(dev))
8773 intel_dp_init(dev, DP_A, PORT_A);
8774
8775 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
8776 /* PCH SDVOB multiplex with HDMIB */
8777 found = intel_sdvo_init(dev, PCH_SDVOB, true);
8778 if (!found)
8779 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
8780 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8781 intel_dp_init(dev, PCH_DP_B, PORT_B);
8782 }
8783
8784 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
8785 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
8786
8787 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
8788 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
8789
8790 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8791 intel_dp_init(dev, PCH_DP_C, PORT_C);
8792
8793 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8794 intel_dp_init(dev, PCH_DP_D, PORT_D);
8795 } else if (IS_VALLEYVIEW(dev)) {
8796 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8797 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8798 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
8799
8800 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
8801 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8802 PORT_B);
8803 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8804 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
8805 }
8806 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8807 bool found = false;
8808
8809 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8810 DRM_DEBUG_KMS("probing SDVOB\n");
8811 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
8812 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8813 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8814 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
8815 }
8816
8817 if (!found && SUPPORTS_INTEGRATED_DP(dev))
8818 intel_dp_init(dev, DP_B, PORT_B);
8819 }
8820
8821 /* Before G4X SDVOC doesn't have its own detect register */
8822
8823 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8824 DRM_DEBUG_KMS("probing SDVOC\n");
8825 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
8826 }
8827
8828 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
8829
8830 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8831 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8832 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
8833 }
8834 if (SUPPORTS_INTEGRATED_DP(dev))
8835 intel_dp_init(dev, DP_C, PORT_C);
8836 }
8837
8838 if (SUPPORTS_INTEGRATED_DP(dev) &&
8839 (I915_READ(DP_D) & DP_DETECTED))
8840 intel_dp_init(dev, DP_D, PORT_D);
8841 } else if (IS_GEN2(dev))
8842 intel_dvo_init(dev);
8843
8844 if (SUPPORTS_TV(dev))
8845 intel_tv_init(dev);
8846
8847 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8848 encoder->base.possible_crtcs = encoder->crtc_mask;
8849 encoder->base.possible_clones =
8850 intel_encoder_clones(encoder);
8851 }
8852
8853 intel_init_pch_refclk(dev);
8854
8855 drm_helper_move_panel_connectors_to_head(dev);
8856 }
8857
8858 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8859 {
8860 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8861
8862 drm_framebuffer_cleanup(fb);
8863 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8864
8865 kfree(intel_fb);
8866 }
8867
8868 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8869 struct drm_file *file,
8870 unsigned int *handle)
8871 {
8872 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8873 struct drm_i915_gem_object *obj = intel_fb->obj;
8874
8875 return drm_gem_handle_create(file, &obj->base, handle);
8876 }
8877
8878 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8879 .destroy = intel_user_framebuffer_destroy,
8880 .create_handle = intel_user_framebuffer_create_handle,
8881 };
8882
8883 int intel_framebuffer_init(struct drm_device *dev,
8884 struct intel_framebuffer *intel_fb,
8885 struct drm_mode_fb_cmd2 *mode_cmd,
8886 struct drm_i915_gem_object *obj)
8887 {
8888 int ret;
8889
8890 if (obj->tiling_mode == I915_TILING_Y) {
8891 DRM_DEBUG("hardware does not support tiling Y\n");
8892 return -EINVAL;
8893 }
8894
8895 if (mode_cmd->pitches[0] & 63) {
8896 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8897 mode_cmd->pitches[0]);
8898 return -EINVAL;
8899 }
8900
8901 /* FIXME <= Gen4 stride limits are bit unclear */
8902 if (mode_cmd->pitches[0] > 32768) {
8903 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8904 mode_cmd->pitches[0]);
8905 return -EINVAL;
8906 }
8907
8908 if (obj->tiling_mode != I915_TILING_NONE &&
8909 mode_cmd->pitches[0] != obj->stride) {
8910 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8911 mode_cmd->pitches[0], obj->stride);
8912 return -EINVAL;
8913 }
8914
8915 /* Reject formats not supported by any plane early. */
8916 switch (mode_cmd->pixel_format) {
8917 case DRM_FORMAT_C8:
8918 case DRM_FORMAT_RGB565:
8919 case DRM_FORMAT_XRGB8888:
8920 case DRM_FORMAT_ARGB8888:
8921 break;
8922 case DRM_FORMAT_XRGB1555:
8923 case DRM_FORMAT_ARGB1555:
8924 if (INTEL_INFO(dev)->gen > 3) {
8925 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8926 return -EINVAL;
8927 }
8928 break;
8929 case DRM_FORMAT_XBGR8888:
8930 case DRM_FORMAT_ABGR8888:
8931 case DRM_FORMAT_XRGB2101010:
8932 case DRM_FORMAT_ARGB2101010:
8933 case DRM_FORMAT_XBGR2101010:
8934 case DRM_FORMAT_ABGR2101010:
8935 if (INTEL_INFO(dev)->gen < 4) {
8936 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8937 return -EINVAL;
8938 }
8939 break;
8940 case DRM_FORMAT_YUYV:
8941 case DRM_FORMAT_UYVY:
8942 case DRM_FORMAT_YVYU:
8943 case DRM_FORMAT_VYUY:
8944 if (INTEL_INFO(dev)->gen < 5) {
8945 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8946 return -EINVAL;
8947 }
8948 break;
8949 default:
8950 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8951 return -EINVAL;
8952 }
8953
8954 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8955 if (mode_cmd->offsets[0] != 0)
8956 return -EINVAL;
8957
8958 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8959 intel_fb->obj = obj;
8960
8961 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8962 if (ret) {
8963 DRM_ERROR("framebuffer init failed %d\n", ret);
8964 return ret;
8965 }
8966
8967 return 0;
8968 }
8969
8970 static struct drm_framebuffer *
8971 intel_user_framebuffer_create(struct drm_device *dev,
8972 struct drm_file *filp,
8973 struct drm_mode_fb_cmd2 *mode_cmd)
8974 {
8975 struct drm_i915_gem_object *obj;
8976
8977 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8978 mode_cmd->handles[0]));
8979 if (&obj->base == NULL)
8980 return ERR_PTR(-ENOENT);
8981
8982 return intel_framebuffer_create(dev, mode_cmd, obj);
8983 }
8984
8985 static const struct drm_mode_config_funcs intel_mode_funcs = {
8986 .fb_create = intel_user_framebuffer_create,
8987 .output_poll_changed = intel_fb_output_poll_changed,
8988 };
8989
8990 /* Set up chip specific display functions */
8991 static void intel_init_display(struct drm_device *dev)
8992 {
8993 struct drm_i915_private *dev_priv = dev->dev_private;
8994
8995 if (HAS_DDI(dev)) {
8996 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
8997 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8998 dev_priv->display.crtc_enable = haswell_crtc_enable;
8999 dev_priv->display.crtc_disable = haswell_crtc_disable;
9000 dev_priv->display.off = haswell_crtc_off;
9001 dev_priv->display.update_plane = ironlake_update_plane;
9002 } else if (HAS_PCH_SPLIT(dev)) {
9003 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
9004 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9005 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9006 dev_priv->display.crtc_disable = ironlake_crtc_disable;
9007 dev_priv->display.off = ironlake_crtc_off;
9008 dev_priv->display.update_plane = ironlake_update_plane;
9009 } else if (IS_VALLEYVIEW(dev)) {
9010 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9011 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9012 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9013 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9014 dev_priv->display.off = i9xx_crtc_off;
9015 dev_priv->display.update_plane = i9xx_update_plane;
9016 } else {
9017 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9018 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9019 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9020 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9021 dev_priv->display.off = i9xx_crtc_off;
9022 dev_priv->display.update_plane = i9xx_update_plane;
9023 }
9024
9025 /* Returns the core display clock speed */
9026 if (IS_VALLEYVIEW(dev))
9027 dev_priv->display.get_display_clock_speed =
9028 valleyview_get_display_clock_speed;
9029 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
9030 dev_priv->display.get_display_clock_speed =
9031 i945_get_display_clock_speed;
9032 else if (IS_I915G(dev))
9033 dev_priv->display.get_display_clock_speed =
9034 i915_get_display_clock_speed;
9035 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
9036 dev_priv->display.get_display_clock_speed =
9037 i9xx_misc_get_display_clock_speed;
9038 else if (IS_I915GM(dev))
9039 dev_priv->display.get_display_clock_speed =
9040 i915gm_get_display_clock_speed;
9041 else if (IS_I865G(dev))
9042 dev_priv->display.get_display_clock_speed =
9043 i865_get_display_clock_speed;
9044 else if (IS_I85X(dev))
9045 dev_priv->display.get_display_clock_speed =
9046 i855_get_display_clock_speed;
9047 else /* 852, 830 */
9048 dev_priv->display.get_display_clock_speed =
9049 i830_get_display_clock_speed;
9050
9051 if (HAS_PCH_SPLIT(dev)) {
9052 if (IS_GEN5(dev)) {
9053 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9054 dev_priv->display.write_eld = ironlake_write_eld;
9055 } else if (IS_GEN6(dev)) {
9056 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9057 dev_priv->display.write_eld = ironlake_write_eld;
9058 } else if (IS_IVYBRIDGE(dev)) {
9059 /* FIXME: detect B0+ stepping and use auto training */
9060 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9061 dev_priv->display.write_eld = ironlake_write_eld;
9062 dev_priv->display.modeset_global_resources =
9063 ivb_modeset_global_resources;
9064 } else if (IS_HASWELL(dev)) {
9065 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
9066 dev_priv->display.write_eld = haswell_write_eld;
9067 dev_priv->display.modeset_global_resources =
9068 haswell_modeset_global_resources;
9069 }
9070 } else if (IS_G4X(dev)) {
9071 dev_priv->display.write_eld = g4x_write_eld;
9072 }
9073
9074 /* Default just returns -ENODEV to indicate unsupported */
9075 dev_priv->display.queue_flip = intel_default_queue_flip;
9076
9077 switch (INTEL_INFO(dev)->gen) {
9078 case 2:
9079 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9080 break;
9081
9082 case 3:
9083 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9084 break;
9085
9086 case 4:
9087 case 5:
9088 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9089 break;
9090
9091 case 6:
9092 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9093 break;
9094 case 7:
9095 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9096 break;
9097 }
9098 }
9099
9100 /*
9101 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9102 * resume, or other times. This quirk makes sure that's the case for
9103 * affected systems.
9104 */
9105 static void quirk_pipea_force(struct drm_device *dev)
9106 {
9107 struct drm_i915_private *dev_priv = dev->dev_private;
9108
9109 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9110 DRM_INFO("applying pipe a force quirk\n");
9111 }
9112
9113 /*
9114 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9115 */
9116 static void quirk_ssc_force_disable(struct drm_device *dev)
9117 {
9118 struct drm_i915_private *dev_priv = dev->dev_private;
9119 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9120 DRM_INFO("applying lvds SSC disable quirk\n");
9121 }
9122
9123 /*
9124 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9125 * brightness value
9126 */
9127 static void quirk_invert_brightness(struct drm_device *dev)
9128 {
9129 struct drm_i915_private *dev_priv = dev->dev_private;
9130 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9131 DRM_INFO("applying inverted panel brightness quirk\n");
9132 }
9133
9134 struct intel_quirk {
9135 int device;
9136 int subsystem_vendor;
9137 int subsystem_device;
9138 void (*hook)(struct drm_device *dev);
9139 };
9140
9141 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9142 struct intel_dmi_quirk {
9143 void (*hook)(struct drm_device *dev);
9144 const struct dmi_system_id (*dmi_id_list)[];
9145 };
9146
9147 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9148 {
9149 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9150 return 1;
9151 }
9152
9153 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9154 {
9155 .dmi_id_list = &(const struct dmi_system_id[]) {
9156 {
9157 .callback = intel_dmi_reverse_brightness,
9158 .ident = "NCR Corporation",
9159 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9160 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9161 },
9162 },
9163 { } /* terminating entry */
9164 },
9165 .hook = quirk_invert_brightness,
9166 },
9167 };
9168
9169 static struct intel_quirk intel_quirks[] = {
9170 /* HP Mini needs pipe A force quirk (LP: #322104) */
9171 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9172
9173 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9174 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9175
9176 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9177 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9178
9179 /* 830/845 need to leave pipe A & dpll A up */
9180 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9181 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9182
9183 /* Lenovo U160 cannot use SSC on LVDS */
9184 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9185
9186 /* Sony Vaio Y cannot use SSC on LVDS */
9187 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9188
9189 /* Acer Aspire 5734Z must invert backlight brightness */
9190 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9191
9192 /* Acer/eMachines G725 */
9193 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
9194
9195 /* Acer/eMachines e725 */
9196 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
9197
9198 /* Acer/Packard Bell NCL20 */
9199 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
9200
9201 /* Acer Aspire 4736Z */
9202 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
9203 };
9204
9205 static void intel_init_quirks(struct drm_device *dev)
9206 {
9207 struct pci_dev *d = dev->pdev;
9208 int i;
9209
9210 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9211 struct intel_quirk *q = &intel_quirks[i];
9212
9213 if (d->device == q->device &&
9214 (d->subsystem_vendor == q->subsystem_vendor ||
9215 q->subsystem_vendor == PCI_ANY_ID) &&
9216 (d->subsystem_device == q->subsystem_device ||
9217 q->subsystem_device == PCI_ANY_ID))
9218 q->hook(dev);
9219 }
9220 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9221 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9222 intel_dmi_quirks[i].hook(dev);
9223 }
9224 }
9225
9226 /* Disable the VGA plane that we never use */
9227 static void i915_disable_vga(struct drm_device *dev)
9228 {
9229 struct drm_i915_private *dev_priv = dev->dev_private;
9230 u8 sr1;
9231 u32 vga_reg = i915_vgacntrl_reg(dev);
9232
9233 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9234 outb(SR01, VGA_SR_INDEX);
9235 sr1 = inb(VGA_SR_DATA);
9236 outb(sr1 | 1<<5, VGA_SR_DATA);
9237 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9238 udelay(300);
9239
9240 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9241 POSTING_READ(vga_reg);
9242 }
9243
9244 void intel_modeset_init_hw(struct drm_device *dev)
9245 {
9246 intel_init_power_well(dev);
9247
9248 intel_prepare_ddi(dev);
9249
9250 intel_init_clock_gating(dev);
9251
9252 mutex_lock(&dev->struct_mutex);
9253 intel_enable_gt_powersave(dev);
9254 mutex_unlock(&dev->struct_mutex);
9255 }
9256
9257 void intel_modeset_suspend_hw(struct drm_device *dev)
9258 {
9259 intel_suspend_hw(dev);
9260 }
9261
9262 void intel_modeset_init(struct drm_device *dev)
9263 {
9264 struct drm_i915_private *dev_priv = dev->dev_private;
9265 int i, j, ret;
9266
9267 drm_mode_config_init(dev);
9268
9269 dev->mode_config.min_width = 0;
9270 dev->mode_config.min_height = 0;
9271
9272 dev->mode_config.preferred_depth = 24;
9273 dev->mode_config.prefer_shadow = 1;
9274
9275 dev->mode_config.funcs = &intel_mode_funcs;
9276
9277 intel_init_quirks(dev);
9278
9279 intel_init_pm(dev);
9280
9281 if (INTEL_INFO(dev)->num_pipes == 0)
9282 return;
9283
9284 intel_init_display(dev);
9285
9286 if (IS_GEN2(dev)) {
9287 dev->mode_config.max_width = 2048;
9288 dev->mode_config.max_height = 2048;
9289 } else if (IS_GEN3(dev)) {
9290 dev->mode_config.max_width = 4096;
9291 dev->mode_config.max_height = 4096;
9292 } else {
9293 dev->mode_config.max_width = 8192;
9294 dev->mode_config.max_height = 8192;
9295 }
9296 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
9297
9298 DRM_DEBUG_KMS("%d display pipe%s available.\n",
9299 INTEL_INFO(dev)->num_pipes,
9300 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
9301
9302 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
9303 intel_crtc_init(dev, i);
9304 for (j = 0; j < dev_priv->num_plane; j++) {
9305 ret = intel_plane_init(dev, i, j);
9306 if (ret)
9307 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9308 pipe_name(i), sprite_name(i, j), ret);
9309 }
9310 }
9311
9312 intel_cpu_pll_init(dev);
9313 intel_pch_pll_init(dev);
9314
9315 /* Just disable it once at startup */
9316 i915_disable_vga(dev);
9317 intel_setup_outputs(dev);
9318
9319 /* Just in case the BIOS is doing something questionable. */
9320 intel_disable_fbc(dev);
9321 }
9322
9323 static void
9324 intel_connector_break_all_links(struct intel_connector *connector)
9325 {
9326 connector->base.dpms = DRM_MODE_DPMS_OFF;
9327 connector->base.encoder = NULL;
9328 connector->encoder->connectors_active = false;
9329 connector->encoder->base.crtc = NULL;
9330 }
9331
9332 static void intel_enable_pipe_a(struct drm_device *dev)
9333 {
9334 struct intel_connector *connector;
9335 struct drm_connector *crt = NULL;
9336 struct intel_load_detect_pipe load_detect_temp;
9337
9338 /* We can't just switch on the pipe A, we need to set things up with a
9339 * proper mode and output configuration. As a gross hack, enable pipe A
9340 * by enabling the load detect pipe once. */
9341 list_for_each_entry(connector,
9342 &dev->mode_config.connector_list,
9343 base.head) {
9344 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9345 crt = &connector->base;
9346 break;
9347 }
9348 }
9349
9350 if (!crt)
9351 return;
9352
9353 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9354 intel_release_load_detect_pipe(crt, &load_detect_temp);
9355
9356
9357 }
9358
9359 static bool
9360 intel_check_plane_mapping(struct intel_crtc *crtc)
9361 {
9362 struct drm_device *dev = crtc->base.dev;
9363 struct drm_i915_private *dev_priv = dev->dev_private;
9364 u32 reg, val;
9365
9366 if (INTEL_INFO(dev)->num_pipes == 1)
9367 return true;
9368
9369 reg = DSPCNTR(!crtc->plane);
9370 val = I915_READ(reg);
9371
9372 if ((val & DISPLAY_PLANE_ENABLE) &&
9373 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9374 return false;
9375
9376 return true;
9377 }
9378
9379 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9380 {
9381 struct drm_device *dev = crtc->base.dev;
9382 struct drm_i915_private *dev_priv = dev->dev_private;
9383 u32 reg;
9384
9385 /* Clear any frame start delays used for debugging left by the BIOS */
9386 reg = PIPECONF(crtc->config.cpu_transcoder);
9387 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9388
9389 /* We need to sanitize the plane -> pipe mapping first because this will
9390 * disable the crtc (and hence change the state) if it is wrong. Note
9391 * that gen4+ has a fixed plane -> pipe mapping. */
9392 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9393 struct intel_connector *connector;
9394 bool plane;
9395
9396 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9397 crtc->base.base.id);
9398
9399 /* Pipe has the wrong plane attached and the plane is active.
9400 * Temporarily change the plane mapping and disable everything
9401 * ... */
9402 plane = crtc->plane;
9403 crtc->plane = !plane;
9404 dev_priv->display.crtc_disable(&crtc->base);
9405 crtc->plane = plane;
9406
9407 /* ... and break all links. */
9408 list_for_each_entry(connector, &dev->mode_config.connector_list,
9409 base.head) {
9410 if (connector->encoder->base.crtc != &crtc->base)
9411 continue;
9412
9413 intel_connector_break_all_links(connector);
9414 }
9415
9416 WARN_ON(crtc->active);
9417 crtc->base.enabled = false;
9418 }
9419
9420 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9421 crtc->pipe == PIPE_A && !crtc->active) {
9422 /* BIOS forgot to enable pipe A, this mostly happens after
9423 * resume. Force-enable the pipe to fix this, the update_dpms
9424 * call below we restore the pipe to the right state, but leave
9425 * the required bits on. */
9426 intel_enable_pipe_a(dev);
9427 }
9428
9429 /* Adjust the state of the output pipe according to whether we
9430 * have active connectors/encoders. */
9431 intel_crtc_update_dpms(&crtc->base);
9432
9433 if (crtc->active != crtc->base.enabled) {
9434 struct intel_encoder *encoder;
9435
9436 /* This can happen either due to bugs in the get_hw_state
9437 * functions or because the pipe is force-enabled due to the
9438 * pipe A quirk. */
9439 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9440 crtc->base.base.id,
9441 crtc->base.enabled ? "enabled" : "disabled",
9442 crtc->active ? "enabled" : "disabled");
9443
9444 crtc->base.enabled = crtc->active;
9445
9446 /* Because we only establish the connector -> encoder ->
9447 * crtc links if something is active, this means the
9448 * crtc is now deactivated. Break the links. connector
9449 * -> encoder links are only establish when things are
9450 * actually up, hence no need to break them. */
9451 WARN_ON(crtc->active);
9452
9453 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9454 WARN_ON(encoder->connectors_active);
9455 encoder->base.crtc = NULL;
9456 }
9457 }
9458 }
9459
9460 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9461 {
9462 struct intel_connector *connector;
9463 struct drm_device *dev = encoder->base.dev;
9464
9465 /* We need to check both for a crtc link (meaning that the
9466 * encoder is active and trying to read from a pipe) and the
9467 * pipe itself being active. */
9468 bool has_active_crtc = encoder->base.crtc &&
9469 to_intel_crtc(encoder->base.crtc)->active;
9470
9471 if (encoder->connectors_active && !has_active_crtc) {
9472 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9473 encoder->base.base.id,
9474 drm_get_encoder_name(&encoder->base));
9475
9476 /* Connector is active, but has no active pipe. This is
9477 * fallout from our resume register restoring. Disable
9478 * the encoder manually again. */
9479 if (encoder->base.crtc) {
9480 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9481 encoder->base.base.id,
9482 drm_get_encoder_name(&encoder->base));
9483 encoder->disable(encoder);
9484 }
9485
9486 /* Inconsistent output/port/pipe state happens presumably due to
9487 * a bug in one of the get_hw_state functions. Or someplace else
9488 * in our code, like the register restore mess on resume. Clamp
9489 * things to off as a safer default. */
9490 list_for_each_entry(connector,
9491 &dev->mode_config.connector_list,
9492 base.head) {
9493 if (connector->encoder != encoder)
9494 continue;
9495
9496 intel_connector_break_all_links(connector);
9497 }
9498 }
9499 /* Enabled encoders without active connectors will be fixed in
9500 * the crtc fixup. */
9501 }
9502
9503 void i915_redisable_vga(struct drm_device *dev)
9504 {
9505 struct drm_i915_private *dev_priv = dev->dev_private;
9506 u32 vga_reg = i915_vgacntrl_reg(dev);
9507
9508 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9509 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9510 i915_disable_vga(dev);
9511 }
9512 }
9513
9514 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9515 * and i915 state tracking structures. */
9516 void intel_modeset_setup_hw_state(struct drm_device *dev,
9517 bool force_restore)
9518 {
9519 struct drm_i915_private *dev_priv = dev->dev_private;
9520 enum pipe pipe;
9521 struct drm_plane *plane;
9522 struct intel_crtc *crtc;
9523 struct intel_encoder *encoder;
9524 struct intel_connector *connector;
9525
9526 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9527 base.head) {
9528 memset(&crtc->config, 0, sizeof(crtc->config));
9529
9530 crtc->active = dev_priv->display.get_pipe_config(crtc,
9531 &crtc->config);
9532
9533 crtc->base.enabled = crtc->active;
9534
9535 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9536 crtc->base.base.id,
9537 crtc->active ? "enabled" : "disabled");
9538 }
9539
9540 if (HAS_DDI(dev))
9541 intel_ddi_setup_hw_pll_state(dev);
9542
9543 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9544 base.head) {
9545 pipe = 0;
9546
9547 if (encoder->get_hw_state(encoder, &pipe)) {
9548 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9549 encoder->base.crtc = &crtc->base;
9550 if (encoder->get_config)
9551 encoder->get_config(encoder, &crtc->config);
9552 } else {
9553 encoder->base.crtc = NULL;
9554 }
9555
9556 encoder->connectors_active = false;
9557 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9558 encoder->base.base.id,
9559 drm_get_encoder_name(&encoder->base),
9560 encoder->base.crtc ? "enabled" : "disabled",
9561 pipe);
9562 }
9563
9564 list_for_each_entry(connector, &dev->mode_config.connector_list,
9565 base.head) {
9566 if (connector->get_hw_state(connector)) {
9567 connector->base.dpms = DRM_MODE_DPMS_ON;
9568 connector->encoder->connectors_active = true;
9569 connector->base.encoder = &connector->encoder->base;
9570 } else {
9571 connector->base.dpms = DRM_MODE_DPMS_OFF;
9572 connector->base.encoder = NULL;
9573 }
9574 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9575 connector->base.base.id,
9576 drm_get_connector_name(&connector->base),
9577 connector->base.encoder ? "enabled" : "disabled");
9578 }
9579
9580 /* HW state is read out, now we need to sanitize this mess. */
9581 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9582 base.head) {
9583 intel_sanitize_encoder(encoder);
9584 }
9585
9586 for_each_pipe(pipe) {
9587 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9588 intel_sanitize_crtc(crtc);
9589 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
9590 }
9591
9592 if (force_restore) {
9593 /*
9594 * We need to use raw interfaces for restoring state to avoid
9595 * checking (bogus) intermediate states.
9596 */
9597 for_each_pipe(pipe) {
9598 struct drm_crtc *crtc =
9599 dev_priv->pipe_to_crtc_mapping[pipe];
9600
9601 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9602 crtc->fb);
9603 }
9604 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9605 intel_plane_restore(plane);
9606
9607 i915_redisable_vga(dev);
9608 } else {
9609 intel_modeset_update_staged_output_state(dev);
9610 }
9611
9612 intel_modeset_check_state(dev);
9613
9614 drm_mode_config_reset(dev);
9615 }
9616
9617 void intel_modeset_gem_init(struct drm_device *dev)
9618 {
9619 intel_modeset_init_hw(dev);
9620
9621 intel_setup_overlay(dev);
9622
9623 intel_modeset_setup_hw_state(dev, false);
9624 }
9625
9626 void intel_modeset_cleanup(struct drm_device *dev)
9627 {
9628 struct drm_i915_private *dev_priv = dev->dev_private;
9629 struct drm_crtc *crtc;
9630 struct intel_crtc *intel_crtc;
9631
9632 /*
9633 * Interrupts and polling as the first thing to avoid creating havoc.
9634 * Too much stuff here (turning of rps, connectors, ...) would
9635 * experience fancy races otherwise.
9636 */
9637 drm_irq_uninstall(dev);
9638 cancel_work_sync(&dev_priv->hotplug_work);
9639 /*
9640 * Due to the hpd irq storm handling the hotplug work can re-arm the
9641 * poll handlers. Hence disable polling after hpd handling is shut down.
9642 */
9643 drm_kms_helper_poll_fini(dev);
9644
9645 mutex_lock(&dev->struct_mutex);
9646
9647 intel_unregister_dsm_handler();
9648
9649 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9650 /* Skip inactive CRTCs */
9651 if (!crtc->fb)
9652 continue;
9653
9654 intel_crtc = to_intel_crtc(crtc);
9655 intel_increase_pllclock(crtc);
9656 }
9657
9658 intel_disable_fbc(dev);
9659
9660 intel_disable_gt_powersave(dev);
9661
9662 ironlake_teardown_rc6(dev);
9663
9664 mutex_unlock(&dev->struct_mutex);
9665
9666 /* flush any delayed tasks or pending work */
9667 flush_scheduled_work();
9668
9669 /* destroy backlight, if any, before the connectors */
9670 intel_panel_destroy_backlight(dev);
9671
9672 drm_mode_config_cleanup(dev);
9673
9674 intel_cleanup_overlay(dev);
9675 }
9676
9677 /*
9678 * Return which encoder is currently attached for connector.
9679 */
9680 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9681 {
9682 return &intel_attached_encoder(connector)->base;
9683 }
9684
9685 void intel_connector_attach_encoder(struct intel_connector *connector,
9686 struct intel_encoder *encoder)
9687 {
9688 connector->encoder = encoder;
9689 drm_mode_connector_attach_encoder(&connector->base,
9690 &encoder->base);
9691 }
9692
9693 /*
9694 * set vga decode state - true == enable VGA decode
9695 */
9696 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9697 {
9698 struct drm_i915_private *dev_priv = dev->dev_private;
9699 u16 gmch_ctrl;
9700
9701 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9702 if (state)
9703 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9704 else
9705 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9706 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9707 return 0;
9708 }
9709
9710 #ifdef CONFIG_DEBUG_FS
9711 #include <linux/seq_file.h>
9712
9713 struct intel_display_error_state {
9714
9715 u32 power_well_driver;
9716
9717 struct intel_cursor_error_state {
9718 u32 control;
9719 u32 position;
9720 u32 base;
9721 u32 size;
9722 } cursor[I915_MAX_PIPES];
9723
9724 struct intel_pipe_error_state {
9725 enum transcoder cpu_transcoder;
9726 u32 conf;
9727 u32 source;
9728
9729 u32 htotal;
9730 u32 hblank;
9731 u32 hsync;
9732 u32 vtotal;
9733 u32 vblank;
9734 u32 vsync;
9735 } pipe[I915_MAX_PIPES];
9736
9737 struct intel_plane_error_state {
9738 u32 control;
9739 u32 stride;
9740 u32 size;
9741 u32 pos;
9742 u32 addr;
9743 u32 surface;
9744 u32 tile_offset;
9745 } plane[I915_MAX_PIPES];
9746 };
9747
9748 struct intel_display_error_state *
9749 intel_display_capture_error_state(struct drm_device *dev)
9750 {
9751 drm_i915_private_t *dev_priv = dev->dev_private;
9752 struct intel_display_error_state *error;
9753 enum transcoder cpu_transcoder;
9754 int i;
9755
9756 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9757 if (error == NULL)
9758 return NULL;
9759
9760 if (HAS_POWER_WELL(dev))
9761 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
9762
9763 for_each_pipe(i) {
9764 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9765 error->pipe[i].cpu_transcoder = cpu_transcoder;
9766
9767 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9768 error->cursor[i].control = I915_READ(CURCNTR(i));
9769 error->cursor[i].position = I915_READ(CURPOS(i));
9770 error->cursor[i].base = I915_READ(CURBASE(i));
9771 } else {
9772 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9773 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9774 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9775 }
9776
9777 error->plane[i].control = I915_READ(DSPCNTR(i));
9778 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9779 if (INTEL_INFO(dev)->gen <= 3) {
9780 error->plane[i].size = I915_READ(DSPSIZE(i));
9781 error->plane[i].pos = I915_READ(DSPPOS(i));
9782 }
9783 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9784 error->plane[i].addr = I915_READ(DSPADDR(i));
9785 if (INTEL_INFO(dev)->gen >= 4) {
9786 error->plane[i].surface = I915_READ(DSPSURF(i));
9787 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9788 }
9789
9790 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9791 error->pipe[i].source = I915_READ(PIPESRC(i));
9792 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9793 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9794 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9795 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9796 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9797 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9798 }
9799
9800 /* In the code above we read the registers without checking if the power
9801 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
9802 * prevent the next I915_WRITE from detecting it and printing an error
9803 * message. */
9804 if (HAS_POWER_WELL(dev))
9805 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
9806
9807 return error;
9808 }
9809
9810 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
9811
9812 void
9813 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
9814 struct drm_device *dev,
9815 struct intel_display_error_state *error)
9816 {
9817 int i;
9818
9819 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
9820 if (HAS_POWER_WELL(dev))
9821 err_printf(m, "PWR_WELL_CTL2: %08x\n",
9822 error->power_well_driver);
9823 for_each_pipe(i) {
9824 err_printf(m, "Pipe [%d]:\n", i);
9825 err_printf(m, " CPU transcoder: %c\n",
9826 transcoder_name(error->pipe[i].cpu_transcoder));
9827 err_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9828 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
9829 err_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9830 err_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9831 err_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9832 err_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9833 err_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9834 err_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9835
9836 err_printf(m, "Plane [%d]:\n", i);
9837 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
9838 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9839 if (INTEL_INFO(dev)->gen <= 3) {
9840 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
9841 err_printf(m, " POS: %08x\n", error->plane[i].pos);
9842 }
9843 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9844 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9845 if (INTEL_INFO(dev)->gen >= 4) {
9846 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
9847 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9848 }
9849
9850 err_printf(m, "Cursor [%d]:\n", i);
9851 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9852 err_printf(m, " POS: %08x\n", error->cursor[i].position);
9853 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
9854 }
9855 }
9856 #endif
Linux kernel - Deliverables
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