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drm/i915: Use new frontbuffer bits to increase pll clock
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_rect.h>
44 #include <linux/dma_remapping.h>
45
46 /* Primary plane formats supported by all gen */
47 #define COMMON_PRIMARY_FORMATS \
48 DRM_FORMAT_C8, \
49 DRM_FORMAT_RGB565, \
50 DRM_FORMAT_XRGB8888, \
51 DRM_FORMAT_ARGB8888
52
53 /* Primary plane formats for gen <= 3 */
54 static const uint32_t intel_primary_formats_gen2[] = {
55 COMMON_PRIMARY_FORMATS,
56 DRM_FORMAT_XRGB1555,
57 DRM_FORMAT_ARGB1555,
58 };
59
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t intel_primary_formats_gen4[] = {
62 COMMON_PRIMARY_FORMATS, \
63 DRM_FORMAT_XBGR8888,
64 DRM_FORMAT_ABGR8888,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_ARGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 DRM_FORMAT_ABGR2101010,
69 };
70
71 /* Cursor formats */
72 static const uint32_t intel_cursor_formats[] = {
73 DRM_FORMAT_ARGB8888,
74 };
75
76 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
77 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
78
79 static void intel_increase_pllclock(struct drm_device *dev,
80 enum pipe pipe);
81 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
82
83 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
84 struct intel_crtc_config *pipe_config);
85 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
86 struct intel_crtc_config *pipe_config);
87
88 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
89 int x, int y, struct drm_framebuffer *old_fb);
90 static int intel_framebuffer_init(struct drm_device *dev,
91 struct intel_framebuffer *ifb,
92 struct drm_mode_fb_cmd2 *mode_cmd,
93 struct drm_i915_gem_object *obj);
94 static void intel_dp_set_m_n(struct intel_crtc *crtc);
95 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
96 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
97 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
98 struct intel_link_m_n *m_n);
99 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
100 static void haswell_set_pipeconf(struct drm_crtc *crtc);
101 static void intel_set_pipe_csc(struct drm_crtc *crtc);
102 static void vlv_prepare_pll(struct intel_crtc *crtc);
103
104 typedef struct {
105 int min, max;
106 } intel_range_t;
107
108 typedef struct {
109 int dot_limit;
110 int p2_slow, p2_fast;
111 } intel_p2_t;
112
113 typedef struct intel_limit intel_limit_t;
114 struct intel_limit {
115 intel_range_t dot, vco, n, m, m1, m2, p, p1;
116 intel_p2_t p2;
117 };
118
119 int
120 intel_pch_rawclk(struct drm_device *dev)
121 {
122 struct drm_i915_private *dev_priv = dev->dev_private;
123
124 WARN_ON(!HAS_PCH_SPLIT(dev));
125
126 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
127 }
128
129 static inline u32 /* units of 100MHz */
130 intel_fdi_link_freq(struct drm_device *dev)
131 {
132 if (IS_GEN5(dev)) {
133 struct drm_i915_private *dev_priv = dev->dev_private;
134 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
135 } else
136 return 27;
137 }
138
139 static const intel_limit_t intel_limits_i8xx_dac = {
140 .dot = { .min = 25000, .max = 350000 },
141 .vco = { .min = 908000, .max = 1512000 },
142 .n = { .min = 2, .max = 16 },
143 .m = { .min = 96, .max = 140 },
144 .m1 = { .min = 18, .max = 26 },
145 .m2 = { .min = 6, .max = 16 },
146 .p = { .min = 4, .max = 128 },
147 .p1 = { .min = 2, .max = 33 },
148 .p2 = { .dot_limit = 165000,
149 .p2_slow = 4, .p2_fast = 2 },
150 };
151
152 static const intel_limit_t intel_limits_i8xx_dvo = {
153 .dot = { .min = 25000, .max = 350000 },
154 .vco = { .min = 908000, .max = 1512000 },
155 .n = { .min = 2, .max = 16 },
156 .m = { .min = 96, .max = 140 },
157 .m1 = { .min = 18, .max = 26 },
158 .m2 = { .min = 6, .max = 16 },
159 .p = { .min = 4, .max = 128 },
160 .p1 = { .min = 2, .max = 33 },
161 .p2 = { .dot_limit = 165000,
162 .p2_slow = 4, .p2_fast = 4 },
163 };
164
165 static const intel_limit_t intel_limits_i8xx_lvds = {
166 .dot = { .min = 25000, .max = 350000 },
167 .vco = { .min = 908000, .max = 1512000 },
168 .n = { .min = 2, .max = 16 },
169 .m = { .min = 96, .max = 140 },
170 .m1 = { .min = 18, .max = 26 },
171 .m2 = { .min = 6, .max = 16 },
172 .p = { .min = 4, .max = 128 },
173 .p1 = { .min = 1, .max = 6 },
174 .p2 = { .dot_limit = 165000,
175 .p2_slow = 14, .p2_fast = 7 },
176 };
177
178 static const intel_limit_t intel_limits_i9xx_sdvo = {
179 .dot = { .min = 20000, .max = 400000 },
180 .vco = { .min = 1400000, .max = 2800000 },
181 .n = { .min = 1, .max = 6 },
182 .m = { .min = 70, .max = 120 },
183 .m1 = { .min = 8, .max = 18 },
184 .m2 = { .min = 3, .max = 7 },
185 .p = { .min = 5, .max = 80 },
186 .p1 = { .min = 1, .max = 8 },
187 .p2 = { .dot_limit = 200000,
188 .p2_slow = 10, .p2_fast = 5 },
189 };
190
191 static const intel_limit_t intel_limits_i9xx_lvds = {
192 .dot = { .min = 20000, .max = 400000 },
193 .vco = { .min = 1400000, .max = 2800000 },
194 .n = { .min = 1, .max = 6 },
195 .m = { .min = 70, .max = 120 },
196 .m1 = { .min = 8, .max = 18 },
197 .m2 = { .min = 3, .max = 7 },
198 .p = { .min = 7, .max = 98 },
199 .p1 = { .min = 1, .max = 8 },
200 .p2 = { .dot_limit = 112000,
201 .p2_slow = 14, .p2_fast = 7 },
202 };
203
204
205 static const intel_limit_t intel_limits_g4x_sdvo = {
206 .dot = { .min = 25000, .max = 270000 },
207 .vco = { .min = 1750000, .max = 3500000},
208 .n = { .min = 1, .max = 4 },
209 .m = { .min = 104, .max = 138 },
210 .m1 = { .min = 17, .max = 23 },
211 .m2 = { .min = 5, .max = 11 },
212 .p = { .min = 10, .max = 30 },
213 .p1 = { .min = 1, .max = 3},
214 .p2 = { .dot_limit = 270000,
215 .p2_slow = 10,
216 .p2_fast = 10
217 },
218 };
219
220 static const intel_limit_t intel_limits_g4x_hdmi = {
221 .dot = { .min = 22000, .max = 400000 },
222 .vco = { .min = 1750000, .max = 3500000},
223 .n = { .min = 1, .max = 4 },
224 .m = { .min = 104, .max = 138 },
225 .m1 = { .min = 16, .max = 23 },
226 .m2 = { .min = 5, .max = 11 },
227 .p = { .min = 5, .max = 80 },
228 .p1 = { .min = 1, .max = 8},
229 .p2 = { .dot_limit = 165000,
230 .p2_slow = 10, .p2_fast = 5 },
231 };
232
233 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
234 .dot = { .min = 20000, .max = 115000 },
235 .vco = { .min = 1750000, .max = 3500000 },
236 .n = { .min = 1, .max = 3 },
237 .m = { .min = 104, .max = 138 },
238 .m1 = { .min = 17, .max = 23 },
239 .m2 = { .min = 5, .max = 11 },
240 .p = { .min = 28, .max = 112 },
241 .p1 = { .min = 2, .max = 8 },
242 .p2 = { .dot_limit = 0,
243 .p2_slow = 14, .p2_fast = 14
244 },
245 };
246
247 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
248 .dot = { .min = 80000, .max = 224000 },
249 .vco = { .min = 1750000, .max = 3500000 },
250 .n = { .min = 1, .max = 3 },
251 .m = { .min = 104, .max = 138 },
252 .m1 = { .min = 17, .max = 23 },
253 .m2 = { .min = 5, .max = 11 },
254 .p = { .min = 14, .max = 42 },
255 .p1 = { .min = 2, .max = 6 },
256 .p2 = { .dot_limit = 0,
257 .p2_slow = 7, .p2_fast = 7
258 },
259 };
260
261 static const intel_limit_t intel_limits_pineview_sdvo = {
262 .dot = { .min = 20000, .max = 400000},
263 .vco = { .min = 1700000, .max = 3500000 },
264 /* Pineview's Ncounter is a ring counter */
265 .n = { .min = 3, .max = 6 },
266 .m = { .min = 2, .max = 256 },
267 /* Pineview only has one combined m divider, which we treat as m2. */
268 .m1 = { .min = 0, .max = 0 },
269 .m2 = { .min = 0, .max = 254 },
270 .p = { .min = 5, .max = 80 },
271 .p1 = { .min = 1, .max = 8 },
272 .p2 = { .dot_limit = 200000,
273 .p2_slow = 10, .p2_fast = 5 },
274 };
275
276 static const intel_limit_t intel_limits_pineview_lvds = {
277 .dot = { .min = 20000, .max = 400000 },
278 .vco = { .min = 1700000, .max = 3500000 },
279 .n = { .min = 3, .max = 6 },
280 .m = { .min = 2, .max = 256 },
281 .m1 = { .min = 0, .max = 0 },
282 .m2 = { .min = 0, .max = 254 },
283 .p = { .min = 7, .max = 112 },
284 .p1 = { .min = 1, .max = 8 },
285 .p2 = { .dot_limit = 112000,
286 .p2_slow = 14, .p2_fast = 14 },
287 };
288
289 /* Ironlake / Sandybridge
290 *
291 * We calculate clock using (register_value + 2) for N/M1/M2, so here
292 * the range value for them is (actual_value - 2).
293 */
294 static const intel_limit_t intel_limits_ironlake_dac = {
295 .dot = { .min = 25000, .max = 350000 },
296 .vco = { .min = 1760000, .max = 3510000 },
297 .n = { .min = 1, .max = 5 },
298 .m = { .min = 79, .max = 127 },
299 .m1 = { .min = 12, .max = 22 },
300 .m2 = { .min = 5, .max = 9 },
301 .p = { .min = 5, .max = 80 },
302 .p1 = { .min = 1, .max = 8 },
303 .p2 = { .dot_limit = 225000,
304 .p2_slow = 10, .p2_fast = 5 },
305 };
306
307 static const intel_limit_t intel_limits_ironlake_single_lvds = {
308 .dot = { .min = 25000, .max = 350000 },
309 .vco = { .min = 1760000, .max = 3510000 },
310 .n = { .min = 1, .max = 3 },
311 .m = { .min = 79, .max = 118 },
312 .m1 = { .min = 12, .max = 22 },
313 .m2 = { .min = 5, .max = 9 },
314 .p = { .min = 28, .max = 112 },
315 .p1 = { .min = 2, .max = 8 },
316 .p2 = { .dot_limit = 225000,
317 .p2_slow = 14, .p2_fast = 14 },
318 };
319
320 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 79, .max = 127 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 14, .max = 56 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 7, .p2_fast = 7 },
331 };
332
333 /* LVDS 100mhz refclk limits. */
334 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
335 .dot = { .min = 25000, .max = 350000 },
336 .vco = { .min = 1760000, .max = 3510000 },
337 .n = { .min = 1, .max = 2 },
338 .m = { .min = 79, .max = 126 },
339 .m1 = { .min = 12, .max = 22 },
340 .m2 = { .min = 5, .max = 9 },
341 .p = { .min = 28, .max = 112 },
342 .p1 = { .min = 2, .max = 8 },
343 .p2 = { .dot_limit = 225000,
344 .p2_slow = 14, .p2_fast = 14 },
345 };
346
347 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
348 .dot = { .min = 25000, .max = 350000 },
349 .vco = { .min = 1760000, .max = 3510000 },
350 .n = { .min = 1, .max = 3 },
351 .m = { .min = 79, .max = 126 },
352 .m1 = { .min = 12, .max = 22 },
353 .m2 = { .min = 5, .max = 9 },
354 .p = { .min = 14, .max = 42 },
355 .p1 = { .min = 2, .max = 6 },
356 .p2 = { .dot_limit = 225000,
357 .p2_slow = 7, .p2_fast = 7 },
358 };
359
360 static const intel_limit_t intel_limits_vlv = {
361 /*
362 * These are the data rate limits (measured in fast clocks)
363 * since those are the strictest limits we have. The fast
364 * clock and actual rate limits are more relaxed, so checking
365 * them would make no difference.
366 */
367 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
368 .vco = { .min = 4000000, .max = 6000000 },
369 .n = { .min = 1, .max = 7 },
370 .m1 = { .min = 2, .max = 3 },
371 .m2 = { .min = 11, .max = 156 },
372 .p1 = { .min = 2, .max = 3 },
373 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
374 };
375
376 static const intel_limit_t intel_limits_chv = {
377 /*
378 * These are the data rate limits (measured in fast clocks)
379 * since those are the strictest limits we have. The fast
380 * clock and actual rate limits are more relaxed, so checking
381 * them would make no difference.
382 */
383 .dot = { .min = 25000 * 5, .max = 540000 * 5},
384 .vco = { .min = 4860000, .max = 6700000 },
385 .n = { .min = 1, .max = 1 },
386 .m1 = { .min = 2, .max = 2 },
387 .m2 = { .min = 24 << 22, .max = 175 << 22 },
388 .p1 = { .min = 2, .max = 4 },
389 .p2 = { .p2_slow = 1, .p2_fast = 14 },
390 };
391
392 static void vlv_clock(int refclk, intel_clock_t *clock)
393 {
394 clock->m = clock->m1 * clock->m2;
395 clock->p = clock->p1 * clock->p2;
396 if (WARN_ON(clock->n == 0 || clock->p == 0))
397 return;
398 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
399 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
400 }
401
402 /**
403 * Returns whether any output on the specified pipe is of the specified type
404 */
405 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
406 {
407 struct drm_device *dev = crtc->dev;
408 struct intel_encoder *encoder;
409
410 for_each_encoder_on_crtc(dev, crtc, encoder)
411 if (encoder->type == type)
412 return true;
413
414 return false;
415 }
416
417 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
418 int refclk)
419 {
420 struct drm_device *dev = crtc->dev;
421 const intel_limit_t *limit;
422
423 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
424 if (intel_is_dual_link_lvds(dev)) {
425 if (refclk == 100000)
426 limit = &intel_limits_ironlake_dual_lvds_100m;
427 else
428 limit = &intel_limits_ironlake_dual_lvds;
429 } else {
430 if (refclk == 100000)
431 limit = &intel_limits_ironlake_single_lvds_100m;
432 else
433 limit = &intel_limits_ironlake_single_lvds;
434 }
435 } else
436 limit = &intel_limits_ironlake_dac;
437
438 return limit;
439 }
440
441 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
442 {
443 struct drm_device *dev = crtc->dev;
444 const intel_limit_t *limit;
445
446 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
447 if (intel_is_dual_link_lvds(dev))
448 limit = &intel_limits_g4x_dual_channel_lvds;
449 else
450 limit = &intel_limits_g4x_single_channel_lvds;
451 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
452 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
453 limit = &intel_limits_g4x_hdmi;
454 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
455 limit = &intel_limits_g4x_sdvo;
456 } else /* The option is for other outputs */
457 limit = &intel_limits_i9xx_sdvo;
458
459 return limit;
460 }
461
462 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
463 {
464 struct drm_device *dev = crtc->dev;
465 const intel_limit_t *limit;
466
467 if (HAS_PCH_SPLIT(dev))
468 limit = intel_ironlake_limit(crtc, refclk);
469 else if (IS_G4X(dev)) {
470 limit = intel_g4x_limit(crtc);
471 } else if (IS_PINEVIEW(dev)) {
472 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
473 limit = &intel_limits_pineview_lvds;
474 else
475 limit = &intel_limits_pineview_sdvo;
476 } else if (IS_CHERRYVIEW(dev)) {
477 limit = &intel_limits_chv;
478 } else if (IS_VALLEYVIEW(dev)) {
479 limit = &intel_limits_vlv;
480 } else if (!IS_GEN2(dev)) {
481 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
482 limit = &intel_limits_i9xx_lvds;
483 else
484 limit = &intel_limits_i9xx_sdvo;
485 } else {
486 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
487 limit = &intel_limits_i8xx_lvds;
488 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
489 limit = &intel_limits_i8xx_dvo;
490 else
491 limit = &intel_limits_i8xx_dac;
492 }
493 return limit;
494 }
495
496 /* m1 is reserved as 0 in Pineview, n is a ring counter */
497 static void pineview_clock(int refclk, intel_clock_t *clock)
498 {
499 clock->m = clock->m2 + 2;
500 clock->p = clock->p1 * clock->p2;
501 if (WARN_ON(clock->n == 0 || clock->p == 0))
502 return;
503 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
504 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
505 }
506
507 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
508 {
509 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
510 }
511
512 static void i9xx_clock(int refclk, intel_clock_t *clock)
513 {
514 clock->m = i9xx_dpll_compute_m(clock);
515 clock->p = clock->p1 * clock->p2;
516 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
517 return;
518 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
519 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
520 }
521
522 static void chv_clock(int refclk, intel_clock_t *clock)
523 {
524 clock->m = clock->m1 * clock->m2;
525 clock->p = clock->p1 * clock->p2;
526 if (WARN_ON(clock->n == 0 || clock->p == 0))
527 return;
528 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
529 clock->n << 22);
530 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
531 }
532
533 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
534 /**
535 * Returns whether the given set of divisors are valid for a given refclk with
536 * the given connectors.
537 */
538
539 static bool intel_PLL_is_valid(struct drm_device *dev,
540 const intel_limit_t *limit,
541 const intel_clock_t *clock)
542 {
543 if (clock->n < limit->n.min || limit->n.max < clock->n)
544 INTELPllInvalid("n out of range\n");
545 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
546 INTELPllInvalid("p1 out of range\n");
547 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
548 INTELPllInvalid("m2 out of range\n");
549 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
550 INTELPllInvalid("m1 out of range\n");
551
552 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
553 if (clock->m1 <= clock->m2)
554 INTELPllInvalid("m1 <= m2\n");
555
556 if (!IS_VALLEYVIEW(dev)) {
557 if (clock->p < limit->p.min || limit->p.max < clock->p)
558 INTELPllInvalid("p out of range\n");
559 if (clock->m < limit->m.min || limit->m.max < clock->m)
560 INTELPllInvalid("m out of range\n");
561 }
562
563 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
564 INTELPllInvalid("vco out of range\n");
565 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
566 * connector, etc., rather than just a single range.
567 */
568 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
569 INTELPllInvalid("dot out of range\n");
570
571 return true;
572 }
573
574 static bool
575 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
576 int target, int refclk, intel_clock_t *match_clock,
577 intel_clock_t *best_clock)
578 {
579 struct drm_device *dev = crtc->dev;
580 intel_clock_t clock;
581 int err = target;
582
583 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
584 /*
585 * For LVDS just rely on its current settings for dual-channel.
586 * We haven't figured out how to reliably set up different
587 * single/dual channel state, if we even can.
588 */
589 if (intel_is_dual_link_lvds(dev))
590 clock.p2 = limit->p2.p2_fast;
591 else
592 clock.p2 = limit->p2.p2_slow;
593 } else {
594 if (target < limit->p2.dot_limit)
595 clock.p2 = limit->p2.p2_slow;
596 else
597 clock.p2 = limit->p2.p2_fast;
598 }
599
600 memset(best_clock, 0, sizeof(*best_clock));
601
602 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
603 clock.m1++) {
604 for (clock.m2 = limit->m2.min;
605 clock.m2 <= limit->m2.max; clock.m2++) {
606 if (clock.m2 >= clock.m1)
607 break;
608 for (clock.n = limit->n.min;
609 clock.n <= limit->n.max; clock.n++) {
610 for (clock.p1 = limit->p1.min;
611 clock.p1 <= limit->p1.max; clock.p1++) {
612 int this_err;
613
614 i9xx_clock(refclk, &clock);
615 if (!intel_PLL_is_valid(dev, limit,
616 &clock))
617 continue;
618 if (match_clock &&
619 clock.p != match_clock->p)
620 continue;
621
622 this_err = abs(clock.dot - target);
623 if (this_err < err) {
624 *best_clock = clock;
625 err = this_err;
626 }
627 }
628 }
629 }
630 }
631
632 return (err != target);
633 }
634
635 static bool
636 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
637 int target, int refclk, intel_clock_t *match_clock,
638 intel_clock_t *best_clock)
639 {
640 struct drm_device *dev = crtc->dev;
641 intel_clock_t clock;
642 int err = target;
643
644 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
645 /*
646 * For LVDS just rely on its current settings for dual-channel.
647 * We haven't figured out how to reliably set up different
648 * single/dual channel state, if we even can.
649 */
650 if (intel_is_dual_link_lvds(dev))
651 clock.p2 = limit->p2.p2_fast;
652 else
653 clock.p2 = limit->p2.p2_slow;
654 } else {
655 if (target < limit->p2.dot_limit)
656 clock.p2 = limit->p2.p2_slow;
657 else
658 clock.p2 = limit->p2.p2_fast;
659 }
660
661 memset(best_clock, 0, sizeof(*best_clock));
662
663 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
664 clock.m1++) {
665 for (clock.m2 = limit->m2.min;
666 clock.m2 <= limit->m2.max; clock.m2++) {
667 for (clock.n = limit->n.min;
668 clock.n <= limit->n.max; clock.n++) {
669 for (clock.p1 = limit->p1.min;
670 clock.p1 <= limit->p1.max; clock.p1++) {
671 int this_err;
672
673 pineview_clock(refclk, &clock);
674 if (!intel_PLL_is_valid(dev, limit,
675 &clock))
676 continue;
677 if (match_clock &&
678 clock.p != match_clock->p)
679 continue;
680
681 this_err = abs(clock.dot - target);
682 if (this_err < err) {
683 *best_clock = clock;
684 err = this_err;
685 }
686 }
687 }
688 }
689 }
690
691 return (err != target);
692 }
693
694 static bool
695 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
696 int target, int refclk, intel_clock_t *match_clock,
697 intel_clock_t *best_clock)
698 {
699 struct drm_device *dev = crtc->dev;
700 intel_clock_t clock;
701 int max_n;
702 bool found;
703 /* approximately equals target * 0.00585 */
704 int err_most = (target >> 8) + (target >> 9);
705 found = false;
706
707 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
708 if (intel_is_dual_link_lvds(dev))
709 clock.p2 = limit->p2.p2_fast;
710 else
711 clock.p2 = limit->p2.p2_slow;
712 } else {
713 if (target < limit->p2.dot_limit)
714 clock.p2 = limit->p2.p2_slow;
715 else
716 clock.p2 = limit->p2.p2_fast;
717 }
718
719 memset(best_clock, 0, sizeof(*best_clock));
720 max_n = limit->n.max;
721 /* based on hardware requirement, prefer smaller n to precision */
722 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
723 /* based on hardware requirement, prefere larger m1,m2 */
724 for (clock.m1 = limit->m1.max;
725 clock.m1 >= limit->m1.min; clock.m1--) {
726 for (clock.m2 = limit->m2.max;
727 clock.m2 >= limit->m2.min; clock.m2--) {
728 for (clock.p1 = limit->p1.max;
729 clock.p1 >= limit->p1.min; clock.p1--) {
730 int this_err;
731
732 i9xx_clock(refclk, &clock);
733 if (!intel_PLL_is_valid(dev, limit,
734 &clock))
735 continue;
736
737 this_err = abs(clock.dot - target);
738 if (this_err < err_most) {
739 *best_clock = clock;
740 err_most = this_err;
741 max_n = clock.n;
742 found = true;
743 }
744 }
745 }
746 }
747 }
748 return found;
749 }
750
751 static bool
752 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
753 int target, int refclk, intel_clock_t *match_clock,
754 intel_clock_t *best_clock)
755 {
756 struct drm_device *dev = crtc->dev;
757 intel_clock_t clock;
758 unsigned int bestppm = 1000000;
759 /* min update 19.2 MHz */
760 int max_n = min(limit->n.max, refclk / 19200);
761 bool found = false;
762
763 target *= 5; /* fast clock */
764
765 memset(best_clock, 0, sizeof(*best_clock));
766
767 /* based on hardware requirement, prefer smaller n to precision */
768 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
769 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
770 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
771 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
772 clock.p = clock.p1 * clock.p2;
773 /* based on hardware requirement, prefer bigger m1,m2 values */
774 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
775 unsigned int ppm, diff;
776
777 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
778 refclk * clock.m1);
779
780 vlv_clock(refclk, &clock);
781
782 if (!intel_PLL_is_valid(dev, limit,
783 &clock))
784 continue;
785
786 diff = abs(clock.dot - target);
787 ppm = div_u64(1000000ULL * diff, target);
788
789 if (ppm < 100 && clock.p > best_clock->p) {
790 bestppm = 0;
791 *best_clock = clock;
792 found = true;
793 }
794
795 if (bestppm >= 10 && ppm < bestppm - 10) {
796 bestppm = ppm;
797 *best_clock = clock;
798 found = true;
799 }
800 }
801 }
802 }
803 }
804
805 return found;
806 }
807
808 static bool
809 chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
810 int target, int refclk, intel_clock_t *match_clock,
811 intel_clock_t *best_clock)
812 {
813 struct drm_device *dev = crtc->dev;
814 intel_clock_t clock;
815 uint64_t m2;
816 int found = false;
817
818 memset(best_clock, 0, sizeof(*best_clock));
819
820 /*
821 * Based on hardware doc, the n always set to 1, and m1 always
822 * set to 2. If requires to support 200Mhz refclk, we need to
823 * revisit this because n may not 1 anymore.
824 */
825 clock.n = 1, clock.m1 = 2;
826 target *= 5; /* fast clock */
827
828 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
829 for (clock.p2 = limit->p2.p2_fast;
830 clock.p2 >= limit->p2.p2_slow;
831 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
832
833 clock.p = clock.p1 * clock.p2;
834
835 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
836 clock.n) << 22, refclk * clock.m1);
837
838 if (m2 > INT_MAX/clock.m1)
839 continue;
840
841 clock.m2 = m2;
842
843 chv_clock(refclk, &clock);
844
845 if (!intel_PLL_is_valid(dev, limit, &clock))
846 continue;
847
848 /* based on hardware requirement, prefer bigger p
849 */
850 if (clock.p > best_clock->p) {
851 *best_clock = clock;
852 found = true;
853 }
854 }
855 }
856
857 return found;
858 }
859
860 bool intel_crtc_active(struct drm_crtc *crtc)
861 {
862 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
863
864 /* Be paranoid as we can arrive here with only partial
865 * state retrieved from the hardware during setup.
866 *
867 * We can ditch the adjusted_mode.crtc_clock check as soon
868 * as Haswell has gained clock readout/fastboot support.
869 *
870 * We can ditch the crtc->primary->fb check as soon as we can
871 * properly reconstruct framebuffers.
872 */
873 return intel_crtc->active && crtc->primary->fb &&
874 intel_crtc->config.adjusted_mode.crtc_clock;
875 }
876
877 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
878 enum pipe pipe)
879 {
880 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
881 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
882
883 return intel_crtc->config.cpu_transcoder;
884 }
885
886 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
887 {
888 struct drm_i915_private *dev_priv = dev->dev_private;
889 u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
890
891 frame = I915_READ(frame_reg);
892
893 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
894 WARN(1, "vblank wait timed out\n");
895 }
896
897 /**
898 * intel_wait_for_vblank - wait for vblank on a given pipe
899 * @dev: drm device
900 * @pipe: pipe to wait for
901 *
902 * Wait for vblank to occur on a given pipe. Needed for various bits of
903 * mode setting code.
904 */
905 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
906 {
907 struct drm_i915_private *dev_priv = dev->dev_private;
908 int pipestat_reg = PIPESTAT(pipe);
909
910 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
911 g4x_wait_for_vblank(dev, pipe);
912 return;
913 }
914
915 /* Clear existing vblank status. Note this will clear any other
916 * sticky status fields as well.
917 *
918 * This races with i915_driver_irq_handler() with the result
919 * that either function could miss a vblank event. Here it is not
920 * fatal, as we will either wait upon the next vblank interrupt or
921 * timeout. Generally speaking intel_wait_for_vblank() is only
922 * called during modeset at which time the GPU should be idle and
923 * should *not* be performing page flips and thus not waiting on
924 * vblanks...
925 * Currently, the result of us stealing a vblank from the irq
926 * handler is that a single frame will be skipped during swapbuffers.
927 */
928 I915_WRITE(pipestat_reg,
929 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
930
931 /* Wait for vblank interrupt bit to set */
932 if (wait_for(I915_READ(pipestat_reg) &
933 PIPE_VBLANK_INTERRUPT_STATUS,
934 50))
935 DRM_DEBUG_KMS("vblank wait timed out\n");
936 }
937
938 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
939 {
940 struct drm_i915_private *dev_priv = dev->dev_private;
941 u32 reg = PIPEDSL(pipe);
942 u32 line1, line2;
943 u32 line_mask;
944
945 if (IS_GEN2(dev))
946 line_mask = DSL_LINEMASK_GEN2;
947 else
948 line_mask = DSL_LINEMASK_GEN3;
949
950 line1 = I915_READ(reg) & line_mask;
951 mdelay(5);
952 line2 = I915_READ(reg) & line_mask;
953
954 return line1 == line2;
955 }
956
957 /*
958 * intel_wait_for_pipe_off - wait for pipe to turn off
959 * @dev: drm device
960 * @pipe: pipe to wait for
961 *
962 * After disabling a pipe, we can't wait for vblank in the usual way,
963 * spinning on the vblank interrupt status bit, since we won't actually
964 * see an interrupt when the pipe is disabled.
965 *
966 * On Gen4 and above:
967 * wait for the pipe register state bit to turn off
968 *
969 * Otherwise:
970 * wait for the display line value to settle (it usually
971 * ends up stopping at the start of the next frame).
972 *
973 */
974 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
975 {
976 struct drm_i915_private *dev_priv = dev->dev_private;
977 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
978 pipe);
979
980 if (INTEL_INFO(dev)->gen >= 4) {
981 int reg = PIPECONF(cpu_transcoder);
982
983 /* Wait for the Pipe State to go off */
984 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
985 100))
986 WARN(1, "pipe_off wait timed out\n");
987 } else {
988 /* Wait for the display line to settle */
989 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
990 WARN(1, "pipe_off wait timed out\n");
991 }
992 }
993
994 /*
995 * ibx_digital_port_connected - is the specified port connected?
996 * @dev_priv: i915 private structure
997 * @port: the port to test
998 *
999 * Returns true if @port is connected, false otherwise.
1000 */
1001 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1002 struct intel_digital_port *port)
1003 {
1004 u32 bit;
1005
1006 if (HAS_PCH_IBX(dev_priv->dev)) {
1007 switch (port->port) {
1008 case PORT_B:
1009 bit = SDE_PORTB_HOTPLUG;
1010 break;
1011 case PORT_C:
1012 bit = SDE_PORTC_HOTPLUG;
1013 break;
1014 case PORT_D:
1015 bit = SDE_PORTD_HOTPLUG;
1016 break;
1017 default:
1018 return true;
1019 }
1020 } else {
1021 switch (port->port) {
1022 case PORT_B:
1023 bit = SDE_PORTB_HOTPLUG_CPT;
1024 break;
1025 case PORT_C:
1026 bit = SDE_PORTC_HOTPLUG_CPT;
1027 break;
1028 case PORT_D:
1029 bit = SDE_PORTD_HOTPLUG_CPT;
1030 break;
1031 default:
1032 return true;
1033 }
1034 }
1035
1036 return I915_READ(SDEISR) & bit;
1037 }
1038
1039 static const char *state_string(bool enabled)
1040 {
1041 return enabled ? "on" : "off";
1042 }
1043
1044 /* Only for pre-ILK configs */
1045 void assert_pll(struct drm_i915_private *dev_priv,
1046 enum pipe pipe, bool state)
1047 {
1048 int reg;
1049 u32 val;
1050 bool cur_state;
1051
1052 reg = DPLL(pipe);
1053 val = I915_READ(reg);
1054 cur_state = !!(val & DPLL_VCO_ENABLE);
1055 WARN(cur_state != state,
1056 "PLL state assertion failure (expected %s, current %s)\n",
1057 state_string(state), state_string(cur_state));
1058 }
1059
1060 /* XXX: the dsi pll is shared between MIPI DSI ports */
1061 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1062 {
1063 u32 val;
1064 bool cur_state;
1065
1066 mutex_lock(&dev_priv->dpio_lock);
1067 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1068 mutex_unlock(&dev_priv->dpio_lock);
1069
1070 cur_state = val & DSI_PLL_VCO_EN;
1071 WARN(cur_state != state,
1072 "DSI PLL state assertion failure (expected %s, current %s)\n",
1073 state_string(state), state_string(cur_state));
1074 }
1075 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1076 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1077
1078 struct intel_shared_dpll *
1079 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1080 {
1081 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1082
1083 if (crtc->config.shared_dpll < 0)
1084 return NULL;
1085
1086 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1087 }
1088
1089 /* For ILK+ */
1090 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1091 struct intel_shared_dpll *pll,
1092 bool state)
1093 {
1094 bool cur_state;
1095 struct intel_dpll_hw_state hw_state;
1096
1097 if (HAS_PCH_LPT(dev_priv->dev)) {
1098 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1099 return;
1100 }
1101
1102 if (WARN (!pll,
1103 "asserting DPLL %s with no DPLL\n", state_string(state)))
1104 return;
1105
1106 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1107 WARN(cur_state != state,
1108 "%s assertion failure (expected %s, current %s)\n",
1109 pll->name, state_string(state), state_string(cur_state));
1110 }
1111
1112 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1113 enum pipe pipe, bool state)
1114 {
1115 int reg;
1116 u32 val;
1117 bool cur_state;
1118 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1119 pipe);
1120
1121 if (HAS_DDI(dev_priv->dev)) {
1122 /* DDI does not have a specific FDI_TX register */
1123 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1124 val = I915_READ(reg);
1125 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1126 } else {
1127 reg = FDI_TX_CTL(pipe);
1128 val = I915_READ(reg);
1129 cur_state = !!(val & FDI_TX_ENABLE);
1130 }
1131 WARN(cur_state != state,
1132 "FDI TX state assertion failure (expected %s, current %s)\n",
1133 state_string(state), state_string(cur_state));
1134 }
1135 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1136 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1137
1138 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1139 enum pipe pipe, bool state)
1140 {
1141 int reg;
1142 u32 val;
1143 bool cur_state;
1144
1145 reg = FDI_RX_CTL(pipe);
1146 val = I915_READ(reg);
1147 cur_state = !!(val & FDI_RX_ENABLE);
1148 WARN(cur_state != state,
1149 "FDI RX state assertion failure (expected %s, current %s)\n",
1150 state_string(state), state_string(cur_state));
1151 }
1152 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1153 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1154
1155 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1156 enum pipe pipe)
1157 {
1158 int reg;
1159 u32 val;
1160
1161 /* ILK FDI PLL is always enabled */
1162 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1163 return;
1164
1165 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1166 if (HAS_DDI(dev_priv->dev))
1167 return;
1168
1169 reg = FDI_TX_CTL(pipe);
1170 val = I915_READ(reg);
1171 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1172 }
1173
1174 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1175 enum pipe pipe, bool state)
1176 {
1177 int reg;
1178 u32 val;
1179 bool cur_state;
1180
1181 reg = FDI_RX_CTL(pipe);
1182 val = I915_READ(reg);
1183 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1184 WARN(cur_state != state,
1185 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1186 state_string(state), state_string(cur_state));
1187 }
1188
1189 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1190 enum pipe pipe)
1191 {
1192 int pp_reg, lvds_reg;
1193 u32 val;
1194 enum pipe panel_pipe = PIPE_A;
1195 bool locked = true;
1196
1197 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1198 pp_reg = PCH_PP_CONTROL;
1199 lvds_reg = PCH_LVDS;
1200 } else {
1201 pp_reg = PP_CONTROL;
1202 lvds_reg = LVDS;
1203 }
1204
1205 val = I915_READ(pp_reg);
1206 if (!(val & PANEL_POWER_ON) ||
1207 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1208 locked = false;
1209
1210 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1211 panel_pipe = PIPE_B;
1212
1213 WARN(panel_pipe == pipe && locked,
1214 "panel assertion failure, pipe %c regs locked\n",
1215 pipe_name(pipe));
1216 }
1217
1218 static void assert_cursor(struct drm_i915_private *dev_priv,
1219 enum pipe pipe, bool state)
1220 {
1221 struct drm_device *dev = dev_priv->dev;
1222 bool cur_state;
1223
1224 if (IS_845G(dev) || IS_I865G(dev))
1225 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1226 else
1227 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1228
1229 WARN(cur_state != state,
1230 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1231 pipe_name(pipe), state_string(state), state_string(cur_state));
1232 }
1233 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1234 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1235
1236 void assert_pipe(struct drm_i915_private *dev_priv,
1237 enum pipe pipe, bool state)
1238 {
1239 int reg;
1240 u32 val;
1241 bool cur_state;
1242 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1243 pipe);
1244
1245 /* if we need the pipe A quirk it must be always on */
1246 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1247 state = true;
1248
1249 if (!intel_display_power_enabled(dev_priv,
1250 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1251 cur_state = false;
1252 } else {
1253 reg = PIPECONF(cpu_transcoder);
1254 val = I915_READ(reg);
1255 cur_state = !!(val & PIPECONF_ENABLE);
1256 }
1257
1258 WARN(cur_state != state,
1259 "pipe %c assertion failure (expected %s, current %s)\n",
1260 pipe_name(pipe), state_string(state), state_string(cur_state));
1261 }
1262
1263 static void assert_plane(struct drm_i915_private *dev_priv,
1264 enum plane plane, bool state)
1265 {
1266 int reg;
1267 u32 val;
1268 bool cur_state;
1269
1270 reg = DSPCNTR(plane);
1271 val = I915_READ(reg);
1272 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1273 WARN(cur_state != state,
1274 "plane %c assertion failure (expected %s, current %s)\n",
1275 plane_name(plane), state_string(state), state_string(cur_state));
1276 }
1277
1278 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1279 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1280
1281 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1282 enum pipe pipe)
1283 {
1284 struct drm_device *dev = dev_priv->dev;
1285 int reg, i;
1286 u32 val;
1287 int cur_pipe;
1288
1289 /* Primary planes are fixed to pipes on gen4+ */
1290 if (INTEL_INFO(dev)->gen >= 4) {
1291 reg = DSPCNTR(pipe);
1292 val = I915_READ(reg);
1293 WARN(val & DISPLAY_PLANE_ENABLE,
1294 "plane %c assertion failure, should be disabled but not\n",
1295 plane_name(pipe));
1296 return;
1297 }
1298
1299 /* Need to check both planes against the pipe */
1300 for_each_pipe(i) {
1301 reg = DSPCNTR(i);
1302 val = I915_READ(reg);
1303 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1304 DISPPLANE_SEL_PIPE_SHIFT;
1305 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1306 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1307 plane_name(i), pipe_name(pipe));
1308 }
1309 }
1310
1311 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1312 enum pipe pipe)
1313 {
1314 struct drm_device *dev = dev_priv->dev;
1315 int reg, sprite;
1316 u32 val;
1317
1318 if (IS_VALLEYVIEW(dev)) {
1319 for_each_sprite(pipe, sprite) {
1320 reg = SPCNTR(pipe, sprite);
1321 val = I915_READ(reg);
1322 WARN(val & SP_ENABLE,
1323 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1324 sprite_name(pipe, sprite), pipe_name(pipe));
1325 }
1326 } else if (INTEL_INFO(dev)->gen >= 7) {
1327 reg = SPRCTL(pipe);
1328 val = I915_READ(reg);
1329 WARN(val & SPRITE_ENABLE,
1330 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1331 plane_name(pipe), pipe_name(pipe));
1332 } else if (INTEL_INFO(dev)->gen >= 5) {
1333 reg = DVSCNTR(pipe);
1334 val = I915_READ(reg);
1335 WARN(val & DVS_ENABLE,
1336 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1337 plane_name(pipe), pipe_name(pipe));
1338 }
1339 }
1340
1341 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1342 {
1343 u32 val;
1344 bool enabled;
1345
1346 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1347
1348 val = I915_READ(PCH_DREF_CONTROL);
1349 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1350 DREF_SUPERSPREAD_SOURCE_MASK));
1351 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1352 }
1353
1354 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1355 enum pipe pipe)
1356 {
1357 int reg;
1358 u32 val;
1359 bool enabled;
1360
1361 reg = PCH_TRANSCONF(pipe);
1362 val = I915_READ(reg);
1363 enabled = !!(val & TRANS_ENABLE);
1364 WARN(enabled,
1365 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1366 pipe_name(pipe));
1367 }
1368
1369 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1370 enum pipe pipe, u32 port_sel, u32 val)
1371 {
1372 if ((val & DP_PORT_EN) == 0)
1373 return false;
1374
1375 if (HAS_PCH_CPT(dev_priv->dev)) {
1376 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1377 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1378 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1379 return false;
1380 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1381 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1382 return false;
1383 } else {
1384 if ((val & DP_PIPE_MASK) != (pipe << 30))
1385 return false;
1386 }
1387 return true;
1388 }
1389
1390 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1391 enum pipe pipe, u32 val)
1392 {
1393 if ((val & SDVO_ENABLE) == 0)
1394 return false;
1395
1396 if (HAS_PCH_CPT(dev_priv->dev)) {
1397 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1398 return false;
1399 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1400 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1401 return false;
1402 } else {
1403 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1404 return false;
1405 }
1406 return true;
1407 }
1408
1409 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1410 enum pipe pipe, u32 val)
1411 {
1412 if ((val & LVDS_PORT_EN) == 0)
1413 return false;
1414
1415 if (HAS_PCH_CPT(dev_priv->dev)) {
1416 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1417 return false;
1418 } else {
1419 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1420 return false;
1421 }
1422 return true;
1423 }
1424
1425 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1426 enum pipe pipe, u32 val)
1427 {
1428 if ((val & ADPA_DAC_ENABLE) == 0)
1429 return false;
1430 if (HAS_PCH_CPT(dev_priv->dev)) {
1431 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1432 return false;
1433 } else {
1434 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1435 return false;
1436 }
1437 return true;
1438 }
1439
1440 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1441 enum pipe pipe, int reg, u32 port_sel)
1442 {
1443 u32 val = I915_READ(reg);
1444 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1445 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1446 reg, pipe_name(pipe));
1447
1448 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1449 && (val & DP_PIPEB_SELECT),
1450 "IBX PCH dp port still using transcoder B\n");
1451 }
1452
1453 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1454 enum pipe pipe, int reg)
1455 {
1456 u32 val = I915_READ(reg);
1457 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1458 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1459 reg, pipe_name(pipe));
1460
1461 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1462 && (val & SDVO_PIPE_B_SELECT),
1463 "IBX PCH hdmi port still using transcoder B\n");
1464 }
1465
1466 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1467 enum pipe pipe)
1468 {
1469 int reg;
1470 u32 val;
1471
1472 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1473 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1474 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1475
1476 reg = PCH_ADPA;
1477 val = I915_READ(reg);
1478 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1479 "PCH VGA enabled on transcoder %c, should be disabled\n",
1480 pipe_name(pipe));
1481
1482 reg = PCH_LVDS;
1483 val = I915_READ(reg);
1484 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1485 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1486 pipe_name(pipe));
1487
1488 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1489 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1490 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1491 }
1492
1493 static void intel_init_dpio(struct drm_device *dev)
1494 {
1495 struct drm_i915_private *dev_priv = dev->dev_private;
1496
1497 if (!IS_VALLEYVIEW(dev))
1498 return;
1499
1500 /*
1501 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1502 * CHV x1 PHY (DP/HDMI D)
1503 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1504 */
1505 if (IS_CHERRYVIEW(dev)) {
1506 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1507 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1508 } else {
1509 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1510 }
1511 }
1512
1513 static void intel_reset_dpio(struct drm_device *dev)
1514 {
1515 struct drm_i915_private *dev_priv = dev->dev_private;
1516
1517 if (!IS_VALLEYVIEW(dev))
1518 return;
1519
1520 if (IS_CHERRYVIEW(dev)) {
1521 enum dpio_phy phy;
1522 u32 val;
1523
1524 for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) {
1525 /* Poll for phypwrgood signal */
1526 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) &
1527 PHY_POWERGOOD(phy), 1))
1528 DRM_ERROR("Display PHY %d is not power up\n", phy);
1529
1530 /*
1531 * Deassert common lane reset for PHY.
1532 *
1533 * This should only be done on init and resume from S3
1534 * with both PLLs disabled, or we risk losing DPIO and
1535 * PLL synchronization.
1536 */
1537 val = I915_READ(DISPLAY_PHY_CONTROL);
1538 I915_WRITE(DISPLAY_PHY_CONTROL,
1539 PHY_COM_LANE_RESET_DEASSERT(phy, val));
1540 }
1541
1542 } else {
1543 /*
1544 * If DPIO has already been reset, e.g. by BIOS, just skip all
1545 * this.
1546 */
1547 if (I915_READ(DPIO_CTL) & DPIO_CMNRST)
1548 return;
1549
1550 /*
1551 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
1552 * Need to assert and de-assert PHY SB reset by gating the
1553 * common lane power, then un-gating it.
1554 * Simply ungating isn't enough to reset the PHY enough to get
1555 * ports and lanes running.
1556 */
1557 __vlv_set_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC,
1558 false);
1559 __vlv_set_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC,
1560 true);
1561 }
1562 }
1563
1564 static void vlv_enable_pll(struct intel_crtc *crtc)
1565 {
1566 struct drm_device *dev = crtc->base.dev;
1567 struct drm_i915_private *dev_priv = dev->dev_private;
1568 int reg = DPLL(crtc->pipe);
1569 u32 dpll = crtc->config.dpll_hw_state.dpll;
1570
1571 assert_pipe_disabled(dev_priv, crtc->pipe);
1572
1573 /* No really, not for ILK+ */
1574 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1575
1576 /* PLL is protected by panel, make sure we can write it */
1577 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1578 assert_panel_unlocked(dev_priv, crtc->pipe);
1579
1580 I915_WRITE(reg, dpll);
1581 POSTING_READ(reg);
1582 udelay(150);
1583
1584 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1585 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1586
1587 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1588 POSTING_READ(DPLL_MD(crtc->pipe));
1589
1590 /* We do this three times for luck */
1591 I915_WRITE(reg, dpll);
1592 POSTING_READ(reg);
1593 udelay(150); /* wait for warmup */
1594 I915_WRITE(reg, dpll);
1595 POSTING_READ(reg);
1596 udelay(150); /* wait for warmup */
1597 I915_WRITE(reg, dpll);
1598 POSTING_READ(reg);
1599 udelay(150); /* wait for warmup */
1600 }
1601
1602 static void chv_enable_pll(struct intel_crtc *crtc)
1603 {
1604 struct drm_device *dev = crtc->base.dev;
1605 struct drm_i915_private *dev_priv = dev->dev_private;
1606 int pipe = crtc->pipe;
1607 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1608 u32 tmp;
1609
1610 assert_pipe_disabled(dev_priv, crtc->pipe);
1611
1612 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1613
1614 mutex_lock(&dev_priv->dpio_lock);
1615
1616 /* Enable back the 10bit clock to display controller */
1617 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1618 tmp |= DPIO_DCLKP_EN;
1619 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1620
1621 /*
1622 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1623 */
1624 udelay(1);
1625
1626 /* Enable PLL */
1627 I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
1628
1629 /* Check PLL is locked */
1630 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1631 DRM_ERROR("PLL %d failed to lock\n", pipe);
1632
1633 /* not sure when this should be written */
1634 I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
1635 POSTING_READ(DPLL_MD(pipe));
1636
1637 mutex_unlock(&dev_priv->dpio_lock);
1638 }
1639
1640 static void i9xx_enable_pll(struct intel_crtc *crtc)
1641 {
1642 struct drm_device *dev = crtc->base.dev;
1643 struct drm_i915_private *dev_priv = dev->dev_private;
1644 int reg = DPLL(crtc->pipe);
1645 u32 dpll = crtc->config.dpll_hw_state.dpll;
1646
1647 assert_pipe_disabled(dev_priv, crtc->pipe);
1648
1649 /* No really, not for ILK+ */
1650 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1651
1652 /* PLL is protected by panel, make sure we can write it */
1653 if (IS_MOBILE(dev) && !IS_I830(dev))
1654 assert_panel_unlocked(dev_priv, crtc->pipe);
1655
1656 I915_WRITE(reg, dpll);
1657
1658 /* Wait for the clocks to stabilize. */
1659 POSTING_READ(reg);
1660 udelay(150);
1661
1662 if (INTEL_INFO(dev)->gen >= 4) {
1663 I915_WRITE(DPLL_MD(crtc->pipe),
1664 crtc->config.dpll_hw_state.dpll_md);
1665 } else {
1666 /* The pixel multiplier can only be updated once the
1667 * DPLL is enabled and the clocks are stable.
1668 *
1669 * So write it again.
1670 */
1671 I915_WRITE(reg, dpll);
1672 }
1673
1674 /* We do this three times for luck */
1675 I915_WRITE(reg, dpll);
1676 POSTING_READ(reg);
1677 udelay(150); /* wait for warmup */
1678 I915_WRITE(reg, dpll);
1679 POSTING_READ(reg);
1680 udelay(150); /* wait for warmup */
1681 I915_WRITE(reg, dpll);
1682 POSTING_READ(reg);
1683 udelay(150); /* wait for warmup */
1684 }
1685
1686 /**
1687 * i9xx_disable_pll - disable a PLL
1688 * @dev_priv: i915 private structure
1689 * @pipe: pipe PLL to disable
1690 *
1691 * Disable the PLL for @pipe, making sure the pipe is off first.
1692 *
1693 * Note! This is for pre-ILK only.
1694 */
1695 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1696 {
1697 /* Don't disable pipe A or pipe A PLLs if needed */
1698 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1699 return;
1700
1701 /* Make sure the pipe isn't still relying on us */
1702 assert_pipe_disabled(dev_priv, pipe);
1703
1704 I915_WRITE(DPLL(pipe), 0);
1705 POSTING_READ(DPLL(pipe));
1706 }
1707
1708 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1709 {
1710 u32 val = 0;
1711
1712 /* Make sure the pipe isn't still relying on us */
1713 assert_pipe_disabled(dev_priv, pipe);
1714
1715 /*
1716 * Leave integrated clock source and reference clock enabled for pipe B.
1717 * The latter is needed for VGA hotplug / manual detection.
1718 */
1719 if (pipe == PIPE_B)
1720 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1721 I915_WRITE(DPLL(pipe), val);
1722 POSTING_READ(DPLL(pipe));
1723
1724 }
1725
1726 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1727 {
1728 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1729 u32 val;
1730
1731 /* Make sure the pipe isn't still relying on us */
1732 assert_pipe_disabled(dev_priv, pipe);
1733
1734 /* Set PLL en = 0 */
1735 val = DPLL_SSC_REF_CLOCK_CHV;
1736 if (pipe != PIPE_A)
1737 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1738 I915_WRITE(DPLL(pipe), val);
1739 POSTING_READ(DPLL(pipe));
1740
1741 mutex_lock(&dev_priv->dpio_lock);
1742
1743 /* Disable 10bit clock to display controller */
1744 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1745 val &= ~DPIO_DCLKP_EN;
1746 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1747
1748 /* disable left/right clock distribution */
1749 if (pipe != PIPE_B) {
1750 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1751 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1752 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1753 } else {
1754 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1755 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1756 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1757 }
1758
1759 mutex_unlock(&dev_priv->dpio_lock);
1760 }
1761
1762 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1763 struct intel_digital_port *dport)
1764 {
1765 u32 port_mask;
1766 int dpll_reg;
1767
1768 switch (dport->port) {
1769 case PORT_B:
1770 port_mask = DPLL_PORTB_READY_MASK;
1771 dpll_reg = DPLL(0);
1772 break;
1773 case PORT_C:
1774 port_mask = DPLL_PORTC_READY_MASK;
1775 dpll_reg = DPLL(0);
1776 break;
1777 case PORT_D:
1778 port_mask = DPLL_PORTD_READY_MASK;
1779 dpll_reg = DPIO_PHY_STATUS;
1780 break;
1781 default:
1782 BUG();
1783 }
1784
1785 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1786 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1787 port_name(dport->port), I915_READ(dpll_reg));
1788 }
1789
1790 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1791 {
1792 struct drm_device *dev = crtc->base.dev;
1793 struct drm_i915_private *dev_priv = dev->dev_private;
1794 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1795
1796 if (WARN_ON(pll == NULL))
1797 return;
1798
1799 WARN_ON(!pll->refcount);
1800 if (pll->active == 0) {
1801 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1802 WARN_ON(pll->on);
1803 assert_shared_dpll_disabled(dev_priv, pll);
1804
1805 pll->mode_set(dev_priv, pll);
1806 }
1807 }
1808
1809 /**
1810 * intel_enable_shared_dpll - enable PCH PLL
1811 * @dev_priv: i915 private structure
1812 * @pipe: pipe PLL to enable
1813 *
1814 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1815 * drives the transcoder clock.
1816 */
1817 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1818 {
1819 struct drm_device *dev = crtc->base.dev;
1820 struct drm_i915_private *dev_priv = dev->dev_private;
1821 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1822
1823 if (WARN_ON(pll == NULL))
1824 return;
1825
1826 if (WARN_ON(pll->refcount == 0))
1827 return;
1828
1829 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1830 pll->name, pll->active, pll->on,
1831 crtc->base.base.id);
1832
1833 if (pll->active++) {
1834 WARN_ON(!pll->on);
1835 assert_shared_dpll_enabled(dev_priv, pll);
1836 return;
1837 }
1838 WARN_ON(pll->on);
1839
1840 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1841 pll->enable(dev_priv, pll);
1842 pll->on = true;
1843 }
1844
1845 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1846 {
1847 struct drm_device *dev = crtc->base.dev;
1848 struct drm_i915_private *dev_priv = dev->dev_private;
1849 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1850
1851 /* PCH only available on ILK+ */
1852 BUG_ON(INTEL_INFO(dev)->gen < 5);
1853 if (WARN_ON(pll == NULL))
1854 return;
1855
1856 if (WARN_ON(pll->refcount == 0))
1857 return;
1858
1859 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1860 pll->name, pll->active, pll->on,
1861 crtc->base.base.id);
1862
1863 if (WARN_ON(pll->active == 0)) {
1864 assert_shared_dpll_disabled(dev_priv, pll);
1865 return;
1866 }
1867
1868 assert_shared_dpll_enabled(dev_priv, pll);
1869 WARN_ON(!pll->on);
1870 if (--pll->active)
1871 return;
1872
1873 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1874 pll->disable(dev_priv, pll);
1875 pll->on = false;
1876 }
1877
1878 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1879 enum pipe pipe)
1880 {
1881 struct drm_device *dev = dev_priv->dev;
1882 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1883 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1884 uint32_t reg, val, pipeconf_val;
1885
1886 /* PCH only available on ILK+ */
1887 BUG_ON(INTEL_INFO(dev)->gen < 5);
1888
1889 /* Make sure PCH DPLL is enabled */
1890 assert_shared_dpll_enabled(dev_priv,
1891 intel_crtc_to_shared_dpll(intel_crtc));
1892
1893 /* FDI must be feeding us bits for PCH ports */
1894 assert_fdi_tx_enabled(dev_priv, pipe);
1895 assert_fdi_rx_enabled(dev_priv, pipe);
1896
1897 if (HAS_PCH_CPT(dev)) {
1898 /* Workaround: Set the timing override bit before enabling the
1899 * pch transcoder. */
1900 reg = TRANS_CHICKEN2(pipe);
1901 val = I915_READ(reg);
1902 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1903 I915_WRITE(reg, val);
1904 }
1905
1906 reg = PCH_TRANSCONF(pipe);
1907 val = I915_READ(reg);
1908 pipeconf_val = I915_READ(PIPECONF(pipe));
1909
1910 if (HAS_PCH_IBX(dev_priv->dev)) {
1911 /*
1912 * make the BPC in transcoder be consistent with
1913 * that in pipeconf reg.
1914 */
1915 val &= ~PIPECONF_BPC_MASK;
1916 val |= pipeconf_val & PIPECONF_BPC_MASK;
1917 }
1918
1919 val &= ~TRANS_INTERLACE_MASK;
1920 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1921 if (HAS_PCH_IBX(dev_priv->dev) &&
1922 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1923 val |= TRANS_LEGACY_INTERLACED_ILK;
1924 else
1925 val |= TRANS_INTERLACED;
1926 else
1927 val |= TRANS_PROGRESSIVE;
1928
1929 I915_WRITE(reg, val | TRANS_ENABLE);
1930 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1931 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1932 }
1933
1934 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1935 enum transcoder cpu_transcoder)
1936 {
1937 u32 val, pipeconf_val;
1938
1939 /* PCH only available on ILK+ */
1940 BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1941
1942 /* FDI must be feeding us bits for PCH ports */
1943 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1944 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1945
1946 /* Workaround: set timing override bit. */
1947 val = I915_READ(_TRANSA_CHICKEN2);
1948 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1949 I915_WRITE(_TRANSA_CHICKEN2, val);
1950
1951 val = TRANS_ENABLE;
1952 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1953
1954 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1955 PIPECONF_INTERLACED_ILK)
1956 val |= TRANS_INTERLACED;
1957 else
1958 val |= TRANS_PROGRESSIVE;
1959
1960 I915_WRITE(LPT_TRANSCONF, val);
1961 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1962 DRM_ERROR("Failed to enable PCH transcoder\n");
1963 }
1964
1965 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1966 enum pipe pipe)
1967 {
1968 struct drm_device *dev = dev_priv->dev;
1969 uint32_t reg, val;
1970
1971 /* FDI relies on the transcoder */
1972 assert_fdi_tx_disabled(dev_priv, pipe);
1973 assert_fdi_rx_disabled(dev_priv, pipe);
1974
1975 /* Ports must be off as well */
1976 assert_pch_ports_disabled(dev_priv, pipe);
1977
1978 reg = PCH_TRANSCONF(pipe);
1979 val = I915_READ(reg);
1980 val &= ~TRANS_ENABLE;
1981 I915_WRITE(reg, val);
1982 /* wait for PCH transcoder off, transcoder state */
1983 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1984 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1985
1986 if (!HAS_PCH_IBX(dev)) {
1987 /* Workaround: Clear the timing override chicken bit again. */
1988 reg = TRANS_CHICKEN2(pipe);
1989 val = I915_READ(reg);
1990 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1991 I915_WRITE(reg, val);
1992 }
1993 }
1994
1995 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1996 {
1997 u32 val;
1998
1999 val = I915_READ(LPT_TRANSCONF);
2000 val &= ~TRANS_ENABLE;
2001 I915_WRITE(LPT_TRANSCONF, val);
2002 /* wait for PCH transcoder off, transcoder state */
2003 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2004 DRM_ERROR("Failed to disable PCH transcoder\n");
2005
2006 /* Workaround: clear timing override bit. */
2007 val = I915_READ(_TRANSA_CHICKEN2);
2008 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2009 I915_WRITE(_TRANSA_CHICKEN2, val);
2010 }
2011
2012 /**
2013 * intel_enable_pipe - enable a pipe, asserting requirements
2014 * @crtc: crtc responsible for the pipe
2015 *
2016 * Enable @crtc's pipe, making sure that various hardware specific requirements
2017 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2018 */
2019 static void intel_enable_pipe(struct intel_crtc *crtc)
2020 {
2021 struct drm_device *dev = crtc->base.dev;
2022 struct drm_i915_private *dev_priv = dev->dev_private;
2023 enum pipe pipe = crtc->pipe;
2024 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2025 pipe);
2026 enum pipe pch_transcoder;
2027 int reg;
2028 u32 val;
2029
2030 assert_planes_disabled(dev_priv, pipe);
2031 assert_cursor_disabled(dev_priv, pipe);
2032 assert_sprites_disabled(dev_priv, pipe);
2033
2034 if (HAS_PCH_LPT(dev_priv->dev))
2035 pch_transcoder = TRANSCODER_A;
2036 else
2037 pch_transcoder = pipe;
2038
2039 /*
2040 * A pipe without a PLL won't actually be able to drive bits from
2041 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2042 * need the check.
2043 */
2044 if (!HAS_PCH_SPLIT(dev_priv->dev))
2045 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
2046 assert_dsi_pll_enabled(dev_priv);
2047 else
2048 assert_pll_enabled(dev_priv, pipe);
2049 else {
2050 if (crtc->config.has_pch_encoder) {
2051 /* if driving the PCH, we need FDI enabled */
2052 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2053 assert_fdi_tx_pll_enabled(dev_priv,
2054 (enum pipe) cpu_transcoder);
2055 }
2056 /* FIXME: assert CPU port conditions for SNB+ */
2057 }
2058
2059 reg = PIPECONF(cpu_transcoder);
2060 val = I915_READ(reg);
2061 if (val & PIPECONF_ENABLE) {
2062 WARN_ON(!(pipe == PIPE_A &&
2063 dev_priv->quirks & QUIRK_PIPEA_FORCE));
2064 return;
2065 }
2066
2067 I915_WRITE(reg, val | PIPECONF_ENABLE);
2068 POSTING_READ(reg);
2069 }
2070
2071 /**
2072 * intel_disable_pipe - disable a pipe, asserting requirements
2073 * @dev_priv: i915 private structure
2074 * @pipe: pipe to disable
2075 *
2076 * Disable @pipe, making sure that various hardware specific requirements
2077 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
2078 *
2079 * @pipe should be %PIPE_A or %PIPE_B.
2080 *
2081 * Will wait until the pipe has shut down before returning.
2082 */
2083 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
2084 enum pipe pipe)
2085 {
2086 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2087 pipe);
2088 int reg;
2089 u32 val;
2090
2091 /*
2092 * Make sure planes won't keep trying to pump pixels to us,
2093 * or we might hang the display.
2094 */
2095 assert_planes_disabled(dev_priv, pipe);
2096 assert_cursor_disabled(dev_priv, pipe);
2097 assert_sprites_disabled(dev_priv, pipe);
2098
2099 /* Don't disable pipe A or pipe A PLLs if needed */
2100 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2101 return;
2102
2103 reg = PIPECONF(cpu_transcoder);
2104 val = I915_READ(reg);
2105 if ((val & PIPECONF_ENABLE) == 0)
2106 return;
2107
2108 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
2109 intel_wait_for_pipe_off(dev_priv->dev, pipe);
2110 }
2111
2112 /*
2113 * Plane regs are double buffered, going from enabled->disabled needs a
2114 * trigger in order to latch. The display address reg provides this.
2115 */
2116 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2117 enum plane plane)
2118 {
2119 struct drm_device *dev = dev_priv->dev;
2120 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2121
2122 I915_WRITE(reg, I915_READ(reg));
2123 POSTING_READ(reg);
2124 }
2125
2126 /**
2127 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2128 * @dev_priv: i915 private structure
2129 * @plane: plane to enable
2130 * @pipe: pipe being fed
2131 *
2132 * Enable @plane on @pipe, making sure that @pipe is running first.
2133 */
2134 static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
2135 enum plane plane, enum pipe pipe)
2136 {
2137 struct intel_crtc *intel_crtc =
2138 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2139 int reg;
2140 u32 val;
2141
2142 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2143 assert_pipe_enabled(dev_priv, pipe);
2144
2145 if (intel_crtc->primary_enabled)
2146 return;
2147
2148 intel_crtc->primary_enabled = true;
2149
2150 reg = DSPCNTR(plane);
2151 val = I915_READ(reg);
2152 WARN_ON(val & DISPLAY_PLANE_ENABLE);
2153
2154 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
2155 intel_flush_primary_plane(dev_priv, plane);
2156 }
2157
2158 /**
2159 * intel_disable_primary_hw_plane - disable the primary hardware plane
2160 * @dev_priv: i915 private structure
2161 * @plane: plane to disable
2162 * @pipe: pipe consuming the data
2163 *
2164 * Disable @plane; should be an independent operation.
2165 */
2166 static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
2167 enum plane plane, enum pipe pipe)
2168 {
2169 struct intel_crtc *intel_crtc =
2170 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2171 int reg;
2172 u32 val;
2173
2174 if (!intel_crtc->primary_enabled)
2175 return;
2176
2177 intel_crtc->primary_enabled = false;
2178
2179 reg = DSPCNTR(plane);
2180 val = I915_READ(reg);
2181 WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0);
2182
2183 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
2184 intel_flush_primary_plane(dev_priv, plane);
2185 }
2186
2187 static bool need_vtd_wa(struct drm_device *dev)
2188 {
2189 #ifdef CONFIG_INTEL_IOMMU
2190 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2191 return true;
2192 #endif
2193 return false;
2194 }
2195
2196 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2197 {
2198 int tile_height;
2199
2200 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2201 return ALIGN(height, tile_height);
2202 }
2203
2204 int
2205 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2206 struct drm_i915_gem_object *obj,
2207 struct intel_engine_cs *pipelined)
2208 {
2209 struct drm_i915_private *dev_priv = dev->dev_private;
2210 u32 alignment;
2211 int ret;
2212
2213 switch (obj->tiling_mode) {
2214 case I915_TILING_NONE:
2215 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2216 alignment = 128 * 1024;
2217 else if (INTEL_INFO(dev)->gen >= 4)
2218 alignment = 4 * 1024;
2219 else
2220 alignment = 64 * 1024;
2221 break;
2222 case I915_TILING_X:
2223 /* pin() will align the object as required by fence */
2224 alignment = 0;
2225 break;
2226 case I915_TILING_Y:
2227 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2228 return -EINVAL;
2229 default:
2230 BUG();
2231 }
2232
2233 /* Note that the w/a also requires 64 PTE of padding following the
2234 * bo. We currently fill all unused PTE with the shadow page and so
2235 * we should always have valid PTE following the scanout preventing
2236 * the VT-d warning.
2237 */
2238 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2239 alignment = 256 * 1024;
2240
2241 dev_priv->mm.interruptible = false;
2242 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2243 if (ret)
2244 goto err_interruptible;
2245
2246 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2247 * fence, whereas 965+ only requires a fence if using
2248 * framebuffer compression. For simplicity, we always install
2249 * a fence as the cost is not that onerous.
2250 */
2251 ret = i915_gem_object_get_fence(obj);
2252 if (ret)
2253 goto err_unpin;
2254
2255 i915_gem_object_pin_fence(obj);
2256
2257 dev_priv->mm.interruptible = true;
2258 return 0;
2259
2260 err_unpin:
2261 i915_gem_object_unpin_from_display_plane(obj);
2262 err_interruptible:
2263 dev_priv->mm.interruptible = true;
2264 return ret;
2265 }
2266
2267 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2268 {
2269 i915_gem_object_unpin_fence(obj);
2270 i915_gem_object_unpin_from_display_plane(obj);
2271 }
2272
2273 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2274 * is assumed to be a power-of-two. */
2275 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2276 unsigned int tiling_mode,
2277 unsigned int cpp,
2278 unsigned int pitch)
2279 {
2280 if (tiling_mode != I915_TILING_NONE) {
2281 unsigned int tile_rows, tiles;
2282
2283 tile_rows = *y / 8;
2284 *y %= 8;
2285
2286 tiles = *x / (512/cpp);
2287 *x %= 512/cpp;
2288
2289 return tile_rows * pitch * 8 + tiles * 4096;
2290 } else {
2291 unsigned int offset;
2292
2293 offset = *y * pitch + *x * cpp;
2294 *y = 0;
2295 *x = (offset & 4095) / cpp;
2296 return offset & -4096;
2297 }
2298 }
2299
2300 int intel_format_to_fourcc(int format)
2301 {
2302 switch (format) {
2303 case DISPPLANE_8BPP:
2304 return DRM_FORMAT_C8;
2305 case DISPPLANE_BGRX555:
2306 return DRM_FORMAT_XRGB1555;
2307 case DISPPLANE_BGRX565:
2308 return DRM_FORMAT_RGB565;
2309 default:
2310 case DISPPLANE_BGRX888:
2311 return DRM_FORMAT_XRGB8888;
2312 case DISPPLANE_RGBX888:
2313 return DRM_FORMAT_XBGR8888;
2314 case DISPPLANE_BGRX101010:
2315 return DRM_FORMAT_XRGB2101010;
2316 case DISPPLANE_RGBX101010:
2317 return DRM_FORMAT_XBGR2101010;
2318 }
2319 }
2320
2321 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2322 struct intel_plane_config *plane_config)
2323 {
2324 struct drm_device *dev = crtc->base.dev;
2325 struct drm_i915_gem_object *obj = NULL;
2326 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2327 u32 base = plane_config->base;
2328
2329 if (plane_config->size == 0)
2330 return false;
2331
2332 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2333 plane_config->size);
2334 if (!obj)
2335 return false;
2336
2337 if (plane_config->tiled) {
2338 obj->tiling_mode = I915_TILING_X;
2339 obj->stride = crtc->base.primary->fb->pitches[0];
2340 }
2341
2342 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2343 mode_cmd.width = crtc->base.primary->fb->width;
2344 mode_cmd.height = crtc->base.primary->fb->height;
2345 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2346
2347 mutex_lock(&dev->struct_mutex);
2348
2349 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2350 &mode_cmd, obj)) {
2351 DRM_DEBUG_KMS("intel fb init failed\n");
2352 goto out_unref_obj;
2353 }
2354
2355 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2356 mutex_unlock(&dev->struct_mutex);
2357
2358 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2359 return true;
2360
2361 out_unref_obj:
2362 drm_gem_object_unreference(&obj->base);
2363 mutex_unlock(&dev->struct_mutex);
2364 return false;
2365 }
2366
2367 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2368 struct intel_plane_config *plane_config)
2369 {
2370 struct drm_device *dev = intel_crtc->base.dev;
2371 struct drm_crtc *c;
2372 struct intel_crtc *i;
2373 struct intel_framebuffer *fb;
2374
2375 if (!intel_crtc->base.primary->fb)
2376 return;
2377
2378 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2379 return;
2380
2381 kfree(intel_crtc->base.primary->fb);
2382 intel_crtc->base.primary->fb = NULL;
2383
2384 /*
2385 * Failed to alloc the obj, check to see if we should share
2386 * an fb with another CRTC instead
2387 */
2388 for_each_crtc(dev, c) {
2389 i = to_intel_crtc(c);
2390
2391 if (c == &intel_crtc->base)
2392 continue;
2393
2394 if (!i->active || !c->primary->fb)
2395 continue;
2396
2397 fb = to_intel_framebuffer(c->primary->fb);
2398 if (i915_gem_obj_ggtt_offset(fb->obj) == plane_config->base) {
2399 drm_framebuffer_reference(c->primary->fb);
2400 intel_crtc->base.primary->fb = c->primary->fb;
2401 fb->obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2402 break;
2403 }
2404 }
2405 }
2406
2407 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2408 struct drm_framebuffer *fb,
2409 int x, int y)
2410 {
2411 struct drm_device *dev = crtc->dev;
2412 struct drm_i915_private *dev_priv = dev->dev_private;
2413 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2414 struct intel_framebuffer *intel_fb;
2415 struct drm_i915_gem_object *obj;
2416 int plane = intel_crtc->plane;
2417 unsigned long linear_offset;
2418 u32 dspcntr;
2419 u32 reg;
2420
2421 intel_fb = to_intel_framebuffer(fb);
2422 obj = intel_fb->obj;
2423
2424 reg = DSPCNTR(plane);
2425 dspcntr = I915_READ(reg);
2426 /* Mask out pixel format bits in case we change it */
2427 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2428 switch (fb->pixel_format) {
2429 case DRM_FORMAT_C8:
2430 dspcntr |= DISPPLANE_8BPP;
2431 break;
2432 case DRM_FORMAT_XRGB1555:
2433 case DRM_FORMAT_ARGB1555:
2434 dspcntr |= DISPPLANE_BGRX555;
2435 break;
2436 case DRM_FORMAT_RGB565:
2437 dspcntr |= DISPPLANE_BGRX565;
2438 break;
2439 case DRM_FORMAT_XRGB8888:
2440 case DRM_FORMAT_ARGB8888:
2441 dspcntr |= DISPPLANE_BGRX888;
2442 break;
2443 case DRM_FORMAT_XBGR8888:
2444 case DRM_FORMAT_ABGR8888:
2445 dspcntr |= DISPPLANE_RGBX888;
2446 break;
2447 case DRM_FORMAT_XRGB2101010:
2448 case DRM_FORMAT_ARGB2101010:
2449 dspcntr |= DISPPLANE_BGRX101010;
2450 break;
2451 case DRM_FORMAT_XBGR2101010:
2452 case DRM_FORMAT_ABGR2101010:
2453 dspcntr |= DISPPLANE_RGBX101010;
2454 break;
2455 default:
2456 BUG();
2457 }
2458
2459 if (INTEL_INFO(dev)->gen >= 4) {
2460 if (obj->tiling_mode != I915_TILING_NONE)
2461 dspcntr |= DISPPLANE_TILED;
2462 else
2463 dspcntr &= ~DISPPLANE_TILED;
2464 }
2465
2466 if (IS_G4X(dev))
2467 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2468
2469 I915_WRITE(reg, dspcntr);
2470
2471 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2472
2473 if (INTEL_INFO(dev)->gen >= 4) {
2474 intel_crtc->dspaddr_offset =
2475 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2476 fb->bits_per_pixel / 8,
2477 fb->pitches[0]);
2478 linear_offset -= intel_crtc->dspaddr_offset;
2479 } else {
2480 intel_crtc->dspaddr_offset = linear_offset;
2481 }
2482
2483 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2484 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2485 fb->pitches[0]);
2486 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2487 if (INTEL_INFO(dev)->gen >= 4) {
2488 I915_WRITE(DSPSURF(plane),
2489 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2490 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2491 I915_WRITE(DSPLINOFF(plane), linear_offset);
2492 } else
2493 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2494 POSTING_READ(reg);
2495 }
2496
2497 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2498 struct drm_framebuffer *fb,
2499 int x, int y)
2500 {
2501 struct drm_device *dev = crtc->dev;
2502 struct drm_i915_private *dev_priv = dev->dev_private;
2503 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2504 struct intel_framebuffer *intel_fb;
2505 struct drm_i915_gem_object *obj;
2506 int plane = intel_crtc->plane;
2507 unsigned long linear_offset;
2508 u32 dspcntr;
2509 u32 reg;
2510
2511 intel_fb = to_intel_framebuffer(fb);
2512 obj = intel_fb->obj;
2513
2514 reg = DSPCNTR(plane);
2515 dspcntr = I915_READ(reg);
2516 /* Mask out pixel format bits in case we change it */
2517 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2518 switch (fb->pixel_format) {
2519 case DRM_FORMAT_C8:
2520 dspcntr |= DISPPLANE_8BPP;
2521 break;
2522 case DRM_FORMAT_RGB565:
2523 dspcntr |= DISPPLANE_BGRX565;
2524 break;
2525 case DRM_FORMAT_XRGB8888:
2526 case DRM_FORMAT_ARGB8888:
2527 dspcntr |= DISPPLANE_BGRX888;
2528 break;
2529 case DRM_FORMAT_XBGR8888:
2530 case DRM_FORMAT_ABGR8888:
2531 dspcntr |= DISPPLANE_RGBX888;
2532 break;
2533 case DRM_FORMAT_XRGB2101010:
2534 case DRM_FORMAT_ARGB2101010:
2535 dspcntr |= DISPPLANE_BGRX101010;
2536 break;
2537 case DRM_FORMAT_XBGR2101010:
2538 case DRM_FORMAT_ABGR2101010:
2539 dspcntr |= DISPPLANE_RGBX101010;
2540 break;
2541 default:
2542 BUG();
2543 }
2544
2545 if (obj->tiling_mode != I915_TILING_NONE)
2546 dspcntr |= DISPPLANE_TILED;
2547 else
2548 dspcntr &= ~DISPPLANE_TILED;
2549
2550 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2551 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2552 else
2553 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2554
2555 I915_WRITE(reg, dspcntr);
2556
2557 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2558 intel_crtc->dspaddr_offset =
2559 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2560 fb->bits_per_pixel / 8,
2561 fb->pitches[0]);
2562 linear_offset -= intel_crtc->dspaddr_offset;
2563
2564 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2565 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2566 fb->pitches[0]);
2567 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2568 I915_WRITE(DSPSURF(plane),
2569 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2570 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2571 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2572 } else {
2573 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2574 I915_WRITE(DSPLINOFF(plane), linear_offset);
2575 }
2576 POSTING_READ(reg);
2577 }
2578
2579 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2580 static int
2581 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2582 int x, int y, enum mode_set_atomic state)
2583 {
2584 struct drm_device *dev = crtc->dev;
2585 struct drm_i915_private *dev_priv = dev->dev_private;
2586
2587 if (dev_priv->display.disable_fbc)
2588 dev_priv->display.disable_fbc(dev);
2589 intel_increase_pllclock(dev, to_intel_crtc(crtc)->pipe);
2590
2591 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2592
2593 return 0;
2594 }
2595
2596 void intel_display_handle_reset(struct drm_device *dev)
2597 {
2598 struct drm_i915_private *dev_priv = dev->dev_private;
2599 struct drm_crtc *crtc;
2600
2601 /*
2602 * Flips in the rings have been nuked by the reset,
2603 * so complete all pending flips so that user space
2604 * will get its events and not get stuck.
2605 *
2606 * Also update the base address of all primary
2607 * planes to the the last fb to make sure we're
2608 * showing the correct fb after a reset.
2609 *
2610 * Need to make two loops over the crtcs so that we
2611 * don't try to grab a crtc mutex before the
2612 * pending_flip_queue really got woken up.
2613 */
2614
2615 for_each_crtc(dev, crtc) {
2616 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2617 enum plane plane = intel_crtc->plane;
2618
2619 intel_prepare_page_flip(dev, plane);
2620 intel_finish_page_flip_plane(dev, plane);
2621 }
2622
2623 for_each_crtc(dev, crtc) {
2624 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2625
2626 drm_modeset_lock(&crtc->mutex, NULL);
2627 /*
2628 * FIXME: Once we have proper support for primary planes (and
2629 * disabling them without disabling the entire crtc) allow again
2630 * a NULL crtc->primary->fb.
2631 */
2632 if (intel_crtc->active && crtc->primary->fb)
2633 dev_priv->display.update_primary_plane(crtc,
2634 crtc->primary->fb,
2635 crtc->x,
2636 crtc->y);
2637 drm_modeset_unlock(&crtc->mutex);
2638 }
2639 }
2640
2641 static int
2642 intel_finish_fb(struct drm_framebuffer *old_fb)
2643 {
2644 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2645 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2646 bool was_interruptible = dev_priv->mm.interruptible;
2647 int ret;
2648
2649 /* Big Hammer, we also need to ensure that any pending
2650 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2651 * current scanout is retired before unpinning the old
2652 * framebuffer.
2653 *
2654 * This should only fail upon a hung GPU, in which case we
2655 * can safely continue.
2656 */
2657 dev_priv->mm.interruptible = false;
2658 ret = i915_gem_object_finish_gpu(obj);
2659 dev_priv->mm.interruptible = was_interruptible;
2660
2661 return ret;
2662 }
2663
2664 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2665 {
2666 struct drm_device *dev = crtc->dev;
2667 struct drm_i915_private *dev_priv = dev->dev_private;
2668 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2669 unsigned long flags;
2670 bool pending;
2671
2672 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2673 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2674 return false;
2675
2676 spin_lock_irqsave(&dev->event_lock, flags);
2677 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2678 spin_unlock_irqrestore(&dev->event_lock, flags);
2679
2680 return pending;
2681 }
2682
2683 static int
2684 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2685 struct drm_framebuffer *fb)
2686 {
2687 struct drm_device *dev = crtc->dev;
2688 struct drm_i915_private *dev_priv = dev->dev_private;
2689 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2690 enum pipe pipe = intel_crtc->pipe;
2691 struct drm_framebuffer *old_fb;
2692 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
2693 int ret;
2694
2695 if (intel_crtc_has_pending_flip(crtc)) {
2696 DRM_ERROR("pipe is still busy with an old pageflip\n");
2697 return -EBUSY;
2698 }
2699
2700 /* no fb bound */
2701 if (!fb) {
2702 DRM_ERROR("No FB bound\n");
2703 return 0;
2704 }
2705
2706 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2707 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2708 plane_name(intel_crtc->plane),
2709 INTEL_INFO(dev)->num_pipes);
2710 return -EINVAL;
2711 }
2712
2713 old_fb = crtc->primary->fb;
2714
2715 mutex_lock(&dev->struct_mutex);
2716 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
2717 if (ret == 0)
2718 i915_gem_track_fb(to_intel_framebuffer(old_fb)->obj, obj,
2719 INTEL_FRONTBUFFER_PRIMARY(pipe));
2720 mutex_unlock(&dev->struct_mutex);
2721 if (ret != 0) {
2722 DRM_ERROR("pin & fence failed\n");
2723 return ret;
2724 }
2725
2726 /*
2727 * Update pipe size and adjust fitter if needed: the reason for this is
2728 * that in compute_mode_changes we check the native mode (not the pfit
2729 * mode) to see if we can flip rather than do a full mode set. In the
2730 * fastboot case, we'll flip, but if we don't update the pipesrc and
2731 * pfit state, we'll end up with a big fb scanned out into the wrong
2732 * sized surface.
2733 *
2734 * To fix this properly, we need to hoist the checks up into
2735 * compute_mode_changes (or above), check the actual pfit state and
2736 * whether the platform allows pfit disable with pipe active, and only
2737 * then update the pipesrc and pfit state, even on the flip path.
2738 */
2739 if (i915.fastboot) {
2740 const struct drm_display_mode *adjusted_mode =
2741 &intel_crtc->config.adjusted_mode;
2742
2743 I915_WRITE(PIPESRC(intel_crtc->pipe),
2744 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2745 (adjusted_mode->crtc_vdisplay - 1));
2746 if (!intel_crtc->config.pch_pfit.enabled &&
2747 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2748 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2749 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2750 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2751 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2752 }
2753 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2754 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2755 }
2756
2757 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2758
2759 crtc->primary->fb = fb;
2760 crtc->x = x;
2761 crtc->y = y;
2762
2763 if (old_fb) {
2764 if (intel_crtc->active && old_fb != fb)
2765 intel_wait_for_vblank(dev, intel_crtc->pipe);
2766 mutex_lock(&dev->struct_mutex);
2767 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2768 mutex_unlock(&dev->struct_mutex);
2769 }
2770
2771 mutex_lock(&dev->struct_mutex);
2772 intel_update_fbc(dev);
2773 mutex_unlock(&dev->struct_mutex);
2774
2775 return 0;
2776 }
2777
2778 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2779 {
2780 struct drm_device *dev = crtc->dev;
2781 struct drm_i915_private *dev_priv = dev->dev_private;
2782 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2783 int pipe = intel_crtc->pipe;
2784 u32 reg, temp;
2785
2786 /* enable normal train */
2787 reg = FDI_TX_CTL(pipe);
2788 temp = I915_READ(reg);
2789 if (IS_IVYBRIDGE(dev)) {
2790 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2791 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2792 } else {
2793 temp &= ~FDI_LINK_TRAIN_NONE;
2794 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2795 }
2796 I915_WRITE(reg, temp);
2797
2798 reg = FDI_RX_CTL(pipe);
2799 temp = I915_READ(reg);
2800 if (HAS_PCH_CPT(dev)) {
2801 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2802 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2803 } else {
2804 temp &= ~FDI_LINK_TRAIN_NONE;
2805 temp |= FDI_LINK_TRAIN_NONE;
2806 }
2807 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2808
2809 /* wait one idle pattern time */
2810 POSTING_READ(reg);
2811 udelay(1000);
2812
2813 /* IVB wants error correction enabled */
2814 if (IS_IVYBRIDGE(dev))
2815 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2816 FDI_FE_ERRC_ENABLE);
2817 }
2818
2819 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2820 {
2821 return crtc->base.enabled && crtc->active &&
2822 crtc->config.has_pch_encoder;
2823 }
2824
2825 static void ivb_modeset_global_resources(struct drm_device *dev)
2826 {
2827 struct drm_i915_private *dev_priv = dev->dev_private;
2828 struct intel_crtc *pipe_B_crtc =
2829 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2830 struct intel_crtc *pipe_C_crtc =
2831 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2832 uint32_t temp;
2833
2834 /*
2835 * When everything is off disable fdi C so that we could enable fdi B
2836 * with all lanes. Note that we don't care about enabled pipes without
2837 * an enabled pch encoder.
2838 */
2839 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2840 !pipe_has_enabled_pch(pipe_C_crtc)) {
2841 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2842 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2843
2844 temp = I915_READ(SOUTH_CHICKEN1);
2845 temp &= ~FDI_BC_BIFURCATION_SELECT;
2846 DRM_DEBUG_KMS("disabling fdi C rx\n");
2847 I915_WRITE(SOUTH_CHICKEN1, temp);
2848 }
2849 }
2850
2851 /* The FDI link training functions for ILK/Ibexpeak. */
2852 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2853 {
2854 struct drm_device *dev = crtc->dev;
2855 struct drm_i915_private *dev_priv = dev->dev_private;
2856 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2857 int pipe = intel_crtc->pipe;
2858 u32 reg, temp, tries;
2859
2860 /* FDI needs bits from pipe first */
2861 assert_pipe_enabled(dev_priv, pipe);
2862
2863 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2864 for train result */
2865 reg = FDI_RX_IMR(pipe);
2866 temp = I915_READ(reg);
2867 temp &= ~FDI_RX_SYMBOL_LOCK;
2868 temp &= ~FDI_RX_BIT_LOCK;
2869 I915_WRITE(reg, temp);
2870 I915_READ(reg);
2871 udelay(150);
2872
2873 /* enable CPU FDI TX and PCH FDI RX */
2874 reg = FDI_TX_CTL(pipe);
2875 temp = I915_READ(reg);
2876 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2877 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2878 temp &= ~FDI_LINK_TRAIN_NONE;
2879 temp |= FDI_LINK_TRAIN_PATTERN_1;
2880 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2881
2882 reg = FDI_RX_CTL(pipe);
2883 temp = I915_READ(reg);
2884 temp &= ~FDI_LINK_TRAIN_NONE;
2885 temp |= FDI_LINK_TRAIN_PATTERN_1;
2886 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2887
2888 POSTING_READ(reg);
2889 udelay(150);
2890
2891 /* Ironlake workaround, enable clock pointer after FDI enable*/
2892 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2893 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2894 FDI_RX_PHASE_SYNC_POINTER_EN);
2895
2896 reg = FDI_RX_IIR(pipe);
2897 for (tries = 0; tries < 5; tries++) {
2898 temp = I915_READ(reg);
2899 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2900
2901 if ((temp & FDI_RX_BIT_LOCK)) {
2902 DRM_DEBUG_KMS("FDI train 1 done.\n");
2903 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2904 break;
2905 }
2906 }
2907 if (tries == 5)
2908 DRM_ERROR("FDI train 1 fail!\n");
2909
2910 /* Train 2 */
2911 reg = FDI_TX_CTL(pipe);
2912 temp = I915_READ(reg);
2913 temp &= ~FDI_LINK_TRAIN_NONE;
2914 temp |= FDI_LINK_TRAIN_PATTERN_2;
2915 I915_WRITE(reg, temp);
2916
2917 reg = FDI_RX_CTL(pipe);
2918 temp = I915_READ(reg);
2919 temp &= ~FDI_LINK_TRAIN_NONE;
2920 temp |= FDI_LINK_TRAIN_PATTERN_2;
2921 I915_WRITE(reg, temp);
2922
2923 POSTING_READ(reg);
2924 udelay(150);
2925
2926 reg = FDI_RX_IIR(pipe);
2927 for (tries = 0; tries < 5; tries++) {
2928 temp = I915_READ(reg);
2929 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2930
2931 if (temp & FDI_RX_SYMBOL_LOCK) {
2932 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2933 DRM_DEBUG_KMS("FDI train 2 done.\n");
2934 break;
2935 }
2936 }
2937 if (tries == 5)
2938 DRM_ERROR("FDI train 2 fail!\n");
2939
2940 DRM_DEBUG_KMS("FDI train done\n");
2941
2942 }
2943
2944 static const int snb_b_fdi_train_param[] = {
2945 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2946 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2947 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2948 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2949 };
2950
2951 /* The FDI link training functions for SNB/Cougarpoint. */
2952 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2953 {
2954 struct drm_device *dev = crtc->dev;
2955 struct drm_i915_private *dev_priv = dev->dev_private;
2956 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2957 int pipe = intel_crtc->pipe;
2958 u32 reg, temp, i, retry;
2959
2960 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2961 for train result */
2962 reg = FDI_RX_IMR(pipe);
2963 temp = I915_READ(reg);
2964 temp &= ~FDI_RX_SYMBOL_LOCK;
2965 temp &= ~FDI_RX_BIT_LOCK;
2966 I915_WRITE(reg, temp);
2967
2968 POSTING_READ(reg);
2969 udelay(150);
2970
2971 /* enable CPU FDI TX and PCH FDI RX */
2972 reg = FDI_TX_CTL(pipe);
2973 temp = I915_READ(reg);
2974 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2975 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2976 temp &= ~FDI_LINK_TRAIN_NONE;
2977 temp |= FDI_LINK_TRAIN_PATTERN_1;
2978 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2979 /* SNB-B */
2980 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2981 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2982
2983 I915_WRITE(FDI_RX_MISC(pipe),
2984 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2985
2986 reg = FDI_RX_CTL(pipe);
2987 temp = I915_READ(reg);
2988 if (HAS_PCH_CPT(dev)) {
2989 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2990 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2991 } else {
2992 temp &= ~FDI_LINK_TRAIN_NONE;
2993 temp |= FDI_LINK_TRAIN_PATTERN_1;
2994 }
2995 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2996
2997 POSTING_READ(reg);
2998 udelay(150);
2999
3000 for (i = 0; i < 4; i++) {
3001 reg = FDI_TX_CTL(pipe);
3002 temp = I915_READ(reg);
3003 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3004 temp |= snb_b_fdi_train_param[i];
3005 I915_WRITE(reg, temp);
3006
3007 POSTING_READ(reg);
3008 udelay(500);
3009
3010 for (retry = 0; retry < 5; retry++) {
3011 reg = FDI_RX_IIR(pipe);
3012 temp = I915_READ(reg);
3013 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3014 if (temp & FDI_RX_BIT_LOCK) {
3015 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3016 DRM_DEBUG_KMS("FDI train 1 done.\n");
3017 break;
3018 }
3019 udelay(50);
3020 }
3021 if (retry < 5)
3022 break;
3023 }
3024 if (i == 4)
3025 DRM_ERROR("FDI train 1 fail!\n");
3026
3027 /* Train 2 */
3028 reg = FDI_TX_CTL(pipe);
3029 temp = I915_READ(reg);
3030 temp &= ~FDI_LINK_TRAIN_NONE;
3031 temp |= FDI_LINK_TRAIN_PATTERN_2;
3032 if (IS_GEN6(dev)) {
3033 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3034 /* SNB-B */
3035 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3036 }
3037 I915_WRITE(reg, temp);
3038
3039 reg = FDI_RX_CTL(pipe);
3040 temp = I915_READ(reg);
3041 if (HAS_PCH_CPT(dev)) {
3042 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3043 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3044 } else {
3045 temp &= ~FDI_LINK_TRAIN_NONE;
3046 temp |= FDI_LINK_TRAIN_PATTERN_2;
3047 }
3048 I915_WRITE(reg, temp);
3049
3050 POSTING_READ(reg);
3051 udelay(150);
3052
3053 for (i = 0; i < 4; i++) {
3054 reg = FDI_TX_CTL(pipe);
3055 temp = I915_READ(reg);
3056 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3057 temp |= snb_b_fdi_train_param[i];
3058 I915_WRITE(reg, temp);
3059
3060 POSTING_READ(reg);
3061 udelay(500);
3062
3063 for (retry = 0; retry < 5; retry++) {
3064 reg = FDI_RX_IIR(pipe);
3065 temp = I915_READ(reg);
3066 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3067 if (temp & FDI_RX_SYMBOL_LOCK) {
3068 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3069 DRM_DEBUG_KMS("FDI train 2 done.\n");
3070 break;
3071 }
3072 udelay(50);
3073 }
3074 if (retry < 5)
3075 break;
3076 }
3077 if (i == 4)
3078 DRM_ERROR("FDI train 2 fail!\n");
3079
3080 DRM_DEBUG_KMS("FDI train done.\n");
3081 }
3082
3083 /* Manual link training for Ivy Bridge A0 parts */
3084 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3085 {
3086 struct drm_device *dev = crtc->dev;
3087 struct drm_i915_private *dev_priv = dev->dev_private;
3088 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3089 int pipe = intel_crtc->pipe;
3090 u32 reg, temp, i, j;
3091
3092 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3093 for train result */
3094 reg = FDI_RX_IMR(pipe);
3095 temp = I915_READ(reg);
3096 temp &= ~FDI_RX_SYMBOL_LOCK;
3097 temp &= ~FDI_RX_BIT_LOCK;
3098 I915_WRITE(reg, temp);
3099
3100 POSTING_READ(reg);
3101 udelay(150);
3102
3103 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3104 I915_READ(FDI_RX_IIR(pipe)));
3105
3106 /* Try each vswing and preemphasis setting twice before moving on */
3107 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3108 /* disable first in case we need to retry */
3109 reg = FDI_TX_CTL(pipe);
3110 temp = I915_READ(reg);
3111 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3112 temp &= ~FDI_TX_ENABLE;
3113 I915_WRITE(reg, temp);
3114
3115 reg = FDI_RX_CTL(pipe);
3116 temp = I915_READ(reg);
3117 temp &= ~FDI_LINK_TRAIN_AUTO;
3118 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3119 temp &= ~FDI_RX_ENABLE;
3120 I915_WRITE(reg, temp);
3121
3122 /* enable CPU FDI TX and PCH FDI RX */
3123 reg = FDI_TX_CTL(pipe);
3124 temp = I915_READ(reg);
3125 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3126 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3127 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3128 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3129 temp |= snb_b_fdi_train_param[j/2];
3130 temp |= FDI_COMPOSITE_SYNC;
3131 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3132
3133 I915_WRITE(FDI_RX_MISC(pipe),
3134 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3135
3136 reg = FDI_RX_CTL(pipe);
3137 temp = I915_READ(reg);
3138 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3139 temp |= FDI_COMPOSITE_SYNC;
3140 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3141
3142 POSTING_READ(reg);
3143 udelay(1); /* should be 0.5us */
3144
3145 for (i = 0; i < 4; i++) {
3146 reg = FDI_RX_IIR(pipe);
3147 temp = I915_READ(reg);
3148 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3149
3150 if (temp & FDI_RX_BIT_LOCK ||
3151 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3152 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3153 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3154 i);
3155 break;
3156 }
3157 udelay(1); /* should be 0.5us */
3158 }
3159 if (i == 4) {
3160 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3161 continue;
3162 }
3163
3164 /* Train 2 */
3165 reg = FDI_TX_CTL(pipe);
3166 temp = I915_READ(reg);
3167 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3168 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3169 I915_WRITE(reg, temp);
3170
3171 reg = FDI_RX_CTL(pipe);
3172 temp = I915_READ(reg);
3173 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3174 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3175 I915_WRITE(reg, temp);
3176
3177 POSTING_READ(reg);
3178 udelay(2); /* should be 1.5us */
3179
3180 for (i = 0; i < 4; i++) {
3181 reg = FDI_RX_IIR(pipe);
3182 temp = I915_READ(reg);
3183 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3184
3185 if (temp & FDI_RX_SYMBOL_LOCK ||
3186 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3187 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3188 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3189 i);
3190 goto train_done;
3191 }
3192 udelay(2); /* should be 1.5us */
3193 }
3194 if (i == 4)
3195 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3196 }
3197
3198 train_done:
3199 DRM_DEBUG_KMS("FDI train done.\n");
3200 }
3201
3202 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3203 {
3204 struct drm_device *dev = intel_crtc->base.dev;
3205 struct drm_i915_private *dev_priv = dev->dev_private;
3206 int pipe = intel_crtc->pipe;
3207 u32 reg, temp;
3208
3209
3210 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3211 reg = FDI_RX_CTL(pipe);
3212 temp = I915_READ(reg);
3213 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3214 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3215 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3216 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3217
3218 POSTING_READ(reg);
3219 udelay(200);
3220
3221 /* Switch from Rawclk to PCDclk */
3222 temp = I915_READ(reg);
3223 I915_WRITE(reg, temp | FDI_PCDCLK);
3224
3225 POSTING_READ(reg);
3226 udelay(200);
3227
3228 /* Enable CPU FDI TX PLL, always on for Ironlake */
3229 reg = FDI_TX_CTL(pipe);
3230 temp = I915_READ(reg);
3231 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3232 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3233
3234 POSTING_READ(reg);
3235 udelay(100);
3236 }
3237 }
3238
3239 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3240 {
3241 struct drm_device *dev = intel_crtc->base.dev;
3242 struct drm_i915_private *dev_priv = dev->dev_private;
3243 int pipe = intel_crtc->pipe;
3244 u32 reg, temp;
3245
3246 /* Switch from PCDclk to Rawclk */
3247 reg = FDI_RX_CTL(pipe);
3248 temp = I915_READ(reg);
3249 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3250
3251 /* Disable CPU FDI TX PLL */
3252 reg = FDI_TX_CTL(pipe);
3253 temp = I915_READ(reg);
3254 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3255
3256 POSTING_READ(reg);
3257 udelay(100);
3258
3259 reg = FDI_RX_CTL(pipe);
3260 temp = I915_READ(reg);
3261 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3262
3263 /* Wait for the clocks to turn off. */
3264 POSTING_READ(reg);
3265 udelay(100);
3266 }
3267
3268 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3269 {
3270 struct drm_device *dev = crtc->dev;
3271 struct drm_i915_private *dev_priv = dev->dev_private;
3272 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3273 int pipe = intel_crtc->pipe;
3274 u32 reg, temp;
3275
3276 /* disable CPU FDI tx and PCH FDI rx */
3277 reg = FDI_TX_CTL(pipe);
3278 temp = I915_READ(reg);
3279 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3280 POSTING_READ(reg);
3281
3282 reg = FDI_RX_CTL(pipe);
3283 temp = I915_READ(reg);
3284 temp &= ~(0x7 << 16);
3285 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3286 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3287
3288 POSTING_READ(reg);
3289 udelay(100);
3290
3291 /* Ironlake workaround, disable clock pointer after downing FDI */
3292 if (HAS_PCH_IBX(dev))
3293 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3294
3295 /* still set train pattern 1 */
3296 reg = FDI_TX_CTL(pipe);
3297 temp = I915_READ(reg);
3298 temp &= ~FDI_LINK_TRAIN_NONE;
3299 temp |= FDI_LINK_TRAIN_PATTERN_1;
3300 I915_WRITE(reg, temp);
3301
3302 reg = FDI_RX_CTL(pipe);
3303 temp = I915_READ(reg);
3304 if (HAS_PCH_CPT(dev)) {
3305 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3306 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3307 } else {
3308 temp &= ~FDI_LINK_TRAIN_NONE;
3309 temp |= FDI_LINK_TRAIN_PATTERN_1;
3310 }
3311 /* BPC in FDI rx is consistent with that in PIPECONF */
3312 temp &= ~(0x07 << 16);
3313 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3314 I915_WRITE(reg, temp);
3315
3316 POSTING_READ(reg);
3317 udelay(100);
3318 }
3319
3320 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3321 {
3322 struct intel_crtc *crtc;
3323
3324 /* Note that we don't need to be called with mode_config.lock here
3325 * as our list of CRTC objects is static for the lifetime of the
3326 * device and so cannot disappear as we iterate. Similarly, we can
3327 * happily treat the predicates as racy, atomic checks as userspace
3328 * cannot claim and pin a new fb without at least acquring the
3329 * struct_mutex and so serialising with us.
3330 */
3331 for_each_intel_crtc(dev, crtc) {
3332 if (atomic_read(&crtc->unpin_work_count) == 0)
3333 continue;
3334
3335 if (crtc->unpin_work)
3336 intel_wait_for_vblank(dev, crtc->pipe);
3337
3338 return true;
3339 }
3340
3341 return false;
3342 }
3343
3344 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3345 {
3346 struct drm_device *dev = crtc->dev;
3347 struct drm_i915_private *dev_priv = dev->dev_private;
3348
3349 if (crtc->primary->fb == NULL)
3350 return;
3351
3352 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3353
3354 WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3355 !intel_crtc_has_pending_flip(crtc),
3356 60*HZ) == 0);
3357
3358 mutex_lock(&dev->struct_mutex);
3359 intel_finish_fb(crtc->primary->fb);
3360 mutex_unlock(&dev->struct_mutex);
3361 }
3362
3363 /* Program iCLKIP clock to the desired frequency */
3364 static void lpt_program_iclkip(struct drm_crtc *crtc)
3365 {
3366 struct drm_device *dev = crtc->dev;
3367 struct drm_i915_private *dev_priv = dev->dev_private;
3368 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3369 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3370 u32 temp;
3371
3372 mutex_lock(&dev_priv->dpio_lock);
3373
3374 /* It is necessary to ungate the pixclk gate prior to programming
3375 * the divisors, and gate it back when it is done.
3376 */
3377 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3378
3379 /* Disable SSCCTL */
3380 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3381 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3382 SBI_SSCCTL_DISABLE,
3383 SBI_ICLK);
3384
3385 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3386 if (clock == 20000) {
3387 auxdiv = 1;
3388 divsel = 0x41;
3389 phaseinc = 0x20;
3390 } else {
3391 /* The iCLK virtual clock root frequency is in MHz,
3392 * but the adjusted_mode->crtc_clock in in KHz. To get the
3393 * divisors, it is necessary to divide one by another, so we
3394 * convert the virtual clock precision to KHz here for higher
3395 * precision.
3396 */
3397 u32 iclk_virtual_root_freq = 172800 * 1000;
3398 u32 iclk_pi_range = 64;
3399 u32 desired_divisor, msb_divisor_value, pi_value;
3400
3401 desired_divisor = (iclk_virtual_root_freq / clock);
3402 msb_divisor_value = desired_divisor / iclk_pi_range;
3403 pi_value = desired_divisor % iclk_pi_range;
3404
3405 auxdiv = 0;
3406 divsel = msb_divisor_value - 2;
3407 phaseinc = pi_value;
3408 }
3409
3410 /* This should not happen with any sane values */
3411 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3412 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3413 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3414 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3415
3416 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3417 clock,
3418 auxdiv,
3419 divsel,
3420 phasedir,
3421 phaseinc);
3422
3423 /* Program SSCDIVINTPHASE6 */
3424 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3425 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3426 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3427 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3428 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3429 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3430 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3431 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3432
3433 /* Program SSCAUXDIV */
3434 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3435 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3436 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3437 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3438
3439 /* Enable modulator and associated divider */
3440 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3441 temp &= ~SBI_SSCCTL_DISABLE;
3442 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3443
3444 /* Wait for initialization time */
3445 udelay(24);
3446
3447 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3448
3449 mutex_unlock(&dev_priv->dpio_lock);
3450 }
3451
3452 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3453 enum pipe pch_transcoder)
3454 {
3455 struct drm_device *dev = crtc->base.dev;
3456 struct drm_i915_private *dev_priv = dev->dev_private;
3457 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3458
3459 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3460 I915_READ(HTOTAL(cpu_transcoder)));
3461 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3462 I915_READ(HBLANK(cpu_transcoder)));
3463 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3464 I915_READ(HSYNC(cpu_transcoder)));
3465
3466 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3467 I915_READ(VTOTAL(cpu_transcoder)));
3468 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3469 I915_READ(VBLANK(cpu_transcoder)));
3470 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3471 I915_READ(VSYNC(cpu_transcoder)));
3472 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3473 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3474 }
3475
3476 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3477 {
3478 struct drm_i915_private *dev_priv = dev->dev_private;
3479 uint32_t temp;
3480
3481 temp = I915_READ(SOUTH_CHICKEN1);
3482 if (temp & FDI_BC_BIFURCATION_SELECT)
3483 return;
3484
3485 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3486 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3487
3488 temp |= FDI_BC_BIFURCATION_SELECT;
3489 DRM_DEBUG_KMS("enabling fdi C rx\n");
3490 I915_WRITE(SOUTH_CHICKEN1, temp);
3491 POSTING_READ(SOUTH_CHICKEN1);
3492 }
3493
3494 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3495 {
3496 struct drm_device *dev = intel_crtc->base.dev;
3497 struct drm_i915_private *dev_priv = dev->dev_private;
3498
3499 switch (intel_crtc->pipe) {
3500 case PIPE_A:
3501 break;
3502 case PIPE_B:
3503 if (intel_crtc->config.fdi_lanes > 2)
3504 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3505 else
3506 cpt_enable_fdi_bc_bifurcation(dev);
3507
3508 break;
3509 case PIPE_C:
3510 cpt_enable_fdi_bc_bifurcation(dev);
3511
3512 break;
3513 default:
3514 BUG();
3515 }
3516 }
3517
3518 /*
3519 * Enable PCH resources required for PCH ports:
3520 * - PCH PLLs
3521 * - FDI training & RX/TX
3522 * - update transcoder timings
3523 * - DP transcoding bits
3524 * - transcoder
3525 */
3526 static void ironlake_pch_enable(struct drm_crtc *crtc)
3527 {
3528 struct drm_device *dev = crtc->dev;
3529 struct drm_i915_private *dev_priv = dev->dev_private;
3530 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3531 int pipe = intel_crtc->pipe;
3532 u32 reg, temp;
3533
3534 assert_pch_transcoder_disabled(dev_priv, pipe);
3535
3536 if (IS_IVYBRIDGE(dev))
3537 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3538
3539 /* Write the TU size bits before fdi link training, so that error
3540 * detection works. */
3541 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3542 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3543
3544 /* For PCH output, training FDI link */
3545 dev_priv->display.fdi_link_train(crtc);
3546
3547 /* We need to program the right clock selection before writing the pixel
3548 * mutliplier into the DPLL. */
3549 if (HAS_PCH_CPT(dev)) {
3550 u32 sel;
3551
3552 temp = I915_READ(PCH_DPLL_SEL);
3553 temp |= TRANS_DPLL_ENABLE(pipe);
3554 sel = TRANS_DPLLB_SEL(pipe);
3555 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3556 temp |= sel;
3557 else
3558 temp &= ~sel;
3559 I915_WRITE(PCH_DPLL_SEL, temp);
3560 }
3561
3562 /* XXX: pch pll's can be enabled any time before we enable the PCH
3563 * transcoder, and we actually should do this to not upset any PCH
3564 * transcoder that already use the clock when we share it.
3565 *
3566 * Note that enable_shared_dpll tries to do the right thing, but
3567 * get_shared_dpll unconditionally resets the pll - we need that to have
3568 * the right LVDS enable sequence. */
3569 intel_enable_shared_dpll(intel_crtc);
3570
3571 /* set transcoder timing, panel must allow it */
3572 assert_panel_unlocked(dev_priv, pipe);
3573 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3574
3575 intel_fdi_normal_train(crtc);
3576
3577 /* For PCH DP, enable TRANS_DP_CTL */
3578 if (HAS_PCH_CPT(dev) &&
3579 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3580 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3581 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3582 reg = TRANS_DP_CTL(pipe);
3583 temp = I915_READ(reg);
3584 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3585 TRANS_DP_SYNC_MASK |
3586 TRANS_DP_BPC_MASK);
3587 temp |= (TRANS_DP_OUTPUT_ENABLE |
3588 TRANS_DP_ENH_FRAMING);
3589 temp |= bpc << 9; /* same format but at 11:9 */
3590
3591 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3592 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3593 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3594 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3595
3596 switch (intel_trans_dp_port_sel(crtc)) {
3597 case PCH_DP_B:
3598 temp |= TRANS_DP_PORT_SEL_B;
3599 break;
3600 case PCH_DP_C:
3601 temp |= TRANS_DP_PORT_SEL_C;
3602 break;
3603 case PCH_DP_D:
3604 temp |= TRANS_DP_PORT_SEL_D;
3605 break;
3606 default:
3607 BUG();
3608 }
3609
3610 I915_WRITE(reg, temp);
3611 }
3612
3613 ironlake_enable_pch_transcoder(dev_priv, pipe);
3614 }
3615
3616 static void lpt_pch_enable(struct drm_crtc *crtc)
3617 {
3618 struct drm_device *dev = crtc->dev;
3619 struct drm_i915_private *dev_priv = dev->dev_private;
3620 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3621 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3622
3623 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3624
3625 lpt_program_iclkip(crtc);
3626
3627 /* Set transcoder timing. */
3628 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3629
3630 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3631 }
3632
3633 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3634 {
3635 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3636
3637 if (pll == NULL)
3638 return;
3639
3640 if (pll->refcount == 0) {
3641 WARN(1, "bad %s refcount\n", pll->name);
3642 return;
3643 }
3644
3645 if (--pll->refcount == 0) {
3646 WARN_ON(pll->on);
3647 WARN_ON(pll->active);
3648 }
3649
3650 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3651 }
3652
3653 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3654 {
3655 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3656 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3657 enum intel_dpll_id i;
3658
3659 if (pll) {
3660 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3661 crtc->base.base.id, pll->name);
3662 intel_put_shared_dpll(crtc);
3663 }
3664
3665 if (HAS_PCH_IBX(dev_priv->dev)) {
3666 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3667 i = (enum intel_dpll_id) crtc->pipe;
3668 pll = &dev_priv->shared_dplls[i];
3669
3670 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3671 crtc->base.base.id, pll->name);
3672
3673 WARN_ON(pll->refcount);
3674
3675 goto found;
3676 }
3677
3678 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3679 pll = &dev_priv->shared_dplls[i];
3680
3681 /* Only want to check enabled timings first */
3682 if (pll->refcount == 0)
3683 continue;
3684
3685 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3686 sizeof(pll->hw_state)) == 0) {
3687 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3688 crtc->base.base.id,
3689 pll->name, pll->refcount, pll->active);
3690
3691 goto found;
3692 }
3693 }
3694
3695 /* Ok no matching timings, maybe there's a free one? */
3696 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3697 pll = &dev_priv->shared_dplls[i];
3698 if (pll->refcount == 0) {
3699 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3700 crtc->base.base.id, pll->name);
3701 goto found;
3702 }
3703 }
3704
3705 return NULL;
3706
3707 found:
3708 if (pll->refcount == 0)
3709 pll->hw_state = crtc->config.dpll_hw_state;
3710
3711 crtc->config.shared_dpll = i;
3712 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3713 pipe_name(crtc->pipe));
3714
3715 pll->refcount++;
3716
3717 return pll;
3718 }
3719
3720 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3721 {
3722 struct drm_i915_private *dev_priv = dev->dev_private;
3723 int dslreg = PIPEDSL(pipe);
3724 u32 temp;
3725
3726 temp = I915_READ(dslreg);
3727 udelay(500);
3728 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3729 if (wait_for(I915_READ(dslreg) != temp, 5))
3730 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3731 }
3732 }
3733
3734 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3735 {
3736 struct drm_device *dev = crtc->base.dev;
3737 struct drm_i915_private *dev_priv = dev->dev_private;
3738 int pipe = crtc->pipe;
3739
3740 if (crtc->config.pch_pfit.enabled) {
3741 /* Force use of hard-coded filter coefficients
3742 * as some pre-programmed values are broken,
3743 * e.g. x201.
3744 */
3745 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3746 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3747 PF_PIPE_SEL_IVB(pipe));
3748 else
3749 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3750 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3751 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3752 }
3753 }
3754
3755 static void intel_enable_planes(struct drm_crtc *crtc)
3756 {
3757 struct drm_device *dev = crtc->dev;
3758 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3759 struct drm_plane *plane;
3760 struct intel_plane *intel_plane;
3761
3762 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3763 intel_plane = to_intel_plane(plane);
3764 if (intel_plane->pipe == pipe)
3765 intel_plane_restore(&intel_plane->base);
3766 }
3767 }
3768
3769 static void intel_disable_planes(struct drm_crtc *crtc)
3770 {
3771 struct drm_device *dev = crtc->dev;
3772 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3773 struct drm_plane *plane;
3774 struct intel_plane *intel_plane;
3775
3776 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3777 intel_plane = to_intel_plane(plane);
3778 if (intel_plane->pipe == pipe)
3779 intel_plane_disable(&intel_plane->base);
3780 }
3781 }
3782
3783 void hsw_enable_ips(struct intel_crtc *crtc)
3784 {
3785 struct drm_device *dev = crtc->base.dev;
3786 struct drm_i915_private *dev_priv = dev->dev_private;
3787
3788 if (!crtc->config.ips_enabled)
3789 return;
3790
3791 /* We can only enable IPS after we enable a plane and wait for a vblank */
3792 intel_wait_for_vblank(dev, crtc->pipe);
3793
3794 assert_plane_enabled(dev_priv, crtc->plane);
3795 if (IS_BROADWELL(dev)) {
3796 mutex_lock(&dev_priv->rps.hw_lock);
3797 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3798 mutex_unlock(&dev_priv->rps.hw_lock);
3799 /* Quoting Art Runyan: "its not safe to expect any particular
3800 * value in IPS_CTL bit 31 after enabling IPS through the
3801 * mailbox." Moreover, the mailbox may return a bogus state,
3802 * so we need to just enable it and continue on.
3803 */
3804 } else {
3805 I915_WRITE(IPS_CTL, IPS_ENABLE);
3806 /* The bit only becomes 1 in the next vblank, so this wait here
3807 * is essentially intel_wait_for_vblank. If we don't have this
3808 * and don't wait for vblanks until the end of crtc_enable, then
3809 * the HW state readout code will complain that the expected
3810 * IPS_CTL value is not the one we read. */
3811 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3812 DRM_ERROR("Timed out waiting for IPS enable\n");
3813 }
3814 }
3815
3816 void hsw_disable_ips(struct intel_crtc *crtc)
3817 {
3818 struct drm_device *dev = crtc->base.dev;
3819 struct drm_i915_private *dev_priv = dev->dev_private;
3820
3821 if (!crtc->config.ips_enabled)
3822 return;
3823
3824 assert_plane_enabled(dev_priv, crtc->plane);
3825 if (IS_BROADWELL(dev)) {
3826 mutex_lock(&dev_priv->rps.hw_lock);
3827 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3828 mutex_unlock(&dev_priv->rps.hw_lock);
3829 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3830 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3831 DRM_ERROR("Timed out waiting for IPS disable\n");
3832 } else {
3833 I915_WRITE(IPS_CTL, 0);
3834 POSTING_READ(IPS_CTL);
3835 }
3836
3837 /* We need to wait for a vblank before we can disable the plane. */
3838 intel_wait_for_vblank(dev, crtc->pipe);
3839 }
3840
3841 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3842 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3843 {
3844 struct drm_device *dev = crtc->dev;
3845 struct drm_i915_private *dev_priv = dev->dev_private;
3846 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3847 enum pipe pipe = intel_crtc->pipe;
3848 int palreg = PALETTE(pipe);
3849 int i;
3850 bool reenable_ips = false;
3851
3852 /* The clocks have to be on to load the palette. */
3853 if (!crtc->enabled || !intel_crtc->active)
3854 return;
3855
3856 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3857 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3858 assert_dsi_pll_enabled(dev_priv);
3859 else
3860 assert_pll_enabled(dev_priv, pipe);
3861 }
3862
3863 /* use legacy palette for Ironlake */
3864 if (HAS_PCH_SPLIT(dev))
3865 palreg = LGC_PALETTE(pipe);
3866
3867 /* Workaround : Do not read or write the pipe palette/gamma data while
3868 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3869 */
3870 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3871 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3872 GAMMA_MODE_MODE_SPLIT)) {
3873 hsw_disable_ips(intel_crtc);
3874 reenable_ips = true;
3875 }
3876
3877 for (i = 0; i < 256; i++) {
3878 I915_WRITE(palreg + 4 * i,
3879 (intel_crtc->lut_r[i] << 16) |
3880 (intel_crtc->lut_g[i] << 8) |
3881 intel_crtc->lut_b[i]);
3882 }
3883
3884 if (reenable_ips)
3885 hsw_enable_ips(intel_crtc);
3886 }
3887
3888 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3889 {
3890 if (!enable && intel_crtc->overlay) {
3891 struct drm_device *dev = intel_crtc->base.dev;
3892 struct drm_i915_private *dev_priv = dev->dev_private;
3893
3894 mutex_lock(&dev->struct_mutex);
3895 dev_priv->mm.interruptible = false;
3896 (void) intel_overlay_switch_off(intel_crtc->overlay);
3897 dev_priv->mm.interruptible = true;
3898 mutex_unlock(&dev->struct_mutex);
3899 }
3900
3901 /* Let userspace switch the overlay on again. In most cases userspace
3902 * has to recompute where to put it anyway.
3903 */
3904 }
3905
3906 /**
3907 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3908 * cursor plane briefly if not already running after enabling the display
3909 * plane.
3910 * This workaround avoids occasional blank screens when self refresh is
3911 * enabled.
3912 */
3913 static void
3914 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3915 {
3916 u32 cntl = I915_READ(CURCNTR(pipe));
3917
3918 if ((cntl & CURSOR_MODE) == 0) {
3919 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3920
3921 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3922 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3923 intel_wait_for_vblank(dev_priv->dev, pipe);
3924 I915_WRITE(CURCNTR(pipe), cntl);
3925 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3926 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3927 }
3928 }
3929
3930 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
3931 {
3932 struct drm_device *dev = crtc->dev;
3933 struct drm_i915_private *dev_priv = dev->dev_private;
3934 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3935 int pipe = intel_crtc->pipe;
3936 int plane = intel_crtc->plane;
3937
3938 drm_vblank_on(dev, pipe);
3939
3940 intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3941 intel_enable_planes(crtc);
3942 /* The fixup needs to happen before cursor is enabled */
3943 if (IS_G4X(dev))
3944 g4x_fixup_plane(dev_priv, pipe);
3945 intel_crtc_update_cursor(crtc, true);
3946 intel_crtc_dpms_overlay(intel_crtc, true);
3947
3948 hsw_enable_ips(intel_crtc);
3949
3950 mutex_lock(&dev->struct_mutex);
3951 intel_update_fbc(dev);
3952 mutex_unlock(&dev->struct_mutex);
3953 }
3954
3955 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
3956 {
3957 struct drm_device *dev = crtc->dev;
3958 struct drm_i915_private *dev_priv = dev->dev_private;
3959 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3960 int pipe = intel_crtc->pipe;
3961 int plane = intel_crtc->plane;
3962
3963 intel_crtc_wait_for_pending_flips(crtc);
3964
3965 if (dev_priv->fbc.plane == plane)
3966 intel_disable_fbc(dev);
3967
3968 hsw_disable_ips(intel_crtc);
3969
3970 intel_crtc_dpms_overlay(intel_crtc, false);
3971 intel_crtc_update_cursor(crtc, false);
3972 intel_disable_planes(crtc);
3973 intel_disable_primary_hw_plane(dev_priv, plane, pipe);
3974
3975 drm_vblank_off(dev, pipe);
3976 }
3977
3978 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3979 {
3980 struct drm_device *dev = crtc->dev;
3981 struct drm_i915_private *dev_priv = dev->dev_private;
3982 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3983 struct intel_encoder *encoder;
3984 int pipe = intel_crtc->pipe;
3985 enum plane plane = intel_crtc->plane;
3986
3987 WARN_ON(!crtc->enabled);
3988
3989 if (intel_crtc->active)
3990 return;
3991
3992 if (intel_crtc->config.has_pch_encoder)
3993 intel_prepare_shared_dpll(intel_crtc);
3994
3995 if (intel_crtc->config.has_dp_encoder)
3996 intel_dp_set_m_n(intel_crtc);
3997
3998 intel_set_pipe_timings(intel_crtc);
3999
4000 if (intel_crtc->config.has_pch_encoder) {
4001 intel_cpu_transcoder_set_m_n(intel_crtc,
4002 &intel_crtc->config.fdi_m_n);
4003 }
4004
4005 ironlake_set_pipeconf(crtc);
4006
4007 /* Set up the display plane register */
4008 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
4009 POSTING_READ(DSPCNTR(plane));
4010
4011 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4012 crtc->x, crtc->y);
4013
4014 intel_crtc->active = true;
4015
4016 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4017 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4018
4019 for_each_encoder_on_crtc(dev, crtc, encoder)
4020 if (encoder->pre_enable)
4021 encoder->pre_enable(encoder);
4022
4023 if (intel_crtc->config.has_pch_encoder) {
4024 /* Note: FDI PLL enabling _must_ be done before we enable the
4025 * cpu pipes, hence this is separate from all the other fdi/pch
4026 * enabling. */
4027 ironlake_fdi_pll_enable(intel_crtc);
4028 } else {
4029 assert_fdi_tx_disabled(dev_priv, pipe);
4030 assert_fdi_rx_disabled(dev_priv, pipe);
4031 }
4032
4033 ironlake_pfit_enable(intel_crtc);
4034
4035 /*
4036 * On ILK+ LUT must be loaded before the pipe is running but with
4037 * clocks enabled
4038 */
4039 intel_crtc_load_lut(crtc);
4040
4041 intel_update_watermarks(crtc);
4042 intel_enable_pipe(intel_crtc);
4043
4044 if (intel_crtc->config.has_pch_encoder)
4045 ironlake_pch_enable(crtc);
4046
4047 for_each_encoder_on_crtc(dev, crtc, encoder)
4048 encoder->enable(encoder);
4049
4050 if (HAS_PCH_CPT(dev))
4051 cpt_verify_modeset(dev, intel_crtc->pipe);
4052
4053 intel_crtc_enable_planes(crtc);
4054 }
4055
4056 /* IPS only exists on ULT machines and is tied to pipe A. */
4057 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4058 {
4059 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4060 }
4061
4062 /*
4063 * This implements the workaround described in the "notes" section of the mode
4064 * set sequence documentation. When going from no pipes or single pipe to
4065 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4066 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4067 */
4068 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4069 {
4070 struct drm_device *dev = crtc->base.dev;
4071 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4072
4073 /* We want to get the other_active_crtc only if there's only 1 other
4074 * active crtc. */
4075 for_each_intel_crtc(dev, crtc_it) {
4076 if (!crtc_it->active || crtc_it == crtc)
4077 continue;
4078
4079 if (other_active_crtc)
4080 return;
4081
4082 other_active_crtc = crtc_it;
4083 }
4084 if (!other_active_crtc)
4085 return;
4086
4087 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4088 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4089 }
4090
4091 static void haswell_crtc_enable(struct drm_crtc *crtc)
4092 {
4093 struct drm_device *dev = crtc->dev;
4094 struct drm_i915_private *dev_priv = dev->dev_private;
4095 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4096 struct intel_encoder *encoder;
4097 int pipe = intel_crtc->pipe;
4098 enum plane plane = intel_crtc->plane;
4099
4100 WARN_ON(!crtc->enabled);
4101
4102 if (intel_crtc->active)
4103 return;
4104
4105 if (intel_crtc->config.has_dp_encoder)
4106 intel_dp_set_m_n(intel_crtc);
4107
4108 intel_set_pipe_timings(intel_crtc);
4109
4110 if (intel_crtc->config.has_pch_encoder) {
4111 intel_cpu_transcoder_set_m_n(intel_crtc,
4112 &intel_crtc->config.fdi_m_n);
4113 }
4114
4115 haswell_set_pipeconf(crtc);
4116
4117 intel_set_pipe_csc(crtc);
4118
4119 /* Set up the display plane register */
4120 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
4121 POSTING_READ(DSPCNTR(plane));
4122
4123 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4124 crtc->x, crtc->y);
4125
4126 intel_crtc->active = true;
4127
4128 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4129 if (intel_crtc->config.has_pch_encoder)
4130 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4131
4132 if (intel_crtc->config.has_pch_encoder)
4133 dev_priv->display.fdi_link_train(crtc);
4134
4135 for_each_encoder_on_crtc(dev, crtc, encoder)
4136 if (encoder->pre_enable)
4137 encoder->pre_enable(encoder);
4138
4139 intel_ddi_enable_pipe_clock(intel_crtc);
4140
4141 ironlake_pfit_enable(intel_crtc);
4142
4143 /*
4144 * On ILK+ LUT must be loaded before the pipe is running but with
4145 * clocks enabled
4146 */
4147 intel_crtc_load_lut(crtc);
4148
4149 intel_ddi_set_pipe_settings(crtc);
4150 intel_ddi_enable_transcoder_func(crtc);
4151
4152 intel_update_watermarks(crtc);
4153 intel_enable_pipe(intel_crtc);
4154
4155 if (intel_crtc->config.has_pch_encoder)
4156 lpt_pch_enable(crtc);
4157
4158 for_each_encoder_on_crtc(dev, crtc, encoder) {
4159 encoder->enable(encoder);
4160 intel_opregion_notify_encoder(encoder, true);
4161 }
4162
4163 /* If we change the relative order between pipe/planes enabling, we need
4164 * to change the workaround. */
4165 haswell_mode_set_planes_workaround(intel_crtc);
4166 intel_crtc_enable_planes(crtc);
4167 }
4168
4169 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4170 {
4171 struct drm_device *dev = crtc->base.dev;
4172 struct drm_i915_private *dev_priv = dev->dev_private;
4173 int pipe = crtc->pipe;
4174
4175 /* To avoid upsetting the power well on haswell only disable the pfit if
4176 * it's in use. The hw state code will make sure we get this right. */
4177 if (crtc->config.pch_pfit.enabled) {
4178 I915_WRITE(PF_CTL(pipe), 0);
4179 I915_WRITE(PF_WIN_POS(pipe), 0);
4180 I915_WRITE(PF_WIN_SZ(pipe), 0);
4181 }
4182 }
4183
4184 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4185 {
4186 struct drm_device *dev = crtc->dev;
4187 struct drm_i915_private *dev_priv = dev->dev_private;
4188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4189 struct intel_encoder *encoder;
4190 int pipe = intel_crtc->pipe;
4191 u32 reg, temp;
4192
4193 if (!intel_crtc->active)
4194 return;
4195
4196 intel_crtc_disable_planes(crtc);
4197
4198 for_each_encoder_on_crtc(dev, crtc, encoder)
4199 encoder->disable(encoder);
4200
4201 if (intel_crtc->config.has_pch_encoder)
4202 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4203
4204 intel_disable_pipe(dev_priv, pipe);
4205
4206 ironlake_pfit_disable(intel_crtc);
4207
4208 for_each_encoder_on_crtc(dev, crtc, encoder)
4209 if (encoder->post_disable)
4210 encoder->post_disable(encoder);
4211
4212 if (intel_crtc->config.has_pch_encoder) {
4213 ironlake_fdi_disable(crtc);
4214
4215 ironlake_disable_pch_transcoder(dev_priv, pipe);
4216 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4217
4218 if (HAS_PCH_CPT(dev)) {
4219 /* disable TRANS_DP_CTL */
4220 reg = TRANS_DP_CTL(pipe);
4221 temp = I915_READ(reg);
4222 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4223 TRANS_DP_PORT_SEL_MASK);
4224 temp |= TRANS_DP_PORT_SEL_NONE;
4225 I915_WRITE(reg, temp);
4226
4227 /* disable DPLL_SEL */
4228 temp = I915_READ(PCH_DPLL_SEL);
4229 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4230 I915_WRITE(PCH_DPLL_SEL, temp);
4231 }
4232
4233 /* disable PCH DPLL */
4234 intel_disable_shared_dpll(intel_crtc);
4235
4236 ironlake_fdi_pll_disable(intel_crtc);
4237 }
4238
4239 intel_crtc->active = false;
4240 intel_update_watermarks(crtc);
4241
4242 mutex_lock(&dev->struct_mutex);
4243 intel_update_fbc(dev);
4244 mutex_unlock(&dev->struct_mutex);
4245 }
4246
4247 static void haswell_crtc_disable(struct drm_crtc *crtc)
4248 {
4249 struct drm_device *dev = crtc->dev;
4250 struct drm_i915_private *dev_priv = dev->dev_private;
4251 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4252 struct intel_encoder *encoder;
4253 int pipe = intel_crtc->pipe;
4254 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4255
4256 if (!intel_crtc->active)
4257 return;
4258
4259 intel_crtc_disable_planes(crtc);
4260
4261 for_each_encoder_on_crtc(dev, crtc, encoder) {
4262 intel_opregion_notify_encoder(encoder, false);
4263 encoder->disable(encoder);
4264 }
4265
4266 if (intel_crtc->config.has_pch_encoder)
4267 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4268 intel_disable_pipe(dev_priv, pipe);
4269
4270 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4271
4272 ironlake_pfit_disable(intel_crtc);
4273
4274 intel_ddi_disable_pipe_clock(intel_crtc);
4275
4276 for_each_encoder_on_crtc(dev, crtc, encoder)
4277 if (encoder->post_disable)
4278 encoder->post_disable(encoder);
4279
4280 if (intel_crtc->config.has_pch_encoder) {
4281 lpt_disable_pch_transcoder(dev_priv);
4282 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4283 intel_ddi_fdi_disable(crtc);
4284 }
4285
4286 intel_crtc->active = false;
4287 intel_update_watermarks(crtc);
4288
4289 mutex_lock(&dev->struct_mutex);
4290 intel_update_fbc(dev);
4291 mutex_unlock(&dev->struct_mutex);
4292 }
4293
4294 static void ironlake_crtc_off(struct drm_crtc *crtc)
4295 {
4296 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4297 intel_put_shared_dpll(intel_crtc);
4298 }
4299
4300 static void haswell_crtc_off(struct drm_crtc *crtc)
4301 {
4302 intel_ddi_put_crtc_pll(crtc);
4303 }
4304
4305 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4306 {
4307 struct drm_device *dev = crtc->base.dev;
4308 struct drm_i915_private *dev_priv = dev->dev_private;
4309 struct intel_crtc_config *pipe_config = &crtc->config;
4310
4311 if (!crtc->config.gmch_pfit.control)
4312 return;
4313
4314 /*
4315 * The panel fitter should only be adjusted whilst the pipe is disabled,
4316 * according to register description and PRM.
4317 */
4318 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4319 assert_pipe_disabled(dev_priv, crtc->pipe);
4320
4321 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4322 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4323
4324 /* Border color in case we don't scale up to the full screen. Black by
4325 * default, change to something else for debugging. */
4326 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4327 }
4328
4329 #define for_each_power_domain(domain, mask) \
4330 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4331 if ((1 << (domain)) & (mask))
4332
4333 enum intel_display_power_domain
4334 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4335 {
4336 struct drm_device *dev = intel_encoder->base.dev;
4337 struct intel_digital_port *intel_dig_port;
4338
4339 switch (intel_encoder->type) {
4340 case INTEL_OUTPUT_UNKNOWN:
4341 /* Only DDI platforms should ever use this output type */
4342 WARN_ON_ONCE(!HAS_DDI(dev));
4343 case INTEL_OUTPUT_DISPLAYPORT:
4344 case INTEL_OUTPUT_HDMI:
4345 case INTEL_OUTPUT_EDP:
4346 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4347 switch (intel_dig_port->port) {
4348 case PORT_A:
4349 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4350 case PORT_B:
4351 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4352 case PORT_C:
4353 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4354 case PORT_D:
4355 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4356 default:
4357 WARN_ON_ONCE(1);
4358 return POWER_DOMAIN_PORT_OTHER;
4359 }
4360 case INTEL_OUTPUT_ANALOG:
4361 return POWER_DOMAIN_PORT_CRT;
4362 case INTEL_OUTPUT_DSI:
4363 return POWER_DOMAIN_PORT_DSI;
4364 default:
4365 return POWER_DOMAIN_PORT_OTHER;
4366 }
4367 }
4368
4369 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4370 {
4371 struct drm_device *dev = crtc->dev;
4372 struct intel_encoder *intel_encoder;
4373 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4374 enum pipe pipe = intel_crtc->pipe;
4375 bool pfit_enabled = intel_crtc->config.pch_pfit.enabled;
4376 unsigned long mask;
4377 enum transcoder transcoder;
4378
4379 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4380
4381 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4382 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4383 if (pfit_enabled)
4384 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4385
4386 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4387 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4388
4389 return mask;
4390 }
4391
4392 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4393 bool enable)
4394 {
4395 if (dev_priv->power_domains.init_power_on == enable)
4396 return;
4397
4398 if (enable)
4399 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4400 else
4401 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4402
4403 dev_priv->power_domains.init_power_on = enable;
4404 }
4405
4406 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4407 {
4408 struct drm_i915_private *dev_priv = dev->dev_private;
4409 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4410 struct intel_crtc *crtc;
4411
4412 /*
4413 * First get all needed power domains, then put all unneeded, to avoid
4414 * any unnecessary toggling of the power wells.
4415 */
4416 for_each_intel_crtc(dev, crtc) {
4417 enum intel_display_power_domain domain;
4418
4419 if (!crtc->base.enabled)
4420 continue;
4421
4422 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4423
4424 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4425 intel_display_power_get(dev_priv, domain);
4426 }
4427
4428 for_each_intel_crtc(dev, crtc) {
4429 enum intel_display_power_domain domain;
4430
4431 for_each_power_domain(domain, crtc->enabled_power_domains)
4432 intel_display_power_put(dev_priv, domain);
4433
4434 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4435 }
4436
4437 intel_display_set_init_power(dev_priv, false);
4438 }
4439
4440 int valleyview_get_vco(struct drm_i915_private *dev_priv)
4441 {
4442 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4443
4444 /* Obtain SKU information */
4445 mutex_lock(&dev_priv->dpio_lock);
4446 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4447 CCK_FUSE_HPLL_FREQ_MASK;
4448 mutex_unlock(&dev_priv->dpio_lock);
4449
4450 return vco_freq[hpll_freq];
4451 }
4452
4453 /* Adjust CDclk dividers to allow high res or save power if possible */
4454 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4455 {
4456 struct drm_i915_private *dev_priv = dev->dev_private;
4457 u32 val, cmd;
4458
4459 WARN_ON(valleyview_cur_cdclk(dev_priv) != dev_priv->vlv_cdclk_freq);
4460 dev_priv->vlv_cdclk_freq = cdclk;
4461
4462 if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
4463 cmd = 2;
4464 else if (cdclk == 266)
4465 cmd = 1;
4466 else
4467 cmd = 0;
4468
4469 mutex_lock(&dev_priv->rps.hw_lock);
4470 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4471 val &= ~DSPFREQGUAR_MASK;
4472 val |= (cmd << DSPFREQGUAR_SHIFT);
4473 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4474 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4475 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4476 50)) {
4477 DRM_ERROR("timed out waiting for CDclk change\n");
4478 }
4479 mutex_unlock(&dev_priv->rps.hw_lock);
4480
4481 if (cdclk == 400) {
4482 u32 divider, vco;
4483
4484 vco = valleyview_get_vco(dev_priv);
4485 divider = ((vco << 1) / cdclk) - 1;
4486
4487 mutex_lock(&dev_priv->dpio_lock);
4488 /* adjust cdclk divider */
4489 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4490 val &= ~0xf;
4491 val |= divider;
4492 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4493 mutex_unlock(&dev_priv->dpio_lock);
4494 }
4495
4496 mutex_lock(&dev_priv->dpio_lock);
4497 /* adjust self-refresh exit latency value */
4498 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4499 val &= ~0x7f;
4500
4501 /*
4502 * For high bandwidth configs, we set a higher latency in the bunit
4503 * so that the core display fetch happens in time to avoid underruns.
4504 */
4505 if (cdclk == 400)
4506 val |= 4500 / 250; /* 4.5 usec */
4507 else
4508 val |= 3000 / 250; /* 3.0 usec */
4509 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4510 mutex_unlock(&dev_priv->dpio_lock);
4511
4512 /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4513 intel_i2c_reset(dev);
4514 }
4515
4516 int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4517 {
4518 int cur_cdclk, vco;
4519 int divider;
4520
4521 vco = valleyview_get_vco(dev_priv);
4522
4523 mutex_lock(&dev_priv->dpio_lock);
4524 divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4525 mutex_unlock(&dev_priv->dpio_lock);
4526
4527 divider &= 0xf;
4528
4529 cur_cdclk = (vco << 1) / (divider + 1);
4530
4531 return cur_cdclk;
4532 }
4533
4534 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4535 int max_pixclk)
4536 {
4537 /*
4538 * Really only a few cases to deal with, as only 4 CDclks are supported:
4539 * 200MHz
4540 * 267MHz
4541 * 320MHz
4542 * 400MHz
4543 * So we check to see whether we're above 90% of the lower bin and
4544 * adjust if needed.
4545 */
4546 if (max_pixclk > 288000) {
4547 return 400;
4548 } else if (max_pixclk > 240000) {
4549 return 320;
4550 } else
4551 return 266;
4552 /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4553 }
4554
4555 /* compute the max pixel clock for new configuration */
4556 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4557 {
4558 struct drm_device *dev = dev_priv->dev;
4559 struct intel_crtc *intel_crtc;
4560 int max_pixclk = 0;
4561
4562 for_each_intel_crtc(dev, intel_crtc) {
4563 if (intel_crtc->new_enabled)
4564 max_pixclk = max(max_pixclk,
4565 intel_crtc->new_config->adjusted_mode.crtc_clock);
4566 }
4567
4568 return max_pixclk;
4569 }
4570
4571 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4572 unsigned *prepare_pipes)
4573 {
4574 struct drm_i915_private *dev_priv = dev->dev_private;
4575 struct intel_crtc *intel_crtc;
4576 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4577
4578 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4579 dev_priv->vlv_cdclk_freq)
4580 return;
4581
4582 /* disable/enable all currently active pipes while we change cdclk */
4583 for_each_intel_crtc(dev, intel_crtc)
4584 if (intel_crtc->base.enabled)
4585 *prepare_pipes |= (1 << intel_crtc->pipe);
4586 }
4587
4588 static void valleyview_modeset_global_resources(struct drm_device *dev)
4589 {
4590 struct drm_i915_private *dev_priv = dev->dev_private;
4591 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4592 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4593
4594 if (req_cdclk != dev_priv->vlv_cdclk_freq)
4595 valleyview_set_cdclk(dev, req_cdclk);
4596 modeset_update_crtc_power_domains(dev);
4597 }
4598
4599 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4600 {
4601 struct drm_device *dev = crtc->dev;
4602 struct drm_i915_private *dev_priv = dev->dev_private;
4603 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4604 struct intel_encoder *encoder;
4605 int pipe = intel_crtc->pipe;
4606 int plane = intel_crtc->plane;
4607 bool is_dsi;
4608 u32 dspcntr;
4609
4610 WARN_ON(!crtc->enabled);
4611
4612 if (intel_crtc->active)
4613 return;
4614
4615 vlv_prepare_pll(intel_crtc);
4616
4617 /* Set up the display plane register */
4618 dspcntr = DISPPLANE_GAMMA_ENABLE;
4619
4620 if (intel_crtc->config.has_dp_encoder)
4621 intel_dp_set_m_n(intel_crtc);
4622
4623 intel_set_pipe_timings(intel_crtc);
4624
4625 /* pipesrc and dspsize control the size that is scaled from,
4626 * which should always be the user's requested size.
4627 */
4628 I915_WRITE(DSPSIZE(plane),
4629 ((intel_crtc->config.pipe_src_h - 1) << 16) |
4630 (intel_crtc->config.pipe_src_w - 1));
4631 I915_WRITE(DSPPOS(plane), 0);
4632
4633 i9xx_set_pipeconf(intel_crtc);
4634
4635 I915_WRITE(DSPCNTR(plane), dspcntr);
4636 POSTING_READ(DSPCNTR(plane));
4637
4638 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4639 crtc->x, crtc->y);
4640
4641 intel_crtc->active = true;
4642
4643 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4644
4645 for_each_encoder_on_crtc(dev, crtc, encoder)
4646 if (encoder->pre_pll_enable)
4647 encoder->pre_pll_enable(encoder);
4648
4649 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4650
4651 if (!is_dsi) {
4652 if (IS_CHERRYVIEW(dev))
4653 chv_enable_pll(intel_crtc);
4654 else
4655 vlv_enable_pll(intel_crtc);
4656 }
4657
4658 for_each_encoder_on_crtc(dev, crtc, encoder)
4659 if (encoder->pre_enable)
4660 encoder->pre_enable(encoder);
4661
4662 i9xx_pfit_enable(intel_crtc);
4663
4664 intel_crtc_load_lut(crtc);
4665
4666 intel_update_watermarks(crtc);
4667 intel_enable_pipe(intel_crtc);
4668
4669 for_each_encoder_on_crtc(dev, crtc, encoder)
4670 encoder->enable(encoder);
4671
4672 intel_crtc_enable_planes(crtc);
4673
4674 /* Underruns don't raise interrupts, so check manually. */
4675 i9xx_check_fifo_underruns(dev);
4676 }
4677
4678 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4679 {
4680 struct drm_device *dev = crtc->base.dev;
4681 struct drm_i915_private *dev_priv = dev->dev_private;
4682
4683 I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4684 I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4685 }
4686
4687 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4688 {
4689 struct drm_device *dev = crtc->dev;
4690 struct drm_i915_private *dev_priv = dev->dev_private;
4691 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4692 struct intel_encoder *encoder;
4693 int pipe = intel_crtc->pipe;
4694 int plane = intel_crtc->plane;
4695 u32 dspcntr;
4696
4697 WARN_ON(!crtc->enabled);
4698
4699 if (intel_crtc->active)
4700 return;
4701
4702 i9xx_set_pll_dividers(intel_crtc);
4703
4704 /* Set up the display plane register */
4705 dspcntr = DISPPLANE_GAMMA_ENABLE;
4706
4707 if (pipe == 0)
4708 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4709 else
4710 dspcntr |= DISPPLANE_SEL_PIPE_B;
4711
4712 if (intel_crtc->config.has_dp_encoder)
4713 intel_dp_set_m_n(intel_crtc);
4714
4715 intel_set_pipe_timings(intel_crtc);
4716
4717 /* pipesrc and dspsize control the size that is scaled from,
4718 * which should always be the user's requested size.
4719 */
4720 I915_WRITE(DSPSIZE(plane),
4721 ((intel_crtc->config.pipe_src_h - 1) << 16) |
4722 (intel_crtc->config.pipe_src_w - 1));
4723 I915_WRITE(DSPPOS(plane), 0);
4724
4725 i9xx_set_pipeconf(intel_crtc);
4726
4727 I915_WRITE(DSPCNTR(plane), dspcntr);
4728 POSTING_READ(DSPCNTR(plane));
4729
4730 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4731 crtc->x, crtc->y);
4732
4733 intel_crtc->active = true;
4734
4735 if (!IS_GEN2(dev))
4736 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4737
4738 for_each_encoder_on_crtc(dev, crtc, encoder)
4739 if (encoder->pre_enable)
4740 encoder->pre_enable(encoder);
4741
4742 i9xx_enable_pll(intel_crtc);
4743
4744 i9xx_pfit_enable(intel_crtc);
4745
4746 intel_crtc_load_lut(crtc);
4747
4748 intel_update_watermarks(crtc);
4749 intel_enable_pipe(intel_crtc);
4750
4751 for_each_encoder_on_crtc(dev, crtc, encoder)
4752 encoder->enable(encoder);
4753
4754 intel_crtc_enable_planes(crtc);
4755
4756 /*
4757 * Gen2 reports pipe underruns whenever all planes are disabled.
4758 * So don't enable underrun reporting before at least some planes
4759 * are enabled.
4760 * FIXME: Need to fix the logic to work when we turn off all planes
4761 * but leave the pipe running.
4762 */
4763 if (IS_GEN2(dev))
4764 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4765
4766 /* Underruns don't raise interrupts, so check manually. */
4767 i9xx_check_fifo_underruns(dev);
4768 }
4769
4770 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4771 {
4772 struct drm_device *dev = crtc->base.dev;
4773 struct drm_i915_private *dev_priv = dev->dev_private;
4774
4775 if (!crtc->config.gmch_pfit.control)
4776 return;
4777
4778 assert_pipe_disabled(dev_priv, crtc->pipe);
4779
4780 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4781 I915_READ(PFIT_CONTROL));
4782 I915_WRITE(PFIT_CONTROL, 0);
4783 }
4784
4785 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4786 {
4787 struct drm_device *dev = crtc->dev;
4788 struct drm_i915_private *dev_priv = dev->dev_private;
4789 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4790 struct intel_encoder *encoder;
4791 int pipe = intel_crtc->pipe;
4792
4793 if (!intel_crtc->active)
4794 return;
4795
4796 /*
4797 * Gen2 reports pipe underruns whenever all planes are disabled.
4798 * So diasble underrun reporting before all the planes get disabled.
4799 * FIXME: Need to fix the logic to work when we turn off all planes
4800 * but leave the pipe running.
4801 */
4802 if (IS_GEN2(dev))
4803 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4804
4805 intel_crtc_disable_planes(crtc);
4806
4807 for_each_encoder_on_crtc(dev, crtc, encoder)
4808 encoder->disable(encoder);
4809
4810 /*
4811 * On gen2 planes are double buffered but the pipe isn't, so we must
4812 * wait for planes to fully turn off before disabling the pipe.
4813 */
4814 if (IS_GEN2(dev))
4815 intel_wait_for_vblank(dev, pipe);
4816
4817 intel_disable_pipe(dev_priv, pipe);
4818
4819 i9xx_pfit_disable(intel_crtc);
4820
4821 for_each_encoder_on_crtc(dev, crtc, encoder)
4822 if (encoder->post_disable)
4823 encoder->post_disable(encoder);
4824
4825 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4826 if (IS_CHERRYVIEW(dev))
4827 chv_disable_pll(dev_priv, pipe);
4828 else if (IS_VALLEYVIEW(dev))
4829 vlv_disable_pll(dev_priv, pipe);
4830 else
4831 i9xx_disable_pll(dev_priv, pipe);
4832 }
4833
4834 if (!IS_GEN2(dev))
4835 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4836
4837 intel_crtc->active = false;
4838 intel_update_watermarks(crtc);
4839
4840 mutex_lock(&dev->struct_mutex);
4841 intel_update_fbc(dev);
4842 mutex_unlock(&dev->struct_mutex);
4843 }
4844
4845 static void i9xx_crtc_off(struct drm_crtc *crtc)
4846 {
4847 }
4848
4849 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4850 bool enabled)
4851 {
4852 struct drm_device *dev = crtc->dev;
4853 struct drm_i915_master_private *master_priv;
4854 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4855 int pipe = intel_crtc->pipe;
4856
4857 if (!dev->primary->master)
4858 return;
4859
4860 master_priv = dev->primary->master->driver_priv;
4861 if (!master_priv->sarea_priv)
4862 return;
4863
4864 switch (pipe) {
4865 case 0:
4866 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4867 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4868 break;
4869 case 1:
4870 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4871 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4872 break;
4873 default:
4874 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4875 break;
4876 }
4877 }
4878
4879 /**
4880 * Sets the power management mode of the pipe and plane.
4881 */
4882 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4883 {
4884 struct drm_device *dev = crtc->dev;
4885 struct drm_i915_private *dev_priv = dev->dev_private;
4886 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4887 struct intel_encoder *intel_encoder;
4888 enum intel_display_power_domain domain;
4889 unsigned long domains;
4890 bool enable = false;
4891
4892 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4893 enable |= intel_encoder->connectors_active;
4894
4895 if (enable) {
4896 if (!intel_crtc->active) {
4897 /*
4898 * FIXME: DDI plls and relevant code isn't converted
4899 * yet, so do runtime PM for DPMS only for all other
4900 * platforms for now.
4901 */
4902 if (!HAS_DDI(dev)) {
4903 domains = get_crtc_power_domains(crtc);
4904 for_each_power_domain(domain, domains)
4905 intel_display_power_get(dev_priv, domain);
4906 intel_crtc->enabled_power_domains = domains;
4907 }
4908
4909 dev_priv->display.crtc_enable(crtc);
4910 }
4911 } else {
4912 if (intel_crtc->active) {
4913 dev_priv->display.crtc_disable(crtc);
4914
4915 if (!HAS_DDI(dev)) {
4916 domains = intel_crtc->enabled_power_domains;
4917 for_each_power_domain(domain, domains)
4918 intel_display_power_put(dev_priv, domain);
4919 intel_crtc->enabled_power_domains = 0;
4920 }
4921 }
4922 }
4923
4924 intel_crtc_update_sarea(crtc, enable);
4925 }
4926
4927 static void intel_crtc_disable(struct drm_crtc *crtc)
4928 {
4929 struct drm_device *dev = crtc->dev;
4930 struct drm_connector *connector;
4931 struct drm_i915_private *dev_priv = dev->dev_private;
4932 struct drm_i915_gem_object *old_obj;
4933 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4934
4935 /* crtc should still be enabled when we disable it. */
4936 WARN_ON(!crtc->enabled);
4937
4938 dev_priv->display.crtc_disable(crtc);
4939 intel_crtc_update_sarea(crtc, false);
4940 dev_priv->display.off(crtc);
4941
4942 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4943 assert_cursor_disabled(dev_priv, pipe);
4944 assert_pipe_disabled(dev->dev_private, pipe);
4945
4946 if (crtc->primary->fb) {
4947 old_obj = to_intel_framebuffer(crtc->primary->fb)->obj;
4948 mutex_lock(&dev->struct_mutex);
4949 intel_unpin_fb_obj(old_obj);
4950 i915_gem_track_fb(old_obj, NULL,
4951 INTEL_FRONTBUFFER_PRIMARY(pipe));
4952 mutex_unlock(&dev->struct_mutex);
4953 crtc->primary->fb = NULL;
4954 }
4955
4956 /* Update computed state. */
4957 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4958 if (!connector->encoder || !connector->encoder->crtc)
4959 continue;
4960
4961 if (connector->encoder->crtc != crtc)
4962 continue;
4963
4964 connector->dpms = DRM_MODE_DPMS_OFF;
4965 to_intel_encoder(connector->encoder)->connectors_active = false;
4966 }
4967 }
4968
4969 void intel_encoder_destroy(struct drm_encoder *encoder)
4970 {
4971 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4972
4973 drm_encoder_cleanup(encoder);
4974 kfree(intel_encoder);
4975 }
4976
4977 /* Simple dpms helper for encoders with just one connector, no cloning and only
4978 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4979 * state of the entire output pipe. */
4980 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4981 {
4982 if (mode == DRM_MODE_DPMS_ON) {
4983 encoder->connectors_active = true;
4984
4985 intel_crtc_update_dpms(encoder->base.crtc);
4986 } else {
4987 encoder->connectors_active = false;
4988
4989 intel_crtc_update_dpms(encoder->base.crtc);
4990 }
4991 }
4992
4993 /* Cross check the actual hw state with our own modeset state tracking (and it's
4994 * internal consistency). */
4995 static void intel_connector_check_state(struct intel_connector *connector)
4996 {
4997 if (connector->get_hw_state(connector)) {
4998 struct intel_encoder *encoder = connector->encoder;
4999 struct drm_crtc *crtc;
5000 bool encoder_enabled;
5001 enum pipe pipe;
5002
5003 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5004 connector->base.base.id,
5005 connector->base.name);
5006
5007 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5008 "wrong connector dpms state\n");
5009 WARN(connector->base.encoder != &encoder->base,
5010 "active connector not linked to encoder\n");
5011 WARN(!encoder->connectors_active,
5012 "encoder->connectors_active not set\n");
5013
5014 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5015 WARN(!encoder_enabled, "encoder not enabled\n");
5016 if (WARN_ON(!encoder->base.crtc))
5017 return;
5018
5019 crtc = encoder->base.crtc;
5020
5021 WARN(!crtc->enabled, "crtc not enabled\n");
5022 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5023 WARN(pipe != to_intel_crtc(crtc)->pipe,
5024 "encoder active on the wrong pipe\n");
5025 }
5026 }
5027
5028 /* Even simpler default implementation, if there's really no special case to
5029 * consider. */
5030 void intel_connector_dpms(struct drm_connector *connector, int mode)
5031 {
5032 /* All the simple cases only support two dpms states. */
5033 if (mode != DRM_MODE_DPMS_ON)
5034 mode = DRM_MODE_DPMS_OFF;
5035
5036 if (mode == connector->dpms)
5037 return;
5038
5039 connector->dpms = mode;
5040
5041 /* Only need to change hw state when actually enabled */
5042 if (connector->encoder)
5043 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5044
5045 intel_modeset_check_state(connector->dev);
5046 }
5047
5048 /* Simple connector->get_hw_state implementation for encoders that support only
5049 * one connector and no cloning and hence the encoder state determines the state
5050 * of the connector. */
5051 bool intel_connector_get_hw_state(struct intel_connector *connector)
5052 {
5053 enum pipe pipe = 0;
5054 struct intel_encoder *encoder = connector->encoder;
5055
5056 return encoder->get_hw_state(encoder, &pipe);
5057 }
5058
5059 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5060 struct intel_crtc_config *pipe_config)
5061 {
5062 struct drm_i915_private *dev_priv = dev->dev_private;
5063 struct intel_crtc *pipe_B_crtc =
5064 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5065
5066 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5067 pipe_name(pipe), pipe_config->fdi_lanes);
5068 if (pipe_config->fdi_lanes > 4) {
5069 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5070 pipe_name(pipe), pipe_config->fdi_lanes);
5071 return false;
5072 }
5073
5074 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5075 if (pipe_config->fdi_lanes > 2) {
5076 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5077 pipe_config->fdi_lanes);
5078 return false;
5079 } else {
5080 return true;
5081 }
5082 }
5083
5084 if (INTEL_INFO(dev)->num_pipes == 2)
5085 return true;
5086
5087 /* Ivybridge 3 pipe is really complicated */
5088 switch (pipe) {
5089 case PIPE_A:
5090 return true;
5091 case PIPE_B:
5092 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5093 pipe_config->fdi_lanes > 2) {
5094 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5095 pipe_name(pipe), pipe_config->fdi_lanes);
5096 return false;
5097 }
5098 return true;
5099 case PIPE_C:
5100 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5101 pipe_B_crtc->config.fdi_lanes <= 2) {
5102 if (pipe_config->fdi_lanes > 2) {
5103 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5104 pipe_name(pipe), pipe_config->fdi_lanes);
5105 return false;
5106 }
5107 } else {
5108 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5109 return false;
5110 }
5111 return true;
5112 default:
5113 BUG();
5114 }
5115 }
5116
5117 #define RETRY 1
5118 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5119 struct intel_crtc_config *pipe_config)
5120 {
5121 struct drm_device *dev = intel_crtc->base.dev;
5122 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5123 int lane, link_bw, fdi_dotclock;
5124 bool setup_ok, needs_recompute = false;
5125
5126 retry:
5127 /* FDI is a binary signal running at ~2.7GHz, encoding
5128 * each output octet as 10 bits. The actual frequency
5129 * is stored as a divider into a 100MHz clock, and the
5130 * mode pixel clock is stored in units of 1KHz.
5131 * Hence the bw of each lane in terms of the mode signal
5132 * is:
5133 */
5134 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5135
5136 fdi_dotclock = adjusted_mode->crtc_clock;
5137
5138 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5139 pipe_config->pipe_bpp);
5140
5141 pipe_config->fdi_lanes = lane;
5142
5143 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5144 link_bw, &pipe_config->fdi_m_n);
5145
5146 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5147 intel_crtc->pipe, pipe_config);
5148 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5149 pipe_config->pipe_bpp -= 2*3;
5150 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5151 pipe_config->pipe_bpp);
5152 needs_recompute = true;
5153 pipe_config->bw_constrained = true;
5154
5155 goto retry;
5156 }
5157
5158 if (needs_recompute)
5159 return RETRY;
5160
5161 return setup_ok ? 0 : -EINVAL;
5162 }
5163
5164 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5165 struct intel_crtc_config *pipe_config)
5166 {
5167 pipe_config->ips_enabled = i915.enable_ips &&
5168 hsw_crtc_supports_ips(crtc) &&
5169 pipe_config->pipe_bpp <= 24;
5170 }
5171
5172 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5173 struct intel_crtc_config *pipe_config)
5174 {
5175 struct drm_device *dev = crtc->base.dev;
5176 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5177
5178 /* FIXME should check pixel clock limits on all platforms */
5179 if (INTEL_INFO(dev)->gen < 4) {
5180 struct drm_i915_private *dev_priv = dev->dev_private;
5181 int clock_limit =
5182 dev_priv->display.get_display_clock_speed(dev);
5183
5184 /*
5185 * Enable pixel doubling when the dot clock
5186 * is > 90% of the (display) core speed.
5187 *
5188 * GDG double wide on either pipe,
5189 * otherwise pipe A only.
5190 */
5191 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5192 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5193 clock_limit *= 2;
5194 pipe_config->double_wide = true;
5195 }
5196
5197 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5198 return -EINVAL;
5199 }
5200
5201 /*
5202 * Pipe horizontal size must be even in:
5203 * - DVO ganged mode
5204 * - LVDS dual channel mode
5205 * - Double wide pipe
5206 */
5207 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5208 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5209 pipe_config->pipe_src_w &= ~1;
5210
5211 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5212 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5213 */
5214 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5215 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5216 return -EINVAL;
5217
5218 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5219 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5220 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5221 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5222 * for lvds. */
5223 pipe_config->pipe_bpp = 8*3;
5224 }
5225
5226 if (HAS_IPS(dev))
5227 hsw_compute_ips_config(crtc, pipe_config);
5228
5229 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
5230 * clock survives for now. */
5231 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5232 pipe_config->shared_dpll = crtc->config.shared_dpll;
5233
5234 if (pipe_config->has_pch_encoder)
5235 return ironlake_fdi_compute_config(crtc, pipe_config);
5236
5237 return 0;
5238 }
5239
5240 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5241 {
5242 return 400000; /* FIXME */
5243 }
5244
5245 static int i945_get_display_clock_speed(struct drm_device *dev)
5246 {
5247 return 400000;
5248 }
5249
5250 static int i915_get_display_clock_speed(struct drm_device *dev)
5251 {
5252 return 333000;
5253 }
5254
5255 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5256 {
5257 return 200000;
5258 }
5259
5260 static int pnv_get_display_clock_speed(struct drm_device *dev)
5261 {
5262 u16 gcfgc = 0;
5263
5264 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5265
5266 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5267 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5268 return 267000;
5269 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5270 return 333000;
5271 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5272 return 444000;
5273 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5274 return 200000;
5275 default:
5276 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5277 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5278 return 133000;
5279 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5280 return 167000;
5281 }
5282 }
5283
5284 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5285 {
5286 u16 gcfgc = 0;
5287
5288 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5289
5290 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5291 return 133000;
5292 else {
5293 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5294 case GC_DISPLAY_CLOCK_333_MHZ:
5295 return 333000;
5296 default:
5297 case GC_DISPLAY_CLOCK_190_200_MHZ:
5298 return 190000;
5299 }
5300 }
5301 }
5302
5303 static int i865_get_display_clock_speed(struct drm_device *dev)
5304 {
5305 return 266000;
5306 }
5307
5308 static int i855_get_display_clock_speed(struct drm_device *dev)
5309 {
5310 u16 hpllcc = 0;
5311 /* Assume that the hardware is in the high speed state. This
5312 * should be the default.
5313 */
5314 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5315 case GC_CLOCK_133_200:
5316 case GC_CLOCK_100_200:
5317 return 200000;
5318 case GC_CLOCK_166_250:
5319 return 250000;
5320 case GC_CLOCK_100_133:
5321 return 133000;
5322 }
5323
5324 /* Shouldn't happen */
5325 return 0;
5326 }
5327
5328 static int i830_get_display_clock_speed(struct drm_device *dev)
5329 {
5330 return 133000;
5331 }
5332
5333 static void
5334 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5335 {
5336 while (*num > DATA_LINK_M_N_MASK ||
5337 *den > DATA_LINK_M_N_MASK) {
5338 *num >>= 1;
5339 *den >>= 1;
5340 }
5341 }
5342
5343 static void compute_m_n(unsigned int m, unsigned int n,
5344 uint32_t *ret_m, uint32_t *ret_n)
5345 {
5346 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5347 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5348 intel_reduce_m_n_ratio(ret_m, ret_n);
5349 }
5350
5351 void
5352 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5353 int pixel_clock, int link_clock,
5354 struct intel_link_m_n *m_n)
5355 {
5356 m_n->tu = 64;
5357
5358 compute_m_n(bits_per_pixel * pixel_clock,
5359 link_clock * nlanes * 8,
5360 &m_n->gmch_m, &m_n->gmch_n);
5361
5362 compute_m_n(pixel_clock, link_clock,
5363 &m_n->link_m, &m_n->link_n);
5364 }
5365
5366 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5367 {
5368 if (i915.panel_use_ssc >= 0)
5369 return i915.panel_use_ssc != 0;
5370 return dev_priv->vbt.lvds_use_ssc
5371 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5372 }
5373
5374 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5375 {
5376 struct drm_device *dev = crtc->dev;
5377 struct drm_i915_private *dev_priv = dev->dev_private;
5378 int refclk;
5379
5380 if (IS_VALLEYVIEW(dev)) {
5381 refclk = 100000;
5382 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5383 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5384 refclk = dev_priv->vbt.lvds_ssc_freq;
5385 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5386 } else if (!IS_GEN2(dev)) {
5387 refclk = 96000;
5388 } else {
5389 refclk = 48000;
5390 }
5391
5392 return refclk;
5393 }
5394
5395 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5396 {
5397 return (1 << dpll->n) << 16 | dpll->m2;
5398 }
5399
5400 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5401 {
5402 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5403 }
5404
5405 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5406 intel_clock_t *reduced_clock)
5407 {
5408 struct drm_device *dev = crtc->base.dev;
5409 u32 fp, fp2 = 0;
5410
5411 if (IS_PINEVIEW(dev)) {
5412 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5413 if (reduced_clock)
5414 fp2 = pnv_dpll_compute_fp(reduced_clock);
5415 } else {
5416 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5417 if (reduced_clock)
5418 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5419 }
5420
5421 crtc->config.dpll_hw_state.fp0 = fp;
5422
5423 crtc->lowfreq_avail = false;
5424 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5425 reduced_clock && i915.powersave) {
5426 crtc->config.dpll_hw_state.fp1 = fp2;
5427 crtc->lowfreq_avail = true;
5428 } else {
5429 crtc->config.dpll_hw_state.fp1 = fp;
5430 }
5431 }
5432
5433 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5434 pipe)
5435 {
5436 u32 reg_val;
5437
5438 /*
5439 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5440 * and set it to a reasonable value instead.
5441 */
5442 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5443 reg_val &= 0xffffff00;
5444 reg_val |= 0x00000030;
5445 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5446
5447 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5448 reg_val &= 0x8cffffff;
5449 reg_val = 0x8c000000;
5450 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5451
5452 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5453 reg_val &= 0xffffff00;
5454 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5455
5456 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5457 reg_val &= 0x00ffffff;
5458 reg_val |= 0xb0000000;
5459 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5460 }
5461
5462 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5463 struct intel_link_m_n *m_n)
5464 {
5465 struct drm_device *dev = crtc->base.dev;
5466 struct drm_i915_private *dev_priv = dev->dev_private;
5467 int pipe = crtc->pipe;
5468
5469 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5470 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5471 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5472 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5473 }
5474
5475 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5476 struct intel_link_m_n *m_n)
5477 {
5478 struct drm_device *dev = crtc->base.dev;
5479 struct drm_i915_private *dev_priv = dev->dev_private;
5480 int pipe = crtc->pipe;
5481 enum transcoder transcoder = crtc->config.cpu_transcoder;
5482
5483 if (INTEL_INFO(dev)->gen >= 5) {
5484 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5485 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5486 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5487 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5488 } else {
5489 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5490 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5491 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5492 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5493 }
5494 }
5495
5496 static void intel_dp_set_m_n(struct intel_crtc *crtc)
5497 {
5498 if (crtc->config.has_pch_encoder)
5499 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5500 else
5501 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5502 }
5503
5504 static void vlv_update_pll(struct intel_crtc *crtc)
5505 {
5506 u32 dpll, dpll_md;
5507
5508 /*
5509 * Enable DPIO clock input. We should never disable the reference
5510 * clock for pipe B, since VGA hotplug / manual detection depends
5511 * on it.
5512 */
5513 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5514 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5515 /* We should never disable this, set it here for state tracking */
5516 if (crtc->pipe == PIPE_B)
5517 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5518 dpll |= DPLL_VCO_ENABLE;
5519 crtc->config.dpll_hw_state.dpll = dpll;
5520
5521 dpll_md = (crtc->config.pixel_multiplier - 1)
5522 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5523 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5524 }
5525
5526 static void vlv_prepare_pll(struct intel_crtc *crtc)
5527 {
5528 struct drm_device *dev = crtc->base.dev;
5529 struct drm_i915_private *dev_priv = dev->dev_private;
5530 int pipe = crtc->pipe;
5531 u32 mdiv;
5532 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5533 u32 coreclk, reg_val;
5534
5535 mutex_lock(&dev_priv->dpio_lock);
5536
5537 bestn = crtc->config.dpll.n;
5538 bestm1 = crtc->config.dpll.m1;
5539 bestm2 = crtc->config.dpll.m2;
5540 bestp1 = crtc->config.dpll.p1;
5541 bestp2 = crtc->config.dpll.p2;
5542
5543 /* See eDP HDMI DPIO driver vbios notes doc */
5544
5545 /* PLL B needs special handling */
5546 if (pipe == PIPE_B)
5547 vlv_pllb_recal_opamp(dev_priv, pipe);
5548
5549 /* Set up Tx target for periodic Rcomp update */
5550 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5551
5552 /* Disable target IRef on PLL */
5553 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5554 reg_val &= 0x00ffffff;
5555 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5556
5557 /* Disable fast lock */
5558 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5559
5560 /* Set idtafcrecal before PLL is enabled */
5561 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5562 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5563 mdiv |= ((bestn << DPIO_N_SHIFT));
5564 mdiv |= (1 << DPIO_K_SHIFT);
5565
5566 /*
5567 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5568 * but we don't support that).
5569 * Note: don't use the DAC post divider as it seems unstable.
5570 */
5571 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5572 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5573
5574 mdiv |= DPIO_ENABLE_CALIBRATION;
5575 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5576
5577 /* Set HBR and RBR LPF coefficients */
5578 if (crtc->config.port_clock == 162000 ||
5579 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5580 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5581 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5582 0x009f0003);
5583 else
5584 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5585 0x00d0000f);
5586
5587 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5588 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5589 /* Use SSC source */
5590 if (pipe == PIPE_A)
5591 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5592 0x0df40000);
5593 else
5594 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5595 0x0df70000);
5596 } else { /* HDMI or VGA */
5597 /* Use bend source */
5598 if (pipe == PIPE_A)
5599 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5600 0x0df70000);
5601 else
5602 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5603 0x0df40000);
5604 }
5605
5606 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5607 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5608 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5609 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5610 coreclk |= 0x01000000;
5611 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5612
5613 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5614 mutex_unlock(&dev_priv->dpio_lock);
5615 }
5616
5617 static void chv_update_pll(struct intel_crtc *crtc)
5618 {
5619 struct drm_device *dev = crtc->base.dev;
5620 struct drm_i915_private *dev_priv = dev->dev_private;
5621 int pipe = crtc->pipe;
5622 int dpll_reg = DPLL(crtc->pipe);
5623 enum dpio_channel port = vlv_pipe_to_channel(pipe);
5624 u32 loopfilter, intcoeff;
5625 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5626 int refclk;
5627
5628 crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5629 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5630 DPLL_VCO_ENABLE;
5631 if (pipe != PIPE_A)
5632 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5633
5634 crtc->config.dpll_hw_state.dpll_md =
5635 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5636
5637 bestn = crtc->config.dpll.n;
5638 bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5639 bestm1 = crtc->config.dpll.m1;
5640 bestm2 = crtc->config.dpll.m2 >> 22;
5641 bestp1 = crtc->config.dpll.p1;
5642 bestp2 = crtc->config.dpll.p2;
5643
5644 /*
5645 * Enable Refclk and SSC
5646 */
5647 I915_WRITE(dpll_reg,
5648 crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5649
5650 mutex_lock(&dev_priv->dpio_lock);
5651
5652 /* p1 and p2 divider */
5653 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5654 5 << DPIO_CHV_S1_DIV_SHIFT |
5655 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5656 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5657 1 << DPIO_CHV_K_DIV_SHIFT);
5658
5659 /* Feedback post-divider - m2 */
5660 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5661
5662 /* Feedback refclk divider - n and m1 */
5663 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5664 DPIO_CHV_M1_DIV_BY_2 |
5665 1 << DPIO_CHV_N_DIV_SHIFT);
5666
5667 /* M2 fraction division */
5668 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5669
5670 /* M2 fraction division enable */
5671 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5672 DPIO_CHV_FRAC_DIV_EN |
5673 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5674
5675 /* Loop filter */
5676 refclk = i9xx_get_refclk(&crtc->base, 0);
5677 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5678 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5679 if (refclk == 100000)
5680 intcoeff = 11;
5681 else if (refclk == 38400)
5682 intcoeff = 10;
5683 else
5684 intcoeff = 9;
5685 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5686 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5687
5688 /* AFC Recal */
5689 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5690 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5691 DPIO_AFC_RECAL);
5692
5693 mutex_unlock(&dev_priv->dpio_lock);
5694 }
5695
5696 static void i9xx_update_pll(struct intel_crtc *crtc,
5697 intel_clock_t *reduced_clock,
5698 int num_connectors)
5699 {
5700 struct drm_device *dev = crtc->base.dev;
5701 struct drm_i915_private *dev_priv = dev->dev_private;
5702 u32 dpll;
5703 bool is_sdvo;
5704 struct dpll *clock = &crtc->config.dpll;
5705
5706 i9xx_update_pll_dividers(crtc, reduced_clock);
5707
5708 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5709 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5710
5711 dpll = DPLL_VGA_MODE_DIS;
5712
5713 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5714 dpll |= DPLLB_MODE_LVDS;
5715 else
5716 dpll |= DPLLB_MODE_DAC_SERIAL;
5717
5718 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5719 dpll |= (crtc->config.pixel_multiplier - 1)
5720 << SDVO_MULTIPLIER_SHIFT_HIRES;
5721 }
5722
5723 if (is_sdvo)
5724 dpll |= DPLL_SDVO_HIGH_SPEED;
5725
5726 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5727 dpll |= DPLL_SDVO_HIGH_SPEED;
5728
5729 /* compute bitmask from p1 value */
5730 if (IS_PINEVIEW(dev))
5731 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5732 else {
5733 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5734 if (IS_G4X(dev) && reduced_clock)
5735 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5736 }
5737 switch (clock->p2) {
5738 case 5:
5739 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5740 break;
5741 case 7:
5742 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5743 break;
5744 case 10:
5745 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5746 break;
5747 case 14:
5748 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5749 break;
5750 }
5751 if (INTEL_INFO(dev)->gen >= 4)
5752 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5753
5754 if (crtc->config.sdvo_tv_clock)
5755 dpll |= PLL_REF_INPUT_TVCLKINBC;
5756 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5757 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5758 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5759 else
5760 dpll |= PLL_REF_INPUT_DREFCLK;
5761
5762 dpll |= DPLL_VCO_ENABLE;
5763 crtc->config.dpll_hw_state.dpll = dpll;
5764
5765 if (INTEL_INFO(dev)->gen >= 4) {
5766 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5767 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5768 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5769 }
5770 }
5771
5772 static void i8xx_update_pll(struct intel_crtc *crtc,
5773 intel_clock_t *reduced_clock,
5774 int num_connectors)
5775 {
5776 struct drm_device *dev = crtc->base.dev;
5777 struct drm_i915_private *dev_priv = dev->dev_private;
5778 u32 dpll;
5779 struct dpll *clock = &crtc->config.dpll;
5780
5781 i9xx_update_pll_dividers(crtc, reduced_clock);
5782
5783 dpll = DPLL_VGA_MODE_DIS;
5784
5785 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5786 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5787 } else {
5788 if (clock->p1 == 2)
5789 dpll |= PLL_P1_DIVIDE_BY_TWO;
5790 else
5791 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5792 if (clock->p2 == 4)
5793 dpll |= PLL_P2_DIVIDE_BY_4;
5794 }
5795
5796 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5797 dpll |= DPLL_DVO_2X_MODE;
5798
5799 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5800 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5801 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5802 else
5803 dpll |= PLL_REF_INPUT_DREFCLK;
5804
5805 dpll |= DPLL_VCO_ENABLE;
5806 crtc->config.dpll_hw_state.dpll = dpll;
5807 }
5808
5809 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5810 {
5811 struct drm_device *dev = intel_crtc->base.dev;
5812 struct drm_i915_private *dev_priv = dev->dev_private;
5813 enum pipe pipe = intel_crtc->pipe;
5814 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5815 struct drm_display_mode *adjusted_mode =
5816 &intel_crtc->config.adjusted_mode;
5817 uint32_t crtc_vtotal, crtc_vblank_end;
5818 int vsyncshift = 0;
5819
5820 /* We need to be careful not to changed the adjusted mode, for otherwise
5821 * the hw state checker will get angry at the mismatch. */
5822 crtc_vtotal = adjusted_mode->crtc_vtotal;
5823 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5824
5825 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5826 /* the chip adds 2 halflines automatically */
5827 crtc_vtotal -= 1;
5828 crtc_vblank_end -= 1;
5829
5830 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5831 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5832 else
5833 vsyncshift = adjusted_mode->crtc_hsync_start -
5834 adjusted_mode->crtc_htotal / 2;
5835 if (vsyncshift < 0)
5836 vsyncshift += adjusted_mode->crtc_htotal;
5837 }
5838
5839 if (INTEL_INFO(dev)->gen > 3)
5840 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5841
5842 I915_WRITE(HTOTAL(cpu_transcoder),
5843 (adjusted_mode->crtc_hdisplay - 1) |
5844 ((adjusted_mode->crtc_htotal - 1) << 16));
5845 I915_WRITE(HBLANK(cpu_transcoder),
5846 (adjusted_mode->crtc_hblank_start - 1) |
5847 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5848 I915_WRITE(HSYNC(cpu_transcoder),
5849 (adjusted_mode->crtc_hsync_start - 1) |
5850 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5851
5852 I915_WRITE(VTOTAL(cpu_transcoder),
5853 (adjusted_mode->crtc_vdisplay - 1) |
5854 ((crtc_vtotal - 1) << 16));
5855 I915_WRITE(VBLANK(cpu_transcoder),
5856 (adjusted_mode->crtc_vblank_start - 1) |
5857 ((crtc_vblank_end - 1) << 16));
5858 I915_WRITE(VSYNC(cpu_transcoder),
5859 (adjusted_mode->crtc_vsync_start - 1) |
5860 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5861
5862 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5863 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5864 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5865 * bits. */
5866 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5867 (pipe == PIPE_B || pipe == PIPE_C))
5868 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5869
5870 /* pipesrc controls the size that is scaled from, which should
5871 * always be the user's requested size.
5872 */
5873 I915_WRITE(PIPESRC(pipe),
5874 ((intel_crtc->config.pipe_src_w - 1) << 16) |
5875 (intel_crtc->config.pipe_src_h - 1));
5876 }
5877
5878 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5879 struct intel_crtc_config *pipe_config)
5880 {
5881 struct drm_device *dev = crtc->base.dev;
5882 struct drm_i915_private *dev_priv = dev->dev_private;
5883 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5884 uint32_t tmp;
5885
5886 tmp = I915_READ(HTOTAL(cpu_transcoder));
5887 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5888 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5889 tmp = I915_READ(HBLANK(cpu_transcoder));
5890 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5891 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5892 tmp = I915_READ(HSYNC(cpu_transcoder));
5893 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5894 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5895
5896 tmp = I915_READ(VTOTAL(cpu_transcoder));
5897 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5898 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5899 tmp = I915_READ(VBLANK(cpu_transcoder));
5900 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5901 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5902 tmp = I915_READ(VSYNC(cpu_transcoder));
5903 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5904 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5905
5906 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5907 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5908 pipe_config->adjusted_mode.crtc_vtotal += 1;
5909 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5910 }
5911
5912 tmp = I915_READ(PIPESRC(crtc->pipe));
5913 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5914 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5915
5916 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5917 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5918 }
5919
5920 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5921 struct intel_crtc_config *pipe_config)
5922 {
5923 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5924 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5925 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5926 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5927
5928 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5929 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5930 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5931 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5932
5933 mode->flags = pipe_config->adjusted_mode.flags;
5934
5935 mode->clock = pipe_config->adjusted_mode.crtc_clock;
5936 mode->flags |= pipe_config->adjusted_mode.flags;
5937 }
5938
5939 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5940 {
5941 struct drm_device *dev = intel_crtc->base.dev;
5942 struct drm_i915_private *dev_priv = dev->dev_private;
5943 uint32_t pipeconf;
5944
5945 pipeconf = 0;
5946
5947 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5948 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5949 pipeconf |= PIPECONF_ENABLE;
5950
5951 if (intel_crtc->config.double_wide)
5952 pipeconf |= PIPECONF_DOUBLE_WIDE;
5953
5954 /* only g4x and later have fancy bpc/dither controls */
5955 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5956 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5957 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5958 pipeconf |= PIPECONF_DITHER_EN |
5959 PIPECONF_DITHER_TYPE_SP;
5960
5961 switch (intel_crtc->config.pipe_bpp) {
5962 case 18:
5963 pipeconf |= PIPECONF_6BPC;
5964 break;
5965 case 24:
5966 pipeconf |= PIPECONF_8BPC;
5967 break;
5968 case 30:
5969 pipeconf |= PIPECONF_10BPC;
5970 break;
5971 default:
5972 /* Case prevented by intel_choose_pipe_bpp_dither. */
5973 BUG();
5974 }
5975 }
5976
5977 if (HAS_PIPE_CXSR(dev)) {
5978 if (intel_crtc->lowfreq_avail) {
5979 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5980 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5981 } else {
5982 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5983 }
5984 }
5985
5986 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
5987 if (INTEL_INFO(dev)->gen < 4 ||
5988 intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5989 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5990 else
5991 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
5992 } else
5993 pipeconf |= PIPECONF_PROGRESSIVE;
5994
5995 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5996 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5997
5998 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5999 POSTING_READ(PIPECONF(intel_crtc->pipe));
6000 }
6001
6002 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
6003 int x, int y,
6004 struct drm_framebuffer *fb)
6005 {
6006 struct drm_device *dev = crtc->dev;
6007 struct drm_i915_private *dev_priv = dev->dev_private;
6008 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6009 int refclk, num_connectors = 0;
6010 intel_clock_t clock, reduced_clock;
6011 bool ok, has_reduced_clock = false;
6012 bool is_lvds = false, is_dsi = false;
6013 struct intel_encoder *encoder;
6014 const intel_limit_t *limit;
6015
6016 for_each_encoder_on_crtc(dev, crtc, encoder) {
6017 switch (encoder->type) {
6018 case INTEL_OUTPUT_LVDS:
6019 is_lvds = true;
6020 break;
6021 case INTEL_OUTPUT_DSI:
6022 is_dsi = true;
6023 break;
6024 }
6025
6026 num_connectors++;
6027 }
6028
6029 if (is_dsi)
6030 return 0;
6031
6032 if (!intel_crtc->config.clock_set) {
6033 refclk = i9xx_get_refclk(crtc, num_connectors);
6034
6035 /*
6036 * Returns a set of divisors for the desired target clock with
6037 * the given refclk, or FALSE. The returned values represent
6038 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6039 * 2) / p1 / p2.
6040 */
6041 limit = intel_limit(crtc, refclk);
6042 ok = dev_priv->display.find_dpll(limit, crtc,
6043 intel_crtc->config.port_clock,
6044 refclk, NULL, &clock);
6045 if (!ok) {
6046 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6047 return -EINVAL;
6048 }
6049
6050 if (is_lvds && dev_priv->lvds_downclock_avail) {
6051 /*
6052 * Ensure we match the reduced clock's P to the target
6053 * clock. If the clocks don't match, we can't switch
6054 * the display clock by using the FP0/FP1. In such case
6055 * we will disable the LVDS downclock feature.
6056 */
6057 has_reduced_clock =
6058 dev_priv->display.find_dpll(limit, crtc,
6059 dev_priv->lvds_downclock,
6060 refclk, &clock,
6061 &reduced_clock);
6062 }
6063 /* Compat-code for transition, will disappear. */
6064 intel_crtc->config.dpll.n = clock.n;
6065 intel_crtc->config.dpll.m1 = clock.m1;
6066 intel_crtc->config.dpll.m2 = clock.m2;
6067 intel_crtc->config.dpll.p1 = clock.p1;
6068 intel_crtc->config.dpll.p2 = clock.p2;
6069 }
6070
6071 if (IS_GEN2(dev)) {
6072 i8xx_update_pll(intel_crtc,
6073 has_reduced_clock ? &reduced_clock : NULL,
6074 num_connectors);
6075 } else if (IS_CHERRYVIEW(dev)) {
6076 chv_update_pll(intel_crtc);
6077 } else if (IS_VALLEYVIEW(dev)) {
6078 vlv_update_pll(intel_crtc);
6079 } else {
6080 i9xx_update_pll(intel_crtc,
6081 has_reduced_clock ? &reduced_clock : NULL,
6082 num_connectors);
6083 }
6084
6085 return 0;
6086 }
6087
6088 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6089 struct intel_crtc_config *pipe_config)
6090 {
6091 struct drm_device *dev = crtc->base.dev;
6092 struct drm_i915_private *dev_priv = dev->dev_private;
6093 uint32_t tmp;
6094
6095 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6096 return;
6097
6098 tmp = I915_READ(PFIT_CONTROL);
6099 if (!(tmp & PFIT_ENABLE))
6100 return;
6101
6102 /* Check whether the pfit is attached to our pipe. */
6103 if (INTEL_INFO(dev)->gen < 4) {
6104 if (crtc->pipe != PIPE_B)
6105 return;
6106 } else {
6107 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6108 return;
6109 }
6110
6111 pipe_config->gmch_pfit.control = tmp;
6112 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6113 if (INTEL_INFO(dev)->gen < 5)
6114 pipe_config->gmch_pfit.lvds_border_bits =
6115 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6116 }
6117
6118 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6119 struct intel_crtc_config *pipe_config)
6120 {
6121 struct drm_device *dev = crtc->base.dev;
6122 struct drm_i915_private *dev_priv = dev->dev_private;
6123 int pipe = pipe_config->cpu_transcoder;
6124 intel_clock_t clock;
6125 u32 mdiv;
6126 int refclk = 100000;
6127
6128 mutex_lock(&dev_priv->dpio_lock);
6129 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6130 mutex_unlock(&dev_priv->dpio_lock);
6131
6132 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6133 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6134 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6135 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6136 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6137
6138 vlv_clock(refclk, &clock);
6139
6140 /* clock.dot is the fast clock */
6141 pipe_config->port_clock = clock.dot / 5;
6142 }
6143
6144 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6145 struct intel_plane_config *plane_config)
6146 {
6147 struct drm_device *dev = crtc->base.dev;
6148 struct drm_i915_private *dev_priv = dev->dev_private;
6149 u32 val, base, offset;
6150 int pipe = crtc->pipe, plane = crtc->plane;
6151 int fourcc, pixel_format;
6152 int aligned_height;
6153
6154 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6155 if (!crtc->base.primary->fb) {
6156 DRM_DEBUG_KMS("failed to alloc fb\n");
6157 return;
6158 }
6159
6160 val = I915_READ(DSPCNTR(plane));
6161
6162 if (INTEL_INFO(dev)->gen >= 4)
6163 if (val & DISPPLANE_TILED)
6164 plane_config->tiled = true;
6165
6166 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6167 fourcc = intel_format_to_fourcc(pixel_format);
6168 crtc->base.primary->fb->pixel_format = fourcc;
6169 crtc->base.primary->fb->bits_per_pixel =
6170 drm_format_plane_cpp(fourcc, 0) * 8;
6171
6172 if (INTEL_INFO(dev)->gen >= 4) {
6173 if (plane_config->tiled)
6174 offset = I915_READ(DSPTILEOFF(plane));
6175 else
6176 offset = I915_READ(DSPLINOFF(plane));
6177 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6178 } else {
6179 base = I915_READ(DSPADDR(plane));
6180 }
6181 plane_config->base = base;
6182
6183 val = I915_READ(PIPESRC(pipe));
6184 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6185 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6186
6187 val = I915_READ(DSPSTRIDE(pipe));
6188 crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
6189
6190 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6191 plane_config->tiled);
6192
6193 plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
6194 aligned_height, PAGE_SIZE);
6195
6196 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6197 pipe, plane, crtc->base.primary->fb->width,
6198 crtc->base.primary->fb->height,
6199 crtc->base.primary->fb->bits_per_pixel, base,
6200 crtc->base.primary->fb->pitches[0],
6201 plane_config->size);
6202
6203 }
6204
6205 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6206 struct intel_crtc_config *pipe_config)
6207 {
6208 struct drm_device *dev = crtc->base.dev;
6209 struct drm_i915_private *dev_priv = dev->dev_private;
6210 int pipe = pipe_config->cpu_transcoder;
6211 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6212 intel_clock_t clock;
6213 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6214 int refclk = 100000;
6215
6216 mutex_lock(&dev_priv->dpio_lock);
6217 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6218 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6219 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6220 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6221 mutex_unlock(&dev_priv->dpio_lock);
6222
6223 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6224 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6225 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6226 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6227 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6228
6229 chv_clock(refclk, &clock);
6230
6231 /* clock.dot is the fast clock */
6232 pipe_config->port_clock = clock.dot / 5;
6233 }
6234
6235 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6236 struct intel_crtc_config *pipe_config)
6237 {
6238 struct drm_device *dev = crtc->base.dev;
6239 struct drm_i915_private *dev_priv = dev->dev_private;
6240 uint32_t tmp;
6241
6242 if (!intel_display_power_enabled(dev_priv,
6243 POWER_DOMAIN_PIPE(crtc->pipe)))
6244 return false;
6245
6246 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6247 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6248
6249 tmp = I915_READ(PIPECONF(crtc->pipe));
6250 if (!(tmp & PIPECONF_ENABLE))
6251 return false;
6252
6253 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6254 switch (tmp & PIPECONF_BPC_MASK) {
6255 case PIPECONF_6BPC:
6256 pipe_config->pipe_bpp = 18;
6257 break;
6258 case PIPECONF_8BPC:
6259 pipe_config->pipe_bpp = 24;
6260 break;
6261 case PIPECONF_10BPC:
6262 pipe_config->pipe_bpp = 30;
6263 break;
6264 default:
6265 break;
6266 }
6267 }
6268
6269 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6270 pipe_config->limited_color_range = true;
6271
6272 if (INTEL_INFO(dev)->gen < 4)
6273 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6274
6275 intel_get_pipe_timings(crtc, pipe_config);
6276
6277 i9xx_get_pfit_config(crtc, pipe_config);
6278
6279 if (INTEL_INFO(dev)->gen >= 4) {
6280 tmp = I915_READ(DPLL_MD(crtc->pipe));
6281 pipe_config->pixel_multiplier =
6282 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6283 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6284 pipe_config->dpll_hw_state.dpll_md = tmp;
6285 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6286 tmp = I915_READ(DPLL(crtc->pipe));
6287 pipe_config->pixel_multiplier =
6288 ((tmp & SDVO_MULTIPLIER_MASK)
6289 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6290 } else {
6291 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6292 * port and will be fixed up in the encoder->get_config
6293 * function. */
6294 pipe_config->pixel_multiplier = 1;
6295 }
6296 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6297 if (!IS_VALLEYVIEW(dev)) {
6298 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6299 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6300 } else {
6301 /* Mask out read-only status bits. */
6302 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6303 DPLL_PORTC_READY_MASK |
6304 DPLL_PORTB_READY_MASK);
6305 }
6306
6307 if (IS_CHERRYVIEW(dev))
6308 chv_crtc_clock_get(crtc, pipe_config);
6309 else if (IS_VALLEYVIEW(dev))
6310 vlv_crtc_clock_get(crtc, pipe_config);
6311 else
6312 i9xx_crtc_clock_get(crtc, pipe_config);
6313
6314 return true;
6315 }
6316
6317 static void ironlake_init_pch_refclk(struct drm_device *dev)
6318 {
6319 struct drm_i915_private *dev_priv = dev->dev_private;
6320 struct drm_mode_config *mode_config = &dev->mode_config;
6321 struct intel_encoder *encoder;
6322 u32 val, final;
6323 bool has_lvds = false;
6324 bool has_cpu_edp = false;
6325 bool has_panel = false;
6326 bool has_ck505 = false;
6327 bool can_ssc = false;
6328
6329 /* We need to take the global config into account */
6330 list_for_each_entry(encoder, &mode_config->encoder_list,
6331 base.head) {
6332 switch (encoder->type) {
6333 case INTEL_OUTPUT_LVDS:
6334 has_panel = true;
6335 has_lvds = true;
6336 break;
6337 case INTEL_OUTPUT_EDP:
6338 has_panel = true;
6339 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6340 has_cpu_edp = true;
6341 break;
6342 }
6343 }
6344
6345 if (HAS_PCH_IBX(dev)) {
6346 has_ck505 = dev_priv->vbt.display_clock_mode;
6347 can_ssc = has_ck505;
6348 } else {
6349 has_ck505 = false;
6350 can_ssc = true;
6351 }
6352
6353 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6354 has_panel, has_lvds, has_ck505);
6355
6356 /* Ironlake: try to setup display ref clock before DPLL
6357 * enabling. This is only under driver's control after
6358 * PCH B stepping, previous chipset stepping should be
6359 * ignoring this setting.
6360 */
6361 val = I915_READ(PCH_DREF_CONTROL);
6362
6363 /* As we must carefully and slowly disable/enable each source in turn,
6364 * compute the final state we want first and check if we need to
6365 * make any changes at all.
6366 */
6367 final = val;
6368 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6369 if (has_ck505)
6370 final |= DREF_NONSPREAD_CK505_ENABLE;
6371 else
6372 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6373
6374 final &= ~DREF_SSC_SOURCE_MASK;
6375 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6376 final &= ~DREF_SSC1_ENABLE;
6377
6378 if (has_panel) {
6379 final |= DREF_SSC_SOURCE_ENABLE;
6380
6381 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6382 final |= DREF_SSC1_ENABLE;
6383
6384 if (has_cpu_edp) {
6385 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6386 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6387 else
6388 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6389 } else
6390 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6391 } else {
6392 final |= DREF_SSC_SOURCE_DISABLE;
6393 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6394 }
6395
6396 if (final == val)
6397 return;
6398
6399 /* Always enable nonspread source */
6400 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6401
6402 if (has_ck505)
6403 val |= DREF_NONSPREAD_CK505_ENABLE;
6404 else
6405 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6406
6407 if (has_panel) {
6408 val &= ~DREF_SSC_SOURCE_MASK;
6409 val |= DREF_SSC_SOURCE_ENABLE;
6410
6411 /* SSC must be turned on before enabling the CPU output */
6412 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6413 DRM_DEBUG_KMS("Using SSC on panel\n");
6414 val |= DREF_SSC1_ENABLE;
6415 } else
6416 val &= ~DREF_SSC1_ENABLE;
6417
6418 /* Get SSC going before enabling the outputs */
6419 I915_WRITE(PCH_DREF_CONTROL, val);
6420 POSTING_READ(PCH_DREF_CONTROL);
6421 udelay(200);
6422
6423 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6424
6425 /* Enable CPU source on CPU attached eDP */
6426 if (has_cpu_edp) {
6427 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6428 DRM_DEBUG_KMS("Using SSC on eDP\n");
6429 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6430 } else
6431 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6432 } else
6433 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6434
6435 I915_WRITE(PCH_DREF_CONTROL, val);
6436 POSTING_READ(PCH_DREF_CONTROL);
6437 udelay(200);
6438 } else {
6439 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6440
6441 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6442
6443 /* Turn off CPU output */
6444 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6445
6446 I915_WRITE(PCH_DREF_CONTROL, val);
6447 POSTING_READ(PCH_DREF_CONTROL);
6448 udelay(200);
6449
6450 /* Turn off the SSC source */
6451 val &= ~DREF_SSC_SOURCE_MASK;
6452 val |= DREF_SSC_SOURCE_DISABLE;
6453
6454 /* Turn off SSC1 */
6455 val &= ~DREF_SSC1_ENABLE;
6456
6457 I915_WRITE(PCH_DREF_CONTROL, val);
6458 POSTING_READ(PCH_DREF_CONTROL);
6459 udelay(200);
6460 }
6461
6462 BUG_ON(val != final);
6463 }
6464
6465 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6466 {
6467 uint32_t tmp;
6468
6469 tmp = I915_READ(SOUTH_CHICKEN2);
6470 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6471 I915_WRITE(SOUTH_CHICKEN2, tmp);
6472
6473 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6474 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6475 DRM_ERROR("FDI mPHY reset assert timeout\n");
6476
6477 tmp = I915_READ(SOUTH_CHICKEN2);
6478 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6479 I915_WRITE(SOUTH_CHICKEN2, tmp);
6480
6481 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6482 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6483 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6484 }
6485
6486 /* WaMPhyProgramming:hsw */
6487 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6488 {
6489 uint32_t tmp;
6490
6491 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6492 tmp &= ~(0xFF << 24);
6493 tmp |= (0x12 << 24);
6494 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6495
6496 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6497 tmp |= (1 << 11);
6498 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6499
6500 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6501 tmp |= (1 << 11);
6502 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6503
6504 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6505 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6506 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6507
6508 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6509 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6510 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6511
6512 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6513 tmp &= ~(7 << 13);
6514 tmp |= (5 << 13);
6515 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6516
6517 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6518 tmp &= ~(7 << 13);
6519 tmp |= (5 << 13);
6520 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6521
6522 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6523 tmp &= ~0xFF;
6524 tmp |= 0x1C;
6525 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6526
6527 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6528 tmp &= ~0xFF;
6529 tmp |= 0x1C;
6530 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6531
6532 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6533 tmp &= ~(0xFF << 16);
6534 tmp |= (0x1C << 16);
6535 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6536
6537 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6538 tmp &= ~(0xFF << 16);
6539 tmp |= (0x1C << 16);
6540 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6541
6542 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6543 tmp |= (1 << 27);
6544 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6545
6546 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6547 tmp |= (1 << 27);
6548 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6549
6550 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6551 tmp &= ~(0xF << 28);
6552 tmp |= (4 << 28);
6553 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6554
6555 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6556 tmp &= ~(0xF << 28);
6557 tmp |= (4 << 28);
6558 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6559 }
6560
6561 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6562 * Programming" based on the parameters passed:
6563 * - Sequence to enable CLKOUT_DP
6564 * - Sequence to enable CLKOUT_DP without spread
6565 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6566 */
6567 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6568 bool with_fdi)
6569 {
6570 struct drm_i915_private *dev_priv = dev->dev_private;
6571 uint32_t reg, tmp;
6572
6573 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6574 with_spread = true;
6575 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6576 with_fdi, "LP PCH doesn't have FDI\n"))
6577 with_fdi = false;
6578
6579 mutex_lock(&dev_priv->dpio_lock);
6580
6581 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6582 tmp &= ~SBI_SSCCTL_DISABLE;
6583 tmp |= SBI_SSCCTL_PATHALT;
6584 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6585
6586 udelay(24);
6587
6588 if (with_spread) {
6589 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6590 tmp &= ~SBI_SSCCTL_PATHALT;
6591 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6592
6593 if (with_fdi) {
6594 lpt_reset_fdi_mphy(dev_priv);
6595 lpt_program_fdi_mphy(dev_priv);
6596 }
6597 }
6598
6599 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6600 SBI_GEN0 : SBI_DBUFF0;
6601 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6602 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6603 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6604
6605 mutex_unlock(&dev_priv->dpio_lock);
6606 }
6607
6608 /* Sequence to disable CLKOUT_DP */
6609 static void lpt_disable_clkout_dp(struct drm_device *dev)
6610 {
6611 struct drm_i915_private *dev_priv = dev->dev_private;
6612 uint32_t reg, tmp;
6613
6614 mutex_lock(&dev_priv->dpio_lock);
6615
6616 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6617 SBI_GEN0 : SBI_DBUFF0;
6618 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6619 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6620 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6621
6622 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6623 if (!(tmp & SBI_SSCCTL_DISABLE)) {
6624 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6625 tmp |= SBI_SSCCTL_PATHALT;
6626 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6627 udelay(32);
6628 }
6629 tmp |= SBI_SSCCTL_DISABLE;
6630 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6631 }
6632
6633 mutex_unlock(&dev_priv->dpio_lock);
6634 }
6635
6636 static void lpt_init_pch_refclk(struct drm_device *dev)
6637 {
6638 struct drm_mode_config *mode_config = &dev->mode_config;
6639 struct intel_encoder *encoder;
6640 bool has_vga = false;
6641
6642 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
6643 switch (encoder->type) {
6644 case INTEL_OUTPUT_ANALOG:
6645 has_vga = true;
6646 break;
6647 }
6648 }
6649
6650 if (has_vga)
6651 lpt_enable_clkout_dp(dev, true, true);
6652 else
6653 lpt_disable_clkout_dp(dev);
6654 }
6655
6656 /*
6657 * Initialize reference clocks when the driver loads
6658 */
6659 void intel_init_pch_refclk(struct drm_device *dev)
6660 {
6661 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6662 ironlake_init_pch_refclk(dev);
6663 else if (HAS_PCH_LPT(dev))
6664 lpt_init_pch_refclk(dev);
6665 }
6666
6667 static int ironlake_get_refclk(struct drm_crtc *crtc)
6668 {
6669 struct drm_device *dev = crtc->dev;
6670 struct drm_i915_private *dev_priv = dev->dev_private;
6671 struct intel_encoder *encoder;
6672 int num_connectors = 0;
6673 bool is_lvds = false;
6674
6675 for_each_encoder_on_crtc(dev, crtc, encoder) {
6676 switch (encoder->type) {
6677 case INTEL_OUTPUT_LVDS:
6678 is_lvds = true;
6679 break;
6680 }
6681 num_connectors++;
6682 }
6683
6684 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6685 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6686 dev_priv->vbt.lvds_ssc_freq);
6687 return dev_priv->vbt.lvds_ssc_freq;
6688 }
6689
6690 return 120000;
6691 }
6692
6693 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6694 {
6695 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6696 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6697 int pipe = intel_crtc->pipe;
6698 uint32_t val;
6699
6700 val = 0;
6701
6702 switch (intel_crtc->config.pipe_bpp) {
6703 case 18:
6704 val |= PIPECONF_6BPC;
6705 break;
6706 case 24:
6707 val |= PIPECONF_8BPC;
6708 break;
6709 case 30:
6710 val |= PIPECONF_10BPC;
6711 break;
6712 case 36:
6713 val |= PIPECONF_12BPC;
6714 break;
6715 default:
6716 /* Case prevented by intel_choose_pipe_bpp_dither. */
6717 BUG();
6718 }
6719
6720 if (intel_crtc->config.dither)
6721 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6722
6723 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6724 val |= PIPECONF_INTERLACED_ILK;
6725 else
6726 val |= PIPECONF_PROGRESSIVE;
6727
6728 if (intel_crtc->config.limited_color_range)
6729 val |= PIPECONF_COLOR_RANGE_SELECT;
6730
6731 I915_WRITE(PIPECONF(pipe), val);
6732 POSTING_READ(PIPECONF(pipe));
6733 }
6734
6735 /*
6736 * Set up the pipe CSC unit.
6737 *
6738 * Currently only full range RGB to limited range RGB conversion
6739 * is supported, but eventually this should handle various
6740 * RGB<->YCbCr scenarios as well.
6741 */
6742 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6743 {
6744 struct drm_device *dev = crtc->dev;
6745 struct drm_i915_private *dev_priv = dev->dev_private;
6746 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6747 int pipe = intel_crtc->pipe;
6748 uint16_t coeff = 0x7800; /* 1.0 */
6749
6750 /*
6751 * TODO: Check what kind of values actually come out of the pipe
6752 * with these coeff/postoff values and adjust to get the best
6753 * accuracy. Perhaps we even need to take the bpc value into
6754 * consideration.
6755 */
6756
6757 if (intel_crtc->config.limited_color_range)
6758 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6759
6760 /*
6761 * GY/GU and RY/RU should be the other way around according
6762 * to BSpec, but reality doesn't agree. Just set them up in
6763 * a way that results in the correct picture.
6764 */
6765 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6766 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6767
6768 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6769 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6770
6771 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6772 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6773
6774 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6775 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6776 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6777
6778 if (INTEL_INFO(dev)->gen > 6) {
6779 uint16_t postoff = 0;
6780
6781 if (intel_crtc->config.limited_color_range)
6782 postoff = (16 * (1 << 12) / 255) & 0x1fff;
6783
6784 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6785 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6786 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6787
6788 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6789 } else {
6790 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6791
6792 if (intel_crtc->config.limited_color_range)
6793 mode |= CSC_BLACK_SCREEN_OFFSET;
6794
6795 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6796 }
6797 }
6798
6799 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6800 {
6801 struct drm_device *dev = crtc->dev;
6802 struct drm_i915_private *dev_priv = dev->dev_private;
6803 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6804 enum pipe pipe = intel_crtc->pipe;
6805 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6806 uint32_t val;
6807
6808 val = 0;
6809
6810 if (IS_HASWELL(dev) && intel_crtc->config.dither)
6811 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6812
6813 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6814 val |= PIPECONF_INTERLACED_ILK;
6815 else
6816 val |= PIPECONF_PROGRESSIVE;
6817
6818 I915_WRITE(PIPECONF(cpu_transcoder), val);
6819 POSTING_READ(PIPECONF(cpu_transcoder));
6820
6821 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6822 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6823
6824 if (IS_BROADWELL(dev)) {
6825 val = 0;
6826
6827 switch (intel_crtc->config.pipe_bpp) {
6828 case 18:
6829 val |= PIPEMISC_DITHER_6_BPC;
6830 break;
6831 case 24:
6832 val |= PIPEMISC_DITHER_8_BPC;
6833 break;
6834 case 30:
6835 val |= PIPEMISC_DITHER_10_BPC;
6836 break;
6837 case 36:
6838 val |= PIPEMISC_DITHER_12_BPC;
6839 break;
6840 default:
6841 /* Case prevented by pipe_config_set_bpp. */
6842 BUG();
6843 }
6844
6845 if (intel_crtc->config.dither)
6846 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6847
6848 I915_WRITE(PIPEMISC(pipe), val);
6849 }
6850 }
6851
6852 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6853 intel_clock_t *clock,
6854 bool *has_reduced_clock,
6855 intel_clock_t *reduced_clock)
6856 {
6857 struct drm_device *dev = crtc->dev;
6858 struct drm_i915_private *dev_priv = dev->dev_private;
6859 struct intel_encoder *intel_encoder;
6860 int refclk;
6861 const intel_limit_t *limit;
6862 bool ret, is_lvds = false;
6863
6864 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6865 switch (intel_encoder->type) {
6866 case INTEL_OUTPUT_LVDS:
6867 is_lvds = true;
6868 break;
6869 }
6870 }
6871
6872 refclk = ironlake_get_refclk(crtc);
6873
6874 /*
6875 * Returns a set of divisors for the desired target clock with the given
6876 * refclk, or FALSE. The returned values represent the clock equation:
6877 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6878 */
6879 limit = intel_limit(crtc, refclk);
6880 ret = dev_priv->display.find_dpll(limit, crtc,
6881 to_intel_crtc(crtc)->config.port_clock,
6882 refclk, NULL, clock);
6883 if (!ret)
6884 return false;
6885
6886 if (is_lvds && dev_priv->lvds_downclock_avail) {
6887 /*
6888 * Ensure we match the reduced clock's P to the target clock.
6889 * If the clocks don't match, we can't switch the display clock
6890 * by using the FP0/FP1. In such case we will disable the LVDS
6891 * downclock feature.
6892 */
6893 *has_reduced_clock =
6894 dev_priv->display.find_dpll(limit, crtc,
6895 dev_priv->lvds_downclock,
6896 refclk, clock,
6897 reduced_clock);
6898 }
6899
6900 return true;
6901 }
6902
6903 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6904 {
6905 /*
6906 * Account for spread spectrum to avoid
6907 * oversubscribing the link. Max center spread
6908 * is 2.5%; use 5% for safety's sake.
6909 */
6910 u32 bps = target_clock * bpp * 21 / 20;
6911 return DIV_ROUND_UP(bps, link_bw * 8);
6912 }
6913
6914 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6915 {
6916 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6917 }
6918
6919 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6920 u32 *fp,
6921 intel_clock_t *reduced_clock, u32 *fp2)
6922 {
6923 struct drm_crtc *crtc = &intel_crtc->base;
6924 struct drm_device *dev = crtc->dev;
6925 struct drm_i915_private *dev_priv = dev->dev_private;
6926 struct intel_encoder *intel_encoder;
6927 uint32_t dpll;
6928 int factor, num_connectors = 0;
6929 bool is_lvds = false, is_sdvo = false;
6930
6931 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6932 switch (intel_encoder->type) {
6933 case INTEL_OUTPUT_LVDS:
6934 is_lvds = true;
6935 break;
6936 case INTEL_OUTPUT_SDVO:
6937 case INTEL_OUTPUT_HDMI:
6938 is_sdvo = true;
6939 break;
6940 }
6941
6942 num_connectors++;
6943 }
6944
6945 /* Enable autotuning of the PLL clock (if permissible) */
6946 factor = 21;
6947 if (is_lvds) {
6948 if ((intel_panel_use_ssc(dev_priv) &&
6949 dev_priv->vbt.lvds_ssc_freq == 100000) ||
6950 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6951 factor = 25;
6952 } else if (intel_crtc->config.sdvo_tv_clock)
6953 factor = 20;
6954
6955 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6956 *fp |= FP_CB_TUNE;
6957
6958 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6959 *fp2 |= FP_CB_TUNE;
6960
6961 dpll = 0;
6962
6963 if (is_lvds)
6964 dpll |= DPLLB_MODE_LVDS;
6965 else
6966 dpll |= DPLLB_MODE_DAC_SERIAL;
6967
6968 dpll |= (intel_crtc->config.pixel_multiplier - 1)
6969 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6970
6971 if (is_sdvo)
6972 dpll |= DPLL_SDVO_HIGH_SPEED;
6973 if (intel_crtc->config.has_dp_encoder)
6974 dpll |= DPLL_SDVO_HIGH_SPEED;
6975
6976 /* compute bitmask from p1 value */
6977 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6978 /* also FPA1 */
6979 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6980
6981 switch (intel_crtc->config.dpll.p2) {
6982 case 5:
6983 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6984 break;
6985 case 7:
6986 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6987 break;
6988 case 10:
6989 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6990 break;
6991 case 14:
6992 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6993 break;
6994 }
6995
6996 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6997 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6998 else
6999 dpll |= PLL_REF_INPUT_DREFCLK;
7000
7001 return dpll | DPLL_VCO_ENABLE;
7002 }
7003
7004 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
7005 int x, int y,
7006 struct drm_framebuffer *fb)
7007 {
7008 struct drm_device *dev = crtc->dev;
7009 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7010 int num_connectors = 0;
7011 intel_clock_t clock, reduced_clock;
7012 u32 dpll = 0, fp = 0, fp2 = 0;
7013 bool ok, has_reduced_clock = false;
7014 bool is_lvds = false;
7015 struct intel_encoder *encoder;
7016 struct intel_shared_dpll *pll;
7017
7018 for_each_encoder_on_crtc(dev, crtc, encoder) {
7019 switch (encoder->type) {
7020 case INTEL_OUTPUT_LVDS:
7021 is_lvds = true;
7022 break;
7023 }
7024
7025 num_connectors++;
7026 }
7027
7028 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7029 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7030
7031 ok = ironlake_compute_clocks(crtc, &clock,
7032 &has_reduced_clock, &reduced_clock);
7033 if (!ok && !intel_crtc->config.clock_set) {
7034 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7035 return -EINVAL;
7036 }
7037 /* Compat-code for transition, will disappear. */
7038 if (!intel_crtc->config.clock_set) {
7039 intel_crtc->config.dpll.n = clock.n;
7040 intel_crtc->config.dpll.m1 = clock.m1;
7041 intel_crtc->config.dpll.m2 = clock.m2;
7042 intel_crtc->config.dpll.p1 = clock.p1;
7043 intel_crtc->config.dpll.p2 = clock.p2;
7044 }
7045
7046 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7047 if (intel_crtc->config.has_pch_encoder) {
7048 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
7049 if (has_reduced_clock)
7050 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7051
7052 dpll = ironlake_compute_dpll(intel_crtc,
7053 &fp, &reduced_clock,
7054 has_reduced_clock ? &fp2 : NULL);
7055
7056 intel_crtc->config.dpll_hw_state.dpll = dpll;
7057 intel_crtc->config.dpll_hw_state.fp0 = fp;
7058 if (has_reduced_clock)
7059 intel_crtc->config.dpll_hw_state.fp1 = fp2;
7060 else
7061 intel_crtc->config.dpll_hw_state.fp1 = fp;
7062
7063 pll = intel_get_shared_dpll(intel_crtc);
7064 if (pll == NULL) {
7065 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7066 pipe_name(intel_crtc->pipe));
7067 return -EINVAL;
7068 }
7069 } else
7070 intel_put_shared_dpll(intel_crtc);
7071
7072 if (is_lvds && has_reduced_clock && i915.powersave)
7073 intel_crtc->lowfreq_avail = true;
7074 else
7075 intel_crtc->lowfreq_avail = false;
7076
7077 return 0;
7078 }
7079
7080 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7081 struct intel_link_m_n *m_n)
7082 {
7083 struct drm_device *dev = crtc->base.dev;
7084 struct drm_i915_private *dev_priv = dev->dev_private;
7085 enum pipe pipe = crtc->pipe;
7086
7087 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7088 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7089 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7090 & ~TU_SIZE_MASK;
7091 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7092 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7093 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7094 }
7095
7096 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7097 enum transcoder transcoder,
7098 struct intel_link_m_n *m_n)
7099 {
7100 struct drm_device *dev = crtc->base.dev;
7101 struct drm_i915_private *dev_priv = dev->dev_private;
7102 enum pipe pipe = crtc->pipe;
7103
7104 if (INTEL_INFO(dev)->gen >= 5) {
7105 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7106 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7107 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7108 & ~TU_SIZE_MASK;
7109 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7110 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7111 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7112 } else {
7113 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7114 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7115 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7116 & ~TU_SIZE_MASK;
7117 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7118 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7119 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7120 }
7121 }
7122
7123 void intel_dp_get_m_n(struct intel_crtc *crtc,
7124 struct intel_crtc_config *pipe_config)
7125 {
7126 if (crtc->config.has_pch_encoder)
7127 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7128 else
7129 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7130 &pipe_config->dp_m_n);
7131 }
7132
7133 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7134 struct intel_crtc_config *pipe_config)
7135 {
7136 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7137 &pipe_config->fdi_m_n);
7138 }
7139
7140 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7141 struct intel_crtc_config *pipe_config)
7142 {
7143 struct drm_device *dev = crtc->base.dev;
7144 struct drm_i915_private *dev_priv = dev->dev_private;
7145 uint32_t tmp;
7146
7147 tmp = I915_READ(PF_CTL(crtc->pipe));
7148
7149 if (tmp & PF_ENABLE) {
7150 pipe_config->pch_pfit.enabled = true;
7151 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7152 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7153
7154 /* We currently do not free assignements of panel fitters on
7155 * ivb/hsw (since we don't use the higher upscaling modes which
7156 * differentiates them) so just WARN about this case for now. */
7157 if (IS_GEN7(dev)) {
7158 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7159 PF_PIPE_SEL_IVB(crtc->pipe));
7160 }
7161 }
7162 }
7163
7164 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7165 struct intel_plane_config *plane_config)
7166 {
7167 struct drm_device *dev = crtc->base.dev;
7168 struct drm_i915_private *dev_priv = dev->dev_private;
7169 u32 val, base, offset;
7170 int pipe = crtc->pipe, plane = crtc->plane;
7171 int fourcc, pixel_format;
7172 int aligned_height;
7173
7174 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7175 if (!crtc->base.primary->fb) {
7176 DRM_DEBUG_KMS("failed to alloc fb\n");
7177 return;
7178 }
7179
7180 val = I915_READ(DSPCNTR(plane));
7181
7182 if (INTEL_INFO(dev)->gen >= 4)
7183 if (val & DISPPLANE_TILED)
7184 plane_config->tiled = true;
7185
7186 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7187 fourcc = intel_format_to_fourcc(pixel_format);
7188 crtc->base.primary->fb->pixel_format = fourcc;
7189 crtc->base.primary->fb->bits_per_pixel =
7190 drm_format_plane_cpp(fourcc, 0) * 8;
7191
7192 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7193 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7194 offset = I915_READ(DSPOFFSET(plane));
7195 } else {
7196 if (plane_config->tiled)
7197 offset = I915_READ(DSPTILEOFF(plane));
7198 else
7199 offset = I915_READ(DSPLINOFF(plane));
7200 }
7201 plane_config->base = base;
7202
7203 val = I915_READ(PIPESRC(pipe));
7204 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7205 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7206
7207 val = I915_READ(DSPSTRIDE(pipe));
7208 crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
7209
7210 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7211 plane_config->tiled);
7212
7213 plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
7214 aligned_height, PAGE_SIZE);
7215
7216 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7217 pipe, plane, crtc->base.primary->fb->width,
7218 crtc->base.primary->fb->height,
7219 crtc->base.primary->fb->bits_per_pixel, base,
7220 crtc->base.primary->fb->pitches[0],
7221 plane_config->size);
7222 }
7223
7224 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7225 struct intel_crtc_config *pipe_config)
7226 {
7227 struct drm_device *dev = crtc->base.dev;
7228 struct drm_i915_private *dev_priv = dev->dev_private;
7229 uint32_t tmp;
7230
7231 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7232 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7233
7234 tmp = I915_READ(PIPECONF(crtc->pipe));
7235 if (!(tmp & PIPECONF_ENABLE))
7236 return false;
7237
7238 switch (tmp & PIPECONF_BPC_MASK) {
7239 case PIPECONF_6BPC:
7240 pipe_config->pipe_bpp = 18;
7241 break;
7242 case PIPECONF_8BPC:
7243 pipe_config->pipe_bpp = 24;
7244 break;
7245 case PIPECONF_10BPC:
7246 pipe_config->pipe_bpp = 30;
7247 break;
7248 case PIPECONF_12BPC:
7249 pipe_config->pipe_bpp = 36;
7250 break;
7251 default:
7252 break;
7253 }
7254
7255 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7256 pipe_config->limited_color_range = true;
7257
7258 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7259 struct intel_shared_dpll *pll;
7260
7261 pipe_config->has_pch_encoder = true;
7262
7263 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7264 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7265 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7266
7267 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7268
7269 if (HAS_PCH_IBX(dev_priv->dev)) {
7270 pipe_config->shared_dpll =
7271 (enum intel_dpll_id) crtc->pipe;
7272 } else {
7273 tmp = I915_READ(PCH_DPLL_SEL);
7274 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7275 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7276 else
7277 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7278 }
7279
7280 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7281
7282 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7283 &pipe_config->dpll_hw_state));
7284
7285 tmp = pipe_config->dpll_hw_state.dpll;
7286 pipe_config->pixel_multiplier =
7287 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7288 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7289
7290 ironlake_pch_clock_get(crtc, pipe_config);
7291 } else {
7292 pipe_config->pixel_multiplier = 1;
7293 }
7294
7295 intel_get_pipe_timings(crtc, pipe_config);
7296
7297 ironlake_get_pfit_config(crtc, pipe_config);
7298
7299 return true;
7300 }
7301
7302 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7303 {
7304 struct drm_device *dev = dev_priv->dev;
7305 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
7306 struct intel_crtc *crtc;
7307
7308 for_each_intel_crtc(dev, crtc)
7309 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7310 pipe_name(crtc->pipe));
7311
7312 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7313 WARN(plls->spll_refcount, "SPLL enabled\n");
7314 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
7315 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
7316 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7317 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7318 "CPU PWM1 enabled\n");
7319 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7320 "CPU PWM2 enabled\n");
7321 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7322 "PCH PWM1 enabled\n");
7323 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7324 "Utility pin enabled\n");
7325 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7326
7327 /*
7328 * In theory we can still leave IRQs enabled, as long as only the HPD
7329 * interrupts remain enabled. We used to check for that, but since it's
7330 * gen-specific and since we only disable LCPLL after we fully disable
7331 * the interrupts, the check below should be enough.
7332 */
7333 WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n");
7334 }
7335
7336 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7337 {
7338 struct drm_device *dev = dev_priv->dev;
7339
7340 if (IS_HASWELL(dev)) {
7341 mutex_lock(&dev_priv->rps.hw_lock);
7342 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7343 val))
7344 DRM_ERROR("Failed to disable D_COMP\n");
7345 mutex_unlock(&dev_priv->rps.hw_lock);
7346 } else {
7347 I915_WRITE(D_COMP, val);
7348 }
7349 POSTING_READ(D_COMP);
7350 }
7351
7352 /*
7353 * This function implements pieces of two sequences from BSpec:
7354 * - Sequence for display software to disable LCPLL
7355 * - Sequence for display software to allow package C8+
7356 * The steps implemented here are just the steps that actually touch the LCPLL
7357 * register. Callers should take care of disabling all the display engine
7358 * functions, doing the mode unset, fixing interrupts, etc.
7359 */
7360 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7361 bool switch_to_fclk, bool allow_power_down)
7362 {
7363 uint32_t val;
7364
7365 assert_can_disable_lcpll(dev_priv);
7366
7367 val = I915_READ(LCPLL_CTL);
7368
7369 if (switch_to_fclk) {
7370 val |= LCPLL_CD_SOURCE_FCLK;
7371 I915_WRITE(LCPLL_CTL, val);
7372
7373 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7374 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7375 DRM_ERROR("Switching to FCLK failed\n");
7376
7377 val = I915_READ(LCPLL_CTL);
7378 }
7379
7380 val |= LCPLL_PLL_DISABLE;
7381 I915_WRITE(LCPLL_CTL, val);
7382 POSTING_READ(LCPLL_CTL);
7383
7384 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7385 DRM_ERROR("LCPLL still locked\n");
7386
7387 val = I915_READ(D_COMP);
7388 val |= D_COMP_COMP_DISABLE;
7389 hsw_write_dcomp(dev_priv, val);
7390 ndelay(100);
7391
7392 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
7393 DRM_ERROR("D_COMP RCOMP still in progress\n");
7394
7395 if (allow_power_down) {
7396 val = I915_READ(LCPLL_CTL);
7397 val |= LCPLL_POWER_DOWN_ALLOW;
7398 I915_WRITE(LCPLL_CTL, val);
7399 POSTING_READ(LCPLL_CTL);
7400 }
7401 }
7402
7403 /*
7404 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7405 * source.
7406 */
7407 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7408 {
7409 uint32_t val;
7410 unsigned long irqflags;
7411
7412 val = I915_READ(LCPLL_CTL);
7413
7414 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7415 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7416 return;
7417
7418 /*
7419 * Make sure we're not on PC8 state before disabling PC8, otherwise
7420 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7421 *
7422 * The other problem is that hsw_restore_lcpll() is called as part of
7423 * the runtime PM resume sequence, so we can't just call
7424 * gen6_gt_force_wake_get() because that function calls
7425 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7426 * while we are on the resume sequence. So to solve this problem we have
7427 * to call special forcewake code that doesn't touch runtime PM and
7428 * doesn't enable the forcewake delayed work.
7429 */
7430 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7431 if (dev_priv->uncore.forcewake_count++ == 0)
7432 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7433 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7434
7435 if (val & LCPLL_POWER_DOWN_ALLOW) {
7436 val &= ~LCPLL_POWER_DOWN_ALLOW;
7437 I915_WRITE(LCPLL_CTL, val);
7438 POSTING_READ(LCPLL_CTL);
7439 }
7440
7441 val = I915_READ(D_COMP);
7442 val |= D_COMP_COMP_FORCE;
7443 val &= ~D_COMP_COMP_DISABLE;
7444 hsw_write_dcomp(dev_priv, val);
7445
7446 val = I915_READ(LCPLL_CTL);
7447 val &= ~LCPLL_PLL_DISABLE;
7448 I915_WRITE(LCPLL_CTL, val);
7449
7450 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7451 DRM_ERROR("LCPLL not locked yet\n");
7452
7453 if (val & LCPLL_CD_SOURCE_FCLK) {
7454 val = I915_READ(LCPLL_CTL);
7455 val &= ~LCPLL_CD_SOURCE_FCLK;
7456 I915_WRITE(LCPLL_CTL, val);
7457
7458 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7459 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7460 DRM_ERROR("Switching back to LCPLL failed\n");
7461 }
7462
7463 /* See the big comment above. */
7464 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7465 if (--dev_priv->uncore.forcewake_count == 0)
7466 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7467 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7468 }
7469
7470 /*
7471 * Package states C8 and deeper are really deep PC states that can only be
7472 * reached when all the devices on the system allow it, so even if the graphics
7473 * device allows PC8+, it doesn't mean the system will actually get to these
7474 * states. Our driver only allows PC8+ when going into runtime PM.
7475 *
7476 * The requirements for PC8+ are that all the outputs are disabled, the power
7477 * well is disabled and most interrupts are disabled, and these are also
7478 * requirements for runtime PM. When these conditions are met, we manually do
7479 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7480 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7481 * hang the machine.
7482 *
7483 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7484 * the state of some registers, so when we come back from PC8+ we need to
7485 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7486 * need to take care of the registers kept by RC6. Notice that this happens even
7487 * if we don't put the device in PCI D3 state (which is what currently happens
7488 * because of the runtime PM support).
7489 *
7490 * For more, read "Display Sequences for Package C8" on the hardware
7491 * documentation.
7492 */
7493 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7494 {
7495 struct drm_device *dev = dev_priv->dev;
7496 uint32_t val;
7497
7498 DRM_DEBUG_KMS("Enabling package C8+\n");
7499
7500 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7501 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7502 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7503 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7504 }
7505
7506 lpt_disable_clkout_dp(dev);
7507 hsw_disable_lcpll(dev_priv, true, true);
7508 }
7509
7510 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7511 {
7512 struct drm_device *dev = dev_priv->dev;
7513 uint32_t val;
7514
7515 DRM_DEBUG_KMS("Disabling package C8+\n");
7516
7517 hsw_restore_lcpll(dev_priv);
7518 lpt_init_pch_refclk(dev);
7519
7520 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7521 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7522 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7523 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7524 }
7525
7526 intel_prepare_ddi(dev);
7527 }
7528
7529 static void snb_modeset_global_resources(struct drm_device *dev)
7530 {
7531 modeset_update_crtc_power_domains(dev);
7532 }
7533
7534 static void haswell_modeset_global_resources(struct drm_device *dev)
7535 {
7536 modeset_update_crtc_power_domains(dev);
7537 }
7538
7539 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7540 int x, int y,
7541 struct drm_framebuffer *fb)
7542 {
7543 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7544
7545 if (!intel_ddi_pll_select(intel_crtc))
7546 return -EINVAL;
7547 intel_ddi_pll_enable(intel_crtc);
7548
7549 intel_crtc->lowfreq_avail = false;
7550
7551 return 0;
7552 }
7553
7554 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7555 struct intel_crtc_config *pipe_config)
7556 {
7557 struct drm_device *dev = crtc->base.dev;
7558 struct drm_i915_private *dev_priv = dev->dev_private;
7559 enum intel_display_power_domain pfit_domain;
7560 uint32_t tmp;
7561
7562 if (!intel_display_power_enabled(dev_priv,
7563 POWER_DOMAIN_PIPE(crtc->pipe)))
7564 return false;
7565
7566 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7567 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7568
7569 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7570 if (tmp & TRANS_DDI_FUNC_ENABLE) {
7571 enum pipe trans_edp_pipe;
7572 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7573 default:
7574 WARN(1, "unknown pipe linked to edp transcoder\n");
7575 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7576 case TRANS_DDI_EDP_INPUT_A_ON:
7577 trans_edp_pipe = PIPE_A;
7578 break;
7579 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7580 trans_edp_pipe = PIPE_B;
7581 break;
7582 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7583 trans_edp_pipe = PIPE_C;
7584 break;
7585 }
7586
7587 if (trans_edp_pipe == crtc->pipe)
7588 pipe_config->cpu_transcoder = TRANSCODER_EDP;
7589 }
7590
7591 if (!intel_display_power_enabled(dev_priv,
7592 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7593 return false;
7594
7595 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7596 if (!(tmp & PIPECONF_ENABLE))
7597 return false;
7598
7599 /*
7600 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7601 * DDI E. So just check whether this pipe is wired to DDI E and whether
7602 * the PCH transcoder is on.
7603 */
7604 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7605 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
7606 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7607 pipe_config->has_pch_encoder = true;
7608
7609 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7610 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7611 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7612
7613 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7614 }
7615
7616 intel_get_pipe_timings(crtc, pipe_config);
7617
7618 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7619 if (intel_display_power_enabled(dev_priv, pfit_domain))
7620 ironlake_get_pfit_config(crtc, pipe_config);
7621
7622 if (IS_HASWELL(dev))
7623 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7624 (I915_READ(IPS_CTL) & IPS_ENABLE);
7625
7626 pipe_config->pixel_multiplier = 1;
7627
7628 return true;
7629 }
7630
7631 static struct {
7632 int clock;
7633 u32 config;
7634 } hdmi_audio_clock[] = {
7635 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7636 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7637 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7638 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7639 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7640 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7641 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7642 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7643 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7644 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7645 };
7646
7647 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7648 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7649 {
7650 int i;
7651
7652 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7653 if (mode->clock == hdmi_audio_clock[i].clock)
7654 break;
7655 }
7656
7657 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7658 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7659 i = 1;
7660 }
7661
7662 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7663 hdmi_audio_clock[i].clock,
7664 hdmi_audio_clock[i].config);
7665
7666 return hdmi_audio_clock[i].config;
7667 }
7668
7669 static bool intel_eld_uptodate(struct drm_connector *connector,
7670 int reg_eldv, uint32_t bits_eldv,
7671 int reg_elda, uint32_t bits_elda,
7672 int reg_edid)
7673 {
7674 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7675 uint8_t *eld = connector->eld;
7676 uint32_t i;
7677
7678 i = I915_READ(reg_eldv);
7679 i &= bits_eldv;
7680
7681 if (!eld[0])
7682 return !i;
7683
7684 if (!i)
7685 return false;
7686
7687 i = I915_READ(reg_elda);
7688 i &= ~bits_elda;
7689 I915_WRITE(reg_elda, i);
7690
7691 for (i = 0; i < eld[2]; i++)
7692 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7693 return false;
7694
7695 return true;
7696 }
7697
7698 static void g4x_write_eld(struct drm_connector *connector,
7699 struct drm_crtc *crtc,
7700 struct drm_display_mode *mode)
7701 {
7702 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7703 uint8_t *eld = connector->eld;
7704 uint32_t eldv;
7705 uint32_t len;
7706 uint32_t i;
7707
7708 i = I915_READ(G4X_AUD_VID_DID);
7709
7710 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7711 eldv = G4X_ELDV_DEVCL_DEVBLC;
7712 else
7713 eldv = G4X_ELDV_DEVCTG;
7714
7715 if (intel_eld_uptodate(connector,
7716 G4X_AUD_CNTL_ST, eldv,
7717 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7718 G4X_HDMIW_HDMIEDID))
7719 return;
7720
7721 i = I915_READ(G4X_AUD_CNTL_ST);
7722 i &= ~(eldv | G4X_ELD_ADDR);
7723 len = (i >> 9) & 0x1f; /* ELD buffer size */
7724 I915_WRITE(G4X_AUD_CNTL_ST, i);
7725
7726 if (!eld[0])
7727 return;
7728
7729 len = min_t(uint8_t, eld[2], len);
7730 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7731 for (i = 0; i < len; i++)
7732 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7733
7734 i = I915_READ(G4X_AUD_CNTL_ST);
7735 i |= eldv;
7736 I915_WRITE(G4X_AUD_CNTL_ST, i);
7737 }
7738
7739 static void haswell_write_eld(struct drm_connector *connector,
7740 struct drm_crtc *crtc,
7741 struct drm_display_mode *mode)
7742 {
7743 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7744 uint8_t *eld = connector->eld;
7745 uint32_t eldv;
7746 uint32_t i;
7747 int len;
7748 int pipe = to_intel_crtc(crtc)->pipe;
7749 int tmp;
7750
7751 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7752 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7753 int aud_config = HSW_AUD_CFG(pipe);
7754 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7755
7756 /* Audio output enable */
7757 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7758 tmp = I915_READ(aud_cntrl_st2);
7759 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7760 I915_WRITE(aud_cntrl_st2, tmp);
7761 POSTING_READ(aud_cntrl_st2);
7762
7763 assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
7764
7765 /* Set ELD valid state */
7766 tmp = I915_READ(aud_cntrl_st2);
7767 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7768 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7769 I915_WRITE(aud_cntrl_st2, tmp);
7770 tmp = I915_READ(aud_cntrl_st2);
7771 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7772
7773 /* Enable HDMI mode */
7774 tmp = I915_READ(aud_config);
7775 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7776 /* clear N_programing_enable and N_value_index */
7777 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7778 I915_WRITE(aud_config, tmp);
7779
7780 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7781
7782 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7783
7784 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7785 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7786 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7787 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7788 } else {
7789 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7790 }
7791
7792 if (intel_eld_uptodate(connector,
7793 aud_cntrl_st2, eldv,
7794 aud_cntl_st, IBX_ELD_ADDRESS,
7795 hdmiw_hdmiedid))
7796 return;
7797
7798 i = I915_READ(aud_cntrl_st2);
7799 i &= ~eldv;
7800 I915_WRITE(aud_cntrl_st2, i);
7801
7802 if (!eld[0])
7803 return;
7804
7805 i = I915_READ(aud_cntl_st);
7806 i &= ~IBX_ELD_ADDRESS;
7807 I915_WRITE(aud_cntl_st, i);
7808 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
7809 DRM_DEBUG_DRIVER("port num:%d\n", i);
7810
7811 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7812 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7813 for (i = 0; i < len; i++)
7814 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7815
7816 i = I915_READ(aud_cntrl_st2);
7817 i |= eldv;
7818 I915_WRITE(aud_cntrl_st2, i);
7819
7820 }
7821
7822 static void ironlake_write_eld(struct drm_connector *connector,
7823 struct drm_crtc *crtc,
7824 struct drm_display_mode *mode)
7825 {
7826 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7827 uint8_t *eld = connector->eld;
7828 uint32_t eldv;
7829 uint32_t i;
7830 int len;
7831 int hdmiw_hdmiedid;
7832 int aud_config;
7833 int aud_cntl_st;
7834 int aud_cntrl_st2;
7835 int pipe = to_intel_crtc(crtc)->pipe;
7836
7837 if (HAS_PCH_IBX(connector->dev)) {
7838 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7839 aud_config = IBX_AUD_CFG(pipe);
7840 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7841 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7842 } else if (IS_VALLEYVIEW(connector->dev)) {
7843 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7844 aud_config = VLV_AUD_CFG(pipe);
7845 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7846 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7847 } else {
7848 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7849 aud_config = CPT_AUD_CFG(pipe);
7850 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7851 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7852 }
7853
7854 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7855
7856 if (IS_VALLEYVIEW(connector->dev)) {
7857 struct intel_encoder *intel_encoder;
7858 struct intel_digital_port *intel_dig_port;
7859
7860 intel_encoder = intel_attached_encoder(connector);
7861 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7862 i = intel_dig_port->port;
7863 } else {
7864 i = I915_READ(aud_cntl_st);
7865 i = (i >> 29) & DIP_PORT_SEL_MASK;
7866 /* DIP_Port_Select, 0x1 = PortB */
7867 }
7868
7869 if (!i) {
7870 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7871 /* operate blindly on all ports */
7872 eldv = IBX_ELD_VALIDB;
7873 eldv |= IBX_ELD_VALIDB << 4;
7874 eldv |= IBX_ELD_VALIDB << 8;
7875 } else {
7876 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7877 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7878 }
7879
7880 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7881 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7882 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7883 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7884 } else {
7885 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7886 }
7887
7888 if (intel_eld_uptodate(connector,
7889 aud_cntrl_st2, eldv,
7890 aud_cntl_st, IBX_ELD_ADDRESS,
7891 hdmiw_hdmiedid))
7892 return;
7893
7894 i = I915_READ(aud_cntrl_st2);
7895 i &= ~eldv;
7896 I915_WRITE(aud_cntrl_st2, i);
7897
7898 if (!eld[0])
7899 return;
7900
7901 i = I915_READ(aud_cntl_st);
7902 i &= ~IBX_ELD_ADDRESS;
7903 I915_WRITE(aud_cntl_st, i);
7904
7905 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7906 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7907 for (i = 0; i < len; i++)
7908 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7909
7910 i = I915_READ(aud_cntrl_st2);
7911 i |= eldv;
7912 I915_WRITE(aud_cntrl_st2, i);
7913 }
7914
7915 void intel_write_eld(struct drm_encoder *encoder,
7916 struct drm_display_mode *mode)
7917 {
7918 struct drm_crtc *crtc = encoder->crtc;
7919 struct drm_connector *connector;
7920 struct drm_device *dev = encoder->dev;
7921 struct drm_i915_private *dev_priv = dev->dev_private;
7922
7923 connector = drm_select_eld(encoder, mode);
7924 if (!connector)
7925 return;
7926
7927 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7928 connector->base.id,
7929 connector->name,
7930 connector->encoder->base.id,
7931 connector->encoder->name);
7932
7933 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7934
7935 if (dev_priv->display.write_eld)
7936 dev_priv->display.write_eld(connector, crtc, mode);
7937 }
7938
7939 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7940 {
7941 struct drm_device *dev = crtc->dev;
7942 struct drm_i915_private *dev_priv = dev->dev_private;
7943 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7944 uint32_t cntl;
7945
7946 if (base != intel_crtc->cursor_base) {
7947 /* On these chipsets we can only modify the base whilst
7948 * the cursor is disabled.
7949 */
7950 if (intel_crtc->cursor_cntl) {
7951 I915_WRITE(_CURACNTR, 0);
7952 POSTING_READ(_CURACNTR);
7953 intel_crtc->cursor_cntl = 0;
7954 }
7955
7956 I915_WRITE(_CURABASE, base);
7957 POSTING_READ(_CURABASE);
7958 }
7959
7960 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7961 cntl = 0;
7962 if (base)
7963 cntl = (CURSOR_ENABLE |
7964 CURSOR_GAMMA_ENABLE |
7965 CURSOR_FORMAT_ARGB);
7966 if (intel_crtc->cursor_cntl != cntl) {
7967 I915_WRITE(_CURACNTR, cntl);
7968 POSTING_READ(_CURACNTR);
7969 intel_crtc->cursor_cntl = cntl;
7970 }
7971 }
7972
7973 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7974 {
7975 struct drm_device *dev = crtc->dev;
7976 struct drm_i915_private *dev_priv = dev->dev_private;
7977 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7978 int pipe = intel_crtc->pipe;
7979 uint32_t cntl;
7980
7981 cntl = 0;
7982 if (base) {
7983 cntl = MCURSOR_GAMMA_ENABLE;
7984 switch (intel_crtc->cursor_width) {
7985 case 64:
7986 cntl |= CURSOR_MODE_64_ARGB_AX;
7987 break;
7988 case 128:
7989 cntl |= CURSOR_MODE_128_ARGB_AX;
7990 break;
7991 case 256:
7992 cntl |= CURSOR_MODE_256_ARGB_AX;
7993 break;
7994 default:
7995 WARN_ON(1);
7996 return;
7997 }
7998 cntl |= pipe << 28; /* Connect to correct pipe */
7999 }
8000 if (intel_crtc->cursor_cntl != cntl) {
8001 I915_WRITE(CURCNTR(pipe), cntl);
8002 POSTING_READ(CURCNTR(pipe));
8003 intel_crtc->cursor_cntl = cntl;
8004 }
8005
8006 /* and commit changes on next vblank */
8007 I915_WRITE(CURBASE(pipe), base);
8008 POSTING_READ(CURBASE(pipe));
8009 }
8010
8011 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
8012 {
8013 struct drm_device *dev = crtc->dev;
8014 struct drm_i915_private *dev_priv = dev->dev_private;
8015 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8016 int pipe = intel_crtc->pipe;
8017 uint32_t cntl;
8018
8019 cntl = 0;
8020 if (base) {
8021 cntl = MCURSOR_GAMMA_ENABLE;
8022 switch (intel_crtc->cursor_width) {
8023 case 64:
8024 cntl |= CURSOR_MODE_64_ARGB_AX;
8025 break;
8026 case 128:
8027 cntl |= CURSOR_MODE_128_ARGB_AX;
8028 break;
8029 case 256:
8030 cntl |= CURSOR_MODE_256_ARGB_AX;
8031 break;
8032 default:
8033 WARN_ON(1);
8034 return;
8035 }
8036 }
8037 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8038 cntl |= CURSOR_PIPE_CSC_ENABLE;
8039
8040 if (intel_crtc->cursor_cntl != cntl) {
8041 I915_WRITE(CURCNTR(pipe), cntl);
8042 POSTING_READ(CURCNTR(pipe));
8043 intel_crtc->cursor_cntl = cntl;
8044 }
8045
8046 /* and commit changes on next vblank */
8047 I915_WRITE(CURBASE(pipe), base);
8048 POSTING_READ(CURBASE(pipe));
8049 }
8050
8051 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8052 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8053 bool on)
8054 {
8055 struct drm_device *dev = crtc->dev;
8056 struct drm_i915_private *dev_priv = dev->dev_private;
8057 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8058 int pipe = intel_crtc->pipe;
8059 int x = crtc->cursor_x;
8060 int y = crtc->cursor_y;
8061 u32 base = 0, pos = 0;
8062
8063 if (on)
8064 base = intel_crtc->cursor_addr;
8065
8066 if (x >= intel_crtc->config.pipe_src_w)
8067 base = 0;
8068
8069 if (y >= intel_crtc->config.pipe_src_h)
8070 base = 0;
8071
8072 if (x < 0) {
8073 if (x + intel_crtc->cursor_width <= 0)
8074 base = 0;
8075
8076 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8077 x = -x;
8078 }
8079 pos |= x << CURSOR_X_SHIFT;
8080
8081 if (y < 0) {
8082 if (y + intel_crtc->cursor_height <= 0)
8083 base = 0;
8084
8085 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8086 y = -y;
8087 }
8088 pos |= y << CURSOR_Y_SHIFT;
8089
8090 if (base == 0 && intel_crtc->cursor_base == 0)
8091 return;
8092
8093 I915_WRITE(CURPOS(pipe), pos);
8094
8095 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev))
8096 ivb_update_cursor(crtc, base);
8097 else if (IS_845G(dev) || IS_I865G(dev))
8098 i845_update_cursor(crtc, base);
8099 else
8100 i9xx_update_cursor(crtc, base);
8101 intel_crtc->cursor_base = base;
8102 }
8103
8104 /*
8105 * intel_crtc_cursor_set_obj - Set cursor to specified GEM object
8106 *
8107 * Note that the object's reference will be consumed if the update fails. If
8108 * the update succeeds, the reference of the old object (if any) will be
8109 * consumed.
8110 */
8111 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8112 struct drm_i915_gem_object *obj,
8113 uint32_t width, uint32_t height)
8114 {
8115 struct drm_device *dev = crtc->dev;
8116 struct drm_i915_private *dev_priv = dev->dev_private;
8117 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8118 enum pipe pipe = intel_crtc->pipe;
8119 unsigned old_width;
8120 uint32_t addr;
8121 int ret;
8122
8123 /* if we want to turn off the cursor ignore width and height */
8124 if (!obj) {
8125 DRM_DEBUG_KMS("cursor off\n");
8126 addr = 0;
8127 obj = NULL;
8128 mutex_lock(&dev->struct_mutex);
8129 goto finish;
8130 }
8131
8132 /* Check for which cursor types we support */
8133 if (!((width == 64 && height == 64) ||
8134 (width == 128 && height == 128 && !IS_GEN2(dev)) ||
8135 (width == 256 && height == 256 && !IS_GEN2(dev)))) {
8136 DRM_DEBUG("Cursor dimension not supported\n");
8137 return -EINVAL;
8138 }
8139
8140 if (obj->base.size < width * height * 4) {
8141 DRM_DEBUG_KMS("buffer is too small\n");
8142 ret = -ENOMEM;
8143 goto fail;
8144 }
8145
8146 /* we only need to pin inside GTT if cursor is non-phy */
8147 mutex_lock(&dev->struct_mutex);
8148 if (!INTEL_INFO(dev)->cursor_needs_physical) {
8149 unsigned alignment;
8150
8151 if (obj->tiling_mode) {
8152 DRM_DEBUG_KMS("cursor cannot be tiled\n");
8153 ret = -EINVAL;
8154 goto fail_locked;
8155 }
8156
8157 /* Note that the w/a also requires 2 PTE of padding following
8158 * the bo. We currently fill all unused PTE with the shadow
8159 * page and so we should always have valid PTE following the
8160 * cursor preventing the VT-d warning.
8161 */
8162 alignment = 0;
8163 if (need_vtd_wa(dev))
8164 alignment = 64*1024;
8165
8166 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8167 if (ret) {
8168 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8169 goto fail_locked;
8170 }
8171
8172 ret = i915_gem_object_put_fence(obj);
8173 if (ret) {
8174 DRM_DEBUG_KMS("failed to release fence for cursor");
8175 goto fail_unpin;
8176 }
8177
8178 addr = i915_gem_obj_ggtt_offset(obj);
8179 } else {
8180 int align = IS_I830(dev) ? 16 * 1024 : 256;
8181 ret = i915_gem_object_attach_phys(obj, align);
8182 if (ret) {
8183 DRM_DEBUG_KMS("failed to attach phys object\n");
8184 goto fail_locked;
8185 }
8186 addr = obj->phys_handle->busaddr;
8187 }
8188
8189 if (IS_GEN2(dev))
8190 I915_WRITE(CURSIZE, (height << 12) | width);
8191
8192 finish:
8193 if (intel_crtc->cursor_bo) {
8194 if (!INTEL_INFO(dev)->cursor_needs_physical)
8195 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8196 }
8197
8198 i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8199 INTEL_FRONTBUFFER_CURSOR(pipe));
8200 mutex_unlock(&dev->struct_mutex);
8201
8202 old_width = intel_crtc->cursor_width;
8203
8204 intel_crtc->cursor_addr = addr;
8205 intel_crtc->cursor_bo = obj;
8206 intel_crtc->cursor_width = width;
8207 intel_crtc->cursor_height = height;
8208
8209 if (intel_crtc->active) {
8210 if (old_width != width)
8211 intel_update_watermarks(crtc);
8212 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8213 }
8214
8215 return 0;
8216 fail_unpin:
8217 i915_gem_object_unpin_from_display_plane(obj);
8218 fail_locked:
8219 mutex_unlock(&dev->struct_mutex);
8220 fail:
8221 drm_gem_object_unreference_unlocked(&obj->base);
8222 return ret;
8223 }
8224
8225 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8226 u16 *blue, uint32_t start, uint32_t size)
8227 {
8228 int end = (start + size > 256) ? 256 : start + size, i;
8229 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8230
8231 for (i = start; i < end; i++) {
8232 intel_crtc->lut_r[i] = red[i] >> 8;
8233 intel_crtc->lut_g[i] = green[i] >> 8;
8234 intel_crtc->lut_b[i] = blue[i] >> 8;
8235 }
8236
8237 intel_crtc_load_lut(crtc);
8238 }
8239
8240 /* VESA 640x480x72Hz mode to set on the pipe */
8241 static struct drm_display_mode load_detect_mode = {
8242 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8243 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8244 };
8245
8246 struct drm_framebuffer *
8247 __intel_framebuffer_create(struct drm_device *dev,
8248 struct drm_mode_fb_cmd2 *mode_cmd,
8249 struct drm_i915_gem_object *obj)
8250 {
8251 struct intel_framebuffer *intel_fb;
8252 int ret;
8253
8254 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8255 if (!intel_fb) {
8256 drm_gem_object_unreference_unlocked(&obj->base);
8257 return ERR_PTR(-ENOMEM);
8258 }
8259
8260 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8261 if (ret)
8262 goto err;
8263
8264 return &intel_fb->base;
8265 err:
8266 drm_gem_object_unreference_unlocked(&obj->base);
8267 kfree(intel_fb);
8268
8269 return ERR_PTR(ret);
8270 }
8271
8272 static struct drm_framebuffer *
8273 intel_framebuffer_create(struct drm_device *dev,
8274 struct drm_mode_fb_cmd2 *mode_cmd,
8275 struct drm_i915_gem_object *obj)
8276 {
8277 struct drm_framebuffer *fb;
8278 int ret;
8279
8280 ret = i915_mutex_lock_interruptible(dev);
8281 if (ret)
8282 return ERR_PTR(ret);
8283 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8284 mutex_unlock(&dev->struct_mutex);
8285
8286 return fb;
8287 }
8288
8289 static u32
8290 intel_framebuffer_pitch_for_width(int width, int bpp)
8291 {
8292 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8293 return ALIGN(pitch, 64);
8294 }
8295
8296 static u32
8297 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8298 {
8299 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8300 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
8301 }
8302
8303 static struct drm_framebuffer *
8304 intel_framebuffer_create_for_mode(struct drm_device *dev,
8305 struct drm_display_mode *mode,
8306 int depth, int bpp)
8307 {
8308 struct drm_i915_gem_object *obj;
8309 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8310
8311 obj = i915_gem_alloc_object(dev,
8312 intel_framebuffer_size_for_mode(mode, bpp));
8313 if (obj == NULL)
8314 return ERR_PTR(-ENOMEM);
8315
8316 mode_cmd.width = mode->hdisplay;
8317 mode_cmd.height = mode->vdisplay;
8318 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8319 bpp);
8320 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8321
8322 return intel_framebuffer_create(dev, &mode_cmd, obj);
8323 }
8324
8325 static struct drm_framebuffer *
8326 mode_fits_in_fbdev(struct drm_device *dev,
8327 struct drm_display_mode *mode)
8328 {
8329 #ifdef CONFIG_DRM_I915_FBDEV
8330 struct drm_i915_private *dev_priv = dev->dev_private;
8331 struct drm_i915_gem_object *obj;
8332 struct drm_framebuffer *fb;
8333
8334 if (!dev_priv->fbdev)
8335 return NULL;
8336
8337 if (!dev_priv->fbdev->fb)
8338 return NULL;
8339
8340 obj = dev_priv->fbdev->fb->obj;
8341 BUG_ON(!obj);
8342
8343 fb = &dev_priv->fbdev->fb->base;
8344 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8345 fb->bits_per_pixel))
8346 return NULL;
8347
8348 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8349 return NULL;
8350
8351 return fb;
8352 #else
8353 return NULL;
8354 #endif
8355 }
8356
8357 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8358 struct drm_display_mode *mode,
8359 struct intel_load_detect_pipe *old,
8360 struct drm_modeset_acquire_ctx *ctx)
8361 {
8362 struct intel_crtc *intel_crtc;
8363 struct intel_encoder *intel_encoder =
8364 intel_attached_encoder(connector);
8365 struct drm_crtc *possible_crtc;
8366 struct drm_encoder *encoder = &intel_encoder->base;
8367 struct drm_crtc *crtc = NULL;
8368 struct drm_device *dev = encoder->dev;
8369 struct drm_framebuffer *fb;
8370 struct drm_mode_config *config = &dev->mode_config;
8371 int ret, i = -1;
8372
8373 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8374 connector->base.id, connector->name,
8375 encoder->base.id, encoder->name);
8376
8377 drm_modeset_acquire_init(ctx, 0);
8378
8379 retry:
8380 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8381 if (ret)
8382 goto fail_unlock;
8383
8384 /*
8385 * Algorithm gets a little messy:
8386 *
8387 * - if the connector already has an assigned crtc, use it (but make
8388 * sure it's on first)
8389 *
8390 * - try to find the first unused crtc that can drive this connector,
8391 * and use that if we find one
8392 */
8393
8394 /* See if we already have a CRTC for this connector */
8395 if (encoder->crtc) {
8396 crtc = encoder->crtc;
8397
8398 ret = drm_modeset_lock(&crtc->mutex, ctx);
8399 if (ret)
8400 goto fail_unlock;
8401
8402 old->dpms_mode = connector->dpms;
8403 old->load_detect_temp = false;
8404
8405 /* Make sure the crtc and connector are running */
8406 if (connector->dpms != DRM_MODE_DPMS_ON)
8407 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8408
8409 return true;
8410 }
8411
8412 /* Find an unused one (if possible) */
8413 for_each_crtc(dev, possible_crtc) {
8414 i++;
8415 if (!(encoder->possible_crtcs & (1 << i)))
8416 continue;
8417 if (!possible_crtc->enabled) {
8418 crtc = possible_crtc;
8419 break;
8420 }
8421 }
8422
8423 /*
8424 * If we didn't find an unused CRTC, don't use any.
8425 */
8426 if (!crtc) {
8427 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8428 goto fail_unlock;
8429 }
8430
8431 ret = drm_modeset_lock(&crtc->mutex, ctx);
8432 if (ret)
8433 goto fail_unlock;
8434 intel_encoder->new_crtc = to_intel_crtc(crtc);
8435 to_intel_connector(connector)->new_encoder = intel_encoder;
8436
8437 intel_crtc = to_intel_crtc(crtc);
8438 intel_crtc->new_enabled = true;
8439 intel_crtc->new_config = &intel_crtc->config;
8440 old->dpms_mode = connector->dpms;
8441 old->load_detect_temp = true;
8442 old->release_fb = NULL;
8443
8444 if (!mode)
8445 mode = &load_detect_mode;
8446
8447 /* We need a framebuffer large enough to accommodate all accesses
8448 * that the plane may generate whilst we perform load detection.
8449 * We can not rely on the fbcon either being present (we get called
8450 * during its initialisation to detect all boot displays, or it may
8451 * not even exist) or that it is large enough to satisfy the
8452 * requested mode.
8453 */
8454 fb = mode_fits_in_fbdev(dev, mode);
8455 if (fb == NULL) {
8456 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8457 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8458 old->release_fb = fb;
8459 } else
8460 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8461 if (IS_ERR(fb)) {
8462 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8463 goto fail;
8464 }
8465
8466 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8467 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8468 if (old->release_fb)
8469 old->release_fb->funcs->destroy(old->release_fb);
8470 goto fail;
8471 }
8472
8473 /* let the connector get through one full cycle before testing */
8474 intel_wait_for_vblank(dev, intel_crtc->pipe);
8475 return true;
8476
8477 fail:
8478 intel_crtc->new_enabled = crtc->enabled;
8479 if (intel_crtc->new_enabled)
8480 intel_crtc->new_config = &intel_crtc->config;
8481 else
8482 intel_crtc->new_config = NULL;
8483 fail_unlock:
8484 if (ret == -EDEADLK) {
8485 drm_modeset_backoff(ctx);
8486 goto retry;
8487 }
8488
8489 drm_modeset_drop_locks(ctx);
8490 drm_modeset_acquire_fini(ctx);
8491
8492 return false;
8493 }
8494
8495 void intel_release_load_detect_pipe(struct drm_connector *connector,
8496 struct intel_load_detect_pipe *old,
8497 struct drm_modeset_acquire_ctx *ctx)
8498 {
8499 struct intel_encoder *intel_encoder =
8500 intel_attached_encoder(connector);
8501 struct drm_encoder *encoder = &intel_encoder->base;
8502 struct drm_crtc *crtc = encoder->crtc;
8503 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8504
8505 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8506 connector->base.id, connector->name,
8507 encoder->base.id, encoder->name);
8508
8509 if (old->load_detect_temp) {
8510 to_intel_connector(connector)->new_encoder = NULL;
8511 intel_encoder->new_crtc = NULL;
8512 intel_crtc->new_enabled = false;
8513 intel_crtc->new_config = NULL;
8514 intel_set_mode(crtc, NULL, 0, 0, NULL);
8515
8516 if (old->release_fb) {
8517 drm_framebuffer_unregister_private(old->release_fb);
8518 drm_framebuffer_unreference(old->release_fb);
8519 }
8520
8521 goto unlock;
8522 return;
8523 }
8524
8525 /* Switch crtc and encoder back off if necessary */
8526 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8527 connector->funcs->dpms(connector, old->dpms_mode);
8528
8529 unlock:
8530 drm_modeset_drop_locks(ctx);
8531 drm_modeset_acquire_fini(ctx);
8532 }
8533
8534 static int i9xx_pll_refclk(struct drm_device *dev,
8535 const struct intel_crtc_config *pipe_config)
8536 {
8537 struct drm_i915_private *dev_priv = dev->dev_private;
8538 u32 dpll = pipe_config->dpll_hw_state.dpll;
8539
8540 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8541 return dev_priv->vbt.lvds_ssc_freq;
8542 else if (HAS_PCH_SPLIT(dev))
8543 return 120000;
8544 else if (!IS_GEN2(dev))
8545 return 96000;
8546 else
8547 return 48000;
8548 }
8549
8550 /* Returns the clock of the currently programmed mode of the given pipe. */
8551 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8552 struct intel_crtc_config *pipe_config)
8553 {
8554 struct drm_device *dev = crtc->base.dev;
8555 struct drm_i915_private *dev_priv = dev->dev_private;
8556 int pipe = pipe_config->cpu_transcoder;
8557 u32 dpll = pipe_config->dpll_hw_state.dpll;
8558 u32 fp;
8559 intel_clock_t clock;
8560 int refclk = i9xx_pll_refclk(dev, pipe_config);
8561
8562 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8563 fp = pipe_config->dpll_hw_state.fp0;
8564 else
8565 fp = pipe_config->dpll_hw_state.fp1;
8566
8567 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8568 if (IS_PINEVIEW(dev)) {
8569 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8570 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8571 } else {
8572 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8573 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8574 }
8575
8576 if (!IS_GEN2(dev)) {
8577 if (IS_PINEVIEW(dev))
8578 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8579 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8580 else
8581 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8582 DPLL_FPA01_P1_POST_DIV_SHIFT);
8583
8584 switch (dpll & DPLL_MODE_MASK) {
8585 case DPLLB_MODE_DAC_SERIAL:
8586 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8587 5 : 10;
8588 break;
8589 case DPLLB_MODE_LVDS:
8590 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8591 7 : 14;
8592 break;
8593 default:
8594 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8595 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8596 return;
8597 }
8598
8599 if (IS_PINEVIEW(dev))
8600 pineview_clock(refclk, &clock);
8601 else
8602 i9xx_clock(refclk, &clock);
8603 } else {
8604 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8605 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8606
8607 if (is_lvds) {
8608 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8609 DPLL_FPA01_P1_POST_DIV_SHIFT);
8610
8611 if (lvds & LVDS_CLKB_POWER_UP)
8612 clock.p2 = 7;
8613 else
8614 clock.p2 = 14;
8615 } else {
8616 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8617 clock.p1 = 2;
8618 else {
8619 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8620 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8621 }
8622 if (dpll & PLL_P2_DIVIDE_BY_4)
8623 clock.p2 = 4;
8624 else
8625 clock.p2 = 2;
8626 }
8627
8628 i9xx_clock(refclk, &clock);
8629 }
8630
8631 /*
8632 * This value includes pixel_multiplier. We will use
8633 * port_clock to compute adjusted_mode.crtc_clock in the
8634 * encoder's get_config() function.
8635 */
8636 pipe_config->port_clock = clock.dot;
8637 }
8638
8639 int intel_dotclock_calculate(int link_freq,
8640 const struct intel_link_m_n *m_n)
8641 {
8642 /*
8643 * The calculation for the data clock is:
8644 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8645 * But we want to avoid losing precison if possible, so:
8646 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8647 *
8648 * and the link clock is simpler:
8649 * link_clock = (m * link_clock) / n
8650 */
8651
8652 if (!m_n->link_n)
8653 return 0;
8654
8655 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8656 }
8657
8658 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8659 struct intel_crtc_config *pipe_config)
8660 {
8661 struct drm_device *dev = crtc->base.dev;
8662
8663 /* read out port_clock from the DPLL */
8664 i9xx_crtc_clock_get(crtc, pipe_config);
8665
8666 /*
8667 * This value does not include pixel_multiplier.
8668 * We will check that port_clock and adjusted_mode.crtc_clock
8669 * agree once we know their relationship in the encoder's
8670 * get_config() function.
8671 */
8672 pipe_config->adjusted_mode.crtc_clock =
8673 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8674 &pipe_config->fdi_m_n);
8675 }
8676
8677 /** Returns the currently programmed mode of the given pipe. */
8678 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8679 struct drm_crtc *crtc)
8680 {
8681 struct drm_i915_private *dev_priv = dev->dev_private;
8682 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8683 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8684 struct drm_display_mode *mode;
8685 struct intel_crtc_config pipe_config;
8686 int htot = I915_READ(HTOTAL(cpu_transcoder));
8687 int hsync = I915_READ(HSYNC(cpu_transcoder));
8688 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8689 int vsync = I915_READ(VSYNC(cpu_transcoder));
8690 enum pipe pipe = intel_crtc->pipe;
8691
8692 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8693 if (!mode)
8694 return NULL;
8695
8696 /*
8697 * Construct a pipe_config sufficient for getting the clock info
8698 * back out of crtc_clock_get.
8699 *
8700 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8701 * to use a real value here instead.
8702 */
8703 pipe_config.cpu_transcoder = (enum transcoder) pipe;
8704 pipe_config.pixel_multiplier = 1;
8705 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8706 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8707 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8708 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8709
8710 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8711 mode->hdisplay = (htot & 0xffff) + 1;
8712 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8713 mode->hsync_start = (hsync & 0xffff) + 1;
8714 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8715 mode->vdisplay = (vtot & 0xffff) + 1;
8716 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8717 mode->vsync_start = (vsync & 0xffff) + 1;
8718 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8719
8720 drm_mode_set_name(mode);
8721
8722 return mode;
8723 }
8724
8725 static void intel_increase_pllclock(struct drm_device *dev,
8726 enum pipe pipe)
8727 {
8728 struct drm_i915_private *dev_priv = dev->dev_private;
8729 int dpll_reg = DPLL(pipe);
8730 int dpll;
8731
8732 if (HAS_PCH_SPLIT(dev))
8733 return;
8734
8735 if (!dev_priv->lvds_downclock_avail)
8736 return;
8737
8738 dpll = I915_READ(dpll_reg);
8739 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8740 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8741
8742 assert_panel_unlocked(dev_priv, pipe);
8743
8744 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8745 I915_WRITE(dpll_reg, dpll);
8746 intel_wait_for_vblank(dev, pipe);
8747
8748 dpll = I915_READ(dpll_reg);
8749 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8750 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8751 }
8752 }
8753
8754 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8755 {
8756 struct drm_device *dev = crtc->dev;
8757 struct drm_i915_private *dev_priv = dev->dev_private;
8758 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8759
8760 if (HAS_PCH_SPLIT(dev))
8761 return;
8762
8763 if (!dev_priv->lvds_downclock_avail)
8764 return;
8765
8766 /*
8767 * Since this is called by a timer, we should never get here in
8768 * the manual case.
8769 */
8770 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8771 int pipe = intel_crtc->pipe;
8772 int dpll_reg = DPLL(pipe);
8773 int dpll;
8774
8775 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8776
8777 assert_panel_unlocked(dev_priv, pipe);
8778
8779 dpll = I915_READ(dpll_reg);
8780 dpll |= DISPLAY_RATE_SELECT_FPA1;
8781 I915_WRITE(dpll_reg, dpll);
8782 intel_wait_for_vblank(dev, pipe);
8783 dpll = I915_READ(dpll_reg);
8784 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8785 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8786 }
8787
8788 }
8789
8790 void intel_mark_busy(struct drm_device *dev)
8791 {
8792 struct drm_i915_private *dev_priv = dev->dev_private;
8793
8794 if (dev_priv->mm.busy)
8795 return;
8796
8797 intel_runtime_pm_get(dev_priv);
8798 i915_update_gfx_val(dev_priv);
8799 dev_priv->mm.busy = true;
8800 }
8801
8802 void intel_mark_idle(struct drm_device *dev)
8803 {
8804 struct drm_i915_private *dev_priv = dev->dev_private;
8805 struct drm_crtc *crtc;
8806
8807 if (!dev_priv->mm.busy)
8808 return;
8809
8810 dev_priv->mm.busy = false;
8811
8812 if (!i915.powersave)
8813 goto out;
8814
8815 for_each_crtc(dev, crtc) {
8816 if (!crtc->primary->fb)
8817 continue;
8818
8819 intel_decrease_pllclock(crtc);
8820 }
8821
8822 if (INTEL_INFO(dev)->gen >= 6)
8823 gen6_rps_idle(dev->dev_private);
8824
8825 out:
8826 intel_runtime_pm_put(dev_priv);
8827 }
8828
8829
8830 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
8831 struct intel_engine_cs *ring)
8832 {
8833 struct drm_device *dev = obj->base.dev;
8834 enum pipe pipe;
8835
8836 intel_edp_psr_exit(dev);
8837
8838 if (!i915.powersave)
8839 return;
8840
8841 for_each_pipe(pipe) {
8842 if (!(obj->frontbuffer_bits &
8843 INTEL_FRONTBUFFER_ALL_MASK(pipe)))
8844 continue;
8845
8846 intel_increase_pllclock(dev, pipe);
8847 if (ring && intel_fbc_enabled(dev))
8848 ring->fbc_dirty = true;
8849 }
8850 }
8851
8852 static void intel_crtc_destroy(struct drm_crtc *crtc)
8853 {
8854 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8855 struct drm_device *dev = crtc->dev;
8856 struct intel_unpin_work *work;
8857 unsigned long flags;
8858
8859 spin_lock_irqsave(&dev->event_lock, flags);
8860 work = intel_crtc->unpin_work;
8861 intel_crtc->unpin_work = NULL;
8862 spin_unlock_irqrestore(&dev->event_lock, flags);
8863
8864 if (work) {
8865 cancel_work_sync(&work->work);
8866 kfree(work);
8867 }
8868
8869 drm_crtc_cleanup(crtc);
8870
8871 kfree(intel_crtc);
8872 }
8873
8874 static void intel_unpin_work_fn(struct work_struct *__work)
8875 {
8876 struct intel_unpin_work *work =
8877 container_of(__work, struct intel_unpin_work, work);
8878 struct drm_device *dev = work->crtc->dev;
8879
8880 mutex_lock(&dev->struct_mutex);
8881 intel_unpin_fb_obj(work->old_fb_obj);
8882 drm_gem_object_unreference(&work->pending_flip_obj->base);
8883 drm_gem_object_unreference(&work->old_fb_obj->base);
8884
8885 intel_update_fbc(dev);
8886 mutex_unlock(&dev->struct_mutex);
8887
8888 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8889 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8890
8891 kfree(work);
8892 }
8893
8894 static void do_intel_finish_page_flip(struct drm_device *dev,
8895 struct drm_crtc *crtc)
8896 {
8897 struct drm_i915_private *dev_priv = dev->dev_private;
8898 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8899 struct intel_unpin_work *work;
8900 unsigned long flags;
8901
8902 /* Ignore early vblank irqs */
8903 if (intel_crtc == NULL)
8904 return;
8905
8906 spin_lock_irqsave(&dev->event_lock, flags);
8907 work = intel_crtc->unpin_work;
8908
8909 /* Ensure we don't miss a work->pending update ... */
8910 smp_rmb();
8911
8912 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8913 spin_unlock_irqrestore(&dev->event_lock, flags);
8914 return;
8915 }
8916
8917 /* and that the unpin work is consistent wrt ->pending. */
8918 smp_rmb();
8919
8920 intel_crtc->unpin_work = NULL;
8921
8922 if (work->event)
8923 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
8924
8925 drm_crtc_vblank_put(crtc);
8926
8927 spin_unlock_irqrestore(&dev->event_lock, flags);
8928
8929 wake_up_all(&dev_priv->pending_flip_queue);
8930
8931 queue_work(dev_priv->wq, &work->work);
8932
8933 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
8934 }
8935
8936 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8937 {
8938 struct drm_i915_private *dev_priv = dev->dev_private;
8939 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8940
8941 do_intel_finish_page_flip(dev, crtc);
8942 }
8943
8944 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8945 {
8946 struct drm_i915_private *dev_priv = dev->dev_private;
8947 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8948
8949 do_intel_finish_page_flip(dev, crtc);
8950 }
8951
8952 /* Is 'a' after or equal to 'b'? */
8953 static bool g4x_flip_count_after_eq(u32 a, u32 b)
8954 {
8955 return !((a - b) & 0x80000000);
8956 }
8957
8958 static bool page_flip_finished(struct intel_crtc *crtc)
8959 {
8960 struct drm_device *dev = crtc->base.dev;
8961 struct drm_i915_private *dev_priv = dev->dev_private;
8962
8963 /*
8964 * The relevant registers doen't exist on pre-ctg.
8965 * As the flip done interrupt doesn't trigger for mmio
8966 * flips on gmch platforms, a flip count check isn't
8967 * really needed there. But since ctg has the registers,
8968 * include it in the check anyway.
8969 */
8970 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
8971 return true;
8972
8973 /*
8974 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
8975 * used the same base address. In that case the mmio flip might
8976 * have completed, but the CS hasn't even executed the flip yet.
8977 *
8978 * A flip count check isn't enough as the CS might have updated
8979 * the base address just after start of vblank, but before we
8980 * managed to process the interrupt. This means we'd complete the
8981 * CS flip too soon.
8982 *
8983 * Combining both checks should get us a good enough result. It may
8984 * still happen that the CS flip has been executed, but has not
8985 * yet actually completed. But in case the base address is the same
8986 * anyway, we don't really care.
8987 */
8988 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
8989 crtc->unpin_work->gtt_offset &&
8990 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
8991 crtc->unpin_work->flip_count);
8992 }
8993
8994 void intel_prepare_page_flip(struct drm_device *dev, int plane)
8995 {
8996 struct drm_i915_private *dev_priv = dev->dev_private;
8997 struct intel_crtc *intel_crtc =
8998 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8999 unsigned long flags;
9000
9001 /* NB: An MMIO update of the plane base pointer will also
9002 * generate a page-flip completion irq, i.e. every modeset
9003 * is also accompanied by a spurious intel_prepare_page_flip().
9004 */
9005 spin_lock_irqsave(&dev->event_lock, flags);
9006 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9007 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9008 spin_unlock_irqrestore(&dev->event_lock, flags);
9009 }
9010
9011 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9012 {
9013 /* Ensure that the work item is consistent when activating it ... */
9014 smp_wmb();
9015 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9016 /* and that it is marked active as soon as the irq could fire. */
9017 smp_wmb();
9018 }
9019
9020 static int intel_gen2_queue_flip(struct drm_device *dev,
9021 struct drm_crtc *crtc,
9022 struct drm_framebuffer *fb,
9023 struct drm_i915_gem_object *obj,
9024 struct intel_engine_cs *ring,
9025 uint32_t flags)
9026 {
9027 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9028 u32 flip_mask;
9029 int ret;
9030
9031 ret = intel_ring_begin(ring, 6);
9032 if (ret)
9033 return ret;
9034
9035 /* Can't queue multiple flips, so wait for the previous
9036 * one to finish before executing the next.
9037 */
9038 if (intel_crtc->plane)
9039 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9040 else
9041 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9042 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9043 intel_ring_emit(ring, MI_NOOP);
9044 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9045 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9046 intel_ring_emit(ring, fb->pitches[0]);
9047 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9048 intel_ring_emit(ring, 0); /* aux display base address, unused */
9049
9050 intel_mark_page_flip_active(intel_crtc);
9051 __intel_ring_advance(ring);
9052 return 0;
9053 }
9054
9055 static int intel_gen3_queue_flip(struct drm_device *dev,
9056 struct drm_crtc *crtc,
9057 struct drm_framebuffer *fb,
9058 struct drm_i915_gem_object *obj,
9059 struct intel_engine_cs *ring,
9060 uint32_t flags)
9061 {
9062 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9063 u32 flip_mask;
9064 int ret;
9065
9066 ret = intel_ring_begin(ring, 6);
9067 if (ret)
9068 return ret;
9069
9070 if (intel_crtc->plane)
9071 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9072 else
9073 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9074 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9075 intel_ring_emit(ring, MI_NOOP);
9076 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9077 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9078 intel_ring_emit(ring, fb->pitches[0]);
9079 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9080 intel_ring_emit(ring, MI_NOOP);
9081
9082 intel_mark_page_flip_active(intel_crtc);
9083 __intel_ring_advance(ring);
9084 return 0;
9085 }
9086
9087 static int intel_gen4_queue_flip(struct drm_device *dev,
9088 struct drm_crtc *crtc,
9089 struct drm_framebuffer *fb,
9090 struct drm_i915_gem_object *obj,
9091 struct intel_engine_cs *ring,
9092 uint32_t flags)
9093 {
9094 struct drm_i915_private *dev_priv = dev->dev_private;
9095 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9096 uint32_t pf, pipesrc;
9097 int ret;
9098
9099 ret = intel_ring_begin(ring, 4);
9100 if (ret)
9101 return ret;
9102
9103 /* i965+ uses the linear or tiled offsets from the
9104 * Display Registers (which do not change across a page-flip)
9105 * so we need only reprogram the base address.
9106 */
9107 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9108 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9109 intel_ring_emit(ring, fb->pitches[0]);
9110 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9111 obj->tiling_mode);
9112
9113 /* XXX Enabling the panel-fitter across page-flip is so far
9114 * untested on non-native modes, so ignore it for now.
9115 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9116 */
9117 pf = 0;
9118 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9119 intel_ring_emit(ring, pf | pipesrc);
9120
9121 intel_mark_page_flip_active(intel_crtc);
9122 __intel_ring_advance(ring);
9123 return 0;
9124 }
9125
9126 static int intel_gen6_queue_flip(struct drm_device *dev,
9127 struct drm_crtc *crtc,
9128 struct drm_framebuffer *fb,
9129 struct drm_i915_gem_object *obj,
9130 struct intel_engine_cs *ring,
9131 uint32_t flags)
9132 {
9133 struct drm_i915_private *dev_priv = dev->dev_private;
9134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9135 uint32_t pf, pipesrc;
9136 int ret;
9137
9138 ret = intel_ring_begin(ring, 4);
9139 if (ret)
9140 return ret;
9141
9142 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9143 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9144 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9145 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9146
9147 /* Contrary to the suggestions in the documentation,
9148 * "Enable Panel Fitter" does not seem to be required when page
9149 * flipping with a non-native mode, and worse causes a normal
9150 * modeset to fail.
9151 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9152 */
9153 pf = 0;
9154 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9155 intel_ring_emit(ring, pf | pipesrc);
9156
9157 intel_mark_page_flip_active(intel_crtc);
9158 __intel_ring_advance(ring);
9159 return 0;
9160 }
9161
9162 static int intel_gen7_queue_flip(struct drm_device *dev,
9163 struct drm_crtc *crtc,
9164 struct drm_framebuffer *fb,
9165 struct drm_i915_gem_object *obj,
9166 struct intel_engine_cs *ring,
9167 uint32_t flags)
9168 {
9169 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9170 uint32_t plane_bit = 0;
9171 int len, ret;
9172
9173 switch (intel_crtc->plane) {
9174 case PLANE_A:
9175 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9176 break;
9177 case PLANE_B:
9178 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9179 break;
9180 case PLANE_C:
9181 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9182 break;
9183 default:
9184 WARN_ONCE(1, "unknown plane in flip command\n");
9185 return -ENODEV;
9186 }
9187
9188 len = 4;
9189 if (ring->id == RCS) {
9190 len += 6;
9191 /*
9192 * On Gen 8, SRM is now taking an extra dword to accommodate
9193 * 48bits addresses, and we need a NOOP for the batch size to
9194 * stay even.
9195 */
9196 if (IS_GEN8(dev))
9197 len += 2;
9198 }
9199
9200 /*
9201 * BSpec MI_DISPLAY_FLIP for IVB:
9202 * "The full packet must be contained within the same cache line."
9203 *
9204 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9205 * cacheline, if we ever start emitting more commands before
9206 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9207 * then do the cacheline alignment, and finally emit the
9208 * MI_DISPLAY_FLIP.
9209 */
9210 ret = intel_ring_cacheline_align(ring);
9211 if (ret)
9212 return ret;
9213
9214 ret = intel_ring_begin(ring, len);
9215 if (ret)
9216 return ret;
9217
9218 /* Unmask the flip-done completion message. Note that the bspec says that
9219 * we should do this for both the BCS and RCS, and that we must not unmask
9220 * more than one flip event at any time (or ensure that one flip message
9221 * can be sent by waiting for flip-done prior to queueing new flips).
9222 * Experimentation says that BCS works despite DERRMR masking all
9223 * flip-done completion events and that unmasking all planes at once
9224 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9225 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9226 */
9227 if (ring->id == RCS) {
9228 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9229 intel_ring_emit(ring, DERRMR);
9230 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9231 DERRMR_PIPEB_PRI_FLIP_DONE |
9232 DERRMR_PIPEC_PRI_FLIP_DONE));
9233 if (IS_GEN8(dev))
9234 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9235 MI_SRM_LRM_GLOBAL_GTT);
9236 else
9237 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9238 MI_SRM_LRM_GLOBAL_GTT);
9239 intel_ring_emit(ring, DERRMR);
9240 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9241 if (IS_GEN8(dev)) {
9242 intel_ring_emit(ring, 0);
9243 intel_ring_emit(ring, MI_NOOP);
9244 }
9245 }
9246
9247 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9248 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9249 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9250 intel_ring_emit(ring, (MI_NOOP));
9251
9252 intel_mark_page_flip_active(intel_crtc);
9253 __intel_ring_advance(ring);
9254 return 0;
9255 }
9256
9257 static bool use_mmio_flip(struct intel_engine_cs *ring,
9258 struct drm_i915_gem_object *obj)
9259 {
9260 /*
9261 * This is not being used for older platforms, because
9262 * non-availability of flip done interrupt forces us to use
9263 * CS flips. Older platforms derive flip done using some clever
9264 * tricks involving the flip_pending status bits and vblank irqs.
9265 * So using MMIO flips there would disrupt this mechanism.
9266 */
9267
9268 if (INTEL_INFO(ring->dev)->gen < 5)
9269 return false;
9270
9271 if (i915.use_mmio_flip < 0)
9272 return false;
9273 else if (i915.use_mmio_flip > 0)
9274 return true;
9275 else
9276 return ring != obj->ring;
9277 }
9278
9279 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9280 {
9281 struct drm_device *dev = intel_crtc->base.dev;
9282 struct drm_i915_private *dev_priv = dev->dev_private;
9283 struct intel_framebuffer *intel_fb =
9284 to_intel_framebuffer(intel_crtc->base.primary->fb);
9285 struct drm_i915_gem_object *obj = intel_fb->obj;
9286 u32 dspcntr;
9287 u32 reg;
9288
9289 intel_mark_page_flip_active(intel_crtc);
9290
9291 reg = DSPCNTR(intel_crtc->plane);
9292 dspcntr = I915_READ(reg);
9293
9294 if (INTEL_INFO(dev)->gen >= 4) {
9295 if (obj->tiling_mode != I915_TILING_NONE)
9296 dspcntr |= DISPPLANE_TILED;
9297 else
9298 dspcntr &= ~DISPPLANE_TILED;
9299 }
9300 I915_WRITE(reg, dspcntr);
9301
9302 I915_WRITE(DSPSURF(intel_crtc->plane),
9303 intel_crtc->unpin_work->gtt_offset);
9304 POSTING_READ(DSPSURF(intel_crtc->plane));
9305 }
9306
9307 static int intel_postpone_flip(struct drm_i915_gem_object *obj)
9308 {
9309 struct intel_engine_cs *ring;
9310 int ret;
9311
9312 lockdep_assert_held(&obj->base.dev->struct_mutex);
9313
9314 if (!obj->last_write_seqno)
9315 return 0;
9316
9317 ring = obj->ring;
9318
9319 if (i915_seqno_passed(ring->get_seqno(ring, true),
9320 obj->last_write_seqno))
9321 return 0;
9322
9323 ret = i915_gem_check_olr(ring, obj->last_write_seqno);
9324 if (ret)
9325 return ret;
9326
9327 if (WARN_ON(!ring->irq_get(ring)))
9328 return 0;
9329
9330 return 1;
9331 }
9332
9333 void intel_notify_mmio_flip(struct intel_engine_cs *ring)
9334 {
9335 struct drm_i915_private *dev_priv = to_i915(ring->dev);
9336 struct intel_crtc *intel_crtc;
9337 unsigned long irq_flags;
9338 u32 seqno;
9339
9340 seqno = ring->get_seqno(ring, false);
9341
9342 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9343 for_each_intel_crtc(ring->dev, intel_crtc) {
9344 struct intel_mmio_flip *mmio_flip;
9345
9346 mmio_flip = &intel_crtc->mmio_flip;
9347 if (mmio_flip->seqno == 0)
9348 continue;
9349
9350 if (ring->id != mmio_flip->ring_id)
9351 continue;
9352
9353 if (i915_seqno_passed(seqno, mmio_flip->seqno)) {
9354 intel_do_mmio_flip(intel_crtc);
9355 mmio_flip->seqno = 0;
9356 ring->irq_put(ring);
9357 }
9358 }
9359 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9360 }
9361
9362 static int intel_queue_mmio_flip(struct drm_device *dev,
9363 struct drm_crtc *crtc,
9364 struct drm_framebuffer *fb,
9365 struct drm_i915_gem_object *obj,
9366 struct intel_engine_cs *ring,
9367 uint32_t flags)
9368 {
9369 struct drm_i915_private *dev_priv = dev->dev_private;
9370 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9371 unsigned long irq_flags;
9372 int ret;
9373
9374 if (WARN_ON(intel_crtc->mmio_flip.seqno))
9375 return -EBUSY;
9376
9377 ret = intel_postpone_flip(obj);
9378 if (ret < 0)
9379 return ret;
9380 if (ret == 0) {
9381 intel_do_mmio_flip(intel_crtc);
9382 return 0;
9383 }
9384
9385 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9386 intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9387 intel_crtc->mmio_flip.ring_id = obj->ring->id;
9388 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9389
9390 /*
9391 * Double check to catch cases where irq fired before
9392 * mmio flip data was ready
9393 */
9394 intel_notify_mmio_flip(obj->ring);
9395 return 0;
9396 }
9397
9398 static int intel_default_queue_flip(struct drm_device *dev,
9399 struct drm_crtc *crtc,
9400 struct drm_framebuffer *fb,
9401 struct drm_i915_gem_object *obj,
9402 struct intel_engine_cs *ring,
9403 uint32_t flags)
9404 {
9405 return -ENODEV;
9406 }
9407
9408 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9409 struct drm_framebuffer *fb,
9410 struct drm_pending_vblank_event *event,
9411 uint32_t page_flip_flags)
9412 {
9413 struct drm_device *dev = crtc->dev;
9414 struct drm_i915_private *dev_priv = dev->dev_private;
9415 struct drm_framebuffer *old_fb = crtc->primary->fb;
9416 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
9417 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9418 enum pipe pipe = intel_crtc->pipe;
9419 struct intel_unpin_work *work;
9420 struct intel_engine_cs *ring;
9421 unsigned long flags;
9422 int ret;
9423
9424 /* Can't change pixel format via MI display flips. */
9425 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9426 return -EINVAL;
9427
9428 /*
9429 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9430 * Note that pitch changes could also affect these register.
9431 */
9432 if (INTEL_INFO(dev)->gen > 3 &&
9433 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9434 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9435 return -EINVAL;
9436
9437 if (i915_terminally_wedged(&dev_priv->gpu_error))
9438 goto out_hang;
9439
9440 work = kzalloc(sizeof(*work), GFP_KERNEL);
9441 if (work == NULL)
9442 return -ENOMEM;
9443
9444 /* Exit PSR early in page flip */
9445 intel_edp_psr_exit(dev);
9446
9447 work->event = event;
9448 work->crtc = crtc;
9449 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
9450 INIT_WORK(&work->work, intel_unpin_work_fn);
9451
9452 ret = drm_crtc_vblank_get(crtc);
9453 if (ret)
9454 goto free_work;
9455
9456 /* We borrow the event spin lock for protecting unpin_work */
9457 spin_lock_irqsave(&dev->event_lock, flags);
9458 if (intel_crtc->unpin_work) {
9459 spin_unlock_irqrestore(&dev->event_lock, flags);
9460 kfree(work);
9461 drm_crtc_vblank_put(crtc);
9462
9463 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9464 return -EBUSY;
9465 }
9466 intel_crtc->unpin_work = work;
9467 spin_unlock_irqrestore(&dev->event_lock, flags);
9468
9469 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9470 flush_workqueue(dev_priv->wq);
9471
9472 ret = i915_mutex_lock_interruptible(dev);
9473 if (ret)
9474 goto cleanup;
9475
9476 /* Reference the objects for the scheduled work. */
9477 drm_gem_object_reference(&work->old_fb_obj->base);
9478 drm_gem_object_reference(&obj->base);
9479
9480 crtc->primary->fb = fb;
9481
9482 work->pending_flip_obj = obj;
9483
9484 work->enable_stall_check = true;
9485
9486 atomic_inc(&intel_crtc->unpin_work_count);
9487 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9488
9489 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9490 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9491
9492 if (IS_VALLEYVIEW(dev)) {
9493 ring = &dev_priv->ring[BCS];
9494 } else if (INTEL_INFO(dev)->gen >= 7) {
9495 ring = obj->ring;
9496 if (ring == NULL || ring->id != RCS)
9497 ring = &dev_priv->ring[BCS];
9498 } else {
9499 ring = &dev_priv->ring[RCS];
9500 }
9501
9502 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9503 if (ret)
9504 goto cleanup_pending;
9505
9506 work->gtt_offset =
9507 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9508
9509 if (use_mmio_flip(ring, obj))
9510 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9511 page_flip_flags);
9512 else
9513 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9514 page_flip_flags);
9515 if (ret)
9516 goto cleanup_unpin;
9517
9518 i915_gem_track_fb(work->old_fb_obj, obj,
9519 INTEL_FRONTBUFFER_PRIMARY(pipe));
9520
9521 intel_disable_fbc(dev);
9522 intel_mark_fb_busy(obj, NULL);
9523 mutex_unlock(&dev->struct_mutex);
9524
9525 trace_i915_flip_request(intel_crtc->plane, obj);
9526
9527 return 0;
9528
9529 cleanup_unpin:
9530 intel_unpin_fb_obj(obj);
9531 cleanup_pending:
9532 atomic_dec(&intel_crtc->unpin_work_count);
9533 crtc->primary->fb = old_fb;
9534 drm_gem_object_unreference(&work->old_fb_obj->base);
9535 drm_gem_object_unreference(&obj->base);
9536 mutex_unlock(&dev->struct_mutex);
9537
9538 cleanup:
9539 spin_lock_irqsave(&dev->event_lock, flags);
9540 intel_crtc->unpin_work = NULL;
9541 spin_unlock_irqrestore(&dev->event_lock, flags);
9542
9543 drm_crtc_vblank_put(crtc);
9544 free_work:
9545 kfree(work);
9546
9547 if (ret == -EIO) {
9548 out_hang:
9549 intel_crtc_wait_for_pending_flips(crtc);
9550 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9551 if (ret == 0 && event)
9552 drm_send_vblank_event(dev, pipe, event);
9553 }
9554 return ret;
9555 }
9556
9557 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9558 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9559 .load_lut = intel_crtc_load_lut,
9560 };
9561
9562 /**
9563 * intel_modeset_update_staged_output_state
9564 *
9565 * Updates the staged output configuration state, e.g. after we've read out the
9566 * current hw state.
9567 */
9568 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9569 {
9570 struct intel_crtc *crtc;
9571 struct intel_encoder *encoder;
9572 struct intel_connector *connector;
9573
9574 list_for_each_entry(connector, &dev->mode_config.connector_list,
9575 base.head) {
9576 connector->new_encoder =
9577 to_intel_encoder(connector->base.encoder);
9578 }
9579
9580 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9581 base.head) {
9582 encoder->new_crtc =
9583 to_intel_crtc(encoder->base.crtc);
9584 }
9585
9586 for_each_intel_crtc(dev, crtc) {
9587 crtc->new_enabled = crtc->base.enabled;
9588
9589 if (crtc->new_enabled)
9590 crtc->new_config = &crtc->config;
9591 else
9592 crtc->new_config = NULL;
9593 }
9594 }
9595
9596 /**
9597 * intel_modeset_commit_output_state
9598 *
9599 * This function copies the stage display pipe configuration to the real one.
9600 */
9601 static void intel_modeset_commit_output_state(struct drm_device *dev)
9602 {
9603 struct intel_crtc *crtc;
9604 struct intel_encoder *encoder;
9605 struct intel_connector *connector;
9606
9607 list_for_each_entry(connector, &dev->mode_config.connector_list,
9608 base.head) {
9609 connector->base.encoder = &connector->new_encoder->base;
9610 }
9611
9612 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9613 base.head) {
9614 encoder->base.crtc = &encoder->new_crtc->base;
9615 }
9616
9617 for_each_intel_crtc(dev, crtc) {
9618 crtc->base.enabled = crtc->new_enabled;
9619 }
9620 }
9621
9622 static void
9623 connected_sink_compute_bpp(struct intel_connector *connector,
9624 struct intel_crtc_config *pipe_config)
9625 {
9626 int bpp = pipe_config->pipe_bpp;
9627
9628 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9629 connector->base.base.id,
9630 connector->base.name);
9631
9632 /* Don't use an invalid EDID bpc value */
9633 if (connector->base.display_info.bpc &&
9634 connector->base.display_info.bpc * 3 < bpp) {
9635 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9636 bpp, connector->base.display_info.bpc*3);
9637 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9638 }
9639
9640 /* Clamp bpp to 8 on screens without EDID 1.4 */
9641 if (connector->base.display_info.bpc == 0 && bpp > 24) {
9642 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9643 bpp);
9644 pipe_config->pipe_bpp = 24;
9645 }
9646 }
9647
9648 static int
9649 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9650 struct drm_framebuffer *fb,
9651 struct intel_crtc_config *pipe_config)
9652 {
9653 struct drm_device *dev = crtc->base.dev;
9654 struct intel_connector *connector;
9655 int bpp;
9656
9657 switch (fb->pixel_format) {
9658 case DRM_FORMAT_C8:
9659 bpp = 8*3; /* since we go through a colormap */
9660 break;
9661 case DRM_FORMAT_XRGB1555:
9662 case DRM_FORMAT_ARGB1555:
9663 /* checked in intel_framebuffer_init already */
9664 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9665 return -EINVAL;
9666 case DRM_FORMAT_RGB565:
9667 bpp = 6*3; /* min is 18bpp */
9668 break;
9669 case DRM_FORMAT_XBGR8888:
9670 case DRM_FORMAT_ABGR8888:
9671 /* checked in intel_framebuffer_init already */
9672 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9673 return -EINVAL;
9674 case DRM_FORMAT_XRGB8888:
9675 case DRM_FORMAT_ARGB8888:
9676 bpp = 8*3;
9677 break;
9678 case DRM_FORMAT_XRGB2101010:
9679 case DRM_FORMAT_ARGB2101010:
9680 case DRM_FORMAT_XBGR2101010:
9681 case DRM_FORMAT_ABGR2101010:
9682 /* checked in intel_framebuffer_init already */
9683 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9684 return -EINVAL;
9685 bpp = 10*3;
9686 break;
9687 /* TODO: gen4+ supports 16 bpc floating point, too. */
9688 default:
9689 DRM_DEBUG_KMS("unsupported depth\n");
9690 return -EINVAL;
9691 }
9692
9693 pipe_config->pipe_bpp = bpp;
9694
9695 /* Clamp display bpp to EDID value */
9696 list_for_each_entry(connector, &dev->mode_config.connector_list,
9697 base.head) {
9698 if (!connector->new_encoder ||
9699 connector->new_encoder->new_crtc != crtc)
9700 continue;
9701
9702 connected_sink_compute_bpp(connector, pipe_config);
9703 }
9704
9705 return bpp;
9706 }
9707
9708 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9709 {
9710 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9711 "type: 0x%x flags: 0x%x\n",
9712 mode->crtc_clock,
9713 mode->crtc_hdisplay, mode->crtc_hsync_start,
9714 mode->crtc_hsync_end, mode->crtc_htotal,
9715 mode->crtc_vdisplay, mode->crtc_vsync_start,
9716 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9717 }
9718
9719 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9720 struct intel_crtc_config *pipe_config,
9721 const char *context)
9722 {
9723 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9724 context, pipe_name(crtc->pipe));
9725
9726 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9727 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9728 pipe_config->pipe_bpp, pipe_config->dither);
9729 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9730 pipe_config->has_pch_encoder,
9731 pipe_config->fdi_lanes,
9732 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9733 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9734 pipe_config->fdi_m_n.tu);
9735 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9736 pipe_config->has_dp_encoder,
9737 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9738 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9739 pipe_config->dp_m_n.tu);
9740 DRM_DEBUG_KMS("requested mode:\n");
9741 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9742 DRM_DEBUG_KMS("adjusted mode:\n");
9743 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9744 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9745 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9746 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9747 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9748 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9749 pipe_config->gmch_pfit.control,
9750 pipe_config->gmch_pfit.pgm_ratios,
9751 pipe_config->gmch_pfit.lvds_border_bits);
9752 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9753 pipe_config->pch_pfit.pos,
9754 pipe_config->pch_pfit.size,
9755 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9756 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9757 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
9758 }
9759
9760 static bool encoders_cloneable(const struct intel_encoder *a,
9761 const struct intel_encoder *b)
9762 {
9763 /* masks could be asymmetric, so check both ways */
9764 return a == b || (a->cloneable & (1 << b->type) &&
9765 b->cloneable & (1 << a->type));
9766 }
9767
9768 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9769 struct intel_encoder *encoder)
9770 {
9771 struct drm_device *dev = crtc->base.dev;
9772 struct intel_encoder *source_encoder;
9773
9774 list_for_each_entry(source_encoder,
9775 &dev->mode_config.encoder_list, base.head) {
9776 if (source_encoder->new_crtc != crtc)
9777 continue;
9778
9779 if (!encoders_cloneable(encoder, source_encoder))
9780 return false;
9781 }
9782
9783 return true;
9784 }
9785
9786 static bool check_encoder_cloning(struct intel_crtc *crtc)
9787 {
9788 struct drm_device *dev = crtc->base.dev;
9789 struct intel_encoder *encoder;
9790
9791 list_for_each_entry(encoder,
9792 &dev->mode_config.encoder_list, base.head) {
9793 if (encoder->new_crtc != crtc)
9794 continue;
9795
9796 if (!check_single_encoder_cloning(crtc, encoder))
9797 return false;
9798 }
9799
9800 return true;
9801 }
9802
9803 static struct intel_crtc_config *
9804 intel_modeset_pipe_config(struct drm_crtc *crtc,
9805 struct drm_framebuffer *fb,
9806 struct drm_display_mode *mode)
9807 {
9808 struct drm_device *dev = crtc->dev;
9809 struct intel_encoder *encoder;
9810 struct intel_crtc_config *pipe_config;
9811 int plane_bpp, ret = -EINVAL;
9812 bool retry = true;
9813
9814 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
9815 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
9816 return ERR_PTR(-EINVAL);
9817 }
9818
9819 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9820 if (!pipe_config)
9821 return ERR_PTR(-ENOMEM);
9822
9823 drm_mode_copy(&pipe_config->adjusted_mode, mode);
9824 drm_mode_copy(&pipe_config->requested_mode, mode);
9825
9826 pipe_config->cpu_transcoder =
9827 (enum transcoder) to_intel_crtc(crtc)->pipe;
9828 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9829
9830 /*
9831 * Sanitize sync polarity flags based on requested ones. If neither
9832 * positive or negative polarity is requested, treat this as meaning
9833 * negative polarity.
9834 */
9835 if (!(pipe_config->adjusted_mode.flags &
9836 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
9837 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
9838
9839 if (!(pipe_config->adjusted_mode.flags &
9840 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
9841 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
9842
9843 /* Compute a starting value for pipe_config->pipe_bpp taking the source
9844 * plane pixel format and any sink constraints into account. Returns the
9845 * source plane bpp so that dithering can be selected on mismatches
9846 * after encoders and crtc also have had their say. */
9847 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
9848 fb, pipe_config);
9849 if (plane_bpp < 0)
9850 goto fail;
9851
9852 /*
9853 * Determine the real pipe dimensions. Note that stereo modes can
9854 * increase the actual pipe size due to the frame doubling and
9855 * insertion of additional space for blanks between the frame. This
9856 * is stored in the crtc timings. We use the requested mode to do this
9857 * computation to clearly distinguish it from the adjusted mode, which
9858 * can be changed by the connectors in the below retry loop.
9859 */
9860 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
9861 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
9862 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
9863
9864 encoder_retry:
9865 /* Ensure the port clock defaults are reset when retrying. */
9866 pipe_config->port_clock = 0;
9867 pipe_config->pixel_multiplier = 1;
9868
9869 /* Fill in default crtc timings, allow encoders to overwrite them. */
9870 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
9871
9872 /* Pass our mode to the connectors and the CRTC to give them a chance to
9873 * adjust it according to limitations or connector properties, and also
9874 * a chance to reject the mode entirely.
9875 */
9876 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9877 base.head) {
9878
9879 if (&encoder->new_crtc->base != crtc)
9880 continue;
9881
9882 if (!(encoder->compute_config(encoder, pipe_config))) {
9883 DRM_DEBUG_KMS("Encoder config failure\n");
9884 goto fail;
9885 }
9886 }
9887
9888 /* Set default port clock if not overwritten by the encoder. Needs to be
9889 * done afterwards in case the encoder adjusts the mode. */
9890 if (!pipe_config->port_clock)
9891 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
9892 * pipe_config->pixel_multiplier;
9893
9894 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
9895 if (ret < 0) {
9896 DRM_DEBUG_KMS("CRTC fixup failed\n");
9897 goto fail;
9898 }
9899
9900 if (ret == RETRY) {
9901 if (WARN(!retry, "loop in pipe configuration computation\n")) {
9902 ret = -EINVAL;
9903 goto fail;
9904 }
9905
9906 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9907 retry = false;
9908 goto encoder_retry;
9909 }
9910
9911 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
9912 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9913 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
9914
9915 return pipe_config;
9916 fail:
9917 kfree(pipe_config);
9918 return ERR_PTR(ret);
9919 }
9920
9921 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
9922 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9923 static void
9924 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
9925 unsigned *prepare_pipes, unsigned *disable_pipes)
9926 {
9927 struct intel_crtc *intel_crtc;
9928 struct drm_device *dev = crtc->dev;
9929 struct intel_encoder *encoder;
9930 struct intel_connector *connector;
9931 struct drm_crtc *tmp_crtc;
9932
9933 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
9934
9935 /* Check which crtcs have changed outputs connected to them, these need
9936 * to be part of the prepare_pipes mask. We don't (yet) support global
9937 * modeset across multiple crtcs, so modeset_pipes will only have one
9938 * bit set at most. */
9939 list_for_each_entry(connector, &dev->mode_config.connector_list,
9940 base.head) {
9941 if (connector->base.encoder == &connector->new_encoder->base)
9942 continue;
9943
9944 if (connector->base.encoder) {
9945 tmp_crtc = connector->base.encoder->crtc;
9946
9947 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9948 }
9949
9950 if (connector->new_encoder)
9951 *prepare_pipes |=
9952 1 << connector->new_encoder->new_crtc->pipe;
9953 }
9954
9955 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9956 base.head) {
9957 if (encoder->base.crtc == &encoder->new_crtc->base)
9958 continue;
9959
9960 if (encoder->base.crtc) {
9961 tmp_crtc = encoder->base.crtc;
9962
9963 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9964 }
9965
9966 if (encoder->new_crtc)
9967 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
9968 }
9969
9970 /* Check for pipes that will be enabled/disabled ... */
9971 for_each_intel_crtc(dev, intel_crtc) {
9972 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
9973 continue;
9974
9975 if (!intel_crtc->new_enabled)
9976 *disable_pipes |= 1 << intel_crtc->pipe;
9977 else
9978 *prepare_pipes |= 1 << intel_crtc->pipe;
9979 }
9980
9981
9982 /* set_mode is also used to update properties on life display pipes. */
9983 intel_crtc = to_intel_crtc(crtc);
9984 if (intel_crtc->new_enabled)
9985 *prepare_pipes |= 1 << intel_crtc->pipe;
9986
9987 /*
9988 * For simplicity do a full modeset on any pipe where the output routing
9989 * changed. We could be more clever, but that would require us to be
9990 * more careful with calling the relevant encoder->mode_set functions.
9991 */
9992 if (*prepare_pipes)
9993 *modeset_pipes = *prepare_pipes;
9994
9995 /* ... and mask these out. */
9996 *modeset_pipes &= ~(*disable_pipes);
9997 *prepare_pipes &= ~(*disable_pipes);
9998
9999 /*
10000 * HACK: We don't (yet) fully support global modesets. intel_set_config
10001 * obies this rule, but the modeset restore mode of
10002 * intel_modeset_setup_hw_state does not.
10003 */
10004 *modeset_pipes &= 1 << intel_crtc->pipe;
10005 *prepare_pipes &= 1 << intel_crtc->pipe;
10006
10007 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10008 *modeset_pipes, *prepare_pipes, *disable_pipes);
10009 }
10010
10011 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10012 {
10013 struct drm_encoder *encoder;
10014 struct drm_device *dev = crtc->dev;
10015
10016 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10017 if (encoder->crtc == crtc)
10018 return true;
10019
10020 return false;
10021 }
10022
10023 static void
10024 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10025 {
10026 struct intel_encoder *intel_encoder;
10027 struct intel_crtc *intel_crtc;
10028 struct drm_connector *connector;
10029
10030 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
10031 base.head) {
10032 if (!intel_encoder->base.crtc)
10033 continue;
10034
10035 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10036
10037 if (prepare_pipes & (1 << intel_crtc->pipe))
10038 intel_encoder->connectors_active = false;
10039 }
10040
10041 intel_modeset_commit_output_state(dev);
10042
10043 /* Double check state. */
10044 for_each_intel_crtc(dev, intel_crtc) {
10045 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10046 WARN_ON(intel_crtc->new_config &&
10047 intel_crtc->new_config != &intel_crtc->config);
10048 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10049 }
10050
10051 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10052 if (!connector->encoder || !connector->encoder->crtc)
10053 continue;
10054
10055 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10056
10057 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10058 struct drm_property *dpms_property =
10059 dev->mode_config.dpms_property;
10060
10061 connector->dpms = DRM_MODE_DPMS_ON;
10062 drm_object_property_set_value(&connector->base,
10063 dpms_property,
10064 DRM_MODE_DPMS_ON);
10065
10066 intel_encoder = to_intel_encoder(connector->encoder);
10067 intel_encoder->connectors_active = true;
10068 }
10069 }
10070
10071 }
10072
10073 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10074 {
10075 int diff;
10076
10077 if (clock1 == clock2)
10078 return true;
10079
10080 if (!clock1 || !clock2)
10081 return false;
10082
10083 diff = abs(clock1 - clock2);
10084
10085 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10086 return true;
10087
10088 return false;
10089 }
10090
10091 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10092 list_for_each_entry((intel_crtc), \
10093 &(dev)->mode_config.crtc_list, \
10094 base.head) \
10095 if (mask & (1 <<(intel_crtc)->pipe))
10096
10097 static bool
10098 intel_pipe_config_compare(struct drm_device *dev,
10099 struct intel_crtc_config *current_config,
10100 struct intel_crtc_config *pipe_config)
10101 {
10102 #define PIPE_CONF_CHECK_X(name) \
10103 if (current_config->name != pipe_config->name) { \
10104 DRM_ERROR("mismatch in " #name " " \
10105 "(expected 0x%08x, found 0x%08x)\n", \
10106 current_config->name, \
10107 pipe_config->name); \
10108 return false; \
10109 }
10110
10111 #define PIPE_CONF_CHECK_I(name) \
10112 if (current_config->name != pipe_config->name) { \
10113 DRM_ERROR("mismatch in " #name " " \
10114 "(expected %i, found %i)\n", \
10115 current_config->name, \
10116 pipe_config->name); \
10117 return false; \
10118 }
10119
10120 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10121 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10122 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10123 "(expected %i, found %i)\n", \
10124 current_config->name & (mask), \
10125 pipe_config->name & (mask)); \
10126 return false; \
10127 }
10128
10129 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10130 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10131 DRM_ERROR("mismatch in " #name " " \
10132 "(expected %i, found %i)\n", \
10133 current_config->name, \
10134 pipe_config->name); \
10135 return false; \
10136 }
10137
10138 #define PIPE_CONF_QUIRK(quirk) \
10139 ((current_config->quirks | pipe_config->quirks) & (quirk))
10140
10141 PIPE_CONF_CHECK_I(cpu_transcoder);
10142
10143 PIPE_CONF_CHECK_I(has_pch_encoder);
10144 PIPE_CONF_CHECK_I(fdi_lanes);
10145 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10146 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10147 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10148 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10149 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10150
10151 PIPE_CONF_CHECK_I(has_dp_encoder);
10152 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10153 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10154 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10155 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10156 PIPE_CONF_CHECK_I(dp_m_n.tu);
10157
10158 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10159 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10160 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10161 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10162 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10163 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10164
10165 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10166 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10167 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10168 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10169 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10170 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10171
10172 PIPE_CONF_CHECK_I(pixel_multiplier);
10173 PIPE_CONF_CHECK_I(has_hdmi_sink);
10174 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10175 IS_VALLEYVIEW(dev))
10176 PIPE_CONF_CHECK_I(limited_color_range);
10177
10178 PIPE_CONF_CHECK_I(has_audio);
10179
10180 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10181 DRM_MODE_FLAG_INTERLACE);
10182
10183 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10184 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10185 DRM_MODE_FLAG_PHSYNC);
10186 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10187 DRM_MODE_FLAG_NHSYNC);
10188 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10189 DRM_MODE_FLAG_PVSYNC);
10190 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10191 DRM_MODE_FLAG_NVSYNC);
10192 }
10193
10194 PIPE_CONF_CHECK_I(pipe_src_w);
10195 PIPE_CONF_CHECK_I(pipe_src_h);
10196
10197 /*
10198 * FIXME: BIOS likes to set up a cloned config with lvds+external
10199 * screen. Since we don't yet re-compute the pipe config when moving
10200 * just the lvds port away to another pipe the sw tracking won't match.
10201 *
10202 * Proper atomic modesets with recomputed global state will fix this.
10203 * Until then just don't check gmch state for inherited modes.
10204 */
10205 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10206 PIPE_CONF_CHECK_I(gmch_pfit.control);
10207 /* pfit ratios are autocomputed by the hw on gen4+ */
10208 if (INTEL_INFO(dev)->gen < 4)
10209 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10210 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10211 }
10212
10213 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10214 if (current_config->pch_pfit.enabled) {
10215 PIPE_CONF_CHECK_I(pch_pfit.pos);
10216 PIPE_CONF_CHECK_I(pch_pfit.size);
10217 }
10218
10219 /* BDW+ don't expose a synchronous way to read the state */
10220 if (IS_HASWELL(dev))
10221 PIPE_CONF_CHECK_I(ips_enabled);
10222
10223 PIPE_CONF_CHECK_I(double_wide);
10224
10225 PIPE_CONF_CHECK_I(shared_dpll);
10226 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10227 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10228 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10229 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10230
10231 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10232 PIPE_CONF_CHECK_I(pipe_bpp);
10233
10234 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10235 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10236
10237 #undef PIPE_CONF_CHECK_X
10238 #undef PIPE_CONF_CHECK_I
10239 #undef PIPE_CONF_CHECK_FLAGS
10240 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10241 #undef PIPE_CONF_QUIRK
10242
10243 return true;
10244 }
10245
10246 static void
10247 check_connector_state(struct drm_device *dev)
10248 {
10249 struct intel_connector *connector;
10250
10251 list_for_each_entry(connector, &dev->mode_config.connector_list,
10252 base.head) {
10253 /* This also checks the encoder/connector hw state with the
10254 * ->get_hw_state callbacks. */
10255 intel_connector_check_state(connector);
10256
10257 WARN(&connector->new_encoder->base != connector->base.encoder,
10258 "connector's staged encoder doesn't match current encoder\n");
10259 }
10260 }
10261
10262 static void
10263 check_encoder_state(struct drm_device *dev)
10264 {
10265 struct intel_encoder *encoder;
10266 struct intel_connector *connector;
10267
10268 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10269 base.head) {
10270 bool enabled = false;
10271 bool active = false;
10272 enum pipe pipe, tracked_pipe;
10273
10274 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10275 encoder->base.base.id,
10276 encoder->base.name);
10277
10278 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10279 "encoder's stage crtc doesn't match current crtc\n");
10280 WARN(encoder->connectors_active && !encoder->base.crtc,
10281 "encoder's active_connectors set, but no crtc\n");
10282
10283 list_for_each_entry(connector, &dev->mode_config.connector_list,
10284 base.head) {
10285 if (connector->base.encoder != &encoder->base)
10286 continue;
10287 enabled = true;
10288 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10289 active = true;
10290 }
10291 WARN(!!encoder->base.crtc != enabled,
10292 "encoder's enabled state mismatch "
10293 "(expected %i, found %i)\n",
10294 !!encoder->base.crtc, enabled);
10295 WARN(active && !encoder->base.crtc,
10296 "active encoder with no crtc\n");
10297
10298 WARN(encoder->connectors_active != active,
10299 "encoder's computed active state doesn't match tracked active state "
10300 "(expected %i, found %i)\n", active, encoder->connectors_active);
10301
10302 active = encoder->get_hw_state(encoder, &pipe);
10303 WARN(active != encoder->connectors_active,
10304 "encoder's hw state doesn't match sw tracking "
10305 "(expected %i, found %i)\n",
10306 encoder->connectors_active, active);
10307
10308 if (!encoder->base.crtc)
10309 continue;
10310
10311 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10312 WARN(active && pipe != tracked_pipe,
10313 "active encoder's pipe doesn't match"
10314 "(expected %i, found %i)\n",
10315 tracked_pipe, pipe);
10316
10317 }
10318 }
10319
10320 static void
10321 check_crtc_state(struct drm_device *dev)
10322 {
10323 struct drm_i915_private *dev_priv = dev->dev_private;
10324 struct intel_crtc *crtc;
10325 struct intel_encoder *encoder;
10326 struct intel_crtc_config pipe_config;
10327
10328 for_each_intel_crtc(dev, crtc) {
10329 bool enabled = false;
10330 bool active = false;
10331
10332 memset(&pipe_config, 0, sizeof(pipe_config));
10333
10334 DRM_DEBUG_KMS("[CRTC:%d]\n",
10335 crtc->base.base.id);
10336
10337 WARN(crtc->active && !crtc->base.enabled,
10338 "active crtc, but not enabled in sw tracking\n");
10339
10340 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10341 base.head) {
10342 if (encoder->base.crtc != &crtc->base)
10343 continue;
10344 enabled = true;
10345 if (encoder->connectors_active)
10346 active = true;
10347 }
10348
10349 WARN(active != crtc->active,
10350 "crtc's computed active state doesn't match tracked active state "
10351 "(expected %i, found %i)\n", active, crtc->active);
10352 WARN(enabled != crtc->base.enabled,
10353 "crtc's computed enabled state doesn't match tracked enabled state "
10354 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10355
10356 active = dev_priv->display.get_pipe_config(crtc,
10357 &pipe_config);
10358
10359 /* hw state is inconsistent with the pipe A quirk */
10360 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
10361 active = crtc->active;
10362
10363 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10364 base.head) {
10365 enum pipe pipe;
10366 if (encoder->base.crtc != &crtc->base)
10367 continue;
10368 if (encoder->get_hw_state(encoder, &pipe))
10369 encoder->get_config(encoder, &pipe_config);
10370 }
10371
10372 WARN(crtc->active != active,
10373 "crtc active state doesn't match with hw state "
10374 "(expected %i, found %i)\n", crtc->active, active);
10375
10376 if (active &&
10377 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10378 WARN(1, "pipe state doesn't match!\n");
10379 intel_dump_pipe_config(crtc, &pipe_config,
10380 "[hw state]");
10381 intel_dump_pipe_config(crtc, &crtc->config,
10382 "[sw state]");
10383 }
10384 }
10385 }
10386
10387 static void
10388 check_shared_dpll_state(struct drm_device *dev)
10389 {
10390 struct drm_i915_private *dev_priv = dev->dev_private;
10391 struct intel_crtc *crtc;
10392 struct intel_dpll_hw_state dpll_hw_state;
10393 int i;
10394
10395 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10396 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10397 int enabled_crtcs = 0, active_crtcs = 0;
10398 bool active;
10399
10400 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10401
10402 DRM_DEBUG_KMS("%s\n", pll->name);
10403
10404 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10405
10406 WARN(pll->active > pll->refcount,
10407 "more active pll users than references: %i vs %i\n",
10408 pll->active, pll->refcount);
10409 WARN(pll->active && !pll->on,
10410 "pll in active use but not on in sw tracking\n");
10411 WARN(pll->on && !pll->active,
10412 "pll in on but not on in use in sw tracking\n");
10413 WARN(pll->on != active,
10414 "pll on state mismatch (expected %i, found %i)\n",
10415 pll->on, active);
10416
10417 for_each_intel_crtc(dev, crtc) {
10418 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10419 enabled_crtcs++;
10420 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10421 active_crtcs++;
10422 }
10423 WARN(pll->active != active_crtcs,
10424 "pll active crtcs mismatch (expected %i, found %i)\n",
10425 pll->active, active_crtcs);
10426 WARN(pll->refcount != enabled_crtcs,
10427 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10428 pll->refcount, enabled_crtcs);
10429
10430 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10431 sizeof(dpll_hw_state)),
10432 "pll hw state mismatch\n");
10433 }
10434 }
10435
10436 void
10437 intel_modeset_check_state(struct drm_device *dev)
10438 {
10439 check_connector_state(dev);
10440 check_encoder_state(dev);
10441 check_crtc_state(dev);
10442 check_shared_dpll_state(dev);
10443 }
10444
10445 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10446 int dotclock)
10447 {
10448 /*
10449 * FDI already provided one idea for the dotclock.
10450 * Yell if the encoder disagrees.
10451 */
10452 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10453 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10454 pipe_config->adjusted_mode.crtc_clock, dotclock);
10455 }
10456
10457 static void update_scanline_offset(struct intel_crtc *crtc)
10458 {
10459 struct drm_device *dev = crtc->base.dev;
10460
10461 /*
10462 * The scanline counter increments at the leading edge of hsync.
10463 *
10464 * On most platforms it starts counting from vtotal-1 on the
10465 * first active line. That means the scanline counter value is
10466 * always one less than what we would expect. Ie. just after
10467 * start of vblank, which also occurs at start of hsync (on the
10468 * last active line), the scanline counter will read vblank_start-1.
10469 *
10470 * On gen2 the scanline counter starts counting from 1 instead
10471 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10472 * to keep the value positive), instead of adding one.
10473 *
10474 * On HSW+ the behaviour of the scanline counter depends on the output
10475 * type. For DP ports it behaves like most other platforms, but on HDMI
10476 * there's an extra 1 line difference. So we need to add two instead of
10477 * one to the value.
10478 */
10479 if (IS_GEN2(dev)) {
10480 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10481 int vtotal;
10482
10483 vtotal = mode->crtc_vtotal;
10484 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10485 vtotal /= 2;
10486
10487 crtc->scanline_offset = vtotal - 1;
10488 } else if (HAS_DDI(dev) &&
10489 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
10490 crtc->scanline_offset = 2;
10491 } else
10492 crtc->scanline_offset = 1;
10493 }
10494
10495 static int __intel_set_mode(struct drm_crtc *crtc,
10496 struct drm_display_mode *mode,
10497 int x, int y, struct drm_framebuffer *fb)
10498 {
10499 struct drm_device *dev = crtc->dev;
10500 struct drm_i915_private *dev_priv = dev->dev_private;
10501 struct drm_display_mode *saved_mode;
10502 struct intel_crtc_config *pipe_config = NULL;
10503 struct intel_crtc *intel_crtc;
10504 unsigned disable_pipes, prepare_pipes, modeset_pipes;
10505 int ret = 0;
10506
10507 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10508 if (!saved_mode)
10509 return -ENOMEM;
10510
10511 intel_modeset_affected_pipes(crtc, &modeset_pipes,
10512 &prepare_pipes, &disable_pipes);
10513
10514 *saved_mode = crtc->mode;
10515
10516 /* Hack: Because we don't (yet) support global modeset on multiple
10517 * crtcs, we don't keep track of the new mode for more than one crtc.
10518 * Hence simply check whether any bit is set in modeset_pipes in all the
10519 * pieces of code that are not yet converted to deal with mutliple crtcs
10520 * changing their mode at the same time. */
10521 if (modeset_pipes) {
10522 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10523 if (IS_ERR(pipe_config)) {
10524 ret = PTR_ERR(pipe_config);
10525 pipe_config = NULL;
10526
10527 goto out;
10528 }
10529 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10530 "[modeset]");
10531 to_intel_crtc(crtc)->new_config = pipe_config;
10532 }
10533
10534 /*
10535 * See if the config requires any additional preparation, e.g.
10536 * to adjust global state with pipes off. We need to do this
10537 * here so we can get the modeset_pipe updated config for the new
10538 * mode set on this crtc. For other crtcs we need to use the
10539 * adjusted_mode bits in the crtc directly.
10540 */
10541 if (IS_VALLEYVIEW(dev)) {
10542 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10543
10544 /* may have added more to prepare_pipes than we should */
10545 prepare_pipes &= ~disable_pipes;
10546 }
10547
10548 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10549 intel_crtc_disable(&intel_crtc->base);
10550
10551 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10552 if (intel_crtc->base.enabled)
10553 dev_priv->display.crtc_disable(&intel_crtc->base);
10554 }
10555
10556 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10557 * to set it here already despite that we pass it down the callchain.
10558 */
10559 if (modeset_pipes) {
10560 crtc->mode = *mode;
10561 /* mode_set/enable/disable functions rely on a correct pipe
10562 * config. */
10563 to_intel_crtc(crtc)->config = *pipe_config;
10564 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10565
10566 /*
10567 * Calculate and store various constants which
10568 * are later needed by vblank and swap-completion
10569 * timestamping. They are derived from true hwmode.
10570 */
10571 drm_calc_timestamping_constants(crtc,
10572 &pipe_config->adjusted_mode);
10573 }
10574
10575 /* Only after disabling all output pipelines that will be changed can we
10576 * update the the output configuration. */
10577 intel_modeset_update_state(dev, prepare_pipes);
10578
10579 if (dev_priv->display.modeset_global_resources)
10580 dev_priv->display.modeset_global_resources(dev);
10581
10582 /* Set up the DPLL and any encoders state that needs to adjust or depend
10583 * on the DPLL.
10584 */
10585 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10586 struct drm_framebuffer *old_fb;
10587 struct drm_i915_gem_object *old_obj = NULL;
10588 struct drm_i915_gem_object *obj =
10589 to_intel_framebuffer(fb)->obj;
10590
10591 mutex_lock(&dev->struct_mutex);
10592 ret = intel_pin_and_fence_fb_obj(dev,
10593 obj,
10594 NULL);
10595 if (ret != 0) {
10596 DRM_ERROR("pin & fence failed\n");
10597 mutex_unlock(&dev->struct_mutex);
10598 goto done;
10599 }
10600 old_fb = crtc->primary->fb;
10601 if (old_fb) {
10602 old_obj = to_intel_framebuffer(old_fb)->obj;
10603 intel_unpin_fb_obj(old_obj);
10604 }
10605 i915_gem_track_fb(old_obj, obj,
10606 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
10607 mutex_unlock(&dev->struct_mutex);
10608
10609 crtc->primary->fb = fb;
10610 crtc->x = x;
10611 crtc->y = y;
10612
10613 ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
10614 x, y, fb);
10615 if (ret)
10616 goto done;
10617 }
10618
10619 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10620 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10621 update_scanline_offset(intel_crtc);
10622
10623 dev_priv->display.crtc_enable(&intel_crtc->base);
10624 }
10625
10626 /* FIXME: add subpixel order */
10627 done:
10628 if (ret && crtc->enabled)
10629 crtc->mode = *saved_mode;
10630
10631 out:
10632 kfree(pipe_config);
10633 kfree(saved_mode);
10634 return ret;
10635 }
10636
10637 static int intel_set_mode(struct drm_crtc *crtc,
10638 struct drm_display_mode *mode,
10639 int x, int y, struct drm_framebuffer *fb)
10640 {
10641 int ret;
10642
10643 ret = __intel_set_mode(crtc, mode, x, y, fb);
10644
10645 if (ret == 0)
10646 intel_modeset_check_state(crtc->dev);
10647
10648 return ret;
10649 }
10650
10651 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10652 {
10653 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10654 }
10655
10656 #undef for_each_intel_crtc_masked
10657
10658 static void intel_set_config_free(struct intel_set_config *config)
10659 {
10660 if (!config)
10661 return;
10662
10663 kfree(config->save_connector_encoders);
10664 kfree(config->save_encoder_crtcs);
10665 kfree(config->save_crtc_enabled);
10666 kfree(config);
10667 }
10668
10669 static int intel_set_config_save_state(struct drm_device *dev,
10670 struct intel_set_config *config)
10671 {
10672 struct drm_crtc *crtc;
10673 struct drm_encoder *encoder;
10674 struct drm_connector *connector;
10675 int count;
10676
10677 config->save_crtc_enabled =
10678 kcalloc(dev->mode_config.num_crtc,
10679 sizeof(bool), GFP_KERNEL);
10680 if (!config->save_crtc_enabled)
10681 return -ENOMEM;
10682
10683 config->save_encoder_crtcs =
10684 kcalloc(dev->mode_config.num_encoder,
10685 sizeof(struct drm_crtc *), GFP_KERNEL);
10686 if (!config->save_encoder_crtcs)
10687 return -ENOMEM;
10688
10689 config->save_connector_encoders =
10690 kcalloc(dev->mode_config.num_connector,
10691 sizeof(struct drm_encoder *), GFP_KERNEL);
10692 if (!config->save_connector_encoders)
10693 return -ENOMEM;
10694
10695 /* Copy data. Note that driver private data is not affected.
10696 * Should anything bad happen only the expected state is
10697 * restored, not the drivers personal bookkeeping.
10698 */
10699 count = 0;
10700 for_each_crtc(dev, crtc) {
10701 config->save_crtc_enabled[count++] = crtc->enabled;
10702 }
10703
10704 count = 0;
10705 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10706 config->save_encoder_crtcs[count++] = encoder->crtc;
10707 }
10708
10709 count = 0;
10710 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10711 config->save_connector_encoders[count++] = connector->encoder;
10712 }
10713
10714 return 0;
10715 }
10716
10717 static void intel_set_config_restore_state(struct drm_device *dev,
10718 struct intel_set_config *config)
10719 {
10720 struct intel_crtc *crtc;
10721 struct intel_encoder *encoder;
10722 struct intel_connector *connector;
10723 int count;
10724
10725 count = 0;
10726 for_each_intel_crtc(dev, crtc) {
10727 crtc->new_enabled = config->save_crtc_enabled[count++];
10728
10729 if (crtc->new_enabled)
10730 crtc->new_config = &crtc->config;
10731 else
10732 crtc->new_config = NULL;
10733 }
10734
10735 count = 0;
10736 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10737 encoder->new_crtc =
10738 to_intel_crtc(config->save_encoder_crtcs[count++]);
10739 }
10740
10741 count = 0;
10742 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10743 connector->new_encoder =
10744 to_intel_encoder(config->save_connector_encoders[count++]);
10745 }
10746 }
10747
10748 static bool
10749 is_crtc_connector_off(struct drm_mode_set *set)
10750 {
10751 int i;
10752
10753 if (set->num_connectors == 0)
10754 return false;
10755
10756 if (WARN_ON(set->connectors == NULL))
10757 return false;
10758
10759 for (i = 0; i < set->num_connectors; i++)
10760 if (set->connectors[i]->encoder &&
10761 set->connectors[i]->encoder->crtc == set->crtc &&
10762 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
10763 return true;
10764
10765 return false;
10766 }
10767
10768 static void
10769 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
10770 struct intel_set_config *config)
10771 {
10772
10773 /* We should be able to check here if the fb has the same properties
10774 * and then just flip_or_move it */
10775 if (is_crtc_connector_off(set)) {
10776 config->mode_changed = true;
10777 } else if (set->crtc->primary->fb != set->fb) {
10778 /*
10779 * If we have no fb, we can only flip as long as the crtc is
10780 * active, otherwise we need a full mode set. The crtc may
10781 * be active if we've only disabled the primary plane, or
10782 * in fastboot situations.
10783 */
10784 if (set->crtc->primary->fb == NULL) {
10785 struct intel_crtc *intel_crtc =
10786 to_intel_crtc(set->crtc);
10787
10788 if (intel_crtc->active) {
10789 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
10790 config->fb_changed = true;
10791 } else {
10792 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
10793 config->mode_changed = true;
10794 }
10795 } else if (set->fb == NULL) {
10796 config->mode_changed = true;
10797 } else if (set->fb->pixel_format !=
10798 set->crtc->primary->fb->pixel_format) {
10799 config->mode_changed = true;
10800 } else {
10801 config->fb_changed = true;
10802 }
10803 }
10804
10805 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
10806 config->fb_changed = true;
10807
10808 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
10809 DRM_DEBUG_KMS("modes are different, full mode set\n");
10810 drm_mode_debug_printmodeline(&set->crtc->mode);
10811 drm_mode_debug_printmodeline(set->mode);
10812 config->mode_changed = true;
10813 }
10814
10815 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
10816 set->crtc->base.id, config->mode_changed, config->fb_changed);
10817 }
10818
10819 static int
10820 intel_modeset_stage_output_state(struct drm_device *dev,
10821 struct drm_mode_set *set,
10822 struct intel_set_config *config)
10823 {
10824 struct intel_connector *connector;
10825 struct intel_encoder *encoder;
10826 struct intel_crtc *crtc;
10827 int ro;
10828
10829 /* The upper layers ensure that we either disable a crtc or have a list
10830 * of connectors. For paranoia, double-check this. */
10831 WARN_ON(!set->fb && (set->num_connectors != 0));
10832 WARN_ON(set->fb && (set->num_connectors == 0));
10833
10834 list_for_each_entry(connector, &dev->mode_config.connector_list,
10835 base.head) {
10836 /* Otherwise traverse passed in connector list and get encoders
10837 * for them. */
10838 for (ro = 0; ro < set->num_connectors; ro++) {
10839 if (set->connectors[ro] == &connector->base) {
10840 connector->new_encoder = connector->encoder;
10841 break;
10842 }
10843 }
10844
10845 /* If we disable the crtc, disable all its connectors. Also, if
10846 * the connector is on the changing crtc but not on the new
10847 * connector list, disable it. */
10848 if ((!set->fb || ro == set->num_connectors) &&
10849 connector->base.encoder &&
10850 connector->base.encoder->crtc == set->crtc) {
10851 connector->new_encoder = NULL;
10852
10853 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
10854 connector->base.base.id,
10855 connector->base.name);
10856 }
10857
10858
10859 if (&connector->new_encoder->base != connector->base.encoder) {
10860 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
10861 config->mode_changed = true;
10862 }
10863 }
10864 /* connector->new_encoder is now updated for all connectors. */
10865
10866 /* Update crtc of enabled connectors. */
10867 list_for_each_entry(connector, &dev->mode_config.connector_list,
10868 base.head) {
10869 struct drm_crtc *new_crtc;
10870
10871 if (!connector->new_encoder)
10872 continue;
10873
10874 new_crtc = connector->new_encoder->base.crtc;
10875
10876 for (ro = 0; ro < set->num_connectors; ro++) {
10877 if (set->connectors[ro] == &connector->base)
10878 new_crtc = set->crtc;
10879 }
10880
10881 /* Make sure the new CRTC will work with the encoder */
10882 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
10883 new_crtc)) {
10884 return -EINVAL;
10885 }
10886 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
10887
10888 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
10889 connector->base.base.id,
10890 connector->base.name,
10891 new_crtc->base.id);
10892 }
10893
10894 /* Check for any encoders that needs to be disabled. */
10895 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10896 base.head) {
10897 int num_connectors = 0;
10898 list_for_each_entry(connector,
10899 &dev->mode_config.connector_list,
10900 base.head) {
10901 if (connector->new_encoder == encoder) {
10902 WARN_ON(!connector->new_encoder->new_crtc);
10903 num_connectors++;
10904 }
10905 }
10906
10907 if (num_connectors == 0)
10908 encoder->new_crtc = NULL;
10909 else if (num_connectors > 1)
10910 return -EINVAL;
10911
10912 /* Only now check for crtc changes so we don't miss encoders
10913 * that will be disabled. */
10914 if (&encoder->new_crtc->base != encoder->base.crtc) {
10915 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
10916 config->mode_changed = true;
10917 }
10918 }
10919 /* Now we've also updated encoder->new_crtc for all encoders. */
10920
10921 for_each_intel_crtc(dev, crtc) {
10922 crtc->new_enabled = false;
10923
10924 list_for_each_entry(encoder,
10925 &dev->mode_config.encoder_list,
10926 base.head) {
10927 if (encoder->new_crtc == crtc) {
10928 crtc->new_enabled = true;
10929 break;
10930 }
10931 }
10932
10933 if (crtc->new_enabled != crtc->base.enabled) {
10934 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
10935 crtc->new_enabled ? "en" : "dis");
10936 config->mode_changed = true;
10937 }
10938
10939 if (crtc->new_enabled)
10940 crtc->new_config = &crtc->config;
10941 else
10942 crtc->new_config = NULL;
10943 }
10944
10945 return 0;
10946 }
10947
10948 static void disable_crtc_nofb(struct intel_crtc *crtc)
10949 {
10950 struct drm_device *dev = crtc->base.dev;
10951 struct intel_encoder *encoder;
10952 struct intel_connector *connector;
10953
10954 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
10955 pipe_name(crtc->pipe));
10956
10957 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10958 if (connector->new_encoder &&
10959 connector->new_encoder->new_crtc == crtc)
10960 connector->new_encoder = NULL;
10961 }
10962
10963 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10964 if (encoder->new_crtc == crtc)
10965 encoder->new_crtc = NULL;
10966 }
10967
10968 crtc->new_enabled = false;
10969 crtc->new_config = NULL;
10970 }
10971
10972 static int intel_crtc_set_config(struct drm_mode_set *set)
10973 {
10974 struct drm_device *dev;
10975 struct drm_mode_set save_set;
10976 struct intel_set_config *config;
10977 int ret;
10978
10979 BUG_ON(!set);
10980 BUG_ON(!set->crtc);
10981 BUG_ON(!set->crtc->helper_private);
10982
10983 /* Enforce sane interface api - has been abused by the fb helper. */
10984 BUG_ON(!set->mode && set->fb);
10985 BUG_ON(set->fb && set->num_connectors == 0);
10986
10987 if (set->fb) {
10988 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
10989 set->crtc->base.id, set->fb->base.id,
10990 (int)set->num_connectors, set->x, set->y);
10991 } else {
10992 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
10993 }
10994
10995 dev = set->crtc->dev;
10996
10997 ret = -ENOMEM;
10998 config = kzalloc(sizeof(*config), GFP_KERNEL);
10999 if (!config)
11000 goto out_config;
11001
11002 ret = intel_set_config_save_state(dev, config);
11003 if (ret)
11004 goto out_config;
11005
11006 save_set.crtc = set->crtc;
11007 save_set.mode = &set->crtc->mode;
11008 save_set.x = set->crtc->x;
11009 save_set.y = set->crtc->y;
11010 save_set.fb = set->crtc->primary->fb;
11011
11012 /* Compute whether we need a full modeset, only an fb base update or no
11013 * change at all. In the future we might also check whether only the
11014 * mode changed, e.g. for LVDS where we only change the panel fitter in
11015 * such cases. */
11016 intel_set_config_compute_mode_changes(set, config);
11017
11018 ret = intel_modeset_stage_output_state(dev, set, config);
11019 if (ret)
11020 goto fail;
11021
11022 if (config->mode_changed) {
11023 ret = intel_set_mode(set->crtc, set->mode,
11024 set->x, set->y, set->fb);
11025 } else if (config->fb_changed) {
11026 struct drm_i915_private *dev_priv = dev->dev_private;
11027 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11028
11029 intel_crtc_wait_for_pending_flips(set->crtc);
11030
11031 ret = intel_pipe_set_base(set->crtc,
11032 set->x, set->y, set->fb);
11033
11034 /*
11035 * We need to make sure the primary plane is re-enabled if it
11036 * has previously been turned off.
11037 */
11038 if (!intel_crtc->primary_enabled && ret == 0) {
11039 WARN_ON(!intel_crtc->active);
11040 intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane,
11041 intel_crtc->pipe);
11042 }
11043
11044 /*
11045 * In the fastboot case this may be our only check of the
11046 * state after boot. It would be better to only do it on
11047 * the first update, but we don't have a nice way of doing that
11048 * (and really, set_config isn't used much for high freq page
11049 * flipping, so increasing its cost here shouldn't be a big
11050 * deal).
11051 */
11052 if (i915.fastboot && ret == 0)
11053 intel_modeset_check_state(set->crtc->dev);
11054 }
11055
11056 if (ret) {
11057 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11058 set->crtc->base.id, ret);
11059 fail:
11060 intel_set_config_restore_state(dev, config);
11061
11062 /*
11063 * HACK: if the pipe was on, but we didn't have a framebuffer,
11064 * force the pipe off to avoid oopsing in the modeset code
11065 * due to fb==NULL. This should only happen during boot since
11066 * we don't yet reconstruct the FB from the hardware state.
11067 */
11068 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11069 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11070
11071 /* Try to restore the config */
11072 if (config->mode_changed &&
11073 intel_set_mode(save_set.crtc, save_set.mode,
11074 save_set.x, save_set.y, save_set.fb))
11075 DRM_ERROR("failed to restore config after modeset failure\n");
11076 }
11077
11078 out_config:
11079 intel_set_config_free(config);
11080 return ret;
11081 }
11082
11083 static const struct drm_crtc_funcs intel_crtc_funcs = {
11084 .gamma_set = intel_crtc_gamma_set,
11085 .set_config = intel_crtc_set_config,
11086 .destroy = intel_crtc_destroy,
11087 .page_flip = intel_crtc_page_flip,
11088 };
11089
11090 static void intel_cpu_pll_init(struct drm_device *dev)
11091 {
11092 if (HAS_DDI(dev))
11093 intel_ddi_pll_init(dev);
11094 }
11095
11096 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11097 struct intel_shared_dpll *pll,
11098 struct intel_dpll_hw_state *hw_state)
11099 {
11100 uint32_t val;
11101
11102 val = I915_READ(PCH_DPLL(pll->id));
11103 hw_state->dpll = val;
11104 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11105 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11106
11107 return val & DPLL_VCO_ENABLE;
11108 }
11109
11110 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11111 struct intel_shared_dpll *pll)
11112 {
11113 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
11114 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
11115 }
11116
11117 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11118 struct intel_shared_dpll *pll)
11119 {
11120 /* PCH refclock must be enabled first */
11121 ibx_assert_pch_refclk_enabled(dev_priv);
11122
11123 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11124
11125 /* Wait for the clocks to stabilize. */
11126 POSTING_READ(PCH_DPLL(pll->id));
11127 udelay(150);
11128
11129 /* The pixel multiplier can only be updated once the
11130 * DPLL is enabled and the clocks are stable.
11131 *
11132 * So write it again.
11133 */
11134 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11135 POSTING_READ(PCH_DPLL(pll->id));
11136 udelay(200);
11137 }
11138
11139 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11140 struct intel_shared_dpll *pll)
11141 {
11142 struct drm_device *dev = dev_priv->dev;
11143 struct intel_crtc *crtc;
11144
11145 /* Make sure no transcoder isn't still depending on us. */
11146 for_each_intel_crtc(dev, crtc) {
11147 if (intel_crtc_to_shared_dpll(crtc) == pll)
11148 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11149 }
11150
11151 I915_WRITE(PCH_DPLL(pll->id), 0);
11152 POSTING_READ(PCH_DPLL(pll->id));
11153 udelay(200);
11154 }
11155
11156 static char *ibx_pch_dpll_names[] = {
11157 "PCH DPLL A",
11158 "PCH DPLL B",
11159 };
11160
11161 static void ibx_pch_dpll_init(struct drm_device *dev)
11162 {
11163 struct drm_i915_private *dev_priv = dev->dev_private;
11164 int i;
11165
11166 dev_priv->num_shared_dpll = 2;
11167
11168 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11169 dev_priv->shared_dplls[i].id = i;
11170 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11171 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11172 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11173 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11174 dev_priv->shared_dplls[i].get_hw_state =
11175 ibx_pch_dpll_get_hw_state;
11176 }
11177 }
11178
11179 static void intel_shared_dpll_init(struct drm_device *dev)
11180 {
11181 struct drm_i915_private *dev_priv = dev->dev_private;
11182
11183 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11184 ibx_pch_dpll_init(dev);
11185 else
11186 dev_priv->num_shared_dpll = 0;
11187
11188 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11189 }
11190
11191 static int
11192 intel_primary_plane_disable(struct drm_plane *plane)
11193 {
11194 struct drm_device *dev = plane->dev;
11195 struct drm_i915_private *dev_priv = dev->dev_private;
11196 struct intel_plane *intel_plane = to_intel_plane(plane);
11197 struct intel_crtc *intel_crtc;
11198
11199 if (!plane->fb)
11200 return 0;
11201
11202 BUG_ON(!plane->crtc);
11203
11204 intel_crtc = to_intel_crtc(plane->crtc);
11205
11206 /*
11207 * Even though we checked plane->fb above, it's still possible that
11208 * the primary plane has been implicitly disabled because the crtc
11209 * coordinates given weren't visible, or because we detected
11210 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11211 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11212 * In either case, we need to unpin the FB and let the fb pointer get
11213 * updated, but otherwise we don't need to touch the hardware.
11214 */
11215 if (!intel_crtc->primary_enabled)
11216 goto disable_unpin;
11217
11218 intel_crtc_wait_for_pending_flips(plane->crtc);
11219 intel_disable_primary_hw_plane(dev_priv, intel_plane->plane,
11220 intel_plane->pipe);
11221 disable_unpin:
11222 i915_gem_track_fb(to_intel_framebuffer(plane->fb)->obj, NULL,
11223 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11224 intel_unpin_fb_obj(to_intel_framebuffer(plane->fb)->obj);
11225 plane->fb = NULL;
11226
11227 return 0;
11228 }
11229
11230 static int
11231 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11232 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11233 unsigned int crtc_w, unsigned int crtc_h,
11234 uint32_t src_x, uint32_t src_y,
11235 uint32_t src_w, uint32_t src_h)
11236 {
11237 struct drm_device *dev = crtc->dev;
11238 struct drm_i915_private *dev_priv = dev->dev_private;
11239 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11240 struct intel_plane *intel_plane = to_intel_plane(plane);
11241 struct drm_i915_gem_object *obj, *old_obj = NULL;
11242 struct drm_rect dest = {
11243 /* integer pixels */
11244 .x1 = crtc_x,
11245 .y1 = crtc_y,
11246 .x2 = crtc_x + crtc_w,
11247 .y2 = crtc_y + crtc_h,
11248 };
11249 struct drm_rect src = {
11250 /* 16.16 fixed point */
11251 .x1 = src_x,
11252 .y1 = src_y,
11253 .x2 = src_x + src_w,
11254 .y2 = src_y + src_h,
11255 };
11256 const struct drm_rect clip = {
11257 /* integer pixels */
11258 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
11259 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
11260 };
11261 bool visible;
11262 int ret;
11263
11264 ret = drm_plane_helper_check_update(plane, crtc, fb,
11265 &src, &dest, &clip,
11266 DRM_PLANE_HELPER_NO_SCALING,
11267 DRM_PLANE_HELPER_NO_SCALING,
11268 false, true, &visible);
11269
11270 if (ret)
11271 return ret;
11272
11273 if (plane->fb)
11274 old_obj = to_intel_framebuffer(plane->fb)->obj;
11275 obj = to_intel_framebuffer(fb)->obj;
11276
11277 /*
11278 * If the CRTC isn't enabled, we're just pinning the framebuffer,
11279 * updating the fb pointer, and returning without touching the
11280 * hardware. This allows us to later do a drmModeSetCrtc with fb=-1 to
11281 * turn on the display with all planes setup as desired.
11282 */
11283 if (!crtc->enabled) {
11284 /*
11285 * If we already called setplane while the crtc was disabled,
11286 * we may have an fb pinned; unpin it.
11287 */
11288 if (plane->fb)
11289 intel_unpin_fb_obj(old_obj);
11290
11291 i915_gem_track_fb(old_obj, obj,
11292 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11293
11294 /* Pin and return without programming hardware */
11295 return intel_pin_and_fence_fb_obj(dev, obj, NULL);
11296 }
11297
11298 intel_crtc_wait_for_pending_flips(crtc);
11299
11300 /*
11301 * If clipping results in a non-visible primary plane, we'll disable
11302 * the primary plane. Note that this is a bit different than what
11303 * happens if userspace explicitly disables the plane by passing fb=0
11304 * because plane->fb still gets set and pinned.
11305 */
11306 if (!visible) {
11307 /*
11308 * Try to pin the new fb first so that we can bail out if we
11309 * fail.
11310 */
11311 if (plane->fb != fb) {
11312 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11313 if (ret)
11314 return ret;
11315 }
11316
11317 i915_gem_track_fb(old_obj, obj,
11318 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11319
11320 if (intel_crtc->primary_enabled)
11321 intel_disable_primary_hw_plane(dev_priv,
11322 intel_plane->plane,
11323 intel_plane->pipe);
11324
11325
11326 if (plane->fb != fb)
11327 if (plane->fb)
11328 intel_unpin_fb_obj(old_obj);
11329
11330 return 0;
11331 }
11332
11333 ret = intel_pipe_set_base(crtc, src.x1, src.y1, fb);
11334 if (ret)
11335 return ret;
11336
11337 if (!intel_crtc->primary_enabled)
11338 intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane,
11339 intel_crtc->pipe);
11340
11341 return 0;
11342 }
11343
11344 /* Common destruction function for both primary and cursor planes */
11345 static void intel_plane_destroy(struct drm_plane *plane)
11346 {
11347 struct intel_plane *intel_plane = to_intel_plane(plane);
11348 drm_plane_cleanup(plane);
11349 kfree(intel_plane);
11350 }
11351
11352 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11353 .update_plane = intel_primary_plane_setplane,
11354 .disable_plane = intel_primary_plane_disable,
11355 .destroy = intel_plane_destroy,
11356 };
11357
11358 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11359 int pipe)
11360 {
11361 struct intel_plane *primary;
11362 const uint32_t *intel_primary_formats;
11363 int num_formats;
11364
11365 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11366 if (primary == NULL)
11367 return NULL;
11368
11369 primary->can_scale = false;
11370 primary->max_downscale = 1;
11371 primary->pipe = pipe;
11372 primary->plane = pipe;
11373 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11374 primary->plane = !pipe;
11375
11376 if (INTEL_INFO(dev)->gen <= 3) {
11377 intel_primary_formats = intel_primary_formats_gen2;
11378 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11379 } else {
11380 intel_primary_formats = intel_primary_formats_gen4;
11381 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11382 }
11383
11384 drm_universal_plane_init(dev, &primary->base, 0,
11385 &intel_primary_plane_funcs,
11386 intel_primary_formats, num_formats,
11387 DRM_PLANE_TYPE_PRIMARY);
11388 return &primary->base;
11389 }
11390
11391 static int
11392 intel_cursor_plane_disable(struct drm_plane *plane)
11393 {
11394 if (!plane->fb)
11395 return 0;
11396
11397 BUG_ON(!plane->crtc);
11398
11399 return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
11400 }
11401
11402 static int
11403 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
11404 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11405 unsigned int crtc_w, unsigned int crtc_h,
11406 uint32_t src_x, uint32_t src_y,
11407 uint32_t src_w, uint32_t src_h)
11408 {
11409 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11410 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11411 struct drm_i915_gem_object *obj = intel_fb->obj;
11412 struct drm_rect dest = {
11413 /* integer pixels */
11414 .x1 = crtc_x,
11415 .y1 = crtc_y,
11416 .x2 = crtc_x + crtc_w,
11417 .y2 = crtc_y + crtc_h,
11418 };
11419 struct drm_rect src = {
11420 /* 16.16 fixed point */
11421 .x1 = src_x,
11422 .y1 = src_y,
11423 .x2 = src_x + src_w,
11424 .y2 = src_y + src_h,
11425 };
11426 const struct drm_rect clip = {
11427 /* integer pixels */
11428 .x2 = intel_crtc->config.pipe_src_w,
11429 .y2 = intel_crtc->config.pipe_src_h,
11430 };
11431 bool visible;
11432 int ret;
11433
11434 ret = drm_plane_helper_check_update(plane, crtc, fb,
11435 &src, &dest, &clip,
11436 DRM_PLANE_HELPER_NO_SCALING,
11437 DRM_PLANE_HELPER_NO_SCALING,
11438 true, true, &visible);
11439 if (ret)
11440 return ret;
11441
11442 crtc->cursor_x = crtc_x;
11443 crtc->cursor_y = crtc_y;
11444 if (fb != crtc->cursor->fb) {
11445 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
11446 } else {
11447 intel_crtc_update_cursor(crtc, visible);
11448 return 0;
11449 }
11450 }
11451 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
11452 .update_plane = intel_cursor_plane_update,
11453 .disable_plane = intel_cursor_plane_disable,
11454 .destroy = intel_plane_destroy,
11455 };
11456
11457 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
11458 int pipe)
11459 {
11460 struct intel_plane *cursor;
11461
11462 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
11463 if (cursor == NULL)
11464 return NULL;
11465
11466 cursor->can_scale = false;
11467 cursor->max_downscale = 1;
11468 cursor->pipe = pipe;
11469 cursor->plane = pipe;
11470
11471 drm_universal_plane_init(dev, &cursor->base, 0,
11472 &intel_cursor_plane_funcs,
11473 intel_cursor_formats,
11474 ARRAY_SIZE(intel_cursor_formats),
11475 DRM_PLANE_TYPE_CURSOR);
11476 return &cursor->base;
11477 }
11478
11479 static void intel_crtc_init(struct drm_device *dev, int pipe)
11480 {
11481 struct drm_i915_private *dev_priv = dev->dev_private;
11482 struct intel_crtc *intel_crtc;
11483 struct drm_plane *primary = NULL;
11484 struct drm_plane *cursor = NULL;
11485 int i, ret;
11486
11487 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
11488 if (intel_crtc == NULL)
11489 return;
11490
11491 primary = intel_primary_plane_create(dev, pipe);
11492 if (!primary)
11493 goto fail;
11494
11495 cursor = intel_cursor_plane_create(dev, pipe);
11496 if (!cursor)
11497 goto fail;
11498
11499 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
11500 cursor, &intel_crtc_funcs);
11501 if (ret)
11502 goto fail;
11503
11504 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
11505 for (i = 0; i < 256; i++) {
11506 intel_crtc->lut_r[i] = i;
11507 intel_crtc->lut_g[i] = i;
11508 intel_crtc->lut_b[i] = i;
11509 }
11510
11511 /*
11512 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
11513 * is hooked to pipe B. Hence we want plane A feeding pipe B.
11514 */
11515 intel_crtc->pipe = pipe;
11516 intel_crtc->plane = pipe;
11517 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
11518 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
11519 intel_crtc->plane = !pipe;
11520 }
11521
11522 intel_crtc->cursor_base = ~0;
11523 intel_crtc->cursor_cntl = ~0;
11524
11525 init_waitqueue_head(&intel_crtc->vbl_wait);
11526
11527 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
11528 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
11529 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
11530 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
11531
11532 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
11533
11534 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
11535 return;
11536
11537 fail:
11538 if (primary)
11539 drm_plane_cleanup(primary);
11540 if (cursor)
11541 drm_plane_cleanup(cursor);
11542 kfree(intel_crtc);
11543 }
11544
11545 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
11546 {
11547 struct drm_encoder *encoder = connector->base.encoder;
11548 struct drm_device *dev = connector->base.dev;
11549
11550 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
11551
11552 if (!encoder)
11553 return INVALID_PIPE;
11554
11555 return to_intel_crtc(encoder->crtc)->pipe;
11556 }
11557
11558 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
11559 struct drm_file *file)
11560 {
11561 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
11562 struct drm_mode_object *drmmode_obj;
11563 struct intel_crtc *crtc;
11564
11565 if (!drm_core_check_feature(dev, DRIVER_MODESET))
11566 return -ENODEV;
11567
11568 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
11569 DRM_MODE_OBJECT_CRTC);
11570
11571 if (!drmmode_obj) {
11572 DRM_ERROR("no such CRTC id\n");
11573 return -ENOENT;
11574 }
11575
11576 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
11577 pipe_from_crtc_id->pipe = crtc->pipe;
11578
11579 return 0;
11580 }
11581
11582 static int intel_encoder_clones(struct intel_encoder *encoder)
11583 {
11584 struct drm_device *dev = encoder->base.dev;
11585 struct intel_encoder *source_encoder;
11586 int index_mask = 0;
11587 int entry = 0;
11588
11589 list_for_each_entry(source_encoder,
11590 &dev->mode_config.encoder_list, base.head) {
11591 if (encoders_cloneable(encoder, source_encoder))
11592 index_mask |= (1 << entry);
11593
11594 entry++;
11595 }
11596
11597 return index_mask;
11598 }
11599
11600 static bool has_edp_a(struct drm_device *dev)
11601 {
11602 struct drm_i915_private *dev_priv = dev->dev_private;
11603
11604 if (!IS_MOBILE(dev))
11605 return false;
11606
11607 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
11608 return false;
11609
11610 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
11611 return false;
11612
11613 return true;
11614 }
11615
11616 const char *intel_output_name(int output)
11617 {
11618 static const char *names[] = {
11619 [INTEL_OUTPUT_UNUSED] = "Unused",
11620 [INTEL_OUTPUT_ANALOG] = "Analog",
11621 [INTEL_OUTPUT_DVO] = "DVO",
11622 [INTEL_OUTPUT_SDVO] = "SDVO",
11623 [INTEL_OUTPUT_LVDS] = "LVDS",
11624 [INTEL_OUTPUT_TVOUT] = "TV",
11625 [INTEL_OUTPUT_HDMI] = "HDMI",
11626 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
11627 [INTEL_OUTPUT_EDP] = "eDP",
11628 [INTEL_OUTPUT_DSI] = "DSI",
11629 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
11630 };
11631
11632 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
11633 return "Invalid";
11634
11635 return names[output];
11636 }
11637
11638 static void intel_setup_outputs(struct drm_device *dev)
11639 {
11640 struct drm_i915_private *dev_priv = dev->dev_private;
11641 struct intel_encoder *encoder;
11642 bool dpd_is_edp = false;
11643
11644 intel_lvds_init(dev);
11645
11646 if (!IS_ULT(dev) && !IS_CHERRYVIEW(dev) && dev_priv->vbt.int_crt_support)
11647 intel_crt_init(dev);
11648
11649 if (HAS_DDI(dev)) {
11650 int found;
11651
11652 /* Haswell uses DDI functions to detect digital outputs */
11653 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
11654 /* DDI A only supports eDP */
11655 if (found)
11656 intel_ddi_init(dev, PORT_A);
11657
11658 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
11659 * register */
11660 found = I915_READ(SFUSE_STRAP);
11661
11662 if (found & SFUSE_STRAP_DDIB_DETECTED)
11663 intel_ddi_init(dev, PORT_B);
11664 if (found & SFUSE_STRAP_DDIC_DETECTED)
11665 intel_ddi_init(dev, PORT_C);
11666 if (found & SFUSE_STRAP_DDID_DETECTED)
11667 intel_ddi_init(dev, PORT_D);
11668 } else if (HAS_PCH_SPLIT(dev)) {
11669 int found;
11670 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
11671
11672 if (has_edp_a(dev))
11673 intel_dp_init(dev, DP_A, PORT_A);
11674
11675 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
11676 /* PCH SDVOB multiplex with HDMIB */
11677 found = intel_sdvo_init(dev, PCH_SDVOB, true);
11678 if (!found)
11679 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
11680 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
11681 intel_dp_init(dev, PCH_DP_B, PORT_B);
11682 }
11683
11684 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
11685 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
11686
11687 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
11688 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
11689
11690 if (I915_READ(PCH_DP_C) & DP_DETECTED)
11691 intel_dp_init(dev, PCH_DP_C, PORT_C);
11692
11693 if (I915_READ(PCH_DP_D) & DP_DETECTED)
11694 intel_dp_init(dev, PCH_DP_D, PORT_D);
11695 } else if (IS_VALLEYVIEW(dev)) {
11696 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
11697 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
11698 PORT_B);
11699 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
11700 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
11701 }
11702
11703 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
11704 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
11705 PORT_C);
11706 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
11707 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
11708 }
11709
11710 if (IS_CHERRYVIEW(dev)) {
11711 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) {
11712 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
11713 PORT_D);
11714 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
11715 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
11716 }
11717 }
11718
11719 intel_dsi_init(dev);
11720 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
11721 bool found = false;
11722
11723 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
11724 DRM_DEBUG_KMS("probing SDVOB\n");
11725 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
11726 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
11727 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
11728 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
11729 }
11730
11731 if (!found && SUPPORTS_INTEGRATED_DP(dev))
11732 intel_dp_init(dev, DP_B, PORT_B);
11733 }
11734
11735 /* Before G4X SDVOC doesn't have its own detect register */
11736
11737 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
11738 DRM_DEBUG_KMS("probing SDVOC\n");
11739 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
11740 }
11741
11742 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
11743
11744 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
11745 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
11746 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
11747 }
11748 if (SUPPORTS_INTEGRATED_DP(dev))
11749 intel_dp_init(dev, DP_C, PORT_C);
11750 }
11751
11752 if (SUPPORTS_INTEGRATED_DP(dev) &&
11753 (I915_READ(DP_D) & DP_DETECTED))
11754 intel_dp_init(dev, DP_D, PORT_D);
11755 } else if (IS_GEN2(dev))
11756 intel_dvo_init(dev);
11757
11758 if (SUPPORTS_TV(dev))
11759 intel_tv_init(dev);
11760
11761 intel_edp_psr_init(dev);
11762
11763 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
11764 encoder->base.possible_crtcs = encoder->crtc_mask;
11765 encoder->base.possible_clones =
11766 intel_encoder_clones(encoder);
11767 }
11768
11769 intel_init_pch_refclk(dev);
11770
11771 drm_helper_move_panel_connectors_to_head(dev);
11772 }
11773
11774 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
11775 {
11776 struct drm_device *dev = fb->dev;
11777 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11778
11779 drm_framebuffer_cleanup(fb);
11780 mutex_lock(&dev->struct_mutex);
11781 WARN_ON(!intel_fb->obj->framebuffer_references--);
11782 drm_gem_object_unreference(&intel_fb->obj->base);
11783 mutex_unlock(&dev->struct_mutex);
11784 kfree(intel_fb);
11785 }
11786
11787 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
11788 struct drm_file *file,
11789 unsigned int *handle)
11790 {
11791 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11792 struct drm_i915_gem_object *obj = intel_fb->obj;
11793
11794 return drm_gem_handle_create(file, &obj->base, handle);
11795 }
11796
11797 static const struct drm_framebuffer_funcs intel_fb_funcs = {
11798 .destroy = intel_user_framebuffer_destroy,
11799 .create_handle = intel_user_framebuffer_create_handle,
11800 };
11801
11802 static int intel_framebuffer_init(struct drm_device *dev,
11803 struct intel_framebuffer *intel_fb,
11804 struct drm_mode_fb_cmd2 *mode_cmd,
11805 struct drm_i915_gem_object *obj)
11806 {
11807 int aligned_height;
11808 int pitch_limit;
11809 int ret;
11810
11811 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
11812
11813 if (obj->tiling_mode == I915_TILING_Y) {
11814 DRM_DEBUG("hardware does not support tiling Y\n");
11815 return -EINVAL;
11816 }
11817
11818 if (mode_cmd->pitches[0] & 63) {
11819 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
11820 mode_cmd->pitches[0]);
11821 return -EINVAL;
11822 }
11823
11824 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
11825 pitch_limit = 32*1024;
11826 } else if (INTEL_INFO(dev)->gen >= 4) {
11827 if (obj->tiling_mode)
11828 pitch_limit = 16*1024;
11829 else
11830 pitch_limit = 32*1024;
11831 } else if (INTEL_INFO(dev)->gen >= 3) {
11832 if (obj->tiling_mode)
11833 pitch_limit = 8*1024;
11834 else
11835 pitch_limit = 16*1024;
11836 } else
11837 /* XXX DSPC is limited to 4k tiled */
11838 pitch_limit = 8*1024;
11839
11840 if (mode_cmd->pitches[0] > pitch_limit) {
11841 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
11842 obj->tiling_mode ? "tiled" : "linear",
11843 mode_cmd->pitches[0], pitch_limit);
11844 return -EINVAL;
11845 }
11846
11847 if (obj->tiling_mode != I915_TILING_NONE &&
11848 mode_cmd->pitches[0] != obj->stride) {
11849 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
11850 mode_cmd->pitches[0], obj->stride);
11851 return -EINVAL;
11852 }
11853
11854 /* Reject formats not supported by any plane early. */
11855 switch (mode_cmd->pixel_format) {
11856 case DRM_FORMAT_C8:
11857 case DRM_FORMAT_RGB565:
11858 case DRM_FORMAT_XRGB8888:
11859 case DRM_FORMAT_ARGB8888:
11860 break;
11861 case DRM_FORMAT_XRGB1555:
11862 case DRM_FORMAT_ARGB1555:
11863 if (INTEL_INFO(dev)->gen > 3) {
11864 DRM_DEBUG("unsupported pixel format: %s\n",
11865 drm_get_format_name(mode_cmd->pixel_format));
11866 return -EINVAL;
11867 }
11868 break;
11869 case DRM_FORMAT_XBGR8888:
11870 case DRM_FORMAT_ABGR8888:
11871 case DRM_FORMAT_XRGB2101010:
11872 case DRM_FORMAT_ARGB2101010:
11873 case DRM_FORMAT_XBGR2101010:
11874 case DRM_FORMAT_ABGR2101010:
11875 if (INTEL_INFO(dev)->gen < 4) {
11876 DRM_DEBUG("unsupported pixel format: %s\n",
11877 drm_get_format_name(mode_cmd->pixel_format));
11878 return -EINVAL;
11879 }
11880 break;
11881 case DRM_FORMAT_YUYV:
11882 case DRM_FORMAT_UYVY:
11883 case DRM_FORMAT_YVYU:
11884 case DRM_FORMAT_VYUY:
11885 if (INTEL_INFO(dev)->gen < 5) {
11886 DRM_DEBUG("unsupported pixel format: %s\n",
11887 drm_get_format_name(mode_cmd->pixel_format));
11888 return -EINVAL;
11889 }
11890 break;
11891 default:
11892 DRM_DEBUG("unsupported pixel format: %s\n",
11893 drm_get_format_name(mode_cmd->pixel_format));
11894 return -EINVAL;
11895 }
11896
11897 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
11898 if (mode_cmd->offsets[0] != 0)
11899 return -EINVAL;
11900
11901 aligned_height = intel_align_height(dev, mode_cmd->height,
11902 obj->tiling_mode);
11903 /* FIXME drm helper for size checks (especially planar formats)? */
11904 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
11905 return -EINVAL;
11906
11907 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
11908 intel_fb->obj = obj;
11909 intel_fb->obj->framebuffer_references++;
11910
11911 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
11912 if (ret) {
11913 DRM_ERROR("framebuffer init failed %d\n", ret);
11914 return ret;
11915 }
11916
11917 return 0;
11918 }
11919
11920 static struct drm_framebuffer *
11921 intel_user_framebuffer_create(struct drm_device *dev,
11922 struct drm_file *filp,
11923 struct drm_mode_fb_cmd2 *mode_cmd)
11924 {
11925 struct drm_i915_gem_object *obj;
11926
11927 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
11928 mode_cmd->handles[0]));
11929 if (&obj->base == NULL)
11930 return ERR_PTR(-ENOENT);
11931
11932 return intel_framebuffer_create(dev, mode_cmd, obj);
11933 }
11934
11935 #ifndef CONFIG_DRM_I915_FBDEV
11936 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
11937 {
11938 }
11939 #endif
11940
11941 static const struct drm_mode_config_funcs intel_mode_funcs = {
11942 .fb_create = intel_user_framebuffer_create,
11943 .output_poll_changed = intel_fbdev_output_poll_changed,
11944 };
11945
11946 /* Set up chip specific display functions */
11947 static void intel_init_display(struct drm_device *dev)
11948 {
11949 struct drm_i915_private *dev_priv = dev->dev_private;
11950
11951 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
11952 dev_priv->display.find_dpll = g4x_find_best_dpll;
11953 else if (IS_CHERRYVIEW(dev))
11954 dev_priv->display.find_dpll = chv_find_best_dpll;
11955 else if (IS_VALLEYVIEW(dev))
11956 dev_priv->display.find_dpll = vlv_find_best_dpll;
11957 else if (IS_PINEVIEW(dev))
11958 dev_priv->display.find_dpll = pnv_find_best_dpll;
11959 else
11960 dev_priv->display.find_dpll = i9xx_find_best_dpll;
11961
11962 if (HAS_DDI(dev)) {
11963 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
11964 dev_priv->display.get_plane_config = ironlake_get_plane_config;
11965 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
11966 dev_priv->display.crtc_enable = haswell_crtc_enable;
11967 dev_priv->display.crtc_disable = haswell_crtc_disable;
11968 dev_priv->display.off = haswell_crtc_off;
11969 dev_priv->display.update_primary_plane =
11970 ironlake_update_primary_plane;
11971 } else if (HAS_PCH_SPLIT(dev)) {
11972 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
11973 dev_priv->display.get_plane_config = ironlake_get_plane_config;
11974 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
11975 dev_priv->display.crtc_enable = ironlake_crtc_enable;
11976 dev_priv->display.crtc_disable = ironlake_crtc_disable;
11977 dev_priv->display.off = ironlake_crtc_off;
11978 dev_priv->display.update_primary_plane =
11979 ironlake_update_primary_plane;
11980 } else if (IS_VALLEYVIEW(dev)) {
11981 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11982 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11983 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11984 dev_priv->display.crtc_enable = valleyview_crtc_enable;
11985 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11986 dev_priv->display.off = i9xx_crtc_off;
11987 dev_priv->display.update_primary_plane =
11988 i9xx_update_primary_plane;
11989 } else {
11990 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11991 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11992 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11993 dev_priv->display.crtc_enable = i9xx_crtc_enable;
11994 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11995 dev_priv->display.off = i9xx_crtc_off;
11996 dev_priv->display.update_primary_plane =
11997 i9xx_update_primary_plane;
11998 }
11999
12000 /* Returns the core display clock speed */
12001 if (IS_VALLEYVIEW(dev))
12002 dev_priv->display.get_display_clock_speed =
12003 valleyview_get_display_clock_speed;
12004 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12005 dev_priv->display.get_display_clock_speed =
12006 i945_get_display_clock_speed;
12007 else if (IS_I915G(dev))
12008 dev_priv->display.get_display_clock_speed =
12009 i915_get_display_clock_speed;
12010 else if (IS_I945GM(dev) || IS_845G(dev))
12011 dev_priv->display.get_display_clock_speed =
12012 i9xx_misc_get_display_clock_speed;
12013 else if (IS_PINEVIEW(dev))
12014 dev_priv->display.get_display_clock_speed =
12015 pnv_get_display_clock_speed;
12016 else if (IS_I915GM(dev))
12017 dev_priv->display.get_display_clock_speed =
12018 i915gm_get_display_clock_speed;
12019 else if (IS_I865G(dev))
12020 dev_priv->display.get_display_clock_speed =
12021 i865_get_display_clock_speed;
12022 else if (IS_I85X(dev))
12023 dev_priv->display.get_display_clock_speed =
12024 i855_get_display_clock_speed;
12025 else /* 852, 830 */
12026 dev_priv->display.get_display_clock_speed =
12027 i830_get_display_clock_speed;
12028
12029 if (HAS_PCH_SPLIT(dev)) {
12030 if (IS_GEN5(dev)) {
12031 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12032 dev_priv->display.write_eld = ironlake_write_eld;
12033 } else if (IS_GEN6(dev)) {
12034 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12035 dev_priv->display.write_eld = ironlake_write_eld;
12036 dev_priv->display.modeset_global_resources =
12037 snb_modeset_global_resources;
12038 } else if (IS_IVYBRIDGE(dev)) {
12039 /* FIXME: detect B0+ stepping and use auto training */
12040 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12041 dev_priv->display.write_eld = ironlake_write_eld;
12042 dev_priv->display.modeset_global_resources =
12043 ivb_modeset_global_resources;
12044 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
12045 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12046 dev_priv->display.write_eld = haswell_write_eld;
12047 dev_priv->display.modeset_global_resources =
12048 haswell_modeset_global_resources;
12049 }
12050 } else if (IS_G4X(dev)) {
12051 dev_priv->display.write_eld = g4x_write_eld;
12052 } else if (IS_VALLEYVIEW(dev)) {
12053 dev_priv->display.modeset_global_resources =
12054 valleyview_modeset_global_resources;
12055 dev_priv->display.write_eld = ironlake_write_eld;
12056 }
12057
12058 /* Default just returns -ENODEV to indicate unsupported */
12059 dev_priv->display.queue_flip = intel_default_queue_flip;
12060
12061 switch (INTEL_INFO(dev)->gen) {
12062 case 2:
12063 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12064 break;
12065
12066 case 3:
12067 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12068 break;
12069
12070 case 4:
12071 case 5:
12072 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12073 break;
12074
12075 case 6:
12076 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12077 break;
12078 case 7:
12079 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12080 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12081 break;
12082 }
12083
12084 intel_panel_init_backlight_funcs(dev);
12085 }
12086
12087 /*
12088 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12089 * resume, or other times. This quirk makes sure that's the case for
12090 * affected systems.
12091 */
12092 static void quirk_pipea_force(struct drm_device *dev)
12093 {
12094 struct drm_i915_private *dev_priv = dev->dev_private;
12095
12096 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12097 DRM_INFO("applying pipe a force quirk\n");
12098 }
12099
12100 /*
12101 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12102 */
12103 static void quirk_ssc_force_disable(struct drm_device *dev)
12104 {
12105 struct drm_i915_private *dev_priv = dev->dev_private;
12106 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12107 DRM_INFO("applying lvds SSC disable quirk\n");
12108 }
12109
12110 /*
12111 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12112 * brightness value
12113 */
12114 static void quirk_invert_brightness(struct drm_device *dev)
12115 {
12116 struct drm_i915_private *dev_priv = dev->dev_private;
12117 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12118 DRM_INFO("applying inverted panel brightness quirk\n");
12119 }
12120
12121 struct intel_quirk {
12122 int device;
12123 int subsystem_vendor;
12124 int subsystem_device;
12125 void (*hook)(struct drm_device *dev);
12126 };
12127
12128 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12129 struct intel_dmi_quirk {
12130 void (*hook)(struct drm_device *dev);
12131 const struct dmi_system_id (*dmi_id_list)[];
12132 };
12133
12134 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12135 {
12136 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12137 return 1;
12138 }
12139
12140 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12141 {
12142 .dmi_id_list = &(const struct dmi_system_id[]) {
12143 {
12144 .callback = intel_dmi_reverse_brightness,
12145 .ident = "NCR Corporation",
12146 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12147 DMI_MATCH(DMI_PRODUCT_NAME, ""),
12148 },
12149 },
12150 { } /* terminating entry */
12151 },
12152 .hook = quirk_invert_brightness,
12153 },
12154 };
12155
12156 static struct intel_quirk intel_quirks[] = {
12157 /* HP Mini needs pipe A force quirk (LP: #322104) */
12158 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12159
12160 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12161 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12162
12163 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12164 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12165
12166 /* Lenovo U160 cannot use SSC on LVDS */
12167 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12168
12169 /* Sony Vaio Y cannot use SSC on LVDS */
12170 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12171
12172 /* Acer Aspire 5734Z must invert backlight brightness */
12173 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12174
12175 /* Acer/eMachines G725 */
12176 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12177
12178 /* Acer/eMachines e725 */
12179 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12180
12181 /* Acer/Packard Bell NCL20 */
12182 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12183
12184 /* Acer Aspire 4736Z */
12185 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12186
12187 /* Acer Aspire 5336 */
12188 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12189 };
12190
12191 static void intel_init_quirks(struct drm_device *dev)
12192 {
12193 struct pci_dev *d = dev->pdev;
12194 int i;
12195
12196 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12197 struct intel_quirk *q = &intel_quirks[i];
12198
12199 if (d->device == q->device &&
12200 (d->subsystem_vendor == q->subsystem_vendor ||
12201 q->subsystem_vendor == PCI_ANY_ID) &&
12202 (d->subsystem_device == q->subsystem_device ||
12203 q->subsystem_device == PCI_ANY_ID))
12204 q->hook(dev);
12205 }
12206 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12207 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12208 intel_dmi_quirks[i].hook(dev);
12209 }
12210 }
12211
12212 /* Disable the VGA plane that we never use */
12213 static void i915_disable_vga(struct drm_device *dev)
12214 {
12215 struct drm_i915_private *dev_priv = dev->dev_private;
12216 u8 sr1;
12217 u32 vga_reg = i915_vgacntrl_reg(dev);
12218
12219 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12220 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12221 outb(SR01, VGA_SR_INDEX);
12222 sr1 = inb(VGA_SR_DATA);
12223 outb(sr1 | 1<<5, VGA_SR_DATA);
12224 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12225 udelay(300);
12226
12227 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
12228 POSTING_READ(vga_reg);
12229 }
12230
12231 void intel_modeset_init_hw(struct drm_device *dev)
12232 {
12233 intel_prepare_ddi(dev);
12234
12235 intel_init_clock_gating(dev);
12236
12237 intel_reset_dpio(dev);
12238
12239 intel_enable_gt_powersave(dev);
12240 }
12241
12242 void intel_modeset_suspend_hw(struct drm_device *dev)
12243 {
12244 intel_suspend_hw(dev);
12245 }
12246
12247 void intel_modeset_init(struct drm_device *dev)
12248 {
12249 struct drm_i915_private *dev_priv = dev->dev_private;
12250 int sprite, ret;
12251 enum pipe pipe;
12252 struct intel_crtc *crtc;
12253
12254 drm_mode_config_init(dev);
12255
12256 dev->mode_config.min_width = 0;
12257 dev->mode_config.min_height = 0;
12258
12259 dev->mode_config.preferred_depth = 24;
12260 dev->mode_config.prefer_shadow = 1;
12261
12262 dev->mode_config.funcs = &intel_mode_funcs;
12263
12264 intel_init_quirks(dev);
12265
12266 intel_init_pm(dev);
12267
12268 if (INTEL_INFO(dev)->num_pipes == 0)
12269 return;
12270
12271 intel_init_display(dev);
12272
12273 if (IS_GEN2(dev)) {
12274 dev->mode_config.max_width = 2048;
12275 dev->mode_config.max_height = 2048;
12276 } else if (IS_GEN3(dev)) {
12277 dev->mode_config.max_width = 4096;
12278 dev->mode_config.max_height = 4096;
12279 } else {
12280 dev->mode_config.max_width = 8192;
12281 dev->mode_config.max_height = 8192;
12282 }
12283
12284 if (IS_GEN2(dev)) {
12285 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12286 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12287 } else {
12288 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
12289 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
12290 }
12291
12292 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
12293
12294 DRM_DEBUG_KMS("%d display pipe%s available.\n",
12295 INTEL_INFO(dev)->num_pipes,
12296 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
12297
12298 for_each_pipe(pipe) {
12299 intel_crtc_init(dev, pipe);
12300 for_each_sprite(pipe, sprite) {
12301 ret = intel_plane_init(dev, pipe, sprite);
12302 if (ret)
12303 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12304 pipe_name(pipe), sprite_name(pipe, sprite), ret);
12305 }
12306 }
12307
12308 intel_init_dpio(dev);
12309 intel_reset_dpio(dev);
12310
12311 intel_cpu_pll_init(dev);
12312 intel_shared_dpll_init(dev);
12313
12314 /* Just disable it once at startup */
12315 i915_disable_vga(dev);
12316 intel_setup_outputs(dev);
12317
12318 /* Just in case the BIOS is doing something questionable. */
12319 intel_disable_fbc(dev);
12320
12321 drm_modeset_lock_all(dev);
12322 intel_modeset_setup_hw_state(dev, false);
12323 drm_modeset_unlock_all(dev);
12324
12325 for_each_intel_crtc(dev, crtc) {
12326 if (!crtc->active)
12327 continue;
12328
12329 /*
12330 * Note that reserving the BIOS fb up front prevents us
12331 * from stuffing other stolen allocations like the ring
12332 * on top. This prevents some ugliness at boot time, and
12333 * can even allow for smooth boot transitions if the BIOS
12334 * fb is large enough for the active pipe configuration.
12335 */
12336 if (dev_priv->display.get_plane_config) {
12337 dev_priv->display.get_plane_config(crtc,
12338 &crtc->plane_config);
12339 /*
12340 * If the fb is shared between multiple heads, we'll
12341 * just get the first one.
12342 */
12343 intel_find_plane_obj(crtc, &crtc->plane_config);
12344 }
12345 }
12346 }
12347
12348 static void intel_enable_pipe_a(struct drm_device *dev)
12349 {
12350 struct intel_connector *connector;
12351 struct drm_connector *crt = NULL;
12352 struct intel_load_detect_pipe load_detect_temp;
12353 struct drm_modeset_acquire_ctx ctx;
12354
12355 /* We can't just switch on the pipe A, we need to set things up with a
12356 * proper mode and output configuration. As a gross hack, enable pipe A
12357 * by enabling the load detect pipe once. */
12358 list_for_each_entry(connector,
12359 &dev->mode_config.connector_list,
12360 base.head) {
12361 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
12362 crt = &connector->base;
12363 break;
12364 }
12365 }
12366
12367 if (!crt)
12368 return;
12369
12370 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, &ctx))
12371 intel_release_load_detect_pipe(crt, &load_detect_temp, &ctx);
12372
12373
12374 }
12375
12376 static bool
12377 intel_check_plane_mapping(struct intel_crtc *crtc)
12378 {
12379 struct drm_device *dev = crtc->base.dev;
12380 struct drm_i915_private *dev_priv = dev->dev_private;
12381 u32 reg, val;
12382
12383 if (INTEL_INFO(dev)->num_pipes == 1)
12384 return true;
12385
12386 reg = DSPCNTR(!crtc->plane);
12387 val = I915_READ(reg);
12388
12389 if ((val & DISPLAY_PLANE_ENABLE) &&
12390 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
12391 return false;
12392
12393 return true;
12394 }
12395
12396 static void intel_sanitize_crtc(struct intel_crtc *crtc)
12397 {
12398 struct drm_device *dev = crtc->base.dev;
12399 struct drm_i915_private *dev_priv = dev->dev_private;
12400 u32 reg;
12401
12402 /* Clear any frame start delays used for debugging left by the BIOS */
12403 reg = PIPECONF(crtc->config.cpu_transcoder);
12404 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
12405
12406 /* restore vblank interrupts to correct state */
12407 if (crtc->active)
12408 drm_vblank_on(dev, crtc->pipe);
12409 else
12410 drm_vblank_off(dev, crtc->pipe);
12411
12412 /* We need to sanitize the plane -> pipe mapping first because this will
12413 * disable the crtc (and hence change the state) if it is wrong. Note
12414 * that gen4+ has a fixed plane -> pipe mapping. */
12415 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
12416 struct intel_connector *connector;
12417 bool plane;
12418
12419 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
12420 crtc->base.base.id);
12421
12422 /* Pipe has the wrong plane attached and the plane is active.
12423 * Temporarily change the plane mapping and disable everything
12424 * ... */
12425 plane = crtc->plane;
12426 crtc->plane = !plane;
12427 dev_priv->display.crtc_disable(&crtc->base);
12428 crtc->plane = plane;
12429
12430 /* ... and break all links. */
12431 list_for_each_entry(connector, &dev->mode_config.connector_list,
12432 base.head) {
12433 if (connector->encoder->base.crtc != &crtc->base)
12434 continue;
12435
12436 connector->base.dpms = DRM_MODE_DPMS_OFF;
12437 connector->base.encoder = NULL;
12438 }
12439 /* multiple connectors may have the same encoder:
12440 * handle them and break crtc link separately */
12441 list_for_each_entry(connector, &dev->mode_config.connector_list,
12442 base.head)
12443 if (connector->encoder->base.crtc == &crtc->base) {
12444 connector->encoder->base.crtc = NULL;
12445 connector->encoder->connectors_active = false;
12446 }
12447
12448 WARN_ON(crtc->active);
12449 crtc->base.enabled = false;
12450 }
12451
12452 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
12453 crtc->pipe == PIPE_A && !crtc->active) {
12454 /* BIOS forgot to enable pipe A, this mostly happens after
12455 * resume. Force-enable the pipe to fix this, the update_dpms
12456 * call below we restore the pipe to the right state, but leave
12457 * the required bits on. */
12458 intel_enable_pipe_a(dev);
12459 }
12460
12461 /* Adjust the state of the output pipe according to whether we
12462 * have active connectors/encoders. */
12463 intel_crtc_update_dpms(&crtc->base);
12464
12465 if (crtc->active != crtc->base.enabled) {
12466 struct intel_encoder *encoder;
12467
12468 /* This can happen either due to bugs in the get_hw_state
12469 * functions or because the pipe is force-enabled due to the
12470 * pipe A quirk. */
12471 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
12472 crtc->base.base.id,
12473 crtc->base.enabled ? "enabled" : "disabled",
12474 crtc->active ? "enabled" : "disabled");
12475
12476 crtc->base.enabled = crtc->active;
12477
12478 /* Because we only establish the connector -> encoder ->
12479 * crtc links if something is active, this means the
12480 * crtc is now deactivated. Break the links. connector
12481 * -> encoder links are only establish when things are
12482 * actually up, hence no need to break them. */
12483 WARN_ON(crtc->active);
12484
12485 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
12486 WARN_ON(encoder->connectors_active);
12487 encoder->base.crtc = NULL;
12488 }
12489 }
12490
12491 if (crtc->active || IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen < 5) {
12492 /*
12493 * We start out with underrun reporting disabled to avoid races.
12494 * For correct bookkeeping mark this on active crtcs.
12495 *
12496 * Also on gmch platforms we dont have any hardware bits to
12497 * disable the underrun reporting. Which means we need to start
12498 * out with underrun reporting disabled also on inactive pipes,
12499 * since otherwise we'll complain about the garbage we read when
12500 * e.g. coming up after runtime pm.
12501 *
12502 * No protection against concurrent access is required - at
12503 * worst a fifo underrun happens which also sets this to false.
12504 */
12505 crtc->cpu_fifo_underrun_disabled = true;
12506 crtc->pch_fifo_underrun_disabled = true;
12507
12508 update_scanline_offset(crtc);
12509 }
12510 }
12511
12512 static void intel_sanitize_encoder(struct intel_encoder *encoder)
12513 {
12514 struct intel_connector *connector;
12515 struct drm_device *dev = encoder->base.dev;
12516
12517 /* We need to check both for a crtc link (meaning that the
12518 * encoder is active and trying to read from a pipe) and the
12519 * pipe itself being active. */
12520 bool has_active_crtc = encoder->base.crtc &&
12521 to_intel_crtc(encoder->base.crtc)->active;
12522
12523 if (encoder->connectors_active && !has_active_crtc) {
12524 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
12525 encoder->base.base.id,
12526 encoder->base.name);
12527
12528 /* Connector is active, but has no active pipe. This is
12529 * fallout from our resume register restoring. Disable
12530 * the encoder manually again. */
12531 if (encoder->base.crtc) {
12532 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
12533 encoder->base.base.id,
12534 encoder->base.name);
12535 encoder->disable(encoder);
12536 }
12537 encoder->base.crtc = NULL;
12538 encoder->connectors_active = false;
12539
12540 /* Inconsistent output/port/pipe state happens presumably due to
12541 * a bug in one of the get_hw_state functions. Or someplace else
12542 * in our code, like the register restore mess on resume. Clamp
12543 * things to off as a safer default. */
12544 list_for_each_entry(connector,
12545 &dev->mode_config.connector_list,
12546 base.head) {
12547 if (connector->encoder != encoder)
12548 continue;
12549 connector->base.dpms = DRM_MODE_DPMS_OFF;
12550 connector->base.encoder = NULL;
12551 }
12552 }
12553 /* Enabled encoders without active connectors will be fixed in
12554 * the crtc fixup. */
12555 }
12556
12557 void i915_redisable_vga_power_on(struct drm_device *dev)
12558 {
12559 struct drm_i915_private *dev_priv = dev->dev_private;
12560 u32 vga_reg = i915_vgacntrl_reg(dev);
12561
12562 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
12563 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
12564 i915_disable_vga(dev);
12565 }
12566 }
12567
12568 void i915_redisable_vga(struct drm_device *dev)
12569 {
12570 struct drm_i915_private *dev_priv = dev->dev_private;
12571
12572 /* This function can be called both from intel_modeset_setup_hw_state or
12573 * at a very early point in our resume sequence, where the power well
12574 * structures are not yet restored. Since this function is at a very
12575 * paranoid "someone might have enabled VGA while we were not looking"
12576 * level, just check if the power well is enabled instead of trying to
12577 * follow the "don't touch the power well if we don't need it" policy
12578 * the rest of the driver uses. */
12579 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
12580 return;
12581
12582 i915_redisable_vga_power_on(dev);
12583 }
12584
12585 static bool primary_get_hw_state(struct intel_crtc *crtc)
12586 {
12587 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
12588
12589 if (!crtc->active)
12590 return false;
12591
12592 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
12593 }
12594
12595 static void intel_modeset_readout_hw_state(struct drm_device *dev)
12596 {
12597 struct drm_i915_private *dev_priv = dev->dev_private;
12598 enum pipe pipe;
12599 struct intel_crtc *crtc;
12600 struct intel_encoder *encoder;
12601 struct intel_connector *connector;
12602 int i;
12603
12604 for_each_intel_crtc(dev, crtc) {
12605 memset(&crtc->config, 0, sizeof(crtc->config));
12606
12607 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
12608
12609 crtc->active = dev_priv->display.get_pipe_config(crtc,
12610 &crtc->config);
12611
12612 crtc->base.enabled = crtc->active;
12613 crtc->primary_enabled = primary_get_hw_state(crtc);
12614
12615 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
12616 crtc->base.base.id,
12617 crtc->active ? "enabled" : "disabled");
12618 }
12619
12620 /* FIXME: Smash this into the new shared dpll infrastructure. */
12621 if (HAS_DDI(dev))
12622 intel_ddi_setup_hw_pll_state(dev);
12623
12624 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12625 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12626
12627 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
12628 pll->active = 0;
12629 for_each_intel_crtc(dev, crtc) {
12630 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12631 pll->active++;
12632 }
12633 pll->refcount = pll->active;
12634
12635 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
12636 pll->name, pll->refcount, pll->on);
12637 }
12638
12639 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
12640 base.head) {
12641 pipe = 0;
12642
12643 if (encoder->get_hw_state(encoder, &pipe)) {
12644 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
12645 encoder->base.crtc = &crtc->base;
12646 encoder->get_config(encoder, &crtc->config);
12647 } else {
12648 encoder->base.crtc = NULL;
12649 }
12650
12651 encoder->connectors_active = false;
12652 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
12653 encoder->base.base.id,
12654 encoder->base.name,
12655 encoder->base.crtc ? "enabled" : "disabled",
12656 pipe_name(pipe));
12657 }
12658
12659 list_for_each_entry(connector, &dev->mode_config.connector_list,
12660 base.head) {
12661 if (connector->get_hw_state(connector)) {
12662 connector->base.dpms = DRM_MODE_DPMS_ON;
12663 connector->encoder->connectors_active = true;
12664 connector->base.encoder = &connector->encoder->base;
12665 } else {
12666 connector->base.dpms = DRM_MODE_DPMS_OFF;
12667 connector->base.encoder = NULL;
12668 }
12669 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
12670 connector->base.base.id,
12671 connector->base.name,
12672 connector->base.encoder ? "enabled" : "disabled");
12673 }
12674 }
12675
12676 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
12677 * and i915 state tracking structures. */
12678 void intel_modeset_setup_hw_state(struct drm_device *dev,
12679 bool force_restore)
12680 {
12681 struct drm_i915_private *dev_priv = dev->dev_private;
12682 enum pipe pipe;
12683 struct intel_crtc *crtc;
12684 struct intel_encoder *encoder;
12685 int i;
12686
12687 intel_modeset_readout_hw_state(dev);
12688
12689 /*
12690 * Now that we have the config, copy it to each CRTC struct
12691 * Note that this could go away if we move to using crtc_config
12692 * checking everywhere.
12693 */
12694 for_each_intel_crtc(dev, crtc) {
12695 if (crtc->active && i915.fastboot) {
12696 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
12697 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
12698 crtc->base.base.id);
12699 drm_mode_debug_printmodeline(&crtc->base.mode);
12700 }
12701 }
12702
12703 /* HW state is read out, now we need to sanitize this mess. */
12704 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
12705 base.head) {
12706 intel_sanitize_encoder(encoder);
12707 }
12708
12709 for_each_pipe(pipe) {
12710 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
12711 intel_sanitize_crtc(crtc);
12712 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
12713 }
12714
12715 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12716 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12717
12718 if (!pll->on || pll->active)
12719 continue;
12720
12721 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
12722
12723 pll->disable(dev_priv, pll);
12724 pll->on = false;
12725 }
12726
12727 if (HAS_PCH_SPLIT(dev))
12728 ilk_wm_get_hw_state(dev);
12729
12730 if (force_restore) {
12731 i915_redisable_vga(dev);
12732
12733 /*
12734 * We need to use raw interfaces for restoring state to avoid
12735 * checking (bogus) intermediate states.
12736 */
12737 for_each_pipe(pipe) {
12738 struct drm_crtc *crtc =
12739 dev_priv->pipe_to_crtc_mapping[pipe];
12740
12741 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
12742 crtc->primary->fb);
12743 }
12744 } else {
12745 intel_modeset_update_staged_output_state(dev);
12746 }
12747
12748 intel_modeset_check_state(dev);
12749 }
12750
12751 void intel_modeset_gem_init(struct drm_device *dev)
12752 {
12753 struct drm_crtc *c;
12754 struct intel_framebuffer *fb;
12755
12756 mutex_lock(&dev->struct_mutex);
12757 intel_init_gt_powersave(dev);
12758 mutex_unlock(&dev->struct_mutex);
12759
12760 intel_modeset_init_hw(dev);
12761
12762 intel_setup_overlay(dev);
12763
12764 /*
12765 * Make sure any fbs we allocated at startup are properly
12766 * pinned & fenced. When we do the allocation it's too early
12767 * for this.
12768 */
12769 mutex_lock(&dev->struct_mutex);
12770 for_each_crtc(dev, c) {
12771 if (!c->primary->fb)
12772 continue;
12773
12774 fb = to_intel_framebuffer(c->primary->fb);
12775 if (intel_pin_and_fence_fb_obj(dev, fb->obj, NULL)) {
12776 DRM_ERROR("failed to pin boot fb on pipe %d\n",
12777 to_intel_crtc(c)->pipe);
12778 drm_framebuffer_unreference(c->primary->fb);
12779 c->primary->fb = NULL;
12780 }
12781 }
12782 mutex_unlock(&dev->struct_mutex);
12783 }
12784
12785 void intel_connector_unregister(struct intel_connector *intel_connector)
12786 {
12787 struct drm_connector *connector = &intel_connector->base;
12788
12789 intel_panel_destroy_backlight(connector);
12790 drm_sysfs_connector_remove(connector);
12791 }
12792
12793 void intel_modeset_cleanup(struct drm_device *dev)
12794 {
12795 struct drm_i915_private *dev_priv = dev->dev_private;
12796 struct drm_connector *connector;
12797
12798 /*
12799 * Interrupts and polling as the first thing to avoid creating havoc.
12800 * Too much stuff here (turning of rps, connectors, ...) would
12801 * experience fancy races otherwise.
12802 */
12803 drm_irq_uninstall(dev);
12804 cancel_work_sync(&dev_priv->hotplug_work);
12805 /*
12806 * Due to the hpd irq storm handling the hotplug work can re-arm the
12807 * poll handlers. Hence disable polling after hpd handling is shut down.
12808 */
12809 drm_kms_helper_poll_fini(dev);
12810
12811 mutex_lock(&dev->struct_mutex);
12812
12813 intel_unregister_dsm_handler();
12814
12815 intel_disable_fbc(dev);
12816
12817 intel_disable_gt_powersave(dev);
12818
12819 ironlake_teardown_rc6(dev);
12820
12821 mutex_unlock(&dev->struct_mutex);
12822
12823 /* flush any delayed tasks or pending work */
12824 flush_scheduled_work();
12825
12826 /* destroy the backlight and sysfs files before encoders/connectors */
12827 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12828 struct intel_connector *intel_connector;
12829
12830 intel_connector = to_intel_connector(connector);
12831 intel_connector->unregister(intel_connector);
12832 }
12833
12834 drm_mode_config_cleanup(dev);
12835
12836 intel_cleanup_overlay(dev);
12837
12838 mutex_lock(&dev->struct_mutex);
12839 intel_cleanup_gt_powersave(dev);
12840 mutex_unlock(&dev->struct_mutex);
12841 }
12842
12843 /*
12844 * Return which encoder is currently attached for connector.
12845 */
12846 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
12847 {
12848 return &intel_attached_encoder(connector)->base;
12849 }
12850
12851 void intel_connector_attach_encoder(struct intel_connector *connector,
12852 struct intel_encoder *encoder)
12853 {
12854 connector->encoder = encoder;
12855 drm_mode_connector_attach_encoder(&connector->base,
12856 &encoder->base);
12857 }
12858
12859 /*
12860 * set vga decode state - true == enable VGA decode
12861 */
12862 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
12863 {
12864 struct drm_i915_private *dev_priv = dev->dev_private;
12865 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
12866 u16 gmch_ctrl;
12867
12868 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
12869 DRM_ERROR("failed to read control word\n");
12870 return -EIO;
12871 }
12872
12873 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
12874 return 0;
12875
12876 if (state)
12877 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
12878 else
12879 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
12880
12881 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
12882 DRM_ERROR("failed to write control word\n");
12883 return -EIO;
12884 }
12885
12886 return 0;
12887 }
12888
12889 struct intel_display_error_state {
12890
12891 u32 power_well_driver;
12892
12893 int num_transcoders;
12894
12895 struct intel_cursor_error_state {
12896 u32 control;
12897 u32 position;
12898 u32 base;
12899 u32 size;
12900 } cursor[I915_MAX_PIPES];
12901
12902 struct intel_pipe_error_state {
12903 bool power_domain_on;
12904 u32 source;
12905 u32 stat;
12906 } pipe[I915_MAX_PIPES];
12907
12908 struct intel_plane_error_state {
12909 u32 control;
12910 u32 stride;
12911 u32 size;
12912 u32 pos;
12913 u32 addr;
12914 u32 surface;
12915 u32 tile_offset;
12916 } plane[I915_MAX_PIPES];
12917
12918 struct intel_transcoder_error_state {
12919 bool power_domain_on;
12920 enum transcoder cpu_transcoder;
12921
12922 u32 conf;
12923
12924 u32 htotal;
12925 u32 hblank;
12926 u32 hsync;
12927 u32 vtotal;
12928 u32 vblank;
12929 u32 vsync;
12930 } transcoder[4];
12931 };
12932
12933 struct intel_display_error_state *
12934 intel_display_capture_error_state(struct drm_device *dev)
12935 {
12936 struct drm_i915_private *dev_priv = dev->dev_private;
12937 struct intel_display_error_state *error;
12938 int transcoders[] = {
12939 TRANSCODER_A,
12940 TRANSCODER_B,
12941 TRANSCODER_C,
12942 TRANSCODER_EDP,
12943 };
12944 int i;
12945
12946 if (INTEL_INFO(dev)->num_pipes == 0)
12947 return NULL;
12948
12949 error = kzalloc(sizeof(*error), GFP_ATOMIC);
12950 if (error == NULL)
12951 return NULL;
12952
12953 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
12954 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
12955
12956 for_each_pipe(i) {
12957 error->pipe[i].power_domain_on =
12958 intel_display_power_enabled_sw(dev_priv,
12959 POWER_DOMAIN_PIPE(i));
12960 if (!error->pipe[i].power_domain_on)
12961 continue;
12962
12963 error->cursor[i].control = I915_READ(CURCNTR(i));
12964 error->cursor[i].position = I915_READ(CURPOS(i));
12965 error->cursor[i].base = I915_READ(CURBASE(i));
12966
12967 error->plane[i].control = I915_READ(DSPCNTR(i));
12968 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
12969 if (INTEL_INFO(dev)->gen <= 3) {
12970 error->plane[i].size = I915_READ(DSPSIZE(i));
12971 error->plane[i].pos = I915_READ(DSPPOS(i));
12972 }
12973 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
12974 error->plane[i].addr = I915_READ(DSPADDR(i));
12975 if (INTEL_INFO(dev)->gen >= 4) {
12976 error->plane[i].surface = I915_READ(DSPSURF(i));
12977 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
12978 }
12979
12980 error->pipe[i].source = I915_READ(PIPESRC(i));
12981
12982 if (!HAS_PCH_SPLIT(dev))
12983 error->pipe[i].stat = I915_READ(PIPESTAT(i));
12984 }
12985
12986 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
12987 if (HAS_DDI(dev_priv->dev))
12988 error->num_transcoders++; /* Account for eDP. */
12989
12990 for (i = 0; i < error->num_transcoders; i++) {
12991 enum transcoder cpu_transcoder = transcoders[i];
12992
12993 error->transcoder[i].power_domain_on =
12994 intel_display_power_enabled_sw(dev_priv,
12995 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
12996 if (!error->transcoder[i].power_domain_on)
12997 continue;
12998
12999 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13000
13001 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13002 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13003 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13004 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13005 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13006 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13007 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13008 }
13009
13010 return error;
13011 }
13012
13013 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13014
13015 void
13016 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13017 struct drm_device *dev,
13018 struct intel_display_error_state *error)
13019 {
13020 int i;
13021
13022 if (!error)
13023 return;
13024
13025 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13026 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13027 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13028 error->power_well_driver);
13029 for_each_pipe(i) {
13030 err_printf(m, "Pipe [%d]:\n", i);
13031 err_printf(m, " Power: %s\n",
13032 error->pipe[i].power_domain_on ? "on" : "off");
13033 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
13034 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
13035
13036 err_printf(m, "Plane [%d]:\n", i);
13037 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
13038 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
13039 if (INTEL_INFO(dev)->gen <= 3) {
13040 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
13041 err_printf(m, " POS: %08x\n", error->plane[i].pos);
13042 }
13043 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13044 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
13045 if (INTEL_INFO(dev)->gen >= 4) {
13046 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
13047 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
13048 }
13049
13050 err_printf(m, "Cursor [%d]:\n", i);
13051 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
13052 err_printf(m, " POS: %08x\n", error->cursor[i].position);
13053 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
13054 }
13055
13056 for (i = 0; i < error->num_transcoders; i++) {
13057 err_printf(m, "CPU transcoder: %c\n",
13058 transcoder_name(error->transcoder[i].cpu_transcoder));
13059 err_printf(m, " Power: %s\n",
13060 error->transcoder[i].power_domain_on ? "on" : "off");
13061 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
13062 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
13063 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
13064 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
13065 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
13066 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
13067 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
13068 }
13069 }
Linux kernel - Deliverables
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