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drm/i915: remove obsolete obj assignment in page flip
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
43
44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
45 static void intel_increase_pllclock(struct drm_crtc *crtc);
46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
47
48 typedef struct {
49 /* given values */
50 int n;
51 int m1, m2;
52 int p1, p2;
53 /* derived values */
54 int dot;
55 int vco;
56 int m;
57 int p;
58 } intel_clock_t;
59
60 typedef struct {
61 int min, max;
62 } intel_range_t;
63
64 typedef struct {
65 int dot_limit;
66 int p2_slow, p2_fast;
67 } intel_p2_t;
68
69 #define INTEL_P2_NUM 2
70 typedef struct intel_limit intel_limit_t;
71 struct intel_limit {
72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 intel_p2_t p2;
74 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
75 int, int, intel_clock_t *, intel_clock_t *);
76 };
77
78 /* FDI */
79 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
80
81 int
82 intel_pch_rawclk(struct drm_device *dev)
83 {
84 struct drm_i915_private *dev_priv = dev->dev_private;
85
86 WARN_ON(!HAS_PCH_SPLIT(dev));
87
88 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
89 }
90
91 static bool
92 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
93 int target, int refclk, intel_clock_t *match_clock,
94 intel_clock_t *best_clock);
95 static bool
96 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
97 int target, int refclk, intel_clock_t *match_clock,
98 intel_clock_t *best_clock);
99
100 static bool
101 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
102 int target, int refclk, intel_clock_t *match_clock,
103 intel_clock_t *best_clock);
104 static bool
105 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
106 int target, int refclk, intel_clock_t *match_clock,
107 intel_clock_t *best_clock);
108
109 static bool
110 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
111 int target, int refclk, intel_clock_t *match_clock,
112 intel_clock_t *best_clock);
113
114 static inline u32 /* units of 100MHz */
115 intel_fdi_link_freq(struct drm_device *dev)
116 {
117 if (IS_GEN5(dev)) {
118 struct drm_i915_private *dev_priv = dev->dev_private;
119 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
120 } else
121 return 27;
122 }
123
124 static const intel_limit_t intel_limits_i8xx_dvo = {
125 .dot = { .min = 25000, .max = 350000 },
126 .vco = { .min = 930000, .max = 1400000 },
127 .n = { .min = 3, .max = 16 },
128 .m = { .min = 96, .max = 140 },
129 .m1 = { .min = 18, .max = 26 },
130 .m2 = { .min = 6, .max = 16 },
131 .p = { .min = 4, .max = 128 },
132 .p1 = { .min = 2, .max = 33 },
133 .p2 = { .dot_limit = 165000,
134 .p2_slow = 4, .p2_fast = 2 },
135 .find_pll = intel_find_best_PLL,
136 };
137
138 static const intel_limit_t intel_limits_i8xx_lvds = {
139 .dot = { .min = 25000, .max = 350000 },
140 .vco = { .min = 930000, .max = 1400000 },
141 .n = { .min = 3, .max = 16 },
142 .m = { .min = 96, .max = 140 },
143 .m1 = { .min = 18, .max = 26 },
144 .m2 = { .min = 6, .max = 16 },
145 .p = { .min = 4, .max = 128 },
146 .p1 = { .min = 1, .max = 6 },
147 .p2 = { .dot_limit = 165000,
148 .p2_slow = 14, .p2_fast = 7 },
149 .find_pll = intel_find_best_PLL,
150 };
151
152 static const intel_limit_t intel_limits_i9xx_sdvo = {
153 .dot = { .min = 20000, .max = 400000 },
154 .vco = { .min = 1400000, .max = 2800000 },
155 .n = { .min = 1, .max = 6 },
156 .m = { .min = 70, .max = 120 },
157 .m1 = { .min = 8, .max = 18 },
158 .m2 = { .min = 3, .max = 7 },
159 .p = { .min = 5, .max = 80 },
160 .p1 = { .min = 1, .max = 8 },
161 .p2 = { .dot_limit = 200000,
162 .p2_slow = 10, .p2_fast = 5 },
163 .find_pll = intel_find_best_PLL,
164 };
165
166 static const intel_limit_t intel_limits_i9xx_lvds = {
167 .dot = { .min = 20000, .max = 400000 },
168 .vco = { .min = 1400000, .max = 2800000 },
169 .n = { .min = 1, .max = 6 },
170 .m = { .min = 70, .max = 120 },
171 .m1 = { .min = 8, .max = 18 },
172 .m2 = { .min = 3, .max = 7 },
173 .p = { .min = 7, .max = 98 },
174 .p1 = { .min = 1, .max = 8 },
175 .p2 = { .dot_limit = 112000,
176 .p2_slow = 14, .p2_fast = 7 },
177 .find_pll = intel_find_best_PLL,
178 };
179
180
181 static const intel_limit_t intel_limits_g4x_sdvo = {
182 .dot = { .min = 25000, .max = 270000 },
183 .vco = { .min = 1750000, .max = 3500000},
184 .n = { .min = 1, .max = 4 },
185 .m = { .min = 104, .max = 138 },
186 .m1 = { .min = 17, .max = 23 },
187 .m2 = { .min = 5, .max = 11 },
188 .p = { .min = 10, .max = 30 },
189 .p1 = { .min = 1, .max = 3},
190 .p2 = { .dot_limit = 270000,
191 .p2_slow = 10,
192 .p2_fast = 10
193 },
194 .find_pll = intel_g4x_find_best_PLL,
195 };
196
197 static const intel_limit_t intel_limits_g4x_hdmi = {
198 .dot = { .min = 22000, .max = 400000 },
199 .vco = { .min = 1750000, .max = 3500000},
200 .n = { .min = 1, .max = 4 },
201 .m = { .min = 104, .max = 138 },
202 .m1 = { .min = 16, .max = 23 },
203 .m2 = { .min = 5, .max = 11 },
204 .p = { .min = 5, .max = 80 },
205 .p1 = { .min = 1, .max = 8},
206 .p2 = { .dot_limit = 165000,
207 .p2_slow = 10, .p2_fast = 5 },
208 .find_pll = intel_g4x_find_best_PLL,
209 };
210
211 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
212 .dot = { .min = 20000, .max = 115000 },
213 .vco = { .min = 1750000, .max = 3500000 },
214 .n = { .min = 1, .max = 3 },
215 .m = { .min = 104, .max = 138 },
216 .m1 = { .min = 17, .max = 23 },
217 .m2 = { .min = 5, .max = 11 },
218 .p = { .min = 28, .max = 112 },
219 .p1 = { .min = 2, .max = 8 },
220 .p2 = { .dot_limit = 0,
221 .p2_slow = 14, .p2_fast = 14
222 },
223 .find_pll = intel_g4x_find_best_PLL,
224 };
225
226 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
227 .dot = { .min = 80000, .max = 224000 },
228 .vco = { .min = 1750000, .max = 3500000 },
229 .n = { .min = 1, .max = 3 },
230 .m = { .min = 104, .max = 138 },
231 .m1 = { .min = 17, .max = 23 },
232 .m2 = { .min = 5, .max = 11 },
233 .p = { .min = 14, .max = 42 },
234 .p1 = { .min = 2, .max = 6 },
235 .p2 = { .dot_limit = 0,
236 .p2_slow = 7, .p2_fast = 7
237 },
238 .find_pll = intel_g4x_find_best_PLL,
239 };
240
241 static const intel_limit_t intel_limits_g4x_display_port = {
242 .dot = { .min = 161670, .max = 227000 },
243 .vco = { .min = 1750000, .max = 3500000},
244 .n = { .min = 1, .max = 2 },
245 .m = { .min = 97, .max = 108 },
246 .m1 = { .min = 0x10, .max = 0x12 },
247 .m2 = { .min = 0x05, .max = 0x06 },
248 .p = { .min = 10, .max = 20 },
249 .p1 = { .min = 1, .max = 2},
250 .p2 = { .dot_limit = 0,
251 .p2_slow = 10, .p2_fast = 10 },
252 .find_pll = intel_find_pll_g4x_dp,
253 };
254
255 static const intel_limit_t intel_limits_pineview_sdvo = {
256 .dot = { .min = 20000, .max = 400000},
257 .vco = { .min = 1700000, .max = 3500000 },
258 /* Pineview's Ncounter is a ring counter */
259 .n = { .min = 3, .max = 6 },
260 .m = { .min = 2, .max = 256 },
261 /* Pineview only has one combined m divider, which we treat as m2. */
262 .m1 = { .min = 0, .max = 0 },
263 .m2 = { .min = 0, .max = 254 },
264 .p = { .min = 5, .max = 80 },
265 .p1 = { .min = 1, .max = 8 },
266 .p2 = { .dot_limit = 200000,
267 .p2_slow = 10, .p2_fast = 5 },
268 .find_pll = intel_find_best_PLL,
269 };
270
271 static const intel_limit_t intel_limits_pineview_lvds = {
272 .dot = { .min = 20000, .max = 400000 },
273 .vco = { .min = 1700000, .max = 3500000 },
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 .m1 = { .min = 0, .max = 0 },
277 .m2 = { .min = 0, .max = 254 },
278 .p = { .min = 7, .max = 112 },
279 .p1 = { .min = 1, .max = 8 },
280 .p2 = { .dot_limit = 112000,
281 .p2_slow = 14, .p2_fast = 14 },
282 .find_pll = intel_find_best_PLL,
283 };
284
285 /* Ironlake / Sandybridge
286 *
287 * We calculate clock using (register_value + 2) for N/M1/M2, so here
288 * the range value for them is (actual_value - 2).
289 */
290 static const intel_limit_t intel_limits_ironlake_dac = {
291 .dot = { .min = 25000, .max = 350000 },
292 .vco = { .min = 1760000, .max = 3510000 },
293 .n = { .min = 1, .max = 5 },
294 .m = { .min = 79, .max = 127 },
295 .m1 = { .min = 12, .max = 22 },
296 .m2 = { .min = 5, .max = 9 },
297 .p = { .min = 5, .max = 80 },
298 .p1 = { .min = 1, .max = 8 },
299 .p2 = { .dot_limit = 225000,
300 .p2_slow = 10, .p2_fast = 5 },
301 .find_pll = intel_g4x_find_best_PLL,
302 };
303
304 static const intel_limit_t intel_limits_ironlake_single_lvds = {
305 .dot = { .min = 25000, .max = 350000 },
306 .vco = { .min = 1760000, .max = 3510000 },
307 .n = { .min = 1, .max = 3 },
308 .m = { .min = 79, .max = 118 },
309 .m1 = { .min = 12, .max = 22 },
310 .m2 = { .min = 5, .max = 9 },
311 .p = { .min = 28, .max = 112 },
312 .p1 = { .min = 2, .max = 8 },
313 .p2 = { .dot_limit = 225000,
314 .p2_slow = 14, .p2_fast = 14 },
315 .find_pll = intel_g4x_find_best_PLL,
316 };
317
318 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
319 .dot = { .min = 25000, .max = 350000 },
320 .vco = { .min = 1760000, .max = 3510000 },
321 .n = { .min = 1, .max = 3 },
322 .m = { .min = 79, .max = 127 },
323 .m1 = { .min = 12, .max = 22 },
324 .m2 = { .min = 5, .max = 9 },
325 .p = { .min = 14, .max = 56 },
326 .p1 = { .min = 2, .max = 8 },
327 .p2 = { .dot_limit = 225000,
328 .p2_slow = 7, .p2_fast = 7 },
329 .find_pll = intel_g4x_find_best_PLL,
330 };
331
332 /* LVDS 100mhz refclk limits. */
333 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
334 .dot = { .min = 25000, .max = 350000 },
335 .vco = { .min = 1760000, .max = 3510000 },
336 .n = { .min = 1, .max = 2 },
337 .m = { .min = 79, .max = 126 },
338 .m1 = { .min = 12, .max = 22 },
339 .m2 = { .min = 5, .max = 9 },
340 .p = { .min = 28, .max = 112 },
341 .p1 = { .min = 2, .max = 8 },
342 .p2 = { .dot_limit = 225000,
343 .p2_slow = 14, .p2_fast = 14 },
344 .find_pll = intel_g4x_find_best_PLL,
345 };
346
347 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
348 .dot = { .min = 25000, .max = 350000 },
349 .vco = { .min = 1760000, .max = 3510000 },
350 .n = { .min = 1, .max = 3 },
351 .m = { .min = 79, .max = 126 },
352 .m1 = { .min = 12, .max = 22 },
353 .m2 = { .min = 5, .max = 9 },
354 .p = { .min = 14, .max = 42 },
355 .p1 = { .min = 2, .max = 6 },
356 .p2 = { .dot_limit = 225000,
357 .p2_slow = 7, .p2_fast = 7 },
358 .find_pll = intel_g4x_find_best_PLL,
359 };
360
361 static const intel_limit_t intel_limits_ironlake_display_port = {
362 .dot = { .min = 25000, .max = 350000 },
363 .vco = { .min = 1760000, .max = 3510000},
364 .n = { .min = 1, .max = 2 },
365 .m = { .min = 81, .max = 90 },
366 .m1 = { .min = 12, .max = 22 },
367 .m2 = { .min = 5, .max = 9 },
368 .p = { .min = 10, .max = 20 },
369 .p1 = { .min = 1, .max = 2},
370 .p2 = { .dot_limit = 0,
371 .p2_slow = 10, .p2_fast = 10 },
372 .find_pll = intel_find_pll_ironlake_dp,
373 };
374
375 static const intel_limit_t intel_limits_vlv_dac = {
376 .dot = { .min = 25000, .max = 270000 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m = { .min = 22, .max = 450 }, /* guess */
380 .m1 = { .min = 2, .max = 3 },
381 .m2 = { .min = 11, .max = 156 },
382 .p = { .min = 10, .max = 30 },
383 .p1 = { .min = 2, .max = 3 },
384 .p2 = { .dot_limit = 270000,
385 .p2_slow = 2, .p2_fast = 20 },
386 .find_pll = intel_vlv_find_best_pll,
387 };
388
389 static const intel_limit_t intel_limits_vlv_hdmi = {
390 .dot = { .min = 20000, .max = 165000 },
391 .vco = { .min = 4000000, .max = 5994000},
392 .n = { .min = 1, .max = 7 },
393 .m = { .min = 60, .max = 300 }, /* guess */
394 .m1 = { .min = 2, .max = 3 },
395 .m2 = { .min = 11, .max = 156 },
396 .p = { .min = 10, .max = 30 },
397 .p1 = { .min = 2, .max = 3 },
398 .p2 = { .dot_limit = 270000,
399 .p2_slow = 2, .p2_fast = 20 },
400 .find_pll = intel_vlv_find_best_pll,
401 };
402
403 static const intel_limit_t intel_limits_vlv_dp = {
404 .dot = { .min = 25000, .max = 270000 },
405 .vco = { .min = 4000000, .max = 6000000 },
406 .n = { .min = 1, .max = 7 },
407 .m = { .min = 22, .max = 450 },
408 .m1 = { .min = 2, .max = 3 },
409 .m2 = { .min = 11, .max = 156 },
410 .p = { .min = 10, .max = 30 },
411 .p1 = { .min = 2, .max = 3 },
412 .p2 = { .dot_limit = 270000,
413 .p2_slow = 2, .p2_fast = 20 },
414 .find_pll = intel_vlv_find_best_pll,
415 };
416
417 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
418 {
419 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
420
421 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
422 DRM_ERROR("DPIO idle wait timed out\n");
423 return 0;
424 }
425
426 I915_WRITE(DPIO_REG, reg);
427 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
428 DPIO_BYTE);
429 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
430 DRM_ERROR("DPIO read wait timed out\n");
431 return 0;
432 }
433
434 return I915_READ(DPIO_DATA);
435 }
436
437 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
438 u32 val)
439 {
440 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
441
442 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
443 DRM_ERROR("DPIO idle wait timed out\n");
444 return;
445 }
446
447 I915_WRITE(DPIO_DATA, val);
448 I915_WRITE(DPIO_REG, reg);
449 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
450 DPIO_BYTE);
451 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
452 DRM_ERROR("DPIO write wait timed out\n");
453 }
454
455 static void vlv_init_dpio(struct drm_device *dev)
456 {
457 struct drm_i915_private *dev_priv = dev->dev_private;
458
459 /* Reset the DPIO config */
460 I915_WRITE(DPIO_CTL, 0);
461 POSTING_READ(DPIO_CTL);
462 I915_WRITE(DPIO_CTL, 1);
463 POSTING_READ(DPIO_CTL);
464 }
465
466 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
467 int refclk)
468 {
469 struct drm_device *dev = crtc->dev;
470 const intel_limit_t *limit;
471
472 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
473 if (intel_is_dual_link_lvds(dev)) {
474 /* LVDS dual channel */
475 if (refclk == 100000)
476 limit = &intel_limits_ironlake_dual_lvds_100m;
477 else
478 limit = &intel_limits_ironlake_dual_lvds;
479 } else {
480 if (refclk == 100000)
481 limit = &intel_limits_ironlake_single_lvds_100m;
482 else
483 limit = &intel_limits_ironlake_single_lvds;
484 }
485 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
486 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
487 limit = &intel_limits_ironlake_display_port;
488 else
489 limit = &intel_limits_ironlake_dac;
490
491 return limit;
492 }
493
494 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
495 {
496 struct drm_device *dev = crtc->dev;
497 const intel_limit_t *limit;
498
499 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
500 if (intel_is_dual_link_lvds(dev))
501 /* LVDS with dual channel */
502 limit = &intel_limits_g4x_dual_channel_lvds;
503 else
504 /* LVDS with dual channel */
505 limit = &intel_limits_g4x_single_channel_lvds;
506 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
507 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
508 limit = &intel_limits_g4x_hdmi;
509 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
510 limit = &intel_limits_g4x_sdvo;
511 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
512 limit = &intel_limits_g4x_display_port;
513 } else /* The option is for other outputs */
514 limit = &intel_limits_i9xx_sdvo;
515
516 return limit;
517 }
518
519 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
520 {
521 struct drm_device *dev = crtc->dev;
522 const intel_limit_t *limit;
523
524 if (HAS_PCH_SPLIT(dev))
525 limit = intel_ironlake_limit(crtc, refclk);
526 else if (IS_G4X(dev)) {
527 limit = intel_g4x_limit(crtc);
528 } else if (IS_PINEVIEW(dev)) {
529 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
530 limit = &intel_limits_pineview_lvds;
531 else
532 limit = &intel_limits_pineview_sdvo;
533 } else if (IS_VALLEYVIEW(dev)) {
534 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
535 limit = &intel_limits_vlv_dac;
536 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
537 limit = &intel_limits_vlv_hdmi;
538 else
539 limit = &intel_limits_vlv_dp;
540 } else if (!IS_GEN2(dev)) {
541 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
542 limit = &intel_limits_i9xx_lvds;
543 else
544 limit = &intel_limits_i9xx_sdvo;
545 } else {
546 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
547 limit = &intel_limits_i8xx_lvds;
548 else
549 limit = &intel_limits_i8xx_dvo;
550 }
551 return limit;
552 }
553
554 /* m1 is reserved as 0 in Pineview, n is a ring counter */
555 static void pineview_clock(int refclk, intel_clock_t *clock)
556 {
557 clock->m = clock->m2 + 2;
558 clock->p = clock->p1 * clock->p2;
559 clock->vco = refclk * clock->m / clock->n;
560 clock->dot = clock->vco / clock->p;
561 }
562
563 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
564 {
565 if (IS_PINEVIEW(dev)) {
566 pineview_clock(refclk, clock);
567 return;
568 }
569 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
570 clock->p = clock->p1 * clock->p2;
571 clock->vco = refclk * clock->m / (clock->n + 2);
572 clock->dot = clock->vco / clock->p;
573 }
574
575 /**
576 * Returns whether any output on the specified pipe is of the specified type
577 */
578 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
579 {
580 struct drm_device *dev = crtc->dev;
581 struct intel_encoder *encoder;
582
583 for_each_encoder_on_crtc(dev, crtc, encoder)
584 if (encoder->type == type)
585 return true;
586
587 return false;
588 }
589
590 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
591 /**
592 * Returns whether the given set of divisors are valid for a given refclk with
593 * the given connectors.
594 */
595
596 static bool intel_PLL_is_valid(struct drm_device *dev,
597 const intel_limit_t *limit,
598 const intel_clock_t *clock)
599 {
600 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
601 INTELPllInvalid("p1 out of range\n");
602 if (clock->p < limit->p.min || limit->p.max < clock->p)
603 INTELPllInvalid("p out of range\n");
604 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
605 INTELPllInvalid("m2 out of range\n");
606 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
607 INTELPllInvalid("m1 out of range\n");
608 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
609 INTELPllInvalid("m1 <= m2\n");
610 if (clock->m < limit->m.min || limit->m.max < clock->m)
611 INTELPllInvalid("m out of range\n");
612 if (clock->n < limit->n.min || limit->n.max < clock->n)
613 INTELPllInvalid("n out of range\n");
614 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
615 INTELPllInvalid("vco out of range\n");
616 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
617 * connector, etc., rather than just a single range.
618 */
619 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
620 INTELPllInvalid("dot out of range\n");
621
622 return true;
623 }
624
625 static bool
626 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
627 int target, int refclk, intel_clock_t *match_clock,
628 intel_clock_t *best_clock)
629
630 {
631 struct drm_device *dev = crtc->dev;
632 intel_clock_t clock;
633 int err = target;
634
635 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
636 /*
637 * For LVDS just rely on its current settings for dual-channel.
638 * We haven't figured out how to reliably set up different
639 * single/dual channel state, if we even can.
640 */
641 if (intel_is_dual_link_lvds(dev))
642 clock.p2 = limit->p2.p2_fast;
643 else
644 clock.p2 = limit->p2.p2_slow;
645 } else {
646 if (target < limit->p2.dot_limit)
647 clock.p2 = limit->p2.p2_slow;
648 else
649 clock.p2 = limit->p2.p2_fast;
650 }
651
652 memset(best_clock, 0, sizeof(*best_clock));
653
654 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
655 clock.m1++) {
656 for (clock.m2 = limit->m2.min;
657 clock.m2 <= limit->m2.max; clock.m2++) {
658 /* m1 is always 0 in Pineview */
659 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
660 break;
661 for (clock.n = limit->n.min;
662 clock.n <= limit->n.max; clock.n++) {
663 for (clock.p1 = limit->p1.min;
664 clock.p1 <= limit->p1.max; clock.p1++) {
665 int this_err;
666
667 intel_clock(dev, refclk, &clock);
668 if (!intel_PLL_is_valid(dev, limit,
669 &clock))
670 continue;
671 if (match_clock &&
672 clock.p != match_clock->p)
673 continue;
674
675 this_err = abs(clock.dot - target);
676 if (this_err < err) {
677 *best_clock = clock;
678 err = this_err;
679 }
680 }
681 }
682 }
683 }
684
685 return (err != target);
686 }
687
688 static bool
689 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
690 int target, int refclk, intel_clock_t *match_clock,
691 intel_clock_t *best_clock)
692 {
693 struct drm_device *dev = crtc->dev;
694 intel_clock_t clock;
695 int max_n;
696 bool found;
697 /* approximately equals target * 0.00585 */
698 int err_most = (target >> 8) + (target >> 9);
699 found = false;
700
701 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
702 int lvds_reg;
703
704 if (HAS_PCH_SPLIT(dev))
705 lvds_reg = PCH_LVDS;
706 else
707 lvds_reg = LVDS;
708 if (intel_is_dual_link_lvds(dev))
709 clock.p2 = limit->p2.p2_fast;
710 else
711 clock.p2 = limit->p2.p2_slow;
712 } else {
713 if (target < limit->p2.dot_limit)
714 clock.p2 = limit->p2.p2_slow;
715 else
716 clock.p2 = limit->p2.p2_fast;
717 }
718
719 memset(best_clock, 0, sizeof(*best_clock));
720 max_n = limit->n.max;
721 /* based on hardware requirement, prefer smaller n to precision */
722 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
723 /* based on hardware requirement, prefere larger m1,m2 */
724 for (clock.m1 = limit->m1.max;
725 clock.m1 >= limit->m1.min; clock.m1--) {
726 for (clock.m2 = limit->m2.max;
727 clock.m2 >= limit->m2.min; clock.m2--) {
728 for (clock.p1 = limit->p1.max;
729 clock.p1 >= limit->p1.min; clock.p1--) {
730 int this_err;
731
732 intel_clock(dev, refclk, &clock);
733 if (!intel_PLL_is_valid(dev, limit,
734 &clock))
735 continue;
736 if (match_clock &&
737 clock.p != match_clock->p)
738 continue;
739
740 this_err = abs(clock.dot - target);
741 if (this_err < err_most) {
742 *best_clock = clock;
743 err_most = this_err;
744 max_n = clock.n;
745 found = true;
746 }
747 }
748 }
749 }
750 }
751 return found;
752 }
753
754 static bool
755 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
756 int target, int refclk, intel_clock_t *match_clock,
757 intel_clock_t *best_clock)
758 {
759 struct drm_device *dev = crtc->dev;
760 intel_clock_t clock;
761
762 if (target < 200000) {
763 clock.n = 1;
764 clock.p1 = 2;
765 clock.p2 = 10;
766 clock.m1 = 12;
767 clock.m2 = 9;
768 } else {
769 clock.n = 2;
770 clock.p1 = 1;
771 clock.p2 = 10;
772 clock.m1 = 14;
773 clock.m2 = 8;
774 }
775 intel_clock(dev, refclk, &clock);
776 memcpy(best_clock, &clock, sizeof(intel_clock_t));
777 return true;
778 }
779
780 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
781 static bool
782 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
783 int target, int refclk, intel_clock_t *match_clock,
784 intel_clock_t *best_clock)
785 {
786 intel_clock_t clock;
787 if (target < 200000) {
788 clock.p1 = 2;
789 clock.p2 = 10;
790 clock.n = 2;
791 clock.m1 = 23;
792 clock.m2 = 8;
793 } else {
794 clock.p1 = 1;
795 clock.p2 = 10;
796 clock.n = 1;
797 clock.m1 = 14;
798 clock.m2 = 2;
799 }
800 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
801 clock.p = (clock.p1 * clock.p2);
802 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
803 clock.vco = 0;
804 memcpy(best_clock, &clock, sizeof(intel_clock_t));
805 return true;
806 }
807 static bool
808 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
809 int target, int refclk, intel_clock_t *match_clock,
810 intel_clock_t *best_clock)
811 {
812 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
813 u32 m, n, fastclk;
814 u32 updrate, minupdate, fracbits, p;
815 unsigned long bestppm, ppm, absppm;
816 int dotclk, flag;
817
818 flag = 0;
819 dotclk = target * 1000;
820 bestppm = 1000000;
821 ppm = absppm = 0;
822 fastclk = dotclk / (2*100);
823 updrate = 0;
824 minupdate = 19200;
825 fracbits = 1;
826 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
827 bestm1 = bestm2 = bestp1 = bestp2 = 0;
828
829 /* based on hardware requirement, prefer smaller n to precision */
830 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
831 updrate = refclk / n;
832 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
833 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
834 if (p2 > 10)
835 p2 = p2 - 1;
836 p = p1 * p2;
837 /* based on hardware requirement, prefer bigger m1,m2 values */
838 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
839 m2 = (((2*(fastclk * p * n / m1 )) +
840 refclk) / (2*refclk));
841 m = m1 * m2;
842 vco = updrate * m;
843 if (vco >= limit->vco.min && vco < limit->vco.max) {
844 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
845 absppm = (ppm > 0) ? ppm : (-ppm);
846 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
847 bestppm = 0;
848 flag = 1;
849 }
850 if (absppm < bestppm - 10) {
851 bestppm = absppm;
852 flag = 1;
853 }
854 if (flag) {
855 bestn = n;
856 bestm1 = m1;
857 bestm2 = m2;
858 bestp1 = p1;
859 bestp2 = p2;
860 flag = 0;
861 }
862 }
863 }
864 }
865 }
866 }
867 best_clock->n = bestn;
868 best_clock->m1 = bestm1;
869 best_clock->m2 = bestm2;
870 best_clock->p1 = bestp1;
871 best_clock->p2 = bestp2;
872
873 return true;
874 }
875
876 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
877 enum pipe pipe)
878 {
879 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
880 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
881
882 return intel_crtc->cpu_transcoder;
883 }
884
885 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
886 {
887 struct drm_i915_private *dev_priv = dev->dev_private;
888 u32 frame, frame_reg = PIPEFRAME(pipe);
889
890 frame = I915_READ(frame_reg);
891
892 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
893 DRM_DEBUG_KMS("vblank wait timed out\n");
894 }
895
896 /**
897 * intel_wait_for_vblank - wait for vblank on a given pipe
898 * @dev: drm device
899 * @pipe: pipe to wait for
900 *
901 * Wait for vblank to occur on a given pipe. Needed for various bits of
902 * mode setting code.
903 */
904 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
905 {
906 struct drm_i915_private *dev_priv = dev->dev_private;
907 int pipestat_reg = PIPESTAT(pipe);
908
909 if (INTEL_INFO(dev)->gen >= 5) {
910 ironlake_wait_for_vblank(dev, pipe);
911 return;
912 }
913
914 /* Clear existing vblank status. Note this will clear any other
915 * sticky status fields as well.
916 *
917 * This races with i915_driver_irq_handler() with the result
918 * that either function could miss a vblank event. Here it is not
919 * fatal, as we will either wait upon the next vblank interrupt or
920 * timeout. Generally speaking intel_wait_for_vblank() is only
921 * called during modeset at which time the GPU should be idle and
922 * should *not* be performing page flips and thus not waiting on
923 * vblanks...
924 * Currently, the result of us stealing a vblank from the irq
925 * handler is that a single frame will be skipped during swapbuffers.
926 */
927 I915_WRITE(pipestat_reg,
928 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
929
930 /* Wait for vblank interrupt bit to set */
931 if (wait_for(I915_READ(pipestat_reg) &
932 PIPE_VBLANK_INTERRUPT_STATUS,
933 50))
934 DRM_DEBUG_KMS("vblank wait timed out\n");
935 }
936
937 /*
938 * intel_wait_for_pipe_off - wait for pipe to turn off
939 * @dev: drm device
940 * @pipe: pipe to wait for
941 *
942 * After disabling a pipe, we can't wait for vblank in the usual way,
943 * spinning on the vblank interrupt status bit, since we won't actually
944 * see an interrupt when the pipe is disabled.
945 *
946 * On Gen4 and above:
947 * wait for the pipe register state bit to turn off
948 *
949 * Otherwise:
950 * wait for the display line value to settle (it usually
951 * ends up stopping at the start of the next frame).
952 *
953 */
954 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
955 {
956 struct drm_i915_private *dev_priv = dev->dev_private;
957 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
958 pipe);
959
960 if (INTEL_INFO(dev)->gen >= 4) {
961 int reg = PIPECONF(cpu_transcoder);
962
963 /* Wait for the Pipe State to go off */
964 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
965 100))
966 WARN(1, "pipe_off wait timed out\n");
967 } else {
968 u32 last_line, line_mask;
969 int reg = PIPEDSL(pipe);
970 unsigned long timeout = jiffies + msecs_to_jiffies(100);
971
972 if (IS_GEN2(dev))
973 line_mask = DSL_LINEMASK_GEN2;
974 else
975 line_mask = DSL_LINEMASK_GEN3;
976
977 /* Wait for the display line to settle */
978 do {
979 last_line = I915_READ(reg) & line_mask;
980 mdelay(5);
981 } while (((I915_READ(reg) & line_mask) != last_line) &&
982 time_after(timeout, jiffies));
983 if (time_after(jiffies, timeout))
984 WARN(1, "pipe_off wait timed out\n");
985 }
986 }
987
988 /*
989 * ibx_digital_port_connected - is the specified port connected?
990 * @dev_priv: i915 private structure
991 * @port: the port to test
992 *
993 * Returns true if @port is connected, false otherwise.
994 */
995 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
996 struct intel_digital_port *port)
997 {
998 u32 bit;
999
1000 if (HAS_PCH_IBX(dev_priv->dev)) {
1001 switch(port->port) {
1002 case PORT_B:
1003 bit = SDE_PORTB_HOTPLUG;
1004 break;
1005 case PORT_C:
1006 bit = SDE_PORTC_HOTPLUG;
1007 break;
1008 case PORT_D:
1009 bit = SDE_PORTD_HOTPLUG;
1010 break;
1011 default:
1012 return true;
1013 }
1014 } else {
1015 switch(port->port) {
1016 case PORT_B:
1017 bit = SDE_PORTB_HOTPLUG_CPT;
1018 break;
1019 case PORT_C:
1020 bit = SDE_PORTC_HOTPLUG_CPT;
1021 break;
1022 case PORT_D:
1023 bit = SDE_PORTD_HOTPLUG_CPT;
1024 break;
1025 default:
1026 return true;
1027 }
1028 }
1029
1030 return I915_READ(SDEISR) & bit;
1031 }
1032
1033 static const char *state_string(bool enabled)
1034 {
1035 return enabled ? "on" : "off";
1036 }
1037
1038 /* Only for pre-ILK configs */
1039 static void assert_pll(struct drm_i915_private *dev_priv,
1040 enum pipe pipe, bool state)
1041 {
1042 int reg;
1043 u32 val;
1044 bool cur_state;
1045
1046 reg = DPLL(pipe);
1047 val = I915_READ(reg);
1048 cur_state = !!(val & DPLL_VCO_ENABLE);
1049 WARN(cur_state != state,
1050 "PLL state assertion failure (expected %s, current %s)\n",
1051 state_string(state), state_string(cur_state));
1052 }
1053 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1054 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1055
1056 /* For ILK+ */
1057 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1058 struct intel_pch_pll *pll,
1059 struct intel_crtc *crtc,
1060 bool state)
1061 {
1062 u32 val;
1063 bool cur_state;
1064
1065 if (HAS_PCH_LPT(dev_priv->dev)) {
1066 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1067 return;
1068 }
1069
1070 if (WARN (!pll,
1071 "asserting PCH PLL %s with no PLL\n", state_string(state)))
1072 return;
1073
1074 val = I915_READ(pll->pll_reg);
1075 cur_state = !!(val & DPLL_VCO_ENABLE);
1076 WARN(cur_state != state,
1077 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1078 pll->pll_reg, state_string(state), state_string(cur_state), val);
1079
1080 /* Make sure the selected PLL is correctly attached to the transcoder */
1081 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1082 u32 pch_dpll;
1083
1084 pch_dpll = I915_READ(PCH_DPLL_SEL);
1085 cur_state = pll->pll_reg == _PCH_DPLL_B;
1086 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1087 "PLL[%d] not attached to this transcoder %d: %08x\n",
1088 cur_state, crtc->pipe, pch_dpll)) {
1089 cur_state = !!(val >> (4*crtc->pipe + 3));
1090 WARN(cur_state != state,
1091 "PLL[%d] not %s on this transcoder %d: %08x\n",
1092 pll->pll_reg == _PCH_DPLL_B,
1093 state_string(state),
1094 crtc->pipe,
1095 val);
1096 }
1097 }
1098 }
1099 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1100 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1101
1102 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1103 enum pipe pipe, bool state)
1104 {
1105 int reg;
1106 u32 val;
1107 bool cur_state;
1108 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1109 pipe);
1110
1111 if (HAS_DDI(dev_priv->dev)) {
1112 /* DDI does not have a specific FDI_TX register */
1113 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1114 val = I915_READ(reg);
1115 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1116 } else {
1117 reg = FDI_TX_CTL(pipe);
1118 val = I915_READ(reg);
1119 cur_state = !!(val & FDI_TX_ENABLE);
1120 }
1121 WARN(cur_state != state,
1122 "FDI TX state assertion failure (expected %s, current %s)\n",
1123 state_string(state), state_string(cur_state));
1124 }
1125 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1126 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1127
1128 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1129 enum pipe pipe, bool state)
1130 {
1131 int reg;
1132 u32 val;
1133 bool cur_state;
1134
1135 reg = FDI_RX_CTL(pipe);
1136 val = I915_READ(reg);
1137 cur_state = !!(val & FDI_RX_ENABLE);
1138 WARN(cur_state != state,
1139 "FDI RX state assertion failure (expected %s, current %s)\n",
1140 state_string(state), state_string(cur_state));
1141 }
1142 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1143 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1144
1145 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1146 enum pipe pipe)
1147 {
1148 int reg;
1149 u32 val;
1150
1151 /* ILK FDI PLL is always enabled */
1152 if (dev_priv->info->gen == 5)
1153 return;
1154
1155 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1156 if (HAS_DDI(dev_priv->dev))
1157 return;
1158
1159 reg = FDI_TX_CTL(pipe);
1160 val = I915_READ(reg);
1161 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1162 }
1163
1164 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1165 enum pipe pipe)
1166 {
1167 int reg;
1168 u32 val;
1169
1170 reg = FDI_RX_CTL(pipe);
1171 val = I915_READ(reg);
1172 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1173 }
1174
1175 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1176 enum pipe pipe)
1177 {
1178 int pp_reg, lvds_reg;
1179 u32 val;
1180 enum pipe panel_pipe = PIPE_A;
1181 bool locked = true;
1182
1183 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1184 pp_reg = PCH_PP_CONTROL;
1185 lvds_reg = PCH_LVDS;
1186 } else {
1187 pp_reg = PP_CONTROL;
1188 lvds_reg = LVDS;
1189 }
1190
1191 val = I915_READ(pp_reg);
1192 if (!(val & PANEL_POWER_ON) ||
1193 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1194 locked = false;
1195
1196 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1197 panel_pipe = PIPE_B;
1198
1199 WARN(panel_pipe == pipe && locked,
1200 "panel assertion failure, pipe %c regs locked\n",
1201 pipe_name(pipe));
1202 }
1203
1204 void assert_pipe(struct drm_i915_private *dev_priv,
1205 enum pipe pipe, bool state)
1206 {
1207 int reg;
1208 u32 val;
1209 bool cur_state;
1210 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1211 pipe);
1212
1213 /* if we need the pipe A quirk it must be always on */
1214 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1215 state = true;
1216
1217 if (IS_HASWELL(dev_priv->dev) && cpu_transcoder != TRANSCODER_EDP &&
1218 !(I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_ENABLE)) {
1219 cur_state = false;
1220 } else {
1221 reg = PIPECONF(cpu_transcoder);
1222 val = I915_READ(reg);
1223 cur_state = !!(val & PIPECONF_ENABLE);
1224 }
1225
1226 WARN(cur_state != state,
1227 "pipe %c assertion failure (expected %s, current %s)\n",
1228 pipe_name(pipe), state_string(state), state_string(cur_state));
1229 }
1230
1231 static void assert_plane(struct drm_i915_private *dev_priv,
1232 enum plane plane, bool state)
1233 {
1234 int reg;
1235 u32 val;
1236 bool cur_state;
1237
1238 reg = DSPCNTR(plane);
1239 val = I915_READ(reg);
1240 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1241 WARN(cur_state != state,
1242 "plane %c assertion failure (expected %s, current %s)\n",
1243 plane_name(plane), state_string(state), state_string(cur_state));
1244 }
1245
1246 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1247 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1248
1249 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1250 enum pipe pipe)
1251 {
1252 int reg, i;
1253 u32 val;
1254 int cur_pipe;
1255
1256 /* Planes are fixed to pipes on ILK+ */
1257 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1258 reg = DSPCNTR(pipe);
1259 val = I915_READ(reg);
1260 WARN((val & DISPLAY_PLANE_ENABLE),
1261 "plane %c assertion failure, should be disabled but not\n",
1262 plane_name(pipe));
1263 return;
1264 }
1265
1266 /* Need to check both planes against the pipe */
1267 for (i = 0; i < 2; i++) {
1268 reg = DSPCNTR(i);
1269 val = I915_READ(reg);
1270 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1271 DISPPLANE_SEL_PIPE_SHIFT;
1272 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1273 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1274 plane_name(i), pipe_name(pipe));
1275 }
1276 }
1277
1278 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1279 {
1280 u32 val;
1281 bool enabled;
1282
1283 if (HAS_PCH_LPT(dev_priv->dev)) {
1284 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1285 return;
1286 }
1287
1288 val = I915_READ(PCH_DREF_CONTROL);
1289 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1290 DREF_SUPERSPREAD_SOURCE_MASK));
1291 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1292 }
1293
1294 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1295 enum pipe pipe)
1296 {
1297 int reg;
1298 u32 val;
1299 bool enabled;
1300
1301 reg = TRANSCONF(pipe);
1302 val = I915_READ(reg);
1303 enabled = !!(val & TRANS_ENABLE);
1304 WARN(enabled,
1305 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1306 pipe_name(pipe));
1307 }
1308
1309 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1310 enum pipe pipe, u32 port_sel, u32 val)
1311 {
1312 if ((val & DP_PORT_EN) == 0)
1313 return false;
1314
1315 if (HAS_PCH_CPT(dev_priv->dev)) {
1316 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1317 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1318 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1319 return false;
1320 } else {
1321 if ((val & DP_PIPE_MASK) != (pipe << 30))
1322 return false;
1323 }
1324 return true;
1325 }
1326
1327 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1328 enum pipe pipe, u32 val)
1329 {
1330 if ((val & PORT_ENABLE) == 0)
1331 return false;
1332
1333 if (HAS_PCH_CPT(dev_priv->dev)) {
1334 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1335 return false;
1336 } else {
1337 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1338 return false;
1339 }
1340 return true;
1341 }
1342
1343 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1344 enum pipe pipe, u32 val)
1345 {
1346 if ((val & LVDS_PORT_EN) == 0)
1347 return false;
1348
1349 if (HAS_PCH_CPT(dev_priv->dev)) {
1350 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1351 return false;
1352 } else {
1353 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1354 return false;
1355 }
1356 return true;
1357 }
1358
1359 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1360 enum pipe pipe, u32 val)
1361 {
1362 if ((val & ADPA_DAC_ENABLE) == 0)
1363 return false;
1364 if (HAS_PCH_CPT(dev_priv->dev)) {
1365 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1366 return false;
1367 } else {
1368 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1369 return false;
1370 }
1371 return true;
1372 }
1373
1374 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1375 enum pipe pipe, int reg, u32 port_sel)
1376 {
1377 u32 val = I915_READ(reg);
1378 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1379 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1380 reg, pipe_name(pipe));
1381
1382 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1383 && (val & DP_PIPEB_SELECT),
1384 "IBX PCH dp port still using transcoder B\n");
1385 }
1386
1387 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1388 enum pipe pipe, int reg)
1389 {
1390 u32 val = I915_READ(reg);
1391 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1392 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1393 reg, pipe_name(pipe));
1394
1395 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1396 && (val & SDVO_PIPE_B_SELECT),
1397 "IBX PCH hdmi port still using transcoder B\n");
1398 }
1399
1400 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1401 enum pipe pipe)
1402 {
1403 int reg;
1404 u32 val;
1405
1406 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1407 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1408 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1409
1410 reg = PCH_ADPA;
1411 val = I915_READ(reg);
1412 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1413 "PCH VGA enabled on transcoder %c, should be disabled\n",
1414 pipe_name(pipe));
1415
1416 reg = PCH_LVDS;
1417 val = I915_READ(reg);
1418 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1419 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1420 pipe_name(pipe));
1421
1422 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1423 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1424 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1425 }
1426
1427 /**
1428 * intel_enable_pll - enable a PLL
1429 * @dev_priv: i915 private structure
1430 * @pipe: pipe PLL to enable
1431 *
1432 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1433 * make sure the PLL reg is writable first though, since the panel write
1434 * protect mechanism may be enabled.
1435 *
1436 * Note! This is for pre-ILK only.
1437 *
1438 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1439 */
1440 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1441 {
1442 int reg;
1443 u32 val;
1444
1445 /* No really, not for ILK+ */
1446 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1447
1448 /* PLL is protected by panel, make sure we can write it */
1449 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1450 assert_panel_unlocked(dev_priv, pipe);
1451
1452 reg = DPLL(pipe);
1453 val = I915_READ(reg);
1454 val |= DPLL_VCO_ENABLE;
1455
1456 /* We do this three times for luck */
1457 I915_WRITE(reg, val);
1458 POSTING_READ(reg);
1459 udelay(150); /* wait for warmup */
1460 I915_WRITE(reg, val);
1461 POSTING_READ(reg);
1462 udelay(150); /* wait for warmup */
1463 I915_WRITE(reg, val);
1464 POSTING_READ(reg);
1465 udelay(150); /* wait for warmup */
1466 }
1467
1468 /**
1469 * intel_disable_pll - disable a PLL
1470 * @dev_priv: i915 private structure
1471 * @pipe: pipe PLL to disable
1472 *
1473 * Disable the PLL for @pipe, making sure the pipe is off first.
1474 *
1475 * Note! This is for pre-ILK only.
1476 */
1477 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1478 {
1479 int reg;
1480 u32 val;
1481
1482 /* Don't disable pipe A or pipe A PLLs if needed */
1483 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1484 return;
1485
1486 /* Make sure the pipe isn't still relying on us */
1487 assert_pipe_disabled(dev_priv, pipe);
1488
1489 reg = DPLL(pipe);
1490 val = I915_READ(reg);
1491 val &= ~DPLL_VCO_ENABLE;
1492 I915_WRITE(reg, val);
1493 POSTING_READ(reg);
1494 }
1495
1496 /* SBI access */
1497 static void
1498 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1499 enum intel_sbi_destination destination)
1500 {
1501 u32 tmp;
1502
1503 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1504
1505 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1506 100)) {
1507 DRM_ERROR("timeout waiting for SBI to become ready\n");
1508 return;
1509 }
1510
1511 I915_WRITE(SBI_ADDR, (reg << 16));
1512 I915_WRITE(SBI_DATA, value);
1513
1514 if (destination == SBI_ICLK)
1515 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1516 else
1517 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1518 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
1519
1520 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1521 100)) {
1522 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1523 return;
1524 }
1525 }
1526
1527 static u32
1528 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1529 enum intel_sbi_destination destination)
1530 {
1531 u32 value = 0;
1532 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1533
1534 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1535 100)) {
1536 DRM_ERROR("timeout waiting for SBI to become ready\n");
1537 return 0;
1538 }
1539
1540 I915_WRITE(SBI_ADDR, (reg << 16));
1541
1542 if (destination == SBI_ICLK)
1543 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1544 else
1545 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1546 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
1547
1548 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1549 100)) {
1550 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1551 return 0;
1552 }
1553
1554 return I915_READ(SBI_DATA);
1555 }
1556
1557 /**
1558 * ironlake_enable_pch_pll - enable PCH PLL
1559 * @dev_priv: i915 private structure
1560 * @pipe: pipe PLL to enable
1561 *
1562 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1563 * drives the transcoder clock.
1564 */
1565 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1566 {
1567 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1568 struct intel_pch_pll *pll;
1569 int reg;
1570 u32 val;
1571
1572 /* PCH PLLs only available on ILK, SNB and IVB */
1573 BUG_ON(dev_priv->info->gen < 5);
1574 pll = intel_crtc->pch_pll;
1575 if (pll == NULL)
1576 return;
1577
1578 if (WARN_ON(pll->refcount == 0))
1579 return;
1580
1581 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1582 pll->pll_reg, pll->active, pll->on,
1583 intel_crtc->base.base.id);
1584
1585 /* PCH refclock must be enabled first */
1586 assert_pch_refclk_enabled(dev_priv);
1587
1588 if (pll->active++ && pll->on) {
1589 assert_pch_pll_enabled(dev_priv, pll, NULL);
1590 return;
1591 }
1592
1593 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1594
1595 reg = pll->pll_reg;
1596 val = I915_READ(reg);
1597 val |= DPLL_VCO_ENABLE;
1598 I915_WRITE(reg, val);
1599 POSTING_READ(reg);
1600 udelay(200);
1601
1602 pll->on = true;
1603 }
1604
1605 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1606 {
1607 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1608 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1609 int reg;
1610 u32 val;
1611
1612 /* PCH only available on ILK+ */
1613 BUG_ON(dev_priv->info->gen < 5);
1614 if (pll == NULL)
1615 return;
1616
1617 if (WARN_ON(pll->refcount == 0))
1618 return;
1619
1620 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1621 pll->pll_reg, pll->active, pll->on,
1622 intel_crtc->base.base.id);
1623
1624 if (WARN_ON(pll->active == 0)) {
1625 assert_pch_pll_disabled(dev_priv, pll, NULL);
1626 return;
1627 }
1628
1629 if (--pll->active) {
1630 assert_pch_pll_enabled(dev_priv, pll, NULL);
1631 return;
1632 }
1633
1634 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1635
1636 /* Make sure transcoder isn't still depending on us */
1637 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1638
1639 reg = pll->pll_reg;
1640 val = I915_READ(reg);
1641 val &= ~DPLL_VCO_ENABLE;
1642 I915_WRITE(reg, val);
1643 POSTING_READ(reg);
1644 udelay(200);
1645
1646 pll->on = false;
1647 }
1648
1649 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1650 enum pipe pipe)
1651 {
1652 struct drm_device *dev = dev_priv->dev;
1653 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1654 uint32_t reg, val, pipeconf_val;
1655
1656 /* PCH only available on ILK+ */
1657 BUG_ON(dev_priv->info->gen < 5);
1658
1659 /* Make sure PCH DPLL is enabled */
1660 assert_pch_pll_enabled(dev_priv,
1661 to_intel_crtc(crtc)->pch_pll,
1662 to_intel_crtc(crtc));
1663
1664 /* FDI must be feeding us bits for PCH ports */
1665 assert_fdi_tx_enabled(dev_priv, pipe);
1666 assert_fdi_rx_enabled(dev_priv, pipe);
1667
1668 if (HAS_PCH_CPT(dev)) {
1669 /* Workaround: Set the timing override bit before enabling the
1670 * pch transcoder. */
1671 reg = TRANS_CHICKEN2(pipe);
1672 val = I915_READ(reg);
1673 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1674 I915_WRITE(reg, val);
1675 }
1676
1677 reg = TRANSCONF(pipe);
1678 val = I915_READ(reg);
1679 pipeconf_val = I915_READ(PIPECONF(pipe));
1680
1681 if (HAS_PCH_IBX(dev_priv->dev)) {
1682 /*
1683 * make the BPC in transcoder be consistent with
1684 * that in pipeconf reg.
1685 */
1686 val &= ~PIPECONF_BPC_MASK;
1687 val |= pipeconf_val & PIPECONF_BPC_MASK;
1688 }
1689
1690 val &= ~TRANS_INTERLACE_MASK;
1691 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1692 if (HAS_PCH_IBX(dev_priv->dev) &&
1693 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1694 val |= TRANS_LEGACY_INTERLACED_ILK;
1695 else
1696 val |= TRANS_INTERLACED;
1697 else
1698 val |= TRANS_PROGRESSIVE;
1699
1700 I915_WRITE(reg, val | TRANS_ENABLE);
1701 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1702 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1703 }
1704
1705 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1706 enum transcoder cpu_transcoder)
1707 {
1708 u32 val, pipeconf_val;
1709
1710 /* PCH only available on ILK+ */
1711 BUG_ON(dev_priv->info->gen < 5);
1712
1713 /* FDI must be feeding us bits for PCH ports */
1714 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1715 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1716
1717 /* Workaround: set timing override bit. */
1718 val = I915_READ(_TRANSA_CHICKEN2);
1719 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1720 I915_WRITE(_TRANSA_CHICKEN2, val);
1721
1722 val = TRANS_ENABLE;
1723 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1724
1725 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1726 PIPECONF_INTERLACED_ILK)
1727 val |= TRANS_INTERLACED;
1728 else
1729 val |= TRANS_PROGRESSIVE;
1730
1731 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
1732 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1733 DRM_ERROR("Failed to enable PCH transcoder\n");
1734 }
1735
1736 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1737 enum pipe pipe)
1738 {
1739 struct drm_device *dev = dev_priv->dev;
1740 uint32_t reg, val;
1741
1742 /* FDI relies on the transcoder */
1743 assert_fdi_tx_disabled(dev_priv, pipe);
1744 assert_fdi_rx_disabled(dev_priv, pipe);
1745
1746 /* Ports must be off as well */
1747 assert_pch_ports_disabled(dev_priv, pipe);
1748
1749 reg = TRANSCONF(pipe);
1750 val = I915_READ(reg);
1751 val &= ~TRANS_ENABLE;
1752 I915_WRITE(reg, val);
1753 /* wait for PCH transcoder off, transcoder state */
1754 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1755 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1756
1757 if (!HAS_PCH_IBX(dev)) {
1758 /* Workaround: Clear the timing override chicken bit again. */
1759 reg = TRANS_CHICKEN2(pipe);
1760 val = I915_READ(reg);
1761 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1762 I915_WRITE(reg, val);
1763 }
1764 }
1765
1766 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1767 {
1768 u32 val;
1769
1770 val = I915_READ(_TRANSACONF);
1771 val &= ~TRANS_ENABLE;
1772 I915_WRITE(_TRANSACONF, val);
1773 /* wait for PCH transcoder off, transcoder state */
1774 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1775 DRM_ERROR("Failed to disable PCH transcoder\n");
1776
1777 /* Workaround: clear timing override bit. */
1778 val = I915_READ(_TRANSA_CHICKEN2);
1779 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1780 I915_WRITE(_TRANSA_CHICKEN2, val);
1781 }
1782
1783 /**
1784 * intel_enable_pipe - enable a pipe, asserting requirements
1785 * @dev_priv: i915 private structure
1786 * @pipe: pipe to enable
1787 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1788 *
1789 * Enable @pipe, making sure that various hardware specific requirements
1790 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1791 *
1792 * @pipe should be %PIPE_A or %PIPE_B.
1793 *
1794 * Will wait until the pipe is actually running (i.e. first vblank) before
1795 * returning.
1796 */
1797 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1798 bool pch_port)
1799 {
1800 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1801 pipe);
1802 enum pipe pch_transcoder;
1803 int reg;
1804 u32 val;
1805
1806 if (HAS_PCH_LPT(dev_priv->dev))
1807 pch_transcoder = TRANSCODER_A;
1808 else
1809 pch_transcoder = pipe;
1810
1811 /*
1812 * A pipe without a PLL won't actually be able to drive bits from
1813 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1814 * need the check.
1815 */
1816 if (!HAS_PCH_SPLIT(dev_priv->dev))
1817 assert_pll_enabled(dev_priv, pipe);
1818 else {
1819 if (pch_port) {
1820 /* if driving the PCH, we need FDI enabled */
1821 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1822 assert_fdi_tx_pll_enabled(dev_priv,
1823 (enum pipe) cpu_transcoder);
1824 }
1825 /* FIXME: assert CPU port conditions for SNB+ */
1826 }
1827
1828 reg = PIPECONF(cpu_transcoder);
1829 val = I915_READ(reg);
1830 if (val & PIPECONF_ENABLE)
1831 return;
1832
1833 I915_WRITE(reg, val | PIPECONF_ENABLE);
1834 intel_wait_for_vblank(dev_priv->dev, pipe);
1835 }
1836
1837 /**
1838 * intel_disable_pipe - disable a pipe, asserting requirements
1839 * @dev_priv: i915 private structure
1840 * @pipe: pipe to disable
1841 *
1842 * Disable @pipe, making sure that various hardware specific requirements
1843 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1844 *
1845 * @pipe should be %PIPE_A or %PIPE_B.
1846 *
1847 * Will wait until the pipe has shut down before returning.
1848 */
1849 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1850 enum pipe pipe)
1851 {
1852 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1853 pipe);
1854 int reg;
1855 u32 val;
1856
1857 /*
1858 * Make sure planes won't keep trying to pump pixels to us,
1859 * or we might hang the display.
1860 */
1861 assert_planes_disabled(dev_priv, pipe);
1862
1863 /* Don't disable pipe A or pipe A PLLs if needed */
1864 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1865 return;
1866
1867 reg = PIPECONF(cpu_transcoder);
1868 val = I915_READ(reg);
1869 if ((val & PIPECONF_ENABLE) == 0)
1870 return;
1871
1872 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1873 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1874 }
1875
1876 /*
1877 * Plane regs are double buffered, going from enabled->disabled needs a
1878 * trigger in order to latch. The display address reg provides this.
1879 */
1880 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1881 enum plane plane)
1882 {
1883 if (dev_priv->info->gen >= 4)
1884 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1885 else
1886 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1887 }
1888
1889 /**
1890 * intel_enable_plane - enable a display plane on a given pipe
1891 * @dev_priv: i915 private structure
1892 * @plane: plane to enable
1893 * @pipe: pipe being fed
1894 *
1895 * Enable @plane on @pipe, making sure that @pipe is running first.
1896 */
1897 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1898 enum plane plane, enum pipe pipe)
1899 {
1900 int reg;
1901 u32 val;
1902
1903 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1904 assert_pipe_enabled(dev_priv, pipe);
1905
1906 reg = DSPCNTR(plane);
1907 val = I915_READ(reg);
1908 if (val & DISPLAY_PLANE_ENABLE)
1909 return;
1910
1911 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1912 intel_flush_display_plane(dev_priv, plane);
1913 intel_wait_for_vblank(dev_priv->dev, pipe);
1914 }
1915
1916 /**
1917 * intel_disable_plane - disable a display plane
1918 * @dev_priv: i915 private structure
1919 * @plane: plane to disable
1920 * @pipe: pipe consuming the data
1921 *
1922 * Disable @plane; should be an independent operation.
1923 */
1924 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1925 enum plane plane, enum pipe pipe)
1926 {
1927 int reg;
1928 u32 val;
1929
1930 reg = DSPCNTR(plane);
1931 val = I915_READ(reg);
1932 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1933 return;
1934
1935 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1936 intel_flush_display_plane(dev_priv, plane);
1937 intel_wait_for_vblank(dev_priv->dev, pipe);
1938 }
1939
1940 int
1941 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1942 struct drm_i915_gem_object *obj,
1943 struct intel_ring_buffer *pipelined)
1944 {
1945 struct drm_i915_private *dev_priv = dev->dev_private;
1946 u32 alignment;
1947 int ret;
1948
1949 switch (obj->tiling_mode) {
1950 case I915_TILING_NONE:
1951 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1952 alignment = 128 * 1024;
1953 else if (INTEL_INFO(dev)->gen >= 4)
1954 alignment = 4 * 1024;
1955 else
1956 alignment = 64 * 1024;
1957 break;
1958 case I915_TILING_X:
1959 /* pin() will align the object as required by fence */
1960 alignment = 0;
1961 break;
1962 case I915_TILING_Y:
1963 /* FIXME: Is this true? */
1964 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1965 return -EINVAL;
1966 default:
1967 BUG();
1968 }
1969
1970 dev_priv->mm.interruptible = false;
1971 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1972 if (ret)
1973 goto err_interruptible;
1974
1975 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1976 * fence, whereas 965+ only requires a fence if using
1977 * framebuffer compression. For simplicity, we always install
1978 * a fence as the cost is not that onerous.
1979 */
1980 ret = i915_gem_object_get_fence(obj);
1981 if (ret)
1982 goto err_unpin;
1983
1984 i915_gem_object_pin_fence(obj);
1985
1986 dev_priv->mm.interruptible = true;
1987 return 0;
1988
1989 err_unpin:
1990 i915_gem_object_unpin(obj);
1991 err_interruptible:
1992 dev_priv->mm.interruptible = true;
1993 return ret;
1994 }
1995
1996 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1997 {
1998 i915_gem_object_unpin_fence(obj);
1999 i915_gem_object_unpin(obj);
2000 }
2001
2002 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2003 * is assumed to be a power-of-two. */
2004 unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
2005 unsigned int bpp,
2006 unsigned int pitch)
2007 {
2008 int tile_rows, tiles;
2009
2010 tile_rows = *y / 8;
2011 *y %= 8;
2012 tiles = *x / (512/bpp);
2013 *x %= 512/bpp;
2014
2015 return tile_rows * pitch * 8 + tiles * 4096;
2016 }
2017
2018 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2019 int x, int y)
2020 {
2021 struct drm_device *dev = crtc->dev;
2022 struct drm_i915_private *dev_priv = dev->dev_private;
2023 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2024 struct intel_framebuffer *intel_fb;
2025 struct drm_i915_gem_object *obj;
2026 int plane = intel_crtc->plane;
2027 unsigned long linear_offset;
2028 u32 dspcntr;
2029 u32 reg;
2030
2031 switch (plane) {
2032 case 0:
2033 case 1:
2034 break;
2035 default:
2036 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2037 return -EINVAL;
2038 }
2039
2040 intel_fb = to_intel_framebuffer(fb);
2041 obj = intel_fb->obj;
2042
2043 reg = DSPCNTR(plane);
2044 dspcntr = I915_READ(reg);
2045 /* Mask out pixel format bits in case we change it */
2046 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2047 switch (fb->pixel_format) {
2048 case DRM_FORMAT_C8:
2049 dspcntr |= DISPPLANE_8BPP;
2050 break;
2051 case DRM_FORMAT_XRGB1555:
2052 case DRM_FORMAT_ARGB1555:
2053 dspcntr |= DISPPLANE_BGRX555;
2054 break;
2055 case DRM_FORMAT_RGB565:
2056 dspcntr |= DISPPLANE_BGRX565;
2057 break;
2058 case DRM_FORMAT_XRGB8888:
2059 case DRM_FORMAT_ARGB8888:
2060 dspcntr |= DISPPLANE_BGRX888;
2061 break;
2062 case DRM_FORMAT_XBGR8888:
2063 case DRM_FORMAT_ABGR8888:
2064 dspcntr |= DISPPLANE_RGBX888;
2065 break;
2066 case DRM_FORMAT_XRGB2101010:
2067 case DRM_FORMAT_ARGB2101010:
2068 dspcntr |= DISPPLANE_BGRX101010;
2069 break;
2070 case DRM_FORMAT_XBGR2101010:
2071 case DRM_FORMAT_ABGR2101010:
2072 dspcntr |= DISPPLANE_RGBX101010;
2073 break;
2074 default:
2075 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2076 return -EINVAL;
2077 }
2078
2079 if (INTEL_INFO(dev)->gen >= 4) {
2080 if (obj->tiling_mode != I915_TILING_NONE)
2081 dspcntr |= DISPPLANE_TILED;
2082 else
2083 dspcntr &= ~DISPPLANE_TILED;
2084 }
2085
2086 I915_WRITE(reg, dspcntr);
2087
2088 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2089
2090 if (INTEL_INFO(dev)->gen >= 4) {
2091 intel_crtc->dspaddr_offset =
2092 intel_gen4_compute_offset_xtiled(&x, &y,
2093 fb->bits_per_pixel / 8,
2094 fb->pitches[0]);
2095 linear_offset -= intel_crtc->dspaddr_offset;
2096 } else {
2097 intel_crtc->dspaddr_offset = linear_offset;
2098 }
2099
2100 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2101 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2102 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2103 if (INTEL_INFO(dev)->gen >= 4) {
2104 I915_MODIFY_DISPBASE(DSPSURF(plane),
2105 obj->gtt_offset + intel_crtc->dspaddr_offset);
2106 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2107 I915_WRITE(DSPLINOFF(plane), linear_offset);
2108 } else
2109 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2110 POSTING_READ(reg);
2111
2112 return 0;
2113 }
2114
2115 static int ironlake_update_plane(struct drm_crtc *crtc,
2116 struct drm_framebuffer *fb, int x, int y)
2117 {
2118 struct drm_device *dev = crtc->dev;
2119 struct drm_i915_private *dev_priv = dev->dev_private;
2120 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2121 struct intel_framebuffer *intel_fb;
2122 struct drm_i915_gem_object *obj;
2123 int plane = intel_crtc->plane;
2124 unsigned long linear_offset;
2125 u32 dspcntr;
2126 u32 reg;
2127
2128 switch (plane) {
2129 case 0:
2130 case 1:
2131 case 2:
2132 break;
2133 default:
2134 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2135 return -EINVAL;
2136 }
2137
2138 intel_fb = to_intel_framebuffer(fb);
2139 obj = intel_fb->obj;
2140
2141 reg = DSPCNTR(plane);
2142 dspcntr = I915_READ(reg);
2143 /* Mask out pixel format bits in case we change it */
2144 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2145 switch (fb->pixel_format) {
2146 case DRM_FORMAT_C8:
2147 dspcntr |= DISPPLANE_8BPP;
2148 break;
2149 case DRM_FORMAT_RGB565:
2150 dspcntr |= DISPPLANE_BGRX565;
2151 break;
2152 case DRM_FORMAT_XRGB8888:
2153 case DRM_FORMAT_ARGB8888:
2154 dspcntr |= DISPPLANE_BGRX888;
2155 break;
2156 case DRM_FORMAT_XBGR8888:
2157 case DRM_FORMAT_ABGR8888:
2158 dspcntr |= DISPPLANE_RGBX888;
2159 break;
2160 case DRM_FORMAT_XRGB2101010:
2161 case DRM_FORMAT_ARGB2101010:
2162 dspcntr |= DISPPLANE_BGRX101010;
2163 break;
2164 case DRM_FORMAT_XBGR2101010:
2165 case DRM_FORMAT_ABGR2101010:
2166 dspcntr |= DISPPLANE_RGBX101010;
2167 break;
2168 default:
2169 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2170 return -EINVAL;
2171 }
2172
2173 if (obj->tiling_mode != I915_TILING_NONE)
2174 dspcntr |= DISPPLANE_TILED;
2175 else
2176 dspcntr &= ~DISPPLANE_TILED;
2177
2178 /* must disable */
2179 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2180
2181 I915_WRITE(reg, dspcntr);
2182
2183 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2184 intel_crtc->dspaddr_offset =
2185 intel_gen4_compute_offset_xtiled(&x, &y,
2186 fb->bits_per_pixel / 8,
2187 fb->pitches[0]);
2188 linear_offset -= intel_crtc->dspaddr_offset;
2189
2190 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2191 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2192 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2193 I915_MODIFY_DISPBASE(DSPSURF(plane),
2194 obj->gtt_offset + intel_crtc->dspaddr_offset);
2195 if (IS_HASWELL(dev)) {
2196 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2197 } else {
2198 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2199 I915_WRITE(DSPLINOFF(plane), linear_offset);
2200 }
2201 POSTING_READ(reg);
2202
2203 return 0;
2204 }
2205
2206 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2207 static int
2208 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2209 int x, int y, enum mode_set_atomic state)
2210 {
2211 struct drm_device *dev = crtc->dev;
2212 struct drm_i915_private *dev_priv = dev->dev_private;
2213
2214 if (dev_priv->display.disable_fbc)
2215 dev_priv->display.disable_fbc(dev);
2216 intel_increase_pllclock(crtc);
2217
2218 return dev_priv->display.update_plane(crtc, fb, x, y);
2219 }
2220
2221 void intel_display_handle_reset(struct drm_device *dev)
2222 {
2223 struct drm_i915_private *dev_priv = dev->dev_private;
2224 struct drm_crtc *crtc;
2225
2226 /*
2227 * Flips in the rings have been nuked by the reset,
2228 * so complete all pending flips so that user space
2229 * will get its events and not get stuck.
2230 *
2231 * Also update the base address of all primary
2232 * planes to the the last fb to make sure we're
2233 * showing the correct fb after a reset.
2234 *
2235 * Need to make two loops over the crtcs so that we
2236 * don't try to grab a crtc mutex before the
2237 * pending_flip_queue really got woken up.
2238 */
2239
2240 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2241 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2242 enum plane plane = intel_crtc->plane;
2243
2244 intel_prepare_page_flip(dev, plane);
2245 intel_finish_page_flip_plane(dev, plane);
2246 }
2247
2248 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2249 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2250
2251 mutex_lock(&crtc->mutex);
2252 if (intel_crtc->active)
2253 dev_priv->display.update_plane(crtc, crtc->fb,
2254 crtc->x, crtc->y);
2255 mutex_unlock(&crtc->mutex);
2256 }
2257 }
2258
2259 static int
2260 intel_finish_fb(struct drm_framebuffer *old_fb)
2261 {
2262 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2263 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2264 bool was_interruptible = dev_priv->mm.interruptible;
2265 int ret;
2266
2267 /* Big Hammer, we also need to ensure that any pending
2268 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2269 * current scanout is retired before unpinning the old
2270 * framebuffer.
2271 *
2272 * This should only fail upon a hung GPU, in which case we
2273 * can safely continue.
2274 */
2275 dev_priv->mm.interruptible = false;
2276 ret = i915_gem_object_finish_gpu(obj);
2277 dev_priv->mm.interruptible = was_interruptible;
2278
2279 return ret;
2280 }
2281
2282 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2283 {
2284 struct drm_device *dev = crtc->dev;
2285 struct drm_i915_master_private *master_priv;
2286 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2287
2288 if (!dev->primary->master)
2289 return;
2290
2291 master_priv = dev->primary->master->driver_priv;
2292 if (!master_priv->sarea_priv)
2293 return;
2294
2295 switch (intel_crtc->pipe) {
2296 case 0:
2297 master_priv->sarea_priv->pipeA_x = x;
2298 master_priv->sarea_priv->pipeA_y = y;
2299 break;
2300 case 1:
2301 master_priv->sarea_priv->pipeB_x = x;
2302 master_priv->sarea_priv->pipeB_y = y;
2303 break;
2304 default:
2305 break;
2306 }
2307 }
2308
2309 static int
2310 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2311 struct drm_framebuffer *fb)
2312 {
2313 struct drm_device *dev = crtc->dev;
2314 struct drm_i915_private *dev_priv = dev->dev_private;
2315 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2316 struct drm_framebuffer *old_fb;
2317 int ret;
2318
2319 /* no fb bound */
2320 if (!fb) {
2321 DRM_ERROR("No FB bound\n");
2322 return 0;
2323 }
2324
2325 if(intel_crtc->plane > dev_priv->num_pipe) {
2326 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2327 intel_crtc->plane,
2328 dev_priv->num_pipe);
2329 return -EINVAL;
2330 }
2331
2332 mutex_lock(&dev->struct_mutex);
2333 ret = intel_pin_and_fence_fb_obj(dev,
2334 to_intel_framebuffer(fb)->obj,
2335 NULL);
2336 if (ret != 0) {
2337 mutex_unlock(&dev->struct_mutex);
2338 DRM_ERROR("pin & fence failed\n");
2339 return ret;
2340 }
2341
2342 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2343 if (ret) {
2344 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2345 mutex_unlock(&dev->struct_mutex);
2346 DRM_ERROR("failed to update base address\n");
2347 return ret;
2348 }
2349
2350 old_fb = crtc->fb;
2351 crtc->fb = fb;
2352 crtc->x = x;
2353 crtc->y = y;
2354
2355 if (old_fb) {
2356 intel_wait_for_vblank(dev, intel_crtc->pipe);
2357 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2358 }
2359
2360 intel_update_fbc(dev);
2361 mutex_unlock(&dev->struct_mutex);
2362
2363 intel_crtc_update_sarea_pos(crtc, x, y);
2364
2365 return 0;
2366 }
2367
2368 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2369 {
2370 struct drm_device *dev = crtc->dev;
2371 struct drm_i915_private *dev_priv = dev->dev_private;
2372 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2373 int pipe = intel_crtc->pipe;
2374 u32 reg, temp;
2375
2376 /* enable normal train */
2377 reg = FDI_TX_CTL(pipe);
2378 temp = I915_READ(reg);
2379 if (IS_IVYBRIDGE(dev)) {
2380 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2381 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2382 } else {
2383 temp &= ~FDI_LINK_TRAIN_NONE;
2384 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2385 }
2386 I915_WRITE(reg, temp);
2387
2388 reg = FDI_RX_CTL(pipe);
2389 temp = I915_READ(reg);
2390 if (HAS_PCH_CPT(dev)) {
2391 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2392 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2393 } else {
2394 temp &= ~FDI_LINK_TRAIN_NONE;
2395 temp |= FDI_LINK_TRAIN_NONE;
2396 }
2397 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2398
2399 /* wait one idle pattern time */
2400 POSTING_READ(reg);
2401 udelay(1000);
2402
2403 /* IVB wants error correction enabled */
2404 if (IS_IVYBRIDGE(dev))
2405 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2406 FDI_FE_ERRC_ENABLE);
2407 }
2408
2409 static void ivb_modeset_global_resources(struct drm_device *dev)
2410 {
2411 struct drm_i915_private *dev_priv = dev->dev_private;
2412 struct intel_crtc *pipe_B_crtc =
2413 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2414 struct intel_crtc *pipe_C_crtc =
2415 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2416 uint32_t temp;
2417
2418 /* When everything is off disable fdi C so that we could enable fdi B
2419 * with all lanes. XXX: This misses the case where a pipe is not using
2420 * any pch resources and so doesn't need any fdi lanes. */
2421 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2422 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2423 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2424
2425 temp = I915_READ(SOUTH_CHICKEN1);
2426 temp &= ~FDI_BC_BIFURCATION_SELECT;
2427 DRM_DEBUG_KMS("disabling fdi C rx\n");
2428 I915_WRITE(SOUTH_CHICKEN1, temp);
2429 }
2430 }
2431
2432 /* The FDI link training functions for ILK/Ibexpeak. */
2433 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2434 {
2435 struct drm_device *dev = crtc->dev;
2436 struct drm_i915_private *dev_priv = dev->dev_private;
2437 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2438 int pipe = intel_crtc->pipe;
2439 int plane = intel_crtc->plane;
2440 u32 reg, temp, tries;
2441
2442 /* FDI needs bits from pipe & plane first */
2443 assert_pipe_enabled(dev_priv, pipe);
2444 assert_plane_enabled(dev_priv, plane);
2445
2446 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2447 for train result */
2448 reg = FDI_RX_IMR(pipe);
2449 temp = I915_READ(reg);
2450 temp &= ~FDI_RX_SYMBOL_LOCK;
2451 temp &= ~FDI_RX_BIT_LOCK;
2452 I915_WRITE(reg, temp);
2453 I915_READ(reg);
2454 udelay(150);
2455
2456 /* enable CPU FDI TX and PCH FDI RX */
2457 reg = FDI_TX_CTL(pipe);
2458 temp = I915_READ(reg);
2459 temp &= ~(7 << 19);
2460 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2461 temp &= ~FDI_LINK_TRAIN_NONE;
2462 temp |= FDI_LINK_TRAIN_PATTERN_1;
2463 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2464
2465 reg = FDI_RX_CTL(pipe);
2466 temp = I915_READ(reg);
2467 temp &= ~FDI_LINK_TRAIN_NONE;
2468 temp |= FDI_LINK_TRAIN_PATTERN_1;
2469 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2470
2471 POSTING_READ(reg);
2472 udelay(150);
2473
2474 /* Ironlake workaround, enable clock pointer after FDI enable*/
2475 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2476 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2477 FDI_RX_PHASE_SYNC_POINTER_EN);
2478
2479 reg = FDI_RX_IIR(pipe);
2480 for (tries = 0; tries < 5; tries++) {
2481 temp = I915_READ(reg);
2482 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2483
2484 if ((temp & FDI_RX_BIT_LOCK)) {
2485 DRM_DEBUG_KMS("FDI train 1 done.\n");
2486 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2487 break;
2488 }
2489 }
2490 if (tries == 5)
2491 DRM_ERROR("FDI train 1 fail!\n");
2492
2493 /* Train 2 */
2494 reg = FDI_TX_CTL(pipe);
2495 temp = I915_READ(reg);
2496 temp &= ~FDI_LINK_TRAIN_NONE;
2497 temp |= FDI_LINK_TRAIN_PATTERN_2;
2498 I915_WRITE(reg, temp);
2499
2500 reg = FDI_RX_CTL(pipe);
2501 temp = I915_READ(reg);
2502 temp &= ~FDI_LINK_TRAIN_NONE;
2503 temp |= FDI_LINK_TRAIN_PATTERN_2;
2504 I915_WRITE(reg, temp);
2505
2506 POSTING_READ(reg);
2507 udelay(150);
2508
2509 reg = FDI_RX_IIR(pipe);
2510 for (tries = 0; tries < 5; tries++) {
2511 temp = I915_READ(reg);
2512 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2513
2514 if (temp & FDI_RX_SYMBOL_LOCK) {
2515 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2516 DRM_DEBUG_KMS("FDI train 2 done.\n");
2517 break;
2518 }
2519 }
2520 if (tries == 5)
2521 DRM_ERROR("FDI train 2 fail!\n");
2522
2523 DRM_DEBUG_KMS("FDI train done\n");
2524
2525 }
2526
2527 static const int snb_b_fdi_train_param[] = {
2528 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2529 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2530 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2531 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2532 };
2533
2534 /* The FDI link training functions for SNB/Cougarpoint. */
2535 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2536 {
2537 struct drm_device *dev = crtc->dev;
2538 struct drm_i915_private *dev_priv = dev->dev_private;
2539 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2540 int pipe = intel_crtc->pipe;
2541 u32 reg, temp, i, retry;
2542
2543 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2544 for train result */
2545 reg = FDI_RX_IMR(pipe);
2546 temp = I915_READ(reg);
2547 temp &= ~FDI_RX_SYMBOL_LOCK;
2548 temp &= ~FDI_RX_BIT_LOCK;
2549 I915_WRITE(reg, temp);
2550
2551 POSTING_READ(reg);
2552 udelay(150);
2553
2554 /* enable CPU FDI TX and PCH FDI RX */
2555 reg = FDI_TX_CTL(pipe);
2556 temp = I915_READ(reg);
2557 temp &= ~(7 << 19);
2558 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2559 temp &= ~FDI_LINK_TRAIN_NONE;
2560 temp |= FDI_LINK_TRAIN_PATTERN_1;
2561 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2562 /* SNB-B */
2563 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2564 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2565
2566 I915_WRITE(FDI_RX_MISC(pipe),
2567 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2568
2569 reg = FDI_RX_CTL(pipe);
2570 temp = I915_READ(reg);
2571 if (HAS_PCH_CPT(dev)) {
2572 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2573 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2574 } else {
2575 temp &= ~FDI_LINK_TRAIN_NONE;
2576 temp |= FDI_LINK_TRAIN_PATTERN_1;
2577 }
2578 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2579
2580 POSTING_READ(reg);
2581 udelay(150);
2582
2583 for (i = 0; i < 4; i++) {
2584 reg = FDI_TX_CTL(pipe);
2585 temp = I915_READ(reg);
2586 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2587 temp |= snb_b_fdi_train_param[i];
2588 I915_WRITE(reg, temp);
2589
2590 POSTING_READ(reg);
2591 udelay(500);
2592
2593 for (retry = 0; retry < 5; retry++) {
2594 reg = FDI_RX_IIR(pipe);
2595 temp = I915_READ(reg);
2596 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2597 if (temp & FDI_RX_BIT_LOCK) {
2598 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2599 DRM_DEBUG_KMS("FDI train 1 done.\n");
2600 break;
2601 }
2602 udelay(50);
2603 }
2604 if (retry < 5)
2605 break;
2606 }
2607 if (i == 4)
2608 DRM_ERROR("FDI train 1 fail!\n");
2609
2610 /* Train 2 */
2611 reg = FDI_TX_CTL(pipe);
2612 temp = I915_READ(reg);
2613 temp &= ~FDI_LINK_TRAIN_NONE;
2614 temp |= FDI_LINK_TRAIN_PATTERN_2;
2615 if (IS_GEN6(dev)) {
2616 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2617 /* SNB-B */
2618 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2619 }
2620 I915_WRITE(reg, temp);
2621
2622 reg = FDI_RX_CTL(pipe);
2623 temp = I915_READ(reg);
2624 if (HAS_PCH_CPT(dev)) {
2625 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2626 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2627 } else {
2628 temp &= ~FDI_LINK_TRAIN_NONE;
2629 temp |= FDI_LINK_TRAIN_PATTERN_2;
2630 }
2631 I915_WRITE(reg, temp);
2632
2633 POSTING_READ(reg);
2634 udelay(150);
2635
2636 for (i = 0; i < 4; i++) {
2637 reg = FDI_TX_CTL(pipe);
2638 temp = I915_READ(reg);
2639 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2640 temp |= snb_b_fdi_train_param[i];
2641 I915_WRITE(reg, temp);
2642
2643 POSTING_READ(reg);
2644 udelay(500);
2645
2646 for (retry = 0; retry < 5; retry++) {
2647 reg = FDI_RX_IIR(pipe);
2648 temp = I915_READ(reg);
2649 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2650 if (temp & FDI_RX_SYMBOL_LOCK) {
2651 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2652 DRM_DEBUG_KMS("FDI train 2 done.\n");
2653 break;
2654 }
2655 udelay(50);
2656 }
2657 if (retry < 5)
2658 break;
2659 }
2660 if (i == 4)
2661 DRM_ERROR("FDI train 2 fail!\n");
2662
2663 DRM_DEBUG_KMS("FDI train done.\n");
2664 }
2665
2666 /* Manual link training for Ivy Bridge A0 parts */
2667 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2668 {
2669 struct drm_device *dev = crtc->dev;
2670 struct drm_i915_private *dev_priv = dev->dev_private;
2671 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2672 int pipe = intel_crtc->pipe;
2673 u32 reg, temp, i;
2674
2675 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2676 for train result */
2677 reg = FDI_RX_IMR(pipe);
2678 temp = I915_READ(reg);
2679 temp &= ~FDI_RX_SYMBOL_LOCK;
2680 temp &= ~FDI_RX_BIT_LOCK;
2681 I915_WRITE(reg, temp);
2682
2683 POSTING_READ(reg);
2684 udelay(150);
2685
2686 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2687 I915_READ(FDI_RX_IIR(pipe)));
2688
2689 /* enable CPU FDI TX and PCH FDI RX */
2690 reg = FDI_TX_CTL(pipe);
2691 temp = I915_READ(reg);
2692 temp &= ~(7 << 19);
2693 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2694 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2695 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2696 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2697 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2698 temp |= FDI_COMPOSITE_SYNC;
2699 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2700
2701 I915_WRITE(FDI_RX_MISC(pipe),
2702 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2703
2704 reg = FDI_RX_CTL(pipe);
2705 temp = I915_READ(reg);
2706 temp &= ~FDI_LINK_TRAIN_AUTO;
2707 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2708 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2709 temp |= FDI_COMPOSITE_SYNC;
2710 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2711
2712 POSTING_READ(reg);
2713 udelay(150);
2714
2715 for (i = 0; i < 4; i++) {
2716 reg = FDI_TX_CTL(pipe);
2717 temp = I915_READ(reg);
2718 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2719 temp |= snb_b_fdi_train_param[i];
2720 I915_WRITE(reg, temp);
2721
2722 POSTING_READ(reg);
2723 udelay(500);
2724
2725 reg = FDI_RX_IIR(pipe);
2726 temp = I915_READ(reg);
2727 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2728
2729 if (temp & FDI_RX_BIT_LOCK ||
2730 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2731 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2732 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2733 break;
2734 }
2735 }
2736 if (i == 4)
2737 DRM_ERROR("FDI train 1 fail!\n");
2738
2739 /* Train 2 */
2740 reg = FDI_TX_CTL(pipe);
2741 temp = I915_READ(reg);
2742 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2743 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2744 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2745 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2746 I915_WRITE(reg, temp);
2747
2748 reg = FDI_RX_CTL(pipe);
2749 temp = I915_READ(reg);
2750 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2751 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2752 I915_WRITE(reg, temp);
2753
2754 POSTING_READ(reg);
2755 udelay(150);
2756
2757 for (i = 0; i < 4; i++) {
2758 reg = FDI_TX_CTL(pipe);
2759 temp = I915_READ(reg);
2760 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2761 temp |= snb_b_fdi_train_param[i];
2762 I915_WRITE(reg, temp);
2763
2764 POSTING_READ(reg);
2765 udelay(500);
2766
2767 reg = FDI_RX_IIR(pipe);
2768 temp = I915_READ(reg);
2769 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2770
2771 if (temp & FDI_RX_SYMBOL_LOCK) {
2772 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2773 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2774 break;
2775 }
2776 }
2777 if (i == 4)
2778 DRM_ERROR("FDI train 2 fail!\n");
2779
2780 DRM_DEBUG_KMS("FDI train done.\n");
2781 }
2782
2783 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2784 {
2785 struct drm_device *dev = intel_crtc->base.dev;
2786 struct drm_i915_private *dev_priv = dev->dev_private;
2787 int pipe = intel_crtc->pipe;
2788 u32 reg, temp;
2789
2790
2791 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2792 reg = FDI_RX_CTL(pipe);
2793 temp = I915_READ(reg);
2794 temp &= ~((0x7 << 19) | (0x7 << 16));
2795 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2796 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2797 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2798
2799 POSTING_READ(reg);
2800 udelay(200);
2801
2802 /* Switch from Rawclk to PCDclk */
2803 temp = I915_READ(reg);
2804 I915_WRITE(reg, temp | FDI_PCDCLK);
2805
2806 POSTING_READ(reg);
2807 udelay(200);
2808
2809 /* Enable CPU FDI TX PLL, always on for Ironlake */
2810 reg = FDI_TX_CTL(pipe);
2811 temp = I915_READ(reg);
2812 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2813 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2814
2815 POSTING_READ(reg);
2816 udelay(100);
2817 }
2818 }
2819
2820 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2821 {
2822 struct drm_device *dev = intel_crtc->base.dev;
2823 struct drm_i915_private *dev_priv = dev->dev_private;
2824 int pipe = intel_crtc->pipe;
2825 u32 reg, temp;
2826
2827 /* Switch from PCDclk to Rawclk */
2828 reg = FDI_RX_CTL(pipe);
2829 temp = I915_READ(reg);
2830 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2831
2832 /* Disable CPU FDI TX PLL */
2833 reg = FDI_TX_CTL(pipe);
2834 temp = I915_READ(reg);
2835 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2836
2837 POSTING_READ(reg);
2838 udelay(100);
2839
2840 reg = FDI_RX_CTL(pipe);
2841 temp = I915_READ(reg);
2842 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2843
2844 /* Wait for the clocks to turn off. */
2845 POSTING_READ(reg);
2846 udelay(100);
2847 }
2848
2849 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2850 {
2851 struct drm_device *dev = crtc->dev;
2852 struct drm_i915_private *dev_priv = dev->dev_private;
2853 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2854 int pipe = intel_crtc->pipe;
2855 u32 reg, temp;
2856
2857 /* disable CPU FDI tx and PCH FDI rx */
2858 reg = FDI_TX_CTL(pipe);
2859 temp = I915_READ(reg);
2860 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2861 POSTING_READ(reg);
2862
2863 reg = FDI_RX_CTL(pipe);
2864 temp = I915_READ(reg);
2865 temp &= ~(0x7 << 16);
2866 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2867 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2868
2869 POSTING_READ(reg);
2870 udelay(100);
2871
2872 /* Ironlake workaround, disable clock pointer after downing FDI */
2873 if (HAS_PCH_IBX(dev)) {
2874 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2875 }
2876
2877 /* still set train pattern 1 */
2878 reg = FDI_TX_CTL(pipe);
2879 temp = I915_READ(reg);
2880 temp &= ~FDI_LINK_TRAIN_NONE;
2881 temp |= FDI_LINK_TRAIN_PATTERN_1;
2882 I915_WRITE(reg, temp);
2883
2884 reg = FDI_RX_CTL(pipe);
2885 temp = I915_READ(reg);
2886 if (HAS_PCH_CPT(dev)) {
2887 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2888 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2889 } else {
2890 temp &= ~FDI_LINK_TRAIN_NONE;
2891 temp |= FDI_LINK_TRAIN_PATTERN_1;
2892 }
2893 /* BPC in FDI rx is consistent with that in PIPECONF */
2894 temp &= ~(0x07 << 16);
2895 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2896 I915_WRITE(reg, temp);
2897
2898 POSTING_READ(reg);
2899 udelay(100);
2900 }
2901
2902 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2903 {
2904 struct drm_device *dev = crtc->dev;
2905 struct drm_i915_private *dev_priv = dev->dev_private;
2906 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2907 unsigned long flags;
2908 bool pending;
2909
2910 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2911 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2912 return false;
2913
2914 spin_lock_irqsave(&dev->event_lock, flags);
2915 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2916 spin_unlock_irqrestore(&dev->event_lock, flags);
2917
2918 return pending;
2919 }
2920
2921 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2922 {
2923 struct drm_device *dev = crtc->dev;
2924 struct drm_i915_private *dev_priv = dev->dev_private;
2925
2926 if (crtc->fb == NULL)
2927 return;
2928
2929 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2930
2931 wait_event(dev_priv->pending_flip_queue,
2932 !intel_crtc_has_pending_flip(crtc));
2933
2934 mutex_lock(&dev->struct_mutex);
2935 intel_finish_fb(crtc->fb);
2936 mutex_unlock(&dev->struct_mutex);
2937 }
2938
2939 static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
2940 {
2941 struct drm_device *dev = crtc->dev;
2942 struct intel_encoder *intel_encoder;
2943
2944 /*
2945 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2946 * must be driven by its own crtc; no sharing is possible.
2947 */
2948 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2949 switch (intel_encoder->type) {
2950 case INTEL_OUTPUT_EDP:
2951 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2952 return false;
2953 continue;
2954 }
2955 }
2956
2957 return true;
2958 }
2959
2960 static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2961 {
2962 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2963 }
2964
2965 /* Program iCLKIP clock to the desired frequency */
2966 static void lpt_program_iclkip(struct drm_crtc *crtc)
2967 {
2968 struct drm_device *dev = crtc->dev;
2969 struct drm_i915_private *dev_priv = dev->dev_private;
2970 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2971 u32 temp;
2972
2973 mutex_lock(&dev_priv->dpio_lock);
2974
2975 /* It is necessary to ungate the pixclk gate prior to programming
2976 * the divisors, and gate it back when it is done.
2977 */
2978 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2979
2980 /* Disable SSCCTL */
2981 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2982 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2983 SBI_SSCCTL_DISABLE,
2984 SBI_ICLK);
2985
2986 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2987 if (crtc->mode.clock == 20000) {
2988 auxdiv = 1;
2989 divsel = 0x41;
2990 phaseinc = 0x20;
2991 } else {
2992 /* The iCLK virtual clock root frequency is in MHz,
2993 * but the crtc->mode.clock in in KHz. To get the divisors,
2994 * it is necessary to divide one by another, so we
2995 * convert the virtual clock precision to KHz here for higher
2996 * precision.
2997 */
2998 u32 iclk_virtual_root_freq = 172800 * 1000;
2999 u32 iclk_pi_range = 64;
3000 u32 desired_divisor, msb_divisor_value, pi_value;
3001
3002 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3003 msb_divisor_value = desired_divisor / iclk_pi_range;
3004 pi_value = desired_divisor % iclk_pi_range;
3005
3006 auxdiv = 0;
3007 divsel = msb_divisor_value - 2;
3008 phaseinc = pi_value;
3009 }
3010
3011 /* This should not happen with any sane values */
3012 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3013 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3014 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3015 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3016
3017 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3018 crtc->mode.clock,
3019 auxdiv,
3020 divsel,
3021 phasedir,
3022 phaseinc);
3023
3024 /* Program SSCDIVINTPHASE6 */
3025 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3026 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3027 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3028 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3029 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3030 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3031 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3032 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3033
3034 /* Program SSCAUXDIV */
3035 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3036 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3037 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3038 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3039
3040 /* Enable modulator and associated divider */
3041 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3042 temp &= ~SBI_SSCCTL_DISABLE;
3043 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3044
3045 /* Wait for initialization time */
3046 udelay(24);
3047
3048 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3049
3050 mutex_unlock(&dev_priv->dpio_lock);
3051 }
3052
3053 /*
3054 * Enable PCH resources required for PCH ports:
3055 * - PCH PLLs
3056 * - FDI training & RX/TX
3057 * - update transcoder timings
3058 * - DP transcoding bits
3059 * - transcoder
3060 */
3061 static void ironlake_pch_enable(struct drm_crtc *crtc)
3062 {
3063 struct drm_device *dev = crtc->dev;
3064 struct drm_i915_private *dev_priv = dev->dev_private;
3065 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3066 int pipe = intel_crtc->pipe;
3067 u32 reg, temp;
3068
3069 assert_transcoder_disabled(dev_priv, pipe);
3070
3071 /* Write the TU size bits before fdi link training, so that error
3072 * detection works. */
3073 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3074 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3075
3076 /* For PCH output, training FDI link */
3077 dev_priv->display.fdi_link_train(crtc);
3078
3079 /* XXX: pch pll's can be enabled any time before we enable the PCH
3080 * transcoder, and we actually should do this to not upset any PCH
3081 * transcoder that already use the clock when we share it.
3082 *
3083 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3084 * unconditionally resets the pll - we need that to have the right LVDS
3085 * enable sequence. */
3086 ironlake_enable_pch_pll(intel_crtc);
3087
3088 if (HAS_PCH_CPT(dev)) {
3089 u32 sel;
3090
3091 temp = I915_READ(PCH_DPLL_SEL);
3092 switch (pipe) {
3093 default:
3094 case 0:
3095 temp |= TRANSA_DPLL_ENABLE;
3096 sel = TRANSA_DPLLB_SEL;
3097 break;
3098 case 1:
3099 temp |= TRANSB_DPLL_ENABLE;
3100 sel = TRANSB_DPLLB_SEL;
3101 break;
3102 case 2:
3103 temp |= TRANSC_DPLL_ENABLE;
3104 sel = TRANSC_DPLLB_SEL;
3105 break;
3106 }
3107 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3108 temp |= sel;
3109 else
3110 temp &= ~sel;
3111 I915_WRITE(PCH_DPLL_SEL, temp);
3112 }
3113
3114 /* set transcoder timing, panel must allow it */
3115 assert_panel_unlocked(dev_priv, pipe);
3116 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3117 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3118 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
3119
3120 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3121 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3122 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
3123 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
3124
3125 intel_fdi_normal_train(crtc);
3126
3127 /* For PCH DP, enable TRANS_DP_CTL */
3128 if (HAS_PCH_CPT(dev) &&
3129 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3130 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3131 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3132 reg = TRANS_DP_CTL(pipe);
3133 temp = I915_READ(reg);
3134 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3135 TRANS_DP_SYNC_MASK |
3136 TRANS_DP_BPC_MASK);
3137 temp |= (TRANS_DP_OUTPUT_ENABLE |
3138 TRANS_DP_ENH_FRAMING);
3139 temp |= bpc << 9; /* same format but at 11:9 */
3140
3141 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3142 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3143 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3144 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3145
3146 switch (intel_trans_dp_port_sel(crtc)) {
3147 case PCH_DP_B:
3148 temp |= TRANS_DP_PORT_SEL_B;
3149 break;
3150 case PCH_DP_C:
3151 temp |= TRANS_DP_PORT_SEL_C;
3152 break;
3153 case PCH_DP_D:
3154 temp |= TRANS_DP_PORT_SEL_D;
3155 break;
3156 default:
3157 BUG();
3158 }
3159
3160 I915_WRITE(reg, temp);
3161 }
3162
3163 ironlake_enable_pch_transcoder(dev_priv, pipe);
3164 }
3165
3166 static void lpt_pch_enable(struct drm_crtc *crtc)
3167 {
3168 struct drm_device *dev = crtc->dev;
3169 struct drm_i915_private *dev_priv = dev->dev_private;
3170 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3171 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3172
3173 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
3174
3175 lpt_program_iclkip(crtc);
3176
3177 /* Set transcoder timing. */
3178 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3179 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3180 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
3181
3182 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3183 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3184 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3185 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
3186
3187 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3188 }
3189
3190 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3191 {
3192 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3193
3194 if (pll == NULL)
3195 return;
3196
3197 if (pll->refcount == 0) {
3198 WARN(1, "bad PCH PLL refcount\n");
3199 return;
3200 }
3201
3202 --pll->refcount;
3203 intel_crtc->pch_pll = NULL;
3204 }
3205
3206 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3207 {
3208 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3209 struct intel_pch_pll *pll;
3210 int i;
3211
3212 pll = intel_crtc->pch_pll;
3213 if (pll) {
3214 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3215 intel_crtc->base.base.id, pll->pll_reg);
3216 goto prepare;
3217 }
3218
3219 if (HAS_PCH_IBX(dev_priv->dev)) {
3220 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3221 i = intel_crtc->pipe;
3222 pll = &dev_priv->pch_plls[i];
3223
3224 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3225 intel_crtc->base.base.id, pll->pll_reg);
3226
3227 goto found;
3228 }
3229
3230 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3231 pll = &dev_priv->pch_plls[i];
3232
3233 /* Only want to check enabled timings first */
3234 if (pll->refcount == 0)
3235 continue;
3236
3237 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3238 fp == I915_READ(pll->fp0_reg)) {
3239 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3240 intel_crtc->base.base.id,
3241 pll->pll_reg, pll->refcount, pll->active);
3242
3243 goto found;
3244 }
3245 }
3246
3247 /* Ok no matching timings, maybe there's a free one? */
3248 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3249 pll = &dev_priv->pch_plls[i];
3250 if (pll->refcount == 0) {
3251 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3252 intel_crtc->base.base.id, pll->pll_reg);
3253 goto found;
3254 }
3255 }
3256
3257 return NULL;
3258
3259 found:
3260 intel_crtc->pch_pll = pll;
3261 pll->refcount++;
3262 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3263 prepare: /* separate function? */
3264 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3265
3266 /* Wait for the clocks to stabilize before rewriting the regs */
3267 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3268 POSTING_READ(pll->pll_reg);
3269 udelay(150);
3270
3271 I915_WRITE(pll->fp0_reg, fp);
3272 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3273 pll->on = false;
3274 return pll;
3275 }
3276
3277 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3278 {
3279 struct drm_i915_private *dev_priv = dev->dev_private;
3280 int dslreg = PIPEDSL(pipe);
3281 u32 temp;
3282
3283 temp = I915_READ(dslreg);
3284 udelay(500);
3285 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3286 if (wait_for(I915_READ(dslreg) != temp, 5))
3287 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3288 }
3289 }
3290
3291 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3292 {
3293 struct drm_device *dev = crtc->dev;
3294 struct drm_i915_private *dev_priv = dev->dev_private;
3295 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3296 struct intel_encoder *encoder;
3297 int pipe = intel_crtc->pipe;
3298 int plane = intel_crtc->plane;
3299 u32 temp;
3300 bool is_pch_port;
3301
3302 WARN_ON(!crtc->enabled);
3303
3304 if (intel_crtc->active)
3305 return;
3306
3307 intel_crtc->active = true;
3308 intel_update_watermarks(dev);
3309
3310 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3311 temp = I915_READ(PCH_LVDS);
3312 if ((temp & LVDS_PORT_EN) == 0)
3313 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3314 }
3315
3316 is_pch_port = ironlake_crtc_driving_pch(crtc);
3317
3318 if (is_pch_port) {
3319 /* Note: FDI PLL enabling _must_ be done before we enable the
3320 * cpu pipes, hence this is separate from all the other fdi/pch
3321 * enabling. */
3322 ironlake_fdi_pll_enable(intel_crtc);
3323 } else {
3324 assert_fdi_tx_disabled(dev_priv, pipe);
3325 assert_fdi_rx_disabled(dev_priv, pipe);
3326 }
3327
3328 for_each_encoder_on_crtc(dev, crtc, encoder)
3329 if (encoder->pre_enable)
3330 encoder->pre_enable(encoder);
3331
3332 /* Enable panel fitting for LVDS */
3333 if (dev_priv->pch_pf_size &&
3334 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3335 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3336 /* Force use of hard-coded filter coefficients
3337 * as some pre-programmed values are broken,
3338 * e.g. x201.
3339 */
3340 if (IS_IVYBRIDGE(dev))
3341 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3342 PF_PIPE_SEL_IVB(pipe));
3343 else
3344 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3345 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3346 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3347 }
3348
3349 /*
3350 * On ILK+ LUT must be loaded before the pipe is running but with
3351 * clocks enabled
3352 */
3353 intel_crtc_load_lut(crtc);
3354
3355 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3356 intel_enable_plane(dev_priv, plane, pipe);
3357
3358 if (is_pch_port)
3359 ironlake_pch_enable(crtc);
3360
3361 mutex_lock(&dev->struct_mutex);
3362 intel_update_fbc(dev);
3363 mutex_unlock(&dev->struct_mutex);
3364
3365 intel_crtc_update_cursor(crtc, true);
3366
3367 for_each_encoder_on_crtc(dev, crtc, encoder)
3368 encoder->enable(encoder);
3369
3370 if (HAS_PCH_CPT(dev))
3371 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3372
3373 /*
3374 * There seems to be a race in PCH platform hw (at least on some
3375 * outputs) where an enabled pipe still completes any pageflip right
3376 * away (as if the pipe is off) instead of waiting for vblank. As soon
3377 * as the first vblank happend, everything works as expected. Hence just
3378 * wait for one vblank before returning to avoid strange things
3379 * happening.
3380 */
3381 intel_wait_for_vblank(dev, intel_crtc->pipe);
3382 }
3383
3384 static void haswell_crtc_enable(struct drm_crtc *crtc)
3385 {
3386 struct drm_device *dev = crtc->dev;
3387 struct drm_i915_private *dev_priv = dev->dev_private;
3388 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3389 struct intel_encoder *encoder;
3390 int pipe = intel_crtc->pipe;
3391 int plane = intel_crtc->plane;
3392 bool is_pch_port;
3393
3394 WARN_ON(!crtc->enabled);
3395
3396 if (intel_crtc->active)
3397 return;
3398
3399 intel_crtc->active = true;
3400 intel_update_watermarks(dev);
3401
3402 is_pch_port = haswell_crtc_driving_pch(crtc);
3403
3404 if (is_pch_port)
3405 dev_priv->display.fdi_link_train(crtc);
3406
3407 for_each_encoder_on_crtc(dev, crtc, encoder)
3408 if (encoder->pre_enable)
3409 encoder->pre_enable(encoder);
3410
3411 intel_ddi_enable_pipe_clock(intel_crtc);
3412
3413 /* Enable panel fitting for eDP */
3414 if (dev_priv->pch_pf_size &&
3415 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3416 /* Force use of hard-coded filter coefficients
3417 * as some pre-programmed values are broken,
3418 * e.g. x201.
3419 */
3420 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3421 PF_PIPE_SEL_IVB(pipe));
3422 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3423 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3424 }
3425
3426 /*
3427 * On ILK+ LUT must be loaded before the pipe is running but with
3428 * clocks enabled
3429 */
3430 intel_crtc_load_lut(crtc);
3431
3432 intel_ddi_set_pipe_settings(crtc);
3433 intel_ddi_enable_pipe_func(crtc);
3434
3435 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3436 intel_enable_plane(dev_priv, plane, pipe);
3437
3438 if (is_pch_port)
3439 lpt_pch_enable(crtc);
3440
3441 mutex_lock(&dev->struct_mutex);
3442 intel_update_fbc(dev);
3443 mutex_unlock(&dev->struct_mutex);
3444
3445 intel_crtc_update_cursor(crtc, true);
3446
3447 for_each_encoder_on_crtc(dev, crtc, encoder)
3448 encoder->enable(encoder);
3449
3450 /*
3451 * There seems to be a race in PCH platform hw (at least on some
3452 * outputs) where an enabled pipe still completes any pageflip right
3453 * away (as if the pipe is off) instead of waiting for vblank. As soon
3454 * as the first vblank happend, everything works as expected. Hence just
3455 * wait for one vblank before returning to avoid strange things
3456 * happening.
3457 */
3458 intel_wait_for_vblank(dev, intel_crtc->pipe);
3459 }
3460
3461 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3462 {
3463 struct drm_device *dev = crtc->dev;
3464 struct drm_i915_private *dev_priv = dev->dev_private;
3465 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3466 struct intel_encoder *encoder;
3467 int pipe = intel_crtc->pipe;
3468 int plane = intel_crtc->plane;
3469 u32 reg, temp;
3470
3471
3472 if (!intel_crtc->active)
3473 return;
3474
3475 for_each_encoder_on_crtc(dev, crtc, encoder)
3476 encoder->disable(encoder);
3477
3478 intel_crtc_wait_for_pending_flips(crtc);
3479 drm_vblank_off(dev, pipe);
3480 intel_crtc_update_cursor(crtc, false);
3481
3482 intel_disable_plane(dev_priv, plane, pipe);
3483
3484 if (dev_priv->cfb_plane == plane)
3485 intel_disable_fbc(dev);
3486
3487 intel_disable_pipe(dev_priv, pipe);
3488
3489 /* Disable PF */
3490 I915_WRITE(PF_CTL(pipe), 0);
3491 I915_WRITE(PF_WIN_SZ(pipe), 0);
3492
3493 for_each_encoder_on_crtc(dev, crtc, encoder)
3494 if (encoder->post_disable)
3495 encoder->post_disable(encoder);
3496
3497 ironlake_fdi_disable(crtc);
3498
3499 ironlake_disable_pch_transcoder(dev_priv, pipe);
3500
3501 if (HAS_PCH_CPT(dev)) {
3502 /* disable TRANS_DP_CTL */
3503 reg = TRANS_DP_CTL(pipe);
3504 temp = I915_READ(reg);
3505 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3506 temp |= TRANS_DP_PORT_SEL_NONE;
3507 I915_WRITE(reg, temp);
3508
3509 /* disable DPLL_SEL */
3510 temp = I915_READ(PCH_DPLL_SEL);
3511 switch (pipe) {
3512 case 0:
3513 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3514 break;
3515 case 1:
3516 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3517 break;
3518 case 2:
3519 /* C shares PLL A or B */
3520 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3521 break;
3522 default:
3523 BUG(); /* wtf */
3524 }
3525 I915_WRITE(PCH_DPLL_SEL, temp);
3526 }
3527
3528 /* disable PCH DPLL */
3529 intel_disable_pch_pll(intel_crtc);
3530
3531 ironlake_fdi_pll_disable(intel_crtc);
3532
3533 intel_crtc->active = false;
3534 intel_update_watermarks(dev);
3535
3536 mutex_lock(&dev->struct_mutex);
3537 intel_update_fbc(dev);
3538 mutex_unlock(&dev->struct_mutex);
3539 }
3540
3541 static void haswell_crtc_disable(struct drm_crtc *crtc)
3542 {
3543 struct drm_device *dev = crtc->dev;
3544 struct drm_i915_private *dev_priv = dev->dev_private;
3545 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3546 struct intel_encoder *encoder;
3547 int pipe = intel_crtc->pipe;
3548 int plane = intel_crtc->plane;
3549 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3550 bool is_pch_port;
3551
3552 if (!intel_crtc->active)
3553 return;
3554
3555 is_pch_port = haswell_crtc_driving_pch(crtc);
3556
3557 for_each_encoder_on_crtc(dev, crtc, encoder)
3558 encoder->disable(encoder);
3559
3560 intel_crtc_wait_for_pending_flips(crtc);
3561 drm_vblank_off(dev, pipe);
3562 intel_crtc_update_cursor(crtc, false);
3563
3564 intel_disable_plane(dev_priv, plane, pipe);
3565
3566 if (dev_priv->cfb_plane == plane)
3567 intel_disable_fbc(dev);
3568
3569 intel_disable_pipe(dev_priv, pipe);
3570
3571 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3572
3573 /* Disable PF */
3574 I915_WRITE(PF_CTL(pipe), 0);
3575 I915_WRITE(PF_WIN_SZ(pipe), 0);
3576
3577 intel_ddi_disable_pipe_clock(intel_crtc);
3578
3579 for_each_encoder_on_crtc(dev, crtc, encoder)
3580 if (encoder->post_disable)
3581 encoder->post_disable(encoder);
3582
3583 if (is_pch_port) {
3584 lpt_disable_pch_transcoder(dev_priv);
3585 intel_ddi_fdi_disable(crtc);
3586 }
3587
3588 intel_crtc->active = false;
3589 intel_update_watermarks(dev);
3590
3591 mutex_lock(&dev->struct_mutex);
3592 intel_update_fbc(dev);
3593 mutex_unlock(&dev->struct_mutex);
3594 }
3595
3596 static void ironlake_crtc_off(struct drm_crtc *crtc)
3597 {
3598 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3599 intel_put_pch_pll(intel_crtc);
3600 }
3601
3602 static void haswell_crtc_off(struct drm_crtc *crtc)
3603 {
3604 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3605
3606 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3607 * start using it. */
3608 intel_crtc->cpu_transcoder = (enum transcoder) intel_crtc->pipe;
3609
3610 intel_ddi_put_crtc_pll(crtc);
3611 }
3612
3613 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3614 {
3615 if (!enable && intel_crtc->overlay) {
3616 struct drm_device *dev = intel_crtc->base.dev;
3617 struct drm_i915_private *dev_priv = dev->dev_private;
3618
3619 mutex_lock(&dev->struct_mutex);
3620 dev_priv->mm.interruptible = false;
3621 (void) intel_overlay_switch_off(intel_crtc->overlay);
3622 dev_priv->mm.interruptible = true;
3623 mutex_unlock(&dev->struct_mutex);
3624 }
3625
3626 /* Let userspace switch the overlay on again. In most cases userspace
3627 * has to recompute where to put it anyway.
3628 */
3629 }
3630
3631 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3632 {
3633 struct drm_device *dev = crtc->dev;
3634 struct drm_i915_private *dev_priv = dev->dev_private;
3635 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3636 struct intel_encoder *encoder;
3637 int pipe = intel_crtc->pipe;
3638 int plane = intel_crtc->plane;
3639
3640 WARN_ON(!crtc->enabled);
3641
3642 if (intel_crtc->active)
3643 return;
3644
3645 intel_crtc->active = true;
3646 intel_update_watermarks(dev);
3647
3648 intel_enable_pll(dev_priv, pipe);
3649
3650 for_each_encoder_on_crtc(dev, crtc, encoder)
3651 if (encoder->pre_enable)
3652 encoder->pre_enable(encoder);
3653
3654 intel_enable_pipe(dev_priv, pipe, false);
3655 intel_enable_plane(dev_priv, plane, pipe);
3656
3657 intel_crtc_load_lut(crtc);
3658 intel_update_fbc(dev);
3659
3660 /* Give the overlay scaler a chance to enable if it's on this pipe */
3661 intel_crtc_dpms_overlay(intel_crtc, true);
3662 intel_crtc_update_cursor(crtc, true);
3663
3664 for_each_encoder_on_crtc(dev, crtc, encoder)
3665 encoder->enable(encoder);
3666 }
3667
3668 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3669 {
3670 struct drm_device *dev = crtc->dev;
3671 struct drm_i915_private *dev_priv = dev->dev_private;
3672 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3673 struct intel_encoder *encoder;
3674 int pipe = intel_crtc->pipe;
3675 int plane = intel_crtc->plane;
3676 u32 pctl;
3677
3678
3679 if (!intel_crtc->active)
3680 return;
3681
3682 for_each_encoder_on_crtc(dev, crtc, encoder)
3683 encoder->disable(encoder);
3684
3685 /* Give the overlay scaler a chance to disable if it's on this pipe */
3686 intel_crtc_wait_for_pending_flips(crtc);
3687 drm_vblank_off(dev, pipe);
3688 intel_crtc_dpms_overlay(intel_crtc, false);
3689 intel_crtc_update_cursor(crtc, false);
3690
3691 if (dev_priv->cfb_plane == plane)
3692 intel_disable_fbc(dev);
3693
3694 intel_disable_plane(dev_priv, plane, pipe);
3695 intel_disable_pipe(dev_priv, pipe);
3696
3697 /* Disable pannel fitter if it is on this pipe. */
3698 pctl = I915_READ(PFIT_CONTROL);
3699 if ((pctl & PFIT_ENABLE) &&
3700 ((pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT) == pipe)
3701 I915_WRITE(PFIT_CONTROL, 0);
3702
3703 intel_disable_pll(dev_priv, pipe);
3704
3705 intel_crtc->active = false;
3706 intel_update_fbc(dev);
3707 intel_update_watermarks(dev);
3708 }
3709
3710 static void i9xx_crtc_off(struct drm_crtc *crtc)
3711 {
3712 }
3713
3714 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3715 bool enabled)
3716 {
3717 struct drm_device *dev = crtc->dev;
3718 struct drm_i915_master_private *master_priv;
3719 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3720 int pipe = intel_crtc->pipe;
3721
3722 if (!dev->primary->master)
3723 return;
3724
3725 master_priv = dev->primary->master->driver_priv;
3726 if (!master_priv->sarea_priv)
3727 return;
3728
3729 switch (pipe) {
3730 case 0:
3731 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3732 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3733 break;
3734 case 1:
3735 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3736 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3737 break;
3738 default:
3739 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3740 break;
3741 }
3742 }
3743
3744 /**
3745 * Sets the power management mode of the pipe and plane.
3746 */
3747 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3748 {
3749 struct drm_device *dev = crtc->dev;
3750 struct drm_i915_private *dev_priv = dev->dev_private;
3751 struct intel_encoder *intel_encoder;
3752 bool enable = false;
3753
3754 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3755 enable |= intel_encoder->connectors_active;
3756
3757 if (enable)
3758 dev_priv->display.crtc_enable(crtc);
3759 else
3760 dev_priv->display.crtc_disable(crtc);
3761
3762 intel_crtc_update_sarea(crtc, enable);
3763 }
3764
3765 static void intel_crtc_noop(struct drm_crtc *crtc)
3766 {
3767 }
3768
3769 static void intel_crtc_disable(struct drm_crtc *crtc)
3770 {
3771 struct drm_device *dev = crtc->dev;
3772 struct drm_connector *connector;
3773 struct drm_i915_private *dev_priv = dev->dev_private;
3774 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3775
3776 /* crtc should still be enabled when we disable it. */
3777 WARN_ON(!crtc->enabled);
3778
3779 intel_crtc->eld_vld = false;
3780 dev_priv->display.crtc_disable(crtc);
3781 intel_crtc_update_sarea(crtc, false);
3782 dev_priv->display.off(crtc);
3783
3784 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3785 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3786
3787 if (crtc->fb) {
3788 mutex_lock(&dev->struct_mutex);
3789 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3790 mutex_unlock(&dev->struct_mutex);
3791 crtc->fb = NULL;
3792 }
3793
3794 /* Update computed state. */
3795 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3796 if (!connector->encoder || !connector->encoder->crtc)
3797 continue;
3798
3799 if (connector->encoder->crtc != crtc)
3800 continue;
3801
3802 connector->dpms = DRM_MODE_DPMS_OFF;
3803 to_intel_encoder(connector->encoder)->connectors_active = false;
3804 }
3805 }
3806
3807 void intel_modeset_disable(struct drm_device *dev)
3808 {
3809 struct drm_crtc *crtc;
3810
3811 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3812 if (crtc->enabled)
3813 intel_crtc_disable(crtc);
3814 }
3815 }
3816
3817 void intel_encoder_noop(struct drm_encoder *encoder)
3818 {
3819 }
3820
3821 void intel_encoder_destroy(struct drm_encoder *encoder)
3822 {
3823 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3824
3825 drm_encoder_cleanup(encoder);
3826 kfree(intel_encoder);
3827 }
3828
3829 /* Simple dpms helper for encodres with just one connector, no cloning and only
3830 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3831 * state of the entire output pipe. */
3832 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3833 {
3834 if (mode == DRM_MODE_DPMS_ON) {
3835 encoder->connectors_active = true;
3836
3837 intel_crtc_update_dpms(encoder->base.crtc);
3838 } else {
3839 encoder->connectors_active = false;
3840
3841 intel_crtc_update_dpms(encoder->base.crtc);
3842 }
3843 }
3844
3845 /* Cross check the actual hw state with our own modeset state tracking (and it's
3846 * internal consistency). */
3847 static void intel_connector_check_state(struct intel_connector *connector)
3848 {
3849 if (connector->get_hw_state(connector)) {
3850 struct intel_encoder *encoder = connector->encoder;
3851 struct drm_crtc *crtc;
3852 bool encoder_enabled;
3853 enum pipe pipe;
3854
3855 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3856 connector->base.base.id,
3857 drm_get_connector_name(&connector->base));
3858
3859 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3860 "wrong connector dpms state\n");
3861 WARN(connector->base.encoder != &encoder->base,
3862 "active connector not linked to encoder\n");
3863 WARN(!encoder->connectors_active,
3864 "encoder->connectors_active not set\n");
3865
3866 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3867 WARN(!encoder_enabled, "encoder not enabled\n");
3868 if (WARN_ON(!encoder->base.crtc))
3869 return;
3870
3871 crtc = encoder->base.crtc;
3872
3873 WARN(!crtc->enabled, "crtc not enabled\n");
3874 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3875 WARN(pipe != to_intel_crtc(crtc)->pipe,
3876 "encoder active on the wrong pipe\n");
3877 }
3878 }
3879
3880 /* Even simpler default implementation, if there's really no special case to
3881 * consider. */
3882 void intel_connector_dpms(struct drm_connector *connector, int mode)
3883 {
3884 struct intel_encoder *encoder = intel_attached_encoder(connector);
3885
3886 /* All the simple cases only support two dpms states. */
3887 if (mode != DRM_MODE_DPMS_ON)
3888 mode = DRM_MODE_DPMS_OFF;
3889
3890 if (mode == connector->dpms)
3891 return;
3892
3893 connector->dpms = mode;
3894
3895 /* Only need to change hw state when actually enabled */
3896 if (encoder->base.crtc)
3897 intel_encoder_dpms(encoder, mode);
3898 else
3899 WARN_ON(encoder->connectors_active != false);
3900
3901 intel_modeset_check_state(connector->dev);
3902 }
3903
3904 /* Simple connector->get_hw_state implementation for encoders that support only
3905 * one connector and no cloning and hence the encoder state determines the state
3906 * of the connector. */
3907 bool intel_connector_get_hw_state(struct intel_connector *connector)
3908 {
3909 enum pipe pipe = 0;
3910 struct intel_encoder *encoder = connector->encoder;
3911
3912 return encoder->get_hw_state(encoder, &pipe);
3913 }
3914
3915 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3916 const struct drm_display_mode *mode,
3917 struct drm_display_mode *adjusted_mode)
3918 {
3919 struct drm_device *dev = crtc->dev;
3920
3921 if (HAS_PCH_SPLIT(dev)) {
3922 /* FDI link clock is fixed at 2.7G */
3923 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3924 return false;
3925 }
3926
3927 /* All interlaced capable intel hw wants timings in frames. Note though
3928 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3929 * timings, so we need to be careful not to clobber these.*/
3930 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3931 drm_mode_set_crtcinfo(adjusted_mode, 0);
3932
3933 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3934 * with a hsync front porch of 0.
3935 */
3936 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3937 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3938 return false;
3939
3940 return true;
3941 }
3942
3943 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3944 {
3945 return 400000; /* FIXME */
3946 }
3947
3948 static int i945_get_display_clock_speed(struct drm_device *dev)
3949 {
3950 return 400000;
3951 }
3952
3953 static int i915_get_display_clock_speed(struct drm_device *dev)
3954 {
3955 return 333000;
3956 }
3957
3958 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3959 {
3960 return 200000;
3961 }
3962
3963 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3964 {
3965 u16 gcfgc = 0;
3966
3967 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3968
3969 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3970 return 133000;
3971 else {
3972 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3973 case GC_DISPLAY_CLOCK_333_MHZ:
3974 return 333000;
3975 default:
3976 case GC_DISPLAY_CLOCK_190_200_MHZ:
3977 return 190000;
3978 }
3979 }
3980 }
3981
3982 static int i865_get_display_clock_speed(struct drm_device *dev)
3983 {
3984 return 266000;
3985 }
3986
3987 static int i855_get_display_clock_speed(struct drm_device *dev)
3988 {
3989 u16 hpllcc = 0;
3990 /* Assume that the hardware is in the high speed state. This
3991 * should be the default.
3992 */
3993 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3994 case GC_CLOCK_133_200:
3995 case GC_CLOCK_100_200:
3996 return 200000;
3997 case GC_CLOCK_166_250:
3998 return 250000;
3999 case GC_CLOCK_100_133:
4000 return 133000;
4001 }
4002
4003 /* Shouldn't happen */
4004 return 0;
4005 }
4006
4007 static int i830_get_display_clock_speed(struct drm_device *dev)
4008 {
4009 return 133000;
4010 }
4011
4012 static void
4013 intel_reduce_ratio(uint32_t *num, uint32_t *den)
4014 {
4015 while (*num > 0xffffff || *den > 0xffffff) {
4016 *num >>= 1;
4017 *den >>= 1;
4018 }
4019 }
4020
4021 void
4022 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4023 int pixel_clock, int link_clock,
4024 struct intel_link_m_n *m_n)
4025 {
4026 m_n->tu = 64;
4027 m_n->gmch_m = bits_per_pixel * pixel_clock;
4028 m_n->gmch_n = link_clock * nlanes * 8;
4029 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4030 m_n->link_m = pixel_clock;
4031 m_n->link_n = link_clock;
4032 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
4033 }
4034
4035 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4036 {
4037 if (i915_panel_use_ssc >= 0)
4038 return i915_panel_use_ssc != 0;
4039 return dev_priv->lvds_use_ssc
4040 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4041 }
4042
4043 /**
4044 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4045 * @crtc: CRTC structure
4046 * @mode: requested mode
4047 *
4048 * A pipe may be connected to one or more outputs. Based on the depth of the
4049 * attached framebuffer, choose a good color depth to use on the pipe.
4050 *
4051 * If possible, match the pipe depth to the fb depth. In some cases, this
4052 * isn't ideal, because the connected output supports a lesser or restricted
4053 * set of depths. Resolve that here:
4054 * LVDS typically supports only 6bpc, so clamp down in that case
4055 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4056 * Displays may support a restricted set as well, check EDID and clamp as
4057 * appropriate.
4058 * DP may want to dither down to 6bpc to fit larger modes
4059 *
4060 * RETURNS:
4061 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4062 * true if they don't match).
4063 */
4064 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4065 struct drm_framebuffer *fb,
4066 unsigned int *pipe_bpp,
4067 struct drm_display_mode *mode)
4068 {
4069 struct drm_device *dev = crtc->dev;
4070 struct drm_i915_private *dev_priv = dev->dev_private;
4071 struct drm_connector *connector;
4072 struct intel_encoder *intel_encoder;
4073 unsigned int display_bpc = UINT_MAX, bpc;
4074
4075 /* Walk the encoders & connectors on this crtc, get min bpc */
4076 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4077
4078 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4079 unsigned int lvds_bpc;
4080
4081 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4082 LVDS_A3_POWER_UP)
4083 lvds_bpc = 8;
4084 else
4085 lvds_bpc = 6;
4086
4087 if (lvds_bpc < display_bpc) {
4088 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4089 display_bpc = lvds_bpc;
4090 }
4091 continue;
4092 }
4093
4094 /* Not one of the known troublemakers, check the EDID */
4095 list_for_each_entry(connector, &dev->mode_config.connector_list,
4096 head) {
4097 if (connector->encoder != &intel_encoder->base)
4098 continue;
4099
4100 /* Don't use an invalid EDID bpc value */
4101 if (connector->display_info.bpc &&
4102 connector->display_info.bpc < display_bpc) {
4103 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4104 display_bpc = connector->display_info.bpc;
4105 }
4106 }
4107
4108 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4109 /* Use VBT settings if we have an eDP panel */
4110 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4111
4112 if (edp_bpc && edp_bpc < display_bpc) {
4113 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4114 display_bpc = edp_bpc;
4115 }
4116 continue;
4117 }
4118
4119 /*
4120 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4121 * through, clamp it down. (Note: >12bpc will be caught below.)
4122 */
4123 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4124 if (display_bpc > 8 && display_bpc < 12) {
4125 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4126 display_bpc = 12;
4127 } else {
4128 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4129 display_bpc = 8;
4130 }
4131 }
4132 }
4133
4134 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4135 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4136 display_bpc = 6;
4137 }
4138
4139 /*
4140 * We could just drive the pipe at the highest bpc all the time and
4141 * enable dithering as needed, but that costs bandwidth. So choose
4142 * the minimum value that expresses the full color range of the fb but
4143 * also stays within the max display bpc discovered above.
4144 */
4145
4146 switch (fb->depth) {
4147 case 8:
4148 bpc = 8; /* since we go through a colormap */
4149 break;
4150 case 15:
4151 case 16:
4152 bpc = 6; /* min is 18bpp */
4153 break;
4154 case 24:
4155 bpc = 8;
4156 break;
4157 case 30:
4158 bpc = 10;
4159 break;
4160 case 48:
4161 bpc = 12;
4162 break;
4163 default:
4164 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4165 bpc = min((unsigned int)8, display_bpc);
4166 break;
4167 }
4168
4169 display_bpc = min(display_bpc, bpc);
4170
4171 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4172 bpc, display_bpc);
4173
4174 *pipe_bpp = display_bpc * 3;
4175
4176 return display_bpc != bpc;
4177 }
4178
4179 static int vlv_get_refclk(struct drm_crtc *crtc)
4180 {
4181 struct drm_device *dev = crtc->dev;
4182 struct drm_i915_private *dev_priv = dev->dev_private;
4183 int refclk = 27000; /* for DP & HDMI */
4184
4185 return 100000; /* only one validated so far */
4186
4187 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4188 refclk = 96000;
4189 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4190 if (intel_panel_use_ssc(dev_priv))
4191 refclk = 100000;
4192 else
4193 refclk = 96000;
4194 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4195 refclk = 100000;
4196 }
4197
4198 return refclk;
4199 }
4200
4201 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4202 {
4203 struct drm_device *dev = crtc->dev;
4204 struct drm_i915_private *dev_priv = dev->dev_private;
4205 int refclk;
4206
4207 if (IS_VALLEYVIEW(dev)) {
4208 refclk = vlv_get_refclk(crtc);
4209 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4210 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4211 refclk = dev_priv->lvds_ssc_freq * 1000;
4212 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4213 refclk / 1000);
4214 } else if (!IS_GEN2(dev)) {
4215 refclk = 96000;
4216 } else {
4217 refclk = 48000;
4218 }
4219
4220 return refclk;
4221 }
4222
4223 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4224 intel_clock_t *clock)
4225 {
4226 /* SDVO TV has fixed PLL values depend on its clock range,
4227 this mirrors vbios setting. */
4228 if (adjusted_mode->clock >= 100000
4229 && adjusted_mode->clock < 140500) {
4230 clock->p1 = 2;
4231 clock->p2 = 10;
4232 clock->n = 3;
4233 clock->m1 = 16;
4234 clock->m2 = 8;
4235 } else if (adjusted_mode->clock >= 140500
4236 && adjusted_mode->clock <= 200000) {
4237 clock->p1 = 1;
4238 clock->p2 = 10;
4239 clock->n = 6;
4240 clock->m1 = 12;
4241 clock->m2 = 8;
4242 }
4243 }
4244
4245 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4246 intel_clock_t *clock,
4247 intel_clock_t *reduced_clock)
4248 {
4249 struct drm_device *dev = crtc->dev;
4250 struct drm_i915_private *dev_priv = dev->dev_private;
4251 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4252 int pipe = intel_crtc->pipe;
4253 u32 fp, fp2 = 0;
4254
4255 if (IS_PINEVIEW(dev)) {
4256 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4257 if (reduced_clock)
4258 fp2 = (1 << reduced_clock->n) << 16 |
4259 reduced_clock->m1 << 8 | reduced_clock->m2;
4260 } else {
4261 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4262 if (reduced_clock)
4263 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4264 reduced_clock->m2;
4265 }
4266
4267 I915_WRITE(FP0(pipe), fp);
4268
4269 intel_crtc->lowfreq_avail = false;
4270 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4271 reduced_clock && i915_powersave) {
4272 I915_WRITE(FP1(pipe), fp2);
4273 intel_crtc->lowfreq_avail = true;
4274 } else {
4275 I915_WRITE(FP1(pipe), fp);
4276 }
4277 }
4278
4279 static void vlv_update_pll(struct drm_crtc *crtc,
4280 struct drm_display_mode *mode,
4281 struct drm_display_mode *adjusted_mode,
4282 intel_clock_t *clock, intel_clock_t *reduced_clock,
4283 int num_connectors)
4284 {
4285 struct drm_device *dev = crtc->dev;
4286 struct drm_i915_private *dev_priv = dev->dev_private;
4287 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4288 int pipe = intel_crtc->pipe;
4289 u32 dpll, mdiv, pdiv;
4290 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4291 bool is_sdvo;
4292 u32 temp;
4293
4294 mutex_lock(&dev_priv->dpio_lock);
4295
4296 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4297 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4298
4299 dpll = DPLL_VGA_MODE_DIS;
4300 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4301 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4302 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4303
4304 I915_WRITE(DPLL(pipe), dpll);
4305 POSTING_READ(DPLL(pipe));
4306
4307 bestn = clock->n;
4308 bestm1 = clock->m1;
4309 bestm2 = clock->m2;
4310 bestp1 = clock->p1;
4311 bestp2 = clock->p2;
4312
4313 /*
4314 * In Valleyview PLL and program lane counter registers are exposed
4315 * through DPIO interface
4316 */
4317 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4318 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4319 mdiv |= ((bestn << DPIO_N_SHIFT));
4320 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4321 mdiv |= (1 << DPIO_K_SHIFT);
4322 mdiv |= DPIO_ENABLE_CALIBRATION;
4323 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4324
4325 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4326
4327 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4328 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4329 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4330 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4331 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4332
4333 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4334
4335 dpll |= DPLL_VCO_ENABLE;
4336 I915_WRITE(DPLL(pipe), dpll);
4337 POSTING_READ(DPLL(pipe));
4338 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4339 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4340
4341 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4342
4343 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4344 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4345
4346 I915_WRITE(DPLL(pipe), dpll);
4347
4348 /* Wait for the clocks to stabilize. */
4349 POSTING_READ(DPLL(pipe));
4350 udelay(150);
4351
4352 temp = 0;
4353 if (is_sdvo) {
4354 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4355 if (temp > 1)
4356 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4357 else
4358 temp = 0;
4359 }
4360 I915_WRITE(DPLL_MD(pipe), temp);
4361 POSTING_READ(DPLL_MD(pipe));
4362
4363 /* Now program lane control registers */
4364 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4365 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4366 {
4367 temp = 0x1000C4;
4368 if(pipe == 1)
4369 temp |= (1 << 21);
4370 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4371 }
4372 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4373 {
4374 temp = 0x1000C4;
4375 if(pipe == 1)
4376 temp |= (1 << 21);
4377 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4378 }
4379
4380 mutex_unlock(&dev_priv->dpio_lock);
4381 }
4382
4383 static void i9xx_update_pll(struct drm_crtc *crtc,
4384 struct drm_display_mode *mode,
4385 struct drm_display_mode *adjusted_mode,
4386 intel_clock_t *clock, intel_clock_t *reduced_clock,
4387 int num_connectors)
4388 {
4389 struct drm_device *dev = crtc->dev;
4390 struct drm_i915_private *dev_priv = dev->dev_private;
4391 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4392 struct intel_encoder *encoder;
4393 int pipe = intel_crtc->pipe;
4394 u32 dpll;
4395 bool is_sdvo;
4396
4397 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4398
4399 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4400 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4401
4402 dpll = DPLL_VGA_MODE_DIS;
4403
4404 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4405 dpll |= DPLLB_MODE_LVDS;
4406 else
4407 dpll |= DPLLB_MODE_DAC_SERIAL;
4408 if (is_sdvo) {
4409 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4410 if (pixel_multiplier > 1) {
4411 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4412 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4413 }
4414 dpll |= DPLL_DVO_HIGH_SPEED;
4415 }
4416 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4417 dpll |= DPLL_DVO_HIGH_SPEED;
4418
4419 /* compute bitmask from p1 value */
4420 if (IS_PINEVIEW(dev))
4421 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4422 else {
4423 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4424 if (IS_G4X(dev) && reduced_clock)
4425 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4426 }
4427 switch (clock->p2) {
4428 case 5:
4429 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4430 break;
4431 case 7:
4432 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4433 break;
4434 case 10:
4435 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4436 break;
4437 case 14:
4438 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4439 break;
4440 }
4441 if (INTEL_INFO(dev)->gen >= 4)
4442 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4443
4444 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4445 dpll |= PLL_REF_INPUT_TVCLKINBC;
4446 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4447 /* XXX: just matching BIOS for now */
4448 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4449 dpll |= 3;
4450 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4451 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4452 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4453 else
4454 dpll |= PLL_REF_INPUT_DREFCLK;
4455
4456 dpll |= DPLL_VCO_ENABLE;
4457 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4458 POSTING_READ(DPLL(pipe));
4459 udelay(150);
4460
4461 for_each_encoder_on_crtc(dev, crtc, encoder)
4462 if (encoder->pre_pll_enable)
4463 encoder->pre_pll_enable(encoder);
4464
4465 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4466 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4467
4468 I915_WRITE(DPLL(pipe), dpll);
4469
4470 /* Wait for the clocks to stabilize. */
4471 POSTING_READ(DPLL(pipe));
4472 udelay(150);
4473
4474 if (INTEL_INFO(dev)->gen >= 4) {
4475 u32 temp = 0;
4476 if (is_sdvo) {
4477 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4478 if (temp > 1)
4479 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4480 else
4481 temp = 0;
4482 }
4483 I915_WRITE(DPLL_MD(pipe), temp);
4484 } else {
4485 /* The pixel multiplier can only be updated once the
4486 * DPLL is enabled and the clocks are stable.
4487 *
4488 * So write it again.
4489 */
4490 I915_WRITE(DPLL(pipe), dpll);
4491 }
4492 }
4493
4494 static void i8xx_update_pll(struct drm_crtc *crtc,
4495 struct drm_display_mode *adjusted_mode,
4496 intel_clock_t *clock, intel_clock_t *reduced_clock,
4497 int num_connectors)
4498 {
4499 struct drm_device *dev = crtc->dev;
4500 struct drm_i915_private *dev_priv = dev->dev_private;
4501 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4502 struct intel_encoder *encoder;
4503 int pipe = intel_crtc->pipe;
4504 u32 dpll;
4505
4506 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4507
4508 dpll = DPLL_VGA_MODE_DIS;
4509
4510 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4511 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4512 } else {
4513 if (clock->p1 == 2)
4514 dpll |= PLL_P1_DIVIDE_BY_TWO;
4515 else
4516 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4517 if (clock->p2 == 4)
4518 dpll |= PLL_P2_DIVIDE_BY_4;
4519 }
4520
4521 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4522 /* XXX: just matching BIOS for now */
4523 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4524 dpll |= 3;
4525 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4526 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4527 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4528 else
4529 dpll |= PLL_REF_INPUT_DREFCLK;
4530
4531 dpll |= DPLL_VCO_ENABLE;
4532 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4533 POSTING_READ(DPLL(pipe));
4534 udelay(150);
4535
4536 for_each_encoder_on_crtc(dev, crtc, encoder)
4537 if (encoder->pre_pll_enable)
4538 encoder->pre_pll_enable(encoder);
4539
4540 I915_WRITE(DPLL(pipe), dpll);
4541
4542 /* Wait for the clocks to stabilize. */
4543 POSTING_READ(DPLL(pipe));
4544 udelay(150);
4545
4546 /* The pixel multiplier can only be updated once the
4547 * DPLL is enabled and the clocks are stable.
4548 *
4549 * So write it again.
4550 */
4551 I915_WRITE(DPLL(pipe), dpll);
4552 }
4553
4554 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4555 struct drm_display_mode *mode,
4556 struct drm_display_mode *adjusted_mode)
4557 {
4558 struct drm_device *dev = intel_crtc->base.dev;
4559 struct drm_i915_private *dev_priv = dev->dev_private;
4560 enum pipe pipe = intel_crtc->pipe;
4561 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4562 uint32_t vsyncshift;
4563
4564 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4565 /* the chip adds 2 halflines automatically */
4566 adjusted_mode->crtc_vtotal -= 1;
4567 adjusted_mode->crtc_vblank_end -= 1;
4568 vsyncshift = adjusted_mode->crtc_hsync_start
4569 - adjusted_mode->crtc_htotal / 2;
4570 } else {
4571 vsyncshift = 0;
4572 }
4573
4574 if (INTEL_INFO(dev)->gen > 3)
4575 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4576
4577 I915_WRITE(HTOTAL(cpu_transcoder),
4578 (adjusted_mode->crtc_hdisplay - 1) |
4579 ((adjusted_mode->crtc_htotal - 1) << 16));
4580 I915_WRITE(HBLANK(cpu_transcoder),
4581 (adjusted_mode->crtc_hblank_start - 1) |
4582 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4583 I915_WRITE(HSYNC(cpu_transcoder),
4584 (adjusted_mode->crtc_hsync_start - 1) |
4585 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4586
4587 I915_WRITE(VTOTAL(cpu_transcoder),
4588 (adjusted_mode->crtc_vdisplay - 1) |
4589 ((adjusted_mode->crtc_vtotal - 1) << 16));
4590 I915_WRITE(VBLANK(cpu_transcoder),
4591 (adjusted_mode->crtc_vblank_start - 1) |
4592 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4593 I915_WRITE(VSYNC(cpu_transcoder),
4594 (adjusted_mode->crtc_vsync_start - 1) |
4595 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4596
4597 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4598 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4599 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4600 * bits. */
4601 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4602 (pipe == PIPE_B || pipe == PIPE_C))
4603 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4604
4605 /* pipesrc controls the size that is scaled from, which should
4606 * always be the user's requested size.
4607 */
4608 I915_WRITE(PIPESRC(pipe),
4609 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4610 }
4611
4612 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4613 struct drm_display_mode *mode,
4614 struct drm_display_mode *adjusted_mode,
4615 int x, int y,
4616 struct drm_framebuffer *fb)
4617 {
4618 struct drm_device *dev = crtc->dev;
4619 struct drm_i915_private *dev_priv = dev->dev_private;
4620 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4621 int pipe = intel_crtc->pipe;
4622 int plane = intel_crtc->plane;
4623 int refclk, num_connectors = 0;
4624 intel_clock_t clock, reduced_clock;
4625 u32 dspcntr, pipeconf;
4626 bool ok, has_reduced_clock = false, is_sdvo = false;
4627 bool is_lvds = false, is_tv = false, is_dp = false;
4628 struct intel_encoder *encoder;
4629 const intel_limit_t *limit;
4630 int ret;
4631
4632 for_each_encoder_on_crtc(dev, crtc, encoder) {
4633 switch (encoder->type) {
4634 case INTEL_OUTPUT_LVDS:
4635 is_lvds = true;
4636 break;
4637 case INTEL_OUTPUT_SDVO:
4638 case INTEL_OUTPUT_HDMI:
4639 is_sdvo = true;
4640 if (encoder->needs_tv_clock)
4641 is_tv = true;
4642 break;
4643 case INTEL_OUTPUT_TVOUT:
4644 is_tv = true;
4645 break;
4646 case INTEL_OUTPUT_DISPLAYPORT:
4647 is_dp = true;
4648 break;
4649 }
4650
4651 num_connectors++;
4652 }
4653
4654 refclk = i9xx_get_refclk(crtc, num_connectors);
4655
4656 /*
4657 * Returns a set of divisors for the desired target clock with the given
4658 * refclk, or FALSE. The returned values represent the clock equation:
4659 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4660 */
4661 limit = intel_limit(crtc, refclk);
4662 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4663 &clock);
4664 if (!ok) {
4665 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4666 return -EINVAL;
4667 }
4668
4669 /* Ensure that the cursor is valid for the new mode before changing... */
4670 intel_crtc_update_cursor(crtc, true);
4671
4672 if (is_lvds && dev_priv->lvds_downclock_avail) {
4673 /*
4674 * Ensure we match the reduced clock's P to the target clock.
4675 * If the clocks don't match, we can't switch the display clock
4676 * by using the FP0/FP1. In such case we will disable the LVDS
4677 * downclock feature.
4678 */
4679 has_reduced_clock = limit->find_pll(limit, crtc,
4680 dev_priv->lvds_downclock,
4681 refclk,
4682 &clock,
4683 &reduced_clock);
4684 }
4685
4686 if (is_sdvo && is_tv)
4687 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4688
4689 if (IS_GEN2(dev))
4690 i8xx_update_pll(crtc, adjusted_mode, &clock,
4691 has_reduced_clock ? &reduced_clock : NULL,
4692 num_connectors);
4693 else if (IS_VALLEYVIEW(dev))
4694 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4695 has_reduced_clock ? &reduced_clock : NULL,
4696 num_connectors);
4697 else
4698 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4699 has_reduced_clock ? &reduced_clock : NULL,
4700 num_connectors);
4701
4702 /* setup pipeconf */
4703 pipeconf = I915_READ(PIPECONF(pipe));
4704
4705 /* Set up the display plane register */
4706 dspcntr = DISPPLANE_GAMMA_ENABLE;
4707
4708 if (pipe == 0)
4709 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4710 else
4711 dspcntr |= DISPPLANE_SEL_PIPE_B;
4712
4713 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4714 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4715 * core speed.
4716 *
4717 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4718 * pipe == 0 check?
4719 */
4720 if (mode->clock >
4721 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4722 pipeconf |= PIPECONF_DOUBLE_WIDE;
4723 else
4724 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4725 }
4726
4727 /* default to 8bpc */
4728 pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
4729 if (is_dp) {
4730 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4731 pipeconf |= PIPECONF_6BPC |
4732 PIPECONF_DITHER_EN |
4733 PIPECONF_DITHER_TYPE_SP;
4734 }
4735 }
4736
4737 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4738 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4739 pipeconf |= PIPECONF_6BPC |
4740 PIPECONF_ENABLE |
4741 I965_PIPECONF_ACTIVE;
4742 }
4743 }
4744
4745 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4746 drm_mode_debug_printmodeline(mode);
4747
4748 if (HAS_PIPE_CXSR(dev)) {
4749 if (intel_crtc->lowfreq_avail) {
4750 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4751 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4752 } else {
4753 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4754 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4755 }
4756 }
4757
4758 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4759 if (!IS_GEN2(dev) &&
4760 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4761 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4762 else
4763 pipeconf |= PIPECONF_PROGRESSIVE;
4764
4765 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4766
4767 /* pipesrc and dspsize control the size that is scaled from,
4768 * which should always be the user's requested size.
4769 */
4770 I915_WRITE(DSPSIZE(plane),
4771 ((mode->vdisplay - 1) << 16) |
4772 (mode->hdisplay - 1));
4773 I915_WRITE(DSPPOS(plane), 0);
4774
4775 I915_WRITE(PIPECONF(pipe), pipeconf);
4776 POSTING_READ(PIPECONF(pipe));
4777 intel_enable_pipe(dev_priv, pipe, false);
4778
4779 intel_wait_for_vblank(dev, pipe);
4780
4781 I915_WRITE(DSPCNTR(plane), dspcntr);
4782 POSTING_READ(DSPCNTR(plane));
4783
4784 ret = intel_pipe_set_base(crtc, x, y, fb);
4785
4786 intel_update_watermarks(dev);
4787
4788 return ret;
4789 }
4790
4791 static void ironlake_init_pch_refclk(struct drm_device *dev)
4792 {
4793 struct drm_i915_private *dev_priv = dev->dev_private;
4794 struct drm_mode_config *mode_config = &dev->mode_config;
4795 struct intel_encoder *encoder;
4796 u32 temp;
4797 bool has_lvds = false;
4798 bool has_cpu_edp = false;
4799 bool has_pch_edp = false;
4800 bool has_panel = false;
4801 bool has_ck505 = false;
4802 bool can_ssc = false;
4803
4804 /* We need to take the global config into account */
4805 list_for_each_entry(encoder, &mode_config->encoder_list,
4806 base.head) {
4807 switch (encoder->type) {
4808 case INTEL_OUTPUT_LVDS:
4809 has_panel = true;
4810 has_lvds = true;
4811 break;
4812 case INTEL_OUTPUT_EDP:
4813 has_panel = true;
4814 if (intel_encoder_is_pch_edp(&encoder->base))
4815 has_pch_edp = true;
4816 else
4817 has_cpu_edp = true;
4818 break;
4819 }
4820 }
4821
4822 if (HAS_PCH_IBX(dev)) {
4823 has_ck505 = dev_priv->display_clock_mode;
4824 can_ssc = has_ck505;
4825 } else {
4826 has_ck505 = false;
4827 can_ssc = true;
4828 }
4829
4830 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4831 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4832 has_ck505);
4833
4834 /* Ironlake: try to setup display ref clock before DPLL
4835 * enabling. This is only under driver's control after
4836 * PCH B stepping, previous chipset stepping should be
4837 * ignoring this setting.
4838 */
4839 temp = I915_READ(PCH_DREF_CONTROL);
4840 /* Always enable nonspread source */
4841 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4842
4843 if (has_ck505)
4844 temp |= DREF_NONSPREAD_CK505_ENABLE;
4845 else
4846 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4847
4848 if (has_panel) {
4849 temp &= ~DREF_SSC_SOURCE_MASK;
4850 temp |= DREF_SSC_SOURCE_ENABLE;
4851
4852 /* SSC must be turned on before enabling the CPU output */
4853 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4854 DRM_DEBUG_KMS("Using SSC on panel\n");
4855 temp |= DREF_SSC1_ENABLE;
4856 } else
4857 temp &= ~DREF_SSC1_ENABLE;
4858
4859 /* Get SSC going before enabling the outputs */
4860 I915_WRITE(PCH_DREF_CONTROL, temp);
4861 POSTING_READ(PCH_DREF_CONTROL);
4862 udelay(200);
4863
4864 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4865
4866 /* Enable CPU source on CPU attached eDP */
4867 if (has_cpu_edp) {
4868 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4869 DRM_DEBUG_KMS("Using SSC on eDP\n");
4870 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4871 }
4872 else
4873 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4874 } else
4875 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4876
4877 I915_WRITE(PCH_DREF_CONTROL, temp);
4878 POSTING_READ(PCH_DREF_CONTROL);
4879 udelay(200);
4880 } else {
4881 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4882
4883 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4884
4885 /* Turn off CPU output */
4886 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4887
4888 I915_WRITE(PCH_DREF_CONTROL, temp);
4889 POSTING_READ(PCH_DREF_CONTROL);
4890 udelay(200);
4891
4892 /* Turn off the SSC source */
4893 temp &= ~DREF_SSC_SOURCE_MASK;
4894 temp |= DREF_SSC_SOURCE_DISABLE;
4895
4896 /* Turn off SSC1 */
4897 temp &= ~ DREF_SSC1_ENABLE;
4898
4899 I915_WRITE(PCH_DREF_CONTROL, temp);
4900 POSTING_READ(PCH_DREF_CONTROL);
4901 udelay(200);
4902 }
4903 }
4904
4905 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4906 static void lpt_init_pch_refclk(struct drm_device *dev)
4907 {
4908 struct drm_i915_private *dev_priv = dev->dev_private;
4909 struct drm_mode_config *mode_config = &dev->mode_config;
4910 struct intel_encoder *encoder;
4911 bool has_vga = false;
4912 bool is_sdv = false;
4913 u32 tmp;
4914
4915 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4916 switch (encoder->type) {
4917 case INTEL_OUTPUT_ANALOG:
4918 has_vga = true;
4919 break;
4920 }
4921 }
4922
4923 if (!has_vga)
4924 return;
4925
4926 mutex_lock(&dev_priv->dpio_lock);
4927
4928 /* XXX: Rip out SDV support once Haswell ships for real. */
4929 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
4930 is_sdv = true;
4931
4932 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4933 tmp &= ~SBI_SSCCTL_DISABLE;
4934 tmp |= SBI_SSCCTL_PATHALT;
4935 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4936
4937 udelay(24);
4938
4939 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4940 tmp &= ~SBI_SSCCTL_PATHALT;
4941 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4942
4943 if (!is_sdv) {
4944 tmp = I915_READ(SOUTH_CHICKEN2);
4945 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
4946 I915_WRITE(SOUTH_CHICKEN2, tmp);
4947
4948 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
4949 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
4950 DRM_ERROR("FDI mPHY reset assert timeout\n");
4951
4952 tmp = I915_READ(SOUTH_CHICKEN2);
4953 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
4954 I915_WRITE(SOUTH_CHICKEN2, tmp);
4955
4956 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
4957 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
4958 100))
4959 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
4960 }
4961
4962 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
4963 tmp &= ~(0xFF << 24);
4964 tmp |= (0x12 << 24);
4965 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
4966
4967 if (!is_sdv) {
4968 tmp = intel_sbi_read(dev_priv, 0x808C, SBI_MPHY);
4969 tmp &= ~(0x3 << 6);
4970 tmp |= (1 << 6) | (1 << 0);
4971 intel_sbi_write(dev_priv, 0x808C, tmp, SBI_MPHY);
4972 }
4973
4974 if (is_sdv) {
4975 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
4976 tmp |= 0x7FFF;
4977 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
4978 }
4979
4980 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
4981 tmp |= (1 << 11);
4982 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
4983
4984 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
4985 tmp |= (1 << 11);
4986 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
4987
4988 if (is_sdv) {
4989 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
4990 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4991 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
4992
4993 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
4994 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4995 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
4996
4997 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
4998 tmp |= (0x3F << 8);
4999 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5000
5001 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5002 tmp |= (0x3F << 8);
5003 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5004 }
5005
5006 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5007 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5008 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5009
5010 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5011 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5012 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5013
5014 if (!is_sdv) {
5015 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5016 tmp &= ~(7 << 13);
5017 tmp |= (5 << 13);
5018 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5019
5020 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5021 tmp &= ~(7 << 13);
5022 tmp |= (5 << 13);
5023 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5024 }
5025
5026 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5027 tmp &= ~0xFF;
5028 tmp |= 0x1C;
5029 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5030
5031 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5032 tmp &= ~0xFF;
5033 tmp |= 0x1C;
5034 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5035
5036 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5037 tmp &= ~(0xFF << 16);
5038 tmp |= (0x1C << 16);
5039 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5040
5041 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5042 tmp &= ~(0xFF << 16);
5043 tmp |= (0x1C << 16);
5044 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5045
5046 if (!is_sdv) {
5047 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5048 tmp |= (1 << 27);
5049 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5050
5051 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5052 tmp |= (1 << 27);
5053 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5054
5055 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5056 tmp &= ~(0xF << 28);
5057 tmp |= (4 << 28);
5058 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5059
5060 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5061 tmp &= ~(0xF << 28);
5062 tmp |= (4 << 28);
5063 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5064 }
5065
5066 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5067 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5068 tmp |= SBI_DBUFF0_ENABLE;
5069 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5070
5071 mutex_unlock(&dev_priv->dpio_lock);
5072 }
5073
5074 /*
5075 * Initialize reference clocks when the driver loads
5076 */
5077 void intel_init_pch_refclk(struct drm_device *dev)
5078 {
5079 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5080 ironlake_init_pch_refclk(dev);
5081 else if (HAS_PCH_LPT(dev))
5082 lpt_init_pch_refclk(dev);
5083 }
5084
5085 static int ironlake_get_refclk(struct drm_crtc *crtc)
5086 {
5087 struct drm_device *dev = crtc->dev;
5088 struct drm_i915_private *dev_priv = dev->dev_private;
5089 struct intel_encoder *encoder;
5090 struct intel_encoder *edp_encoder = NULL;
5091 int num_connectors = 0;
5092 bool is_lvds = false;
5093
5094 for_each_encoder_on_crtc(dev, crtc, encoder) {
5095 switch (encoder->type) {
5096 case INTEL_OUTPUT_LVDS:
5097 is_lvds = true;
5098 break;
5099 case INTEL_OUTPUT_EDP:
5100 edp_encoder = encoder;
5101 break;
5102 }
5103 num_connectors++;
5104 }
5105
5106 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5107 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5108 dev_priv->lvds_ssc_freq);
5109 return dev_priv->lvds_ssc_freq * 1000;
5110 }
5111
5112 return 120000;
5113 }
5114
5115 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5116 struct drm_display_mode *adjusted_mode,
5117 bool dither)
5118 {
5119 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5120 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5121 int pipe = intel_crtc->pipe;
5122 uint32_t val;
5123
5124 val = I915_READ(PIPECONF(pipe));
5125
5126 val &= ~PIPECONF_BPC_MASK;
5127 switch (intel_crtc->bpp) {
5128 case 18:
5129 val |= PIPECONF_6BPC;
5130 break;
5131 case 24:
5132 val |= PIPECONF_8BPC;
5133 break;
5134 case 30:
5135 val |= PIPECONF_10BPC;
5136 break;
5137 case 36:
5138 val |= PIPECONF_12BPC;
5139 break;
5140 default:
5141 /* Case prevented by intel_choose_pipe_bpp_dither. */
5142 BUG();
5143 }
5144
5145 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5146 if (dither)
5147 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5148
5149 val &= ~PIPECONF_INTERLACE_MASK;
5150 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5151 val |= PIPECONF_INTERLACED_ILK;
5152 else
5153 val |= PIPECONF_PROGRESSIVE;
5154
5155 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5156 val |= PIPECONF_COLOR_RANGE_SELECT;
5157 else
5158 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5159
5160 I915_WRITE(PIPECONF(pipe), val);
5161 POSTING_READ(PIPECONF(pipe));
5162 }
5163
5164 /*
5165 * Set up the pipe CSC unit.
5166 *
5167 * Currently only full range RGB to limited range RGB conversion
5168 * is supported, but eventually this should handle various
5169 * RGB<->YCbCr scenarios as well.
5170 */
5171 static void intel_set_pipe_csc(struct drm_crtc *crtc,
5172 const struct drm_display_mode *adjusted_mode)
5173 {
5174 struct drm_device *dev = crtc->dev;
5175 struct drm_i915_private *dev_priv = dev->dev_private;
5176 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5177 int pipe = intel_crtc->pipe;
5178 uint16_t coeff = 0x7800; /* 1.0 */
5179
5180 /*
5181 * TODO: Check what kind of values actually come out of the pipe
5182 * with these coeff/postoff values and adjust to get the best
5183 * accuracy. Perhaps we even need to take the bpc value into
5184 * consideration.
5185 */
5186
5187 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5188 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5189
5190 /*
5191 * GY/GU and RY/RU should be the other way around according
5192 * to BSpec, but reality doesn't agree. Just set them up in
5193 * a way that results in the correct picture.
5194 */
5195 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5196 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5197
5198 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5199 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5200
5201 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5202 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5203
5204 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5205 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5206 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5207
5208 if (INTEL_INFO(dev)->gen > 6) {
5209 uint16_t postoff = 0;
5210
5211 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5212 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5213
5214 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5215 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5216 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5217
5218 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5219 } else {
5220 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5221
5222 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5223 mode |= CSC_BLACK_SCREEN_OFFSET;
5224
5225 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5226 }
5227 }
5228
5229 static void haswell_set_pipeconf(struct drm_crtc *crtc,
5230 struct drm_display_mode *adjusted_mode,
5231 bool dither)
5232 {
5233 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5234 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5235 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5236 uint32_t val;
5237
5238 val = I915_READ(PIPECONF(cpu_transcoder));
5239
5240 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5241 if (dither)
5242 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5243
5244 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5245 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5246 val |= PIPECONF_INTERLACED_ILK;
5247 else
5248 val |= PIPECONF_PROGRESSIVE;
5249
5250 I915_WRITE(PIPECONF(cpu_transcoder), val);
5251 POSTING_READ(PIPECONF(cpu_transcoder));
5252 }
5253
5254 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5255 struct drm_display_mode *adjusted_mode,
5256 intel_clock_t *clock,
5257 bool *has_reduced_clock,
5258 intel_clock_t *reduced_clock)
5259 {
5260 struct drm_device *dev = crtc->dev;
5261 struct drm_i915_private *dev_priv = dev->dev_private;
5262 struct intel_encoder *intel_encoder;
5263 int refclk;
5264 const intel_limit_t *limit;
5265 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5266
5267 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5268 switch (intel_encoder->type) {
5269 case INTEL_OUTPUT_LVDS:
5270 is_lvds = true;
5271 break;
5272 case INTEL_OUTPUT_SDVO:
5273 case INTEL_OUTPUT_HDMI:
5274 is_sdvo = true;
5275 if (intel_encoder->needs_tv_clock)
5276 is_tv = true;
5277 break;
5278 case INTEL_OUTPUT_TVOUT:
5279 is_tv = true;
5280 break;
5281 }
5282 }
5283
5284 refclk = ironlake_get_refclk(crtc);
5285
5286 /*
5287 * Returns a set of divisors for the desired target clock with the given
5288 * refclk, or FALSE. The returned values represent the clock equation:
5289 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5290 */
5291 limit = intel_limit(crtc, refclk);
5292 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5293 clock);
5294 if (!ret)
5295 return false;
5296
5297 if (is_lvds && dev_priv->lvds_downclock_avail) {
5298 /*
5299 * Ensure we match the reduced clock's P to the target clock.
5300 * If the clocks don't match, we can't switch the display clock
5301 * by using the FP0/FP1. In such case we will disable the LVDS
5302 * downclock feature.
5303 */
5304 *has_reduced_clock = limit->find_pll(limit, crtc,
5305 dev_priv->lvds_downclock,
5306 refclk,
5307 clock,
5308 reduced_clock);
5309 }
5310
5311 if (is_sdvo && is_tv)
5312 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5313
5314 return true;
5315 }
5316
5317 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5318 {
5319 struct drm_i915_private *dev_priv = dev->dev_private;
5320 uint32_t temp;
5321
5322 temp = I915_READ(SOUTH_CHICKEN1);
5323 if (temp & FDI_BC_BIFURCATION_SELECT)
5324 return;
5325
5326 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5327 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5328
5329 temp |= FDI_BC_BIFURCATION_SELECT;
5330 DRM_DEBUG_KMS("enabling fdi C rx\n");
5331 I915_WRITE(SOUTH_CHICKEN1, temp);
5332 POSTING_READ(SOUTH_CHICKEN1);
5333 }
5334
5335 static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5336 {
5337 struct drm_device *dev = intel_crtc->base.dev;
5338 struct drm_i915_private *dev_priv = dev->dev_private;
5339 struct intel_crtc *pipe_B_crtc =
5340 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5341
5342 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5343 intel_crtc->pipe, intel_crtc->fdi_lanes);
5344 if (intel_crtc->fdi_lanes > 4) {
5345 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5346 intel_crtc->pipe, intel_crtc->fdi_lanes);
5347 /* Clamp lanes to avoid programming the hw with bogus values. */
5348 intel_crtc->fdi_lanes = 4;
5349
5350 return false;
5351 }
5352
5353 if (dev_priv->num_pipe == 2)
5354 return true;
5355
5356 switch (intel_crtc->pipe) {
5357 case PIPE_A:
5358 return true;
5359 case PIPE_B:
5360 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5361 intel_crtc->fdi_lanes > 2) {
5362 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5363 intel_crtc->pipe, intel_crtc->fdi_lanes);
5364 /* Clamp lanes to avoid programming the hw with bogus values. */
5365 intel_crtc->fdi_lanes = 2;
5366
5367 return false;
5368 }
5369
5370 if (intel_crtc->fdi_lanes > 2)
5371 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5372 else
5373 cpt_enable_fdi_bc_bifurcation(dev);
5374
5375 return true;
5376 case PIPE_C:
5377 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5378 if (intel_crtc->fdi_lanes > 2) {
5379 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5380 intel_crtc->pipe, intel_crtc->fdi_lanes);
5381 /* Clamp lanes to avoid programming the hw with bogus values. */
5382 intel_crtc->fdi_lanes = 2;
5383
5384 return false;
5385 }
5386 } else {
5387 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5388 return false;
5389 }
5390
5391 cpt_enable_fdi_bc_bifurcation(dev);
5392
5393 return true;
5394 default:
5395 BUG();
5396 }
5397 }
5398
5399 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5400 {
5401 /*
5402 * Account for spread spectrum to avoid
5403 * oversubscribing the link. Max center spread
5404 * is 2.5%; use 5% for safety's sake.
5405 */
5406 u32 bps = target_clock * bpp * 21 / 20;
5407 return bps / (link_bw * 8) + 1;
5408 }
5409
5410 static void ironlake_set_m_n(struct drm_crtc *crtc,
5411 struct drm_display_mode *mode,
5412 struct drm_display_mode *adjusted_mode)
5413 {
5414 struct drm_device *dev = crtc->dev;
5415 struct drm_i915_private *dev_priv = dev->dev_private;
5416 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5417 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5418 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5419 struct intel_link_m_n m_n = {0};
5420 int target_clock, pixel_multiplier, lane, link_bw;
5421 bool is_dp = false, is_cpu_edp = false;
5422
5423 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5424 switch (intel_encoder->type) {
5425 case INTEL_OUTPUT_DISPLAYPORT:
5426 is_dp = true;
5427 break;
5428 case INTEL_OUTPUT_EDP:
5429 is_dp = true;
5430 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5431 is_cpu_edp = true;
5432 edp_encoder = intel_encoder;
5433 break;
5434 }
5435 }
5436
5437 /* FDI link */
5438 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5439 lane = 0;
5440 /* CPU eDP doesn't require FDI link, so just set DP M/N
5441 according to current link config */
5442 if (is_cpu_edp) {
5443 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5444 } else {
5445 /* FDI is a binary signal running at ~2.7GHz, encoding
5446 * each output octet as 10 bits. The actual frequency
5447 * is stored as a divider into a 100MHz clock, and the
5448 * mode pixel clock is stored in units of 1KHz.
5449 * Hence the bw of each lane in terms of the mode signal
5450 * is:
5451 */
5452 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5453 }
5454
5455 /* [e]DP over FDI requires target mode clock instead of link clock. */
5456 if (edp_encoder)
5457 target_clock = intel_edp_target_clock(edp_encoder, mode);
5458 else if (is_dp)
5459 target_clock = mode->clock;
5460 else
5461 target_clock = adjusted_mode->clock;
5462
5463 if (!lane)
5464 lane = ironlake_get_lanes_required(target_clock, link_bw,
5465 intel_crtc->bpp);
5466
5467 intel_crtc->fdi_lanes = lane;
5468
5469 if (pixel_multiplier > 1)
5470 link_bw *= pixel_multiplier;
5471 intel_link_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw, &m_n);
5472
5473 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5474 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5475 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5476 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
5477 }
5478
5479 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5480 struct drm_display_mode *adjusted_mode,
5481 intel_clock_t *clock, u32 fp)
5482 {
5483 struct drm_crtc *crtc = &intel_crtc->base;
5484 struct drm_device *dev = crtc->dev;
5485 struct drm_i915_private *dev_priv = dev->dev_private;
5486 struct intel_encoder *intel_encoder;
5487 uint32_t dpll;
5488 int factor, pixel_multiplier, num_connectors = 0;
5489 bool is_lvds = false, is_sdvo = false, is_tv = false;
5490 bool is_dp = false, is_cpu_edp = false;
5491
5492 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5493 switch (intel_encoder->type) {
5494 case INTEL_OUTPUT_LVDS:
5495 is_lvds = true;
5496 break;
5497 case INTEL_OUTPUT_SDVO:
5498 case INTEL_OUTPUT_HDMI:
5499 is_sdvo = true;
5500 if (intel_encoder->needs_tv_clock)
5501 is_tv = true;
5502 break;
5503 case INTEL_OUTPUT_TVOUT:
5504 is_tv = true;
5505 break;
5506 case INTEL_OUTPUT_DISPLAYPORT:
5507 is_dp = true;
5508 break;
5509 case INTEL_OUTPUT_EDP:
5510 is_dp = true;
5511 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5512 is_cpu_edp = true;
5513 break;
5514 }
5515
5516 num_connectors++;
5517 }
5518
5519 /* Enable autotuning of the PLL clock (if permissible) */
5520 factor = 21;
5521 if (is_lvds) {
5522 if ((intel_panel_use_ssc(dev_priv) &&
5523 dev_priv->lvds_ssc_freq == 100) ||
5524 intel_is_dual_link_lvds(dev))
5525 factor = 25;
5526 } else if (is_sdvo && is_tv)
5527 factor = 20;
5528
5529 if (clock->m < factor * clock->n)
5530 fp |= FP_CB_TUNE;
5531
5532 dpll = 0;
5533
5534 if (is_lvds)
5535 dpll |= DPLLB_MODE_LVDS;
5536 else
5537 dpll |= DPLLB_MODE_DAC_SERIAL;
5538 if (is_sdvo) {
5539 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5540 if (pixel_multiplier > 1) {
5541 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5542 }
5543 dpll |= DPLL_DVO_HIGH_SPEED;
5544 }
5545 if (is_dp && !is_cpu_edp)
5546 dpll |= DPLL_DVO_HIGH_SPEED;
5547
5548 /* compute bitmask from p1 value */
5549 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5550 /* also FPA1 */
5551 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5552
5553 switch (clock->p2) {
5554 case 5:
5555 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5556 break;
5557 case 7:
5558 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5559 break;
5560 case 10:
5561 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5562 break;
5563 case 14:
5564 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5565 break;
5566 }
5567
5568 if (is_sdvo && is_tv)
5569 dpll |= PLL_REF_INPUT_TVCLKINBC;
5570 else if (is_tv)
5571 /* XXX: just matching BIOS for now */
5572 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5573 dpll |= 3;
5574 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5575 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5576 else
5577 dpll |= PLL_REF_INPUT_DREFCLK;
5578
5579 return dpll;
5580 }
5581
5582 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5583 struct drm_display_mode *mode,
5584 struct drm_display_mode *adjusted_mode,
5585 int x, int y,
5586 struct drm_framebuffer *fb)
5587 {
5588 struct drm_device *dev = crtc->dev;
5589 struct drm_i915_private *dev_priv = dev->dev_private;
5590 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5591 int pipe = intel_crtc->pipe;
5592 int plane = intel_crtc->plane;
5593 int num_connectors = 0;
5594 intel_clock_t clock, reduced_clock;
5595 u32 dpll, fp = 0, fp2 = 0;
5596 bool ok, has_reduced_clock = false;
5597 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5598 struct intel_encoder *encoder;
5599 int ret;
5600 bool dither, fdi_config_ok;
5601
5602 for_each_encoder_on_crtc(dev, crtc, encoder) {
5603 switch (encoder->type) {
5604 case INTEL_OUTPUT_LVDS:
5605 is_lvds = true;
5606 break;
5607 case INTEL_OUTPUT_DISPLAYPORT:
5608 is_dp = true;
5609 break;
5610 case INTEL_OUTPUT_EDP:
5611 is_dp = true;
5612 if (!intel_encoder_is_pch_edp(&encoder->base))
5613 is_cpu_edp = true;
5614 break;
5615 }
5616
5617 num_connectors++;
5618 }
5619
5620 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5621 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5622
5623 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5624 &has_reduced_clock, &reduced_clock);
5625 if (!ok) {
5626 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5627 return -EINVAL;
5628 }
5629
5630 /* Ensure that the cursor is valid for the new mode before changing... */
5631 intel_crtc_update_cursor(crtc, true);
5632
5633 /* determine panel color depth */
5634 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5635 adjusted_mode);
5636 if (is_lvds && dev_priv->lvds_dither)
5637 dither = true;
5638
5639 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5640 if (has_reduced_clock)
5641 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5642 reduced_clock.m2;
5643
5644 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5645
5646 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5647 drm_mode_debug_printmodeline(mode);
5648
5649 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5650 if (!is_cpu_edp) {
5651 struct intel_pch_pll *pll;
5652
5653 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5654 if (pll == NULL) {
5655 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5656 pipe);
5657 return -EINVAL;
5658 }
5659 } else
5660 intel_put_pch_pll(intel_crtc);
5661
5662 if (is_dp && !is_cpu_edp)
5663 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5664
5665 for_each_encoder_on_crtc(dev, crtc, encoder)
5666 if (encoder->pre_pll_enable)
5667 encoder->pre_pll_enable(encoder);
5668
5669 if (intel_crtc->pch_pll) {
5670 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5671
5672 /* Wait for the clocks to stabilize. */
5673 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5674 udelay(150);
5675
5676 /* The pixel multiplier can only be updated once the
5677 * DPLL is enabled and the clocks are stable.
5678 *
5679 * So write it again.
5680 */
5681 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5682 }
5683
5684 intel_crtc->lowfreq_avail = false;
5685 if (intel_crtc->pch_pll) {
5686 if (is_lvds && has_reduced_clock && i915_powersave) {
5687 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5688 intel_crtc->lowfreq_avail = true;
5689 } else {
5690 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5691 }
5692 }
5693
5694 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5695
5696 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5697 * ironlake_check_fdi_lanes. */
5698 ironlake_set_m_n(crtc, mode, adjusted_mode);
5699
5700 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5701
5702 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5703
5704 intel_wait_for_vblank(dev, pipe);
5705
5706 /* Set up the display plane register */
5707 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5708 POSTING_READ(DSPCNTR(plane));
5709
5710 ret = intel_pipe_set_base(crtc, x, y, fb);
5711
5712 intel_update_watermarks(dev);
5713
5714 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5715
5716 return fdi_config_ok ? ret : -EINVAL;
5717 }
5718
5719 static void haswell_modeset_global_resources(struct drm_device *dev)
5720 {
5721 struct drm_i915_private *dev_priv = dev->dev_private;
5722 bool enable = false;
5723 struct intel_crtc *crtc;
5724 struct intel_encoder *encoder;
5725
5726 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5727 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5728 enable = true;
5729 /* XXX: Should check for edp transcoder here, but thanks to init
5730 * sequence that's not yet available. Just in case desktop eDP
5731 * on PORT D is possible on haswell, too. */
5732 }
5733
5734 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5735 base.head) {
5736 if (encoder->type != INTEL_OUTPUT_EDP &&
5737 encoder->connectors_active)
5738 enable = true;
5739 }
5740
5741 /* Even the eDP panel fitter is outside the always-on well. */
5742 if (dev_priv->pch_pf_size)
5743 enable = true;
5744
5745 intel_set_power_well(dev, enable);
5746 }
5747
5748 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5749 struct drm_display_mode *mode,
5750 struct drm_display_mode *adjusted_mode,
5751 int x, int y,
5752 struct drm_framebuffer *fb)
5753 {
5754 struct drm_device *dev = crtc->dev;
5755 struct drm_i915_private *dev_priv = dev->dev_private;
5756 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5757 int pipe = intel_crtc->pipe;
5758 int plane = intel_crtc->plane;
5759 int num_connectors = 0;
5760 bool is_dp = false, is_cpu_edp = false;
5761 struct intel_encoder *encoder;
5762 int ret;
5763 bool dither;
5764
5765 for_each_encoder_on_crtc(dev, crtc, encoder) {
5766 switch (encoder->type) {
5767 case INTEL_OUTPUT_DISPLAYPORT:
5768 is_dp = true;
5769 break;
5770 case INTEL_OUTPUT_EDP:
5771 is_dp = true;
5772 if (!intel_encoder_is_pch_edp(&encoder->base))
5773 is_cpu_edp = true;
5774 break;
5775 }
5776
5777 num_connectors++;
5778 }
5779
5780 /* We are not sure yet this won't happen. */
5781 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5782 INTEL_PCH_TYPE(dev));
5783
5784 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5785 num_connectors, pipe_name(pipe));
5786
5787 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
5788 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5789
5790 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5791
5792 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5793 return -EINVAL;
5794
5795 /* Ensure that the cursor is valid for the new mode before changing... */
5796 intel_crtc_update_cursor(crtc, true);
5797
5798 /* determine panel color depth */
5799 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5800 adjusted_mode);
5801
5802 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5803 drm_mode_debug_printmodeline(mode);
5804
5805 if (is_dp && !is_cpu_edp)
5806 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5807
5808 intel_crtc->lowfreq_avail = false;
5809
5810 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5811
5812 if (!is_dp || is_cpu_edp)
5813 ironlake_set_m_n(crtc, mode, adjusted_mode);
5814
5815 haswell_set_pipeconf(crtc, adjusted_mode, dither);
5816
5817 intel_set_pipe_csc(crtc, adjusted_mode);
5818
5819 /* Set up the display plane register */
5820 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
5821 POSTING_READ(DSPCNTR(plane));
5822
5823 ret = intel_pipe_set_base(crtc, x, y, fb);
5824
5825 intel_update_watermarks(dev);
5826
5827 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5828
5829 return ret;
5830 }
5831
5832 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5833 struct drm_display_mode *mode,
5834 struct drm_display_mode *adjusted_mode,
5835 int x, int y,
5836 struct drm_framebuffer *fb)
5837 {
5838 struct drm_device *dev = crtc->dev;
5839 struct drm_i915_private *dev_priv = dev->dev_private;
5840 struct drm_encoder_helper_funcs *encoder_funcs;
5841 struct intel_encoder *encoder;
5842 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5843 int pipe = intel_crtc->pipe;
5844 int ret;
5845
5846 if (IS_HASWELL(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5847 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5848 else
5849 intel_crtc->cpu_transcoder = pipe;
5850
5851 drm_vblank_pre_modeset(dev, pipe);
5852
5853 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5854 x, y, fb);
5855 drm_vblank_post_modeset(dev, pipe);
5856
5857 if (ret != 0)
5858 return ret;
5859
5860 for_each_encoder_on_crtc(dev, crtc, encoder) {
5861 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5862 encoder->base.base.id,
5863 drm_get_encoder_name(&encoder->base),
5864 mode->base.id, mode->name);
5865 encoder_funcs = encoder->base.helper_private;
5866 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5867 }
5868
5869 return 0;
5870 }
5871
5872 static bool intel_eld_uptodate(struct drm_connector *connector,
5873 int reg_eldv, uint32_t bits_eldv,
5874 int reg_elda, uint32_t bits_elda,
5875 int reg_edid)
5876 {
5877 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5878 uint8_t *eld = connector->eld;
5879 uint32_t i;
5880
5881 i = I915_READ(reg_eldv);
5882 i &= bits_eldv;
5883
5884 if (!eld[0])
5885 return !i;
5886
5887 if (!i)
5888 return false;
5889
5890 i = I915_READ(reg_elda);
5891 i &= ~bits_elda;
5892 I915_WRITE(reg_elda, i);
5893
5894 for (i = 0; i < eld[2]; i++)
5895 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5896 return false;
5897
5898 return true;
5899 }
5900
5901 static void g4x_write_eld(struct drm_connector *connector,
5902 struct drm_crtc *crtc)
5903 {
5904 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5905 uint8_t *eld = connector->eld;
5906 uint32_t eldv;
5907 uint32_t len;
5908 uint32_t i;
5909
5910 i = I915_READ(G4X_AUD_VID_DID);
5911
5912 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5913 eldv = G4X_ELDV_DEVCL_DEVBLC;
5914 else
5915 eldv = G4X_ELDV_DEVCTG;
5916
5917 if (intel_eld_uptodate(connector,
5918 G4X_AUD_CNTL_ST, eldv,
5919 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5920 G4X_HDMIW_HDMIEDID))
5921 return;
5922
5923 i = I915_READ(G4X_AUD_CNTL_ST);
5924 i &= ~(eldv | G4X_ELD_ADDR);
5925 len = (i >> 9) & 0x1f; /* ELD buffer size */
5926 I915_WRITE(G4X_AUD_CNTL_ST, i);
5927
5928 if (!eld[0])
5929 return;
5930
5931 len = min_t(uint8_t, eld[2], len);
5932 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5933 for (i = 0; i < len; i++)
5934 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5935
5936 i = I915_READ(G4X_AUD_CNTL_ST);
5937 i |= eldv;
5938 I915_WRITE(G4X_AUD_CNTL_ST, i);
5939 }
5940
5941 static void haswell_write_eld(struct drm_connector *connector,
5942 struct drm_crtc *crtc)
5943 {
5944 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5945 uint8_t *eld = connector->eld;
5946 struct drm_device *dev = crtc->dev;
5947 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5948 uint32_t eldv;
5949 uint32_t i;
5950 int len;
5951 int pipe = to_intel_crtc(crtc)->pipe;
5952 int tmp;
5953
5954 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5955 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5956 int aud_config = HSW_AUD_CFG(pipe);
5957 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5958
5959
5960 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5961
5962 /* Audio output enable */
5963 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5964 tmp = I915_READ(aud_cntrl_st2);
5965 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5966 I915_WRITE(aud_cntrl_st2, tmp);
5967
5968 /* Wait for 1 vertical blank */
5969 intel_wait_for_vblank(dev, pipe);
5970
5971 /* Set ELD valid state */
5972 tmp = I915_READ(aud_cntrl_st2);
5973 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5974 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5975 I915_WRITE(aud_cntrl_st2, tmp);
5976 tmp = I915_READ(aud_cntrl_st2);
5977 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5978
5979 /* Enable HDMI mode */
5980 tmp = I915_READ(aud_config);
5981 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5982 /* clear N_programing_enable and N_value_index */
5983 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5984 I915_WRITE(aud_config, tmp);
5985
5986 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5987
5988 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5989 intel_crtc->eld_vld = true;
5990
5991 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5992 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5993 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5994 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5995 } else
5996 I915_WRITE(aud_config, 0);
5997
5998 if (intel_eld_uptodate(connector,
5999 aud_cntrl_st2, eldv,
6000 aud_cntl_st, IBX_ELD_ADDRESS,
6001 hdmiw_hdmiedid))
6002 return;
6003
6004 i = I915_READ(aud_cntrl_st2);
6005 i &= ~eldv;
6006 I915_WRITE(aud_cntrl_st2, i);
6007
6008 if (!eld[0])
6009 return;
6010
6011 i = I915_READ(aud_cntl_st);
6012 i &= ~IBX_ELD_ADDRESS;
6013 I915_WRITE(aud_cntl_st, i);
6014 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6015 DRM_DEBUG_DRIVER("port num:%d\n", i);
6016
6017 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6018 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6019 for (i = 0; i < len; i++)
6020 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6021
6022 i = I915_READ(aud_cntrl_st2);
6023 i |= eldv;
6024 I915_WRITE(aud_cntrl_st2, i);
6025
6026 }
6027
6028 static void ironlake_write_eld(struct drm_connector *connector,
6029 struct drm_crtc *crtc)
6030 {
6031 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6032 uint8_t *eld = connector->eld;
6033 uint32_t eldv;
6034 uint32_t i;
6035 int len;
6036 int hdmiw_hdmiedid;
6037 int aud_config;
6038 int aud_cntl_st;
6039 int aud_cntrl_st2;
6040 int pipe = to_intel_crtc(crtc)->pipe;
6041
6042 if (HAS_PCH_IBX(connector->dev)) {
6043 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6044 aud_config = IBX_AUD_CFG(pipe);
6045 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6046 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6047 } else {
6048 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6049 aud_config = CPT_AUD_CFG(pipe);
6050 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6051 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6052 }
6053
6054 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6055
6056 i = I915_READ(aud_cntl_st);
6057 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6058 if (!i) {
6059 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6060 /* operate blindly on all ports */
6061 eldv = IBX_ELD_VALIDB;
6062 eldv |= IBX_ELD_VALIDB << 4;
6063 eldv |= IBX_ELD_VALIDB << 8;
6064 } else {
6065 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6066 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6067 }
6068
6069 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6070 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6071 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6072 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6073 } else
6074 I915_WRITE(aud_config, 0);
6075
6076 if (intel_eld_uptodate(connector,
6077 aud_cntrl_st2, eldv,
6078 aud_cntl_st, IBX_ELD_ADDRESS,
6079 hdmiw_hdmiedid))
6080 return;
6081
6082 i = I915_READ(aud_cntrl_st2);
6083 i &= ~eldv;
6084 I915_WRITE(aud_cntrl_st2, i);
6085
6086 if (!eld[0])
6087 return;
6088
6089 i = I915_READ(aud_cntl_st);
6090 i &= ~IBX_ELD_ADDRESS;
6091 I915_WRITE(aud_cntl_st, i);
6092
6093 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6094 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6095 for (i = 0; i < len; i++)
6096 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6097
6098 i = I915_READ(aud_cntrl_st2);
6099 i |= eldv;
6100 I915_WRITE(aud_cntrl_st2, i);
6101 }
6102
6103 void intel_write_eld(struct drm_encoder *encoder,
6104 struct drm_display_mode *mode)
6105 {
6106 struct drm_crtc *crtc = encoder->crtc;
6107 struct drm_connector *connector;
6108 struct drm_device *dev = encoder->dev;
6109 struct drm_i915_private *dev_priv = dev->dev_private;
6110
6111 connector = drm_select_eld(encoder, mode);
6112 if (!connector)
6113 return;
6114
6115 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6116 connector->base.id,
6117 drm_get_connector_name(connector),
6118 connector->encoder->base.id,
6119 drm_get_encoder_name(connector->encoder));
6120
6121 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6122
6123 if (dev_priv->display.write_eld)
6124 dev_priv->display.write_eld(connector, crtc);
6125 }
6126
6127 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6128 void intel_crtc_load_lut(struct drm_crtc *crtc)
6129 {
6130 struct drm_device *dev = crtc->dev;
6131 struct drm_i915_private *dev_priv = dev->dev_private;
6132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6133 int palreg = PALETTE(intel_crtc->pipe);
6134 int i;
6135
6136 /* The clocks have to be on to load the palette. */
6137 if (!crtc->enabled || !intel_crtc->active)
6138 return;
6139
6140 /* use legacy palette for Ironlake */
6141 if (HAS_PCH_SPLIT(dev))
6142 palreg = LGC_PALETTE(intel_crtc->pipe);
6143
6144 for (i = 0; i < 256; i++) {
6145 I915_WRITE(palreg + 4 * i,
6146 (intel_crtc->lut_r[i] << 16) |
6147 (intel_crtc->lut_g[i] << 8) |
6148 intel_crtc->lut_b[i]);
6149 }
6150 }
6151
6152 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6153 {
6154 struct drm_device *dev = crtc->dev;
6155 struct drm_i915_private *dev_priv = dev->dev_private;
6156 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6157 bool visible = base != 0;
6158 u32 cntl;
6159
6160 if (intel_crtc->cursor_visible == visible)
6161 return;
6162
6163 cntl = I915_READ(_CURACNTR);
6164 if (visible) {
6165 /* On these chipsets we can only modify the base whilst
6166 * the cursor is disabled.
6167 */
6168 I915_WRITE(_CURABASE, base);
6169
6170 cntl &= ~(CURSOR_FORMAT_MASK);
6171 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6172 cntl |= CURSOR_ENABLE |
6173 CURSOR_GAMMA_ENABLE |
6174 CURSOR_FORMAT_ARGB;
6175 } else
6176 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6177 I915_WRITE(_CURACNTR, cntl);
6178
6179 intel_crtc->cursor_visible = visible;
6180 }
6181
6182 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6183 {
6184 struct drm_device *dev = crtc->dev;
6185 struct drm_i915_private *dev_priv = dev->dev_private;
6186 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6187 int pipe = intel_crtc->pipe;
6188 bool visible = base != 0;
6189
6190 if (intel_crtc->cursor_visible != visible) {
6191 uint32_t cntl = I915_READ(CURCNTR(pipe));
6192 if (base) {
6193 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6194 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6195 cntl |= pipe << 28; /* Connect to correct pipe */
6196 } else {
6197 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6198 cntl |= CURSOR_MODE_DISABLE;
6199 }
6200 I915_WRITE(CURCNTR(pipe), cntl);
6201
6202 intel_crtc->cursor_visible = visible;
6203 }
6204 /* and commit changes on next vblank */
6205 I915_WRITE(CURBASE(pipe), base);
6206 }
6207
6208 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6209 {
6210 struct drm_device *dev = crtc->dev;
6211 struct drm_i915_private *dev_priv = dev->dev_private;
6212 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6213 int pipe = intel_crtc->pipe;
6214 bool visible = base != 0;
6215
6216 if (intel_crtc->cursor_visible != visible) {
6217 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6218 if (base) {
6219 cntl &= ~CURSOR_MODE;
6220 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6221 } else {
6222 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6223 cntl |= CURSOR_MODE_DISABLE;
6224 }
6225 if (IS_HASWELL(dev))
6226 cntl |= CURSOR_PIPE_CSC_ENABLE;
6227 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6228
6229 intel_crtc->cursor_visible = visible;
6230 }
6231 /* and commit changes on next vblank */
6232 I915_WRITE(CURBASE_IVB(pipe), base);
6233 }
6234
6235 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6236 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6237 bool on)
6238 {
6239 struct drm_device *dev = crtc->dev;
6240 struct drm_i915_private *dev_priv = dev->dev_private;
6241 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6242 int pipe = intel_crtc->pipe;
6243 int x = intel_crtc->cursor_x;
6244 int y = intel_crtc->cursor_y;
6245 u32 base, pos;
6246 bool visible;
6247
6248 pos = 0;
6249
6250 if (on && crtc->enabled && crtc->fb) {
6251 base = intel_crtc->cursor_addr;
6252 if (x > (int) crtc->fb->width)
6253 base = 0;
6254
6255 if (y > (int) crtc->fb->height)
6256 base = 0;
6257 } else
6258 base = 0;
6259
6260 if (x < 0) {
6261 if (x + intel_crtc->cursor_width < 0)
6262 base = 0;
6263
6264 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6265 x = -x;
6266 }
6267 pos |= x << CURSOR_X_SHIFT;
6268
6269 if (y < 0) {
6270 if (y + intel_crtc->cursor_height < 0)
6271 base = 0;
6272
6273 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6274 y = -y;
6275 }
6276 pos |= y << CURSOR_Y_SHIFT;
6277
6278 visible = base != 0;
6279 if (!visible && !intel_crtc->cursor_visible)
6280 return;
6281
6282 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6283 I915_WRITE(CURPOS_IVB(pipe), pos);
6284 ivb_update_cursor(crtc, base);
6285 } else {
6286 I915_WRITE(CURPOS(pipe), pos);
6287 if (IS_845G(dev) || IS_I865G(dev))
6288 i845_update_cursor(crtc, base);
6289 else
6290 i9xx_update_cursor(crtc, base);
6291 }
6292 }
6293
6294 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6295 struct drm_file *file,
6296 uint32_t handle,
6297 uint32_t width, uint32_t height)
6298 {
6299 struct drm_device *dev = crtc->dev;
6300 struct drm_i915_private *dev_priv = dev->dev_private;
6301 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6302 struct drm_i915_gem_object *obj;
6303 uint32_t addr;
6304 int ret;
6305
6306 /* if we want to turn off the cursor ignore width and height */
6307 if (!handle) {
6308 DRM_DEBUG_KMS("cursor off\n");
6309 addr = 0;
6310 obj = NULL;
6311 mutex_lock(&dev->struct_mutex);
6312 goto finish;
6313 }
6314
6315 /* Currently we only support 64x64 cursors */
6316 if (width != 64 || height != 64) {
6317 DRM_ERROR("we currently only support 64x64 cursors\n");
6318 return -EINVAL;
6319 }
6320
6321 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6322 if (&obj->base == NULL)
6323 return -ENOENT;
6324
6325 if (obj->base.size < width * height * 4) {
6326 DRM_ERROR("buffer is to small\n");
6327 ret = -ENOMEM;
6328 goto fail;
6329 }
6330
6331 /* we only need to pin inside GTT if cursor is non-phy */
6332 mutex_lock(&dev->struct_mutex);
6333 if (!dev_priv->info->cursor_needs_physical) {
6334 if (obj->tiling_mode) {
6335 DRM_ERROR("cursor cannot be tiled\n");
6336 ret = -EINVAL;
6337 goto fail_locked;
6338 }
6339
6340 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6341 if (ret) {
6342 DRM_ERROR("failed to move cursor bo into the GTT\n");
6343 goto fail_locked;
6344 }
6345
6346 ret = i915_gem_object_put_fence(obj);
6347 if (ret) {
6348 DRM_ERROR("failed to release fence for cursor");
6349 goto fail_unpin;
6350 }
6351
6352 addr = obj->gtt_offset;
6353 } else {
6354 int align = IS_I830(dev) ? 16 * 1024 : 256;
6355 ret = i915_gem_attach_phys_object(dev, obj,
6356 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6357 align);
6358 if (ret) {
6359 DRM_ERROR("failed to attach phys object\n");
6360 goto fail_locked;
6361 }
6362 addr = obj->phys_obj->handle->busaddr;
6363 }
6364
6365 if (IS_GEN2(dev))
6366 I915_WRITE(CURSIZE, (height << 12) | width);
6367
6368 finish:
6369 if (intel_crtc->cursor_bo) {
6370 if (dev_priv->info->cursor_needs_physical) {
6371 if (intel_crtc->cursor_bo != obj)
6372 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6373 } else
6374 i915_gem_object_unpin(intel_crtc->cursor_bo);
6375 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6376 }
6377
6378 mutex_unlock(&dev->struct_mutex);
6379
6380 intel_crtc->cursor_addr = addr;
6381 intel_crtc->cursor_bo = obj;
6382 intel_crtc->cursor_width = width;
6383 intel_crtc->cursor_height = height;
6384
6385 intel_crtc_update_cursor(crtc, true);
6386
6387 return 0;
6388 fail_unpin:
6389 i915_gem_object_unpin(obj);
6390 fail_locked:
6391 mutex_unlock(&dev->struct_mutex);
6392 fail:
6393 drm_gem_object_unreference_unlocked(&obj->base);
6394 return ret;
6395 }
6396
6397 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6398 {
6399 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6400
6401 intel_crtc->cursor_x = x;
6402 intel_crtc->cursor_y = y;
6403
6404 intel_crtc_update_cursor(crtc, true);
6405
6406 return 0;
6407 }
6408
6409 /** Sets the color ramps on behalf of RandR */
6410 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6411 u16 blue, int regno)
6412 {
6413 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6414
6415 intel_crtc->lut_r[regno] = red >> 8;
6416 intel_crtc->lut_g[regno] = green >> 8;
6417 intel_crtc->lut_b[regno] = blue >> 8;
6418 }
6419
6420 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6421 u16 *blue, int regno)
6422 {
6423 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6424
6425 *red = intel_crtc->lut_r[regno] << 8;
6426 *green = intel_crtc->lut_g[regno] << 8;
6427 *blue = intel_crtc->lut_b[regno] << 8;
6428 }
6429
6430 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6431 u16 *blue, uint32_t start, uint32_t size)
6432 {
6433 int end = (start + size > 256) ? 256 : start + size, i;
6434 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6435
6436 for (i = start; i < end; i++) {
6437 intel_crtc->lut_r[i] = red[i] >> 8;
6438 intel_crtc->lut_g[i] = green[i] >> 8;
6439 intel_crtc->lut_b[i] = blue[i] >> 8;
6440 }
6441
6442 intel_crtc_load_lut(crtc);
6443 }
6444
6445 /**
6446 * Get a pipe with a simple mode set on it for doing load-based monitor
6447 * detection.
6448 *
6449 * It will be up to the load-detect code to adjust the pipe as appropriate for
6450 * its requirements. The pipe will be connected to no other encoders.
6451 *
6452 * Currently this code will only succeed if there is a pipe with no encoders
6453 * configured for it. In the future, it could choose to temporarily disable
6454 * some outputs to free up a pipe for its use.
6455 *
6456 * \return crtc, or NULL if no pipes are available.
6457 */
6458
6459 /* VESA 640x480x72Hz mode to set on the pipe */
6460 static struct drm_display_mode load_detect_mode = {
6461 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6462 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6463 };
6464
6465 static struct drm_framebuffer *
6466 intel_framebuffer_create(struct drm_device *dev,
6467 struct drm_mode_fb_cmd2 *mode_cmd,
6468 struct drm_i915_gem_object *obj)
6469 {
6470 struct intel_framebuffer *intel_fb;
6471 int ret;
6472
6473 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6474 if (!intel_fb) {
6475 drm_gem_object_unreference_unlocked(&obj->base);
6476 return ERR_PTR(-ENOMEM);
6477 }
6478
6479 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6480 if (ret) {
6481 drm_gem_object_unreference_unlocked(&obj->base);
6482 kfree(intel_fb);
6483 return ERR_PTR(ret);
6484 }
6485
6486 return &intel_fb->base;
6487 }
6488
6489 static u32
6490 intel_framebuffer_pitch_for_width(int width, int bpp)
6491 {
6492 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6493 return ALIGN(pitch, 64);
6494 }
6495
6496 static u32
6497 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6498 {
6499 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6500 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6501 }
6502
6503 static struct drm_framebuffer *
6504 intel_framebuffer_create_for_mode(struct drm_device *dev,
6505 struct drm_display_mode *mode,
6506 int depth, int bpp)
6507 {
6508 struct drm_i915_gem_object *obj;
6509 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6510
6511 obj = i915_gem_alloc_object(dev,
6512 intel_framebuffer_size_for_mode(mode, bpp));
6513 if (obj == NULL)
6514 return ERR_PTR(-ENOMEM);
6515
6516 mode_cmd.width = mode->hdisplay;
6517 mode_cmd.height = mode->vdisplay;
6518 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6519 bpp);
6520 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6521
6522 return intel_framebuffer_create(dev, &mode_cmd, obj);
6523 }
6524
6525 static struct drm_framebuffer *
6526 mode_fits_in_fbdev(struct drm_device *dev,
6527 struct drm_display_mode *mode)
6528 {
6529 struct drm_i915_private *dev_priv = dev->dev_private;
6530 struct drm_i915_gem_object *obj;
6531 struct drm_framebuffer *fb;
6532
6533 if (dev_priv->fbdev == NULL)
6534 return NULL;
6535
6536 obj = dev_priv->fbdev->ifb.obj;
6537 if (obj == NULL)
6538 return NULL;
6539
6540 fb = &dev_priv->fbdev->ifb.base;
6541 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6542 fb->bits_per_pixel))
6543 return NULL;
6544
6545 if (obj->base.size < mode->vdisplay * fb->pitches[0])
6546 return NULL;
6547
6548 return fb;
6549 }
6550
6551 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6552 struct drm_display_mode *mode,
6553 struct intel_load_detect_pipe *old)
6554 {
6555 struct intel_crtc *intel_crtc;
6556 struct intel_encoder *intel_encoder =
6557 intel_attached_encoder(connector);
6558 struct drm_crtc *possible_crtc;
6559 struct drm_encoder *encoder = &intel_encoder->base;
6560 struct drm_crtc *crtc = NULL;
6561 struct drm_device *dev = encoder->dev;
6562 struct drm_framebuffer *fb;
6563 int i = -1;
6564
6565 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6566 connector->base.id, drm_get_connector_name(connector),
6567 encoder->base.id, drm_get_encoder_name(encoder));
6568
6569 /*
6570 * Algorithm gets a little messy:
6571 *
6572 * - if the connector already has an assigned crtc, use it (but make
6573 * sure it's on first)
6574 *
6575 * - try to find the first unused crtc that can drive this connector,
6576 * and use that if we find one
6577 */
6578
6579 /* See if we already have a CRTC for this connector */
6580 if (encoder->crtc) {
6581 crtc = encoder->crtc;
6582
6583 mutex_lock(&crtc->mutex);
6584
6585 old->dpms_mode = connector->dpms;
6586 old->load_detect_temp = false;
6587
6588 /* Make sure the crtc and connector are running */
6589 if (connector->dpms != DRM_MODE_DPMS_ON)
6590 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6591
6592 return true;
6593 }
6594
6595 /* Find an unused one (if possible) */
6596 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6597 i++;
6598 if (!(encoder->possible_crtcs & (1 << i)))
6599 continue;
6600 if (!possible_crtc->enabled) {
6601 crtc = possible_crtc;
6602 break;
6603 }
6604 }
6605
6606 /*
6607 * If we didn't find an unused CRTC, don't use any.
6608 */
6609 if (!crtc) {
6610 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6611 return false;
6612 }
6613
6614 mutex_lock(&crtc->mutex);
6615 intel_encoder->new_crtc = to_intel_crtc(crtc);
6616 to_intel_connector(connector)->new_encoder = intel_encoder;
6617
6618 intel_crtc = to_intel_crtc(crtc);
6619 old->dpms_mode = connector->dpms;
6620 old->load_detect_temp = true;
6621 old->release_fb = NULL;
6622
6623 if (!mode)
6624 mode = &load_detect_mode;
6625
6626 /* We need a framebuffer large enough to accommodate all accesses
6627 * that the plane may generate whilst we perform load detection.
6628 * We can not rely on the fbcon either being present (we get called
6629 * during its initialisation to detect all boot displays, or it may
6630 * not even exist) or that it is large enough to satisfy the
6631 * requested mode.
6632 */
6633 fb = mode_fits_in_fbdev(dev, mode);
6634 if (fb == NULL) {
6635 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6636 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6637 old->release_fb = fb;
6638 } else
6639 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6640 if (IS_ERR(fb)) {
6641 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6642 mutex_unlock(&crtc->mutex);
6643 return false;
6644 }
6645
6646 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6647 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6648 if (old->release_fb)
6649 old->release_fb->funcs->destroy(old->release_fb);
6650 mutex_unlock(&crtc->mutex);
6651 return false;
6652 }
6653
6654 /* let the connector get through one full cycle before testing */
6655 intel_wait_for_vblank(dev, intel_crtc->pipe);
6656 return true;
6657 }
6658
6659 void intel_release_load_detect_pipe(struct drm_connector *connector,
6660 struct intel_load_detect_pipe *old)
6661 {
6662 struct intel_encoder *intel_encoder =
6663 intel_attached_encoder(connector);
6664 struct drm_encoder *encoder = &intel_encoder->base;
6665 struct drm_crtc *crtc = encoder->crtc;
6666
6667 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6668 connector->base.id, drm_get_connector_name(connector),
6669 encoder->base.id, drm_get_encoder_name(encoder));
6670
6671 if (old->load_detect_temp) {
6672 to_intel_connector(connector)->new_encoder = NULL;
6673 intel_encoder->new_crtc = NULL;
6674 intel_set_mode(crtc, NULL, 0, 0, NULL);
6675
6676 if (old->release_fb) {
6677 drm_framebuffer_unregister_private(old->release_fb);
6678 drm_framebuffer_unreference(old->release_fb);
6679 }
6680
6681 mutex_unlock(&crtc->mutex);
6682 return;
6683 }
6684
6685 /* Switch crtc and encoder back off if necessary */
6686 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6687 connector->funcs->dpms(connector, old->dpms_mode);
6688
6689 mutex_unlock(&crtc->mutex);
6690 }
6691
6692 /* Returns the clock of the currently programmed mode of the given pipe. */
6693 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6694 {
6695 struct drm_i915_private *dev_priv = dev->dev_private;
6696 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6697 int pipe = intel_crtc->pipe;
6698 u32 dpll = I915_READ(DPLL(pipe));
6699 u32 fp;
6700 intel_clock_t clock;
6701
6702 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6703 fp = I915_READ(FP0(pipe));
6704 else
6705 fp = I915_READ(FP1(pipe));
6706
6707 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6708 if (IS_PINEVIEW(dev)) {
6709 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6710 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6711 } else {
6712 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6713 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6714 }
6715
6716 if (!IS_GEN2(dev)) {
6717 if (IS_PINEVIEW(dev))
6718 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6719 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6720 else
6721 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6722 DPLL_FPA01_P1_POST_DIV_SHIFT);
6723
6724 switch (dpll & DPLL_MODE_MASK) {
6725 case DPLLB_MODE_DAC_SERIAL:
6726 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6727 5 : 10;
6728 break;
6729 case DPLLB_MODE_LVDS:
6730 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6731 7 : 14;
6732 break;
6733 default:
6734 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6735 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6736 return 0;
6737 }
6738
6739 /* XXX: Handle the 100Mhz refclk */
6740 intel_clock(dev, 96000, &clock);
6741 } else {
6742 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6743
6744 if (is_lvds) {
6745 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6746 DPLL_FPA01_P1_POST_DIV_SHIFT);
6747 clock.p2 = 14;
6748
6749 if ((dpll & PLL_REF_INPUT_MASK) ==
6750 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6751 /* XXX: might not be 66MHz */
6752 intel_clock(dev, 66000, &clock);
6753 } else
6754 intel_clock(dev, 48000, &clock);
6755 } else {
6756 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6757 clock.p1 = 2;
6758 else {
6759 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6760 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6761 }
6762 if (dpll & PLL_P2_DIVIDE_BY_4)
6763 clock.p2 = 4;
6764 else
6765 clock.p2 = 2;
6766
6767 intel_clock(dev, 48000, &clock);
6768 }
6769 }
6770
6771 /* XXX: It would be nice to validate the clocks, but we can't reuse
6772 * i830PllIsValid() because it relies on the xf86_config connector
6773 * configuration being accurate, which it isn't necessarily.
6774 */
6775
6776 return clock.dot;
6777 }
6778
6779 /** Returns the currently programmed mode of the given pipe. */
6780 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6781 struct drm_crtc *crtc)
6782 {
6783 struct drm_i915_private *dev_priv = dev->dev_private;
6784 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6785 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
6786 struct drm_display_mode *mode;
6787 int htot = I915_READ(HTOTAL(cpu_transcoder));
6788 int hsync = I915_READ(HSYNC(cpu_transcoder));
6789 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6790 int vsync = I915_READ(VSYNC(cpu_transcoder));
6791
6792 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6793 if (!mode)
6794 return NULL;
6795
6796 mode->clock = intel_crtc_clock_get(dev, crtc);
6797 mode->hdisplay = (htot & 0xffff) + 1;
6798 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6799 mode->hsync_start = (hsync & 0xffff) + 1;
6800 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6801 mode->vdisplay = (vtot & 0xffff) + 1;
6802 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6803 mode->vsync_start = (vsync & 0xffff) + 1;
6804 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6805
6806 drm_mode_set_name(mode);
6807
6808 return mode;
6809 }
6810
6811 static void intel_increase_pllclock(struct drm_crtc *crtc)
6812 {
6813 struct drm_device *dev = crtc->dev;
6814 drm_i915_private_t *dev_priv = dev->dev_private;
6815 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6816 int pipe = intel_crtc->pipe;
6817 int dpll_reg = DPLL(pipe);
6818 int dpll;
6819
6820 if (HAS_PCH_SPLIT(dev))
6821 return;
6822
6823 if (!dev_priv->lvds_downclock_avail)
6824 return;
6825
6826 dpll = I915_READ(dpll_reg);
6827 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6828 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6829
6830 assert_panel_unlocked(dev_priv, pipe);
6831
6832 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6833 I915_WRITE(dpll_reg, dpll);
6834 intel_wait_for_vblank(dev, pipe);
6835
6836 dpll = I915_READ(dpll_reg);
6837 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6838 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6839 }
6840 }
6841
6842 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6843 {
6844 struct drm_device *dev = crtc->dev;
6845 drm_i915_private_t *dev_priv = dev->dev_private;
6846 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6847
6848 if (HAS_PCH_SPLIT(dev))
6849 return;
6850
6851 if (!dev_priv->lvds_downclock_avail)
6852 return;
6853
6854 /*
6855 * Since this is called by a timer, we should never get here in
6856 * the manual case.
6857 */
6858 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6859 int pipe = intel_crtc->pipe;
6860 int dpll_reg = DPLL(pipe);
6861 int dpll;
6862
6863 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6864
6865 assert_panel_unlocked(dev_priv, pipe);
6866
6867 dpll = I915_READ(dpll_reg);
6868 dpll |= DISPLAY_RATE_SELECT_FPA1;
6869 I915_WRITE(dpll_reg, dpll);
6870 intel_wait_for_vblank(dev, pipe);
6871 dpll = I915_READ(dpll_reg);
6872 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6873 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6874 }
6875
6876 }
6877
6878 void intel_mark_busy(struct drm_device *dev)
6879 {
6880 i915_update_gfx_val(dev->dev_private);
6881 }
6882
6883 void intel_mark_idle(struct drm_device *dev)
6884 {
6885 struct drm_crtc *crtc;
6886
6887 if (!i915_powersave)
6888 return;
6889
6890 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6891 if (!crtc->fb)
6892 continue;
6893
6894 intel_decrease_pllclock(crtc);
6895 }
6896 }
6897
6898 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6899 {
6900 struct drm_device *dev = obj->base.dev;
6901 struct drm_crtc *crtc;
6902
6903 if (!i915_powersave)
6904 return;
6905
6906 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6907 if (!crtc->fb)
6908 continue;
6909
6910 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6911 intel_increase_pllclock(crtc);
6912 }
6913 }
6914
6915 static void intel_crtc_destroy(struct drm_crtc *crtc)
6916 {
6917 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6918 struct drm_device *dev = crtc->dev;
6919 struct intel_unpin_work *work;
6920 unsigned long flags;
6921
6922 spin_lock_irqsave(&dev->event_lock, flags);
6923 work = intel_crtc->unpin_work;
6924 intel_crtc->unpin_work = NULL;
6925 spin_unlock_irqrestore(&dev->event_lock, flags);
6926
6927 if (work) {
6928 cancel_work_sync(&work->work);
6929 kfree(work);
6930 }
6931
6932 drm_crtc_cleanup(crtc);
6933
6934 kfree(intel_crtc);
6935 }
6936
6937 static void intel_unpin_work_fn(struct work_struct *__work)
6938 {
6939 struct intel_unpin_work *work =
6940 container_of(__work, struct intel_unpin_work, work);
6941 struct drm_device *dev = work->crtc->dev;
6942
6943 mutex_lock(&dev->struct_mutex);
6944 intel_unpin_fb_obj(work->old_fb_obj);
6945 drm_gem_object_unreference(&work->pending_flip_obj->base);
6946 drm_gem_object_unreference(&work->old_fb_obj->base);
6947
6948 intel_update_fbc(dev);
6949 mutex_unlock(&dev->struct_mutex);
6950
6951 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
6952 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
6953
6954 kfree(work);
6955 }
6956
6957 static void do_intel_finish_page_flip(struct drm_device *dev,
6958 struct drm_crtc *crtc)
6959 {
6960 drm_i915_private_t *dev_priv = dev->dev_private;
6961 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6962 struct intel_unpin_work *work;
6963 unsigned long flags;
6964
6965 /* Ignore early vblank irqs */
6966 if (intel_crtc == NULL)
6967 return;
6968
6969 spin_lock_irqsave(&dev->event_lock, flags);
6970 work = intel_crtc->unpin_work;
6971
6972 /* Ensure we don't miss a work->pending update ... */
6973 smp_rmb();
6974
6975 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6976 spin_unlock_irqrestore(&dev->event_lock, flags);
6977 return;
6978 }
6979
6980 /* and that the unpin work is consistent wrt ->pending. */
6981 smp_rmb();
6982
6983 intel_crtc->unpin_work = NULL;
6984
6985 if (work->event)
6986 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6987
6988 drm_vblank_put(dev, intel_crtc->pipe);
6989
6990 spin_unlock_irqrestore(&dev->event_lock, flags);
6991
6992 wake_up_all(&dev_priv->pending_flip_queue);
6993
6994 queue_work(dev_priv->wq, &work->work);
6995
6996 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6997 }
6998
6999 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7000 {
7001 drm_i915_private_t *dev_priv = dev->dev_private;
7002 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7003
7004 do_intel_finish_page_flip(dev, crtc);
7005 }
7006
7007 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7008 {
7009 drm_i915_private_t *dev_priv = dev->dev_private;
7010 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7011
7012 do_intel_finish_page_flip(dev, crtc);
7013 }
7014
7015 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7016 {
7017 drm_i915_private_t *dev_priv = dev->dev_private;
7018 struct intel_crtc *intel_crtc =
7019 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7020 unsigned long flags;
7021
7022 /* NB: An MMIO update of the plane base pointer will also
7023 * generate a page-flip completion irq, i.e. every modeset
7024 * is also accompanied by a spurious intel_prepare_page_flip().
7025 */
7026 spin_lock_irqsave(&dev->event_lock, flags);
7027 if (intel_crtc->unpin_work)
7028 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7029 spin_unlock_irqrestore(&dev->event_lock, flags);
7030 }
7031
7032 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7033 {
7034 /* Ensure that the work item is consistent when activating it ... */
7035 smp_wmb();
7036 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7037 /* and that it is marked active as soon as the irq could fire. */
7038 smp_wmb();
7039 }
7040
7041 static int intel_gen2_queue_flip(struct drm_device *dev,
7042 struct drm_crtc *crtc,
7043 struct drm_framebuffer *fb,
7044 struct drm_i915_gem_object *obj)
7045 {
7046 struct drm_i915_private *dev_priv = dev->dev_private;
7047 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7048 u32 flip_mask;
7049 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7050 int ret;
7051
7052 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7053 if (ret)
7054 goto err;
7055
7056 ret = intel_ring_begin(ring, 6);
7057 if (ret)
7058 goto err_unpin;
7059
7060 /* Can't queue multiple flips, so wait for the previous
7061 * one to finish before executing the next.
7062 */
7063 if (intel_crtc->plane)
7064 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7065 else
7066 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7067 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7068 intel_ring_emit(ring, MI_NOOP);
7069 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7070 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7071 intel_ring_emit(ring, fb->pitches[0]);
7072 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7073 intel_ring_emit(ring, 0); /* aux display base address, unused */
7074
7075 intel_mark_page_flip_active(intel_crtc);
7076 intel_ring_advance(ring);
7077 return 0;
7078
7079 err_unpin:
7080 intel_unpin_fb_obj(obj);
7081 err:
7082 return ret;
7083 }
7084
7085 static int intel_gen3_queue_flip(struct drm_device *dev,
7086 struct drm_crtc *crtc,
7087 struct drm_framebuffer *fb,
7088 struct drm_i915_gem_object *obj)
7089 {
7090 struct drm_i915_private *dev_priv = dev->dev_private;
7091 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7092 u32 flip_mask;
7093 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7094 int ret;
7095
7096 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7097 if (ret)
7098 goto err;
7099
7100 ret = intel_ring_begin(ring, 6);
7101 if (ret)
7102 goto err_unpin;
7103
7104 if (intel_crtc->plane)
7105 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7106 else
7107 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7108 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7109 intel_ring_emit(ring, MI_NOOP);
7110 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7111 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7112 intel_ring_emit(ring, fb->pitches[0]);
7113 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7114 intel_ring_emit(ring, MI_NOOP);
7115
7116 intel_mark_page_flip_active(intel_crtc);
7117 intel_ring_advance(ring);
7118 return 0;
7119
7120 err_unpin:
7121 intel_unpin_fb_obj(obj);
7122 err:
7123 return ret;
7124 }
7125
7126 static int intel_gen4_queue_flip(struct drm_device *dev,
7127 struct drm_crtc *crtc,
7128 struct drm_framebuffer *fb,
7129 struct drm_i915_gem_object *obj)
7130 {
7131 struct drm_i915_private *dev_priv = dev->dev_private;
7132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7133 uint32_t pf, pipesrc;
7134 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7135 int ret;
7136
7137 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7138 if (ret)
7139 goto err;
7140
7141 ret = intel_ring_begin(ring, 4);
7142 if (ret)
7143 goto err_unpin;
7144
7145 /* i965+ uses the linear or tiled offsets from the
7146 * Display Registers (which do not change across a page-flip)
7147 * so we need only reprogram the base address.
7148 */
7149 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7150 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7151 intel_ring_emit(ring, fb->pitches[0]);
7152 intel_ring_emit(ring,
7153 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7154 obj->tiling_mode);
7155
7156 /* XXX Enabling the panel-fitter across page-flip is so far
7157 * untested on non-native modes, so ignore it for now.
7158 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7159 */
7160 pf = 0;
7161 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7162 intel_ring_emit(ring, pf | pipesrc);
7163
7164 intel_mark_page_flip_active(intel_crtc);
7165 intel_ring_advance(ring);
7166 return 0;
7167
7168 err_unpin:
7169 intel_unpin_fb_obj(obj);
7170 err:
7171 return ret;
7172 }
7173
7174 static int intel_gen6_queue_flip(struct drm_device *dev,
7175 struct drm_crtc *crtc,
7176 struct drm_framebuffer *fb,
7177 struct drm_i915_gem_object *obj)
7178 {
7179 struct drm_i915_private *dev_priv = dev->dev_private;
7180 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7181 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7182 uint32_t pf, pipesrc;
7183 int ret;
7184
7185 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7186 if (ret)
7187 goto err;
7188
7189 ret = intel_ring_begin(ring, 4);
7190 if (ret)
7191 goto err_unpin;
7192
7193 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7194 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7195 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7196 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7197
7198 /* Contrary to the suggestions in the documentation,
7199 * "Enable Panel Fitter" does not seem to be required when page
7200 * flipping with a non-native mode, and worse causes a normal
7201 * modeset to fail.
7202 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7203 */
7204 pf = 0;
7205 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7206 intel_ring_emit(ring, pf | pipesrc);
7207
7208 intel_mark_page_flip_active(intel_crtc);
7209 intel_ring_advance(ring);
7210 return 0;
7211
7212 err_unpin:
7213 intel_unpin_fb_obj(obj);
7214 err:
7215 return ret;
7216 }
7217
7218 /*
7219 * On gen7 we currently use the blit ring because (in early silicon at least)
7220 * the render ring doesn't give us interrpts for page flip completion, which
7221 * means clients will hang after the first flip is queued. Fortunately the
7222 * blit ring generates interrupts properly, so use it instead.
7223 */
7224 static int intel_gen7_queue_flip(struct drm_device *dev,
7225 struct drm_crtc *crtc,
7226 struct drm_framebuffer *fb,
7227 struct drm_i915_gem_object *obj)
7228 {
7229 struct drm_i915_private *dev_priv = dev->dev_private;
7230 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7231 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7232 uint32_t plane_bit = 0;
7233 int ret;
7234
7235 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7236 if (ret)
7237 goto err;
7238
7239 switch(intel_crtc->plane) {
7240 case PLANE_A:
7241 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7242 break;
7243 case PLANE_B:
7244 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7245 break;
7246 case PLANE_C:
7247 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7248 break;
7249 default:
7250 WARN_ONCE(1, "unknown plane in flip command\n");
7251 ret = -ENODEV;
7252 goto err_unpin;
7253 }
7254
7255 ret = intel_ring_begin(ring, 4);
7256 if (ret)
7257 goto err_unpin;
7258
7259 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7260 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7261 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7262 intel_ring_emit(ring, (MI_NOOP));
7263
7264 intel_mark_page_flip_active(intel_crtc);
7265 intel_ring_advance(ring);
7266 return 0;
7267
7268 err_unpin:
7269 intel_unpin_fb_obj(obj);
7270 err:
7271 return ret;
7272 }
7273
7274 static int intel_default_queue_flip(struct drm_device *dev,
7275 struct drm_crtc *crtc,
7276 struct drm_framebuffer *fb,
7277 struct drm_i915_gem_object *obj)
7278 {
7279 return -ENODEV;
7280 }
7281
7282 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7283 struct drm_framebuffer *fb,
7284 struct drm_pending_vblank_event *event)
7285 {
7286 struct drm_device *dev = crtc->dev;
7287 struct drm_i915_private *dev_priv = dev->dev_private;
7288 struct intel_framebuffer *intel_fb;
7289 struct drm_i915_gem_object *obj;
7290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7291 struct intel_unpin_work *work;
7292 unsigned long flags;
7293 int ret;
7294
7295 /* Can't change pixel format via MI display flips. */
7296 if (fb->pixel_format != crtc->fb->pixel_format)
7297 return -EINVAL;
7298
7299 /*
7300 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7301 * Note that pitch changes could also affect these register.
7302 */
7303 if (INTEL_INFO(dev)->gen > 3 &&
7304 (fb->offsets[0] != crtc->fb->offsets[0] ||
7305 fb->pitches[0] != crtc->fb->pitches[0]))
7306 return -EINVAL;
7307
7308 work = kzalloc(sizeof *work, GFP_KERNEL);
7309 if (work == NULL)
7310 return -ENOMEM;
7311
7312 work->event = event;
7313 work->crtc = crtc;
7314 intel_fb = to_intel_framebuffer(crtc->fb);
7315 work->old_fb_obj = intel_fb->obj;
7316 INIT_WORK(&work->work, intel_unpin_work_fn);
7317
7318 ret = drm_vblank_get(dev, intel_crtc->pipe);
7319 if (ret)
7320 goto free_work;
7321
7322 /* We borrow the event spin lock for protecting unpin_work */
7323 spin_lock_irqsave(&dev->event_lock, flags);
7324 if (intel_crtc->unpin_work) {
7325 spin_unlock_irqrestore(&dev->event_lock, flags);
7326 kfree(work);
7327 drm_vblank_put(dev, intel_crtc->pipe);
7328
7329 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7330 return -EBUSY;
7331 }
7332 intel_crtc->unpin_work = work;
7333 spin_unlock_irqrestore(&dev->event_lock, flags);
7334
7335 intel_fb = to_intel_framebuffer(fb);
7336 obj = intel_fb->obj;
7337
7338 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7339 flush_workqueue(dev_priv->wq);
7340
7341 ret = i915_mutex_lock_interruptible(dev);
7342 if (ret)
7343 goto cleanup;
7344
7345 /* Reference the objects for the scheduled work. */
7346 drm_gem_object_reference(&work->old_fb_obj->base);
7347 drm_gem_object_reference(&obj->base);
7348
7349 crtc->fb = fb;
7350
7351 work->pending_flip_obj = obj;
7352
7353 work->enable_stall_check = true;
7354
7355 atomic_inc(&intel_crtc->unpin_work_count);
7356 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7357
7358 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7359 if (ret)
7360 goto cleanup_pending;
7361
7362 intel_disable_fbc(dev);
7363 intel_mark_fb_busy(obj);
7364 mutex_unlock(&dev->struct_mutex);
7365
7366 trace_i915_flip_request(intel_crtc->plane, obj);
7367
7368 return 0;
7369
7370 cleanup_pending:
7371 atomic_dec(&intel_crtc->unpin_work_count);
7372 drm_gem_object_unreference(&work->old_fb_obj->base);
7373 drm_gem_object_unreference(&obj->base);
7374 mutex_unlock(&dev->struct_mutex);
7375
7376 cleanup:
7377 spin_lock_irqsave(&dev->event_lock, flags);
7378 intel_crtc->unpin_work = NULL;
7379 spin_unlock_irqrestore(&dev->event_lock, flags);
7380
7381 drm_vblank_put(dev, intel_crtc->pipe);
7382 free_work:
7383 kfree(work);
7384
7385 return ret;
7386 }
7387
7388 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7389 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7390 .load_lut = intel_crtc_load_lut,
7391 .disable = intel_crtc_noop,
7392 };
7393
7394 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7395 {
7396 struct intel_encoder *other_encoder;
7397 struct drm_crtc *crtc = &encoder->new_crtc->base;
7398
7399 if (WARN_ON(!crtc))
7400 return false;
7401
7402 list_for_each_entry(other_encoder,
7403 &crtc->dev->mode_config.encoder_list,
7404 base.head) {
7405
7406 if (&other_encoder->new_crtc->base != crtc ||
7407 encoder == other_encoder)
7408 continue;
7409 else
7410 return true;
7411 }
7412
7413 return false;
7414 }
7415
7416 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7417 struct drm_crtc *crtc)
7418 {
7419 struct drm_device *dev;
7420 struct drm_crtc *tmp;
7421 int crtc_mask = 1;
7422
7423 WARN(!crtc, "checking null crtc?\n");
7424
7425 dev = crtc->dev;
7426
7427 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7428 if (tmp == crtc)
7429 break;
7430 crtc_mask <<= 1;
7431 }
7432
7433 if (encoder->possible_crtcs & crtc_mask)
7434 return true;
7435 return false;
7436 }
7437
7438 /**
7439 * intel_modeset_update_staged_output_state
7440 *
7441 * Updates the staged output configuration state, e.g. after we've read out the
7442 * current hw state.
7443 */
7444 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7445 {
7446 struct intel_encoder *encoder;
7447 struct intel_connector *connector;
7448
7449 list_for_each_entry(connector, &dev->mode_config.connector_list,
7450 base.head) {
7451 connector->new_encoder =
7452 to_intel_encoder(connector->base.encoder);
7453 }
7454
7455 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7456 base.head) {
7457 encoder->new_crtc =
7458 to_intel_crtc(encoder->base.crtc);
7459 }
7460 }
7461
7462 /**
7463 * intel_modeset_commit_output_state
7464 *
7465 * This function copies the stage display pipe configuration to the real one.
7466 */
7467 static void intel_modeset_commit_output_state(struct drm_device *dev)
7468 {
7469 struct intel_encoder *encoder;
7470 struct intel_connector *connector;
7471
7472 list_for_each_entry(connector, &dev->mode_config.connector_list,
7473 base.head) {
7474 connector->base.encoder = &connector->new_encoder->base;
7475 }
7476
7477 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7478 base.head) {
7479 encoder->base.crtc = &encoder->new_crtc->base;
7480 }
7481 }
7482
7483 static struct drm_display_mode *
7484 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7485 struct drm_display_mode *mode)
7486 {
7487 struct drm_device *dev = crtc->dev;
7488 struct drm_display_mode *adjusted_mode;
7489 struct drm_encoder_helper_funcs *encoder_funcs;
7490 struct intel_encoder *encoder;
7491
7492 adjusted_mode = drm_mode_duplicate(dev, mode);
7493 if (!adjusted_mode)
7494 return ERR_PTR(-ENOMEM);
7495
7496 /* Pass our mode to the connectors and the CRTC to give them a chance to
7497 * adjust it according to limitations or connector properties, and also
7498 * a chance to reject the mode entirely.
7499 */
7500 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7501 base.head) {
7502
7503 if (&encoder->new_crtc->base != crtc)
7504 continue;
7505 encoder_funcs = encoder->base.helper_private;
7506 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7507 adjusted_mode))) {
7508 DRM_DEBUG_KMS("Encoder fixup failed\n");
7509 goto fail;
7510 }
7511 }
7512
7513 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7514 DRM_DEBUG_KMS("CRTC fixup failed\n");
7515 goto fail;
7516 }
7517 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7518
7519 return adjusted_mode;
7520 fail:
7521 drm_mode_destroy(dev, adjusted_mode);
7522 return ERR_PTR(-EINVAL);
7523 }
7524
7525 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7526 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7527 static void
7528 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7529 unsigned *prepare_pipes, unsigned *disable_pipes)
7530 {
7531 struct intel_crtc *intel_crtc;
7532 struct drm_device *dev = crtc->dev;
7533 struct intel_encoder *encoder;
7534 struct intel_connector *connector;
7535 struct drm_crtc *tmp_crtc;
7536
7537 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7538
7539 /* Check which crtcs have changed outputs connected to them, these need
7540 * to be part of the prepare_pipes mask. We don't (yet) support global
7541 * modeset across multiple crtcs, so modeset_pipes will only have one
7542 * bit set at most. */
7543 list_for_each_entry(connector, &dev->mode_config.connector_list,
7544 base.head) {
7545 if (connector->base.encoder == &connector->new_encoder->base)
7546 continue;
7547
7548 if (connector->base.encoder) {
7549 tmp_crtc = connector->base.encoder->crtc;
7550
7551 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7552 }
7553
7554 if (connector->new_encoder)
7555 *prepare_pipes |=
7556 1 << connector->new_encoder->new_crtc->pipe;
7557 }
7558
7559 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7560 base.head) {
7561 if (encoder->base.crtc == &encoder->new_crtc->base)
7562 continue;
7563
7564 if (encoder->base.crtc) {
7565 tmp_crtc = encoder->base.crtc;
7566
7567 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7568 }
7569
7570 if (encoder->new_crtc)
7571 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7572 }
7573
7574 /* Check for any pipes that will be fully disabled ... */
7575 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7576 base.head) {
7577 bool used = false;
7578
7579 /* Don't try to disable disabled crtcs. */
7580 if (!intel_crtc->base.enabled)
7581 continue;
7582
7583 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7584 base.head) {
7585 if (encoder->new_crtc == intel_crtc)
7586 used = true;
7587 }
7588
7589 if (!used)
7590 *disable_pipes |= 1 << intel_crtc->pipe;
7591 }
7592
7593
7594 /* set_mode is also used to update properties on life display pipes. */
7595 intel_crtc = to_intel_crtc(crtc);
7596 if (crtc->enabled)
7597 *prepare_pipes |= 1 << intel_crtc->pipe;
7598
7599 /* We only support modeset on one single crtc, hence we need to do that
7600 * only for the passed in crtc iff we change anything else than just
7601 * disable crtcs.
7602 *
7603 * This is actually not true, to be fully compatible with the old crtc
7604 * helper we automatically disable _any_ output (i.e. doesn't need to be
7605 * connected to the crtc we're modesetting on) if it's disconnected.
7606 * Which is a rather nutty api (since changed the output configuration
7607 * without userspace's explicit request can lead to confusion), but
7608 * alas. Hence we currently need to modeset on all pipes we prepare. */
7609 if (*prepare_pipes)
7610 *modeset_pipes = *prepare_pipes;
7611
7612 /* ... and mask these out. */
7613 *modeset_pipes &= ~(*disable_pipes);
7614 *prepare_pipes &= ~(*disable_pipes);
7615 }
7616
7617 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7618 {
7619 struct drm_encoder *encoder;
7620 struct drm_device *dev = crtc->dev;
7621
7622 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7623 if (encoder->crtc == crtc)
7624 return true;
7625
7626 return false;
7627 }
7628
7629 static void
7630 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7631 {
7632 struct intel_encoder *intel_encoder;
7633 struct intel_crtc *intel_crtc;
7634 struct drm_connector *connector;
7635
7636 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7637 base.head) {
7638 if (!intel_encoder->base.crtc)
7639 continue;
7640
7641 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7642
7643 if (prepare_pipes & (1 << intel_crtc->pipe))
7644 intel_encoder->connectors_active = false;
7645 }
7646
7647 intel_modeset_commit_output_state(dev);
7648
7649 /* Update computed state. */
7650 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7651 base.head) {
7652 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7653 }
7654
7655 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7656 if (!connector->encoder || !connector->encoder->crtc)
7657 continue;
7658
7659 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7660
7661 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7662 struct drm_property *dpms_property =
7663 dev->mode_config.dpms_property;
7664
7665 connector->dpms = DRM_MODE_DPMS_ON;
7666 drm_object_property_set_value(&connector->base,
7667 dpms_property,
7668 DRM_MODE_DPMS_ON);
7669
7670 intel_encoder = to_intel_encoder(connector->encoder);
7671 intel_encoder->connectors_active = true;
7672 }
7673 }
7674
7675 }
7676
7677 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7678 list_for_each_entry((intel_crtc), \
7679 &(dev)->mode_config.crtc_list, \
7680 base.head) \
7681 if (mask & (1 <<(intel_crtc)->pipe)) \
7682
7683 void
7684 intel_modeset_check_state(struct drm_device *dev)
7685 {
7686 struct intel_crtc *crtc;
7687 struct intel_encoder *encoder;
7688 struct intel_connector *connector;
7689
7690 list_for_each_entry(connector, &dev->mode_config.connector_list,
7691 base.head) {
7692 /* This also checks the encoder/connector hw state with the
7693 * ->get_hw_state callbacks. */
7694 intel_connector_check_state(connector);
7695
7696 WARN(&connector->new_encoder->base != connector->base.encoder,
7697 "connector's staged encoder doesn't match current encoder\n");
7698 }
7699
7700 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7701 base.head) {
7702 bool enabled = false;
7703 bool active = false;
7704 enum pipe pipe, tracked_pipe;
7705
7706 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7707 encoder->base.base.id,
7708 drm_get_encoder_name(&encoder->base));
7709
7710 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7711 "encoder's stage crtc doesn't match current crtc\n");
7712 WARN(encoder->connectors_active && !encoder->base.crtc,
7713 "encoder's active_connectors set, but no crtc\n");
7714
7715 list_for_each_entry(connector, &dev->mode_config.connector_list,
7716 base.head) {
7717 if (connector->base.encoder != &encoder->base)
7718 continue;
7719 enabled = true;
7720 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7721 active = true;
7722 }
7723 WARN(!!encoder->base.crtc != enabled,
7724 "encoder's enabled state mismatch "
7725 "(expected %i, found %i)\n",
7726 !!encoder->base.crtc, enabled);
7727 WARN(active && !encoder->base.crtc,
7728 "active encoder with no crtc\n");
7729
7730 WARN(encoder->connectors_active != active,
7731 "encoder's computed active state doesn't match tracked active state "
7732 "(expected %i, found %i)\n", active, encoder->connectors_active);
7733
7734 active = encoder->get_hw_state(encoder, &pipe);
7735 WARN(active != encoder->connectors_active,
7736 "encoder's hw state doesn't match sw tracking "
7737 "(expected %i, found %i)\n",
7738 encoder->connectors_active, active);
7739
7740 if (!encoder->base.crtc)
7741 continue;
7742
7743 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7744 WARN(active && pipe != tracked_pipe,
7745 "active encoder's pipe doesn't match"
7746 "(expected %i, found %i)\n",
7747 tracked_pipe, pipe);
7748
7749 }
7750
7751 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7752 base.head) {
7753 bool enabled = false;
7754 bool active = false;
7755
7756 DRM_DEBUG_KMS("[CRTC:%d]\n",
7757 crtc->base.base.id);
7758
7759 WARN(crtc->active && !crtc->base.enabled,
7760 "active crtc, but not enabled in sw tracking\n");
7761
7762 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7763 base.head) {
7764 if (encoder->base.crtc != &crtc->base)
7765 continue;
7766 enabled = true;
7767 if (encoder->connectors_active)
7768 active = true;
7769 }
7770 WARN(active != crtc->active,
7771 "crtc's computed active state doesn't match tracked active state "
7772 "(expected %i, found %i)\n", active, crtc->active);
7773 WARN(enabled != crtc->base.enabled,
7774 "crtc's computed enabled state doesn't match tracked enabled state "
7775 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7776
7777 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7778 }
7779 }
7780
7781 int intel_set_mode(struct drm_crtc *crtc,
7782 struct drm_display_mode *mode,
7783 int x, int y, struct drm_framebuffer *fb)
7784 {
7785 struct drm_device *dev = crtc->dev;
7786 drm_i915_private_t *dev_priv = dev->dev_private;
7787 struct drm_display_mode *adjusted_mode, *saved_mode, *saved_hwmode;
7788 struct intel_crtc *intel_crtc;
7789 unsigned disable_pipes, prepare_pipes, modeset_pipes;
7790 int ret = 0;
7791
7792 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
7793 if (!saved_mode)
7794 return -ENOMEM;
7795 saved_hwmode = saved_mode + 1;
7796
7797 intel_modeset_affected_pipes(crtc, &modeset_pipes,
7798 &prepare_pipes, &disable_pipes);
7799
7800 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7801 modeset_pipes, prepare_pipes, disable_pipes);
7802
7803 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7804 intel_crtc_disable(&intel_crtc->base);
7805
7806 *saved_hwmode = crtc->hwmode;
7807 *saved_mode = crtc->mode;
7808
7809 /* Hack: Because we don't (yet) support global modeset on multiple
7810 * crtcs, we don't keep track of the new mode for more than one crtc.
7811 * Hence simply check whether any bit is set in modeset_pipes in all the
7812 * pieces of code that are not yet converted to deal with mutliple crtcs
7813 * changing their mode at the same time. */
7814 adjusted_mode = NULL;
7815 if (modeset_pipes) {
7816 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7817 if (IS_ERR(adjusted_mode)) {
7818 ret = PTR_ERR(adjusted_mode);
7819 goto out;
7820 }
7821 }
7822
7823 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7824 if (intel_crtc->base.enabled)
7825 dev_priv->display.crtc_disable(&intel_crtc->base);
7826 }
7827
7828 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7829 * to set it here already despite that we pass it down the callchain.
7830 */
7831 if (modeset_pipes)
7832 crtc->mode = *mode;
7833
7834 /* Only after disabling all output pipelines that will be changed can we
7835 * update the the output configuration. */
7836 intel_modeset_update_state(dev, prepare_pipes);
7837
7838 if (dev_priv->display.modeset_global_resources)
7839 dev_priv->display.modeset_global_resources(dev);
7840
7841 /* Set up the DPLL and any encoders state that needs to adjust or depend
7842 * on the DPLL.
7843 */
7844 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7845 ret = intel_crtc_mode_set(&intel_crtc->base,
7846 mode, adjusted_mode,
7847 x, y, fb);
7848 if (ret)
7849 goto done;
7850 }
7851
7852 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7853 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7854 dev_priv->display.crtc_enable(&intel_crtc->base);
7855
7856 if (modeset_pipes) {
7857 /* Store real post-adjustment hardware mode. */
7858 crtc->hwmode = *adjusted_mode;
7859
7860 /* Calculate and store various constants which
7861 * are later needed by vblank and swap-completion
7862 * timestamping. They are derived from true hwmode.
7863 */
7864 drm_calc_timestamping_constants(crtc);
7865 }
7866
7867 /* FIXME: add subpixel order */
7868 done:
7869 drm_mode_destroy(dev, adjusted_mode);
7870 if (ret && crtc->enabled) {
7871 crtc->hwmode = *saved_hwmode;
7872 crtc->mode = *saved_mode;
7873 } else {
7874 intel_modeset_check_state(dev);
7875 }
7876
7877 out:
7878 kfree(saved_mode);
7879 return ret;
7880 }
7881
7882 void intel_crtc_restore_mode(struct drm_crtc *crtc)
7883 {
7884 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
7885 }
7886
7887 #undef for_each_intel_crtc_masked
7888
7889 static void intel_set_config_free(struct intel_set_config *config)
7890 {
7891 if (!config)
7892 return;
7893
7894 kfree(config->save_connector_encoders);
7895 kfree(config->save_encoder_crtcs);
7896 kfree(config);
7897 }
7898
7899 static int intel_set_config_save_state(struct drm_device *dev,
7900 struct intel_set_config *config)
7901 {
7902 struct drm_encoder *encoder;
7903 struct drm_connector *connector;
7904 int count;
7905
7906 config->save_encoder_crtcs =
7907 kcalloc(dev->mode_config.num_encoder,
7908 sizeof(struct drm_crtc *), GFP_KERNEL);
7909 if (!config->save_encoder_crtcs)
7910 return -ENOMEM;
7911
7912 config->save_connector_encoders =
7913 kcalloc(dev->mode_config.num_connector,
7914 sizeof(struct drm_encoder *), GFP_KERNEL);
7915 if (!config->save_connector_encoders)
7916 return -ENOMEM;
7917
7918 /* Copy data. Note that driver private data is not affected.
7919 * Should anything bad happen only the expected state is
7920 * restored, not the drivers personal bookkeeping.
7921 */
7922 count = 0;
7923 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7924 config->save_encoder_crtcs[count++] = encoder->crtc;
7925 }
7926
7927 count = 0;
7928 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7929 config->save_connector_encoders[count++] = connector->encoder;
7930 }
7931
7932 return 0;
7933 }
7934
7935 static void intel_set_config_restore_state(struct drm_device *dev,
7936 struct intel_set_config *config)
7937 {
7938 struct intel_encoder *encoder;
7939 struct intel_connector *connector;
7940 int count;
7941
7942 count = 0;
7943 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7944 encoder->new_crtc =
7945 to_intel_crtc(config->save_encoder_crtcs[count++]);
7946 }
7947
7948 count = 0;
7949 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7950 connector->new_encoder =
7951 to_intel_encoder(config->save_connector_encoders[count++]);
7952 }
7953 }
7954
7955 static void
7956 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7957 struct intel_set_config *config)
7958 {
7959
7960 /* We should be able to check here if the fb has the same properties
7961 * and then just flip_or_move it */
7962 if (set->crtc->fb != set->fb) {
7963 /* If we have no fb then treat it as a full mode set */
7964 if (set->crtc->fb == NULL) {
7965 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7966 config->mode_changed = true;
7967 } else if (set->fb == NULL) {
7968 config->mode_changed = true;
7969 } else if (set->fb->depth != set->crtc->fb->depth) {
7970 config->mode_changed = true;
7971 } else if (set->fb->bits_per_pixel !=
7972 set->crtc->fb->bits_per_pixel) {
7973 config->mode_changed = true;
7974 } else
7975 config->fb_changed = true;
7976 }
7977
7978 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7979 config->fb_changed = true;
7980
7981 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7982 DRM_DEBUG_KMS("modes are different, full mode set\n");
7983 drm_mode_debug_printmodeline(&set->crtc->mode);
7984 drm_mode_debug_printmodeline(set->mode);
7985 config->mode_changed = true;
7986 }
7987 }
7988
7989 static int
7990 intel_modeset_stage_output_state(struct drm_device *dev,
7991 struct drm_mode_set *set,
7992 struct intel_set_config *config)
7993 {
7994 struct drm_crtc *new_crtc;
7995 struct intel_connector *connector;
7996 struct intel_encoder *encoder;
7997 int count, ro;
7998
7999 /* The upper layers ensure that we either disable a crtc or have a list
8000 * of connectors. For paranoia, double-check this. */
8001 WARN_ON(!set->fb && (set->num_connectors != 0));
8002 WARN_ON(set->fb && (set->num_connectors == 0));
8003
8004 count = 0;
8005 list_for_each_entry(connector, &dev->mode_config.connector_list,
8006 base.head) {
8007 /* Otherwise traverse passed in connector list and get encoders
8008 * for them. */
8009 for (ro = 0; ro < set->num_connectors; ro++) {
8010 if (set->connectors[ro] == &connector->base) {
8011 connector->new_encoder = connector->encoder;
8012 break;
8013 }
8014 }
8015
8016 /* If we disable the crtc, disable all its connectors. Also, if
8017 * the connector is on the changing crtc but not on the new
8018 * connector list, disable it. */
8019 if ((!set->fb || ro == set->num_connectors) &&
8020 connector->base.encoder &&
8021 connector->base.encoder->crtc == set->crtc) {
8022 connector->new_encoder = NULL;
8023
8024 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8025 connector->base.base.id,
8026 drm_get_connector_name(&connector->base));
8027 }
8028
8029
8030 if (&connector->new_encoder->base != connector->base.encoder) {
8031 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8032 config->mode_changed = true;
8033 }
8034 }
8035 /* connector->new_encoder is now updated for all connectors. */
8036
8037 /* Update crtc of enabled connectors. */
8038 count = 0;
8039 list_for_each_entry(connector, &dev->mode_config.connector_list,
8040 base.head) {
8041 if (!connector->new_encoder)
8042 continue;
8043
8044 new_crtc = connector->new_encoder->base.crtc;
8045
8046 for (ro = 0; ro < set->num_connectors; ro++) {
8047 if (set->connectors[ro] == &connector->base)
8048 new_crtc = set->crtc;
8049 }
8050
8051 /* Make sure the new CRTC will work with the encoder */
8052 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8053 new_crtc)) {
8054 return -EINVAL;
8055 }
8056 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8057
8058 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8059 connector->base.base.id,
8060 drm_get_connector_name(&connector->base),
8061 new_crtc->base.id);
8062 }
8063
8064 /* Check for any encoders that needs to be disabled. */
8065 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8066 base.head) {
8067 list_for_each_entry(connector,
8068 &dev->mode_config.connector_list,
8069 base.head) {
8070 if (connector->new_encoder == encoder) {
8071 WARN_ON(!connector->new_encoder->new_crtc);
8072
8073 goto next_encoder;
8074 }
8075 }
8076 encoder->new_crtc = NULL;
8077 next_encoder:
8078 /* Only now check for crtc changes so we don't miss encoders
8079 * that will be disabled. */
8080 if (&encoder->new_crtc->base != encoder->base.crtc) {
8081 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8082 config->mode_changed = true;
8083 }
8084 }
8085 /* Now we've also updated encoder->new_crtc for all encoders. */
8086
8087 return 0;
8088 }
8089
8090 static int intel_crtc_set_config(struct drm_mode_set *set)
8091 {
8092 struct drm_device *dev;
8093 struct drm_mode_set save_set;
8094 struct intel_set_config *config;
8095 int ret;
8096
8097 BUG_ON(!set);
8098 BUG_ON(!set->crtc);
8099 BUG_ON(!set->crtc->helper_private);
8100
8101 if (!set->mode)
8102 set->fb = NULL;
8103
8104 /* The fb helper likes to play gross jokes with ->mode_set_config.
8105 * Unfortunately the crtc helper doesn't do much at all for this case,
8106 * so we have to cope with this madness until the fb helper is fixed up. */
8107 if (set->fb && set->num_connectors == 0)
8108 return 0;
8109
8110 if (set->fb) {
8111 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8112 set->crtc->base.id, set->fb->base.id,
8113 (int)set->num_connectors, set->x, set->y);
8114 } else {
8115 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8116 }
8117
8118 dev = set->crtc->dev;
8119
8120 ret = -ENOMEM;
8121 config = kzalloc(sizeof(*config), GFP_KERNEL);
8122 if (!config)
8123 goto out_config;
8124
8125 ret = intel_set_config_save_state(dev, config);
8126 if (ret)
8127 goto out_config;
8128
8129 save_set.crtc = set->crtc;
8130 save_set.mode = &set->crtc->mode;
8131 save_set.x = set->crtc->x;
8132 save_set.y = set->crtc->y;
8133 save_set.fb = set->crtc->fb;
8134
8135 /* Compute whether we need a full modeset, only an fb base update or no
8136 * change at all. In the future we might also check whether only the
8137 * mode changed, e.g. for LVDS where we only change the panel fitter in
8138 * such cases. */
8139 intel_set_config_compute_mode_changes(set, config);
8140
8141 ret = intel_modeset_stage_output_state(dev, set, config);
8142 if (ret)
8143 goto fail;
8144
8145 if (config->mode_changed) {
8146 if (set->mode) {
8147 DRM_DEBUG_KMS("attempting to set mode from"
8148 " userspace\n");
8149 drm_mode_debug_printmodeline(set->mode);
8150 }
8151
8152 ret = intel_set_mode(set->crtc, set->mode,
8153 set->x, set->y, set->fb);
8154 if (ret) {
8155 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8156 set->crtc->base.id, ret);
8157 goto fail;
8158 }
8159 } else if (config->fb_changed) {
8160 intel_crtc_wait_for_pending_flips(set->crtc);
8161
8162 ret = intel_pipe_set_base(set->crtc,
8163 set->x, set->y, set->fb);
8164 }
8165
8166 intel_set_config_free(config);
8167
8168 return 0;
8169
8170 fail:
8171 intel_set_config_restore_state(dev, config);
8172
8173 /* Try to restore the config */
8174 if (config->mode_changed &&
8175 intel_set_mode(save_set.crtc, save_set.mode,
8176 save_set.x, save_set.y, save_set.fb))
8177 DRM_ERROR("failed to restore config after modeset failure\n");
8178
8179 out_config:
8180 intel_set_config_free(config);
8181 return ret;
8182 }
8183
8184 static const struct drm_crtc_funcs intel_crtc_funcs = {
8185 .cursor_set = intel_crtc_cursor_set,
8186 .cursor_move = intel_crtc_cursor_move,
8187 .gamma_set = intel_crtc_gamma_set,
8188 .set_config = intel_crtc_set_config,
8189 .destroy = intel_crtc_destroy,
8190 .page_flip = intel_crtc_page_flip,
8191 };
8192
8193 static void intel_cpu_pll_init(struct drm_device *dev)
8194 {
8195 if (HAS_DDI(dev))
8196 intel_ddi_pll_init(dev);
8197 }
8198
8199 static void intel_pch_pll_init(struct drm_device *dev)
8200 {
8201 drm_i915_private_t *dev_priv = dev->dev_private;
8202 int i;
8203
8204 if (dev_priv->num_pch_pll == 0) {
8205 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8206 return;
8207 }
8208
8209 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8210 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8211 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8212 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8213 }
8214 }
8215
8216 static void intel_crtc_init(struct drm_device *dev, int pipe)
8217 {
8218 drm_i915_private_t *dev_priv = dev->dev_private;
8219 struct intel_crtc *intel_crtc;
8220 int i;
8221
8222 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8223 if (intel_crtc == NULL)
8224 return;
8225
8226 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8227
8228 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8229 for (i = 0; i < 256; i++) {
8230 intel_crtc->lut_r[i] = i;
8231 intel_crtc->lut_g[i] = i;
8232 intel_crtc->lut_b[i] = i;
8233 }
8234
8235 /* Swap pipes & planes for FBC on pre-965 */
8236 intel_crtc->pipe = pipe;
8237 intel_crtc->plane = pipe;
8238 intel_crtc->cpu_transcoder = pipe;
8239 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8240 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8241 intel_crtc->plane = !pipe;
8242 }
8243
8244 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8245 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8246 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8247 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8248
8249 intel_crtc->bpp = 24; /* default for pre-Ironlake */
8250
8251 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8252 }
8253
8254 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8255 struct drm_file *file)
8256 {
8257 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8258 struct drm_mode_object *drmmode_obj;
8259 struct intel_crtc *crtc;
8260
8261 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8262 return -ENODEV;
8263
8264 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8265 DRM_MODE_OBJECT_CRTC);
8266
8267 if (!drmmode_obj) {
8268 DRM_ERROR("no such CRTC id\n");
8269 return -EINVAL;
8270 }
8271
8272 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8273 pipe_from_crtc_id->pipe = crtc->pipe;
8274
8275 return 0;
8276 }
8277
8278 static int intel_encoder_clones(struct intel_encoder *encoder)
8279 {
8280 struct drm_device *dev = encoder->base.dev;
8281 struct intel_encoder *source_encoder;
8282 int index_mask = 0;
8283 int entry = 0;
8284
8285 list_for_each_entry(source_encoder,
8286 &dev->mode_config.encoder_list, base.head) {
8287
8288 if (encoder == source_encoder)
8289 index_mask |= (1 << entry);
8290
8291 /* Intel hw has only one MUX where enocoders could be cloned. */
8292 if (encoder->cloneable && source_encoder->cloneable)
8293 index_mask |= (1 << entry);
8294
8295 entry++;
8296 }
8297
8298 return index_mask;
8299 }
8300
8301 static bool has_edp_a(struct drm_device *dev)
8302 {
8303 struct drm_i915_private *dev_priv = dev->dev_private;
8304
8305 if (!IS_MOBILE(dev))
8306 return false;
8307
8308 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8309 return false;
8310
8311 if (IS_GEN5(dev) &&
8312 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8313 return false;
8314
8315 return true;
8316 }
8317
8318 static void intel_setup_outputs(struct drm_device *dev)
8319 {
8320 struct drm_i915_private *dev_priv = dev->dev_private;
8321 struct intel_encoder *encoder;
8322 bool dpd_is_edp = false;
8323 bool has_lvds;
8324
8325 has_lvds = intel_lvds_init(dev);
8326 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8327 /* disable the panel fitter on everything but LVDS */
8328 I915_WRITE(PFIT_CONTROL, 0);
8329 }
8330
8331 if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
8332 intel_crt_init(dev);
8333
8334 if (HAS_DDI(dev)) {
8335 int found;
8336
8337 /* Haswell uses DDI functions to detect digital outputs */
8338 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8339 /* DDI A only supports eDP */
8340 if (found)
8341 intel_ddi_init(dev, PORT_A);
8342
8343 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8344 * register */
8345 found = I915_READ(SFUSE_STRAP);
8346
8347 if (found & SFUSE_STRAP_DDIB_DETECTED)
8348 intel_ddi_init(dev, PORT_B);
8349 if (found & SFUSE_STRAP_DDIC_DETECTED)
8350 intel_ddi_init(dev, PORT_C);
8351 if (found & SFUSE_STRAP_DDID_DETECTED)
8352 intel_ddi_init(dev, PORT_D);
8353 } else if (HAS_PCH_SPLIT(dev)) {
8354 int found;
8355 dpd_is_edp = intel_dpd_is_edp(dev);
8356
8357 if (has_edp_a(dev))
8358 intel_dp_init(dev, DP_A, PORT_A);
8359
8360 if (I915_READ(HDMIB) & PORT_DETECTED) {
8361 /* PCH SDVOB multiplex with HDMIB */
8362 found = intel_sdvo_init(dev, PCH_SDVOB, true);
8363 if (!found)
8364 intel_hdmi_init(dev, HDMIB, PORT_B);
8365 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8366 intel_dp_init(dev, PCH_DP_B, PORT_B);
8367 }
8368
8369 if (I915_READ(HDMIC) & PORT_DETECTED)
8370 intel_hdmi_init(dev, HDMIC, PORT_C);
8371
8372 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
8373 intel_hdmi_init(dev, HDMID, PORT_D);
8374
8375 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8376 intel_dp_init(dev, PCH_DP_C, PORT_C);
8377
8378 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8379 intel_dp_init(dev, PCH_DP_D, PORT_D);
8380 } else if (IS_VALLEYVIEW(dev)) {
8381 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8382 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8383 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
8384
8385 if (I915_READ(VLV_DISPLAY_BASE + SDVOB) & PORT_DETECTED) {
8386 intel_hdmi_init(dev, VLV_DISPLAY_BASE + SDVOB, PORT_B);
8387 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8388 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
8389 }
8390
8391 if (I915_READ(VLV_DISPLAY_BASE + SDVOC) & PORT_DETECTED)
8392 intel_hdmi_init(dev, VLV_DISPLAY_BASE + SDVOC, PORT_C);
8393
8394 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8395 bool found = false;
8396
8397 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8398 DRM_DEBUG_KMS("probing SDVOB\n");
8399 found = intel_sdvo_init(dev, SDVOB, true);
8400 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8401 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8402 intel_hdmi_init(dev, SDVOB, PORT_B);
8403 }
8404
8405 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8406 DRM_DEBUG_KMS("probing DP_B\n");
8407 intel_dp_init(dev, DP_B, PORT_B);
8408 }
8409 }
8410
8411 /* Before G4X SDVOC doesn't have its own detect register */
8412
8413 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8414 DRM_DEBUG_KMS("probing SDVOC\n");
8415 found = intel_sdvo_init(dev, SDVOC, false);
8416 }
8417
8418 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8419
8420 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8421 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8422 intel_hdmi_init(dev, SDVOC, PORT_C);
8423 }
8424 if (SUPPORTS_INTEGRATED_DP(dev)) {
8425 DRM_DEBUG_KMS("probing DP_C\n");
8426 intel_dp_init(dev, DP_C, PORT_C);
8427 }
8428 }
8429
8430 if (SUPPORTS_INTEGRATED_DP(dev) &&
8431 (I915_READ(DP_D) & DP_DETECTED)) {
8432 DRM_DEBUG_KMS("probing DP_D\n");
8433 intel_dp_init(dev, DP_D, PORT_D);
8434 }
8435 } else if (IS_GEN2(dev))
8436 intel_dvo_init(dev);
8437
8438 if (SUPPORTS_TV(dev))
8439 intel_tv_init(dev);
8440
8441 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8442 encoder->base.possible_crtcs = encoder->crtc_mask;
8443 encoder->base.possible_clones =
8444 intel_encoder_clones(encoder);
8445 }
8446
8447 intel_init_pch_refclk(dev);
8448
8449 drm_helper_move_panel_connectors_to_head(dev);
8450 }
8451
8452 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8453 {
8454 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8455
8456 drm_framebuffer_cleanup(fb);
8457 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8458
8459 kfree(intel_fb);
8460 }
8461
8462 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8463 struct drm_file *file,
8464 unsigned int *handle)
8465 {
8466 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8467 struct drm_i915_gem_object *obj = intel_fb->obj;
8468
8469 return drm_gem_handle_create(file, &obj->base, handle);
8470 }
8471
8472 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8473 .destroy = intel_user_framebuffer_destroy,
8474 .create_handle = intel_user_framebuffer_create_handle,
8475 };
8476
8477 int intel_framebuffer_init(struct drm_device *dev,
8478 struct intel_framebuffer *intel_fb,
8479 struct drm_mode_fb_cmd2 *mode_cmd,
8480 struct drm_i915_gem_object *obj)
8481 {
8482 int ret;
8483
8484 if (obj->tiling_mode == I915_TILING_Y) {
8485 DRM_DEBUG("hardware does not support tiling Y\n");
8486 return -EINVAL;
8487 }
8488
8489 if (mode_cmd->pitches[0] & 63) {
8490 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8491 mode_cmd->pitches[0]);
8492 return -EINVAL;
8493 }
8494
8495 /* FIXME <= Gen4 stride limits are bit unclear */
8496 if (mode_cmd->pitches[0] > 32768) {
8497 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8498 mode_cmd->pitches[0]);
8499 return -EINVAL;
8500 }
8501
8502 if (obj->tiling_mode != I915_TILING_NONE &&
8503 mode_cmd->pitches[0] != obj->stride) {
8504 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8505 mode_cmd->pitches[0], obj->stride);
8506 return -EINVAL;
8507 }
8508
8509 /* Reject formats not supported by any plane early. */
8510 switch (mode_cmd->pixel_format) {
8511 case DRM_FORMAT_C8:
8512 case DRM_FORMAT_RGB565:
8513 case DRM_FORMAT_XRGB8888:
8514 case DRM_FORMAT_ARGB8888:
8515 break;
8516 case DRM_FORMAT_XRGB1555:
8517 case DRM_FORMAT_ARGB1555:
8518 if (INTEL_INFO(dev)->gen > 3) {
8519 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8520 return -EINVAL;
8521 }
8522 break;
8523 case DRM_FORMAT_XBGR8888:
8524 case DRM_FORMAT_ABGR8888:
8525 case DRM_FORMAT_XRGB2101010:
8526 case DRM_FORMAT_ARGB2101010:
8527 case DRM_FORMAT_XBGR2101010:
8528 case DRM_FORMAT_ABGR2101010:
8529 if (INTEL_INFO(dev)->gen < 4) {
8530 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8531 return -EINVAL;
8532 }
8533 break;
8534 case DRM_FORMAT_YUYV:
8535 case DRM_FORMAT_UYVY:
8536 case DRM_FORMAT_YVYU:
8537 case DRM_FORMAT_VYUY:
8538 if (INTEL_INFO(dev)->gen < 5) {
8539 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8540 return -EINVAL;
8541 }
8542 break;
8543 default:
8544 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8545 return -EINVAL;
8546 }
8547
8548 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8549 if (mode_cmd->offsets[0] != 0)
8550 return -EINVAL;
8551
8552 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8553 intel_fb->obj = obj;
8554
8555 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8556 if (ret) {
8557 DRM_ERROR("framebuffer init failed %d\n", ret);
8558 return ret;
8559 }
8560
8561 return 0;
8562 }
8563
8564 static struct drm_framebuffer *
8565 intel_user_framebuffer_create(struct drm_device *dev,
8566 struct drm_file *filp,
8567 struct drm_mode_fb_cmd2 *mode_cmd)
8568 {
8569 struct drm_i915_gem_object *obj;
8570
8571 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8572 mode_cmd->handles[0]));
8573 if (&obj->base == NULL)
8574 return ERR_PTR(-ENOENT);
8575
8576 return intel_framebuffer_create(dev, mode_cmd, obj);
8577 }
8578
8579 static const struct drm_mode_config_funcs intel_mode_funcs = {
8580 .fb_create = intel_user_framebuffer_create,
8581 .output_poll_changed = intel_fb_output_poll_changed,
8582 };
8583
8584 /* Set up chip specific display functions */
8585 static void intel_init_display(struct drm_device *dev)
8586 {
8587 struct drm_i915_private *dev_priv = dev->dev_private;
8588
8589 /* We always want a DPMS function */
8590 if (HAS_DDI(dev)) {
8591 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8592 dev_priv->display.crtc_enable = haswell_crtc_enable;
8593 dev_priv->display.crtc_disable = haswell_crtc_disable;
8594 dev_priv->display.off = haswell_crtc_off;
8595 dev_priv->display.update_plane = ironlake_update_plane;
8596 } else if (HAS_PCH_SPLIT(dev)) {
8597 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8598 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8599 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8600 dev_priv->display.off = ironlake_crtc_off;
8601 dev_priv->display.update_plane = ironlake_update_plane;
8602 } else {
8603 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8604 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8605 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8606 dev_priv->display.off = i9xx_crtc_off;
8607 dev_priv->display.update_plane = i9xx_update_plane;
8608 }
8609
8610 /* Returns the core display clock speed */
8611 if (IS_VALLEYVIEW(dev))
8612 dev_priv->display.get_display_clock_speed =
8613 valleyview_get_display_clock_speed;
8614 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8615 dev_priv->display.get_display_clock_speed =
8616 i945_get_display_clock_speed;
8617 else if (IS_I915G(dev))
8618 dev_priv->display.get_display_clock_speed =
8619 i915_get_display_clock_speed;
8620 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8621 dev_priv->display.get_display_clock_speed =
8622 i9xx_misc_get_display_clock_speed;
8623 else if (IS_I915GM(dev))
8624 dev_priv->display.get_display_clock_speed =
8625 i915gm_get_display_clock_speed;
8626 else if (IS_I865G(dev))
8627 dev_priv->display.get_display_clock_speed =
8628 i865_get_display_clock_speed;
8629 else if (IS_I85X(dev))
8630 dev_priv->display.get_display_clock_speed =
8631 i855_get_display_clock_speed;
8632 else /* 852, 830 */
8633 dev_priv->display.get_display_clock_speed =
8634 i830_get_display_clock_speed;
8635
8636 if (HAS_PCH_SPLIT(dev)) {
8637 if (IS_GEN5(dev)) {
8638 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8639 dev_priv->display.write_eld = ironlake_write_eld;
8640 } else if (IS_GEN6(dev)) {
8641 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8642 dev_priv->display.write_eld = ironlake_write_eld;
8643 } else if (IS_IVYBRIDGE(dev)) {
8644 /* FIXME: detect B0+ stepping and use auto training */
8645 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8646 dev_priv->display.write_eld = ironlake_write_eld;
8647 dev_priv->display.modeset_global_resources =
8648 ivb_modeset_global_resources;
8649 } else if (IS_HASWELL(dev)) {
8650 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8651 dev_priv->display.write_eld = haswell_write_eld;
8652 dev_priv->display.modeset_global_resources =
8653 haswell_modeset_global_resources;
8654 }
8655 } else if (IS_G4X(dev)) {
8656 dev_priv->display.write_eld = g4x_write_eld;
8657 }
8658
8659 /* Default just returns -ENODEV to indicate unsupported */
8660 dev_priv->display.queue_flip = intel_default_queue_flip;
8661
8662 switch (INTEL_INFO(dev)->gen) {
8663 case 2:
8664 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8665 break;
8666
8667 case 3:
8668 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8669 break;
8670
8671 case 4:
8672 case 5:
8673 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8674 break;
8675
8676 case 6:
8677 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8678 break;
8679 case 7:
8680 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8681 break;
8682 }
8683 }
8684
8685 /*
8686 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8687 * resume, or other times. This quirk makes sure that's the case for
8688 * affected systems.
8689 */
8690 static void quirk_pipea_force(struct drm_device *dev)
8691 {
8692 struct drm_i915_private *dev_priv = dev->dev_private;
8693
8694 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8695 DRM_INFO("applying pipe a force quirk\n");
8696 }
8697
8698 /*
8699 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8700 */
8701 static void quirk_ssc_force_disable(struct drm_device *dev)
8702 {
8703 struct drm_i915_private *dev_priv = dev->dev_private;
8704 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8705 DRM_INFO("applying lvds SSC disable quirk\n");
8706 }
8707
8708 /*
8709 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8710 * brightness value
8711 */
8712 static void quirk_invert_brightness(struct drm_device *dev)
8713 {
8714 struct drm_i915_private *dev_priv = dev->dev_private;
8715 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8716 DRM_INFO("applying inverted panel brightness quirk\n");
8717 }
8718
8719 struct intel_quirk {
8720 int device;
8721 int subsystem_vendor;
8722 int subsystem_device;
8723 void (*hook)(struct drm_device *dev);
8724 };
8725
8726 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8727 struct intel_dmi_quirk {
8728 void (*hook)(struct drm_device *dev);
8729 const struct dmi_system_id (*dmi_id_list)[];
8730 };
8731
8732 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8733 {
8734 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8735 return 1;
8736 }
8737
8738 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8739 {
8740 .dmi_id_list = &(const struct dmi_system_id[]) {
8741 {
8742 .callback = intel_dmi_reverse_brightness,
8743 .ident = "NCR Corporation",
8744 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8745 DMI_MATCH(DMI_PRODUCT_NAME, ""),
8746 },
8747 },
8748 { } /* terminating entry */
8749 },
8750 .hook = quirk_invert_brightness,
8751 },
8752 };
8753
8754 static struct intel_quirk intel_quirks[] = {
8755 /* HP Mini needs pipe A force quirk (LP: #322104) */
8756 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8757
8758 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8759 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8760
8761 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8762 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8763
8764 /* 830/845 need to leave pipe A & dpll A up */
8765 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8766 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8767
8768 /* Lenovo U160 cannot use SSC on LVDS */
8769 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8770
8771 /* Sony Vaio Y cannot use SSC on LVDS */
8772 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8773
8774 /* Acer Aspire 5734Z must invert backlight brightness */
8775 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8776
8777 /* Acer/eMachines G725 */
8778 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
8779
8780 /* Acer/eMachines e725 */
8781 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
8782
8783 /* Acer/Packard Bell NCL20 */
8784 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
8785
8786 /* Acer Aspire 4736Z */
8787 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
8788 };
8789
8790 static void intel_init_quirks(struct drm_device *dev)
8791 {
8792 struct pci_dev *d = dev->pdev;
8793 int i;
8794
8795 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8796 struct intel_quirk *q = &intel_quirks[i];
8797
8798 if (d->device == q->device &&
8799 (d->subsystem_vendor == q->subsystem_vendor ||
8800 q->subsystem_vendor == PCI_ANY_ID) &&
8801 (d->subsystem_device == q->subsystem_device ||
8802 q->subsystem_device == PCI_ANY_ID))
8803 q->hook(dev);
8804 }
8805 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8806 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8807 intel_dmi_quirks[i].hook(dev);
8808 }
8809 }
8810
8811 /* Disable the VGA plane that we never use */
8812 static void i915_disable_vga(struct drm_device *dev)
8813 {
8814 struct drm_i915_private *dev_priv = dev->dev_private;
8815 u8 sr1;
8816 u32 vga_reg = i915_vgacntrl_reg(dev);
8817
8818 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8819 outb(SR01, VGA_SR_INDEX);
8820 sr1 = inb(VGA_SR_DATA);
8821 outb(sr1 | 1<<5, VGA_SR_DATA);
8822 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8823 udelay(300);
8824
8825 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8826 POSTING_READ(vga_reg);
8827 }
8828
8829 void intel_modeset_init_hw(struct drm_device *dev)
8830 {
8831 intel_init_power_well(dev);
8832
8833 intel_prepare_ddi(dev);
8834
8835 intel_init_clock_gating(dev);
8836
8837 mutex_lock(&dev->struct_mutex);
8838 intel_enable_gt_powersave(dev);
8839 mutex_unlock(&dev->struct_mutex);
8840 }
8841
8842 void intel_modeset_init(struct drm_device *dev)
8843 {
8844 struct drm_i915_private *dev_priv = dev->dev_private;
8845 int i, ret;
8846
8847 drm_mode_config_init(dev);
8848
8849 dev->mode_config.min_width = 0;
8850 dev->mode_config.min_height = 0;
8851
8852 dev->mode_config.preferred_depth = 24;
8853 dev->mode_config.prefer_shadow = 1;
8854
8855 dev->mode_config.funcs = &intel_mode_funcs;
8856
8857 intel_init_quirks(dev);
8858
8859 intel_init_pm(dev);
8860
8861 intel_init_display(dev);
8862
8863 if (IS_GEN2(dev)) {
8864 dev->mode_config.max_width = 2048;
8865 dev->mode_config.max_height = 2048;
8866 } else if (IS_GEN3(dev)) {
8867 dev->mode_config.max_width = 4096;
8868 dev->mode_config.max_height = 4096;
8869 } else {
8870 dev->mode_config.max_width = 8192;
8871 dev->mode_config.max_height = 8192;
8872 }
8873 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
8874
8875 DRM_DEBUG_KMS("%d display pipe%s available.\n",
8876 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8877
8878 for (i = 0; i < dev_priv->num_pipe; i++) {
8879 intel_crtc_init(dev, i);
8880 ret = intel_plane_init(dev, i);
8881 if (ret)
8882 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8883 }
8884
8885 intel_cpu_pll_init(dev);
8886 intel_pch_pll_init(dev);
8887
8888 /* Just disable it once at startup */
8889 i915_disable_vga(dev);
8890 intel_setup_outputs(dev);
8891
8892 /* Just in case the BIOS is doing something questionable. */
8893 intel_disable_fbc(dev);
8894 }
8895
8896 static void
8897 intel_connector_break_all_links(struct intel_connector *connector)
8898 {
8899 connector->base.dpms = DRM_MODE_DPMS_OFF;
8900 connector->base.encoder = NULL;
8901 connector->encoder->connectors_active = false;
8902 connector->encoder->base.crtc = NULL;
8903 }
8904
8905 static void intel_enable_pipe_a(struct drm_device *dev)
8906 {
8907 struct intel_connector *connector;
8908 struct drm_connector *crt = NULL;
8909 struct intel_load_detect_pipe load_detect_temp;
8910
8911 /* We can't just switch on the pipe A, we need to set things up with a
8912 * proper mode and output configuration. As a gross hack, enable pipe A
8913 * by enabling the load detect pipe once. */
8914 list_for_each_entry(connector,
8915 &dev->mode_config.connector_list,
8916 base.head) {
8917 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8918 crt = &connector->base;
8919 break;
8920 }
8921 }
8922
8923 if (!crt)
8924 return;
8925
8926 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8927 intel_release_load_detect_pipe(crt, &load_detect_temp);
8928
8929
8930 }
8931
8932 static bool
8933 intel_check_plane_mapping(struct intel_crtc *crtc)
8934 {
8935 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8936 u32 reg, val;
8937
8938 if (dev_priv->num_pipe == 1)
8939 return true;
8940
8941 reg = DSPCNTR(!crtc->plane);
8942 val = I915_READ(reg);
8943
8944 if ((val & DISPLAY_PLANE_ENABLE) &&
8945 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8946 return false;
8947
8948 return true;
8949 }
8950
8951 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8952 {
8953 struct drm_device *dev = crtc->base.dev;
8954 struct drm_i915_private *dev_priv = dev->dev_private;
8955 u32 reg;
8956
8957 /* Clear any frame start delays used for debugging left by the BIOS */
8958 reg = PIPECONF(crtc->cpu_transcoder);
8959 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8960
8961 /* We need to sanitize the plane -> pipe mapping first because this will
8962 * disable the crtc (and hence change the state) if it is wrong. Note
8963 * that gen4+ has a fixed plane -> pipe mapping. */
8964 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
8965 struct intel_connector *connector;
8966 bool plane;
8967
8968 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8969 crtc->base.base.id);
8970
8971 /* Pipe has the wrong plane attached and the plane is active.
8972 * Temporarily change the plane mapping and disable everything
8973 * ... */
8974 plane = crtc->plane;
8975 crtc->plane = !plane;
8976 dev_priv->display.crtc_disable(&crtc->base);
8977 crtc->plane = plane;
8978
8979 /* ... and break all links. */
8980 list_for_each_entry(connector, &dev->mode_config.connector_list,
8981 base.head) {
8982 if (connector->encoder->base.crtc != &crtc->base)
8983 continue;
8984
8985 intel_connector_break_all_links(connector);
8986 }
8987
8988 WARN_ON(crtc->active);
8989 crtc->base.enabled = false;
8990 }
8991
8992 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8993 crtc->pipe == PIPE_A && !crtc->active) {
8994 /* BIOS forgot to enable pipe A, this mostly happens after
8995 * resume. Force-enable the pipe to fix this, the update_dpms
8996 * call below we restore the pipe to the right state, but leave
8997 * the required bits on. */
8998 intel_enable_pipe_a(dev);
8999 }
9000
9001 /* Adjust the state of the output pipe according to whether we
9002 * have active connectors/encoders. */
9003 intel_crtc_update_dpms(&crtc->base);
9004
9005 if (crtc->active != crtc->base.enabled) {
9006 struct intel_encoder *encoder;
9007
9008 /* This can happen either due to bugs in the get_hw_state
9009 * functions or because the pipe is force-enabled due to the
9010 * pipe A quirk. */
9011 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9012 crtc->base.base.id,
9013 crtc->base.enabled ? "enabled" : "disabled",
9014 crtc->active ? "enabled" : "disabled");
9015
9016 crtc->base.enabled = crtc->active;
9017
9018 /* Because we only establish the connector -> encoder ->
9019 * crtc links if something is active, this means the
9020 * crtc is now deactivated. Break the links. connector
9021 * -> encoder links are only establish when things are
9022 * actually up, hence no need to break them. */
9023 WARN_ON(crtc->active);
9024
9025 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9026 WARN_ON(encoder->connectors_active);
9027 encoder->base.crtc = NULL;
9028 }
9029 }
9030 }
9031
9032 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9033 {
9034 struct intel_connector *connector;
9035 struct drm_device *dev = encoder->base.dev;
9036
9037 /* We need to check both for a crtc link (meaning that the
9038 * encoder is active and trying to read from a pipe) and the
9039 * pipe itself being active. */
9040 bool has_active_crtc = encoder->base.crtc &&
9041 to_intel_crtc(encoder->base.crtc)->active;
9042
9043 if (encoder->connectors_active && !has_active_crtc) {
9044 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9045 encoder->base.base.id,
9046 drm_get_encoder_name(&encoder->base));
9047
9048 /* Connector is active, but has no active pipe. This is
9049 * fallout from our resume register restoring. Disable
9050 * the encoder manually again. */
9051 if (encoder->base.crtc) {
9052 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9053 encoder->base.base.id,
9054 drm_get_encoder_name(&encoder->base));
9055 encoder->disable(encoder);
9056 }
9057
9058 /* Inconsistent output/port/pipe state happens presumably due to
9059 * a bug in one of the get_hw_state functions. Or someplace else
9060 * in our code, like the register restore mess on resume. Clamp
9061 * things to off as a safer default. */
9062 list_for_each_entry(connector,
9063 &dev->mode_config.connector_list,
9064 base.head) {
9065 if (connector->encoder != encoder)
9066 continue;
9067
9068 intel_connector_break_all_links(connector);
9069 }
9070 }
9071 /* Enabled encoders without active connectors will be fixed in
9072 * the crtc fixup. */
9073 }
9074
9075 void i915_redisable_vga(struct drm_device *dev)
9076 {
9077 struct drm_i915_private *dev_priv = dev->dev_private;
9078 u32 vga_reg = i915_vgacntrl_reg(dev);
9079
9080 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9081 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9082 i915_disable_vga(dev);
9083 }
9084 }
9085
9086 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9087 * and i915 state tracking structures. */
9088 void intel_modeset_setup_hw_state(struct drm_device *dev,
9089 bool force_restore)
9090 {
9091 struct drm_i915_private *dev_priv = dev->dev_private;
9092 enum pipe pipe;
9093 u32 tmp;
9094 struct intel_crtc *crtc;
9095 struct intel_encoder *encoder;
9096 struct intel_connector *connector;
9097
9098 if (HAS_DDI(dev)) {
9099 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9100
9101 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9102 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9103 case TRANS_DDI_EDP_INPUT_A_ON:
9104 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9105 pipe = PIPE_A;
9106 break;
9107 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9108 pipe = PIPE_B;
9109 break;
9110 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9111 pipe = PIPE_C;
9112 break;
9113 }
9114
9115 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9116 crtc->cpu_transcoder = TRANSCODER_EDP;
9117
9118 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9119 pipe_name(pipe));
9120 }
9121 }
9122
9123 for_each_pipe(pipe) {
9124 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9125
9126 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
9127 if (tmp & PIPECONF_ENABLE)
9128 crtc->active = true;
9129 else
9130 crtc->active = false;
9131
9132 crtc->base.enabled = crtc->active;
9133
9134 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9135 crtc->base.base.id,
9136 crtc->active ? "enabled" : "disabled");
9137 }
9138
9139 if (HAS_DDI(dev))
9140 intel_ddi_setup_hw_pll_state(dev);
9141
9142 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9143 base.head) {
9144 pipe = 0;
9145
9146 if (encoder->get_hw_state(encoder, &pipe)) {
9147 encoder->base.crtc =
9148 dev_priv->pipe_to_crtc_mapping[pipe];
9149 } else {
9150 encoder->base.crtc = NULL;
9151 }
9152
9153 encoder->connectors_active = false;
9154 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9155 encoder->base.base.id,
9156 drm_get_encoder_name(&encoder->base),
9157 encoder->base.crtc ? "enabled" : "disabled",
9158 pipe);
9159 }
9160
9161 list_for_each_entry(connector, &dev->mode_config.connector_list,
9162 base.head) {
9163 if (connector->get_hw_state(connector)) {
9164 connector->base.dpms = DRM_MODE_DPMS_ON;
9165 connector->encoder->connectors_active = true;
9166 connector->base.encoder = &connector->encoder->base;
9167 } else {
9168 connector->base.dpms = DRM_MODE_DPMS_OFF;
9169 connector->base.encoder = NULL;
9170 }
9171 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9172 connector->base.base.id,
9173 drm_get_connector_name(&connector->base),
9174 connector->base.encoder ? "enabled" : "disabled");
9175 }
9176
9177 /* HW state is read out, now we need to sanitize this mess. */
9178 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9179 base.head) {
9180 intel_sanitize_encoder(encoder);
9181 }
9182
9183 for_each_pipe(pipe) {
9184 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9185 intel_sanitize_crtc(crtc);
9186 }
9187
9188 if (force_restore) {
9189 for_each_pipe(pipe) {
9190 intel_crtc_restore_mode(dev_priv->pipe_to_crtc_mapping[pipe]);
9191 }
9192
9193 i915_redisable_vga(dev);
9194 } else {
9195 intel_modeset_update_staged_output_state(dev);
9196 }
9197
9198 intel_modeset_check_state(dev);
9199
9200 drm_mode_config_reset(dev);
9201 }
9202
9203 void intel_modeset_gem_init(struct drm_device *dev)
9204 {
9205 intel_modeset_init_hw(dev);
9206
9207 intel_setup_overlay(dev);
9208
9209 intel_modeset_setup_hw_state(dev, false);
9210 }
9211
9212 void intel_modeset_cleanup(struct drm_device *dev)
9213 {
9214 struct drm_i915_private *dev_priv = dev->dev_private;
9215 struct drm_crtc *crtc;
9216 struct intel_crtc *intel_crtc;
9217
9218 drm_kms_helper_poll_fini(dev);
9219 mutex_lock(&dev->struct_mutex);
9220
9221 intel_unregister_dsm_handler();
9222
9223
9224 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9225 /* Skip inactive CRTCs */
9226 if (!crtc->fb)
9227 continue;
9228
9229 intel_crtc = to_intel_crtc(crtc);
9230 intel_increase_pllclock(crtc);
9231 }
9232
9233 intel_disable_fbc(dev);
9234
9235 intel_disable_gt_powersave(dev);
9236
9237 ironlake_teardown_rc6(dev);
9238
9239 if (IS_VALLEYVIEW(dev))
9240 vlv_init_dpio(dev);
9241
9242 mutex_unlock(&dev->struct_mutex);
9243
9244 /* Disable the irq before mode object teardown, for the irq might
9245 * enqueue unpin/hotplug work. */
9246 drm_irq_uninstall(dev);
9247 cancel_work_sync(&dev_priv->hotplug_work);
9248 cancel_work_sync(&dev_priv->rps.work);
9249
9250 /* flush any delayed tasks or pending work */
9251 flush_scheduled_work();
9252
9253 drm_mode_config_cleanup(dev);
9254
9255 intel_cleanup_overlay(dev);
9256 }
9257
9258 /*
9259 * Return which encoder is currently attached for connector.
9260 */
9261 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9262 {
9263 return &intel_attached_encoder(connector)->base;
9264 }
9265
9266 void intel_connector_attach_encoder(struct intel_connector *connector,
9267 struct intel_encoder *encoder)
9268 {
9269 connector->encoder = encoder;
9270 drm_mode_connector_attach_encoder(&connector->base,
9271 &encoder->base);
9272 }
9273
9274 /*
9275 * set vga decode state - true == enable VGA decode
9276 */
9277 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9278 {
9279 struct drm_i915_private *dev_priv = dev->dev_private;
9280 u16 gmch_ctrl;
9281
9282 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9283 if (state)
9284 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9285 else
9286 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9287 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9288 return 0;
9289 }
9290
9291 #ifdef CONFIG_DEBUG_FS
9292 #include <linux/seq_file.h>
9293
9294 struct intel_display_error_state {
9295 struct intel_cursor_error_state {
9296 u32 control;
9297 u32 position;
9298 u32 base;
9299 u32 size;
9300 } cursor[I915_MAX_PIPES];
9301
9302 struct intel_pipe_error_state {
9303 u32 conf;
9304 u32 source;
9305
9306 u32 htotal;
9307 u32 hblank;
9308 u32 hsync;
9309 u32 vtotal;
9310 u32 vblank;
9311 u32 vsync;
9312 } pipe[I915_MAX_PIPES];
9313
9314 struct intel_plane_error_state {
9315 u32 control;
9316 u32 stride;
9317 u32 size;
9318 u32 pos;
9319 u32 addr;
9320 u32 surface;
9321 u32 tile_offset;
9322 } plane[I915_MAX_PIPES];
9323 };
9324
9325 struct intel_display_error_state *
9326 intel_display_capture_error_state(struct drm_device *dev)
9327 {
9328 drm_i915_private_t *dev_priv = dev->dev_private;
9329 struct intel_display_error_state *error;
9330 enum transcoder cpu_transcoder;
9331 int i;
9332
9333 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9334 if (error == NULL)
9335 return NULL;
9336
9337 for_each_pipe(i) {
9338 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9339
9340 error->cursor[i].control = I915_READ(CURCNTR(i));
9341 error->cursor[i].position = I915_READ(CURPOS(i));
9342 error->cursor[i].base = I915_READ(CURBASE(i));
9343
9344 error->plane[i].control = I915_READ(DSPCNTR(i));
9345 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9346 error->plane[i].size = I915_READ(DSPSIZE(i));
9347 error->plane[i].pos = I915_READ(DSPPOS(i));
9348 error->plane[i].addr = I915_READ(DSPADDR(i));
9349 if (INTEL_INFO(dev)->gen >= 4) {
9350 error->plane[i].surface = I915_READ(DSPSURF(i));
9351 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9352 }
9353
9354 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9355 error->pipe[i].source = I915_READ(PIPESRC(i));
9356 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9357 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9358 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9359 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9360 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9361 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9362 }
9363
9364 return error;
9365 }
9366
9367 void
9368 intel_display_print_error_state(struct seq_file *m,
9369 struct drm_device *dev,
9370 struct intel_display_error_state *error)
9371 {
9372 drm_i915_private_t *dev_priv = dev->dev_private;
9373 int i;
9374
9375 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9376 for_each_pipe(i) {
9377 seq_printf(m, "Pipe [%d]:\n", i);
9378 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9379 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9380 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9381 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9382 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9383 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9384 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9385 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9386
9387 seq_printf(m, "Plane [%d]:\n", i);
9388 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9389 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9390 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9391 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9392 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9393 if (INTEL_INFO(dev)->gen >= 4) {
9394 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9395 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9396 }
9397
9398 seq_printf(m, "Cursor [%d]:\n", i);
9399 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9400 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9401 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9402 }
9403 }
9404 #endif
Linux kernel - Deliverables
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