2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 static void intel_increase_pllclock(struct drm_crtc
*crtc
);
45 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
47 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
48 struct intel_crtc_config
*pipe_config
);
49 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
50 struct intel_crtc_config
*pipe_config
);
52 static int intel_set_mode(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
53 int x
, int y
, struct drm_framebuffer
*old_fb
);
65 typedef struct intel_limit intel_limit_t
;
67 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
72 intel_pch_rawclk(struct drm_device
*dev
)
74 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
76 WARN_ON(!HAS_PCH_SPLIT(dev
));
78 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
81 static inline u32
/* units of 100MHz */
82 intel_fdi_link_freq(struct drm_device
*dev
)
85 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
86 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
91 static const intel_limit_t intel_limits_i8xx_dac
= {
92 .dot
= { .min
= 25000, .max
= 350000 },
93 .vco
= { .min
= 908000, .max
= 1512000 },
94 .n
= { .min
= 2, .max
= 16 },
95 .m
= { .min
= 96, .max
= 140 },
96 .m1
= { .min
= 18, .max
= 26 },
97 .m2
= { .min
= 6, .max
= 16 },
98 .p
= { .min
= 4, .max
= 128 },
99 .p1
= { .min
= 2, .max
= 33 },
100 .p2
= { .dot_limit
= 165000,
101 .p2_slow
= 4, .p2_fast
= 2 },
104 static const intel_limit_t intel_limits_i8xx_dvo
= {
105 .dot
= { .min
= 25000, .max
= 350000 },
106 .vco
= { .min
= 908000, .max
= 1512000 },
107 .n
= { .min
= 2, .max
= 16 },
108 .m
= { .min
= 96, .max
= 140 },
109 .m1
= { .min
= 18, .max
= 26 },
110 .m2
= { .min
= 6, .max
= 16 },
111 .p
= { .min
= 4, .max
= 128 },
112 .p1
= { .min
= 2, .max
= 33 },
113 .p2
= { .dot_limit
= 165000,
114 .p2_slow
= 4, .p2_fast
= 4 },
117 static const intel_limit_t intel_limits_i8xx_lvds
= {
118 .dot
= { .min
= 25000, .max
= 350000 },
119 .vco
= { .min
= 908000, .max
= 1512000 },
120 .n
= { .min
= 2, .max
= 16 },
121 .m
= { .min
= 96, .max
= 140 },
122 .m1
= { .min
= 18, .max
= 26 },
123 .m2
= { .min
= 6, .max
= 16 },
124 .p
= { .min
= 4, .max
= 128 },
125 .p1
= { .min
= 1, .max
= 6 },
126 .p2
= { .dot_limit
= 165000,
127 .p2_slow
= 14, .p2_fast
= 7 },
130 static const intel_limit_t intel_limits_i9xx_sdvo
= {
131 .dot
= { .min
= 20000, .max
= 400000 },
132 .vco
= { .min
= 1400000, .max
= 2800000 },
133 .n
= { .min
= 1, .max
= 6 },
134 .m
= { .min
= 70, .max
= 120 },
135 .m1
= { .min
= 8, .max
= 18 },
136 .m2
= { .min
= 3, .max
= 7 },
137 .p
= { .min
= 5, .max
= 80 },
138 .p1
= { .min
= 1, .max
= 8 },
139 .p2
= { .dot_limit
= 200000,
140 .p2_slow
= 10, .p2_fast
= 5 },
143 static const intel_limit_t intel_limits_i9xx_lvds
= {
144 .dot
= { .min
= 20000, .max
= 400000 },
145 .vco
= { .min
= 1400000, .max
= 2800000 },
146 .n
= { .min
= 1, .max
= 6 },
147 .m
= { .min
= 70, .max
= 120 },
148 .m1
= { .min
= 8, .max
= 18 },
149 .m2
= { .min
= 3, .max
= 7 },
150 .p
= { .min
= 7, .max
= 98 },
151 .p1
= { .min
= 1, .max
= 8 },
152 .p2
= { .dot_limit
= 112000,
153 .p2_slow
= 14, .p2_fast
= 7 },
157 static const intel_limit_t intel_limits_g4x_sdvo
= {
158 .dot
= { .min
= 25000, .max
= 270000 },
159 .vco
= { .min
= 1750000, .max
= 3500000},
160 .n
= { .min
= 1, .max
= 4 },
161 .m
= { .min
= 104, .max
= 138 },
162 .m1
= { .min
= 17, .max
= 23 },
163 .m2
= { .min
= 5, .max
= 11 },
164 .p
= { .min
= 10, .max
= 30 },
165 .p1
= { .min
= 1, .max
= 3},
166 .p2
= { .dot_limit
= 270000,
172 static const intel_limit_t intel_limits_g4x_hdmi
= {
173 .dot
= { .min
= 22000, .max
= 400000 },
174 .vco
= { .min
= 1750000, .max
= 3500000},
175 .n
= { .min
= 1, .max
= 4 },
176 .m
= { .min
= 104, .max
= 138 },
177 .m1
= { .min
= 16, .max
= 23 },
178 .m2
= { .min
= 5, .max
= 11 },
179 .p
= { .min
= 5, .max
= 80 },
180 .p1
= { .min
= 1, .max
= 8},
181 .p2
= { .dot_limit
= 165000,
182 .p2_slow
= 10, .p2_fast
= 5 },
185 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
186 .dot
= { .min
= 20000, .max
= 115000 },
187 .vco
= { .min
= 1750000, .max
= 3500000 },
188 .n
= { .min
= 1, .max
= 3 },
189 .m
= { .min
= 104, .max
= 138 },
190 .m1
= { .min
= 17, .max
= 23 },
191 .m2
= { .min
= 5, .max
= 11 },
192 .p
= { .min
= 28, .max
= 112 },
193 .p1
= { .min
= 2, .max
= 8 },
194 .p2
= { .dot_limit
= 0,
195 .p2_slow
= 14, .p2_fast
= 14
199 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
200 .dot
= { .min
= 80000, .max
= 224000 },
201 .vco
= { .min
= 1750000, .max
= 3500000 },
202 .n
= { .min
= 1, .max
= 3 },
203 .m
= { .min
= 104, .max
= 138 },
204 .m1
= { .min
= 17, .max
= 23 },
205 .m2
= { .min
= 5, .max
= 11 },
206 .p
= { .min
= 14, .max
= 42 },
207 .p1
= { .min
= 2, .max
= 6 },
208 .p2
= { .dot_limit
= 0,
209 .p2_slow
= 7, .p2_fast
= 7
213 static const intel_limit_t intel_limits_pineview_sdvo
= {
214 .dot
= { .min
= 20000, .max
= 400000},
215 .vco
= { .min
= 1700000, .max
= 3500000 },
216 /* Pineview's Ncounter is a ring counter */
217 .n
= { .min
= 3, .max
= 6 },
218 .m
= { .min
= 2, .max
= 256 },
219 /* Pineview only has one combined m divider, which we treat as m2. */
220 .m1
= { .min
= 0, .max
= 0 },
221 .m2
= { .min
= 0, .max
= 254 },
222 .p
= { .min
= 5, .max
= 80 },
223 .p1
= { .min
= 1, .max
= 8 },
224 .p2
= { .dot_limit
= 200000,
225 .p2_slow
= 10, .p2_fast
= 5 },
228 static const intel_limit_t intel_limits_pineview_lvds
= {
229 .dot
= { .min
= 20000, .max
= 400000 },
230 .vco
= { .min
= 1700000, .max
= 3500000 },
231 .n
= { .min
= 3, .max
= 6 },
232 .m
= { .min
= 2, .max
= 256 },
233 .m1
= { .min
= 0, .max
= 0 },
234 .m2
= { .min
= 0, .max
= 254 },
235 .p
= { .min
= 7, .max
= 112 },
236 .p1
= { .min
= 1, .max
= 8 },
237 .p2
= { .dot_limit
= 112000,
238 .p2_slow
= 14, .p2_fast
= 14 },
241 /* Ironlake / Sandybridge
243 * We calculate clock using (register_value + 2) for N/M1/M2, so here
244 * the range value for them is (actual_value - 2).
246 static const intel_limit_t intel_limits_ironlake_dac
= {
247 .dot
= { .min
= 25000, .max
= 350000 },
248 .vco
= { .min
= 1760000, .max
= 3510000 },
249 .n
= { .min
= 1, .max
= 5 },
250 .m
= { .min
= 79, .max
= 127 },
251 .m1
= { .min
= 12, .max
= 22 },
252 .m2
= { .min
= 5, .max
= 9 },
253 .p
= { .min
= 5, .max
= 80 },
254 .p1
= { .min
= 1, .max
= 8 },
255 .p2
= { .dot_limit
= 225000,
256 .p2_slow
= 10, .p2_fast
= 5 },
259 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
260 .dot
= { .min
= 25000, .max
= 350000 },
261 .vco
= { .min
= 1760000, .max
= 3510000 },
262 .n
= { .min
= 1, .max
= 3 },
263 .m
= { .min
= 79, .max
= 118 },
264 .m1
= { .min
= 12, .max
= 22 },
265 .m2
= { .min
= 5, .max
= 9 },
266 .p
= { .min
= 28, .max
= 112 },
267 .p1
= { .min
= 2, .max
= 8 },
268 .p2
= { .dot_limit
= 225000,
269 .p2_slow
= 14, .p2_fast
= 14 },
272 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
273 .dot
= { .min
= 25000, .max
= 350000 },
274 .vco
= { .min
= 1760000, .max
= 3510000 },
275 .n
= { .min
= 1, .max
= 3 },
276 .m
= { .min
= 79, .max
= 127 },
277 .m1
= { .min
= 12, .max
= 22 },
278 .m2
= { .min
= 5, .max
= 9 },
279 .p
= { .min
= 14, .max
= 56 },
280 .p1
= { .min
= 2, .max
= 8 },
281 .p2
= { .dot_limit
= 225000,
282 .p2_slow
= 7, .p2_fast
= 7 },
285 /* LVDS 100mhz refclk limits. */
286 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
287 .dot
= { .min
= 25000, .max
= 350000 },
288 .vco
= { .min
= 1760000, .max
= 3510000 },
289 .n
= { .min
= 1, .max
= 2 },
290 .m
= { .min
= 79, .max
= 126 },
291 .m1
= { .min
= 12, .max
= 22 },
292 .m2
= { .min
= 5, .max
= 9 },
293 .p
= { .min
= 28, .max
= 112 },
294 .p1
= { .min
= 2, .max
= 8 },
295 .p2
= { .dot_limit
= 225000,
296 .p2_slow
= 14, .p2_fast
= 14 },
299 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
300 .dot
= { .min
= 25000, .max
= 350000 },
301 .vco
= { .min
= 1760000, .max
= 3510000 },
302 .n
= { .min
= 1, .max
= 3 },
303 .m
= { .min
= 79, .max
= 126 },
304 .m1
= { .min
= 12, .max
= 22 },
305 .m2
= { .min
= 5, .max
= 9 },
306 .p
= { .min
= 14, .max
= 42 },
307 .p1
= { .min
= 2, .max
= 6 },
308 .p2
= { .dot_limit
= 225000,
309 .p2_slow
= 7, .p2_fast
= 7 },
312 static const intel_limit_t intel_limits_vlv
= {
314 * These are the data rate limits (measured in fast clocks)
315 * since those are the strictest limits we have. The fast
316 * clock and actual rate limits are more relaxed, so checking
317 * them would make no difference.
319 .dot
= { .min
= 25000 * 5, .max
= 270000 * 5 },
320 .vco
= { .min
= 4000000, .max
= 6000000 },
321 .n
= { .min
= 1, .max
= 7 },
322 .m1
= { .min
= 2, .max
= 3 },
323 .m2
= { .min
= 11, .max
= 156 },
324 .p1
= { .min
= 2, .max
= 3 },
325 .p2
= { .p2_slow
= 2, .p2_fast
= 20 }, /* slow=min, fast=max */
328 static void vlv_clock(int refclk
, intel_clock_t
*clock
)
330 clock
->m
= clock
->m1
* clock
->m2
;
331 clock
->p
= clock
->p1
* clock
->p2
;
332 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
334 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
335 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
339 * Returns whether any output on the specified pipe is of the specified type
341 static bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
343 struct drm_device
*dev
= crtc
->dev
;
344 struct intel_encoder
*encoder
;
346 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
347 if (encoder
->type
== type
)
353 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
,
356 struct drm_device
*dev
= crtc
->dev
;
357 const intel_limit_t
*limit
;
359 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
360 if (intel_is_dual_link_lvds(dev
)) {
361 if (refclk
== 100000)
362 limit
= &intel_limits_ironlake_dual_lvds_100m
;
364 limit
= &intel_limits_ironlake_dual_lvds
;
366 if (refclk
== 100000)
367 limit
= &intel_limits_ironlake_single_lvds_100m
;
369 limit
= &intel_limits_ironlake_single_lvds
;
372 limit
= &intel_limits_ironlake_dac
;
377 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
379 struct drm_device
*dev
= crtc
->dev
;
380 const intel_limit_t
*limit
;
382 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
383 if (intel_is_dual_link_lvds(dev
))
384 limit
= &intel_limits_g4x_dual_channel_lvds
;
386 limit
= &intel_limits_g4x_single_channel_lvds
;
387 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
388 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
389 limit
= &intel_limits_g4x_hdmi
;
390 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
391 limit
= &intel_limits_g4x_sdvo
;
392 } else /* The option is for other outputs */
393 limit
= &intel_limits_i9xx_sdvo
;
398 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
, int refclk
)
400 struct drm_device
*dev
= crtc
->dev
;
401 const intel_limit_t
*limit
;
403 if (HAS_PCH_SPLIT(dev
))
404 limit
= intel_ironlake_limit(crtc
, refclk
);
405 else if (IS_G4X(dev
)) {
406 limit
= intel_g4x_limit(crtc
);
407 } else if (IS_PINEVIEW(dev
)) {
408 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
409 limit
= &intel_limits_pineview_lvds
;
411 limit
= &intel_limits_pineview_sdvo
;
412 } else if (IS_VALLEYVIEW(dev
)) {
413 limit
= &intel_limits_vlv
;
414 } else if (!IS_GEN2(dev
)) {
415 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
416 limit
= &intel_limits_i9xx_lvds
;
418 limit
= &intel_limits_i9xx_sdvo
;
420 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
421 limit
= &intel_limits_i8xx_lvds
;
422 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
))
423 limit
= &intel_limits_i8xx_dvo
;
425 limit
= &intel_limits_i8xx_dac
;
430 /* m1 is reserved as 0 in Pineview, n is a ring counter */
431 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
433 clock
->m
= clock
->m2
+ 2;
434 clock
->p
= clock
->p1
* clock
->p2
;
435 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
437 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
438 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
441 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
443 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
446 static void i9xx_clock(int refclk
, intel_clock_t
*clock
)
448 clock
->m
= i9xx_dpll_compute_m(clock
);
449 clock
->p
= clock
->p1
* clock
->p2
;
450 if (WARN_ON(clock
->n
+ 2 == 0 || clock
->p
== 0))
452 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
+ 2);
453 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
456 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
458 * Returns whether the given set of divisors are valid for a given refclk with
459 * the given connectors.
462 static bool intel_PLL_is_valid(struct drm_device
*dev
,
463 const intel_limit_t
*limit
,
464 const intel_clock_t
*clock
)
466 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
467 INTELPllInvalid("n out of range\n");
468 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
469 INTELPllInvalid("p1 out of range\n");
470 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
471 INTELPllInvalid("m2 out of range\n");
472 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
473 INTELPllInvalid("m1 out of range\n");
475 if (!IS_PINEVIEW(dev
) && !IS_VALLEYVIEW(dev
))
476 if (clock
->m1
<= clock
->m2
)
477 INTELPllInvalid("m1 <= m2\n");
479 if (!IS_VALLEYVIEW(dev
)) {
480 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
481 INTELPllInvalid("p out of range\n");
482 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
483 INTELPllInvalid("m out of range\n");
486 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
487 INTELPllInvalid("vco out of range\n");
488 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
489 * connector, etc., rather than just a single range.
491 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
492 INTELPllInvalid("dot out of range\n");
498 i9xx_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
499 int target
, int refclk
, intel_clock_t
*match_clock
,
500 intel_clock_t
*best_clock
)
502 struct drm_device
*dev
= crtc
->dev
;
506 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
508 * For LVDS just rely on its current settings for dual-channel.
509 * We haven't figured out how to reliably set up different
510 * single/dual channel state, if we even can.
512 if (intel_is_dual_link_lvds(dev
))
513 clock
.p2
= limit
->p2
.p2_fast
;
515 clock
.p2
= limit
->p2
.p2_slow
;
517 if (target
< limit
->p2
.dot_limit
)
518 clock
.p2
= limit
->p2
.p2_slow
;
520 clock
.p2
= limit
->p2
.p2_fast
;
523 memset(best_clock
, 0, sizeof(*best_clock
));
525 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
527 for (clock
.m2
= limit
->m2
.min
;
528 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
529 if (clock
.m2
>= clock
.m1
)
531 for (clock
.n
= limit
->n
.min
;
532 clock
.n
<= limit
->n
.max
; clock
.n
++) {
533 for (clock
.p1
= limit
->p1
.min
;
534 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
537 i9xx_clock(refclk
, &clock
);
538 if (!intel_PLL_is_valid(dev
, limit
,
542 clock
.p
!= match_clock
->p
)
545 this_err
= abs(clock
.dot
- target
);
546 if (this_err
< err
) {
555 return (err
!= target
);
559 pnv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
560 int target
, int refclk
, intel_clock_t
*match_clock
,
561 intel_clock_t
*best_clock
)
563 struct drm_device
*dev
= crtc
->dev
;
567 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
569 * For LVDS just rely on its current settings for dual-channel.
570 * We haven't figured out how to reliably set up different
571 * single/dual channel state, if we even can.
573 if (intel_is_dual_link_lvds(dev
))
574 clock
.p2
= limit
->p2
.p2_fast
;
576 clock
.p2
= limit
->p2
.p2_slow
;
578 if (target
< limit
->p2
.dot_limit
)
579 clock
.p2
= limit
->p2
.p2_slow
;
581 clock
.p2
= limit
->p2
.p2_fast
;
584 memset(best_clock
, 0, sizeof(*best_clock
));
586 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
588 for (clock
.m2
= limit
->m2
.min
;
589 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
590 for (clock
.n
= limit
->n
.min
;
591 clock
.n
<= limit
->n
.max
; clock
.n
++) {
592 for (clock
.p1
= limit
->p1
.min
;
593 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
596 pineview_clock(refclk
, &clock
);
597 if (!intel_PLL_is_valid(dev
, limit
,
601 clock
.p
!= match_clock
->p
)
604 this_err
= abs(clock
.dot
- target
);
605 if (this_err
< err
) {
614 return (err
!= target
);
618 g4x_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
619 int target
, int refclk
, intel_clock_t
*match_clock
,
620 intel_clock_t
*best_clock
)
622 struct drm_device
*dev
= crtc
->dev
;
626 /* approximately equals target * 0.00585 */
627 int err_most
= (target
>> 8) + (target
>> 9);
630 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
631 if (intel_is_dual_link_lvds(dev
))
632 clock
.p2
= limit
->p2
.p2_fast
;
634 clock
.p2
= limit
->p2
.p2_slow
;
636 if (target
< limit
->p2
.dot_limit
)
637 clock
.p2
= limit
->p2
.p2_slow
;
639 clock
.p2
= limit
->p2
.p2_fast
;
642 memset(best_clock
, 0, sizeof(*best_clock
));
643 max_n
= limit
->n
.max
;
644 /* based on hardware requirement, prefer smaller n to precision */
645 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
646 /* based on hardware requirement, prefere larger m1,m2 */
647 for (clock
.m1
= limit
->m1
.max
;
648 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
649 for (clock
.m2
= limit
->m2
.max
;
650 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
651 for (clock
.p1
= limit
->p1
.max
;
652 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
655 i9xx_clock(refclk
, &clock
);
656 if (!intel_PLL_is_valid(dev
, limit
,
660 this_err
= abs(clock
.dot
- target
);
661 if (this_err
< err_most
) {
675 vlv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
676 int target
, int refclk
, intel_clock_t
*match_clock
,
677 intel_clock_t
*best_clock
)
679 struct drm_device
*dev
= crtc
->dev
;
681 unsigned int bestppm
= 1000000;
682 /* min update 19.2 MHz */
683 int max_n
= min(limit
->n
.max
, refclk
/ 19200);
686 target
*= 5; /* fast clock */
688 memset(best_clock
, 0, sizeof(*best_clock
));
690 /* based on hardware requirement, prefer smaller n to precision */
691 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
692 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
693 for (clock
.p2
= limit
->p2
.p2_fast
; clock
.p2
>= limit
->p2
.p2_slow
;
694 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
695 clock
.p
= clock
.p1
* clock
.p2
;
696 /* based on hardware requirement, prefer bigger m1,m2 values */
697 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
698 unsigned int ppm
, diff
;
700 clock
.m2
= DIV_ROUND_CLOSEST(target
* clock
.p
* clock
.n
,
703 vlv_clock(refclk
, &clock
);
705 if (!intel_PLL_is_valid(dev
, limit
,
709 diff
= abs(clock
.dot
- target
);
710 ppm
= div_u64(1000000ULL * diff
, target
);
712 if (ppm
< 100 && clock
.p
> best_clock
->p
) {
718 if (bestppm
>= 10 && ppm
< bestppm
- 10) {
731 bool intel_crtc_active(struct drm_crtc
*crtc
)
733 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
735 /* Be paranoid as we can arrive here with only partial
736 * state retrieved from the hardware during setup.
738 * We can ditch the adjusted_mode.crtc_clock check as soon
739 * as Haswell has gained clock readout/fastboot support.
741 * We can ditch the crtc->fb check as soon as we can
742 * properly reconstruct framebuffers.
744 return intel_crtc
->active
&& crtc
->fb
&&
745 intel_crtc
->config
.adjusted_mode
.crtc_clock
;
748 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
751 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
752 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
754 return intel_crtc
->config
.cpu_transcoder
;
757 static void g4x_wait_for_vblank(struct drm_device
*dev
, int pipe
)
759 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
760 u32 frame
, frame_reg
= PIPE_FRMCOUNT_GM45(pipe
);
762 frame
= I915_READ(frame_reg
);
764 if (wait_for(I915_READ_NOTRACE(frame_reg
) != frame
, 50))
765 DRM_DEBUG_KMS("vblank wait timed out\n");
769 * intel_wait_for_vblank - wait for vblank on a given pipe
771 * @pipe: pipe to wait for
773 * Wait for vblank to occur on a given pipe. Needed for various bits of
776 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
778 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
779 int pipestat_reg
= PIPESTAT(pipe
);
781 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
782 g4x_wait_for_vblank(dev
, pipe
);
786 /* Clear existing vblank status. Note this will clear any other
787 * sticky status fields as well.
789 * This races with i915_driver_irq_handler() with the result
790 * that either function could miss a vblank event. Here it is not
791 * fatal, as we will either wait upon the next vblank interrupt or
792 * timeout. Generally speaking intel_wait_for_vblank() is only
793 * called during modeset at which time the GPU should be idle and
794 * should *not* be performing page flips and thus not waiting on
796 * Currently, the result of us stealing a vblank from the irq
797 * handler is that a single frame will be skipped during swapbuffers.
799 I915_WRITE(pipestat_reg
,
800 I915_READ(pipestat_reg
) | PIPE_VBLANK_INTERRUPT_STATUS
);
802 /* Wait for vblank interrupt bit to set */
803 if (wait_for(I915_READ(pipestat_reg
) &
804 PIPE_VBLANK_INTERRUPT_STATUS
,
806 DRM_DEBUG_KMS("vblank wait timed out\n");
809 static bool pipe_dsl_stopped(struct drm_device
*dev
, enum pipe pipe
)
811 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
812 u32 reg
= PIPEDSL(pipe
);
817 line_mask
= DSL_LINEMASK_GEN2
;
819 line_mask
= DSL_LINEMASK_GEN3
;
821 line1
= I915_READ(reg
) & line_mask
;
823 line2
= I915_READ(reg
) & line_mask
;
825 return line1
== line2
;
829 * intel_wait_for_pipe_off - wait for pipe to turn off
831 * @pipe: pipe to wait for
833 * After disabling a pipe, we can't wait for vblank in the usual way,
834 * spinning on the vblank interrupt status bit, since we won't actually
835 * see an interrupt when the pipe is disabled.
838 * wait for the pipe register state bit to turn off
841 * wait for the display line value to settle (it usually
842 * ends up stopping at the start of the next frame).
845 void intel_wait_for_pipe_off(struct drm_device
*dev
, int pipe
)
847 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
848 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
851 if (INTEL_INFO(dev
)->gen
>= 4) {
852 int reg
= PIPECONF(cpu_transcoder
);
854 /* Wait for the Pipe State to go off */
855 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
857 WARN(1, "pipe_off wait timed out\n");
859 /* Wait for the display line to settle */
860 if (wait_for(pipe_dsl_stopped(dev
, pipe
), 100))
861 WARN(1, "pipe_off wait timed out\n");
866 * ibx_digital_port_connected - is the specified port connected?
867 * @dev_priv: i915 private structure
868 * @port: the port to test
870 * Returns true if @port is connected, false otherwise.
872 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
873 struct intel_digital_port
*port
)
877 if (HAS_PCH_IBX(dev_priv
->dev
)) {
880 bit
= SDE_PORTB_HOTPLUG
;
883 bit
= SDE_PORTC_HOTPLUG
;
886 bit
= SDE_PORTD_HOTPLUG
;
894 bit
= SDE_PORTB_HOTPLUG_CPT
;
897 bit
= SDE_PORTC_HOTPLUG_CPT
;
900 bit
= SDE_PORTD_HOTPLUG_CPT
;
907 return I915_READ(SDEISR
) & bit
;
910 static const char *state_string(bool enabled
)
912 return enabled
? "on" : "off";
915 /* Only for pre-ILK configs */
916 void assert_pll(struct drm_i915_private
*dev_priv
,
917 enum pipe pipe
, bool state
)
924 val
= I915_READ(reg
);
925 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
926 WARN(cur_state
!= state
,
927 "PLL state assertion failure (expected %s, current %s)\n",
928 state_string(state
), state_string(cur_state
));
931 /* XXX: the dsi pll is shared between MIPI DSI ports */
932 static void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
937 mutex_lock(&dev_priv
->dpio_lock
);
938 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
939 mutex_unlock(&dev_priv
->dpio_lock
);
941 cur_state
= val
& DSI_PLL_VCO_EN
;
942 WARN(cur_state
!= state
,
943 "DSI PLL state assertion failure (expected %s, current %s)\n",
944 state_string(state
), state_string(cur_state
));
946 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
947 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
949 struct intel_shared_dpll
*
950 intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
)
952 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
954 if (crtc
->config
.shared_dpll
< 0)
957 return &dev_priv
->shared_dplls
[crtc
->config
.shared_dpll
];
961 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
962 struct intel_shared_dpll
*pll
,
966 struct intel_dpll_hw_state hw_state
;
968 if (HAS_PCH_LPT(dev_priv
->dev
)) {
969 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
974 "asserting DPLL %s with no DPLL\n", state_string(state
)))
977 cur_state
= pll
->get_hw_state(dev_priv
, pll
, &hw_state
);
978 WARN(cur_state
!= state
,
979 "%s assertion failure (expected %s, current %s)\n",
980 pll
->name
, state_string(state
), state_string(cur_state
));
983 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
984 enum pipe pipe
, bool state
)
989 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
992 if (HAS_DDI(dev_priv
->dev
)) {
993 /* DDI does not have a specific FDI_TX register */
994 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
995 val
= I915_READ(reg
);
996 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
998 reg
= FDI_TX_CTL(pipe
);
999 val
= I915_READ(reg
);
1000 cur_state
= !!(val
& FDI_TX_ENABLE
);
1002 WARN(cur_state
!= state
,
1003 "FDI TX state assertion failure (expected %s, current %s)\n",
1004 state_string(state
), state_string(cur_state
));
1006 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1007 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1009 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1010 enum pipe pipe
, bool state
)
1016 reg
= FDI_RX_CTL(pipe
);
1017 val
= I915_READ(reg
);
1018 cur_state
= !!(val
& FDI_RX_ENABLE
);
1019 WARN(cur_state
!= state
,
1020 "FDI RX state assertion failure (expected %s, current %s)\n",
1021 state_string(state
), state_string(cur_state
));
1023 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1024 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1026 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1032 /* ILK FDI PLL is always enabled */
1033 if (dev_priv
->info
->gen
== 5)
1036 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1037 if (HAS_DDI(dev_priv
->dev
))
1040 reg
= FDI_TX_CTL(pipe
);
1041 val
= I915_READ(reg
);
1042 WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1045 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1046 enum pipe pipe
, bool state
)
1052 reg
= FDI_RX_CTL(pipe
);
1053 val
= I915_READ(reg
);
1054 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1055 WARN(cur_state
!= state
,
1056 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1057 state_string(state
), state_string(cur_state
));
1060 static void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1063 int pp_reg
, lvds_reg
;
1065 enum pipe panel_pipe
= PIPE_A
;
1068 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
1069 pp_reg
= PCH_PP_CONTROL
;
1070 lvds_reg
= PCH_LVDS
;
1072 pp_reg
= PP_CONTROL
;
1076 val
= I915_READ(pp_reg
);
1077 if (!(val
& PANEL_POWER_ON
) ||
1078 ((val
& PANEL_UNLOCK_REGS
) == PANEL_UNLOCK_REGS
))
1081 if (I915_READ(lvds_reg
) & LVDS_PIPEB_SELECT
)
1082 panel_pipe
= PIPE_B
;
1084 WARN(panel_pipe
== pipe
&& locked
,
1085 "panel assertion failure, pipe %c regs locked\n",
1089 static void assert_cursor(struct drm_i915_private
*dev_priv
,
1090 enum pipe pipe
, bool state
)
1092 struct drm_device
*dev
= dev_priv
->dev
;
1095 if (IS_845G(dev
) || IS_I865G(dev
))
1096 cur_state
= I915_READ(_CURACNTR
) & CURSOR_ENABLE
;
1097 else if (INTEL_INFO(dev
)->gen
<= 6 || IS_VALLEYVIEW(dev
))
1098 cur_state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
1100 cur_state
= I915_READ(CURCNTR_IVB(pipe
)) & CURSOR_MODE
;
1102 WARN(cur_state
!= state
,
1103 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1104 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1106 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1107 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1109 void assert_pipe(struct drm_i915_private
*dev_priv
,
1110 enum pipe pipe
, bool state
)
1115 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1118 /* if we need the pipe A quirk it must be always on */
1119 if (pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
1122 if (!intel_display_power_enabled(dev_priv
->dev
,
1123 POWER_DOMAIN_TRANSCODER(cpu_transcoder
))) {
1126 reg
= PIPECONF(cpu_transcoder
);
1127 val
= I915_READ(reg
);
1128 cur_state
= !!(val
& PIPECONF_ENABLE
);
1131 WARN(cur_state
!= state
,
1132 "pipe %c assertion failure (expected %s, current %s)\n",
1133 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1136 static void assert_plane(struct drm_i915_private
*dev_priv
,
1137 enum plane plane
, bool state
)
1143 reg
= DSPCNTR(plane
);
1144 val
= I915_READ(reg
);
1145 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1146 WARN(cur_state
!= state
,
1147 "plane %c assertion failure (expected %s, current %s)\n",
1148 plane_name(plane
), state_string(state
), state_string(cur_state
));
1151 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1152 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1154 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1157 struct drm_device
*dev
= dev_priv
->dev
;
1162 /* Primary planes are fixed to pipes on gen4+ */
1163 if (INTEL_INFO(dev
)->gen
>= 4) {
1164 reg
= DSPCNTR(pipe
);
1165 val
= I915_READ(reg
);
1166 WARN((val
& DISPLAY_PLANE_ENABLE
),
1167 "plane %c assertion failure, should be disabled but not\n",
1172 /* Need to check both planes against the pipe */
1175 val
= I915_READ(reg
);
1176 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1177 DISPPLANE_SEL_PIPE_SHIFT
;
1178 WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1179 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1180 plane_name(i
), pipe_name(pipe
));
1184 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1187 struct drm_device
*dev
= dev_priv
->dev
;
1191 if (IS_VALLEYVIEW(dev
)) {
1192 for (i
= 0; i
< dev_priv
->num_plane
; i
++) {
1193 reg
= SPCNTR(pipe
, i
);
1194 val
= I915_READ(reg
);
1195 WARN((val
& SP_ENABLE
),
1196 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1197 sprite_name(pipe
, i
), pipe_name(pipe
));
1199 } else if (INTEL_INFO(dev
)->gen
>= 7) {
1201 val
= I915_READ(reg
);
1202 WARN((val
& SPRITE_ENABLE
),
1203 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1204 plane_name(pipe
), pipe_name(pipe
));
1205 } else if (INTEL_INFO(dev
)->gen
>= 5) {
1206 reg
= DVSCNTR(pipe
);
1207 val
= I915_READ(reg
);
1208 WARN((val
& DVS_ENABLE
),
1209 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1210 plane_name(pipe
), pipe_name(pipe
));
1214 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1219 WARN_ON(!(HAS_PCH_IBX(dev_priv
->dev
) || HAS_PCH_CPT(dev_priv
->dev
)));
1221 val
= I915_READ(PCH_DREF_CONTROL
);
1222 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1223 DREF_SUPERSPREAD_SOURCE_MASK
));
1224 WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1227 static void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1234 reg
= PCH_TRANSCONF(pipe
);
1235 val
= I915_READ(reg
);
1236 enabled
= !!(val
& TRANS_ENABLE
);
1238 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1242 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1243 enum pipe pipe
, u32 port_sel
, u32 val
)
1245 if ((val
& DP_PORT_EN
) == 0)
1248 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1249 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1250 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1251 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1254 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1260 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1261 enum pipe pipe
, u32 val
)
1263 if ((val
& SDVO_ENABLE
) == 0)
1266 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1267 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1270 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1276 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1277 enum pipe pipe
, u32 val
)
1279 if ((val
& LVDS_PORT_EN
) == 0)
1282 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1283 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1286 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1292 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1293 enum pipe pipe
, u32 val
)
1295 if ((val
& ADPA_DAC_ENABLE
) == 0)
1297 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1298 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1301 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1307 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1308 enum pipe pipe
, int reg
, u32 port_sel
)
1310 u32 val
= I915_READ(reg
);
1311 WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1312 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1313 reg
, pipe_name(pipe
));
1315 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1316 && (val
& DP_PIPEB_SELECT
),
1317 "IBX PCH dp port still using transcoder B\n");
1320 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1321 enum pipe pipe
, int reg
)
1323 u32 val
= I915_READ(reg
);
1324 WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1325 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1326 reg
, pipe_name(pipe
));
1328 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_ENABLE
) == 0
1329 && (val
& SDVO_PIPE_B_SELECT
),
1330 "IBX PCH hdmi port still using transcoder B\n");
1333 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1339 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1340 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1341 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1344 val
= I915_READ(reg
);
1345 WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1346 "PCH VGA enabled on transcoder %c, should be disabled\n",
1350 val
= I915_READ(reg
);
1351 WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1352 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1355 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1356 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1357 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1360 static void intel_init_dpio(struct drm_device
*dev
)
1362 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1364 if (!IS_VALLEYVIEW(dev
))
1367 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO
;
1370 static void intel_reset_dpio(struct drm_device
*dev
)
1372 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1374 if (!IS_VALLEYVIEW(dev
))
1378 * Enable the CRI clock source so we can get at the display and the
1379 * reference clock for VGA hotplug / manual detection.
1381 I915_WRITE(DPLL(PIPE_B
), I915_READ(DPLL(PIPE_B
)) |
1382 DPLL_REFA_CLK_ENABLE_VLV
|
1383 DPLL_INTEGRATED_CRI_CLK_VLV
);
1386 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1387 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
1388 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
1389 * b. The other bits such as sfr settings / modesel may all be set
1392 * This should only be done on init and resume from S3 with both
1393 * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1395 I915_WRITE(DPIO_CTL
, I915_READ(DPIO_CTL
) | DPIO_CMNRST
);
1398 static void vlv_enable_pll(struct intel_crtc
*crtc
)
1400 struct drm_device
*dev
= crtc
->base
.dev
;
1401 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1402 int reg
= DPLL(crtc
->pipe
);
1403 u32 dpll
= crtc
->config
.dpll_hw_state
.dpll
;
1405 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1407 /* No really, not for ILK+ */
1408 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
));
1410 /* PLL is protected by panel, make sure we can write it */
1411 if (IS_MOBILE(dev_priv
->dev
) && !IS_I830(dev_priv
->dev
))
1412 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1414 I915_WRITE(reg
, dpll
);
1418 if (wait_for(((I915_READ(reg
) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1419 DRM_ERROR("DPLL %d failed to lock\n", crtc
->pipe
);
1421 I915_WRITE(DPLL_MD(crtc
->pipe
), crtc
->config
.dpll_hw_state
.dpll_md
);
1422 POSTING_READ(DPLL_MD(crtc
->pipe
));
1424 /* We do this three times for luck */
1425 I915_WRITE(reg
, dpll
);
1427 udelay(150); /* wait for warmup */
1428 I915_WRITE(reg
, dpll
);
1430 udelay(150); /* wait for warmup */
1431 I915_WRITE(reg
, dpll
);
1433 udelay(150); /* wait for warmup */
1436 static void i9xx_enable_pll(struct intel_crtc
*crtc
)
1438 struct drm_device
*dev
= crtc
->base
.dev
;
1439 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1440 int reg
= DPLL(crtc
->pipe
);
1441 u32 dpll
= crtc
->config
.dpll_hw_state
.dpll
;
1443 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1445 /* No really, not for ILK+ */
1446 BUG_ON(dev_priv
->info
->gen
>= 5);
1448 /* PLL is protected by panel, make sure we can write it */
1449 if (IS_MOBILE(dev
) && !IS_I830(dev
))
1450 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1452 I915_WRITE(reg
, dpll
);
1454 /* Wait for the clocks to stabilize. */
1458 if (INTEL_INFO(dev
)->gen
>= 4) {
1459 I915_WRITE(DPLL_MD(crtc
->pipe
),
1460 crtc
->config
.dpll_hw_state
.dpll_md
);
1462 /* The pixel multiplier can only be updated once the
1463 * DPLL is enabled and the clocks are stable.
1465 * So write it again.
1467 I915_WRITE(reg
, dpll
);
1470 /* We do this three times for luck */
1471 I915_WRITE(reg
, dpll
);
1473 udelay(150); /* wait for warmup */
1474 I915_WRITE(reg
, dpll
);
1476 udelay(150); /* wait for warmup */
1477 I915_WRITE(reg
, dpll
);
1479 udelay(150); /* wait for warmup */
1483 * i9xx_disable_pll - disable a PLL
1484 * @dev_priv: i915 private structure
1485 * @pipe: pipe PLL to disable
1487 * Disable the PLL for @pipe, making sure the pipe is off first.
1489 * Note! This is for pre-ILK only.
1491 static void i9xx_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1493 /* Don't disable pipe A or pipe A PLLs if needed */
1494 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1497 /* Make sure the pipe isn't still relying on us */
1498 assert_pipe_disabled(dev_priv
, pipe
);
1500 I915_WRITE(DPLL(pipe
), 0);
1501 POSTING_READ(DPLL(pipe
));
1504 static void vlv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1508 /* Make sure the pipe isn't still relying on us */
1509 assert_pipe_disabled(dev_priv
, pipe
);
1512 * Leave integrated clock source and reference clock enabled for pipe B.
1513 * The latter is needed for VGA hotplug / manual detection.
1516 val
= DPLL_INTEGRATED_CRI_CLK_VLV
| DPLL_REFA_CLK_ENABLE_VLV
;
1517 I915_WRITE(DPLL(pipe
), val
);
1518 POSTING_READ(DPLL(pipe
));
1521 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1522 struct intel_digital_port
*dport
)
1526 switch (dport
->port
) {
1528 port_mask
= DPLL_PORTB_READY_MASK
;
1531 port_mask
= DPLL_PORTC_READY_MASK
;
1537 if (wait_for((I915_READ(DPLL(0)) & port_mask
) == 0, 1000))
1538 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1539 port_name(dport
->port
), I915_READ(DPLL(0)));
1543 * ironlake_enable_shared_dpll - enable PCH PLL
1544 * @dev_priv: i915 private structure
1545 * @pipe: pipe PLL to enable
1547 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1548 * drives the transcoder clock.
1550 static void ironlake_enable_shared_dpll(struct intel_crtc
*crtc
)
1552 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1553 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1555 /* PCH PLLs only available on ILK, SNB and IVB */
1556 BUG_ON(dev_priv
->info
->gen
< 5);
1557 if (WARN_ON(pll
== NULL
))
1560 if (WARN_ON(pll
->refcount
== 0))
1563 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1564 pll
->name
, pll
->active
, pll
->on
,
1565 crtc
->base
.base
.id
);
1567 if (pll
->active
++) {
1569 assert_shared_dpll_enabled(dev_priv
, pll
);
1574 DRM_DEBUG_KMS("enabling %s\n", pll
->name
);
1575 pll
->enable(dev_priv
, pll
);
1579 static void intel_disable_shared_dpll(struct intel_crtc
*crtc
)
1581 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1582 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1584 /* PCH only available on ILK+ */
1585 BUG_ON(dev_priv
->info
->gen
< 5);
1586 if (WARN_ON(pll
== NULL
))
1589 if (WARN_ON(pll
->refcount
== 0))
1592 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1593 pll
->name
, pll
->active
, pll
->on
,
1594 crtc
->base
.base
.id
);
1596 if (WARN_ON(pll
->active
== 0)) {
1597 assert_shared_dpll_disabled(dev_priv
, pll
);
1601 assert_shared_dpll_enabled(dev_priv
, pll
);
1606 DRM_DEBUG_KMS("disabling %s\n", pll
->name
);
1607 pll
->disable(dev_priv
, pll
);
1611 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1614 struct drm_device
*dev
= dev_priv
->dev
;
1615 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1616 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1617 uint32_t reg
, val
, pipeconf_val
;
1619 /* PCH only available on ILK+ */
1620 BUG_ON(dev_priv
->info
->gen
< 5);
1622 /* Make sure PCH DPLL is enabled */
1623 assert_shared_dpll_enabled(dev_priv
,
1624 intel_crtc_to_shared_dpll(intel_crtc
));
1626 /* FDI must be feeding us bits for PCH ports */
1627 assert_fdi_tx_enabled(dev_priv
, pipe
);
1628 assert_fdi_rx_enabled(dev_priv
, pipe
);
1630 if (HAS_PCH_CPT(dev
)) {
1631 /* Workaround: Set the timing override bit before enabling the
1632 * pch transcoder. */
1633 reg
= TRANS_CHICKEN2(pipe
);
1634 val
= I915_READ(reg
);
1635 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1636 I915_WRITE(reg
, val
);
1639 reg
= PCH_TRANSCONF(pipe
);
1640 val
= I915_READ(reg
);
1641 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1643 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1645 * make the BPC in transcoder be consistent with
1646 * that in pipeconf reg.
1648 val
&= ~PIPECONF_BPC_MASK
;
1649 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1652 val
&= ~TRANS_INTERLACE_MASK
;
1653 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1654 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1655 intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
))
1656 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1658 val
|= TRANS_INTERLACED
;
1660 val
|= TRANS_PROGRESSIVE
;
1662 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1663 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1664 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
1667 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1668 enum transcoder cpu_transcoder
)
1670 u32 val
, pipeconf_val
;
1672 /* PCH only available on ILK+ */
1673 BUG_ON(dev_priv
->info
->gen
< 5);
1675 /* FDI must be feeding us bits for PCH ports */
1676 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1677 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
1679 /* Workaround: set timing override bit. */
1680 val
= I915_READ(_TRANSA_CHICKEN2
);
1681 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1682 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1685 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1687 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1688 PIPECONF_INTERLACED_ILK
)
1689 val
|= TRANS_INTERLACED
;
1691 val
|= TRANS_PROGRESSIVE
;
1693 I915_WRITE(LPT_TRANSCONF
, val
);
1694 if (wait_for(I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
, 100))
1695 DRM_ERROR("Failed to enable PCH transcoder\n");
1698 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1701 struct drm_device
*dev
= dev_priv
->dev
;
1704 /* FDI relies on the transcoder */
1705 assert_fdi_tx_disabled(dev_priv
, pipe
);
1706 assert_fdi_rx_disabled(dev_priv
, pipe
);
1708 /* Ports must be off as well */
1709 assert_pch_ports_disabled(dev_priv
, pipe
);
1711 reg
= PCH_TRANSCONF(pipe
);
1712 val
= I915_READ(reg
);
1713 val
&= ~TRANS_ENABLE
;
1714 I915_WRITE(reg
, val
);
1715 /* wait for PCH transcoder off, transcoder state */
1716 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1717 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
1719 if (!HAS_PCH_IBX(dev
)) {
1720 /* Workaround: Clear the timing override chicken bit again. */
1721 reg
= TRANS_CHICKEN2(pipe
);
1722 val
= I915_READ(reg
);
1723 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1724 I915_WRITE(reg
, val
);
1728 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1732 val
= I915_READ(LPT_TRANSCONF
);
1733 val
&= ~TRANS_ENABLE
;
1734 I915_WRITE(LPT_TRANSCONF
, val
);
1735 /* wait for PCH transcoder off, transcoder state */
1736 if (wait_for((I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
) == 0, 50))
1737 DRM_ERROR("Failed to disable PCH transcoder\n");
1739 /* Workaround: clear timing override bit. */
1740 val
= I915_READ(_TRANSA_CHICKEN2
);
1741 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1742 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1746 * intel_enable_pipe - enable a pipe, asserting requirements
1747 * @dev_priv: i915 private structure
1748 * @pipe: pipe to enable
1749 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1751 * Enable @pipe, making sure that various hardware specific requirements
1752 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1754 * @pipe should be %PIPE_A or %PIPE_B.
1756 * Will wait until the pipe is actually running (i.e. first vblank) before
1759 static void intel_enable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
1760 bool pch_port
, bool dsi
)
1762 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1764 enum pipe pch_transcoder
;
1768 assert_planes_disabled(dev_priv
, pipe
);
1769 assert_cursor_disabled(dev_priv
, pipe
);
1770 assert_sprites_disabled(dev_priv
, pipe
);
1772 if (HAS_PCH_LPT(dev_priv
->dev
))
1773 pch_transcoder
= TRANSCODER_A
;
1775 pch_transcoder
= pipe
;
1778 * A pipe without a PLL won't actually be able to drive bits from
1779 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1782 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
1784 assert_dsi_pll_enabled(dev_priv
);
1786 assert_pll_enabled(dev_priv
, pipe
);
1789 /* if driving the PCH, we need FDI enabled */
1790 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
1791 assert_fdi_tx_pll_enabled(dev_priv
,
1792 (enum pipe
) cpu_transcoder
);
1794 /* FIXME: assert CPU port conditions for SNB+ */
1797 reg
= PIPECONF(cpu_transcoder
);
1798 val
= I915_READ(reg
);
1799 if (val
& PIPECONF_ENABLE
)
1802 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
1803 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1807 * intel_disable_pipe - disable a pipe, asserting requirements
1808 * @dev_priv: i915 private structure
1809 * @pipe: pipe to disable
1811 * Disable @pipe, making sure that various hardware specific requirements
1812 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1814 * @pipe should be %PIPE_A or %PIPE_B.
1816 * Will wait until the pipe has shut down before returning.
1818 static void intel_disable_pipe(struct drm_i915_private
*dev_priv
,
1821 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1827 * Make sure planes won't keep trying to pump pixels to us,
1828 * or we might hang the display.
1830 assert_planes_disabled(dev_priv
, pipe
);
1831 assert_cursor_disabled(dev_priv
, pipe
);
1832 assert_sprites_disabled(dev_priv
, pipe
);
1834 /* Don't disable pipe A or pipe A PLLs if needed */
1835 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1838 reg
= PIPECONF(cpu_transcoder
);
1839 val
= I915_READ(reg
);
1840 if ((val
& PIPECONF_ENABLE
) == 0)
1843 I915_WRITE(reg
, val
& ~PIPECONF_ENABLE
);
1844 intel_wait_for_pipe_off(dev_priv
->dev
, pipe
);
1848 * Plane regs are double buffered, going from enabled->disabled needs a
1849 * trigger in order to latch. The display address reg provides this.
1851 void intel_flush_primary_plane(struct drm_i915_private
*dev_priv
,
1854 u32 reg
= dev_priv
->info
->gen
>= 4 ? DSPSURF(plane
) : DSPADDR(plane
);
1856 I915_WRITE(reg
, I915_READ(reg
));
1861 * intel_enable_primary_plane - enable the primary plane on a given pipe
1862 * @dev_priv: i915 private structure
1863 * @plane: plane to enable
1864 * @pipe: pipe being fed
1866 * Enable @plane on @pipe, making sure that @pipe is running first.
1868 static void intel_enable_primary_plane(struct drm_i915_private
*dev_priv
,
1869 enum plane plane
, enum pipe pipe
)
1871 struct intel_crtc
*intel_crtc
=
1872 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
1876 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1877 assert_pipe_enabled(dev_priv
, pipe
);
1879 WARN(intel_crtc
->primary_enabled
, "Primary plane already enabled\n");
1881 intel_crtc
->primary_enabled
= true;
1883 reg
= DSPCNTR(plane
);
1884 val
= I915_READ(reg
);
1885 if (val
& DISPLAY_PLANE_ENABLE
)
1888 I915_WRITE(reg
, val
| DISPLAY_PLANE_ENABLE
);
1889 intel_flush_primary_plane(dev_priv
, plane
);
1890 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1894 * intel_disable_primary_plane - disable the primary plane
1895 * @dev_priv: i915 private structure
1896 * @plane: plane to disable
1897 * @pipe: pipe consuming the data
1899 * Disable @plane; should be an independent operation.
1901 static void intel_disable_primary_plane(struct drm_i915_private
*dev_priv
,
1902 enum plane plane
, enum pipe pipe
)
1904 struct intel_crtc
*intel_crtc
=
1905 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
1909 WARN(!intel_crtc
->primary_enabled
, "Primary plane already disabled\n");
1911 intel_crtc
->primary_enabled
= false;
1913 reg
= DSPCNTR(plane
);
1914 val
= I915_READ(reg
);
1915 if ((val
& DISPLAY_PLANE_ENABLE
) == 0)
1918 I915_WRITE(reg
, val
& ~DISPLAY_PLANE_ENABLE
);
1919 intel_flush_primary_plane(dev_priv
, plane
);
1920 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1923 static bool need_vtd_wa(struct drm_device
*dev
)
1925 #ifdef CONFIG_INTEL_IOMMU
1926 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
1933 intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
1934 struct drm_i915_gem_object
*obj
,
1935 struct intel_ring_buffer
*pipelined
)
1937 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1941 switch (obj
->tiling_mode
) {
1942 case I915_TILING_NONE
:
1943 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
1944 alignment
= 128 * 1024;
1945 else if (INTEL_INFO(dev
)->gen
>= 4)
1946 alignment
= 4 * 1024;
1948 alignment
= 64 * 1024;
1951 /* pin() will align the object as required by fence */
1955 WARN(1, "Y tiled bo slipped through, driver bug!\n");
1961 /* Note that the w/a also requires 64 PTE of padding following the
1962 * bo. We currently fill all unused PTE with the shadow page and so
1963 * we should always have valid PTE following the scanout preventing
1966 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
1967 alignment
= 256 * 1024;
1969 dev_priv
->mm
.interruptible
= false;
1970 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
);
1972 goto err_interruptible
;
1974 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1975 * fence, whereas 965+ only requires a fence if using
1976 * framebuffer compression. For simplicity, we always install
1977 * a fence as the cost is not that onerous.
1979 ret
= i915_gem_object_get_fence(obj
);
1983 i915_gem_object_pin_fence(obj
);
1985 dev_priv
->mm
.interruptible
= true;
1989 i915_gem_object_unpin_from_display_plane(obj
);
1991 dev_priv
->mm
.interruptible
= true;
1995 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
)
1997 i915_gem_object_unpin_fence(obj
);
1998 i915_gem_object_unpin_from_display_plane(obj
);
2001 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2002 * is assumed to be a power-of-two. */
2003 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
2004 unsigned int tiling_mode
,
2008 if (tiling_mode
!= I915_TILING_NONE
) {
2009 unsigned int tile_rows
, tiles
;
2014 tiles
= *x
/ (512/cpp
);
2017 return tile_rows
* pitch
* 8 + tiles
* 4096;
2019 unsigned int offset
;
2021 offset
= *y
* pitch
+ *x
* cpp
;
2023 *x
= (offset
& 4095) / cpp
;
2024 return offset
& -4096;
2028 static int i9xx_update_plane(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2031 struct drm_device
*dev
= crtc
->dev
;
2032 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2033 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2034 struct intel_framebuffer
*intel_fb
;
2035 struct drm_i915_gem_object
*obj
;
2036 int plane
= intel_crtc
->plane
;
2037 unsigned long linear_offset
;
2046 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane
));
2050 intel_fb
= to_intel_framebuffer(fb
);
2051 obj
= intel_fb
->obj
;
2053 reg
= DSPCNTR(plane
);
2054 dspcntr
= I915_READ(reg
);
2055 /* Mask out pixel format bits in case we change it */
2056 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2057 switch (fb
->pixel_format
) {
2059 dspcntr
|= DISPPLANE_8BPP
;
2061 case DRM_FORMAT_XRGB1555
:
2062 case DRM_FORMAT_ARGB1555
:
2063 dspcntr
|= DISPPLANE_BGRX555
;
2065 case DRM_FORMAT_RGB565
:
2066 dspcntr
|= DISPPLANE_BGRX565
;
2068 case DRM_FORMAT_XRGB8888
:
2069 case DRM_FORMAT_ARGB8888
:
2070 dspcntr
|= DISPPLANE_BGRX888
;
2072 case DRM_FORMAT_XBGR8888
:
2073 case DRM_FORMAT_ABGR8888
:
2074 dspcntr
|= DISPPLANE_RGBX888
;
2076 case DRM_FORMAT_XRGB2101010
:
2077 case DRM_FORMAT_ARGB2101010
:
2078 dspcntr
|= DISPPLANE_BGRX101010
;
2080 case DRM_FORMAT_XBGR2101010
:
2081 case DRM_FORMAT_ABGR2101010
:
2082 dspcntr
|= DISPPLANE_RGBX101010
;
2088 if (INTEL_INFO(dev
)->gen
>= 4) {
2089 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2090 dspcntr
|= DISPPLANE_TILED
;
2092 dspcntr
&= ~DISPPLANE_TILED
;
2096 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2098 I915_WRITE(reg
, dspcntr
);
2100 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2102 if (INTEL_INFO(dev
)->gen
>= 4) {
2103 intel_crtc
->dspaddr_offset
=
2104 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2105 fb
->bits_per_pixel
/ 8,
2107 linear_offset
-= intel_crtc
->dspaddr_offset
;
2109 intel_crtc
->dspaddr_offset
= linear_offset
;
2112 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2113 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2115 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2116 if (INTEL_INFO(dev
)->gen
>= 4) {
2117 I915_WRITE(DSPSURF(plane
),
2118 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2119 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2120 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2122 I915_WRITE(DSPADDR(plane
), i915_gem_obj_ggtt_offset(obj
) + linear_offset
);
2128 static int ironlake_update_plane(struct drm_crtc
*crtc
,
2129 struct drm_framebuffer
*fb
, int x
, int y
)
2131 struct drm_device
*dev
= crtc
->dev
;
2132 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2133 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2134 struct intel_framebuffer
*intel_fb
;
2135 struct drm_i915_gem_object
*obj
;
2136 int plane
= intel_crtc
->plane
;
2137 unsigned long linear_offset
;
2147 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane
));
2151 intel_fb
= to_intel_framebuffer(fb
);
2152 obj
= intel_fb
->obj
;
2154 reg
= DSPCNTR(plane
);
2155 dspcntr
= I915_READ(reg
);
2156 /* Mask out pixel format bits in case we change it */
2157 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2158 switch (fb
->pixel_format
) {
2160 dspcntr
|= DISPPLANE_8BPP
;
2162 case DRM_FORMAT_RGB565
:
2163 dspcntr
|= DISPPLANE_BGRX565
;
2165 case DRM_FORMAT_XRGB8888
:
2166 case DRM_FORMAT_ARGB8888
:
2167 dspcntr
|= DISPPLANE_BGRX888
;
2169 case DRM_FORMAT_XBGR8888
:
2170 case DRM_FORMAT_ABGR8888
:
2171 dspcntr
|= DISPPLANE_RGBX888
;
2173 case DRM_FORMAT_XRGB2101010
:
2174 case DRM_FORMAT_ARGB2101010
:
2175 dspcntr
|= DISPPLANE_BGRX101010
;
2177 case DRM_FORMAT_XBGR2101010
:
2178 case DRM_FORMAT_ABGR2101010
:
2179 dspcntr
|= DISPPLANE_RGBX101010
;
2185 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2186 dspcntr
|= DISPPLANE_TILED
;
2188 dspcntr
&= ~DISPPLANE_TILED
;
2190 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2191 dspcntr
&= ~DISPPLANE_TRICKLE_FEED_DISABLE
;
2193 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2195 I915_WRITE(reg
, dspcntr
);
2197 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2198 intel_crtc
->dspaddr_offset
=
2199 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2200 fb
->bits_per_pixel
/ 8,
2202 linear_offset
-= intel_crtc
->dspaddr_offset
;
2204 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2205 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2207 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2208 I915_WRITE(DSPSURF(plane
),
2209 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2210 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2211 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2213 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2214 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2221 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2223 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2224 int x
, int y
, enum mode_set_atomic state
)
2226 struct drm_device
*dev
= crtc
->dev
;
2227 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2229 if (dev_priv
->display
.disable_fbc
)
2230 dev_priv
->display
.disable_fbc(dev
);
2231 intel_increase_pllclock(crtc
);
2233 return dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2236 void intel_display_handle_reset(struct drm_device
*dev
)
2238 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2239 struct drm_crtc
*crtc
;
2242 * Flips in the rings have been nuked by the reset,
2243 * so complete all pending flips so that user space
2244 * will get its events and not get stuck.
2246 * Also update the base address of all primary
2247 * planes to the the last fb to make sure we're
2248 * showing the correct fb after a reset.
2250 * Need to make two loops over the crtcs so that we
2251 * don't try to grab a crtc mutex before the
2252 * pending_flip_queue really got woken up.
2255 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2256 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2257 enum plane plane
= intel_crtc
->plane
;
2259 intel_prepare_page_flip(dev
, plane
);
2260 intel_finish_page_flip_plane(dev
, plane
);
2263 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2264 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2266 mutex_lock(&crtc
->mutex
);
2268 * FIXME: Once we have proper support for primary planes (and
2269 * disabling them without disabling the entire crtc) allow again
2272 if (intel_crtc
->active
&& crtc
->fb
)
2273 dev_priv
->display
.update_plane(crtc
, crtc
->fb
,
2275 mutex_unlock(&crtc
->mutex
);
2280 intel_finish_fb(struct drm_framebuffer
*old_fb
)
2282 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(old_fb
)->obj
;
2283 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2284 bool was_interruptible
= dev_priv
->mm
.interruptible
;
2287 /* Big Hammer, we also need to ensure that any pending
2288 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2289 * current scanout is retired before unpinning the old
2292 * This should only fail upon a hung GPU, in which case we
2293 * can safely continue.
2295 dev_priv
->mm
.interruptible
= false;
2296 ret
= i915_gem_object_finish_gpu(obj
);
2297 dev_priv
->mm
.interruptible
= was_interruptible
;
2302 static void intel_crtc_update_sarea_pos(struct drm_crtc
*crtc
, int x
, int y
)
2304 struct drm_device
*dev
= crtc
->dev
;
2305 struct drm_i915_master_private
*master_priv
;
2306 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2308 if (!dev
->primary
->master
)
2311 master_priv
= dev
->primary
->master
->driver_priv
;
2312 if (!master_priv
->sarea_priv
)
2315 switch (intel_crtc
->pipe
) {
2317 master_priv
->sarea_priv
->pipeA_x
= x
;
2318 master_priv
->sarea_priv
->pipeA_y
= y
;
2321 master_priv
->sarea_priv
->pipeB_x
= x
;
2322 master_priv
->sarea_priv
->pipeB_y
= y
;
2330 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2331 struct drm_framebuffer
*fb
)
2333 struct drm_device
*dev
= crtc
->dev
;
2334 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2335 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2336 struct drm_framebuffer
*old_fb
;
2341 DRM_ERROR("No FB bound\n");
2345 if (intel_crtc
->plane
> INTEL_INFO(dev
)->num_pipes
) {
2346 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2347 plane_name(intel_crtc
->plane
),
2348 INTEL_INFO(dev
)->num_pipes
);
2352 mutex_lock(&dev
->struct_mutex
);
2353 ret
= intel_pin_and_fence_fb_obj(dev
,
2354 to_intel_framebuffer(fb
)->obj
,
2357 mutex_unlock(&dev
->struct_mutex
);
2358 DRM_ERROR("pin & fence failed\n");
2363 * Update pipe size and adjust fitter if needed: the reason for this is
2364 * that in compute_mode_changes we check the native mode (not the pfit
2365 * mode) to see if we can flip rather than do a full mode set. In the
2366 * fastboot case, we'll flip, but if we don't update the pipesrc and
2367 * pfit state, we'll end up with a big fb scanned out into the wrong
2370 * To fix this properly, we need to hoist the checks up into
2371 * compute_mode_changes (or above), check the actual pfit state and
2372 * whether the platform allows pfit disable with pipe active, and only
2373 * then update the pipesrc and pfit state, even on the flip path.
2375 if (i915_fastboot
) {
2376 const struct drm_display_mode
*adjusted_mode
=
2377 &intel_crtc
->config
.adjusted_mode
;
2379 I915_WRITE(PIPESRC(intel_crtc
->pipe
),
2380 ((adjusted_mode
->crtc_hdisplay
- 1) << 16) |
2381 (adjusted_mode
->crtc_vdisplay
- 1));
2382 if (!intel_crtc
->config
.pch_pfit
.enabled
&&
2383 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) ||
2384 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
2385 I915_WRITE(PF_CTL(intel_crtc
->pipe
), 0);
2386 I915_WRITE(PF_WIN_POS(intel_crtc
->pipe
), 0);
2387 I915_WRITE(PF_WIN_SZ(intel_crtc
->pipe
), 0);
2389 intel_crtc
->config
.pipe_src_w
= adjusted_mode
->crtc_hdisplay
;
2390 intel_crtc
->config
.pipe_src_h
= adjusted_mode
->crtc_vdisplay
;
2393 ret
= dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2395 intel_unpin_fb_obj(to_intel_framebuffer(fb
)->obj
);
2396 mutex_unlock(&dev
->struct_mutex
);
2397 DRM_ERROR("failed to update base address\n");
2407 if (intel_crtc
->active
&& old_fb
!= fb
)
2408 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2409 intel_unpin_fb_obj(to_intel_framebuffer(old_fb
)->obj
);
2412 intel_update_fbc(dev
);
2413 intel_edp_psr_update(dev
);
2414 mutex_unlock(&dev
->struct_mutex
);
2416 intel_crtc_update_sarea_pos(crtc
, x
, y
);
2421 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
2423 struct drm_device
*dev
= crtc
->dev
;
2424 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2425 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2426 int pipe
= intel_crtc
->pipe
;
2429 /* enable normal train */
2430 reg
= FDI_TX_CTL(pipe
);
2431 temp
= I915_READ(reg
);
2432 if (IS_IVYBRIDGE(dev
)) {
2433 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2434 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2436 temp
&= ~FDI_LINK_TRAIN_NONE
;
2437 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2439 I915_WRITE(reg
, temp
);
2441 reg
= FDI_RX_CTL(pipe
);
2442 temp
= I915_READ(reg
);
2443 if (HAS_PCH_CPT(dev
)) {
2444 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2445 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2447 temp
&= ~FDI_LINK_TRAIN_NONE
;
2448 temp
|= FDI_LINK_TRAIN_NONE
;
2450 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2452 /* wait one idle pattern time */
2456 /* IVB wants error correction enabled */
2457 if (IS_IVYBRIDGE(dev
))
2458 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
2459 FDI_FE_ERRC_ENABLE
);
2462 static bool pipe_has_enabled_pch(struct intel_crtc
*crtc
)
2464 return crtc
->base
.enabled
&& crtc
->active
&&
2465 crtc
->config
.has_pch_encoder
;
2468 static void ivb_modeset_global_resources(struct drm_device
*dev
)
2470 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2471 struct intel_crtc
*pipe_B_crtc
=
2472 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
2473 struct intel_crtc
*pipe_C_crtc
=
2474 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]);
2478 * When everything is off disable fdi C so that we could enable fdi B
2479 * with all lanes. Note that we don't care about enabled pipes without
2480 * an enabled pch encoder.
2482 if (!pipe_has_enabled_pch(pipe_B_crtc
) &&
2483 !pipe_has_enabled_pch(pipe_C_crtc
)) {
2484 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
2485 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
2487 temp
= I915_READ(SOUTH_CHICKEN1
);
2488 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
2489 DRM_DEBUG_KMS("disabling fdi C rx\n");
2490 I915_WRITE(SOUTH_CHICKEN1
, temp
);
2494 /* The FDI link training functions for ILK/Ibexpeak. */
2495 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
2497 struct drm_device
*dev
= crtc
->dev
;
2498 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2499 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2500 int pipe
= intel_crtc
->pipe
;
2501 int plane
= intel_crtc
->plane
;
2502 u32 reg
, temp
, tries
;
2504 /* FDI needs bits from pipe & plane first */
2505 assert_pipe_enabled(dev_priv
, pipe
);
2506 assert_plane_enabled(dev_priv
, plane
);
2508 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2510 reg
= FDI_RX_IMR(pipe
);
2511 temp
= I915_READ(reg
);
2512 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2513 temp
&= ~FDI_RX_BIT_LOCK
;
2514 I915_WRITE(reg
, temp
);
2518 /* enable CPU FDI TX and PCH FDI RX */
2519 reg
= FDI_TX_CTL(pipe
);
2520 temp
= I915_READ(reg
);
2521 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2522 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2523 temp
&= ~FDI_LINK_TRAIN_NONE
;
2524 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2525 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2527 reg
= FDI_RX_CTL(pipe
);
2528 temp
= I915_READ(reg
);
2529 temp
&= ~FDI_LINK_TRAIN_NONE
;
2530 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2531 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2536 /* Ironlake workaround, enable clock pointer after FDI enable*/
2537 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2538 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
2539 FDI_RX_PHASE_SYNC_POINTER_EN
);
2541 reg
= FDI_RX_IIR(pipe
);
2542 for (tries
= 0; tries
< 5; tries
++) {
2543 temp
= I915_READ(reg
);
2544 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2546 if ((temp
& FDI_RX_BIT_LOCK
)) {
2547 DRM_DEBUG_KMS("FDI train 1 done.\n");
2548 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2553 DRM_ERROR("FDI train 1 fail!\n");
2556 reg
= FDI_TX_CTL(pipe
);
2557 temp
= I915_READ(reg
);
2558 temp
&= ~FDI_LINK_TRAIN_NONE
;
2559 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2560 I915_WRITE(reg
, temp
);
2562 reg
= FDI_RX_CTL(pipe
);
2563 temp
= I915_READ(reg
);
2564 temp
&= ~FDI_LINK_TRAIN_NONE
;
2565 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2566 I915_WRITE(reg
, temp
);
2571 reg
= FDI_RX_IIR(pipe
);
2572 for (tries
= 0; tries
< 5; tries
++) {
2573 temp
= I915_READ(reg
);
2574 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2576 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2577 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2578 DRM_DEBUG_KMS("FDI train 2 done.\n");
2583 DRM_ERROR("FDI train 2 fail!\n");
2585 DRM_DEBUG_KMS("FDI train done\n");
2589 static const int snb_b_fdi_train_param
[] = {
2590 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
2591 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
2592 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
2593 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
2596 /* The FDI link training functions for SNB/Cougarpoint. */
2597 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
2599 struct drm_device
*dev
= crtc
->dev
;
2600 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2601 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2602 int pipe
= intel_crtc
->pipe
;
2603 u32 reg
, temp
, i
, retry
;
2605 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2607 reg
= FDI_RX_IMR(pipe
);
2608 temp
= I915_READ(reg
);
2609 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2610 temp
&= ~FDI_RX_BIT_LOCK
;
2611 I915_WRITE(reg
, temp
);
2616 /* enable CPU FDI TX and PCH FDI RX */
2617 reg
= FDI_TX_CTL(pipe
);
2618 temp
= I915_READ(reg
);
2619 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2620 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2621 temp
&= ~FDI_LINK_TRAIN_NONE
;
2622 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2623 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2625 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2626 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2628 I915_WRITE(FDI_RX_MISC(pipe
),
2629 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2631 reg
= FDI_RX_CTL(pipe
);
2632 temp
= I915_READ(reg
);
2633 if (HAS_PCH_CPT(dev
)) {
2634 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2635 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2637 temp
&= ~FDI_LINK_TRAIN_NONE
;
2638 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2640 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2645 for (i
= 0; i
< 4; i
++) {
2646 reg
= FDI_TX_CTL(pipe
);
2647 temp
= I915_READ(reg
);
2648 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2649 temp
|= snb_b_fdi_train_param
[i
];
2650 I915_WRITE(reg
, temp
);
2655 for (retry
= 0; retry
< 5; retry
++) {
2656 reg
= FDI_RX_IIR(pipe
);
2657 temp
= I915_READ(reg
);
2658 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2659 if (temp
& FDI_RX_BIT_LOCK
) {
2660 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2661 DRM_DEBUG_KMS("FDI train 1 done.\n");
2670 DRM_ERROR("FDI train 1 fail!\n");
2673 reg
= FDI_TX_CTL(pipe
);
2674 temp
= I915_READ(reg
);
2675 temp
&= ~FDI_LINK_TRAIN_NONE
;
2676 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2678 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2680 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2682 I915_WRITE(reg
, temp
);
2684 reg
= FDI_RX_CTL(pipe
);
2685 temp
= I915_READ(reg
);
2686 if (HAS_PCH_CPT(dev
)) {
2687 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2688 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2690 temp
&= ~FDI_LINK_TRAIN_NONE
;
2691 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2693 I915_WRITE(reg
, temp
);
2698 for (i
= 0; i
< 4; i
++) {
2699 reg
= FDI_TX_CTL(pipe
);
2700 temp
= I915_READ(reg
);
2701 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2702 temp
|= snb_b_fdi_train_param
[i
];
2703 I915_WRITE(reg
, temp
);
2708 for (retry
= 0; retry
< 5; retry
++) {
2709 reg
= FDI_RX_IIR(pipe
);
2710 temp
= I915_READ(reg
);
2711 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2712 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2713 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2714 DRM_DEBUG_KMS("FDI train 2 done.\n");
2723 DRM_ERROR("FDI train 2 fail!\n");
2725 DRM_DEBUG_KMS("FDI train done.\n");
2728 /* Manual link training for Ivy Bridge A0 parts */
2729 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
2731 struct drm_device
*dev
= crtc
->dev
;
2732 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2733 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2734 int pipe
= intel_crtc
->pipe
;
2735 u32 reg
, temp
, i
, j
;
2737 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2739 reg
= FDI_RX_IMR(pipe
);
2740 temp
= I915_READ(reg
);
2741 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2742 temp
&= ~FDI_RX_BIT_LOCK
;
2743 I915_WRITE(reg
, temp
);
2748 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2749 I915_READ(FDI_RX_IIR(pipe
)));
2751 /* Try each vswing and preemphasis setting twice before moving on */
2752 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
2753 /* disable first in case we need to retry */
2754 reg
= FDI_TX_CTL(pipe
);
2755 temp
= I915_READ(reg
);
2756 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
2757 temp
&= ~FDI_TX_ENABLE
;
2758 I915_WRITE(reg
, temp
);
2760 reg
= FDI_RX_CTL(pipe
);
2761 temp
= I915_READ(reg
);
2762 temp
&= ~FDI_LINK_TRAIN_AUTO
;
2763 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2764 temp
&= ~FDI_RX_ENABLE
;
2765 I915_WRITE(reg
, temp
);
2767 /* enable CPU FDI TX and PCH FDI RX */
2768 reg
= FDI_TX_CTL(pipe
);
2769 temp
= I915_READ(reg
);
2770 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2771 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2772 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
2773 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2774 temp
|= snb_b_fdi_train_param
[j
/2];
2775 temp
|= FDI_COMPOSITE_SYNC
;
2776 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2778 I915_WRITE(FDI_RX_MISC(pipe
),
2779 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2781 reg
= FDI_RX_CTL(pipe
);
2782 temp
= I915_READ(reg
);
2783 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2784 temp
|= FDI_COMPOSITE_SYNC
;
2785 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2788 udelay(1); /* should be 0.5us */
2790 for (i
= 0; i
< 4; i
++) {
2791 reg
= FDI_RX_IIR(pipe
);
2792 temp
= I915_READ(reg
);
2793 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2795 if (temp
& FDI_RX_BIT_LOCK
||
2796 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
2797 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2798 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2802 udelay(1); /* should be 0.5us */
2805 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
2810 reg
= FDI_TX_CTL(pipe
);
2811 temp
= I915_READ(reg
);
2812 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2813 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
2814 I915_WRITE(reg
, temp
);
2816 reg
= FDI_RX_CTL(pipe
);
2817 temp
= I915_READ(reg
);
2818 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2819 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2820 I915_WRITE(reg
, temp
);
2823 udelay(2); /* should be 1.5us */
2825 for (i
= 0; i
< 4; i
++) {
2826 reg
= FDI_RX_IIR(pipe
);
2827 temp
= I915_READ(reg
);
2828 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2830 if (temp
& FDI_RX_SYMBOL_LOCK
||
2831 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
2832 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2833 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2837 udelay(2); /* should be 1.5us */
2840 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
2844 DRM_DEBUG_KMS("FDI train done.\n");
2847 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
2849 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2850 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2851 int pipe
= intel_crtc
->pipe
;
2855 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2856 reg
= FDI_RX_CTL(pipe
);
2857 temp
= I915_READ(reg
);
2858 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
2859 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2860 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2861 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
2866 /* Switch from Rawclk to PCDclk */
2867 temp
= I915_READ(reg
);
2868 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
2873 /* Enable CPU FDI TX PLL, always on for Ironlake */
2874 reg
= FDI_TX_CTL(pipe
);
2875 temp
= I915_READ(reg
);
2876 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
2877 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
2884 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
2886 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2887 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2888 int pipe
= intel_crtc
->pipe
;
2891 /* Switch from PCDclk to Rawclk */
2892 reg
= FDI_RX_CTL(pipe
);
2893 temp
= I915_READ(reg
);
2894 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
2896 /* Disable CPU FDI TX PLL */
2897 reg
= FDI_TX_CTL(pipe
);
2898 temp
= I915_READ(reg
);
2899 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
2904 reg
= FDI_RX_CTL(pipe
);
2905 temp
= I915_READ(reg
);
2906 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
2908 /* Wait for the clocks to turn off. */
2913 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
2915 struct drm_device
*dev
= crtc
->dev
;
2916 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2917 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2918 int pipe
= intel_crtc
->pipe
;
2921 /* disable CPU FDI tx and PCH FDI rx */
2922 reg
= FDI_TX_CTL(pipe
);
2923 temp
= I915_READ(reg
);
2924 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
2927 reg
= FDI_RX_CTL(pipe
);
2928 temp
= I915_READ(reg
);
2929 temp
&= ~(0x7 << 16);
2930 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2931 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
2936 /* Ironlake workaround, disable clock pointer after downing FDI */
2937 if (HAS_PCH_IBX(dev
)) {
2938 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2941 /* still set train pattern 1 */
2942 reg
= FDI_TX_CTL(pipe
);
2943 temp
= I915_READ(reg
);
2944 temp
&= ~FDI_LINK_TRAIN_NONE
;
2945 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2946 I915_WRITE(reg
, temp
);
2948 reg
= FDI_RX_CTL(pipe
);
2949 temp
= I915_READ(reg
);
2950 if (HAS_PCH_CPT(dev
)) {
2951 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2952 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2954 temp
&= ~FDI_LINK_TRAIN_NONE
;
2955 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2957 /* BPC in FDI rx is consistent with that in PIPECONF */
2958 temp
&= ~(0x07 << 16);
2959 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2960 I915_WRITE(reg
, temp
);
2966 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
2968 struct drm_device
*dev
= crtc
->dev
;
2969 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2970 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2971 unsigned long flags
;
2974 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
2975 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
2978 spin_lock_irqsave(&dev
->event_lock
, flags
);
2979 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
2980 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2985 bool intel_has_pending_fb_unpin(struct drm_device
*dev
)
2987 struct intel_crtc
*crtc
;
2989 /* Note that we don't need to be called with mode_config.lock here
2990 * as our list of CRTC objects is static for the lifetime of the
2991 * device and so cannot disappear as we iterate. Similarly, we can
2992 * happily treat the predicates as racy, atomic checks as userspace
2993 * cannot claim and pin a new fb without at least acquring the
2994 * struct_mutex and so serialising with us.
2996 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
2997 if (atomic_read(&crtc
->unpin_work_count
) == 0)
3000 if (crtc
->unpin_work
)
3001 intel_wait_for_vblank(dev
, crtc
->pipe
);
3009 static void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
3011 struct drm_device
*dev
= crtc
->dev
;
3012 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3014 if (crtc
->fb
== NULL
)
3017 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
3019 wait_event(dev_priv
->pending_flip_queue
,
3020 !intel_crtc_has_pending_flip(crtc
));
3022 mutex_lock(&dev
->struct_mutex
);
3023 intel_finish_fb(crtc
->fb
);
3024 mutex_unlock(&dev
->struct_mutex
);
3027 /* Program iCLKIP clock to the desired frequency */
3028 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
3030 struct drm_device
*dev
= crtc
->dev
;
3031 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3032 int clock
= to_intel_crtc(crtc
)->config
.adjusted_mode
.crtc_clock
;
3033 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
3036 mutex_lock(&dev_priv
->dpio_lock
);
3038 /* It is necessary to ungate the pixclk gate prior to programming
3039 * the divisors, and gate it back when it is done.
3041 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
3043 /* Disable SSCCTL */
3044 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
3045 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
3049 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3050 if (clock
== 20000) {
3055 /* The iCLK virtual clock root frequency is in MHz,
3056 * but the adjusted_mode->crtc_clock in in KHz. To get the
3057 * divisors, it is necessary to divide one by another, so we
3058 * convert the virtual clock precision to KHz here for higher
3061 u32 iclk_virtual_root_freq
= 172800 * 1000;
3062 u32 iclk_pi_range
= 64;
3063 u32 desired_divisor
, msb_divisor_value
, pi_value
;
3065 desired_divisor
= (iclk_virtual_root_freq
/ clock
);
3066 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
3067 pi_value
= desired_divisor
% iclk_pi_range
;
3070 divsel
= msb_divisor_value
- 2;
3071 phaseinc
= pi_value
;
3074 /* This should not happen with any sane values */
3075 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
3076 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
3077 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
3078 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
3080 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3087 /* Program SSCDIVINTPHASE6 */
3088 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
3089 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
3090 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
3091 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
3092 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
3093 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
3094 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
3095 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
3097 /* Program SSCAUXDIV */
3098 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
3099 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3100 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
3101 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
3103 /* Enable modulator and associated divider */
3104 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
3105 temp
&= ~SBI_SSCCTL_DISABLE
;
3106 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
3108 /* Wait for initialization time */
3111 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
3113 mutex_unlock(&dev_priv
->dpio_lock
);
3116 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
3117 enum pipe pch_transcoder
)
3119 struct drm_device
*dev
= crtc
->base
.dev
;
3120 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3121 enum transcoder cpu_transcoder
= crtc
->config
.cpu_transcoder
;
3123 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
3124 I915_READ(HTOTAL(cpu_transcoder
)));
3125 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
3126 I915_READ(HBLANK(cpu_transcoder
)));
3127 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
3128 I915_READ(HSYNC(cpu_transcoder
)));
3130 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
3131 I915_READ(VTOTAL(cpu_transcoder
)));
3132 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
3133 I915_READ(VBLANK(cpu_transcoder
)));
3134 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
3135 I915_READ(VSYNC(cpu_transcoder
)));
3136 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
3137 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
3140 static void cpt_enable_fdi_bc_bifurcation(struct drm_device
*dev
)
3142 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3145 temp
= I915_READ(SOUTH_CHICKEN1
);
3146 if (temp
& FDI_BC_BIFURCATION_SELECT
)
3149 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
3150 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
3152 temp
|= FDI_BC_BIFURCATION_SELECT
;
3153 DRM_DEBUG_KMS("enabling fdi C rx\n");
3154 I915_WRITE(SOUTH_CHICKEN1
, temp
);
3155 POSTING_READ(SOUTH_CHICKEN1
);
3158 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
3160 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3161 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3163 switch (intel_crtc
->pipe
) {
3167 if (intel_crtc
->config
.fdi_lanes
> 2)
3168 WARN_ON(I915_READ(SOUTH_CHICKEN1
) & FDI_BC_BIFURCATION_SELECT
);
3170 cpt_enable_fdi_bc_bifurcation(dev
);
3174 cpt_enable_fdi_bc_bifurcation(dev
);
3183 * Enable PCH resources required for PCH ports:
3185 * - FDI training & RX/TX
3186 * - update transcoder timings
3187 * - DP transcoding bits
3190 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
3192 struct drm_device
*dev
= crtc
->dev
;
3193 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3194 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3195 int pipe
= intel_crtc
->pipe
;
3198 assert_pch_transcoder_disabled(dev_priv
, pipe
);
3200 if (IS_IVYBRIDGE(dev
))
3201 ivybridge_update_fdi_bc_bifurcation(intel_crtc
);
3203 /* Write the TU size bits before fdi link training, so that error
3204 * detection works. */
3205 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
3206 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
3208 /* For PCH output, training FDI link */
3209 dev_priv
->display
.fdi_link_train(crtc
);
3211 /* We need to program the right clock selection before writing the pixel
3212 * mutliplier into the DPLL. */
3213 if (HAS_PCH_CPT(dev
)) {
3216 temp
= I915_READ(PCH_DPLL_SEL
);
3217 temp
|= TRANS_DPLL_ENABLE(pipe
);
3218 sel
= TRANS_DPLLB_SEL(pipe
);
3219 if (intel_crtc
->config
.shared_dpll
== DPLL_ID_PCH_PLL_B
)
3223 I915_WRITE(PCH_DPLL_SEL
, temp
);
3226 /* XXX: pch pll's can be enabled any time before we enable the PCH
3227 * transcoder, and we actually should do this to not upset any PCH
3228 * transcoder that already use the clock when we share it.
3230 * Note that enable_shared_dpll tries to do the right thing, but
3231 * get_shared_dpll unconditionally resets the pll - we need that to have
3232 * the right LVDS enable sequence. */
3233 ironlake_enable_shared_dpll(intel_crtc
);
3235 /* set transcoder timing, panel must allow it */
3236 assert_panel_unlocked(dev_priv
, pipe
);
3237 ironlake_pch_transcoder_set_timings(intel_crtc
, pipe
);
3239 intel_fdi_normal_train(crtc
);
3241 /* For PCH DP, enable TRANS_DP_CTL */
3242 if (HAS_PCH_CPT(dev
) &&
3243 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
3244 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3245 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
3246 reg
= TRANS_DP_CTL(pipe
);
3247 temp
= I915_READ(reg
);
3248 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
3249 TRANS_DP_SYNC_MASK
|
3251 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
3252 TRANS_DP_ENH_FRAMING
);
3253 temp
|= bpc
<< 9; /* same format but at 11:9 */
3255 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
3256 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
3257 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
3258 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
3260 switch (intel_trans_dp_port_sel(crtc
)) {
3262 temp
|= TRANS_DP_PORT_SEL_B
;
3265 temp
|= TRANS_DP_PORT_SEL_C
;
3268 temp
|= TRANS_DP_PORT_SEL_D
;
3274 I915_WRITE(reg
, temp
);
3277 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
3280 static void lpt_pch_enable(struct drm_crtc
*crtc
)
3282 struct drm_device
*dev
= crtc
->dev
;
3283 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3284 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3285 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
3287 assert_pch_transcoder_disabled(dev_priv
, TRANSCODER_A
);
3289 lpt_program_iclkip(crtc
);
3291 /* Set transcoder timing. */
3292 ironlake_pch_transcoder_set_timings(intel_crtc
, PIPE_A
);
3294 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
3297 static void intel_put_shared_dpll(struct intel_crtc
*crtc
)
3299 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3304 if (pll
->refcount
== 0) {
3305 WARN(1, "bad %s refcount\n", pll
->name
);
3309 if (--pll
->refcount
== 0) {
3311 WARN_ON(pll
->active
);
3314 crtc
->config
.shared_dpll
= DPLL_ID_PRIVATE
;
3317 static struct intel_shared_dpll
*intel_get_shared_dpll(struct intel_crtc
*crtc
)
3319 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
3320 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3321 enum intel_dpll_id i
;
3324 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3325 crtc
->base
.base
.id
, pll
->name
);
3326 intel_put_shared_dpll(crtc
);
3329 if (HAS_PCH_IBX(dev_priv
->dev
)) {
3330 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3331 i
= (enum intel_dpll_id
) crtc
->pipe
;
3332 pll
= &dev_priv
->shared_dplls
[i
];
3334 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3335 crtc
->base
.base
.id
, pll
->name
);
3340 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3341 pll
= &dev_priv
->shared_dplls
[i
];
3343 /* Only want to check enabled timings first */
3344 if (pll
->refcount
== 0)
3347 if (memcmp(&crtc
->config
.dpll_hw_state
, &pll
->hw_state
,
3348 sizeof(pll
->hw_state
)) == 0) {
3349 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3351 pll
->name
, pll
->refcount
, pll
->active
);
3357 /* Ok no matching timings, maybe there's a free one? */
3358 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3359 pll
= &dev_priv
->shared_dplls
[i
];
3360 if (pll
->refcount
== 0) {
3361 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3362 crtc
->base
.base
.id
, pll
->name
);
3370 crtc
->config
.shared_dpll
= i
;
3371 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll
->name
,
3372 pipe_name(crtc
->pipe
));
3374 if (pll
->active
== 0) {
3375 memcpy(&pll
->hw_state
, &crtc
->config
.dpll_hw_state
,
3376 sizeof(pll
->hw_state
));
3378 DRM_DEBUG_DRIVER("setting up %s\n", pll
->name
);
3380 assert_shared_dpll_disabled(dev_priv
, pll
);
3382 pll
->mode_set(dev_priv
, pll
);
3389 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
3391 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3392 int dslreg
= PIPEDSL(pipe
);
3395 temp
= I915_READ(dslreg
);
3397 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
3398 if (wait_for(I915_READ(dslreg
) != temp
, 5))
3399 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
3403 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
3405 struct drm_device
*dev
= crtc
->base
.dev
;
3406 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3407 int pipe
= crtc
->pipe
;
3409 if (crtc
->config
.pch_pfit
.enabled
) {
3410 /* Force use of hard-coded filter coefficients
3411 * as some pre-programmed values are broken,
3414 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
3415 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
3416 PF_PIPE_SEL_IVB(pipe
));
3418 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
3419 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
.pch_pfit
.pos
);
3420 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
.pch_pfit
.size
);
3424 static void intel_enable_planes(struct drm_crtc
*crtc
)
3426 struct drm_device
*dev
= crtc
->dev
;
3427 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
3428 struct intel_plane
*intel_plane
;
3430 list_for_each_entry(intel_plane
, &dev
->mode_config
.plane_list
, base
.head
)
3431 if (intel_plane
->pipe
== pipe
)
3432 intel_plane_restore(&intel_plane
->base
);
3435 static void intel_disable_planes(struct drm_crtc
*crtc
)
3437 struct drm_device
*dev
= crtc
->dev
;
3438 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
3439 struct intel_plane
*intel_plane
;
3441 list_for_each_entry(intel_plane
, &dev
->mode_config
.plane_list
, base
.head
)
3442 if (intel_plane
->pipe
== pipe
)
3443 intel_plane_disable(&intel_plane
->base
);
3446 void hsw_enable_ips(struct intel_crtc
*crtc
)
3448 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
3450 if (!crtc
->config
.ips_enabled
)
3453 /* We can only enable IPS after we enable a plane and wait for a vblank.
3454 * We guarantee that the plane is enabled by calling intel_enable_ips
3455 * only after intel_enable_plane. And intel_enable_plane already waits
3456 * for a vblank, so all we need to do here is to enable the IPS bit. */
3457 assert_plane_enabled(dev_priv
, crtc
->plane
);
3458 if (IS_BROADWELL(crtc
->base
.dev
)) {
3459 mutex_lock(&dev_priv
->rps
.hw_lock
);
3460 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0xc0000000));
3461 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3462 /* Quoting Art Runyan: "its not safe to expect any particular
3463 * value in IPS_CTL bit 31 after enabling IPS through the
3464 * mailbox." Moreover, the mailbox may return a bogus state,
3465 * so we need to just enable it and continue on.
3468 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
3469 /* The bit only becomes 1 in the next vblank, so this wait here
3470 * is essentially intel_wait_for_vblank. If we don't have this
3471 * and don't wait for vblanks until the end of crtc_enable, then
3472 * the HW state readout code will complain that the expected
3473 * IPS_CTL value is not the one we read. */
3474 if (wait_for(I915_READ_NOTRACE(IPS_CTL
) & IPS_ENABLE
, 50))
3475 DRM_ERROR("Timed out waiting for IPS enable\n");
3479 void hsw_disable_ips(struct intel_crtc
*crtc
)
3481 struct drm_device
*dev
= crtc
->base
.dev
;
3482 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3484 if (!crtc
->config
.ips_enabled
)
3487 assert_plane_enabled(dev_priv
, crtc
->plane
);
3488 if (IS_BROADWELL(crtc
->base
.dev
)) {
3489 mutex_lock(&dev_priv
->rps
.hw_lock
);
3490 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0));
3491 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3493 I915_WRITE(IPS_CTL
, 0);
3494 POSTING_READ(IPS_CTL
);
3497 /* We need to wait for a vblank before we can disable the plane. */
3498 intel_wait_for_vblank(dev
, crtc
->pipe
);
3501 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3502 static void intel_crtc_load_lut(struct drm_crtc
*crtc
)
3504 struct drm_device
*dev
= crtc
->dev
;
3505 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3506 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3507 enum pipe pipe
= intel_crtc
->pipe
;
3508 int palreg
= PALETTE(pipe
);
3510 bool reenable_ips
= false;
3512 /* The clocks have to be on to load the palette. */
3513 if (!crtc
->enabled
|| !intel_crtc
->active
)
3516 if (!HAS_PCH_SPLIT(dev_priv
->dev
)) {
3517 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
))
3518 assert_dsi_pll_enabled(dev_priv
);
3520 assert_pll_enabled(dev_priv
, pipe
);
3523 /* use legacy palette for Ironlake */
3524 if (HAS_PCH_SPLIT(dev
))
3525 palreg
= LGC_PALETTE(pipe
);
3527 /* Workaround : Do not read or write the pipe palette/gamma data while
3528 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3530 if (IS_HASWELL(dev
) && intel_crtc
->config
.ips_enabled
&&
3531 ((I915_READ(GAMMA_MODE(pipe
)) & GAMMA_MODE_MODE_MASK
) ==
3532 GAMMA_MODE_MODE_SPLIT
)) {
3533 hsw_disable_ips(intel_crtc
);
3534 reenable_ips
= true;
3537 for (i
= 0; i
< 256; i
++) {
3538 I915_WRITE(palreg
+ 4 * i
,
3539 (intel_crtc
->lut_r
[i
] << 16) |
3540 (intel_crtc
->lut_g
[i
] << 8) |
3541 intel_crtc
->lut_b
[i
]);
3545 hsw_enable_ips(intel_crtc
);
3548 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
3550 struct drm_device
*dev
= crtc
->dev
;
3551 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3552 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3553 struct intel_encoder
*encoder
;
3554 int pipe
= intel_crtc
->pipe
;
3555 int plane
= intel_crtc
->plane
;
3557 WARN_ON(!crtc
->enabled
);
3559 if (intel_crtc
->active
)
3562 intel_crtc
->active
= true;
3564 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
3565 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
3567 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3568 if (encoder
->pre_enable
)
3569 encoder
->pre_enable(encoder
);
3571 if (intel_crtc
->config
.has_pch_encoder
) {
3572 /* Note: FDI PLL enabling _must_ be done before we enable the
3573 * cpu pipes, hence this is separate from all the other fdi/pch
3575 ironlake_fdi_pll_enable(intel_crtc
);
3577 assert_fdi_tx_disabled(dev_priv
, pipe
);
3578 assert_fdi_rx_disabled(dev_priv
, pipe
);
3581 ironlake_pfit_enable(intel_crtc
);
3584 * On ILK+ LUT must be loaded before the pipe is running but with
3587 intel_crtc_load_lut(crtc
);
3589 intel_update_watermarks(crtc
);
3590 intel_enable_pipe(dev_priv
, pipe
,
3591 intel_crtc
->config
.has_pch_encoder
, false);
3592 intel_enable_primary_plane(dev_priv
, plane
, pipe
);
3593 intel_enable_planes(crtc
);
3594 intel_crtc_update_cursor(crtc
, true);
3596 if (intel_crtc
->config
.has_pch_encoder
)
3597 ironlake_pch_enable(crtc
);
3599 mutex_lock(&dev
->struct_mutex
);
3600 intel_update_fbc(dev
);
3601 mutex_unlock(&dev
->struct_mutex
);
3603 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3604 encoder
->enable(encoder
);
3606 if (HAS_PCH_CPT(dev
))
3607 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
3610 * There seems to be a race in PCH platform hw (at least on some
3611 * outputs) where an enabled pipe still completes any pageflip right
3612 * away (as if the pipe is off) instead of waiting for vblank. As soon
3613 * as the first vblank happend, everything works as expected. Hence just
3614 * wait for one vblank before returning to avoid strange things
3617 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3620 /* IPS only exists on ULT machines and is tied to pipe A. */
3621 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
3623 return HAS_IPS(crtc
->base
.dev
) && crtc
->pipe
== PIPE_A
;
3626 static void haswell_crtc_enable_planes(struct drm_crtc
*crtc
)
3628 struct drm_device
*dev
= crtc
->dev
;
3629 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3630 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3631 int pipe
= intel_crtc
->pipe
;
3632 int plane
= intel_crtc
->plane
;
3634 intel_enable_primary_plane(dev_priv
, plane
, pipe
);
3635 intel_enable_planes(crtc
);
3636 intel_crtc_update_cursor(crtc
, true);
3638 hsw_enable_ips(intel_crtc
);
3640 mutex_lock(&dev
->struct_mutex
);
3641 intel_update_fbc(dev
);
3642 mutex_unlock(&dev
->struct_mutex
);
3645 static void haswell_crtc_disable_planes(struct drm_crtc
*crtc
)
3647 struct drm_device
*dev
= crtc
->dev
;
3648 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3649 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3650 int pipe
= intel_crtc
->pipe
;
3651 int plane
= intel_crtc
->plane
;
3653 intel_crtc_wait_for_pending_flips(crtc
);
3654 drm_vblank_off(dev
, pipe
);
3656 /* FBC must be disabled before disabling the plane on HSW. */
3657 if (dev_priv
->fbc
.plane
== plane
)
3658 intel_disable_fbc(dev
);
3660 hsw_disable_ips(intel_crtc
);
3662 intel_crtc_update_cursor(crtc
, false);
3663 intel_disable_planes(crtc
);
3664 intel_disable_primary_plane(dev_priv
, plane
, pipe
);
3668 * This implements the workaround described in the "notes" section of the mode
3669 * set sequence documentation. When going from no pipes or single pipe to
3670 * multiple pipes, and planes are enabled after the pipe, we need to wait at
3671 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3673 static void haswell_mode_set_planes_workaround(struct intel_crtc
*crtc
)
3675 struct drm_device
*dev
= crtc
->base
.dev
;
3676 struct intel_crtc
*crtc_it
, *other_active_crtc
= NULL
;
3678 /* We want to get the other_active_crtc only if there's only 1 other
3680 list_for_each_entry(crtc_it
, &dev
->mode_config
.crtc_list
, base
.head
) {
3681 if (!crtc_it
->active
|| crtc_it
== crtc
)
3684 if (other_active_crtc
)
3687 other_active_crtc
= crtc_it
;
3689 if (!other_active_crtc
)
3692 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
3693 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
3696 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
3698 struct drm_device
*dev
= crtc
->dev
;
3699 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3700 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3701 struct intel_encoder
*encoder
;
3702 int pipe
= intel_crtc
->pipe
;
3704 WARN_ON(!crtc
->enabled
);
3706 if (intel_crtc
->active
)
3709 intel_crtc
->active
= true;
3711 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
3712 if (intel_crtc
->config
.has_pch_encoder
)
3713 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
3715 if (intel_crtc
->config
.has_pch_encoder
)
3716 dev_priv
->display
.fdi_link_train(crtc
);
3718 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3719 if (encoder
->pre_enable
)
3720 encoder
->pre_enable(encoder
);
3722 intel_ddi_enable_pipe_clock(intel_crtc
);
3724 ironlake_pfit_enable(intel_crtc
);
3727 * On ILK+ LUT must be loaded before the pipe is running but with
3730 intel_crtc_load_lut(crtc
);
3732 intel_ddi_set_pipe_settings(crtc
);
3733 intel_ddi_enable_transcoder_func(crtc
);
3735 intel_update_watermarks(crtc
);
3736 intel_enable_pipe(dev_priv
, pipe
,
3737 intel_crtc
->config
.has_pch_encoder
, false);
3739 if (intel_crtc
->config
.has_pch_encoder
)
3740 lpt_pch_enable(crtc
);
3742 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
3743 encoder
->enable(encoder
);
3744 intel_opregion_notify_encoder(encoder
, true);
3747 /* If we change the relative order between pipe/planes enabling, we need
3748 * to change the workaround. */
3749 haswell_mode_set_planes_workaround(intel_crtc
);
3750 haswell_crtc_enable_planes(crtc
);
3753 * There seems to be a race in PCH platform hw (at least on some
3754 * outputs) where an enabled pipe still completes any pageflip right
3755 * away (as if the pipe is off) instead of waiting for vblank. As soon
3756 * as the first vblank happend, everything works as expected. Hence just
3757 * wait for one vblank before returning to avoid strange things
3760 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3763 static void ironlake_pfit_disable(struct intel_crtc
*crtc
)
3765 struct drm_device
*dev
= crtc
->base
.dev
;
3766 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3767 int pipe
= crtc
->pipe
;
3769 /* To avoid upsetting the power well on haswell only disable the pfit if
3770 * it's in use. The hw state code will make sure we get this right. */
3771 if (crtc
->config
.pch_pfit
.enabled
) {
3772 I915_WRITE(PF_CTL(pipe
), 0);
3773 I915_WRITE(PF_WIN_POS(pipe
), 0);
3774 I915_WRITE(PF_WIN_SZ(pipe
), 0);
3778 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
3780 struct drm_device
*dev
= crtc
->dev
;
3781 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3782 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3783 struct intel_encoder
*encoder
;
3784 int pipe
= intel_crtc
->pipe
;
3785 int plane
= intel_crtc
->plane
;
3789 if (!intel_crtc
->active
)
3792 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3793 encoder
->disable(encoder
);
3795 intel_crtc_wait_for_pending_flips(crtc
);
3796 drm_vblank_off(dev
, pipe
);
3798 if (dev_priv
->fbc
.plane
== plane
)
3799 intel_disable_fbc(dev
);
3801 intel_crtc_update_cursor(crtc
, false);
3802 intel_disable_planes(crtc
);
3803 intel_disable_primary_plane(dev_priv
, plane
, pipe
);
3805 if (intel_crtc
->config
.has_pch_encoder
)
3806 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, false);
3808 intel_disable_pipe(dev_priv
, pipe
);
3810 ironlake_pfit_disable(intel_crtc
);
3812 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3813 if (encoder
->post_disable
)
3814 encoder
->post_disable(encoder
);
3816 if (intel_crtc
->config
.has_pch_encoder
) {
3817 ironlake_fdi_disable(crtc
);
3819 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
3820 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
3822 if (HAS_PCH_CPT(dev
)) {
3823 /* disable TRANS_DP_CTL */
3824 reg
= TRANS_DP_CTL(pipe
);
3825 temp
= I915_READ(reg
);
3826 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
3827 TRANS_DP_PORT_SEL_MASK
);
3828 temp
|= TRANS_DP_PORT_SEL_NONE
;
3829 I915_WRITE(reg
, temp
);
3831 /* disable DPLL_SEL */
3832 temp
= I915_READ(PCH_DPLL_SEL
);
3833 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
3834 I915_WRITE(PCH_DPLL_SEL
, temp
);
3837 /* disable PCH DPLL */
3838 intel_disable_shared_dpll(intel_crtc
);
3840 ironlake_fdi_pll_disable(intel_crtc
);
3843 intel_crtc
->active
= false;
3844 intel_update_watermarks(crtc
);
3846 mutex_lock(&dev
->struct_mutex
);
3847 intel_update_fbc(dev
);
3848 mutex_unlock(&dev
->struct_mutex
);
3851 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
3853 struct drm_device
*dev
= crtc
->dev
;
3854 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3855 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3856 struct intel_encoder
*encoder
;
3857 int pipe
= intel_crtc
->pipe
;
3858 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
3860 if (!intel_crtc
->active
)
3863 haswell_crtc_disable_planes(crtc
);
3865 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
3866 intel_opregion_notify_encoder(encoder
, false);
3867 encoder
->disable(encoder
);
3870 if (intel_crtc
->config
.has_pch_encoder
)
3871 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, false);
3872 intel_disable_pipe(dev_priv
, pipe
);
3874 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
3876 ironlake_pfit_disable(intel_crtc
);
3878 intel_ddi_disable_pipe_clock(intel_crtc
);
3880 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3881 if (encoder
->post_disable
)
3882 encoder
->post_disable(encoder
);
3884 if (intel_crtc
->config
.has_pch_encoder
) {
3885 lpt_disable_pch_transcoder(dev_priv
);
3886 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
3887 intel_ddi_fdi_disable(crtc
);
3890 intel_crtc
->active
= false;
3891 intel_update_watermarks(crtc
);
3893 mutex_lock(&dev
->struct_mutex
);
3894 intel_update_fbc(dev
);
3895 mutex_unlock(&dev
->struct_mutex
);
3898 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
3900 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3901 intel_put_shared_dpll(intel_crtc
);
3904 static void haswell_crtc_off(struct drm_crtc
*crtc
)
3906 intel_ddi_put_crtc_pll(crtc
);
3909 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
3911 if (!enable
&& intel_crtc
->overlay
) {
3912 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3913 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3915 mutex_lock(&dev
->struct_mutex
);
3916 dev_priv
->mm
.interruptible
= false;
3917 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
3918 dev_priv
->mm
.interruptible
= true;
3919 mutex_unlock(&dev
->struct_mutex
);
3922 /* Let userspace switch the overlay on again. In most cases userspace
3923 * has to recompute where to put it anyway.
3928 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3929 * cursor plane briefly if not already running after enabling the display
3931 * This workaround avoids occasional blank screens when self refresh is
3935 g4x_fixup_plane(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
3937 u32 cntl
= I915_READ(CURCNTR(pipe
));
3939 if ((cntl
& CURSOR_MODE
) == 0) {
3940 u32 fw_bcl_self
= I915_READ(FW_BLC_SELF
);
3942 I915_WRITE(FW_BLC_SELF
, fw_bcl_self
& ~FW_BLC_SELF_EN
);
3943 I915_WRITE(CURCNTR(pipe
), CURSOR_MODE_64_ARGB_AX
);
3944 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
3945 I915_WRITE(CURCNTR(pipe
), cntl
);
3946 I915_WRITE(CURBASE(pipe
), I915_READ(CURBASE(pipe
)));
3947 I915_WRITE(FW_BLC_SELF
, fw_bcl_self
);
3951 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
3953 struct drm_device
*dev
= crtc
->base
.dev
;
3954 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3955 struct intel_crtc_config
*pipe_config
= &crtc
->config
;
3957 if (!crtc
->config
.gmch_pfit
.control
)
3961 * The panel fitter should only be adjusted whilst the pipe is disabled,
3962 * according to register description and PRM.
3964 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
3965 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
3967 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
3968 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
3970 /* Border color in case we don't scale up to the full screen. Black by
3971 * default, change to something else for debugging. */
3972 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
3975 int valleyview_get_vco(struct drm_i915_private
*dev_priv
)
3977 int hpll_freq
, vco_freq
[] = { 800, 1600, 2000, 2400 };
3979 /* Obtain SKU information */
3980 mutex_lock(&dev_priv
->dpio_lock
);
3981 hpll_freq
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
) &
3982 CCK_FUSE_HPLL_FREQ_MASK
;
3983 mutex_unlock(&dev_priv
->dpio_lock
);
3985 return vco_freq
[hpll_freq
];
3988 /* Adjust CDclk dividers to allow high res or save power if possible */
3989 static void valleyview_set_cdclk(struct drm_device
*dev
, int cdclk
)
3991 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3994 if (cdclk
>= 320) /* jump to highest voltage for 400MHz too */
3996 else if (cdclk
== 266)
4001 mutex_lock(&dev_priv
->rps
.hw_lock
);
4002 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
4003 val
&= ~DSPFREQGUAR_MASK
;
4004 val
|= (cmd
<< DSPFREQGUAR_SHIFT
);
4005 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
4006 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
4007 DSPFREQSTAT_MASK
) == (cmd
<< DSPFREQSTAT_SHIFT
),
4009 DRM_ERROR("timed out waiting for CDclk change\n");
4011 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4016 vco
= valleyview_get_vco(dev_priv
);
4017 divider
= ((vco
<< 1) / cdclk
) - 1;
4019 mutex_lock(&dev_priv
->dpio_lock
);
4020 /* adjust cdclk divider */
4021 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
4024 vlv_cck_write(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
, val
);
4025 mutex_unlock(&dev_priv
->dpio_lock
);
4028 mutex_lock(&dev_priv
->dpio_lock
);
4029 /* adjust self-refresh exit latency value */
4030 val
= vlv_bunit_read(dev_priv
, BUNIT_REG_BISOC
);
4034 * For high bandwidth configs, we set a higher latency in the bunit
4035 * so that the core display fetch happens in time to avoid underruns.
4038 val
|= 4500 / 250; /* 4.5 usec */
4040 val
|= 3000 / 250; /* 3.0 usec */
4041 vlv_bunit_write(dev_priv
, BUNIT_REG_BISOC
, val
);
4042 mutex_unlock(&dev_priv
->dpio_lock
);
4044 /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4045 intel_i2c_reset(dev
);
4048 static int valleyview_cur_cdclk(struct drm_i915_private
*dev_priv
)
4053 vco
= valleyview_get_vco(dev_priv
);
4055 mutex_lock(&dev_priv
->dpio_lock
);
4056 divider
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
4057 mutex_unlock(&dev_priv
->dpio_lock
);
4061 cur_cdclk
= (vco
<< 1) / (divider
+ 1);
4066 static int valleyview_calc_cdclk(struct drm_i915_private
*dev_priv
,
4071 cur_cdclk
= valleyview_cur_cdclk(dev_priv
);
4074 * Really only a few cases to deal with, as only 4 CDclks are supported:
4079 * So we check to see whether we're above 90% of the lower bin and
4082 if (max_pixclk
> 288000) {
4084 } else if (max_pixclk
> 240000) {
4088 /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4091 static int intel_mode_max_pixclk(struct drm_i915_private
*dev_priv
,
4092 unsigned modeset_pipes
,
4093 struct intel_crtc_config
*pipe_config
)
4095 struct drm_device
*dev
= dev_priv
->dev
;
4096 struct intel_crtc
*intel_crtc
;
4099 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
4101 if (modeset_pipes
& (1 << intel_crtc
->pipe
))
4102 max_pixclk
= max(max_pixclk
,
4103 pipe_config
->adjusted_mode
.crtc_clock
);
4104 else if (intel_crtc
->base
.enabled
)
4105 max_pixclk
= max(max_pixclk
,
4106 intel_crtc
->config
.adjusted_mode
.crtc_clock
);
4112 static void valleyview_modeset_global_pipes(struct drm_device
*dev
,
4113 unsigned *prepare_pipes
,
4114 unsigned modeset_pipes
,
4115 struct intel_crtc_config
*pipe_config
)
4117 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4118 struct intel_crtc
*intel_crtc
;
4119 int max_pixclk
= intel_mode_max_pixclk(dev_priv
, modeset_pipes
,
4121 int cur_cdclk
= valleyview_cur_cdclk(dev_priv
);
4123 if (valleyview_calc_cdclk(dev_priv
, max_pixclk
) == cur_cdclk
)
4126 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
4128 if (intel_crtc
->base
.enabled
)
4129 *prepare_pipes
|= (1 << intel_crtc
->pipe
);
4132 static void valleyview_modeset_global_resources(struct drm_device
*dev
)
4134 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4135 int max_pixclk
= intel_mode_max_pixclk(dev_priv
, 0, NULL
);
4136 int cur_cdclk
= valleyview_cur_cdclk(dev_priv
);
4137 int req_cdclk
= valleyview_calc_cdclk(dev_priv
, max_pixclk
);
4139 if (req_cdclk
!= cur_cdclk
)
4140 valleyview_set_cdclk(dev
, req_cdclk
);
4143 static void valleyview_crtc_enable(struct drm_crtc
*crtc
)
4145 struct drm_device
*dev
= crtc
->dev
;
4146 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4147 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4148 struct intel_encoder
*encoder
;
4149 int pipe
= intel_crtc
->pipe
;
4150 int plane
= intel_crtc
->plane
;
4153 WARN_ON(!crtc
->enabled
);
4155 if (intel_crtc
->active
)
4158 intel_crtc
->active
= true;
4160 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4161 if (encoder
->pre_pll_enable
)
4162 encoder
->pre_pll_enable(encoder
);
4164 is_dsi
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
);
4167 vlv_enable_pll(intel_crtc
);
4169 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4170 if (encoder
->pre_enable
)
4171 encoder
->pre_enable(encoder
);
4173 i9xx_pfit_enable(intel_crtc
);
4175 intel_crtc_load_lut(crtc
);
4177 intel_update_watermarks(crtc
);
4178 intel_enable_pipe(dev_priv
, pipe
, false, is_dsi
);
4179 intel_enable_primary_plane(dev_priv
, plane
, pipe
);
4180 intel_enable_planes(crtc
);
4181 intel_crtc_update_cursor(crtc
, true);
4183 intel_update_fbc(dev
);
4185 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4186 encoder
->enable(encoder
);
4189 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
4191 struct drm_device
*dev
= crtc
->dev
;
4192 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4193 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4194 struct intel_encoder
*encoder
;
4195 int pipe
= intel_crtc
->pipe
;
4196 int plane
= intel_crtc
->plane
;
4198 WARN_ON(!crtc
->enabled
);
4200 if (intel_crtc
->active
)
4203 intel_crtc
->active
= true;
4205 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4206 if (encoder
->pre_enable
)
4207 encoder
->pre_enable(encoder
);
4209 i9xx_enable_pll(intel_crtc
);
4211 i9xx_pfit_enable(intel_crtc
);
4213 intel_crtc_load_lut(crtc
);
4215 intel_update_watermarks(crtc
);
4216 intel_enable_pipe(dev_priv
, pipe
, false, false);
4217 intel_enable_primary_plane(dev_priv
, plane
, pipe
);
4218 intel_enable_planes(crtc
);
4219 /* The fixup needs to happen before cursor is enabled */
4221 g4x_fixup_plane(dev_priv
, pipe
);
4222 intel_crtc_update_cursor(crtc
, true);
4224 /* Give the overlay scaler a chance to enable if it's on this pipe */
4225 intel_crtc_dpms_overlay(intel_crtc
, true);
4227 intel_update_fbc(dev
);
4229 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4230 encoder
->enable(encoder
);
4233 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
4235 struct drm_device
*dev
= crtc
->base
.dev
;
4236 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4238 if (!crtc
->config
.gmch_pfit
.control
)
4241 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
4243 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4244 I915_READ(PFIT_CONTROL
));
4245 I915_WRITE(PFIT_CONTROL
, 0);
4248 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
4250 struct drm_device
*dev
= crtc
->dev
;
4251 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4252 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4253 struct intel_encoder
*encoder
;
4254 int pipe
= intel_crtc
->pipe
;
4255 int plane
= intel_crtc
->plane
;
4257 if (!intel_crtc
->active
)
4260 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4261 encoder
->disable(encoder
);
4263 /* Give the overlay scaler a chance to disable if it's on this pipe */
4264 intel_crtc_wait_for_pending_flips(crtc
);
4265 drm_vblank_off(dev
, pipe
);
4267 if (dev_priv
->fbc
.plane
== plane
)
4268 intel_disable_fbc(dev
);
4270 intel_crtc_dpms_overlay(intel_crtc
, false);
4271 intel_crtc_update_cursor(crtc
, false);
4272 intel_disable_planes(crtc
);
4273 intel_disable_primary_plane(dev_priv
, plane
, pipe
);
4275 intel_disable_pipe(dev_priv
, pipe
);
4277 i9xx_pfit_disable(intel_crtc
);
4279 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4280 if (encoder
->post_disable
)
4281 encoder
->post_disable(encoder
);
4283 if (IS_VALLEYVIEW(dev
) && !intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
))
4284 vlv_disable_pll(dev_priv
, pipe
);
4285 else if (!IS_VALLEYVIEW(dev
))
4286 i9xx_disable_pll(dev_priv
, pipe
);
4288 intel_crtc
->active
= false;
4289 intel_update_watermarks(crtc
);
4291 intel_update_fbc(dev
);
4294 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
4298 static void intel_crtc_update_sarea(struct drm_crtc
*crtc
,
4301 struct drm_device
*dev
= crtc
->dev
;
4302 struct drm_i915_master_private
*master_priv
;
4303 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4304 int pipe
= intel_crtc
->pipe
;
4306 if (!dev
->primary
->master
)
4309 master_priv
= dev
->primary
->master
->driver_priv
;
4310 if (!master_priv
->sarea_priv
)
4315 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
4316 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
4319 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
4320 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
4323 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe
));
4329 * Sets the power management mode of the pipe and plane.
4331 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
4333 struct drm_device
*dev
= crtc
->dev
;
4334 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4335 struct intel_encoder
*intel_encoder
;
4336 bool enable
= false;
4338 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
4339 enable
|= intel_encoder
->connectors_active
;
4342 dev_priv
->display
.crtc_enable(crtc
);
4344 dev_priv
->display
.crtc_disable(crtc
);
4346 intel_crtc_update_sarea(crtc
, enable
);
4349 static void intel_crtc_disable(struct drm_crtc
*crtc
)
4351 struct drm_device
*dev
= crtc
->dev
;
4352 struct drm_connector
*connector
;
4353 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4354 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4356 /* crtc should still be enabled when we disable it. */
4357 WARN_ON(!crtc
->enabled
);
4359 dev_priv
->display
.crtc_disable(crtc
);
4360 intel_crtc
->eld_vld
= false;
4361 intel_crtc_update_sarea(crtc
, false);
4362 dev_priv
->display
.off(crtc
);
4364 assert_plane_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->plane
);
4365 assert_cursor_disabled(dev_priv
, to_intel_crtc(crtc
)->pipe
);
4366 assert_pipe_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->pipe
);
4369 mutex_lock(&dev
->struct_mutex
);
4370 intel_unpin_fb_obj(to_intel_framebuffer(crtc
->fb
)->obj
);
4371 mutex_unlock(&dev
->struct_mutex
);
4375 /* Update computed state. */
4376 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
4377 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
4380 if (connector
->encoder
->crtc
!= crtc
)
4383 connector
->dpms
= DRM_MODE_DPMS_OFF
;
4384 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
4388 void intel_encoder_destroy(struct drm_encoder
*encoder
)
4390 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
4392 drm_encoder_cleanup(encoder
);
4393 kfree(intel_encoder
);
4396 /* Simple dpms helper for encoders with just one connector, no cloning and only
4397 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4398 * state of the entire output pipe. */
4399 static void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
4401 if (mode
== DRM_MODE_DPMS_ON
) {
4402 encoder
->connectors_active
= true;
4404 intel_crtc_update_dpms(encoder
->base
.crtc
);
4406 encoder
->connectors_active
= false;
4408 intel_crtc_update_dpms(encoder
->base
.crtc
);
4412 /* Cross check the actual hw state with our own modeset state tracking (and it's
4413 * internal consistency). */
4414 static void intel_connector_check_state(struct intel_connector
*connector
)
4416 if (connector
->get_hw_state(connector
)) {
4417 struct intel_encoder
*encoder
= connector
->encoder
;
4418 struct drm_crtc
*crtc
;
4419 bool encoder_enabled
;
4422 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4423 connector
->base
.base
.id
,
4424 drm_get_connector_name(&connector
->base
));
4426 WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
4427 "wrong connector dpms state\n");
4428 WARN(connector
->base
.encoder
!= &encoder
->base
,
4429 "active connector not linked to encoder\n");
4430 WARN(!encoder
->connectors_active
,
4431 "encoder->connectors_active not set\n");
4433 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
4434 WARN(!encoder_enabled
, "encoder not enabled\n");
4435 if (WARN_ON(!encoder
->base
.crtc
))
4438 crtc
= encoder
->base
.crtc
;
4440 WARN(!crtc
->enabled
, "crtc not enabled\n");
4441 WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
4442 WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
4443 "encoder active on the wrong pipe\n");
4447 /* Even simpler default implementation, if there's really no special case to
4449 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
4451 /* All the simple cases only support two dpms states. */
4452 if (mode
!= DRM_MODE_DPMS_ON
)
4453 mode
= DRM_MODE_DPMS_OFF
;
4455 if (mode
== connector
->dpms
)
4458 connector
->dpms
= mode
;
4460 /* Only need to change hw state when actually enabled */
4461 if (connector
->encoder
)
4462 intel_encoder_dpms(to_intel_encoder(connector
->encoder
), mode
);
4464 intel_modeset_check_state(connector
->dev
);
4467 /* Simple connector->get_hw_state implementation for encoders that support only
4468 * one connector and no cloning and hence the encoder state determines the state
4469 * of the connector. */
4470 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
4473 struct intel_encoder
*encoder
= connector
->encoder
;
4475 return encoder
->get_hw_state(encoder
, &pipe
);
4478 static bool ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
4479 struct intel_crtc_config
*pipe_config
)
4481 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4482 struct intel_crtc
*pipe_B_crtc
=
4483 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
4485 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4486 pipe_name(pipe
), pipe_config
->fdi_lanes
);
4487 if (pipe_config
->fdi_lanes
> 4) {
4488 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4489 pipe_name(pipe
), pipe_config
->fdi_lanes
);
4493 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
4494 if (pipe_config
->fdi_lanes
> 2) {
4495 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4496 pipe_config
->fdi_lanes
);
4503 if (INTEL_INFO(dev
)->num_pipes
== 2)
4506 /* Ivybridge 3 pipe is really complicated */
4511 if (dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]->enabled
&&
4512 pipe_config
->fdi_lanes
> 2) {
4513 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4514 pipe_name(pipe
), pipe_config
->fdi_lanes
);
4519 if (!pipe_has_enabled_pch(pipe_B_crtc
) ||
4520 pipe_B_crtc
->config
.fdi_lanes
<= 2) {
4521 if (pipe_config
->fdi_lanes
> 2) {
4522 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4523 pipe_name(pipe
), pipe_config
->fdi_lanes
);
4527 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4537 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
4538 struct intel_crtc_config
*pipe_config
)
4540 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4541 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
4542 int lane
, link_bw
, fdi_dotclock
;
4543 bool setup_ok
, needs_recompute
= false;
4546 /* FDI is a binary signal running at ~2.7GHz, encoding
4547 * each output octet as 10 bits. The actual frequency
4548 * is stored as a divider into a 100MHz clock, and the
4549 * mode pixel clock is stored in units of 1KHz.
4550 * Hence the bw of each lane in terms of the mode signal
4553 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
4555 fdi_dotclock
= adjusted_mode
->crtc_clock
;
4557 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
4558 pipe_config
->pipe_bpp
);
4560 pipe_config
->fdi_lanes
= lane
;
4562 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
4563 link_bw
, &pipe_config
->fdi_m_n
);
4565 setup_ok
= ironlake_check_fdi_lanes(intel_crtc
->base
.dev
,
4566 intel_crtc
->pipe
, pipe_config
);
4567 if (!setup_ok
&& pipe_config
->pipe_bpp
> 6*3) {
4568 pipe_config
->pipe_bpp
-= 2*3;
4569 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4570 pipe_config
->pipe_bpp
);
4571 needs_recompute
= true;
4572 pipe_config
->bw_constrained
= true;
4577 if (needs_recompute
)
4580 return setup_ok
? 0 : -EINVAL
;
4583 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
4584 struct intel_crtc_config
*pipe_config
)
4586 pipe_config
->ips_enabled
= i915_enable_ips
&&
4587 hsw_crtc_supports_ips(crtc
) &&
4588 pipe_config
->pipe_bpp
<= 24;
4591 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
4592 struct intel_crtc_config
*pipe_config
)
4594 struct drm_device
*dev
= crtc
->base
.dev
;
4595 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
4597 /* FIXME should check pixel clock limits on all platforms */
4598 if (INTEL_INFO(dev
)->gen
< 4) {
4599 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4601 dev_priv
->display
.get_display_clock_speed(dev
);
4604 * Enable pixel doubling when the dot clock
4605 * is > 90% of the (display) core speed.
4607 * GDG double wide on either pipe,
4608 * otherwise pipe A only.
4610 if ((crtc
->pipe
== PIPE_A
|| IS_I915G(dev
)) &&
4611 adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10) {
4613 pipe_config
->double_wide
= true;
4616 if (adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10)
4621 * Pipe horizontal size must be even in:
4623 * - LVDS dual channel mode
4624 * - Double wide pipe
4626 if ((intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4627 intel_is_dual_link_lvds(dev
)) || pipe_config
->double_wide
)
4628 pipe_config
->pipe_src_w
&= ~1;
4630 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4631 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4633 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
4634 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
4637 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) && pipe_config
->pipe_bpp
> 10*3) {
4638 pipe_config
->pipe_bpp
= 10*3; /* 12bpc is gen5+ */
4639 } else if (INTEL_INFO(dev
)->gen
<= 4 && pipe_config
->pipe_bpp
> 8*3) {
4640 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4642 pipe_config
->pipe_bpp
= 8*3;
4646 hsw_compute_ips_config(crtc
, pipe_config
);
4648 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4649 * clock survives for now. */
4650 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
4651 pipe_config
->shared_dpll
= crtc
->config
.shared_dpll
;
4653 if (pipe_config
->has_pch_encoder
)
4654 return ironlake_fdi_compute_config(crtc
, pipe_config
);
4659 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
4661 return 400000; /* FIXME */
4664 static int i945_get_display_clock_speed(struct drm_device
*dev
)
4669 static int i915_get_display_clock_speed(struct drm_device
*dev
)
4674 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
4679 static int pnv_get_display_clock_speed(struct drm_device
*dev
)
4683 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
4685 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
4686 case GC_DISPLAY_CLOCK_267_MHZ_PNV
:
4688 case GC_DISPLAY_CLOCK_333_MHZ_PNV
:
4690 case GC_DISPLAY_CLOCK_444_MHZ_PNV
:
4692 case GC_DISPLAY_CLOCK_200_MHZ_PNV
:
4695 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc
);
4696 case GC_DISPLAY_CLOCK_133_MHZ_PNV
:
4698 case GC_DISPLAY_CLOCK_167_MHZ_PNV
:
4703 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
4707 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
4709 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
4712 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
4713 case GC_DISPLAY_CLOCK_333_MHZ
:
4716 case GC_DISPLAY_CLOCK_190_200_MHZ
:
4722 static int i865_get_display_clock_speed(struct drm_device
*dev
)
4727 static int i855_get_display_clock_speed(struct drm_device
*dev
)
4730 /* Assume that the hardware is in the high speed state. This
4731 * should be the default.
4733 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
4734 case GC_CLOCK_133_200
:
4735 case GC_CLOCK_100_200
:
4737 case GC_CLOCK_166_250
:
4739 case GC_CLOCK_100_133
:
4743 /* Shouldn't happen */
4747 static int i830_get_display_clock_speed(struct drm_device
*dev
)
4753 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
4755 while (*num
> DATA_LINK_M_N_MASK
||
4756 *den
> DATA_LINK_M_N_MASK
) {
4762 static void compute_m_n(unsigned int m
, unsigned int n
,
4763 uint32_t *ret_m
, uint32_t *ret_n
)
4765 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
4766 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
4767 intel_reduce_m_n_ratio(ret_m
, ret_n
);
4771 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
4772 int pixel_clock
, int link_clock
,
4773 struct intel_link_m_n
*m_n
)
4777 compute_m_n(bits_per_pixel
* pixel_clock
,
4778 link_clock
* nlanes
* 8,
4779 &m_n
->gmch_m
, &m_n
->gmch_n
);
4781 compute_m_n(pixel_clock
, link_clock
,
4782 &m_n
->link_m
, &m_n
->link_n
);
4785 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
4787 if (i915_panel_use_ssc
>= 0)
4788 return i915_panel_use_ssc
!= 0;
4789 return dev_priv
->vbt
.lvds_use_ssc
4790 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
4793 static int i9xx_get_refclk(struct drm_crtc
*crtc
, int num_connectors
)
4795 struct drm_device
*dev
= crtc
->dev
;
4796 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4799 if (IS_VALLEYVIEW(dev
)) {
4801 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4802 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
4803 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
4804 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
4805 } else if (!IS_GEN2(dev
)) {
4814 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
4816 return (1 << dpll
->n
) << 16 | dpll
->m2
;
4819 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
4821 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
4824 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
4825 intel_clock_t
*reduced_clock
)
4827 struct drm_device
*dev
= crtc
->base
.dev
;
4828 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4829 int pipe
= crtc
->pipe
;
4832 if (IS_PINEVIEW(dev
)) {
4833 fp
= pnv_dpll_compute_fp(&crtc
->config
.dpll
);
4835 fp2
= pnv_dpll_compute_fp(reduced_clock
);
4837 fp
= i9xx_dpll_compute_fp(&crtc
->config
.dpll
);
4839 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
4842 I915_WRITE(FP0(pipe
), fp
);
4843 crtc
->config
.dpll_hw_state
.fp0
= fp
;
4845 crtc
->lowfreq_avail
= false;
4846 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4847 reduced_clock
&& i915_powersave
) {
4848 I915_WRITE(FP1(pipe
), fp2
);
4849 crtc
->config
.dpll_hw_state
.fp1
= fp2
;
4850 crtc
->lowfreq_avail
= true;
4852 I915_WRITE(FP1(pipe
), fp
);
4853 crtc
->config
.dpll_hw_state
.fp1
= fp
;
4857 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
4863 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4864 * and set it to a reasonable value instead.
4866 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
4867 reg_val
&= 0xffffff00;
4868 reg_val
|= 0x00000030;
4869 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
4871 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
4872 reg_val
&= 0x8cffffff;
4873 reg_val
= 0x8c000000;
4874 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
4876 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
4877 reg_val
&= 0xffffff00;
4878 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
4880 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
4881 reg_val
&= 0x00ffffff;
4882 reg_val
|= 0xb0000000;
4883 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
4886 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
4887 struct intel_link_m_n
*m_n
)
4889 struct drm_device
*dev
= crtc
->base
.dev
;
4890 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4891 int pipe
= crtc
->pipe
;
4893 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
4894 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
4895 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
4896 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
4899 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
4900 struct intel_link_m_n
*m_n
)
4902 struct drm_device
*dev
= crtc
->base
.dev
;
4903 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4904 int pipe
= crtc
->pipe
;
4905 enum transcoder transcoder
= crtc
->config
.cpu_transcoder
;
4907 if (INTEL_INFO(dev
)->gen
>= 5) {
4908 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
4909 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
4910 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
4911 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
4913 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
4914 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
4915 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
4916 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
4920 static void intel_dp_set_m_n(struct intel_crtc
*crtc
)
4922 if (crtc
->config
.has_pch_encoder
)
4923 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
4925 intel_cpu_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
4928 static void vlv_update_pll(struct intel_crtc
*crtc
)
4930 struct drm_device
*dev
= crtc
->base
.dev
;
4931 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4932 int pipe
= crtc
->pipe
;
4934 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
4935 u32 coreclk
, reg_val
, dpll_md
;
4937 mutex_lock(&dev_priv
->dpio_lock
);
4939 bestn
= crtc
->config
.dpll
.n
;
4940 bestm1
= crtc
->config
.dpll
.m1
;
4941 bestm2
= crtc
->config
.dpll
.m2
;
4942 bestp1
= crtc
->config
.dpll
.p1
;
4943 bestp2
= crtc
->config
.dpll
.p2
;
4945 /* See eDP HDMI DPIO driver vbios notes doc */
4947 /* PLL B needs special handling */
4949 vlv_pllb_recal_opamp(dev_priv
, pipe
);
4951 /* Set up Tx target for periodic Rcomp update */
4952 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9_BCAST
, 0x0100000f);
4954 /* Disable target IRef on PLL */
4955 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW8(pipe
));
4956 reg_val
&= 0x00ffffff;
4957 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW8(pipe
), reg_val
);
4959 /* Disable fast lock */
4960 vlv_dpio_write(dev_priv
, pipe
, VLV_CMN_DW0
, 0x610);
4962 /* Set idtafcrecal before PLL is enabled */
4963 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
4964 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
4965 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
4966 mdiv
|= (1 << DPIO_K_SHIFT
);
4969 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4970 * but we don't support that).
4971 * Note: don't use the DAC post divider as it seems unstable.
4973 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
4974 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
4976 mdiv
|= DPIO_ENABLE_CALIBRATION
;
4977 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
4979 /* Set HBR and RBR LPF coefficients */
4980 if (crtc
->config
.port_clock
== 162000 ||
4981 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_ANALOG
) ||
4982 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
))
4983 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
4986 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
4989 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
) ||
4990 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
)) {
4991 /* Use SSC source */
4993 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
4996 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
4998 } else { /* HDMI or VGA */
4999 /* Use bend source */
5001 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5004 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5008 coreclk
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW7(pipe
));
5009 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
5010 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
) ||
5011 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
))
5012 coreclk
|= 0x01000000;
5013 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW7(pipe
), coreclk
);
5015 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW11(pipe
), 0x87871000);
5018 * Enable DPIO clock input. We should never disable the reference
5019 * clock for pipe B, since VGA hotplug / manual detection depends
5022 dpll
= DPLL_EXT_BUFFER_ENABLE_VLV
| DPLL_REFA_CLK_ENABLE_VLV
|
5023 DPLL_VGA_MODE_DIS
| DPLL_INTEGRATED_CLOCK_VLV
;
5024 /* We should never disable this, set it here for state tracking */
5026 dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
5027 dpll
|= DPLL_VCO_ENABLE
;
5028 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
5030 dpll_md
= (crtc
->config
.pixel_multiplier
- 1)
5031 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
5032 crtc
->config
.dpll_hw_state
.dpll_md
= dpll_md
;
5034 if (crtc
->config
.has_dp_encoder
)
5035 intel_dp_set_m_n(crtc
);
5037 mutex_unlock(&dev_priv
->dpio_lock
);
5040 static void i9xx_update_pll(struct intel_crtc
*crtc
,
5041 intel_clock_t
*reduced_clock
,
5044 struct drm_device
*dev
= crtc
->base
.dev
;
5045 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5048 struct dpll
*clock
= &crtc
->config
.dpll
;
5050 i9xx_update_pll_dividers(crtc
, reduced_clock
);
5052 is_sdvo
= intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_SDVO
) ||
5053 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
);
5055 dpll
= DPLL_VGA_MODE_DIS
;
5057 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
))
5058 dpll
|= DPLLB_MODE_LVDS
;
5060 dpll
|= DPLLB_MODE_DAC_SERIAL
;
5062 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
5063 dpll
|= (crtc
->config
.pixel_multiplier
- 1)
5064 << SDVO_MULTIPLIER_SHIFT_HIRES
;
5068 dpll
|= DPLL_SDVO_HIGH_SPEED
;
5070 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
))
5071 dpll
|= DPLL_SDVO_HIGH_SPEED
;
5073 /* compute bitmask from p1 value */
5074 if (IS_PINEVIEW(dev
))
5075 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
5077 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5078 if (IS_G4X(dev
) && reduced_clock
)
5079 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
5081 switch (clock
->p2
) {
5083 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
5086 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
5089 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
5092 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
5095 if (INTEL_INFO(dev
)->gen
>= 4)
5096 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
5098 if (crtc
->config
.sdvo_tv_clock
)
5099 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
5100 else if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
5101 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
5102 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
5104 dpll
|= PLL_REF_INPUT_DREFCLK
;
5106 dpll
|= DPLL_VCO_ENABLE
;
5107 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
5109 if (INTEL_INFO(dev
)->gen
>= 4) {
5110 u32 dpll_md
= (crtc
->config
.pixel_multiplier
- 1)
5111 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
5112 crtc
->config
.dpll_hw_state
.dpll_md
= dpll_md
;
5115 if (crtc
->config
.has_dp_encoder
)
5116 intel_dp_set_m_n(crtc
);
5119 static void i8xx_update_pll(struct intel_crtc
*crtc
,
5120 intel_clock_t
*reduced_clock
,
5123 struct drm_device
*dev
= crtc
->base
.dev
;
5124 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5126 struct dpll
*clock
= &crtc
->config
.dpll
;
5128 i9xx_update_pll_dividers(crtc
, reduced_clock
);
5130 dpll
= DPLL_VGA_MODE_DIS
;
5132 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
)) {
5133 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5136 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
5138 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5140 dpll
|= PLL_P2_DIVIDE_BY_4
;
5143 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DVO
))
5144 dpll
|= DPLL_DVO_2X_MODE
;
5146 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
5147 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
5148 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
5150 dpll
|= PLL_REF_INPUT_DREFCLK
;
5152 dpll
|= DPLL_VCO_ENABLE
;
5153 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
5156 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
5158 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5159 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5160 enum pipe pipe
= intel_crtc
->pipe
;
5161 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
5162 struct drm_display_mode
*adjusted_mode
=
5163 &intel_crtc
->config
.adjusted_mode
;
5164 uint32_t vsyncshift
, crtc_vtotal
, crtc_vblank_end
;
5166 /* We need to be careful not to changed the adjusted mode, for otherwise
5167 * the hw state checker will get angry at the mismatch. */
5168 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
5169 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
5171 if (!IS_GEN2(dev
) && adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
5172 /* the chip adds 2 halflines automatically */
5174 crtc_vblank_end
-= 1;
5175 vsyncshift
= adjusted_mode
->crtc_hsync_start
5176 - adjusted_mode
->crtc_htotal
/ 2;
5181 if (INTEL_INFO(dev
)->gen
> 3)
5182 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
5184 I915_WRITE(HTOTAL(cpu_transcoder
),
5185 (adjusted_mode
->crtc_hdisplay
- 1) |
5186 ((adjusted_mode
->crtc_htotal
- 1) << 16));
5187 I915_WRITE(HBLANK(cpu_transcoder
),
5188 (adjusted_mode
->crtc_hblank_start
- 1) |
5189 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
5190 I915_WRITE(HSYNC(cpu_transcoder
),
5191 (adjusted_mode
->crtc_hsync_start
- 1) |
5192 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
5194 I915_WRITE(VTOTAL(cpu_transcoder
),
5195 (adjusted_mode
->crtc_vdisplay
- 1) |
5196 ((crtc_vtotal
- 1) << 16));
5197 I915_WRITE(VBLANK(cpu_transcoder
),
5198 (adjusted_mode
->crtc_vblank_start
- 1) |
5199 ((crtc_vblank_end
- 1) << 16));
5200 I915_WRITE(VSYNC(cpu_transcoder
),
5201 (adjusted_mode
->crtc_vsync_start
- 1) |
5202 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
5204 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5205 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5206 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5208 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
5209 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
5210 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
5212 /* pipesrc controls the size that is scaled from, which should
5213 * always be the user's requested size.
5215 I915_WRITE(PIPESRC(pipe
),
5216 ((intel_crtc
->config
.pipe_src_w
- 1) << 16) |
5217 (intel_crtc
->config
.pipe_src_h
- 1));
5220 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
5221 struct intel_crtc_config
*pipe_config
)
5223 struct drm_device
*dev
= crtc
->base
.dev
;
5224 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5225 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
5228 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
5229 pipe_config
->adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
5230 pipe_config
->adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
5231 tmp
= I915_READ(HBLANK(cpu_transcoder
));
5232 pipe_config
->adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
5233 pipe_config
->adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
5234 tmp
= I915_READ(HSYNC(cpu_transcoder
));
5235 pipe_config
->adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
5236 pipe_config
->adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
5238 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
5239 pipe_config
->adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
5240 pipe_config
->adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
5241 tmp
= I915_READ(VBLANK(cpu_transcoder
));
5242 pipe_config
->adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
5243 pipe_config
->adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
5244 tmp
= I915_READ(VSYNC(cpu_transcoder
));
5245 pipe_config
->adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
5246 pipe_config
->adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
5248 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
5249 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
5250 pipe_config
->adjusted_mode
.crtc_vtotal
+= 1;
5251 pipe_config
->adjusted_mode
.crtc_vblank_end
+= 1;
5254 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
5255 pipe_config
->pipe_src_h
= (tmp
& 0xffff) + 1;
5256 pipe_config
->pipe_src_w
= ((tmp
>> 16) & 0xffff) + 1;
5258 pipe_config
->requested_mode
.vdisplay
= pipe_config
->pipe_src_h
;
5259 pipe_config
->requested_mode
.hdisplay
= pipe_config
->pipe_src_w
;
5262 static void intel_crtc_mode_from_pipe_config(struct intel_crtc
*intel_crtc
,
5263 struct intel_crtc_config
*pipe_config
)
5265 struct drm_crtc
*crtc
= &intel_crtc
->base
;
5267 crtc
->mode
.hdisplay
= pipe_config
->adjusted_mode
.crtc_hdisplay
;
5268 crtc
->mode
.htotal
= pipe_config
->adjusted_mode
.crtc_htotal
;
5269 crtc
->mode
.hsync_start
= pipe_config
->adjusted_mode
.crtc_hsync_start
;
5270 crtc
->mode
.hsync_end
= pipe_config
->adjusted_mode
.crtc_hsync_end
;
5272 crtc
->mode
.vdisplay
= pipe_config
->adjusted_mode
.crtc_vdisplay
;
5273 crtc
->mode
.vtotal
= pipe_config
->adjusted_mode
.crtc_vtotal
;
5274 crtc
->mode
.vsync_start
= pipe_config
->adjusted_mode
.crtc_vsync_start
;
5275 crtc
->mode
.vsync_end
= pipe_config
->adjusted_mode
.crtc_vsync_end
;
5277 crtc
->mode
.flags
= pipe_config
->adjusted_mode
.flags
;
5279 crtc
->mode
.clock
= pipe_config
->adjusted_mode
.crtc_clock
;
5280 crtc
->mode
.flags
|= pipe_config
->adjusted_mode
.flags
;
5283 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
5285 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5286 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5291 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
5292 I915_READ(PIPECONF(intel_crtc
->pipe
)) & PIPECONF_ENABLE
)
5293 pipeconf
|= PIPECONF_ENABLE
;
5295 if (intel_crtc
->config
.double_wide
)
5296 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
5298 /* only g4x and later have fancy bpc/dither controls */
5299 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
5300 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5301 if (intel_crtc
->config
.dither
&& intel_crtc
->config
.pipe_bpp
!= 30)
5302 pipeconf
|= PIPECONF_DITHER_EN
|
5303 PIPECONF_DITHER_TYPE_SP
;
5305 switch (intel_crtc
->config
.pipe_bpp
) {
5307 pipeconf
|= PIPECONF_6BPC
;
5310 pipeconf
|= PIPECONF_8BPC
;
5313 pipeconf
|= PIPECONF_10BPC
;
5316 /* Case prevented by intel_choose_pipe_bpp_dither. */
5321 if (HAS_PIPE_CXSR(dev
)) {
5322 if (intel_crtc
->lowfreq_avail
) {
5323 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5324 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
5326 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5330 if (!IS_GEN2(dev
) &&
5331 intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
5332 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
5334 pipeconf
|= PIPECONF_PROGRESSIVE
;
5336 if (IS_VALLEYVIEW(dev
) && intel_crtc
->config
.limited_color_range
)
5337 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
5339 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
5340 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
5343 static int i9xx_crtc_mode_set(struct drm_crtc
*crtc
,
5345 struct drm_framebuffer
*fb
)
5347 struct drm_device
*dev
= crtc
->dev
;
5348 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5349 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5350 int pipe
= intel_crtc
->pipe
;
5351 int plane
= intel_crtc
->plane
;
5352 int refclk
, num_connectors
= 0;
5353 intel_clock_t clock
, reduced_clock
;
5355 bool ok
, has_reduced_clock
= false;
5356 bool is_lvds
= false, is_dsi
= false;
5357 struct intel_encoder
*encoder
;
5358 const intel_limit_t
*limit
;
5361 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5362 switch (encoder
->type
) {
5363 case INTEL_OUTPUT_LVDS
:
5366 case INTEL_OUTPUT_DSI
:
5377 if (!intel_crtc
->config
.clock_set
) {
5378 refclk
= i9xx_get_refclk(crtc
, num_connectors
);
5381 * Returns a set of divisors for the desired target clock with
5382 * the given refclk, or FALSE. The returned values represent
5383 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5386 limit
= intel_limit(crtc
, refclk
);
5387 ok
= dev_priv
->display
.find_dpll(limit
, crtc
,
5388 intel_crtc
->config
.port_clock
,
5389 refclk
, NULL
, &clock
);
5391 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5395 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
5397 * Ensure we match the reduced clock's P to the target
5398 * clock. If the clocks don't match, we can't switch
5399 * the display clock by using the FP0/FP1. In such case
5400 * we will disable the LVDS downclock feature.
5403 dev_priv
->display
.find_dpll(limit
, crtc
,
5404 dev_priv
->lvds_downclock
,
5408 /* Compat-code for transition, will disappear. */
5409 intel_crtc
->config
.dpll
.n
= clock
.n
;
5410 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
5411 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
5412 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
5413 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
5417 i8xx_update_pll(intel_crtc
,
5418 has_reduced_clock
? &reduced_clock
: NULL
,
5420 } else if (IS_VALLEYVIEW(dev
)) {
5421 vlv_update_pll(intel_crtc
);
5423 i9xx_update_pll(intel_crtc
,
5424 has_reduced_clock
? &reduced_clock
: NULL
,
5429 /* Set up the display plane register */
5430 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
5432 if (!IS_VALLEYVIEW(dev
)) {
5434 dspcntr
&= ~DISPPLANE_SEL_PIPE_MASK
;
5436 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
5439 intel_set_pipe_timings(intel_crtc
);
5441 /* pipesrc and dspsize control the size that is scaled from,
5442 * which should always be the user's requested size.
5444 I915_WRITE(DSPSIZE(plane
),
5445 ((intel_crtc
->config
.pipe_src_h
- 1) << 16) |
5446 (intel_crtc
->config
.pipe_src_w
- 1));
5447 I915_WRITE(DSPPOS(plane
), 0);
5449 i9xx_set_pipeconf(intel_crtc
);
5451 I915_WRITE(DSPCNTR(plane
), dspcntr
);
5452 POSTING_READ(DSPCNTR(plane
));
5454 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
5459 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
5460 struct intel_crtc_config
*pipe_config
)
5462 struct drm_device
*dev
= crtc
->base
.dev
;
5463 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5466 if (INTEL_INFO(dev
)->gen
<= 3 && (IS_I830(dev
) || !IS_MOBILE(dev
)))
5469 tmp
= I915_READ(PFIT_CONTROL
);
5470 if (!(tmp
& PFIT_ENABLE
))
5473 /* Check whether the pfit is attached to our pipe. */
5474 if (INTEL_INFO(dev
)->gen
< 4) {
5475 if (crtc
->pipe
!= PIPE_B
)
5478 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
5482 pipe_config
->gmch_pfit
.control
= tmp
;
5483 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
5484 if (INTEL_INFO(dev
)->gen
< 5)
5485 pipe_config
->gmch_pfit
.lvds_border_bits
=
5486 I915_READ(LVDS
) & LVDS_BORDER_ENABLE
;
5489 static void vlv_crtc_clock_get(struct intel_crtc
*crtc
,
5490 struct intel_crtc_config
*pipe_config
)
5492 struct drm_device
*dev
= crtc
->base
.dev
;
5493 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5494 int pipe
= pipe_config
->cpu_transcoder
;
5495 intel_clock_t clock
;
5497 int refclk
= 100000;
5499 mutex_lock(&dev_priv
->dpio_lock
);
5500 mdiv
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW3(pipe
));
5501 mutex_unlock(&dev_priv
->dpio_lock
);
5503 clock
.m1
= (mdiv
>> DPIO_M1DIV_SHIFT
) & 7;
5504 clock
.m2
= mdiv
& DPIO_M2DIV_MASK
;
5505 clock
.n
= (mdiv
>> DPIO_N_SHIFT
) & 0xf;
5506 clock
.p1
= (mdiv
>> DPIO_P1_SHIFT
) & 7;
5507 clock
.p2
= (mdiv
>> DPIO_P2_SHIFT
) & 0x1f;
5509 vlv_clock(refclk
, &clock
);
5511 /* clock.dot is the fast clock */
5512 pipe_config
->port_clock
= clock
.dot
/ 5;
5515 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
5516 struct intel_crtc_config
*pipe_config
)
5518 struct drm_device
*dev
= crtc
->base
.dev
;
5519 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5522 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
5523 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
5525 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
5526 if (!(tmp
& PIPECONF_ENABLE
))
5529 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
5530 switch (tmp
& PIPECONF_BPC_MASK
) {
5532 pipe_config
->pipe_bpp
= 18;
5535 pipe_config
->pipe_bpp
= 24;
5537 case PIPECONF_10BPC
:
5538 pipe_config
->pipe_bpp
= 30;
5545 if (INTEL_INFO(dev
)->gen
< 4)
5546 pipe_config
->double_wide
= tmp
& PIPECONF_DOUBLE_WIDE
;
5548 intel_get_pipe_timings(crtc
, pipe_config
);
5550 i9xx_get_pfit_config(crtc
, pipe_config
);
5552 if (INTEL_INFO(dev
)->gen
>= 4) {
5553 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
5554 pipe_config
->pixel_multiplier
=
5555 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
5556 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
5557 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
5558 } else if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
5559 tmp
= I915_READ(DPLL(crtc
->pipe
));
5560 pipe_config
->pixel_multiplier
=
5561 ((tmp
& SDVO_MULTIPLIER_MASK
)
5562 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
5564 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5565 * port and will be fixed up in the encoder->get_config
5567 pipe_config
->pixel_multiplier
= 1;
5569 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
5570 if (!IS_VALLEYVIEW(dev
)) {
5571 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
5572 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
5574 /* Mask out read-only status bits. */
5575 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
5576 DPLL_PORTC_READY_MASK
|
5577 DPLL_PORTB_READY_MASK
);
5580 if (IS_VALLEYVIEW(dev
))
5581 vlv_crtc_clock_get(crtc
, pipe_config
);
5583 i9xx_crtc_clock_get(crtc
, pipe_config
);
5588 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
5590 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5591 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
5592 struct intel_encoder
*encoder
;
5594 bool has_lvds
= false;
5595 bool has_cpu_edp
= false;
5596 bool has_panel
= false;
5597 bool has_ck505
= false;
5598 bool can_ssc
= false;
5600 /* We need to take the global config into account */
5601 list_for_each_entry(encoder
, &mode_config
->encoder_list
,
5603 switch (encoder
->type
) {
5604 case INTEL_OUTPUT_LVDS
:
5608 case INTEL_OUTPUT_EDP
:
5610 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
5616 if (HAS_PCH_IBX(dev
)) {
5617 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
5618 can_ssc
= has_ck505
;
5624 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5625 has_panel
, has_lvds
, has_ck505
);
5627 /* Ironlake: try to setup display ref clock before DPLL
5628 * enabling. This is only under driver's control after
5629 * PCH B stepping, previous chipset stepping should be
5630 * ignoring this setting.
5632 val
= I915_READ(PCH_DREF_CONTROL
);
5634 /* As we must carefully and slowly disable/enable each source in turn,
5635 * compute the final state we want first and check if we need to
5636 * make any changes at all.
5639 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
5641 final
|= DREF_NONSPREAD_CK505_ENABLE
;
5643 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
5645 final
&= ~DREF_SSC_SOURCE_MASK
;
5646 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
5647 final
&= ~DREF_SSC1_ENABLE
;
5650 final
|= DREF_SSC_SOURCE_ENABLE
;
5652 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
5653 final
|= DREF_SSC1_ENABLE
;
5656 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
5657 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
5659 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
5661 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5663 final
|= DREF_SSC_SOURCE_DISABLE
;
5664 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5670 /* Always enable nonspread source */
5671 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
5674 val
|= DREF_NONSPREAD_CK505_ENABLE
;
5676 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
5679 val
&= ~DREF_SSC_SOURCE_MASK
;
5680 val
|= DREF_SSC_SOURCE_ENABLE
;
5682 /* SSC must be turned on before enabling the CPU output */
5683 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
5684 DRM_DEBUG_KMS("Using SSC on panel\n");
5685 val
|= DREF_SSC1_ENABLE
;
5687 val
&= ~DREF_SSC1_ENABLE
;
5689 /* Get SSC going before enabling the outputs */
5690 I915_WRITE(PCH_DREF_CONTROL
, val
);
5691 POSTING_READ(PCH_DREF_CONTROL
);
5694 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
5696 /* Enable CPU source on CPU attached eDP */
5698 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
5699 DRM_DEBUG_KMS("Using SSC on eDP\n");
5700 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
5703 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
5705 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5707 I915_WRITE(PCH_DREF_CONTROL
, val
);
5708 POSTING_READ(PCH_DREF_CONTROL
);
5711 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5713 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
5715 /* Turn off CPU output */
5716 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5718 I915_WRITE(PCH_DREF_CONTROL
, val
);
5719 POSTING_READ(PCH_DREF_CONTROL
);
5722 /* Turn off the SSC source */
5723 val
&= ~DREF_SSC_SOURCE_MASK
;
5724 val
|= DREF_SSC_SOURCE_DISABLE
;
5727 val
&= ~DREF_SSC1_ENABLE
;
5729 I915_WRITE(PCH_DREF_CONTROL
, val
);
5730 POSTING_READ(PCH_DREF_CONTROL
);
5734 BUG_ON(val
!= final
);
5737 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
5741 tmp
= I915_READ(SOUTH_CHICKEN2
);
5742 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
5743 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
5745 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
5746 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
5747 DRM_ERROR("FDI mPHY reset assert timeout\n");
5749 tmp
= I915_READ(SOUTH_CHICKEN2
);
5750 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
5751 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
5753 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
5754 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
5755 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5758 /* WaMPhyProgramming:hsw */
5759 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
5763 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
5764 tmp
&= ~(0xFF << 24);
5765 tmp
|= (0x12 << 24);
5766 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
5768 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
5770 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
5772 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
5774 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
5776 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
5777 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
5778 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
5780 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
5781 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
5782 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
5784 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
5787 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
5789 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
5792 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
5794 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
5797 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
5799 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
5802 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
5804 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
5805 tmp
&= ~(0xFF << 16);
5806 tmp
|= (0x1C << 16);
5807 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
5809 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
5810 tmp
&= ~(0xFF << 16);
5811 tmp
|= (0x1C << 16);
5812 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
5814 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
5816 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
5818 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
5820 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
5822 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
5823 tmp
&= ~(0xF << 28);
5825 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
5827 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
5828 tmp
&= ~(0xF << 28);
5830 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
5833 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5834 * Programming" based on the parameters passed:
5835 * - Sequence to enable CLKOUT_DP
5836 * - Sequence to enable CLKOUT_DP without spread
5837 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5839 static void lpt_enable_clkout_dp(struct drm_device
*dev
, bool with_spread
,
5842 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5845 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
5847 if (WARN(dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
&&
5848 with_fdi
, "LP PCH doesn't have FDI\n"))
5851 mutex_lock(&dev_priv
->dpio_lock
);
5853 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
5854 tmp
&= ~SBI_SSCCTL_DISABLE
;
5855 tmp
|= SBI_SSCCTL_PATHALT
;
5856 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5861 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
5862 tmp
&= ~SBI_SSCCTL_PATHALT
;
5863 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5866 lpt_reset_fdi_mphy(dev_priv
);
5867 lpt_program_fdi_mphy(dev_priv
);
5871 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
5872 SBI_GEN0
: SBI_DBUFF0
;
5873 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
5874 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
5875 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
5877 mutex_unlock(&dev_priv
->dpio_lock
);
5880 /* Sequence to disable CLKOUT_DP */
5881 static void lpt_disable_clkout_dp(struct drm_device
*dev
)
5883 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5886 mutex_lock(&dev_priv
->dpio_lock
);
5888 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
5889 SBI_GEN0
: SBI_DBUFF0
;
5890 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
5891 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
5892 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
5894 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
5895 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
5896 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
5897 tmp
|= SBI_SSCCTL_PATHALT
;
5898 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5901 tmp
|= SBI_SSCCTL_DISABLE
;
5902 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5905 mutex_unlock(&dev_priv
->dpio_lock
);
5908 static void lpt_init_pch_refclk(struct drm_device
*dev
)
5910 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
5911 struct intel_encoder
*encoder
;
5912 bool has_vga
= false;
5914 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
) {
5915 switch (encoder
->type
) {
5916 case INTEL_OUTPUT_ANALOG
:
5923 lpt_enable_clkout_dp(dev
, true, true);
5925 lpt_disable_clkout_dp(dev
);
5929 * Initialize reference clocks when the driver loads
5931 void intel_init_pch_refclk(struct drm_device
*dev
)
5933 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
5934 ironlake_init_pch_refclk(dev
);
5935 else if (HAS_PCH_LPT(dev
))
5936 lpt_init_pch_refclk(dev
);
5939 static int ironlake_get_refclk(struct drm_crtc
*crtc
)
5941 struct drm_device
*dev
= crtc
->dev
;
5942 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5943 struct intel_encoder
*encoder
;
5944 int num_connectors
= 0;
5945 bool is_lvds
= false;
5947 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5948 switch (encoder
->type
) {
5949 case INTEL_OUTPUT_LVDS
:
5956 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
5957 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
5958 dev_priv
->vbt
.lvds_ssc_freq
);
5959 return dev_priv
->vbt
.lvds_ssc_freq
;
5965 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
5967 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
5968 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5969 int pipe
= intel_crtc
->pipe
;
5974 switch (intel_crtc
->config
.pipe_bpp
) {
5976 val
|= PIPECONF_6BPC
;
5979 val
|= PIPECONF_8BPC
;
5982 val
|= PIPECONF_10BPC
;
5985 val
|= PIPECONF_12BPC
;
5988 /* Case prevented by intel_choose_pipe_bpp_dither. */
5992 if (intel_crtc
->config
.dither
)
5993 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
5995 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
5996 val
|= PIPECONF_INTERLACED_ILK
;
5998 val
|= PIPECONF_PROGRESSIVE
;
6000 if (intel_crtc
->config
.limited_color_range
)
6001 val
|= PIPECONF_COLOR_RANGE_SELECT
;
6003 I915_WRITE(PIPECONF(pipe
), val
);
6004 POSTING_READ(PIPECONF(pipe
));
6008 * Set up the pipe CSC unit.
6010 * Currently only full range RGB to limited range RGB conversion
6011 * is supported, but eventually this should handle various
6012 * RGB<->YCbCr scenarios as well.
6014 static void intel_set_pipe_csc(struct drm_crtc
*crtc
)
6016 struct drm_device
*dev
= crtc
->dev
;
6017 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6018 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6019 int pipe
= intel_crtc
->pipe
;
6020 uint16_t coeff
= 0x7800; /* 1.0 */
6023 * TODO: Check what kind of values actually come out of the pipe
6024 * with these coeff/postoff values and adjust to get the best
6025 * accuracy. Perhaps we even need to take the bpc value into
6029 if (intel_crtc
->config
.limited_color_range
)
6030 coeff
= ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6033 * GY/GU and RY/RU should be the other way around according
6034 * to BSpec, but reality doesn't agree. Just set them up in
6035 * a way that results in the correct picture.
6037 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeff
<< 16);
6038 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), 0);
6040 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeff
);
6041 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), 0);
6043 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), 0);
6044 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeff
<< 16);
6046 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
6047 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
6048 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
6050 if (INTEL_INFO(dev
)->gen
> 6) {
6051 uint16_t postoff
= 0;
6053 if (intel_crtc
->config
.limited_color_range
)
6054 postoff
= (16 * (1 << 12) / 255) & 0x1fff;
6056 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
6057 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
6058 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
6060 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
6062 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
6064 if (intel_crtc
->config
.limited_color_range
)
6065 mode
|= CSC_BLACK_SCREEN_OFFSET
;
6067 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
6071 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
6073 struct drm_device
*dev
= crtc
->dev
;
6074 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6075 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6076 enum pipe pipe
= intel_crtc
->pipe
;
6077 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
6082 if (IS_HASWELL(dev
) && intel_crtc
->config
.dither
)
6083 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
6085 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
6086 val
|= PIPECONF_INTERLACED_ILK
;
6088 val
|= PIPECONF_PROGRESSIVE
;
6090 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
6091 POSTING_READ(PIPECONF(cpu_transcoder
));
6093 I915_WRITE(GAMMA_MODE(intel_crtc
->pipe
), GAMMA_MODE_MODE_8BIT
);
6094 POSTING_READ(GAMMA_MODE(intel_crtc
->pipe
));
6096 if (IS_BROADWELL(dev
)) {
6099 switch (intel_crtc
->config
.pipe_bpp
) {
6101 val
|= PIPEMISC_DITHER_6_BPC
;
6104 val
|= PIPEMISC_DITHER_8_BPC
;
6107 val
|= PIPEMISC_DITHER_10_BPC
;
6110 val
|= PIPEMISC_DITHER_12_BPC
;
6113 /* Case prevented by pipe_config_set_bpp. */
6117 if (intel_crtc
->config
.dither
)
6118 val
|= PIPEMISC_DITHER_ENABLE
| PIPEMISC_DITHER_TYPE_SP
;
6120 I915_WRITE(PIPEMISC(pipe
), val
);
6124 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
6125 intel_clock_t
*clock
,
6126 bool *has_reduced_clock
,
6127 intel_clock_t
*reduced_clock
)
6129 struct drm_device
*dev
= crtc
->dev
;
6130 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6131 struct intel_encoder
*intel_encoder
;
6133 const intel_limit_t
*limit
;
6134 bool ret
, is_lvds
= false;
6136 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
6137 switch (intel_encoder
->type
) {
6138 case INTEL_OUTPUT_LVDS
:
6144 refclk
= ironlake_get_refclk(crtc
);
6147 * Returns a set of divisors for the desired target clock with the given
6148 * refclk, or FALSE. The returned values represent the clock equation:
6149 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6151 limit
= intel_limit(crtc
, refclk
);
6152 ret
= dev_priv
->display
.find_dpll(limit
, crtc
,
6153 to_intel_crtc(crtc
)->config
.port_clock
,
6154 refclk
, NULL
, clock
);
6158 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
6160 * Ensure we match the reduced clock's P to the target clock.
6161 * If the clocks don't match, we can't switch the display clock
6162 * by using the FP0/FP1. In such case we will disable the LVDS
6163 * downclock feature.
6165 *has_reduced_clock
=
6166 dev_priv
->display
.find_dpll(limit
, crtc
,
6167 dev_priv
->lvds_downclock
,
6175 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
6178 * Account for spread spectrum to avoid
6179 * oversubscribing the link. Max center spread
6180 * is 2.5%; use 5% for safety's sake.
6182 u32 bps
= target_clock
* bpp
* 21 / 20;
6183 return bps
/ (link_bw
* 8) + 1;
6186 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
6188 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
6191 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
6193 intel_clock_t
*reduced_clock
, u32
*fp2
)
6195 struct drm_crtc
*crtc
= &intel_crtc
->base
;
6196 struct drm_device
*dev
= crtc
->dev
;
6197 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6198 struct intel_encoder
*intel_encoder
;
6200 int factor
, num_connectors
= 0;
6201 bool is_lvds
= false, is_sdvo
= false;
6203 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
6204 switch (intel_encoder
->type
) {
6205 case INTEL_OUTPUT_LVDS
:
6208 case INTEL_OUTPUT_SDVO
:
6209 case INTEL_OUTPUT_HDMI
:
6217 /* Enable autotuning of the PLL clock (if permissible) */
6220 if ((intel_panel_use_ssc(dev_priv
) &&
6221 dev_priv
->vbt
.lvds_ssc_freq
== 100000) ||
6222 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
6224 } else if (intel_crtc
->config
.sdvo_tv_clock
)
6227 if (ironlake_needs_fb_cb_tune(&intel_crtc
->config
.dpll
, factor
))
6230 if (fp2
&& (reduced_clock
->m
< factor
* reduced_clock
->n
))
6236 dpll
|= DPLLB_MODE_LVDS
;
6238 dpll
|= DPLLB_MODE_DAC_SERIAL
;
6240 dpll
|= (intel_crtc
->config
.pixel_multiplier
- 1)
6241 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
6244 dpll
|= DPLL_SDVO_HIGH_SPEED
;
6245 if (intel_crtc
->config
.has_dp_encoder
)
6246 dpll
|= DPLL_SDVO_HIGH_SPEED
;
6248 /* compute bitmask from p1 value */
6249 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
6251 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
6253 switch (intel_crtc
->config
.dpll
.p2
) {
6255 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
6258 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
6261 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
6264 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
6268 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
6269 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
6271 dpll
|= PLL_REF_INPUT_DREFCLK
;
6273 return dpll
| DPLL_VCO_ENABLE
;
6276 static int ironlake_crtc_mode_set(struct drm_crtc
*crtc
,
6278 struct drm_framebuffer
*fb
)
6280 struct drm_device
*dev
= crtc
->dev
;
6281 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6282 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6283 int pipe
= intel_crtc
->pipe
;
6284 int plane
= intel_crtc
->plane
;
6285 int num_connectors
= 0;
6286 intel_clock_t clock
, reduced_clock
;
6287 u32 dpll
= 0, fp
= 0, fp2
= 0;
6288 bool ok
, has_reduced_clock
= false;
6289 bool is_lvds
= false;
6290 struct intel_encoder
*encoder
;
6291 struct intel_shared_dpll
*pll
;
6294 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
6295 switch (encoder
->type
) {
6296 case INTEL_OUTPUT_LVDS
:
6304 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
6305 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
6307 ok
= ironlake_compute_clocks(crtc
, &clock
,
6308 &has_reduced_clock
, &reduced_clock
);
6309 if (!ok
&& !intel_crtc
->config
.clock_set
) {
6310 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6313 /* Compat-code for transition, will disappear. */
6314 if (!intel_crtc
->config
.clock_set
) {
6315 intel_crtc
->config
.dpll
.n
= clock
.n
;
6316 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
6317 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
6318 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
6319 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
6322 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6323 if (intel_crtc
->config
.has_pch_encoder
) {
6324 fp
= i9xx_dpll_compute_fp(&intel_crtc
->config
.dpll
);
6325 if (has_reduced_clock
)
6326 fp2
= i9xx_dpll_compute_fp(&reduced_clock
);
6328 dpll
= ironlake_compute_dpll(intel_crtc
,
6329 &fp
, &reduced_clock
,
6330 has_reduced_clock
? &fp2
: NULL
);
6332 intel_crtc
->config
.dpll_hw_state
.dpll
= dpll
;
6333 intel_crtc
->config
.dpll_hw_state
.fp0
= fp
;
6334 if (has_reduced_clock
)
6335 intel_crtc
->config
.dpll_hw_state
.fp1
= fp2
;
6337 intel_crtc
->config
.dpll_hw_state
.fp1
= fp
;
6339 pll
= intel_get_shared_dpll(intel_crtc
);
6341 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6346 intel_put_shared_dpll(intel_crtc
);
6348 if (intel_crtc
->config
.has_dp_encoder
)
6349 intel_dp_set_m_n(intel_crtc
);
6351 if (is_lvds
&& has_reduced_clock
&& i915_powersave
)
6352 intel_crtc
->lowfreq_avail
= true;
6354 intel_crtc
->lowfreq_avail
= false;
6356 intel_set_pipe_timings(intel_crtc
);
6358 if (intel_crtc
->config
.has_pch_encoder
) {
6359 intel_cpu_transcoder_set_m_n(intel_crtc
,
6360 &intel_crtc
->config
.fdi_m_n
);
6363 ironlake_set_pipeconf(crtc
);
6365 /* Set up the display plane register */
6366 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
);
6367 POSTING_READ(DSPCNTR(plane
));
6369 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
6374 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
6375 struct intel_link_m_n
*m_n
)
6377 struct drm_device
*dev
= crtc
->base
.dev
;
6378 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6379 enum pipe pipe
= crtc
->pipe
;
6381 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
6382 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
6383 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
6385 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
6386 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
6387 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
6390 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
6391 enum transcoder transcoder
,
6392 struct intel_link_m_n
*m_n
)
6394 struct drm_device
*dev
= crtc
->base
.dev
;
6395 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6396 enum pipe pipe
= crtc
->pipe
;
6398 if (INTEL_INFO(dev
)->gen
>= 5) {
6399 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
6400 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
6401 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
6403 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
6404 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
6405 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
6407 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
6408 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
6409 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
6411 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
6412 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
6413 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
6417 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
6418 struct intel_crtc_config
*pipe_config
)
6420 if (crtc
->config
.has_pch_encoder
)
6421 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
6423 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
6424 &pipe_config
->dp_m_n
);
6427 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
6428 struct intel_crtc_config
*pipe_config
)
6430 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
6431 &pipe_config
->fdi_m_n
);
6434 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
6435 struct intel_crtc_config
*pipe_config
)
6437 struct drm_device
*dev
= crtc
->base
.dev
;
6438 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6441 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
6443 if (tmp
& PF_ENABLE
) {
6444 pipe_config
->pch_pfit
.enabled
= true;
6445 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
6446 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
6448 /* We currently do not free assignements of panel fitters on
6449 * ivb/hsw (since we don't use the higher upscaling modes which
6450 * differentiates them) so just WARN about this case for now. */
6452 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
6453 PF_PIPE_SEL_IVB(crtc
->pipe
));
6458 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
6459 struct intel_crtc_config
*pipe_config
)
6461 struct drm_device
*dev
= crtc
->base
.dev
;
6462 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6465 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
6466 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
6468 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
6469 if (!(tmp
& PIPECONF_ENABLE
))
6472 switch (tmp
& PIPECONF_BPC_MASK
) {
6474 pipe_config
->pipe_bpp
= 18;
6477 pipe_config
->pipe_bpp
= 24;
6479 case PIPECONF_10BPC
:
6480 pipe_config
->pipe_bpp
= 30;
6482 case PIPECONF_12BPC
:
6483 pipe_config
->pipe_bpp
= 36;
6489 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
6490 struct intel_shared_dpll
*pll
;
6492 pipe_config
->has_pch_encoder
= true;
6494 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
6495 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
6496 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
6498 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
6500 if (HAS_PCH_IBX(dev_priv
->dev
)) {
6501 pipe_config
->shared_dpll
=
6502 (enum intel_dpll_id
) crtc
->pipe
;
6504 tmp
= I915_READ(PCH_DPLL_SEL
);
6505 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
6506 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_B
;
6508 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_A
;
6511 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
6513 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
6514 &pipe_config
->dpll_hw_state
));
6516 tmp
= pipe_config
->dpll_hw_state
.dpll
;
6517 pipe_config
->pixel_multiplier
=
6518 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
6519 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
6521 ironlake_pch_clock_get(crtc
, pipe_config
);
6523 pipe_config
->pixel_multiplier
= 1;
6526 intel_get_pipe_timings(crtc
, pipe_config
);
6528 ironlake_get_pfit_config(crtc
, pipe_config
);
6533 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
6535 struct drm_device
*dev
= dev_priv
->dev
;
6536 struct intel_ddi_plls
*plls
= &dev_priv
->ddi_plls
;
6537 struct intel_crtc
*crtc
;
6538 unsigned long irqflags
;
6541 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
)
6542 WARN(crtc
->active
, "CRTC for pipe %c enabled\n",
6543 pipe_name(crtc
->pipe
));
6545 WARN(I915_READ(HSW_PWR_WELL_DRIVER
), "Power well on\n");
6546 WARN(plls
->spll_refcount
, "SPLL enabled\n");
6547 WARN(plls
->wrpll1_refcount
, "WRPLL1 enabled\n");
6548 WARN(plls
->wrpll2_refcount
, "WRPLL2 enabled\n");
6549 WARN(I915_READ(PCH_PP_STATUS
) & PP_ON
, "Panel power on\n");
6550 WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
6551 "CPU PWM1 enabled\n");
6552 WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
6553 "CPU PWM2 enabled\n");
6554 WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
6555 "PCH PWM1 enabled\n");
6556 WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
6557 "Utility pin enabled\n");
6558 WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
6560 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
6561 val
= I915_READ(DEIMR
);
6562 WARN((val
| DE_PCH_EVENT_IVB
) != 0xffffffff,
6563 "Unexpected DEIMR bits enabled: 0x%x\n", val
);
6564 val
= I915_READ(SDEIMR
);
6565 WARN((val
| SDE_HOTPLUG_MASK_CPT
) != 0xffffffff,
6566 "Unexpected SDEIMR bits enabled: 0x%x\n", val
);
6567 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
6571 * This function implements pieces of two sequences from BSpec:
6572 * - Sequence for display software to disable LCPLL
6573 * - Sequence for display software to allow package C8+
6574 * The steps implemented here are just the steps that actually touch the LCPLL
6575 * register. Callers should take care of disabling all the display engine
6576 * functions, doing the mode unset, fixing interrupts, etc.
6578 static void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
6579 bool switch_to_fclk
, bool allow_power_down
)
6583 assert_can_disable_lcpll(dev_priv
);
6585 val
= I915_READ(LCPLL_CTL
);
6587 if (switch_to_fclk
) {
6588 val
|= LCPLL_CD_SOURCE_FCLK
;
6589 I915_WRITE(LCPLL_CTL
, val
);
6591 if (wait_for_atomic_us(I915_READ(LCPLL_CTL
) &
6592 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
6593 DRM_ERROR("Switching to FCLK failed\n");
6595 val
= I915_READ(LCPLL_CTL
);
6598 val
|= LCPLL_PLL_DISABLE
;
6599 I915_WRITE(LCPLL_CTL
, val
);
6600 POSTING_READ(LCPLL_CTL
);
6602 if (wait_for((I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
) == 0, 1))
6603 DRM_ERROR("LCPLL still locked\n");
6605 val
= I915_READ(D_COMP
);
6606 val
|= D_COMP_COMP_DISABLE
;
6607 mutex_lock(&dev_priv
->rps
.hw_lock
);
6608 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
, val
))
6609 DRM_ERROR("Failed to disable D_COMP\n");
6610 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6611 POSTING_READ(D_COMP
);
6614 if (wait_for((I915_READ(D_COMP
) & D_COMP_RCOMP_IN_PROGRESS
) == 0, 1))
6615 DRM_ERROR("D_COMP RCOMP still in progress\n");
6617 if (allow_power_down
) {
6618 val
= I915_READ(LCPLL_CTL
);
6619 val
|= LCPLL_POWER_DOWN_ALLOW
;
6620 I915_WRITE(LCPLL_CTL
, val
);
6621 POSTING_READ(LCPLL_CTL
);
6626 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6629 static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
6633 val
= I915_READ(LCPLL_CTL
);
6635 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
6636 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
6639 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6640 * we'll hang the machine! */
6641 gen6_gt_force_wake_get(dev_priv
, FORCEWAKE_ALL
);
6643 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
6644 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
6645 I915_WRITE(LCPLL_CTL
, val
);
6646 POSTING_READ(LCPLL_CTL
);
6649 val
= I915_READ(D_COMP
);
6650 val
|= D_COMP_COMP_FORCE
;
6651 val
&= ~D_COMP_COMP_DISABLE
;
6652 mutex_lock(&dev_priv
->rps
.hw_lock
);
6653 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
, val
))
6654 DRM_ERROR("Failed to enable D_COMP\n");
6655 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6656 POSTING_READ(D_COMP
);
6658 val
= I915_READ(LCPLL_CTL
);
6659 val
&= ~LCPLL_PLL_DISABLE
;
6660 I915_WRITE(LCPLL_CTL
, val
);
6662 if (wait_for(I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
, 5))
6663 DRM_ERROR("LCPLL not locked yet\n");
6665 if (val
& LCPLL_CD_SOURCE_FCLK
) {
6666 val
= I915_READ(LCPLL_CTL
);
6667 val
&= ~LCPLL_CD_SOURCE_FCLK
;
6668 I915_WRITE(LCPLL_CTL
, val
);
6670 if (wait_for_atomic_us((I915_READ(LCPLL_CTL
) &
6671 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
6672 DRM_ERROR("Switching back to LCPLL failed\n");
6675 gen6_gt_force_wake_put(dev_priv
, FORCEWAKE_ALL
);
6678 void hsw_enable_pc8_work(struct work_struct
*__work
)
6680 struct drm_i915_private
*dev_priv
=
6681 container_of(to_delayed_work(__work
), struct drm_i915_private
,
6683 struct drm_device
*dev
= dev_priv
->dev
;
6686 WARN_ON(!HAS_PC8(dev
));
6688 if (dev_priv
->pc8
.enabled
)
6691 DRM_DEBUG_KMS("Enabling package C8+\n");
6693 dev_priv
->pc8
.enabled
= true;
6695 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
6696 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
6697 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
6698 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
6701 lpt_disable_clkout_dp(dev
);
6702 hsw_pc8_disable_interrupts(dev
);
6703 hsw_disable_lcpll(dev_priv
, true, true);
6705 intel_runtime_pm_put(dev_priv
);
6708 static void __hsw_enable_package_c8(struct drm_i915_private
*dev_priv
)
6710 WARN_ON(!mutex_is_locked(&dev_priv
->pc8
.lock
));
6711 WARN(dev_priv
->pc8
.disable_count
< 1,
6712 "pc8.disable_count: %d\n", dev_priv
->pc8
.disable_count
);
6714 dev_priv
->pc8
.disable_count
--;
6715 if (dev_priv
->pc8
.disable_count
!= 0)
6718 schedule_delayed_work(&dev_priv
->pc8
.enable_work
,
6719 msecs_to_jiffies(i915_pc8_timeout
));
6722 static void __hsw_disable_package_c8(struct drm_i915_private
*dev_priv
)
6724 struct drm_device
*dev
= dev_priv
->dev
;
6727 WARN_ON(!mutex_is_locked(&dev_priv
->pc8
.lock
));
6728 WARN(dev_priv
->pc8
.disable_count
< 0,
6729 "pc8.disable_count: %d\n", dev_priv
->pc8
.disable_count
);
6731 dev_priv
->pc8
.disable_count
++;
6732 if (dev_priv
->pc8
.disable_count
!= 1)
6735 WARN_ON(!HAS_PC8(dev
));
6737 cancel_delayed_work_sync(&dev_priv
->pc8
.enable_work
);
6738 if (!dev_priv
->pc8
.enabled
)
6741 DRM_DEBUG_KMS("Disabling package C8+\n");
6743 intel_runtime_pm_get(dev_priv
);
6745 hsw_restore_lcpll(dev_priv
);
6746 hsw_pc8_restore_interrupts(dev
);
6747 lpt_init_pch_refclk(dev
);
6749 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
6750 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
6751 val
|= PCH_LP_PARTITION_LEVEL_DISABLE
;
6752 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
6755 intel_prepare_ddi(dev
);
6756 i915_gem_init_swizzling(dev
);
6757 mutex_lock(&dev_priv
->rps
.hw_lock
);
6758 gen6_update_ring_freq(dev
);
6759 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6760 dev_priv
->pc8
.enabled
= false;
6763 void hsw_enable_package_c8(struct drm_i915_private
*dev_priv
)
6765 if (!HAS_PC8(dev_priv
->dev
))
6768 mutex_lock(&dev_priv
->pc8
.lock
);
6769 __hsw_enable_package_c8(dev_priv
);
6770 mutex_unlock(&dev_priv
->pc8
.lock
);
6773 void hsw_disable_package_c8(struct drm_i915_private
*dev_priv
)
6775 if (!HAS_PC8(dev_priv
->dev
))
6778 mutex_lock(&dev_priv
->pc8
.lock
);
6779 __hsw_disable_package_c8(dev_priv
);
6780 mutex_unlock(&dev_priv
->pc8
.lock
);
6783 static bool hsw_can_enable_package_c8(struct drm_i915_private
*dev_priv
)
6785 struct drm_device
*dev
= dev_priv
->dev
;
6786 struct intel_crtc
*crtc
;
6789 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
)
6790 if (crtc
->base
.enabled
)
6793 /* This case is still possible since we have the i915.disable_power_well
6794 * parameter and also the KVMr or something else might be requesting the
6796 val
= I915_READ(HSW_PWR_WELL_DRIVER
);
6798 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6805 /* Since we're called from modeset_global_resources there's no way to
6806 * symmetrically increase and decrease the refcount, so we use
6807 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6810 static void hsw_update_package_c8(struct drm_device
*dev
)
6812 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6815 if (!HAS_PC8(dev_priv
->dev
))
6818 if (!i915_enable_pc8
)
6821 mutex_lock(&dev_priv
->pc8
.lock
);
6823 allow
= hsw_can_enable_package_c8(dev_priv
);
6825 if (allow
== dev_priv
->pc8
.requirements_met
)
6828 dev_priv
->pc8
.requirements_met
= allow
;
6831 __hsw_enable_package_c8(dev_priv
);
6833 __hsw_disable_package_c8(dev_priv
);
6836 mutex_unlock(&dev_priv
->pc8
.lock
);
6839 static void hsw_package_c8_gpu_idle(struct drm_i915_private
*dev_priv
)
6841 if (!HAS_PC8(dev_priv
->dev
))
6844 mutex_lock(&dev_priv
->pc8
.lock
);
6845 if (!dev_priv
->pc8
.gpu_idle
) {
6846 dev_priv
->pc8
.gpu_idle
= true;
6847 __hsw_enable_package_c8(dev_priv
);
6849 mutex_unlock(&dev_priv
->pc8
.lock
);
6852 static void hsw_package_c8_gpu_busy(struct drm_i915_private
*dev_priv
)
6854 if (!HAS_PC8(dev_priv
->dev
))
6857 mutex_lock(&dev_priv
->pc8
.lock
);
6858 if (dev_priv
->pc8
.gpu_idle
) {
6859 dev_priv
->pc8
.gpu_idle
= false;
6860 __hsw_disable_package_c8(dev_priv
);
6862 mutex_unlock(&dev_priv
->pc8
.lock
);
6865 #define for_each_power_domain(domain, mask) \
6866 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
6867 if ((1 << (domain)) & (mask))
6869 static unsigned long get_pipe_power_domains(struct drm_device
*dev
,
6870 enum pipe pipe
, bool pfit_enabled
)
6873 enum transcoder transcoder
;
6875 transcoder
= intel_pipe_to_cpu_transcoder(dev
->dev_private
, pipe
);
6877 mask
= BIT(POWER_DOMAIN_PIPE(pipe
));
6878 mask
|= BIT(POWER_DOMAIN_TRANSCODER(transcoder
));
6880 mask
|= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe
));
6885 void intel_display_set_init_power(struct drm_device
*dev
, bool enable
)
6887 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6889 if (dev_priv
->power_domains
.init_power_on
== enable
)
6893 intel_display_power_get(dev
, POWER_DOMAIN_INIT
);
6895 intel_display_power_put(dev
, POWER_DOMAIN_INIT
);
6897 dev_priv
->power_domains
.init_power_on
= enable
;
6900 static void modeset_update_power_wells(struct drm_device
*dev
)
6902 unsigned long pipe_domains
[I915_MAX_PIPES
] = { 0, };
6903 struct intel_crtc
*crtc
;
6906 * First get all needed power domains, then put all unneeded, to avoid
6907 * any unnecessary toggling of the power wells.
6909 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
6910 enum intel_display_power_domain domain
;
6912 if (!crtc
->base
.enabled
)
6915 pipe_domains
[crtc
->pipe
] = get_pipe_power_domains(dev
,
6917 crtc
->config
.pch_pfit
.enabled
);
6919 for_each_power_domain(domain
, pipe_domains
[crtc
->pipe
])
6920 intel_display_power_get(dev
, domain
);
6923 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
6924 enum intel_display_power_domain domain
;
6926 for_each_power_domain(domain
, crtc
->enabled_power_domains
)
6927 intel_display_power_put(dev
, domain
);
6929 crtc
->enabled_power_domains
= pipe_domains
[crtc
->pipe
];
6932 intel_display_set_init_power(dev
, false);
6935 static void haswell_modeset_global_resources(struct drm_device
*dev
)
6937 modeset_update_power_wells(dev
);
6938 hsw_update_package_c8(dev
);
6941 static int haswell_crtc_mode_set(struct drm_crtc
*crtc
,
6943 struct drm_framebuffer
*fb
)
6945 struct drm_device
*dev
= crtc
->dev
;
6946 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6947 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6948 int plane
= intel_crtc
->plane
;
6951 if (!intel_ddi_pll_select(intel_crtc
))
6953 intel_ddi_pll_enable(intel_crtc
);
6955 if (intel_crtc
->config
.has_dp_encoder
)
6956 intel_dp_set_m_n(intel_crtc
);
6958 intel_crtc
->lowfreq_avail
= false;
6960 intel_set_pipe_timings(intel_crtc
);
6962 if (intel_crtc
->config
.has_pch_encoder
) {
6963 intel_cpu_transcoder_set_m_n(intel_crtc
,
6964 &intel_crtc
->config
.fdi_m_n
);
6967 haswell_set_pipeconf(crtc
);
6969 intel_set_pipe_csc(crtc
);
6971 /* Set up the display plane register */
6972 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
| DISPPLANE_PIPE_CSC_ENABLE
);
6973 POSTING_READ(DSPCNTR(plane
));
6975 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
6980 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
6981 struct intel_crtc_config
*pipe_config
)
6983 struct drm_device
*dev
= crtc
->base
.dev
;
6984 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6985 enum intel_display_power_domain pfit_domain
;
6988 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
6989 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
6991 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
6992 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
6993 enum pipe trans_edp_pipe
;
6994 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
6996 WARN(1, "unknown pipe linked to edp transcoder\n");
6997 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
6998 case TRANS_DDI_EDP_INPUT_A_ON
:
6999 trans_edp_pipe
= PIPE_A
;
7001 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
7002 trans_edp_pipe
= PIPE_B
;
7004 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
7005 trans_edp_pipe
= PIPE_C
;
7009 if (trans_edp_pipe
== crtc
->pipe
)
7010 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
7013 if (!intel_display_power_enabled(dev
,
7014 POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
)))
7017 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
7018 if (!(tmp
& PIPECONF_ENABLE
))
7022 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7023 * DDI E. So just check whether this pipe is wired to DDI E and whether
7024 * the PCH transcoder is on.
7026 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
7027 if ((tmp
& TRANS_DDI_PORT_MASK
) == TRANS_DDI_SELECT_PORT(PORT_E
) &&
7028 I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
7029 pipe_config
->has_pch_encoder
= true;
7031 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
7032 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
7033 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
7035 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
7038 intel_get_pipe_timings(crtc
, pipe_config
);
7040 pfit_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
7041 if (intel_display_power_enabled(dev
, pfit_domain
))
7042 ironlake_get_pfit_config(crtc
, pipe_config
);
7044 if (IS_HASWELL(dev
))
7045 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
7046 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
7048 pipe_config
->pixel_multiplier
= 1;
7053 static int intel_crtc_mode_set(struct drm_crtc
*crtc
,
7055 struct drm_framebuffer
*fb
)
7057 struct drm_device
*dev
= crtc
->dev
;
7058 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7059 struct intel_encoder
*encoder
;
7060 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7061 struct drm_display_mode
*mode
= &intel_crtc
->config
.requested_mode
;
7062 int pipe
= intel_crtc
->pipe
;
7065 drm_vblank_pre_modeset(dev
, pipe
);
7067 ret
= dev_priv
->display
.crtc_mode_set(crtc
, x
, y
, fb
);
7069 drm_vblank_post_modeset(dev
, pipe
);
7074 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
7075 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7076 encoder
->base
.base
.id
,
7077 drm_get_encoder_name(&encoder
->base
),
7078 mode
->base
.id
, mode
->name
);
7079 encoder
->mode_set(encoder
);
7088 } hdmi_audio_clock
[] = {
7089 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175
},
7090 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200
}, /* default per bspec */
7091 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000
},
7092 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027
},
7093 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000
},
7094 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054
},
7095 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176
},
7096 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250
},
7097 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352
},
7098 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500
},
7101 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7102 static u32
audio_config_hdmi_pixel_clock(struct drm_display_mode
*mode
)
7106 for (i
= 0; i
< ARRAY_SIZE(hdmi_audio_clock
); i
++) {
7107 if (mode
->clock
== hdmi_audio_clock
[i
].clock
)
7111 if (i
== ARRAY_SIZE(hdmi_audio_clock
)) {
7112 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode
->clock
);
7116 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7117 hdmi_audio_clock
[i
].clock
,
7118 hdmi_audio_clock
[i
].config
);
7120 return hdmi_audio_clock
[i
].config
;
7123 static bool intel_eld_uptodate(struct drm_connector
*connector
,
7124 int reg_eldv
, uint32_t bits_eldv
,
7125 int reg_elda
, uint32_t bits_elda
,
7128 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
7129 uint8_t *eld
= connector
->eld
;
7132 i
= I915_READ(reg_eldv
);
7141 i
= I915_READ(reg_elda
);
7143 I915_WRITE(reg_elda
, i
);
7145 for (i
= 0; i
< eld
[2]; i
++)
7146 if (I915_READ(reg_edid
) != *((uint32_t *)eld
+ i
))
7152 static void g4x_write_eld(struct drm_connector
*connector
,
7153 struct drm_crtc
*crtc
,
7154 struct drm_display_mode
*mode
)
7156 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
7157 uint8_t *eld
= connector
->eld
;
7162 i
= I915_READ(G4X_AUD_VID_DID
);
7164 if (i
== INTEL_AUDIO_DEVBLC
|| i
== INTEL_AUDIO_DEVCL
)
7165 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
7167 eldv
= G4X_ELDV_DEVCTG
;
7169 if (intel_eld_uptodate(connector
,
7170 G4X_AUD_CNTL_ST
, eldv
,
7171 G4X_AUD_CNTL_ST
, G4X_ELD_ADDR
,
7172 G4X_HDMIW_HDMIEDID
))
7175 i
= I915_READ(G4X_AUD_CNTL_ST
);
7176 i
&= ~(eldv
| G4X_ELD_ADDR
);
7177 len
= (i
>> 9) & 0x1f; /* ELD buffer size */
7178 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
7183 len
= min_t(uint8_t, eld
[2], len
);
7184 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
7185 for (i
= 0; i
< len
; i
++)
7186 I915_WRITE(G4X_HDMIW_HDMIEDID
, *((uint32_t *)eld
+ i
));
7188 i
= I915_READ(G4X_AUD_CNTL_ST
);
7190 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
7193 static void haswell_write_eld(struct drm_connector
*connector
,
7194 struct drm_crtc
*crtc
,
7195 struct drm_display_mode
*mode
)
7197 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
7198 uint8_t *eld
= connector
->eld
;
7199 struct drm_device
*dev
= crtc
->dev
;
7200 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7204 int pipe
= to_intel_crtc(crtc
)->pipe
;
7207 int hdmiw_hdmiedid
= HSW_AUD_EDID_DATA(pipe
);
7208 int aud_cntl_st
= HSW_AUD_DIP_ELD_CTRL(pipe
);
7209 int aud_config
= HSW_AUD_CFG(pipe
);
7210 int aud_cntrl_st2
= HSW_AUD_PIN_ELD_CP_VLD
;
7213 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
7215 /* Audio output enable */
7216 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7217 tmp
= I915_READ(aud_cntrl_st2
);
7218 tmp
|= (AUDIO_OUTPUT_ENABLE_A
<< (pipe
* 4));
7219 I915_WRITE(aud_cntrl_st2
, tmp
);
7221 /* Wait for 1 vertical blank */
7222 intel_wait_for_vblank(dev
, pipe
);
7224 /* Set ELD valid state */
7225 tmp
= I915_READ(aud_cntrl_st2
);
7226 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp
);
7227 tmp
|= (AUDIO_ELD_VALID_A
<< (pipe
* 4));
7228 I915_WRITE(aud_cntrl_st2
, tmp
);
7229 tmp
= I915_READ(aud_cntrl_st2
);
7230 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp
);
7232 /* Enable HDMI mode */
7233 tmp
= I915_READ(aud_config
);
7234 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp
);
7235 /* clear N_programing_enable and N_value_index */
7236 tmp
&= ~(AUD_CONFIG_N_VALUE_INDEX
| AUD_CONFIG_N_PROG_ENABLE
);
7237 I915_WRITE(aud_config
, tmp
);
7239 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
7241 eldv
= AUDIO_ELD_VALID_A
<< (pipe
* 4);
7242 intel_crtc
->eld_vld
= true;
7244 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
7245 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7246 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7247 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
7249 I915_WRITE(aud_config
, audio_config_hdmi_pixel_clock(mode
));
7252 if (intel_eld_uptodate(connector
,
7253 aud_cntrl_st2
, eldv
,
7254 aud_cntl_st
, IBX_ELD_ADDRESS
,
7258 i
= I915_READ(aud_cntrl_st2
);
7260 I915_WRITE(aud_cntrl_st2
, i
);
7265 i
= I915_READ(aud_cntl_st
);
7266 i
&= ~IBX_ELD_ADDRESS
;
7267 I915_WRITE(aud_cntl_st
, i
);
7268 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
7269 DRM_DEBUG_DRIVER("port num:%d\n", i
);
7271 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
7272 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
7273 for (i
= 0; i
< len
; i
++)
7274 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
7276 i
= I915_READ(aud_cntrl_st2
);
7278 I915_WRITE(aud_cntrl_st2
, i
);
7282 static void ironlake_write_eld(struct drm_connector
*connector
,
7283 struct drm_crtc
*crtc
,
7284 struct drm_display_mode
*mode
)
7286 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
7287 uint8_t *eld
= connector
->eld
;
7295 int pipe
= to_intel_crtc(crtc
)->pipe
;
7297 if (HAS_PCH_IBX(connector
->dev
)) {
7298 hdmiw_hdmiedid
= IBX_HDMIW_HDMIEDID(pipe
);
7299 aud_config
= IBX_AUD_CFG(pipe
);
7300 aud_cntl_st
= IBX_AUD_CNTL_ST(pipe
);
7301 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
7302 } else if (IS_VALLEYVIEW(connector
->dev
)) {
7303 hdmiw_hdmiedid
= VLV_HDMIW_HDMIEDID(pipe
);
7304 aud_config
= VLV_AUD_CFG(pipe
);
7305 aud_cntl_st
= VLV_AUD_CNTL_ST(pipe
);
7306 aud_cntrl_st2
= VLV_AUD_CNTL_ST2
;
7308 hdmiw_hdmiedid
= CPT_HDMIW_HDMIEDID(pipe
);
7309 aud_config
= CPT_AUD_CFG(pipe
);
7310 aud_cntl_st
= CPT_AUD_CNTL_ST(pipe
);
7311 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
7314 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
7316 if (IS_VALLEYVIEW(connector
->dev
)) {
7317 struct intel_encoder
*intel_encoder
;
7318 struct intel_digital_port
*intel_dig_port
;
7320 intel_encoder
= intel_attached_encoder(connector
);
7321 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
7322 i
= intel_dig_port
->port
;
7324 i
= I915_READ(aud_cntl_st
);
7325 i
= (i
>> 29) & DIP_PORT_SEL_MASK
;
7326 /* DIP_Port_Select, 0x1 = PortB */
7330 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7331 /* operate blindly on all ports */
7332 eldv
= IBX_ELD_VALIDB
;
7333 eldv
|= IBX_ELD_VALIDB
<< 4;
7334 eldv
|= IBX_ELD_VALIDB
<< 8;
7336 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i
));
7337 eldv
= IBX_ELD_VALIDB
<< ((i
- 1) * 4);
7340 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
7341 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7342 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7343 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
7345 I915_WRITE(aud_config
, audio_config_hdmi_pixel_clock(mode
));
7348 if (intel_eld_uptodate(connector
,
7349 aud_cntrl_st2
, eldv
,
7350 aud_cntl_st
, IBX_ELD_ADDRESS
,
7354 i
= I915_READ(aud_cntrl_st2
);
7356 I915_WRITE(aud_cntrl_st2
, i
);
7361 i
= I915_READ(aud_cntl_st
);
7362 i
&= ~IBX_ELD_ADDRESS
;
7363 I915_WRITE(aud_cntl_st
, i
);
7365 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
7366 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
7367 for (i
= 0; i
< len
; i
++)
7368 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
7370 i
= I915_READ(aud_cntrl_st2
);
7372 I915_WRITE(aud_cntrl_st2
, i
);
7375 void intel_write_eld(struct drm_encoder
*encoder
,
7376 struct drm_display_mode
*mode
)
7378 struct drm_crtc
*crtc
= encoder
->crtc
;
7379 struct drm_connector
*connector
;
7380 struct drm_device
*dev
= encoder
->dev
;
7381 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7383 connector
= drm_select_eld(encoder
, mode
);
7387 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7389 drm_get_connector_name(connector
),
7390 connector
->encoder
->base
.id
,
7391 drm_get_encoder_name(connector
->encoder
));
7393 connector
->eld
[6] = drm_av_sync_delay(connector
, mode
) / 2;
7395 if (dev_priv
->display
.write_eld
)
7396 dev_priv
->display
.write_eld(connector
, crtc
, mode
);
7399 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
7401 struct drm_device
*dev
= crtc
->dev
;
7402 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7403 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7404 bool visible
= base
!= 0;
7407 if (intel_crtc
->cursor_visible
== visible
)
7410 cntl
= I915_READ(_CURACNTR
);
7412 /* On these chipsets we can only modify the base whilst
7413 * the cursor is disabled.
7415 I915_WRITE(_CURABASE
, base
);
7417 cntl
&= ~(CURSOR_FORMAT_MASK
);
7418 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7419 cntl
|= CURSOR_ENABLE
|
7420 CURSOR_GAMMA_ENABLE
|
7423 cntl
&= ~(CURSOR_ENABLE
| CURSOR_GAMMA_ENABLE
);
7424 I915_WRITE(_CURACNTR
, cntl
);
7426 intel_crtc
->cursor_visible
= visible
;
7429 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
7431 struct drm_device
*dev
= crtc
->dev
;
7432 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7433 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7434 int pipe
= intel_crtc
->pipe
;
7435 bool visible
= base
!= 0;
7437 if (intel_crtc
->cursor_visible
!= visible
) {
7438 uint32_t cntl
= I915_READ(CURCNTR(pipe
));
7440 cntl
&= ~(CURSOR_MODE
| MCURSOR_PIPE_SELECT
);
7441 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
7442 cntl
|= pipe
<< 28; /* Connect to correct pipe */
7444 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
7445 cntl
|= CURSOR_MODE_DISABLE
;
7447 I915_WRITE(CURCNTR(pipe
), cntl
);
7449 intel_crtc
->cursor_visible
= visible
;
7451 /* and commit changes on next vblank */
7452 POSTING_READ(CURCNTR(pipe
));
7453 I915_WRITE(CURBASE(pipe
), base
);
7454 POSTING_READ(CURBASE(pipe
));
7457 static void ivb_update_cursor(struct drm_crtc
*crtc
, u32 base
)
7459 struct drm_device
*dev
= crtc
->dev
;
7460 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7461 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7462 int pipe
= intel_crtc
->pipe
;
7463 bool visible
= base
!= 0;
7465 if (intel_crtc
->cursor_visible
!= visible
) {
7466 uint32_t cntl
= I915_READ(CURCNTR_IVB(pipe
));
7468 cntl
&= ~CURSOR_MODE
;
7469 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
7471 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
7472 cntl
|= CURSOR_MODE_DISABLE
;
7474 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
7475 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
7476 cntl
&= ~CURSOR_TRICKLE_FEED_DISABLE
;
7478 I915_WRITE(CURCNTR_IVB(pipe
), cntl
);
7480 intel_crtc
->cursor_visible
= visible
;
7482 /* and commit changes on next vblank */
7483 POSTING_READ(CURCNTR_IVB(pipe
));
7484 I915_WRITE(CURBASE_IVB(pipe
), base
);
7485 POSTING_READ(CURBASE_IVB(pipe
));
7488 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7489 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
7492 struct drm_device
*dev
= crtc
->dev
;
7493 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7494 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7495 int pipe
= intel_crtc
->pipe
;
7496 int x
= intel_crtc
->cursor_x
;
7497 int y
= intel_crtc
->cursor_y
;
7498 u32 base
= 0, pos
= 0;
7502 base
= intel_crtc
->cursor_addr
;
7504 if (x
>= intel_crtc
->config
.pipe_src_w
)
7507 if (y
>= intel_crtc
->config
.pipe_src_h
)
7511 if (x
+ intel_crtc
->cursor_width
<= 0)
7514 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
7517 pos
|= x
<< CURSOR_X_SHIFT
;
7520 if (y
+ intel_crtc
->cursor_height
<= 0)
7523 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
7526 pos
|= y
<< CURSOR_Y_SHIFT
;
7528 visible
= base
!= 0;
7529 if (!visible
&& !intel_crtc
->cursor_visible
)
7532 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
7533 I915_WRITE(CURPOS_IVB(pipe
), pos
);
7534 ivb_update_cursor(crtc
, base
);
7536 I915_WRITE(CURPOS(pipe
), pos
);
7537 if (IS_845G(dev
) || IS_I865G(dev
))
7538 i845_update_cursor(crtc
, base
);
7540 i9xx_update_cursor(crtc
, base
);
7544 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
7545 struct drm_file
*file
,
7547 uint32_t width
, uint32_t height
)
7549 struct drm_device
*dev
= crtc
->dev
;
7550 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7551 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7552 struct drm_i915_gem_object
*obj
;
7556 /* if we want to turn off the cursor ignore width and height */
7558 DRM_DEBUG_KMS("cursor off\n");
7561 mutex_lock(&dev
->struct_mutex
);
7565 /* Currently we only support 64x64 cursors */
7566 if (width
!= 64 || height
!= 64) {
7567 DRM_ERROR("we currently only support 64x64 cursors\n");
7571 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
7572 if (&obj
->base
== NULL
)
7575 if (obj
->base
.size
< width
* height
* 4) {
7576 DRM_ERROR("buffer is to small\n");
7581 /* we only need to pin inside GTT if cursor is non-phy */
7582 mutex_lock(&dev
->struct_mutex
);
7583 if (!dev_priv
->info
->cursor_needs_physical
) {
7586 if (obj
->tiling_mode
) {
7587 DRM_ERROR("cursor cannot be tiled\n");
7592 /* Note that the w/a also requires 2 PTE of padding following
7593 * the bo. We currently fill all unused PTE with the shadow
7594 * page and so we should always have valid PTE following the
7595 * cursor preventing the VT-d warning.
7598 if (need_vtd_wa(dev
))
7599 alignment
= 64*1024;
7601 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, NULL
);
7603 DRM_ERROR("failed to move cursor bo into the GTT\n");
7607 ret
= i915_gem_object_put_fence(obj
);
7609 DRM_ERROR("failed to release fence for cursor");
7613 addr
= i915_gem_obj_ggtt_offset(obj
);
7615 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
7616 ret
= i915_gem_attach_phys_object(dev
, obj
,
7617 (intel_crtc
->pipe
== 0) ? I915_GEM_PHYS_CURSOR_0
: I915_GEM_PHYS_CURSOR_1
,
7620 DRM_ERROR("failed to attach phys object\n");
7623 addr
= obj
->phys_obj
->handle
->busaddr
;
7627 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
7630 if (intel_crtc
->cursor_bo
) {
7631 if (dev_priv
->info
->cursor_needs_physical
) {
7632 if (intel_crtc
->cursor_bo
!= obj
)
7633 i915_gem_detach_phys_object(dev
, intel_crtc
->cursor_bo
);
7635 i915_gem_object_unpin_from_display_plane(intel_crtc
->cursor_bo
);
7636 drm_gem_object_unreference(&intel_crtc
->cursor_bo
->base
);
7639 mutex_unlock(&dev
->struct_mutex
);
7641 intel_crtc
->cursor_addr
= addr
;
7642 intel_crtc
->cursor_bo
= obj
;
7643 intel_crtc
->cursor_width
= width
;
7644 intel_crtc
->cursor_height
= height
;
7646 if (intel_crtc
->active
)
7647 intel_crtc_update_cursor(crtc
, intel_crtc
->cursor_bo
!= NULL
);
7651 i915_gem_object_unpin_from_display_plane(obj
);
7653 mutex_unlock(&dev
->struct_mutex
);
7655 drm_gem_object_unreference_unlocked(&obj
->base
);
7659 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
7661 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7663 intel_crtc
->cursor_x
= clamp_t(int, x
, SHRT_MIN
, SHRT_MAX
);
7664 intel_crtc
->cursor_y
= clamp_t(int, y
, SHRT_MIN
, SHRT_MAX
);
7666 if (intel_crtc
->active
)
7667 intel_crtc_update_cursor(crtc
, intel_crtc
->cursor_bo
!= NULL
);
7672 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
7673 u16
*blue
, uint32_t start
, uint32_t size
)
7675 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
7676 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7678 for (i
= start
; i
< end
; i
++) {
7679 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
7680 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
7681 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
7684 intel_crtc_load_lut(crtc
);
7687 /* VESA 640x480x72Hz mode to set on the pipe */
7688 static struct drm_display_mode load_detect_mode
= {
7689 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
7690 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
7693 static struct drm_framebuffer
*
7694 intel_framebuffer_create(struct drm_device
*dev
,
7695 struct drm_mode_fb_cmd2
*mode_cmd
,
7696 struct drm_i915_gem_object
*obj
)
7698 struct intel_framebuffer
*intel_fb
;
7701 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
7703 drm_gem_object_unreference_unlocked(&obj
->base
);
7704 return ERR_PTR(-ENOMEM
);
7707 ret
= i915_mutex_lock_interruptible(dev
);
7711 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
7712 mutex_unlock(&dev
->struct_mutex
);
7716 return &intel_fb
->base
;
7718 drm_gem_object_unreference_unlocked(&obj
->base
);
7721 return ERR_PTR(ret
);
7725 intel_framebuffer_pitch_for_width(int width
, int bpp
)
7727 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
7728 return ALIGN(pitch
, 64);
7732 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
7734 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
7735 return ALIGN(pitch
* mode
->vdisplay
, PAGE_SIZE
);
7738 static struct drm_framebuffer
*
7739 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
7740 struct drm_display_mode
*mode
,
7743 struct drm_i915_gem_object
*obj
;
7744 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
7746 obj
= i915_gem_alloc_object(dev
,
7747 intel_framebuffer_size_for_mode(mode
, bpp
));
7749 return ERR_PTR(-ENOMEM
);
7751 mode_cmd
.width
= mode
->hdisplay
;
7752 mode_cmd
.height
= mode
->vdisplay
;
7753 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
7755 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
7757 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
7760 static struct drm_framebuffer
*
7761 mode_fits_in_fbdev(struct drm_device
*dev
,
7762 struct drm_display_mode
*mode
)
7764 #ifdef CONFIG_DRM_I915_FBDEV
7765 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7766 struct drm_i915_gem_object
*obj
;
7767 struct drm_framebuffer
*fb
;
7769 if (dev_priv
->fbdev
== NULL
)
7772 obj
= dev_priv
->fbdev
->ifb
.obj
;
7776 fb
= &dev_priv
->fbdev
->ifb
.base
;
7777 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
7778 fb
->bits_per_pixel
))
7781 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
7790 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
7791 struct drm_display_mode
*mode
,
7792 struct intel_load_detect_pipe
*old
)
7794 struct intel_crtc
*intel_crtc
;
7795 struct intel_encoder
*intel_encoder
=
7796 intel_attached_encoder(connector
);
7797 struct drm_crtc
*possible_crtc
;
7798 struct drm_encoder
*encoder
= &intel_encoder
->base
;
7799 struct drm_crtc
*crtc
= NULL
;
7800 struct drm_device
*dev
= encoder
->dev
;
7801 struct drm_framebuffer
*fb
;
7804 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7805 connector
->base
.id
, drm_get_connector_name(connector
),
7806 encoder
->base
.id
, drm_get_encoder_name(encoder
));
7809 * Algorithm gets a little messy:
7811 * - if the connector already has an assigned crtc, use it (but make
7812 * sure it's on first)
7814 * - try to find the first unused crtc that can drive this connector,
7815 * and use that if we find one
7818 /* See if we already have a CRTC for this connector */
7819 if (encoder
->crtc
) {
7820 crtc
= encoder
->crtc
;
7822 mutex_lock(&crtc
->mutex
);
7824 old
->dpms_mode
= connector
->dpms
;
7825 old
->load_detect_temp
= false;
7827 /* Make sure the crtc and connector are running */
7828 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
7829 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
7834 /* Find an unused one (if possible) */
7835 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
7837 if (!(encoder
->possible_crtcs
& (1 << i
)))
7839 if (!possible_crtc
->enabled
) {
7840 crtc
= possible_crtc
;
7846 * If we didn't find an unused CRTC, don't use any.
7849 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7853 mutex_lock(&crtc
->mutex
);
7854 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
7855 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
7857 intel_crtc
= to_intel_crtc(crtc
);
7858 old
->dpms_mode
= connector
->dpms
;
7859 old
->load_detect_temp
= true;
7860 old
->release_fb
= NULL
;
7863 mode
= &load_detect_mode
;
7865 /* We need a framebuffer large enough to accommodate all accesses
7866 * that the plane may generate whilst we perform load detection.
7867 * We can not rely on the fbcon either being present (we get called
7868 * during its initialisation to detect all boot displays, or it may
7869 * not even exist) or that it is large enough to satisfy the
7872 fb
= mode_fits_in_fbdev(dev
, mode
);
7874 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7875 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
7876 old
->release_fb
= fb
;
7878 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7880 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7881 mutex_unlock(&crtc
->mutex
);
7885 if (intel_set_mode(crtc
, mode
, 0, 0, fb
)) {
7886 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7887 if (old
->release_fb
)
7888 old
->release_fb
->funcs
->destroy(old
->release_fb
);
7889 mutex_unlock(&crtc
->mutex
);
7893 /* let the connector get through one full cycle before testing */
7894 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
7898 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
7899 struct intel_load_detect_pipe
*old
)
7901 struct intel_encoder
*intel_encoder
=
7902 intel_attached_encoder(connector
);
7903 struct drm_encoder
*encoder
= &intel_encoder
->base
;
7904 struct drm_crtc
*crtc
= encoder
->crtc
;
7906 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7907 connector
->base
.id
, drm_get_connector_name(connector
),
7908 encoder
->base
.id
, drm_get_encoder_name(encoder
));
7910 if (old
->load_detect_temp
) {
7911 to_intel_connector(connector
)->new_encoder
= NULL
;
7912 intel_encoder
->new_crtc
= NULL
;
7913 intel_set_mode(crtc
, NULL
, 0, 0, NULL
);
7915 if (old
->release_fb
) {
7916 drm_framebuffer_unregister_private(old
->release_fb
);
7917 drm_framebuffer_unreference(old
->release_fb
);
7920 mutex_unlock(&crtc
->mutex
);
7924 /* Switch crtc and encoder back off if necessary */
7925 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
7926 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
7928 mutex_unlock(&crtc
->mutex
);
7931 static int i9xx_pll_refclk(struct drm_device
*dev
,
7932 const struct intel_crtc_config
*pipe_config
)
7934 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7935 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
7937 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
7938 return dev_priv
->vbt
.lvds_ssc_freq
;
7939 else if (HAS_PCH_SPLIT(dev
))
7941 else if (!IS_GEN2(dev
))
7947 /* Returns the clock of the currently programmed mode of the given pipe. */
7948 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
7949 struct intel_crtc_config
*pipe_config
)
7951 struct drm_device
*dev
= crtc
->base
.dev
;
7952 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7953 int pipe
= pipe_config
->cpu_transcoder
;
7954 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
7956 intel_clock_t clock
;
7957 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
7959 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
7960 fp
= pipe_config
->dpll_hw_state
.fp0
;
7962 fp
= pipe_config
->dpll_hw_state
.fp1
;
7964 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
7965 if (IS_PINEVIEW(dev
)) {
7966 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
7967 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
7969 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
7970 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
7973 if (!IS_GEN2(dev
)) {
7974 if (IS_PINEVIEW(dev
))
7975 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
7976 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
7978 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
7979 DPLL_FPA01_P1_POST_DIV_SHIFT
);
7981 switch (dpll
& DPLL_MODE_MASK
) {
7982 case DPLLB_MODE_DAC_SERIAL
:
7983 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
7986 case DPLLB_MODE_LVDS
:
7987 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
7991 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7992 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
7996 if (IS_PINEVIEW(dev
))
7997 pineview_clock(refclk
, &clock
);
7999 i9xx_clock(refclk
, &clock
);
8001 u32 lvds
= IS_I830(dev
) ? 0 : I915_READ(LVDS
);
8002 bool is_lvds
= (pipe
== 1) && (lvds
& LVDS_PORT_EN
);
8005 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
8006 DPLL_FPA01_P1_POST_DIV_SHIFT
);
8008 if (lvds
& LVDS_CLKB_POWER_UP
)
8013 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
8016 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
8017 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
8019 if (dpll
& PLL_P2_DIVIDE_BY_4
)
8025 i9xx_clock(refclk
, &clock
);
8029 * This value includes pixel_multiplier. We will use
8030 * port_clock to compute adjusted_mode.crtc_clock in the
8031 * encoder's get_config() function.
8033 pipe_config
->port_clock
= clock
.dot
;
8036 int intel_dotclock_calculate(int link_freq
,
8037 const struct intel_link_m_n
*m_n
)
8040 * The calculation for the data clock is:
8041 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8042 * But we want to avoid losing precison if possible, so:
8043 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8045 * and the link clock is simpler:
8046 * link_clock = (m * link_clock) / n
8052 return div_u64((u64
)m_n
->link_m
* link_freq
, m_n
->link_n
);
8055 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
8056 struct intel_crtc_config
*pipe_config
)
8058 struct drm_device
*dev
= crtc
->base
.dev
;
8060 /* read out port_clock from the DPLL */
8061 i9xx_crtc_clock_get(crtc
, pipe_config
);
8064 * This value does not include pixel_multiplier.
8065 * We will check that port_clock and adjusted_mode.crtc_clock
8066 * agree once we know their relationship in the encoder's
8067 * get_config() function.
8069 pipe_config
->adjusted_mode
.crtc_clock
=
8070 intel_dotclock_calculate(intel_fdi_link_freq(dev
) * 10000,
8071 &pipe_config
->fdi_m_n
);
8074 /** Returns the currently programmed mode of the given pipe. */
8075 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
8076 struct drm_crtc
*crtc
)
8078 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8079 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8080 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
8081 struct drm_display_mode
*mode
;
8082 struct intel_crtc_config pipe_config
;
8083 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
8084 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
8085 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
8086 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
8087 enum pipe pipe
= intel_crtc
->pipe
;
8089 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
8094 * Construct a pipe_config sufficient for getting the clock info
8095 * back out of crtc_clock_get.
8097 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8098 * to use a real value here instead.
8100 pipe_config
.cpu_transcoder
= (enum transcoder
) pipe
;
8101 pipe_config
.pixel_multiplier
= 1;
8102 pipe_config
.dpll_hw_state
.dpll
= I915_READ(DPLL(pipe
));
8103 pipe_config
.dpll_hw_state
.fp0
= I915_READ(FP0(pipe
));
8104 pipe_config
.dpll_hw_state
.fp1
= I915_READ(FP1(pipe
));
8105 i9xx_crtc_clock_get(intel_crtc
, &pipe_config
);
8107 mode
->clock
= pipe_config
.port_clock
/ pipe_config
.pixel_multiplier
;
8108 mode
->hdisplay
= (htot
& 0xffff) + 1;
8109 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
8110 mode
->hsync_start
= (hsync
& 0xffff) + 1;
8111 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
8112 mode
->vdisplay
= (vtot
& 0xffff) + 1;
8113 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
8114 mode
->vsync_start
= (vsync
& 0xffff) + 1;
8115 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
8117 drm_mode_set_name(mode
);
8122 static void intel_increase_pllclock(struct drm_crtc
*crtc
)
8124 struct drm_device
*dev
= crtc
->dev
;
8125 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8126 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8127 int pipe
= intel_crtc
->pipe
;
8128 int dpll_reg
= DPLL(pipe
);
8131 if (HAS_PCH_SPLIT(dev
))
8134 if (!dev_priv
->lvds_downclock_avail
)
8137 dpll
= I915_READ(dpll_reg
);
8138 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
8139 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8141 assert_panel_unlocked(dev_priv
, pipe
);
8143 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
8144 I915_WRITE(dpll_reg
, dpll
);
8145 intel_wait_for_vblank(dev
, pipe
);
8147 dpll
= I915_READ(dpll_reg
);
8148 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
8149 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8153 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
8155 struct drm_device
*dev
= crtc
->dev
;
8156 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8157 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8159 if (HAS_PCH_SPLIT(dev
))
8162 if (!dev_priv
->lvds_downclock_avail
)
8166 * Since this is called by a timer, we should never get here in
8169 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
8170 int pipe
= intel_crtc
->pipe
;
8171 int dpll_reg
= DPLL(pipe
);
8174 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8176 assert_panel_unlocked(dev_priv
, pipe
);
8178 dpll
= I915_READ(dpll_reg
);
8179 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
8180 I915_WRITE(dpll_reg
, dpll
);
8181 intel_wait_for_vblank(dev
, pipe
);
8182 dpll
= I915_READ(dpll_reg
);
8183 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
8184 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8189 void intel_mark_busy(struct drm_device
*dev
)
8191 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8193 hsw_package_c8_gpu_busy(dev_priv
);
8194 i915_update_gfx_val(dev_priv
);
8197 void intel_mark_idle(struct drm_device
*dev
)
8199 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8200 struct drm_crtc
*crtc
;
8202 hsw_package_c8_gpu_idle(dev_priv
);
8204 if (!i915_powersave
)
8207 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
8211 intel_decrease_pllclock(crtc
);
8214 if (dev_priv
->info
->gen
>= 6)
8215 gen6_rps_idle(dev
->dev_private
);
8218 void intel_mark_fb_busy(struct drm_i915_gem_object
*obj
,
8219 struct intel_ring_buffer
*ring
)
8221 struct drm_device
*dev
= obj
->base
.dev
;
8222 struct drm_crtc
*crtc
;
8224 if (!i915_powersave
)
8227 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
8231 if (to_intel_framebuffer(crtc
->fb
)->obj
!= obj
)
8234 intel_increase_pllclock(crtc
);
8235 if (ring
&& intel_fbc_enabled(dev
))
8236 ring
->fbc_dirty
= true;
8240 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
8242 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8243 struct drm_device
*dev
= crtc
->dev
;
8244 struct intel_unpin_work
*work
;
8245 unsigned long flags
;
8247 spin_lock_irqsave(&dev
->event_lock
, flags
);
8248 work
= intel_crtc
->unpin_work
;
8249 intel_crtc
->unpin_work
= NULL
;
8250 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
8253 cancel_work_sync(&work
->work
);
8257 intel_crtc_cursor_set(crtc
, NULL
, 0, 0, 0);
8259 drm_crtc_cleanup(crtc
);
8264 static void intel_unpin_work_fn(struct work_struct
*__work
)
8266 struct intel_unpin_work
*work
=
8267 container_of(__work
, struct intel_unpin_work
, work
);
8268 struct drm_device
*dev
= work
->crtc
->dev
;
8270 mutex_lock(&dev
->struct_mutex
);
8271 intel_unpin_fb_obj(work
->old_fb_obj
);
8272 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
8273 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
8275 intel_update_fbc(dev
);
8276 mutex_unlock(&dev
->struct_mutex
);
8278 BUG_ON(atomic_read(&to_intel_crtc(work
->crtc
)->unpin_work_count
) == 0);
8279 atomic_dec(&to_intel_crtc(work
->crtc
)->unpin_work_count
);
8284 static void do_intel_finish_page_flip(struct drm_device
*dev
,
8285 struct drm_crtc
*crtc
)
8287 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8288 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8289 struct intel_unpin_work
*work
;
8290 unsigned long flags
;
8292 /* Ignore early vblank irqs */
8293 if (intel_crtc
== NULL
)
8296 spin_lock_irqsave(&dev
->event_lock
, flags
);
8297 work
= intel_crtc
->unpin_work
;
8299 /* Ensure we don't miss a work->pending update ... */
8302 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
8303 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
8307 /* and that the unpin work is consistent wrt ->pending. */
8310 intel_crtc
->unpin_work
= NULL
;
8313 drm_send_vblank_event(dev
, intel_crtc
->pipe
, work
->event
);
8315 drm_vblank_put(dev
, intel_crtc
->pipe
);
8317 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
8319 wake_up_all(&dev_priv
->pending_flip_queue
);
8321 queue_work(dev_priv
->wq
, &work
->work
);
8323 trace_i915_flip_complete(intel_crtc
->plane
, work
->pending_flip_obj
);
8326 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
8328 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8329 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
8331 do_intel_finish_page_flip(dev
, crtc
);
8334 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
8336 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8337 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
8339 do_intel_finish_page_flip(dev
, crtc
);
8342 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
8344 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8345 struct intel_crtc
*intel_crtc
=
8346 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
8347 unsigned long flags
;
8349 /* NB: An MMIO update of the plane base pointer will also
8350 * generate a page-flip completion irq, i.e. every modeset
8351 * is also accompanied by a spurious intel_prepare_page_flip().
8353 spin_lock_irqsave(&dev
->event_lock
, flags
);
8354 if (intel_crtc
->unpin_work
)
8355 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
8356 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
8359 inline static void intel_mark_page_flip_active(struct intel_crtc
*intel_crtc
)
8361 /* Ensure that the work item is consistent when activating it ... */
8363 atomic_set(&intel_crtc
->unpin_work
->pending
, INTEL_FLIP_PENDING
);
8364 /* and that it is marked active as soon as the irq could fire. */
8368 static int intel_gen2_queue_flip(struct drm_device
*dev
,
8369 struct drm_crtc
*crtc
,
8370 struct drm_framebuffer
*fb
,
8371 struct drm_i915_gem_object
*obj
,
8374 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8375 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8377 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
8380 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
8384 ret
= intel_ring_begin(ring
, 6);
8388 /* Can't queue multiple flips, so wait for the previous
8389 * one to finish before executing the next.
8391 if (intel_crtc
->plane
)
8392 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
8394 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
8395 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
8396 intel_ring_emit(ring
, MI_NOOP
);
8397 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
8398 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
8399 intel_ring_emit(ring
, fb
->pitches
[0]);
8400 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
8401 intel_ring_emit(ring
, 0); /* aux display base address, unused */
8403 intel_mark_page_flip_active(intel_crtc
);
8404 __intel_ring_advance(ring
);
8408 intel_unpin_fb_obj(obj
);
8413 static int intel_gen3_queue_flip(struct drm_device
*dev
,
8414 struct drm_crtc
*crtc
,
8415 struct drm_framebuffer
*fb
,
8416 struct drm_i915_gem_object
*obj
,
8419 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8420 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8422 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
8425 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
8429 ret
= intel_ring_begin(ring
, 6);
8433 if (intel_crtc
->plane
)
8434 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
8436 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
8437 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
8438 intel_ring_emit(ring
, MI_NOOP
);
8439 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
8440 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
8441 intel_ring_emit(ring
, fb
->pitches
[0]);
8442 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
8443 intel_ring_emit(ring
, MI_NOOP
);
8445 intel_mark_page_flip_active(intel_crtc
);
8446 __intel_ring_advance(ring
);
8450 intel_unpin_fb_obj(obj
);
8455 static int intel_gen4_queue_flip(struct drm_device
*dev
,
8456 struct drm_crtc
*crtc
,
8457 struct drm_framebuffer
*fb
,
8458 struct drm_i915_gem_object
*obj
,
8461 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8462 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8463 uint32_t pf
, pipesrc
;
8464 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
8467 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
8471 ret
= intel_ring_begin(ring
, 4);
8475 /* i965+ uses the linear or tiled offsets from the
8476 * Display Registers (which do not change across a page-flip)
8477 * so we need only reprogram the base address.
8479 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
8480 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
8481 intel_ring_emit(ring
, fb
->pitches
[0]);
8482 intel_ring_emit(ring
,
8483 (i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
) |
8486 /* XXX Enabling the panel-fitter across page-flip is so far
8487 * untested on non-native modes, so ignore it for now.
8488 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8491 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
8492 intel_ring_emit(ring
, pf
| pipesrc
);
8494 intel_mark_page_flip_active(intel_crtc
);
8495 __intel_ring_advance(ring
);
8499 intel_unpin_fb_obj(obj
);
8504 static int intel_gen6_queue_flip(struct drm_device
*dev
,
8505 struct drm_crtc
*crtc
,
8506 struct drm_framebuffer
*fb
,
8507 struct drm_i915_gem_object
*obj
,
8510 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8511 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8512 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
8513 uint32_t pf
, pipesrc
;
8516 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
8520 ret
= intel_ring_begin(ring
, 4);
8524 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
8525 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
8526 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
8527 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
8529 /* Contrary to the suggestions in the documentation,
8530 * "Enable Panel Fitter" does not seem to be required when page
8531 * flipping with a non-native mode, and worse causes a normal
8533 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8536 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
8537 intel_ring_emit(ring
, pf
| pipesrc
);
8539 intel_mark_page_flip_active(intel_crtc
);
8540 __intel_ring_advance(ring
);
8544 intel_unpin_fb_obj(obj
);
8549 static int intel_gen7_queue_flip(struct drm_device
*dev
,
8550 struct drm_crtc
*crtc
,
8551 struct drm_framebuffer
*fb
,
8552 struct drm_i915_gem_object
*obj
,
8555 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8556 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8557 struct intel_ring_buffer
*ring
;
8558 uint32_t plane_bit
= 0;
8562 if (IS_VALLEYVIEW(dev
) || ring
== NULL
|| ring
->id
!= RCS
)
8563 ring
= &dev_priv
->ring
[BCS
];
8565 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
8569 switch(intel_crtc
->plane
) {
8571 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
8574 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
8577 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
8580 WARN_ONCE(1, "unknown plane in flip command\n");
8586 if (ring
->id
== RCS
)
8590 * BSpec MI_DISPLAY_FLIP for IVB:
8591 * "The full packet must be contained within the same cache line."
8593 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
8594 * cacheline, if we ever start emitting more commands before
8595 * the MI_DISPLAY_FLIP we may need to first emit everything else,
8596 * then do the cacheline alignment, and finally emit the
8599 ret
= intel_ring_cacheline_align(ring
);
8603 ret
= intel_ring_begin(ring
, len
);
8607 /* Unmask the flip-done completion message. Note that the bspec says that
8608 * we should do this for both the BCS and RCS, and that we must not unmask
8609 * more than one flip event at any time (or ensure that one flip message
8610 * can be sent by waiting for flip-done prior to queueing new flips).
8611 * Experimentation says that BCS works despite DERRMR masking all
8612 * flip-done completion events and that unmasking all planes at once
8613 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8614 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8616 if (ring
->id
== RCS
) {
8617 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
8618 intel_ring_emit(ring
, DERRMR
);
8619 intel_ring_emit(ring
, ~(DERRMR_PIPEA_PRI_FLIP_DONE
|
8620 DERRMR_PIPEB_PRI_FLIP_DONE
|
8621 DERRMR_PIPEC_PRI_FLIP_DONE
));
8622 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM(1) |
8623 MI_SRM_LRM_GLOBAL_GTT
);
8624 intel_ring_emit(ring
, DERRMR
);
8625 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
+ 256);
8628 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
8629 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
8630 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
8631 intel_ring_emit(ring
, (MI_NOOP
));
8633 intel_mark_page_flip_active(intel_crtc
);
8634 __intel_ring_advance(ring
);
8638 intel_unpin_fb_obj(obj
);
8643 static int intel_default_queue_flip(struct drm_device
*dev
,
8644 struct drm_crtc
*crtc
,
8645 struct drm_framebuffer
*fb
,
8646 struct drm_i915_gem_object
*obj
,
8652 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
8653 struct drm_framebuffer
*fb
,
8654 struct drm_pending_vblank_event
*event
,
8655 uint32_t page_flip_flags
)
8657 struct drm_device
*dev
= crtc
->dev
;
8658 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8659 struct drm_framebuffer
*old_fb
= crtc
->fb
;
8660 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(fb
)->obj
;
8661 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8662 struct intel_unpin_work
*work
;
8663 unsigned long flags
;
8666 /* Can't change pixel format via MI display flips. */
8667 if (fb
->pixel_format
!= crtc
->fb
->pixel_format
)
8671 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8672 * Note that pitch changes could also affect these register.
8674 if (INTEL_INFO(dev
)->gen
> 3 &&
8675 (fb
->offsets
[0] != crtc
->fb
->offsets
[0] ||
8676 fb
->pitches
[0] != crtc
->fb
->pitches
[0]))
8679 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
8683 work
->event
= event
;
8685 work
->old_fb_obj
= to_intel_framebuffer(old_fb
)->obj
;
8686 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
8688 ret
= drm_vblank_get(dev
, intel_crtc
->pipe
);
8692 /* We borrow the event spin lock for protecting unpin_work */
8693 spin_lock_irqsave(&dev
->event_lock
, flags
);
8694 if (intel_crtc
->unpin_work
) {
8695 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
8697 drm_vblank_put(dev
, intel_crtc
->pipe
);
8699 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8702 intel_crtc
->unpin_work
= work
;
8703 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
8705 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
8706 flush_workqueue(dev_priv
->wq
);
8708 ret
= i915_mutex_lock_interruptible(dev
);
8712 /* Reference the objects for the scheduled work. */
8713 drm_gem_object_reference(&work
->old_fb_obj
->base
);
8714 drm_gem_object_reference(&obj
->base
);
8718 work
->pending_flip_obj
= obj
;
8720 work
->enable_stall_check
= true;
8722 atomic_inc(&intel_crtc
->unpin_work_count
);
8723 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
8725 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
, page_flip_flags
);
8727 goto cleanup_pending
;
8729 intel_disable_fbc(dev
);
8730 intel_mark_fb_busy(obj
, NULL
);
8731 mutex_unlock(&dev
->struct_mutex
);
8733 trace_i915_flip_request(intel_crtc
->plane
, obj
);
8738 atomic_dec(&intel_crtc
->unpin_work_count
);
8740 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
8741 drm_gem_object_unreference(&obj
->base
);
8742 mutex_unlock(&dev
->struct_mutex
);
8745 spin_lock_irqsave(&dev
->event_lock
, flags
);
8746 intel_crtc
->unpin_work
= NULL
;
8747 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
8749 drm_vblank_put(dev
, intel_crtc
->pipe
);
8756 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
8757 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
8758 .load_lut
= intel_crtc_load_lut
,
8762 * intel_modeset_update_staged_output_state
8764 * Updates the staged output configuration state, e.g. after we've read out the
8767 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
8769 struct intel_encoder
*encoder
;
8770 struct intel_connector
*connector
;
8772 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8774 connector
->new_encoder
=
8775 to_intel_encoder(connector
->base
.encoder
);
8778 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8781 to_intel_crtc(encoder
->base
.crtc
);
8786 * intel_modeset_commit_output_state
8788 * This function copies the stage display pipe configuration to the real one.
8790 static void intel_modeset_commit_output_state(struct drm_device
*dev
)
8792 struct intel_encoder
*encoder
;
8793 struct intel_connector
*connector
;
8795 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8797 connector
->base
.encoder
= &connector
->new_encoder
->base
;
8800 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8802 encoder
->base
.crtc
= &encoder
->new_crtc
->base
;
8807 connected_sink_compute_bpp(struct intel_connector
* connector
,
8808 struct intel_crtc_config
*pipe_config
)
8810 int bpp
= pipe_config
->pipe_bpp
;
8812 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8813 connector
->base
.base
.id
,
8814 drm_get_connector_name(&connector
->base
));
8816 /* Don't use an invalid EDID bpc value */
8817 if (connector
->base
.display_info
.bpc
&&
8818 connector
->base
.display_info
.bpc
* 3 < bpp
) {
8819 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8820 bpp
, connector
->base
.display_info
.bpc
*3);
8821 pipe_config
->pipe_bpp
= connector
->base
.display_info
.bpc
*3;
8824 /* Clamp bpp to 8 on screens without EDID 1.4 */
8825 if (connector
->base
.display_info
.bpc
== 0 && bpp
> 24) {
8826 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8828 pipe_config
->pipe_bpp
= 24;
8833 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
8834 struct drm_framebuffer
*fb
,
8835 struct intel_crtc_config
*pipe_config
)
8837 struct drm_device
*dev
= crtc
->base
.dev
;
8838 struct intel_connector
*connector
;
8841 switch (fb
->pixel_format
) {
8843 bpp
= 8*3; /* since we go through a colormap */
8845 case DRM_FORMAT_XRGB1555
:
8846 case DRM_FORMAT_ARGB1555
:
8847 /* checked in intel_framebuffer_init already */
8848 if (WARN_ON(INTEL_INFO(dev
)->gen
> 3))
8850 case DRM_FORMAT_RGB565
:
8851 bpp
= 6*3; /* min is 18bpp */
8853 case DRM_FORMAT_XBGR8888
:
8854 case DRM_FORMAT_ABGR8888
:
8855 /* checked in intel_framebuffer_init already */
8856 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
8858 case DRM_FORMAT_XRGB8888
:
8859 case DRM_FORMAT_ARGB8888
:
8862 case DRM_FORMAT_XRGB2101010
:
8863 case DRM_FORMAT_ARGB2101010
:
8864 case DRM_FORMAT_XBGR2101010
:
8865 case DRM_FORMAT_ABGR2101010
:
8866 /* checked in intel_framebuffer_init already */
8867 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
8871 /* TODO: gen4+ supports 16 bpc floating point, too. */
8873 DRM_DEBUG_KMS("unsupported depth\n");
8877 pipe_config
->pipe_bpp
= bpp
;
8879 /* Clamp display bpp to EDID value */
8880 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8882 if (!connector
->new_encoder
||
8883 connector
->new_encoder
->new_crtc
!= crtc
)
8886 connected_sink_compute_bpp(connector
, pipe_config
);
8892 static void intel_dump_crtc_timings(const struct drm_display_mode
*mode
)
8894 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8895 "type: 0x%x flags: 0x%x\n",
8897 mode
->crtc_hdisplay
, mode
->crtc_hsync_start
,
8898 mode
->crtc_hsync_end
, mode
->crtc_htotal
,
8899 mode
->crtc_vdisplay
, mode
->crtc_vsync_start
,
8900 mode
->crtc_vsync_end
, mode
->crtc_vtotal
, mode
->type
, mode
->flags
);
8903 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
8904 struct intel_crtc_config
*pipe_config
,
8905 const char *context
)
8907 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc
->base
.base
.id
,
8908 context
, pipe_name(crtc
->pipe
));
8910 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config
->cpu_transcoder
));
8911 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8912 pipe_config
->pipe_bpp
, pipe_config
->dither
);
8913 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8914 pipe_config
->has_pch_encoder
,
8915 pipe_config
->fdi_lanes
,
8916 pipe_config
->fdi_m_n
.gmch_m
, pipe_config
->fdi_m_n
.gmch_n
,
8917 pipe_config
->fdi_m_n
.link_m
, pipe_config
->fdi_m_n
.link_n
,
8918 pipe_config
->fdi_m_n
.tu
);
8919 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8920 pipe_config
->has_dp_encoder
,
8921 pipe_config
->dp_m_n
.gmch_m
, pipe_config
->dp_m_n
.gmch_n
,
8922 pipe_config
->dp_m_n
.link_m
, pipe_config
->dp_m_n
.link_n
,
8923 pipe_config
->dp_m_n
.tu
);
8924 DRM_DEBUG_KMS("requested mode:\n");
8925 drm_mode_debug_printmodeline(&pipe_config
->requested_mode
);
8926 DRM_DEBUG_KMS("adjusted mode:\n");
8927 drm_mode_debug_printmodeline(&pipe_config
->adjusted_mode
);
8928 intel_dump_crtc_timings(&pipe_config
->adjusted_mode
);
8929 DRM_DEBUG_KMS("port clock: %d\n", pipe_config
->port_clock
);
8930 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8931 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
8932 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8933 pipe_config
->gmch_pfit
.control
,
8934 pipe_config
->gmch_pfit
.pgm_ratios
,
8935 pipe_config
->gmch_pfit
.lvds_border_bits
);
8936 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
8937 pipe_config
->pch_pfit
.pos
,
8938 pipe_config
->pch_pfit
.size
,
8939 pipe_config
->pch_pfit
.enabled
? "enabled" : "disabled");
8940 DRM_DEBUG_KMS("ips: %i\n", pipe_config
->ips_enabled
);
8941 DRM_DEBUG_KMS("double wide: %i\n", pipe_config
->double_wide
);
8944 static bool check_encoder_cloning(struct drm_crtc
*crtc
)
8946 int num_encoders
= 0;
8947 bool uncloneable_encoders
= false;
8948 struct intel_encoder
*encoder
;
8950 list_for_each_entry(encoder
, &crtc
->dev
->mode_config
.encoder_list
,
8952 if (&encoder
->new_crtc
->base
!= crtc
)
8956 if (!encoder
->cloneable
)
8957 uncloneable_encoders
= true;
8960 return !(num_encoders
> 1 && uncloneable_encoders
);
8963 static struct intel_crtc_config
*
8964 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
8965 struct drm_framebuffer
*fb
,
8966 struct drm_display_mode
*mode
)
8968 struct drm_device
*dev
= crtc
->dev
;
8969 struct intel_encoder
*encoder
;
8970 struct intel_crtc_config
*pipe_config
;
8971 int plane_bpp
, ret
= -EINVAL
;
8974 if (!check_encoder_cloning(crtc
)) {
8975 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8976 return ERR_PTR(-EINVAL
);
8979 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
8981 return ERR_PTR(-ENOMEM
);
8983 drm_mode_copy(&pipe_config
->adjusted_mode
, mode
);
8984 drm_mode_copy(&pipe_config
->requested_mode
, mode
);
8986 pipe_config
->cpu_transcoder
=
8987 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
8988 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
8991 * Sanitize sync polarity flags based on requested ones. If neither
8992 * positive or negative polarity is requested, treat this as meaning
8993 * negative polarity.
8995 if (!(pipe_config
->adjusted_mode
.flags
&
8996 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
8997 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
8999 if (!(pipe_config
->adjusted_mode
.flags
&
9000 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
9001 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
9003 /* Compute a starting value for pipe_config->pipe_bpp taking the source
9004 * plane pixel format and any sink constraints into account. Returns the
9005 * source plane bpp so that dithering can be selected on mismatches
9006 * after encoders and crtc also have had their say. */
9007 plane_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
9013 * Determine the real pipe dimensions. Note that stereo modes can
9014 * increase the actual pipe size due to the frame doubling and
9015 * insertion of additional space for blanks between the frame. This
9016 * is stored in the crtc timings. We use the requested mode to do this
9017 * computation to clearly distinguish it from the adjusted mode, which
9018 * can be changed by the connectors in the below retry loop.
9020 drm_mode_set_crtcinfo(&pipe_config
->requested_mode
, CRTC_STEREO_DOUBLE
);
9021 pipe_config
->pipe_src_w
= pipe_config
->requested_mode
.crtc_hdisplay
;
9022 pipe_config
->pipe_src_h
= pipe_config
->requested_mode
.crtc_vdisplay
;
9025 /* Ensure the port clock defaults are reset when retrying. */
9026 pipe_config
->port_clock
= 0;
9027 pipe_config
->pixel_multiplier
= 1;
9029 /* Fill in default crtc timings, allow encoders to overwrite them. */
9030 drm_mode_set_crtcinfo(&pipe_config
->adjusted_mode
, CRTC_STEREO_DOUBLE
);
9032 /* Pass our mode to the connectors and the CRTC to give them a chance to
9033 * adjust it according to limitations or connector properties, and also
9034 * a chance to reject the mode entirely.
9036 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9039 if (&encoder
->new_crtc
->base
!= crtc
)
9042 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
9043 DRM_DEBUG_KMS("Encoder config failure\n");
9048 /* Set default port clock if not overwritten by the encoder. Needs to be
9049 * done afterwards in case the encoder adjusts the mode. */
9050 if (!pipe_config
->port_clock
)
9051 pipe_config
->port_clock
= pipe_config
->adjusted_mode
.crtc_clock
9052 * pipe_config
->pixel_multiplier
;
9054 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
9056 DRM_DEBUG_KMS("CRTC fixup failed\n");
9061 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
9066 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9071 pipe_config
->dither
= pipe_config
->pipe_bpp
!= plane_bpp
;
9072 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9073 plane_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
9078 return ERR_PTR(ret
);
9081 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
9082 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9084 intel_modeset_affected_pipes(struct drm_crtc
*crtc
, unsigned *modeset_pipes
,
9085 unsigned *prepare_pipes
, unsigned *disable_pipes
)
9087 struct intel_crtc
*intel_crtc
;
9088 struct drm_device
*dev
= crtc
->dev
;
9089 struct intel_encoder
*encoder
;
9090 struct intel_connector
*connector
;
9091 struct drm_crtc
*tmp_crtc
;
9093 *disable_pipes
= *modeset_pipes
= *prepare_pipes
= 0;
9095 /* Check which crtcs have changed outputs connected to them, these need
9096 * to be part of the prepare_pipes mask. We don't (yet) support global
9097 * modeset across multiple crtcs, so modeset_pipes will only have one
9098 * bit set at most. */
9099 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9101 if (connector
->base
.encoder
== &connector
->new_encoder
->base
)
9104 if (connector
->base
.encoder
) {
9105 tmp_crtc
= connector
->base
.encoder
->crtc
;
9107 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
9110 if (connector
->new_encoder
)
9112 1 << connector
->new_encoder
->new_crtc
->pipe
;
9115 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9117 if (encoder
->base
.crtc
== &encoder
->new_crtc
->base
)
9120 if (encoder
->base
.crtc
) {
9121 tmp_crtc
= encoder
->base
.crtc
;
9123 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
9126 if (encoder
->new_crtc
)
9127 *prepare_pipes
|= 1 << encoder
->new_crtc
->pipe
;
9130 /* Check for any pipes that will be fully disabled ... */
9131 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
9135 /* Don't try to disable disabled crtcs. */
9136 if (!intel_crtc
->base
.enabled
)
9139 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9141 if (encoder
->new_crtc
== intel_crtc
)
9146 *disable_pipes
|= 1 << intel_crtc
->pipe
;
9150 /* set_mode is also used to update properties on life display pipes. */
9151 intel_crtc
= to_intel_crtc(crtc
);
9153 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
9156 * For simplicity do a full modeset on any pipe where the output routing
9157 * changed. We could be more clever, but that would require us to be
9158 * more careful with calling the relevant encoder->mode_set functions.
9161 *modeset_pipes
= *prepare_pipes
;
9163 /* ... and mask these out. */
9164 *modeset_pipes
&= ~(*disable_pipes
);
9165 *prepare_pipes
&= ~(*disable_pipes
);
9168 * HACK: We don't (yet) fully support global modesets. intel_set_config
9169 * obies this rule, but the modeset restore mode of
9170 * intel_modeset_setup_hw_state does not.
9172 *modeset_pipes
&= 1 << intel_crtc
->pipe
;
9173 *prepare_pipes
&= 1 << intel_crtc
->pipe
;
9175 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9176 *modeset_pipes
, *prepare_pipes
, *disable_pipes
);
9179 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
9181 struct drm_encoder
*encoder
;
9182 struct drm_device
*dev
= crtc
->dev
;
9184 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
9185 if (encoder
->crtc
== crtc
)
9192 intel_modeset_update_state(struct drm_device
*dev
, unsigned prepare_pipes
)
9194 struct intel_encoder
*intel_encoder
;
9195 struct intel_crtc
*intel_crtc
;
9196 struct drm_connector
*connector
;
9198 list_for_each_entry(intel_encoder
, &dev
->mode_config
.encoder_list
,
9200 if (!intel_encoder
->base
.crtc
)
9203 intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
9205 if (prepare_pipes
& (1 << intel_crtc
->pipe
))
9206 intel_encoder
->connectors_active
= false;
9209 intel_modeset_commit_output_state(dev
);
9211 /* Update computed state. */
9212 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
9214 intel_crtc
->base
.enabled
= intel_crtc_in_use(&intel_crtc
->base
);
9217 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
9218 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
9221 intel_crtc
= to_intel_crtc(connector
->encoder
->crtc
);
9223 if (prepare_pipes
& (1 << intel_crtc
->pipe
)) {
9224 struct drm_property
*dpms_property
=
9225 dev
->mode_config
.dpms_property
;
9227 connector
->dpms
= DRM_MODE_DPMS_ON
;
9228 drm_object_property_set_value(&connector
->base
,
9232 intel_encoder
= to_intel_encoder(connector
->encoder
);
9233 intel_encoder
->connectors_active
= true;
9239 static bool intel_fuzzy_clock_check(int clock1
, int clock2
)
9243 if (clock1
== clock2
)
9246 if (!clock1
|| !clock2
)
9249 diff
= abs(clock1
- clock2
);
9251 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
9257 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9258 list_for_each_entry((intel_crtc), \
9259 &(dev)->mode_config.crtc_list, \
9261 if (mask & (1 <<(intel_crtc)->pipe))
9264 intel_pipe_config_compare(struct drm_device
*dev
,
9265 struct intel_crtc_config
*current_config
,
9266 struct intel_crtc_config
*pipe_config
)
9268 #define PIPE_CONF_CHECK_X(name) \
9269 if (current_config->name != pipe_config->name) { \
9270 DRM_ERROR("mismatch in " #name " " \
9271 "(expected 0x%08x, found 0x%08x)\n", \
9272 current_config->name, \
9273 pipe_config->name); \
9277 #define PIPE_CONF_CHECK_I(name) \
9278 if (current_config->name != pipe_config->name) { \
9279 DRM_ERROR("mismatch in " #name " " \
9280 "(expected %i, found %i)\n", \
9281 current_config->name, \
9282 pipe_config->name); \
9286 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
9287 if ((current_config->name ^ pipe_config->name) & (mask)) { \
9288 DRM_ERROR("mismatch in " #name "(" #mask ") " \
9289 "(expected %i, found %i)\n", \
9290 current_config->name & (mask), \
9291 pipe_config->name & (mask)); \
9295 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9296 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9297 DRM_ERROR("mismatch in " #name " " \
9298 "(expected %i, found %i)\n", \
9299 current_config->name, \
9300 pipe_config->name); \
9304 #define PIPE_CONF_QUIRK(quirk) \
9305 ((current_config->quirks | pipe_config->quirks) & (quirk))
9307 PIPE_CONF_CHECK_I(cpu_transcoder
);
9309 PIPE_CONF_CHECK_I(has_pch_encoder
);
9310 PIPE_CONF_CHECK_I(fdi_lanes
);
9311 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_m
);
9312 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_n
);
9313 PIPE_CONF_CHECK_I(fdi_m_n
.link_m
);
9314 PIPE_CONF_CHECK_I(fdi_m_n
.link_n
);
9315 PIPE_CONF_CHECK_I(fdi_m_n
.tu
);
9317 PIPE_CONF_CHECK_I(has_dp_encoder
);
9318 PIPE_CONF_CHECK_I(dp_m_n
.gmch_m
);
9319 PIPE_CONF_CHECK_I(dp_m_n
.gmch_n
);
9320 PIPE_CONF_CHECK_I(dp_m_n
.link_m
);
9321 PIPE_CONF_CHECK_I(dp_m_n
.link_n
);
9322 PIPE_CONF_CHECK_I(dp_m_n
.tu
);
9324 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hdisplay
);
9325 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_htotal
);
9326 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_start
);
9327 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_end
);
9328 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_start
);
9329 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_end
);
9331 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vdisplay
);
9332 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vtotal
);
9333 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_start
);
9334 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_end
);
9335 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_start
);
9336 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_end
);
9338 PIPE_CONF_CHECK_I(pixel_multiplier
);
9340 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
9341 DRM_MODE_FLAG_INTERLACE
);
9343 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
9344 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
9345 DRM_MODE_FLAG_PHSYNC
);
9346 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
9347 DRM_MODE_FLAG_NHSYNC
);
9348 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
9349 DRM_MODE_FLAG_PVSYNC
);
9350 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
9351 DRM_MODE_FLAG_NVSYNC
);
9354 PIPE_CONF_CHECK_I(pipe_src_w
);
9355 PIPE_CONF_CHECK_I(pipe_src_h
);
9357 PIPE_CONF_CHECK_I(gmch_pfit
.control
);
9358 /* pfit ratios are autocomputed by the hw on gen4+ */
9359 if (INTEL_INFO(dev
)->gen
< 4)
9360 PIPE_CONF_CHECK_I(gmch_pfit
.pgm_ratios
);
9361 PIPE_CONF_CHECK_I(gmch_pfit
.lvds_border_bits
);
9362 PIPE_CONF_CHECK_I(pch_pfit
.enabled
);
9363 if (current_config
->pch_pfit
.enabled
) {
9364 PIPE_CONF_CHECK_I(pch_pfit
.pos
);
9365 PIPE_CONF_CHECK_I(pch_pfit
.size
);
9368 /* BDW+ don't expose a synchronous way to read the state */
9369 if (IS_HASWELL(dev
))
9370 PIPE_CONF_CHECK_I(ips_enabled
);
9372 PIPE_CONF_CHECK_I(double_wide
);
9374 PIPE_CONF_CHECK_I(shared_dpll
);
9375 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
9376 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
9377 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
9378 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
9380 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5)
9381 PIPE_CONF_CHECK_I(pipe_bpp
);
9383 if (!HAS_DDI(dev
)) {
9384 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode
.crtc_clock
);
9385 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
9388 #undef PIPE_CONF_CHECK_X
9389 #undef PIPE_CONF_CHECK_I
9390 #undef PIPE_CONF_CHECK_FLAGS
9391 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
9392 #undef PIPE_CONF_QUIRK
9398 check_connector_state(struct drm_device
*dev
)
9400 struct intel_connector
*connector
;
9402 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9404 /* This also checks the encoder/connector hw state with the
9405 * ->get_hw_state callbacks. */
9406 intel_connector_check_state(connector
);
9408 WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
9409 "connector's staged encoder doesn't match current encoder\n");
9414 check_encoder_state(struct drm_device
*dev
)
9416 struct intel_encoder
*encoder
;
9417 struct intel_connector
*connector
;
9419 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9421 bool enabled
= false;
9422 bool active
= false;
9423 enum pipe pipe
, tracked_pipe
;
9425 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
9426 encoder
->base
.base
.id
,
9427 drm_get_encoder_name(&encoder
->base
));
9429 WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
9430 "encoder's stage crtc doesn't match current crtc\n");
9431 WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
9432 "encoder's active_connectors set, but no crtc\n");
9434 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9436 if (connector
->base
.encoder
!= &encoder
->base
)
9439 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
9442 WARN(!!encoder
->base
.crtc
!= enabled
,
9443 "encoder's enabled state mismatch "
9444 "(expected %i, found %i)\n",
9445 !!encoder
->base
.crtc
, enabled
);
9446 WARN(active
&& !encoder
->base
.crtc
,
9447 "active encoder with no crtc\n");
9449 WARN(encoder
->connectors_active
!= active
,
9450 "encoder's computed active state doesn't match tracked active state "
9451 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
9453 active
= encoder
->get_hw_state(encoder
, &pipe
);
9454 WARN(active
!= encoder
->connectors_active
,
9455 "encoder's hw state doesn't match sw tracking "
9456 "(expected %i, found %i)\n",
9457 encoder
->connectors_active
, active
);
9459 if (!encoder
->base
.crtc
)
9462 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
9463 WARN(active
&& pipe
!= tracked_pipe
,
9464 "active encoder's pipe doesn't match"
9465 "(expected %i, found %i)\n",
9466 tracked_pipe
, pipe
);
9472 check_crtc_state(struct drm_device
*dev
)
9474 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
9475 struct intel_crtc
*crtc
;
9476 struct intel_encoder
*encoder
;
9477 struct intel_crtc_config pipe_config
;
9479 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
9481 bool enabled
= false;
9482 bool active
= false;
9484 memset(&pipe_config
, 0, sizeof(pipe_config
));
9486 DRM_DEBUG_KMS("[CRTC:%d]\n",
9487 crtc
->base
.base
.id
);
9489 WARN(crtc
->active
&& !crtc
->base
.enabled
,
9490 "active crtc, but not enabled in sw tracking\n");
9492 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9494 if (encoder
->base
.crtc
!= &crtc
->base
)
9497 if (encoder
->connectors_active
)
9501 WARN(active
!= crtc
->active
,
9502 "crtc's computed active state doesn't match tracked active state "
9503 "(expected %i, found %i)\n", active
, crtc
->active
);
9504 WARN(enabled
!= crtc
->base
.enabled
,
9505 "crtc's computed enabled state doesn't match tracked enabled state "
9506 "(expected %i, found %i)\n", enabled
, crtc
->base
.enabled
);
9508 active
= dev_priv
->display
.get_pipe_config(crtc
,
9511 /* hw state is inconsistent with the pipe A quirk */
9512 if (crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
9513 active
= crtc
->active
;
9515 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9518 if (encoder
->base
.crtc
!= &crtc
->base
)
9520 if (encoder
->get_hw_state(encoder
, &pipe
))
9521 encoder
->get_config(encoder
, &pipe_config
);
9524 WARN(crtc
->active
!= active
,
9525 "crtc active state doesn't match with hw state "
9526 "(expected %i, found %i)\n", crtc
->active
, active
);
9529 !intel_pipe_config_compare(dev
, &crtc
->config
, &pipe_config
)) {
9530 WARN(1, "pipe state doesn't match!\n");
9531 intel_dump_pipe_config(crtc
, &pipe_config
,
9533 intel_dump_pipe_config(crtc
, &crtc
->config
,
9540 check_shared_dpll_state(struct drm_device
*dev
)
9542 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
9543 struct intel_crtc
*crtc
;
9544 struct intel_dpll_hw_state dpll_hw_state
;
9547 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
9548 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
9549 int enabled_crtcs
= 0, active_crtcs
= 0;
9552 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
9554 DRM_DEBUG_KMS("%s\n", pll
->name
);
9556 active
= pll
->get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
9558 WARN(pll
->active
> pll
->refcount
,
9559 "more active pll users than references: %i vs %i\n",
9560 pll
->active
, pll
->refcount
);
9561 WARN(pll
->active
&& !pll
->on
,
9562 "pll in active use but not on in sw tracking\n");
9563 WARN(pll
->on
&& !pll
->active
,
9564 "pll in on but not on in use in sw tracking\n");
9565 WARN(pll
->on
!= active
,
9566 "pll on state mismatch (expected %i, found %i)\n",
9569 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
9571 if (crtc
->base
.enabled
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
9573 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
9576 WARN(pll
->active
!= active_crtcs
,
9577 "pll active crtcs mismatch (expected %i, found %i)\n",
9578 pll
->active
, active_crtcs
);
9579 WARN(pll
->refcount
!= enabled_crtcs
,
9580 "pll enabled crtcs mismatch (expected %i, found %i)\n",
9581 pll
->refcount
, enabled_crtcs
);
9583 WARN(pll
->on
&& memcmp(&pll
->hw_state
, &dpll_hw_state
,
9584 sizeof(dpll_hw_state
)),
9585 "pll hw state mismatch\n");
9590 intel_modeset_check_state(struct drm_device
*dev
)
9592 check_connector_state(dev
);
9593 check_encoder_state(dev
);
9594 check_crtc_state(dev
);
9595 check_shared_dpll_state(dev
);
9598 void ironlake_check_encoder_dotclock(const struct intel_crtc_config
*pipe_config
,
9602 * FDI already provided one idea for the dotclock.
9603 * Yell if the encoder disagrees.
9605 WARN(!intel_fuzzy_clock_check(pipe_config
->adjusted_mode
.crtc_clock
, dotclock
),
9606 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9607 pipe_config
->adjusted_mode
.crtc_clock
, dotclock
);
9610 static int __intel_set_mode(struct drm_crtc
*crtc
,
9611 struct drm_display_mode
*mode
,
9612 int x
, int y
, struct drm_framebuffer
*fb
)
9614 struct drm_device
*dev
= crtc
->dev
;
9615 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
9616 struct drm_display_mode
*saved_mode
;
9617 struct intel_crtc_config
*pipe_config
= NULL
;
9618 struct intel_crtc
*intel_crtc
;
9619 unsigned disable_pipes
, prepare_pipes
, modeset_pipes
;
9622 saved_mode
= kmalloc(sizeof(*saved_mode
), GFP_KERNEL
);
9626 intel_modeset_affected_pipes(crtc
, &modeset_pipes
,
9627 &prepare_pipes
, &disable_pipes
);
9629 *saved_mode
= crtc
->mode
;
9631 /* Hack: Because we don't (yet) support global modeset on multiple
9632 * crtcs, we don't keep track of the new mode for more than one crtc.
9633 * Hence simply check whether any bit is set in modeset_pipes in all the
9634 * pieces of code that are not yet converted to deal with mutliple crtcs
9635 * changing their mode at the same time. */
9636 if (modeset_pipes
) {
9637 pipe_config
= intel_modeset_pipe_config(crtc
, fb
, mode
);
9638 if (IS_ERR(pipe_config
)) {
9639 ret
= PTR_ERR(pipe_config
);
9644 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,
9649 * See if the config requires any additional preparation, e.g.
9650 * to adjust global state with pipes off. We need to do this
9651 * here so we can get the modeset_pipe updated config for the new
9652 * mode set on this crtc. For other crtcs we need to use the
9653 * adjusted_mode bits in the crtc directly.
9655 if (IS_VALLEYVIEW(dev
)) {
9656 valleyview_modeset_global_pipes(dev
, &prepare_pipes
,
9657 modeset_pipes
, pipe_config
);
9659 /* may have added more to prepare_pipes than we should */
9660 prepare_pipes
&= ~disable_pipes
;
9663 for_each_intel_crtc_masked(dev
, disable_pipes
, intel_crtc
)
9664 intel_crtc_disable(&intel_crtc
->base
);
9666 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
9667 if (intel_crtc
->base
.enabled
)
9668 dev_priv
->display
.crtc_disable(&intel_crtc
->base
);
9671 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9672 * to set it here already despite that we pass it down the callchain.
9674 if (modeset_pipes
) {
9676 /* mode_set/enable/disable functions rely on a correct pipe
9678 to_intel_crtc(crtc
)->config
= *pipe_config
;
9681 * Calculate and store various constants which
9682 * are later needed by vblank and swap-completion
9683 * timestamping. They are derived from true hwmode.
9685 drm_calc_timestamping_constants(crtc
,
9686 &pipe_config
->adjusted_mode
);
9689 /* Only after disabling all output pipelines that will be changed can we
9690 * update the the output configuration. */
9691 intel_modeset_update_state(dev
, prepare_pipes
);
9693 if (dev_priv
->display
.modeset_global_resources
)
9694 dev_priv
->display
.modeset_global_resources(dev
);
9696 /* Set up the DPLL and any encoders state that needs to adjust or depend
9699 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
9700 ret
= intel_crtc_mode_set(&intel_crtc
->base
,
9706 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9707 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
)
9708 dev_priv
->display
.crtc_enable(&intel_crtc
->base
);
9710 /* FIXME: add subpixel order */
9712 if (ret
&& crtc
->enabled
)
9713 crtc
->mode
= *saved_mode
;
9721 static int intel_set_mode(struct drm_crtc
*crtc
,
9722 struct drm_display_mode
*mode
,
9723 int x
, int y
, struct drm_framebuffer
*fb
)
9727 ret
= __intel_set_mode(crtc
, mode
, x
, y
, fb
);
9730 intel_modeset_check_state(crtc
->dev
);
9735 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
9737 intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
, crtc
->fb
);
9740 #undef for_each_intel_crtc_masked
9742 static void intel_set_config_free(struct intel_set_config
*config
)
9747 kfree(config
->save_connector_encoders
);
9748 kfree(config
->save_encoder_crtcs
);
9752 static int intel_set_config_save_state(struct drm_device
*dev
,
9753 struct intel_set_config
*config
)
9755 struct drm_encoder
*encoder
;
9756 struct drm_connector
*connector
;
9759 config
->save_encoder_crtcs
=
9760 kcalloc(dev
->mode_config
.num_encoder
,
9761 sizeof(struct drm_crtc
*), GFP_KERNEL
);
9762 if (!config
->save_encoder_crtcs
)
9765 config
->save_connector_encoders
=
9766 kcalloc(dev
->mode_config
.num_connector
,
9767 sizeof(struct drm_encoder
*), GFP_KERNEL
);
9768 if (!config
->save_connector_encoders
)
9771 /* Copy data. Note that driver private data is not affected.
9772 * Should anything bad happen only the expected state is
9773 * restored, not the drivers personal bookkeeping.
9776 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
9777 config
->save_encoder_crtcs
[count
++] = encoder
->crtc
;
9781 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
9782 config
->save_connector_encoders
[count
++] = connector
->encoder
;
9788 static void intel_set_config_restore_state(struct drm_device
*dev
,
9789 struct intel_set_config
*config
)
9791 struct intel_encoder
*encoder
;
9792 struct intel_connector
*connector
;
9796 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
9798 to_intel_crtc(config
->save_encoder_crtcs
[count
++]);
9802 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
9803 connector
->new_encoder
=
9804 to_intel_encoder(config
->save_connector_encoders
[count
++]);
9809 is_crtc_connector_off(struct drm_mode_set
*set
)
9813 if (set
->num_connectors
== 0)
9816 if (WARN_ON(set
->connectors
== NULL
))
9819 for (i
= 0; i
< set
->num_connectors
; i
++)
9820 if (set
->connectors
[i
]->encoder
&&
9821 set
->connectors
[i
]->encoder
->crtc
== set
->crtc
&&
9822 set
->connectors
[i
]->dpms
!= DRM_MODE_DPMS_ON
)
9829 intel_set_config_compute_mode_changes(struct drm_mode_set
*set
,
9830 struct intel_set_config
*config
)
9833 /* We should be able to check here if the fb has the same properties
9834 * and then just flip_or_move it */
9835 if (is_crtc_connector_off(set
)) {
9836 config
->mode_changed
= true;
9837 } else if (set
->crtc
->fb
!= set
->fb
) {
9838 /* If we have no fb then treat it as a full mode set */
9839 if (set
->crtc
->fb
== NULL
) {
9840 struct intel_crtc
*intel_crtc
=
9841 to_intel_crtc(set
->crtc
);
9843 if (intel_crtc
->active
&& i915_fastboot
) {
9844 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9845 config
->fb_changed
= true;
9847 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9848 config
->mode_changed
= true;
9850 } else if (set
->fb
== NULL
) {
9851 config
->mode_changed
= true;
9852 } else if (set
->fb
->pixel_format
!=
9853 set
->crtc
->fb
->pixel_format
) {
9854 config
->mode_changed
= true;
9856 config
->fb_changed
= true;
9860 if (set
->fb
&& (set
->x
!= set
->crtc
->x
|| set
->y
!= set
->crtc
->y
))
9861 config
->fb_changed
= true;
9863 if (set
->mode
&& !drm_mode_equal(set
->mode
, &set
->crtc
->mode
)) {
9864 DRM_DEBUG_KMS("modes are different, full mode set\n");
9865 drm_mode_debug_printmodeline(&set
->crtc
->mode
);
9866 drm_mode_debug_printmodeline(set
->mode
);
9867 config
->mode_changed
= true;
9870 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9871 set
->crtc
->base
.id
, config
->mode_changed
, config
->fb_changed
);
9875 intel_modeset_stage_output_state(struct drm_device
*dev
,
9876 struct drm_mode_set
*set
,
9877 struct intel_set_config
*config
)
9879 struct drm_crtc
*new_crtc
;
9880 struct intel_connector
*connector
;
9881 struct intel_encoder
*encoder
;
9884 /* The upper layers ensure that we either disable a crtc or have a list
9885 * of connectors. For paranoia, double-check this. */
9886 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
9887 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
9889 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9891 /* Otherwise traverse passed in connector list and get encoders
9893 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
9894 if (set
->connectors
[ro
] == &connector
->base
) {
9895 connector
->new_encoder
= connector
->encoder
;
9900 /* If we disable the crtc, disable all its connectors. Also, if
9901 * the connector is on the changing crtc but not on the new
9902 * connector list, disable it. */
9903 if ((!set
->fb
|| ro
== set
->num_connectors
) &&
9904 connector
->base
.encoder
&&
9905 connector
->base
.encoder
->crtc
== set
->crtc
) {
9906 connector
->new_encoder
= NULL
;
9908 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9909 connector
->base
.base
.id
,
9910 drm_get_connector_name(&connector
->base
));
9914 if (&connector
->new_encoder
->base
!= connector
->base
.encoder
) {
9915 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
9916 config
->mode_changed
= true;
9919 /* connector->new_encoder is now updated for all connectors. */
9921 /* Update crtc of enabled connectors. */
9922 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9924 if (!connector
->new_encoder
)
9927 new_crtc
= connector
->new_encoder
->base
.crtc
;
9929 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
9930 if (set
->connectors
[ro
] == &connector
->base
)
9931 new_crtc
= set
->crtc
;
9934 /* Make sure the new CRTC will work with the encoder */
9935 if (!drm_encoder_crtc_ok(&connector
->new_encoder
->base
,
9939 connector
->encoder
->new_crtc
= to_intel_crtc(new_crtc
);
9941 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9942 connector
->base
.base
.id
,
9943 drm_get_connector_name(&connector
->base
),
9947 /* Check for any encoders that needs to be disabled. */
9948 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9950 int num_connectors
= 0;
9951 list_for_each_entry(connector
,
9952 &dev
->mode_config
.connector_list
,
9954 if (connector
->new_encoder
== encoder
) {
9955 WARN_ON(!connector
->new_encoder
->new_crtc
);
9960 if (num_connectors
== 0)
9961 encoder
->new_crtc
= NULL
;
9962 else if (num_connectors
> 1)
9965 /* Only now check for crtc changes so we don't miss encoders
9966 * that will be disabled. */
9967 if (&encoder
->new_crtc
->base
!= encoder
->base
.crtc
) {
9968 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
9969 config
->mode_changed
= true;
9972 /* Now we've also updated encoder->new_crtc for all encoders. */
9977 static int intel_crtc_set_config(struct drm_mode_set
*set
)
9979 struct drm_device
*dev
;
9980 struct drm_mode_set save_set
;
9981 struct intel_set_config
*config
;
9986 BUG_ON(!set
->crtc
->helper_private
);
9988 /* Enforce sane interface api - has been abused by the fb helper. */
9989 BUG_ON(!set
->mode
&& set
->fb
);
9990 BUG_ON(set
->fb
&& set
->num_connectors
== 0);
9993 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9994 set
->crtc
->base
.id
, set
->fb
->base
.id
,
9995 (int)set
->num_connectors
, set
->x
, set
->y
);
9997 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
10000 dev
= set
->crtc
->dev
;
10003 config
= kzalloc(sizeof(*config
), GFP_KERNEL
);
10007 ret
= intel_set_config_save_state(dev
, config
);
10011 save_set
.crtc
= set
->crtc
;
10012 save_set
.mode
= &set
->crtc
->mode
;
10013 save_set
.x
= set
->crtc
->x
;
10014 save_set
.y
= set
->crtc
->y
;
10015 save_set
.fb
= set
->crtc
->fb
;
10017 /* Compute whether we need a full modeset, only an fb base update or no
10018 * change at all. In the future we might also check whether only the
10019 * mode changed, e.g. for LVDS where we only change the panel fitter in
10021 intel_set_config_compute_mode_changes(set
, config
);
10023 ret
= intel_modeset_stage_output_state(dev
, set
, config
);
10027 if (config
->mode_changed
) {
10028 ret
= intel_set_mode(set
->crtc
, set
->mode
,
10029 set
->x
, set
->y
, set
->fb
);
10030 } else if (config
->fb_changed
) {
10031 intel_crtc_wait_for_pending_flips(set
->crtc
);
10033 ret
= intel_pipe_set_base(set
->crtc
,
10034 set
->x
, set
->y
, set
->fb
);
10036 * In the fastboot case this may be our only check of the
10037 * state after boot. It would be better to only do it on
10038 * the first update, but we don't have a nice way of doing that
10039 * (and really, set_config isn't used much for high freq page
10040 * flipping, so increasing its cost here shouldn't be a big
10043 if (i915_fastboot
&& ret
== 0)
10044 intel_modeset_check_state(set
->crtc
->dev
);
10048 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
10049 set
->crtc
->base
.id
, ret
);
10051 intel_set_config_restore_state(dev
, config
);
10053 /* Try to restore the config */
10054 if (config
->mode_changed
&&
10055 intel_set_mode(save_set
.crtc
, save_set
.mode
,
10056 save_set
.x
, save_set
.y
, save_set
.fb
))
10057 DRM_ERROR("failed to restore config after modeset failure\n");
10061 intel_set_config_free(config
);
10065 static const struct drm_crtc_funcs intel_crtc_funcs
= {
10066 .cursor_set
= intel_crtc_cursor_set
,
10067 .cursor_move
= intel_crtc_cursor_move
,
10068 .gamma_set
= intel_crtc_gamma_set
,
10069 .set_config
= intel_crtc_set_config
,
10070 .destroy
= intel_crtc_destroy
,
10071 .page_flip
= intel_crtc_page_flip
,
10074 static void intel_cpu_pll_init(struct drm_device
*dev
)
10077 intel_ddi_pll_init(dev
);
10080 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private
*dev_priv
,
10081 struct intel_shared_dpll
*pll
,
10082 struct intel_dpll_hw_state
*hw_state
)
10086 val
= I915_READ(PCH_DPLL(pll
->id
));
10087 hw_state
->dpll
= val
;
10088 hw_state
->fp0
= I915_READ(PCH_FP0(pll
->id
));
10089 hw_state
->fp1
= I915_READ(PCH_FP1(pll
->id
));
10091 return val
& DPLL_VCO_ENABLE
;
10094 static void ibx_pch_dpll_mode_set(struct drm_i915_private
*dev_priv
,
10095 struct intel_shared_dpll
*pll
)
10097 I915_WRITE(PCH_FP0(pll
->id
), pll
->hw_state
.fp0
);
10098 I915_WRITE(PCH_FP1(pll
->id
), pll
->hw_state
.fp1
);
10101 static void ibx_pch_dpll_enable(struct drm_i915_private
*dev_priv
,
10102 struct intel_shared_dpll
*pll
)
10104 /* PCH refclock must be enabled first */
10105 ibx_assert_pch_refclk_enabled(dev_priv
);
10107 I915_WRITE(PCH_DPLL(pll
->id
), pll
->hw_state
.dpll
);
10109 /* Wait for the clocks to stabilize. */
10110 POSTING_READ(PCH_DPLL(pll
->id
));
10113 /* The pixel multiplier can only be updated once the
10114 * DPLL is enabled and the clocks are stable.
10116 * So write it again.
10118 I915_WRITE(PCH_DPLL(pll
->id
), pll
->hw_state
.dpll
);
10119 POSTING_READ(PCH_DPLL(pll
->id
));
10123 static void ibx_pch_dpll_disable(struct drm_i915_private
*dev_priv
,
10124 struct intel_shared_dpll
*pll
)
10126 struct drm_device
*dev
= dev_priv
->dev
;
10127 struct intel_crtc
*crtc
;
10129 /* Make sure no transcoder isn't still depending on us. */
10130 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
10131 if (intel_crtc_to_shared_dpll(crtc
) == pll
)
10132 assert_pch_transcoder_disabled(dev_priv
, crtc
->pipe
);
10135 I915_WRITE(PCH_DPLL(pll
->id
), 0);
10136 POSTING_READ(PCH_DPLL(pll
->id
));
10140 static char *ibx_pch_dpll_names
[] = {
10145 static void ibx_pch_dpll_init(struct drm_device
*dev
)
10147 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10150 dev_priv
->num_shared_dpll
= 2;
10152 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
10153 dev_priv
->shared_dplls
[i
].id
= i
;
10154 dev_priv
->shared_dplls
[i
].name
= ibx_pch_dpll_names
[i
];
10155 dev_priv
->shared_dplls
[i
].mode_set
= ibx_pch_dpll_mode_set
;
10156 dev_priv
->shared_dplls
[i
].enable
= ibx_pch_dpll_enable
;
10157 dev_priv
->shared_dplls
[i
].disable
= ibx_pch_dpll_disable
;
10158 dev_priv
->shared_dplls
[i
].get_hw_state
=
10159 ibx_pch_dpll_get_hw_state
;
10163 static void intel_shared_dpll_init(struct drm_device
*dev
)
10165 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10167 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
10168 ibx_pch_dpll_init(dev
);
10170 dev_priv
->num_shared_dpll
= 0;
10172 BUG_ON(dev_priv
->num_shared_dpll
> I915_NUM_PLLS
);
10175 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
10177 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
10178 struct intel_crtc
*intel_crtc
;
10181 intel_crtc
= kzalloc(sizeof(*intel_crtc
), GFP_KERNEL
);
10182 if (intel_crtc
== NULL
)
10185 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
10187 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
10188 for (i
= 0; i
< 256; i
++) {
10189 intel_crtc
->lut_r
[i
] = i
;
10190 intel_crtc
->lut_g
[i
] = i
;
10191 intel_crtc
->lut_b
[i
] = i
;
10195 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
10196 * is hooked to plane B. Hence we want plane A feeding pipe B.
10198 intel_crtc
->pipe
= pipe
;
10199 intel_crtc
->plane
= pipe
;
10200 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4) {
10201 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
10202 intel_crtc
->plane
= !pipe
;
10205 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
10206 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
10207 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
10208 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
10210 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
10213 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
)
10215 struct drm_encoder
*encoder
= connector
->base
.encoder
;
10217 WARN_ON(!mutex_is_locked(&connector
->base
.dev
->mode_config
.mutex
));
10220 return INVALID_PIPE
;
10222 return to_intel_crtc(encoder
->crtc
)->pipe
;
10225 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
10226 struct drm_file
*file
)
10228 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
10229 struct drm_mode_object
*drmmode_obj
;
10230 struct intel_crtc
*crtc
;
10232 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
10235 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
10236 DRM_MODE_OBJECT_CRTC
);
10238 if (!drmmode_obj
) {
10239 DRM_ERROR("no such CRTC id\n");
10243 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
10244 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
10249 static int intel_encoder_clones(struct intel_encoder
*encoder
)
10251 struct drm_device
*dev
= encoder
->base
.dev
;
10252 struct intel_encoder
*source_encoder
;
10253 int index_mask
= 0;
10256 list_for_each_entry(source_encoder
,
10257 &dev
->mode_config
.encoder_list
, base
.head
) {
10259 if (encoder
== source_encoder
)
10260 index_mask
|= (1 << entry
);
10262 /* Intel hw has only one MUX where enocoders could be cloned. */
10263 if (encoder
->cloneable
&& source_encoder
->cloneable
)
10264 index_mask
|= (1 << entry
);
10272 static bool has_edp_a(struct drm_device
*dev
)
10274 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10276 if (!IS_MOBILE(dev
))
10279 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
10282 if (IS_GEN5(dev
) &&
10283 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES
) & ILK_eDP_A_DISABLE
))
10289 const char *intel_output_name(int output
)
10291 static const char *names
[] = {
10292 [INTEL_OUTPUT_UNUSED
] = "Unused",
10293 [INTEL_OUTPUT_ANALOG
] = "Analog",
10294 [INTEL_OUTPUT_DVO
] = "DVO",
10295 [INTEL_OUTPUT_SDVO
] = "SDVO",
10296 [INTEL_OUTPUT_LVDS
] = "LVDS",
10297 [INTEL_OUTPUT_TVOUT
] = "TV",
10298 [INTEL_OUTPUT_HDMI
] = "HDMI",
10299 [INTEL_OUTPUT_DISPLAYPORT
] = "DisplayPort",
10300 [INTEL_OUTPUT_EDP
] = "eDP",
10301 [INTEL_OUTPUT_DSI
] = "DSI",
10302 [INTEL_OUTPUT_UNKNOWN
] = "Unknown",
10305 if (output
< 0 || output
>= ARRAY_SIZE(names
) || !names
[output
])
10308 return names
[output
];
10311 static void intel_setup_outputs(struct drm_device
*dev
)
10313 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10314 struct intel_encoder
*encoder
;
10315 bool dpd_is_edp
= false;
10317 intel_lvds_init(dev
);
10320 intel_crt_init(dev
);
10322 if (HAS_DDI(dev
)) {
10325 /* Haswell uses DDI functions to detect digital outputs */
10326 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
10327 /* DDI A only supports eDP */
10329 intel_ddi_init(dev
, PORT_A
);
10331 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
10333 found
= I915_READ(SFUSE_STRAP
);
10335 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
10336 intel_ddi_init(dev
, PORT_B
);
10337 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
10338 intel_ddi_init(dev
, PORT_C
);
10339 if (found
& SFUSE_STRAP_DDID_DETECTED
)
10340 intel_ddi_init(dev
, PORT_D
);
10341 } else if (HAS_PCH_SPLIT(dev
)) {
10343 dpd_is_edp
= intel_dp_is_edp(dev
, PORT_D
);
10345 if (has_edp_a(dev
))
10346 intel_dp_init(dev
, DP_A
, PORT_A
);
10348 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
10349 /* PCH SDVOB multiplex with HDMIB */
10350 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
10352 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
10353 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
10354 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
10357 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
10358 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
10360 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
10361 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
10363 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
10364 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
10366 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
10367 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
10368 } else if (IS_VALLEYVIEW(dev
)) {
10369 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIB
) & SDVO_DETECTED
) {
10370 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIB
,
10372 if (I915_READ(VLV_DISPLAY_BASE
+ DP_B
) & DP_DETECTED
)
10373 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_B
, PORT_B
);
10376 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIC
) & SDVO_DETECTED
) {
10377 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIC
,
10379 if (I915_READ(VLV_DISPLAY_BASE
+ DP_C
) & DP_DETECTED
)
10380 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_C
, PORT_C
);
10383 intel_dsi_init(dev
);
10384 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
10385 bool found
= false;
10387 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
10388 DRM_DEBUG_KMS("probing SDVOB\n");
10389 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, true);
10390 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
10391 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
10392 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
10395 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
))
10396 intel_dp_init(dev
, DP_B
, PORT_B
);
10399 /* Before G4X SDVOC doesn't have its own detect register */
10401 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
10402 DRM_DEBUG_KMS("probing SDVOC\n");
10403 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, false);
10406 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
10408 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
10409 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
10410 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
10412 if (SUPPORTS_INTEGRATED_DP(dev
))
10413 intel_dp_init(dev
, DP_C
, PORT_C
);
10416 if (SUPPORTS_INTEGRATED_DP(dev
) &&
10417 (I915_READ(DP_D
) & DP_DETECTED
))
10418 intel_dp_init(dev
, DP_D
, PORT_D
);
10419 } else if (IS_GEN2(dev
))
10420 intel_dvo_init(dev
);
10422 if (SUPPORTS_TV(dev
))
10423 intel_tv_init(dev
);
10425 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
10426 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
10427 encoder
->base
.possible_clones
=
10428 intel_encoder_clones(encoder
);
10431 intel_init_pch_refclk(dev
);
10433 drm_helper_move_panel_connectors_to_head(dev
);
10436 void intel_framebuffer_fini(struct intel_framebuffer
*fb
)
10438 drm_framebuffer_cleanup(&fb
->base
);
10439 WARN_ON(!fb
->obj
->framebuffer_references
--);
10440 drm_gem_object_unreference_unlocked(&fb
->obj
->base
);
10443 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
10445 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
10447 intel_framebuffer_fini(intel_fb
);
10451 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
10452 struct drm_file
*file
,
10453 unsigned int *handle
)
10455 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
10456 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
10458 return drm_gem_handle_create(file
, &obj
->base
, handle
);
10461 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
10462 .destroy
= intel_user_framebuffer_destroy
,
10463 .create_handle
= intel_user_framebuffer_create_handle
,
10466 int intel_framebuffer_init(struct drm_device
*dev
,
10467 struct intel_framebuffer
*intel_fb
,
10468 struct drm_mode_fb_cmd2
*mode_cmd
,
10469 struct drm_i915_gem_object
*obj
)
10471 int aligned_height
, tile_height
;
10475 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
10477 if (obj
->tiling_mode
== I915_TILING_Y
) {
10478 DRM_DEBUG("hardware does not support tiling Y\n");
10482 if (mode_cmd
->pitches
[0] & 63) {
10483 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
10484 mode_cmd
->pitches
[0]);
10488 if (INTEL_INFO(dev
)->gen
>= 5 && !IS_VALLEYVIEW(dev
)) {
10489 pitch_limit
= 32*1024;
10490 } else if (INTEL_INFO(dev
)->gen
>= 4) {
10491 if (obj
->tiling_mode
)
10492 pitch_limit
= 16*1024;
10494 pitch_limit
= 32*1024;
10495 } else if (INTEL_INFO(dev
)->gen
>= 3) {
10496 if (obj
->tiling_mode
)
10497 pitch_limit
= 8*1024;
10499 pitch_limit
= 16*1024;
10501 /* XXX DSPC is limited to 4k tiled */
10502 pitch_limit
= 8*1024;
10504 if (mode_cmd
->pitches
[0] > pitch_limit
) {
10505 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10506 obj
->tiling_mode
? "tiled" : "linear",
10507 mode_cmd
->pitches
[0], pitch_limit
);
10511 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
10512 mode_cmd
->pitches
[0] != obj
->stride
) {
10513 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10514 mode_cmd
->pitches
[0], obj
->stride
);
10518 /* Reject formats not supported by any plane early. */
10519 switch (mode_cmd
->pixel_format
) {
10520 case DRM_FORMAT_C8
:
10521 case DRM_FORMAT_RGB565
:
10522 case DRM_FORMAT_XRGB8888
:
10523 case DRM_FORMAT_ARGB8888
:
10525 case DRM_FORMAT_XRGB1555
:
10526 case DRM_FORMAT_ARGB1555
:
10527 if (INTEL_INFO(dev
)->gen
> 3) {
10528 DRM_DEBUG("unsupported pixel format: %s\n",
10529 drm_get_format_name(mode_cmd
->pixel_format
));
10533 case DRM_FORMAT_XBGR8888
:
10534 case DRM_FORMAT_ABGR8888
:
10535 case DRM_FORMAT_XRGB2101010
:
10536 case DRM_FORMAT_ARGB2101010
:
10537 case DRM_FORMAT_XBGR2101010
:
10538 case DRM_FORMAT_ABGR2101010
:
10539 if (INTEL_INFO(dev
)->gen
< 4) {
10540 DRM_DEBUG("unsupported pixel format: %s\n",
10541 drm_get_format_name(mode_cmd
->pixel_format
));
10545 case DRM_FORMAT_YUYV
:
10546 case DRM_FORMAT_UYVY
:
10547 case DRM_FORMAT_YVYU
:
10548 case DRM_FORMAT_VYUY
:
10549 if (INTEL_INFO(dev
)->gen
< 5) {
10550 DRM_DEBUG("unsupported pixel format: %s\n",
10551 drm_get_format_name(mode_cmd
->pixel_format
));
10556 DRM_DEBUG("unsupported pixel format: %s\n",
10557 drm_get_format_name(mode_cmd
->pixel_format
));
10561 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10562 if (mode_cmd
->offsets
[0] != 0)
10565 tile_height
= IS_GEN2(dev
) ? 16 : 8;
10566 aligned_height
= ALIGN(mode_cmd
->height
,
10567 obj
->tiling_mode
? tile_height
: 1);
10568 /* FIXME drm helper for size checks (especially planar formats)? */
10569 if (obj
->base
.size
< aligned_height
* mode_cmd
->pitches
[0])
10572 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
10573 intel_fb
->obj
= obj
;
10574 intel_fb
->obj
->framebuffer_references
++;
10576 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
10578 DRM_ERROR("framebuffer init failed %d\n", ret
);
10585 static struct drm_framebuffer
*
10586 intel_user_framebuffer_create(struct drm_device
*dev
,
10587 struct drm_file
*filp
,
10588 struct drm_mode_fb_cmd2
*mode_cmd
)
10590 struct drm_i915_gem_object
*obj
;
10592 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
10593 mode_cmd
->handles
[0]));
10594 if (&obj
->base
== NULL
)
10595 return ERR_PTR(-ENOENT
);
10597 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
10600 #ifndef CONFIG_DRM_I915_FBDEV
10601 static inline void intel_fbdev_output_poll_changed(struct drm_device
*dev
)
10606 static const struct drm_mode_config_funcs intel_mode_funcs
= {
10607 .fb_create
= intel_user_framebuffer_create
,
10608 .output_poll_changed
= intel_fbdev_output_poll_changed
,
10611 /* Set up chip specific display functions */
10612 static void intel_init_display(struct drm_device
*dev
)
10614 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10616 if (HAS_PCH_SPLIT(dev
) || IS_G4X(dev
))
10617 dev_priv
->display
.find_dpll
= g4x_find_best_dpll
;
10618 else if (IS_VALLEYVIEW(dev
))
10619 dev_priv
->display
.find_dpll
= vlv_find_best_dpll
;
10620 else if (IS_PINEVIEW(dev
))
10621 dev_priv
->display
.find_dpll
= pnv_find_best_dpll
;
10623 dev_priv
->display
.find_dpll
= i9xx_find_best_dpll
;
10625 if (HAS_DDI(dev
)) {
10626 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
10627 dev_priv
->display
.crtc_mode_set
= haswell_crtc_mode_set
;
10628 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
10629 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
10630 dev_priv
->display
.off
= haswell_crtc_off
;
10631 dev_priv
->display
.update_plane
= ironlake_update_plane
;
10632 } else if (HAS_PCH_SPLIT(dev
)) {
10633 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
10634 dev_priv
->display
.crtc_mode_set
= ironlake_crtc_mode_set
;
10635 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
10636 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
10637 dev_priv
->display
.off
= ironlake_crtc_off
;
10638 dev_priv
->display
.update_plane
= ironlake_update_plane
;
10639 } else if (IS_VALLEYVIEW(dev
)) {
10640 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
10641 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
10642 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
10643 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
10644 dev_priv
->display
.off
= i9xx_crtc_off
;
10645 dev_priv
->display
.update_plane
= i9xx_update_plane
;
10647 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
10648 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
10649 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
10650 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
10651 dev_priv
->display
.off
= i9xx_crtc_off
;
10652 dev_priv
->display
.update_plane
= i9xx_update_plane
;
10655 /* Returns the core display clock speed */
10656 if (IS_VALLEYVIEW(dev
))
10657 dev_priv
->display
.get_display_clock_speed
=
10658 valleyview_get_display_clock_speed
;
10659 else if (IS_I945G(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
10660 dev_priv
->display
.get_display_clock_speed
=
10661 i945_get_display_clock_speed
;
10662 else if (IS_I915G(dev
))
10663 dev_priv
->display
.get_display_clock_speed
=
10664 i915_get_display_clock_speed
;
10665 else if (IS_I945GM(dev
) || IS_845G(dev
))
10666 dev_priv
->display
.get_display_clock_speed
=
10667 i9xx_misc_get_display_clock_speed
;
10668 else if (IS_PINEVIEW(dev
))
10669 dev_priv
->display
.get_display_clock_speed
=
10670 pnv_get_display_clock_speed
;
10671 else if (IS_I915GM(dev
))
10672 dev_priv
->display
.get_display_clock_speed
=
10673 i915gm_get_display_clock_speed
;
10674 else if (IS_I865G(dev
))
10675 dev_priv
->display
.get_display_clock_speed
=
10676 i865_get_display_clock_speed
;
10677 else if (IS_I85X(dev
))
10678 dev_priv
->display
.get_display_clock_speed
=
10679 i855_get_display_clock_speed
;
10680 else /* 852, 830 */
10681 dev_priv
->display
.get_display_clock_speed
=
10682 i830_get_display_clock_speed
;
10684 if (HAS_PCH_SPLIT(dev
)) {
10685 if (IS_GEN5(dev
)) {
10686 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
10687 dev_priv
->display
.write_eld
= ironlake_write_eld
;
10688 } else if (IS_GEN6(dev
)) {
10689 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
10690 dev_priv
->display
.write_eld
= ironlake_write_eld
;
10691 } else if (IS_IVYBRIDGE(dev
)) {
10692 /* FIXME: detect B0+ stepping and use auto training */
10693 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
10694 dev_priv
->display
.write_eld
= ironlake_write_eld
;
10695 dev_priv
->display
.modeset_global_resources
=
10696 ivb_modeset_global_resources
;
10697 } else if (IS_HASWELL(dev
) || IS_GEN8(dev
)) {
10698 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
10699 dev_priv
->display
.write_eld
= haswell_write_eld
;
10700 dev_priv
->display
.modeset_global_resources
=
10701 haswell_modeset_global_resources
;
10703 } else if (IS_G4X(dev
)) {
10704 dev_priv
->display
.write_eld
= g4x_write_eld
;
10705 } else if (IS_VALLEYVIEW(dev
)) {
10706 dev_priv
->display
.modeset_global_resources
=
10707 valleyview_modeset_global_resources
;
10708 dev_priv
->display
.write_eld
= ironlake_write_eld
;
10711 /* Default just returns -ENODEV to indicate unsupported */
10712 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
10714 switch (INTEL_INFO(dev
)->gen
) {
10716 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
10720 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
10725 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
10729 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
10732 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
10733 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
10737 intel_panel_init_backlight_funcs(dev
);
10741 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10742 * resume, or other times. This quirk makes sure that's the case for
10743 * affected systems.
10745 static void quirk_pipea_force(struct drm_device
*dev
)
10747 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10749 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
10750 DRM_INFO("applying pipe a force quirk\n");
10754 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10756 static void quirk_ssc_force_disable(struct drm_device
*dev
)
10758 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10759 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
10760 DRM_INFO("applying lvds SSC disable quirk\n");
10764 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10767 static void quirk_invert_brightness(struct drm_device
*dev
)
10769 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10770 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
10771 DRM_INFO("applying inverted panel brightness quirk\n");
10774 struct intel_quirk
{
10776 int subsystem_vendor
;
10777 int subsystem_device
;
10778 void (*hook
)(struct drm_device
*dev
);
10781 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10782 struct intel_dmi_quirk
{
10783 void (*hook
)(struct drm_device
*dev
);
10784 const struct dmi_system_id (*dmi_id_list
)[];
10787 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
10789 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
10793 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
10795 .dmi_id_list
= &(const struct dmi_system_id
[]) {
10797 .callback
= intel_dmi_reverse_brightness
,
10798 .ident
= "NCR Corporation",
10799 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
10800 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
10803 { } /* terminating entry */
10805 .hook
= quirk_invert_brightness
,
10809 static struct intel_quirk intel_quirks
[] = {
10810 /* HP Mini needs pipe A force quirk (LP: #322104) */
10811 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
10813 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10814 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
10816 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10817 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
10819 /* 830 needs to leave pipe A & dpll A up */
10820 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
10822 /* Lenovo U160 cannot use SSC on LVDS */
10823 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
10825 /* Sony Vaio Y cannot use SSC on LVDS */
10826 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
10828 /* Acer Aspire 5734Z must invert backlight brightness */
10829 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
10831 /* Acer/eMachines G725 */
10832 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
10834 /* Acer/eMachines e725 */
10835 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
10837 /* Acer/Packard Bell NCL20 */
10838 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
10840 /* Acer Aspire 4736Z */
10841 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
10844 static void intel_init_quirks(struct drm_device
*dev
)
10846 struct pci_dev
*d
= dev
->pdev
;
10849 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
10850 struct intel_quirk
*q
= &intel_quirks
[i
];
10852 if (d
->device
== q
->device
&&
10853 (d
->subsystem_vendor
== q
->subsystem_vendor
||
10854 q
->subsystem_vendor
== PCI_ANY_ID
) &&
10855 (d
->subsystem_device
== q
->subsystem_device
||
10856 q
->subsystem_device
== PCI_ANY_ID
))
10859 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
10860 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
10861 intel_dmi_quirks
[i
].hook(dev
);
10865 /* Disable the VGA plane that we never use */
10866 static void i915_disable_vga(struct drm_device
*dev
)
10868 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10870 u32 vga_reg
= i915_vgacntrl_reg(dev
);
10872 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
10873 outb(SR01
, VGA_SR_INDEX
);
10874 sr1
= inb(VGA_SR_DATA
);
10875 outb(sr1
| 1<<5, VGA_SR_DATA
);
10876 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
10879 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
10880 POSTING_READ(vga_reg
);
10883 void intel_modeset_init_hw(struct drm_device
*dev
)
10885 intel_prepare_ddi(dev
);
10887 intel_init_clock_gating(dev
);
10889 intel_reset_dpio(dev
);
10891 mutex_lock(&dev
->struct_mutex
);
10892 intel_enable_gt_powersave(dev
);
10893 mutex_unlock(&dev
->struct_mutex
);
10896 void intel_modeset_suspend_hw(struct drm_device
*dev
)
10898 intel_suspend_hw(dev
);
10901 void intel_modeset_init(struct drm_device
*dev
)
10903 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10906 drm_mode_config_init(dev
);
10908 dev
->mode_config
.min_width
= 0;
10909 dev
->mode_config
.min_height
= 0;
10911 dev
->mode_config
.preferred_depth
= 24;
10912 dev
->mode_config
.prefer_shadow
= 1;
10914 dev
->mode_config
.funcs
= &intel_mode_funcs
;
10916 intel_init_quirks(dev
);
10918 intel_init_pm(dev
);
10920 if (INTEL_INFO(dev
)->num_pipes
== 0)
10923 intel_init_display(dev
);
10925 if (IS_GEN2(dev
)) {
10926 dev
->mode_config
.max_width
= 2048;
10927 dev
->mode_config
.max_height
= 2048;
10928 } else if (IS_GEN3(dev
)) {
10929 dev
->mode_config
.max_width
= 4096;
10930 dev
->mode_config
.max_height
= 4096;
10932 dev
->mode_config
.max_width
= 8192;
10933 dev
->mode_config
.max_height
= 8192;
10935 dev
->mode_config
.fb_base
= dev_priv
->gtt
.mappable_base
;
10937 DRM_DEBUG_KMS("%d display pipe%s available.\n",
10938 INTEL_INFO(dev
)->num_pipes
,
10939 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
10942 intel_crtc_init(dev
, i
);
10943 for (j
= 0; j
< dev_priv
->num_plane
; j
++) {
10944 ret
= intel_plane_init(dev
, i
, j
);
10946 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10947 pipe_name(i
), sprite_name(i
, j
), ret
);
10951 intel_init_dpio(dev
);
10952 intel_reset_dpio(dev
);
10954 intel_cpu_pll_init(dev
);
10955 intel_shared_dpll_init(dev
);
10957 /* Just disable it once at startup */
10958 i915_disable_vga(dev
);
10959 intel_setup_outputs(dev
);
10961 /* Just in case the BIOS is doing something questionable. */
10962 intel_disable_fbc(dev
);
10966 intel_connector_break_all_links(struct intel_connector
*connector
)
10968 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
10969 connector
->base
.encoder
= NULL
;
10970 connector
->encoder
->connectors_active
= false;
10971 connector
->encoder
->base
.crtc
= NULL
;
10974 static void intel_enable_pipe_a(struct drm_device
*dev
)
10976 struct intel_connector
*connector
;
10977 struct drm_connector
*crt
= NULL
;
10978 struct intel_load_detect_pipe load_detect_temp
;
10980 /* We can't just switch on the pipe A, we need to set things up with a
10981 * proper mode and output configuration. As a gross hack, enable pipe A
10982 * by enabling the load detect pipe once. */
10983 list_for_each_entry(connector
,
10984 &dev
->mode_config
.connector_list
,
10986 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
10987 crt
= &connector
->base
;
10995 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
))
10996 intel_release_load_detect_pipe(crt
, &load_detect_temp
);
11002 intel_check_plane_mapping(struct intel_crtc
*crtc
)
11004 struct drm_device
*dev
= crtc
->base
.dev
;
11005 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11008 if (INTEL_INFO(dev
)->num_pipes
== 1)
11011 reg
= DSPCNTR(!crtc
->plane
);
11012 val
= I915_READ(reg
);
11014 if ((val
& DISPLAY_PLANE_ENABLE
) &&
11015 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
11021 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
11023 struct drm_device
*dev
= crtc
->base
.dev
;
11024 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11027 /* Clear any frame start delays used for debugging left by the BIOS */
11028 reg
= PIPECONF(crtc
->config
.cpu_transcoder
);
11029 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
11031 /* We need to sanitize the plane -> pipe mapping first because this will
11032 * disable the crtc (and hence change the state) if it is wrong. Note
11033 * that gen4+ has a fixed plane -> pipe mapping. */
11034 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
11035 struct intel_connector
*connector
;
11038 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
11039 crtc
->base
.base
.id
);
11041 /* Pipe has the wrong plane attached and the plane is active.
11042 * Temporarily change the plane mapping and disable everything
11044 plane
= crtc
->plane
;
11045 crtc
->plane
= !plane
;
11046 dev_priv
->display
.crtc_disable(&crtc
->base
);
11047 crtc
->plane
= plane
;
11049 /* ... and break all links. */
11050 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11052 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
11055 intel_connector_break_all_links(connector
);
11058 WARN_ON(crtc
->active
);
11059 crtc
->base
.enabled
= false;
11062 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
11063 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
11064 /* BIOS forgot to enable pipe A, this mostly happens after
11065 * resume. Force-enable the pipe to fix this, the update_dpms
11066 * call below we restore the pipe to the right state, but leave
11067 * the required bits on. */
11068 intel_enable_pipe_a(dev
);
11071 /* Adjust the state of the output pipe according to whether we
11072 * have active connectors/encoders. */
11073 intel_crtc_update_dpms(&crtc
->base
);
11075 if (crtc
->active
!= crtc
->base
.enabled
) {
11076 struct intel_encoder
*encoder
;
11078 /* This can happen either due to bugs in the get_hw_state
11079 * functions or because the pipe is force-enabled due to the
11081 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
11082 crtc
->base
.base
.id
,
11083 crtc
->base
.enabled
? "enabled" : "disabled",
11084 crtc
->active
? "enabled" : "disabled");
11086 crtc
->base
.enabled
= crtc
->active
;
11088 /* Because we only establish the connector -> encoder ->
11089 * crtc links if something is active, this means the
11090 * crtc is now deactivated. Break the links. connector
11091 * -> encoder links are only establish when things are
11092 * actually up, hence no need to break them. */
11093 WARN_ON(crtc
->active
);
11095 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
11096 WARN_ON(encoder
->connectors_active
);
11097 encoder
->base
.crtc
= NULL
;
11102 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
11104 struct intel_connector
*connector
;
11105 struct drm_device
*dev
= encoder
->base
.dev
;
11107 /* We need to check both for a crtc link (meaning that the
11108 * encoder is active and trying to read from a pipe) and the
11109 * pipe itself being active. */
11110 bool has_active_crtc
= encoder
->base
.crtc
&&
11111 to_intel_crtc(encoder
->base
.crtc
)->active
;
11113 if (encoder
->connectors_active
&& !has_active_crtc
) {
11114 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
11115 encoder
->base
.base
.id
,
11116 drm_get_encoder_name(&encoder
->base
));
11118 /* Connector is active, but has no active pipe. This is
11119 * fallout from our resume register restoring. Disable
11120 * the encoder manually again. */
11121 if (encoder
->base
.crtc
) {
11122 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
11123 encoder
->base
.base
.id
,
11124 drm_get_encoder_name(&encoder
->base
));
11125 encoder
->disable(encoder
);
11128 /* Inconsistent output/port/pipe state happens presumably due to
11129 * a bug in one of the get_hw_state functions. Or someplace else
11130 * in our code, like the register restore mess on resume. Clamp
11131 * things to off as a safer default. */
11132 list_for_each_entry(connector
,
11133 &dev
->mode_config
.connector_list
,
11135 if (connector
->encoder
!= encoder
)
11138 intel_connector_break_all_links(connector
);
11141 /* Enabled encoders without active connectors will be fixed in
11142 * the crtc fixup. */
11145 void i915_redisable_vga(struct drm_device
*dev
)
11147 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11148 u32 vga_reg
= i915_vgacntrl_reg(dev
);
11150 /* This function can be called both from intel_modeset_setup_hw_state or
11151 * at a very early point in our resume sequence, where the power well
11152 * structures are not yet restored. Since this function is at a very
11153 * paranoid "someone might have enabled VGA while we were not looking"
11154 * level, just check if the power well is enabled instead of trying to
11155 * follow the "don't touch the power well if we don't need it" policy
11156 * the rest of the driver uses. */
11157 if ((IS_HASWELL(dev
) || IS_BROADWELL(dev
)) &&
11158 (I915_READ(HSW_PWR_WELL_DRIVER
) & HSW_PWR_WELL_STATE_ENABLED
) == 0)
11161 if (!(I915_READ(vga_reg
) & VGA_DISP_DISABLE
)) {
11162 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
11163 i915_disable_vga(dev
);
11167 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
11169 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11171 struct intel_crtc
*crtc
;
11172 struct intel_encoder
*encoder
;
11173 struct intel_connector
*connector
;
11176 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
11178 memset(&crtc
->config
, 0, sizeof(crtc
->config
));
11180 crtc
->active
= dev_priv
->display
.get_pipe_config(crtc
,
11183 crtc
->base
.enabled
= crtc
->active
;
11184 crtc
->primary_enabled
= crtc
->active
;
11186 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
11187 crtc
->base
.base
.id
,
11188 crtc
->active
? "enabled" : "disabled");
11191 /* FIXME: Smash this into the new shared dpll infrastructure. */
11193 intel_ddi_setup_hw_pll_state(dev
);
11195 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
11196 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
11198 pll
->on
= pll
->get_hw_state(dev_priv
, pll
, &pll
->hw_state
);
11200 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
11202 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
11205 pll
->refcount
= pll
->active
;
11207 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
11208 pll
->name
, pll
->refcount
, pll
->on
);
11211 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
11215 if (encoder
->get_hw_state(encoder
, &pipe
)) {
11216 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
11217 encoder
->base
.crtc
= &crtc
->base
;
11218 encoder
->get_config(encoder
, &crtc
->config
);
11220 encoder
->base
.crtc
= NULL
;
11223 encoder
->connectors_active
= false;
11224 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
11225 encoder
->base
.base
.id
,
11226 drm_get_encoder_name(&encoder
->base
),
11227 encoder
->base
.crtc
? "enabled" : "disabled",
11231 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11233 if (connector
->get_hw_state(connector
)) {
11234 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
11235 connector
->encoder
->connectors_active
= true;
11236 connector
->base
.encoder
= &connector
->encoder
->base
;
11238 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
11239 connector
->base
.encoder
= NULL
;
11241 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
11242 connector
->base
.base
.id
,
11243 drm_get_connector_name(&connector
->base
),
11244 connector
->base
.encoder
? "enabled" : "disabled");
11248 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
11249 * and i915 state tracking structures. */
11250 void intel_modeset_setup_hw_state(struct drm_device
*dev
,
11251 bool force_restore
)
11253 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11255 struct intel_crtc
*crtc
;
11256 struct intel_encoder
*encoder
;
11259 intel_modeset_readout_hw_state(dev
);
11262 * Now that we have the config, copy it to each CRTC struct
11263 * Note that this could go away if we move to using crtc_config
11264 * checking everywhere.
11266 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
11268 if (crtc
->active
&& i915_fastboot
) {
11269 intel_crtc_mode_from_pipe_config(crtc
, &crtc
->config
);
11271 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
11272 crtc
->base
.base
.id
);
11273 drm_mode_debug_printmodeline(&crtc
->base
.mode
);
11277 /* HW state is read out, now we need to sanitize this mess. */
11278 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
11280 intel_sanitize_encoder(encoder
);
11283 for_each_pipe(pipe
) {
11284 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
11285 intel_sanitize_crtc(crtc
);
11286 intel_dump_pipe_config(crtc
, &crtc
->config
, "[setup_hw_state]");
11289 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
11290 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
11292 if (!pll
->on
|| pll
->active
)
11295 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll
->name
);
11297 pll
->disable(dev_priv
, pll
);
11301 if (HAS_PCH_SPLIT(dev
))
11302 ilk_wm_get_hw_state(dev
);
11304 if (force_restore
) {
11305 i915_redisable_vga(dev
);
11308 * We need to use raw interfaces for restoring state to avoid
11309 * checking (bogus) intermediate states.
11311 for_each_pipe(pipe
) {
11312 struct drm_crtc
*crtc
=
11313 dev_priv
->pipe_to_crtc_mapping
[pipe
];
11315 __intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
,
11319 intel_modeset_update_staged_output_state(dev
);
11322 intel_modeset_check_state(dev
);
11325 void intel_modeset_gem_init(struct drm_device
*dev
)
11327 intel_modeset_init_hw(dev
);
11329 intel_setup_overlay(dev
);
11331 mutex_lock(&dev
->mode_config
.mutex
);
11332 drm_mode_config_reset(dev
);
11333 intel_modeset_setup_hw_state(dev
, false);
11334 mutex_unlock(&dev
->mode_config
.mutex
);
11337 void intel_modeset_cleanup(struct drm_device
*dev
)
11339 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11340 struct drm_crtc
*crtc
;
11341 struct drm_connector
*connector
;
11344 * Interrupts and polling as the first thing to avoid creating havoc.
11345 * Too much stuff here (turning of rps, connectors, ...) would
11346 * experience fancy races otherwise.
11348 drm_irq_uninstall(dev
);
11349 cancel_work_sync(&dev_priv
->hotplug_work
);
11351 * Due to the hpd irq storm handling the hotplug work can re-arm the
11352 * poll handlers. Hence disable polling after hpd handling is shut down.
11354 drm_kms_helper_poll_fini(dev
);
11356 mutex_lock(&dev
->struct_mutex
);
11358 intel_unregister_dsm_handler();
11360 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
11361 /* Skip inactive CRTCs */
11365 intel_increase_pllclock(crtc
);
11368 intel_disable_fbc(dev
);
11370 intel_disable_gt_powersave(dev
);
11372 ironlake_teardown_rc6(dev
);
11374 mutex_unlock(&dev
->struct_mutex
);
11376 /* flush any delayed tasks or pending work */
11377 flush_scheduled_work();
11379 /* destroy the backlight and sysfs files before encoders/connectors */
11380 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
11381 intel_panel_destroy_backlight(connector
);
11382 drm_sysfs_connector_remove(connector
);
11385 drm_mode_config_cleanup(dev
);
11387 intel_cleanup_overlay(dev
);
11391 * Return which encoder is currently attached for connector.
11393 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
11395 return &intel_attached_encoder(connector
)->base
;
11398 void intel_connector_attach_encoder(struct intel_connector
*connector
,
11399 struct intel_encoder
*encoder
)
11401 connector
->encoder
= encoder
;
11402 drm_mode_connector_attach_encoder(&connector
->base
,
11407 * set vga decode state - true == enable VGA decode
11409 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
11411 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11412 unsigned reg
= INTEL_INFO(dev
)->gen
>= 6 ? SNB_GMCH_CTRL
: INTEL_GMCH_CTRL
;
11415 pci_read_config_word(dev_priv
->bridge_dev
, reg
, &gmch_ctrl
);
11417 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
11419 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
11420 pci_write_config_word(dev_priv
->bridge_dev
, reg
, gmch_ctrl
);
11424 struct intel_display_error_state
{
11426 u32 power_well_driver
;
11428 int num_transcoders
;
11430 struct intel_cursor_error_state
{
11435 } cursor
[I915_MAX_PIPES
];
11437 struct intel_pipe_error_state
{
11438 bool power_domain_on
;
11440 } pipe
[I915_MAX_PIPES
];
11442 struct intel_plane_error_state
{
11450 } plane
[I915_MAX_PIPES
];
11452 struct intel_transcoder_error_state
{
11453 bool power_domain_on
;
11454 enum transcoder cpu_transcoder
;
11467 struct intel_display_error_state
*
11468 intel_display_capture_error_state(struct drm_device
*dev
)
11470 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
11471 struct intel_display_error_state
*error
;
11472 int transcoders
[] = {
11480 if (INTEL_INFO(dev
)->num_pipes
== 0)
11483 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
11487 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
11488 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_DRIVER
);
11491 error
->pipe
[i
].power_domain_on
=
11492 intel_display_power_enabled_sw(dev
, POWER_DOMAIN_PIPE(i
));
11493 if (!error
->pipe
[i
].power_domain_on
)
11496 if (INTEL_INFO(dev
)->gen
<= 6 || IS_VALLEYVIEW(dev
)) {
11497 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
11498 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
11499 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
11501 error
->cursor
[i
].control
= I915_READ(CURCNTR_IVB(i
));
11502 error
->cursor
[i
].position
= I915_READ(CURPOS_IVB(i
));
11503 error
->cursor
[i
].base
= I915_READ(CURBASE_IVB(i
));
11506 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
11507 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
11508 if (INTEL_INFO(dev
)->gen
<= 3) {
11509 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
11510 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
11512 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
11513 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
11514 if (INTEL_INFO(dev
)->gen
>= 4) {
11515 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
11516 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
11519 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
11522 error
->num_transcoders
= INTEL_INFO(dev
)->num_pipes
;
11523 if (HAS_DDI(dev_priv
->dev
))
11524 error
->num_transcoders
++; /* Account for eDP. */
11526 for (i
= 0; i
< error
->num_transcoders
; i
++) {
11527 enum transcoder cpu_transcoder
= transcoders
[i
];
11529 error
->transcoder
[i
].power_domain_on
=
11530 intel_display_power_enabled_sw(dev
,
11531 POWER_DOMAIN_TRANSCODER(cpu_transcoder
));
11532 if (!error
->transcoder
[i
].power_domain_on
)
11535 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
11537 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
11538 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
11539 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
11540 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
11541 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
11542 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
11543 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
11549 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
11552 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
11553 struct drm_device
*dev
,
11554 struct intel_display_error_state
*error
)
11561 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
11562 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
11563 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
11564 error
->power_well_driver
);
11566 err_printf(m
, "Pipe [%d]:\n", i
);
11567 err_printf(m
, " Power: %s\n",
11568 error
->pipe
[i
].power_domain_on
? "on" : "off");
11569 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
11571 err_printf(m
, "Plane [%d]:\n", i
);
11572 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
11573 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
11574 if (INTEL_INFO(dev
)->gen
<= 3) {
11575 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
11576 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
11578 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
11579 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
11580 if (INTEL_INFO(dev
)->gen
>= 4) {
11581 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
11582 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
11585 err_printf(m
, "Cursor [%d]:\n", i
);
11586 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
11587 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
11588 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
11591 for (i
= 0; i
< error
->num_transcoders
; i
++) {
11592 err_printf(m
, "CPU transcoder: %c\n",
11593 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
11594 err_printf(m
, " Power: %s\n",
11595 error
->transcoder
[i
].power_domain_on
? "on" : "off");
11596 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
11597 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
11598 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
11599 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
11600 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
11601 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
11602 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);