2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 static void intel_increase_pllclock(struct drm_crtc
*crtc
);
45 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
47 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
48 struct intel_crtc_config
*pipe_config
);
49 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
50 struct intel_crtc_config
*pipe_config
);
52 static int intel_set_mode(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
53 int x
, int y
, struct drm_framebuffer
*old_fb
);
65 typedef struct intel_limit intel_limit_t
;
67 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
72 intel_pch_rawclk(struct drm_device
*dev
)
74 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
76 WARN_ON(!HAS_PCH_SPLIT(dev
));
78 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
81 static inline u32
/* units of 100MHz */
82 intel_fdi_link_freq(struct drm_device
*dev
)
85 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
86 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
91 static const intel_limit_t intel_limits_i8xx_dac
= {
92 .dot
= { .min
= 25000, .max
= 350000 },
93 .vco
= { .min
= 930000, .max
= 1400000 },
94 .n
= { .min
= 3, .max
= 16 },
95 .m
= { .min
= 96, .max
= 140 },
96 .m1
= { .min
= 18, .max
= 26 },
97 .m2
= { .min
= 6, .max
= 16 },
98 .p
= { .min
= 4, .max
= 128 },
99 .p1
= { .min
= 2, .max
= 33 },
100 .p2
= { .dot_limit
= 165000,
101 .p2_slow
= 4, .p2_fast
= 2 },
104 static const intel_limit_t intel_limits_i8xx_dvo
= {
105 .dot
= { .min
= 25000, .max
= 350000 },
106 .vco
= { .min
= 930000, .max
= 1400000 },
107 .n
= { .min
= 3, .max
= 16 },
108 .m
= { .min
= 96, .max
= 140 },
109 .m1
= { .min
= 18, .max
= 26 },
110 .m2
= { .min
= 6, .max
= 16 },
111 .p
= { .min
= 4, .max
= 128 },
112 .p1
= { .min
= 2, .max
= 33 },
113 .p2
= { .dot_limit
= 165000,
114 .p2_slow
= 4, .p2_fast
= 4 },
117 static const intel_limit_t intel_limits_i8xx_lvds
= {
118 .dot
= { .min
= 25000, .max
= 350000 },
119 .vco
= { .min
= 930000, .max
= 1400000 },
120 .n
= { .min
= 3, .max
= 16 },
121 .m
= { .min
= 96, .max
= 140 },
122 .m1
= { .min
= 18, .max
= 26 },
123 .m2
= { .min
= 6, .max
= 16 },
124 .p
= { .min
= 4, .max
= 128 },
125 .p1
= { .min
= 1, .max
= 6 },
126 .p2
= { .dot_limit
= 165000,
127 .p2_slow
= 14, .p2_fast
= 7 },
130 static const intel_limit_t intel_limits_i9xx_sdvo
= {
131 .dot
= { .min
= 20000, .max
= 400000 },
132 .vco
= { .min
= 1400000, .max
= 2800000 },
133 .n
= { .min
= 1, .max
= 6 },
134 .m
= { .min
= 70, .max
= 120 },
135 .m1
= { .min
= 8, .max
= 18 },
136 .m2
= { .min
= 3, .max
= 7 },
137 .p
= { .min
= 5, .max
= 80 },
138 .p1
= { .min
= 1, .max
= 8 },
139 .p2
= { .dot_limit
= 200000,
140 .p2_slow
= 10, .p2_fast
= 5 },
143 static const intel_limit_t intel_limits_i9xx_lvds
= {
144 .dot
= { .min
= 20000, .max
= 400000 },
145 .vco
= { .min
= 1400000, .max
= 2800000 },
146 .n
= { .min
= 1, .max
= 6 },
147 .m
= { .min
= 70, .max
= 120 },
148 .m1
= { .min
= 8, .max
= 18 },
149 .m2
= { .min
= 3, .max
= 7 },
150 .p
= { .min
= 7, .max
= 98 },
151 .p1
= { .min
= 1, .max
= 8 },
152 .p2
= { .dot_limit
= 112000,
153 .p2_slow
= 14, .p2_fast
= 7 },
157 static const intel_limit_t intel_limits_g4x_sdvo
= {
158 .dot
= { .min
= 25000, .max
= 270000 },
159 .vco
= { .min
= 1750000, .max
= 3500000},
160 .n
= { .min
= 1, .max
= 4 },
161 .m
= { .min
= 104, .max
= 138 },
162 .m1
= { .min
= 17, .max
= 23 },
163 .m2
= { .min
= 5, .max
= 11 },
164 .p
= { .min
= 10, .max
= 30 },
165 .p1
= { .min
= 1, .max
= 3},
166 .p2
= { .dot_limit
= 270000,
172 static const intel_limit_t intel_limits_g4x_hdmi
= {
173 .dot
= { .min
= 22000, .max
= 400000 },
174 .vco
= { .min
= 1750000, .max
= 3500000},
175 .n
= { .min
= 1, .max
= 4 },
176 .m
= { .min
= 104, .max
= 138 },
177 .m1
= { .min
= 16, .max
= 23 },
178 .m2
= { .min
= 5, .max
= 11 },
179 .p
= { .min
= 5, .max
= 80 },
180 .p1
= { .min
= 1, .max
= 8},
181 .p2
= { .dot_limit
= 165000,
182 .p2_slow
= 10, .p2_fast
= 5 },
185 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
186 .dot
= { .min
= 20000, .max
= 115000 },
187 .vco
= { .min
= 1750000, .max
= 3500000 },
188 .n
= { .min
= 1, .max
= 3 },
189 .m
= { .min
= 104, .max
= 138 },
190 .m1
= { .min
= 17, .max
= 23 },
191 .m2
= { .min
= 5, .max
= 11 },
192 .p
= { .min
= 28, .max
= 112 },
193 .p1
= { .min
= 2, .max
= 8 },
194 .p2
= { .dot_limit
= 0,
195 .p2_slow
= 14, .p2_fast
= 14
199 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
200 .dot
= { .min
= 80000, .max
= 224000 },
201 .vco
= { .min
= 1750000, .max
= 3500000 },
202 .n
= { .min
= 1, .max
= 3 },
203 .m
= { .min
= 104, .max
= 138 },
204 .m1
= { .min
= 17, .max
= 23 },
205 .m2
= { .min
= 5, .max
= 11 },
206 .p
= { .min
= 14, .max
= 42 },
207 .p1
= { .min
= 2, .max
= 6 },
208 .p2
= { .dot_limit
= 0,
209 .p2_slow
= 7, .p2_fast
= 7
213 static const intel_limit_t intel_limits_pineview_sdvo
= {
214 .dot
= { .min
= 20000, .max
= 400000},
215 .vco
= { .min
= 1700000, .max
= 3500000 },
216 /* Pineview's Ncounter is a ring counter */
217 .n
= { .min
= 3, .max
= 6 },
218 .m
= { .min
= 2, .max
= 256 },
219 /* Pineview only has one combined m divider, which we treat as m2. */
220 .m1
= { .min
= 0, .max
= 0 },
221 .m2
= { .min
= 0, .max
= 254 },
222 .p
= { .min
= 5, .max
= 80 },
223 .p1
= { .min
= 1, .max
= 8 },
224 .p2
= { .dot_limit
= 200000,
225 .p2_slow
= 10, .p2_fast
= 5 },
228 static const intel_limit_t intel_limits_pineview_lvds
= {
229 .dot
= { .min
= 20000, .max
= 400000 },
230 .vco
= { .min
= 1700000, .max
= 3500000 },
231 .n
= { .min
= 3, .max
= 6 },
232 .m
= { .min
= 2, .max
= 256 },
233 .m1
= { .min
= 0, .max
= 0 },
234 .m2
= { .min
= 0, .max
= 254 },
235 .p
= { .min
= 7, .max
= 112 },
236 .p1
= { .min
= 1, .max
= 8 },
237 .p2
= { .dot_limit
= 112000,
238 .p2_slow
= 14, .p2_fast
= 14 },
241 /* Ironlake / Sandybridge
243 * We calculate clock using (register_value + 2) for N/M1/M2, so here
244 * the range value for them is (actual_value - 2).
246 static const intel_limit_t intel_limits_ironlake_dac
= {
247 .dot
= { .min
= 25000, .max
= 350000 },
248 .vco
= { .min
= 1760000, .max
= 3510000 },
249 .n
= { .min
= 1, .max
= 5 },
250 .m
= { .min
= 79, .max
= 127 },
251 .m1
= { .min
= 12, .max
= 22 },
252 .m2
= { .min
= 5, .max
= 9 },
253 .p
= { .min
= 5, .max
= 80 },
254 .p1
= { .min
= 1, .max
= 8 },
255 .p2
= { .dot_limit
= 225000,
256 .p2_slow
= 10, .p2_fast
= 5 },
259 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
260 .dot
= { .min
= 25000, .max
= 350000 },
261 .vco
= { .min
= 1760000, .max
= 3510000 },
262 .n
= { .min
= 1, .max
= 3 },
263 .m
= { .min
= 79, .max
= 118 },
264 .m1
= { .min
= 12, .max
= 22 },
265 .m2
= { .min
= 5, .max
= 9 },
266 .p
= { .min
= 28, .max
= 112 },
267 .p1
= { .min
= 2, .max
= 8 },
268 .p2
= { .dot_limit
= 225000,
269 .p2_slow
= 14, .p2_fast
= 14 },
272 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
273 .dot
= { .min
= 25000, .max
= 350000 },
274 .vco
= { .min
= 1760000, .max
= 3510000 },
275 .n
= { .min
= 1, .max
= 3 },
276 .m
= { .min
= 79, .max
= 127 },
277 .m1
= { .min
= 12, .max
= 22 },
278 .m2
= { .min
= 5, .max
= 9 },
279 .p
= { .min
= 14, .max
= 56 },
280 .p1
= { .min
= 2, .max
= 8 },
281 .p2
= { .dot_limit
= 225000,
282 .p2_slow
= 7, .p2_fast
= 7 },
285 /* LVDS 100mhz refclk limits. */
286 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
287 .dot
= { .min
= 25000, .max
= 350000 },
288 .vco
= { .min
= 1760000, .max
= 3510000 },
289 .n
= { .min
= 1, .max
= 2 },
290 .m
= { .min
= 79, .max
= 126 },
291 .m1
= { .min
= 12, .max
= 22 },
292 .m2
= { .min
= 5, .max
= 9 },
293 .p
= { .min
= 28, .max
= 112 },
294 .p1
= { .min
= 2, .max
= 8 },
295 .p2
= { .dot_limit
= 225000,
296 .p2_slow
= 14, .p2_fast
= 14 },
299 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
300 .dot
= { .min
= 25000, .max
= 350000 },
301 .vco
= { .min
= 1760000, .max
= 3510000 },
302 .n
= { .min
= 1, .max
= 3 },
303 .m
= { .min
= 79, .max
= 126 },
304 .m1
= { .min
= 12, .max
= 22 },
305 .m2
= { .min
= 5, .max
= 9 },
306 .p
= { .min
= 14, .max
= 42 },
307 .p1
= { .min
= 2, .max
= 6 },
308 .p2
= { .dot_limit
= 225000,
309 .p2_slow
= 7, .p2_fast
= 7 },
312 static const intel_limit_t intel_limits_vlv
= {
314 * These are the data rate limits (measured in fast clocks)
315 * since those are the strictest limits we have. The fast
316 * clock and actual rate limits are more relaxed, so checking
317 * them would make no difference.
319 .dot
= { .min
= 25000 * 5, .max
= 270000 * 5 },
320 .vco
= { .min
= 4000000, .max
= 6000000 },
321 .n
= { .min
= 1, .max
= 7 },
322 .m1
= { .min
= 2, .max
= 3 },
323 .m2
= { .min
= 11, .max
= 156 },
324 .p1
= { .min
= 2, .max
= 3 },
325 .p2
= { .p2_slow
= 2, .p2_fast
= 20 }, /* slow=min, fast=max */
328 static void vlv_clock(int refclk
, intel_clock_t
*clock
)
330 clock
->m
= clock
->m1
* clock
->m2
;
331 clock
->p
= clock
->p1
* clock
->p2
;
332 clock
->vco
= refclk
* clock
->m
/ clock
->n
;
333 clock
->dot
= clock
->vco
/ clock
->p
;
337 * Returns whether any output on the specified pipe is of the specified type
339 static bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
341 struct drm_device
*dev
= crtc
->dev
;
342 struct intel_encoder
*encoder
;
344 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
345 if (encoder
->type
== type
)
351 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
,
354 struct drm_device
*dev
= crtc
->dev
;
355 const intel_limit_t
*limit
;
357 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
358 if (intel_is_dual_link_lvds(dev
)) {
359 if (refclk
== 100000)
360 limit
= &intel_limits_ironlake_dual_lvds_100m
;
362 limit
= &intel_limits_ironlake_dual_lvds
;
364 if (refclk
== 100000)
365 limit
= &intel_limits_ironlake_single_lvds_100m
;
367 limit
= &intel_limits_ironlake_single_lvds
;
370 limit
= &intel_limits_ironlake_dac
;
375 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
377 struct drm_device
*dev
= crtc
->dev
;
378 const intel_limit_t
*limit
;
380 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
381 if (intel_is_dual_link_lvds(dev
))
382 limit
= &intel_limits_g4x_dual_channel_lvds
;
384 limit
= &intel_limits_g4x_single_channel_lvds
;
385 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
386 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
387 limit
= &intel_limits_g4x_hdmi
;
388 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
389 limit
= &intel_limits_g4x_sdvo
;
390 } else /* The option is for other outputs */
391 limit
= &intel_limits_i9xx_sdvo
;
396 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
, int refclk
)
398 struct drm_device
*dev
= crtc
->dev
;
399 const intel_limit_t
*limit
;
401 if (HAS_PCH_SPLIT(dev
))
402 limit
= intel_ironlake_limit(crtc
, refclk
);
403 else if (IS_G4X(dev
)) {
404 limit
= intel_g4x_limit(crtc
);
405 } else if (IS_PINEVIEW(dev
)) {
406 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
407 limit
= &intel_limits_pineview_lvds
;
409 limit
= &intel_limits_pineview_sdvo
;
410 } else if (IS_VALLEYVIEW(dev
)) {
411 limit
= &intel_limits_vlv
;
412 } else if (!IS_GEN2(dev
)) {
413 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
414 limit
= &intel_limits_i9xx_lvds
;
416 limit
= &intel_limits_i9xx_sdvo
;
418 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
419 limit
= &intel_limits_i8xx_lvds
;
420 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
))
421 limit
= &intel_limits_i8xx_dvo
;
423 limit
= &intel_limits_i8xx_dac
;
428 /* m1 is reserved as 0 in Pineview, n is a ring counter */
429 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
431 clock
->m
= clock
->m2
+ 2;
432 clock
->p
= clock
->p1
* clock
->p2
;
433 clock
->vco
= refclk
* clock
->m
/ clock
->n
;
434 clock
->dot
= clock
->vco
/ clock
->p
;
437 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
439 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
442 static void i9xx_clock(int refclk
, intel_clock_t
*clock
)
444 clock
->m
= i9xx_dpll_compute_m(clock
);
445 clock
->p
= clock
->p1
* clock
->p2
;
446 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
447 clock
->dot
= clock
->vco
/ clock
->p
;
450 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
452 * Returns whether the given set of divisors are valid for a given refclk with
453 * the given connectors.
456 static bool intel_PLL_is_valid(struct drm_device
*dev
,
457 const intel_limit_t
*limit
,
458 const intel_clock_t
*clock
)
460 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
461 INTELPllInvalid("n out of range\n");
462 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
463 INTELPllInvalid("p1 out of range\n");
464 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
465 INTELPllInvalid("m2 out of range\n");
466 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
467 INTELPllInvalid("m1 out of range\n");
469 if (!IS_PINEVIEW(dev
) && !IS_VALLEYVIEW(dev
))
470 if (clock
->m1
<= clock
->m2
)
471 INTELPllInvalid("m1 <= m2\n");
473 if (!IS_VALLEYVIEW(dev
)) {
474 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
475 INTELPllInvalid("p out of range\n");
476 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
477 INTELPllInvalid("m out of range\n");
480 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
481 INTELPllInvalid("vco out of range\n");
482 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
483 * connector, etc., rather than just a single range.
485 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
486 INTELPllInvalid("dot out of range\n");
492 i9xx_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
493 int target
, int refclk
, intel_clock_t
*match_clock
,
494 intel_clock_t
*best_clock
)
496 struct drm_device
*dev
= crtc
->dev
;
500 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
502 * For LVDS just rely on its current settings for dual-channel.
503 * We haven't figured out how to reliably set up different
504 * single/dual channel state, if we even can.
506 if (intel_is_dual_link_lvds(dev
))
507 clock
.p2
= limit
->p2
.p2_fast
;
509 clock
.p2
= limit
->p2
.p2_slow
;
511 if (target
< limit
->p2
.dot_limit
)
512 clock
.p2
= limit
->p2
.p2_slow
;
514 clock
.p2
= limit
->p2
.p2_fast
;
517 memset(best_clock
, 0, sizeof(*best_clock
));
519 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
521 for (clock
.m2
= limit
->m2
.min
;
522 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
523 if (clock
.m2
>= clock
.m1
)
525 for (clock
.n
= limit
->n
.min
;
526 clock
.n
<= limit
->n
.max
; clock
.n
++) {
527 for (clock
.p1
= limit
->p1
.min
;
528 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
531 i9xx_clock(refclk
, &clock
);
532 if (!intel_PLL_is_valid(dev
, limit
,
536 clock
.p
!= match_clock
->p
)
539 this_err
= abs(clock
.dot
- target
);
540 if (this_err
< err
) {
549 return (err
!= target
);
553 pnv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
554 int target
, int refclk
, intel_clock_t
*match_clock
,
555 intel_clock_t
*best_clock
)
557 struct drm_device
*dev
= crtc
->dev
;
561 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
563 * For LVDS just rely on its current settings for dual-channel.
564 * We haven't figured out how to reliably set up different
565 * single/dual channel state, if we even can.
567 if (intel_is_dual_link_lvds(dev
))
568 clock
.p2
= limit
->p2
.p2_fast
;
570 clock
.p2
= limit
->p2
.p2_slow
;
572 if (target
< limit
->p2
.dot_limit
)
573 clock
.p2
= limit
->p2
.p2_slow
;
575 clock
.p2
= limit
->p2
.p2_fast
;
578 memset(best_clock
, 0, sizeof(*best_clock
));
580 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
582 for (clock
.m2
= limit
->m2
.min
;
583 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
584 for (clock
.n
= limit
->n
.min
;
585 clock
.n
<= limit
->n
.max
; clock
.n
++) {
586 for (clock
.p1
= limit
->p1
.min
;
587 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
590 pineview_clock(refclk
, &clock
);
591 if (!intel_PLL_is_valid(dev
, limit
,
595 clock
.p
!= match_clock
->p
)
598 this_err
= abs(clock
.dot
- target
);
599 if (this_err
< err
) {
608 return (err
!= target
);
612 g4x_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
613 int target
, int refclk
, intel_clock_t
*match_clock
,
614 intel_clock_t
*best_clock
)
616 struct drm_device
*dev
= crtc
->dev
;
620 /* approximately equals target * 0.00585 */
621 int err_most
= (target
>> 8) + (target
>> 9);
624 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
625 if (intel_is_dual_link_lvds(dev
))
626 clock
.p2
= limit
->p2
.p2_fast
;
628 clock
.p2
= limit
->p2
.p2_slow
;
630 if (target
< limit
->p2
.dot_limit
)
631 clock
.p2
= limit
->p2
.p2_slow
;
633 clock
.p2
= limit
->p2
.p2_fast
;
636 memset(best_clock
, 0, sizeof(*best_clock
));
637 max_n
= limit
->n
.max
;
638 /* based on hardware requirement, prefer smaller n to precision */
639 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
640 /* based on hardware requirement, prefere larger m1,m2 */
641 for (clock
.m1
= limit
->m1
.max
;
642 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
643 for (clock
.m2
= limit
->m2
.max
;
644 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
645 for (clock
.p1
= limit
->p1
.max
;
646 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
649 i9xx_clock(refclk
, &clock
);
650 if (!intel_PLL_is_valid(dev
, limit
,
654 this_err
= abs(clock
.dot
- target
);
655 if (this_err
< err_most
) {
669 vlv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
670 int target
, int refclk
, intel_clock_t
*match_clock
,
671 intel_clock_t
*best_clock
)
673 struct drm_device
*dev
= crtc
->dev
;
675 unsigned int bestppm
= 1000000;
676 /* min update 19.2 MHz */
677 int max_n
= min(limit
->n
.max
, refclk
/ 19200);
680 target
*= 5; /* fast clock */
682 memset(best_clock
, 0, sizeof(*best_clock
));
684 /* based on hardware requirement, prefer smaller n to precision */
685 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
686 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
687 for (clock
.p2
= limit
->p2
.p2_fast
; clock
.p2
>= limit
->p2
.p2_slow
;
688 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
689 clock
.p
= clock
.p1
* clock
.p2
;
690 /* based on hardware requirement, prefer bigger m1,m2 values */
691 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
692 unsigned int ppm
, diff
;
694 clock
.m2
= DIV_ROUND_CLOSEST(target
* clock
.p
* clock
.n
,
697 vlv_clock(refclk
, &clock
);
699 if (!intel_PLL_is_valid(dev
, limit
,
703 diff
= abs(clock
.dot
- target
);
704 ppm
= div_u64(1000000ULL * diff
, target
);
706 if (ppm
< 100 && clock
.p
> best_clock
->p
) {
712 if (bestppm
>= 10 && ppm
< bestppm
- 10) {
725 bool intel_crtc_active(struct drm_crtc
*crtc
)
727 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
729 /* Be paranoid as we can arrive here with only partial
730 * state retrieved from the hardware during setup.
732 * We can ditch the adjusted_mode.crtc_clock check as soon
733 * as Haswell has gained clock readout/fastboot support.
735 * We can ditch the crtc->fb check as soon as we can
736 * properly reconstruct framebuffers.
738 return intel_crtc
->active
&& crtc
->fb
&&
739 intel_crtc
->config
.adjusted_mode
.crtc_clock
;
742 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
745 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
746 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
748 return intel_crtc
->config
.cpu_transcoder
;
751 static void ironlake_wait_for_vblank(struct drm_device
*dev
, int pipe
)
753 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
754 u32 frame
, frame_reg
= PIPEFRAME(pipe
);
756 frame
= I915_READ(frame_reg
);
758 if (wait_for(I915_READ_NOTRACE(frame_reg
) != frame
, 50))
759 DRM_DEBUG_KMS("vblank wait timed out\n");
763 * intel_wait_for_vblank - wait for vblank on a given pipe
765 * @pipe: pipe to wait for
767 * Wait for vblank to occur on a given pipe. Needed for various bits of
770 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
772 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
773 int pipestat_reg
= PIPESTAT(pipe
);
775 if (INTEL_INFO(dev
)->gen
>= 5) {
776 ironlake_wait_for_vblank(dev
, pipe
);
780 /* Clear existing vblank status. Note this will clear any other
781 * sticky status fields as well.
783 * This races with i915_driver_irq_handler() with the result
784 * that either function could miss a vblank event. Here it is not
785 * fatal, as we will either wait upon the next vblank interrupt or
786 * timeout. Generally speaking intel_wait_for_vblank() is only
787 * called during modeset at which time the GPU should be idle and
788 * should *not* be performing page flips and thus not waiting on
790 * Currently, the result of us stealing a vblank from the irq
791 * handler is that a single frame will be skipped during swapbuffers.
793 I915_WRITE(pipestat_reg
,
794 I915_READ(pipestat_reg
) | PIPE_VBLANK_INTERRUPT_STATUS
);
796 /* Wait for vblank interrupt bit to set */
797 if (wait_for(I915_READ(pipestat_reg
) &
798 PIPE_VBLANK_INTERRUPT_STATUS
,
800 DRM_DEBUG_KMS("vblank wait timed out\n");
804 * intel_wait_for_pipe_off - wait for pipe to turn off
806 * @pipe: pipe to wait for
808 * After disabling a pipe, we can't wait for vblank in the usual way,
809 * spinning on the vblank interrupt status bit, since we won't actually
810 * see an interrupt when the pipe is disabled.
813 * wait for the pipe register state bit to turn off
816 * wait for the display line value to settle (it usually
817 * ends up stopping at the start of the next frame).
820 void intel_wait_for_pipe_off(struct drm_device
*dev
, int pipe
)
822 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
823 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
826 if (INTEL_INFO(dev
)->gen
>= 4) {
827 int reg
= PIPECONF(cpu_transcoder
);
829 /* Wait for the Pipe State to go off */
830 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
832 WARN(1, "pipe_off wait timed out\n");
834 u32 last_line
, line_mask
;
835 int reg
= PIPEDSL(pipe
);
836 unsigned long timeout
= jiffies
+ msecs_to_jiffies(100);
839 line_mask
= DSL_LINEMASK_GEN2
;
841 line_mask
= DSL_LINEMASK_GEN3
;
843 /* Wait for the display line to settle */
845 last_line
= I915_READ(reg
) & line_mask
;
847 } while (((I915_READ(reg
) & line_mask
) != last_line
) &&
848 time_after(timeout
, jiffies
));
849 if (time_after(jiffies
, timeout
))
850 WARN(1, "pipe_off wait timed out\n");
855 * ibx_digital_port_connected - is the specified port connected?
856 * @dev_priv: i915 private structure
857 * @port: the port to test
859 * Returns true if @port is connected, false otherwise.
861 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
862 struct intel_digital_port
*port
)
866 if (HAS_PCH_IBX(dev_priv
->dev
)) {
869 bit
= SDE_PORTB_HOTPLUG
;
872 bit
= SDE_PORTC_HOTPLUG
;
875 bit
= SDE_PORTD_HOTPLUG
;
883 bit
= SDE_PORTB_HOTPLUG_CPT
;
886 bit
= SDE_PORTC_HOTPLUG_CPT
;
889 bit
= SDE_PORTD_HOTPLUG_CPT
;
896 return I915_READ(SDEISR
) & bit
;
899 static const char *state_string(bool enabled
)
901 return enabled
? "on" : "off";
904 /* Only for pre-ILK configs */
905 void assert_pll(struct drm_i915_private
*dev_priv
,
906 enum pipe pipe
, bool state
)
913 val
= I915_READ(reg
);
914 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
915 WARN(cur_state
!= state
,
916 "PLL state assertion failure (expected %s, current %s)\n",
917 state_string(state
), state_string(cur_state
));
920 /* XXX: the dsi pll is shared between MIPI DSI ports */
921 static void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
926 mutex_lock(&dev_priv
->dpio_lock
);
927 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
928 mutex_unlock(&dev_priv
->dpio_lock
);
930 cur_state
= val
& DSI_PLL_VCO_EN
;
931 WARN(cur_state
!= state
,
932 "DSI PLL state assertion failure (expected %s, current %s)\n",
933 state_string(state
), state_string(cur_state
));
935 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
936 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
938 struct intel_shared_dpll
*
939 intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
)
941 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
943 if (crtc
->config
.shared_dpll
< 0)
946 return &dev_priv
->shared_dplls
[crtc
->config
.shared_dpll
];
950 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
951 struct intel_shared_dpll
*pll
,
955 struct intel_dpll_hw_state hw_state
;
957 if (HAS_PCH_LPT(dev_priv
->dev
)) {
958 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
963 "asserting DPLL %s with no DPLL\n", state_string(state
)))
966 cur_state
= pll
->get_hw_state(dev_priv
, pll
, &hw_state
);
967 WARN(cur_state
!= state
,
968 "%s assertion failure (expected %s, current %s)\n",
969 pll
->name
, state_string(state
), state_string(cur_state
));
972 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
973 enum pipe pipe
, bool state
)
978 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
981 if (HAS_DDI(dev_priv
->dev
)) {
982 /* DDI does not have a specific FDI_TX register */
983 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
984 val
= I915_READ(reg
);
985 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
987 reg
= FDI_TX_CTL(pipe
);
988 val
= I915_READ(reg
);
989 cur_state
= !!(val
& FDI_TX_ENABLE
);
991 WARN(cur_state
!= state
,
992 "FDI TX state assertion failure (expected %s, current %s)\n",
993 state_string(state
), state_string(cur_state
));
995 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
996 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
998 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
999 enum pipe pipe
, bool state
)
1005 reg
= FDI_RX_CTL(pipe
);
1006 val
= I915_READ(reg
);
1007 cur_state
= !!(val
& FDI_RX_ENABLE
);
1008 WARN(cur_state
!= state
,
1009 "FDI RX state assertion failure (expected %s, current %s)\n",
1010 state_string(state
), state_string(cur_state
));
1012 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1013 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1015 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1021 /* ILK FDI PLL is always enabled */
1022 if (dev_priv
->info
->gen
== 5)
1025 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1026 if (HAS_DDI(dev_priv
->dev
))
1029 reg
= FDI_TX_CTL(pipe
);
1030 val
= I915_READ(reg
);
1031 WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1034 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1035 enum pipe pipe
, bool state
)
1041 reg
= FDI_RX_CTL(pipe
);
1042 val
= I915_READ(reg
);
1043 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1044 WARN(cur_state
!= state
,
1045 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1046 state_string(state
), state_string(cur_state
));
1049 static void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1052 int pp_reg
, lvds_reg
;
1054 enum pipe panel_pipe
= PIPE_A
;
1057 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
1058 pp_reg
= PCH_PP_CONTROL
;
1059 lvds_reg
= PCH_LVDS
;
1061 pp_reg
= PP_CONTROL
;
1065 val
= I915_READ(pp_reg
);
1066 if (!(val
& PANEL_POWER_ON
) ||
1067 ((val
& PANEL_UNLOCK_REGS
) == PANEL_UNLOCK_REGS
))
1070 if (I915_READ(lvds_reg
) & LVDS_PIPEB_SELECT
)
1071 panel_pipe
= PIPE_B
;
1073 WARN(panel_pipe
== pipe
&& locked
,
1074 "panel assertion failure, pipe %c regs locked\n",
1078 static void assert_cursor(struct drm_i915_private
*dev_priv
,
1079 enum pipe pipe
, bool state
)
1081 struct drm_device
*dev
= dev_priv
->dev
;
1084 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
1085 cur_state
= I915_READ(CURCNTR_IVB(pipe
)) & CURSOR_MODE
;
1086 else if (IS_845G(dev
) || IS_I865G(dev
))
1087 cur_state
= I915_READ(_CURACNTR
) & CURSOR_ENABLE
;
1089 cur_state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
1091 WARN(cur_state
!= state
,
1092 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1093 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1095 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1096 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1098 void assert_pipe(struct drm_i915_private
*dev_priv
,
1099 enum pipe pipe
, bool state
)
1104 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1107 /* if we need the pipe A quirk it must be always on */
1108 if (pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
1111 if (!intel_display_power_enabled(dev_priv
->dev
,
1112 POWER_DOMAIN_TRANSCODER(cpu_transcoder
))) {
1115 reg
= PIPECONF(cpu_transcoder
);
1116 val
= I915_READ(reg
);
1117 cur_state
= !!(val
& PIPECONF_ENABLE
);
1120 WARN(cur_state
!= state
,
1121 "pipe %c assertion failure (expected %s, current %s)\n",
1122 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1125 static void assert_plane(struct drm_i915_private
*dev_priv
,
1126 enum plane plane
, bool state
)
1132 reg
= DSPCNTR(plane
);
1133 val
= I915_READ(reg
);
1134 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1135 WARN(cur_state
!= state
,
1136 "plane %c assertion failure (expected %s, current %s)\n",
1137 plane_name(plane
), state_string(state
), state_string(cur_state
));
1140 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1141 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1143 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1146 struct drm_device
*dev
= dev_priv
->dev
;
1151 /* Primary planes are fixed to pipes on gen4+ */
1152 if (INTEL_INFO(dev
)->gen
>= 4) {
1153 reg
= DSPCNTR(pipe
);
1154 val
= I915_READ(reg
);
1155 WARN((val
& DISPLAY_PLANE_ENABLE
),
1156 "plane %c assertion failure, should be disabled but not\n",
1161 /* Need to check both planes against the pipe */
1164 val
= I915_READ(reg
);
1165 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1166 DISPPLANE_SEL_PIPE_SHIFT
;
1167 WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1168 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1169 plane_name(i
), pipe_name(pipe
));
1173 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1176 struct drm_device
*dev
= dev_priv
->dev
;
1180 if (IS_VALLEYVIEW(dev
)) {
1181 for (i
= 0; i
< dev_priv
->num_plane
; i
++) {
1182 reg
= SPCNTR(pipe
, i
);
1183 val
= I915_READ(reg
);
1184 WARN((val
& SP_ENABLE
),
1185 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1186 sprite_name(pipe
, i
), pipe_name(pipe
));
1188 } else if (INTEL_INFO(dev
)->gen
>= 7) {
1190 val
= I915_READ(reg
);
1191 WARN((val
& SPRITE_ENABLE
),
1192 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1193 plane_name(pipe
), pipe_name(pipe
));
1194 } else if (INTEL_INFO(dev
)->gen
>= 5) {
1195 reg
= DVSCNTR(pipe
);
1196 val
= I915_READ(reg
);
1197 WARN((val
& DVS_ENABLE
),
1198 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1199 plane_name(pipe
), pipe_name(pipe
));
1203 static void assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1208 if (HAS_PCH_LPT(dev_priv
->dev
)) {
1209 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1213 val
= I915_READ(PCH_DREF_CONTROL
);
1214 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1215 DREF_SUPERSPREAD_SOURCE_MASK
));
1216 WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1219 static void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1226 reg
= PCH_TRANSCONF(pipe
);
1227 val
= I915_READ(reg
);
1228 enabled
= !!(val
& TRANS_ENABLE
);
1230 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1234 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1235 enum pipe pipe
, u32 port_sel
, u32 val
)
1237 if ((val
& DP_PORT_EN
) == 0)
1240 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1241 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1242 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1243 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1246 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1252 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1253 enum pipe pipe
, u32 val
)
1255 if ((val
& SDVO_ENABLE
) == 0)
1258 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1259 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1262 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1268 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1269 enum pipe pipe
, u32 val
)
1271 if ((val
& LVDS_PORT_EN
) == 0)
1274 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1275 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1278 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1284 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1285 enum pipe pipe
, u32 val
)
1287 if ((val
& ADPA_DAC_ENABLE
) == 0)
1289 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1290 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1293 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1299 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1300 enum pipe pipe
, int reg
, u32 port_sel
)
1302 u32 val
= I915_READ(reg
);
1303 WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1304 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1305 reg
, pipe_name(pipe
));
1307 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1308 && (val
& DP_PIPEB_SELECT
),
1309 "IBX PCH dp port still using transcoder B\n");
1312 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1313 enum pipe pipe
, int reg
)
1315 u32 val
= I915_READ(reg
);
1316 WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1317 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1318 reg
, pipe_name(pipe
));
1320 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_ENABLE
) == 0
1321 && (val
& SDVO_PIPE_B_SELECT
),
1322 "IBX PCH hdmi port still using transcoder B\n");
1325 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1331 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1332 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1333 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1336 val
= I915_READ(reg
);
1337 WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1338 "PCH VGA enabled on transcoder %c, should be disabled\n",
1342 val
= I915_READ(reg
);
1343 WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1344 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1347 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1348 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1349 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1352 static void intel_init_dpio(struct drm_device
*dev
)
1354 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1356 if (!IS_VALLEYVIEW(dev
))
1360 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1361 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
1362 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
1363 * b. The other bits such as sfr settings / modesel may all be set
1366 * This should only be done on init and resume from S3 with both
1367 * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1369 I915_WRITE(DPIO_CTL
, I915_READ(DPIO_CTL
) | DPIO_CMNRST
);
1372 static void vlv_enable_pll(struct intel_crtc
*crtc
)
1374 struct drm_device
*dev
= crtc
->base
.dev
;
1375 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1376 int reg
= DPLL(crtc
->pipe
);
1377 u32 dpll
= crtc
->config
.dpll_hw_state
.dpll
;
1379 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1381 /* No really, not for ILK+ */
1382 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
));
1384 /* PLL is protected by panel, make sure we can write it */
1385 if (IS_MOBILE(dev_priv
->dev
) && !IS_I830(dev_priv
->dev
))
1386 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1388 I915_WRITE(reg
, dpll
);
1392 if (wait_for(((I915_READ(reg
) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1393 DRM_ERROR("DPLL %d failed to lock\n", crtc
->pipe
);
1395 I915_WRITE(DPLL_MD(crtc
->pipe
), crtc
->config
.dpll_hw_state
.dpll_md
);
1396 POSTING_READ(DPLL_MD(crtc
->pipe
));
1398 /* We do this three times for luck */
1399 I915_WRITE(reg
, dpll
);
1401 udelay(150); /* wait for warmup */
1402 I915_WRITE(reg
, dpll
);
1404 udelay(150); /* wait for warmup */
1405 I915_WRITE(reg
, dpll
);
1407 udelay(150); /* wait for warmup */
1410 static void i9xx_enable_pll(struct intel_crtc
*crtc
)
1412 struct drm_device
*dev
= crtc
->base
.dev
;
1413 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1414 int reg
= DPLL(crtc
->pipe
);
1415 u32 dpll
= crtc
->config
.dpll_hw_state
.dpll
;
1417 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1419 /* No really, not for ILK+ */
1420 BUG_ON(dev_priv
->info
->gen
>= 5);
1422 /* PLL is protected by panel, make sure we can write it */
1423 if (IS_MOBILE(dev
) && !IS_I830(dev
))
1424 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1426 I915_WRITE(reg
, dpll
);
1428 /* Wait for the clocks to stabilize. */
1432 if (INTEL_INFO(dev
)->gen
>= 4) {
1433 I915_WRITE(DPLL_MD(crtc
->pipe
),
1434 crtc
->config
.dpll_hw_state
.dpll_md
);
1436 /* The pixel multiplier can only be updated once the
1437 * DPLL is enabled and the clocks are stable.
1439 * So write it again.
1441 I915_WRITE(reg
, dpll
);
1444 /* We do this three times for luck */
1445 I915_WRITE(reg
, dpll
);
1447 udelay(150); /* wait for warmup */
1448 I915_WRITE(reg
, dpll
);
1450 udelay(150); /* wait for warmup */
1451 I915_WRITE(reg
, dpll
);
1453 udelay(150); /* wait for warmup */
1457 * i9xx_disable_pll - disable a PLL
1458 * @dev_priv: i915 private structure
1459 * @pipe: pipe PLL to disable
1461 * Disable the PLL for @pipe, making sure the pipe is off first.
1463 * Note! This is for pre-ILK only.
1465 static void i9xx_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1467 /* Don't disable pipe A or pipe A PLLs if needed */
1468 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1471 /* Make sure the pipe isn't still relying on us */
1472 assert_pipe_disabled(dev_priv
, pipe
);
1474 I915_WRITE(DPLL(pipe
), 0);
1475 POSTING_READ(DPLL(pipe
));
1478 static void vlv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1482 /* Make sure the pipe isn't still relying on us */
1483 assert_pipe_disabled(dev_priv
, pipe
);
1485 /* Leave integrated clock source enabled */
1487 val
= DPLL_INTEGRATED_CRI_CLK_VLV
;
1488 I915_WRITE(DPLL(pipe
), val
);
1489 POSTING_READ(DPLL(pipe
));
1492 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
, int port
)
1497 port_mask
= DPLL_PORTB_READY_MASK
;
1499 port_mask
= DPLL_PORTC_READY_MASK
;
1501 if (wait_for((I915_READ(DPLL(0)) & port_mask
) == 0, 1000))
1502 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1503 'B' + port
, I915_READ(DPLL(0)));
1507 * ironlake_enable_shared_dpll - enable PCH PLL
1508 * @dev_priv: i915 private structure
1509 * @pipe: pipe PLL to enable
1511 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1512 * drives the transcoder clock.
1514 static void ironlake_enable_shared_dpll(struct intel_crtc
*crtc
)
1516 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1517 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1519 /* PCH PLLs only available on ILK, SNB and IVB */
1520 BUG_ON(dev_priv
->info
->gen
< 5);
1521 if (WARN_ON(pll
== NULL
))
1524 if (WARN_ON(pll
->refcount
== 0))
1527 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1528 pll
->name
, pll
->active
, pll
->on
,
1529 crtc
->base
.base
.id
);
1531 if (pll
->active
++) {
1533 assert_shared_dpll_enabled(dev_priv
, pll
);
1538 DRM_DEBUG_KMS("enabling %s\n", pll
->name
);
1539 pll
->enable(dev_priv
, pll
);
1543 static void intel_disable_shared_dpll(struct intel_crtc
*crtc
)
1545 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1546 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1548 /* PCH only available on ILK+ */
1549 BUG_ON(dev_priv
->info
->gen
< 5);
1550 if (WARN_ON(pll
== NULL
))
1553 if (WARN_ON(pll
->refcount
== 0))
1556 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1557 pll
->name
, pll
->active
, pll
->on
,
1558 crtc
->base
.base
.id
);
1560 if (WARN_ON(pll
->active
== 0)) {
1561 assert_shared_dpll_disabled(dev_priv
, pll
);
1565 assert_shared_dpll_enabled(dev_priv
, pll
);
1570 DRM_DEBUG_KMS("disabling %s\n", pll
->name
);
1571 pll
->disable(dev_priv
, pll
);
1575 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1578 struct drm_device
*dev
= dev_priv
->dev
;
1579 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1580 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1581 uint32_t reg
, val
, pipeconf_val
;
1583 /* PCH only available on ILK+ */
1584 BUG_ON(dev_priv
->info
->gen
< 5);
1586 /* Make sure PCH DPLL is enabled */
1587 assert_shared_dpll_enabled(dev_priv
,
1588 intel_crtc_to_shared_dpll(intel_crtc
));
1590 /* FDI must be feeding us bits for PCH ports */
1591 assert_fdi_tx_enabled(dev_priv
, pipe
);
1592 assert_fdi_rx_enabled(dev_priv
, pipe
);
1594 if (HAS_PCH_CPT(dev
)) {
1595 /* Workaround: Set the timing override bit before enabling the
1596 * pch transcoder. */
1597 reg
= TRANS_CHICKEN2(pipe
);
1598 val
= I915_READ(reg
);
1599 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1600 I915_WRITE(reg
, val
);
1603 reg
= PCH_TRANSCONF(pipe
);
1604 val
= I915_READ(reg
);
1605 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1607 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1609 * make the BPC in transcoder be consistent with
1610 * that in pipeconf reg.
1612 val
&= ~PIPECONF_BPC_MASK
;
1613 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1616 val
&= ~TRANS_INTERLACE_MASK
;
1617 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1618 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1619 intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
))
1620 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1622 val
|= TRANS_INTERLACED
;
1624 val
|= TRANS_PROGRESSIVE
;
1626 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1627 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1628 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
1631 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1632 enum transcoder cpu_transcoder
)
1634 u32 val
, pipeconf_val
;
1636 /* PCH only available on ILK+ */
1637 BUG_ON(dev_priv
->info
->gen
< 5);
1639 /* FDI must be feeding us bits for PCH ports */
1640 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1641 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
1643 /* Workaround: set timing override bit. */
1644 val
= I915_READ(_TRANSA_CHICKEN2
);
1645 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1646 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1649 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1651 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1652 PIPECONF_INTERLACED_ILK
)
1653 val
|= TRANS_INTERLACED
;
1655 val
|= TRANS_PROGRESSIVE
;
1657 I915_WRITE(LPT_TRANSCONF
, val
);
1658 if (wait_for(I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
, 100))
1659 DRM_ERROR("Failed to enable PCH transcoder\n");
1662 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1665 struct drm_device
*dev
= dev_priv
->dev
;
1668 /* FDI relies on the transcoder */
1669 assert_fdi_tx_disabled(dev_priv
, pipe
);
1670 assert_fdi_rx_disabled(dev_priv
, pipe
);
1672 /* Ports must be off as well */
1673 assert_pch_ports_disabled(dev_priv
, pipe
);
1675 reg
= PCH_TRANSCONF(pipe
);
1676 val
= I915_READ(reg
);
1677 val
&= ~TRANS_ENABLE
;
1678 I915_WRITE(reg
, val
);
1679 /* wait for PCH transcoder off, transcoder state */
1680 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1681 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
1683 if (!HAS_PCH_IBX(dev
)) {
1684 /* Workaround: Clear the timing override chicken bit again. */
1685 reg
= TRANS_CHICKEN2(pipe
);
1686 val
= I915_READ(reg
);
1687 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1688 I915_WRITE(reg
, val
);
1692 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1696 val
= I915_READ(LPT_TRANSCONF
);
1697 val
&= ~TRANS_ENABLE
;
1698 I915_WRITE(LPT_TRANSCONF
, val
);
1699 /* wait for PCH transcoder off, transcoder state */
1700 if (wait_for((I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
) == 0, 50))
1701 DRM_ERROR("Failed to disable PCH transcoder\n");
1703 /* Workaround: clear timing override bit. */
1704 val
= I915_READ(_TRANSA_CHICKEN2
);
1705 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1706 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1710 * intel_enable_pipe - enable a pipe, asserting requirements
1711 * @dev_priv: i915 private structure
1712 * @pipe: pipe to enable
1713 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1715 * Enable @pipe, making sure that various hardware specific requirements
1716 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1718 * @pipe should be %PIPE_A or %PIPE_B.
1720 * Will wait until the pipe is actually running (i.e. first vblank) before
1723 static void intel_enable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
1724 bool pch_port
, bool dsi
)
1726 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1728 enum pipe pch_transcoder
;
1732 assert_planes_disabled(dev_priv
, pipe
);
1733 assert_cursor_disabled(dev_priv
, pipe
);
1734 assert_sprites_disabled(dev_priv
, pipe
);
1736 if (HAS_PCH_LPT(dev_priv
->dev
))
1737 pch_transcoder
= TRANSCODER_A
;
1739 pch_transcoder
= pipe
;
1742 * A pipe without a PLL won't actually be able to drive bits from
1743 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1746 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
1748 assert_dsi_pll_enabled(dev_priv
);
1750 assert_pll_enabled(dev_priv
, pipe
);
1753 /* if driving the PCH, we need FDI enabled */
1754 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
1755 assert_fdi_tx_pll_enabled(dev_priv
,
1756 (enum pipe
) cpu_transcoder
);
1758 /* FIXME: assert CPU port conditions for SNB+ */
1761 reg
= PIPECONF(cpu_transcoder
);
1762 val
= I915_READ(reg
);
1763 if (val
& PIPECONF_ENABLE
)
1766 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
1767 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1771 * intel_disable_pipe - disable a pipe, asserting requirements
1772 * @dev_priv: i915 private structure
1773 * @pipe: pipe to disable
1775 * Disable @pipe, making sure that various hardware specific requirements
1776 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1778 * @pipe should be %PIPE_A or %PIPE_B.
1780 * Will wait until the pipe has shut down before returning.
1782 static void intel_disable_pipe(struct drm_i915_private
*dev_priv
,
1785 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1791 * Make sure planes won't keep trying to pump pixels to us,
1792 * or we might hang the display.
1794 assert_planes_disabled(dev_priv
, pipe
);
1795 assert_cursor_disabled(dev_priv
, pipe
);
1796 assert_sprites_disabled(dev_priv
, pipe
);
1798 /* Don't disable pipe A or pipe A PLLs if needed */
1799 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1802 reg
= PIPECONF(cpu_transcoder
);
1803 val
= I915_READ(reg
);
1804 if ((val
& PIPECONF_ENABLE
) == 0)
1807 I915_WRITE(reg
, val
& ~PIPECONF_ENABLE
);
1808 intel_wait_for_pipe_off(dev_priv
->dev
, pipe
);
1812 * Plane regs are double buffered, going from enabled->disabled needs a
1813 * trigger in order to latch. The display address reg provides this.
1815 void intel_flush_display_plane(struct drm_i915_private
*dev_priv
,
1818 if (dev_priv
->info
->gen
>= 4)
1819 I915_WRITE(DSPSURF(plane
), I915_READ(DSPSURF(plane
)));
1821 I915_WRITE(DSPADDR(plane
), I915_READ(DSPADDR(plane
)));
1825 * intel_enable_plane - enable a display plane on a given pipe
1826 * @dev_priv: i915 private structure
1827 * @plane: plane to enable
1828 * @pipe: pipe being fed
1830 * Enable @plane on @pipe, making sure that @pipe is running first.
1832 static void intel_enable_plane(struct drm_i915_private
*dev_priv
,
1833 enum plane plane
, enum pipe pipe
)
1838 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1839 assert_pipe_enabled(dev_priv
, pipe
);
1841 reg
= DSPCNTR(plane
);
1842 val
= I915_READ(reg
);
1843 if (val
& DISPLAY_PLANE_ENABLE
)
1846 I915_WRITE(reg
, val
| DISPLAY_PLANE_ENABLE
);
1847 intel_flush_display_plane(dev_priv
, plane
);
1848 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1852 * intel_disable_plane - disable a display plane
1853 * @dev_priv: i915 private structure
1854 * @plane: plane to disable
1855 * @pipe: pipe consuming the data
1857 * Disable @plane; should be an independent operation.
1859 static void intel_disable_plane(struct drm_i915_private
*dev_priv
,
1860 enum plane plane
, enum pipe pipe
)
1865 reg
= DSPCNTR(plane
);
1866 val
= I915_READ(reg
);
1867 if ((val
& DISPLAY_PLANE_ENABLE
) == 0)
1870 I915_WRITE(reg
, val
& ~DISPLAY_PLANE_ENABLE
);
1871 intel_flush_display_plane(dev_priv
, plane
);
1872 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1875 static bool need_vtd_wa(struct drm_device
*dev
)
1877 #ifdef CONFIG_INTEL_IOMMU
1878 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
1885 intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
1886 struct drm_i915_gem_object
*obj
,
1887 struct intel_ring_buffer
*pipelined
)
1889 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1893 switch (obj
->tiling_mode
) {
1894 case I915_TILING_NONE
:
1895 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
1896 alignment
= 128 * 1024;
1897 else if (INTEL_INFO(dev
)->gen
>= 4)
1898 alignment
= 4 * 1024;
1900 alignment
= 64 * 1024;
1903 /* pin() will align the object as required by fence */
1907 /* Despite that we check this in framebuffer_init userspace can
1908 * screw us over and change the tiling after the fact. Only
1909 * pinned buffers can't change their tiling. */
1910 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1916 /* Note that the w/a also requires 64 PTE of padding following the
1917 * bo. We currently fill all unused PTE with the shadow page and so
1918 * we should always have valid PTE following the scanout preventing
1921 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
1922 alignment
= 256 * 1024;
1924 dev_priv
->mm
.interruptible
= false;
1925 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
);
1927 goto err_interruptible
;
1929 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1930 * fence, whereas 965+ only requires a fence if using
1931 * framebuffer compression. For simplicity, we always install
1932 * a fence as the cost is not that onerous.
1934 ret
= i915_gem_object_get_fence(obj
);
1938 i915_gem_object_pin_fence(obj
);
1940 dev_priv
->mm
.interruptible
= true;
1944 i915_gem_object_unpin_from_display_plane(obj
);
1946 dev_priv
->mm
.interruptible
= true;
1950 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
)
1952 i915_gem_object_unpin_fence(obj
);
1953 i915_gem_object_unpin_from_display_plane(obj
);
1956 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1957 * is assumed to be a power-of-two. */
1958 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
1959 unsigned int tiling_mode
,
1963 if (tiling_mode
!= I915_TILING_NONE
) {
1964 unsigned int tile_rows
, tiles
;
1969 tiles
= *x
/ (512/cpp
);
1972 return tile_rows
* pitch
* 8 + tiles
* 4096;
1974 unsigned int offset
;
1976 offset
= *y
* pitch
+ *x
* cpp
;
1978 *x
= (offset
& 4095) / cpp
;
1979 return offset
& -4096;
1983 static int i9xx_update_plane(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
1986 struct drm_device
*dev
= crtc
->dev
;
1987 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1988 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1989 struct intel_framebuffer
*intel_fb
;
1990 struct drm_i915_gem_object
*obj
;
1991 int plane
= intel_crtc
->plane
;
1992 unsigned long linear_offset
;
2001 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane
));
2005 intel_fb
= to_intel_framebuffer(fb
);
2006 obj
= intel_fb
->obj
;
2008 reg
= DSPCNTR(plane
);
2009 dspcntr
= I915_READ(reg
);
2010 /* Mask out pixel format bits in case we change it */
2011 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2012 switch (fb
->pixel_format
) {
2014 dspcntr
|= DISPPLANE_8BPP
;
2016 case DRM_FORMAT_XRGB1555
:
2017 case DRM_FORMAT_ARGB1555
:
2018 dspcntr
|= DISPPLANE_BGRX555
;
2020 case DRM_FORMAT_RGB565
:
2021 dspcntr
|= DISPPLANE_BGRX565
;
2023 case DRM_FORMAT_XRGB8888
:
2024 case DRM_FORMAT_ARGB8888
:
2025 dspcntr
|= DISPPLANE_BGRX888
;
2027 case DRM_FORMAT_XBGR8888
:
2028 case DRM_FORMAT_ABGR8888
:
2029 dspcntr
|= DISPPLANE_RGBX888
;
2031 case DRM_FORMAT_XRGB2101010
:
2032 case DRM_FORMAT_ARGB2101010
:
2033 dspcntr
|= DISPPLANE_BGRX101010
;
2035 case DRM_FORMAT_XBGR2101010
:
2036 case DRM_FORMAT_ABGR2101010
:
2037 dspcntr
|= DISPPLANE_RGBX101010
;
2043 if (INTEL_INFO(dev
)->gen
>= 4) {
2044 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2045 dspcntr
|= DISPPLANE_TILED
;
2047 dspcntr
&= ~DISPPLANE_TILED
;
2051 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2053 I915_WRITE(reg
, dspcntr
);
2055 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2057 if (INTEL_INFO(dev
)->gen
>= 4) {
2058 intel_crtc
->dspaddr_offset
=
2059 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2060 fb
->bits_per_pixel
/ 8,
2062 linear_offset
-= intel_crtc
->dspaddr_offset
;
2064 intel_crtc
->dspaddr_offset
= linear_offset
;
2067 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2068 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2070 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2071 if (INTEL_INFO(dev
)->gen
>= 4) {
2072 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2073 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2074 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2075 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2077 I915_WRITE(DSPADDR(plane
), i915_gem_obj_ggtt_offset(obj
) + linear_offset
);
2083 static int ironlake_update_plane(struct drm_crtc
*crtc
,
2084 struct drm_framebuffer
*fb
, int x
, int y
)
2086 struct drm_device
*dev
= crtc
->dev
;
2087 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2088 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2089 struct intel_framebuffer
*intel_fb
;
2090 struct drm_i915_gem_object
*obj
;
2091 int plane
= intel_crtc
->plane
;
2092 unsigned long linear_offset
;
2102 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane
));
2106 intel_fb
= to_intel_framebuffer(fb
);
2107 obj
= intel_fb
->obj
;
2109 reg
= DSPCNTR(plane
);
2110 dspcntr
= I915_READ(reg
);
2111 /* Mask out pixel format bits in case we change it */
2112 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2113 switch (fb
->pixel_format
) {
2115 dspcntr
|= DISPPLANE_8BPP
;
2117 case DRM_FORMAT_RGB565
:
2118 dspcntr
|= DISPPLANE_BGRX565
;
2120 case DRM_FORMAT_XRGB8888
:
2121 case DRM_FORMAT_ARGB8888
:
2122 dspcntr
|= DISPPLANE_BGRX888
;
2124 case DRM_FORMAT_XBGR8888
:
2125 case DRM_FORMAT_ABGR8888
:
2126 dspcntr
|= DISPPLANE_RGBX888
;
2128 case DRM_FORMAT_XRGB2101010
:
2129 case DRM_FORMAT_ARGB2101010
:
2130 dspcntr
|= DISPPLANE_BGRX101010
;
2132 case DRM_FORMAT_XBGR2101010
:
2133 case DRM_FORMAT_ABGR2101010
:
2134 dspcntr
|= DISPPLANE_RGBX101010
;
2140 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2141 dspcntr
|= DISPPLANE_TILED
;
2143 dspcntr
&= ~DISPPLANE_TILED
;
2145 if (IS_HASWELL(dev
))
2146 dspcntr
&= ~DISPPLANE_TRICKLE_FEED_DISABLE
;
2148 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2150 I915_WRITE(reg
, dspcntr
);
2152 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2153 intel_crtc
->dspaddr_offset
=
2154 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2155 fb
->bits_per_pixel
/ 8,
2157 linear_offset
-= intel_crtc
->dspaddr_offset
;
2159 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2160 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2162 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2163 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2164 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2165 if (IS_HASWELL(dev
)) {
2166 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2168 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2169 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2176 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2178 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2179 int x
, int y
, enum mode_set_atomic state
)
2181 struct drm_device
*dev
= crtc
->dev
;
2182 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2184 if (dev_priv
->display
.disable_fbc
)
2185 dev_priv
->display
.disable_fbc(dev
);
2186 intel_increase_pllclock(crtc
);
2188 return dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2191 void intel_display_handle_reset(struct drm_device
*dev
)
2193 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2194 struct drm_crtc
*crtc
;
2197 * Flips in the rings have been nuked by the reset,
2198 * so complete all pending flips so that user space
2199 * will get its events and not get stuck.
2201 * Also update the base address of all primary
2202 * planes to the the last fb to make sure we're
2203 * showing the correct fb after a reset.
2205 * Need to make two loops over the crtcs so that we
2206 * don't try to grab a crtc mutex before the
2207 * pending_flip_queue really got woken up.
2210 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2211 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2212 enum plane plane
= intel_crtc
->plane
;
2214 intel_prepare_page_flip(dev
, plane
);
2215 intel_finish_page_flip_plane(dev
, plane
);
2218 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2219 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2221 mutex_lock(&crtc
->mutex
);
2222 if (intel_crtc
->active
)
2223 dev_priv
->display
.update_plane(crtc
, crtc
->fb
,
2225 mutex_unlock(&crtc
->mutex
);
2230 intel_finish_fb(struct drm_framebuffer
*old_fb
)
2232 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(old_fb
)->obj
;
2233 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2234 bool was_interruptible
= dev_priv
->mm
.interruptible
;
2237 /* Big Hammer, we also need to ensure that any pending
2238 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2239 * current scanout is retired before unpinning the old
2242 * This should only fail upon a hung GPU, in which case we
2243 * can safely continue.
2245 dev_priv
->mm
.interruptible
= false;
2246 ret
= i915_gem_object_finish_gpu(obj
);
2247 dev_priv
->mm
.interruptible
= was_interruptible
;
2252 static void intel_crtc_update_sarea_pos(struct drm_crtc
*crtc
, int x
, int y
)
2254 struct drm_device
*dev
= crtc
->dev
;
2255 struct drm_i915_master_private
*master_priv
;
2256 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2258 if (!dev
->primary
->master
)
2261 master_priv
= dev
->primary
->master
->driver_priv
;
2262 if (!master_priv
->sarea_priv
)
2265 switch (intel_crtc
->pipe
) {
2267 master_priv
->sarea_priv
->pipeA_x
= x
;
2268 master_priv
->sarea_priv
->pipeA_y
= y
;
2271 master_priv
->sarea_priv
->pipeB_x
= x
;
2272 master_priv
->sarea_priv
->pipeB_y
= y
;
2280 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2281 struct drm_framebuffer
*fb
)
2283 struct drm_device
*dev
= crtc
->dev
;
2284 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2285 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2286 struct drm_framebuffer
*old_fb
;
2291 DRM_ERROR("No FB bound\n");
2295 if (intel_crtc
->plane
> INTEL_INFO(dev
)->num_pipes
) {
2296 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2297 plane_name(intel_crtc
->plane
),
2298 INTEL_INFO(dev
)->num_pipes
);
2302 mutex_lock(&dev
->struct_mutex
);
2303 ret
= intel_pin_and_fence_fb_obj(dev
,
2304 to_intel_framebuffer(fb
)->obj
,
2307 mutex_unlock(&dev
->struct_mutex
);
2308 DRM_ERROR("pin & fence failed\n");
2313 * Update pipe size and adjust fitter if needed: the reason for this is
2314 * that in compute_mode_changes we check the native mode (not the pfit
2315 * mode) to see if we can flip rather than do a full mode set. In the
2316 * fastboot case, we'll flip, but if we don't update the pipesrc and
2317 * pfit state, we'll end up with a big fb scanned out into the wrong
2320 * To fix this properly, we need to hoist the checks up into
2321 * compute_mode_changes (or above), check the actual pfit state and
2322 * whether the platform allows pfit disable with pipe active, and only
2323 * then update the pipesrc and pfit state, even on the flip path.
2325 if (i915_fastboot
) {
2326 const struct drm_display_mode
*adjusted_mode
=
2327 &intel_crtc
->config
.adjusted_mode
;
2329 I915_WRITE(PIPESRC(intel_crtc
->pipe
),
2330 ((adjusted_mode
->crtc_hdisplay
- 1) << 16) |
2331 (adjusted_mode
->crtc_vdisplay
- 1));
2332 if (!intel_crtc
->config
.pch_pfit
.enabled
&&
2333 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) ||
2334 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
2335 I915_WRITE(PF_CTL(intel_crtc
->pipe
), 0);
2336 I915_WRITE(PF_WIN_POS(intel_crtc
->pipe
), 0);
2337 I915_WRITE(PF_WIN_SZ(intel_crtc
->pipe
), 0);
2341 ret
= dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2343 intel_unpin_fb_obj(to_intel_framebuffer(fb
)->obj
);
2344 mutex_unlock(&dev
->struct_mutex
);
2345 DRM_ERROR("failed to update base address\n");
2355 if (intel_crtc
->active
&& old_fb
!= fb
)
2356 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2357 intel_unpin_fb_obj(to_intel_framebuffer(old_fb
)->obj
);
2360 intel_update_fbc(dev
);
2361 intel_edp_psr_update(dev
);
2362 mutex_unlock(&dev
->struct_mutex
);
2364 intel_crtc_update_sarea_pos(crtc
, x
, y
);
2369 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
2371 struct drm_device
*dev
= crtc
->dev
;
2372 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2373 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2374 int pipe
= intel_crtc
->pipe
;
2377 /* enable normal train */
2378 reg
= FDI_TX_CTL(pipe
);
2379 temp
= I915_READ(reg
);
2380 if (IS_IVYBRIDGE(dev
)) {
2381 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2382 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2384 temp
&= ~FDI_LINK_TRAIN_NONE
;
2385 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2387 I915_WRITE(reg
, temp
);
2389 reg
= FDI_RX_CTL(pipe
);
2390 temp
= I915_READ(reg
);
2391 if (HAS_PCH_CPT(dev
)) {
2392 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2393 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2395 temp
&= ~FDI_LINK_TRAIN_NONE
;
2396 temp
|= FDI_LINK_TRAIN_NONE
;
2398 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2400 /* wait one idle pattern time */
2404 /* IVB wants error correction enabled */
2405 if (IS_IVYBRIDGE(dev
))
2406 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
2407 FDI_FE_ERRC_ENABLE
);
2410 static bool pipe_has_enabled_pch(struct intel_crtc
*intel_crtc
)
2412 return intel_crtc
->base
.enabled
&& intel_crtc
->config
.has_pch_encoder
;
2415 static void ivb_modeset_global_resources(struct drm_device
*dev
)
2417 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2418 struct intel_crtc
*pipe_B_crtc
=
2419 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
2420 struct intel_crtc
*pipe_C_crtc
=
2421 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]);
2425 * When everything is off disable fdi C so that we could enable fdi B
2426 * with all lanes. Note that we don't care about enabled pipes without
2427 * an enabled pch encoder.
2429 if (!pipe_has_enabled_pch(pipe_B_crtc
) &&
2430 !pipe_has_enabled_pch(pipe_C_crtc
)) {
2431 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
2432 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
2434 temp
= I915_READ(SOUTH_CHICKEN1
);
2435 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
2436 DRM_DEBUG_KMS("disabling fdi C rx\n");
2437 I915_WRITE(SOUTH_CHICKEN1
, temp
);
2441 /* The FDI link training functions for ILK/Ibexpeak. */
2442 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
2444 struct drm_device
*dev
= crtc
->dev
;
2445 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2446 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2447 int pipe
= intel_crtc
->pipe
;
2448 int plane
= intel_crtc
->plane
;
2449 u32 reg
, temp
, tries
;
2451 /* FDI needs bits from pipe & plane first */
2452 assert_pipe_enabled(dev_priv
, pipe
);
2453 assert_plane_enabled(dev_priv
, plane
);
2455 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2457 reg
= FDI_RX_IMR(pipe
);
2458 temp
= I915_READ(reg
);
2459 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2460 temp
&= ~FDI_RX_BIT_LOCK
;
2461 I915_WRITE(reg
, temp
);
2465 /* enable CPU FDI TX and PCH FDI RX */
2466 reg
= FDI_TX_CTL(pipe
);
2467 temp
= I915_READ(reg
);
2468 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2469 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2470 temp
&= ~FDI_LINK_TRAIN_NONE
;
2471 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2472 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2474 reg
= FDI_RX_CTL(pipe
);
2475 temp
= I915_READ(reg
);
2476 temp
&= ~FDI_LINK_TRAIN_NONE
;
2477 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2478 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2483 /* Ironlake workaround, enable clock pointer after FDI enable*/
2484 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2485 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
2486 FDI_RX_PHASE_SYNC_POINTER_EN
);
2488 reg
= FDI_RX_IIR(pipe
);
2489 for (tries
= 0; tries
< 5; tries
++) {
2490 temp
= I915_READ(reg
);
2491 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2493 if ((temp
& FDI_RX_BIT_LOCK
)) {
2494 DRM_DEBUG_KMS("FDI train 1 done.\n");
2495 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2500 DRM_ERROR("FDI train 1 fail!\n");
2503 reg
= FDI_TX_CTL(pipe
);
2504 temp
= I915_READ(reg
);
2505 temp
&= ~FDI_LINK_TRAIN_NONE
;
2506 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2507 I915_WRITE(reg
, temp
);
2509 reg
= FDI_RX_CTL(pipe
);
2510 temp
= I915_READ(reg
);
2511 temp
&= ~FDI_LINK_TRAIN_NONE
;
2512 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2513 I915_WRITE(reg
, temp
);
2518 reg
= FDI_RX_IIR(pipe
);
2519 for (tries
= 0; tries
< 5; tries
++) {
2520 temp
= I915_READ(reg
);
2521 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2523 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2524 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2525 DRM_DEBUG_KMS("FDI train 2 done.\n");
2530 DRM_ERROR("FDI train 2 fail!\n");
2532 DRM_DEBUG_KMS("FDI train done\n");
2536 static const int snb_b_fdi_train_param
[] = {
2537 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
2538 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
2539 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
2540 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
2543 /* The FDI link training functions for SNB/Cougarpoint. */
2544 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
2546 struct drm_device
*dev
= crtc
->dev
;
2547 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2548 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2549 int pipe
= intel_crtc
->pipe
;
2550 u32 reg
, temp
, i
, retry
;
2552 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2554 reg
= FDI_RX_IMR(pipe
);
2555 temp
= I915_READ(reg
);
2556 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2557 temp
&= ~FDI_RX_BIT_LOCK
;
2558 I915_WRITE(reg
, temp
);
2563 /* enable CPU FDI TX and PCH FDI RX */
2564 reg
= FDI_TX_CTL(pipe
);
2565 temp
= I915_READ(reg
);
2566 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2567 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2568 temp
&= ~FDI_LINK_TRAIN_NONE
;
2569 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2570 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2572 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2573 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2575 I915_WRITE(FDI_RX_MISC(pipe
),
2576 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2578 reg
= FDI_RX_CTL(pipe
);
2579 temp
= I915_READ(reg
);
2580 if (HAS_PCH_CPT(dev
)) {
2581 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2582 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2584 temp
&= ~FDI_LINK_TRAIN_NONE
;
2585 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2587 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2592 for (i
= 0; i
< 4; i
++) {
2593 reg
= FDI_TX_CTL(pipe
);
2594 temp
= I915_READ(reg
);
2595 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2596 temp
|= snb_b_fdi_train_param
[i
];
2597 I915_WRITE(reg
, temp
);
2602 for (retry
= 0; retry
< 5; retry
++) {
2603 reg
= FDI_RX_IIR(pipe
);
2604 temp
= I915_READ(reg
);
2605 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2606 if (temp
& FDI_RX_BIT_LOCK
) {
2607 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2608 DRM_DEBUG_KMS("FDI train 1 done.\n");
2617 DRM_ERROR("FDI train 1 fail!\n");
2620 reg
= FDI_TX_CTL(pipe
);
2621 temp
= I915_READ(reg
);
2622 temp
&= ~FDI_LINK_TRAIN_NONE
;
2623 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2625 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2627 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2629 I915_WRITE(reg
, temp
);
2631 reg
= FDI_RX_CTL(pipe
);
2632 temp
= I915_READ(reg
);
2633 if (HAS_PCH_CPT(dev
)) {
2634 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2635 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2637 temp
&= ~FDI_LINK_TRAIN_NONE
;
2638 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2640 I915_WRITE(reg
, temp
);
2645 for (i
= 0; i
< 4; i
++) {
2646 reg
= FDI_TX_CTL(pipe
);
2647 temp
= I915_READ(reg
);
2648 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2649 temp
|= snb_b_fdi_train_param
[i
];
2650 I915_WRITE(reg
, temp
);
2655 for (retry
= 0; retry
< 5; retry
++) {
2656 reg
= FDI_RX_IIR(pipe
);
2657 temp
= I915_READ(reg
);
2658 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2659 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2660 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2661 DRM_DEBUG_KMS("FDI train 2 done.\n");
2670 DRM_ERROR("FDI train 2 fail!\n");
2672 DRM_DEBUG_KMS("FDI train done.\n");
2675 /* Manual link training for Ivy Bridge A0 parts */
2676 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
2678 struct drm_device
*dev
= crtc
->dev
;
2679 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2680 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2681 int pipe
= intel_crtc
->pipe
;
2682 u32 reg
, temp
, i
, j
;
2684 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2686 reg
= FDI_RX_IMR(pipe
);
2687 temp
= I915_READ(reg
);
2688 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2689 temp
&= ~FDI_RX_BIT_LOCK
;
2690 I915_WRITE(reg
, temp
);
2695 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2696 I915_READ(FDI_RX_IIR(pipe
)));
2698 /* Try each vswing and preemphasis setting twice before moving on */
2699 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
2700 /* disable first in case we need to retry */
2701 reg
= FDI_TX_CTL(pipe
);
2702 temp
= I915_READ(reg
);
2703 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
2704 temp
&= ~FDI_TX_ENABLE
;
2705 I915_WRITE(reg
, temp
);
2707 reg
= FDI_RX_CTL(pipe
);
2708 temp
= I915_READ(reg
);
2709 temp
&= ~FDI_LINK_TRAIN_AUTO
;
2710 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2711 temp
&= ~FDI_RX_ENABLE
;
2712 I915_WRITE(reg
, temp
);
2714 /* enable CPU FDI TX and PCH FDI RX */
2715 reg
= FDI_TX_CTL(pipe
);
2716 temp
= I915_READ(reg
);
2717 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2718 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2719 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
2720 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2721 temp
|= snb_b_fdi_train_param
[j
/2];
2722 temp
|= FDI_COMPOSITE_SYNC
;
2723 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2725 I915_WRITE(FDI_RX_MISC(pipe
),
2726 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2728 reg
= FDI_RX_CTL(pipe
);
2729 temp
= I915_READ(reg
);
2730 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2731 temp
|= FDI_COMPOSITE_SYNC
;
2732 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2735 udelay(1); /* should be 0.5us */
2737 for (i
= 0; i
< 4; i
++) {
2738 reg
= FDI_RX_IIR(pipe
);
2739 temp
= I915_READ(reg
);
2740 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2742 if (temp
& FDI_RX_BIT_LOCK
||
2743 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
2744 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2745 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2749 udelay(1); /* should be 0.5us */
2752 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
2757 reg
= FDI_TX_CTL(pipe
);
2758 temp
= I915_READ(reg
);
2759 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2760 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
2761 I915_WRITE(reg
, temp
);
2763 reg
= FDI_RX_CTL(pipe
);
2764 temp
= I915_READ(reg
);
2765 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2766 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2767 I915_WRITE(reg
, temp
);
2770 udelay(2); /* should be 1.5us */
2772 for (i
= 0; i
< 4; i
++) {
2773 reg
= FDI_RX_IIR(pipe
);
2774 temp
= I915_READ(reg
);
2775 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2777 if (temp
& FDI_RX_SYMBOL_LOCK
||
2778 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
2779 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2780 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2784 udelay(2); /* should be 1.5us */
2787 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
2791 DRM_DEBUG_KMS("FDI train done.\n");
2794 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
2796 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2797 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2798 int pipe
= intel_crtc
->pipe
;
2802 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2803 reg
= FDI_RX_CTL(pipe
);
2804 temp
= I915_READ(reg
);
2805 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
2806 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2807 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2808 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
2813 /* Switch from Rawclk to PCDclk */
2814 temp
= I915_READ(reg
);
2815 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
2820 /* Enable CPU FDI TX PLL, always on for Ironlake */
2821 reg
= FDI_TX_CTL(pipe
);
2822 temp
= I915_READ(reg
);
2823 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
2824 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
2831 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
2833 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2834 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2835 int pipe
= intel_crtc
->pipe
;
2838 /* Switch from PCDclk to Rawclk */
2839 reg
= FDI_RX_CTL(pipe
);
2840 temp
= I915_READ(reg
);
2841 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
2843 /* Disable CPU FDI TX PLL */
2844 reg
= FDI_TX_CTL(pipe
);
2845 temp
= I915_READ(reg
);
2846 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
2851 reg
= FDI_RX_CTL(pipe
);
2852 temp
= I915_READ(reg
);
2853 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
2855 /* Wait for the clocks to turn off. */
2860 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
2862 struct drm_device
*dev
= crtc
->dev
;
2863 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2864 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2865 int pipe
= intel_crtc
->pipe
;
2868 /* disable CPU FDI tx and PCH FDI rx */
2869 reg
= FDI_TX_CTL(pipe
);
2870 temp
= I915_READ(reg
);
2871 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
2874 reg
= FDI_RX_CTL(pipe
);
2875 temp
= I915_READ(reg
);
2876 temp
&= ~(0x7 << 16);
2877 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2878 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
2883 /* Ironlake workaround, disable clock pointer after downing FDI */
2884 if (HAS_PCH_IBX(dev
)) {
2885 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2888 /* still set train pattern 1 */
2889 reg
= FDI_TX_CTL(pipe
);
2890 temp
= I915_READ(reg
);
2891 temp
&= ~FDI_LINK_TRAIN_NONE
;
2892 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2893 I915_WRITE(reg
, temp
);
2895 reg
= FDI_RX_CTL(pipe
);
2896 temp
= I915_READ(reg
);
2897 if (HAS_PCH_CPT(dev
)) {
2898 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2899 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2901 temp
&= ~FDI_LINK_TRAIN_NONE
;
2902 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2904 /* BPC in FDI rx is consistent with that in PIPECONF */
2905 temp
&= ~(0x07 << 16);
2906 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2907 I915_WRITE(reg
, temp
);
2913 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
2915 struct drm_device
*dev
= crtc
->dev
;
2916 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2917 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2918 unsigned long flags
;
2921 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
2922 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
2925 spin_lock_irqsave(&dev
->event_lock
, flags
);
2926 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
2927 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2932 static void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
2934 struct drm_device
*dev
= crtc
->dev
;
2935 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2937 if (crtc
->fb
== NULL
)
2940 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
2942 wait_event(dev_priv
->pending_flip_queue
,
2943 !intel_crtc_has_pending_flip(crtc
));
2945 mutex_lock(&dev
->struct_mutex
);
2946 intel_finish_fb(crtc
->fb
);
2947 mutex_unlock(&dev
->struct_mutex
);
2950 /* Program iCLKIP clock to the desired frequency */
2951 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
2953 struct drm_device
*dev
= crtc
->dev
;
2954 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2955 int clock
= to_intel_crtc(crtc
)->config
.adjusted_mode
.crtc_clock
;
2956 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
2959 mutex_lock(&dev_priv
->dpio_lock
);
2961 /* It is necessary to ungate the pixclk gate prior to programming
2962 * the divisors, and gate it back when it is done.
2964 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
2966 /* Disable SSCCTL */
2967 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
2968 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
2972 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2973 if (clock
== 20000) {
2978 /* The iCLK virtual clock root frequency is in MHz,
2979 * but the adjusted_mode->crtc_clock in in KHz. To get the
2980 * divisors, it is necessary to divide one by another, so we
2981 * convert the virtual clock precision to KHz here for higher
2984 u32 iclk_virtual_root_freq
= 172800 * 1000;
2985 u32 iclk_pi_range
= 64;
2986 u32 desired_divisor
, msb_divisor_value
, pi_value
;
2988 desired_divisor
= (iclk_virtual_root_freq
/ clock
);
2989 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
2990 pi_value
= desired_divisor
% iclk_pi_range
;
2993 divsel
= msb_divisor_value
- 2;
2994 phaseinc
= pi_value
;
2997 /* This should not happen with any sane values */
2998 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
2999 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
3000 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
3001 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
3003 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3010 /* Program SSCDIVINTPHASE6 */
3011 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
3012 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
3013 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
3014 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
3015 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
3016 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
3017 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
3018 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
3020 /* Program SSCAUXDIV */
3021 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
3022 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3023 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
3024 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
3026 /* Enable modulator and associated divider */
3027 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
3028 temp
&= ~SBI_SSCCTL_DISABLE
;
3029 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
3031 /* Wait for initialization time */
3034 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
3036 mutex_unlock(&dev_priv
->dpio_lock
);
3039 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
3040 enum pipe pch_transcoder
)
3042 struct drm_device
*dev
= crtc
->base
.dev
;
3043 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3044 enum transcoder cpu_transcoder
= crtc
->config
.cpu_transcoder
;
3046 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
3047 I915_READ(HTOTAL(cpu_transcoder
)));
3048 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
3049 I915_READ(HBLANK(cpu_transcoder
)));
3050 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
3051 I915_READ(HSYNC(cpu_transcoder
)));
3053 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
3054 I915_READ(VTOTAL(cpu_transcoder
)));
3055 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
3056 I915_READ(VBLANK(cpu_transcoder
)));
3057 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
3058 I915_READ(VSYNC(cpu_transcoder
)));
3059 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
3060 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
3064 * Enable PCH resources required for PCH ports:
3066 * - FDI training & RX/TX
3067 * - update transcoder timings
3068 * - DP transcoding bits
3071 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
3073 struct drm_device
*dev
= crtc
->dev
;
3074 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3075 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3076 int pipe
= intel_crtc
->pipe
;
3079 assert_pch_transcoder_disabled(dev_priv
, pipe
);
3081 /* Write the TU size bits before fdi link training, so that error
3082 * detection works. */
3083 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
3084 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
3086 /* For PCH output, training FDI link */
3087 dev_priv
->display
.fdi_link_train(crtc
);
3089 /* We need to program the right clock selection before writing the pixel
3090 * mutliplier into the DPLL. */
3091 if (HAS_PCH_CPT(dev
)) {
3094 temp
= I915_READ(PCH_DPLL_SEL
);
3095 temp
|= TRANS_DPLL_ENABLE(pipe
);
3096 sel
= TRANS_DPLLB_SEL(pipe
);
3097 if (intel_crtc
->config
.shared_dpll
== DPLL_ID_PCH_PLL_B
)
3101 I915_WRITE(PCH_DPLL_SEL
, temp
);
3104 /* XXX: pch pll's can be enabled any time before we enable the PCH
3105 * transcoder, and we actually should do this to not upset any PCH
3106 * transcoder that already use the clock when we share it.
3108 * Note that enable_shared_dpll tries to do the right thing, but
3109 * get_shared_dpll unconditionally resets the pll - we need that to have
3110 * the right LVDS enable sequence. */
3111 ironlake_enable_shared_dpll(intel_crtc
);
3113 /* set transcoder timing, panel must allow it */
3114 assert_panel_unlocked(dev_priv
, pipe
);
3115 ironlake_pch_transcoder_set_timings(intel_crtc
, pipe
);
3117 intel_fdi_normal_train(crtc
);
3119 /* For PCH DP, enable TRANS_DP_CTL */
3120 if (HAS_PCH_CPT(dev
) &&
3121 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
3122 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3123 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
3124 reg
= TRANS_DP_CTL(pipe
);
3125 temp
= I915_READ(reg
);
3126 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
3127 TRANS_DP_SYNC_MASK
|
3129 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
3130 TRANS_DP_ENH_FRAMING
);
3131 temp
|= bpc
<< 9; /* same format but at 11:9 */
3133 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
3134 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
3135 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
3136 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
3138 switch (intel_trans_dp_port_sel(crtc
)) {
3140 temp
|= TRANS_DP_PORT_SEL_B
;
3143 temp
|= TRANS_DP_PORT_SEL_C
;
3146 temp
|= TRANS_DP_PORT_SEL_D
;
3152 I915_WRITE(reg
, temp
);
3155 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
3158 static void lpt_pch_enable(struct drm_crtc
*crtc
)
3160 struct drm_device
*dev
= crtc
->dev
;
3161 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3162 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3163 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
3165 assert_pch_transcoder_disabled(dev_priv
, TRANSCODER_A
);
3167 lpt_program_iclkip(crtc
);
3169 /* Set transcoder timing. */
3170 ironlake_pch_transcoder_set_timings(intel_crtc
, PIPE_A
);
3172 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
3175 static void intel_put_shared_dpll(struct intel_crtc
*crtc
)
3177 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3182 if (pll
->refcount
== 0) {
3183 WARN(1, "bad %s refcount\n", pll
->name
);
3187 if (--pll
->refcount
== 0) {
3189 WARN_ON(pll
->active
);
3192 crtc
->config
.shared_dpll
= DPLL_ID_PRIVATE
;
3195 static struct intel_shared_dpll
*intel_get_shared_dpll(struct intel_crtc
*crtc
)
3197 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
3198 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3199 enum intel_dpll_id i
;
3202 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3203 crtc
->base
.base
.id
, pll
->name
);
3204 intel_put_shared_dpll(crtc
);
3207 if (HAS_PCH_IBX(dev_priv
->dev
)) {
3208 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3209 i
= (enum intel_dpll_id
) crtc
->pipe
;
3210 pll
= &dev_priv
->shared_dplls
[i
];
3212 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3213 crtc
->base
.base
.id
, pll
->name
);
3218 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3219 pll
= &dev_priv
->shared_dplls
[i
];
3221 /* Only want to check enabled timings first */
3222 if (pll
->refcount
== 0)
3225 if (memcmp(&crtc
->config
.dpll_hw_state
, &pll
->hw_state
,
3226 sizeof(pll
->hw_state
)) == 0) {
3227 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3229 pll
->name
, pll
->refcount
, pll
->active
);
3235 /* Ok no matching timings, maybe there's a free one? */
3236 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3237 pll
= &dev_priv
->shared_dplls
[i
];
3238 if (pll
->refcount
== 0) {
3239 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3240 crtc
->base
.base
.id
, pll
->name
);
3248 crtc
->config
.shared_dpll
= i
;
3249 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll
->name
,
3250 pipe_name(crtc
->pipe
));
3252 if (pll
->active
== 0) {
3253 memcpy(&pll
->hw_state
, &crtc
->config
.dpll_hw_state
,
3254 sizeof(pll
->hw_state
));
3256 DRM_DEBUG_DRIVER("setting up %s\n", pll
->name
);
3258 assert_shared_dpll_disabled(dev_priv
, pll
);
3260 pll
->mode_set(dev_priv
, pll
);
3267 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
3269 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3270 int dslreg
= PIPEDSL(pipe
);
3273 temp
= I915_READ(dslreg
);
3275 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
3276 if (wait_for(I915_READ(dslreg
) != temp
, 5))
3277 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
3281 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
3283 struct drm_device
*dev
= crtc
->base
.dev
;
3284 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3285 int pipe
= crtc
->pipe
;
3287 if (crtc
->config
.pch_pfit
.enabled
) {
3288 /* Force use of hard-coded filter coefficients
3289 * as some pre-programmed values are broken,
3292 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
3293 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
3294 PF_PIPE_SEL_IVB(pipe
));
3296 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
3297 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
.pch_pfit
.pos
);
3298 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
.pch_pfit
.size
);
3302 static void intel_enable_planes(struct drm_crtc
*crtc
)
3304 struct drm_device
*dev
= crtc
->dev
;
3305 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
3306 struct intel_plane
*intel_plane
;
3308 list_for_each_entry(intel_plane
, &dev
->mode_config
.plane_list
, base
.head
)
3309 if (intel_plane
->pipe
== pipe
)
3310 intel_plane_restore(&intel_plane
->base
);
3313 static void intel_disable_planes(struct drm_crtc
*crtc
)
3315 struct drm_device
*dev
= crtc
->dev
;
3316 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
3317 struct intel_plane
*intel_plane
;
3319 list_for_each_entry(intel_plane
, &dev
->mode_config
.plane_list
, base
.head
)
3320 if (intel_plane
->pipe
== pipe
)
3321 intel_plane_disable(&intel_plane
->base
);
3324 static void hsw_enable_ips(struct intel_crtc
*crtc
)
3326 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
3328 if (!crtc
->config
.ips_enabled
)
3331 /* We can only enable IPS after we enable a plane and wait for a vblank.
3332 * We guarantee that the plane is enabled by calling intel_enable_ips
3333 * only after intel_enable_plane. And intel_enable_plane already waits
3334 * for a vblank, so all we need to do here is to enable the IPS bit. */
3335 assert_plane_enabled(dev_priv
, crtc
->plane
);
3336 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
3339 static void hsw_disable_ips(struct intel_crtc
*crtc
)
3341 struct drm_device
*dev
= crtc
->base
.dev
;
3342 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3344 if (!crtc
->config
.ips_enabled
)
3347 assert_plane_enabled(dev_priv
, crtc
->plane
);
3348 I915_WRITE(IPS_CTL
, 0);
3349 POSTING_READ(IPS_CTL
);
3351 /* We need to wait for a vblank before we can disable the plane. */
3352 intel_wait_for_vblank(dev
, crtc
->pipe
);
3355 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3356 static void intel_crtc_load_lut(struct drm_crtc
*crtc
)
3358 struct drm_device
*dev
= crtc
->dev
;
3359 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3360 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3361 enum pipe pipe
= intel_crtc
->pipe
;
3362 int palreg
= PALETTE(pipe
);
3364 bool reenable_ips
= false;
3366 /* The clocks have to be on to load the palette. */
3367 if (!crtc
->enabled
|| !intel_crtc
->active
)
3370 if (!HAS_PCH_SPLIT(dev_priv
->dev
)) {
3371 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
))
3372 assert_dsi_pll_enabled(dev_priv
);
3374 assert_pll_enabled(dev_priv
, pipe
);
3377 /* use legacy palette for Ironlake */
3378 if (HAS_PCH_SPLIT(dev
))
3379 palreg
= LGC_PALETTE(pipe
);
3381 /* Workaround : Do not read or write the pipe palette/gamma data while
3382 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3384 if (intel_crtc
->config
.ips_enabled
&&
3385 ((I915_READ(GAMMA_MODE(pipe
)) & GAMMA_MODE_MODE_MASK
) ==
3386 GAMMA_MODE_MODE_SPLIT
)) {
3387 hsw_disable_ips(intel_crtc
);
3388 reenable_ips
= true;
3391 for (i
= 0; i
< 256; i
++) {
3392 I915_WRITE(palreg
+ 4 * i
,
3393 (intel_crtc
->lut_r
[i
] << 16) |
3394 (intel_crtc
->lut_g
[i
] << 8) |
3395 intel_crtc
->lut_b
[i
]);
3399 hsw_enable_ips(intel_crtc
);
3402 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
3404 struct drm_device
*dev
= crtc
->dev
;
3405 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3406 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3407 struct intel_encoder
*encoder
;
3408 int pipe
= intel_crtc
->pipe
;
3409 int plane
= intel_crtc
->plane
;
3411 WARN_ON(!crtc
->enabled
);
3413 if (intel_crtc
->active
)
3416 intel_crtc
->active
= true;
3418 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
3419 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
3421 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3422 if (encoder
->pre_enable
)
3423 encoder
->pre_enable(encoder
);
3425 if (intel_crtc
->config
.has_pch_encoder
) {
3426 /* Note: FDI PLL enabling _must_ be done before we enable the
3427 * cpu pipes, hence this is separate from all the other fdi/pch
3429 ironlake_fdi_pll_enable(intel_crtc
);
3431 assert_fdi_tx_disabled(dev_priv
, pipe
);
3432 assert_fdi_rx_disabled(dev_priv
, pipe
);
3435 ironlake_pfit_enable(intel_crtc
);
3438 * On ILK+ LUT must be loaded before the pipe is running but with
3441 intel_crtc_load_lut(crtc
);
3443 intel_update_watermarks(crtc
);
3444 intel_enable_pipe(dev_priv
, pipe
,
3445 intel_crtc
->config
.has_pch_encoder
, false);
3446 intel_enable_plane(dev_priv
, plane
, pipe
);
3447 intel_enable_planes(crtc
);
3448 intel_crtc_update_cursor(crtc
, true);
3450 if (intel_crtc
->config
.has_pch_encoder
)
3451 ironlake_pch_enable(crtc
);
3453 mutex_lock(&dev
->struct_mutex
);
3454 intel_update_fbc(dev
);
3455 mutex_unlock(&dev
->struct_mutex
);
3457 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3458 encoder
->enable(encoder
);
3460 if (HAS_PCH_CPT(dev
))
3461 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
3464 * There seems to be a race in PCH platform hw (at least on some
3465 * outputs) where an enabled pipe still completes any pageflip right
3466 * away (as if the pipe is off) instead of waiting for vblank. As soon
3467 * as the first vblank happend, everything works as expected. Hence just
3468 * wait for one vblank before returning to avoid strange things
3471 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3474 /* IPS only exists on ULT machines and is tied to pipe A. */
3475 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
3477 return HAS_IPS(crtc
->base
.dev
) && crtc
->pipe
== PIPE_A
;
3480 static void haswell_crtc_enable_planes(struct drm_crtc
*crtc
)
3482 struct drm_device
*dev
= crtc
->dev
;
3483 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3484 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3485 int pipe
= intel_crtc
->pipe
;
3486 int plane
= intel_crtc
->plane
;
3488 intel_enable_plane(dev_priv
, plane
, pipe
);
3489 intel_enable_planes(crtc
);
3490 intel_crtc_update_cursor(crtc
, true);
3492 hsw_enable_ips(intel_crtc
);
3494 mutex_lock(&dev
->struct_mutex
);
3495 intel_update_fbc(dev
);
3496 mutex_unlock(&dev
->struct_mutex
);
3499 static void haswell_crtc_disable_planes(struct drm_crtc
*crtc
)
3501 struct drm_device
*dev
= crtc
->dev
;
3502 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3503 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3504 int pipe
= intel_crtc
->pipe
;
3505 int plane
= intel_crtc
->plane
;
3507 intel_crtc_wait_for_pending_flips(crtc
);
3508 drm_vblank_off(dev
, pipe
);
3510 /* FBC must be disabled before disabling the plane on HSW. */
3511 if (dev_priv
->fbc
.plane
== plane
)
3512 intel_disable_fbc(dev
);
3514 hsw_disable_ips(intel_crtc
);
3516 intel_crtc_update_cursor(crtc
, false);
3517 intel_disable_planes(crtc
);
3518 intel_disable_plane(dev_priv
, plane
, pipe
);
3522 * This implements the workaround described in the "notes" section of the mode
3523 * set sequence documentation. When going from no pipes or single pipe to
3524 * multiple pipes, and planes are enabled after the pipe, we need to wait at
3525 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3527 static void haswell_mode_set_planes_workaround(struct intel_crtc
*crtc
)
3529 struct drm_device
*dev
= crtc
->base
.dev
;
3530 struct intel_crtc
*crtc_it
, *other_active_crtc
= NULL
;
3532 /* We want to get the other_active_crtc only if there's only 1 other
3534 list_for_each_entry(crtc_it
, &dev
->mode_config
.crtc_list
, base
.head
) {
3535 if (!crtc_it
->active
|| crtc_it
== crtc
)
3538 if (other_active_crtc
)
3541 other_active_crtc
= crtc_it
;
3543 if (!other_active_crtc
)
3546 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
3547 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
3550 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
3552 struct drm_device
*dev
= crtc
->dev
;
3553 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3554 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3555 struct intel_encoder
*encoder
;
3556 int pipe
= intel_crtc
->pipe
;
3558 WARN_ON(!crtc
->enabled
);
3560 if (intel_crtc
->active
)
3563 intel_crtc
->active
= true;
3565 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
3566 if (intel_crtc
->config
.has_pch_encoder
)
3567 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
3569 if (intel_crtc
->config
.has_pch_encoder
)
3570 dev_priv
->display
.fdi_link_train(crtc
);
3572 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3573 if (encoder
->pre_enable
)
3574 encoder
->pre_enable(encoder
);
3576 intel_ddi_enable_pipe_clock(intel_crtc
);
3578 ironlake_pfit_enable(intel_crtc
);
3581 * On ILK+ LUT must be loaded before the pipe is running but with
3584 intel_crtc_load_lut(crtc
);
3586 intel_ddi_set_pipe_settings(crtc
);
3587 intel_ddi_enable_transcoder_func(crtc
);
3589 intel_update_watermarks(crtc
);
3590 intel_enable_pipe(dev_priv
, pipe
,
3591 intel_crtc
->config
.has_pch_encoder
, false);
3593 if (intel_crtc
->config
.has_pch_encoder
)
3594 lpt_pch_enable(crtc
);
3596 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
3597 encoder
->enable(encoder
);
3598 intel_opregion_notify_encoder(encoder
, true);
3601 /* If we change the relative order between pipe/planes enabling, we need
3602 * to change the workaround. */
3603 haswell_mode_set_planes_workaround(intel_crtc
);
3604 haswell_crtc_enable_planes(crtc
);
3607 * There seems to be a race in PCH platform hw (at least on some
3608 * outputs) where an enabled pipe still completes any pageflip right
3609 * away (as if the pipe is off) instead of waiting for vblank. As soon
3610 * as the first vblank happend, everything works as expected. Hence just
3611 * wait for one vblank before returning to avoid strange things
3614 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3617 static void ironlake_pfit_disable(struct intel_crtc
*crtc
)
3619 struct drm_device
*dev
= crtc
->base
.dev
;
3620 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3621 int pipe
= crtc
->pipe
;
3623 /* To avoid upsetting the power well on haswell only disable the pfit if
3624 * it's in use. The hw state code will make sure we get this right. */
3625 if (crtc
->config
.pch_pfit
.enabled
) {
3626 I915_WRITE(PF_CTL(pipe
), 0);
3627 I915_WRITE(PF_WIN_POS(pipe
), 0);
3628 I915_WRITE(PF_WIN_SZ(pipe
), 0);
3632 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
3634 struct drm_device
*dev
= crtc
->dev
;
3635 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3636 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3637 struct intel_encoder
*encoder
;
3638 int pipe
= intel_crtc
->pipe
;
3639 int plane
= intel_crtc
->plane
;
3643 if (!intel_crtc
->active
)
3646 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3647 encoder
->disable(encoder
);
3649 intel_crtc_wait_for_pending_flips(crtc
);
3650 drm_vblank_off(dev
, pipe
);
3652 if (dev_priv
->fbc
.plane
== plane
)
3653 intel_disable_fbc(dev
);
3655 intel_crtc_update_cursor(crtc
, false);
3656 intel_disable_planes(crtc
);
3657 intel_disable_plane(dev_priv
, plane
, pipe
);
3659 if (intel_crtc
->config
.has_pch_encoder
)
3660 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, false);
3662 intel_disable_pipe(dev_priv
, pipe
);
3664 ironlake_pfit_disable(intel_crtc
);
3666 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3667 if (encoder
->post_disable
)
3668 encoder
->post_disable(encoder
);
3670 if (intel_crtc
->config
.has_pch_encoder
) {
3671 ironlake_fdi_disable(crtc
);
3673 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
3674 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
3676 if (HAS_PCH_CPT(dev
)) {
3677 /* disable TRANS_DP_CTL */
3678 reg
= TRANS_DP_CTL(pipe
);
3679 temp
= I915_READ(reg
);
3680 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
3681 TRANS_DP_PORT_SEL_MASK
);
3682 temp
|= TRANS_DP_PORT_SEL_NONE
;
3683 I915_WRITE(reg
, temp
);
3685 /* disable DPLL_SEL */
3686 temp
= I915_READ(PCH_DPLL_SEL
);
3687 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
3688 I915_WRITE(PCH_DPLL_SEL
, temp
);
3691 /* disable PCH DPLL */
3692 intel_disable_shared_dpll(intel_crtc
);
3694 ironlake_fdi_pll_disable(intel_crtc
);
3697 intel_crtc
->active
= false;
3698 intel_update_watermarks(crtc
);
3700 mutex_lock(&dev
->struct_mutex
);
3701 intel_update_fbc(dev
);
3702 mutex_unlock(&dev
->struct_mutex
);
3705 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
3707 struct drm_device
*dev
= crtc
->dev
;
3708 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3709 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3710 struct intel_encoder
*encoder
;
3711 int pipe
= intel_crtc
->pipe
;
3712 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
3714 if (!intel_crtc
->active
)
3717 haswell_crtc_disable_planes(crtc
);
3719 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
3720 intel_opregion_notify_encoder(encoder
, false);
3721 encoder
->disable(encoder
);
3724 if (intel_crtc
->config
.has_pch_encoder
)
3725 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, false);
3726 intel_disable_pipe(dev_priv
, pipe
);
3728 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
3730 ironlake_pfit_disable(intel_crtc
);
3732 intel_ddi_disable_pipe_clock(intel_crtc
);
3734 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3735 if (encoder
->post_disable
)
3736 encoder
->post_disable(encoder
);
3738 if (intel_crtc
->config
.has_pch_encoder
) {
3739 lpt_disable_pch_transcoder(dev_priv
);
3740 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
3741 intel_ddi_fdi_disable(crtc
);
3744 intel_crtc
->active
= false;
3745 intel_update_watermarks(crtc
);
3747 mutex_lock(&dev
->struct_mutex
);
3748 intel_update_fbc(dev
);
3749 mutex_unlock(&dev
->struct_mutex
);
3752 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
3754 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3755 intel_put_shared_dpll(intel_crtc
);
3758 static void haswell_crtc_off(struct drm_crtc
*crtc
)
3760 intel_ddi_put_crtc_pll(crtc
);
3763 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
3765 if (!enable
&& intel_crtc
->overlay
) {
3766 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3767 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3769 mutex_lock(&dev
->struct_mutex
);
3770 dev_priv
->mm
.interruptible
= false;
3771 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
3772 dev_priv
->mm
.interruptible
= true;
3773 mutex_unlock(&dev
->struct_mutex
);
3776 /* Let userspace switch the overlay on again. In most cases userspace
3777 * has to recompute where to put it anyway.
3782 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3783 * cursor plane briefly if not already running after enabling the display
3785 * This workaround avoids occasional blank screens when self refresh is
3789 g4x_fixup_plane(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
3791 u32 cntl
= I915_READ(CURCNTR(pipe
));
3793 if ((cntl
& CURSOR_MODE
) == 0) {
3794 u32 fw_bcl_self
= I915_READ(FW_BLC_SELF
);
3796 I915_WRITE(FW_BLC_SELF
, fw_bcl_self
& ~FW_BLC_SELF_EN
);
3797 I915_WRITE(CURCNTR(pipe
), CURSOR_MODE_64_ARGB_AX
);
3798 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
3799 I915_WRITE(CURCNTR(pipe
), cntl
);
3800 I915_WRITE(CURBASE(pipe
), I915_READ(CURBASE(pipe
)));
3801 I915_WRITE(FW_BLC_SELF
, fw_bcl_self
);
3805 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
3807 struct drm_device
*dev
= crtc
->base
.dev
;
3808 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3809 struct intel_crtc_config
*pipe_config
= &crtc
->config
;
3811 if (!crtc
->config
.gmch_pfit
.control
)
3815 * The panel fitter should only be adjusted whilst the pipe is disabled,
3816 * according to register description and PRM.
3818 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
3819 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
3821 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
3822 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
3824 /* Border color in case we don't scale up to the full screen. Black by
3825 * default, change to something else for debugging. */
3826 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
3829 static void valleyview_crtc_enable(struct drm_crtc
*crtc
)
3831 struct drm_device
*dev
= crtc
->dev
;
3832 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3833 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3834 struct intel_encoder
*encoder
;
3835 int pipe
= intel_crtc
->pipe
;
3836 int plane
= intel_crtc
->plane
;
3839 WARN_ON(!crtc
->enabled
);
3841 if (intel_crtc
->active
)
3844 intel_crtc
->active
= true;
3846 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3847 if (encoder
->pre_pll_enable
)
3848 encoder
->pre_pll_enable(encoder
);
3850 is_dsi
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
);
3853 vlv_enable_pll(intel_crtc
);
3855 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3856 if (encoder
->pre_enable
)
3857 encoder
->pre_enable(encoder
);
3859 i9xx_pfit_enable(intel_crtc
);
3861 intel_crtc_load_lut(crtc
);
3863 intel_update_watermarks(crtc
);
3864 intel_enable_pipe(dev_priv
, pipe
, false, is_dsi
);
3865 intel_enable_plane(dev_priv
, plane
, pipe
);
3866 intel_enable_planes(crtc
);
3867 intel_crtc_update_cursor(crtc
, true);
3869 intel_update_fbc(dev
);
3871 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3872 encoder
->enable(encoder
);
3875 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
3877 struct drm_device
*dev
= crtc
->dev
;
3878 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3879 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3880 struct intel_encoder
*encoder
;
3881 int pipe
= intel_crtc
->pipe
;
3882 int plane
= intel_crtc
->plane
;
3884 WARN_ON(!crtc
->enabled
);
3886 if (intel_crtc
->active
)
3889 intel_crtc
->active
= true;
3891 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3892 if (encoder
->pre_enable
)
3893 encoder
->pre_enable(encoder
);
3895 i9xx_enable_pll(intel_crtc
);
3897 i9xx_pfit_enable(intel_crtc
);
3899 intel_crtc_load_lut(crtc
);
3901 intel_update_watermarks(crtc
);
3902 intel_enable_pipe(dev_priv
, pipe
, false, false);
3903 intel_enable_plane(dev_priv
, plane
, pipe
);
3904 intel_enable_planes(crtc
);
3905 /* The fixup needs to happen before cursor is enabled */
3907 g4x_fixup_plane(dev_priv
, pipe
);
3908 intel_crtc_update_cursor(crtc
, true);
3910 /* Give the overlay scaler a chance to enable if it's on this pipe */
3911 intel_crtc_dpms_overlay(intel_crtc
, true);
3913 intel_update_fbc(dev
);
3915 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3916 encoder
->enable(encoder
);
3919 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
3921 struct drm_device
*dev
= crtc
->base
.dev
;
3922 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3924 if (!crtc
->config
.gmch_pfit
.control
)
3927 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
3929 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3930 I915_READ(PFIT_CONTROL
));
3931 I915_WRITE(PFIT_CONTROL
, 0);
3934 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
3936 struct drm_device
*dev
= crtc
->dev
;
3937 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3938 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3939 struct intel_encoder
*encoder
;
3940 int pipe
= intel_crtc
->pipe
;
3941 int plane
= intel_crtc
->plane
;
3943 if (!intel_crtc
->active
)
3946 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3947 encoder
->disable(encoder
);
3949 /* Give the overlay scaler a chance to disable if it's on this pipe */
3950 intel_crtc_wait_for_pending_flips(crtc
);
3951 drm_vblank_off(dev
, pipe
);
3953 if (dev_priv
->fbc
.plane
== plane
)
3954 intel_disable_fbc(dev
);
3956 intel_crtc_dpms_overlay(intel_crtc
, false);
3957 intel_crtc_update_cursor(crtc
, false);
3958 intel_disable_planes(crtc
);
3959 intel_disable_plane(dev_priv
, plane
, pipe
);
3961 intel_disable_pipe(dev_priv
, pipe
);
3963 i9xx_pfit_disable(intel_crtc
);
3965 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3966 if (encoder
->post_disable
)
3967 encoder
->post_disable(encoder
);
3969 if (IS_VALLEYVIEW(dev
) && !intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
))
3970 vlv_disable_pll(dev_priv
, pipe
);
3971 else if (!IS_VALLEYVIEW(dev
))
3972 i9xx_disable_pll(dev_priv
, pipe
);
3974 intel_crtc
->active
= false;
3975 intel_update_watermarks(crtc
);
3977 intel_update_fbc(dev
);
3980 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
3984 static void intel_crtc_update_sarea(struct drm_crtc
*crtc
,
3987 struct drm_device
*dev
= crtc
->dev
;
3988 struct drm_i915_master_private
*master_priv
;
3989 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3990 int pipe
= intel_crtc
->pipe
;
3992 if (!dev
->primary
->master
)
3995 master_priv
= dev
->primary
->master
->driver_priv
;
3996 if (!master_priv
->sarea_priv
)
4001 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
4002 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
4005 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
4006 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
4009 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe
));
4015 * Sets the power management mode of the pipe and plane.
4017 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
4019 struct drm_device
*dev
= crtc
->dev
;
4020 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4021 struct intel_encoder
*intel_encoder
;
4022 bool enable
= false;
4024 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
4025 enable
|= intel_encoder
->connectors_active
;
4028 dev_priv
->display
.crtc_enable(crtc
);
4030 dev_priv
->display
.crtc_disable(crtc
);
4032 intel_crtc_update_sarea(crtc
, enable
);
4035 static void intel_crtc_disable(struct drm_crtc
*crtc
)
4037 struct drm_device
*dev
= crtc
->dev
;
4038 struct drm_connector
*connector
;
4039 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4040 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4042 /* crtc should still be enabled when we disable it. */
4043 WARN_ON(!crtc
->enabled
);
4045 dev_priv
->display
.crtc_disable(crtc
);
4046 intel_crtc
->eld_vld
= false;
4047 intel_crtc_update_sarea(crtc
, false);
4048 dev_priv
->display
.off(crtc
);
4050 assert_plane_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->plane
);
4051 assert_cursor_disabled(dev_priv
, to_intel_crtc(crtc
)->pipe
);
4052 assert_pipe_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->pipe
);
4055 mutex_lock(&dev
->struct_mutex
);
4056 intel_unpin_fb_obj(to_intel_framebuffer(crtc
->fb
)->obj
);
4057 mutex_unlock(&dev
->struct_mutex
);
4061 /* Update computed state. */
4062 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
4063 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
4066 if (connector
->encoder
->crtc
!= crtc
)
4069 connector
->dpms
= DRM_MODE_DPMS_OFF
;
4070 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
4074 void intel_encoder_destroy(struct drm_encoder
*encoder
)
4076 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
4078 drm_encoder_cleanup(encoder
);
4079 kfree(intel_encoder
);
4082 /* Simple dpms helper for encoders with just one connector, no cloning and only
4083 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4084 * state of the entire output pipe. */
4085 static void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
4087 if (mode
== DRM_MODE_DPMS_ON
) {
4088 encoder
->connectors_active
= true;
4090 intel_crtc_update_dpms(encoder
->base
.crtc
);
4092 encoder
->connectors_active
= false;
4094 intel_crtc_update_dpms(encoder
->base
.crtc
);
4098 /* Cross check the actual hw state with our own modeset state tracking (and it's
4099 * internal consistency). */
4100 static void intel_connector_check_state(struct intel_connector
*connector
)
4102 if (connector
->get_hw_state(connector
)) {
4103 struct intel_encoder
*encoder
= connector
->encoder
;
4104 struct drm_crtc
*crtc
;
4105 bool encoder_enabled
;
4108 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4109 connector
->base
.base
.id
,
4110 drm_get_connector_name(&connector
->base
));
4112 WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
4113 "wrong connector dpms state\n");
4114 WARN(connector
->base
.encoder
!= &encoder
->base
,
4115 "active connector not linked to encoder\n");
4116 WARN(!encoder
->connectors_active
,
4117 "encoder->connectors_active not set\n");
4119 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
4120 WARN(!encoder_enabled
, "encoder not enabled\n");
4121 if (WARN_ON(!encoder
->base
.crtc
))
4124 crtc
= encoder
->base
.crtc
;
4126 WARN(!crtc
->enabled
, "crtc not enabled\n");
4127 WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
4128 WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
4129 "encoder active on the wrong pipe\n");
4133 /* Even simpler default implementation, if there's really no special case to
4135 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
4137 struct intel_encoder
*encoder
= intel_attached_encoder(connector
);
4139 /* All the simple cases only support two dpms states. */
4140 if (mode
!= DRM_MODE_DPMS_ON
)
4141 mode
= DRM_MODE_DPMS_OFF
;
4143 if (mode
== connector
->dpms
)
4146 connector
->dpms
= mode
;
4148 /* Only need to change hw state when actually enabled */
4149 if (encoder
->base
.crtc
)
4150 intel_encoder_dpms(encoder
, mode
);
4152 WARN_ON(encoder
->connectors_active
!= false);
4154 intel_modeset_check_state(connector
->dev
);
4157 /* Simple connector->get_hw_state implementation for encoders that support only
4158 * one connector and no cloning and hence the encoder state determines the state
4159 * of the connector. */
4160 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
4163 struct intel_encoder
*encoder
= connector
->encoder
;
4165 return encoder
->get_hw_state(encoder
, &pipe
);
4168 static bool ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
4169 struct intel_crtc_config
*pipe_config
)
4171 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4172 struct intel_crtc
*pipe_B_crtc
=
4173 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
4175 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4176 pipe_name(pipe
), pipe_config
->fdi_lanes
);
4177 if (pipe_config
->fdi_lanes
> 4) {
4178 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4179 pipe_name(pipe
), pipe_config
->fdi_lanes
);
4183 if (IS_HASWELL(dev
)) {
4184 if (pipe_config
->fdi_lanes
> 2) {
4185 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4186 pipe_config
->fdi_lanes
);
4193 if (INTEL_INFO(dev
)->num_pipes
== 2)
4196 /* Ivybridge 3 pipe is really complicated */
4201 if (dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]->enabled
&&
4202 pipe_config
->fdi_lanes
> 2) {
4203 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4204 pipe_name(pipe
), pipe_config
->fdi_lanes
);
4209 if (!pipe_has_enabled_pch(pipe_B_crtc
) ||
4210 pipe_B_crtc
->config
.fdi_lanes
<= 2) {
4211 if (pipe_config
->fdi_lanes
> 2) {
4212 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4213 pipe_name(pipe
), pipe_config
->fdi_lanes
);
4217 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4227 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
4228 struct intel_crtc_config
*pipe_config
)
4230 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4231 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
4232 int lane
, link_bw
, fdi_dotclock
;
4233 bool setup_ok
, needs_recompute
= false;
4236 /* FDI is a binary signal running at ~2.7GHz, encoding
4237 * each output octet as 10 bits. The actual frequency
4238 * is stored as a divider into a 100MHz clock, and the
4239 * mode pixel clock is stored in units of 1KHz.
4240 * Hence the bw of each lane in terms of the mode signal
4243 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
4245 fdi_dotclock
= adjusted_mode
->crtc_clock
;
4247 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
4248 pipe_config
->pipe_bpp
);
4250 pipe_config
->fdi_lanes
= lane
;
4252 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
4253 link_bw
, &pipe_config
->fdi_m_n
);
4255 setup_ok
= ironlake_check_fdi_lanes(intel_crtc
->base
.dev
,
4256 intel_crtc
->pipe
, pipe_config
);
4257 if (!setup_ok
&& pipe_config
->pipe_bpp
> 6*3) {
4258 pipe_config
->pipe_bpp
-= 2*3;
4259 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4260 pipe_config
->pipe_bpp
);
4261 needs_recompute
= true;
4262 pipe_config
->bw_constrained
= true;
4267 if (needs_recompute
)
4270 return setup_ok
? 0 : -EINVAL
;
4273 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
4274 struct intel_crtc_config
*pipe_config
)
4276 pipe_config
->ips_enabled
= i915_enable_ips
&&
4277 hsw_crtc_supports_ips(crtc
) &&
4278 pipe_config
->pipe_bpp
<= 24;
4281 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
4282 struct intel_crtc_config
*pipe_config
)
4284 struct drm_device
*dev
= crtc
->base
.dev
;
4285 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
4287 /* FIXME should check pixel clock limits on all platforms */
4288 if (INTEL_INFO(dev
)->gen
< 4) {
4289 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4291 dev_priv
->display
.get_display_clock_speed(dev
);
4294 * Enable pixel doubling when the dot clock
4295 * is > 90% of the (display) core speed.
4297 * GDG double wide on either pipe,
4298 * otherwise pipe A only.
4300 if ((crtc
->pipe
== PIPE_A
|| IS_I915G(dev
)) &&
4301 adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10) {
4303 pipe_config
->double_wide
= true;
4306 if (adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10)
4311 * Pipe horizontal size must be even in:
4313 * - LVDS dual channel mode
4314 * - Double wide pipe
4316 if ((intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4317 intel_is_dual_link_lvds(dev
)) || pipe_config
->double_wide
)
4318 pipe_config
->pipe_src_w
&= ~1;
4320 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4321 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4323 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
4324 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
4327 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) && pipe_config
->pipe_bpp
> 10*3) {
4328 pipe_config
->pipe_bpp
= 10*3; /* 12bpc is gen5+ */
4329 } else if (INTEL_INFO(dev
)->gen
<= 4 && pipe_config
->pipe_bpp
> 8*3) {
4330 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4332 pipe_config
->pipe_bpp
= 8*3;
4336 hsw_compute_ips_config(crtc
, pipe_config
);
4338 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4339 * clock survives for now. */
4340 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
4341 pipe_config
->shared_dpll
= crtc
->config
.shared_dpll
;
4343 if (pipe_config
->has_pch_encoder
)
4344 return ironlake_fdi_compute_config(crtc
, pipe_config
);
4349 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
4351 return 400000; /* FIXME */
4354 static int i945_get_display_clock_speed(struct drm_device
*dev
)
4359 static int i915_get_display_clock_speed(struct drm_device
*dev
)
4364 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
4369 static int pnv_get_display_clock_speed(struct drm_device
*dev
)
4373 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
4375 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
4376 case GC_DISPLAY_CLOCK_267_MHZ_PNV
:
4378 case GC_DISPLAY_CLOCK_333_MHZ_PNV
:
4380 case GC_DISPLAY_CLOCK_444_MHZ_PNV
:
4382 case GC_DISPLAY_CLOCK_200_MHZ_PNV
:
4385 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc
);
4386 case GC_DISPLAY_CLOCK_133_MHZ_PNV
:
4388 case GC_DISPLAY_CLOCK_167_MHZ_PNV
:
4393 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
4397 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
4399 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
4402 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
4403 case GC_DISPLAY_CLOCK_333_MHZ
:
4406 case GC_DISPLAY_CLOCK_190_200_MHZ
:
4412 static int i865_get_display_clock_speed(struct drm_device
*dev
)
4417 static int i855_get_display_clock_speed(struct drm_device
*dev
)
4420 /* Assume that the hardware is in the high speed state. This
4421 * should be the default.
4423 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
4424 case GC_CLOCK_133_200
:
4425 case GC_CLOCK_100_200
:
4427 case GC_CLOCK_166_250
:
4429 case GC_CLOCK_100_133
:
4433 /* Shouldn't happen */
4437 static int i830_get_display_clock_speed(struct drm_device
*dev
)
4443 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
4445 while (*num
> DATA_LINK_M_N_MASK
||
4446 *den
> DATA_LINK_M_N_MASK
) {
4452 static void compute_m_n(unsigned int m
, unsigned int n
,
4453 uint32_t *ret_m
, uint32_t *ret_n
)
4455 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
4456 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
4457 intel_reduce_m_n_ratio(ret_m
, ret_n
);
4461 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
4462 int pixel_clock
, int link_clock
,
4463 struct intel_link_m_n
*m_n
)
4467 compute_m_n(bits_per_pixel
* pixel_clock
,
4468 link_clock
* nlanes
* 8,
4469 &m_n
->gmch_m
, &m_n
->gmch_n
);
4471 compute_m_n(pixel_clock
, link_clock
,
4472 &m_n
->link_m
, &m_n
->link_n
);
4475 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
4477 if (i915_panel_use_ssc
>= 0)
4478 return i915_panel_use_ssc
!= 0;
4479 return dev_priv
->vbt
.lvds_use_ssc
4480 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
4483 static int i9xx_get_refclk(struct drm_crtc
*crtc
, int num_connectors
)
4485 struct drm_device
*dev
= crtc
->dev
;
4486 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4489 if (IS_VALLEYVIEW(dev
)) {
4491 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4492 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
4493 refclk
= dev_priv
->vbt
.lvds_ssc_freq
* 1000;
4494 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4496 } else if (!IS_GEN2(dev
)) {
4505 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
4507 return (1 << dpll
->n
) << 16 | dpll
->m2
;
4510 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
4512 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
4515 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
4516 intel_clock_t
*reduced_clock
)
4518 struct drm_device
*dev
= crtc
->base
.dev
;
4519 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4520 int pipe
= crtc
->pipe
;
4523 if (IS_PINEVIEW(dev
)) {
4524 fp
= pnv_dpll_compute_fp(&crtc
->config
.dpll
);
4526 fp2
= pnv_dpll_compute_fp(reduced_clock
);
4528 fp
= i9xx_dpll_compute_fp(&crtc
->config
.dpll
);
4530 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
4533 I915_WRITE(FP0(pipe
), fp
);
4534 crtc
->config
.dpll_hw_state
.fp0
= fp
;
4536 crtc
->lowfreq_avail
= false;
4537 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4538 reduced_clock
&& i915_powersave
) {
4539 I915_WRITE(FP1(pipe
), fp2
);
4540 crtc
->config
.dpll_hw_state
.fp1
= fp2
;
4541 crtc
->lowfreq_avail
= true;
4543 I915_WRITE(FP1(pipe
), fp
);
4544 crtc
->config
.dpll_hw_state
.fp1
= fp
;
4548 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
4554 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4555 * and set it to a reasonable value instead.
4557 reg_val
= vlv_dpio_read(dev_priv
, pipe
, DPIO_IREF(1));
4558 reg_val
&= 0xffffff00;
4559 reg_val
|= 0x00000030;
4560 vlv_dpio_write(dev_priv
, pipe
, DPIO_IREF(1), reg_val
);
4562 reg_val
= vlv_dpio_read(dev_priv
, pipe
, DPIO_CALIBRATION
);
4563 reg_val
&= 0x8cffffff;
4564 reg_val
= 0x8c000000;
4565 vlv_dpio_write(dev_priv
, pipe
, DPIO_CALIBRATION
, reg_val
);
4567 reg_val
= vlv_dpio_read(dev_priv
, pipe
, DPIO_IREF(1));
4568 reg_val
&= 0xffffff00;
4569 vlv_dpio_write(dev_priv
, pipe
, DPIO_IREF(1), reg_val
);
4571 reg_val
= vlv_dpio_read(dev_priv
, pipe
, DPIO_CALIBRATION
);
4572 reg_val
&= 0x00ffffff;
4573 reg_val
|= 0xb0000000;
4574 vlv_dpio_write(dev_priv
, pipe
, DPIO_CALIBRATION
, reg_val
);
4577 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
4578 struct intel_link_m_n
*m_n
)
4580 struct drm_device
*dev
= crtc
->base
.dev
;
4581 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4582 int pipe
= crtc
->pipe
;
4584 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
4585 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
4586 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
4587 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
4590 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
4591 struct intel_link_m_n
*m_n
)
4593 struct drm_device
*dev
= crtc
->base
.dev
;
4594 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4595 int pipe
= crtc
->pipe
;
4596 enum transcoder transcoder
= crtc
->config
.cpu_transcoder
;
4598 if (INTEL_INFO(dev
)->gen
>= 5) {
4599 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
4600 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
4601 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
4602 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
4604 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
4605 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
4606 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
4607 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
4611 static void intel_dp_set_m_n(struct intel_crtc
*crtc
)
4613 if (crtc
->config
.has_pch_encoder
)
4614 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
4616 intel_cpu_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
4619 static void vlv_update_pll(struct intel_crtc
*crtc
)
4621 struct drm_device
*dev
= crtc
->base
.dev
;
4622 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4623 int pipe
= crtc
->pipe
;
4625 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
4626 u32 coreclk
, reg_val
, dpll_md
;
4628 mutex_lock(&dev_priv
->dpio_lock
);
4630 bestn
= crtc
->config
.dpll
.n
;
4631 bestm1
= crtc
->config
.dpll
.m1
;
4632 bestm2
= crtc
->config
.dpll
.m2
;
4633 bestp1
= crtc
->config
.dpll
.p1
;
4634 bestp2
= crtc
->config
.dpll
.p2
;
4636 /* See eDP HDMI DPIO driver vbios notes doc */
4638 /* PLL B needs special handling */
4640 vlv_pllb_recal_opamp(dev_priv
, pipe
);
4642 /* Set up Tx target for periodic Rcomp update */
4643 vlv_dpio_write(dev_priv
, pipe
, DPIO_IREF_BCAST
, 0x0100000f);
4645 /* Disable target IRef on PLL */
4646 reg_val
= vlv_dpio_read(dev_priv
, pipe
, DPIO_IREF_CTL(pipe
));
4647 reg_val
&= 0x00ffffff;
4648 vlv_dpio_write(dev_priv
, pipe
, DPIO_IREF_CTL(pipe
), reg_val
);
4650 /* Disable fast lock */
4651 vlv_dpio_write(dev_priv
, pipe
, DPIO_FASTCLK_DISABLE
, 0x610);
4653 /* Set idtafcrecal before PLL is enabled */
4654 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
4655 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
4656 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
4657 mdiv
|= (1 << DPIO_K_SHIFT
);
4660 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4661 * but we don't support that).
4662 * Note: don't use the DAC post divider as it seems unstable.
4664 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
4665 vlv_dpio_write(dev_priv
, pipe
, DPIO_DIV(pipe
), mdiv
);
4667 mdiv
|= DPIO_ENABLE_CALIBRATION
;
4668 vlv_dpio_write(dev_priv
, pipe
, DPIO_DIV(pipe
), mdiv
);
4670 /* Set HBR and RBR LPF coefficients */
4671 if (crtc
->config
.port_clock
== 162000 ||
4672 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_ANALOG
) ||
4673 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
))
4674 vlv_dpio_write(dev_priv
, pipe
, DPIO_LPF_COEFF(pipe
),
4677 vlv_dpio_write(dev_priv
, pipe
, DPIO_LPF_COEFF(pipe
),
4680 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
) ||
4681 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
)) {
4682 /* Use SSC source */
4684 vlv_dpio_write(dev_priv
, pipe
, DPIO_REFSFR(pipe
),
4687 vlv_dpio_write(dev_priv
, pipe
, DPIO_REFSFR(pipe
),
4689 } else { /* HDMI or VGA */
4690 /* Use bend source */
4692 vlv_dpio_write(dev_priv
, pipe
, DPIO_REFSFR(pipe
),
4695 vlv_dpio_write(dev_priv
, pipe
, DPIO_REFSFR(pipe
),
4699 coreclk
= vlv_dpio_read(dev_priv
, pipe
, DPIO_CORE_CLK(pipe
));
4700 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
4701 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
) ||
4702 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
))
4703 coreclk
|= 0x01000000;
4704 vlv_dpio_write(dev_priv
, pipe
, DPIO_CORE_CLK(pipe
), coreclk
);
4706 vlv_dpio_write(dev_priv
, pipe
, DPIO_PLL_CML(pipe
), 0x87871000);
4708 /* Enable DPIO clock input */
4709 dpll
= DPLL_EXT_BUFFER_ENABLE_VLV
| DPLL_REFA_CLK_ENABLE_VLV
|
4710 DPLL_VGA_MODE_DIS
| DPLL_INTEGRATED_CLOCK_VLV
;
4711 /* We should never disable this, set it here for state tracking */
4713 dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
4714 dpll
|= DPLL_VCO_ENABLE
;
4715 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
4717 dpll_md
= (crtc
->config
.pixel_multiplier
- 1)
4718 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4719 crtc
->config
.dpll_hw_state
.dpll_md
= dpll_md
;
4721 if (crtc
->config
.has_dp_encoder
)
4722 intel_dp_set_m_n(crtc
);
4724 mutex_unlock(&dev_priv
->dpio_lock
);
4727 static void i9xx_update_pll(struct intel_crtc
*crtc
,
4728 intel_clock_t
*reduced_clock
,
4731 struct drm_device
*dev
= crtc
->base
.dev
;
4732 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4735 struct dpll
*clock
= &crtc
->config
.dpll
;
4737 i9xx_update_pll_dividers(crtc
, reduced_clock
);
4739 is_sdvo
= intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_SDVO
) ||
4740 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
);
4742 dpll
= DPLL_VGA_MODE_DIS
;
4744 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
))
4745 dpll
|= DPLLB_MODE_LVDS
;
4747 dpll
|= DPLLB_MODE_DAC_SERIAL
;
4749 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
4750 dpll
|= (crtc
->config
.pixel_multiplier
- 1)
4751 << SDVO_MULTIPLIER_SHIFT_HIRES
;
4755 dpll
|= DPLL_SDVO_HIGH_SPEED
;
4757 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
))
4758 dpll
|= DPLL_SDVO_HIGH_SPEED
;
4760 /* compute bitmask from p1 value */
4761 if (IS_PINEVIEW(dev
))
4762 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
4764 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4765 if (IS_G4X(dev
) && reduced_clock
)
4766 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
4768 switch (clock
->p2
) {
4770 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
4773 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
4776 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
4779 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
4782 if (INTEL_INFO(dev
)->gen
>= 4)
4783 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
4785 if (crtc
->config
.sdvo_tv_clock
)
4786 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
4787 else if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4788 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4789 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4791 dpll
|= PLL_REF_INPUT_DREFCLK
;
4793 dpll
|= DPLL_VCO_ENABLE
;
4794 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
4796 if (INTEL_INFO(dev
)->gen
>= 4) {
4797 u32 dpll_md
= (crtc
->config
.pixel_multiplier
- 1)
4798 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4799 crtc
->config
.dpll_hw_state
.dpll_md
= dpll_md
;
4802 if (crtc
->config
.has_dp_encoder
)
4803 intel_dp_set_m_n(crtc
);
4806 static void i8xx_update_pll(struct intel_crtc
*crtc
,
4807 intel_clock_t
*reduced_clock
,
4810 struct drm_device
*dev
= crtc
->base
.dev
;
4811 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4813 struct dpll
*clock
= &crtc
->config
.dpll
;
4815 i9xx_update_pll_dividers(crtc
, reduced_clock
);
4817 dpll
= DPLL_VGA_MODE_DIS
;
4819 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
)) {
4820 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4823 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
4825 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4827 dpll
|= PLL_P2_DIVIDE_BY_4
;
4830 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DVO
))
4831 dpll
|= DPLL_DVO_2X_MODE
;
4833 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4834 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4835 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4837 dpll
|= PLL_REF_INPUT_DREFCLK
;
4839 dpll
|= DPLL_VCO_ENABLE
;
4840 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
4843 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
4845 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4846 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4847 enum pipe pipe
= intel_crtc
->pipe
;
4848 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
4849 struct drm_display_mode
*adjusted_mode
=
4850 &intel_crtc
->config
.adjusted_mode
;
4851 uint32_t vsyncshift
, crtc_vtotal
, crtc_vblank_end
;
4853 /* We need to be careful not to changed the adjusted mode, for otherwise
4854 * the hw state checker will get angry at the mismatch. */
4855 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
4856 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
4858 if (!IS_GEN2(dev
) && adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
4859 /* the chip adds 2 halflines automatically */
4861 crtc_vblank_end
-= 1;
4862 vsyncshift
= adjusted_mode
->crtc_hsync_start
4863 - adjusted_mode
->crtc_htotal
/ 2;
4868 if (INTEL_INFO(dev
)->gen
> 3)
4869 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
4871 I915_WRITE(HTOTAL(cpu_transcoder
),
4872 (adjusted_mode
->crtc_hdisplay
- 1) |
4873 ((adjusted_mode
->crtc_htotal
- 1) << 16));
4874 I915_WRITE(HBLANK(cpu_transcoder
),
4875 (adjusted_mode
->crtc_hblank_start
- 1) |
4876 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
4877 I915_WRITE(HSYNC(cpu_transcoder
),
4878 (adjusted_mode
->crtc_hsync_start
- 1) |
4879 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
4881 I915_WRITE(VTOTAL(cpu_transcoder
),
4882 (adjusted_mode
->crtc_vdisplay
- 1) |
4883 ((crtc_vtotal
- 1) << 16));
4884 I915_WRITE(VBLANK(cpu_transcoder
),
4885 (adjusted_mode
->crtc_vblank_start
- 1) |
4886 ((crtc_vblank_end
- 1) << 16));
4887 I915_WRITE(VSYNC(cpu_transcoder
),
4888 (adjusted_mode
->crtc_vsync_start
- 1) |
4889 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
4891 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4892 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4893 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4895 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
4896 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
4897 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
4899 /* pipesrc controls the size that is scaled from, which should
4900 * always be the user's requested size.
4902 I915_WRITE(PIPESRC(pipe
),
4903 ((intel_crtc
->config
.pipe_src_w
- 1) << 16) |
4904 (intel_crtc
->config
.pipe_src_h
- 1));
4907 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
4908 struct intel_crtc_config
*pipe_config
)
4910 struct drm_device
*dev
= crtc
->base
.dev
;
4911 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4912 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
4915 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
4916 pipe_config
->adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
4917 pipe_config
->adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
4918 tmp
= I915_READ(HBLANK(cpu_transcoder
));
4919 pipe_config
->adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
4920 pipe_config
->adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
4921 tmp
= I915_READ(HSYNC(cpu_transcoder
));
4922 pipe_config
->adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
4923 pipe_config
->adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
4925 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
4926 pipe_config
->adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
4927 pipe_config
->adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
4928 tmp
= I915_READ(VBLANK(cpu_transcoder
));
4929 pipe_config
->adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
4930 pipe_config
->adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
4931 tmp
= I915_READ(VSYNC(cpu_transcoder
));
4932 pipe_config
->adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
4933 pipe_config
->adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
4935 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
4936 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
4937 pipe_config
->adjusted_mode
.crtc_vtotal
+= 1;
4938 pipe_config
->adjusted_mode
.crtc_vblank_end
+= 1;
4941 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
4942 pipe_config
->pipe_src_h
= (tmp
& 0xffff) + 1;
4943 pipe_config
->pipe_src_w
= ((tmp
>> 16) & 0xffff) + 1;
4945 pipe_config
->requested_mode
.vdisplay
= pipe_config
->pipe_src_h
;
4946 pipe_config
->requested_mode
.hdisplay
= pipe_config
->pipe_src_w
;
4949 static void intel_crtc_mode_from_pipe_config(struct intel_crtc
*intel_crtc
,
4950 struct intel_crtc_config
*pipe_config
)
4952 struct drm_crtc
*crtc
= &intel_crtc
->base
;
4954 crtc
->mode
.hdisplay
= pipe_config
->adjusted_mode
.crtc_hdisplay
;
4955 crtc
->mode
.htotal
= pipe_config
->adjusted_mode
.crtc_htotal
;
4956 crtc
->mode
.hsync_start
= pipe_config
->adjusted_mode
.crtc_hsync_start
;
4957 crtc
->mode
.hsync_end
= pipe_config
->adjusted_mode
.crtc_hsync_end
;
4959 crtc
->mode
.vdisplay
= pipe_config
->adjusted_mode
.crtc_vdisplay
;
4960 crtc
->mode
.vtotal
= pipe_config
->adjusted_mode
.crtc_vtotal
;
4961 crtc
->mode
.vsync_start
= pipe_config
->adjusted_mode
.crtc_vsync_start
;
4962 crtc
->mode
.vsync_end
= pipe_config
->adjusted_mode
.crtc_vsync_end
;
4964 crtc
->mode
.flags
= pipe_config
->adjusted_mode
.flags
;
4966 crtc
->mode
.clock
= pipe_config
->adjusted_mode
.crtc_clock
;
4967 crtc
->mode
.flags
|= pipe_config
->adjusted_mode
.flags
;
4970 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
4972 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4973 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4978 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
4979 I915_READ(PIPECONF(intel_crtc
->pipe
)) & PIPECONF_ENABLE
)
4980 pipeconf
|= PIPECONF_ENABLE
;
4982 if (intel_crtc
->config
.double_wide
)
4983 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
4985 /* only g4x and later have fancy bpc/dither controls */
4986 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
4987 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4988 if (intel_crtc
->config
.dither
&& intel_crtc
->config
.pipe_bpp
!= 30)
4989 pipeconf
|= PIPECONF_DITHER_EN
|
4990 PIPECONF_DITHER_TYPE_SP
;
4992 switch (intel_crtc
->config
.pipe_bpp
) {
4994 pipeconf
|= PIPECONF_6BPC
;
4997 pipeconf
|= PIPECONF_8BPC
;
5000 pipeconf
|= PIPECONF_10BPC
;
5003 /* Case prevented by intel_choose_pipe_bpp_dither. */
5008 if (HAS_PIPE_CXSR(dev
)) {
5009 if (intel_crtc
->lowfreq_avail
) {
5010 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5011 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
5013 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5017 if (!IS_GEN2(dev
) &&
5018 intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
5019 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
5021 pipeconf
|= PIPECONF_PROGRESSIVE
;
5023 if (IS_VALLEYVIEW(dev
) && intel_crtc
->config
.limited_color_range
)
5024 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
5026 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
5027 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
5030 static int i9xx_crtc_mode_set(struct drm_crtc
*crtc
,
5032 struct drm_framebuffer
*fb
)
5034 struct drm_device
*dev
= crtc
->dev
;
5035 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5036 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5037 int pipe
= intel_crtc
->pipe
;
5038 int plane
= intel_crtc
->plane
;
5039 int refclk
, num_connectors
= 0;
5040 intel_clock_t clock
, reduced_clock
;
5042 bool ok
, has_reduced_clock
= false;
5043 bool is_lvds
= false, is_dsi
= false;
5044 struct intel_encoder
*encoder
;
5045 const intel_limit_t
*limit
;
5048 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5049 switch (encoder
->type
) {
5050 case INTEL_OUTPUT_LVDS
:
5053 case INTEL_OUTPUT_DSI
:
5064 if (!intel_crtc
->config
.clock_set
) {
5065 refclk
= i9xx_get_refclk(crtc
, num_connectors
);
5068 * Returns a set of divisors for the desired target clock with
5069 * the given refclk, or FALSE. The returned values represent
5070 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5073 limit
= intel_limit(crtc
, refclk
);
5074 ok
= dev_priv
->display
.find_dpll(limit
, crtc
,
5075 intel_crtc
->config
.port_clock
,
5076 refclk
, NULL
, &clock
);
5078 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5082 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
5084 * Ensure we match the reduced clock's P to the target
5085 * clock. If the clocks don't match, we can't switch
5086 * the display clock by using the FP0/FP1. In such case
5087 * we will disable the LVDS downclock feature.
5090 dev_priv
->display
.find_dpll(limit
, crtc
,
5091 dev_priv
->lvds_downclock
,
5095 /* Compat-code for transition, will disappear. */
5096 intel_crtc
->config
.dpll
.n
= clock
.n
;
5097 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
5098 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
5099 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
5100 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
5104 i8xx_update_pll(intel_crtc
,
5105 has_reduced_clock
? &reduced_clock
: NULL
,
5107 } else if (IS_VALLEYVIEW(dev
)) {
5108 vlv_update_pll(intel_crtc
);
5110 i9xx_update_pll(intel_crtc
,
5111 has_reduced_clock
? &reduced_clock
: NULL
,
5116 /* Set up the display plane register */
5117 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
5119 if (!IS_VALLEYVIEW(dev
)) {
5121 dspcntr
&= ~DISPPLANE_SEL_PIPE_MASK
;
5123 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
5126 intel_set_pipe_timings(intel_crtc
);
5128 /* pipesrc and dspsize control the size that is scaled from,
5129 * which should always be the user's requested size.
5131 I915_WRITE(DSPSIZE(plane
),
5132 ((intel_crtc
->config
.pipe_src_h
- 1) << 16) |
5133 (intel_crtc
->config
.pipe_src_w
- 1));
5134 I915_WRITE(DSPPOS(plane
), 0);
5136 i9xx_set_pipeconf(intel_crtc
);
5138 I915_WRITE(DSPCNTR(plane
), dspcntr
);
5139 POSTING_READ(DSPCNTR(plane
));
5141 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
5146 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
5147 struct intel_crtc_config
*pipe_config
)
5149 struct drm_device
*dev
= crtc
->base
.dev
;
5150 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5153 tmp
= I915_READ(PFIT_CONTROL
);
5154 if (!(tmp
& PFIT_ENABLE
))
5157 /* Check whether the pfit is attached to our pipe. */
5158 if (INTEL_INFO(dev
)->gen
< 4) {
5159 if (crtc
->pipe
!= PIPE_B
)
5162 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
5166 pipe_config
->gmch_pfit
.control
= tmp
;
5167 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
5168 if (INTEL_INFO(dev
)->gen
< 5)
5169 pipe_config
->gmch_pfit
.lvds_border_bits
=
5170 I915_READ(LVDS
) & LVDS_BORDER_ENABLE
;
5173 static void vlv_crtc_clock_get(struct intel_crtc
*crtc
,
5174 struct intel_crtc_config
*pipe_config
)
5176 struct drm_device
*dev
= crtc
->base
.dev
;
5177 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5178 int pipe
= pipe_config
->cpu_transcoder
;
5179 intel_clock_t clock
;
5181 int refclk
= 100000;
5183 mutex_lock(&dev_priv
->dpio_lock
);
5184 mdiv
= vlv_dpio_read(dev_priv
, pipe
, DPIO_DIV(pipe
));
5185 mutex_unlock(&dev_priv
->dpio_lock
);
5187 clock
.m1
= (mdiv
>> DPIO_M1DIV_SHIFT
) & 7;
5188 clock
.m2
= mdiv
& DPIO_M2DIV_MASK
;
5189 clock
.n
= (mdiv
>> DPIO_N_SHIFT
) & 0xf;
5190 clock
.p1
= (mdiv
>> DPIO_P1_SHIFT
) & 7;
5191 clock
.p2
= (mdiv
>> DPIO_P2_SHIFT
) & 0x1f;
5193 clock
.vco
= refclk
* clock
.m1
* clock
.m2
/ clock
.n
;
5194 clock
.dot
= 2 * clock
.vco
/ (clock
.p1
* clock
.p2
);
5196 pipe_config
->port_clock
= clock
.dot
/ 10;
5199 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
5200 struct intel_crtc_config
*pipe_config
)
5202 struct drm_device
*dev
= crtc
->base
.dev
;
5203 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5206 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
5207 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
5209 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
5210 if (!(tmp
& PIPECONF_ENABLE
))
5213 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
5214 switch (tmp
& PIPECONF_BPC_MASK
) {
5216 pipe_config
->pipe_bpp
= 18;
5219 pipe_config
->pipe_bpp
= 24;
5221 case PIPECONF_10BPC
:
5222 pipe_config
->pipe_bpp
= 30;
5229 if (INTEL_INFO(dev
)->gen
< 4)
5230 pipe_config
->double_wide
= tmp
& PIPECONF_DOUBLE_WIDE
;
5232 intel_get_pipe_timings(crtc
, pipe_config
);
5234 i9xx_get_pfit_config(crtc
, pipe_config
);
5236 if (INTEL_INFO(dev
)->gen
>= 4) {
5237 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
5238 pipe_config
->pixel_multiplier
=
5239 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
5240 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
5241 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
5242 } else if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
5243 tmp
= I915_READ(DPLL(crtc
->pipe
));
5244 pipe_config
->pixel_multiplier
=
5245 ((tmp
& SDVO_MULTIPLIER_MASK
)
5246 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
5248 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5249 * port and will be fixed up in the encoder->get_config
5251 pipe_config
->pixel_multiplier
= 1;
5253 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
5254 if (!IS_VALLEYVIEW(dev
)) {
5255 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
5256 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
5258 /* Mask out read-only status bits. */
5259 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
5260 DPLL_PORTC_READY_MASK
|
5261 DPLL_PORTB_READY_MASK
);
5264 if (IS_VALLEYVIEW(dev
))
5265 vlv_crtc_clock_get(crtc
, pipe_config
);
5267 i9xx_crtc_clock_get(crtc
, pipe_config
);
5272 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
5274 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5275 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
5276 struct intel_encoder
*encoder
;
5278 bool has_lvds
= false;
5279 bool has_cpu_edp
= false;
5280 bool has_panel
= false;
5281 bool has_ck505
= false;
5282 bool can_ssc
= false;
5284 /* We need to take the global config into account */
5285 list_for_each_entry(encoder
, &mode_config
->encoder_list
,
5287 switch (encoder
->type
) {
5288 case INTEL_OUTPUT_LVDS
:
5292 case INTEL_OUTPUT_EDP
:
5294 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
5300 if (HAS_PCH_IBX(dev
)) {
5301 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
5302 can_ssc
= has_ck505
;
5308 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5309 has_panel
, has_lvds
, has_ck505
);
5311 /* Ironlake: try to setup display ref clock before DPLL
5312 * enabling. This is only under driver's control after
5313 * PCH B stepping, previous chipset stepping should be
5314 * ignoring this setting.
5316 val
= I915_READ(PCH_DREF_CONTROL
);
5318 /* As we must carefully and slowly disable/enable each source in turn,
5319 * compute the final state we want first and check if we need to
5320 * make any changes at all.
5323 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
5325 final
|= DREF_NONSPREAD_CK505_ENABLE
;
5327 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
5329 final
&= ~DREF_SSC_SOURCE_MASK
;
5330 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
5331 final
&= ~DREF_SSC1_ENABLE
;
5334 final
|= DREF_SSC_SOURCE_ENABLE
;
5336 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
5337 final
|= DREF_SSC1_ENABLE
;
5340 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
5341 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
5343 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
5345 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5347 final
|= DREF_SSC_SOURCE_DISABLE
;
5348 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5354 /* Always enable nonspread source */
5355 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
5358 val
|= DREF_NONSPREAD_CK505_ENABLE
;
5360 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
5363 val
&= ~DREF_SSC_SOURCE_MASK
;
5364 val
|= DREF_SSC_SOURCE_ENABLE
;
5366 /* SSC must be turned on before enabling the CPU output */
5367 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
5368 DRM_DEBUG_KMS("Using SSC on panel\n");
5369 val
|= DREF_SSC1_ENABLE
;
5371 val
&= ~DREF_SSC1_ENABLE
;
5373 /* Get SSC going before enabling the outputs */
5374 I915_WRITE(PCH_DREF_CONTROL
, val
);
5375 POSTING_READ(PCH_DREF_CONTROL
);
5378 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
5380 /* Enable CPU source on CPU attached eDP */
5382 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
5383 DRM_DEBUG_KMS("Using SSC on eDP\n");
5384 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
5387 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
5389 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5391 I915_WRITE(PCH_DREF_CONTROL
, val
);
5392 POSTING_READ(PCH_DREF_CONTROL
);
5395 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5397 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
5399 /* Turn off CPU output */
5400 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5402 I915_WRITE(PCH_DREF_CONTROL
, val
);
5403 POSTING_READ(PCH_DREF_CONTROL
);
5406 /* Turn off the SSC source */
5407 val
&= ~DREF_SSC_SOURCE_MASK
;
5408 val
|= DREF_SSC_SOURCE_DISABLE
;
5411 val
&= ~DREF_SSC1_ENABLE
;
5413 I915_WRITE(PCH_DREF_CONTROL
, val
);
5414 POSTING_READ(PCH_DREF_CONTROL
);
5418 BUG_ON(val
!= final
);
5421 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
5425 tmp
= I915_READ(SOUTH_CHICKEN2
);
5426 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
5427 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
5429 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
5430 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
5431 DRM_ERROR("FDI mPHY reset assert timeout\n");
5433 tmp
= I915_READ(SOUTH_CHICKEN2
);
5434 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
5435 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
5437 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
5438 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
5439 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5442 /* WaMPhyProgramming:hsw */
5443 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
5447 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
5448 tmp
&= ~(0xFF << 24);
5449 tmp
|= (0x12 << 24);
5450 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
5452 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
5454 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
5456 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
5458 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
5460 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
5461 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
5462 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
5464 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
5465 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
5466 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
5468 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
5471 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
5473 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
5476 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
5478 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
5481 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
5483 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
5486 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
5488 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
5489 tmp
&= ~(0xFF << 16);
5490 tmp
|= (0x1C << 16);
5491 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
5493 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
5494 tmp
&= ~(0xFF << 16);
5495 tmp
|= (0x1C << 16);
5496 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
5498 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
5500 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
5502 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
5504 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
5506 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
5507 tmp
&= ~(0xF << 28);
5509 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
5511 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
5512 tmp
&= ~(0xF << 28);
5514 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
5517 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5518 * Programming" based on the parameters passed:
5519 * - Sequence to enable CLKOUT_DP
5520 * - Sequence to enable CLKOUT_DP without spread
5521 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5523 static void lpt_enable_clkout_dp(struct drm_device
*dev
, bool with_spread
,
5526 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5529 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
5531 if (WARN(dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
&&
5532 with_fdi
, "LP PCH doesn't have FDI\n"))
5535 mutex_lock(&dev_priv
->dpio_lock
);
5537 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
5538 tmp
&= ~SBI_SSCCTL_DISABLE
;
5539 tmp
|= SBI_SSCCTL_PATHALT
;
5540 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5545 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
5546 tmp
&= ~SBI_SSCCTL_PATHALT
;
5547 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5550 lpt_reset_fdi_mphy(dev_priv
);
5551 lpt_program_fdi_mphy(dev_priv
);
5555 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
5556 SBI_GEN0
: SBI_DBUFF0
;
5557 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
5558 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
5559 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
5561 mutex_unlock(&dev_priv
->dpio_lock
);
5564 /* Sequence to disable CLKOUT_DP */
5565 static void lpt_disable_clkout_dp(struct drm_device
*dev
)
5567 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5570 mutex_lock(&dev_priv
->dpio_lock
);
5572 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
5573 SBI_GEN0
: SBI_DBUFF0
;
5574 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
5575 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
5576 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
5578 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
5579 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
5580 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
5581 tmp
|= SBI_SSCCTL_PATHALT
;
5582 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5585 tmp
|= SBI_SSCCTL_DISABLE
;
5586 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5589 mutex_unlock(&dev_priv
->dpio_lock
);
5592 static void lpt_init_pch_refclk(struct drm_device
*dev
)
5594 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
5595 struct intel_encoder
*encoder
;
5596 bool has_vga
= false;
5598 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
) {
5599 switch (encoder
->type
) {
5600 case INTEL_OUTPUT_ANALOG
:
5607 lpt_enable_clkout_dp(dev
, true, true);
5609 lpt_disable_clkout_dp(dev
);
5613 * Initialize reference clocks when the driver loads
5615 void intel_init_pch_refclk(struct drm_device
*dev
)
5617 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
5618 ironlake_init_pch_refclk(dev
);
5619 else if (HAS_PCH_LPT(dev
))
5620 lpt_init_pch_refclk(dev
);
5623 static int ironlake_get_refclk(struct drm_crtc
*crtc
)
5625 struct drm_device
*dev
= crtc
->dev
;
5626 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5627 struct intel_encoder
*encoder
;
5628 int num_connectors
= 0;
5629 bool is_lvds
= false;
5631 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5632 switch (encoder
->type
) {
5633 case INTEL_OUTPUT_LVDS
:
5640 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
5641 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5642 dev_priv
->vbt
.lvds_ssc_freq
);
5643 return dev_priv
->vbt
.lvds_ssc_freq
* 1000;
5649 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
5651 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
5652 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5653 int pipe
= intel_crtc
->pipe
;
5658 switch (intel_crtc
->config
.pipe_bpp
) {
5660 val
|= PIPECONF_6BPC
;
5663 val
|= PIPECONF_8BPC
;
5666 val
|= PIPECONF_10BPC
;
5669 val
|= PIPECONF_12BPC
;
5672 /* Case prevented by intel_choose_pipe_bpp_dither. */
5676 if (intel_crtc
->config
.dither
)
5677 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
5679 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
5680 val
|= PIPECONF_INTERLACED_ILK
;
5682 val
|= PIPECONF_PROGRESSIVE
;
5684 if (intel_crtc
->config
.limited_color_range
)
5685 val
|= PIPECONF_COLOR_RANGE_SELECT
;
5687 I915_WRITE(PIPECONF(pipe
), val
);
5688 POSTING_READ(PIPECONF(pipe
));
5692 * Set up the pipe CSC unit.
5694 * Currently only full range RGB to limited range RGB conversion
5695 * is supported, but eventually this should handle various
5696 * RGB<->YCbCr scenarios as well.
5698 static void intel_set_pipe_csc(struct drm_crtc
*crtc
)
5700 struct drm_device
*dev
= crtc
->dev
;
5701 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5702 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5703 int pipe
= intel_crtc
->pipe
;
5704 uint16_t coeff
= 0x7800; /* 1.0 */
5707 * TODO: Check what kind of values actually come out of the pipe
5708 * with these coeff/postoff values and adjust to get the best
5709 * accuracy. Perhaps we even need to take the bpc value into
5713 if (intel_crtc
->config
.limited_color_range
)
5714 coeff
= ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5717 * GY/GU and RY/RU should be the other way around according
5718 * to BSpec, but reality doesn't agree. Just set them up in
5719 * a way that results in the correct picture.
5721 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeff
<< 16);
5722 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), 0);
5724 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeff
);
5725 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), 0);
5727 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), 0);
5728 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeff
<< 16);
5730 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
5731 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
5732 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
5734 if (INTEL_INFO(dev
)->gen
> 6) {
5735 uint16_t postoff
= 0;
5737 if (intel_crtc
->config
.limited_color_range
)
5738 postoff
= (16 * (1 << 13) / 255) & 0x1fff;
5740 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
5741 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
5742 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
5744 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
5746 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
5748 if (intel_crtc
->config
.limited_color_range
)
5749 mode
|= CSC_BLACK_SCREEN_OFFSET
;
5751 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
5755 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
5757 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
5758 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5759 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
5764 if (intel_crtc
->config
.dither
)
5765 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
5767 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
5768 val
|= PIPECONF_INTERLACED_ILK
;
5770 val
|= PIPECONF_PROGRESSIVE
;
5772 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
5773 POSTING_READ(PIPECONF(cpu_transcoder
));
5775 I915_WRITE(GAMMA_MODE(intel_crtc
->pipe
), GAMMA_MODE_MODE_8BIT
);
5776 POSTING_READ(GAMMA_MODE(intel_crtc
->pipe
));
5779 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
5780 intel_clock_t
*clock
,
5781 bool *has_reduced_clock
,
5782 intel_clock_t
*reduced_clock
)
5784 struct drm_device
*dev
= crtc
->dev
;
5785 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5786 struct intel_encoder
*intel_encoder
;
5788 const intel_limit_t
*limit
;
5789 bool ret
, is_lvds
= false;
5791 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5792 switch (intel_encoder
->type
) {
5793 case INTEL_OUTPUT_LVDS
:
5799 refclk
= ironlake_get_refclk(crtc
);
5802 * Returns a set of divisors for the desired target clock with the given
5803 * refclk, or FALSE. The returned values represent the clock equation:
5804 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5806 limit
= intel_limit(crtc
, refclk
);
5807 ret
= dev_priv
->display
.find_dpll(limit
, crtc
,
5808 to_intel_crtc(crtc
)->config
.port_clock
,
5809 refclk
, NULL
, clock
);
5813 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
5815 * Ensure we match the reduced clock's P to the target clock.
5816 * If the clocks don't match, we can't switch the display clock
5817 * by using the FP0/FP1. In such case we will disable the LVDS
5818 * downclock feature.
5820 *has_reduced_clock
=
5821 dev_priv
->display
.find_dpll(limit
, crtc
,
5822 dev_priv
->lvds_downclock
,
5830 static void cpt_enable_fdi_bc_bifurcation(struct drm_device
*dev
)
5832 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5835 temp
= I915_READ(SOUTH_CHICKEN1
);
5836 if (temp
& FDI_BC_BIFURCATION_SELECT
)
5839 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
5840 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
5842 temp
|= FDI_BC_BIFURCATION_SELECT
;
5843 DRM_DEBUG_KMS("enabling fdi C rx\n");
5844 I915_WRITE(SOUTH_CHICKEN1
, temp
);
5845 POSTING_READ(SOUTH_CHICKEN1
);
5848 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
5850 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5851 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5853 switch (intel_crtc
->pipe
) {
5857 if (intel_crtc
->config
.fdi_lanes
> 2)
5858 WARN_ON(I915_READ(SOUTH_CHICKEN1
) & FDI_BC_BIFURCATION_SELECT
);
5860 cpt_enable_fdi_bc_bifurcation(dev
);
5864 cpt_enable_fdi_bc_bifurcation(dev
);
5872 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
5875 * Account for spread spectrum to avoid
5876 * oversubscribing the link. Max center spread
5877 * is 2.5%; use 5% for safety's sake.
5879 u32 bps
= target_clock
* bpp
* 21 / 20;
5880 return bps
/ (link_bw
* 8) + 1;
5883 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
5885 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
5888 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
5890 intel_clock_t
*reduced_clock
, u32
*fp2
)
5892 struct drm_crtc
*crtc
= &intel_crtc
->base
;
5893 struct drm_device
*dev
= crtc
->dev
;
5894 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5895 struct intel_encoder
*intel_encoder
;
5897 int factor
, num_connectors
= 0;
5898 bool is_lvds
= false, is_sdvo
= false;
5900 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5901 switch (intel_encoder
->type
) {
5902 case INTEL_OUTPUT_LVDS
:
5905 case INTEL_OUTPUT_SDVO
:
5906 case INTEL_OUTPUT_HDMI
:
5914 /* Enable autotuning of the PLL clock (if permissible) */
5917 if ((intel_panel_use_ssc(dev_priv
) &&
5918 dev_priv
->vbt
.lvds_ssc_freq
== 100) ||
5919 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
5921 } else if (intel_crtc
->config
.sdvo_tv_clock
)
5924 if (ironlake_needs_fb_cb_tune(&intel_crtc
->config
.dpll
, factor
))
5927 if (fp2
&& (reduced_clock
->m
< factor
* reduced_clock
->n
))
5933 dpll
|= DPLLB_MODE_LVDS
;
5935 dpll
|= DPLLB_MODE_DAC_SERIAL
;
5937 dpll
|= (intel_crtc
->config
.pixel_multiplier
- 1)
5938 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
5941 dpll
|= DPLL_SDVO_HIGH_SPEED
;
5942 if (intel_crtc
->config
.has_dp_encoder
)
5943 dpll
|= DPLL_SDVO_HIGH_SPEED
;
5945 /* compute bitmask from p1 value */
5946 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5948 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
5950 switch (intel_crtc
->config
.dpll
.p2
) {
5952 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
5955 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
5958 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
5961 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
5965 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
5966 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
5968 dpll
|= PLL_REF_INPUT_DREFCLK
;
5970 return dpll
| DPLL_VCO_ENABLE
;
5973 static int ironlake_crtc_mode_set(struct drm_crtc
*crtc
,
5975 struct drm_framebuffer
*fb
)
5977 struct drm_device
*dev
= crtc
->dev
;
5978 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5979 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5980 int pipe
= intel_crtc
->pipe
;
5981 int plane
= intel_crtc
->plane
;
5982 int num_connectors
= 0;
5983 intel_clock_t clock
, reduced_clock
;
5984 u32 dpll
= 0, fp
= 0, fp2
= 0;
5985 bool ok
, has_reduced_clock
= false;
5986 bool is_lvds
= false;
5987 struct intel_encoder
*encoder
;
5988 struct intel_shared_dpll
*pll
;
5991 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5992 switch (encoder
->type
) {
5993 case INTEL_OUTPUT_LVDS
:
6001 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
6002 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
6004 ok
= ironlake_compute_clocks(crtc
, &clock
,
6005 &has_reduced_clock
, &reduced_clock
);
6006 if (!ok
&& !intel_crtc
->config
.clock_set
) {
6007 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6010 /* Compat-code for transition, will disappear. */
6011 if (!intel_crtc
->config
.clock_set
) {
6012 intel_crtc
->config
.dpll
.n
= clock
.n
;
6013 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
6014 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
6015 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
6016 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
6019 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6020 if (intel_crtc
->config
.has_pch_encoder
) {
6021 fp
= i9xx_dpll_compute_fp(&intel_crtc
->config
.dpll
);
6022 if (has_reduced_clock
)
6023 fp2
= i9xx_dpll_compute_fp(&reduced_clock
);
6025 dpll
= ironlake_compute_dpll(intel_crtc
,
6026 &fp
, &reduced_clock
,
6027 has_reduced_clock
? &fp2
: NULL
);
6029 intel_crtc
->config
.dpll_hw_state
.dpll
= dpll
;
6030 intel_crtc
->config
.dpll_hw_state
.fp0
= fp
;
6031 if (has_reduced_clock
)
6032 intel_crtc
->config
.dpll_hw_state
.fp1
= fp2
;
6034 intel_crtc
->config
.dpll_hw_state
.fp1
= fp
;
6036 pll
= intel_get_shared_dpll(intel_crtc
);
6038 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6043 intel_put_shared_dpll(intel_crtc
);
6045 if (intel_crtc
->config
.has_dp_encoder
)
6046 intel_dp_set_m_n(intel_crtc
);
6048 if (is_lvds
&& has_reduced_clock
&& i915_powersave
)
6049 intel_crtc
->lowfreq_avail
= true;
6051 intel_crtc
->lowfreq_avail
= false;
6053 if (intel_crtc
->config
.has_pch_encoder
) {
6054 pll
= intel_crtc_to_shared_dpll(intel_crtc
);
6058 intel_set_pipe_timings(intel_crtc
);
6060 if (intel_crtc
->config
.has_pch_encoder
) {
6061 intel_cpu_transcoder_set_m_n(intel_crtc
,
6062 &intel_crtc
->config
.fdi_m_n
);
6065 if (IS_IVYBRIDGE(dev
))
6066 ivybridge_update_fdi_bc_bifurcation(intel_crtc
);
6068 ironlake_set_pipeconf(crtc
);
6070 /* Set up the display plane register */
6071 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
);
6072 POSTING_READ(DSPCNTR(plane
));
6074 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
6079 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
6080 struct intel_link_m_n
*m_n
)
6082 struct drm_device
*dev
= crtc
->base
.dev
;
6083 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6084 enum pipe pipe
= crtc
->pipe
;
6086 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
6087 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
6088 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
6090 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
6091 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
6092 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
6095 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
6096 enum transcoder transcoder
,
6097 struct intel_link_m_n
*m_n
)
6099 struct drm_device
*dev
= crtc
->base
.dev
;
6100 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6101 enum pipe pipe
= crtc
->pipe
;
6103 if (INTEL_INFO(dev
)->gen
>= 5) {
6104 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
6105 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
6106 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
6108 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
6109 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
6110 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
6112 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
6113 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
6114 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
6116 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
6117 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
6118 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
6122 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
6123 struct intel_crtc_config
*pipe_config
)
6125 if (crtc
->config
.has_pch_encoder
)
6126 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
6128 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
6129 &pipe_config
->dp_m_n
);
6132 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
6133 struct intel_crtc_config
*pipe_config
)
6135 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
6136 &pipe_config
->fdi_m_n
);
6139 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
6140 struct intel_crtc_config
*pipe_config
)
6142 struct drm_device
*dev
= crtc
->base
.dev
;
6143 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6146 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
6148 if (tmp
& PF_ENABLE
) {
6149 pipe_config
->pch_pfit
.enabled
= true;
6150 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
6151 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
6153 /* We currently do not free assignements of panel fitters on
6154 * ivb/hsw (since we don't use the higher upscaling modes which
6155 * differentiates them) so just WARN about this case for now. */
6157 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
6158 PF_PIPE_SEL_IVB(crtc
->pipe
));
6163 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
6164 struct intel_crtc_config
*pipe_config
)
6166 struct drm_device
*dev
= crtc
->base
.dev
;
6167 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6170 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
6171 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
6173 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
6174 if (!(tmp
& PIPECONF_ENABLE
))
6177 switch (tmp
& PIPECONF_BPC_MASK
) {
6179 pipe_config
->pipe_bpp
= 18;
6182 pipe_config
->pipe_bpp
= 24;
6184 case PIPECONF_10BPC
:
6185 pipe_config
->pipe_bpp
= 30;
6187 case PIPECONF_12BPC
:
6188 pipe_config
->pipe_bpp
= 36;
6194 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
6195 struct intel_shared_dpll
*pll
;
6197 pipe_config
->has_pch_encoder
= true;
6199 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
6200 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
6201 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
6203 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
6205 if (HAS_PCH_IBX(dev_priv
->dev
)) {
6206 pipe_config
->shared_dpll
=
6207 (enum intel_dpll_id
) crtc
->pipe
;
6209 tmp
= I915_READ(PCH_DPLL_SEL
);
6210 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
6211 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_B
;
6213 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_A
;
6216 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
6218 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
6219 &pipe_config
->dpll_hw_state
));
6221 tmp
= pipe_config
->dpll_hw_state
.dpll
;
6222 pipe_config
->pixel_multiplier
=
6223 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
6224 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
6226 ironlake_pch_clock_get(crtc
, pipe_config
);
6228 pipe_config
->pixel_multiplier
= 1;
6231 intel_get_pipe_timings(crtc
, pipe_config
);
6233 ironlake_get_pfit_config(crtc
, pipe_config
);
6238 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
6240 struct drm_device
*dev
= dev_priv
->dev
;
6241 struct intel_ddi_plls
*plls
= &dev_priv
->ddi_plls
;
6242 struct intel_crtc
*crtc
;
6243 unsigned long irqflags
;
6246 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
)
6247 WARN(crtc
->base
.enabled
, "CRTC for pipe %c enabled\n",
6248 pipe_name(crtc
->pipe
));
6250 WARN(I915_READ(HSW_PWR_WELL_DRIVER
), "Power well on\n");
6251 WARN(plls
->spll_refcount
, "SPLL enabled\n");
6252 WARN(plls
->wrpll1_refcount
, "WRPLL1 enabled\n");
6253 WARN(plls
->wrpll2_refcount
, "WRPLL2 enabled\n");
6254 WARN(I915_READ(PCH_PP_STATUS
) & PP_ON
, "Panel power on\n");
6255 WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
6256 "CPU PWM1 enabled\n");
6257 WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
6258 "CPU PWM2 enabled\n");
6259 WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
6260 "PCH PWM1 enabled\n");
6261 WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
6262 "Utility pin enabled\n");
6263 WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
6265 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
6266 val
= I915_READ(DEIMR
);
6267 WARN((val
& ~DE_PCH_EVENT_IVB
) != val
,
6268 "Unexpected DEIMR bits enabled: 0x%x\n", val
);
6269 val
= I915_READ(SDEIMR
);
6270 WARN((val
| SDE_HOTPLUG_MASK_CPT
) != 0xffffffff,
6271 "Unexpected SDEIMR bits enabled: 0x%x\n", val
);
6272 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
6276 * This function implements pieces of two sequences from BSpec:
6277 * - Sequence for display software to disable LCPLL
6278 * - Sequence for display software to allow package C8+
6279 * The steps implemented here are just the steps that actually touch the LCPLL
6280 * register. Callers should take care of disabling all the display engine
6281 * functions, doing the mode unset, fixing interrupts, etc.
6283 static void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
6284 bool switch_to_fclk
, bool allow_power_down
)
6288 assert_can_disable_lcpll(dev_priv
);
6290 val
= I915_READ(LCPLL_CTL
);
6292 if (switch_to_fclk
) {
6293 val
|= LCPLL_CD_SOURCE_FCLK
;
6294 I915_WRITE(LCPLL_CTL
, val
);
6296 if (wait_for_atomic_us(I915_READ(LCPLL_CTL
) &
6297 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
6298 DRM_ERROR("Switching to FCLK failed\n");
6300 val
= I915_READ(LCPLL_CTL
);
6303 val
|= LCPLL_PLL_DISABLE
;
6304 I915_WRITE(LCPLL_CTL
, val
);
6305 POSTING_READ(LCPLL_CTL
);
6307 if (wait_for((I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
) == 0, 1))
6308 DRM_ERROR("LCPLL still locked\n");
6310 val
= I915_READ(D_COMP
);
6311 val
|= D_COMP_COMP_DISABLE
;
6312 mutex_lock(&dev_priv
->rps
.hw_lock
);
6313 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
, val
))
6314 DRM_ERROR("Failed to disable D_COMP\n");
6315 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6316 POSTING_READ(D_COMP
);
6319 if (wait_for((I915_READ(D_COMP
) & D_COMP_RCOMP_IN_PROGRESS
) == 0, 1))
6320 DRM_ERROR("D_COMP RCOMP still in progress\n");
6322 if (allow_power_down
) {
6323 val
= I915_READ(LCPLL_CTL
);
6324 val
|= LCPLL_POWER_DOWN_ALLOW
;
6325 I915_WRITE(LCPLL_CTL
, val
);
6326 POSTING_READ(LCPLL_CTL
);
6331 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6334 static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
6338 val
= I915_READ(LCPLL_CTL
);
6340 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
6341 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
6344 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6345 * we'll hang the machine! */
6346 dev_priv
->uncore
.funcs
.force_wake_get(dev_priv
);
6348 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
6349 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
6350 I915_WRITE(LCPLL_CTL
, val
);
6351 POSTING_READ(LCPLL_CTL
);
6354 val
= I915_READ(D_COMP
);
6355 val
|= D_COMP_COMP_FORCE
;
6356 val
&= ~D_COMP_COMP_DISABLE
;
6357 mutex_lock(&dev_priv
->rps
.hw_lock
);
6358 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
, val
))
6359 DRM_ERROR("Failed to enable D_COMP\n");
6360 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6361 POSTING_READ(D_COMP
);
6363 val
= I915_READ(LCPLL_CTL
);
6364 val
&= ~LCPLL_PLL_DISABLE
;
6365 I915_WRITE(LCPLL_CTL
, val
);
6367 if (wait_for(I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
, 5))
6368 DRM_ERROR("LCPLL not locked yet\n");
6370 if (val
& LCPLL_CD_SOURCE_FCLK
) {
6371 val
= I915_READ(LCPLL_CTL
);
6372 val
&= ~LCPLL_CD_SOURCE_FCLK
;
6373 I915_WRITE(LCPLL_CTL
, val
);
6375 if (wait_for_atomic_us((I915_READ(LCPLL_CTL
) &
6376 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
6377 DRM_ERROR("Switching back to LCPLL failed\n");
6380 dev_priv
->uncore
.funcs
.force_wake_put(dev_priv
);
6383 void hsw_enable_pc8_work(struct work_struct
*__work
)
6385 struct drm_i915_private
*dev_priv
=
6386 container_of(to_delayed_work(__work
), struct drm_i915_private
,
6388 struct drm_device
*dev
= dev_priv
->dev
;
6391 if (dev_priv
->pc8
.enabled
)
6394 DRM_DEBUG_KMS("Enabling package C8+\n");
6396 dev_priv
->pc8
.enabled
= true;
6398 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
6399 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
6400 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
6401 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
6404 lpt_disable_clkout_dp(dev
);
6405 hsw_pc8_disable_interrupts(dev
);
6406 hsw_disable_lcpll(dev_priv
, true, true);
6409 static void __hsw_enable_package_c8(struct drm_i915_private
*dev_priv
)
6411 WARN_ON(!mutex_is_locked(&dev_priv
->pc8
.lock
));
6412 WARN(dev_priv
->pc8
.disable_count
< 1,
6413 "pc8.disable_count: %d\n", dev_priv
->pc8
.disable_count
);
6415 dev_priv
->pc8
.disable_count
--;
6416 if (dev_priv
->pc8
.disable_count
!= 0)
6419 schedule_delayed_work(&dev_priv
->pc8
.enable_work
,
6420 msecs_to_jiffies(i915_pc8_timeout
));
6423 static void __hsw_disable_package_c8(struct drm_i915_private
*dev_priv
)
6425 struct drm_device
*dev
= dev_priv
->dev
;
6428 WARN_ON(!mutex_is_locked(&dev_priv
->pc8
.lock
));
6429 WARN(dev_priv
->pc8
.disable_count
< 0,
6430 "pc8.disable_count: %d\n", dev_priv
->pc8
.disable_count
);
6432 dev_priv
->pc8
.disable_count
++;
6433 if (dev_priv
->pc8
.disable_count
!= 1)
6436 cancel_delayed_work_sync(&dev_priv
->pc8
.enable_work
);
6437 if (!dev_priv
->pc8
.enabled
)
6440 DRM_DEBUG_KMS("Disabling package C8+\n");
6442 hsw_restore_lcpll(dev_priv
);
6443 hsw_pc8_restore_interrupts(dev
);
6444 lpt_init_pch_refclk(dev
);
6446 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
6447 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
6448 val
|= PCH_LP_PARTITION_LEVEL_DISABLE
;
6449 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
6452 intel_prepare_ddi(dev
);
6453 i915_gem_init_swizzling(dev
);
6454 mutex_lock(&dev_priv
->rps
.hw_lock
);
6455 gen6_update_ring_freq(dev
);
6456 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6457 dev_priv
->pc8
.enabled
= false;
6460 void hsw_enable_package_c8(struct drm_i915_private
*dev_priv
)
6462 mutex_lock(&dev_priv
->pc8
.lock
);
6463 __hsw_enable_package_c8(dev_priv
);
6464 mutex_unlock(&dev_priv
->pc8
.lock
);
6467 void hsw_disable_package_c8(struct drm_i915_private
*dev_priv
)
6469 mutex_lock(&dev_priv
->pc8
.lock
);
6470 __hsw_disable_package_c8(dev_priv
);
6471 mutex_unlock(&dev_priv
->pc8
.lock
);
6474 static bool hsw_can_enable_package_c8(struct drm_i915_private
*dev_priv
)
6476 struct drm_device
*dev
= dev_priv
->dev
;
6477 struct intel_crtc
*crtc
;
6480 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
)
6481 if (crtc
->base
.enabled
)
6484 /* This case is still possible since we have the i915.disable_power_well
6485 * parameter and also the KVMr or something else might be requesting the
6487 val
= I915_READ(HSW_PWR_WELL_DRIVER
);
6489 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6496 /* Since we're called from modeset_global_resources there's no way to
6497 * symmetrically increase and decrease the refcount, so we use
6498 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6501 static void hsw_update_package_c8(struct drm_device
*dev
)
6503 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6506 if (!i915_enable_pc8
)
6509 mutex_lock(&dev_priv
->pc8
.lock
);
6511 allow
= hsw_can_enable_package_c8(dev_priv
);
6513 if (allow
== dev_priv
->pc8
.requirements_met
)
6516 dev_priv
->pc8
.requirements_met
= allow
;
6519 __hsw_enable_package_c8(dev_priv
);
6521 __hsw_disable_package_c8(dev_priv
);
6524 mutex_unlock(&dev_priv
->pc8
.lock
);
6527 static void hsw_package_c8_gpu_idle(struct drm_i915_private
*dev_priv
)
6529 if (!dev_priv
->pc8
.gpu_idle
) {
6530 dev_priv
->pc8
.gpu_idle
= true;
6531 hsw_enable_package_c8(dev_priv
);
6535 static void hsw_package_c8_gpu_busy(struct drm_i915_private
*dev_priv
)
6537 if (dev_priv
->pc8
.gpu_idle
) {
6538 dev_priv
->pc8
.gpu_idle
= false;
6539 hsw_disable_package_c8(dev_priv
);
6543 static void haswell_modeset_global_resources(struct drm_device
*dev
)
6545 bool enable
= false;
6546 struct intel_crtc
*crtc
;
6548 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
6549 if (!crtc
->base
.enabled
)
6552 if (crtc
->pipe
!= PIPE_A
|| crtc
->config
.pch_pfit
.enabled
||
6553 crtc
->config
.cpu_transcoder
!= TRANSCODER_EDP
)
6557 intel_set_power_well(dev
, enable
);
6559 hsw_update_package_c8(dev
);
6562 static int haswell_crtc_mode_set(struct drm_crtc
*crtc
,
6564 struct drm_framebuffer
*fb
)
6566 struct drm_device
*dev
= crtc
->dev
;
6567 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6568 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6569 int plane
= intel_crtc
->plane
;
6572 if (!intel_ddi_pll_mode_set(crtc
))
6575 if (intel_crtc
->config
.has_dp_encoder
)
6576 intel_dp_set_m_n(intel_crtc
);
6578 intel_crtc
->lowfreq_avail
= false;
6580 intel_set_pipe_timings(intel_crtc
);
6582 if (intel_crtc
->config
.has_pch_encoder
) {
6583 intel_cpu_transcoder_set_m_n(intel_crtc
,
6584 &intel_crtc
->config
.fdi_m_n
);
6587 haswell_set_pipeconf(crtc
);
6589 intel_set_pipe_csc(crtc
);
6591 /* Set up the display plane register */
6592 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
| DISPPLANE_PIPE_CSC_ENABLE
);
6593 POSTING_READ(DSPCNTR(plane
));
6595 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
6600 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
6601 struct intel_crtc_config
*pipe_config
)
6603 struct drm_device
*dev
= crtc
->base
.dev
;
6604 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6605 enum intel_display_power_domain pfit_domain
;
6608 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
6609 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
6611 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
6612 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
6613 enum pipe trans_edp_pipe
;
6614 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
6616 WARN(1, "unknown pipe linked to edp transcoder\n");
6617 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
6618 case TRANS_DDI_EDP_INPUT_A_ON
:
6619 trans_edp_pipe
= PIPE_A
;
6621 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
6622 trans_edp_pipe
= PIPE_B
;
6624 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
6625 trans_edp_pipe
= PIPE_C
;
6629 if (trans_edp_pipe
== crtc
->pipe
)
6630 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
6633 if (!intel_display_power_enabled(dev
,
6634 POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
)))
6637 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
6638 if (!(tmp
& PIPECONF_ENABLE
))
6642 * Haswell has only FDI/PCH transcoder A. It is which is connected to
6643 * DDI E. So just check whether this pipe is wired to DDI E and whether
6644 * the PCH transcoder is on.
6646 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
6647 if ((tmp
& TRANS_DDI_PORT_MASK
) == TRANS_DDI_SELECT_PORT(PORT_E
) &&
6648 I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
6649 pipe_config
->has_pch_encoder
= true;
6651 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
6652 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
6653 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
6655 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
6658 intel_get_pipe_timings(crtc
, pipe_config
);
6660 pfit_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
6661 if (intel_display_power_enabled(dev
, pfit_domain
))
6662 ironlake_get_pfit_config(crtc
, pipe_config
);
6664 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
6665 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
6667 pipe_config
->pixel_multiplier
= 1;
6672 static int intel_crtc_mode_set(struct drm_crtc
*crtc
,
6674 struct drm_framebuffer
*fb
)
6676 struct drm_device
*dev
= crtc
->dev
;
6677 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6678 struct intel_encoder
*encoder
;
6679 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6680 struct drm_display_mode
*mode
= &intel_crtc
->config
.requested_mode
;
6681 int pipe
= intel_crtc
->pipe
;
6684 drm_vblank_pre_modeset(dev
, pipe
);
6686 ret
= dev_priv
->display
.crtc_mode_set(crtc
, x
, y
, fb
);
6688 drm_vblank_post_modeset(dev
, pipe
);
6693 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
6694 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6695 encoder
->base
.base
.id
,
6696 drm_get_encoder_name(&encoder
->base
),
6697 mode
->base
.id
, mode
->name
);
6698 encoder
->mode_set(encoder
);
6704 static bool intel_eld_uptodate(struct drm_connector
*connector
,
6705 int reg_eldv
, uint32_t bits_eldv
,
6706 int reg_elda
, uint32_t bits_elda
,
6709 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6710 uint8_t *eld
= connector
->eld
;
6713 i
= I915_READ(reg_eldv
);
6722 i
= I915_READ(reg_elda
);
6724 I915_WRITE(reg_elda
, i
);
6726 for (i
= 0; i
< eld
[2]; i
++)
6727 if (I915_READ(reg_edid
) != *((uint32_t *)eld
+ i
))
6733 static void g4x_write_eld(struct drm_connector
*connector
,
6734 struct drm_crtc
*crtc
)
6736 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6737 uint8_t *eld
= connector
->eld
;
6742 i
= I915_READ(G4X_AUD_VID_DID
);
6744 if (i
== INTEL_AUDIO_DEVBLC
|| i
== INTEL_AUDIO_DEVCL
)
6745 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
6747 eldv
= G4X_ELDV_DEVCTG
;
6749 if (intel_eld_uptodate(connector
,
6750 G4X_AUD_CNTL_ST
, eldv
,
6751 G4X_AUD_CNTL_ST
, G4X_ELD_ADDR
,
6752 G4X_HDMIW_HDMIEDID
))
6755 i
= I915_READ(G4X_AUD_CNTL_ST
);
6756 i
&= ~(eldv
| G4X_ELD_ADDR
);
6757 len
= (i
>> 9) & 0x1f; /* ELD buffer size */
6758 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
6763 len
= min_t(uint8_t, eld
[2], len
);
6764 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6765 for (i
= 0; i
< len
; i
++)
6766 I915_WRITE(G4X_HDMIW_HDMIEDID
, *((uint32_t *)eld
+ i
));
6768 i
= I915_READ(G4X_AUD_CNTL_ST
);
6770 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
6773 static void haswell_write_eld(struct drm_connector
*connector
,
6774 struct drm_crtc
*crtc
)
6776 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6777 uint8_t *eld
= connector
->eld
;
6778 struct drm_device
*dev
= crtc
->dev
;
6779 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6783 int pipe
= to_intel_crtc(crtc
)->pipe
;
6786 int hdmiw_hdmiedid
= HSW_AUD_EDID_DATA(pipe
);
6787 int aud_cntl_st
= HSW_AUD_DIP_ELD_CTRL(pipe
);
6788 int aud_config
= HSW_AUD_CFG(pipe
);
6789 int aud_cntrl_st2
= HSW_AUD_PIN_ELD_CP_VLD
;
6792 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6794 /* Audio output enable */
6795 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6796 tmp
= I915_READ(aud_cntrl_st2
);
6797 tmp
|= (AUDIO_OUTPUT_ENABLE_A
<< (pipe
* 4));
6798 I915_WRITE(aud_cntrl_st2
, tmp
);
6800 /* Wait for 1 vertical blank */
6801 intel_wait_for_vblank(dev
, pipe
);
6803 /* Set ELD valid state */
6804 tmp
= I915_READ(aud_cntrl_st2
);
6805 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp
);
6806 tmp
|= (AUDIO_ELD_VALID_A
<< (pipe
* 4));
6807 I915_WRITE(aud_cntrl_st2
, tmp
);
6808 tmp
= I915_READ(aud_cntrl_st2
);
6809 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp
);
6811 /* Enable HDMI mode */
6812 tmp
= I915_READ(aud_config
);
6813 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp
);
6814 /* clear N_programing_enable and N_value_index */
6815 tmp
&= ~(AUD_CONFIG_N_VALUE_INDEX
| AUD_CONFIG_N_PROG_ENABLE
);
6816 I915_WRITE(aud_config
, tmp
);
6818 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
6820 eldv
= AUDIO_ELD_VALID_A
<< (pipe
* 4);
6821 intel_crtc
->eld_vld
= true;
6823 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
6824 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6825 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6826 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
6828 I915_WRITE(aud_config
, 0);
6830 if (intel_eld_uptodate(connector
,
6831 aud_cntrl_st2
, eldv
,
6832 aud_cntl_st
, IBX_ELD_ADDRESS
,
6836 i
= I915_READ(aud_cntrl_st2
);
6838 I915_WRITE(aud_cntrl_st2
, i
);
6843 i
= I915_READ(aud_cntl_st
);
6844 i
&= ~IBX_ELD_ADDRESS
;
6845 I915_WRITE(aud_cntl_st
, i
);
6846 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
6847 DRM_DEBUG_DRIVER("port num:%d\n", i
);
6849 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
6850 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6851 for (i
= 0; i
< len
; i
++)
6852 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
6854 i
= I915_READ(aud_cntrl_st2
);
6856 I915_WRITE(aud_cntrl_st2
, i
);
6860 static void ironlake_write_eld(struct drm_connector
*connector
,
6861 struct drm_crtc
*crtc
)
6863 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6864 uint8_t *eld
= connector
->eld
;
6872 int pipe
= to_intel_crtc(crtc
)->pipe
;
6874 if (HAS_PCH_IBX(connector
->dev
)) {
6875 hdmiw_hdmiedid
= IBX_HDMIW_HDMIEDID(pipe
);
6876 aud_config
= IBX_AUD_CFG(pipe
);
6877 aud_cntl_st
= IBX_AUD_CNTL_ST(pipe
);
6878 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
6880 hdmiw_hdmiedid
= CPT_HDMIW_HDMIEDID(pipe
);
6881 aud_config
= CPT_AUD_CFG(pipe
);
6882 aud_cntl_st
= CPT_AUD_CNTL_ST(pipe
);
6883 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
6886 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
6888 i
= I915_READ(aud_cntl_st
);
6889 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
6891 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6892 /* operate blindly on all ports */
6893 eldv
= IBX_ELD_VALIDB
;
6894 eldv
|= IBX_ELD_VALIDB
<< 4;
6895 eldv
|= IBX_ELD_VALIDB
<< 8;
6897 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i
));
6898 eldv
= IBX_ELD_VALIDB
<< ((i
- 1) * 4);
6901 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
6902 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6903 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6904 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
6906 I915_WRITE(aud_config
, 0);
6908 if (intel_eld_uptodate(connector
,
6909 aud_cntrl_st2
, eldv
,
6910 aud_cntl_st
, IBX_ELD_ADDRESS
,
6914 i
= I915_READ(aud_cntrl_st2
);
6916 I915_WRITE(aud_cntrl_st2
, i
);
6921 i
= I915_READ(aud_cntl_st
);
6922 i
&= ~IBX_ELD_ADDRESS
;
6923 I915_WRITE(aud_cntl_st
, i
);
6925 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
6926 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6927 for (i
= 0; i
< len
; i
++)
6928 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
6930 i
= I915_READ(aud_cntrl_st2
);
6932 I915_WRITE(aud_cntrl_st2
, i
);
6935 void intel_write_eld(struct drm_encoder
*encoder
,
6936 struct drm_display_mode
*mode
)
6938 struct drm_crtc
*crtc
= encoder
->crtc
;
6939 struct drm_connector
*connector
;
6940 struct drm_device
*dev
= encoder
->dev
;
6941 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6943 connector
= drm_select_eld(encoder
, mode
);
6947 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6949 drm_get_connector_name(connector
),
6950 connector
->encoder
->base
.id
,
6951 drm_get_encoder_name(connector
->encoder
));
6953 connector
->eld
[6] = drm_av_sync_delay(connector
, mode
) / 2;
6955 if (dev_priv
->display
.write_eld
)
6956 dev_priv
->display
.write_eld(connector
, crtc
);
6959 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6961 struct drm_device
*dev
= crtc
->dev
;
6962 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6963 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6964 bool visible
= base
!= 0;
6967 if (intel_crtc
->cursor_visible
== visible
)
6970 cntl
= I915_READ(_CURACNTR
);
6972 /* On these chipsets we can only modify the base whilst
6973 * the cursor is disabled.
6975 I915_WRITE(_CURABASE
, base
);
6977 cntl
&= ~(CURSOR_FORMAT_MASK
);
6978 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6979 cntl
|= CURSOR_ENABLE
|
6980 CURSOR_GAMMA_ENABLE
|
6983 cntl
&= ~(CURSOR_ENABLE
| CURSOR_GAMMA_ENABLE
);
6984 I915_WRITE(_CURACNTR
, cntl
);
6986 intel_crtc
->cursor_visible
= visible
;
6989 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6991 struct drm_device
*dev
= crtc
->dev
;
6992 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6993 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6994 int pipe
= intel_crtc
->pipe
;
6995 bool visible
= base
!= 0;
6997 if (intel_crtc
->cursor_visible
!= visible
) {
6998 uint32_t cntl
= I915_READ(CURCNTR(pipe
));
7000 cntl
&= ~(CURSOR_MODE
| MCURSOR_PIPE_SELECT
);
7001 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
7002 cntl
|= pipe
<< 28; /* Connect to correct pipe */
7004 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
7005 cntl
|= CURSOR_MODE_DISABLE
;
7007 I915_WRITE(CURCNTR(pipe
), cntl
);
7009 intel_crtc
->cursor_visible
= visible
;
7011 /* and commit changes on next vblank */
7012 I915_WRITE(CURBASE(pipe
), base
);
7015 static void ivb_update_cursor(struct drm_crtc
*crtc
, u32 base
)
7017 struct drm_device
*dev
= crtc
->dev
;
7018 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7019 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7020 int pipe
= intel_crtc
->pipe
;
7021 bool visible
= base
!= 0;
7023 if (intel_crtc
->cursor_visible
!= visible
) {
7024 uint32_t cntl
= I915_READ(CURCNTR_IVB(pipe
));
7026 cntl
&= ~CURSOR_MODE
;
7027 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
7029 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
7030 cntl
|= CURSOR_MODE_DISABLE
;
7032 if (IS_HASWELL(dev
)) {
7033 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
7034 cntl
&= ~CURSOR_TRICKLE_FEED_DISABLE
;
7036 I915_WRITE(CURCNTR_IVB(pipe
), cntl
);
7038 intel_crtc
->cursor_visible
= visible
;
7040 /* and commit changes on next vblank */
7041 I915_WRITE(CURBASE_IVB(pipe
), base
);
7044 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7045 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
7048 struct drm_device
*dev
= crtc
->dev
;
7049 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7050 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7051 int pipe
= intel_crtc
->pipe
;
7052 int x
= intel_crtc
->cursor_x
;
7053 int y
= intel_crtc
->cursor_y
;
7054 u32 base
= 0, pos
= 0;
7058 base
= intel_crtc
->cursor_addr
;
7060 if (x
>= intel_crtc
->config
.pipe_src_w
)
7063 if (y
>= intel_crtc
->config
.pipe_src_h
)
7067 if (x
+ intel_crtc
->cursor_width
<= 0)
7070 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
7073 pos
|= x
<< CURSOR_X_SHIFT
;
7076 if (y
+ intel_crtc
->cursor_height
<= 0)
7079 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
7082 pos
|= y
<< CURSOR_Y_SHIFT
;
7084 visible
= base
!= 0;
7085 if (!visible
&& !intel_crtc
->cursor_visible
)
7088 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
7089 I915_WRITE(CURPOS_IVB(pipe
), pos
);
7090 ivb_update_cursor(crtc
, base
);
7092 I915_WRITE(CURPOS(pipe
), pos
);
7093 if (IS_845G(dev
) || IS_I865G(dev
))
7094 i845_update_cursor(crtc
, base
);
7096 i9xx_update_cursor(crtc
, base
);
7100 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
7101 struct drm_file
*file
,
7103 uint32_t width
, uint32_t height
)
7105 struct drm_device
*dev
= crtc
->dev
;
7106 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7107 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7108 struct drm_i915_gem_object
*obj
;
7112 /* if we want to turn off the cursor ignore width and height */
7114 DRM_DEBUG_KMS("cursor off\n");
7117 mutex_lock(&dev
->struct_mutex
);
7121 /* Currently we only support 64x64 cursors */
7122 if (width
!= 64 || height
!= 64) {
7123 DRM_ERROR("we currently only support 64x64 cursors\n");
7127 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
7128 if (&obj
->base
== NULL
)
7131 if (obj
->base
.size
< width
* height
* 4) {
7132 DRM_ERROR("buffer is to small\n");
7137 /* we only need to pin inside GTT if cursor is non-phy */
7138 mutex_lock(&dev
->struct_mutex
);
7139 if (!dev_priv
->info
->cursor_needs_physical
) {
7142 if (obj
->tiling_mode
) {
7143 DRM_ERROR("cursor cannot be tiled\n");
7148 /* Note that the w/a also requires 2 PTE of padding following
7149 * the bo. We currently fill all unused PTE with the shadow
7150 * page and so we should always have valid PTE following the
7151 * cursor preventing the VT-d warning.
7154 if (need_vtd_wa(dev
))
7155 alignment
= 64*1024;
7157 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, NULL
);
7159 DRM_ERROR("failed to move cursor bo into the GTT\n");
7163 ret
= i915_gem_object_put_fence(obj
);
7165 DRM_ERROR("failed to release fence for cursor");
7169 addr
= i915_gem_obj_ggtt_offset(obj
);
7171 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
7172 ret
= i915_gem_attach_phys_object(dev
, obj
,
7173 (intel_crtc
->pipe
== 0) ? I915_GEM_PHYS_CURSOR_0
: I915_GEM_PHYS_CURSOR_1
,
7176 DRM_ERROR("failed to attach phys object\n");
7179 addr
= obj
->phys_obj
->handle
->busaddr
;
7183 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
7186 if (intel_crtc
->cursor_bo
) {
7187 if (dev_priv
->info
->cursor_needs_physical
) {
7188 if (intel_crtc
->cursor_bo
!= obj
)
7189 i915_gem_detach_phys_object(dev
, intel_crtc
->cursor_bo
);
7191 i915_gem_object_unpin_from_display_plane(intel_crtc
->cursor_bo
);
7192 drm_gem_object_unreference(&intel_crtc
->cursor_bo
->base
);
7195 mutex_unlock(&dev
->struct_mutex
);
7197 intel_crtc
->cursor_addr
= addr
;
7198 intel_crtc
->cursor_bo
= obj
;
7199 intel_crtc
->cursor_width
= width
;
7200 intel_crtc
->cursor_height
= height
;
7202 if (intel_crtc
->active
)
7203 intel_crtc_update_cursor(crtc
, intel_crtc
->cursor_bo
!= NULL
);
7207 i915_gem_object_unpin_from_display_plane(obj
);
7209 mutex_unlock(&dev
->struct_mutex
);
7211 drm_gem_object_unreference_unlocked(&obj
->base
);
7215 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
7217 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7219 intel_crtc
->cursor_x
= x
;
7220 intel_crtc
->cursor_y
= y
;
7222 if (intel_crtc
->active
)
7223 intel_crtc_update_cursor(crtc
, intel_crtc
->cursor_bo
!= NULL
);
7228 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
7229 u16
*blue
, uint32_t start
, uint32_t size
)
7231 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
7232 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7234 for (i
= start
; i
< end
; i
++) {
7235 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
7236 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
7237 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
7240 intel_crtc_load_lut(crtc
);
7243 /* VESA 640x480x72Hz mode to set on the pipe */
7244 static struct drm_display_mode load_detect_mode
= {
7245 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
7246 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
7249 static struct drm_framebuffer
*
7250 intel_framebuffer_create(struct drm_device
*dev
,
7251 struct drm_mode_fb_cmd2
*mode_cmd
,
7252 struct drm_i915_gem_object
*obj
)
7254 struct intel_framebuffer
*intel_fb
;
7257 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
7259 drm_gem_object_unreference_unlocked(&obj
->base
);
7260 return ERR_PTR(-ENOMEM
);
7263 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
7265 drm_gem_object_unreference_unlocked(&obj
->base
);
7267 return ERR_PTR(ret
);
7270 return &intel_fb
->base
;
7274 intel_framebuffer_pitch_for_width(int width
, int bpp
)
7276 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
7277 return ALIGN(pitch
, 64);
7281 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
7283 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
7284 return ALIGN(pitch
* mode
->vdisplay
, PAGE_SIZE
);
7287 static struct drm_framebuffer
*
7288 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
7289 struct drm_display_mode
*mode
,
7292 struct drm_i915_gem_object
*obj
;
7293 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
7295 obj
= i915_gem_alloc_object(dev
,
7296 intel_framebuffer_size_for_mode(mode
, bpp
));
7298 return ERR_PTR(-ENOMEM
);
7300 mode_cmd
.width
= mode
->hdisplay
;
7301 mode_cmd
.height
= mode
->vdisplay
;
7302 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
7304 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
7306 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
7309 static struct drm_framebuffer
*
7310 mode_fits_in_fbdev(struct drm_device
*dev
,
7311 struct drm_display_mode
*mode
)
7313 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7314 struct drm_i915_gem_object
*obj
;
7315 struct drm_framebuffer
*fb
;
7317 if (dev_priv
->fbdev
== NULL
)
7320 obj
= dev_priv
->fbdev
->ifb
.obj
;
7324 fb
= &dev_priv
->fbdev
->ifb
.base
;
7325 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
7326 fb
->bits_per_pixel
))
7329 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
7335 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
7336 struct drm_display_mode
*mode
,
7337 struct intel_load_detect_pipe
*old
)
7339 struct intel_crtc
*intel_crtc
;
7340 struct intel_encoder
*intel_encoder
=
7341 intel_attached_encoder(connector
);
7342 struct drm_crtc
*possible_crtc
;
7343 struct drm_encoder
*encoder
= &intel_encoder
->base
;
7344 struct drm_crtc
*crtc
= NULL
;
7345 struct drm_device
*dev
= encoder
->dev
;
7346 struct drm_framebuffer
*fb
;
7349 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7350 connector
->base
.id
, drm_get_connector_name(connector
),
7351 encoder
->base
.id
, drm_get_encoder_name(encoder
));
7354 * Algorithm gets a little messy:
7356 * - if the connector already has an assigned crtc, use it (but make
7357 * sure it's on first)
7359 * - try to find the first unused crtc that can drive this connector,
7360 * and use that if we find one
7363 /* See if we already have a CRTC for this connector */
7364 if (encoder
->crtc
) {
7365 crtc
= encoder
->crtc
;
7367 mutex_lock(&crtc
->mutex
);
7369 old
->dpms_mode
= connector
->dpms
;
7370 old
->load_detect_temp
= false;
7372 /* Make sure the crtc and connector are running */
7373 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
7374 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
7379 /* Find an unused one (if possible) */
7380 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
7382 if (!(encoder
->possible_crtcs
& (1 << i
)))
7384 if (!possible_crtc
->enabled
) {
7385 crtc
= possible_crtc
;
7391 * If we didn't find an unused CRTC, don't use any.
7394 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7398 mutex_lock(&crtc
->mutex
);
7399 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
7400 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
7402 intel_crtc
= to_intel_crtc(crtc
);
7403 old
->dpms_mode
= connector
->dpms
;
7404 old
->load_detect_temp
= true;
7405 old
->release_fb
= NULL
;
7408 mode
= &load_detect_mode
;
7410 /* We need a framebuffer large enough to accommodate all accesses
7411 * that the plane may generate whilst we perform load detection.
7412 * We can not rely on the fbcon either being present (we get called
7413 * during its initialisation to detect all boot displays, or it may
7414 * not even exist) or that it is large enough to satisfy the
7417 fb
= mode_fits_in_fbdev(dev
, mode
);
7419 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7420 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
7421 old
->release_fb
= fb
;
7423 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7425 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7426 mutex_unlock(&crtc
->mutex
);
7430 if (intel_set_mode(crtc
, mode
, 0, 0, fb
)) {
7431 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7432 if (old
->release_fb
)
7433 old
->release_fb
->funcs
->destroy(old
->release_fb
);
7434 mutex_unlock(&crtc
->mutex
);
7438 /* let the connector get through one full cycle before testing */
7439 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
7443 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
7444 struct intel_load_detect_pipe
*old
)
7446 struct intel_encoder
*intel_encoder
=
7447 intel_attached_encoder(connector
);
7448 struct drm_encoder
*encoder
= &intel_encoder
->base
;
7449 struct drm_crtc
*crtc
= encoder
->crtc
;
7451 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7452 connector
->base
.id
, drm_get_connector_name(connector
),
7453 encoder
->base
.id
, drm_get_encoder_name(encoder
));
7455 if (old
->load_detect_temp
) {
7456 to_intel_connector(connector
)->new_encoder
= NULL
;
7457 intel_encoder
->new_crtc
= NULL
;
7458 intel_set_mode(crtc
, NULL
, 0, 0, NULL
);
7460 if (old
->release_fb
) {
7461 drm_framebuffer_unregister_private(old
->release_fb
);
7462 drm_framebuffer_unreference(old
->release_fb
);
7465 mutex_unlock(&crtc
->mutex
);
7469 /* Switch crtc and encoder back off if necessary */
7470 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
7471 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
7473 mutex_unlock(&crtc
->mutex
);
7476 static int i9xx_pll_refclk(struct drm_device
*dev
,
7477 const struct intel_crtc_config
*pipe_config
)
7479 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7480 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
7482 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
7483 return dev_priv
->vbt
.lvds_ssc_freq
* 1000;
7484 else if (HAS_PCH_SPLIT(dev
))
7486 else if (!IS_GEN2(dev
))
7492 /* Returns the clock of the currently programmed mode of the given pipe. */
7493 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
7494 struct intel_crtc_config
*pipe_config
)
7496 struct drm_device
*dev
= crtc
->base
.dev
;
7497 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7498 int pipe
= pipe_config
->cpu_transcoder
;
7499 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
7501 intel_clock_t clock
;
7502 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
7504 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
7505 fp
= pipe_config
->dpll_hw_state
.fp0
;
7507 fp
= pipe_config
->dpll_hw_state
.fp1
;
7509 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
7510 if (IS_PINEVIEW(dev
)) {
7511 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
7512 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
7514 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
7515 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
7518 if (!IS_GEN2(dev
)) {
7519 if (IS_PINEVIEW(dev
))
7520 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
7521 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
7523 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
7524 DPLL_FPA01_P1_POST_DIV_SHIFT
);
7526 switch (dpll
& DPLL_MODE_MASK
) {
7527 case DPLLB_MODE_DAC_SERIAL
:
7528 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
7531 case DPLLB_MODE_LVDS
:
7532 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
7536 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7537 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
7541 if (IS_PINEVIEW(dev
))
7542 pineview_clock(refclk
, &clock
);
7544 i9xx_clock(refclk
, &clock
);
7546 bool is_lvds
= (pipe
== 1) && (I915_READ(LVDS
) & LVDS_PORT_EN
);
7549 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
7550 DPLL_FPA01_P1_POST_DIV_SHIFT
);
7553 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
7556 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
7557 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
7559 if (dpll
& PLL_P2_DIVIDE_BY_4
)
7565 i9xx_clock(refclk
, &clock
);
7569 * This value includes pixel_multiplier. We will use
7570 * port_clock to compute adjusted_mode.crtc_clock in the
7571 * encoder's get_config() function.
7573 pipe_config
->port_clock
= clock
.dot
;
7576 int intel_dotclock_calculate(int link_freq
,
7577 const struct intel_link_m_n
*m_n
)
7580 * The calculation for the data clock is:
7581 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
7582 * But we want to avoid losing precison if possible, so:
7583 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
7585 * and the link clock is simpler:
7586 * link_clock = (m * link_clock) / n
7592 return div_u64((u64
)m_n
->link_m
* link_freq
, m_n
->link_n
);
7595 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
7596 struct intel_crtc_config
*pipe_config
)
7598 struct drm_device
*dev
= crtc
->base
.dev
;
7600 /* read out port_clock from the DPLL */
7601 i9xx_crtc_clock_get(crtc
, pipe_config
);
7604 * This value does not include pixel_multiplier.
7605 * We will check that port_clock and adjusted_mode.crtc_clock
7606 * agree once we know their relationship in the encoder's
7607 * get_config() function.
7609 pipe_config
->adjusted_mode
.crtc_clock
=
7610 intel_dotclock_calculate(intel_fdi_link_freq(dev
) * 10000,
7611 &pipe_config
->fdi_m_n
);
7614 /** Returns the currently programmed mode of the given pipe. */
7615 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
7616 struct drm_crtc
*crtc
)
7618 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7619 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7620 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
7621 struct drm_display_mode
*mode
;
7622 struct intel_crtc_config pipe_config
;
7623 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
7624 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
7625 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
7626 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
7627 enum pipe pipe
= intel_crtc
->pipe
;
7629 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
7634 * Construct a pipe_config sufficient for getting the clock info
7635 * back out of crtc_clock_get.
7637 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7638 * to use a real value here instead.
7640 pipe_config
.cpu_transcoder
= (enum transcoder
) pipe
;
7641 pipe_config
.pixel_multiplier
= 1;
7642 pipe_config
.dpll_hw_state
.dpll
= I915_READ(DPLL(pipe
));
7643 pipe_config
.dpll_hw_state
.fp0
= I915_READ(FP0(pipe
));
7644 pipe_config
.dpll_hw_state
.fp1
= I915_READ(FP1(pipe
));
7645 i9xx_crtc_clock_get(intel_crtc
, &pipe_config
);
7647 mode
->clock
= pipe_config
.port_clock
/ pipe_config
.pixel_multiplier
;
7648 mode
->hdisplay
= (htot
& 0xffff) + 1;
7649 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
7650 mode
->hsync_start
= (hsync
& 0xffff) + 1;
7651 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
7652 mode
->vdisplay
= (vtot
& 0xffff) + 1;
7653 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
7654 mode
->vsync_start
= (vsync
& 0xffff) + 1;
7655 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
7657 drm_mode_set_name(mode
);
7662 static void intel_increase_pllclock(struct drm_crtc
*crtc
)
7664 struct drm_device
*dev
= crtc
->dev
;
7665 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7666 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7667 int pipe
= intel_crtc
->pipe
;
7668 int dpll_reg
= DPLL(pipe
);
7671 if (HAS_PCH_SPLIT(dev
))
7674 if (!dev_priv
->lvds_downclock_avail
)
7677 dpll
= I915_READ(dpll_reg
);
7678 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
7679 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7681 assert_panel_unlocked(dev_priv
, pipe
);
7683 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
7684 I915_WRITE(dpll_reg
, dpll
);
7685 intel_wait_for_vblank(dev
, pipe
);
7687 dpll
= I915_READ(dpll_reg
);
7688 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
7689 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7693 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
7695 struct drm_device
*dev
= crtc
->dev
;
7696 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7697 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7699 if (HAS_PCH_SPLIT(dev
))
7702 if (!dev_priv
->lvds_downclock_avail
)
7706 * Since this is called by a timer, we should never get here in
7709 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
7710 int pipe
= intel_crtc
->pipe
;
7711 int dpll_reg
= DPLL(pipe
);
7714 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7716 assert_panel_unlocked(dev_priv
, pipe
);
7718 dpll
= I915_READ(dpll_reg
);
7719 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
7720 I915_WRITE(dpll_reg
, dpll
);
7721 intel_wait_for_vblank(dev
, pipe
);
7722 dpll
= I915_READ(dpll_reg
);
7723 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
7724 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7729 void intel_mark_busy(struct drm_device
*dev
)
7731 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7733 hsw_package_c8_gpu_busy(dev_priv
);
7734 i915_update_gfx_val(dev_priv
);
7737 void intel_mark_idle(struct drm_device
*dev
)
7739 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7740 struct drm_crtc
*crtc
;
7742 hsw_package_c8_gpu_idle(dev_priv
);
7744 if (!i915_powersave
)
7747 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
7751 intel_decrease_pllclock(crtc
);
7754 if (dev_priv
->info
->gen
>= 6)
7755 gen6_rps_idle(dev
->dev_private
);
7758 void intel_mark_fb_busy(struct drm_i915_gem_object
*obj
,
7759 struct intel_ring_buffer
*ring
)
7761 struct drm_device
*dev
= obj
->base
.dev
;
7762 struct drm_crtc
*crtc
;
7764 if (!i915_powersave
)
7767 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
7771 if (to_intel_framebuffer(crtc
->fb
)->obj
!= obj
)
7774 intel_increase_pllclock(crtc
);
7775 if (ring
&& intel_fbc_enabled(dev
))
7776 ring
->fbc_dirty
= true;
7780 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
7782 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7783 struct drm_device
*dev
= crtc
->dev
;
7784 struct intel_unpin_work
*work
;
7785 unsigned long flags
;
7787 spin_lock_irqsave(&dev
->event_lock
, flags
);
7788 work
= intel_crtc
->unpin_work
;
7789 intel_crtc
->unpin_work
= NULL
;
7790 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7793 cancel_work_sync(&work
->work
);
7797 intel_crtc_cursor_set(crtc
, NULL
, 0, 0, 0);
7799 drm_crtc_cleanup(crtc
);
7804 static void intel_unpin_work_fn(struct work_struct
*__work
)
7806 struct intel_unpin_work
*work
=
7807 container_of(__work
, struct intel_unpin_work
, work
);
7808 struct drm_device
*dev
= work
->crtc
->dev
;
7810 mutex_lock(&dev
->struct_mutex
);
7811 intel_unpin_fb_obj(work
->old_fb_obj
);
7812 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
7813 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
7815 intel_update_fbc(dev
);
7816 mutex_unlock(&dev
->struct_mutex
);
7818 BUG_ON(atomic_read(&to_intel_crtc(work
->crtc
)->unpin_work_count
) == 0);
7819 atomic_dec(&to_intel_crtc(work
->crtc
)->unpin_work_count
);
7824 static void do_intel_finish_page_flip(struct drm_device
*dev
,
7825 struct drm_crtc
*crtc
)
7827 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7828 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7829 struct intel_unpin_work
*work
;
7830 unsigned long flags
;
7832 /* Ignore early vblank irqs */
7833 if (intel_crtc
== NULL
)
7836 spin_lock_irqsave(&dev
->event_lock
, flags
);
7837 work
= intel_crtc
->unpin_work
;
7839 /* Ensure we don't miss a work->pending update ... */
7842 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
7843 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7847 /* and that the unpin work is consistent wrt ->pending. */
7850 intel_crtc
->unpin_work
= NULL
;
7853 drm_send_vblank_event(dev
, intel_crtc
->pipe
, work
->event
);
7855 drm_vblank_put(dev
, intel_crtc
->pipe
);
7857 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7859 wake_up_all(&dev_priv
->pending_flip_queue
);
7861 queue_work(dev_priv
->wq
, &work
->work
);
7863 trace_i915_flip_complete(intel_crtc
->plane
, work
->pending_flip_obj
);
7866 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
7868 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7869 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
7871 do_intel_finish_page_flip(dev
, crtc
);
7874 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
7876 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7877 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
7879 do_intel_finish_page_flip(dev
, crtc
);
7882 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
7884 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7885 struct intel_crtc
*intel_crtc
=
7886 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
7887 unsigned long flags
;
7889 /* NB: An MMIO update of the plane base pointer will also
7890 * generate a page-flip completion irq, i.e. every modeset
7891 * is also accompanied by a spurious intel_prepare_page_flip().
7893 spin_lock_irqsave(&dev
->event_lock
, flags
);
7894 if (intel_crtc
->unpin_work
)
7895 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
7896 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7899 inline static void intel_mark_page_flip_active(struct intel_crtc
*intel_crtc
)
7901 /* Ensure that the work item is consistent when activating it ... */
7903 atomic_set(&intel_crtc
->unpin_work
->pending
, INTEL_FLIP_PENDING
);
7904 /* and that it is marked active as soon as the irq could fire. */
7908 static int intel_gen2_queue_flip(struct drm_device
*dev
,
7909 struct drm_crtc
*crtc
,
7910 struct drm_framebuffer
*fb
,
7911 struct drm_i915_gem_object
*obj
,
7914 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7915 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7917 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7920 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7924 ret
= intel_ring_begin(ring
, 6);
7928 /* Can't queue multiple flips, so wait for the previous
7929 * one to finish before executing the next.
7931 if (intel_crtc
->plane
)
7932 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
7934 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
7935 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
7936 intel_ring_emit(ring
, MI_NOOP
);
7937 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7938 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7939 intel_ring_emit(ring
, fb
->pitches
[0]);
7940 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
7941 intel_ring_emit(ring
, 0); /* aux display base address, unused */
7943 intel_mark_page_flip_active(intel_crtc
);
7944 __intel_ring_advance(ring
);
7948 intel_unpin_fb_obj(obj
);
7953 static int intel_gen3_queue_flip(struct drm_device
*dev
,
7954 struct drm_crtc
*crtc
,
7955 struct drm_framebuffer
*fb
,
7956 struct drm_i915_gem_object
*obj
,
7959 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7960 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7962 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7965 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7969 ret
= intel_ring_begin(ring
, 6);
7973 if (intel_crtc
->plane
)
7974 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
7976 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
7977 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
7978 intel_ring_emit(ring
, MI_NOOP
);
7979 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
7980 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7981 intel_ring_emit(ring
, fb
->pitches
[0]);
7982 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
7983 intel_ring_emit(ring
, MI_NOOP
);
7985 intel_mark_page_flip_active(intel_crtc
);
7986 __intel_ring_advance(ring
);
7990 intel_unpin_fb_obj(obj
);
7995 static int intel_gen4_queue_flip(struct drm_device
*dev
,
7996 struct drm_crtc
*crtc
,
7997 struct drm_framebuffer
*fb
,
7998 struct drm_i915_gem_object
*obj
,
8001 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8002 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8003 uint32_t pf
, pipesrc
;
8004 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
8007 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
8011 ret
= intel_ring_begin(ring
, 4);
8015 /* i965+ uses the linear or tiled offsets from the
8016 * Display Registers (which do not change across a page-flip)
8017 * so we need only reprogram the base address.
8019 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
8020 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
8021 intel_ring_emit(ring
, fb
->pitches
[0]);
8022 intel_ring_emit(ring
,
8023 (i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
) |
8026 /* XXX Enabling the panel-fitter across page-flip is so far
8027 * untested on non-native modes, so ignore it for now.
8028 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8031 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
8032 intel_ring_emit(ring
, pf
| pipesrc
);
8034 intel_mark_page_flip_active(intel_crtc
);
8035 __intel_ring_advance(ring
);
8039 intel_unpin_fb_obj(obj
);
8044 static int intel_gen6_queue_flip(struct drm_device
*dev
,
8045 struct drm_crtc
*crtc
,
8046 struct drm_framebuffer
*fb
,
8047 struct drm_i915_gem_object
*obj
,
8050 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8051 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8052 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
8053 uint32_t pf
, pipesrc
;
8056 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
8060 ret
= intel_ring_begin(ring
, 4);
8064 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
8065 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
8066 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
8067 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
8069 /* Contrary to the suggestions in the documentation,
8070 * "Enable Panel Fitter" does not seem to be required when page
8071 * flipping with a non-native mode, and worse causes a normal
8073 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8076 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
8077 intel_ring_emit(ring
, pf
| pipesrc
);
8079 intel_mark_page_flip_active(intel_crtc
);
8080 __intel_ring_advance(ring
);
8084 intel_unpin_fb_obj(obj
);
8089 static int intel_gen7_queue_flip(struct drm_device
*dev
,
8090 struct drm_crtc
*crtc
,
8091 struct drm_framebuffer
*fb
,
8092 struct drm_i915_gem_object
*obj
,
8095 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8096 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8097 struct intel_ring_buffer
*ring
;
8098 uint32_t plane_bit
= 0;
8102 if (IS_VALLEYVIEW(dev
) || ring
== NULL
|| ring
->id
!= RCS
)
8103 ring
= &dev_priv
->ring
[BCS
];
8105 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
8109 switch(intel_crtc
->plane
) {
8111 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
8114 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
8117 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
8120 WARN_ONCE(1, "unknown plane in flip command\n");
8126 if (ring
->id
== RCS
)
8129 ret
= intel_ring_begin(ring
, len
);
8133 /* Unmask the flip-done completion message. Note that the bspec says that
8134 * we should do this for both the BCS and RCS, and that we must not unmask
8135 * more than one flip event at any time (or ensure that one flip message
8136 * can be sent by waiting for flip-done prior to queueing new flips).
8137 * Experimentation says that BCS works despite DERRMR masking all
8138 * flip-done completion events and that unmasking all planes at once
8139 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8140 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8142 if (ring
->id
== RCS
) {
8143 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
8144 intel_ring_emit(ring
, DERRMR
);
8145 intel_ring_emit(ring
, ~(DERRMR_PIPEA_PRI_FLIP_DONE
|
8146 DERRMR_PIPEB_PRI_FLIP_DONE
|
8147 DERRMR_PIPEC_PRI_FLIP_DONE
));
8148 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM(1));
8149 intel_ring_emit(ring
, DERRMR
);
8150 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
+ 256);
8153 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
8154 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
8155 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
8156 intel_ring_emit(ring
, (MI_NOOP
));
8158 intel_mark_page_flip_active(intel_crtc
);
8159 __intel_ring_advance(ring
);
8163 intel_unpin_fb_obj(obj
);
8168 static int intel_default_queue_flip(struct drm_device
*dev
,
8169 struct drm_crtc
*crtc
,
8170 struct drm_framebuffer
*fb
,
8171 struct drm_i915_gem_object
*obj
,
8177 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
8178 struct drm_framebuffer
*fb
,
8179 struct drm_pending_vblank_event
*event
,
8180 uint32_t page_flip_flags
)
8182 struct drm_device
*dev
= crtc
->dev
;
8183 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8184 struct drm_framebuffer
*old_fb
= crtc
->fb
;
8185 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(fb
)->obj
;
8186 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8187 struct intel_unpin_work
*work
;
8188 unsigned long flags
;
8191 /* Can't change pixel format via MI display flips. */
8192 if (fb
->pixel_format
!= crtc
->fb
->pixel_format
)
8196 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8197 * Note that pitch changes could also affect these register.
8199 if (INTEL_INFO(dev
)->gen
> 3 &&
8200 (fb
->offsets
[0] != crtc
->fb
->offsets
[0] ||
8201 fb
->pitches
[0] != crtc
->fb
->pitches
[0]))
8204 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
8208 work
->event
= event
;
8210 work
->old_fb_obj
= to_intel_framebuffer(old_fb
)->obj
;
8211 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
8213 ret
= drm_vblank_get(dev
, intel_crtc
->pipe
);
8217 /* We borrow the event spin lock for protecting unpin_work */
8218 spin_lock_irqsave(&dev
->event_lock
, flags
);
8219 if (intel_crtc
->unpin_work
) {
8220 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
8222 drm_vblank_put(dev
, intel_crtc
->pipe
);
8224 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8227 intel_crtc
->unpin_work
= work
;
8228 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
8230 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
8231 flush_workqueue(dev_priv
->wq
);
8233 ret
= i915_mutex_lock_interruptible(dev
);
8237 /* Reference the objects for the scheduled work. */
8238 drm_gem_object_reference(&work
->old_fb_obj
->base
);
8239 drm_gem_object_reference(&obj
->base
);
8243 work
->pending_flip_obj
= obj
;
8245 work
->enable_stall_check
= true;
8247 atomic_inc(&intel_crtc
->unpin_work_count
);
8248 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
8250 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
, page_flip_flags
);
8252 goto cleanup_pending
;
8254 intel_disable_fbc(dev
);
8255 intel_mark_fb_busy(obj
, NULL
);
8256 mutex_unlock(&dev
->struct_mutex
);
8258 trace_i915_flip_request(intel_crtc
->plane
, obj
);
8263 atomic_dec(&intel_crtc
->unpin_work_count
);
8265 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
8266 drm_gem_object_unreference(&obj
->base
);
8267 mutex_unlock(&dev
->struct_mutex
);
8270 spin_lock_irqsave(&dev
->event_lock
, flags
);
8271 intel_crtc
->unpin_work
= NULL
;
8272 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
8274 drm_vblank_put(dev
, intel_crtc
->pipe
);
8281 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
8282 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
8283 .load_lut
= intel_crtc_load_lut
,
8286 static bool intel_encoder_crtc_ok(struct drm_encoder
*encoder
,
8287 struct drm_crtc
*crtc
)
8289 struct drm_device
*dev
;
8290 struct drm_crtc
*tmp
;
8293 WARN(!crtc
, "checking null crtc?\n");
8297 list_for_each_entry(tmp
, &dev
->mode_config
.crtc_list
, head
) {
8303 if (encoder
->possible_crtcs
& crtc_mask
)
8309 * intel_modeset_update_staged_output_state
8311 * Updates the staged output configuration state, e.g. after we've read out the
8314 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
8316 struct intel_encoder
*encoder
;
8317 struct intel_connector
*connector
;
8319 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8321 connector
->new_encoder
=
8322 to_intel_encoder(connector
->base
.encoder
);
8325 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8328 to_intel_crtc(encoder
->base
.crtc
);
8333 * intel_modeset_commit_output_state
8335 * This function copies the stage display pipe configuration to the real one.
8337 static void intel_modeset_commit_output_state(struct drm_device
*dev
)
8339 struct intel_encoder
*encoder
;
8340 struct intel_connector
*connector
;
8342 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8344 connector
->base
.encoder
= &connector
->new_encoder
->base
;
8347 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8349 encoder
->base
.crtc
= &encoder
->new_crtc
->base
;
8354 connected_sink_compute_bpp(struct intel_connector
* connector
,
8355 struct intel_crtc_config
*pipe_config
)
8357 int bpp
= pipe_config
->pipe_bpp
;
8359 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8360 connector
->base
.base
.id
,
8361 drm_get_connector_name(&connector
->base
));
8363 /* Don't use an invalid EDID bpc value */
8364 if (connector
->base
.display_info
.bpc
&&
8365 connector
->base
.display_info
.bpc
* 3 < bpp
) {
8366 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8367 bpp
, connector
->base
.display_info
.bpc
*3);
8368 pipe_config
->pipe_bpp
= connector
->base
.display_info
.bpc
*3;
8371 /* Clamp bpp to 8 on screens without EDID 1.4 */
8372 if (connector
->base
.display_info
.bpc
== 0 && bpp
> 24) {
8373 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8375 pipe_config
->pipe_bpp
= 24;
8380 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
8381 struct drm_framebuffer
*fb
,
8382 struct intel_crtc_config
*pipe_config
)
8384 struct drm_device
*dev
= crtc
->base
.dev
;
8385 struct intel_connector
*connector
;
8388 switch (fb
->pixel_format
) {
8390 bpp
= 8*3; /* since we go through a colormap */
8392 case DRM_FORMAT_XRGB1555
:
8393 case DRM_FORMAT_ARGB1555
:
8394 /* checked in intel_framebuffer_init already */
8395 if (WARN_ON(INTEL_INFO(dev
)->gen
> 3))
8397 case DRM_FORMAT_RGB565
:
8398 bpp
= 6*3; /* min is 18bpp */
8400 case DRM_FORMAT_XBGR8888
:
8401 case DRM_FORMAT_ABGR8888
:
8402 /* checked in intel_framebuffer_init already */
8403 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
8405 case DRM_FORMAT_XRGB8888
:
8406 case DRM_FORMAT_ARGB8888
:
8409 case DRM_FORMAT_XRGB2101010
:
8410 case DRM_FORMAT_ARGB2101010
:
8411 case DRM_FORMAT_XBGR2101010
:
8412 case DRM_FORMAT_ABGR2101010
:
8413 /* checked in intel_framebuffer_init already */
8414 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
8418 /* TODO: gen4+ supports 16 bpc floating point, too. */
8420 DRM_DEBUG_KMS("unsupported depth\n");
8424 pipe_config
->pipe_bpp
= bpp
;
8426 /* Clamp display bpp to EDID value */
8427 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8429 if (!connector
->new_encoder
||
8430 connector
->new_encoder
->new_crtc
!= crtc
)
8433 connected_sink_compute_bpp(connector
, pipe_config
);
8439 static void intel_dump_crtc_timings(const struct drm_display_mode
*mode
)
8441 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8442 "type: 0x%x flags: 0x%x\n",
8444 mode
->crtc_hdisplay
, mode
->crtc_hsync_start
,
8445 mode
->crtc_hsync_end
, mode
->crtc_htotal
,
8446 mode
->crtc_vdisplay
, mode
->crtc_vsync_start
,
8447 mode
->crtc_vsync_end
, mode
->crtc_vtotal
, mode
->type
, mode
->flags
);
8450 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
8451 struct intel_crtc_config
*pipe_config
,
8452 const char *context
)
8454 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc
->base
.base
.id
,
8455 context
, pipe_name(crtc
->pipe
));
8457 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config
->cpu_transcoder
));
8458 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8459 pipe_config
->pipe_bpp
, pipe_config
->dither
);
8460 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8461 pipe_config
->has_pch_encoder
,
8462 pipe_config
->fdi_lanes
,
8463 pipe_config
->fdi_m_n
.gmch_m
, pipe_config
->fdi_m_n
.gmch_n
,
8464 pipe_config
->fdi_m_n
.link_m
, pipe_config
->fdi_m_n
.link_n
,
8465 pipe_config
->fdi_m_n
.tu
);
8466 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8467 pipe_config
->has_dp_encoder
,
8468 pipe_config
->dp_m_n
.gmch_m
, pipe_config
->dp_m_n
.gmch_n
,
8469 pipe_config
->dp_m_n
.link_m
, pipe_config
->dp_m_n
.link_n
,
8470 pipe_config
->dp_m_n
.tu
);
8471 DRM_DEBUG_KMS("requested mode:\n");
8472 drm_mode_debug_printmodeline(&pipe_config
->requested_mode
);
8473 DRM_DEBUG_KMS("adjusted mode:\n");
8474 drm_mode_debug_printmodeline(&pipe_config
->adjusted_mode
);
8475 intel_dump_crtc_timings(&pipe_config
->adjusted_mode
);
8476 DRM_DEBUG_KMS("port clock: %d\n", pipe_config
->port_clock
);
8477 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8478 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
8479 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8480 pipe_config
->gmch_pfit
.control
,
8481 pipe_config
->gmch_pfit
.pgm_ratios
,
8482 pipe_config
->gmch_pfit
.lvds_border_bits
);
8483 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
8484 pipe_config
->pch_pfit
.pos
,
8485 pipe_config
->pch_pfit
.size
,
8486 pipe_config
->pch_pfit
.enabled
? "enabled" : "disabled");
8487 DRM_DEBUG_KMS("ips: %i\n", pipe_config
->ips_enabled
);
8488 DRM_DEBUG_KMS("double wide: %i\n", pipe_config
->double_wide
);
8491 static bool check_encoder_cloning(struct drm_crtc
*crtc
)
8493 int num_encoders
= 0;
8494 bool uncloneable_encoders
= false;
8495 struct intel_encoder
*encoder
;
8497 list_for_each_entry(encoder
, &crtc
->dev
->mode_config
.encoder_list
,
8499 if (&encoder
->new_crtc
->base
!= crtc
)
8503 if (!encoder
->cloneable
)
8504 uncloneable_encoders
= true;
8507 return !(num_encoders
> 1 && uncloneable_encoders
);
8510 static struct intel_crtc_config
*
8511 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
8512 struct drm_framebuffer
*fb
,
8513 struct drm_display_mode
*mode
)
8515 struct drm_device
*dev
= crtc
->dev
;
8516 struct intel_encoder
*encoder
;
8517 struct intel_crtc_config
*pipe_config
;
8518 int plane_bpp
, ret
= -EINVAL
;
8521 if (!check_encoder_cloning(crtc
)) {
8522 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8523 return ERR_PTR(-EINVAL
);
8526 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
8528 return ERR_PTR(-ENOMEM
);
8530 drm_mode_copy(&pipe_config
->adjusted_mode
, mode
);
8531 drm_mode_copy(&pipe_config
->requested_mode
, mode
);
8533 pipe_config
->cpu_transcoder
=
8534 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
8535 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
8538 * Sanitize sync polarity flags based on requested ones. If neither
8539 * positive or negative polarity is requested, treat this as meaning
8540 * negative polarity.
8542 if (!(pipe_config
->adjusted_mode
.flags
&
8543 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
8544 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
8546 if (!(pipe_config
->adjusted_mode
.flags
&
8547 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
8548 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
8550 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8551 * plane pixel format and any sink constraints into account. Returns the
8552 * source plane bpp so that dithering can be selected on mismatches
8553 * after encoders and crtc also have had their say. */
8554 plane_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
8560 * Determine the real pipe dimensions. Note that stereo modes can
8561 * increase the actual pipe size due to the frame doubling and
8562 * insertion of additional space for blanks between the frame. This
8563 * is stored in the crtc timings. We use the requested mode to do this
8564 * computation to clearly distinguish it from the adjusted mode, which
8565 * can be changed by the connectors in the below retry loop.
8567 drm_mode_set_crtcinfo(&pipe_config
->requested_mode
, CRTC_STEREO_DOUBLE
);
8568 pipe_config
->pipe_src_w
= pipe_config
->requested_mode
.crtc_hdisplay
;
8569 pipe_config
->pipe_src_h
= pipe_config
->requested_mode
.crtc_vdisplay
;
8572 /* Ensure the port clock defaults are reset when retrying. */
8573 pipe_config
->port_clock
= 0;
8574 pipe_config
->pixel_multiplier
= 1;
8576 /* Fill in default crtc timings, allow encoders to overwrite them. */
8577 drm_mode_set_crtcinfo(&pipe_config
->adjusted_mode
, CRTC_STEREO_DOUBLE
);
8579 /* Pass our mode to the connectors and the CRTC to give them a chance to
8580 * adjust it according to limitations or connector properties, and also
8581 * a chance to reject the mode entirely.
8583 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8586 if (&encoder
->new_crtc
->base
!= crtc
)
8589 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
8590 DRM_DEBUG_KMS("Encoder config failure\n");
8595 /* Set default port clock if not overwritten by the encoder. Needs to be
8596 * done afterwards in case the encoder adjusts the mode. */
8597 if (!pipe_config
->port_clock
)
8598 pipe_config
->port_clock
= pipe_config
->adjusted_mode
.crtc_clock
8599 * pipe_config
->pixel_multiplier
;
8601 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
8603 DRM_DEBUG_KMS("CRTC fixup failed\n");
8608 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
8613 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8618 pipe_config
->dither
= pipe_config
->pipe_bpp
!= plane_bpp
;
8619 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8620 plane_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
8625 return ERR_PTR(ret
);
8628 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
8629 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8631 intel_modeset_affected_pipes(struct drm_crtc
*crtc
, unsigned *modeset_pipes
,
8632 unsigned *prepare_pipes
, unsigned *disable_pipes
)
8634 struct intel_crtc
*intel_crtc
;
8635 struct drm_device
*dev
= crtc
->dev
;
8636 struct intel_encoder
*encoder
;
8637 struct intel_connector
*connector
;
8638 struct drm_crtc
*tmp_crtc
;
8640 *disable_pipes
= *modeset_pipes
= *prepare_pipes
= 0;
8642 /* Check which crtcs have changed outputs connected to them, these need
8643 * to be part of the prepare_pipes mask. We don't (yet) support global
8644 * modeset across multiple crtcs, so modeset_pipes will only have one
8645 * bit set at most. */
8646 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8648 if (connector
->base
.encoder
== &connector
->new_encoder
->base
)
8651 if (connector
->base
.encoder
) {
8652 tmp_crtc
= connector
->base
.encoder
->crtc
;
8654 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
8657 if (connector
->new_encoder
)
8659 1 << connector
->new_encoder
->new_crtc
->pipe
;
8662 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8664 if (encoder
->base
.crtc
== &encoder
->new_crtc
->base
)
8667 if (encoder
->base
.crtc
) {
8668 tmp_crtc
= encoder
->base
.crtc
;
8670 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
8673 if (encoder
->new_crtc
)
8674 *prepare_pipes
|= 1 << encoder
->new_crtc
->pipe
;
8677 /* Check for any pipes that will be fully disabled ... */
8678 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
8682 /* Don't try to disable disabled crtcs. */
8683 if (!intel_crtc
->base
.enabled
)
8686 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8688 if (encoder
->new_crtc
== intel_crtc
)
8693 *disable_pipes
|= 1 << intel_crtc
->pipe
;
8697 /* set_mode is also used to update properties on life display pipes. */
8698 intel_crtc
= to_intel_crtc(crtc
);
8700 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
8703 * For simplicity do a full modeset on any pipe where the output routing
8704 * changed. We could be more clever, but that would require us to be
8705 * more careful with calling the relevant encoder->mode_set functions.
8708 *modeset_pipes
= *prepare_pipes
;
8710 /* ... and mask these out. */
8711 *modeset_pipes
&= ~(*disable_pipes
);
8712 *prepare_pipes
&= ~(*disable_pipes
);
8715 * HACK: We don't (yet) fully support global modesets. intel_set_config
8716 * obies this rule, but the modeset restore mode of
8717 * intel_modeset_setup_hw_state does not.
8719 *modeset_pipes
&= 1 << intel_crtc
->pipe
;
8720 *prepare_pipes
&= 1 << intel_crtc
->pipe
;
8722 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8723 *modeset_pipes
, *prepare_pipes
, *disable_pipes
);
8726 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
8728 struct drm_encoder
*encoder
;
8729 struct drm_device
*dev
= crtc
->dev
;
8731 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
8732 if (encoder
->crtc
== crtc
)
8739 intel_modeset_update_state(struct drm_device
*dev
, unsigned prepare_pipes
)
8741 struct intel_encoder
*intel_encoder
;
8742 struct intel_crtc
*intel_crtc
;
8743 struct drm_connector
*connector
;
8745 list_for_each_entry(intel_encoder
, &dev
->mode_config
.encoder_list
,
8747 if (!intel_encoder
->base
.crtc
)
8750 intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
8752 if (prepare_pipes
& (1 << intel_crtc
->pipe
))
8753 intel_encoder
->connectors_active
= false;
8756 intel_modeset_commit_output_state(dev
);
8758 /* Update computed state. */
8759 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
8761 intel_crtc
->base
.enabled
= intel_crtc_in_use(&intel_crtc
->base
);
8764 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
8765 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
8768 intel_crtc
= to_intel_crtc(connector
->encoder
->crtc
);
8770 if (prepare_pipes
& (1 << intel_crtc
->pipe
)) {
8771 struct drm_property
*dpms_property
=
8772 dev
->mode_config
.dpms_property
;
8774 connector
->dpms
= DRM_MODE_DPMS_ON
;
8775 drm_object_property_set_value(&connector
->base
,
8779 intel_encoder
= to_intel_encoder(connector
->encoder
);
8780 intel_encoder
->connectors_active
= true;
8786 static bool intel_fuzzy_clock_check(int clock1
, int clock2
)
8790 if (clock1
== clock2
)
8793 if (!clock1
|| !clock2
)
8796 diff
= abs(clock1
- clock2
);
8798 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
8804 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8805 list_for_each_entry((intel_crtc), \
8806 &(dev)->mode_config.crtc_list, \
8808 if (mask & (1 <<(intel_crtc)->pipe))
8811 intel_pipe_config_compare(struct drm_device
*dev
,
8812 struct intel_crtc_config
*current_config
,
8813 struct intel_crtc_config
*pipe_config
)
8815 #define PIPE_CONF_CHECK_X(name) \
8816 if (current_config->name != pipe_config->name) { \
8817 DRM_ERROR("mismatch in " #name " " \
8818 "(expected 0x%08x, found 0x%08x)\n", \
8819 current_config->name, \
8820 pipe_config->name); \
8824 #define PIPE_CONF_CHECK_I(name) \
8825 if (current_config->name != pipe_config->name) { \
8826 DRM_ERROR("mismatch in " #name " " \
8827 "(expected %i, found %i)\n", \
8828 current_config->name, \
8829 pipe_config->name); \
8833 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
8834 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8835 DRM_ERROR("mismatch in " #name "(" #mask ") " \
8836 "(expected %i, found %i)\n", \
8837 current_config->name & (mask), \
8838 pipe_config->name & (mask)); \
8842 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
8843 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
8844 DRM_ERROR("mismatch in " #name " " \
8845 "(expected %i, found %i)\n", \
8846 current_config->name, \
8847 pipe_config->name); \
8851 #define PIPE_CONF_QUIRK(quirk) \
8852 ((current_config->quirks | pipe_config->quirks) & (quirk))
8854 PIPE_CONF_CHECK_I(cpu_transcoder
);
8856 PIPE_CONF_CHECK_I(has_pch_encoder
);
8857 PIPE_CONF_CHECK_I(fdi_lanes
);
8858 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_m
);
8859 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_n
);
8860 PIPE_CONF_CHECK_I(fdi_m_n
.link_m
);
8861 PIPE_CONF_CHECK_I(fdi_m_n
.link_n
);
8862 PIPE_CONF_CHECK_I(fdi_m_n
.tu
);
8864 PIPE_CONF_CHECK_I(has_dp_encoder
);
8865 PIPE_CONF_CHECK_I(dp_m_n
.gmch_m
);
8866 PIPE_CONF_CHECK_I(dp_m_n
.gmch_n
);
8867 PIPE_CONF_CHECK_I(dp_m_n
.link_m
);
8868 PIPE_CONF_CHECK_I(dp_m_n
.link_n
);
8869 PIPE_CONF_CHECK_I(dp_m_n
.tu
);
8871 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hdisplay
);
8872 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_htotal
);
8873 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_start
);
8874 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_end
);
8875 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_start
);
8876 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_end
);
8878 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vdisplay
);
8879 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vtotal
);
8880 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_start
);
8881 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_end
);
8882 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_start
);
8883 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_end
);
8885 PIPE_CONF_CHECK_I(pixel_multiplier
);
8887 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8888 DRM_MODE_FLAG_INTERLACE
);
8890 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
8891 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8892 DRM_MODE_FLAG_PHSYNC
);
8893 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8894 DRM_MODE_FLAG_NHSYNC
);
8895 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8896 DRM_MODE_FLAG_PVSYNC
);
8897 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8898 DRM_MODE_FLAG_NVSYNC
);
8901 PIPE_CONF_CHECK_I(pipe_src_w
);
8902 PIPE_CONF_CHECK_I(pipe_src_h
);
8904 PIPE_CONF_CHECK_I(gmch_pfit
.control
);
8905 /* pfit ratios are autocomputed by the hw on gen4+ */
8906 if (INTEL_INFO(dev
)->gen
< 4)
8907 PIPE_CONF_CHECK_I(gmch_pfit
.pgm_ratios
);
8908 PIPE_CONF_CHECK_I(gmch_pfit
.lvds_border_bits
);
8909 PIPE_CONF_CHECK_I(pch_pfit
.enabled
);
8910 if (current_config
->pch_pfit
.enabled
) {
8911 PIPE_CONF_CHECK_I(pch_pfit
.pos
);
8912 PIPE_CONF_CHECK_I(pch_pfit
.size
);
8915 PIPE_CONF_CHECK_I(ips_enabled
);
8917 PIPE_CONF_CHECK_I(double_wide
);
8919 PIPE_CONF_CHECK_I(shared_dpll
);
8920 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
8921 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
8922 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
8923 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
8925 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5)
8926 PIPE_CONF_CHECK_I(pipe_bpp
);
8928 if (!IS_HASWELL(dev
)) {
8929 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode
.crtc_clock
);
8930 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
8933 #undef PIPE_CONF_CHECK_X
8934 #undef PIPE_CONF_CHECK_I
8935 #undef PIPE_CONF_CHECK_FLAGS
8936 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
8937 #undef PIPE_CONF_QUIRK
8943 check_connector_state(struct drm_device
*dev
)
8945 struct intel_connector
*connector
;
8947 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8949 /* This also checks the encoder/connector hw state with the
8950 * ->get_hw_state callbacks. */
8951 intel_connector_check_state(connector
);
8953 WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
8954 "connector's staged encoder doesn't match current encoder\n");
8959 check_encoder_state(struct drm_device
*dev
)
8961 struct intel_encoder
*encoder
;
8962 struct intel_connector
*connector
;
8964 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8966 bool enabled
= false;
8967 bool active
= false;
8968 enum pipe pipe
, tracked_pipe
;
8970 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8971 encoder
->base
.base
.id
,
8972 drm_get_encoder_name(&encoder
->base
));
8974 WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
8975 "encoder's stage crtc doesn't match current crtc\n");
8976 WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
8977 "encoder's active_connectors set, but no crtc\n");
8979 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8981 if (connector
->base
.encoder
!= &encoder
->base
)
8984 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
8987 WARN(!!encoder
->base
.crtc
!= enabled
,
8988 "encoder's enabled state mismatch "
8989 "(expected %i, found %i)\n",
8990 !!encoder
->base
.crtc
, enabled
);
8991 WARN(active
&& !encoder
->base
.crtc
,
8992 "active encoder with no crtc\n");
8994 WARN(encoder
->connectors_active
!= active
,
8995 "encoder's computed active state doesn't match tracked active state "
8996 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
8998 active
= encoder
->get_hw_state(encoder
, &pipe
);
8999 WARN(active
!= encoder
->connectors_active
,
9000 "encoder's hw state doesn't match sw tracking "
9001 "(expected %i, found %i)\n",
9002 encoder
->connectors_active
, active
);
9004 if (!encoder
->base
.crtc
)
9007 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
9008 WARN(active
&& pipe
!= tracked_pipe
,
9009 "active encoder's pipe doesn't match"
9010 "(expected %i, found %i)\n",
9011 tracked_pipe
, pipe
);
9017 check_crtc_state(struct drm_device
*dev
)
9019 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
9020 struct intel_crtc
*crtc
;
9021 struct intel_encoder
*encoder
;
9022 struct intel_crtc_config pipe_config
;
9024 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
9026 bool enabled
= false;
9027 bool active
= false;
9029 memset(&pipe_config
, 0, sizeof(pipe_config
));
9031 DRM_DEBUG_KMS("[CRTC:%d]\n",
9032 crtc
->base
.base
.id
);
9034 WARN(crtc
->active
&& !crtc
->base
.enabled
,
9035 "active crtc, but not enabled in sw tracking\n");
9037 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9039 if (encoder
->base
.crtc
!= &crtc
->base
)
9042 if (encoder
->connectors_active
)
9046 WARN(active
!= crtc
->active
,
9047 "crtc's computed active state doesn't match tracked active state "
9048 "(expected %i, found %i)\n", active
, crtc
->active
);
9049 WARN(enabled
!= crtc
->base
.enabled
,
9050 "crtc's computed enabled state doesn't match tracked enabled state "
9051 "(expected %i, found %i)\n", enabled
, crtc
->base
.enabled
);
9053 active
= dev_priv
->display
.get_pipe_config(crtc
,
9056 /* hw state is inconsistent with the pipe A quirk */
9057 if (crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
9058 active
= crtc
->active
;
9060 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9063 if (encoder
->base
.crtc
!= &crtc
->base
)
9065 if (encoder
->get_config
&&
9066 encoder
->get_hw_state(encoder
, &pipe
))
9067 encoder
->get_config(encoder
, &pipe_config
);
9070 WARN(crtc
->active
!= active
,
9071 "crtc active state doesn't match with hw state "
9072 "(expected %i, found %i)\n", crtc
->active
, active
);
9075 !intel_pipe_config_compare(dev
, &crtc
->config
, &pipe_config
)) {
9076 WARN(1, "pipe state doesn't match!\n");
9077 intel_dump_pipe_config(crtc
, &pipe_config
,
9079 intel_dump_pipe_config(crtc
, &crtc
->config
,
9086 check_shared_dpll_state(struct drm_device
*dev
)
9088 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
9089 struct intel_crtc
*crtc
;
9090 struct intel_dpll_hw_state dpll_hw_state
;
9093 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
9094 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
9095 int enabled_crtcs
= 0, active_crtcs
= 0;
9098 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
9100 DRM_DEBUG_KMS("%s\n", pll
->name
);
9102 active
= pll
->get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
9104 WARN(pll
->active
> pll
->refcount
,
9105 "more active pll users than references: %i vs %i\n",
9106 pll
->active
, pll
->refcount
);
9107 WARN(pll
->active
&& !pll
->on
,
9108 "pll in active use but not on in sw tracking\n");
9109 WARN(pll
->on
&& !pll
->active
,
9110 "pll in on but not on in use in sw tracking\n");
9111 WARN(pll
->on
!= active
,
9112 "pll on state mismatch (expected %i, found %i)\n",
9115 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
9117 if (crtc
->base
.enabled
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
9119 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
9122 WARN(pll
->active
!= active_crtcs
,
9123 "pll active crtcs mismatch (expected %i, found %i)\n",
9124 pll
->active
, active_crtcs
);
9125 WARN(pll
->refcount
!= enabled_crtcs
,
9126 "pll enabled crtcs mismatch (expected %i, found %i)\n",
9127 pll
->refcount
, enabled_crtcs
);
9129 WARN(pll
->on
&& memcmp(&pll
->hw_state
, &dpll_hw_state
,
9130 sizeof(dpll_hw_state
)),
9131 "pll hw state mismatch\n");
9136 intel_modeset_check_state(struct drm_device
*dev
)
9138 check_connector_state(dev
);
9139 check_encoder_state(dev
);
9140 check_crtc_state(dev
);
9141 check_shared_dpll_state(dev
);
9144 void ironlake_check_encoder_dotclock(const struct intel_crtc_config
*pipe_config
,
9148 * FDI already provided one idea for the dotclock.
9149 * Yell if the encoder disagrees.
9151 WARN(!intel_fuzzy_clock_check(pipe_config
->adjusted_mode
.crtc_clock
, dotclock
),
9152 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9153 pipe_config
->adjusted_mode
.crtc_clock
, dotclock
);
9156 static int __intel_set_mode(struct drm_crtc
*crtc
,
9157 struct drm_display_mode
*mode
,
9158 int x
, int y
, struct drm_framebuffer
*fb
)
9160 struct drm_device
*dev
= crtc
->dev
;
9161 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
9162 struct drm_display_mode
*saved_mode
, *saved_hwmode
;
9163 struct intel_crtc_config
*pipe_config
= NULL
;
9164 struct intel_crtc
*intel_crtc
;
9165 unsigned disable_pipes
, prepare_pipes
, modeset_pipes
;
9168 saved_mode
= kcalloc(2, sizeof(*saved_mode
), GFP_KERNEL
);
9171 saved_hwmode
= saved_mode
+ 1;
9173 intel_modeset_affected_pipes(crtc
, &modeset_pipes
,
9174 &prepare_pipes
, &disable_pipes
);
9176 *saved_hwmode
= crtc
->hwmode
;
9177 *saved_mode
= crtc
->mode
;
9179 /* Hack: Because we don't (yet) support global modeset on multiple
9180 * crtcs, we don't keep track of the new mode for more than one crtc.
9181 * Hence simply check whether any bit is set in modeset_pipes in all the
9182 * pieces of code that are not yet converted to deal with mutliple crtcs
9183 * changing their mode at the same time. */
9184 if (modeset_pipes
) {
9185 pipe_config
= intel_modeset_pipe_config(crtc
, fb
, mode
);
9186 if (IS_ERR(pipe_config
)) {
9187 ret
= PTR_ERR(pipe_config
);
9192 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,
9196 for_each_intel_crtc_masked(dev
, disable_pipes
, intel_crtc
)
9197 intel_crtc_disable(&intel_crtc
->base
);
9199 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
9200 if (intel_crtc
->base
.enabled
)
9201 dev_priv
->display
.crtc_disable(&intel_crtc
->base
);
9204 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9205 * to set it here already despite that we pass it down the callchain.
9207 if (modeset_pipes
) {
9209 /* mode_set/enable/disable functions rely on a correct pipe
9211 to_intel_crtc(crtc
)->config
= *pipe_config
;
9214 /* Only after disabling all output pipelines that will be changed can we
9215 * update the the output configuration. */
9216 intel_modeset_update_state(dev
, prepare_pipes
);
9218 if (dev_priv
->display
.modeset_global_resources
)
9219 dev_priv
->display
.modeset_global_resources(dev
);
9221 /* Set up the DPLL and any encoders state that needs to adjust or depend
9224 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
9225 ret
= intel_crtc_mode_set(&intel_crtc
->base
,
9231 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9232 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
)
9233 dev_priv
->display
.crtc_enable(&intel_crtc
->base
);
9235 if (modeset_pipes
) {
9236 /* Store real post-adjustment hardware mode. */
9237 crtc
->hwmode
= pipe_config
->adjusted_mode
;
9239 /* Calculate and store various constants which
9240 * are later needed by vblank and swap-completion
9241 * timestamping. They are derived from true hwmode.
9243 drm_calc_timestamping_constants(crtc
);
9246 /* FIXME: add subpixel order */
9248 if (ret
&& crtc
->enabled
) {
9249 crtc
->hwmode
= *saved_hwmode
;
9250 crtc
->mode
= *saved_mode
;
9259 static int intel_set_mode(struct drm_crtc
*crtc
,
9260 struct drm_display_mode
*mode
,
9261 int x
, int y
, struct drm_framebuffer
*fb
)
9265 ret
= __intel_set_mode(crtc
, mode
, x
, y
, fb
);
9268 intel_modeset_check_state(crtc
->dev
);
9273 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
9275 intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
, crtc
->fb
);
9278 #undef for_each_intel_crtc_masked
9280 static void intel_set_config_free(struct intel_set_config
*config
)
9285 kfree(config
->save_connector_encoders
);
9286 kfree(config
->save_encoder_crtcs
);
9290 static int intel_set_config_save_state(struct drm_device
*dev
,
9291 struct intel_set_config
*config
)
9293 struct drm_encoder
*encoder
;
9294 struct drm_connector
*connector
;
9297 config
->save_encoder_crtcs
=
9298 kcalloc(dev
->mode_config
.num_encoder
,
9299 sizeof(struct drm_crtc
*), GFP_KERNEL
);
9300 if (!config
->save_encoder_crtcs
)
9303 config
->save_connector_encoders
=
9304 kcalloc(dev
->mode_config
.num_connector
,
9305 sizeof(struct drm_encoder
*), GFP_KERNEL
);
9306 if (!config
->save_connector_encoders
)
9309 /* Copy data. Note that driver private data is not affected.
9310 * Should anything bad happen only the expected state is
9311 * restored, not the drivers personal bookkeeping.
9314 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
9315 config
->save_encoder_crtcs
[count
++] = encoder
->crtc
;
9319 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
9320 config
->save_connector_encoders
[count
++] = connector
->encoder
;
9326 static void intel_set_config_restore_state(struct drm_device
*dev
,
9327 struct intel_set_config
*config
)
9329 struct intel_encoder
*encoder
;
9330 struct intel_connector
*connector
;
9334 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
9336 to_intel_crtc(config
->save_encoder_crtcs
[count
++]);
9340 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
9341 connector
->new_encoder
=
9342 to_intel_encoder(config
->save_connector_encoders
[count
++]);
9347 is_crtc_connector_off(struct drm_mode_set
*set
)
9351 if (set
->num_connectors
== 0)
9354 if (WARN_ON(set
->connectors
== NULL
))
9357 for (i
= 0; i
< set
->num_connectors
; i
++)
9358 if (set
->connectors
[i
]->encoder
&&
9359 set
->connectors
[i
]->encoder
->crtc
== set
->crtc
&&
9360 set
->connectors
[i
]->dpms
!= DRM_MODE_DPMS_ON
)
9367 intel_set_config_compute_mode_changes(struct drm_mode_set
*set
,
9368 struct intel_set_config
*config
)
9371 /* We should be able to check here if the fb has the same properties
9372 * and then just flip_or_move it */
9373 if (is_crtc_connector_off(set
)) {
9374 config
->mode_changed
= true;
9375 } else if (set
->crtc
->fb
!= set
->fb
) {
9376 /* If we have no fb then treat it as a full mode set */
9377 if (set
->crtc
->fb
== NULL
) {
9378 struct intel_crtc
*intel_crtc
=
9379 to_intel_crtc(set
->crtc
);
9381 if (intel_crtc
->active
&& i915_fastboot
) {
9382 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9383 config
->fb_changed
= true;
9385 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9386 config
->mode_changed
= true;
9388 } else if (set
->fb
== NULL
) {
9389 config
->mode_changed
= true;
9390 } else if (set
->fb
->pixel_format
!=
9391 set
->crtc
->fb
->pixel_format
) {
9392 config
->mode_changed
= true;
9394 config
->fb_changed
= true;
9398 if (set
->fb
&& (set
->x
!= set
->crtc
->x
|| set
->y
!= set
->crtc
->y
))
9399 config
->fb_changed
= true;
9401 if (set
->mode
&& !drm_mode_equal(set
->mode
, &set
->crtc
->mode
)) {
9402 DRM_DEBUG_KMS("modes are different, full mode set\n");
9403 drm_mode_debug_printmodeline(&set
->crtc
->mode
);
9404 drm_mode_debug_printmodeline(set
->mode
);
9405 config
->mode_changed
= true;
9408 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9409 set
->crtc
->base
.id
, config
->mode_changed
, config
->fb_changed
);
9413 intel_modeset_stage_output_state(struct drm_device
*dev
,
9414 struct drm_mode_set
*set
,
9415 struct intel_set_config
*config
)
9417 struct drm_crtc
*new_crtc
;
9418 struct intel_connector
*connector
;
9419 struct intel_encoder
*encoder
;
9422 /* The upper layers ensure that we either disable a crtc or have a list
9423 * of connectors. For paranoia, double-check this. */
9424 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
9425 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
9427 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9429 /* Otherwise traverse passed in connector list and get encoders
9431 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
9432 if (set
->connectors
[ro
] == &connector
->base
) {
9433 connector
->new_encoder
= connector
->encoder
;
9438 /* If we disable the crtc, disable all its connectors. Also, if
9439 * the connector is on the changing crtc but not on the new
9440 * connector list, disable it. */
9441 if ((!set
->fb
|| ro
== set
->num_connectors
) &&
9442 connector
->base
.encoder
&&
9443 connector
->base
.encoder
->crtc
== set
->crtc
) {
9444 connector
->new_encoder
= NULL
;
9446 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9447 connector
->base
.base
.id
,
9448 drm_get_connector_name(&connector
->base
));
9452 if (&connector
->new_encoder
->base
!= connector
->base
.encoder
) {
9453 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
9454 config
->mode_changed
= true;
9457 /* connector->new_encoder is now updated for all connectors. */
9459 /* Update crtc of enabled connectors. */
9460 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9462 if (!connector
->new_encoder
)
9465 new_crtc
= connector
->new_encoder
->base
.crtc
;
9467 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
9468 if (set
->connectors
[ro
] == &connector
->base
)
9469 new_crtc
= set
->crtc
;
9472 /* Make sure the new CRTC will work with the encoder */
9473 if (!intel_encoder_crtc_ok(&connector
->new_encoder
->base
,
9477 connector
->encoder
->new_crtc
= to_intel_crtc(new_crtc
);
9479 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9480 connector
->base
.base
.id
,
9481 drm_get_connector_name(&connector
->base
),
9485 /* Check for any encoders that needs to be disabled. */
9486 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9488 list_for_each_entry(connector
,
9489 &dev
->mode_config
.connector_list
,
9491 if (connector
->new_encoder
== encoder
) {
9492 WARN_ON(!connector
->new_encoder
->new_crtc
);
9497 encoder
->new_crtc
= NULL
;
9499 /* Only now check for crtc changes so we don't miss encoders
9500 * that will be disabled. */
9501 if (&encoder
->new_crtc
->base
!= encoder
->base
.crtc
) {
9502 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
9503 config
->mode_changed
= true;
9506 /* Now we've also updated encoder->new_crtc for all encoders. */
9511 static int intel_crtc_set_config(struct drm_mode_set
*set
)
9513 struct drm_device
*dev
;
9514 struct drm_mode_set save_set
;
9515 struct intel_set_config
*config
;
9520 BUG_ON(!set
->crtc
->helper_private
);
9522 /* Enforce sane interface api - has been abused by the fb helper. */
9523 BUG_ON(!set
->mode
&& set
->fb
);
9524 BUG_ON(set
->fb
&& set
->num_connectors
== 0);
9527 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9528 set
->crtc
->base
.id
, set
->fb
->base
.id
,
9529 (int)set
->num_connectors
, set
->x
, set
->y
);
9531 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
9534 dev
= set
->crtc
->dev
;
9537 config
= kzalloc(sizeof(*config
), GFP_KERNEL
);
9541 ret
= intel_set_config_save_state(dev
, config
);
9545 save_set
.crtc
= set
->crtc
;
9546 save_set
.mode
= &set
->crtc
->mode
;
9547 save_set
.x
= set
->crtc
->x
;
9548 save_set
.y
= set
->crtc
->y
;
9549 save_set
.fb
= set
->crtc
->fb
;
9551 /* Compute whether we need a full modeset, only an fb base update or no
9552 * change at all. In the future we might also check whether only the
9553 * mode changed, e.g. for LVDS where we only change the panel fitter in
9555 intel_set_config_compute_mode_changes(set
, config
);
9557 ret
= intel_modeset_stage_output_state(dev
, set
, config
);
9561 if (config
->mode_changed
) {
9562 ret
= intel_set_mode(set
->crtc
, set
->mode
,
9563 set
->x
, set
->y
, set
->fb
);
9564 } else if (config
->fb_changed
) {
9565 intel_crtc_wait_for_pending_flips(set
->crtc
);
9567 ret
= intel_pipe_set_base(set
->crtc
,
9568 set
->x
, set
->y
, set
->fb
);
9572 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9573 set
->crtc
->base
.id
, ret
);
9575 intel_set_config_restore_state(dev
, config
);
9577 /* Try to restore the config */
9578 if (config
->mode_changed
&&
9579 intel_set_mode(save_set
.crtc
, save_set
.mode
,
9580 save_set
.x
, save_set
.y
, save_set
.fb
))
9581 DRM_ERROR("failed to restore config after modeset failure\n");
9585 intel_set_config_free(config
);
9589 static const struct drm_crtc_funcs intel_crtc_funcs
= {
9590 .cursor_set
= intel_crtc_cursor_set
,
9591 .cursor_move
= intel_crtc_cursor_move
,
9592 .gamma_set
= intel_crtc_gamma_set
,
9593 .set_config
= intel_crtc_set_config
,
9594 .destroy
= intel_crtc_destroy
,
9595 .page_flip
= intel_crtc_page_flip
,
9598 static void intel_cpu_pll_init(struct drm_device
*dev
)
9601 intel_ddi_pll_init(dev
);
9604 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private
*dev_priv
,
9605 struct intel_shared_dpll
*pll
,
9606 struct intel_dpll_hw_state
*hw_state
)
9610 val
= I915_READ(PCH_DPLL(pll
->id
));
9611 hw_state
->dpll
= val
;
9612 hw_state
->fp0
= I915_READ(PCH_FP0(pll
->id
));
9613 hw_state
->fp1
= I915_READ(PCH_FP1(pll
->id
));
9615 return val
& DPLL_VCO_ENABLE
;
9618 static void ibx_pch_dpll_mode_set(struct drm_i915_private
*dev_priv
,
9619 struct intel_shared_dpll
*pll
)
9621 I915_WRITE(PCH_FP0(pll
->id
), pll
->hw_state
.fp0
);
9622 I915_WRITE(PCH_FP1(pll
->id
), pll
->hw_state
.fp1
);
9625 static void ibx_pch_dpll_enable(struct drm_i915_private
*dev_priv
,
9626 struct intel_shared_dpll
*pll
)
9628 /* PCH refclock must be enabled first */
9629 assert_pch_refclk_enabled(dev_priv
);
9631 I915_WRITE(PCH_DPLL(pll
->id
), pll
->hw_state
.dpll
);
9633 /* Wait for the clocks to stabilize. */
9634 POSTING_READ(PCH_DPLL(pll
->id
));
9637 /* The pixel multiplier can only be updated once the
9638 * DPLL is enabled and the clocks are stable.
9640 * So write it again.
9642 I915_WRITE(PCH_DPLL(pll
->id
), pll
->hw_state
.dpll
);
9643 POSTING_READ(PCH_DPLL(pll
->id
));
9647 static void ibx_pch_dpll_disable(struct drm_i915_private
*dev_priv
,
9648 struct intel_shared_dpll
*pll
)
9650 struct drm_device
*dev
= dev_priv
->dev
;
9651 struct intel_crtc
*crtc
;
9653 /* Make sure no transcoder isn't still depending on us. */
9654 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
9655 if (intel_crtc_to_shared_dpll(crtc
) == pll
)
9656 assert_pch_transcoder_disabled(dev_priv
, crtc
->pipe
);
9659 I915_WRITE(PCH_DPLL(pll
->id
), 0);
9660 POSTING_READ(PCH_DPLL(pll
->id
));
9664 static char *ibx_pch_dpll_names
[] = {
9669 static void ibx_pch_dpll_init(struct drm_device
*dev
)
9671 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9674 dev_priv
->num_shared_dpll
= 2;
9676 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
9677 dev_priv
->shared_dplls
[i
].id
= i
;
9678 dev_priv
->shared_dplls
[i
].name
= ibx_pch_dpll_names
[i
];
9679 dev_priv
->shared_dplls
[i
].mode_set
= ibx_pch_dpll_mode_set
;
9680 dev_priv
->shared_dplls
[i
].enable
= ibx_pch_dpll_enable
;
9681 dev_priv
->shared_dplls
[i
].disable
= ibx_pch_dpll_disable
;
9682 dev_priv
->shared_dplls
[i
].get_hw_state
=
9683 ibx_pch_dpll_get_hw_state
;
9687 static void intel_shared_dpll_init(struct drm_device
*dev
)
9689 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9691 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
9692 ibx_pch_dpll_init(dev
);
9694 dev_priv
->num_shared_dpll
= 0;
9696 BUG_ON(dev_priv
->num_shared_dpll
> I915_NUM_PLLS
);
9697 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9698 dev_priv
->num_shared_dpll
);
9701 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
9703 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
9704 struct intel_crtc
*intel_crtc
;
9707 intel_crtc
= kzalloc(sizeof(*intel_crtc
), GFP_KERNEL
);
9708 if (intel_crtc
== NULL
)
9711 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
9713 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
9714 for (i
= 0; i
< 256; i
++) {
9715 intel_crtc
->lut_r
[i
] = i
;
9716 intel_crtc
->lut_g
[i
] = i
;
9717 intel_crtc
->lut_b
[i
] = i
;
9720 /* Swap pipes & planes for FBC on pre-965 */
9721 intel_crtc
->pipe
= pipe
;
9722 intel_crtc
->plane
= pipe
;
9723 if (IS_MOBILE(dev
) && IS_GEN3(dev
)) {
9724 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
9725 intel_crtc
->plane
= !pipe
;
9728 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
9729 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
9730 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
9731 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
9733 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
9736 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
9737 struct drm_file
*file
)
9739 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
9740 struct drm_mode_object
*drmmode_obj
;
9741 struct intel_crtc
*crtc
;
9743 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
9746 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
9747 DRM_MODE_OBJECT_CRTC
);
9750 DRM_ERROR("no such CRTC id\n");
9754 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
9755 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
9760 static int intel_encoder_clones(struct intel_encoder
*encoder
)
9762 struct drm_device
*dev
= encoder
->base
.dev
;
9763 struct intel_encoder
*source_encoder
;
9767 list_for_each_entry(source_encoder
,
9768 &dev
->mode_config
.encoder_list
, base
.head
) {
9770 if (encoder
== source_encoder
)
9771 index_mask
|= (1 << entry
);
9773 /* Intel hw has only one MUX where enocoders could be cloned. */
9774 if (encoder
->cloneable
&& source_encoder
->cloneable
)
9775 index_mask
|= (1 << entry
);
9783 static bool has_edp_a(struct drm_device
*dev
)
9785 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9787 if (!IS_MOBILE(dev
))
9790 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
9794 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES
) & ILK_eDP_A_DISABLE
))
9800 static void intel_setup_outputs(struct drm_device
*dev
)
9802 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9803 struct intel_encoder
*encoder
;
9804 bool dpd_is_edp
= false;
9806 intel_lvds_init(dev
);
9809 intel_crt_init(dev
);
9814 /* Haswell uses DDI functions to detect digital outputs */
9815 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
9816 /* DDI A only supports eDP */
9818 intel_ddi_init(dev
, PORT_A
);
9820 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9822 found
= I915_READ(SFUSE_STRAP
);
9824 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
9825 intel_ddi_init(dev
, PORT_B
);
9826 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
9827 intel_ddi_init(dev
, PORT_C
);
9828 if (found
& SFUSE_STRAP_DDID_DETECTED
)
9829 intel_ddi_init(dev
, PORT_D
);
9830 } else if (HAS_PCH_SPLIT(dev
)) {
9832 dpd_is_edp
= intel_dpd_is_edp(dev
);
9835 intel_dp_init(dev
, DP_A
, PORT_A
);
9837 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
9838 /* PCH SDVOB multiplex with HDMIB */
9839 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
9841 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
9842 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
9843 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
9846 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
9847 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
9849 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
9850 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
9852 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
9853 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
9855 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
9856 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
9857 } else if (IS_VALLEYVIEW(dev
)) {
9858 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9859 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIC
) & SDVO_DETECTED
) {
9860 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIC
,
9862 if (I915_READ(VLV_DISPLAY_BASE
+ DP_C
) & DP_DETECTED
)
9863 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_C
,
9867 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIB
) & SDVO_DETECTED
) {
9868 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIB
,
9870 if (I915_READ(VLV_DISPLAY_BASE
+ DP_B
) & DP_DETECTED
)
9871 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_B
, PORT_B
);
9874 intel_dsi_init(dev
);
9875 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
9878 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
9879 DRM_DEBUG_KMS("probing SDVOB\n");
9880 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, true);
9881 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
9882 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9883 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
9886 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
))
9887 intel_dp_init(dev
, DP_B
, PORT_B
);
9890 /* Before G4X SDVOC doesn't have its own detect register */
9892 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
9893 DRM_DEBUG_KMS("probing SDVOC\n");
9894 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, false);
9897 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
9899 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
9900 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9901 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
9903 if (SUPPORTS_INTEGRATED_DP(dev
))
9904 intel_dp_init(dev
, DP_C
, PORT_C
);
9907 if (SUPPORTS_INTEGRATED_DP(dev
) &&
9908 (I915_READ(DP_D
) & DP_DETECTED
))
9909 intel_dp_init(dev
, DP_D
, PORT_D
);
9910 } else if (IS_GEN2(dev
))
9911 intel_dvo_init(dev
);
9913 if (SUPPORTS_TV(dev
))
9916 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
9917 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
9918 encoder
->base
.possible_clones
=
9919 intel_encoder_clones(encoder
);
9922 intel_init_pch_refclk(dev
);
9924 drm_helper_move_panel_connectors_to_head(dev
);
9927 void intel_framebuffer_fini(struct intel_framebuffer
*fb
)
9929 drm_framebuffer_cleanup(&fb
->base
);
9930 drm_gem_object_unreference_unlocked(&fb
->obj
->base
);
9933 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
9935 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
9937 intel_framebuffer_fini(intel_fb
);
9941 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
9942 struct drm_file
*file
,
9943 unsigned int *handle
)
9945 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
9946 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
9948 return drm_gem_handle_create(file
, &obj
->base
, handle
);
9951 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
9952 .destroy
= intel_user_framebuffer_destroy
,
9953 .create_handle
= intel_user_framebuffer_create_handle
,
9956 int intel_framebuffer_init(struct drm_device
*dev
,
9957 struct intel_framebuffer
*intel_fb
,
9958 struct drm_mode_fb_cmd2
*mode_cmd
,
9959 struct drm_i915_gem_object
*obj
)
9964 if (obj
->tiling_mode
== I915_TILING_Y
) {
9965 DRM_DEBUG("hardware does not support tiling Y\n");
9969 if (mode_cmd
->pitches
[0] & 63) {
9970 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9971 mode_cmd
->pitches
[0]);
9975 if (INTEL_INFO(dev
)->gen
>= 5 && !IS_VALLEYVIEW(dev
)) {
9976 pitch_limit
= 32*1024;
9977 } else if (INTEL_INFO(dev
)->gen
>= 4) {
9978 if (obj
->tiling_mode
)
9979 pitch_limit
= 16*1024;
9981 pitch_limit
= 32*1024;
9982 } else if (INTEL_INFO(dev
)->gen
>= 3) {
9983 if (obj
->tiling_mode
)
9984 pitch_limit
= 8*1024;
9986 pitch_limit
= 16*1024;
9988 /* XXX DSPC is limited to 4k tiled */
9989 pitch_limit
= 8*1024;
9991 if (mode_cmd
->pitches
[0] > pitch_limit
) {
9992 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9993 obj
->tiling_mode
? "tiled" : "linear",
9994 mode_cmd
->pitches
[0], pitch_limit
);
9998 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
9999 mode_cmd
->pitches
[0] != obj
->stride
) {
10000 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10001 mode_cmd
->pitches
[0], obj
->stride
);
10005 /* Reject formats not supported by any plane early. */
10006 switch (mode_cmd
->pixel_format
) {
10007 case DRM_FORMAT_C8
:
10008 case DRM_FORMAT_RGB565
:
10009 case DRM_FORMAT_XRGB8888
:
10010 case DRM_FORMAT_ARGB8888
:
10012 case DRM_FORMAT_XRGB1555
:
10013 case DRM_FORMAT_ARGB1555
:
10014 if (INTEL_INFO(dev
)->gen
> 3) {
10015 DRM_DEBUG("unsupported pixel format: %s\n",
10016 drm_get_format_name(mode_cmd
->pixel_format
));
10020 case DRM_FORMAT_XBGR8888
:
10021 case DRM_FORMAT_ABGR8888
:
10022 case DRM_FORMAT_XRGB2101010
:
10023 case DRM_FORMAT_ARGB2101010
:
10024 case DRM_FORMAT_XBGR2101010
:
10025 case DRM_FORMAT_ABGR2101010
:
10026 if (INTEL_INFO(dev
)->gen
< 4) {
10027 DRM_DEBUG("unsupported pixel format: %s\n",
10028 drm_get_format_name(mode_cmd
->pixel_format
));
10032 case DRM_FORMAT_YUYV
:
10033 case DRM_FORMAT_UYVY
:
10034 case DRM_FORMAT_YVYU
:
10035 case DRM_FORMAT_VYUY
:
10036 if (INTEL_INFO(dev
)->gen
< 5) {
10037 DRM_DEBUG("unsupported pixel format: %s\n",
10038 drm_get_format_name(mode_cmd
->pixel_format
));
10043 DRM_DEBUG("unsupported pixel format: %s\n",
10044 drm_get_format_name(mode_cmd
->pixel_format
));
10048 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10049 if (mode_cmd
->offsets
[0] != 0)
10052 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
10053 intel_fb
->obj
= obj
;
10055 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
10057 DRM_ERROR("framebuffer init failed %d\n", ret
);
10064 static struct drm_framebuffer
*
10065 intel_user_framebuffer_create(struct drm_device
*dev
,
10066 struct drm_file
*filp
,
10067 struct drm_mode_fb_cmd2
*mode_cmd
)
10069 struct drm_i915_gem_object
*obj
;
10071 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
10072 mode_cmd
->handles
[0]));
10073 if (&obj
->base
== NULL
)
10074 return ERR_PTR(-ENOENT
);
10076 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
10079 static const struct drm_mode_config_funcs intel_mode_funcs
= {
10080 .fb_create
= intel_user_framebuffer_create
,
10081 .output_poll_changed
= intel_fb_output_poll_changed
,
10084 /* Set up chip specific display functions */
10085 static void intel_init_display(struct drm_device
*dev
)
10087 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10089 if (HAS_PCH_SPLIT(dev
) || IS_G4X(dev
))
10090 dev_priv
->display
.find_dpll
= g4x_find_best_dpll
;
10091 else if (IS_VALLEYVIEW(dev
))
10092 dev_priv
->display
.find_dpll
= vlv_find_best_dpll
;
10093 else if (IS_PINEVIEW(dev
))
10094 dev_priv
->display
.find_dpll
= pnv_find_best_dpll
;
10096 dev_priv
->display
.find_dpll
= i9xx_find_best_dpll
;
10098 if (HAS_DDI(dev
)) {
10099 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
10100 dev_priv
->display
.crtc_mode_set
= haswell_crtc_mode_set
;
10101 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
10102 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
10103 dev_priv
->display
.off
= haswell_crtc_off
;
10104 dev_priv
->display
.update_plane
= ironlake_update_plane
;
10105 } else if (HAS_PCH_SPLIT(dev
)) {
10106 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
10107 dev_priv
->display
.crtc_mode_set
= ironlake_crtc_mode_set
;
10108 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
10109 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
10110 dev_priv
->display
.off
= ironlake_crtc_off
;
10111 dev_priv
->display
.update_plane
= ironlake_update_plane
;
10112 } else if (IS_VALLEYVIEW(dev
)) {
10113 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
10114 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
10115 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
10116 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
10117 dev_priv
->display
.off
= i9xx_crtc_off
;
10118 dev_priv
->display
.update_plane
= i9xx_update_plane
;
10120 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
10121 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
10122 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
10123 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
10124 dev_priv
->display
.off
= i9xx_crtc_off
;
10125 dev_priv
->display
.update_plane
= i9xx_update_plane
;
10128 /* Returns the core display clock speed */
10129 if (IS_VALLEYVIEW(dev
))
10130 dev_priv
->display
.get_display_clock_speed
=
10131 valleyview_get_display_clock_speed
;
10132 else if (IS_I945G(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
10133 dev_priv
->display
.get_display_clock_speed
=
10134 i945_get_display_clock_speed
;
10135 else if (IS_I915G(dev
))
10136 dev_priv
->display
.get_display_clock_speed
=
10137 i915_get_display_clock_speed
;
10138 else if (IS_I945GM(dev
) || IS_845G(dev
))
10139 dev_priv
->display
.get_display_clock_speed
=
10140 i9xx_misc_get_display_clock_speed
;
10141 else if (IS_PINEVIEW(dev
))
10142 dev_priv
->display
.get_display_clock_speed
=
10143 pnv_get_display_clock_speed
;
10144 else if (IS_I915GM(dev
))
10145 dev_priv
->display
.get_display_clock_speed
=
10146 i915gm_get_display_clock_speed
;
10147 else if (IS_I865G(dev
))
10148 dev_priv
->display
.get_display_clock_speed
=
10149 i865_get_display_clock_speed
;
10150 else if (IS_I85X(dev
))
10151 dev_priv
->display
.get_display_clock_speed
=
10152 i855_get_display_clock_speed
;
10153 else /* 852, 830 */
10154 dev_priv
->display
.get_display_clock_speed
=
10155 i830_get_display_clock_speed
;
10157 if (HAS_PCH_SPLIT(dev
)) {
10158 if (IS_GEN5(dev
)) {
10159 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
10160 dev_priv
->display
.write_eld
= ironlake_write_eld
;
10161 } else if (IS_GEN6(dev
)) {
10162 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
10163 dev_priv
->display
.write_eld
= ironlake_write_eld
;
10164 } else if (IS_IVYBRIDGE(dev
)) {
10165 /* FIXME: detect B0+ stepping and use auto training */
10166 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
10167 dev_priv
->display
.write_eld
= ironlake_write_eld
;
10168 dev_priv
->display
.modeset_global_resources
=
10169 ivb_modeset_global_resources
;
10170 } else if (IS_HASWELL(dev
)) {
10171 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
10172 dev_priv
->display
.write_eld
= haswell_write_eld
;
10173 dev_priv
->display
.modeset_global_resources
=
10174 haswell_modeset_global_resources
;
10176 } else if (IS_G4X(dev
)) {
10177 dev_priv
->display
.write_eld
= g4x_write_eld
;
10180 /* Default just returns -ENODEV to indicate unsupported */
10181 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
10183 switch (INTEL_INFO(dev
)->gen
) {
10185 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
10189 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
10194 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
10198 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
10201 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
10207 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10208 * resume, or other times. This quirk makes sure that's the case for
10209 * affected systems.
10211 static void quirk_pipea_force(struct drm_device
*dev
)
10213 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10215 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
10216 DRM_INFO("applying pipe a force quirk\n");
10220 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10222 static void quirk_ssc_force_disable(struct drm_device
*dev
)
10224 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10225 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
10226 DRM_INFO("applying lvds SSC disable quirk\n");
10230 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10233 static void quirk_invert_brightness(struct drm_device
*dev
)
10235 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10236 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
10237 DRM_INFO("applying inverted panel brightness quirk\n");
10241 * Some machines (Dell XPS13) suffer broken backlight controls if
10242 * BLM_PCH_PWM_ENABLE is set.
10244 static void quirk_no_pcm_pwm_enable(struct drm_device
*dev
)
10246 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10247 dev_priv
->quirks
|= QUIRK_NO_PCH_PWM_ENABLE
;
10248 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10251 struct intel_quirk
{
10253 int subsystem_vendor
;
10254 int subsystem_device
;
10255 void (*hook
)(struct drm_device
*dev
);
10258 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10259 struct intel_dmi_quirk
{
10260 void (*hook
)(struct drm_device
*dev
);
10261 const struct dmi_system_id (*dmi_id_list
)[];
10264 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
10266 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
10270 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
10272 .dmi_id_list
= &(const struct dmi_system_id
[]) {
10274 .callback
= intel_dmi_reverse_brightness
,
10275 .ident
= "NCR Corporation",
10276 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
10277 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
10280 { } /* terminating entry */
10282 .hook
= quirk_invert_brightness
,
10286 static struct intel_quirk intel_quirks
[] = {
10287 /* HP Mini needs pipe A force quirk (LP: #322104) */
10288 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
10290 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10291 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
10293 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10294 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
10296 /* 830/845 need to leave pipe A & dpll A up */
10297 { 0x2562, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
10298 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
10300 /* Lenovo U160 cannot use SSC on LVDS */
10301 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
10303 /* Sony Vaio Y cannot use SSC on LVDS */
10304 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
10307 * All GM45 Acer (and its brands eMachines and Packard Bell) laptops
10308 * seem to use inverted backlight PWM.
10310 { 0x2a42, 0x1025, PCI_ANY_ID
, quirk_invert_brightness
},
10312 /* Dell XPS13 HD Sandy Bridge */
10313 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable
},
10314 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10315 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable
},
10318 static void intel_init_quirks(struct drm_device
*dev
)
10320 struct pci_dev
*d
= dev
->pdev
;
10323 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
10324 struct intel_quirk
*q
= &intel_quirks
[i
];
10326 if (d
->device
== q
->device
&&
10327 (d
->subsystem_vendor
== q
->subsystem_vendor
||
10328 q
->subsystem_vendor
== PCI_ANY_ID
) &&
10329 (d
->subsystem_device
== q
->subsystem_device
||
10330 q
->subsystem_device
== PCI_ANY_ID
))
10333 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
10334 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
10335 intel_dmi_quirks
[i
].hook(dev
);
10339 /* Disable the VGA plane that we never use */
10340 static void i915_disable_vga(struct drm_device
*dev
)
10342 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10344 u32 vga_reg
= i915_vgacntrl_reg(dev
);
10346 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
10347 outb(SR01
, VGA_SR_INDEX
);
10348 sr1
= inb(VGA_SR_DATA
);
10349 outb(sr1
| 1<<5, VGA_SR_DATA
);
10350 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
10353 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
10354 POSTING_READ(vga_reg
);
10357 static void i915_enable_vga_mem(struct drm_device
*dev
)
10359 /* Enable VGA memory on Intel HD */
10360 if (HAS_PCH_SPLIT(dev
)) {
10361 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
10362 outb(inb(VGA_MSR_READ
) | VGA_MSR_MEM_EN
, VGA_MSR_WRITE
);
10363 vga_set_legacy_decoding(dev
->pdev
, VGA_RSRC_LEGACY_IO
|
10364 VGA_RSRC_LEGACY_MEM
|
10365 VGA_RSRC_NORMAL_IO
|
10366 VGA_RSRC_NORMAL_MEM
);
10367 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
10371 void i915_disable_vga_mem(struct drm_device
*dev
)
10373 /* Disable VGA memory on Intel HD */
10374 if (HAS_PCH_SPLIT(dev
)) {
10375 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
10376 outb(inb(VGA_MSR_READ
) & ~VGA_MSR_MEM_EN
, VGA_MSR_WRITE
);
10377 vga_set_legacy_decoding(dev
->pdev
, VGA_RSRC_LEGACY_IO
|
10378 VGA_RSRC_NORMAL_IO
|
10379 VGA_RSRC_NORMAL_MEM
);
10380 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
10384 void intel_modeset_init_hw(struct drm_device
*dev
)
10386 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10388 intel_prepare_ddi(dev
);
10390 intel_init_clock_gating(dev
);
10392 /* Enable the CRI clock source so we can get at the display */
10393 if (IS_VALLEYVIEW(dev
))
10394 I915_WRITE(DPLL(PIPE_B
), I915_READ(DPLL(PIPE_B
)) |
10395 DPLL_INTEGRATED_CRI_CLK_VLV
);
10397 intel_init_dpio(dev
);
10399 mutex_lock(&dev
->struct_mutex
);
10400 intel_enable_gt_powersave(dev
);
10401 mutex_unlock(&dev
->struct_mutex
);
10404 void intel_modeset_suspend_hw(struct drm_device
*dev
)
10406 intel_suspend_hw(dev
);
10409 void intel_modeset_init(struct drm_device
*dev
)
10411 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10414 drm_mode_config_init(dev
);
10416 dev
->mode_config
.min_width
= 0;
10417 dev
->mode_config
.min_height
= 0;
10419 dev
->mode_config
.preferred_depth
= 24;
10420 dev
->mode_config
.prefer_shadow
= 1;
10422 dev
->mode_config
.funcs
= &intel_mode_funcs
;
10424 intel_init_quirks(dev
);
10426 intel_init_pm(dev
);
10428 if (INTEL_INFO(dev
)->num_pipes
== 0)
10431 intel_init_display(dev
);
10433 if (IS_GEN2(dev
)) {
10434 dev
->mode_config
.max_width
= 2048;
10435 dev
->mode_config
.max_height
= 2048;
10436 } else if (IS_GEN3(dev
)) {
10437 dev
->mode_config
.max_width
= 4096;
10438 dev
->mode_config
.max_height
= 4096;
10440 dev
->mode_config
.max_width
= 8192;
10441 dev
->mode_config
.max_height
= 8192;
10443 dev
->mode_config
.fb_base
= dev_priv
->gtt
.mappable_base
;
10445 DRM_DEBUG_KMS("%d display pipe%s available.\n",
10446 INTEL_INFO(dev
)->num_pipes
,
10447 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
10450 intel_crtc_init(dev
, i
);
10451 for (j
= 0; j
< dev_priv
->num_plane
; j
++) {
10452 ret
= intel_plane_init(dev
, i
, j
);
10454 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10455 pipe_name(i
), sprite_name(i
, j
), ret
);
10459 intel_cpu_pll_init(dev
);
10460 intel_shared_dpll_init(dev
);
10462 /* Just disable it once at startup */
10463 i915_disable_vga(dev
);
10464 intel_setup_outputs(dev
);
10466 /* Just in case the BIOS is doing something questionable. */
10467 intel_disable_fbc(dev
);
10471 intel_connector_break_all_links(struct intel_connector
*connector
)
10473 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
10474 connector
->base
.encoder
= NULL
;
10475 connector
->encoder
->connectors_active
= false;
10476 connector
->encoder
->base
.crtc
= NULL
;
10479 static void intel_enable_pipe_a(struct drm_device
*dev
)
10481 struct intel_connector
*connector
;
10482 struct drm_connector
*crt
= NULL
;
10483 struct intel_load_detect_pipe load_detect_temp
;
10485 /* We can't just switch on the pipe A, we need to set things up with a
10486 * proper mode and output configuration. As a gross hack, enable pipe A
10487 * by enabling the load detect pipe once. */
10488 list_for_each_entry(connector
,
10489 &dev
->mode_config
.connector_list
,
10491 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
10492 crt
= &connector
->base
;
10500 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
))
10501 intel_release_load_detect_pipe(crt
, &load_detect_temp
);
10507 intel_check_plane_mapping(struct intel_crtc
*crtc
)
10509 struct drm_device
*dev
= crtc
->base
.dev
;
10510 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10513 if (INTEL_INFO(dev
)->num_pipes
== 1)
10516 reg
= DSPCNTR(!crtc
->plane
);
10517 val
= I915_READ(reg
);
10519 if ((val
& DISPLAY_PLANE_ENABLE
) &&
10520 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
10526 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
10528 struct drm_device
*dev
= crtc
->base
.dev
;
10529 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10532 /* Clear any frame start delays used for debugging left by the BIOS */
10533 reg
= PIPECONF(crtc
->config
.cpu_transcoder
);
10534 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
10536 /* We need to sanitize the plane -> pipe mapping first because this will
10537 * disable the crtc (and hence change the state) if it is wrong. Note
10538 * that gen4+ has a fixed plane -> pipe mapping. */
10539 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
10540 struct intel_connector
*connector
;
10543 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10544 crtc
->base
.base
.id
);
10546 /* Pipe has the wrong plane attached and the plane is active.
10547 * Temporarily change the plane mapping and disable everything
10549 plane
= crtc
->plane
;
10550 crtc
->plane
= !plane
;
10551 dev_priv
->display
.crtc_disable(&crtc
->base
);
10552 crtc
->plane
= plane
;
10554 /* ... and break all links. */
10555 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10557 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
10560 intel_connector_break_all_links(connector
);
10563 WARN_ON(crtc
->active
);
10564 crtc
->base
.enabled
= false;
10567 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
10568 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
10569 /* BIOS forgot to enable pipe A, this mostly happens after
10570 * resume. Force-enable the pipe to fix this, the update_dpms
10571 * call below we restore the pipe to the right state, but leave
10572 * the required bits on. */
10573 intel_enable_pipe_a(dev
);
10576 /* Adjust the state of the output pipe according to whether we
10577 * have active connectors/encoders. */
10578 intel_crtc_update_dpms(&crtc
->base
);
10580 if (crtc
->active
!= crtc
->base
.enabled
) {
10581 struct intel_encoder
*encoder
;
10583 /* This can happen either due to bugs in the get_hw_state
10584 * functions or because the pipe is force-enabled due to the
10586 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10587 crtc
->base
.base
.id
,
10588 crtc
->base
.enabled
? "enabled" : "disabled",
10589 crtc
->active
? "enabled" : "disabled");
10591 crtc
->base
.enabled
= crtc
->active
;
10593 /* Because we only establish the connector -> encoder ->
10594 * crtc links if something is active, this means the
10595 * crtc is now deactivated. Break the links. connector
10596 * -> encoder links are only establish when things are
10597 * actually up, hence no need to break them. */
10598 WARN_ON(crtc
->active
);
10600 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
10601 WARN_ON(encoder
->connectors_active
);
10602 encoder
->base
.crtc
= NULL
;
10607 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
10609 struct intel_connector
*connector
;
10610 struct drm_device
*dev
= encoder
->base
.dev
;
10612 /* We need to check both for a crtc link (meaning that the
10613 * encoder is active and trying to read from a pipe) and the
10614 * pipe itself being active. */
10615 bool has_active_crtc
= encoder
->base
.crtc
&&
10616 to_intel_crtc(encoder
->base
.crtc
)->active
;
10618 if (encoder
->connectors_active
&& !has_active_crtc
) {
10619 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10620 encoder
->base
.base
.id
,
10621 drm_get_encoder_name(&encoder
->base
));
10623 /* Connector is active, but has no active pipe. This is
10624 * fallout from our resume register restoring. Disable
10625 * the encoder manually again. */
10626 if (encoder
->base
.crtc
) {
10627 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10628 encoder
->base
.base
.id
,
10629 drm_get_encoder_name(&encoder
->base
));
10630 encoder
->disable(encoder
);
10633 /* Inconsistent output/port/pipe state happens presumably due to
10634 * a bug in one of the get_hw_state functions. Or someplace else
10635 * in our code, like the register restore mess on resume. Clamp
10636 * things to off as a safer default. */
10637 list_for_each_entry(connector
,
10638 &dev
->mode_config
.connector_list
,
10640 if (connector
->encoder
!= encoder
)
10643 intel_connector_break_all_links(connector
);
10646 /* Enabled encoders without active connectors will be fixed in
10647 * the crtc fixup. */
10650 void i915_redisable_vga(struct drm_device
*dev
)
10652 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10653 u32 vga_reg
= i915_vgacntrl_reg(dev
);
10655 /* This function can be called both from intel_modeset_setup_hw_state or
10656 * at a very early point in our resume sequence, where the power well
10657 * structures are not yet restored. Since this function is at a very
10658 * paranoid "someone might have enabled VGA while we were not looking"
10659 * level, just check if the power well is enabled instead of trying to
10660 * follow the "don't touch the power well if we don't need it" policy
10661 * the rest of the driver uses. */
10662 if (HAS_POWER_WELL(dev
) &&
10663 (I915_READ(HSW_PWR_WELL_DRIVER
) & HSW_PWR_WELL_STATE_ENABLED
) == 0)
10666 if (!(I915_READ(vga_reg
) & VGA_DISP_DISABLE
)) {
10667 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
10668 i915_disable_vga(dev
);
10669 i915_disable_vga_mem(dev
);
10673 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
10675 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10677 struct intel_crtc
*crtc
;
10678 struct intel_encoder
*encoder
;
10679 struct intel_connector
*connector
;
10682 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
10684 memset(&crtc
->config
, 0, sizeof(crtc
->config
));
10686 crtc
->active
= dev_priv
->display
.get_pipe_config(crtc
,
10689 crtc
->base
.enabled
= crtc
->active
;
10691 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10692 crtc
->base
.base
.id
,
10693 crtc
->active
? "enabled" : "disabled");
10696 /* FIXME: Smash this into the new shared dpll infrastructure. */
10698 intel_ddi_setup_hw_pll_state(dev
);
10700 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
10701 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
10703 pll
->on
= pll
->get_hw_state(dev_priv
, pll
, &pll
->hw_state
);
10705 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
10707 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
10710 pll
->refcount
= pll
->active
;
10712 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10713 pll
->name
, pll
->refcount
, pll
->on
);
10716 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
10720 if (encoder
->get_hw_state(encoder
, &pipe
)) {
10721 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
10722 encoder
->base
.crtc
= &crtc
->base
;
10723 if (encoder
->get_config
)
10724 encoder
->get_config(encoder
, &crtc
->config
);
10726 encoder
->base
.crtc
= NULL
;
10729 encoder
->connectors_active
= false;
10730 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10731 encoder
->base
.base
.id
,
10732 drm_get_encoder_name(&encoder
->base
),
10733 encoder
->base
.crtc
? "enabled" : "disabled",
10737 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10739 if (connector
->get_hw_state(connector
)) {
10740 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
10741 connector
->encoder
->connectors_active
= true;
10742 connector
->base
.encoder
= &connector
->encoder
->base
;
10744 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
10745 connector
->base
.encoder
= NULL
;
10747 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10748 connector
->base
.base
.id
,
10749 drm_get_connector_name(&connector
->base
),
10750 connector
->base
.encoder
? "enabled" : "disabled");
10754 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10755 * and i915 state tracking structures. */
10756 void intel_modeset_setup_hw_state(struct drm_device
*dev
,
10757 bool force_restore
)
10759 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10761 struct intel_crtc
*crtc
;
10762 struct intel_encoder
*encoder
;
10765 intel_modeset_readout_hw_state(dev
);
10768 * Now that we have the config, copy it to each CRTC struct
10769 * Note that this could go away if we move to using crtc_config
10770 * checking everywhere.
10772 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
10774 if (crtc
->active
&& i915_fastboot
) {
10775 intel_crtc_mode_from_pipe_config(crtc
, &crtc
->config
);
10777 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10778 crtc
->base
.base
.id
);
10779 drm_mode_debug_printmodeline(&crtc
->base
.mode
);
10783 /* HW state is read out, now we need to sanitize this mess. */
10784 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
10786 intel_sanitize_encoder(encoder
);
10789 for_each_pipe(pipe
) {
10790 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
10791 intel_sanitize_crtc(crtc
);
10792 intel_dump_pipe_config(crtc
, &crtc
->config
, "[setup_hw_state]");
10795 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
10796 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
10798 if (!pll
->on
|| pll
->active
)
10801 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll
->name
);
10803 pll
->disable(dev_priv
, pll
);
10807 if (force_restore
) {
10808 i915_redisable_vga(dev
);
10811 * We need to use raw interfaces for restoring state to avoid
10812 * checking (bogus) intermediate states.
10814 for_each_pipe(pipe
) {
10815 struct drm_crtc
*crtc
=
10816 dev_priv
->pipe_to_crtc_mapping
[pipe
];
10818 __intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
,
10822 intel_modeset_update_staged_output_state(dev
);
10825 intel_modeset_check_state(dev
);
10827 drm_mode_config_reset(dev
);
10830 void intel_modeset_gem_init(struct drm_device
*dev
)
10832 intel_modeset_init_hw(dev
);
10834 intel_setup_overlay(dev
);
10836 intel_modeset_setup_hw_state(dev
, false);
10839 void intel_modeset_cleanup(struct drm_device
*dev
)
10841 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10842 struct drm_crtc
*crtc
;
10843 struct drm_connector
*connector
;
10846 * Interrupts and polling as the first thing to avoid creating havoc.
10847 * Too much stuff here (turning of rps, connectors, ...) would
10848 * experience fancy races otherwise.
10850 drm_irq_uninstall(dev
);
10851 cancel_work_sync(&dev_priv
->hotplug_work
);
10853 * Due to the hpd irq storm handling the hotplug work can re-arm the
10854 * poll handlers. Hence disable polling after hpd handling is shut down.
10856 drm_kms_helper_poll_fini(dev
);
10858 mutex_lock(&dev
->struct_mutex
);
10860 intel_unregister_dsm_handler();
10862 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
10863 /* Skip inactive CRTCs */
10867 intel_increase_pllclock(crtc
);
10870 intel_disable_fbc(dev
);
10872 i915_enable_vga_mem(dev
);
10874 intel_disable_gt_powersave(dev
);
10876 ironlake_teardown_rc6(dev
);
10878 mutex_unlock(&dev
->struct_mutex
);
10880 /* flush any delayed tasks or pending work */
10881 flush_scheduled_work();
10883 /* destroy backlight, if any, before the connectors */
10884 intel_panel_destroy_backlight(dev
);
10886 /* destroy the sysfs files before encoders/connectors */
10887 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
)
10888 drm_sysfs_connector_remove(connector
);
10890 drm_mode_config_cleanup(dev
);
10892 intel_cleanup_overlay(dev
);
10896 * Return which encoder is currently attached for connector.
10898 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
10900 return &intel_attached_encoder(connector
)->base
;
10903 void intel_connector_attach_encoder(struct intel_connector
*connector
,
10904 struct intel_encoder
*encoder
)
10906 connector
->encoder
= encoder
;
10907 drm_mode_connector_attach_encoder(&connector
->base
,
10912 * set vga decode state - true == enable VGA decode
10914 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
10916 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10919 pci_read_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, &gmch_ctrl
);
10921 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
10923 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
10924 pci_write_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, gmch_ctrl
);
10928 struct intel_display_error_state
{
10930 u32 power_well_driver
;
10932 int num_transcoders
;
10934 struct intel_cursor_error_state
{
10939 } cursor
[I915_MAX_PIPES
];
10941 struct intel_pipe_error_state
{
10943 } pipe
[I915_MAX_PIPES
];
10945 struct intel_plane_error_state
{
10953 } plane
[I915_MAX_PIPES
];
10955 struct intel_transcoder_error_state
{
10956 enum transcoder cpu_transcoder
;
10969 struct intel_display_error_state
*
10970 intel_display_capture_error_state(struct drm_device
*dev
)
10972 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
10973 struct intel_display_error_state
*error
;
10974 int transcoders
[] = {
10982 if (INTEL_INFO(dev
)->num_pipes
== 0)
10985 error
= kmalloc(sizeof(*error
), GFP_ATOMIC
);
10989 if (HAS_POWER_WELL(dev
))
10990 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_DRIVER
);
10993 if (INTEL_INFO(dev
)->gen
<= 6 || IS_VALLEYVIEW(dev
)) {
10994 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
10995 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
10996 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
10998 error
->cursor
[i
].control
= I915_READ(CURCNTR_IVB(i
));
10999 error
->cursor
[i
].position
= I915_READ(CURPOS_IVB(i
));
11000 error
->cursor
[i
].base
= I915_READ(CURBASE_IVB(i
));
11003 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
11004 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
11005 if (INTEL_INFO(dev
)->gen
<= 3) {
11006 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
11007 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
11009 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
11010 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
11011 if (INTEL_INFO(dev
)->gen
>= 4) {
11012 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
11013 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
11016 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
11019 error
->num_transcoders
= INTEL_INFO(dev
)->num_pipes
;
11020 if (HAS_DDI(dev_priv
->dev
))
11021 error
->num_transcoders
++; /* Account for eDP. */
11023 for (i
= 0; i
< error
->num_transcoders
; i
++) {
11024 enum transcoder cpu_transcoder
= transcoders
[i
];
11026 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
11028 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
11029 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
11030 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
11031 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
11032 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
11033 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
11034 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
11037 /* In the code above we read the registers without checking if the power
11038 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
11039 * prevent the next I915_WRITE from detecting it and printing an error
11041 intel_uncore_clear_errors(dev
);
11046 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
11049 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
11050 struct drm_device
*dev
,
11051 struct intel_display_error_state
*error
)
11058 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
11059 if (HAS_POWER_WELL(dev
))
11060 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
11061 error
->power_well_driver
);
11063 err_printf(m
, "Pipe [%d]:\n", i
);
11064 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
11066 err_printf(m
, "Plane [%d]:\n", i
);
11067 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
11068 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
11069 if (INTEL_INFO(dev
)->gen
<= 3) {
11070 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
11071 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
11073 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
11074 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
11075 if (INTEL_INFO(dev
)->gen
>= 4) {
11076 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
11077 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
11080 err_printf(m
, "Cursor [%d]:\n", i
);
11081 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
11082 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
11083 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
11086 for (i
= 0; i
< error
->num_transcoders
; i
++) {
11087 err_printf(m
, " CPU transcoder: %c\n",
11088 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
11089 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
11090 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
11091 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
11092 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
11093 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
11094 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
11095 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);