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drm/i915: Switch to common shared dpll framework for WRPLLs
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_rect.h>
44 #include <linux/dma_remapping.h>
45
46 /* Primary plane formats supported by all gen */
47 #define COMMON_PRIMARY_FORMATS \
48 DRM_FORMAT_C8, \
49 DRM_FORMAT_RGB565, \
50 DRM_FORMAT_XRGB8888, \
51 DRM_FORMAT_ARGB8888
52
53 /* Primary plane formats for gen <= 3 */
54 static const uint32_t intel_primary_formats_gen2[] = {
55 COMMON_PRIMARY_FORMATS,
56 DRM_FORMAT_XRGB1555,
57 DRM_FORMAT_ARGB1555,
58 };
59
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t intel_primary_formats_gen4[] = {
62 COMMON_PRIMARY_FORMATS, \
63 DRM_FORMAT_XBGR8888,
64 DRM_FORMAT_ABGR8888,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_ARGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 DRM_FORMAT_ABGR2101010,
69 };
70
71 /* Cursor formats */
72 static const uint32_t intel_cursor_formats[] = {
73 DRM_FORMAT_ARGB8888,
74 };
75
76 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
77 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
78
79 static void intel_increase_pllclock(struct drm_device *dev,
80 enum pipe pipe);
81 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
82
83 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
84 struct intel_crtc_config *pipe_config);
85 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
86 struct intel_crtc_config *pipe_config);
87
88 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
89 int x, int y, struct drm_framebuffer *old_fb);
90 static int intel_framebuffer_init(struct drm_device *dev,
91 struct intel_framebuffer *ifb,
92 struct drm_mode_fb_cmd2 *mode_cmd,
93 struct drm_i915_gem_object *obj);
94 static void intel_dp_set_m_n(struct intel_crtc *crtc);
95 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
96 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
97 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
98 struct intel_link_m_n *m_n);
99 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
100 static void haswell_set_pipeconf(struct drm_crtc *crtc);
101 static void intel_set_pipe_csc(struct drm_crtc *crtc);
102 static void vlv_prepare_pll(struct intel_crtc *crtc);
103
104 typedef struct {
105 int min, max;
106 } intel_range_t;
107
108 typedef struct {
109 int dot_limit;
110 int p2_slow, p2_fast;
111 } intel_p2_t;
112
113 typedef struct intel_limit intel_limit_t;
114 struct intel_limit {
115 intel_range_t dot, vco, n, m, m1, m2, p, p1;
116 intel_p2_t p2;
117 };
118
119 int
120 intel_pch_rawclk(struct drm_device *dev)
121 {
122 struct drm_i915_private *dev_priv = dev->dev_private;
123
124 WARN_ON(!HAS_PCH_SPLIT(dev));
125
126 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
127 }
128
129 static inline u32 /* units of 100MHz */
130 intel_fdi_link_freq(struct drm_device *dev)
131 {
132 if (IS_GEN5(dev)) {
133 struct drm_i915_private *dev_priv = dev->dev_private;
134 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
135 } else
136 return 27;
137 }
138
139 static const intel_limit_t intel_limits_i8xx_dac = {
140 .dot = { .min = 25000, .max = 350000 },
141 .vco = { .min = 908000, .max = 1512000 },
142 .n = { .min = 2, .max = 16 },
143 .m = { .min = 96, .max = 140 },
144 .m1 = { .min = 18, .max = 26 },
145 .m2 = { .min = 6, .max = 16 },
146 .p = { .min = 4, .max = 128 },
147 .p1 = { .min = 2, .max = 33 },
148 .p2 = { .dot_limit = 165000,
149 .p2_slow = 4, .p2_fast = 2 },
150 };
151
152 static const intel_limit_t intel_limits_i8xx_dvo = {
153 .dot = { .min = 25000, .max = 350000 },
154 .vco = { .min = 908000, .max = 1512000 },
155 .n = { .min = 2, .max = 16 },
156 .m = { .min = 96, .max = 140 },
157 .m1 = { .min = 18, .max = 26 },
158 .m2 = { .min = 6, .max = 16 },
159 .p = { .min = 4, .max = 128 },
160 .p1 = { .min = 2, .max = 33 },
161 .p2 = { .dot_limit = 165000,
162 .p2_slow = 4, .p2_fast = 4 },
163 };
164
165 static const intel_limit_t intel_limits_i8xx_lvds = {
166 .dot = { .min = 25000, .max = 350000 },
167 .vco = { .min = 908000, .max = 1512000 },
168 .n = { .min = 2, .max = 16 },
169 .m = { .min = 96, .max = 140 },
170 .m1 = { .min = 18, .max = 26 },
171 .m2 = { .min = 6, .max = 16 },
172 .p = { .min = 4, .max = 128 },
173 .p1 = { .min = 1, .max = 6 },
174 .p2 = { .dot_limit = 165000,
175 .p2_slow = 14, .p2_fast = 7 },
176 };
177
178 static const intel_limit_t intel_limits_i9xx_sdvo = {
179 .dot = { .min = 20000, .max = 400000 },
180 .vco = { .min = 1400000, .max = 2800000 },
181 .n = { .min = 1, .max = 6 },
182 .m = { .min = 70, .max = 120 },
183 .m1 = { .min = 8, .max = 18 },
184 .m2 = { .min = 3, .max = 7 },
185 .p = { .min = 5, .max = 80 },
186 .p1 = { .min = 1, .max = 8 },
187 .p2 = { .dot_limit = 200000,
188 .p2_slow = 10, .p2_fast = 5 },
189 };
190
191 static const intel_limit_t intel_limits_i9xx_lvds = {
192 .dot = { .min = 20000, .max = 400000 },
193 .vco = { .min = 1400000, .max = 2800000 },
194 .n = { .min = 1, .max = 6 },
195 .m = { .min = 70, .max = 120 },
196 .m1 = { .min = 8, .max = 18 },
197 .m2 = { .min = 3, .max = 7 },
198 .p = { .min = 7, .max = 98 },
199 .p1 = { .min = 1, .max = 8 },
200 .p2 = { .dot_limit = 112000,
201 .p2_slow = 14, .p2_fast = 7 },
202 };
203
204
205 static const intel_limit_t intel_limits_g4x_sdvo = {
206 .dot = { .min = 25000, .max = 270000 },
207 .vco = { .min = 1750000, .max = 3500000},
208 .n = { .min = 1, .max = 4 },
209 .m = { .min = 104, .max = 138 },
210 .m1 = { .min = 17, .max = 23 },
211 .m2 = { .min = 5, .max = 11 },
212 .p = { .min = 10, .max = 30 },
213 .p1 = { .min = 1, .max = 3},
214 .p2 = { .dot_limit = 270000,
215 .p2_slow = 10,
216 .p2_fast = 10
217 },
218 };
219
220 static const intel_limit_t intel_limits_g4x_hdmi = {
221 .dot = { .min = 22000, .max = 400000 },
222 .vco = { .min = 1750000, .max = 3500000},
223 .n = { .min = 1, .max = 4 },
224 .m = { .min = 104, .max = 138 },
225 .m1 = { .min = 16, .max = 23 },
226 .m2 = { .min = 5, .max = 11 },
227 .p = { .min = 5, .max = 80 },
228 .p1 = { .min = 1, .max = 8},
229 .p2 = { .dot_limit = 165000,
230 .p2_slow = 10, .p2_fast = 5 },
231 };
232
233 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
234 .dot = { .min = 20000, .max = 115000 },
235 .vco = { .min = 1750000, .max = 3500000 },
236 .n = { .min = 1, .max = 3 },
237 .m = { .min = 104, .max = 138 },
238 .m1 = { .min = 17, .max = 23 },
239 .m2 = { .min = 5, .max = 11 },
240 .p = { .min = 28, .max = 112 },
241 .p1 = { .min = 2, .max = 8 },
242 .p2 = { .dot_limit = 0,
243 .p2_slow = 14, .p2_fast = 14
244 },
245 };
246
247 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
248 .dot = { .min = 80000, .max = 224000 },
249 .vco = { .min = 1750000, .max = 3500000 },
250 .n = { .min = 1, .max = 3 },
251 .m = { .min = 104, .max = 138 },
252 .m1 = { .min = 17, .max = 23 },
253 .m2 = { .min = 5, .max = 11 },
254 .p = { .min = 14, .max = 42 },
255 .p1 = { .min = 2, .max = 6 },
256 .p2 = { .dot_limit = 0,
257 .p2_slow = 7, .p2_fast = 7
258 },
259 };
260
261 static const intel_limit_t intel_limits_pineview_sdvo = {
262 .dot = { .min = 20000, .max = 400000},
263 .vco = { .min = 1700000, .max = 3500000 },
264 /* Pineview's Ncounter is a ring counter */
265 .n = { .min = 3, .max = 6 },
266 .m = { .min = 2, .max = 256 },
267 /* Pineview only has one combined m divider, which we treat as m2. */
268 .m1 = { .min = 0, .max = 0 },
269 .m2 = { .min = 0, .max = 254 },
270 .p = { .min = 5, .max = 80 },
271 .p1 = { .min = 1, .max = 8 },
272 .p2 = { .dot_limit = 200000,
273 .p2_slow = 10, .p2_fast = 5 },
274 };
275
276 static const intel_limit_t intel_limits_pineview_lvds = {
277 .dot = { .min = 20000, .max = 400000 },
278 .vco = { .min = 1700000, .max = 3500000 },
279 .n = { .min = 3, .max = 6 },
280 .m = { .min = 2, .max = 256 },
281 .m1 = { .min = 0, .max = 0 },
282 .m2 = { .min = 0, .max = 254 },
283 .p = { .min = 7, .max = 112 },
284 .p1 = { .min = 1, .max = 8 },
285 .p2 = { .dot_limit = 112000,
286 .p2_slow = 14, .p2_fast = 14 },
287 };
288
289 /* Ironlake / Sandybridge
290 *
291 * We calculate clock using (register_value + 2) for N/M1/M2, so here
292 * the range value for them is (actual_value - 2).
293 */
294 static const intel_limit_t intel_limits_ironlake_dac = {
295 .dot = { .min = 25000, .max = 350000 },
296 .vco = { .min = 1760000, .max = 3510000 },
297 .n = { .min = 1, .max = 5 },
298 .m = { .min = 79, .max = 127 },
299 .m1 = { .min = 12, .max = 22 },
300 .m2 = { .min = 5, .max = 9 },
301 .p = { .min = 5, .max = 80 },
302 .p1 = { .min = 1, .max = 8 },
303 .p2 = { .dot_limit = 225000,
304 .p2_slow = 10, .p2_fast = 5 },
305 };
306
307 static const intel_limit_t intel_limits_ironlake_single_lvds = {
308 .dot = { .min = 25000, .max = 350000 },
309 .vco = { .min = 1760000, .max = 3510000 },
310 .n = { .min = 1, .max = 3 },
311 .m = { .min = 79, .max = 118 },
312 .m1 = { .min = 12, .max = 22 },
313 .m2 = { .min = 5, .max = 9 },
314 .p = { .min = 28, .max = 112 },
315 .p1 = { .min = 2, .max = 8 },
316 .p2 = { .dot_limit = 225000,
317 .p2_slow = 14, .p2_fast = 14 },
318 };
319
320 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 79, .max = 127 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 14, .max = 56 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 7, .p2_fast = 7 },
331 };
332
333 /* LVDS 100mhz refclk limits. */
334 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
335 .dot = { .min = 25000, .max = 350000 },
336 .vco = { .min = 1760000, .max = 3510000 },
337 .n = { .min = 1, .max = 2 },
338 .m = { .min = 79, .max = 126 },
339 .m1 = { .min = 12, .max = 22 },
340 .m2 = { .min = 5, .max = 9 },
341 .p = { .min = 28, .max = 112 },
342 .p1 = { .min = 2, .max = 8 },
343 .p2 = { .dot_limit = 225000,
344 .p2_slow = 14, .p2_fast = 14 },
345 };
346
347 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
348 .dot = { .min = 25000, .max = 350000 },
349 .vco = { .min = 1760000, .max = 3510000 },
350 .n = { .min = 1, .max = 3 },
351 .m = { .min = 79, .max = 126 },
352 .m1 = { .min = 12, .max = 22 },
353 .m2 = { .min = 5, .max = 9 },
354 .p = { .min = 14, .max = 42 },
355 .p1 = { .min = 2, .max = 6 },
356 .p2 = { .dot_limit = 225000,
357 .p2_slow = 7, .p2_fast = 7 },
358 };
359
360 static const intel_limit_t intel_limits_vlv = {
361 /*
362 * These are the data rate limits (measured in fast clocks)
363 * since those are the strictest limits we have. The fast
364 * clock and actual rate limits are more relaxed, so checking
365 * them would make no difference.
366 */
367 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
368 .vco = { .min = 4000000, .max = 6000000 },
369 .n = { .min = 1, .max = 7 },
370 .m1 = { .min = 2, .max = 3 },
371 .m2 = { .min = 11, .max = 156 },
372 .p1 = { .min = 2, .max = 3 },
373 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
374 };
375
376 static const intel_limit_t intel_limits_chv = {
377 /*
378 * These are the data rate limits (measured in fast clocks)
379 * since those are the strictest limits we have. The fast
380 * clock and actual rate limits are more relaxed, so checking
381 * them would make no difference.
382 */
383 .dot = { .min = 25000 * 5, .max = 540000 * 5},
384 .vco = { .min = 4860000, .max = 6700000 },
385 .n = { .min = 1, .max = 1 },
386 .m1 = { .min = 2, .max = 2 },
387 .m2 = { .min = 24 << 22, .max = 175 << 22 },
388 .p1 = { .min = 2, .max = 4 },
389 .p2 = { .p2_slow = 1, .p2_fast = 14 },
390 };
391
392 static void vlv_clock(int refclk, intel_clock_t *clock)
393 {
394 clock->m = clock->m1 * clock->m2;
395 clock->p = clock->p1 * clock->p2;
396 if (WARN_ON(clock->n == 0 || clock->p == 0))
397 return;
398 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
399 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
400 }
401
402 /**
403 * Returns whether any output on the specified pipe is of the specified type
404 */
405 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
406 {
407 struct drm_device *dev = crtc->dev;
408 struct intel_encoder *encoder;
409
410 for_each_encoder_on_crtc(dev, crtc, encoder)
411 if (encoder->type == type)
412 return true;
413
414 return false;
415 }
416
417 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
418 int refclk)
419 {
420 struct drm_device *dev = crtc->dev;
421 const intel_limit_t *limit;
422
423 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
424 if (intel_is_dual_link_lvds(dev)) {
425 if (refclk == 100000)
426 limit = &intel_limits_ironlake_dual_lvds_100m;
427 else
428 limit = &intel_limits_ironlake_dual_lvds;
429 } else {
430 if (refclk == 100000)
431 limit = &intel_limits_ironlake_single_lvds_100m;
432 else
433 limit = &intel_limits_ironlake_single_lvds;
434 }
435 } else
436 limit = &intel_limits_ironlake_dac;
437
438 return limit;
439 }
440
441 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
442 {
443 struct drm_device *dev = crtc->dev;
444 const intel_limit_t *limit;
445
446 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
447 if (intel_is_dual_link_lvds(dev))
448 limit = &intel_limits_g4x_dual_channel_lvds;
449 else
450 limit = &intel_limits_g4x_single_channel_lvds;
451 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
452 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
453 limit = &intel_limits_g4x_hdmi;
454 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
455 limit = &intel_limits_g4x_sdvo;
456 } else /* The option is for other outputs */
457 limit = &intel_limits_i9xx_sdvo;
458
459 return limit;
460 }
461
462 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
463 {
464 struct drm_device *dev = crtc->dev;
465 const intel_limit_t *limit;
466
467 if (HAS_PCH_SPLIT(dev))
468 limit = intel_ironlake_limit(crtc, refclk);
469 else if (IS_G4X(dev)) {
470 limit = intel_g4x_limit(crtc);
471 } else if (IS_PINEVIEW(dev)) {
472 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
473 limit = &intel_limits_pineview_lvds;
474 else
475 limit = &intel_limits_pineview_sdvo;
476 } else if (IS_CHERRYVIEW(dev)) {
477 limit = &intel_limits_chv;
478 } else if (IS_VALLEYVIEW(dev)) {
479 limit = &intel_limits_vlv;
480 } else if (!IS_GEN2(dev)) {
481 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
482 limit = &intel_limits_i9xx_lvds;
483 else
484 limit = &intel_limits_i9xx_sdvo;
485 } else {
486 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
487 limit = &intel_limits_i8xx_lvds;
488 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
489 limit = &intel_limits_i8xx_dvo;
490 else
491 limit = &intel_limits_i8xx_dac;
492 }
493 return limit;
494 }
495
496 /* m1 is reserved as 0 in Pineview, n is a ring counter */
497 static void pineview_clock(int refclk, intel_clock_t *clock)
498 {
499 clock->m = clock->m2 + 2;
500 clock->p = clock->p1 * clock->p2;
501 if (WARN_ON(clock->n == 0 || clock->p == 0))
502 return;
503 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
504 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
505 }
506
507 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
508 {
509 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
510 }
511
512 static void i9xx_clock(int refclk, intel_clock_t *clock)
513 {
514 clock->m = i9xx_dpll_compute_m(clock);
515 clock->p = clock->p1 * clock->p2;
516 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
517 return;
518 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
519 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
520 }
521
522 static void chv_clock(int refclk, intel_clock_t *clock)
523 {
524 clock->m = clock->m1 * clock->m2;
525 clock->p = clock->p1 * clock->p2;
526 if (WARN_ON(clock->n == 0 || clock->p == 0))
527 return;
528 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
529 clock->n << 22);
530 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
531 }
532
533 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
534 /**
535 * Returns whether the given set of divisors are valid for a given refclk with
536 * the given connectors.
537 */
538
539 static bool intel_PLL_is_valid(struct drm_device *dev,
540 const intel_limit_t *limit,
541 const intel_clock_t *clock)
542 {
543 if (clock->n < limit->n.min || limit->n.max < clock->n)
544 INTELPllInvalid("n out of range\n");
545 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
546 INTELPllInvalid("p1 out of range\n");
547 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
548 INTELPllInvalid("m2 out of range\n");
549 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
550 INTELPllInvalid("m1 out of range\n");
551
552 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
553 if (clock->m1 <= clock->m2)
554 INTELPllInvalid("m1 <= m2\n");
555
556 if (!IS_VALLEYVIEW(dev)) {
557 if (clock->p < limit->p.min || limit->p.max < clock->p)
558 INTELPllInvalid("p out of range\n");
559 if (clock->m < limit->m.min || limit->m.max < clock->m)
560 INTELPllInvalid("m out of range\n");
561 }
562
563 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
564 INTELPllInvalid("vco out of range\n");
565 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
566 * connector, etc., rather than just a single range.
567 */
568 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
569 INTELPllInvalid("dot out of range\n");
570
571 return true;
572 }
573
574 static bool
575 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
576 int target, int refclk, intel_clock_t *match_clock,
577 intel_clock_t *best_clock)
578 {
579 struct drm_device *dev = crtc->dev;
580 intel_clock_t clock;
581 int err = target;
582
583 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
584 /*
585 * For LVDS just rely on its current settings for dual-channel.
586 * We haven't figured out how to reliably set up different
587 * single/dual channel state, if we even can.
588 */
589 if (intel_is_dual_link_lvds(dev))
590 clock.p2 = limit->p2.p2_fast;
591 else
592 clock.p2 = limit->p2.p2_slow;
593 } else {
594 if (target < limit->p2.dot_limit)
595 clock.p2 = limit->p2.p2_slow;
596 else
597 clock.p2 = limit->p2.p2_fast;
598 }
599
600 memset(best_clock, 0, sizeof(*best_clock));
601
602 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
603 clock.m1++) {
604 for (clock.m2 = limit->m2.min;
605 clock.m2 <= limit->m2.max; clock.m2++) {
606 if (clock.m2 >= clock.m1)
607 break;
608 for (clock.n = limit->n.min;
609 clock.n <= limit->n.max; clock.n++) {
610 for (clock.p1 = limit->p1.min;
611 clock.p1 <= limit->p1.max; clock.p1++) {
612 int this_err;
613
614 i9xx_clock(refclk, &clock);
615 if (!intel_PLL_is_valid(dev, limit,
616 &clock))
617 continue;
618 if (match_clock &&
619 clock.p != match_clock->p)
620 continue;
621
622 this_err = abs(clock.dot - target);
623 if (this_err < err) {
624 *best_clock = clock;
625 err = this_err;
626 }
627 }
628 }
629 }
630 }
631
632 return (err != target);
633 }
634
635 static bool
636 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
637 int target, int refclk, intel_clock_t *match_clock,
638 intel_clock_t *best_clock)
639 {
640 struct drm_device *dev = crtc->dev;
641 intel_clock_t clock;
642 int err = target;
643
644 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
645 /*
646 * For LVDS just rely on its current settings for dual-channel.
647 * We haven't figured out how to reliably set up different
648 * single/dual channel state, if we even can.
649 */
650 if (intel_is_dual_link_lvds(dev))
651 clock.p2 = limit->p2.p2_fast;
652 else
653 clock.p2 = limit->p2.p2_slow;
654 } else {
655 if (target < limit->p2.dot_limit)
656 clock.p2 = limit->p2.p2_slow;
657 else
658 clock.p2 = limit->p2.p2_fast;
659 }
660
661 memset(best_clock, 0, sizeof(*best_clock));
662
663 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
664 clock.m1++) {
665 for (clock.m2 = limit->m2.min;
666 clock.m2 <= limit->m2.max; clock.m2++) {
667 for (clock.n = limit->n.min;
668 clock.n <= limit->n.max; clock.n++) {
669 for (clock.p1 = limit->p1.min;
670 clock.p1 <= limit->p1.max; clock.p1++) {
671 int this_err;
672
673 pineview_clock(refclk, &clock);
674 if (!intel_PLL_is_valid(dev, limit,
675 &clock))
676 continue;
677 if (match_clock &&
678 clock.p != match_clock->p)
679 continue;
680
681 this_err = abs(clock.dot - target);
682 if (this_err < err) {
683 *best_clock = clock;
684 err = this_err;
685 }
686 }
687 }
688 }
689 }
690
691 return (err != target);
692 }
693
694 static bool
695 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
696 int target, int refclk, intel_clock_t *match_clock,
697 intel_clock_t *best_clock)
698 {
699 struct drm_device *dev = crtc->dev;
700 intel_clock_t clock;
701 int max_n;
702 bool found;
703 /* approximately equals target * 0.00585 */
704 int err_most = (target >> 8) + (target >> 9);
705 found = false;
706
707 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
708 if (intel_is_dual_link_lvds(dev))
709 clock.p2 = limit->p2.p2_fast;
710 else
711 clock.p2 = limit->p2.p2_slow;
712 } else {
713 if (target < limit->p2.dot_limit)
714 clock.p2 = limit->p2.p2_slow;
715 else
716 clock.p2 = limit->p2.p2_fast;
717 }
718
719 memset(best_clock, 0, sizeof(*best_clock));
720 max_n = limit->n.max;
721 /* based on hardware requirement, prefer smaller n to precision */
722 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
723 /* based on hardware requirement, prefere larger m1,m2 */
724 for (clock.m1 = limit->m1.max;
725 clock.m1 >= limit->m1.min; clock.m1--) {
726 for (clock.m2 = limit->m2.max;
727 clock.m2 >= limit->m2.min; clock.m2--) {
728 for (clock.p1 = limit->p1.max;
729 clock.p1 >= limit->p1.min; clock.p1--) {
730 int this_err;
731
732 i9xx_clock(refclk, &clock);
733 if (!intel_PLL_is_valid(dev, limit,
734 &clock))
735 continue;
736
737 this_err = abs(clock.dot - target);
738 if (this_err < err_most) {
739 *best_clock = clock;
740 err_most = this_err;
741 max_n = clock.n;
742 found = true;
743 }
744 }
745 }
746 }
747 }
748 return found;
749 }
750
751 static bool
752 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
753 int target, int refclk, intel_clock_t *match_clock,
754 intel_clock_t *best_clock)
755 {
756 struct drm_device *dev = crtc->dev;
757 intel_clock_t clock;
758 unsigned int bestppm = 1000000;
759 /* min update 19.2 MHz */
760 int max_n = min(limit->n.max, refclk / 19200);
761 bool found = false;
762
763 target *= 5; /* fast clock */
764
765 memset(best_clock, 0, sizeof(*best_clock));
766
767 /* based on hardware requirement, prefer smaller n to precision */
768 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
769 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
770 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
771 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
772 clock.p = clock.p1 * clock.p2;
773 /* based on hardware requirement, prefer bigger m1,m2 values */
774 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
775 unsigned int ppm, diff;
776
777 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
778 refclk * clock.m1);
779
780 vlv_clock(refclk, &clock);
781
782 if (!intel_PLL_is_valid(dev, limit,
783 &clock))
784 continue;
785
786 diff = abs(clock.dot - target);
787 ppm = div_u64(1000000ULL * diff, target);
788
789 if (ppm < 100 && clock.p > best_clock->p) {
790 bestppm = 0;
791 *best_clock = clock;
792 found = true;
793 }
794
795 if (bestppm >= 10 && ppm < bestppm - 10) {
796 bestppm = ppm;
797 *best_clock = clock;
798 found = true;
799 }
800 }
801 }
802 }
803 }
804
805 return found;
806 }
807
808 static bool
809 chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
810 int target, int refclk, intel_clock_t *match_clock,
811 intel_clock_t *best_clock)
812 {
813 struct drm_device *dev = crtc->dev;
814 intel_clock_t clock;
815 uint64_t m2;
816 int found = false;
817
818 memset(best_clock, 0, sizeof(*best_clock));
819
820 /*
821 * Based on hardware doc, the n always set to 1, and m1 always
822 * set to 2. If requires to support 200Mhz refclk, we need to
823 * revisit this because n may not 1 anymore.
824 */
825 clock.n = 1, clock.m1 = 2;
826 target *= 5; /* fast clock */
827
828 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
829 for (clock.p2 = limit->p2.p2_fast;
830 clock.p2 >= limit->p2.p2_slow;
831 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
832
833 clock.p = clock.p1 * clock.p2;
834
835 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
836 clock.n) << 22, refclk * clock.m1);
837
838 if (m2 > INT_MAX/clock.m1)
839 continue;
840
841 clock.m2 = m2;
842
843 chv_clock(refclk, &clock);
844
845 if (!intel_PLL_is_valid(dev, limit, &clock))
846 continue;
847
848 /* based on hardware requirement, prefer bigger p
849 */
850 if (clock.p > best_clock->p) {
851 *best_clock = clock;
852 found = true;
853 }
854 }
855 }
856
857 return found;
858 }
859
860 bool intel_crtc_active(struct drm_crtc *crtc)
861 {
862 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
863
864 /* Be paranoid as we can arrive here with only partial
865 * state retrieved from the hardware during setup.
866 *
867 * We can ditch the adjusted_mode.crtc_clock check as soon
868 * as Haswell has gained clock readout/fastboot support.
869 *
870 * We can ditch the crtc->primary->fb check as soon as we can
871 * properly reconstruct framebuffers.
872 */
873 return intel_crtc->active && crtc->primary->fb &&
874 intel_crtc->config.adjusted_mode.crtc_clock;
875 }
876
877 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
878 enum pipe pipe)
879 {
880 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
881 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
882
883 return intel_crtc->config.cpu_transcoder;
884 }
885
886 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
887 {
888 struct drm_i915_private *dev_priv = dev->dev_private;
889 u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
890
891 frame = I915_READ(frame_reg);
892
893 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
894 WARN(1, "vblank wait timed out\n");
895 }
896
897 /**
898 * intel_wait_for_vblank - wait for vblank on a given pipe
899 * @dev: drm device
900 * @pipe: pipe to wait for
901 *
902 * Wait for vblank to occur on a given pipe. Needed for various bits of
903 * mode setting code.
904 */
905 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
906 {
907 struct drm_i915_private *dev_priv = dev->dev_private;
908 int pipestat_reg = PIPESTAT(pipe);
909
910 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
911 g4x_wait_for_vblank(dev, pipe);
912 return;
913 }
914
915 /* Clear existing vblank status. Note this will clear any other
916 * sticky status fields as well.
917 *
918 * This races with i915_driver_irq_handler() with the result
919 * that either function could miss a vblank event. Here it is not
920 * fatal, as we will either wait upon the next vblank interrupt or
921 * timeout. Generally speaking intel_wait_for_vblank() is only
922 * called during modeset at which time the GPU should be idle and
923 * should *not* be performing page flips and thus not waiting on
924 * vblanks...
925 * Currently, the result of us stealing a vblank from the irq
926 * handler is that a single frame will be skipped during swapbuffers.
927 */
928 I915_WRITE(pipestat_reg,
929 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
930
931 /* Wait for vblank interrupt bit to set */
932 if (wait_for(I915_READ(pipestat_reg) &
933 PIPE_VBLANK_INTERRUPT_STATUS,
934 50))
935 DRM_DEBUG_KMS("vblank wait timed out\n");
936 }
937
938 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
939 {
940 struct drm_i915_private *dev_priv = dev->dev_private;
941 u32 reg = PIPEDSL(pipe);
942 u32 line1, line2;
943 u32 line_mask;
944
945 if (IS_GEN2(dev))
946 line_mask = DSL_LINEMASK_GEN2;
947 else
948 line_mask = DSL_LINEMASK_GEN3;
949
950 line1 = I915_READ(reg) & line_mask;
951 mdelay(5);
952 line2 = I915_READ(reg) & line_mask;
953
954 return line1 == line2;
955 }
956
957 /*
958 * intel_wait_for_pipe_off - wait for pipe to turn off
959 * @dev: drm device
960 * @pipe: pipe to wait for
961 *
962 * After disabling a pipe, we can't wait for vblank in the usual way,
963 * spinning on the vblank interrupt status bit, since we won't actually
964 * see an interrupt when the pipe is disabled.
965 *
966 * On Gen4 and above:
967 * wait for the pipe register state bit to turn off
968 *
969 * Otherwise:
970 * wait for the display line value to settle (it usually
971 * ends up stopping at the start of the next frame).
972 *
973 */
974 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
975 {
976 struct drm_i915_private *dev_priv = dev->dev_private;
977 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
978 pipe);
979
980 if (INTEL_INFO(dev)->gen >= 4) {
981 int reg = PIPECONF(cpu_transcoder);
982
983 /* Wait for the Pipe State to go off */
984 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
985 100))
986 WARN(1, "pipe_off wait timed out\n");
987 } else {
988 /* Wait for the display line to settle */
989 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
990 WARN(1, "pipe_off wait timed out\n");
991 }
992 }
993
994 /*
995 * ibx_digital_port_connected - is the specified port connected?
996 * @dev_priv: i915 private structure
997 * @port: the port to test
998 *
999 * Returns true if @port is connected, false otherwise.
1000 */
1001 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1002 struct intel_digital_port *port)
1003 {
1004 u32 bit;
1005
1006 if (HAS_PCH_IBX(dev_priv->dev)) {
1007 switch (port->port) {
1008 case PORT_B:
1009 bit = SDE_PORTB_HOTPLUG;
1010 break;
1011 case PORT_C:
1012 bit = SDE_PORTC_HOTPLUG;
1013 break;
1014 case PORT_D:
1015 bit = SDE_PORTD_HOTPLUG;
1016 break;
1017 default:
1018 return true;
1019 }
1020 } else {
1021 switch (port->port) {
1022 case PORT_B:
1023 bit = SDE_PORTB_HOTPLUG_CPT;
1024 break;
1025 case PORT_C:
1026 bit = SDE_PORTC_HOTPLUG_CPT;
1027 break;
1028 case PORT_D:
1029 bit = SDE_PORTD_HOTPLUG_CPT;
1030 break;
1031 default:
1032 return true;
1033 }
1034 }
1035
1036 return I915_READ(SDEISR) & bit;
1037 }
1038
1039 static const char *state_string(bool enabled)
1040 {
1041 return enabled ? "on" : "off";
1042 }
1043
1044 /* Only for pre-ILK configs */
1045 void assert_pll(struct drm_i915_private *dev_priv,
1046 enum pipe pipe, bool state)
1047 {
1048 int reg;
1049 u32 val;
1050 bool cur_state;
1051
1052 reg = DPLL(pipe);
1053 val = I915_READ(reg);
1054 cur_state = !!(val & DPLL_VCO_ENABLE);
1055 WARN(cur_state != state,
1056 "PLL state assertion failure (expected %s, current %s)\n",
1057 state_string(state), state_string(cur_state));
1058 }
1059
1060 /* XXX: the dsi pll is shared between MIPI DSI ports */
1061 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1062 {
1063 u32 val;
1064 bool cur_state;
1065
1066 mutex_lock(&dev_priv->dpio_lock);
1067 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1068 mutex_unlock(&dev_priv->dpio_lock);
1069
1070 cur_state = val & DSI_PLL_VCO_EN;
1071 WARN(cur_state != state,
1072 "DSI PLL state assertion failure (expected %s, current %s)\n",
1073 state_string(state), state_string(cur_state));
1074 }
1075 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1076 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1077
1078 struct intel_shared_dpll *
1079 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1080 {
1081 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1082
1083 if (crtc->config.shared_dpll < 0)
1084 return NULL;
1085
1086 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1087 }
1088
1089 /* For ILK+ */
1090 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1091 struct intel_shared_dpll *pll,
1092 bool state)
1093 {
1094 bool cur_state;
1095 struct intel_dpll_hw_state hw_state;
1096
1097 if (HAS_PCH_LPT(dev_priv->dev)) {
1098 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1099 return;
1100 }
1101
1102 if (WARN (!pll,
1103 "asserting DPLL %s with no DPLL\n", state_string(state)))
1104 return;
1105
1106 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1107 WARN(cur_state != state,
1108 "%s assertion failure (expected %s, current %s)\n",
1109 pll->name, state_string(state), state_string(cur_state));
1110 }
1111
1112 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1113 enum pipe pipe, bool state)
1114 {
1115 int reg;
1116 u32 val;
1117 bool cur_state;
1118 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1119 pipe);
1120
1121 if (HAS_DDI(dev_priv->dev)) {
1122 /* DDI does not have a specific FDI_TX register */
1123 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1124 val = I915_READ(reg);
1125 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1126 } else {
1127 reg = FDI_TX_CTL(pipe);
1128 val = I915_READ(reg);
1129 cur_state = !!(val & FDI_TX_ENABLE);
1130 }
1131 WARN(cur_state != state,
1132 "FDI TX state assertion failure (expected %s, current %s)\n",
1133 state_string(state), state_string(cur_state));
1134 }
1135 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1136 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1137
1138 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1139 enum pipe pipe, bool state)
1140 {
1141 int reg;
1142 u32 val;
1143 bool cur_state;
1144
1145 reg = FDI_RX_CTL(pipe);
1146 val = I915_READ(reg);
1147 cur_state = !!(val & FDI_RX_ENABLE);
1148 WARN(cur_state != state,
1149 "FDI RX state assertion failure (expected %s, current %s)\n",
1150 state_string(state), state_string(cur_state));
1151 }
1152 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1153 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1154
1155 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1156 enum pipe pipe)
1157 {
1158 int reg;
1159 u32 val;
1160
1161 /* ILK FDI PLL is always enabled */
1162 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1163 return;
1164
1165 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1166 if (HAS_DDI(dev_priv->dev))
1167 return;
1168
1169 reg = FDI_TX_CTL(pipe);
1170 val = I915_READ(reg);
1171 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1172 }
1173
1174 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1175 enum pipe pipe, bool state)
1176 {
1177 int reg;
1178 u32 val;
1179 bool cur_state;
1180
1181 reg = FDI_RX_CTL(pipe);
1182 val = I915_READ(reg);
1183 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1184 WARN(cur_state != state,
1185 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1186 state_string(state), state_string(cur_state));
1187 }
1188
1189 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1190 enum pipe pipe)
1191 {
1192 int pp_reg, lvds_reg;
1193 u32 val;
1194 enum pipe panel_pipe = PIPE_A;
1195 bool locked = true;
1196
1197 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1198 pp_reg = PCH_PP_CONTROL;
1199 lvds_reg = PCH_LVDS;
1200 } else {
1201 pp_reg = PP_CONTROL;
1202 lvds_reg = LVDS;
1203 }
1204
1205 val = I915_READ(pp_reg);
1206 if (!(val & PANEL_POWER_ON) ||
1207 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1208 locked = false;
1209
1210 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1211 panel_pipe = PIPE_B;
1212
1213 WARN(panel_pipe == pipe && locked,
1214 "panel assertion failure, pipe %c regs locked\n",
1215 pipe_name(pipe));
1216 }
1217
1218 static void assert_cursor(struct drm_i915_private *dev_priv,
1219 enum pipe pipe, bool state)
1220 {
1221 struct drm_device *dev = dev_priv->dev;
1222 bool cur_state;
1223
1224 if (IS_845G(dev) || IS_I865G(dev))
1225 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1226 else
1227 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1228
1229 WARN(cur_state != state,
1230 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1231 pipe_name(pipe), state_string(state), state_string(cur_state));
1232 }
1233 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1234 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1235
1236 void assert_pipe(struct drm_i915_private *dev_priv,
1237 enum pipe pipe, bool state)
1238 {
1239 int reg;
1240 u32 val;
1241 bool cur_state;
1242 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1243 pipe);
1244
1245 /* if we need the pipe A quirk it must be always on */
1246 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1247 state = true;
1248
1249 if (!intel_display_power_enabled(dev_priv,
1250 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1251 cur_state = false;
1252 } else {
1253 reg = PIPECONF(cpu_transcoder);
1254 val = I915_READ(reg);
1255 cur_state = !!(val & PIPECONF_ENABLE);
1256 }
1257
1258 WARN(cur_state != state,
1259 "pipe %c assertion failure (expected %s, current %s)\n",
1260 pipe_name(pipe), state_string(state), state_string(cur_state));
1261 }
1262
1263 static void assert_plane(struct drm_i915_private *dev_priv,
1264 enum plane plane, bool state)
1265 {
1266 int reg;
1267 u32 val;
1268 bool cur_state;
1269
1270 reg = DSPCNTR(plane);
1271 val = I915_READ(reg);
1272 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1273 WARN(cur_state != state,
1274 "plane %c assertion failure (expected %s, current %s)\n",
1275 plane_name(plane), state_string(state), state_string(cur_state));
1276 }
1277
1278 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1279 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1280
1281 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1282 enum pipe pipe)
1283 {
1284 struct drm_device *dev = dev_priv->dev;
1285 int reg, i;
1286 u32 val;
1287 int cur_pipe;
1288
1289 /* Primary planes are fixed to pipes on gen4+ */
1290 if (INTEL_INFO(dev)->gen >= 4) {
1291 reg = DSPCNTR(pipe);
1292 val = I915_READ(reg);
1293 WARN(val & DISPLAY_PLANE_ENABLE,
1294 "plane %c assertion failure, should be disabled but not\n",
1295 plane_name(pipe));
1296 return;
1297 }
1298
1299 /* Need to check both planes against the pipe */
1300 for_each_pipe(i) {
1301 reg = DSPCNTR(i);
1302 val = I915_READ(reg);
1303 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1304 DISPPLANE_SEL_PIPE_SHIFT;
1305 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1306 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1307 plane_name(i), pipe_name(pipe));
1308 }
1309 }
1310
1311 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1312 enum pipe pipe)
1313 {
1314 struct drm_device *dev = dev_priv->dev;
1315 int reg, sprite;
1316 u32 val;
1317
1318 if (IS_VALLEYVIEW(dev)) {
1319 for_each_sprite(pipe, sprite) {
1320 reg = SPCNTR(pipe, sprite);
1321 val = I915_READ(reg);
1322 WARN(val & SP_ENABLE,
1323 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1324 sprite_name(pipe, sprite), pipe_name(pipe));
1325 }
1326 } else if (INTEL_INFO(dev)->gen >= 7) {
1327 reg = SPRCTL(pipe);
1328 val = I915_READ(reg);
1329 WARN(val & SPRITE_ENABLE,
1330 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1331 plane_name(pipe), pipe_name(pipe));
1332 } else if (INTEL_INFO(dev)->gen >= 5) {
1333 reg = DVSCNTR(pipe);
1334 val = I915_READ(reg);
1335 WARN(val & DVS_ENABLE,
1336 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1337 plane_name(pipe), pipe_name(pipe));
1338 }
1339 }
1340
1341 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1342 {
1343 u32 val;
1344 bool enabled;
1345
1346 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1347
1348 val = I915_READ(PCH_DREF_CONTROL);
1349 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1350 DREF_SUPERSPREAD_SOURCE_MASK));
1351 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1352 }
1353
1354 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1355 enum pipe pipe)
1356 {
1357 int reg;
1358 u32 val;
1359 bool enabled;
1360
1361 reg = PCH_TRANSCONF(pipe);
1362 val = I915_READ(reg);
1363 enabled = !!(val & TRANS_ENABLE);
1364 WARN(enabled,
1365 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1366 pipe_name(pipe));
1367 }
1368
1369 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1370 enum pipe pipe, u32 port_sel, u32 val)
1371 {
1372 if ((val & DP_PORT_EN) == 0)
1373 return false;
1374
1375 if (HAS_PCH_CPT(dev_priv->dev)) {
1376 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1377 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1378 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1379 return false;
1380 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1381 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1382 return false;
1383 } else {
1384 if ((val & DP_PIPE_MASK) != (pipe << 30))
1385 return false;
1386 }
1387 return true;
1388 }
1389
1390 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1391 enum pipe pipe, u32 val)
1392 {
1393 if ((val & SDVO_ENABLE) == 0)
1394 return false;
1395
1396 if (HAS_PCH_CPT(dev_priv->dev)) {
1397 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1398 return false;
1399 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1400 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1401 return false;
1402 } else {
1403 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1404 return false;
1405 }
1406 return true;
1407 }
1408
1409 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1410 enum pipe pipe, u32 val)
1411 {
1412 if ((val & LVDS_PORT_EN) == 0)
1413 return false;
1414
1415 if (HAS_PCH_CPT(dev_priv->dev)) {
1416 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1417 return false;
1418 } else {
1419 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1420 return false;
1421 }
1422 return true;
1423 }
1424
1425 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1426 enum pipe pipe, u32 val)
1427 {
1428 if ((val & ADPA_DAC_ENABLE) == 0)
1429 return false;
1430 if (HAS_PCH_CPT(dev_priv->dev)) {
1431 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1432 return false;
1433 } else {
1434 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1435 return false;
1436 }
1437 return true;
1438 }
1439
1440 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1441 enum pipe pipe, int reg, u32 port_sel)
1442 {
1443 u32 val = I915_READ(reg);
1444 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1445 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1446 reg, pipe_name(pipe));
1447
1448 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1449 && (val & DP_PIPEB_SELECT),
1450 "IBX PCH dp port still using transcoder B\n");
1451 }
1452
1453 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1454 enum pipe pipe, int reg)
1455 {
1456 u32 val = I915_READ(reg);
1457 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1458 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1459 reg, pipe_name(pipe));
1460
1461 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1462 && (val & SDVO_PIPE_B_SELECT),
1463 "IBX PCH hdmi port still using transcoder B\n");
1464 }
1465
1466 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1467 enum pipe pipe)
1468 {
1469 int reg;
1470 u32 val;
1471
1472 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1473 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1474 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1475
1476 reg = PCH_ADPA;
1477 val = I915_READ(reg);
1478 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1479 "PCH VGA enabled on transcoder %c, should be disabled\n",
1480 pipe_name(pipe));
1481
1482 reg = PCH_LVDS;
1483 val = I915_READ(reg);
1484 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1485 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1486 pipe_name(pipe));
1487
1488 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1489 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1490 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1491 }
1492
1493 static void intel_init_dpio(struct drm_device *dev)
1494 {
1495 struct drm_i915_private *dev_priv = dev->dev_private;
1496
1497 if (!IS_VALLEYVIEW(dev))
1498 return;
1499
1500 /*
1501 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1502 * CHV x1 PHY (DP/HDMI D)
1503 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1504 */
1505 if (IS_CHERRYVIEW(dev)) {
1506 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1507 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1508 } else {
1509 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1510 }
1511 }
1512
1513 static void intel_reset_dpio(struct drm_device *dev)
1514 {
1515 struct drm_i915_private *dev_priv = dev->dev_private;
1516
1517 if (IS_CHERRYVIEW(dev)) {
1518 enum dpio_phy phy;
1519 u32 val;
1520
1521 for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) {
1522 /* Poll for phypwrgood signal */
1523 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) &
1524 PHY_POWERGOOD(phy), 1))
1525 DRM_ERROR("Display PHY %d is not power up\n", phy);
1526
1527 /*
1528 * Deassert common lane reset for PHY.
1529 *
1530 * This should only be done on init and resume from S3
1531 * with both PLLs disabled, or we risk losing DPIO and
1532 * PLL synchronization.
1533 */
1534 val = I915_READ(DISPLAY_PHY_CONTROL);
1535 I915_WRITE(DISPLAY_PHY_CONTROL,
1536 PHY_COM_LANE_RESET_DEASSERT(phy, val));
1537 }
1538 }
1539 }
1540
1541 static void vlv_enable_pll(struct intel_crtc *crtc)
1542 {
1543 struct drm_device *dev = crtc->base.dev;
1544 struct drm_i915_private *dev_priv = dev->dev_private;
1545 int reg = DPLL(crtc->pipe);
1546 u32 dpll = crtc->config.dpll_hw_state.dpll;
1547
1548 assert_pipe_disabled(dev_priv, crtc->pipe);
1549
1550 /* No really, not for ILK+ */
1551 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1552
1553 /* PLL is protected by panel, make sure we can write it */
1554 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1555 assert_panel_unlocked(dev_priv, crtc->pipe);
1556
1557 I915_WRITE(reg, dpll);
1558 POSTING_READ(reg);
1559 udelay(150);
1560
1561 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1562 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1563
1564 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1565 POSTING_READ(DPLL_MD(crtc->pipe));
1566
1567 /* We do this three times for luck */
1568 I915_WRITE(reg, dpll);
1569 POSTING_READ(reg);
1570 udelay(150); /* wait for warmup */
1571 I915_WRITE(reg, dpll);
1572 POSTING_READ(reg);
1573 udelay(150); /* wait for warmup */
1574 I915_WRITE(reg, dpll);
1575 POSTING_READ(reg);
1576 udelay(150); /* wait for warmup */
1577 }
1578
1579 static void chv_enable_pll(struct intel_crtc *crtc)
1580 {
1581 struct drm_device *dev = crtc->base.dev;
1582 struct drm_i915_private *dev_priv = dev->dev_private;
1583 int pipe = crtc->pipe;
1584 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1585 u32 tmp;
1586
1587 assert_pipe_disabled(dev_priv, crtc->pipe);
1588
1589 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1590
1591 mutex_lock(&dev_priv->dpio_lock);
1592
1593 /* Enable back the 10bit clock to display controller */
1594 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1595 tmp |= DPIO_DCLKP_EN;
1596 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1597
1598 /*
1599 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1600 */
1601 udelay(1);
1602
1603 /* Enable PLL */
1604 I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
1605
1606 /* Check PLL is locked */
1607 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1608 DRM_ERROR("PLL %d failed to lock\n", pipe);
1609
1610 /* not sure when this should be written */
1611 I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
1612 POSTING_READ(DPLL_MD(pipe));
1613
1614 mutex_unlock(&dev_priv->dpio_lock);
1615 }
1616
1617 static void i9xx_enable_pll(struct intel_crtc *crtc)
1618 {
1619 struct drm_device *dev = crtc->base.dev;
1620 struct drm_i915_private *dev_priv = dev->dev_private;
1621 int reg = DPLL(crtc->pipe);
1622 u32 dpll = crtc->config.dpll_hw_state.dpll;
1623
1624 assert_pipe_disabled(dev_priv, crtc->pipe);
1625
1626 /* No really, not for ILK+ */
1627 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1628
1629 /* PLL is protected by panel, make sure we can write it */
1630 if (IS_MOBILE(dev) && !IS_I830(dev))
1631 assert_panel_unlocked(dev_priv, crtc->pipe);
1632
1633 I915_WRITE(reg, dpll);
1634
1635 /* Wait for the clocks to stabilize. */
1636 POSTING_READ(reg);
1637 udelay(150);
1638
1639 if (INTEL_INFO(dev)->gen >= 4) {
1640 I915_WRITE(DPLL_MD(crtc->pipe),
1641 crtc->config.dpll_hw_state.dpll_md);
1642 } else {
1643 /* The pixel multiplier can only be updated once the
1644 * DPLL is enabled and the clocks are stable.
1645 *
1646 * So write it again.
1647 */
1648 I915_WRITE(reg, dpll);
1649 }
1650
1651 /* We do this three times for luck */
1652 I915_WRITE(reg, dpll);
1653 POSTING_READ(reg);
1654 udelay(150); /* wait for warmup */
1655 I915_WRITE(reg, dpll);
1656 POSTING_READ(reg);
1657 udelay(150); /* wait for warmup */
1658 I915_WRITE(reg, dpll);
1659 POSTING_READ(reg);
1660 udelay(150); /* wait for warmup */
1661 }
1662
1663 /**
1664 * i9xx_disable_pll - disable a PLL
1665 * @dev_priv: i915 private structure
1666 * @pipe: pipe PLL to disable
1667 *
1668 * Disable the PLL for @pipe, making sure the pipe is off first.
1669 *
1670 * Note! This is for pre-ILK only.
1671 */
1672 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1673 {
1674 /* Don't disable pipe A or pipe A PLLs if needed */
1675 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1676 return;
1677
1678 /* Make sure the pipe isn't still relying on us */
1679 assert_pipe_disabled(dev_priv, pipe);
1680
1681 I915_WRITE(DPLL(pipe), 0);
1682 POSTING_READ(DPLL(pipe));
1683 }
1684
1685 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1686 {
1687 u32 val = 0;
1688
1689 /* Make sure the pipe isn't still relying on us */
1690 assert_pipe_disabled(dev_priv, pipe);
1691
1692 /*
1693 * Leave integrated clock source and reference clock enabled for pipe B.
1694 * The latter is needed for VGA hotplug / manual detection.
1695 */
1696 if (pipe == PIPE_B)
1697 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1698 I915_WRITE(DPLL(pipe), val);
1699 POSTING_READ(DPLL(pipe));
1700
1701 }
1702
1703 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1704 {
1705 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1706 u32 val;
1707
1708 /* Make sure the pipe isn't still relying on us */
1709 assert_pipe_disabled(dev_priv, pipe);
1710
1711 /* Set PLL en = 0 */
1712 val = DPLL_SSC_REF_CLOCK_CHV;
1713 if (pipe != PIPE_A)
1714 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1715 I915_WRITE(DPLL(pipe), val);
1716 POSTING_READ(DPLL(pipe));
1717
1718 mutex_lock(&dev_priv->dpio_lock);
1719
1720 /* Disable 10bit clock to display controller */
1721 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1722 val &= ~DPIO_DCLKP_EN;
1723 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1724
1725 /* disable left/right clock distribution */
1726 if (pipe != PIPE_B) {
1727 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1728 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1729 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1730 } else {
1731 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1732 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1733 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1734 }
1735
1736 mutex_unlock(&dev_priv->dpio_lock);
1737 }
1738
1739 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1740 struct intel_digital_port *dport)
1741 {
1742 u32 port_mask;
1743 int dpll_reg;
1744
1745 switch (dport->port) {
1746 case PORT_B:
1747 port_mask = DPLL_PORTB_READY_MASK;
1748 dpll_reg = DPLL(0);
1749 break;
1750 case PORT_C:
1751 port_mask = DPLL_PORTC_READY_MASK;
1752 dpll_reg = DPLL(0);
1753 break;
1754 case PORT_D:
1755 port_mask = DPLL_PORTD_READY_MASK;
1756 dpll_reg = DPIO_PHY_STATUS;
1757 break;
1758 default:
1759 BUG();
1760 }
1761
1762 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1763 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1764 port_name(dport->port), I915_READ(dpll_reg));
1765 }
1766
1767 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1768 {
1769 struct drm_device *dev = crtc->base.dev;
1770 struct drm_i915_private *dev_priv = dev->dev_private;
1771 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1772
1773 if (WARN_ON(pll == NULL))
1774 return;
1775
1776 WARN_ON(!pll->refcount);
1777 if (pll->active == 0) {
1778 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1779 WARN_ON(pll->on);
1780 assert_shared_dpll_disabled(dev_priv, pll);
1781
1782 pll->mode_set(dev_priv, pll);
1783 }
1784 }
1785
1786 /**
1787 * intel_enable_shared_dpll - enable PCH PLL
1788 * @dev_priv: i915 private structure
1789 * @pipe: pipe PLL to enable
1790 *
1791 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1792 * drives the transcoder clock.
1793 */
1794 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1795 {
1796 struct drm_device *dev = crtc->base.dev;
1797 struct drm_i915_private *dev_priv = dev->dev_private;
1798 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1799
1800 if (WARN_ON(pll == NULL))
1801 return;
1802
1803 if (WARN_ON(pll->refcount == 0))
1804 return;
1805
1806 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1807 pll->name, pll->active, pll->on,
1808 crtc->base.base.id);
1809
1810 if (pll->active++) {
1811 WARN_ON(!pll->on);
1812 assert_shared_dpll_enabled(dev_priv, pll);
1813 return;
1814 }
1815 WARN_ON(pll->on);
1816
1817 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1818
1819 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1820 pll->enable(dev_priv, pll);
1821 pll->on = true;
1822 }
1823
1824 void intel_disable_shared_dpll(struct intel_crtc *crtc)
1825 {
1826 struct drm_device *dev = crtc->base.dev;
1827 struct drm_i915_private *dev_priv = dev->dev_private;
1828 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1829
1830 /* PCH only available on ILK+ */
1831 BUG_ON(INTEL_INFO(dev)->gen < 5);
1832 if (WARN_ON(pll == NULL))
1833 return;
1834
1835 if (WARN_ON(pll->refcount == 0))
1836 return;
1837
1838 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1839 pll->name, pll->active, pll->on,
1840 crtc->base.base.id);
1841
1842 if (WARN_ON(pll->active == 0)) {
1843 assert_shared_dpll_disabled(dev_priv, pll);
1844 return;
1845 }
1846
1847 assert_shared_dpll_enabled(dev_priv, pll);
1848 WARN_ON(!pll->on);
1849 if (--pll->active)
1850 return;
1851
1852 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1853 pll->disable(dev_priv, pll);
1854 pll->on = false;
1855
1856 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1857 }
1858
1859 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1860 enum pipe pipe)
1861 {
1862 struct drm_device *dev = dev_priv->dev;
1863 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1864 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1865 uint32_t reg, val, pipeconf_val;
1866
1867 /* PCH only available on ILK+ */
1868 BUG_ON(INTEL_INFO(dev)->gen < 5);
1869
1870 /* Make sure PCH DPLL is enabled */
1871 assert_shared_dpll_enabled(dev_priv,
1872 intel_crtc_to_shared_dpll(intel_crtc));
1873
1874 /* FDI must be feeding us bits for PCH ports */
1875 assert_fdi_tx_enabled(dev_priv, pipe);
1876 assert_fdi_rx_enabled(dev_priv, pipe);
1877
1878 if (HAS_PCH_CPT(dev)) {
1879 /* Workaround: Set the timing override bit before enabling the
1880 * pch transcoder. */
1881 reg = TRANS_CHICKEN2(pipe);
1882 val = I915_READ(reg);
1883 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1884 I915_WRITE(reg, val);
1885 }
1886
1887 reg = PCH_TRANSCONF(pipe);
1888 val = I915_READ(reg);
1889 pipeconf_val = I915_READ(PIPECONF(pipe));
1890
1891 if (HAS_PCH_IBX(dev_priv->dev)) {
1892 /*
1893 * make the BPC in transcoder be consistent with
1894 * that in pipeconf reg.
1895 */
1896 val &= ~PIPECONF_BPC_MASK;
1897 val |= pipeconf_val & PIPECONF_BPC_MASK;
1898 }
1899
1900 val &= ~TRANS_INTERLACE_MASK;
1901 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1902 if (HAS_PCH_IBX(dev_priv->dev) &&
1903 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1904 val |= TRANS_LEGACY_INTERLACED_ILK;
1905 else
1906 val |= TRANS_INTERLACED;
1907 else
1908 val |= TRANS_PROGRESSIVE;
1909
1910 I915_WRITE(reg, val | TRANS_ENABLE);
1911 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1912 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1913 }
1914
1915 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1916 enum transcoder cpu_transcoder)
1917 {
1918 u32 val, pipeconf_val;
1919
1920 /* PCH only available on ILK+ */
1921 BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1922
1923 /* FDI must be feeding us bits for PCH ports */
1924 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1925 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1926
1927 /* Workaround: set timing override bit. */
1928 val = I915_READ(_TRANSA_CHICKEN2);
1929 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1930 I915_WRITE(_TRANSA_CHICKEN2, val);
1931
1932 val = TRANS_ENABLE;
1933 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1934
1935 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1936 PIPECONF_INTERLACED_ILK)
1937 val |= TRANS_INTERLACED;
1938 else
1939 val |= TRANS_PROGRESSIVE;
1940
1941 I915_WRITE(LPT_TRANSCONF, val);
1942 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1943 DRM_ERROR("Failed to enable PCH transcoder\n");
1944 }
1945
1946 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1947 enum pipe pipe)
1948 {
1949 struct drm_device *dev = dev_priv->dev;
1950 uint32_t reg, val;
1951
1952 /* FDI relies on the transcoder */
1953 assert_fdi_tx_disabled(dev_priv, pipe);
1954 assert_fdi_rx_disabled(dev_priv, pipe);
1955
1956 /* Ports must be off as well */
1957 assert_pch_ports_disabled(dev_priv, pipe);
1958
1959 reg = PCH_TRANSCONF(pipe);
1960 val = I915_READ(reg);
1961 val &= ~TRANS_ENABLE;
1962 I915_WRITE(reg, val);
1963 /* wait for PCH transcoder off, transcoder state */
1964 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1965 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1966
1967 if (!HAS_PCH_IBX(dev)) {
1968 /* Workaround: Clear the timing override chicken bit again. */
1969 reg = TRANS_CHICKEN2(pipe);
1970 val = I915_READ(reg);
1971 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1972 I915_WRITE(reg, val);
1973 }
1974 }
1975
1976 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1977 {
1978 u32 val;
1979
1980 val = I915_READ(LPT_TRANSCONF);
1981 val &= ~TRANS_ENABLE;
1982 I915_WRITE(LPT_TRANSCONF, val);
1983 /* wait for PCH transcoder off, transcoder state */
1984 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1985 DRM_ERROR("Failed to disable PCH transcoder\n");
1986
1987 /* Workaround: clear timing override bit. */
1988 val = I915_READ(_TRANSA_CHICKEN2);
1989 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1990 I915_WRITE(_TRANSA_CHICKEN2, val);
1991 }
1992
1993 /**
1994 * intel_enable_pipe - enable a pipe, asserting requirements
1995 * @crtc: crtc responsible for the pipe
1996 *
1997 * Enable @crtc's pipe, making sure that various hardware specific requirements
1998 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1999 */
2000 static void intel_enable_pipe(struct intel_crtc *crtc)
2001 {
2002 struct drm_device *dev = crtc->base.dev;
2003 struct drm_i915_private *dev_priv = dev->dev_private;
2004 enum pipe pipe = crtc->pipe;
2005 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2006 pipe);
2007 enum pipe pch_transcoder;
2008 int reg;
2009 u32 val;
2010
2011 assert_planes_disabled(dev_priv, pipe);
2012 assert_cursor_disabled(dev_priv, pipe);
2013 assert_sprites_disabled(dev_priv, pipe);
2014
2015 if (HAS_PCH_LPT(dev_priv->dev))
2016 pch_transcoder = TRANSCODER_A;
2017 else
2018 pch_transcoder = pipe;
2019
2020 /*
2021 * A pipe without a PLL won't actually be able to drive bits from
2022 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2023 * need the check.
2024 */
2025 if (!HAS_PCH_SPLIT(dev_priv->dev))
2026 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
2027 assert_dsi_pll_enabled(dev_priv);
2028 else
2029 assert_pll_enabled(dev_priv, pipe);
2030 else {
2031 if (crtc->config.has_pch_encoder) {
2032 /* if driving the PCH, we need FDI enabled */
2033 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2034 assert_fdi_tx_pll_enabled(dev_priv,
2035 (enum pipe) cpu_transcoder);
2036 }
2037 /* FIXME: assert CPU port conditions for SNB+ */
2038 }
2039
2040 reg = PIPECONF(cpu_transcoder);
2041 val = I915_READ(reg);
2042 if (val & PIPECONF_ENABLE) {
2043 WARN_ON(!(pipe == PIPE_A &&
2044 dev_priv->quirks & QUIRK_PIPEA_FORCE));
2045 return;
2046 }
2047
2048 I915_WRITE(reg, val | PIPECONF_ENABLE);
2049 POSTING_READ(reg);
2050 }
2051
2052 /**
2053 * intel_disable_pipe - disable a pipe, asserting requirements
2054 * @dev_priv: i915 private structure
2055 * @pipe: pipe to disable
2056 *
2057 * Disable @pipe, making sure that various hardware specific requirements
2058 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
2059 *
2060 * @pipe should be %PIPE_A or %PIPE_B.
2061 *
2062 * Will wait until the pipe has shut down before returning.
2063 */
2064 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
2065 enum pipe pipe)
2066 {
2067 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2068 pipe);
2069 int reg;
2070 u32 val;
2071
2072 /*
2073 * Make sure planes won't keep trying to pump pixels to us,
2074 * or we might hang the display.
2075 */
2076 assert_planes_disabled(dev_priv, pipe);
2077 assert_cursor_disabled(dev_priv, pipe);
2078 assert_sprites_disabled(dev_priv, pipe);
2079
2080 /* Don't disable pipe A or pipe A PLLs if needed */
2081 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2082 return;
2083
2084 reg = PIPECONF(cpu_transcoder);
2085 val = I915_READ(reg);
2086 if ((val & PIPECONF_ENABLE) == 0)
2087 return;
2088
2089 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
2090 intel_wait_for_pipe_off(dev_priv->dev, pipe);
2091 }
2092
2093 /*
2094 * Plane regs are double buffered, going from enabled->disabled needs a
2095 * trigger in order to latch. The display address reg provides this.
2096 */
2097 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2098 enum plane plane)
2099 {
2100 struct drm_device *dev = dev_priv->dev;
2101 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2102
2103 I915_WRITE(reg, I915_READ(reg));
2104 POSTING_READ(reg);
2105 }
2106
2107 /**
2108 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2109 * @dev_priv: i915 private structure
2110 * @plane: plane to enable
2111 * @pipe: pipe being fed
2112 *
2113 * Enable @plane on @pipe, making sure that @pipe is running first.
2114 */
2115 static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
2116 enum plane plane, enum pipe pipe)
2117 {
2118 struct drm_device *dev = dev_priv->dev;
2119 struct intel_crtc *intel_crtc =
2120 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2121 int reg;
2122 u32 val;
2123
2124 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2125 assert_pipe_enabled(dev_priv, pipe);
2126
2127 if (intel_crtc->primary_enabled)
2128 return;
2129
2130 intel_crtc->primary_enabled = true;
2131
2132 reg = DSPCNTR(plane);
2133 val = I915_READ(reg);
2134 WARN_ON(val & DISPLAY_PLANE_ENABLE);
2135
2136 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
2137 intel_flush_primary_plane(dev_priv, plane);
2138
2139 /*
2140 * BDW signals flip done immediately if the plane
2141 * is disabled, even if the plane enable is already
2142 * armed to occur at the next vblank :(
2143 */
2144 if (IS_BROADWELL(dev))
2145 intel_wait_for_vblank(dev, intel_crtc->pipe);
2146 }
2147
2148 /**
2149 * intel_disable_primary_hw_plane - disable the primary hardware plane
2150 * @dev_priv: i915 private structure
2151 * @plane: plane to disable
2152 * @pipe: pipe consuming the data
2153 *
2154 * Disable @plane; should be an independent operation.
2155 */
2156 static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
2157 enum plane plane, enum pipe pipe)
2158 {
2159 struct intel_crtc *intel_crtc =
2160 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2161 int reg;
2162 u32 val;
2163
2164 if (!intel_crtc->primary_enabled)
2165 return;
2166
2167 intel_crtc->primary_enabled = false;
2168
2169 reg = DSPCNTR(plane);
2170 val = I915_READ(reg);
2171 WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0);
2172
2173 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
2174 intel_flush_primary_plane(dev_priv, plane);
2175 }
2176
2177 static bool need_vtd_wa(struct drm_device *dev)
2178 {
2179 #ifdef CONFIG_INTEL_IOMMU
2180 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2181 return true;
2182 #endif
2183 return false;
2184 }
2185
2186 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2187 {
2188 int tile_height;
2189
2190 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2191 return ALIGN(height, tile_height);
2192 }
2193
2194 int
2195 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2196 struct drm_i915_gem_object *obj,
2197 struct intel_engine_cs *pipelined)
2198 {
2199 struct drm_i915_private *dev_priv = dev->dev_private;
2200 u32 alignment;
2201 int ret;
2202
2203 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2204
2205 switch (obj->tiling_mode) {
2206 case I915_TILING_NONE:
2207 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2208 alignment = 128 * 1024;
2209 else if (INTEL_INFO(dev)->gen >= 4)
2210 alignment = 4 * 1024;
2211 else
2212 alignment = 64 * 1024;
2213 break;
2214 case I915_TILING_X:
2215 /* pin() will align the object as required by fence */
2216 alignment = 0;
2217 break;
2218 case I915_TILING_Y:
2219 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2220 return -EINVAL;
2221 default:
2222 BUG();
2223 }
2224
2225 /* Note that the w/a also requires 64 PTE of padding following the
2226 * bo. We currently fill all unused PTE with the shadow page and so
2227 * we should always have valid PTE following the scanout preventing
2228 * the VT-d warning.
2229 */
2230 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2231 alignment = 256 * 1024;
2232
2233 dev_priv->mm.interruptible = false;
2234 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2235 if (ret)
2236 goto err_interruptible;
2237
2238 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2239 * fence, whereas 965+ only requires a fence if using
2240 * framebuffer compression. For simplicity, we always install
2241 * a fence as the cost is not that onerous.
2242 */
2243 ret = i915_gem_object_get_fence(obj);
2244 if (ret)
2245 goto err_unpin;
2246
2247 i915_gem_object_pin_fence(obj);
2248
2249 dev_priv->mm.interruptible = true;
2250 return 0;
2251
2252 err_unpin:
2253 i915_gem_object_unpin_from_display_plane(obj);
2254 err_interruptible:
2255 dev_priv->mm.interruptible = true;
2256 return ret;
2257 }
2258
2259 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2260 {
2261 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2262
2263 i915_gem_object_unpin_fence(obj);
2264 i915_gem_object_unpin_from_display_plane(obj);
2265 }
2266
2267 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2268 * is assumed to be a power-of-two. */
2269 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2270 unsigned int tiling_mode,
2271 unsigned int cpp,
2272 unsigned int pitch)
2273 {
2274 if (tiling_mode != I915_TILING_NONE) {
2275 unsigned int tile_rows, tiles;
2276
2277 tile_rows = *y / 8;
2278 *y %= 8;
2279
2280 tiles = *x / (512/cpp);
2281 *x %= 512/cpp;
2282
2283 return tile_rows * pitch * 8 + tiles * 4096;
2284 } else {
2285 unsigned int offset;
2286
2287 offset = *y * pitch + *x * cpp;
2288 *y = 0;
2289 *x = (offset & 4095) / cpp;
2290 return offset & -4096;
2291 }
2292 }
2293
2294 int intel_format_to_fourcc(int format)
2295 {
2296 switch (format) {
2297 case DISPPLANE_8BPP:
2298 return DRM_FORMAT_C8;
2299 case DISPPLANE_BGRX555:
2300 return DRM_FORMAT_XRGB1555;
2301 case DISPPLANE_BGRX565:
2302 return DRM_FORMAT_RGB565;
2303 default:
2304 case DISPPLANE_BGRX888:
2305 return DRM_FORMAT_XRGB8888;
2306 case DISPPLANE_RGBX888:
2307 return DRM_FORMAT_XBGR8888;
2308 case DISPPLANE_BGRX101010:
2309 return DRM_FORMAT_XRGB2101010;
2310 case DISPPLANE_RGBX101010:
2311 return DRM_FORMAT_XBGR2101010;
2312 }
2313 }
2314
2315 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2316 struct intel_plane_config *plane_config)
2317 {
2318 struct drm_device *dev = crtc->base.dev;
2319 struct drm_i915_gem_object *obj = NULL;
2320 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2321 u32 base = plane_config->base;
2322
2323 if (plane_config->size == 0)
2324 return false;
2325
2326 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2327 plane_config->size);
2328 if (!obj)
2329 return false;
2330
2331 if (plane_config->tiled) {
2332 obj->tiling_mode = I915_TILING_X;
2333 obj->stride = crtc->base.primary->fb->pitches[0];
2334 }
2335
2336 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2337 mode_cmd.width = crtc->base.primary->fb->width;
2338 mode_cmd.height = crtc->base.primary->fb->height;
2339 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2340
2341 mutex_lock(&dev->struct_mutex);
2342
2343 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2344 &mode_cmd, obj)) {
2345 DRM_DEBUG_KMS("intel fb init failed\n");
2346 goto out_unref_obj;
2347 }
2348
2349 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2350 mutex_unlock(&dev->struct_mutex);
2351
2352 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2353 return true;
2354
2355 out_unref_obj:
2356 drm_gem_object_unreference(&obj->base);
2357 mutex_unlock(&dev->struct_mutex);
2358 return false;
2359 }
2360
2361 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2362 struct intel_plane_config *plane_config)
2363 {
2364 struct drm_device *dev = intel_crtc->base.dev;
2365 struct drm_crtc *c;
2366 struct intel_crtc *i;
2367 struct drm_i915_gem_object *obj;
2368
2369 if (!intel_crtc->base.primary->fb)
2370 return;
2371
2372 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2373 return;
2374
2375 kfree(intel_crtc->base.primary->fb);
2376 intel_crtc->base.primary->fb = NULL;
2377
2378 /*
2379 * Failed to alloc the obj, check to see if we should share
2380 * an fb with another CRTC instead
2381 */
2382 for_each_crtc(dev, c) {
2383 i = to_intel_crtc(c);
2384
2385 if (c == &intel_crtc->base)
2386 continue;
2387
2388 if (!i->active)
2389 continue;
2390
2391 obj = intel_fb_obj(c->primary->fb);
2392 if (obj == NULL)
2393 continue;
2394
2395 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2396 drm_framebuffer_reference(c->primary->fb);
2397 intel_crtc->base.primary->fb = c->primary->fb;
2398 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2399 break;
2400 }
2401 }
2402 }
2403
2404 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2405 struct drm_framebuffer *fb,
2406 int x, int y)
2407 {
2408 struct drm_device *dev = crtc->dev;
2409 struct drm_i915_private *dev_priv = dev->dev_private;
2410 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2411 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2412 int plane = intel_crtc->plane;
2413 unsigned long linear_offset;
2414 u32 dspcntr;
2415 u32 reg;
2416
2417 reg = DSPCNTR(plane);
2418 dspcntr = I915_READ(reg);
2419 /* Mask out pixel format bits in case we change it */
2420 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2421 switch (fb->pixel_format) {
2422 case DRM_FORMAT_C8:
2423 dspcntr |= DISPPLANE_8BPP;
2424 break;
2425 case DRM_FORMAT_XRGB1555:
2426 case DRM_FORMAT_ARGB1555:
2427 dspcntr |= DISPPLANE_BGRX555;
2428 break;
2429 case DRM_FORMAT_RGB565:
2430 dspcntr |= DISPPLANE_BGRX565;
2431 break;
2432 case DRM_FORMAT_XRGB8888:
2433 case DRM_FORMAT_ARGB8888:
2434 dspcntr |= DISPPLANE_BGRX888;
2435 break;
2436 case DRM_FORMAT_XBGR8888:
2437 case DRM_FORMAT_ABGR8888:
2438 dspcntr |= DISPPLANE_RGBX888;
2439 break;
2440 case DRM_FORMAT_XRGB2101010:
2441 case DRM_FORMAT_ARGB2101010:
2442 dspcntr |= DISPPLANE_BGRX101010;
2443 break;
2444 case DRM_FORMAT_XBGR2101010:
2445 case DRM_FORMAT_ABGR2101010:
2446 dspcntr |= DISPPLANE_RGBX101010;
2447 break;
2448 default:
2449 BUG();
2450 }
2451
2452 if (INTEL_INFO(dev)->gen >= 4) {
2453 if (obj->tiling_mode != I915_TILING_NONE)
2454 dspcntr |= DISPPLANE_TILED;
2455 else
2456 dspcntr &= ~DISPPLANE_TILED;
2457 }
2458
2459 if (IS_G4X(dev))
2460 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2461
2462 I915_WRITE(reg, dspcntr);
2463
2464 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2465
2466 if (INTEL_INFO(dev)->gen >= 4) {
2467 intel_crtc->dspaddr_offset =
2468 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2469 fb->bits_per_pixel / 8,
2470 fb->pitches[0]);
2471 linear_offset -= intel_crtc->dspaddr_offset;
2472 } else {
2473 intel_crtc->dspaddr_offset = linear_offset;
2474 }
2475
2476 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2477 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2478 fb->pitches[0]);
2479 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2480 if (INTEL_INFO(dev)->gen >= 4) {
2481 I915_WRITE(DSPSURF(plane),
2482 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2483 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2484 I915_WRITE(DSPLINOFF(plane), linear_offset);
2485 } else
2486 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2487 POSTING_READ(reg);
2488 }
2489
2490 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2491 struct drm_framebuffer *fb,
2492 int x, int y)
2493 {
2494 struct drm_device *dev = crtc->dev;
2495 struct drm_i915_private *dev_priv = dev->dev_private;
2496 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2497 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2498 int plane = intel_crtc->plane;
2499 unsigned long linear_offset;
2500 u32 dspcntr;
2501 u32 reg;
2502
2503 reg = DSPCNTR(plane);
2504 dspcntr = I915_READ(reg);
2505 /* Mask out pixel format bits in case we change it */
2506 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2507 switch (fb->pixel_format) {
2508 case DRM_FORMAT_C8:
2509 dspcntr |= DISPPLANE_8BPP;
2510 break;
2511 case DRM_FORMAT_RGB565:
2512 dspcntr |= DISPPLANE_BGRX565;
2513 break;
2514 case DRM_FORMAT_XRGB8888:
2515 case DRM_FORMAT_ARGB8888:
2516 dspcntr |= DISPPLANE_BGRX888;
2517 break;
2518 case DRM_FORMAT_XBGR8888:
2519 case DRM_FORMAT_ABGR8888:
2520 dspcntr |= DISPPLANE_RGBX888;
2521 break;
2522 case DRM_FORMAT_XRGB2101010:
2523 case DRM_FORMAT_ARGB2101010:
2524 dspcntr |= DISPPLANE_BGRX101010;
2525 break;
2526 case DRM_FORMAT_XBGR2101010:
2527 case DRM_FORMAT_ABGR2101010:
2528 dspcntr |= DISPPLANE_RGBX101010;
2529 break;
2530 default:
2531 BUG();
2532 }
2533
2534 if (obj->tiling_mode != I915_TILING_NONE)
2535 dspcntr |= DISPPLANE_TILED;
2536 else
2537 dspcntr &= ~DISPPLANE_TILED;
2538
2539 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2540 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2541 else
2542 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2543
2544 I915_WRITE(reg, dspcntr);
2545
2546 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2547 intel_crtc->dspaddr_offset =
2548 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2549 fb->bits_per_pixel / 8,
2550 fb->pitches[0]);
2551 linear_offset -= intel_crtc->dspaddr_offset;
2552
2553 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2554 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2555 fb->pitches[0]);
2556 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2557 I915_WRITE(DSPSURF(plane),
2558 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2559 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2560 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2561 } else {
2562 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2563 I915_WRITE(DSPLINOFF(plane), linear_offset);
2564 }
2565 POSTING_READ(reg);
2566 }
2567
2568 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2569 static int
2570 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2571 int x, int y, enum mode_set_atomic state)
2572 {
2573 struct drm_device *dev = crtc->dev;
2574 struct drm_i915_private *dev_priv = dev->dev_private;
2575
2576 if (dev_priv->display.disable_fbc)
2577 dev_priv->display.disable_fbc(dev);
2578 intel_increase_pllclock(dev, to_intel_crtc(crtc)->pipe);
2579
2580 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2581
2582 return 0;
2583 }
2584
2585 void intel_display_handle_reset(struct drm_device *dev)
2586 {
2587 struct drm_i915_private *dev_priv = dev->dev_private;
2588 struct drm_crtc *crtc;
2589
2590 /*
2591 * Flips in the rings have been nuked by the reset,
2592 * so complete all pending flips so that user space
2593 * will get its events and not get stuck.
2594 *
2595 * Also update the base address of all primary
2596 * planes to the the last fb to make sure we're
2597 * showing the correct fb after a reset.
2598 *
2599 * Need to make two loops over the crtcs so that we
2600 * don't try to grab a crtc mutex before the
2601 * pending_flip_queue really got woken up.
2602 */
2603
2604 for_each_crtc(dev, crtc) {
2605 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2606 enum plane plane = intel_crtc->plane;
2607
2608 intel_prepare_page_flip(dev, plane);
2609 intel_finish_page_flip_plane(dev, plane);
2610 }
2611
2612 for_each_crtc(dev, crtc) {
2613 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2614
2615 drm_modeset_lock(&crtc->mutex, NULL);
2616 /*
2617 * FIXME: Once we have proper support for primary planes (and
2618 * disabling them without disabling the entire crtc) allow again
2619 * a NULL crtc->primary->fb.
2620 */
2621 if (intel_crtc->active && crtc->primary->fb)
2622 dev_priv->display.update_primary_plane(crtc,
2623 crtc->primary->fb,
2624 crtc->x,
2625 crtc->y);
2626 drm_modeset_unlock(&crtc->mutex);
2627 }
2628 }
2629
2630 static int
2631 intel_finish_fb(struct drm_framebuffer *old_fb)
2632 {
2633 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2634 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2635 bool was_interruptible = dev_priv->mm.interruptible;
2636 int ret;
2637
2638 /* Big Hammer, we also need to ensure that any pending
2639 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2640 * current scanout is retired before unpinning the old
2641 * framebuffer.
2642 *
2643 * This should only fail upon a hung GPU, in which case we
2644 * can safely continue.
2645 */
2646 dev_priv->mm.interruptible = false;
2647 ret = i915_gem_object_finish_gpu(obj);
2648 dev_priv->mm.interruptible = was_interruptible;
2649
2650 return ret;
2651 }
2652
2653 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2654 {
2655 struct drm_device *dev = crtc->dev;
2656 struct drm_i915_private *dev_priv = dev->dev_private;
2657 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2658 unsigned long flags;
2659 bool pending;
2660
2661 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2662 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2663 return false;
2664
2665 spin_lock_irqsave(&dev->event_lock, flags);
2666 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2667 spin_unlock_irqrestore(&dev->event_lock, flags);
2668
2669 return pending;
2670 }
2671
2672 static int
2673 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2674 struct drm_framebuffer *fb)
2675 {
2676 struct drm_device *dev = crtc->dev;
2677 struct drm_i915_private *dev_priv = dev->dev_private;
2678 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2679 enum pipe pipe = intel_crtc->pipe;
2680 struct drm_framebuffer *old_fb = crtc->primary->fb;
2681 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2682 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
2683 int ret;
2684
2685 if (intel_crtc_has_pending_flip(crtc)) {
2686 DRM_ERROR("pipe is still busy with an old pageflip\n");
2687 return -EBUSY;
2688 }
2689
2690 /* no fb bound */
2691 if (!fb) {
2692 DRM_ERROR("No FB bound\n");
2693 return 0;
2694 }
2695
2696 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2697 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2698 plane_name(intel_crtc->plane),
2699 INTEL_INFO(dev)->num_pipes);
2700 return -EINVAL;
2701 }
2702
2703 mutex_lock(&dev->struct_mutex);
2704 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
2705 if (ret == 0)
2706 i915_gem_track_fb(old_obj, obj,
2707 INTEL_FRONTBUFFER_PRIMARY(pipe));
2708 mutex_unlock(&dev->struct_mutex);
2709 if (ret != 0) {
2710 DRM_ERROR("pin & fence failed\n");
2711 return ret;
2712 }
2713
2714 /*
2715 * Update pipe size and adjust fitter if needed: the reason for this is
2716 * that in compute_mode_changes we check the native mode (not the pfit
2717 * mode) to see if we can flip rather than do a full mode set. In the
2718 * fastboot case, we'll flip, but if we don't update the pipesrc and
2719 * pfit state, we'll end up with a big fb scanned out into the wrong
2720 * sized surface.
2721 *
2722 * To fix this properly, we need to hoist the checks up into
2723 * compute_mode_changes (or above), check the actual pfit state and
2724 * whether the platform allows pfit disable with pipe active, and only
2725 * then update the pipesrc and pfit state, even on the flip path.
2726 */
2727 if (i915.fastboot) {
2728 const struct drm_display_mode *adjusted_mode =
2729 &intel_crtc->config.adjusted_mode;
2730
2731 I915_WRITE(PIPESRC(intel_crtc->pipe),
2732 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2733 (adjusted_mode->crtc_vdisplay - 1));
2734 if (!intel_crtc->config.pch_pfit.enabled &&
2735 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2736 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2737 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2738 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2739 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2740 }
2741 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2742 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2743 }
2744
2745 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2746
2747 if (intel_crtc->active)
2748 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2749
2750 crtc->primary->fb = fb;
2751 crtc->x = x;
2752 crtc->y = y;
2753
2754 if (old_fb) {
2755 if (intel_crtc->active && old_fb != fb)
2756 intel_wait_for_vblank(dev, intel_crtc->pipe);
2757 mutex_lock(&dev->struct_mutex);
2758 intel_unpin_fb_obj(old_obj);
2759 mutex_unlock(&dev->struct_mutex);
2760 }
2761
2762 mutex_lock(&dev->struct_mutex);
2763 intel_update_fbc(dev);
2764 mutex_unlock(&dev->struct_mutex);
2765
2766 return 0;
2767 }
2768
2769 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2770 {
2771 struct drm_device *dev = crtc->dev;
2772 struct drm_i915_private *dev_priv = dev->dev_private;
2773 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2774 int pipe = intel_crtc->pipe;
2775 u32 reg, temp;
2776
2777 /* enable normal train */
2778 reg = FDI_TX_CTL(pipe);
2779 temp = I915_READ(reg);
2780 if (IS_IVYBRIDGE(dev)) {
2781 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2782 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2783 } else {
2784 temp &= ~FDI_LINK_TRAIN_NONE;
2785 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2786 }
2787 I915_WRITE(reg, temp);
2788
2789 reg = FDI_RX_CTL(pipe);
2790 temp = I915_READ(reg);
2791 if (HAS_PCH_CPT(dev)) {
2792 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2793 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2794 } else {
2795 temp &= ~FDI_LINK_TRAIN_NONE;
2796 temp |= FDI_LINK_TRAIN_NONE;
2797 }
2798 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2799
2800 /* wait one idle pattern time */
2801 POSTING_READ(reg);
2802 udelay(1000);
2803
2804 /* IVB wants error correction enabled */
2805 if (IS_IVYBRIDGE(dev))
2806 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2807 FDI_FE_ERRC_ENABLE);
2808 }
2809
2810 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2811 {
2812 return crtc->base.enabled && crtc->active &&
2813 crtc->config.has_pch_encoder;
2814 }
2815
2816 static void ivb_modeset_global_resources(struct drm_device *dev)
2817 {
2818 struct drm_i915_private *dev_priv = dev->dev_private;
2819 struct intel_crtc *pipe_B_crtc =
2820 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2821 struct intel_crtc *pipe_C_crtc =
2822 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2823 uint32_t temp;
2824
2825 /*
2826 * When everything is off disable fdi C so that we could enable fdi B
2827 * with all lanes. Note that we don't care about enabled pipes without
2828 * an enabled pch encoder.
2829 */
2830 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2831 !pipe_has_enabled_pch(pipe_C_crtc)) {
2832 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2833 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2834
2835 temp = I915_READ(SOUTH_CHICKEN1);
2836 temp &= ~FDI_BC_BIFURCATION_SELECT;
2837 DRM_DEBUG_KMS("disabling fdi C rx\n");
2838 I915_WRITE(SOUTH_CHICKEN1, temp);
2839 }
2840 }
2841
2842 /* The FDI link training functions for ILK/Ibexpeak. */
2843 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2844 {
2845 struct drm_device *dev = crtc->dev;
2846 struct drm_i915_private *dev_priv = dev->dev_private;
2847 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2848 int pipe = intel_crtc->pipe;
2849 u32 reg, temp, tries;
2850
2851 /* FDI needs bits from pipe first */
2852 assert_pipe_enabled(dev_priv, pipe);
2853
2854 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2855 for train result */
2856 reg = FDI_RX_IMR(pipe);
2857 temp = I915_READ(reg);
2858 temp &= ~FDI_RX_SYMBOL_LOCK;
2859 temp &= ~FDI_RX_BIT_LOCK;
2860 I915_WRITE(reg, temp);
2861 I915_READ(reg);
2862 udelay(150);
2863
2864 /* enable CPU FDI TX and PCH FDI RX */
2865 reg = FDI_TX_CTL(pipe);
2866 temp = I915_READ(reg);
2867 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2868 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2869 temp &= ~FDI_LINK_TRAIN_NONE;
2870 temp |= FDI_LINK_TRAIN_PATTERN_1;
2871 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2872
2873 reg = FDI_RX_CTL(pipe);
2874 temp = I915_READ(reg);
2875 temp &= ~FDI_LINK_TRAIN_NONE;
2876 temp |= FDI_LINK_TRAIN_PATTERN_1;
2877 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2878
2879 POSTING_READ(reg);
2880 udelay(150);
2881
2882 /* Ironlake workaround, enable clock pointer after FDI enable*/
2883 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2884 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2885 FDI_RX_PHASE_SYNC_POINTER_EN);
2886
2887 reg = FDI_RX_IIR(pipe);
2888 for (tries = 0; tries < 5; tries++) {
2889 temp = I915_READ(reg);
2890 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2891
2892 if ((temp & FDI_RX_BIT_LOCK)) {
2893 DRM_DEBUG_KMS("FDI train 1 done.\n");
2894 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2895 break;
2896 }
2897 }
2898 if (tries == 5)
2899 DRM_ERROR("FDI train 1 fail!\n");
2900
2901 /* Train 2 */
2902 reg = FDI_TX_CTL(pipe);
2903 temp = I915_READ(reg);
2904 temp &= ~FDI_LINK_TRAIN_NONE;
2905 temp |= FDI_LINK_TRAIN_PATTERN_2;
2906 I915_WRITE(reg, temp);
2907
2908 reg = FDI_RX_CTL(pipe);
2909 temp = I915_READ(reg);
2910 temp &= ~FDI_LINK_TRAIN_NONE;
2911 temp |= FDI_LINK_TRAIN_PATTERN_2;
2912 I915_WRITE(reg, temp);
2913
2914 POSTING_READ(reg);
2915 udelay(150);
2916
2917 reg = FDI_RX_IIR(pipe);
2918 for (tries = 0; tries < 5; tries++) {
2919 temp = I915_READ(reg);
2920 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2921
2922 if (temp & FDI_RX_SYMBOL_LOCK) {
2923 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2924 DRM_DEBUG_KMS("FDI train 2 done.\n");
2925 break;
2926 }
2927 }
2928 if (tries == 5)
2929 DRM_ERROR("FDI train 2 fail!\n");
2930
2931 DRM_DEBUG_KMS("FDI train done\n");
2932
2933 }
2934
2935 static const int snb_b_fdi_train_param[] = {
2936 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2937 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2938 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2939 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2940 };
2941
2942 /* The FDI link training functions for SNB/Cougarpoint. */
2943 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2944 {
2945 struct drm_device *dev = crtc->dev;
2946 struct drm_i915_private *dev_priv = dev->dev_private;
2947 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2948 int pipe = intel_crtc->pipe;
2949 u32 reg, temp, i, retry;
2950
2951 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2952 for train result */
2953 reg = FDI_RX_IMR(pipe);
2954 temp = I915_READ(reg);
2955 temp &= ~FDI_RX_SYMBOL_LOCK;
2956 temp &= ~FDI_RX_BIT_LOCK;
2957 I915_WRITE(reg, temp);
2958
2959 POSTING_READ(reg);
2960 udelay(150);
2961
2962 /* enable CPU FDI TX and PCH FDI RX */
2963 reg = FDI_TX_CTL(pipe);
2964 temp = I915_READ(reg);
2965 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2966 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2967 temp &= ~FDI_LINK_TRAIN_NONE;
2968 temp |= FDI_LINK_TRAIN_PATTERN_1;
2969 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2970 /* SNB-B */
2971 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2972 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2973
2974 I915_WRITE(FDI_RX_MISC(pipe),
2975 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2976
2977 reg = FDI_RX_CTL(pipe);
2978 temp = I915_READ(reg);
2979 if (HAS_PCH_CPT(dev)) {
2980 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2981 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2982 } else {
2983 temp &= ~FDI_LINK_TRAIN_NONE;
2984 temp |= FDI_LINK_TRAIN_PATTERN_1;
2985 }
2986 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2987
2988 POSTING_READ(reg);
2989 udelay(150);
2990
2991 for (i = 0; i < 4; i++) {
2992 reg = FDI_TX_CTL(pipe);
2993 temp = I915_READ(reg);
2994 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2995 temp |= snb_b_fdi_train_param[i];
2996 I915_WRITE(reg, temp);
2997
2998 POSTING_READ(reg);
2999 udelay(500);
3000
3001 for (retry = 0; retry < 5; retry++) {
3002 reg = FDI_RX_IIR(pipe);
3003 temp = I915_READ(reg);
3004 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3005 if (temp & FDI_RX_BIT_LOCK) {
3006 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3007 DRM_DEBUG_KMS("FDI train 1 done.\n");
3008 break;
3009 }
3010 udelay(50);
3011 }
3012 if (retry < 5)
3013 break;
3014 }
3015 if (i == 4)
3016 DRM_ERROR("FDI train 1 fail!\n");
3017
3018 /* Train 2 */
3019 reg = FDI_TX_CTL(pipe);
3020 temp = I915_READ(reg);
3021 temp &= ~FDI_LINK_TRAIN_NONE;
3022 temp |= FDI_LINK_TRAIN_PATTERN_2;
3023 if (IS_GEN6(dev)) {
3024 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3025 /* SNB-B */
3026 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3027 }
3028 I915_WRITE(reg, temp);
3029
3030 reg = FDI_RX_CTL(pipe);
3031 temp = I915_READ(reg);
3032 if (HAS_PCH_CPT(dev)) {
3033 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3034 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3035 } else {
3036 temp &= ~FDI_LINK_TRAIN_NONE;
3037 temp |= FDI_LINK_TRAIN_PATTERN_2;
3038 }
3039 I915_WRITE(reg, temp);
3040
3041 POSTING_READ(reg);
3042 udelay(150);
3043
3044 for (i = 0; i < 4; i++) {
3045 reg = FDI_TX_CTL(pipe);
3046 temp = I915_READ(reg);
3047 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3048 temp |= snb_b_fdi_train_param[i];
3049 I915_WRITE(reg, temp);
3050
3051 POSTING_READ(reg);
3052 udelay(500);
3053
3054 for (retry = 0; retry < 5; retry++) {
3055 reg = FDI_RX_IIR(pipe);
3056 temp = I915_READ(reg);
3057 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3058 if (temp & FDI_RX_SYMBOL_LOCK) {
3059 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3060 DRM_DEBUG_KMS("FDI train 2 done.\n");
3061 break;
3062 }
3063 udelay(50);
3064 }
3065 if (retry < 5)
3066 break;
3067 }
3068 if (i == 4)
3069 DRM_ERROR("FDI train 2 fail!\n");
3070
3071 DRM_DEBUG_KMS("FDI train done.\n");
3072 }
3073
3074 /* Manual link training for Ivy Bridge A0 parts */
3075 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3076 {
3077 struct drm_device *dev = crtc->dev;
3078 struct drm_i915_private *dev_priv = dev->dev_private;
3079 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3080 int pipe = intel_crtc->pipe;
3081 u32 reg, temp, i, j;
3082
3083 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3084 for train result */
3085 reg = FDI_RX_IMR(pipe);
3086 temp = I915_READ(reg);
3087 temp &= ~FDI_RX_SYMBOL_LOCK;
3088 temp &= ~FDI_RX_BIT_LOCK;
3089 I915_WRITE(reg, temp);
3090
3091 POSTING_READ(reg);
3092 udelay(150);
3093
3094 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3095 I915_READ(FDI_RX_IIR(pipe)));
3096
3097 /* Try each vswing and preemphasis setting twice before moving on */
3098 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3099 /* disable first in case we need to retry */
3100 reg = FDI_TX_CTL(pipe);
3101 temp = I915_READ(reg);
3102 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3103 temp &= ~FDI_TX_ENABLE;
3104 I915_WRITE(reg, temp);
3105
3106 reg = FDI_RX_CTL(pipe);
3107 temp = I915_READ(reg);
3108 temp &= ~FDI_LINK_TRAIN_AUTO;
3109 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3110 temp &= ~FDI_RX_ENABLE;
3111 I915_WRITE(reg, temp);
3112
3113 /* enable CPU FDI TX and PCH FDI RX */
3114 reg = FDI_TX_CTL(pipe);
3115 temp = I915_READ(reg);
3116 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3117 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3118 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3119 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3120 temp |= snb_b_fdi_train_param[j/2];
3121 temp |= FDI_COMPOSITE_SYNC;
3122 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3123
3124 I915_WRITE(FDI_RX_MISC(pipe),
3125 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3126
3127 reg = FDI_RX_CTL(pipe);
3128 temp = I915_READ(reg);
3129 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3130 temp |= FDI_COMPOSITE_SYNC;
3131 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3132
3133 POSTING_READ(reg);
3134 udelay(1); /* should be 0.5us */
3135
3136 for (i = 0; i < 4; i++) {
3137 reg = FDI_RX_IIR(pipe);
3138 temp = I915_READ(reg);
3139 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3140
3141 if (temp & FDI_RX_BIT_LOCK ||
3142 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3143 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3144 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3145 i);
3146 break;
3147 }
3148 udelay(1); /* should be 0.5us */
3149 }
3150 if (i == 4) {
3151 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3152 continue;
3153 }
3154
3155 /* Train 2 */
3156 reg = FDI_TX_CTL(pipe);
3157 temp = I915_READ(reg);
3158 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3159 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3160 I915_WRITE(reg, temp);
3161
3162 reg = FDI_RX_CTL(pipe);
3163 temp = I915_READ(reg);
3164 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3165 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3166 I915_WRITE(reg, temp);
3167
3168 POSTING_READ(reg);
3169 udelay(2); /* should be 1.5us */
3170
3171 for (i = 0; i < 4; i++) {
3172 reg = FDI_RX_IIR(pipe);
3173 temp = I915_READ(reg);
3174 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3175
3176 if (temp & FDI_RX_SYMBOL_LOCK ||
3177 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3178 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3179 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3180 i);
3181 goto train_done;
3182 }
3183 udelay(2); /* should be 1.5us */
3184 }
3185 if (i == 4)
3186 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3187 }
3188
3189 train_done:
3190 DRM_DEBUG_KMS("FDI train done.\n");
3191 }
3192
3193 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3194 {
3195 struct drm_device *dev = intel_crtc->base.dev;
3196 struct drm_i915_private *dev_priv = dev->dev_private;
3197 int pipe = intel_crtc->pipe;
3198 u32 reg, temp;
3199
3200
3201 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3202 reg = FDI_RX_CTL(pipe);
3203 temp = I915_READ(reg);
3204 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3205 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3206 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3207 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3208
3209 POSTING_READ(reg);
3210 udelay(200);
3211
3212 /* Switch from Rawclk to PCDclk */
3213 temp = I915_READ(reg);
3214 I915_WRITE(reg, temp | FDI_PCDCLK);
3215
3216 POSTING_READ(reg);
3217 udelay(200);
3218
3219 /* Enable CPU FDI TX PLL, always on for Ironlake */
3220 reg = FDI_TX_CTL(pipe);
3221 temp = I915_READ(reg);
3222 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3223 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3224
3225 POSTING_READ(reg);
3226 udelay(100);
3227 }
3228 }
3229
3230 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3231 {
3232 struct drm_device *dev = intel_crtc->base.dev;
3233 struct drm_i915_private *dev_priv = dev->dev_private;
3234 int pipe = intel_crtc->pipe;
3235 u32 reg, temp;
3236
3237 /* Switch from PCDclk to Rawclk */
3238 reg = FDI_RX_CTL(pipe);
3239 temp = I915_READ(reg);
3240 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3241
3242 /* Disable CPU FDI TX PLL */
3243 reg = FDI_TX_CTL(pipe);
3244 temp = I915_READ(reg);
3245 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3246
3247 POSTING_READ(reg);
3248 udelay(100);
3249
3250 reg = FDI_RX_CTL(pipe);
3251 temp = I915_READ(reg);
3252 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3253
3254 /* Wait for the clocks to turn off. */
3255 POSTING_READ(reg);
3256 udelay(100);
3257 }
3258
3259 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3260 {
3261 struct drm_device *dev = crtc->dev;
3262 struct drm_i915_private *dev_priv = dev->dev_private;
3263 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3264 int pipe = intel_crtc->pipe;
3265 u32 reg, temp;
3266
3267 /* disable CPU FDI tx and PCH FDI rx */
3268 reg = FDI_TX_CTL(pipe);
3269 temp = I915_READ(reg);
3270 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3271 POSTING_READ(reg);
3272
3273 reg = FDI_RX_CTL(pipe);
3274 temp = I915_READ(reg);
3275 temp &= ~(0x7 << 16);
3276 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3277 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3278
3279 POSTING_READ(reg);
3280 udelay(100);
3281
3282 /* Ironlake workaround, disable clock pointer after downing FDI */
3283 if (HAS_PCH_IBX(dev))
3284 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3285
3286 /* still set train pattern 1 */
3287 reg = FDI_TX_CTL(pipe);
3288 temp = I915_READ(reg);
3289 temp &= ~FDI_LINK_TRAIN_NONE;
3290 temp |= FDI_LINK_TRAIN_PATTERN_1;
3291 I915_WRITE(reg, temp);
3292
3293 reg = FDI_RX_CTL(pipe);
3294 temp = I915_READ(reg);
3295 if (HAS_PCH_CPT(dev)) {
3296 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3297 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3298 } else {
3299 temp &= ~FDI_LINK_TRAIN_NONE;
3300 temp |= FDI_LINK_TRAIN_PATTERN_1;
3301 }
3302 /* BPC in FDI rx is consistent with that in PIPECONF */
3303 temp &= ~(0x07 << 16);
3304 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3305 I915_WRITE(reg, temp);
3306
3307 POSTING_READ(reg);
3308 udelay(100);
3309 }
3310
3311 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3312 {
3313 struct intel_crtc *crtc;
3314
3315 /* Note that we don't need to be called with mode_config.lock here
3316 * as our list of CRTC objects is static for the lifetime of the
3317 * device and so cannot disappear as we iterate. Similarly, we can
3318 * happily treat the predicates as racy, atomic checks as userspace
3319 * cannot claim and pin a new fb without at least acquring the
3320 * struct_mutex and so serialising with us.
3321 */
3322 for_each_intel_crtc(dev, crtc) {
3323 if (atomic_read(&crtc->unpin_work_count) == 0)
3324 continue;
3325
3326 if (crtc->unpin_work)
3327 intel_wait_for_vblank(dev, crtc->pipe);
3328
3329 return true;
3330 }
3331
3332 return false;
3333 }
3334
3335 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3336 {
3337 struct drm_device *dev = crtc->dev;
3338 struct drm_i915_private *dev_priv = dev->dev_private;
3339
3340 if (crtc->primary->fb == NULL)
3341 return;
3342
3343 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3344
3345 WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3346 !intel_crtc_has_pending_flip(crtc),
3347 60*HZ) == 0);
3348
3349 mutex_lock(&dev->struct_mutex);
3350 intel_finish_fb(crtc->primary->fb);
3351 mutex_unlock(&dev->struct_mutex);
3352 }
3353
3354 /* Program iCLKIP clock to the desired frequency */
3355 static void lpt_program_iclkip(struct drm_crtc *crtc)
3356 {
3357 struct drm_device *dev = crtc->dev;
3358 struct drm_i915_private *dev_priv = dev->dev_private;
3359 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3360 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3361 u32 temp;
3362
3363 mutex_lock(&dev_priv->dpio_lock);
3364
3365 /* It is necessary to ungate the pixclk gate prior to programming
3366 * the divisors, and gate it back when it is done.
3367 */
3368 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3369
3370 /* Disable SSCCTL */
3371 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3372 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3373 SBI_SSCCTL_DISABLE,
3374 SBI_ICLK);
3375
3376 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3377 if (clock == 20000) {
3378 auxdiv = 1;
3379 divsel = 0x41;
3380 phaseinc = 0x20;
3381 } else {
3382 /* The iCLK virtual clock root frequency is in MHz,
3383 * but the adjusted_mode->crtc_clock in in KHz. To get the
3384 * divisors, it is necessary to divide one by another, so we
3385 * convert the virtual clock precision to KHz here for higher
3386 * precision.
3387 */
3388 u32 iclk_virtual_root_freq = 172800 * 1000;
3389 u32 iclk_pi_range = 64;
3390 u32 desired_divisor, msb_divisor_value, pi_value;
3391
3392 desired_divisor = (iclk_virtual_root_freq / clock);
3393 msb_divisor_value = desired_divisor / iclk_pi_range;
3394 pi_value = desired_divisor % iclk_pi_range;
3395
3396 auxdiv = 0;
3397 divsel = msb_divisor_value - 2;
3398 phaseinc = pi_value;
3399 }
3400
3401 /* This should not happen with any sane values */
3402 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3403 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3404 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3405 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3406
3407 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3408 clock,
3409 auxdiv,
3410 divsel,
3411 phasedir,
3412 phaseinc);
3413
3414 /* Program SSCDIVINTPHASE6 */
3415 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3416 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3417 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3418 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3419 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3420 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3421 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3422 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3423
3424 /* Program SSCAUXDIV */
3425 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3426 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3427 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3428 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3429
3430 /* Enable modulator and associated divider */
3431 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3432 temp &= ~SBI_SSCCTL_DISABLE;
3433 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3434
3435 /* Wait for initialization time */
3436 udelay(24);
3437
3438 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3439
3440 mutex_unlock(&dev_priv->dpio_lock);
3441 }
3442
3443 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3444 enum pipe pch_transcoder)
3445 {
3446 struct drm_device *dev = crtc->base.dev;
3447 struct drm_i915_private *dev_priv = dev->dev_private;
3448 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3449
3450 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3451 I915_READ(HTOTAL(cpu_transcoder)));
3452 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3453 I915_READ(HBLANK(cpu_transcoder)));
3454 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3455 I915_READ(HSYNC(cpu_transcoder)));
3456
3457 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3458 I915_READ(VTOTAL(cpu_transcoder)));
3459 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3460 I915_READ(VBLANK(cpu_transcoder)));
3461 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3462 I915_READ(VSYNC(cpu_transcoder)));
3463 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3464 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3465 }
3466
3467 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3468 {
3469 struct drm_i915_private *dev_priv = dev->dev_private;
3470 uint32_t temp;
3471
3472 temp = I915_READ(SOUTH_CHICKEN1);
3473 if (temp & FDI_BC_BIFURCATION_SELECT)
3474 return;
3475
3476 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3477 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3478
3479 temp |= FDI_BC_BIFURCATION_SELECT;
3480 DRM_DEBUG_KMS("enabling fdi C rx\n");
3481 I915_WRITE(SOUTH_CHICKEN1, temp);
3482 POSTING_READ(SOUTH_CHICKEN1);
3483 }
3484
3485 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3486 {
3487 struct drm_device *dev = intel_crtc->base.dev;
3488 struct drm_i915_private *dev_priv = dev->dev_private;
3489
3490 switch (intel_crtc->pipe) {
3491 case PIPE_A:
3492 break;
3493 case PIPE_B:
3494 if (intel_crtc->config.fdi_lanes > 2)
3495 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3496 else
3497 cpt_enable_fdi_bc_bifurcation(dev);
3498
3499 break;
3500 case PIPE_C:
3501 cpt_enable_fdi_bc_bifurcation(dev);
3502
3503 break;
3504 default:
3505 BUG();
3506 }
3507 }
3508
3509 /*
3510 * Enable PCH resources required for PCH ports:
3511 * - PCH PLLs
3512 * - FDI training & RX/TX
3513 * - update transcoder timings
3514 * - DP transcoding bits
3515 * - transcoder
3516 */
3517 static void ironlake_pch_enable(struct drm_crtc *crtc)
3518 {
3519 struct drm_device *dev = crtc->dev;
3520 struct drm_i915_private *dev_priv = dev->dev_private;
3521 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3522 int pipe = intel_crtc->pipe;
3523 u32 reg, temp;
3524
3525 assert_pch_transcoder_disabled(dev_priv, pipe);
3526
3527 if (IS_IVYBRIDGE(dev))
3528 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3529
3530 /* Write the TU size bits before fdi link training, so that error
3531 * detection works. */
3532 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3533 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3534
3535 /* For PCH output, training FDI link */
3536 dev_priv->display.fdi_link_train(crtc);
3537
3538 /* We need to program the right clock selection before writing the pixel
3539 * mutliplier into the DPLL. */
3540 if (HAS_PCH_CPT(dev)) {
3541 u32 sel;
3542
3543 temp = I915_READ(PCH_DPLL_SEL);
3544 temp |= TRANS_DPLL_ENABLE(pipe);
3545 sel = TRANS_DPLLB_SEL(pipe);
3546 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3547 temp |= sel;
3548 else
3549 temp &= ~sel;
3550 I915_WRITE(PCH_DPLL_SEL, temp);
3551 }
3552
3553 /* XXX: pch pll's can be enabled any time before we enable the PCH
3554 * transcoder, and we actually should do this to not upset any PCH
3555 * transcoder that already use the clock when we share it.
3556 *
3557 * Note that enable_shared_dpll tries to do the right thing, but
3558 * get_shared_dpll unconditionally resets the pll - we need that to have
3559 * the right LVDS enable sequence. */
3560 intel_enable_shared_dpll(intel_crtc);
3561
3562 /* set transcoder timing, panel must allow it */
3563 assert_panel_unlocked(dev_priv, pipe);
3564 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3565
3566 intel_fdi_normal_train(crtc);
3567
3568 /* For PCH DP, enable TRANS_DP_CTL */
3569 if (HAS_PCH_CPT(dev) &&
3570 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3571 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3572 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3573 reg = TRANS_DP_CTL(pipe);
3574 temp = I915_READ(reg);
3575 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3576 TRANS_DP_SYNC_MASK |
3577 TRANS_DP_BPC_MASK);
3578 temp |= (TRANS_DP_OUTPUT_ENABLE |
3579 TRANS_DP_ENH_FRAMING);
3580 temp |= bpc << 9; /* same format but at 11:9 */
3581
3582 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3583 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3584 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3585 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3586
3587 switch (intel_trans_dp_port_sel(crtc)) {
3588 case PCH_DP_B:
3589 temp |= TRANS_DP_PORT_SEL_B;
3590 break;
3591 case PCH_DP_C:
3592 temp |= TRANS_DP_PORT_SEL_C;
3593 break;
3594 case PCH_DP_D:
3595 temp |= TRANS_DP_PORT_SEL_D;
3596 break;
3597 default:
3598 BUG();
3599 }
3600
3601 I915_WRITE(reg, temp);
3602 }
3603
3604 ironlake_enable_pch_transcoder(dev_priv, pipe);
3605 }
3606
3607 static void lpt_pch_enable(struct drm_crtc *crtc)
3608 {
3609 struct drm_device *dev = crtc->dev;
3610 struct drm_i915_private *dev_priv = dev->dev_private;
3611 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3612 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3613
3614 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3615
3616 lpt_program_iclkip(crtc);
3617
3618 /* Set transcoder timing. */
3619 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3620
3621 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3622 }
3623
3624 void intel_put_shared_dpll(struct intel_crtc *crtc)
3625 {
3626 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3627
3628 if (pll == NULL)
3629 return;
3630
3631 if (pll->refcount == 0) {
3632 WARN(1, "bad %s refcount\n", pll->name);
3633 return;
3634 }
3635
3636 if (--pll->refcount == 0) {
3637 WARN_ON(pll->on);
3638 WARN_ON(pll->active);
3639 }
3640
3641 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3642 }
3643
3644 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3645 {
3646 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3647 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3648 enum intel_dpll_id i;
3649
3650 if (pll) {
3651 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3652 crtc->base.base.id, pll->name);
3653 intel_put_shared_dpll(crtc);
3654 }
3655
3656 if (HAS_PCH_IBX(dev_priv->dev)) {
3657 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3658 i = (enum intel_dpll_id) crtc->pipe;
3659 pll = &dev_priv->shared_dplls[i];
3660
3661 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3662 crtc->base.base.id, pll->name);
3663
3664 WARN_ON(pll->refcount);
3665
3666 goto found;
3667 }
3668
3669 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3670 pll = &dev_priv->shared_dplls[i];
3671
3672 /* Only want to check enabled timings first */
3673 if (pll->refcount == 0)
3674 continue;
3675
3676 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3677 sizeof(pll->hw_state)) == 0) {
3678 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3679 crtc->base.base.id,
3680 pll->name, pll->refcount, pll->active);
3681
3682 goto found;
3683 }
3684 }
3685
3686 /* Ok no matching timings, maybe there's a free one? */
3687 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3688 pll = &dev_priv->shared_dplls[i];
3689 if (pll->refcount == 0) {
3690 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3691 crtc->base.base.id, pll->name);
3692 goto found;
3693 }
3694 }
3695
3696 return NULL;
3697
3698 found:
3699 if (pll->refcount == 0)
3700 pll->hw_state = crtc->config.dpll_hw_state;
3701
3702 crtc->config.shared_dpll = i;
3703 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3704 pipe_name(crtc->pipe));
3705
3706 pll->refcount++;
3707
3708 return pll;
3709 }
3710
3711 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3712 {
3713 struct drm_i915_private *dev_priv = dev->dev_private;
3714 int dslreg = PIPEDSL(pipe);
3715 u32 temp;
3716
3717 temp = I915_READ(dslreg);
3718 udelay(500);
3719 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3720 if (wait_for(I915_READ(dslreg) != temp, 5))
3721 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3722 }
3723 }
3724
3725 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3726 {
3727 struct drm_device *dev = crtc->base.dev;
3728 struct drm_i915_private *dev_priv = dev->dev_private;
3729 int pipe = crtc->pipe;
3730
3731 if (crtc->config.pch_pfit.enabled) {
3732 /* Force use of hard-coded filter coefficients
3733 * as some pre-programmed values are broken,
3734 * e.g. x201.
3735 */
3736 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3737 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3738 PF_PIPE_SEL_IVB(pipe));
3739 else
3740 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3741 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3742 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3743 }
3744 }
3745
3746 static void intel_enable_planes(struct drm_crtc *crtc)
3747 {
3748 struct drm_device *dev = crtc->dev;
3749 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3750 struct drm_plane *plane;
3751 struct intel_plane *intel_plane;
3752
3753 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3754 intel_plane = to_intel_plane(plane);
3755 if (intel_plane->pipe == pipe)
3756 intel_plane_restore(&intel_plane->base);
3757 }
3758 }
3759
3760 static void intel_disable_planes(struct drm_crtc *crtc)
3761 {
3762 struct drm_device *dev = crtc->dev;
3763 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3764 struct drm_plane *plane;
3765 struct intel_plane *intel_plane;
3766
3767 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3768 intel_plane = to_intel_plane(plane);
3769 if (intel_plane->pipe == pipe)
3770 intel_plane_disable(&intel_plane->base);
3771 }
3772 }
3773
3774 void hsw_enable_ips(struct intel_crtc *crtc)
3775 {
3776 struct drm_device *dev = crtc->base.dev;
3777 struct drm_i915_private *dev_priv = dev->dev_private;
3778
3779 if (!crtc->config.ips_enabled)
3780 return;
3781
3782 /* We can only enable IPS after we enable a plane and wait for a vblank */
3783 intel_wait_for_vblank(dev, crtc->pipe);
3784
3785 assert_plane_enabled(dev_priv, crtc->plane);
3786 if (IS_BROADWELL(dev)) {
3787 mutex_lock(&dev_priv->rps.hw_lock);
3788 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3789 mutex_unlock(&dev_priv->rps.hw_lock);
3790 /* Quoting Art Runyan: "its not safe to expect any particular
3791 * value in IPS_CTL bit 31 after enabling IPS through the
3792 * mailbox." Moreover, the mailbox may return a bogus state,
3793 * so we need to just enable it and continue on.
3794 */
3795 } else {
3796 I915_WRITE(IPS_CTL, IPS_ENABLE);
3797 /* The bit only becomes 1 in the next vblank, so this wait here
3798 * is essentially intel_wait_for_vblank. If we don't have this
3799 * and don't wait for vblanks until the end of crtc_enable, then
3800 * the HW state readout code will complain that the expected
3801 * IPS_CTL value is not the one we read. */
3802 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3803 DRM_ERROR("Timed out waiting for IPS enable\n");
3804 }
3805 }
3806
3807 void hsw_disable_ips(struct intel_crtc *crtc)
3808 {
3809 struct drm_device *dev = crtc->base.dev;
3810 struct drm_i915_private *dev_priv = dev->dev_private;
3811
3812 if (!crtc->config.ips_enabled)
3813 return;
3814
3815 assert_plane_enabled(dev_priv, crtc->plane);
3816 if (IS_BROADWELL(dev)) {
3817 mutex_lock(&dev_priv->rps.hw_lock);
3818 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3819 mutex_unlock(&dev_priv->rps.hw_lock);
3820 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3821 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3822 DRM_ERROR("Timed out waiting for IPS disable\n");
3823 } else {
3824 I915_WRITE(IPS_CTL, 0);
3825 POSTING_READ(IPS_CTL);
3826 }
3827
3828 /* We need to wait for a vblank before we can disable the plane. */
3829 intel_wait_for_vblank(dev, crtc->pipe);
3830 }
3831
3832 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3833 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3834 {
3835 struct drm_device *dev = crtc->dev;
3836 struct drm_i915_private *dev_priv = dev->dev_private;
3837 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3838 enum pipe pipe = intel_crtc->pipe;
3839 int palreg = PALETTE(pipe);
3840 int i;
3841 bool reenable_ips = false;
3842
3843 /* The clocks have to be on to load the palette. */
3844 if (!crtc->enabled || !intel_crtc->active)
3845 return;
3846
3847 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3848 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3849 assert_dsi_pll_enabled(dev_priv);
3850 else
3851 assert_pll_enabled(dev_priv, pipe);
3852 }
3853
3854 /* use legacy palette for Ironlake */
3855 if (HAS_PCH_SPLIT(dev))
3856 palreg = LGC_PALETTE(pipe);
3857
3858 /* Workaround : Do not read or write the pipe palette/gamma data while
3859 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3860 */
3861 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3862 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3863 GAMMA_MODE_MODE_SPLIT)) {
3864 hsw_disable_ips(intel_crtc);
3865 reenable_ips = true;
3866 }
3867
3868 for (i = 0; i < 256; i++) {
3869 I915_WRITE(palreg + 4 * i,
3870 (intel_crtc->lut_r[i] << 16) |
3871 (intel_crtc->lut_g[i] << 8) |
3872 intel_crtc->lut_b[i]);
3873 }
3874
3875 if (reenable_ips)
3876 hsw_enable_ips(intel_crtc);
3877 }
3878
3879 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3880 {
3881 if (!enable && intel_crtc->overlay) {
3882 struct drm_device *dev = intel_crtc->base.dev;
3883 struct drm_i915_private *dev_priv = dev->dev_private;
3884
3885 mutex_lock(&dev->struct_mutex);
3886 dev_priv->mm.interruptible = false;
3887 (void) intel_overlay_switch_off(intel_crtc->overlay);
3888 dev_priv->mm.interruptible = true;
3889 mutex_unlock(&dev->struct_mutex);
3890 }
3891
3892 /* Let userspace switch the overlay on again. In most cases userspace
3893 * has to recompute where to put it anyway.
3894 */
3895 }
3896
3897 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
3898 {
3899 struct drm_device *dev = crtc->dev;
3900 struct drm_i915_private *dev_priv = dev->dev_private;
3901 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3902 int pipe = intel_crtc->pipe;
3903 int plane = intel_crtc->plane;
3904
3905 drm_vblank_on(dev, pipe);
3906
3907 intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3908 intel_enable_planes(crtc);
3909 intel_crtc_update_cursor(crtc, true);
3910 intel_crtc_dpms_overlay(intel_crtc, true);
3911
3912 hsw_enable_ips(intel_crtc);
3913
3914 mutex_lock(&dev->struct_mutex);
3915 intel_update_fbc(dev);
3916 mutex_unlock(&dev->struct_mutex);
3917
3918 /*
3919 * FIXME: Once we grow proper nuclear flip support out of this we need
3920 * to compute the mask of flip planes precisely. For the time being
3921 * consider this a flip from a NULL plane.
3922 */
3923 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
3924 }
3925
3926 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
3927 {
3928 struct drm_device *dev = crtc->dev;
3929 struct drm_i915_private *dev_priv = dev->dev_private;
3930 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3931 int pipe = intel_crtc->pipe;
3932 int plane = intel_crtc->plane;
3933
3934 intel_crtc_wait_for_pending_flips(crtc);
3935
3936 if (dev_priv->fbc.plane == plane)
3937 intel_disable_fbc(dev);
3938
3939 hsw_disable_ips(intel_crtc);
3940
3941 intel_crtc_dpms_overlay(intel_crtc, false);
3942 intel_crtc_update_cursor(crtc, false);
3943 intel_disable_planes(crtc);
3944 intel_disable_primary_hw_plane(dev_priv, plane, pipe);
3945
3946 /*
3947 * FIXME: Once we grow proper nuclear flip support out of this we need
3948 * to compute the mask of flip planes precisely. For the time being
3949 * consider this a flip to a NULL plane.
3950 */
3951 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
3952
3953 drm_vblank_off(dev, pipe);
3954 }
3955
3956 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3957 {
3958 struct drm_device *dev = crtc->dev;
3959 struct drm_i915_private *dev_priv = dev->dev_private;
3960 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3961 struct intel_encoder *encoder;
3962 int pipe = intel_crtc->pipe;
3963 enum plane plane = intel_crtc->plane;
3964
3965 WARN_ON(!crtc->enabled);
3966
3967 if (intel_crtc->active)
3968 return;
3969
3970 if (intel_crtc->config.has_pch_encoder)
3971 intel_prepare_shared_dpll(intel_crtc);
3972
3973 if (intel_crtc->config.has_dp_encoder)
3974 intel_dp_set_m_n(intel_crtc);
3975
3976 intel_set_pipe_timings(intel_crtc);
3977
3978 if (intel_crtc->config.has_pch_encoder) {
3979 intel_cpu_transcoder_set_m_n(intel_crtc,
3980 &intel_crtc->config.fdi_m_n);
3981 }
3982
3983 ironlake_set_pipeconf(crtc);
3984
3985 /* Set up the display plane register */
3986 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
3987 POSTING_READ(DSPCNTR(plane));
3988
3989 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
3990 crtc->x, crtc->y);
3991
3992 intel_crtc->active = true;
3993
3994 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3995 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3996
3997 for_each_encoder_on_crtc(dev, crtc, encoder)
3998 if (encoder->pre_enable)
3999 encoder->pre_enable(encoder);
4000
4001 if (intel_crtc->config.has_pch_encoder) {
4002 /* Note: FDI PLL enabling _must_ be done before we enable the
4003 * cpu pipes, hence this is separate from all the other fdi/pch
4004 * enabling. */
4005 ironlake_fdi_pll_enable(intel_crtc);
4006 } else {
4007 assert_fdi_tx_disabled(dev_priv, pipe);
4008 assert_fdi_rx_disabled(dev_priv, pipe);
4009 }
4010
4011 ironlake_pfit_enable(intel_crtc);
4012
4013 /*
4014 * On ILK+ LUT must be loaded before the pipe is running but with
4015 * clocks enabled
4016 */
4017 intel_crtc_load_lut(crtc);
4018
4019 intel_update_watermarks(crtc);
4020 intel_enable_pipe(intel_crtc);
4021
4022 if (intel_crtc->config.has_pch_encoder)
4023 ironlake_pch_enable(crtc);
4024
4025 for_each_encoder_on_crtc(dev, crtc, encoder)
4026 encoder->enable(encoder);
4027
4028 if (HAS_PCH_CPT(dev))
4029 cpt_verify_modeset(dev, intel_crtc->pipe);
4030
4031 intel_crtc_enable_planes(crtc);
4032 }
4033
4034 /* IPS only exists on ULT machines and is tied to pipe A. */
4035 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4036 {
4037 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4038 }
4039
4040 /*
4041 * This implements the workaround described in the "notes" section of the mode
4042 * set sequence documentation. When going from no pipes or single pipe to
4043 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4044 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4045 */
4046 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4047 {
4048 struct drm_device *dev = crtc->base.dev;
4049 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4050
4051 /* We want to get the other_active_crtc only if there's only 1 other
4052 * active crtc. */
4053 for_each_intel_crtc(dev, crtc_it) {
4054 if (!crtc_it->active || crtc_it == crtc)
4055 continue;
4056
4057 if (other_active_crtc)
4058 return;
4059
4060 other_active_crtc = crtc_it;
4061 }
4062 if (!other_active_crtc)
4063 return;
4064
4065 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4066 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4067 }
4068
4069 static void haswell_crtc_enable(struct drm_crtc *crtc)
4070 {
4071 struct drm_device *dev = crtc->dev;
4072 struct drm_i915_private *dev_priv = dev->dev_private;
4073 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4074 struct intel_encoder *encoder;
4075 int pipe = intel_crtc->pipe;
4076 enum plane plane = intel_crtc->plane;
4077
4078 WARN_ON(!crtc->enabled);
4079
4080 if (intel_crtc->active)
4081 return;
4082
4083 if (intel_crtc->config.has_dp_encoder)
4084 intel_dp_set_m_n(intel_crtc);
4085
4086 intel_set_pipe_timings(intel_crtc);
4087
4088 if (intel_crtc->config.has_pch_encoder) {
4089 intel_cpu_transcoder_set_m_n(intel_crtc,
4090 &intel_crtc->config.fdi_m_n);
4091 }
4092
4093 haswell_set_pipeconf(crtc);
4094
4095 intel_set_pipe_csc(crtc);
4096
4097 /* Set up the display plane register */
4098 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
4099 POSTING_READ(DSPCNTR(plane));
4100
4101 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4102 crtc->x, crtc->y);
4103
4104 intel_crtc->active = true;
4105
4106 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4107 for_each_encoder_on_crtc(dev, crtc, encoder)
4108 if (encoder->pre_enable)
4109 encoder->pre_enable(encoder);
4110
4111 if (intel_crtc->config.has_pch_encoder) {
4112 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4113 dev_priv->display.fdi_link_train(crtc);
4114 }
4115
4116 intel_ddi_enable_pipe_clock(intel_crtc);
4117
4118 ironlake_pfit_enable(intel_crtc);
4119
4120 /*
4121 * On ILK+ LUT must be loaded before the pipe is running but with
4122 * clocks enabled
4123 */
4124 intel_crtc_load_lut(crtc);
4125
4126 intel_ddi_set_pipe_settings(crtc);
4127 intel_ddi_enable_transcoder_func(crtc);
4128
4129 intel_update_watermarks(crtc);
4130 intel_enable_pipe(intel_crtc);
4131
4132 if (intel_crtc->config.has_pch_encoder)
4133 lpt_pch_enable(crtc);
4134
4135 for_each_encoder_on_crtc(dev, crtc, encoder) {
4136 encoder->enable(encoder);
4137 intel_opregion_notify_encoder(encoder, true);
4138 }
4139
4140 /* If we change the relative order between pipe/planes enabling, we need
4141 * to change the workaround. */
4142 haswell_mode_set_planes_workaround(intel_crtc);
4143 intel_crtc_enable_planes(crtc);
4144 }
4145
4146 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4147 {
4148 struct drm_device *dev = crtc->base.dev;
4149 struct drm_i915_private *dev_priv = dev->dev_private;
4150 int pipe = crtc->pipe;
4151
4152 /* To avoid upsetting the power well on haswell only disable the pfit if
4153 * it's in use. The hw state code will make sure we get this right. */
4154 if (crtc->config.pch_pfit.enabled) {
4155 I915_WRITE(PF_CTL(pipe), 0);
4156 I915_WRITE(PF_WIN_POS(pipe), 0);
4157 I915_WRITE(PF_WIN_SZ(pipe), 0);
4158 }
4159 }
4160
4161 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4162 {
4163 struct drm_device *dev = crtc->dev;
4164 struct drm_i915_private *dev_priv = dev->dev_private;
4165 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4166 struct intel_encoder *encoder;
4167 int pipe = intel_crtc->pipe;
4168 u32 reg, temp;
4169
4170 if (!intel_crtc->active)
4171 return;
4172
4173 intel_crtc_disable_planes(crtc);
4174
4175 for_each_encoder_on_crtc(dev, crtc, encoder)
4176 encoder->disable(encoder);
4177
4178 if (intel_crtc->config.has_pch_encoder)
4179 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4180
4181 intel_disable_pipe(dev_priv, pipe);
4182
4183 ironlake_pfit_disable(intel_crtc);
4184
4185 for_each_encoder_on_crtc(dev, crtc, encoder)
4186 if (encoder->post_disable)
4187 encoder->post_disable(encoder);
4188
4189 if (intel_crtc->config.has_pch_encoder) {
4190 ironlake_fdi_disable(crtc);
4191
4192 ironlake_disable_pch_transcoder(dev_priv, pipe);
4193 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4194
4195 if (HAS_PCH_CPT(dev)) {
4196 /* disable TRANS_DP_CTL */
4197 reg = TRANS_DP_CTL(pipe);
4198 temp = I915_READ(reg);
4199 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4200 TRANS_DP_PORT_SEL_MASK);
4201 temp |= TRANS_DP_PORT_SEL_NONE;
4202 I915_WRITE(reg, temp);
4203
4204 /* disable DPLL_SEL */
4205 temp = I915_READ(PCH_DPLL_SEL);
4206 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4207 I915_WRITE(PCH_DPLL_SEL, temp);
4208 }
4209
4210 /* disable PCH DPLL */
4211 intel_disable_shared_dpll(intel_crtc);
4212
4213 ironlake_fdi_pll_disable(intel_crtc);
4214 }
4215
4216 intel_crtc->active = false;
4217 intel_update_watermarks(crtc);
4218
4219 mutex_lock(&dev->struct_mutex);
4220 intel_update_fbc(dev);
4221 mutex_unlock(&dev->struct_mutex);
4222 }
4223
4224 static void haswell_crtc_disable(struct drm_crtc *crtc)
4225 {
4226 struct drm_device *dev = crtc->dev;
4227 struct drm_i915_private *dev_priv = dev->dev_private;
4228 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4229 struct intel_encoder *encoder;
4230 int pipe = intel_crtc->pipe;
4231 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4232
4233 if (!intel_crtc->active)
4234 return;
4235
4236 intel_crtc_disable_planes(crtc);
4237
4238 for_each_encoder_on_crtc(dev, crtc, encoder) {
4239 intel_opregion_notify_encoder(encoder, false);
4240 encoder->disable(encoder);
4241 }
4242
4243 if (intel_crtc->config.has_pch_encoder)
4244 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4245 intel_disable_pipe(dev_priv, pipe);
4246
4247 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4248
4249 ironlake_pfit_disable(intel_crtc);
4250
4251 intel_ddi_disable_pipe_clock(intel_crtc);
4252
4253 if (intel_crtc->config.has_pch_encoder) {
4254 lpt_disable_pch_transcoder(dev_priv);
4255 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4256 intel_ddi_fdi_disable(crtc);
4257 }
4258
4259 for_each_encoder_on_crtc(dev, crtc, encoder)
4260 if (encoder->post_disable)
4261 encoder->post_disable(encoder);
4262
4263 intel_crtc->active = false;
4264 intel_update_watermarks(crtc);
4265
4266 mutex_lock(&dev->struct_mutex);
4267 intel_update_fbc(dev);
4268 mutex_unlock(&dev->struct_mutex);
4269 }
4270
4271 static void ironlake_crtc_off(struct drm_crtc *crtc)
4272 {
4273 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4274 intel_put_shared_dpll(intel_crtc);
4275 }
4276
4277 static void haswell_crtc_off(struct drm_crtc *crtc)
4278 {
4279 intel_ddi_put_crtc_pll(crtc);
4280 }
4281
4282 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4283 {
4284 struct drm_device *dev = crtc->base.dev;
4285 struct drm_i915_private *dev_priv = dev->dev_private;
4286 struct intel_crtc_config *pipe_config = &crtc->config;
4287
4288 if (!crtc->config.gmch_pfit.control)
4289 return;
4290
4291 /*
4292 * The panel fitter should only be adjusted whilst the pipe is disabled,
4293 * according to register description and PRM.
4294 */
4295 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4296 assert_pipe_disabled(dev_priv, crtc->pipe);
4297
4298 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4299 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4300
4301 /* Border color in case we don't scale up to the full screen. Black by
4302 * default, change to something else for debugging. */
4303 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4304 }
4305
4306 #define for_each_power_domain(domain, mask) \
4307 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4308 if ((1 << (domain)) & (mask))
4309
4310 enum intel_display_power_domain
4311 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4312 {
4313 struct drm_device *dev = intel_encoder->base.dev;
4314 struct intel_digital_port *intel_dig_port;
4315
4316 switch (intel_encoder->type) {
4317 case INTEL_OUTPUT_UNKNOWN:
4318 /* Only DDI platforms should ever use this output type */
4319 WARN_ON_ONCE(!HAS_DDI(dev));
4320 case INTEL_OUTPUT_DISPLAYPORT:
4321 case INTEL_OUTPUT_HDMI:
4322 case INTEL_OUTPUT_EDP:
4323 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4324 switch (intel_dig_port->port) {
4325 case PORT_A:
4326 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4327 case PORT_B:
4328 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4329 case PORT_C:
4330 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4331 case PORT_D:
4332 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4333 default:
4334 WARN_ON_ONCE(1);
4335 return POWER_DOMAIN_PORT_OTHER;
4336 }
4337 case INTEL_OUTPUT_ANALOG:
4338 return POWER_DOMAIN_PORT_CRT;
4339 case INTEL_OUTPUT_DSI:
4340 return POWER_DOMAIN_PORT_DSI;
4341 default:
4342 return POWER_DOMAIN_PORT_OTHER;
4343 }
4344 }
4345
4346 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4347 {
4348 struct drm_device *dev = crtc->dev;
4349 struct intel_encoder *intel_encoder;
4350 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4351 enum pipe pipe = intel_crtc->pipe;
4352 unsigned long mask;
4353 enum transcoder transcoder;
4354
4355 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4356
4357 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4358 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4359 if (intel_crtc->config.pch_pfit.enabled ||
4360 intel_crtc->config.pch_pfit.force_thru)
4361 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4362
4363 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4364 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4365
4366 return mask;
4367 }
4368
4369 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4370 bool enable)
4371 {
4372 if (dev_priv->power_domains.init_power_on == enable)
4373 return;
4374
4375 if (enable)
4376 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4377 else
4378 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4379
4380 dev_priv->power_domains.init_power_on = enable;
4381 }
4382
4383 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4384 {
4385 struct drm_i915_private *dev_priv = dev->dev_private;
4386 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4387 struct intel_crtc *crtc;
4388
4389 /*
4390 * First get all needed power domains, then put all unneeded, to avoid
4391 * any unnecessary toggling of the power wells.
4392 */
4393 for_each_intel_crtc(dev, crtc) {
4394 enum intel_display_power_domain domain;
4395
4396 if (!crtc->base.enabled)
4397 continue;
4398
4399 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4400
4401 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4402 intel_display_power_get(dev_priv, domain);
4403 }
4404
4405 for_each_intel_crtc(dev, crtc) {
4406 enum intel_display_power_domain domain;
4407
4408 for_each_power_domain(domain, crtc->enabled_power_domains)
4409 intel_display_power_put(dev_priv, domain);
4410
4411 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4412 }
4413
4414 intel_display_set_init_power(dev_priv, false);
4415 }
4416
4417 /* returns HPLL frequency in kHz */
4418 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4419 {
4420 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4421
4422 /* Obtain SKU information */
4423 mutex_lock(&dev_priv->dpio_lock);
4424 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4425 CCK_FUSE_HPLL_FREQ_MASK;
4426 mutex_unlock(&dev_priv->dpio_lock);
4427
4428 return vco_freq[hpll_freq] * 1000;
4429 }
4430
4431 static void vlv_update_cdclk(struct drm_device *dev)
4432 {
4433 struct drm_i915_private *dev_priv = dev->dev_private;
4434
4435 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4436 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz",
4437 dev_priv->vlv_cdclk_freq);
4438
4439 /*
4440 * Program the gmbus_freq based on the cdclk frequency.
4441 * BSpec erroneously claims we should aim for 4MHz, but
4442 * in fact 1MHz is the correct frequency.
4443 */
4444 I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
4445 }
4446
4447 /* Adjust CDclk dividers to allow high res or save power if possible */
4448 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4449 {
4450 struct drm_i915_private *dev_priv = dev->dev_private;
4451 u32 val, cmd;
4452
4453 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4454
4455 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4456 cmd = 2;
4457 else if (cdclk == 266667)
4458 cmd = 1;
4459 else
4460 cmd = 0;
4461
4462 mutex_lock(&dev_priv->rps.hw_lock);
4463 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4464 val &= ~DSPFREQGUAR_MASK;
4465 val |= (cmd << DSPFREQGUAR_SHIFT);
4466 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4467 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4468 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4469 50)) {
4470 DRM_ERROR("timed out waiting for CDclk change\n");
4471 }
4472 mutex_unlock(&dev_priv->rps.hw_lock);
4473
4474 if (cdclk == 400000) {
4475 u32 divider, vco;
4476
4477 vco = valleyview_get_vco(dev_priv);
4478 divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1;
4479
4480 mutex_lock(&dev_priv->dpio_lock);
4481 /* adjust cdclk divider */
4482 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4483 val &= ~DISPLAY_FREQUENCY_VALUES;
4484 val |= divider;
4485 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4486
4487 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4488 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4489 50))
4490 DRM_ERROR("timed out waiting for CDclk change\n");
4491 mutex_unlock(&dev_priv->dpio_lock);
4492 }
4493
4494 mutex_lock(&dev_priv->dpio_lock);
4495 /* adjust self-refresh exit latency value */
4496 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4497 val &= ~0x7f;
4498
4499 /*
4500 * For high bandwidth configs, we set a higher latency in the bunit
4501 * so that the core display fetch happens in time to avoid underruns.
4502 */
4503 if (cdclk == 400000)
4504 val |= 4500 / 250; /* 4.5 usec */
4505 else
4506 val |= 3000 / 250; /* 3.0 usec */
4507 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4508 mutex_unlock(&dev_priv->dpio_lock);
4509
4510 vlv_update_cdclk(dev);
4511 }
4512
4513 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4514 int max_pixclk)
4515 {
4516 int vco = valleyview_get_vco(dev_priv);
4517 int freq_320 = (vco << 1) % 320000 != 0 ? 333333 : 320000;
4518
4519 /*
4520 * Really only a few cases to deal with, as only 4 CDclks are supported:
4521 * 200MHz
4522 * 267MHz
4523 * 320/333MHz (depends on HPLL freq)
4524 * 400MHz
4525 * So we check to see whether we're above 90% of the lower bin and
4526 * adjust if needed.
4527 *
4528 * We seem to get an unstable or solid color picture at 200MHz.
4529 * Not sure what's wrong. For now use 200MHz only when all pipes
4530 * are off.
4531 */
4532 if (max_pixclk > freq_320*9/10)
4533 return 400000;
4534 else if (max_pixclk > 266667*9/10)
4535 return freq_320;
4536 else if (max_pixclk > 0)
4537 return 266667;
4538 else
4539 return 200000;
4540 }
4541
4542 /* compute the max pixel clock for new configuration */
4543 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4544 {
4545 struct drm_device *dev = dev_priv->dev;
4546 struct intel_crtc *intel_crtc;
4547 int max_pixclk = 0;
4548
4549 for_each_intel_crtc(dev, intel_crtc) {
4550 if (intel_crtc->new_enabled)
4551 max_pixclk = max(max_pixclk,
4552 intel_crtc->new_config->adjusted_mode.crtc_clock);
4553 }
4554
4555 return max_pixclk;
4556 }
4557
4558 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4559 unsigned *prepare_pipes)
4560 {
4561 struct drm_i915_private *dev_priv = dev->dev_private;
4562 struct intel_crtc *intel_crtc;
4563 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4564
4565 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4566 dev_priv->vlv_cdclk_freq)
4567 return;
4568
4569 /* disable/enable all currently active pipes while we change cdclk */
4570 for_each_intel_crtc(dev, intel_crtc)
4571 if (intel_crtc->base.enabled)
4572 *prepare_pipes |= (1 << intel_crtc->pipe);
4573 }
4574
4575 static void valleyview_modeset_global_resources(struct drm_device *dev)
4576 {
4577 struct drm_i915_private *dev_priv = dev->dev_private;
4578 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4579 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4580
4581 if (req_cdclk != dev_priv->vlv_cdclk_freq)
4582 valleyview_set_cdclk(dev, req_cdclk);
4583 modeset_update_crtc_power_domains(dev);
4584 }
4585
4586 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4587 {
4588 struct drm_device *dev = crtc->dev;
4589 struct drm_i915_private *dev_priv = dev->dev_private;
4590 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4591 struct intel_encoder *encoder;
4592 int pipe = intel_crtc->pipe;
4593 int plane = intel_crtc->plane;
4594 bool is_dsi;
4595 u32 dspcntr;
4596
4597 WARN_ON(!crtc->enabled);
4598
4599 if (intel_crtc->active)
4600 return;
4601
4602 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4603
4604 if (!is_dsi && !IS_CHERRYVIEW(dev))
4605 vlv_prepare_pll(intel_crtc);
4606
4607 /* Set up the display plane register */
4608 dspcntr = DISPPLANE_GAMMA_ENABLE;
4609
4610 if (intel_crtc->config.has_dp_encoder)
4611 intel_dp_set_m_n(intel_crtc);
4612
4613 intel_set_pipe_timings(intel_crtc);
4614
4615 /* pipesrc and dspsize control the size that is scaled from,
4616 * which should always be the user's requested size.
4617 */
4618 I915_WRITE(DSPSIZE(plane),
4619 ((intel_crtc->config.pipe_src_h - 1) << 16) |
4620 (intel_crtc->config.pipe_src_w - 1));
4621 I915_WRITE(DSPPOS(plane), 0);
4622
4623 i9xx_set_pipeconf(intel_crtc);
4624
4625 I915_WRITE(DSPCNTR(plane), dspcntr);
4626 POSTING_READ(DSPCNTR(plane));
4627
4628 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4629 crtc->x, crtc->y);
4630
4631 intel_crtc->active = true;
4632
4633 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4634
4635 for_each_encoder_on_crtc(dev, crtc, encoder)
4636 if (encoder->pre_pll_enable)
4637 encoder->pre_pll_enable(encoder);
4638
4639 if (!is_dsi) {
4640 if (IS_CHERRYVIEW(dev))
4641 chv_enable_pll(intel_crtc);
4642 else
4643 vlv_enable_pll(intel_crtc);
4644 }
4645
4646 for_each_encoder_on_crtc(dev, crtc, encoder)
4647 if (encoder->pre_enable)
4648 encoder->pre_enable(encoder);
4649
4650 i9xx_pfit_enable(intel_crtc);
4651
4652 intel_crtc_load_lut(crtc);
4653
4654 intel_update_watermarks(crtc);
4655 intel_enable_pipe(intel_crtc);
4656
4657 for_each_encoder_on_crtc(dev, crtc, encoder)
4658 encoder->enable(encoder);
4659
4660 intel_crtc_enable_planes(crtc);
4661
4662 /* Underruns don't raise interrupts, so check manually. */
4663 i9xx_check_fifo_underruns(dev);
4664 }
4665
4666 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4667 {
4668 struct drm_device *dev = crtc->base.dev;
4669 struct drm_i915_private *dev_priv = dev->dev_private;
4670
4671 I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4672 I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4673 }
4674
4675 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4676 {
4677 struct drm_device *dev = crtc->dev;
4678 struct drm_i915_private *dev_priv = dev->dev_private;
4679 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4680 struct intel_encoder *encoder;
4681 int pipe = intel_crtc->pipe;
4682 int plane = intel_crtc->plane;
4683 u32 dspcntr;
4684
4685 WARN_ON(!crtc->enabled);
4686
4687 if (intel_crtc->active)
4688 return;
4689
4690 i9xx_set_pll_dividers(intel_crtc);
4691
4692 /* Set up the display plane register */
4693 dspcntr = DISPPLANE_GAMMA_ENABLE;
4694
4695 if (pipe == 0)
4696 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4697 else
4698 dspcntr |= DISPPLANE_SEL_PIPE_B;
4699
4700 if (intel_crtc->config.has_dp_encoder)
4701 intel_dp_set_m_n(intel_crtc);
4702
4703 intel_set_pipe_timings(intel_crtc);
4704
4705 /* pipesrc and dspsize control the size that is scaled from,
4706 * which should always be the user's requested size.
4707 */
4708 I915_WRITE(DSPSIZE(plane),
4709 ((intel_crtc->config.pipe_src_h - 1) << 16) |
4710 (intel_crtc->config.pipe_src_w - 1));
4711 I915_WRITE(DSPPOS(plane), 0);
4712
4713 i9xx_set_pipeconf(intel_crtc);
4714
4715 I915_WRITE(DSPCNTR(plane), dspcntr);
4716 POSTING_READ(DSPCNTR(plane));
4717
4718 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4719 crtc->x, crtc->y);
4720
4721 intel_crtc->active = true;
4722
4723 if (!IS_GEN2(dev))
4724 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4725
4726 for_each_encoder_on_crtc(dev, crtc, encoder)
4727 if (encoder->pre_enable)
4728 encoder->pre_enable(encoder);
4729
4730 i9xx_enable_pll(intel_crtc);
4731
4732 i9xx_pfit_enable(intel_crtc);
4733
4734 intel_crtc_load_lut(crtc);
4735
4736 intel_update_watermarks(crtc);
4737 intel_enable_pipe(intel_crtc);
4738
4739 for_each_encoder_on_crtc(dev, crtc, encoder)
4740 encoder->enable(encoder);
4741
4742 intel_crtc_enable_planes(crtc);
4743
4744 /*
4745 * Gen2 reports pipe underruns whenever all planes are disabled.
4746 * So don't enable underrun reporting before at least some planes
4747 * are enabled.
4748 * FIXME: Need to fix the logic to work when we turn off all planes
4749 * but leave the pipe running.
4750 */
4751 if (IS_GEN2(dev))
4752 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4753
4754 /* Underruns don't raise interrupts, so check manually. */
4755 i9xx_check_fifo_underruns(dev);
4756 }
4757
4758 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4759 {
4760 struct drm_device *dev = crtc->base.dev;
4761 struct drm_i915_private *dev_priv = dev->dev_private;
4762
4763 if (!crtc->config.gmch_pfit.control)
4764 return;
4765
4766 assert_pipe_disabled(dev_priv, crtc->pipe);
4767
4768 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4769 I915_READ(PFIT_CONTROL));
4770 I915_WRITE(PFIT_CONTROL, 0);
4771 }
4772
4773 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4774 {
4775 struct drm_device *dev = crtc->dev;
4776 struct drm_i915_private *dev_priv = dev->dev_private;
4777 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4778 struct intel_encoder *encoder;
4779 int pipe = intel_crtc->pipe;
4780
4781 if (!intel_crtc->active)
4782 return;
4783
4784 /*
4785 * Gen2 reports pipe underruns whenever all planes are disabled.
4786 * So diasble underrun reporting before all the planes get disabled.
4787 * FIXME: Need to fix the logic to work when we turn off all planes
4788 * but leave the pipe running.
4789 */
4790 if (IS_GEN2(dev))
4791 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4792
4793 /*
4794 * Vblank time updates from the shadow to live plane control register
4795 * are blocked if the memory self-refresh mode is active at that
4796 * moment. So to make sure the plane gets truly disabled, disable
4797 * first the self-refresh mode. The self-refresh enable bit in turn
4798 * will be checked/applied by the HW only at the next frame start
4799 * event which is after the vblank start event, so we need to have a
4800 * wait-for-vblank between disabling the plane and the pipe.
4801 */
4802 intel_set_memory_cxsr(dev_priv, false);
4803 intel_crtc_disable_planes(crtc);
4804
4805 for_each_encoder_on_crtc(dev, crtc, encoder)
4806 encoder->disable(encoder);
4807
4808 /*
4809 * On gen2 planes are double buffered but the pipe isn't, so we must
4810 * wait for planes to fully turn off before disabling the pipe.
4811 * We also need to wait on all gmch platforms because of the
4812 * self-refresh mode constraint explained above.
4813 */
4814 intel_wait_for_vblank(dev, pipe);
4815
4816 intel_disable_pipe(dev_priv, pipe);
4817
4818 i9xx_pfit_disable(intel_crtc);
4819
4820 for_each_encoder_on_crtc(dev, crtc, encoder)
4821 if (encoder->post_disable)
4822 encoder->post_disable(encoder);
4823
4824 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4825 if (IS_CHERRYVIEW(dev))
4826 chv_disable_pll(dev_priv, pipe);
4827 else if (IS_VALLEYVIEW(dev))
4828 vlv_disable_pll(dev_priv, pipe);
4829 else
4830 i9xx_disable_pll(dev_priv, pipe);
4831 }
4832
4833 if (!IS_GEN2(dev))
4834 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4835
4836 intel_crtc->active = false;
4837 intel_update_watermarks(crtc);
4838
4839 mutex_lock(&dev->struct_mutex);
4840 intel_update_fbc(dev);
4841 mutex_unlock(&dev->struct_mutex);
4842 }
4843
4844 static void i9xx_crtc_off(struct drm_crtc *crtc)
4845 {
4846 }
4847
4848 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4849 bool enabled)
4850 {
4851 struct drm_device *dev = crtc->dev;
4852 struct drm_i915_master_private *master_priv;
4853 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4854 int pipe = intel_crtc->pipe;
4855
4856 if (!dev->primary->master)
4857 return;
4858
4859 master_priv = dev->primary->master->driver_priv;
4860 if (!master_priv->sarea_priv)
4861 return;
4862
4863 switch (pipe) {
4864 case 0:
4865 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4866 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4867 break;
4868 case 1:
4869 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4870 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4871 break;
4872 default:
4873 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4874 break;
4875 }
4876 }
4877
4878 /**
4879 * Sets the power management mode of the pipe and plane.
4880 */
4881 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4882 {
4883 struct drm_device *dev = crtc->dev;
4884 struct drm_i915_private *dev_priv = dev->dev_private;
4885 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4886 struct intel_encoder *intel_encoder;
4887 enum intel_display_power_domain domain;
4888 unsigned long domains;
4889 bool enable = false;
4890
4891 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4892 enable |= intel_encoder->connectors_active;
4893
4894 if (enable) {
4895 if (!intel_crtc->active) {
4896 /*
4897 * FIXME: DDI plls and relevant code isn't converted
4898 * yet, so do runtime PM for DPMS only for all other
4899 * platforms for now.
4900 */
4901 if (!HAS_DDI(dev)) {
4902 domains = get_crtc_power_domains(crtc);
4903 for_each_power_domain(domain, domains)
4904 intel_display_power_get(dev_priv, domain);
4905 intel_crtc->enabled_power_domains = domains;
4906 }
4907
4908 dev_priv->display.crtc_enable(crtc);
4909 }
4910 } else {
4911 if (intel_crtc->active) {
4912 dev_priv->display.crtc_disable(crtc);
4913
4914 if (!HAS_DDI(dev)) {
4915 domains = intel_crtc->enabled_power_domains;
4916 for_each_power_domain(domain, domains)
4917 intel_display_power_put(dev_priv, domain);
4918 intel_crtc->enabled_power_domains = 0;
4919 }
4920 }
4921 }
4922
4923 intel_crtc_update_sarea(crtc, enable);
4924 }
4925
4926 static void intel_crtc_disable(struct drm_crtc *crtc)
4927 {
4928 struct drm_device *dev = crtc->dev;
4929 struct drm_connector *connector;
4930 struct drm_i915_private *dev_priv = dev->dev_private;
4931 struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
4932 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4933
4934 /* crtc should still be enabled when we disable it. */
4935 WARN_ON(!crtc->enabled);
4936
4937 dev_priv->display.crtc_disable(crtc);
4938 intel_crtc_update_sarea(crtc, false);
4939 dev_priv->display.off(crtc);
4940
4941 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4942 assert_cursor_disabled(dev_priv, pipe);
4943 assert_pipe_disabled(dev->dev_private, pipe);
4944
4945 if (crtc->primary->fb) {
4946 mutex_lock(&dev->struct_mutex);
4947 intel_unpin_fb_obj(old_obj);
4948 i915_gem_track_fb(old_obj, NULL,
4949 INTEL_FRONTBUFFER_PRIMARY(pipe));
4950 mutex_unlock(&dev->struct_mutex);
4951 crtc->primary->fb = NULL;
4952 }
4953
4954 /* Update computed state. */
4955 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4956 if (!connector->encoder || !connector->encoder->crtc)
4957 continue;
4958
4959 if (connector->encoder->crtc != crtc)
4960 continue;
4961
4962 connector->dpms = DRM_MODE_DPMS_OFF;
4963 to_intel_encoder(connector->encoder)->connectors_active = false;
4964 }
4965 }
4966
4967 void intel_encoder_destroy(struct drm_encoder *encoder)
4968 {
4969 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4970
4971 drm_encoder_cleanup(encoder);
4972 kfree(intel_encoder);
4973 }
4974
4975 /* Simple dpms helper for encoders with just one connector, no cloning and only
4976 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4977 * state of the entire output pipe. */
4978 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4979 {
4980 if (mode == DRM_MODE_DPMS_ON) {
4981 encoder->connectors_active = true;
4982
4983 intel_crtc_update_dpms(encoder->base.crtc);
4984 } else {
4985 encoder->connectors_active = false;
4986
4987 intel_crtc_update_dpms(encoder->base.crtc);
4988 }
4989 }
4990
4991 /* Cross check the actual hw state with our own modeset state tracking (and it's
4992 * internal consistency). */
4993 static void intel_connector_check_state(struct intel_connector *connector)
4994 {
4995 if (connector->get_hw_state(connector)) {
4996 struct intel_encoder *encoder = connector->encoder;
4997 struct drm_crtc *crtc;
4998 bool encoder_enabled;
4999 enum pipe pipe;
5000
5001 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5002 connector->base.base.id,
5003 connector->base.name);
5004
5005 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5006 "wrong connector dpms state\n");
5007 WARN(connector->base.encoder != &encoder->base,
5008 "active connector not linked to encoder\n");
5009 WARN(!encoder->connectors_active,
5010 "encoder->connectors_active not set\n");
5011
5012 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5013 WARN(!encoder_enabled, "encoder not enabled\n");
5014 if (WARN_ON(!encoder->base.crtc))
5015 return;
5016
5017 crtc = encoder->base.crtc;
5018
5019 WARN(!crtc->enabled, "crtc not enabled\n");
5020 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5021 WARN(pipe != to_intel_crtc(crtc)->pipe,
5022 "encoder active on the wrong pipe\n");
5023 }
5024 }
5025
5026 /* Even simpler default implementation, if there's really no special case to
5027 * consider. */
5028 void intel_connector_dpms(struct drm_connector *connector, int mode)
5029 {
5030 /* All the simple cases only support two dpms states. */
5031 if (mode != DRM_MODE_DPMS_ON)
5032 mode = DRM_MODE_DPMS_OFF;
5033
5034 if (mode == connector->dpms)
5035 return;
5036
5037 connector->dpms = mode;
5038
5039 /* Only need to change hw state when actually enabled */
5040 if (connector->encoder)
5041 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5042
5043 intel_modeset_check_state(connector->dev);
5044 }
5045
5046 /* Simple connector->get_hw_state implementation for encoders that support only
5047 * one connector and no cloning and hence the encoder state determines the state
5048 * of the connector. */
5049 bool intel_connector_get_hw_state(struct intel_connector *connector)
5050 {
5051 enum pipe pipe = 0;
5052 struct intel_encoder *encoder = connector->encoder;
5053
5054 return encoder->get_hw_state(encoder, &pipe);
5055 }
5056
5057 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5058 struct intel_crtc_config *pipe_config)
5059 {
5060 struct drm_i915_private *dev_priv = dev->dev_private;
5061 struct intel_crtc *pipe_B_crtc =
5062 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5063
5064 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5065 pipe_name(pipe), pipe_config->fdi_lanes);
5066 if (pipe_config->fdi_lanes > 4) {
5067 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5068 pipe_name(pipe), pipe_config->fdi_lanes);
5069 return false;
5070 }
5071
5072 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5073 if (pipe_config->fdi_lanes > 2) {
5074 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5075 pipe_config->fdi_lanes);
5076 return false;
5077 } else {
5078 return true;
5079 }
5080 }
5081
5082 if (INTEL_INFO(dev)->num_pipes == 2)
5083 return true;
5084
5085 /* Ivybridge 3 pipe is really complicated */
5086 switch (pipe) {
5087 case PIPE_A:
5088 return true;
5089 case PIPE_B:
5090 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5091 pipe_config->fdi_lanes > 2) {
5092 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5093 pipe_name(pipe), pipe_config->fdi_lanes);
5094 return false;
5095 }
5096 return true;
5097 case PIPE_C:
5098 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5099 pipe_B_crtc->config.fdi_lanes <= 2) {
5100 if (pipe_config->fdi_lanes > 2) {
5101 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5102 pipe_name(pipe), pipe_config->fdi_lanes);
5103 return false;
5104 }
5105 } else {
5106 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5107 return false;
5108 }
5109 return true;
5110 default:
5111 BUG();
5112 }
5113 }
5114
5115 #define RETRY 1
5116 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5117 struct intel_crtc_config *pipe_config)
5118 {
5119 struct drm_device *dev = intel_crtc->base.dev;
5120 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5121 int lane, link_bw, fdi_dotclock;
5122 bool setup_ok, needs_recompute = false;
5123
5124 retry:
5125 /* FDI is a binary signal running at ~2.7GHz, encoding
5126 * each output octet as 10 bits. The actual frequency
5127 * is stored as a divider into a 100MHz clock, and the
5128 * mode pixel clock is stored in units of 1KHz.
5129 * Hence the bw of each lane in terms of the mode signal
5130 * is:
5131 */
5132 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5133
5134 fdi_dotclock = adjusted_mode->crtc_clock;
5135
5136 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5137 pipe_config->pipe_bpp);
5138
5139 pipe_config->fdi_lanes = lane;
5140
5141 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5142 link_bw, &pipe_config->fdi_m_n);
5143
5144 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5145 intel_crtc->pipe, pipe_config);
5146 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5147 pipe_config->pipe_bpp -= 2*3;
5148 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5149 pipe_config->pipe_bpp);
5150 needs_recompute = true;
5151 pipe_config->bw_constrained = true;
5152
5153 goto retry;
5154 }
5155
5156 if (needs_recompute)
5157 return RETRY;
5158
5159 return setup_ok ? 0 : -EINVAL;
5160 }
5161
5162 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5163 struct intel_crtc_config *pipe_config)
5164 {
5165 pipe_config->ips_enabled = i915.enable_ips &&
5166 hsw_crtc_supports_ips(crtc) &&
5167 pipe_config->pipe_bpp <= 24;
5168 }
5169
5170 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5171 struct intel_crtc_config *pipe_config)
5172 {
5173 struct drm_device *dev = crtc->base.dev;
5174 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5175
5176 /* FIXME should check pixel clock limits on all platforms */
5177 if (INTEL_INFO(dev)->gen < 4) {
5178 struct drm_i915_private *dev_priv = dev->dev_private;
5179 int clock_limit =
5180 dev_priv->display.get_display_clock_speed(dev);
5181
5182 /*
5183 * Enable pixel doubling when the dot clock
5184 * is > 90% of the (display) core speed.
5185 *
5186 * GDG double wide on either pipe,
5187 * otherwise pipe A only.
5188 */
5189 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5190 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5191 clock_limit *= 2;
5192 pipe_config->double_wide = true;
5193 }
5194
5195 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5196 return -EINVAL;
5197 }
5198
5199 /*
5200 * Pipe horizontal size must be even in:
5201 * - DVO ganged mode
5202 * - LVDS dual channel mode
5203 * - Double wide pipe
5204 */
5205 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5206 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5207 pipe_config->pipe_src_w &= ~1;
5208
5209 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5210 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5211 */
5212 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5213 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5214 return -EINVAL;
5215
5216 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5217 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5218 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5219 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5220 * for lvds. */
5221 pipe_config->pipe_bpp = 8*3;
5222 }
5223
5224 if (HAS_IPS(dev))
5225 hsw_compute_ips_config(crtc, pipe_config);
5226
5227 /*
5228 * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the
5229 * old clock survives for now.
5230 */
5231 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev) || HAS_DDI(dev))
5232 pipe_config->shared_dpll = crtc->config.shared_dpll;
5233
5234 if (pipe_config->has_pch_encoder)
5235 return ironlake_fdi_compute_config(crtc, pipe_config);
5236
5237 return 0;
5238 }
5239
5240 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5241 {
5242 struct drm_i915_private *dev_priv = dev->dev_private;
5243 int vco = valleyview_get_vco(dev_priv);
5244 u32 val;
5245 int divider;
5246
5247 mutex_lock(&dev_priv->dpio_lock);
5248 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5249 mutex_unlock(&dev_priv->dpio_lock);
5250
5251 divider = val & DISPLAY_FREQUENCY_VALUES;
5252
5253 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5254 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5255 "cdclk change in progress\n");
5256
5257 return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
5258 }
5259
5260 static int i945_get_display_clock_speed(struct drm_device *dev)
5261 {
5262 return 400000;
5263 }
5264
5265 static int i915_get_display_clock_speed(struct drm_device *dev)
5266 {
5267 return 333000;
5268 }
5269
5270 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5271 {
5272 return 200000;
5273 }
5274
5275 static int pnv_get_display_clock_speed(struct drm_device *dev)
5276 {
5277 u16 gcfgc = 0;
5278
5279 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5280
5281 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5282 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5283 return 267000;
5284 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5285 return 333000;
5286 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5287 return 444000;
5288 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5289 return 200000;
5290 default:
5291 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5292 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5293 return 133000;
5294 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5295 return 167000;
5296 }
5297 }
5298
5299 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5300 {
5301 u16 gcfgc = 0;
5302
5303 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5304
5305 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5306 return 133000;
5307 else {
5308 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5309 case GC_DISPLAY_CLOCK_333_MHZ:
5310 return 333000;
5311 default:
5312 case GC_DISPLAY_CLOCK_190_200_MHZ:
5313 return 190000;
5314 }
5315 }
5316 }
5317
5318 static int i865_get_display_clock_speed(struct drm_device *dev)
5319 {
5320 return 266000;
5321 }
5322
5323 static int i855_get_display_clock_speed(struct drm_device *dev)
5324 {
5325 u16 hpllcc = 0;
5326 /* Assume that the hardware is in the high speed state. This
5327 * should be the default.
5328 */
5329 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5330 case GC_CLOCK_133_200:
5331 case GC_CLOCK_100_200:
5332 return 200000;
5333 case GC_CLOCK_166_250:
5334 return 250000;
5335 case GC_CLOCK_100_133:
5336 return 133000;
5337 }
5338
5339 /* Shouldn't happen */
5340 return 0;
5341 }
5342
5343 static int i830_get_display_clock_speed(struct drm_device *dev)
5344 {
5345 return 133000;
5346 }
5347
5348 static void
5349 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5350 {
5351 while (*num > DATA_LINK_M_N_MASK ||
5352 *den > DATA_LINK_M_N_MASK) {
5353 *num >>= 1;
5354 *den >>= 1;
5355 }
5356 }
5357
5358 static void compute_m_n(unsigned int m, unsigned int n,
5359 uint32_t *ret_m, uint32_t *ret_n)
5360 {
5361 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5362 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5363 intel_reduce_m_n_ratio(ret_m, ret_n);
5364 }
5365
5366 void
5367 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5368 int pixel_clock, int link_clock,
5369 struct intel_link_m_n *m_n)
5370 {
5371 m_n->tu = 64;
5372
5373 compute_m_n(bits_per_pixel * pixel_clock,
5374 link_clock * nlanes * 8,
5375 &m_n->gmch_m, &m_n->gmch_n);
5376
5377 compute_m_n(pixel_clock, link_clock,
5378 &m_n->link_m, &m_n->link_n);
5379 }
5380
5381 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5382 {
5383 if (i915.panel_use_ssc >= 0)
5384 return i915.panel_use_ssc != 0;
5385 return dev_priv->vbt.lvds_use_ssc
5386 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5387 }
5388
5389 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5390 {
5391 struct drm_device *dev = crtc->dev;
5392 struct drm_i915_private *dev_priv = dev->dev_private;
5393 int refclk;
5394
5395 if (IS_VALLEYVIEW(dev)) {
5396 refclk = 100000;
5397 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5398 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5399 refclk = dev_priv->vbt.lvds_ssc_freq;
5400 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5401 } else if (!IS_GEN2(dev)) {
5402 refclk = 96000;
5403 } else {
5404 refclk = 48000;
5405 }
5406
5407 return refclk;
5408 }
5409
5410 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5411 {
5412 return (1 << dpll->n) << 16 | dpll->m2;
5413 }
5414
5415 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5416 {
5417 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5418 }
5419
5420 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5421 intel_clock_t *reduced_clock)
5422 {
5423 struct drm_device *dev = crtc->base.dev;
5424 u32 fp, fp2 = 0;
5425
5426 if (IS_PINEVIEW(dev)) {
5427 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5428 if (reduced_clock)
5429 fp2 = pnv_dpll_compute_fp(reduced_clock);
5430 } else {
5431 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5432 if (reduced_clock)
5433 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5434 }
5435
5436 crtc->config.dpll_hw_state.fp0 = fp;
5437
5438 crtc->lowfreq_avail = false;
5439 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5440 reduced_clock && i915.powersave) {
5441 crtc->config.dpll_hw_state.fp1 = fp2;
5442 crtc->lowfreq_avail = true;
5443 } else {
5444 crtc->config.dpll_hw_state.fp1 = fp;
5445 }
5446 }
5447
5448 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5449 pipe)
5450 {
5451 u32 reg_val;
5452
5453 /*
5454 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5455 * and set it to a reasonable value instead.
5456 */
5457 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5458 reg_val &= 0xffffff00;
5459 reg_val |= 0x00000030;
5460 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5461
5462 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5463 reg_val &= 0x8cffffff;
5464 reg_val = 0x8c000000;
5465 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5466
5467 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5468 reg_val &= 0xffffff00;
5469 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5470
5471 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5472 reg_val &= 0x00ffffff;
5473 reg_val |= 0xb0000000;
5474 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5475 }
5476
5477 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5478 struct intel_link_m_n *m_n)
5479 {
5480 struct drm_device *dev = crtc->base.dev;
5481 struct drm_i915_private *dev_priv = dev->dev_private;
5482 int pipe = crtc->pipe;
5483
5484 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5485 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5486 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5487 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5488 }
5489
5490 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5491 struct intel_link_m_n *m_n)
5492 {
5493 struct drm_device *dev = crtc->base.dev;
5494 struct drm_i915_private *dev_priv = dev->dev_private;
5495 int pipe = crtc->pipe;
5496 enum transcoder transcoder = crtc->config.cpu_transcoder;
5497
5498 if (INTEL_INFO(dev)->gen >= 5) {
5499 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5500 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5501 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5502 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5503 } else {
5504 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5505 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5506 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5507 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5508 }
5509 }
5510
5511 static void intel_dp_set_m_n(struct intel_crtc *crtc)
5512 {
5513 if (crtc->config.has_pch_encoder)
5514 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5515 else
5516 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5517 }
5518
5519 static void vlv_update_pll(struct intel_crtc *crtc)
5520 {
5521 u32 dpll, dpll_md;
5522
5523 /*
5524 * Enable DPIO clock input. We should never disable the reference
5525 * clock for pipe B, since VGA hotplug / manual detection depends
5526 * on it.
5527 */
5528 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5529 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5530 /* We should never disable this, set it here for state tracking */
5531 if (crtc->pipe == PIPE_B)
5532 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5533 dpll |= DPLL_VCO_ENABLE;
5534 crtc->config.dpll_hw_state.dpll = dpll;
5535
5536 dpll_md = (crtc->config.pixel_multiplier - 1)
5537 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5538 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5539 }
5540
5541 static void vlv_prepare_pll(struct intel_crtc *crtc)
5542 {
5543 struct drm_device *dev = crtc->base.dev;
5544 struct drm_i915_private *dev_priv = dev->dev_private;
5545 int pipe = crtc->pipe;
5546 u32 mdiv;
5547 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5548 u32 coreclk, reg_val;
5549
5550 mutex_lock(&dev_priv->dpio_lock);
5551
5552 bestn = crtc->config.dpll.n;
5553 bestm1 = crtc->config.dpll.m1;
5554 bestm2 = crtc->config.dpll.m2;
5555 bestp1 = crtc->config.dpll.p1;
5556 bestp2 = crtc->config.dpll.p2;
5557
5558 /* See eDP HDMI DPIO driver vbios notes doc */
5559
5560 /* PLL B needs special handling */
5561 if (pipe == PIPE_B)
5562 vlv_pllb_recal_opamp(dev_priv, pipe);
5563
5564 /* Set up Tx target for periodic Rcomp update */
5565 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5566
5567 /* Disable target IRef on PLL */
5568 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5569 reg_val &= 0x00ffffff;
5570 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5571
5572 /* Disable fast lock */
5573 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5574
5575 /* Set idtafcrecal before PLL is enabled */
5576 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5577 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5578 mdiv |= ((bestn << DPIO_N_SHIFT));
5579 mdiv |= (1 << DPIO_K_SHIFT);
5580
5581 /*
5582 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5583 * but we don't support that).
5584 * Note: don't use the DAC post divider as it seems unstable.
5585 */
5586 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5587 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5588
5589 mdiv |= DPIO_ENABLE_CALIBRATION;
5590 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5591
5592 /* Set HBR and RBR LPF coefficients */
5593 if (crtc->config.port_clock == 162000 ||
5594 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5595 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5596 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5597 0x009f0003);
5598 else
5599 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5600 0x00d0000f);
5601
5602 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5603 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5604 /* Use SSC source */
5605 if (pipe == PIPE_A)
5606 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5607 0x0df40000);
5608 else
5609 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5610 0x0df70000);
5611 } else { /* HDMI or VGA */
5612 /* Use bend source */
5613 if (pipe == PIPE_A)
5614 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5615 0x0df70000);
5616 else
5617 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5618 0x0df40000);
5619 }
5620
5621 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5622 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5623 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5624 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5625 coreclk |= 0x01000000;
5626 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5627
5628 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5629 mutex_unlock(&dev_priv->dpio_lock);
5630 }
5631
5632 static void chv_update_pll(struct intel_crtc *crtc)
5633 {
5634 struct drm_device *dev = crtc->base.dev;
5635 struct drm_i915_private *dev_priv = dev->dev_private;
5636 int pipe = crtc->pipe;
5637 int dpll_reg = DPLL(crtc->pipe);
5638 enum dpio_channel port = vlv_pipe_to_channel(pipe);
5639 u32 loopfilter, intcoeff;
5640 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5641 int refclk;
5642
5643 crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5644 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5645 DPLL_VCO_ENABLE;
5646 if (pipe != PIPE_A)
5647 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5648
5649 crtc->config.dpll_hw_state.dpll_md =
5650 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5651
5652 bestn = crtc->config.dpll.n;
5653 bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5654 bestm1 = crtc->config.dpll.m1;
5655 bestm2 = crtc->config.dpll.m2 >> 22;
5656 bestp1 = crtc->config.dpll.p1;
5657 bestp2 = crtc->config.dpll.p2;
5658
5659 /*
5660 * Enable Refclk and SSC
5661 */
5662 I915_WRITE(dpll_reg,
5663 crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5664
5665 mutex_lock(&dev_priv->dpio_lock);
5666
5667 /* p1 and p2 divider */
5668 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5669 5 << DPIO_CHV_S1_DIV_SHIFT |
5670 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5671 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5672 1 << DPIO_CHV_K_DIV_SHIFT);
5673
5674 /* Feedback post-divider - m2 */
5675 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5676
5677 /* Feedback refclk divider - n and m1 */
5678 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5679 DPIO_CHV_M1_DIV_BY_2 |
5680 1 << DPIO_CHV_N_DIV_SHIFT);
5681
5682 /* M2 fraction division */
5683 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5684
5685 /* M2 fraction division enable */
5686 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5687 DPIO_CHV_FRAC_DIV_EN |
5688 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5689
5690 /* Loop filter */
5691 refclk = i9xx_get_refclk(&crtc->base, 0);
5692 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5693 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5694 if (refclk == 100000)
5695 intcoeff = 11;
5696 else if (refclk == 38400)
5697 intcoeff = 10;
5698 else
5699 intcoeff = 9;
5700 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5701 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5702
5703 /* AFC Recal */
5704 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5705 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5706 DPIO_AFC_RECAL);
5707
5708 mutex_unlock(&dev_priv->dpio_lock);
5709 }
5710
5711 static void i9xx_update_pll(struct intel_crtc *crtc,
5712 intel_clock_t *reduced_clock,
5713 int num_connectors)
5714 {
5715 struct drm_device *dev = crtc->base.dev;
5716 struct drm_i915_private *dev_priv = dev->dev_private;
5717 u32 dpll;
5718 bool is_sdvo;
5719 struct dpll *clock = &crtc->config.dpll;
5720
5721 i9xx_update_pll_dividers(crtc, reduced_clock);
5722
5723 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5724 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5725
5726 dpll = DPLL_VGA_MODE_DIS;
5727
5728 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5729 dpll |= DPLLB_MODE_LVDS;
5730 else
5731 dpll |= DPLLB_MODE_DAC_SERIAL;
5732
5733 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5734 dpll |= (crtc->config.pixel_multiplier - 1)
5735 << SDVO_MULTIPLIER_SHIFT_HIRES;
5736 }
5737
5738 if (is_sdvo)
5739 dpll |= DPLL_SDVO_HIGH_SPEED;
5740
5741 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5742 dpll |= DPLL_SDVO_HIGH_SPEED;
5743
5744 /* compute bitmask from p1 value */
5745 if (IS_PINEVIEW(dev))
5746 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5747 else {
5748 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5749 if (IS_G4X(dev) && reduced_clock)
5750 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5751 }
5752 switch (clock->p2) {
5753 case 5:
5754 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5755 break;
5756 case 7:
5757 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5758 break;
5759 case 10:
5760 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5761 break;
5762 case 14:
5763 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5764 break;
5765 }
5766 if (INTEL_INFO(dev)->gen >= 4)
5767 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5768
5769 if (crtc->config.sdvo_tv_clock)
5770 dpll |= PLL_REF_INPUT_TVCLKINBC;
5771 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5772 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5773 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5774 else
5775 dpll |= PLL_REF_INPUT_DREFCLK;
5776
5777 dpll |= DPLL_VCO_ENABLE;
5778 crtc->config.dpll_hw_state.dpll = dpll;
5779
5780 if (INTEL_INFO(dev)->gen >= 4) {
5781 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5782 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5783 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5784 }
5785 }
5786
5787 static void i8xx_update_pll(struct intel_crtc *crtc,
5788 intel_clock_t *reduced_clock,
5789 int num_connectors)
5790 {
5791 struct drm_device *dev = crtc->base.dev;
5792 struct drm_i915_private *dev_priv = dev->dev_private;
5793 u32 dpll;
5794 struct dpll *clock = &crtc->config.dpll;
5795
5796 i9xx_update_pll_dividers(crtc, reduced_clock);
5797
5798 dpll = DPLL_VGA_MODE_DIS;
5799
5800 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5801 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5802 } else {
5803 if (clock->p1 == 2)
5804 dpll |= PLL_P1_DIVIDE_BY_TWO;
5805 else
5806 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5807 if (clock->p2 == 4)
5808 dpll |= PLL_P2_DIVIDE_BY_4;
5809 }
5810
5811 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5812 dpll |= DPLL_DVO_2X_MODE;
5813
5814 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5815 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5816 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5817 else
5818 dpll |= PLL_REF_INPUT_DREFCLK;
5819
5820 dpll |= DPLL_VCO_ENABLE;
5821 crtc->config.dpll_hw_state.dpll = dpll;
5822 }
5823
5824 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5825 {
5826 struct drm_device *dev = intel_crtc->base.dev;
5827 struct drm_i915_private *dev_priv = dev->dev_private;
5828 enum pipe pipe = intel_crtc->pipe;
5829 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5830 struct drm_display_mode *adjusted_mode =
5831 &intel_crtc->config.adjusted_mode;
5832 uint32_t crtc_vtotal, crtc_vblank_end;
5833 int vsyncshift = 0;
5834
5835 /* We need to be careful not to changed the adjusted mode, for otherwise
5836 * the hw state checker will get angry at the mismatch. */
5837 crtc_vtotal = adjusted_mode->crtc_vtotal;
5838 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5839
5840 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5841 /* the chip adds 2 halflines automatically */
5842 crtc_vtotal -= 1;
5843 crtc_vblank_end -= 1;
5844
5845 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5846 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5847 else
5848 vsyncshift = adjusted_mode->crtc_hsync_start -
5849 adjusted_mode->crtc_htotal / 2;
5850 if (vsyncshift < 0)
5851 vsyncshift += adjusted_mode->crtc_htotal;
5852 }
5853
5854 if (INTEL_INFO(dev)->gen > 3)
5855 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5856
5857 I915_WRITE(HTOTAL(cpu_transcoder),
5858 (adjusted_mode->crtc_hdisplay - 1) |
5859 ((adjusted_mode->crtc_htotal - 1) << 16));
5860 I915_WRITE(HBLANK(cpu_transcoder),
5861 (adjusted_mode->crtc_hblank_start - 1) |
5862 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5863 I915_WRITE(HSYNC(cpu_transcoder),
5864 (adjusted_mode->crtc_hsync_start - 1) |
5865 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5866
5867 I915_WRITE(VTOTAL(cpu_transcoder),
5868 (adjusted_mode->crtc_vdisplay - 1) |
5869 ((crtc_vtotal - 1) << 16));
5870 I915_WRITE(VBLANK(cpu_transcoder),
5871 (adjusted_mode->crtc_vblank_start - 1) |
5872 ((crtc_vblank_end - 1) << 16));
5873 I915_WRITE(VSYNC(cpu_transcoder),
5874 (adjusted_mode->crtc_vsync_start - 1) |
5875 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5876
5877 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5878 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5879 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5880 * bits. */
5881 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5882 (pipe == PIPE_B || pipe == PIPE_C))
5883 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5884
5885 /* pipesrc controls the size that is scaled from, which should
5886 * always be the user's requested size.
5887 */
5888 I915_WRITE(PIPESRC(pipe),
5889 ((intel_crtc->config.pipe_src_w - 1) << 16) |
5890 (intel_crtc->config.pipe_src_h - 1));
5891 }
5892
5893 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5894 struct intel_crtc_config *pipe_config)
5895 {
5896 struct drm_device *dev = crtc->base.dev;
5897 struct drm_i915_private *dev_priv = dev->dev_private;
5898 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5899 uint32_t tmp;
5900
5901 tmp = I915_READ(HTOTAL(cpu_transcoder));
5902 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5903 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5904 tmp = I915_READ(HBLANK(cpu_transcoder));
5905 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5906 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5907 tmp = I915_READ(HSYNC(cpu_transcoder));
5908 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5909 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5910
5911 tmp = I915_READ(VTOTAL(cpu_transcoder));
5912 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5913 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5914 tmp = I915_READ(VBLANK(cpu_transcoder));
5915 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5916 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5917 tmp = I915_READ(VSYNC(cpu_transcoder));
5918 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5919 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5920
5921 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5922 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5923 pipe_config->adjusted_mode.crtc_vtotal += 1;
5924 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5925 }
5926
5927 tmp = I915_READ(PIPESRC(crtc->pipe));
5928 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5929 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5930
5931 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5932 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5933 }
5934
5935 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5936 struct intel_crtc_config *pipe_config)
5937 {
5938 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5939 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5940 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5941 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5942
5943 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5944 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5945 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5946 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5947
5948 mode->flags = pipe_config->adjusted_mode.flags;
5949
5950 mode->clock = pipe_config->adjusted_mode.crtc_clock;
5951 mode->flags |= pipe_config->adjusted_mode.flags;
5952 }
5953
5954 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5955 {
5956 struct drm_device *dev = intel_crtc->base.dev;
5957 struct drm_i915_private *dev_priv = dev->dev_private;
5958 uint32_t pipeconf;
5959
5960 pipeconf = 0;
5961
5962 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5963 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5964 pipeconf |= PIPECONF_ENABLE;
5965
5966 if (intel_crtc->config.double_wide)
5967 pipeconf |= PIPECONF_DOUBLE_WIDE;
5968
5969 /* only g4x and later have fancy bpc/dither controls */
5970 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5971 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5972 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5973 pipeconf |= PIPECONF_DITHER_EN |
5974 PIPECONF_DITHER_TYPE_SP;
5975
5976 switch (intel_crtc->config.pipe_bpp) {
5977 case 18:
5978 pipeconf |= PIPECONF_6BPC;
5979 break;
5980 case 24:
5981 pipeconf |= PIPECONF_8BPC;
5982 break;
5983 case 30:
5984 pipeconf |= PIPECONF_10BPC;
5985 break;
5986 default:
5987 /* Case prevented by intel_choose_pipe_bpp_dither. */
5988 BUG();
5989 }
5990 }
5991
5992 if (HAS_PIPE_CXSR(dev)) {
5993 if (intel_crtc->lowfreq_avail) {
5994 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5995 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5996 } else {
5997 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5998 }
5999 }
6000
6001 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6002 if (INTEL_INFO(dev)->gen < 4 ||
6003 intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
6004 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6005 else
6006 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6007 } else
6008 pipeconf |= PIPECONF_PROGRESSIVE;
6009
6010 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6011 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6012
6013 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6014 POSTING_READ(PIPECONF(intel_crtc->pipe));
6015 }
6016
6017 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
6018 int x, int y,
6019 struct drm_framebuffer *fb)
6020 {
6021 struct drm_device *dev = crtc->dev;
6022 struct drm_i915_private *dev_priv = dev->dev_private;
6023 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6024 int refclk, num_connectors = 0;
6025 intel_clock_t clock, reduced_clock;
6026 bool ok, has_reduced_clock = false;
6027 bool is_lvds = false, is_dsi = false;
6028 struct intel_encoder *encoder;
6029 const intel_limit_t *limit;
6030
6031 for_each_encoder_on_crtc(dev, crtc, encoder) {
6032 switch (encoder->type) {
6033 case INTEL_OUTPUT_LVDS:
6034 is_lvds = true;
6035 break;
6036 case INTEL_OUTPUT_DSI:
6037 is_dsi = true;
6038 break;
6039 }
6040
6041 num_connectors++;
6042 }
6043
6044 if (is_dsi)
6045 return 0;
6046
6047 if (!intel_crtc->config.clock_set) {
6048 refclk = i9xx_get_refclk(crtc, num_connectors);
6049
6050 /*
6051 * Returns a set of divisors for the desired target clock with
6052 * the given refclk, or FALSE. The returned values represent
6053 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6054 * 2) / p1 / p2.
6055 */
6056 limit = intel_limit(crtc, refclk);
6057 ok = dev_priv->display.find_dpll(limit, crtc,
6058 intel_crtc->config.port_clock,
6059 refclk, NULL, &clock);
6060 if (!ok) {
6061 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6062 return -EINVAL;
6063 }
6064
6065 if (is_lvds && dev_priv->lvds_downclock_avail) {
6066 /*
6067 * Ensure we match the reduced clock's P to the target
6068 * clock. If the clocks don't match, we can't switch
6069 * the display clock by using the FP0/FP1. In such case
6070 * we will disable the LVDS downclock feature.
6071 */
6072 has_reduced_clock =
6073 dev_priv->display.find_dpll(limit, crtc,
6074 dev_priv->lvds_downclock,
6075 refclk, &clock,
6076 &reduced_clock);
6077 }
6078 /* Compat-code for transition, will disappear. */
6079 intel_crtc->config.dpll.n = clock.n;
6080 intel_crtc->config.dpll.m1 = clock.m1;
6081 intel_crtc->config.dpll.m2 = clock.m2;
6082 intel_crtc->config.dpll.p1 = clock.p1;
6083 intel_crtc->config.dpll.p2 = clock.p2;
6084 }
6085
6086 if (IS_GEN2(dev)) {
6087 i8xx_update_pll(intel_crtc,
6088 has_reduced_clock ? &reduced_clock : NULL,
6089 num_connectors);
6090 } else if (IS_CHERRYVIEW(dev)) {
6091 chv_update_pll(intel_crtc);
6092 } else if (IS_VALLEYVIEW(dev)) {
6093 vlv_update_pll(intel_crtc);
6094 } else {
6095 i9xx_update_pll(intel_crtc,
6096 has_reduced_clock ? &reduced_clock : NULL,
6097 num_connectors);
6098 }
6099
6100 return 0;
6101 }
6102
6103 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6104 struct intel_crtc_config *pipe_config)
6105 {
6106 struct drm_device *dev = crtc->base.dev;
6107 struct drm_i915_private *dev_priv = dev->dev_private;
6108 uint32_t tmp;
6109
6110 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6111 return;
6112
6113 tmp = I915_READ(PFIT_CONTROL);
6114 if (!(tmp & PFIT_ENABLE))
6115 return;
6116
6117 /* Check whether the pfit is attached to our pipe. */
6118 if (INTEL_INFO(dev)->gen < 4) {
6119 if (crtc->pipe != PIPE_B)
6120 return;
6121 } else {
6122 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6123 return;
6124 }
6125
6126 pipe_config->gmch_pfit.control = tmp;
6127 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6128 if (INTEL_INFO(dev)->gen < 5)
6129 pipe_config->gmch_pfit.lvds_border_bits =
6130 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6131 }
6132
6133 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6134 struct intel_crtc_config *pipe_config)
6135 {
6136 struct drm_device *dev = crtc->base.dev;
6137 struct drm_i915_private *dev_priv = dev->dev_private;
6138 int pipe = pipe_config->cpu_transcoder;
6139 intel_clock_t clock;
6140 u32 mdiv;
6141 int refclk = 100000;
6142
6143 mutex_lock(&dev_priv->dpio_lock);
6144 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6145 mutex_unlock(&dev_priv->dpio_lock);
6146
6147 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6148 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6149 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6150 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6151 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6152
6153 vlv_clock(refclk, &clock);
6154
6155 /* clock.dot is the fast clock */
6156 pipe_config->port_clock = clock.dot / 5;
6157 }
6158
6159 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6160 struct intel_plane_config *plane_config)
6161 {
6162 struct drm_device *dev = crtc->base.dev;
6163 struct drm_i915_private *dev_priv = dev->dev_private;
6164 u32 val, base, offset;
6165 int pipe = crtc->pipe, plane = crtc->plane;
6166 int fourcc, pixel_format;
6167 int aligned_height;
6168
6169 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6170 if (!crtc->base.primary->fb) {
6171 DRM_DEBUG_KMS("failed to alloc fb\n");
6172 return;
6173 }
6174
6175 val = I915_READ(DSPCNTR(plane));
6176
6177 if (INTEL_INFO(dev)->gen >= 4)
6178 if (val & DISPPLANE_TILED)
6179 plane_config->tiled = true;
6180
6181 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6182 fourcc = intel_format_to_fourcc(pixel_format);
6183 crtc->base.primary->fb->pixel_format = fourcc;
6184 crtc->base.primary->fb->bits_per_pixel =
6185 drm_format_plane_cpp(fourcc, 0) * 8;
6186
6187 if (INTEL_INFO(dev)->gen >= 4) {
6188 if (plane_config->tiled)
6189 offset = I915_READ(DSPTILEOFF(plane));
6190 else
6191 offset = I915_READ(DSPLINOFF(plane));
6192 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6193 } else {
6194 base = I915_READ(DSPADDR(plane));
6195 }
6196 plane_config->base = base;
6197
6198 val = I915_READ(PIPESRC(pipe));
6199 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6200 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6201
6202 val = I915_READ(DSPSTRIDE(pipe));
6203 crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
6204
6205 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6206 plane_config->tiled);
6207
6208 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6209 aligned_height);
6210
6211 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6212 pipe, plane, crtc->base.primary->fb->width,
6213 crtc->base.primary->fb->height,
6214 crtc->base.primary->fb->bits_per_pixel, base,
6215 crtc->base.primary->fb->pitches[0],
6216 plane_config->size);
6217
6218 }
6219
6220 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6221 struct intel_crtc_config *pipe_config)
6222 {
6223 struct drm_device *dev = crtc->base.dev;
6224 struct drm_i915_private *dev_priv = dev->dev_private;
6225 int pipe = pipe_config->cpu_transcoder;
6226 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6227 intel_clock_t clock;
6228 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6229 int refclk = 100000;
6230
6231 mutex_lock(&dev_priv->dpio_lock);
6232 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6233 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6234 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6235 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6236 mutex_unlock(&dev_priv->dpio_lock);
6237
6238 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6239 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6240 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6241 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6242 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6243
6244 chv_clock(refclk, &clock);
6245
6246 /* clock.dot is the fast clock */
6247 pipe_config->port_clock = clock.dot / 5;
6248 }
6249
6250 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6251 struct intel_crtc_config *pipe_config)
6252 {
6253 struct drm_device *dev = crtc->base.dev;
6254 struct drm_i915_private *dev_priv = dev->dev_private;
6255 uint32_t tmp;
6256
6257 if (!intel_display_power_enabled(dev_priv,
6258 POWER_DOMAIN_PIPE(crtc->pipe)))
6259 return false;
6260
6261 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6262 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6263
6264 tmp = I915_READ(PIPECONF(crtc->pipe));
6265 if (!(tmp & PIPECONF_ENABLE))
6266 return false;
6267
6268 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6269 switch (tmp & PIPECONF_BPC_MASK) {
6270 case PIPECONF_6BPC:
6271 pipe_config->pipe_bpp = 18;
6272 break;
6273 case PIPECONF_8BPC:
6274 pipe_config->pipe_bpp = 24;
6275 break;
6276 case PIPECONF_10BPC:
6277 pipe_config->pipe_bpp = 30;
6278 break;
6279 default:
6280 break;
6281 }
6282 }
6283
6284 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6285 pipe_config->limited_color_range = true;
6286
6287 if (INTEL_INFO(dev)->gen < 4)
6288 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6289
6290 intel_get_pipe_timings(crtc, pipe_config);
6291
6292 i9xx_get_pfit_config(crtc, pipe_config);
6293
6294 if (INTEL_INFO(dev)->gen >= 4) {
6295 tmp = I915_READ(DPLL_MD(crtc->pipe));
6296 pipe_config->pixel_multiplier =
6297 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6298 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6299 pipe_config->dpll_hw_state.dpll_md = tmp;
6300 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6301 tmp = I915_READ(DPLL(crtc->pipe));
6302 pipe_config->pixel_multiplier =
6303 ((tmp & SDVO_MULTIPLIER_MASK)
6304 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6305 } else {
6306 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6307 * port and will be fixed up in the encoder->get_config
6308 * function. */
6309 pipe_config->pixel_multiplier = 1;
6310 }
6311 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6312 if (!IS_VALLEYVIEW(dev)) {
6313 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6314 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6315 } else {
6316 /* Mask out read-only status bits. */
6317 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6318 DPLL_PORTC_READY_MASK |
6319 DPLL_PORTB_READY_MASK);
6320 }
6321
6322 if (IS_CHERRYVIEW(dev))
6323 chv_crtc_clock_get(crtc, pipe_config);
6324 else if (IS_VALLEYVIEW(dev))
6325 vlv_crtc_clock_get(crtc, pipe_config);
6326 else
6327 i9xx_crtc_clock_get(crtc, pipe_config);
6328
6329 return true;
6330 }
6331
6332 static void ironlake_init_pch_refclk(struct drm_device *dev)
6333 {
6334 struct drm_i915_private *dev_priv = dev->dev_private;
6335 struct drm_mode_config *mode_config = &dev->mode_config;
6336 struct intel_encoder *encoder;
6337 u32 val, final;
6338 bool has_lvds = false;
6339 bool has_cpu_edp = false;
6340 bool has_panel = false;
6341 bool has_ck505 = false;
6342 bool can_ssc = false;
6343
6344 /* We need to take the global config into account */
6345 list_for_each_entry(encoder, &mode_config->encoder_list,
6346 base.head) {
6347 switch (encoder->type) {
6348 case INTEL_OUTPUT_LVDS:
6349 has_panel = true;
6350 has_lvds = true;
6351 break;
6352 case INTEL_OUTPUT_EDP:
6353 has_panel = true;
6354 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6355 has_cpu_edp = true;
6356 break;
6357 }
6358 }
6359
6360 if (HAS_PCH_IBX(dev)) {
6361 has_ck505 = dev_priv->vbt.display_clock_mode;
6362 can_ssc = has_ck505;
6363 } else {
6364 has_ck505 = false;
6365 can_ssc = true;
6366 }
6367
6368 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6369 has_panel, has_lvds, has_ck505);
6370
6371 /* Ironlake: try to setup display ref clock before DPLL
6372 * enabling. This is only under driver's control after
6373 * PCH B stepping, previous chipset stepping should be
6374 * ignoring this setting.
6375 */
6376 val = I915_READ(PCH_DREF_CONTROL);
6377
6378 /* As we must carefully and slowly disable/enable each source in turn,
6379 * compute the final state we want first and check if we need to
6380 * make any changes at all.
6381 */
6382 final = val;
6383 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6384 if (has_ck505)
6385 final |= DREF_NONSPREAD_CK505_ENABLE;
6386 else
6387 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6388
6389 final &= ~DREF_SSC_SOURCE_MASK;
6390 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6391 final &= ~DREF_SSC1_ENABLE;
6392
6393 if (has_panel) {
6394 final |= DREF_SSC_SOURCE_ENABLE;
6395
6396 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6397 final |= DREF_SSC1_ENABLE;
6398
6399 if (has_cpu_edp) {
6400 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6401 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6402 else
6403 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6404 } else
6405 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6406 } else {
6407 final |= DREF_SSC_SOURCE_DISABLE;
6408 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6409 }
6410
6411 if (final == val)
6412 return;
6413
6414 /* Always enable nonspread source */
6415 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6416
6417 if (has_ck505)
6418 val |= DREF_NONSPREAD_CK505_ENABLE;
6419 else
6420 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6421
6422 if (has_panel) {
6423 val &= ~DREF_SSC_SOURCE_MASK;
6424 val |= DREF_SSC_SOURCE_ENABLE;
6425
6426 /* SSC must be turned on before enabling the CPU output */
6427 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6428 DRM_DEBUG_KMS("Using SSC on panel\n");
6429 val |= DREF_SSC1_ENABLE;
6430 } else
6431 val &= ~DREF_SSC1_ENABLE;
6432
6433 /* Get SSC going before enabling the outputs */
6434 I915_WRITE(PCH_DREF_CONTROL, val);
6435 POSTING_READ(PCH_DREF_CONTROL);
6436 udelay(200);
6437
6438 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6439
6440 /* Enable CPU source on CPU attached eDP */
6441 if (has_cpu_edp) {
6442 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6443 DRM_DEBUG_KMS("Using SSC on eDP\n");
6444 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6445 } else
6446 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6447 } else
6448 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6449
6450 I915_WRITE(PCH_DREF_CONTROL, val);
6451 POSTING_READ(PCH_DREF_CONTROL);
6452 udelay(200);
6453 } else {
6454 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6455
6456 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6457
6458 /* Turn off CPU output */
6459 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6460
6461 I915_WRITE(PCH_DREF_CONTROL, val);
6462 POSTING_READ(PCH_DREF_CONTROL);
6463 udelay(200);
6464
6465 /* Turn off the SSC source */
6466 val &= ~DREF_SSC_SOURCE_MASK;
6467 val |= DREF_SSC_SOURCE_DISABLE;
6468
6469 /* Turn off SSC1 */
6470 val &= ~DREF_SSC1_ENABLE;
6471
6472 I915_WRITE(PCH_DREF_CONTROL, val);
6473 POSTING_READ(PCH_DREF_CONTROL);
6474 udelay(200);
6475 }
6476
6477 BUG_ON(val != final);
6478 }
6479
6480 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6481 {
6482 uint32_t tmp;
6483
6484 tmp = I915_READ(SOUTH_CHICKEN2);
6485 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6486 I915_WRITE(SOUTH_CHICKEN2, tmp);
6487
6488 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6489 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6490 DRM_ERROR("FDI mPHY reset assert timeout\n");
6491
6492 tmp = I915_READ(SOUTH_CHICKEN2);
6493 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6494 I915_WRITE(SOUTH_CHICKEN2, tmp);
6495
6496 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6497 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6498 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6499 }
6500
6501 /* WaMPhyProgramming:hsw */
6502 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6503 {
6504 uint32_t tmp;
6505
6506 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6507 tmp &= ~(0xFF << 24);
6508 tmp |= (0x12 << 24);
6509 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6510
6511 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6512 tmp |= (1 << 11);
6513 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6514
6515 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6516 tmp |= (1 << 11);
6517 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6518
6519 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6520 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6521 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6522
6523 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6524 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6525 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6526
6527 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6528 tmp &= ~(7 << 13);
6529 tmp |= (5 << 13);
6530 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6531
6532 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6533 tmp &= ~(7 << 13);
6534 tmp |= (5 << 13);
6535 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6536
6537 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6538 tmp &= ~0xFF;
6539 tmp |= 0x1C;
6540 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6541
6542 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6543 tmp &= ~0xFF;
6544 tmp |= 0x1C;
6545 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6546
6547 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6548 tmp &= ~(0xFF << 16);
6549 tmp |= (0x1C << 16);
6550 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6551
6552 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6553 tmp &= ~(0xFF << 16);
6554 tmp |= (0x1C << 16);
6555 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6556
6557 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6558 tmp |= (1 << 27);
6559 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6560
6561 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6562 tmp |= (1 << 27);
6563 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6564
6565 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6566 tmp &= ~(0xF << 28);
6567 tmp |= (4 << 28);
6568 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6569
6570 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6571 tmp &= ~(0xF << 28);
6572 tmp |= (4 << 28);
6573 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6574 }
6575
6576 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6577 * Programming" based on the parameters passed:
6578 * - Sequence to enable CLKOUT_DP
6579 * - Sequence to enable CLKOUT_DP without spread
6580 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6581 */
6582 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6583 bool with_fdi)
6584 {
6585 struct drm_i915_private *dev_priv = dev->dev_private;
6586 uint32_t reg, tmp;
6587
6588 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6589 with_spread = true;
6590 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6591 with_fdi, "LP PCH doesn't have FDI\n"))
6592 with_fdi = false;
6593
6594 mutex_lock(&dev_priv->dpio_lock);
6595
6596 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6597 tmp &= ~SBI_SSCCTL_DISABLE;
6598 tmp |= SBI_SSCCTL_PATHALT;
6599 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6600
6601 udelay(24);
6602
6603 if (with_spread) {
6604 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6605 tmp &= ~SBI_SSCCTL_PATHALT;
6606 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6607
6608 if (with_fdi) {
6609 lpt_reset_fdi_mphy(dev_priv);
6610 lpt_program_fdi_mphy(dev_priv);
6611 }
6612 }
6613
6614 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6615 SBI_GEN0 : SBI_DBUFF0;
6616 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6617 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6618 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6619
6620 mutex_unlock(&dev_priv->dpio_lock);
6621 }
6622
6623 /* Sequence to disable CLKOUT_DP */
6624 static void lpt_disable_clkout_dp(struct drm_device *dev)
6625 {
6626 struct drm_i915_private *dev_priv = dev->dev_private;
6627 uint32_t reg, tmp;
6628
6629 mutex_lock(&dev_priv->dpio_lock);
6630
6631 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6632 SBI_GEN0 : SBI_DBUFF0;
6633 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6634 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6635 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6636
6637 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6638 if (!(tmp & SBI_SSCCTL_DISABLE)) {
6639 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6640 tmp |= SBI_SSCCTL_PATHALT;
6641 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6642 udelay(32);
6643 }
6644 tmp |= SBI_SSCCTL_DISABLE;
6645 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6646 }
6647
6648 mutex_unlock(&dev_priv->dpio_lock);
6649 }
6650
6651 static void lpt_init_pch_refclk(struct drm_device *dev)
6652 {
6653 struct drm_mode_config *mode_config = &dev->mode_config;
6654 struct intel_encoder *encoder;
6655 bool has_vga = false;
6656
6657 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
6658 switch (encoder->type) {
6659 case INTEL_OUTPUT_ANALOG:
6660 has_vga = true;
6661 break;
6662 }
6663 }
6664
6665 if (has_vga)
6666 lpt_enable_clkout_dp(dev, true, true);
6667 else
6668 lpt_disable_clkout_dp(dev);
6669 }
6670
6671 /*
6672 * Initialize reference clocks when the driver loads
6673 */
6674 void intel_init_pch_refclk(struct drm_device *dev)
6675 {
6676 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6677 ironlake_init_pch_refclk(dev);
6678 else if (HAS_PCH_LPT(dev))
6679 lpt_init_pch_refclk(dev);
6680 }
6681
6682 static int ironlake_get_refclk(struct drm_crtc *crtc)
6683 {
6684 struct drm_device *dev = crtc->dev;
6685 struct drm_i915_private *dev_priv = dev->dev_private;
6686 struct intel_encoder *encoder;
6687 int num_connectors = 0;
6688 bool is_lvds = false;
6689
6690 for_each_encoder_on_crtc(dev, crtc, encoder) {
6691 switch (encoder->type) {
6692 case INTEL_OUTPUT_LVDS:
6693 is_lvds = true;
6694 break;
6695 }
6696 num_connectors++;
6697 }
6698
6699 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6700 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6701 dev_priv->vbt.lvds_ssc_freq);
6702 return dev_priv->vbt.lvds_ssc_freq;
6703 }
6704
6705 return 120000;
6706 }
6707
6708 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6709 {
6710 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6711 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6712 int pipe = intel_crtc->pipe;
6713 uint32_t val;
6714
6715 val = 0;
6716
6717 switch (intel_crtc->config.pipe_bpp) {
6718 case 18:
6719 val |= PIPECONF_6BPC;
6720 break;
6721 case 24:
6722 val |= PIPECONF_8BPC;
6723 break;
6724 case 30:
6725 val |= PIPECONF_10BPC;
6726 break;
6727 case 36:
6728 val |= PIPECONF_12BPC;
6729 break;
6730 default:
6731 /* Case prevented by intel_choose_pipe_bpp_dither. */
6732 BUG();
6733 }
6734
6735 if (intel_crtc->config.dither)
6736 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6737
6738 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6739 val |= PIPECONF_INTERLACED_ILK;
6740 else
6741 val |= PIPECONF_PROGRESSIVE;
6742
6743 if (intel_crtc->config.limited_color_range)
6744 val |= PIPECONF_COLOR_RANGE_SELECT;
6745
6746 I915_WRITE(PIPECONF(pipe), val);
6747 POSTING_READ(PIPECONF(pipe));
6748 }
6749
6750 /*
6751 * Set up the pipe CSC unit.
6752 *
6753 * Currently only full range RGB to limited range RGB conversion
6754 * is supported, but eventually this should handle various
6755 * RGB<->YCbCr scenarios as well.
6756 */
6757 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6758 {
6759 struct drm_device *dev = crtc->dev;
6760 struct drm_i915_private *dev_priv = dev->dev_private;
6761 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6762 int pipe = intel_crtc->pipe;
6763 uint16_t coeff = 0x7800; /* 1.0 */
6764
6765 /*
6766 * TODO: Check what kind of values actually come out of the pipe
6767 * with these coeff/postoff values and adjust to get the best
6768 * accuracy. Perhaps we even need to take the bpc value into
6769 * consideration.
6770 */
6771
6772 if (intel_crtc->config.limited_color_range)
6773 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6774
6775 /*
6776 * GY/GU and RY/RU should be the other way around according
6777 * to BSpec, but reality doesn't agree. Just set them up in
6778 * a way that results in the correct picture.
6779 */
6780 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6781 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6782
6783 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6784 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6785
6786 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6787 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6788
6789 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6790 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6791 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6792
6793 if (INTEL_INFO(dev)->gen > 6) {
6794 uint16_t postoff = 0;
6795
6796 if (intel_crtc->config.limited_color_range)
6797 postoff = (16 * (1 << 12) / 255) & 0x1fff;
6798
6799 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6800 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6801 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6802
6803 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6804 } else {
6805 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6806
6807 if (intel_crtc->config.limited_color_range)
6808 mode |= CSC_BLACK_SCREEN_OFFSET;
6809
6810 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6811 }
6812 }
6813
6814 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6815 {
6816 struct drm_device *dev = crtc->dev;
6817 struct drm_i915_private *dev_priv = dev->dev_private;
6818 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6819 enum pipe pipe = intel_crtc->pipe;
6820 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6821 uint32_t val;
6822
6823 val = 0;
6824
6825 if (IS_HASWELL(dev) && intel_crtc->config.dither)
6826 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6827
6828 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6829 val |= PIPECONF_INTERLACED_ILK;
6830 else
6831 val |= PIPECONF_PROGRESSIVE;
6832
6833 I915_WRITE(PIPECONF(cpu_transcoder), val);
6834 POSTING_READ(PIPECONF(cpu_transcoder));
6835
6836 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6837 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6838
6839 if (IS_BROADWELL(dev)) {
6840 val = 0;
6841
6842 switch (intel_crtc->config.pipe_bpp) {
6843 case 18:
6844 val |= PIPEMISC_DITHER_6_BPC;
6845 break;
6846 case 24:
6847 val |= PIPEMISC_DITHER_8_BPC;
6848 break;
6849 case 30:
6850 val |= PIPEMISC_DITHER_10_BPC;
6851 break;
6852 case 36:
6853 val |= PIPEMISC_DITHER_12_BPC;
6854 break;
6855 default:
6856 /* Case prevented by pipe_config_set_bpp. */
6857 BUG();
6858 }
6859
6860 if (intel_crtc->config.dither)
6861 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6862
6863 I915_WRITE(PIPEMISC(pipe), val);
6864 }
6865 }
6866
6867 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6868 intel_clock_t *clock,
6869 bool *has_reduced_clock,
6870 intel_clock_t *reduced_clock)
6871 {
6872 struct drm_device *dev = crtc->dev;
6873 struct drm_i915_private *dev_priv = dev->dev_private;
6874 struct intel_encoder *intel_encoder;
6875 int refclk;
6876 const intel_limit_t *limit;
6877 bool ret, is_lvds = false;
6878
6879 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6880 switch (intel_encoder->type) {
6881 case INTEL_OUTPUT_LVDS:
6882 is_lvds = true;
6883 break;
6884 }
6885 }
6886
6887 refclk = ironlake_get_refclk(crtc);
6888
6889 /*
6890 * Returns a set of divisors for the desired target clock with the given
6891 * refclk, or FALSE. The returned values represent the clock equation:
6892 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6893 */
6894 limit = intel_limit(crtc, refclk);
6895 ret = dev_priv->display.find_dpll(limit, crtc,
6896 to_intel_crtc(crtc)->config.port_clock,
6897 refclk, NULL, clock);
6898 if (!ret)
6899 return false;
6900
6901 if (is_lvds && dev_priv->lvds_downclock_avail) {
6902 /*
6903 * Ensure we match the reduced clock's P to the target clock.
6904 * If the clocks don't match, we can't switch the display clock
6905 * by using the FP0/FP1. In such case we will disable the LVDS
6906 * downclock feature.
6907 */
6908 *has_reduced_clock =
6909 dev_priv->display.find_dpll(limit, crtc,
6910 dev_priv->lvds_downclock,
6911 refclk, clock,
6912 reduced_clock);
6913 }
6914
6915 return true;
6916 }
6917
6918 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6919 {
6920 /*
6921 * Account for spread spectrum to avoid
6922 * oversubscribing the link. Max center spread
6923 * is 2.5%; use 5% for safety's sake.
6924 */
6925 u32 bps = target_clock * bpp * 21 / 20;
6926 return DIV_ROUND_UP(bps, link_bw * 8);
6927 }
6928
6929 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6930 {
6931 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6932 }
6933
6934 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6935 u32 *fp,
6936 intel_clock_t *reduced_clock, u32 *fp2)
6937 {
6938 struct drm_crtc *crtc = &intel_crtc->base;
6939 struct drm_device *dev = crtc->dev;
6940 struct drm_i915_private *dev_priv = dev->dev_private;
6941 struct intel_encoder *intel_encoder;
6942 uint32_t dpll;
6943 int factor, num_connectors = 0;
6944 bool is_lvds = false, is_sdvo = false;
6945
6946 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6947 switch (intel_encoder->type) {
6948 case INTEL_OUTPUT_LVDS:
6949 is_lvds = true;
6950 break;
6951 case INTEL_OUTPUT_SDVO:
6952 case INTEL_OUTPUT_HDMI:
6953 is_sdvo = true;
6954 break;
6955 }
6956
6957 num_connectors++;
6958 }
6959
6960 /* Enable autotuning of the PLL clock (if permissible) */
6961 factor = 21;
6962 if (is_lvds) {
6963 if ((intel_panel_use_ssc(dev_priv) &&
6964 dev_priv->vbt.lvds_ssc_freq == 100000) ||
6965 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6966 factor = 25;
6967 } else if (intel_crtc->config.sdvo_tv_clock)
6968 factor = 20;
6969
6970 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6971 *fp |= FP_CB_TUNE;
6972
6973 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6974 *fp2 |= FP_CB_TUNE;
6975
6976 dpll = 0;
6977
6978 if (is_lvds)
6979 dpll |= DPLLB_MODE_LVDS;
6980 else
6981 dpll |= DPLLB_MODE_DAC_SERIAL;
6982
6983 dpll |= (intel_crtc->config.pixel_multiplier - 1)
6984 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6985
6986 if (is_sdvo)
6987 dpll |= DPLL_SDVO_HIGH_SPEED;
6988 if (intel_crtc->config.has_dp_encoder)
6989 dpll |= DPLL_SDVO_HIGH_SPEED;
6990
6991 /* compute bitmask from p1 value */
6992 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6993 /* also FPA1 */
6994 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6995
6996 switch (intel_crtc->config.dpll.p2) {
6997 case 5:
6998 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6999 break;
7000 case 7:
7001 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7002 break;
7003 case 10:
7004 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7005 break;
7006 case 14:
7007 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7008 break;
7009 }
7010
7011 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7012 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7013 else
7014 dpll |= PLL_REF_INPUT_DREFCLK;
7015
7016 return dpll | DPLL_VCO_ENABLE;
7017 }
7018
7019 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
7020 int x, int y,
7021 struct drm_framebuffer *fb)
7022 {
7023 struct drm_device *dev = crtc->dev;
7024 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7025 int num_connectors = 0;
7026 intel_clock_t clock, reduced_clock;
7027 u32 dpll = 0, fp = 0, fp2 = 0;
7028 bool ok, has_reduced_clock = false;
7029 bool is_lvds = false;
7030 struct intel_encoder *encoder;
7031 struct intel_shared_dpll *pll;
7032
7033 for_each_encoder_on_crtc(dev, crtc, encoder) {
7034 switch (encoder->type) {
7035 case INTEL_OUTPUT_LVDS:
7036 is_lvds = true;
7037 break;
7038 }
7039
7040 num_connectors++;
7041 }
7042
7043 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7044 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7045
7046 ok = ironlake_compute_clocks(crtc, &clock,
7047 &has_reduced_clock, &reduced_clock);
7048 if (!ok && !intel_crtc->config.clock_set) {
7049 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7050 return -EINVAL;
7051 }
7052 /* Compat-code for transition, will disappear. */
7053 if (!intel_crtc->config.clock_set) {
7054 intel_crtc->config.dpll.n = clock.n;
7055 intel_crtc->config.dpll.m1 = clock.m1;
7056 intel_crtc->config.dpll.m2 = clock.m2;
7057 intel_crtc->config.dpll.p1 = clock.p1;
7058 intel_crtc->config.dpll.p2 = clock.p2;
7059 }
7060
7061 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7062 if (intel_crtc->config.has_pch_encoder) {
7063 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
7064 if (has_reduced_clock)
7065 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7066
7067 dpll = ironlake_compute_dpll(intel_crtc,
7068 &fp, &reduced_clock,
7069 has_reduced_clock ? &fp2 : NULL);
7070
7071 intel_crtc->config.dpll_hw_state.dpll = dpll;
7072 intel_crtc->config.dpll_hw_state.fp0 = fp;
7073 if (has_reduced_clock)
7074 intel_crtc->config.dpll_hw_state.fp1 = fp2;
7075 else
7076 intel_crtc->config.dpll_hw_state.fp1 = fp;
7077
7078 pll = intel_get_shared_dpll(intel_crtc);
7079 if (pll == NULL) {
7080 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7081 pipe_name(intel_crtc->pipe));
7082 return -EINVAL;
7083 }
7084 } else
7085 intel_put_shared_dpll(intel_crtc);
7086
7087 if (is_lvds && has_reduced_clock && i915.powersave)
7088 intel_crtc->lowfreq_avail = true;
7089 else
7090 intel_crtc->lowfreq_avail = false;
7091
7092 return 0;
7093 }
7094
7095 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7096 struct intel_link_m_n *m_n)
7097 {
7098 struct drm_device *dev = crtc->base.dev;
7099 struct drm_i915_private *dev_priv = dev->dev_private;
7100 enum pipe pipe = crtc->pipe;
7101
7102 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7103 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7104 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7105 & ~TU_SIZE_MASK;
7106 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7107 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7108 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7109 }
7110
7111 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7112 enum transcoder transcoder,
7113 struct intel_link_m_n *m_n)
7114 {
7115 struct drm_device *dev = crtc->base.dev;
7116 struct drm_i915_private *dev_priv = dev->dev_private;
7117 enum pipe pipe = crtc->pipe;
7118
7119 if (INTEL_INFO(dev)->gen >= 5) {
7120 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7121 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7122 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7123 & ~TU_SIZE_MASK;
7124 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7125 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7126 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7127 } else {
7128 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7129 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7130 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7131 & ~TU_SIZE_MASK;
7132 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7133 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7134 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7135 }
7136 }
7137
7138 void intel_dp_get_m_n(struct intel_crtc *crtc,
7139 struct intel_crtc_config *pipe_config)
7140 {
7141 if (crtc->config.has_pch_encoder)
7142 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7143 else
7144 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7145 &pipe_config->dp_m_n);
7146 }
7147
7148 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7149 struct intel_crtc_config *pipe_config)
7150 {
7151 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7152 &pipe_config->fdi_m_n);
7153 }
7154
7155 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7156 struct intel_crtc_config *pipe_config)
7157 {
7158 struct drm_device *dev = crtc->base.dev;
7159 struct drm_i915_private *dev_priv = dev->dev_private;
7160 uint32_t tmp;
7161
7162 tmp = I915_READ(PF_CTL(crtc->pipe));
7163
7164 if (tmp & PF_ENABLE) {
7165 pipe_config->pch_pfit.enabled = true;
7166 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7167 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7168
7169 /* We currently do not free assignements of panel fitters on
7170 * ivb/hsw (since we don't use the higher upscaling modes which
7171 * differentiates them) so just WARN about this case for now. */
7172 if (IS_GEN7(dev)) {
7173 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7174 PF_PIPE_SEL_IVB(crtc->pipe));
7175 }
7176 }
7177 }
7178
7179 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7180 struct intel_plane_config *plane_config)
7181 {
7182 struct drm_device *dev = crtc->base.dev;
7183 struct drm_i915_private *dev_priv = dev->dev_private;
7184 u32 val, base, offset;
7185 int pipe = crtc->pipe, plane = crtc->plane;
7186 int fourcc, pixel_format;
7187 int aligned_height;
7188
7189 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7190 if (!crtc->base.primary->fb) {
7191 DRM_DEBUG_KMS("failed to alloc fb\n");
7192 return;
7193 }
7194
7195 val = I915_READ(DSPCNTR(plane));
7196
7197 if (INTEL_INFO(dev)->gen >= 4)
7198 if (val & DISPPLANE_TILED)
7199 plane_config->tiled = true;
7200
7201 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7202 fourcc = intel_format_to_fourcc(pixel_format);
7203 crtc->base.primary->fb->pixel_format = fourcc;
7204 crtc->base.primary->fb->bits_per_pixel =
7205 drm_format_plane_cpp(fourcc, 0) * 8;
7206
7207 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7208 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7209 offset = I915_READ(DSPOFFSET(plane));
7210 } else {
7211 if (plane_config->tiled)
7212 offset = I915_READ(DSPTILEOFF(plane));
7213 else
7214 offset = I915_READ(DSPLINOFF(plane));
7215 }
7216 plane_config->base = base;
7217
7218 val = I915_READ(PIPESRC(pipe));
7219 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7220 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7221
7222 val = I915_READ(DSPSTRIDE(pipe));
7223 crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
7224
7225 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7226 plane_config->tiled);
7227
7228 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7229 aligned_height);
7230
7231 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7232 pipe, plane, crtc->base.primary->fb->width,
7233 crtc->base.primary->fb->height,
7234 crtc->base.primary->fb->bits_per_pixel, base,
7235 crtc->base.primary->fb->pitches[0],
7236 plane_config->size);
7237 }
7238
7239 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7240 struct intel_crtc_config *pipe_config)
7241 {
7242 struct drm_device *dev = crtc->base.dev;
7243 struct drm_i915_private *dev_priv = dev->dev_private;
7244 uint32_t tmp;
7245
7246 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7247 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7248
7249 tmp = I915_READ(PIPECONF(crtc->pipe));
7250 if (!(tmp & PIPECONF_ENABLE))
7251 return false;
7252
7253 switch (tmp & PIPECONF_BPC_MASK) {
7254 case PIPECONF_6BPC:
7255 pipe_config->pipe_bpp = 18;
7256 break;
7257 case PIPECONF_8BPC:
7258 pipe_config->pipe_bpp = 24;
7259 break;
7260 case PIPECONF_10BPC:
7261 pipe_config->pipe_bpp = 30;
7262 break;
7263 case PIPECONF_12BPC:
7264 pipe_config->pipe_bpp = 36;
7265 break;
7266 default:
7267 break;
7268 }
7269
7270 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7271 pipe_config->limited_color_range = true;
7272
7273 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7274 struct intel_shared_dpll *pll;
7275
7276 pipe_config->has_pch_encoder = true;
7277
7278 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7279 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7280 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7281
7282 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7283
7284 if (HAS_PCH_IBX(dev_priv->dev)) {
7285 pipe_config->shared_dpll =
7286 (enum intel_dpll_id) crtc->pipe;
7287 } else {
7288 tmp = I915_READ(PCH_DPLL_SEL);
7289 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7290 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7291 else
7292 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7293 }
7294
7295 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7296
7297 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7298 &pipe_config->dpll_hw_state));
7299
7300 tmp = pipe_config->dpll_hw_state.dpll;
7301 pipe_config->pixel_multiplier =
7302 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7303 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7304
7305 ironlake_pch_clock_get(crtc, pipe_config);
7306 } else {
7307 pipe_config->pixel_multiplier = 1;
7308 }
7309
7310 intel_get_pipe_timings(crtc, pipe_config);
7311
7312 ironlake_get_pfit_config(crtc, pipe_config);
7313
7314 return true;
7315 }
7316
7317 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7318 {
7319 struct drm_device *dev = dev_priv->dev;
7320 struct intel_crtc *crtc;
7321
7322 for_each_intel_crtc(dev, crtc)
7323 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7324 pipe_name(crtc->pipe));
7325
7326 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7327 WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7328 WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7329 WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7330 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7331 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7332 "CPU PWM1 enabled\n");
7333 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7334 "CPU PWM2 enabled\n");
7335 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7336 "PCH PWM1 enabled\n");
7337 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7338 "Utility pin enabled\n");
7339 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7340
7341 /*
7342 * In theory we can still leave IRQs enabled, as long as only the HPD
7343 * interrupts remain enabled. We used to check for that, but since it's
7344 * gen-specific and since we only disable LCPLL after we fully disable
7345 * the interrupts, the check below should be enough.
7346 */
7347 WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n");
7348 }
7349
7350 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7351 {
7352 struct drm_device *dev = dev_priv->dev;
7353
7354 if (IS_HASWELL(dev))
7355 return I915_READ(D_COMP_HSW);
7356 else
7357 return I915_READ(D_COMP_BDW);
7358 }
7359
7360 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7361 {
7362 struct drm_device *dev = dev_priv->dev;
7363
7364 if (IS_HASWELL(dev)) {
7365 mutex_lock(&dev_priv->rps.hw_lock);
7366 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7367 val))
7368 DRM_ERROR("Failed to write to D_COMP\n");
7369 mutex_unlock(&dev_priv->rps.hw_lock);
7370 } else {
7371 I915_WRITE(D_COMP_BDW, val);
7372 POSTING_READ(D_COMP_BDW);
7373 }
7374 }
7375
7376 /*
7377 * This function implements pieces of two sequences from BSpec:
7378 * - Sequence for display software to disable LCPLL
7379 * - Sequence for display software to allow package C8+
7380 * The steps implemented here are just the steps that actually touch the LCPLL
7381 * register. Callers should take care of disabling all the display engine
7382 * functions, doing the mode unset, fixing interrupts, etc.
7383 */
7384 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7385 bool switch_to_fclk, bool allow_power_down)
7386 {
7387 uint32_t val;
7388
7389 assert_can_disable_lcpll(dev_priv);
7390
7391 val = I915_READ(LCPLL_CTL);
7392
7393 if (switch_to_fclk) {
7394 val |= LCPLL_CD_SOURCE_FCLK;
7395 I915_WRITE(LCPLL_CTL, val);
7396
7397 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7398 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7399 DRM_ERROR("Switching to FCLK failed\n");
7400
7401 val = I915_READ(LCPLL_CTL);
7402 }
7403
7404 val |= LCPLL_PLL_DISABLE;
7405 I915_WRITE(LCPLL_CTL, val);
7406 POSTING_READ(LCPLL_CTL);
7407
7408 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7409 DRM_ERROR("LCPLL still locked\n");
7410
7411 val = hsw_read_dcomp(dev_priv);
7412 val |= D_COMP_COMP_DISABLE;
7413 hsw_write_dcomp(dev_priv, val);
7414 ndelay(100);
7415
7416 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7417 1))
7418 DRM_ERROR("D_COMP RCOMP still in progress\n");
7419
7420 if (allow_power_down) {
7421 val = I915_READ(LCPLL_CTL);
7422 val |= LCPLL_POWER_DOWN_ALLOW;
7423 I915_WRITE(LCPLL_CTL, val);
7424 POSTING_READ(LCPLL_CTL);
7425 }
7426 }
7427
7428 /*
7429 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7430 * source.
7431 */
7432 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7433 {
7434 uint32_t val;
7435 unsigned long irqflags;
7436
7437 val = I915_READ(LCPLL_CTL);
7438
7439 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7440 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7441 return;
7442
7443 /*
7444 * Make sure we're not on PC8 state before disabling PC8, otherwise
7445 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7446 *
7447 * The other problem is that hsw_restore_lcpll() is called as part of
7448 * the runtime PM resume sequence, so we can't just call
7449 * gen6_gt_force_wake_get() because that function calls
7450 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7451 * while we are on the resume sequence. So to solve this problem we have
7452 * to call special forcewake code that doesn't touch runtime PM and
7453 * doesn't enable the forcewake delayed work.
7454 */
7455 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7456 if (dev_priv->uncore.forcewake_count++ == 0)
7457 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7458 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7459
7460 if (val & LCPLL_POWER_DOWN_ALLOW) {
7461 val &= ~LCPLL_POWER_DOWN_ALLOW;
7462 I915_WRITE(LCPLL_CTL, val);
7463 POSTING_READ(LCPLL_CTL);
7464 }
7465
7466 val = hsw_read_dcomp(dev_priv);
7467 val |= D_COMP_COMP_FORCE;
7468 val &= ~D_COMP_COMP_DISABLE;
7469 hsw_write_dcomp(dev_priv, val);
7470
7471 val = I915_READ(LCPLL_CTL);
7472 val &= ~LCPLL_PLL_DISABLE;
7473 I915_WRITE(LCPLL_CTL, val);
7474
7475 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7476 DRM_ERROR("LCPLL not locked yet\n");
7477
7478 if (val & LCPLL_CD_SOURCE_FCLK) {
7479 val = I915_READ(LCPLL_CTL);
7480 val &= ~LCPLL_CD_SOURCE_FCLK;
7481 I915_WRITE(LCPLL_CTL, val);
7482
7483 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7484 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7485 DRM_ERROR("Switching back to LCPLL failed\n");
7486 }
7487
7488 /* See the big comment above. */
7489 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7490 if (--dev_priv->uncore.forcewake_count == 0)
7491 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7492 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7493 }
7494
7495 /*
7496 * Package states C8 and deeper are really deep PC states that can only be
7497 * reached when all the devices on the system allow it, so even if the graphics
7498 * device allows PC8+, it doesn't mean the system will actually get to these
7499 * states. Our driver only allows PC8+ when going into runtime PM.
7500 *
7501 * The requirements for PC8+ are that all the outputs are disabled, the power
7502 * well is disabled and most interrupts are disabled, and these are also
7503 * requirements for runtime PM. When these conditions are met, we manually do
7504 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7505 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7506 * hang the machine.
7507 *
7508 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7509 * the state of some registers, so when we come back from PC8+ we need to
7510 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7511 * need to take care of the registers kept by RC6. Notice that this happens even
7512 * if we don't put the device in PCI D3 state (which is what currently happens
7513 * because of the runtime PM support).
7514 *
7515 * For more, read "Display Sequences for Package C8" on the hardware
7516 * documentation.
7517 */
7518 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7519 {
7520 struct drm_device *dev = dev_priv->dev;
7521 uint32_t val;
7522
7523 DRM_DEBUG_KMS("Enabling package C8+\n");
7524
7525 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7526 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7527 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7528 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7529 }
7530
7531 lpt_disable_clkout_dp(dev);
7532 hsw_disable_lcpll(dev_priv, true, true);
7533 }
7534
7535 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7536 {
7537 struct drm_device *dev = dev_priv->dev;
7538 uint32_t val;
7539
7540 DRM_DEBUG_KMS("Disabling package C8+\n");
7541
7542 hsw_restore_lcpll(dev_priv);
7543 lpt_init_pch_refclk(dev);
7544
7545 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7546 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7547 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7548 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7549 }
7550
7551 intel_prepare_ddi(dev);
7552 }
7553
7554 static void snb_modeset_global_resources(struct drm_device *dev)
7555 {
7556 modeset_update_crtc_power_domains(dev);
7557 }
7558
7559 static void haswell_modeset_global_resources(struct drm_device *dev)
7560 {
7561 modeset_update_crtc_power_domains(dev);
7562 }
7563
7564 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7565 int x, int y,
7566 struct drm_framebuffer *fb)
7567 {
7568 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7569
7570 if (!intel_ddi_pll_select(intel_crtc))
7571 return -EINVAL;
7572
7573 if (intel_crtc_to_shared_dpll(intel_crtc))
7574 intel_enable_shared_dpll(intel_crtc);
7575
7576 intel_crtc->lowfreq_avail = false;
7577
7578 return 0;
7579 }
7580
7581 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
7582 struct intel_crtc_config *pipe_config)
7583 {
7584 struct drm_device *dev = crtc->base.dev;
7585 struct drm_i915_private *dev_priv = dev->dev_private;
7586 struct intel_shared_dpll *pll;
7587 enum port port;
7588 uint32_t tmp;
7589
7590 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7591
7592 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
7593
7594 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
7595
7596 switch (pipe_config->ddi_pll_sel) {
7597 case PORT_CLK_SEL_WRPLL1:
7598 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7599 break;
7600 case PORT_CLK_SEL_WRPLL2:
7601 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7602 break;
7603 }
7604
7605 if (pipe_config->shared_dpll >= 0) {
7606 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7607
7608 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7609 &pipe_config->dpll_hw_state));
7610 }
7611
7612 /*
7613 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7614 * DDI E. So just check whether this pipe is wired to DDI E and whether
7615 * the PCH transcoder is on.
7616 */
7617 if ((port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7618 pipe_config->has_pch_encoder = true;
7619
7620 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7621 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7622 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7623
7624 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7625 }
7626 }
7627
7628 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7629 struct intel_crtc_config *pipe_config)
7630 {
7631 struct drm_device *dev = crtc->base.dev;
7632 struct drm_i915_private *dev_priv = dev->dev_private;
7633 enum intel_display_power_domain pfit_domain;
7634 uint32_t tmp;
7635
7636 if (!intel_display_power_enabled(dev_priv,
7637 POWER_DOMAIN_PIPE(crtc->pipe)))
7638 return false;
7639
7640 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7641 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7642
7643 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7644 if (tmp & TRANS_DDI_FUNC_ENABLE) {
7645 enum pipe trans_edp_pipe;
7646 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7647 default:
7648 WARN(1, "unknown pipe linked to edp transcoder\n");
7649 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7650 case TRANS_DDI_EDP_INPUT_A_ON:
7651 trans_edp_pipe = PIPE_A;
7652 break;
7653 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7654 trans_edp_pipe = PIPE_B;
7655 break;
7656 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7657 trans_edp_pipe = PIPE_C;
7658 break;
7659 }
7660
7661 if (trans_edp_pipe == crtc->pipe)
7662 pipe_config->cpu_transcoder = TRANSCODER_EDP;
7663 }
7664
7665 if (!intel_display_power_enabled(dev_priv,
7666 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7667 return false;
7668
7669 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7670 if (!(tmp & PIPECONF_ENABLE))
7671 return false;
7672
7673 haswell_get_ddi_port_state(crtc, pipe_config);
7674
7675 intel_get_pipe_timings(crtc, pipe_config);
7676
7677 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7678 if (intel_display_power_enabled(dev_priv, pfit_domain))
7679 ironlake_get_pfit_config(crtc, pipe_config);
7680
7681 if (IS_HASWELL(dev))
7682 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7683 (I915_READ(IPS_CTL) & IPS_ENABLE);
7684
7685 pipe_config->pixel_multiplier = 1;
7686
7687 return true;
7688 }
7689
7690 static struct {
7691 int clock;
7692 u32 config;
7693 } hdmi_audio_clock[] = {
7694 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7695 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7696 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7697 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7698 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7699 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7700 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7701 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7702 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7703 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7704 };
7705
7706 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7707 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7708 {
7709 int i;
7710
7711 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7712 if (mode->clock == hdmi_audio_clock[i].clock)
7713 break;
7714 }
7715
7716 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7717 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7718 i = 1;
7719 }
7720
7721 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7722 hdmi_audio_clock[i].clock,
7723 hdmi_audio_clock[i].config);
7724
7725 return hdmi_audio_clock[i].config;
7726 }
7727
7728 static bool intel_eld_uptodate(struct drm_connector *connector,
7729 int reg_eldv, uint32_t bits_eldv,
7730 int reg_elda, uint32_t bits_elda,
7731 int reg_edid)
7732 {
7733 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7734 uint8_t *eld = connector->eld;
7735 uint32_t i;
7736
7737 i = I915_READ(reg_eldv);
7738 i &= bits_eldv;
7739
7740 if (!eld[0])
7741 return !i;
7742
7743 if (!i)
7744 return false;
7745
7746 i = I915_READ(reg_elda);
7747 i &= ~bits_elda;
7748 I915_WRITE(reg_elda, i);
7749
7750 for (i = 0; i < eld[2]; i++)
7751 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7752 return false;
7753
7754 return true;
7755 }
7756
7757 static void g4x_write_eld(struct drm_connector *connector,
7758 struct drm_crtc *crtc,
7759 struct drm_display_mode *mode)
7760 {
7761 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7762 uint8_t *eld = connector->eld;
7763 uint32_t eldv;
7764 uint32_t len;
7765 uint32_t i;
7766
7767 i = I915_READ(G4X_AUD_VID_DID);
7768
7769 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7770 eldv = G4X_ELDV_DEVCL_DEVBLC;
7771 else
7772 eldv = G4X_ELDV_DEVCTG;
7773
7774 if (intel_eld_uptodate(connector,
7775 G4X_AUD_CNTL_ST, eldv,
7776 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7777 G4X_HDMIW_HDMIEDID))
7778 return;
7779
7780 i = I915_READ(G4X_AUD_CNTL_ST);
7781 i &= ~(eldv | G4X_ELD_ADDR);
7782 len = (i >> 9) & 0x1f; /* ELD buffer size */
7783 I915_WRITE(G4X_AUD_CNTL_ST, i);
7784
7785 if (!eld[0])
7786 return;
7787
7788 len = min_t(uint8_t, eld[2], len);
7789 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7790 for (i = 0; i < len; i++)
7791 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7792
7793 i = I915_READ(G4X_AUD_CNTL_ST);
7794 i |= eldv;
7795 I915_WRITE(G4X_AUD_CNTL_ST, i);
7796 }
7797
7798 static void haswell_write_eld(struct drm_connector *connector,
7799 struct drm_crtc *crtc,
7800 struct drm_display_mode *mode)
7801 {
7802 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7803 uint8_t *eld = connector->eld;
7804 uint32_t eldv;
7805 uint32_t i;
7806 int len;
7807 int pipe = to_intel_crtc(crtc)->pipe;
7808 int tmp;
7809
7810 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7811 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7812 int aud_config = HSW_AUD_CFG(pipe);
7813 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7814
7815 /* Audio output enable */
7816 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7817 tmp = I915_READ(aud_cntrl_st2);
7818 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7819 I915_WRITE(aud_cntrl_st2, tmp);
7820 POSTING_READ(aud_cntrl_st2);
7821
7822 assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
7823
7824 /* Set ELD valid state */
7825 tmp = I915_READ(aud_cntrl_st2);
7826 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7827 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7828 I915_WRITE(aud_cntrl_st2, tmp);
7829 tmp = I915_READ(aud_cntrl_st2);
7830 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7831
7832 /* Enable HDMI mode */
7833 tmp = I915_READ(aud_config);
7834 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7835 /* clear N_programing_enable and N_value_index */
7836 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7837 I915_WRITE(aud_config, tmp);
7838
7839 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7840
7841 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7842
7843 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7844 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7845 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7846 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7847 } else {
7848 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7849 }
7850
7851 if (intel_eld_uptodate(connector,
7852 aud_cntrl_st2, eldv,
7853 aud_cntl_st, IBX_ELD_ADDRESS,
7854 hdmiw_hdmiedid))
7855 return;
7856
7857 i = I915_READ(aud_cntrl_st2);
7858 i &= ~eldv;
7859 I915_WRITE(aud_cntrl_st2, i);
7860
7861 if (!eld[0])
7862 return;
7863
7864 i = I915_READ(aud_cntl_st);
7865 i &= ~IBX_ELD_ADDRESS;
7866 I915_WRITE(aud_cntl_st, i);
7867 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
7868 DRM_DEBUG_DRIVER("port num:%d\n", i);
7869
7870 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7871 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7872 for (i = 0; i < len; i++)
7873 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7874
7875 i = I915_READ(aud_cntrl_st2);
7876 i |= eldv;
7877 I915_WRITE(aud_cntrl_st2, i);
7878
7879 }
7880
7881 static void ironlake_write_eld(struct drm_connector *connector,
7882 struct drm_crtc *crtc,
7883 struct drm_display_mode *mode)
7884 {
7885 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7886 uint8_t *eld = connector->eld;
7887 uint32_t eldv;
7888 uint32_t i;
7889 int len;
7890 int hdmiw_hdmiedid;
7891 int aud_config;
7892 int aud_cntl_st;
7893 int aud_cntrl_st2;
7894 int pipe = to_intel_crtc(crtc)->pipe;
7895
7896 if (HAS_PCH_IBX(connector->dev)) {
7897 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7898 aud_config = IBX_AUD_CFG(pipe);
7899 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7900 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7901 } else if (IS_VALLEYVIEW(connector->dev)) {
7902 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7903 aud_config = VLV_AUD_CFG(pipe);
7904 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7905 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7906 } else {
7907 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7908 aud_config = CPT_AUD_CFG(pipe);
7909 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7910 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7911 }
7912
7913 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7914
7915 if (IS_VALLEYVIEW(connector->dev)) {
7916 struct intel_encoder *intel_encoder;
7917 struct intel_digital_port *intel_dig_port;
7918
7919 intel_encoder = intel_attached_encoder(connector);
7920 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7921 i = intel_dig_port->port;
7922 } else {
7923 i = I915_READ(aud_cntl_st);
7924 i = (i >> 29) & DIP_PORT_SEL_MASK;
7925 /* DIP_Port_Select, 0x1 = PortB */
7926 }
7927
7928 if (!i) {
7929 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7930 /* operate blindly on all ports */
7931 eldv = IBX_ELD_VALIDB;
7932 eldv |= IBX_ELD_VALIDB << 4;
7933 eldv |= IBX_ELD_VALIDB << 8;
7934 } else {
7935 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7936 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7937 }
7938
7939 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7940 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7941 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7942 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7943 } else {
7944 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7945 }
7946
7947 if (intel_eld_uptodate(connector,
7948 aud_cntrl_st2, eldv,
7949 aud_cntl_st, IBX_ELD_ADDRESS,
7950 hdmiw_hdmiedid))
7951 return;
7952
7953 i = I915_READ(aud_cntrl_st2);
7954 i &= ~eldv;
7955 I915_WRITE(aud_cntrl_st2, i);
7956
7957 if (!eld[0])
7958 return;
7959
7960 i = I915_READ(aud_cntl_st);
7961 i &= ~IBX_ELD_ADDRESS;
7962 I915_WRITE(aud_cntl_st, i);
7963
7964 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7965 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7966 for (i = 0; i < len; i++)
7967 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7968
7969 i = I915_READ(aud_cntrl_st2);
7970 i |= eldv;
7971 I915_WRITE(aud_cntrl_st2, i);
7972 }
7973
7974 void intel_write_eld(struct drm_encoder *encoder,
7975 struct drm_display_mode *mode)
7976 {
7977 struct drm_crtc *crtc = encoder->crtc;
7978 struct drm_connector *connector;
7979 struct drm_device *dev = encoder->dev;
7980 struct drm_i915_private *dev_priv = dev->dev_private;
7981
7982 connector = drm_select_eld(encoder, mode);
7983 if (!connector)
7984 return;
7985
7986 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7987 connector->base.id,
7988 connector->name,
7989 connector->encoder->base.id,
7990 connector->encoder->name);
7991
7992 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7993
7994 if (dev_priv->display.write_eld)
7995 dev_priv->display.write_eld(connector, crtc, mode);
7996 }
7997
7998 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7999 {
8000 struct drm_device *dev = crtc->dev;
8001 struct drm_i915_private *dev_priv = dev->dev_private;
8002 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8003 uint32_t cntl;
8004
8005 if (base != intel_crtc->cursor_base) {
8006 /* On these chipsets we can only modify the base whilst
8007 * the cursor is disabled.
8008 */
8009 if (intel_crtc->cursor_cntl) {
8010 I915_WRITE(_CURACNTR, 0);
8011 POSTING_READ(_CURACNTR);
8012 intel_crtc->cursor_cntl = 0;
8013 }
8014
8015 I915_WRITE(_CURABASE, base);
8016 POSTING_READ(_CURABASE);
8017 }
8018
8019 /* XXX width must be 64, stride 256 => 0x00 << 28 */
8020 cntl = 0;
8021 if (base)
8022 cntl = (CURSOR_ENABLE |
8023 CURSOR_GAMMA_ENABLE |
8024 CURSOR_FORMAT_ARGB);
8025 if (intel_crtc->cursor_cntl != cntl) {
8026 I915_WRITE(_CURACNTR, cntl);
8027 POSTING_READ(_CURACNTR);
8028 intel_crtc->cursor_cntl = cntl;
8029 }
8030 }
8031
8032 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8033 {
8034 struct drm_device *dev = crtc->dev;
8035 struct drm_i915_private *dev_priv = dev->dev_private;
8036 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8037 int pipe = intel_crtc->pipe;
8038 uint32_t cntl;
8039
8040 cntl = 0;
8041 if (base) {
8042 cntl = MCURSOR_GAMMA_ENABLE;
8043 switch (intel_crtc->cursor_width) {
8044 case 64:
8045 cntl |= CURSOR_MODE_64_ARGB_AX;
8046 break;
8047 case 128:
8048 cntl |= CURSOR_MODE_128_ARGB_AX;
8049 break;
8050 case 256:
8051 cntl |= CURSOR_MODE_256_ARGB_AX;
8052 break;
8053 default:
8054 WARN_ON(1);
8055 return;
8056 }
8057 cntl |= pipe << 28; /* Connect to correct pipe */
8058 }
8059 if (intel_crtc->cursor_cntl != cntl) {
8060 I915_WRITE(CURCNTR(pipe), cntl);
8061 POSTING_READ(CURCNTR(pipe));
8062 intel_crtc->cursor_cntl = cntl;
8063 }
8064
8065 /* and commit changes on next vblank */
8066 I915_WRITE(CURBASE(pipe), base);
8067 POSTING_READ(CURBASE(pipe));
8068 }
8069
8070 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
8071 {
8072 struct drm_device *dev = crtc->dev;
8073 struct drm_i915_private *dev_priv = dev->dev_private;
8074 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8075 int pipe = intel_crtc->pipe;
8076 uint32_t cntl;
8077
8078 cntl = 0;
8079 if (base) {
8080 cntl = MCURSOR_GAMMA_ENABLE;
8081 switch (intel_crtc->cursor_width) {
8082 case 64:
8083 cntl |= CURSOR_MODE_64_ARGB_AX;
8084 break;
8085 case 128:
8086 cntl |= CURSOR_MODE_128_ARGB_AX;
8087 break;
8088 case 256:
8089 cntl |= CURSOR_MODE_256_ARGB_AX;
8090 break;
8091 default:
8092 WARN_ON(1);
8093 return;
8094 }
8095 }
8096 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8097 cntl |= CURSOR_PIPE_CSC_ENABLE;
8098
8099 if (intel_crtc->cursor_cntl != cntl) {
8100 I915_WRITE(CURCNTR(pipe), cntl);
8101 POSTING_READ(CURCNTR(pipe));
8102 intel_crtc->cursor_cntl = cntl;
8103 }
8104
8105 /* and commit changes on next vblank */
8106 I915_WRITE(CURBASE(pipe), base);
8107 POSTING_READ(CURBASE(pipe));
8108 }
8109
8110 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8111 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8112 bool on)
8113 {
8114 struct drm_device *dev = crtc->dev;
8115 struct drm_i915_private *dev_priv = dev->dev_private;
8116 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8117 int pipe = intel_crtc->pipe;
8118 int x = crtc->cursor_x;
8119 int y = crtc->cursor_y;
8120 u32 base = 0, pos = 0;
8121
8122 if (on)
8123 base = intel_crtc->cursor_addr;
8124
8125 if (x >= intel_crtc->config.pipe_src_w)
8126 base = 0;
8127
8128 if (y >= intel_crtc->config.pipe_src_h)
8129 base = 0;
8130
8131 if (x < 0) {
8132 if (x + intel_crtc->cursor_width <= 0)
8133 base = 0;
8134
8135 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8136 x = -x;
8137 }
8138 pos |= x << CURSOR_X_SHIFT;
8139
8140 if (y < 0) {
8141 if (y + intel_crtc->cursor_height <= 0)
8142 base = 0;
8143
8144 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8145 y = -y;
8146 }
8147 pos |= y << CURSOR_Y_SHIFT;
8148
8149 if (base == 0 && intel_crtc->cursor_base == 0)
8150 return;
8151
8152 I915_WRITE(CURPOS(pipe), pos);
8153
8154 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev))
8155 ivb_update_cursor(crtc, base);
8156 else if (IS_845G(dev) || IS_I865G(dev))
8157 i845_update_cursor(crtc, base);
8158 else
8159 i9xx_update_cursor(crtc, base);
8160 intel_crtc->cursor_base = base;
8161 }
8162
8163 /*
8164 * intel_crtc_cursor_set_obj - Set cursor to specified GEM object
8165 *
8166 * Note that the object's reference will be consumed if the update fails. If
8167 * the update succeeds, the reference of the old object (if any) will be
8168 * consumed.
8169 */
8170 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8171 struct drm_i915_gem_object *obj,
8172 uint32_t width, uint32_t height)
8173 {
8174 struct drm_device *dev = crtc->dev;
8175 struct drm_i915_private *dev_priv = dev->dev_private;
8176 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8177 enum pipe pipe = intel_crtc->pipe;
8178 unsigned old_width;
8179 uint32_t addr;
8180 int ret;
8181
8182 /* if we want to turn off the cursor ignore width and height */
8183 if (!obj) {
8184 DRM_DEBUG_KMS("cursor off\n");
8185 addr = 0;
8186 obj = NULL;
8187 mutex_lock(&dev->struct_mutex);
8188 goto finish;
8189 }
8190
8191 /* Check for which cursor types we support */
8192 if (!((width == 64 && height == 64) ||
8193 (width == 128 && height == 128 && !IS_GEN2(dev)) ||
8194 (width == 256 && height == 256 && !IS_GEN2(dev)))) {
8195 DRM_DEBUG("Cursor dimension not supported\n");
8196 return -EINVAL;
8197 }
8198
8199 if (obj->base.size < width * height * 4) {
8200 DRM_DEBUG_KMS("buffer is too small\n");
8201 ret = -ENOMEM;
8202 goto fail;
8203 }
8204
8205 /* we only need to pin inside GTT if cursor is non-phy */
8206 mutex_lock(&dev->struct_mutex);
8207 if (!INTEL_INFO(dev)->cursor_needs_physical) {
8208 unsigned alignment;
8209
8210 if (obj->tiling_mode) {
8211 DRM_DEBUG_KMS("cursor cannot be tiled\n");
8212 ret = -EINVAL;
8213 goto fail_locked;
8214 }
8215
8216 /* Note that the w/a also requires 2 PTE of padding following
8217 * the bo. We currently fill all unused PTE with the shadow
8218 * page and so we should always have valid PTE following the
8219 * cursor preventing the VT-d warning.
8220 */
8221 alignment = 0;
8222 if (need_vtd_wa(dev))
8223 alignment = 64*1024;
8224
8225 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8226 if (ret) {
8227 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8228 goto fail_locked;
8229 }
8230
8231 ret = i915_gem_object_put_fence(obj);
8232 if (ret) {
8233 DRM_DEBUG_KMS("failed to release fence for cursor");
8234 goto fail_unpin;
8235 }
8236
8237 addr = i915_gem_obj_ggtt_offset(obj);
8238 } else {
8239 int align = IS_I830(dev) ? 16 * 1024 : 256;
8240 ret = i915_gem_object_attach_phys(obj, align);
8241 if (ret) {
8242 DRM_DEBUG_KMS("failed to attach phys object\n");
8243 goto fail_locked;
8244 }
8245 addr = obj->phys_handle->busaddr;
8246 }
8247
8248 if (IS_GEN2(dev))
8249 I915_WRITE(CURSIZE, (height << 12) | width);
8250
8251 finish:
8252 if (intel_crtc->cursor_bo) {
8253 if (!INTEL_INFO(dev)->cursor_needs_physical)
8254 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8255 }
8256
8257 i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8258 INTEL_FRONTBUFFER_CURSOR(pipe));
8259 mutex_unlock(&dev->struct_mutex);
8260
8261 old_width = intel_crtc->cursor_width;
8262
8263 intel_crtc->cursor_addr = addr;
8264 intel_crtc->cursor_bo = obj;
8265 intel_crtc->cursor_width = width;
8266 intel_crtc->cursor_height = height;
8267
8268 if (intel_crtc->active) {
8269 if (old_width != width)
8270 intel_update_watermarks(crtc);
8271 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8272 }
8273
8274 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8275
8276 return 0;
8277 fail_unpin:
8278 i915_gem_object_unpin_from_display_plane(obj);
8279 fail_locked:
8280 mutex_unlock(&dev->struct_mutex);
8281 fail:
8282 drm_gem_object_unreference_unlocked(&obj->base);
8283 return ret;
8284 }
8285
8286 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8287 u16 *blue, uint32_t start, uint32_t size)
8288 {
8289 int end = (start + size > 256) ? 256 : start + size, i;
8290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8291
8292 for (i = start; i < end; i++) {
8293 intel_crtc->lut_r[i] = red[i] >> 8;
8294 intel_crtc->lut_g[i] = green[i] >> 8;
8295 intel_crtc->lut_b[i] = blue[i] >> 8;
8296 }
8297
8298 intel_crtc_load_lut(crtc);
8299 }
8300
8301 /* VESA 640x480x72Hz mode to set on the pipe */
8302 static struct drm_display_mode load_detect_mode = {
8303 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8304 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8305 };
8306
8307 struct drm_framebuffer *
8308 __intel_framebuffer_create(struct drm_device *dev,
8309 struct drm_mode_fb_cmd2 *mode_cmd,
8310 struct drm_i915_gem_object *obj)
8311 {
8312 struct intel_framebuffer *intel_fb;
8313 int ret;
8314
8315 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8316 if (!intel_fb) {
8317 drm_gem_object_unreference_unlocked(&obj->base);
8318 return ERR_PTR(-ENOMEM);
8319 }
8320
8321 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8322 if (ret)
8323 goto err;
8324
8325 return &intel_fb->base;
8326 err:
8327 drm_gem_object_unreference_unlocked(&obj->base);
8328 kfree(intel_fb);
8329
8330 return ERR_PTR(ret);
8331 }
8332
8333 static struct drm_framebuffer *
8334 intel_framebuffer_create(struct drm_device *dev,
8335 struct drm_mode_fb_cmd2 *mode_cmd,
8336 struct drm_i915_gem_object *obj)
8337 {
8338 struct drm_framebuffer *fb;
8339 int ret;
8340
8341 ret = i915_mutex_lock_interruptible(dev);
8342 if (ret)
8343 return ERR_PTR(ret);
8344 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8345 mutex_unlock(&dev->struct_mutex);
8346
8347 return fb;
8348 }
8349
8350 static u32
8351 intel_framebuffer_pitch_for_width(int width, int bpp)
8352 {
8353 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8354 return ALIGN(pitch, 64);
8355 }
8356
8357 static u32
8358 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8359 {
8360 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8361 return PAGE_ALIGN(pitch * mode->vdisplay);
8362 }
8363
8364 static struct drm_framebuffer *
8365 intel_framebuffer_create_for_mode(struct drm_device *dev,
8366 struct drm_display_mode *mode,
8367 int depth, int bpp)
8368 {
8369 struct drm_i915_gem_object *obj;
8370 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8371
8372 obj = i915_gem_alloc_object(dev,
8373 intel_framebuffer_size_for_mode(mode, bpp));
8374 if (obj == NULL)
8375 return ERR_PTR(-ENOMEM);
8376
8377 mode_cmd.width = mode->hdisplay;
8378 mode_cmd.height = mode->vdisplay;
8379 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8380 bpp);
8381 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8382
8383 return intel_framebuffer_create(dev, &mode_cmd, obj);
8384 }
8385
8386 static struct drm_framebuffer *
8387 mode_fits_in_fbdev(struct drm_device *dev,
8388 struct drm_display_mode *mode)
8389 {
8390 #ifdef CONFIG_DRM_I915_FBDEV
8391 struct drm_i915_private *dev_priv = dev->dev_private;
8392 struct drm_i915_gem_object *obj;
8393 struct drm_framebuffer *fb;
8394
8395 if (!dev_priv->fbdev)
8396 return NULL;
8397
8398 if (!dev_priv->fbdev->fb)
8399 return NULL;
8400
8401 obj = dev_priv->fbdev->fb->obj;
8402 BUG_ON(!obj);
8403
8404 fb = &dev_priv->fbdev->fb->base;
8405 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8406 fb->bits_per_pixel))
8407 return NULL;
8408
8409 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8410 return NULL;
8411
8412 return fb;
8413 #else
8414 return NULL;
8415 #endif
8416 }
8417
8418 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8419 struct drm_display_mode *mode,
8420 struct intel_load_detect_pipe *old,
8421 struct drm_modeset_acquire_ctx *ctx)
8422 {
8423 struct intel_crtc *intel_crtc;
8424 struct intel_encoder *intel_encoder =
8425 intel_attached_encoder(connector);
8426 struct drm_crtc *possible_crtc;
8427 struct drm_encoder *encoder = &intel_encoder->base;
8428 struct drm_crtc *crtc = NULL;
8429 struct drm_device *dev = encoder->dev;
8430 struct drm_framebuffer *fb;
8431 struct drm_mode_config *config = &dev->mode_config;
8432 int ret, i = -1;
8433
8434 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8435 connector->base.id, connector->name,
8436 encoder->base.id, encoder->name);
8437
8438 drm_modeset_acquire_init(ctx, 0);
8439
8440 retry:
8441 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8442 if (ret)
8443 goto fail_unlock;
8444
8445 /*
8446 * Algorithm gets a little messy:
8447 *
8448 * - if the connector already has an assigned crtc, use it (but make
8449 * sure it's on first)
8450 *
8451 * - try to find the first unused crtc that can drive this connector,
8452 * and use that if we find one
8453 */
8454
8455 /* See if we already have a CRTC for this connector */
8456 if (encoder->crtc) {
8457 crtc = encoder->crtc;
8458
8459 ret = drm_modeset_lock(&crtc->mutex, ctx);
8460 if (ret)
8461 goto fail_unlock;
8462
8463 old->dpms_mode = connector->dpms;
8464 old->load_detect_temp = false;
8465
8466 /* Make sure the crtc and connector are running */
8467 if (connector->dpms != DRM_MODE_DPMS_ON)
8468 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8469
8470 return true;
8471 }
8472
8473 /* Find an unused one (if possible) */
8474 for_each_crtc(dev, possible_crtc) {
8475 i++;
8476 if (!(encoder->possible_crtcs & (1 << i)))
8477 continue;
8478 if (!possible_crtc->enabled) {
8479 crtc = possible_crtc;
8480 break;
8481 }
8482 }
8483
8484 /*
8485 * If we didn't find an unused CRTC, don't use any.
8486 */
8487 if (!crtc) {
8488 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8489 goto fail_unlock;
8490 }
8491
8492 ret = drm_modeset_lock(&crtc->mutex, ctx);
8493 if (ret)
8494 goto fail_unlock;
8495 intel_encoder->new_crtc = to_intel_crtc(crtc);
8496 to_intel_connector(connector)->new_encoder = intel_encoder;
8497
8498 intel_crtc = to_intel_crtc(crtc);
8499 intel_crtc->new_enabled = true;
8500 intel_crtc->new_config = &intel_crtc->config;
8501 old->dpms_mode = connector->dpms;
8502 old->load_detect_temp = true;
8503 old->release_fb = NULL;
8504
8505 if (!mode)
8506 mode = &load_detect_mode;
8507
8508 /* We need a framebuffer large enough to accommodate all accesses
8509 * that the plane may generate whilst we perform load detection.
8510 * We can not rely on the fbcon either being present (we get called
8511 * during its initialisation to detect all boot displays, or it may
8512 * not even exist) or that it is large enough to satisfy the
8513 * requested mode.
8514 */
8515 fb = mode_fits_in_fbdev(dev, mode);
8516 if (fb == NULL) {
8517 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8518 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8519 old->release_fb = fb;
8520 } else
8521 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8522 if (IS_ERR(fb)) {
8523 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8524 goto fail;
8525 }
8526
8527 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8528 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8529 if (old->release_fb)
8530 old->release_fb->funcs->destroy(old->release_fb);
8531 goto fail;
8532 }
8533
8534 /* let the connector get through one full cycle before testing */
8535 intel_wait_for_vblank(dev, intel_crtc->pipe);
8536 return true;
8537
8538 fail:
8539 intel_crtc->new_enabled = crtc->enabled;
8540 if (intel_crtc->new_enabled)
8541 intel_crtc->new_config = &intel_crtc->config;
8542 else
8543 intel_crtc->new_config = NULL;
8544 fail_unlock:
8545 if (ret == -EDEADLK) {
8546 drm_modeset_backoff(ctx);
8547 goto retry;
8548 }
8549
8550 drm_modeset_drop_locks(ctx);
8551 drm_modeset_acquire_fini(ctx);
8552
8553 return false;
8554 }
8555
8556 void intel_release_load_detect_pipe(struct drm_connector *connector,
8557 struct intel_load_detect_pipe *old,
8558 struct drm_modeset_acquire_ctx *ctx)
8559 {
8560 struct intel_encoder *intel_encoder =
8561 intel_attached_encoder(connector);
8562 struct drm_encoder *encoder = &intel_encoder->base;
8563 struct drm_crtc *crtc = encoder->crtc;
8564 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8565
8566 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8567 connector->base.id, connector->name,
8568 encoder->base.id, encoder->name);
8569
8570 if (old->load_detect_temp) {
8571 to_intel_connector(connector)->new_encoder = NULL;
8572 intel_encoder->new_crtc = NULL;
8573 intel_crtc->new_enabled = false;
8574 intel_crtc->new_config = NULL;
8575 intel_set_mode(crtc, NULL, 0, 0, NULL);
8576
8577 if (old->release_fb) {
8578 drm_framebuffer_unregister_private(old->release_fb);
8579 drm_framebuffer_unreference(old->release_fb);
8580 }
8581
8582 goto unlock;
8583 return;
8584 }
8585
8586 /* Switch crtc and encoder back off if necessary */
8587 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8588 connector->funcs->dpms(connector, old->dpms_mode);
8589
8590 unlock:
8591 drm_modeset_drop_locks(ctx);
8592 drm_modeset_acquire_fini(ctx);
8593 }
8594
8595 static int i9xx_pll_refclk(struct drm_device *dev,
8596 const struct intel_crtc_config *pipe_config)
8597 {
8598 struct drm_i915_private *dev_priv = dev->dev_private;
8599 u32 dpll = pipe_config->dpll_hw_state.dpll;
8600
8601 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8602 return dev_priv->vbt.lvds_ssc_freq;
8603 else if (HAS_PCH_SPLIT(dev))
8604 return 120000;
8605 else if (!IS_GEN2(dev))
8606 return 96000;
8607 else
8608 return 48000;
8609 }
8610
8611 /* Returns the clock of the currently programmed mode of the given pipe. */
8612 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8613 struct intel_crtc_config *pipe_config)
8614 {
8615 struct drm_device *dev = crtc->base.dev;
8616 struct drm_i915_private *dev_priv = dev->dev_private;
8617 int pipe = pipe_config->cpu_transcoder;
8618 u32 dpll = pipe_config->dpll_hw_state.dpll;
8619 u32 fp;
8620 intel_clock_t clock;
8621 int refclk = i9xx_pll_refclk(dev, pipe_config);
8622
8623 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8624 fp = pipe_config->dpll_hw_state.fp0;
8625 else
8626 fp = pipe_config->dpll_hw_state.fp1;
8627
8628 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8629 if (IS_PINEVIEW(dev)) {
8630 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8631 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8632 } else {
8633 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8634 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8635 }
8636
8637 if (!IS_GEN2(dev)) {
8638 if (IS_PINEVIEW(dev))
8639 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8640 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8641 else
8642 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8643 DPLL_FPA01_P1_POST_DIV_SHIFT);
8644
8645 switch (dpll & DPLL_MODE_MASK) {
8646 case DPLLB_MODE_DAC_SERIAL:
8647 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8648 5 : 10;
8649 break;
8650 case DPLLB_MODE_LVDS:
8651 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8652 7 : 14;
8653 break;
8654 default:
8655 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8656 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8657 return;
8658 }
8659
8660 if (IS_PINEVIEW(dev))
8661 pineview_clock(refclk, &clock);
8662 else
8663 i9xx_clock(refclk, &clock);
8664 } else {
8665 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8666 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8667
8668 if (is_lvds) {
8669 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8670 DPLL_FPA01_P1_POST_DIV_SHIFT);
8671
8672 if (lvds & LVDS_CLKB_POWER_UP)
8673 clock.p2 = 7;
8674 else
8675 clock.p2 = 14;
8676 } else {
8677 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8678 clock.p1 = 2;
8679 else {
8680 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8681 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8682 }
8683 if (dpll & PLL_P2_DIVIDE_BY_4)
8684 clock.p2 = 4;
8685 else
8686 clock.p2 = 2;
8687 }
8688
8689 i9xx_clock(refclk, &clock);
8690 }
8691
8692 /*
8693 * This value includes pixel_multiplier. We will use
8694 * port_clock to compute adjusted_mode.crtc_clock in the
8695 * encoder's get_config() function.
8696 */
8697 pipe_config->port_clock = clock.dot;
8698 }
8699
8700 int intel_dotclock_calculate(int link_freq,
8701 const struct intel_link_m_n *m_n)
8702 {
8703 /*
8704 * The calculation for the data clock is:
8705 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8706 * But we want to avoid losing precison if possible, so:
8707 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8708 *
8709 * and the link clock is simpler:
8710 * link_clock = (m * link_clock) / n
8711 */
8712
8713 if (!m_n->link_n)
8714 return 0;
8715
8716 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8717 }
8718
8719 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8720 struct intel_crtc_config *pipe_config)
8721 {
8722 struct drm_device *dev = crtc->base.dev;
8723
8724 /* read out port_clock from the DPLL */
8725 i9xx_crtc_clock_get(crtc, pipe_config);
8726
8727 /*
8728 * This value does not include pixel_multiplier.
8729 * We will check that port_clock and adjusted_mode.crtc_clock
8730 * agree once we know their relationship in the encoder's
8731 * get_config() function.
8732 */
8733 pipe_config->adjusted_mode.crtc_clock =
8734 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8735 &pipe_config->fdi_m_n);
8736 }
8737
8738 /** Returns the currently programmed mode of the given pipe. */
8739 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8740 struct drm_crtc *crtc)
8741 {
8742 struct drm_i915_private *dev_priv = dev->dev_private;
8743 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8744 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8745 struct drm_display_mode *mode;
8746 struct intel_crtc_config pipe_config;
8747 int htot = I915_READ(HTOTAL(cpu_transcoder));
8748 int hsync = I915_READ(HSYNC(cpu_transcoder));
8749 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8750 int vsync = I915_READ(VSYNC(cpu_transcoder));
8751 enum pipe pipe = intel_crtc->pipe;
8752
8753 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8754 if (!mode)
8755 return NULL;
8756
8757 /*
8758 * Construct a pipe_config sufficient for getting the clock info
8759 * back out of crtc_clock_get.
8760 *
8761 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8762 * to use a real value here instead.
8763 */
8764 pipe_config.cpu_transcoder = (enum transcoder) pipe;
8765 pipe_config.pixel_multiplier = 1;
8766 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8767 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8768 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8769 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8770
8771 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8772 mode->hdisplay = (htot & 0xffff) + 1;
8773 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8774 mode->hsync_start = (hsync & 0xffff) + 1;
8775 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8776 mode->vdisplay = (vtot & 0xffff) + 1;
8777 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8778 mode->vsync_start = (vsync & 0xffff) + 1;
8779 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8780
8781 drm_mode_set_name(mode);
8782
8783 return mode;
8784 }
8785
8786 static void intel_increase_pllclock(struct drm_device *dev,
8787 enum pipe pipe)
8788 {
8789 struct drm_i915_private *dev_priv = dev->dev_private;
8790 int dpll_reg = DPLL(pipe);
8791 int dpll;
8792
8793 if (HAS_PCH_SPLIT(dev))
8794 return;
8795
8796 if (!dev_priv->lvds_downclock_avail)
8797 return;
8798
8799 dpll = I915_READ(dpll_reg);
8800 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8801 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8802
8803 assert_panel_unlocked(dev_priv, pipe);
8804
8805 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8806 I915_WRITE(dpll_reg, dpll);
8807 intel_wait_for_vblank(dev, pipe);
8808
8809 dpll = I915_READ(dpll_reg);
8810 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8811 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8812 }
8813 }
8814
8815 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8816 {
8817 struct drm_device *dev = crtc->dev;
8818 struct drm_i915_private *dev_priv = dev->dev_private;
8819 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8820
8821 if (HAS_PCH_SPLIT(dev))
8822 return;
8823
8824 if (!dev_priv->lvds_downclock_avail)
8825 return;
8826
8827 /*
8828 * Since this is called by a timer, we should never get here in
8829 * the manual case.
8830 */
8831 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8832 int pipe = intel_crtc->pipe;
8833 int dpll_reg = DPLL(pipe);
8834 int dpll;
8835
8836 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8837
8838 assert_panel_unlocked(dev_priv, pipe);
8839
8840 dpll = I915_READ(dpll_reg);
8841 dpll |= DISPLAY_RATE_SELECT_FPA1;
8842 I915_WRITE(dpll_reg, dpll);
8843 intel_wait_for_vblank(dev, pipe);
8844 dpll = I915_READ(dpll_reg);
8845 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8846 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8847 }
8848
8849 }
8850
8851 void intel_mark_busy(struct drm_device *dev)
8852 {
8853 struct drm_i915_private *dev_priv = dev->dev_private;
8854
8855 if (dev_priv->mm.busy)
8856 return;
8857
8858 intel_runtime_pm_get(dev_priv);
8859 i915_update_gfx_val(dev_priv);
8860 dev_priv->mm.busy = true;
8861 }
8862
8863 void intel_mark_idle(struct drm_device *dev)
8864 {
8865 struct drm_i915_private *dev_priv = dev->dev_private;
8866 struct drm_crtc *crtc;
8867
8868 if (!dev_priv->mm.busy)
8869 return;
8870
8871 dev_priv->mm.busy = false;
8872
8873 if (!i915.powersave)
8874 goto out;
8875
8876 for_each_crtc(dev, crtc) {
8877 if (!crtc->primary->fb)
8878 continue;
8879
8880 intel_decrease_pllclock(crtc);
8881 }
8882
8883 if (INTEL_INFO(dev)->gen >= 6)
8884 gen6_rps_idle(dev->dev_private);
8885
8886 out:
8887 intel_runtime_pm_put(dev_priv);
8888 }
8889
8890
8891 /**
8892 * intel_mark_fb_busy - mark given planes as busy
8893 * @dev: DRM device
8894 * @frontbuffer_bits: bits for the affected planes
8895 * @ring: optional ring for asynchronous commands
8896 *
8897 * This function gets called every time the screen contents change. It can be
8898 * used to keep e.g. the update rate at the nominal refresh rate with DRRS.
8899 */
8900 static void intel_mark_fb_busy(struct drm_device *dev,
8901 unsigned frontbuffer_bits,
8902 struct intel_engine_cs *ring)
8903 {
8904 enum pipe pipe;
8905
8906 if (!i915.powersave)
8907 return;
8908
8909 for_each_pipe(pipe) {
8910 if (!(frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe)))
8911 continue;
8912
8913 intel_increase_pllclock(dev, pipe);
8914 if (ring && intel_fbc_enabled(dev))
8915 ring->fbc_dirty = true;
8916 }
8917 }
8918
8919 /**
8920 * intel_fb_obj_invalidate - invalidate frontbuffer object
8921 * @obj: GEM object to invalidate
8922 * @ring: set for asynchronous rendering
8923 *
8924 * This function gets called every time rendering on the given object starts and
8925 * frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must
8926 * be invalidated. If @ring is non-NULL any subsequent invalidation will be delayed
8927 * until the rendering completes or a flip on this frontbuffer plane is
8928 * scheduled.
8929 */
8930 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
8931 struct intel_engine_cs *ring)
8932 {
8933 struct drm_device *dev = obj->base.dev;
8934 struct drm_i915_private *dev_priv = dev->dev_private;
8935
8936 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
8937
8938 if (!obj->frontbuffer_bits)
8939 return;
8940
8941 if (ring) {
8942 mutex_lock(&dev_priv->fb_tracking.lock);
8943 dev_priv->fb_tracking.busy_bits
8944 |= obj->frontbuffer_bits;
8945 dev_priv->fb_tracking.flip_bits
8946 &= ~obj->frontbuffer_bits;
8947 mutex_unlock(&dev_priv->fb_tracking.lock);
8948 }
8949
8950 intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring);
8951
8952 intel_edp_psr_exit(dev);
8953 }
8954
8955 /**
8956 * intel_frontbuffer_flush - flush frontbuffer
8957 * @dev: DRM device
8958 * @frontbuffer_bits: frontbuffer plane tracking bits
8959 *
8960 * This function gets called every time rendering on the given planes has
8961 * completed and frontbuffer caching can be started again. Flushes will get
8962 * delayed if they're blocked by some oustanding asynchronous rendering.
8963 *
8964 * Can be called without any locks held.
8965 */
8966 void intel_frontbuffer_flush(struct drm_device *dev,
8967 unsigned frontbuffer_bits)
8968 {
8969 struct drm_i915_private *dev_priv = dev->dev_private;
8970
8971 /* Delay flushing when rings are still busy.*/
8972 mutex_lock(&dev_priv->fb_tracking.lock);
8973 frontbuffer_bits &= ~dev_priv->fb_tracking.busy_bits;
8974 mutex_unlock(&dev_priv->fb_tracking.lock);
8975
8976 intel_mark_fb_busy(dev, frontbuffer_bits, NULL);
8977
8978 intel_edp_psr_exit(dev);
8979 }
8980
8981 /**
8982 * intel_fb_obj_flush - flush frontbuffer object
8983 * @obj: GEM object to flush
8984 * @retire: set when retiring asynchronous rendering
8985 *
8986 * This function gets called every time rendering on the given object has
8987 * completed and frontbuffer caching can be started again. If @retire is true
8988 * then any delayed flushes will be unblocked.
8989 */
8990 void intel_fb_obj_flush(struct drm_i915_gem_object *obj,
8991 bool retire)
8992 {
8993 struct drm_device *dev = obj->base.dev;
8994 struct drm_i915_private *dev_priv = dev->dev_private;
8995 unsigned frontbuffer_bits;
8996
8997 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
8998
8999 if (!obj->frontbuffer_bits)
9000 return;
9001
9002 frontbuffer_bits = obj->frontbuffer_bits;
9003
9004 if (retire) {
9005 mutex_lock(&dev_priv->fb_tracking.lock);
9006 /* Filter out new bits since rendering started. */
9007 frontbuffer_bits &= dev_priv->fb_tracking.busy_bits;
9008
9009 dev_priv->fb_tracking.busy_bits &= ~frontbuffer_bits;
9010 mutex_unlock(&dev_priv->fb_tracking.lock);
9011 }
9012
9013 intel_frontbuffer_flush(dev, frontbuffer_bits);
9014 }
9015
9016 /**
9017 * intel_frontbuffer_flip_prepare - prepare asnychronous frontbuffer flip
9018 * @dev: DRM device
9019 * @frontbuffer_bits: frontbuffer plane tracking bits
9020 *
9021 * This function gets called after scheduling a flip on @obj. The actual
9022 * frontbuffer flushing will be delayed until completion is signalled with
9023 * intel_frontbuffer_flip_complete. If an invalidate happens in between this
9024 * flush will be cancelled.
9025 *
9026 * Can be called without any locks held.
9027 */
9028 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
9029 unsigned frontbuffer_bits)
9030 {
9031 struct drm_i915_private *dev_priv = dev->dev_private;
9032
9033 mutex_lock(&dev_priv->fb_tracking.lock);
9034 dev_priv->fb_tracking.flip_bits
9035 |= frontbuffer_bits;
9036 mutex_unlock(&dev_priv->fb_tracking.lock);
9037 }
9038
9039 /**
9040 * intel_frontbuffer_flip_complete - complete asynchronous frontbuffer flush
9041 * @dev: DRM device
9042 * @frontbuffer_bits: frontbuffer plane tracking bits
9043 *
9044 * This function gets called after the flip has been latched and will complete
9045 * on the next vblank. It will execute the fush if it hasn't been cancalled yet.
9046 *
9047 * Can be called without any locks held.
9048 */
9049 void intel_frontbuffer_flip_complete(struct drm_device *dev,
9050 unsigned frontbuffer_bits)
9051 {
9052 struct drm_i915_private *dev_priv = dev->dev_private;
9053
9054 mutex_lock(&dev_priv->fb_tracking.lock);
9055 /* Mask any cancelled flips. */
9056 frontbuffer_bits &= dev_priv->fb_tracking.flip_bits;
9057 dev_priv->fb_tracking.flip_bits &= ~frontbuffer_bits;
9058 mutex_unlock(&dev_priv->fb_tracking.lock);
9059
9060 intel_frontbuffer_flush(dev, frontbuffer_bits);
9061 }
9062
9063 static void intel_crtc_destroy(struct drm_crtc *crtc)
9064 {
9065 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9066 struct drm_device *dev = crtc->dev;
9067 struct intel_unpin_work *work;
9068 unsigned long flags;
9069
9070 spin_lock_irqsave(&dev->event_lock, flags);
9071 work = intel_crtc->unpin_work;
9072 intel_crtc->unpin_work = NULL;
9073 spin_unlock_irqrestore(&dev->event_lock, flags);
9074
9075 if (work) {
9076 cancel_work_sync(&work->work);
9077 kfree(work);
9078 }
9079
9080 drm_crtc_cleanup(crtc);
9081
9082 kfree(intel_crtc);
9083 }
9084
9085 static void intel_unpin_work_fn(struct work_struct *__work)
9086 {
9087 struct intel_unpin_work *work =
9088 container_of(__work, struct intel_unpin_work, work);
9089 struct drm_device *dev = work->crtc->dev;
9090 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9091
9092 mutex_lock(&dev->struct_mutex);
9093 intel_unpin_fb_obj(work->old_fb_obj);
9094 drm_gem_object_unreference(&work->pending_flip_obj->base);
9095 drm_gem_object_unreference(&work->old_fb_obj->base);
9096
9097 intel_update_fbc(dev);
9098 mutex_unlock(&dev->struct_mutex);
9099
9100 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9101
9102 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9103 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9104
9105 kfree(work);
9106 }
9107
9108 static void do_intel_finish_page_flip(struct drm_device *dev,
9109 struct drm_crtc *crtc)
9110 {
9111 struct drm_i915_private *dev_priv = dev->dev_private;
9112 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9113 struct intel_unpin_work *work;
9114 unsigned long flags;
9115
9116 /* Ignore early vblank irqs */
9117 if (intel_crtc == NULL)
9118 return;
9119
9120 spin_lock_irqsave(&dev->event_lock, flags);
9121 work = intel_crtc->unpin_work;
9122
9123 /* Ensure we don't miss a work->pending update ... */
9124 smp_rmb();
9125
9126 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9127 spin_unlock_irqrestore(&dev->event_lock, flags);
9128 return;
9129 }
9130
9131 /* and that the unpin work is consistent wrt ->pending. */
9132 smp_rmb();
9133
9134 intel_crtc->unpin_work = NULL;
9135
9136 if (work->event)
9137 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
9138
9139 drm_crtc_vblank_put(crtc);
9140
9141 spin_unlock_irqrestore(&dev->event_lock, flags);
9142
9143 wake_up_all(&dev_priv->pending_flip_queue);
9144
9145 queue_work(dev_priv->wq, &work->work);
9146
9147 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
9148 }
9149
9150 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9151 {
9152 struct drm_i915_private *dev_priv = dev->dev_private;
9153 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9154
9155 do_intel_finish_page_flip(dev, crtc);
9156 }
9157
9158 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9159 {
9160 struct drm_i915_private *dev_priv = dev->dev_private;
9161 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9162
9163 do_intel_finish_page_flip(dev, crtc);
9164 }
9165
9166 /* Is 'a' after or equal to 'b'? */
9167 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9168 {
9169 return !((a - b) & 0x80000000);
9170 }
9171
9172 static bool page_flip_finished(struct intel_crtc *crtc)
9173 {
9174 struct drm_device *dev = crtc->base.dev;
9175 struct drm_i915_private *dev_priv = dev->dev_private;
9176
9177 /*
9178 * The relevant registers doen't exist on pre-ctg.
9179 * As the flip done interrupt doesn't trigger for mmio
9180 * flips on gmch platforms, a flip count check isn't
9181 * really needed there. But since ctg has the registers,
9182 * include it in the check anyway.
9183 */
9184 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9185 return true;
9186
9187 /*
9188 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9189 * used the same base address. In that case the mmio flip might
9190 * have completed, but the CS hasn't even executed the flip yet.
9191 *
9192 * A flip count check isn't enough as the CS might have updated
9193 * the base address just after start of vblank, but before we
9194 * managed to process the interrupt. This means we'd complete the
9195 * CS flip too soon.
9196 *
9197 * Combining both checks should get us a good enough result. It may
9198 * still happen that the CS flip has been executed, but has not
9199 * yet actually completed. But in case the base address is the same
9200 * anyway, we don't really care.
9201 */
9202 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9203 crtc->unpin_work->gtt_offset &&
9204 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9205 crtc->unpin_work->flip_count);
9206 }
9207
9208 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9209 {
9210 struct drm_i915_private *dev_priv = dev->dev_private;
9211 struct intel_crtc *intel_crtc =
9212 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9213 unsigned long flags;
9214
9215 /* NB: An MMIO update of the plane base pointer will also
9216 * generate a page-flip completion irq, i.e. every modeset
9217 * is also accompanied by a spurious intel_prepare_page_flip().
9218 */
9219 spin_lock_irqsave(&dev->event_lock, flags);
9220 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9221 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9222 spin_unlock_irqrestore(&dev->event_lock, flags);
9223 }
9224
9225 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9226 {
9227 /* Ensure that the work item is consistent when activating it ... */
9228 smp_wmb();
9229 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9230 /* and that it is marked active as soon as the irq could fire. */
9231 smp_wmb();
9232 }
9233
9234 static int intel_gen2_queue_flip(struct drm_device *dev,
9235 struct drm_crtc *crtc,
9236 struct drm_framebuffer *fb,
9237 struct drm_i915_gem_object *obj,
9238 struct intel_engine_cs *ring,
9239 uint32_t flags)
9240 {
9241 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9242 u32 flip_mask;
9243 int ret;
9244
9245 ret = intel_ring_begin(ring, 6);
9246 if (ret)
9247 return ret;
9248
9249 /* Can't queue multiple flips, so wait for the previous
9250 * one to finish before executing the next.
9251 */
9252 if (intel_crtc->plane)
9253 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9254 else
9255 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9256 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9257 intel_ring_emit(ring, MI_NOOP);
9258 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9259 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9260 intel_ring_emit(ring, fb->pitches[0]);
9261 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9262 intel_ring_emit(ring, 0); /* aux display base address, unused */
9263
9264 intel_mark_page_flip_active(intel_crtc);
9265 __intel_ring_advance(ring);
9266 return 0;
9267 }
9268
9269 static int intel_gen3_queue_flip(struct drm_device *dev,
9270 struct drm_crtc *crtc,
9271 struct drm_framebuffer *fb,
9272 struct drm_i915_gem_object *obj,
9273 struct intel_engine_cs *ring,
9274 uint32_t flags)
9275 {
9276 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9277 u32 flip_mask;
9278 int ret;
9279
9280 ret = intel_ring_begin(ring, 6);
9281 if (ret)
9282 return ret;
9283
9284 if (intel_crtc->plane)
9285 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9286 else
9287 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9288 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9289 intel_ring_emit(ring, MI_NOOP);
9290 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9291 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9292 intel_ring_emit(ring, fb->pitches[0]);
9293 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9294 intel_ring_emit(ring, MI_NOOP);
9295
9296 intel_mark_page_flip_active(intel_crtc);
9297 __intel_ring_advance(ring);
9298 return 0;
9299 }
9300
9301 static int intel_gen4_queue_flip(struct drm_device *dev,
9302 struct drm_crtc *crtc,
9303 struct drm_framebuffer *fb,
9304 struct drm_i915_gem_object *obj,
9305 struct intel_engine_cs *ring,
9306 uint32_t flags)
9307 {
9308 struct drm_i915_private *dev_priv = dev->dev_private;
9309 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9310 uint32_t pf, pipesrc;
9311 int ret;
9312
9313 ret = intel_ring_begin(ring, 4);
9314 if (ret)
9315 return ret;
9316
9317 /* i965+ uses the linear or tiled offsets from the
9318 * Display Registers (which do not change across a page-flip)
9319 * so we need only reprogram the base address.
9320 */
9321 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9322 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9323 intel_ring_emit(ring, fb->pitches[0]);
9324 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9325 obj->tiling_mode);
9326
9327 /* XXX Enabling the panel-fitter across page-flip is so far
9328 * untested on non-native modes, so ignore it for now.
9329 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9330 */
9331 pf = 0;
9332 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9333 intel_ring_emit(ring, pf | pipesrc);
9334
9335 intel_mark_page_flip_active(intel_crtc);
9336 __intel_ring_advance(ring);
9337 return 0;
9338 }
9339
9340 static int intel_gen6_queue_flip(struct drm_device *dev,
9341 struct drm_crtc *crtc,
9342 struct drm_framebuffer *fb,
9343 struct drm_i915_gem_object *obj,
9344 struct intel_engine_cs *ring,
9345 uint32_t flags)
9346 {
9347 struct drm_i915_private *dev_priv = dev->dev_private;
9348 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9349 uint32_t pf, pipesrc;
9350 int ret;
9351
9352 ret = intel_ring_begin(ring, 4);
9353 if (ret)
9354 return ret;
9355
9356 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9357 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9358 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9359 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9360
9361 /* Contrary to the suggestions in the documentation,
9362 * "Enable Panel Fitter" does not seem to be required when page
9363 * flipping with a non-native mode, and worse causes a normal
9364 * modeset to fail.
9365 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9366 */
9367 pf = 0;
9368 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9369 intel_ring_emit(ring, pf | pipesrc);
9370
9371 intel_mark_page_flip_active(intel_crtc);
9372 __intel_ring_advance(ring);
9373 return 0;
9374 }
9375
9376 static int intel_gen7_queue_flip(struct drm_device *dev,
9377 struct drm_crtc *crtc,
9378 struct drm_framebuffer *fb,
9379 struct drm_i915_gem_object *obj,
9380 struct intel_engine_cs *ring,
9381 uint32_t flags)
9382 {
9383 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9384 uint32_t plane_bit = 0;
9385 int len, ret;
9386
9387 switch (intel_crtc->plane) {
9388 case PLANE_A:
9389 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9390 break;
9391 case PLANE_B:
9392 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9393 break;
9394 case PLANE_C:
9395 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9396 break;
9397 default:
9398 WARN_ONCE(1, "unknown plane in flip command\n");
9399 return -ENODEV;
9400 }
9401
9402 len = 4;
9403 if (ring->id == RCS) {
9404 len += 6;
9405 /*
9406 * On Gen 8, SRM is now taking an extra dword to accommodate
9407 * 48bits addresses, and we need a NOOP for the batch size to
9408 * stay even.
9409 */
9410 if (IS_GEN8(dev))
9411 len += 2;
9412 }
9413
9414 /*
9415 * BSpec MI_DISPLAY_FLIP for IVB:
9416 * "The full packet must be contained within the same cache line."
9417 *
9418 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9419 * cacheline, if we ever start emitting more commands before
9420 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9421 * then do the cacheline alignment, and finally emit the
9422 * MI_DISPLAY_FLIP.
9423 */
9424 ret = intel_ring_cacheline_align(ring);
9425 if (ret)
9426 return ret;
9427
9428 ret = intel_ring_begin(ring, len);
9429 if (ret)
9430 return ret;
9431
9432 /* Unmask the flip-done completion message. Note that the bspec says that
9433 * we should do this for both the BCS and RCS, and that we must not unmask
9434 * more than one flip event at any time (or ensure that one flip message
9435 * can be sent by waiting for flip-done prior to queueing new flips).
9436 * Experimentation says that BCS works despite DERRMR masking all
9437 * flip-done completion events and that unmasking all planes at once
9438 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9439 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9440 */
9441 if (ring->id == RCS) {
9442 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9443 intel_ring_emit(ring, DERRMR);
9444 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9445 DERRMR_PIPEB_PRI_FLIP_DONE |
9446 DERRMR_PIPEC_PRI_FLIP_DONE));
9447 if (IS_GEN8(dev))
9448 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9449 MI_SRM_LRM_GLOBAL_GTT);
9450 else
9451 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9452 MI_SRM_LRM_GLOBAL_GTT);
9453 intel_ring_emit(ring, DERRMR);
9454 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9455 if (IS_GEN8(dev)) {
9456 intel_ring_emit(ring, 0);
9457 intel_ring_emit(ring, MI_NOOP);
9458 }
9459 }
9460
9461 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9462 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9463 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9464 intel_ring_emit(ring, (MI_NOOP));
9465
9466 intel_mark_page_flip_active(intel_crtc);
9467 __intel_ring_advance(ring);
9468 return 0;
9469 }
9470
9471 static bool use_mmio_flip(struct intel_engine_cs *ring,
9472 struct drm_i915_gem_object *obj)
9473 {
9474 /*
9475 * This is not being used for older platforms, because
9476 * non-availability of flip done interrupt forces us to use
9477 * CS flips. Older platforms derive flip done using some clever
9478 * tricks involving the flip_pending status bits and vblank irqs.
9479 * So using MMIO flips there would disrupt this mechanism.
9480 */
9481
9482 if (ring == NULL)
9483 return true;
9484
9485 if (INTEL_INFO(ring->dev)->gen < 5)
9486 return false;
9487
9488 if (i915.use_mmio_flip < 0)
9489 return false;
9490 else if (i915.use_mmio_flip > 0)
9491 return true;
9492 else
9493 return ring != obj->ring;
9494 }
9495
9496 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9497 {
9498 struct drm_device *dev = intel_crtc->base.dev;
9499 struct drm_i915_private *dev_priv = dev->dev_private;
9500 struct intel_framebuffer *intel_fb =
9501 to_intel_framebuffer(intel_crtc->base.primary->fb);
9502 struct drm_i915_gem_object *obj = intel_fb->obj;
9503 u32 dspcntr;
9504 u32 reg;
9505
9506 intel_mark_page_flip_active(intel_crtc);
9507
9508 reg = DSPCNTR(intel_crtc->plane);
9509 dspcntr = I915_READ(reg);
9510
9511 if (INTEL_INFO(dev)->gen >= 4) {
9512 if (obj->tiling_mode != I915_TILING_NONE)
9513 dspcntr |= DISPPLANE_TILED;
9514 else
9515 dspcntr &= ~DISPPLANE_TILED;
9516 }
9517 I915_WRITE(reg, dspcntr);
9518
9519 I915_WRITE(DSPSURF(intel_crtc->plane),
9520 intel_crtc->unpin_work->gtt_offset);
9521 POSTING_READ(DSPSURF(intel_crtc->plane));
9522 }
9523
9524 static int intel_postpone_flip(struct drm_i915_gem_object *obj)
9525 {
9526 struct intel_engine_cs *ring;
9527 int ret;
9528
9529 lockdep_assert_held(&obj->base.dev->struct_mutex);
9530
9531 if (!obj->last_write_seqno)
9532 return 0;
9533
9534 ring = obj->ring;
9535
9536 if (i915_seqno_passed(ring->get_seqno(ring, true),
9537 obj->last_write_seqno))
9538 return 0;
9539
9540 ret = i915_gem_check_olr(ring, obj->last_write_seqno);
9541 if (ret)
9542 return ret;
9543
9544 if (WARN_ON(!ring->irq_get(ring)))
9545 return 0;
9546
9547 return 1;
9548 }
9549
9550 void intel_notify_mmio_flip(struct intel_engine_cs *ring)
9551 {
9552 struct drm_i915_private *dev_priv = to_i915(ring->dev);
9553 struct intel_crtc *intel_crtc;
9554 unsigned long irq_flags;
9555 u32 seqno;
9556
9557 seqno = ring->get_seqno(ring, false);
9558
9559 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9560 for_each_intel_crtc(ring->dev, intel_crtc) {
9561 struct intel_mmio_flip *mmio_flip;
9562
9563 mmio_flip = &intel_crtc->mmio_flip;
9564 if (mmio_flip->seqno == 0)
9565 continue;
9566
9567 if (ring->id != mmio_flip->ring_id)
9568 continue;
9569
9570 if (i915_seqno_passed(seqno, mmio_flip->seqno)) {
9571 intel_do_mmio_flip(intel_crtc);
9572 mmio_flip->seqno = 0;
9573 ring->irq_put(ring);
9574 }
9575 }
9576 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9577 }
9578
9579 static int intel_queue_mmio_flip(struct drm_device *dev,
9580 struct drm_crtc *crtc,
9581 struct drm_framebuffer *fb,
9582 struct drm_i915_gem_object *obj,
9583 struct intel_engine_cs *ring,
9584 uint32_t flags)
9585 {
9586 struct drm_i915_private *dev_priv = dev->dev_private;
9587 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9588 unsigned long irq_flags;
9589 int ret;
9590
9591 if (WARN_ON(intel_crtc->mmio_flip.seqno))
9592 return -EBUSY;
9593
9594 ret = intel_postpone_flip(obj);
9595 if (ret < 0)
9596 return ret;
9597 if (ret == 0) {
9598 intel_do_mmio_flip(intel_crtc);
9599 return 0;
9600 }
9601
9602 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9603 intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9604 intel_crtc->mmio_flip.ring_id = obj->ring->id;
9605 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9606
9607 /*
9608 * Double check to catch cases where irq fired before
9609 * mmio flip data was ready
9610 */
9611 intel_notify_mmio_flip(obj->ring);
9612 return 0;
9613 }
9614
9615 static int intel_default_queue_flip(struct drm_device *dev,
9616 struct drm_crtc *crtc,
9617 struct drm_framebuffer *fb,
9618 struct drm_i915_gem_object *obj,
9619 struct intel_engine_cs *ring,
9620 uint32_t flags)
9621 {
9622 return -ENODEV;
9623 }
9624
9625 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9626 struct drm_framebuffer *fb,
9627 struct drm_pending_vblank_event *event,
9628 uint32_t page_flip_flags)
9629 {
9630 struct drm_device *dev = crtc->dev;
9631 struct drm_i915_private *dev_priv = dev->dev_private;
9632 struct drm_framebuffer *old_fb = crtc->primary->fb;
9633 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9634 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9635 enum pipe pipe = intel_crtc->pipe;
9636 struct intel_unpin_work *work;
9637 struct intel_engine_cs *ring;
9638 unsigned long flags;
9639 int ret;
9640
9641 /*
9642 * drm_mode_page_flip_ioctl() should already catch this, but double
9643 * check to be safe. In the future we may enable pageflipping from
9644 * a disabled primary plane.
9645 */
9646 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9647 return -EBUSY;
9648
9649 /* Can't change pixel format via MI display flips. */
9650 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9651 return -EINVAL;
9652
9653 /*
9654 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9655 * Note that pitch changes could also affect these register.
9656 */
9657 if (INTEL_INFO(dev)->gen > 3 &&
9658 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9659 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9660 return -EINVAL;
9661
9662 if (i915_terminally_wedged(&dev_priv->gpu_error))
9663 goto out_hang;
9664
9665 work = kzalloc(sizeof(*work), GFP_KERNEL);
9666 if (work == NULL)
9667 return -ENOMEM;
9668
9669 work->event = event;
9670 work->crtc = crtc;
9671 work->old_fb_obj = intel_fb_obj(old_fb);
9672 INIT_WORK(&work->work, intel_unpin_work_fn);
9673
9674 ret = drm_crtc_vblank_get(crtc);
9675 if (ret)
9676 goto free_work;
9677
9678 /* We borrow the event spin lock for protecting unpin_work */
9679 spin_lock_irqsave(&dev->event_lock, flags);
9680 if (intel_crtc->unpin_work) {
9681 spin_unlock_irqrestore(&dev->event_lock, flags);
9682 kfree(work);
9683 drm_crtc_vblank_put(crtc);
9684
9685 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9686 return -EBUSY;
9687 }
9688 intel_crtc->unpin_work = work;
9689 spin_unlock_irqrestore(&dev->event_lock, flags);
9690
9691 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9692 flush_workqueue(dev_priv->wq);
9693
9694 ret = i915_mutex_lock_interruptible(dev);
9695 if (ret)
9696 goto cleanup;
9697
9698 /* Reference the objects for the scheduled work. */
9699 drm_gem_object_reference(&work->old_fb_obj->base);
9700 drm_gem_object_reference(&obj->base);
9701
9702 crtc->primary->fb = fb;
9703
9704 work->pending_flip_obj = obj;
9705
9706 work->enable_stall_check = true;
9707
9708 atomic_inc(&intel_crtc->unpin_work_count);
9709 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9710
9711 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9712 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9713
9714 if (IS_VALLEYVIEW(dev)) {
9715 ring = &dev_priv->ring[BCS];
9716 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9717 /* vlv: DISPLAY_FLIP fails to change tiling */
9718 ring = NULL;
9719 } else if (IS_IVYBRIDGE(dev)) {
9720 ring = &dev_priv->ring[BCS];
9721 } else if (INTEL_INFO(dev)->gen >= 7) {
9722 ring = obj->ring;
9723 if (ring == NULL || ring->id != RCS)
9724 ring = &dev_priv->ring[BCS];
9725 } else {
9726 ring = &dev_priv->ring[RCS];
9727 }
9728
9729 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9730 if (ret)
9731 goto cleanup_pending;
9732
9733 work->gtt_offset =
9734 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9735
9736 if (use_mmio_flip(ring, obj))
9737 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9738 page_flip_flags);
9739 else
9740 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9741 page_flip_flags);
9742 if (ret)
9743 goto cleanup_unpin;
9744
9745 i915_gem_track_fb(work->old_fb_obj, obj,
9746 INTEL_FRONTBUFFER_PRIMARY(pipe));
9747
9748 intel_disable_fbc(dev);
9749 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9750 mutex_unlock(&dev->struct_mutex);
9751
9752 trace_i915_flip_request(intel_crtc->plane, obj);
9753
9754 return 0;
9755
9756 cleanup_unpin:
9757 intel_unpin_fb_obj(obj);
9758 cleanup_pending:
9759 atomic_dec(&intel_crtc->unpin_work_count);
9760 crtc->primary->fb = old_fb;
9761 drm_gem_object_unreference(&work->old_fb_obj->base);
9762 drm_gem_object_unreference(&obj->base);
9763 mutex_unlock(&dev->struct_mutex);
9764
9765 cleanup:
9766 spin_lock_irqsave(&dev->event_lock, flags);
9767 intel_crtc->unpin_work = NULL;
9768 spin_unlock_irqrestore(&dev->event_lock, flags);
9769
9770 drm_crtc_vblank_put(crtc);
9771 free_work:
9772 kfree(work);
9773
9774 if (ret == -EIO) {
9775 out_hang:
9776 intel_crtc_wait_for_pending_flips(crtc);
9777 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9778 if (ret == 0 && event)
9779 drm_send_vblank_event(dev, pipe, event);
9780 }
9781 return ret;
9782 }
9783
9784 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9785 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9786 .load_lut = intel_crtc_load_lut,
9787 };
9788
9789 /**
9790 * intel_modeset_update_staged_output_state
9791 *
9792 * Updates the staged output configuration state, e.g. after we've read out the
9793 * current hw state.
9794 */
9795 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9796 {
9797 struct intel_crtc *crtc;
9798 struct intel_encoder *encoder;
9799 struct intel_connector *connector;
9800
9801 list_for_each_entry(connector, &dev->mode_config.connector_list,
9802 base.head) {
9803 connector->new_encoder =
9804 to_intel_encoder(connector->base.encoder);
9805 }
9806
9807 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9808 base.head) {
9809 encoder->new_crtc =
9810 to_intel_crtc(encoder->base.crtc);
9811 }
9812
9813 for_each_intel_crtc(dev, crtc) {
9814 crtc->new_enabled = crtc->base.enabled;
9815
9816 if (crtc->new_enabled)
9817 crtc->new_config = &crtc->config;
9818 else
9819 crtc->new_config = NULL;
9820 }
9821 }
9822
9823 /**
9824 * intel_modeset_commit_output_state
9825 *
9826 * This function copies the stage display pipe configuration to the real one.
9827 */
9828 static void intel_modeset_commit_output_state(struct drm_device *dev)
9829 {
9830 struct intel_crtc *crtc;
9831 struct intel_encoder *encoder;
9832 struct intel_connector *connector;
9833
9834 list_for_each_entry(connector, &dev->mode_config.connector_list,
9835 base.head) {
9836 connector->base.encoder = &connector->new_encoder->base;
9837 }
9838
9839 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9840 base.head) {
9841 encoder->base.crtc = &encoder->new_crtc->base;
9842 }
9843
9844 for_each_intel_crtc(dev, crtc) {
9845 crtc->base.enabled = crtc->new_enabled;
9846 }
9847 }
9848
9849 static void
9850 connected_sink_compute_bpp(struct intel_connector *connector,
9851 struct intel_crtc_config *pipe_config)
9852 {
9853 int bpp = pipe_config->pipe_bpp;
9854
9855 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9856 connector->base.base.id,
9857 connector->base.name);
9858
9859 /* Don't use an invalid EDID bpc value */
9860 if (connector->base.display_info.bpc &&
9861 connector->base.display_info.bpc * 3 < bpp) {
9862 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9863 bpp, connector->base.display_info.bpc*3);
9864 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9865 }
9866
9867 /* Clamp bpp to 8 on screens without EDID 1.4 */
9868 if (connector->base.display_info.bpc == 0 && bpp > 24) {
9869 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9870 bpp);
9871 pipe_config->pipe_bpp = 24;
9872 }
9873 }
9874
9875 static int
9876 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9877 struct drm_framebuffer *fb,
9878 struct intel_crtc_config *pipe_config)
9879 {
9880 struct drm_device *dev = crtc->base.dev;
9881 struct intel_connector *connector;
9882 int bpp;
9883
9884 switch (fb->pixel_format) {
9885 case DRM_FORMAT_C8:
9886 bpp = 8*3; /* since we go through a colormap */
9887 break;
9888 case DRM_FORMAT_XRGB1555:
9889 case DRM_FORMAT_ARGB1555:
9890 /* checked in intel_framebuffer_init already */
9891 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9892 return -EINVAL;
9893 case DRM_FORMAT_RGB565:
9894 bpp = 6*3; /* min is 18bpp */
9895 break;
9896 case DRM_FORMAT_XBGR8888:
9897 case DRM_FORMAT_ABGR8888:
9898 /* checked in intel_framebuffer_init already */
9899 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9900 return -EINVAL;
9901 case DRM_FORMAT_XRGB8888:
9902 case DRM_FORMAT_ARGB8888:
9903 bpp = 8*3;
9904 break;
9905 case DRM_FORMAT_XRGB2101010:
9906 case DRM_FORMAT_ARGB2101010:
9907 case DRM_FORMAT_XBGR2101010:
9908 case DRM_FORMAT_ABGR2101010:
9909 /* checked in intel_framebuffer_init already */
9910 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9911 return -EINVAL;
9912 bpp = 10*3;
9913 break;
9914 /* TODO: gen4+ supports 16 bpc floating point, too. */
9915 default:
9916 DRM_DEBUG_KMS("unsupported depth\n");
9917 return -EINVAL;
9918 }
9919
9920 pipe_config->pipe_bpp = bpp;
9921
9922 /* Clamp display bpp to EDID value */
9923 list_for_each_entry(connector, &dev->mode_config.connector_list,
9924 base.head) {
9925 if (!connector->new_encoder ||
9926 connector->new_encoder->new_crtc != crtc)
9927 continue;
9928
9929 connected_sink_compute_bpp(connector, pipe_config);
9930 }
9931
9932 return bpp;
9933 }
9934
9935 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9936 {
9937 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9938 "type: 0x%x flags: 0x%x\n",
9939 mode->crtc_clock,
9940 mode->crtc_hdisplay, mode->crtc_hsync_start,
9941 mode->crtc_hsync_end, mode->crtc_htotal,
9942 mode->crtc_vdisplay, mode->crtc_vsync_start,
9943 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9944 }
9945
9946 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9947 struct intel_crtc_config *pipe_config,
9948 const char *context)
9949 {
9950 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9951 context, pipe_name(crtc->pipe));
9952
9953 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9954 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9955 pipe_config->pipe_bpp, pipe_config->dither);
9956 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9957 pipe_config->has_pch_encoder,
9958 pipe_config->fdi_lanes,
9959 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9960 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9961 pipe_config->fdi_m_n.tu);
9962 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9963 pipe_config->has_dp_encoder,
9964 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9965 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9966 pipe_config->dp_m_n.tu);
9967 DRM_DEBUG_KMS("requested mode:\n");
9968 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9969 DRM_DEBUG_KMS("adjusted mode:\n");
9970 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9971 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9972 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9973 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9974 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9975 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9976 pipe_config->gmch_pfit.control,
9977 pipe_config->gmch_pfit.pgm_ratios,
9978 pipe_config->gmch_pfit.lvds_border_bits);
9979 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9980 pipe_config->pch_pfit.pos,
9981 pipe_config->pch_pfit.size,
9982 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9983 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9984 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
9985 }
9986
9987 static bool encoders_cloneable(const struct intel_encoder *a,
9988 const struct intel_encoder *b)
9989 {
9990 /* masks could be asymmetric, so check both ways */
9991 return a == b || (a->cloneable & (1 << b->type) &&
9992 b->cloneable & (1 << a->type));
9993 }
9994
9995 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9996 struct intel_encoder *encoder)
9997 {
9998 struct drm_device *dev = crtc->base.dev;
9999 struct intel_encoder *source_encoder;
10000
10001 list_for_each_entry(source_encoder,
10002 &dev->mode_config.encoder_list, base.head) {
10003 if (source_encoder->new_crtc != crtc)
10004 continue;
10005
10006 if (!encoders_cloneable(encoder, source_encoder))
10007 return false;
10008 }
10009
10010 return true;
10011 }
10012
10013 static bool check_encoder_cloning(struct intel_crtc *crtc)
10014 {
10015 struct drm_device *dev = crtc->base.dev;
10016 struct intel_encoder *encoder;
10017
10018 list_for_each_entry(encoder,
10019 &dev->mode_config.encoder_list, base.head) {
10020 if (encoder->new_crtc != crtc)
10021 continue;
10022
10023 if (!check_single_encoder_cloning(crtc, encoder))
10024 return false;
10025 }
10026
10027 return true;
10028 }
10029
10030 static struct intel_crtc_config *
10031 intel_modeset_pipe_config(struct drm_crtc *crtc,
10032 struct drm_framebuffer *fb,
10033 struct drm_display_mode *mode)
10034 {
10035 struct drm_device *dev = crtc->dev;
10036 struct intel_encoder *encoder;
10037 struct intel_crtc_config *pipe_config;
10038 int plane_bpp, ret = -EINVAL;
10039 bool retry = true;
10040
10041 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10042 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10043 return ERR_PTR(-EINVAL);
10044 }
10045
10046 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10047 if (!pipe_config)
10048 return ERR_PTR(-ENOMEM);
10049
10050 drm_mode_copy(&pipe_config->adjusted_mode, mode);
10051 drm_mode_copy(&pipe_config->requested_mode, mode);
10052
10053 pipe_config->cpu_transcoder =
10054 (enum transcoder) to_intel_crtc(crtc)->pipe;
10055 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10056
10057 /*
10058 * Sanitize sync polarity flags based on requested ones. If neither
10059 * positive or negative polarity is requested, treat this as meaning
10060 * negative polarity.
10061 */
10062 if (!(pipe_config->adjusted_mode.flags &
10063 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10064 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10065
10066 if (!(pipe_config->adjusted_mode.flags &
10067 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10068 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10069
10070 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10071 * plane pixel format and any sink constraints into account. Returns the
10072 * source plane bpp so that dithering can be selected on mismatches
10073 * after encoders and crtc also have had their say. */
10074 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10075 fb, pipe_config);
10076 if (plane_bpp < 0)
10077 goto fail;
10078
10079 /*
10080 * Determine the real pipe dimensions. Note that stereo modes can
10081 * increase the actual pipe size due to the frame doubling and
10082 * insertion of additional space for blanks between the frame. This
10083 * is stored in the crtc timings. We use the requested mode to do this
10084 * computation to clearly distinguish it from the adjusted mode, which
10085 * can be changed by the connectors in the below retry loop.
10086 */
10087 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10088 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10089 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10090
10091 encoder_retry:
10092 /* Ensure the port clock defaults are reset when retrying. */
10093 pipe_config->port_clock = 0;
10094 pipe_config->pixel_multiplier = 1;
10095
10096 /* Fill in default crtc timings, allow encoders to overwrite them. */
10097 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
10098
10099 /* Pass our mode to the connectors and the CRTC to give them a chance to
10100 * adjust it according to limitations or connector properties, and also
10101 * a chance to reject the mode entirely.
10102 */
10103 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10104 base.head) {
10105
10106 if (&encoder->new_crtc->base != crtc)
10107 continue;
10108
10109 if (!(encoder->compute_config(encoder, pipe_config))) {
10110 DRM_DEBUG_KMS("Encoder config failure\n");
10111 goto fail;
10112 }
10113 }
10114
10115 /* Set default port clock if not overwritten by the encoder. Needs to be
10116 * done afterwards in case the encoder adjusts the mode. */
10117 if (!pipe_config->port_clock)
10118 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10119 * pipe_config->pixel_multiplier;
10120
10121 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10122 if (ret < 0) {
10123 DRM_DEBUG_KMS("CRTC fixup failed\n");
10124 goto fail;
10125 }
10126
10127 if (ret == RETRY) {
10128 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10129 ret = -EINVAL;
10130 goto fail;
10131 }
10132
10133 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10134 retry = false;
10135 goto encoder_retry;
10136 }
10137
10138 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10139 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10140 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10141
10142 return pipe_config;
10143 fail:
10144 kfree(pipe_config);
10145 return ERR_PTR(ret);
10146 }
10147
10148 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10149 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10150 static void
10151 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10152 unsigned *prepare_pipes, unsigned *disable_pipes)
10153 {
10154 struct intel_crtc *intel_crtc;
10155 struct drm_device *dev = crtc->dev;
10156 struct intel_encoder *encoder;
10157 struct intel_connector *connector;
10158 struct drm_crtc *tmp_crtc;
10159
10160 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10161
10162 /* Check which crtcs have changed outputs connected to them, these need
10163 * to be part of the prepare_pipes mask. We don't (yet) support global
10164 * modeset across multiple crtcs, so modeset_pipes will only have one
10165 * bit set at most. */
10166 list_for_each_entry(connector, &dev->mode_config.connector_list,
10167 base.head) {
10168 if (connector->base.encoder == &connector->new_encoder->base)
10169 continue;
10170
10171 if (connector->base.encoder) {
10172 tmp_crtc = connector->base.encoder->crtc;
10173
10174 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10175 }
10176
10177 if (connector->new_encoder)
10178 *prepare_pipes |=
10179 1 << connector->new_encoder->new_crtc->pipe;
10180 }
10181
10182 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10183 base.head) {
10184 if (encoder->base.crtc == &encoder->new_crtc->base)
10185 continue;
10186
10187 if (encoder->base.crtc) {
10188 tmp_crtc = encoder->base.crtc;
10189
10190 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10191 }
10192
10193 if (encoder->new_crtc)
10194 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10195 }
10196
10197 /* Check for pipes that will be enabled/disabled ... */
10198 for_each_intel_crtc(dev, intel_crtc) {
10199 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10200 continue;
10201
10202 if (!intel_crtc->new_enabled)
10203 *disable_pipes |= 1 << intel_crtc->pipe;
10204 else
10205 *prepare_pipes |= 1 << intel_crtc->pipe;
10206 }
10207
10208
10209 /* set_mode is also used to update properties on life display pipes. */
10210 intel_crtc = to_intel_crtc(crtc);
10211 if (intel_crtc->new_enabled)
10212 *prepare_pipes |= 1 << intel_crtc->pipe;
10213
10214 /*
10215 * For simplicity do a full modeset on any pipe where the output routing
10216 * changed. We could be more clever, but that would require us to be
10217 * more careful with calling the relevant encoder->mode_set functions.
10218 */
10219 if (*prepare_pipes)
10220 *modeset_pipes = *prepare_pipes;
10221
10222 /* ... and mask these out. */
10223 *modeset_pipes &= ~(*disable_pipes);
10224 *prepare_pipes &= ~(*disable_pipes);
10225
10226 /*
10227 * HACK: We don't (yet) fully support global modesets. intel_set_config
10228 * obies this rule, but the modeset restore mode of
10229 * intel_modeset_setup_hw_state does not.
10230 */
10231 *modeset_pipes &= 1 << intel_crtc->pipe;
10232 *prepare_pipes &= 1 << intel_crtc->pipe;
10233
10234 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10235 *modeset_pipes, *prepare_pipes, *disable_pipes);
10236 }
10237
10238 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10239 {
10240 struct drm_encoder *encoder;
10241 struct drm_device *dev = crtc->dev;
10242
10243 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10244 if (encoder->crtc == crtc)
10245 return true;
10246
10247 return false;
10248 }
10249
10250 static void
10251 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10252 {
10253 struct intel_encoder *intel_encoder;
10254 struct intel_crtc *intel_crtc;
10255 struct drm_connector *connector;
10256
10257 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
10258 base.head) {
10259 if (!intel_encoder->base.crtc)
10260 continue;
10261
10262 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10263
10264 if (prepare_pipes & (1 << intel_crtc->pipe))
10265 intel_encoder->connectors_active = false;
10266 }
10267
10268 intel_modeset_commit_output_state(dev);
10269
10270 /* Double check state. */
10271 for_each_intel_crtc(dev, intel_crtc) {
10272 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10273 WARN_ON(intel_crtc->new_config &&
10274 intel_crtc->new_config != &intel_crtc->config);
10275 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10276 }
10277
10278 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10279 if (!connector->encoder || !connector->encoder->crtc)
10280 continue;
10281
10282 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10283
10284 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10285 struct drm_property *dpms_property =
10286 dev->mode_config.dpms_property;
10287
10288 connector->dpms = DRM_MODE_DPMS_ON;
10289 drm_object_property_set_value(&connector->base,
10290 dpms_property,
10291 DRM_MODE_DPMS_ON);
10292
10293 intel_encoder = to_intel_encoder(connector->encoder);
10294 intel_encoder->connectors_active = true;
10295 }
10296 }
10297
10298 }
10299
10300 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10301 {
10302 int diff;
10303
10304 if (clock1 == clock2)
10305 return true;
10306
10307 if (!clock1 || !clock2)
10308 return false;
10309
10310 diff = abs(clock1 - clock2);
10311
10312 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10313 return true;
10314
10315 return false;
10316 }
10317
10318 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10319 list_for_each_entry((intel_crtc), \
10320 &(dev)->mode_config.crtc_list, \
10321 base.head) \
10322 if (mask & (1 <<(intel_crtc)->pipe))
10323
10324 static bool
10325 intel_pipe_config_compare(struct drm_device *dev,
10326 struct intel_crtc_config *current_config,
10327 struct intel_crtc_config *pipe_config)
10328 {
10329 #define PIPE_CONF_CHECK_X(name) \
10330 if (current_config->name != pipe_config->name) { \
10331 DRM_ERROR("mismatch in " #name " " \
10332 "(expected 0x%08x, found 0x%08x)\n", \
10333 current_config->name, \
10334 pipe_config->name); \
10335 return false; \
10336 }
10337
10338 #define PIPE_CONF_CHECK_I(name) \
10339 if (current_config->name != pipe_config->name) { \
10340 DRM_ERROR("mismatch in " #name " " \
10341 "(expected %i, found %i)\n", \
10342 current_config->name, \
10343 pipe_config->name); \
10344 return false; \
10345 }
10346
10347 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10348 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10349 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10350 "(expected %i, found %i)\n", \
10351 current_config->name & (mask), \
10352 pipe_config->name & (mask)); \
10353 return false; \
10354 }
10355
10356 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10357 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10358 DRM_ERROR("mismatch in " #name " " \
10359 "(expected %i, found %i)\n", \
10360 current_config->name, \
10361 pipe_config->name); \
10362 return false; \
10363 }
10364
10365 #define PIPE_CONF_QUIRK(quirk) \
10366 ((current_config->quirks | pipe_config->quirks) & (quirk))
10367
10368 PIPE_CONF_CHECK_I(cpu_transcoder);
10369
10370 PIPE_CONF_CHECK_I(has_pch_encoder);
10371 PIPE_CONF_CHECK_I(fdi_lanes);
10372 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10373 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10374 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10375 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10376 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10377
10378 PIPE_CONF_CHECK_I(has_dp_encoder);
10379 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10380 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10381 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10382 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10383 PIPE_CONF_CHECK_I(dp_m_n.tu);
10384
10385 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10386 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10387 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10388 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10389 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10390 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10391
10392 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10393 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10394 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10395 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10396 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10397 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10398
10399 PIPE_CONF_CHECK_I(pixel_multiplier);
10400 PIPE_CONF_CHECK_I(has_hdmi_sink);
10401 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10402 IS_VALLEYVIEW(dev))
10403 PIPE_CONF_CHECK_I(limited_color_range);
10404
10405 PIPE_CONF_CHECK_I(has_audio);
10406
10407 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10408 DRM_MODE_FLAG_INTERLACE);
10409
10410 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10411 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10412 DRM_MODE_FLAG_PHSYNC);
10413 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10414 DRM_MODE_FLAG_NHSYNC);
10415 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10416 DRM_MODE_FLAG_PVSYNC);
10417 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10418 DRM_MODE_FLAG_NVSYNC);
10419 }
10420
10421 PIPE_CONF_CHECK_I(pipe_src_w);
10422 PIPE_CONF_CHECK_I(pipe_src_h);
10423
10424 /*
10425 * FIXME: BIOS likes to set up a cloned config with lvds+external
10426 * screen. Since we don't yet re-compute the pipe config when moving
10427 * just the lvds port away to another pipe the sw tracking won't match.
10428 *
10429 * Proper atomic modesets with recomputed global state will fix this.
10430 * Until then just don't check gmch state for inherited modes.
10431 */
10432 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10433 PIPE_CONF_CHECK_I(gmch_pfit.control);
10434 /* pfit ratios are autocomputed by the hw on gen4+ */
10435 if (INTEL_INFO(dev)->gen < 4)
10436 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10437 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10438 }
10439
10440 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10441 if (current_config->pch_pfit.enabled) {
10442 PIPE_CONF_CHECK_I(pch_pfit.pos);
10443 PIPE_CONF_CHECK_I(pch_pfit.size);
10444 }
10445
10446 /* BDW+ don't expose a synchronous way to read the state */
10447 if (IS_HASWELL(dev))
10448 PIPE_CONF_CHECK_I(ips_enabled);
10449
10450 PIPE_CONF_CHECK_I(double_wide);
10451
10452 PIPE_CONF_CHECK_X(ddi_pll_sel);
10453
10454 PIPE_CONF_CHECK_I(shared_dpll);
10455 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10456 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10457 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10458 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10459 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10460
10461 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10462 PIPE_CONF_CHECK_I(pipe_bpp);
10463
10464 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10465 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10466
10467 #undef PIPE_CONF_CHECK_X
10468 #undef PIPE_CONF_CHECK_I
10469 #undef PIPE_CONF_CHECK_FLAGS
10470 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10471 #undef PIPE_CONF_QUIRK
10472
10473 return true;
10474 }
10475
10476 static void
10477 check_connector_state(struct drm_device *dev)
10478 {
10479 struct intel_connector *connector;
10480
10481 list_for_each_entry(connector, &dev->mode_config.connector_list,
10482 base.head) {
10483 /* This also checks the encoder/connector hw state with the
10484 * ->get_hw_state callbacks. */
10485 intel_connector_check_state(connector);
10486
10487 WARN(&connector->new_encoder->base != connector->base.encoder,
10488 "connector's staged encoder doesn't match current encoder\n");
10489 }
10490 }
10491
10492 static void
10493 check_encoder_state(struct drm_device *dev)
10494 {
10495 struct intel_encoder *encoder;
10496 struct intel_connector *connector;
10497
10498 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10499 base.head) {
10500 bool enabled = false;
10501 bool active = false;
10502 enum pipe pipe, tracked_pipe;
10503
10504 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10505 encoder->base.base.id,
10506 encoder->base.name);
10507
10508 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10509 "encoder's stage crtc doesn't match current crtc\n");
10510 WARN(encoder->connectors_active && !encoder->base.crtc,
10511 "encoder's active_connectors set, but no crtc\n");
10512
10513 list_for_each_entry(connector, &dev->mode_config.connector_list,
10514 base.head) {
10515 if (connector->base.encoder != &encoder->base)
10516 continue;
10517 enabled = true;
10518 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10519 active = true;
10520 }
10521 WARN(!!encoder->base.crtc != enabled,
10522 "encoder's enabled state mismatch "
10523 "(expected %i, found %i)\n",
10524 !!encoder->base.crtc, enabled);
10525 WARN(active && !encoder->base.crtc,
10526 "active encoder with no crtc\n");
10527
10528 WARN(encoder->connectors_active != active,
10529 "encoder's computed active state doesn't match tracked active state "
10530 "(expected %i, found %i)\n", active, encoder->connectors_active);
10531
10532 active = encoder->get_hw_state(encoder, &pipe);
10533 WARN(active != encoder->connectors_active,
10534 "encoder's hw state doesn't match sw tracking "
10535 "(expected %i, found %i)\n",
10536 encoder->connectors_active, active);
10537
10538 if (!encoder->base.crtc)
10539 continue;
10540
10541 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10542 WARN(active && pipe != tracked_pipe,
10543 "active encoder's pipe doesn't match"
10544 "(expected %i, found %i)\n",
10545 tracked_pipe, pipe);
10546
10547 }
10548 }
10549
10550 static void
10551 check_crtc_state(struct drm_device *dev)
10552 {
10553 struct drm_i915_private *dev_priv = dev->dev_private;
10554 struct intel_crtc *crtc;
10555 struct intel_encoder *encoder;
10556 struct intel_crtc_config pipe_config;
10557
10558 for_each_intel_crtc(dev, crtc) {
10559 bool enabled = false;
10560 bool active = false;
10561
10562 memset(&pipe_config, 0, sizeof(pipe_config));
10563
10564 DRM_DEBUG_KMS("[CRTC:%d]\n",
10565 crtc->base.base.id);
10566
10567 WARN(crtc->active && !crtc->base.enabled,
10568 "active crtc, but not enabled in sw tracking\n");
10569
10570 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10571 base.head) {
10572 if (encoder->base.crtc != &crtc->base)
10573 continue;
10574 enabled = true;
10575 if (encoder->connectors_active)
10576 active = true;
10577 }
10578
10579 WARN(active != crtc->active,
10580 "crtc's computed active state doesn't match tracked active state "
10581 "(expected %i, found %i)\n", active, crtc->active);
10582 WARN(enabled != crtc->base.enabled,
10583 "crtc's computed enabled state doesn't match tracked enabled state "
10584 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10585
10586 active = dev_priv->display.get_pipe_config(crtc,
10587 &pipe_config);
10588
10589 /* hw state is inconsistent with the pipe A quirk */
10590 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
10591 active = crtc->active;
10592
10593 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10594 base.head) {
10595 enum pipe pipe;
10596 if (encoder->base.crtc != &crtc->base)
10597 continue;
10598 if (encoder->get_hw_state(encoder, &pipe))
10599 encoder->get_config(encoder, &pipe_config);
10600 }
10601
10602 WARN(crtc->active != active,
10603 "crtc active state doesn't match with hw state "
10604 "(expected %i, found %i)\n", crtc->active, active);
10605
10606 if (active &&
10607 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10608 WARN(1, "pipe state doesn't match!\n");
10609 intel_dump_pipe_config(crtc, &pipe_config,
10610 "[hw state]");
10611 intel_dump_pipe_config(crtc, &crtc->config,
10612 "[sw state]");
10613 }
10614 }
10615 }
10616
10617 static void
10618 check_shared_dpll_state(struct drm_device *dev)
10619 {
10620 struct drm_i915_private *dev_priv = dev->dev_private;
10621 struct intel_crtc *crtc;
10622 struct intel_dpll_hw_state dpll_hw_state;
10623 int i;
10624
10625 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10626 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10627 int enabled_crtcs = 0, active_crtcs = 0;
10628 bool active;
10629
10630 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10631
10632 DRM_DEBUG_KMS("%s\n", pll->name);
10633
10634 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10635
10636 WARN(pll->active > pll->refcount,
10637 "more active pll users than references: %i vs %i\n",
10638 pll->active, pll->refcount);
10639 WARN(pll->active && !pll->on,
10640 "pll in active use but not on in sw tracking\n");
10641 WARN(pll->on && !pll->active,
10642 "pll in on but not on in use in sw tracking\n");
10643 WARN(pll->on != active,
10644 "pll on state mismatch (expected %i, found %i)\n",
10645 pll->on, active);
10646
10647 for_each_intel_crtc(dev, crtc) {
10648 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10649 enabled_crtcs++;
10650 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10651 active_crtcs++;
10652 }
10653 WARN(pll->active != active_crtcs,
10654 "pll active crtcs mismatch (expected %i, found %i)\n",
10655 pll->active, active_crtcs);
10656 WARN(pll->refcount != enabled_crtcs,
10657 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10658 pll->refcount, enabled_crtcs);
10659
10660 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10661 sizeof(dpll_hw_state)),
10662 "pll hw state mismatch\n");
10663 }
10664 }
10665
10666 void
10667 intel_modeset_check_state(struct drm_device *dev)
10668 {
10669 check_connector_state(dev);
10670 check_encoder_state(dev);
10671 check_crtc_state(dev);
10672 check_shared_dpll_state(dev);
10673 }
10674
10675 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10676 int dotclock)
10677 {
10678 /*
10679 * FDI already provided one idea for the dotclock.
10680 * Yell if the encoder disagrees.
10681 */
10682 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10683 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10684 pipe_config->adjusted_mode.crtc_clock, dotclock);
10685 }
10686
10687 static void update_scanline_offset(struct intel_crtc *crtc)
10688 {
10689 struct drm_device *dev = crtc->base.dev;
10690
10691 /*
10692 * The scanline counter increments at the leading edge of hsync.
10693 *
10694 * On most platforms it starts counting from vtotal-1 on the
10695 * first active line. That means the scanline counter value is
10696 * always one less than what we would expect. Ie. just after
10697 * start of vblank, which also occurs at start of hsync (on the
10698 * last active line), the scanline counter will read vblank_start-1.
10699 *
10700 * On gen2 the scanline counter starts counting from 1 instead
10701 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10702 * to keep the value positive), instead of adding one.
10703 *
10704 * On HSW+ the behaviour of the scanline counter depends on the output
10705 * type. For DP ports it behaves like most other platforms, but on HDMI
10706 * there's an extra 1 line difference. So we need to add two instead of
10707 * one to the value.
10708 */
10709 if (IS_GEN2(dev)) {
10710 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10711 int vtotal;
10712
10713 vtotal = mode->crtc_vtotal;
10714 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10715 vtotal /= 2;
10716
10717 crtc->scanline_offset = vtotal - 1;
10718 } else if (HAS_DDI(dev) &&
10719 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
10720 crtc->scanline_offset = 2;
10721 } else
10722 crtc->scanline_offset = 1;
10723 }
10724
10725 static int __intel_set_mode(struct drm_crtc *crtc,
10726 struct drm_display_mode *mode,
10727 int x, int y, struct drm_framebuffer *fb)
10728 {
10729 struct drm_device *dev = crtc->dev;
10730 struct drm_i915_private *dev_priv = dev->dev_private;
10731 struct drm_display_mode *saved_mode;
10732 struct intel_crtc_config *pipe_config = NULL;
10733 struct intel_crtc *intel_crtc;
10734 unsigned disable_pipes, prepare_pipes, modeset_pipes;
10735 int ret = 0;
10736
10737 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10738 if (!saved_mode)
10739 return -ENOMEM;
10740
10741 intel_modeset_affected_pipes(crtc, &modeset_pipes,
10742 &prepare_pipes, &disable_pipes);
10743
10744 *saved_mode = crtc->mode;
10745
10746 /* Hack: Because we don't (yet) support global modeset on multiple
10747 * crtcs, we don't keep track of the new mode for more than one crtc.
10748 * Hence simply check whether any bit is set in modeset_pipes in all the
10749 * pieces of code that are not yet converted to deal with mutliple crtcs
10750 * changing their mode at the same time. */
10751 if (modeset_pipes) {
10752 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10753 if (IS_ERR(pipe_config)) {
10754 ret = PTR_ERR(pipe_config);
10755 pipe_config = NULL;
10756
10757 goto out;
10758 }
10759 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10760 "[modeset]");
10761 to_intel_crtc(crtc)->new_config = pipe_config;
10762 }
10763
10764 /*
10765 * See if the config requires any additional preparation, e.g.
10766 * to adjust global state with pipes off. We need to do this
10767 * here so we can get the modeset_pipe updated config for the new
10768 * mode set on this crtc. For other crtcs we need to use the
10769 * adjusted_mode bits in the crtc directly.
10770 */
10771 if (IS_VALLEYVIEW(dev)) {
10772 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10773
10774 /* may have added more to prepare_pipes than we should */
10775 prepare_pipes &= ~disable_pipes;
10776 }
10777
10778 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10779 intel_crtc_disable(&intel_crtc->base);
10780
10781 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10782 if (intel_crtc->base.enabled)
10783 dev_priv->display.crtc_disable(&intel_crtc->base);
10784 }
10785
10786 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10787 * to set it here already despite that we pass it down the callchain.
10788 */
10789 if (modeset_pipes) {
10790 crtc->mode = *mode;
10791 /* mode_set/enable/disable functions rely on a correct pipe
10792 * config. */
10793 to_intel_crtc(crtc)->config = *pipe_config;
10794 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10795
10796 /*
10797 * Calculate and store various constants which
10798 * are later needed by vblank and swap-completion
10799 * timestamping. They are derived from true hwmode.
10800 */
10801 drm_calc_timestamping_constants(crtc,
10802 &pipe_config->adjusted_mode);
10803 }
10804
10805 /* Only after disabling all output pipelines that will be changed can we
10806 * update the the output configuration. */
10807 intel_modeset_update_state(dev, prepare_pipes);
10808
10809 if (dev_priv->display.modeset_global_resources)
10810 dev_priv->display.modeset_global_resources(dev);
10811
10812 /* Set up the DPLL and any encoders state that needs to adjust or depend
10813 * on the DPLL.
10814 */
10815 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10816 struct drm_framebuffer *old_fb = crtc->primary->fb;
10817 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
10818 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10819
10820 mutex_lock(&dev->struct_mutex);
10821 ret = intel_pin_and_fence_fb_obj(dev,
10822 obj,
10823 NULL);
10824 if (ret != 0) {
10825 DRM_ERROR("pin & fence failed\n");
10826 mutex_unlock(&dev->struct_mutex);
10827 goto done;
10828 }
10829 if (old_fb)
10830 intel_unpin_fb_obj(old_obj);
10831 i915_gem_track_fb(old_obj, obj,
10832 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
10833 mutex_unlock(&dev->struct_mutex);
10834
10835 crtc->primary->fb = fb;
10836 crtc->x = x;
10837 crtc->y = y;
10838
10839 ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
10840 x, y, fb);
10841 if (ret)
10842 goto done;
10843 }
10844
10845 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10846 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10847 update_scanline_offset(intel_crtc);
10848
10849 dev_priv->display.crtc_enable(&intel_crtc->base);
10850 }
10851
10852 /* FIXME: add subpixel order */
10853 done:
10854 if (ret && crtc->enabled)
10855 crtc->mode = *saved_mode;
10856
10857 out:
10858 kfree(pipe_config);
10859 kfree(saved_mode);
10860 return ret;
10861 }
10862
10863 static int intel_set_mode(struct drm_crtc *crtc,
10864 struct drm_display_mode *mode,
10865 int x, int y, struct drm_framebuffer *fb)
10866 {
10867 int ret;
10868
10869 ret = __intel_set_mode(crtc, mode, x, y, fb);
10870
10871 if (ret == 0)
10872 intel_modeset_check_state(crtc->dev);
10873
10874 return ret;
10875 }
10876
10877 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10878 {
10879 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10880 }
10881
10882 #undef for_each_intel_crtc_masked
10883
10884 static void intel_set_config_free(struct intel_set_config *config)
10885 {
10886 if (!config)
10887 return;
10888
10889 kfree(config->save_connector_encoders);
10890 kfree(config->save_encoder_crtcs);
10891 kfree(config->save_crtc_enabled);
10892 kfree(config);
10893 }
10894
10895 static int intel_set_config_save_state(struct drm_device *dev,
10896 struct intel_set_config *config)
10897 {
10898 struct drm_crtc *crtc;
10899 struct drm_encoder *encoder;
10900 struct drm_connector *connector;
10901 int count;
10902
10903 config->save_crtc_enabled =
10904 kcalloc(dev->mode_config.num_crtc,
10905 sizeof(bool), GFP_KERNEL);
10906 if (!config->save_crtc_enabled)
10907 return -ENOMEM;
10908
10909 config->save_encoder_crtcs =
10910 kcalloc(dev->mode_config.num_encoder,
10911 sizeof(struct drm_crtc *), GFP_KERNEL);
10912 if (!config->save_encoder_crtcs)
10913 return -ENOMEM;
10914
10915 config->save_connector_encoders =
10916 kcalloc(dev->mode_config.num_connector,
10917 sizeof(struct drm_encoder *), GFP_KERNEL);
10918 if (!config->save_connector_encoders)
10919 return -ENOMEM;
10920
10921 /* Copy data. Note that driver private data is not affected.
10922 * Should anything bad happen only the expected state is
10923 * restored, not the drivers personal bookkeeping.
10924 */
10925 count = 0;
10926 for_each_crtc(dev, crtc) {
10927 config->save_crtc_enabled[count++] = crtc->enabled;
10928 }
10929
10930 count = 0;
10931 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10932 config->save_encoder_crtcs[count++] = encoder->crtc;
10933 }
10934
10935 count = 0;
10936 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10937 config->save_connector_encoders[count++] = connector->encoder;
10938 }
10939
10940 return 0;
10941 }
10942
10943 static void intel_set_config_restore_state(struct drm_device *dev,
10944 struct intel_set_config *config)
10945 {
10946 struct intel_crtc *crtc;
10947 struct intel_encoder *encoder;
10948 struct intel_connector *connector;
10949 int count;
10950
10951 count = 0;
10952 for_each_intel_crtc(dev, crtc) {
10953 crtc->new_enabled = config->save_crtc_enabled[count++];
10954
10955 if (crtc->new_enabled)
10956 crtc->new_config = &crtc->config;
10957 else
10958 crtc->new_config = NULL;
10959 }
10960
10961 count = 0;
10962 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10963 encoder->new_crtc =
10964 to_intel_crtc(config->save_encoder_crtcs[count++]);
10965 }
10966
10967 count = 0;
10968 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10969 connector->new_encoder =
10970 to_intel_encoder(config->save_connector_encoders[count++]);
10971 }
10972 }
10973
10974 static bool
10975 is_crtc_connector_off(struct drm_mode_set *set)
10976 {
10977 int i;
10978
10979 if (set->num_connectors == 0)
10980 return false;
10981
10982 if (WARN_ON(set->connectors == NULL))
10983 return false;
10984
10985 for (i = 0; i < set->num_connectors; i++)
10986 if (set->connectors[i]->encoder &&
10987 set->connectors[i]->encoder->crtc == set->crtc &&
10988 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
10989 return true;
10990
10991 return false;
10992 }
10993
10994 static void
10995 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
10996 struct intel_set_config *config)
10997 {
10998
10999 /* We should be able to check here if the fb has the same properties
11000 * and then just flip_or_move it */
11001 if (is_crtc_connector_off(set)) {
11002 config->mode_changed = true;
11003 } else if (set->crtc->primary->fb != set->fb) {
11004 /*
11005 * If we have no fb, we can only flip as long as the crtc is
11006 * active, otherwise we need a full mode set. The crtc may
11007 * be active if we've only disabled the primary plane, or
11008 * in fastboot situations.
11009 */
11010 if (set->crtc->primary->fb == NULL) {
11011 struct intel_crtc *intel_crtc =
11012 to_intel_crtc(set->crtc);
11013
11014 if (intel_crtc->active) {
11015 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11016 config->fb_changed = true;
11017 } else {
11018 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11019 config->mode_changed = true;
11020 }
11021 } else if (set->fb == NULL) {
11022 config->mode_changed = true;
11023 } else if (set->fb->pixel_format !=
11024 set->crtc->primary->fb->pixel_format) {
11025 config->mode_changed = true;
11026 } else {
11027 config->fb_changed = true;
11028 }
11029 }
11030
11031 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11032 config->fb_changed = true;
11033
11034 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11035 DRM_DEBUG_KMS("modes are different, full mode set\n");
11036 drm_mode_debug_printmodeline(&set->crtc->mode);
11037 drm_mode_debug_printmodeline(set->mode);
11038 config->mode_changed = true;
11039 }
11040
11041 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11042 set->crtc->base.id, config->mode_changed, config->fb_changed);
11043 }
11044
11045 static int
11046 intel_modeset_stage_output_state(struct drm_device *dev,
11047 struct drm_mode_set *set,
11048 struct intel_set_config *config)
11049 {
11050 struct intel_connector *connector;
11051 struct intel_encoder *encoder;
11052 struct intel_crtc *crtc;
11053 int ro;
11054
11055 /* The upper layers ensure that we either disable a crtc or have a list
11056 * of connectors. For paranoia, double-check this. */
11057 WARN_ON(!set->fb && (set->num_connectors != 0));
11058 WARN_ON(set->fb && (set->num_connectors == 0));
11059
11060 list_for_each_entry(connector, &dev->mode_config.connector_list,
11061 base.head) {
11062 /* Otherwise traverse passed in connector list and get encoders
11063 * for them. */
11064 for (ro = 0; ro < set->num_connectors; ro++) {
11065 if (set->connectors[ro] == &connector->base) {
11066 connector->new_encoder = connector->encoder;
11067 break;
11068 }
11069 }
11070
11071 /* If we disable the crtc, disable all its connectors. Also, if
11072 * the connector is on the changing crtc but not on the new
11073 * connector list, disable it. */
11074 if ((!set->fb || ro == set->num_connectors) &&
11075 connector->base.encoder &&
11076 connector->base.encoder->crtc == set->crtc) {
11077 connector->new_encoder = NULL;
11078
11079 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11080 connector->base.base.id,
11081 connector->base.name);
11082 }
11083
11084
11085 if (&connector->new_encoder->base != connector->base.encoder) {
11086 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11087 config->mode_changed = true;
11088 }
11089 }
11090 /* connector->new_encoder is now updated for all connectors. */
11091
11092 /* Update crtc of enabled connectors. */
11093 list_for_each_entry(connector, &dev->mode_config.connector_list,
11094 base.head) {
11095 struct drm_crtc *new_crtc;
11096
11097 if (!connector->new_encoder)
11098 continue;
11099
11100 new_crtc = connector->new_encoder->base.crtc;
11101
11102 for (ro = 0; ro < set->num_connectors; ro++) {
11103 if (set->connectors[ro] == &connector->base)
11104 new_crtc = set->crtc;
11105 }
11106
11107 /* Make sure the new CRTC will work with the encoder */
11108 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11109 new_crtc)) {
11110 return -EINVAL;
11111 }
11112 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
11113
11114 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11115 connector->base.base.id,
11116 connector->base.name,
11117 new_crtc->base.id);
11118 }
11119
11120 /* Check for any encoders that needs to be disabled. */
11121 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11122 base.head) {
11123 int num_connectors = 0;
11124 list_for_each_entry(connector,
11125 &dev->mode_config.connector_list,
11126 base.head) {
11127 if (connector->new_encoder == encoder) {
11128 WARN_ON(!connector->new_encoder->new_crtc);
11129 num_connectors++;
11130 }
11131 }
11132
11133 if (num_connectors == 0)
11134 encoder->new_crtc = NULL;
11135 else if (num_connectors > 1)
11136 return -EINVAL;
11137
11138 /* Only now check for crtc changes so we don't miss encoders
11139 * that will be disabled. */
11140 if (&encoder->new_crtc->base != encoder->base.crtc) {
11141 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11142 config->mode_changed = true;
11143 }
11144 }
11145 /* Now we've also updated encoder->new_crtc for all encoders. */
11146
11147 for_each_intel_crtc(dev, crtc) {
11148 crtc->new_enabled = false;
11149
11150 list_for_each_entry(encoder,
11151 &dev->mode_config.encoder_list,
11152 base.head) {
11153 if (encoder->new_crtc == crtc) {
11154 crtc->new_enabled = true;
11155 break;
11156 }
11157 }
11158
11159 if (crtc->new_enabled != crtc->base.enabled) {
11160 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11161 crtc->new_enabled ? "en" : "dis");
11162 config->mode_changed = true;
11163 }
11164
11165 if (crtc->new_enabled)
11166 crtc->new_config = &crtc->config;
11167 else
11168 crtc->new_config = NULL;
11169 }
11170
11171 return 0;
11172 }
11173
11174 static void disable_crtc_nofb(struct intel_crtc *crtc)
11175 {
11176 struct drm_device *dev = crtc->base.dev;
11177 struct intel_encoder *encoder;
11178 struct intel_connector *connector;
11179
11180 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11181 pipe_name(crtc->pipe));
11182
11183 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11184 if (connector->new_encoder &&
11185 connector->new_encoder->new_crtc == crtc)
11186 connector->new_encoder = NULL;
11187 }
11188
11189 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
11190 if (encoder->new_crtc == crtc)
11191 encoder->new_crtc = NULL;
11192 }
11193
11194 crtc->new_enabled = false;
11195 crtc->new_config = NULL;
11196 }
11197
11198 static int intel_crtc_set_config(struct drm_mode_set *set)
11199 {
11200 struct drm_device *dev;
11201 struct drm_mode_set save_set;
11202 struct intel_set_config *config;
11203 int ret;
11204
11205 BUG_ON(!set);
11206 BUG_ON(!set->crtc);
11207 BUG_ON(!set->crtc->helper_private);
11208
11209 /* Enforce sane interface api - has been abused by the fb helper. */
11210 BUG_ON(!set->mode && set->fb);
11211 BUG_ON(set->fb && set->num_connectors == 0);
11212
11213 if (set->fb) {
11214 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11215 set->crtc->base.id, set->fb->base.id,
11216 (int)set->num_connectors, set->x, set->y);
11217 } else {
11218 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11219 }
11220
11221 dev = set->crtc->dev;
11222
11223 ret = -ENOMEM;
11224 config = kzalloc(sizeof(*config), GFP_KERNEL);
11225 if (!config)
11226 goto out_config;
11227
11228 ret = intel_set_config_save_state(dev, config);
11229 if (ret)
11230 goto out_config;
11231
11232 save_set.crtc = set->crtc;
11233 save_set.mode = &set->crtc->mode;
11234 save_set.x = set->crtc->x;
11235 save_set.y = set->crtc->y;
11236 save_set.fb = set->crtc->primary->fb;
11237
11238 /* Compute whether we need a full modeset, only an fb base update or no
11239 * change at all. In the future we might also check whether only the
11240 * mode changed, e.g. for LVDS where we only change the panel fitter in
11241 * such cases. */
11242 intel_set_config_compute_mode_changes(set, config);
11243
11244 ret = intel_modeset_stage_output_state(dev, set, config);
11245 if (ret)
11246 goto fail;
11247
11248 if (config->mode_changed) {
11249 ret = intel_set_mode(set->crtc, set->mode,
11250 set->x, set->y, set->fb);
11251 } else if (config->fb_changed) {
11252 struct drm_i915_private *dev_priv = dev->dev_private;
11253 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11254
11255 intel_crtc_wait_for_pending_flips(set->crtc);
11256
11257 ret = intel_pipe_set_base(set->crtc,
11258 set->x, set->y, set->fb);
11259
11260 /*
11261 * We need to make sure the primary plane is re-enabled if it
11262 * has previously been turned off.
11263 */
11264 if (!intel_crtc->primary_enabled && ret == 0) {
11265 WARN_ON(!intel_crtc->active);
11266 intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane,
11267 intel_crtc->pipe);
11268 }
11269
11270 /*
11271 * In the fastboot case this may be our only check of the
11272 * state after boot. It would be better to only do it on
11273 * the first update, but we don't have a nice way of doing that
11274 * (and really, set_config isn't used much for high freq page
11275 * flipping, so increasing its cost here shouldn't be a big
11276 * deal).
11277 */
11278 if (i915.fastboot && ret == 0)
11279 intel_modeset_check_state(set->crtc->dev);
11280 }
11281
11282 if (ret) {
11283 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11284 set->crtc->base.id, ret);
11285 fail:
11286 intel_set_config_restore_state(dev, config);
11287
11288 /*
11289 * HACK: if the pipe was on, but we didn't have a framebuffer,
11290 * force the pipe off to avoid oopsing in the modeset code
11291 * due to fb==NULL. This should only happen during boot since
11292 * we don't yet reconstruct the FB from the hardware state.
11293 */
11294 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11295 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11296
11297 /* Try to restore the config */
11298 if (config->mode_changed &&
11299 intel_set_mode(save_set.crtc, save_set.mode,
11300 save_set.x, save_set.y, save_set.fb))
11301 DRM_ERROR("failed to restore config after modeset failure\n");
11302 }
11303
11304 out_config:
11305 intel_set_config_free(config);
11306 return ret;
11307 }
11308
11309 static const struct drm_crtc_funcs intel_crtc_funcs = {
11310 .gamma_set = intel_crtc_gamma_set,
11311 .set_config = intel_crtc_set_config,
11312 .destroy = intel_crtc_destroy,
11313 .page_flip = intel_crtc_page_flip,
11314 };
11315
11316 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11317 struct intel_shared_dpll *pll,
11318 struct intel_dpll_hw_state *hw_state)
11319 {
11320 uint32_t val;
11321
11322 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS))
11323 return false;
11324
11325 val = I915_READ(PCH_DPLL(pll->id));
11326 hw_state->dpll = val;
11327 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11328 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11329
11330 return val & DPLL_VCO_ENABLE;
11331 }
11332
11333 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11334 struct intel_shared_dpll *pll)
11335 {
11336 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
11337 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
11338 }
11339
11340 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11341 struct intel_shared_dpll *pll)
11342 {
11343 /* PCH refclock must be enabled first */
11344 ibx_assert_pch_refclk_enabled(dev_priv);
11345
11346 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11347
11348 /* Wait for the clocks to stabilize. */
11349 POSTING_READ(PCH_DPLL(pll->id));
11350 udelay(150);
11351
11352 /* The pixel multiplier can only be updated once the
11353 * DPLL is enabled and the clocks are stable.
11354 *
11355 * So write it again.
11356 */
11357 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11358 POSTING_READ(PCH_DPLL(pll->id));
11359 udelay(200);
11360 }
11361
11362 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11363 struct intel_shared_dpll *pll)
11364 {
11365 struct drm_device *dev = dev_priv->dev;
11366 struct intel_crtc *crtc;
11367
11368 /* Make sure no transcoder isn't still depending on us. */
11369 for_each_intel_crtc(dev, crtc) {
11370 if (intel_crtc_to_shared_dpll(crtc) == pll)
11371 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11372 }
11373
11374 I915_WRITE(PCH_DPLL(pll->id), 0);
11375 POSTING_READ(PCH_DPLL(pll->id));
11376 udelay(200);
11377 }
11378
11379 static char *ibx_pch_dpll_names[] = {
11380 "PCH DPLL A",
11381 "PCH DPLL B",
11382 };
11383
11384 static void ibx_pch_dpll_init(struct drm_device *dev)
11385 {
11386 struct drm_i915_private *dev_priv = dev->dev_private;
11387 int i;
11388
11389 dev_priv->num_shared_dpll = 2;
11390
11391 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11392 dev_priv->shared_dplls[i].id = i;
11393 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11394 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11395 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11396 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11397 dev_priv->shared_dplls[i].get_hw_state =
11398 ibx_pch_dpll_get_hw_state;
11399 }
11400 }
11401
11402 static void intel_shared_dpll_init(struct drm_device *dev)
11403 {
11404 struct drm_i915_private *dev_priv = dev->dev_private;
11405
11406 if (HAS_DDI(dev))
11407 intel_ddi_pll_init(dev);
11408 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11409 ibx_pch_dpll_init(dev);
11410 else
11411 dev_priv->num_shared_dpll = 0;
11412
11413 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11414 }
11415
11416 static int
11417 intel_primary_plane_disable(struct drm_plane *plane)
11418 {
11419 struct drm_device *dev = plane->dev;
11420 struct drm_i915_private *dev_priv = dev->dev_private;
11421 struct intel_plane *intel_plane = to_intel_plane(plane);
11422 struct intel_crtc *intel_crtc;
11423
11424 if (!plane->fb)
11425 return 0;
11426
11427 BUG_ON(!plane->crtc);
11428
11429 intel_crtc = to_intel_crtc(plane->crtc);
11430
11431 /*
11432 * Even though we checked plane->fb above, it's still possible that
11433 * the primary plane has been implicitly disabled because the crtc
11434 * coordinates given weren't visible, or because we detected
11435 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11436 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11437 * In either case, we need to unpin the FB and let the fb pointer get
11438 * updated, but otherwise we don't need to touch the hardware.
11439 */
11440 if (!intel_crtc->primary_enabled)
11441 goto disable_unpin;
11442
11443 intel_crtc_wait_for_pending_flips(plane->crtc);
11444 intel_disable_primary_hw_plane(dev_priv, intel_plane->plane,
11445 intel_plane->pipe);
11446 disable_unpin:
11447 mutex_lock(&dev->struct_mutex);
11448 i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
11449 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11450 intel_unpin_fb_obj(intel_fb_obj(plane->fb));
11451 mutex_unlock(&dev->struct_mutex);
11452 plane->fb = NULL;
11453
11454 return 0;
11455 }
11456
11457 static int
11458 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11459 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11460 unsigned int crtc_w, unsigned int crtc_h,
11461 uint32_t src_x, uint32_t src_y,
11462 uint32_t src_w, uint32_t src_h)
11463 {
11464 struct drm_device *dev = crtc->dev;
11465 struct drm_i915_private *dev_priv = dev->dev_private;
11466 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11467 struct intel_plane *intel_plane = to_intel_plane(plane);
11468 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11469 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11470 struct drm_rect dest = {
11471 /* integer pixels */
11472 .x1 = crtc_x,
11473 .y1 = crtc_y,
11474 .x2 = crtc_x + crtc_w,
11475 .y2 = crtc_y + crtc_h,
11476 };
11477 struct drm_rect src = {
11478 /* 16.16 fixed point */
11479 .x1 = src_x,
11480 .y1 = src_y,
11481 .x2 = src_x + src_w,
11482 .y2 = src_y + src_h,
11483 };
11484 const struct drm_rect clip = {
11485 /* integer pixels */
11486 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
11487 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
11488 };
11489 bool visible;
11490 int ret;
11491
11492 ret = drm_plane_helper_check_update(plane, crtc, fb,
11493 &src, &dest, &clip,
11494 DRM_PLANE_HELPER_NO_SCALING,
11495 DRM_PLANE_HELPER_NO_SCALING,
11496 false, true, &visible);
11497
11498 if (ret)
11499 return ret;
11500
11501 /*
11502 * If the CRTC isn't enabled, we're just pinning the framebuffer,
11503 * updating the fb pointer, and returning without touching the
11504 * hardware. This allows us to later do a drmModeSetCrtc with fb=-1 to
11505 * turn on the display with all planes setup as desired.
11506 */
11507 if (!crtc->enabled) {
11508 mutex_lock(&dev->struct_mutex);
11509
11510 /*
11511 * If we already called setplane while the crtc was disabled,
11512 * we may have an fb pinned; unpin it.
11513 */
11514 if (plane->fb)
11515 intel_unpin_fb_obj(old_obj);
11516
11517 i915_gem_track_fb(old_obj, obj,
11518 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11519
11520 /* Pin and return without programming hardware */
11521 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11522 mutex_unlock(&dev->struct_mutex);
11523
11524 return ret;
11525 }
11526
11527 intel_crtc_wait_for_pending_flips(crtc);
11528
11529 /*
11530 * If clipping results in a non-visible primary plane, we'll disable
11531 * the primary plane. Note that this is a bit different than what
11532 * happens if userspace explicitly disables the plane by passing fb=0
11533 * because plane->fb still gets set and pinned.
11534 */
11535 if (!visible) {
11536 mutex_lock(&dev->struct_mutex);
11537
11538 /*
11539 * Try to pin the new fb first so that we can bail out if we
11540 * fail.
11541 */
11542 if (plane->fb != fb) {
11543 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11544 if (ret) {
11545 mutex_unlock(&dev->struct_mutex);
11546 return ret;
11547 }
11548 }
11549
11550 i915_gem_track_fb(old_obj, obj,
11551 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11552
11553 if (intel_crtc->primary_enabled)
11554 intel_disable_primary_hw_plane(dev_priv,
11555 intel_plane->plane,
11556 intel_plane->pipe);
11557
11558
11559 if (plane->fb != fb)
11560 if (plane->fb)
11561 intel_unpin_fb_obj(old_obj);
11562
11563 mutex_unlock(&dev->struct_mutex);
11564
11565 return 0;
11566 }
11567
11568 ret = intel_pipe_set_base(crtc, src.x1, src.y1, fb);
11569 if (ret)
11570 return ret;
11571
11572 if (!intel_crtc->primary_enabled)
11573 intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane,
11574 intel_crtc->pipe);
11575
11576 return 0;
11577 }
11578
11579 /* Common destruction function for both primary and cursor planes */
11580 static void intel_plane_destroy(struct drm_plane *plane)
11581 {
11582 struct intel_plane *intel_plane = to_intel_plane(plane);
11583 drm_plane_cleanup(plane);
11584 kfree(intel_plane);
11585 }
11586
11587 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11588 .update_plane = intel_primary_plane_setplane,
11589 .disable_plane = intel_primary_plane_disable,
11590 .destroy = intel_plane_destroy,
11591 };
11592
11593 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11594 int pipe)
11595 {
11596 struct intel_plane *primary;
11597 const uint32_t *intel_primary_formats;
11598 int num_formats;
11599
11600 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11601 if (primary == NULL)
11602 return NULL;
11603
11604 primary->can_scale = false;
11605 primary->max_downscale = 1;
11606 primary->pipe = pipe;
11607 primary->plane = pipe;
11608 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11609 primary->plane = !pipe;
11610
11611 if (INTEL_INFO(dev)->gen <= 3) {
11612 intel_primary_formats = intel_primary_formats_gen2;
11613 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11614 } else {
11615 intel_primary_formats = intel_primary_formats_gen4;
11616 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11617 }
11618
11619 drm_universal_plane_init(dev, &primary->base, 0,
11620 &intel_primary_plane_funcs,
11621 intel_primary_formats, num_formats,
11622 DRM_PLANE_TYPE_PRIMARY);
11623 return &primary->base;
11624 }
11625
11626 static int
11627 intel_cursor_plane_disable(struct drm_plane *plane)
11628 {
11629 if (!plane->fb)
11630 return 0;
11631
11632 BUG_ON(!plane->crtc);
11633
11634 return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
11635 }
11636
11637 static int
11638 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
11639 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11640 unsigned int crtc_w, unsigned int crtc_h,
11641 uint32_t src_x, uint32_t src_y,
11642 uint32_t src_w, uint32_t src_h)
11643 {
11644 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11645 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11646 struct drm_i915_gem_object *obj = intel_fb->obj;
11647 struct drm_rect dest = {
11648 /* integer pixels */
11649 .x1 = crtc_x,
11650 .y1 = crtc_y,
11651 .x2 = crtc_x + crtc_w,
11652 .y2 = crtc_y + crtc_h,
11653 };
11654 struct drm_rect src = {
11655 /* 16.16 fixed point */
11656 .x1 = src_x,
11657 .y1 = src_y,
11658 .x2 = src_x + src_w,
11659 .y2 = src_y + src_h,
11660 };
11661 const struct drm_rect clip = {
11662 /* integer pixels */
11663 .x2 = intel_crtc->config.pipe_src_w,
11664 .y2 = intel_crtc->config.pipe_src_h,
11665 };
11666 bool visible;
11667 int ret;
11668
11669 ret = drm_plane_helper_check_update(plane, crtc, fb,
11670 &src, &dest, &clip,
11671 DRM_PLANE_HELPER_NO_SCALING,
11672 DRM_PLANE_HELPER_NO_SCALING,
11673 true, true, &visible);
11674 if (ret)
11675 return ret;
11676
11677 crtc->cursor_x = crtc_x;
11678 crtc->cursor_y = crtc_y;
11679 if (fb != crtc->cursor->fb) {
11680 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
11681 } else {
11682 intel_crtc_update_cursor(crtc, visible);
11683 return 0;
11684 }
11685 }
11686 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
11687 .update_plane = intel_cursor_plane_update,
11688 .disable_plane = intel_cursor_plane_disable,
11689 .destroy = intel_plane_destroy,
11690 };
11691
11692 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
11693 int pipe)
11694 {
11695 struct intel_plane *cursor;
11696
11697 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
11698 if (cursor == NULL)
11699 return NULL;
11700
11701 cursor->can_scale = false;
11702 cursor->max_downscale = 1;
11703 cursor->pipe = pipe;
11704 cursor->plane = pipe;
11705
11706 drm_universal_plane_init(dev, &cursor->base, 0,
11707 &intel_cursor_plane_funcs,
11708 intel_cursor_formats,
11709 ARRAY_SIZE(intel_cursor_formats),
11710 DRM_PLANE_TYPE_CURSOR);
11711 return &cursor->base;
11712 }
11713
11714 static void intel_crtc_init(struct drm_device *dev, int pipe)
11715 {
11716 struct drm_i915_private *dev_priv = dev->dev_private;
11717 struct intel_crtc *intel_crtc;
11718 struct drm_plane *primary = NULL;
11719 struct drm_plane *cursor = NULL;
11720 int i, ret;
11721
11722 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
11723 if (intel_crtc == NULL)
11724 return;
11725
11726 primary = intel_primary_plane_create(dev, pipe);
11727 if (!primary)
11728 goto fail;
11729
11730 cursor = intel_cursor_plane_create(dev, pipe);
11731 if (!cursor)
11732 goto fail;
11733
11734 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
11735 cursor, &intel_crtc_funcs);
11736 if (ret)
11737 goto fail;
11738
11739 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
11740 for (i = 0; i < 256; i++) {
11741 intel_crtc->lut_r[i] = i;
11742 intel_crtc->lut_g[i] = i;
11743 intel_crtc->lut_b[i] = i;
11744 }
11745
11746 /*
11747 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
11748 * is hooked to pipe B. Hence we want plane A feeding pipe B.
11749 */
11750 intel_crtc->pipe = pipe;
11751 intel_crtc->plane = pipe;
11752 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
11753 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
11754 intel_crtc->plane = !pipe;
11755 }
11756
11757 intel_crtc->cursor_base = ~0;
11758 intel_crtc->cursor_cntl = ~0;
11759
11760 init_waitqueue_head(&intel_crtc->vbl_wait);
11761
11762 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
11763 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
11764 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
11765 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
11766
11767 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
11768
11769 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
11770 return;
11771
11772 fail:
11773 if (primary)
11774 drm_plane_cleanup(primary);
11775 if (cursor)
11776 drm_plane_cleanup(cursor);
11777 kfree(intel_crtc);
11778 }
11779
11780 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
11781 {
11782 struct drm_encoder *encoder = connector->base.encoder;
11783 struct drm_device *dev = connector->base.dev;
11784
11785 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
11786
11787 if (!encoder)
11788 return INVALID_PIPE;
11789
11790 return to_intel_crtc(encoder->crtc)->pipe;
11791 }
11792
11793 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
11794 struct drm_file *file)
11795 {
11796 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
11797 struct drm_mode_object *drmmode_obj;
11798 struct intel_crtc *crtc;
11799
11800 if (!drm_core_check_feature(dev, DRIVER_MODESET))
11801 return -ENODEV;
11802
11803 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
11804 DRM_MODE_OBJECT_CRTC);
11805
11806 if (!drmmode_obj) {
11807 DRM_ERROR("no such CRTC id\n");
11808 return -ENOENT;
11809 }
11810
11811 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
11812 pipe_from_crtc_id->pipe = crtc->pipe;
11813
11814 return 0;
11815 }
11816
11817 static int intel_encoder_clones(struct intel_encoder *encoder)
11818 {
11819 struct drm_device *dev = encoder->base.dev;
11820 struct intel_encoder *source_encoder;
11821 int index_mask = 0;
11822 int entry = 0;
11823
11824 list_for_each_entry(source_encoder,
11825 &dev->mode_config.encoder_list, base.head) {
11826 if (encoders_cloneable(encoder, source_encoder))
11827 index_mask |= (1 << entry);
11828
11829 entry++;
11830 }
11831
11832 return index_mask;
11833 }
11834
11835 static bool has_edp_a(struct drm_device *dev)
11836 {
11837 struct drm_i915_private *dev_priv = dev->dev_private;
11838
11839 if (!IS_MOBILE(dev))
11840 return false;
11841
11842 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
11843 return false;
11844
11845 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
11846 return false;
11847
11848 return true;
11849 }
11850
11851 const char *intel_output_name(int output)
11852 {
11853 static const char *names[] = {
11854 [INTEL_OUTPUT_UNUSED] = "Unused",
11855 [INTEL_OUTPUT_ANALOG] = "Analog",
11856 [INTEL_OUTPUT_DVO] = "DVO",
11857 [INTEL_OUTPUT_SDVO] = "SDVO",
11858 [INTEL_OUTPUT_LVDS] = "LVDS",
11859 [INTEL_OUTPUT_TVOUT] = "TV",
11860 [INTEL_OUTPUT_HDMI] = "HDMI",
11861 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
11862 [INTEL_OUTPUT_EDP] = "eDP",
11863 [INTEL_OUTPUT_DSI] = "DSI",
11864 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
11865 };
11866
11867 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
11868 return "Invalid";
11869
11870 return names[output];
11871 }
11872
11873 static bool intel_crt_present(struct drm_device *dev)
11874 {
11875 struct drm_i915_private *dev_priv = dev->dev_private;
11876
11877 if (IS_ULT(dev))
11878 return false;
11879
11880 if (IS_CHERRYVIEW(dev))
11881 return false;
11882
11883 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
11884 return false;
11885
11886 return true;
11887 }
11888
11889 static void intel_setup_outputs(struct drm_device *dev)
11890 {
11891 struct drm_i915_private *dev_priv = dev->dev_private;
11892 struct intel_encoder *encoder;
11893 bool dpd_is_edp = false;
11894
11895 intel_lvds_init(dev);
11896
11897 if (intel_crt_present(dev))
11898 intel_crt_init(dev);
11899
11900 if (HAS_DDI(dev)) {
11901 int found;
11902
11903 /* Haswell uses DDI functions to detect digital outputs */
11904 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
11905 /* DDI A only supports eDP */
11906 if (found)
11907 intel_ddi_init(dev, PORT_A);
11908
11909 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
11910 * register */
11911 found = I915_READ(SFUSE_STRAP);
11912
11913 if (found & SFUSE_STRAP_DDIB_DETECTED)
11914 intel_ddi_init(dev, PORT_B);
11915 if (found & SFUSE_STRAP_DDIC_DETECTED)
11916 intel_ddi_init(dev, PORT_C);
11917 if (found & SFUSE_STRAP_DDID_DETECTED)
11918 intel_ddi_init(dev, PORT_D);
11919 } else if (HAS_PCH_SPLIT(dev)) {
11920 int found;
11921 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
11922
11923 if (has_edp_a(dev))
11924 intel_dp_init(dev, DP_A, PORT_A);
11925
11926 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
11927 /* PCH SDVOB multiplex with HDMIB */
11928 found = intel_sdvo_init(dev, PCH_SDVOB, true);
11929 if (!found)
11930 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
11931 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
11932 intel_dp_init(dev, PCH_DP_B, PORT_B);
11933 }
11934
11935 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
11936 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
11937
11938 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
11939 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
11940
11941 if (I915_READ(PCH_DP_C) & DP_DETECTED)
11942 intel_dp_init(dev, PCH_DP_C, PORT_C);
11943
11944 if (I915_READ(PCH_DP_D) & DP_DETECTED)
11945 intel_dp_init(dev, PCH_DP_D, PORT_D);
11946 } else if (IS_VALLEYVIEW(dev)) {
11947 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
11948 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
11949 PORT_B);
11950 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
11951 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
11952 }
11953
11954 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
11955 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
11956 PORT_C);
11957 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
11958 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
11959 }
11960
11961 if (IS_CHERRYVIEW(dev)) {
11962 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) {
11963 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
11964 PORT_D);
11965 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
11966 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
11967 }
11968 }
11969
11970 intel_dsi_init(dev);
11971 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
11972 bool found = false;
11973
11974 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
11975 DRM_DEBUG_KMS("probing SDVOB\n");
11976 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
11977 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
11978 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
11979 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
11980 }
11981
11982 if (!found && SUPPORTS_INTEGRATED_DP(dev))
11983 intel_dp_init(dev, DP_B, PORT_B);
11984 }
11985
11986 /* Before G4X SDVOC doesn't have its own detect register */
11987
11988 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
11989 DRM_DEBUG_KMS("probing SDVOC\n");
11990 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
11991 }
11992
11993 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
11994
11995 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
11996 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
11997 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
11998 }
11999 if (SUPPORTS_INTEGRATED_DP(dev))
12000 intel_dp_init(dev, DP_C, PORT_C);
12001 }
12002
12003 if (SUPPORTS_INTEGRATED_DP(dev) &&
12004 (I915_READ(DP_D) & DP_DETECTED))
12005 intel_dp_init(dev, DP_D, PORT_D);
12006 } else if (IS_GEN2(dev))
12007 intel_dvo_init(dev);
12008
12009 if (SUPPORTS_TV(dev))
12010 intel_tv_init(dev);
12011
12012 intel_edp_psr_init(dev);
12013
12014 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
12015 encoder->base.possible_crtcs = encoder->crtc_mask;
12016 encoder->base.possible_clones =
12017 intel_encoder_clones(encoder);
12018 }
12019
12020 intel_init_pch_refclk(dev);
12021
12022 drm_helper_move_panel_connectors_to_head(dev);
12023 }
12024
12025 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12026 {
12027 struct drm_device *dev = fb->dev;
12028 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12029
12030 drm_framebuffer_cleanup(fb);
12031 mutex_lock(&dev->struct_mutex);
12032 WARN_ON(!intel_fb->obj->framebuffer_references--);
12033 drm_gem_object_unreference(&intel_fb->obj->base);
12034 mutex_unlock(&dev->struct_mutex);
12035 kfree(intel_fb);
12036 }
12037
12038 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12039 struct drm_file *file,
12040 unsigned int *handle)
12041 {
12042 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12043 struct drm_i915_gem_object *obj = intel_fb->obj;
12044
12045 return drm_gem_handle_create(file, &obj->base, handle);
12046 }
12047
12048 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12049 .destroy = intel_user_framebuffer_destroy,
12050 .create_handle = intel_user_framebuffer_create_handle,
12051 };
12052
12053 static int intel_framebuffer_init(struct drm_device *dev,
12054 struct intel_framebuffer *intel_fb,
12055 struct drm_mode_fb_cmd2 *mode_cmd,
12056 struct drm_i915_gem_object *obj)
12057 {
12058 int aligned_height;
12059 int pitch_limit;
12060 int ret;
12061
12062 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12063
12064 if (obj->tiling_mode == I915_TILING_Y) {
12065 DRM_DEBUG("hardware does not support tiling Y\n");
12066 return -EINVAL;
12067 }
12068
12069 if (mode_cmd->pitches[0] & 63) {
12070 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12071 mode_cmd->pitches[0]);
12072 return -EINVAL;
12073 }
12074
12075 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12076 pitch_limit = 32*1024;
12077 } else if (INTEL_INFO(dev)->gen >= 4) {
12078 if (obj->tiling_mode)
12079 pitch_limit = 16*1024;
12080 else
12081 pitch_limit = 32*1024;
12082 } else if (INTEL_INFO(dev)->gen >= 3) {
12083 if (obj->tiling_mode)
12084 pitch_limit = 8*1024;
12085 else
12086 pitch_limit = 16*1024;
12087 } else
12088 /* XXX DSPC is limited to 4k tiled */
12089 pitch_limit = 8*1024;
12090
12091 if (mode_cmd->pitches[0] > pitch_limit) {
12092 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12093 obj->tiling_mode ? "tiled" : "linear",
12094 mode_cmd->pitches[0], pitch_limit);
12095 return -EINVAL;
12096 }
12097
12098 if (obj->tiling_mode != I915_TILING_NONE &&
12099 mode_cmd->pitches[0] != obj->stride) {
12100 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12101 mode_cmd->pitches[0], obj->stride);
12102 return -EINVAL;
12103 }
12104
12105 /* Reject formats not supported by any plane early. */
12106 switch (mode_cmd->pixel_format) {
12107 case DRM_FORMAT_C8:
12108 case DRM_FORMAT_RGB565:
12109 case DRM_FORMAT_XRGB8888:
12110 case DRM_FORMAT_ARGB8888:
12111 break;
12112 case DRM_FORMAT_XRGB1555:
12113 case DRM_FORMAT_ARGB1555:
12114 if (INTEL_INFO(dev)->gen > 3) {
12115 DRM_DEBUG("unsupported pixel format: %s\n",
12116 drm_get_format_name(mode_cmd->pixel_format));
12117 return -EINVAL;
12118 }
12119 break;
12120 case DRM_FORMAT_XBGR8888:
12121 case DRM_FORMAT_ABGR8888:
12122 case DRM_FORMAT_XRGB2101010:
12123 case DRM_FORMAT_ARGB2101010:
12124 case DRM_FORMAT_XBGR2101010:
12125 case DRM_FORMAT_ABGR2101010:
12126 if (INTEL_INFO(dev)->gen < 4) {
12127 DRM_DEBUG("unsupported pixel format: %s\n",
12128 drm_get_format_name(mode_cmd->pixel_format));
12129 return -EINVAL;
12130 }
12131 break;
12132 case DRM_FORMAT_YUYV:
12133 case DRM_FORMAT_UYVY:
12134 case DRM_FORMAT_YVYU:
12135 case DRM_FORMAT_VYUY:
12136 if (INTEL_INFO(dev)->gen < 5) {
12137 DRM_DEBUG("unsupported pixel format: %s\n",
12138 drm_get_format_name(mode_cmd->pixel_format));
12139 return -EINVAL;
12140 }
12141 break;
12142 default:
12143 DRM_DEBUG("unsupported pixel format: %s\n",
12144 drm_get_format_name(mode_cmd->pixel_format));
12145 return -EINVAL;
12146 }
12147
12148 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12149 if (mode_cmd->offsets[0] != 0)
12150 return -EINVAL;
12151
12152 aligned_height = intel_align_height(dev, mode_cmd->height,
12153 obj->tiling_mode);
12154 /* FIXME drm helper for size checks (especially planar formats)? */
12155 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12156 return -EINVAL;
12157
12158 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12159 intel_fb->obj = obj;
12160 intel_fb->obj->framebuffer_references++;
12161
12162 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12163 if (ret) {
12164 DRM_ERROR("framebuffer init failed %d\n", ret);
12165 return ret;
12166 }
12167
12168 return 0;
12169 }
12170
12171 static struct drm_framebuffer *
12172 intel_user_framebuffer_create(struct drm_device *dev,
12173 struct drm_file *filp,
12174 struct drm_mode_fb_cmd2 *mode_cmd)
12175 {
12176 struct drm_i915_gem_object *obj;
12177
12178 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12179 mode_cmd->handles[0]));
12180 if (&obj->base == NULL)
12181 return ERR_PTR(-ENOENT);
12182
12183 return intel_framebuffer_create(dev, mode_cmd, obj);
12184 }
12185
12186 #ifndef CONFIG_DRM_I915_FBDEV
12187 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12188 {
12189 }
12190 #endif
12191
12192 static const struct drm_mode_config_funcs intel_mode_funcs = {
12193 .fb_create = intel_user_framebuffer_create,
12194 .output_poll_changed = intel_fbdev_output_poll_changed,
12195 };
12196
12197 /* Set up chip specific display functions */
12198 static void intel_init_display(struct drm_device *dev)
12199 {
12200 struct drm_i915_private *dev_priv = dev->dev_private;
12201
12202 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12203 dev_priv->display.find_dpll = g4x_find_best_dpll;
12204 else if (IS_CHERRYVIEW(dev))
12205 dev_priv->display.find_dpll = chv_find_best_dpll;
12206 else if (IS_VALLEYVIEW(dev))
12207 dev_priv->display.find_dpll = vlv_find_best_dpll;
12208 else if (IS_PINEVIEW(dev))
12209 dev_priv->display.find_dpll = pnv_find_best_dpll;
12210 else
12211 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12212
12213 if (HAS_DDI(dev)) {
12214 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12215 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12216 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
12217 dev_priv->display.crtc_enable = haswell_crtc_enable;
12218 dev_priv->display.crtc_disable = haswell_crtc_disable;
12219 dev_priv->display.off = haswell_crtc_off;
12220 dev_priv->display.update_primary_plane =
12221 ironlake_update_primary_plane;
12222 } else if (HAS_PCH_SPLIT(dev)) {
12223 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12224 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12225 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
12226 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12227 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12228 dev_priv->display.off = ironlake_crtc_off;
12229 dev_priv->display.update_primary_plane =
12230 ironlake_update_primary_plane;
12231 } else if (IS_VALLEYVIEW(dev)) {
12232 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12233 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12234 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12235 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12236 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12237 dev_priv->display.off = i9xx_crtc_off;
12238 dev_priv->display.update_primary_plane =
12239 i9xx_update_primary_plane;
12240 } else {
12241 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12242 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12243 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12244 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12245 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12246 dev_priv->display.off = i9xx_crtc_off;
12247 dev_priv->display.update_primary_plane =
12248 i9xx_update_primary_plane;
12249 }
12250
12251 /* Returns the core display clock speed */
12252 if (IS_VALLEYVIEW(dev))
12253 dev_priv->display.get_display_clock_speed =
12254 valleyview_get_display_clock_speed;
12255 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12256 dev_priv->display.get_display_clock_speed =
12257 i945_get_display_clock_speed;
12258 else if (IS_I915G(dev))
12259 dev_priv->display.get_display_clock_speed =
12260 i915_get_display_clock_speed;
12261 else if (IS_I945GM(dev) || IS_845G(dev))
12262 dev_priv->display.get_display_clock_speed =
12263 i9xx_misc_get_display_clock_speed;
12264 else if (IS_PINEVIEW(dev))
12265 dev_priv->display.get_display_clock_speed =
12266 pnv_get_display_clock_speed;
12267 else if (IS_I915GM(dev))
12268 dev_priv->display.get_display_clock_speed =
12269 i915gm_get_display_clock_speed;
12270 else if (IS_I865G(dev))
12271 dev_priv->display.get_display_clock_speed =
12272 i865_get_display_clock_speed;
12273 else if (IS_I85X(dev))
12274 dev_priv->display.get_display_clock_speed =
12275 i855_get_display_clock_speed;
12276 else /* 852, 830 */
12277 dev_priv->display.get_display_clock_speed =
12278 i830_get_display_clock_speed;
12279
12280 if (HAS_PCH_SPLIT(dev)) {
12281 if (IS_GEN5(dev)) {
12282 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12283 dev_priv->display.write_eld = ironlake_write_eld;
12284 } else if (IS_GEN6(dev)) {
12285 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12286 dev_priv->display.write_eld = ironlake_write_eld;
12287 dev_priv->display.modeset_global_resources =
12288 snb_modeset_global_resources;
12289 } else if (IS_IVYBRIDGE(dev)) {
12290 /* FIXME: detect B0+ stepping and use auto training */
12291 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12292 dev_priv->display.write_eld = ironlake_write_eld;
12293 dev_priv->display.modeset_global_resources =
12294 ivb_modeset_global_resources;
12295 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
12296 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12297 dev_priv->display.write_eld = haswell_write_eld;
12298 dev_priv->display.modeset_global_resources =
12299 haswell_modeset_global_resources;
12300 }
12301 } else if (IS_G4X(dev)) {
12302 dev_priv->display.write_eld = g4x_write_eld;
12303 } else if (IS_VALLEYVIEW(dev)) {
12304 dev_priv->display.modeset_global_resources =
12305 valleyview_modeset_global_resources;
12306 dev_priv->display.write_eld = ironlake_write_eld;
12307 }
12308
12309 /* Default just returns -ENODEV to indicate unsupported */
12310 dev_priv->display.queue_flip = intel_default_queue_flip;
12311
12312 switch (INTEL_INFO(dev)->gen) {
12313 case 2:
12314 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12315 break;
12316
12317 case 3:
12318 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12319 break;
12320
12321 case 4:
12322 case 5:
12323 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12324 break;
12325
12326 case 6:
12327 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12328 break;
12329 case 7:
12330 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12331 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12332 break;
12333 }
12334
12335 intel_panel_init_backlight_funcs(dev);
12336 }
12337
12338 /*
12339 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12340 * resume, or other times. This quirk makes sure that's the case for
12341 * affected systems.
12342 */
12343 static void quirk_pipea_force(struct drm_device *dev)
12344 {
12345 struct drm_i915_private *dev_priv = dev->dev_private;
12346
12347 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12348 DRM_INFO("applying pipe a force quirk\n");
12349 }
12350
12351 /*
12352 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12353 */
12354 static void quirk_ssc_force_disable(struct drm_device *dev)
12355 {
12356 struct drm_i915_private *dev_priv = dev->dev_private;
12357 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12358 DRM_INFO("applying lvds SSC disable quirk\n");
12359 }
12360
12361 /*
12362 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12363 * brightness value
12364 */
12365 static void quirk_invert_brightness(struct drm_device *dev)
12366 {
12367 struct drm_i915_private *dev_priv = dev->dev_private;
12368 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12369 DRM_INFO("applying inverted panel brightness quirk\n");
12370 }
12371
12372 struct intel_quirk {
12373 int device;
12374 int subsystem_vendor;
12375 int subsystem_device;
12376 void (*hook)(struct drm_device *dev);
12377 };
12378
12379 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12380 struct intel_dmi_quirk {
12381 void (*hook)(struct drm_device *dev);
12382 const struct dmi_system_id (*dmi_id_list)[];
12383 };
12384
12385 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12386 {
12387 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12388 return 1;
12389 }
12390
12391 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12392 {
12393 .dmi_id_list = &(const struct dmi_system_id[]) {
12394 {
12395 .callback = intel_dmi_reverse_brightness,
12396 .ident = "NCR Corporation",
12397 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12398 DMI_MATCH(DMI_PRODUCT_NAME, ""),
12399 },
12400 },
12401 { } /* terminating entry */
12402 },
12403 .hook = quirk_invert_brightness,
12404 },
12405 };
12406
12407 static struct intel_quirk intel_quirks[] = {
12408 /* HP Mini needs pipe A force quirk (LP: #322104) */
12409 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12410
12411 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12412 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12413
12414 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12415 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12416
12417 /* Lenovo U160 cannot use SSC on LVDS */
12418 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12419
12420 /* Sony Vaio Y cannot use SSC on LVDS */
12421 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12422
12423 /* Acer Aspire 5734Z must invert backlight brightness */
12424 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12425
12426 /* Acer/eMachines G725 */
12427 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12428
12429 /* Acer/eMachines e725 */
12430 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12431
12432 /* Acer/Packard Bell NCL20 */
12433 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12434
12435 /* Acer Aspire 4736Z */
12436 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12437
12438 /* Acer Aspire 5336 */
12439 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12440 };
12441
12442 static void intel_init_quirks(struct drm_device *dev)
12443 {
12444 struct pci_dev *d = dev->pdev;
12445 int i;
12446
12447 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12448 struct intel_quirk *q = &intel_quirks[i];
12449
12450 if (d->device == q->device &&
12451 (d->subsystem_vendor == q->subsystem_vendor ||
12452 q->subsystem_vendor == PCI_ANY_ID) &&
12453 (d->subsystem_device == q->subsystem_device ||
12454 q->subsystem_device == PCI_ANY_ID))
12455 q->hook(dev);
12456 }
12457 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12458 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12459 intel_dmi_quirks[i].hook(dev);
12460 }
12461 }
12462
12463 /* Disable the VGA plane that we never use */
12464 static void i915_disable_vga(struct drm_device *dev)
12465 {
12466 struct drm_i915_private *dev_priv = dev->dev_private;
12467 u8 sr1;
12468 u32 vga_reg = i915_vgacntrl_reg(dev);
12469
12470 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12471 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12472 outb(SR01, VGA_SR_INDEX);
12473 sr1 = inb(VGA_SR_DATA);
12474 outb(sr1 | 1<<5, VGA_SR_DATA);
12475 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12476 udelay(300);
12477
12478 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
12479 POSTING_READ(vga_reg);
12480 }
12481
12482 void intel_modeset_init_hw(struct drm_device *dev)
12483 {
12484 intel_prepare_ddi(dev);
12485
12486 if (IS_VALLEYVIEW(dev))
12487 vlv_update_cdclk(dev);
12488
12489 intel_init_clock_gating(dev);
12490
12491 intel_reset_dpio(dev);
12492
12493 intel_enable_gt_powersave(dev);
12494 }
12495
12496 void intel_modeset_suspend_hw(struct drm_device *dev)
12497 {
12498 intel_suspend_hw(dev);
12499 }
12500
12501 void intel_modeset_init(struct drm_device *dev)
12502 {
12503 struct drm_i915_private *dev_priv = dev->dev_private;
12504 int sprite, ret;
12505 enum pipe pipe;
12506 struct intel_crtc *crtc;
12507
12508 drm_mode_config_init(dev);
12509
12510 dev->mode_config.min_width = 0;
12511 dev->mode_config.min_height = 0;
12512
12513 dev->mode_config.preferred_depth = 24;
12514 dev->mode_config.prefer_shadow = 1;
12515
12516 dev->mode_config.funcs = &intel_mode_funcs;
12517
12518 intel_init_quirks(dev);
12519
12520 intel_init_pm(dev);
12521
12522 if (INTEL_INFO(dev)->num_pipes == 0)
12523 return;
12524
12525 intel_init_display(dev);
12526
12527 if (IS_GEN2(dev)) {
12528 dev->mode_config.max_width = 2048;
12529 dev->mode_config.max_height = 2048;
12530 } else if (IS_GEN3(dev)) {
12531 dev->mode_config.max_width = 4096;
12532 dev->mode_config.max_height = 4096;
12533 } else {
12534 dev->mode_config.max_width = 8192;
12535 dev->mode_config.max_height = 8192;
12536 }
12537
12538 if (IS_GEN2(dev)) {
12539 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12540 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12541 } else {
12542 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
12543 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
12544 }
12545
12546 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
12547
12548 DRM_DEBUG_KMS("%d display pipe%s available.\n",
12549 INTEL_INFO(dev)->num_pipes,
12550 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
12551
12552 for_each_pipe(pipe) {
12553 intel_crtc_init(dev, pipe);
12554 for_each_sprite(pipe, sprite) {
12555 ret = intel_plane_init(dev, pipe, sprite);
12556 if (ret)
12557 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12558 pipe_name(pipe), sprite_name(pipe, sprite), ret);
12559 }
12560 }
12561
12562 intel_init_dpio(dev);
12563 intel_reset_dpio(dev);
12564
12565 intel_shared_dpll_init(dev);
12566
12567 /* Just disable it once at startup */
12568 i915_disable_vga(dev);
12569 intel_setup_outputs(dev);
12570
12571 /* Just in case the BIOS is doing something questionable. */
12572 intel_disable_fbc(dev);
12573
12574 drm_modeset_lock_all(dev);
12575 intel_modeset_setup_hw_state(dev, false);
12576 drm_modeset_unlock_all(dev);
12577
12578 for_each_intel_crtc(dev, crtc) {
12579 if (!crtc->active)
12580 continue;
12581
12582 /*
12583 * Note that reserving the BIOS fb up front prevents us
12584 * from stuffing other stolen allocations like the ring
12585 * on top. This prevents some ugliness at boot time, and
12586 * can even allow for smooth boot transitions if the BIOS
12587 * fb is large enough for the active pipe configuration.
12588 */
12589 if (dev_priv->display.get_plane_config) {
12590 dev_priv->display.get_plane_config(crtc,
12591 &crtc->plane_config);
12592 /*
12593 * If the fb is shared between multiple heads, we'll
12594 * just get the first one.
12595 */
12596 intel_find_plane_obj(crtc, &crtc->plane_config);
12597 }
12598 }
12599 }
12600
12601 static void intel_enable_pipe_a(struct drm_device *dev)
12602 {
12603 struct intel_connector *connector;
12604 struct drm_connector *crt = NULL;
12605 struct intel_load_detect_pipe load_detect_temp;
12606 struct drm_modeset_acquire_ctx ctx;
12607
12608 /* We can't just switch on the pipe A, we need to set things up with a
12609 * proper mode and output configuration. As a gross hack, enable pipe A
12610 * by enabling the load detect pipe once. */
12611 list_for_each_entry(connector,
12612 &dev->mode_config.connector_list,
12613 base.head) {
12614 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
12615 crt = &connector->base;
12616 break;
12617 }
12618 }
12619
12620 if (!crt)
12621 return;
12622
12623 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, &ctx))
12624 intel_release_load_detect_pipe(crt, &load_detect_temp, &ctx);
12625
12626
12627 }
12628
12629 static bool
12630 intel_check_plane_mapping(struct intel_crtc *crtc)
12631 {
12632 struct drm_device *dev = crtc->base.dev;
12633 struct drm_i915_private *dev_priv = dev->dev_private;
12634 u32 reg, val;
12635
12636 if (INTEL_INFO(dev)->num_pipes == 1)
12637 return true;
12638
12639 reg = DSPCNTR(!crtc->plane);
12640 val = I915_READ(reg);
12641
12642 if ((val & DISPLAY_PLANE_ENABLE) &&
12643 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
12644 return false;
12645
12646 return true;
12647 }
12648
12649 static void intel_sanitize_crtc(struct intel_crtc *crtc)
12650 {
12651 struct drm_device *dev = crtc->base.dev;
12652 struct drm_i915_private *dev_priv = dev->dev_private;
12653 u32 reg;
12654
12655 /* Clear any frame start delays used for debugging left by the BIOS */
12656 reg = PIPECONF(crtc->config.cpu_transcoder);
12657 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
12658
12659 /* restore vblank interrupts to correct state */
12660 if (crtc->active)
12661 drm_vblank_on(dev, crtc->pipe);
12662 else
12663 drm_vblank_off(dev, crtc->pipe);
12664
12665 /* We need to sanitize the plane -> pipe mapping first because this will
12666 * disable the crtc (and hence change the state) if it is wrong. Note
12667 * that gen4+ has a fixed plane -> pipe mapping. */
12668 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
12669 struct intel_connector *connector;
12670 bool plane;
12671
12672 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
12673 crtc->base.base.id);
12674
12675 /* Pipe has the wrong plane attached and the plane is active.
12676 * Temporarily change the plane mapping and disable everything
12677 * ... */
12678 plane = crtc->plane;
12679 crtc->plane = !plane;
12680 dev_priv->display.crtc_disable(&crtc->base);
12681 crtc->plane = plane;
12682
12683 /* ... and break all links. */
12684 list_for_each_entry(connector, &dev->mode_config.connector_list,
12685 base.head) {
12686 if (connector->encoder->base.crtc != &crtc->base)
12687 continue;
12688
12689 connector->base.dpms = DRM_MODE_DPMS_OFF;
12690 connector->base.encoder = NULL;
12691 }
12692 /* multiple connectors may have the same encoder:
12693 * handle them and break crtc link separately */
12694 list_for_each_entry(connector, &dev->mode_config.connector_list,
12695 base.head)
12696 if (connector->encoder->base.crtc == &crtc->base) {
12697 connector->encoder->base.crtc = NULL;
12698 connector->encoder->connectors_active = false;
12699 }
12700
12701 WARN_ON(crtc->active);
12702 crtc->base.enabled = false;
12703 }
12704
12705 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
12706 crtc->pipe == PIPE_A && !crtc->active) {
12707 /* BIOS forgot to enable pipe A, this mostly happens after
12708 * resume. Force-enable the pipe to fix this, the update_dpms
12709 * call below we restore the pipe to the right state, but leave
12710 * the required bits on. */
12711 intel_enable_pipe_a(dev);
12712 }
12713
12714 /* Adjust the state of the output pipe according to whether we
12715 * have active connectors/encoders. */
12716 intel_crtc_update_dpms(&crtc->base);
12717
12718 if (crtc->active != crtc->base.enabled) {
12719 struct intel_encoder *encoder;
12720
12721 /* This can happen either due to bugs in the get_hw_state
12722 * functions or because the pipe is force-enabled due to the
12723 * pipe A quirk. */
12724 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
12725 crtc->base.base.id,
12726 crtc->base.enabled ? "enabled" : "disabled",
12727 crtc->active ? "enabled" : "disabled");
12728
12729 crtc->base.enabled = crtc->active;
12730
12731 /* Because we only establish the connector -> encoder ->
12732 * crtc links if something is active, this means the
12733 * crtc is now deactivated. Break the links. connector
12734 * -> encoder links are only establish when things are
12735 * actually up, hence no need to break them. */
12736 WARN_ON(crtc->active);
12737
12738 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
12739 WARN_ON(encoder->connectors_active);
12740 encoder->base.crtc = NULL;
12741 }
12742 }
12743
12744 if (crtc->active || IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen < 5) {
12745 /*
12746 * We start out with underrun reporting disabled to avoid races.
12747 * For correct bookkeeping mark this on active crtcs.
12748 *
12749 * Also on gmch platforms we dont have any hardware bits to
12750 * disable the underrun reporting. Which means we need to start
12751 * out with underrun reporting disabled also on inactive pipes,
12752 * since otherwise we'll complain about the garbage we read when
12753 * e.g. coming up after runtime pm.
12754 *
12755 * No protection against concurrent access is required - at
12756 * worst a fifo underrun happens which also sets this to false.
12757 */
12758 crtc->cpu_fifo_underrun_disabled = true;
12759 crtc->pch_fifo_underrun_disabled = true;
12760
12761 update_scanline_offset(crtc);
12762 }
12763 }
12764
12765 static void intel_sanitize_encoder(struct intel_encoder *encoder)
12766 {
12767 struct intel_connector *connector;
12768 struct drm_device *dev = encoder->base.dev;
12769
12770 /* We need to check both for a crtc link (meaning that the
12771 * encoder is active and trying to read from a pipe) and the
12772 * pipe itself being active. */
12773 bool has_active_crtc = encoder->base.crtc &&
12774 to_intel_crtc(encoder->base.crtc)->active;
12775
12776 if (encoder->connectors_active && !has_active_crtc) {
12777 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
12778 encoder->base.base.id,
12779 encoder->base.name);
12780
12781 /* Connector is active, but has no active pipe. This is
12782 * fallout from our resume register restoring. Disable
12783 * the encoder manually again. */
12784 if (encoder->base.crtc) {
12785 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
12786 encoder->base.base.id,
12787 encoder->base.name);
12788 encoder->disable(encoder);
12789 }
12790 encoder->base.crtc = NULL;
12791 encoder->connectors_active = false;
12792
12793 /* Inconsistent output/port/pipe state happens presumably due to
12794 * a bug in one of the get_hw_state functions. Or someplace else
12795 * in our code, like the register restore mess on resume. Clamp
12796 * things to off as a safer default. */
12797 list_for_each_entry(connector,
12798 &dev->mode_config.connector_list,
12799 base.head) {
12800 if (connector->encoder != encoder)
12801 continue;
12802 connector->base.dpms = DRM_MODE_DPMS_OFF;
12803 connector->base.encoder = NULL;
12804 }
12805 }
12806 /* Enabled encoders without active connectors will be fixed in
12807 * the crtc fixup. */
12808 }
12809
12810 void i915_redisable_vga_power_on(struct drm_device *dev)
12811 {
12812 struct drm_i915_private *dev_priv = dev->dev_private;
12813 u32 vga_reg = i915_vgacntrl_reg(dev);
12814
12815 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
12816 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
12817 i915_disable_vga(dev);
12818 }
12819 }
12820
12821 void i915_redisable_vga(struct drm_device *dev)
12822 {
12823 struct drm_i915_private *dev_priv = dev->dev_private;
12824
12825 /* This function can be called both from intel_modeset_setup_hw_state or
12826 * at a very early point in our resume sequence, where the power well
12827 * structures are not yet restored. Since this function is at a very
12828 * paranoid "someone might have enabled VGA while we were not looking"
12829 * level, just check if the power well is enabled instead of trying to
12830 * follow the "don't touch the power well if we don't need it" policy
12831 * the rest of the driver uses. */
12832 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
12833 return;
12834
12835 i915_redisable_vga_power_on(dev);
12836 }
12837
12838 static bool primary_get_hw_state(struct intel_crtc *crtc)
12839 {
12840 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
12841
12842 if (!crtc->active)
12843 return false;
12844
12845 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
12846 }
12847
12848 static void intel_modeset_readout_hw_state(struct drm_device *dev)
12849 {
12850 struct drm_i915_private *dev_priv = dev->dev_private;
12851 enum pipe pipe;
12852 struct intel_crtc *crtc;
12853 struct intel_encoder *encoder;
12854 struct intel_connector *connector;
12855 int i;
12856
12857 for_each_intel_crtc(dev, crtc) {
12858 memset(&crtc->config, 0, sizeof(crtc->config));
12859
12860 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
12861
12862 crtc->active = dev_priv->display.get_pipe_config(crtc,
12863 &crtc->config);
12864
12865 crtc->base.enabled = crtc->active;
12866 crtc->primary_enabled = primary_get_hw_state(crtc);
12867
12868 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
12869 crtc->base.base.id,
12870 crtc->active ? "enabled" : "disabled");
12871 }
12872
12873 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12874 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12875
12876 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
12877 pll->active = 0;
12878 for_each_intel_crtc(dev, crtc) {
12879 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12880 pll->active++;
12881 }
12882 pll->refcount = pll->active;
12883
12884 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
12885 pll->name, pll->refcount, pll->on);
12886
12887 if (pll->refcount)
12888 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
12889 }
12890
12891 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
12892 base.head) {
12893 pipe = 0;
12894
12895 if (encoder->get_hw_state(encoder, &pipe)) {
12896 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
12897 encoder->base.crtc = &crtc->base;
12898 encoder->get_config(encoder, &crtc->config);
12899 } else {
12900 encoder->base.crtc = NULL;
12901 }
12902
12903 encoder->connectors_active = false;
12904 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
12905 encoder->base.base.id,
12906 encoder->base.name,
12907 encoder->base.crtc ? "enabled" : "disabled",
12908 pipe_name(pipe));
12909 }
12910
12911 list_for_each_entry(connector, &dev->mode_config.connector_list,
12912 base.head) {
12913 if (connector->get_hw_state(connector)) {
12914 connector->base.dpms = DRM_MODE_DPMS_ON;
12915 connector->encoder->connectors_active = true;
12916 connector->base.encoder = &connector->encoder->base;
12917 } else {
12918 connector->base.dpms = DRM_MODE_DPMS_OFF;
12919 connector->base.encoder = NULL;
12920 }
12921 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
12922 connector->base.base.id,
12923 connector->base.name,
12924 connector->base.encoder ? "enabled" : "disabled");
12925 }
12926 }
12927
12928 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
12929 * and i915 state tracking structures. */
12930 void intel_modeset_setup_hw_state(struct drm_device *dev,
12931 bool force_restore)
12932 {
12933 struct drm_i915_private *dev_priv = dev->dev_private;
12934 enum pipe pipe;
12935 struct intel_crtc *crtc;
12936 struct intel_encoder *encoder;
12937 int i;
12938
12939 intel_modeset_readout_hw_state(dev);
12940
12941 /*
12942 * Now that we have the config, copy it to each CRTC struct
12943 * Note that this could go away if we move to using crtc_config
12944 * checking everywhere.
12945 */
12946 for_each_intel_crtc(dev, crtc) {
12947 if (crtc->active && i915.fastboot) {
12948 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
12949 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
12950 crtc->base.base.id);
12951 drm_mode_debug_printmodeline(&crtc->base.mode);
12952 }
12953 }
12954
12955 /* HW state is read out, now we need to sanitize this mess. */
12956 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
12957 base.head) {
12958 intel_sanitize_encoder(encoder);
12959 }
12960
12961 for_each_pipe(pipe) {
12962 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
12963 intel_sanitize_crtc(crtc);
12964 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
12965 }
12966
12967 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12968 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12969
12970 if (!pll->on || pll->active)
12971 continue;
12972
12973 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
12974
12975 pll->disable(dev_priv, pll);
12976 pll->on = false;
12977 }
12978
12979 if (HAS_PCH_SPLIT(dev))
12980 ilk_wm_get_hw_state(dev);
12981
12982 if (force_restore) {
12983 i915_redisable_vga(dev);
12984
12985 /*
12986 * We need to use raw interfaces for restoring state to avoid
12987 * checking (bogus) intermediate states.
12988 */
12989 for_each_pipe(pipe) {
12990 struct drm_crtc *crtc =
12991 dev_priv->pipe_to_crtc_mapping[pipe];
12992
12993 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
12994 crtc->primary->fb);
12995 }
12996 } else {
12997 intel_modeset_update_staged_output_state(dev);
12998 }
12999
13000 intel_modeset_check_state(dev);
13001 }
13002
13003 void intel_modeset_gem_init(struct drm_device *dev)
13004 {
13005 struct drm_crtc *c;
13006 struct drm_i915_gem_object *obj;
13007
13008 mutex_lock(&dev->struct_mutex);
13009 intel_init_gt_powersave(dev);
13010 mutex_unlock(&dev->struct_mutex);
13011
13012 intel_modeset_init_hw(dev);
13013
13014 intel_setup_overlay(dev);
13015
13016 /*
13017 * Make sure any fbs we allocated at startup are properly
13018 * pinned & fenced. When we do the allocation it's too early
13019 * for this.
13020 */
13021 mutex_lock(&dev->struct_mutex);
13022 for_each_crtc(dev, c) {
13023 obj = intel_fb_obj(c->primary->fb);
13024 if (obj == NULL)
13025 continue;
13026
13027 if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) {
13028 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13029 to_intel_crtc(c)->pipe);
13030 drm_framebuffer_unreference(c->primary->fb);
13031 c->primary->fb = NULL;
13032 }
13033 }
13034 mutex_unlock(&dev->struct_mutex);
13035 }
13036
13037 void intel_connector_unregister(struct intel_connector *intel_connector)
13038 {
13039 struct drm_connector *connector = &intel_connector->base;
13040
13041 intel_panel_destroy_backlight(connector);
13042 drm_sysfs_connector_remove(connector);
13043 }
13044
13045 void intel_modeset_cleanup(struct drm_device *dev)
13046 {
13047 struct drm_i915_private *dev_priv = dev->dev_private;
13048 struct drm_connector *connector;
13049
13050 /*
13051 * Interrupts and polling as the first thing to avoid creating havoc.
13052 * Too much stuff here (turning of rps, connectors, ...) would
13053 * experience fancy races otherwise.
13054 */
13055 drm_irq_uninstall(dev);
13056 cancel_work_sync(&dev_priv->hotplug_work);
13057 /*
13058 * Due to the hpd irq storm handling the hotplug work can re-arm the
13059 * poll handlers. Hence disable polling after hpd handling is shut down.
13060 */
13061 drm_kms_helper_poll_fini(dev);
13062
13063 mutex_lock(&dev->struct_mutex);
13064
13065 intel_unregister_dsm_handler();
13066
13067 intel_disable_fbc(dev);
13068
13069 intel_disable_gt_powersave(dev);
13070
13071 ironlake_teardown_rc6(dev);
13072
13073 mutex_unlock(&dev->struct_mutex);
13074
13075 /* flush any delayed tasks or pending work */
13076 flush_scheduled_work();
13077
13078 /* destroy the backlight and sysfs files before encoders/connectors */
13079 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13080 struct intel_connector *intel_connector;
13081
13082 intel_connector = to_intel_connector(connector);
13083 intel_connector->unregister(intel_connector);
13084 }
13085
13086 drm_mode_config_cleanup(dev);
13087
13088 intel_cleanup_overlay(dev);
13089
13090 mutex_lock(&dev->struct_mutex);
13091 intel_cleanup_gt_powersave(dev);
13092 mutex_unlock(&dev->struct_mutex);
13093 }
13094
13095 /*
13096 * Return which encoder is currently attached for connector.
13097 */
13098 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13099 {
13100 return &intel_attached_encoder(connector)->base;
13101 }
13102
13103 void intel_connector_attach_encoder(struct intel_connector *connector,
13104 struct intel_encoder *encoder)
13105 {
13106 connector->encoder = encoder;
13107 drm_mode_connector_attach_encoder(&connector->base,
13108 &encoder->base);
13109 }
13110
13111 /*
13112 * set vga decode state - true == enable VGA decode
13113 */
13114 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13115 {
13116 struct drm_i915_private *dev_priv = dev->dev_private;
13117 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13118 u16 gmch_ctrl;
13119
13120 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13121 DRM_ERROR("failed to read control word\n");
13122 return -EIO;
13123 }
13124
13125 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13126 return 0;
13127
13128 if (state)
13129 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13130 else
13131 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13132
13133 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13134 DRM_ERROR("failed to write control word\n");
13135 return -EIO;
13136 }
13137
13138 return 0;
13139 }
13140
13141 struct intel_display_error_state {
13142
13143 u32 power_well_driver;
13144
13145 int num_transcoders;
13146
13147 struct intel_cursor_error_state {
13148 u32 control;
13149 u32 position;
13150 u32 base;
13151 u32 size;
13152 } cursor[I915_MAX_PIPES];
13153
13154 struct intel_pipe_error_state {
13155 bool power_domain_on;
13156 u32 source;
13157 u32 stat;
13158 } pipe[I915_MAX_PIPES];
13159
13160 struct intel_plane_error_state {
13161 u32 control;
13162 u32 stride;
13163 u32 size;
13164 u32 pos;
13165 u32 addr;
13166 u32 surface;
13167 u32 tile_offset;
13168 } plane[I915_MAX_PIPES];
13169
13170 struct intel_transcoder_error_state {
13171 bool power_domain_on;
13172 enum transcoder cpu_transcoder;
13173
13174 u32 conf;
13175
13176 u32 htotal;
13177 u32 hblank;
13178 u32 hsync;
13179 u32 vtotal;
13180 u32 vblank;
13181 u32 vsync;
13182 } transcoder[4];
13183 };
13184
13185 struct intel_display_error_state *
13186 intel_display_capture_error_state(struct drm_device *dev)
13187 {
13188 struct drm_i915_private *dev_priv = dev->dev_private;
13189 struct intel_display_error_state *error;
13190 int transcoders[] = {
13191 TRANSCODER_A,
13192 TRANSCODER_B,
13193 TRANSCODER_C,
13194 TRANSCODER_EDP,
13195 };
13196 int i;
13197
13198 if (INTEL_INFO(dev)->num_pipes == 0)
13199 return NULL;
13200
13201 error = kzalloc(sizeof(*error), GFP_ATOMIC);
13202 if (error == NULL)
13203 return NULL;
13204
13205 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13206 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13207
13208 for_each_pipe(i) {
13209 error->pipe[i].power_domain_on =
13210 intel_display_power_enabled_unlocked(dev_priv,
13211 POWER_DOMAIN_PIPE(i));
13212 if (!error->pipe[i].power_domain_on)
13213 continue;
13214
13215 error->cursor[i].control = I915_READ(CURCNTR(i));
13216 error->cursor[i].position = I915_READ(CURPOS(i));
13217 error->cursor[i].base = I915_READ(CURBASE(i));
13218
13219 error->plane[i].control = I915_READ(DSPCNTR(i));
13220 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13221 if (INTEL_INFO(dev)->gen <= 3) {
13222 error->plane[i].size = I915_READ(DSPSIZE(i));
13223 error->plane[i].pos = I915_READ(DSPPOS(i));
13224 }
13225 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13226 error->plane[i].addr = I915_READ(DSPADDR(i));
13227 if (INTEL_INFO(dev)->gen >= 4) {
13228 error->plane[i].surface = I915_READ(DSPSURF(i));
13229 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13230 }
13231
13232 error->pipe[i].source = I915_READ(PIPESRC(i));
13233
13234 if (!HAS_PCH_SPLIT(dev))
13235 error->pipe[i].stat = I915_READ(PIPESTAT(i));
13236 }
13237
13238 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13239 if (HAS_DDI(dev_priv->dev))
13240 error->num_transcoders++; /* Account for eDP. */
13241
13242 for (i = 0; i < error->num_transcoders; i++) {
13243 enum transcoder cpu_transcoder = transcoders[i];
13244
13245 error->transcoder[i].power_domain_on =
13246 intel_display_power_enabled_unlocked(dev_priv,
13247 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13248 if (!error->transcoder[i].power_domain_on)
13249 continue;
13250
13251 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13252
13253 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13254 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13255 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13256 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13257 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13258 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13259 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13260 }
13261
13262 return error;
13263 }
13264
13265 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13266
13267 void
13268 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13269 struct drm_device *dev,
13270 struct intel_display_error_state *error)
13271 {
13272 int i;
13273
13274 if (!error)
13275 return;
13276
13277 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13278 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13279 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13280 error->power_well_driver);
13281 for_each_pipe(i) {
13282 err_printf(m, "Pipe [%d]:\n", i);
13283 err_printf(m, " Power: %s\n",
13284 error->pipe[i].power_domain_on ? "on" : "off");
13285 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
13286 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
13287
13288 err_printf(m, "Plane [%d]:\n", i);
13289 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
13290 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
13291 if (INTEL_INFO(dev)->gen <= 3) {
13292 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
13293 err_printf(m, " POS: %08x\n", error->plane[i].pos);
13294 }
13295 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13296 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
13297 if (INTEL_INFO(dev)->gen >= 4) {
13298 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
13299 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
13300 }
13301
13302 err_printf(m, "Cursor [%d]:\n", i);
13303 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
13304 err_printf(m, " POS: %08x\n", error->cursor[i].position);
13305 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
13306 }
13307
13308 for (i = 0; i < error->num_transcoders; i++) {
13309 err_printf(m, "CPU transcoder: %c\n",
13310 transcoder_name(error->transcoder[i].cpu_transcoder));
13311 err_printf(m, " Power: %s\n",
13312 error->transcoder[i].power_domain_on ? "on" : "off");
13313 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
13314 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
13315 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
13316 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
13317 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
13318 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
13319 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
13320 }
13321 }
Linux kernel - Deliverables
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