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[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
43
44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
45 static void intel_increase_pllclock(struct drm_crtc *crtc);
46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
47
48 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
49 struct intel_crtc_config *pipe_config);
50 static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
51 struct intel_crtc_config *pipe_config);
52
53 typedef struct {
54 int min, max;
55 } intel_range_t;
56
57 typedef struct {
58 int dot_limit;
59 int p2_slow, p2_fast;
60 } intel_p2_t;
61
62 #define INTEL_P2_NUM 2
63 typedef struct intel_limit intel_limit_t;
64 struct intel_limit {
65 intel_range_t dot, vco, n, m, m1, m2, p, p1;
66 intel_p2_t p2;
67 };
68
69 /* FDI */
70 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
71
72 int
73 intel_pch_rawclk(struct drm_device *dev)
74 {
75 struct drm_i915_private *dev_priv = dev->dev_private;
76
77 WARN_ON(!HAS_PCH_SPLIT(dev));
78
79 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
80 }
81
82 static inline u32 /* units of 100MHz */
83 intel_fdi_link_freq(struct drm_device *dev)
84 {
85 if (IS_GEN5(dev)) {
86 struct drm_i915_private *dev_priv = dev->dev_private;
87 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
88 } else
89 return 27;
90 }
91
92 static const intel_limit_t intel_limits_i8xx_dvo = {
93 .dot = { .min = 25000, .max = 350000 },
94 .vco = { .min = 930000, .max = 1400000 },
95 .n = { .min = 3, .max = 16 },
96 .m = { .min = 96, .max = 140 },
97 .m1 = { .min = 18, .max = 26 },
98 .m2 = { .min = 6, .max = 16 },
99 .p = { .min = 4, .max = 128 },
100 .p1 = { .min = 2, .max = 33 },
101 .p2 = { .dot_limit = 165000,
102 .p2_slow = 4, .p2_fast = 2 },
103 };
104
105 static const intel_limit_t intel_limits_i8xx_lvds = {
106 .dot = { .min = 25000, .max = 350000 },
107 .vco = { .min = 930000, .max = 1400000 },
108 .n = { .min = 3, .max = 16 },
109 .m = { .min = 96, .max = 140 },
110 .m1 = { .min = 18, .max = 26 },
111 .m2 = { .min = 6, .max = 16 },
112 .p = { .min = 4, .max = 128 },
113 .p1 = { .min = 1, .max = 6 },
114 .p2 = { .dot_limit = 165000,
115 .p2_slow = 14, .p2_fast = 7 },
116 };
117
118 static const intel_limit_t intel_limits_i9xx_sdvo = {
119 .dot = { .min = 20000, .max = 400000 },
120 .vco = { .min = 1400000, .max = 2800000 },
121 .n = { .min = 1, .max = 6 },
122 .m = { .min = 70, .max = 120 },
123 .m1 = { .min = 8, .max = 18 },
124 .m2 = { .min = 3, .max = 7 },
125 .p = { .min = 5, .max = 80 },
126 .p1 = { .min = 1, .max = 8 },
127 .p2 = { .dot_limit = 200000,
128 .p2_slow = 10, .p2_fast = 5 },
129 };
130
131 static const intel_limit_t intel_limits_i9xx_lvds = {
132 .dot = { .min = 20000, .max = 400000 },
133 .vco = { .min = 1400000, .max = 2800000 },
134 .n = { .min = 1, .max = 6 },
135 .m = { .min = 70, .max = 120 },
136 .m1 = { .min = 8, .max = 18 },
137 .m2 = { .min = 3, .max = 7 },
138 .p = { .min = 7, .max = 98 },
139 .p1 = { .min = 1, .max = 8 },
140 .p2 = { .dot_limit = 112000,
141 .p2_slow = 14, .p2_fast = 7 },
142 };
143
144
145 static const intel_limit_t intel_limits_g4x_sdvo = {
146 .dot = { .min = 25000, .max = 270000 },
147 .vco = { .min = 1750000, .max = 3500000},
148 .n = { .min = 1, .max = 4 },
149 .m = { .min = 104, .max = 138 },
150 .m1 = { .min = 17, .max = 23 },
151 .m2 = { .min = 5, .max = 11 },
152 .p = { .min = 10, .max = 30 },
153 .p1 = { .min = 1, .max = 3},
154 .p2 = { .dot_limit = 270000,
155 .p2_slow = 10,
156 .p2_fast = 10
157 },
158 };
159
160 static const intel_limit_t intel_limits_g4x_hdmi = {
161 .dot = { .min = 22000, .max = 400000 },
162 .vco = { .min = 1750000, .max = 3500000},
163 .n = { .min = 1, .max = 4 },
164 .m = { .min = 104, .max = 138 },
165 .m1 = { .min = 16, .max = 23 },
166 .m2 = { .min = 5, .max = 11 },
167 .p = { .min = 5, .max = 80 },
168 .p1 = { .min = 1, .max = 8},
169 .p2 = { .dot_limit = 165000,
170 .p2_slow = 10, .p2_fast = 5 },
171 };
172
173 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
174 .dot = { .min = 20000, .max = 115000 },
175 .vco = { .min = 1750000, .max = 3500000 },
176 .n = { .min = 1, .max = 3 },
177 .m = { .min = 104, .max = 138 },
178 .m1 = { .min = 17, .max = 23 },
179 .m2 = { .min = 5, .max = 11 },
180 .p = { .min = 28, .max = 112 },
181 .p1 = { .min = 2, .max = 8 },
182 .p2 = { .dot_limit = 0,
183 .p2_slow = 14, .p2_fast = 14
184 },
185 };
186
187 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
188 .dot = { .min = 80000, .max = 224000 },
189 .vco = { .min = 1750000, .max = 3500000 },
190 .n = { .min = 1, .max = 3 },
191 .m = { .min = 104, .max = 138 },
192 .m1 = { .min = 17, .max = 23 },
193 .m2 = { .min = 5, .max = 11 },
194 .p = { .min = 14, .max = 42 },
195 .p1 = { .min = 2, .max = 6 },
196 .p2 = { .dot_limit = 0,
197 .p2_slow = 7, .p2_fast = 7
198 },
199 };
200
201 static const intel_limit_t intel_limits_pineview_sdvo = {
202 .dot = { .min = 20000, .max = 400000},
203 .vco = { .min = 1700000, .max = 3500000 },
204 /* Pineview's Ncounter is a ring counter */
205 .n = { .min = 3, .max = 6 },
206 .m = { .min = 2, .max = 256 },
207 /* Pineview only has one combined m divider, which we treat as m2. */
208 .m1 = { .min = 0, .max = 0 },
209 .m2 = { .min = 0, .max = 254 },
210 .p = { .min = 5, .max = 80 },
211 .p1 = { .min = 1, .max = 8 },
212 .p2 = { .dot_limit = 200000,
213 .p2_slow = 10, .p2_fast = 5 },
214 };
215
216 static const intel_limit_t intel_limits_pineview_lvds = {
217 .dot = { .min = 20000, .max = 400000 },
218 .vco = { .min = 1700000, .max = 3500000 },
219 .n = { .min = 3, .max = 6 },
220 .m = { .min = 2, .max = 256 },
221 .m1 = { .min = 0, .max = 0 },
222 .m2 = { .min = 0, .max = 254 },
223 .p = { .min = 7, .max = 112 },
224 .p1 = { .min = 1, .max = 8 },
225 .p2 = { .dot_limit = 112000,
226 .p2_slow = 14, .p2_fast = 14 },
227 };
228
229 /* Ironlake / Sandybridge
230 *
231 * We calculate clock using (register_value + 2) for N/M1/M2, so here
232 * the range value for them is (actual_value - 2).
233 */
234 static const intel_limit_t intel_limits_ironlake_dac = {
235 .dot = { .min = 25000, .max = 350000 },
236 .vco = { .min = 1760000, .max = 3510000 },
237 .n = { .min = 1, .max = 5 },
238 .m = { .min = 79, .max = 127 },
239 .m1 = { .min = 12, .max = 22 },
240 .m2 = { .min = 5, .max = 9 },
241 .p = { .min = 5, .max = 80 },
242 .p1 = { .min = 1, .max = 8 },
243 .p2 = { .dot_limit = 225000,
244 .p2_slow = 10, .p2_fast = 5 },
245 };
246
247 static const intel_limit_t intel_limits_ironlake_single_lvds = {
248 .dot = { .min = 25000, .max = 350000 },
249 .vco = { .min = 1760000, .max = 3510000 },
250 .n = { .min = 1, .max = 3 },
251 .m = { .min = 79, .max = 118 },
252 .m1 = { .min = 12, .max = 22 },
253 .m2 = { .min = 5, .max = 9 },
254 .p = { .min = 28, .max = 112 },
255 .p1 = { .min = 2, .max = 8 },
256 .p2 = { .dot_limit = 225000,
257 .p2_slow = 14, .p2_fast = 14 },
258 };
259
260 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
261 .dot = { .min = 25000, .max = 350000 },
262 .vco = { .min = 1760000, .max = 3510000 },
263 .n = { .min = 1, .max = 3 },
264 .m = { .min = 79, .max = 127 },
265 .m1 = { .min = 12, .max = 22 },
266 .m2 = { .min = 5, .max = 9 },
267 .p = { .min = 14, .max = 56 },
268 .p1 = { .min = 2, .max = 8 },
269 .p2 = { .dot_limit = 225000,
270 .p2_slow = 7, .p2_fast = 7 },
271 };
272
273 /* LVDS 100mhz refclk limits. */
274 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
275 .dot = { .min = 25000, .max = 350000 },
276 .vco = { .min = 1760000, .max = 3510000 },
277 .n = { .min = 1, .max = 2 },
278 .m = { .min = 79, .max = 126 },
279 .m1 = { .min = 12, .max = 22 },
280 .m2 = { .min = 5, .max = 9 },
281 .p = { .min = 28, .max = 112 },
282 .p1 = { .min = 2, .max = 8 },
283 .p2 = { .dot_limit = 225000,
284 .p2_slow = 14, .p2_fast = 14 },
285 };
286
287 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
288 .dot = { .min = 25000, .max = 350000 },
289 .vco = { .min = 1760000, .max = 3510000 },
290 .n = { .min = 1, .max = 3 },
291 .m = { .min = 79, .max = 126 },
292 .m1 = { .min = 12, .max = 22 },
293 .m2 = { .min = 5, .max = 9 },
294 .p = { .min = 14, .max = 42 },
295 .p1 = { .min = 2, .max = 6 },
296 .p2 = { .dot_limit = 225000,
297 .p2_slow = 7, .p2_fast = 7 },
298 };
299
300 static const intel_limit_t intel_limits_vlv_dac = {
301 .dot = { .min = 25000, .max = 270000 },
302 .vco = { .min = 4000000, .max = 6000000 },
303 .n = { .min = 1, .max = 7 },
304 .m = { .min = 22, .max = 450 }, /* guess */
305 .m1 = { .min = 2, .max = 3 },
306 .m2 = { .min = 11, .max = 156 },
307 .p = { .min = 10, .max = 30 },
308 .p1 = { .min = 1, .max = 3 },
309 .p2 = { .dot_limit = 270000,
310 .p2_slow = 2, .p2_fast = 20 },
311 };
312
313 static const intel_limit_t intel_limits_vlv_hdmi = {
314 .dot = { .min = 25000, .max = 270000 },
315 .vco = { .min = 4000000, .max = 6000000 },
316 .n = { .min = 1, .max = 7 },
317 .m = { .min = 60, .max = 300 }, /* guess */
318 .m1 = { .min = 2, .max = 3 },
319 .m2 = { .min = 11, .max = 156 },
320 .p = { .min = 10, .max = 30 },
321 .p1 = { .min = 2, .max = 3 },
322 .p2 = { .dot_limit = 270000,
323 .p2_slow = 2, .p2_fast = 20 },
324 };
325
326 static const intel_limit_t intel_limits_vlv_dp = {
327 .dot = { .min = 25000, .max = 270000 },
328 .vco = { .min = 4000000, .max = 6000000 },
329 .n = { .min = 1, .max = 7 },
330 .m = { .min = 22, .max = 450 },
331 .m1 = { .min = 2, .max = 3 },
332 .m2 = { .min = 11, .max = 156 },
333 .p = { .min = 10, .max = 30 },
334 .p1 = { .min = 1, .max = 3 },
335 .p2 = { .dot_limit = 270000,
336 .p2_slow = 2, .p2_fast = 20 },
337 };
338
339 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
340 int refclk)
341 {
342 struct drm_device *dev = crtc->dev;
343 const intel_limit_t *limit;
344
345 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
346 if (intel_is_dual_link_lvds(dev)) {
347 if (refclk == 100000)
348 limit = &intel_limits_ironlake_dual_lvds_100m;
349 else
350 limit = &intel_limits_ironlake_dual_lvds;
351 } else {
352 if (refclk == 100000)
353 limit = &intel_limits_ironlake_single_lvds_100m;
354 else
355 limit = &intel_limits_ironlake_single_lvds;
356 }
357 } else
358 limit = &intel_limits_ironlake_dac;
359
360 return limit;
361 }
362
363 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
364 {
365 struct drm_device *dev = crtc->dev;
366 const intel_limit_t *limit;
367
368 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
369 if (intel_is_dual_link_lvds(dev))
370 limit = &intel_limits_g4x_dual_channel_lvds;
371 else
372 limit = &intel_limits_g4x_single_channel_lvds;
373 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
374 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
375 limit = &intel_limits_g4x_hdmi;
376 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
377 limit = &intel_limits_g4x_sdvo;
378 } else /* The option is for other outputs */
379 limit = &intel_limits_i9xx_sdvo;
380
381 return limit;
382 }
383
384 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
385 {
386 struct drm_device *dev = crtc->dev;
387 const intel_limit_t *limit;
388
389 if (HAS_PCH_SPLIT(dev))
390 limit = intel_ironlake_limit(crtc, refclk);
391 else if (IS_G4X(dev)) {
392 limit = intel_g4x_limit(crtc);
393 } else if (IS_PINEVIEW(dev)) {
394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
395 limit = &intel_limits_pineview_lvds;
396 else
397 limit = &intel_limits_pineview_sdvo;
398 } else if (IS_VALLEYVIEW(dev)) {
399 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
400 limit = &intel_limits_vlv_dac;
401 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
402 limit = &intel_limits_vlv_hdmi;
403 else
404 limit = &intel_limits_vlv_dp;
405 } else if (!IS_GEN2(dev)) {
406 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
407 limit = &intel_limits_i9xx_lvds;
408 else
409 limit = &intel_limits_i9xx_sdvo;
410 } else {
411 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
412 limit = &intel_limits_i8xx_lvds;
413 else
414 limit = &intel_limits_i8xx_dvo;
415 }
416 return limit;
417 }
418
419 /* m1 is reserved as 0 in Pineview, n is a ring counter */
420 static void pineview_clock(int refclk, intel_clock_t *clock)
421 {
422 clock->m = clock->m2 + 2;
423 clock->p = clock->p1 * clock->p2;
424 clock->vco = refclk * clock->m / clock->n;
425 clock->dot = clock->vco / clock->p;
426 }
427
428 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
429 {
430 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
431 }
432
433 static void i9xx_clock(int refclk, intel_clock_t *clock)
434 {
435 clock->m = i9xx_dpll_compute_m(clock);
436 clock->p = clock->p1 * clock->p2;
437 clock->vco = refclk * clock->m / (clock->n + 2);
438 clock->dot = clock->vco / clock->p;
439 }
440
441 /**
442 * Returns whether any output on the specified pipe is of the specified type
443 */
444 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
445 {
446 struct drm_device *dev = crtc->dev;
447 struct intel_encoder *encoder;
448
449 for_each_encoder_on_crtc(dev, crtc, encoder)
450 if (encoder->type == type)
451 return true;
452
453 return false;
454 }
455
456 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
457 /**
458 * Returns whether the given set of divisors are valid for a given refclk with
459 * the given connectors.
460 */
461
462 static bool intel_PLL_is_valid(struct drm_device *dev,
463 const intel_limit_t *limit,
464 const intel_clock_t *clock)
465 {
466 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
467 INTELPllInvalid("p1 out of range\n");
468 if (clock->p < limit->p.min || limit->p.max < clock->p)
469 INTELPllInvalid("p out of range\n");
470 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
471 INTELPllInvalid("m2 out of range\n");
472 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
473 INTELPllInvalid("m1 out of range\n");
474 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
475 INTELPllInvalid("m1 <= m2\n");
476 if (clock->m < limit->m.min || limit->m.max < clock->m)
477 INTELPllInvalid("m out of range\n");
478 if (clock->n < limit->n.min || limit->n.max < clock->n)
479 INTELPllInvalid("n out of range\n");
480 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
481 INTELPllInvalid("vco out of range\n");
482 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
483 * connector, etc., rather than just a single range.
484 */
485 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
486 INTELPllInvalid("dot out of range\n");
487
488 return true;
489 }
490
491 static bool
492 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
493 int target, int refclk, intel_clock_t *match_clock,
494 intel_clock_t *best_clock)
495 {
496 struct drm_device *dev = crtc->dev;
497 intel_clock_t clock;
498 int err = target;
499
500 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
501 /*
502 * For LVDS just rely on its current settings for dual-channel.
503 * We haven't figured out how to reliably set up different
504 * single/dual channel state, if we even can.
505 */
506 if (intel_is_dual_link_lvds(dev))
507 clock.p2 = limit->p2.p2_fast;
508 else
509 clock.p2 = limit->p2.p2_slow;
510 } else {
511 if (target < limit->p2.dot_limit)
512 clock.p2 = limit->p2.p2_slow;
513 else
514 clock.p2 = limit->p2.p2_fast;
515 }
516
517 memset(best_clock, 0, sizeof(*best_clock));
518
519 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
520 clock.m1++) {
521 for (clock.m2 = limit->m2.min;
522 clock.m2 <= limit->m2.max; clock.m2++) {
523 if (clock.m2 >= clock.m1)
524 break;
525 for (clock.n = limit->n.min;
526 clock.n <= limit->n.max; clock.n++) {
527 for (clock.p1 = limit->p1.min;
528 clock.p1 <= limit->p1.max; clock.p1++) {
529 int this_err;
530
531 i9xx_clock(refclk, &clock);
532 if (!intel_PLL_is_valid(dev, limit,
533 &clock))
534 continue;
535 if (match_clock &&
536 clock.p != match_clock->p)
537 continue;
538
539 this_err = abs(clock.dot - target);
540 if (this_err < err) {
541 *best_clock = clock;
542 err = this_err;
543 }
544 }
545 }
546 }
547 }
548
549 return (err != target);
550 }
551
552 static bool
553 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
554 int target, int refclk, intel_clock_t *match_clock,
555 intel_clock_t *best_clock)
556 {
557 struct drm_device *dev = crtc->dev;
558 intel_clock_t clock;
559 int err = target;
560
561 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
562 /*
563 * For LVDS just rely on its current settings for dual-channel.
564 * We haven't figured out how to reliably set up different
565 * single/dual channel state, if we even can.
566 */
567 if (intel_is_dual_link_lvds(dev))
568 clock.p2 = limit->p2.p2_fast;
569 else
570 clock.p2 = limit->p2.p2_slow;
571 } else {
572 if (target < limit->p2.dot_limit)
573 clock.p2 = limit->p2.p2_slow;
574 else
575 clock.p2 = limit->p2.p2_fast;
576 }
577
578 memset(best_clock, 0, sizeof(*best_clock));
579
580 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
581 clock.m1++) {
582 for (clock.m2 = limit->m2.min;
583 clock.m2 <= limit->m2.max; clock.m2++) {
584 for (clock.n = limit->n.min;
585 clock.n <= limit->n.max; clock.n++) {
586 for (clock.p1 = limit->p1.min;
587 clock.p1 <= limit->p1.max; clock.p1++) {
588 int this_err;
589
590 pineview_clock(refclk, &clock);
591 if (!intel_PLL_is_valid(dev, limit,
592 &clock))
593 continue;
594 if (match_clock &&
595 clock.p != match_clock->p)
596 continue;
597
598 this_err = abs(clock.dot - target);
599 if (this_err < err) {
600 *best_clock = clock;
601 err = this_err;
602 }
603 }
604 }
605 }
606 }
607
608 return (err != target);
609 }
610
611 static bool
612 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
613 int target, int refclk, intel_clock_t *match_clock,
614 intel_clock_t *best_clock)
615 {
616 struct drm_device *dev = crtc->dev;
617 intel_clock_t clock;
618 int max_n;
619 bool found;
620 /* approximately equals target * 0.00585 */
621 int err_most = (target >> 8) + (target >> 9);
622 found = false;
623
624 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
625 if (intel_is_dual_link_lvds(dev))
626 clock.p2 = limit->p2.p2_fast;
627 else
628 clock.p2 = limit->p2.p2_slow;
629 } else {
630 if (target < limit->p2.dot_limit)
631 clock.p2 = limit->p2.p2_slow;
632 else
633 clock.p2 = limit->p2.p2_fast;
634 }
635
636 memset(best_clock, 0, sizeof(*best_clock));
637 max_n = limit->n.max;
638 /* based on hardware requirement, prefer smaller n to precision */
639 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
640 /* based on hardware requirement, prefere larger m1,m2 */
641 for (clock.m1 = limit->m1.max;
642 clock.m1 >= limit->m1.min; clock.m1--) {
643 for (clock.m2 = limit->m2.max;
644 clock.m2 >= limit->m2.min; clock.m2--) {
645 for (clock.p1 = limit->p1.max;
646 clock.p1 >= limit->p1.min; clock.p1--) {
647 int this_err;
648
649 i9xx_clock(refclk, &clock);
650 if (!intel_PLL_is_valid(dev, limit,
651 &clock))
652 continue;
653
654 this_err = abs(clock.dot - target);
655 if (this_err < err_most) {
656 *best_clock = clock;
657 err_most = this_err;
658 max_n = clock.n;
659 found = true;
660 }
661 }
662 }
663 }
664 }
665 return found;
666 }
667
668 static bool
669 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
670 int target, int refclk, intel_clock_t *match_clock,
671 intel_clock_t *best_clock)
672 {
673 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
674 u32 m, n, fastclk;
675 u32 updrate, minupdate, fracbits, p;
676 unsigned long bestppm, ppm, absppm;
677 int dotclk, flag;
678
679 flag = 0;
680 dotclk = target * 1000;
681 bestppm = 1000000;
682 ppm = absppm = 0;
683 fastclk = dotclk / (2*100);
684 updrate = 0;
685 minupdate = 19200;
686 fracbits = 1;
687 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
688 bestm1 = bestm2 = bestp1 = bestp2 = 0;
689
690 /* based on hardware requirement, prefer smaller n to precision */
691 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
692 updrate = refclk / n;
693 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
694 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
695 if (p2 > 10)
696 p2 = p2 - 1;
697 p = p1 * p2;
698 /* based on hardware requirement, prefer bigger m1,m2 values */
699 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
700 m2 = (((2*(fastclk * p * n / m1 )) +
701 refclk) / (2*refclk));
702 m = m1 * m2;
703 vco = updrate * m;
704 if (vco >= limit->vco.min && vco < limit->vco.max) {
705 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
706 absppm = (ppm > 0) ? ppm : (-ppm);
707 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
708 bestppm = 0;
709 flag = 1;
710 }
711 if (absppm < bestppm - 10) {
712 bestppm = absppm;
713 flag = 1;
714 }
715 if (flag) {
716 bestn = n;
717 bestm1 = m1;
718 bestm2 = m2;
719 bestp1 = p1;
720 bestp2 = p2;
721 flag = 0;
722 }
723 }
724 }
725 }
726 }
727 }
728 best_clock->n = bestn;
729 best_clock->m1 = bestm1;
730 best_clock->m2 = bestm2;
731 best_clock->p1 = bestp1;
732 best_clock->p2 = bestp2;
733
734 return true;
735 }
736
737 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
738 enum pipe pipe)
739 {
740 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
741 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
742
743 return intel_crtc->config.cpu_transcoder;
744 }
745
746 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
747 {
748 struct drm_i915_private *dev_priv = dev->dev_private;
749 u32 frame, frame_reg = PIPEFRAME(pipe);
750
751 frame = I915_READ(frame_reg);
752
753 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
754 DRM_DEBUG_KMS("vblank wait timed out\n");
755 }
756
757 /**
758 * intel_wait_for_vblank - wait for vblank on a given pipe
759 * @dev: drm device
760 * @pipe: pipe to wait for
761 *
762 * Wait for vblank to occur on a given pipe. Needed for various bits of
763 * mode setting code.
764 */
765 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
766 {
767 struct drm_i915_private *dev_priv = dev->dev_private;
768 int pipestat_reg = PIPESTAT(pipe);
769
770 if (INTEL_INFO(dev)->gen >= 5) {
771 ironlake_wait_for_vblank(dev, pipe);
772 return;
773 }
774
775 /* Clear existing vblank status. Note this will clear any other
776 * sticky status fields as well.
777 *
778 * This races with i915_driver_irq_handler() with the result
779 * that either function could miss a vblank event. Here it is not
780 * fatal, as we will either wait upon the next vblank interrupt or
781 * timeout. Generally speaking intel_wait_for_vblank() is only
782 * called during modeset at which time the GPU should be idle and
783 * should *not* be performing page flips and thus not waiting on
784 * vblanks...
785 * Currently, the result of us stealing a vblank from the irq
786 * handler is that a single frame will be skipped during swapbuffers.
787 */
788 I915_WRITE(pipestat_reg,
789 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
790
791 /* Wait for vblank interrupt bit to set */
792 if (wait_for(I915_READ(pipestat_reg) &
793 PIPE_VBLANK_INTERRUPT_STATUS,
794 50))
795 DRM_DEBUG_KMS("vblank wait timed out\n");
796 }
797
798 /*
799 * intel_wait_for_pipe_off - wait for pipe to turn off
800 * @dev: drm device
801 * @pipe: pipe to wait for
802 *
803 * After disabling a pipe, we can't wait for vblank in the usual way,
804 * spinning on the vblank interrupt status bit, since we won't actually
805 * see an interrupt when the pipe is disabled.
806 *
807 * On Gen4 and above:
808 * wait for the pipe register state bit to turn off
809 *
810 * Otherwise:
811 * wait for the display line value to settle (it usually
812 * ends up stopping at the start of the next frame).
813 *
814 */
815 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
816 {
817 struct drm_i915_private *dev_priv = dev->dev_private;
818 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
819 pipe);
820
821 if (INTEL_INFO(dev)->gen >= 4) {
822 int reg = PIPECONF(cpu_transcoder);
823
824 /* Wait for the Pipe State to go off */
825 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
826 100))
827 WARN(1, "pipe_off wait timed out\n");
828 } else {
829 u32 last_line, line_mask;
830 int reg = PIPEDSL(pipe);
831 unsigned long timeout = jiffies + msecs_to_jiffies(100);
832
833 if (IS_GEN2(dev))
834 line_mask = DSL_LINEMASK_GEN2;
835 else
836 line_mask = DSL_LINEMASK_GEN3;
837
838 /* Wait for the display line to settle */
839 do {
840 last_line = I915_READ(reg) & line_mask;
841 mdelay(5);
842 } while (((I915_READ(reg) & line_mask) != last_line) &&
843 time_after(timeout, jiffies));
844 if (time_after(jiffies, timeout))
845 WARN(1, "pipe_off wait timed out\n");
846 }
847 }
848
849 /*
850 * ibx_digital_port_connected - is the specified port connected?
851 * @dev_priv: i915 private structure
852 * @port: the port to test
853 *
854 * Returns true if @port is connected, false otherwise.
855 */
856 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
857 struct intel_digital_port *port)
858 {
859 u32 bit;
860
861 if (HAS_PCH_IBX(dev_priv->dev)) {
862 switch(port->port) {
863 case PORT_B:
864 bit = SDE_PORTB_HOTPLUG;
865 break;
866 case PORT_C:
867 bit = SDE_PORTC_HOTPLUG;
868 break;
869 case PORT_D:
870 bit = SDE_PORTD_HOTPLUG;
871 break;
872 default:
873 return true;
874 }
875 } else {
876 switch(port->port) {
877 case PORT_B:
878 bit = SDE_PORTB_HOTPLUG_CPT;
879 break;
880 case PORT_C:
881 bit = SDE_PORTC_HOTPLUG_CPT;
882 break;
883 case PORT_D:
884 bit = SDE_PORTD_HOTPLUG_CPT;
885 break;
886 default:
887 return true;
888 }
889 }
890
891 return I915_READ(SDEISR) & bit;
892 }
893
894 static const char *state_string(bool enabled)
895 {
896 return enabled ? "on" : "off";
897 }
898
899 /* Only for pre-ILK configs */
900 void assert_pll(struct drm_i915_private *dev_priv,
901 enum pipe pipe, bool state)
902 {
903 int reg;
904 u32 val;
905 bool cur_state;
906
907 reg = DPLL(pipe);
908 val = I915_READ(reg);
909 cur_state = !!(val & DPLL_VCO_ENABLE);
910 WARN(cur_state != state,
911 "PLL state assertion failure (expected %s, current %s)\n",
912 state_string(state), state_string(cur_state));
913 }
914
915 struct intel_shared_dpll *
916 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
917 {
918 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
919
920 if (crtc->config.shared_dpll < 0)
921 return NULL;
922
923 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
924 }
925
926 /* For ILK+ */
927 void assert_shared_dpll(struct drm_i915_private *dev_priv,
928 struct intel_shared_dpll *pll,
929 bool state)
930 {
931 bool cur_state;
932 struct intel_dpll_hw_state hw_state;
933
934 if (HAS_PCH_LPT(dev_priv->dev)) {
935 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
936 return;
937 }
938
939 if (WARN (!pll,
940 "asserting DPLL %s with no DPLL\n", state_string(state)))
941 return;
942
943 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
944 WARN(cur_state != state,
945 "%s assertion failure (expected %s, current %s)\n",
946 pll->name, state_string(state), state_string(cur_state));
947 }
948
949 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
950 enum pipe pipe, bool state)
951 {
952 int reg;
953 u32 val;
954 bool cur_state;
955 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
956 pipe);
957
958 if (HAS_DDI(dev_priv->dev)) {
959 /* DDI does not have a specific FDI_TX register */
960 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
961 val = I915_READ(reg);
962 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
963 } else {
964 reg = FDI_TX_CTL(pipe);
965 val = I915_READ(reg);
966 cur_state = !!(val & FDI_TX_ENABLE);
967 }
968 WARN(cur_state != state,
969 "FDI TX state assertion failure (expected %s, current %s)\n",
970 state_string(state), state_string(cur_state));
971 }
972 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
973 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
974
975 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
976 enum pipe pipe, bool state)
977 {
978 int reg;
979 u32 val;
980 bool cur_state;
981
982 reg = FDI_RX_CTL(pipe);
983 val = I915_READ(reg);
984 cur_state = !!(val & FDI_RX_ENABLE);
985 WARN(cur_state != state,
986 "FDI RX state assertion failure (expected %s, current %s)\n",
987 state_string(state), state_string(cur_state));
988 }
989 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
990 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
991
992 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
993 enum pipe pipe)
994 {
995 int reg;
996 u32 val;
997
998 /* ILK FDI PLL is always enabled */
999 if (dev_priv->info->gen == 5)
1000 return;
1001
1002 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1003 if (HAS_DDI(dev_priv->dev))
1004 return;
1005
1006 reg = FDI_TX_CTL(pipe);
1007 val = I915_READ(reg);
1008 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1009 }
1010
1011 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1012 enum pipe pipe, bool state)
1013 {
1014 int reg;
1015 u32 val;
1016 bool cur_state;
1017
1018 reg = FDI_RX_CTL(pipe);
1019 val = I915_READ(reg);
1020 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1021 WARN(cur_state != state,
1022 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1023 state_string(state), state_string(cur_state));
1024 }
1025
1026 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1027 enum pipe pipe)
1028 {
1029 int pp_reg, lvds_reg;
1030 u32 val;
1031 enum pipe panel_pipe = PIPE_A;
1032 bool locked = true;
1033
1034 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1035 pp_reg = PCH_PP_CONTROL;
1036 lvds_reg = PCH_LVDS;
1037 } else {
1038 pp_reg = PP_CONTROL;
1039 lvds_reg = LVDS;
1040 }
1041
1042 val = I915_READ(pp_reg);
1043 if (!(val & PANEL_POWER_ON) ||
1044 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1045 locked = false;
1046
1047 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1048 panel_pipe = PIPE_B;
1049
1050 WARN(panel_pipe == pipe && locked,
1051 "panel assertion failure, pipe %c regs locked\n",
1052 pipe_name(pipe));
1053 }
1054
1055 void assert_pipe(struct drm_i915_private *dev_priv,
1056 enum pipe pipe, bool state)
1057 {
1058 int reg;
1059 u32 val;
1060 bool cur_state;
1061 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1062 pipe);
1063
1064 /* if we need the pipe A quirk it must be always on */
1065 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1066 state = true;
1067
1068 if (!intel_display_power_enabled(dev_priv->dev,
1069 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1070 cur_state = false;
1071 } else {
1072 reg = PIPECONF(cpu_transcoder);
1073 val = I915_READ(reg);
1074 cur_state = !!(val & PIPECONF_ENABLE);
1075 }
1076
1077 WARN(cur_state != state,
1078 "pipe %c assertion failure (expected %s, current %s)\n",
1079 pipe_name(pipe), state_string(state), state_string(cur_state));
1080 }
1081
1082 static void assert_plane(struct drm_i915_private *dev_priv,
1083 enum plane plane, bool state)
1084 {
1085 int reg;
1086 u32 val;
1087 bool cur_state;
1088
1089 reg = DSPCNTR(plane);
1090 val = I915_READ(reg);
1091 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1092 WARN(cur_state != state,
1093 "plane %c assertion failure (expected %s, current %s)\n",
1094 plane_name(plane), state_string(state), state_string(cur_state));
1095 }
1096
1097 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1098 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1099
1100 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1101 enum pipe pipe)
1102 {
1103 struct drm_device *dev = dev_priv->dev;
1104 int reg, i;
1105 u32 val;
1106 int cur_pipe;
1107
1108 /* Primary planes are fixed to pipes on gen4+ */
1109 if (INTEL_INFO(dev)->gen >= 4) {
1110 reg = DSPCNTR(pipe);
1111 val = I915_READ(reg);
1112 WARN((val & DISPLAY_PLANE_ENABLE),
1113 "plane %c assertion failure, should be disabled but not\n",
1114 plane_name(pipe));
1115 return;
1116 }
1117
1118 /* Need to check both planes against the pipe */
1119 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
1120 reg = DSPCNTR(i);
1121 val = I915_READ(reg);
1122 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1123 DISPPLANE_SEL_PIPE_SHIFT;
1124 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1125 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1126 plane_name(i), pipe_name(pipe));
1127 }
1128 }
1129
1130 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1131 enum pipe pipe)
1132 {
1133 struct drm_device *dev = dev_priv->dev;
1134 int reg, i;
1135 u32 val;
1136
1137 if (IS_VALLEYVIEW(dev)) {
1138 for (i = 0; i < dev_priv->num_plane; i++) {
1139 reg = SPCNTR(pipe, i);
1140 val = I915_READ(reg);
1141 WARN((val & SP_ENABLE),
1142 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1143 sprite_name(pipe, i), pipe_name(pipe));
1144 }
1145 } else if (INTEL_INFO(dev)->gen >= 7) {
1146 reg = SPRCTL(pipe);
1147 val = I915_READ(reg);
1148 WARN((val & SPRITE_ENABLE),
1149 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1150 plane_name(pipe), pipe_name(pipe));
1151 } else if (INTEL_INFO(dev)->gen >= 5) {
1152 reg = DVSCNTR(pipe);
1153 val = I915_READ(reg);
1154 WARN((val & DVS_ENABLE),
1155 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1156 plane_name(pipe), pipe_name(pipe));
1157 }
1158 }
1159
1160 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1161 {
1162 u32 val;
1163 bool enabled;
1164
1165 if (HAS_PCH_LPT(dev_priv->dev)) {
1166 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1167 return;
1168 }
1169
1170 val = I915_READ(PCH_DREF_CONTROL);
1171 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1172 DREF_SUPERSPREAD_SOURCE_MASK));
1173 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1174 }
1175
1176 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1177 enum pipe pipe)
1178 {
1179 int reg;
1180 u32 val;
1181 bool enabled;
1182
1183 reg = PCH_TRANSCONF(pipe);
1184 val = I915_READ(reg);
1185 enabled = !!(val & TRANS_ENABLE);
1186 WARN(enabled,
1187 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1188 pipe_name(pipe));
1189 }
1190
1191 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1192 enum pipe pipe, u32 port_sel, u32 val)
1193 {
1194 if ((val & DP_PORT_EN) == 0)
1195 return false;
1196
1197 if (HAS_PCH_CPT(dev_priv->dev)) {
1198 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1199 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1200 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1201 return false;
1202 } else {
1203 if ((val & DP_PIPE_MASK) != (pipe << 30))
1204 return false;
1205 }
1206 return true;
1207 }
1208
1209 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1210 enum pipe pipe, u32 val)
1211 {
1212 if ((val & SDVO_ENABLE) == 0)
1213 return false;
1214
1215 if (HAS_PCH_CPT(dev_priv->dev)) {
1216 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1217 return false;
1218 } else {
1219 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1220 return false;
1221 }
1222 return true;
1223 }
1224
1225 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1226 enum pipe pipe, u32 val)
1227 {
1228 if ((val & LVDS_PORT_EN) == 0)
1229 return false;
1230
1231 if (HAS_PCH_CPT(dev_priv->dev)) {
1232 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1233 return false;
1234 } else {
1235 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1236 return false;
1237 }
1238 return true;
1239 }
1240
1241 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1242 enum pipe pipe, u32 val)
1243 {
1244 if ((val & ADPA_DAC_ENABLE) == 0)
1245 return false;
1246 if (HAS_PCH_CPT(dev_priv->dev)) {
1247 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1248 return false;
1249 } else {
1250 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1251 return false;
1252 }
1253 return true;
1254 }
1255
1256 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1257 enum pipe pipe, int reg, u32 port_sel)
1258 {
1259 u32 val = I915_READ(reg);
1260 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1261 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1262 reg, pipe_name(pipe));
1263
1264 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1265 && (val & DP_PIPEB_SELECT),
1266 "IBX PCH dp port still using transcoder B\n");
1267 }
1268
1269 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1270 enum pipe pipe, int reg)
1271 {
1272 u32 val = I915_READ(reg);
1273 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1274 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1275 reg, pipe_name(pipe));
1276
1277 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1278 && (val & SDVO_PIPE_B_SELECT),
1279 "IBX PCH hdmi port still using transcoder B\n");
1280 }
1281
1282 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1283 enum pipe pipe)
1284 {
1285 int reg;
1286 u32 val;
1287
1288 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1289 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1290 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1291
1292 reg = PCH_ADPA;
1293 val = I915_READ(reg);
1294 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1295 "PCH VGA enabled on transcoder %c, should be disabled\n",
1296 pipe_name(pipe));
1297
1298 reg = PCH_LVDS;
1299 val = I915_READ(reg);
1300 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1301 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1302 pipe_name(pipe));
1303
1304 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1305 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1306 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1307 }
1308
1309 static void vlv_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1310 {
1311 int reg;
1312 u32 val;
1313
1314 assert_pipe_disabled(dev_priv, pipe);
1315
1316 /* No really, not for ILK+ */
1317 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1318
1319 /* PLL is protected by panel, make sure we can write it */
1320 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1321 assert_panel_unlocked(dev_priv, pipe);
1322
1323 reg = DPLL(pipe);
1324 val = I915_READ(reg);
1325 val |= DPLL_VCO_ENABLE;
1326
1327 /* We do this three times for luck */
1328 I915_WRITE(reg, val);
1329 POSTING_READ(reg);
1330 udelay(150); /* wait for warmup */
1331 I915_WRITE(reg, val);
1332 POSTING_READ(reg);
1333 udelay(150); /* wait for warmup */
1334 I915_WRITE(reg, val);
1335 POSTING_READ(reg);
1336 udelay(150); /* wait for warmup */
1337 }
1338
1339 static void i9xx_enable_pll(struct intel_crtc *crtc)
1340 {
1341 struct drm_device *dev = crtc->base.dev;
1342 struct drm_i915_private *dev_priv = dev->dev_private;
1343 int reg = DPLL(crtc->pipe);
1344 u32 dpll = crtc->config.dpll_hw_state.dpll;
1345
1346 assert_pipe_disabled(dev_priv, crtc->pipe);
1347
1348 /* No really, not for ILK+ */
1349 BUG_ON(dev_priv->info->gen >= 5);
1350
1351 /* PLL is protected by panel, make sure we can write it */
1352 if (IS_MOBILE(dev) && !IS_I830(dev))
1353 assert_panel_unlocked(dev_priv, crtc->pipe);
1354
1355 I915_WRITE(reg, dpll);
1356
1357 /* Wait for the clocks to stabilize. */
1358 POSTING_READ(reg);
1359 udelay(150);
1360
1361 if (INTEL_INFO(dev)->gen >= 4) {
1362 I915_WRITE(DPLL_MD(crtc->pipe),
1363 crtc->config.dpll_hw_state.dpll_md);
1364 } else {
1365 /* The pixel multiplier can only be updated once the
1366 * DPLL is enabled and the clocks are stable.
1367 *
1368 * So write it again.
1369 */
1370 I915_WRITE(reg, dpll);
1371 }
1372
1373 /* We do this three times for luck */
1374 I915_WRITE(reg, dpll);
1375 POSTING_READ(reg);
1376 udelay(150); /* wait for warmup */
1377 I915_WRITE(reg, dpll);
1378 POSTING_READ(reg);
1379 udelay(150); /* wait for warmup */
1380 I915_WRITE(reg, dpll);
1381 POSTING_READ(reg);
1382 udelay(150); /* wait for warmup */
1383 }
1384
1385 /**
1386 * intel_disable_pll - disable a PLL
1387 * @dev_priv: i915 private structure
1388 * @pipe: pipe PLL to disable
1389 *
1390 * Disable the PLL for @pipe, making sure the pipe is off first.
1391 *
1392 * Note! This is for pre-ILK only.
1393 */
1394 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1395 {
1396 int reg;
1397 u32 val;
1398
1399 /* Don't disable pipe A or pipe A PLLs if needed */
1400 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1401 return;
1402
1403 /* Make sure the pipe isn't still relying on us */
1404 assert_pipe_disabled(dev_priv, pipe);
1405
1406 reg = DPLL(pipe);
1407 val = I915_READ(reg);
1408 val &= ~DPLL_VCO_ENABLE;
1409 I915_WRITE(reg, val);
1410 POSTING_READ(reg);
1411 }
1412
1413 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1414 {
1415 u32 port_mask;
1416
1417 if (!port)
1418 port_mask = DPLL_PORTB_READY_MASK;
1419 else
1420 port_mask = DPLL_PORTC_READY_MASK;
1421
1422 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1423 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1424 'B' + port, I915_READ(DPLL(0)));
1425 }
1426
1427 /**
1428 * ironlake_enable_shared_dpll - enable PCH PLL
1429 * @dev_priv: i915 private structure
1430 * @pipe: pipe PLL to enable
1431 *
1432 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1433 * drives the transcoder clock.
1434 */
1435 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1436 {
1437 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1438 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1439
1440 /* PCH PLLs only available on ILK, SNB and IVB */
1441 BUG_ON(dev_priv->info->gen < 5);
1442 if (WARN_ON(pll == NULL))
1443 return;
1444
1445 if (WARN_ON(pll->refcount == 0))
1446 return;
1447
1448 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1449 pll->name, pll->active, pll->on,
1450 crtc->base.base.id);
1451
1452 if (pll->active++) {
1453 WARN_ON(!pll->on);
1454 assert_shared_dpll_enabled(dev_priv, pll);
1455 return;
1456 }
1457 WARN_ON(pll->on);
1458
1459 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1460 pll->enable(dev_priv, pll);
1461 pll->on = true;
1462 }
1463
1464 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1465 {
1466 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1467 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1468
1469 /* PCH only available on ILK+ */
1470 BUG_ON(dev_priv->info->gen < 5);
1471 if (WARN_ON(pll == NULL))
1472 return;
1473
1474 if (WARN_ON(pll->refcount == 0))
1475 return;
1476
1477 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1478 pll->name, pll->active, pll->on,
1479 crtc->base.base.id);
1480
1481 if (WARN_ON(pll->active == 0)) {
1482 assert_shared_dpll_disabled(dev_priv, pll);
1483 return;
1484 }
1485
1486 assert_shared_dpll_enabled(dev_priv, pll);
1487 WARN_ON(!pll->on);
1488 if (--pll->active)
1489 return;
1490
1491 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1492 pll->disable(dev_priv, pll);
1493 pll->on = false;
1494 }
1495
1496 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1497 enum pipe pipe)
1498 {
1499 struct drm_device *dev = dev_priv->dev;
1500 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1501 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1502 uint32_t reg, val, pipeconf_val;
1503
1504 /* PCH only available on ILK+ */
1505 BUG_ON(dev_priv->info->gen < 5);
1506
1507 /* Make sure PCH DPLL is enabled */
1508 assert_shared_dpll_enabled(dev_priv,
1509 intel_crtc_to_shared_dpll(intel_crtc));
1510
1511 /* FDI must be feeding us bits for PCH ports */
1512 assert_fdi_tx_enabled(dev_priv, pipe);
1513 assert_fdi_rx_enabled(dev_priv, pipe);
1514
1515 if (HAS_PCH_CPT(dev)) {
1516 /* Workaround: Set the timing override bit before enabling the
1517 * pch transcoder. */
1518 reg = TRANS_CHICKEN2(pipe);
1519 val = I915_READ(reg);
1520 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1521 I915_WRITE(reg, val);
1522 }
1523
1524 reg = PCH_TRANSCONF(pipe);
1525 val = I915_READ(reg);
1526 pipeconf_val = I915_READ(PIPECONF(pipe));
1527
1528 if (HAS_PCH_IBX(dev_priv->dev)) {
1529 /*
1530 * make the BPC in transcoder be consistent with
1531 * that in pipeconf reg.
1532 */
1533 val &= ~PIPECONF_BPC_MASK;
1534 val |= pipeconf_val & PIPECONF_BPC_MASK;
1535 }
1536
1537 val &= ~TRANS_INTERLACE_MASK;
1538 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1539 if (HAS_PCH_IBX(dev_priv->dev) &&
1540 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1541 val |= TRANS_LEGACY_INTERLACED_ILK;
1542 else
1543 val |= TRANS_INTERLACED;
1544 else
1545 val |= TRANS_PROGRESSIVE;
1546
1547 I915_WRITE(reg, val | TRANS_ENABLE);
1548 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1549 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1550 }
1551
1552 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1553 enum transcoder cpu_transcoder)
1554 {
1555 u32 val, pipeconf_val;
1556
1557 /* PCH only available on ILK+ */
1558 BUG_ON(dev_priv->info->gen < 5);
1559
1560 /* FDI must be feeding us bits for PCH ports */
1561 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1562 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1563
1564 /* Workaround: set timing override bit. */
1565 val = I915_READ(_TRANSA_CHICKEN2);
1566 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1567 I915_WRITE(_TRANSA_CHICKEN2, val);
1568
1569 val = TRANS_ENABLE;
1570 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1571
1572 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1573 PIPECONF_INTERLACED_ILK)
1574 val |= TRANS_INTERLACED;
1575 else
1576 val |= TRANS_PROGRESSIVE;
1577
1578 I915_WRITE(LPT_TRANSCONF, val);
1579 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1580 DRM_ERROR("Failed to enable PCH transcoder\n");
1581 }
1582
1583 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1584 enum pipe pipe)
1585 {
1586 struct drm_device *dev = dev_priv->dev;
1587 uint32_t reg, val;
1588
1589 /* FDI relies on the transcoder */
1590 assert_fdi_tx_disabled(dev_priv, pipe);
1591 assert_fdi_rx_disabled(dev_priv, pipe);
1592
1593 /* Ports must be off as well */
1594 assert_pch_ports_disabled(dev_priv, pipe);
1595
1596 reg = PCH_TRANSCONF(pipe);
1597 val = I915_READ(reg);
1598 val &= ~TRANS_ENABLE;
1599 I915_WRITE(reg, val);
1600 /* wait for PCH transcoder off, transcoder state */
1601 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1602 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1603
1604 if (!HAS_PCH_IBX(dev)) {
1605 /* Workaround: Clear the timing override chicken bit again. */
1606 reg = TRANS_CHICKEN2(pipe);
1607 val = I915_READ(reg);
1608 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1609 I915_WRITE(reg, val);
1610 }
1611 }
1612
1613 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1614 {
1615 u32 val;
1616
1617 val = I915_READ(LPT_TRANSCONF);
1618 val &= ~TRANS_ENABLE;
1619 I915_WRITE(LPT_TRANSCONF, val);
1620 /* wait for PCH transcoder off, transcoder state */
1621 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1622 DRM_ERROR("Failed to disable PCH transcoder\n");
1623
1624 /* Workaround: clear timing override bit. */
1625 val = I915_READ(_TRANSA_CHICKEN2);
1626 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1627 I915_WRITE(_TRANSA_CHICKEN2, val);
1628 }
1629
1630 /**
1631 * intel_enable_pipe - enable a pipe, asserting requirements
1632 * @dev_priv: i915 private structure
1633 * @pipe: pipe to enable
1634 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1635 *
1636 * Enable @pipe, making sure that various hardware specific requirements
1637 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1638 *
1639 * @pipe should be %PIPE_A or %PIPE_B.
1640 *
1641 * Will wait until the pipe is actually running (i.e. first vblank) before
1642 * returning.
1643 */
1644 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1645 bool pch_port)
1646 {
1647 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1648 pipe);
1649 enum pipe pch_transcoder;
1650 int reg;
1651 u32 val;
1652
1653 assert_planes_disabled(dev_priv, pipe);
1654 assert_sprites_disabled(dev_priv, pipe);
1655
1656 if (HAS_PCH_LPT(dev_priv->dev))
1657 pch_transcoder = TRANSCODER_A;
1658 else
1659 pch_transcoder = pipe;
1660
1661 /*
1662 * A pipe without a PLL won't actually be able to drive bits from
1663 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1664 * need the check.
1665 */
1666 if (!HAS_PCH_SPLIT(dev_priv->dev))
1667 assert_pll_enabled(dev_priv, pipe);
1668 else {
1669 if (pch_port) {
1670 /* if driving the PCH, we need FDI enabled */
1671 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1672 assert_fdi_tx_pll_enabled(dev_priv,
1673 (enum pipe) cpu_transcoder);
1674 }
1675 /* FIXME: assert CPU port conditions for SNB+ */
1676 }
1677
1678 reg = PIPECONF(cpu_transcoder);
1679 val = I915_READ(reg);
1680 if (val & PIPECONF_ENABLE)
1681 return;
1682
1683 I915_WRITE(reg, val | PIPECONF_ENABLE);
1684 intel_wait_for_vblank(dev_priv->dev, pipe);
1685 }
1686
1687 /**
1688 * intel_disable_pipe - disable a pipe, asserting requirements
1689 * @dev_priv: i915 private structure
1690 * @pipe: pipe to disable
1691 *
1692 * Disable @pipe, making sure that various hardware specific requirements
1693 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1694 *
1695 * @pipe should be %PIPE_A or %PIPE_B.
1696 *
1697 * Will wait until the pipe has shut down before returning.
1698 */
1699 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1700 enum pipe pipe)
1701 {
1702 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1703 pipe);
1704 int reg;
1705 u32 val;
1706
1707 /*
1708 * Make sure planes won't keep trying to pump pixels to us,
1709 * or we might hang the display.
1710 */
1711 assert_planes_disabled(dev_priv, pipe);
1712 assert_sprites_disabled(dev_priv, pipe);
1713
1714 /* Don't disable pipe A or pipe A PLLs if needed */
1715 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1716 return;
1717
1718 reg = PIPECONF(cpu_transcoder);
1719 val = I915_READ(reg);
1720 if ((val & PIPECONF_ENABLE) == 0)
1721 return;
1722
1723 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1724 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1725 }
1726
1727 /*
1728 * Plane regs are double buffered, going from enabled->disabled needs a
1729 * trigger in order to latch. The display address reg provides this.
1730 */
1731 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1732 enum plane plane)
1733 {
1734 if (dev_priv->info->gen >= 4)
1735 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1736 else
1737 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1738 }
1739
1740 /**
1741 * intel_enable_plane - enable a display plane on a given pipe
1742 * @dev_priv: i915 private structure
1743 * @plane: plane to enable
1744 * @pipe: pipe being fed
1745 *
1746 * Enable @plane on @pipe, making sure that @pipe is running first.
1747 */
1748 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1749 enum plane plane, enum pipe pipe)
1750 {
1751 int reg;
1752 u32 val;
1753
1754 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1755 assert_pipe_enabled(dev_priv, pipe);
1756
1757 reg = DSPCNTR(plane);
1758 val = I915_READ(reg);
1759 if (val & DISPLAY_PLANE_ENABLE)
1760 return;
1761
1762 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1763 intel_flush_display_plane(dev_priv, plane);
1764 intel_wait_for_vblank(dev_priv->dev, pipe);
1765 }
1766
1767 /**
1768 * intel_disable_plane - disable a display plane
1769 * @dev_priv: i915 private structure
1770 * @plane: plane to disable
1771 * @pipe: pipe consuming the data
1772 *
1773 * Disable @plane; should be an independent operation.
1774 */
1775 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1776 enum plane plane, enum pipe pipe)
1777 {
1778 int reg;
1779 u32 val;
1780
1781 reg = DSPCNTR(plane);
1782 val = I915_READ(reg);
1783 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1784 return;
1785
1786 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1787 intel_flush_display_plane(dev_priv, plane);
1788 intel_wait_for_vblank(dev_priv->dev, pipe);
1789 }
1790
1791 static bool need_vtd_wa(struct drm_device *dev)
1792 {
1793 #ifdef CONFIG_INTEL_IOMMU
1794 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1795 return true;
1796 #endif
1797 return false;
1798 }
1799
1800 int
1801 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1802 struct drm_i915_gem_object *obj,
1803 struct intel_ring_buffer *pipelined)
1804 {
1805 struct drm_i915_private *dev_priv = dev->dev_private;
1806 u32 alignment;
1807 int ret;
1808
1809 switch (obj->tiling_mode) {
1810 case I915_TILING_NONE:
1811 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1812 alignment = 128 * 1024;
1813 else if (INTEL_INFO(dev)->gen >= 4)
1814 alignment = 4 * 1024;
1815 else
1816 alignment = 64 * 1024;
1817 break;
1818 case I915_TILING_X:
1819 /* pin() will align the object as required by fence */
1820 alignment = 0;
1821 break;
1822 case I915_TILING_Y:
1823 /* Despite that we check this in framebuffer_init userspace can
1824 * screw us over and change the tiling after the fact. Only
1825 * pinned buffers can't change their tiling. */
1826 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1827 return -EINVAL;
1828 default:
1829 BUG();
1830 }
1831
1832 /* Note that the w/a also requires 64 PTE of padding following the
1833 * bo. We currently fill all unused PTE with the shadow page and so
1834 * we should always have valid PTE following the scanout preventing
1835 * the VT-d warning.
1836 */
1837 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1838 alignment = 256 * 1024;
1839
1840 dev_priv->mm.interruptible = false;
1841 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1842 if (ret)
1843 goto err_interruptible;
1844
1845 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1846 * fence, whereas 965+ only requires a fence if using
1847 * framebuffer compression. For simplicity, we always install
1848 * a fence as the cost is not that onerous.
1849 */
1850 ret = i915_gem_object_get_fence(obj);
1851 if (ret)
1852 goto err_unpin;
1853
1854 i915_gem_object_pin_fence(obj);
1855
1856 dev_priv->mm.interruptible = true;
1857 return 0;
1858
1859 err_unpin:
1860 i915_gem_object_unpin(obj);
1861 err_interruptible:
1862 dev_priv->mm.interruptible = true;
1863 return ret;
1864 }
1865
1866 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1867 {
1868 i915_gem_object_unpin_fence(obj);
1869 i915_gem_object_unpin(obj);
1870 }
1871
1872 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1873 * is assumed to be a power-of-two. */
1874 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1875 unsigned int tiling_mode,
1876 unsigned int cpp,
1877 unsigned int pitch)
1878 {
1879 if (tiling_mode != I915_TILING_NONE) {
1880 unsigned int tile_rows, tiles;
1881
1882 tile_rows = *y / 8;
1883 *y %= 8;
1884
1885 tiles = *x / (512/cpp);
1886 *x %= 512/cpp;
1887
1888 return tile_rows * pitch * 8 + tiles * 4096;
1889 } else {
1890 unsigned int offset;
1891
1892 offset = *y * pitch + *x * cpp;
1893 *y = 0;
1894 *x = (offset & 4095) / cpp;
1895 return offset & -4096;
1896 }
1897 }
1898
1899 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1900 int x, int y)
1901 {
1902 struct drm_device *dev = crtc->dev;
1903 struct drm_i915_private *dev_priv = dev->dev_private;
1904 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1905 struct intel_framebuffer *intel_fb;
1906 struct drm_i915_gem_object *obj;
1907 int plane = intel_crtc->plane;
1908 unsigned long linear_offset;
1909 u32 dspcntr;
1910 u32 reg;
1911
1912 switch (plane) {
1913 case 0:
1914 case 1:
1915 break;
1916 default:
1917 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1918 return -EINVAL;
1919 }
1920
1921 intel_fb = to_intel_framebuffer(fb);
1922 obj = intel_fb->obj;
1923
1924 reg = DSPCNTR(plane);
1925 dspcntr = I915_READ(reg);
1926 /* Mask out pixel format bits in case we change it */
1927 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1928 switch (fb->pixel_format) {
1929 case DRM_FORMAT_C8:
1930 dspcntr |= DISPPLANE_8BPP;
1931 break;
1932 case DRM_FORMAT_XRGB1555:
1933 case DRM_FORMAT_ARGB1555:
1934 dspcntr |= DISPPLANE_BGRX555;
1935 break;
1936 case DRM_FORMAT_RGB565:
1937 dspcntr |= DISPPLANE_BGRX565;
1938 break;
1939 case DRM_FORMAT_XRGB8888:
1940 case DRM_FORMAT_ARGB8888:
1941 dspcntr |= DISPPLANE_BGRX888;
1942 break;
1943 case DRM_FORMAT_XBGR8888:
1944 case DRM_FORMAT_ABGR8888:
1945 dspcntr |= DISPPLANE_RGBX888;
1946 break;
1947 case DRM_FORMAT_XRGB2101010:
1948 case DRM_FORMAT_ARGB2101010:
1949 dspcntr |= DISPPLANE_BGRX101010;
1950 break;
1951 case DRM_FORMAT_XBGR2101010:
1952 case DRM_FORMAT_ABGR2101010:
1953 dspcntr |= DISPPLANE_RGBX101010;
1954 break;
1955 default:
1956 BUG();
1957 }
1958
1959 if (INTEL_INFO(dev)->gen >= 4) {
1960 if (obj->tiling_mode != I915_TILING_NONE)
1961 dspcntr |= DISPPLANE_TILED;
1962 else
1963 dspcntr &= ~DISPPLANE_TILED;
1964 }
1965
1966 if (IS_G4X(dev))
1967 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1968
1969 I915_WRITE(reg, dspcntr);
1970
1971 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1972
1973 if (INTEL_INFO(dev)->gen >= 4) {
1974 intel_crtc->dspaddr_offset =
1975 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1976 fb->bits_per_pixel / 8,
1977 fb->pitches[0]);
1978 linear_offset -= intel_crtc->dspaddr_offset;
1979 } else {
1980 intel_crtc->dspaddr_offset = linear_offset;
1981 }
1982
1983 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1984 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
1985 fb->pitches[0]);
1986 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1987 if (INTEL_INFO(dev)->gen >= 4) {
1988 I915_MODIFY_DISPBASE(DSPSURF(plane),
1989 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
1990 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1991 I915_WRITE(DSPLINOFF(plane), linear_offset);
1992 } else
1993 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
1994 POSTING_READ(reg);
1995
1996 return 0;
1997 }
1998
1999 static int ironlake_update_plane(struct drm_crtc *crtc,
2000 struct drm_framebuffer *fb, int x, int y)
2001 {
2002 struct drm_device *dev = crtc->dev;
2003 struct drm_i915_private *dev_priv = dev->dev_private;
2004 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2005 struct intel_framebuffer *intel_fb;
2006 struct drm_i915_gem_object *obj;
2007 int plane = intel_crtc->plane;
2008 unsigned long linear_offset;
2009 u32 dspcntr;
2010 u32 reg;
2011
2012 switch (plane) {
2013 case 0:
2014 case 1:
2015 case 2:
2016 break;
2017 default:
2018 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2019 return -EINVAL;
2020 }
2021
2022 intel_fb = to_intel_framebuffer(fb);
2023 obj = intel_fb->obj;
2024
2025 reg = DSPCNTR(plane);
2026 dspcntr = I915_READ(reg);
2027 /* Mask out pixel format bits in case we change it */
2028 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2029 switch (fb->pixel_format) {
2030 case DRM_FORMAT_C8:
2031 dspcntr |= DISPPLANE_8BPP;
2032 break;
2033 case DRM_FORMAT_RGB565:
2034 dspcntr |= DISPPLANE_BGRX565;
2035 break;
2036 case DRM_FORMAT_XRGB8888:
2037 case DRM_FORMAT_ARGB8888:
2038 dspcntr |= DISPPLANE_BGRX888;
2039 break;
2040 case DRM_FORMAT_XBGR8888:
2041 case DRM_FORMAT_ABGR8888:
2042 dspcntr |= DISPPLANE_RGBX888;
2043 break;
2044 case DRM_FORMAT_XRGB2101010:
2045 case DRM_FORMAT_ARGB2101010:
2046 dspcntr |= DISPPLANE_BGRX101010;
2047 break;
2048 case DRM_FORMAT_XBGR2101010:
2049 case DRM_FORMAT_ABGR2101010:
2050 dspcntr |= DISPPLANE_RGBX101010;
2051 break;
2052 default:
2053 BUG();
2054 }
2055
2056 if (obj->tiling_mode != I915_TILING_NONE)
2057 dspcntr |= DISPPLANE_TILED;
2058 else
2059 dspcntr &= ~DISPPLANE_TILED;
2060
2061 /* must disable */
2062 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2063
2064 I915_WRITE(reg, dspcntr);
2065
2066 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2067 intel_crtc->dspaddr_offset =
2068 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2069 fb->bits_per_pixel / 8,
2070 fb->pitches[0]);
2071 linear_offset -= intel_crtc->dspaddr_offset;
2072
2073 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2074 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2075 fb->pitches[0]);
2076 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2077 I915_MODIFY_DISPBASE(DSPSURF(plane),
2078 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2079 if (IS_HASWELL(dev)) {
2080 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2081 } else {
2082 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2083 I915_WRITE(DSPLINOFF(plane), linear_offset);
2084 }
2085 POSTING_READ(reg);
2086
2087 return 0;
2088 }
2089
2090 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2091 static int
2092 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2093 int x, int y, enum mode_set_atomic state)
2094 {
2095 struct drm_device *dev = crtc->dev;
2096 struct drm_i915_private *dev_priv = dev->dev_private;
2097
2098 if (dev_priv->display.disable_fbc)
2099 dev_priv->display.disable_fbc(dev);
2100 intel_increase_pllclock(crtc);
2101
2102 return dev_priv->display.update_plane(crtc, fb, x, y);
2103 }
2104
2105 void intel_display_handle_reset(struct drm_device *dev)
2106 {
2107 struct drm_i915_private *dev_priv = dev->dev_private;
2108 struct drm_crtc *crtc;
2109
2110 /*
2111 * Flips in the rings have been nuked by the reset,
2112 * so complete all pending flips so that user space
2113 * will get its events and not get stuck.
2114 *
2115 * Also update the base address of all primary
2116 * planes to the the last fb to make sure we're
2117 * showing the correct fb after a reset.
2118 *
2119 * Need to make two loops over the crtcs so that we
2120 * don't try to grab a crtc mutex before the
2121 * pending_flip_queue really got woken up.
2122 */
2123
2124 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2125 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2126 enum plane plane = intel_crtc->plane;
2127
2128 intel_prepare_page_flip(dev, plane);
2129 intel_finish_page_flip_plane(dev, plane);
2130 }
2131
2132 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2133 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2134
2135 mutex_lock(&crtc->mutex);
2136 if (intel_crtc->active)
2137 dev_priv->display.update_plane(crtc, crtc->fb,
2138 crtc->x, crtc->y);
2139 mutex_unlock(&crtc->mutex);
2140 }
2141 }
2142
2143 static int
2144 intel_finish_fb(struct drm_framebuffer *old_fb)
2145 {
2146 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2147 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2148 bool was_interruptible = dev_priv->mm.interruptible;
2149 int ret;
2150
2151 /* Big Hammer, we also need to ensure that any pending
2152 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2153 * current scanout is retired before unpinning the old
2154 * framebuffer.
2155 *
2156 * This should only fail upon a hung GPU, in which case we
2157 * can safely continue.
2158 */
2159 dev_priv->mm.interruptible = false;
2160 ret = i915_gem_object_finish_gpu(obj);
2161 dev_priv->mm.interruptible = was_interruptible;
2162
2163 return ret;
2164 }
2165
2166 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2167 {
2168 struct drm_device *dev = crtc->dev;
2169 struct drm_i915_master_private *master_priv;
2170 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2171
2172 if (!dev->primary->master)
2173 return;
2174
2175 master_priv = dev->primary->master->driver_priv;
2176 if (!master_priv->sarea_priv)
2177 return;
2178
2179 switch (intel_crtc->pipe) {
2180 case 0:
2181 master_priv->sarea_priv->pipeA_x = x;
2182 master_priv->sarea_priv->pipeA_y = y;
2183 break;
2184 case 1:
2185 master_priv->sarea_priv->pipeB_x = x;
2186 master_priv->sarea_priv->pipeB_y = y;
2187 break;
2188 default:
2189 break;
2190 }
2191 }
2192
2193 static int
2194 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2195 struct drm_framebuffer *fb)
2196 {
2197 struct drm_device *dev = crtc->dev;
2198 struct drm_i915_private *dev_priv = dev->dev_private;
2199 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2200 struct drm_framebuffer *old_fb;
2201 int ret;
2202
2203 /* no fb bound */
2204 if (!fb) {
2205 DRM_ERROR("No FB bound\n");
2206 return 0;
2207 }
2208
2209 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2210 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2211 plane_name(intel_crtc->plane),
2212 INTEL_INFO(dev)->num_pipes);
2213 return -EINVAL;
2214 }
2215
2216 mutex_lock(&dev->struct_mutex);
2217 ret = intel_pin_and_fence_fb_obj(dev,
2218 to_intel_framebuffer(fb)->obj,
2219 NULL);
2220 if (ret != 0) {
2221 mutex_unlock(&dev->struct_mutex);
2222 DRM_ERROR("pin & fence failed\n");
2223 return ret;
2224 }
2225
2226 /* Update pipe size and adjust fitter if needed */
2227 if (i915_fastboot) {
2228 I915_WRITE(PIPESRC(intel_crtc->pipe),
2229 ((crtc->mode.hdisplay - 1) << 16) |
2230 (crtc->mode.vdisplay - 1));
2231 if (!intel_crtc->config.pch_pfit.size &&
2232 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2233 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2234 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2235 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2236 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2237 }
2238 }
2239
2240 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2241 if (ret) {
2242 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2243 mutex_unlock(&dev->struct_mutex);
2244 DRM_ERROR("failed to update base address\n");
2245 return ret;
2246 }
2247
2248 old_fb = crtc->fb;
2249 crtc->fb = fb;
2250 crtc->x = x;
2251 crtc->y = y;
2252
2253 if (old_fb) {
2254 if (intel_crtc->active && old_fb != fb)
2255 intel_wait_for_vblank(dev, intel_crtc->pipe);
2256 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2257 }
2258
2259 intel_update_fbc(dev);
2260 mutex_unlock(&dev->struct_mutex);
2261
2262 intel_crtc_update_sarea_pos(crtc, x, y);
2263
2264 return 0;
2265 }
2266
2267 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2268 {
2269 struct drm_device *dev = crtc->dev;
2270 struct drm_i915_private *dev_priv = dev->dev_private;
2271 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2272 int pipe = intel_crtc->pipe;
2273 u32 reg, temp;
2274
2275 /* enable normal train */
2276 reg = FDI_TX_CTL(pipe);
2277 temp = I915_READ(reg);
2278 if (IS_IVYBRIDGE(dev)) {
2279 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2280 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2281 } else {
2282 temp &= ~FDI_LINK_TRAIN_NONE;
2283 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2284 }
2285 I915_WRITE(reg, temp);
2286
2287 reg = FDI_RX_CTL(pipe);
2288 temp = I915_READ(reg);
2289 if (HAS_PCH_CPT(dev)) {
2290 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2291 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2292 } else {
2293 temp &= ~FDI_LINK_TRAIN_NONE;
2294 temp |= FDI_LINK_TRAIN_NONE;
2295 }
2296 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2297
2298 /* wait one idle pattern time */
2299 POSTING_READ(reg);
2300 udelay(1000);
2301
2302 /* IVB wants error correction enabled */
2303 if (IS_IVYBRIDGE(dev))
2304 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2305 FDI_FE_ERRC_ENABLE);
2306 }
2307
2308 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2309 {
2310 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2311 }
2312
2313 static void ivb_modeset_global_resources(struct drm_device *dev)
2314 {
2315 struct drm_i915_private *dev_priv = dev->dev_private;
2316 struct intel_crtc *pipe_B_crtc =
2317 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2318 struct intel_crtc *pipe_C_crtc =
2319 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2320 uint32_t temp;
2321
2322 /*
2323 * When everything is off disable fdi C so that we could enable fdi B
2324 * with all lanes. Note that we don't care about enabled pipes without
2325 * an enabled pch encoder.
2326 */
2327 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2328 !pipe_has_enabled_pch(pipe_C_crtc)) {
2329 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2330 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2331
2332 temp = I915_READ(SOUTH_CHICKEN1);
2333 temp &= ~FDI_BC_BIFURCATION_SELECT;
2334 DRM_DEBUG_KMS("disabling fdi C rx\n");
2335 I915_WRITE(SOUTH_CHICKEN1, temp);
2336 }
2337 }
2338
2339 /* The FDI link training functions for ILK/Ibexpeak. */
2340 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2341 {
2342 struct drm_device *dev = crtc->dev;
2343 struct drm_i915_private *dev_priv = dev->dev_private;
2344 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2345 int pipe = intel_crtc->pipe;
2346 int plane = intel_crtc->plane;
2347 u32 reg, temp, tries;
2348
2349 /* FDI needs bits from pipe & plane first */
2350 assert_pipe_enabled(dev_priv, pipe);
2351 assert_plane_enabled(dev_priv, plane);
2352
2353 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2354 for train result */
2355 reg = FDI_RX_IMR(pipe);
2356 temp = I915_READ(reg);
2357 temp &= ~FDI_RX_SYMBOL_LOCK;
2358 temp &= ~FDI_RX_BIT_LOCK;
2359 I915_WRITE(reg, temp);
2360 I915_READ(reg);
2361 udelay(150);
2362
2363 /* enable CPU FDI TX and PCH FDI RX */
2364 reg = FDI_TX_CTL(pipe);
2365 temp = I915_READ(reg);
2366 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2367 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2368 temp &= ~FDI_LINK_TRAIN_NONE;
2369 temp |= FDI_LINK_TRAIN_PATTERN_1;
2370 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2371
2372 reg = FDI_RX_CTL(pipe);
2373 temp = I915_READ(reg);
2374 temp &= ~FDI_LINK_TRAIN_NONE;
2375 temp |= FDI_LINK_TRAIN_PATTERN_1;
2376 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2377
2378 POSTING_READ(reg);
2379 udelay(150);
2380
2381 /* Ironlake workaround, enable clock pointer after FDI enable*/
2382 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2383 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2384 FDI_RX_PHASE_SYNC_POINTER_EN);
2385
2386 reg = FDI_RX_IIR(pipe);
2387 for (tries = 0; tries < 5; tries++) {
2388 temp = I915_READ(reg);
2389 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2390
2391 if ((temp & FDI_RX_BIT_LOCK)) {
2392 DRM_DEBUG_KMS("FDI train 1 done.\n");
2393 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2394 break;
2395 }
2396 }
2397 if (tries == 5)
2398 DRM_ERROR("FDI train 1 fail!\n");
2399
2400 /* Train 2 */
2401 reg = FDI_TX_CTL(pipe);
2402 temp = I915_READ(reg);
2403 temp &= ~FDI_LINK_TRAIN_NONE;
2404 temp |= FDI_LINK_TRAIN_PATTERN_2;
2405 I915_WRITE(reg, temp);
2406
2407 reg = FDI_RX_CTL(pipe);
2408 temp = I915_READ(reg);
2409 temp &= ~FDI_LINK_TRAIN_NONE;
2410 temp |= FDI_LINK_TRAIN_PATTERN_2;
2411 I915_WRITE(reg, temp);
2412
2413 POSTING_READ(reg);
2414 udelay(150);
2415
2416 reg = FDI_RX_IIR(pipe);
2417 for (tries = 0; tries < 5; tries++) {
2418 temp = I915_READ(reg);
2419 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2420
2421 if (temp & FDI_RX_SYMBOL_LOCK) {
2422 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2423 DRM_DEBUG_KMS("FDI train 2 done.\n");
2424 break;
2425 }
2426 }
2427 if (tries == 5)
2428 DRM_ERROR("FDI train 2 fail!\n");
2429
2430 DRM_DEBUG_KMS("FDI train done\n");
2431
2432 }
2433
2434 static const int snb_b_fdi_train_param[] = {
2435 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2436 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2437 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2438 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2439 };
2440
2441 /* The FDI link training functions for SNB/Cougarpoint. */
2442 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2443 {
2444 struct drm_device *dev = crtc->dev;
2445 struct drm_i915_private *dev_priv = dev->dev_private;
2446 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2447 int pipe = intel_crtc->pipe;
2448 u32 reg, temp, i, retry;
2449
2450 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2451 for train result */
2452 reg = FDI_RX_IMR(pipe);
2453 temp = I915_READ(reg);
2454 temp &= ~FDI_RX_SYMBOL_LOCK;
2455 temp &= ~FDI_RX_BIT_LOCK;
2456 I915_WRITE(reg, temp);
2457
2458 POSTING_READ(reg);
2459 udelay(150);
2460
2461 /* enable CPU FDI TX and PCH FDI RX */
2462 reg = FDI_TX_CTL(pipe);
2463 temp = I915_READ(reg);
2464 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2465 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2466 temp &= ~FDI_LINK_TRAIN_NONE;
2467 temp |= FDI_LINK_TRAIN_PATTERN_1;
2468 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2469 /* SNB-B */
2470 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2471 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2472
2473 I915_WRITE(FDI_RX_MISC(pipe),
2474 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2475
2476 reg = FDI_RX_CTL(pipe);
2477 temp = I915_READ(reg);
2478 if (HAS_PCH_CPT(dev)) {
2479 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2480 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2481 } else {
2482 temp &= ~FDI_LINK_TRAIN_NONE;
2483 temp |= FDI_LINK_TRAIN_PATTERN_1;
2484 }
2485 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2486
2487 POSTING_READ(reg);
2488 udelay(150);
2489
2490 for (i = 0; i < 4; i++) {
2491 reg = FDI_TX_CTL(pipe);
2492 temp = I915_READ(reg);
2493 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2494 temp |= snb_b_fdi_train_param[i];
2495 I915_WRITE(reg, temp);
2496
2497 POSTING_READ(reg);
2498 udelay(500);
2499
2500 for (retry = 0; retry < 5; retry++) {
2501 reg = FDI_RX_IIR(pipe);
2502 temp = I915_READ(reg);
2503 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2504 if (temp & FDI_RX_BIT_LOCK) {
2505 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2506 DRM_DEBUG_KMS("FDI train 1 done.\n");
2507 break;
2508 }
2509 udelay(50);
2510 }
2511 if (retry < 5)
2512 break;
2513 }
2514 if (i == 4)
2515 DRM_ERROR("FDI train 1 fail!\n");
2516
2517 /* Train 2 */
2518 reg = FDI_TX_CTL(pipe);
2519 temp = I915_READ(reg);
2520 temp &= ~FDI_LINK_TRAIN_NONE;
2521 temp |= FDI_LINK_TRAIN_PATTERN_2;
2522 if (IS_GEN6(dev)) {
2523 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2524 /* SNB-B */
2525 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2526 }
2527 I915_WRITE(reg, temp);
2528
2529 reg = FDI_RX_CTL(pipe);
2530 temp = I915_READ(reg);
2531 if (HAS_PCH_CPT(dev)) {
2532 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2533 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2534 } else {
2535 temp &= ~FDI_LINK_TRAIN_NONE;
2536 temp |= FDI_LINK_TRAIN_PATTERN_2;
2537 }
2538 I915_WRITE(reg, temp);
2539
2540 POSTING_READ(reg);
2541 udelay(150);
2542
2543 for (i = 0; i < 4; i++) {
2544 reg = FDI_TX_CTL(pipe);
2545 temp = I915_READ(reg);
2546 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2547 temp |= snb_b_fdi_train_param[i];
2548 I915_WRITE(reg, temp);
2549
2550 POSTING_READ(reg);
2551 udelay(500);
2552
2553 for (retry = 0; retry < 5; retry++) {
2554 reg = FDI_RX_IIR(pipe);
2555 temp = I915_READ(reg);
2556 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2557 if (temp & FDI_RX_SYMBOL_LOCK) {
2558 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2559 DRM_DEBUG_KMS("FDI train 2 done.\n");
2560 break;
2561 }
2562 udelay(50);
2563 }
2564 if (retry < 5)
2565 break;
2566 }
2567 if (i == 4)
2568 DRM_ERROR("FDI train 2 fail!\n");
2569
2570 DRM_DEBUG_KMS("FDI train done.\n");
2571 }
2572
2573 /* Manual link training for Ivy Bridge A0 parts */
2574 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2575 {
2576 struct drm_device *dev = crtc->dev;
2577 struct drm_i915_private *dev_priv = dev->dev_private;
2578 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2579 int pipe = intel_crtc->pipe;
2580 u32 reg, temp, i;
2581
2582 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2583 for train result */
2584 reg = FDI_RX_IMR(pipe);
2585 temp = I915_READ(reg);
2586 temp &= ~FDI_RX_SYMBOL_LOCK;
2587 temp &= ~FDI_RX_BIT_LOCK;
2588 I915_WRITE(reg, temp);
2589
2590 POSTING_READ(reg);
2591 udelay(150);
2592
2593 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2594 I915_READ(FDI_RX_IIR(pipe)));
2595
2596 /* enable CPU FDI TX and PCH FDI RX */
2597 reg = FDI_TX_CTL(pipe);
2598 temp = I915_READ(reg);
2599 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2600 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2601 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2602 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2603 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2604 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2605 temp |= FDI_COMPOSITE_SYNC;
2606 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2607
2608 I915_WRITE(FDI_RX_MISC(pipe),
2609 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2610
2611 reg = FDI_RX_CTL(pipe);
2612 temp = I915_READ(reg);
2613 temp &= ~FDI_LINK_TRAIN_AUTO;
2614 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2615 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2616 temp |= FDI_COMPOSITE_SYNC;
2617 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2618
2619 POSTING_READ(reg);
2620 udelay(150);
2621
2622 for (i = 0; i < 4; i++) {
2623 reg = FDI_TX_CTL(pipe);
2624 temp = I915_READ(reg);
2625 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2626 temp |= snb_b_fdi_train_param[i];
2627 I915_WRITE(reg, temp);
2628
2629 POSTING_READ(reg);
2630 udelay(500);
2631
2632 reg = FDI_RX_IIR(pipe);
2633 temp = I915_READ(reg);
2634 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2635
2636 if (temp & FDI_RX_BIT_LOCK ||
2637 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2638 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2639 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2640 break;
2641 }
2642 }
2643 if (i == 4)
2644 DRM_ERROR("FDI train 1 fail!\n");
2645
2646 /* Train 2 */
2647 reg = FDI_TX_CTL(pipe);
2648 temp = I915_READ(reg);
2649 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2650 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2651 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2652 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2653 I915_WRITE(reg, temp);
2654
2655 reg = FDI_RX_CTL(pipe);
2656 temp = I915_READ(reg);
2657 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2658 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2659 I915_WRITE(reg, temp);
2660
2661 POSTING_READ(reg);
2662 udelay(150);
2663
2664 for (i = 0; i < 4; i++) {
2665 reg = FDI_TX_CTL(pipe);
2666 temp = I915_READ(reg);
2667 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2668 temp |= snb_b_fdi_train_param[i];
2669 I915_WRITE(reg, temp);
2670
2671 POSTING_READ(reg);
2672 udelay(500);
2673
2674 reg = FDI_RX_IIR(pipe);
2675 temp = I915_READ(reg);
2676 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2677
2678 if (temp & FDI_RX_SYMBOL_LOCK) {
2679 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2680 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2681 break;
2682 }
2683 }
2684 if (i == 4)
2685 DRM_ERROR("FDI train 2 fail!\n");
2686
2687 DRM_DEBUG_KMS("FDI train done.\n");
2688 }
2689
2690 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2691 {
2692 struct drm_device *dev = intel_crtc->base.dev;
2693 struct drm_i915_private *dev_priv = dev->dev_private;
2694 int pipe = intel_crtc->pipe;
2695 u32 reg, temp;
2696
2697
2698 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2699 reg = FDI_RX_CTL(pipe);
2700 temp = I915_READ(reg);
2701 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2702 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2703 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2704 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2705
2706 POSTING_READ(reg);
2707 udelay(200);
2708
2709 /* Switch from Rawclk to PCDclk */
2710 temp = I915_READ(reg);
2711 I915_WRITE(reg, temp | FDI_PCDCLK);
2712
2713 POSTING_READ(reg);
2714 udelay(200);
2715
2716 /* Enable CPU FDI TX PLL, always on for Ironlake */
2717 reg = FDI_TX_CTL(pipe);
2718 temp = I915_READ(reg);
2719 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2720 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2721
2722 POSTING_READ(reg);
2723 udelay(100);
2724 }
2725 }
2726
2727 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2728 {
2729 struct drm_device *dev = intel_crtc->base.dev;
2730 struct drm_i915_private *dev_priv = dev->dev_private;
2731 int pipe = intel_crtc->pipe;
2732 u32 reg, temp;
2733
2734 /* Switch from PCDclk to Rawclk */
2735 reg = FDI_RX_CTL(pipe);
2736 temp = I915_READ(reg);
2737 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2738
2739 /* Disable CPU FDI TX PLL */
2740 reg = FDI_TX_CTL(pipe);
2741 temp = I915_READ(reg);
2742 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2743
2744 POSTING_READ(reg);
2745 udelay(100);
2746
2747 reg = FDI_RX_CTL(pipe);
2748 temp = I915_READ(reg);
2749 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2750
2751 /* Wait for the clocks to turn off. */
2752 POSTING_READ(reg);
2753 udelay(100);
2754 }
2755
2756 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2757 {
2758 struct drm_device *dev = crtc->dev;
2759 struct drm_i915_private *dev_priv = dev->dev_private;
2760 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2761 int pipe = intel_crtc->pipe;
2762 u32 reg, temp;
2763
2764 /* disable CPU FDI tx and PCH FDI rx */
2765 reg = FDI_TX_CTL(pipe);
2766 temp = I915_READ(reg);
2767 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2768 POSTING_READ(reg);
2769
2770 reg = FDI_RX_CTL(pipe);
2771 temp = I915_READ(reg);
2772 temp &= ~(0x7 << 16);
2773 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2774 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2775
2776 POSTING_READ(reg);
2777 udelay(100);
2778
2779 /* Ironlake workaround, disable clock pointer after downing FDI */
2780 if (HAS_PCH_IBX(dev)) {
2781 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2782 }
2783
2784 /* still set train pattern 1 */
2785 reg = FDI_TX_CTL(pipe);
2786 temp = I915_READ(reg);
2787 temp &= ~FDI_LINK_TRAIN_NONE;
2788 temp |= FDI_LINK_TRAIN_PATTERN_1;
2789 I915_WRITE(reg, temp);
2790
2791 reg = FDI_RX_CTL(pipe);
2792 temp = I915_READ(reg);
2793 if (HAS_PCH_CPT(dev)) {
2794 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2795 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2796 } else {
2797 temp &= ~FDI_LINK_TRAIN_NONE;
2798 temp |= FDI_LINK_TRAIN_PATTERN_1;
2799 }
2800 /* BPC in FDI rx is consistent with that in PIPECONF */
2801 temp &= ~(0x07 << 16);
2802 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2803 I915_WRITE(reg, temp);
2804
2805 POSTING_READ(reg);
2806 udelay(100);
2807 }
2808
2809 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2810 {
2811 struct drm_device *dev = crtc->dev;
2812 struct drm_i915_private *dev_priv = dev->dev_private;
2813 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2814 unsigned long flags;
2815 bool pending;
2816
2817 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2818 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2819 return false;
2820
2821 spin_lock_irqsave(&dev->event_lock, flags);
2822 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2823 spin_unlock_irqrestore(&dev->event_lock, flags);
2824
2825 return pending;
2826 }
2827
2828 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2829 {
2830 struct drm_device *dev = crtc->dev;
2831 struct drm_i915_private *dev_priv = dev->dev_private;
2832
2833 if (crtc->fb == NULL)
2834 return;
2835
2836 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2837
2838 wait_event(dev_priv->pending_flip_queue,
2839 !intel_crtc_has_pending_flip(crtc));
2840
2841 mutex_lock(&dev->struct_mutex);
2842 intel_finish_fb(crtc->fb);
2843 mutex_unlock(&dev->struct_mutex);
2844 }
2845
2846 /* Program iCLKIP clock to the desired frequency */
2847 static void lpt_program_iclkip(struct drm_crtc *crtc)
2848 {
2849 struct drm_device *dev = crtc->dev;
2850 struct drm_i915_private *dev_priv = dev->dev_private;
2851 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2852 u32 temp;
2853
2854 mutex_lock(&dev_priv->dpio_lock);
2855
2856 /* It is necessary to ungate the pixclk gate prior to programming
2857 * the divisors, and gate it back when it is done.
2858 */
2859 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2860
2861 /* Disable SSCCTL */
2862 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2863 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2864 SBI_SSCCTL_DISABLE,
2865 SBI_ICLK);
2866
2867 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2868 if (crtc->mode.clock == 20000) {
2869 auxdiv = 1;
2870 divsel = 0x41;
2871 phaseinc = 0x20;
2872 } else {
2873 /* The iCLK virtual clock root frequency is in MHz,
2874 * but the crtc->mode.clock in in KHz. To get the divisors,
2875 * it is necessary to divide one by another, so we
2876 * convert the virtual clock precision to KHz here for higher
2877 * precision.
2878 */
2879 u32 iclk_virtual_root_freq = 172800 * 1000;
2880 u32 iclk_pi_range = 64;
2881 u32 desired_divisor, msb_divisor_value, pi_value;
2882
2883 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2884 msb_divisor_value = desired_divisor / iclk_pi_range;
2885 pi_value = desired_divisor % iclk_pi_range;
2886
2887 auxdiv = 0;
2888 divsel = msb_divisor_value - 2;
2889 phaseinc = pi_value;
2890 }
2891
2892 /* This should not happen with any sane values */
2893 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2894 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2895 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2896 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2897
2898 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2899 crtc->mode.clock,
2900 auxdiv,
2901 divsel,
2902 phasedir,
2903 phaseinc);
2904
2905 /* Program SSCDIVINTPHASE6 */
2906 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2907 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2908 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2909 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2910 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2911 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2912 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2913 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2914
2915 /* Program SSCAUXDIV */
2916 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2917 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2918 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2919 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2920
2921 /* Enable modulator and associated divider */
2922 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2923 temp &= ~SBI_SSCCTL_DISABLE;
2924 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2925
2926 /* Wait for initialization time */
2927 udelay(24);
2928
2929 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2930
2931 mutex_unlock(&dev_priv->dpio_lock);
2932 }
2933
2934 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2935 enum pipe pch_transcoder)
2936 {
2937 struct drm_device *dev = crtc->base.dev;
2938 struct drm_i915_private *dev_priv = dev->dev_private;
2939 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2940
2941 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2942 I915_READ(HTOTAL(cpu_transcoder)));
2943 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2944 I915_READ(HBLANK(cpu_transcoder)));
2945 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2946 I915_READ(HSYNC(cpu_transcoder)));
2947
2948 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2949 I915_READ(VTOTAL(cpu_transcoder)));
2950 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2951 I915_READ(VBLANK(cpu_transcoder)));
2952 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2953 I915_READ(VSYNC(cpu_transcoder)));
2954 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2955 I915_READ(VSYNCSHIFT(cpu_transcoder)));
2956 }
2957
2958 /*
2959 * Enable PCH resources required for PCH ports:
2960 * - PCH PLLs
2961 * - FDI training & RX/TX
2962 * - update transcoder timings
2963 * - DP transcoding bits
2964 * - transcoder
2965 */
2966 static void ironlake_pch_enable(struct drm_crtc *crtc)
2967 {
2968 struct drm_device *dev = crtc->dev;
2969 struct drm_i915_private *dev_priv = dev->dev_private;
2970 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2971 int pipe = intel_crtc->pipe;
2972 u32 reg, temp;
2973
2974 assert_pch_transcoder_disabled(dev_priv, pipe);
2975
2976 /* Write the TU size bits before fdi link training, so that error
2977 * detection works. */
2978 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2979 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2980
2981 /* For PCH output, training FDI link */
2982 dev_priv->display.fdi_link_train(crtc);
2983
2984 /* XXX: pch pll's can be enabled any time before we enable the PCH
2985 * transcoder, and we actually should do this to not upset any PCH
2986 * transcoder that already use the clock when we share it.
2987 *
2988 * Note that enable_shared_dpll tries to do the right thing, but
2989 * get_shared_dpll unconditionally resets the pll - we need that to have
2990 * the right LVDS enable sequence. */
2991 ironlake_enable_shared_dpll(intel_crtc);
2992
2993 if (HAS_PCH_CPT(dev)) {
2994 u32 sel;
2995
2996 temp = I915_READ(PCH_DPLL_SEL);
2997 temp |= TRANS_DPLL_ENABLE(pipe);
2998 sel = TRANS_DPLLB_SEL(pipe);
2999 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3000 temp |= sel;
3001 else
3002 temp &= ~sel;
3003 I915_WRITE(PCH_DPLL_SEL, temp);
3004 }
3005
3006 /* set transcoder timing, panel must allow it */
3007 assert_panel_unlocked(dev_priv, pipe);
3008 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3009
3010 intel_fdi_normal_train(crtc);
3011
3012 /* For PCH DP, enable TRANS_DP_CTL */
3013 if (HAS_PCH_CPT(dev) &&
3014 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3015 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3016 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3017 reg = TRANS_DP_CTL(pipe);
3018 temp = I915_READ(reg);
3019 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3020 TRANS_DP_SYNC_MASK |
3021 TRANS_DP_BPC_MASK);
3022 temp |= (TRANS_DP_OUTPUT_ENABLE |
3023 TRANS_DP_ENH_FRAMING);
3024 temp |= bpc << 9; /* same format but at 11:9 */
3025
3026 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3027 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3028 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3029 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3030
3031 switch (intel_trans_dp_port_sel(crtc)) {
3032 case PCH_DP_B:
3033 temp |= TRANS_DP_PORT_SEL_B;
3034 break;
3035 case PCH_DP_C:
3036 temp |= TRANS_DP_PORT_SEL_C;
3037 break;
3038 case PCH_DP_D:
3039 temp |= TRANS_DP_PORT_SEL_D;
3040 break;
3041 default:
3042 BUG();
3043 }
3044
3045 I915_WRITE(reg, temp);
3046 }
3047
3048 ironlake_enable_pch_transcoder(dev_priv, pipe);
3049 }
3050
3051 static void lpt_pch_enable(struct drm_crtc *crtc)
3052 {
3053 struct drm_device *dev = crtc->dev;
3054 struct drm_i915_private *dev_priv = dev->dev_private;
3055 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3056 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3057
3058 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3059
3060 lpt_program_iclkip(crtc);
3061
3062 /* Set transcoder timing. */
3063 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3064
3065 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3066 }
3067
3068 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3069 {
3070 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3071
3072 if (pll == NULL)
3073 return;
3074
3075 if (pll->refcount == 0) {
3076 WARN(1, "bad %s refcount\n", pll->name);
3077 return;
3078 }
3079
3080 if (--pll->refcount == 0) {
3081 WARN_ON(pll->on);
3082 WARN_ON(pll->active);
3083 }
3084
3085 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3086 }
3087
3088 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3089 {
3090 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3091 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3092 enum intel_dpll_id i;
3093
3094 if (pll) {
3095 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3096 crtc->base.base.id, pll->name);
3097 intel_put_shared_dpll(crtc);
3098 }
3099
3100 if (HAS_PCH_IBX(dev_priv->dev)) {
3101 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3102 i = (enum intel_dpll_id) crtc->pipe;
3103 pll = &dev_priv->shared_dplls[i];
3104
3105 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3106 crtc->base.base.id, pll->name);
3107
3108 goto found;
3109 }
3110
3111 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3112 pll = &dev_priv->shared_dplls[i];
3113
3114 /* Only want to check enabled timings first */
3115 if (pll->refcount == 0)
3116 continue;
3117
3118 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3119 sizeof(pll->hw_state)) == 0) {
3120 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3121 crtc->base.base.id,
3122 pll->name, pll->refcount, pll->active);
3123
3124 goto found;
3125 }
3126 }
3127
3128 /* Ok no matching timings, maybe there's a free one? */
3129 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3130 pll = &dev_priv->shared_dplls[i];
3131 if (pll->refcount == 0) {
3132 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3133 crtc->base.base.id, pll->name);
3134 goto found;
3135 }
3136 }
3137
3138 return NULL;
3139
3140 found:
3141 crtc->config.shared_dpll = i;
3142 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3143 pipe_name(crtc->pipe));
3144
3145 if (pll->active == 0) {
3146 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3147 sizeof(pll->hw_state));
3148
3149 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3150 WARN_ON(pll->on);
3151 assert_shared_dpll_disabled(dev_priv, pll);
3152
3153 pll->mode_set(dev_priv, pll);
3154 }
3155 pll->refcount++;
3156
3157 return pll;
3158 }
3159
3160 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3161 {
3162 struct drm_i915_private *dev_priv = dev->dev_private;
3163 int dslreg = PIPEDSL(pipe);
3164 u32 temp;
3165
3166 temp = I915_READ(dslreg);
3167 udelay(500);
3168 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3169 if (wait_for(I915_READ(dslreg) != temp, 5))
3170 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3171 }
3172 }
3173
3174 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3175 {
3176 struct drm_device *dev = crtc->base.dev;
3177 struct drm_i915_private *dev_priv = dev->dev_private;
3178 int pipe = crtc->pipe;
3179
3180 if (crtc->config.pch_pfit.size) {
3181 /* Force use of hard-coded filter coefficients
3182 * as some pre-programmed values are broken,
3183 * e.g. x201.
3184 */
3185 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3186 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3187 PF_PIPE_SEL_IVB(pipe));
3188 else
3189 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3190 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3191 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3192 }
3193 }
3194
3195 static void intel_enable_planes(struct drm_crtc *crtc)
3196 {
3197 struct drm_device *dev = crtc->dev;
3198 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3199 struct intel_plane *intel_plane;
3200
3201 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3202 if (intel_plane->pipe == pipe)
3203 intel_plane_restore(&intel_plane->base);
3204 }
3205
3206 static void intel_disable_planes(struct drm_crtc *crtc)
3207 {
3208 struct drm_device *dev = crtc->dev;
3209 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3210 struct intel_plane *intel_plane;
3211
3212 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3213 if (intel_plane->pipe == pipe)
3214 intel_plane_disable(&intel_plane->base);
3215 }
3216
3217 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3218 {
3219 struct drm_device *dev = crtc->dev;
3220 struct drm_i915_private *dev_priv = dev->dev_private;
3221 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3222 struct intel_encoder *encoder;
3223 int pipe = intel_crtc->pipe;
3224 int plane = intel_crtc->plane;
3225
3226 WARN_ON(!crtc->enabled);
3227
3228 if (intel_crtc->active)
3229 return;
3230
3231 intel_crtc->active = true;
3232
3233 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3234 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3235
3236 intel_update_watermarks(dev);
3237
3238 for_each_encoder_on_crtc(dev, crtc, encoder)
3239 if (encoder->pre_enable)
3240 encoder->pre_enable(encoder);
3241
3242 if (intel_crtc->config.has_pch_encoder) {
3243 /* Note: FDI PLL enabling _must_ be done before we enable the
3244 * cpu pipes, hence this is separate from all the other fdi/pch
3245 * enabling. */
3246 ironlake_fdi_pll_enable(intel_crtc);
3247 } else {
3248 assert_fdi_tx_disabled(dev_priv, pipe);
3249 assert_fdi_rx_disabled(dev_priv, pipe);
3250 }
3251
3252 ironlake_pfit_enable(intel_crtc);
3253
3254 /*
3255 * On ILK+ LUT must be loaded before the pipe is running but with
3256 * clocks enabled
3257 */
3258 intel_crtc_load_lut(crtc);
3259
3260 intel_enable_pipe(dev_priv, pipe,
3261 intel_crtc->config.has_pch_encoder);
3262 intel_enable_plane(dev_priv, plane, pipe);
3263 intel_enable_planes(crtc);
3264 intel_crtc_update_cursor(crtc, true);
3265
3266 if (intel_crtc->config.has_pch_encoder)
3267 ironlake_pch_enable(crtc);
3268
3269 mutex_lock(&dev->struct_mutex);
3270 intel_update_fbc(dev);
3271 mutex_unlock(&dev->struct_mutex);
3272
3273 for_each_encoder_on_crtc(dev, crtc, encoder)
3274 encoder->enable(encoder);
3275
3276 if (HAS_PCH_CPT(dev))
3277 cpt_verify_modeset(dev, intel_crtc->pipe);
3278
3279 /*
3280 * There seems to be a race in PCH platform hw (at least on some
3281 * outputs) where an enabled pipe still completes any pageflip right
3282 * away (as if the pipe is off) instead of waiting for vblank. As soon
3283 * as the first vblank happend, everything works as expected. Hence just
3284 * wait for one vblank before returning to avoid strange things
3285 * happening.
3286 */
3287 intel_wait_for_vblank(dev, intel_crtc->pipe);
3288 }
3289
3290 /* IPS only exists on ULT machines and is tied to pipe A. */
3291 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3292 {
3293 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3294 }
3295
3296 static void hsw_enable_ips(struct intel_crtc *crtc)
3297 {
3298 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3299
3300 if (!crtc->config.ips_enabled)
3301 return;
3302
3303 /* We can only enable IPS after we enable a plane and wait for a vblank.
3304 * We guarantee that the plane is enabled by calling intel_enable_ips
3305 * only after intel_enable_plane. And intel_enable_plane already waits
3306 * for a vblank, so all we need to do here is to enable the IPS bit. */
3307 assert_plane_enabled(dev_priv, crtc->plane);
3308 I915_WRITE(IPS_CTL, IPS_ENABLE);
3309 }
3310
3311 static void hsw_disable_ips(struct intel_crtc *crtc)
3312 {
3313 struct drm_device *dev = crtc->base.dev;
3314 struct drm_i915_private *dev_priv = dev->dev_private;
3315
3316 if (!crtc->config.ips_enabled)
3317 return;
3318
3319 assert_plane_enabled(dev_priv, crtc->plane);
3320 I915_WRITE(IPS_CTL, 0);
3321
3322 /* We need to wait for a vblank before we can disable the plane. */
3323 intel_wait_for_vblank(dev, crtc->pipe);
3324 }
3325
3326 static void haswell_crtc_enable(struct drm_crtc *crtc)
3327 {
3328 struct drm_device *dev = crtc->dev;
3329 struct drm_i915_private *dev_priv = dev->dev_private;
3330 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3331 struct intel_encoder *encoder;
3332 int pipe = intel_crtc->pipe;
3333 int plane = intel_crtc->plane;
3334
3335 WARN_ON(!crtc->enabled);
3336
3337 if (intel_crtc->active)
3338 return;
3339
3340 intel_crtc->active = true;
3341
3342 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3343 if (intel_crtc->config.has_pch_encoder)
3344 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3345
3346 intel_update_watermarks(dev);
3347
3348 if (intel_crtc->config.has_pch_encoder)
3349 dev_priv->display.fdi_link_train(crtc);
3350
3351 for_each_encoder_on_crtc(dev, crtc, encoder)
3352 if (encoder->pre_enable)
3353 encoder->pre_enable(encoder);
3354
3355 intel_ddi_enable_pipe_clock(intel_crtc);
3356
3357 ironlake_pfit_enable(intel_crtc);
3358
3359 /*
3360 * On ILK+ LUT must be loaded before the pipe is running but with
3361 * clocks enabled
3362 */
3363 intel_crtc_load_lut(crtc);
3364
3365 intel_ddi_set_pipe_settings(crtc);
3366 intel_ddi_enable_transcoder_func(crtc);
3367
3368 intel_enable_pipe(dev_priv, pipe,
3369 intel_crtc->config.has_pch_encoder);
3370 intel_enable_plane(dev_priv, plane, pipe);
3371 intel_enable_planes(crtc);
3372 intel_crtc_update_cursor(crtc, true);
3373
3374 hsw_enable_ips(intel_crtc);
3375
3376 if (intel_crtc->config.has_pch_encoder)
3377 lpt_pch_enable(crtc);
3378
3379 mutex_lock(&dev->struct_mutex);
3380 intel_update_fbc(dev);
3381 mutex_unlock(&dev->struct_mutex);
3382
3383 for_each_encoder_on_crtc(dev, crtc, encoder)
3384 encoder->enable(encoder);
3385
3386 /*
3387 * There seems to be a race in PCH platform hw (at least on some
3388 * outputs) where an enabled pipe still completes any pageflip right
3389 * away (as if the pipe is off) instead of waiting for vblank. As soon
3390 * as the first vblank happend, everything works as expected. Hence just
3391 * wait for one vblank before returning to avoid strange things
3392 * happening.
3393 */
3394 intel_wait_for_vblank(dev, intel_crtc->pipe);
3395 }
3396
3397 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3398 {
3399 struct drm_device *dev = crtc->base.dev;
3400 struct drm_i915_private *dev_priv = dev->dev_private;
3401 int pipe = crtc->pipe;
3402
3403 /* To avoid upsetting the power well on haswell only disable the pfit if
3404 * it's in use. The hw state code will make sure we get this right. */
3405 if (crtc->config.pch_pfit.size) {
3406 I915_WRITE(PF_CTL(pipe), 0);
3407 I915_WRITE(PF_WIN_POS(pipe), 0);
3408 I915_WRITE(PF_WIN_SZ(pipe), 0);
3409 }
3410 }
3411
3412 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3413 {
3414 struct drm_device *dev = crtc->dev;
3415 struct drm_i915_private *dev_priv = dev->dev_private;
3416 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3417 struct intel_encoder *encoder;
3418 int pipe = intel_crtc->pipe;
3419 int plane = intel_crtc->plane;
3420 u32 reg, temp;
3421
3422
3423 if (!intel_crtc->active)
3424 return;
3425
3426 for_each_encoder_on_crtc(dev, crtc, encoder)
3427 encoder->disable(encoder);
3428
3429 intel_crtc_wait_for_pending_flips(crtc);
3430 drm_vblank_off(dev, pipe);
3431
3432 if (dev_priv->fbc.plane == plane)
3433 intel_disable_fbc(dev);
3434
3435 intel_crtc_update_cursor(crtc, false);
3436 intel_disable_planes(crtc);
3437 intel_disable_plane(dev_priv, plane, pipe);
3438
3439 if (intel_crtc->config.has_pch_encoder)
3440 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3441
3442 intel_disable_pipe(dev_priv, pipe);
3443
3444 ironlake_pfit_disable(intel_crtc);
3445
3446 for_each_encoder_on_crtc(dev, crtc, encoder)
3447 if (encoder->post_disable)
3448 encoder->post_disable(encoder);
3449
3450 if (intel_crtc->config.has_pch_encoder) {
3451 ironlake_fdi_disable(crtc);
3452
3453 ironlake_disable_pch_transcoder(dev_priv, pipe);
3454 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3455
3456 if (HAS_PCH_CPT(dev)) {
3457 /* disable TRANS_DP_CTL */
3458 reg = TRANS_DP_CTL(pipe);
3459 temp = I915_READ(reg);
3460 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3461 TRANS_DP_PORT_SEL_MASK);
3462 temp |= TRANS_DP_PORT_SEL_NONE;
3463 I915_WRITE(reg, temp);
3464
3465 /* disable DPLL_SEL */
3466 temp = I915_READ(PCH_DPLL_SEL);
3467 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3468 I915_WRITE(PCH_DPLL_SEL, temp);
3469 }
3470
3471 /* disable PCH DPLL */
3472 intel_disable_shared_dpll(intel_crtc);
3473
3474 ironlake_fdi_pll_disable(intel_crtc);
3475 }
3476
3477 intel_crtc->active = false;
3478 intel_update_watermarks(dev);
3479
3480 mutex_lock(&dev->struct_mutex);
3481 intel_update_fbc(dev);
3482 mutex_unlock(&dev->struct_mutex);
3483 }
3484
3485 static void haswell_crtc_disable(struct drm_crtc *crtc)
3486 {
3487 struct drm_device *dev = crtc->dev;
3488 struct drm_i915_private *dev_priv = dev->dev_private;
3489 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3490 struct intel_encoder *encoder;
3491 int pipe = intel_crtc->pipe;
3492 int plane = intel_crtc->plane;
3493 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3494
3495 if (!intel_crtc->active)
3496 return;
3497
3498 for_each_encoder_on_crtc(dev, crtc, encoder)
3499 encoder->disable(encoder);
3500
3501 intel_crtc_wait_for_pending_flips(crtc);
3502 drm_vblank_off(dev, pipe);
3503
3504 /* FBC must be disabled before disabling the plane on HSW. */
3505 if (dev_priv->fbc.plane == plane)
3506 intel_disable_fbc(dev);
3507
3508 hsw_disable_ips(intel_crtc);
3509
3510 intel_crtc_update_cursor(crtc, false);
3511 intel_disable_planes(crtc);
3512 intel_disable_plane(dev_priv, plane, pipe);
3513
3514 if (intel_crtc->config.has_pch_encoder)
3515 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3516 intel_disable_pipe(dev_priv, pipe);
3517
3518 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3519
3520 ironlake_pfit_disable(intel_crtc);
3521
3522 intel_ddi_disable_pipe_clock(intel_crtc);
3523
3524 for_each_encoder_on_crtc(dev, crtc, encoder)
3525 if (encoder->post_disable)
3526 encoder->post_disable(encoder);
3527
3528 if (intel_crtc->config.has_pch_encoder) {
3529 lpt_disable_pch_transcoder(dev_priv);
3530 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3531 intel_ddi_fdi_disable(crtc);
3532 }
3533
3534 intel_crtc->active = false;
3535 intel_update_watermarks(dev);
3536
3537 mutex_lock(&dev->struct_mutex);
3538 intel_update_fbc(dev);
3539 mutex_unlock(&dev->struct_mutex);
3540 }
3541
3542 static void ironlake_crtc_off(struct drm_crtc *crtc)
3543 {
3544 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3545 intel_put_shared_dpll(intel_crtc);
3546 }
3547
3548 static void haswell_crtc_off(struct drm_crtc *crtc)
3549 {
3550 intel_ddi_put_crtc_pll(crtc);
3551 }
3552
3553 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3554 {
3555 if (!enable && intel_crtc->overlay) {
3556 struct drm_device *dev = intel_crtc->base.dev;
3557 struct drm_i915_private *dev_priv = dev->dev_private;
3558
3559 mutex_lock(&dev->struct_mutex);
3560 dev_priv->mm.interruptible = false;
3561 (void) intel_overlay_switch_off(intel_crtc->overlay);
3562 dev_priv->mm.interruptible = true;
3563 mutex_unlock(&dev->struct_mutex);
3564 }
3565
3566 /* Let userspace switch the overlay on again. In most cases userspace
3567 * has to recompute where to put it anyway.
3568 */
3569 }
3570
3571 /**
3572 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3573 * cursor plane briefly if not already running after enabling the display
3574 * plane.
3575 * This workaround avoids occasional blank screens when self refresh is
3576 * enabled.
3577 */
3578 static void
3579 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3580 {
3581 u32 cntl = I915_READ(CURCNTR(pipe));
3582
3583 if ((cntl & CURSOR_MODE) == 0) {
3584 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3585
3586 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3587 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3588 intel_wait_for_vblank(dev_priv->dev, pipe);
3589 I915_WRITE(CURCNTR(pipe), cntl);
3590 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3591 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3592 }
3593 }
3594
3595 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3596 {
3597 struct drm_device *dev = crtc->base.dev;
3598 struct drm_i915_private *dev_priv = dev->dev_private;
3599 struct intel_crtc_config *pipe_config = &crtc->config;
3600
3601 if (!crtc->config.gmch_pfit.control)
3602 return;
3603
3604 /*
3605 * The panel fitter should only be adjusted whilst the pipe is disabled,
3606 * according to register description and PRM.
3607 */
3608 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3609 assert_pipe_disabled(dev_priv, crtc->pipe);
3610
3611 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3612 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3613
3614 /* Border color in case we don't scale up to the full screen. Black by
3615 * default, change to something else for debugging. */
3616 I915_WRITE(BCLRPAT(crtc->pipe), 0);
3617 }
3618
3619 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3620 {
3621 struct drm_device *dev = crtc->dev;
3622 struct drm_i915_private *dev_priv = dev->dev_private;
3623 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3624 struct intel_encoder *encoder;
3625 int pipe = intel_crtc->pipe;
3626 int plane = intel_crtc->plane;
3627
3628 WARN_ON(!crtc->enabled);
3629
3630 if (intel_crtc->active)
3631 return;
3632
3633 intel_crtc->active = true;
3634 intel_update_watermarks(dev);
3635
3636 mutex_lock(&dev_priv->dpio_lock);
3637
3638 for_each_encoder_on_crtc(dev, crtc, encoder)
3639 if (encoder->pre_pll_enable)
3640 encoder->pre_pll_enable(encoder);
3641
3642 vlv_enable_pll(dev_priv, pipe);
3643
3644 for_each_encoder_on_crtc(dev, crtc, encoder)
3645 if (encoder->pre_enable)
3646 encoder->pre_enable(encoder);
3647
3648 /* VLV wants encoder enabling _before_ the pipe is up. */
3649 for_each_encoder_on_crtc(dev, crtc, encoder)
3650 encoder->enable(encoder);
3651
3652 i9xx_pfit_enable(intel_crtc);
3653
3654 intel_crtc_load_lut(crtc);
3655
3656 intel_enable_pipe(dev_priv, pipe, false);
3657 intel_enable_plane(dev_priv, plane, pipe);
3658 intel_enable_planes(crtc);
3659 intel_crtc_update_cursor(crtc, true);
3660
3661 intel_update_fbc(dev);
3662
3663 mutex_unlock(&dev_priv->dpio_lock);
3664 }
3665
3666 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3667 {
3668 struct drm_device *dev = crtc->dev;
3669 struct drm_i915_private *dev_priv = dev->dev_private;
3670 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3671 struct intel_encoder *encoder;
3672 int pipe = intel_crtc->pipe;
3673 int plane = intel_crtc->plane;
3674
3675 WARN_ON(!crtc->enabled);
3676
3677 if (intel_crtc->active)
3678 return;
3679
3680 intel_crtc->active = true;
3681 intel_update_watermarks(dev);
3682
3683 for_each_encoder_on_crtc(dev, crtc, encoder)
3684 if (encoder->pre_enable)
3685 encoder->pre_enable(encoder);
3686
3687 i9xx_enable_pll(intel_crtc);
3688
3689 i9xx_pfit_enable(intel_crtc);
3690
3691 intel_crtc_load_lut(crtc);
3692
3693 intel_enable_pipe(dev_priv, pipe, false);
3694 intel_enable_plane(dev_priv, plane, pipe);
3695 intel_enable_planes(crtc);
3696 /* The fixup needs to happen before cursor is enabled */
3697 if (IS_G4X(dev))
3698 g4x_fixup_plane(dev_priv, pipe);
3699 intel_crtc_update_cursor(crtc, true);
3700
3701 /* Give the overlay scaler a chance to enable if it's on this pipe */
3702 intel_crtc_dpms_overlay(intel_crtc, true);
3703
3704 intel_update_fbc(dev);
3705
3706 for_each_encoder_on_crtc(dev, crtc, encoder)
3707 encoder->enable(encoder);
3708 }
3709
3710 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3711 {
3712 struct drm_device *dev = crtc->base.dev;
3713 struct drm_i915_private *dev_priv = dev->dev_private;
3714
3715 if (!crtc->config.gmch_pfit.control)
3716 return;
3717
3718 assert_pipe_disabled(dev_priv, crtc->pipe);
3719
3720 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3721 I915_READ(PFIT_CONTROL));
3722 I915_WRITE(PFIT_CONTROL, 0);
3723 }
3724
3725 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3726 {
3727 struct drm_device *dev = crtc->dev;
3728 struct drm_i915_private *dev_priv = dev->dev_private;
3729 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3730 struct intel_encoder *encoder;
3731 int pipe = intel_crtc->pipe;
3732 int plane = intel_crtc->plane;
3733
3734 if (!intel_crtc->active)
3735 return;
3736
3737 for_each_encoder_on_crtc(dev, crtc, encoder)
3738 encoder->disable(encoder);
3739
3740 /* Give the overlay scaler a chance to disable if it's on this pipe */
3741 intel_crtc_wait_for_pending_flips(crtc);
3742 drm_vblank_off(dev, pipe);
3743
3744 if (dev_priv->fbc.plane == plane)
3745 intel_disable_fbc(dev);
3746
3747 intel_crtc_dpms_overlay(intel_crtc, false);
3748 intel_crtc_update_cursor(crtc, false);
3749 intel_disable_planes(crtc);
3750 intel_disable_plane(dev_priv, plane, pipe);
3751
3752 intel_disable_pipe(dev_priv, pipe);
3753
3754 i9xx_pfit_disable(intel_crtc);
3755
3756 for_each_encoder_on_crtc(dev, crtc, encoder)
3757 if (encoder->post_disable)
3758 encoder->post_disable(encoder);
3759
3760 intel_disable_pll(dev_priv, pipe);
3761
3762 intel_crtc->active = false;
3763 intel_update_fbc(dev);
3764 intel_update_watermarks(dev);
3765 }
3766
3767 static void i9xx_crtc_off(struct drm_crtc *crtc)
3768 {
3769 }
3770
3771 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3772 bool enabled)
3773 {
3774 struct drm_device *dev = crtc->dev;
3775 struct drm_i915_master_private *master_priv;
3776 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3777 int pipe = intel_crtc->pipe;
3778
3779 if (!dev->primary->master)
3780 return;
3781
3782 master_priv = dev->primary->master->driver_priv;
3783 if (!master_priv->sarea_priv)
3784 return;
3785
3786 switch (pipe) {
3787 case 0:
3788 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3789 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3790 break;
3791 case 1:
3792 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3793 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3794 break;
3795 default:
3796 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3797 break;
3798 }
3799 }
3800
3801 /**
3802 * Sets the power management mode of the pipe and plane.
3803 */
3804 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3805 {
3806 struct drm_device *dev = crtc->dev;
3807 struct drm_i915_private *dev_priv = dev->dev_private;
3808 struct intel_encoder *intel_encoder;
3809 bool enable = false;
3810
3811 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3812 enable |= intel_encoder->connectors_active;
3813
3814 if (enable)
3815 dev_priv->display.crtc_enable(crtc);
3816 else
3817 dev_priv->display.crtc_disable(crtc);
3818
3819 intel_crtc_update_sarea(crtc, enable);
3820 }
3821
3822 static void intel_crtc_disable(struct drm_crtc *crtc)
3823 {
3824 struct drm_device *dev = crtc->dev;
3825 struct drm_connector *connector;
3826 struct drm_i915_private *dev_priv = dev->dev_private;
3827 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3828
3829 /* crtc should still be enabled when we disable it. */
3830 WARN_ON(!crtc->enabled);
3831
3832 dev_priv->display.crtc_disable(crtc);
3833 intel_crtc->eld_vld = false;
3834 intel_crtc_update_sarea(crtc, false);
3835 dev_priv->display.off(crtc);
3836
3837 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3838 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3839
3840 if (crtc->fb) {
3841 mutex_lock(&dev->struct_mutex);
3842 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3843 mutex_unlock(&dev->struct_mutex);
3844 crtc->fb = NULL;
3845 }
3846
3847 /* Update computed state. */
3848 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3849 if (!connector->encoder || !connector->encoder->crtc)
3850 continue;
3851
3852 if (connector->encoder->crtc != crtc)
3853 continue;
3854
3855 connector->dpms = DRM_MODE_DPMS_OFF;
3856 to_intel_encoder(connector->encoder)->connectors_active = false;
3857 }
3858 }
3859
3860 void intel_modeset_disable(struct drm_device *dev)
3861 {
3862 struct drm_crtc *crtc;
3863
3864 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3865 if (crtc->enabled)
3866 intel_crtc_disable(crtc);
3867 }
3868 }
3869
3870 void intel_encoder_destroy(struct drm_encoder *encoder)
3871 {
3872 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3873
3874 drm_encoder_cleanup(encoder);
3875 kfree(intel_encoder);
3876 }
3877
3878 /* Simple dpms helper for encodres with just one connector, no cloning and only
3879 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3880 * state of the entire output pipe. */
3881 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3882 {
3883 if (mode == DRM_MODE_DPMS_ON) {
3884 encoder->connectors_active = true;
3885
3886 intel_crtc_update_dpms(encoder->base.crtc);
3887 } else {
3888 encoder->connectors_active = false;
3889
3890 intel_crtc_update_dpms(encoder->base.crtc);
3891 }
3892 }
3893
3894 /* Cross check the actual hw state with our own modeset state tracking (and it's
3895 * internal consistency). */
3896 static void intel_connector_check_state(struct intel_connector *connector)
3897 {
3898 if (connector->get_hw_state(connector)) {
3899 struct intel_encoder *encoder = connector->encoder;
3900 struct drm_crtc *crtc;
3901 bool encoder_enabled;
3902 enum pipe pipe;
3903
3904 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3905 connector->base.base.id,
3906 drm_get_connector_name(&connector->base));
3907
3908 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3909 "wrong connector dpms state\n");
3910 WARN(connector->base.encoder != &encoder->base,
3911 "active connector not linked to encoder\n");
3912 WARN(!encoder->connectors_active,
3913 "encoder->connectors_active not set\n");
3914
3915 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3916 WARN(!encoder_enabled, "encoder not enabled\n");
3917 if (WARN_ON(!encoder->base.crtc))
3918 return;
3919
3920 crtc = encoder->base.crtc;
3921
3922 WARN(!crtc->enabled, "crtc not enabled\n");
3923 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3924 WARN(pipe != to_intel_crtc(crtc)->pipe,
3925 "encoder active on the wrong pipe\n");
3926 }
3927 }
3928
3929 /* Even simpler default implementation, if there's really no special case to
3930 * consider. */
3931 void intel_connector_dpms(struct drm_connector *connector, int mode)
3932 {
3933 struct intel_encoder *encoder = intel_attached_encoder(connector);
3934
3935 /* All the simple cases only support two dpms states. */
3936 if (mode != DRM_MODE_DPMS_ON)
3937 mode = DRM_MODE_DPMS_OFF;
3938
3939 if (mode == connector->dpms)
3940 return;
3941
3942 connector->dpms = mode;
3943
3944 /* Only need to change hw state when actually enabled */
3945 if (encoder->base.crtc)
3946 intel_encoder_dpms(encoder, mode);
3947 else
3948 WARN_ON(encoder->connectors_active != false);
3949
3950 intel_modeset_check_state(connector->dev);
3951 }
3952
3953 /* Simple connector->get_hw_state implementation for encoders that support only
3954 * one connector and no cloning and hence the encoder state determines the state
3955 * of the connector. */
3956 bool intel_connector_get_hw_state(struct intel_connector *connector)
3957 {
3958 enum pipe pipe = 0;
3959 struct intel_encoder *encoder = connector->encoder;
3960
3961 return encoder->get_hw_state(encoder, &pipe);
3962 }
3963
3964 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3965 struct intel_crtc_config *pipe_config)
3966 {
3967 struct drm_i915_private *dev_priv = dev->dev_private;
3968 struct intel_crtc *pipe_B_crtc =
3969 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3970
3971 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3972 pipe_name(pipe), pipe_config->fdi_lanes);
3973 if (pipe_config->fdi_lanes > 4) {
3974 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3975 pipe_name(pipe), pipe_config->fdi_lanes);
3976 return false;
3977 }
3978
3979 if (IS_HASWELL(dev)) {
3980 if (pipe_config->fdi_lanes > 2) {
3981 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3982 pipe_config->fdi_lanes);
3983 return false;
3984 } else {
3985 return true;
3986 }
3987 }
3988
3989 if (INTEL_INFO(dev)->num_pipes == 2)
3990 return true;
3991
3992 /* Ivybridge 3 pipe is really complicated */
3993 switch (pipe) {
3994 case PIPE_A:
3995 return true;
3996 case PIPE_B:
3997 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
3998 pipe_config->fdi_lanes > 2) {
3999 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4000 pipe_name(pipe), pipe_config->fdi_lanes);
4001 return false;
4002 }
4003 return true;
4004 case PIPE_C:
4005 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4006 pipe_B_crtc->config.fdi_lanes <= 2) {
4007 if (pipe_config->fdi_lanes > 2) {
4008 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4009 pipe_name(pipe), pipe_config->fdi_lanes);
4010 return false;
4011 }
4012 } else {
4013 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4014 return false;
4015 }
4016 return true;
4017 default:
4018 BUG();
4019 }
4020 }
4021
4022 #define RETRY 1
4023 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4024 struct intel_crtc_config *pipe_config)
4025 {
4026 struct drm_device *dev = intel_crtc->base.dev;
4027 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4028 int lane, link_bw, fdi_dotclock;
4029 bool setup_ok, needs_recompute = false;
4030
4031 retry:
4032 /* FDI is a binary signal running at ~2.7GHz, encoding
4033 * each output octet as 10 bits. The actual frequency
4034 * is stored as a divider into a 100MHz clock, and the
4035 * mode pixel clock is stored in units of 1KHz.
4036 * Hence the bw of each lane in terms of the mode signal
4037 * is:
4038 */
4039 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4040
4041 fdi_dotclock = adjusted_mode->clock;
4042 fdi_dotclock /= pipe_config->pixel_multiplier;
4043
4044 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4045 pipe_config->pipe_bpp);
4046
4047 pipe_config->fdi_lanes = lane;
4048
4049 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4050 link_bw, &pipe_config->fdi_m_n);
4051
4052 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4053 intel_crtc->pipe, pipe_config);
4054 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4055 pipe_config->pipe_bpp -= 2*3;
4056 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4057 pipe_config->pipe_bpp);
4058 needs_recompute = true;
4059 pipe_config->bw_constrained = true;
4060
4061 goto retry;
4062 }
4063
4064 if (needs_recompute)
4065 return RETRY;
4066
4067 return setup_ok ? 0 : -EINVAL;
4068 }
4069
4070 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4071 struct intel_crtc_config *pipe_config)
4072 {
4073 pipe_config->ips_enabled = i915_enable_ips &&
4074 hsw_crtc_supports_ips(crtc) &&
4075 pipe_config->pipe_bpp == 24;
4076 }
4077
4078 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4079 struct intel_crtc_config *pipe_config)
4080 {
4081 struct drm_device *dev = crtc->base.dev;
4082 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4083
4084 if (HAS_PCH_SPLIT(dev)) {
4085 /* FDI link clock is fixed at 2.7G */
4086 if (pipe_config->requested_mode.clock * 3
4087 > IRONLAKE_FDI_FREQ * 4)
4088 return -EINVAL;
4089 }
4090
4091 /* All interlaced capable intel hw wants timings in frames. Note though
4092 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4093 * timings, so we need to be careful not to clobber these.*/
4094 if (!pipe_config->timings_set)
4095 drm_mode_set_crtcinfo(adjusted_mode, 0);
4096
4097 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4098 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4099 */
4100 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4101 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4102 return -EINVAL;
4103
4104 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4105 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4106 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4107 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4108 * for lvds. */
4109 pipe_config->pipe_bpp = 8*3;
4110 }
4111
4112 if (HAS_IPS(dev))
4113 hsw_compute_ips_config(crtc, pipe_config);
4114
4115 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4116 * clock survives for now. */
4117 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4118 pipe_config->shared_dpll = crtc->config.shared_dpll;
4119
4120 if (pipe_config->has_pch_encoder)
4121 return ironlake_fdi_compute_config(crtc, pipe_config);
4122
4123 return 0;
4124 }
4125
4126 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4127 {
4128 return 400000; /* FIXME */
4129 }
4130
4131 static int i945_get_display_clock_speed(struct drm_device *dev)
4132 {
4133 return 400000;
4134 }
4135
4136 static int i915_get_display_clock_speed(struct drm_device *dev)
4137 {
4138 return 333000;
4139 }
4140
4141 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4142 {
4143 return 200000;
4144 }
4145
4146 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4147 {
4148 u16 gcfgc = 0;
4149
4150 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4151
4152 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4153 return 133000;
4154 else {
4155 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4156 case GC_DISPLAY_CLOCK_333_MHZ:
4157 return 333000;
4158 default:
4159 case GC_DISPLAY_CLOCK_190_200_MHZ:
4160 return 190000;
4161 }
4162 }
4163 }
4164
4165 static int i865_get_display_clock_speed(struct drm_device *dev)
4166 {
4167 return 266000;
4168 }
4169
4170 static int i855_get_display_clock_speed(struct drm_device *dev)
4171 {
4172 u16 hpllcc = 0;
4173 /* Assume that the hardware is in the high speed state. This
4174 * should be the default.
4175 */
4176 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4177 case GC_CLOCK_133_200:
4178 case GC_CLOCK_100_200:
4179 return 200000;
4180 case GC_CLOCK_166_250:
4181 return 250000;
4182 case GC_CLOCK_100_133:
4183 return 133000;
4184 }
4185
4186 /* Shouldn't happen */
4187 return 0;
4188 }
4189
4190 static int i830_get_display_clock_speed(struct drm_device *dev)
4191 {
4192 return 133000;
4193 }
4194
4195 static void
4196 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4197 {
4198 while (*num > DATA_LINK_M_N_MASK ||
4199 *den > DATA_LINK_M_N_MASK) {
4200 *num >>= 1;
4201 *den >>= 1;
4202 }
4203 }
4204
4205 static void compute_m_n(unsigned int m, unsigned int n,
4206 uint32_t *ret_m, uint32_t *ret_n)
4207 {
4208 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4209 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4210 intel_reduce_m_n_ratio(ret_m, ret_n);
4211 }
4212
4213 void
4214 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4215 int pixel_clock, int link_clock,
4216 struct intel_link_m_n *m_n)
4217 {
4218 m_n->tu = 64;
4219
4220 compute_m_n(bits_per_pixel * pixel_clock,
4221 link_clock * nlanes * 8,
4222 &m_n->gmch_m, &m_n->gmch_n);
4223
4224 compute_m_n(pixel_clock, link_clock,
4225 &m_n->link_m, &m_n->link_n);
4226 }
4227
4228 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4229 {
4230 if (i915_panel_use_ssc >= 0)
4231 return i915_panel_use_ssc != 0;
4232 return dev_priv->vbt.lvds_use_ssc
4233 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4234 }
4235
4236 static int vlv_get_refclk(struct drm_crtc *crtc)
4237 {
4238 struct drm_device *dev = crtc->dev;
4239 struct drm_i915_private *dev_priv = dev->dev_private;
4240 int refclk = 27000; /* for DP & HDMI */
4241
4242 return 100000; /* only one validated so far */
4243
4244 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4245 refclk = 96000;
4246 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4247 if (intel_panel_use_ssc(dev_priv))
4248 refclk = 100000;
4249 else
4250 refclk = 96000;
4251 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4252 refclk = 100000;
4253 }
4254
4255 return refclk;
4256 }
4257
4258 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4259 {
4260 struct drm_device *dev = crtc->dev;
4261 struct drm_i915_private *dev_priv = dev->dev_private;
4262 int refclk;
4263
4264 if (IS_VALLEYVIEW(dev)) {
4265 refclk = vlv_get_refclk(crtc);
4266 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4267 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4268 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4269 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4270 refclk / 1000);
4271 } else if (!IS_GEN2(dev)) {
4272 refclk = 96000;
4273 } else {
4274 refclk = 48000;
4275 }
4276
4277 return refclk;
4278 }
4279
4280 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4281 {
4282 return (1 << dpll->n) << 16 | dpll->m2;
4283 }
4284
4285 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4286 {
4287 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4288 }
4289
4290 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4291 intel_clock_t *reduced_clock)
4292 {
4293 struct drm_device *dev = crtc->base.dev;
4294 struct drm_i915_private *dev_priv = dev->dev_private;
4295 int pipe = crtc->pipe;
4296 u32 fp, fp2 = 0;
4297
4298 if (IS_PINEVIEW(dev)) {
4299 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4300 if (reduced_clock)
4301 fp2 = pnv_dpll_compute_fp(reduced_clock);
4302 } else {
4303 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4304 if (reduced_clock)
4305 fp2 = i9xx_dpll_compute_fp(reduced_clock);
4306 }
4307
4308 I915_WRITE(FP0(pipe), fp);
4309 crtc->config.dpll_hw_state.fp0 = fp;
4310
4311 crtc->lowfreq_avail = false;
4312 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4313 reduced_clock && i915_powersave) {
4314 I915_WRITE(FP1(pipe), fp2);
4315 crtc->config.dpll_hw_state.fp1 = fp2;
4316 crtc->lowfreq_avail = true;
4317 } else {
4318 I915_WRITE(FP1(pipe), fp);
4319 crtc->config.dpll_hw_state.fp1 = fp;
4320 }
4321 }
4322
4323 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4324 {
4325 u32 reg_val;
4326
4327 /*
4328 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4329 * and set it to a reasonable value instead.
4330 */
4331 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4332 reg_val &= 0xffffff00;
4333 reg_val |= 0x00000030;
4334 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4335
4336 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4337 reg_val &= 0x8cffffff;
4338 reg_val = 0x8c000000;
4339 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4340
4341 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4342 reg_val &= 0xffffff00;
4343 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4344
4345 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4346 reg_val &= 0x00ffffff;
4347 reg_val |= 0xb0000000;
4348 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4349 }
4350
4351 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4352 struct intel_link_m_n *m_n)
4353 {
4354 struct drm_device *dev = crtc->base.dev;
4355 struct drm_i915_private *dev_priv = dev->dev_private;
4356 int pipe = crtc->pipe;
4357
4358 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4359 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4360 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4361 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4362 }
4363
4364 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4365 struct intel_link_m_n *m_n)
4366 {
4367 struct drm_device *dev = crtc->base.dev;
4368 struct drm_i915_private *dev_priv = dev->dev_private;
4369 int pipe = crtc->pipe;
4370 enum transcoder transcoder = crtc->config.cpu_transcoder;
4371
4372 if (INTEL_INFO(dev)->gen >= 5) {
4373 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4374 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4375 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4376 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4377 } else {
4378 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4379 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4380 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4381 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4382 }
4383 }
4384
4385 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4386 {
4387 if (crtc->config.has_pch_encoder)
4388 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4389 else
4390 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4391 }
4392
4393 static void vlv_update_pll(struct intel_crtc *crtc)
4394 {
4395 struct drm_device *dev = crtc->base.dev;
4396 struct drm_i915_private *dev_priv = dev->dev_private;
4397 struct intel_encoder *encoder;
4398 int pipe = crtc->pipe;
4399 u32 dpll, mdiv;
4400 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4401 bool is_hdmi;
4402 u32 coreclk, reg_val, dpll_md;
4403
4404 mutex_lock(&dev_priv->dpio_lock);
4405
4406 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4407
4408 bestn = crtc->config.dpll.n;
4409 bestm1 = crtc->config.dpll.m1;
4410 bestm2 = crtc->config.dpll.m2;
4411 bestp1 = crtc->config.dpll.p1;
4412 bestp2 = crtc->config.dpll.p2;
4413
4414 /* See eDP HDMI DPIO driver vbios notes doc */
4415
4416 /* PLL B needs special handling */
4417 if (pipe)
4418 vlv_pllb_recal_opamp(dev_priv);
4419
4420 /* Set up Tx target for periodic Rcomp update */
4421 vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4422
4423 /* Disable target IRef on PLL */
4424 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4425 reg_val &= 0x00ffffff;
4426 vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4427
4428 /* Disable fast lock */
4429 vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4430
4431 /* Set idtafcrecal before PLL is enabled */
4432 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4433 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4434 mdiv |= ((bestn << DPIO_N_SHIFT));
4435 mdiv |= (1 << DPIO_K_SHIFT);
4436
4437 /*
4438 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4439 * but we don't support that).
4440 * Note: don't use the DAC post divider as it seems unstable.
4441 */
4442 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4443 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4444
4445 mdiv |= DPIO_ENABLE_CALIBRATION;
4446 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4447
4448 /* Set HBR and RBR LPF coefficients */
4449 if (crtc->config.port_clock == 162000 ||
4450 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4451 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4452 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4453 0x005f0021);
4454 else
4455 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4456 0x00d0000f);
4457
4458 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4459 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4460 /* Use SSC source */
4461 if (!pipe)
4462 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4463 0x0df40000);
4464 else
4465 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4466 0x0df70000);
4467 } else { /* HDMI or VGA */
4468 /* Use bend source */
4469 if (!pipe)
4470 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4471 0x0df70000);
4472 else
4473 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4474 0x0df40000);
4475 }
4476
4477 coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4478 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4479 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4480 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4481 coreclk |= 0x01000000;
4482 vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4483
4484 vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4485
4486 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4487 if (encoder->pre_pll_enable)
4488 encoder->pre_pll_enable(encoder);
4489
4490 /* Enable DPIO clock input */
4491 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4492 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4493 if (pipe)
4494 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4495
4496 dpll |= DPLL_VCO_ENABLE;
4497 crtc->config.dpll_hw_state.dpll = dpll;
4498
4499 I915_WRITE(DPLL(pipe), dpll);
4500 POSTING_READ(DPLL(pipe));
4501 udelay(150);
4502
4503 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4504 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4505
4506 dpll_md = (crtc->config.pixel_multiplier - 1)
4507 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4508 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4509
4510 I915_WRITE(DPLL_MD(pipe), dpll_md);
4511 POSTING_READ(DPLL_MD(pipe));
4512
4513 if (crtc->config.has_dp_encoder)
4514 intel_dp_set_m_n(crtc);
4515
4516 mutex_unlock(&dev_priv->dpio_lock);
4517 }
4518
4519 static void i9xx_update_pll(struct intel_crtc *crtc,
4520 intel_clock_t *reduced_clock,
4521 int num_connectors)
4522 {
4523 struct drm_device *dev = crtc->base.dev;
4524 struct drm_i915_private *dev_priv = dev->dev_private;
4525 u32 dpll;
4526 bool is_sdvo;
4527 struct dpll *clock = &crtc->config.dpll;
4528
4529 i9xx_update_pll_dividers(crtc, reduced_clock);
4530
4531 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4532 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4533
4534 dpll = DPLL_VGA_MODE_DIS;
4535
4536 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4537 dpll |= DPLLB_MODE_LVDS;
4538 else
4539 dpll |= DPLLB_MODE_DAC_SERIAL;
4540
4541 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4542 dpll |= (crtc->config.pixel_multiplier - 1)
4543 << SDVO_MULTIPLIER_SHIFT_HIRES;
4544 }
4545
4546 if (is_sdvo)
4547 dpll |= DPLL_DVO_HIGH_SPEED;
4548
4549 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4550 dpll |= DPLL_DVO_HIGH_SPEED;
4551
4552 /* compute bitmask from p1 value */
4553 if (IS_PINEVIEW(dev))
4554 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4555 else {
4556 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4557 if (IS_G4X(dev) && reduced_clock)
4558 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4559 }
4560 switch (clock->p2) {
4561 case 5:
4562 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4563 break;
4564 case 7:
4565 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4566 break;
4567 case 10:
4568 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4569 break;
4570 case 14:
4571 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4572 break;
4573 }
4574 if (INTEL_INFO(dev)->gen >= 4)
4575 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4576
4577 if (crtc->config.sdvo_tv_clock)
4578 dpll |= PLL_REF_INPUT_TVCLKINBC;
4579 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4580 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4581 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4582 else
4583 dpll |= PLL_REF_INPUT_DREFCLK;
4584
4585 dpll |= DPLL_VCO_ENABLE;
4586 crtc->config.dpll_hw_state.dpll = dpll;
4587
4588 if (INTEL_INFO(dev)->gen >= 4) {
4589 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4590 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4591 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4592 }
4593
4594 if (crtc->config.has_dp_encoder)
4595 intel_dp_set_m_n(crtc);
4596 }
4597
4598 static void i8xx_update_pll(struct intel_crtc *crtc,
4599 intel_clock_t *reduced_clock,
4600 int num_connectors)
4601 {
4602 struct drm_device *dev = crtc->base.dev;
4603 struct drm_i915_private *dev_priv = dev->dev_private;
4604 u32 dpll;
4605 struct dpll *clock = &crtc->config.dpll;
4606
4607 i9xx_update_pll_dividers(crtc, reduced_clock);
4608
4609 dpll = DPLL_VGA_MODE_DIS;
4610
4611 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4612 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4613 } else {
4614 if (clock->p1 == 2)
4615 dpll |= PLL_P1_DIVIDE_BY_TWO;
4616 else
4617 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4618 if (clock->p2 == 4)
4619 dpll |= PLL_P2_DIVIDE_BY_4;
4620 }
4621
4622 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4623 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4624 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4625 else
4626 dpll |= PLL_REF_INPUT_DREFCLK;
4627
4628 dpll |= DPLL_VCO_ENABLE;
4629 crtc->config.dpll_hw_state.dpll = dpll;
4630 }
4631
4632 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4633 {
4634 struct drm_device *dev = intel_crtc->base.dev;
4635 struct drm_i915_private *dev_priv = dev->dev_private;
4636 enum pipe pipe = intel_crtc->pipe;
4637 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4638 struct drm_display_mode *adjusted_mode =
4639 &intel_crtc->config.adjusted_mode;
4640 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4641 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4642
4643 /* We need to be careful not to changed the adjusted mode, for otherwise
4644 * the hw state checker will get angry at the mismatch. */
4645 crtc_vtotal = adjusted_mode->crtc_vtotal;
4646 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4647
4648 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4649 /* the chip adds 2 halflines automatically */
4650 crtc_vtotal -= 1;
4651 crtc_vblank_end -= 1;
4652 vsyncshift = adjusted_mode->crtc_hsync_start
4653 - adjusted_mode->crtc_htotal / 2;
4654 } else {
4655 vsyncshift = 0;
4656 }
4657
4658 if (INTEL_INFO(dev)->gen > 3)
4659 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4660
4661 I915_WRITE(HTOTAL(cpu_transcoder),
4662 (adjusted_mode->crtc_hdisplay - 1) |
4663 ((adjusted_mode->crtc_htotal - 1) << 16));
4664 I915_WRITE(HBLANK(cpu_transcoder),
4665 (adjusted_mode->crtc_hblank_start - 1) |
4666 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4667 I915_WRITE(HSYNC(cpu_transcoder),
4668 (adjusted_mode->crtc_hsync_start - 1) |
4669 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4670
4671 I915_WRITE(VTOTAL(cpu_transcoder),
4672 (adjusted_mode->crtc_vdisplay - 1) |
4673 ((crtc_vtotal - 1) << 16));
4674 I915_WRITE(VBLANK(cpu_transcoder),
4675 (adjusted_mode->crtc_vblank_start - 1) |
4676 ((crtc_vblank_end - 1) << 16));
4677 I915_WRITE(VSYNC(cpu_transcoder),
4678 (adjusted_mode->crtc_vsync_start - 1) |
4679 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4680
4681 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4682 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4683 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4684 * bits. */
4685 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4686 (pipe == PIPE_B || pipe == PIPE_C))
4687 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4688
4689 /* pipesrc controls the size that is scaled from, which should
4690 * always be the user's requested size.
4691 */
4692 I915_WRITE(PIPESRC(pipe),
4693 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4694 }
4695
4696 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4697 struct intel_crtc_config *pipe_config)
4698 {
4699 struct drm_device *dev = crtc->base.dev;
4700 struct drm_i915_private *dev_priv = dev->dev_private;
4701 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4702 uint32_t tmp;
4703
4704 tmp = I915_READ(HTOTAL(cpu_transcoder));
4705 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4706 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4707 tmp = I915_READ(HBLANK(cpu_transcoder));
4708 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4709 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4710 tmp = I915_READ(HSYNC(cpu_transcoder));
4711 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4712 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4713
4714 tmp = I915_READ(VTOTAL(cpu_transcoder));
4715 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4716 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4717 tmp = I915_READ(VBLANK(cpu_transcoder));
4718 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4719 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4720 tmp = I915_READ(VSYNC(cpu_transcoder));
4721 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4722 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4723
4724 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4725 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4726 pipe_config->adjusted_mode.crtc_vtotal += 1;
4727 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4728 }
4729
4730 tmp = I915_READ(PIPESRC(crtc->pipe));
4731 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4732 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4733 }
4734
4735 static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4736 struct intel_crtc_config *pipe_config)
4737 {
4738 struct drm_crtc *crtc = &intel_crtc->base;
4739
4740 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4741 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4742 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4743 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4744
4745 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4746 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4747 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4748 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4749
4750 crtc->mode.flags = pipe_config->adjusted_mode.flags;
4751
4752 crtc->mode.clock = pipe_config->adjusted_mode.clock;
4753 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4754 }
4755
4756 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4757 {
4758 struct drm_device *dev = intel_crtc->base.dev;
4759 struct drm_i915_private *dev_priv = dev->dev_private;
4760 uint32_t pipeconf;
4761
4762 pipeconf = 0;
4763
4764 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4765 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4766 * core speed.
4767 *
4768 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4769 * pipe == 0 check?
4770 */
4771 if (intel_crtc->config.requested_mode.clock >
4772 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4773 pipeconf |= PIPECONF_DOUBLE_WIDE;
4774 }
4775
4776 /* only g4x and later have fancy bpc/dither controls */
4777 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4778 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4779 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4780 pipeconf |= PIPECONF_DITHER_EN |
4781 PIPECONF_DITHER_TYPE_SP;
4782
4783 switch (intel_crtc->config.pipe_bpp) {
4784 case 18:
4785 pipeconf |= PIPECONF_6BPC;
4786 break;
4787 case 24:
4788 pipeconf |= PIPECONF_8BPC;
4789 break;
4790 case 30:
4791 pipeconf |= PIPECONF_10BPC;
4792 break;
4793 default:
4794 /* Case prevented by intel_choose_pipe_bpp_dither. */
4795 BUG();
4796 }
4797 }
4798
4799 if (HAS_PIPE_CXSR(dev)) {
4800 if (intel_crtc->lowfreq_avail) {
4801 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4802 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4803 } else {
4804 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4805 }
4806 }
4807
4808 if (!IS_GEN2(dev) &&
4809 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4810 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4811 else
4812 pipeconf |= PIPECONF_PROGRESSIVE;
4813
4814 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4815 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4816
4817 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4818 POSTING_READ(PIPECONF(intel_crtc->pipe));
4819 }
4820
4821 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4822 int x, int y,
4823 struct drm_framebuffer *fb)
4824 {
4825 struct drm_device *dev = crtc->dev;
4826 struct drm_i915_private *dev_priv = dev->dev_private;
4827 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4828 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4829 int pipe = intel_crtc->pipe;
4830 int plane = intel_crtc->plane;
4831 int refclk, num_connectors = 0;
4832 intel_clock_t clock, reduced_clock;
4833 u32 dspcntr;
4834 bool ok, has_reduced_clock = false;
4835 bool is_lvds = false;
4836 struct intel_encoder *encoder;
4837 const intel_limit_t *limit;
4838 int ret;
4839
4840 for_each_encoder_on_crtc(dev, crtc, encoder) {
4841 switch (encoder->type) {
4842 case INTEL_OUTPUT_LVDS:
4843 is_lvds = true;
4844 break;
4845 }
4846
4847 num_connectors++;
4848 }
4849
4850 refclk = i9xx_get_refclk(crtc, num_connectors);
4851
4852 /*
4853 * Returns a set of divisors for the desired target clock with the given
4854 * refclk, or FALSE. The returned values represent the clock equation:
4855 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4856 */
4857 limit = intel_limit(crtc, refclk);
4858 ok = dev_priv->display.find_dpll(limit, crtc,
4859 intel_crtc->config.port_clock,
4860 refclk, NULL, &clock);
4861 if (!ok && !intel_crtc->config.clock_set) {
4862 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4863 return -EINVAL;
4864 }
4865
4866 /* Ensure that the cursor is valid for the new mode before changing... */
4867 intel_crtc_update_cursor(crtc, true);
4868
4869 if (is_lvds && dev_priv->lvds_downclock_avail) {
4870 /*
4871 * Ensure we match the reduced clock's P to the target clock.
4872 * If the clocks don't match, we can't switch the display clock
4873 * by using the FP0/FP1. In such case we will disable the LVDS
4874 * downclock feature.
4875 */
4876 has_reduced_clock =
4877 dev_priv->display.find_dpll(limit, crtc,
4878 dev_priv->lvds_downclock,
4879 refclk, &clock,
4880 &reduced_clock);
4881 }
4882 /* Compat-code for transition, will disappear. */
4883 if (!intel_crtc->config.clock_set) {
4884 intel_crtc->config.dpll.n = clock.n;
4885 intel_crtc->config.dpll.m1 = clock.m1;
4886 intel_crtc->config.dpll.m2 = clock.m2;
4887 intel_crtc->config.dpll.p1 = clock.p1;
4888 intel_crtc->config.dpll.p2 = clock.p2;
4889 }
4890
4891 if (IS_GEN2(dev))
4892 i8xx_update_pll(intel_crtc,
4893 has_reduced_clock ? &reduced_clock : NULL,
4894 num_connectors);
4895 else if (IS_VALLEYVIEW(dev))
4896 vlv_update_pll(intel_crtc);
4897 else
4898 i9xx_update_pll(intel_crtc,
4899 has_reduced_clock ? &reduced_clock : NULL,
4900 num_connectors);
4901
4902 /* Set up the display plane register */
4903 dspcntr = DISPPLANE_GAMMA_ENABLE;
4904
4905 if (!IS_VALLEYVIEW(dev)) {
4906 if (pipe == 0)
4907 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4908 else
4909 dspcntr |= DISPPLANE_SEL_PIPE_B;
4910 }
4911
4912 intel_set_pipe_timings(intel_crtc);
4913
4914 /* pipesrc and dspsize control the size that is scaled from,
4915 * which should always be the user's requested size.
4916 */
4917 I915_WRITE(DSPSIZE(plane),
4918 ((mode->vdisplay - 1) << 16) |
4919 (mode->hdisplay - 1));
4920 I915_WRITE(DSPPOS(plane), 0);
4921
4922 i9xx_set_pipeconf(intel_crtc);
4923
4924 I915_WRITE(DSPCNTR(plane), dspcntr);
4925 POSTING_READ(DSPCNTR(plane));
4926
4927 ret = intel_pipe_set_base(crtc, x, y, fb);
4928
4929 intel_update_watermarks(dev);
4930
4931 return ret;
4932 }
4933
4934 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4935 struct intel_crtc_config *pipe_config)
4936 {
4937 struct drm_device *dev = crtc->base.dev;
4938 struct drm_i915_private *dev_priv = dev->dev_private;
4939 uint32_t tmp;
4940
4941 tmp = I915_READ(PFIT_CONTROL);
4942
4943 if (INTEL_INFO(dev)->gen < 4) {
4944 if (crtc->pipe != PIPE_B)
4945 return;
4946
4947 /* gen2/3 store dither state in pfit control, needs to match */
4948 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
4949 } else {
4950 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4951 return;
4952 }
4953
4954 if (!(tmp & PFIT_ENABLE))
4955 return;
4956
4957 pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
4958 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4959 if (INTEL_INFO(dev)->gen < 5)
4960 pipe_config->gmch_pfit.lvds_border_bits =
4961 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4962 }
4963
4964 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4965 struct intel_crtc_config *pipe_config)
4966 {
4967 struct drm_device *dev = crtc->base.dev;
4968 struct drm_i915_private *dev_priv = dev->dev_private;
4969 uint32_t tmp;
4970
4971 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
4972 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
4973
4974 tmp = I915_READ(PIPECONF(crtc->pipe));
4975 if (!(tmp & PIPECONF_ENABLE))
4976 return false;
4977
4978 intel_get_pipe_timings(crtc, pipe_config);
4979
4980 i9xx_get_pfit_config(crtc, pipe_config);
4981
4982 if (INTEL_INFO(dev)->gen >= 4) {
4983 tmp = I915_READ(DPLL_MD(crtc->pipe));
4984 pipe_config->pixel_multiplier =
4985 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
4986 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
4987 pipe_config->dpll_hw_state.dpll_md = tmp;
4988 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4989 tmp = I915_READ(DPLL(crtc->pipe));
4990 pipe_config->pixel_multiplier =
4991 ((tmp & SDVO_MULTIPLIER_MASK)
4992 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
4993 } else {
4994 /* Note that on i915G/GM the pixel multiplier is in the sdvo
4995 * port and will be fixed up in the encoder->get_config
4996 * function. */
4997 pipe_config->pixel_multiplier = 1;
4998 }
4999 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5000 if (!IS_VALLEYVIEW(dev)) {
5001 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5002 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5003 } else {
5004 /* Mask out read-only status bits. */
5005 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5006 DPLL_PORTC_READY_MASK |
5007 DPLL_PORTB_READY_MASK);
5008 }
5009
5010 return true;
5011 }
5012
5013 static void ironlake_init_pch_refclk(struct drm_device *dev)
5014 {
5015 struct drm_i915_private *dev_priv = dev->dev_private;
5016 struct drm_mode_config *mode_config = &dev->mode_config;
5017 struct intel_encoder *encoder;
5018 u32 val, final;
5019 bool has_lvds = false;
5020 bool has_cpu_edp = false;
5021 bool has_panel = false;
5022 bool has_ck505 = false;
5023 bool can_ssc = false;
5024
5025 /* We need to take the global config into account */
5026 list_for_each_entry(encoder, &mode_config->encoder_list,
5027 base.head) {
5028 switch (encoder->type) {
5029 case INTEL_OUTPUT_LVDS:
5030 has_panel = true;
5031 has_lvds = true;
5032 break;
5033 case INTEL_OUTPUT_EDP:
5034 has_panel = true;
5035 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5036 has_cpu_edp = true;
5037 break;
5038 }
5039 }
5040
5041 if (HAS_PCH_IBX(dev)) {
5042 has_ck505 = dev_priv->vbt.display_clock_mode;
5043 can_ssc = has_ck505;
5044 } else {
5045 has_ck505 = false;
5046 can_ssc = true;
5047 }
5048
5049 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5050 has_panel, has_lvds, has_ck505);
5051
5052 /* Ironlake: try to setup display ref clock before DPLL
5053 * enabling. This is only under driver's control after
5054 * PCH B stepping, previous chipset stepping should be
5055 * ignoring this setting.
5056 */
5057 val = I915_READ(PCH_DREF_CONTROL);
5058
5059 /* As we must carefully and slowly disable/enable each source in turn,
5060 * compute the final state we want first and check if we need to
5061 * make any changes at all.
5062 */
5063 final = val;
5064 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5065 if (has_ck505)
5066 final |= DREF_NONSPREAD_CK505_ENABLE;
5067 else
5068 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5069
5070 final &= ~DREF_SSC_SOURCE_MASK;
5071 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5072 final &= ~DREF_SSC1_ENABLE;
5073
5074 if (has_panel) {
5075 final |= DREF_SSC_SOURCE_ENABLE;
5076
5077 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5078 final |= DREF_SSC1_ENABLE;
5079
5080 if (has_cpu_edp) {
5081 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5082 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5083 else
5084 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5085 } else
5086 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5087 } else {
5088 final |= DREF_SSC_SOURCE_DISABLE;
5089 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5090 }
5091
5092 if (final == val)
5093 return;
5094
5095 /* Always enable nonspread source */
5096 val &= ~DREF_NONSPREAD_SOURCE_MASK;
5097
5098 if (has_ck505)
5099 val |= DREF_NONSPREAD_CK505_ENABLE;
5100 else
5101 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5102
5103 if (has_panel) {
5104 val &= ~DREF_SSC_SOURCE_MASK;
5105 val |= DREF_SSC_SOURCE_ENABLE;
5106
5107 /* SSC must be turned on before enabling the CPU output */
5108 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5109 DRM_DEBUG_KMS("Using SSC on panel\n");
5110 val |= DREF_SSC1_ENABLE;
5111 } else
5112 val &= ~DREF_SSC1_ENABLE;
5113
5114 /* Get SSC going before enabling the outputs */
5115 I915_WRITE(PCH_DREF_CONTROL, val);
5116 POSTING_READ(PCH_DREF_CONTROL);
5117 udelay(200);
5118
5119 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5120
5121 /* Enable CPU source on CPU attached eDP */
5122 if (has_cpu_edp) {
5123 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5124 DRM_DEBUG_KMS("Using SSC on eDP\n");
5125 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5126 }
5127 else
5128 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5129 } else
5130 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5131
5132 I915_WRITE(PCH_DREF_CONTROL, val);
5133 POSTING_READ(PCH_DREF_CONTROL);
5134 udelay(200);
5135 } else {
5136 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5137
5138 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5139
5140 /* Turn off CPU output */
5141 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5142
5143 I915_WRITE(PCH_DREF_CONTROL, val);
5144 POSTING_READ(PCH_DREF_CONTROL);
5145 udelay(200);
5146
5147 /* Turn off the SSC source */
5148 val &= ~DREF_SSC_SOURCE_MASK;
5149 val |= DREF_SSC_SOURCE_DISABLE;
5150
5151 /* Turn off SSC1 */
5152 val &= ~DREF_SSC1_ENABLE;
5153
5154 I915_WRITE(PCH_DREF_CONTROL, val);
5155 POSTING_READ(PCH_DREF_CONTROL);
5156 udelay(200);
5157 }
5158
5159 BUG_ON(val != final);
5160 }
5161
5162 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5163 static void lpt_init_pch_refclk(struct drm_device *dev)
5164 {
5165 struct drm_i915_private *dev_priv = dev->dev_private;
5166 struct drm_mode_config *mode_config = &dev->mode_config;
5167 struct intel_encoder *encoder;
5168 bool has_vga = false;
5169 bool is_sdv = false;
5170 u32 tmp;
5171
5172 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5173 switch (encoder->type) {
5174 case INTEL_OUTPUT_ANALOG:
5175 has_vga = true;
5176 break;
5177 }
5178 }
5179
5180 if (!has_vga)
5181 return;
5182
5183 mutex_lock(&dev_priv->dpio_lock);
5184
5185 /* XXX: Rip out SDV support once Haswell ships for real. */
5186 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5187 is_sdv = true;
5188
5189 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5190 tmp &= ~SBI_SSCCTL_DISABLE;
5191 tmp |= SBI_SSCCTL_PATHALT;
5192 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5193
5194 udelay(24);
5195
5196 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5197 tmp &= ~SBI_SSCCTL_PATHALT;
5198 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5199
5200 if (!is_sdv) {
5201 tmp = I915_READ(SOUTH_CHICKEN2);
5202 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5203 I915_WRITE(SOUTH_CHICKEN2, tmp);
5204
5205 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5206 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5207 DRM_ERROR("FDI mPHY reset assert timeout\n");
5208
5209 tmp = I915_READ(SOUTH_CHICKEN2);
5210 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5211 I915_WRITE(SOUTH_CHICKEN2, tmp);
5212
5213 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5214 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5215 100))
5216 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5217 }
5218
5219 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5220 tmp &= ~(0xFF << 24);
5221 tmp |= (0x12 << 24);
5222 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5223
5224 if (is_sdv) {
5225 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5226 tmp |= 0x7FFF;
5227 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5228 }
5229
5230 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5231 tmp |= (1 << 11);
5232 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5233
5234 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5235 tmp |= (1 << 11);
5236 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5237
5238 if (is_sdv) {
5239 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5240 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5241 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5242
5243 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5244 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5245 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5246
5247 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5248 tmp |= (0x3F << 8);
5249 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5250
5251 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5252 tmp |= (0x3F << 8);
5253 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5254 }
5255
5256 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5257 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5258 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5259
5260 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5261 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5262 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5263
5264 if (!is_sdv) {
5265 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5266 tmp &= ~(7 << 13);
5267 tmp |= (5 << 13);
5268 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5269
5270 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5271 tmp &= ~(7 << 13);
5272 tmp |= (5 << 13);
5273 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5274 }
5275
5276 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5277 tmp &= ~0xFF;
5278 tmp |= 0x1C;
5279 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5280
5281 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5282 tmp &= ~0xFF;
5283 tmp |= 0x1C;
5284 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5285
5286 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5287 tmp &= ~(0xFF << 16);
5288 tmp |= (0x1C << 16);
5289 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5290
5291 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5292 tmp &= ~(0xFF << 16);
5293 tmp |= (0x1C << 16);
5294 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5295
5296 if (!is_sdv) {
5297 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5298 tmp |= (1 << 27);
5299 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5300
5301 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5302 tmp |= (1 << 27);
5303 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5304
5305 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5306 tmp &= ~(0xF << 28);
5307 tmp |= (4 << 28);
5308 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5309
5310 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5311 tmp &= ~(0xF << 28);
5312 tmp |= (4 << 28);
5313 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5314 }
5315
5316 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5317 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5318 tmp |= SBI_DBUFF0_ENABLE;
5319 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5320
5321 mutex_unlock(&dev_priv->dpio_lock);
5322 }
5323
5324 /*
5325 * Initialize reference clocks when the driver loads
5326 */
5327 void intel_init_pch_refclk(struct drm_device *dev)
5328 {
5329 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5330 ironlake_init_pch_refclk(dev);
5331 else if (HAS_PCH_LPT(dev))
5332 lpt_init_pch_refclk(dev);
5333 }
5334
5335 static int ironlake_get_refclk(struct drm_crtc *crtc)
5336 {
5337 struct drm_device *dev = crtc->dev;
5338 struct drm_i915_private *dev_priv = dev->dev_private;
5339 struct intel_encoder *encoder;
5340 int num_connectors = 0;
5341 bool is_lvds = false;
5342
5343 for_each_encoder_on_crtc(dev, crtc, encoder) {
5344 switch (encoder->type) {
5345 case INTEL_OUTPUT_LVDS:
5346 is_lvds = true;
5347 break;
5348 }
5349 num_connectors++;
5350 }
5351
5352 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5353 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5354 dev_priv->vbt.lvds_ssc_freq);
5355 return dev_priv->vbt.lvds_ssc_freq * 1000;
5356 }
5357
5358 return 120000;
5359 }
5360
5361 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5362 {
5363 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5364 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5365 int pipe = intel_crtc->pipe;
5366 uint32_t val;
5367
5368 val = 0;
5369
5370 switch (intel_crtc->config.pipe_bpp) {
5371 case 18:
5372 val |= PIPECONF_6BPC;
5373 break;
5374 case 24:
5375 val |= PIPECONF_8BPC;
5376 break;
5377 case 30:
5378 val |= PIPECONF_10BPC;
5379 break;
5380 case 36:
5381 val |= PIPECONF_12BPC;
5382 break;
5383 default:
5384 /* Case prevented by intel_choose_pipe_bpp_dither. */
5385 BUG();
5386 }
5387
5388 if (intel_crtc->config.dither)
5389 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5390
5391 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5392 val |= PIPECONF_INTERLACED_ILK;
5393 else
5394 val |= PIPECONF_PROGRESSIVE;
5395
5396 if (intel_crtc->config.limited_color_range)
5397 val |= PIPECONF_COLOR_RANGE_SELECT;
5398
5399 I915_WRITE(PIPECONF(pipe), val);
5400 POSTING_READ(PIPECONF(pipe));
5401 }
5402
5403 /*
5404 * Set up the pipe CSC unit.
5405 *
5406 * Currently only full range RGB to limited range RGB conversion
5407 * is supported, but eventually this should handle various
5408 * RGB<->YCbCr scenarios as well.
5409 */
5410 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5411 {
5412 struct drm_device *dev = crtc->dev;
5413 struct drm_i915_private *dev_priv = dev->dev_private;
5414 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5415 int pipe = intel_crtc->pipe;
5416 uint16_t coeff = 0x7800; /* 1.0 */
5417
5418 /*
5419 * TODO: Check what kind of values actually come out of the pipe
5420 * with these coeff/postoff values and adjust to get the best
5421 * accuracy. Perhaps we even need to take the bpc value into
5422 * consideration.
5423 */
5424
5425 if (intel_crtc->config.limited_color_range)
5426 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5427
5428 /*
5429 * GY/GU and RY/RU should be the other way around according
5430 * to BSpec, but reality doesn't agree. Just set them up in
5431 * a way that results in the correct picture.
5432 */
5433 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5434 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5435
5436 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5437 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5438
5439 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5440 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5441
5442 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5443 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5444 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5445
5446 if (INTEL_INFO(dev)->gen > 6) {
5447 uint16_t postoff = 0;
5448
5449 if (intel_crtc->config.limited_color_range)
5450 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5451
5452 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5453 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5454 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5455
5456 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5457 } else {
5458 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5459
5460 if (intel_crtc->config.limited_color_range)
5461 mode |= CSC_BLACK_SCREEN_OFFSET;
5462
5463 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5464 }
5465 }
5466
5467 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5468 {
5469 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5470 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5471 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5472 uint32_t val;
5473
5474 val = 0;
5475
5476 if (intel_crtc->config.dither)
5477 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5478
5479 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5480 val |= PIPECONF_INTERLACED_ILK;
5481 else
5482 val |= PIPECONF_PROGRESSIVE;
5483
5484 I915_WRITE(PIPECONF(cpu_transcoder), val);
5485 POSTING_READ(PIPECONF(cpu_transcoder));
5486
5487 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5488 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
5489 }
5490
5491 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5492 intel_clock_t *clock,
5493 bool *has_reduced_clock,
5494 intel_clock_t *reduced_clock)
5495 {
5496 struct drm_device *dev = crtc->dev;
5497 struct drm_i915_private *dev_priv = dev->dev_private;
5498 struct intel_encoder *intel_encoder;
5499 int refclk;
5500 const intel_limit_t *limit;
5501 bool ret, is_lvds = false;
5502
5503 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5504 switch (intel_encoder->type) {
5505 case INTEL_OUTPUT_LVDS:
5506 is_lvds = true;
5507 break;
5508 }
5509 }
5510
5511 refclk = ironlake_get_refclk(crtc);
5512
5513 /*
5514 * Returns a set of divisors for the desired target clock with the given
5515 * refclk, or FALSE. The returned values represent the clock equation:
5516 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5517 */
5518 limit = intel_limit(crtc, refclk);
5519 ret = dev_priv->display.find_dpll(limit, crtc,
5520 to_intel_crtc(crtc)->config.port_clock,
5521 refclk, NULL, clock);
5522 if (!ret)
5523 return false;
5524
5525 if (is_lvds && dev_priv->lvds_downclock_avail) {
5526 /*
5527 * Ensure we match the reduced clock's P to the target clock.
5528 * If the clocks don't match, we can't switch the display clock
5529 * by using the FP0/FP1. In such case we will disable the LVDS
5530 * downclock feature.
5531 */
5532 *has_reduced_clock =
5533 dev_priv->display.find_dpll(limit, crtc,
5534 dev_priv->lvds_downclock,
5535 refclk, clock,
5536 reduced_clock);
5537 }
5538
5539 return true;
5540 }
5541
5542 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5543 {
5544 struct drm_i915_private *dev_priv = dev->dev_private;
5545 uint32_t temp;
5546
5547 temp = I915_READ(SOUTH_CHICKEN1);
5548 if (temp & FDI_BC_BIFURCATION_SELECT)
5549 return;
5550
5551 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5552 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5553
5554 temp |= FDI_BC_BIFURCATION_SELECT;
5555 DRM_DEBUG_KMS("enabling fdi C rx\n");
5556 I915_WRITE(SOUTH_CHICKEN1, temp);
5557 POSTING_READ(SOUTH_CHICKEN1);
5558 }
5559
5560 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5561 {
5562 struct drm_device *dev = intel_crtc->base.dev;
5563 struct drm_i915_private *dev_priv = dev->dev_private;
5564
5565 switch (intel_crtc->pipe) {
5566 case PIPE_A:
5567 break;
5568 case PIPE_B:
5569 if (intel_crtc->config.fdi_lanes > 2)
5570 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5571 else
5572 cpt_enable_fdi_bc_bifurcation(dev);
5573
5574 break;
5575 case PIPE_C:
5576 cpt_enable_fdi_bc_bifurcation(dev);
5577
5578 break;
5579 default:
5580 BUG();
5581 }
5582 }
5583
5584 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5585 {
5586 /*
5587 * Account for spread spectrum to avoid
5588 * oversubscribing the link. Max center spread
5589 * is 2.5%; use 5% for safety's sake.
5590 */
5591 u32 bps = target_clock * bpp * 21 / 20;
5592 return bps / (link_bw * 8) + 1;
5593 }
5594
5595 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5596 {
5597 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5598 }
5599
5600 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5601 u32 *fp,
5602 intel_clock_t *reduced_clock, u32 *fp2)
5603 {
5604 struct drm_crtc *crtc = &intel_crtc->base;
5605 struct drm_device *dev = crtc->dev;
5606 struct drm_i915_private *dev_priv = dev->dev_private;
5607 struct intel_encoder *intel_encoder;
5608 uint32_t dpll;
5609 int factor, num_connectors = 0;
5610 bool is_lvds = false, is_sdvo = false;
5611
5612 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5613 switch (intel_encoder->type) {
5614 case INTEL_OUTPUT_LVDS:
5615 is_lvds = true;
5616 break;
5617 case INTEL_OUTPUT_SDVO:
5618 case INTEL_OUTPUT_HDMI:
5619 is_sdvo = true;
5620 break;
5621 }
5622
5623 num_connectors++;
5624 }
5625
5626 /* Enable autotuning of the PLL clock (if permissible) */
5627 factor = 21;
5628 if (is_lvds) {
5629 if ((intel_panel_use_ssc(dev_priv) &&
5630 dev_priv->vbt.lvds_ssc_freq == 100) ||
5631 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5632 factor = 25;
5633 } else if (intel_crtc->config.sdvo_tv_clock)
5634 factor = 20;
5635
5636 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5637 *fp |= FP_CB_TUNE;
5638
5639 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5640 *fp2 |= FP_CB_TUNE;
5641
5642 dpll = 0;
5643
5644 if (is_lvds)
5645 dpll |= DPLLB_MODE_LVDS;
5646 else
5647 dpll |= DPLLB_MODE_DAC_SERIAL;
5648
5649 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5650 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5651
5652 if (is_sdvo)
5653 dpll |= DPLL_DVO_HIGH_SPEED;
5654 if (intel_crtc->config.has_dp_encoder)
5655 dpll |= DPLL_DVO_HIGH_SPEED;
5656
5657 /* compute bitmask from p1 value */
5658 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5659 /* also FPA1 */
5660 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5661
5662 switch (intel_crtc->config.dpll.p2) {
5663 case 5:
5664 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5665 break;
5666 case 7:
5667 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5668 break;
5669 case 10:
5670 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5671 break;
5672 case 14:
5673 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5674 break;
5675 }
5676
5677 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5678 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5679 else
5680 dpll |= PLL_REF_INPUT_DREFCLK;
5681
5682 return dpll | DPLL_VCO_ENABLE;
5683 }
5684
5685 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5686 int x, int y,
5687 struct drm_framebuffer *fb)
5688 {
5689 struct drm_device *dev = crtc->dev;
5690 struct drm_i915_private *dev_priv = dev->dev_private;
5691 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5692 int pipe = intel_crtc->pipe;
5693 int plane = intel_crtc->plane;
5694 int num_connectors = 0;
5695 intel_clock_t clock, reduced_clock;
5696 u32 dpll = 0, fp = 0, fp2 = 0;
5697 bool ok, has_reduced_clock = false;
5698 bool is_lvds = false;
5699 struct intel_encoder *encoder;
5700 struct intel_shared_dpll *pll;
5701 int ret;
5702
5703 for_each_encoder_on_crtc(dev, crtc, encoder) {
5704 switch (encoder->type) {
5705 case INTEL_OUTPUT_LVDS:
5706 is_lvds = true;
5707 break;
5708 }
5709
5710 num_connectors++;
5711 }
5712
5713 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5714 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5715
5716 ok = ironlake_compute_clocks(crtc, &clock,
5717 &has_reduced_clock, &reduced_clock);
5718 if (!ok && !intel_crtc->config.clock_set) {
5719 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5720 return -EINVAL;
5721 }
5722 /* Compat-code for transition, will disappear. */
5723 if (!intel_crtc->config.clock_set) {
5724 intel_crtc->config.dpll.n = clock.n;
5725 intel_crtc->config.dpll.m1 = clock.m1;
5726 intel_crtc->config.dpll.m2 = clock.m2;
5727 intel_crtc->config.dpll.p1 = clock.p1;
5728 intel_crtc->config.dpll.p2 = clock.p2;
5729 }
5730
5731 /* Ensure that the cursor is valid for the new mode before changing... */
5732 intel_crtc_update_cursor(crtc, true);
5733
5734 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5735 if (intel_crtc->config.has_pch_encoder) {
5736 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5737 if (has_reduced_clock)
5738 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5739
5740 dpll = ironlake_compute_dpll(intel_crtc,
5741 &fp, &reduced_clock,
5742 has_reduced_clock ? &fp2 : NULL);
5743
5744 intel_crtc->config.dpll_hw_state.dpll = dpll;
5745 intel_crtc->config.dpll_hw_state.fp0 = fp;
5746 if (has_reduced_clock)
5747 intel_crtc->config.dpll_hw_state.fp1 = fp2;
5748 else
5749 intel_crtc->config.dpll_hw_state.fp1 = fp;
5750
5751 pll = intel_get_shared_dpll(intel_crtc);
5752 if (pll == NULL) {
5753 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5754 pipe_name(pipe));
5755 return -EINVAL;
5756 }
5757 } else
5758 intel_put_shared_dpll(intel_crtc);
5759
5760 if (intel_crtc->config.has_dp_encoder)
5761 intel_dp_set_m_n(intel_crtc);
5762
5763 if (is_lvds && has_reduced_clock && i915_powersave)
5764 intel_crtc->lowfreq_avail = true;
5765 else
5766 intel_crtc->lowfreq_avail = false;
5767
5768 if (intel_crtc->config.has_pch_encoder) {
5769 pll = intel_crtc_to_shared_dpll(intel_crtc);
5770
5771 }
5772
5773 intel_set_pipe_timings(intel_crtc);
5774
5775 if (intel_crtc->config.has_pch_encoder) {
5776 intel_cpu_transcoder_set_m_n(intel_crtc,
5777 &intel_crtc->config.fdi_m_n);
5778 }
5779
5780 if (IS_IVYBRIDGE(dev))
5781 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5782
5783 ironlake_set_pipeconf(crtc);
5784
5785 /* Set up the display plane register */
5786 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5787 POSTING_READ(DSPCNTR(plane));
5788
5789 ret = intel_pipe_set_base(crtc, x, y, fb);
5790
5791 intel_update_watermarks(dev);
5792
5793 return ret;
5794 }
5795
5796 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5797 struct intel_crtc_config *pipe_config)
5798 {
5799 struct drm_device *dev = crtc->base.dev;
5800 struct drm_i915_private *dev_priv = dev->dev_private;
5801 enum transcoder transcoder = pipe_config->cpu_transcoder;
5802
5803 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5804 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5805 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5806 & ~TU_SIZE_MASK;
5807 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5808 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5809 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5810 }
5811
5812 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5813 struct intel_crtc_config *pipe_config)
5814 {
5815 struct drm_device *dev = crtc->base.dev;
5816 struct drm_i915_private *dev_priv = dev->dev_private;
5817 uint32_t tmp;
5818
5819 tmp = I915_READ(PF_CTL(crtc->pipe));
5820
5821 if (tmp & PF_ENABLE) {
5822 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5823 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5824
5825 /* We currently do not free assignements of panel fitters on
5826 * ivb/hsw (since we don't use the higher upscaling modes which
5827 * differentiates them) so just WARN about this case for now. */
5828 if (IS_GEN7(dev)) {
5829 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5830 PF_PIPE_SEL_IVB(crtc->pipe));
5831 }
5832 }
5833 }
5834
5835 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5836 struct intel_crtc_config *pipe_config)
5837 {
5838 struct drm_device *dev = crtc->base.dev;
5839 struct drm_i915_private *dev_priv = dev->dev_private;
5840 uint32_t tmp;
5841
5842 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5843 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5844
5845 tmp = I915_READ(PIPECONF(crtc->pipe));
5846 if (!(tmp & PIPECONF_ENABLE))
5847 return false;
5848
5849 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5850 struct intel_shared_dpll *pll;
5851
5852 pipe_config->has_pch_encoder = true;
5853
5854 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5855 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5856 FDI_DP_PORT_WIDTH_SHIFT) + 1;
5857
5858 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5859
5860 if (HAS_PCH_IBX(dev_priv->dev)) {
5861 pipe_config->shared_dpll =
5862 (enum intel_dpll_id) crtc->pipe;
5863 } else {
5864 tmp = I915_READ(PCH_DPLL_SEL);
5865 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5866 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5867 else
5868 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5869 }
5870
5871 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5872
5873 WARN_ON(!pll->get_hw_state(dev_priv, pll,
5874 &pipe_config->dpll_hw_state));
5875
5876 tmp = pipe_config->dpll_hw_state.dpll;
5877 pipe_config->pixel_multiplier =
5878 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
5879 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
5880 } else {
5881 pipe_config->pixel_multiplier = 1;
5882 }
5883
5884 intel_get_pipe_timings(crtc, pipe_config);
5885
5886 ironlake_get_pfit_config(crtc, pipe_config);
5887
5888 return true;
5889 }
5890
5891 static void haswell_modeset_global_resources(struct drm_device *dev)
5892 {
5893 bool enable = false;
5894 struct intel_crtc *crtc;
5895
5896 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5897 if (!crtc->base.enabled)
5898 continue;
5899
5900 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5901 crtc->config.cpu_transcoder != TRANSCODER_EDP)
5902 enable = true;
5903 }
5904
5905 intel_set_power_well(dev, enable);
5906 }
5907
5908 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5909 int x, int y,
5910 struct drm_framebuffer *fb)
5911 {
5912 struct drm_device *dev = crtc->dev;
5913 struct drm_i915_private *dev_priv = dev->dev_private;
5914 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5915 int plane = intel_crtc->plane;
5916 int ret;
5917
5918 if (!intel_ddi_pll_mode_set(crtc))
5919 return -EINVAL;
5920
5921 /* Ensure that the cursor is valid for the new mode before changing... */
5922 intel_crtc_update_cursor(crtc, true);
5923
5924 if (intel_crtc->config.has_dp_encoder)
5925 intel_dp_set_m_n(intel_crtc);
5926
5927 intel_crtc->lowfreq_avail = false;
5928
5929 intel_set_pipe_timings(intel_crtc);
5930
5931 if (intel_crtc->config.has_pch_encoder) {
5932 intel_cpu_transcoder_set_m_n(intel_crtc,
5933 &intel_crtc->config.fdi_m_n);
5934 }
5935
5936 haswell_set_pipeconf(crtc);
5937
5938 intel_set_pipe_csc(crtc);
5939
5940 /* Set up the display plane register */
5941 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
5942 POSTING_READ(DSPCNTR(plane));
5943
5944 ret = intel_pipe_set_base(crtc, x, y, fb);
5945
5946 intel_update_watermarks(dev);
5947
5948 return ret;
5949 }
5950
5951 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5952 struct intel_crtc_config *pipe_config)
5953 {
5954 struct drm_device *dev = crtc->base.dev;
5955 struct drm_i915_private *dev_priv = dev->dev_private;
5956 enum intel_display_power_domain pfit_domain;
5957 uint32_t tmp;
5958
5959 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5960 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5961
5962 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5963 if (tmp & TRANS_DDI_FUNC_ENABLE) {
5964 enum pipe trans_edp_pipe;
5965 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
5966 default:
5967 WARN(1, "unknown pipe linked to edp transcoder\n");
5968 case TRANS_DDI_EDP_INPUT_A_ONOFF:
5969 case TRANS_DDI_EDP_INPUT_A_ON:
5970 trans_edp_pipe = PIPE_A;
5971 break;
5972 case TRANS_DDI_EDP_INPUT_B_ONOFF:
5973 trans_edp_pipe = PIPE_B;
5974 break;
5975 case TRANS_DDI_EDP_INPUT_C_ONOFF:
5976 trans_edp_pipe = PIPE_C;
5977 break;
5978 }
5979
5980 if (trans_edp_pipe == crtc->pipe)
5981 pipe_config->cpu_transcoder = TRANSCODER_EDP;
5982 }
5983
5984 if (!intel_display_power_enabled(dev,
5985 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
5986 return false;
5987
5988 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
5989 if (!(tmp & PIPECONF_ENABLE))
5990 return false;
5991
5992 /*
5993 * Haswell has only FDI/PCH transcoder A. It is which is connected to
5994 * DDI E. So just check whether this pipe is wired to DDI E and whether
5995 * the PCH transcoder is on.
5996 */
5997 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
5998 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
5999 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6000 pipe_config->has_pch_encoder = true;
6001
6002 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6003 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6004 FDI_DP_PORT_WIDTH_SHIFT) + 1;
6005
6006 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6007 }
6008
6009 intel_get_pipe_timings(crtc, pipe_config);
6010
6011 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6012 if (intel_display_power_enabled(dev, pfit_domain))
6013 ironlake_get_pfit_config(crtc, pipe_config);
6014
6015 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6016 (I915_READ(IPS_CTL) & IPS_ENABLE);
6017
6018 pipe_config->pixel_multiplier = 1;
6019
6020 return true;
6021 }
6022
6023 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6024 int x, int y,
6025 struct drm_framebuffer *fb)
6026 {
6027 struct drm_device *dev = crtc->dev;
6028 struct drm_i915_private *dev_priv = dev->dev_private;
6029 struct drm_encoder_helper_funcs *encoder_funcs;
6030 struct intel_encoder *encoder;
6031 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6032 struct drm_display_mode *adjusted_mode =
6033 &intel_crtc->config.adjusted_mode;
6034 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6035 int pipe = intel_crtc->pipe;
6036 int ret;
6037
6038 drm_vblank_pre_modeset(dev, pipe);
6039
6040 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6041
6042 drm_vblank_post_modeset(dev, pipe);
6043
6044 if (ret != 0)
6045 return ret;
6046
6047 for_each_encoder_on_crtc(dev, crtc, encoder) {
6048 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6049 encoder->base.base.id,
6050 drm_get_encoder_name(&encoder->base),
6051 mode->base.id, mode->name);
6052 if (encoder->mode_set) {
6053 encoder->mode_set(encoder);
6054 } else {
6055 encoder_funcs = encoder->base.helper_private;
6056 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6057 }
6058 }
6059
6060 return 0;
6061 }
6062
6063 static bool intel_eld_uptodate(struct drm_connector *connector,
6064 int reg_eldv, uint32_t bits_eldv,
6065 int reg_elda, uint32_t bits_elda,
6066 int reg_edid)
6067 {
6068 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6069 uint8_t *eld = connector->eld;
6070 uint32_t i;
6071
6072 i = I915_READ(reg_eldv);
6073 i &= bits_eldv;
6074
6075 if (!eld[0])
6076 return !i;
6077
6078 if (!i)
6079 return false;
6080
6081 i = I915_READ(reg_elda);
6082 i &= ~bits_elda;
6083 I915_WRITE(reg_elda, i);
6084
6085 for (i = 0; i < eld[2]; i++)
6086 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6087 return false;
6088
6089 return true;
6090 }
6091
6092 static void g4x_write_eld(struct drm_connector *connector,
6093 struct drm_crtc *crtc)
6094 {
6095 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6096 uint8_t *eld = connector->eld;
6097 uint32_t eldv;
6098 uint32_t len;
6099 uint32_t i;
6100
6101 i = I915_READ(G4X_AUD_VID_DID);
6102
6103 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6104 eldv = G4X_ELDV_DEVCL_DEVBLC;
6105 else
6106 eldv = G4X_ELDV_DEVCTG;
6107
6108 if (intel_eld_uptodate(connector,
6109 G4X_AUD_CNTL_ST, eldv,
6110 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6111 G4X_HDMIW_HDMIEDID))
6112 return;
6113
6114 i = I915_READ(G4X_AUD_CNTL_ST);
6115 i &= ~(eldv | G4X_ELD_ADDR);
6116 len = (i >> 9) & 0x1f; /* ELD buffer size */
6117 I915_WRITE(G4X_AUD_CNTL_ST, i);
6118
6119 if (!eld[0])
6120 return;
6121
6122 len = min_t(uint8_t, eld[2], len);
6123 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6124 for (i = 0; i < len; i++)
6125 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6126
6127 i = I915_READ(G4X_AUD_CNTL_ST);
6128 i |= eldv;
6129 I915_WRITE(G4X_AUD_CNTL_ST, i);
6130 }
6131
6132 static void haswell_write_eld(struct drm_connector *connector,
6133 struct drm_crtc *crtc)
6134 {
6135 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6136 uint8_t *eld = connector->eld;
6137 struct drm_device *dev = crtc->dev;
6138 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6139 uint32_t eldv;
6140 uint32_t i;
6141 int len;
6142 int pipe = to_intel_crtc(crtc)->pipe;
6143 int tmp;
6144
6145 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6146 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6147 int aud_config = HSW_AUD_CFG(pipe);
6148 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6149
6150
6151 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6152
6153 /* Audio output enable */
6154 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6155 tmp = I915_READ(aud_cntrl_st2);
6156 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6157 I915_WRITE(aud_cntrl_st2, tmp);
6158
6159 /* Wait for 1 vertical blank */
6160 intel_wait_for_vblank(dev, pipe);
6161
6162 /* Set ELD valid state */
6163 tmp = I915_READ(aud_cntrl_st2);
6164 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6165 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6166 I915_WRITE(aud_cntrl_st2, tmp);
6167 tmp = I915_READ(aud_cntrl_st2);
6168 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6169
6170 /* Enable HDMI mode */
6171 tmp = I915_READ(aud_config);
6172 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6173 /* clear N_programing_enable and N_value_index */
6174 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6175 I915_WRITE(aud_config, tmp);
6176
6177 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6178
6179 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6180 intel_crtc->eld_vld = true;
6181
6182 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6183 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6184 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6185 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6186 } else
6187 I915_WRITE(aud_config, 0);
6188
6189 if (intel_eld_uptodate(connector,
6190 aud_cntrl_st2, eldv,
6191 aud_cntl_st, IBX_ELD_ADDRESS,
6192 hdmiw_hdmiedid))
6193 return;
6194
6195 i = I915_READ(aud_cntrl_st2);
6196 i &= ~eldv;
6197 I915_WRITE(aud_cntrl_st2, i);
6198
6199 if (!eld[0])
6200 return;
6201
6202 i = I915_READ(aud_cntl_st);
6203 i &= ~IBX_ELD_ADDRESS;
6204 I915_WRITE(aud_cntl_st, i);
6205 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6206 DRM_DEBUG_DRIVER("port num:%d\n", i);
6207
6208 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6209 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6210 for (i = 0; i < len; i++)
6211 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6212
6213 i = I915_READ(aud_cntrl_st2);
6214 i |= eldv;
6215 I915_WRITE(aud_cntrl_st2, i);
6216
6217 }
6218
6219 static void ironlake_write_eld(struct drm_connector *connector,
6220 struct drm_crtc *crtc)
6221 {
6222 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6223 uint8_t *eld = connector->eld;
6224 uint32_t eldv;
6225 uint32_t i;
6226 int len;
6227 int hdmiw_hdmiedid;
6228 int aud_config;
6229 int aud_cntl_st;
6230 int aud_cntrl_st2;
6231 int pipe = to_intel_crtc(crtc)->pipe;
6232
6233 if (HAS_PCH_IBX(connector->dev)) {
6234 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6235 aud_config = IBX_AUD_CFG(pipe);
6236 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6237 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6238 } else {
6239 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6240 aud_config = CPT_AUD_CFG(pipe);
6241 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6242 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6243 }
6244
6245 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6246
6247 i = I915_READ(aud_cntl_st);
6248 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6249 if (!i) {
6250 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6251 /* operate blindly on all ports */
6252 eldv = IBX_ELD_VALIDB;
6253 eldv |= IBX_ELD_VALIDB << 4;
6254 eldv |= IBX_ELD_VALIDB << 8;
6255 } else {
6256 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6257 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6258 }
6259
6260 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6261 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6262 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6263 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6264 } else
6265 I915_WRITE(aud_config, 0);
6266
6267 if (intel_eld_uptodate(connector,
6268 aud_cntrl_st2, eldv,
6269 aud_cntl_st, IBX_ELD_ADDRESS,
6270 hdmiw_hdmiedid))
6271 return;
6272
6273 i = I915_READ(aud_cntrl_st2);
6274 i &= ~eldv;
6275 I915_WRITE(aud_cntrl_st2, i);
6276
6277 if (!eld[0])
6278 return;
6279
6280 i = I915_READ(aud_cntl_st);
6281 i &= ~IBX_ELD_ADDRESS;
6282 I915_WRITE(aud_cntl_st, i);
6283
6284 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6285 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6286 for (i = 0; i < len; i++)
6287 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6288
6289 i = I915_READ(aud_cntrl_st2);
6290 i |= eldv;
6291 I915_WRITE(aud_cntrl_st2, i);
6292 }
6293
6294 void intel_write_eld(struct drm_encoder *encoder,
6295 struct drm_display_mode *mode)
6296 {
6297 struct drm_crtc *crtc = encoder->crtc;
6298 struct drm_connector *connector;
6299 struct drm_device *dev = encoder->dev;
6300 struct drm_i915_private *dev_priv = dev->dev_private;
6301
6302 connector = drm_select_eld(encoder, mode);
6303 if (!connector)
6304 return;
6305
6306 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6307 connector->base.id,
6308 drm_get_connector_name(connector),
6309 connector->encoder->base.id,
6310 drm_get_encoder_name(connector->encoder));
6311
6312 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6313
6314 if (dev_priv->display.write_eld)
6315 dev_priv->display.write_eld(connector, crtc);
6316 }
6317
6318 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6319 void intel_crtc_load_lut(struct drm_crtc *crtc)
6320 {
6321 struct drm_device *dev = crtc->dev;
6322 struct drm_i915_private *dev_priv = dev->dev_private;
6323 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6324 enum pipe pipe = intel_crtc->pipe;
6325 int palreg = PALETTE(pipe);
6326 int i;
6327 bool reenable_ips = false;
6328
6329 /* The clocks have to be on to load the palette. */
6330 if (!crtc->enabled || !intel_crtc->active)
6331 return;
6332
6333 if (!HAS_PCH_SPLIT(dev_priv->dev))
6334 assert_pll_enabled(dev_priv, pipe);
6335
6336 /* use legacy palette for Ironlake */
6337 if (HAS_PCH_SPLIT(dev))
6338 palreg = LGC_PALETTE(pipe);
6339
6340 /* Workaround : Do not read or write the pipe palette/gamma data while
6341 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6342 */
6343 if (intel_crtc->config.ips_enabled &&
6344 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6345 GAMMA_MODE_MODE_SPLIT)) {
6346 hsw_disable_ips(intel_crtc);
6347 reenable_ips = true;
6348 }
6349
6350 for (i = 0; i < 256; i++) {
6351 I915_WRITE(palreg + 4 * i,
6352 (intel_crtc->lut_r[i] << 16) |
6353 (intel_crtc->lut_g[i] << 8) |
6354 intel_crtc->lut_b[i]);
6355 }
6356
6357 if (reenable_ips)
6358 hsw_enable_ips(intel_crtc);
6359 }
6360
6361 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6362 {
6363 struct drm_device *dev = crtc->dev;
6364 struct drm_i915_private *dev_priv = dev->dev_private;
6365 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6366 bool visible = base != 0;
6367 u32 cntl;
6368
6369 if (intel_crtc->cursor_visible == visible)
6370 return;
6371
6372 cntl = I915_READ(_CURACNTR);
6373 if (visible) {
6374 /* On these chipsets we can only modify the base whilst
6375 * the cursor is disabled.
6376 */
6377 I915_WRITE(_CURABASE, base);
6378
6379 cntl &= ~(CURSOR_FORMAT_MASK);
6380 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6381 cntl |= CURSOR_ENABLE |
6382 CURSOR_GAMMA_ENABLE |
6383 CURSOR_FORMAT_ARGB;
6384 } else
6385 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6386 I915_WRITE(_CURACNTR, cntl);
6387
6388 intel_crtc->cursor_visible = visible;
6389 }
6390
6391 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6392 {
6393 struct drm_device *dev = crtc->dev;
6394 struct drm_i915_private *dev_priv = dev->dev_private;
6395 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6396 int pipe = intel_crtc->pipe;
6397 bool visible = base != 0;
6398
6399 if (intel_crtc->cursor_visible != visible) {
6400 uint32_t cntl = I915_READ(CURCNTR(pipe));
6401 if (base) {
6402 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6403 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6404 cntl |= pipe << 28; /* Connect to correct pipe */
6405 } else {
6406 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6407 cntl |= CURSOR_MODE_DISABLE;
6408 }
6409 I915_WRITE(CURCNTR(pipe), cntl);
6410
6411 intel_crtc->cursor_visible = visible;
6412 }
6413 /* and commit changes on next vblank */
6414 I915_WRITE(CURBASE(pipe), base);
6415 }
6416
6417 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6418 {
6419 struct drm_device *dev = crtc->dev;
6420 struct drm_i915_private *dev_priv = dev->dev_private;
6421 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6422 int pipe = intel_crtc->pipe;
6423 bool visible = base != 0;
6424
6425 if (intel_crtc->cursor_visible != visible) {
6426 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6427 if (base) {
6428 cntl &= ~CURSOR_MODE;
6429 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6430 } else {
6431 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6432 cntl |= CURSOR_MODE_DISABLE;
6433 }
6434 if (IS_HASWELL(dev))
6435 cntl |= CURSOR_PIPE_CSC_ENABLE;
6436 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6437
6438 intel_crtc->cursor_visible = visible;
6439 }
6440 /* and commit changes on next vblank */
6441 I915_WRITE(CURBASE_IVB(pipe), base);
6442 }
6443
6444 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6445 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6446 bool on)
6447 {
6448 struct drm_device *dev = crtc->dev;
6449 struct drm_i915_private *dev_priv = dev->dev_private;
6450 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6451 int pipe = intel_crtc->pipe;
6452 int x = intel_crtc->cursor_x;
6453 int y = intel_crtc->cursor_y;
6454 u32 base, pos;
6455 bool visible;
6456
6457 pos = 0;
6458
6459 if (on && crtc->enabled && crtc->fb) {
6460 base = intel_crtc->cursor_addr;
6461 if (x > (int) crtc->fb->width)
6462 base = 0;
6463
6464 if (y > (int) crtc->fb->height)
6465 base = 0;
6466 } else
6467 base = 0;
6468
6469 if (x < 0) {
6470 if (x + intel_crtc->cursor_width < 0)
6471 base = 0;
6472
6473 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6474 x = -x;
6475 }
6476 pos |= x << CURSOR_X_SHIFT;
6477
6478 if (y < 0) {
6479 if (y + intel_crtc->cursor_height < 0)
6480 base = 0;
6481
6482 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6483 y = -y;
6484 }
6485 pos |= y << CURSOR_Y_SHIFT;
6486
6487 visible = base != 0;
6488 if (!visible && !intel_crtc->cursor_visible)
6489 return;
6490
6491 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6492 I915_WRITE(CURPOS_IVB(pipe), pos);
6493 ivb_update_cursor(crtc, base);
6494 } else {
6495 I915_WRITE(CURPOS(pipe), pos);
6496 if (IS_845G(dev) || IS_I865G(dev))
6497 i845_update_cursor(crtc, base);
6498 else
6499 i9xx_update_cursor(crtc, base);
6500 }
6501 }
6502
6503 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6504 struct drm_file *file,
6505 uint32_t handle,
6506 uint32_t width, uint32_t height)
6507 {
6508 struct drm_device *dev = crtc->dev;
6509 struct drm_i915_private *dev_priv = dev->dev_private;
6510 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6511 struct drm_i915_gem_object *obj;
6512 uint32_t addr;
6513 int ret;
6514
6515 /* if we want to turn off the cursor ignore width and height */
6516 if (!handle) {
6517 DRM_DEBUG_KMS("cursor off\n");
6518 addr = 0;
6519 obj = NULL;
6520 mutex_lock(&dev->struct_mutex);
6521 goto finish;
6522 }
6523
6524 /* Currently we only support 64x64 cursors */
6525 if (width != 64 || height != 64) {
6526 DRM_ERROR("we currently only support 64x64 cursors\n");
6527 return -EINVAL;
6528 }
6529
6530 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6531 if (&obj->base == NULL)
6532 return -ENOENT;
6533
6534 if (obj->base.size < width * height * 4) {
6535 DRM_ERROR("buffer is to small\n");
6536 ret = -ENOMEM;
6537 goto fail;
6538 }
6539
6540 /* we only need to pin inside GTT if cursor is non-phy */
6541 mutex_lock(&dev->struct_mutex);
6542 if (!dev_priv->info->cursor_needs_physical) {
6543 unsigned alignment;
6544
6545 if (obj->tiling_mode) {
6546 DRM_ERROR("cursor cannot be tiled\n");
6547 ret = -EINVAL;
6548 goto fail_locked;
6549 }
6550
6551 /* Note that the w/a also requires 2 PTE of padding following
6552 * the bo. We currently fill all unused PTE with the shadow
6553 * page and so we should always have valid PTE following the
6554 * cursor preventing the VT-d warning.
6555 */
6556 alignment = 0;
6557 if (need_vtd_wa(dev))
6558 alignment = 64*1024;
6559
6560 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6561 if (ret) {
6562 DRM_ERROR("failed to move cursor bo into the GTT\n");
6563 goto fail_locked;
6564 }
6565
6566 ret = i915_gem_object_put_fence(obj);
6567 if (ret) {
6568 DRM_ERROR("failed to release fence for cursor");
6569 goto fail_unpin;
6570 }
6571
6572 addr = i915_gem_obj_ggtt_offset(obj);
6573 } else {
6574 int align = IS_I830(dev) ? 16 * 1024 : 256;
6575 ret = i915_gem_attach_phys_object(dev, obj,
6576 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6577 align);
6578 if (ret) {
6579 DRM_ERROR("failed to attach phys object\n");
6580 goto fail_locked;
6581 }
6582 addr = obj->phys_obj->handle->busaddr;
6583 }
6584
6585 if (IS_GEN2(dev))
6586 I915_WRITE(CURSIZE, (height << 12) | width);
6587
6588 finish:
6589 if (intel_crtc->cursor_bo) {
6590 if (dev_priv->info->cursor_needs_physical) {
6591 if (intel_crtc->cursor_bo != obj)
6592 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6593 } else
6594 i915_gem_object_unpin(intel_crtc->cursor_bo);
6595 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6596 }
6597
6598 mutex_unlock(&dev->struct_mutex);
6599
6600 intel_crtc->cursor_addr = addr;
6601 intel_crtc->cursor_bo = obj;
6602 intel_crtc->cursor_width = width;
6603 intel_crtc->cursor_height = height;
6604
6605 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6606
6607 return 0;
6608 fail_unpin:
6609 i915_gem_object_unpin(obj);
6610 fail_locked:
6611 mutex_unlock(&dev->struct_mutex);
6612 fail:
6613 drm_gem_object_unreference_unlocked(&obj->base);
6614 return ret;
6615 }
6616
6617 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6618 {
6619 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6620
6621 intel_crtc->cursor_x = x;
6622 intel_crtc->cursor_y = y;
6623
6624 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6625
6626 return 0;
6627 }
6628
6629 /** Sets the color ramps on behalf of RandR */
6630 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6631 u16 blue, int regno)
6632 {
6633 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6634
6635 intel_crtc->lut_r[regno] = red >> 8;
6636 intel_crtc->lut_g[regno] = green >> 8;
6637 intel_crtc->lut_b[regno] = blue >> 8;
6638 }
6639
6640 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6641 u16 *blue, int regno)
6642 {
6643 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6644
6645 *red = intel_crtc->lut_r[regno] << 8;
6646 *green = intel_crtc->lut_g[regno] << 8;
6647 *blue = intel_crtc->lut_b[regno] << 8;
6648 }
6649
6650 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6651 u16 *blue, uint32_t start, uint32_t size)
6652 {
6653 int end = (start + size > 256) ? 256 : start + size, i;
6654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6655
6656 for (i = start; i < end; i++) {
6657 intel_crtc->lut_r[i] = red[i] >> 8;
6658 intel_crtc->lut_g[i] = green[i] >> 8;
6659 intel_crtc->lut_b[i] = blue[i] >> 8;
6660 }
6661
6662 intel_crtc_load_lut(crtc);
6663 }
6664
6665 /* VESA 640x480x72Hz mode to set on the pipe */
6666 static struct drm_display_mode load_detect_mode = {
6667 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6668 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6669 };
6670
6671 static struct drm_framebuffer *
6672 intel_framebuffer_create(struct drm_device *dev,
6673 struct drm_mode_fb_cmd2 *mode_cmd,
6674 struct drm_i915_gem_object *obj)
6675 {
6676 struct intel_framebuffer *intel_fb;
6677 int ret;
6678
6679 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6680 if (!intel_fb) {
6681 drm_gem_object_unreference_unlocked(&obj->base);
6682 return ERR_PTR(-ENOMEM);
6683 }
6684
6685 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6686 if (ret) {
6687 drm_gem_object_unreference_unlocked(&obj->base);
6688 kfree(intel_fb);
6689 return ERR_PTR(ret);
6690 }
6691
6692 return &intel_fb->base;
6693 }
6694
6695 static u32
6696 intel_framebuffer_pitch_for_width(int width, int bpp)
6697 {
6698 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6699 return ALIGN(pitch, 64);
6700 }
6701
6702 static u32
6703 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6704 {
6705 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6706 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6707 }
6708
6709 static struct drm_framebuffer *
6710 intel_framebuffer_create_for_mode(struct drm_device *dev,
6711 struct drm_display_mode *mode,
6712 int depth, int bpp)
6713 {
6714 struct drm_i915_gem_object *obj;
6715 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6716
6717 obj = i915_gem_alloc_object(dev,
6718 intel_framebuffer_size_for_mode(mode, bpp));
6719 if (obj == NULL)
6720 return ERR_PTR(-ENOMEM);
6721
6722 mode_cmd.width = mode->hdisplay;
6723 mode_cmd.height = mode->vdisplay;
6724 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6725 bpp);
6726 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6727
6728 return intel_framebuffer_create(dev, &mode_cmd, obj);
6729 }
6730
6731 static struct drm_framebuffer *
6732 mode_fits_in_fbdev(struct drm_device *dev,
6733 struct drm_display_mode *mode)
6734 {
6735 struct drm_i915_private *dev_priv = dev->dev_private;
6736 struct drm_i915_gem_object *obj;
6737 struct drm_framebuffer *fb;
6738
6739 if (dev_priv->fbdev == NULL)
6740 return NULL;
6741
6742 obj = dev_priv->fbdev->ifb.obj;
6743 if (obj == NULL)
6744 return NULL;
6745
6746 fb = &dev_priv->fbdev->ifb.base;
6747 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6748 fb->bits_per_pixel))
6749 return NULL;
6750
6751 if (obj->base.size < mode->vdisplay * fb->pitches[0])
6752 return NULL;
6753
6754 return fb;
6755 }
6756
6757 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6758 struct drm_display_mode *mode,
6759 struct intel_load_detect_pipe *old)
6760 {
6761 struct intel_crtc *intel_crtc;
6762 struct intel_encoder *intel_encoder =
6763 intel_attached_encoder(connector);
6764 struct drm_crtc *possible_crtc;
6765 struct drm_encoder *encoder = &intel_encoder->base;
6766 struct drm_crtc *crtc = NULL;
6767 struct drm_device *dev = encoder->dev;
6768 struct drm_framebuffer *fb;
6769 int i = -1;
6770
6771 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6772 connector->base.id, drm_get_connector_name(connector),
6773 encoder->base.id, drm_get_encoder_name(encoder));
6774
6775 /*
6776 * Algorithm gets a little messy:
6777 *
6778 * - if the connector already has an assigned crtc, use it (but make
6779 * sure it's on first)
6780 *
6781 * - try to find the first unused crtc that can drive this connector,
6782 * and use that if we find one
6783 */
6784
6785 /* See if we already have a CRTC for this connector */
6786 if (encoder->crtc) {
6787 crtc = encoder->crtc;
6788
6789 mutex_lock(&crtc->mutex);
6790
6791 old->dpms_mode = connector->dpms;
6792 old->load_detect_temp = false;
6793
6794 /* Make sure the crtc and connector are running */
6795 if (connector->dpms != DRM_MODE_DPMS_ON)
6796 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6797
6798 return true;
6799 }
6800
6801 /* Find an unused one (if possible) */
6802 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6803 i++;
6804 if (!(encoder->possible_crtcs & (1 << i)))
6805 continue;
6806 if (!possible_crtc->enabled) {
6807 crtc = possible_crtc;
6808 break;
6809 }
6810 }
6811
6812 /*
6813 * If we didn't find an unused CRTC, don't use any.
6814 */
6815 if (!crtc) {
6816 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6817 return false;
6818 }
6819
6820 mutex_lock(&crtc->mutex);
6821 intel_encoder->new_crtc = to_intel_crtc(crtc);
6822 to_intel_connector(connector)->new_encoder = intel_encoder;
6823
6824 intel_crtc = to_intel_crtc(crtc);
6825 old->dpms_mode = connector->dpms;
6826 old->load_detect_temp = true;
6827 old->release_fb = NULL;
6828
6829 if (!mode)
6830 mode = &load_detect_mode;
6831
6832 /* We need a framebuffer large enough to accommodate all accesses
6833 * that the plane may generate whilst we perform load detection.
6834 * We can not rely on the fbcon either being present (we get called
6835 * during its initialisation to detect all boot displays, or it may
6836 * not even exist) or that it is large enough to satisfy the
6837 * requested mode.
6838 */
6839 fb = mode_fits_in_fbdev(dev, mode);
6840 if (fb == NULL) {
6841 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6842 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6843 old->release_fb = fb;
6844 } else
6845 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6846 if (IS_ERR(fb)) {
6847 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6848 mutex_unlock(&crtc->mutex);
6849 return false;
6850 }
6851
6852 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6853 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6854 if (old->release_fb)
6855 old->release_fb->funcs->destroy(old->release_fb);
6856 mutex_unlock(&crtc->mutex);
6857 return false;
6858 }
6859
6860 /* let the connector get through one full cycle before testing */
6861 intel_wait_for_vblank(dev, intel_crtc->pipe);
6862 return true;
6863 }
6864
6865 void intel_release_load_detect_pipe(struct drm_connector *connector,
6866 struct intel_load_detect_pipe *old)
6867 {
6868 struct intel_encoder *intel_encoder =
6869 intel_attached_encoder(connector);
6870 struct drm_encoder *encoder = &intel_encoder->base;
6871 struct drm_crtc *crtc = encoder->crtc;
6872
6873 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6874 connector->base.id, drm_get_connector_name(connector),
6875 encoder->base.id, drm_get_encoder_name(encoder));
6876
6877 if (old->load_detect_temp) {
6878 to_intel_connector(connector)->new_encoder = NULL;
6879 intel_encoder->new_crtc = NULL;
6880 intel_set_mode(crtc, NULL, 0, 0, NULL);
6881
6882 if (old->release_fb) {
6883 drm_framebuffer_unregister_private(old->release_fb);
6884 drm_framebuffer_unreference(old->release_fb);
6885 }
6886
6887 mutex_unlock(&crtc->mutex);
6888 return;
6889 }
6890
6891 /* Switch crtc and encoder back off if necessary */
6892 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6893 connector->funcs->dpms(connector, old->dpms_mode);
6894
6895 mutex_unlock(&crtc->mutex);
6896 }
6897
6898 /* Returns the clock of the currently programmed mode of the given pipe. */
6899 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
6900 struct intel_crtc_config *pipe_config)
6901 {
6902 struct drm_device *dev = crtc->base.dev;
6903 struct drm_i915_private *dev_priv = dev->dev_private;
6904 int pipe = pipe_config->cpu_transcoder;
6905 u32 dpll = I915_READ(DPLL(pipe));
6906 u32 fp;
6907 intel_clock_t clock;
6908
6909 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6910 fp = I915_READ(FP0(pipe));
6911 else
6912 fp = I915_READ(FP1(pipe));
6913
6914 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6915 if (IS_PINEVIEW(dev)) {
6916 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6917 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6918 } else {
6919 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6920 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6921 }
6922
6923 if (!IS_GEN2(dev)) {
6924 if (IS_PINEVIEW(dev))
6925 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6926 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6927 else
6928 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6929 DPLL_FPA01_P1_POST_DIV_SHIFT);
6930
6931 switch (dpll & DPLL_MODE_MASK) {
6932 case DPLLB_MODE_DAC_SERIAL:
6933 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6934 5 : 10;
6935 break;
6936 case DPLLB_MODE_LVDS:
6937 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6938 7 : 14;
6939 break;
6940 default:
6941 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6942 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6943 pipe_config->adjusted_mode.clock = 0;
6944 return;
6945 }
6946
6947 if (IS_PINEVIEW(dev))
6948 pineview_clock(96000, &clock);
6949 else
6950 i9xx_clock(96000, &clock);
6951 } else {
6952 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6953
6954 if (is_lvds) {
6955 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6956 DPLL_FPA01_P1_POST_DIV_SHIFT);
6957 clock.p2 = 14;
6958
6959 if ((dpll & PLL_REF_INPUT_MASK) ==
6960 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6961 /* XXX: might not be 66MHz */
6962 i9xx_clock(66000, &clock);
6963 } else
6964 i9xx_clock(48000, &clock);
6965 } else {
6966 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6967 clock.p1 = 2;
6968 else {
6969 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6970 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6971 }
6972 if (dpll & PLL_P2_DIVIDE_BY_4)
6973 clock.p2 = 4;
6974 else
6975 clock.p2 = 2;
6976
6977 i9xx_clock(48000, &clock);
6978 }
6979 }
6980
6981 pipe_config->adjusted_mode.clock = clock.dot *
6982 pipe_config->pixel_multiplier;
6983 }
6984
6985 static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
6986 struct intel_crtc_config *pipe_config)
6987 {
6988 struct drm_device *dev = crtc->base.dev;
6989 struct drm_i915_private *dev_priv = dev->dev_private;
6990 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6991 int link_freq, repeat;
6992 u64 clock;
6993 u32 link_m, link_n;
6994
6995 repeat = pipe_config->pixel_multiplier;
6996
6997 /*
6998 * The calculation for the data clock is:
6999 * pixel_clock = ((m/n)*(link_clock * nr_lanes * repeat))/bpp
7000 * But we want to avoid losing precison if possible, so:
7001 * pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp))
7002 *
7003 * and the link clock is simpler:
7004 * link_clock = (m * link_clock * repeat) / n
7005 */
7006
7007 /*
7008 * We need to get the FDI or DP link clock here to derive
7009 * the M/N dividers.
7010 *
7011 * For FDI, we read it from the BIOS or use a fixed 2.7GHz.
7012 * For DP, it's either 1.62GHz or 2.7GHz.
7013 * We do our calculations in 10*MHz since we don't need much precison.
7014 */
7015 if (pipe_config->has_pch_encoder)
7016 link_freq = intel_fdi_link_freq(dev) * 10000;
7017 else
7018 link_freq = pipe_config->port_clock;
7019
7020 link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
7021 link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder));
7022
7023 if (!link_m || !link_n)
7024 return;
7025
7026 clock = ((u64)link_m * (u64)link_freq * (u64)repeat);
7027 do_div(clock, link_n);
7028
7029 pipe_config->adjusted_mode.clock = clock;
7030 }
7031
7032 /** Returns the currently programmed mode of the given pipe. */
7033 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7034 struct drm_crtc *crtc)
7035 {
7036 struct drm_i915_private *dev_priv = dev->dev_private;
7037 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7038 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7039 struct drm_display_mode *mode;
7040 struct intel_crtc_config pipe_config;
7041 int htot = I915_READ(HTOTAL(cpu_transcoder));
7042 int hsync = I915_READ(HSYNC(cpu_transcoder));
7043 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7044 int vsync = I915_READ(VSYNC(cpu_transcoder));
7045
7046 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7047 if (!mode)
7048 return NULL;
7049
7050 /*
7051 * Construct a pipe_config sufficient for getting the clock info
7052 * back out of crtc_clock_get.
7053 *
7054 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7055 * to use a real value here instead.
7056 */
7057 pipe_config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
7058 pipe_config.pixel_multiplier = 1;
7059 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7060
7061 mode->clock = pipe_config.adjusted_mode.clock;
7062 mode->hdisplay = (htot & 0xffff) + 1;
7063 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7064 mode->hsync_start = (hsync & 0xffff) + 1;
7065 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7066 mode->vdisplay = (vtot & 0xffff) + 1;
7067 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7068 mode->vsync_start = (vsync & 0xffff) + 1;
7069 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7070
7071 drm_mode_set_name(mode);
7072
7073 return mode;
7074 }
7075
7076 static void intel_increase_pllclock(struct drm_crtc *crtc)
7077 {
7078 struct drm_device *dev = crtc->dev;
7079 drm_i915_private_t *dev_priv = dev->dev_private;
7080 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7081 int pipe = intel_crtc->pipe;
7082 int dpll_reg = DPLL(pipe);
7083 int dpll;
7084
7085 if (HAS_PCH_SPLIT(dev))
7086 return;
7087
7088 if (!dev_priv->lvds_downclock_avail)
7089 return;
7090
7091 dpll = I915_READ(dpll_reg);
7092 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7093 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7094
7095 assert_panel_unlocked(dev_priv, pipe);
7096
7097 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7098 I915_WRITE(dpll_reg, dpll);
7099 intel_wait_for_vblank(dev, pipe);
7100
7101 dpll = I915_READ(dpll_reg);
7102 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7103 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7104 }
7105 }
7106
7107 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7108 {
7109 struct drm_device *dev = crtc->dev;
7110 drm_i915_private_t *dev_priv = dev->dev_private;
7111 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7112
7113 if (HAS_PCH_SPLIT(dev))
7114 return;
7115
7116 if (!dev_priv->lvds_downclock_avail)
7117 return;
7118
7119 /*
7120 * Since this is called by a timer, we should never get here in
7121 * the manual case.
7122 */
7123 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7124 int pipe = intel_crtc->pipe;
7125 int dpll_reg = DPLL(pipe);
7126 int dpll;
7127
7128 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7129
7130 assert_panel_unlocked(dev_priv, pipe);
7131
7132 dpll = I915_READ(dpll_reg);
7133 dpll |= DISPLAY_RATE_SELECT_FPA1;
7134 I915_WRITE(dpll_reg, dpll);
7135 intel_wait_for_vblank(dev, pipe);
7136 dpll = I915_READ(dpll_reg);
7137 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7138 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7139 }
7140
7141 }
7142
7143 void intel_mark_busy(struct drm_device *dev)
7144 {
7145 i915_update_gfx_val(dev->dev_private);
7146 }
7147
7148 void intel_mark_idle(struct drm_device *dev)
7149 {
7150 struct drm_crtc *crtc;
7151
7152 if (!i915_powersave)
7153 return;
7154
7155 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7156 if (!crtc->fb)
7157 continue;
7158
7159 intel_decrease_pllclock(crtc);
7160 }
7161 }
7162
7163 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7164 struct intel_ring_buffer *ring)
7165 {
7166 struct drm_device *dev = obj->base.dev;
7167 struct drm_crtc *crtc;
7168
7169 if (!i915_powersave)
7170 return;
7171
7172 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7173 if (!crtc->fb)
7174 continue;
7175
7176 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7177 continue;
7178
7179 intel_increase_pllclock(crtc);
7180 if (ring && intel_fbc_enabled(dev))
7181 ring->fbc_dirty = true;
7182 }
7183 }
7184
7185 static void intel_crtc_destroy(struct drm_crtc *crtc)
7186 {
7187 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7188 struct drm_device *dev = crtc->dev;
7189 struct intel_unpin_work *work;
7190 unsigned long flags;
7191
7192 spin_lock_irqsave(&dev->event_lock, flags);
7193 work = intel_crtc->unpin_work;
7194 intel_crtc->unpin_work = NULL;
7195 spin_unlock_irqrestore(&dev->event_lock, flags);
7196
7197 if (work) {
7198 cancel_work_sync(&work->work);
7199 kfree(work);
7200 }
7201
7202 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7203
7204 drm_crtc_cleanup(crtc);
7205
7206 kfree(intel_crtc);
7207 }
7208
7209 static void intel_unpin_work_fn(struct work_struct *__work)
7210 {
7211 struct intel_unpin_work *work =
7212 container_of(__work, struct intel_unpin_work, work);
7213 struct drm_device *dev = work->crtc->dev;
7214
7215 mutex_lock(&dev->struct_mutex);
7216 intel_unpin_fb_obj(work->old_fb_obj);
7217 drm_gem_object_unreference(&work->pending_flip_obj->base);
7218 drm_gem_object_unreference(&work->old_fb_obj->base);
7219
7220 intel_update_fbc(dev);
7221 mutex_unlock(&dev->struct_mutex);
7222
7223 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7224 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7225
7226 kfree(work);
7227 }
7228
7229 static void do_intel_finish_page_flip(struct drm_device *dev,
7230 struct drm_crtc *crtc)
7231 {
7232 drm_i915_private_t *dev_priv = dev->dev_private;
7233 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7234 struct intel_unpin_work *work;
7235 unsigned long flags;
7236
7237 /* Ignore early vblank irqs */
7238 if (intel_crtc == NULL)
7239 return;
7240
7241 spin_lock_irqsave(&dev->event_lock, flags);
7242 work = intel_crtc->unpin_work;
7243
7244 /* Ensure we don't miss a work->pending update ... */
7245 smp_rmb();
7246
7247 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7248 spin_unlock_irqrestore(&dev->event_lock, flags);
7249 return;
7250 }
7251
7252 /* and that the unpin work is consistent wrt ->pending. */
7253 smp_rmb();
7254
7255 intel_crtc->unpin_work = NULL;
7256
7257 if (work->event)
7258 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7259
7260 drm_vblank_put(dev, intel_crtc->pipe);
7261
7262 spin_unlock_irqrestore(&dev->event_lock, flags);
7263
7264 wake_up_all(&dev_priv->pending_flip_queue);
7265
7266 queue_work(dev_priv->wq, &work->work);
7267
7268 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7269 }
7270
7271 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7272 {
7273 drm_i915_private_t *dev_priv = dev->dev_private;
7274 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7275
7276 do_intel_finish_page_flip(dev, crtc);
7277 }
7278
7279 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7280 {
7281 drm_i915_private_t *dev_priv = dev->dev_private;
7282 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7283
7284 do_intel_finish_page_flip(dev, crtc);
7285 }
7286
7287 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7288 {
7289 drm_i915_private_t *dev_priv = dev->dev_private;
7290 struct intel_crtc *intel_crtc =
7291 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7292 unsigned long flags;
7293
7294 /* NB: An MMIO update of the plane base pointer will also
7295 * generate a page-flip completion irq, i.e. every modeset
7296 * is also accompanied by a spurious intel_prepare_page_flip().
7297 */
7298 spin_lock_irqsave(&dev->event_lock, flags);
7299 if (intel_crtc->unpin_work)
7300 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7301 spin_unlock_irqrestore(&dev->event_lock, flags);
7302 }
7303
7304 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7305 {
7306 /* Ensure that the work item is consistent when activating it ... */
7307 smp_wmb();
7308 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7309 /* and that it is marked active as soon as the irq could fire. */
7310 smp_wmb();
7311 }
7312
7313 static int intel_gen2_queue_flip(struct drm_device *dev,
7314 struct drm_crtc *crtc,
7315 struct drm_framebuffer *fb,
7316 struct drm_i915_gem_object *obj)
7317 {
7318 struct drm_i915_private *dev_priv = dev->dev_private;
7319 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7320 u32 flip_mask;
7321 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7322 int ret;
7323
7324 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7325 if (ret)
7326 goto err;
7327
7328 ret = intel_ring_begin(ring, 6);
7329 if (ret)
7330 goto err_unpin;
7331
7332 /* Can't queue multiple flips, so wait for the previous
7333 * one to finish before executing the next.
7334 */
7335 if (intel_crtc->plane)
7336 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7337 else
7338 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7339 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7340 intel_ring_emit(ring, MI_NOOP);
7341 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7342 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7343 intel_ring_emit(ring, fb->pitches[0]);
7344 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7345 intel_ring_emit(ring, 0); /* aux display base address, unused */
7346
7347 intel_mark_page_flip_active(intel_crtc);
7348 intel_ring_advance(ring);
7349 return 0;
7350
7351 err_unpin:
7352 intel_unpin_fb_obj(obj);
7353 err:
7354 return ret;
7355 }
7356
7357 static int intel_gen3_queue_flip(struct drm_device *dev,
7358 struct drm_crtc *crtc,
7359 struct drm_framebuffer *fb,
7360 struct drm_i915_gem_object *obj)
7361 {
7362 struct drm_i915_private *dev_priv = dev->dev_private;
7363 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7364 u32 flip_mask;
7365 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7366 int ret;
7367
7368 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7369 if (ret)
7370 goto err;
7371
7372 ret = intel_ring_begin(ring, 6);
7373 if (ret)
7374 goto err_unpin;
7375
7376 if (intel_crtc->plane)
7377 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7378 else
7379 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7380 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7381 intel_ring_emit(ring, MI_NOOP);
7382 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7383 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7384 intel_ring_emit(ring, fb->pitches[0]);
7385 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7386 intel_ring_emit(ring, MI_NOOP);
7387
7388 intel_mark_page_flip_active(intel_crtc);
7389 intel_ring_advance(ring);
7390 return 0;
7391
7392 err_unpin:
7393 intel_unpin_fb_obj(obj);
7394 err:
7395 return ret;
7396 }
7397
7398 static int intel_gen4_queue_flip(struct drm_device *dev,
7399 struct drm_crtc *crtc,
7400 struct drm_framebuffer *fb,
7401 struct drm_i915_gem_object *obj)
7402 {
7403 struct drm_i915_private *dev_priv = dev->dev_private;
7404 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7405 uint32_t pf, pipesrc;
7406 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7407 int ret;
7408
7409 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7410 if (ret)
7411 goto err;
7412
7413 ret = intel_ring_begin(ring, 4);
7414 if (ret)
7415 goto err_unpin;
7416
7417 /* i965+ uses the linear or tiled offsets from the
7418 * Display Registers (which do not change across a page-flip)
7419 * so we need only reprogram the base address.
7420 */
7421 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7422 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7423 intel_ring_emit(ring, fb->pitches[0]);
7424 intel_ring_emit(ring,
7425 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
7426 obj->tiling_mode);
7427
7428 /* XXX Enabling the panel-fitter across page-flip is so far
7429 * untested on non-native modes, so ignore it for now.
7430 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7431 */
7432 pf = 0;
7433 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7434 intel_ring_emit(ring, pf | pipesrc);
7435
7436 intel_mark_page_flip_active(intel_crtc);
7437 intel_ring_advance(ring);
7438 return 0;
7439
7440 err_unpin:
7441 intel_unpin_fb_obj(obj);
7442 err:
7443 return ret;
7444 }
7445
7446 static int intel_gen6_queue_flip(struct drm_device *dev,
7447 struct drm_crtc *crtc,
7448 struct drm_framebuffer *fb,
7449 struct drm_i915_gem_object *obj)
7450 {
7451 struct drm_i915_private *dev_priv = dev->dev_private;
7452 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7453 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7454 uint32_t pf, pipesrc;
7455 int ret;
7456
7457 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7458 if (ret)
7459 goto err;
7460
7461 ret = intel_ring_begin(ring, 4);
7462 if (ret)
7463 goto err_unpin;
7464
7465 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7466 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7467 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7468 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7469
7470 /* Contrary to the suggestions in the documentation,
7471 * "Enable Panel Fitter" does not seem to be required when page
7472 * flipping with a non-native mode, and worse causes a normal
7473 * modeset to fail.
7474 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7475 */
7476 pf = 0;
7477 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7478 intel_ring_emit(ring, pf | pipesrc);
7479
7480 intel_mark_page_flip_active(intel_crtc);
7481 intel_ring_advance(ring);
7482 return 0;
7483
7484 err_unpin:
7485 intel_unpin_fb_obj(obj);
7486 err:
7487 return ret;
7488 }
7489
7490 /*
7491 * On gen7 we currently use the blit ring because (in early silicon at least)
7492 * the render ring doesn't give us interrpts for page flip completion, which
7493 * means clients will hang after the first flip is queued. Fortunately the
7494 * blit ring generates interrupts properly, so use it instead.
7495 */
7496 static int intel_gen7_queue_flip(struct drm_device *dev,
7497 struct drm_crtc *crtc,
7498 struct drm_framebuffer *fb,
7499 struct drm_i915_gem_object *obj)
7500 {
7501 struct drm_i915_private *dev_priv = dev->dev_private;
7502 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7503 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7504 uint32_t plane_bit = 0;
7505 int ret;
7506
7507 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7508 if (ret)
7509 goto err;
7510
7511 switch(intel_crtc->plane) {
7512 case PLANE_A:
7513 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7514 break;
7515 case PLANE_B:
7516 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7517 break;
7518 case PLANE_C:
7519 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7520 break;
7521 default:
7522 WARN_ONCE(1, "unknown plane in flip command\n");
7523 ret = -ENODEV;
7524 goto err_unpin;
7525 }
7526
7527 ret = intel_ring_begin(ring, 4);
7528 if (ret)
7529 goto err_unpin;
7530
7531 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7532 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7533 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7534 intel_ring_emit(ring, (MI_NOOP));
7535
7536 intel_mark_page_flip_active(intel_crtc);
7537 intel_ring_advance(ring);
7538 return 0;
7539
7540 err_unpin:
7541 intel_unpin_fb_obj(obj);
7542 err:
7543 return ret;
7544 }
7545
7546 static int intel_default_queue_flip(struct drm_device *dev,
7547 struct drm_crtc *crtc,
7548 struct drm_framebuffer *fb,
7549 struct drm_i915_gem_object *obj)
7550 {
7551 return -ENODEV;
7552 }
7553
7554 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7555 struct drm_framebuffer *fb,
7556 struct drm_pending_vblank_event *event)
7557 {
7558 struct drm_device *dev = crtc->dev;
7559 struct drm_i915_private *dev_priv = dev->dev_private;
7560 struct drm_framebuffer *old_fb = crtc->fb;
7561 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7562 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7563 struct intel_unpin_work *work;
7564 unsigned long flags;
7565 int ret;
7566
7567 /* Can't change pixel format via MI display flips. */
7568 if (fb->pixel_format != crtc->fb->pixel_format)
7569 return -EINVAL;
7570
7571 /*
7572 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7573 * Note that pitch changes could also affect these register.
7574 */
7575 if (INTEL_INFO(dev)->gen > 3 &&
7576 (fb->offsets[0] != crtc->fb->offsets[0] ||
7577 fb->pitches[0] != crtc->fb->pitches[0]))
7578 return -EINVAL;
7579
7580 work = kzalloc(sizeof *work, GFP_KERNEL);
7581 if (work == NULL)
7582 return -ENOMEM;
7583
7584 work->event = event;
7585 work->crtc = crtc;
7586 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7587 INIT_WORK(&work->work, intel_unpin_work_fn);
7588
7589 ret = drm_vblank_get(dev, intel_crtc->pipe);
7590 if (ret)
7591 goto free_work;
7592
7593 /* We borrow the event spin lock for protecting unpin_work */
7594 spin_lock_irqsave(&dev->event_lock, flags);
7595 if (intel_crtc->unpin_work) {
7596 spin_unlock_irqrestore(&dev->event_lock, flags);
7597 kfree(work);
7598 drm_vblank_put(dev, intel_crtc->pipe);
7599
7600 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7601 return -EBUSY;
7602 }
7603 intel_crtc->unpin_work = work;
7604 spin_unlock_irqrestore(&dev->event_lock, flags);
7605
7606 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7607 flush_workqueue(dev_priv->wq);
7608
7609 ret = i915_mutex_lock_interruptible(dev);
7610 if (ret)
7611 goto cleanup;
7612
7613 /* Reference the objects for the scheduled work. */
7614 drm_gem_object_reference(&work->old_fb_obj->base);
7615 drm_gem_object_reference(&obj->base);
7616
7617 crtc->fb = fb;
7618
7619 work->pending_flip_obj = obj;
7620
7621 work->enable_stall_check = true;
7622
7623 atomic_inc(&intel_crtc->unpin_work_count);
7624 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7625
7626 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7627 if (ret)
7628 goto cleanup_pending;
7629
7630 intel_disable_fbc(dev);
7631 intel_mark_fb_busy(obj, NULL);
7632 mutex_unlock(&dev->struct_mutex);
7633
7634 trace_i915_flip_request(intel_crtc->plane, obj);
7635
7636 return 0;
7637
7638 cleanup_pending:
7639 atomic_dec(&intel_crtc->unpin_work_count);
7640 crtc->fb = old_fb;
7641 drm_gem_object_unreference(&work->old_fb_obj->base);
7642 drm_gem_object_unreference(&obj->base);
7643 mutex_unlock(&dev->struct_mutex);
7644
7645 cleanup:
7646 spin_lock_irqsave(&dev->event_lock, flags);
7647 intel_crtc->unpin_work = NULL;
7648 spin_unlock_irqrestore(&dev->event_lock, flags);
7649
7650 drm_vblank_put(dev, intel_crtc->pipe);
7651 free_work:
7652 kfree(work);
7653
7654 return ret;
7655 }
7656
7657 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7658 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7659 .load_lut = intel_crtc_load_lut,
7660 };
7661
7662 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7663 struct drm_crtc *crtc)
7664 {
7665 struct drm_device *dev;
7666 struct drm_crtc *tmp;
7667 int crtc_mask = 1;
7668
7669 WARN(!crtc, "checking null crtc?\n");
7670
7671 dev = crtc->dev;
7672
7673 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7674 if (tmp == crtc)
7675 break;
7676 crtc_mask <<= 1;
7677 }
7678
7679 if (encoder->possible_crtcs & crtc_mask)
7680 return true;
7681 return false;
7682 }
7683
7684 /**
7685 * intel_modeset_update_staged_output_state
7686 *
7687 * Updates the staged output configuration state, e.g. after we've read out the
7688 * current hw state.
7689 */
7690 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7691 {
7692 struct intel_encoder *encoder;
7693 struct intel_connector *connector;
7694
7695 list_for_each_entry(connector, &dev->mode_config.connector_list,
7696 base.head) {
7697 connector->new_encoder =
7698 to_intel_encoder(connector->base.encoder);
7699 }
7700
7701 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7702 base.head) {
7703 encoder->new_crtc =
7704 to_intel_crtc(encoder->base.crtc);
7705 }
7706 }
7707
7708 /**
7709 * intel_modeset_commit_output_state
7710 *
7711 * This function copies the stage display pipe configuration to the real one.
7712 */
7713 static void intel_modeset_commit_output_state(struct drm_device *dev)
7714 {
7715 struct intel_encoder *encoder;
7716 struct intel_connector *connector;
7717
7718 list_for_each_entry(connector, &dev->mode_config.connector_list,
7719 base.head) {
7720 connector->base.encoder = &connector->new_encoder->base;
7721 }
7722
7723 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7724 base.head) {
7725 encoder->base.crtc = &encoder->new_crtc->base;
7726 }
7727 }
7728
7729 static void
7730 connected_sink_compute_bpp(struct intel_connector * connector,
7731 struct intel_crtc_config *pipe_config)
7732 {
7733 int bpp = pipe_config->pipe_bpp;
7734
7735 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7736 connector->base.base.id,
7737 drm_get_connector_name(&connector->base));
7738
7739 /* Don't use an invalid EDID bpc value */
7740 if (connector->base.display_info.bpc &&
7741 connector->base.display_info.bpc * 3 < bpp) {
7742 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7743 bpp, connector->base.display_info.bpc*3);
7744 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7745 }
7746
7747 /* Clamp bpp to 8 on screens without EDID 1.4 */
7748 if (connector->base.display_info.bpc == 0 && bpp > 24) {
7749 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7750 bpp);
7751 pipe_config->pipe_bpp = 24;
7752 }
7753 }
7754
7755 static int
7756 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7757 struct drm_framebuffer *fb,
7758 struct intel_crtc_config *pipe_config)
7759 {
7760 struct drm_device *dev = crtc->base.dev;
7761 struct intel_connector *connector;
7762 int bpp;
7763
7764 switch (fb->pixel_format) {
7765 case DRM_FORMAT_C8:
7766 bpp = 8*3; /* since we go through a colormap */
7767 break;
7768 case DRM_FORMAT_XRGB1555:
7769 case DRM_FORMAT_ARGB1555:
7770 /* checked in intel_framebuffer_init already */
7771 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7772 return -EINVAL;
7773 case DRM_FORMAT_RGB565:
7774 bpp = 6*3; /* min is 18bpp */
7775 break;
7776 case DRM_FORMAT_XBGR8888:
7777 case DRM_FORMAT_ABGR8888:
7778 /* checked in intel_framebuffer_init already */
7779 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7780 return -EINVAL;
7781 case DRM_FORMAT_XRGB8888:
7782 case DRM_FORMAT_ARGB8888:
7783 bpp = 8*3;
7784 break;
7785 case DRM_FORMAT_XRGB2101010:
7786 case DRM_FORMAT_ARGB2101010:
7787 case DRM_FORMAT_XBGR2101010:
7788 case DRM_FORMAT_ABGR2101010:
7789 /* checked in intel_framebuffer_init already */
7790 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7791 return -EINVAL;
7792 bpp = 10*3;
7793 break;
7794 /* TODO: gen4+ supports 16 bpc floating point, too. */
7795 default:
7796 DRM_DEBUG_KMS("unsupported depth\n");
7797 return -EINVAL;
7798 }
7799
7800 pipe_config->pipe_bpp = bpp;
7801
7802 /* Clamp display bpp to EDID value */
7803 list_for_each_entry(connector, &dev->mode_config.connector_list,
7804 base.head) {
7805 if (!connector->new_encoder ||
7806 connector->new_encoder->new_crtc != crtc)
7807 continue;
7808
7809 connected_sink_compute_bpp(connector, pipe_config);
7810 }
7811
7812 return bpp;
7813 }
7814
7815 static void intel_dump_pipe_config(struct intel_crtc *crtc,
7816 struct intel_crtc_config *pipe_config,
7817 const char *context)
7818 {
7819 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7820 context, pipe_name(crtc->pipe));
7821
7822 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7823 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7824 pipe_config->pipe_bpp, pipe_config->dither);
7825 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7826 pipe_config->has_pch_encoder,
7827 pipe_config->fdi_lanes,
7828 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7829 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7830 pipe_config->fdi_m_n.tu);
7831 DRM_DEBUG_KMS("requested mode:\n");
7832 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7833 DRM_DEBUG_KMS("adjusted mode:\n");
7834 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7835 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7836 pipe_config->gmch_pfit.control,
7837 pipe_config->gmch_pfit.pgm_ratios,
7838 pipe_config->gmch_pfit.lvds_border_bits);
7839 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7840 pipe_config->pch_pfit.pos,
7841 pipe_config->pch_pfit.size);
7842 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
7843 }
7844
7845 static bool check_encoder_cloning(struct drm_crtc *crtc)
7846 {
7847 int num_encoders = 0;
7848 bool uncloneable_encoders = false;
7849 struct intel_encoder *encoder;
7850
7851 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
7852 base.head) {
7853 if (&encoder->new_crtc->base != crtc)
7854 continue;
7855
7856 num_encoders++;
7857 if (!encoder->cloneable)
7858 uncloneable_encoders = true;
7859 }
7860
7861 return !(num_encoders > 1 && uncloneable_encoders);
7862 }
7863
7864 static struct intel_crtc_config *
7865 intel_modeset_pipe_config(struct drm_crtc *crtc,
7866 struct drm_framebuffer *fb,
7867 struct drm_display_mode *mode)
7868 {
7869 struct drm_device *dev = crtc->dev;
7870 struct drm_encoder_helper_funcs *encoder_funcs;
7871 struct intel_encoder *encoder;
7872 struct intel_crtc_config *pipe_config;
7873 int plane_bpp, ret = -EINVAL;
7874 bool retry = true;
7875
7876 if (!check_encoder_cloning(crtc)) {
7877 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
7878 return ERR_PTR(-EINVAL);
7879 }
7880
7881 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7882 if (!pipe_config)
7883 return ERR_PTR(-ENOMEM);
7884
7885 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7886 drm_mode_copy(&pipe_config->requested_mode, mode);
7887 pipe_config->cpu_transcoder =
7888 (enum transcoder) to_intel_crtc(crtc)->pipe;
7889 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7890
7891 /* Compute a starting value for pipe_config->pipe_bpp taking the source
7892 * plane pixel format and any sink constraints into account. Returns the
7893 * source plane bpp so that dithering can be selected on mismatches
7894 * after encoders and crtc also have had their say. */
7895 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7896 fb, pipe_config);
7897 if (plane_bpp < 0)
7898 goto fail;
7899
7900 encoder_retry:
7901 /* Ensure the port clock defaults are reset when retrying. */
7902 pipe_config->port_clock = 0;
7903 pipe_config->pixel_multiplier = 1;
7904
7905 /* Pass our mode to the connectors and the CRTC to give them a chance to
7906 * adjust it according to limitations or connector properties, and also
7907 * a chance to reject the mode entirely.
7908 */
7909 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7910 base.head) {
7911
7912 if (&encoder->new_crtc->base != crtc)
7913 continue;
7914
7915 if (encoder->compute_config) {
7916 if (!(encoder->compute_config(encoder, pipe_config))) {
7917 DRM_DEBUG_KMS("Encoder config failure\n");
7918 goto fail;
7919 }
7920
7921 continue;
7922 }
7923
7924 encoder_funcs = encoder->base.helper_private;
7925 if (!(encoder_funcs->mode_fixup(&encoder->base,
7926 &pipe_config->requested_mode,
7927 &pipe_config->adjusted_mode))) {
7928 DRM_DEBUG_KMS("Encoder fixup failed\n");
7929 goto fail;
7930 }
7931 }
7932
7933 /* Set default port clock if not overwritten by the encoder. Needs to be
7934 * done afterwards in case the encoder adjusts the mode. */
7935 if (!pipe_config->port_clock)
7936 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
7937
7938 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
7939 if (ret < 0) {
7940 DRM_DEBUG_KMS("CRTC fixup failed\n");
7941 goto fail;
7942 }
7943
7944 if (ret == RETRY) {
7945 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7946 ret = -EINVAL;
7947 goto fail;
7948 }
7949
7950 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7951 retry = false;
7952 goto encoder_retry;
7953 }
7954
7955 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7956 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7957 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7958
7959 return pipe_config;
7960 fail:
7961 kfree(pipe_config);
7962 return ERR_PTR(ret);
7963 }
7964
7965 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7966 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7967 static void
7968 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7969 unsigned *prepare_pipes, unsigned *disable_pipes)
7970 {
7971 struct intel_crtc *intel_crtc;
7972 struct drm_device *dev = crtc->dev;
7973 struct intel_encoder *encoder;
7974 struct intel_connector *connector;
7975 struct drm_crtc *tmp_crtc;
7976
7977 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7978
7979 /* Check which crtcs have changed outputs connected to them, these need
7980 * to be part of the prepare_pipes mask. We don't (yet) support global
7981 * modeset across multiple crtcs, so modeset_pipes will only have one
7982 * bit set at most. */
7983 list_for_each_entry(connector, &dev->mode_config.connector_list,
7984 base.head) {
7985 if (connector->base.encoder == &connector->new_encoder->base)
7986 continue;
7987
7988 if (connector->base.encoder) {
7989 tmp_crtc = connector->base.encoder->crtc;
7990
7991 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7992 }
7993
7994 if (connector->new_encoder)
7995 *prepare_pipes |=
7996 1 << connector->new_encoder->new_crtc->pipe;
7997 }
7998
7999 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8000 base.head) {
8001 if (encoder->base.crtc == &encoder->new_crtc->base)
8002 continue;
8003
8004 if (encoder->base.crtc) {
8005 tmp_crtc = encoder->base.crtc;
8006
8007 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8008 }
8009
8010 if (encoder->new_crtc)
8011 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
8012 }
8013
8014 /* Check for any pipes that will be fully disabled ... */
8015 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8016 base.head) {
8017 bool used = false;
8018
8019 /* Don't try to disable disabled crtcs. */
8020 if (!intel_crtc->base.enabled)
8021 continue;
8022
8023 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8024 base.head) {
8025 if (encoder->new_crtc == intel_crtc)
8026 used = true;
8027 }
8028
8029 if (!used)
8030 *disable_pipes |= 1 << intel_crtc->pipe;
8031 }
8032
8033
8034 /* set_mode is also used to update properties on life display pipes. */
8035 intel_crtc = to_intel_crtc(crtc);
8036 if (crtc->enabled)
8037 *prepare_pipes |= 1 << intel_crtc->pipe;
8038
8039 /*
8040 * For simplicity do a full modeset on any pipe where the output routing
8041 * changed. We could be more clever, but that would require us to be
8042 * more careful with calling the relevant encoder->mode_set functions.
8043 */
8044 if (*prepare_pipes)
8045 *modeset_pipes = *prepare_pipes;
8046
8047 /* ... and mask these out. */
8048 *modeset_pipes &= ~(*disable_pipes);
8049 *prepare_pipes &= ~(*disable_pipes);
8050
8051 /*
8052 * HACK: We don't (yet) fully support global modesets. intel_set_config
8053 * obies this rule, but the modeset restore mode of
8054 * intel_modeset_setup_hw_state does not.
8055 */
8056 *modeset_pipes &= 1 << intel_crtc->pipe;
8057 *prepare_pipes &= 1 << intel_crtc->pipe;
8058
8059 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8060 *modeset_pipes, *prepare_pipes, *disable_pipes);
8061 }
8062
8063 static bool intel_crtc_in_use(struct drm_crtc *crtc)
8064 {
8065 struct drm_encoder *encoder;
8066 struct drm_device *dev = crtc->dev;
8067
8068 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8069 if (encoder->crtc == crtc)
8070 return true;
8071
8072 return false;
8073 }
8074
8075 static void
8076 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8077 {
8078 struct intel_encoder *intel_encoder;
8079 struct intel_crtc *intel_crtc;
8080 struct drm_connector *connector;
8081
8082 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8083 base.head) {
8084 if (!intel_encoder->base.crtc)
8085 continue;
8086
8087 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8088
8089 if (prepare_pipes & (1 << intel_crtc->pipe))
8090 intel_encoder->connectors_active = false;
8091 }
8092
8093 intel_modeset_commit_output_state(dev);
8094
8095 /* Update computed state. */
8096 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8097 base.head) {
8098 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8099 }
8100
8101 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8102 if (!connector->encoder || !connector->encoder->crtc)
8103 continue;
8104
8105 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8106
8107 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8108 struct drm_property *dpms_property =
8109 dev->mode_config.dpms_property;
8110
8111 connector->dpms = DRM_MODE_DPMS_ON;
8112 drm_object_property_set_value(&connector->base,
8113 dpms_property,
8114 DRM_MODE_DPMS_ON);
8115
8116 intel_encoder = to_intel_encoder(connector->encoder);
8117 intel_encoder->connectors_active = true;
8118 }
8119 }
8120
8121 }
8122
8123 static bool intel_fuzzy_clock_check(struct intel_crtc_config *cur,
8124 struct intel_crtc_config *new)
8125 {
8126 int clock1, clock2, diff;
8127
8128 clock1 = cur->adjusted_mode.clock;
8129 clock2 = new->adjusted_mode.clock;
8130
8131 if (clock1 == clock2)
8132 return true;
8133
8134 if (!clock1 || !clock2)
8135 return false;
8136
8137 diff = abs(clock1 - clock2);
8138
8139 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8140 return true;
8141
8142 return false;
8143 }
8144
8145 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8146 list_for_each_entry((intel_crtc), \
8147 &(dev)->mode_config.crtc_list, \
8148 base.head) \
8149 if (mask & (1 <<(intel_crtc)->pipe))
8150
8151 static bool
8152 intel_pipe_config_compare(struct drm_device *dev,
8153 struct intel_crtc_config *current_config,
8154 struct intel_crtc_config *pipe_config)
8155 {
8156 #define PIPE_CONF_CHECK_X(name) \
8157 if (current_config->name != pipe_config->name) { \
8158 DRM_ERROR("mismatch in " #name " " \
8159 "(expected 0x%08x, found 0x%08x)\n", \
8160 current_config->name, \
8161 pipe_config->name); \
8162 return false; \
8163 }
8164
8165 #define PIPE_CONF_CHECK_I(name) \
8166 if (current_config->name != pipe_config->name) { \
8167 DRM_ERROR("mismatch in " #name " " \
8168 "(expected %i, found %i)\n", \
8169 current_config->name, \
8170 pipe_config->name); \
8171 return false; \
8172 }
8173
8174 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
8175 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8176 DRM_ERROR("mismatch in " #name "(" #mask ") " \
8177 "(expected %i, found %i)\n", \
8178 current_config->name & (mask), \
8179 pipe_config->name & (mask)); \
8180 return false; \
8181 }
8182
8183 #define PIPE_CONF_QUIRK(quirk) \
8184 ((current_config->quirks | pipe_config->quirks) & (quirk))
8185
8186 PIPE_CONF_CHECK_I(cpu_transcoder);
8187
8188 PIPE_CONF_CHECK_I(has_pch_encoder);
8189 PIPE_CONF_CHECK_I(fdi_lanes);
8190 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8191 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8192 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8193 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8194 PIPE_CONF_CHECK_I(fdi_m_n.tu);
8195
8196 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8197 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8198 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8199 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8200 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8201 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8202
8203 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8204 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8205 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8206 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8207 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8208 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8209
8210 PIPE_CONF_CHECK_I(pixel_multiplier);
8211
8212 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8213 DRM_MODE_FLAG_INTERLACE);
8214
8215 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8216 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8217 DRM_MODE_FLAG_PHSYNC);
8218 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8219 DRM_MODE_FLAG_NHSYNC);
8220 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8221 DRM_MODE_FLAG_PVSYNC);
8222 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8223 DRM_MODE_FLAG_NVSYNC);
8224 }
8225
8226 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8227 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8228
8229 PIPE_CONF_CHECK_I(gmch_pfit.control);
8230 /* pfit ratios are autocomputed by the hw on gen4+ */
8231 if (INTEL_INFO(dev)->gen < 4)
8232 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8233 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8234 PIPE_CONF_CHECK_I(pch_pfit.pos);
8235 PIPE_CONF_CHECK_I(pch_pfit.size);
8236
8237 PIPE_CONF_CHECK_I(ips_enabled);
8238
8239 PIPE_CONF_CHECK_I(shared_dpll);
8240 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8241 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
8242 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8243 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
8244
8245 #undef PIPE_CONF_CHECK_X
8246 #undef PIPE_CONF_CHECK_I
8247 #undef PIPE_CONF_CHECK_FLAGS
8248 #undef PIPE_CONF_QUIRK
8249
8250 if (!IS_HASWELL(dev)) {
8251 if (!intel_fuzzy_clock_check(current_config, pipe_config)) {
8252 DRM_ERROR("mismatch in clock (expected %d, found %d)\n",
8253 current_config->adjusted_mode.clock,
8254 pipe_config->adjusted_mode.clock);
8255 return false;
8256 }
8257 }
8258
8259 return true;
8260 }
8261
8262 static void
8263 check_connector_state(struct drm_device *dev)
8264 {
8265 struct intel_connector *connector;
8266
8267 list_for_each_entry(connector, &dev->mode_config.connector_list,
8268 base.head) {
8269 /* This also checks the encoder/connector hw state with the
8270 * ->get_hw_state callbacks. */
8271 intel_connector_check_state(connector);
8272
8273 WARN(&connector->new_encoder->base != connector->base.encoder,
8274 "connector's staged encoder doesn't match current encoder\n");
8275 }
8276 }
8277
8278 static void
8279 check_encoder_state(struct drm_device *dev)
8280 {
8281 struct intel_encoder *encoder;
8282 struct intel_connector *connector;
8283
8284 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8285 base.head) {
8286 bool enabled = false;
8287 bool active = false;
8288 enum pipe pipe, tracked_pipe;
8289
8290 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8291 encoder->base.base.id,
8292 drm_get_encoder_name(&encoder->base));
8293
8294 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8295 "encoder's stage crtc doesn't match current crtc\n");
8296 WARN(encoder->connectors_active && !encoder->base.crtc,
8297 "encoder's active_connectors set, but no crtc\n");
8298
8299 list_for_each_entry(connector, &dev->mode_config.connector_list,
8300 base.head) {
8301 if (connector->base.encoder != &encoder->base)
8302 continue;
8303 enabled = true;
8304 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8305 active = true;
8306 }
8307 WARN(!!encoder->base.crtc != enabled,
8308 "encoder's enabled state mismatch "
8309 "(expected %i, found %i)\n",
8310 !!encoder->base.crtc, enabled);
8311 WARN(active && !encoder->base.crtc,
8312 "active encoder with no crtc\n");
8313
8314 WARN(encoder->connectors_active != active,
8315 "encoder's computed active state doesn't match tracked active state "
8316 "(expected %i, found %i)\n", active, encoder->connectors_active);
8317
8318 active = encoder->get_hw_state(encoder, &pipe);
8319 WARN(active != encoder->connectors_active,
8320 "encoder's hw state doesn't match sw tracking "
8321 "(expected %i, found %i)\n",
8322 encoder->connectors_active, active);
8323
8324 if (!encoder->base.crtc)
8325 continue;
8326
8327 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8328 WARN(active && pipe != tracked_pipe,
8329 "active encoder's pipe doesn't match"
8330 "(expected %i, found %i)\n",
8331 tracked_pipe, pipe);
8332
8333 }
8334 }
8335
8336 static void
8337 check_crtc_state(struct drm_device *dev)
8338 {
8339 drm_i915_private_t *dev_priv = dev->dev_private;
8340 struct intel_crtc *crtc;
8341 struct intel_encoder *encoder;
8342 struct intel_crtc_config pipe_config;
8343
8344 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8345 base.head) {
8346 bool enabled = false;
8347 bool active = false;
8348
8349 memset(&pipe_config, 0, sizeof(pipe_config));
8350
8351 DRM_DEBUG_KMS("[CRTC:%d]\n",
8352 crtc->base.base.id);
8353
8354 WARN(crtc->active && !crtc->base.enabled,
8355 "active crtc, but not enabled in sw tracking\n");
8356
8357 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8358 base.head) {
8359 if (encoder->base.crtc != &crtc->base)
8360 continue;
8361 enabled = true;
8362 if (encoder->connectors_active)
8363 active = true;
8364 }
8365
8366 WARN(active != crtc->active,
8367 "crtc's computed active state doesn't match tracked active state "
8368 "(expected %i, found %i)\n", active, crtc->active);
8369 WARN(enabled != crtc->base.enabled,
8370 "crtc's computed enabled state doesn't match tracked enabled state "
8371 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8372
8373 active = dev_priv->display.get_pipe_config(crtc,
8374 &pipe_config);
8375
8376 /* hw state is inconsistent with the pipe A quirk */
8377 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8378 active = crtc->active;
8379
8380 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8381 base.head) {
8382 if (encoder->base.crtc != &crtc->base)
8383 continue;
8384 if (encoder->get_config)
8385 encoder->get_config(encoder, &pipe_config);
8386 }
8387
8388 if (dev_priv->display.get_clock)
8389 dev_priv->display.get_clock(crtc, &pipe_config);
8390
8391 WARN(crtc->active != active,
8392 "crtc active state doesn't match with hw state "
8393 "(expected %i, found %i)\n", crtc->active, active);
8394
8395 if (active &&
8396 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8397 WARN(1, "pipe state doesn't match!\n");
8398 intel_dump_pipe_config(crtc, &pipe_config,
8399 "[hw state]");
8400 intel_dump_pipe_config(crtc, &crtc->config,
8401 "[sw state]");
8402 }
8403 }
8404 }
8405
8406 static void
8407 check_shared_dpll_state(struct drm_device *dev)
8408 {
8409 drm_i915_private_t *dev_priv = dev->dev_private;
8410 struct intel_crtc *crtc;
8411 struct intel_dpll_hw_state dpll_hw_state;
8412 int i;
8413
8414 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8415 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8416 int enabled_crtcs = 0, active_crtcs = 0;
8417 bool active;
8418
8419 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8420
8421 DRM_DEBUG_KMS("%s\n", pll->name);
8422
8423 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8424
8425 WARN(pll->active > pll->refcount,
8426 "more active pll users than references: %i vs %i\n",
8427 pll->active, pll->refcount);
8428 WARN(pll->active && !pll->on,
8429 "pll in active use but not on in sw tracking\n");
8430 WARN(pll->on != active,
8431 "pll on state mismatch (expected %i, found %i)\n",
8432 pll->on, active);
8433
8434 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8435 base.head) {
8436 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8437 enabled_crtcs++;
8438 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8439 active_crtcs++;
8440 }
8441 WARN(pll->active != active_crtcs,
8442 "pll active crtcs mismatch (expected %i, found %i)\n",
8443 pll->active, active_crtcs);
8444 WARN(pll->refcount != enabled_crtcs,
8445 "pll enabled crtcs mismatch (expected %i, found %i)\n",
8446 pll->refcount, enabled_crtcs);
8447
8448 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8449 sizeof(dpll_hw_state)),
8450 "pll hw state mismatch\n");
8451 }
8452 }
8453
8454 void
8455 intel_modeset_check_state(struct drm_device *dev)
8456 {
8457 check_connector_state(dev);
8458 check_encoder_state(dev);
8459 check_crtc_state(dev);
8460 check_shared_dpll_state(dev);
8461 }
8462
8463 static int __intel_set_mode(struct drm_crtc *crtc,
8464 struct drm_display_mode *mode,
8465 int x, int y, struct drm_framebuffer *fb)
8466 {
8467 struct drm_device *dev = crtc->dev;
8468 drm_i915_private_t *dev_priv = dev->dev_private;
8469 struct drm_display_mode *saved_mode, *saved_hwmode;
8470 struct intel_crtc_config *pipe_config = NULL;
8471 struct intel_crtc *intel_crtc;
8472 unsigned disable_pipes, prepare_pipes, modeset_pipes;
8473 int ret = 0;
8474
8475 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
8476 if (!saved_mode)
8477 return -ENOMEM;
8478 saved_hwmode = saved_mode + 1;
8479
8480 intel_modeset_affected_pipes(crtc, &modeset_pipes,
8481 &prepare_pipes, &disable_pipes);
8482
8483 *saved_hwmode = crtc->hwmode;
8484 *saved_mode = crtc->mode;
8485
8486 /* Hack: Because we don't (yet) support global modeset on multiple
8487 * crtcs, we don't keep track of the new mode for more than one crtc.
8488 * Hence simply check whether any bit is set in modeset_pipes in all the
8489 * pieces of code that are not yet converted to deal with mutliple crtcs
8490 * changing their mode at the same time. */
8491 if (modeset_pipes) {
8492 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8493 if (IS_ERR(pipe_config)) {
8494 ret = PTR_ERR(pipe_config);
8495 pipe_config = NULL;
8496
8497 goto out;
8498 }
8499 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8500 "[modeset]");
8501 }
8502
8503 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8504 intel_crtc_disable(&intel_crtc->base);
8505
8506 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8507 if (intel_crtc->base.enabled)
8508 dev_priv->display.crtc_disable(&intel_crtc->base);
8509 }
8510
8511 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8512 * to set it here already despite that we pass it down the callchain.
8513 */
8514 if (modeset_pipes) {
8515 crtc->mode = *mode;
8516 /* mode_set/enable/disable functions rely on a correct pipe
8517 * config. */
8518 to_intel_crtc(crtc)->config = *pipe_config;
8519 }
8520
8521 /* Only after disabling all output pipelines that will be changed can we
8522 * update the the output configuration. */
8523 intel_modeset_update_state(dev, prepare_pipes);
8524
8525 if (dev_priv->display.modeset_global_resources)
8526 dev_priv->display.modeset_global_resources(dev);
8527
8528 /* Set up the DPLL and any encoders state that needs to adjust or depend
8529 * on the DPLL.
8530 */
8531 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8532 ret = intel_crtc_mode_set(&intel_crtc->base,
8533 x, y, fb);
8534 if (ret)
8535 goto done;
8536 }
8537
8538 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8539 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8540 dev_priv->display.crtc_enable(&intel_crtc->base);
8541
8542 if (modeset_pipes) {
8543 /* Store real post-adjustment hardware mode. */
8544 crtc->hwmode = pipe_config->adjusted_mode;
8545
8546 /* Calculate and store various constants which
8547 * are later needed by vblank and swap-completion
8548 * timestamping. They are derived from true hwmode.
8549 */
8550 drm_calc_timestamping_constants(crtc);
8551 }
8552
8553 /* FIXME: add subpixel order */
8554 done:
8555 if (ret && crtc->enabled) {
8556 crtc->hwmode = *saved_hwmode;
8557 crtc->mode = *saved_mode;
8558 }
8559
8560 out:
8561 kfree(pipe_config);
8562 kfree(saved_mode);
8563 return ret;
8564 }
8565
8566 int intel_set_mode(struct drm_crtc *crtc,
8567 struct drm_display_mode *mode,
8568 int x, int y, struct drm_framebuffer *fb)
8569 {
8570 int ret;
8571
8572 ret = __intel_set_mode(crtc, mode, x, y, fb);
8573
8574 if (ret == 0)
8575 intel_modeset_check_state(crtc->dev);
8576
8577 return ret;
8578 }
8579
8580 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8581 {
8582 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8583 }
8584
8585 #undef for_each_intel_crtc_masked
8586
8587 static void intel_set_config_free(struct intel_set_config *config)
8588 {
8589 if (!config)
8590 return;
8591
8592 kfree(config->save_connector_encoders);
8593 kfree(config->save_encoder_crtcs);
8594 kfree(config);
8595 }
8596
8597 static int intel_set_config_save_state(struct drm_device *dev,
8598 struct intel_set_config *config)
8599 {
8600 struct drm_encoder *encoder;
8601 struct drm_connector *connector;
8602 int count;
8603
8604 config->save_encoder_crtcs =
8605 kcalloc(dev->mode_config.num_encoder,
8606 sizeof(struct drm_crtc *), GFP_KERNEL);
8607 if (!config->save_encoder_crtcs)
8608 return -ENOMEM;
8609
8610 config->save_connector_encoders =
8611 kcalloc(dev->mode_config.num_connector,
8612 sizeof(struct drm_encoder *), GFP_KERNEL);
8613 if (!config->save_connector_encoders)
8614 return -ENOMEM;
8615
8616 /* Copy data. Note that driver private data is not affected.
8617 * Should anything bad happen only the expected state is
8618 * restored, not the drivers personal bookkeeping.
8619 */
8620 count = 0;
8621 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8622 config->save_encoder_crtcs[count++] = encoder->crtc;
8623 }
8624
8625 count = 0;
8626 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8627 config->save_connector_encoders[count++] = connector->encoder;
8628 }
8629
8630 return 0;
8631 }
8632
8633 static void intel_set_config_restore_state(struct drm_device *dev,
8634 struct intel_set_config *config)
8635 {
8636 struct intel_encoder *encoder;
8637 struct intel_connector *connector;
8638 int count;
8639
8640 count = 0;
8641 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8642 encoder->new_crtc =
8643 to_intel_crtc(config->save_encoder_crtcs[count++]);
8644 }
8645
8646 count = 0;
8647 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8648 connector->new_encoder =
8649 to_intel_encoder(config->save_connector_encoders[count++]);
8650 }
8651 }
8652
8653 static bool
8654 is_crtc_connector_off(struct drm_crtc *crtc, struct drm_connector *connectors,
8655 int num_connectors)
8656 {
8657 int i;
8658
8659 for (i = 0; i < num_connectors; i++)
8660 if (connectors[i].encoder &&
8661 connectors[i].encoder->crtc == crtc &&
8662 connectors[i].dpms != DRM_MODE_DPMS_ON)
8663 return true;
8664
8665 return false;
8666 }
8667
8668 static void
8669 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8670 struct intel_set_config *config)
8671 {
8672
8673 /* We should be able to check here if the fb has the same properties
8674 * and then just flip_or_move it */
8675 if (set->connectors != NULL &&
8676 is_crtc_connector_off(set->crtc, *set->connectors,
8677 set->num_connectors)) {
8678 config->mode_changed = true;
8679 } else if (set->crtc->fb != set->fb) {
8680 /* If we have no fb then treat it as a full mode set */
8681 if (set->crtc->fb == NULL) {
8682 struct intel_crtc *intel_crtc =
8683 to_intel_crtc(set->crtc);
8684
8685 if (intel_crtc->active && i915_fastboot) {
8686 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
8687 config->fb_changed = true;
8688 } else {
8689 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
8690 config->mode_changed = true;
8691 }
8692 } else if (set->fb == NULL) {
8693 config->mode_changed = true;
8694 } else if (set->fb->pixel_format !=
8695 set->crtc->fb->pixel_format) {
8696 config->mode_changed = true;
8697 } else {
8698 config->fb_changed = true;
8699 }
8700 }
8701
8702 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8703 config->fb_changed = true;
8704
8705 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8706 DRM_DEBUG_KMS("modes are different, full mode set\n");
8707 drm_mode_debug_printmodeline(&set->crtc->mode);
8708 drm_mode_debug_printmodeline(set->mode);
8709 config->mode_changed = true;
8710 }
8711 }
8712
8713 static int
8714 intel_modeset_stage_output_state(struct drm_device *dev,
8715 struct drm_mode_set *set,
8716 struct intel_set_config *config)
8717 {
8718 struct drm_crtc *new_crtc;
8719 struct intel_connector *connector;
8720 struct intel_encoder *encoder;
8721 int count, ro;
8722
8723 /* The upper layers ensure that we either disable a crtc or have a list
8724 * of connectors. For paranoia, double-check this. */
8725 WARN_ON(!set->fb && (set->num_connectors != 0));
8726 WARN_ON(set->fb && (set->num_connectors == 0));
8727
8728 count = 0;
8729 list_for_each_entry(connector, &dev->mode_config.connector_list,
8730 base.head) {
8731 /* Otherwise traverse passed in connector list and get encoders
8732 * for them. */
8733 for (ro = 0; ro < set->num_connectors; ro++) {
8734 if (set->connectors[ro] == &connector->base) {
8735 connector->new_encoder = connector->encoder;
8736 break;
8737 }
8738 }
8739
8740 /* If we disable the crtc, disable all its connectors. Also, if
8741 * the connector is on the changing crtc but not on the new
8742 * connector list, disable it. */
8743 if ((!set->fb || ro == set->num_connectors) &&
8744 connector->base.encoder &&
8745 connector->base.encoder->crtc == set->crtc) {
8746 connector->new_encoder = NULL;
8747
8748 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8749 connector->base.base.id,
8750 drm_get_connector_name(&connector->base));
8751 }
8752
8753
8754 if (&connector->new_encoder->base != connector->base.encoder) {
8755 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8756 config->mode_changed = true;
8757 }
8758 }
8759 /* connector->new_encoder is now updated for all connectors. */
8760
8761 /* Update crtc of enabled connectors. */
8762 count = 0;
8763 list_for_each_entry(connector, &dev->mode_config.connector_list,
8764 base.head) {
8765 if (!connector->new_encoder)
8766 continue;
8767
8768 new_crtc = connector->new_encoder->base.crtc;
8769
8770 for (ro = 0; ro < set->num_connectors; ro++) {
8771 if (set->connectors[ro] == &connector->base)
8772 new_crtc = set->crtc;
8773 }
8774
8775 /* Make sure the new CRTC will work with the encoder */
8776 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8777 new_crtc)) {
8778 return -EINVAL;
8779 }
8780 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8781
8782 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8783 connector->base.base.id,
8784 drm_get_connector_name(&connector->base),
8785 new_crtc->base.id);
8786 }
8787
8788 /* Check for any encoders that needs to be disabled. */
8789 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8790 base.head) {
8791 list_for_each_entry(connector,
8792 &dev->mode_config.connector_list,
8793 base.head) {
8794 if (connector->new_encoder == encoder) {
8795 WARN_ON(!connector->new_encoder->new_crtc);
8796
8797 goto next_encoder;
8798 }
8799 }
8800 encoder->new_crtc = NULL;
8801 next_encoder:
8802 /* Only now check for crtc changes so we don't miss encoders
8803 * that will be disabled. */
8804 if (&encoder->new_crtc->base != encoder->base.crtc) {
8805 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8806 config->mode_changed = true;
8807 }
8808 }
8809 /* Now we've also updated encoder->new_crtc for all encoders. */
8810
8811 return 0;
8812 }
8813
8814 static int intel_crtc_set_config(struct drm_mode_set *set)
8815 {
8816 struct drm_device *dev;
8817 struct drm_mode_set save_set;
8818 struct intel_set_config *config;
8819 int ret;
8820
8821 BUG_ON(!set);
8822 BUG_ON(!set->crtc);
8823 BUG_ON(!set->crtc->helper_private);
8824
8825 /* Enforce sane interface api - has been abused by the fb helper. */
8826 BUG_ON(!set->mode && set->fb);
8827 BUG_ON(set->fb && set->num_connectors == 0);
8828
8829 if (set->fb) {
8830 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8831 set->crtc->base.id, set->fb->base.id,
8832 (int)set->num_connectors, set->x, set->y);
8833 } else {
8834 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8835 }
8836
8837 dev = set->crtc->dev;
8838
8839 ret = -ENOMEM;
8840 config = kzalloc(sizeof(*config), GFP_KERNEL);
8841 if (!config)
8842 goto out_config;
8843
8844 ret = intel_set_config_save_state(dev, config);
8845 if (ret)
8846 goto out_config;
8847
8848 save_set.crtc = set->crtc;
8849 save_set.mode = &set->crtc->mode;
8850 save_set.x = set->crtc->x;
8851 save_set.y = set->crtc->y;
8852 save_set.fb = set->crtc->fb;
8853
8854 /* Compute whether we need a full modeset, only an fb base update or no
8855 * change at all. In the future we might also check whether only the
8856 * mode changed, e.g. for LVDS where we only change the panel fitter in
8857 * such cases. */
8858 intel_set_config_compute_mode_changes(set, config);
8859
8860 ret = intel_modeset_stage_output_state(dev, set, config);
8861 if (ret)
8862 goto fail;
8863
8864 if (config->mode_changed) {
8865 ret = intel_set_mode(set->crtc, set->mode,
8866 set->x, set->y, set->fb);
8867 } else if (config->fb_changed) {
8868 intel_crtc_wait_for_pending_flips(set->crtc);
8869
8870 ret = intel_pipe_set_base(set->crtc,
8871 set->x, set->y, set->fb);
8872 }
8873
8874 if (ret) {
8875 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
8876 set->crtc->base.id, ret);
8877 fail:
8878 intel_set_config_restore_state(dev, config);
8879
8880 /* Try to restore the config */
8881 if (config->mode_changed &&
8882 intel_set_mode(save_set.crtc, save_set.mode,
8883 save_set.x, save_set.y, save_set.fb))
8884 DRM_ERROR("failed to restore config after modeset failure\n");
8885 }
8886
8887 out_config:
8888 intel_set_config_free(config);
8889 return ret;
8890 }
8891
8892 static const struct drm_crtc_funcs intel_crtc_funcs = {
8893 .cursor_set = intel_crtc_cursor_set,
8894 .cursor_move = intel_crtc_cursor_move,
8895 .gamma_set = intel_crtc_gamma_set,
8896 .set_config = intel_crtc_set_config,
8897 .destroy = intel_crtc_destroy,
8898 .page_flip = intel_crtc_page_flip,
8899 };
8900
8901 static void intel_cpu_pll_init(struct drm_device *dev)
8902 {
8903 if (HAS_DDI(dev))
8904 intel_ddi_pll_init(dev);
8905 }
8906
8907 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
8908 struct intel_shared_dpll *pll,
8909 struct intel_dpll_hw_state *hw_state)
8910 {
8911 uint32_t val;
8912
8913 val = I915_READ(PCH_DPLL(pll->id));
8914 hw_state->dpll = val;
8915 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
8916 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
8917
8918 return val & DPLL_VCO_ENABLE;
8919 }
8920
8921 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
8922 struct intel_shared_dpll *pll)
8923 {
8924 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
8925 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
8926 }
8927
8928 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
8929 struct intel_shared_dpll *pll)
8930 {
8931 /* PCH refclock must be enabled first */
8932 assert_pch_refclk_enabled(dev_priv);
8933
8934 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
8935
8936 /* Wait for the clocks to stabilize. */
8937 POSTING_READ(PCH_DPLL(pll->id));
8938 udelay(150);
8939
8940 /* The pixel multiplier can only be updated once the
8941 * DPLL is enabled and the clocks are stable.
8942 *
8943 * So write it again.
8944 */
8945 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
8946 POSTING_READ(PCH_DPLL(pll->id));
8947 udelay(200);
8948 }
8949
8950 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
8951 struct intel_shared_dpll *pll)
8952 {
8953 struct drm_device *dev = dev_priv->dev;
8954 struct intel_crtc *crtc;
8955
8956 /* Make sure no transcoder isn't still depending on us. */
8957 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
8958 if (intel_crtc_to_shared_dpll(crtc) == pll)
8959 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
8960 }
8961
8962 I915_WRITE(PCH_DPLL(pll->id), 0);
8963 POSTING_READ(PCH_DPLL(pll->id));
8964 udelay(200);
8965 }
8966
8967 static char *ibx_pch_dpll_names[] = {
8968 "PCH DPLL A",
8969 "PCH DPLL B",
8970 };
8971
8972 static void ibx_pch_dpll_init(struct drm_device *dev)
8973 {
8974 struct drm_i915_private *dev_priv = dev->dev_private;
8975 int i;
8976
8977 dev_priv->num_shared_dpll = 2;
8978
8979 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8980 dev_priv->shared_dplls[i].id = i;
8981 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
8982 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
8983 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
8984 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
8985 dev_priv->shared_dplls[i].get_hw_state =
8986 ibx_pch_dpll_get_hw_state;
8987 }
8988 }
8989
8990 static void intel_shared_dpll_init(struct drm_device *dev)
8991 {
8992 struct drm_i915_private *dev_priv = dev->dev_private;
8993
8994 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8995 ibx_pch_dpll_init(dev);
8996 else
8997 dev_priv->num_shared_dpll = 0;
8998
8999 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9000 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9001 dev_priv->num_shared_dpll);
9002 }
9003
9004 static void intel_crtc_init(struct drm_device *dev, int pipe)
9005 {
9006 drm_i915_private_t *dev_priv = dev->dev_private;
9007 struct intel_crtc *intel_crtc;
9008 int i;
9009
9010 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
9011 if (intel_crtc == NULL)
9012 return;
9013
9014 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9015
9016 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
9017 for (i = 0; i < 256; i++) {
9018 intel_crtc->lut_r[i] = i;
9019 intel_crtc->lut_g[i] = i;
9020 intel_crtc->lut_b[i] = i;
9021 }
9022
9023 /* Swap pipes & planes for FBC on pre-965 */
9024 intel_crtc->pipe = pipe;
9025 intel_crtc->plane = pipe;
9026 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
9027 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
9028 intel_crtc->plane = !pipe;
9029 }
9030
9031 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9032 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9033 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9034 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9035
9036 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
9037 }
9038
9039 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
9040 struct drm_file *file)
9041 {
9042 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
9043 struct drm_mode_object *drmmode_obj;
9044 struct intel_crtc *crtc;
9045
9046 if (!drm_core_check_feature(dev, DRIVER_MODESET))
9047 return -ENODEV;
9048
9049 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9050 DRM_MODE_OBJECT_CRTC);
9051
9052 if (!drmmode_obj) {
9053 DRM_ERROR("no such CRTC id\n");
9054 return -EINVAL;
9055 }
9056
9057 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9058 pipe_from_crtc_id->pipe = crtc->pipe;
9059
9060 return 0;
9061 }
9062
9063 static int intel_encoder_clones(struct intel_encoder *encoder)
9064 {
9065 struct drm_device *dev = encoder->base.dev;
9066 struct intel_encoder *source_encoder;
9067 int index_mask = 0;
9068 int entry = 0;
9069
9070 list_for_each_entry(source_encoder,
9071 &dev->mode_config.encoder_list, base.head) {
9072
9073 if (encoder == source_encoder)
9074 index_mask |= (1 << entry);
9075
9076 /* Intel hw has only one MUX where enocoders could be cloned. */
9077 if (encoder->cloneable && source_encoder->cloneable)
9078 index_mask |= (1 << entry);
9079
9080 entry++;
9081 }
9082
9083 return index_mask;
9084 }
9085
9086 static bool has_edp_a(struct drm_device *dev)
9087 {
9088 struct drm_i915_private *dev_priv = dev->dev_private;
9089
9090 if (!IS_MOBILE(dev))
9091 return false;
9092
9093 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9094 return false;
9095
9096 if (IS_GEN5(dev) &&
9097 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9098 return false;
9099
9100 return true;
9101 }
9102
9103 static void intel_setup_outputs(struct drm_device *dev)
9104 {
9105 struct drm_i915_private *dev_priv = dev->dev_private;
9106 struct intel_encoder *encoder;
9107 bool dpd_is_edp = false;
9108
9109 intel_lvds_init(dev);
9110
9111 if (!IS_ULT(dev))
9112 intel_crt_init(dev);
9113
9114 if (HAS_DDI(dev)) {
9115 int found;
9116
9117 /* Haswell uses DDI functions to detect digital outputs */
9118 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9119 /* DDI A only supports eDP */
9120 if (found)
9121 intel_ddi_init(dev, PORT_A);
9122
9123 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9124 * register */
9125 found = I915_READ(SFUSE_STRAP);
9126
9127 if (found & SFUSE_STRAP_DDIB_DETECTED)
9128 intel_ddi_init(dev, PORT_B);
9129 if (found & SFUSE_STRAP_DDIC_DETECTED)
9130 intel_ddi_init(dev, PORT_C);
9131 if (found & SFUSE_STRAP_DDID_DETECTED)
9132 intel_ddi_init(dev, PORT_D);
9133 } else if (HAS_PCH_SPLIT(dev)) {
9134 int found;
9135 dpd_is_edp = intel_dpd_is_edp(dev);
9136
9137 if (has_edp_a(dev))
9138 intel_dp_init(dev, DP_A, PORT_A);
9139
9140 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
9141 /* PCH SDVOB multiplex with HDMIB */
9142 found = intel_sdvo_init(dev, PCH_SDVOB, true);
9143 if (!found)
9144 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
9145 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
9146 intel_dp_init(dev, PCH_DP_B, PORT_B);
9147 }
9148
9149 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
9150 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
9151
9152 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
9153 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
9154
9155 if (I915_READ(PCH_DP_C) & DP_DETECTED)
9156 intel_dp_init(dev, PCH_DP_C, PORT_C);
9157
9158 if (I915_READ(PCH_DP_D) & DP_DETECTED)
9159 intel_dp_init(dev, PCH_DP_D, PORT_D);
9160 } else if (IS_VALLEYVIEW(dev)) {
9161 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9162 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9163 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
9164
9165 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
9166 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9167 PORT_B);
9168 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9169 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
9170 }
9171 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
9172 bool found = false;
9173
9174 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9175 DRM_DEBUG_KMS("probing SDVOB\n");
9176 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
9177 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9178 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9179 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
9180 }
9181
9182 if (!found && SUPPORTS_INTEGRATED_DP(dev))
9183 intel_dp_init(dev, DP_B, PORT_B);
9184 }
9185
9186 /* Before G4X SDVOC doesn't have its own detect register */
9187
9188 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9189 DRM_DEBUG_KMS("probing SDVOC\n");
9190 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
9191 }
9192
9193 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
9194
9195 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9196 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9197 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
9198 }
9199 if (SUPPORTS_INTEGRATED_DP(dev))
9200 intel_dp_init(dev, DP_C, PORT_C);
9201 }
9202
9203 if (SUPPORTS_INTEGRATED_DP(dev) &&
9204 (I915_READ(DP_D) & DP_DETECTED))
9205 intel_dp_init(dev, DP_D, PORT_D);
9206 } else if (IS_GEN2(dev))
9207 intel_dvo_init(dev);
9208
9209 if (SUPPORTS_TV(dev))
9210 intel_tv_init(dev);
9211
9212 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9213 encoder->base.possible_crtcs = encoder->crtc_mask;
9214 encoder->base.possible_clones =
9215 intel_encoder_clones(encoder);
9216 }
9217
9218 intel_init_pch_refclk(dev);
9219
9220 drm_helper_move_panel_connectors_to_head(dev);
9221 }
9222
9223 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9224 {
9225 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9226
9227 drm_framebuffer_cleanup(fb);
9228 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
9229
9230 kfree(intel_fb);
9231 }
9232
9233 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
9234 struct drm_file *file,
9235 unsigned int *handle)
9236 {
9237 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9238 struct drm_i915_gem_object *obj = intel_fb->obj;
9239
9240 return drm_gem_handle_create(file, &obj->base, handle);
9241 }
9242
9243 static const struct drm_framebuffer_funcs intel_fb_funcs = {
9244 .destroy = intel_user_framebuffer_destroy,
9245 .create_handle = intel_user_framebuffer_create_handle,
9246 };
9247
9248 int intel_framebuffer_init(struct drm_device *dev,
9249 struct intel_framebuffer *intel_fb,
9250 struct drm_mode_fb_cmd2 *mode_cmd,
9251 struct drm_i915_gem_object *obj)
9252 {
9253 int pitch_limit;
9254 int ret;
9255
9256 if (obj->tiling_mode == I915_TILING_Y) {
9257 DRM_DEBUG("hardware does not support tiling Y\n");
9258 return -EINVAL;
9259 }
9260
9261 if (mode_cmd->pitches[0] & 63) {
9262 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9263 mode_cmd->pitches[0]);
9264 return -EINVAL;
9265 }
9266
9267 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9268 pitch_limit = 32*1024;
9269 } else if (INTEL_INFO(dev)->gen >= 4) {
9270 if (obj->tiling_mode)
9271 pitch_limit = 16*1024;
9272 else
9273 pitch_limit = 32*1024;
9274 } else if (INTEL_INFO(dev)->gen >= 3) {
9275 if (obj->tiling_mode)
9276 pitch_limit = 8*1024;
9277 else
9278 pitch_limit = 16*1024;
9279 } else
9280 /* XXX DSPC is limited to 4k tiled */
9281 pitch_limit = 8*1024;
9282
9283 if (mode_cmd->pitches[0] > pitch_limit) {
9284 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9285 obj->tiling_mode ? "tiled" : "linear",
9286 mode_cmd->pitches[0], pitch_limit);
9287 return -EINVAL;
9288 }
9289
9290 if (obj->tiling_mode != I915_TILING_NONE &&
9291 mode_cmd->pitches[0] != obj->stride) {
9292 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9293 mode_cmd->pitches[0], obj->stride);
9294 return -EINVAL;
9295 }
9296
9297 /* Reject formats not supported by any plane early. */
9298 switch (mode_cmd->pixel_format) {
9299 case DRM_FORMAT_C8:
9300 case DRM_FORMAT_RGB565:
9301 case DRM_FORMAT_XRGB8888:
9302 case DRM_FORMAT_ARGB8888:
9303 break;
9304 case DRM_FORMAT_XRGB1555:
9305 case DRM_FORMAT_ARGB1555:
9306 if (INTEL_INFO(dev)->gen > 3) {
9307 DRM_DEBUG("unsupported pixel format: %s\n",
9308 drm_get_format_name(mode_cmd->pixel_format));
9309 return -EINVAL;
9310 }
9311 break;
9312 case DRM_FORMAT_XBGR8888:
9313 case DRM_FORMAT_ABGR8888:
9314 case DRM_FORMAT_XRGB2101010:
9315 case DRM_FORMAT_ARGB2101010:
9316 case DRM_FORMAT_XBGR2101010:
9317 case DRM_FORMAT_ABGR2101010:
9318 if (INTEL_INFO(dev)->gen < 4) {
9319 DRM_DEBUG("unsupported pixel format: %s\n",
9320 drm_get_format_name(mode_cmd->pixel_format));
9321 return -EINVAL;
9322 }
9323 break;
9324 case DRM_FORMAT_YUYV:
9325 case DRM_FORMAT_UYVY:
9326 case DRM_FORMAT_YVYU:
9327 case DRM_FORMAT_VYUY:
9328 if (INTEL_INFO(dev)->gen < 5) {
9329 DRM_DEBUG("unsupported pixel format: %s\n",
9330 drm_get_format_name(mode_cmd->pixel_format));
9331 return -EINVAL;
9332 }
9333 break;
9334 default:
9335 DRM_DEBUG("unsupported pixel format: %s\n",
9336 drm_get_format_name(mode_cmd->pixel_format));
9337 return -EINVAL;
9338 }
9339
9340 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9341 if (mode_cmd->offsets[0] != 0)
9342 return -EINVAL;
9343
9344 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9345 intel_fb->obj = obj;
9346
9347 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9348 if (ret) {
9349 DRM_ERROR("framebuffer init failed %d\n", ret);
9350 return ret;
9351 }
9352
9353 return 0;
9354 }
9355
9356 static struct drm_framebuffer *
9357 intel_user_framebuffer_create(struct drm_device *dev,
9358 struct drm_file *filp,
9359 struct drm_mode_fb_cmd2 *mode_cmd)
9360 {
9361 struct drm_i915_gem_object *obj;
9362
9363 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9364 mode_cmd->handles[0]));
9365 if (&obj->base == NULL)
9366 return ERR_PTR(-ENOENT);
9367
9368 return intel_framebuffer_create(dev, mode_cmd, obj);
9369 }
9370
9371 static const struct drm_mode_config_funcs intel_mode_funcs = {
9372 .fb_create = intel_user_framebuffer_create,
9373 .output_poll_changed = intel_fb_output_poll_changed,
9374 };
9375
9376 /* Set up chip specific display functions */
9377 static void intel_init_display(struct drm_device *dev)
9378 {
9379 struct drm_i915_private *dev_priv = dev->dev_private;
9380
9381 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9382 dev_priv->display.find_dpll = g4x_find_best_dpll;
9383 else if (IS_VALLEYVIEW(dev))
9384 dev_priv->display.find_dpll = vlv_find_best_dpll;
9385 else if (IS_PINEVIEW(dev))
9386 dev_priv->display.find_dpll = pnv_find_best_dpll;
9387 else
9388 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9389
9390 if (HAS_DDI(dev)) {
9391 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
9392 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
9393 dev_priv->display.crtc_enable = haswell_crtc_enable;
9394 dev_priv->display.crtc_disable = haswell_crtc_disable;
9395 dev_priv->display.off = haswell_crtc_off;
9396 dev_priv->display.update_plane = ironlake_update_plane;
9397 } else if (HAS_PCH_SPLIT(dev)) {
9398 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
9399 dev_priv->display.get_clock = ironlake_crtc_clock_get;
9400 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9401 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9402 dev_priv->display.crtc_disable = ironlake_crtc_disable;
9403 dev_priv->display.off = ironlake_crtc_off;
9404 dev_priv->display.update_plane = ironlake_update_plane;
9405 } else if (IS_VALLEYVIEW(dev)) {
9406 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9407 dev_priv->display.get_clock = i9xx_crtc_clock_get;
9408 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9409 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9410 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9411 dev_priv->display.off = i9xx_crtc_off;
9412 dev_priv->display.update_plane = i9xx_update_plane;
9413 } else {
9414 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9415 dev_priv->display.get_clock = i9xx_crtc_clock_get;
9416 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9417 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9418 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9419 dev_priv->display.off = i9xx_crtc_off;
9420 dev_priv->display.update_plane = i9xx_update_plane;
9421 }
9422
9423 /* Returns the core display clock speed */
9424 if (IS_VALLEYVIEW(dev))
9425 dev_priv->display.get_display_clock_speed =
9426 valleyview_get_display_clock_speed;
9427 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
9428 dev_priv->display.get_display_clock_speed =
9429 i945_get_display_clock_speed;
9430 else if (IS_I915G(dev))
9431 dev_priv->display.get_display_clock_speed =
9432 i915_get_display_clock_speed;
9433 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
9434 dev_priv->display.get_display_clock_speed =
9435 i9xx_misc_get_display_clock_speed;
9436 else if (IS_I915GM(dev))
9437 dev_priv->display.get_display_clock_speed =
9438 i915gm_get_display_clock_speed;
9439 else if (IS_I865G(dev))
9440 dev_priv->display.get_display_clock_speed =
9441 i865_get_display_clock_speed;
9442 else if (IS_I85X(dev))
9443 dev_priv->display.get_display_clock_speed =
9444 i855_get_display_clock_speed;
9445 else /* 852, 830 */
9446 dev_priv->display.get_display_clock_speed =
9447 i830_get_display_clock_speed;
9448
9449 if (HAS_PCH_SPLIT(dev)) {
9450 if (IS_GEN5(dev)) {
9451 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9452 dev_priv->display.write_eld = ironlake_write_eld;
9453 } else if (IS_GEN6(dev)) {
9454 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9455 dev_priv->display.write_eld = ironlake_write_eld;
9456 } else if (IS_IVYBRIDGE(dev)) {
9457 /* FIXME: detect B0+ stepping and use auto training */
9458 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9459 dev_priv->display.write_eld = ironlake_write_eld;
9460 dev_priv->display.modeset_global_resources =
9461 ivb_modeset_global_resources;
9462 } else if (IS_HASWELL(dev)) {
9463 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
9464 dev_priv->display.write_eld = haswell_write_eld;
9465 dev_priv->display.modeset_global_resources =
9466 haswell_modeset_global_resources;
9467 }
9468 } else if (IS_G4X(dev)) {
9469 dev_priv->display.write_eld = g4x_write_eld;
9470 }
9471
9472 /* Default just returns -ENODEV to indicate unsupported */
9473 dev_priv->display.queue_flip = intel_default_queue_flip;
9474
9475 switch (INTEL_INFO(dev)->gen) {
9476 case 2:
9477 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9478 break;
9479
9480 case 3:
9481 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9482 break;
9483
9484 case 4:
9485 case 5:
9486 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9487 break;
9488
9489 case 6:
9490 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9491 break;
9492 case 7:
9493 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9494 break;
9495 }
9496 }
9497
9498 /*
9499 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9500 * resume, or other times. This quirk makes sure that's the case for
9501 * affected systems.
9502 */
9503 static void quirk_pipea_force(struct drm_device *dev)
9504 {
9505 struct drm_i915_private *dev_priv = dev->dev_private;
9506
9507 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9508 DRM_INFO("applying pipe a force quirk\n");
9509 }
9510
9511 /*
9512 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9513 */
9514 static void quirk_ssc_force_disable(struct drm_device *dev)
9515 {
9516 struct drm_i915_private *dev_priv = dev->dev_private;
9517 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9518 DRM_INFO("applying lvds SSC disable quirk\n");
9519 }
9520
9521 /*
9522 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9523 * brightness value
9524 */
9525 static void quirk_invert_brightness(struct drm_device *dev)
9526 {
9527 struct drm_i915_private *dev_priv = dev->dev_private;
9528 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9529 DRM_INFO("applying inverted panel brightness quirk\n");
9530 }
9531
9532 struct intel_quirk {
9533 int device;
9534 int subsystem_vendor;
9535 int subsystem_device;
9536 void (*hook)(struct drm_device *dev);
9537 };
9538
9539 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9540 struct intel_dmi_quirk {
9541 void (*hook)(struct drm_device *dev);
9542 const struct dmi_system_id (*dmi_id_list)[];
9543 };
9544
9545 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9546 {
9547 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9548 return 1;
9549 }
9550
9551 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9552 {
9553 .dmi_id_list = &(const struct dmi_system_id[]) {
9554 {
9555 .callback = intel_dmi_reverse_brightness,
9556 .ident = "NCR Corporation",
9557 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9558 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9559 },
9560 },
9561 { } /* terminating entry */
9562 },
9563 .hook = quirk_invert_brightness,
9564 },
9565 };
9566
9567 static struct intel_quirk intel_quirks[] = {
9568 /* HP Mini needs pipe A force quirk (LP: #322104) */
9569 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9570
9571 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9572 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9573
9574 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9575 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9576
9577 /* 830/845 need to leave pipe A & dpll A up */
9578 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9579 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9580
9581 /* Lenovo U160 cannot use SSC on LVDS */
9582 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9583
9584 /* Sony Vaio Y cannot use SSC on LVDS */
9585 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9586
9587 /* Acer Aspire 5734Z must invert backlight brightness */
9588 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9589
9590 /* Acer/eMachines G725 */
9591 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
9592
9593 /* Acer/eMachines e725 */
9594 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
9595
9596 /* Acer/Packard Bell NCL20 */
9597 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
9598
9599 /* Acer Aspire 4736Z */
9600 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
9601 };
9602
9603 static void intel_init_quirks(struct drm_device *dev)
9604 {
9605 struct pci_dev *d = dev->pdev;
9606 int i;
9607
9608 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9609 struct intel_quirk *q = &intel_quirks[i];
9610
9611 if (d->device == q->device &&
9612 (d->subsystem_vendor == q->subsystem_vendor ||
9613 q->subsystem_vendor == PCI_ANY_ID) &&
9614 (d->subsystem_device == q->subsystem_device ||
9615 q->subsystem_device == PCI_ANY_ID))
9616 q->hook(dev);
9617 }
9618 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9619 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9620 intel_dmi_quirks[i].hook(dev);
9621 }
9622 }
9623
9624 /* Disable the VGA plane that we never use */
9625 static void i915_disable_vga(struct drm_device *dev)
9626 {
9627 struct drm_i915_private *dev_priv = dev->dev_private;
9628 u8 sr1;
9629 u32 vga_reg = i915_vgacntrl_reg(dev);
9630
9631 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9632 outb(SR01, VGA_SR_INDEX);
9633 sr1 = inb(VGA_SR_DATA);
9634 outb(sr1 | 1<<5, VGA_SR_DATA);
9635 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9636 udelay(300);
9637
9638 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9639 POSTING_READ(vga_reg);
9640 }
9641
9642 void intel_modeset_init_hw(struct drm_device *dev)
9643 {
9644 intel_init_power_well(dev);
9645
9646 intel_prepare_ddi(dev);
9647
9648 intel_init_clock_gating(dev);
9649
9650 mutex_lock(&dev->struct_mutex);
9651 intel_enable_gt_powersave(dev);
9652 mutex_unlock(&dev->struct_mutex);
9653 }
9654
9655 void intel_modeset_suspend_hw(struct drm_device *dev)
9656 {
9657 intel_suspend_hw(dev);
9658 }
9659
9660 void intel_modeset_init(struct drm_device *dev)
9661 {
9662 struct drm_i915_private *dev_priv = dev->dev_private;
9663 int i, j, ret;
9664
9665 drm_mode_config_init(dev);
9666
9667 dev->mode_config.min_width = 0;
9668 dev->mode_config.min_height = 0;
9669
9670 dev->mode_config.preferred_depth = 24;
9671 dev->mode_config.prefer_shadow = 1;
9672
9673 dev->mode_config.funcs = &intel_mode_funcs;
9674
9675 intel_init_quirks(dev);
9676
9677 intel_init_pm(dev);
9678
9679 if (INTEL_INFO(dev)->num_pipes == 0)
9680 return;
9681
9682 intel_init_display(dev);
9683
9684 if (IS_GEN2(dev)) {
9685 dev->mode_config.max_width = 2048;
9686 dev->mode_config.max_height = 2048;
9687 } else if (IS_GEN3(dev)) {
9688 dev->mode_config.max_width = 4096;
9689 dev->mode_config.max_height = 4096;
9690 } else {
9691 dev->mode_config.max_width = 8192;
9692 dev->mode_config.max_height = 8192;
9693 }
9694 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
9695
9696 DRM_DEBUG_KMS("%d display pipe%s available.\n",
9697 INTEL_INFO(dev)->num_pipes,
9698 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
9699
9700 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
9701 intel_crtc_init(dev, i);
9702 for (j = 0; j < dev_priv->num_plane; j++) {
9703 ret = intel_plane_init(dev, i, j);
9704 if (ret)
9705 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9706 pipe_name(i), sprite_name(i, j), ret);
9707 }
9708 }
9709
9710 intel_cpu_pll_init(dev);
9711 intel_shared_dpll_init(dev);
9712
9713 /* Just disable it once at startup */
9714 i915_disable_vga(dev);
9715 intel_setup_outputs(dev);
9716
9717 /* Just in case the BIOS is doing something questionable. */
9718 intel_disable_fbc(dev);
9719 }
9720
9721 static void
9722 intel_connector_break_all_links(struct intel_connector *connector)
9723 {
9724 connector->base.dpms = DRM_MODE_DPMS_OFF;
9725 connector->base.encoder = NULL;
9726 connector->encoder->connectors_active = false;
9727 connector->encoder->base.crtc = NULL;
9728 }
9729
9730 static void intel_enable_pipe_a(struct drm_device *dev)
9731 {
9732 struct intel_connector *connector;
9733 struct drm_connector *crt = NULL;
9734 struct intel_load_detect_pipe load_detect_temp;
9735
9736 /* We can't just switch on the pipe A, we need to set things up with a
9737 * proper mode and output configuration. As a gross hack, enable pipe A
9738 * by enabling the load detect pipe once. */
9739 list_for_each_entry(connector,
9740 &dev->mode_config.connector_list,
9741 base.head) {
9742 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9743 crt = &connector->base;
9744 break;
9745 }
9746 }
9747
9748 if (!crt)
9749 return;
9750
9751 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9752 intel_release_load_detect_pipe(crt, &load_detect_temp);
9753
9754
9755 }
9756
9757 static bool
9758 intel_check_plane_mapping(struct intel_crtc *crtc)
9759 {
9760 struct drm_device *dev = crtc->base.dev;
9761 struct drm_i915_private *dev_priv = dev->dev_private;
9762 u32 reg, val;
9763
9764 if (INTEL_INFO(dev)->num_pipes == 1)
9765 return true;
9766
9767 reg = DSPCNTR(!crtc->plane);
9768 val = I915_READ(reg);
9769
9770 if ((val & DISPLAY_PLANE_ENABLE) &&
9771 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9772 return false;
9773
9774 return true;
9775 }
9776
9777 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9778 {
9779 struct drm_device *dev = crtc->base.dev;
9780 struct drm_i915_private *dev_priv = dev->dev_private;
9781 u32 reg;
9782
9783 /* Clear any frame start delays used for debugging left by the BIOS */
9784 reg = PIPECONF(crtc->config.cpu_transcoder);
9785 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9786
9787 /* We need to sanitize the plane -> pipe mapping first because this will
9788 * disable the crtc (and hence change the state) if it is wrong. Note
9789 * that gen4+ has a fixed plane -> pipe mapping. */
9790 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9791 struct intel_connector *connector;
9792 bool plane;
9793
9794 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9795 crtc->base.base.id);
9796
9797 /* Pipe has the wrong plane attached and the plane is active.
9798 * Temporarily change the plane mapping and disable everything
9799 * ... */
9800 plane = crtc->plane;
9801 crtc->plane = !plane;
9802 dev_priv->display.crtc_disable(&crtc->base);
9803 crtc->plane = plane;
9804
9805 /* ... and break all links. */
9806 list_for_each_entry(connector, &dev->mode_config.connector_list,
9807 base.head) {
9808 if (connector->encoder->base.crtc != &crtc->base)
9809 continue;
9810
9811 intel_connector_break_all_links(connector);
9812 }
9813
9814 WARN_ON(crtc->active);
9815 crtc->base.enabled = false;
9816 }
9817
9818 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9819 crtc->pipe == PIPE_A && !crtc->active) {
9820 /* BIOS forgot to enable pipe A, this mostly happens after
9821 * resume. Force-enable the pipe to fix this, the update_dpms
9822 * call below we restore the pipe to the right state, but leave
9823 * the required bits on. */
9824 intel_enable_pipe_a(dev);
9825 }
9826
9827 /* Adjust the state of the output pipe according to whether we
9828 * have active connectors/encoders. */
9829 intel_crtc_update_dpms(&crtc->base);
9830
9831 if (crtc->active != crtc->base.enabled) {
9832 struct intel_encoder *encoder;
9833
9834 /* This can happen either due to bugs in the get_hw_state
9835 * functions or because the pipe is force-enabled due to the
9836 * pipe A quirk. */
9837 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9838 crtc->base.base.id,
9839 crtc->base.enabled ? "enabled" : "disabled",
9840 crtc->active ? "enabled" : "disabled");
9841
9842 crtc->base.enabled = crtc->active;
9843
9844 /* Because we only establish the connector -> encoder ->
9845 * crtc links if something is active, this means the
9846 * crtc is now deactivated. Break the links. connector
9847 * -> encoder links are only establish when things are
9848 * actually up, hence no need to break them. */
9849 WARN_ON(crtc->active);
9850
9851 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9852 WARN_ON(encoder->connectors_active);
9853 encoder->base.crtc = NULL;
9854 }
9855 }
9856 }
9857
9858 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9859 {
9860 struct intel_connector *connector;
9861 struct drm_device *dev = encoder->base.dev;
9862
9863 /* We need to check both for a crtc link (meaning that the
9864 * encoder is active and trying to read from a pipe) and the
9865 * pipe itself being active. */
9866 bool has_active_crtc = encoder->base.crtc &&
9867 to_intel_crtc(encoder->base.crtc)->active;
9868
9869 if (encoder->connectors_active && !has_active_crtc) {
9870 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9871 encoder->base.base.id,
9872 drm_get_encoder_name(&encoder->base));
9873
9874 /* Connector is active, but has no active pipe. This is
9875 * fallout from our resume register restoring. Disable
9876 * the encoder manually again. */
9877 if (encoder->base.crtc) {
9878 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9879 encoder->base.base.id,
9880 drm_get_encoder_name(&encoder->base));
9881 encoder->disable(encoder);
9882 }
9883
9884 /* Inconsistent output/port/pipe state happens presumably due to
9885 * a bug in one of the get_hw_state functions. Or someplace else
9886 * in our code, like the register restore mess on resume. Clamp
9887 * things to off as a safer default. */
9888 list_for_each_entry(connector,
9889 &dev->mode_config.connector_list,
9890 base.head) {
9891 if (connector->encoder != encoder)
9892 continue;
9893
9894 intel_connector_break_all_links(connector);
9895 }
9896 }
9897 /* Enabled encoders without active connectors will be fixed in
9898 * the crtc fixup. */
9899 }
9900
9901 void i915_redisable_vga(struct drm_device *dev)
9902 {
9903 struct drm_i915_private *dev_priv = dev->dev_private;
9904 u32 vga_reg = i915_vgacntrl_reg(dev);
9905
9906 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9907 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9908 i915_disable_vga(dev);
9909 }
9910 }
9911
9912 static void intel_modeset_readout_hw_state(struct drm_device *dev)
9913 {
9914 struct drm_i915_private *dev_priv = dev->dev_private;
9915 enum pipe pipe;
9916 struct intel_crtc *crtc;
9917 struct intel_encoder *encoder;
9918 struct intel_connector *connector;
9919 int i;
9920
9921 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9922 base.head) {
9923 memset(&crtc->config, 0, sizeof(crtc->config));
9924
9925 crtc->active = dev_priv->display.get_pipe_config(crtc,
9926 &crtc->config);
9927
9928 crtc->base.enabled = crtc->active;
9929
9930 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9931 crtc->base.base.id,
9932 crtc->active ? "enabled" : "disabled");
9933 }
9934
9935 /* FIXME: Smash this into the new shared dpll infrastructure. */
9936 if (HAS_DDI(dev))
9937 intel_ddi_setup_hw_pll_state(dev);
9938
9939 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9940 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9941
9942 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
9943 pll->active = 0;
9944 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9945 base.head) {
9946 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9947 pll->active++;
9948 }
9949 pll->refcount = pll->active;
9950
9951 DRM_DEBUG_KMS("%s hw state readout: refcount %i\n",
9952 pll->name, pll->refcount);
9953 }
9954
9955 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9956 base.head) {
9957 pipe = 0;
9958
9959 if (encoder->get_hw_state(encoder, &pipe)) {
9960 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9961 encoder->base.crtc = &crtc->base;
9962 if (encoder->get_config)
9963 encoder->get_config(encoder, &crtc->config);
9964 } else {
9965 encoder->base.crtc = NULL;
9966 }
9967
9968 encoder->connectors_active = false;
9969 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9970 encoder->base.base.id,
9971 drm_get_encoder_name(&encoder->base),
9972 encoder->base.crtc ? "enabled" : "disabled",
9973 pipe);
9974 }
9975
9976 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9977 base.head) {
9978 if (!crtc->active)
9979 continue;
9980 if (dev_priv->display.get_clock)
9981 dev_priv->display.get_clock(crtc,
9982 &crtc->config);
9983 }
9984
9985 list_for_each_entry(connector, &dev->mode_config.connector_list,
9986 base.head) {
9987 if (connector->get_hw_state(connector)) {
9988 connector->base.dpms = DRM_MODE_DPMS_ON;
9989 connector->encoder->connectors_active = true;
9990 connector->base.encoder = &connector->encoder->base;
9991 } else {
9992 connector->base.dpms = DRM_MODE_DPMS_OFF;
9993 connector->base.encoder = NULL;
9994 }
9995 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9996 connector->base.base.id,
9997 drm_get_connector_name(&connector->base),
9998 connector->base.encoder ? "enabled" : "disabled");
9999 }
10000 }
10001
10002 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10003 * and i915 state tracking structures. */
10004 void intel_modeset_setup_hw_state(struct drm_device *dev,
10005 bool force_restore)
10006 {
10007 struct drm_i915_private *dev_priv = dev->dev_private;
10008 enum pipe pipe;
10009 struct drm_plane *plane;
10010 struct intel_crtc *crtc;
10011 struct intel_encoder *encoder;
10012
10013 intel_modeset_readout_hw_state(dev);
10014
10015 /*
10016 * Now that we have the config, copy it to each CRTC struct
10017 * Note that this could go away if we move to using crtc_config
10018 * checking everywhere.
10019 */
10020 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10021 base.head) {
10022 if (crtc->active && i915_fastboot) {
10023 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10024
10025 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10026 crtc->base.base.id);
10027 drm_mode_debug_printmodeline(&crtc->base.mode);
10028 }
10029 }
10030
10031 /* HW state is read out, now we need to sanitize this mess. */
10032 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10033 base.head) {
10034 intel_sanitize_encoder(encoder);
10035 }
10036
10037 for_each_pipe(pipe) {
10038 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10039 intel_sanitize_crtc(crtc);
10040 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
10041 }
10042
10043 if (force_restore) {
10044 /*
10045 * We need to use raw interfaces for restoring state to avoid
10046 * checking (bogus) intermediate states.
10047 */
10048 for_each_pipe(pipe) {
10049 struct drm_crtc *crtc =
10050 dev_priv->pipe_to_crtc_mapping[pipe];
10051
10052 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10053 crtc->fb);
10054 }
10055 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
10056 intel_plane_restore(plane);
10057
10058 i915_redisable_vga(dev);
10059 } else {
10060 intel_modeset_update_staged_output_state(dev);
10061 }
10062
10063 intel_modeset_check_state(dev);
10064
10065 drm_mode_config_reset(dev);
10066 }
10067
10068 void intel_modeset_gem_init(struct drm_device *dev)
10069 {
10070 intel_modeset_init_hw(dev);
10071
10072 intel_setup_overlay(dev);
10073
10074 intel_modeset_setup_hw_state(dev, false);
10075 }
10076
10077 void intel_modeset_cleanup(struct drm_device *dev)
10078 {
10079 struct drm_i915_private *dev_priv = dev->dev_private;
10080 struct drm_crtc *crtc;
10081 struct intel_crtc *intel_crtc;
10082
10083 /*
10084 * Interrupts and polling as the first thing to avoid creating havoc.
10085 * Too much stuff here (turning of rps, connectors, ...) would
10086 * experience fancy races otherwise.
10087 */
10088 drm_irq_uninstall(dev);
10089 cancel_work_sync(&dev_priv->hotplug_work);
10090 /*
10091 * Due to the hpd irq storm handling the hotplug work can re-arm the
10092 * poll handlers. Hence disable polling after hpd handling is shut down.
10093 */
10094 drm_kms_helper_poll_fini(dev);
10095
10096 mutex_lock(&dev->struct_mutex);
10097
10098 intel_unregister_dsm_handler();
10099
10100 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10101 /* Skip inactive CRTCs */
10102 if (!crtc->fb)
10103 continue;
10104
10105 intel_crtc = to_intel_crtc(crtc);
10106 intel_increase_pllclock(crtc);
10107 }
10108
10109 intel_disable_fbc(dev);
10110
10111 intel_disable_gt_powersave(dev);
10112
10113 ironlake_teardown_rc6(dev);
10114
10115 mutex_unlock(&dev->struct_mutex);
10116
10117 /* flush any delayed tasks or pending work */
10118 flush_scheduled_work();
10119
10120 /* destroy backlight, if any, before the connectors */
10121 intel_panel_destroy_backlight(dev);
10122
10123 drm_mode_config_cleanup(dev);
10124
10125 intel_cleanup_overlay(dev);
10126 }
10127
10128 /*
10129 * Return which encoder is currently attached for connector.
10130 */
10131 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
10132 {
10133 return &intel_attached_encoder(connector)->base;
10134 }
10135
10136 void intel_connector_attach_encoder(struct intel_connector *connector,
10137 struct intel_encoder *encoder)
10138 {
10139 connector->encoder = encoder;
10140 drm_mode_connector_attach_encoder(&connector->base,
10141 &encoder->base);
10142 }
10143
10144 /*
10145 * set vga decode state - true == enable VGA decode
10146 */
10147 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10148 {
10149 struct drm_i915_private *dev_priv = dev->dev_private;
10150 u16 gmch_ctrl;
10151
10152 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10153 if (state)
10154 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10155 else
10156 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10157 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10158 return 0;
10159 }
10160
10161 #ifdef CONFIG_DEBUG_FS
10162 #include <linux/seq_file.h>
10163
10164 struct intel_display_error_state {
10165
10166 u32 power_well_driver;
10167
10168 struct intel_cursor_error_state {
10169 u32 control;
10170 u32 position;
10171 u32 base;
10172 u32 size;
10173 } cursor[I915_MAX_PIPES];
10174
10175 struct intel_pipe_error_state {
10176 enum transcoder cpu_transcoder;
10177 u32 conf;
10178 u32 source;
10179
10180 u32 htotal;
10181 u32 hblank;
10182 u32 hsync;
10183 u32 vtotal;
10184 u32 vblank;
10185 u32 vsync;
10186 } pipe[I915_MAX_PIPES];
10187
10188 struct intel_plane_error_state {
10189 u32 control;
10190 u32 stride;
10191 u32 size;
10192 u32 pos;
10193 u32 addr;
10194 u32 surface;
10195 u32 tile_offset;
10196 } plane[I915_MAX_PIPES];
10197 };
10198
10199 struct intel_display_error_state *
10200 intel_display_capture_error_state(struct drm_device *dev)
10201 {
10202 drm_i915_private_t *dev_priv = dev->dev_private;
10203 struct intel_display_error_state *error;
10204 enum transcoder cpu_transcoder;
10205 int i;
10206
10207 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10208 if (error == NULL)
10209 return NULL;
10210
10211 if (HAS_POWER_WELL(dev))
10212 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10213
10214 for_each_pipe(i) {
10215 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
10216 error->pipe[i].cpu_transcoder = cpu_transcoder;
10217
10218 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10219 error->cursor[i].control = I915_READ(CURCNTR(i));
10220 error->cursor[i].position = I915_READ(CURPOS(i));
10221 error->cursor[i].base = I915_READ(CURBASE(i));
10222 } else {
10223 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10224 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10225 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10226 }
10227
10228 error->plane[i].control = I915_READ(DSPCNTR(i));
10229 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
10230 if (INTEL_INFO(dev)->gen <= 3) {
10231 error->plane[i].size = I915_READ(DSPSIZE(i));
10232 error->plane[i].pos = I915_READ(DSPPOS(i));
10233 }
10234 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10235 error->plane[i].addr = I915_READ(DSPADDR(i));
10236 if (INTEL_INFO(dev)->gen >= 4) {
10237 error->plane[i].surface = I915_READ(DSPSURF(i));
10238 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10239 }
10240
10241 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10242 error->pipe[i].source = I915_READ(PIPESRC(i));
10243 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10244 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10245 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10246 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10247 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10248 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
10249 }
10250
10251 /* In the code above we read the registers without checking if the power
10252 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10253 * prevent the next I915_WRITE from detecting it and printing an error
10254 * message. */
10255 if (HAS_POWER_WELL(dev))
10256 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
10257
10258 return error;
10259 }
10260
10261 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10262
10263 void
10264 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
10265 struct drm_device *dev,
10266 struct intel_display_error_state *error)
10267 {
10268 int i;
10269
10270 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
10271 if (HAS_POWER_WELL(dev))
10272 err_printf(m, "PWR_WELL_CTL2: %08x\n",
10273 error->power_well_driver);
10274 for_each_pipe(i) {
10275 err_printf(m, "Pipe [%d]:\n", i);
10276 err_printf(m, " CPU transcoder: %c\n",
10277 transcoder_name(error->pipe[i].cpu_transcoder));
10278 err_printf(m, " CONF: %08x\n", error->pipe[i].conf);
10279 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
10280 err_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
10281 err_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
10282 err_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
10283 err_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
10284 err_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
10285 err_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
10286
10287 err_printf(m, "Plane [%d]:\n", i);
10288 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
10289 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
10290 if (INTEL_INFO(dev)->gen <= 3) {
10291 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
10292 err_printf(m, " POS: %08x\n", error->plane[i].pos);
10293 }
10294 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10295 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
10296 if (INTEL_INFO(dev)->gen >= 4) {
10297 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
10298 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
10299 }
10300
10301 err_printf(m, "Cursor [%d]:\n", i);
10302 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
10303 err_printf(m, " POS: %08x\n", error->cursor[i].position);
10304 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
10305 }
10306 }
10307 #endif
Linux kernel - Deliverables
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