2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
39 #include "i915_trace.h"
40 #include "drm_dp_helper.h"
41 #include "drm_crtc_helper.h"
42 #include <linux/dma_remapping.h>
44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
46 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
);
47 static void intel_increase_pllclock(struct drm_crtc
*crtc
);
48 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
71 #define INTEL_P2_NUM 2
72 typedef struct intel_limit intel_limit_t
;
74 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
76 bool (* find_pll
)(const intel_limit_t
*, struct drm_crtc
*,
77 int, int, intel_clock_t
*, intel_clock_t
*);
81 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
84 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
85 int target
, int refclk
, intel_clock_t
*match_clock
,
86 intel_clock_t
*best_clock
);
88 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
89 int target
, int refclk
, intel_clock_t
*match_clock
,
90 intel_clock_t
*best_clock
);
93 intel_find_pll_g4x_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
94 int target
, int refclk
, intel_clock_t
*match_clock
,
95 intel_clock_t
*best_clock
);
97 intel_find_pll_ironlake_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
98 int target
, int refclk
, intel_clock_t
*match_clock
,
99 intel_clock_t
*best_clock
);
101 static inline u32
/* units of 100MHz */
102 intel_fdi_link_freq(struct drm_device
*dev
)
105 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
106 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
111 static const intel_limit_t intel_limits_i8xx_dvo
= {
112 .dot
= { .min
= 25000, .max
= 350000 },
113 .vco
= { .min
= 930000, .max
= 1400000 },
114 .n
= { .min
= 3, .max
= 16 },
115 .m
= { .min
= 96, .max
= 140 },
116 .m1
= { .min
= 18, .max
= 26 },
117 .m2
= { .min
= 6, .max
= 16 },
118 .p
= { .min
= 4, .max
= 128 },
119 .p1
= { .min
= 2, .max
= 33 },
120 .p2
= { .dot_limit
= 165000,
121 .p2_slow
= 4, .p2_fast
= 2 },
122 .find_pll
= intel_find_best_PLL
,
125 static const intel_limit_t intel_limits_i8xx_lvds
= {
126 .dot
= { .min
= 25000, .max
= 350000 },
127 .vco
= { .min
= 930000, .max
= 1400000 },
128 .n
= { .min
= 3, .max
= 16 },
129 .m
= { .min
= 96, .max
= 140 },
130 .m1
= { .min
= 18, .max
= 26 },
131 .m2
= { .min
= 6, .max
= 16 },
132 .p
= { .min
= 4, .max
= 128 },
133 .p1
= { .min
= 1, .max
= 6 },
134 .p2
= { .dot_limit
= 165000,
135 .p2_slow
= 14, .p2_fast
= 7 },
136 .find_pll
= intel_find_best_PLL
,
139 static const intel_limit_t intel_limits_i9xx_sdvo
= {
140 .dot
= { .min
= 20000, .max
= 400000 },
141 .vco
= { .min
= 1400000, .max
= 2800000 },
142 .n
= { .min
= 1, .max
= 6 },
143 .m
= { .min
= 70, .max
= 120 },
144 .m1
= { .min
= 10, .max
= 22 },
145 .m2
= { .min
= 5, .max
= 9 },
146 .p
= { .min
= 5, .max
= 80 },
147 .p1
= { .min
= 1, .max
= 8 },
148 .p2
= { .dot_limit
= 200000,
149 .p2_slow
= 10, .p2_fast
= 5 },
150 .find_pll
= intel_find_best_PLL
,
153 static const intel_limit_t intel_limits_i9xx_lvds
= {
154 .dot
= { .min
= 20000, .max
= 400000 },
155 .vco
= { .min
= 1400000, .max
= 2800000 },
156 .n
= { .min
= 1, .max
= 6 },
157 .m
= { .min
= 70, .max
= 120 },
158 .m1
= { .min
= 10, .max
= 22 },
159 .m2
= { .min
= 5, .max
= 9 },
160 .p
= { .min
= 7, .max
= 98 },
161 .p1
= { .min
= 1, .max
= 8 },
162 .p2
= { .dot_limit
= 112000,
163 .p2_slow
= 14, .p2_fast
= 7 },
164 .find_pll
= intel_find_best_PLL
,
168 static const intel_limit_t intel_limits_g4x_sdvo
= {
169 .dot
= { .min
= 25000, .max
= 270000 },
170 .vco
= { .min
= 1750000, .max
= 3500000},
171 .n
= { .min
= 1, .max
= 4 },
172 .m
= { .min
= 104, .max
= 138 },
173 .m1
= { .min
= 17, .max
= 23 },
174 .m2
= { .min
= 5, .max
= 11 },
175 .p
= { .min
= 10, .max
= 30 },
176 .p1
= { .min
= 1, .max
= 3},
177 .p2
= { .dot_limit
= 270000,
181 .find_pll
= intel_g4x_find_best_PLL
,
184 static const intel_limit_t intel_limits_g4x_hdmi
= {
185 .dot
= { .min
= 22000, .max
= 400000 },
186 .vco
= { .min
= 1750000, .max
= 3500000},
187 .n
= { .min
= 1, .max
= 4 },
188 .m
= { .min
= 104, .max
= 138 },
189 .m1
= { .min
= 16, .max
= 23 },
190 .m2
= { .min
= 5, .max
= 11 },
191 .p
= { .min
= 5, .max
= 80 },
192 .p1
= { .min
= 1, .max
= 8},
193 .p2
= { .dot_limit
= 165000,
194 .p2_slow
= 10, .p2_fast
= 5 },
195 .find_pll
= intel_g4x_find_best_PLL
,
198 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
199 .dot
= { .min
= 20000, .max
= 115000 },
200 .vco
= { .min
= 1750000, .max
= 3500000 },
201 .n
= { .min
= 1, .max
= 3 },
202 .m
= { .min
= 104, .max
= 138 },
203 .m1
= { .min
= 17, .max
= 23 },
204 .m2
= { .min
= 5, .max
= 11 },
205 .p
= { .min
= 28, .max
= 112 },
206 .p1
= { .min
= 2, .max
= 8 },
207 .p2
= { .dot_limit
= 0,
208 .p2_slow
= 14, .p2_fast
= 14
210 .find_pll
= intel_g4x_find_best_PLL
,
213 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
214 .dot
= { .min
= 80000, .max
= 224000 },
215 .vco
= { .min
= 1750000, .max
= 3500000 },
216 .n
= { .min
= 1, .max
= 3 },
217 .m
= { .min
= 104, .max
= 138 },
218 .m1
= { .min
= 17, .max
= 23 },
219 .m2
= { .min
= 5, .max
= 11 },
220 .p
= { .min
= 14, .max
= 42 },
221 .p1
= { .min
= 2, .max
= 6 },
222 .p2
= { .dot_limit
= 0,
223 .p2_slow
= 7, .p2_fast
= 7
225 .find_pll
= intel_g4x_find_best_PLL
,
228 static const intel_limit_t intel_limits_g4x_display_port
= {
229 .dot
= { .min
= 161670, .max
= 227000 },
230 .vco
= { .min
= 1750000, .max
= 3500000},
231 .n
= { .min
= 1, .max
= 2 },
232 .m
= { .min
= 97, .max
= 108 },
233 .m1
= { .min
= 0x10, .max
= 0x12 },
234 .m2
= { .min
= 0x05, .max
= 0x06 },
235 .p
= { .min
= 10, .max
= 20 },
236 .p1
= { .min
= 1, .max
= 2},
237 .p2
= { .dot_limit
= 0,
238 .p2_slow
= 10, .p2_fast
= 10 },
239 .find_pll
= intel_find_pll_g4x_dp
,
242 static const intel_limit_t intel_limits_pineview_sdvo
= {
243 .dot
= { .min
= 20000, .max
= 400000},
244 .vco
= { .min
= 1700000, .max
= 3500000 },
245 /* Pineview's Ncounter is a ring counter */
246 .n
= { .min
= 3, .max
= 6 },
247 .m
= { .min
= 2, .max
= 256 },
248 /* Pineview only has one combined m divider, which we treat as m2. */
249 .m1
= { .min
= 0, .max
= 0 },
250 .m2
= { .min
= 0, .max
= 254 },
251 .p
= { .min
= 5, .max
= 80 },
252 .p1
= { .min
= 1, .max
= 8 },
253 .p2
= { .dot_limit
= 200000,
254 .p2_slow
= 10, .p2_fast
= 5 },
255 .find_pll
= intel_find_best_PLL
,
258 static const intel_limit_t intel_limits_pineview_lvds
= {
259 .dot
= { .min
= 20000, .max
= 400000 },
260 .vco
= { .min
= 1700000, .max
= 3500000 },
261 .n
= { .min
= 3, .max
= 6 },
262 .m
= { .min
= 2, .max
= 256 },
263 .m1
= { .min
= 0, .max
= 0 },
264 .m2
= { .min
= 0, .max
= 254 },
265 .p
= { .min
= 7, .max
= 112 },
266 .p1
= { .min
= 1, .max
= 8 },
267 .p2
= { .dot_limit
= 112000,
268 .p2_slow
= 14, .p2_fast
= 14 },
269 .find_pll
= intel_find_best_PLL
,
272 /* Ironlake / Sandybridge
274 * We calculate clock using (register_value + 2) for N/M1/M2, so here
275 * the range value for them is (actual_value - 2).
277 static const intel_limit_t intel_limits_ironlake_dac
= {
278 .dot
= { .min
= 25000, .max
= 350000 },
279 .vco
= { .min
= 1760000, .max
= 3510000 },
280 .n
= { .min
= 1, .max
= 5 },
281 .m
= { .min
= 79, .max
= 127 },
282 .m1
= { .min
= 12, .max
= 22 },
283 .m2
= { .min
= 5, .max
= 9 },
284 .p
= { .min
= 5, .max
= 80 },
285 .p1
= { .min
= 1, .max
= 8 },
286 .p2
= { .dot_limit
= 225000,
287 .p2_slow
= 10, .p2_fast
= 5 },
288 .find_pll
= intel_g4x_find_best_PLL
,
291 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
292 .dot
= { .min
= 25000, .max
= 350000 },
293 .vco
= { .min
= 1760000, .max
= 3510000 },
294 .n
= { .min
= 1, .max
= 3 },
295 .m
= { .min
= 79, .max
= 118 },
296 .m1
= { .min
= 12, .max
= 22 },
297 .m2
= { .min
= 5, .max
= 9 },
298 .p
= { .min
= 28, .max
= 112 },
299 .p1
= { .min
= 2, .max
= 8 },
300 .p2
= { .dot_limit
= 225000,
301 .p2_slow
= 14, .p2_fast
= 14 },
302 .find_pll
= intel_g4x_find_best_PLL
,
305 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
306 .dot
= { .min
= 25000, .max
= 350000 },
307 .vco
= { .min
= 1760000, .max
= 3510000 },
308 .n
= { .min
= 1, .max
= 3 },
309 .m
= { .min
= 79, .max
= 127 },
310 .m1
= { .min
= 12, .max
= 22 },
311 .m2
= { .min
= 5, .max
= 9 },
312 .p
= { .min
= 14, .max
= 56 },
313 .p1
= { .min
= 2, .max
= 8 },
314 .p2
= { .dot_limit
= 225000,
315 .p2_slow
= 7, .p2_fast
= 7 },
316 .find_pll
= intel_g4x_find_best_PLL
,
319 /* LVDS 100mhz refclk limits. */
320 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
321 .dot
= { .min
= 25000, .max
= 350000 },
322 .vco
= { .min
= 1760000, .max
= 3510000 },
323 .n
= { .min
= 1, .max
= 2 },
324 .m
= { .min
= 79, .max
= 126 },
325 .m1
= { .min
= 12, .max
= 22 },
326 .m2
= { .min
= 5, .max
= 9 },
327 .p
= { .min
= 28, .max
= 112 },
328 .p1
= { .min
= 2, .max
= 8 },
329 .p2
= { .dot_limit
= 225000,
330 .p2_slow
= 14, .p2_fast
= 14 },
331 .find_pll
= intel_g4x_find_best_PLL
,
334 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
335 .dot
= { .min
= 25000, .max
= 350000 },
336 .vco
= { .min
= 1760000, .max
= 3510000 },
337 .n
= { .min
= 1, .max
= 3 },
338 .m
= { .min
= 79, .max
= 126 },
339 .m1
= { .min
= 12, .max
= 22 },
340 .m2
= { .min
= 5, .max
= 9 },
341 .p
= { .min
= 14, .max
= 42 },
342 .p1
= { .min
= 2, .max
= 6 },
343 .p2
= { .dot_limit
= 225000,
344 .p2_slow
= 7, .p2_fast
= 7 },
345 .find_pll
= intel_g4x_find_best_PLL
,
348 static const intel_limit_t intel_limits_ironlake_display_port
= {
349 .dot
= { .min
= 25000, .max
= 350000 },
350 .vco
= { .min
= 1760000, .max
= 3510000},
351 .n
= { .min
= 1, .max
= 2 },
352 .m
= { .min
= 81, .max
= 90 },
353 .m1
= { .min
= 12, .max
= 22 },
354 .m2
= { .min
= 5, .max
= 9 },
355 .p
= { .min
= 10, .max
= 20 },
356 .p1
= { .min
= 1, .max
= 2},
357 .p2
= { .dot_limit
= 0,
358 .p2_slow
= 10, .p2_fast
= 10 },
359 .find_pll
= intel_find_pll_ironlake_dp
,
362 u32
intel_dpio_read(struct drm_i915_private
*dev_priv
, int reg
)
367 spin_lock_irqsave(&dev_priv
->dpio_lock
, flags
);
368 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
369 DRM_ERROR("DPIO idle wait timed out\n");
373 I915_WRITE(DPIO_REG
, reg
);
374 I915_WRITE(DPIO_PKT
, DPIO_RID
| DPIO_OP_READ
| DPIO_PORTID
|
376 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
377 DRM_ERROR("DPIO read wait timed out\n");
380 val
= I915_READ(DPIO_DATA
);
383 spin_unlock_irqrestore(&dev_priv
->dpio_lock
, flags
);
387 static void vlv_init_dpio(struct drm_device
*dev
)
389 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
391 /* Reset the DPIO config */
392 I915_WRITE(DPIO_CTL
, 0);
393 POSTING_READ(DPIO_CTL
);
394 I915_WRITE(DPIO_CTL
, 1);
395 POSTING_READ(DPIO_CTL
);
398 static int intel_dual_link_lvds_callback(const struct dmi_system_id
*id
)
400 DRM_INFO("Forcing lvds to dual link mode on %s\n", id
->ident
);
404 static const struct dmi_system_id intel_dual_link_lvds
[] = {
406 .callback
= intel_dual_link_lvds_callback
,
407 .ident
= "Apple MacBook Pro (Core i5/i7 Series)",
409 DMI_MATCH(DMI_SYS_VENDOR
, "Apple Inc."),
410 DMI_MATCH(DMI_PRODUCT_NAME
, "MacBookPro8,2"),
413 { } /* terminating entry */
416 static bool is_dual_link_lvds(struct drm_i915_private
*dev_priv
,
421 /* use the module option value if specified */
422 if (i915_lvds_channel_mode
> 0)
423 return i915_lvds_channel_mode
== 2;
425 if (dmi_check_system(intel_dual_link_lvds
))
428 if (dev_priv
->lvds_val
)
429 val
= dev_priv
->lvds_val
;
431 /* BIOS should set the proper LVDS register value at boot, but
432 * in reality, it doesn't set the value when the lid is closed;
433 * we need to check "the value to be set" in VBT when LVDS
434 * register is uninitialized.
436 val
= I915_READ(reg
);
437 if (!(val
& ~LVDS_DETECTED
))
438 val
= dev_priv
->bios_lvds_val
;
439 dev_priv
->lvds_val
= val
;
441 return (val
& LVDS_CLKB_POWER_MASK
) == LVDS_CLKB_POWER_UP
;
444 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
,
447 struct drm_device
*dev
= crtc
->dev
;
448 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
449 const intel_limit_t
*limit
;
451 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
452 if (is_dual_link_lvds(dev_priv
, PCH_LVDS
)) {
453 /* LVDS dual channel */
454 if (refclk
== 100000)
455 limit
= &intel_limits_ironlake_dual_lvds_100m
;
457 limit
= &intel_limits_ironlake_dual_lvds
;
459 if (refclk
== 100000)
460 limit
= &intel_limits_ironlake_single_lvds_100m
;
462 limit
= &intel_limits_ironlake_single_lvds
;
464 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
466 limit
= &intel_limits_ironlake_display_port
;
468 limit
= &intel_limits_ironlake_dac
;
473 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
475 struct drm_device
*dev
= crtc
->dev
;
476 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
477 const intel_limit_t
*limit
;
479 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
480 if (is_dual_link_lvds(dev_priv
, LVDS
))
481 /* LVDS with dual channel */
482 limit
= &intel_limits_g4x_dual_channel_lvds
;
484 /* LVDS with dual channel */
485 limit
= &intel_limits_g4x_single_channel_lvds
;
486 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
487 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
488 limit
= &intel_limits_g4x_hdmi
;
489 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
490 limit
= &intel_limits_g4x_sdvo
;
491 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
492 limit
= &intel_limits_g4x_display_port
;
493 } else /* The option is for other outputs */
494 limit
= &intel_limits_i9xx_sdvo
;
499 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
, int refclk
)
501 struct drm_device
*dev
= crtc
->dev
;
502 const intel_limit_t
*limit
;
504 if (HAS_PCH_SPLIT(dev
))
505 limit
= intel_ironlake_limit(crtc
, refclk
);
506 else if (IS_G4X(dev
)) {
507 limit
= intel_g4x_limit(crtc
);
508 } else if (IS_PINEVIEW(dev
)) {
509 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
510 limit
= &intel_limits_pineview_lvds
;
512 limit
= &intel_limits_pineview_sdvo
;
513 } else if (!IS_GEN2(dev
)) {
514 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
515 limit
= &intel_limits_i9xx_lvds
;
517 limit
= &intel_limits_i9xx_sdvo
;
519 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
520 limit
= &intel_limits_i8xx_lvds
;
522 limit
= &intel_limits_i8xx_dvo
;
527 /* m1 is reserved as 0 in Pineview, n is a ring counter */
528 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
530 clock
->m
= clock
->m2
+ 2;
531 clock
->p
= clock
->p1
* clock
->p2
;
532 clock
->vco
= refclk
* clock
->m
/ clock
->n
;
533 clock
->dot
= clock
->vco
/ clock
->p
;
536 static void intel_clock(struct drm_device
*dev
, int refclk
, intel_clock_t
*clock
)
538 if (IS_PINEVIEW(dev
)) {
539 pineview_clock(refclk
, clock
);
542 clock
->m
= 5 * (clock
->m1
+ 2) + (clock
->m2
+ 2);
543 clock
->p
= clock
->p1
* clock
->p2
;
544 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
545 clock
->dot
= clock
->vco
/ clock
->p
;
549 * Returns whether any output on the specified pipe is of the specified type
551 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
553 struct drm_device
*dev
= crtc
->dev
;
554 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
555 struct intel_encoder
*encoder
;
557 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
)
558 if (encoder
->base
.crtc
== crtc
&& encoder
->type
== type
)
564 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
566 * Returns whether the given set of divisors are valid for a given refclk with
567 * the given connectors.
570 static bool intel_PLL_is_valid(struct drm_device
*dev
,
571 const intel_limit_t
*limit
,
572 const intel_clock_t
*clock
)
574 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
575 INTELPllInvalid("p1 out of range\n");
576 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
577 INTELPllInvalid("p out of range\n");
578 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
579 INTELPllInvalid("m2 out of range\n");
580 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
581 INTELPllInvalid("m1 out of range\n");
582 if (clock
->m1
<= clock
->m2
&& !IS_PINEVIEW(dev
))
583 INTELPllInvalid("m1 <= m2\n");
584 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
585 INTELPllInvalid("m out of range\n");
586 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
587 INTELPllInvalid("n out of range\n");
588 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
589 INTELPllInvalid("vco out of range\n");
590 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
591 * connector, etc., rather than just a single range.
593 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
594 INTELPllInvalid("dot out of range\n");
600 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
601 int target
, int refclk
, intel_clock_t
*match_clock
,
602 intel_clock_t
*best_clock
)
605 struct drm_device
*dev
= crtc
->dev
;
606 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
610 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
611 (I915_READ(LVDS
)) != 0) {
613 * For LVDS, if the panel is on, just rely on its current
614 * settings for dual-channel. We haven't figured out how to
615 * reliably set up different single/dual channel state, if we
618 if (is_dual_link_lvds(dev_priv
, LVDS
))
619 clock
.p2
= limit
->p2
.p2_fast
;
621 clock
.p2
= limit
->p2
.p2_slow
;
623 if (target
< limit
->p2
.dot_limit
)
624 clock
.p2
= limit
->p2
.p2_slow
;
626 clock
.p2
= limit
->p2
.p2_fast
;
629 memset(best_clock
, 0, sizeof(*best_clock
));
631 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
633 for (clock
.m2
= limit
->m2
.min
;
634 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
635 /* m1 is always 0 in Pineview */
636 if (clock
.m2
>= clock
.m1
&& !IS_PINEVIEW(dev
))
638 for (clock
.n
= limit
->n
.min
;
639 clock
.n
<= limit
->n
.max
; clock
.n
++) {
640 for (clock
.p1
= limit
->p1
.min
;
641 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
644 intel_clock(dev
, refclk
, &clock
);
645 if (!intel_PLL_is_valid(dev
, limit
,
649 clock
.p
!= match_clock
->p
)
652 this_err
= abs(clock
.dot
- target
);
653 if (this_err
< err
) {
662 return (err
!= target
);
666 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
667 int target
, int refclk
, intel_clock_t
*match_clock
,
668 intel_clock_t
*best_clock
)
670 struct drm_device
*dev
= crtc
->dev
;
671 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
675 /* approximately equals target * 0.00585 */
676 int err_most
= (target
>> 8) + (target
>> 9);
679 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
682 if (HAS_PCH_SPLIT(dev
))
686 if ((I915_READ(lvds_reg
) & LVDS_CLKB_POWER_MASK
) ==
688 clock
.p2
= limit
->p2
.p2_fast
;
690 clock
.p2
= limit
->p2
.p2_slow
;
692 if (target
< limit
->p2
.dot_limit
)
693 clock
.p2
= limit
->p2
.p2_slow
;
695 clock
.p2
= limit
->p2
.p2_fast
;
698 memset(best_clock
, 0, sizeof(*best_clock
));
699 max_n
= limit
->n
.max
;
700 /* based on hardware requirement, prefer smaller n to precision */
701 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
702 /* based on hardware requirement, prefere larger m1,m2 */
703 for (clock
.m1
= limit
->m1
.max
;
704 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
705 for (clock
.m2
= limit
->m2
.max
;
706 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
707 for (clock
.p1
= limit
->p1
.max
;
708 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
711 intel_clock(dev
, refclk
, &clock
);
712 if (!intel_PLL_is_valid(dev
, limit
,
716 clock
.p
!= match_clock
->p
)
719 this_err
= abs(clock
.dot
- target
);
720 if (this_err
< err_most
) {
734 intel_find_pll_ironlake_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
735 int target
, int refclk
, intel_clock_t
*match_clock
,
736 intel_clock_t
*best_clock
)
738 struct drm_device
*dev
= crtc
->dev
;
741 if (target
< 200000) {
754 intel_clock(dev
, refclk
, &clock
);
755 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
759 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
761 intel_find_pll_g4x_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
762 int target
, int refclk
, intel_clock_t
*match_clock
,
763 intel_clock_t
*best_clock
)
766 if (target
< 200000) {
779 clock
.m
= 5 * (clock
.m1
+ 2) + (clock
.m2
+ 2);
780 clock
.p
= (clock
.p1
* clock
.p2
);
781 clock
.dot
= 96000 * clock
.m
/ (clock
.n
+ 2) / clock
.p
;
783 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
787 static void ironlake_wait_for_vblank(struct drm_device
*dev
, int pipe
)
789 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
790 u32 frame
, frame_reg
= PIPEFRAME(pipe
);
792 frame
= I915_READ(frame_reg
);
794 if (wait_for(I915_READ_NOTRACE(frame_reg
) != frame
, 50))
795 DRM_DEBUG_KMS("vblank wait timed out\n");
799 * intel_wait_for_vblank - wait for vblank on a given pipe
801 * @pipe: pipe to wait for
803 * Wait for vblank to occur on a given pipe. Needed for various bits of
806 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
808 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
809 int pipestat_reg
= PIPESTAT(pipe
);
811 if (INTEL_INFO(dev
)->gen
>= 5) {
812 ironlake_wait_for_vblank(dev
, pipe
);
816 /* Clear existing vblank status. Note this will clear any other
817 * sticky status fields as well.
819 * This races with i915_driver_irq_handler() with the result
820 * that either function could miss a vblank event. Here it is not
821 * fatal, as we will either wait upon the next vblank interrupt or
822 * timeout. Generally speaking intel_wait_for_vblank() is only
823 * called during modeset at which time the GPU should be idle and
824 * should *not* be performing page flips and thus not waiting on
826 * Currently, the result of us stealing a vblank from the irq
827 * handler is that a single frame will be skipped during swapbuffers.
829 I915_WRITE(pipestat_reg
,
830 I915_READ(pipestat_reg
) | PIPE_VBLANK_INTERRUPT_STATUS
);
832 /* Wait for vblank interrupt bit to set */
833 if (wait_for(I915_READ(pipestat_reg
) &
834 PIPE_VBLANK_INTERRUPT_STATUS
,
836 DRM_DEBUG_KMS("vblank wait timed out\n");
840 * intel_wait_for_pipe_off - wait for pipe to turn off
842 * @pipe: pipe to wait for
844 * After disabling a pipe, we can't wait for vblank in the usual way,
845 * spinning on the vblank interrupt status bit, since we won't actually
846 * see an interrupt when the pipe is disabled.
849 * wait for the pipe register state bit to turn off
852 * wait for the display line value to settle (it usually
853 * ends up stopping at the start of the next frame).
856 void intel_wait_for_pipe_off(struct drm_device
*dev
, int pipe
)
858 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
860 if (INTEL_INFO(dev
)->gen
>= 4) {
861 int reg
= PIPECONF(pipe
);
863 /* Wait for the Pipe State to go off */
864 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
866 DRM_DEBUG_KMS("pipe_off wait timed out\n");
868 u32 last_line
, line_mask
;
869 int reg
= PIPEDSL(pipe
);
870 unsigned long timeout
= jiffies
+ msecs_to_jiffies(100);
873 line_mask
= DSL_LINEMASK_GEN2
;
875 line_mask
= DSL_LINEMASK_GEN3
;
877 /* Wait for the display line to settle */
879 last_line
= I915_READ(reg
) & line_mask
;
881 } while (((I915_READ(reg
) & line_mask
) != last_line
) &&
882 time_after(timeout
, jiffies
));
883 if (time_after(jiffies
, timeout
))
884 DRM_DEBUG_KMS("pipe_off wait timed out\n");
888 static const char *state_string(bool enabled
)
890 return enabled
? "on" : "off";
893 /* Only for pre-ILK configs */
894 static void assert_pll(struct drm_i915_private
*dev_priv
,
895 enum pipe pipe
, bool state
)
902 val
= I915_READ(reg
);
903 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
904 WARN(cur_state
!= state
,
905 "PLL state assertion failure (expected %s, current %s)\n",
906 state_string(state
), state_string(cur_state
));
908 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
909 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
912 static void assert_pch_pll(struct drm_i915_private
*dev_priv
,
913 struct intel_pch_pll
*pll
,
914 struct intel_crtc
*crtc
,
920 if (HAS_PCH_LPT(dev_priv
->dev
)) {
921 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
926 "asserting PCH PLL %s with no PLL\n", state_string(state
)))
929 val
= I915_READ(pll
->pll_reg
);
930 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
931 WARN(cur_state
!= state
,
932 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
933 pll
->pll_reg
, state_string(state
), state_string(cur_state
), val
);
935 /* Make sure the selected PLL is correctly attached to the transcoder */
936 if (crtc
&& HAS_PCH_CPT(dev_priv
->dev
)) {
939 pch_dpll
= I915_READ(PCH_DPLL_SEL
);
940 cur_state
= pll
->pll_reg
== _PCH_DPLL_B
;
941 if (!WARN(((pch_dpll
>> (4 * crtc
->pipe
)) & 1) != cur_state
,
942 "PLL[%d] not attached to this transcoder %d: %08x\n",
943 cur_state
, crtc
->pipe
, pch_dpll
)) {
944 cur_state
= !!(val
>> (4*crtc
->pipe
+ 3));
945 WARN(cur_state
!= state
,
946 "PLL[%d] not %s on this transcoder %d: %08x\n",
947 pll
->pll_reg
== _PCH_DPLL_B
,
954 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
955 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
957 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
958 enum pipe pipe
, bool state
)
964 if (IS_HASWELL(dev_priv
->dev
)) {
965 /* On Haswell, DDI is used instead of FDI_TX_CTL */
966 reg
= DDI_FUNC_CTL(pipe
);
967 val
= I915_READ(reg
);
968 cur_state
= !!(val
& PIPE_DDI_FUNC_ENABLE
);
970 reg
= FDI_TX_CTL(pipe
);
971 val
= I915_READ(reg
);
972 cur_state
= !!(val
& FDI_TX_ENABLE
);
974 WARN(cur_state
!= state
,
975 "FDI TX state assertion failure (expected %s, current %s)\n",
976 state_string(state
), state_string(cur_state
));
978 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
979 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
981 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
982 enum pipe pipe
, bool state
)
988 if (IS_HASWELL(dev_priv
->dev
) && pipe
> 0) {
989 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
992 reg
= FDI_RX_CTL(pipe
);
993 val
= I915_READ(reg
);
994 cur_state
= !!(val
& FDI_RX_ENABLE
);
996 WARN(cur_state
!= state
,
997 "FDI RX state assertion failure (expected %s, current %s)\n",
998 state_string(state
), state_string(cur_state
));
1000 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1001 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1003 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1009 /* ILK FDI PLL is always enabled */
1010 if (dev_priv
->info
->gen
== 5)
1013 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1014 if (IS_HASWELL(dev_priv
->dev
))
1017 reg
= FDI_TX_CTL(pipe
);
1018 val
= I915_READ(reg
);
1019 WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1022 static void assert_fdi_rx_pll_enabled(struct drm_i915_private
*dev_priv
,
1028 if (IS_HASWELL(dev_priv
->dev
) && pipe
> 0) {
1029 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1032 reg
= FDI_RX_CTL(pipe
);
1033 val
= I915_READ(reg
);
1034 WARN(!(val
& FDI_RX_PLL_ENABLE
), "FDI RX PLL assertion failure, should be active but is disabled\n");
1037 static void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1040 int pp_reg
, lvds_reg
;
1042 enum pipe panel_pipe
= PIPE_A
;
1045 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
1046 pp_reg
= PCH_PP_CONTROL
;
1047 lvds_reg
= PCH_LVDS
;
1049 pp_reg
= PP_CONTROL
;
1053 val
= I915_READ(pp_reg
);
1054 if (!(val
& PANEL_POWER_ON
) ||
1055 ((val
& PANEL_UNLOCK_REGS
) == PANEL_UNLOCK_REGS
))
1058 if (I915_READ(lvds_reg
) & LVDS_PIPEB_SELECT
)
1059 panel_pipe
= PIPE_B
;
1061 WARN(panel_pipe
== pipe
&& locked
,
1062 "panel assertion failure, pipe %c regs locked\n",
1066 void assert_pipe(struct drm_i915_private
*dev_priv
,
1067 enum pipe pipe
, bool state
)
1073 /* if we need the pipe A quirk it must be always on */
1074 if (pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
1077 reg
= PIPECONF(pipe
);
1078 val
= I915_READ(reg
);
1079 cur_state
= !!(val
& PIPECONF_ENABLE
);
1080 WARN(cur_state
!= state
,
1081 "pipe %c assertion failure (expected %s, current %s)\n",
1082 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1085 static void assert_plane(struct drm_i915_private
*dev_priv
,
1086 enum plane plane
, bool state
)
1092 reg
= DSPCNTR(plane
);
1093 val
= I915_READ(reg
);
1094 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1095 WARN(cur_state
!= state
,
1096 "plane %c assertion failure (expected %s, current %s)\n",
1097 plane_name(plane
), state_string(state
), state_string(cur_state
));
1100 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1101 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1103 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1110 /* Planes are fixed to pipes on ILK+ */
1111 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
1112 reg
= DSPCNTR(pipe
);
1113 val
= I915_READ(reg
);
1114 WARN((val
& DISPLAY_PLANE_ENABLE
),
1115 "plane %c assertion failure, should be disabled but not\n",
1120 /* Need to check both planes against the pipe */
1121 for (i
= 0; i
< 2; i
++) {
1123 val
= I915_READ(reg
);
1124 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1125 DISPPLANE_SEL_PIPE_SHIFT
;
1126 WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1127 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1128 plane_name(i
), pipe_name(pipe
));
1132 static void assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1137 if (HAS_PCH_LPT(dev_priv
->dev
)) {
1138 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1142 val
= I915_READ(PCH_DREF_CONTROL
);
1143 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1144 DREF_SUPERSPREAD_SOURCE_MASK
));
1145 WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1148 static void assert_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1155 reg
= TRANSCONF(pipe
);
1156 val
= I915_READ(reg
);
1157 enabled
= !!(val
& TRANS_ENABLE
);
1159 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1163 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1164 enum pipe pipe
, u32 port_sel
, u32 val
)
1166 if ((val
& DP_PORT_EN
) == 0)
1169 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1170 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1171 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1172 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1175 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1181 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1182 enum pipe pipe
, u32 val
)
1184 if ((val
& PORT_ENABLE
) == 0)
1187 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1188 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1191 if ((val
& TRANSCODER_MASK
) != TRANSCODER(pipe
))
1197 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1198 enum pipe pipe
, u32 val
)
1200 if ((val
& LVDS_PORT_EN
) == 0)
1203 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1204 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1207 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1213 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1214 enum pipe pipe
, u32 val
)
1216 if ((val
& ADPA_DAC_ENABLE
) == 0)
1218 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1219 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1222 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1228 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1229 enum pipe pipe
, int reg
, u32 port_sel
)
1231 u32 val
= I915_READ(reg
);
1232 WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1233 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1234 reg
, pipe_name(pipe
));
1237 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1238 enum pipe pipe
, int reg
)
1240 u32 val
= I915_READ(reg
);
1241 WARN(hdmi_pipe_enabled(dev_priv
, val
, pipe
),
1242 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1243 reg
, pipe_name(pipe
));
1246 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1252 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1253 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1254 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1257 val
= I915_READ(reg
);
1258 WARN(adpa_pipe_enabled(dev_priv
, val
, pipe
),
1259 "PCH VGA enabled on transcoder %c, should be disabled\n",
1263 val
= I915_READ(reg
);
1264 WARN(lvds_pipe_enabled(dev_priv
, val
, pipe
),
1265 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1268 assert_pch_hdmi_disabled(dev_priv
, pipe
, HDMIB
);
1269 assert_pch_hdmi_disabled(dev_priv
, pipe
, HDMIC
);
1270 assert_pch_hdmi_disabled(dev_priv
, pipe
, HDMID
);
1274 * intel_enable_pll - enable a PLL
1275 * @dev_priv: i915 private structure
1276 * @pipe: pipe PLL to enable
1278 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1279 * make sure the PLL reg is writable first though, since the panel write
1280 * protect mechanism may be enabled.
1282 * Note! This is for pre-ILK only.
1284 static void intel_enable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1289 /* No really, not for ILK+ */
1290 BUG_ON(dev_priv
->info
->gen
>= 5);
1292 /* PLL is protected by panel, make sure we can write it */
1293 if (IS_MOBILE(dev_priv
->dev
) && !IS_I830(dev_priv
->dev
))
1294 assert_panel_unlocked(dev_priv
, pipe
);
1297 val
= I915_READ(reg
);
1298 val
|= DPLL_VCO_ENABLE
;
1300 /* We do this three times for luck */
1301 I915_WRITE(reg
, val
);
1303 udelay(150); /* wait for warmup */
1304 I915_WRITE(reg
, val
);
1306 udelay(150); /* wait for warmup */
1307 I915_WRITE(reg
, val
);
1309 udelay(150); /* wait for warmup */
1313 * intel_disable_pll - disable a PLL
1314 * @dev_priv: i915 private structure
1315 * @pipe: pipe PLL to disable
1317 * Disable the PLL for @pipe, making sure the pipe is off first.
1319 * Note! This is for pre-ILK only.
1321 static void intel_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1326 /* Don't disable pipe A or pipe A PLLs if needed */
1327 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1330 /* Make sure the pipe isn't still relying on us */
1331 assert_pipe_disabled(dev_priv
, pipe
);
1334 val
= I915_READ(reg
);
1335 val
&= ~DPLL_VCO_ENABLE
;
1336 I915_WRITE(reg
, val
);
1342 intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
)
1344 unsigned long flags
;
1346 spin_lock_irqsave(&dev_priv
->dpio_lock
, flags
);
1347 if (wait_for((I915_READ(SBI_CTL_STAT
) & SBI_READY
) == 0,
1349 DRM_ERROR("timeout waiting for SBI to become ready\n");
1353 I915_WRITE(SBI_ADDR
,
1355 I915_WRITE(SBI_DATA
,
1357 I915_WRITE(SBI_CTL_STAT
,
1361 if (wait_for((I915_READ(SBI_CTL_STAT
) & (SBI_READY
| SBI_RESPONSE_SUCCESS
)) == 0,
1363 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1368 spin_unlock_irqrestore(&dev_priv
->dpio_lock
, flags
);
1372 intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
)
1374 unsigned long flags
;
1377 spin_lock_irqsave(&dev_priv
->dpio_lock
, flags
);
1378 if (wait_for((I915_READ(SBI_CTL_STAT
) & SBI_READY
) == 0,
1380 DRM_ERROR("timeout waiting for SBI to become ready\n");
1384 I915_WRITE(SBI_ADDR
,
1386 I915_WRITE(SBI_CTL_STAT
,
1390 if (wait_for((I915_READ(SBI_CTL_STAT
) & (SBI_READY
| SBI_RESPONSE_SUCCESS
)) == 0,
1392 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1396 value
= I915_READ(SBI_DATA
);
1399 spin_unlock_irqrestore(&dev_priv
->dpio_lock
, flags
);
1404 * intel_enable_pch_pll - enable PCH PLL
1405 * @dev_priv: i915 private structure
1406 * @pipe: pipe PLL to enable
1408 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1409 * drives the transcoder clock.
1411 static void intel_enable_pch_pll(struct intel_crtc
*intel_crtc
)
1413 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
1414 struct intel_pch_pll
*pll
;
1418 /* PCH PLLs only available on ILK, SNB and IVB */
1419 BUG_ON(dev_priv
->info
->gen
< 5);
1420 pll
= intel_crtc
->pch_pll
;
1424 if (WARN_ON(pll
->refcount
== 0))
1427 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1428 pll
->pll_reg
, pll
->active
, pll
->on
,
1429 intel_crtc
->base
.base
.id
);
1431 /* PCH refclock must be enabled first */
1432 assert_pch_refclk_enabled(dev_priv
);
1434 if (pll
->active
++ && pll
->on
) {
1435 assert_pch_pll_enabled(dev_priv
, pll
, NULL
);
1439 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll
->pll_reg
);
1442 val
= I915_READ(reg
);
1443 val
|= DPLL_VCO_ENABLE
;
1444 I915_WRITE(reg
, val
);
1451 static void intel_disable_pch_pll(struct intel_crtc
*intel_crtc
)
1453 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
1454 struct intel_pch_pll
*pll
= intel_crtc
->pch_pll
;
1458 /* PCH only available on ILK+ */
1459 BUG_ON(dev_priv
->info
->gen
< 5);
1463 if (WARN_ON(pll
->refcount
== 0))
1466 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1467 pll
->pll_reg
, pll
->active
, pll
->on
,
1468 intel_crtc
->base
.base
.id
);
1470 if (WARN_ON(pll
->active
== 0)) {
1471 assert_pch_pll_disabled(dev_priv
, pll
, NULL
);
1475 if (--pll
->active
) {
1476 assert_pch_pll_enabled(dev_priv
, pll
, NULL
);
1480 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll
->pll_reg
);
1482 /* Make sure transcoder isn't still depending on us */
1483 assert_transcoder_disabled(dev_priv
, intel_crtc
->pipe
);
1486 val
= I915_READ(reg
);
1487 val
&= ~DPLL_VCO_ENABLE
;
1488 I915_WRITE(reg
, val
);
1495 static void intel_enable_transcoder(struct drm_i915_private
*dev_priv
,
1499 u32 val
, pipeconf_val
;
1500 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1502 /* PCH only available on ILK+ */
1503 BUG_ON(dev_priv
->info
->gen
< 5);
1505 /* Make sure PCH DPLL is enabled */
1506 assert_pch_pll_enabled(dev_priv
,
1507 to_intel_crtc(crtc
)->pch_pll
,
1508 to_intel_crtc(crtc
));
1510 /* FDI must be feeding us bits for PCH ports */
1511 assert_fdi_tx_enabled(dev_priv
, pipe
);
1512 assert_fdi_rx_enabled(dev_priv
, pipe
);
1514 if (IS_HASWELL(dev_priv
->dev
) && pipe
> 0) {
1515 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1518 reg
= TRANSCONF(pipe
);
1519 val
= I915_READ(reg
);
1520 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1522 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1524 * make the BPC in transcoder be consistent with
1525 * that in pipeconf reg.
1527 val
&= ~PIPE_BPC_MASK
;
1528 val
|= pipeconf_val
& PIPE_BPC_MASK
;
1531 val
&= ~TRANS_INTERLACE_MASK
;
1532 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1533 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1534 intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
))
1535 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1537 val
|= TRANS_INTERLACED
;
1539 val
|= TRANS_PROGRESSIVE
;
1541 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1542 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1543 DRM_ERROR("failed to enable transcoder %d\n", pipe
);
1546 static void intel_disable_transcoder(struct drm_i915_private
*dev_priv
,
1552 /* FDI relies on the transcoder */
1553 assert_fdi_tx_disabled(dev_priv
, pipe
);
1554 assert_fdi_rx_disabled(dev_priv
, pipe
);
1556 /* Ports must be off as well */
1557 assert_pch_ports_disabled(dev_priv
, pipe
);
1559 reg
= TRANSCONF(pipe
);
1560 val
= I915_READ(reg
);
1561 val
&= ~TRANS_ENABLE
;
1562 I915_WRITE(reg
, val
);
1563 /* wait for PCH transcoder off, transcoder state */
1564 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1565 DRM_ERROR("failed to disable transcoder %d\n", pipe
);
1569 * intel_enable_pipe - enable a pipe, asserting requirements
1570 * @dev_priv: i915 private structure
1571 * @pipe: pipe to enable
1572 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1574 * Enable @pipe, making sure that various hardware specific requirements
1575 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1577 * @pipe should be %PIPE_A or %PIPE_B.
1579 * Will wait until the pipe is actually running (i.e. first vblank) before
1582 static void intel_enable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
1589 * A pipe without a PLL won't actually be able to drive bits from
1590 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1593 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
1594 assert_pll_enabled(dev_priv
, pipe
);
1597 /* if driving the PCH, we need FDI enabled */
1598 assert_fdi_rx_pll_enabled(dev_priv
, pipe
);
1599 assert_fdi_tx_pll_enabled(dev_priv
, pipe
);
1601 /* FIXME: assert CPU port conditions for SNB+ */
1604 reg
= PIPECONF(pipe
);
1605 val
= I915_READ(reg
);
1606 if (val
& PIPECONF_ENABLE
)
1609 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
1610 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1614 * intel_disable_pipe - disable a pipe, asserting requirements
1615 * @dev_priv: i915 private structure
1616 * @pipe: pipe to disable
1618 * Disable @pipe, making sure that various hardware specific requirements
1619 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1621 * @pipe should be %PIPE_A or %PIPE_B.
1623 * Will wait until the pipe has shut down before returning.
1625 static void intel_disable_pipe(struct drm_i915_private
*dev_priv
,
1632 * Make sure planes won't keep trying to pump pixels to us,
1633 * or we might hang the display.
1635 assert_planes_disabled(dev_priv
, pipe
);
1637 /* Don't disable pipe A or pipe A PLLs if needed */
1638 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1641 reg
= PIPECONF(pipe
);
1642 val
= I915_READ(reg
);
1643 if ((val
& PIPECONF_ENABLE
) == 0)
1646 I915_WRITE(reg
, val
& ~PIPECONF_ENABLE
);
1647 intel_wait_for_pipe_off(dev_priv
->dev
, pipe
);
1651 * Plane regs are double buffered, going from enabled->disabled needs a
1652 * trigger in order to latch. The display address reg provides this.
1654 void intel_flush_display_plane(struct drm_i915_private
*dev_priv
,
1657 I915_WRITE(DSPADDR(plane
), I915_READ(DSPADDR(plane
)));
1658 I915_WRITE(DSPSURF(plane
), I915_READ(DSPSURF(plane
)));
1662 * intel_enable_plane - enable a display plane on a given pipe
1663 * @dev_priv: i915 private structure
1664 * @plane: plane to enable
1665 * @pipe: pipe being fed
1667 * Enable @plane on @pipe, making sure that @pipe is running first.
1669 static void intel_enable_plane(struct drm_i915_private
*dev_priv
,
1670 enum plane plane
, enum pipe pipe
)
1675 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1676 assert_pipe_enabled(dev_priv
, pipe
);
1678 reg
= DSPCNTR(plane
);
1679 val
= I915_READ(reg
);
1680 if (val
& DISPLAY_PLANE_ENABLE
)
1683 I915_WRITE(reg
, val
| DISPLAY_PLANE_ENABLE
);
1684 intel_flush_display_plane(dev_priv
, plane
);
1685 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1689 * intel_disable_plane - disable a display plane
1690 * @dev_priv: i915 private structure
1691 * @plane: plane to disable
1692 * @pipe: pipe consuming the data
1694 * Disable @plane; should be an independent operation.
1696 static void intel_disable_plane(struct drm_i915_private
*dev_priv
,
1697 enum plane plane
, enum pipe pipe
)
1702 reg
= DSPCNTR(plane
);
1703 val
= I915_READ(reg
);
1704 if ((val
& DISPLAY_PLANE_ENABLE
) == 0)
1707 I915_WRITE(reg
, val
& ~DISPLAY_PLANE_ENABLE
);
1708 intel_flush_display_plane(dev_priv
, plane
);
1709 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1712 static void disable_pch_dp(struct drm_i915_private
*dev_priv
,
1713 enum pipe pipe
, int reg
, u32 port_sel
)
1715 u32 val
= I915_READ(reg
);
1716 if (dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
)) {
1717 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg
, pipe
);
1718 I915_WRITE(reg
, val
& ~DP_PORT_EN
);
1722 static void disable_pch_hdmi(struct drm_i915_private
*dev_priv
,
1723 enum pipe pipe
, int reg
)
1725 u32 val
= I915_READ(reg
);
1726 if (hdmi_pipe_enabled(dev_priv
, val
, pipe
)) {
1727 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1729 I915_WRITE(reg
, val
& ~PORT_ENABLE
);
1733 /* Disable any ports connected to this transcoder */
1734 static void intel_disable_pch_ports(struct drm_i915_private
*dev_priv
,
1739 val
= I915_READ(PCH_PP_CONTROL
);
1740 I915_WRITE(PCH_PP_CONTROL
, val
| PANEL_UNLOCK_REGS
);
1742 disable_pch_dp(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1743 disable_pch_dp(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1744 disable_pch_dp(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1747 val
= I915_READ(reg
);
1748 if (adpa_pipe_enabled(dev_priv
, val
, pipe
))
1749 I915_WRITE(reg
, val
& ~ADPA_DAC_ENABLE
);
1752 val
= I915_READ(reg
);
1753 if (lvds_pipe_enabled(dev_priv
, val
, pipe
)) {
1754 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe
, val
);
1755 I915_WRITE(reg
, val
& ~LVDS_PORT_EN
);
1760 disable_pch_hdmi(dev_priv
, pipe
, HDMIB
);
1761 disable_pch_hdmi(dev_priv
, pipe
, HDMIC
);
1762 disable_pch_hdmi(dev_priv
, pipe
, HDMID
);
1766 intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
1767 struct drm_i915_gem_object
*obj
,
1768 struct intel_ring_buffer
*pipelined
)
1770 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1774 switch (obj
->tiling_mode
) {
1775 case I915_TILING_NONE
:
1776 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
1777 alignment
= 128 * 1024;
1778 else if (INTEL_INFO(dev
)->gen
>= 4)
1779 alignment
= 4 * 1024;
1781 alignment
= 64 * 1024;
1784 /* pin() will align the object as required by fence */
1788 /* FIXME: Is this true? */
1789 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1795 dev_priv
->mm
.interruptible
= false;
1796 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
);
1798 goto err_interruptible
;
1800 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1801 * fence, whereas 965+ only requires a fence if using
1802 * framebuffer compression. For simplicity, we always install
1803 * a fence as the cost is not that onerous.
1805 ret
= i915_gem_object_get_fence(obj
);
1809 i915_gem_object_pin_fence(obj
);
1811 dev_priv
->mm
.interruptible
= true;
1815 i915_gem_object_unpin(obj
);
1817 dev_priv
->mm
.interruptible
= true;
1821 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
)
1823 i915_gem_object_unpin_fence(obj
);
1824 i915_gem_object_unpin(obj
);
1827 static int i9xx_update_plane(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
1830 struct drm_device
*dev
= crtc
->dev
;
1831 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1832 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1833 struct intel_framebuffer
*intel_fb
;
1834 struct drm_i915_gem_object
*obj
;
1835 int plane
= intel_crtc
->plane
;
1836 unsigned long Start
, Offset
;
1845 DRM_ERROR("Can't update plane %d in SAREA\n", plane
);
1849 intel_fb
= to_intel_framebuffer(fb
);
1850 obj
= intel_fb
->obj
;
1852 reg
= DSPCNTR(plane
);
1853 dspcntr
= I915_READ(reg
);
1854 /* Mask out pixel format bits in case we change it */
1855 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
1856 switch (fb
->bits_per_pixel
) {
1858 dspcntr
|= DISPPLANE_8BPP
;
1861 if (fb
->depth
== 15)
1862 dspcntr
|= DISPPLANE_15_16BPP
;
1864 dspcntr
|= DISPPLANE_16BPP
;
1868 dspcntr
|= DISPPLANE_32BPP_NO_ALPHA
;
1871 DRM_ERROR("Unknown color depth %d\n", fb
->bits_per_pixel
);
1874 if (INTEL_INFO(dev
)->gen
>= 4) {
1875 if (obj
->tiling_mode
!= I915_TILING_NONE
)
1876 dspcntr
|= DISPPLANE_TILED
;
1878 dspcntr
&= ~DISPPLANE_TILED
;
1881 I915_WRITE(reg
, dspcntr
);
1883 Start
= obj
->gtt_offset
;
1884 Offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
1886 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1887 Start
, Offset
, x
, y
, fb
->pitches
[0]);
1888 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
1889 if (INTEL_INFO(dev
)->gen
>= 4) {
1890 I915_MODIFY_DISPBASE(DSPSURF(plane
), Start
);
1891 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
1892 I915_WRITE(DSPADDR(plane
), Offset
);
1894 I915_WRITE(DSPADDR(plane
), Start
+ Offset
);
1900 static int ironlake_update_plane(struct drm_crtc
*crtc
,
1901 struct drm_framebuffer
*fb
, int x
, int y
)
1903 struct drm_device
*dev
= crtc
->dev
;
1904 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1905 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1906 struct intel_framebuffer
*intel_fb
;
1907 struct drm_i915_gem_object
*obj
;
1908 int plane
= intel_crtc
->plane
;
1909 unsigned long Start
, Offset
;
1919 DRM_ERROR("Can't update plane %d in SAREA\n", plane
);
1923 intel_fb
= to_intel_framebuffer(fb
);
1924 obj
= intel_fb
->obj
;
1926 reg
= DSPCNTR(plane
);
1927 dspcntr
= I915_READ(reg
);
1928 /* Mask out pixel format bits in case we change it */
1929 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
1930 switch (fb
->bits_per_pixel
) {
1932 dspcntr
|= DISPPLANE_8BPP
;
1935 if (fb
->depth
!= 16)
1938 dspcntr
|= DISPPLANE_16BPP
;
1942 if (fb
->depth
== 24)
1943 dspcntr
|= DISPPLANE_32BPP_NO_ALPHA
;
1944 else if (fb
->depth
== 30)
1945 dspcntr
|= DISPPLANE_32BPP_30BIT_NO_ALPHA
;
1950 DRM_ERROR("Unknown color depth %d\n", fb
->bits_per_pixel
);
1954 if (obj
->tiling_mode
!= I915_TILING_NONE
)
1955 dspcntr
|= DISPPLANE_TILED
;
1957 dspcntr
&= ~DISPPLANE_TILED
;
1960 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
1962 I915_WRITE(reg
, dspcntr
);
1964 Start
= obj
->gtt_offset
;
1965 Offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
1967 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1968 Start
, Offset
, x
, y
, fb
->pitches
[0]);
1969 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
1970 I915_MODIFY_DISPBASE(DSPSURF(plane
), Start
);
1971 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
1972 I915_WRITE(DSPADDR(plane
), Offset
);
1978 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1980 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
1981 int x
, int y
, enum mode_set_atomic state
)
1983 struct drm_device
*dev
= crtc
->dev
;
1984 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1986 if (dev_priv
->display
.disable_fbc
)
1987 dev_priv
->display
.disable_fbc(dev
);
1988 intel_increase_pllclock(crtc
);
1990 return dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
1994 intel_finish_fb(struct drm_framebuffer
*old_fb
)
1996 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(old_fb
)->obj
;
1997 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1998 bool was_interruptible
= dev_priv
->mm
.interruptible
;
2001 wait_event(dev_priv
->pending_flip_queue
,
2002 atomic_read(&dev_priv
->mm
.wedged
) ||
2003 atomic_read(&obj
->pending_flip
) == 0);
2005 /* Big Hammer, we also need to ensure that any pending
2006 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2007 * current scanout is retired before unpinning the old
2010 * This should only fail upon a hung GPU, in which case we
2011 * can safely continue.
2013 dev_priv
->mm
.interruptible
= false;
2014 ret
= i915_gem_object_finish_gpu(obj
);
2015 dev_priv
->mm
.interruptible
= was_interruptible
;
2021 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2022 struct drm_framebuffer
*old_fb
)
2024 struct drm_device
*dev
= crtc
->dev
;
2025 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2026 struct drm_i915_master_private
*master_priv
;
2027 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2032 DRM_ERROR("No FB bound\n");
2036 if(intel_crtc
->plane
> dev_priv
->num_pipe
) {
2037 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2039 dev_priv
->num_pipe
);
2043 mutex_lock(&dev
->struct_mutex
);
2044 ret
= intel_pin_and_fence_fb_obj(dev
,
2045 to_intel_framebuffer(crtc
->fb
)->obj
,
2048 mutex_unlock(&dev
->struct_mutex
);
2049 DRM_ERROR("pin & fence failed\n");
2054 intel_finish_fb(old_fb
);
2056 ret
= dev_priv
->display
.update_plane(crtc
, crtc
->fb
, x
, y
);
2058 intel_unpin_fb_obj(to_intel_framebuffer(crtc
->fb
)->obj
);
2059 mutex_unlock(&dev
->struct_mutex
);
2060 DRM_ERROR("failed to update base address\n");
2065 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2066 intel_unpin_fb_obj(to_intel_framebuffer(old_fb
)->obj
);
2069 intel_update_fbc(dev
);
2070 mutex_unlock(&dev
->struct_mutex
);
2072 if (!dev
->primary
->master
)
2075 master_priv
= dev
->primary
->master
->driver_priv
;
2076 if (!master_priv
->sarea_priv
)
2079 if (intel_crtc
->pipe
) {
2080 master_priv
->sarea_priv
->pipeB_x
= x
;
2081 master_priv
->sarea_priv
->pipeB_y
= y
;
2083 master_priv
->sarea_priv
->pipeA_x
= x
;
2084 master_priv
->sarea_priv
->pipeA_y
= y
;
2090 static void ironlake_set_pll_edp(struct drm_crtc
*crtc
, int clock
)
2092 struct drm_device
*dev
= crtc
->dev
;
2093 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2096 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock
);
2097 dpa_ctl
= I915_READ(DP_A
);
2098 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
2100 if (clock
< 200000) {
2102 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
2103 /* workaround for 160Mhz:
2104 1) program 0x4600c bits 15:0 = 0x8124
2105 2) program 0x46010 bit 0 = 1
2106 3) program 0x46034 bit 24 = 1
2107 4) program 0x64000 bit 14 = 1
2109 temp
= I915_READ(0x4600c);
2111 I915_WRITE(0x4600c, temp
| 0x8124);
2113 temp
= I915_READ(0x46010);
2114 I915_WRITE(0x46010, temp
| 1);
2116 temp
= I915_READ(0x46034);
2117 I915_WRITE(0x46034, temp
| (1 << 24));
2119 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
2121 I915_WRITE(DP_A
, dpa_ctl
);
2127 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
2129 struct drm_device
*dev
= crtc
->dev
;
2130 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2131 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2132 int pipe
= intel_crtc
->pipe
;
2135 /* enable normal train */
2136 reg
= FDI_TX_CTL(pipe
);
2137 temp
= I915_READ(reg
);
2138 if (IS_IVYBRIDGE(dev
)) {
2139 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2140 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2142 temp
&= ~FDI_LINK_TRAIN_NONE
;
2143 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2145 I915_WRITE(reg
, temp
);
2147 reg
= FDI_RX_CTL(pipe
);
2148 temp
= I915_READ(reg
);
2149 if (HAS_PCH_CPT(dev
)) {
2150 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2151 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2153 temp
&= ~FDI_LINK_TRAIN_NONE
;
2154 temp
|= FDI_LINK_TRAIN_NONE
;
2156 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2158 /* wait one idle pattern time */
2162 /* IVB wants error correction enabled */
2163 if (IS_IVYBRIDGE(dev
))
2164 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
2165 FDI_FE_ERRC_ENABLE
);
2168 static void cpt_phase_pointer_enable(struct drm_device
*dev
, int pipe
)
2170 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2171 u32 flags
= I915_READ(SOUTH_CHICKEN1
);
2173 flags
|= FDI_PHASE_SYNC_OVR(pipe
);
2174 I915_WRITE(SOUTH_CHICKEN1
, flags
); /* once to unlock... */
2175 flags
|= FDI_PHASE_SYNC_EN(pipe
);
2176 I915_WRITE(SOUTH_CHICKEN1
, flags
); /* then again to enable */
2177 POSTING_READ(SOUTH_CHICKEN1
);
2180 /* The FDI link training functions for ILK/Ibexpeak. */
2181 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
2183 struct drm_device
*dev
= crtc
->dev
;
2184 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2185 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2186 int pipe
= intel_crtc
->pipe
;
2187 int plane
= intel_crtc
->plane
;
2188 u32 reg
, temp
, tries
;
2190 /* FDI needs bits from pipe & plane first */
2191 assert_pipe_enabled(dev_priv
, pipe
);
2192 assert_plane_enabled(dev_priv
, plane
);
2194 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2196 reg
= FDI_RX_IMR(pipe
);
2197 temp
= I915_READ(reg
);
2198 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2199 temp
&= ~FDI_RX_BIT_LOCK
;
2200 I915_WRITE(reg
, temp
);
2204 /* enable CPU FDI TX and PCH FDI RX */
2205 reg
= FDI_TX_CTL(pipe
);
2206 temp
= I915_READ(reg
);
2208 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2209 temp
&= ~FDI_LINK_TRAIN_NONE
;
2210 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2211 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2213 reg
= FDI_RX_CTL(pipe
);
2214 temp
= I915_READ(reg
);
2215 temp
&= ~FDI_LINK_TRAIN_NONE
;
2216 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2217 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2222 /* Ironlake workaround, enable clock pointer after FDI enable*/
2223 if (HAS_PCH_IBX(dev
)) {
2224 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2225 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
2226 FDI_RX_PHASE_SYNC_POINTER_EN
);
2229 reg
= FDI_RX_IIR(pipe
);
2230 for (tries
= 0; tries
< 5; tries
++) {
2231 temp
= I915_READ(reg
);
2232 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2234 if ((temp
& FDI_RX_BIT_LOCK
)) {
2235 DRM_DEBUG_KMS("FDI train 1 done.\n");
2236 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2241 DRM_ERROR("FDI train 1 fail!\n");
2244 reg
= FDI_TX_CTL(pipe
);
2245 temp
= I915_READ(reg
);
2246 temp
&= ~FDI_LINK_TRAIN_NONE
;
2247 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2248 I915_WRITE(reg
, temp
);
2250 reg
= FDI_RX_CTL(pipe
);
2251 temp
= I915_READ(reg
);
2252 temp
&= ~FDI_LINK_TRAIN_NONE
;
2253 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2254 I915_WRITE(reg
, temp
);
2259 reg
= FDI_RX_IIR(pipe
);
2260 for (tries
= 0; tries
< 5; tries
++) {
2261 temp
= I915_READ(reg
);
2262 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2264 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2265 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2266 DRM_DEBUG_KMS("FDI train 2 done.\n");
2271 DRM_ERROR("FDI train 2 fail!\n");
2273 DRM_DEBUG_KMS("FDI train done\n");
2277 static const int snb_b_fdi_train_param
[] = {
2278 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
2279 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
2280 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
2281 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
2284 /* The FDI link training functions for SNB/Cougarpoint. */
2285 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
2287 struct drm_device
*dev
= crtc
->dev
;
2288 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2289 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2290 int pipe
= intel_crtc
->pipe
;
2291 u32 reg
, temp
, i
, retry
;
2293 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2295 reg
= FDI_RX_IMR(pipe
);
2296 temp
= I915_READ(reg
);
2297 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2298 temp
&= ~FDI_RX_BIT_LOCK
;
2299 I915_WRITE(reg
, temp
);
2304 /* enable CPU FDI TX and PCH FDI RX */
2305 reg
= FDI_TX_CTL(pipe
);
2306 temp
= I915_READ(reg
);
2308 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2309 temp
&= ~FDI_LINK_TRAIN_NONE
;
2310 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2311 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2313 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2314 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2316 reg
= FDI_RX_CTL(pipe
);
2317 temp
= I915_READ(reg
);
2318 if (HAS_PCH_CPT(dev
)) {
2319 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2320 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2322 temp
&= ~FDI_LINK_TRAIN_NONE
;
2323 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2325 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2330 if (HAS_PCH_CPT(dev
))
2331 cpt_phase_pointer_enable(dev
, pipe
);
2333 for (i
= 0; i
< 4; i
++) {
2334 reg
= FDI_TX_CTL(pipe
);
2335 temp
= I915_READ(reg
);
2336 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2337 temp
|= snb_b_fdi_train_param
[i
];
2338 I915_WRITE(reg
, temp
);
2343 for (retry
= 0; retry
< 5; retry
++) {
2344 reg
= FDI_RX_IIR(pipe
);
2345 temp
= I915_READ(reg
);
2346 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2347 if (temp
& FDI_RX_BIT_LOCK
) {
2348 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2349 DRM_DEBUG_KMS("FDI train 1 done.\n");
2358 DRM_ERROR("FDI train 1 fail!\n");
2361 reg
= FDI_TX_CTL(pipe
);
2362 temp
= I915_READ(reg
);
2363 temp
&= ~FDI_LINK_TRAIN_NONE
;
2364 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2366 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2368 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2370 I915_WRITE(reg
, temp
);
2372 reg
= FDI_RX_CTL(pipe
);
2373 temp
= I915_READ(reg
);
2374 if (HAS_PCH_CPT(dev
)) {
2375 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2376 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2378 temp
&= ~FDI_LINK_TRAIN_NONE
;
2379 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2381 I915_WRITE(reg
, temp
);
2386 for (i
= 0; i
< 4; i
++) {
2387 reg
= FDI_TX_CTL(pipe
);
2388 temp
= I915_READ(reg
);
2389 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2390 temp
|= snb_b_fdi_train_param
[i
];
2391 I915_WRITE(reg
, temp
);
2396 for (retry
= 0; retry
< 5; retry
++) {
2397 reg
= FDI_RX_IIR(pipe
);
2398 temp
= I915_READ(reg
);
2399 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2400 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2401 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2402 DRM_DEBUG_KMS("FDI train 2 done.\n");
2411 DRM_ERROR("FDI train 2 fail!\n");
2413 DRM_DEBUG_KMS("FDI train done.\n");
2416 /* Manual link training for Ivy Bridge A0 parts */
2417 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
2419 struct drm_device
*dev
= crtc
->dev
;
2420 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2421 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2422 int pipe
= intel_crtc
->pipe
;
2425 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2427 reg
= FDI_RX_IMR(pipe
);
2428 temp
= I915_READ(reg
);
2429 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2430 temp
&= ~FDI_RX_BIT_LOCK
;
2431 I915_WRITE(reg
, temp
);
2436 /* enable CPU FDI TX and PCH FDI RX */
2437 reg
= FDI_TX_CTL(pipe
);
2438 temp
= I915_READ(reg
);
2440 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2441 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
2442 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
2443 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2444 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2445 temp
|= FDI_COMPOSITE_SYNC
;
2446 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2448 reg
= FDI_RX_CTL(pipe
);
2449 temp
= I915_READ(reg
);
2450 temp
&= ~FDI_LINK_TRAIN_AUTO
;
2451 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2452 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2453 temp
|= FDI_COMPOSITE_SYNC
;
2454 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2459 if (HAS_PCH_CPT(dev
))
2460 cpt_phase_pointer_enable(dev
, pipe
);
2462 for (i
= 0; i
< 4; i
++) {
2463 reg
= FDI_TX_CTL(pipe
);
2464 temp
= I915_READ(reg
);
2465 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2466 temp
|= snb_b_fdi_train_param
[i
];
2467 I915_WRITE(reg
, temp
);
2472 reg
= FDI_RX_IIR(pipe
);
2473 temp
= I915_READ(reg
);
2474 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2476 if (temp
& FDI_RX_BIT_LOCK
||
2477 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
2478 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2479 DRM_DEBUG_KMS("FDI train 1 done.\n");
2484 DRM_ERROR("FDI train 1 fail!\n");
2487 reg
= FDI_TX_CTL(pipe
);
2488 temp
= I915_READ(reg
);
2489 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2490 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
2491 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2492 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2493 I915_WRITE(reg
, temp
);
2495 reg
= FDI_RX_CTL(pipe
);
2496 temp
= I915_READ(reg
);
2497 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2498 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2499 I915_WRITE(reg
, temp
);
2504 for (i
= 0; i
< 4; i
++) {
2505 reg
= FDI_TX_CTL(pipe
);
2506 temp
= I915_READ(reg
);
2507 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2508 temp
|= snb_b_fdi_train_param
[i
];
2509 I915_WRITE(reg
, temp
);
2514 reg
= FDI_RX_IIR(pipe
);
2515 temp
= I915_READ(reg
);
2516 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2518 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2519 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2520 DRM_DEBUG_KMS("FDI train 2 done.\n");
2525 DRM_ERROR("FDI train 2 fail!\n");
2527 DRM_DEBUG_KMS("FDI train done.\n");
2530 static void ironlake_fdi_pll_enable(struct drm_crtc
*crtc
)
2532 struct drm_device
*dev
= crtc
->dev
;
2533 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2534 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2535 int pipe
= intel_crtc
->pipe
;
2538 /* Write the TU size bits so error detection works */
2539 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
2540 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
2542 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2543 reg
= FDI_RX_CTL(pipe
);
2544 temp
= I915_READ(reg
);
2545 temp
&= ~((0x7 << 19) | (0x7 << 16));
2546 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2547 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) << 11;
2548 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
2553 /* Switch from Rawclk to PCDclk */
2554 temp
= I915_READ(reg
);
2555 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
2560 /* On Haswell, the PLL configuration for ports and pipes is handled
2561 * separately, as part of DDI setup */
2562 if (!IS_HASWELL(dev
)) {
2563 /* Enable CPU FDI TX PLL, always on for Ironlake */
2564 reg
= FDI_TX_CTL(pipe
);
2565 temp
= I915_READ(reg
);
2566 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
2567 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
2575 static void cpt_phase_pointer_disable(struct drm_device
*dev
, int pipe
)
2577 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2578 u32 flags
= I915_READ(SOUTH_CHICKEN1
);
2580 flags
&= ~(FDI_PHASE_SYNC_EN(pipe
));
2581 I915_WRITE(SOUTH_CHICKEN1
, flags
); /* once to disable... */
2582 flags
&= ~(FDI_PHASE_SYNC_OVR(pipe
));
2583 I915_WRITE(SOUTH_CHICKEN1
, flags
); /* then again to lock */
2584 POSTING_READ(SOUTH_CHICKEN1
);
2586 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
2588 struct drm_device
*dev
= crtc
->dev
;
2589 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2590 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2591 int pipe
= intel_crtc
->pipe
;
2594 /* disable CPU FDI tx and PCH FDI rx */
2595 reg
= FDI_TX_CTL(pipe
);
2596 temp
= I915_READ(reg
);
2597 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
2600 reg
= FDI_RX_CTL(pipe
);
2601 temp
= I915_READ(reg
);
2602 temp
&= ~(0x7 << 16);
2603 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) << 11;
2604 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
2609 /* Ironlake workaround, disable clock pointer after downing FDI */
2610 if (HAS_PCH_IBX(dev
)) {
2611 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2612 I915_WRITE(FDI_RX_CHICKEN(pipe
),
2613 I915_READ(FDI_RX_CHICKEN(pipe
) &
2614 ~FDI_RX_PHASE_SYNC_POINTER_EN
));
2615 } else if (HAS_PCH_CPT(dev
)) {
2616 cpt_phase_pointer_disable(dev
, pipe
);
2619 /* still set train pattern 1 */
2620 reg
= FDI_TX_CTL(pipe
);
2621 temp
= I915_READ(reg
);
2622 temp
&= ~FDI_LINK_TRAIN_NONE
;
2623 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2624 I915_WRITE(reg
, temp
);
2626 reg
= FDI_RX_CTL(pipe
);
2627 temp
= I915_READ(reg
);
2628 if (HAS_PCH_CPT(dev
)) {
2629 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2630 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2632 temp
&= ~FDI_LINK_TRAIN_NONE
;
2633 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2635 /* BPC in FDI rx is consistent with that in PIPECONF */
2636 temp
&= ~(0x07 << 16);
2637 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) << 11;
2638 I915_WRITE(reg
, temp
);
2644 static void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
2646 struct drm_device
*dev
= crtc
->dev
;
2648 if (crtc
->fb
== NULL
)
2651 mutex_lock(&dev
->struct_mutex
);
2652 intel_finish_fb(crtc
->fb
);
2653 mutex_unlock(&dev
->struct_mutex
);
2656 static bool intel_crtc_driving_pch(struct drm_crtc
*crtc
)
2658 struct drm_device
*dev
= crtc
->dev
;
2659 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
2660 struct intel_encoder
*encoder
;
2663 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2664 * must be driven by its own crtc; no sharing is possible.
2666 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
) {
2667 if (encoder
->base
.crtc
!= crtc
)
2670 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2671 * CPU handles all others */
2672 if (IS_HASWELL(dev
)) {
2673 /* It is still unclear how this will work on PPT, so throw up a warning */
2674 WARN_ON(!HAS_PCH_LPT(dev
));
2676 if (encoder
->type
== DRM_MODE_ENCODER_DAC
) {
2677 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2680 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
2686 switch (encoder
->type
) {
2687 case INTEL_OUTPUT_EDP
:
2688 if (!intel_encoder_is_pch_edp(&encoder
->base
))
2697 /* Program iCLKIP clock to the desired frequency */
2698 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
2700 struct drm_device
*dev
= crtc
->dev
;
2701 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2702 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
2705 /* It is necessary to ungate the pixclk gate prior to programming
2706 * the divisors, and gate it back when it is done.
2708 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
2710 /* Disable SSCCTL */
2711 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
2712 intel_sbi_read(dev_priv
, SBI_SSCCTL6
) |
2713 SBI_SSCCTL_DISABLE
);
2715 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2716 if (crtc
->mode
.clock
== 20000) {
2721 /* The iCLK virtual clock root frequency is in MHz,
2722 * but the crtc->mode.clock in in KHz. To get the divisors,
2723 * it is necessary to divide one by another, so we
2724 * convert the virtual clock precision to KHz here for higher
2727 u32 iclk_virtual_root_freq
= 172800 * 1000;
2728 u32 iclk_pi_range
= 64;
2729 u32 desired_divisor
, msb_divisor_value
, pi_value
;
2731 desired_divisor
= (iclk_virtual_root_freq
/ crtc
->mode
.clock
);
2732 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
2733 pi_value
= desired_divisor
% iclk_pi_range
;
2736 divsel
= msb_divisor_value
- 2;
2737 phaseinc
= pi_value
;
2740 /* This should not happen with any sane values */
2741 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
2742 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
2743 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
2744 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
2746 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2753 /* Program SSCDIVINTPHASE6 */
2754 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
);
2755 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
2756 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
2757 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
2758 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
2759 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
2760 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
2762 intel_sbi_write(dev_priv
,
2763 SBI_SSCDIVINTPHASE6
,
2766 /* Program SSCAUXDIV */
2767 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
);
2768 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2769 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
2770 intel_sbi_write(dev_priv
,
2775 /* Enable modulator and associated divider */
2776 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
);
2777 temp
&= ~SBI_SSCCTL_DISABLE
;
2778 intel_sbi_write(dev_priv
,
2782 /* Wait for initialization time */
2785 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
2789 * Enable PCH resources required for PCH ports:
2791 * - FDI training & RX/TX
2792 * - update transcoder timings
2793 * - DP transcoding bits
2796 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
2798 struct drm_device
*dev
= crtc
->dev
;
2799 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2800 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2801 int pipe
= intel_crtc
->pipe
;
2804 assert_transcoder_disabled(dev_priv
, pipe
);
2806 /* For PCH output, training FDI link */
2807 dev_priv
->display
.fdi_link_train(crtc
);
2809 intel_enable_pch_pll(intel_crtc
);
2811 if (HAS_PCH_LPT(dev
)) {
2812 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
2813 lpt_program_iclkip(crtc
);
2814 } else if (HAS_PCH_CPT(dev
)) {
2817 temp
= I915_READ(PCH_DPLL_SEL
);
2821 temp
|= TRANSA_DPLL_ENABLE
;
2822 sel
= TRANSA_DPLLB_SEL
;
2825 temp
|= TRANSB_DPLL_ENABLE
;
2826 sel
= TRANSB_DPLLB_SEL
;
2829 temp
|= TRANSC_DPLL_ENABLE
;
2830 sel
= TRANSC_DPLLB_SEL
;
2833 if (intel_crtc
->pch_pll
->pll_reg
== _PCH_DPLL_B
)
2837 I915_WRITE(PCH_DPLL_SEL
, temp
);
2840 /* set transcoder timing, panel must allow it */
2841 assert_panel_unlocked(dev_priv
, pipe
);
2842 I915_WRITE(TRANS_HTOTAL(pipe
), I915_READ(HTOTAL(pipe
)));
2843 I915_WRITE(TRANS_HBLANK(pipe
), I915_READ(HBLANK(pipe
)));
2844 I915_WRITE(TRANS_HSYNC(pipe
), I915_READ(HSYNC(pipe
)));
2846 I915_WRITE(TRANS_VTOTAL(pipe
), I915_READ(VTOTAL(pipe
)));
2847 I915_WRITE(TRANS_VBLANK(pipe
), I915_READ(VBLANK(pipe
)));
2848 I915_WRITE(TRANS_VSYNC(pipe
), I915_READ(VSYNC(pipe
)));
2849 I915_WRITE(TRANS_VSYNCSHIFT(pipe
), I915_READ(VSYNCSHIFT(pipe
)));
2851 if (!IS_HASWELL(dev
))
2852 intel_fdi_normal_train(crtc
);
2854 /* For PCH DP, enable TRANS_DP_CTL */
2855 if (HAS_PCH_CPT(dev
) &&
2856 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
2857 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
2858 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) >> 5;
2859 reg
= TRANS_DP_CTL(pipe
);
2860 temp
= I915_READ(reg
);
2861 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
2862 TRANS_DP_SYNC_MASK
|
2864 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
2865 TRANS_DP_ENH_FRAMING
);
2866 temp
|= bpc
<< 9; /* same format but at 11:9 */
2868 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
2869 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
2870 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
2871 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
2873 switch (intel_trans_dp_port_sel(crtc
)) {
2875 temp
|= TRANS_DP_PORT_SEL_B
;
2878 temp
|= TRANS_DP_PORT_SEL_C
;
2881 temp
|= TRANS_DP_PORT_SEL_D
;
2884 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2885 temp
|= TRANS_DP_PORT_SEL_B
;
2889 I915_WRITE(reg
, temp
);
2892 intel_enable_transcoder(dev_priv
, pipe
);
2895 static void intel_put_pch_pll(struct intel_crtc
*intel_crtc
)
2897 struct intel_pch_pll
*pll
= intel_crtc
->pch_pll
;
2902 if (pll
->refcount
== 0) {
2903 WARN(1, "bad PCH PLL refcount\n");
2908 intel_crtc
->pch_pll
= NULL
;
2911 static struct intel_pch_pll
*intel_get_pch_pll(struct intel_crtc
*intel_crtc
, u32 dpll
, u32 fp
)
2913 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
2914 struct intel_pch_pll
*pll
;
2917 pll
= intel_crtc
->pch_pll
;
2919 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
2920 intel_crtc
->base
.base
.id
, pll
->pll_reg
);
2924 if (HAS_PCH_IBX(dev_priv
->dev
)) {
2925 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
2926 i
= intel_crtc
->pipe
;
2927 pll
= &dev_priv
->pch_plls
[i
];
2929 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
2930 intel_crtc
->base
.base
.id
, pll
->pll_reg
);
2935 for (i
= 0; i
< dev_priv
->num_pch_pll
; i
++) {
2936 pll
= &dev_priv
->pch_plls
[i
];
2938 /* Only want to check enabled timings first */
2939 if (pll
->refcount
== 0)
2942 if (dpll
== (I915_READ(pll
->pll_reg
) & 0x7fffffff) &&
2943 fp
== I915_READ(pll
->fp0_reg
)) {
2944 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
2945 intel_crtc
->base
.base
.id
,
2946 pll
->pll_reg
, pll
->refcount
, pll
->active
);
2952 /* Ok no matching timings, maybe there's a free one? */
2953 for (i
= 0; i
< dev_priv
->num_pch_pll
; i
++) {
2954 pll
= &dev_priv
->pch_plls
[i
];
2955 if (pll
->refcount
== 0) {
2956 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
2957 intel_crtc
->base
.base
.id
, pll
->pll_reg
);
2965 intel_crtc
->pch_pll
= pll
;
2967 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i
, intel_crtc
->pipe
);
2968 prepare
: /* separate function? */
2969 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll
->pll_reg
);
2971 /* Wait for the clocks to stabilize before rewriting the regs */
2972 I915_WRITE(pll
->pll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
2973 POSTING_READ(pll
->pll_reg
);
2976 I915_WRITE(pll
->fp0_reg
, fp
);
2977 I915_WRITE(pll
->pll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
2982 void intel_cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
2984 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2985 int dslreg
= PIPEDSL(pipe
), tc2reg
= TRANS_CHICKEN2(pipe
);
2988 temp
= I915_READ(dslreg
);
2990 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
2991 /* Without this, mode sets may fail silently on FDI */
2992 I915_WRITE(tc2reg
, TRANS_AUTOTRAIN_GEN_STALL_DIS
);
2994 I915_WRITE(tc2reg
, 0);
2995 if (wait_for(I915_READ(dslreg
) != temp
, 5))
2996 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe
);
3000 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
3002 struct drm_device
*dev
= crtc
->dev
;
3003 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3004 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3005 int pipe
= intel_crtc
->pipe
;
3006 int plane
= intel_crtc
->plane
;
3010 if (intel_crtc
->active
)
3013 intel_crtc
->active
= true;
3014 intel_update_watermarks(dev
);
3016 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
3017 temp
= I915_READ(PCH_LVDS
);
3018 if ((temp
& LVDS_PORT_EN
) == 0)
3019 I915_WRITE(PCH_LVDS
, temp
| LVDS_PORT_EN
);
3022 is_pch_port
= intel_crtc_driving_pch(crtc
);
3025 ironlake_fdi_pll_enable(crtc
);
3027 ironlake_fdi_disable(crtc
);
3029 /* Enable panel fitting for LVDS */
3030 if (dev_priv
->pch_pf_size
&&
3031 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) || HAS_eDP
)) {
3032 /* Force use of hard-coded filter coefficients
3033 * as some pre-programmed values are broken,
3036 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
3037 I915_WRITE(PF_WIN_POS(pipe
), dev_priv
->pch_pf_pos
);
3038 I915_WRITE(PF_WIN_SZ(pipe
), dev_priv
->pch_pf_size
);
3042 * On ILK+ LUT must be loaded before the pipe is running but with
3045 intel_crtc_load_lut(crtc
);
3047 intel_enable_pipe(dev_priv
, pipe
, is_pch_port
);
3048 intel_enable_plane(dev_priv
, plane
, pipe
);
3051 ironlake_pch_enable(crtc
);
3053 mutex_lock(&dev
->struct_mutex
);
3054 intel_update_fbc(dev
);
3055 mutex_unlock(&dev
->struct_mutex
);
3057 intel_crtc_update_cursor(crtc
, true);
3060 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
3062 struct drm_device
*dev
= crtc
->dev
;
3063 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3064 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3065 int pipe
= intel_crtc
->pipe
;
3066 int plane
= intel_crtc
->plane
;
3069 if (!intel_crtc
->active
)
3072 intel_crtc_wait_for_pending_flips(crtc
);
3073 drm_vblank_off(dev
, pipe
);
3074 intel_crtc_update_cursor(crtc
, false);
3076 intel_disable_plane(dev_priv
, plane
, pipe
);
3078 if (dev_priv
->cfb_plane
== plane
)
3079 intel_disable_fbc(dev
);
3081 intel_disable_pipe(dev_priv
, pipe
);
3084 I915_WRITE(PF_CTL(pipe
), 0);
3085 I915_WRITE(PF_WIN_SZ(pipe
), 0);
3087 ironlake_fdi_disable(crtc
);
3089 /* This is a horrible layering violation; we should be doing this in
3090 * the connector/encoder ->prepare instead, but we don't always have
3091 * enough information there about the config to know whether it will
3092 * actually be necessary or just cause undesired flicker.
3094 intel_disable_pch_ports(dev_priv
, pipe
);
3096 intel_disable_transcoder(dev_priv
, pipe
);
3098 if (HAS_PCH_CPT(dev
)) {
3099 /* disable TRANS_DP_CTL */
3100 reg
= TRANS_DP_CTL(pipe
);
3101 temp
= I915_READ(reg
);
3102 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
| TRANS_DP_PORT_SEL_MASK
);
3103 temp
|= TRANS_DP_PORT_SEL_NONE
;
3104 I915_WRITE(reg
, temp
);
3106 /* disable DPLL_SEL */
3107 temp
= I915_READ(PCH_DPLL_SEL
);
3110 temp
&= ~(TRANSA_DPLL_ENABLE
| TRANSA_DPLLB_SEL
);
3113 temp
&= ~(TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
);
3116 /* C shares PLL A or B */
3117 temp
&= ~(TRANSC_DPLL_ENABLE
| TRANSC_DPLLB_SEL
);
3122 I915_WRITE(PCH_DPLL_SEL
, temp
);
3125 /* disable PCH DPLL */
3126 intel_disable_pch_pll(intel_crtc
);
3128 /* Switch from PCDclk to Rawclk */
3129 reg
= FDI_RX_CTL(pipe
);
3130 temp
= I915_READ(reg
);
3131 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
3133 /* Disable CPU FDI TX PLL */
3134 reg
= FDI_TX_CTL(pipe
);
3135 temp
= I915_READ(reg
);
3136 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
3141 reg
= FDI_RX_CTL(pipe
);
3142 temp
= I915_READ(reg
);
3143 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
3145 /* Wait for the clocks to turn off. */
3149 intel_crtc
->active
= false;
3150 intel_update_watermarks(dev
);
3152 mutex_lock(&dev
->struct_mutex
);
3153 intel_update_fbc(dev
);
3154 mutex_unlock(&dev
->struct_mutex
);
3157 static void ironlake_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
3159 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3160 int pipe
= intel_crtc
->pipe
;
3161 int plane
= intel_crtc
->plane
;
3163 /* XXX: When our outputs are all unaware of DPMS modes other than off
3164 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3167 case DRM_MODE_DPMS_ON
:
3168 case DRM_MODE_DPMS_STANDBY
:
3169 case DRM_MODE_DPMS_SUSPEND
:
3170 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe
, plane
);
3171 ironlake_crtc_enable(crtc
);
3174 case DRM_MODE_DPMS_OFF
:
3175 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe
, plane
);
3176 ironlake_crtc_disable(crtc
);
3181 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
3183 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3184 intel_put_pch_pll(intel_crtc
);
3187 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
3189 if (!enable
&& intel_crtc
->overlay
) {
3190 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3191 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3193 mutex_lock(&dev
->struct_mutex
);
3194 dev_priv
->mm
.interruptible
= false;
3195 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
3196 dev_priv
->mm
.interruptible
= true;
3197 mutex_unlock(&dev
->struct_mutex
);
3200 /* Let userspace switch the overlay on again. In most cases userspace
3201 * has to recompute where to put it anyway.
3205 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
3207 struct drm_device
*dev
= crtc
->dev
;
3208 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3209 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3210 int pipe
= intel_crtc
->pipe
;
3211 int plane
= intel_crtc
->plane
;
3213 if (intel_crtc
->active
)
3216 intel_crtc
->active
= true;
3217 intel_update_watermarks(dev
);
3219 intel_enable_pll(dev_priv
, pipe
);
3220 intel_enable_pipe(dev_priv
, pipe
, false);
3221 intel_enable_plane(dev_priv
, plane
, pipe
);
3223 intel_crtc_load_lut(crtc
);
3224 intel_update_fbc(dev
);
3226 /* Give the overlay scaler a chance to enable if it's on this pipe */
3227 intel_crtc_dpms_overlay(intel_crtc
, true);
3228 intel_crtc_update_cursor(crtc
, true);
3231 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
3233 struct drm_device
*dev
= crtc
->dev
;
3234 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3235 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3236 int pipe
= intel_crtc
->pipe
;
3237 int plane
= intel_crtc
->plane
;
3239 if (!intel_crtc
->active
)
3242 /* Give the overlay scaler a chance to disable if it's on this pipe */
3243 intel_crtc_wait_for_pending_flips(crtc
);
3244 drm_vblank_off(dev
, pipe
);
3245 intel_crtc_dpms_overlay(intel_crtc
, false);
3246 intel_crtc_update_cursor(crtc
, false);
3248 if (dev_priv
->cfb_plane
== plane
)
3249 intel_disable_fbc(dev
);
3251 intel_disable_plane(dev_priv
, plane
, pipe
);
3252 intel_disable_pipe(dev_priv
, pipe
);
3253 intel_disable_pll(dev_priv
, pipe
);
3255 intel_crtc
->active
= false;
3256 intel_update_fbc(dev
);
3257 intel_update_watermarks(dev
);
3260 static void i9xx_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
3262 /* XXX: When our outputs are all unaware of DPMS modes other than off
3263 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3266 case DRM_MODE_DPMS_ON
:
3267 case DRM_MODE_DPMS_STANDBY
:
3268 case DRM_MODE_DPMS_SUSPEND
:
3269 i9xx_crtc_enable(crtc
);
3271 case DRM_MODE_DPMS_OFF
:
3272 i9xx_crtc_disable(crtc
);
3277 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
3282 * Sets the power management mode of the pipe and plane.
3284 static void intel_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
3286 struct drm_device
*dev
= crtc
->dev
;
3287 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3288 struct drm_i915_master_private
*master_priv
;
3289 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3290 int pipe
= intel_crtc
->pipe
;
3293 if (intel_crtc
->dpms_mode
== mode
)
3296 intel_crtc
->dpms_mode
= mode
;
3298 dev_priv
->display
.dpms(crtc
, mode
);
3300 if (!dev
->primary
->master
)
3303 master_priv
= dev
->primary
->master
->driver_priv
;
3304 if (!master_priv
->sarea_priv
)
3307 enabled
= crtc
->enabled
&& mode
!= DRM_MODE_DPMS_OFF
;
3311 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3312 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3315 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3316 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3319 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe
));
3324 static void intel_crtc_disable(struct drm_crtc
*crtc
)
3326 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
3327 struct drm_device
*dev
= crtc
->dev
;
3328 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3330 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_OFF
);
3331 dev_priv
->display
.off(crtc
);
3333 assert_plane_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->plane
);
3334 assert_pipe_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->pipe
);
3337 mutex_lock(&dev
->struct_mutex
);
3338 intel_unpin_fb_obj(to_intel_framebuffer(crtc
->fb
)->obj
);
3339 mutex_unlock(&dev
->struct_mutex
);
3343 /* Prepare for a mode set.
3345 * Note we could be a lot smarter here. We need to figure out which outputs
3346 * will be enabled, which disabled (in short, how the config will changes)
3347 * and perform the minimum necessary steps to accomplish that, e.g. updating
3348 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3349 * panel fitting is in the proper state, etc.
3351 static void i9xx_crtc_prepare(struct drm_crtc
*crtc
)
3353 i9xx_crtc_disable(crtc
);
3356 static void i9xx_crtc_commit(struct drm_crtc
*crtc
)
3358 i9xx_crtc_enable(crtc
);
3361 static void ironlake_crtc_prepare(struct drm_crtc
*crtc
)
3363 ironlake_crtc_disable(crtc
);
3366 static void ironlake_crtc_commit(struct drm_crtc
*crtc
)
3368 ironlake_crtc_enable(crtc
);
3371 void intel_encoder_prepare(struct drm_encoder
*encoder
)
3373 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
3374 /* lvds has its own version of prepare see intel_lvds_prepare */
3375 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_OFF
);
3378 void intel_encoder_commit(struct drm_encoder
*encoder
)
3380 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
3381 struct drm_device
*dev
= encoder
->dev
;
3382 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
3384 /* lvds has its own version of commit see intel_lvds_commit */
3385 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
3387 if (HAS_PCH_CPT(dev
))
3388 intel_cpt_verify_modeset(dev
, intel_crtc
->pipe
);
3391 void intel_encoder_destroy(struct drm_encoder
*encoder
)
3393 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
3395 drm_encoder_cleanup(encoder
);
3396 kfree(intel_encoder
);
3399 static bool intel_crtc_mode_fixup(struct drm_crtc
*crtc
,
3400 struct drm_display_mode
*mode
,
3401 struct drm_display_mode
*adjusted_mode
)
3403 struct drm_device
*dev
= crtc
->dev
;
3405 if (HAS_PCH_SPLIT(dev
)) {
3406 /* FDI link clock is fixed at 2.7G */
3407 if (mode
->clock
* 3 > IRONLAKE_FDI_FREQ
* 4)
3411 /* All interlaced capable intel hw wants timings in frames. Note though
3412 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3413 * timings, so we need to be careful not to clobber these.*/
3414 if (!(adjusted_mode
->private_flags
& INTEL_MODE_CRTC_TIMINGS_SET
))
3415 drm_mode_set_crtcinfo(adjusted_mode
, 0);
3420 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
3422 return 400000; /* FIXME */
3425 static int i945_get_display_clock_speed(struct drm_device
*dev
)
3430 static int i915_get_display_clock_speed(struct drm_device
*dev
)
3435 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
3440 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
3444 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
3446 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
3449 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
3450 case GC_DISPLAY_CLOCK_333_MHZ
:
3453 case GC_DISPLAY_CLOCK_190_200_MHZ
:
3459 static int i865_get_display_clock_speed(struct drm_device
*dev
)
3464 static int i855_get_display_clock_speed(struct drm_device
*dev
)
3467 /* Assume that the hardware is in the high speed state. This
3468 * should be the default.
3470 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
3471 case GC_CLOCK_133_200
:
3472 case GC_CLOCK_100_200
:
3474 case GC_CLOCK_166_250
:
3476 case GC_CLOCK_100_133
:
3480 /* Shouldn't happen */
3484 static int i830_get_display_clock_speed(struct drm_device
*dev
)
3498 fdi_reduce_ratio(u32
*num
, u32
*den
)
3500 while (*num
> 0xffffff || *den
> 0xffffff) {
3507 ironlake_compute_m_n(int bits_per_pixel
, int nlanes
, int pixel_clock
,
3508 int link_clock
, struct fdi_m_n
*m_n
)
3510 m_n
->tu
= 64; /* default size */
3512 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3513 m_n
->gmch_m
= bits_per_pixel
* pixel_clock
;
3514 m_n
->gmch_n
= link_clock
* nlanes
* 8;
3515 fdi_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
3517 m_n
->link_m
= pixel_clock
;
3518 m_n
->link_n
= link_clock
;
3519 fdi_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
3522 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
3524 if (i915_panel_use_ssc
>= 0)
3525 return i915_panel_use_ssc
!= 0;
3526 return dev_priv
->lvds_use_ssc
3527 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
3531 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3532 * @crtc: CRTC structure
3533 * @mode: requested mode
3535 * A pipe may be connected to one or more outputs. Based on the depth of the
3536 * attached framebuffer, choose a good color depth to use on the pipe.
3538 * If possible, match the pipe depth to the fb depth. In some cases, this
3539 * isn't ideal, because the connected output supports a lesser or restricted
3540 * set of depths. Resolve that here:
3541 * LVDS typically supports only 6bpc, so clamp down in that case
3542 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3543 * Displays may support a restricted set as well, check EDID and clamp as
3545 * DP may want to dither down to 6bpc to fit larger modes
3548 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3549 * true if they don't match).
3551 static bool intel_choose_pipe_bpp_dither(struct drm_crtc
*crtc
,
3552 unsigned int *pipe_bpp
,
3553 struct drm_display_mode
*mode
)
3555 struct drm_device
*dev
= crtc
->dev
;
3556 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3557 struct drm_encoder
*encoder
;
3558 struct drm_connector
*connector
;
3559 unsigned int display_bpc
= UINT_MAX
, bpc
;
3561 /* Walk the encoders & connectors on this crtc, get min bpc */
3562 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
3563 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
3565 if (encoder
->crtc
!= crtc
)
3568 if (intel_encoder
->type
== INTEL_OUTPUT_LVDS
) {
3569 unsigned int lvds_bpc
;
3571 if ((I915_READ(PCH_LVDS
) & LVDS_A3_POWER_MASK
) ==
3577 if (lvds_bpc
< display_bpc
) {
3578 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc
, lvds_bpc
);
3579 display_bpc
= lvds_bpc
;
3584 if (intel_encoder
->type
== INTEL_OUTPUT_EDP
) {
3585 /* Use VBT settings if we have an eDP panel */
3586 unsigned int edp_bpc
= dev_priv
->edp
.bpp
/ 3;
3588 if (edp_bpc
< display_bpc
) {
3589 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc
, edp_bpc
);
3590 display_bpc
= edp_bpc
;
3595 /* Not one of the known troublemakers, check the EDID */
3596 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
3598 if (connector
->encoder
!= encoder
)
3601 /* Don't use an invalid EDID bpc value */
3602 if (connector
->display_info
.bpc
&&
3603 connector
->display_info
.bpc
< display_bpc
) {
3604 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc
, connector
->display_info
.bpc
);
3605 display_bpc
= connector
->display_info
.bpc
;
3610 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3611 * through, clamp it down. (Note: >12bpc will be caught below.)
3613 if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
) {
3614 if (display_bpc
> 8 && display_bpc
< 12) {
3615 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
3618 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
3624 if (mode
->private_flags
& INTEL_MODE_DP_FORCE_6BPC
) {
3625 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3630 * We could just drive the pipe at the highest bpc all the time and
3631 * enable dithering as needed, but that costs bandwidth. So choose
3632 * the minimum value that expresses the full color range of the fb but
3633 * also stays within the max display bpc discovered above.
3636 switch (crtc
->fb
->depth
) {
3638 bpc
= 8; /* since we go through a colormap */
3642 bpc
= 6; /* min is 18bpp */
3654 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3655 bpc
= min((unsigned int)8, display_bpc
);
3659 display_bpc
= min(display_bpc
, bpc
);
3661 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3664 *pipe_bpp
= display_bpc
* 3;
3666 return display_bpc
!= bpc
;
3669 static int i9xx_get_refclk(struct drm_crtc
*crtc
, int num_connectors
)
3671 struct drm_device
*dev
= crtc
->dev
;
3672 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3675 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
3676 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
3677 refclk
= dev_priv
->lvds_ssc_freq
* 1000;
3678 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3680 } else if (!IS_GEN2(dev
)) {
3689 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode
*adjusted_mode
,
3690 intel_clock_t
*clock
)
3692 /* SDVO TV has fixed PLL values depend on its clock range,
3693 this mirrors vbios setting. */
3694 if (adjusted_mode
->clock
>= 100000
3695 && adjusted_mode
->clock
< 140500) {
3701 } else if (adjusted_mode
->clock
>= 140500
3702 && adjusted_mode
->clock
<= 200000) {
3711 static void i9xx_update_pll_dividers(struct drm_crtc
*crtc
,
3712 intel_clock_t
*clock
,
3713 intel_clock_t
*reduced_clock
)
3715 struct drm_device
*dev
= crtc
->dev
;
3716 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3717 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3718 int pipe
= intel_crtc
->pipe
;
3721 if (IS_PINEVIEW(dev
)) {
3722 fp
= (1 << clock
->n
) << 16 | clock
->m1
<< 8 | clock
->m2
;
3724 fp2
= (1 << reduced_clock
->n
) << 16 |
3725 reduced_clock
->m1
<< 8 | reduced_clock
->m2
;
3727 fp
= clock
->n
<< 16 | clock
->m1
<< 8 | clock
->m2
;
3729 fp2
= reduced_clock
->n
<< 16 | reduced_clock
->m1
<< 8 |
3733 I915_WRITE(FP0(pipe
), fp
);
3735 intel_crtc
->lowfreq_avail
= false;
3736 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
3737 reduced_clock
&& i915_powersave
) {
3738 I915_WRITE(FP1(pipe
), fp2
);
3739 intel_crtc
->lowfreq_avail
= true;
3741 I915_WRITE(FP1(pipe
), fp
);
3745 static void intel_update_lvds(struct drm_crtc
*crtc
, intel_clock_t
*clock
,
3746 struct drm_display_mode
*adjusted_mode
)
3748 struct drm_device
*dev
= crtc
->dev
;
3749 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3750 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3751 int pipe
= intel_crtc
->pipe
;
3754 temp
= I915_READ(LVDS
);
3755 temp
|= LVDS_PORT_EN
| LVDS_A0A2_CLKA_POWER_UP
;
3757 temp
|= LVDS_PIPEB_SELECT
;
3759 temp
&= ~LVDS_PIPEB_SELECT
;
3761 /* set the corresponsding LVDS_BORDER bit */
3762 temp
|= dev_priv
->lvds_border_bits
;
3763 /* Set the B0-B3 data pairs corresponding to whether we're going to
3764 * set the DPLLs for dual-channel mode or not.
3767 temp
|= LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
;
3769 temp
&= ~(LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
);
3771 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3772 * appropriately here, but we need to look more thoroughly into how
3773 * panels behave in the two modes.
3775 /* set the dithering flag on LVDS as needed */
3776 if (INTEL_INFO(dev
)->gen
>= 4) {
3777 if (dev_priv
->lvds_dither
)
3778 temp
|= LVDS_ENABLE_DITHER
;
3780 temp
&= ~LVDS_ENABLE_DITHER
;
3782 temp
&= ~(LVDS_HSYNC_POLARITY
| LVDS_VSYNC_POLARITY
);
3783 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
3784 temp
|= LVDS_HSYNC_POLARITY
;
3785 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
3786 temp
|= LVDS_VSYNC_POLARITY
;
3787 I915_WRITE(LVDS
, temp
);
3790 static void i9xx_update_pll(struct drm_crtc
*crtc
,
3791 struct drm_display_mode
*mode
,
3792 struct drm_display_mode
*adjusted_mode
,
3793 intel_clock_t
*clock
, intel_clock_t
*reduced_clock
,
3796 struct drm_device
*dev
= crtc
->dev
;
3797 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3798 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3799 int pipe
= intel_crtc
->pipe
;
3803 is_sdvo
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
) ||
3804 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
);
3806 dpll
= DPLL_VGA_MODE_DIS
;
3808 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
3809 dpll
|= DPLLB_MODE_LVDS
;
3811 dpll
|= DPLLB_MODE_DAC_SERIAL
;
3813 int pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
3814 if (pixel_multiplier
> 1) {
3815 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
3816 dpll
|= (pixel_multiplier
- 1) << SDVO_MULTIPLIER_SHIFT_HIRES
;
3818 dpll
|= DPLL_DVO_HIGH_SPEED
;
3820 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
))
3821 dpll
|= DPLL_DVO_HIGH_SPEED
;
3823 /* compute bitmask from p1 value */
3824 if (IS_PINEVIEW(dev
))
3825 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
3827 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
3828 if (IS_G4X(dev
) && reduced_clock
)
3829 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
3831 switch (clock
->p2
) {
3833 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
3836 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
3839 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
3842 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
3845 if (INTEL_INFO(dev
)->gen
>= 4)
3846 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
3848 if (is_sdvo
&& intel_pipe_has_type(crtc
, INTEL_OUTPUT_TVOUT
))
3849 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
3850 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_TVOUT
))
3851 /* XXX: just matching BIOS for now */
3852 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3854 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
3855 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
3856 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
3858 dpll
|= PLL_REF_INPUT_DREFCLK
;
3860 dpll
|= DPLL_VCO_ENABLE
;
3861 I915_WRITE(DPLL(pipe
), dpll
& ~DPLL_VCO_ENABLE
);
3862 POSTING_READ(DPLL(pipe
));
3865 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3866 * This is an exception to the general rule that mode_set doesn't turn
3869 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
3870 intel_update_lvds(crtc
, clock
, adjusted_mode
);
3872 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
))
3873 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
3875 I915_WRITE(DPLL(pipe
), dpll
);
3877 /* Wait for the clocks to stabilize. */
3878 POSTING_READ(DPLL(pipe
));
3881 if (INTEL_INFO(dev
)->gen
>= 4) {
3884 temp
= intel_mode_get_pixel_multiplier(adjusted_mode
);
3886 temp
= (temp
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
3890 I915_WRITE(DPLL_MD(pipe
), temp
);
3892 /* The pixel multiplier can only be updated once the
3893 * DPLL is enabled and the clocks are stable.
3895 * So write it again.
3897 I915_WRITE(DPLL(pipe
), dpll
);
3901 static void i8xx_update_pll(struct drm_crtc
*crtc
,
3902 struct drm_display_mode
*adjusted_mode
,
3903 intel_clock_t
*clock
,
3906 struct drm_device
*dev
= crtc
->dev
;
3907 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3908 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3909 int pipe
= intel_crtc
->pipe
;
3912 dpll
= DPLL_VGA_MODE_DIS
;
3914 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
3915 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
3918 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
3920 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
3922 dpll
|= PLL_P2_DIVIDE_BY_4
;
3925 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_TVOUT
))
3926 /* XXX: just matching BIOS for now */
3927 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3929 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
3930 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
3931 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
3933 dpll
|= PLL_REF_INPUT_DREFCLK
;
3935 dpll
|= DPLL_VCO_ENABLE
;
3936 I915_WRITE(DPLL(pipe
), dpll
& ~DPLL_VCO_ENABLE
);
3937 POSTING_READ(DPLL(pipe
));
3940 I915_WRITE(DPLL(pipe
), dpll
);
3942 /* Wait for the clocks to stabilize. */
3943 POSTING_READ(DPLL(pipe
));
3946 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3947 * This is an exception to the general rule that mode_set doesn't turn
3950 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
3951 intel_update_lvds(crtc
, clock
, adjusted_mode
);
3953 /* The pixel multiplier can only be updated once the
3954 * DPLL is enabled and the clocks are stable.
3956 * So write it again.
3958 I915_WRITE(DPLL(pipe
), dpll
);
3961 static int i9xx_crtc_mode_set(struct drm_crtc
*crtc
,
3962 struct drm_display_mode
*mode
,
3963 struct drm_display_mode
*adjusted_mode
,
3965 struct drm_framebuffer
*old_fb
)
3967 struct drm_device
*dev
= crtc
->dev
;
3968 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3969 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3970 int pipe
= intel_crtc
->pipe
;
3971 int plane
= intel_crtc
->plane
;
3972 int refclk
, num_connectors
= 0;
3973 intel_clock_t clock
, reduced_clock
;
3974 u32 dspcntr
, pipeconf
, vsyncshift
;
3975 bool ok
, has_reduced_clock
= false, is_sdvo
= false;
3976 bool is_lvds
= false, is_tv
= false, is_dp
= false;
3977 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3978 struct intel_encoder
*encoder
;
3979 const intel_limit_t
*limit
;
3982 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
) {
3983 if (encoder
->base
.crtc
!= crtc
)
3986 switch (encoder
->type
) {
3987 case INTEL_OUTPUT_LVDS
:
3990 case INTEL_OUTPUT_SDVO
:
3991 case INTEL_OUTPUT_HDMI
:
3993 if (encoder
->needs_tv_clock
)
3996 case INTEL_OUTPUT_TVOUT
:
3999 case INTEL_OUTPUT_DISPLAYPORT
:
4007 refclk
= i9xx_get_refclk(crtc
, num_connectors
);
4010 * Returns a set of divisors for the desired target clock with the given
4011 * refclk, or FALSE. The returned values represent the clock equation:
4012 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4014 limit
= intel_limit(crtc
, refclk
);
4015 ok
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, NULL
,
4018 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4022 /* Ensure that the cursor is valid for the new mode before changing... */
4023 intel_crtc_update_cursor(crtc
, true);
4025 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
4027 * Ensure we match the reduced clock's P to the target clock.
4028 * If the clocks don't match, we can't switch the display clock
4029 * by using the FP0/FP1. In such case we will disable the LVDS
4030 * downclock feature.
4032 has_reduced_clock
= limit
->find_pll(limit
, crtc
,
4033 dev_priv
->lvds_downclock
,
4039 if (is_sdvo
&& is_tv
)
4040 i9xx_adjust_sdvo_tv_clock(adjusted_mode
, &clock
);
4042 i9xx_update_pll_dividers(crtc
, &clock
, has_reduced_clock
?
4043 &reduced_clock
: NULL
);
4046 i8xx_update_pll(crtc
, adjusted_mode
, &clock
, num_connectors
);
4048 i9xx_update_pll(crtc
, mode
, adjusted_mode
, &clock
,
4049 has_reduced_clock
? &reduced_clock
: NULL
,
4052 /* setup pipeconf */
4053 pipeconf
= I915_READ(PIPECONF(pipe
));
4055 /* Set up the display plane register */
4056 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
4059 dspcntr
&= ~DISPPLANE_SEL_PIPE_MASK
;
4061 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
4063 if (pipe
== 0 && INTEL_INFO(dev
)->gen
< 4) {
4064 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4067 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4071 dev_priv
->display
.get_display_clock_speed(dev
) * 9 / 10)
4072 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
4074 pipeconf
&= ~PIPECONF_DOUBLE_WIDE
;
4077 /* default to 8bpc */
4078 pipeconf
&= ~(PIPECONF_BPP_MASK
| PIPECONF_DITHER_EN
);
4080 if (mode
->private_flags
& INTEL_MODE_DP_FORCE_6BPC
) {
4081 pipeconf
|= PIPECONF_BPP_6
|
4082 PIPECONF_DITHER_EN
|
4083 PIPECONF_DITHER_TYPE_SP
;
4087 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe
== 0 ? 'A' : 'B');
4088 drm_mode_debug_printmodeline(mode
);
4090 if (HAS_PIPE_CXSR(dev
)) {
4091 if (intel_crtc
->lowfreq_avail
) {
4092 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4093 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
4095 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4096 pipeconf
&= ~PIPECONF_CXSR_DOWNCLOCK
;
4100 pipeconf
&= ~PIPECONF_INTERLACE_MASK
;
4101 if (!IS_GEN2(dev
) &&
4102 adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
4103 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
4104 /* the chip adds 2 halflines automatically */
4105 adjusted_mode
->crtc_vtotal
-= 1;
4106 adjusted_mode
->crtc_vblank_end
-= 1;
4107 vsyncshift
= adjusted_mode
->crtc_hsync_start
4108 - adjusted_mode
->crtc_htotal
/2;
4110 pipeconf
|= PIPECONF_PROGRESSIVE
;
4115 I915_WRITE(VSYNCSHIFT(pipe
), vsyncshift
);
4117 I915_WRITE(HTOTAL(pipe
),
4118 (adjusted_mode
->crtc_hdisplay
- 1) |
4119 ((adjusted_mode
->crtc_htotal
- 1) << 16));
4120 I915_WRITE(HBLANK(pipe
),
4121 (adjusted_mode
->crtc_hblank_start
- 1) |
4122 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
4123 I915_WRITE(HSYNC(pipe
),
4124 (adjusted_mode
->crtc_hsync_start
- 1) |
4125 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
4127 I915_WRITE(VTOTAL(pipe
),
4128 (adjusted_mode
->crtc_vdisplay
- 1) |
4129 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
4130 I915_WRITE(VBLANK(pipe
),
4131 (adjusted_mode
->crtc_vblank_start
- 1) |
4132 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
4133 I915_WRITE(VSYNC(pipe
),
4134 (adjusted_mode
->crtc_vsync_start
- 1) |
4135 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
4137 /* pipesrc and dspsize control the size that is scaled from,
4138 * which should always be the user's requested size.
4140 I915_WRITE(DSPSIZE(plane
),
4141 ((mode
->vdisplay
- 1) << 16) |
4142 (mode
->hdisplay
- 1));
4143 I915_WRITE(DSPPOS(plane
), 0);
4144 I915_WRITE(PIPESRC(pipe
),
4145 ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
4147 I915_WRITE(PIPECONF(pipe
), pipeconf
);
4148 POSTING_READ(PIPECONF(pipe
));
4149 intel_enable_pipe(dev_priv
, pipe
, false);
4151 intel_wait_for_vblank(dev
, pipe
);
4153 I915_WRITE(DSPCNTR(plane
), dspcntr
);
4154 POSTING_READ(DSPCNTR(plane
));
4156 ret
= intel_pipe_set_base(crtc
, x
, y
, old_fb
);
4158 intel_update_watermarks(dev
);
4164 * Initialize reference clocks when the driver loads
4166 void ironlake_init_pch_refclk(struct drm_device
*dev
)
4168 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4169 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
4170 struct intel_encoder
*encoder
;
4172 bool has_lvds
= false;
4173 bool has_cpu_edp
= false;
4174 bool has_pch_edp
= false;
4175 bool has_panel
= false;
4176 bool has_ck505
= false;
4177 bool can_ssc
= false;
4179 /* We need to take the global config into account */
4180 list_for_each_entry(encoder
, &mode_config
->encoder_list
,
4182 switch (encoder
->type
) {
4183 case INTEL_OUTPUT_LVDS
:
4187 case INTEL_OUTPUT_EDP
:
4189 if (intel_encoder_is_pch_edp(&encoder
->base
))
4197 if (HAS_PCH_IBX(dev
)) {
4198 has_ck505
= dev_priv
->display_clock_mode
;
4199 can_ssc
= has_ck505
;
4205 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4206 has_panel
, has_lvds
, has_pch_edp
, has_cpu_edp
,
4209 /* Ironlake: try to setup display ref clock before DPLL
4210 * enabling. This is only under driver's control after
4211 * PCH B stepping, previous chipset stepping should be
4212 * ignoring this setting.
4214 temp
= I915_READ(PCH_DREF_CONTROL
);
4215 /* Always enable nonspread source */
4216 temp
&= ~DREF_NONSPREAD_SOURCE_MASK
;
4219 temp
|= DREF_NONSPREAD_CK505_ENABLE
;
4221 temp
|= DREF_NONSPREAD_SOURCE_ENABLE
;
4224 temp
&= ~DREF_SSC_SOURCE_MASK
;
4225 temp
|= DREF_SSC_SOURCE_ENABLE
;
4227 /* SSC must be turned on before enabling the CPU output */
4228 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
4229 DRM_DEBUG_KMS("Using SSC on panel\n");
4230 temp
|= DREF_SSC1_ENABLE
;
4232 temp
&= ~DREF_SSC1_ENABLE
;
4234 /* Get SSC going before enabling the outputs */
4235 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4236 POSTING_READ(PCH_DREF_CONTROL
);
4239 temp
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
4241 /* Enable CPU source on CPU attached eDP */
4243 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
4244 DRM_DEBUG_KMS("Using SSC on eDP\n");
4245 temp
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
4248 temp
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
4250 temp
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
4252 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4253 POSTING_READ(PCH_DREF_CONTROL
);
4256 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4258 temp
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
4260 /* Turn off CPU output */
4261 temp
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
4263 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4264 POSTING_READ(PCH_DREF_CONTROL
);
4267 /* Turn off the SSC source */
4268 temp
&= ~DREF_SSC_SOURCE_MASK
;
4269 temp
|= DREF_SSC_SOURCE_DISABLE
;
4272 temp
&= ~ DREF_SSC1_ENABLE
;
4274 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4275 POSTING_READ(PCH_DREF_CONTROL
);
4280 static int ironlake_get_refclk(struct drm_crtc
*crtc
)
4282 struct drm_device
*dev
= crtc
->dev
;
4283 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4284 struct intel_encoder
*encoder
;
4285 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
4286 struct intel_encoder
*edp_encoder
= NULL
;
4287 int num_connectors
= 0;
4288 bool is_lvds
= false;
4290 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
) {
4291 if (encoder
->base
.crtc
!= crtc
)
4294 switch (encoder
->type
) {
4295 case INTEL_OUTPUT_LVDS
:
4298 case INTEL_OUTPUT_EDP
:
4299 edp_encoder
= encoder
;
4305 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
4306 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4307 dev_priv
->lvds_ssc_freq
);
4308 return dev_priv
->lvds_ssc_freq
* 1000;
4314 static int ironlake_crtc_mode_set(struct drm_crtc
*crtc
,
4315 struct drm_display_mode
*mode
,
4316 struct drm_display_mode
*adjusted_mode
,
4318 struct drm_framebuffer
*old_fb
)
4320 struct drm_device
*dev
= crtc
->dev
;
4321 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4322 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4323 int pipe
= intel_crtc
->pipe
;
4324 int plane
= intel_crtc
->plane
;
4325 int refclk
, num_connectors
= 0;
4326 intel_clock_t clock
, reduced_clock
;
4327 u32 dpll
, fp
= 0, fp2
= 0, dspcntr
, pipeconf
;
4328 bool ok
, has_reduced_clock
= false, is_sdvo
= false;
4329 bool is_crt
= false, is_lvds
= false, is_tv
= false, is_dp
= false;
4330 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
4331 struct intel_encoder
*encoder
, *edp_encoder
= NULL
;
4332 const intel_limit_t
*limit
;
4334 struct fdi_m_n m_n
= {0};
4336 int target_clock
, pixel_multiplier
, lane
, link_bw
, factor
;
4337 unsigned int pipe_bpp
;
4339 bool is_cpu_edp
= false, is_pch_edp
= false;
4341 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
) {
4342 if (encoder
->base
.crtc
!= crtc
)
4345 switch (encoder
->type
) {
4346 case INTEL_OUTPUT_LVDS
:
4349 case INTEL_OUTPUT_SDVO
:
4350 case INTEL_OUTPUT_HDMI
:
4352 if (encoder
->needs_tv_clock
)
4355 case INTEL_OUTPUT_TVOUT
:
4358 case INTEL_OUTPUT_ANALOG
:
4361 case INTEL_OUTPUT_DISPLAYPORT
:
4364 case INTEL_OUTPUT_EDP
:
4366 if (intel_encoder_is_pch_edp(&encoder
->base
))
4370 edp_encoder
= encoder
;
4377 refclk
= ironlake_get_refclk(crtc
);
4380 * Returns a set of divisors for the desired target clock with the given
4381 * refclk, or FALSE. The returned values represent the clock equation:
4382 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4384 limit
= intel_limit(crtc
, refclk
);
4385 ok
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, NULL
,
4388 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4392 /* Ensure that the cursor is valid for the new mode before changing... */
4393 intel_crtc_update_cursor(crtc
, true);
4395 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
4397 * Ensure we match the reduced clock's P to the target clock.
4398 * If the clocks don't match, we can't switch the display clock
4399 * by using the FP0/FP1. In such case we will disable the LVDS
4400 * downclock feature.
4402 has_reduced_clock
= limit
->find_pll(limit
, crtc
,
4403 dev_priv
->lvds_downclock
,
4408 /* SDVO TV has fixed PLL values depend on its clock range,
4409 this mirrors vbios setting. */
4410 if (is_sdvo
&& is_tv
) {
4411 if (adjusted_mode
->clock
>= 100000
4412 && adjusted_mode
->clock
< 140500) {
4418 } else if (adjusted_mode
->clock
>= 140500
4419 && adjusted_mode
->clock
<= 200000) {
4429 pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4431 /* CPU eDP doesn't require FDI link, so just set DP M/N
4432 according to current link config */
4434 target_clock
= mode
->clock
;
4435 intel_edp_link_config(edp_encoder
, &lane
, &link_bw
);
4437 /* [e]DP over FDI requires target mode clock
4438 instead of link clock */
4440 target_clock
= mode
->clock
;
4442 target_clock
= adjusted_mode
->clock
;
4444 /* FDI is a binary signal running at ~2.7GHz, encoding
4445 * each output octet as 10 bits. The actual frequency
4446 * is stored as a divider into a 100MHz clock, and the
4447 * mode pixel clock is stored in units of 1KHz.
4448 * Hence the bw of each lane in terms of the mode signal
4451 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
4454 /* determine panel color depth */
4455 temp
= I915_READ(PIPECONF(pipe
));
4456 temp
&= ~PIPE_BPC_MASK
;
4457 dither
= intel_choose_pipe_bpp_dither(crtc
, &pipe_bpp
, mode
);
4472 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4479 intel_crtc
->bpp
= pipe_bpp
;
4480 I915_WRITE(PIPECONF(pipe
), temp
);
4484 * Account for spread spectrum to avoid
4485 * oversubscribing the link. Max center spread
4486 * is 2.5%; use 5% for safety's sake.
4488 u32 bps
= target_clock
* intel_crtc
->bpp
* 21 / 20;
4489 lane
= bps
/ (link_bw
* 8) + 1;
4492 intel_crtc
->fdi_lanes
= lane
;
4494 if (pixel_multiplier
> 1)
4495 link_bw
*= pixel_multiplier
;
4496 ironlake_compute_m_n(intel_crtc
->bpp
, lane
, target_clock
, link_bw
,
4499 fp
= clock
.n
<< 16 | clock
.m1
<< 8 | clock
.m2
;
4500 if (has_reduced_clock
)
4501 fp2
= reduced_clock
.n
<< 16 | reduced_clock
.m1
<< 8 |
4504 /* Enable autotuning of the PLL clock (if permissible) */
4507 if ((intel_panel_use_ssc(dev_priv
) &&
4508 dev_priv
->lvds_ssc_freq
== 100) ||
4509 (I915_READ(PCH_LVDS
) & LVDS_CLKB_POWER_MASK
) == LVDS_CLKB_POWER_UP
)
4511 } else if (is_sdvo
&& is_tv
)
4514 if (clock
.m
< factor
* clock
.n
)
4520 dpll
|= DPLLB_MODE_LVDS
;
4522 dpll
|= DPLLB_MODE_DAC_SERIAL
;
4524 int pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4525 if (pixel_multiplier
> 1) {
4526 dpll
|= (pixel_multiplier
- 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
4528 dpll
|= DPLL_DVO_HIGH_SPEED
;
4530 if (is_dp
&& !is_cpu_edp
)
4531 dpll
|= DPLL_DVO_HIGH_SPEED
;
4533 /* compute bitmask from p1 value */
4534 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4536 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
4540 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
4543 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
4546 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
4549 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
4553 if (is_sdvo
&& is_tv
)
4554 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
4556 /* XXX: just matching BIOS for now */
4557 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4559 else if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4560 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4562 dpll
|= PLL_REF_INPUT_DREFCLK
;
4564 /* setup pipeconf */
4565 pipeconf
= I915_READ(PIPECONF(pipe
));
4567 /* Set up the display plane register */
4568 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
4570 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe
);
4571 drm_mode_debug_printmodeline(mode
);
4573 /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
4574 * pre-Haswell/LPT generation */
4575 if (HAS_PCH_LPT(dev
)) {
4576 DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
4578 } else if (!is_cpu_edp
) {
4579 struct intel_pch_pll
*pll
;
4581 pll
= intel_get_pch_pll(intel_crtc
, dpll
, fp
);
4583 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4588 intel_put_pch_pll(intel_crtc
);
4590 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4591 * This is an exception to the general rule that mode_set doesn't turn
4595 temp
= I915_READ(PCH_LVDS
);
4596 temp
|= LVDS_PORT_EN
| LVDS_A0A2_CLKA_POWER_UP
;
4597 if (HAS_PCH_CPT(dev
)) {
4598 temp
&= ~PORT_TRANS_SEL_MASK
;
4599 temp
|= PORT_TRANS_SEL_CPT(pipe
);
4602 temp
|= LVDS_PIPEB_SELECT
;
4604 temp
&= ~LVDS_PIPEB_SELECT
;
4607 /* set the corresponsding LVDS_BORDER bit */
4608 temp
|= dev_priv
->lvds_border_bits
;
4609 /* Set the B0-B3 data pairs corresponding to whether we're going to
4610 * set the DPLLs for dual-channel mode or not.
4613 temp
|= LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
;
4615 temp
&= ~(LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
);
4617 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4618 * appropriately here, but we need to look more thoroughly into how
4619 * panels behave in the two modes.
4621 temp
&= ~(LVDS_HSYNC_POLARITY
| LVDS_VSYNC_POLARITY
);
4622 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
4623 temp
|= LVDS_HSYNC_POLARITY
;
4624 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
4625 temp
|= LVDS_VSYNC_POLARITY
;
4626 I915_WRITE(PCH_LVDS
, temp
);
4629 pipeconf
&= ~PIPECONF_DITHER_EN
;
4630 pipeconf
&= ~PIPECONF_DITHER_TYPE_MASK
;
4631 if ((is_lvds
&& dev_priv
->lvds_dither
) || dither
) {
4632 pipeconf
|= PIPECONF_DITHER_EN
;
4633 pipeconf
|= PIPECONF_DITHER_TYPE_SP
;
4635 if (is_dp
&& !is_cpu_edp
) {
4636 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
4638 /* For non-DP output, clear any trans DP clock recovery setting.*/
4639 I915_WRITE(TRANSDATA_M1(pipe
), 0);
4640 I915_WRITE(TRANSDATA_N1(pipe
), 0);
4641 I915_WRITE(TRANSDPLINK_M1(pipe
), 0);
4642 I915_WRITE(TRANSDPLINK_N1(pipe
), 0);
4645 if (intel_crtc
->pch_pll
) {
4646 I915_WRITE(intel_crtc
->pch_pll
->pll_reg
, dpll
);
4648 /* Wait for the clocks to stabilize. */
4649 POSTING_READ(intel_crtc
->pch_pll
->pll_reg
);
4652 /* The pixel multiplier can only be updated once the
4653 * DPLL is enabled and the clocks are stable.
4655 * So write it again.
4657 I915_WRITE(intel_crtc
->pch_pll
->pll_reg
, dpll
);
4660 intel_crtc
->lowfreq_avail
= false;
4661 if (intel_crtc
->pch_pll
) {
4662 if (is_lvds
&& has_reduced_clock
&& i915_powersave
) {
4663 I915_WRITE(intel_crtc
->pch_pll
->fp1_reg
, fp2
);
4664 intel_crtc
->lowfreq_avail
= true;
4665 if (HAS_PIPE_CXSR(dev
)) {
4666 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4667 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
4670 I915_WRITE(intel_crtc
->pch_pll
->fp1_reg
, fp
);
4671 if (HAS_PIPE_CXSR(dev
)) {
4672 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4673 pipeconf
&= ~PIPECONF_CXSR_DOWNCLOCK
;
4678 pipeconf
&= ~PIPECONF_INTERLACE_MASK
;
4679 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
4680 pipeconf
|= PIPECONF_INTERLACED_ILK
;
4681 /* the chip adds 2 halflines automatically */
4682 adjusted_mode
->crtc_vtotal
-= 1;
4683 adjusted_mode
->crtc_vblank_end
-= 1;
4684 I915_WRITE(VSYNCSHIFT(pipe
),
4685 adjusted_mode
->crtc_hsync_start
4686 - adjusted_mode
->crtc_htotal
/2);
4688 pipeconf
|= PIPECONF_PROGRESSIVE
;
4689 I915_WRITE(VSYNCSHIFT(pipe
), 0);
4692 I915_WRITE(HTOTAL(pipe
),
4693 (adjusted_mode
->crtc_hdisplay
- 1) |
4694 ((adjusted_mode
->crtc_htotal
- 1) << 16));
4695 I915_WRITE(HBLANK(pipe
),
4696 (adjusted_mode
->crtc_hblank_start
- 1) |
4697 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
4698 I915_WRITE(HSYNC(pipe
),
4699 (adjusted_mode
->crtc_hsync_start
- 1) |
4700 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
4702 I915_WRITE(VTOTAL(pipe
),
4703 (adjusted_mode
->crtc_vdisplay
- 1) |
4704 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
4705 I915_WRITE(VBLANK(pipe
),
4706 (adjusted_mode
->crtc_vblank_start
- 1) |
4707 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
4708 I915_WRITE(VSYNC(pipe
),
4709 (adjusted_mode
->crtc_vsync_start
- 1) |
4710 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
4712 /* pipesrc controls the size that is scaled from, which should
4713 * always be the user's requested size.
4715 I915_WRITE(PIPESRC(pipe
),
4716 ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
4718 I915_WRITE(PIPE_DATA_M1(pipe
), TU_SIZE(m_n
.tu
) | m_n
.gmch_m
);
4719 I915_WRITE(PIPE_DATA_N1(pipe
), m_n
.gmch_n
);
4720 I915_WRITE(PIPE_LINK_M1(pipe
), m_n
.link_m
);
4721 I915_WRITE(PIPE_LINK_N1(pipe
), m_n
.link_n
);
4724 ironlake_set_pll_edp(crtc
, adjusted_mode
->clock
);
4726 I915_WRITE(PIPECONF(pipe
), pipeconf
);
4727 POSTING_READ(PIPECONF(pipe
));
4729 intel_wait_for_vblank(dev
, pipe
);
4731 I915_WRITE(DSPCNTR(plane
), dspcntr
);
4732 POSTING_READ(DSPCNTR(plane
));
4734 ret
= intel_pipe_set_base(crtc
, x
, y
, old_fb
);
4736 intel_update_watermarks(dev
);
4738 intel_update_linetime_watermarks(dev
, pipe
, adjusted_mode
);
4743 static int intel_crtc_mode_set(struct drm_crtc
*crtc
,
4744 struct drm_display_mode
*mode
,
4745 struct drm_display_mode
*adjusted_mode
,
4747 struct drm_framebuffer
*old_fb
)
4749 struct drm_device
*dev
= crtc
->dev
;
4750 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4751 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4752 int pipe
= intel_crtc
->pipe
;
4755 drm_vblank_pre_modeset(dev
, pipe
);
4757 ret
= dev_priv
->display
.crtc_mode_set(crtc
, mode
, adjusted_mode
,
4759 drm_vblank_post_modeset(dev
, pipe
);
4762 intel_crtc
->dpms_mode
= DRM_MODE_DPMS_OFF
;
4764 intel_crtc
->dpms_mode
= DRM_MODE_DPMS_ON
;
4769 static bool intel_eld_uptodate(struct drm_connector
*connector
,
4770 int reg_eldv
, uint32_t bits_eldv
,
4771 int reg_elda
, uint32_t bits_elda
,
4774 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
4775 uint8_t *eld
= connector
->eld
;
4778 i
= I915_READ(reg_eldv
);
4787 i
= I915_READ(reg_elda
);
4789 I915_WRITE(reg_elda
, i
);
4791 for (i
= 0; i
< eld
[2]; i
++)
4792 if (I915_READ(reg_edid
) != *((uint32_t *)eld
+ i
))
4798 static void g4x_write_eld(struct drm_connector
*connector
,
4799 struct drm_crtc
*crtc
)
4801 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
4802 uint8_t *eld
= connector
->eld
;
4807 i
= I915_READ(G4X_AUD_VID_DID
);
4809 if (i
== INTEL_AUDIO_DEVBLC
|| i
== INTEL_AUDIO_DEVCL
)
4810 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
4812 eldv
= G4X_ELDV_DEVCTG
;
4814 if (intel_eld_uptodate(connector
,
4815 G4X_AUD_CNTL_ST
, eldv
,
4816 G4X_AUD_CNTL_ST
, G4X_ELD_ADDR
,
4817 G4X_HDMIW_HDMIEDID
))
4820 i
= I915_READ(G4X_AUD_CNTL_ST
);
4821 i
&= ~(eldv
| G4X_ELD_ADDR
);
4822 len
= (i
>> 9) & 0x1f; /* ELD buffer size */
4823 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
4828 len
= min_t(uint8_t, eld
[2], len
);
4829 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
4830 for (i
= 0; i
< len
; i
++)
4831 I915_WRITE(G4X_HDMIW_HDMIEDID
, *((uint32_t *)eld
+ i
));
4833 i
= I915_READ(G4X_AUD_CNTL_ST
);
4835 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
4838 static void ironlake_write_eld(struct drm_connector
*connector
,
4839 struct drm_crtc
*crtc
)
4841 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
4842 uint8_t *eld
= connector
->eld
;
4851 if (HAS_PCH_IBX(connector
->dev
)) {
4852 hdmiw_hdmiedid
= IBX_HDMIW_HDMIEDID_A
;
4853 aud_config
= IBX_AUD_CONFIG_A
;
4854 aud_cntl_st
= IBX_AUD_CNTL_ST_A
;
4855 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
4857 hdmiw_hdmiedid
= CPT_HDMIW_HDMIEDID_A
;
4858 aud_config
= CPT_AUD_CONFIG_A
;
4859 aud_cntl_st
= CPT_AUD_CNTL_ST_A
;
4860 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
4863 i
= to_intel_crtc(crtc
)->pipe
;
4864 hdmiw_hdmiedid
+= i
* 0x100;
4865 aud_cntl_st
+= i
* 0x100;
4866 aud_config
+= i
* 0x100;
4868 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i
));
4870 i
= I915_READ(aud_cntl_st
);
4871 i
= (i
>> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
4873 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
4874 /* operate blindly on all ports */
4875 eldv
= IBX_ELD_VALIDB
;
4876 eldv
|= IBX_ELD_VALIDB
<< 4;
4877 eldv
|= IBX_ELD_VALIDB
<< 8;
4879 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i
);
4880 eldv
= IBX_ELD_VALIDB
<< ((i
- 1) * 4);
4883 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
4884 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
4885 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
4886 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
4888 I915_WRITE(aud_config
, 0);
4890 if (intel_eld_uptodate(connector
,
4891 aud_cntrl_st2
, eldv
,
4892 aud_cntl_st
, IBX_ELD_ADDRESS
,
4896 i
= I915_READ(aud_cntrl_st2
);
4898 I915_WRITE(aud_cntrl_st2
, i
);
4903 i
= I915_READ(aud_cntl_st
);
4904 i
&= ~IBX_ELD_ADDRESS
;
4905 I915_WRITE(aud_cntl_st
, i
);
4907 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
4908 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
4909 for (i
= 0; i
< len
; i
++)
4910 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
4912 i
= I915_READ(aud_cntrl_st2
);
4914 I915_WRITE(aud_cntrl_st2
, i
);
4917 void intel_write_eld(struct drm_encoder
*encoder
,
4918 struct drm_display_mode
*mode
)
4920 struct drm_crtc
*crtc
= encoder
->crtc
;
4921 struct drm_connector
*connector
;
4922 struct drm_device
*dev
= encoder
->dev
;
4923 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4925 connector
= drm_select_eld(encoder
, mode
);
4929 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
4931 drm_get_connector_name(connector
),
4932 connector
->encoder
->base
.id
,
4933 drm_get_encoder_name(connector
->encoder
));
4935 connector
->eld
[6] = drm_av_sync_delay(connector
, mode
) / 2;
4937 if (dev_priv
->display
.write_eld
)
4938 dev_priv
->display
.write_eld(connector
, crtc
);
4941 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4942 void intel_crtc_load_lut(struct drm_crtc
*crtc
)
4944 struct drm_device
*dev
= crtc
->dev
;
4945 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4946 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4947 int palreg
= PALETTE(intel_crtc
->pipe
);
4950 /* The clocks have to be on to load the palette. */
4951 if (!crtc
->enabled
|| !intel_crtc
->active
)
4954 /* use legacy palette for Ironlake */
4955 if (HAS_PCH_SPLIT(dev
))
4956 palreg
= LGC_PALETTE(intel_crtc
->pipe
);
4958 for (i
= 0; i
< 256; i
++) {
4959 I915_WRITE(palreg
+ 4 * i
,
4960 (intel_crtc
->lut_r
[i
] << 16) |
4961 (intel_crtc
->lut_g
[i
] << 8) |
4962 intel_crtc
->lut_b
[i
]);
4966 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
4968 struct drm_device
*dev
= crtc
->dev
;
4969 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4970 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4971 bool visible
= base
!= 0;
4974 if (intel_crtc
->cursor_visible
== visible
)
4977 cntl
= I915_READ(_CURACNTR
);
4979 /* On these chipsets we can only modify the base whilst
4980 * the cursor is disabled.
4982 I915_WRITE(_CURABASE
, base
);
4984 cntl
&= ~(CURSOR_FORMAT_MASK
);
4985 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4986 cntl
|= CURSOR_ENABLE
|
4987 CURSOR_GAMMA_ENABLE
|
4990 cntl
&= ~(CURSOR_ENABLE
| CURSOR_GAMMA_ENABLE
);
4991 I915_WRITE(_CURACNTR
, cntl
);
4993 intel_crtc
->cursor_visible
= visible
;
4996 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
4998 struct drm_device
*dev
= crtc
->dev
;
4999 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5000 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5001 int pipe
= intel_crtc
->pipe
;
5002 bool visible
= base
!= 0;
5004 if (intel_crtc
->cursor_visible
!= visible
) {
5005 uint32_t cntl
= I915_READ(CURCNTR(pipe
));
5007 cntl
&= ~(CURSOR_MODE
| MCURSOR_PIPE_SELECT
);
5008 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
5009 cntl
|= pipe
<< 28; /* Connect to correct pipe */
5011 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
5012 cntl
|= CURSOR_MODE_DISABLE
;
5014 I915_WRITE(CURCNTR(pipe
), cntl
);
5016 intel_crtc
->cursor_visible
= visible
;
5018 /* and commit changes on next vblank */
5019 I915_WRITE(CURBASE(pipe
), base
);
5022 static void ivb_update_cursor(struct drm_crtc
*crtc
, u32 base
)
5024 struct drm_device
*dev
= crtc
->dev
;
5025 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5026 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5027 int pipe
= intel_crtc
->pipe
;
5028 bool visible
= base
!= 0;
5030 if (intel_crtc
->cursor_visible
!= visible
) {
5031 uint32_t cntl
= I915_READ(CURCNTR_IVB(pipe
));
5033 cntl
&= ~CURSOR_MODE
;
5034 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
5036 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
5037 cntl
|= CURSOR_MODE_DISABLE
;
5039 I915_WRITE(CURCNTR_IVB(pipe
), cntl
);
5041 intel_crtc
->cursor_visible
= visible
;
5043 /* and commit changes on next vblank */
5044 I915_WRITE(CURBASE_IVB(pipe
), base
);
5047 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5048 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
5051 struct drm_device
*dev
= crtc
->dev
;
5052 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5053 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5054 int pipe
= intel_crtc
->pipe
;
5055 int x
= intel_crtc
->cursor_x
;
5056 int y
= intel_crtc
->cursor_y
;
5062 if (on
&& crtc
->enabled
&& crtc
->fb
) {
5063 base
= intel_crtc
->cursor_addr
;
5064 if (x
> (int) crtc
->fb
->width
)
5067 if (y
> (int) crtc
->fb
->height
)
5073 if (x
+ intel_crtc
->cursor_width
< 0)
5076 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
5079 pos
|= x
<< CURSOR_X_SHIFT
;
5082 if (y
+ intel_crtc
->cursor_height
< 0)
5085 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
5088 pos
|= y
<< CURSOR_Y_SHIFT
;
5090 visible
= base
!= 0;
5091 if (!visible
&& !intel_crtc
->cursor_visible
)
5094 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
5095 I915_WRITE(CURPOS_IVB(pipe
), pos
);
5096 ivb_update_cursor(crtc
, base
);
5098 I915_WRITE(CURPOS(pipe
), pos
);
5099 if (IS_845G(dev
) || IS_I865G(dev
))
5100 i845_update_cursor(crtc
, base
);
5102 i9xx_update_cursor(crtc
, base
);
5106 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
5107 struct drm_file
*file
,
5109 uint32_t width
, uint32_t height
)
5111 struct drm_device
*dev
= crtc
->dev
;
5112 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5113 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5114 struct drm_i915_gem_object
*obj
;
5118 DRM_DEBUG_KMS("\n");
5120 /* if we want to turn off the cursor ignore width and height */
5122 DRM_DEBUG_KMS("cursor off\n");
5125 mutex_lock(&dev
->struct_mutex
);
5129 /* Currently we only support 64x64 cursors */
5130 if (width
!= 64 || height
!= 64) {
5131 DRM_ERROR("we currently only support 64x64 cursors\n");
5135 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
5136 if (&obj
->base
== NULL
)
5139 if (obj
->base
.size
< width
* height
* 4) {
5140 DRM_ERROR("buffer is to small\n");
5145 /* we only need to pin inside GTT if cursor is non-phy */
5146 mutex_lock(&dev
->struct_mutex
);
5147 if (!dev_priv
->info
->cursor_needs_physical
) {
5148 if (obj
->tiling_mode
) {
5149 DRM_ERROR("cursor cannot be tiled\n");
5154 ret
= i915_gem_object_pin_to_display_plane(obj
, 0, NULL
);
5156 DRM_ERROR("failed to move cursor bo into the GTT\n");
5160 ret
= i915_gem_object_put_fence(obj
);
5162 DRM_ERROR("failed to release fence for cursor");
5166 addr
= obj
->gtt_offset
;
5168 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
5169 ret
= i915_gem_attach_phys_object(dev
, obj
,
5170 (intel_crtc
->pipe
== 0) ? I915_GEM_PHYS_CURSOR_0
: I915_GEM_PHYS_CURSOR_1
,
5173 DRM_ERROR("failed to attach phys object\n");
5176 addr
= obj
->phys_obj
->handle
->busaddr
;
5180 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
5183 if (intel_crtc
->cursor_bo
) {
5184 if (dev_priv
->info
->cursor_needs_physical
) {
5185 if (intel_crtc
->cursor_bo
!= obj
)
5186 i915_gem_detach_phys_object(dev
, intel_crtc
->cursor_bo
);
5188 i915_gem_object_unpin(intel_crtc
->cursor_bo
);
5189 drm_gem_object_unreference(&intel_crtc
->cursor_bo
->base
);
5192 mutex_unlock(&dev
->struct_mutex
);
5194 intel_crtc
->cursor_addr
= addr
;
5195 intel_crtc
->cursor_bo
= obj
;
5196 intel_crtc
->cursor_width
= width
;
5197 intel_crtc
->cursor_height
= height
;
5199 intel_crtc_update_cursor(crtc
, true);
5203 i915_gem_object_unpin(obj
);
5205 mutex_unlock(&dev
->struct_mutex
);
5207 drm_gem_object_unreference_unlocked(&obj
->base
);
5211 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
5213 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5215 intel_crtc
->cursor_x
= x
;
5216 intel_crtc
->cursor_y
= y
;
5218 intel_crtc_update_cursor(crtc
, true);
5223 /** Sets the color ramps on behalf of RandR */
5224 void intel_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
5225 u16 blue
, int regno
)
5227 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5229 intel_crtc
->lut_r
[regno
] = red
>> 8;
5230 intel_crtc
->lut_g
[regno
] = green
>> 8;
5231 intel_crtc
->lut_b
[regno
] = blue
>> 8;
5234 void intel_crtc_fb_gamma_get(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
5235 u16
*blue
, int regno
)
5237 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5239 *red
= intel_crtc
->lut_r
[regno
] << 8;
5240 *green
= intel_crtc
->lut_g
[regno
] << 8;
5241 *blue
= intel_crtc
->lut_b
[regno
] << 8;
5244 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
5245 u16
*blue
, uint32_t start
, uint32_t size
)
5247 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
5248 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5250 for (i
= start
; i
< end
; i
++) {
5251 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
5252 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
5253 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
5256 intel_crtc_load_lut(crtc
);
5260 * Get a pipe with a simple mode set on it for doing load-based monitor
5263 * It will be up to the load-detect code to adjust the pipe as appropriate for
5264 * its requirements. The pipe will be connected to no other encoders.
5266 * Currently this code will only succeed if there is a pipe with no encoders
5267 * configured for it. In the future, it could choose to temporarily disable
5268 * some outputs to free up a pipe for its use.
5270 * \return crtc, or NULL if no pipes are available.
5273 /* VESA 640x480x72Hz mode to set on the pipe */
5274 static struct drm_display_mode load_detect_mode
= {
5275 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
5276 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
5279 static struct drm_framebuffer
*
5280 intel_framebuffer_create(struct drm_device
*dev
,
5281 struct drm_mode_fb_cmd2
*mode_cmd
,
5282 struct drm_i915_gem_object
*obj
)
5284 struct intel_framebuffer
*intel_fb
;
5287 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
5289 drm_gem_object_unreference_unlocked(&obj
->base
);
5290 return ERR_PTR(-ENOMEM
);
5293 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
5295 drm_gem_object_unreference_unlocked(&obj
->base
);
5297 return ERR_PTR(ret
);
5300 return &intel_fb
->base
;
5304 intel_framebuffer_pitch_for_width(int width
, int bpp
)
5306 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
5307 return ALIGN(pitch
, 64);
5311 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
5313 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
5314 return ALIGN(pitch
* mode
->vdisplay
, PAGE_SIZE
);
5317 static struct drm_framebuffer
*
5318 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
5319 struct drm_display_mode
*mode
,
5322 struct drm_i915_gem_object
*obj
;
5323 struct drm_mode_fb_cmd2 mode_cmd
;
5325 obj
= i915_gem_alloc_object(dev
,
5326 intel_framebuffer_size_for_mode(mode
, bpp
));
5328 return ERR_PTR(-ENOMEM
);
5330 mode_cmd
.width
= mode
->hdisplay
;
5331 mode_cmd
.height
= mode
->vdisplay
;
5332 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
5334 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
5336 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
5339 static struct drm_framebuffer
*
5340 mode_fits_in_fbdev(struct drm_device
*dev
,
5341 struct drm_display_mode
*mode
)
5343 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5344 struct drm_i915_gem_object
*obj
;
5345 struct drm_framebuffer
*fb
;
5347 if (dev_priv
->fbdev
== NULL
)
5350 obj
= dev_priv
->fbdev
->ifb
.obj
;
5354 fb
= &dev_priv
->fbdev
->ifb
.base
;
5355 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
5356 fb
->bits_per_pixel
))
5359 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
5365 bool intel_get_load_detect_pipe(struct intel_encoder
*intel_encoder
,
5366 struct drm_connector
*connector
,
5367 struct drm_display_mode
*mode
,
5368 struct intel_load_detect_pipe
*old
)
5370 struct intel_crtc
*intel_crtc
;
5371 struct drm_crtc
*possible_crtc
;
5372 struct drm_encoder
*encoder
= &intel_encoder
->base
;
5373 struct drm_crtc
*crtc
= NULL
;
5374 struct drm_device
*dev
= encoder
->dev
;
5375 struct drm_framebuffer
*old_fb
;
5378 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5379 connector
->base
.id
, drm_get_connector_name(connector
),
5380 encoder
->base
.id
, drm_get_encoder_name(encoder
));
5383 * Algorithm gets a little messy:
5385 * - if the connector already has an assigned crtc, use it (but make
5386 * sure it's on first)
5388 * - try to find the first unused crtc that can drive this connector,
5389 * and use that if we find one
5392 /* See if we already have a CRTC for this connector */
5393 if (encoder
->crtc
) {
5394 crtc
= encoder
->crtc
;
5396 intel_crtc
= to_intel_crtc(crtc
);
5397 old
->dpms_mode
= intel_crtc
->dpms_mode
;
5398 old
->load_detect_temp
= false;
5400 /* Make sure the crtc and connector are running */
5401 if (intel_crtc
->dpms_mode
!= DRM_MODE_DPMS_ON
) {
5402 struct drm_encoder_helper_funcs
*encoder_funcs
;
5403 struct drm_crtc_helper_funcs
*crtc_funcs
;
5405 crtc_funcs
= crtc
->helper_private
;
5406 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
5408 encoder_funcs
= encoder
->helper_private
;
5409 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
5415 /* Find an unused one (if possible) */
5416 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
5418 if (!(encoder
->possible_crtcs
& (1 << i
)))
5420 if (!possible_crtc
->enabled
) {
5421 crtc
= possible_crtc
;
5427 * If we didn't find an unused CRTC, don't use any.
5430 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5434 encoder
->crtc
= crtc
;
5435 connector
->encoder
= encoder
;
5437 intel_crtc
= to_intel_crtc(crtc
);
5438 old
->dpms_mode
= intel_crtc
->dpms_mode
;
5439 old
->load_detect_temp
= true;
5440 old
->release_fb
= NULL
;
5443 mode
= &load_detect_mode
;
5447 /* We need a framebuffer large enough to accommodate all accesses
5448 * that the plane may generate whilst we perform load detection.
5449 * We can not rely on the fbcon either being present (we get called
5450 * during its initialisation to detect all boot displays, or it may
5451 * not even exist) or that it is large enough to satisfy the
5454 crtc
->fb
= mode_fits_in_fbdev(dev
, mode
);
5455 if (crtc
->fb
== NULL
) {
5456 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5457 crtc
->fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
5458 old
->release_fb
= crtc
->fb
;
5460 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5461 if (IS_ERR(crtc
->fb
)) {
5462 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5467 if (!drm_crtc_helper_set_mode(crtc
, mode
, 0, 0, old_fb
)) {
5468 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
5469 if (old
->release_fb
)
5470 old
->release_fb
->funcs
->destroy(old
->release_fb
);
5475 /* let the connector get through one full cycle before testing */
5476 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
5481 void intel_release_load_detect_pipe(struct intel_encoder
*intel_encoder
,
5482 struct drm_connector
*connector
,
5483 struct intel_load_detect_pipe
*old
)
5485 struct drm_encoder
*encoder
= &intel_encoder
->base
;
5486 struct drm_device
*dev
= encoder
->dev
;
5487 struct drm_crtc
*crtc
= encoder
->crtc
;
5488 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
5489 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
5491 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5492 connector
->base
.id
, drm_get_connector_name(connector
),
5493 encoder
->base
.id
, drm_get_encoder_name(encoder
));
5495 if (old
->load_detect_temp
) {
5496 connector
->encoder
= NULL
;
5497 drm_helper_disable_unused_functions(dev
);
5499 if (old
->release_fb
)
5500 old
->release_fb
->funcs
->destroy(old
->release_fb
);
5505 /* Switch crtc and encoder back off if necessary */
5506 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
) {
5507 encoder_funcs
->dpms(encoder
, old
->dpms_mode
);
5508 crtc_funcs
->dpms(crtc
, old
->dpms_mode
);
5512 /* Returns the clock of the currently programmed mode of the given pipe. */
5513 static int intel_crtc_clock_get(struct drm_device
*dev
, struct drm_crtc
*crtc
)
5515 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5516 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5517 int pipe
= intel_crtc
->pipe
;
5518 u32 dpll
= I915_READ(DPLL(pipe
));
5520 intel_clock_t clock
;
5522 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
5523 fp
= I915_READ(FP0(pipe
));
5525 fp
= I915_READ(FP1(pipe
));
5527 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
5528 if (IS_PINEVIEW(dev
)) {
5529 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
5530 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
5532 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
5533 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
5536 if (!IS_GEN2(dev
)) {
5537 if (IS_PINEVIEW(dev
))
5538 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
5539 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
5541 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
5542 DPLL_FPA01_P1_POST_DIV_SHIFT
);
5544 switch (dpll
& DPLL_MODE_MASK
) {
5545 case DPLLB_MODE_DAC_SERIAL
:
5546 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
5549 case DPLLB_MODE_LVDS
:
5550 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
5554 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5555 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
5559 /* XXX: Handle the 100Mhz refclk */
5560 intel_clock(dev
, 96000, &clock
);
5562 bool is_lvds
= (pipe
== 1) && (I915_READ(LVDS
) & LVDS_PORT_EN
);
5565 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
5566 DPLL_FPA01_P1_POST_DIV_SHIFT
);
5569 if ((dpll
& PLL_REF_INPUT_MASK
) ==
5570 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
5571 /* XXX: might not be 66MHz */
5572 intel_clock(dev
, 66000, &clock
);
5574 intel_clock(dev
, 48000, &clock
);
5576 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
5579 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
5580 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
5582 if (dpll
& PLL_P2_DIVIDE_BY_4
)
5587 intel_clock(dev
, 48000, &clock
);
5591 /* XXX: It would be nice to validate the clocks, but we can't reuse
5592 * i830PllIsValid() because it relies on the xf86_config connector
5593 * configuration being accurate, which it isn't necessarily.
5599 /** Returns the currently programmed mode of the given pipe. */
5600 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
5601 struct drm_crtc
*crtc
)
5603 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5604 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5605 int pipe
= intel_crtc
->pipe
;
5606 struct drm_display_mode
*mode
;
5607 int htot
= I915_READ(HTOTAL(pipe
));
5608 int hsync
= I915_READ(HSYNC(pipe
));
5609 int vtot
= I915_READ(VTOTAL(pipe
));
5610 int vsync
= I915_READ(VSYNC(pipe
));
5612 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
5616 mode
->clock
= intel_crtc_clock_get(dev
, crtc
);
5617 mode
->hdisplay
= (htot
& 0xffff) + 1;
5618 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
5619 mode
->hsync_start
= (hsync
& 0xffff) + 1;
5620 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
5621 mode
->vdisplay
= (vtot
& 0xffff) + 1;
5622 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
5623 mode
->vsync_start
= (vsync
& 0xffff) + 1;
5624 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
5626 drm_mode_set_name(mode
);
5631 #define GPU_IDLE_TIMEOUT 500 /* ms */
5633 /* When this timer fires, we've been idle for awhile */
5634 static void intel_gpu_idle_timer(unsigned long arg
)
5636 struct drm_device
*dev
= (struct drm_device
*)arg
;
5637 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5639 if (!list_empty(&dev_priv
->mm
.active_list
)) {
5640 /* Still processing requests, so just re-arm the timer. */
5641 mod_timer(&dev_priv
->idle_timer
, jiffies
+
5642 msecs_to_jiffies(GPU_IDLE_TIMEOUT
));
5646 dev_priv
->busy
= false;
5647 queue_work(dev_priv
->wq
, &dev_priv
->idle_work
);
5650 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
5652 static void intel_crtc_idle_timer(unsigned long arg
)
5654 struct intel_crtc
*intel_crtc
= (struct intel_crtc
*)arg
;
5655 struct drm_crtc
*crtc
= &intel_crtc
->base
;
5656 drm_i915_private_t
*dev_priv
= crtc
->dev
->dev_private
;
5657 struct intel_framebuffer
*intel_fb
;
5659 intel_fb
= to_intel_framebuffer(crtc
->fb
);
5660 if (intel_fb
&& intel_fb
->obj
->active
) {
5661 /* The framebuffer is still being accessed by the GPU. */
5662 mod_timer(&intel_crtc
->idle_timer
, jiffies
+
5663 msecs_to_jiffies(CRTC_IDLE_TIMEOUT
));
5667 intel_crtc
->busy
= false;
5668 queue_work(dev_priv
->wq
, &dev_priv
->idle_work
);
5671 static void intel_increase_pllclock(struct drm_crtc
*crtc
)
5673 struct drm_device
*dev
= crtc
->dev
;
5674 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5675 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5676 int pipe
= intel_crtc
->pipe
;
5677 int dpll_reg
= DPLL(pipe
);
5680 if (HAS_PCH_SPLIT(dev
))
5683 if (!dev_priv
->lvds_downclock_avail
)
5686 dpll
= I915_READ(dpll_reg
);
5687 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
5688 DRM_DEBUG_DRIVER("upclocking LVDS\n");
5690 assert_panel_unlocked(dev_priv
, pipe
);
5692 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
5693 I915_WRITE(dpll_reg
, dpll
);
5694 intel_wait_for_vblank(dev
, pipe
);
5696 dpll
= I915_READ(dpll_reg
);
5697 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
5698 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
5701 /* Schedule downclock */
5702 mod_timer(&intel_crtc
->idle_timer
, jiffies
+
5703 msecs_to_jiffies(CRTC_IDLE_TIMEOUT
));
5706 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
5708 struct drm_device
*dev
= crtc
->dev
;
5709 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5710 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5712 if (HAS_PCH_SPLIT(dev
))
5715 if (!dev_priv
->lvds_downclock_avail
)
5719 * Since this is called by a timer, we should never get here in
5722 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
5723 int pipe
= intel_crtc
->pipe
;
5724 int dpll_reg
= DPLL(pipe
);
5727 DRM_DEBUG_DRIVER("downclocking LVDS\n");
5729 assert_panel_unlocked(dev_priv
, pipe
);
5731 dpll
= I915_READ(dpll_reg
);
5732 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
5733 I915_WRITE(dpll_reg
, dpll
);
5734 intel_wait_for_vblank(dev
, pipe
);
5735 dpll
= I915_READ(dpll_reg
);
5736 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
5737 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
5743 * intel_idle_update - adjust clocks for idleness
5744 * @work: work struct
5746 * Either the GPU or display (or both) went idle. Check the busy status
5747 * here and adjust the CRTC and GPU clocks as necessary.
5749 static void intel_idle_update(struct work_struct
*work
)
5751 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
5753 struct drm_device
*dev
= dev_priv
->dev
;
5754 struct drm_crtc
*crtc
;
5755 struct intel_crtc
*intel_crtc
;
5757 if (!i915_powersave
)
5760 mutex_lock(&dev
->struct_mutex
);
5762 i915_update_gfx_val(dev_priv
);
5764 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
5765 /* Skip inactive CRTCs */
5769 intel_crtc
= to_intel_crtc(crtc
);
5770 if (!intel_crtc
->busy
)
5771 intel_decrease_pllclock(crtc
);
5775 mutex_unlock(&dev
->struct_mutex
);
5779 * intel_mark_busy - mark the GPU and possibly the display busy
5781 * @obj: object we're operating on
5783 * Callers can use this function to indicate that the GPU is busy processing
5784 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
5785 * buffer), we'll also mark the display as busy, so we know to increase its
5788 void intel_mark_busy(struct drm_device
*dev
, struct drm_i915_gem_object
*obj
)
5790 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5791 struct drm_crtc
*crtc
= NULL
;
5792 struct intel_framebuffer
*intel_fb
;
5793 struct intel_crtc
*intel_crtc
;
5795 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
5798 if (!dev_priv
->busy
) {
5799 intel_sanitize_pm(dev
);
5800 dev_priv
->busy
= true;
5802 mod_timer(&dev_priv
->idle_timer
, jiffies
+
5803 msecs_to_jiffies(GPU_IDLE_TIMEOUT
));
5808 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
5812 intel_crtc
= to_intel_crtc(crtc
);
5813 intel_fb
= to_intel_framebuffer(crtc
->fb
);
5814 if (intel_fb
->obj
== obj
) {
5815 if (!intel_crtc
->busy
) {
5816 /* Non-busy -> busy, upclock */
5817 intel_increase_pllclock(crtc
);
5818 intel_crtc
->busy
= true;
5820 /* Busy -> busy, put off timer */
5821 mod_timer(&intel_crtc
->idle_timer
, jiffies
+
5822 msecs_to_jiffies(CRTC_IDLE_TIMEOUT
));
5828 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
5830 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5831 struct drm_device
*dev
= crtc
->dev
;
5832 struct intel_unpin_work
*work
;
5833 unsigned long flags
;
5835 spin_lock_irqsave(&dev
->event_lock
, flags
);
5836 work
= intel_crtc
->unpin_work
;
5837 intel_crtc
->unpin_work
= NULL
;
5838 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
5841 cancel_work_sync(&work
->work
);
5845 drm_crtc_cleanup(crtc
);
5850 static void intel_unpin_work_fn(struct work_struct
*__work
)
5852 struct intel_unpin_work
*work
=
5853 container_of(__work
, struct intel_unpin_work
, work
);
5855 mutex_lock(&work
->dev
->struct_mutex
);
5856 intel_unpin_fb_obj(work
->old_fb_obj
);
5857 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
5858 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
5860 intel_update_fbc(work
->dev
);
5861 mutex_unlock(&work
->dev
->struct_mutex
);
5865 static void do_intel_finish_page_flip(struct drm_device
*dev
,
5866 struct drm_crtc
*crtc
)
5868 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5869 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5870 struct intel_unpin_work
*work
;
5871 struct drm_i915_gem_object
*obj
;
5872 struct drm_pending_vblank_event
*e
;
5873 struct timeval tnow
, tvbl
;
5874 unsigned long flags
;
5876 /* Ignore early vblank irqs */
5877 if (intel_crtc
== NULL
)
5880 do_gettimeofday(&tnow
);
5882 spin_lock_irqsave(&dev
->event_lock
, flags
);
5883 work
= intel_crtc
->unpin_work
;
5884 if (work
== NULL
|| !work
->pending
) {
5885 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
5889 intel_crtc
->unpin_work
= NULL
;
5893 e
->event
.sequence
= drm_vblank_count_and_time(dev
, intel_crtc
->pipe
, &tvbl
);
5895 /* Called before vblank count and timestamps have
5896 * been updated for the vblank interval of flip
5897 * completion? Need to increment vblank count and
5898 * add one videorefresh duration to returned timestamp
5899 * to account for this. We assume this happened if we
5900 * get called over 0.9 frame durations after the last
5901 * timestamped vblank.
5903 * This calculation can not be used with vrefresh rates
5904 * below 5Hz (10Hz to be on the safe side) without
5905 * promoting to 64 integers.
5907 if (10 * (timeval_to_ns(&tnow
) - timeval_to_ns(&tvbl
)) >
5908 9 * crtc
->framedur_ns
) {
5909 e
->event
.sequence
++;
5910 tvbl
= ns_to_timeval(timeval_to_ns(&tvbl
) +
5914 e
->event
.tv_sec
= tvbl
.tv_sec
;
5915 e
->event
.tv_usec
= tvbl
.tv_usec
;
5917 list_add_tail(&e
->base
.link
,
5918 &e
->base
.file_priv
->event_list
);
5919 wake_up_interruptible(&e
->base
.file_priv
->event_wait
);
5922 drm_vblank_put(dev
, intel_crtc
->pipe
);
5924 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
5926 obj
= work
->old_fb_obj
;
5928 atomic_clear_mask(1 << intel_crtc
->plane
,
5929 &obj
->pending_flip
.counter
);
5930 if (atomic_read(&obj
->pending_flip
) == 0)
5931 wake_up(&dev_priv
->pending_flip_queue
);
5933 schedule_work(&work
->work
);
5935 trace_i915_flip_complete(intel_crtc
->plane
, work
->pending_flip_obj
);
5938 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
5940 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5941 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
5943 do_intel_finish_page_flip(dev
, crtc
);
5946 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
5948 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5949 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
5951 do_intel_finish_page_flip(dev
, crtc
);
5954 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
5956 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5957 struct intel_crtc
*intel_crtc
=
5958 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
5959 unsigned long flags
;
5961 spin_lock_irqsave(&dev
->event_lock
, flags
);
5962 if (intel_crtc
->unpin_work
) {
5963 if ((++intel_crtc
->unpin_work
->pending
) > 1)
5964 DRM_ERROR("Prepared flip multiple times\n");
5966 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5968 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
5971 static int intel_gen2_queue_flip(struct drm_device
*dev
,
5972 struct drm_crtc
*crtc
,
5973 struct drm_framebuffer
*fb
,
5974 struct drm_i915_gem_object
*obj
)
5976 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5977 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5978 unsigned long offset
;
5980 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
5983 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
5987 /* Offset into the new buffer for cases of shared fbs between CRTCs */
5988 offset
= crtc
->y
* fb
->pitches
[0] + crtc
->x
* fb
->bits_per_pixel
/8;
5990 ret
= intel_ring_begin(ring
, 6);
5994 /* Can't queue multiple flips, so wait for the previous
5995 * one to finish before executing the next.
5997 if (intel_crtc
->plane
)
5998 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
6000 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
6001 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
6002 intel_ring_emit(ring
, MI_NOOP
);
6003 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
6004 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
6005 intel_ring_emit(ring
, fb
->pitches
[0]);
6006 intel_ring_emit(ring
, obj
->gtt_offset
+ offset
);
6007 intel_ring_emit(ring
, 0); /* aux display base address, unused */
6008 intel_ring_advance(ring
);
6012 intel_unpin_fb_obj(obj
);
6017 static int intel_gen3_queue_flip(struct drm_device
*dev
,
6018 struct drm_crtc
*crtc
,
6019 struct drm_framebuffer
*fb
,
6020 struct drm_i915_gem_object
*obj
)
6022 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6023 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6024 unsigned long offset
;
6026 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
6029 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
6033 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6034 offset
= crtc
->y
* fb
->pitches
[0] + crtc
->x
* fb
->bits_per_pixel
/8;
6036 ret
= intel_ring_begin(ring
, 6);
6040 if (intel_crtc
->plane
)
6041 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
6043 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
6044 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
6045 intel_ring_emit(ring
, MI_NOOP
);
6046 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
6047 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
6048 intel_ring_emit(ring
, fb
->pitches
[0]);
6049 intel_ring_emit(ring
, obj
->gtt_offset
+ offset
);
6050 intel_ring_emit(ring
, MI_NOOP
);
6052 intel_ring_advance(ring
);
6056 intel_unpin_fb_obj(obj
);
6061 static int intel_gen4_queue_flip(struct drm_device
*dev
,
6062 struct drm_crtc
*crtc
,
6063 struct drm_framebuffer
*fb
,
6064 struct drm_i915_gem_object
*obj
)
6066 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6067 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6068 uint32_t pf
, pipesrc
;
6069 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
6072 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
6076 ret
= intel_ring_begin(ring
, 4);
6080 /* i965+ uses the linear or tiled offsets from the
6081 * Display Registers (which do not change across a page-flip)
6082 * so we need only reprogram the base address.
6084 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
6085 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
6086 intel_ring_emit(ring
, fb
->pitches
[0]);
6087 intel_ring_emit(ring
, obj
->gtt_offset
| obj
->tiling_mode
);
6089 /* XXX Enabling the panel-fitter across page-flip is so far
6090 * untested on non-native modes, so ignore it for now.
6091 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6094 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
6095 intel_ring_emit(ring
, pf
| pipesrc
);
6096 intel_ring_advance(ring
);
6100 intel_unpin_fb_obj(obj
);
6105 static int intel_gen6_queue_flip(struct drm_device
*dev
,
6106 struct drm_crtc
*crtc
,
6107 struct drm_framebuffer
*fb
,
6108 struct drm_i915_gem_object
*obj
)
6110 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6111 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6112 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
6113 uint32_t pf
, pipesrc
;
6116 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
6120 ret
= intel_ring_begin(ring
, 4);
6124 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
6125 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
6126 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
6127 intel_ring_emit(ring
, obj
->gtt_offset
);
6129 /* Contrary to the suggestions in the documentation,
6130 * "Enable Panel Fitter" does not seem to be required when page
6131 * flipping with a non-native mode, and worse causes a normal
6133 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6136 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
6137 intel_ring_emit(ring
, pf
| pipesrc
);
6138 intel_ring_advance(ring
);
6142 intel_unpin_fb_obj(obj
);
6148 * On gen7 we currently use the blit ring because (in early silicon at least)
6149 * the render ring doesn't give us interrpts for page flip completion, which
6150 * means clients will hang after the first flip is queued. Fortunately the
6151 * blit ring generates interrupts properly, so use it instead.
6153 static int intel_gen7_queue_flip(struct drm_device
*dev
,
6154 struct drm_crtc
*crtc
,
6155 struct drm_framebuffer
*fb
,
6156 struct drm_i915_gem_object
*obj
)
6158 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6159 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6160 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[BCS
];
6161 uint32_t plane_bit
= 0;
6164 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
6168 switch(intel_crtc
->plane
) {
6170 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
6173 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
6176 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
6179 WARN_ONCE(1, "unknown plane in flip command\n");
6184 ret
= intel_ring_begin(ring
, 4);
6188 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
6189 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
6190 intel_ring_emit(ring
, (obj
->gtt_offset
));
6191 intel_ring_emit(ring
, (MI_NOOP
));
6192 intel_ring_advance(ring
);
6196 intel_unpin_fb_obj(obj
);
6201 static int intel_default_queue_flip(struct drm_device
*dev
,
6202 struct drm_crtc
*crtc
,
6203 struct drm_framebuffer
*fb
,
6204 struct drm_i915_gem_object
*obj
)
6209 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
6210 struct drm_framebuffer
*fb
,
6211 struct drm_pending_vblank_event
*event
)
6213 struct drm_device
*dev
= crtc
->dev
;
6214 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6215 struct intel_framebuffer
*intel_fb
;
6216 struct drm_i915_gem_object
*obj
;
6217 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6218 struct intel_unpin_work
*work
;
6219 unsigned long flags
;
6222 work
= kzalloc(sizeof *work
, GFP_KERNEL
);
6226 work
->event
= event
;
6227 work
->dev
= crtc
->dev
;
6228 intel_fb
= to_intel_framebuffer(crtc
->fb
);
6229 work
->old_fb_obj
= intel_fb
->obj
;
6230 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
6232 ret
= drm_vblank_get(dev
, intel_crtc
->pipe
);
6236 /* We borrow the event spin lock for protecting unpin_work */
6237 spin_lock_irqsave(&dev
->event_lock
, flags
);
6238 if (intel_crtc
->unpin_work
) {
6239 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6241 drm_vblank_put(dev
, intel_crtc
->pipe
);
6243 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6246 intel_crtc
->unpin_work
= work
;
6247 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6249 intel_fb
= to_intel_framebuffer(fb
);
6250 obj
= intel_fb
->obj
;
6252 mutex_lock(&dev
->struct_mutex
);
6254 /* Reference the objects for the scheduled work. */
6255 drm_gem_object_reference(&work
->old_fb_obj
->base
);
6256 drm_gem_object_reference(&obj
->base
);
6260 work
->pending_flip_obj
= obj
;
6262 work
->enable_stall_check
= true;
6264 /* Block clients from rendering to the new back buffer until
6265 * the flip occurs and the object is no longer visible.
6267 atomic_add(1 << intel_crtc
->plane
, &work
->old_fb_obj
->pending_flip
);
6269 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
);
6271 goto cleanup_pending
;
6273 intel_disable_fbc(dev
);
6274 intel_mark_busy(dev
, obj
);
6275 mutex_unlock(&dev
->struct_mutex
);
6277 trace_i915_flip_request(intel_crtc
->plane
, obj
);
6282 atomic_sub(1 << intel_crtc
->plane
, &work
->old_fb_obj
->pending_flip
);
6283 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
6284 drm_gem_object_unreference(&obj
->base
);
6285 mutex_unlock(&dev
->struct_mutex
);
6287 spin_lock_irqsave(&dev
->event_lock
, flags
);
6288 intel_crtc
->unpin_work
= NULL
;
6289 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6291 drm_vblank_put(dev
, intel_crtc
->pipe
);
6298 static void intel_sanitize_modesetting(struct drm_device
*dev
,
6299 int pipe
, int plane
)
6301 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6305 /* Clear any frame start delays used for debugging left by the BIOS */
6308 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
6311 if (HAS_PCH_SPLIT(dev
))
6314 /* Who knows what state these registers were left in by the BIOS or
6317 * If we leave the registers in a conflicting state (e.g. with the
6318 * display plane reading from the other pipe than the one we intend
6319 * to use) then when we attempt to teardown the active mode, we will
6320 * not disable the pipes and planes in the correct order -- leaving
6321 * a plane reading from a disabled pipe and possibly leading to
6322 * undefined behaviour.
6325 reg
= DSPCNTR(plane
);
6326 val
= I915_READ(reg
);
6328 if ((val
& DISPLAY_PLANE_ENABLE
) == 0)
6330 if (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == pipe
)
6333 /* This display plane is active and attached to the other CPU pipe. */
6336 /* Disable the plane and wait for it to stop reading from the pipe. */
6337 intel_disable_plane(dev_priv
, plane
, pipe
);
6338 intel_disable_pipe(dev_priv
, pipe
);
6341 static void intel_crtc_reset(struct drm_crtc
*crtc
)
6343 struct drm_device
*dev
= crtc
->dev
;
6344 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6346 /* Reset flags back to the 'unknown' status so that they
6347 * will be correctly set on the initial modeset.
6349 intel_crtc
->dpms_mode
= -1;
6351 /* We need to fix up any BIOS configuration that conflicts with
6354 intel_sanitize_modesetting(dev
, intel_crtc
->pipe
, intel_crtc
->plane
);
6357 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
6358 .dpms
= intel_crtc_dpms
,
6359 .mode_fixup
= intel_crtc_mode_fixup
,
6360 .mode_set
= intel_crtc_mode_set
,
6361 .mode_set_base
= intel_pipe_set_base
,
6362 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
6363 .load_lut
= intel_crtc_load_lut
,
6364 .disable
= intel_crtc_disable
,
6367 static const struct drm_crtc_funcs intel_crtc_funcs
= {
6368 .reset
= intel_crtc_reset
,
6369 .cursor_set
= intel_crtc_cursor_set
,
6370 .cursor_move
= intel_crtc_cursor_move
,
6371 .gamma_set
= intel_crtc_gamma_set
,
6372 .set_config
= drm_crtc_helper_set_config
,
6373 .destroy
= intel_crtc_destroy
,
6374 .page_flip
= intel_crtc_page_flip
,
6377 static void intel_pch_pll_init(struct drm_device
*dev
)
6379 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6382 if (dev_priv
->num_pch_pll
== 0) {
6383 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
6387 for (i
= 0; i
< dev_priv
->num_pch_pll
; i
++) {
6388 dev_priv
->pch_plls
[i
].pll_reg
= _PCH_DPLL(i
);
6389 dev_priv
->pch_plls
[i
].fp0_reg
= _PCH_FP0(i
);
6390 dev_priv
->pch_plls
[i
].fp1_reg
= _PCH_FP1(i
);
6394 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
6396 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6397 struct intel_crtc
*intel_crtc
;
6400 intel_crtc
= kzalloc(sizeof(struct intel_crtc
) + (INTELFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
6401 if (intel_crtc
== NULL
)
6404 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
6406 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
6407 for (i
= 0; i
< 256; i
++) {
6408 intel_crtc
->lut_r
[i
] = i
;
6409 intel_crtc
->lut_g
[i
] = i
;
6410 intel_crtc
->lut_b
[i
] = i
;
6413 /* Swap pipes & planes for FBC on pre-965 */
6414 intel_crtc
->pipe
= pipe
;
6415 intel_crtc
->plane
= pipe
;
6416 if (IS_MOBILE(dev
) && IS_GEN3(dev
)) {
6417 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
6418 intel_crtc
->plane
= !pipe
;
6421 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
6422 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
6423 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
6424 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
6426 intel_crtc_reset(&intel_crtc
->base
);
6427 intel_crtc
->active
= true; /* force the pipe off on setup_init_config */
6428 intel_crtc
->bpp
= 24; /* default for pre-Ironlake */
6430 if (HAS_PCH_SPLIT(dev
)) {
6431 intel_helper_funcs
.prepare
= ironlake_crtc_prepare
;
6432 intel_helper_funcs
.commit
= ironlake_crtc_commit
;
6434 intel_helper_funcs
.prepare
= i9xx_crtc_prepare
;
6435 intel_helper_funcs
.commit
= i9xx_crtc_commit
;
6438 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
6440 intel_crtc
->busy
= false;
6442 setup_timer(&intel_crtc
->idle_timer
, intel_crtc_idle_timer
,
6443 (unsigned long)intel_crtc
);
6446 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
6447 struct drm_file
*file
)
6449 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
6450 struct drm_mode_object
*drmmode_obj
;
6451 struct intel_crtc
*crtc
;
6453 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
6456 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
6457 DRM_MODE_OBJECT_CRTC
);
6460 DRM_ERROR("no such CRTC id\n");
6464 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
6465 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
6470 static int intel_encoder_clones(struct drm_device
*dev
, int type_mask
)
6472 struct intel_encoder
*encoder
;
6476 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
6477 if (type_mask
& encoder
->clone_mask
)
6478 index_mask
|= (1 << entry
);
6485 static bool has_edp_a(struct drm_device
*dev
)
6487 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6489 if (!IS_MOBILE(dev
))
6492 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
6496 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES
) & ILK_eDP_A_DISABLE
))
6502 static void intel_setup_outputs(struct drm_device
*dev
)
6504 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6505 struct intel_encoder
*encoder
;
6506 bool dpd_is_edp
= false;
6509 has_lvds
= intel_lvds_init(dev
);
6510 if (!has_lvds
&& !HAS_PCH_SPLIT(dev
)) {
6511 /* disable the panel fitter on everything but LVDS */
6512 I915_WRITE(PFIT_CONTROL
, 0);
6515 if (HAS_PCH_SPLIT(dev
)) {
6516 dpd_is_edp
= intel_dpd_is_edp(dev
);
6519 intel_dp_init(dev
, DP_A
);
6521 if (dpd_is_edp
&& (I915_READ(PCH_DP_D
) & DP_DETECTED
))
6522 intel_dp_init(dev
, PCH_DP_D
);
6525 intel_crt_init(dev
);
6527 if (IS_HASWELL(dev
)) {
6530 /* Haswell uses DDI functions to detect digital outputs */
6531 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
6532 /* DDI A only supports eDP */
6534 intel_ddi_init(dev
, PORT_A
);
6536 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
6538 found
= I915_READ(SFUSE_STRAP
);
6540 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
6541 intel_ddi_init(dev
, PORT_B
);
6542 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
6543 intel_ddi_init(dev
, PORT_C
);
6544 if (found
& SFUSE_STRAP_DDID_DETECTED
)
6545 intel_ddi_init(dev
, PORT_D
);
6546 } else if (HAS_PCH_SPLIT(dev
)) {
6549 if (I915_READ(HDMIB
) & PORT_DETECTED
) {
6550 /* PCH SDVOB multiplex with HDMIB */
6551 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
6553 intel_hdmi_init(dev
, HDMIB
);
6554 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
6555 intel_dp_init(dev
, PCH_DP_B
);
6558 if (I915_READ(HDMIC
) & PORT_DETECTED
)
6559 intel_hdmi_init(dev
, HDMIC
);
6561 if (!dpd_is_edp
&& I915_READ(HDMID
) & PORT_DETECTED
)
6562 intel_hdmi_init(dev
, HDMID
);
6564 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
6565 intel_dp_init(dev
, PCH_DP_C
);
6567 if (!dpd_is_edp
&& (I915_READ(PCH_DP_D
) & DP_DETECTED
))
6568 intel_dp_init(dev
, PCH_DP_D
);
6570 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
6573 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
6574 DRM_DEBUG_KMS("probing SDVOB\n");
6575 found
= intel_sdvo_init(dev
, SDVOB
, true);
6576 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
6577 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
6578 intel_hdmi_init(dev
, SDVOB
);
6581 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
)) {
6582 DRM_DEBUG_KMS("probing DP_B\n");
6583 intel_dp_init(dev
, DP_B
);
6587 /* Before G4X SDVOC doesn't have its own detect register */
6589 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
6590 DRM_DEBUG_KMS("probing SDVOC\n");
6591 found
= intel_sdvo_init(dev
, SDVOC
, false);
6594 if (!found
&& (I915_READ(SDVOC
) & SDVO_DETECTED
)) {
6596 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
6597 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
6598 intel_hdmi_init(dev
, SDVOC
);
6600 if (SUPPORTS_INTEGRATED_DP(dev
)) {
6601 DRM_DEBUG_KMS("probing DP_C\n");
6602 intel_dp_init(dev
, DP_C
);
6606 if (SUPPORTS_INTEGRATED_DP(dev
) &&
6607 (I915_READ(DP_D
) & DP_DETECTED
)) {
6608 DRM_DEBUG_KMS("probing DP_D\n");
6609 intel_dp_init(dev
, DP_D
);
6611 } else if (IS_GEN2(dev
))
6612 intel_dvo_init(dev
);
6614 if (SUPPORTS_TV(dev
))
6617 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
6618 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
6619 encoder
->base
.possible_clones
=
6620 intel_encoder_clones(dev
, encoder
->clone_mask
);
6623 /* disable all the possible outputs/crtcs before entering KMS mode */
6624 drm_helper_disable_unused_functions(dev
);
6626 if (HAS_PCH_SPLIT(dev
))
6627 ironlake_init_pch_refclk(dev
);
6630 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
6632 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
6634 drm_framebuffer_cleanup(fb
);
6635 drm_gem_object_unreference_unlocked(&intel_fb
->obj
->base
);
6640 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
6641 struct drm_file
*file
,
6642 unsigned int *handle
)
6644 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
6645 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
6647 return drm_gem_handle_create(file
, &obj
->base
, handle
);
6650 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
6651 .destroy
= intel_user_framebuffer_destroy
,
6652 .create_handle
= intel_user_framebuffer_create_handle
,
6655 int intel_framebuffer_init(struct drm_device
*dev
,
6656 struct intel_framebuffer
*intel_fb
,
6657 struct drm_mode_fb_cmd2
*mode_cmd
,
6658 struct drm_i915_gem_object
*obj
)
6662 if (obj
->tiling_mode
== I915_TILING_Y
)
6665 if (mode_cmd
->pitches
[0] & 63)
6668 switch (mode_cmd
->pixel_format
) {
6669 case DRM_FORMAT_RGB332
:
6670 case DRM_FORMAT_RGB565
:
6671 case DRM_FORMAT_XRGB8888
:
6672 case DRM_FORMAT_XBGR8888
:
6673 case DRM_FORMAT_ARGB8888
:
6674 case DRM_FORMAT_XRGB2101010
:
6675 case DRM_FORMAT_ARGB2101010
:
6676 /* RGB formats are common across chipsets */
6678 case DRM_FORMAT_YUYV
:
6679 case DRM_FORMAT_UYVY
:
6680 case DRM_FORMAT_YVYU
:
6681 case DRM_FORMAT_VYUY
:
6684 DRM_DEBUG_KMS("unsupported pixel format %u\n",
6685 mode_cmd
->pixel_format
);
6689 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
6691 DRM_ERROR("framebuffer init failed %d\n", ret
);
6695 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
6696 intel_fb
->obj
= obj
;
6700 static struct drm_framebuffer
*
6701 intel_user_framebuffer_create(struct drm_device
*dev
,
6702 struct drm_file
*filp
,
6703 struct drm_mode_fb_cmd2
*mode_cmd
)
6705 struct drm_i915_gem_object
*obj
;
6707 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
6708 mode_cmd
->handles
[0]));
6709 if (&obj
->base
== NULL
)
6710 return ERR_PTR(-ENOENT
);
6712 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
6715 static const struct drm_mode_config_funcs intel_mode_funcs
= {
6716 .fb_create
= intel_user_framebuffer_create
,
6717 .output_poll_changed
= intel_fb_output_poll_changed
,
6720 /* Set up chip specific display functions */
6721 static void intel_init_display(struct drm_device
*dev
)
6723 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6725 /* We always want a DPMS function */
6726 if (HAS_PCH_SPLIT(dev
)) {
6727 dev_priv
->display
.dpms
= ironlake_crtc_dpms
;
6728 dev_priv
->display
.crtc_mode_set
= ironlake_crtc_mode_set
;
6729 dev_priv
->display
.off
= ironlake_crtc_off
;
6730 dev_priv
->display
.update_plane
= ironlake_update_plane
;
6732 dev_priv
->display
.dpms
= i9xx_crtc_dpms
;
6733 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
6734 dev_priv
->display
.off
= i9xx_crtc_off
;
6735 dev_priv
->display
.update_plane
= i9xx_update_plane
;
6738 /* Returns the core display clock speed */
6739 if (IS_VALLEYVIEW(dev
))
6740 dev_priv
->display
.get_display_clock_speed
=
6741 valleyview_get_display_clock_speed
;
6742 else if (IS_I945G(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
6743 dev_priv
->display
.get_display_clock_speed
=
6744 i945_get_display_clock_speed
;
6745 else if (IS_I915G(dev
))
6746 dev_priv
->display
.get_display_clock_speed
=
6747 i915_get_display_clock_speed
;
6748 else if (IS_I945GM(dev
) || IS_845G(dev
) || IS_PINEVIEW_M(dev
))
6749 dev_priv
->display
.get_display_clock_speed
=
6750 i9xx_misc_get_display_clock_speed
;
6751 else if (IS_I915GM(dev
))
6752 dev_priv
->display
.get_display_clock_speed
=
6753 i915gm_get_display_clock_speed
;
6754 else if (IS_I865G(dev
))
6755 dev_priv
->display
.get_display_clock_speed
=
6756 i865_get_display_clock_speed
;
6757 else if (IS_I85X(dev
))
6758 dev_priv
->display
.get_display_clock_speed
=
6759 i855_get_display_clock_speed
;
6761 dev_priv
->display
.get_display_clock_speed
=
6762 i830_get_display_clock_speed
;
6764 if (HAS_PCH_SPLIT(dev
)) {
6766 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
6767 dev_priv
->display
.write_eld
= ironlake_write_eld
;
6768 } else if (IS_GEN6(dev
)) {
6769 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
6770 dev_priv
->display
.write_eld
= ironlake_write_eld
;
6771 } else if (IS_IVYBRIDGE(dev
)) {
6772 /* FIXME: detect B0+ stepping and use auto training */
6773 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
6774 dev_priv
->display
.write_eld
= ironlake_write_eld
;
6775 } else if (IS_HASWELL(dev
)) {
6776 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
6777 dev_priv
->display
.write_eld
= ironlake_write_eld
;
6779 dev_priv
->display
.update_wm
= NULL
;
6780 } else if (IS_VALLEYVIEW(dev
)) {
6781 dev_priv
->display
.force_wake_get
= vlv_force_wake_get
;
6782 dev_priv
->display
.force_wake_put
= vlv_force_wake_put
;
6783 } else if (IS_G4X(dev
)) {
6784 dev_priv
->display
.write_eld
= g4x_write_eld
;
6787 /* Default just returns -ENODEV to indicate unsupported */
6788 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
6790 switch (INTEL_INFO(dev
)->gen
) {
6792 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
6796 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
6801 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
6805 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
6808 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
6814 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
6815 * resume, or other times. This quirk makes sure that's the case for
6818 static void quirk_pipea_force(struct drm_device
*dev
)
6820 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6822 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
6823 DRM_INFO("applying pipe a force quirk\n");
6827 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
6829 static void quirk_ssc_force_disable(struct drm_device
*dev
)
6831 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6832 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
6833 DRM_INFO("applying lvds SSC disable quirk\n");
6837 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
6840 static void quirk_invert_brightness(struct drm_device
*dev
)
6842 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6843 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
6844 DRM_INFO("applying inverted panel brightness quirk\n");
6847 struct intel_quirk
{
6849 int subsystem_vendor
;
6850 int subsystem_device
;
6851 void (*hook
)(struct drm_device
*dev
);
6854 static struct intel_quirk intel_quirks
[] = {
6855 /* HP Mini needs pipe A force quirk (LP: #322104) */
6856 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
6858 /* Thinkpad R31 needs pipe A force quirk */
6859 { 0x3577, 0x1014, 0x0505, quirk_pipea_force
},
6860 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
6861 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
6863 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
6864 { 0x3577, 0x1014, 0x0513, quirk_pipea_force
},
6865 /* ThinkPad X40 needs pipe A force quirk */
6867 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6868 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
6870 /* 855 & before need to leave pipe A & dpll A up */
6871 { 0x3582, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
6872 { 0x2562, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
6874 /* Lenovo U160 cannot use SSC on LVDS */
6875 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
6877 /* Sony Vaio Y cannot use SSC on LVDS */
6878 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
6880 /* Acer Aspire 5734Z must invert backlight brightness */
6881 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
6884 static void intel_init_quirks(struct drm_device
*dev
)
6886 struct pci_dev
*d
= dev
->pdev
;
6889 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
6890 struct intel_quirk
*q
= &intel_quirks
[i
];
6892 if (d
->device
== q
->device
&&
6893 (d
->subsystem_vendor
== q
->subsystem_vendor
||
6894 q
->subsystem_vendor
== PCI_ANY_ID
) &&
6895 (d
->subsystem_device
== q
->subsystem_device
||
6896 q
->subsystem_device
== PCI_ANY_ID
))
6901 /* Disable the VGA plane that we never use */
6902 static void i915_disable_vga(struct drm_device
*dev
)
6904 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6908 if (HAS_PCH_SPLIT(dev
))
6909 vga_reg
= CPU_VGACNTRL
;
6913 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
6914 outb(SR01
, VGA_SR_INDEX
);
6915 sr1
= inb(VGA_SR_DATA
);
6916 outb(sr1
| 1<<5, VGA_SR_DATA
);
6917 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
6920 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
6921 POSTING_READ(vga_reg
);
6924 void intel_modeset_init_hw(struct drm_device
*dev
)
6926 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6928 intel_init_clock_gating(dev
);
6930 if (IS_IRONLAKE_M(dev
)) {
6931 ironlake_enable_drps(dev
);
6932 ironlake_enable_rc6(dev
);
6933 intel_init_emon(dev
);
6936 if ((IS_GEN6(dev
) || IS_GEN7(dev
)) && !IS_VALLEYVIEW(dev
)) {
6937 gen6_enable_rps(dev_priv
);
6938 gen6_update_ring_freq(dev_priv
);
6942 void intel_modeset_init(struct drm_device
*dev
)
6944 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6947 drm_mode_config_init(dev
);
6949 dev
->mode_config
.min_width
= 0;
6950 dev
->mode_config
.min_height
= 0;
6952 dev
->mode_config
.preferred_depth
= 24;
6953 dev
->mode_config
.prefer_shadow
= 1;
6955 dev
->mode_config
.funcs
= &intel_mode_funcs
;
6957 intel_init_quirks(dev
);
6961 intel_prepare_ddi(dev
);
6963 intel_init_display(dev
);
6966 dev
->mode_config
.max_width
= 2048;
6967 dev
->mode_config
.max_height
= 2048;
6968 } else if (IS_GEN3(dev
)) {
6969 dev
->mode_config
.max_width
= 4096;
6970 dev
->mode_config
.max_height
= 4096;
6972 dev
->mode_config
.max_width
= 8192;
6973 dev
->mode_config
.max_height
= 8192;
6975 dev
->mode_config
.fb_base
= dev
->agp
->base
;
6977 DRM_DEBUG_KMS("%d display pipe%s available.\n",
6978 dev_priv
->num_pipe
, dev_priv
->num_pipe
> 1 ? "s" : "");
6980 for (i
= 0; i
< dev_priv
->num_pipe
; i
++) {
6981 intel_crtc_init(dev
, i
);
6982 ret
= intel_plane_init(dev
, i
);
6984 DRM_DEBUG_KMS("plane %d init failed: %d\n", i
, ret
);
6987 intel_pch_pll_init(dev
);
6989 /* Just disable it once at startup */
6990 i915_disable_vga(dev
);
6991 intel_setup_outputs(dev
);
6993 INIT_WORK(&dev_priv
->idle_work
, intel_idle_update
);
6994 setup_timer(&dev_priv
->idle_timer
, intel_gpu_idle_timer
,
6995 (unsigned long)dev
);
6998 void intel_modeset_gem_init(struct drm_device
*dev
)
7000 intel_modeset_init_hw(dev
);
7002 intel_setup_overlay(dev
);
7005 void intel_modeset_cleanup(struct drm_device
*dev
)
7007 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7008 struct drm_crtc
*crtc
;
7009 struct intel_crtc
*intel_crtc
;
7011 drm_kms_helper_poll_fini(dev
);
7012 mutex_lock(&dev
->struct_mutex
);
7014 intel_unregister_dsm_handler();
7017 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
7018 /* Skip inactive CRTCs */
7022 intel_crtc
= to_intel_crtc(crtc
);
7023 intel_increase_pllclock(crtc
);
7026 intel_disable_fbc(dev
);
7028 if (IS_IRONLAKE_M(dev
))
7029 ironlake_disable_drps(dev
);
7030 if ((IS_GEN6(dev
) || IS_GEN7(dev
)) && !IS_VALLEYVIEW(dev
))
7031 gen6_disable_rps(dev
);
7033 if (IS_IRONLAKE_M(dev
))
7034 ironlake_disable_rc6(dev
);
7036 if (IS_VALLEYVIEW(dev
))
7039 mutex_unlock(&dev
->struct_mutex
);
7041 /* Disable the irq before mode object teardown, for the irq might
7042 * enqueue unpin/hotplug work. */
7043 drm_irq_uninstall(dev
);
7044 cancel_work_sync(&dev_priv
->hotplug_work
);
7045 cancel_work_sync(&dev_priv
->rps_work
);
7047 /* flush any delayed tasks or pending work */
7048 flush_scheduled_work();
7050 /* Shut off idle work before the crtcs get freed. */
7051 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
7052 intel_crtc
= to_intel_crtc(crtc
);
7053 del_timer_sync(&intel_crtc
->idle_timer
);
7055 del_timer_sync(&dev_priv
->idle_timer
);
7056 cancel_work_sync(&dev_priv
->idle_work
);
7058 drm_mode_config_cleanup(dev
);
7062 * Return which encoder is currently attached for connector.
7064 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
7066 return &intel_attached_encoder(connector
)->base
;
7069 void intel_connector_attach_encoder(struct intel_connector
*connector
,
7070 struct intel_encoder
*encoder
)
7072 connector
->encoder
= encoder
;
7073 drm_mode_connector_attach_encoder(&connector
->base
,
7078 * set vga decode state - true == enable VGA decode
7080 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
7082 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7085 pci_read_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, &gmch_ctrl
);
7087 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
7089 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
7090 pci_write_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, gmch_ctrl
);
7094 #ifdef CONFIG_DEBUG_FS
7095 #include <linux/seq_file.h>
7097 struct intel_display_error_state
{
7098 struct intel_cursor_error_state
{
7105 struct intel_pipe_error_state
{
7117 struct intel_plane_error_state
{
7128 struct intel_display_error_state
*
7129 intel_display_capture_error_state(struct drm_device
*dev
)
7131 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7132 struct intel_display_error_state
*error
;
7135 error
= kmalloc(sizeof(*error
), GFP_ATOMIC
);
7139 for (i
= 0; i
< 2; i
++) {
7140 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
7141 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
7142 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
7144 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
7145 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
7146 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
7147 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
7148 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
7149 if (INTEL_INFO(dev
)->gen
>= 4) {
7150 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
7151 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
7154 error
->pipe
[i
].conf
= I915_READ(PIPECONF(i
));
7155 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
7156 error
->pipe
[i
].htotal
= I915_READ(HTOTAL(i
));
7157 error
->pipe
[i
].hblank
= I915_READ(HBLANK(i
));
7158 error
->pipe
[i
].hsync
= I915_READ(HSYNC(i
));
7159 error
->pipe
[i
].vtotal
= I915_READ(VTOTAL(i
));
7160 error
->pipe
[i
].vblank
= I915_READ(VBLANK(i
));
7161 error
->pipe
[i
].vsync
= I915_READ(VSYNC(i
));
7168 intel_display_print_error_state(struct seq_file
*m
,
7169 struct drm_device
*dev
,
7170 struct intel_display_error_state
*error
)
7174 for (i
= 0; i
< 2; i
++) {
7175 seq_printf(m
, "Pipe [%d]:\n", i
);
7176 seq_printf(m
, " CONF: %08x\n", error
->pipe
[i
].conf
);
7177 seq_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
7178 seq_printf(m
, " HTOTAL: %08x\n", error
->pipe
[i
].htotal
);
7179 seq_printf(m
, " HBLANK: %08x\n", error
->pipe
[i
].hblank
);
7180 seq_printf(m
, " HSYNC: %08x\n", error
->pipe
[i
].hsync
);
7181 seq_printf(m
, " VTOTAL: %08x\n", error
->pipe
[i
].vtotal
);
7182 seq_printf(m
, " VBLANK: %08x\n", error
->pipe
[i
].vblank
);
7183 seq_printf(m
, " VSYNC: %08x\n", error
->pipe
[i
].vsync
);
7185 seq_printf(m
, "Plane [%d]:\n", i
);
7186 seq_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
7187 seq_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
7188 seq_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
7189 seq_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
7190 seq_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
7191 if (INTEL_INFO(dev
)->gen
>= 4) {
7192 seq_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
7193 seq_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
7196 seq_printf(m
, "Cursor [%d]:\n", i
);
7197 seq_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
7198 seq_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
7199 seq_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);