2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
);
45 static void intel_increase_pllclock(struct drm_crtc
*crtc
);
46 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
57 #define INTEL_P2_NUM 2
58 typedef struct intel_limit intel_limit_t
;
60 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
63 * find_pll() - Find the best values for the PLL
64 * @limit: limits for the PLL
66 * @target: target frequency in kHz
67 * @refclk: reference clock frequency in kHz
68 * @match_clock: if provided, @best_clock P divider must
69 * match the P divider from @match_clock
70 * used for LVDS downclocking
71 * @best_clock: best PLL values found
73 * Returns true on success, false on failure.
75 bool (*find_pll
)(const intel_limit_t
*limit
,
76 struct drm_crtc
*crtc
,
77 int target
, int refclk
,
78 intel_clock_t
*match_clock
,
79 intel_clock_t
*best_clock
);
83 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
86 intel_pch_rawclk(struct drm_device
*dev
)
88 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
90 WARN_ON(!HAS_PCH_SPLIT(dev
));
92 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
96 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
97 int target
, int refclk
, intel_clock_t
*match_clock
,
98 intel_clock_t
*best_clock
);
100 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
101 int target
, int refclk
, intel_clock_t
*match_clock
,
102 intel_clock_t
*best_clock
);
105 intel_vlv_find_best_pll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
106 int target
, int refclk
, intel_clock_t
*match_clock
,
107 intel_clock_t
*best_clock
);
109 static inline u32
/* units of 100MHz */
110 intel_fdi_link_freq(struct drm_device
*dev
)
113 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
114 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
119 static const intel_limit_t intel_limits_i8xx_dvo
= {
120 .dot
= { .min
= 25000, .max
= 350000 },
121 .vco
= { .min
= 930000, .max
= 1400000 },
122 .n
= { .min
= 3, .max
= 16 },
123 .m
= { .min
= 96, .max
= 140 },
124 .m1
= { .min
= 18, .max
= 26 },
125 .m2
= { .min
= 6, .max
= 16 },
126 .p
= { .min
= 4, .max
= 128 },
127 .p1
= { .min
= 2, .max
= 33 },
128 .p2
= { .dot_limit
= 165000,
129 .p2_slow
= 4, .p2_fast
= 2 },
130 .find_pll
= intel_find_best_PLL
,
133 static const intel_limit_t intel_limits_i8xx_lvds
= {
134 .dot
= { .min
= 25000, .max
= 350000 },
135 .vco
= { .min
= 930000, .max
= 1400000 },
136 .n
= { .min
= 3, .max
= 16 },
137 .m
= { .min
= 96, .max
= 140 },
138 .m1
= { .min
= 18, .max
= 26 },
139 .m2
= { .min
= 6, .max
= 16 },
140 .p
= { .min
= 4, .max
= 128 },
141 .p1
= { .min
= 1, .max
= 6 },
142 .p2
= { .dot_limit
= 165000,
143 .p2_slow
= 14, .p2_fast
= 7 },
144 .find_pll
= intel_find_best_PLL
,
147 static const intel_limit_t intel_limits_i9xx_sdvo
= {
148 .dot
= { .min
= 20000, .max
= 400000 },
149 .vco
= { .min
= 1400000, .max
= 2800000 },
150 .n
= { .min
= 1, .max
= 6 },
151 .m
= { .min
= 70, .max
= 120 },
152 .m1
= { .min
= 8, .max
= 18 },
153 .m2
= { .min
= 3, .max
= 7 },
154 .p
= { .min
= 5, .max
= 80 },
155 .p1
= { .min
= 1, .max
= 8 },
156 .p2
= { .dot_limit
= 200000,
157 .p2_slow
= 10, .p2_fast
= 5 },
158 .find_pll
= intel_find_best_PLL
,
161 static const intel_limit_t intel_limits_i9xx_lvds
= {
162 .dot
= { .min
= 20000, .max
= 400000 },
163 .vco
= { .min
= 1400000, .max
= 2800000 },
164 .n
= { .min
= 1, .max
= 6 },
165 .m
= { .min
= 70, .max
= 120 },
166 .m1
= { .min
= 8, .max
= 18 },
167 .m2
= { .min
= 3, .max
= 7 },
168 .p
= { .min
= 7, .max
= 98 },
169 .p1
= { .min
= 1, .max
= 8 },
170 .p2
= { .dot_limit
= 112000,
171 .p2_slow
= 14, .p2_fast
= 7 },
172 .find_pll
= intel_find_best_PLL
,
176 static const intel_limit_t intel_limits_g4x_sdvo
= {
177 .dot
= { .min
= 25000, .max
= 270000 },
178 .vco
= { .min
= 1750000, .max
= 3500000},
179 .n
= { .min
= 1, .max
= 4 },
180 .m
= { .min
= 104, .max
= 138 },
181 .m1
= { .min
= 17, .max
= 23 },
182 .m2
= { .min
= 5, .max
= 11 },
183 .p
= { .min
= 10, .max
= 30 },
184 .p1
= { .min
= 1, .max
= 3},
185 .p2
= { .dot_limit
= 270000,
189 .find_pll
= intel_g4x_find_best_PLL
,
192 static const intel_limit_t intel_limits_g4x_hdmi
= {
193 .dot
= { .min
= 22000, .max
= 400000 },
194 .vco
= { .min
= 1750000, .max
= 3500000},
195 .n
= { .min
= 1, .max
= 4 },
196 .m
= { .min
= 104, .max
= 138 },
197 .m1
= { .min
= 16, .max
= 23 },
198 .m2
= { .min
= 5, .max
= 11 },
199 .p
= { .min
= 5, .max
= 80 },
200 .p1
= { .min
= 1, .max
= 8},
201 .p2
= { .dot_limit
= 165000,
202 .p2_slow
= 10, .p2_fast
= 5 },
203 .find_pll
= intel_g4x_find_best_PLL
,
206 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
207 .dot
= { .min
= 20000, .max
= 115000 },
208 .vco
= { .min
= 1750000, .max
= 3500000 },
209 .n
= { .min
= 1, .max
= 3 },
210 .m
= { .min
= 104, .max
= 138 },
211 .m1
= { .min
= 17, .max
= 23 },
212 .m2
= { .min
= 5, .max
= 11 },
213 .p
= { .min
= 28, .max
= 112 },
214 .p1
= { .min
= 2, .max
= 8 },
215 .p2
= { .dot_limit
= 0,
216 .p2_slow
= 14, .p2_fast
= 14
218 .find_pll
= intel_g4x_find_best_PLL
,
221 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
222 .dot
= { .min
= 80000, .max
= 224000 },
223 .vco
= { .min
= 1750000, .max
= 3500000 },
224 .n
= { .min
= 1, .max
= 3 },
225 .m
= { .min
= 104, .max
= 138 },
226 .m1
= { .min
= 17, .max
= 23 },
227 .m2
= { .min
= 5, .max
= 11 },
228 .p
= { .min
= 14, .max
= 42 },
229 .p1
= { .min
= 2, .max
= 6 },
230 .p2
= { .dot_limit
= 0,
231 .p2_slow
= 7, .p2_fast
= 7
233 .find_pll
= intel_g4x_find_best_PLL
,
236 static const intel_limit_t intel_limits_pineview_sdvo
= {
237 .dot
= { .min
= 20000, .max
= 400000},
238 .vco
= { .min
= 1700000, .max
= 3500000 },
239 /* Pineview's Ncounter is a ring counter */
240 .n
= { .min
= 3, .max
= 6 },
241 .m
= { .min
= 2, .max
= 256 },
242 /* Pineview only has one combined m divider, which we treat as m2. */
243 .m1
= { .min
= 0, .max
= 0 },
244 .m2
= { .min
= 0, .max
= 254 },
245 .p
= { .min
= 5, .max
= 80 },
246 .p1
= { .min
= 1, .max
= 8 },
247 .p2
= { .dot_limit
= 200000,
248 .p2_slow
= 10, .p2_fast
= 5 },
249 .find_pll
= intel_find_best_PLL
,
252 static const intel_limit_t intel_limits_pineview_lvds
= {
253 .dot
= { .min
= 20000, .max
= 400000 },
254 .vco
= { .min
= 1700000, .max
= 3500000 },
255 .n
= { .min
= 3, .max
= 6 },
256 .m
= { .min
= 2, .max
= 256 },
257 .m1
= { .min
= 0, .max
= 0 },
258 .m2
= { .min
= 0, .max
= 254 },
259 .p
= { .min
= 7, .max
= 112 },
260 .p1
= { .min
= 1, .max
= 8 },
261 .p2
= { .dot_limit
= 112000,
262 .p2_slow
= 14, .p2_fast
= 14 },
263 .find_pll
= intel_find_best_PLL
,
266 /* Ironlake / Sandybridge
268 * We calculate clock using (register_value + 2) for N/M1/M2, so here
269 * the range value for them is (actual_value - 2).
271 static const intel_limit_t intel_limits_ironlake_dac
= {
272 .dot
= { .min
= 25000, .max
= 350000 },
273 .vco
= { .min
= 1760000, .max
= 3510000 },
274 .n
= { .min
= 1, .max
= 5 },
275 .m
= { .min
= 79, .max
= 127 },
276 .m1
= { .min
= 12, .max
= 22 },
277 .m2
= { .min
= 5, .max
= 9 },
278 .p
= { .min
= 5, .max
= 80 },
279 .p1
= { .min
= 1, .max
= 8 },
280 .p2
= { .dot_limit
= 225000,
281 .p2_slow
= 10, .p2_fast
= 5 },
282 .find_pll
= intel_g4x_find_best_PLL
,
285 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
286 .dot
= { .min
= 25000, .max
= 350000 },
287 .vco
= { .min
= 1760000, .max
= 3510000 },
288 .n
= { .min
= 1, .max
= 3 },
289 .m
= { .min
= 79, .max
= 118 },
290 .m1
= { .min
= 12, .max
= 22 },
291 .m2
= { .min
= 5, .max
= 9 },
292 .p
= { .min
= 28, .max
= 112 },
293 .p1
= { .min
= 2, .max
= 8 },
294 .p2
= { .dot_limit
= 225000,
295 .p2_slow
= 14, .p2_fast
= 14 },
296 .find_pll
= intel_g4x_find_best_PLL
,
299 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
300 .dot
= { .min
= 25000, .max
= 350000 },
301 .vco
= { .min
= 1760000, .max
= 3510000 },
302 .n
= { .min
= 1, .max
= 3 },
303 .m
= { .min
= 79, .max
= 127 },
304 .m1
= { .min
= 12, .max
= 22 },
305 .m2
= { .min
= 5, .max
= 9 },
306 .p
= { .min
= 14, .max
= 56 },
307 .p1
= { .min
= 2, .max
= 8 },
308 .p2
= { .dot_limit
= 225000,
309 .p2_slow
= 7, .p2_fast
= 7 },
310 .find_pll
= intel_g4x_find_best_PLL
,
313 /* LVDS 100mhz refclk limits. */
314 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
315 .dot
= { .min
= 25000, .max
= 350000 },
316 .vco
= { .min
= 1760000, .max
= 3510000 },
317 .n
= { .min
= 1, .max
= 2 },
318 .m
= { .min
= 79, .max
= 126 },
319 .m1
= { .min
= 12, .max
= 22 },
320 .m2
= { .min
= 5, .max
= 9 },
321 .p
= { .min
= 28, .max
= 112 },
322 .p1
= { .min
= 2, .max
= 8 },
323 .p2
= { .dot_limit
= 225000,
324 .p2_slow
= 14, .p2_fast
= 14 },
325 .find_pll
= intel_g4x_find_best_PLL
,
328 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
329 .dot
= { .min
= 25000, .max
= 350000 },
330 .vco
= { .min
= 1760000, .max
= 3510000 },
331 .n
= { .min
= 1, .max
= 3 },
332 .m
= { .min
= 79, .max
= 126 },
333 .m1
= { .min
= 12, .max
= 22 },
334 .m2
= { .min
= 5, .max
= 9 },
335 .p
= { .min
= 14, .max
= 42 },
336 .p1
= { .min
= 2, .max
= 6 },
337 .p2
= { .dot_limit
= 225000,
338 .p2_slow
= 7, .p2_fast
= 7 },
339 .find_pll
= intel_g4x_find_best_PLL
,
342 static const intel_limit_t intel_limits_vlv_dac
= {
343 .dot
= { .min
= 25000, .max
= 270000 },
344 .vco
= { .min
= 4000000, .max
= 6000000 },
345 .n
= { .min
= 1, .max
= 7 },
346 .m
= { .min
= 22, .max
= 450 }, /* guess */
347 .m1
= { .min
= 2, .max
= 3 },
348 .m2
= { .min
= 11, .max
= 156 },
349 .p
= { .min
= 10, .max
= 30 },
350 .p1
= { .min
= 1, .max
= 3 },
351 .p2
= { .dot_limit
= 270000,
352 .p2_slow
= 2, .p2_fast
= 20 },
353 .find_pll
= intel_vlv_find_best_pll
,
356 static const intel_limit_t intel_limits_vlv_hdmi
= {
357 .dot
= { .min
= 25000, .max
= 270000 },
358 .vco
= { .min
= 4000000, .max
= 6000000 },
359 .n
= { .min
= 1, .max
= 7 },
360 .m
= { .min
= 60, .max
= 300 }, /* guess */
361 .m1
= { .min
= 2, .max
= 3 },
362 .m2
= { .min
= 11, .max
= 156 },
363 .p
= { .min
= 10, .max
= 30 },
364 .p1
= { .min
= 2, .max
= 3 },
365 .p2
= { .dot_limit
= 270000,
366 .p2_slow
= 2, .p2_fast
= 20 },
367 .find_pll
= intel_vlv_find_best_pll
,
370 static const intel_limit_t intel_limits_vlv_dp
= {
371 .dot
= { .min
= 25000, .max
= 270000 },
372 .vco
= { .min
= 4000000, .max
= 6000000 },
373 .n
= { .min
= 1, .max
= 7 },
374 .m
= { .min
= 22, .max
= 450 },
375 .m1
= { .min
= 2, .max
= 3 },
376 .m2
= { .min
= 11, .max
= 156 },
377 .p
= { .min
= 10, .max
= 30 },
378 .p1
= { .min
= 1, .max
= 3 },
379 .p2
= { .dot_limit
= 270000,
380 .p2_slow
= 2, .p2_fast
= 20 },
381 .find_pll
= intel_vlv_find_best_pll
,
384 u32
intel_dpio_read(struct drm_i915_private
*dev_priv
, int reg
)
386 WARN_ON(!mutex_is_locked(&dev_priv
->dpio_lock
));
388 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
389 DRM_ERROR("DPIO idle wait timed out\n");
393 I915_WRITE(DPIO_REG
, reg
);
394 I915_WRITE(DPIO_PKT
, DPIO_RID
| DPIO_OP_READ
| DPIO_PORTID
|
396 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
397 DRM_ERROR("DPIO read wait timed out\n");
401 return I915_READ(DPIO_DATA
);
404 void intel_dpio_write(struct drm_i915_private
*dev_priv
, int reg
, u32 val
)
406 WARN_ON(!mutex_is_locked(&dev_priv
->dpio_lock
));
408 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
409 DRM_ERROR("DPIO idle wait timed out\n");
413 I915_WRITE(DPIO_DATA
, val
);
414 I915_WRITE(DPIO_REG
, reg
);
415 I915_WRITE(DPIO_PKT
, DPIO_RID
| DPIO_OP_WRITE
| DPIO_PORTID
|
417 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100))
418 DRM_ERROR("DPIO write wait timed out\n");
421 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
,
424 struct drm_device
*dev
= crtc
->dev
;
425 const intel_limit_t
*limit
;
427 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
428 if (intel_is_dual_link_lvds(dev
)) {
429 if (refclk
== 100000)
430 limit
= &intel_limits_ironlake_dual_lvds_100m
;
432 limit
= &intel_limits_ironlake_dual_lvds
;
434 if (refclk
== 100000)
435 limit
= &intel_limits_ironlake_single_lvds_100m
;
437 limit
= &intel_limits_ironlake_single_lvds
;
440 limit
= &intel_limits_ironlake_dac
;
445 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
447 struct drm_device
*dev
= crtc
->dev
;
448 const intel_limit_t
*limit
;
450 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
451 if (intel_is_dual_link_lvds(dev
))
452 limit
= &intel_limits_g4x_dual_channel_lvds
;
454 limit
= &intel_limits_g4x_single_channel_lvds
;
455 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
456 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
457 limit
= &intel_limits_g4x_hdmi
;
458 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
459 limit
= &intel_limits_g4x_sdvo
;
460 } else /* The option is for other outputs */
461 limit
= &intel_limits_i9xx_sdvo
;
466 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
, int refclk
)
468 struct drm_device
*dev
= crtc
->dev
;
469 const intel_limit_t
*limit
;
471 if (HAS_PCH_SPLIT(dev
))
472 limit
= intel_ironlake_limit(crtc
, refclk
);
473 else if (IS_G4X(dev
)) {
474 limit
= intel_g4x_limit(crtc
);
475 } else if (IS_PINEVIEW(dev
)) {
476 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
477 limit
= &intel_limits_pineview_lvds
;
479 limit
= &intel_limits_pineview_sdvo
;
480 } else if (IS_VALLEYVIEW(dev
)) {
481 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
))
482 limit
= &intel_limits_vlv_dac
;
483 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
484 limit
= &intel_limits_vlv_hdmi
;
486 limit
= &intel_limits_vlv_dp
;
487 } else if (!IS_GEN2(dev
)) {
488 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
489 limit
= &intel_limits_i9xx_lvds
;
491 limit
= &intel_limits_i9xx_sdvo
;
493 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
494 limit
= &intel_limits_i8xx_lvds
;
496 limit
= &intel_limits_i8xx_dvo
;
501 /* m1 is reserved as 0 in Pineview, n is a ring counter */
502 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
504 clock
->m
= clock
->m2
+ 2;
505 clock
->p
= clock
->p1
* clock
->p2
;
506 clock
->vco
= refclk
* clock
->m
/ clock
->n
;
507 clock
->dot
= clock
->vco
/ clock
->p
;
510 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
512 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
515 static void intel_clock(struct drm_device
*dev
, int refclk
, intel_clock_t
*clock
)
517 if (IS_PINEVIEW(dev
)) {
518 pineview_clock(refclk
, clock
);
521 clock
->m
= i9xx_dpll_compute_m(clock
);
522 clock
->p
= clock
->p1
* clock
->p2
;
523 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
524 clock
->dot
= clock
->vco
/ clock
->p
;
528 * Returns whether any output on the specified pipe is of the specified type
530 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
532 struct drm_device
*dev
= crtc
->dev
;
533 struct intel_encoder
*encoder
;
535 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
536 if (encoder
->type
== type
)
542 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
544 * Returns whether the given set of divisors are valid for a given refclk with
545 * the given connectors.
548 static bool intel_PLL_is_valid(struct drm_device
*dev
,
549 const intel_limit_t
*limit
,
550 const intel_clock_t
*clock
)
552 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
553 INTELPllInvalid("p1 out of range\n");
554 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
555 INTELPllInvalid("p out of range\n");
556 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
557 INTELPllInvalid("m2 out of range\n");
558 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
559 INTELPllInvalid("m1 out of range\n");
560 if (clock
->m1
<= clock
->m2
&& !IS_PINEVIEW(dev
))
561 INTELPllInvalid("m1 <= m2\n");
562 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
563 INTELPllInvalid("m out of range\n");
564 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
565 INTELPllInvalid("n out of range\n");
566 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
567 INTELPllInvalid("vco out of range\n");
568 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
569 * connector, etc., rather than just a single range.
571 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
572 INTELPllInvalid("dot out of range\n");
578 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
579 int target
, int refclk
, intel_clock_t
*match_clock
,
580 intel_clock_t
*best_clock
)
583 struct drm_device
*dev
= crtc
->dev
;
587 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
589 * For LVDS just rely on its current settings for dual-channel.
590 * We haven't figured out how to reliably set up different
591 * single/dual channel state, if we even can.
593 if (intel_is_dual_link_lvds(dev
))
594 clock
.p2
= limit
->p2
.p2_fast
;
596 clock
.p2
= limit
->p2
.p2_slow
;
598 if (target
< limit
->p2
.dot_limit
)
599 clock
.p2
= limit
->p2
.p2_slow
;
601 clock
.p2
= limit
->p2
.p2_fast
;
604 memset(best_clock
, 0, sizeof(*best_clock
));
606 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
608 for (clock
.m2
= limit
->m2
.min
;
609 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
610 /* m1 is always 0 in Pineview */
611 if (clock
.m2
>= clock
.m1
&& !IS_PINEVIEW(dev
))
613 for (clock
.n
= limit
->n
.min
;
614 clock
.n
<= limit
->n
.max
; clock
.n
++) {
615 for (clock
.p1
= limit
->p1
.min
;
616 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
619 intel_clock(dev
, refclk
, &clock
);
620 if (!intel_PLL_is_valid(dev
, limit
,
624 clock
.p
!= match_clock
->p
)
627 this_err
= abs(clock
.dot
- target
);
628 if (this_err
< err
) {
637 return (err
!= target
);
641 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
642 int target
, int refclk
, intel_clock_t
*match_clock
,
643 intel_clock_t
*best_clock
)
645 struct drm_device
*dev
= crtc
->dev
;
649 /* approximately equals target * 0.00585 */
650 int err_most
= (target
>> 8) + (target
>> 9);
653 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
656 if (HAS_PCH_SPLIT(dev
))
660 if (intel_is_dual_link_lvds(dev
))
661 clock
.p2
= limit
->p2
.p2_fast
;
663 clock
.p2
= limit
->p2
.p2_slow
;
665 if (target
< limit
->p2
.dot_limit
)
666 clock
.p2
= limit
->p2
.p2_slow
;
668 clock
.p2
= limit
->p2
.p2_fast
;
671 memset(best_clock
, 0, sizeof(*best_clock
));
672 max_n
= limit
->n
.max
;
673 /* based on hardware requirement, prefer smaller n to precision */
674 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
675 /* based on hardware requirement, prefere larger m1,m2 */
676 for (clock
.m1
= limit
->m1
.max
;
677 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
678 for (clock
.m2
= limit
->m2
.max
;
679 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
680 for (clock
.p1
= limit
->p1
.max
;
681 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
684 intel_clock(dev
, refclk
, &clock
);
685 if (!intel_PLL_is_valid(dev
, limit
,
689 this_err
= abs(clock
.dot
- target
);
690 if (this_err
< err_most
) {
704 intel_vlv_find_best_pll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
705 int target
, int refclk
, intel_clock_t
*match_clock
,
706 intel_clock_t
*best_clock
)
708 u32 p1
, p2
, m1
, m2
, vco
, bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
710 u32 updrate
, minupdate
, fracbits
, p
;
711 unsigned long bestppm
, ppm
, absppm
;
715 dotclk
= target
* 1000;
718 fastclk
= dotclk
/ (2*100);
722 n
= p
= p1
= p2
= m
= m1
= m2
= vco
= bestn
= 0;
723 bestm1
= bestm2
= bestp1
= bestp2
= 0;
725 /* based on hardware requirement, prefer smaller n to precision */
726 for (n
= limit
->n
.min
; n
<= ((refclk
) / minupdate
); n
++) {
727 updrate
= refclk
/ n
;
728 for (p1
= limit
->p1
.max
; p1
> limit
->p1
.min
; p1
--) {
729 for (p2
= limit
->p2
.p2_fast
+1; p2
> 0; p2
--) {
733 /* based on hardware requirement, prefer bigger m1,m2 values */
734 for (m1
= limit
->m1
.min
; m1
<= limit
->m1
.max
; m1
++) {
735 m2
= (((2*(fastclk
* p
* n
/ m1
)) +
736 refclk
) / (2*refclk
));
739 if (vco
>= limit
->vco
.min
&& vco
< limit
->vco
.max
) {
740 ppm
= 1000000 * ((vco
/ p
) - fastclk
) / fastclk
;
741 absppm
= (ppm
> 0) ? ppm
: (-ppm
);
742 if (absppm
< 100 && ((p1
* p2
) > (bestp1
* bestp2
))) {
746 if (absppm
< bestppm
- 10) {
763 best_clock
->n
= bestn
;
764 best_clock
->m1
= bestm1
;
765 best_clock
->m2
= bestm2
;
766 best_clock
->p1
= bestp1
;
767 best_clock
->p2
= bestp2
;
772 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
775 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
776 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
778 return intel_crtc
->config
.cpu_transcoder
;
781 static void ironlake_wait_for_vblank(struct drm_device
*dev
, int pipe
)
783 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
784 u32 frame
, frame_reg
= PIPEFRAME(pipe
);
786 frame
= I915_READ(frame_reg
);
788 if (wait_for(I915_READ_NOTRACE(frame_reg
) != frame
, 50))
789 DRM_DEBUG_KMS("vblank wait timed out\n");
793 * intel_wait_for_vblank - wait for vblank on a given pipe
795 * @pipe: pipe to wait for
797 * Wait for vblank to occur on a given pipe. Needed for various bits of
800 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
802 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
803 int pipestat_reg
= PIPESTAT(pipe
);
805 if (INTEL_INFO(dev
)->gen
>= 5) {
806 ironlake_wait_for_vblank(dev
, pipe
);
810 /* Clear existing vblank status. Note this will clear any other
811 * sticky status fields as well.
813 * This races with i915_driver_irq_handler() with the result
814 * that either function could miss a vblank event. Here it is not
815 * fatal, as we will either wait upon the next vblank interrupt or
816 * timeout. Generally speaking intel_wait_for_vblank() is only
817 * called during modeset at which time the GPU should be idle and
818 * should *not* be performing page flips and thus not waiting on
820 * Currently, the result of us stealing a vblank from the irq
821 * handler is that a single frame will be skipped during swapbuffers.
823 I915_WRITE(pipestat_reg
,
824 I915_READ(pipestat_reg
) | PIPE_VBLANK_INTERRUPT_STATUS
);
826 /* Wait for vblank interrupt bit to set */
827 if (wait_for(I915_READ(pipestat_reg
) &
828 PIPE_VBLANK_INTERRUPT_STATUS
,
830 DRM_DEBUG_KMS("vblank wait timed out\n");
834 * intel_wait_for_pipe_off - wait for pipe to turn off
836 * @pipe: pipe to wait for
838 * After disabling a pipe, we can't wait for vblank in the usual way,
839 * spinning on the vblank interrupt status bit, since we won't actually
840 * see an interrupt when the pipe is disabled.
843 * wait for the pipe register state bit to turn off
846 * wait for the display line value to settle (it usually
847 * ends up stopping at the start of the next frame).
850 void intel_wait_for_pipe_off(struct drm_device
*dev
, int pipe
)
852 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
853 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
856 if (INTEL_INFO(dev
)->gen
>= 4) {
857 int reg
= PIPECONF(cpu_transcoder
);
859 /* Wait for the Pipe State to go off */
860 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
862 WARN(1, "pipe_off wait timed out\n");
864 u32 last_line
, line_mask
;
865 int reg
= PIPEDSL(pipe
);
866 unsigned long timeout
= jiffies
+ msecs_to_jiffies(100);
869 line_mask
= DSL_LINEMASK_GEN2
;
871 line_mask
= DSL_LINEMASK_GEN3
;
873 /* Wait for the display line to settle */
875 last_line
= I915_READ(reg
) & line_mask
;
877 } while (((I915_READ(reg
) & line_mask
) != last_line
) &&
878 time_after(timeout
, jiffies
));
879 if (time_after(jiffies
, timeout
))
880 WARN(1, "pipe_off wait timed out\n");
885 * ibx_digital_port_connected - is the specified port connected?
886 * @dev_priv: i915 private structure
887 * @port: the port to test
889 * Returns true if @port is connected, false otherwise.
891 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
892 struct intel_digital_port
*port
)
896 if (HAS_PCH_IBX(dev_priv
->dev
)) {
899 bit
= SDE_PORTB_HOTPLUG
;
902 bit
= SDE_PORTC_HOTPLUG
;
905 bit
= SDE_PORTD_HOTPLUG
;
913 bit
= SDE_PORTB_HOTPLUG_CPT
;
916 bit
= SDE_PORTC_HOTPLUG_CPT
;
919 bit
= SDE_PORTD_HOTPLUG_CPT
;
926 return I915_READ(SDEISR
) & bit
;
929 static const char *state_string(bool enabled
)
931 return enabled
? "on" : "off";
934 /* Only for pre-ILK configs */
935 static void assert_pll(struct drm_i915_private
*dev_priv
,
936 enum pipe pipe
, bool state
)
943 val
= I915_READ(reg
);
944 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
945 WARN(cur_state
!= state
,
946 "PLL state assertion failure (expected %s, current %s)\n",
947 state_string(state
), state_string(cur_state
));
949 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
950 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
953 static void assert_pch_pll(struct drm_i915_private
*dev_priv
,
954 struct intel_pch_pll
*pll
,
955 struct intel_crtc
*crtc
,
961 if (HAS_PCH_LPT(dev_priv
->dev
)) {
962 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
967 "asserting PCH PLL %s with no PLL\n", state_string(state
)))
970 val
= I915_READ(pll
->pll_reg
);
971 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
972 WARN(cur_state
!= state
,
973 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
974 pll
->pll_reg
, state_string(state
), state_string(cur_state
), val
);
976 /* Make sure the selected PLL is correctly attached to the transcoder */
977 if (crtc
&& HAS_PCH_CPT(dev_priv
->dev
)) {
980 pch_dpll
= I915_READ(PCH_DPLL_SEL
);
981 cur_state
= pll
->pll_reg
== _PCH_DPLL_B
;
982 if (!WARN(((pch_dpll
>> (4 * crtc
->pipe
)) & 1) != cur_state
,
983 "PLL[%d] not attached to this transcoder %c: %08x\n",
984 cur_state
, pipe_name(crtc
->pipe
), pch_dpll
)) {
985 cur_state
= !!(val
>> (4*crtc
->pipe
+ 3));
986 WARN(cur_state
!= state
,
987 "PLL[%d] not %s on this transcoder %c: %08x\n",
988 pll
->pll_reg
== _PCH_DPLL_B
,
990 pipe_name(crtc
->pipe
),
995 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
996 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
998 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
999 enum pipe pipe
, bool state
)
1004 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1007 if (HAS_DDI(dev_priv
->dev
)) {
1008 /* DDI does not have a specific FDI_TX register */
1009 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1010 val
= I915_READ(reg
);
1011 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1013 reg
= FDI_TX_CTL(pipe
);
1014 val
= I915_READ(reg
);
1015 cur_state
= !!(val
& FDI_TX_ENABLE
);
1017 WARN(cur_state
!= state
,
1018 "FDI TX state assertion failure (expected %s, current %s)\n",
1019 state_string(state
), state_string(cur_state
));
1021 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1022 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1024 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1025 enum pipe pipe
, bool state
)
1031 reg
= FDI_RX_CTL(pipe
);
1032 val
= I915_READ(reg
);
1033 cur_state
= !!(val
& FDI_RX_ENABLE
);
1034 WARN(cur_state
!= state
,
1035 "FDI RX state assertion failure (expected %s, current %s)\n",
1036 state_string(state
), state_string(cur_state
));
1038 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1039 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1041 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1047 /* ILK FDI PLL is always enabled */
1048 if (dev_priv
->info
->gen
== 5)
1051 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1052 if (HAS_DDI(dev_priv
->dev
))
1055 reg
= FDI_TX_CTL(pipe
);
1056 val
= I915_READ(reg
);
1057 WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1060 static void assert_fdi_rx_pll_enabled(struct drm_i915_private
*dev_priv
,
1066 reg
= FDI_RX_CTL(pipe
);
1067 val
= I915_READ(reg
);
1068 WARN(!(val
& FDI_RX_PLL_ENABLE
), "FDI RX PLL assertion failure, should be active but is disabled\n");
1071 static void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1074 int pp_reg
, lvds_reg
;
1076 enum pipe panel_pipe
= PIPE_A
;
1079 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
1080 pp_reg
= PCH_PP_CONTROL
;
1081 lvds_reg
= PCH_LVDS
;
1083 pp_reg
= PP_CONTROL
;
1087 val
= I915_READ(pp_reg
);
1088 if (!(val
& PANEL_POWER_ON
) ||
1089 ((val
& PANEL_UNLOCK_REGS
) == PANEL_UNLOCK_REGS
))
1092 if (I915_READ(lvds_reg
) & LVDS_PIPEB_SELECT
)
1093 panel_pipe
= PIPE_B
;
1095 WARN(panel_pipe
== pipe
&& locked
,
1096 "panel assertion failure, pipe %c regs locked\n",
1100 void assert_pipe(struct drm_i915_private
*dev_priv
,
1101 enum pipe pipe
, bool state
)
1106 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1109 /* if we need the pipe A quirk it must be always on */
1110 if (pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
1113 if (!intel_using_power_well(dev_priv
->dev
) &&
1114 cpu_transcoder
!= TRANSCODER_EDP
) {
1117 reg
= PIPECONF(cpu_transcoder
);
1118 val
= I915_READ(reg
);
1119 cur_state
= !!(val
& PIPECONF_ENABLE
);
1122 WARN(cur_state
!= state
,
1123 "pipe %c assertion failure (expected %s, current %s)\n",
1124 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1127 static void assert_plane(struct drm_i915_private
*dev_priv
,
1128 enum plane plane
, bool state
)
1134 reg
= DSPCNTR(plane
);
1135 val
= I915_READ(reg
);
1136 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1137 WARN(cur_state
!= state
,
1138 "plane %c assertion failure (expected %s, current %s)\n",
1139 plane_name(plane
), state_string(state
), state_string(cur_state
));
1142 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1143 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1145 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1152 /* Planes are fixed to pipes on ILK+ */
1153 if (HAS_PCH_SPLIT(dev_priv
->dev
) || IS_VALLEYVIEW(dev_priv
->dev
)) {
1154 reg
= DSPCNTR(pipe
);
1155 val
= I915_READ(reg
);
1156 WARN((val
& DISPLAY_PLANE_ENABLE
),
1157 "plane %c assertion failure, should be disabled but not\n",
1162 /* Need to check both planes against the pipe */
1163 for (i
= 0; i
< 2; i
++) {
1165 val
= I915_READ(reg
);
1166 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1167 DISPPLANE_SEL_PIPE_SHIFT
;
1168 WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1169 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1170 plane_name(i
), pipe_name(pipe
));
1174 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1180 if (!IS_VALLEYVIEW(dev_priv
->dev
))
1183 /* Need to check both planes against the pipe */
1184 for (i
= 0; i
< dev_priv
->num_plane
; i
++) {
1185 reg
= SPCNTR(pipe
, i
);
1186 val
= I915_READ(reg
);
1187 WARN((val
& SP_ENABLE
),
1188 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1189 sprite_name(pipe
, i
), pipe_name(pipe
));
1193 static void assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1198 if (HAS_PCH_LPT(dev_priv
->dev
)) {
1199 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1203 val
= I915_READ(PCH_DREF_CONTROL
);
1204 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1205 DREF_SUPERSPREAD_SOURCE_MASK
));
1206 WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1209 static void assert_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1216 reg
= TRANSCONF(pipe
);
1217 val
= I915_READ(reg
);
1218 enabled
= !!(val
& TRANS_ENABLE
);
1220 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1224 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1225 enum pipe pipe
, u32 port_sel
, u32 val
)
1227 if ((val
& DP_PORT_EN
) == 0)
1230 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1231 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1232 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1233 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1236 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1242 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1243 enum pipe pipe
, u32 val
)
1245 if ((val
& SDVO_ENABLE
) == 0)
1248 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1249 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1252 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1258 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1259 enum pipe pipe
, u32 val
)
1261 if ((val
& LVDS_PORT_EN
) == 0)
1264 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1265 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1268 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1274 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1275 enum pipe pipe
, u32 val
)
1277 if ((val
& ADPA_DAC_ENABLE
) == 0)
1279 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1280 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1283 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1289 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1290 enum pipe pipe
, int reg
, u32 port_sel
)
1292 u32 val
= I915_READ(reg
);
1293 WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1294 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1295 reg
, pipe_name(pipe
));
1297 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1298 && (val
& DP_PIPEB_SELECT
),
1299 "IBX PCH dp port still using transcoder B\n");
1302 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1303 enum pipe pipe
, int reg
)
1305 u32 val
= I915_READ(reg
);
1306 WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1307 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1308 reg
, pipe_name(pipe
));
1310 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_ENABLE
) == 0
1311 && (val
& SDVO_PIPE_B_SELECT
),
1312 "IBX PCH hdmi port still using transcoder B\n");
1315 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1321 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1322 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1323 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1326 val
= I915_READ(reg
);
1327 WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1328 "PCH VGA enabled on transcoder %c, should be disabled\n",
1332 val
= I915_READ(reg
);
1333 WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1334 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1337 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1338 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1339 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1343 * intel_enable_pll - enable a PLL
1344 * @dev_priv: i915 private structure
1345 * @pipe: pipe PLL to enable
1347 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1348 * make sure the PLL reg is writable first though, since the panel write
1349 * protect mechanism may be enabled.
1351 * Note! This is for pre-ILK only.
1353 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1355 static void intel_enable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1360 assert_pipe_disabled(dev_priv
, pipe
);
1362 /* No really, not for ILK+ */
1363 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
) && dev_priv
->info
->gen
>= 5);
1365 /* PLL is protected by panel, make sure we can write it */
1366 if (IS_MOBILE(dev_priv
->dev
) && !IS_I830(dev_priv
->dev
))
1367 assert_panel_unlocked(dev_priv
, pipe
);
1370 val
= I915_READ(reg
);
1371 val
|= DPLL_VCO_ENABLE
;
1373 /* We do this three times for luck */
1374 I915_WRITE(reg
, val
);
1376 udelay(150); /* wait for warmup */
1377 I915_WRITE(reg
, val
);
1379 udelay(150); /* wait for warmup */
1380 I915_WRITE(reg
, val
);
1382 udelay(150); /* wait for warmup */
1386 * intel_disable_pll - disable a PLL
1387 * @dev_priv: i915 private structure
1388 * @pipe: pipe PLL to disable
1390 * Disable the PLL for @pipe, making sure the pipe is off first.
1392 * Note! This is for pre-ILK only.
1394 static void intel_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1399 /* Don't disable pipe A or pipe A PLLs if needed */
1400 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1403 /* Make sure the pipe isn't still relying on us */
1404 assert_pipe_disabled(dev_priv
, pipe
);
1407 val
= I915_READ(reg
);
1408 val
&= ~DPLL_VCO_ENABLE
;
1409 I915_WRITE(reg
, val
);
1415 intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
1416 enum intel_sbi_destination destination
)
1420 WARN_ON(!mutex_is_locked(&dev_priv
->dpio_lock
));
1422 if (wait_for((I915_READ(SBI_CTL_STAT
) & SBI_BUSY
) == 0,
1424 DRM_ERROR("timeout waiting for SBI to become ready\n");
1428 I915_WRITE(SBI_ADDR
, (reg
<< 16));
1429 I915_WRITE(SBI_DATA
, value
);
1431 if (destination
== SBI_ICLK
)
1432 tmp
= SBI_CTL_DEST_ICLK
| SBI_CTL_OP_CRWR
;
1434 tmp
= SBI_CTL_DEST_MPHY
| SBI_CTL_OP_IOWR
;
1435 I915_WRITE(SBI_CTL_STAT
, SBI_BUSY
| tmp
);
1437 if (wait_for((I915_READ(SBI_CTL_STAT
) & (SBI_BUSY
| SBI_RESPONSE_FAIL
)) == 0,
1439 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1445 intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
1446 enum intel_sbi_destination destination
)
1449 WARN_ON(!mutex_is_locked(&dev_priv
->dpio_lock
));
1451 if (wait_for((I915_READ(SBI_CTL_STAT
) & SBI_BUSY
) == 0,
1453 DRM_ERROR("timeout waiting for SBI to become ready\n");
1457 I915_WRITE(SBI_ADDR
, (reg
<< 16));
1459 if (destination
== SBI_ICLK
)
1460 value
= SBI_CTL_DEST_ICLK
| SBI_CTL_OP_CRRD
;
1462 value
= SBI_CTL_DEST_MPHY
| SBI_CTL_OP_IORD
;
1463 I915_WRITE(SBI_CTL_STAT
, value
| SBI_BUSY
);
1465 if (wait_for((I915_READ(SBI_CTL_STAT
) & (SBI_BUSY
| SBI_RESPONSE_FAIL
)) == 0,
1467 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1471 return I915_READ(SBI_DATA
);
1474 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
, int port
)
1479 port_mask
= DPLL_PORTB_READY_MASK
;
1481 port_mask
= DPLL_PORTC_READY_MASK
;
1483 if (wait_for((I915_READ(DPLL(0)) & port_mask
) == 0, 1000))
1484 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1485 'B' + port
, I915_READ(DPLL(0)));
1489 * ironlake_enable_pch_pll - enable PCH PLL
1490 * @dev_priv: i915 private structure
1491 * @pipe: pipe PLL to enable
1493 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1494 * drives the transcoder clock.
1496 static void ironlake_enable_pch_pll(struct intel_crtc
*intel_crtc
)
1498 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
1499 struct intel_pch_pll
*pll
;
1503 /* PCH PLLs only available on ILK, SNB and IVB */
1504 BUG_ON(dev_priv
->info
->gen
< 5);
1505 pll
= intel_crtc
->pch_pll
;
1509 if (WARN_ON(pll
->refcount
== 0))
1512 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1513 pll
->pll_reg
, pll
->active
, pll
->on
,
1514 intel_crtc
->base
.base
.id
);
1516 /* PCH refclock must be enabled first */
1517 assert_pch_refclk_enabled(dev_priv
);
1519 if (pll
->active
++ && pll
->on
) {
1520 assert_pch_pll_enabled(dev_priv
, pll
, NULL
);
1524 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll
->pll_reg
);
1527 val
= I915_READ(reg
);
1528 val
|= DPLL_VCO_ENABLE
;
1529 I915_WRITE(reg
, val
);
1536 static void intel_disable_pch_pll(struct intel_crtc
*intel_crtc
)
1538 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
1539 struct intel_pch_pll
*pll
= intel_crtc
->pch_pll
;
1543 /* PCH only available on ILK+ */
1544 BUG_ON(dev_priv
->info
->gen
< 5);
1548 if (WARN_ON(pll
->refcount
== 0))
1551 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1552 pll
->pll_reg
, pll
->active
, pll
->on
,
1553 intel_crtc
->base
.base
.id
);
1555 if (WARN_ON(pll
->active
== 0)) {
1556 assert_pch_pll_disabled(dev_priv
, pll
, NULL
);
1560 if (--pll
->active
) {
1561 assert_pch_pll_enabled(dev_priv
, pll
, NULL
);
1565 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll
->pll_reg
);
1567 /* Make sure transcoder isn't still depending on us */
1568 assert_transcoder_disabled(dev_priv
, intel_crtc
->pipe
);
1571 val
= I915_READ(reg
);
1572 val
&= ~DPLL_VCO_ENABLE
;
1573 I915_WRITE(reg
, val
);
1580 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1583 struct drm_device
*dev
= dev_priv
->dev
;
1584 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1585 uint32_t reg
, val
, pipeconf_val
;
1587 /* PCH only available on ILK+ */
1588 BUG_ON(dev_priv
->info
->gen
< 5);
1590 /* Make sure PCH DPLL is enabled */
1591 assert_pch_pll_enabled(dev_priv
,
1592 to_intel_crtc(crtc
)->pch_pll
,
1593 to_intel_crtc(crtc
));
1595 /* FDI must be feeding us bits for PCH ports */
1596 assert_fdi_tx_enabled(dev_priv
, pipe
);
1597 assert_fdi_rx_enabled(dev_priv
, pipe
);
1599 if (HAS_PCH_CPT(dev
)) {
1600 /* Workaround: Set the timing override bit before enabling the
1601 * pch transcoder. */
1602 reg
= TRANS_CHICKEN2(pipe
);
1603 val
= I915_READ(reg
);
1604 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1605 I915_WRITE(reg
, val
);
1608 reg
= TRANSCONF(pipe
);
1609 val
= I915_READ(reg
);
1610 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1612 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1614 * make the BPC in transcoder be consistent with
1615 * that in pipeconf reg.
1617 val
&= ~PIPECONF_BPC_MASK
;
1618 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1621 val
&= ~TRANS_INTERLACE_MASK
;
1622 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1623 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1624 intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
))
1625 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1627 val
|= TRANS_INTERLACED
;
1629 val
|= TRANS_PROGRESSIVE
;
1631 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1632 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1633 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
1636 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1637 enum transcoder cpu_transcoder
)
1639 u32 val
, pipeconf_val
;
1641 /* PCH only available on ILK+ */
1642 BUG_ON(dev_priv
->info
->gen
< 5);
1644 /* FDI must be feeding us bits for PCH ports */
1645 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1646 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
1648 /* Workaround: set timing override bit. */
1649 val
= I915_READ(_TRANSA_CHICKEN2
);
1650 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1651 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1654 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1656 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1657 PIPECONF_INTERLACED_ILK
)
1658 val
|= TRANS_INTERLACED
;
1660 val
|= TRANS_PROGRESSIVE
;
1662 I915_WRITE(TRANSCONF(TRANSCODER_A
), val
);
1663 if (wait_for(I915_READ(_TRANSACONF
) & TRANS_STATE_ENABLE
, 100))
1664 DRM_ERROR("Failed to enable PCH transcoder\n");
1667 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1670 struct drm_device
*dev
= dev_priv
->dev
;
1673 /* FDI relies on the transcoder */
1674 assert_fdi_tx_disabled(dev_priv
, pipe
);
1675 assert_fdi_rx_disabled(dev_priv
, pipe
);
1677 /* Ports must be off as well */
1678 assert_pch_ports_disabled(dev_priv
, pipe
);
1680 reg
= TRANSCONF(pipe
);
1681 val
= I915_READ(reg
);
1682 val
&= ~TRANS_ENABLE
;
1683 I915_WRITE(reg
, val
);
1684 /* wait for PCH transcoder off, transcoder state */
1685 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1686 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
1688 if (!HAS_PCH_IBX(dev
)) {
1689 /* Workaround: Clear the timing override chicken bit again. */
1690 reg
= TRANS_CHICKEN2(pipe
);
1691 val
= I915_READ(reg
);
1692 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1693 I915_WRITE(reg
, val
);
1697 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1701 val
= I915_READ(_TRANSACONF
);
1702 val
&= ~TRANS_ENABLE
;
1703 I915_WRITE(_TRANSACONF
, val
);
1704 /* wait for PCH transcoder off, transcoder state */
1705 if (wait_for((I915_READ(_TRANSACONF
) & TRANS_STATE_ENABLE
) == 0, 50))
1706 DRM_ERROR("Failed to disable PCH transcoder\n");
1708 /* Workaround: clear timing override bit. */
1709 val
= I915_READ(_TRANSA_CHICKEN2
);
1710 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1711 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1715 * intel_enable_pipe - enable a pipe, asserting requirements
1716 * @dev_priv: i915 private structure
1717 * @pipe: pipe to enable
1718 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1720 * Enable @pipe, making sure that various hardware specific requirements
1721 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1723 * @pipe should be %PIPE_A or %PIPE_B.
1725 * Will wait until the pipe is actually running (i.e. first vblank) before
1728 static void intel_enable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
1731 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1733 enum pipe pch_transcoder
;
1737 assert_planes_disabled(dev_priv
, pipe
);
1738 assert_sprites_disabled(dev_priv
, pipe
);
1740 if (HAS_PCH_LPT(dev_priv
->dev
))
1741 pch_transcoder
= TRANSCODER_A
;
1743 pch_transcoder
= pipe
;
1746 * A pipe without a PLL won't actually be able to drive bits from
1747 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1750 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
1751 assert_pll_enabled(dev_priv
, pipe
);
1754 /* if driving the PCH, we need FDI enabled */
1755 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
1756 assert_fdi_tx_pll_enabled(dev_priv
,
1757 (enum pipe
) cpu_transcoder
);
1759 /* FIXME: assert CPU port conditions for SNB+ */
1762 reg
= PIPECONF(cpu_transcoder
);
1763 val
= I915_READ(reg
);
1764 if (val
& PIPECONF_ENABLE
)
1767 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
1768 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1772 * intel_disable_pipe - disable a pipe, asserting requirements
1773 * @dev_priv: i915 private structure
1774 * @pipe: pipe to disable
1776 * Disable @pipe, making sure that various hardware specific requirements
1777 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1779 * @pipe should be %PIPE_A or %PIPE_B.
1781 * Will wait until the pipe has shut down before returning.
1783 static void intel_disable_pipe(struct drm_i915_private
*dev_priv
,
1786 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1792 * Make sure planes won't keep trying to pump pixels to us,
1793 * or we might hang the display.
1795 assert_planes_disabled(dev_priv
, pipe
);
1796 assert_sprites_disabled(dev_priv
, pipe
);
1798 /* Don't disable pipe A or pipe A PLLs if needed */
1799 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1802 reg
= PIPECONF(cpu_transcoder
);
1803 val
= I915_READ(reg
);
1804 if ((val
& PIPECONF_ENABLE
) == 0)
1807 I915_WRITE(reg
, val
& ~PIPECONF_ENABLE
);
1808 intel_wait_for_pipe_off(dev_priv
->dev
, pipe
);
1812 * Plane regs are double buffered, going from enabled->disabled needs a
1813 * trigger in order to latch. The display address reg provides this.
1815 void intel_flush_display_plane(struct drm_i915_private
*dev_priv
,
1818 if (dev_priv
->info
->gen
>= 4)
1819 I915_WRITE(DSPSURF(plane
), I915_READ(DSPSURF(plane
)));
1821 I915_WRITE(DSPADDR(plane
), I915_READ(DSPADDR(plane
)));
1825 * intel_enable_plane - enable a display plane on a given pipe
1826 * @dev_priv: i915 private structure
1827 * @plane: plane to enable
1828 * @pipe: pipe being fed
1830 * Enable @plane on @pipe, making sure that @pipe is running first.
1832 static void intel_enable_plane(struct drm_i915_private
*dev_priv
,
1833 enum plane plane
, enum pipe pipe
)
1838 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1839 assert_pipe_enabled(dev_priv
, pipe
);
1841 reg
= DSPCNTR(plane
);
1842 val
= I915_READ(reg
);
1843 if (val
& DISPLAY_PLANE_ENABLE
)
1846 I915_WRITE(reg
, val
| DISPLAY_PLANE_ENABLE
);
1847 intel_flush_display_plane(dev_priv
, plane
);
1848 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1852 * intel_disable_plane - disable a display plane
1853 * @dev_priv: i915 private structure
1854 * @plane: plane to disable
1855 * @pipe: pipe consuming the data
1857 * Disable @plane; should be an independent operation.
1859 static void intel_disable_plane(struct drm_i915_private
*dev_priv
,
1860 enum plane plane
, enum pipe pipe
)
1865 reg
= DSPCNTR(plane
);
1866 val
= I915_READ(reg
);
1867 if ((val
& DISPLAY_PLANE_ENABLE
) == 0)
1870 I915_WRITE(reg
, val
& ~DISPLAY_PLANE_ENABLE
);
1871 intel_flush_display_plane(dev_priv
, plane
);
1872 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1875 static bool need_vtd_wa(struct drm_device
*dev
)
1877 #ifdef CONFIG_INTEL_IOMMU
1878 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
1885 intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
1886 struct drm_i915_gem_object
*obj
,
1887 struct intel_ring_buffer
*pipelined
)
1889 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1893 switch (obj
->tiling_mode
) {
1894 case I915_TILING_NONE
:
1895 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
1896 alignment
= 128 * 1024;
1897 else if (INTEL_INFO(dev
)->gen
>= 4)
1898 alignment
= 4 * 1024;
1900 alignment
= 64 * 1024;
1903 /* pin() will align the object as required by fence */
1907 /* Despite that we check this in framebuffer_init userspace can
1908 * screw us over and change the tiling after the fact. Only
1909 * pinned buffers can't change their tiling. */
1910 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1916 /* Note that the w/a also requires 64 PTE of padding following the
1917 * bo. We currently fill all unused PTE with the shadow page and so
1918 * we should always have valid PTE following the scanout preventing
1921 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
1922 alignment
= 256 * 1024;
1924 dev_priv
->mm
.interruptible
= false;
1925 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
);
1927 goto err_interruptible
;
1929 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1930 * fence, whereas 965+ only requires a fence if using
1931 * framebuffer compression. For simplicity, we always install
1932 * a fence as the cost is not that onerous.
1934 ret
= i915_gem_object_get_fence(obj
);
1938 i915_gem_object_pin_fence(obj
);
1940 dev_priv
->mm
.interruptible
= true;
1944 i915_gem_object_unpin(obj
);
1946 dev_priv
->mm
.interruptible
= true;
1950 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
)
1952 i915_gem_object_unpin_fence(obj
);
1953 i915_gem_object_unpin(obj
);
1956 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1957 * is assumed to be a power-of-two. */
1958 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
1959 unsigned int tiling_mode
,
1963 if (tiling_mode
!= I915_TILING_NONE
) {
1964 unsigned int tile_rows
, tiles
;
1969 tiles
= *x
/ (512/cpp
);
1972 return tile_rows
* pitch
* 8 + tiles
* 4096;
1974 unsigned int offset
;
1976 offset
= *y
* pitch
+ *x
* cpp
;
1978 *x
= (offset
& 4095) / cpp
;
1979 return offset
& -4096;
1983 static int i9xx_update_plane(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
1986 struct drm_device
*dev
= crtc
->dev
;
1987 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1988 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1989 struct intel_framebuffer
*intel_fb
;
1990 struct drm_i915_gem_object
*obj
;
1991 int plane
= intel_crtc
->plane
;
1992 unsigned long linear_offset
;
2001 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane
));
2005 intel_fb
= to_intel_framebuffer(fb
);
2006 obj
= intel_fb
->obj
;
2008 reg
= DSPCNTR(plane
);
2009 dspcntr
= I915_READ(reg
);
2010 /* Mask out pixel format bits in case we change it */
2011 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2012 switch (fb
->pixel_format
) {
2014 dspcntr
|= DISPPLANE_8BPP
;
2016 case DRM_FORMAT_XRGB1555
:
2017 case DRM_FORMAT_ARGB1555
:
2018 dspcntr
|= DISPPLANE_BGRX555
;
2020 case DRM_FORMAT_RGB565
:
2021 dspcntr
|= DISPPLANE_BGRX565
;
2023 case DRM_FORMAT_XRGB8888
:
2024 case DRM_FORMAT_ARGB8888
:
2025 dspcntr
|= DISPPLANE_BGRX888
;
2027 case DRM_FORMAT_XBGR8888
:
2028 case DRM_FORMAT_ABGR8888
:
2029 dspcntr
|= DISPPLANE_RGBX888
;
2031 case DRM_FORMAT_XRGB2101010
:
2032 case DRM_FORMAT_ARGB2101010
:
2033 dspcntr
|= DISPPLANE_BGRX101010
;
2035 case DRM_FORMAT_XBGR2101010
:
2036 case DRM_FORMAT_ABGR2101010
:
2037 dspcntr
|= DISPPLANE_RGBX101010
;
2043 if (INTEL_INFO(dev
)->gen
>= 4) {
2044 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2045 dspcntr
|= DISPPLANE_TILED
;
2047 dspcntr
&= ~DISPPLANE_TILED
;
2050 I915_WRITE(reg
, dspcntr
);
2052 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2054 if (INTEL_INFO(dev
)->gen
>= 4) {
2055 intel_crtc
->dspaddr_offset
=
2056 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2057 fb
->bits_per_pixel
/ 8,
2059 linear_offset
-= intel_crtc
->dspaddr_offset
;
2061 intel_crtc
->dspaddr_offset
= linear_offset
;
2064 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2065 obj
->gtt_offset
, linear_offset
, x
, y
, fb
->pitches
[0]);
2066 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2067 if (INTEL_INFO(dev
)->gen
>= 4) {
2068 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2069 obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
2070 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2071 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2073 I915_WRITE(DSPADDR(plane
), obj
->gtt_offset
+ linear_offset
);
2079 static int ironlake_update_plane(struct drm_crtc
*crtc
,
2080 struct drm_framebuffer
*fb
, int x
, int y
)
2082 struct drm_device
*dev
= crtc
->dev
;
2083 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2084 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2085 struct intel_framebuffer
*intel_fb
;
2086 struct drm_i915_gem_object
*obj
;
2087 int plane
= intel_crtc
->plane
;
2088 unsigned long linear_offset
;
2098 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane
));
2102 intel_fb
= to_intel_framebuffer(fb
);
2103 obj
= intel_fb
->obj
;
2105 reg
= DSPCNTR(plane
);
2106 dspcntr
= I915_READ(reg
);
2107 /* Mask out pixel format bits in case we change it */
2108 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2109 switch (fb
->pixel_format
) {
2111 dspcntr
|= DISPPLANE_8BPP
;
2113 case DRM_FORMAT_RGB565
:
2114 dspcntr
|= DISPPLANE_BGRX565
;
2116 case DRM_FORMAT_XRGB8888
:
2117 case DRM_FORMAT_ARGB8888
:
2118 dspcntr
|= DISPPLANE_BGRX888
;
2120 case DRM_FORMAT_XBGR8888
:
2121 case DRM_FORMAT_ABGR8888
:
2122 dspcntr
|= DISPPLANE_RGBX888
;
2124 case DRM_FORMAT_XRGB2101010
:
2125 case DRM_FORMAT_ARGB2101010
:
2126 dspcntr
|= DISPPLANE_BGRX101010
;
2128 case DRM_FORMAT_XBGR2101010
:
2129 case DRM_FORMAT_ABGR2101010
:
2130 dspcntr
|= DISPPLANE_RGBX101010
;
2136 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2137 dspcntr
|= DISPPLANE_TILED
;
2139 dspcntr
&= ~DISPPLANE_TILED
;
2142 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2144 I915_WRITE(reg
, dspcntr
);
2146 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2147 intel_crtc
->dspaddr_offset
=
2148 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2149 fb
->bits_per_pixel
/ 8,
2151 linear_offset
-= intel_crtc
->dspaddr_offset
;
2153 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2154 obj
->gtt_offset
, linear_offset
, x
, y
, fb
->pitches
[0]);
2155 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2156 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2157 obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
2158 if (IS_HASWELL(dev
)) {
2159 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2161 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2162 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2169 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2171 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2172 int x
, int y
, enum mode_set_atomic state
)
2174 struct drm_device
*dev
= crtc
->dev
;
2175 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2177 if (dev_priv
->display
.disable_fbc
)
2178 dev_priv
->display
.disable_fbc(dev
);
2179 intel_increase_pllclock(crtc
);
2181 return dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2184 void intel_display_handle_reset(struct drm_device
*dev
)
2186 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2187 struct drm_crtc
*crtc
;
2190 * Flips in the rings have been nuked by the reset,
2191 * so complete all pending flips so that user space
2192 * will get its events and not get stuck.
2194 * Also update the base address of all primary
2195 * planes to the the last fb to make sure we're
2196 * showing the correct fb after a reset.
2198 * Need to make two loops over the crtcs so that we
2199 * don't try to grab a crtc mutex before the
2200 * pending_flip_queue really got woken up.
2203 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2204 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2205 enum plane plane
= intel_crtc
->plane
;
2207 intel_prepare_page_flip(dev
, plane
);
2208 intel_finish_page_flip_plane(dev
, plane
);
2211 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2212 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2214 mutex_lock(&crtc
->mutex
);
2215 if (intel_crtc
->active
)
2216 dev_priv
->display
.update_plane(crtc
, crtc
->fb
,
2218 mutex_unlock(&crtc
->mutex
);
2223 intel_finish_fb(struct drm_framebuffer
*old_fb
)
2225 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(old_fb
)->obj
;
2226 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2227 bool was_interruptible
= dev_priv
->mm
.interruptible
;
2230 /* Big Hammer, we also need to ensure that any pending
2231 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2232 * current scanout is retired before unpinning the old
2235 * This should only fail upon a hung GPU, in which case we
2236 * can safely continue.
2238 dev_priv
->mm
.interruptible
= false;
2239 ret
= i915_gem_object_finish_gpu(obj
);
2240 dev_priv
->mm
.interruptible
= was_interruptible
;
2245 static void intel_crtc_update_sarea_pos(struct drm_crtc
*crtc
, int x
, int y
)
2247 struct drm_device
*dev
= crtc
->dev
;
2248 struct drm_i915_master_private
*master_priv
;
2249 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2251 if (!dev
->primary
->master
)
2254 master_priv
= dev
->primary
->master
->driver_priv
;
2255 if (!master_priv
->sarea_priv
)
2258 switch (intel_crtc
->pipe
) {
2260 master_priv
->sarea_priv
->pipeA_x
= x
;
2261 master_priv
->sarea_priv
->pipeA_y
= y
;
2264 master_priv
->sarea_priv
->pipeB_x
= x
;
2265 master_priv
->sarea_priv
->pipeB_y
= y
;
2273 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2274 struct drm_framebuffer
*fb
)
2276 struct drm_device
*dev
= crtc
->dev
;
2277 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2278 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2279 struct drm_framebuffer
*old_fb
;
2284 DRM_ERROR("No FB bound\n");
2288 if (intel_crtc
->plane
> INTEL_INFO(dev
)->num_pipes
) {
2289 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2290 plane_name(intel_crtc
->plane
),
2291 INTEL_INFO(dev
)->num_pipes
);
2295 mutex_lock(&dev
->struct_mutex
);
2296 ret
= intel_pin_and_fence_fb_obj(dev
,
2297 to_intel_framebuffer(fb
)->obj
,
2300 mutex_unlock(&dev
->struct_mutex
);
2301 DRM_ERROR("pin & fence failed\n");
2305 ret
= dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2307 intel_unpin_fb_obj(to_intel_framebuffer(fb
)->obj
);
2308 mutex_unlock(&dev
->struct_mutex
);
2309 DRM_ERROR("failed to update base address\n");
2319 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2320 intel_unpin_fb_obj(to_intel_framebuffer(old_fb
)->obj
);
2323 intel_update_fbc(dev
);
2324 mutex_unlock(&dev
->struct_mutex
);
2326 intel_crtc_update_sarea_pos(crtc
, x
, y
);
2331 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
2333 struct drm_device
*dev
= crtc
->dev
;
2334 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2335 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2336 int pipe
= intel_crtc
->pipe
;
2339 /* enable normal train */
2340 reg
= FDI_TX_CTL(pipe
);
2341 temp
= I915_READ(reg
);
2342 if (IS_IVYBRIDGE(dev
)) {
2343 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2344 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2346 temp
&= ~FDI_LINK_TRAIN_NONE
;
2347 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2349 I915_WRITE(reg
, temp
);
2351 reg
= FDI_RX_CTL(pipe
);
2352 temp
= I915_READ(reg
);
2353 if (HAS_PCH_CPT(dev
)) {
2354 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2355 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2357 temp
&= ~FDI_LINK_TRAIN_NONE
;
2358 temp
|= FDI_LINK_TRAIN_NONE
;
2360 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2362 /* wait one idle pattern time */
2366 /* IVB wants error correction enabled */
2367 if (IS_IVYBRIDGE(dev
))
2368 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
2369 FDI_FE_ERRC_ENABLE
);
2372 static void ivb_modeset_global_resources(struct drm_device
*dev
)
2374 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2375 struct intel_crtc
*pipe_B_crtc
=
2376 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
2377 struct intel_crtc
*pipe_C_crtc
=
2378 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]);
2381 /* When everything is off disable fdi C so that we could enable fdi B
2382 * with all lanes. XXX: This misses the case where a pipe is not using
2383 * any pch resources and so doesn't need any fdi lanes. */
2384 if (!pipe_B_crtc
->base
.enabled
&& !pipe_C_crtc
->base
.enabled
) {
2385 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
2386 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
2388 temp
= I915_READ(SOUTH_CHICKEN1
);
2389 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
2390 DRM_DEBUG_KMS("disabling fdi C rx\n");
2391 I915_WRITE(SOUTH_CHICKEN1
, temp
);
2395 /* The FDI link training functions for ILK/Ibexpeak. */
2396 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
2398 struct drm_device
*dev
= crtc
->dev
;
2399 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2400 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2401 int pipe
= intel_crtc
->pipe
;
2402 int plane
= intel_crtc
->plane
;
2403 u32 reg
, temp
, tries
;
2405 /* FDI needs bits from pipe & plane first */
2406 assert_pipe_enabled(dev_priv
, pipe
);
2407 assert_plane_enabled(dev_priv
, plane
);
2409 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2411 reg
= FDI_RX_IMR(pipe
);
2412 temp
= I915_READ(reg
);
2413 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2414 temp
&= ~FDI_RX_BIT_LOCK
;
2415 I915_WRITE(reg
, temp
);
2419 /* enable CPU FDI TX and PCH FDI RX */
2420 reg
= FDI_TX_CTL(pipe
);
2421 temp
= I915_READ(reg
);
2423 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2424 temp
&= ~FDI_LINK_TRAIN_NONE
;
2425 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2426 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2428 reg
= FDI_RX_CTL(pipe
);
2429 temp
= I915_READ(reg
);
2430 temp
&= ~FDI_LINK_TRAIN_NONE
;
2431 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2432 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2437 /* Ironlake workaround, enable clock pointer after FDI enable*/
2438 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2439 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
2440 FDI_RX_PHASE_SYNC_POINTER_EN
);
2442 reg
= FDI_RX_IIR(pipe
);
2443 for (tries
= 0; tries
< 5; tries
++) {
2444 temp
= I915_READ(reg
);
2445 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2447 if ((temp
& FDI_RX_BIT_LOCK
)) {
2448 DRM_DEBUG_KMS("FDI train 1 done.\n");
2449 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2454 DRM_ERROR("FDI train 1 fail!\n");
2457 reg
= FDI_TX_CTL(pipe
);
2458 temp
= I915_READ(reg
);
2459 temp
&= ~FDI_LINK_TRAIN_NONE
;
2460 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2461 I915_WRITE(reg
, temp
);
2463 reg
= FDI_RX_CTL(pipe
);
2464 temp
= I915_READ(reg
);
2465 temp
&= ~FDI_LINK_TRAIN_NONE
;
2466 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2467 I915_WRITE(reg
, temp
);
2472 reg
= FDI_RX_IIR(pipe
);
2473 for (tries
= 0; tries
< 5; tries
++) {
2474 temp
= I915_READ(reg
);
2475 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2477 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2478 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2479 DRM_DEBUG_KMS("FDI train 2 done.\n");
2484 DRM_ERROR("FDI train 2 fail!\n");
2486 DRM_DEBUG_KMS("FDI train done\n");
2490 static const int snb_b_fdi_train_param
[] = {
2491 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
2492 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
2493 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
2494 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
2497 /* The FDI link training functions for SNB/Cougarpoint. */
2498 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
2500 struct drm_device
*dev
= crtc
->dev
;
2501 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2502 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2503 int pipe
= intel_crtc
->pipe
;
2504 u32 reg
, temp
, i
, retry
;
2506 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2508 reg
= FDI_RX_IMR(pipe
);
2509 temp
= I915_READ(reg
);
2510 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2511 temp
&= ~FDI_RX_BIT_LOCK
;
2512 I915_WRITE(reg
, temp
);
2517 /* enable CPU FDI TX and PCH FDI RX */
2518 reg
= FDI_TX_CTL(pipe
);
2519 temp
= I915_READ(reg
);
2521 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2522 temp
&= ~FDI_LINK_TRAIN_NONE
;
2523 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2524 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2526 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2527 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2529 I915_WRITE(FDI_RX_MISC(pipe
),
2530 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2532 reg
= FDI_RX_CTL(pipe
);
2533 temp
= I915_READ(reg
);
2534 if (HAS_PCH_CPT(dev
)) {
2535 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2536 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2538 temp
&= ~FDI_LINK_TRAIN_NONE
;
2539 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2541 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2546 for (i
= 0; i
< 4; i
++) {
2547 reg
= FDI_TX_CTL(pipe
);
2548 temp
= I915_READ(reg
);
2549 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2550 temp
|= snb_b_fdi_train_param
[i
];
2551 I915_WRITE(reg
, temp
);
2556 for (retry
= 0; retry
< 5; retry
++) {
2557 reg
= FDI_RX_IIR(pipe
);
2558 temp
= I915_READ(reg
);
2559 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2560 if (temp
& FDI_RX_BIT_LOCK
) {
2561 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2562 DRM_DEBUG_KMS("FDI train 1 done.\n");
2571 DRM_ERROR("FDI train 1 fail!\n");
2574 reg
= FDI_TX_CTL(pipe
);
2575 temp
= I915_READ(reg
);
2576 temp
&= ~FDI_LINK_TRAIN_NONE
;
2577 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2579 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2581 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2583 I915_WRITE(reg
, temp
);
2585 reg
= FDI_RX_CTL(pipe
);
2586 temp
= I915_READ(reg
);
2587 if (HAS_PCH_CPT(dev
)) {
2588 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2589 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2591 temp
&= ~FDI_LINK_TRAIN_NONE
;
2592 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2594 I915_WRITE(reg
, temp
);
2599 for (i
= 0; i
< 4; i
++) {
2600 reg
= FDI_TX_CTL(pipe
);
2601 temp
= I915_READ(reg
);
2602 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2603 temp
|= snb_b_fdi_train_param
[i
];
2604 I915_WRITE(reg
, temp
);
2609 for (retry
= 0; retry
< 5; retry
++) {
2610 reg
= FDI_RX_IIR(pipe
);
2611 temp
= I915_READ(reg
);
2612 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2613 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2614 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2615 DRM_DEBUG_KMS("FDI train 2 done.\n");
2624 DRM_ERROR("FDI train 2 fail!\n");
2626 DRM_DEBUG_KMS("FDI train done.\n");
2629 /* Manual link training for Ivy Bridge A0 parts */
2630 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
2632 struct drm_device
*dev
= crtc
->dev
;
2633 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2634 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2635 int pipe
= intel_crtc
->pipe
;
2638 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2640 reg
= FDI_RX_IMR(pipe
);
2641 temp
= I915_READ(reg
);
2642 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2643 temp
&= ~FDI_RX_BIT_LOCK
;
2644 I915_WRITE(reg
, temp
);
2649 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2650 I915_READ(FDI_RX_IIR(pipe
)));
2652 /* enable CPU FDI TX and PCH FDI RX */
2653 reg
= FDI_TX_CTL(pipe
);
2654 temp
= I915_READ(reg
);
2656 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2657 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
2658 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
2659 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2660 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2661 temp
|= FDI_COMPOSITE_SYNC
;
2662 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2664 I915_WRITE(FDI_RX_MISC(pipe
),
2665 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2667 reg
= FDI_RX_CTL(pipe
);
2668 temp
= I915_READ(reg
);
2669 temp
&= ~FDI_LINK_TRAIN_AUTO
;
2670 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2671 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2672 temp
|= FDI_COMPOSITE_SYNC
;
2673 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2678 for (i
= 0; i
< 4; i
++) {
2679 reg
= FDI_TX_CTL(pipe
);
2680 temp
= I915_READ(reg
);
2681 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2682 temp
|= snb_b_fdi_train_param
[i
];
2683 I915_WRITE(reg
, temp
);
2688 reg
= FDI_RX_IIR(pipe
);
2689 temp
= I915_READ(reg
);
2690 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2692 if (temp
& FDI_RX_BIT_LOCK
||
2693 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
2694 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2695 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i
);
2700 DRM_ERROR("FDI train 1 fail!\n");
2703 reg
= FDI_TX_CTL(pipe
);
2704 temp
= I915_READ(reg
);
2705 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2706 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
2707 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2708 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2709 I915_WRITE(reg
, temp
);
2711 reg
= FDI_RX_CTL(pipe
);
2712 temp
= I915_READ(reg
);
2713 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2714 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2715 I915_WRITE(reg
, temp
);
2720 for (i
= 0; i
< 4; i
++) {
2721 reg
= FDI_TX_CTL(pipe
);
2722 temp
= I915_READ(reg
);
2723 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2724 temp
|= snb_b_fdi_train_param
[i
];
2725 I915_WRITE(reg
, temp
);
2730 reg
= FDI_RX_IIR(pipe
);
2731 temp
= I915_READ(reg
);
2732 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2734 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2735 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2736 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i
);
2741 DRM_ERROR("FDI train 2 fail!\n");
2743 DRM_DEBUG_KMS("FDI train done.\n");
2746 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
2748 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2749 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2750 int pipe
= intel_crtc
->pipe
;
2754 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2755 reg
= FDI_RX_CTL(pipe
);
2756 temp
= I915_READ(reg
);
2757 temp
&= ~((0x7 << 19) | (0x7 << 16));
2758 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2759 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2760 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
2765 /* Switch from Rawclk to PCDclk */
2766 temp
= I915_READ(reg
);
2767 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
2772 /* Enable CPU FDI TX PLL, always on for Ironlake */
2773 reg
= FDI_TX_CTL(pipe
);
2774 temp
= I915_READ(reg
);
2775 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
2776 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
2783 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
2785 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2786 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2787 int pipe
= intel_crtc
->pipe
;
2790 /* Switch from PCDclk to Rawclk */
2791 reg
= FDI_RX_CTL(pipe
);
2792 temp
= I915_READ(reg
);
2793 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
2795 /* Disable CPU FDI TX PLL */
2796 reg
= FDI_TX_CTL(pipe
);
2797 temp
= I915_READ(reg
);
2798 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
2803 reg
= FDI_RX_CTL(pipe
);
2804 temp
= I915_READ(reg
);
2805 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
2807 /* Wait for the clocks to turn off. */
2812 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
2814 struct drm_device
*dev
= crtc
->dev
;
2815 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2816 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2817 int pipe
= intel_crtc
->pipe
;
2820 /* disable CPU FDI tx and PCH FDI rx */
2821 reg
= FDI_TX_CTL(pipe
);
2822 temp
= I915_READ(reg
);
2823 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
2826 reg
= FDI_RX_CTL(pipe
);
2827 temp
= I915_READ(reg
);
2828 temp
&= ~(0x7 << 16);
2829 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2830 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
2835 /* Ironlake workaround, disable clock pointer after downing FDI */
2836 if (HAS_PCH_IBX(dev
)) {
2837 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2840 /* still set train pattern 1 */
2841 reg
= FDI_TX_CTL(pipe
);
2842 temp
= I915_READ(reg
);
2843 temp
&= ~FDI_LINK_TRAIN_NONE
;
2844 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2845 I915_WRITE(reg
, temp
);
2847 reg
= FDI_RX_CTL(pipe
);
2848 temp
= I915_READ(reg
);
2849 if (HAS_PCH_CPT(dev
)) {
2850 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2851 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2853 temp
&= ~FDI_LINK_TRAIN_NONE
;
2854 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2856 /* BPC in FDI rx is consistent with that in PIPECONF */
2857 temp
&= ~(0x07 << 16);
2858 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2859 I915_WRITE(reg
, temp
);
2865 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
2867 struct drm_device
*dev
= crtc
->dev
;
2868 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2869 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2870 unsigned long flags
;
2873 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
2874 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
2877 spin_lock_irqsave(&dev
->event_lock
, flags
);
2878 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
2879 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2884 static void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
2886 struct drm_device
*dev
= crtc
->dev
;
2887 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2889 if (crtc
->fb
== NULL
)
2892 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
2894 wait_event(dev_priv
->pending_flip_queue
,
2895 !intel_crtc_has_pending_flip(crtc
));
2897 mutex_lock(&dev
->struct_mutex
);
2898 intel_finish_fb(crtc
->fb
);
2899 mutex_unlock(&dev
->struct_mutex
);
2902 /* Program iCLKIP clock to the desired frequency */
2903 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
2905 struct drm_device
*dev
= crtc
->dev
;
2906 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2907 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
2910 mutex_lock(&dev_priv
->dpio_lock
);
2912 /* It is necessary to ungate the pixclk gate prior to programming
2913 * the divisors, and gate it back when it is done.
2915 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
2917 /* Disable SSCCTL */
2918 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
2919 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
2923 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2924 if (crtc
->mode
.clock
== 20000) {
2929 /* The iCLK virtual clock root frequency is in MHz,
2930 * but the crtc->mode.clock in in KHz. To get the divisors,
2931 * it is necessary to divide one by another, so we
2932 * convert the virtual clock precision to KHz here for higher
2935 u32 iclk_virtual_root_freq
= 172800 * 1000;
2936 u32 iclk_pi_range
= 64;
2937 u32 desired_divisor
, msb_divisor_value
, pi_value
;
2939 desired_divisor
= (iclk_virtual_root_freq
/ crtc
->mode
.clock
);
2940 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
2941 pi_value
= desired_divisor
% iclk_pi_range
;
2944 divsel
= msb_divisor_value
- 2;
2945 phaseinc
= pi_value
;
2948 /* This should not happen with any sane values */
2949 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
2950 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
2951 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
2952 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
2954 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2961 /* Program SSCDIVINTPHASE6 */
2962 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
2963 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
2964 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
2965 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
2966 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
2967 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
2968 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
2969 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
2971 /* Program SSCAUXDIV */
2972 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
2973 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2974 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
2975 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
2977 /* Enable modulator and associated divider */
2978 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
2979 temp
&= ~SBI_SSCCTL_DISABLE
;
2980 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
2982 /* Wait for initialization time */
2985 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
2987 mutex_unlock(&dev_priv
->dpio_lock
);
2991 * Enable PCH resources required for PCH ports:
2993 * - FDI training & RX/TX
2994 * - update transcoder timings
2995 * - DP transcoding bits
2998 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
3000 struct drm_device
*dev
= crtc
->dev
;
3001 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3002 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3003 int pipe
= intel_crtc
->pipe
;
3006 assert_transcoder_disabled(dev_priv
, pipe
);
3008 /* Write the TU size bits before fdi link training, so that error
3009 * detection works. */
3010 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
3011 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
3013 /* For PCH output, training FDI link */
3014 dev_priv
->display
.fdi_link_train(crtc
);
3016 /* XXX: pch pll's can be enabled any time before we enable the PCH
3017 * transcoder, and we actually should do this to not upset any PCH
3018 * transcoder that already use the clock when we share it.
3020 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3021 * unconditionally resets the pll - we need that to have the right LVDS
3022 * enable sequence. */
3023 ironlake_enable_pch_pll(intel_crtc
);
3025 if (HAS_PCH_CPT(dev
)) {
3028 temp
= I915_READ(PCH_DPLL_SEL
);
3032 temp
|= TRANSA_DPLL_ENABLE
;
3033 sel
= TRANSA_DPLLB_SEL
;
3036 temp
|= TRANSB_DPLL_ENABLE
;
3037 sel
= TRANSB_DPLLB_SEL
;
3040 temp
|= TRANSC_DPLL_ENABLE
;
3041 sel
= TRANSC_DPLLB_SEL
;
3044 if (intel_crtc
->pch_pll
->pll_reg
== _PCH_DPLL_B
)
3048 I915_WRITE(PCH_DPLL_SEL
, temp
);
3051 /* set transcoder timing, panel must allow it */
3052 assert_panel_unlocked(dev_priv
, pipe
);
3053 I915_WRITE(TRANS_HTOTAL(pipe
), I915_READ(HTOTAL(pipe
)));
3054 I915_WRITE(TRANS_HBLANK(pipe
), I915_READ(HBLANK(pipe
)));
3055 I915_WRITE(TRANS_HSYNC(pipe
), I915_READ(HSYNC(pipe
)));
3057 I915_WRITE(TRANS_VTOTAL(pipe
), I915_READ(VTOTAL(pipe
)));
3058 I915_WRITE(TRANS_VBLANK(pipe
), I915_READ(VBLANK(pipe
)));
3059 I915_WRITE(TRANS_VSYNC(pipe
), I915_READ(VSYNC(pipe
)));
3060 I915_WRITE(TRANS_VSYNCSHIFT(pipe
), I915_READ(VSYNCSHIFT(pipe
)));
3062 intel_fdi_normal_train(crtc
);
3064 /* For PCH DP, enable TRANS_DP_CTL */
3065 if (HAS_PCH_CPT(dev
) &&
3066 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
3067 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3068 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
3069 reg
= TRANS_DP_CTL(pipe
);
3070 temp
= I915_READ(reg
);
3071 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
3072 TRANS_DP_SYNC_MASK
|
3074 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
3075 TRANS_DP_ENH_FRAMING
);
3076 temp
|= bpc
<< 9; /* same format but at 11:9 */
3078 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
3079 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
3080 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
3081 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
3083 switch (intel_trans_dp_port_sel(crtc
)) {
3085 temp
|= TRANS_DP_PORT_SEL_B
;
3088 temp
|= TRANS_DP_PORT_SEL_C
;
3091 temp
|= TRANS_DP_PORT_SEL_D
;
3097 I915_WRITE(reg
, temp
);
3100 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
3103 static void lpt_pch_enable(struct drm_crtc
*crtc
)
3105 struct drm_device
*dev
= crtc
->dev
;
3106 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3107 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3108 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
3110 assert_transcoder_disabled(dev_priv
, TRANSCODER_A
);
3112 lpt_program_iclkip(crtc
);
3114 /* Set transcoder timing. */
3115 I915_WRITE(_TRANS_HTOTAL_A
, I915_READ(HTOTAL(cpu_transcoder
)));
3116 I915_WRITE(_TRANS_HBLANK_A
, I915_READ(HBLANK(cpu_transcoder
)));
3117 I915_WRITE(_TRANS_HSYNC_A
, I915_READ(HSYNC(cpu_transcoder
)));
3119 I915_WRITE(_TRANS_VTOTAL_A
, I915_READ(VTOTAL(cpu_transcoder
)));
3120 I915_WRITE(_TRANS_VBLANK_A
, I915_READ(VBLANK(cpu_transcoder
)));
3121 I915_WRITE(_TRANS_VSYNC_A
, I915_READ(VSYNC(cpu_transcoder
)));
3122 I915_WRITE(_TRANS_VSYNCSHIFT_A
, I915_READ(VSYNCSHIFT(cpu_transcoder
)));
3124 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
3127 static void intel_put_pch_pll(struct intel_crtc
*intel_crtc
)
3129 struct intel_pch_pll
*pll
= intel_crtc
->pch_pll
;
3134 if (pll
->refcount
== 0) {
3135 WARN(1, "bad PCH PLL refcount\n");
3140 intel_crtc
->pch_pll
= NULL
;
3143 static struct intel_pch_pll
*intel_get_pch_pll(struct intel_crtc
*intel_crtc
, u32 dpll
, u32 fp
)
3145 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
3146 struct intel_pch_pll
*pll
;
3149 pll
= intel_crtc
->pch_pll
;
3151 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3152 intel_crtc
->base
.base
.id
, pll
->pll_reg
);
3156 if (HAS_PCH_IBX(dev_priv
->dev
)) {
3157 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3158 i
= intel_crtc
->pipe
;
3159 pll
= &dev_priv
->pch_plls
[i
];
3161 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3162 intel_crtc
->base
.base
.id
, pll
->pll_reg
);
3167 for (i
= 0; i
< dev_priv
->num_pch_pll
; i
++) {
3168 pll
= &dev_priv
->pch_plls
[i
];
3170 /* Only want to check enabled timings first */
3171 if (pll
->refcount
== 0)
3174 if (dpll
== (I915_READ(pll
->pll_reg
) & 0x7fffffff) &&
3175 fp
== I915_READ(pll
->fp0_reg
)) {
3176 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3177 intel_crtc
->base
.base
.id
,
3178 pll
->pll_reg
, pll
->refcount
, pll
->active
);
3184 /* Ok no matching timings, maybe there's a free one? */
3185 for (i
= 0; i
< dev_priv
->num_pch_pll
; i
++) {
3186 pll
= &dev_priv
->pch_plls
[i
];
3187 if (pll
->refcount
== 0) {
3188 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3189 intel_crtc
->base
.base
.id
, pll
->pll_reg
);
3197 intel_crtc
->pch_pll
= pll
;
3199 DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i
, pipe_name(intel_crtc
->pipe
));
3200 prepare
: /* separate function? */
3201 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll
->pll_reg
);
3203 /* Wait for the clocks to stabilize before rewriting the regs */
3204 I915_WRITE(pll
->pll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
3205 POSTING_READ(pll
->pll_reg
);
3208 I915_WRITE(pll
->fp0_reg
, fp
);
3209 I915_WRITE(pll
->pll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
3214 void intel_cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
3216 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3217 int dslreg
= PIPEDSL(pipe
);
3220 temp
= I915_READ(dslreg
);
3222 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
3223 if (wait_for(I915_READ(dslreg
) != temp
, 5))
3224 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
3228 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
3230 struct drm_device
*dev
= crtc
->dev
;
3231 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3232 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3233 struct intel_encoder
*encoder
;
3234 int pipe
= intel_crtc
->pipe
;
3235 int plane
= intel_crtc
->plane
;
3238 WARN_ON(!crtc
->enabled
);
3240 if (intel_crtc
->active
)
3243 intel_crtc
->active
= true;
3245 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
3246 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
3248 intel_update_watermarks(dev
);
3250 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
3251 temp
= I915_READ(PCH_LVDS
);
3252 if ((temp
& LVDS_PORT_EN
) == 0)
3253 I915_WRITE(PCH_LVDS
, temp
| LVDS_PORT_EN
);
3257 if (intel_crtc
->config
.has_pch_encoder
) {
3258 /* Note: FDI PLL enabling _must_ be done before we enable the
3259 * cpu pipes, hence this is separate from all the other fdi/pch
3261 ironlake_fdi_pll_enable(intel_crtc
);
3263 assert_fdi_tx_disabled(dev_priv
, pipe
);
3264 assert_fdi_rx_disabled(dev_priv
, pipe
);
3267 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3268 if (encoder
->pre_enable
)
3269 encoder
->pre_enable(encoder
);
3271 /* Enable panel fitting for LVDS */
3272 if (dev_priv
->pch_pf_size
&&
3273 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) ||
3274 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3275 /* Force use of hard-coded filter coefficients
3276 * as some pre-programmed values are broken,
3279 if (IS_IVYBRIDGE(dev
))
3280 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
3281 PF_PIPE_SEL_IVB(pipe
));
3283 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
3284 I915_WRITE(PF_WIN_POS(pipe
), dev_priv
->pch_pf_pos
);
3285 I915_WRITE(PF_WIN_SZ(pipe
), dev_priv
->pch_pf_size
);
3289 * On ILK+ LUT must be loaded before the pipe is running but with
3292 intel_crtc_load_lut(crtc
);
3294 intel_enable_pipe(dev_priv
, pipe
,
3295 intel_crtc
->config
.has_pch_encoder
);
3296 intel_enable_plane(dev_priv
, plane
, pipe
);
3298 if (intel_crtc
->config
.has_pch_encoder
)
3299 ironlake_pch_enable(crtc
);
3301 mutex_lock(&dev
->struct_mutex
);
3302 intel_update_fbc(dev
);
3303 mutex_unlock(&dev
->struct_mutex
);
3305 intel_crtc_update_cursor(crtc
, true);
3307 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3308 encoder
->enable(encoder
);
3310 if (HAS_PCH_CPT(dev
))
3311 intel_cpt_verify_modeset(dev
, intel_crtc
->pipe
);
3314 * There seems to be a race in PCH platform hw (at least on some
3315 * outputs) where an enabled pipe still completes any pageflip right
3316 * away (as if the pipe is off) instead of waiting for vblank. As soon
3317 * as the first vblank happend, everything works as expected. Hence just
3318 * wait for one vblank before returning to avoid strange things
3321 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3324 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
3326 struct drm_device
*dev
= crtc
->dev
;
3327 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3328 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3329 struct intel_encoder
*encoder
;
3330 int pipe
= intel_crtc
->pipe
;
3331 int plane
= intel_crtc
->plane
;
3333 WARN_ON(!crtc
->enabled
);
3335 if (intel_crtc
->active
)
3338 intel_crtc
->active
= true;
3340 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
3341 if (intel_crtc
->config
.has_pch_encoder
)
3342 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
3344 intel_update_watermarks(dev
);
3346 if (intel_crtc
->config
.has_pch_encoder
)
3347 dev_priv
->display
.fdi_link_train(crtc
);
3349 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3350 if (encoder
->pre_enable
)
3351 encoder
->pre_enable(encoder
);
3353 intel_ddi_enable_pipe_clock(intel_crtc
);
3355 /* Enable panel fitting for eDP */
3356 if (dev_priv
->pch_pf_size
&&
3357 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
)) {
3358 /* Force use of hard-coded filter coefficients
3359 * as some pre-programmed values are broken,
3362 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
3363 PF_PIPE_SEL_IVB(pipe
));
3364 I915_WRITE(PF_WIN_POS(pipe
), dev_priv
->pch_pf_pos
);
3365 I915_WRITE(PF_WIN_SZ(pipe
), dev_priv
->pch_pf_size
);
3369 * On ILK+ LUT must be loaded before the pipe is running but with
3372 intel_crtc_load_lut(crtc
);
3374 intel_ddi_set_pipe_settings(crtc
);
3375 intel_ddi_enable_transcoder_func(crtc
);
3377 intel_enable_pipe(dev_priv
, pipe
,
3378 intel_crtc
->config
.has_pch_encoder
);
3379 intel_enable_plane(dev_priv
, plane
, pipe
);
3381 if (intel_crtc
->config
.has_pch_encoder
)
3382 lpt_pch_enable(crtc
);
3384 mutex_lock(&dev
->struct_mutex
);
3385 intel_update_fbc(dev
);
3386 mutex_unlock(&dev
->struct_mutex
);
3388 intel_crtc_update_cursor(crtc
, true);
3390 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3391 encoder
->enable(encoder
);
3394 * There seems to be a race in PCH platform hw (at least on some
3395 * outputs) where an enabled pipe still completes any pageflip right
3396 * away (as if the pipe is off) instead of waiting for vblank. As soon
3397 * as the first vblank happend, everything works as expected. Hence just
3398 * wait for one vblank before returning to avoid strange things
3401 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3404 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
3406 struct drm_device
*dev
= crtc
->dev
;
3407 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3408 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3409 struct intel_encoder
*encoder
;
3410 int pipe
= intel_crtc
->pipe
;
3411 int plane
= intel_crtc
->plane
;
3415 if (!intel_crtc
->active
)
3418 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3419 encoder
->disable(encoder
);
3421 intel_crtc_wait_for_pending_flips(crtc
);
3422 drm_vblank_off(dev
, pipe
);
3423 intel_crtc_update_cursor(crtc
, false);
3425 intel_disable_plane(dev_priv
, plane
, pipe
);
3427 if (dev_priv
->cfb_plane
== plane
)
3428 intel_disable_fbc(dev
);
3430 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, false);
3431 intel_disable_pipe(dev_priv
, pipe
);
3434 I915_WRITE(PF_CTL(pipe
), 0);
3435 I915_WRITE(PF_WIN_SZ(pipe
), 0);
3437 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3438 if (encoder
->post_disable
)
3439 encoder
->post_disable(encoder
);
3441 ironlake_fdi_disable(crtc
);
3443 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
3444 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
3446 if (HAS_PCH_CPT(dev
)) {
3447 /* disable TRANS_DP_CTL */
3448 reg
= TRANS_DP_CTL(pipe
);
3449 temp
= I915_READ(reg
);
3450 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
| TRANS_DP_PORT_SEL_MASK
);
3451 temp
|= TRANS_DP_PORT_SEL_NONE
;
3452 I915_WRITE(reg
, temp
);
3454 /* disable DPLL_SEL */
3455 temp
= I915_READ(PCH_DPLL_SEL
);
3458 temp
&= ~(TRANSA_DPLL_ENABLE
| TRANSA_DPLLB_SEL
);
3461 temp
&= ~(TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
);
3464 /* C shares PLL A or B */
3465 temp
&= ~(TRANSC_DPLL_ENABLE
| TRANSC_DPLLB_SEL
);
3470 I915_WRITE(PCH_DPLL_SEL
, temp
);
3473 /* disable PCH DPLL */
3474 intel_disable_pch_pll(intel_crtc
);
3476 ironlake_fdi_pll_disable(intel_crtc
);
3478 intel_crtc
->active
= false;
3479 intel_update_watermarks(dev
);
3481 mutex_lock(&dev
->struct_mutex
);
3482 intel_update_fbc(dev
);
3483 mutex_unlock(&dev
->struct_mutex
);
3486 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
3488 struct drm_device
*dev
= crtc
->dev
;
3489 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3490 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3491 struct intel_encoder
*encoder
;
3492 int pipe
= intel_crtc
->pipe
;
3493 int plane
= intel_crtc
->plane
;
3494 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
3496 if (!intel_crtc
->active
)
3499 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3500 encoder
->disable(encoder
);
3502 intel_crtc_wait_for_pending_flips(crtc
);
3503 drm_vblank_off(dev
, pipe
);
3504 intel_crtc_update_cursor(crtc
, false);
3506 intel_disable_plane(dev_priv
, plane
, pipe
);
3508 if (dev_priv
->cfb_plane
== plane
)
3509 intel_disable_fbc(dev
);
3511 if (intel_crtc
->config
.has_pch_encoder
)
3512 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, false);
3513 intel_disable_pipe(dev_priv
, pipe
);
3515 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
3517 /* XXX: Once we have proper panel fitter state tracking implemented with
3518 * hardware state read/check support we should switch to only disable
3519 * the panel fitter when we know it's used. */
3520 if (intel_using_power_well(dev
)) {
3521 I915_WRITE(PF_CTL(pipe
), 0);
3522 I915_WRITE(PF_WIN_SZ(pipe
), 0);
3525 intel_ddi_disable_pipe_clock(intel_crtc
);
3527 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3528 if (encoder
->post_disable
)
3529 encoder
->post_disable(encoder
);
3531 if (intel_crtc
->config
.has_pch_encoder
) {
3532 lpt_disable_pch_transcoder(dev_priv
);
3533 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
3534 intel_ddi_fdi_disable(crtc
);
3537 intel_crtc
->active
= false;
3538 intel_update_watermarks(dev
);
3540 mutex_lock(&dev
->struct_mutex
);
3541 intel_update_fbc(dev
);
3542 mutex_unlock(&dev
->struct_mutex
);
3545 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
3547 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3548 intel_put_pch_pll(intel_crtc
);
3551 static void haswell_crtc_off(struct drm_crtc
*crtc
)
3553 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3555 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3556 * start using it. */
3557 intel_crtc
->config
.cpu_transcoder
= (enum transcoder
) intel_crtc
->pipe
;
3559 intel_ddi_put_crtc_pll(crtc
);
3562 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
3564 if (!enable
&& intel_crtc
->overlay
) {
3565 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3566 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3568 mutex_lock(&dev
->struct_mutex
);
3569 dev_priv
->mm
.interruptible
= false;
3570 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
3571 dev_priv
->mm
.interruptible
= true;
3572 mutex_unlock(&dev
->struct_mutex
);
3575 /* Let userspace switch the overlay on again. In most cases userspace
3576 * has to recompute where to put it anyway.
3581 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3582 * cursor plane briefly if not already running after enabling the display
3584 * This workaround avoids occasional blank screens when self refresh is
3588 g4x_fixup_plane(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
3590 u32 cntl
= I915_READ(CURCNTR(pipe
));
3592 if ((cntl
& CURSOR_MODE
) == 0) {
3593 u32 fw_bcl_self
= I915_READ(FW_BLC_SELF
);
3595 I915_WRITE(FW_BLC_SELF
, fw_bcl_self
& ~FW_BLC_SELF_EN
);
3596 I915_WRITE(CURCNTR(pipe
), CURSOR_MODE_64_ARGB_AX
);
3597 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
3598 I915_WRITE(CURCNTR(pipe
), cntl
);
3599 I915_WRITE(CURBASE(pipe
), I915_READ(CURBASE(pipe
)));
3600 I915_WRITE(FW_BLC_SELF
, fw_bcl_self
);
3604 static void valleyview_crtc_enable(struct drm_crtc
*crtc
)
3606 struct drm_device
*dev
= crtc
->dev
;
3607 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3608 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3609 struct intel_encoder
*encoder
;
3610 int pipe
= intel_crtc
->pipe
;
3611 int plane
= intel_crtc
->plane
;
3613 WARN_ON(!crtc
->enabled
);
3615 if (intel_crtc
->active
)
3618 intel_crtc
->active
= true;
3619 intel_update_watermarks(dev
);
3621 mutex_lock(&dev_priv
->dpio_lock
);
3623 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3624 if (encoder
->pre_pll_enable
)
3625 encoder
->pre_pll_enable(encoder
);
3627 intel_enable_pll(dev_priv
, pipe
);
3629 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3630 if (encoder
->pre_enable
)
3631 encoder
->pre_enable(encoder
);
3633 /* VLV wants encoder enabling _before_ the pipe is up. */
3634 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3635 encoder
->enable(encoder
);
3637 intel_enable_pipe(dev_priv
, pipe
, false);
3638 intel_enable_plane(dev_priv
, plane
, pipe
);
3640 intel_crtc_load_lut(crtc
);
3641 intel_update_fbc(dev
);
3643 /* Give the overlay scaler a chance to enable if it's on this pipe */
3644 intel_crtc_dpms_overlay(intel_crtc
, true);
3645 intel_crtc_update_cursor(crtc
, true);
3647 mutex_unlock(&dev_priv
->dpio_lock
);
3650 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
3652 struct drm_device
*dev
= crtc
->dev
;
3653 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3654 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3655 struct intel_encoder
*encoder
;
3656 int pipe
= intel_crtc
->pipe
;
3657 int plane
= intel_crtc
->plane
;
3659 WARN_ON(!crtc
->enabled
);
3661 if (intel_crtc
->active
)
3664 intel_crtc
->active
= true;
3665 intel_update_watermarks(dev
);
3667 intel_enable_pll(dev_priv
, pipe
);
3669 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3670 if (encoder
->pre_enable
)
3671 encoder
->pre_enable(encoder
);
3673 intel_enable_pipe(dev_priv
, pipe
, false);
3674 intel_enable_plane(dev_priv
, plane
, pipe
);
3676 g4x_fixup_plane(dev_priv
, pipe
);
3678 intel_crtc_load_lut(crtc
);
3679 intel_update_fbc(dev
);
3681 /* Give the overlay scaler a chance to enable if it's on this pipe */
3682 intel_crtc_dpms_overlay(intel_crtc
, true);
3683 intel_crtc_update_cursor(crtc
, true);
3685 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3686 encoder
->enable(encoder
);
3689 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
3691 struct drm_device
*dev
= crtc
->base
.dev
;
3692 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3694 uint32_t pctl
= I915_READ(PFIT_CONTROL
);
3696 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
3698 if (INTEL_INFO(dev
)->gen
>= 4)
3699 pipe
= (pctl
& PFIT_PIPE_MASK
) >> PFIT_PIPE_SHIFT
;
3703 if (pipe
== crtc
->pipe
) {
3704 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", pctl
);
3705 I915_WRITE(PFIT_CONTROL
, 0);
3709 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
3711 struct drm_device
*dev
= crtc
->dev
;
3712 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3713 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3714 struct intel_encoder
*encoder
;
3715 int pipe
= intel_crtc
->pipe
;
3716 int plane
= intel_crtc
->plane
;
3718 if (!intel_crtc
->active
)
3721 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3722 encoder
->disable(encoder
);
3724 /* Give the overlay scaler a chance to disable if it's on this pipe */
3725 intel_crtc_wait_for_pending_flips(crtc
);
3726 drm_vblank_off(dev
, pipe
);
3727 intel_crtc_dpms_overlay(intel_crtc
, false);
3728 intel_crtc_update_cursor(crtc
, false);
3730 if (dev_priv
->cfb_plane
== plane
)
3731 intel_disable_fbc(dev
);
3733 intel_disable_plane(dev_priv
, plane
, pipe
);
3734 intel_disable_pipe(dev_priv
, pipe
);
3736 i9xx_pfit_disable(intel_crtc
);
3738 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3739 if (encoder
->post_disable
)
3740 encoder
->post_disable(encoder
);
3742 intel_disable_pll(dev_priv
, pipe
);
3744 intel_crtc
->active
= false;
3745 intel_update_fbc(dev
);
3746 intel_update_watermarks(dev
);
3749 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
3753 static void intel_crtc_update_sarea(struct drm_crtc
*crtc
,
3756 struct drm_device
*dev
= crtc
->dev
;
3757 struct drm_i915_master_private
*master_priv
;
3758 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3759 int pipe
= intel_crtc
->pipe
;
3761 if (!dev
->primary
->master
)
3764 master_priv
= dev
->primary
->master
->driver_priv
;
3765 if (!master_priv
->sarea_priv
)
3770 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3771 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3774 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3775 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3778 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe
));
3784 * Sets the power management mode of the pipe and plane.
3786 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
3788 struct drm_device
*dev
= crtc
->dev
;
3789 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3790 struct intel_encoder
*intel_encoder
;
3791 bool enable
= false;
3793 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
3794 enable
|= intel_encoder
->connectors_active
;
3797 dev_priv
->display
.crtc_enable(crtc
);
3799 dev_priv
->display
.crtc_disable(crtc
);
3801 intel_crtc_update_sarea(crtc
, enable
);
3804 static void intel_crtc_disable(struct drm_crtc
*crtc
)
3806 struct drm_device
*dev
= crtc
->dev
;
3807 struct drm_connector
*connector
;
3808 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3809 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3811 /* crtc should still be enabled when we disable it. */
3812 WARN_ON(!crtc
->enabled
);
3814 intel_crtc
->eld_vld
= false;
3815 dev_priv
->display
.crtc_disable(crtc
);
3816 intel_crtc_update_sarea(crtc
, false);
3817 dev_priv
->display
.off(crtc
);
3819 assert_plane_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->plane
);
3820 assert_pipe_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->pipe
);
3823 mutex_lock(&dev
->struct_mutex
);
3824 intel_unpin_fb_obj(to_intel_framebuffer(crtc
->fb
)->obj
);
3825 mutex_unlock(&dev
->struct_mutex
);
3829 /* Update computed state. */
3830 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
3831 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
3834 if (connector
->encoder
->crtc
!= crtc
)
3837 connector
->dpms
= DRM_MODE_DPMS_OFF
;
3838 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
3842 void intel_modeset_disable(struct drm_device
*dev
)
3844 struct drm_crtc
*crtc
;
3846 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
3848 intel_crtc_disable(crtc
);
3852 void intel_encoder_destroy(struct drm_encoder
*encoder
)
3854 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
3856 drm_encoder_cleanup(encoder
);
3857 kfree(intel_encoder
);
3860 /* Simple dpms helper for encodres with just one connector, no cloning and only
3861 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3862 * state of the entire output pipe. */
3863 void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
3865 if (mode
== DRM_MODE_DPMS_ON
) {
3866 encoder
->connectors_active
= true;
3868 intel_crtc_update_dpms(encoder
->base
.crtc
);
3870 encoder
->connectors_active
= false;
3872 intel_crtc_update_dpms(encoder
->base
.crtc
);
3876 /* Cross check the actual hw state with our own modeset state tracking (and it's
3877 * internal consistency). */
3878 static void intel_connector_check_state(struct intel_connector
*connector
)
3880 if (connector
->get_hw_state(connector
)) {
3881 struct intel_encoder
*encoder
= connector
->encoder
;
3882 struct drm_crtc
*crtc
;
3883 bool encoder_enabled
;
3886 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3887 connector
->base
.base
.id
,
3888 drm_get_connector_name(&connector
->base
));
3890 WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
3891 "wrong connector dpms state\n");
3892 WARN(connector
->base
.encoder
!= &encoder
->base
,
3893 "active connector not linked to encoder\n");
3894 WARN(!encoder
->connectors_active
,
3895 "encoder->connectors_active not set\n");
3897 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
3898 WARN(!encoder_enabled
, "encoder not enabled\n");
3899 if (WARN_ON(!encoder
->base
.crtc
))
3902 crtc
= encoder
->base
.crtc
;
3904 WARN(!crtc
->enabled
, "crtc not enabled\n");
3905 WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
3906 WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
3907 "encoder active on the wrong pipe\n");
3911 /* Even simpler default implementation, if there's really no special case to
3913 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
3915 struct intel_encoder
*encoder
= intel_attached_encoder(connector
);
3917 /* All the simple cases only support two dpms states. */
3918 if (mode
!= DRM_MODE_DPMS_ON
)
3919 mode
= DRM_MODE_DPMS_OFF
;
3921 if (mode
== connector
->dpms
)
3924 connector
->dpms
= mode
;
3926 /* Only need to change hw state when actually enabled */
3927 if (encoder
->base
.crtc
)
3928 intel_encoder_dpms(encoder
, mode
);
3930 WARN_ON(encoder
->connectors_active
!= false);
3932 intel_modeset_check_state(connector
->dev
);
3935 /* Simple connector->get_hw_state implementation for encoders that support only
3936 * one connector and no cloning and hence the encoder state determines the state
3937 * of the connector. */
3938 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
3941 struct intel_encoder
*encoder
= connector
->encoder
;
3943 return encoder
->get_hw_state(encoder
, &pipe
);
3946 static bool intel_crtc_compute_config(struct drm_crtc
*crtc
,
3947 struct intel_crtc_config
*pipe_config
)
3949 struct drm_device
*dev
= crtc
->dev
;
3950 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
3952 if (HAS_PCH_SPLIT(dev
)) {
3953 /* FDI link clock is fixed at 2.7G */
3954 if (pipe_config
->requested_mode
.clock
* 3
3955 > IRONLAKE_FDI_FREQ
* 4)
3959 /* All interlaced capable intel hw wants timings in frames. Note though
3960 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3961 * timings, so we need to be careful not to clobber these.*/
3962 if (!pipe_config
->timings_set
)
3963 drm_mode_set_crtcinfo(adjusted_mode
, 0);
3965 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3966 * with a hsync front porch of 0.
3968 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
3969 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
3972 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) && pipe_config
->pipe_bpp
> 10*3) {
3973 pipe_config
->pipe_bpp
= 10*3; /* 12bpc is gen5+ */
3974 } else if (INTEL_INFO(dev
)->gen
<= 4 && pipe_config
->pipe_bpp
> 8*3) {
3975 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
3977 pipe_config
->pipe_bpp
= 8*3;
3983 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
3985 return 400000; /* FIXME */
3988 static int i945_get_display_clock_speed(struct drm_device
*dev
)
3993 static int i915_get_display_clock_speed(struct drm_device
*dev
)
3998 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
4003 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
4007 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
4009 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
4012 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
4013 case GC_DISPLAY_CLOCK_333_MHZ
:
4016 case GC_DISPLAY_CLOCK_190_200_MHZ
:
4022 static int i865_get_display_clock_speed(struct drm_device
*dev
)
4027 static int i855_get_display_clock_speed(struct drm_device
*dev
)
4030 /* Assume that the hardware is in the high speed state. This
4031 * should be the default.
4033 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
4034 case GC_CLOCK_133_200
:
4035 case GC_CLOCK_100_200
:
4037 case GC_CLOCK_166_250
:
4039 case GC_CLOCK_100_133
:
4043 /* Shouldn't happen */
4047 static int i830_get_display_clock_speed(struct drm_device
*dev
)
4053 intel_reduce_ratio(uint32_t *num
, uint32_t *den
)
4055 while (*num
> 0xffffff || *den
> 0xffffff) {
4062 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
4063 int pixel_clock
, int link_clock
,
4064 struct intel_link_m_n
*m_n
)
4067 m_n
->gmch_m
= bits_per_pixel
* pixel_clock
;
4068 m_n
->gmch_n
= link_clock
* nlanes
* 8;
4069 intel_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
4070 m_n
->link_m
= pixel_clock
;
4071 m_n
->link_n
= link_clock
;
4072 intel_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
4075 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
4077 if (i915_panel_use_ssc
>= 0)
4078 return i915_panel_use_ssc
!= 0;
4079 return dev_priv
->lvds_use_ssc
4080 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
4083 static int vlv_get_refclk(struct drm_crtc
*crtc
)
4085 struct drm_device
*dev
= crtc
->dev
;
4086 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4087 int refclk
= 27000; /* for DP & HDMI */
4089 return 100000; /* only one validated so far */
4091 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
4093 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
4094 if (intel_panel_use_ssc(dev_priv
))
4098 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
)) {
4105 static int i9xx_get_refclk(struct drm_crtc
*crtc
, int num_connectors
)
4107 struct drm_device
*dev
= crtc
->dev
;
4108 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4111 if (IS_VALLEYVIEW(dev
)) {
4112 refclk
= vlv_get_refclk(crtc
);
4113 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4114 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
4115 refclk
= dev_priv
->lvds_ssc_freq
* 1000;
4116 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4118 } else if (!IS_GEN2(dev
)) {
4127 static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc
*crtc
)
4129 unsigned dotclock
= crtc
->config
.adjusted_mode
.clock
;
4130 struct dpll
*clock
= &crtc
->config
.dpll
;
4132 /* SDVO TV has fixed PLL values depend on its clock range,
4133 this mirrors vbios setting. */
4134 if (dotclock
>= 100000 && dotclock
< 140500) {
4140 } else if (dotclock
>= 140500 && dotclock
<= 200000) {
4148 crtc
->config
.clock_set
= true;
4151 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
4153 return (1 << dpll
->n
) << 16 | dpll
->m1
<< 8 | dpll
->m2
;
4156 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
4158 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
4161 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
4162 intel_clock_t
*reduced_clock
)
4164 struct drm_device
*dev
= crtc
->base
.dev
;
4165 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4166 int pipe
= crtc
->pipe
;
4169 if (IS_PINEVIEW(dev
)) {
4170 fp
= pnv_dpll_compute_fp(&crtc
->config
.dpll
);
4172 fp2
= pnv_dpll_compute_fp(reduced_clock
);
4174 fp
= i9xx_dpll_compute_fp(&crtc
->config
.dpll
);
4176 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
4179 I915_WRITE(FP0(pipe
), fp
);
4181 crtc
->lowfreq_avail
= false;
4182 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4183 reduced_clock
&& i915_powersave
) {
4184 I915_WRITE(FP1(pipe
), fp2
);
4185 crtc
->lowfreq_avail
= true;
4187 I915_WRITE(FP1(pipe
), fp
);
4191 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
)
4196 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4197 * and set it to a reasonable value instead.
4199 reg_val
= intel_dpio_read(dev_priv
, DPIO_IREF(1));
4200 reg_val
&= 0xffffff00;
4201 reg_val
|= 0x00000030;
4202 intel_dpio_write(dev_priv
, DPIO_IREF(1), reg_val
);
4204 reg_val
= intel_dpio_read(dev_priv
, DPIO_CALIBRATION
);
4205 reg_val
&= 0x8cffffff;
4206 reg_val
= 0x8c000000;
4207 intel_dpio_write(dev_priv
, DPIO_CALIBRATION
, reg_val
);
4209 reg_val
= intel_dpio_read(dev_priv
, DPIO_IREF(1));
4210 reg_val
&= 0xffffff00;
4211 intel_dpio_write(dev_priv
, DPIO_IREF(1), reg_val
);
4213 reg_val
= intel_dpio_read(dev_priv
, DPIO_CALIBRATION
);
4214 reg_val
&= 0x00ffffff;
4215 reg_val
|= 0xb0000000;
4216 intel_dpio_write(dev_priv
, DPIO_CALIBRATION
, reg_val
);
4219 static void intel_dp_set_m_n(struct intel_crtc
*crtc
)
4221 if (crtc
->config
.has_pch_encoder
)
4222 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
4224 intel_cpu_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
4227 static void vlv_update_pll(struct intel_crtc
*crtc
)
4229 struct drm_device
*dev
= crtc
->base
.dev
;
4230 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4231 struct drm_display_mode
*adjusted_mode
=
4232 &crtc
->config
.adjusted_mode
;
4233 struct intel_encoder
*encoder
;
4234 int pipe
= crtc
->pipe
;
4236 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
4238 u32 coreclk
, reg_val
, temp
;
4240 mutex_lock(&dev_priv
->dpio_lock
);
4242 is_hdmi
= intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
);
4244 bestn
= crtc
->config
.dpll
.n
;
4245 bestm1
= crtc
->config
.dpll
.m1
;
4246 bestm2
= crtc
->config
.dpll
.m2
;
4247 bestp1
= crtc
->config
.dpll
.p1
;
4248 bestp2
= crtc
->config
.dpll
.p2
;
4250 /* See eDP HDMI DPIO driver vbios notes doc */
4252 /* PLL B needs special handling */
4254 vlv_pllb_recal_opamp(dev_priv
);
4256 /* Set up Tx target for periodic Rcomp update */
4257 intel_dpio_write(dev_priv
, DPIO_IREF_BCAST
, 0x0100000f);
4259 /* Disable target IRef on PLL */
4260 reg_val
= intel_dpio_read(dev_priv
, DPIO_IREF_CTL(pipe
));
4261 reg_val
&= 0x00ffffff;
4262 intel_dpio_write(dev_priv
, DPIO_IREF_CTL(pipe
), reg_val
);
4264 /* Disable fast lock */
4265 intel_dpio_write(dev_priv
, DPIO_FASTCLK_DISABLE
, 0x610);
4267 /* Set idtafcrecal before PLL is enabled */
4268 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
4269 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
4270 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
4271 mdiv
|= (1 << DPIO_K_SHIFT
);
4272 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
) ||
4273 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
) ||
4274 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
))
4275 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
4276 intel_dpio_write(dev_priv
, DPIO_DIV(pipe
), mdiv
);
4278 mdiv
|= DPIO_ENABLE_CALIBRATION
;
4279 intel_dpio_write(dev_priv
, DPIO_DIV(pipe
), mdiv
);
4281 /* Set HBR and RBR LPF coefficients */
4282 if (adjusted_mode
->clock
== 162000 ||
4283 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
))
4284 intel_dpio_write(dev_priv
, DPIO_LFP_COEFF(pipe
),
4287 intel_dpio_write(dev_priv
, DPIO_LFP_COEFF(pipe
),
4290 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
) ||
4291 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
)) {
4292 /* Use SSC source */
4294 intel_dpio_write(dev_priv
, DPIO_REFSFR(pipe
),
4297 intel_dpio_write(dev_priv
, DPIO_REFSFR(pipe
),
4299 } else { /* HDMI or VGA */
4300 /* Use bend source */
4302 intel_dpio_write(dev_priv
, DPIO_REFSFR(pipe
),
4305 intel_dpio_write(dev_priv
, DPIO_REFSFR(pipe
),
4309 coreclk
= intel_dpio_read(dev_priv
, DPIO_CORE_CLK(pipe
));
4310 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
4311 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
) ||
4312 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
))
4313 coreclk
|= 0x01000000;
4314 intel_dpio_write(dev_priv
, DPIO_CORE_CLK(pipe
), coreclk
);
4316 intel_dpio_write(dev_priv
, DPIO_PLL_CML(pipe
), 0x87871000);
4318 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
4319 if (encoder
->pre_pll_enable
)
4320 encoder
->pre_pll_enable(encoder
);
4322 /* Enable DPIO clock input */
4323 dpll
= DPLL_EXT_BUFFER_ENABLE_VLV
| DPLL_REFA_CLK_ENABLE_VLV
|
4324 DPLL_VGA_MODE_DIS
| DPLL_INTEGRATED_CLOCK_VLV
;
4326 dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
4328 dpll
|= DPLL_VCO_ENABLE
;
4329 I915_WRITE(DPLL(pipe
), dpll
);
4330 POSTING_READ(DPLL(pipe
));
4333 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
4334 DRM_ERROR("DPLL %d failed to lock\n", pipe
);
4338 if (crtc
->config
.pixel_multiplier
> 1) {
4339 temp
= (crtc
->config
.pixel_multiplier
- 1)
4340 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4343 I915_WRITE(DPLL_MD(pipe
), temp
);
4344 POSTING_READ(DPLL_MD(pipe
));
4347 if (crtc
->config
.has_dp_encoder
)
4348 intel_dp_set_m_n(crtc
);
4350 mutex_unlock(&dev_priv
->dpio_lock
);
4353 static void i9xx_update_pll(struct intel_crtc
*crtc
,
4354 intel_clock_t
*reduced_clock
,
4357 struct drm_device
*dev
= crtc
->base
.dev
;
4358 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4359 struct intel_encoder
*encoder
;
4360 int pipe
= crtc
->pipe
;
4363 struct dpll
*clock
= &crtc
->config
.dpll
;
4365 i9xx_update_pll_dividers(crtc
, reduced_clock
);
4367 is_sdvo
= intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_SDVO
) ||
4368 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
);
4370 dpll
= DPLL_VGA_MODE_DIS
;
4372 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
))
4373 dpll
|= DPLLB_MODE_LVDS
;
4375 dpll
|= DPLLB_MODE_DAC_SERIAL
;
4378 if ((crtc
->config
.pixel_multiplier
> 1) &&
4379 (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))) {
4380 dpll
|= (crtc
->config
.pixel_multiplier
- 1)
4381 << SDVO_MULTIPLIER_SHIFT_HIRES
;
4383 dpll
|= DPLL_DVO_HIGH_SPEED
;
4385 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
))
4386 dpll
|= DPLL_DVO_HIGH_SPEED
;
4388 /* compute bitmask from p1 value */
4389 if (IS_PINEVIEW(dev
))
4390 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
4392 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4393 if (IS_G4X(dev
) && reduced_clock
)
4394 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
4396 switch (clock
->p2
) {
4398 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
4401 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
4404 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
4407 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
4410 if (INTEL_INFO(dev
)->gen
>= 4)
4411 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
4413 if (is_sdvo
&& intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_TVOUT
))
4414 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
4415 else if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_TVOUT
))
4416 /* XXX: just matching BIOS for now */
4417 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4419 else if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4420 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4421 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4423 dpll
|= PLL_REF_INPUT_DREFCLK
;
4425 dpll
|= DPLL_VCO_ENABLE
;
4426 I915_WRITE(DPLL(pipe
), dpll
& ~DPLL_VCO_ENABLE
);
4427 POSTING_READ(DPLL(pipe
));
4430 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
4431 if (encoder
->pre_pll_enable
)
4432 encoder
->pre_pll_enable(encoder
);
4434 if (crtc
->config
.has_dp_encoder
)
4435 intel_dp_set_m_n(crtc
);
4437 I915_WRITE(DPLL(pipe
), dpll
);
4439 /* Wait for the clocks to stabilize. */
4440 POSTING_READ(DPLL(pipe
));
4443 if (INTEL_INFO(dev
)->gen
>= 4) {
4447 if (crtc
->config
.pixel_multiplier
> 1) {
4448 temp
= (crtc
->config
.pixel_multiplier
- 1)
4449 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4452 I915_WRITE(DPLL_MD(pipe
), temp
);
4454 /* The pixel multiplier can only be updated once the
4455 * DPLL is enabled and the clocks are stable.
4457 * So write it again.
4459 I915_WRITE(DPLL(pipe
), dpll
);
4463 static void i8xx_update_pll(struct intel_crtc
*crtc
,
4464 struct drm_display_mode
*adjusted_mode
,
4465 intel_clock_t
*reduced_clock
,
4468 struct drm_device
*dev
= crtc
->base
.dev
;
4469 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4470 struct intel_encoder
*encoder
;
4471 int pipe
= crtc
->pipe
;
4473 struct dpll
*clock
= &crtc
->config
.dpll
;
4475 i9xx_update_pll_dividers(crtc
, reduced_clock
);
4477 dpll
= DPLL_VGA_MODE_DIS
;
4479 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
)) {
4480 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4483 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
4485 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4487 dpll
|= PLL_P2_DIVIDE_BY_4
;
4490 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4491 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4492 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4494 dpll
|= PLL_REF_INPUT_DREFCLK
;
4496 dpll
|= DPLL_VCO_ENABLE
;
4497 I915_WRITE(DPLL(pipe
), dpll
& ~DPLL_VCO_ENABLE
);
4498 POSTING_READ(DPLL(pipe
));
4501 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
4502 if (encoder
->pre_pll_enable
)
4503 encoder
->pre_pll_enable(encoder
);
4505 I915_WRITE(DPLL(pipe
), dpll
);
4507 /* Wait for the clocks to stabilize. */
4508 POSTING_READ(DPLL(pipe
));
4511 /* The pixel multiplier can only be updated once the
4512 * DPLL is enabled and the clocks are stable.
4514 * So write it again.
4516 I915_WRITE(DPLL(pipe
), dpll
);
4519 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
,
4520 struct drm_display_mode
*mode
,
4521 struct drm_display_mode
*adjusted_mode
)
4523 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4524 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4525 enum pipe pipe
= intel_crtc
->pipe
;
4526 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
4527 uint32_t vsyncshift
;
4529 if (!IS_GEN2(dev
) && adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
4530 /* the chip adds 2 halflines automatically */
4531 adjusted_mode
->crtc_vtotal
-= 1;
4532 adjusted_mode
->crtc_vblank_end
-= 1;
4533 vsyncshift
= adjusted_mode
->crtc_hsync_start
4534 - adjusted_mode
->crtc_htotal
/ 2;
4539 if (INTEL_INFO(dev
)->gen
> 3)
4540 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
4542 I915_WRITE(HTOTAL(cpu_transcoder
),
4543 (adjusted_mode
->crtc_hdisplay
- 1) |
4544 ((adjusted_mode
->crtc_htotal
- 1) << 16));
4545 I915_WRITE(HBLANK(cpu_transcoder
),
4546 (adjusted_mode
->crtc_hblank_start
- 1) |
4547 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
4548 I915_WRITE(HSYNC(cpu_transcoder
),
4549 (adjusted_mode
->crtc_hsync_start
- 1) |
4550 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
4552 I915_WRITE(VTOTAL(cpu_transcoder
),
4553 (adjusted_mode
->crtc_vdisplay
- 1) |
4554 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
4555 I915_WRITE(VBLANK(cpu_transcoder
),
4556 (adjusted_mode
->crtc_vblank_start
- 1) |
4557 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
4558 I915_WRITE(VSYNC(cpu_transcoder
),
4559 (adjusted_mode
->crtc_vsync_start
- 1) |
4560 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
4562 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4563 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4564 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4566 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
4567 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
4568 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
4570 /* pipesrc controls the size that is scaled from, which should
4571 * always be the user's requested size.
4573 I915_WRITE(PIPESRC(pipe
),
4574 ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
4577 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
4579 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4580 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4583 pipeconf
= I915_READ(PIPECONF(intel_crtc
->pipe
));
4585 if (intel_crtc
->pipe
== 0 && INTEL_INFO(dev
)->gen
< 4) {
4586 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4589 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4592 if (intel_crtc
->config
.requested_mode
.clock
>
4593 dev_priv
->display
.get_display_clock_speed(dev
) * 9 / 10)
4594 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
4596 pipeconf
&= ~PIPECONF_DOUBLE_WIDE
;
4599 /* default to 8bpc */
4600 pipeconf
&= ~(PIPECONF_BPC_MASK
| PIPECONF_DITHER_EN
);
4601 if (intel_crtc
->config
.has_dp_encoder
) {
4602 if (intel_crtc
->config
.dither
) {
4603 pipeconf
|= PIPECONF_6BPC
|
4604 PIPECONF_DITHER_EN
|
4605 PIPECONF_DITHER_TYPE_SP
;
4609 if (IS_VALLEYVIEW(dev
) && intel_pipe_has_type(&intel_crtc
->base
,
4610 INTEL_OUTPUT_EDP
)) {
4611 if (intel_crtc
->config
.dither
) {
4612 pipeconf
|= PIPECONF_6BPC
|
4614 I965_PIPECONF_ACTIVE
;
4618 if (HAS_PIPE_CXSR(dev
)) {
4619 if (intel_crtc
->lowfreq_avail
) {
4620 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4621 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
4623 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4624 pipeconf
&= ~PIPECONF_CXSR_DOWNCLOCK
;
4628 pipeconf
&= ~PIPECONF_INTERLACE_MASK
;
4629 if (!IS_GEN2(dev
) &&
4630 intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
4631 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
4633 pipeconf
|= PIPECONF_PROGRESSIVE
;
4635 if (IS_VALLEYVIEW(dev
)) {
4636 if (intel_crtc
->config
.limited_color_range
)
4637 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
4639 pipeconf
&= ~PIPECONF_COLOR_RANGE_SELECT
;
4642 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
4643 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
4646 static int i9xx_crtc_mode_set(struct drm_crtc
*crtc
,
4648 struct drm_framebuffer
*fb
)
4650 struct drm_device
*dev
= crtc
->dev
;
4651 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4652 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4653 struct drm_display_mode
*adjusted_mode
=
4654 &intel_crtc
->config
.adjusted_mode
;
4655 struct drm_display_mode
*mode
= &intel_crtc
->config
.requested_mode
;
4656 int pipe
= intel_crtc
->pipe
;
4657 int plane
= intel_crtc
->plane
;
4658 int refclk
, num_connectors
= 0;
4659 intel_clock_t clock
, reduced_clock
;
4661 bool ok
, has_reduced_clock
= false, is_sdvo
= false;
4662 bool is_lvds
= false, is_tv
= false;
4663 struct intel_encoder
*encoder
;
4664 const intel_limit_t
*limit
;
4667 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4668 switch (encoder
->type
) {
4669 case INTEL_OUTPUT_LVDS
:
4672 case INTEL_OUTPUT_SDVO
:
4673 case INTEL_OUTPUT_HDMI
:
4675 if (encoder
->needs_tv_clock
)
4678 case INTEL_OUTPUT_TVOUT
:
4686 refclk
= i9xx_get_refclk(crtc
, num_connectors
);
4689 * Returns a set of divisors for the desired target clock with the given
4690 * refclk, or FALSE. The returned values represent the clock equation:
4691 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4693 limit
= intel_limit(crtc
, refclk
);
4694 ok
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, NULL
,
4697 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4701 /* Ensure that the cursor is valid for the new mode before changing... */
4702 intel_crtc_update_cursor(crtc
, true);
4704 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
4706 * Ensure we match the reduced clock's P to the target clock.
4707 * If the clocks don't match, we can't switch the display clock
4708 * by using the FP0/FP1. In such case we will disable the LVDS
4709 * downclock feature.
4711 has_reduced_clock
= limit
->find_pll(limit
, crtc
,
4712 dev_priv
->lvds_downclock
,
4717 /* Compat-code for transition, will disappear. */
4718 if (!intel_crtc
->config
.clock_set
) {
4719 intel_crtc
->config
.dpll
.n
= clock
.n
;
4720 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
4721 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
4722 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
4723 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
4726 if (is_sdvo
&& is_tv
)
4727 i9xx_adjust_sdvo_tv_clock(intel_crtc
);
4730 i8xx_update_pll(intel_crtc
, adjusted_mode
,
4731 has_reduced_clock
? &reduced_clock
: NULL
,
4733 else if (IS_VALLEYVIEW(dev
))
4734 vlv_update_pll(intel_crtc
);
4736 i9xx_update_pll(intel_crtc
,
4737 has_reduced_clock
? &reduced_clock
: NULL
,
4740 /* Set up the display plane register */
4741 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
4743 if (!IS_VALLEYVIEW(dev
)) {
4745 dspcntr
&= ~DISPPLANE_SEL_PIPE_MASK
;
4747 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
4750 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe
));
4751 drm_mode_debug_printmodeline(mode
);
4753 intel_set_pipe_timings(intel_crtc
, mode
, adjusted_mode
);
4755 /* pipesrc and dspsize control the size that is scaled from,
4756 * which should always be the user's requested size.
4758 I915_WRITE(DSPSIZE(plane
),
4759 ((mode
->vdisplay
- 1) << 16) |
4760 (mode
->hdisplay
- 1));
4761 I915_WRITE(DSPPOS(plane
), 0);
4763 i9xx_set_pipeconf(intel_crtc
);
4765 I915_WRITE(DSPCNTR(plane
), dspcntr
);
4766 POSTING_READ(DSPCNTR(plane
));
4768 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
4770 intel_update_watermarks(dev
);
4775 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
4776 struct intel_crtc_config
*pipe_config
)
4778 struct drm_device
*dev
= crtc
->base
.dev
;
4779 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4782 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
4783 if (!(tmp
& PIPECONF_ENABLE
))
4789 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
4791 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4792 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
4793 struct intel_encoder
*encoder
;
4795 bool has_lvds
= false;
4796 bool has_cpu_edp
= false;
4797 bool has_pch_edp
= false;
4798 bool has_panel
= false;
4799 bool has_ck505
= false;
4800 bool can_ssc
= false;
4802 /* We need to take the global config into account */
4803 list_for_each_entry(encoder
, &mode_config
->encoder_list
,
4805 switch (encoder
->type
) {
4806 case INTEL_OUTPUT_LVDS
:
4810 case INTEL_OUTPUT_EDP
:
4812 if (intel_encoder_is_pch_edp(&encoder
->base
))
4820 if (HAS_PCH_IBX(dev
)) {
4821 has_ck505
= dev_priv
->display_clock_mode
;
4822 can_ssc
= has_ck505
;
4828 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4829 has_panel
, has_lvds
, has_pch_edp
, has_cpu_edp
,
4832 /* Ironlake: try to setup display ref clock before DPLL
4833 * enabling. This is only under driver's control after
4834 * PCH B stepping, previous chipset stepping should be
4835 * ignoring this setting.
4837 val
= I915_READ(PCH_DREF_CONTROL
);
4839 /* As we must carefully and slowly disable/enable each source in turn,
4840 * compute the final state we want first and check if we need to
4841 * make any changes at all.
4844 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
4846 final
|= DREF_NONSPREAD_CK505_ENABLE
;
4848 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
4850 final
&= ~DREF_SSC_SOURCE_MASK
;
4851 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
4852 final
&= ~DREF_SSC1_ENABLE
;
4855 final
|= DREF_SSC_SOURCE_ENABLE
;
4857 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
4858 final
|= DREF_SSC1_ENABLE
;
4861 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
4862 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
4864 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
4866 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
4868 final
|= DREF_SSC_SOURCE_DISABLE
;
4869 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
4875 /* Always enable nonspread source */
4876 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
4879 val
|= DREF_NONSPREAD_CK505_ENABLE
;
4881 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
4884 val
&= ~DREF_SSC_SOURCE_MASK
;
4885 val
|= DREF_SSC_SOURCE_ENABLE
;
4887 /* SSC must be turned on before enabling the CPU output */
4888 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
4889 DRM_DEBUG_KMS("Using SSC on panel\n");
4890 val
|= DREF_SSC1_ENABLE
;
4892 val
&= ~DREF_SSC1_ENABLE
;
4894 /* Get SSC going before enabling the outputs */
4895 I915_WRITE(PCH_DREF_CONTROL
, val
);
4896 POSTING_READ(PCH_DREF_CONTROL
);
4899 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
4901 /* Enable CPU source on CPU attached eDP */
4903 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
4904 DRM_DEBUG_KMS("Using SSC on eDP\n");
4905 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
4908 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
4910 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
4912 I915_WRITE(PCH_DREF_CONTROL
, val
);
4913 POSTING_READ(PCH_DREF_CONTROL
);
4916 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4918 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
4920 /* Turn off CPU output */
4921 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
4923 I915_WRITE(PCH_DREF_CONTROL
, val
);
4924 POSTING_READ(PCH_DREF_CONTROL
);
4927 /* Turn off the SSC source */
4928 val
&= ~DREF_SSC_SOURCE_MASK
;
4929 val
|= DREF_SSC_SOURCE_DISABLE
;
4932 val
&= ~DREF_SSC1_ENABLE
;
4934 I915_WRITE(PCH_DREF_CONTROL
, val
);
4935 POSTING_READ(PCH_DREF_CONTROL
);
4939 BUG_ON(val
!= final
);
4942 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4943 static void lpt_init_pch_refclk(struct drm_device
*dev
)
4945 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4946 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
4947 struct intel_encoder
*encoder
;
4948 bool has_vga
= false;
4949 bool is_sdv
= false;
4952 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
) {
4953 switch (encoder
->type
) {
4954 case INTEL_OUTPUT_ANALOG
:
4963 mutex_lock(&dev_priv
->dpio_lock
);
4965 /* XXX: Rip out SDV support once Haswell ships for real. */
4966 if (IS_HASWELL(dev
) && (dev
->pci_device
& 0xFF00) == 0x0C00)
4969 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
4970 tmp
&= ~SBI_SSCCTL_DISABLE
;
4971 tmp
|= SBI_SSCCTL_PATHALT
;
4972 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
4976 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
4977 tmp
&= ~SBI_SSCCTL_PATHALT
;
4978 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
4981 tmp
= I915_READ(SOUTH_CHICKEN2
);
4982 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
4983 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
4985 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
4986 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
4987 DRM_ERROR("FDI mPHY reset assert timeout\n");
4989 tmp
= I915_READ(SOUTH_CHICKEN2
);
4990 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
4991 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
4993 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
4994 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0,
4996 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
4999 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
5000 tmp
&= ~(0xFF << 24);
5001 tmp
|= (0x12 << 24);
5002 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
5005 tmp
= intel_sbi_read(dev_priv
, 0x800C, SBI_MPHY
);
5007 intel_sbi_write(dev_priv
, 0x800C, tmp
, SBI_MPHY
);
5010 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
5012 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
5014 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
5016 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
5019 tmp
= intel_sbi_read(dev_priv
, 0x2038, SBI_MPHY
);
5020 tmp
|= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5021 intel_sbi_write(dev_priv
, 0x2038, tmp
, SBI_MPHY
);
5023 tmp
= intel_sbi_read(dev_priv
, 0x2138, SBI_MPHY
);
5024 tmp
|= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5025 intel_sbi_write(dev_priv
, 0x2138, tmp
, SBI_MPHY
);
5027 tmp
= intel_sbi_read(dev_priv
, 0x203C, SBI_MPHY
);
5029 intel_sbi_write(dev_priv
, 0x203C, tmp
, SBI_MPHY
);
5031 tmp
= intel_sbi_read(dev_priv
, 0x213C, SBI_MPHY
);
5033 intel_sbi_write(dev_priv
, 0x213C, tmp
, SBI_MPHY
);
5036 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
5037 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
5038 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
5040 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
5041 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
5042 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
5045 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
5048 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
5050 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
5053 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
5056 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
5059 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
5061 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
5064 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
5066 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
5067 tmp
&= ~(0xFF << 16);
5068 tmp
|= (0x1C << 16);
5069 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
5071 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
5072 tmp
&= ~(0xFF << 16);
5073 tmp
|= (0x1C << 16);
5074 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
5077 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
5079 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
5081 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
5083 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
5085 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
5086 tmp
&= ~(0xF << 28);
5088 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
5090 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
5091 tmp
&= ~(0xF << 28);
5093 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
5096 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5097 tmp
= intel_sbi_read(dev_priv
, SBI_DBUFF0
, SBI_ICLK
);
5098 tmp
|= SBI_DBUFF0_ENABLE
;
5099 intel_sbi_write(dev_priv
, SBI_DBUFF0
, tmp
, SBI_ICLK
);
5101 mutex_unlock(&dev_priv
->dpio_lock
);
5105 * Initialize reference clocks when the driver loads
5107 void intel_init_pch_refclk(struct drm_device
*dev
)
5109 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
5110 ironlake_init_pch_refclk(dev
);
5111 else if (HAS_PCH_LPT(dev
))
5112 lpt_init_pch_refclk(dev
);
5115 static int ironlake_get_refclk(struct drm_crtc
*crtc
)
5117 struct drm_device
*dev
= crtc
->dev
;
5118 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5119 struct intel_encoder
*encoder
;
5120 struct intel_encoder
*edp_encoder
= NULL
;
5121 int num_connectors
= 0;
5122 bool is_lvds
= false;
5124 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5125 switch (encoder
->type
) {
5126 case INTEL_OUTPUT_LVDS
:
5129 case INTEL_OUTPUT_EDP
:
5130 edp_encoder
= encoder
;
5136 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
5137 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5138 dev_priv
->lvds_ssc_freq
);
5139 return dev_priv
->lvds_ssc_freq
* 1000;
5145 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
,
5146 struct drm_display_mode
*adjusted_mode
)
5148 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
5149 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5150 int pipe
= intel_crtc
->pipe
;
5153 val
= I915_READ(PIPECONF(pipe
));
5155 val
&= ~PIPECONF_BPC_MASK
;
5156 switch (intel_crtc
->config
.pipe_bpp
) {
5158 val
|= PIPECONF_6BPC
;
5161 val
|= PIPECONF_8BPC
;
5164 val
|= PIPECONF_10BPC
;
5167 val
|= PIPECONF_12BPC
;
5170 /* Case prevented by intel_choose_pipe_bpp_dither. */
5174 val
&= ~(PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_MASK
);
5175 if (intel_crtc
->config
.dither
)
5176 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
5178 val
&= ~PIPECONF_INTERLACE_MASK
;
5179 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
5180 val
|= PIPECONF_INTERLACED_ILK
;
5182 val
|= PIPECONF_PROGRESSIVE
;
5184 if (intel_crtc
->config
.limited_color_range
)
5185 val
|= PIPECONF_COLOR_RANGE_SELECT
;
5187 val
&= ~PIPECONF_COLOR_RANGE_SELECT
;
5189 I915_WRITE(PIPECONF(pipe
), val
);
5190 POSTING_READ(PIPECONF(pipe
));
5194 * Set up the pipe CSC unit.
5196 * Currently only full range RGB to limited range RGB conversion
5197 * is supported, but eventually this should handle various
5198 * RGB<->YCbCr scenarios as well.
5200 static void intel_set_pipe_csc(struct drm_crtc
*crtc
)
5202 struct drm_device
*dev
= crtc
->dev
;
5203 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5204 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5205 int pipe
= intel_crtc
->pipe
;
5206 uint16_t coeff
= 0x7800; /* 1.0 */
5209 * TODO: Check what kind of values actually come out of the pipe
5210 * with these coeff/postoff values and adjust to get the best
5211 * accuracy. Perhaps we even need to take the bpc value into
5215 if (intel_crtc
->config
.limited_color_range
)
5216 coeff
= ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5219 * GY/GU and RY/RU should be the other way around according
5220 * to BSpec, but reality doesn't agree. Just set them up in
5221 * a way that results in the correct picture.
5223 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeff
<< 16);
5224 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), 0);
5226 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeff
);
5227 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), 0);
5229 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), 0);
5230 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeff
<< 16);
5232 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
5233 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
5234 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
5236 if (INTEL_INFO(dev
)->gen
> 6) {
5237 uint16_t postoff
= 0;
5239 if (intel_crtc
->config
.limited_color_range
)
5240 postoff
= (16 * (1 << 13) / 255) & 0x1fff;
5242 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
5243 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
5244 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
5246 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
5248 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
5250 if (intel_crtc
->config
.limited_color_range
)
5251 mode
|= CSC_BLACK_SCREEN_OFFSET
;
5253 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
5257 static void haswell_set_pipeconf(struct drm_crtc
*crtc
,
5258 struct drm_display_mode
*adjusted_mode
)
5260 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
5261 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5262 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
5265 val
= I915_READ(PIPECONF(cpu_transcoder
));
5267 val
&= ~(PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_MASK
);
5268 if (intel_crtc
->config
.dither
)
5269 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
5271 val
&= ~PIPECONF_INTERLACE_MASK_HSW
;
5272 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
5273 val
|= PIPECONF_INTERLACED_ILK
;
5275 val
|= PIPECONF_PROGRESSIVE
;
5277 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
5278 POSTING_READ(PIPECONF(cpu_transcoder
));
5281 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
5282 struct drm_display_mode
*adjusted_mode
,
5283 intel_clock_t
*clock
,
5284 bool *has_reduced_clock
,
5285 intel_clock_t
*reduced_clock
)
5287 struct drm_device
*dev
= crtc
->dev
;
5288 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5289 struct intel_encoder
*intel_encoder
;
5291 const intel_limit_t
*limit
;
5292 bool ret
, is_sdvo
= false, is_tv
= false, is_lvds
= false;
5294 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5295 switch (intel_encoder
->type
) {
5296 case INTEL_OUTPUT_LVDS
:
5299 case INTEL_OUTPUT_SDVO
:
5300 case INTEL_OUTPUT_HDMI
:
5302 if (intel_encoder
->needs_tv_clock
)
5305 case INTEL_OUTPUT_TVOUT
:
5311 refclk
= ironlake_get_refclk(crtc
);
5314 * Returns a set of divisors for the desired target clock with the given
5315 * refclk, or FALSE. The returned values represent the clock equation:
5316 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5318 limit
= intel_limit(crtc
, refclk
);
5319 ret
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, NULL
,
5324 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
5326 * Ensure we match the reduced clock's P to the target clock.
5327 * If the clocks don't match, we can't switch the display clock
5328 * by using the FP0/FP1. In such case we will disable the LVDS
5329 * downclock feature.
5331 *has_reduced_clock
= limit
->find_pll(limit
, crtc
,
5332 dev_priv
->lvds_downclock
,
5338 if (is_sdvo
&& is_tv
)
5339 i9xx_adjust_sdvo_tv_clock(to_intel_crtc(crtc
));
5344 static void cpt_enable_fdi_bc_bifurcation(struct drm_device
*dev
)
5346 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5349 temp
= I915_READ(SOUTH_CHICKEN1
);
5350 if (temp
& FDI_BC_BIFURCATION_SELECT
)
5353 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
5354 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
5356 temp
|= FDI_BC_BIFURCATION_SELECT
;
5357 DRM_DEBUG_KMS("enabling fdi C rx\n");
5358 I915_WRITE(SOUTH_CHICKEN1
, temp
);
5359 POSTING_READ(SOUTH_CHICKEN1
);
5362 static bool ironlake_check_fdi_lanes(struct intel_crtc
*intel_crtc
)
5364 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5365 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5366 struct intel_crtc
*pipe_B_crtc
=
5367 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
5369 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5370 pipe_name(intel_crtc
->pipe
), intel_crtc
->fdi_lanes
);
5371 if (intel_crtc
->fdi_lanes
> 4) {
5372 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5373 pipe_name(intel_crtc
->pipe
), intel_crtc
->fdi_lanes
);
5374 /* Clamp lanes to avoid programming the hw with bogus values. */
5375 intel_crtc
->fdi_lanes
= 4;
5380 if (INTEL_INFO(dev
)->num_pipes
== 2)
5383 switch (intel_crtc
->pipe
) {
5387 if (dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]->enabled
&&
5388 intel_crtc
->fdi_lanes
> 2) {
5389 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5390 pipe_name(intel_crtc
->pipe
), intel_crtc
->fdi_lanes
);
5391 /* Clamp lanes to avoid programming the hw with bogus values. */
5392 intel_crtc
->fdi_lanes
= 2;
5397 if (intel_crtc
->fdi_lanes
> 2)
5398 WARN_ON(I915_READ(SOUTH_CHICKEN1
) & FDI_BC_BIFURCATION_SELECT
);
5400 cpt_enable_fdi_bc_bifurcation(dev
);
5404 if (!pipe_B_crtc
->base
.enabled
|| pipe_B_crtc
->fdi_lanes
<= 2) {
5405 if (intel_crtc
->fdi_lanes
> 2) {
5406 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5407 pipe_name(intel_crtc
->pipe
), intel_crtc
->fdi_lanes
);
5408 /* Clamp lanes to avoid programming the hw with bogus values. */
5409 intel_crtc
->fdi_lanes
= 2;
5414 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5418 cpt_enable_fdi_bc_bifurcation(dev
);
5426 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
5429 * Account for spread spectrum to avoid
5430 * oversubscribing the link. Max center spread
5431 * is 2.5%; use 5% for safety's sake.
5433 u32 bps
= target_clock
* bpp
* 21 / 20;
5434 return bps
/ (link_bw
* 8) + 1;
5437 void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
5438 struct intel_link_m_n
*m_n
)
5440 struct drm_device
*dev
= crtc
->base
.dev
;
5441 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5442 int pipe
= crtc
->pipe
;
5444 I915_WRITE(TRANSDATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5445 I915_WRITE(TRANSDATA_N1(pipe
), m_n
->gmch_n
);
5446 I915_WRITE(TRANSDPLINK_M1(pipe
), m_n
->link_m
);
5447 I915_WRITE(TRANSDPLINK_N1(pipe
), m_n
->link_n
);
5450 void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
5451 struct intel_link_m_n
*m_n
)
5453 struct drm_device
*dev
= crtc
->base
.dev
;
5454 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5455 int pipe
= crtc
->pipe
;
5456 enum transcoder transcoder
= crtc
->config
.cpu_transcoder
;
5458 if (INTEL_INFO(dev
)->gen
>= 5) {
5459 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5460 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
5461 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
5462 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
5464 I915_WRITE(PIPE_GMCH_DATA_M(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5465 I915_WRITE(PIPE_GMCH_DATA_N(pipe
), m_n
->gmch_n
);
5466 I915_WRITE(PIPE_DP_LINK_M(pipe
), m_n
->link_m
);
5467 I915_WRITE(PIPE_DP_LINK_N(pipe
), m_n
->link_n
);
5471 static void ironlake_fdi_set_m_n(struct drm_crtc
*crtc
)
5473 struct drm_device
*dev
= crtc
->dev
;
5474 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5475 struct drm_display_mode
*adjusted_mode
=
5476 &intel_crtc
->config
.adjusted_mode
;
5477 struct intel_link_m_n m_n
= {0};
5478 int target_clock
, lane
, link_bw
;
5480 /* FDI is a binary signal running at ~2.7GHz, encoding
5481 * each output octet as 10 bits. The actual frequency
5482 * is stored as a divider into a 100MHz clock, and the
5483 * mode pixel clock is stored in units of 1KHz.
5484 * Hence the bw of each lane in terms of the mode signal
5487 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
5489 if (intel_crtc
->config
.pixel_target_clock
)
5490 target_clock
= intel_crtc
->config
.pixel_target_clock
;
5492 target_clock
= adjusted_mode
->clock
;
5494 lane
= ironlake_get_lanes_required(target_clock
, link_bw
,
5495 intel_crtc
->config
.pipe_bpp
);
5497 intel_crtc
->fdi_lanes
= lane
;
5499 if (intel_crtc
->config
.pixel_multiplier
> 1)
5500 link_bw
*= intel_crtc
->config
.pixel_multiplier
;
5501 intel_link_compute_m_n(intel_crtc
->config
.pipe_bpp
, lane
, target_clock
,
5504 intel_cpu_transcoder_set_m_n(intel_crtc
, &m_n
);
5507 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
5509 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
5512 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
5514 intel_clock_t
*reduced_clock
, u32
*fp2
)
5516 struct drm_crtc
*crtc
= &intel_crtc
->base
;
5517 struct drm_device
*dev
= crtc
->dev
;
5518 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5519 struct intel_encoder
*intel_encoder
;
5521 int factor
, num_connectors
= 0;
5522 bool is_lvds
= false, is_sdvo
= false, is_tv
= false;
5524 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5525 switch (intel_encoder
->type
) {
5526 case INTEL_OUTPUT_LVDS
:
5529 case INTEL_OUTPUT_SDVO
:
5530 case INTEL_OUTPUT_HDMI
:
5532 if (intel_encoder
->needs_tv_clock
)
5535 case INTEL_OUTPUT_TVOUT
:
5543 /* Enable autotuning of the PLL clock (if permissible) */
5546 if ((intel_panel_use_ssc(dev_priv
) &&
5547 dev_priv
->lvds_ssc_freq
== 100) ||
5548 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
5550 } else if (is_sdvo
&& is_tv
)
5553 if (ironlake_needs_fb_cb_tune(&intel_crtc
->config
.dpll
, factor
))
5556 if (fp2
&& (reduced_clock
->m
< factor
* reduced_clock
->n
))
5562 dpll
|= DPLLB_MODE_LVDS
;
5564 dpll
|= DPLLB_MODE_DAC_SERIAL
;
5566 if (intel_crtc
->config
.pixel_multiplier
> 1) {
5567 dpll
|= (intel_crtc
->config
.pixel_multiplier
- 1)
5568 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
5570 dpll
|= DPLL_DVO_HIGH_SPEED
;
5572 if (intel_crtc
->config
.has_dp_encoder
)
5573 dpll
|= DPLL_DVO_HIGH_SPEED
;
5575 /* compute bitmask from p1 value */
5576 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5578 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
5580 switch (intel_crtc
->config
.dpll
.p2
) {
5582 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
5585 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
5588 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
5591 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
5595 if (is_sdvo
&& is_tv
)
5596 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
5598 /* XXX: just matching BIOS for now */
5599 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5601 else if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
5602 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
5604 dpll
|= PLL_REF_INPUT_DREFCLK
;
5609 static int ironlake_crtc_mode_set(struct drm_crtc
*crtc
,
5611 struct drm_framebuffer
*fb
)
5613 struct drm_device
*dev
= crtc
->dev
;
5614 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5615 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5616 struct drm_display_mode
*adjusted_mode
=
5617 &intel_crtc
->config
.adjusted_mode
;
5618 struct drm_display_mode
*mode
= &intel_crtc
->config
.requested_mode
;
5619 int pipe
= intel_crtc
->pipe
;
5620 int plane
= intel_crtc
->plane
;
5621 int num_connectors
= 0;
5622 intel_clock_t clock
, reduced_clock
;
5623 u32 dpll
= 0, fp
= 0, fp2
= 0;
5624 bool ok
, has_reduced_clock
= false;
5625 bool is_lvds
= false;
5626 struct intel_encoder
*encoder
;
5630 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5631 switch (encoder
->type
) {
5632 case INTEL_OUTPUT_LVDS
:
5640 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
5641 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
5643 intel_crtc
->config
.cpu_transcoder
= pipe
;
5645 ok
= ironlake_compute_clocks(crtc
, adjusted_mode
, &clock
,
5646 &has_reduced_clock
, &reduced_clock
);
5648 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5651 /* Compat-code for transition, will disappear. */
5652 if (!intel_crtc
->config
.clock_set
) {
5653 intel_crtc
->config
.dpll
.n
= clock
.n
;
5654 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
5655 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
5656 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
5657 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
5660 /* Ensure that the cursor is valid for the new mode before changing... */
5661 intel_crtc_update_cursor(crtc
, true);
5663 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe
));
5664 drm_mode_debug_printmodeline(mode
);
5666 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5667 if (intel_crtc
->config
.has_pch_encoder
) {
5668 struct intel_pch_pll
*pll
;
5670 fp
= i9xx_dpll_compute_fp(&intel_crtc
->config
.dpll
);
5671 if (has_reduced_clock
)
5672 fp2
= i9xx_dpll_compute_fp(&reduced_clock
);
5674 dpll
= ironlake_compute_dpll(intel_crtc
,
5675 &fp
, &reduced_clock
,
5676 has_reduced_clock
? &fp2
: NULL
);
5678 pll
= intel_get_pch_pll(intel_crtc
, dpll
, fp
);
5680 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5685 intel_put_pch_pll(intel_crtc
);
5687 if (intel_crtc
->config
.has_dp_encoder
)
5688 intel_dp_set_m_n(intel_crtc
);
5690 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5691 if (encoder
->pre_pll_enable
)
5692 encoder
->pre_pll_enable(encoder
);
5694 if (intel_crtc
->pch_pll
) {
5695 I915_WRITE(intel_crtc
->pch_pll
->pll_reg
, dpll
);
5697 /* Wait for the clocks to stabilize. */
5698 POSTING_READ(intel_crtc
->pch_pll
->pll_reg
);
5701 /* The pixel multiplier can only be updated once the
5702 * DPLL is enabled and the clocks are stable.
5704 * So write it again.
5706 I915_WRITE(intel_crtc
->pch_pll
->pll_reg
, dpll
);
5709 intel_crtc
->lowfreq_avail
= false;
5710 if (intel_crtc
->pch_pll
) {
5711 if (is_lvds
&& has_reduced_clock
&& i915_powersave
) {
5712 I915_WRITE(intel_crtc
->pch_pll
->fp1_reg
, fp2
);
5713 intel_crtc
->lowfreq_avail
= true;
5715 I915_WRITE(intel_crtc
->pch_pll
->fp1_reg
, fp
);
5719 intel_set_pipe_timings(intel_crtc
, mode
, adjusted_mode
);
5721 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5722 * ironlake_check_fdi_lanes. */
5723 intel_crtc
->fdi_lanes
= 0;
5724 if (intel_crtc
->config
.has_pch_encoder
)
5725 ironlake_fdi_set_m_n(crtc
);
5727 fdi_config_ok
= ironlake_check_fdi_lanes(intel_crtc
);
5729 ironlake_set_pipeconf(crtc
, adjusted_mode
);
5731 /* Set up the display plane register */
5732 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
);
5733 POSTING_READ(DSPCNTR(plane
));
5735 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
5737 intel_update_watermarks(dev
);
5739 intel_update_linetime_watermarks(dev
, pipe
, adjusted_mode
);
5741 return fdi_config_ok
? ret
: -EINVAL
;
5744 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
5745 struct intel_crtc_config
*pipe_config
)
5747 struct drm_device
*dev
= crtc
->base
.dev
;
5748 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5751 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
5752 if (!(tmp
& PIPECONF_ENABLE
))
5755 if (I915_READ(TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
)
5756 pipe_config
->has_pch_encoder
= true;
5761 static void haswell_modeset_global_resources(struct drm_device
*dev
)
5763 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5764 bool enable
= false;
5765 struct intel_crtc
*crtc
;
5766 struct intel_encoder
*encoder
;
5768 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
5769 if (crtc
->pipe
!= PIPE_A
&& crtc
->base
.enabled
)
5771 /* XXX: Should check for edp transcoder here, but thanks to init
5772 * sequence that's not yet available. Just in case desktop eDP
5773 * on PORT D is possible on haswell, too. */
5776 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
5778 if (encoder
->type
!= INTEL_OUTPUT_EDP
&&
5779 encoder
->connectors_active
)
5783 /* Even the eDP panel fitter is outside the always-on well. */
5784 if (dev_priv
->pch_pf_size
)
5787 intel_set_power_well(dev
, enable
);
5790 static int haswell_crtc_mode_set(struct drm_crtc
*crtc
,
5792 struct drm_framebuffer
*fb
)
5794 struct drm_device
*dev
= crtc
->dev
;
5795 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5796 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5797 struct drm_display_mode
*adjusted_mode
=
5798 &intel_crtc
->config
.adjusted_mode
;
5799 struct drm_display_mode
*mode
= &intel_crtc
->config
.requested_mode
;
5800 int pipe
= intel_crtc
->pipe
;
5801 int plane
= intel_crtc
->plane
;
5802 int num_connectors
= 0;
5803 bool is_cpu_edp
= false;
5804 struct intel_encoder
*encoder
;
5807 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5808 switch (encoder
->type
) {
5809 case INTEL_OUTPUT_EDP
:
5810 if (!intel_encoder_is_pch_edp(&encoder
->base
))
5819 intel_crtc
->config
.cpu_transcoder
= TRANSCODER_EDP
;
5821 intel_crtc
->config
.cpu_transcoder
= pipe
;
5823 /* We are not sure yet this won't happen. */
5824 WARN(!HAS_PCH_LPT(dev
), "Unexpected PCH type %d\n",
5825 INTEL_PCH_TYPE(dev
));
5827 WARN(num_connectors
!= 1, "%d connectors attached to pipe %c\n",
5828 num_connectors
, pipe_name(pipe
));
5830 WARN_ON(I915_READ(PIPECONF(intel_crtc
->config
.cpu_transcoder
)) &
5831 (PIPECONF_ENABLE
| I965_PIPECONF_ACTIVE
));
5833 WARN_ON(I915_READ(DSPCNTR(plane
)) & DISPLAY_PLANE_ENABLE
);
5835 if (!intel_ddi_pll_mode_set(crtc
, adjusted_mode
->clock
))
5838 /* Ensure that the cursor is valid for the new mode before changing... */
5839 intel_crtc_update_cursor(crtc
, true);
5841 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe
));
5842 drm_mode_debug_printmodeline(mode
);
5844 if (intel_crtc
->config
.has_dp_encoder
)
5845 intel_dp_set_m_n(intel_crtc
);
5847 intel_crtc
->lowfreq_avail
= false;
5849 intel_set_pipe_timings(intel_crtc
, mode
, adjusted_mode
);
5851 if (intel_crtc
->config
.has_pch_encoder
)
5852 ironlake_fdi_set_m_n(crtc
);
5854 haswell_set_pipeconf(crtc
, adjusted_mode
);
5856 intel_set_pipe_csc(crtc
);
5858 /* Set up the display plane register */
5859 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
| DISPPLANE_PIPE_CSC_ENABLE
);
5860 POSTING_READ(DSPCNTR(plane
));
5862 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
5864 intel_update_watermarks(dev
);
5866 intel_update_linetime_watermarks(dev
, pipe
, adjusted_mode
);
5871 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
5872 struct intel_crtc_config
*pipe_config
)
5874 struct drm_device
*dev
= crtc
->base
.dev
;
5875 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5876 enum transcoder cpu_transcoder
= crtc
->config
.cpu_transcoder
;
5879 if (!intel_using_power_well(dev_priv
->dev
) &&
5880 cpu_transcoder
!= TRANSCODER_EDP
)
5883 tmp
= I915_READ(PIPECONF(cpu_transcoder
));
5884 if (!(tmp
& PIPECONF_ENABLE
))
5888 * Haswell has only FDI/PCH transcoder A. It is which is connected to
5889 * DDI E. So just check whether this pipe is wired to DDI E and whether
5890 * the PCH transcoder is on.
5892 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
5893 if ((tmp
& TRANS_DDI_PORT_MASK
) == TRANS_DDI_SELECT_PORT(PORT_E
) &&
5894 I915_READ(TRANSCONF(PIPE_A
)) & TRANS_ENABLE
)
5895 pipe_config
->has_pch_encoder
= true;
5900 static int intel_crtc_mode_set(struct drm_crtc
*crtc
,
5902 struct drm_framebuffer
*fb
)
5904 struct drm_device
*dev
= crtc
->dev
;
5905 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5906 struct drm_encoder_helper_funcs
*encoder_funcs
;
5907 struct intel_encoder
*encoder
;
5908 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5909 struct drm_display_mode
*adjusted_mode
=
5910 &intel_crtc
->config
.adjusted_mode
;
5911 struct drm_display_mode
*mode
= &intel_crtc
->config
.requested_mode
;
5912 int pipe
= intel_crtc
->pipe
;
5915 drm_vblank_pre_modeset(dev
, pipe
);
5917 ret
= dev_priv
->display
.crtc_mode_set(crtc
, x
, y
, fb
);
5919 drm_vblank_post_modeset(dev
, pipe
);
5924 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5925 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5926 encoder
->base
.base
.id
,
5927 drm_get_encoder_name(&encoder
->base
),
5928 mode
->base
.id
, mode
->name
);
5929 if (encoder
->mode_set
) {
5930 encoder
->mode_set(encoder
);
5932 encoder_funcs
= encoder
->base
.helper_private
;
5933 encoder_funcs
->mode_set(&encoder
->base
, mode
, adjusted_mode
);
5940 static bool intel_eld_uptodate(struct drm_connector
*connector
,
5941 int reg_eldv
, uint32_t bits_eldv
,
5942 int reg_elda
, uint32_t bits_elda
,
5945 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
5946 uint8_t *eld
= connector
->eld
;
5949 i
= I915_READ(reg_eldv
);
5958 i
= I915_READ(reg_elda
);
5960 I915_WRITE(reg_elda
, i
);
5962 for (i
= 0; i
< eld
[2]; i
++)
5963 if (I915_READ(reg_edid
) != *((uint32_t *)eld
+ i
))
5969 static void g4x_write_eld(struct drm_connector
*connector
,
5970 struct drm_crtc
*crtc
)
5972 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
5973 uint8_t *eld
= connector
->eld
;
5978 i
= I915_READ(G4X_AUD_VID_DID
);
5980 if (i
== INTEL_AUDIO_DEVBLC
|| i
== INTEL_AUDIO_DEVCL
)
5981 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
5983 eldv
= G4X_ELDV_DEVCTG
;
5985 if (intel_eld_uptodate(connector
,
5986 G4X_AUD_CNTL_ST
, eldv
,
5987 G4X_AUD_CNTL_ST
, G4X_ELD_ADDR
,
5988 G4X_HDMIW_HDMIEDID
))
5991 i
= I915_READ(G4X_AUD_CNTL_ST
);
5992 i
&= ~(eldv
| G4X_ELD_ADDR
);
5993 len
= (i
>> 9) & 0x1f; /* ELD buffer size */
5994 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
5999 len
= min_t(uint8_t, eld
[2], len
);
6000 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6001 for (i
= 0; i
< len
; i
++)
6002 I915_WRITE(G4X_HDMIW_HDMIEDID
, *((uint32_t *)eld
+ i
));
6004 i
= I915_READ(G4X_AUD_CNTL_ST
);
6006 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
6009 static void haswell_write_eld(struct drm_connector
*connector
,
6010 struct drm_crtc
*crtc
)
6012 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6013 uint8_t *eld
= connector
->eld
;
6014 struct drm_device
*dev
= crtc
->dev
;
6015 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6019 int pipe
= to_intel_crtc(crtc
)->pipe
;
6022 int hdmiw_hdmiedid
= HSW_AUD_EDID_DATA(pipe
);
6023 int aud_cntl_st
= HSW_AUD_DIP_ELD_CTRL(pipe
);
6024 int aud_config
= HSW_AUD_CFG(pipe
);
6025 int aud_cntrl_st2
= HSW_AUD_PIN_ELD_CP_VLD
;
6028 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6030 /* Audio output enable */
6031 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6032 tmp
= I915_READ(aud_cntrl_st2
);
6033 tmp
|= (AUDIO_OUTPUT_ENABLE_A
<< (pipe
* 4));
6034 I915_WRITE(aud_cntrl_st2
, tmp
);
6036 /* Wait for 1 vertical blank */
6037 intel_wait_for_vblank(dev
, pipe
);
6039 /* Set ELD valid state */
6040 tmp
= I915_READ(aud_cntrl_st2
);
6041 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp
);
6042 tmp
|= (AUDIO_ELD_VALID_A
<< (pipe
* 4));
6043 I915_WRITE(aud_cntrl_st2
, tmp
);
6044 tmp
= I915_READ(aud_cntrl_st2
);
6045 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp
);
6047 /* Enable HDMI mode */
6048 tmp
= I915_READ(aud_config
);
6049 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp
);
6050 /* clear N_programing_enable and N_value_index */
6051 tmp
&= ~(AUD_CONFIG_N_VALUE_INDEX
| AUD_CONFIG_N_PROG_ENABLE
);
6052 I915_WRITE(aud_config
, tmp
);
6054 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
6056 eldv
= AUDIO_ELD_VALID_A
<< (pipe
* 4);
6057 intel_crtc
->eld_vld
= true;
6059 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
6060 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6061 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6062 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
6064 I915_WRITE(aud_config
, 0);
6066 if (intel_eld_uptodate(connector
,
6067 aud_cntrl_st2
, eldv
,
6068 aud_cntl_st
, IBX_ELD_ADDRESS
,
6072 i
= I915_READ(aud_cntrl_st2
);
6074 I915_WRITE(aud_cntrl_st2
, i
);
6079 i
= I915_READ(aud_cntl_st
);
6080 i
&= ~IBX_ELD_ADDRESS
;
6081 I915_WRITE(aud_cntl_st
, i
);
6082 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
6083 DRM_DEBUG_DRIVER("port num:%d\n", i
);
6085 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
6086 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6087 for (i
= 0; i
< len
; i
++)
6088 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
6090 i
= I915_READ(aud_cntrl_st2
);
6092 I915_WRITE(aud_cntrl_st2
, i
);
6096 static void ironlake_write_eld(struct drm_connector
*connector
,
6097 struct drm_crtc
*crtc
)
6099 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6100 uint8_t *eld
= connector
->eld
;
6108 int pipe
= to_intel_crtc(crtc
)->pipe
;
6110 if (HAS_PCH_IBX(connector
->dev
)) {
6111 hdmiw_hdmiedid
= IBX_HDMIW_HDMIEDID(pipe
);
6112 aud_config
= IBX_AUD_CFG(pipe
);
6113 aud_cntl_st
= IBX_AUD_CNTL_ST(pipe
);
6114 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
6116 hdmiw_hdmiedid
= CPT_HDMIW_HDMIEDID(pipe
);
6117 aud_config
= CPT_AUD_CFG(pipe
);
6118 aud_cntl_st
= CPT_AUD_CNTL_ST(pipe
);
6119 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
6122 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
6124 i
= I915_READ(aud_cntl_st
);
6125 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
6127 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6128 /* operate blindly on all ports */
6129 eldv
= IBX_ELD_VALIDB
;
6130 eldv
|= IBX_ELD_VALIDB
<< 4;
6131 eldv
|= IBX_ELD_VALIDB
<< 8;
6133 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i
));
6134 eldv
= IBX_ELD_VALIDB
<< ((i
- 1) * 4);
6137 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
6138 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6139 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6140 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
6142 I915_WRITE(aud_config
, 0);
6144 if (intel_eld_uptodate(connector
,
6145 aud_cntrl_st2
, eldv
,
6146 aud_cntl_st
, IBX_ELD_ADDRESS
,
6150 i
= I915_READ(aud_cntrl_st2
);
6152 I915_WRITE(aud_cntrl_st2
, i
);
6157 i
= I915_READ(aud_cntl_st
);
6158 i
&= ~IBX_ELD_ADDRESS
;
6159 I915_WRITE(aud_cntl_st
, i
);
6161 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
6162 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6163 for (i
= 0; i
< len
; i
++)
6164 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
6166 i
= I915_READ(aud_cntrl_st2
);
6168 I915_WRITE(aud_cntrl_st2
, i
);
6171 void intel_write_eld(struct drm_encoder
*encoder
,
6172 struct drm_display_mode
*mode
)
6174 struct drm_crtc
*crtc
= encoder
->crtc
;
6175 struct drm_connector
*connector
;
6176 struct drm_device
*dev
= encoder
->dev
;
6177 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6179 connector
= drm_select_eld(encoder
, mode
);
6183 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6185 drm_get_connector_name(connector
),
6186 connector
->encoder
->base
.id
,
6187 drm_get_encoder_name(connector
->encoder
));
6189 connector
->eld
[6] = drm_av_sync_delay(connector
, mode
) / 2;
6191 if (dev_priv
->display
.write_eld
)
6192 dev_priv
->display
.write_eld(connector
, crtc
);
6195 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6196 void intel_crtc_load_lut(struct drm_crtc
*crtc
)
6198 struct drm_device
*dev
= crtc
->dev
;
6199 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6200 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6201 int palreg
= PALETTE(intel_crtc
->pipe
);
6204 /* The clocks have to be on to load the palette. */
6205 if (!crtc
->enabled
|| !intel_crtc
->active
)
6208 /* use legacy palette for Ironlake */
6209 if (HAS_PCH_SPLIT(dev
))
6210 palreg
= LGC_PALETTE(intel_crtc
->pipe
);
6212 for (i
= 0; i
< 256; i
++) {
6213 I915_WRITE(palreg
+ 4 * i
,
6214 (intel_crtc
->lut_r
[i
] << 16) |
6215 (intel_crtc
->lut_g
[i
] << 8) |
6216 intel_crtc
->lut_b
[i
]);
6220 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6222 struct drm_device
*dev
= crtc
->dev
;
6223 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6224 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6225 bool visible
= base
!= 0;
6228 if (intel_crtc
->cursor_visible
== visible
)
6231 cntl
= I915_READ(_CURACNTR
);
6233 /* On these chipsets we can only modify the base whilst
6234 * the cursor is disabled.
6236 I915_WRITE(_CURABASE
, base
);
6238 cntl
&= ~(CURSOR_FORMAT_MASK
);
6239 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6240 cntl
|= CURSOR_ENABLE
|
6241 CURSOR_GAMMA_ENABLE
|
6244 cntl
&= ~(CURSOR_ENABLE
| CURSOR_GAMMA_ENABLE
);
6245 I915_WRITE(_CURACNTR
, cntl
);
6247 intel_crtc
->cursor_visible
= visible
;
6250 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6252 struct drm_device
*dev
= crtc
->dev
;
6253 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6254 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6255 int pipe
= intel_crtc
->pipe
;
6256 bool visible
= base
!= 0;
6258 if (intel_crtc
->cursor_visible
!= visible
) {
6259 uint32_t cntl
= I915_READ(CURCNTR(pipe
));
6261 cntl
&= ~(CURSOR_MODE
| MCURSOR_PIPE_SELECT
);
6262 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
6263 cntl
|= pipe
<< 28; /* Connect to correct pipe */
6265 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
6266 cntl
|= CURSOR_MODE_DISABLE
;
6268 I915_WRITE(CURCNTR(pipe
), cntl
);
6270 intel_crtc
->cursor_visible
= visible
;
6272 /* and commit changes on next vblank */
6273 I915_WRITE(CURBASE(pipe
), base
);
6276 static void ivb_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6278 struct drm_device
*dev
= crtc
->dev
;
6279 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6280 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6281 int pipe
= intel_crtc
->pipe
;
6282 bool visible
= base
!= 0;
6284 if (intel_crtc
->cursor_visible
!= visible
) {
6285 uint32_t cntl
= I915_READ(CURCNTR_IVB(pipe
));
6287 cntl
&= ~CURSOR_MODE
;
6288 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
6290 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
6291 cntl
|= CURSOR_MODE_DISABLE
;
6293 if (IS_HASWELL(dev
))
6294 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
6295 I915_WRITE(CURCNTR_IVB(pipe
), cntl
);
6297 intel_crtc
->cursor_visible
= visible
;
6299 /* and commit changes on next vblank */
6300 I915_WRITE(CURBASE_IVB(pipe
), base
);
6303 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6304 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
6307 struct drm_device
*dev
= crtc
->dev
;
6308 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6309 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6310 int pipe
= intel_crtc
->pipe
;
6311 int x
= intel_crtc
->cursor_x
;
6312 int y
= intel_crtc
->cursor_y
;
6318 if (on
&& crtc
->enabled
&& crtc
->fb
) {
6319 base
= intel_crtc
->cursor_addr
;
6320 if (x
> (int) crtc
->fb
->width
)
6323 if (y
> (int) crtc
->fb
->height
)
6329 if (x
+ intel_crtc
->cursor_width
< 0)
6332 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
6335 pos
|= x
<< CURSOR_X_SHIFT
;
6338 if (y
+ intel_crtc
->cursor_height
< 0)
6341 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
6344 pos
|= y
<< CURSOR_Y_SHIFT
;
6346 visible
= base
!= 0;
6347 if (!visible
&& !intel_crtc
->cursor_visible
)
6350 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
6351 I915_WRITE(CURPOS_IVB(pipe
), pos
);
6352 ivb_update_cursor(crtc
, base
);
6354 I915_WRITE(CURPOS(pipe
), pos
);
6355 if (IS_845G(dev
) || IS_I865G(dev
))
6356 i845_update_cursor(crtc
, base
);
6358 i9xx_update_cursor(crtc
, base
);
6362 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
6363 struct drm_file
*file
,
6365 uint32_t width
, uint32_t height
)
6367 struct drm_device
*dev
= crtc
->dev
;
6368 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6369 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6370 struct drm_i915_gem_object
*obj
;
6374 /* if we want to turn off the cursor ignore width and height */
6376 DRM_DEBUG_KMS("cursor off\n");
6379 mutex_lock(&dev
->struct_mutex
);
6383 /* Currently we only support 64x64 cursors */
6384 if (width
!= 64 || height
!= 64) {
6385 DRM_ERROR("we currently only support 64x64 cursors\n");
6389 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
6390 if (&obj
->base
== NULL
)
6393 if (obj
->base
.size
< width
* height
* 4) {
6394 DRM_ERROR("buffer is to small\n");
6399 /* we only need to pin inside GTT if cursor is non-phy */
6400 mutex_lock(&dev
->struct_mutex
);
6401 if (!dev_priv
->info
->cursor_needs_physical
) {
6404 if (obj
->tiling_mode
) {
6405 DRM_ERROR("cursor cannot be tiled\n");
6410 /* Note that the w/a also requires 2 PTE of padding following
6411 * the bo. We currently fill all unused PTE with the shadow
6412 * page and so we should always have valid PTE following the
6413 * cursor preventing the VT-d warning.
6416 if (need_vtd_wa(dev
))
6417 alignment
= 64*1024;
6419 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, NULL
);
6421 DRM_ERROR("failed to move cursor bo into the GTT\n");
6425 ret
= i915_gem_object_put_fence(obj
);
6427 DRM_ERROR("failed to release fence for cursor");
6431 addr
= obj
->gtt_offset
;
6433 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
6434 ret
= i915_gem_attach_phys_object(dev
, obj
,
6435 (intel_crtc
->pipe
== 0) ? I915_GEM_PHYS_CURSOR_0
: I915_GEM_PHYS_CURSOR_1
,
6438 DRM_ERROR("failed to attach phys object\n");
6441 addr
= obj
->phys_obj
->handle
->busaddr
;
6445 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
6448 if (intel_crtc
->cursor_bo
) {
6449 if (dev_priv
->info
->cursor_needs_physical
) {
6450 if (intel_crtc
->cursor_bo
!= obj
)
6451 i915_gem_detach_phys_object(dev
, intel_crtc
->cursor_bo
);
6453 i915_gem_object_unpin(intel_crtc
->cursor_bo
);
6454 drm_gem_object_unreference(&intel_crtc
->cursor_bo
->base
);
6457 mutex_unlock(&dev
->struct_mutex
);
6459 intel_crtc
->cursor_addr
= addr
;
6460 intel_crtc
->cursor_bo
= obj
;
6461 intel_crtc
->cursor_width
= width
;
6462 intel_crtc
->cursor_height
= height
;
6464 intel_crtc_update_cursor(crtc
, true);
6468 i915_gem_object_unpin(obj
);
6470 mutex_unlock(&dev
->struct_mutex
);
6472 drm_gem_object_unreference_unlocked(&obj
->base
);
6476 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
6478 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6480 intel_crtc
->cursor_x
= x
;
6481 intel_crtc
->cursor_y
= y
;
6483 intel_crtc_update_cursor(crtc
, true);
6488 /** Sets the color ramps on behalf of RandR */
6489 void intel_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
6490 u16 blue
, int regno
)
6492 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6494 intel_crtc
->lut_r
[regno
] = red
>> 8;
6495 intel_crtc
->lut_g
[regno
] = green
>> 8;
6496 intel_crtc
->lut_b
[regno
] = blue
>> 8;
6499 void intel_crtc_fb_gamma_get(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
6500 u16
*blue
, int regno
)
6502 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6504 *red
= intel_crtc
->lut_r
[regno
] << 8;
6505 *green
= intel_crtc
->lut_g
[regno
] << 8;
6506 *blue
= intel_crtc
->lut_b
[regno
] << 8;
6509 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
6510 u16
*blue
, uint32_t start
, uint32_t size
)
6512 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
6513 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6515 for (i
= start
; i
< end
; i
++) {
6516 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
6517 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
6518 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
6521 intel_crtc_load_lut(crtc
);
6524 /* VESA 640x480x72Hz mode to set on the pipe */
6525 static struct drm_display_mode load_detect_mode
= {
6526 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
6527 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
6530 static struct drm_framebuffer
*
6531 intel_framebuffer_create(struct drm_device
*dev
,
6532 struct drm_mode_fb_cmd2
*mode_cmd
,
6533 struct drm_i915_gem_object
*obj
)
6535 struct intel_framebuffer
*intel_fb
;
6538 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
6540 drm_gem_object_unreference_unlocked(&obj
->base
);
6541 return ERR_PTR(-ENOMEM
);
6544 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
6546 drm_gem_object_unreference_unlocked(&obj
->base
);
6548 return ERR_PTR(ret
);
6551 return &intel_fb
->base
;
6555 intel_framebuffer_pitch_for_width(int width
, int bpp
)
6557 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
6558 return ALIGN(pitch
, 64);
6562 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
6564 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
6565 return ALIGN(pitch
* mode
->vdisplay
, PAGE_SIZE
);
6568 static struct drm_framebuffer
*
6569 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
6570 struct drm_display_mode
*mode
,
6573 struct drm_i915_gem_object
*obj
;
6574 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
6576 obj
= i915_gem_alloc_object(dev
,
6577 intel_framebuffer_size_for_mode(mode
, bpp
));
6579 return ERR_PTR(-ENOMEM
);
6581 mode_cmd
.width
= mode
->hdisplay
;
6582 mode_cmd
.height
= mode
->vdisplay
;
6583 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
6585 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
6587 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
6590 static struct drm_framebuffer
*
6591 mode_fits_in_fbdev(struct drm_device
*dev
,
6592 struct drm_display_mode
*mode
)
6594 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6595 struct drm_i915_gem_object
*obj
;
6596 struct drm_framebuffer
*fb
;
6598 if (dev_priv
->fbdev
== NULL
)
6601 obj
= dev_priv
->fbdev
->ifb
.obj
;
6605 fb
= &dev_priv
->fbdev
->ifb
.base
;
6606 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
6607 fb
->bits_per_pixel
))
6610 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
6616 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
6617 struct drm_display_mode
*mode
,
6618 struct intel_load_detect_pipe
*old
)
6620 struct intel_crtc
*intel_crtc
;
6621 struct intel_encoder
*intel_encoder
=
6622 intel_attached_encoder(connector
);
6623 struct drm_crtc
*possible_crtc
;
6624 struct drm_encoder
*encoder
= &intel_encoder
->base
;
6625 struct drm_crtc
*crtc
= NULL
;
6626 struct drm_device
*dev
= encoder
->dev
;
6627 struct drm_framebuffer
*fb
;
6630 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6631 connector
->base
.id
, drm_get_connector_name(connector
),
6632 encoder
->base
.id
, drm_get_encoder_name(encoder
));
6635 * Algorithm gets a little messy:
6637 * - if the connector already has an assigned crtc, use it (but make
6638 * sure it's on first)
6640 * - try to find the first unused crtc that can drive this connector,
6641 * and use that if we find one
6644 /* See if we already have a CRTC for this connector */
6645 if (encoder
->crtc
) {
6646 crtc
= encoder
->crtc
;
6648 mutex_lock(&crtc
->mutex
);
6650 old
->dpms_mode
= connector
->dpms
;
6651 old
->load_detect_temp
= false;
6653 /* Make sure the crtc and connector are running */
6654 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
6655 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
6660 /* Find an unused one (if possible) */
6661 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
6663 if (!(encoder
->possible_crtcs
& (1 << i
)))
6665 if (!possible_crtc
->enabled
) {
6666 crtc
= possible_crtc
;
6672 * If we didn't find an unused CRTC, don't use any.
6675 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6679 mutex_lock(&crtc
->mutex
);
6680 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
6681 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
6683 intel_crtc
= to_intel_crtc(crtc
);
6684 old
->dpms_mode
= connector
->dpms
;
6685 old
->load_detect_temp
= true;
6686 old
->release_fb
= NULL
;
6689 mode
= &load_detect_mode
;
6691 /* We need a framebuffer large enough to accommodate all accesses
6692 * that the plane may generate whilst we perform load detection.
6693 * We can not rely on the fbcon either being present (we get called
6694 * during its initialisation to detect all boot displays, or it may
6695 * not even exist) or that it is large enough to satisfy the
6698 fb
= mode_fits_in_fbdev(dev
, mode
);
6700 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6701 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
6702 old
->release_fb
= fb
;
6704 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6706 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6707 mutex_unlock(&crtc
->mutex
);
6711 if (intel_set_mode(crtc
, mode
, 0, 0, fb
)) {
6712 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6713 if (old
->release_fb
)
6714 old
->release_fb
->funcs
->destroy(old
->release_fb
);
6715 mutex_unlock(&crtc
->mutex
);
6719 /* let the connector get through one full cycle before testing */
6720 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
6724 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
6725 struct intel_load_detect_pipe
*old
)
6727 struct intel_encoder
*intel_encoder
=
6728 intel_attached_encoder(connector
);
6729 struct drm_encoder
*encoder
= &intel_encoder
->base
;
6730 struct drm_crtc
*crtc
= encoder
->crtc
;
6732 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6733 connector
->base
.id
, drm_get_connector_name(connector
),
6734 encoder
->base
.id
, drm_get_encoder_name(encoder
));
6736 if (old
->load_detect_temp
) {
6737 to_intel_connector(connector
)->new_encoder
= NULL
;
6738 intel_encoder
->new_crtc
= NULL
;
6739 intel_set_mode(crtc
, NULL
, 0, 0, NULL
);
6741 if (old
->release_fb
) {
6742 drm_framebuffer_unregister_private(old
->release_fb
);
6743 drm_framebuffer_unreference(old
->release_fb
);
6746 mutex_unlock(&crtc
->mutex
);
6750 /* Switch crtc and encoder back off if necessary */
6751 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
6752 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
6754 mutex_unlock(&crtc
->mutex
);
6757 /* Returns the clock of the currently programmed mode of the given pipe. */
6758 static int intel_crtc_clock_get(struct drm_device
*dev
, struct drm_crtc
*crtc
)
6760 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6761 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6762 int pipe
= intel_crtc
->pipe
;
6763 u32 dpll
= I915_READ(DPLL(pipe
));
6765 intel_clock_t clock
;
6767 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
6768 fp
= I915_READ(FP0(pipe
));
6770 fp
= I915_READ(FP1(pipe
));
6772 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
6773 if (IS_PINEVIEW(dev
)) {
6774 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
6775 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
6777 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
6778 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
6781 if (!IS_GEN2(dev
)) {
6782 if (IS_PINEVIEW(dev
))
6783 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
6784 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
6786 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
6787 DPLL_FPA01_P1_POST_DIV_SHIFT
);
6789 switch (dpll
& DPLL_MODE_MASK
) {
6790 case DPLLB_MODE_DAC_SERIAL
:
6791 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
6794 case DPLLB_MODE_LVDS
:
6795 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
6799 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6800 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
6804 /* XXX: Handle the 100Mhz refclk */
6805 intel_clock(dev
, 96000, &clock
);
6807 bool is_lvds
= (pipe
== 1) && (I915_READ(LVDS
) & LVDS_PORT_EN
);
6810 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
6811 DPLL_FPA01_P1_POST_DIV_SHIFT
);
6814 if ((dpll
& PLL_REF_INPUT_MASK
) ==
6815 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
6816 /* XXX: might not be 66MHz */
6817 intel_clock(dev
, 66000, &clock
);
6819 intel_clock(dev
, 48000, &clock
);
6821 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
6824 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
6825 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
6827 if (dpll
& PLL_P2_DIVIDE_BY_4
)
6832 intel_clock(dev
, 48000, &clock
);
6836 /* XXX: It would be nice to validate the clocks, but we can't reuse
6837 * i830PllIsValid() because it relies on the xf86_config connector
6838 * configuration being accurate, which it isn't necessarily.
6844 /** Returns the currently programmed mode of the given pipe. */
6845 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
6846 struct drm_crtc
*crtc
)
6848 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6849 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6850 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
6851 struct drm_display_mode
*mode
;
6852 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
6853 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
6854 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
6855 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
6857 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
6861 mode
->clock
= intel_crtc_clock_get(dev
, crtc
);
6862 mode
->hdisplay
= (htot
& 0xffff) + 1;
6863 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
6864 mode
->hsync_start
= (hsync
& 0xffff) + 1;
6865 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
6866 mode
->vdisplay
= (vtot
& 0xffff) + 1;
6867 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
6868 mode
->vsync_start
= (vsync
& 0xffff) + 1;
6869 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
6871 drm_mode_set_name(mode
);
6876 static void intel_increase_pllclock(struct drm_crtc
*crtc
)
6878 struct drm_device
*dev
= crtc
->dev
;
6879 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6880 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6881 int pipe
= intel_crtc
->pipe
;
6882 int dpll_reg
= DPLL(pipe
);
6885 if (HAS_PCH_SPLIT(dev
))
6888 if (!dev_priv
->lvds_downclock_avail
)
6891 dpll
= I915_READ(dpll_reg
);
6892 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
6893 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6895 assert_panel_unlocked(dev_priv
, pipe
);
6897 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
6898 I915_WRITE(dpll_reg
, dpll
);
6899 intel_wait_for_vblank(dev
, pipe
);
6901 dpll
= I915_READ(dpll_reg
);
6902 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
6903 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6907 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
6909 struct drm_device
*dev
= crtc
->dev
;
6910 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6911 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6913 if (HAS_PCH_SPLIT(dev
))
6916 if (!dev_priv
->lvds_downclock_avail
)
6920 * Since this is called by a timer, we should never get here in
6923 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
6924 int pipe
= intel_crtc
->pipe
;
6925 int dpll_reg
= DPLL(pipe
);
6928 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6930 assert_panel_unlocked(dev_priv
, pipe
);
6932 dpll
= I915_READ(dpll_reg
);
6933 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
6934 I915_WRITE(dpll_reg
, dpll
);
6935 intel_wait_for_vblank(dev
, pipe
);
6936 dpll
= I915_READ(dpll_reg
);
6937 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
6938 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6943 void intel_mark_busy(struct drm_device
*dev
)
6945 i915_update_gfx_val(dev
->dev_private
);
6948 void intel_mark_idle(struct drm_device
*dev
)
6950 struct drm_crtc
*crtc
;
6952 if (!i915_powersave
)
6955 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
6959 intel_decrease_pllclock(crtc
);
6963 void intel_mark_fb_busy(struct drm_i915_gem_object
*obj
)
6965 struct drm_device
*dev
= obj
->base
.dev
;
6966 struct drm_crtc
*crtc
;
6968 if (!i915_powersave
)
6971 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
6975 if (to_intel_framebuffer(crtc
->fb
)->obj
== obj
)
6976 intel_increase_pllclock(crtc
);
6980 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
6982 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6983 struct drm_device
*dev
= crtc
->dev
;
6984 struct intel_unpin_work
*work
;
6985 unsigned long flags
;
6987 spin_lock_irqsave(&dev
->event_lock
, flags
);
6988 work
= intel_crtc
->unpin_work
;
6989 intel_crtc
->unpin_work
= NULL
;
6990 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6993 cancel_work_sync(&work
->work
);
6997 drm_crtc_cleanup(crtc
);
7002 static void intel_unpin_work_fn(struct work_struct
*__work
)
7004 struct intel_unpin_work
*work
=
7005 container_of(__work
, struct intel_unpin_work
, work
);
7006 struct drm_device
*dev
= work
->crtc
->dev
;
7008 mutex_lock(&dev
->struct_mutex
);
7009 intel_unpin_fb_obj(work
->old_fb_obj
);
7010 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
7011 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
7013 intel_update_fbc(dev
);
7014 mutex_unlock(&dev
->struct_mutex
);
7016 BUG_ON(atomic_read(&to_intel_crtc(work
->crtc
)->unpin_work_count
) == 0);
7017 atomic_dec(&to_intel_crtc(work
->crtc
)->unpin_work_count
);
7022 static void do_intel_finish_page_flip(struct drm_device
*dev
,
7023 struct drm_crtc
*crtc
)
7025 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7026 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7027 struct intel_unpin_work
*work
;
7028 unsigned long flags
;
7030 /* Ignore early vblank irqs */
7031 if (intel_crtc
== NULL
)
7034 spin_lock_irqsave(&dev
->event_lock
, flags
);
7035 work
= intel_crtc
->unpin_work
;
7037 /* Ensure we don't miss a work->pending update ... */
7040 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
7041 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7045 /* and that the unpin work is consistent wrt ->pending. */
7048 intel_crtc
->unpin_work
= NULL
;
7051 drm_send_vblank_event(dev
, intel_crtc
->pipe
, work
->event
);
7053 drm_vblank_put(dev
, intel_crtc
->pipe
);
7055 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7057 wake_up_all(&dev_priv
->pending_flip_queue
);
7059 queue_work(dev_priv
->wq
, &work
->work
);
7061 trace_i915_flip_complete(intel_crtc
->plane
, work
->pending_flip_obj
);
7064 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
7066 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7067 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
7069 do_intel_finish_page_flip(dev
, crtc
);
7072 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
7074 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7075 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
7077 do_intel_finish_page_flip(dev
, crtc
);
7080 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
7082 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7083 struct intel_crtc
*intel_crtc
=
7084 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
7085 unsigned long flags
;
7087 /* NB: An MMIO update of the plane base pointer will also
7088 * generate a page-flip completion irq, i.e. every modeset
7089 * is also accompanied by a spurious intel_prepare_page_flip().
7091 spin_lock_irqsave(&dev
->event_lock
, flags
);
7092 if (intel_crtc
->unpin_work
)
7093 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
7094 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7097 inline static void intel_mark_page_flip_active(struct intel_crtc
*intel_crtc
)
7099 /* Ensure that the work item is consistent when activating it ... */
7101 atomic_set(&intel_crtc
->unpin_work
->pending
, INTEL_FLIP_PENDING
);
7102 /* and that it is marked active as soon as the irq could fire. */
7106 static int intel_gen2_queue_flip(struct drm_device
*dev
,
7107 struct drm_crtc
*crtc
,
7108 struct drm_framebuffer
*fb
,
7109 struct drm_i915_gem_object
*obj
)
7111 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7112 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7114 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7117 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7121 ret
= intel_ring_begin(ring
, 6);
7125 /* Can't queue multiple flips, so wait for the previous
7126 * one to finish before executing the next.
7128 if (intel_crtc
->plane
)
7129 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
7131 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
7132 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
7133 intel_ring_emit(ring
, MI_NOOP
);
7134 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7135 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7136 intel_ring_emit(ring
, fb
->pitches
[0]);
7137 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
7138 intel_ring_emit(ring
, 0); /* aux display base address, unused */
7140 intel_mark_page_flip_active(intel_crtc
);
7141 intel_ring_advance(ring
);
7145 intel_unpin_fb_obj(obj
);
7150 static int intel_gen3_queue_flip(struct drm_device
*dev
,
7151 struct drm_crtc
*crtc
,
7152 struct drm_framebuffer
*fb
,
7153 struct drm_i915_gem_object
*obj
)
7155 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7156 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7158 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7161 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7165 ret
= intel_ring_begin(ring
, 6);
7169 if (intel_crtc
->plane
)
7170 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
7172 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
7173 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
7174 intel_ring_emit(ring
, MI_NOOP
);
7175 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
7176 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7177 intel_ring_emit(ring
, fb
->pitches
[0]);
7178 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
7179 intel_ring_emit(ring
, MI_NOOP
);
7181 intel_mark_page_flip_active(intel_crtc
);
7182 intel_ring_advance(ring
);
7186 intel_unpin_fb_obj(obj
);
7191 static int intel_gen4_queue_flip(struct drm_device
*dev
,
7192 struct drm_crtc
*crtc
,
7193 struct drm_framebuffer
*fb
,
7194 struct drm_i915_gem_object
*obj
)
7196 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7197 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7198 uint32_t pf
, pipesrc
;
7199 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7202 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7206 ret
= intel_ring_begin(ring
, 4);
7210 /* i965+ uses the linear or tiled offsets from the
7211 * Display Registers (which do not change across a page-flip)
7212 * so we need only reprogram the base address.
7214 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7215 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7216 intel_ring_emit(ring
, fb
->pitches
[0]);
7217 intel_ring_emit(ring
,
7218 (obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
) |
7221 /* XXX Enabling the panel-fitter across page-flip is so far
7222 * untested on non-native modes, so ignore it for now.
7223 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7226 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
7227 intel_ring_emit(ring
, pf
| pipesrc
);
7229 intel_mark_page_flip_active(intel_crtc
);
7230 intel_ring_advance(ring
);
7234 intel_unpin_fb_obj(obj
);
7239 static int intel_gen6_queue_flip(struct drm_device
*dev
,
7240 struct drm_crtc
*crtc
,
7241 struct drm_framebuffer
*fb
,
7242 struct drm_i915_gem_object
*obj
)
7244 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7245 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7246 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7247 uint32_t pf
, pipesrc
;
7250 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7254 ret
= intel_ring_begin(ring
, 4);
7258 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7259 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7260 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
7261 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
7263 /* Contrary to the suggestions in the documentation,
7264 * "Enable Panel Fitter" does not seem to be required when page
7265 * flipping with a non-native mode, and worse causes a normal
7267 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7270 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
7271 intel_ring_emit(ring
, pf
| pipesrc
);
7273 intel_mark_page_flip_active(intel_crtc
);
7274 intel_ring_advance(ring
);
7278 intel_unpin_fb_obj(obj
);
7284 * On gen7 we currently use the blit ring because (in early silicon at least)
7285 * the render ring doesn't give us interrpts for page flip completion, which
7286 * means clients will hang after the first flip is queued. Fortunately the
7287 * blit ring generates interrupts properly, so use it instead.
7289 static int intel_gen7_queue_flip(struct drm_device
*dev
,
7290 struct drm_crtc
*crtc
,
7291 struct drm_framebuffer
*fb
,
7292 struct drm_i915_gem_object
*obj
)
7294 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7295 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7296 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[BCS
];
7297 uint32_t plane_bit
= 0;
7300 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7304 switch(intel_crtc
->plane
) {
7306 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
7309 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
7312 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
7315 WARN_ONCE(1, "unknown plane in flip command\n");
7320 ret
= intel_ring_begin(ring
, 4);
7324 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
7325 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
7326 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
7327 intel_ring_emit(ring
, (MI_NOOP
));
7329 intel_mark_page_flip_active(intel_crtc
);
7330 intel_ring_advance(ring
);
7334 intel_unpin_fb_obj(obj
);
7339 static int intel_default_queue_flip(struct drm_device
*dev
,
7340 struct drm_crtc
*crtc
,
7341 struct drm_framebuffer
*fb
,
7342 struct drm_i915_gem_object
*obj
)
7347 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
7348 struct drm_framebuffer
*fb
,
7349 struct drm_pending_vblank_event
*event
)
7351 struct drm_device
*dev
= crtc
->dev
;
7352 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7353 struct drm_framebuffer
*old_fb
= crtc
->fb
;
7354 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(fb
)->obj
;
7355 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7356 struct intel_unpin_work
*work
;
7357 unsigned long flags
;
7360 /* Can't change pixel format via MI display flips. */
7361 if (fb
->pixel_format
!= crtc
->fb
->pixel_format
)
7365 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7366 * Note that pitch changes could also affect these register.
7368 if (INTEL_INFO(dev
)->gen
> 3 &&
7369 (fb
->offsets
[0] != crtc
->fb
->offsets
[0] ||
7370 fb
->pitches
[0] != crtc
->fb
->pitches
[0]))
7373 work
= kzalloc(sizeof *work
, GFP_KERNEL
);
7377 work
->event
= event
;
7379 work
->old_fb_obj
= to_intel_framebuffer(old_fb
)->obj
;
7380 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
7382 ret
= drm_vblank_get(dev
, intel_crtc
->pipe
);
7386 /* We borrow the event spin lock for protecting unpin_work */
7387 spin_lock_irqsave(&dev
->event_lock
, flags
);
7388 if (intel_crtc
->unpin_work
) {
7389 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7391 drm_vblank_put(dev
, intel_crtc
->pipe
);
7393 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7396 intel_crtc
->unpin_work
= work
;
7397 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7399 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
7400 flush_workqueue(dev_priv
->wq
);
7402 ret
= i915_mutex_lock_interruptible(dev
);
7406 /* Reference the objects for the scheduled work. */
7407 drm_gem_object_reference(&work
->old_fb_obj
->base
);
7408 drm_gem_object_reference(&obj
->base
);
7412 work
->pending_flip_obj
= obj
;
7414 work
->enable_stall_check
= true;
7416 atomic_inc(&intel_crtc
->unpin_work_count
);
7417 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
7419 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
);
7421 goto cleanup_pending
;
7423 intel_disable_fbc(dev
);
7424 intel_mark_fb_busy(obj
);
7425 mutex_unlock(&dev
->struct_mutex
);
7427 trace_i915_flip_request(intel_crtc
->plane
, obj
);
7432 atomic_dec(&intel_crtc
->unpin_work_count
);
7434 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
7435 drm_gem_object_unreference(&obj
->base
);
7436 mutex_unlock(&dev
->struct_mutex
);
7439 spin_lock_irqsave(&dev
->event_lock
, flags
);
7440 intel_crtc
->unpin_work
= NULL
;
7441 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7443 drm_vblank_put(dev
, intel_crtc
->pipe
);
7450 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
7451 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
7452 .load_lut
= intel_crtc_load_lut
,
7455 bool intel_encoder_check_is_cloned(struct intel_encoder
*encoder
)
7457 struct intel_encoder
*other_encoder
;
7458 struct drm_crtc
*crtc
= &encoder
->new_crtc
->base
;
7463 list_for_each_entry(other_encoder
,
7464 &crtc
->dev
->mode_config
.encoder_list
,
7467 if (&other_encoder
->new_crtc
->base
!= crtc
||
7468 encoder
== other_encoder
)
7477 static bool intel_encoder_crtc_ok(struct drm_encoder
*encoder
,
7478 struct drm_crtc
*crtc
)
7480 struct drm_device
*dev
;
7481 struct drm_crtc
*tmp
;
7484 WARN(!crtc
, "checking null crtc?\n");
7488 list_for_each_entry(tmp
, &dev
->mode_config
.crtc_list
, head
) {
7494 if (encoder
->possible_crtcs
& crtc_mask
)
7500 * intel_modeset_update_staged_output_state
7502 * Updates the staged output configuration state, e.g. after we've read out the
7505 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
7507 struct intel_encoder
*encoder
;
7508 struct intel_connector
*connector
;
7510 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7512 connector
->new_encoder
=
7513 to_intel_encoder(connector
->base
.encoder
);
7516 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7519 to_intel_crtc(encoder
->base
.crtc
);
7524 * intel_modeset_commit_output_state
7526 * This function copies the stage display pipe configuration to the real one.
7528 static void intel_modeset_commit_output_state(struct drm_device
*dev
)
7530 struct intel_encoder
*encoder
;
7531 struct intel_connector
*connector
;
7533 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7535 connector
->base
.encoder
= &connector
->new_encoder
->base
;
7538 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7540 encoder
->base
.crtc
= &encoder
->new_crtc
->base
;
7545 pipe_config_set_bpp(struct drm_crtc
*crtc
,
7546 struct drm_framebuffer
*fb
,
7547 struct intel_crtc_config
*pipe_config
)
7549 struct drm_device
*dev
= crtc
->dev
;
7550 struct drm_connector
*connector
;
7553 switch (fb
->pixel_format
) {
7555 bpp
= 8*3; /* since we go through a colormap */
7557 case DRM_FORMAT_XRGB1555
:
7558 case DRM_FORMAT_ARGB1555
:
7559 /* checked in intel_framebuffer_init already */
7560 if (WARN_ON(INTEL_INFO(dev
)->gen
> 3))
7562 case DRM_FORMAT_RGB565
:
7563 bpp
= 6*3; /* min is 18bpp */
7565 case DRM_FORMAT_XBGR8888
:
7566 case DRM_FORMAT_ABGR8888
:
7567 /* checked in intel_framebuffer_init already */
7568 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
7570 case DRM_FORMAT_XRGB8888
:
7571 case DRM_FORMAT_ARGB8888
:
7574 case DRM_FORMAT_XRGB2101010
:
7575 case DRM_FORMAT_ARGB2101010
:
7576 case DRM_FORMAT_XBGR2101010
:
7577 case DRM_FORMAT_ABGR2101010
:
7578 /* checked in intel_framebuffer_init already */
7579 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
7583 /* TODO: gen4+ supports 16 bpc floating point, too. */
7585 DRM_DEBUG_KMS("unsupported depth\n");
7589 pipe_config
->pipe_bpp
= bpp
;
7591 /* Clamp display bpp to EDID value */
7592 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7594 if (connector
->encoder
&& connector
->encoder
->crtc
!= crtc
)
7597 /* Don't use an invalid EDID bpc value */
7598 if (connector
->display_info
.bpc
&&
7599 connector
->display_info
.bpc
* 3 < bpp
) {
7600 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7601 bpp
, connector
->display_info
.bpc
*3);
7602 pipe_config
->pipe_bpp
= connector
->display_info
.bpc
*3;
7605 /* Clamp bpp to 8 on screens without EDID 1.4 */
7606 if (connector
->display_info
.bpc
== 0 && bpp
> 24) {
7607 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7609 pipe_config
->pipe_bpp
= 24;
7616 static struct intel_crtc_config
*
7617 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
7618 struct drm_framebuffer
*fb
,
7619 struct drm_display_mode
*mode
)
7621 struct drm_device
*dev
= crtc
->dev
;
7622 struct drm_encoder_helper_funcs
*encoder_funcs
;
7623 struct intel_encoder
*encoder
;
7624 struct intel_crtc_config
*pipe_config
;
7627 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
7629 return ERR_PTR(-ENOMEM
);
7631 drm_mode_copy(&pipe_config
->adjusted_mode
, mode
);
7632 drm_mode_copy(&pipe_config
->requested_mode
, mode
);
7634 plane_bpp
= pipe_config_set_bpp(crtc
, fb
, pipe_config
);
7638 /* Pass our mode to the connectors and the CRTC to give them a chance to
7639 * adjust it according to limitations or connector properties, and also
7640 * a chance to reject the mode entirely.
7642 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7645 if (&encoder
->new_crtc
->base
!= crtc
)
7648 if (encoder
->compute_config
) {
7649 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
7650 DRM_DEBUG_KMS("Encoder config failure\n");
7657 encoder_funcs
= encoder
->base
.helper_private
;
7658 if (!(encoder_funcs
->mode_fixup(&encoder
->base
,
7659 &pipe_config
->requested_mode
,
7660 &pipe_config
->adjusted_mode
))) {
7661 DRM_DEBUG_KMS("Encoder fixup failed\n");
7666 if (!(intel_crtc_compute_config(crtc
, pipe_config
))) {
7667 DRM_DEBUG_KMS("CRTC fixup failed\n");
7670 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc
->base
.id
);
7672 pipe_config
->dither
= pipe_config
->pipe_bpp
!= plane_bpp
;
7673 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7674 plane_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
7679 return ERR_PTR(-EINVAL
);
7682 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7683 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7685 intel_modeset_affected_pipes(struct drm_crtc
*crtc
, unsigned *modeset_pipes
,
7686 unsigned *prepare_pipes
, unsigned *disable_pipes
)
7688 struct intel_crtc
*intel_crtc
;
7689 struct drm_device
*dev
= crtc
->dev
;
7690 struct intel_encoder
*encoder
;
7691 struct intel_connector
*connector
;
7692 struct drm_crtc
*tmp_crtc
;
7694 *disable_pipes
= *modeset_pipes
= *prepare_pipes
= 0;
7696 /* Check which crtcs have changed outputs connected to them, these need
7697 * to be part of the prepare_pipes mask. We don't (yet) support global
7698 * modeset across multiple crtcs, so modeset_pipes will only have one
7699 * bit set at most. */
7700 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7702 if (connector
->base
.encoder
== &connector
->new_encoder
->base
)
7705 if (connector
->base
.encoder
) {
7706 tmp_crtc
= connector
->base
.encoder
->crtc
;
7708 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
7711 if (connector
->new_encoder
)
7713 1 << connector
->new_encoder
->new_crtc
->pipe
;
7716 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7718 if (encoder
->base
.crtc
== &encoder
->new_crtc
->base
)
7721 if (encoder
->base
.crtc
) {
7722 tmp_crtc
= encoder
->base
.crtc
;
7724 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
7727 if (encoder
->new_crtc
)
7728 *prepare_pipes
|= 1 << encoder
->new_crtc
->pipe
;
7731 /* Check for any pipes that will be fully disabled ... */
7732 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
7736 /* Don't try to disable disabled crtcs. */
7737 if (!intel_crtc
->base
.enabled
)
7740 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7742 if (encoder
->new_crtc
== intel_crtc
)
7747 *disable_pipes
|= 1 << intel_crtc
->pipe
;
7751 /* set_mode is also used to update properties on life display pipes. */
7752 intel_crtc
= to_intel_crtc(crtc
);
7754 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
7757 * For simplicity do a full modeset on any pipe where the output routing
7758 * changed. We could be more clever, but that would require us to be
7759 * more careful with calling the relevant encoder->mode_set functions.
7762 *modeset_pipes
= *prepare_pipes
;
7764 /* ... and mask these out. */
7765 *modeset_pipes
&= ~(*disable_pipes
);
7766 *prepare_pipes
&= ~(*disable_pipes
);
7769 * HACK: We don't (yet) fully support global modesets. intel_set_config
7770 * obies this rule, but the modeset restore mode of
7771 * intel_modeset_setup_hw_state does not.
7773 *modeset_pipes
&= 1 << intel_crtc
->pipe
;
7774 *prepare_pipes
&= 1 << intel_crtc
->pipe
;
7776 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7777 *modeset_pipes
, *prepare_pipes
, *disable_pipes
);
7780 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
7782 struct drm_encoder
*encoder
;
7783 struct drm_device
*dev
= crtc
->dev
;
7785 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
7786 if (encoder
->crtc
== crtc
)
7793 intel_modeset_update_state(struct drm_device
*dev
, unsigned prepare_pipes
)
7795 struct intel_encoder
*intel_encoder
;
7796 struct intel_crtc
*intel_crtc
;
7797 struct drm_connector
*connector
;
7799 list_for_each_entry(intel_encoder
, &dev
->mode_config
.encoder_list
,
7801 if (!intel_encoder
->base
.crtc
)
7804 intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
7806 if (prepare_pipes
& (1 << intel_crtc
->pipe
))
7807 intel_encoder
->connectors_active
= false;
7810 intel_modeset_commit_output_state(dev
);
7812 /* Update computed state. */
7813 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
7815 intel_crtc
->base
.enabled
= intel_crtc_in_use(&intel_crtc
->base
);
7818 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
7819 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
7822 intel_crtc
= to_intel_crtc(connector
->encoder
->crtc
);
7824 if (prepare_pipes
& (1 << intel_crtc
->pipe
)) {
7825 struct drm_property
*dpms_property
=
7826 dev
->mode_config
.dpms_property
;
7828 connector
->dpms
= DRM_MODE_DPMS_ON
;
7829 drm_object_property_set_value(&connector
->base
,
7833 intel_encoder
= to_intel_encoder(connector
->encoder
);
7834 intel_encoder
->connectors_active
= true;
7840 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7841 list_for_each_entry((intel_crtc), \
7842 &(dev)->mode_config.crtc_list, \
7844 if (mask & (1 <<(intel_crtc)->pipe)) \
7847 intel_pipe_config_compare(struct intel_crtc_config
*current_config
,
7848 struct intel_crtc_config
*pipe_config
)
7850 if (current_config
->has_pch_encoder
!= pipe_config
->has_pch_encoder
) {
7851 DRM_ERROR("mismatch in has_pch_encoder "
7852 "(expected %i, found %i)\n",
7853 current_config
->has_pch_encoder
,
7854 pipe_config
->has_pch_encoder
);
7862 intel_modeset_check_state(struct drm_device
*dev
)
7864 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7865 struct intel_crtc
*crtc
;
7866 struct intel_encoder
*encoder
;
7867 struct intel_connector
*connector
;
7868 struct intel_crtc_config pipe_config
;
7870 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7872 /* This also checks the encoder/connector hw state with the
7873 * ->get_hw_state callbacks. */
7874 intel_connector_check_state(connector
);
7876 WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
7877 "connector's staged encoder doesn't match current encoder\n");
7880 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7882 bool enabled
= false;
7883 bool active
= false;
7884 enum pipe pipe
, tracked_pipe
;
7886 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7887 encoder
->base
.base
.id
,
7888 drm_get_encoder_name(&encoder
->base
));
7890 WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
7891 "encoder's stage crtc doesn't match current crtc\n");
7892 WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
7893 "encoder's active_connectors set, but no crtc\n");
7895 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7897 if (connector
->base
.encoder
!= &encoder
->base
)
7900 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
7903 WARN(!!encoder
->base
.crtc
!= enabled
,
7904 "encoder's enabled state mismatch "
7905 "(expected %i, found %i)\n",
7906 !!encoder
->base
.crtc
, enabled
);
7907 WARN(active
&& !encoder
->base
.crtc
,
7908 "active encoder with no crtc\n");
7910 WARN(encoder
->connectors_active
!= active
,
7911 "encoder's computed active state doesn't match tracked active state "
7912 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
7914 active
= encoder
->get_hw_state(encoder
, &pipe
);
7915 WARN(active
!= encoder
->connectors_active
,
7916 "encoder's hw state doesn't match sw tracking "
7917 "(expected %i, found %i)\n",
7918 encoder
->connectors_active
, active
);
7920 if (!encoder
->base
.crtc
)
7923 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
7924 WARN(active
&& pipe
!= tracked_pipe
,
7925 "active encoder's pipe doesn't match"
7926 "(expected %i, found %i)\n",
7927 tracked_pipe
, pipe
);
7931 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
7933 bool enabled
= false;
7934 bool active
= false;
7936 DRM_DEBUG_KMS("[CRTC:%d]\n",
7937 crtc
->base
.base
.id
);
7939 WARN(crtc
->active
&& !crtc
->base
.enabled
,
7940 "active crtc, but not enabled in sw tracking\n");
7942 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7944 if (encoder
->base
.crtc
!= &crtc
->base
)
7947 if (encoder
->connectors_active
)
7950 WARN(active
!= crtc
->active
,
7951 "crtc's computed active state doesn't match tracked active state "
7952 "(expected %i, found %i)\n", active
, crtc
->active
);
7953 WARN(enabled
!= crtc
->base
.enabled
,
7954 "crtc's computed enabled state doesn't match tracked enabled state "
7955 "(expected %i, found %i)\n", enabled
, crtc
->base
.enabled
);
7957 memset(&pipe_config
, 0, sizeof(pipe_config
));
7958 active
= dev_priv
->display
.get_pipe_config(crtc
,
7960 WARN(crtc
->active
!= active
,
7961 "crtc active state doesn't match with hw state "
7962 "(expected %i, found %i)\n", crtc
->active
, active
);
7965 !intel_pipe_config_compare(&crtc
->config
, &pipe_config
),
7966 "pipe state doesn't match!\n");
7970 static int __intel_set_mode(struct drm_crtc
*crtc
,
7971 struct drm_display_mode
*mode
,
7972 int x
, int y
, struct drm_framebuffer
*fb
)
7974 struct drm_device
*dev
= crtc
->dev
;
7975 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7976 struct drm_display_mode
*saved_mode
, *saved_hwmode
;
7977 struct intel_crtc_config
*pipe_config
= NULL
;
7978 struct intel_crtc
*intel_crtc
;
7979 unsigned disable_pipes
, prepare_pipes
, modeset_pipes
;
7982 saved_mode
= kmalloc(2 * sizeof(*saved_mode
), GFP_KERNEL
);
7985 saved_hwmode
= saved_mode
+ 1;
7987 intel_modeset_affected_pipes(crtc
, &modeset_pipes
,
7988 &prepare_pipes
, &disable_pipes
);
7990 *saved_hwmode
= crtc
->hwmode
;
7991 *saved_mode
= crtc
->mode
;
7993 /* Hack: Because we don't (yet) support global modeset on multiple
7994 * crtcs, we don't keep track of the new mode for more than one crtc.
7995 * Hence simply check whether any bit is set in modeset_pipes in all the
7996 * pieces of code that are not yet converted to deal with mutliple crtcs
7997 * changing their mode at the same time. */
7998 if (modeset_pipes
) {
7999 pipe_config
= intel_modeset_pipe_config(crtc
, fb
, mode
);
8000 if (IS_ERR(pipe_config
)) {
8001 ret
= PTR_ERR(pipe_config
);
8008 for_each_intel_crtc_masked(dev
, disable_pipes
, intel_crtc
)
8009 intel_crtc_disable(&intel_crtc
->base
);
8011 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
8012 if (intel_crtc
->base
.enabled
)
8013 dev_priv
->display
.crtc_disable(&intel_crtc
->base
);
8016 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8017 * to set it here already despite that we pass it down the callchain.
8019 if (modeset_pipes
) {
8020 enum transcoder tmp
= to_intel_crtc(crtc
)->config
.cpu_transcoder
;
8022 /* mode_set/enable/disable functions rely on a correct pipe
8024 to_intel_crtc(crtc
)->config
= *pipe_config
;
8025 to_intel_crtc(crtc
)->config
.cpu_transcoder
= tmp
;
8028 /* Only after disabling all output pipelines that will be changed can we
8029 * update the the output configuration. */
8030 intel_modeset_update_state(dev
, prepare_pipes
);
8032 if (dev_priv
->display
.modeset_global_resources
)
8033 dev_priv
->display
.modeset_global_resources(dev
);
8035 /* Set up the DPLL and any encoders state that needs to adjust or depend
8038 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
8039 ret
= intel_crtc_mode_set(&intel_crtc
->base
,
8045 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8046 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
)
8047 dev_priv
->display
.crtc_enable(&intel_crtc
->base
);
8049 if (modeset_pipes
) {
8050 /* Store real post-adjustment hardware mode. */
8051 crtc
->hwmode
= pipe_config
->adjusted_mode
;
8053 /* Calculate and store various constants which
8054 * are later needed by vblank and swap-completion
8055 * timestamping. They are derived from true hwmode.
8057 drm_calc_timestamping_constants(crtc
);
8060 /* FIXME: add subpixel order */
8062 if (ret
&& crtc
->enabled
) {
8063 crtc
->hwmode
= *saved_hwmode
;
8064 crtc
->mode
= *saved_mode
;
8073 int intel_set_mode(struct drm_crtc
*crtc
,
8074 struct drm_display_mode
*mode
,
8075 int x
, int y
, struct drm_framebuffer
*fb
)
8079 ret
= __intel_set_mode(crtc
, mode
, x
, y
, fb
);
8082 intel_modeset_check_state(crtc
->dev
);
8087 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
8089 intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
, crtc
->fb
);
8092 #undef for_each_intel_crtc_masked
8094 static void intel_set_config_free(struct intel_set_config
*config
)
8099 kfree(config
->save_connector_encoders
);
8100 kfree(config
->save_encoder_crtcs
);
8104 static int intel_set_config_save_state(struct drm_device
*dev
,
8105 struct intel_set_config
*config
)
8107 struct drm_encoder
*encoder
;
8108 struct drm_connector
*connector
;
8111 config
->save_encoder_crtcs
=
8112 kcalloc(dev
->mode_config
.num_encoder
,
8113 sizeof(struct drm_crtc
*), GFP_KERNEL
);
8114 if (!config
->save_encoder_crtcs
)
8117 config
->save_connector_encoders
=
8118 kcalloc(dev
->mode_config
.num_connector
,
8119 sizeof(struct drm_encoder
*), GFP_KERNEL
);
8120 if (!config
->save_connector_encoders
)
8123 /* Copy data. Note that driver private data is not affected.
8124 * Should anything bad happen only the expected state is
8125 * restored, not the drivers personal bookkeeping.
8128 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
8129 config
->save_encoder_crtcs
[count
++] = encoder
->crtc
;
8133 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
8134 config
->save_connector_encoders
[count
++] = connector
->encoder
;
8140 static void intel_set_config_restore_state(struct drm_device
*dev
,
8141 struct intel_set_config
*config
)
8143 struct intel_encoder
*encoder
;
8144 struct intel_connector
*connector
;
8148 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
8150 to_intel_crtc(config
->save_encoder_crtcs
[count
++]);
8154 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
8155 connector
->new_encoder
=
8156 to_intel_encoder(config
->save_connector_encoders
[count
++]);
8161 intel_set_config_compute_mode_changes(struct drm_mode_set
*set
,
8162 struct intel_set_config
*config
)
8165 /* We should be able to check here if the fb has the same properties
8166 * and then just flip_or_move it */
8167 if (set
->crtc
->fb
!= set
->fb
) {
8168 /* If we have no fb then treat it as a full mode set */
8169 if (set
->crtc
->fb
== NULL
) {
8170 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8171 config
->mode_changed
= true;
8172 } else if (set
->fb
== NULL
) {
8173 config
->mode_changed
= true;
8174 } else if (set
->fb
->pixel_format
!=
8175 set
->crtc
->fb
->pixel_format
) {
8176 config
->mode_changed
= true;
8178 config
->fb_changed
= true;
8181 if (set
->fb
&& (set
->x
!= set
->crtc
->x
|| set
->y
!= set
->crtc
->y
))
8182 config
->fb_changed
= true;
8184 if (set
->mode
&& !drm_mode_equal(set
->mode
, &set
->crtc
->mode
)) {
8185 DRM_DEBUG_KMS("modes are different, full mode set\n");
8186 drm_mode_debug_printmodeline(&set
->crtc
->mode
);
8187 drm_mode_debug_printmodeline(set
->mode
);
8188 config
->mode_changed
= true;
8193 intel_modeset_stage_output_state(struct drm_device
*dev
,
8194 struct drm_mode_set
*set
,
8195 struct intel_set_config
*config
)
8197 struct drm_crtc
*new_crtc
;
8198 struct intel_connector
*connector
;
8199 struct intel_encoder
*encoder
;
8202 /* The upper layers ensure that we either disable a crtc or have a list
8203 * of connectors. For paranoia, double-check this. */
8204 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
8205 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
8208 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8210 /* Otherwise traverse passed in connector list and get encoders
8212 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
8213 if (set
->connectors
[ro
] == &connector
->base
) {
8214 connector
->new_encoder
= connector
->encoder
;
8219 /* If we disable the crtc, disable all its connectors. Also, if
8220 * the connector is on the changing crtc but not on the new
8221 * connector list, disable it. */
8222 if ((!set
->fb
|| ro
== set
->num_connectors
) &&
8223 connector
->base
.encoder
&&
8224 connector
->base
.encoder
->crtc
== set
->crtc
) {
8225 connector
->new_encoder
= NULL
;
8227 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8228 connector
->base
.base
.id
,
8229 drm_get_connector_name(&connector
->base
));
8233 if (&connector
->new_encoder
->base
!= connector
->base
.encoder
) {
8234 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8235 config
->mode_changed
= true;
8238 /* connector->new_encoder is now updated for all connectors. */
8240 /* Update crtc of enabled connectors. */
8242 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8244 if (!connector
->new_encoder
)
8247 new_crtc
= connector
->new_encoder
->base
.crtc
;
8249 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
8250 if (set
->connectors
[ro
] == &connector
->base
)
8251 new_crtc
= set
->crtc
;
8254 /* Make sure the new CRTC will work with the encoder */
8255 if (!intel_encoder_crtc_ok(&connector
->new_encoder
->base
,
8259 connector
->encoder
->new_crtc
= to_intel_crtc(new_crtc
);
8261 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8262 connector
->base
.base
.id
,
8263 drm_get_connector_name(&connector
->base
),
8267 /* Check for any encoders that needs to be disabled. */
8268 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8270 list_for_each_entry(connector
,
8271 &dev
->mode_config
.connector_list
,
8273 if (connector
->new_encoder
== encoder
) {
8274 WARN_ON(!connector
->new_encoder
->new_crtc
);
8279 encoder
->new_crtc
= NULL
;
8281 /* Only now check for crtc changes so we don't miss encoders
8282 * that will be disabled. */
8283 if (&encoder
->new_crtc
->base
!= encoder
->base
.crtc
) {
8284 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8285 config
->mode_changed
= true;
8288 /* Now we've also updated encoder->new_crtc for all encoders. */
8293 static int intel_crtc_set_config(struct drm_mode_set
*set
)
8295 struct drm_device
*dev
;
8296 struct drm_mode_set save_set
;
8297 struct intel_set_config
*config
;
8302 BUG_ON(!set
->crtc
->helper_private
);
8304 /* Enforce sane interface api - has been abused by the fb helper. */
8305 BUG_ON(!set
->mode
&& set
->fb
);
8306 BUG_ON(set
->fb
&& set
->num_connectors
== 0);
8309 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8310 set
->crtc
->base
.id
, set
->fb
->base
.id
,
8311 (int)set
->num_connectors
, set
->x
, set
->y
);
8313 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
8316 dev
= set
->crtc
->dev
;
8319 config
= kzalloc(sizeof(*config
), GFP_KERNEL
);
8323 ret
= intel_set_config_save_state(dev
, config
);
8327 save_set
.crtc
= set
->crtc
;
8328 save_set
.mode
= &set
->crtc
->mode
;
8329 save_set
.x
= set
->crtc
->x
;
8330 save_set
.y
= set
->crtc
->y
;
8331 save_set
.fb
= set
->crtc
->fb
;
8333 /* Compute whether we need a full modeset, only an fb base update or no
8334 * change at all. In the future we might also check whether only the
8335 * mode changed, e.g. for LVDS where we only change the panel fitter in
8337 intel_set_config_compute_mode_changes(set
, config
);
8339 ret
= intel_modeset_stage_output_state(dev
, set
, config
);
8343 if (config
->mode_changed
) {
8345 DRM_DEBUG_KMS("attempting to set mode from"
8347 drm_mode_debug_printmodeline(set
->mode
);
8350 ret
= intel_set_mode(set
->crtc
, set
->mode
,
8351 set
->x
, set
->y
, set
->fb
);
8353 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8354 set
->crtc
->base
.id
, ret
);
8357 } else if (config
->fb_changed
) {
8358 intel_crtc_wait_for_pending_flips(set
->crtc
);
8360 ret
= intel_pipe_set_base(set
->crtc
,
8361 set
->x
, set
->y
, set
->fb
);
8364 intel_set_config_free(config
);
8369 intel_set_config_restore_state(dev
, config
);
8371 /* Try to restore the config */
8372 if (config
->mode_changed
&&
8373 intel_set_mode(save_set
.crtc
, save_set
.mode
,
8374 save_set
.x
, save_set
.y
, save_set
.fb
))
8375 DRM_ERROR("failed to restore config after modeset failure\n");
8378 intel_set_config_free(config
);
8382 static const struct drm_crtc_funcs intel_crtc_funcs
= {
8383 .cursor_set
= intel_crtc_cursor_set
,
8384 .cursor_move
= intel_crtc_cursor_move
,
8385 .gamma_set
= intel_crtc_gamma_set
,
8386 .set_config
= intel_crtc_set_config
,
8387 .destroy
= intel_crtc_destroy
,
8388 .page_flip
= intel_crtc_page_flip
,
8391 static void intel_cpu_pll_init(struct drm_device
*dev
)
8394 intel_ddi_pll_init(dev
);
8397 static void intel_pch_pll_init(struct drm_device
*dev
)
8399 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8402 if (dev_priv
->num_pch_pll
== 0) {
8403 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8407 for (i
= 0; i
< dev_priv
->num_pch_pll
; i
++) {
8408 dev_priv
->pch_plls
[i
].pll_reg
= _PCH_DPLL(i
);
8409 dev_priv
->pch_plls
[i
].fp0_reg
= _PCH_FP0(i
);
8410 dev_priv
->pch_plls
[i
].fp1_reg
= _PCH_FP1(i
);
8414 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
8416 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8417 struct intel_crtc
*intel_crtc
;
8420 intel_crtc
= kzalloc(sizeof(struct intel_crtc
) + (INTELFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
8421 if (intel_crtc
== NULL
)
8424 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
8426 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
8427 for (i
= 0; i
< 256; i
++) {
8428 intel_crtc
->lut_r
[i
] = i
;
8429 intel_crtc
->lut_g
[i
] = i
;
8430 intel_crtc
->lut_b
[i
] = i
;
8433 /* Swap pipes & planes for FBC on pre-965 */
8434 intel_crtc
->pipe
= pipe
;
8435 intel_crtc
->plane
= pipe
;
8436 intel_crtc
->config
.cpu_transcoder
= pipe
;
8437 if (IS_MOBILE(dev
) && IS_GEN3(dev
)) {
8438 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8439 intel_crtc
->plane
= !pipe
;
8442 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
8443 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
8444 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
8445 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
8447 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
8450 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
8451 struct drm_file
*file
)
8453 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
8454 struct drm_mode_object
*drmmode_obj
;
8455 struct intel_crtc
*crtc
;
8457 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
8460 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
8461 DRM_MODE_OBJECT_CRTC
);
8464 DRM_ERROR("no such CRTC id\n");
8468 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
8469 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
8474 static int intel_encoder_clones(struct intel_encoder
*encoder
)
8476 struct drm_device
*dev
= encoder
->base
.dev
;
8477 struct intel_encoder
*source_encoder
;
8481 list_for_each_entry(source_encoder
,
8482 &dev
->mode_config
.encoder_list
, base
.head
) {
8484 if (encoder
== source_encoder
)
8485 index_mask
|= (1 << entry
);
8487 /* Intel hw has only one MUX where enocoders could be cloned. */
8488 if (encoder
->cloneable
&& source_encoder
->cloneable
)
8489 index_mask
|= (1 << entry
);
8497 static bool has_edp_a(struct drm_device
*dev
)
8499 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8501 if (!IS_MOBILE(dev
))
8504 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
8508 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES
) & ILK_eDP_A_DISABLE
))
8514 static void intel_setup_outputs(struct drm_device
*dev
)
8516 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8517 struct intel_encoder
*encoder
;
8518 bool dpd_is_edp
= false;
8521 has_lvds
= intel_lvds_init(dev
);
8522 if (!has_lvds
&& !HAS_PCH_SPLIT(dev
)) {
8523 /* disable the panel fitter on everything but LVDS */
8524 I915_WRITE(PFIT_CONTROL
, 0);
8528 intel_crt_init(dev
);
8533 /* Haswell uses DDI functions to detect digital outputs */
8534 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
8535 /* DDI A only supports eDP */
8537 intel_ddi_init(dev
, PORT_A
);
8539 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8541 found
= I915_READ(SFUSE_STRAP
);
8543 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
8544 intel_ddi_init(dev
, PORT_B
);
8545 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
8546 intel_ddi_init(dev
, PORT_C
);
8547 if (found
& SFUSE_STRAP_DDID_DETECTED
)
8548 intel_ddi_init(dev
, PORT_D
);
8549 } else if (HAS_PCH_SPLIT(dev
)) {
8551 dpd_is_edp
= intel_dpd_is_edp(dev
);
8554 intel_dp_init(dev
, DP_A
, PORT_A
);
8556 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
8557 /* PCH SDVOB multiplex with HDMIB */
8558 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
8560 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
8561 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
8562 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
8565 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
8566 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
8568 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
8569 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
8571 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
8572 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
8574 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
8575 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
8576 } else if (IS_VALLEYVIEW(dev
)) {
8577 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8578 if (I915_READ(VLV_DISPLAY_BASE
+ DP_C
) & DP_DETECTED
)
8579 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_C
, PORT_C
);
8581 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIB
) & SDVO_DETECTED
) {
8582 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIB
,
8584 if (I915_READ(VLV_DISPLAY_BASE
+ DP_B
) & DP_DETECTED
)
8585 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_B
, PORT_B
);
8587 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
8590 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
8591 DRM_DEBUG_KMS("probing SDVOB\n");
8592 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, true);
8593 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
8594 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8595 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
8598 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
)) {
8599 DRM_DEBUG_KMS("probing DP_B\n");
8600 intel_dp_init(dev
, DP_B
, PORT_B
);
8604 /* Before G4X SDVOC doesn't have its own detect register */
8606 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
8607 DRM_DEBUG_KMS("probing SDVOC\n");
8608 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, false);
8611 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
8613 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
8614 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8615 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
8617 if (SUPPORTS_INTEGRATED_DP(dev
)) {
8618 DRM_DEBUG_KMS("probing DP_C\n");
8619 intel_dp_init(dev
, DP_C
, PORT_C
);
8623 if (SUPPORTS_INTEGRATED_DP(dev
) &&
8624 (I915_READ(DP_D
) & DP_DETECTED
)) {
8625 DRM_DEBUG_KMS("probing DP_D\n");
8626 intel_dp_init(dev
, DP_D
, PORT_D
);
8628 } else if (IS_GEN2(dev
))
8629 intel_dvo_init(dev
);
8631 if (SUPPORTS_TV(dev
))
8634 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
8635 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
8636 encoder
->base
.possible_clones
=
8637 intel_encoder_clones(encoder
);
8640 intel_init_pch_refclk(dev
);
8642 drm_helper_move_panel_connectors_to_head(dev
);
8645 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
8647 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
8649 drm_framebuffer_cleanup(fb
);
8650 drm_gem_object_unreference_unlocked(&intel_fb
->obj
->base
);
8655 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
8656 struct drm_file
*file
,
8657 unsigned int *handle
)
8659 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
8660 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
8662 return drm_gem_handle_create(file
, &obj
->base
, handle
);
8665 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
8666 .destroy
= intel_user_framebuffer_destroy
,
8667 .create_handle
= intel_user_framebuffer_create_handle
,
8670 int intel_framebuffer_init(struct drm_device
*dev
,
8671 struct intel_framebuffer
*intel_fb
,
8672 struct drm_mode_fb_cmd2
*mode_cmd
,
8673 struct drm_i915_gem_object
*obj
)
8677 if (obj
->tiling_mode
== I915_TILING_Y
) {
8678 DRM_DEBUG("hardware does not support tiling Y\n");
8682 if (mode_cmd
->pitches
[0] & 63) {
8683 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8684 mode_cmd
->pitches
[0]);
8688 /* FIXME <= Gen4 stride limits are bit unclear */
8689 if (mode_cmd
->pitches
[0] > 32768) {
8690 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8691 mode_cmd
->pitches
[0]);
8695 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
8696 mode_cmd
->pitches
[0] != obj
->stride
) {
8697 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8698 mode_cmd
->pitches
[0], obj
->stride
);
8702 /* Reject formats not supported by any plane early. */
8703 switch (mode_cmd
->pixel_format
) {
8705 case DRM_FORMAT_RGB565
:
8706 case DRM_FORMAT_XRGB8888
:
8707 case DRM_FORMAT_ARGB8888
:
8709 case DRM_FORMAT_XRGB1555
:
8710 case DRM_FORMAT_ARGB1555
:
8711 if (INTEL_INFO(dev
)->gen
> 3) {
8712 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd
->pixel_format
);
8716 case DRM_FORMAT_XBGR8888
:
8717 case DRM_FORMAT_ABGR8888
:
8718 case DRM_FORMAT_XRGB2101010
:
8719 case DRM_FORMAT_ARGB2101010
:
8720 case DRM_FORMAT_XBGR2101010
:
8721 case DRM_FORMAT_ABGR2101010
:
8722 if (INTEL_INFO(dev
)->gen
< 4) {
8723 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd
->pixel_format
);
8727 case DRM_FORMAT_YUYV
:
8728 case DRM_FORMAT_UYVY
:
8729 case DRM_FORMAT_YVYU
:
8730 case DRM_FORMAT_VYUY
:
8731 if (INTEL_INFO(dev
)->gen
< 5) {
8732 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd
->pixel_format
);
8737 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd
->pixel_format
);
8741 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8742 if (mode_cmd
->offsets
[0] != 0)
8745 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
8746 intel_fb
->obj
= obj
;
8748 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
8750 DRM_ERROR("framebuffer init failed %d\n", ret
);
8757 static struct drm_framebuffer
*
8758 intel_user_framebuffer_create(struct drm_device
*dev
,
8759 struct drm_file
*filp
,
8760 struct drm_mode_fb_cmd2
*mode_cmd
)
8762 struct drm_i915_gem_object
*obj
;
8764 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
8765 mode_cmd
->handles
[0]));
8766 if (&obj
->base
== NULL
)
8767 return ERR_PTR(-ENOENT
);
8769 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
8772 static const struct drm_mode_config_funcs intel_mode_funcs
= {
8773 .fb_create
= intel_user_framebuffer_create
,
8774 .output_poll_changed
= intel_fb_output_poll_changed
,
8777 /* Set up chip specific display functions */
8778 static void intel_init_display(struct drm_device
*dev
)
8780 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8783 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
8784 dev_priv
->display
.crtc_mode_set
= haswell_crtc_mode_set
;
8785 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
8786 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
8787 dev_priv
->display
.off
= haswell_crtc_off
;
8788 dev_priv
->display
.update_plane
= ironlake_update_plane
;
8789 } else if (HAS_PCH_SPLIT(dev
)) {
8790 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
8791 dev_priv
->display
.crtc_mode_set
= ironlake_crtc_mode_set
;
8792 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
8793 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
8794 dev_priv
->display
.off
= ironlake_crtc_off
;
8795 dev_priv
->display
.update_plane
= ironlake_update_plane
;
8796 } else if (IS_VALLEYVIEW(dev
)) {
8797 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
8798 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
8799 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
8800 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
8801 dev_priv
->display
.off
= i9xx_crtc_off
;
8802 dev_priv
->display
.update_plane
= i9xx_update_plane
;
8804 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
8805 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
8806 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
8807 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
8808 dev_priv
->display
.off
= i9xx_crtc_off
;
8809 dev_priv
->display
.update_plane
= i9xx_update_plane
;
8812 /* Returns the core display clock speed */
8813 if (IS_VALLEYVIEW(dev
))
8814 dev_priv
->display
.get_display_clock_speed
=
8815 valleyview_get_display_clock_speed
;
8816 else if (IS_I945G(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
8817 dev_priv
->display
.get_display_clock_speed
=
8818 i945_get_display_clock_speed
;
8819 else if (IS_I915G(dev
))
8820 dev_priv
->display
.get_display_clock_speed
=
8821 i915_get_display_clock_speed
;
8822 else if (IS_I945GM(dev
) || IS_845G(dev
) || IS_PINEVIEW_M(dev
))
8823 dev_priv
->display
.get_display_clock_speed
=
8824 i9xx_misc_get_display_clock_speed
;
8825 else if (IS_I915GM(dev
))
8826 dev_priv
->display
.get_display_clock_speed
=
8827 i915gm_get_display_clock_speed
;
8828 else if (IS_I865G(dev
))
8829 dev_priv
->display
.get_display_clock_speed
=
8830 i865_get_display_clock_speed
;
8831 else if (IS_I85X(dev
))
8832 dev_priv
->display
.get_display_clock_speed
=
8833 i855_get_display_clock_speed
;
8835 dev_priv
->display
.get_display_clock_speed
=
8836 i830_get_display_clock_speed
;
8838 if (HAS_PCH_SPLIT(dev
)) {
8840 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
8841 dev_priv
->display
.write_eld
= ironlake_write_eld
;
8842 } else if (IS_GEN6(dev
)) {
8843 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
8844 dev_priv
->display
.write_eld
= ironlake_write_eld
;
8845 } else if (IS_IVYBRIDGE(dev
)) {
8846 /* FIXME: detect B0+ stepping and use auto training */
8847 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
8848 dev_priv
->display
.write_eld
= ironlake_write_eld
;
8849 dev_priv
->display
.modeset_global_resources
=
8850 ivb_modeset_global_resources
;
8851 } else if (IS_HASWELL(dev
)) {
8852 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
8853 dev_priv
->display
.write_eld
= haswell_write_eld
;
8854 dev_priv
->display
.modeset_global_resources
=
8855 haswell_modeset_global_resources
;
8857 } else if (IS_G4X(dev
)) {
8858 dev_priv
->display
.write_eld
= g4x_write_eld
;
8861 /* Default just returns -ENODEV to indicate unsupported */
8862 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
8864 switch (INTEL_INFO(dev
)->gen
) {
8866 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
8870 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
8875 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
8879 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
8882 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
8888 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8889 * resume, or other times. This quirk makes sure that's the case for
8892 static void quirk_pipea_force(struct drm_device
*dev
)
8894 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8896 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
8897 DRM_INFO("applying pipe a force quirk\n");
8901 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8903 static void quirk_ssc_force_disable(struct drm_device
*dev
)
8905 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8906 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
8907 DRM_INFO("applying lvds SSC disable quirk\n");
8911 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8914 static void quirk_invert_brightness(struct drm_device
*dev
)
8916 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8917 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
8918 DRM_INFO("applying inverted panel brightness quirk\n");
8921 struct intel_quirk
{
8923 int subsystem_vendor
;
8924 int subsystem_device
;
8925 void (*hook
)(struct drm_device
*dev
);
8928 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8929 struct intel_dmi_quirk
{
8930 void (*hook
)(struct drm_device
*dev
);
8931 const struct dmi_system_id (*dmi_id_list
)[];
8934 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
8936 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
8940 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
8942 .dmi_id_list
= &(const struct dmi_system_id
[]) {
8944 .callback
= intel_dmi_reverse_brightness
,
8945 .ident
= "NCR Corporation",
8946 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
8947 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
8950 { } /* terminating entry */
8952 .hook
= quirk_invert_brightness
,
8956 static struct intel_quirk intel_quirks
[] = {
8957 /* HP Mini needs pipe A force quirk (LP: #322104) */
8958 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
8960 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8961 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
8963 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8964 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
8966 /* 830/845 need to leave pipe A & dpll A up */
8967 { 0x2562, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
8968 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
8970 /* Lenovo U160 cannot use SSC on LVDS */
8971 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
8973 /* Sony Vaio Y cannot use SSC on LVDS */
8974 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
8976 /* Acer Aspire 5734Z must invert backlight brightness */
8977 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
8979 /* Acer/eMachines G725 */
8980 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
8982 /* Acer/eMachines e725 */
8983 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
8985 /* Acer/Packard Bell NCL20 */
8986 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
8988 /* Acer Aspire 4736Z */
8989 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
8992 static void intel_init_quirks(struct drm_device
*dev
)
8994 struct pci_dev
*d
= dev
->pdev
;
8997 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
8998 struct intel_quirk
*q
= &intel_quirks
[i
];
9000 if (d
->device
== q
->device
&&
9001 (d
->subsystem_vendor
== q
->subsystem_vendor
||
9002 q
->subsystem_vendor
== PCI_ANY_ID
) &&
9003 (d
->subsystem_device
== q
->subsystem_device
||
9004 q
->subsystem_device
== PCI_ANY_ID
))
9007 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
9008 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
9009 intel_dmi_quirks
[i
].hook(dev
);
9013 /* Disable the VGA plane that we never use */
9014 static void i915_disable_vga(struct drm_device
*dev
)
9016 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9018 u32 vga_reg
= i915_vgacntrl_reg(dev
);
9020 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
9021 outb(SR01
, VGA_SR_INDEX
);
9022 sr1
= inb(VGA_SR_DATA
);
9023 outb(sr1
| 1<<5, VGA_SR_DATA
);
9024 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
9027 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
9028 POSTING_READ(vga_reg
);
9031 void intel_modeset_init_hw(struct drm_device
*dev
)
9033 intel_init_power_well(dev
);
9035 intel_prepare_ddi(dev
);
9037 intel_init_clock_gating(dev
);
9039 mutex_lock(&dev
->struct_mutex
);
9040 intel_enable_gt_powersave(dev
);
9041 mutex_unlock(&dev
->struct_mutex
);
9044 void intel_modeset_init(struct drm_device
*dev
)
9046 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9049 drm_mode_config_init(dev
);
9051 dev
->mode_config
.min_width
= 0;
9052 dev
->mode_config
.min_height
= 0;
9054 dev
->mode_config
.preferred_depth
= 24;
9055 dev
->mode_config
.prefer_shadow
= 1;
9057 dev
->mode_config
.funcs
= &intel_mode_funcs
;
9059 intel_init_quirks(dev
);
9063 if (INTEL_INFO(dev
)->num_pipes
== 0)
9066 intel_init_display(dev
);
9069 dev
->mode_config
.max_width
= 2048;
9070 dev
->mode_config
.max_height
= 2048;
9071 } else if (IS_GEN3(dev
)) {
9072 dev
->mode_config
.max_width
= 4096;
9073 dev
->mode_config
.max_height
= 4096;
9075 dev
->mode_config
.max_width
= 8192;
9076 dev
->mode_config
.max_height
= 8192;
9078 dev
->mode_config
.fb_base
= dev_priv
->gtt
.mappable_base
;
9080 DRM_DEBUG_KMS("%d display pipe%s available.\n",
9081 INTEL_INFO(dev
)->num_pipes
,
9082 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
9084 for (i
= 0; i
< INTEL_INFO(dev
)->num_pipes
; i
++) {
9085 intel_crtc_init(dev
, i
);
9086 for (j
= 0; j
< dev_priv
->num_plane
; j
++) {
9087 ret
= intel_plane_init(dev
, i
, j
);
9089 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9090 pipe_name(i
), sprite_name(i
, j
), ret
);
9094 intel_cpu_pll_init(dev
);
9095 intel_pch_pll_init(dev
);
9097 /* Just disable it once at startup */
9098 i915_disable_vga(dev
);
9099 intel_setup_outputs(dev
);
9101 /* Just in case the BIOS is doing something questionable. */
9102 intel_disable_fbc(dev
);
9106 intel_connector_break_all_links(struct intel_connector
*connector
)
9108 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
9109 connector
->base
.encoder
= NULL
;
9110 connector
->encoder
->connectors_active
= false;
9111 connector
->encoder
->base
.crtc
= NULL
;
9114 static void intel_enable_pipe_a(struct drm_device
*dev
)
9116 struct intel_connector
*connector
;
9117 struct drm_connector
*crt
= NULL
;
9118 struct intel_load_detect_pipe load_detect_temp
;
9120 /* We can't just switch on the pipe A, we need to set things up with a
9121 * proper mode and output configuration. As a gross hack, enable pipe A
9122 * by enabling the load detect pipe once. */
9123 list_for_each_entry(connector
,
9124 &dev
->mode_config
.connector_list
,
9126 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
9127 crt
= &connector
->base
;
9135 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
))
9136 intel_release_load_detect_pipe(crt
, &load_detect_temp
);
9142 intel_check_plane_mapping(struct intel_crtc
*crtc
)
9144 struct drm_device
*dev
= crtc
->base
.dev
;
9145 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9148 if (INTEL_INFO(dev
)->num_pipes
== 1)
9151 reg
= DSPCNTR(!crtc
->plane
);
9152 val
= I915_READ(reg
);
9154 if ((val
& DISPLAY_PLANE_ENABLE
) &&
9155 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
9161 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
9163 struct drm_device
*dev
= crtc
->base
.dev
;
9164 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9167 /* Clear any frame start delays used for debugging left by the BIOS */
9168 reg
= PIPECONF(crtc
->config
.cpu_transcoder
);
9169 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
9171 /* We need to sanitize the plane -> pipe mapping first because this will
9172 * disable the crtc (and hence change the state) if it is wrong. Note
9173 * that gen4+ has a fixed plane -> pipe mapping. */
9174 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
9175 struct intel_connector
*connector
;
9178 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9179 crtc
->base
.base
.id
);
9181 /* Pipe has the wrong plane attached and the plane is active.
9182 * Temporarily change the plane mapping and disable everything
9184 plane
= crtc
->plane
;
9185 crtc
->plane
= !plane
;
9186 dev_priv
->display
.crtc_disable(&crtc
->base
);
9187 crtc
->plane
= plane
;
9189 /* ... and break all links. */
9190 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9192 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
9195 intel_connector_break_all_links(connector
);
9198 WARN_ON(crtc
->active
);
9199 crtc
->base
.enabled
= false;
9202 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
9203 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
9204 /* BIOS forgot to enable pipe A, this mostly happens after
9205 * resume. Force-enable the pipe to fix this, the update_dpms
9206 * call below we restore the pipe to the right state, but leave
9207 * the required bits on. */
9208 intel_enable_pipe_a(dev
);
9211 /* Adjust the state of the output pipe according to whether we
9212 * have active connectors/encoders. */
9213 intel_crtc_update_dpms(&crtc
->base
);
9215 if (crtc
->active
!= crtc
->base
.enabled
) {
9216 struct intel_encoder
*encoder
;
9218 /* This can happen either due to bugs in the get_hw_state
9219 * functions or because the pipe is force-enabled due to the
9221 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9223 crtc
->base
.enabled
? "enabled" : "disabled",
9224 crtc
->active
? "enabled" : "disabled");
9226 crtc
->base
.enabled
= crtc
->active
;
9228 /* Because we only establish the connector -> encoder ->
9229 * crtc links if something is active, this means the
9230 * crtc is now deactivated. Break the links. connector
9231 * -> encoder links are only establish when things are
9232 * actually up, hence no need to break them. */
9233 WARN_ON(crtc
->active
);
9235 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
9236 WARN_ON(encoder
->connectors_active
);
9237 encoder
->base
.crtc
= NULL
;
9242 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
9244 struct intel_connector
*connector
;
9245 struct drm_device
*dev
= encoder
->base
.dev
;
9247 /* We need to check both for a crtc link (meaning that the
9248 * encoder is active and trying to read from a pipe) and the
9249 * pipe itself being active. */
9250 bool has_active_crtc
= encoder
->base
.crtc
&&
9251 to_intel_crtc(encoder
->base
.crtc
)->active
;
9253 if (encoder
->connectors_active
&& !has_active_crtc
) {
9254 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9255 encoder
->base
.base
.id
,
9256 drm_get_encoder_name(&encoder
->base
));
9258 /* Connector is active, but has no active pipe. This is
9259 * fallout from our resume register restoring. Disable
9260 * the encoder manually again. */
9261 if (encoder
->base
.crtc
) {
9262 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9263 encoder
->base
.base
.id
,
9264 drm_get_encoder_name(&encoder
->base
));
9265 encoder
->disable(encoder
);
9268 /* Inconsistent output/port/pipe state happens presumably due to
9269 * a bug in one of the get_hw_state functions. Or someplace else
9270 * in our code, like the register restore mess on resume. Clamp
9271 * things to off as a safer default. */
9272 list_for_each_entry(connector
,
9273 &dev
->mode_config
.connector_list
,
9275 if (connector
->encoder
!= encoder
)
9278 intel_connector_break_all_links(connector
);
9281 /* Enabled encoders without active connectors will be fixed in
9282 * the crtc fixup. */
9285 void i915_redisable_vga(struct drm_device
*dev
)
9287 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9288 u32 vga_reg
= i915_vgacntrl_reg(dev
);
9290 if (I915_READ(vga_reg
) != VGA_DISP_DISABLE
) {
9291 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9292 i915_disable_vga(dev
);
9296 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9297 * and i915 state tracking structures. */
9298 void intel_modeset_setup_hw_state(struct drm_device
*dev
,
9301 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9304 struct drm_plane
*plane
;
9305 struct intel_crtc
*crtc
;
9306 struct intel_encoder
*encoder
;
9307 struct intel_connector
*connector
;
9310 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
9312 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
9313 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
9314 case TRANS_DDI_EDP_INPUT_A_ON
:
9315 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
9318 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
9321 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
9325 /* A bogus value has been programmed, disable
9327 WARN(1, "Bogus eDP source %08x\n", tmp
);
9328 intel_ddi_disable_transcoder_func(dev_priv
,
9333 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
9334 crtc
->config
.cpu_transcoder
= TRANSCODER_EDP
;
9336 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9342 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
9344 enum transcoder tmp
= crtc
->config
.cpu_transcoder
;
9345 memset(&crtc
->config
, 0, sizeof(crtc
->config
));
9346 crtc
->config
.cpu_transcoder
= tmp
;
9348 crtc
->active
= dev_priv
->display
.get_pipe_config(crtc
,
9351 crtc
->base
.enabled
= crtc
->active
;
9353 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9355 crtc
->active
? "enabled" : "disabled");
9359 intel_ddi_setup_hw_pll_state(dev
);
9361 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9365 if (encoder
->get_hw_state(encoder
, &pipe
)) {
9366 encoder
->base
.crtc
=
9367 dev_priv
->pipe_to_crtc_mapping
[pipe
];
9369 encoder
->base
.crtc
= NULL
;
9372 encoder
->connectors_active
= false;
9373 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9374 encoder
->base
.base
.id
,
9375 drm_get_encoder_name(&encoder
->base
),
9376 encoder
->base
.crtc
? "enabled" : "disabled",
9380 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9382 if (connector
->get_hw_state(connector
)) {
9383 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
9384 connector
->encoder
->connectors_active
= true;
9385 connector
->base
.encoder
= &connector
->encoder
->base
;
9387 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
9388 connector
->base
.encoder
= NULL
;
9390 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9391 connector
->base
.base
.id
,
9392 drm_get_connector_name(&connector
->base
),
9393 connector
->base
.encoder
? "enabled" : "disabled");
9396 /* HW state is read out, now we need to sanitize this mess. */
9397 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9399 intel_sanitize_encoder(encoder
);
9402 for_each_pipe(pipe
) {
9403 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
9404 intel_sanitize_crtc(crtc
);
9407 if (force_restore
) {
9409 * We need to use raw interfaces for restoring state to avoid
9410 * checking (bogus) intermediate states.
9412 for_each_pipe(pipe
) {
9413 struct drm_crtc
*crtc
=
9414 dev_priv
->pipe_to_crtc_mapping
[pipe
];
9416 __intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
,
9419 list_for_each_entry(plane
, &dev
->mode_config
.plane_list
, head
)
9420 intel_plane_restore(plane
);
9422 i915_redisable_vga(dev
);
9424 intel_modeset_update_staged_output_state(dev
);
9427 intel_modeset_check_state(dev
);
9429 drm_mode_config_reset(dev
);
9432 void intel_modeset_gem_init(struct drm_device
*dev
)
9434 intel_modeset_init_hw(dev
);
9436 intel_setup_overlay(dev
);
9438 intel_modeset_setup_hw_state(dev
, false);
9441 void intel_modeset_cleanup(struct drm_device
*dev
)
9443 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9444 struct drm_crtc
*crtc
;
9445 struct intel_crtc
*intel_crtc
;
9448 * Interrupts and polling as the first thing to avoid creating havoc.
9449 * Too much stuff here (turning of rps, connectors, ...) would
9450 * experience fancy races otherwise.
9452 drm_irq_uninstall(dev
);
9453 cancel_work_sync(&dev_priv
->hotplug_work
);
9455 * Due to the hpd irq storm handling the hotplug work can re-arm the
9456 * poll handlers. Hence disable polling after hpd handling is shut down.
9458 drm_kms_helper_poll_fini(dev
);
9460 mutex_lock(&dev
->struct_mutex
);
9462 intel_unregister_dsm_handler();
9464 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
9465 /* Skip inactive CRTCs */
9469 intel_crtc
= to_intel_crtc(crtc
);
9470 intel_increase_pllclock(crtc
);
9473 intel_disable_fbc(dev
);
9475 intel_disable_gt_powersave(dev
);
9477 ironlake_teardown_rc6(dev
);
9479 mutex_unlock(&dev
->struct_mutex
);
9481 /* flush any delayed tasks or pending work */
9482 flush_scheduled_work();
9484 /* destroy backlight, if any, before the connectors */
9485 intel_panel_destroy_backlight(dev
);
9487 drm_mode_config_cleanup(dev
);
9489 intel_cleanup_overlay(dev
);
9493 * Return which encoder is currently attached for connector.
9495 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
9497 return &intel_attached_encoder(connector
)->base
;
9500 void intel_connector_attach_encoder(struct intel_connector
*connector
,
9501 struct intel_encoder
*encoder
)
9503 connector
->encoder
= encoder
;
9504 drm_mode_connector_attach_encoder(&connector
->base
,
9509 * set vga decode state - true == enable VGA decode
9511 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
9513 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9516 pci_read_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, &gmch_ctrl
);
9518 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
9520 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
9521 pci_write_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, gmch_ctrl
);
9525 #ifdef CONFIG_DEBUG_FS
9526 #include <linux/seq_file.h>
9528 struct intel_display_error_state
{
9529 struct intel_cursor_error_state
{
9534 } cursor
[I915_MAX_PIPES
];
9536 struct intel_pipe_error_state
{
9546 } pipe
[I915_MAX_PIPES
];
9548 struct intel_plane_error_state
{
9556 } plane
[I915_MAX_PIPES
];
9559 struct intel_display_error_state
*
9560 intel_display_capture_error_state(struct drm_device
*dev
)
9562 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
9563 struct intel_display_error_state
*error
;
9564 enum transcoder cpu_transcoder
;
9567 error
= kmalloc(sizeof(*error
), GFP_ATOMIC
);
9572 cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
, i
);
9574 if (INTEL_INFO(dev
)->gen
<= 6 || IS_VALLEYVIEW(dev
)) {
9575 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
9576 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
9577 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
9579 error
->cursor
[i
].control
= I915_READ(CURCNTR_IVB(i
));
9580 error
->cursor
[i
].position
= I915_READ(CURPOS_IVB(i
));
9581 error
->cursor
[i
].base
= I915_READ(CURBASE_IVB(i
));
9584 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
9585 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
9586 if (INTEL_INFO(dev
)->gen
<= 3) {
9587 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
9588 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
9590 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
9591 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
9592 if (INTEL_INFO(dev
)->gen
>= 4) {
9593 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
9594 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
9597 error
->pipe
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
9598 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
9599 error
->pipe
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
9600 error
->pipe
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
9601 error
->pipe
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
9602 error
->pipe
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
9603 error
->pipe
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
9604 error
->pipe
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
9611 intel_display_print_error_state(struct seq_file
*m
,
9612 struct drm_device
*dev
,
9613 struct intel_display_error_state
*error
)
9617 seq_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
9619 seq_printf(m
, "Pipe [%d]:\n", i
);
9620 seq_printf(m
, " CONF: %08x\n", error
->pipe
[i
].conf
);
9621 seq_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
9622 seq_printf(m
, " HTOTAL: %08x\n", error
->pipe
[i
].htotal
);
9623 seq_printf(m
, " HBLANK: %08x\n", error
->pipe
[i
].hblank
);
9624 seq_printf(m
, " HSYNC: %08x\n", error
->pipe
[i
].hsync
);
9625 seq_printf(m
, " VTOTAL: %08x\n", error
->pipe
[i
].vtotal
);
9626 seq_printf(m
, " VBLANK: %08x\n", error
->pipe
[i
].vblank
);
9627 seq_printf(m
, " VSYNC: %08x\n", error
->pipe
[i
].vsync
);
9629 seq_printf(m
, "Plane [%d]:\n", i
);
9630 seq_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
9631 seq_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
9632 if (INTEL_INFO(dev
)->gen
<= 3) {
9633 seq_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
9634 seq_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
9636 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
9637 seq_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
9638 if (INTEL_INFO(dev
)->gen
>= 4) {
9639 seq_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
9640 seq_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
9643 seq_printf(m
, "Cursor [%d]:\n", i
);
9644 seq_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
9645 seq_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
9646 seq_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);