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drm/i915: Set M2_N2 registers during mode set
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_rect.h>
44 #include <linux/dma_remapping.h>
45
46 /* Primary plane formats supported by all gen */
47 #define COMMON_PRIMARY_FORMATS \
48 DRM_FORMAT_C8, \
49 DRM_FORMAT_RGB565, \
50 DRM_FORMAT_XRGB8888, \
51 DRM_FORMAT_ARGB8888
52
53 /* Primary plane formats for gen <= 3 */
54 static const uint32_t intel_primary_formats_gen2[] = {
55 COMMON_PRIMARY_FORMATS,
56 DRM_FORMAT_XRGB1555,
57 DRM_FORMAT_ARGB1555,
58 };
59
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t intel_primary_formats_gen4[] = {
62 COMMON_PRIMARY_FORMATS, \
63 DRM_FORMAT_XBGR8888,
64 DRM_FORMAT_ABGR8888,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_ARGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 DRM_FORMAT_ABGR2101010,
69 };
70
71 /* Cursor formats */
72 static const uint32_t intel_cursor_formats[] = {
73 DRM_FORMAT_ARGB8888,
74 };
75
76 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
77 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
78
79 static void intel_increase_pllclock(struct drm_device *dev,
80 enum pipe pipe);
81 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
82
83 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
84 struct intel_crtc_config *pipe_config);
85 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
86 struct intel_crtc_config *pipe_config);
87
88 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
89 int x, int y, struct drm_framebuffer *old_fb);
90 static int intel_framebuffer_init(struct drm_device *dev,
91 struct intel_framebuffer *ifb,
92 struct drm_mode_fb_cmd2 *mode_cmd,
93 struct drm_i915_gem_object *obj);
94 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
95 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
96 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
97 struct intel_link_m_n *m_n,
98 struct intel_link_m_n *m2_n2);
99 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
100 static void haswell_set_pipeconf(struct drm_crtc *crtc);
101 static void intel_set_pipe_csc(struct drm_crtc *crtc);
102 static void vlv_prepare_pll(struct intel_crtc *crtc);
103
104 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
105 {
106 if (!connector->mst_port)
107 return connector->encoder;
108 else
109 return &connector->mst_port->mst_encoders[pipe]->base;
110 }
111
112 typedef struct {
113 int min, max;
114 } intel_range_t;
115
116 typedef struct {
117 int dot_limit;
118 int p2_slow, p2_fast;
119 } intel_p2_t;
120
121 typedef struct intel_limit intel_limit_t;
122 struct intel_limit {
123 intel_range_t dot, vco, n, m, m1, m2, p, p1;
124 intel_p2_t p2;
125 };
126
127 int
128 intel_pch_rawclk(struct drm_device *dev)
129 {
130 struct drm_i915_private *dev_priv = dev->dev_private;
131
132 WARN_ON(!HAS_PCH_SPLIT(dev));
133
134 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
135 }
136
137 static inline u32 /* units of 100MHz */
138 intel_fdi_link_freq(struct drm_device *dev)
139 {
140 if (IS_GEN5(dev)) {
141 struct drm_i915_private *dev_priv = dev->dev_private;
142 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
143 } else
144 return 27;
145 }
146
147 static const intel_limit_t intel_limits_i8xx_dac = {
148 .dot = { .min = 25000, .max = 350000 },
149 .vco = { .min = 908000, .max = 1512000 },
150 .n = { .min = 2, .max = 16 },
151 .m = { .min = 96, .max = 140 },
152 .m1 = { .min = 18, .max = 26 },
153 .m2 = { .min = 6, .max = 16 },
154 .p = { .min = 4, .max = 128 },
155 .p1 = { .min = 2, .max = 33 },
156 .p2 = { .dot_limit = 165000,
157 .p2_slow = 4, .p2_fast = 2 },
158 };
159
160 static const intel_limit_t intel_limits_i8xx_dvo = {
161 .dot = { .min = 25000, .max = 350000 },
162 .vco = { .min = 908000, .max = 1512000 },
163 .n = { .min = 2, .max = 16 },
164 .m = { .min = 96, .max = 140 },
165 .m1 = { .min = 18, .max = 26 },
166 .m2 = { .min = 6, .max = 16 },
167 .p = { .min = 4, .max = 128 },
168 .p1 = { .min = 2, .max = 33 },
169 .p2 = { .dot_limit = 165000,
170 .p2_slow = 4, .p2_fast = 4 },
171 };
172
173 static const intel_limit_t intel_limits_i8xx_lvds = {
174 .dot = { .min = 25000, .max = 350000 },
175 .vco = { .min = 908000, .max = 1512000 },
176 .n = { .min = 2, .max = 16 },
177 .m = { .min = 96, .max = 140 },
178 .m1 = { .min = 18, .max = 26 },
179 .m2 = { .min = 6, .max = 16 },
180 .p = { .min = 4, .max = 128 },
181 .p1 = { .min = 1, .max = 6 },
182 .p2 = { .dot_limit = 165000,
183 .p2_slow = 14, .p2_fast = 7 },
184 };
185
186 static const intel_limit_t intel_limits_i9xx_sdvo = {
187 .dot = { .min = 20000, .max = 400000 },
188 .vco = { .min = 1400000, .max = 2800000 },
189 .n = { .min = 1, .max = 6 },
190 .m = { .min = 70, .max = 120 },
191 .m1 = { .min = 8, .max = 18 },
192 .m2 = { .min = 3, .max = 7 },
193 .p = { .min = 5, .max = 80 },
194 .p1 = { .min = 1, .max = 8 },
195 .p2 = { .dot_limit = 200000,
196 .p2_slow = 10, .p2_fast = 5 },
197 };
198
199 static const intel_limit_t intel_limits_i9xx_lvds = {
200 .dot = { .min = 20000, .max = 400000 },
201 .vco = { .min = 1400000, .max = 2800000 },
202 .n = { .min = 1, .max = 6 },
203 .m = { .min = 70, .max = 120 },
204 .m1 = { .min = 8, .max = 18 },
205 .m2 = { .min = 3, .max = 7 },
206 .p = { .min = 7, .max = 98 },
207 .p1 = { .min = 1, .max = 8 },
208 .p2 = { .dot_limit = 112000,
209 .p2_slow = 14, .p2_fast = 7 },
210 };
211
212
213 static const intel_limit_t intel_limits_g4x_sdvo = {
214 .dot = { .min = 25000, .max = 270000 },
215 .vco = { .min = 1750000, .max = 3500000},
216 .n = { .min = 1, .max = 4 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 17, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 10, .max = 30 },
221 .p1 = { .min = 1, .max = 3},
222 .p2 = { .dot_limit = 270000,
223 .p2_slow = 10,
224 .p2_fast = 10
225 },
226 };
227
228 static const intel_limit_t intel_limits_g4x_hdmi = {
229 .dot = { .min = 22000, .max = 400000 },
230 .vco = { .min = 1750000, .max = 3500000},
231 .n = { .min = 1, .max = 4 },
232 .m = { .min = 104, .max = 138 },
233 .m1 = { .min = 16, .max = 23 },
234 .m2 = { .min = 5, .max = 11 },
235 .p = { .min = 5, .max = 80 },
236 .p1 = { .min = 1, .max = 8},
237 .p2 = { .dot_limit = 165000,
238 .p2_slow = 10, .p2_fast = 5 },
239 };
240
241 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
242 .dot = { .min = 20000, .max = 115000 },
243 .vco = { .min = 1750000, .max = 3500000 },
244 .n = { .min = 1, .max = 3 },
245 .m = { .min = 104, .max = 138 },
246 .m1 = { .min = 17, .max = 23 },
247 .m2 = { .min = 5, .max = 11 },
248 .p = { .min = 28, .max = 112 },
249 .p1 = { .min = 2, .max = 8 },
250 .p2 = { .dot_limit = 0,
251 .p2_slow = 14, .p2_fast = 14
252 },
253 };
254
255 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
256 .dot = { .min = 80000, .max = 224000 },
257 .vco = { .min = 1750000, .max = 3500000 },
258 .n = { .min = 1, .max = 3 },
259 .m = { .min = 104, .max = 138 },
260 .m1 = { .min = 17, .max = 23 },
261 .m2 = { .min = 5, .max = 11 },
262 .p = { .min = 14, .max = 42 },
263 .p1 = { .min = 2, .max = 6 },
264 .p2 = { .dot_limit = 0,
265 .p2_slow = 7, .p2_fast = 7
266 },
267 };
268
269 static const intel_limit_t intel_limits_pineview_sdvo = {
270 .dot = { .min = 20000, .max = 400000},
271 .vco = { .min = 1700000, .max = 3500000 },
272 /* Pineview's Ncounter is a ring counter */
273 .n = { .min = 3, .max = 6 },
274 .m = { .min = 2, .max = 256 },
275 /* Pineview only has one combined m divider, which we treat as m2. */
276 .m1 = { .min = 0, .max = 0 },
277 .m2 = { .min = 0, .max = 254 },
278 .p = { .min = 5, .max = 80 },
279 .p1 = { .min = 1, .max = 8 },
280 .p2 = { .dot_limit = 200000,
281 .p2_slow = 10, .p2_fast = 5 },
282 };
283
284 static const intel_limit_t intel_limits_pineview_lvds = {
285 .dot = { .min = 20000, .max = 400000 },
286 .vco = { .min = 1700000, .max = 3500000 },
287 .n = { .min = 3, .max = 6 },
288 .m = { .min = 2, .max = 256 },
289 .m1 = { .min = 0, .max = 0 },
290 .m2 = { .min = 0, .max = 254 },
291 .p = { .min = 7, .max = 112 },
292 .p1 = { .min = 1, .max = 8 },
293 .p2 = { .dot_limit = 112000,
294 .p2_slow = 14, .p2_fast = 14 },
295 };
296
297 /* Ironlake / Sandybridge
298 *
299 * We calculate clock using (register_value + 2) for N/M1/M2, so here
300 * the range value for them is (actual_value - 2).
301 */
302 static const intel_limit_t intel_limits_ironlake_dac = {
303 .dot = { .min = 25000, .max = 350000 },
304 .vco = { .min = 1760000, .max = 3510000 },
305 .n = { .min = 1, .max = 5 },
306 .m = { .min = 79, .max = 127 },
307 .m1 = { .min = 12, .max = 22 },
308 .m2 = { .min = 5, .max = 9 },
309 .p = { .min = 5, .max = 80 },
310 .p1 = { .min = 1, .max = 8 },
311 .p2 = { .dot_limit = 225000,
312 .p2_slow = 10, .p2_fast = 5 },
313 };
314
315 static const intel_limit_t intel_limits_ironlake_single_lvds = {
316 .dot = { .min = 25000, .max = 350000 },
317 .vco = { .min = 1760000, .max = 3510000 },
318 .n = { .min = 1, .max = 3 },
319 .m = { .min = 79, .max = 118 },
320 .m1 = { .min = 12, .max = 22 },
321 .m2 = { .min = 5, .max = 9 },
322 .p = { .min = 28, .max = 112 },
323 .p1 = { .min = 2, .max = 8 },
324 .p2 = { .dot_limit = 225000,
325 .p2_slow = 14, .p2_fast = 14 },
326 };
327
328 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
329 .dot = { .min = 25000, .max = 350000 },
330 .vco = { .min = 1760000, .max = 3510000 },
331 .n = { .min = 1, .max = 3 },
332 .m = { .min = 79, .max = 127 },
333 .m1 = { .min = 12, .max = 22 },
334 .m2 = { .min = 5, .max = 9 },
335 .p = { .min = 14, .max = 56 },
336 .p1 = { .min = 2, .max = 8 },
337 .p2 = { .dot_limit = 225000,
338 .p2_slow = 7, .p2_fast = 7 },
339 };
340
341 /* LVDS 100mhz refclk limits. */
342 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
343 .dot = { .min = 25000, .max = 350000 },
344 .vco = { .min = 1760000, .max = 3510000 },
345 .n = { .min = 1, .max = 2 },
346 .m = { .min = 79, .max = 126 },
347 .m1 = { .min = 12, .max = 22 },
348 .m2 = { .min = 5, .max = 9 },
349 .p = { .min = 28, .max = 112 },
350 .p1 = { .min = 2, .max = 8 },
351 .p2 = { .dot_limit = 225000,
352 .p2_slow = 14, .p2_fast = 14 },
353 };
354
355 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
356 .dot = { .min = 25000, .max = 350000 },
357 .vco = { .min = 1760000, .max = 3510000 },
358 .n = { .min = 1, .max = 3 },
359 .m = { .min = 79, .max = 126 },
360 .m1 = { .min = 12, .max = 22 },
361 .m2 = { .min = 5, .max = 9 },
362 .p = { .min = 14, .max = 42 },
363 .p1 = { .min = 2, .max = 6 },
364 .p2 = { .dot_limit = 225000,
365 .p2_slow = 7, .p2_fast = 7 },
366 };
367
368 static const intel_limit_t intel_limits_vlv = {
369 /*
370 * These are the data rate limits (measured in fast clocks)
371 * since those are the strictest limits we have. The fast
372 * clock and actual rate limits are more relaxed, so checking
373 * them would make no difference.
374 */
375 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
376 .vco = { .min = 4000000, .max = 6000000 },
377 .n = { .min = 1, .max = 7 },
378 .m1 = { .min = 2, .max = 3 },
379 .m2 = { .min = 11, .max = 156 },
380 .p1 = { .min = 2, .max = 3 },
381 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
382 };
383
384 static const intel_limit_t intel_limits_chv = {
385 /*
386 * These are the data rate limits (measured in fast clocks)
387 * since those are the strictest limits we have. The fast
388 * clock and actual rate limits are more relaxed, so checking
389 * them would make no difference.
390 */
391 .dot = { .min = 25000 * 5, .max = 540000 * 5},
392 .vco = { .min = 4860000, .max = 6700000 },
393 .n = { .min = 1, .max = 1 },
394 .m1 = { .min = 2, .max = 2 },
395 .m2 = { .min = 24 << 22, .max = 175 << 22 },
396 .p1 = { .min = 2, .max = 4 },
397 .p2 = { .p2_slow = 1, .p2_fast = 14 },
398 };
399
400 static void vlv_clock(int refclk, intel_clock_t *clock)
401 {
402 clock->m = clock->m1 * clock->m2;
403 clock->p = clock->p1 * clock->p2;
404 if (WARN_ON(clock->n == 0 || clock->p == 0))
405 return;
406 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
407 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
408 }
409
410 /**
411 * Returns whether any output on the specified pipe is of the specified type
412 */
413 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
414 {
415 struct drm_device *dev = crtc->dev;
416 struct intel_encoder *encoder;
417
418 for_each_encoder_on_crtc(dev, crtc, encoder)
419 if (encoder->type == type)
420 return true;
421
422 return false;
423 }
424
425 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
426 int refclk)
427 {
428 struct drm_device *dev = crtc->dev;
429 const intel_limit_t *limit;
430
431 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
432 if (intel_is_dual_link_lvds(dev)) {
433 if (refclk == 100000)
434 limit = &intel_limits_ironlake_dual_lvds_100m;
435 else
436 limit = &intel_limits_ironlake_dual_lvds;
437 } else {
438 if (refclk == 100000)
439 limit = &intel_limits_ironlake_single_lvds_100m;
440 else
441 limit = &intel_limits_ironlake_single_lvds;
442 }
443 } else
444 limit = &intel_limits_ironlake_dac;
445
446 return limit;
447 }
448
449 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
450 {
451 struct drm_device *dev = crtc->dev;
452 const intel_limit_t *limit;
453
454 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
455 if (intel_is_dual_link_lvds(dev))
456 limit = &intel_limits_g4x_dual_channel_lvds;
457 else
458 limit = &intel_limits_g4x_single_channel_lvds;
459 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
460 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
461 limit = &intel_limits_g4x_hdmi;
462 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
463 limit = &intel_limits_g4x_sdvo;
464 } else /* The option is for other outputs */
465 limit = &intel_limits_i9xx_sdvo;
466
467 return limit;
468 }
469
470 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
471 {
472 struct drm_device *dev = crtc->dev;
473 const intel_limit_t *limit;
474
475 if (HAS_PCH_SPLIT(dev))
476 limit = intel_ironlake_limit(crtc, refclk);
477 else if (IS_G4X(dev)) {
478 limit = intel_g4x_limit(crtc);
479 } else if (IS_PINEVIEW(dev)) {
480 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
481 limit = &intel_limits_pineview_lvds;
482 else
483 limit = &intel_limits_pineview_sdvo;
484 } else if (IS_CHERRYVIEW(dev)) {
485 limit = &intel_limits_chv;
486 } else if (IS_VALLEYVIEW(dev)) {
487 limit = &intel_limits_vlv;
488 } else if (!IS_GEN2(dev)) {
489 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
490 limit = &intel_limits_i9xx_lvds;
491 else
492 limit = &intel_limits_i9xx_sdvo;
493 } else {
494 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
495 limit = &intel_limits_i8xx_lvds;
496 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
497 limit = &intel_limits_i8xx_dvo;
498 else
499 limit = &intel_limits_i8xx_dac;
500 }
501 return limit;
502 }
503
504 /* m1 is reserved as 0 in Pineview, n is a ring counter */
505 static void pineview_clock(int refclk, intel_clock_t *clock)
506 {
507 clock->m = clock->m2 + 2;
508 clock->p = clock->p1 * clock->p2;
509 if (WARN_ON(clock->n == 0 || clock->p == 0))
510 return;
511 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
512 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
513 }
514
515 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
516 {
517 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
518 }
519
520 static void i9xx_clock(int refclk, intel_clock_t *clock)
521 {
522 clock->m = i9xx_dpll_compute_m(clock);
523 clock->p = clock->p1 * clock->p2;
524 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
525 return;
526 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
527 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
528 }
529
530 static void chv_clock(int refclk, intel_clock_t *clock)
531 {
532 clock->m = clock->m1 * clock->m2;
533 clock->p = clock->p1 * clock->p2;
534 if (WARN_ON(clock->n == 0 || clock->p == 0))
535 return;
536 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
537 clock->n << 22);
538 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
539 }
540
541 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
542 /**
543 * Returns whether the given set of divisors are valid for a given refclk with
544 * the given connectors.
545 */
546
547 static bool intel_PLL_is_valid(struct drm_device *dev,
548 const intel_limit_t *limit,
549 const intel_clock_t *clock)
550 {
551 if (clock->n < limit->n.min || limit->n.max < clock->n)
552 INTELPllInvalid("n out of range\n");
553 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
554 INTELPllInvalid("p1 out of range\n");
555 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
556 INTELPllInvalid("m2 out of range\n");
557 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
558 INTELPllInvalid("m1 out of range\n");
559
560 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
561 if (clock->m1 <= clock->m2)
562 INTELPllInvalid("m1 <= m2\n");
563
564 if (!IS_VALLEYVIEW(dev)) {
565 if (clock->p < limit->p.min || limit->p.max < clock->p)
566 INTELPllInvalid("p out of range\n");
567 if (clock->m < limit->m.min || limit->m.max < clock->m)
568 INTELPllInvalid("m out of range\n");
569 }
570
571 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
572 INTELPllInvalid("vco out of range\n");
573 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
574 * connector, etc., rather than just a single range.
575 */
576 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
577 INTELPllInvalid("dot out of range\n");
578
579 return true;
580 }
581
582 static bool
583 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
584 int target, int refclk, intel_clock_t *match_clock,
585 intel_clock_t *best_clock)
586 {
587 struct drm_device *dev = crtc->dev;
588 intel_clock_t clock;
589 int err = target;
590
591 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
592 /*
593 * For LVDS just rely on its current settings for dual-channel.
594 * We haven't figured out how to reliably set up different
595 * single/dual channel state, if we even can.
596 */
597 if (intel_is_dual_link_lvds(dev))
598 clock.p2 = limit->p2.p2_fast;
599 else
600 clock.p2 = limit->p2.p2_slow;
601 } else {
602 if (target < limit->p2.dot_limit)
603 clock.p2 = limit->p2.p2_slow;
604 else
605 clock.p2 = limit->p2.p2_fast;
606 }
607
608 memset(best_clock, 0, sizeof(*best_clock));
609
610 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
611 clock.m1++) {
612 for (clock.m2 = limit->m2.min;
613 clock.m2 <= limit->m2.max; clock.m2++) {
614 if (clock.m2 >= clock.m1)
615 break;
616 for (clock.n = limit->n.min;
617 clock.n <= limit->n.max; clock.n++) {
618 for (clock.p1 = limit->p1.min;
619 clock.p1 <= limit->p1.max; clock.p1++) {
620 int this_err;
621
622 i9xx_clock(refclk, &clock);
623 if (!intel_PLL_is_valid(dev, limit,
624 &clock))
625 continue;
626 if (match_clock &&
627 clock.p != match_clock->p)
628 continue;
629
630 this_err = abs(clock.dot - target);
631 if (this_err < err) {
632 *best_clock = clock;
633 err = this_err;
634 }
635 }
636 }
637 }
638 }
639
640 return (err != target);
641 }
642
643 static bool
644 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
645 int target, int refclk, intel_clock_t *match_clock,
646 intel_clock_t *best_clock)
647 {
648 struct drm_device *dev = crtc->dev;
649 intel_clock_t clock;
650 int err = target;
651
652 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
653 /*
654 * For LVDS just rely on its current settings for dual-channel.
655 * We haven't figured out how to reliably set up different
656 * single/dual channel state, if we even can.
657 */
658 if (intel_is_dual_link_lvds(dev))
659 clock.p2 = limit->p2.p2_fast;
660 else
661 clock.p2 = limit->p2.p2_slow;
662 } else {
663 if (target < limit->p2.dot_limit)
664 clock.p2 = limit->p2.p2_slow;
665 else
666 clock.p2 = limit->p2.p2_fast;
667 }
668
669 memset(best_clock, 0, sizeof(*best_clock));
670
671 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
672 clock.m1++) {
673 for (clock.m2 = limit->m2.min;
674 clock.m2 <= limit->m2.max; clock.m2++) {
675 for (clock.n = limit->n.min;
676 clock.n <= limit->n.max; clock.n++) {
677 for (clock.p1 = limit->p1.min;
678 clock.p1 <= limit->p1.max; clock.p1++) {
679 int this_err;
680
681 pineview_clock(refclk, &clock);
682 if (!intel_PLL_is_valid(dev, limit,
683 &clock))
684 continue;
685 if (match_clock &&
686 clock.p != match_clock->p)
687 continue;
688
689 this_err = abs(clock.dot - target);
690 if (this_err < err) {
691 *best_clock = clock;
692 err = this_err;
693 }
694 }
695 }
696 }
697 }
698
699 return (err != target);
700 }
701
702 static bool
703 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
704 int target, int refclk, intel_clock_t *match_clock,
705 intel_clock_t *best_clock)
706 {
707 struct drm_device *dev = crtc->dev;
708 intel_clock_t clock;
709 int max_n;
710 bool found;
711 /* approximately equals target * 0.00585 */
712 int err_most = (target >> 8) + (target >> 9);
713 found = false;
714
715 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
716 if (intel_is_dual_link_lvds(dev))
717 clock.p2 = limit->p2.p2_fast;
718 else
719 clock.p2 = limit->p2.p2_slow;
720 } else {
721 if (target < limit->p2.dot_limit)
722 clock.p2 = limit->p2.p2_slow;
723 else
724 clock.p2 = limit->p2.p2_fast;
725 }
726
727 memset(best_clock, 0, sizeof(*best_clock));
728 max_n = limit->n.max;
729 /* based on hardware requirement, prefer smaller n to precision */
730 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
731 /* based on hardware requirement, prefere larger m1,m2 */
732 for (clock.m1 = limit->m1.max;
733 clock.m1 >= limit->m1.min; clock.m1--) {
734 for (clock.m2 = limit->m2.max;
735 clock.m2 >= limit->m2.min; clock.m2--) {
736 for (clock.p1 = limit->p1.max;
737 clock.p1 >= limit->p1.min; clock.p1--) {
738 int this_err;
739
740 i9xx_clock(refclk, &clock);
741 if (!intel_PLL_is_valid(dev, limit,
742 &clock))
743 continue;
744
745 this_err = abs(clock.dot - target);
746 if (this_err < err_most) {
747 *best_clock = clock;
748 err_most = this_err;
749 max_n = clock.n;
750 found = true;
751 }
752 }
753 }
754 }
755 }
756 return found;
757 }
758
759 static bool
760 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
761 int target, int refclk, intel_clock_t *match_clock,
762 intel_clock_t *best_clock)
763 {
764 struct drm_device *dev = crtc->dev;
765 intel_clock_t clock;
766 unsigned int bestppm = 1000000;
767 /* min update 19.2 MHz */
768 int max_n = min(limit->n.max, refclk / 19200);
769 bool found = false;
770
771 target *= 5; /* fast clock */
772
773 memset(best_clock, 0, sizeof(*best_clock));
774
775 /* based on hardware requirement, prefer smaller n to precision */
776 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
777 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
778 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
779 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
780 clock.p = clock.p1 * clock.p2;
781 /* based on hardware requirement, prefer bigger m1,m2 values */
782 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
783 unsigned int ppm, diff;
784
785 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
786 refclk * clock.m1);
787
788 vlv_clock(refclk, &clock);
789
790 if (!intel_PLL_is_valid(dev, limit,
791 &clock))
792 continue;
793
794 diff = abs(clock.dot - target);
795 ppm = div_u64(1000000ULL * diff, target);
796
797 if (ppm < 100 && clock.p > best_clock->p) {
798 bestppm = 0;
799 *best_clock = clock;
800 found = true;
801 }
802
803 if (bestppm >= 10 && ppm < bestppm - 10) {
804 bestppm = ppm;
805 *best_clock = clock;
806 found = true;
807 }
808 }
809 }
810 }
811 }
812
813 return found;
814 }
815
816 static bool
817 chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
818 int target, int refclk, intel_clock_t *match_clock,
819 intel_clock_t *best_clock)
820 {
821 struct drm_device *dev = crtc->dev;
822 intel_clock_t clock;
823 uint64_t m2;
824 int found = false;
825
826 memset(best_clock, 0, sizeof(*best_clock));
827
828 /*
829 * Based on hardware doc, the n always set to 1, and m1 always
830 * set to 2. If requires to support 200Mhz refclk, we need to
831 * revisit this because n may not 1 anymore.
832 */
833 clock.n = 1, clock.m1 = 2;
834 target *= 5; /* fast clock */
835
836 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
837 for (clock.p2 = limit->p2.p2_fast;
838 clock.p2 >= limit->p2.p2_slow;
839 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
840
841 clock.p = clock.p1 * clock.p2;
842
843 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
844 clock.n) << 22, refclk * clock.m1);
845
846 if (m2 > INT_MAX/clock.m1)
847 continue;
848
849 clock.m2 = m2;
850
851 chv_clock(refclk, &clock);
852
853 if (!intel_PLL_is_valid(dev, limit, &clock))
854 continue;
855
856 /* based on hardware requirement, prefer bigger p
857 */
858 if (clock.p > best_clock->p) {
859 *best_clock = clock;
860 found = true;
861 }
862 }
863 }
864
865 return found;
866 }
867
868 bool intel_crtc_active(struct drm_crtc *crtc)
869 {
870 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
871
872 /* Be paranoid as we can arrive here with only partial
873 * state retrieved from the hardware during setup.
874 *
875 * We can ditch the adjusted_mode.crtc_clock check as soon
876 * as Haswell has gained clock readout/fastboot support.
877 *
878 * We can ditch the crtc->primary->fb check as soon as we can
879 * properly reconstruct framebuffers.
880 */
881 return intel_crtc->active && crtc->primary->fb &&
882 intel_crtc->config.adjusted_mode.crtc_clock;
883 }
884
885 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
886 enum pipe pipe)
887 {
888 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
889 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
890
891 return intel_crtc->config.cpu_transcoder;
892 }
893
894 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
895 {
896 struct drm_i915_private *dev_priv = dev->dev_private;
897 u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
898
899 frame = I915_READ(frame_reg);
900
901 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
902 WARN(1, "vblank wait timed out\n");
903 }
904
905 /**
906 * intel_wait_for_vblank - wait for vblank on a given pipe
907 * @dev: drm device
908 * @pipe: pipe to wait for
909 *
910 * Wait for vblank to occur on a given pipe. Needed for various bits of
911 * mode setting code.
912 */
913 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
914 {
915 struct drm_i915_private *dev_priv = dev->dev_private;
916 int pipestat_reg = PIPESTAT(pipe);
917
918 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
919 g4x_wait_for_vblank(dev, pipe);
920 return;
921 }
922
923 /* Clear existing vblank status. Note this will clear any other
924 * sticky status fields as well.
925 *
926 * This races with i915_driver_irq_handler() with the result
927 * that either function could miss a vblank event. Here it is not
928 * fatal, as we will either wait upon the next vblank interrupt or
929 * timeout. Generally speaking intel_wait_for_vblank() is only
930 * called during modeset at which time the GPU should be idle and
931 * should *not* be performing page flips and thus not waiting on
932 * vblanks...
933 * Currently, the result of us stealing a vblank from the irq
934 * handler is that a single frame will be skipped during swapbuffers.
935 */
936 I915_WRITE(pipestat_reg,
937 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
938
939 /* Wait for vblank interrupt bit to set */
940 if (wait_for(I915_READ(pipestat_reg) &
941 PIPE_VBLANK_INTERRUPT_STATUS,
942 50))
943 DRM_DEBUG_KMS("vblank wait timed out\n");
944 }
945
946 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
947 {
948 struct drm_i915_private *dev_priv = dev->dev_private;
949 u32 reg = PIPEDSL(pipe);
950 u32 line1, line2;
951 u32 line_mask;
952
953 if (IS_GEN2(dev))
954 line_mask = DSL_LINEMASK_GEN2;
955 else
956 line_mask = DSL_LINEMASK_GEN3;
957
958 line1 = I915_READ(reg) & line_mask;
959 mdelay(5);
960 line2 = I915_READ(reg) & line_mask;
961
962 return line1 == line2;
963 }
964
965 /*
966 * intel_wait_for_pipe_off - wait for pipe to turn off
967 * @dev: drm device
968 * @pipe: pipe to wait for
969 *
970 * After disabling a pipe, we can't wait for vblank in the usual way,
971 * spinning on the vblank interrupt status bit, since we won't actually
972 * see an interrupt when the pipe is disabled.
973 *
974 * On Gen4 and above:
975 * wait for the pipe register state bit to turn off
976 *
977 * Otherwise:
978 * wait for the display line value to settle (it usually
979 * ends up stopping at the start of the next frame).
980 *
981 */
982 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
983 {
984 struct drm_i915_private *dev_priv = dev->dev_private;
985 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
986 pipe);
987
988 if (INTEL_INFO(dev)->gen >= 4) {
989 int reg = PIPECONF(cpu_transcoder);
990
991 /* Wait for the Pipe State to go off */
992 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
993 100))
994 WARN(1, "pipe_off wait timed out\n");
995 } else {
996 /* Wait for the display line to settle */
997 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
998 WARN(1, "pipe_off wait timed out\n");
999 }
1000 }
1001
1002 /*
1003 * ibx_digital_port_connected - is the specified port connected?
1004 * @dev_priv: i915 private structure
1005 * @port: the port to test
1006 *
1007 * Returns true if @port is connected, false otherwise.
1008 */
1009 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1010 struct intel_digital_port *port)
1011 {
1012 u32 bit;
1013
1014 if (HAS_PCH_IBX(dev_priv->dev)) {
1015 switch (port->port) {
1016 case PORT_B:
1017 bit = SDE_PORTB_HOTPLUG;
1018 break;
1019 case PORT_C:
1020 bit = SDE_PORTC_HOTPLUG;
1021 break;
1022 case PORT_D:
1023 bit = SDE_PORTD_HOTPLUG;
1024 break;
1025 default:
1026 return true;
1027 }
1028 } else {
1029 switch (port->port) {
1030 case PORT_B:
1031 bit = SDE_PORTB_HOTPLUG_CPT;
1032 break;
1033 case PORT_C:
1034 bit = SDE_PORTC_HOTPLUG_CPT;
1035 break;
1036 case PORT_D:
1037 bit = SDE_PORTD_HOTPLUG_CPT;
1038 break;
1039 default:
1040 return true;
1041 }
1042 }
1043
1044 return I915_READ(SDEISR) & bit;
1045 }
1046
1047 static const char *state_string(bool enabled)
1048 {
1049 return enabled ? "on" : "off";
1050 }
1051
1052 /* Only for pre-ILK configs */
1053 void assert_pll(struct drm_i915_private *dev_priv,
1054 enum pipe pipe, bool state)
1055 {
1056 int reg;
1057 u32 val;
1058 bool cur_state;
1059
1060 reg = DPLL(pipe);
1061 val = I915_READ(reg);
1062 cur_state = !!(val & DPLL_VCO_ENABLE);
1063 WARN(cur_state != state,
1064 "PLL state assertion failure (expected %s, current %s)\n",
1065 state_string(state), state_string(cur_state));
1066 }
1067
1068 /* XXX: the dsi pll is shared between MIPI DSI ports */
1069 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1070 {
1071 u32 val;
1072 bool cur_state;
1073
1074 mutex_lock(&dev_priv->dpio_lock);
1075 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1076 mutex_unlock(&dev_priv->dpio_lock);
1077
1078 cur_state = val & DSI_PLL_VCO_EN;
1079 WARN(cur_state != state,
1080 "DSI PLL state assertion failure (expected %s, current %s)\n",
1081 state_string(state), state_string(cur_state));
1082 }
1083 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1084 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1085
1086 struct intel_shared_dpll *
1087 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1088 {
1089 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1090
1091 if (crtc->config.shared_dpll < 0)
1092 return NULL;
1093
1094 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1095 }
1096
1097 /* For ILK+ */
1098 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1099 struct intel_shared_dpll *pll,
1100 bool state)
1101 {
1102 bool cur_state;
1103 struct intel_dpll_hw_state hw_state;
1104
1105 if (WARN (!pll,
1106 "asserting DPLL %s with no DPLL\n", state_string(state)))
1107 return;
1108
1109 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1110 WARN(cur_state != state,
1111 "%s assertion failure (expected %s, current %s)\n",
1112 pll->name, state_string(state), state_string(cur_state));
1113 }
1114
1115 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1116 enum pipe pipe, bool state)
1117 {
1118 int reg;
1119 u32 val;
1120 bool cur_state;
1121 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1122 pipe);
1123
1124 if (HAS_DDI(dev_priv->dev)) {
1125 /* DDI does not have a specific FDI_TX register */
1126 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1127 val = I915_READ(reg);
1128 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1129 } else {
1130 reg = FDI_TX_CTL(pipe);
1131 val = I915_READ(reg);
1132 cur_state = !!(val & FDI_TX_ENABLE);
1133 }
1134 WARN(cur_state != state,
1135 "FDI TX state assertion failure (expected %s, current %s)\n",
1136 state_string(state), state_string(cur_state));
1137 }
1138 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1139 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1140
1141 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1142 enum pipe pipe, bool state)
1143 {
1144 int reg;
1145 u32 val;
1146 bool cur_state;
1147
1148 reg = FDI_RX_CTL(pipe);
1149 val = I915_READ(reg);
1150 cur_state = !!(val & FDI_RX_ENABLE);
1151 WARN(cur_state != state,
1152 "FDI RX state assertion failure (expected %s, current %s)\n",
1153 state_string(state), state_string(cur_state));
1154 }
1155 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1156 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1157
1158 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1159 enum pipe pipe)
1160 {
1161 int reg;
1162 u32 val;
1163
1164 /* ILK FDI PLL is always enabled */
1165 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1166 return;
1167
1168 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1169 if (HAS_DDI(dev_priv->dev))
1170 return;
1171
1172 reg = FDI_TX_CTL(pipe);
1173 val = I915_READ(reg);
1174 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1175 }
1176
1177 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1178 enum pipe pipe, bool state)
1179 {
1180 int reg;
1181 u32 val;
1182 bool cur_state;
1183
1184 reg = FDI_RX_CTL(pipe);
1185 val = I915_READ(reg);
1186 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1187 WARN(cur_state != state,
1188 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1189 state_string(state), state_string(cur_state));
1190 }
1191
1192 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1193 enum pipe pipe)
1194 {
1195 int pp_reg, lvds_reg;
1196 u32 val;
1197 enum pipe panel_pipe = PIPE_A;
1198 bool locked = true;
1199
1200 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1201 pp_reg = PCH_PP_CONTROL;
1202 lvds_reg = PCH_LVDS;
1203 } else {
1204 pp_reg = PP_CONTROL;
1205 lvds_reg = LVDS;
1206 }
1207
1208 val = I915_READ(pp_reg);
1209 if (!(val & PANEL_POWER_ON) ||
1210 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1211 locked = false;
1212
1213 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1214 panel_pipe = PIPE_B;
1215
1216 WARN(panel_pipe == pipe && locked,
1217 "panel assertion failure, pipe %c regs locked\n",
1218 pipe_name(pipe));
1219 }
1220
1221 static void assert_cursor(struct drm_i915_private *dev_priv,
1222 enum pipe pipe, bool state)
1223 {
1224 struct drm_device *dev = dev_priv->dev;
1225 bool cur_state;
1226
1227 if (IS_845G(dev) || IS_I865G(dev))
1228 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1229 else
1230 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1231
1232 WARN(cur_state != state,
1233 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1234 pipe_name(pipe), state_string(state), state_string(cur_state));
1235 }
1236 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1237 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1238
1239 void assert_pipe(struct drm_i915_private *dev_priv,
1240 enum pipe pipe, bool state)
1241 {
1242 int reg;
1243 u32 val;
1244 bool cur_state;
1245 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1246 pipe);
1247
1248 /* if we need the pipe A quirk it must be always on */
1249 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1250 state = true;
1251
1252 if (!intel_display_power_enabled(dev_priv,
1253 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1254 cur_state = false;
1255 } else {
1256 reg = PIPECONF(cpu_transcoder);
1257 val = I915_READ(reg);
1258 cur_state = !!(val & PIPECONF_ENABLE);
1259 }
1260
1261 WARN(cur_state != state,
1262 "pipe %c assertion failure (expected %s, current %s)\n",
1263 pipe_name(pipe), state_string(state), state_string(cur_state));
1264 }
1265
1266 static void assert_plane(struct drm_i915_private *dev_priv,
1267 enum plane plane, bool state)
1268 {
1269 int reg;
1270 u32 val;
1271 bool cur_state;
1272
1273 reg = DSPCNTR(plane);
1274 val = I915_READ(reg);
1275 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1276 WARN(cur_state != state,
1277 "plane %c assertion failure (expected %s, current %s)\n",
1278 plane_name(plane), state_string(state), state_string(cur_state));
1279 }
1280
1281 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1282 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1283
1284 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1285 enum pipe pipe)
1286 {
1287 struct drm_device *dev = dev_priv->dev;
1288 int reg, i;
1289 u32 val;
1290 int cur_pipe;
1291
1292 /* Primary planes are fixed to pipes on gen4+ */
1293 if (INTEL_INFO(dev)->gen >= 4) {
1294 reg = DSPCNTR(pipe);
1295 val = I915_READ(reg);
1296 WARN(val & DISPLAY_PLANE_ENABLE,
1297 "plane %c assertion failure, should be disabled but not\n",
1298 plane_name(pipe));
1299 return;
1300 }
1301
1302 /* Need to check both planes against the pipe */
1303 for_each_pipe(i) {
1304 reg = DSPCNTR(i);
1305 val = I915_READ(reg);
1306 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1307 DISPPLANE_SEL_PIPE_SHIFT;
1308 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1309 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1310 plane_name(i), pipe_name(pipe));
1311 }
1312 }
1313
1314 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1315 enum pipe pipe)
1316 {
1317 struct drm_device *dev = dev_priv->dev;
1318 int reg, sprite;
1319 u32 val;
1320
1321 if (IS_VALLEYVIEW(dev)) {
1322 for_each_sprite(pipe, sprite) {
1323 reg = SPCNTR(pipe, sprite);
1324 val = I915_READ(reg);
1325 WARN(val & SP_ENABLE,
1326 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1327 sprite_name(pipe, sprite), pipe_name(pipe));
1328 }
1329 } else if (INTEL_INFO(dev)->gen >= 7) {
1330 reg = SPRCTL(pipe);
1331 val = I915_READ(reg);
1332 WARN(val & SPRITE_ENABLE,
1333 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1334 plane_name(pipe), pipe_name(pipe));
1335 } else if (INTEL_INFO(dev)->gen >= 5) {
1336 reg = DVSCNTR(pipe);
1337 val = I915_READ(reg);
1338 WARN(val & DVS_ENABLE,
1339 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1340 plane_name(pipe), pipe_name(pipe));
1341 }
1342 }
1343
1344 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1345 {
1346 u32 val;
1347 bool enabled;
1348
1349 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1350
1351 val = I915_READ(PCH_DREF_CONTROL);
1352 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1353 DREF_SUPERSPREAD_SOURCE_MASK));
1354 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1355 }
1356
1357 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1358 enum pipe pipe)
1359 {
1360 int reg;
1361 u32 val;
1362 bool enabled;
1363
1364 reg = PCH_TRANSCONF(pipe);
1365 val = I915_READ(reg);
1366 enabled = !!(val & TRANS_ENABLE);
1367 WARN(enabled,
1368 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1369 pipe_name(pipe));
1370 }
1371
1372 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1373 enum pipe pipe, u32 port_sel, u32 val)
1374 {
1375 if ((val & DP_PORT_EN) == 0)
1376 return false;
1377
1378 if (HAS_PCH_CPT(dev_priv->dev)) {
1379 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1380 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1381 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1382 return false;
1383 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1384 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1385 return false;
1386 } else {
1387 if ((val & DP_PIPE_MASK) != (pipe << 30))
1388 return false;
1389 }
1390 return true;
1391 }
1392
1393 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1394 enum pipe pipe, u32 val)
1395 {
1396 if ((val & SDVO_ENABLE) == 0)
1397 return false;
1398
1399 if (HAS_PCH_CPT(dev_priv->dev)) {
1400 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1401 return false;
1402 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1403 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1404 return false;
1405 } else {
1406 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1407 return false;
1408 }
1409 return true;
1410 }
1411
1412 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1413 enum pipe pipe, u32 val)
1414 {
1415 if ((val & LVDS_PORT_EN) == 0)
1416 return false;
1417
1418 if (HAS_PCH_CPT(dev_priv->dev)) {
1419 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1420 return false;
1421 } else {
1422 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1423 return false;
1424 }
1425 return true;
1426 }
1427
1428 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1429 enum pipe pipe, u32 val)
1430 {
1431 if ((val & ADPA_DAC_ENABLE) == 0)
1432 return false;
1433 if (HAS_PCH_CPT(dev_priv->dev)) {
1434 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1435 return false;
1436 } else {
1437 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1438 return false;
1439 }
1440 return true;
1441 }
1442
1443 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1444 enum pipe pipe, int reg, u32 port_sel)
1445 {
1446 u32 val = I915_READ(reg);
1447 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1448 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1449 reg, pipe_name(pipe));
1450
1451 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1452 && (val & DP_PIPEB_SELECT),
1453 "IBX PCH dp port still using transcoder B\n");
1454 }
1455
1456 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1457 enum pipe pipe, int reg)
1458 {
1459 u32 val = I915_READ(reg);
1460 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1461 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1462 reg, pipe_name(pipe));
1463
1464 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1465 && (val & SDVO_PIPE_B_SELECT),
1466 "IBX PCH hdmi port still using transcoder B\n");
1467 }
1468
1469 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1470 enum pipe pipe)
1471 {
1472 int reg;
1473 u32 val;
1474
1475 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1476 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1477 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1478
1479 reg = PCH_ADPA;
1480 val = I915_READ(reg);
1481 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1482 "PCH VGA enabled on transcoder %c, should be disabled\n",
1483 pipe_name(pipe));
1484
1485 reg = PCH_LVDS;
1486 val = I915_READ(reg);
1487 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1488 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1489 pipe_name(pipe));
1490
1491 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1492 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1493 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1494 }
1495
1496 static void intel_init_dpio(struct drm_device *dev)
1497 {
1498 struct drm_i915_private *dev_priv = dev->dev_private;
1499
1500 if (!IS_VALLEYVIEW(dev))
1501 return;
1502
1503 /*
1504 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1505 * CHV x1 PHY (DP/HDMI D)
1506 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1507 */
1508 if (IS_CHERRYVIEW(dev)) {
1509 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1510 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1511 } else {
1512 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1513 }
1514 }
1515
1516 static void intel_reset_dpio(struct drm_device *dev)
1517 {
1518 struct drm_i915_private *dev_priv = dev->dev_private;
1519
1520 if (IS_CHERRYVIEW(dev)) {
1521 enum dpio_phy phy;
1522 u32 val;
1523
1524 for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) {
1525 /* Poll for phypwrgood signal */
1526 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) &
1527 PHY_POWERGOOD(phy), 1))
1528 DRM_ERROR("Display PHY %d is not power up\n", phy);
1529
1530 /*
1531 * Deassert common lane reset for PHY.
1532 *
1533 * This should only be done on init and resume from S3
1534 * with both PLLs disabled, or we risk losing DPIO and
1535 * PLL synchronization.
1536 */
1537 val = I915_READ(DISPLAY_PHY_CONTROL);
1538 I915_WRITE(DISPLAY_PHY_CONTROL,
1539 PHY_COM_LANE_RESET_DEASSERT(phy, val));
1540 }
1541 }
1542 }
1543
1544 static void vlv_enable_pll(struct intel_crtc *crtc)
1545 {
1546 struct drm_device *dev = crtc->base.dev;
1547 struct drm_i915_private *dev_priv = dev->dev_private;
1548 int reg = DPLL(crtc->pipe);
1549 u32 dpll = crtc->config.dpll_hw_state.dpll;
1550
1551 assert_pipe_disabled(dev_priv, crtc->pipe);
1552
1553 /* No really, not for ILK+ */
1554 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1555
1556 /* PLL is protected by panel, make sure we can write it */
1557 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1558 assert_panel_unlocked(dev_priv, crtc->pipe);
1559
1560 I915_WRITE(reg, dpll);
1561 POSTING_READ(reg);
1562 udelay(150);
1563
1564 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1565 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1566
1567 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1568 POSTING_READ(DPLL_MD(crtc->pipe));
1569
1570 /* We do this three times for luck */
1571 I915_WRITE(reg, dpll);
1572 POSTING_READ(reg);
1573 udelay(150); /* wait for warmup */
1574 I915_WRITE(reg, dpll);
1575 POSTING_READ(reg);
1576 udelay(150); /* wait for warmup */
1577 I915_WRITE(reg, dpll);
1578 POSTING_READ(reg);
1579 udelay(150); /* wait for warmup */
1580 }
1581
1582 static void chv_enable_pll(struct intel_crtc *crtc)
1583 {
1584 struct drm_device *dev = crtc->base.dev;
1585 struct drm_i915_private *dev_priv = dev->dev_private;
1586 int pipe = crtc->pipe;
1587 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1588 u32 tmp;
1589
1590 assert_pipe_disabled(dev_priv, crtc->pipe);
1591
1592 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1593
1594 mutex_lock(&dev_priv->dpio_lock);
1595
1596 /* Enable back the 10bit clock to display controller */
1597 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1598 tmp |= DPIO_DCLKP_EN;
1599 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1600
1601 /*
1602 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1603 */
1604 udelay(1);
1605
1606 /* Enable PLL */
1607 I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
1608
1609 /* Check PLL is locked */
1610 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1611 DRM_ERROR("PLL %d failed to lock\n", pipe);
1612
1613 /* not sure when this should be written */
1614 I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
1615 POSTING_READ(DPLL_MD(pipe));
1616
1617 mutex_unlock(&dev_priv->dpio_lock);
1618 }
1619
1620 static void i9xx_enable_pll(struct intel_crtc *crtc)
1621 {
1622 struct drm_device *dev = crtc->base.dev;
1623 struct drm_i915_private *dev_priv = dev->dev_private;
1624 int reg = DPLL(crtc->pipe);
1625 u32 dpll = crtc->config.dpll_hw_state.dpll;
1626
1627 assert_pipe_disabled(dev_priv, crtc->pipe);
1628
1629 /* No really, not for ILK+ */
1630 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1631
1632 /* PLL is protected by panel, make sure we can write it */
1633 if (IS_MOBILE(dev) && !IS_I830(dev))
1634 assert_panel_unlocked(dev_priv, crtc->pipe);
1635
1636 I915_WRITE(reg, dpll);
1637
1638 /* Wait for the clocks to stabilize. */
1639 POSTING_READ(reg);
1640 udelay(150);
1641
1642 if (INTEL_INFO(dev)->gen >= 4) {
1643 I915_WRITE(DPLL_MD(crtc->pipe),
1644 crtc->config.dpll_hw_state.dpll_md);
1645 } else {
1646 /* The pixel multiplier can only be updated once the
1647 * DPLL is enabled and the clocks are stable.
1648 *
1649 * So write it again.
1650 */
1651 I915_WRITE(reg, dpll);
1652 }
1653
1654 /* We do this three times for luck */
1655 I915_WRITE(reg, dpll);
1656 POSTING_READ(reg);
1657 udelay(150); /* wait for warmup */
1658 I915_WRITE(reg, dpll);
1659 POSTING_READ(reg);
1660 udelay(150); /* wait for warmup */
1661 I915_WRITE(reg, dpll);
1662 POSTING_READ(reg);
1663 udelay(150); /* wait for warmup */
1664 }
1665
1666 /**
1667 * i9xx_disable_pll - disable a PLL
1668 * @dev_priv: i915 private structure
1669 * @pipe: pipe PLL to disable
1670 *
1671 * Disable the PLL for @pipe, making sure the pipe is off first.
1672 *
1673 * Note! This is for pre-ILK only.
1674 */
1675 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1676 {
1677 /* Don't disable pipe A or pipe A PLLs if needed */
1678 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1679 return;
1680
1681 /* Make sure the pipe isn't still relying on us */
1682 assert_pipe_disabled(dev_priv, pipe);
1683
1684 I915_WRITE(DPLL(pipe), 0);
1685 POSTING_READ(DPLL(pipe));
1686 }
1687
1688 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1689 {
1690 u32 val = 0;
1691
1692 /* Make sure the pipe isn't still relying on us */
1693 assert_pipe_disabled(dev_priv, pipe);
1694
1695 /*
1696 * Leave integrated clock source and reference clock enabled for pipe B.
1697 * The latter is needed for VGA hotplug / manual detection.
1698 */
1699 if (pipe == PIPE_B)
1700 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1701 I915_WRITE(DPLL(pipe), val);
1702 POSTING_READ(DPLL(pipe));
1703
1704 }
1705
1706 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1707 {
1708 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1709 u32 val;
1710
1711 /* Make sure the pipe isn't still relying on us */
1712 assert_pipe_disabled(dev_priv, pipe);
1713
1714 /* Set PLL en = 0 */
1715 val = DPLL_SSC_REF_CLOCK_CHV;
1716 if (pipe != PIPE_A)
1717 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1718 I915_WRITE(DPLL(pipe), val);
1719 POSTING_READ(DPLL(pipe));
1720
1721 mutex_lock(&dev_priv->dpio_lock);
1722
1723 /* Disable 10bit clock to display controller */
1724 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1725 val &= ~DPIO_DCLKP_EN;
1726 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1727
1728 /* disable left/right clock distribution */
1729 if (pipe != PIPE_B) {
1730 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1731 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1732 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1733 } else {
1734 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1735 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1736 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1737 }
1738
1739 mutex_unlock(&dev_priv->dpio_lock);
1740 }
1741
1742 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1743 struct intel_digital_port *dport)
1744 {
1745 u32 port_mask;
1746 int dpll_reg;
1747
1748 switch (dport->port) {
1749 case PORT_B:
1750 port_mask = DPLL_PORTB_READY_MASK;
1751 dpll_reg = DPLL(0);
1752 break;
1753 case PORT_C:
1754 port_mask = DPLL_PORTC_READY_MASK;
1755 dpll_reg = DPLL(0);
1756 break;
1757 case PORT_D:
1758 port_mask = DPLL_PORTD_READY_MASK;
1759 dpll_reg = DPIO_PHY_STATUS;
1760 break;
1761 default:
1762 BUG();
1763 }
1764
1765 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1766 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1767 port_name(dport->port), I915_READ(dpll_reg));
1768 }
1769
1770 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1771 {
1772 struct drm_device *dev = crtc->base.dev;
1773 struct drm_i915_private *dev_priv = dev->dev_private;
1774 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1775
1776 if (WARN_ON(pll == NULL))
1777 return;
1778
1779 WARN_ON(!pll->refcount);
1780 if (pll->active == 0) {
1781 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1782 WARN_ON(pll->on);
1783 assert_shared_dpll_disabled(dev_priv, pll);
1784
1785 pll->mode_set(dev_priv, pll);
1786 }
1787 }
1788
1789 /**
1790 * intel_enable_shared_dpll - enable PCH PLL
1791 * @dev_priv: i915 private structure
1792 * @pipe: pipe PLL to enable
1793 *
1794 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1795 * drives the transcoder clock.
1796 */
1797 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1798 {
1799 struct drm_device *dev = crtc->base.dev;
1800 struct drm_i915_private *dev_priv = dev->dev_private;
1801 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1802
1803 if (WARN_ON(pll == NULL))
1804 return;
1805
1806 if (WARN_ON(pll->refcount == 0))
1807 return;
1808
1809 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1810 pll->name, pll->active, pll->on,
1811 crtc->base.base.id);
1812
1813 if (pll->active++) {
1814 WARN_ON(!pll->on);
1815 assert_shared_dpll_enabled(dev_priv, pll);
1816 return;
1817 }
1818 WARN_ON(pll->on);
1819
1820 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1821
1822 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1823 pll->enable(dev_priv, pll);
1824 pll->on = true;
1825 }
1826
1827 void intel_disable_shared_dpll(struct intel_crtc *crtc)
1828 {
1829 struct drm_device *dev = crtc->base.dev;
1830 struct drm_i915_private *dev_priv = dev->dev_private;
1831 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1832
1833 /* PCH only available on ILK+ */
1834 BUG_ON(INTEL_INFO(dev)->gen < 5);
1835 if (WARN_ON(pll == NULL))
1836 return;
1837
1838 if (WARN_ON(pll->refcount == 0))
1839 return;
1840
1841 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1842 pll->name, pll->active, pll->on,
1843 crtc->base.base.id);
1844
1845 if (WARN_ON(pll->active == 0)) {
1846 assert_shared_dpll_disabled(dev_priv, pll);
1847 return;
1848 }
1849
1850 assert_shared_dpll_enabled(dev_priv, pll);
1851 WARN_ON(!pll->on);
1852 if (--pll->active)
1853 return;
1854
1855 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1856 pll->disable(dev_priv, pll);
1857 pll->on = false;
1858
1859 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1860 }
1861
1862 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1863 enum pipe pipe)
1864 {
1865 struct drm_device *dev = dev_priv->dev;
1866 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1867 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1868 uint32_t reg, val, pipeconf_val;
1869
1870 /* PCH only available on ILK+ */
1871 BUG_ON(INTEL_INFO(dev)->gen < 5);
1872
1873 /* Make sure PCH DPLL is enabled */
1874 assert_shared_dpll_enabled(dev_priv,
1875 intel_crtc_to_shared_dpll(intel_crtc));
1876
1877 /* FDI must be feeding us bits for PCH ports */
1878 assert_fdi_tx_enabled(dev_priv, pipe);
1879 assert_fdi_rx_enabled(dev_priv, pipe);
1880
1881 if (HAS_PCH_CPT(dev)) {
1882 /* Workaround: Set the timing override bit before enabling the
1883 * pch transcoder. */
1884 reg = TRANS_CHICKEN2(pipe);
1885 val = I915_READ(reg);
1886 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1887 I915_WRITE(reg, val);
1888 }
1889
1890 reg = PCH_TRANSCONF(pipe);
1891 val = I915_READ(reg);
1892 pipeconf_val = I915_READ(PIPECONF(pipe));
1893
1894 if (HAS_PCH_IBX(dev_priv->dev)) {
1895 /*
1896 * make the BPC in transcoder be consistent with
1897 * that in pipeconf reg.
1898 */
1899 val &= ~PIPECONF_BPC_MASK;
1900 val |= pipeconf_val & PIPECONF_BPC_MASK;
1901 }
1902
1903 val &= ~TRANS_INTERLACE_MASK;
1904 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1905 if (HAS_PCH_IBX(dev_priv->dev) &&
1906 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1907 val |= TRANS_LEGACY_INTERLACED_ILK;
1908 else
1909 val |= TRANS_INTERLACED;
1910 else
1911 val |= TRANS_PROGRESSIVE;
1912
1913 I915_WRITE(reg, val | TRANS_ENABLE);
1914 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1915 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1916 }
1917
1918 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1919 enum transcoder cpu_transcoder)
1920 {
1921 u32 val, pipeconf_val;
1922
1923 /* PCH only available on ILK+ */
1924 BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1925
1926 /* FDI must be feeding us bits for PCH ports */
1927 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1928 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1929
1930 /* Workaround: set timing override bit. */
1931 val = I915_READ(_TRANSA_CHICKEN2);
1932 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1933 I915_WRITE(_TRANSA_CHICKEN2, val);
1934
1935 val = TRANS_ENABLE;
1936 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1937
1938 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1939 PIPECONF_INTERLACED_ILK)
1940 val |= TRANS_INTERLACED;
1941 else
1942 val |= TRANS_PROGRESSIVE;
1943
1944 I915_WRITE(LPT_TRANSCONF, val);
1945 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1946 DRM_ERROR("Failed to enable PCH transcoder\n");
1947 }
1948
1949 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1950 enum pipe pipe)
1951 {
1952 struct drm_device *dev = dev_priv->dev;
1953 uint32_t reg, val;
1954
1955 /* FDI relies on the transcoder */
1956 assert_fdi_tx_disabled(dev_priv, pipe);
1957 assert_fdi_rx_disabled(dev_priv, pipe);
1958
1959 /* Ports must be off as well */
1960 assert_pch_ports_disabled(dev_priv, pipe);
1961
1962 reg = PCH_TRANSCONF(pipe);
1963 val = I915_READ(reg);
1964 val &= ~TRANS_ENABLE;
1965 I915_WRITE(reg, val);
1966 /* wait for PCH transcoder off, transcoder state */
1967 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1968 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1969
1970 if (!HAS_PCH_IBX(dev)) {
1971 /* Workaround: Clear the timing override chicken bit again. */
1972 reg = TRANS_CHICKEN2(pipe);
1973 val = I915_READ(reg);
1974 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1975 I915_WRITE(reg, val);
1976 }
1977 }
1978
1979 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1980 {
1981 u32 val;
1982
1983 val = I915_READ(LPT_TRANSCONF);
1984 val &= ~TRANS_ENABLE;
1985 I915_WRITE(LPT_TRANSCONF, val);
1986 /* wait for PCH transcoder off, transcoder state */
1987 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1988 DRM_ERROR("Failed to disable PCH transcoder\n");
1989
1990 /* Workaround: clear timing override bit. */
1991 val = I915_READ(_TRANSA_CHICKEN2);
1992 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1993 I915_WRITE(_TRANSA_CHICKEN2, val);
1994 }
1995
1996 /**
1997 * intel_enable_pipe - enable a pipe, asserting requirements
1998 * @crtc: crtc responsible for the pipe
1999 *
2000 * Enable @crtc's pipe, making sure that various hardware specific requirements
2001 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2002 */
2003 static void intel_enable_pipe(struct intel_crtc *crtc)
2004 {
2005 struct drm_device *dev = crtc->base.dev;
2006 struct drm_i915_private *dev_priv = dev->dev_private;
2007 enum pipe pipe = crtc->pipe;
2008 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2009 pipe);
2010 enum pipe pch_transcoder;
2011 int reg;
2012 u32 val;
2013
2014 assert_planes_disabled(dev_priv, pipe);
2015 assert_cursor_disabled(dev_priv, pipe);
2016 assert_sprites_disabled(dev_priv, pipe);
2017
2018 if (HAS_PCH_LPT(dev_priv->dev))
2019 pch_transcoder = TRANSCODER_A;
2020 else
2021 pch_transcoder = pipe;
2022
2023 /*
2024 * A pipe without a PLL won't actually be able to drive bits from
2025 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2026 * need the check.
2027 */
2028 if (!HAS_PCH_SPLIT(dev_priv->dev))
2029 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
2030 assert_dsi_pll_enabled(dev_priv);
2031 else
2032 assert_pll_enabled(dev_priv, pipe);
2033 else {
2034 if (crtc->config.has_pch_encoder) {
2035 /* if driving the PCH, we need FDI enabled */
2036 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2037 assert_fdi_tx_pll_enabled(dev_priv,
2038 (enum pipe) cpu_transcoder);
2039 }
2040 /* FIXME: assert CPU port conditions for SNB+ */
2041 }
2042
2043 reg = PIPECONF(cpu_transcoder);
2044 val = I915_READ(reg);
2045 if (val & PIPECONF_ENABLE) {
2046 WARN_ON(!(pipe == PIPE_A &&
2047 dev_priv->quirks & QUIRK_PIPEA_FORCE));
2048 return;
2049 }
2050
2051 I915_WRITE(reg, val | PIPECONF_ENABLE);
2052 POSTING_READ(reg);
2053 }
2054
2055 /**
2056 * intel_disable_pipe - disable a pipe, asserting requirements
2057 * @dev_priv: i915 private structure
2058 * @pipe: pipe to disable
2059 *
2060 * Disable @pipe, making sure that various hardware specific requirements
2061 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
2062 *
2063 * @pipe should be %PIPE_A or %PIPE_B.
2064 *
2065 * Will wait until the pipe has shut down before returning.
2066 */
2067 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
2068 enum pipe pipe)
2069 {
2070 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2071 pipe);
2072 int reg;
2073 u32 val;
2074
2075 /*
2076 * Make sure planes won't keep trying to pump pixels to us,
2077 * or we might hang the display.
2078 */
2079 assert_planes_disabled(dev_priv, pipe);
2080 assert_cursor_disabled(dev_priv, pipe);
2081 assert_sprites_disabled(dev_priv, pipe);
2082
2083 /* Don't disable pipe A or pipe A PLLs if needed */
2084 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2085 return;
2086
2087 reg = PIPECONF(cpu_transcoder);
2088 val = I915_READ(reg);
2089 if ((val & PIPECONF_ENABLE) == 0)
2090 return;
2091
2092 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
2093 intel_wait_for_pipe_off(dev_priv->dev, pipe);
2094 }
2095
2096 /*
2097 * Plane regs are double buffered, going from enabled->disabled needs a
2098 * trigger in order to latch. The display address reg provides this.
2099 */
2100 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2101 enum plane plane)
2102 {
2103 struct drm_device *dev = dev_priv->dev;
2104 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2105
2106 I915_WRITE(reg, I915_READ(reg));
2107 POSTING_READ(reg);
2108 }
2109
2110 /**
2111 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2112 * @dev_priv: i915 private structure
2113 * @plane: plane to enable
2114 * @pipe: pipe being fed
2115 *
2116 * Enable @plane on @pipe, making sure that @pipe is running first.
2117 */
2118 static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
2119 enum plane plane, enum pipe pipe)
2120 {
2121 struct drm_device *dev = dev_priv->dev;
2122 struct intel_crtc *intel_crtc =
2123 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2124 int reg;
2125 u32 val;
2126
2127 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2128 assert_pipe_enabled(dev_priv, pipe);
2129
2130 if (intel_crtc->primary_enabled)
2131 return;
2132
2133 intel_crtc->primary_enabled = true;
2134
2135 reg = DSPCNTR(plane);
2136 val = I915_READ(reg);
2137 WARN_ON(val & DISPLAY_PLANE_ENABLE);
2138
2139 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
2140 intel_flush_primary_plane(dev_priv, plane);
2141
2142 /*
2143 * BDW signals flip done immediately if the plane
2144 * is disabled, even if the plane enable is already
2145 * armed to occur at the next vblank :(
2146 */
2147 if (IS_BROADWELL(dev))
2148 intel_wait_for_vblank(dev, intel_crtc->pipe);
2149 }
2150
2151 /**
2152 * intel_disable_primary_hw_plane - disable the primary hardware plane
2153 * @dev_priv: i915 private structure
2154 * @plane: plane to disable
2155 * @pipe: pipe consuming the data
2156 *
2157 * Disable @plane; should be an independent operation.
2158 */
2159 static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
2160 enum plane plane, enum pipe pipe)
2161 {
2162 struct intel_crtc *intel_crtc =
2163 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2164 int reg;
2165 u32 val;
2166
2167 if (!intel_crtc->primary_enabled)
2168 return;
2169
2170 intel_crtc->primary_enabled = false;
2171
2172 reg = DSPCNTR(plane);
2173 val = I915_READ(reg);
2174 WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0);
2175
2176 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
2177 intel_flush_primary_plane(dev_priv, plane);
2178 }
2179
2180 static bool need_vtd_wa(struct drm_device *dev)
2181 {
2182 #ifdef CONFIG_INTEL_IOMMU
2183 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2184 return true;
2185 #endif
2186 return false;
2187 }
2188
2189 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2190 {
2191 int tile_height;
2192
2193 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2194 return ALIGN(height, tile_height);
2195 }
2196
2197 int
2198 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2199 struct drm_i915_gem_object *obj,
2200 struct intel_engine_cs *pipelined)
2201 {
2202 struct drm_i915_private *dev_priv = dev->dev_private;
2203 u32 alignment;
2204 int ret;
2205
2206 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2207
2208 switch (obj->tiling_mode) {
2209 case I915_TILING_NONE:
2210 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2211 alignment = 128 * 1024;
2212 else if (INTEL_INFO(dev)->gen >= 4)
2213 alignment = 4 * 1024;
2214 else
2215 alignment = 64 * 1024;
2216 break;
2217 case I915_TILING_X:
2218 /* pin() will align the object as required by fence */
2219 alignment = 0;
2220 break;
2221 case I915_TILING_Y:
2222 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2223 return -EINVAL;
2224 default:
2225 BUG();
2226 }
2227
2228 /* Note that the w/a also requires 64 PTE of padding following the
2229 * bo. We currently fill all unused PTE with the shadow page and so
2230 * we should always have valid PTE following the scanout preventing
2231 * the VT-d warning.
2232 */
2233 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2234 alignment = 256 * 1024;
2235
2236 dev_priv->mm.interruptible = false;
2237 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2238 if (ret)
2239 goto err_interruptible;
2240
2241 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2242 * fence, whereas 965+ only requires a fence if using
2243 * framebuffer compression. For simplicity, we always install
2244 * a fence as the cost is not that onerous.
2245 */
2246 ret = i915_gem_object_get_fence(obj);
2247 if (ret)
2248 goto err_unpin;
2249
2250 i915_gem_object_pin_fence(obj);
2251
2252 dev_priv->mm.interruptible = true;
2253 return 0;
2254
2255 err_unpin:
2256 i915_gem_object_unpin_from_display_plane(obj);
2257 err_interruptible:
2258 dev_priv->mm.interruptible = true;
2259 return ret;
2260 }
2261
2262 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2263 {
2264 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2265
2266 i915_gem_object_unpin_fence(obj);
2267 i915_gem_object_unpin_from_display_plane(obj);
2268 }
2269
2270 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2271 * is assumed to be a power-of-two. */
2272 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2273 unsigned int tiling_mode,
2274 unsigned int cpp,
2275 unsigned int pitch)
2276 {
2277 if (tiling_mode != I915_TILING_NONE) {
2278 unsigned int tile_rows, tiles;
2279
2280 tile_rows = *y / 8;
2281 *y %= 8;
2282
2283 tiles = *x / (512/cpp);
2284 *x %= 512/cpp;
2285
2286 return tile_rows * pitch * 8 + tiles * 4096;
2287 } else {
2288 unsigned int offset;
2289
2290 offset = *y * pitch + *x * cpp;
2291 *y = 0;
2292 *x = (offset & 4095) / cpp;
2293 return offset & -4096;
2294 }
2295 }
2296
2297 int intel_format_to_fourcc(int format)
2298 {
2299 switch (format) {
2300 case DISPPLANE_8BPP:
2301 return DRM_FORMAT_C8;
2302 case DISPPLANE_BGRX555:
2303 return DRM_FORMAT_XRGB1555;
2304 case DISPPLANE_BGRX565:
2305 return DRM_FORMAT_RGB565;
2306 default:
2307 case DISPPLANE_BGRX888:
2308 return DRM_FORMAT_XRGB8888;
2309 case DISPPLANE_RGBX888:
2310 return DRM_FORMAT_XBGR8888;
2311 case DISPPLANE_BGRX101010:
2312 return DRM_FORMAT_XRGB2101010;
2313 case DISPPLANE_RGBX101010:
2314 return DRM_FORMAT_XBGR2101010;
2315 }
2316 }
2317
2318 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2319 struct intel_plane_config *plane_config)
2320 {
2321 struct drm_device *dev = crtc->base.dev;
2322 struct drm_i915_gem_object *obj = NULL;
2323 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2324 u32 base = plane_config->base;
2325
2326 if (plane_config->size == 0)
2327 return false;
2328
2329 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2330 plane_config->size);
2331 if (!obj)
2332 return false;
2333
2334 if (plane_config->tiled) {
2335 obj->tiling_mode = I915_TILING_X;
2336 obj->stride = crtc->base.primary->fb->pitches[0];
2337 }
2338
2339 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2340 mode_cmd.width = crtc->base.primary->fb->width;
2341 mode_cmd.height = crtc->base.primary->fb->height;
2342 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2343
2344 mutex_lock(&dev->struct_mutex);
2345
2346 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2347 &mode_cmd, obj)) {
2348 DRM_DEBUG_KMS("intel fb init failed\n");
2349 goto out_unref_obj;
2350 }
2351
2352 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2353 mutex_unlock(&dev->struct_mutex);
2354
2355 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2356 return true;
2357
2358 out_unref_obj:
2359 drm_gem_object_unreference(&obj->base);
2360 mutex_unlock(&dev->struct_mutex);
2361 return false;
2362 }
2363
2364 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2365 struct intel_plane_config *plane_config)
2366 {
2367 struct drm_device *dev = intel_crtc->base.dev;
2368 struct drm_crtc *c;
2369 struct intel_crtc *i;
2370 struct drm_i915_gem_object *obj;
2371
2372 if (!intel_crtc->base.primary->fb)
2373 return;
2374
2375 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2376 return;
2377
2378 kfree(intel_crtc->base.primary->fb);
2379 intel_crtc->base.primary->fb = NULL;
2380
2381 /*
2382 * Failed to alloc the obj, check to see if we should share
2383 * an fb with another CRTC instead
2384 */
2385 for_each_crtc(dev, c) {
2386 i = to_intel_crtc(c);
2387
2388 if (c == &intel_crtc->base)
2389 continue;
2390
2391 if (!i->active)
2392 continue;
2393
2394 obj = intel_fb_obj(c->primary->fb);
2395 if (obj == NULL)
2396 continue;
2397
2398 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2399 drm_framebuffer_reference(c->primary->fb);
2400 intel_crtc->base.primary->fb = c->primary->fb;
2401 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2402 break;
2403 }
2404 }
2405 }
2406
2407 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2408 struct drm_framebuffer *fb,
2409 int x, int y)
2410 {
2411 struct drm_device *dev = crtc->dev;
2412 struct drm_i915_private *dev_priv = dev->dev_private;
2413 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2414 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2415 int plane = intel_crtc->plane;
2416 unsigned long linear_offset;
2417 u32 dspcntr;
2418 u32 reg;
2419
2420 reg = DSPCNTR(plane);
2421 dspcntr = I915_READ(reg);
2422 /* Mask out pixel format bits in case we change it */
2423 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2424 switch (fb->pixel_format) {
2425 case DRM_FORMAT_C8:
2426 dspcntr |= DISPPLANE_8BPP;
2427 break;
2428 case DRM_FORMAT_XRGB1555:
2429 case DRM_FORMAT_ARGB1555:
2430 dspcntr |= DISPPLANE_BGRX555;
2431 break;
2432 case DRM_FORMAT_RGB565:
2433 dspcntr |= DISPPLANE_BGRX565;
2434 break;
2435 case DRM_FORMAT_XRGB8888:
2436 case DRM_FORMAT_ARGB8888:
2437 dspcntr |= DISPPLANE_BGRX888;
2438 break;
2439 case DRM_FORMAT_XBGR8888:
2440 case DRM_FORMAT_ABGR8888:
2441 dspcntr |= DISPPLANE_RGBX888;
2442 break;
2443 case DRM_FORMAT_XRGB2101010:
2444 case DRM_FORMAT_ARGB2101010:
2445 dspcntr |= DISPPLANE_BGRX101010;
2446 break;
2447 case DRM_FORMAT_XBGR2101010:
2448 case DRM_FORMAT_ABGR2101010:
2449 dspcntr |= DISPPLANE_RGBX101010;
2450 break;
2451 default:
2452 BUG();
2453 }
2454
2455 if (INTEL_INFO(dev)->gen >= 4) {
2456 if (obj->tiling_mode != I915_TILING_NONE)
2457 dspcntr |= DISPPLANE_TILED;
2458 else
2459 dspcntr &= ~DISPPLANE_TILED;
2460 }
2461
2462 if (IS_G4X(dev))
2463 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2464
2465 I915_WRITE(reg, dspcntr);
2466
2467 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2468
2469 if (INTEL_INFO(dev)->gen >= 4) {
2470 intel_crtc->dspaddr_offset =
2471 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2472 fb->bits_per_pixel / 8,
2473 fb->pitches[0]);
2474 linear_offset -= intel_crtc->dspaddr_offset;
2475 } else {
2476 intel_crtc->dspaddr_offset = linear_offset;
2477 }
2478
2479 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2480 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2481 fb->pitches[0]);
2482 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2483 if (INTEL_INFO(dev)->gen >= 4) {
2484 I915_WRITE(DSPSURF(plane),
2485 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2486 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2487 I915_WRITE(DSPLINOFF(plane), linear_offset);
2488 } else
2489 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2490 POSTING_READ(reg);
2491 }
2492
2493 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2494 struct drm_framebuffer *fb,
2495 int x, int y)
2496 {
2497 struct drm_device *dev = crtc->dev;
2498 struct drm_i915_private *dev_priv = dev->dev_private;
2499 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2500 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2501 int plane = intel_crtc->plane;
2502 unsigned long linear_offset;
2503 u32 dspcntr;
2504 u32 reg;
2505
2506 reg = DSPCNTR(plane);
2507 dspcntr = I915_READ(reg);
2508 /* Mask out pixel format bits in case we change it */
2509 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2510 switch (fb->pixel_format) {
2511 case DRM_FORMAT_C8:
2512 dspcntr |= DISPPLANE_8BPP;
2513 break;
2514 case DRM_FORMAT_RGB565:
2515 dspcntr |= DISPPLANE_BGRX565;
2516 break;
2517 case DRM_FORMAT_XRGB8888:
2518 case DRM_FORMAT_ARGB8888:
2519 dspcntr |= DISPPLANE_BGRX888;
2520 break;
2521 case DRM_FORMAT_XBGR8888:
2522 case DRM_FORMAT_ABGR8888:
2523 dspcntr |= DISPPLANE_RGBX888;
2524 break;
2525 case DRM_FORMAT_XRGB2101010:
2526 case DRM_FORMAT_ARGB2101010:
2527 dspcntr |= DISPPLANE_BGRX101010;
2528 break;
2529 case DRM_FORMAT_XBGR2101010:
2530 case DRM_FORMAT_ABGR2101010:
2531 dspcntr |= DISPPLANE_RGBX101010;
2532 break;
2533 default:
2534 BUG();
2535 }
2536
2537 if (obj->tiling_mode != I915_TILING_NONE)
2538 dspcntr |= DISPPLANE_TILED;
2539 else
2540 dspcntr &= ~DISPPLANE_TILED;
2541
2542 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2543 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2544 else
2545 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2546
2547 I915_WRITE(reg, dspcntr);
2548
2549 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2550 intel_crtc->dspaddr_offset =
2551 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2552 fb->bits_per_pixel / 8,
2553 fb->pitches[0]);
2554 linear_offset -= intel_crtc->dspaddr_offset;
2555
2556 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2557 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2558 fb->pitches[0]);
2559 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2560 I915_WRITE(DSPSURF(plane),
2561 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2562 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2563 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2564 } else {
2565 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2566 I915_WRITE(DSPLINOFF(plane), linear_offset);
2567 }
2568 POSTING_READ(reg);
2569 }
2570
2571 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2572 static int
2573 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2574 int x, int y, enum mode_set_atomic state)
2575 {
2576 struct drm_device *dev = crtc->dev;
2577 struct drm_i915_private *dev_priv = dev->dev_private;
2578
2579 if (dev_priv->display.disable_fbc)
2580 dev_priv->display.disable_fbc(dev);
2581 intel_increase_pllclock(dev, to_intel_crtc(crtc)->pipe);
2582
2583 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2584
2585 return 0;
2586 }
2587
2588 void intel_display_handle_reset(struct drm_device *dev)
2589 {
2590 struct drm_i915_private *dev_priv = dev->dev_private;
2591 struct drm_crtc *crtc;
2592
2593 /*
2594 * Flips in the rings have been nuked by the reset,
2595 * so complete all pending flips so that user space
2596 * will get its events and not get stuck.
2597 *
2598 * Also update the base address of all primary
2599 * planes to the the last fb to make sure we're
2600 * showing the correct fb after a reset.
2601 *
2602 * Need to make two loops over the crtcs so that we
2603 * don't try to grab a crtc mutex before the
2604 * pending_flip_queue really got woken up.
2605 */
2606
2607 for_each_crtc(dev, crtc) {
2608 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2609 enum plane plane = intel_crtc->plane;
2610
2611 intel_prepare_page_flip(dev, plane);
2612 intel_finish_page_flip_plane(dev, plane);
2613 }
2614
2615 for_each_crtc(dev, crtc) {
2616 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2617
2618 drm_modeset_lock(&crtc->mutex, NULL);
2619 /*
2620 * FIXME: Once we have proper support for primary planes (and
2621 * disabling them without disabling the entire crtc) allow again
2622 * a NULL crtc->primary->fb.
2623 */
2624 if (intel_crtc->active && crtc->primary->fb)
2625 dev_priv->display.update_primary_plane(crtc,
2626 crtc->primary->fb,
2627 crtc->x,
2628 crtc->y);
2629 drm_modeset_unlock(&crtc->mutex);
2630 }
2631 }
2632
2633 static int
2634 intel_finish_fb(struct drm_framebuffer *old_fb)
2635 {
2636 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2637 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2638 bool was_interruptible = dev_priv->mm.interruptible;
2639 int ret;
2640
2641 /* Big Hammer, we also need to ensure that any pending
2642 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2643 * current scanout is retired before unpinning the old
2644 * framebuffer.
2645 *
2646 * This should only fail upon a hung GPU, in which case we
2647 * can safely continue.
2648 */
2649 dev_priv->mm.interruptible = false;
2650 ret = i915_gem_object_finish_gpu(obj);
2651 dev_priv->mm.interruptible = was_interruptible;
2652
2653 return ret;
2654 }
2655
2656 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2657 {
2658 struct drm_device *dev = crtc->dev;
2659 struct drm_i915_private *dev_priv = dev->dev_private;
2660 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2661 unsigned long flags;
2662 bool pending;
2663
2664 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2665 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2666 return false;
2667
2668 spin_lock_irqsave(&dev->event_lock, flags);
2669 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2670 spin_unlock_irqrestore(&dev->event_lock, flags);
2671
2672 return pending;
2673 }
2674
2675 static int
2676 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2677 struct drm_framebuffer *fb)
2678 {
2679 struct drm_device *dev = crtc->dev;
2680 struct drm_i915_private *dev_priv = dev->dev_private;
2681 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2682 enum pipe pipe = intel_crtc->pipe;
2683 struct drm_framebuffer *old_fb = crtc->primary->fb;
2684 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2685 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
2686 int ret;
2687
2688 if (intel_crtc_has_pending_flip(crtc)) {
2689 DRM_ERROR("pipe is still busy with an old pageflip\n");
2690 return -EBUSY;
2691 }
2692
2693 /* no fb bound */
2694 if (!fb) {
2695 DRM_ERROR("No FB bound\n");
2696 return 0;
2697 }
2698
2699 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2700 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2701 plane_name(intel_crtc->plane),
2702 INTEL_INFO(dev)->num_pipes);
2703 return -EINVAL;
2704 }
2705
2706 mutex_lock(&dev->struct_mutex);
2707 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
2708 if (ret == 0)
2709 i915_gem_track_fb(old_obj, obj,
2710 INTEL_FRONTBUFFER_PRIMARY(pipe));
2711 mutex_unlock(&dev->struct_mutex);
2712 if (ret != 0) {
2713 DRM_ERROR("pin & fence failed\n");
2714 return ret;
2715 }
2716
2717 /*
2718 * Update pipe size and adjust fitter if needed: the reason for this is
2719 * that in compute_mode_changes we check the native mode (not the pfit
2720 * mode) to see if we can flip rather than do a full mode set. In the
2721 * fastboot case, we'll flip, but if we don't update the pipesrc and
2722 * pfit state, we'll end up with a big fb scanned out into the wrong
2723 * sized surface.
2724 *
2725 * To fix this properly, we need to hoist the checks up into
2726 * compute_mode_changes (or above), check the actual pfit state and
2727 * whether the platform allows pfit disable with pipe active, and only
2728 * then update the pipesrc and pfit state, even on the flip path.
2729 */
2730 if (i915.fastboot) {
2731 const struct drm_display_mode *adjusted_mode =
2732 &intel_crtc->config.adjusted_mode;
2733
2734 I915_WRITE(PIPESRC(intel_crtc->pipe),
2735 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2736 (adjusted_mode->crtc_vdisplay - 1));
2737 if (!intel_crtc->config.pch_pfit.enabled &&
2738 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2739 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2740 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2741 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2742 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2743 }
2744 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2745 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2746 }
2747
2748 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2749
2750 if (intel_crtc->active)
2751 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2752
2753 crtc->primary->fb = fb;
2754 crtc->x = x;
2755 crtc->y = y;
2756
2757 if (old_fb) {
2758 if (intel_crtc->active && old_fb != fb)
2759 intel_wait_for_vblank(dev, intel_crtc->pipe);
2760 mutex_lock(&dev->struct_mutex);
2761 intel_unpin_fb_obj(old_obj);
2762 mutex_unlock(&dev->struct_mutex);
2763 }
2764
2765 mutex_lock(&dev->struct_mutex);
2766 intel_update_fbc(dev);
2767 mutex_unlock(&dev->struct_mutex);
2768
2769 return 0;
2770 }
2771
2772 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2773 {
2774 struct drm_device *dev = crtc->dev;
2775 struct drm_i915_private *dev_priv = dev->dev_private;
2776 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2777 int pipe = intel_crtc->pipe;
2778 u32 reg, temp;
2779
2780 /* enable normal train */
2781 reg = FDI_TX_CTL(pipe);
2782 temp = I915_READ(reg);
2783 if (IS_IVYBRIDGE(dev)) {
2784 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2785 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2786 } else {
2787 temp &= ~FDI_LINK_TRAIN_NONE;
2788 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2789 }
2790 I915_WRITE(reg, temp);
2791
2792 reg = FDI_RX_CTL(pipe);
2793 temp = I915_READ(reg);
2794 if (HAS_PCH_CPT(dev)) {
2795 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2796 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2797 } else {
2798 temp &= ~FDI_LINK_TRAIN_NONE;
2799 temp |= FDI_LINK_TRAIN_NONE;
2800 }
2801 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2802
2803 /* wait one idle pattern time */
2804 POSTING_READ(reg);
2805 udelay(1000);
2806
2807 /* IVB wants error correction enabled */
2808 if (IS_IVYBRIDGE(dev))
2809 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2810 FDI_FE_ERRC_ENABLE);
2811 }
2812
2813 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2814 {
2815 return crtc->base.enabled && crtc->active &&
2816 crtc->config.has_pch_encoder;
2817 }
2818
2819 static void ivb_modeset_global_resources(struct drm_device *dev)
2820 {
2821 struct drm_i915_private *dev_priv = dev->dev_private;
2822 struct intel_crtc *pipe_B_crtc =
2823 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2824 struct intel_crtc *pipe_C_crtc =
2825 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2826 uint32_t temp;
2827
2828 /*
2829 * When everything is off disable fdi C so that we could enable fdi B
2830 * with all lanes. Note that we don't care about enabled pipes without
2831 * an enabled pch encoder.
2832 */
2833 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2834 !pipe_has_enabled_pch(pipe_C_crtc)) {
2835 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2836 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2837
2838 temp = I915_READ(SOUTH_CHICKEN1);
2839 temp &= ~FDI_BC_BIFURCATION_SELECT;
2840 DRM_DEBUG_KMS("disabling fdi C rx\n");
2841 I915_WRITE(SOUTH_CHICKEN1, temp);
2842 }
2843 }
2844
2845 /* The FDI link training functions for ILK/Ibexpeak. */
2846 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2847 {
2848 struct drm_device *dev = crtc->dev;
2849 struct drm_i915_private *dev_priv = dev->dev_private;
2850 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2851 int pipe = intel_crtc->pipe;
2852 u32 reg, temp, tries;
2853
2854 /* FDI needs bits from pipe first */
2855 assert_pipe_enabled(dev_priv, pipe);
2856
2857 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2858 for train result */
2859 reg = FDI_RX_IMR(pipe);
2860 temp = I915_READ(reg);
2861 temp &= ~FDI_RX_SYMBOL_LOCK;
2862 temp &= ~FDI_RX_BIT_LOCK;
2863 I915_WRITE(reg, temp);
2864 I915_READ(reg);
2865 udelay(150);
2866
2867 /* enable CPU FDI TX and PCH FDI RX */
2868 reg = FDI_TX_CTL(pipe);
2869 temp = I915_READ(reg);
2870 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2871 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2872 temp &= ~FDI_LINK_TRAIN_NONE;
2873 temp |= FDI_LINK_TRAIN_PATTERN_1;
2874 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2875
2876 reg = FDI_RX_CTL(pipe);
2877 temp = I915_READ(reg);
2878 temp &= ~FDI_LINK_TRAIN_NONE;
2879 temp |= FDI_LINK_TRAIN_PATTERN_1;
2880 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2881
2882 POSTING_READ(reg);
2883 udelay(150);
2884
2885 /* Ironlake workaround, enable clock pointer after FDI enable*/
2886 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2887 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2888 FDI_RX_PHASE_SYNC_POINTER_EN);
2889
2890 reg = FDI_RX_IIR(pipe);
2891 for (tries = 0; tries < 5; tries++) {
2892 temp = I915_READ(reg);
2893 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2894
2895 if ((temp & FDI_RX_BIT_LOCK)) {
2896 DRM_DEBUG_KMS("FDI train 1 done.\n");
2897 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2898 break;
2899 }
2900 }
2901 if (tries == 5)
2902 DRM_ERROR("FDI train 1 fail!\n");
2903
2904 /* Train 2 */
2905 reg = FDI_TX_CTL(pipe);
2906 temp = I915_READ(reg);
2907 temp &= ~FDI_LINK_TRAIN_NONE;
2908 temp |= FDI_LINK_TRAIN_PATTERN_2;
2909 I915_WRITE(reg, temp);
2910
2911 reg = FDI_RX_CTL(pipe);
2912 temp = I915_READ(reg);
2913 temp &= ~FDI_LINK_TRAIN_NONE;
2914 temp |= FDI_LINK_TRAIN_PATTERN_2;
2915 I915_WRITE(reg, temp);
2916
2917 POSTING_READ(reg);
2918 udelay(150);
2919
2920 reg = FDI_RX_IIR(pipe);
2921 for (tries = 0; tries < 5; tries++) {
2922 temp = I915_READ(reg);
2923 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2924
2925 if (temp & FDI_RX_SYMBOL_LOCK) {
2926 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2927 DRM_DEBUG_KMS("FDI train 2 done.\n");
2928 break;
2929 }
2930 }
2931 if (tries == 5)
2932 DRM_ERROR("FDI train 2 fail!\n");
2933
2934 DRM_DEBUG_KMS("FDI train done\n");
2935
2936 }
2937
2938 static const int snb_b_fdi_train_param[] = {
2939 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2940 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2941 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2942 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2943 };
2944
2945 /* The FDI link training functions for SNB/Cougarpoint. */
2946 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2947 {
2948 struct drm_device *dev = crtc->dev;
2949 struct drm_i915_private *dev_priv = dev->dev_private;
2950 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2951 int pipe = intel_crtc->pipe;
2952 u32 reg, temp, i, retry;
2953
2954 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2955 for train result */
2956 reg = FDI_RX_IMR(pipe);
2957 temp = I915_READ(reg);
2958 temp &= ~FDI_RX_SYMBOL_LOCK;
2959 temp &= ~FDI_RX_BIT_LOCK;
2960 I915_WRITE(reg, temp);
2961
2962 POSTING_READ(reg);
2963 udelay(150);
2964
2965 /* enable CPU FDI TX and PCH FDI RX */
2966 reg = FDI_TX_CTL(pipe);
2967 temp = I915_READ(reg);
2968 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2969 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2970 temp &= ~FDI_LINK_TRAIN_NONE;
2971 temp |= FDI_LINK_TRAIN_PATTERN_1;
2972 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2973 /* SNB-B */
2974 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2975 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2976
2977 I915_WRITE(FDI_RX_MISC(pipe),
2978 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2979
2980 reg = FDI_RX_CTL(pipe);
2981 temp = I915_READ(reg);
2982 if (HAS_PCH_CPT(dev)) {
2983 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2984 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2985 } else {
2986 temp &= ~FDI_LINK_TRAIN_NONE;
2987 temp |= FDI_LINK_TRAIN_PATTERN_1;
2988 }
2989 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2990
2991 POSTING_READ(reg);
2992 udelay(150);
2993
2994 for (i = 0; i < 4; i++) {
2995 reg = FDI_TX_CTL(pipe);
2996 temp = I915_READ(reg);
2997 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2998 temp |= snb_b_fdi_train_param[i];
2999 I915_WRITE(reg, temp);
3000
3001 POSTING_READ(reg);
3002 udelay(500);
3003
3004 for (retry = 0; retry < 5; retry++) {
3005 reg = FDI_RX_IIR(pipe);
3006 temp = I915_READ(reg);
3007 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3008 if (temp & FDI_RX_BIT_LOCK) {
3009 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3010 DRM_DEBUG_KMS("FDI train 1 done.\n");
3011 break;
3012 }
3013 udelay(50);
3014 }
3015 if (retry < 5)
3016 break;
3017 }
3018 if (i == 4)
3019 DRM_ERROR("FDI train 1 fail!\n");
3020
3021 /* Train 2 */
3022 reg = FDI_TX_CTL(pipe);
3023 temp = I915_READ(reg);
3024 temp &= ~FDI_LINK_TRAIN_NONE;
3025 temp |= FDI_LINK_TRAIN_PATTERN_2;
3026 if (IS_GEN6(dev)) {
3027 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3028 /* SNB-B */
3029 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3030 }
3031 I915_WRITE(reg, temp);
3032
3033 reg = FDI_RX_CTL(pipe);
3034 temp = I915_READ(reg);
3035 if (HAS_PCH_CPT(dev)) {
3036 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3037 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3038 } else {
3039 temp &= ~FDI_LINK_TRAIN_NONE;
3040 temp |= FDI_LINK_TRAIN_PATTERN_2;
3041 }
3042 I915_WRITE(reg, temp);
3043
3044 POSTING_READ(reg);
3045 udelay(150);
3046
3047 for (i = 0; i < 4; i++) {
3048 reg = FDI_TX_CTL(pipe);
3049 temp = I915_READ(reg);
3050 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3051 temp |= snb_b_fdi_train_param[i];
3052 I915_WRITE(reg, temp);
3053
3054 POSTING_READ(reg);
3055 udelay(500);
3056
3057 for (retry = 0; retry < 5; retry++) {
3058 reg = FDI_RX_IIR(pipe);
3059 temp = I915_READ(reg);
3060 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3061 if (temp & FDI_RX_SYMBOL_LOCK) {
3062 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3063 DRM_DEBUG_KMS("FDI train 2 done.\n");
3064 break;
3065 }
3066 udelay(50);
3067 }
3068 if (retry < 5)
3069 break;
3070 }
3071 if (i == 4)
3072 DRM_ERROR("FDI train 2 fail!\n");
3073
3074 DRM_DEBUG_KMS("FDI train done.\n");
3075 }
3076
3077 /* Manual link training for Ivy Bridge A0 parts */
3078 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3079 {
3080 struct drm_device *dev = crtc->dev;
3081 struct drm_i915_private *dev_priv = dev->dev_private;
3082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3083 int pipe = intel_crtc->pipe;
3084 u32 reg, temp, i, j;
3085
3086 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3087 for train result */
3088 reg = FDI_RX_IMR(pipe);
3089 temp = I915_READ(reg);
3090 temp &= ~FDI_RX_SYMBOL_LOCK;
3091 temp &= ~FDI_RX_BIT_LOCK;
3092 I915_WRITE(reg, temp);
3093
3094 POSTING_READ(reg);
3095 udelay(150);
3096
3097 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3098 I915_READ(FDI_RX_IIR(pipe)));
3099
3100 /* Try each vswing and preemphasis setting twice before moving on */
3101 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3102 /* disable first in case we need to retry */
3103 reg = FDI_TX_CTL(pipe);
3104 temp = I915_READ(reg);
3105 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3106 temp &= ~FDI_TX_ENABLE;
3107 I915_WRITE(reg, temp);
3108
3109 reg = FDI_RX_CTL(pipe);
3110 temp = I915_READ(reg);
3111 temp &= ~FDI_LINK_TRAIN_AUTO;
3112 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3113 temp &= ~FDI_RX_ENABLE;
3114 I915_WRITE(reg, temp);
3115
3116 /* enable CPU FDI TX and PCH FDI RX */
3117 reg = FDI_TX_CTL(pipe);
3118 temp = I915_READ(reg);
3119 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3120 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3121 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3122 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3123 temp |= snb_b_fdi_train_param[j/2];
3124 temp |= FDI_COMPOSITE_SYNC;
3125 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3126
3127 I915_WRITE(FDI_RX_MISC(pipe),
3128 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3129
3130 reg = FDI_RX_CTL(pipe);
3131 temp = I915_READ(reg);
3132 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3133 temp |= FDI_COMPOSITE_SYNC;
3134 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3135
3136 POSTING_READ(reg);
3137 udelay(1); /* should be 0.5us */
3138
3139 for (i = 0; i < 4; i++) {
3140 reg = FDI_RX_IIR(pipe);
3141 temp = I915_READ(reg);
3142 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3143
3144 if (temp & FDI_RX_BIT_LOCK ||
3145 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3146 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3147 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3148 i);
3149 break;
3150 }
3151 udelay(1); /* should be 0.5us */
3152 }
3153 if (i == 4) {
3154 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3155 continue;
3156 }
3157
3158 /* Train 2 */
3159 reg = FDI_TX_CTL(pipe);
3160 temp = I915_READ(reg);
3161 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3162 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3163 I915_WRITE(reg, temp);
3164
3165 reg = FDI_RX_CTL(pipe);
3166 temp = I915_READ(reg);
3167 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3168 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3169 I915_WRITE(reg, temp);
3170
3171 POSTING_READ(reg);
3172 udelay(2); /* should be 1.5us */
3173
3174 for (i = 0; i < 4; i++) {
3175 reg = FDI_RX_IIR(pipe);
3176 temp = I915_READ(reg);
3177 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3178
3179 if (temp & FDI_RX_SYMBOL_LOCK ||
3180 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3181 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3182 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3183 i);
3184 goto train_done;
3185 }
3186 udelay(2); /* should be 1.5us */
3187 }
3188 if (i == 4)
3189 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3190 }
3191
3192 train_done:
3193 DRM_DEBUG_KMS("FDI train done.\n");
3194 }
3195
3196 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3197 {
3198 struct drm_device *dev = intel_crtc->base.dev;
3199 struct drm_i915_private *dev_priv = dev->dev_private;
3200 int pipe = intel_crtc->pipe;
3201 u32 reg, temp;
3202
3203
3204 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3205 reg = FDI_RX_CTL(pipe);
3206 temp = I915_READ(reg);
3207 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3208 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3209 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3210 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3211
3212 POSTING_READ(reg);
3213 udelay(200);
3214
3215 /* Switch from Rawclk to PCDclk */
3216 temp = I915_READ(reg);
3217 I915_WRITE(reg, temp | FDI_PCDCLK);
3218
3219 POSTING_READ(reg);
3220 udelay(200);
3221
3222 /* Enable CPU FDI TX PLL, always on for Ironlake */
3223 reg = FDI_TX_CTL(pipe);
3224 temp = I915_READ(reg);
3225 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3226 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3227
3228 POSTING_READ(reg);
3229 udelay(100);
3230 }
3231 }
3232
3233 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3234 {
3235 struct drm_device *dev = intel_crtc->base.dev;
3236 struct drm_i915_private *dev_priv = dev->dev_private;
3237 int pipe = intel_crtc->pipe;
3238 u32 reg, temp;
3239
3240 /* Switch from PCDclk to Rawclk */
3241 reg = FDI_RX_CTL(pipe);
3242 temp = I915_READ(reg);
3243 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3244
3245 /* Disable CPU FDI TX PLL */
3246 reg = FDI_TX_CTL(pipe);
3247 temp = I915_READ(reg);
3248 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3249
3250 POSTING_READ(reg);
3251 udelay(100);
3252
3253 reg = FDI_RX_CTL(pipe);
3254 temp = I915_READ(reg);
3255 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3256
3257 /* Wait for the clocks to turn off. */
3258 POSTING_READ(reg);
3259 udelay(100);
3260 }
3261
3262 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3263 {
3264 struct drm_device *dev = crtc->dev;
3265 struct drm_i915_private *dev_priv = dev->dev_private;
3266 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3267 int pipe = intel_crtc->pipe;
3268 u32 reg, temp;
3269
3270 /* disable CPU FDI tx and PCH FDI rx */
3271 reg = FDI_TX_CTL(pipe);
3272 temp = I915_READ(reg);
3273 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3274 POSTING_READ(reg);
3275
3276 reg = FDI_RX_CTL(pipe);
3277 temp = I915_READ(reg);
3278 temp &= ~(0x7 << 16);
3279 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3280 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3281
3282 POSTING_READ(reg);
3283 udelay(100);
3284
3285 /* Ironlake workaround, disable clock pointer after downing FDI */
3286 if (HAS_PCH_IBX(dev))
3287 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3288
3289 /* still set train pattern 1 */
3290 reg = FDI_TX_CTL(pipe);
3291 temp = I915_READ(reg);
3292 temp &= ~FDI_LINK_TRAIN_NONE;
3293 temp |= FDI_LINK_TRAIN_PATTERN_1;
3294 I915_WRITE(reg, temp);
3295
3296 reg = FDI_RX_CTL(pipe);
3297 temp = I915_READ(reg);
3298 if (HAS_PCH_CPT(dev)) {
3299 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3300 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3301 } else {
3302 temp &= ~FDI_LINK_TRAIN_NONE;
3303 temp |= FDI_LINK_TRAIN_PATTERN_1;
3304 }
3305 /* BPC in FDI rx is consistent with that in PIPECONF */
3306 temp &= ~(0x07 << 16);
3307 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3308 I915_WRITE(reg, temp);
3309
3310 POSTING_READ(reg);
3311 udelay(100);
3312 }
3313
3314 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3315 {
3316 struct intel_crtc *crtc;
3317
3318 /* Note that we don't need to be called with mode_config.lock here
3319 * as our list of CRTC objects is static for the lifetime of the
3320 * device and so cannot disappear as we iterate. Similarly, we can
3321 * happily treat the predicates as racy, atomic checks as userspace
3322 * cannot claim and pin a new fb without at least acquring the
3323 * struct_mutex and so serialising with us.
3324 */
3325 for_each_intel_crtc(dev, crtc) {
3326 if (atomic_read(&crtc->unpin_work_count) == 0)
3327 continue;
3328
3329 if (crtc->unpin_work)
3330 intel_wait_for_vblank(dev, crtc->pipe);
3331
3332 return true;
3333 }
3334
3335 return false;
3336 }
3337
3338 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3339 {
3340 struct drm_device *dev = crtc->dev;
3341 struct drm_i915_private *dev_priv = dev->dev_private;
3342
3343 if (crtc->primary->fb == NULL)
3344 return;
3345
3346 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3347
3348 WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3349 !intel_crtc_has_pending_flip(crtc),
3350 60*HZ) == 0);
3351
3352 mutex_lock(&dev->struct_mutex);
3353 intel_finish_fb(crtc->primary->fb);
3354 mutex_unlock(&dev->struct_mutex);
3355 }
3356
3357 /* Program iCLKIP clock to the desired frequency */
3358 static void lpt_program_iclkip(struct drm_crtc *crtc)
3359 {
3360 struct drm_device *dev = crtc->dev;
3361 struct drm_i915_private *dev_priv = dev->dev_private;
3362 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3363 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3364 u32 temp;
3365
3366 mutex_lock(&dev_priv->dpio_lock);
3367
3368 /* It is necessary to ungate the pixclk gate prior to programming
3369 * the divisors, and gate it back when it is done.
3370 */
3371 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3372
3373 /* Disable SSCCTL */
3374 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3375 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3376 SBI_SSCCTL_DISABLE,
3377 SBI_ICLK);
3378
3379 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3380 if (clock == 20000) {
3381 auxdiv = 1;
3382 divsel = 0x41;
3383 phaseinc = 0x20;
3384 } else {
3385 /* The iCLK virtual clock root frequency is in MHz,
3386 * but the adjusted_mode->crtc_clock in in KHz. To get the
3387 * divisors, it is necessary to divide one by another, so we
3388 * convert the virtual clock precision to KHz here for higher
3389 * precision.
3390 */
3391 u32 iclk_virtual_root_freq = 172800 * 1000;
3392 u32 iclk_pi_range = 64;
3393 u32 desired_divisor, msb_divisor_value, pi_value;
3394
3395 desired_divisor = (iclk_virtual_root_freq / clock);
3396 msb_divisor_value = desired_divisor / iclk_pi_range;
3397 pi_value = desired_divisor % iclk_pi_range;
3398
3399 auxdiv = 0;
3400 divsel = msb_divisor_value - 2;
3401 phaseinc = pi_value;
3402 }
3403
3404 /* This should not happen with any sane values */
3405 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3406 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3407 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3408 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3409
3410 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3411 clock,
3412 auxdiv,
3413 divsel,
3414 phasedir,
3415 phaseinc);
3416
3417 /* Program SSCDIVINTPHASE6 */
3418 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3419 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3420 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3421 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3422 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3423 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3424 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3425 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3426
3427 /* Program SSCAUXDIV */
3428 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3429 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3430 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3431 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3432
3433 /* Enable modulator and associated divider */
3434 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3435 temp &= ~SBI_SSCCTL_DISABLE;
3436 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3437
3438 /* Wait for initialization time */
3439 udelay(24);
3440
3441 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3442
3443 mutex_unlock(&dev_priv->dpio_lock);
3444 }
3445
3446 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3447 enum pipe pch_transcoder)
3448 {
3449 struct drm_device *dev = crtc->base.dev;
3450 struct drm_i915_private *dev_priv = dev->dev_private;
3451 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3452
3453 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3454 I915_READ(HTOTAL(cpu_transcoder)));
3455 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3456 I915_READ(HBLANK(cpu_transcoder)));
3457 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3458 I915_READ(HSYNC(cpu_transcoder)));
3459
3460 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3461 I915_READ(VTOTAL(cpu_transcoder)));
3462 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3463 I915_READ(VBLANK(cpu_transcoder)));
3464 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3465 I915_READ(VSYNC(cpu_transcoder)));
3466 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3467 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3468 }
3469
3470 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3471 {
3472 struct drm_i915_private *dev_priv = dev->dev_private;
3473 uint32_t temp;
3474
3475 temp = I915_READ(SOUTH_CHICKEN1);
3476 if (temp & FDI_BC_BIFURCATION_SELECT)
3477 return;
3478
3479 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3480 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3481
3482 temp |= FDI_BC_BIFURCATION_SELECT;
3483 DRM_DEBUG_KMS("enabling fdi C rx\n");
3484 I915_WRITE(SOUTH_CHICKEN1, temp);
3485 POSTING_READ(SOUTH_CHICKEN1);
3486 }
3487
3488 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3489 {
3490 struct drm_device *dev = intel_crtc->base.dev;
3491 struct drm_i915_private *dev_priv = dev->dev_private;
3492
3493 switch (intel_crtc->pipe) {
3494 case PIPE_A:
3495 break;
3496 case PIPE_B:
3497 if (intel_crtc->config.fdi_lanes > 2)
3498 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3499 else
3500 cpt_enable_fdi_bc_bifurcation(dev);
3501
3502 break;
3503 case PIPE_C:
3504 cpt_enable_fdi_bc_bifurcation(dev);
3505
3506 break;
3507 default:
3508 BUG();
3509 }
3510 }
3511
3512 /*
3513 * Enable PCH resources required for PCH ports:
3514 * - PCH PLLs
3515 * - FDI training & RX/TX
3516 * - update transcoder timings
3517 * - DP transcoding bits
3518 * - transcoder
3519 */
3520 static void ironlake_pch_enable(struct drm_crtc *crtc)
3521 {
3522 struct drm_device *dev = crtc->dev;
3523 struct drm_i915_private *dev_priv = dev->dev_private;
3524 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3525 int pipe = intel_crtc->pipe;
3526 u32 reg, temp;
3527
3528 assert_pch_transcoder_disabled(dev_priv, pipe);
3529
3530 if (IS_IVYBRIDGE(dev))
3531 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3532
3533 /* Write the TU size bits before fdi link training, so that error
3534 * detection works. */
3535 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3536 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3537
3538 /* For PCH output, training FDI link */
3539 dev_priv->display.fdi_link_train(crtc);
3540
3541 /* We need to program the right clock selection before writing the pixel
3542 * mutliplier into the DPLL. */
3543 if (HAS_PCH_CPT(dev)) {
3544 u32 sel;
3545
3546 temp = I915_READ(PCH_DPLL_SEL);
3547 temp |= TRANS_DPLL_ENABLE(pipe);
3548 sel = TRANS_DPLLB_SEL(pipe);
3549 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3550 temp |= sel;
3551 else
3552 temp &= ~sel;
3553 I915_WRITE(PCH_DPLL_SEL, temp);
3554 }
3555
3556 /* XXX: pch pll's can be enabled any time before we enable the PCH
3557 * transcoder, and we actually should do this to not upset any PCH
3558 * transcoder that already use the clock when we share it.
3559 *
3560 * Note that enable_shared_dpll tries to do the right thing, but
3561 * get_shared_dpll unconditionally resets the pll - we need that to have
3562 * the right LVDS enable sequence. */
3563 intel_enable_shared_dpll(intel_crtc);
3564
3565 /* set transcoder timing, panel must allow it */
3566 assert_panel_unlocked(dev_priv, pipe);
3567 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3568
3569 intel_fdi_normal_train(crtc);
3570
3571 /* For PCH DP, enable TRANS_DP_CTL */
3572 if (HAS_PCH_CPT(dev) &&
3573 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3574 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3575 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3576 reg = TRANS_DP_CTL(pipe);
3577 temp = I915_READ(reg);
3578 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3579 TRANS_DP_SYNC_MASK |
3580 TRANS_DP_BPC_MASK);
3581 temp |= (TRANS_DP_OUTPUT_ENABLE |
3582 TRANS_DP_ENH_FRAMING);
3583 temp |= bpc << 9; /* same format but at 11:9 */
3584
3585 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3586 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3587 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3588 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3589
3590 switch (intel_trans_dp_port_sel(crtc)) {
3591 case PCH_DP_B:
3592 temp |= TRANS_DP_PORT_SEL_B;
3593 break;
3594 case PCH_DP_C:
3595 temp |= TRANS_DP_PORT_SEL_C;
3596 break;
3597 case PCH_DP_D:
3598 temp |= TRANS_DP_PORT_SEL_D;
3599 break;
3600 default:
3601 BUG();
3602 }
3603
3604 I915_WRITE(reg, temp);
3605 }
3606
3607 ironlake_enable_pch_transcoder(dev_priv, pipe);
3608 }
3609
3610 static void lpt_pch_enable(struct drm_crtc *crtc)
3611 {
3612 struct drm_device *dev = crtc->dev;
3613 struct drm_i915_private *dev_priv = dev->dev_private;
3614 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3615 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3616
3617 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3618
3619 lpt_program_iclkip(crtc);
3620
3621 /* Set transcoder timing. */
3622 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3623
3624 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3625 }
3626
3627 void intel_put_shared_dpll(struct intel_crtc *crtc)
3628 {
3629 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3630
3631 if (pll == NULL)
3632 return;
3633
3634 if (pll->refcount == 0) {
3635 WARN(1, "bad %s refcount\n", pll->name);
3636 return;
3637 }
3638
3639 if (--pll->refcount == 0) {
3640 WARN_ON(pll->on);
3641 WARN_ON(pll->active);
3642 }
3643
3644 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3645 }
3646
3647 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3648 {
3649 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3650 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3651 enum intel_dpll_id i;
3652
3653 if (pll) {
3654 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3655 crtc->base.base.id, pll->name);
3656 intel_put_shared_dpll(crtc);
3657 }
3658
3659 if (HAS_PCH_IBX(dev_priv->dev)) {
3660 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3661 i = (enum intel_dpll_id) crtc->pipe;
3662 pll = &dev_priv->shared_dplls[i];
3663
3664 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3665 crtc->base.base.id, pll->name);
3666
3667 WARN_ON(pll->refcount);
3668
3669 goto found;
3670 }
3671
3672 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3673 pll = &dev_priv->shared_dplls[i];
3674
3675 /* Only want to check enabled timings first */
3676 if (pll->refcount == 0)
3677 continue;
3678
3679 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3680 sizeof(pll->hw_state)) == 0) {
3681 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3682 crtc->base.base.id,
3683 pll->name, pll->refcount, pll->active);
3684
3685 goto found;
3686 }
3687 }
3688
3689 /* Ok no matching timings, maybe there's a free one? */
3690 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3691 pll = &dev_priv->shared_dplls[i];
3692 if (pll->refcount == 0) {
3693 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3694 crtc->base.base.id, pll->name);
3695 goto found;
3696 }
3697 }
3698
3699 return NULL;
3700
3701 found:
3702 if (pll->refcount == 0)
3703 pll->hw_state = crtc->config.dpll_hw_state;
3704
3705 crtc->config.shared_dpll = i;
3706 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3707 pipe_name(crtc->pipe));
3708
3709 pll->refcount++;
3710
3711 return pll;
3712 }
3713
3714 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3715 {
3716 struct drm_i915_private *dev_priv = dev->dev_private;
3717 int dslreg = PIPEDSL(pipe);
3718 u32 temp;
3719
3720 temp = I915_READ(dslreg);
3721 udelay(500);
3722 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3723 if (wait_for(I915_READ(dslreg) != temp, 5))
3724 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3725 }
3726 }
3727
3728 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3729 {
3730 struct drm_device *dev = crtc->base.dev;
3731 struct drm_i915_private *dev_priv = dev->dev_private;
3732 int pipe = crtc->pipe;
3733
3734 if (crtc->config.pch_pfit.enabled) {
3735 /* Force use of hard-coded filter coefficients
3736 * as some pre-programmed values are broken,
3737 * e.g. x201.
3738 */
3739 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3740 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3741 PF_PIPE_SEL_IVB(pipe));
3742 else
3743 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3744 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3745 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3746 }
3747 }
3748
3749 static void intel_enable_planes(struct drm_crtc *crtc)
3750 {
3751 struct drm_device *dev = crtc->dev;
3752 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3753 struct drm_plane *plane;
3754 struct intel_plane *intel_plane;
3755
3756 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3757 intel_plane = to_intel_plane(plane);
3758 if (intel_plane->pipe == pipe)
3759 intel_plane_restore(&intel_plane->base);
3760 }
3761 }
3762
3763 static void intel_disable_planes(struct drm_crtc *crtc)
3764 {
3765 struct drm_device *dev = crtc->dev;
3766 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3767 struct drm_plane *plane;
3768 struct intel_plane *intel_plane;
3769
3770 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3771 intel_plane = to_intel_plane(plane);
3772 if (intel_plane->pipe == pipe)
3773 intel_plane_disable(&intel_plane->base);
3774 }
3775 }
3776
3777 void hsw_enable_ips(struct intel_crtc *crtc)
3778 {
3779 struct drm_device *dev = crtc->base.dev;
3780 struct drm_i915_private *dev_priv = dev->dev_private;
3781
3782 if (!crtc->config.ips_enabled)
3783 return;
3784
3785 /* We can only enable IPS after we enable a plane and wait for a vblank */
3786 intel_wait_for_vblank(dev, crtc->pipe);
3787
3788 assert_plane_enabled(dev_priv, crtc->plane);
3789 if (IS_BROADWELL(dev)) {
3790 mutex_lock(&dev_priv->rps.hw_lock);
3791 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3792 mutex_unlock(&dev_priv->rps.hw_lock);
3793 /* Quoting Art Runyan: "its not safe to expect any particular
3794 * value in IPS_CTL bit 31 after enabling IPS through the
3795 * mailbox." Moreover, the mailbox may return a bogus state,
3796 * so we need to just enable it and continue on.
3797 */
3798 } else {
3799 I915_WRITE(IPS_CTL, IPS_ENABLE);
3800 /* The bit only becomes 1 in the next vblank, so this wait here
3801 * is essentially intel_wait_for_vblank. If we don't have this
3802 * and don't wait for vblanks until the end of crtc_enable, then
3803 * the HW state readout code will complain that the expected
3804 * IPS_CTL value is not the one we read. */
3805 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3806 DRM_ERROR("Timed out waiting for IPS enable\n");
3807 }
3808 }
3809
3810 void hsw_disable_ips(struct intel_crtc *crtc)
3811 {
3812 struct drm_device *dev = crtc->base.dev;
3813 struct drm_i915_private *dev_priv = dev->dev_private;
3814
3815 if (!crtc->config.ips_enabled)
3816 return;
3817
3818 assert_plane_enabled(dev_priv, crtc->plane);
3819 if (IS_BROADWELL(dev)) {
3820 mutex_lock(&dev_priv->rps.hw_lock);
3821 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3822 mutex_unlock(&dev_priv->rps.hw_lock);
3823 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3824 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3825 DRM_ERROR("Timed out waiting for IPS disable\n");
3826 } else {
3827 I915_WRITE(IPS_CTL, 0);
3828 POSTING_READ(IPS_CTL);
3829 }
3830
3831 /* We need to wait for a vblank before we can disable the plane. */
3832 intel_wait_for_vblank(dev, crtc->pipe);
3833 }
3834
3835 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3836 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3837 {
3838 struct drm_device *dev = crtc->dev;
3839 struct drm_i915_private *dev_priv = dev->dev_private;
3840 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3841 enum pipe pipe = intel_crtc->pipe;
3842 int palreg = PALETTE(pipe);
3843 int i;
3844 bool reenable_ips = false;
3845
3846 /* The clocks have to be on to load the palette. */
3847 if (!crtc->enabled || !intel_crtc->active)
3848 return;
3849
3850 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3851 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3852 assert_dsi_pll_enabled(dev_priv);
3853 else
3854 assert_pll_enabled(dev_priv, pipe);
3855 }
3856
3857 /* use legacy palette for Ironlake */
3858 if (!HAS_GMCH_DISPLAY(dev))
3859 palreg = LGC_PALETTE(pipe);
3860
3861 /* Workaround : Do not read or write the pipe palette/gamma data while
3862 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3863 */
3864 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3865 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3866 GAMMA_MODE_MODE_SPLIT)) {
3867 hsw_disable_ips(intel_crtc);
3868 reenable_ips = true;
3869 }
3870
3871 for (i = 0; i < 256; i++) {
3872 I915_WRITE(palreg + 4 * i,
3873 (intel_crtc->lut_r[i] << 16) |
3874 (intel_crtc->lut_g[i] << 8) |
3875 intel_crtc->lut_b[i]);
3876 }
3877
3878 if (reenable_ips)
3879 hsw_enable_ips(intel_crtc);
3880 }
3881
3882 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3883 {
3884 if (!enable && intel_crtc->overlay) {
3885 struct drm_device *dev = intel_crtc->base.dev;
3886 struct drm_i915_private *dev_priv = dev->dev_private;
3887
3888 mutex_lock(&dev->struct_mutex);
3889 dev_priv->mm.interruptible = false;
3890 (void) intel_overlay_switch_off(intel_crtc->overlay);
3891 dev_priv->mm.interruptible = true;
3892 mutex_unlock(&dev->struct_mutex);
3893 }
3894
3895 /* Let userspace switch the overlay on again. In most cases userspace
3896 * has to recompute where to put it anyway.
3897 */
3898 }
3899
3900 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
3901 {
3902 struct drm_device *dev = crtc->dev;
3903 struct drm_i915_private *dev_priv = dev->dev_private;
3904 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3905 int pipe = intel_crtc->pipe;
3906 int plane = intel_crtc->plane;
3907
3908 drm_vblank_on(dev, pipe);
3909
3910 intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3911 intel_enable_planes(crtc);
3912 intel_crtc_update_cursor(crtc, true);
3913 intel_crtc_dpms_overlay(intel_crtc, true);
3914
3915 hsw_enable_ips(intel_crtc);
3916
3917 mutex_lock(&dev->struct_mutex);
3918 intel_update_fbc(dev);
3919 mutex_unlock(&dev->struct_mutex);
3920
3921 /*
3922 * FIXME: Once we grow proper nuclear flip support out of this we need
3923 * to compute the mask of flip planes precisely. For the time being
3924 * consider this a flip from a NULL plane.
3925 */
3926 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
3927 }
3928
3929 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
3930 {
3931 struct drm_device *dev = crtc->dev;
3932 struct drm_i915_private *dev_priv = dev->dev_private;
3933 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3934 int pipe = intel_crtc->pipe;
3935 int plane = intel_crtc->plane;
3936
3937 intel_crtc_wait_for_pending_flips(crtc);
3938
3939 if (dev_priv->fbc.plane == plane)
3940 intel_disable_fbc(dev);
3941
3942 hsw_disable_ips(intel_crtc);
3943
3944 intel_crtc_dpms_overlay(intel_crtc, false);
3945 intel_crtc_update_cursor(crtc, false);
3946 intel_disable_planes(crtc);
3947 intel_disable_primary_hw_plane(dev_priv, plane, pipe);
3948
3949 /*
3950 * FIXME: Once we grow proper nuclear flip support out of this we need
3951 * to compute the mask of flip planes precisely. For the time being
3952 * consider this a flip to a NULL plane.
3953 */
3954 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
3955
3956 drm_vblank_off(dev, pipe);
3957 }
3958
3959 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3960 {
3961 struct drm_device *dev = crtc->dev;
3962 struct drm_i915_private *dev_priv = dev->dev_private;
3963 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3964 struct intel_encoder *encoder;
3965 int pipe = intel_crtc->pipe;
3966 enum plane plane = intel_crtc->plane;
3967
3968 WARN_ON(!crtc->enabled);
3969
3970 if (intel_crtc->active)
3971 return;
3972
3973 if (intel_crtc->config.has_pch_encoder)
3974 intel_prepare_shared_dpll(intel_crtc);
3975
3976 if (intel_crtc->config.has_dp_encoder)
3977 intel_dp_set_m_n(intel_crtc);
3978
3979 intel_set_pipe_timings(intel_crtc);
3980
3981 if (intel_crtc->config.has_pch_encoder) {
3982 intel_cpu_transcoder_set_m_n(intel_crtc,
3983 &intel_crtc->config.fdi_m_n, NULL);
3984 }
3985
3986 ironlake_set_pipeconf(crtc);
3987
3988 /* Set up the display plane register */
3989 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
3990 POSTING_READ(DSPCNTR(plane));
3991
3992 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
3993 crtc->x, crtc->y);
3994
3995 intel_crtc->active = true;
3996
3997 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3998 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3999
4000 for_each_encoder_on_crtc(dev, crtc, encoder)
4001 if (encoder->pre_enable)
4002 encoder->pre_enable(encoder);
4003
4004 if (intel_crtc->config.has_pch_encoder) {
4005 /* Note: FDI PLL enabling _must_ be done before we enable the
4006 * cpu pipes, hence this is separate from all the other fdi/pch
4007 * enabling. */
4008 ironlake_fdi_pll_enable(intel_crtc);
4009 } else {
4010 assert_fdi_tx_disabled(dev_priv, pipe);
4011 assert_fdi_rx_disabled(dev_priv, pipe);
4012 }
4013
4014 ironlake_pfit_enable(intel_crtc);
4015
4016 /*
4017 * On ILK+ LUT must be loaded before the pipe is running but with
4018 * clocks enabled
4019 */
4020 intel_crtc_load_lut(crtc);
4021
4022 intel_update_watermarks(crtc);
4023 intel_enable_pipe(intel_crtc);
4024
4025 if (intel_crtc->config.has_pch_encoder)
4026 ironlake_pch_enable(crtc);
4027
4028 for_each_encoder_on_crtc(dev, crtc, encoder)
4029 encoder->enable(encoder);
4030
4031 if (HAS_PCH_CPT(dev))
4032 cpt_verify_modeset(dev, intel_crtc->pipe);
4033
4034 intel_crtc_enable_planes(crtc);
4035 }
4036
4037 /* IPS only exists on ULT machines and is tied to pipe A. */
4038 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4039 {
4040 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4041 }
4042
4043 /*
4044 * This implements the workaround described in the "notes" section of the mode
4045 * set sequence documentation. When going from no pipes or single pipe to
4046 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4047 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4048 */
4049 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4050 {
4051 struct drm_device *dev = crtc->base.dev;
4052 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4053
4054 /* We want to get the other_active_crtc only if there's only 1 other
4055 * active crtc. */
4056 for_each_intel_crtc(dev, crtc_it) {
4057 if (!crtc_it->active || crtc_it == crtc)
4058 continue;
4059
4060 if (other_active_crtc)
4061 return;
4062
4063 other_active_crtc = crtc_it;
4064 }
4065 if (!other_active_crtc)
4066 return;
4067
4068 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4069 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4070 }
4071
4072 static void haswell_crtc_enable(struct drm_crtc *crtc)
4073 {
4074 struct drm_device *dev = crtc->dev;
4075 struct drm_i915_private *dev_priv = dev->dev_private;
4076 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4077 struct intel_encoder *encoder;
4078 int pipe = intel_crtc->pipe;
4079 enum plane plane = intel_crtc->plane;
4080
4081 WARN_ON(!crtc->enabled);
4082
4083 if (intel_crtc->active)
4084 return;
4085
4086 if (intel_crtc_to_shared_dpll(intel_crtc))
4087 intel_enable_shared_dpll(intel_crtc);
4088
4089 if (intel_crtc->config.has_dp_encoder)
4090 intel_dp_set_m_n(intel_crtc);
4091
4092 intel_set_pipe_timings(intel_crtc);
4093
4094 if (intel_crtc->config.has_pch_encoder) {
4095 intel_cpu_transcoder_set_m_n(intel_crtc,
4096 &intel_crtc->config.fdi_m_n, NULL);
4097 }
4098
4099 haswell_set_pipeconf(crtc);
4100
4101 intel_set_pipe_csc(crtc);
4102
4103 /* Set up the display plane register */
4104 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
4105 POSTING_READ(DSPCNTR(plane));
4106
4107 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4108 crtc->x, crtc->y);
4109
4110 intel_crtc->active = true;
4111
4112 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4113 for_each_encoder_on_crtc(dev, crtc, encoder)
4114 if (encoder->pre_enable)
4115 encoder->pre_enable(encoder);
4116
4117 if (intel_crtc->config.has_pch_encoder) {
4118 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4119 dev_priv->display.fdi_link_train(crtc);
4120 }
4121
4122 intel_ddi_enable_pipe_clock(intel_crtc);
4123
4124 ironlake_pfit_enable(intel_crtc);
4125
4126 /*
4127 * On ILK+ LUT must be loaded before the pipe is running but with
4128 * clocks enabled
4129 */
4130 intel_crtc_load_lut(crtc);
4131
4132 intel_ddi_set_pipe_settings(crtc);
4133 intel_ddi_enable_transcoder_func(crtc);
4134
4135 intel_update_watermarks(crtc);
4136 intel_enable_pipe(intel_crtc);
4137
4138 if (intel_crtc->config.has_pch_encoder)
4139 lpt_pch_enable(crtc);
4140
4141 if (intel_crtc->config.dp_encoder_is_mst)
4142 intel_ddi_set_vc_payload_alloc(crtc, true);
4143
4144 for_each_encoder_on_crtc(dev, crtc, encoder) {
4145 encoder->enable(encoder);
4146 intel_opregion_notify_encoder(encoder, true);
4147 }
4148
4149 /* If we change the relative order between pipe/planes enabling, we need
4150 * to change the workaround. */
4151 haswell_mode_set_planes_workaround(intel_crtc);
4152 intel_crtc_enable_planes(crtc);
4153 }
4154
4155 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4156 {
4157 struct drm_device *dev = crtc->base.dev;
4158 struct drm_i915_private *dev_priv = dev->dev_private;
4159 int pipe = crtc->pipe;
4160
4161 /* To avoid upsetting the power well on haswell only disable the pfit if
4162 * it's in use. The hw state code will make sure we get this right. */
4163 if (crtc->config.pch_pfit.enabled) {
4164 I915_WRITE(PF_CTL(pipe), 0);
4165 I915_WRITE(PF_WIN_POS(pipe), 0);
4166 I915_WRITE(PF_WIN_SZ(pipe), 0);
4167 }
4168 }
4169
4170 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4171 {
4172 struct drm_device *dev = crtc->dev;
4173 struct drm_i915_private *dev_priv = dev->dev_private;
4174 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4175 struct intel_encoder *encoder;
4176 int pipe = intel_crtc->pipe;
4177 u32 reg, temp;
4178
4179 if (!intel_crtc->active)
4180 return;
4181
4182 intel_crtc_disable_planes(crtc);
4183
4184 for_each_encoder_on_crtc(dev, crtc, encoder)
4185 encoder->disable(encoder);
4186
4187 if (intel_crtc->config.has_pch_encoder)
4188 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4189
4190 intel_disable_pipe(dev_priv, pipe);
4191
4192 if (intel_crtc->config.dp_encoder_is_mst)
4193 intel_ddi_set_vc_payload_alloc(crtc, false);
4194
4195 ironlake_pfit_disable(intel_crtc);
4196
4197 for_each_encoder_on_crtc(dev, crtc, encoder)
4198 if (encoder->post_disable)
4199 encoder->post_disable(encoder);
4200
4201 if (intel_crtc->config.has_pch_encoder) {
4202 ironlake_fdi_disable(crtc);
4203
4204 ironlake_disable_pch_transcoder(dev_priv, pipe);
4205 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4206
4207 if (HAS_PCH_CPT(dev)) {
4208 /* disable TRANS_DP_CTL */
4209 reg = TRANS_DP_CTL(pipe);
4210 temp = I915_READ(reg);
4211 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4212 TRANS_DP_PORT_SEL_MASK);
4213 temp |= TRANS_DP_PORT_SEL_NONE;
4214 I915_WRITE(reg, temp);
4215
4216 /* disable DPLL_SEL */
4217 temp = I915_READ(PCH_DPLL_SEL);
4218 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4219 I915_WRITE(PCH_DPLL_SEL, temp);
4220 }
4221
4222 /* disable PCH DPLL */
4223 intel_disable_shared_dpll(intel_crtc);
4224
4225 ironlake_fdi_pll_disable(intel_crtc);
4226 }
4227
4228 intel_crtc->active = false;
4229 intel_update_watermarks(crtc);
4230
4231 mutex_lock(&dev->struct_mutex);
4232 intel_update_fbc(dev);
4233 mutex_unlock(&dev->struct_mutex);
4234 }
4235
4236 static void haswell_crtc_disable(struct drm_crtc *crtc)
4237 {
4238 struct drm_device *dev = crtc->dev;
4239 struct drm_i915_private *dev_priv = dev->dev_private;
4240 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4241 struct intel_encoder *encoder;
4242 int pipe = intel_crtc->pipe;
4243 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4244
4245 if (!intel_crtc->active)
4246 return;
4247
4248 intel_crtc_disable_planes(crtc);
4249
4250 for_each_encoder_on_crtc(dev, crtc, encoder) {
4251 intel_opregion_notify_encoder(encoder, false);
4252 encoder->disable(encoder);
4253 }
4254
4255 if (intel_crtc->config.has_pch_encoder)
4256 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4257 intel_disable_pipe(dev_priv, pipe);
4258
4259 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4260
4261 ironlake_pfit_disable(intel_crtc);
4262
4263 intel_ddi_disable_pipe_clock(intel_crtc);
4264
4265 if (intel_crtc->config.has_pch_encoder) {
4266 lpt_disable_pch_transcoder(dev_priv);
4267 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4268 intel_ddi_fdi_disable(crtc);
4269 }
4270
4271 for_each_encoder_on_crtc(dev, crtc, encoder)
4272 if (encoder->post_disable)
4273 encoder->post_disable(encoder);
4274
4275 intel_crtc->active = false;
4276 intel_update_watermarks(crtc);
4277
4278 mutex_lock(&dev->struct_mutex);
4279 intel_update_fbc(dev);
4280 mutex_unlock(&dev->struct_mutex);
4281
4282 if (intel_crtc_to_shared_dpll(intel_crtc))
4283 intel_disable_shared_dpll(intel_crtc);
4284 }
4285
4286 static void ironlake_crtc_off(struct drm_crtc *crtc)
4287 {
4288 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4289 intel_put_shared_dpll(intel_crtc);
4290 }
4291
4292
4293 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4294 {
4295 struct drm_device *dev = crtc->base.dev;
4296 struct drm_i915_private *dev_priv = dev->dev_private;
4297 struct intel_crtc_config *pipe_config = &crtc->config;
4298
4299 if (!crtc->config.gmch_pfit.control)
4300 return;
4301
4302 /*
4303 * The panel fitter should only be adjusted whilst the pipe is disabled,
4304 * according to register description and PRM.
4305 */
4306 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4307 assert_pipe_disabled(dev_priv, crtc->pipe);
4308
4309 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4310 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4311
4312 /* Border color in case we don't scale up to the full screen. Black by
4313 * default, change to something else for debugging. */
4314 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4315 }
4316
4317 static enum intel_display_power_domain port_to_power_domain(enum port port)
4318 {
4319 switch (port) {
4320 case PORT_A:
4321 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4322 case PORT_B:
4323 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4324 case PORT_C:
4325 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4326 case PORT_D:
4327 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4328 default:
4329 WARN_ON_ONCE(1);
4330 return POWER_DOMAIN_PORT_OTHER;
4331 }
4332 }
4333
4334 #define for_each_power_domain(domain, mask) \
4335 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4336 if ((1 << (domain)) & (mask))
4337
4338 enum intel_display_power_domain
4339 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4340 {
4341 struct drm_device *dev = intel_encoder->base.dev;
4342 struct intel_digital_port *intel_dig_port;
4343
4344 switch (intel_encoder->type) {
4345 case INTEL_OUTPUT_UNKNOWN:
4346 /* Only DDI platforms should ever use this output type */
4347 WARN_ON_ONCE(!HAS_DDI(dev));
4348 case INTEL_OUTPUT_DISPLAYPORT:
4349 case INTEL_OUTPUT_HDMI:
4350 case INTEL_OUTPUT_EDP:
4351 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4352 return port_to_power_domain(intel_dig_port->port);
4353 case INTEL_OUTPUT_DP_MST:
4354 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4355 return port_to_power_domain(intel_dig_port->port);
4356 case INTEL_OUTPUT_ANALOG:
4357 return POWER_DOMAIN_PORT_CRT;
4358 case INTEL_OUTPUT_DSI:
4359 return POWER_DOMAIN_PORT_DSI;
4360 default:
4361 return POWER_DOMAIN_PORT_OTHER;
4362 }
4363 }
4364
4365 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4366 {
4367 struct drm_device *dev = crtc->dev;
4368 struct intel_encoder *intel_encoder;
4369 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4370 enum pipe pipe = intel_crtc->pipe;
4371 unsigned long mask;
4372 enum transcoder transcoder;
4373
4374 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4375
4376 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4377 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4378 if (intel_crtc->config.pch_pfit.enabled ||
4379 intel_crtc->config.pch_pfit.force_thru)
4380 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4381
4382 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4383 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4384
4385 return mask;
4386 }
4387
4388 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4389 bool enable)
4390 {
4391 if (dev_priv->power_domains.init_power_on == enable)
4392 return;
4393
4394 if (enable)
4395 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4396 else
4397 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4398
4399 dev_priv->power_domains.init_power_on = enable;
4400 }
4401
4402 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4403 {
4404 struct drm_i915_private *dev_priv = dev->dev_private;
4405 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4406 struct intel_crtc *crtc;
4407
4408 /*
4409 * First get all needed power domains, then put all unneeded, to avoid
4410 * any unnecessary toggling of the power wells.
4411 */
4412 for_each_intel_crtc(dev, crtc) {
4413 enum intel_display_power_domain domain;
4414
4415 if (!crtc->base.enabled)
4416 continue;
4417
4418 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4419
4420 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4421 intel_display_power_get(dev_priv, domain);
4422 }
4423
4424 for_each_intel_crtc(dev, crtc) {
4425 enum intel_display_power_domain domain;
4426
4427 for_each_power_domain(domain, crtc->enabled_power_domains)
4428 intel_display_power_put(dev_priv, domain);
4429
4430 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4431 }
4432
4433 intel_display_set_init_power(dev_priv, false);
4434 }
4435
4436 /* returns HPLL frequency in kHz */
4437 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4438 {
4439 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4440
4441 /* Obtain SKU information */
4442 mutex_lock(&dev_priv->dpio_lock);
4443 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4444 CCK_FUSE_HPLL_FREQ_MASK;
4445 mutex_unlock(&dev_priv->dpio_lock);
4446
4447 return vco_freq[hpll_freq] * 1000;
4448 }
4449
4450 static void vlv_update_cdclk(struct drm_device *dev)
4451 {
4452 struct drm_i915_private *dev_priv = dev->dev_private;
4453
4454 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4455 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz",
4456 dev_priv->vlv_cdclk_freq);
4457
4458 /*
4459 * Program the gmbus_freq based on the cdclk frequency.
4460 * BSpec erroneously claims we should aim for 4MHz, but
4461 * in fact 1MHz is the correct frequency.
4462 */
4463 I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
4464 }
4465
4466 /* Adjust CDclk dividers to allow high res or save power if possible */
4467 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4468 {
4469 struct drm_i915_private *dev_priv = dev->dev_private;
4470 u32 val, cmd;
4471
4472 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4473
4474 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4475 cmd = 2;
4476 else if (cdclk == 266667)
4477 cmd = 1;
4478 else
4479 cmd = 0;
4480
4481 mutex_lock(&dev_priv->rps.hw_lock);
4482 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4483 val &= ~DSPFREQGUAR_MASK;
4484 val |= (cmd << DSPFREQGUAR_SHIFT);
4485 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4486 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4487 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4488 50)) {
4489 DRM_ERROR("timed out waiting for CDclk change\n");
4490 }
4491 mutex_unlock(&dev_priv->rps.hw_lock);
4492
4493 if (cdclk == 400000) {
4494 u32 divider, vco;
4495
4496 vco = valleyview_get_vco(dev_priv);
4497 divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1;
4498
4499 mutex_lock(&dev_priv->dpio_lock);
4500 /* adjust cdclk divider */
4501 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4502 val &= ~DISPLAY_FREQUENCY_VALUES;
4503 val |= divider;
4504 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4505
4506 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4507 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4508 50))
4509 DRM_ERROR("timed out waiting for CDclk change\n");
4510 mutex_unlock(&dev_priv->dpio_lock);
4511 }
4512
4513 mutex_lock(&dev_priv->dpio_lock);
4514 /* adjust self-refresh exit latency value */
4515 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4516 val &= ~0x7f;
4517
4518 /*
4519 * For high bandwidth configs, we set a higher latency in the bunit
4520 * so that the core display fetch happens in time to avoid underruns.
4521 */
4522 if (cdclk == 400000)
4523 val |= 4500 / 250; /* 4.5 usec */
4524 else
4525 val |= 3000 / 250; /* 3.0 usec */
4526 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4527 mutex_unlock(&dev_priv->dpio_lock);
4528
4529 vlv_update_cdclk(dev);
4530 }
4531
4532 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4533 int max_pixclk)
4534 {
4535 int vco = valleyview_get_vco(dev_priv);
4536 int freq_320 = (vco << 1) % 320000 != 0 ? 333333 : 320000;
4537
4538 /*
4539 * Really only a few cases to deal with, as only 4 CDclks are supported:
4540 * 200MHz
4541 * 267MHz
4542 * 320/333MHz (depends on HPLL freq)
4543 * 400MHz
4544 * So we check to see whether we're above 90% of the lower bin and
4545 * adjust if needed.
4546 *
4547 * We seem to get an unstable or solid color picture at 200MHz.
4548 * Not sure what's wrong. For now use 200MHz only when all pipes
4549 * are off.
4550 */
4551 if (max_pixclk > freq_320*9/10)
4552 return 400000;
4553 else if (max_pixclk > 266667*9/10)
4554 return freq_320;
4555 else if (max_pixclk > 0)
4556 return 266667;
4557 else
4558 return 200000;
4559 }
4560
4561 /* compute the max pixel clock for new configuration */
4562 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4563 {
4564 struct drm_device *dev = dev_priv->dev;
4565 struct intel_crtc *intel_crtc;
4566 int max_pixclk = 0;
4567
4568 for_each_intel_crtc(dev, intel_crtc) {
4569 if (intel_crtc->new_enabled)
4570 max_pixclk = max(max_pixclk,
4571 intel_crtc->new_config->adjusted_mode.crtc_clock);
4572 }
4573
4574 return max_pixclk;
4575 }
4576
4577 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4578 unsigned *prepare_pipes)
4579 {
4580 struct drm_i915_private *dev_priv = dev->dev_private;
4581 struct intel_crtc *intel_crtc;
4582 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4583
4584 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4585 dev_priv->vlv_cdclk_freq)
4586 return;
4587
4588 /* disable/enable all currently active pipes while we change cdclk */
4589 for_each_intel_crtc(dev, intel_crtc)
4590 if (intel_crtc->base.enabled)
4591 *prepare_pipes |= (1 << intel_crtc->pipe);
4592 }
4593
4594 static void valleyview_modeset_global_resources(struct drm_device *dev)
4595 {
4596 struct drm_i915_private *dev_priv = dev->dev_private;
4597 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4598 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4599
4600 if (req_cdclk != dev_priv->vlv_cdclk_freq)
4601 valleyview_set_cdclk(dev, req_cdclk);
4602 modeset_update_crtc_power_domains(dev);
4603 }
4604
4605 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4606 {
4607 struct drm_device *dev = crtc->dev;
4608 struct drm_i915_private *dev_priv = dev->dev_private;
4609 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4610 struct intel_encoder *encoder;
4611 int pipe = intel_crtc->pipe;
4612 int plane = intel_crtc->plane;
4613 bool is_dsi;
4614 u32 dspcntr;
4615
4616 WARN_ON(!crtc->enabled);
4617
4618 if (intel_crtc->active)
4619 return;
4620
4621 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4622
4623 if (!is_dsi && !IS_CHERRYVIEW(dev))
4624 vlv_prepare_pll(intel_crtc);
4625
4626 /* Set up the display plane register */
4627 dspcntr = DISPPLANE_GAMMA_ENABLE;
4628
4629 if (intel_crtc->config.has_dp_encoder)
4630 intel_dp_set_m_n(intel_crtc);
4631
4632 intel_set_pipe_timings(intel_crtc);
4633
4634 /* pipesrc and dspsize control the size that is scaled from,
4635 * which should always be the user's requested size.
4636 */
4637 I915_WRITE(DSPSIZE(plane),
4638 ((intel_crtc->config.pipe_src_h - 1) << 16) |
4639 (intel_crtc->config.pipe_src_w - 1));
4640 I915_WRITE(DSPPOS(plane), 0);
4641
4642 i9xx_set_pipeconf(intel_crtc);
4643
4644 I915_WRITE(DSPCNTR(plane), dspcntr);
4645 POSTING_READ(DSPCNTR(plane));
4646
4647 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4648 crtc->x, crtc->y);
4649
4650 intel_crtc->active = true;
4651
4652 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4653
4654 for_each_encoder_on_crtc(dev, crtc, encoder)
4655 if (encoder->pre_pll_enable)
4656 encoder->pre_pll_enable(encoder);
4657
4658 if (!is_dsi) {
4659 if (IS_CHERRYVIEW(dev))
4660 chv_enable_pll(intel_crtc);
4661 else
4662 vlv_enable_pll(intel_crtc);
4663 }
4664
4665 for_each_encoder_on_crtc(dev, crtc, encoder)
4666 if (encoder->pre_enable)
4667 encoder->pre_enable(encoder);
4668
4669 i9xx_pfit_enable(intel_crtc);
4670
4671 intel_crtc_load_lut(crtc);
4672
4673 intel_update_watermarks(crtc);
4674 intel_enable_pipe(intel_crtc);
4675
4676 for_each_encoder_on_crtc(dev, crtc, encoder)
4677 encoder->enable(encoder);
4678
4679 intel_crtc_enable_planes(crtc);
4680
4681 /* Underruns don't raise interrupts, so check manually. */
4682 i9xx_check_fifo_underruns(dev);
4683 }
4684
4685 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4686 {
4687 struct drm_device *dev = crtc->base.dev;
4688 struct drm_i915_private *dev_priv = dev->dev_private;
4689
4690 I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4691 I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4692 }
4693
4694 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4695 {
4696 struct drm_device *dev = crtc->dev;
4697 struct drm_i915_private *dev_priv = dev->dev_private;
4698 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4699 struct intel_encoder *encoder;
4700 int pipe = intel_crtc->pipe;
4701 int plane = intel_crtc->plane;
4702 u32 dspcntr;
4703
4704 WARN_ON(!crtc->enabled);
4705
4706 if (intel_crtc->active)
4707 return;
4708
4709 i9xx_set_pll_dividers(intel_crtc);
4710
4711 /* Set up the display plane register */
4712 dspcntr = DISPPLANE_GAMMA_ENABLE;
4713
4714 if (pipe == 0)
4715 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4716 else
4717 dspcntr |= DISPPLANE_SEL_PIPE_B;
4718
4719 if (intel_crtc->config.has_dp_encoder)
4720 intel_dp_set_m_n(intel_crtc);
4721
4722 intel_set_pipe_timings(intel_crtc);
4723
4724 /* pipesrc and dspsize control the size that is scaled from,
4725 * which should always be the user's requested size.
4726 */
4727 I915_WRITE(DSPSIZE(plane),
4728 ((intel_crtc->config.pipe_src_h - 1) << 16) |
4729 (intel_crtc->config.pipe_src_w - 1));
4730 I915_WRITE(DSPPOS(plane), 0);
4731
4732 i9xx_set_pipeconf(intel_crtc);
4733
4734 I915_WRITE(DSPCNTR(plane), dspcntr);
4735 POSTING_READ(DSPCNTR(plane));
4736
4737 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4738 crtc->x, crtc->y);
4739
4740 intel_crtc->active = true;
4741
4742 if (!IS_GEN2(dev))
4743 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4744
4745 for_each_encoder_on_crtc(dev, crtc, encoder)
4746 if (encoder->pre_enable)
4747 encoder->pre_enable(encoder);
4748
4749 i9xx_enable_pll(intel_crtc);
4750
4751 i9xx_pfit_enable(intel_crtc);
4752
4753 intel_crtc_load_lut(crtc);
4754
4755 intel_update_watermarks(crtc);
4756 intel_enable_pipe(intel_crtc);
4757
4758 for_each_encoder_on_crtc(dev, crtc, encoder)
4759 encoder->enable(encoder);
4760
4761 intel_crtc_enable_planes(crtc);
4762
4763 /*
4764 * Gen2 reports pipe underruns whenever all planes are disabled.
4765 * So don't enable underrun reporting before at least some planes
4766 * are enabled.
4767 * FIXME: Need to fix the logic to work when we turn off all planes
4768 * but leave the pipe running.
4769 */
4770 if (IS_GEN2(dev))
4771 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4772
4773 /* Underruns don't raise interrupts, so check manually. */
4774 i9xx_check_fifo_underruns(dev);
4775 }
4776
4777 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4778 {
4779 struct drm_device *dev = crtc->base.dev;
4780 struct drm_i915_private *dev_priv = dev->dev_private;
4781
4782 if (!crtc->config.gmch_pfit.control)
4783 return;
4784
4785 assert_pipe_disabled(dev_priv, crtc->pipe);
4786
4787 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4788 I915_READ(PFIT_CONTROL));
4789 I915_WRITE(PFIT_CONTROL, 0);
4790 }
4791
4792 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4793 {
4794 struct drm_device *dev = crtc->dev;
4795 struct drm_i915_private *dev_priv = dev->dev_private;
4796 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4797 struct intel_encoder *encoder;
4798 int pipe = intel_crtc->pipe;
4799
4800 if (!intel_crtc->active)
4801 return;
4802
4803 /*
4804 * Gen2 reports pipe underruns whenever all planes are disabled.
4805 * So diasble underrun reporting before all the planes get disabled.
4806 * FIXME: Need to fix the logic to work when we turn off all planes
4807 * but leave the pipe running.
4808 */
4809 if (IS_GEN2(dev))
4810 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4811
4812 /*
4813 * Vblank time updates from the shadow to live plane control register
4814 * are blocked if the memory self-refresh mode is active at that
4815 * moment. So to make sure the plane gets truly disabled, disable
4816 * first the self-refresh mode. The self-refresh enable bit in turn
4817 * will be checked/applied by the HW only at the next frame start
4818 * event which is after the vblank start event, so we need to have a
4819 * wait-for-vblank between disabling the plane and the pipe.
4820 */
4821 intel_set_memory_cxsr(dev_priv, false);
4822 intel_crtc_disable_planes(crtc);
4823
4824 for_each_encoder_on_crtc(dev, crtc, encoder)
4825 encoder->disable(encoder);
4826
4827 /*
4828 * On gen2 planes are double buffered but the pipe isn't, so we must
4829 * wait for planes to fully turn off before disabling the pipe.
4830 * We also need to wait on all gmch platforms because of the
4831 * self-refresh mode constraint explained above.
4832 */
4833 intel_wait_for_vblank(dev, pipe);
4834
4835 intel_disable_pipe(dev_priv, pipe);
4836
4837 i9xx_pfit_disable(intel_crtc);
4838
4839 for_each_encoder_on_crtc(dev, crtc, encoder)
4840 if (encoder->post_disable)
4841 encoder->post_disable(encoder);
4842
4843 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4844 if (IS_CHERRYVIEW(dev))
4845 chv_disable_pll(dev_priv, pipe);
4846 else if (IS_VALLEYVIEW(dev))
4847 vlv_disable_pll(dev_priv, pipe);
4848 else
4849 i9xx_disable_pll(dev_priv, pipe);
4850 }
4851
4852 if (!IS_GEN2(dev))
4853 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4854
4855 intel_crtc->active = false;
4856 intel_update_watermarks(crtc);
4857
4858 mutex_lock(&dev->struct_mutex);
4859 intel_update_fbc(dev);
4860 mutex_unlock(&dev->struct_mutex);
4861 }
4862
4863 static void i9xx_crtc_off(struct drm_crtc *crtc)
4864 {
4865 }
4866
4867 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4868 bool enabled)
4869 {
4870 struct drm_device *dev = crtc->dev;
4871 struct drm_i915_master_private *master_priv;
4872 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4873 int pipe = intel_crtc->pipe;
4874
4875 if (!dev->primary->master)
4876 return;
4877
4878 master_priv = dev->primary->master->driver_priv;
4879 if (!master_priv->sarea_priv)
4880 return;
4881
4882 switch (pipe) {
4883 case 0:
4884 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4885 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4886 break;
4887 case 1:
4888 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4889 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4890 break;
4891 default:
4892 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4893 break;
4894 }
4895 }
4896
4897 /* Master function to enable/disable CRTC and corresponding power wells */
4898 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
4899 {
4900 struct drm_device *dev = crtc->dev;
4901 struct drm_i915_private *dev_priv = dev->dev_private;
4902 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4903 enum intel_display_power_domain domain;
4904 unsigned long domains;
4905
4906 if (enable) {
4907 if (!intel_crtc->active) {
4908 domains = get_crtc_power_domains(crtc);
4909 for_each_power_domain(domain, domains)
4910 intel_display_power_get(dev_priv, domain);
4911 intel_crtc->enabled_power_domains = domains;
4912
4913 dev_priv->display.crtc_enable(crtc);
4914 }
4915 } else {
4916 if (intel_crtc->active) {
4917 dev_priv->display.crtc_disable(crtc);
4918
4919 domains = intel_crtc->enabled_power_domains;
4920 for_each_power_domain(domain, domains)
4921 intel_display_power_put(dev_priv, domain);
4922 intel_crtc->enabled_power_domains = 0;
4923 }
4924 }
4925 }
4926
4927 /**
4928 * Sets the power management mode of the pipe and plane.
4929 */
4930 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4931 {
4932 struct drm_device *dev = crtc->dev;
4933 struct intel_encoder *intel_encoder;
4934 bool enable = false;
4935
4936 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4937 enable |= intel_encoder->connectors_active;
4938
4939 intel_crtc_control(crtc, enable);
4940
4941 intel_crtc_update_sarea(crtc, enable);
4942 }
4943
4944 static void intel_crtc_disable(struct drm_crtc *crtc)
4945 {
4946 struct drm_device *dev = crtc->dev;
4947 struct drm_connector *connector;
4948 struct drm_i915_private *dev_priv = dev->dev_private;
4949 struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
4950 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4951
4952 /* crtc should still be enabled when we disable it. */
4953 WARN_ON(!crtc->enabled);
4954
4955 dev_priv->display.crtc_disable(crtc);
4956 intel_crtc_update_sarea(crtc, false);
4957 dev_priv->display.off(crtc);
4958
4959 if (crtc->primary->fb) {
4960 mutex_lock(&dev->struct_mutex);
4961 intel_unpin_fb_obj(old_obj);
4962 i915_gem_track_fb(old_obj, NULL,
4963 INTEL_FRONTBUFFER_PRIMARY(pipe));
4964 mutex_unlock(&dev->struct_mutex);
4965 crtc->primary->fb = NULL;
4966 }
4967
4968 /* Update computed state. */
4969 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4970 if (!connector->encoder || !connector->encoder->crtc)
4971 continue;
4972
4973 if (connector->encoder->crtc != crtc)
4974 continue;
4975
4976 connector->dpms = DRM_MODE_DPMS_OFF;
4977 to_intel_encoder(connector->encoder)->connectors_active = false;
4978 }
4979 }
4980
4981 void intel_encoder_destroy(struct drm_encoder *encoder)
4982 {
4983 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4984
4985 drm_encoder_cleanup(encoder);
4986 kfree(intel_encoder);
4987 }
4988
4989 /* Simple dpms helper for encoders with just one connector, no cloning and only
4990 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4991 * state of the entire output pipe. */
4992 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4993 {
4994 if (mode == DRM_MODE_DPMS_ON) {
4995 encoder->connectors_active = true;
4996
4997 intel_crtc_update_dpms(encoder->base.crtc);
4998 } else {
4999 encoder->connectors_active = false;
5000
5001 intel_crtc_update_dpms(encoder->base.crtc);
5002 }
5003 }
5004
5005 /* Cross check the actual hw state with our own modeset state tracking (and it's
5006 * internal consistency). */
5007 static void intel_connector_check_state(struct intel_connector *connector)
5008 {
5009 if (connector->get_hw_state(connector)) {
5010 struct intel_encoder *encoder = connector->encoder;
5011 struct drm_crtc *crtc;
5012 bool encoder_enabled;
5013 enum pipe pipe;
5014
5015 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5016 connector->base.base.id,
5017 connector->base.name);
5018
5019 /* there is no real hw state for MST connectors */
5020 if (connector->mst_port)
5021 return;
5022
5023 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5024 "wrong connector dpms state\n");
5025 WARN(connector->base.encoder != &encoder->base,
5026 "active connector not linked to encoder\n");
5027
5028 if (encoder) {
5029 WARN(!encoder->connectors_active,
5030 "encoder->connectors_active not set\n");
5031
5032 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5033 WARN(!encoder_enabled, "encoder not enabled\n");
5034 if (WARN_ON(!encoder->base.crtc))
5035 return;
5036
5037 crtc = encoder->base.crtc;
5038
5039 WARN(!crtc->enabled, "crtc not enabled\n");
5040 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5041 WARN(pipe != to_intel_crtc(crtc)->pipe,
5042 "encoder active on the wrong pipe\n");
5043 }
5044 }
5045 }
5046
5047 /* Even simpler default implementation, if there's really no special case to
5048 * consider. */
5049 void intel_connector_dpms(struct drm_connector *connector, int mode)
5050 {
5051 /* All the simple cases only support two dpms states. */
5052 if (mode != DRM_MODE_DPMS_ON)
5053 mode = DRM_MODE_DPMS_OFF;
5054
5055 if (mode == connector->dpms)
5056 return;
5057
5058 connector->dpms = mode;
5059
5060 /* Only need to change hw state when actually enabled */
5061 if (connector->encoder)
5062 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5063
5064 intel_modeset_check_state(connector->dev);
5065 }
5066
5067 /* Simple connector->get_hw_state implementation for encoders that support only
5068 * one connector and no cloning and hence the encoder state determines the state
5069 * of the connector. */
5070 bool intel_connector_get_hw_state(struct intel_connector *connector)
5071 {
5072 enum pipe pipe = 0;
5073 struct intel_encoder *encoder = connector->encoder;
5074
5075 return encoder->get_hw_state(encoder, &pipe);
5076 }
5077
5078 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5079 struct intel_crtc_config *pipe_config)
5080 {
5081 struct drm_i915_private *dev_priv = dev->dev_private;
5082 struct intel_crtc *pipe_B_crtc =
5083 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5084
5085 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5086 pipe_name(pipe), pipe_config->fdi_lanes);
5087 if (pipe_config->fdi_lanes > 4) {
5088 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5089 pipe_name(pipe), pipe_config->fdi_lanes);
5090 return false;
5091 }
5092
5093 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5094 if (pipe_config->fdi_lanes > 2) {
5095 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5096 pipe_config->fdi_lanes);
5097 return false;
5098 } else {
5099 return true;
5100 }
5101 }
5102
5103 if (INTEL_INFO(dev)->num_pipes == 2)
5104 return true;
5105
5106 /* Ivybridge 3 pipe is really complicated */
5107 switch (pipe) {
5108 case PIPE_A:
5109 return true;
5110 case PIPE_B:
5111 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5112 pipe_config->fdi_lanes > 2) {
5113 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5114 pipe_name(pipe), pipe_config->fdi_lanes);
5115 return false;
5116 }
5117 return true;
5118 case PIPE_C:
5119 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5120 pipe_B_crtc->config.fdi_lanes <= 2) {
5121 if (pipe_config->fdi_lanes > 2) {
5122 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5123 pipe_name(pipe), pipe_config->fdi_lanes);
5124 return false;
5125 }
5126 } else {
5127 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5128 return false;
5129 }
5130 return true;
5131 default:
5132 BUG();
5133 }
5134 }
5135
5136 #define RETRY 1
5137 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5138 struct intel_crtc_config *pipe_config)
5139 {
5140 struct drm_device *dev = intel_crtc->base.dev;
5141 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5142 int lane, link_bw, fdi_dotclock;
5143 bool setup_ok, needs_recompute = false;
5144
5145 retry:
5146 /* FDI is a binary signal running at ~2.7GHz, encoding
5147 * each output octet as 10 bits. The actual frequency
5148 * is stored as a divider into a 100MHz clock, and the
5149 * mode pixel clock is stored in units of 1KHz.
5150 * Hence the bw of each lane in terms of the mode signal
5151 * is:
5152 */
5153 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5154
5155 fdi_dotclock = adjusted_mode->crtc_clock;
5156
5157 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5158 pipe_config->pipe_bpp);
5159
5160 pipe_config->fdi_lanes = lane;
5161
5162 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5163 link_bw, &pipe_config->fdi_m_n);
5164
5165 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5166 intel_crtc->pipe, pipe_config);
5167 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5168 pipe_config->pipe_bpp -= 2*3;
5169 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5170 pipe_config->pipe_bpp);
5171 needs_recompute = true;
5172 pipe_config->bw_constrained = true;
5173
5174 goto retry;
5175 }
5176
5177 if (needs_recompute)
5178 return RETRY;
5179
5180 return setup_ok ? 0 : -EINVAL;
5181 }
5182
5183 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5184 struct intel_crtc_config *pipe_config)
5185 {
5186 pipe_config->ips_enabled = i915.enable_ips &&
5187 hsw_crtc_supports_ips(crtc) &&
5188 pipe_config->pipe_bpp <= 24;
5189 }
5190
5191 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5192 struct intel_crtc_config *pipe_config)
5193 {
5194 struct drm_device *dev = crtc->base.dev;
5195 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5196
5197 /* FIXME should check pixel clock limits on all platforms */
5198 if (INTEL_INFO(dev)->gen < 4) {
5199 struct drm_i915_private *dev_priv = dev->dev_private;
5200 int clock_limit =
5201 dev_priv->display.get_display_clock_speed(dev);
5202
5203 /*
5204 * Enable pixel doubling when the dot clock
5205 * is > 90% of the (display) core speed.
5206 *
5207 * GDG double wide on either pipe,
5208 * otherwise pipe A only.
5209 */
5210 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5211 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5212 clock_limit *= 2;
5213 pipe_config->double_wide = true;
5214 }
5215
5216 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5217 return -EINVAL;
5218 }
5219
5220 /*
5221 * Pipe horizontal size must be even in:
5222 * - DVO ganged mode
5223 * - LVDS dual channel mode
5224 * - Double wide pipe
5225 */
5226 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5227 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5228 pipe_config->pipe_src_w &= ~1;
5229
5230 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5231 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5232 */
5233 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5234 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5235 return -EINVAL;
5236
5237 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5238 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5239 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5240 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5241 * for lvds. */
5242 pipe_config->pipe_bpp = 8*3;
5243 }
5244
5245 if (HAS_IPS(dev))
5246 hsw_compute_ips_config(crtc, pipe_config);
5247
5248 /*
5249 * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the
5250 * old clock survives for now.
5251 */
5252 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev) || HAS_DDI(dev))
5253 pipe_config->shared_dpll = crtc->config.shared_dpll;
5254
5255 if (pipe_config->has_pch_encoder)
5256 return ironlake_fdi_compute_config(crtc, pipe_config);
5257
5258 return 0;
5259 }
5260
5261 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5262 {
5263 struct drm_i915_private *dev_priv = dev->dev_private;
5264 int vco = valleyview_get_vco(dev_priv);
5265 u32 val;
5266 int divider;
5267
5268 mutex_lock(&dev_priv->dpio_lock);
5269 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5270 mutex_unlock(&dev_priv->dpio_lock);
5271
5272 divider = val & DISPLAY_FREQUENCY_VALUES;
5273
5274 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5275 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5276 "cdclk change in progress\n");
5277
5278 return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
5279 }
5280
5281 static int i945_get_display_clock_speed(struct drm_device *dev)
5282 {
5283 return 400000;
5284 }
5285
5286 static int i915_get_display_clock_speed(struct drm_device *dev)
5287 {
5288 return 333000;
5289 }
5290
5291 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5292 {
5293 return 200000;
5294 }
5295
5296 static int pnv_get_display_clock_speed(struct drm_device *dev)
5297 {
5298 u16 gcfgc = 0;
5299
5300 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5301
5302 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5303 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5304 return 267000;
5305 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5306 return 333000;
5307 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5308 return 444000;
5309 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5310 return 200000;
5311 default:
5312 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5313 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5314 return 133000;
5315 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5316 return 167000;
5317 }
5318 }
5319
5320 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5321 {
5322 u16 gcfgc = 0;
5323
5324 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5325
5326 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5327 return 133000;
5328 else {
5329 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5330 case GC_DISPLAY_CLOCK_333_MHZ:
5331 return 333000;
5332 default:
5333 case GC_DISPLAY_CLOCK_190_200_MHZ:
5334 return 190000;
5335 }
5336 }
5337 }
5338
5339 static int i865_get_display_clock_speed(struct drm_device *dev)
5340 {
5341 return 266000;
5342 }
5343
5344 static int i855_get_display_clock_speed(struct drm_device *dev)
5345 {
5346 u16 hpllcc = 0;
5347 /* Assume that the hardware is in the high speed state. This
5348 * should be the default.
5349 */
5350 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5351 case GC_CLOCK_133_200:
5352 case GC_CLOCK_100_200:
5353 return 200000;
5354 case GC_CLOCK_166_250:
5355 return 250000;
5356 case GC_CLOCK_100_133:
5357 return 133000;
5358 }
5359
5360 /* Shouldn't happen */
5361 return 0;
5362 }
5363
5364 static int i830_get_display_clock_speed(struct drm_device *dev)
5365 {
5366 return 133000;
5367 }
5368
5369 static void
5370 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5371 {
5372 while (*num > DATA_LINK_M_N_MASK ||
5373 *den > DATA_LINK_M_N_MASK) {
5374 *num >>= 1;
5375 *den >>= 1;
5376 }
5377 }
5378
5379 static void compute_m_n(unsigned int m, unsigned int n,
5380 uint32_t *ret_m, uint32_t *ret_n)
5381 {
5382 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5383 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5384 intel_reduce_m_n_ratio(ret_m, ret_n);
5385 }
5386
5387 void
5388 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5389 int pixel_clock, int link_clock,
5390 struct intel_link_m_n *m_n)
5391 {
5392 m_n->tu = 64;
5393
5394 compute_m_n(bits_per_pixel * pixel_clock,
5395 link_clock * nlanes * 8,
5396 &m_n->gmch_m, &m_n->gmch_n);
5397
5398 compute_m_n(pixel_clock, link_clock,
5399 &m_n->link_m, &m_n->link_n);
5400 }
5401
5402 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5403 {
5404 if (i915.panel_use_ssc >= 0)
5405 return i915.panel_use_ssc != 0;
5406 return dev_priv->vbt.lvds_use_ssc
5407 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5408 }
5409
5410 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5411 {
5412 struct drm_device *dev = crtc->dev;
5413 struct drm_i915_private *dev_priv = dev->dev_private;
5414 int refclk;
5415
5416 if (IS_VALLEYVIEW(dev)) {
5417 refclk = 100000;
5418 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5419 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5420 refclk = dev_priv->vbt.lvds_ssc_freq;
5421 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5422 } else if (!IS_GEN2(dev)) {
5423 refclk = 96000;
5424 } else {
5425 refclk = 48000;
5426 }
5427
5428 return refclk;
5429 }
5430
5431 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5432 {
5433 return (1 << dpll->n) << 16 | dpll->m2;
5434 }
5435
5436 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5437 {
5438 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5439 }
5440
5441 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5442 intel_clock_t *reduced_clock)
5443 {
5444 struct drm_device *dev = crtc->base.dev;
5445 u32 fp, fp2 = 0;
5446
5447 if (IS_PINEVIEW(dev)) {
5448 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5449 if (reduced_clock)
5450 fp2 = pnv_dpll_compute_fp(reduced_clock);
5451 } else {
5452 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5453 if (reduced_clock)
5454 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5455 }
5456
5457 crtc->config.dpll_hw_state.fp0 = fp;
5458
5459 crtc->lowfreq_avail = false;
5460 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5461 reduced_clock && i915.powersave) {
5462 crtc->config.dpll_hw_state.fp1 = fp2;
5463 crtc->lowfreq_avail = true;
5464 } else {
5465 crtc->config.dpll_hw_state.fp1 = fp;
5466 }
5467 }
5468
5469 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5470 pipe)
5471 {
5472 u32 reg_val;
5473
5474 /*
5475 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5476 * and set it to a reasonable value instead.
5477 */
5478 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5479 reg_val &= 0xffffff00;
5480 reg_val |= 0x00000030;
5481 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5482
5483 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5484 reg_val &= 0x8cffffff;
5485 reg_val = 0x8c000000;
5486 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5487
5488 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5489 reg_val &= 0xffffff00;
5490 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5491
5492 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5493 reg_val &= 0x00ffffff;
5494 reg_val |= 0xb0000000;
5495 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5496 }
5497
5498 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5499 struct intel_link_m_n *m_n)
5500 {
5501 struct drm_device *dev = crtc->base.dev;
5502 struct drm_i915_private *dev_priv = dev->dev_private;
5503 int pipe = crtc->pipe;
5504
5505 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5506 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5507 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5508 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5509 }
5510
5511 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5512 struct intel_link_m_n *m_n,
5513 struct intel_link_m_n *m2_n2)
5514 {
5515 struct drm_device *dev = crtc->base.dev;
5516 struct drm_i915_private *dev_priv = dev->dev_private;
5517 int pipe = crtc->pipe;
5518 enum transcoder transcoder = crtc->config.cpu_transcoder;
5519
5520 if (INTEL_INFO(dev)->gen >= 5) {
5521 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5522 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5523 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5524 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5525 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5526 * for gen < 8) and if DRRS is supported (to make sure the
5527 * registers are not unnecessarily accessed).
5528 */
5529 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5530 crtc->config.has_drrs) {
5531 I915_WRITE(PIPE_DATA_M2(transcoder),
5532 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5533 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5534 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5535 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5536 }
5537 } else {
5538 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5539 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5540 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5541 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5542 }
5543 }
5544
5545 void intel_dp_set_m_n(struct intel_crtc *crtc)
5546 {
5547 if (crtc->config.has_pch_encoder)
5548 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5549 else
5550 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
5551 &crtc->config.dp_m2_n2);
5552 }
5553
5554 static void vlv_update_pll(struct intel_crtc *crtc)
5555 {
5556 u32 dpll, dpll_md;
5557
5558 /*
5559 * Enable DPIO clock input. We should never disable the reference
5560 * clock for pipe B, since VGA hotplug / manual detection depends
5561 * on it.
5562 */
5563 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5564 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5565 /* We should never disable this, set it here for state tracking */
5566 if (crtc->pipe == PIPE_B)
5567 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5568 dpll |= DPLL_VCO_ENABLE;
5569 crtc->config.dpll_hw_state.dpll = dpll;
5570
5571 dpll_md = (crtc->config.pixel_multiplier - 1)
5572 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5573 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5574 }
5575
5576 static void vlv_prepare_pll(struct intel_crtc *crtc)
5577 {
5578 struct drm_device *dev = crtc->base.dev;
5579 struct drm_i915_private *dev_priv = dev->dev_private;
5580 int pipe = crtc->pipe;
5581 u32 mdiv;
5582 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5583 u32 coreclk, reg_val;
5584
5585 mutex_lock(&dev_priv->dpio_lock);
5586
5587 bestn = crtc->config.dpll.n;
5588 bestm1 = crtc->config.dpll.m1;
5589 bestm2 = crtc->config.dpll.m2;
5590 bestp1 = crtc->config.dpll.p1;
5591 bestp2 = crtc->config.dpll.p2;
5592
5593 /* See eDP HDMI DPIO driver vbios notes doc */
5594
5595 /* PLL B needs special handling */
5596 if (pipe == PIPE_B)
5597 vlv_pllb_recal_opamp(dev_priv, pipe);
5598
5599 /* Set up Tx target for periodic Rcomp update */
5600 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5601
5602 /* Disable target IRef on PLL */
5603 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5604 reg_val &= 0x00ffffff;
5605 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5606
5607 /* Disable fast lock */
5608 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5609
5610 /* Set idtafcrecal before PLL is enabled */
5611 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5612 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5613 mdiv |= ((bestn << DPIO_N_SHIFT));
5614 mdiv |= (1 << DPIO_K_SHIFT);
5615
5616 /*
5617 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5618 * but we don't support that).
5619 * Note: don't use the DAC post divider as it seems unstable.
5620 */
5621 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5622 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5623
5624 mdiv |= DPIO_ENABLE_CALIBRATION;
5625 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5626
5627 /* Set HBR and RBR LPF coefficients */
5628 if (crtc->config.port_clock == 162000 ||
5629 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5630 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5631 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5632 0x009f0003);
5633 else
5634 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5635 0x00d0000f);
5636
5637 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5638 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5639 /* Use SSC source */
5640 if (pipe == PIPE_A)
5641 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5642 0x0df40000);
5643 else
5644 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5645 0x0df70000);
5646 } else { /* HDMI or VGA */
5647 /* Use bend source */
5648 if (pipe == PIPE_A)
5649 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5650 0x0df70000);
5651 else
5652 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5653 0x0df40000);
5654 }
5655
5656 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5657 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5658 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5659 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5660 coreclk |= 0x01000000;
5661 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5662
5663 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5664 mutex_unlock(&dev_priv->dpio_lock);
5665 }
5666
5667 static void chv_update_pll(struct intel_crtc *crtc)
5668 {
5669 struct drm_device *dev = crtc->base.dev;
5670 struct drm_i915_private *dev_priv = dev->dev_private;
5671 int pipe = crtc->pipe;
5672 int dpll_reg = DPLL(crtc->pipe);
5673 enum dpio_channel port = vlv_pipe_to_channel(pipe);
5674 u32 loopfilter, intcoeff;
5675 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5676 int refclk;
5677
5678 crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5679 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5680 DPLL_VCO_ENABLE;
5681 if (pipe != PIPE_A)
5682 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5683
5684 crtc->config.dpll_hw_state.dpll_md =
5685 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5686
5687 bestn = crtc->config.dpll.n;
5688 bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5689 bestm1 = crtc->config.dpll.m1;
5690 bestm2 = crtc->config.dpll.m2 >> 22;
5691 bestp1 = crtc->config.dpll.p1;
5692 bestp2 = crtc->config.dpll.p2;
5693
5694 /*
5695 * Enable Refclk and SSC
5696 */
5697 I915_WRITE(dpll_reg,
5698 crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5699
5700 mutex_lock(&dev_priv->dpio_lock);
5701
5702 /* p1 and p2 divider */
5703 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5704 5 << DPIO_CHV_S1_DIV_SHIFT |
5705 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5706 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5707 1 << DPIO_CHV_K_DIV_SHIFT);
5708
5709 /* Feedback post-divider - m2 */
5710 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5711
5712 /* Feedback refclk divider - n and m1 */
5713 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5714 DPIO_CHV_M1_DIV_BY_2 |
5715 1 << DPIO_CHV_N_DIV_SHIFT);
5716
5717 /* M2 fraction division */
5718 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5719
5720 /* M2 fraction division enable */
5721 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5722 DPIO_CHV_FRAC_DIV_EN |
5723 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5724
5725 /* Loop filter */
5726 refclk = i9xx_get_refclk(&crtc->base, 0);
5727 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5728 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5729 if (refclk == 100000)
5730 intcoeff = 11;
5731 else if (refclk == 38400)
5732 intcoeff = 10;
5733 else
5734 intcoeff = 9;
5735 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5736 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5737
5738 /* AFC Recal */
5739 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5740 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5741 DPIO_AFC_RECAL);
5742
5743 mutex_unlock(&dev_priv->dpio_lock);
5744 }
5745
5746 static void i9xx_update_pll(struct intel_crtc *crtc,
5747 intel_clock_t *reduced_clock,
5748 int num_connectors)
5749 {
5750 struct drm_device *dev = crtc->base.dev;
5751 struct drm_i915_private *dev_priv = dev->dev_private;
5752 u32 dpll;
5753 bool is_sdvo;
5754 struct dpll *clock = &crtc->config.dpll;
5755
5756 i9xx_update_pll_dividers(crtc, reduced_clock);
5757
5758 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5759 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5760
5761 dpll = DPLL_VGA_MODE_DIS;
5762
5763 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5764 dpll |= DPLLB_MODE_LVDS;
5765 else
5766 dpll |= DPLLB_MODE_DAC_SERIAL;
5767
5768 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5769 dpll |= (crtc->config.pixel_multiplier - 1)
5770 << SDVO_MULTIPLIER_SHIFT_HIRES;
5771 }
5772
5773 if (is_sdvo)
5774 dpll |= DPLL_SDVO_HIGH_SPEED;
5775
5776 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5777 dpll |= DPLL_SDVO_HIGH_SPEED;
5778
5779 /* compute bitmask from p1 value */
5780 if (IS_PINEVIEW(dev))
5781 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5782 else {
5783 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5784 if (IS_G4X(dev) && reduced_clock)
5785 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5786 }
5787 switch (clock->p2) {
5788 case 5:
5789 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5790 break;
5791 case 7:
5792 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5793 break;
5794 case 10:
5795 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5796 break;
5797 case 14:
5798 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5799 break;
5800 }
5801 if (INTEL_INFO(dev)->gen >= 4)
5802 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5803
5804 if (crtc->config.sdvo_tv_clock)
5805 dpll |= PLL_REF_INPUT_TVCLKINBC;
5806 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5807 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5808 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5809 else
5810 dpll |= PLL_REF_INPUT_DREFCLK;
5811
5812 dpll |= DPLL_VCO_ENABLE;
5813 crtc->config.dpll_hw_state.dpll = dpll;
5814
5815 if (INTEL_INFO(dev)->gen >= 4) {
5816 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5817 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5818 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5819 }
5820 }
5821
5822 static void i8xx_update_pll(struct intel_crtc *crtc,
5823 intel_clock_t *reduced_clock,
5824 int num_connectors)
5825 {
5826 struct drm_device *dev = crtc->base.dev;
5827 struct drm_i915_private *dev_priv = dev->dev_private;
5828 u32 dpll;
5829 struct dpll *clock = &crtc->config.dpll;
5830
5831 i9xx_update_pll_dividers(crtc, reduced_clock);
5832
5833 dpll = DPLL_VGA_MODE_DIS;
5834
5835 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5836 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5837 } else {
5838 if (clock->p1 == 2)
5839 dpll |= PLL_P1_DIVIDE_BY_TWO;
5840 else
5841 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5842 if (clock->p2 == 4)
5843 dpll |= PLL_P2_DIVIDE_BY_4;
5844 }
5845
5846 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5847 dpll |= DPLL_DVO_2X_MODE;
5848
5849 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5850 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5851 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5852 else
5853 dpll |= PLL_REF_INPUT_DREFCLK;
5854
5855 dpll |= DPLL_VCO_ENABLE;
5856 crtc->config.dpll_hw_state.dpll = dpll;
5857 }
5858
5859 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5860 {
5861 struct drm_device *dev = intel_crtc->base.dev;
5862 struct drm_i915_private *dev_priv = dev->dev_private;
5863 enum pipe pipe = intel_crtc->pipe;
5864 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5865 struct drm_display_mode *adjusted_mode =
5866 &intel_crtc->config.adjusted_mode;
5867 uint32_t crtc_vtotal, crtc_vblank_end;
5868 int vsyncshift = 0;
5869
5870 /* We need to be careful not to changed the adjusted mode, for otherwise
5871 * the hw state checker will get angry at the mismatch. */
5872 crtc_vtotal = adjusted_mode->crtc_vtotal;
5873 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5874
5875 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5876 /* the chip adds 2 halflines automatically */
5877 crtc_vtotal -= 1;
5878 crtc_vblank_end -= 1;
5879
5880 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5881 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5882 else
5883 vsyncshift = adjusted_mode->crtc_hsync_start -
5884 adjusted_mode->crtc_htotal / 2;
5885 if (vsyncshift < 0)
5886 vsyncshift += adjusted_mode->crtc_htotal;
5887 }
5888
5889 if (INTEL_INFO(dev)->gen > 3)
5890 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5891
5892 I915_WRITE(HTOTAL(cpu_transcoder),
5893 (adjusted_mode->crtc_hdisplay - 1) |
5894 ((adjusted_mode->crtc_htotal - 1) << 16));
5895 I915_WRITE(HBLANK(cpu_transcoder),
5896 (adjusted_mode->crtc_hblank_start - 1) |
5897 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5898 I915_WRITE(HSYNC(cpu_transcoder),
5899 (adjusted_mode->crtc_hsync_start - 1) |
5900 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5901
5902 I915_WRITE(VTOTAL(cpu_transcoder),
5903 (adjusted_mode->crtc_vdisplay - 1) |
5904 ((crtc_vtotal - 1) << 16));
5905 I915_WRITE(VBLANK(cpu_transcoder),
5906 (adjusted_mode->crtc_vblank_start - 1) |
5907 ((crtc_vblank_end - 1) << 16));
5908 I915_WRITE(VSYNC(cpu_transcoder),
5909 (adjusted_mode->crtc_vsync_start - 1) |
5910 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5911
5912 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5913 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5914 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5915 * bits. */
5916 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5917 (pipe == PIPE_B || pipe == PIPE_C))
5918 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5919
5920 /* pipesrc controls the size that is scaled from, which should
5921 * always be the user's requested size.
5922 */
5923 I915_WRITE(PIPESRC(pipe),
5924 ((intel_crtc->config.pipe_src_w - 1) << 16) |
5925 (intel_crtc->config.pipe_src_h - 1));
5926 }
5927
5928 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5929 struct intel_crtc_config *pipe_config)
5930 {
5931 struct drm_device *dev = crtc->base.dev;
5932 struct drm_i915_private *dev_priv = dev->dev_private;
5933 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5934 uint32_t tmp;
5935
5936 tmp = I915_READ(HTOTAL(cpu_transcoder));
5937 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5938 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5939 tmp = I915_READ(HBLANK(cpu_transcoder));
5940 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5941 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5942 tmp = I915_READ(HSYNC(cpu_transcoder));
5943 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5944 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5945
5946 tmp = I915_READ(VTOTAL(cpu_transcoder));
5947 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5948 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5949 tmp = I915_READ(VBLANK(cpu_transcoder));
5950 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5951 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5952 tmp = I915_READ(VSYNC(cpu_transcoder));
5953 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5954 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5955
5956 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5957 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5958 pipe_config->adjusted_mode.crtc_vtotal += 1;
5959 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5960 }
5961
5962 tmp = I915_READ(PIPESRC(crtc->pipe));
5963 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5964 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5965
5966 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5967 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5968 }
5969
5970 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5971 struct intel_crtc_config *pipe_config)
5972 {
5973 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5974 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5975 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5976 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5977
5978 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5979 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5980 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5981 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5982
5983 mode->flags = pipe_config->adjusted_mode.flags;
5984
5985 mode->clock = pipe_config->adjusted_mode.crtc_clock;
5986 mode->flags |= pipe_config->adjusted_mode.flags;
5987 }
5988
5989 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5990 {
5991 struct drm_device *dev = intel_crtc->base.dev;
5992 struct drm_i915_private *dev_priv = dev->dev_private;
5993 uint32_t pipeconf;
5994
5995 pipeconf = 0;
5996
5997 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5998 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5999 pipeconf |= PIPECONF_ENABLE;
6000
6001 if (intel_crtc->config.double_wide)
6002 pipeconf |= PIPECONF_DOUBLE_WIDE;
6003
6004 /* only g4x and later have fancy bpc/dither controls */
6005 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6006 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6007 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
6008 pipeconf |= PIPECONF_DITHER_EN |
6009 PIPECONF_DITHER_TYPE_SP;
6010
6011 switch (intel_crtc->config.pipe_bpp) {
6012 case 18:
6013 pipeconf |= PIPECONF_6BPC;
6014 break;
6015 case 24:
6016 pipeconf |= PIPECONF_8BPC;
6017 break;
6018 case 30:
6019 pipeconf |= PIPECONF_10BPC;
6020 break;
6021 default:
6022 /* Case prevented by intel_choose_pipe_bpp_dither. */
6023 BUG();
6024 }
6025 }
6026
6027 if (HAS_PIPE_CXSR(dev)) {
6028 if (intel_crtc->lowfreq_avail) {
6029 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6030 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6031 } else {
6032 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6033 }
6034 }
6035
6036 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6037 if (INTEL_INFO(dev)->gen < 4 ||
6038 intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
6039 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6040 else
6041 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6042 } else
6043 pipeconf |= PIPECONF_PROGRESSIVE;
6044
6045 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6046 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6047
6048 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6049 POSTING_READ(PIPECONF(intel_crtc->pipe));
6050 }
6051
6052 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
6053 int x, int y,
6054 struct drm_framebuffer *fb)
6055 {
6056 struct drm_device *dev = crtc->dev;
6057 struct drm_i915_private *dev_priv = dev->dev_private;
6058 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6059 int refclk, num_connectors = 0;
6060 intel_clock_t clock, reduced_clock;
6061 bool ok, has_reduced_clock = false;
6062 bool is_lvds = false, is_dsi = false;
6063 struct intel_encoder *encoder;
6064 const intel_limit_t *limit;
6065
6066 for_each_encoder_on_crtc(dev, crtc, encoder) {
6067 switch (encoder->type) {
6068 case INTEL_OUTPUT_LVDS:
6069 is_lvds = true;
6070 break;
6071 case INTEL_OUTPUT_DSI:
6072 is_dsi = true;
6073 break;
6074 }
6075
6076 num_connectors++;
6077 }
6078
6079 if (is_dsi)
6080 return 0;
6081
6082 if (!intel_crtc->config.clock_set) {
6083 refclk = i9xx_get_refclk(crtc, num_connectors);
6084
6085 /*
6086 * Returns a set of divisors for the desired target clock with
6087 * the given refclk, or FALSE. The returned values represent
6088 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6089 * 2) / p1 / p2.
6090 */
6091 limit = intel_limit(crtc, refclk);
6092 ok = dev_priv->display.find_dpll(limit, crtc,
6093 intel_crtc->config.port_clock,
6094 refclk, NULL, &clock);
6095 if (!ok) {
6096 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6097 return -EINVAL;
6098 }
6099
6100 if (is_lvds && dev_priv->lvds_downclock_avail) {
6101 /*
6102 * Ensure we match the reduced clock's P to the target
6103 * clock. If the clocks don't match, we can't switch
6104 * the display clock by using the FP0/FP1. In such case
6105 * we will disable the LVDS downclock feature.
6106 */
6107 has_reduced_clock =
6108 dev_priv->display.find_dpll(limit, crtc,
6109 dev_priv->lvds_downclock,
6110 refclk, &clock,
6111 &reduced_clock);
6112 }
6113 /* Compat-code for transition, will disappear. */
6114 intel_crtc->config.dpll.n = clock.n;
6115 intel_crtc->config.dpll.m1 = clock.m1;
6116 intel_crtc->config.dpll.m2 = clock.m2;
6117 intel_crtc->config.dpll.p1 = clock.p1;
6118 intel_crtc->config.dpll.p2 = clock.p2;
6119 }
6120
6121 if (IS_GEN2(dev)) {
6122 i8xx_update_pll(intel_crtc,
6123 has_reduced_clock ? &reduced_clock : NULL,
6124 num_connectors);
6125 } else if (IS_CHERRYVIEW(dev)) {
6126 chv_update_pll(intel_crtc);
6127 } else if (IS_VALLEYVIEW(dev)) {
6128 vlv_update_pll(intel_crtc);
6129 } else {
6130 i9xx_update_pll(intel_crtc,
6131 has_reduced_clock ? &reduced_clock : NULL,
6132 num_connectors);
6133 }
6134
6135 return 0;
6136 }
6137
6138 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6139 struct intel_crtc_config *pipe_config)
6140 {
6141 struct drm_device *dev = crtc->base.dev;
6142 struct drm_i915_private *dev_priv = dev->dev_private;
6143 uint32_t tmp;
6144
6145 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6146 return;
6147
6148 tmp = I915_READ(PFIT_CONTROL);
6149 if (!(tmp & PFIT_ENABLE))
6150 return;
6151
6152 /* Check whether the pfit is attached to our pipe. */
6153 if (INTEL_INFO(dev)->gen < 4) {
6154 if (crtc->pipe != PIPE_B)
6155 return;
6156 } else {
6157 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6158 return;
6159 }
6160
6161 pipe_config->gmch_pfit.control = tmp;
6162 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6163 if (INTEL_INFO(dev)->gen < 5)
6164 pipe_config->gmch_pfit.lvds_border_bits =
6165 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6166 }
6167
6168 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6169 struct intel_crtc_config *pipe_config)
6170 {
6171 struct drm_device *dev = crtc->base.dev;
6172 struct drm_i915_private *dev_priv = dev->dev_private;
6173 int pipe = pipe_config->cpu_transcoder;
6174 intel_clock_t clock;
6175 u32 mdiv;
6176 int refclk = 100000;
6177
6178 /* In case of MIPI DPLL will not even be used */
6179 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6180 return;
6181
6182 mutex_lock(&dev_priv->dpio_lock);
6183 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6184 mutex_unlock(&dev_priv->dpio_lock);
6185
6186 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6187 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6188 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6189 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6190 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6191
6192 vlv_clock(refclk, &clock);
6193
6194 /* clock.dot is the fast clock */
6195 pipe_config->port_clock = clock.dot / 5;
6196 }
6197
6198 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6199 struct intel_plane_config *plane_config)
6200 {
6201 struct drm_device *dev = crtc->base.dev;
6202 struct drm_i915_private *dev_priv = dev->dev_private;
6203 u32 val, base, offset;
6204 int pipe = crtc->pipe, plane = crtc->plane;
6205 int fourcc, pixel_format;
6206 int aligned_height;
6207
6208 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6209 if (!crtc->base.primary->fb) {
6210 DRM_DEBUG_KMS("failed to alloc fb\n");
6211 return;
6212 }
6213
6214 val = I915_READ(DSPCNTR(plane));
6215
6216 if (INTEL_INFO(dev)->gen >= 4)
6217 if (val & DISPPLANE_TILED)
6218 plane_config->tiled = true;
6219
6220 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6221 fourcc = intel_format_to_fourcc(pixel_format);
6222 crtc->base.primary->fb->pixel_format = fourcc;
6223 crtc->base.primary->fb->bits_per_pixel =
6224 drm_format_plane_cpp(fourcc, 0) * 8;
6225
6226 if (INTEL_INFO(dev)->gen >= 4) {
6227 if (plane_config->tiled)
6228 offset = I915_READ(DSPTILEOFF(plane));
6229 else
6230 offset = I915_READ(DSPLINOFF(plane));
6231 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6232 } else {
6233 base = I915_READ(DSPADDR(plane));
6234 }
6235 plane_config->base = base;
6236
6237 val = I915_READ(PIPESRC(pipe));
6238 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6239 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6240
6241 val = I915_READ(DSPSTRIDE(pipe));
6242 crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
6243
6244 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6245 plane_config->tiled);
6246
6247 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6248 aligned_height);
6249
6250 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6251 pipe, plane, crtc->base.primary->fb->width,
6252 crtc->base.primary->fb->height,
6253 crtc->base.primary->fb->bits_per_pixel, base,
6254 crtc->base.primary->fb->pitches[0],
6255 plane_config->size);
6256
6257 }
6258
6259 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6260 struct intel_crtc_config *pipe_config)
6261 {
6262 struct drm_device *dev = crtc->base.dev;
6263 struct drm_i915_private *dev_priv = dev->dev_private;
6264 int pipe = pipe_config->cpu_transcoder;
6265 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6266 intel_clock_t clock;
6267 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6268 int refclk = 100000;
6269
6270 mutex_lock(&dev_priv->dpio_lock);
6271 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6272 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6273 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6274 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6275 mutex_unlock(&dev_priv->dpio_lock);
6276
6277 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6278 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6279 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6280 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6281 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6282
6283 chv_clock(refclk, &clock);
6284
6285 /* clock.dot is the fast clock */
6286 pipe_config->port_clock = clock.dot / 5;
6287 }
6288
6289 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6290 struct intel_crtc_config *pipe_config)
6291 {
6292 struct drm_device *dev = crtc->base.dev;
6293 struct drm_i915_private *dev_priv = dev->dev_private;
6294 uint32_t tmp;
6295
6296 if (!intel_display_power_enabled(dev_priv,
6297 POWER_DOMAIN_PIPE(crtc->pipe)))
6298 return false;
6299
6300 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6301 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6302
6303 tmp = I915_READ(PIPECONF(crtc->pipe));
6304 if (!(tmp & PIPECONF_ENABLE))
6305 return false;
6306
6307 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6308 switch (tmp & PIPECONF_BPC_MASK) {
6309 case PIPECONF_6BPC:
6310 pipe_config->pipe_bpp = 18;
6311 break;
6312 case PIPECONF_8BPC:
6313 pipe_config->pipe_bpp = 24;
6314 break;
6315 case PIPECONF_10BPC:
6316 pipe_config->pipe_bpp = 30;
6317 break;
6318 default:
6319 break;
6320 }
6321 }
6322
6323 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6324 pipe_config->limited_color_range = true;
6325
6326 if (INTEL_INFO(dev)->gen < 4)
6327 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6328
6329 intel_get_pipe_timings(crtc, pipe_config);
6330
6331 i9xx_get_pfit_config(crtc, pipe_config);
6332
6333 if (INTEL_INFO(dev)->gen >= 4) {
6334 tmp = I915_READ(DPLL_MD(crtc->pipe));
6335 pipe_config->pixel_multiplier =
6336 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6337 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6338 pipe_config->dpll_hw_state.dpll_md = tmp;
6339 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6340 tmp = I915_READ(DPLL(crtc->pipe));
6341 pipe_config->pixel_multiplier =
6342 ((tmp & SDVO_MULTIPLIER_MASK)
6343 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6344 } else {
6345 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6346 * port and will be fixed up in the encoder->get_config
6347 * function. */
6348 pipe_config->pixel_multiplier = 1;
6349 }
6350 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6351 if (!IS_VALLEYVIEW(dev)) {
6352 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6353 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6354 } else {
6355 /* Mask out read-only status bits. */
6356 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6357 DPLL_PORTC_READY_MASK |
6358 DPLL_PORTB_READY_MASK);
6359 }
6360
6361 if (IS_CHERRYVIEW(dev))
6362 chv_crtc_clock_get(crtc, pipe_config);
6363 else if (IS_VALLEYVIEW(dev))
6364 vlv_crtc_clock_get(crtc, pipe_config);
6365 else
6366 i9xx_crtc_clock_get(crtc, pipe_config);
6367
6368 return true;
6369 }
6370
6371 static void ironlake_init_pch_refclk(struct drm_device *dev)
6372 {
6373 struct drm_i915_private *dev_priv = dev->dev_private;
6374 struct drm_mode_config *mode_config = &dev->mode_config;
6375 struct intel_encoder *encoder;
6376 u32 val, final;
6377 bool has_lvds = false;
6378 bool has_cpu_edp = false;
6379 bool has_panel = false;
6380 bool has_ck505 = false;
6381 bool can_ssc = false;
6382
6383 /* We need to take the global config into account */
6384 list_for_each_entry(encoder, &mode_config->encoder_list,
6385 base.head) {
6386 switch (encoder->type) {
6387 case INTEL_OUTPUT_LVDS:
6388 has_panel = true;
6389 has_lvds = true;
6390 break;
6391 case INTEL_OUTPUT_EDP:
6392 has_panel = true;
6393 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6394 has_cpu_edp = true;
6395 break;
6396 }
6397 }
6398
6399 if (HAS_PCH_IBX(dev)) {
6400 has_ck505 = dev_priv->vbt.display_clock_mode;
6401 can_ssc = has_ck505;
6402 } else {
6403 has_ck505 = false;
6404 can_ssc = true;
6405 }
6406
6407 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6408 has_panel, has_lvds, has_ck505);
6409
6410 /* Ironlake: try to setup display ref clock before DPLL
6411 * enabling. This is only under driver's control after
6412 * PCH B stepping, previous chipset stepping should be
6413 * ignoring this setting.
6414 */
6415 val = I915_READ(PCH_DREF_CONTROL);
6416
6417 /* As we must carefully and slowly disable/enable each source in turn,
6418 * compute the final state we want first and check if we need to
6419 * make any changes at all.
6420 */
6421 final = val;
6422 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6423 if (has_ck505)
6424 final |= DREF_NONSPREAD_CK505_ENABLE;
6425 else
6426 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6427
6428 final &= ~DREF_SSC_SOURCE_MASK;
6429 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6430 final &= ~DREF_SSC1_ENABLE;
6431
6432 if (has_panel) {
6433 final |= DREF_SSC_SOURCE_ENABLE;
6434
6435 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6436 final |= DREF_SSC1_ENABLE;
6437
6438 if (has_cpu_edp) {
6439 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6440 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6441 else
6442 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6443 } else
6444 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6445 } else {
6446 final |= DREF_SSC_SOURCE_DISABLE;
6447 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6448 }
6449
6450 if (final == val)
6451 return;
6452
6453 /* Always enable nonspread source */
6454 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6455
6456 if (has_ck505)
6457 val |= DREF_NONSPREAD_CK505_ENABLE;
6458 else
6459 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6460
6461 if (has_panel) {
6462 val &= ~DREF_SSC_SOURCE_MASK;
6463 val |= DREF_SSC_SOURCE_ENABLE;
6464
6465 /* SSC must be turned on before enabling the CPU output */
6466 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6467 DRM_DEBUG_KMS("Using SSC on panel\n");
6468 val |= DREF_SSC1_ENABLE;
6469 } else
6470 val &= ~DREF_SSC1_ENABLE;
6471
6472 /* Get SSC going before enabling the outputs */
6473 I915_WRITE(PCH_DREF_CONTROL, val);
6474 POSTING_READ(PCH_DREF_CONTROL);
6475 udelay(200);
6476
6477 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6478
6479 /* Enable CPU source on CPU attached eDP */
6480 if (has_cpu_edp) {
6481 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6482 DRM_DEBUG_KMS("Using SSC on eDP\n");
6483 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6484 } else
6485 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6486 } else
6487 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6488
6489 I915_WRITE(PCH_DREF_CONTROL, val);
6490 POSTING_READ(PCH_DREF_CONTROL);
6491 udelay(200);
6492 } else {
6493 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6494
6495 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6496
6497 /* Turn off CPU output */
6498 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6499
6500 I915_WRITE(PCH_DREF_CONTROL, val);
6501 POSTING_READ(PCH_DREF_CONTROL);
6502 udelay(200);
6503
6504 /* Turn off the SSC source */
6505 val &= ~DREF_SSC_SOURCE_MASK;
6506 val |= DREF_SSC_SOURCE_DISABLE;
6507
6508 /* Turn off SSC1 */
6509 val &= ~DREF_SSC1_ENABLE;
6510
6511 I915_WRITE(PCH_DREF_CONTROL, val);
6512 POSTING_READ(PCH_DREF_CONTROL);
6513 udelay(200);
6514 }
6515
6516 BUG_ON(val != final);
6517 }
6518
6519 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6520 {
6521 uint32_t tmp;
6522
6523 tmp = I915_READ(SOUTH_CHICKEN2);
6524 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6525 I915_WRITE(SOUTH_CHICKEN2, tmp);
6526
6527 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6528 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6529 DRM_ERROR("FDI mPHY reset assert timeout\n");
6530
6531 tmp = I915_READ(SOUTH_CHICKEN2);
6532 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6533 I915_WRITE(SOUTH_CHICKEN2, tmp);
6534
6535 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6536 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6537 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6538 }
6539
6540 /* WaMPhyProgramming:hsw */
6541 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6542 {
6543 uint32_t tmp;
6544
6545 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6546 tmp &= ~(0xFF << 24);
6547 tmp |= (0x12 << 24);
6548 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6549
6550 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6551 tmp |= (1 << 11);
6552 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6553
6554 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6555 tmp |= (1 << 11);
6556 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6557
6558 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6559 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6560 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6561
6562 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6563 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6564 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6565
6566 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6567 tmp &= ~(7 << 13);
6568 tmp |= (5 << 13);
6569 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6570
6571 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6572 tmp &= ~(7 << 13);
6573 tmp |= (5 << 13);
6574 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6575
6576 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6577 tmp &= ~0xFF;
6578 tmp |= 0x1C;
6579 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6580
6581 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6582 tmp &= ~0xFF;
6583 tmp |= 0x1C;
6584 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6585
6586 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6587 tmp &= ~(0xFF << 16);
6588 tmp |= (0x1C << 16);
6589 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6590
6591 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6592 tmp &= ~(0xFF << 16);
6593 tmp |= (0x1C << 16);
6594 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6595
6596 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6597 tmp |= (1 << 27);
6598 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6599
6600 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6601 tmp |= (1 << 27);
6602 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6603
6604 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6605 tmp &= ~(0xF << 28);
6606 tmp |= (4 << 28);
6607 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6608
6609 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6610 tmp &= ~(0xF << 28);
6611 tmp |= (4 << 28);
6612 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6613 }
6614
6615 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6616 * Programming" based on the parameters passed:
6617 * - Sequence to enable CLKOUT_DP
6618 * - Sequence to enable CLKOUT_DP without spread
6619 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6620 */
6621 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6622 bool with_fdi)
6623 {
6624 struct drm_i915_private *dev_priv = dev->dev_private;
6625 uint32_t reg, tmp;
6626
6627 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6628 with_spread = true;
6629 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6630 with_fdi, "LP PCH doesn't have FDI\n"))
6631 with_fdi = false;
6632
6633 mutex_lock(&dev_priv->dpio_lock);
6634
6635 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6636 tmp &= ~SBI_SSCCTL_DISABLE;
6637 tmp |= SBI_SSCCTL_PATHALT;
6638 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6639
6640 udelay(24);
6641
6642 if (with_spread) {
6643 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6644 tmp &= ~SBI_SSCCTL_PATHALT;
6645 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6646
6647 if (with_fdi) {
6648 lpt_reset_fdi_mphy(dev_priv);
6649 lpt_program_fdi_mphy(dev_priv);
6650 }
6651 }
6652
6653 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6654 SBI_GEN0 : SBI_DBUFF0;
6655 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6656 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6657 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6658
6659 mutex_unlock(&dev_priv->dpio_lock);
6660 }
6661
6662 /* Sequence to disable CLKOUT_DP */
6663 static void lpt_disable_clkout_dp(struct drm_device *dev)
6664 {
6665 struct drm_i915_private *dev_priv = dev->dev_private;
6666 uint32_t reg, tmp;
6667
6668 mutex_lock(&dev_priv->dpio_lock);
6669
6670 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6671 SBI_GEN0 : SBI_DBUFF0;
6672 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6673 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6674 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6675
6676 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6677 if (!(tmp & SBI_SSCCTL_DISABLE)) {
6678 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6679 tmp |= SBI_SSCCTL_PATHALT;
6680 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6681 udelay(32);
6682 }
6683 tmp |= SBI_SSCCTL_DISABLE;
6684 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6685 }
6686
6687 mutex_unlock(&dev_priv->dpio_lock);
6688 }
6689
6690 static void lpt_init_pch_refclk(struct drm_device *dev)
6691 {
6692 struct drm_mode_config *mode_config = &dev->mode_config;
6693 struct intel_encoder *encoder;
6694 bool has_vga = false;
6695
6696 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
6697 switch (encoder->type) {
6698 case INTEL_OUTPUT_ANALOG:
6699 has_vga = true;
6700 break;
6701 }
6702 }
6703
6704 if (has_vga)
6705 lpt_enable_clkout_dp(dev, true, true);
6706 else
6707 lpt_disable_clkout_dp(dev);
6708 }
6709
6710 /*
6711 * Initialize reference clocks when the driver loads
6712 */
6713 void intel_init_pch_refclk(struct drm_device *dev)
6714 {
6715 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6716 ironlake_init_pch_refclk(dev);
6717 else if (HAS_PCH_LPT(dev))
6718 lpt_init_pch_refclk(dev);
6719 }
6720
6721 static int ironlake_get_refclk(struct drm_crtc *crtc)
6722 {
6723 struct drm_device *dev = crtc->dev;
6724 struct drm_i915_private *dev_priv = dev->dev_private;
6725 struct intel_encoder *encoder;
6726 int num_connectors = 0;
6727 bool is_lvds = false;
6728
6729 for_each_encoder_on_crtc(dev, crtc, encoder) {
6730 switch (encoder->type) {
6731 case INTEL_OUTPUT_LVDS:
6732 is_lvds = true;
6733 break;
6734 }
6735 num_connectors++;
6736 }
6737
6738 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6739 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6740 dev_priv->vbt.lvds_ssc_freq);
6741 return dev_priv->vbt.lvds_ssc_freq;
6742 }
6743
6744 return 120000;
6745 }
6746
6747 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6748 {
6749 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6750 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6751 int pipe = intel_crtc->pipe;
6752 uint32_t val;
6753
6754 val = 0;
6755
6756 switch (intel_crtc->config.pipe_bpp) {
6757 case 18:
6758 val |= PIPECONF_6BPC;
6759 break;
6760 case 24:
6761 val |= PIPECONF_8BPC;
6762 break;
6763 case 30:
6764 val |= PIPECONF_10BPC;
6765 break;
6766 case 36:
6767 val |= PIPECONF_12BPC;
6768 break;
6769 default:
6770 /* Case prevented by intel_choose_pipe_bpp_dither. */
6771 BUG();
6772 }
6773
6774 if (intel_crtc->config.dither)
6775 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6776
6777 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6778 val |= PIPECONF_INTERLACED_ILK;
6779 else
6780 val |= PIPECONF_PROGRESSIVE;
6781
6782 if (intel_crtc->config.limited_color_range)
6783 val |= PIPECONF_COLOR_RANGE_SELECT;
6784
6785 I915_WRITE(PIPECONF(pipe), val);
6786 POSTING_READ(PIPECONF(pipe));
6787 }
6788
6789 /*
6790 * Set up the pipe CSC unit.
6791 *
6792 * Currently only full range RGB to limited range RGB conversion
6793 * is supported, but eventually this should handle various
6794 * RGB<->YCbCr scenarios as well.
6795 */
6796 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6797 {
6798 struct drm_device *dev = crtc->dev;
6799 struct drm_i915_private *dev_priv = dev->dev_private;
6800 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6801 int pipe = intel_crtc->pipe;
6802 uint16_t coeff = 0x7800; /* 1.0 */
6803
6804 /*
6805 * TODO: Check what kind of values actually come out of the pipe
6806 * with these coeff/postoff values and adjust to get the best
6807 * accuracy. Perhaps we even need to take the bpc value into
6808 * consideration.
6809 */
6810
6811 if (intel_crtc->config.limited_color_range)
6812 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6813
6814 /*
6815 * GY/GU and RY/RU should be the other way around according
6816 * to BSpec, but reality doesn't agree. Just set them up in
6817 * a way that results in the correct picture.
6818 */
6819 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6820 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6821
6822 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6823 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6824
6825 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6826 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6827
6828 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6829 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6830 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6831
6832 if (INTEL_INFO(dev)->gen > 6) {
6833 uint16_t postoff = 0;
6834
6835 if (intel_crtc->config.limited_color_range)
6836 postoff = (16 * (1 << 12) / 255) & 0x1fff;
6837
6838 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6839 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6840 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6841
6842 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6843 } else {
6844 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6845
6846 if (intel_crtc->config.limited_color_range)
6847 mode |= CSC_BLACK_SCREEN_OFFSET;
6848
6849 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6850 }
6851 }
6852
6853 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6854 {
6855 struct drm_device *dev = crtc->dev;
6856 struct drm_i915_private *dev_priv = dev->dev_private;
6857 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6858 enum pipe pipe = intel_crtc->pipe;
6859 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6860 uint32_t val;
6861
6862 val = 0;
6863
6864 if (IS_HASWELL(dev) && intel_crtc->config.dither)
6865 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6866
6867 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6868 val |= PIPECONF_INTERLACED_ILK;
6869 else
6870 val |= PIPECONF_PROGRESSIVE;
6871
6872 I915_WRITE(PIPECONF(cpu_transcoder), val);
6873 POSTING_READ(PIPECONF(cpu_transcoder));
6874
6875 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6876 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6877
6878 if (IS_BROADWELL(dev)) {
6879 val = 0;
6880
6881 switch (intel_crtc->config.pipe_bpp) {
6882 case 18:
6883 val |= PIPEMISC_DITHER_6_BPC;
6884 break;
6885 case 24:
6886 val |= PIPEMISC_DITHER_8_BPC;
6887 break;
6888 case 30:
6889 val |= PIPEMISC_DITHER_10_BPC;
6890 break;
6891 case 36:
6892 val |= PIPEMISC_DITHER_12_BPC;
6893 break;
6894 default:
6895 /* Case prevented by pipe_config_set_bpp. */
6896 BUG();
6897 }
6898
6899 if (intel_crtc->config.dither)
6900 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6901
6902 I915_WRITE(PIPEMISC(pipe), val);
6903 }
6904 }
6905
6906 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6907 intel_clock_t *clock,
6908 bool *has_reduced_clock,
6909 intel_clock_t *reduced_clock)
6910 {
6911 struct drm_device *dev = crtc->dev;
6912 struct drm_i915_private *dev_priv = dev->dev_private;
6913 struct intel_encoder *intel_encoder;
6914 int refclk;
6915 const intel_limit_t *limit;
6916 bool ret, is_lvds = false;
6917
6918 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6919 switch (intel_encoder->type) {
6920 case INTEL_OUTPUT_LVDS:
6921 is_lvds = true;
6922 break;
6923 }
6924 }
6925
6926 refclk = ironlake_get_refclk(crtc);
6927
6928 /*
6929 * Returns a set of divisors for the desired target clock with the given
6930 * refclk, or FALSE. The returned values represent the clock equation:
6931 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6932 */
6933 limit = intel_limit(crtc, refclk);
6934 ret = dev_priv->display.find_dpll(limit, crtc,
6935 to_intel_crtc(crtc)->config.port_clock,
6936 refclk, NULL, clock);
6937 if (!ret)
6938 return false;
6939
6940 if (is_lvds && dev_priv->lvds_downclock_avail) {
6941 /*
6942 * Ensure we match the reduced clock's P to the target clock.
6943 * If the clocks don't match, we can't switch the display clock
6944 * by using the FP0/FP1. In such case we will disable the LVDS
6945 * downclock feature.
6946 */
6947 *has_reduced_clock =
6948 dev_priv->display.find_dpll(limit, crtc,
6949 dev_priv->lvds_downclock,
6950 refclk, clock,
6951 reduced_clock);
6952 }
6953
6954 return true;
6955 }
6956
6957 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6958 {
6959 /*
6960 * Account for spread spectrum to avoid
6961 * oversubscribing the link. Max center spread
6962 * is 2.5%; use 5% for safety's sake.
6963 */
6964 u32 bps = target_clock * bpp * 21 / 20;
6965 return DIV_ROUND_UP(bps, link_bw * 8);
6966 }
6967
6968 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6969 {
6970 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6971 }
6972
6973 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6974 u32 *fp,
6975 intel_clock_t *reduced_clock, u32 *fp2)
6976 {
6977 struct drm_crtc *crtc = &intel_crtc->base;
6978 struct drm_device *dev = crtc->dev;
6979 struct drm_i915_private *dev_priv = dev->dev_private;
6980 struct intel_encoder *intel_encoder;
6981 uint32_t dpll;
6982 int factor, num_connectors = 0;
6983 bool is_lvds = false, is_sdvo = false;
6984
6985 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6986 switch (intel_encoder->type) {
6987 case INTEL_OUTPUT_LVDS:
6988 is_lvds = true;
6989 break;
6990 case INTEL_OUTPUT_SDVO:
6991 case INTEL_OUTPUT_HDMI:
6992 is_sdvo = true;
6993 break;
6994 }
6995
6996 num_connectors++;
6997 }
6998
6999 /* Enable autotuning of the PLL clock (if permissible) */
7000 factor = 21;
7001 if (is_lvds) {
7002 if ((intel_panel_use_ssc(dev_priv) &&
7003 dev_priv->vbt.lvds_ssc_freq == 100000) ||
7004 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7005 factor = 25;
7006 } else if (intel_crtc->config.sdvo_tv_clock)
7007 factor = 20;
7008
7009 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7010 *fp |= FP_CB_TUNE;
7011
7012 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7013 *fp2 |= FP_CB_TUNE;
7014
7015 dpll = 0;
7016
7017 if (is_lvds)
7018 dpll |= DPLLB_MODE_LVDS;
7019 else
7020 dpll |= DPLLB_MODE_DAC_SERIAL;
7021
7022 dpll |= (intel_crtc->config.pixel_multiplier - 1)
7023 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7024
7025 if (is_sdvo)
7026 dpll |= DPLL_SDVO_HIGH_SPEED;
7027 if (intel_crtc->config.has_dp_encoder)
7028 dpll |= DPLL_SDVO_HIGH_SPEED;
7029
7030 /* compute bitmask from p1 value */
7031 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7032 /* also FPA1 */
7033 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7034
7035 switch (intel_crtc->config.dpll.p2) {
7036 case 5:
7037 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7038 break;
7039 case 7:
7040 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7041 break;
7042 case 10:
7043 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7044 break;
7045 case 14:
7046 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7047 break;
7048 }
7049
7050 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7051 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7052 else
7053 dpll |= PLL_REF_INPUT_DREFCLK;
7054
7055 return dpll | DPLL_VCO_ENABLE;
7056 }
7057
7058 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
7059 int x, int y,
7060 struct drm_framebuffer *fb)
7061 {
7062 struct drm_device *dev = crtc->dev;
7063 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7064 int num_connectors = 0;
7065 intel_clock_t clock, reduced_clock;
7066 u32 dpll = 0, fp = 0, fp2 = 0;
7067 bool ok, has_reduced_clock = false;
7068 bool is_lvds = false;
7069 struct intel_encoder *encoder;
7070 struct intel_shared_dpll *pll;
7071
7072 for_each_encoder_on_crtc(dev, crtc, encoder) {
7073 switch (encoder->type) {
7074 case INTEL_OUTPUT_LVDS:
7075 is_lvds = true;
7076 break;
7077 }
7078
7079 num_connectors++;
7080 }
7081
7082 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7083 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7084
7085 ok = ironlake_compute_clocks(crtc, &clock,
7086 &has_reduced_clock, &reduced_clock);
7087 if (!ok && !intel_crtc->config.clock_set) {
7088 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7089 return -EINVAL;
7090 }
7091 /* Compat-code for transition, will disappear. */
7092 if (!intel_crtc->config.clock_set) {
7093 intel_crtc->config.dpll.n = clock.n;
7094 intel_crtc->config.dpll.m1 = clock.m1;
7095 intel_crtc->config.dpll.m2 = clock.m2;
7096 intel_crtc->config.dpll.p1 = clock.p1;
7097 intel_crtc->config.dpll.p2 = clock.p2;
7098 }
7099
7100 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7101 if (intel_crtc->config.has_pch_encoder) {
7102 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
7103 if (has_reduced_clock)
7104 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7105
7106 dpll = ironlake_compute_dpll(intel_crtc,
7107 &fp, &reduced_clock,
7108 has_reduced_clock ? &fp2 : NULL);
7109
7110 intel_crtc->config.dpll_hw_state.dpll = dpll;
7111 intel_crtc->config.dpll_hw_state.fp0 = fp;
7112 if (has_reduced_clock)
7113 intel_crtc->config.dpll_hw_state.fp1 = fp2;
7114 else
7115 intel_crtc->config.dpll_hw_state.fp1 = fp;
7116
7117 pll = intel_get_shared_dpll(intel_crtc);
7118 if (pll == NULL) {
7119 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7120 pipe_name(intel_crtc->pipe));
7121 return -EINVAL;
7122 }
7123 } else
7124 intel_put_shared_dpll(intel_crtc);
7125
7126 if (is_lvds && has_reduced_clock && i915.powersave)
7127 intel_crtc->lowfreq_avail = true;
7128 else
7129 intel_crtc->lowfreq_avail = false;
7130
7131 return 0;
7132 }
7133
7134 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7135 struct intel_link_m_n *m_n)
7136 {
7137 struct drm_device *dev = crtc->base.dev;
7138 struct drm_i915_private *dev_priv = dev->dev_private;
7139 enum pipe pipe = crtc->pipe;
7140
7141 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7142 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7143 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7144 & ~TU_SIZE_MASK;
7145 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7146 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7147 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7148 }
7149
7150 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7151 enum transcoder transcoder,
7152 struct intel_link_m_n *m_n)
7153 {
7154 struct drm_device *dev = crtc->base.dev;
7155 struct drm_i915_private *dev_priv = dev->dev_private;
7156 enum pipe pipe = crtc->pipe;
7157
7158 if (INTEL_INFO(dev)->gen >= 5) {
7159 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7160 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7161 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7162 & ~TU_SIZE_MASK;
7163 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7164 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7165 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7166 } else {
7167 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7168 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7169 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7170 & ~TU_SIZE_MASK;
7171 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7172 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7173 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7174 }
7175 }
7176
7177 void intel_dp_get_m_n(struct intel_crtc *crtc,
7178 struct intel_crtc_config *pipe_config)
7179 {
7180 if (crtc->config.has_pch_encoder)
7181 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7182 else
7183 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7184 &pipe_config->dp_m_n);
7185 }
7186
7187 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7188 struct intel_crtc_config *pipe_config)
7189 {
7190 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7191 &pipe_config->fdi_m_n);
7192 }
7193
7194 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7195 struct intel_crtc_config *pipe_config)
7196 {
7197 struct drm_device *dev = crtc->base.dev;
7198 struct drm_i915_private *dev_priv = dev->dev_private;
7199 uint32_t tmp;
7200
7201 tmp = I915_READ(PF_CTL(crtc->pipe));
7202
7203 if (tmp & PF_ENABLE) {
7204 pipe_config->pch_pfit.enabled = true;
7205 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7206 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7207
7208 /* We currently do not free assignements of panel fitters on
7209 * ivb/hsw (since we don't use the higher upscaling modes which
7210 * differentiates them) so just WARN about this case for now. */
7211 if (IS_GEN7(dev)) {
7212 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7213 PF_PIPE_SEL_IVB(crtc->pipe));
7214 }
7215 }
7216 }
7217
7218 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7219 struct intel_plane_config *plane_config)
7220 {
7221 struct drm_device *dev = crtc->base.dev;
7222 struct drm_i915_private *dev_priv = dev->dev_private;
7223 u32 val, base, offset;
7224 int pipe = crtc->pipe, plane = crtc->plane;
7225 int fourcc, pixel_format;
7226 int aligned_height;
7227
7228 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7229 if (!crtc->base.primary->fb) {
7230 DRM_DEBUG_KMS("failed to alloc fb\n");
7231 return;
7232 }
7233
7234 val = I915_READ(DSPCNTR(plane));
7235
7236 if (INTEL_INFO(dev)->gen >= 4)
7237 if (val & DISPPLANE_TILED)
7238 plane_config->tiled = true;
7239
7240 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7241 fourcc = intel_format_to_fourcc(pixel_format);
7242 crtc->base.primary->fb->pixel_format = fourcc;
7243 crtc->base.primary->fb->bits_per_pixel =
7244 drm_format_plane_cpp(fourcc, 0) * 8;
7245
7246 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7247 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7248 offset = I915_READ(DSPOFFSET(plane));
7249 } else {
7250 if (plane_config->tiled)
7251 offset = I915_READ(DSPTILEOFF(plane));
7252 else
7253 offset = I915_READ(DSPLINOFF(plane));
7254 }
7255 plane_config->base = base;
7256
7257 val = I915_READ(PIPESRC(pipe));
7258 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7259 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7260
7261 val = I915_READ(DSPSTRIDE(pipe));
7262 crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
7263
7264 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7265 plane_config->tiled);
7266
7267 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7268 aligned_height);
7269
7270 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7271 pipe, plane, crtc->base.primary->fb->width,
7272 crtc->base.primary->fb->height,
7273 crtc->base.primary->fb->bits_per_pixel, base,
7274 crtc->base.primary->fb->pitches[0],
7275 plane_config->size);
7276 }
7277
7278 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7279 struct intel_crtc_config *pipe_config)
7280 {
7281 struct drm_device *dev = crtc->base.dev;
7282 struct drm_i915_private *dev_priv = dev->dev_private;
7283 uint32_t tmp;
7284
7285 if (!intel_display_power_enabled(dev_priv,
7286 POWER_DOMAIN_PIPE(crtc->pipe)))
7287 return false;
7288
7289 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7290 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7291
7292 tmp = I915_READ(PIPECONF(crtc->pipe));
7293 if (!(tmp & PIPECONF_ENABLE))
7294 return false;
7295
7296 switch (tmp & PIPECONF_BPC_MASK) {
7297 case PIPECONF_6BPC:
7298 pipe_config->pipe_bpp = 18;
7299 break;
7300 case PIPECONF_8BPC:
7301 pipe_config->pipe_bpp = 24;
7302 break;
7303 case PIPECONF_10BPC:
7304 pipe_config->pipe_bpp = 30;
7305 break;
7306 case PIPECONF_12BPC:
7307 pipe_config->pipe_bpp = 36;
7308 break;
7309 default:
7310 break;
7311 }
7312
7313 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7314 pipe_config->limited_color_range = true;
7315
7316 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7317 struct intel_shared_dpll *pll;
7318
7319 pipe_config->has_pch_encoder = true;
7320
7321 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7322 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7323 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7324
7325 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7326
7327 if (HAS_PCH_IBX(dev_priv->dev)) {
7328 pipe_config->shared_dpll =
7329 (enum intel_dpll_id) crtc->pipe;
7330 } else {
7331 tmp = I915_READ(PCH_DPLL_SEL);
7332 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7333 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7334 else
7335 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7336 }
7337
7338 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7339
7340 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7341 &pipe_config->dpll_hw_state));
7342
7343 tmp = pipe_config->dpll_hw_state.dpll;
7344 pipe_config->pixel_multiplier =
7345 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7346 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7347
7348 ironlake_pch_clock_get(crtc, pipe_config);
7349 } else {
7350 pipe_config->pixel_multiplier = 1;
7351 }
7352
7353 intel_get_pipe_timings(crtc, pipe_config);
7354
7355 ironlake_get_pfit_config(crtc, pipe_config);
7356
7357 return true;
7358 }
7359
7360 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7361 {
7362 struct drm_device *dev = dev_priv->dev;
7363 struct intel_crtc *crtc;
7364
7365 for_each_intel_crtc(dev, crtc)
7366 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7367 pipe_name(crtc->pipe));
7368
7369 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7370 WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7371 WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7372 WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7373 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7374 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7375 "CPU PWM1 enabled\n");
7376 if (IS_HASWELL(dev))
7377 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7378 "CPU PWM2 enabled\n");
7379 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7380 "PCH PWM1 enabled\n");
7381 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7382 "Utility pin enabled\n");
7383 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7384
7385 /*
7386 * In theory we can still leave IRQs enabled, as long as only the HPD
7387 * interrupts remain enabled. We used to check for that, but since it's
7388 * gen-specific and since we only disable LCPLL after we fully disable
7389 * the interrupts, the check below should be enough.
7390 */
7391 WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7392 }
7393
7394 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7395 {
7396 struct drm_device *dev = dev_priv->dev;
7397
7398 if (IS_HASWELL(dev))
7399 return I915_READ(D_COMP_HSW);
7400 else
7401 return I915_READ(D_COMP_BDW);
7402 }
7403
7404 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7405 {
7406 struct drm_device *dev = dev_priv->dev;
7407
7408 if (IS_HASWELL(dev)) {
7409 mutex_lock(&dev_priv->rps.hw_lock);
7410 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7411 val))
7412 DRM_ERROR("Failed to write to D_COMP\n");
7413 mutex_unlock(&dev_priv->rps.hw_lock);
7414 } else {
7415 I915_WRITE(D_COMP_BDW, val);
7416 POSTING_READ(D_COMP_BDW);
7417 }
7418 }
7419
7420 /*
7421 * This function implements pieces of two sequences from BSpec:
7422 * - Sequence for display software to disable LCPLL
7423 * - Sequence for display software to allow package C8+
7424 * The steps implemented here are just the steps that actually touch the LCPLL
7425 * register. Callers should take care of disabling all the display engine
7426 * functions, doing the mode unset, fixing interrupts, etc.
7427 */
7428 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7429 bool switch_to_fclk, bool allow_power_down)
7430 {
7431 uint32_t val;
7432
7433 assert_can_disable_lcpll(dev_priv);
7434
7435 val = I915_READ(LCPLL_CTL);
7436
7437 if (switch_to_fclk) {
7438 val |= LCPLL_CD_SOURCE_FCLK;
7439 I915_WRITE(LCPLL_CTL, val);
7440
7441 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7442 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7443 DRM_ERROR("Switching to FCLK failed\n");
7444
7445 val = I915_READ(LCPLL_CTL);
7446 }
7447
7448 val |= LCPLL_PLL_DISABLE;
7449 I915_WRITE(LCPLL_CTL, val);
7450 POSTING_READ(LCPLL_CTL);
7451
7452 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7453 DRM_ERROR("LCPLL still locked\n");
7454
7455 val = hsw_read_dcomp(dev_priv);
7456 val |= D_COMP_COMP_DISABLE;
7457 hsw_write_dcomp(dev_priv, val);
7458 ndelay(100);
7459
7460 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7461 1))
7462 DRM_ERROR("D_COMP RCOMP still in progress\n");
7463
7464 if (allow_power_down) {
7465 val = I915_READ(LCPLL_CTL);
7466 val |= LCPLL_POWER_DOWN_ALLOW;
7467 I915_WRITE(LCPLL_CTL, val);
7468 POSTING_READ(LCPLL_CTL);
7469 }
7470 }
7471
7472 /*
7473 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7474 * source.
7475 */
7476 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7477 {
7478 uint32_t val;
7479 unsigned long irqflags;
7480
7481 val = I915_READ(LCPLL_CTL);
7482
7483 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7484 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7485 return;
7486
7487 /*
7488 * Make sure we're not on PC8 state before disabling PC8, otherwise
7489 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7490 *
7491 * The other problem is that hsw_restore_lcpll() is called as part of
7492 * the runtime PM resume sequence, so we can't just call
7493 * gen6_gt_force_wake_get() because that function calls
7494 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7495 * while we are on the resume sequence. So to solve this problem we have
7496 * to call special forcewake code that doesn't touch runtime PM and
7497 * doesn't enable the forcewake delayed work.
7498 */
7499 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7500 if (dev_priv->uncore.forcewake_count++ == 0)
7501 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7502 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7503
7504 if (val & LCPLL_POWER_DOWN_ALLOW) {
7505 val &= ~LCPLL_POWER_DOWN_ALLOW;
7506 I915_WRITE(LCPLL_CTL, val);
7507 POSTING_READ(LCPLL_CTL);
7508 }
7509
7510 val = hsw_read_dcomp(dev_priv);
7511 val |= D_COMP_COMP_FORCE;
7512 val &= ~D_COMP_COMP_DISABLE;
7513 hsw_write_dcomp(dev_priv, val);
7514
7515 val = I915_READ(LCPLL_CTL);
7516 val &= ~LCPLL_PLL_DISABLE;
7517 I915_WRITE(LCPLL_CTL, val);
7518
7519 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7520 DRM_ERROR("LCPLL not locked yet\n");
7521
7522 if (val & LCPLL_CD_SOURCE_FCLK) {
7523 val = I915_READ(LCPLL_CTL);
7524 val &= ~LCPLL_CD_SOURCE_FCLK;
7525 I915_WRITE(LCPLL_CTL, val);
7526
7527 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7528 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7529 DRM_ERROR("Switching back to LCPLL failed\n");
7530 }
7531
7532 /* See the big comment above. */
7533 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7534 if (--dev_priv->uncore.forcewake_count == 0)
7535 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7536 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7537 }
7538
7539 /*
7540 * Package states C8 and deeper are really deep PC states that can only be
7541 * reached when all the devices on the system allow it, so even if the graphics
7542 * device allows PC8+, it doesn't mean the system will actually get to these
7543 * states. Our driver only allows PC8+ when going into runtime PM.
7544 *
7545 * The requirements for PC8+ are that all the outputs are disabled, the power
7546 * well is disabled and most interrupts are disabled, and these are also
7547 * requirements for runtime PM. When these conditions are met, we manually do
7548 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7549 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7550 * hang the machine.
7551 *
7552 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7553 * the state of some registers, so when we come back from PC8+ we need to
7554 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7555 * need to take care of the registers kept by RC6. Notice that this happens even
7556 * if we don't put the device in PCI D3 state (which is what currently happens
7557 * because of the runtime PM support).
7558 *
7559 * For more, read "Display Sequences for Package C8" on the hardware
7560 * documentation.
7561 */
7562 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7563 {
7564 struct drm_device *dev = dev_priv->dev;
7565 uint32_t val;
7566
7567 DRM_DEBUG_KMS("Enabling package C8+\n");
7568
7569 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7570 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7571 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7572 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7573 }
7574
7575 lpt_disable_clkout_dp(dev);
7576 hsw_disable_lcpll(dev_priv, true, true);
7577 }
7578
7579 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7580 {
7581 struct drm_device *dev = dev_priv->dev;
7582 uint32_t val;
7583
7584 DRM_DEBUG_KMS("Disabling package C8+\n");
7585
7586 hsw_restore_lcpll(dev_priv);
7587 lpt_init_pch_refclk(dev);
7588
7589 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7590 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7591 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7592 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7593 }
7594
7595 intel_prepare_ddi(dev);
7596 }
7597
7598 static void snb_modeset_global_resources(struct drm_device *dev)
7599 {
7600 modeset_update_crtc_power_domains(dev);
7601 }
7602
7603 static void haswell_modeset_global_resources(struct drm_device *dev)
7604 {
7605 modeset_update_crtc_power_domains(dev);
7606 }
7607
7608 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7609 int x, int y,
7610 struct drm_framebuffer *fb)
7611 {
7612 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7613
7614 if (!intel_ddi_pll_select(intel_crtc))
7615 return -EINVAL;
7616
7617 intel_crtc->lowfreq_avail = false;
7618
7619 return 0;
7620 }
7621
7622 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
7623 struct intel_crtc_config *pipe_config)
7624 {
7625 struct drm_device *dev = crtc->base.dev;
7626 struct drm_i915_private *dev_priv = dev->dev_private;
7627 struct intel_shared_dpll *pll;
7628 enum port port;
7629 uint32_t tmp;
7630
7631 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7632
7633 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
7634
7635 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
7636
7637 switch (pipe_config->ddi_pll_sel) {
7638 case PORT_CLK_SEL_WRPLL1:
7639 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7640 break;
7641 case PORT_CLK_SEL_WRPLL2:
7642 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7643 break;
7644 }
7645
7646 if (pipe_config->shared_dpll >= 0) {
7647 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7648
7649 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7650 &pipe_config->dpll_hw_state));
7651 }
7652
7653 /*
7654 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7655 * DDI E. So just check whether this pipe is wired to DDI E and whether
7656 * the PCH transcoder is on.
7657 */
7658 if ((port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7659 pipe_config->has_pch_encoder = true;
7660
7661 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7662 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7663 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7664
7665 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7666 }
7667 }
7668
7669 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7670 struct intel_crtc_config *pipe_config)
7671 {
7672 struct drm_device *dev = crtc->base.dev;
7673 struct drm_i915_private *dev_priv = dev->dev_private;
7674 enum intel_display_power_domain pfit_domain;
7675 uint32_t tmp;
7676
7677 if (!intel_display_power_enabled(dev_priv,
7678 POWER_DOMAIN_PIPE(crtc->pipe)))
7679 return false;
7680
7681 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7682 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7683
7684 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7685 if (tmp & TRANS_DDI_FUNC_ENABLE) {
7686 enum pipe trans_edp_pipe;
7687 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7688 default:
7689 WARN(1, "unknown pipe linked to edp transcoder\n");
7690 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7691 case TRANS_DDI_EDP_INPUT_A_ON:
7692 trans_edp_pipe = PIPE_A;
7693 break;
7694 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7695 trans_edp_pipe = PIPE_B;
7696 break;
7697 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7698 trans_edp_pipe = PIPE_C;
7699 break;
7700 }
7701
7702 if (trans_edp_pipe == crtc->pipe)
7703 pipe_config->cpu_transcoder = TRANSCODER_EDP;
7704 }
7705
7706 if (!intel_display_power_enabled(dev_priv,
7707 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7708 return false;
7709
7710 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7711 if (!(tmp & PIPECONF_ENABLE))
7712 return false;
7713
7714 haswell_get_ddi_port_state(crtc, pipe_config);
7715
7716 intel_get_pipe_timings(crtc, pipe_config);
7717
7718 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7719 if (intel_display_power_enabled(dev_priv, pfit_domain))
7720 ironlake_get_pfit_config(crtc, pipe_config);
7721
7722 if (IS_HASWELL(dev))
7723 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7724 (I915_READ(IPS_CTL) & IPS_ENABLE);
7725
7726 pipe_config->pixel_multiplier = 1;
7727
7728 return true;
7729 }
7730
7731 static struct {
7732 int clock;
7733 u32 config;
7734 } hdmi_audio_clock[] = {
7735 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7736 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7737 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7738 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7739 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7740 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7741 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7742 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7743 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7744 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7745 };
7746
7747 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7748 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7749 {
7750 int i;
7751
7752 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7753 if (mode->clock == hdmi_audio_clock[i].clock)
7754 break;
7755 }
7756
7757 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7758 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7759 i = 1;
7760 }
7761
7762 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7763 hdmi_audio_clock[i].clock,
7764 hdmi_audio_clock[i].config);
7765
7766 return hdmi_audio_clock[i].config;
7767 }
7768
7769 static bool intel_eld_uptodate(struct drm_connector *connector,
7770 int reg_eldv, uint32_t bits_eldv,
7771 int reg_elda, uint32_t bits_elda,
7772 int reg_edid)
7773 {
7774 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7775 uint8_t *eld = connector->eld;
7776 uint32_t i;
7777
7778 i = I915_READ(reg_eldv);
7779 i &= bits_eldv;
7780
7781 if (!eld[0])
7782 return !i;
7783
7784 if (!i)
7785 return false;
7786
7787 i = I915_READ(reg_elda);
7788 i &= ~bits_elda;
7789 I915_WRITE(reg_elda, i);
7790
7791 for (i = 0; i < eld[2]; i++)
7792 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7793 return false;
7794
7795 return true;
7796 }
7797
7798 static void g4x_write_eld(struct drm_connector *connector,
7799 struct drm_crtc *crtc,
7800 struct drm_display_mode *mode)
7801 {
7802 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7803 uint8_t *eld = connector->eld;
7804 uint32_t eldv;
7805 uint32_t len;
7806 uint32_t i;
7807
7808 i = I915_READ(G4X_AUD_VID_DID);
7809
7810 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7811 eldv = G4X_ELDV_DEVCL_DEVBLC;
7812 else
7813 eldv = G4X_ELDV_DEVCTG;
7814
7815 if (intel_eld_uptodate(connector,
7816 G4X_AUD_CNTL_ST, eldv,
7817 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7818 G4X_HDMIW_HDMIEDID))
7819 return;
7820
7821 i = I915_READ(G4X_AUD_CNTL_ST);
7822 i &= ~(eldv | G4X_ELD_ADDR);
7823 len = (i >> 9) & 0x1f; /* ELD buffer size */
7824 I915_WRITE(G4X_AUD_CNTL_ST, i);
7825
7826 if (!eld[0])
7827 return;
7828
7829 len = min_t(uint8_t, eld[2], len);
7830 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7831 for (i = 0; i < len; i++)
7832 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7833
7834 i = I915_READ(G4X_AUD_CNTL_ST);
7835 i |= eldv;
7836 I915_WRITE(G4X_AUD_CNTL_ST, i);
7837 }
7838
7839 static void haswell_write_eld(struct drm_connector *connector,
7840 struct drm_crtc *crtc,
7841 struct drm_display_mode *mode)
7842 {
7843 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7844 uint8_t *eld = connector->eld;
7845 uint32_t eldv;
7846 uint32_t i;
7847 int len;
7848 int pipe = to_intel_crtc(crtc)->pipe;
7849 int tmp;
7850
7851 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7852 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7853 int aud_config = HSW_AUD_CFG(pipe);
7854 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7855
7856 /* Audio output enable */
7857 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7858 tmp = I915_READ(aud_cntrl_st2);
7859 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7860 I915_WRITE(aud_cntrl_st2, tmp);
7861 POSTING_READ(aud_cntrl_st2);
7862
7863 assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
7864
7865 /* Set ELD valid state */
7866 tmp = I915_READ(aud_cntrl_st2);
7867 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7868 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7869 I915_WRITE(aud_cntrl_st2, tmp);
7870 tmp = I915_READ(aud_cntrl_st2);
7871 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7872
7873 /* Enable HDMI mode */
7874 tmp = I915_READ(aud_config);
7875 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7876 /* clear N_programing_enable and N_value_index */
7877 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7878 I915_WRITE(aud_config, tmp);
7879
7880 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7881
7882 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7883
7884 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7885 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7886 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7887 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7888 } else {
7889 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7890 }
7891
7892 if (intel_eld_uptodate(connector,
7893 aud_cntrl_st2, eldv,
7894 aud_cntl_st, IBX_ELD_ADDRESS,
7895 hdmiw_hdmiedid))
7896 return;
7897
7898 i = I915_READ(aud_cntrl_st2);
7899 i &= ~eldv;
7900 I915_WRITE(aud_cntrl_st2, i);
7901
7902 if (!eld[0])
7903 return;
7904
7905 i = I915_READ(aud_cntl_st);
7906 i &= ~IBX_ELD_ADDRESS;
7907 I915_WRITE(aud_cntl_st, i);
7908 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
7909 DRM_DEBUG_DRIVER("port num:%d\n", i);
7910
7911 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7912 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7913 for (i = 0; i < len; i++)
7914 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7915
7916 i = I915_READ(aud_cntrl_st2);
7917 i |= eldv;
7918 I915_WRITE(aud_cntrl_st2, i);
7919
7920 }
7921
7922 static void ironlake_write_eld(struct drm_connector *connector,
7923 struct drm_crtc *crtc,
7924 struct drm_display_mode *mode)
7925 {
7926 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7927 uint8_t *eld = connector->eld;
7928 uint32_t eldv;
7929 uint32_t i;
7930 int len;
7931 int hdmiw_hdmiedid;
7932 int aud_config;
7933 int aud_cntl_st;
7934 int aud_cntrl_st2;
7935 int pipe = to_intel_crtc(crtc)->pipe;
7936
7937 if (HAS_PCH_IBX(connector->dev)) {
7938 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7939 aud_config = IBX_AUD_CFG(pipe);
7940 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7941 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7942 } else if (IS_VALLEYVIEW(connector->dev)) {
7943 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7944 aud_config = VLV_AUD_CFG(pipe);
7945 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7946 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7947 } else {
7948 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7949 aud_config = CPT_AUD_CFG(pipe);
7950 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7951 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7952 }
7953
7954 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7955
7956 if (IS_VALLEYVIEW(connector->dev)) {
7957 struct intel_encoder *intel_encoder;
7958 struct intel_digital_port *intel_dig_port;
7959
7960 intel_encoder = intel_attached_encoder(connector);
7961 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7962 i = intel_dig_port->port;
7963 } else {
7964 i = I915_READ(aud_cntl_st);
7965 i = (i >> 29) & DIP_PORT_SEL_MASK;
7966 /* DIP_Port_Select, 0x1 = PortB */
7967 }
7968
7969 if (!i) {
7970 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7971 /* operate blindly on all ports */
7972 eldv = IBX_ELD_VALIDB;
7973 eldv |= IBX_ELD_VALIDB << 4;
7974 eldv |= IBX_ELD_VALIDB << 8;
7975 } else {
7976 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7977 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7978 }
7979
7980 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7981 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7982 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7983 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7984 } else {
7985 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7986 }
7987
7988 if (intel_eld_uptodate(connector,
7989 aud_cntrl_st2, eldv,
7990 aud_cntl_st, IBX_ELD_ADDRESS,
7991 hdmiw_hdmiedid))
7992 return;
7993
7994 i = I915_READ(aud_cntrl_st2);
7995 i &= ~eldv;
7996 I915_WRITE(aud_cntrl_st2, i);
7997
7998 if (!eld[0])
7999 return;
8000
8001 i = I915_READ(aud_cntl_st);
8002 i &= ~IBX_ELD_ADDRESS;
8003 I915_WRITE(aud_cntl_st, i);
8004
8005 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
8006 DRM_DEBUG_DRIVER("ELD size %d\n", len);
8007 for (i = 0; i < len; i++)
8008 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
8009
8010 i = I915_READ(aud_cntrl_st2);
8011 i |= eldv;
8012 I915_WRITE(aud_cntrl_st2, i);
8013 }
8014
8015 void intel_write_eld(struct drm_encoder *encoder,
8016 struct drm_display_mode *mode)
8017 {
8018 struct drm_crtc *crtc = encoder->crtc;
8019 struct drm_connector *connector;
8020 struct drm_device *dev = encoder->dev;
8021 struct drm_i915_private *dev_priv = dev->dev_private;
8022
8023 connector = drm_select_eld(encoder, mode);
8024 if (!connector)
8025 return;
8026
8027 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8028 connector->base.id,
8029 connector->name,
8030 connector->encoder->base.id,
8031 connector->encoder->name);
8032
8033 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
8034
8035 if (dev_priv->display.write_eld)
8036 dev_priv->display.write_eld(connector, crtc, mode);
8037 }
8038
8039 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8040 {
8041 struct drm_device *dev = crtc->dev;
8042 struct drm_i915_private *dev_priv = dev->dev_private;
8043 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8044 uint32_t cntl;
8045
8046 if (base != intel_crtc->cursor_base) {
8047 /* On these chipsets we can only modify the base whilst
8048 * the cursor is disabled.
8049 */
8050 if (intel_crtc->cursor_cntl) {
8051 I915_WRITE(_CURACNTR, 0);
8052 POSTING_READ(_CURACNTR);
8053 intel_crtc->cursor_cntl = 0;
8054 }
8055
8056 I915_WRITE(_CURABASE, base);
8057 POSTING_READ(_CURABASE);
8058 }
8059
8060 /* XXX width must be 64, stride 256 => 0x00 << 28 */
8061 cntl = 0;
8062 if (base)
8063 cntl = (CURSOR_ENABLE |
8064 CURSOR_GAMMA_ENABLE |
8065 CURSOR_FORMAT_ARGB);
8066 if (intel_crtc->cursor_cntl != cntl) {
8067 I915_WRITE(_CURACNTR, cntl);
8068 POSTING_READ(_CURACNTR);
8069 intel_crtc->cursor_cntl = cntl;
8070 }
8071 }
8072
8073 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8074 {
8075 struct drm_device *dev = crtc->dev;
8076 struct drm_i915_private *dev_priv = dev->dev_private;
8077 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8078 int pipe = intel_crtc->pipe;
8079 uint32_t cntl;
8080
8081 cntl = 0;
8082 if (base) {
8083 cntl = MCURSOR_GAMMA_ENABLE;
8084 switch (intel_crtc->cursor_width) {
8085 case 64:
8086 cntl |= CURSOR_MODE_64_ARGB_AX;
8087 break;
8088 case 128:
8089 cntl |= CURSOR_MODE_128_ARGB_AX;
8090 break;
8091 case 256:
8092 cntl |= CURSOR_MODE_256_ARGB_AX;
8093 break;
8094 default:
8095 WARN_ON(1);
8096 return;
8097 }
8098 cntl |= pipe << 28; /* Connect to correct pipe */
8099 }
8100 if (intel_crtc->cursor_cntl != cntl) {
8101 I915_WRITE(CURCNTR(pipe), cntl);
8102 POSTING_READ(CURCNTR(pipe));
8103 intel_crtc->cursor_cntl = cntl;
8104 }
8105
8106 /* and commit changes on next vblank */
8107 I915_WRITE(CURBASE(pipe), base);
8108 POSTING_READ(CURBASE(pipe));
8109 }
8110
8111 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
8112 {
8113 struct drm_device *dev = crtc->dev;
8114 struct drm_i915_private *dev_priv = dev->dev_private;
8115 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8116 int pipe = intel_crtc->pipe;
8117 uint32_t cntl;
8118
8119 cntl = 0;
8120 if (base) {
8121 cntl = MCURSOR_GAMMA_ENABLE;
8122 switch (intel_crtc->cursor_width) {
8123 case 64:
8124 cntl |= CURSOR_MODE_64_ARGB_AX;
8125 break;
8126 case 128:
8127 cntl |= CURSOR_MODE_128_ARGB_AX;
8128 break;
8129 case 256:
8130 cntl |= CURSOR_MODE_256_ARGB_AX;
8131 break;
8132 default:
8133 WARN_ON(1);
8134 return;
8135 }
8136 }
8137 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8138 cntl |= CURSOR_PIPE_CSC_ENABLE;
8139
8140 if (intel_crtc->cursor_cntl != cntl) {
8141 I915_WRITE(CURCNTR(pipe), cntl);
8142 POSTING_READ(CURCNTR(pipe));
8143 intel_crtc->cursor_cntl = cntl;
8144 }
8145
8146 /* and commit changes on next vblank */
8147 I915_WRITE(CURBASE(pipe), base);
8148 POSTING_READ(CURBASE(pipe));
8149 }
8150
8151 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8152 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8153 bool on)
8154 {
8155 struct drm_device *dev = crtc->dev;
8156 struct drm_i915_private *dev_priv = dev->dev_private;
8157 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8158 int pipe = intel_crtc->pipe;
8159 int x = crtc->cursor_x;
8160 int y = crtc->cursor_y;
8161 u32 base = 0, pos = 0;
8162
8163 if (on)
8164 base = intel_crtc->cursor_addr;
8165
8166 if (x >= intel_crtc->config.pipe_src_w)
8167 base = 0;
8168
8169 if (y >= intel_crtc->config.pipe_src_h)
8170 base = 0;
8171
8172 if (x < 0) {
8173 if (x + intel_crtc->cursor_width <= 0)
8174 base = 0;
8175
8176 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8177 x = -x;
8178 }
8179 pos |= x << CURSOR_X_SHIFT;
8180
8181 if (y < 0) {
8182 if (y + intel_crtc->cursor_height <= 0)
8183 base = 0;
8184
8185 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8186 y = -y;
8187 }
8188 pos |= y << CURSOR_Y_SHIFT;
8189
8190 if (base == 0 && intel_crtc->cursor_base == 0)
8191 return;
8192
8193 I915_WRITE(CURPOS(pipe), pos);
8194
8195 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev))
8196 ivb_update_cursor(crtc, base);
8197 else if (IS_845G(dev) || IS_I865G(dev))
8198 i845_update_cursor(crtc, base);
8199 else
8200 i9xx_update_cursor(crtc, base);
8201 intel_crtc->cursor_base = base;
8202 }
8203
8204 /*
8205 * intel_crtc_cursor_set_obj - Set cursor to specified GEM object
8206 *
8207 * Note that the object's reference will be consumed if the update fails. If
8208 * the update succeeds, the reference of the old object (if any) will be
8209 * consumed.
8210 */
8211 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8212 struct drm_i915_gem_object *obj,
8213 uint32_t width, uint32_t height)
8214 {
8215 struct drm_device *dev = crtc->dev;
8216 struct drm_i915_private *dev_priv = dev->dev_private;
8217 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8218 enum pipe pipe = intel_crtc->pipe;
8219 unsigned old_width;
8220 uint32_t addr;
8221 int ret;
8222
8223 /* if we want to turn off the cursor ignore width and height */
8224 if (!obj) {
8225 DRM_DEBUG_KMS("cursor off\n");
8226 addr = 0;
8227 obj = NULL;
8228 mutex_lock(&dev->struct_mutex);
8229 goto finish;
8230 }
8231
8232 /* Check for which cursor types we support */
8233 if (!((width == 64 && height == 64) ||
8234 (width == 128 && height == 128 && !IS_GEN2(dev)) ||
8235 (width == 256 && height == 256 && !IS_GEN2(dev)))) {
8236 DRM_DEBUG("Cursor dimension not supported\n");
8237 return -EINVAL;
8238 }
8239
8240 if (obj->base.size < width * height * 4) {
8241 DRM_DEBUG_KMS("buffer is too small\n");
8242 ret = -ENOMEM;
8243 goto fail;
8244 }
8245
8246 /* we only need to pin inside GTT if cursor is non-phy */
8247 mutex_lock(&dev->struct_mutex);
8248 if (!INTEL_INFO(dev)->cursor_needs_physical) {
8249 unsigned alignment;
8250
8251 if (obj->tiling_mode) {
8252 DRM_DEBUG_KMS("cursor cannot be tiled\n");
8253 ret = -EINVAL;
8254 goto fail_locked;
8255 }
8256
8257 /* Note that the w/a also requires 2 PTE of padding following
8258 * the bo. We currently fill all unused PTE with the shadow
8259 * page and so we should always have valid PTE following the
8260 * cursor preventing the VT-d warning.
8261 */
8262 alignment = 0;
8263 if (need_vtd_wa(dev))
8264 alignment = 64*1024;
8265
8266 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8267 if (ret) {
8268 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8269 goto fail_locked;
8270 }
8271
8272 ret = i915_gem_object_put_fence(obj);
8273 if (ret) {
8274 DRM_DEBUG_KMS("failed to release fence for cursor");
8275 goto fail_unpin;
8276 }
8277
8278 addr = i915_gem_obj_ggtt_offset(obj);
8279 } else {
8280 int align = IS_I830(dev) ? 16 * 1024 : 256;
8281 ret = i915_gem_object_attach_phys(obj, align);
8282 if (ret) {
8283 DRM_DEBUG_KMS("failed to attach phys object\n");
8284 goto fail_locked;
8285 }
8286 addr = obj->phys_handle->busaddr;
8287 }
8288
8289 if (IS_GEN2(dev))
8290 I915_WRITE(CURSIZE, (height << 12) | width);
8291
8292 finish:
8293 if (intel_crtc->cursor_bo) {
8294 if (!INTEL_INFO(dev)->cursor_needs_physical)
8295 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8296 }
8297
8298 i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8299 INTEL_FRONTBUFFER_CURSOR(pipe));
8300 mutex_unlock(&dev->struct_mutex);
8301
8302 old_width = intel_crtc->cursor_width;
8303
8304 intel_crtc->cursor_addr = addr;
8305 intel_crtc->cursor_bo = obj;
8306 intel_crtc->cursor_width = width;
8307 intel_crtc->cursor_height = height;
8308
8309 if (intel_crtc->active) {
8310 if (old_width != width)
8311 intel_update_watermarks(crtc);
8312 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8313 }
8314
8315 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8316
8317 return 0;
8318 fail_unpin:
8319 i915_gem_object_unpin_from_display_plane(obj);
8320 fail_locked:
8321 mutex_unlock(&dev->struct_mutex);
8322 fail:
8323 drm_gem_object_unreference_unlocked(&obj->base);
8324 return ret;
8325 }
8326
8327 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8328 u16 *blue, uint32_t start, uint32_t size)
8329 {
8330 int end = (start + size > 256) ? 256 : start + size, i;
8331 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8332
8333 for (i = start; i < end; i++) {
8334 intel_crtc->lut_r[i] = red[i] >> 8;
8335 intel_crtc->lut_g[i] = green[i] >> 8;
8336 intel_crtc->lut_b[i] = blue[i] >> 8;
8337 }
8338
8339 intel_crtc_load_lut(crtc);
8340 }
8341
8342 /* VESA 640x480x72Hz mode to set on the pipe */
8343 static struct drm_display_mode load_detect_mode = {
8344 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8345 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8346 };
8347
8348 struct drm_framebuffer *
8349 __intel_framebuffer_create(struct drm_device *dev,
8350 struct drm_mode_fb_cmd2 *mode_cmd,
8351 struct drm_i915_gem_object *obj)
8352 {
8353 struct intel_framebuffer *intel_fb;
8354 int ret;
8355
8356 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8357 if (!intel_fb) {
8358 drm_gem_object_unreference_unlocked(&obj->base);
8359 return ERR_PTR(-ENOMEM);
8360 }
8361
8362 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8363 if (ret)
8364 goto err;
8365
8366 return &intel_fb->base;
8367 err:
8368 drm_gem_object_unreference_unlocked(&obj->base);
8369 kfree(intel_fb);
8370
8371 return ERR_PTR(ret);
8372 }
8373
8374 static struct drm_framebuffer *
8375 intel_framebuffer_create(struct drm_device *dev,
8376 struct drm_mode_fb_cmd2 *mode_cmd,
8377 struct drm_i915_gem_object *obj)
8378 {
8379 struct drm_framebuffer *fb;
8380 int ret;
8381
8382 ret = i915_mutex_lock_interruptible(dev);
8383 if (ret)
8384 return ERR_PTR(ret);
8385 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8386 mutex_unlock(&dev->struct_mutex);
8387
8388 return fb;
8389 }
8390
8391 static u32
8392 intel_framebuffer_pitch_for_width(int width, int bpp)
8393 {
8394 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8395 return ALIGN(pitch, 64);
8396 }
8397
8398 static u32
8399 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8400 {
8401 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8402 return PAGE_ALIGN(pitch * mode->vdisplay);
8403 }
8404
8405 static struct drm_framebuffer *
8406 intel_framebuffer_create_for_mode(struct drm_device *dev,
8407 struct drm_display_mode *mode,
8408 int depth, int bpp)
8409 {
8410 struct drm_i915_gem_object *obj;
8411 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8412
8413 obj = i915_gem_alloc_object(dev,
8414 intel_framebuffer_size_for_mode(mode, bpp));
8415 if (obj == NULL)
8416 return ERR_PTR(-ENOMEM);
8417
8418 mode_cmd.width = mode->hdisplay;
8419 mode_cmd.height = mode->vdisplay;
8420 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8421 bpp);
8422 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8423
8424 return intel_framebuffer_create(dev, &mode_cmd, obj);
8425 }
8426
8427 static struct drm_framebuffer *
8428 mode_fits_in_fbdev(struct drm_device *dev,
8429 struct drm_display_mode *mode)
8430 {
8431 #ifdef CONFIG_DRM_I915_FBDEV
8432 struct drm_i915_private *dev_priv = dev->dev_private;
8433 struct drm_i915_gem_object *obj;
8434 struct drm_framebuffer *fb;
8435
8436 if (!dev_priv->fbdev)
8437 return NULL;
8438
8439 if (!dev_priv->fbdev->fb)
8440 return NULL;
8441
8442 obj = dev_priv->fbdev->fb->obj;
8443 BUG_ON(!obj);
8444
8445 fb = &dev_priv->fbdev->fb->base;
8446 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8447 fb->bits_per_pixel))
8448 return NULL;
8449
8450 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8451 return NULL;
8452
8453 return fb;
8454 #else
8455 return NULL;
8456 #endif
8457 }
8458
8459 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8460 struct drm_display_mode *mode,
8461 struct intel_load_detect_pipe *old,
8462 struct drm_modeset_acquire_ctx *ctx)
8463 {
8464 struct intel_crtc *intel_crtc;
8465 struct intel_encoder *intel_encoder =
8466 intel_attached_encoder(connector);
8467 struct drm_crtc *possible_crtc;
8468 struct drm_encoder *encoder = &intel_encoder->base;
8469 struct drm_crtc *crtc = NULL;
8470 struct drm_device *dev = encoder->dev;
8471 struct drm_framebuffer *fb;
8472 struct drm_mode_config *config = &dev->mode_config;
8473 int ret, i = -1;
8474
8475 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8476 connector->base.id, connector->name,
8477 encoder->base.id, encoder->name);
8478
8479 drm_modeset_acquire_init(ctx, 0);
8480
8481 retry:
8482 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8483 if (ret)
8484 goto fail_unlock;
8485
8486 /*
8487 * Algorithm gets a little messy:
8488 *
8489 * - if the connector already has an assigned crtc, use it (but make
8490 * sure it's on first)
8491 *
8492 * - try to find the first unused crtc that can drive this connector,
8493 * and use that if we find one
8494 */
8495
8496 /* See if we already have a CRTC for this connector */
8497 if (encoder->crtc) {
8498 crtc = encoder->crtc;
8499
8500 ret = drm_modeset_lock(&crtc->mutex, ctx);
8501 if (ret)
8502 goto fail_unlock;
8503
8504 old->dpms_mode = connector->dpms;
8505 old->load_detect_temp = false;
8506
8507 /* Make sure the crtc and connector are running */
8508 if (connector->dpms != DRM_MODE_DPMS_ON)
8509 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8510
8511 return true;
8512 }
8513
8514 /* Find an unused one (if possible) */
8515 for_each_crtc(dev, possible_crtc) {
8516 i++;
8517 if (!(encoder->possible_crtcs & (1 << i)))
8518 continue;
8519 if (!possible_crtc->enabled) {
8520 crtc = possible_crtc;
8521 break;
8522 }
8523 }
8524
8525 /*
8526 * If we didn't find an unused CRTC, don't use any.
8527 */
8528 if (!crtc) {
8529 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8530 goto fail_unlock;
8531 }
8532
8533 ret = drm_modeset_lock(&crtc->mutex, ctx);
8534 if (ret)
8535 goto fail_unlock;
8536 intel_encoder->new_crtc = to_intel_crtc(crtc);
8537 to_intel_connector(connector)->new_encoder = intel_encoder;
8538
8539 intel_crtc = to_intel_crtc(crtc);
8540 intel_crtc->new_enabled = true;
8541 intel_crtc->new_config = &intel_crtc->config;
8542 old->dpms_mode = connector->dpms;
8543 old->load_detect_temp = true;
8544 old->release_fb = NULL;
8545
8546 if (!mode)
8547 mode = &load_detect_mode;
8548
8549 /* We need a framebuffer large enough to accommodate all accesses
8550 * that the plane may generate whilst we perform load detection.
8551 * We can not rely on the fbcon either being present (we get called
8552 * during its initialisation to detect all boot displays, or it may
8553 * not even exist) or that it is large enough to satisfy the
8554 * requested mode.
8555 */
8556 fb = mode_fits_in_fbdev(dev, mode);
8557 if (fb == NULL) {
8558 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8559 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8560 old->release_fb = fb;
8561 } else
8562 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8563 if (IS_ERR(fb)) {
8564 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8565 goto fail;
8566 }
8567
8568 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8569 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8570 if (old->release_fb)
8571 old->release_fb->funcs->destroy(old->release_fb);
8572 goto fail;
8573 }
8574
8575 /* let the connector get through one full cycle before testing */
8576 intel_wait_for_vblank(dev, intel_crtc->pipe);
8577 return true;
8578
8579 fail:
8580 intel_crtc->new_enabled = crtc->enabled;
8581 if (intel_crtc->new_enabled)
8582 intel_crtc->new_config = &intel_crtc->config;
8583 else
8584 intel_crtc->new_config = NULL;
8585 fail_unlock:
8586 if (ret == -EDEADLK) {
8587 drm_modeset_backoff(ctx);
8588 goto retry;
8589 }
8590
8591 drm_modeset_drop_locks(ctx);
8592 drm_modeset_acquire_fini(ctx);
8593
8594 return false;
8595 }
8596
8597 void intel_release_load_detect_pipe(struct drm_connector *connector,
8598 struct intel_load_detect_pipe *old,
8599 struct drm_modeset_acquire_ctx *ctx)
8600 {
8601 struct intel_encoder *intel_encoder =
8602 intel_attached_encoder(connector);
8603 struct drm_encoder *encoder = &intel_encoder->base;
8604 struct drm_crtc *crtc = encoder->crtc;
8605 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8606
8607 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8608 connector->base.id, connector->name,
8609 encoder->base.id, encoder->name);
8610
8611 if (old->load_detect_temp) {
8612 to_intel_connector(connector)->new_encoder = NULL;
8613 intel_encoder->new_crtc = NULL;
8614 intel_crtc->new_enabled = false;
8615 intel_crtc->new_config = NULL;
8616 intel_set_mode(crtc, NULL, 0, 0, NULL);
8617
8618 if (old->release_fb) {
8619 drm_framebuffer_unregister_private(old->release_fb);
8620 drm_framebuffer_unreference(old->release_fb);
8621 }
8622
8623 goto unlock;
8624 return;
8625 }
8626
8627 /* Switch crtc and encoder back off if necessary */
8628 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8629 connector->funcs->dpms(connector, old->dpms_mode);
8630
8631 unlock:
8632 drm_modeset_drop_locks(ctx);
8633 drm_modeset_acquire_fini(ctx);
8634 }
8635
8636 static int i9xx_pll_refclk(struct drm_device *dev,
8637 const struct intel_crtc_config *pipe_config)
8638 {
8639 struct drm_i915_private *dev_priv = dev->dev_private;
8640 u32 dpll = pipe_config->dpll_hw_state.dpll;
8641
8642 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8643 return dev_priv->vbt.lvds_ssc_freq;
8644 else if (HAS_PCH_SPLIT(dev))
8645 return 120000;
8646 else if (!IS_GEN2(dev))
8647 return 96000;
8648 else
8649 return 48000;
8650 }
8651
8652 /* Returns the clock of the currently programmed mode of the given pipe. */
8653 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8654 struct intel_crtc_config *pipe_config)
8655 {
8656 struct drm_device *dev = crtc->base.dev;
8657 struct drm_i915_private *dev_priv = dev->dev_private;
8658 int pipe = pipe_config->cpu_transcoder;
8659 u32 dpll = pipe_config->dpll_hw_state.dpll;
8660 u32 fp;
8661 intel_clock_t clock;
8662 int refclk = i9xx_pll_refclk(dev, pipe_config);
8663
8664 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8665 fp = pipe_config->dpll_hw_state.fp0;
8666 else
8667 fp = pipe_config->dpll_hw_state.fp1;
8668
8669 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8670 if (IS_PINEVIEW(dev)) {
8671 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8672 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8673 } else {
8674 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8675 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8676 }
8677
8678 if (!IS_GEN2(dev)) {
8679 if (IS_PINEVIEW(dev))
8680 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8681 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8682 else
8683 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8684 DPLL_FPA01_P1_POST_DIV_SHIFT);
8685
8686 switch (dpll & DPLL_MODE_MASK) {
8687 case DPLLB_MODE_DAC_SERIAL:
8688 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8689 5 : 10;
8690 break;
8691 case DPLLB_MODE_LVDS:
8692 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8693 7 : 14;
8694 break;
8695 default:
8696 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8697 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8698 return;
8699 }
8700
8701 if (IS_PINEVIEW(dev))
8702 pineview_clock(refclk, &clock);
8703 else
8704 i9xx_clock(refclk, &clock);
8705 } else {
8706 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8707 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8708
8709 if (is_lvds) {
8710 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8711 DPLL_FPA01_P1_POST_DIV_SHIFT);
8712
8713 if (lvds & LVDS_CLKB_POWER_UP)
8714 clock.p2 = 7;
8715 else
8716 clock.p2 = 14;
8717 } else {
8718 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8719 clock.p1 = 2;
8720 else {
8721 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8722 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8723 }
8724 if (dpll & PLL_P2_DIVIDE_BY_4)
8725 clock.p2 = 4;
8726 else
8727 clock.p2 = 2;
8728 }
8729
8730 i9xx_clock(refclk, &clock);
8731 }
8732
8733 /*
8734 * This value includes pixel_multiplier. We will use
8735 * port_clock to compute adjusted_mode.crtc_clock in the
8736 * encoder's get_config() function.
8737 */
8738 pipe_config->port_clock = clock.dot;
8739 }
8740
8741 int intel_dotclock_calculate(int link_freq,
8742 const struct intel_link_m_n *m_n)
8743 {
8744 /*
8745 * The calculation for the data clock is:
8746 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8747 * But we want to avoid losing precison if possible, so:
8748 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8749 *
8750 * and the link clock is simpler:
8751 * link_clock = (m * link_clock) / n
8752 */
8753
8754 if (!m_n->link_n)
8755 return 0;
8756
8757 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8758 }
8759
8760 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8761 struct intel_crtc_config *pipe_config)
8762 {
8763 struct drm_device *dev = crtc->base.dev;
8764
8765 /* read out port_clock from the DPLL */
8766 i9xx_crtc_clock_get(crtc, pipe_config);
8767
8768 /*
8769 * This value does not include pixel_multiplier.
8770 * We will check that port_clock and adjusted_mode.crtc_clock
8771 * agree once we know their relationship in the encoder's
8772 * get_config() function.
8773 */
8774 pipe_config->adjusted_mode.crtc_clock =
8775 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8776 &pipe_config->fdi_m_n);
8777 }
8778
8779 /** Returns the currently programmed mode of the given pipe. */
8780 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8781 struct drm_crtc *crtc)
8782 {
8783 struct drm_i915_private *dev_priv = dev->dev_private;
8784 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8785 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8786 struct drm_display_mode *mode;
8787 struct intel_crtc_config pipe_config;
8788 int htot = I915_READ(HTOTAL(cpu_transcoder));
8789 int hsync = I915_READ(HSYNC(cpu_transcoder));
8790 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8791 int vsync = I915_READ(VSYNC(cpu_transcoder));
8792 enum pipe pipe = intel_crtc->pipe;
8793
8794 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8795 if (!mode)
8796 return NULL;
8797
8798 /*
8799 * Construct a pipe_config sufficient for getting the clock info
8800 * back out of crtc_clock_get.
8801 *
8802 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8803 * to use a real value here instead.
8804 */
8805 pipe_config.cpu_transcoder = (enum transcoder) pipe;
8806 pipe_config.pixel_multiplier = 1;
8807 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8808 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8809 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8810 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8811
8812 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8813 mode->hdisplay = (htot & 0xffff) + 1;
8814 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8815 mode->hsync_start = (hsync & 0xffff) + 1;
8816 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8817 mode->vdisplay = (vtot & 0xffff) + 1;
8818 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8819 mode->vsync_start = (vsync & 0xffff) + 1;
8820 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8821
8822 drm_mode_set_name(mode);
8823
8824 return mode;
8825 }
8826
8827 static void intel_increase_pllclock(struct drm_device *dev,
8828 enum pipe pipe)
8829 {
8830 struct drm_i915_private *dev_priv = dev->dev_private;
8831 int dpll_reg = DPLL(pipe);
8832 int dpll;
8833
8834 if (!HAS_GMCH_DISPLAY(dev))
8835 return;
8836
8837 if (!dev_priv->lvds_downclock_avail)
8838 return;
8839
8840 dpll = I915_READ(dpll_reg);
8841 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8842 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8843
8844 assert_panel_unlocked(dev_priv, pipe);
8845
8846 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8847 I915_WRITE(dpll_reg, dpll);
8848 intel_wait_for_vblank(dev, pipe);
8849
8850 dpll = I915_READ(dpll_reg);
8851 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8852 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8853 }
8854 }
8855
8856 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8857 {
8858 struct drm_device *dev = crtc->dev;
8859 struct drm_i915_private *dev_priv = dev->dev_private;
8860 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8861
8862 if (!HAS_GMCH_DISPLAY(dev))
8863 return;
8864
8865 if (!dev_priv->lvds_downclock_avail)
8866 return;
8867
8868 /*
8869 * Since this is called by a timer, we should never get here in
8870 * the manual case.
8871 */
8872 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8873 int pipe = intel_crtc->pipe;
8874 int dpll_reg = DPLL(pipe);
8875 int dpll;
8876
8877 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8878
8879 assert_panel_unlocked(dev_priv, pipe);
8880
8881 dpll = I915_READ(dpll_reg);
8882 dpll |= DISPLAY_RATE_SELECT_FPA1;
8883 I915_WRITE(dpll_reg, dpll);
8884 intel_wait_for_vblank(dev, pipe);
8885 dpll = I915_READ(dpll_reg);
8886 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8887 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8888 }
8889
8890 }
8891
8892 void intel_mark_busy(struct drm_device *dev)
8893 {
8894 struct drm_i915_private *dev_priv = dev->dev_private;
8895
8896 if (dev_priv->mm.busy)
8897 return;
8898
8899 intel_runtime_pm_get(dev_priv);
8900 i915_update_gfx_val(dev_priv);
8901 dev_priv->mm.busy = true;
8902 }
8903
8904 void intel_mark_idle(struct drm_device *dev)
8905 {
8906 struct drm_i915_private *dev_priv = dev->dev_private;
8907 struct drm_crtc *crtc;
8908
8909 if (!dev_priv->mm.busy)
8910 return;
8911
8912 dev_priv->mm.busy = false;
8913
8914 if (!i915.powersave)
8915 goto out;
8916
8917 for_each_crtc(dev, crtc) {
8918 if (!crtc->primary->fb)
8919 continue;
8920
8921 intel_decrease_pllclock(crtc);
8922 }
8923
8924 if (INTEL_INFO(dev)->gen >= 6)
8925 gen6_rps_idle(dev->dev_private);
8926
8927 out:
8928 intel_runtime_pm_put(dev_priv);
8929 }
8930
8931
8932 /**
8933 * intel_mark_fb_busy - mark given planes as busy
8934 * @dev: DRM device
8935 * @frontbuffer_bits: bits for the affected planes
8936 * @ring: optional ring for asynchronous commands
8937 *
8938 * This function gets called every time the screen contents change. It can be
8939 * used to keep e.g. the update rate at the nominal refresh rate with DRRS.
8940 */
8941 static void intel_mark_fb_busy(struct drm_device *dev,
8942 unsigned frontbuffer_bits,
8943 struct intel_engine_cs *ring)
8944 {
8945 enum pipe pipe;
8946
8947 if (!i915.powersave)
8948 return;
8949
8950 for_each_pipe(pipe) {
8951 if (!(frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe)))
8952 continue;
8953
8954 intel_increase_pllclock(dev, pipe);
8955 if (ring && intel_fbc_enabled(dev))
8956 ring->fbc_dirty = true;
8957 }
8958 }
8959
8960 /**
8961 * intel_fb_obj_invalidate - invalidate frontbuffer object
8962 * @obj: GEM object to invalidate
8963 * @ring: set for asynchronous rendering
8964 *
8965 * This function gets called every time rendering on the given object starts and
8966 * frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must
8967 * be invalidated. If @ring is non-NULL any subsequent invalidation will be delayed
8968 * until the rendering completes or a flip on this frontbuffer plane is
8969 * scheduled.
8970 */
8971 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
8972 struct intel_engine_cs *ring)
8973 {
8974 struct drm_device *dev = obj->base.dev;
8975 struct drm_i915_private *dev_priv = dev->dev_private;
8976
8977 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
8978
8979 if (!obj->frontbuffer_bits)
8980 return;
8981
8982 if (ring) {
8983 mutex_lock(&dev_priv->fb_tracking.lock);
8984 dev_priv->fb_tracking.busy_bits
8985 |= obj->frontbuffer_bits;
8986 dev_priv->fb_tracking.flip_bits
8987 &= ~obj->frontbuffer_bits;
8988 mutex_unlock(&dev_priv->fb_tracking.lock);
8989 }
8990
8991 intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring);
8992
8993 intel_edp_psr_invalidate(dev, obj->frontbuffer_bits);
8994 }
8995
8996 /**
8997 * intel_frontbuffer_flush - flush frontbuffer
8998 * @dev: DRM device
8999 * @frontbuffer_bits: frontbuffer plane tracking bits
9000 *
9001 * This function gets called every time rendering on the given planes has
9002 * completed and frontbuffer caching can be started again. Flushes will get
9003 * delayed if they're blocked by some oustanding asynchronous rendering.
9004 *
9005 * Can be called without any locks held.
9006 */
9007 void intel_frontbuffer_flush(struct drm_device *dev,
9008 unsigned frontbuffer_bits)
9009 {
9010 struct drm_i915_private *dev_priv = dev->dev_private;
9011
9012 /* Delay flushing when rings are still busy.*/
9013 mutex_lock(&dev_priv->fb_tracking.lock);
9014 frontbuffer_bits &= ~dev_priv->fb_tracking.busy_bits;
9015 mutex_unlock(&dev_priv->fb_tracking.lock);
9016
9017 intel_mark_fb_busy(dev, frontbuffer_bits, NULL);
9018
9019 intel_edp_psr_flush(dev, frontbuffer_bits);
9020 }
9021
9022 /**
9023 * intel_fb_obj_flush - flush frontbuffer object
9024 * @obj: GEM object to flush
9025 * @retire: set when retiring asynchronous rendering
9026 *
9027 * This function gets called every time rendering on the given object has
9028 * completed and frontbuffer caching can be started again. If @retire is true
9029 * then any delayed flushes will be unblocked.
9030 */
9031 void intel_fb_obj_flush(struct drm_i915_gem_object *obj,
9032 bool retire)
9033 {
9034 struct drm_device *dev = obj->base.dev;
9035 struct drm_i915_private *dev_priv = dev->dev_private;
9036 unsigned frontbuffer_bits;
9037
9038 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
9039
9040 if (!obj->frontbuffer_bits)
9041 return;
9042
9043 frontbuffer_bits = obj->frontbuffer_bits;
9044
9045 if (retire) {
9046 mutex_lock(&dev_priv->fb_tracking.lock);
9047 /* Filter out new bits since rendering started. */
9048 frontbuffer_bits &= dev_priv->fb_tracking.busy_bits;
9049
9050 dev_priv->fb_tracking.busy_bits &= ~frontbuffer_bits;
9051 mutex_unlock(&dev_priv->fb_tracking.lock);
9052 }
9053
9054 intel_frontbuffer_flush(dev, frontbuffer_bits);
9055 }
9056
9057 /**
9058 * intel_frontbuffer_flip_prepare - prepare asnychronous frontbuffer flip
9059 * @dev: DRM device
9060 * @frontbuffer_bits: frontbuffer plane tracking bits
9061 *
9062 * This function gets called after scheduling a flip on @obj. The actual
9063 * frontbuffer flushing will be delayed until completion is signalled with
9064 * intel_frontbuffer_flip_complete. If an invalidate happens in between this
9065 * flush will be cancelled.
9066 *
9067 * Can be called without any locks held.
9068 */
9069 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
9070 unsigned frontbuffer_bits)
9071 {
9072 struct drm_i915_private *dev_priv = dev->dev_private;
9073
9074 mutex_lock(&dev_priv->fb_tracking.lock);
9075 dev_priv->fb_tracking.flip_bits
9076 |= frontbuffer_bits;
9077 mutex_unlock(&dev_priv->fb_tracking.lock);
9078 }
9079
9080 /**
9081 * intel_frontbuffer_flip_complete - complete asynchronous frontbuffer flush
9082 * @dev: DRM device
9083 * @frontbuffer_bits: frontbuffer plane tracking bits
9084 *
9085 * This function gets called after the flip has been latched and will complete
9086 * on the next vblank. It will execute the fush if it hasn't been cancalled yet.
9087 *
9088 * Can be called without any locks held.
9089 */
9090 void intel_frontbuffer_flip_complete(struct drm_device *dev,
9091 unsigned frontbuffer_bits)
9092 {
9093 struct drm_i915_private *dev_priv = dev->dev_private;
9094
9095 mutex_lock(&dev_priv->fb_tracking.lock);
9096 /* Mask any cancelled flips. */
9097 frontbuffer_bits &= dev_priv->fb_tracking.flip_bits;
9098 dev_priv->fb_tracking.flip_bits &= ~frontbuffer_bits;
9099 mutex_unlock(&dev_priv->fb_tracking.lock);
9100
9101 intel_frontbuffer_flush(dev, frontbuffer_bits);
9102 }
9103
9104 static void intel_crtc_destroy(struct drm_crtc *crtc)
9105 {
9106 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9107 struct drm_device *dev = crtc->dev;
9108 struct intel_unpin_work *work;
9109 unsigned long flags;
9110
9111 spin_lock_irqsave(&dev->event_lock, flags);
9112 work = intel_crtc->unpin_work;
9113 intel_crtc->unpin_work = NULL;
9114 spin_unlock_irqrestore(&dev->event_lock, flags);
9115
9116 if (work) {
9117 cancel_work_sync(&work->work);
9118 kfree(work);
9119 }
9120
9121 drm_crtc_cleanup(crtc);
9122
9123 kfree(intel_crtc);
9124 }
9125
9126 static void intel_unpin_work_fn(struct work_struct *__work)
9127 {
9128 struct intel_unpin_work *work =
9129 container_of(__work, struct intel_unpin_work, work);
9130 struct drm_device *dev = work->crtc->dev;
9131 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9132
9133 mutex_lock(&dev->struct_mutex);
9134 intel_unpin_fb_obj(work->old_fb_obj);
9135 drm_gem_object_unreference(&work->pending_flip_obj->base);
9136 drm_gem_object_unreference(&work->old_fb_obj->base);
9137
9138 intel_update_fbc(dev);
9139 mutex_unlock(&dev->struct_mutex);
9140
9141 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9142
9143 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9144 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9145
9146 kfree(work);
9147 }
9148
9149 static void do_intel_finish_page_flip(struct drm_device *dev,
9150 struct drm_crtc *crtc)
9151 {
9152 struct drm_i915_private *dev_priv = dev->dev_private;
9153 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9154 struct intel_unpin_work *work;
9155 unsigned long flags;
9156
9157 /* Ignore early vblank irqs */
9158 if (intel_crtc == NULL)
9159 return;
9160
9161 spin_lock_irqsave(&dev->event_lock, flags);
9162 work = intel_crtc->unpin_work;
9163
9164 /* Ensure we don't miss a work->pending update ... */
9165 smp_rmb();
9166
9167 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9168 spin_unlock_irqrestore(&dev->event_lock, flags);
9169 return;
9170 }
9171
9172 /* and that the unpin work is consistent wrt ->pending. */
9173 smp_rmb();
9174
9175 intel_crtc->unpin_work = NULL;
9176
9177 if (work->event)
9178 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
9179
9180 drm_crtc_vblank_put(crtc);
9181
9182 spin_unlock_irqrestore(&dev->event_lock, flags);
9183
9184 wake_up_all(&dev_priv->pending_flip_queue);
9185
9186 queue_work(dev_priv->wq, &work->work);
9187
9188 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
9189 }
9190
9191 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9192 {
9193 struct drm_i915_private *dev_priv = dev->dev_private;
9194 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9195
9196 do_intel_finish_page_flip(dev, crtc);
9197 }
9198
9199 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9200 {
9201 struct drm_i915_private *dev_priv = dev->dev_private;
9202 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9203
9204 do_intel_finish_page_flip(dev, crtc);
9205 }
9206
9207 /* Is 'a' after or equal to 'b'? */
9208 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9209 {
9210 return !((a - b) & 0x80000000);
9211 }
9212
9213 static bool page_flip_finished(struct intel_crtc *crtc)
9214 {
9215 struct drm_device *dev = crtc->base.dev;
9216 struct drm_i915_private *dev_priv = dev->dev_private;
9217
9218 /*
9219 * The relevant registers doen't exist on pre-ctg.
9220 * As the flip done interrupt doesn't trigger for mmio
9221 * flips on gmch platforms, a flip count check isn't
9222 * really needed there. But since ctg has the registers,
9223 * include it in the check anyway.
9224 */
9225 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9226 return true;
9227
9228 /*
9229 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9230 * used the same base address. In that case the mmio flip might
9231 * have completed, but the CS hasn't even executed the flip yet.
9232 *
9233 * A flip count check isn't enough as the CS might have updated
9234 * the base address just after start of vblank, but before we
9235 * managed to process the interrupt. This means we'd complete the
9236 * CS flip too soon.
9237 *
9238 * Combining both checks should get us a good enough result. It may
9239 * still happen that the CS flip has been executed, but has not
9240 * yet actually completed. But in case the base address is the same
9241 * anyway, we don't really care.
9242 */
9243 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9244 crtc->unpin_work->gtt_offset &&
9245 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9246 crtc->unpin_work->flip_count);
9247 }
9248
9249 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9250 {
9251 struct drm_i915_private *dev_priv = dev->dev_private;
9252 struct intel_crtc *intel_crtc =
9253 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9254 unsigned long flags;
9255
9256 /* NB: An MMIO update of the plane base pointer will also
9257 * generate a page-flip completion irq, i.e. every modeset
9258 * is also accompanied by a spurious intel_prepare_page_flip().
9259 */
9260 spin_lock_irqsave(&dev->event_lock, flags);
9261 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9262 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9263 spin_unlock_irqrestore(&dev->event_lock, flags);
9264 }
9265
9266 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9267 {
9268 /* Ensure that the work item is consistent when activating it ... */
9269 smp_wmb();
9270 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9271 /* and that it is marked active as soon as the irq could fire. */
9272 smp_wmb();
9273 }
9274
9275 static int intel_gen2_queue_flip(struct drm_device *dev,
9276 struct drm_crtc *crtc,
9277 struct drm_framebuffer *fb,
9278 struct drm_i915_gem_object *obj,
9279 struct intel_engine_cs *ring,
9280 uint32_t flags)
9281 {
9282 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9283 u32 flip_mask;
9284 int ret;
9285
9286 ret = intel_ring_begin(ring, 6);
9287 if (ret)
9288 return ret;
9289
9290 /* Can't queue multiple flips, so wait for the previous
9291 * one to finish before executing the next.
9292 */
9293 if (intel_crtc->plane)
9294 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9295 else
9296 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9297 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9298 intel_ring_emit(ring, MI_NOOP);
9299 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9300 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9301 intel_ring_emit(ring, fb->pitches[0]);
9302 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9303 intel_ring_emit(ring, 0); /* aux display base address, unused */
9304
9305 intel_mark_page_flip_active(intel_crtc);
9306 __intel_ring_advance(ring);
9307 return 0;
9308 }
9309
9310 static int intel_gen3_queue_flip(struct drm_device *dev,
9311 struct drm_crtc *crtc,
9312 struct drm_framebuffer *fb,
9313 struct drm_i915_gem_object *obj,
9314 struct intel_engine_cs *ring,
9315 uint32_t flags)
9316 {
9317 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9318 u32 flip_mask;
9319 int ret;
9320
9321 ret = intel_ring_begin(ring, 6);
9322 if (ret)
9323 return ret;
9324
9325 if (intel_crtc->plane)
9326 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9327 else
9328 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9329 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9330 intel_ring_emit(ring, MI_NOOP);
9331 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9332 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9333 intel_ring_emit(ring, fb->pitches[0]);
9334 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9335 intel_ring_emit(ring, MI_NOOP);
9336
9337 intel_mark_page_flip_active(intel_crtc);
9338 __intel_ring_advance(ring);
9339 return 0;
9340 }
9341
9342 static int intel_gen4_queue_flip(struct drm_device *dev,
9343 struct drm_crtc *crtc,
9344 struct drm_framebuffer *fb,
9345 struct drm_i915_gem_object *obj,
9346 struct intel_engine_cs *ring,
9347 uint32_t flags)
9348 {
9349 struct drm_i915_private *dev_priv = dev->dev_private;
9350 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9351 uint32_t pf, pipesrc;
9352 int ret;
9353
9354 ret = intel_ring_begin(ring, 4);
9355 if (ret)
9356 return ret;
9357
9358 /* i965+ uses the linear or tiled offsets from the
9359 * Display Registers (which do not change across a page-flip)
9360 * so we need only reprogram the base address.
9361 */
9362 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9363 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9364 intel_ring_emit(ring, fb->pitches[0]);
9365 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9366 obj->tiling_mode);
9367
9368 /* XXX Enabling the panel-fitter across page-flip is so far
9369 * untested on non-native modes, so ignore it for now.
9370 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9371 */
9372 pf = 0;
9373 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9374 intel_ring_emit(ring, pf | pipesrc);
9375
9376 intel_mark_page_flip_active(intel_crtc);
9377 __intel_ring_advance(ring);
9378 return 0;
9379 }
9380
9381 static int intel_gen6_queue_flip(struct drm_device *dev,
9382 struct drm_crtc *crtc,
9383 struct drm_framebuffer *fb,
9384 struct drm_i915_gem_object *obj,
9385 struct intel_engine_cs *ring,
9386 uint32_t flags)
9387 {
9388 struct drm_i915_private *dev_priv = dev->dev_private;
9389 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9390 uint32_t pf, pipesrc;
9391 int ret;
9392
9393 ret = intel_ring_begin(ring, 4);
9394 if (ret)
9395 return ret;
9396
9397 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9398 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9399 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9400 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9401
9402 /* Contrary to the suggestions in the documentation,
9403 * "Enable Panel Fitter" does not seem to be required when page
9404 * flipping with a non-native mode, and worse causes a normal
9405 * modeset to fail.
9406 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9407 */
9408 pf = 0;
9409 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9410 intel_ring_emit(ring, pf | pipesrc);
9411
9412 intel_mark_page_flip_active(intel_crtc);
9413 __intel_ring_advance(ring);
9414 return 0;
9415 }
9416
9417 static int intel_gen7_queue_flip(struct drm_device *dev,
9418 struct drm_crtc *crtc,
9419 struct drm_framebuffer *fb,
9420 struct drm_i915_gem_object *obj,
9421 struct intel_engine_cs *ring,
9422 uint32_t flags)
9423 {
9424 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9425 uint32_t plane_bit = 0;
9426 int len, ret;
9427
9428 switch (intel_crtc->plane) {
9429 case PLANE_A:
9430 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9431 break;
9432 case PLANE_B:
9433 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9434 break;
9435 case PLANE_C:
9436 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9437 break;
9438 default:
9439 WARN_ONCE(1, "unknown plane in flip command\n");
9440 return -ENODEV;
9441 }
9442
9443 len = 4;
9444 if (ring->id == RCS) {
9445 len += 6;
9446 /*
9447 * On Gen 8, SRM is now taking an extra dword to accommodate
9448 * 48bits addresses, and we need a NOOP for the batch size to
9449 * stay even.
9450 */
9451 if (IS_GEN8(dev))
9452 len += 2;
9453 }
9454
9455 /*
9456 * BSpec MI_DISPLAY_FLIP for IVB:
9457 * "The full packet must be contained within the same cache line."
9458 *
9459 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9460 * cacheline, if we ever start emitting more commands before
9461 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9462 * then do the cacheline alignment, and finally emit the
9463 * MI_DISPLAY_FLIP.
9464 */
9465 ret = intel_ring_cacheline_align(ring);
9466 if (ret)
9467 return ret;
9468
9469 ret = intel_ring_begin(ring, len);
9470 if (ret)
9471 return ret;
9472
9473 /* Unmask the flip-done completion message. Note that the bspec says that
9474 * we should do this for both the BCS and RCS, and that we must not unmask
9475 * more than one flip event at any time (or ensure that one flip message
9476 * can be sent by waiting for flip-done prior to queueing new flips).
9477 * Experimentation says that BCS works despite DERRMR masking all
9478 * flip-done completion events and that unmasking all planes at once
9479 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9480 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9481 */
9482 if (ring->id == RCS) {
9483 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9484 intel_ring_emit(ring, DERRMR);
9485 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9486 DERRMR_PIPEB_PRI_FLIP_DONE |
9487 DERRMR_PIPEC_PRI_FLIP_DONE));
9488 if (IS_GEN8(dev))
9489 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9490 MI_SRM_LRM_GLOBAL_GTT);
9491 else
9492 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9493 MI_SRM_LRM_GLOBAL_GTT);
9494 intel_ring_emit(ring, DERRMR);
9495 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9496 if (IS_GEN8(dev)) {
9497 intel_ring_emit(ring, 0);
9498 intel_ring_emit(ring, MI_NOOP);
9499 }
9500 }
9501
9502 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9503 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9504 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9505 intel_ring_emit(ring, (MI_NOOP));
9506
9507 intel_mark_page_flip_active(intel_crtc);
9508 __intel_ring_advance(ring);
9509 return 0;
9510 }
9511
9512 static bool use_mmio_flip(struct intel_engine_cs *ring,
9513 struct drm_i915_gem_object *obj)
9514 {
9515 /*
9516 * This is not being used for older platforms, because
9517 * non-availability of flip done interrupt forces us to use
9518 * CS flips. Older platforms derive flip done using some clever
9519 * tricks involving the flip_pending status bits and vblank irqs.
9520 * So using MMIO flips there would disrupt this mechanism.
9521 */
9522
9523 if (ring == NULL)
9524 return true;
9525
9526 if (INTEL_INFO(ring->dev)->gen < 5)
9527 return false;
9528
9529 if (i915.use_mmio_flip < 0)
9530 return false;
9531 else if (i915.use_mmio_flip > 0)
9532 return true;
9533 else
9534 return ring != obj->ring;
9535 }
9536
9537 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9538 {
9539 struct drm_device *dev = intel_crtc->base.dev;
9540 struct drm_i915_private *dev_priv = dev->dev_private;
9541 struct intel_framebuffer *intel_fb =
9542 to_intel_framebuffer(intel_crtc->base.primary->fb);
9543 struct drm_i915_gem_object *obj = intel_fb->obj;
9544 u32 dspcntr;
9545 u32 reg;
9546
9547 intel_mark_page_flip_active(intel_crtc);
9548
9549 reg = DSPCNTR(intel_crtc->plane);
9550 dspcntr = I915_READ(reg);
9551
9552 if (INTEL_INFO(dev)->gen >= 4) {
9553 if (obj->tiling_mode != I915_TILING_NONE)
9554 dspcntr |= DISPPLANE_TILED;
9555 else
9556 dspcntr &= ~DISPPLANE_TILED;
9557 }
9558 I915_WRITE(reg, dspcntr);
9559
9560 I915_WRITE(DSPSURF(intel_crtc->plane),
9561 intel_crtc->unpin_work->gtt_offset);
9562 POSTING_READ(DSPSURF(intel_crtc->plane));
9563 }
9564
9565 static int intel_postpone_flip(struct drm_i915_gem_object *obj)
9566 {
9567 struct intel_engine_cs *ring;
9568 int ret;
9569
9570 lockdep_assert_held(&obj->base.dev->struct_mutex);
9571
9572 if (!obj->last_write_seqno)
9573 return 0;
9574
9575 ring = obj->ring;
9576
9577 if (i915_seqno_passed(ring->get_seqno(ring, true),
9578 obj->last_write_seqno))
9579 return 0;
9580
9581 ret = i915_gem_check_olr(ring, obj->last_write_seqno);
9582 if (ret)
9583 return ret;
9584
9585 if (WARN_ON(!ring->irq_get(ring)))
9586 return 0;
9587
9588 return 1;
9589 }
9590
9591 void intel_notify_mmio_flip(struct intel_engine_cs *ring)
9592 {
9593 struct drm_i915_private *dev_priv = to_i915(ring->dev);
9594 struct intel_crtc *intel_crtc;
9595 unsigned long irq_flags;
9596 u32 seqno;
9597
9598 seqno = ring->get_seqno(ring, false);
9599
9600 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9601 for_each_intel_crtc(ring->dev, intel_crtc) {
9602 struct intel_mmio_flip *mmio_flip;
9603
9604 mmio_flip = &intel_crtc->mmio_flip;
9605 if (mmio_flip->seqno == 0)
9606 continue;
9607
9608 if (ring->id != mmio_flip->ring_id)
9609 continue;
9610
9611 if (i915_seqno_passed(seqno, mmio_flip->seqno)) {
9612 intel_do_mmio_flip(intel_crtc);
9613 mmio_flip->seqno = 0;
9614 ring->irq_put(ring);
9615 }
9616 }
9617 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9618 }
9619
9620 static int intel_queue_mmio_flip(struct drm_device *dev,
9621 struct drm_crtc *crtc,
9622 struct drm_framebuffer *fb,
9623 struct drm_i915_gem_object *obj,
9624 struct intel_engine_cs *ring,
9625 uint32_t flags)
9626 {
9627 struct drm_i915_private *dev_priv = dev->dev_private;
9628 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9629 unsigned long irq_flags;
9630 int ret;
9631
9632 if (WARN_ON(intel_crtc->mmio_flip.seqno))
9633 return -EBUSY;
9634
9635 ret = intel_postpone_flip(obj);
9636 if (ret < 0)
9637 return ret;
9638 if (ret == 0) {
9639 intel_do_mmio_flip(intel_crtc);
9640 return 0;
9641 }
9642
9643 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9644 intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9645 intel_crtc->mmio_flip.ring_id = obj->ring->id;
9646 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9647
9648 /*
9649 * Double check to catch cases where irq fired before
9650 * mmio flip data was ready
9651 */
9652 intel_notify_mmio_flip(obj->ring);
9653 return 0;
9654 }
9655
9656 static int intel_default_queue_flip(struct drm_device *dev,
9657 struct drm_crtc *crtc,
9658 struct drm_framebuffer *fb,
9659 struct drm_i915_gem_object *obj,
9660 struct intel_engine_cs *ring,
9661 uint32_t flags)
9662 {
9663 return -ENODEV;
9664 }
9665
9666 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9667 struct drm_framebuffer *fb,
9668 struct drm_pending_vblank_event *event,
9669 uint32_t page_flip_flags)
9670 {
9671 struct drm_device *dev = crtc->dev;
9672 struct drm_i915_private *dev_priv = dev->dev_private;
9673 struct drm_framebuffer *old_fb = crtc->primary->fb;
9674 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9675 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9676 enum pipe pipe = intel_crtc->pipe;
9677 struct intel_unpin_work *work;
9678 struct intel_engine_cs *ring;
9679 unsigned long flags;
9680 int ret;
9681
9682 /*
9683 * drm_mode_page_flip_ioctl() should already catch this, but double
9684 * check to be safe. In the future we may enable pageflipping from
9685 * a disabled primary plane.
9686 */
9687 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9688 return -EBUSY;
9689
9690 /* Can't change pixel format via MI display flips. */
9691 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9692 return -EINVAL;
9693
9694 /*
9695 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9696 * Note that pitch changes could also affect these register.
9697 */
9698 if (INTEL_INFO(dev)->gen > 3 &&
9699 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9700 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9701 return -EINVAL;
9702
9703 if (i915_terminally_wedged(&dev_priv->gpu_error))
9704 goto out_hang;
9705
9706 work = kzalloc(sizeof(*work), GFP_KERNEL);
9707 if (work == NULL)
9708 return -ENOMEM;
9709
9710 work->event = event;
9711 work->crtc = crtc;
9712 work->old_fb_obj = intel_fb_obj(old_fb);
9713 INIT_WORK(&work->work, intel_unpin_work_fn);
9714
9715 ret = drm_crtc_vblank_get(crtc);
9716 if (ret)
9717 goto free_work;
9718
9719 /* We borrow the event spin lock for protecting unpin_work */
9720 spin_lock_irqsave(&dev->event_lock, flags);
9721 if (intel_crtc->unpin_work) {
9722 spin_unlock_irqrestore(&dev->event_lock, flags);
9723 kfree(work);
9724 drm_crtc_vblank_put(crtc);
9725
9726 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9727 return -EBUSY;
9728 }
9729 intel_crtc->unpin_work = work;
9730 spin_unlock_irqrestore(&dev->event_lock, flags);
9731
9732 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9733 flush_workqueue(dev_priv->wq);
9734
9735 ret = i915_mutex_lock_interruptible(dev);
9736 if (ret)
9737 goto cleanup;
9738
9739 /* Reference the objects for the scheduled work. */
9740 drm_gem_object_reference(&work->old_fb_obj->base);
9741 drm_gem_object_reference(&obj->base);
9742
9743 crtc->primary->fb = fb;
9744
9745 work->pending_flip_obj = obj;
9746
9747 work->enable_stall_check = true;
9748
9749 atomic_inc(&intel_crtc->unpin_work_count);
9750 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9751
9752 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9753 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9754
9755 if (IS_VALLEYVIEW(dev)) {
9756 ring = &dev_priv->ring[BCS];
9757 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9758 /* vlv: DISPLAY_FLIP fails to change tiling */
9759 ring = NULL;
9760 } else if (IS_IVYBRIDGE(dev)) {
9761 ring = &dev_priv->ring[BCS];
9762 } else if (INTEL_INFO(dev)->gen >= 7) {
9763 ring = obj->ring;
9764 if (ring == NULL || ring->id != RCS)
9765 ring = &dev_priv->ring[BCS];
9766 } else {
9767 ring = &dev_priv->ring[RCS];
9768 }
9769
9770 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9771 if (ret)
9772 goto cleanup_pending;
9773
9774 work->gtt_offset =
9775 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9776
9777 if (use_mmio_flip(ring, obj))
9778 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9779 page_flip_flags);
9780 else
9781 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9782 page_flip_flags);
9783 if (ret)
9784 goto cleanup_unpin;
9785
9786 i915_gem_track_fb(work->old_fb_obj, obj,
9787 INTEL_FRONTBUFFER_PRIMARY(pipe));
9788
9789 intel_disable_fbc(dev);
9790 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9791 mutex_unlock(&dev->struct_mutex);
9792
9793 trace_i915_flip_request(intel_crtc->plane, obj);
9794
9795 return 0;
9796
9797 cleanup_unpin:
9798 intel_unpin_fb_obj(obj);
9799 cleanup_pending:
9800 atomic_dec(&intel_crtc->unpin_work_count);
9801 crtc->primary->fb = old_fb;
9802 drm_gem_object_unreference(&work->old_fb_obj->base);
9803 drm_gem_object_unreference(&obj->base);
9804 mutex_unlock(&dev->struct_mutex);
9805
9806 cleanup:
9807 spin_lock_irqsave(&dev->event_lock, flags);
9808 intel_crtc->unpin_work = NULL;
9809 spin_unlock_irqrestore(&dev->event_lock, flags);
9810
9811 drm_crtc_vblank_put(crtc);
9812 free_work:
9813 kfree(work);
9814
9815 if (ret == -EIO) {
9816 out_hang:
9817 intel_crtc_wait_for_pending_flips(crtc);
9818 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9819 if (ret == 0 && event)
9820 drm_send_vblank_event(dev, pipe, event);
9821 }
9822 return ret;
9823 }
9824
9825 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9826 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9827 .load_lut = intel_crtc_load_lut,
9828 };
9829
9830 /**
9831 * intel_modeset_update_staged_output_state
9832 *
9833 * Updates the staged output configuration state, e.g. after we've read out the
9834 * current hw state.
9835 */
9836 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9837 {
9838 struct intel_crtc *crtc;
9839 struct intel_encoder *encoder;
9840 struct intel_connector *connector;
9841
9842 list_for_each_entry(connector, &dev->mode_config.connector_list,
9843 base.head) {
9844 connector->new_encoder =
9845 to_intel_encoder(connector->base.encoder);
9846 }
9847
9848 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9849 base.head) {
9850 encoder->new_crtc =
9851 to_intel_crtc(encoder->base.crtc);
9852 }
9853
9854 for_each_intel_crtc(dev, crtc) {
9855 crtc->new_enabled = crtc->base.enabled;
9856
9857 if (crtc->new_enabled)
9858 crtc->new_config = &crtc->config;
9859 else
9860 crtc->new_config = NULL;
9861 }
9862 }
9863
9864 /**
9865 * intel_modeset_commit_output_state
9866 *
9867 * This function copies the stage display pipe configuration to the real one.
9868 */
9869 static void intel_modeset_commit_output_state(struct drm_device *dev)
9870 {
9871 struct intel_crtc *crtc;
9872 struct intel_encoder *encoder;
9873 struct intel_connector *connector;
9874
9875 list_for_each_entry(connector, &dev->mode_config.connector_list,
9876 base.head) {
9877 connector->base.encoder = &connector->new_encoder->base;
9878 }
9879
9880 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9881 base.head) {
9882 encoder->base.crtc = &encoder->new_crtc->base;
9883 }
9884
9885 for_each_intel_crtc(dev, crtc) {
9886 crtc->base.enabled = crtc->new_enabled;
9887 }
9888 }
9889
9890 static void
9891 connected_sink_compute_bpp(struct intel_connector *connector,
9892 struct intel_crtc_config *pipe_config)
9893 {
9894 int bpp = pipe_config->pipe_bpp;
9895
9896 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9897 connector->base.base.id,
9898 connector->base.name);
9899
9900 /* Don't use an invalid EDID bpc value */
9901 if (connector->base.display_info.bpc &&
9902 connector->base.display_info.bpc * 3 < bpp) {
9903 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9904 bpp, connector->base.display_info.bpc*3);
9905 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9906 }
9907
9908 /* Clamp bpp to 8 on screens without EDID 1.4 */
9909 if (connector->base.display_info.bpc == 0 && bpp > 24) {
9910 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9911 bpp);
9912 pipe_config->pipe_bpp = 24;
9913 }
9914 }
9915
9916 static int
9917 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9918 struct drm_framebuffer *fb,
9919 struct intel_crtc_config *pipe_config)
9920 {
9921 struct drm_device *dev = crtc->base.dev;
9922 struct intel_connector *connector;
9923 int bpp;
9924
9925 switch (fb->pixel_format) {
9926 case DRM_FORMAT_C8:
9927 bpp = 8*3; /* since we go through a colormap */
9928 break;
9929 case DRM_FORMAT_XRGB1555:
9930 case DRM_FORMAT_ARGB1555:
9931 /* checked in intel_framebuffer_init already */
9932 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9933 return -EINVAL;
9934 case DRM_FORMAT_RGB565:
9935 bpp = 6*3; /* min is 18bpp */
9936 break;
9937 case DRM_FORMAT_XBGR8888:
9938 case DRM_FORMAT_ABGR8888:
9939 /* checked in intel_framebuffer_init already */
9940 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9941 return -EINVAL;
9942 case DRM_FORMAT_XRGB8888:
9943 case DRM_FORMAT_ARGB8888:
9944 bpp = 8*3;
9945 break;
9946 case DRM_FORMAT_XRGB2101010:
9947 case DRM_FORMAT_ARGB2101010:
9948 case DRM_FORMAT_XBGR2101010:
9949 case DRM_FORMAT_ABGR2101010:
9950 /* checked in intel_framebuffer_init already */
9951 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9952 return -EINVAL;
9953 bpp = 10*3;
9954 break;
9955 /* TODO: gen4+ supports 16 bpc floating point, too. */
9956 default:
9957 DRM_DEBUG_KMS("unsupported depth\n");
9958 return -EINVAL;
9959 }
9960
9961 pipe_config->pipe_bpp = bpp;
9962
9963 /* Clamp display bpp to EDID value */
9964 list_for_each_entry(connector, &dev->mode_config.connector_list,
9965 base.head) {
9966 if (!connector->new_encoder ||
9967 connector->new_encoder->new_crtc != crtc)
9968 continue;
9969
9970 connected_sink_compute_bpp(connector, pipe_config);
9971 }
9972
9973 return bpp;
9974 }
9975
9976 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9977 {
9978 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9979 "type: 0x%x flags: 0x%x\n",
9980 mode->crtc_clock,
9981 mode->crtc_hdisplay, mode->crtc_hsync_start,
9982 mode->crtc_hsync_end, mode->crtc_htotal,
9983 mode->crtc_vdisplay, mode->crtc_vsync_start,
9984 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9985 }
9986
9987 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9988 struct intel_crtc_config *pipe_config,
9989 const char *context)
9990 {
9991 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9992 context, pipe_name(crtc->pipe));
9993
9994 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9995 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9996 pipe_config->pipe_bpp, pipe_config->dither);
9997 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9998 pipe_config->has_pch_encoder,
9999 pipe_config->fdi_lanes,
10000 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10001 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10002 pipe_config->fdi_m_n.tu);
10003 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10004 pipe_config->has_dp_encoder,
10005 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10006 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10007 pipe_config->dp_m_n.tu);
10008 DRM_DEBUG_KMS("requested mode:\n");
10009 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
10010 DRM_DEBUG_KMS("adjusted mode:\n");
10011 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
10012 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
10013 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10014 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10015 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10016 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10017 pipe_config->gmch_pfit.control,
10018 pipe_config->gmch_pfit.pgm_ratios,
10019 pipe_config->gmch_pfit.lvds_border_bits);
10020 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10021 pipe_config->pch_pfit.pos,
10022 pipe_config->pch_pfit.size,
10023 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10024 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10025 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10026 }
10027
10028 static bool encoders_cloneable(const struct intel_encoder *a,
10029 const struct intel_encoder *b)
10030 {
10031 /* masks could be asymmetric, so check both ways */
10032 return a == b || (a->cloneable & (1 << b->type) &&
10033 b->cloneable & (1 << a->type));
10034 }
10035
10036 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10037 struct intel_encoder *encoder)
10038 {
10039 struct drm_device *dev = crtc->base.dev;
10040 struct intel_encoder *source_encoder;
10041
10042 list_for_each_entry(source_encoder,
10043 &dev->mode_config.encoder_list, base.head) {
10044 if (source_encoder->new_crtc != crtc)
10045 continue;
10046
10047 if (!encoders_cloneable(encoder, source_encoder))
10048 return false;
10049 }
10050
10051 return true;
10052 }
10053
10054 static bool check_encoder_cloning(struct intel_crtc *crtc)
10055 {
10056 struct drm_device *dev = crtc->base.dev;
10057 struct intel_encoder *encoder;
10058
10059 list_for_each_entry(encoder,
10060 &dev->mode_config.encoder_list, base.head) {
10061 if (encoder->new_crtc != crtc)
10062 continue;
10063
10064 if (!check_single_encoder_cloning(crtc, encoder))
10065 return false;
10066 }
10067
10068 return true;
10069 }
10070
10071 static struct intel_crtc_config *
10072 intel_modeset_pipe_config(struct drm_crtc *crtc,
10073 struct drm_framebuffer *fb,
10074 struct drm_display_mode *mode)
10075 {
10076 struct drm_device *dev = crtc->dev;
10077 struct intel_encoder *encoder;
10078 struct intel_crtc_config *pipe_config;
10079 int plane_bpp, ret = -EINVAL;
10080 bool retry = true;
10081
10082 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10083 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10084 return ERR_PTR(-EINVAL);
10085 }
10086
10087 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10088 if (!pipe_config)
10089 return ERR_PTR(-ENOMEM);
10090
10091 drm_mode_copy(&pipe_config->adjusted_mode, mode);
10092 drm_mode_copy(&pipe_config->requested_mode, mode);
10093
10094 pipe_config->cpu_transcoder =
10095 (enum transcoder) to_intel_crtc(crtc)->pipe;
10096 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10097
10098 /*
10099 * Sanitize sync polarity flags based on requested ones. If neither
10100 * positive or negative polarity is requested, treat this as meaning
10101 * negative polarity.
10102 */
10103 if (!(pipe_config->adjusted_mode.flags &
10104 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10105 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10106
10107 if (!(pipe_config->adjusted_mode.flags &
10108 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10109 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10110
10111 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10112 * plane pixel format and any sink constraints into account. Returns the
10113 * source plane bpp so that dithering can be selected on mismatches
10114 * after encoders and crtc also have had their say. */
10115 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10116 fb, pipe_config);
10117 if (plane_bpp < 0)
10118 goto fail;
10119
10120 /*
10121 * Determine the real pipe dimensions. Note that stereo modes can
10122 * increase the actual pipe size due to the frame doubling and
10123 * insertion of additional space for blanks between the frame. This
10124 * is stored in the crtc timings. We use the requested mode to do this
10125 * computation to clearly distinguish it from the adjusted mode, which
10126 * can be changed by the connectors in the below retry loop.
10127 */
10128 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10129 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10130 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10131
10132 encoder_retry:
10133 /* Ensure the port clock defaults are reset when retrying. */
10134 pipe_config->port_clock = 0;
10135 pipe_config->pixel_multiplier = 1;
10136
10137 /* Fill in default crtc timings, allow encoders to overwrite them. */
10138 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
10139
10140 /* Pass our mode to the connectors and the CRTC to give them a chance to
10141 * adjust it according to limitations or connector properties, and also
10142 * a chance to reject the mode entirely.
10143 */
10144 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10145 base.head) {
10146
10147 if (&encoder->new_crtc->base != crtc)
10148 continue;
10149
10150 if (!(encoder->compute_config(encoder, pipe_config))) {
10151 DRM_DEBUG_KMS("Encoder config failure\n");
10152 goto fail;
10153 }
10154 }
10155
10156 /* Set default port clock if not overwritten by the encoder. Needs to be
10157 * done afterwards in case the encoder adjusts the mode. */
10158 if (!pipe_config->port_clock)
10159 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10160 * pipe_config->pixel_multiplier;
10161
10162 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10163 if (ret < 0) {
10164 DRM_DEBUG_KMS("CRTC fixup failed\n");
10165 goto fail;
10166 }
10167
10168 if (ret == RETRY) {
10169 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10170 ret = -EINVAL;
10171 goto fail;
10172 }
10173
10174 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10175 retry = false;
10176 goto encoder_retry;
10177 }
10178
10179 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10180 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10181 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10182
10183 return pipe_config;
10184 fail:
10185 kfree(pipe_config);
10186 return ERR_PTR(ret);
10187 }
10188
10189 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10190 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10191 static void
10192 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10193 unsigned *prepare_pipes, unsigned *disable_pipes)
10194 {
10195 struct intel_crtc *intel_crtc;
10196 struct drm_device *dev = crtc->dev;
10197 struct intel_encoder *encoder;
10198 struct intel_connector *connector;
10199 struct drm_crtc *tmp_crtc;
10200
10201 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10202
10203 /* Check which crtcs have changed outputs connected to them, these need
10204 * to be part of the prepare_pipes mask. We don't (yet) support global
10205 * modeset across multiple crtcs, so modeset_pipes will only have one
10206 * bit set at most. */
10207 list_for_each_entry(connector, &dev->mode_config.connector_list,
10208 base.head) {
10209 if (connector->base.encoder == &connector->new_encoder->base)
10210 continue;
10211
10212 if (connector->base.encoder) {
10213 tmp_crtc = connector->base.encoder->crtc;
10214
10215 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10216 }
10217
10218 if (connector->new_encoder)
10219 *prepare_pipes |=
10220 1 << connector->new_encoder->new_crtc->pipe;
10221 }
10222
10223 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10224 base.head) {
10225 if (encoder->base.crtc == &encoder->new_crtc->base)
10226 continue;
10227
10228 if (encoder->base.crtc) {
10229 tmp_crtc = encoder->base.crtc;
10230
10231 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10232 }
10233
10234 if (encoder->new_crtc)
10235 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10236 }
10237
10238 /* Check for pipes that will be enabled/disabled ... */
10239 for_each_intel_crtc(dev, intel_crtc) {
10240 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10241 continue;
10242
10243 if (!intel_crtc->new_enabled)
10244 *disable_pipes |= 1 << intel_crtc->pipe;
10245 else
10246 *prepare_pipes |= 1 << intel_crtc->pipe;
10247 }
10248
10249
10250 /* set_mode is also used to update properties on life display pipes. */
10251 intel_crtc = to_intel_crtc(crtc);
10252 if (intel_crtc->new_enabled)
10253 *prepare_pipes |= 1 << intel_crtc->pipe;
10254
10255 /*
10256 * For simplicity do a full modeset on any pipe where the output routing
10257 * changed. We could be more clever, but that would require us to be
10258 * more careful with calling the relevant encoder->mode_set functions.
10259 */
10260 if (*prepare_pipes)
10261 *modeset_pipes = *prepare_pipes;
10262
10263 /* ... and mask these out. */
10264 *modeset_pipes &= ~(*disable_pipes);
10265 *prepare_pipes &= ~(*disable_pipes);
10266
10267 /*
10268 * HACK: We don't (yet) fully support global modesets. intel_set_config
10269 * obies this rule, but the modeset restore mode of
10270 * intel_modeset_setup_hw_state does not.
10271 */
10272 *modeset_pipes &= 1 << intel_crtc->pipe;
10273 *prepare_pipes &= 1 << intel_crtc->pipe;
10274
10275 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10276 *modeset_pipes, *prepare_pipes, *disable_pipes);
10277 }
10278
10279 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10280 {
10281 struct drm_encoder *encoder;
10282 struct drm_device *dev = crtc->dev;
10283
10284 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10285 if (encoder->crtc == crtc)
10286 return true;
10287
10288 return false;
10289 }
10290
10291 static void
10292 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10293 {
10294 struct intel_encoder *intel_encoder;
10295 struct intel_crtc *intel_crtc;
10296 struct drm_connector *connector;
10297
10298 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
10299 base.head) {
10300 if (!intel_encoder->base.crtc)
10301 continue;
10302
10303 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10304
10305 if (prepare_pipes & (1 << intel_crtc->pipe))
10306 intel_encoder->connectors_active = false;
10307 }
10308
10309 intel_modeset_commit_output_state(dev);
10310
10311 /* Double check state. */
10312 for_each_intel_crtc(dev, intel_crtc) {
10313 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10314 WARN_ON(intel_crtc->new_config &&
10315 intel_crtc->new_config != &intel_crtc->config);
10316 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10317 }
10318
10319 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10320 if (!connector->encoder || !connector->encoder->crtc)
10321 continue;
10322
10323 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10324
10325 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10326 struct drm_property *dpms_property =
10327 dev->mode_config.dpms_property;
10328
10329 connector->dpms = DRM_MODE_DPMS_ON;
10330 drm_object_property_set_value(&connector->base,
10331 dpms_property,
10332 DRM_MODE_DPMS_ON);
10333
10334 intel_encoder = to_intel_encoder(connector->encoder);
10335 intel_encoder->connectors_active = true;
10336 }
10337 }
10338
10339 }
10340
10341 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10342 {
10343 int diff;
10344
10345 if (clock1 == clock2)
10346 return true;
10347
10348 if (!clock1 || !clock2)
10349 return false;
10350
10351 diff = abs(clock1 - clock2);
10352
10353 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10354 return true;
10355
10356 return false;
10357 }
10358
10359 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10360 list_for_each_entry((intel_crtc), \
10361 &(dev)->mode_config.crtc_list, \
10362 base.head) \
10363 if (mask & (1 <<(intel_crtc)->pipe))
10364
10365 static bool
10366 intel_pipe_config_compare(struct drm_device *dev,
10367 struct intel_crtc_config *current_config,
10368 struct intel_crtc_config *pipe_config)
10369 {
10370 #define PIPE_CONF_CHECK_X(name) \
10371 if (current_config->name != pipe_config->name) { \
10372 DRM_ERROR("mismatch in " #name " " \
10373 "(expected 0x%08x, found 0x%08x)\n", \
10374 current_config->name, \
10375 pipe_config->name); \
10376 return false; \
10377 }
10378
10379 #define PIPE_CONF_CHECK_I(name) \
10380 if (current_config->name != pipe_config->name) { \
10381 DRM_ERROR("mismatch in " #name " " \
10382 "(expected %i, found %i)\n", \
10383 current_config->name, \
10384 pipe_config->name); \
10385 return false; \
10386 }
10387
10388 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10389 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10390 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10391 "(expected %i, found %i)\n", \
10392 current_config->name & (mask), \
10393 pipe_config->name & (mask)); \
10394 return false; \
10395 }
10396
10397 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10398 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10399 DRM_ERROR("mismatch in " #name " " \
10400 "(expected %i, found %i)\n", \
10401 current_config->name, \
10402 pipe_config->name); \
10403 return false; \
10404 }
10405
10406 #define PIPE_CONF_QUIRK(quirk) \
10407 ((current_config->quirks | pipe_config->quirks) & (quirk))
10408
10409 PIPE_CONF_CHECK_I(cpu_transcoder);
10410
10411 PIPE_CONF_CHECK_I(has_pch_encoder);
10412 PIPE_CONF_CHECK_I(fdi_lanes);
10413 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10414 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10415 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10416 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10417 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10418
10419 PIPE_CONF_CHECK_I(has_dp_encoder);
10420 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10421 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10422 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10423 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10424 PIPE_CONF_CHECK_I(dp_m_n.tu);
10425
10426 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10427 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10428 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10429 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10430 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10431 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10432
10433 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10434 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10435 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10436 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10437 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10438 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10439
10440 PIPE_CONF_CHECK_I(pixel_multiplier);
10441 PIPE_CONF_CHECK_I(has_hdmi_sink);
10442 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10443 IS_VALLEYVIEW(dev))
10444 PIPE_CONF_CHECK_I(limited_color_range);
10445
10446 PIPE_CONF_CHECK_I(has_audio);
10447
10448 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10449 DRM_MODE_FLAG_INTERLACE);
10450
10451 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10452 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10453 DRM_MODE_FLAG_PHSYNC);
10454 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10455 DRM_MODE_FLAG_NHSYNC);
10456 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10457 DRM_MODE_FLAG_PVSYNC);
10458 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10459 DRM_MODE_FLAG_NVSYNC);
10460 }
10461
10462 PIPE_CONF_CHECK_I(pipe_src_w);
10463 PIPE_CONF_CHECK_I(pipe_src_h);
10464
10465 /*
10466 * FIXME: BIOS likes to set up a cloned config with lvds+external
10467 * screen. Since we don't yet re-compute the pipe config when moving
10468 * just the lvds port away to another pipe the sw tracking won't match.
10469 *
10470 * Proper atomic modesets with recomputed global state will fix this.
10471 * Until then just don't check gmch state for inherited modes.
10472 */
10473 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10474 PIPE_CONF_CHECK_I(gmch_pfit.control);
10475 /* pfit ratios are autocomputed by the hw on gen4+ */
10476 if (INTEL_INFO(dev)->gen < 4)
10477 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10478 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10479 }
10480
10481 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10482 if (current_config->pch_pfit.enabled) {
10483 PIPE_CONF_CHECK_I(pch_pfit.pos);
10484 PIPE_CONF_CHECK_I(pch_pfit.size);
10485 }
10486
10487 /* BDW+ don't expose a synchronous way to read the state */
10488 if (IS_HASWELL(dev))
10489 PIPE_CONF_CHECK_I(ips_enabled);
10490
10491 PIPE_CONF_CHECK_I(double_wide);
10492
10493 PIPE_CONF_CHECK_X(ddi_pll_sel);
10494
10495 PIPE_CONF_CHECK_I(shared_dpll);
10496 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10497 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10498 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10499 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10500 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10501
10502 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10503 PIPE_CONF_CHECK_I(pipe_bpp);
10504
10505 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10506 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10507
10508 #undef PIPE_CONF_CHECK_X
10509 #undef PIPE_CONF_CHECK_I
10510 #undef PIPE_CONF_CHECK_FLAGS
10511 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10512 #undef PIPE_CONF_QUIRK
10513
10514 return true;
10515 }
10516
10517 static void
10518 check_connector_state(struct drm_device *dev)
10519 {
10520 struct intel_connector *connector;
10521
10522 list_for_each_entry(connector, &dev->mode_config.connector_list,
10523 base.head) {
10524 /* This also checks the encoder/connector hw state with the
10525 * ->get_hw_state callbacks. */
10526 intel_connector_check_state(connector);
10527
10528 WARN(&connector->new_encoder->base != connector->base.encoder,
10529 "connector's staged encoder doesn't match current encoder\n");
10530 }
10531 }
10532
10533 static void
10534 check_encoder_state(struct drm_device *dev)
10535 {
10536 struct intel_encoder *encoder;
10537 struct intel_connector *connector;
10538
10539 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10540 base.head) {
10541 bool enabled = false;
10542 bool active = false;
10543 enum pipe pipe, tracked_pipe;
10544
10545 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10546 encoder->base.base.id,
10547 encoder->base.name);
10548
10549 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10550 "encoder's stage crtc doesn't match current crtc\n");
10551 WARN(encoder->connectors_active && !encoder->base.crtc,
10552 "encoder's active_connectors set, but no crtc\n");
10553
10554 list_for_each_entry(connector, &dev->mode_config.connector_list,
10555 base.head) {
10556 if (connector->base.encoder != &encoder->base)
10557 continue;
10558 enabled = true;
10559 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10560 active = true;
10561 }
10562 /*
10563 * for MST connectors if we unplug the connector is gone
10564 * away but the encoder is still connected to a crtc
10565 * until a modeset happens in response to the hotplug.
10566 */
10567 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10568 continue;
10569
10570 WARN(!!encoder->base.crtc != enabled,
10571 "encoder's enabled state mismatch "
10572 "(expected %i, found %i)\n",
10573 !!encoder->base.crtc, enabled);
10574 WARN(active && !encoder->base.crtc,
10575 "active encoder with no crtc\n");
10576
10577 WARN(encoder->connectors_active != active,
10578 "encoder's computed active state doesn't match tracked active state "
10579 "(expected %i, found %i)\n", active, encoder->connectors_active);
10580
10581 active = encoder->get_hw_state(encoder, &pipe);
10582 WARN(active != encoder->connectors_active,
10583 "encoder's hw state doesn't match sw tracking "
10584 "(expected %i, found %i)\n",
10585 encoder->connectors_active, active);
10586
10587 if (!encoder->base.crtc)
10588 continue;
10589
10590 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10591 WARN(active && pipe != tracked_pipe,
10592 "active encoder's pipe doesn't match"
10593 "(expected %i, found %i)\n",
10594 tracked_pipe, pipe);
10595
10596 }
10597 }
10598
10599 static void
10600 check_crtc_state(struct drm_device *dev)
10601 {
10602 struct drm_i915_private *dev_priv = dev->dev_private;
10603 struct intel_crtc *crtc;
10604 struct intel_encoder *encoder;
10605 struct intel_crtc_config pipe_config;
10606
10607 for_each_intel_crtc(dev, crtc) {
10608 bool enabled = false;
10609 bool active = false;
10610
10611 memset(&pipe_config, 0, sizeof(pipe_config));
10612
10613 DRM_DEBUG_KMS("[CRTC:%d]\n",
10614 crtc->base.base.id);
10615
10616 WARN(crtc->active && !crtc->base.enabled,
10617 "active crtc, but not enabled in sw tracking\n");
10618
10619 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10620 base.head) {
10621 if (encoder->base.crtc != &crtc->base)
10622 continue;
10623 enabled = true;
10624 if (encoder->connectors_active)
10625 active = true;
10626 }
10627
10628 WARN(active != crtc->active,
10629 "crtc's computed active state doesn't match tracked active state "
10630 "(expected %i, found %i)\n", active, crtc->active);
10631 WARN(enabled != crtc->base.enabled,
10632 "crtc's computed enabled state doesn't match tracked enabled state "
10633 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10634
10635 active = dev_priv->display.get_pipe_config(crtc,
10636 &pipe_config);
10637
10638 /* hw state is inconsistent with the pipe A quirk */
10639 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
10640 active = crtc->active;
10641
10642 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10643 base.head) {
10644 enum pipe pipe;
10645 if (encoder->base.crtc != &crtc->base)
10646 continue;
10647 if (encoder->get_hw_state(encoder, &pipe))
10648 encoder->get_config(encoder, &pipe_config);
10649 }
10650
10651 WARN(crtc->active != active,
10652 "crtc active state doesn't match with hw state "
10653 "(expected %i, found %i)\n", crtc->active, active);
10654
10655 if (active &&
10656 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10657 WARN(1, "pipe state doesn't match!\n");
10658 intel_dump_pipe_config(crtc, &pipe_config,
10659 "[hw state]");
10660 intel_dump_pipe_config(crtc, &crtc->config,
10661 "[sw state]");
10662 }
10663 }
10664 }
10665
10666 static void
10667 check_shared_dpll_state(struct drm_device *dev)
10668 {
10669 struct drm_i915_private *dev_priv = dev->dev_private;
10670 struct intel_crtc *crtc;
10671 struct intel_dpll_hw_state dpll_hw_state;
10672 int i;
10673
10674 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10675 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10676 int enabled_crtcs = 0, active_crtcs = 0;
10677 bool active;
10678
10679 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10680
10681 DRM_DEBUG_KMS("%s\n", pll->name);
10682
10683 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10684
10685 WARN(pll->active > pll->refcount,
10686 "more active pll users than references: %i vs %i\n",
10687 pll->active, pll->refcount);
10688 WARN(pll->active && !pll->on,
10689 "pll in active use but not on in sw tracking\n");
10690 WARN(pll->on && !pll->active,
10691 "pll in on but not on in use in sw tracking\n");
10692 WARN(pll->on != active,
10693 "pll on state mismatch (expected %i, found %i)\n",
10694 pll->on, active);
10695
10696 for_each_intel_crtc(dev, crtc) {
10697 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10698 enabled_crtcs++;
10699 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10700 active_crtcs++;
10701 }
10702 WARN(pll->active != active_crtcs,
10703 "pll active crtcs mismatch (expected %i, found %i)\n",
10704 pll->active, active_crtcs);
10705 WARN(pll->refcount != enabled_crtcs,
10706 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10707 pll->refcount, enabled_crtcs);
10708
10709 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10710 sizeof(dpll_hw_state)),
10711 "pll hw state mismatch\n");
10712 }
10713 }
10714
10715 void
10716 intel_modeset_check_state(struct drm_device *dev)
10717 {
10718 check_connector_state(dev);
10719 check_encoder_state(dev);
10720 check_crtc_state(dev);
10721 check_shared_dpll_state(dev);
10722 }
10723
10724 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10725 int dotclock)
10726 {
10727 /*
10728 * FDI already provided one idea for the dotclock.
10729 * Yell if the encoder disagrees.
10730 */
10731 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10732 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10733 pipe_config->adjusted_mode.crtc_clock, dotclock);
10734 }
10735
10736 static void update_scanline_offset(struct intel_crtc *crtc)
10737 {
10738 struct drm_device *dev = crtc->base.dev;
10739
10740 /*
10741 * The scanline counter increments at the leading edge of hsync.
10742 *
10743 * On most platforms it starts counting from vtotal-1 on the
10744 * first active line. That means the scanline counter value is
10745 * always one less than what we would expect. Ie. just after
10746 * start of vblank, which also occurs at start of hsync (on the
10747 * last active line), the scanline counter will read vblank_start-1.
10748 *
10749 * On gen2 the scanline counter starts counting from 1 instead
10750 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10751 * to keep the value positive), instead of adding one.
10752 *
10753 * On HSW+ the behaviour of the scanline counter depends on the output
10754 * type. For DP ports it behaves like most other platforms, but on HDMI
10755 * there's an extra 1 line difference. So we need to add two instead of
10756 * one to the value.
10757 */
10758 if (IS_GEN2(dev)) {
10759 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10760 int vtotal;
10761
10762 vtotal = mode->crtc_vtotal;
10763 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10764 vtotal /= 2;
10765
10766 crtc->scanline_offset = vtotal - 1;
10767 } else if (HAS_DDI(dev) &&
10768 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
10769 crtc->scanline_offset = 2;
10770 } else
10771 crtc->scanline_offset = 1;
10772 }
10773
10774 static int __intel_set_mode(struct drm_crtc *crtc,
10775 struct drm_display_mode *mode,
10776 int x, int y, struct drm_framebuffer *fb)
10777 {
10778 struct drm_device *dev = crtc->dev;
10779 struct drm_i915_private *dev_priv = dev->dev_private;
10780 struct drm_display_mode *saved_mode;
10781 struct intel_crtc_config *pipe_config = NULL;
10782 struct intel_crtc *intel_crtc;
10783 unsigned disable_pipes, prepare_pipes, modeset_pipes;
10784 int ret = 0;
10785
10786 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10787 if (!saved_mode)
10788 return -ENOMEM;
10789
10790 intel_modeset_affected_pipes(crtc, &modeset_pipes,
10791 &prepare_pipes, &disable_pipes);
10792
10793 *saved_mode = crtc->mode;
10794
10795 /* Hack: Because we don't (yet) support global modeset on multiple
10796 * crtcs, we don't keep track of the new mode for more than one crtc.
10797 * Hence simply check whether any bit is set in modeset_pipes in all the
10798 * pieces of code that are not yet converted to deal with mutliple crtcs
10799 * changing their mode at the same time. */
10800 if (modeset_pipes) {
10801 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10802 if (IS_ERR(pipe_config)) {
10803 ret = PTR_ERR(pipe_config);
10804 pipe_config = NULL;
10805
10806 goto out;
10807 }
10808 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10809 "[modeset]");
10810 to_intel_crtc(crtc)->new_config = pipe_config;
10811 }
10812
10813 /*
10814 * See if the config requires any additional preparation, e.g.
10815 * to adjust global state with pipes off. We need to do this
10816 * here so we can get the modeset_pipe updated config for the new
10817 * mode set on this crtc. For other crtcs we need to use the
10818 * adjusted_mode bits in the crtc directly.
10819 */
10820 if (IS_VALLEYVIEW(dev)) {
10821 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10822
10823 /* may have added more to prepare_pipes than we should */
10824 prepare_pipes &= ~disable_pipes;
10825 }
10826
10827 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10828 intel_crtc_disable(&intel_crtc->base);
10829
10830 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10831 if (intel_crtc->base.enabled)
10832 dev_priv->display.crtc_disable(&intel_crtc->base);
10833 }
10834
10835 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10836 * to set it here already despite that we pass it down the callchain.
10837 */
10838 if (modeset_pipes) {
10839 crtc->mode = *mode;
10840 /* mode_set/enable/disable functions rely on a correct pipe
10841 * config. */
10842 to_intel_crtc(crtc)->config = *pipe_config;
10843 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10844
10845 /*
10846 * Calculate and store various constants which
10847 * are later needed by vblank and swap-completion
10848 * timestamping. They are derived from true hwmode.
10849 */
10850 drm_calc_timestamping_constants(crtc,
10851 &pipe_config->adjusted_mode);
10852 }
10853
10854 /* Only after disabling all output pipelines that will be changed can we
10855 * update the the output configuration. */
10856 intel_modeset_update_state(dev, prepare_pipes);
10857
10858 if (dev_priv->display.modeset_global_resources)
10859 dev_priv->display.modeset_global_resources(dev);
10860
10861 /* Set up the DPLL and any encoders state that needs to adjust or depend
10862 * on the DPLL.
10863 */
10864 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10865 struct drm_framebuffer *old_fb = crtc->primary->fb;
10866 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
10867 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10868
10869 mutex_lock(&dev->struct_mutex);
10870 ret = intel_pin_and_fence_fb_obj(dev,
10871 obj,
10872 NULL);
10873 if (ret != 0) {
10874 DRM_ERROR("pin & fence failed\n");
10875 mutex_unlock(&dev->struct_mutex);
10876 goto done;
10877 }
10878 if (old_fb)
10879 intel_unpin_fb_obj(old_obj);
10880 i915_gem_track_fb(old_obj, obj,
10881 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
10882 mutex_unlock(&dev->struct_mutex);
10883
10884 crtc->primary->fb = fb;
10885 crtc->x = x;
10886 crtc->y = y;
10887
10888 ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
10889 x, y, fb);
10890 if (ret)
10891 goto done;
10892 }
10893
10894 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10895 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10896 update_scanline_offset(intel_crtc);
10897
10898 dev_priv->display.crtc_enable(&intel_crtc->base);
10899 }
10900
10901 /* FIXME: add subpixel order */
10902 done:
10903 if (ret && crtc->enabled)
10904 crtc->mode = *saved_mode;
10905
10906 out:
10907 kfree(pipe_config);
10908 kfree(saved_mode);
10909 return ret;
10910 }
10911
10912 static int intel_set_mode(struct drm_crtc *crtc,
10913 struct drm_display_mode *mode,
10914 int x, int y, struct drm_framebuffer *fb)
10915 {
10916 int ret;
10917
10918 ret = __intel_set_mode(crtc, mode, x, y, fb);
10919
10920 if (ret == 0)
10921 intel_modeset_check_state(crtc->dev);
10922
10923 return ret;
10924 }
10925
10926 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10927 {
10928 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10929 }
10930
10931 #undef for_each_intel_crtc_masked
10932
10933 static void intel_set_config_free(struct intel_set_config *config)
10934 {
10935 if (!config)
10936 return;
10937
10938 kfree(config->save_connector_encoders);
10939 kfree(config->save_encoder_crtcs);
10940 kfree(config->save_crtc_enabled);
10941 kfree(config);
10942 }
10943
10944 static int intel_set_config_save_state(struct drm_device *dev,
10945 struct intel_set_config *config)
10946 {
10947 struct drm_crtc *crtc;
10948 struct drm_encoder *encoder;
10949 struct drm_connector *connector;
10950 int count;
10951
10952 config->save_crtc_enabled =
10953 kcalloc(dev->mode_config.num_crtc,
10954 sizeof(bool), GFP_KERNEL);
10955 if (!config->save_crtc_enabled)
10956 return -ENOMEM;
10957
10958 config->save_encoder_crtcs =
10959 kcalloc(dev->mode_config.num_encoder,
10960 sizeof(struct drm_crtc *), GFP_KERNEL);
10961 if (!config->save_encoder_crtcs)
10962 return -ENOMEM;
10963
10964 config->save_connector_encoders =
10965 kcalloc(dev->mode_config.num_connector,
10966 sizeof(struct drm_encoder *), GFP_KERNEL);
10967 if (!config->save_connector_encoders)
10968 return -ENOMEM;
10969
10970 /* Copy data. Note that driver private data is not affected.
10971 * Should anything bad happen only the expected state is
10972 * restored, not the drivers personal bookkeeping.
10973 */
10974 count = 0;
10975 for_each_crtc(dev, crtc) {
10976 config->save_crtc_enabled[count++] = crtc->enabled;
10977 }
10978
10979 count = 0;
10980 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10981 config->save_encoder_crtcs[count++] = encoder->crtc;
10982 }
10983
10984 count = 0;
10985 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10986 config->save_connector_encoders[count++] = connector->encoder;
10987 }
10988
10989 return 0;
10990 }
10991
10992 static void intel_set_config_restore_state(struct drm_device *dev,
10993 struct intel_set_config *config)
10994 {
10995 struct intel_crtc *crtc;
10996 struct intel_encoder *encoder;
10997 struct intel_connector *connector;
10998 int count;
10999
11000 count = 0;
11001 for_each_intel_crtc(dev, crtc) {
11002 crtc->new_enabled = config->save_crtc_enabled[count++];
11003
11004 if (crtc->new_enabled)
11005 crtc->new_config = &crtc->config;
11006 else
11007 crtc->new_config = NULL;
11008 }
11009
11010 count = 0;
11011 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
11012 encoder->new_crtc =
11013 to_intel_crtc(config->save_encoder_crtcs[count++]);
11014 }
11015
11016 count = 0;
11017 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11018 connector->new_encoder =
11019 to_intel_encoder(config->save_connector_encoders[count++]);
11020 }
11021 }
11022
11023 static bool
11024 is_crtc_connector_off(struct drm_mode_set *set)
11025 {
11026 int i;
11027
11028 if (set->num_connectors == 0)
11029 return false;
11030
11031 if (WARN_ON(set->connectors == NULL))
11032 return false;
11033
11034 for (i = 0; i < set->num_connectors; i++)
11035 if (set->connectors[i]->encoder &&
11036 set->connectors[i]->encoder->crtc == set->crtc &&
11037 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11038 return true;
11039
11040 return false;
11041 }
11042
11043 static void
11044 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11045 struct intel_set_config *config)
11046 {
11047
11048 /* We should be able to check here if the fb has the same properties
11049 * and then just flip_or_move it */
11050 if (is_crtc_connector_off(set)) {
11051 config->mode_changed = true;
11052 } else if (set->crtc->primary->fb != set->fb) {
11053 /*
11054 * If we have no fb, we can only flip as long as the crtc is
11055 * active, otherwise we need a full mode set. The crtc may
11056 * be active if we've only disabled the primary plane, or
11057 * in fastboot situations.
11058 */
11059 if (set->crtc->primary->fb == NULL) {
11060 struct intel_crtc *intel_crtc =
11061 to_intel_crtc(set->crtc);
11062
11063 if (intel_crtc->active) {
11064 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11065 config->fb_changed = true;
11066 } else {
11067 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11068 config->mode_changed = true;
11069 }
11070 } else if (set->fb == NULL) {
11071 config->mode_changed = true;
11072 } else if (set->fb->pixel_format !=
11073 set->crtc->primary->fb->pixel_format) {
11074 config->mode_changed = true;
11075 } else {
11076 config->fb_changed = true;
11077 }
11078 }
11079
11080 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11081 config->fb_changed = true;
11082
11083 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11084 DRM_DEBUG_KMS("modes are different, full mode set\n");
11085 drm_mode_debug_printmodeline(&set->crtc->mode);
11086 drm_mode_debug_printmodeline(set->mode);
11087 config->mode_changed = true;
11088 }
11089
11090 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11091 set->crtc->base.id, config->mode_changed, config->fb_changed);
11092 }
11093
11094 static int
11095 intel_modeset_stage_output_state(struct drm_device *dev,
11096 struct drm_mode_set *set,
11097 struct intel_set_config *config)
11098 {
11099 struct intel_connector *connector;
11100 struct intel_encoder *encoder;
11101 struct intel_crtc *crtc;
11102 int ro;
11103
11104 /* The upper layers ensure that we either disable a crtc or have a list
11105 * of connectors. For paranoia, double-check this. */
11106 WARN_ON(!set->fb && (set->num_connectors != 0));
11107 WARN_ON(set->fb && (set->num_connectors == 0));
11108
11109 list_for_each_entry(connector, &dev->mode_config.connector_list,
11110 base.head) {
11111 /* Otherwise traverse passed in connector list and get encoders
11112 * for them. */
11113 for (ro = 0; ro < set->num_connectors; ro++) {
11114 if (set->connectors[ro] == &connector->base) {
11115 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11116 break;
11117 }
11118 }
11119
11120 /* If we disable the crtc, disable all its connectors. Also, if
11121 * the connector is on the changing crtc but not on the new
11122 * connector list, disable it. */
11123 if ((!set->fb || ro == set->num_connectors) &&
11124 connector->base.encoder &&
11125 connector->base.encoder->crtc == set->crtc) {
11126 connector->new_encoder = NULL;
11127
11128 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11129 connector->base.base.id,
11130 connector->base.name);
11131 }
11132
11133
11134 if (&connector->new_encoder->base != connector->base.encoder) {
11135 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11136 config->mode_changed = true;
11137 }
11138 }
11139 /* connector->new_encoder is now updated for all connectors. */
11140
11141 /* Update crtc of enabled connectors. */
11142 list_for_each_entry(connector, &dev->mode_config.connector_list,
11143 base.head) {
11144 struct drm_crtc *new_crtc;
11145
11146 if (!connector->new_encoder)
11147 continue;
11148
11149 new_crtc = connector->new_encoder->base.crtc;
11150
11151 for (ro = 0; ro < set->num_connectors; ro++) {
11152 if (set->connectors[ro] == &connector->base)
11153 new_crtc = set->crtc;
11154 }
11155
11156 /* Make sure the new CRTC will work with the encoder */
11157 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11158 new_crtc)) {
11159 return -EINVAL;
11160 }
11161 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11162
11163 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11164 connector->base.base.id,
11165 connector->base.name,
11166 new_crtc->base.id);
11167 }
11168
11169 /* Check for any encoders that needs to be disabled. */
11170 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11171 base.head) {
11172 int num_connectors = 0;
11173 list_for_each_entry(connector,
11174 &dev->mode_config.connector_list,
11175 base.head) {
11176 if (connector->new_encoder == encoder) {
11177 WARN_ON(!connector->new_encoder->new_crtc);
11178 num_connectors++;
11179 }
11180 }
11181
11182 if (num_connectors == 0)
11183 encoder->new_crtc = NULL;
11184 else if (num_connectors > 1)
11185 return -EINVAL;
11186
11187 /* Only now check for crtc changes so we don't miss encoders
11188 * that will be disabled. */
11189 if (&encoder->new_crtc->base != encoder->base.crtc) {
11190 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11191 config->mode_changed = true;
11192 }
11193 }
11194 /* Now we've also updated encoder->new_crtc for all encoders. */
11195 list_for_each_entry(connector, &dev->mode_config.connector_list,
11196 base.head) {
11197 if (connector->new_encoder)
11198 if (connector->new_encoder != connector->encoder)
11199 connector->encoder = connector->new_encoder;
11200 }
11201 for_each_intel_crtc(dev, crtc) {
11202 crtc->new_enabled = false;
11203
11204 list_for_each_entry(encoder,
11205 &dev->mode_config.encoder_list,
11206 base.head) {
11207 if (encoder->new_crtc == crtc) {
11208 crtc->new_enabled = true;
11209 break;
11210 }
11211 }
11212
11213 if (crtc->new_enabled != crtc->base.enabled) {
11214 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11215 crtc->new_enabled ? "en" : "dis");
11216 config->mode_changed = true;
11217 }
11218
11219 if (crtc->new_enabled)
11220 crtc->new_config = &crtc->config;
11221 else
11222 crtc->new_config = NULL;
11223 }
11224
11225 return 0;
11226 }
11227
11228 static void disable_crtc_nofb(struct intel_crtc *crtc)
11229 {
11230 struct drm_device *dev = crtc->base.dev;
11231 struct intel_encoder *encoder;
11232 struct intel_connector *connector;
11233
11234 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11235 pipe_name(crtc->pipe));
11236
11237 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11238 if (connector->new_encoder &&
11239 connector->new_encoder->new_crtc == crtc)
11240 connector->new_encoder = NULL;
11241 }
11242
11243 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
11244 if (encoder->new_crtc == crtc)
11245 encoder->new_crtc = NULL;
11246 }
11247
11248 crtc->new_enabled = false;
11249 crtc->new_config = NULL;
11250 }
11251
11252 static int intel_crtc_set_config(struct drm_mode_set *set)
11253 {
11254 struct drm_device *dev;
11255 struct drm_mode_set save_set;
11256 struct intel_set_config *config;
11257 int ret;
11258
11259 BUG_ON(!set);
11260 BUG_ON(!set->crtc);
11261 BUG_ON(!set->crtc->helper_private);
11262
11263 /* Enforce sane interface api - has been abused by the fb helper. */
11264 BUG_ON(!set->mode && set->fb);
11265 BUG_ON(set->fb && set->num_connectors == 0);
11266
11267 if (set->fb) {
11268 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11269 set->crtc->base.id, set->fb->base.id,
11270 (int)set->num_connectors, set->x, set->y);
11271 } else {
11272 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11273 }
11274
11275 dev = set->crtc->dev;
11276
11277 ret = -ENOMEM;
11278 config = kzalloc(sizeof(*config), GFP_KERNEL);
11279 if (!config)
11280 goto out_config;
11281
11282 ret = intel_set_config_save_state(dev, config);
11283 if (ret)
11284 goto out_config;
11285
11286 save_set.crtc = set->crtc;
11287 save_set.mode = &set->crtc->mode;
11288 save_set.x = set->crtc->x;
11289 save_set.y = set->crtc->y;
11290 save_set.fb = set->crtc->primary->fb;
11291
11292 /* Compute whether we need a full modeset, only an fb base update or no
11293 * change at all. In the future we might also check whether only the
11294 * mode changed, e.g. for LVDS where we only change the panel fitter in
11295 * such cases. */
11296 intel_set_config_compute_mode_changes(set, config);
11297
11298 ret = intel_modeset_stage_output_state(dev, set, config);
11299 if (ret)
11300 goto fail;
11301
11302 if (config->mode_changed) {
11303 ret = intel_set_mode(set->crtc, set->mode,
11304 set->x, set->y, set->fb);
11305 } else if (config->fb_changed) {
11306 struct drm_i915_private *dev_priv = dev->dev_private;
11307 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11308
11309 intel_crtc_wait_for_pending_flips(set->crtc);
11310
11311 ret = intel_pipe_set_base(set->crtc,
11312 set->x, set->y, set->fb);
11313
11314 /*
11315 * We need to make sure the primary plane is re-enabled if it
11316 * has previously been turned off.
11317 */
11318 if (!intel_crtc->primary_enabled && ret == 0) {
11319 WARN_ON(!intel_crtc->active);
11320 intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane,
11321 intel_crtc->pipe);
11322 }
11323
11324 /*
11325 * In the fastboot case this may be our only check of the
11326 * state after boot. It would be better to only do it on
11327 * the first update, but we don't have a nice way of doing that
11328 * (and really, set_config isn't used much for high freq page
11329 * flipping, so increasing its cost here shouldn't be a big
11330 * deal).
11331 */
11332 if (i915.fastboot && ret == 0)
11333 intel_modeset_check_state(set->crtc->dev);
11334 }
11335
11336 if (ret) {
11337 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11338 set->crtc->base.id, ret);
11339 fail:
11340 intel_set_config_restore_state(dev, config);
11341
11342 /*
11343 * HACK: if the pipe was on, but we didn't have a framebuffer,
11344 * force the pipe off to avoid oopsing in the modeset code
11345 * due to fb==NULL. This should only happen during boot since
11346 * we don't yet reconstruct the FB from the hardware state.
11347 */
11348 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11349 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11350
11351 /* Try to restore the config */
11352 if (config->mode_changed &&
11353 intel_set_mode(save_set.crtc, save_set.mode,
11354 save_set.x, save_set.y, save_set.fb))
11355 DRM_ERROR("failed to restore config after modeset failure\n");
11356 }
11357
11358 out_config:
11359 intel_set_config_free(config);
11360 return ret;
11361 }
11362
11363 static const struct drm_crtc_funcs intel_crtc_funcs = {
11364 .gamma_set = intel_crtc_gamma_set,
11365 .set_config = intel_crtc_set_config,
11366 .destroy = intel_crtc_destroy,
11367 .page_flip = intel_crtc_page_flip,
11368 };
11369
11370 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11371 struct intel_shared_dpll *pll,
11372 struct intel_dpll_hw_state *hw_state)
11373 {
11374 uint32_t val;
11375
11376 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS))
11377 return false;
11378
11379 val = I915_READ(PCH_DPLL(pll->id));
11380 hw_state->dpll = val;
11381 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11382 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11383
11384 return val & DPLL_VCO_ENABLE;
11385 }
11386
11387 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11388 struct intel_shared_dpll *pll)
11389 {
11390 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
11391 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
11392 }
11393
11394 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11395 struct intel_shared_dpll *pll)
11396 {
11397 /* PCH refclock must be enabled first */
11398 ibx_assert_pch_refclk_enabled(dev_priv);
11399
11400 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11401
11402 /* Wait for the clocks to stabilize. */
11403 POSTING_READ(PCH_DPLL(pll->id));
11404 udelay(150);
11405
11406 /* The pixel multiplier can only be updated once the
11407 * DPLL is enabled and the clocks are stable.
11408 *
11409 * So write it again.
11410 */
11411 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11412 POSTING_READ(PCH_DPLL(pll->id));
11413 udelay(200);
11414 }
11415
11416 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11417 struct intel_shared_dpll *pll)
11418 {
11419 struct drm_device *dev = dev_priv->dev;
11420 struct intel_crtc *crtc;
11421
11422 /* Make sure no transcoder isn't still depending on us. */
11423 for_each_intel_crtc(dev, crtc) {
11424 if (intel_crtc_to_shared_dpll(crtc) == pll)
11425 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11426 }
11427
11428 I915_WRITE(PCH_DPLL(pll->id), 0);
11429 POSTING_READ(PCH_DPLL(pll->id));
11430 udelay(200);
11431 }
11432
11433 static char *ibx_pch_dpll_names[] = {
11434 "PCH DPLL A",
11435 "PCH DPLL B",
11436 };
11437
11438 static void ibx_pch_dpll_init(struct drm_device *dev)
11439 {
11440 struct drm_i915_private *dev_priv = dev->dev_private;
11441 int i;
11442
11443 dev_priv->num_shared_dpll = 2;
11444
11445 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11446 dev_priv->shared_dplls[i].id = i;
11447 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11448 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11449 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11450 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11451 dev_priv->shared_dplls[i].get_hw_state =
11452 ibx_pch_dpll_get_hw_state;
11453 }
11454 }
11455
11456 static void intel_shared_dpll_init(struct drm_device *dev)
11457 {
11458 struct drm_i915_private *dev_priv = dev->dev_private;
11459
11460 if (HAS_DDI(dev))
11461 intel_ddi_pll_init(dev);
11462 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11463 ibx_pch_dpll_init(dev);
11464 else
11465 dev_priv->num_shared_dpll = 0;
11466
11467 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11468 }
11469
11470 static int
11471 intel_primary_plane_disable(struct drm_plane *plane)
11472 {
11473 struct drm_device *dev = plane->dev;
11474 struct drm_i915_private *dev_priv = dev->dev_private;
11475 struct intel_plane *intel_plane = to_intel_plane(plane);
11476 struct intel_crtc *intel_crtc;
11477
11478 if (!plane->fb)
11479 return 0;
11480
11481 BUG_ON(!plane->crtc);
11482
11483 intel_crtc = to_intel_crtc(plane->crtc);
11484
11485 /*
11486 * Even though we checked plane->fb above, it's still possible that
11487 * the primary plane has been implicitly disabled because the crtc
11488 * coordinates given weren't visible, or because we detected
11489 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11490 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11491 * In either case, we need to unpin the FB and let the fb pointer get
11492 * updated, but otherwise we don't need to touch the hardware.
11493 */
11494 if (!intel_crtc->primary_enabled)
11495 goto disable_unpin;
11496
11497 intel_crtc_wait_for_pending_flips(plane->crtc);
11498 intel_disable_primary_hw_plane(dev_priv, intel_plane->plane,
11499 intel_plane->pipe);
11500 disable_unpin:
11501 mutex_lock(&dev->struct_mutex);
11502 i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
11503 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11504 intel_unpin_fb_obj(intel_fb_obj(plane->fb));
11505 mutex_unlock(&dev->struct_mutex);
11506 plane->fb = NULL;
11507
11508 return 0;
11509 }
11510
11511 static int
11512 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11513 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11514 unsigned int crtc_w, unsigned int crtc_h,
11515 uint32_t src_x, uint32_t src_y,
11516 uint32_t src_w, uint32_t src_h)
11517 {
11518 struct drm_device *dev = crtc->dev;
11519 struct drm_i915_private *dev_priv = dev->dev_private;
11520 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11521 struct intel_plane *intel_plane = to_intel_plane(plane);
11522 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11523 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11524 struct drm_rect dest = {
11525 /* integer pixels */
11526 .x1 = crtc_x,
11527 .y1 = crtc_y,
11528 .x2 = crtc_x + crtc_w,
11529 .y2 = crtc_y + crtc_h,
11530 };
11531 struct drm_rect src = {
11532 /* 16.16 fixed point */
11533 .x1 = src_x,
11534 .y1 = src_y,
11535 .x2 = src_x + src_w,
11536 .y2 = src_y + src_h,
11537 };
11538 const struct drm_rect clip = {
11539 /* integer pixels */
11540 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
11541 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
11542 };
11543 bool visible;
11544 int ret;
11545
11546 ret = drm_plane_helper_check_update(plane, crtc, fb,
11547 &src, &dest, &clip,
11548 DRM_PLANE_HELPER_NO_SCALING,
11549 DRM_PLANE_HELPER_NO_SCALING,
11550 false, true, &visible);
11551
11552 if (ret)
11553 return ret;
11554
11555 /*
11556 * If the CRTC isn't enabled, we're just pinning the framebuffer,
11557 * updating the fb pointer, and returning without touching the
11558 * hardware. This allows us to later do a drmModeSetCrtc with fb=-1 to
11559 * turn on the display with all planes setup as desired.
11560 */
11561 if (!crtc->enabled) {
11562 mutex_lock(&dev->struct_mutex);
11563
11564 /*
11565 * If we already called setplane while the crtc was disabled,
11566 * we may have an fb pinned; unpin it.
11567 */
11568 if (plane->fb)
11569 intel_unpin_fb_obj(old_obj);
11570
11571 i915_gem_track_fb(old_obj, obj,
11572 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11573
11574 /* Pin and return without programming hardware */
11575 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11576 mutex_unlock(&dev->struct_mutex);
11577
11578 return ret;
11579 }
11580
11581 intel_crtc_wait_for_pending_flips(crtc);
11582
11583 /*
11584 * If clipping results in a non-visible primary plane, we'll disable
11585 * the primary plane. Note that this is a bit different than what
11586 * happens if userspace explicitly disables the plane by passing fb=0
11587 * because plane->fb still gets set and pinned.
11588 */
11589 if (!visible) {
11590 mutex_lock(&dev->struct_mutex);
11591
11592 /*
11593 * Try to pin the new fb first so that we can bail out if we
11594 * fail.
11595 */
11596 if (plane->fb != fb) {
11597 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11598 if (ret) {
11599 mutex_unlock(&dev->struct_mutex);
11600 return ret;
11601 }
11602 }
11603
11604 i915_gem_track_fb(old_obj, obj,
11605 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11606
11607 if (intel_crtc->primary_enabled)
11608 intel_disable_primary_hw_plane(dev_priv,
11609 intel_plane->plane,
11610 intel_plane->pipe);
11611
11612
11613 if (plane->fb != fb)
11614 if (plane->fb)
11615 intel_unpin_fb_obj(old_obj);
11616
11617 mutex_unlock(&dev->struct_mutex);
11618
11619 return 0;
11620 }
11621
11622 ret = intel_pipe_set_base(crtc, src.x1, src.y1, fb);
11623 if (ret)
11624 return ret;
11625
11626 if (!intel_crtc->primary_enabled)
11627 intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane,
11628 intel_crtc->pipe);
11629
11630 return 0;
11631 }
11632
11633 /* Common destruction function for both primary and cursor planes */
11634 static void intel_plane_destroy(struct drm_plane *plane)
11635 {
11636 struct intel_plane *intel_plane = to_intel_plane(plane);
11637 drm_plane_cleanup(plane);
11638 kfree(intel_plane);
11639 }
11640
11641 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11642 .update_plane = intel_primary_plane_setplane,
11643 .disable_plane = intel_primary_plane_disable,
11644 .destroy = intel_plane_destroy,
11645 };
11646
11647 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11648 int pipe)
11649 {
11650 struct intel_plane *primary;
11651 const uint32_t *intel_primary_formats;
11652 int num_formats;
11653
11654 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11655 if (primary == NULL)
11656 return NULL;
11657
11658 primary->can_scale = false;
11659 primary->max_downscale = 1;
11660 primary->pipe = pipe;
11661 primary->plane = pipe;
11662 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11663 primary->plane = !pipe;
11664
11665 if (INTEL_INFO(dev)->gen <= 3) {
11666 intel_primary_formats = intel_primary_formats_gen2;
11667 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11668 } else {
11669 intel_primary_formats = intel_primary_formats_gen4;
11670 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11671 }
11672
11673 drm_universal_plane_init(dev, &primary->base, 0,
11674 &intel_primary_plane_funcs,
11675 intel_primary_formats, num_formats,
11676 DRM_PLANE_TYPE_PRIMARY);
11677 return &primary->base;
11678 }
11679
11680 static int
11681 intel_cursor_plane_disable(struct drm_plane *plane)
11682 {
11683 if (!plane->fb)
11684 return 0;
11685
11686 BUG_ON(!plane->crtc);
11687
11688 return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
11689 }
11690
11691 static int
11692 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
11693 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11694 unsigned int crtc_w, unsigned int crtc_h,
11695 uint32_t src_x, uint32_t src_y,
11696 uint32_t src_w, uint32_t src_h)
11697 {
11698 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11699 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11700 struct drm_i915_gem_object *obj = intel_fb->obj;
11701 struct drm_rect dest = {
11702 /* integer pixels */
11703 .x1 = crtc_x,
11704 .y1 = crtc_y,
11705 .x2 = crtc_x + crtc_w,
11706 .y2 = crtc_y + crtc_h,
11707 };
11708 struct drm_rect src = {
11709 /* 16.16 fixed point */
11710 .x1 = src_x,
11711 .y1 = src_y,
11712 .x2 = src_x + src_w,
11713 .y2 = src_y + src_h,
11714 };
11715 const struct drm_rect clip = {
11716 /* integer pixels */
11717 .x2 = intel_crtc->config.pipe_src_w,
11718 .y2 = intel_crtc->config.pipe_src_h,
11719 };
11720 bool visible;
11721 int ret;
11722
11723 ret = drm_plane_helper_check_update(plane, crtc, fb,
11724 &src, &dest, &clip,
11725 DRM_PLANE_HELPER_NO_SCALING,
11726 DRM_PLANE_HELPER_NO_SCALING,
11727 true, true, &visible);
11728 if (ret)
11729 return ret;
11730
11731 crtc->cursor_x = crtc_x;
11732 crtc->cursor_y = crtc_y;
11733 if (fb != crtc->cursor->fb) {
11734 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
11735 } else {
11736 intel_crtc_update_cursor(crtc, visible);
11737 return 0;
11738 }
11739 }
11740 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
11741 .update_plane = intel_cursor_plane_update,
11742 .disable_plane = intel_cursor_plane_disable,
11743 .destroy = intel_plane_destroy,
11744 };
11745
11746 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
11747 int pipe)
11748 {
11749 struct intel_plane *cursor;
11750
11751 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
11752 if (cursor == NULL)
11753 return NULL;
11754
11755 cursor->can_scale = false;
11756 cursor->max_downscale = 1;
11757 cursor->pipe = pipe;
11758 cursor->plane = pipe;
11759
11760 drm_universal_plane_init(dev, &cursor->base, 0,
11761 &intel_cursor_plane_funcs,
11762 intel_cursor_formats,
11763 ARRAY_SIZE(intel_cursor_formats),
11764 DRM_PLANE_TYPE_CURSOR);
11765 return &cursor->base;
11766 }
11767
11768 static void intel_crtc_init(struct drm_device *dev, int pipe)
11769 {
11770 struct drm_i915_private *dev_priv = dev->dev_private;
11771 struct intel_crtc *intel_crtc;
11772 struct drm_plane *primary = NULL;
11773 struct drm_plane *cursor = NULL;
11774 int i, ret;
11775
11776 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
11777 if (intel_crtc == NULL)
11778 return;
11779
11780 primary = intel_primary_plane_create(dev, pipe);
11781 if (!primary)
11782 goto fail;
11783
11784 cursor = intel_cursor_plane_create(dev, pipe);
11785 if (!cursor)
11786 goto fail;
11787
11788 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
11789 cursor, &intel_crtc_funcs);
11790 if (ret)
11791 goto fail;
11792
11793 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
11794 for (i = 0; i < 256; i++) {
11795 intel_crtc->lut_r[i] = i;
11796 intel_crtc->lut_g[i] = i;
11797 intel_crtc->lut_b[i] = i;
11798 }
11799
11800 /*
11801 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
11802 * is hooked to pipe B. Hence we want plane A feeding pipe B.
11803 */
11804 intel_crtc->pipe = pipe;
11805 intel_crtc->plane = pipe;
11806 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
11807 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
11808 intel_crtc->plane = !pipe;
11809 }
11810
11811 intel_crtc->cursor_base = ~0;
11812 intel_crtc->cursor_cntl = ~0;
11813
11814 init_waitqueue_head(&intel_crtc->vbl_wait);
11815
11816 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
11817 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
11818 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
11819 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
11820
11821 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
11822
11823 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
11824 return;
11825
11826 fail:
11827 if (primary)
11828 drm_plane_cleanup(primary);
11829 if (cursor)
11830 drm_plane_cleanup(cursor);
11831 kfree(intel_crtc);
11832 }
11833
11834 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
11835 {
11836 struct drm_encoder *encoder = connector->base.encoder;
11837 struct drm_device *dev = connector->base.dev;
11838
11839 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
11840
11841 if (!encoder)
11842 return INVALID_PIPE;
11843
11844 return to_intel_crtc(encoder->crtc)->pipe;
11845 }
11846
11847 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
11848 struct drm_file *file)
11849 {
11850 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
11851 struct drm_crtc *drmmode_crtc;
11852 struct intel_crtc *crtc;
11853
11854 if (!drm_core_check_feature(dev, DRIVER_MODESET))
11855 return -ENODEV;
11856
11857 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
11858
11859 if (!drmmode_crtc) {
11860 DRM_ERROR("no such CRTC id\n");
11861 return -ENOENT;
11862 }
11863
11864 crtc = to_intel_crtc(drmmode_crtc);
11865 pipe_from_crtc_id->pipe = crtc->pipe;
11866
11867 return 0;
11868 }
11869
11870 static int intel_encoder_clones(struct intel_encoder *encoder)
11871 {
11872 struct drm_device *dev = encoder->base.dev;
11873 struct intel_encoder *source_encoder;
11874 int index_mask = 0;
11875 int entry = 0;
11876
11877 list_for_each_entry(source_encoder,
11878 &dev->mode_config.encoder_list, base.head) {
11879 if (encoders_cloneable(encoder, source_encoder))
11880 index_mask |= (1 << entry);
11881
11882 entry++;
11883 }
11884
11885 return index_mask;
11886 }
11887
11888 static bool has_edp_a(struct drm_device *dev)
11889 {
11890 struct drm_i915_private *dev_priv = dev->dev_private;
11891
11892 if (!IS_MOBILE(dev))
11893 return false;
11894
11895 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
11896 return false;
11897
11898 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
11899 return false;
11900
11901 return true;
11902 }
11903
11904 const char *intel_output_name(int output)
11905 {
11906 static const char *names[] = {
11907 [INTEL_OUTPUT_UNUSED] = "Unused",
11908 [INTEL_OUTPUT_ANALOG] = "Analog",
11909 [INTEL_OUTPUT_DVO] = "DVO",
11910 [INTEL_OUTPUT_SDVO] = "SDVO",
11911 [INTEL_OUTPUT_LVDS] = "LVDS",
11912 [INTEL_OUTPUT_TVOUT] = "TV",
11913 [INTEL_OUTPUT_HDMI] = "HDMI",
11914 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
11915 [INTEL_OUTPUT_EDP] = "eDP",
11916 [INTEL_OUTPUT_DSI] = "DSI",
11917 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
11918 };
11919
11920 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
11921 return "Invalid";
11922
11923 return names[output];
11924 }
11925
11926 static bool intel_crt_present(struct drm_device *dev)
11927 {
11928 struct drm_i915_private *dev_priv = dev->dev_private;
11929
11930 if (IS_ULT(dev))
11931 return false;
11932
11933 if (IS_CHERRYVIEW(dev))
11934 return false;
11935
11936 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
11937 return false;
11938
11939 return true;
11940 }
11941
11942 static void intel_setup_outputs(struct drm_device *dev)
11943 {
11944 struct drm_i915_private *dev_priv = dev->dev_private;
11945 struct intel_encoder *encoder;
11946 bool dpd_is_edp = false;
11947
11948 intel_lvds_init(dev);
11949
11950 if (intel_crt_present(dev))
11951 intel_crt_init(dev);
11952
11953 if (HAS_DDI(dev)) {
11954 int found;
11955
11956 /* Haswell uses DDI functions to detect digital outputs */
11957 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
11958 /* DDI A only supports eDP */
11959 if (found)
11960 intel_ddi_init(dev, PORT_A);
11961
11962 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
11963 * register */
11964 found = I915_READ(SFUSE_STRAP);
11965
11966 if (found & SFUSE_STRAP_DDIB_DETECTED)
11967 intel_ddi_init(dev, PORT_B);
11968 if (found & SFUSE_STRAP_DDIC_DETECTED)
11969 intel_ddi_init(dev, PORT_C);
11970 if (found & SFUSE_STRAP_DDID_DETECTED)
11971 intel_ddi_init(dev, PORT_D);
11972 } else if (HAS_PCH_SPLIT(dev)) {
11973 int found;
11974 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
11975
11976 if (has_edp_a(dev))
11977 intel_dp_init(dev, DP_A, PORT_A);
11978
11979 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
11980 /* PCH SDVOB multiplex with HDMIB */
11981 found = intel_sdvo_init(dev, PCH_SDVOB, true);
11982 if (!found)
11983 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
11984 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
11985 intel_dp_init(dev, PCH_DP_B, PORT_B);
11986 }
11987
11988 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
11989 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
11990
11991 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
11992 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
11993
11994 if (I915_READ(PCH_DP_C) & DP_DETECTED)
11995 intel_dp_init(dev, PCH_DP_C, PORT_C);
11996
11997 if (I915_READ(PCH_DP_D) & DP_DETECTED)
11998 intel_dp_init(dev, PCH_DP_D, PORT_D);
11999 } else if (IS_VALLEYVIEW(dev)) {
12000 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
12001 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12002 PORT_B);
12003 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
12004 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12005 }
12006
12007 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
12008 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12009 PORT_C);
12010 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
12011 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12012 }
12013
12014 if (IS_CHERRYVIEW(dev)) {
12015 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) {
12016 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12017 PORT_D);
12018 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12019 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12020 }
12021 }
12022
12023 intel_dsi_init(dev);
12024 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12025 bool found = false;
12026
12027 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12028 DRM_DEBUG_KMS("probing SDVOB\n");
12029 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12030 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12031 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12032 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12033 }
12034
12035 if (!found && SUPPORTS_INTEGRATED_DP(dev))
12036 intel_dp_init(dev, DP_B, PORT_B);
12037 }
12038
12039 /* Before G4X SDVOC doesn't have its own detect register */
12040
12041 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12042 DRM_DEBUG_KMS("probing SDVOC\n");
12043 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12044 }
12045
12046 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12047
12048 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12049 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12050 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12051 }
12052 if (SUPPORTS_INTEGRATED_DP(dev))
12053 intel_dp_init(dev, DP_C, PORT_C);
12054 }
12055
12056 if (SUPPORTS_INTEGRATED_DP(dev) &&
12057 (I915_READ(DP_D) & DP_DETECTED))
12058 intel_dp_init(dev, DP_D, PORT_D);
12059 } else if (IS_GEN2(dev))
12060 intel_dvo_init(dev);
12061
12062 if (SUPPORTS_TV(dev))
12063 intel_tv_init(dev);
12064
12065 intel_edp_psr_init(dev);
12066
12067 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
12068 encoder->base.possible_crtcs = encoder->crtc_mask;
12069 encoder->base.possible_clones =
12070 intel_encoder_clones(encoder);
12071 }
12072
12073 intel_init_pch_refclk(dev);
12074
12075 drm_helper_move_panel_connectors_to_head(dev);
12076 }
12077
12078 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12079 {
12080 struct drm_device *dev = fb->dev;
12081 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12082
12083 drm_framebuffer_cleanup(fb);
12084 mutex_lock(&dev->struct_mutex);
12085 WARN_ON(!intel_fb->obj->framebuffer_references--);
12086 drm_gem_object_unreference(&intel_fb->obj->base);
12087 mutex_unlock(&dev->struct_mutex);
12088 kfree(intel_fb);
12089 }
12090
12091 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12092 struct drm_file *file,
12093 unsigned int *handle)
12094 {
12095 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12096 struct drm_i915_gem_object *obj = intel_fb->obj;
12097
12098 return drm_gem_handle_create(file, &obj->base, handle);
12099 }
12100
12101 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12102 .destroy = intel_user_framebuffer_destroy,
12103 .create_handle = intel_user_framebuffer_create_handle,
12104 };
12105
12106 static int intel_framebuffer_init(struct drm_device *dev,
12107 struct intel_framebuffer *intel_fb,
12108 struct drm_mode_fb_cmd2 *mode_cmd,
12109 struct drm_i915_gem_object *obj)
12110 {
12111 int aligned_height;
12112 int pitch_limit;
12113 int ret;
12114
12115 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12116
12117 if (obj->tiling_mode == I915_TILING_Y) {
12118 DRM_DEBUG("hardware does not support tiling Y\n");
12119 return -EINVAL;
12120 }
12121
12122 if (mode_cmd->pitches[0] & 63) {
12123 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12124 mode_cmd->pitches[0]);
12125 return -EINVAL;
12126 }
12127
12128 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12129 pitch_limit = 32*1024;
12130 } else if (INTEL_INFO(dev)->gen >= 4) {
12131 if (obj->tiling_mode)
12132 pitch_limit = 16*1024;
12133 else
12134 pitch_limit = 32*1024;
12135 } else if (INTEL_INFO(dev)->gen >= 3) {
12136 if (obj->tiling_mode)
12137 pitch_limit = 8*1024;
12138 else
12139 pitch_limit = 16*1024;
12140 } else
12141 /* XXX DSPC is limited to 4k tiled */
12142 pitch_limit = 8*1024;
12143
12144 if (mode_cmd->pitches[0] > pitch_limit) {
12145 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12146 obj->tiling_mode ? "tiled" : "linear",
12147 mode_cmd->pitches[0], pitch_limit);
12148 return -EINVAL;
12149 }
12150
12151 if (obj->tiling_mode != I915_TILING_NONE &&
12152 mode_cmd->pitches[0] != obj->stride) {
12153 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12154 mode_cmd->pitches[0], obj->stride);
12155 return -EINVAL;
12156 }
12157
12158 /* Reject formats not supported by any plane early. */
12159 switch (mode_cmd->pixel_format) {
12160 case DRM_FORMAT_C8:
12161 case DRM_FORMAT_RGB565:
12162 case DRM_FORMAT_XRGB8888:
12163 case DRM_FORMAT_ARGB8888:
12164 break;
12165 case DRM_FORMAT_XRGB1555:
12166 case DRM_FORMAT_ARGB1555:
12167 if (INTEL_INFO(dev)->gen > 3) {
12168 DRM_DEBUG("unsupported pixel format: %s\n",
12169 drm_get_format_name(mode_cmd->pixel_format));
12170 return -EINVAL;
12171 }
12172 break;
12173 case DRM_FORMAT_XBGR8888:
12174 case DRM_FORMAT_ABGR8888:
12175 case DRM_FORMAT_XRGB2101010:
12176 case DRM_FORMAT_ARGB2101010:
12177 case DRM_FORMAT_XBGR2101010:
12178 case DRM_FORMAT_ABGR2101010:
12179 if (INTEL_INFO(dev)->gen < 4) {
12180 DRM_DEBUG("unsupported pixel format: %s\n",
12181 drm_get_format_name(mode_cmd->pixel_format));
12182 return -EINVAL;
12183 }
12184 break;
12185 case DRM_FORMAT_YUYV:
12186 case DRM_FORMAT_UYVY:
12187 case DRM_FORMAT_YVYU:
12188 case DRM_FORMAT_VYUY:
12189 if (INTEL_INFO(dev)->gen < 5) {
12190 DRM_DEBUG("unsupported pixel format: %s\n",
12191 drm_get_format_name(mode_cmd->pixel_format));
12192 return -EINVAL;
12193 }
12194 break;
12195 default:
12196 DRM_DEBUG("unsupported pixel format: %s\n",
12197 drm_get_format_name(mode_cmd->pixel_format));
12198 return -EINVAL;
12199 }
12200
12201 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12202 if (mode_cmd->offsets[0] != 0)
12203 return -EINVAL;
12204
12205 aligned_height = intel_align_height(dev, mode_cmd->height,
12206 obj->tiling_mode);
12207 /* FIXME drm helper for size checks (especially planar formats)? */
12208 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12209 return -EINVAL;
12210
12211 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12212 intel_fb->obj = obj;
12213 intel_fb->obj->framebuffer_references++;
12214
12215 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12216 if (ret) {
12217 DRM_ERROR("framebuffer init failed %d\n", ret);
12218 return ret;
12219 }
12220
12221 return 0;
12222 }
12223
12224 static struct drm_framebuffer *
12225 intel_user_framebuffer_create(struct drm_device *dev,
12226 struct drm_file *filp,
12227 struct drm_mode_fb_cmd2 *mode_cmd)
12228 {
12229 struct drm_i915_gem_object *obj;
12230
12231 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12232 mode_cmd->handles[0]));
12233 if (&obj->base == NULL)
12234 return ERR_PTR(-ENOENT);
12235
12236 return intel_framebuffer_create(dev, mode_cmd, obj);
12237 }
12238
12239 #ifndef CONFIG_DRM_I915_FBDEV
12240 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12241 {
12242 }
12243 #endif
12244
12245 static const struct drm_mode_config_funcs intel_mode_funcs = {
12246 .fb_create = intel_user_framebuffer_create,
12247 .output_poll_changed = intel_fbdev_output_poll_changed,
12248 };
12249
12250 /* Set up chip specific display functions */
12251 static void intel_init_display(struct drm_device *dev)
12252 {
12253 struct drm_i915_private *dev_priv = dev->dev_private;
12254
12255 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12256 dev_priv->display.find_dpll = g4x_find_best_dpll;
12257 else if (IS_CHERRYVIEW(dev))
12258 dev_priv->display.find_dpll = chv_find_best_dpll;
12259 else if (IS_VALLEYVIEW(dev))
12260 dev_priv->display.find_dpll = vlv_find_best_dpll;
12261 else if (IS_PINEVIEW(dev))
12262 dev_priv->display.find_dpll = pnv_find_best_dpll;
12263 else
12264 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12265
12266 if (HAS_DDI(dev)) {
12267 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12268 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12269 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
12270 dev_priv->display.crtc_enable = haswell_crtc_enable;
12271 dev_priv->display.crtc_disable = haswell_crtc_disable;
12272 dev_priv->display.off = ironlake_crtc_off;
12273 dev_priv->display.update_primary_plane =
12274 ironlake_update_primary_plane;
12275 } else if (HAS_PCH_SPLIT(dev)) {
12276 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12277 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12278 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
12279 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12280 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12281 dev_priv->display.off = ironlake_crtc_off;
12282 dev_priv->display.update_primary_plane =
12283 ironlake_update_primary_plane;
12284 } else if (IS_VALLEYVIEW(dev)) {
12285 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12286 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12287 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12288 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12289 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12290 dev_priv->display.off = i9xx_crtc_off;
12291 dev_priv->display.update_primary_plane =
12292 i9xx_update_primary_plane;
12293 } else {
12294 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12295 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12296 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12297 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12298 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12299 dev_priv->display.off = i9xx_crtc_off;
12300 dev_priv->display.update_primary_plane =
12301 i9xx_update_primary_plane;
12302 }
12303
12304 /* Returns the core display clock speed */
12305 if (IS_VALLEYVIEW(dev))
12306 dev_priv->display.get_display_clock_speed =
12307 valleyview_get_display_clock_speed;
12308 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12309 dev_priv->display.get_display_clock_speed =
12310 i945_get_display_clock_speed;
12311 else if (IS_I915G(dev))
12312 dev_priv->display.get_display_clock_speed =
12313 i915_get_display_clock_speed;
12314 else if (IS_I945GM(dev) || IS_845G(dev))
12315 dev_priv->display.get_display_clock_speed =
12316 i9xx_misc_get_display_clock_speed;
12317 else if (IS_PINEVIEW(dev))
12318 dev_priv->display.get_display_clock_speed =
12319 pnv_get_display_clock_speed;
12320 else if (IS_I915GM(dev))
12321 dev_priv->display.get_display_clock_speed =
12322 i915gm_get_display_clock_speed;
12323 else if (IS_I865G(dev))
12324 dev_priv->display.get_display_clock_speed =
12325 i865_get_display_clock_speed;
12326 else if (IS_I85X(dev))
12327 dev_priv->display.get_display_clock_speed =
12328 i855_get_display_clock_speed;
12329 else /* 852, 830 */
12330 dev_priv->display.get_display_clock_speed =
12331 i830_get_display_clock_speed;
12332
12333 if (HAS_PCH_SPLIT(dev)) {
12334 if (IS_GEN5(dev)) {
12335 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12336 dev_priv->display.write_eld = ironlake_write_eld;
12337 } else if (IS_GEN6(dev)) {
12338 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12339 dev_priv->display.write_eld = ironlake_write_eld;
12340 dev_priv->display.modeset_global_resources =
12341 snb_modeset_global_resources;
12342 } else if (IS_IVYBRIDGE(dev)) {
12343 /* FIXME: detect B0+ stepping and use auto training */
12344 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12345 dev_priv->display.write_eld = ironlake_write_eld;
12346 dev_priv->display.modeset_global_resources =
12347 ivb_modeset_global_resources;
12348 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
12349 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12350 dev_priv->display.write_eld = haswell_write_eld;
12351 dev_priv->display.modeset_global_resources =
12352 haswell_modeset_global_resources;
12353 }
12354 } else if (IS_G4X(dev)) {
12355 dev_priv->display.write_eld = g4x_write_eld;
12356 } else if (IS_VALLEYVIEW(dev)) {
12357 dev_priv->display.modeset_global_resources =
12358 valleyview_modeset_global_resources;
12359 dev_priv->display.write_eld = ironlake_write_eld;
12360 }
12361
12362 /* Default just returns -ENODEV to indicate unsupported */
12363 dev_priv->display.queue_flip = intel_default_queue_flip;
12364
12365 switch (INTEL_INFO(dev)->gen) {
12366 case 2:
12367 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12368 break;
12369
12370 case 3:
12371 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12372 break;
12373
12374 case 4:
12375 case 5:
12376 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12377 break;
12378
12379 case 6:
12380 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12381 break;
12382 case 7:
12383 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12384 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12385 break;
12386 }
12387
12388 intel_panel_init_backlight_funcs(dev);
12389 }
12390
12391 /*
12392 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12393 * resume, or other times. This quirk makes sure that's the case for
12394 * affected systems.
12395 */
12396 static void quirk_pipea_force(struct drm_device *dev)
12397 {
12398 struct drm_i915_private *dev_priv = dev->dev_private;
12399
12400 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12401 DRM_INFO("applying pipe a force quirk\n");
12402 }
12403
12404 /*
12405 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12406 */
12407 static void quirk_ssc_force_disable(struct drm_device *dev)
12408 {
12409 struct drm_i915_private *dev_priv = dev->dev_private;
12410 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12411 DRM_INFO("applying lvds SSC disable quirk\n");
12412 }
12413
12414 /*
12415 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12416 * brightness value
12417 */
12418 static void quirk_invert_brightness(struct drm_device *dev)
12419 {
12420 struct drm_i915_private *dev_priv = dev->dev_private;
12421 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12422 DRM_INFO("applying inverted panel brightness quirk\n");
12423 }
12424
12425 /* Some VBT's incorrectly indicate no backlight is present */
12426 static void quirk_backlight_present(struct drm_device *dev)
12427 {
12428 struct drm_i915_private *dev_priv = dev->dev_private;
12429 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12430 DRM_INFO("applying backlight present quirk\n");
12431 }
12432
12433 struct intel_quirk {
12434 int device;
12435 int subsystem_vendor;
12436 int subsystem_device;
12437 void (*hook)(struct drm_device *dev);
12438 };
12439
12440 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12441 struct intel_dmi_quirk {
12442 void (*hook)(struct drm_device *dev);
12443 const struct dmi_system_id (*dmi_id_list)[];
12444 };
12445
12446 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12447 {
12448 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12449 return 1;
12450 }
12451
12452 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12453 {
12454 .dmi_id_list = &(const struct dmi_system_id[]) {
12455 {
12456 .callback = intel_dmi_reverse_brightness,
12457 .ident = "NCR Corporation",
12458 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12459 DMI_MATCH(DMI_PRODUCT_NAME, ""),
12460 },
12461 },
12462 { } /* terminating entry */
12463 },
12464 .hook = quirk_invert_brightness,
12465 },
12466 };
12467
12468 static struct intel_quirk intel_quirks[] = {
12469 /* HP Mini needs pipe A force quirk (LP: #322104) */
12470 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12471
12472 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12473 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12474
12475 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12476 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12477
12478 /* Lenovo U160 cannot use SSC on LVDS */
12479 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12480
12481 /* Sony Vaio Y cannot use SSC on LVDS */
12482 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12483
12484 /* Acer Aspire 5734Z must invert backlight brightness */
12485 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12486
12487 /* Acer/eMachines G725 */
12488 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12489
12490 /* Acer/eMachines e725 */
12491 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12492
12493 /* Acer/Packard Bell NCL20 */
12494 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12495
12496 /* Acer Aspire 4736Z */
12497 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12498
12499 /* Acer Aspire 5336 */
12500 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12501
12502 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12503 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
12504
12505 /* Toshiba CB35 Chromebook (Celeron 2955U) */
12506 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
12507
12508 /* HP Chromebook 14 (Celeron 2955U) */
12509 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
12510 };
12511
12512 static void intel_init_quirks(struct drm_device *dev)
12513 {
12514 struct pci_dev *d = dev->pdev;
12515 int i;
12516
12517 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12518 struct intel_quirk *q = &intel_quirks[i];
12519
12520 if (d->device == q->device &&
12521 (d->subsystem_vendor == q->subsystem_vendor ||
12522 q->subsystem_vendor == PCI_ANY_ID) &&
12523 (d->subsystem_device == q->subsystem_device ||
12524 q->subsystem_device == PCI_ANY_ID))
12525 q->hook(dev);
12526 }
12527 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12528 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12529 intel_dmi_quirks[i].hook(dev);
12530 }
12531 }
12532
12533 /* Disable the VGA plane that we never use */
12534 static void i915_disable_vga(struct drm_device *dev)
12535 {
12536 struct drm_i915_private *dev_priv = dev->dev_private;
12537 u8 sr1;
12538 u32 vga_reg = i915_vgacntrl_reg(dev);
12539
12540 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12541 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12542 outb(SR01, VGA_SR_INDEX);
12543 sr1 = inb(VGA_SR_DATA);
12544 outb(sr1 | 1<<5, VGA_SR_DATA);
12545 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12546 udelay(300);
12547
12548 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
12549 POSTING_READ(vga_reg);
12550 }
12551
12552 void intel_modeset_init_hw(struct drm_device *dev)
12553 {
12554 intel_prepare_ddi(dev);
12555
12556 if (IS_VALLEYVIEW(dev))
12557 vlv_update_cdclk(dev);
12558
12559 intel_init_clock_gating(dev);
12560
12561 intel_reset_dpio(dev);
12562
12563 intel_enable_gt_powersave(dev);
12564 }
12565
12566 void intel_modeset_suspend_hw(struct drm_device *dev)
12567 {
12568 intel_suspend_hw(dev);
12569 }
12570
12571 void intel_modeset_init(struct drm_device *dev)
12572 {
12573 struct drm_i915_private *dev_priv = dev->dev_private;
12574 int sprite, ret;
12575 enum pipe pipe;
12576 struct intel_crtc *crtc;
12577
12578 drm_mode_config_init(dev);
12579
12580 dev->mode_config.min_width = 0;
12581 dev->mode_config.min_height = 0;
12582
12583 dev->mode_config.preferred_depth = 24;
12584 dev->mode_config.prefer_shadow = 1;
12585
12586 dev->mode_config.funcs = &intel_mode_funcs;
12587
12588 intel_init_quirks(dev);
12589
12590 intel_init_pm(dev);
12591
12592 if (INTEL_INFO(dev)->num_pipes == 0)
12593 return;
12594
12595 intel_init_display(dev);
12596
12597 if (IS_GEN2(dev)) {
12598 dev->mode_config.max_width = 2048;
12599 dev->mode_config.max_height = 2048;
12600 } else if (IS_GEN3(dev)) {
12601 dev->mode_config.max_width = 4096;
12602 dev->mode_config.max_height = 4096;
12603 } else {
12604 dev->mode_config.max_width = 8192;
12605 dev->mode_config.max_height = 8192;
12606 }
12607
12608 if (IS_GEN2(dev)) {
12609 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12610 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12611 } else {
12612 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
12613 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
12614 }
12615
12616 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
12617
12618 DRM_DEBUG_KMS("%d display pipe%s available.\n",
12619 INTEL_INFO(dev)->num_pipes,
12620 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
12621
12622 for_each_pipe(pipe) {
12623 intel_crtc_init(dev, pipe);
12624 for_each_sprite(pipe, sprite) {
12625 ret = intel_plane_init(dev, pipe, sprite);
12626 if (ret)
12627 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12628 pipe_name(pipe), sprite_name(pipe, sprite), ret);
12629 }
12630 }
12631
12632 intel_init_dpio(dev);
12633 intel_reset_dpio(dev);
12634
12635 intel_shared_dpll_init(dev);
12636
12637 /* Just disable it once at startup */
12638 i915_disable_vga(dev);
12639 intel_setup_outputs(dev);
12640
12641 /* Just in case the BIOS is doing something questionable. */
12642 intel_disable_fbc(dev);
12643
12644 drm_modeset_lock_all(dev);
12645 intel_modeset_setup_hw_state(dev, false);
12646 drm_modeset_unlock_all(dev);
12647
12648 for_each_intel_crtc(dev, crtc) {
12649 if (!crtc->active)
12650 continue;
12651
12652 /*
12653 * Note that reserving the BIOS fb up front prevents us
12654 * from stuffing other stolen allocations like the ring
12655 * on top. This prevents some ugliness at boot time, and
12656 * can even allow for smooth boot transitions if the BIOS
12657 * fb is large enough for the active pipe configuration.
12658 */
12659 if (dev_priv->display.get_plane_config) {
12660 dev_priv->display.get_plane_config(crtc,
12661 &crtc->plane_config);
12662 /*
12663 * If the fb is shared between multiple heads, we'll
12664 * just get the first one.
12665 */
12666 intel_find_plane_obj(crtc, &crtc->plane_config);
12667 }
12668 }
12669 }
12670
12671 static void intel_enable_pipe_a(struct drm_device *dev)
12672 {
12673 struct intel_connector *connector;
12674 struct drm_connector *crt = NULL;
12675 struct intel_load_detect_pipe load_detect_temp;
12676 struct drm_modeset_acquire_ctx ctx;
12677
12678 /* We can't just switch on the pipe A, we need to set things up with a
12679 * proper mode and output configuration. As a gross hack, enable pipe A
12680 * by enabling the load detect pipe once. */
12681 list_for_each_entry(connector,
12682 &dev->mode_config.connector_list,
12683 base.head) {
12684 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
12685 crt = &connector->base;
12686 break;
12687 }
12688 }
12689
12690 if (!crt)
12691 return;
12692
12693 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, &ctx))
12694 intel_release_load_detect_pipe(crt, &load_detect_temp, &ctx);
12695
12696
12697 }
12698
12699 static bool
12700 intel_check_plane_mapping(struct intel_crtc *crtc)
12701 {
12702 struct drm_device *dev = crtc->base.dev;
12703 struct drm_i915_private *dev_priv = dev->dev_private;
12704 u32 reg, val;
12705
12706 if (INTEL_INFO(dev)->num_pipes == 1)
12707 return true;
12708
12709 reg = DSPCNTR(!crtc->plane);
12710 val = I915_READ(reg);
12711
12712 if ((val & DISPLAY_PLANE_ENABLE) &&
12713 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
12714 return false;
12715
12716 return true;
12717 }
12718
12719 static void intel_sanitize_crtc(struct intel_crtc *crtc)
12720 {
12721 struct drm_device *dev = crtc->base.dev;
12722 struct drm_i915_private *dev_priv = dev->dev_private;
12723 u32 reg;
12724
12725 /* Clear any frame start delays used for debugging left by the BIOS */
12726 reg = PIPECONF(crtc->config.cpu_transcoder);
12727 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
12728
12729 /* restore vblank interrupts to correct state */
12730 if (crtc->active)
12731 drm_vblank_on(dev, crtc->pipe);
12732 else
12733 drm_vblank_off(dev, crtc->pipe);
12734
12735 /* We need to sanitize the plane -> pipe mapping first because this will
12736 * disable the crtc (and hence change the state) if it is wrong. Note
12737 * that gen4+ has a fixed plane -> pipe mapping. */
12738 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
12739 struct intel_connector *connector;
12740 bool plane;
12741
12742 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
12743 crtc->base.base.id);
12744
12745 /* Pipe has the wrong plane attached and the plane is active.
12746 * Temporarily change the plane mapping and disable everything
12747 * ... */
12748 plane = crtc->plane;
12749 crtc->plane = !plane;
12750 crtc->primary_enabled = true;
12751 dev_priv->display.crtc_disable(&crtc->base);
12752 crtc->plane = plane;
12753
12754 /* ... and break all links. */
12755 list_for_each_entry(connector, &dev->mode_config.connector_list,
12756 base.head) {
12757 if (connector->encoder->base.crtc != &crtc->base)
12758 continue;
12759
12760 connector->base.dpms = DRM_MODE_DPMS_OFF;
12761 connector->base.encoder = NULL;
12762 }
12763 /* multiple connectors may have the same encoder:
12764 * handle them and break crtc link separately */
12765 list_for_each_entry(connector, &dev->mode_config.connector_list,
12766 base.head)
12767 if (connector->encoder->base.crtc == &crtc->base) {
12768 connector->encoder->base.crtc = NULL;
12769 connector->encoder->connectors_active = false;
12770 }
12771
12772 WARN_ON(crtc->active);
12773 crtc->base.enabled = false;
12774 }
12775
12776 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
12777 crtc->pipe == PIPE_A && !crtc->active) {
12778 /* BIOS forgot to enable pipe A, this mostly happens after
12779 * resume. Force-enable the pipe to fix this, the update_dpms
12780 * call below we restore the pipe to the right state, but leave
12781 * the required bits on. */
12782 intel_enable_pipe_a(dev);
12783 }
12784
12785 /* Adjust the state of the output pipe according to whether we
12786 * have active connectors/encoders. */
12787 intel_crtc_update_dpms(&crtc->base);
12788
12789 if (crtc->active != crtc->base.enabled) {
12790 struct intel_encoder *encoder;
12791
12792 /* This can happen either due to bugs in the get_hw_state
12793 * functions or because the pipe is force-enabled due to the
12794 * pipe A quirk. */
12795 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
12796 crtc->base.base.id,
12797 crtc->base.enabled ? "enabled" : "disabled",
12798 crtc->active ? "enabled" : "disabled");
12799
12800 crtc->base.enabled = crtc->active;
12801
12802 /* Because we only establish the connector -> encoder ->
12803 * crtc links if something is active, this means the
12804 * crtc is now deactivated. Break the links. connector
12805 * -> encoder links are only establish when things are
12806 * actually up, hence no need to break them. */
12807 WARN_ON(crtc->active);
12808
12809 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
12810 WARN_ON(encoder->connectors_active);
12811 encoder->base.crtc = NULL;
12812 }
12813 }
12814
12815 if (crtc->active || IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen < 5) {
12816 /*
12817 * We start out with underrun reporting disabled to avoid races.
12818 * For correct bookkeeping mark this on active crtcs.
12819 *
12820 * Also on gmch platforms we dont have any hardware bits to
12821 * disable the underrun reporting. Which means we need to start
12822 * out with underrun reporting disabled also on inactive pipes,
12823 * since otherwise we'll complain about the garbage we read when
12824 * e.g. coming up after runtime pm.
12825 *
12826 * No protection against concurrent access is required - at
12827 * worst a fifo underrun happens which also sets this to false.
12828 */
12829 crtc->cpu_fifo_underrun_disabled = true;
12830 crtc->pch_fifo_underrun_disabled = true;
12831
12832 update_scanline_offset(crtc);
12833 }
12834 }
12835
12836 static void intel_sanitize_encoder(struct intel_encoder *encoder)
12837 {
12838 struct intel_connector *connector;
12839 struct drm_device *dev = encoder->base.dev;
12840
12841 /* We need to check both for a crtc link (meaning that the
12842 * encoder is active and trying to read from a pipe) and the
12843 * pipe itself being active. */
12844 bool has_active_crtc = encoder->base.crtc &&
12845 to_intel_crtc(encoder->base.crtc)->active;
12846
12847 if (encoder->connectors_active && !has_active_crtc) {
12848 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
12849 encoder->base.base.id,
12850 encoder->base.name);
12851
12852 /* Connector is active, but has no active pipe. This is
12853 * fallout from our resume register restoring. Disable
12854 * the encoder manually again. */
12855 if (encoder->base.crtc) {
12856 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
12857 encoder->base.base.id,
12858 encoder->base.name);
12859 encoder->disable(encoder);
12860 if (encoder->post_disable)
12861 encoder->post_disable(encoder);
12862 }
12863 encoder->base.crtc = NULL;
12864 encoder->connectors_active = false;
12865
12866 /* Inconsistent output/port/pipe state happens presumably due to
12867 * a bug in one of the get_hw_state functions. Or someplace else
12868 * in our code, like the register restore mess on resume. Clamp
12869 * things to off as a safer default. */
12870 list_for_each_entry(connector,
12871 &dev->mode_config.connector_list,
12872 base.head) {
12873 if (connector->encoder != encoder)
12874 continue;
12875 connector->base.dpms = DRM_MODE_DPMS_OFF;
12876 connector->base.encoder = NULL;
12877 }
12878 }
12879 /* Enabled encoders without active connectors will be fixed in
12880 * the crtc fixup. */
12881 }
12882
12883 void i915_redisable_vga_power_on(struct drm_device *dev)
12884 {
12885 struct drm_i915_private *dev_priv = dev->dev_private;
12886 u32 vga_reg = i915_vgacntrl_reg(dev);
12887
12888 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
12889 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
12890 i915_disable_vga(dev);
12891 }
12892 }
12893
12894 void i915_redisable_vga(struct drm_device *dev)
12895 {
12896 struct drm_i915_private *dev_priv = dev->dev_private;
12897
12898 /* This function can be called both from intel_modeset_setup_hw_state or
12899 * at a very early point in our resume sequence, where the power well
12900 * structures are not yet restored. Since this function is at a very
12901 * paranoid "someone might have enabled VGA while we were not looking"
12902 * level, just check if the power well is enabled instead of trying to
12903 * follow the "don't touch the power well if we don't need it" policy
12904 * the rest of the driver uses. */
12905 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
12906 return;
12907
12908 i915_redisable_vga_power_on(dev);
12909 }
12910
12911 static bool primary_get_hw_state(struct intel_crtc *crtc)
12912 {
12913 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
12914
12915 if (!crtc->active)
12916 return false;
12917
12918 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
12919 }
12920
12921 static void intel_modeset_readout_hw_state(struct drm_device *dev)
12922 {
12923 struct drm_i915_private *dev_priv = dev->dev_private;
12924 enum pipe pipe;
12925 struct intel_crtc *crtc;
12926 struct intel_encoder *encoder;
12927 struct intel_connector *connector;
12928 int i;
12929
12930 for_each_intel_crtc(dev, crtc) {
12931 memset(&crtc->config, 0, sizeof(crtc->config));
12932
12933 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
12934
12935 crtc->active = dev_priv->display.get_pipe_config(crtc,
12936 &crtc->config);
12937
12938 crtc->base.enabled = crtc->active;
12939 crtc->primary_enabled = primary_get_hw_state(crtc);
12940
12941 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
12942 crtc->base.base.id,
12943 crtc->active ? "enabled" : "disabled");
12944 }
12945
12946 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12947 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12948
12949 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
12950 pll->active = 0;
12951 for_each_intel_crtc(dev, crtc) {
12952 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12953 pll->active++;
12954 }
12955 pll->refcount = pll->active;
12956
12957 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
12958 pll->name, pll->refcount, pll->on);
12959
12960 if (pll->refcount)
12961 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
12962 }
12963
12964 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
12965 base.head) {
12966 pipe = 0;
12967
12968 if (encoder->get_hw_state(encoder, &pipe)) {
12969 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
12970 encoder->base.crtc = &crtc->base;
12971 encoder->get_config(encoder, &crtc->config);
12972 } else {
12973 encoder->base.crtc = NULL;
12974 }
12975
12976 encoder->connectors_active = false;
12977 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
12978 encoder->base.base.id,
12979 encoder->base.name,
12980 encoder->base.crtc ? "enabled" : "disabled",
12981 pipe_name(pipe));
12982 }
12983
12984 list_for_each_entry(connector, &dev->mode_config.connector_list,
12985 base.head) {
12986 if (connector->get_hw_state(connector)) {
12987 connector->base.dpms = DRM_MODE_DPMS_ON;
12988 connector->encoder->connectors_active = true;
12989 connector->base.encoder = &connector->encoder->base;
12990 } else {
12991 connector->base.dpms = DRM_MODE_DPMS_OFF;
12992 connector->base.encoder = NULL;
12993 }
12994 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
12995 connector->base.base.id,
12996 connector->base.name,
12997 connector->base.encoder ? "enabled" : "disabled");
12998 }
12999 }
13000
13001 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13002 * and i915 state tracking structures. */
13003 void intel_modeset_setup_hw_state(struct drm_device *dev,
13004 bool force_restore)
13005 {
13006 struct drm_i915_private *dev_priv = dev->dev_private;
13007 enum pipe pipe;
13008 struct intel_crtc *crtc;
13009 struct intel_encoder *encoder;
13010 int i;
13011
13012 intel_modeset_readout_hw_state(dev);
13013
13014 /*
13015 * Now that we have the config, copy it to each CRTC struct
13016 * Note that this could go away if we move to using crtc_config
13017 * checking everywhere.
13018 */
13019 for_each_intel_crtc(dev, crtc) {
13020 if (crtc->active && i915.fastboot) {
13021 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
13022 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13023 crtc->base.base.id);
13024 drm_mode_debug_printmodeline(&crtc->base.mode);
13025 }
13026 }
13027
13028 /* HW state is read out, now we need to sanitize this mess. */
13029 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
13030 base.head) {
13031 intel_sanitize_encoder(encoder);
13032 }
13033
13034 for_each_pipe(pipe) {
13035 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13036 intel_sanitize_crtc(crtc);
13037 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
13038 }
13039
13040 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13041 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13042
13043 if (!pll->on || pll->active)
13044 continue;
13045
13046 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13047
13048 pll->disable(dev_priv, pll);
13049 pll->on = false;
13050 }
13051
13052 if (HAS_PCH_SPLIT(dev))
13053 ilk_wm_get_hw_state(dev);
13054
13055 if (force_restore) {
13056 i915_redisable_vga(dev);
13057
13058 /*
13059 * We need to use raw interfaces for restoring state to avoid
13060 * checking (bogus) intermediate states.
13061 */
13062 for_each_pipe(pipe) {
13063 struct drm_crtc *crtc =
13064 dev_priv->pipe_to_crtc_mapping[pipe];
13065
13066 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13067 crtc->primary->fb);
13068 }
13069 } else {
13070 intel_modeset_update_staged_output_state(dev);
13071 }
13072
13073 intel_modeset_check_state(dev);
13074 }
13075
13076 void intel_modeset_gem_init(struct drm_device *dev)
13077 {
13078 struct drm_crtc *c;
13079 struct drm_i915_gem_object *obj;
13080
13081 mutex_lock(&dev->struct_mutex);
13082 intel_init_gt_powersave(dev);
13083 mutex_unlock(&dev->struct_mutex);
13084
13085 intel_modeset_init_hw(dev);
13086
13087 intel_setup_overlay(dev);
13088
13089 /*
13090 * Make sure any fbs we allocated at startup are properly
13091 * pinned & fenced. When we do the allocation it's too early
13092 * for this.
13093 */
13094 mutex_lock(&dev->struct_mutex);
13095 for_each_crtc(dev, c) {
13096 obj = intel_fb_obj(c->primary->fb);
13097 if (obj == NULL)
13098 continue;
13099
13100 if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) {
13101 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13102 to_intel_crtc(c)->pipe);
13103 drm_framebuffer_unreference(c->primary->fb);
13104 c->primary->fb = NULL;
13105 }
13106 }
13107 mutex_unlock(&dev->struct_mutex);
13108 }
13109
13110 void intel_connector_unregister(struct intel_connector *intel_connector)
13111 {
13112 struct drm_connector *connector = &intel_connector->base;
13113
13114 intel_panel_destroy_backlight(connector);
13115 drm_connector_unregister(connector);
13116 }
13117
13118 void intel_modeset_cleanup(struct drm_device *dev)
13119 {
13120 struct drm_i915_private *dev_priv = dev->dev_private;
13121 struct drm_connector *connector;
13122
13123 /*
13124 * Interrupts and polling as the first thing to avoid creating havoc.
13125 * Too much stuff here (turning of rps, connectors, ...) would
13126 * experience fancy races otherwise.
13127 */
13128 drm_irq_uninstall(dev);
13129 cancel_work_sync(&dev_priv->hotplug_work);
13130 dev_priv->pm._irqs_disabled = true;
13131
13132 /*
13133 * Due to the hpd irq storm handling the hotplug work can re-arm the
13134 * poll handlers. Hence disable polling after hpd handling is shut down.
13135 */
13136 drm_kms_helper_poll_fini(dev);
13137
13138 mutex_lock(&dev->struct_mutex);
13139
13140 intel_unregister_dsm_handler();
13141
13142 intel_disable_fbc(dev);
13143
13144 intel_disable_gt_powersave(dev);
13145
13146 ironlake_teardown_rc6(dev);
13147
13148 mutex_unlock(&dev->struct_mutex);
13149
13150 /* flush any delayed tasks or pending work */
13151 flush_scheduled_work();
13152
13153 /* destroy the backlight and sysfs files before encoders/connectors */
13154 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13155 struct intel_connector *intel_connector;
13156
13157 intel_connector = to_intel_connector(connector);
13158 intel_connector->unregister(intel_connector);
13159 }
13160
13161 drm_mode_config_cleanup(dev);
13162
13163 intel_cleanup_overlay(dev);
13164
13165 mutex_lock(&dev->struct_mutex);
13166 intel_cleanup_gt_powersave(dev);
13167 mutex_unlock(&dev->struct_mutex);
13168 }
13169
13170 /*
13171 * Return which encoder is currently attached for connector.
13172 */
13173 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13174 {
13175 return &intel_attached_encoder(connector)->base;
13176 }
13177
13178 void intel_connector_attach_encoder(struct intel_connector *connector,
13179 struct intel_encoder *encoder)
13180 {
13181 connector->encoder = encoder;
13182 drm_mode_connector_attach_encoder(&connector->base,
13183 &encoder->base);
13184 }
13185
13186 /*
13187 * set vga decode state - true == enable VGA decode
13188 */
13189 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13190 {
13191 struct drm_i915_private *dev_priv = dev->dev_private;
13192 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13193 u16 gmch_ctrl;
13194
13195 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13196 DRM_ERROR("failed to read control word\n");
13197 return -EIO;
13198 }
13199
13200 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13201 return 0;
13202
13203 if (state)
13204 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13205 else
13206 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13207
13208 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13209 DRM_ERROR("failed to write control word\n");
13210 return -EIO;
13211 }
13212
13213 return 0;
13214 }
13215
13216 struct intel_display_error_state {
13217
13218 u32 power_well_driver;
13219
13220 int num_transcoders;
13221
13222 struct intel_cursor_error_state {
13223 u32 control;
13224 u32 position;
13225 u32 base;
13226 u32 size;
13227 } cursor[I915_MAX_PIPES];
13228
13229 struct intel_pipe_error_state {
13230 bool power_domain_on;
13231 u32 source;
13232 u32 stat;
13233 } pipe[I915_MAX_PIPES];
13234
13235 struct intel_plane_error_state {
13236 u32 control;
13237 u32 stride;
13238 u32 size;
13239 u32 pos;
13240 u32 addr;
13241 u32 surface;
13242 u32 tile_offset;
13243 } plane[I915_MAX_PIPES];
13244
13245 struct intel_transcoder_error_state {
13246 bool power_domain_on;
13247 enum transcoder cpu_transcoder;
13248
13249 u32 conf;
13250
13251 u32 htotal;
13252 u32 hblank;
13253 u32 hsync;
13254 u32 vtotal;
13255 u32 vblank;
13256 u32 vsync;
13257 } transcoder[4];
13258 };
13259
13260 struct intel_display_error_state *
13261 intel_display_capture_error_state(struct drm_device *dev)
13262 {
13263 struct drm_i915_private *dev_priv = dev->dev_private;
13264 struct intel_display_error_state *error;
13265 int transcoders[] = {
13266 TRANSCODER_A,
13267 TRANSCODER_B,
13268 TRANSCODER_C,
13269 TRANSCODER_EDP,
13270 };
13271 int i;
13272
13273 if (INTEL_INFO(dev)->num_pipes == 0)
13274 return NULL;
13275
13276 error = kzalloc(sizeof(*error), GFP_ATOMIC);
13277 if (error == NULL)
13278 return NULL;
13279
13280 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13281 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13282
13283 for_each_pipe(i) {
13284 error->pipe[i].power_domain_on =
13285 intel_display_power_enabled_unlocked(dev_priv,
13286 POWER_DOMAIN_PIPE(i));
13287 if (!error->pipe[i].power_domain_on)
13288 continue;
13289
13290 error->cursor[i].control = I915_READ(CURCNTR(i));
13291 error->cursor[i].position = I915_READ(CURPOS(i));
13292 error->cursor[i].base = I915_READ(CURBASE(i));
13293
13294 error->plane[i].control = I915_READ(DSPCNTR(i));
13295 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13296 if (INTEL_INFO(dev)->gen <= 3) {
13297 error->plane[i].size = I915_READ(DSPSIZE(i));
13298 error->plane[i].pos = I915_READ(DSPPOS(i));
13299 }
13300 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13301 error->plane[i].addr = I915_READ(DSPADDR(i));
13302 if (INTEL_INFO(dev)->gen >= 4) {
13303 error->plane[i].surface = I915_READ(DSPSURF(i));
13304 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13305 }
13306
13307 error->pipe[i].source = I915_READ(PIPESRC(i));
13308
13309 if (HAS_GMCH_DISPLAY(dev))
13310 error->pipe[i].stat = I915_READ(PIPESTAT(i));
13311 }
13312
13313 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13314 if (HAS_DDI(dev_priv->dev))
13315 error->num_transcoders++; /* Account for eDP. */
13316
13317 for (i = 0; i < error->num_transcoders; i++) {
13318 enum transcoder cpu_transcoder = transcoders[i];
13319
13320 error->transcoder[i].power_domain_on =
13321 intel_display_power_enabled_unlocked(dev_priv,
13322 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13323 if (!error->transcoder[i].power_domain_on)
13324 continue;
13325
13326 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13327
13328 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13329 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13330 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13331 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13332 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13333 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13334 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13335 }
13336
13337 return error;
13338 }
13339
13340 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13341
13342 void
13343 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13344 struct drm_device *dev,
13345 struct intel_display_error_state *error)
13346 {
13347 int i;
13348
13349 if (!error)
13350 return;
13351
13352 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13353 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13354 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13355 error->power_well_driver);
13356 for_each_pipe(i) {
13357 err_printf(m, "Pipe [%d]:\n", i);
13358 err_printf(m, " Power: %s\n",
13359 error->pipe[i].power_domain_on ? "on" : "off");
13360 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
13361 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
13362
13363 err_printf(m, "Plane [%d]:\n", i);
13364 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
13365 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
13366 if (INTEL_INFO(dev)->gen <= 3) {
13367 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
13368 err_printf(m, " POS: %08x\n", error->plane[i].pos);
13369 }
13370 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13371 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
13372 if (INTEL_INFO(dev)->gen >= 4) {
13373 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
13374 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
13375 }
13376
13377 err_printf(m, "Cursor [%d]:\n", i);
13378 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
13379 err_printf(m, " POS: %08x\n", error->cursor[i].position);
13380 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
13381 }
13382
13383 for (i = 0; i < error->num_transcoders; i++) {
13384 err_printf(m, "CPU transcoder: %c\n",
13385 transcoder_name(error->transcoder[i].cpu_transcoder));
13386 err_printf(m, " Power: %s\n",
13387 error->transcoder[i].power_domain_on ? "on" : "off");
13388 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
13389 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
13390 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
13391 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
13392 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
13393 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
13394 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
13395 }
13396 }
Linux kernel - Deliverables
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