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drm/i915: simplify intel_encoder_commit
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include "drmP.h"
36 #include "intel_drv.h"
37 #include "i915_drm.h"
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include "drm_dp_helper.h"
41 #include "drm_crtc_helper.h"
42 #include <linux/dma_remapping.h>
43
44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
47 static void intel_increase_pllclock(struct drm_crtc *crtc);
48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
49
50 typedef struct {
51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
60 } intel_clock_t;
61
62 typedef struct {
63 int min, max;
64 } intel_range_t;
65
66 typedef struct {
67 int dot_limit;
68 int p2_slow, p2_fast;
69 } intel_p2_t;
70
71 #define INTEL_P2_NUM 2
72 typedef struct intel_limit intel_limit_t;
73 struct intel_limit {
74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
77 int, int, intel_clock_t *, intel_clock_t *);
78 };
79
80 /* FDI */
81 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
83 static bool
84 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
85 int target, int refclk, intel_clock_t *match_clock,
86 intel_clock_t *best_clock);
87 static bool
88 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
89 int target, int refclk, intel_clock_t *match_clock,
90 intel_clock_t *best_clock);
91
92 static bool
93 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
94 int target, int refclk, intel_clock_t *match_clock,
95 intel_clock_t *best_clock);
96 static bool
97 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
98 int target, int refclk, intel_clock_t *match_clock,
99 intel_clock_t *best_clock);
100
101 static inline u32 /* units of 100MHz */
102 intel_fdi_link_freq(struct drm_device *dev)
103 {
104 if (IS_GEN5(dev)) {
105 struct drm_i915_private *dev_priv = dev->dev_private;
106 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
107 } else
108 return 27;
109 }
110
111 static const intel_limit_t intel_limits_i8xx_dvo = {
112 .dot = { .min = 25000, .max = 350000 },
113 .vco = { .min = 930000, .max = 1400000 },
114 .n = { .min = 3, .max = 16 },
115 .m = { .min = 96, .max = 140 },
116 .m1 = { .min = 18, .max = 26 },
117 .m2 = { .min = 6, .max = 16 },
118 .p = { .min = 4, .max = 128 },
119 .p1 = { .min = 2, .max = 33 },
120 .p2 = { .dot_limit = 165000,
121 .p2_slow = 4, .p2_fast = 2 },
122 .find_pll = intel_find_best_PLL,
123 };
124
125 static const intel_limit_t intel_limits_i8xx_lvds = {
126 .dot = { .min = 25000, .max = 350000 },
127 .vco = { .min = 930000, .max = 1400000 },
128 .n = { .min = 3, .max = 16 },
129 .m = { .min = 96, .max = 140 },
130 .m1 = { .min = 18, .max = 26 },
131 .m2 = { .min = 6, .max = 16 },
132 .p = { .min = 4, .max = 128 },
133 .p1 = { .min = 1, .max = 6 },
134 .p2 = { .dot_limit = 165000,
135 .p2_slow = 14, .p2_fast = 7 },
136 .find_pll = intel_find_best_PLL,
137 };
138
139 static const intel_limit_t intel_limits_i9xx_sdvo = {
140 .dot = { .min = 20000, .max = 400000 },
141 .vco = { .min = 1400000, .max = 2800000 },
142 .n = { .min = 1, .max = 6 },
143 .m = { .min = 70, .max = 120 },
144 .m1 = { .min = 10, .max = 22 },
145 .m2 = { .min = 5, .max = 9 },
146 .p = { .min = 5, .max = 80 },
147 .p1 = { .min = 1, .max = 8 },
148 .p2 = { .dot_limit = 200000,
149 .p2_slow = 10, .p2_fast = 5 },
150 .find_pll = intel_find_best_PLL,
151 };
152
153 static const intel_limit_t intel_limits_i9xx_lvds = {
154 .dot = { .min = 20000, .max = 400000 },
155 .vco = { .min = 1400000, .max = 2800000 },
156 .n = { .min = 1, .max = 6 },
157 .m = { .min = 70, .max = 120 },
158 .m1 = { .min = 10, .max = 22 },
159 .m2 = { .min = 5, .max = 9 },
160 .p = { .min = 7, .max = 98 },
161 .p1 = { .min = 1, .max = 8 },
162 .p2 = { .dot_limit = 112000,
163 .p2_slow = 14, .p2_fast = 7 },
164 .find_pll = intel_find_best_PLL,
165 };
166
167
168 static const intel_limit_t intel_limits_g4x_sdvo = {
169 .dot = { .min = 25000, .max = 270000 },
170 .vco = { .min = 1750000, .max = 3500000},
171 .n = { .min = 1, .max = 4 },
172 .m = { .min = 104, .max = 138 },
173 .m1 = { .min = 17, .max = 23 },
174 .m2 = { .min = 5, .max = 11 },
175 .p = { .min = 10, .max = 30 },
176 .p1 = { .min = 1, .max = 3},
177 .p2 = { .dot_limit = 270000,
178 .p2_slow = 10,
179 .p2_fast = 10
180 },
181 .find_pll = intel_g4x_find_best_PLL,
182 };
183
184 static const intel_limit_t intel_limits_g4x_hdmi = {
185 .dot = { .min = 22000, .max = 400000 },
186 .vco = { .min = 1750000, .max = 3500000},
187 .n = { .min = 1, .max = 4 },
188 .m = { .min = 104, .max = 138 },
189 .m1 = { .min = 16, .max = 23 },
190 .m2 = { .min = 5, .max = 11 },
191 .p = { .min = 5, .max = 80 },
192 .p1 = { .min = 1, .max = 8},
193 .p2 = { .dot_limit = 165000,
194 .p2_slow = 10, .p2_fast = 5 },
195 .find_pll = intel_g4x_find_best_PLL,
196 };
197
198 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
199 .dot = { .min = 20000, .max = 115000 },
200 .vco = { .min = 1750000, .max = 3500000 },
201 .n = { .min = 1, .max = 3 },
202 .m = { .min = 104, .max = 138 },
203 .m1 = { .min = 17, .max = 23 },
204 .m2 = { .min = 5, .max = 11 },
205 .p = { .min = 28, .max = 112 },
206 .p1 = { .min = 2, .max = 8 },
207 .p2 = { .dot_limit = 0,
208 .p2_slow = 14, .p2_fast = 14
209 },
210 .find_pll = intel_g4x_find_best_PLL,
211 };
212
213 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
214 .dot = { .min = 80000, .max = 224000 },
215 .vco = { .min = 1750000, .max = 3500000 },
216 .n = { .min = 1, .max = 3 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 17, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 14, .max = 42 },
221 .p1 = { .min = 2, .max = 6 },
222 .p2 = { .dot_limit = 0,
223 .p2_slow = 7, .p2_fast = 7
224 },
225 .find_pll = intel_g4x_find_best_PLL,
226 };
227
228 static const intel_limit_t intel_limits_g4x_display_port = {
229 .dot = { .min = 161670, .max = 227000 },
230 .vco = { .min = 1750000, .max = 3500000},
231 .n = { .min = 1, .max = 2 },
232 .m = { .min = 97, .max = 108 },
233 .m1 = { .min = 0x10, .max = 0x12 },
234 .m2 = { .min = 0x05, .max = 0x06 },
235 .p = { .min = 10, .max = 20 },
236 .p1 = { .min = 1, .max = 2},
237 .p2 = { .dot_limit = 0,
238 .p2_slow = 10, .p2_fast = 10 },
239 .find_pll = intel_find_pll_g4x_dp,
240 };
241
242 static const intel_limit_t intel_limits_pineview_sdvo = {
243 .dot = { .min = 20000, .max = 400000},
244 .vco = { .min = 1700000, .max = 3500000 },
245 /* Pineview's Ncounter is a ring counter */
246 .n = { .min = 3, .max = 6 },
247 .m = { .min = 2, .max = 256 },
248 /* Pineview only has one combined m divider, which we treat as m2. */
249 .m1 = { .min = 0, .max = 0 },
250 .m2 = { .min = 0, .max = 254 },
251 .p = { .min = 5, .max = 80 },
252 .p1 = { .min = 1, .max = 8 },
253 .p2 = { .dot_limit = 200000,
254 .p2_slow = 10, .p2_fast = 5 },
255 .find_pll = intel_find_best_PLL,
256 };
257
258 static const intel_limit_t intel_limits_pineview_lvds = {
259 .dot = { .min = 20000, .max = 400000 },
260 .vco = { .min = 1700000, .max = 3500000 },
261 .n = { .min = 3, .max = 6 },
262 .m = { .min = 2, .max = 256 },
263 .m1 = { .min = 0, .max = 0 },
264 .m2 = { .min = 0, .max = 254 },
265 .p = { .min = 7, .max = 112 },
266 .p1 = { .min = 1, .max = 8 },
267 .p2 = { .dot_limit = 112000,
268 .p2_slow = 14, .p2_fast = 14 },
269 .find_pll = intel_find_best_PLL,
270 };
271
272 /* Ironlake / Sandybridge
273 *
274 * We calculate clock using (register_value + 2) for N/M1/M2, so here
275 * the range value for them is (actual_value - 2).
276 */
277 static const intel_limit_t intel_limits_ironlake_dac = {
278 .dot = { .min = 25000, .max = 350000 },
279 .vco = { .min = 1760000, .max = 3510000 },
280 .n = { .min = 1, .max = 5 },
281 .m = { .min = 79, .max = 127 },
282 .m1 = { .min = 12, .max = 22 },
283 .m2 = { .min = 5, .max = 9 },
284 .p = { .min = 5, .max = 80 },
285 .p1 = { .min = 1, .max = 8 },
286 .p2 = { .dot_limit = 225000,
287 .p2_slow = 10, .p2_fast = 5 },
288 .find_pll = intel_g4x_find_best_PLL,
289 };
290
291 static const intel_limit_t intel_limits_ironlake_single_lvds = {
292 .dot = { .min = 25000, .max = 350000 },
293 .vco = { .min = 1760000, .max = 3510000 },
294 .n = { .min = 1, .max = 3 },
295 .m = { .min = 79, .max = 118 },
296 .m1 = { .min = 12, .max = 22 },
297 .m2 = { .min = 5, .max = 9 },
298 .p = { .min = 28, .max = 112 },
299 .p1 = { .min = 2, .max = 8 },
300 .p2 = { .dot_limit = 225000,
301 .p2_slow = 14, .p2_fast = 14 },
302 .find_pll = intel_g4x_find_best_PLL,
303 };
304
305 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
306 .dot = { .min = 25000, .max = 350000 },
307 .vco = { .min = 1760000, .max = 3510000 },
308 .n = { .min = 1, .max = 3 },
309 .m = { .min = 79, .max = 127 },
310 .m1 = { .min = 12, .max = 22 },
311 .m2 = { .min = 5, .max = 9 },
312 .p = { .min = 14, .max = 56 },
313 .p1 = { .min = 2, .max = 8 },
314 .p2 = { .dot_limit = 225000,
315 .p2_slow = 7, .p2_fast = 7 },
316 .find_pll = intel_g4x_find_best_PLL,
317 };
318
319 /* LVDS 100mhz refclk limits. */
320 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 2 },
324 .m = { .min = 79, .max = 126 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 28, .max = 112 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 14, .p2_fast = 14 },
331 .find_pll = intel_g4x_find_best_PLL,
332 };
333
334 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
335 .dot = { .min = 25000, .max = 350000 },
336 .vco = { .min = 1760000, .max = 3510000 },
337 .n = { .min = 1, .max = 3 },
338 .m = { .min = 79, .max = 126 },
339 .m1 = { .min = 12, .max = 22 },
340 .m2 = { .min = 5, .max = 9 },
341 .p = { .min = 14, .max = 42 },
342 .p1 = { .min = 2, .max = 6 },
343 .p2 = { .dot_limit = 225000,
344 .p2_slow = 7, .p2_fast = 7 },
345 .find_pll = intel_g4x_find_best_PLL,
346 };
347
348 static const intel_limit_t intel_limits_ironlake_display_port = {
349 .dot = { .min = 25000, .max = 350000 },
350 .vco = { .min = 1760000, .max = 3510000},
351 .n = { .min = 1, .max = 2 },
352 .m = { .min = 81, .max = 90 },
353 .m1 = { .min = 12, .max = 22 },
354 .m2 = { .min = 5, .max = 9 },
355 .p = { .min = 10, .max = 20 },
356 .p1 = { .min = 1, .max = 2},
357 .p2 = { .dot_limit = 0,
358 .p2_slow = 10, .p2_fast = 10 },
359 .find_pll = intel_find_pll_ironlake_dp,
360 };
361
362 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
363 {
364 unsigned long flags;
365 u32 val = 0;
366
367 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
368 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
369 DRM_ERROR("DPIO idle wait timed out\n");
370 goto out_unlock;
371 }
372
373 I915_WRITE(DPIO_REG, reg);
374 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
375 DPIO_BYTE);
376 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
377 DRM_ERROR("DPIO read wait timed out\n");
378 goto out_unlock;
379 }
380 val = I915_READ(DPIO_DATA);
381
382 out_unlock:
383 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
384 return val;
385 }
386
387 static void vlv_init_dpio(struct drm_device *dev)
388 {
389 struct drm_i915_private *dev_priv = dev->dev_private;
390
391 /* Reset the DPIO config */
392 I915_WRITE(DPIO_CTL, 0);
393 POSTING_READ(DPIO_CTL);
394 I915_WRITE(DPIO_CTL, 1);
395 POSTING_READ(DPIO_CTL);
396 }
397
398 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
399 {
400 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
401 return 1;
402 }
403
404 static const struct dmi_system_id intel_dual_link_lvds[] = {
405 {
406 .callback = intel_dual_link_lvds_callback,
407 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
408 .matches = {
409 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
410 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
411 },
412 },
413 { } /* terminating entry */
414 };
415
416 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
417 unsigned int reg)
418 {
419 unsigned int val;
420
421 /* use the module option value if specified */
422 if (i915_lvds_channel_mode > 0)
423 return i915_lvds_channel_mode == 2;
424
425 if (dmi_check_system(intel_dual_link_lvds))
426 return true;
427
428 if (dev_priv->lvds_val)
429 val = dev_priv->lvds_val;
430 else {
431 /* BIOS should set the proper LVDS register value at boot, but
432 * in reality, it doesn't set the value when the lid is closed;
433 * we need to check "the value to be set" in VBT when LVDS
434 * register is uninitialized.
435 */
436 val = I915_READ(reg);
437 if (!(val & ~LVDS_DETECTED))
438 val = dev_priv->bios_lvds_val;
439 dev_priv->lvds_val = val;
440 }
441 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
442 }
443
444 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
445 int refclk)
446 {
447 struct drm_device *dev = crtc->dev;
448 struct drm_i915_private *dev_priv = dev->dev_private;
449 const intel_limit_t *limit;
450
451 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
452 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
453 /* LVDS dual channel */
454 if (refclk == 100000)
455 limit = &intel_limits_ironlake_dual_lvds_100m;
456 else
457 limit = &intel_limits_ironlake_dual_lvds;
458 } else {
459 if (refclk == 100000)
460 limit = &intel_limits_ironlake_single_lvds_100m;
461 else
462 limit = &intel_limits_ironlake_single_lvds;
463 }
464 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
465 HAS_eDP)
466 limit = &intel_limits_ironlake_display_port;
467 else
468 limit = &intel_limits_ironlake_dac;
469
470 return limit;
471 }
472
473 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
474 {
475 struct drm_device *dev = crtc->dev;
476 struct drm_i915_private *dev_priv = dev->dev_private;
477 const intel_limit_t *limit;
478
479 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
480 if (is_dual_link_lvds(dev_priv, LVDS))
481 /* LVDS with dual channel */
482 limit = &intel_limits_g4x_dual_channel_lvds;
483 else
484 /* LVDS with dual channel */
485 limit = &intel_limits_g4x_single_channel_lvds;
486 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
487 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
488 limit = &intel_limits_g4x_hdmi;
489 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
490 limit = &intel_limits_g4x_sdvo;
491 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
492 limit = &intel_limits_g4x_display_port;
493 } else /* The option is for other outputs */
494 limit = &intel_limits_i9xx_sdvo;
495
496 return limit;
497 }
498
499 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
500 {
501 struct drm_device *dev = crtc->dev;
502 const intel_limit_t *limit;
503
504 if (HAS_PCH_SPLIT(dev))
505 limit = intel_ironlake_limit(crtc, refclk);
506 else if (IS_G4X(dev)) {
507 limit = intel_g4x_limit(crtc);
508 } else if (IS_PINEVIEW(dev)) {
509 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
510 limit = &intel_limits_pineview_lvds;
511 else
512 limit = &intel_limits_pineview_sdvo;
513 } else if (!IS_GEN2(dev)) {
514 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
515 limit = &intel_limits_i9xx_lvds;
516 else
517 limit = &intel_limits_i9xx_sdvo;
518 } else {
519 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
520 limit = &intel_limits_i8xx_lvds;
521 else
522 limit = &intel_limits_i8xx_dvo;
523 }
524 return limit;
525 }
526
527 /* m1 is reserved as 0 in Pineview, n is a ring counter */
528 static void pineview_clock(int refclk, intel_clock_t *clock)
529 {
530 clock->m = clock->m2 + 2;
531 clock->p = clock->p1 * clock->p2;
532 clock->vco = refclk * clock->m / clock->n;
533 clock->dot = clock->vco / clock->p;
534 }
535
536 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
537 {
538 if (IS_PINEVIEW(dev)) {
539 pineview_clock(refclk, clock);
540 return;
541 }
542 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
543 clock->p = clock->p1 * clock->p2;
544 clock->vco = refclk * clock->m / (clock->n + 2);
545 clock->dot = clock->vco / clock->p;
546 }
547
548 /**
549 * Returns whether any output on the specified pipe is of the specified type
550 */
551 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
552 {
553 struct drm_device *dev = crtc->dev;
554 struct drm_mode_config *mode_config = &dev->mode_config;
555 struct intel_encoder *encoder;
556
557 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
558 if (encoder->base.crtc == crtc && encoder->type == type)
559 return true;
560
561 return false;
562 }
563
564 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
565 /**
566 * Returns whether the given set of divisors are valid for a given refclk with
567 * the given connectors.
568 */
569
570 static bool intel_PLL_is_valid(struct drm_device *dev,
571 const intel_limit_t *limit,
572 const intel_clock_t *clock)
573 {
574 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
575 INTELPllInvalid("p1 out of range\n");
576 if (clock->p < limit->p.min || limit->p.max < clock->p)
577 INTELPllInvalid("p out of range\n");
578 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
579 INTELPllInvalid("m2 out of range\n");
580 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
581 INTELPllInvalid("m1 out of range\n");
582 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
583 INTELPllInvalid("m1 <= m2\n");
584 if (clock->m < limit->m.min || limit->m.max < clock->m)
585 INTELPllInvalid("m out of range\n");
586 if (clock->n < limit->n.min || limit->n.max < clock->n)
587 INTELPllInvalid("n out of range\n");
588 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
589 INTELPllInvalid("vco out of range\n");
590 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
591 * connector, etc., rather than just a single range.
592 */
593 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
594 INTELPllInvalid("dot out of range\n");
595
596 return true;
597 }
598
599 static bool
600 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
601 int target, int refclk, intel_clock_t *match_clock,
602 intel_clock_t *best_clock)
603
604 {
605 struct drm_device *dev = crtc->dev;
606 struct drm_i915_private *dev_priv = dev->dev_private;
607 intel_clock_t clock;
608 int err = target;
609
610 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
611 (I915_READ(LVDS)) != 0) {
612 /*
613 * For LVDS, if the panel is on, just rely on its current
614 * settings for dual-channel. We haven't figured out how to
615 * reliably set up different single/dual channel state, if we
616 * even can.
617 */
618 if (is_dual_link_lvds(dev_priv, LVDS))
619 clock.p2 = limit->p2.p2_fast;
620 else
621 clock.p2 = limit->p2.p2_slow;
622 } else {
623 if (target < limit->p2.dot_limit)
624 clock.p2 = limit->p2.p2_slow;
625 else
626 clock.p2 = limit->p2.p2_fast;
627 }
628
629 memset(best_clock, 0, sizeof(*best_clock));
630
631 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
632 clock.m1++) {
633 for (clock.m2 = limit->m2.min;
634 clock.m2 <= limit->m2.max; clock.m2++) {
635 /* m1 is always 0 in Pineview */
636 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
637 break;
638 for (clock.n = limit->n.min;
639 clock.n <= limit->n.max; clock.n++) {
640 for (clock.p1 = limit->p1.min;
641 clock.p1 <= limit->p1.max; clock.p1++) {
642 int this_err;
643
644 intel_clock(dev, refclk, &clock);
645 if (!intel_PLL_is_valid(dev, limit,
646 &clock))
647 continue;
648 if (match_clock &&
649 clock.p != match_clock->p)
650 continue;
651
652 this_err = abs(clock.dot - target);
653 if (this_err < err) {
654 *best_clock = clock;
655 err = this_err;
656 }
657 }
658 }
659 }
660 }
661
662 return (err != target);
663 }
664
665 static bool
666 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
667 int target, int refclk, intel_clock_t *match_clock,
668 intel_clock_t *best_clock)
669 {
670 struct drm_device *dev = crtc->dev;
671 struct drm_i915_private *dev_priv = dev->dev_private;
672 intel_clock_t clock;
673 int max_n;
674 bool found;
675 /* approximately equals target * 0.00585 */
676 int err_most = (target >> 8) + (target >> 9);
677 found = false;
678
679 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
680 int lvds_reg;
681
682 if (HAS_PCH_SPLIT(dev))
683 lvds_reg = PCH_LVDS;
684 else
685 lvds_reg = LVDS;
686 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
687 LVDS_CLKB_POWER_UP)
688 clock.p2 = limit->p2.p2_fast;
689 else
690 clock.p2 = limit->p2.p2_slow;
691 } else {
692 if (target < limit->p2.dot_limit)
693 clock.p2 = limit->p2.p2_slow;
694 else
695 clock.p2 = limit->p2.p2_fast;
696 }
697
698 memset(best_clock, 0, sizeof(*best_clock));
699 max_n = limit->n.max;
700 /* based on hardware requirement, prefer smaller n to precision */
701 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
702 /* based on hardware requirement, prefere larger m1,m2 */
703 for (clock.m1 = limit->m1.max;
704 clock.m1 >= limit->m1.min; clock.m1--) {
705 for (clock.m2 = limit->m2.max;
706 clock.m2 >= limit->m2.min; clock.m2--) {
707 for (clock.p1 = limit->p1.max;
708 clock.p1 >= limit->p1.min; clock.p1--) {
709 int this_err;
710
711 intel_clock(dev, refclk, &clock);
712 if (!intel_PLL_is_valid(dev, limit,
713 &clock))
714 continue;
715 if (match_clock &&
716 clock.p != match_clock->p)
717 continue;
718
719 this_err = abs(clock.dot - target);
720 if (this_err < err_most) {
721 *best_clock = clock;
722 err_most = this_err;
723 max_n = clock.n;
724 found = true;
725 }
726 }
727 }
728 }
729 }
730 return found;
731 }
732
733 static bool
734 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
735 int target, int refclk, intel_clock_t *match_clock,
736 intel_clock_t *best_clock)
737 {
738 struct drm_device *dev = crtc->dev;
739 intel_clock_t clock;
740
741 if (target < 200000) {
742 clock.n = 1;
743 clock.p1 = 2;
744 clock.p2 = 10;
745 clock.m1 = 12;
746 clock.m2 = 9;
747 } else {
748 clock.n = 2;
749 clock.p1 = 1;
750 clock.p2 = 10;
751 clock.m1 = 14;
752 clock.m2 = 8;
753 }
754 intel_clock(dev, refclk, &clock);
755 memcpy(best_clock, &clock, sizeof(intel_clock_t));
756 return true;
757 }
758
759 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
760 static bool
761 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
762 int target, int refclk, intel_clock_t *match_clock,
763 intel_clock_t *best_clock)
764 {
765 intel_clock_t clock;
766 if (target < 200000) {
767 clock.p1 = 2;
768 clock.p2 = 10;
769 clock.n = 2;
770 clock.m1 = 23;
771 clock.m2 = 8;
772 } else {
773 clock.p1 = 1;
774 clock.p2 = 10;
775 clock.n = 1;
776 clock.m1 = 14;
777 clock.m2 = 2;
778 }
779 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
780 clock.p = (clock.p1 * clock.p2);
781 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
782 clock.vco = 0;
783 memcpy(best_clock, &clock, sizeof(intel_clock_t));
784 return true;
785 }
786
787 /**
788 * intel_wait_for_vblank - wait for vblank on a given pipe
789 * @dev: drm device
790 * @pipe: pipe to wait for
791 *
792 * Wait for vblank to occur on a given pipe. Needed for various bits of
793 * mode setting code.
794 */
795 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
796 {
797 struct drm_i915_private *dev_priv = dev->dev_private;
798 int pipestat_reg = PIPESTAT(pipe);
799
800 /* Clear existing vblank status. Note this will clear any other
801 * sticky status fields as well.
802 *
803 * This races with i915_driver_irq_handler() with the result
804 * that either function could miss a vblank event. Here it is not
805 * fatal, as we will either wait upon the next vblank interrupt or
806 * timeout. Generally speaking intel_wait_for_vblank() is only
807 * called during modeset at which time the GPU should be idle and
808 * should *not* be performing page flips and thus not waiting on
809 * vblanks...
810 * Currently, the result of us stealing a vblank from the irq
811 * handler is that a single frame will be skipped during swapbuffers.
812 */
813 I915_WRITE(pipestat_reg,
814 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
815
816 /* Wait for vblank interrupt bit to set */
817 if (wait_for(I915_READ(pipestat_reg) &
818 PIPE_VBLANK_INTERRUPT_STATUS,
819 50))
820 DRM_DEBUG_KMS("vblank wait timed out\n");
821 }
822
823 /*
824 * intel_wait_for_pipe_off - wait for pipe to turn off
825 * @dev: drm device
826 * @pipe: pipe to wait for
827 *
828 * After disabling a pipe, we can't wait for vblank in the usual way,
829 * spinning on the vblank interrupt status bit, since we won't actually
830 * see an interrupt when the pipe is disabled.
831 *
832 * On Gen4 and above:
833 * wait for the pipe register state bit to turn off
834 *
835 * Otherwise:
836 * wait for the display line value to settle (it usually
837 * ends up stopping at the start of the next frame).
838 *
839 */
840 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
841 {
842 struct drm_i915_private *dev_priv = dev->dev_private;
843
844 if (INTEL_INFO(dev)->gen >= 4) {
845 int reg = PIPECONF(pipe);
846
847 /* Wait for the Pipe State to go off */
848 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
849 100))
850 DRM_DEBUG_KMS("pipe_off wait timed out\n");
851 } else {
852 u32 last_line, line_mask;
853 int reg = PIPEDSL(pipe);
854 unsigned long timeout = jiffies + msecs_to_jiffies(100);
855
856 if (IS_GEN2(dev))
857 line_mask = DSL_LINEMASK_GEN2;
858 else
859 line_mask = DSL_LINEMASK_GEN3;
860
861 /* Wait for the display line to settle */
862 do {
863 last_line = I915_READ(reg) & line_mask;
864 mdelay(5);
865 } while (((I915_READ(reg) & line_mask) != last_line) &&
866 time_after(timeout, jiffies));
867 if (time_after(jiffies, timeout))
868 DRM_DEBUG_KMS("pipe_off wait timed out\n");
869 }
870 }
871
872 static const char *state_string(bool enabled)
873 {
874 return enabled ? "on" : "off";
875 }
876
877 /* Only for pre-ILK configs */
878 static void assert_pll(struct drm_i915_private *dev_priv,
879 enum pipe pipe, bool state)
880 {
881 int reg;
882 u32 val;
883 bool cur_state;
884
885 reg = DPLL(pipe);
886 val = I915_READ(reg);
887 cur_state = !!(val & DPLL_VCO_ENABLE);
888 WARN(cur_state != state,
889 "PLL state assertion failure (expected %s, current %s)\n",
890 state_string(state), state_string(cur_state));
891 }
892 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
893 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
894
895 /* For ILK+ */
896 static void assert_pch_pll(struct drm_i915_private *dev_priv,
897 struct intel_crtc *intel_crtc, bool state)
898 {
899 int reg;
900 u32 val;
901 bool cur_state;
902
903 if (!intel_crtc->pch_pll) {
904 WARN(1, "asserting PCH PLL enabled with no PLL\n");
905 return;
906 }
907
908 if (HAS_PCH_CPT(dev_priv->dev)) {
909 u32 pch_dpll;
910
911 pch_dpll = I915_READ(PCH_DPLL_SEL);
912
913 /* Make sure the selected PLL is enabled to the transcoder */
914 WARN(!((pch_dpll >> (4 * intel_crtc->pipe)) & 8),
915 "transcoder %d PLL not enabled\n", intel_crtc->pipe);
916 }
917
918 reg = intel_crtc->pch_pll->pll_reg;
919 val = I915_READ(reg);
920 cur_state = !!(val & DPLL_VCO_ENABLE);
921 WARN(cur_state != state,
922 "PCH PLL state assertion failure (expected %s, current %s)\n",
923 state_string(state), state_string(cur_state));
924 }
925 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
926 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
927
928 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
929 enum pipe pipe, bool state)
930 {
931 int reg;
932 u32 val;
933 bool cur_state;
934
935 reg = FDI_TX_CTL(pipe);
936 val = I915_READ(reg);
937 cur_state = !!(val & FDI_TX_ENABLE);
938 WARN(cur_state != state,
939 "FDI TX state assertion failure (expected %s, current %s)\n",
940 state_string(state), state_string(cur_state));
941 }
942 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
943 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
944
945 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
946 enum pipe pipe, bool state)
947 {
948 int reg;
949 u32 val;
950 bool cur_state;
951
952 reg = FDI_RX_CTL(pipe);
953 val = I915_READ(reg);
954 cur_state = !!(val & FDI_RX_ENABLE);
955 WARN(cur_state != state,
956 "FDI RX state assertion failure (expected %s, current %s)\n",
957 state_string(state), state_string(cur_state));
958 }
959 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
960 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
961
962 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
963 enum pipe pipe)
964 {
965 int reg;
966 u32 val;
967
968 /* ILK FDI PLL is always enabled */
969 if (dev_priv->info->gen == 5)
970 return;
971
972 reg = FDI_TX_CTL(pipe);
973 val = I915_READ(reg);
974 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
975 }
976
977 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
978 enum pipe pipe)
979 {
980 int reg;
981 u32 val;
982
983 reg = FDI_RX_CTL(pipe);
984 val = I915_READ(reg);
985 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
986 }
987
988 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
989 enum pipe pipe)
990 {
991 int pp_reg, lvds_reg;
992 u32 val;
993 enum pipe panel_pipe = PIPE_A;
994 bool locked = true;
995
996 if (HAS_PCH_SPLIT(dev_priv->dev)) {
997 pp_reg = PCH_PP_CONTROL;
998 lvds_reg = PCH_LVDS;
999 } else {
1000 pp_reg = PP_CONTROL;
1001 lvds_reg = LVDS;
1002 }
1003
1004 val = I915_READ(pp_reg);
1005 if (!(val & PANEL_POWER_ON) ||
1006 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1007 locked = false;
1008
1009 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1010 panel_pipe = PIPE_B;
1011
1012 WARN(panel_pipe == pipe && locked,
1013 "panel assertion failure, pipe %c regs locked\n",
1014 pipe_name(pipe));
1015 }
1016
1017 void assert_pipe(struct drm_i915_private *dev_priv,
1018 enum pipe pipe, bool state)
1019 {
1020 int reg;
1021 u32 val;
1022 bool cur_state;
1023
1024 /* if we need the pipe A quirk it must be always on */
1025 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1026 state = true;
1027
1028 reg = PIPECONF(pipe);
1029 val = I915_READ(reg);
1030 cur_state = !!(val & PIPECONF_ENABLE);
1031 WARN(cur_state != state,
1032 "pipe %c assertion failure (expected %s, current %s)\n",
1033 pipe_name(pipe), state_string(state), state_string(cur_state));
1034 }
1035
1036 static void assert_plane(struct drm_i915_private *dev_priv,
1037 enum plane plane, bool state)
1038 {
1039 int reg;
1040 u32 val;
1041 bool cur_state;
1042
1043 reg = DSPCNTR(plane);
1044 val = I915_READ(reg);
1045 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1046 WARN(cur_state != state,
1047 "plane %c assertion failure (expected %s, current %s)\n",
1048 plane_name(plane), state_string(state), state_string(cur_state));
1049 }
1050
1051 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1052 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1053
1054 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1055 enum pipe pipe)
1056 {
1057 int reg, i;
1058 u32 val;
1059 int cur_pipe;
1060
1061 /* Planes are fixed to pipes on ILK+ */
1062 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1063 reg = DSPCNTR(pipe);
1064 val = I915_READ(reg);
1065 WARN((val & DISPLAY_PLANE_ENABLE),
1066 "plane %c assertion failure, should be disabled but not\n",
1067 plane_name(pipe));
1068 return;
1069 }
1070
1071 /* Need to check both planes against the pipe */
1072 for (i = 0; i < 2; i++) {
1073 reg = DSPCNTR(i);
1074 val = I915_READ(reg);
1075 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1076 DISPPLANE_SEL_PIPE_SHIFT;
1077 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1078 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1079 plane_name(i), pipe_name(pipe));
1080 }
1081 }
1082
1083 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1084 {
1085 u32 val;
1086 bool enabled;
1087
1088 val = I915_READ(PCH_DREF_CONTROL);
1089 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1090 DREF_SUPERSPREAD_SOURCE_MASK));
1091 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1092 }
1093
1094 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1095 enum pipe pipe)
1096 {
1097 int reg;
1098 u32 val;
1099 bool enabled;
1100
1101 reg = TRANSCONF(pipe);
1102 val = I915_READ(reg);
1103 enabled = !!(val & TRANS_ENABLE);
1104 WARN(enabled,
1105 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1106 pipe_name(pipe));
1107 }
1108
1109 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1110 enum pipe pipe, u32 port_sel, u32 val)
1111 {
1112 if ((val & DP_PORT_EN) == 0)
1113 return false;
1114
1115 if (HAS_PCH_CPT(dev_priv->dev)) {
1116 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1117 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1118 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1119 return false;
1120 } else {
1121 if ((val & DP_PIPE_MASK) != (pipe << 30))
1122 return false;
1123 }
1124 return true;
1125 }
1126
1127 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1128 enum pipe pipe, u32 val)
1129 {
1130 if ((val & PORT_ENABLE) == 0)
1131 return false;
1132
1133 if (HAS_PCH_CPT(dev_priv->dev)) {
1134 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1135 return false;
1136 } else {
1137 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1138 return false;
1139 }
1140 return true;
1141 }
1142
1143 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1144 enum pipe pipe, u32 val)
1145 {
1146 if ((val & LVDS_PORT_EN) == 0)
1147 return false;
1148
1149 if (HAS_PCH_CPT(dev_priv->dev)) {
1150 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1151 return false;
1152 } else {
1153 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1154 return false;
1155 }
1156 return true;
1157 }
1158
1159 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1160 enum pipe pipe, u32 val)
1161 {
1162 if ((val & ADPA_DAC_ENABLE) == 0)
1163 return false;
1164 if (HAS_PCH_CPT(dev_priv->dev)) {
1165 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1166 return false;
1167 } else {
1168 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1169 return false;
1170 }
1171 return true;
1172 }
1173
1174 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1175 enum pipe pipe, int reg, u32 port_sel)
1176 {
1177 u32 val = I915_READ(reg);
1178 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1179 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1180 reg, pipe_name(pipe));
1181 }
1182
1183 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1184 enum pipe pipe, int reg)
1185 {
1186 u32 val = I915_READ(reg);
1187 WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
1188 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1189 reg, pipe_name(pipe));
1190 }
1191
1192 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1193 enum pipe pipe)
1194 {
1195 int reg;
1196 u32 val;
1197
1198 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1199 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1200 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1201
1202 reg = PCH_ADPA;
1203 val = I915_READ(reg);
1204 WARN(adpa_pipe_enabled(dev_priv, val, pipe),
1205 "PCH VGA enabled on transcoder %c, should be disabled\n",
1206 pipe_name(pipe));
1207
1208 reg = PCH_LVDS;
1209 val = I915_READ(reg);
1210 WARN(lvds_pipe_enabled(dev_priv, val, pipe),
1211 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1212 pipe_name(pipe));
1213
1214 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1215 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1216 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1217 }
1218
1219 /**
1220 * intel_enable_pll - enable a PLL
1221 * @dev_priv: i915 private structure
1222 * @pipe: pipe PLL to enable
1223 *
1224 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1225 * make sure the PLL reg is writable first though, since the panel write
1226 * protect mechanism may be enabled.
1227 *
1228 * Note! This is for pre-ILK only.
1229 */
1230 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1231 {
1232 int reg;
1233 u32 val;
1234
1235 /* No really, not for ILK+ */
1236 BUG_ON(dev_priv->info->gen >= 5);
1237
1238 /* PLL is protected by panel, make sure we can write it */
1239 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1240 assert_panel_unlocked(dev_priv, pipe);
1241
1242 reg = DPLL(pipe);
1243 val = I915_READ(reg);
1244 val |= DPLL_VCO_ENABLE;
1245
1246 /* We do this three times for luck */
1247 I915_WRITE(reg, val);
1248 POSTING_READ(reg);
1249 udelay(150); /* wait for warmup */
1250 I915_WRITE(reg, val);
1251 POSTING_READ(reg);
1252 udelay(150); /* wait for warmup */
1253 I915_WRITE(reg, val);
1254 POSTING_READ(reg);
1255 udelay(150); /* wait for warmup */
1256 }
1257
1258 /**
1259 * intel_disable_pll - disable a PLL
1260 * @dev_priv: i915 private structure
1261 * @pipe: pipe PLL to disable
1262 *
1263 * Disable the PLL for @pipe, making sure the pipe is off first.
1264 *
1265 * Note! This is for pre-ILK only.
1266 */
1267 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1268 {
1269 int reg;
1270 u32 val;
1271
1272 /* Don't disable pipe A or pipe A PLLs if needed */
1273 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1274 return;
1275
1276 /* Make sure the pipe isn't still relying on us */
1277 assert_pipe_disabled(dev_priv, pipe);
1278
1279 reg = DPLL(pipe);
1280 val = I915_READ(reg);
1281 val &= ~DPLL_VCO_ENABLE;
1282 I915_WRITE(reg, val);
1283 POSTING_READ(reg);
1284 }
1285
1286 /**
1287 * intel_enable_pch_pll - enable PCH PLL
1288 * @dev_priv: i915 private structure
1289 * @pipe: pipe PLL to enable
1290 *
1291 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1292 * drives the transcoder clock.
1293 */
1294 static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
1295 {
1296 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1297 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1298 int reg;
1299 u32 val;
1300
1301 /* PCH only available on ILK+ */
1302 BUG_ON(dev_priv->info->gen < 5);
1303 BUG_ON(pll == NULL);
1304 BUG_ON(pll->refcount == 0);
1305
1306 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1307 pll->pll_reg, pll->active, pll->on,
1308 intel_crtc->base.base.id);
1309
1310 /* PCH refclock must be enabled first */
1311 assert_pch_refclk_enabled(dev_priv);
1312
1313 if (pll->active++ && pll->on) {
1314 assert_pch_pll_enabled(dev_priv, intel_crtc);
1315 return;
1316 }
1317
1318 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1319
1320 reg = pll->pll_reg;
1321 val = I915_READ(reg);
1322 val |= DPLL_VCO_ENABLE;
1323 I915_WRITE(reg, val);
1324 POSTING_READ(reg);
1325 udelay(200);
1326
1327 pll->on = true;
1328 }
1329
1330 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1331 {
1332 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1333 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1334 int reg;
1335 u32 val;
1336
1337 /* PCH only available on ILK+ */
1338 BUG_ON(dev_priv->info->gen < 5);
1339 if (pll == NULL)
1340 return;
1341
1342 BUG_ON(pll->refcount == 0);
1343
1344 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1345 pll->pll_reg, pll->active, pll->on,
1346 intel_crtc->base.base.id);
1347
1348 BUG_ON(pll->active == 0);
1349 if (--pll->active) {
1350 assert_pch_pll_enabled(dev_priv, intel_crtc);
1351 return;
1352 }
1353
1354 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1355
1356 /* Make sure transcoder isn't still depending on us */
1357 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1358
1359 reg = pll->pll_reg;
1360 val = I915_READ(reg);
1361 val &= ~DPLL_VCO_ENABLE;
1362 I915_WRITE(reg, val);
1363 POSTING_READ(reg);
1364 udelay(200);
1365
1366 pll->on = false;
1367 }
1368
1369 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1370 enum pipe pipe)
1371 {
1372 int reg;
1373 u32 val, pipeconf_val;
1374 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1375
1376 /* PCH only available on ILK+ */
1377 BUG_ON(dev_priv->info->gen < 5);
1378
1379 /* Make sure PCH DPLL is enabled */
1380 assert_pch_pll_enabled(dev_priv, to_intel_crtc(crtc));
1381
1382 /* FDI must be feeding us bits for PCH ports */
1383 assert_fdi_tx_enabled(dev_priv, pipe);
1384 assert_fdi_rx_enabled(dev_priv, pipe);
1385
1386 reg = TRANSCONF(pipe);
1387 val = I915_READ(reg);
1388 pipeconf_val = I915_READ(PIPECONF(pipe));
1389
1390 if (HAS_PCH_IBX(dev_priv->dev)) {
1391 /*
1392 * make the BPC in transcoder be consistent with
1393 * that in pipeconf reg.
1394 */
1395 val &= ~PIPE_BPC_MASK;
1396 val |= pipeconf_val & PIPE_BPC_MASK;
1397 }
1398
1399 val &= ~TRANS_INTERLACE_MASK;
1400 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1401 if (HAS_PCH_IBX(dev_priv->dev) &&
1402 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1403 val |= TRANS_LEGACY_INTERLACED_ILK;
1404 else
1405 val |= TRANS_INTERLACED;
1406 else
1407 val |= TRANS_PROGRESSIVE;
1408
1409 I915_WRITE(reg, val | TRANS_ENABLE);
1410 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1411 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1412 }
1413
1414 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1415 enum pipe pipe)
1416 {
1417 int reg;
1418 u32 val;
1419
1420 /* FDI relies on the transcoder */
1421 assert_fdi_tx_disabled(dev_priv, pipe);
1422 assert_fdi_rx_disabled(dev_priv, pipe);
1423
1424 /* Ports must be off as well */
1425 assert_pch_ports_disabled(dev_priv, pipe);
1426
1427 reg = TRANSCONF(pipe);
1428 val = I915_READ(reg);
1429 val &= ~TRANS_ENABLE;
1430 I915_WRITE(reg, val);
1431 /* wait for PCH transcoder off, transcoder state */
1432 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1433 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1434 }
1435
1436 /**
1437 * intel_enable_pipe - enable a pipe, asserting requirements
1438 * @dev_priv: i915 private structure
1439 * @pipe: pipe to enable
1440 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1441 *
1442 * Enable @pipe, making sure that various hardware specific requirements
1443 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1444 *
1445 * @pipe should be %PIPE_A or %PIPE_B.
1446 *
1447 * Will wait until the pipe is actually running (i.e. first vblank) before
1448 * returning.
1449 */
1450 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1451 bool pch_port)
1452 {
1453 int reg;
1454 u32 val;
1455
1456 /*
1457 * A pipe without a PLL won't actually be able to drive bits from
1458 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1459 * need the check.
1460 */
1461 if (!HAS_PCH_SPLIT(dev_priv->dev))
1462 assert_pll_enabled(dev_priv, pipe);
1463 else {
1464 if (pch_port) {
1465 /* if driving the PCH, we need FDI enabled */
1466 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1467 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1468 }
1469 /* FIXME: assert CPU port conditions for SNB+ */
1470 }
1471
1472 reg = PIPECONF(pipe);
1473 val = I915_READ(reg);
1474 if (val & PIPECONF_ENABLE)
1475 return;
1476
1477 I915_WRITE(reg, val | PIPECONF_ENABLE);
1478 intel_wait_for_vblank(dev_priv->dev, pipe);
1479 }
1480
1481 /**
1482 * intel_disable_pipe - disable a pipe, asserting requirements
1483 * @dev_priv: i915 private structure
1484 * @pipe: pipe to disable
1485 *
1486 * Disable @pipe, making sure that various hardware specific requirements
1487 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1488 *
1489 * @pipe should be %PIPE_A or %PIPE_B.
1490 *
1491 * Will wait until the pipe has shut down before returning.
1492 */
1493 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1494 enum pipe pipe)
1495 {
1496 int reg;
1497 u32 val;
1498
1499 /*
1500 * Make sure planes won't keep trying to pump pixels to us,
1501 * or we might hang the display.
1502 */
1503 assert_planes_disabled(dev_priv, pipe);
1504
1505 /* Don't disable pipe A or pipe A PLLs if needed */
1506 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1507 return;
1508
1509 reg = PIPECONF(pipe);
1510 val = I915_READ(reg);
1511 if ((val & PIPECONF_ENABLE) == 0)
1512 return;
1513
1514 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1515 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1516 }
1517
1518 /*
1519 * Plane regs are double buffered, going from enabled->disabled needs a
1520 * trigger in order to latch. The display address reg provides this.
1521 */
1522 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1523 enum plane plane)
1524 {
1525 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1526 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1527 }
1528
1529 /**
1530 * intel_enable_plane - enable a display plane on a given pipe
1531 * @dev_priv: i915 private structure
1532 * @plane: plane to enable
1533 * @pipe: pipe being fed
1534 *
1535 * Enable @plane on @pipe, making sure that @pipe is running first.
1536 */
1537 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1538 enum plane plane, enum pipe pipe)
1539 {
1540 int reg;
1541 u32 val;
1542
1543 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1544 assert_pipe_enabled(dev_priv, pipe);
1545
1546 reg = DSPCNTR(plane);
1547 val = I915_READ(reg);
1548 if (val & DISPLAY_PLANE_ENABLE)
1549 return;
1550
1551 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1552 intel_flush_display_plane(dev_priv, plane);
1553 intel_wait_for_vblank(dev_priv->dev, pipe);
1554 }
1555
1556 /**
1557 * intel_disable_plane - disable a display plane
1558 * @dev_priv: i915 private structure
1559 * @plane: plane to disable
1560 * @pipe: pipe consuming the data
1561 *
1562 * Disable @plane; should be an independent operation.
1563 */
1564 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1565 enum plane plane, enum pipe pipe)
1566 {
1567 int reg;
1568 u32 val;
1569
1570 reg = DSPCNTR(plane);
1571 val = I915_READ(reg);
1572 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1573 return;
1574
1575 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1576 intel_flush_display_plane(dev_priv, plane);
1577 intel_wait_for_vblank(dev_priv->dev, pipe);
1578 }
1579
1580 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1581 enum pipe pipe, int reg, u32 port_sel)
1582 {
1583 u32 val = I915_READ(reg);
1584 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1585 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1586 I915_WRITE(reg, val & ~DP_PORT_EN);
1587 }
1588 }
1589
1590 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1591 enum pipe pipe, int reg)
1592 {
1593 u32 val = I915_READ(reg);
1594 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1595 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1596 reg, pipe);
1597 I915_WRITE(reg, val & ~PORT_ENABLE);
1598 }
1599 }
1600
1601 /* Disable any ports connected to this transcoder */
1602 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1603 enum pipe pipe)
1604 {
1605 u32 reg, val;
1606
1607 val = I915_READ(PCH_PP_CONTROL);
1608 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1609
1610 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1611 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1612 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1613
1614 reg = PCH_ADPA;
1615 val = I915_READ(reg);
1616 if (adpa_pipe_enabled(dev_priv, val, pipe))
1617 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1618
1619 reg = PCH_LVDS;
1620 val = I915_READ(reg);
1621 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1622 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1623 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1624 POSTING_READ(reg);
1625 udelay(100);
1626 }
1627
1628 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1629 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1630 disable_pch_hdmi(dev_priv, pipe, HDMID);
1631 }
1632
1633 int
1634 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1635 struct drm_i915_gem_object *obj,
1636 struct intel_ring_buffer *pipelined)
1637 {
1638 struct drm_i915_private *dev_priv = dev->dev_private;
1639 u32 alignment;
1640 int ret;
1641
1642 switch (obj->tiling_mode) {
1643 case I915_TILING_NONE:
1644 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1645 alignment = 128 * 1024;
1646 else if (INTEL_INFO(dev)->gen >= 4)
1647 alignment = 4 * 1024;
1648 else
1649 alignment = 64 * 1024;
1650 break;
1651 case I915_TILING_X:
1652 /* pin() will align the object as required by fence */
1653 alignment = 0;
1654 break;
1655 case I915_TILING_Y:
1656 /* FIXME: Is this true? */
1657 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1658 return -EINVAL;
1659 default:
1660 BUG();
1661 }
1662
1663 dev_priv->mm.interruptible = false;
1664 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1665 if (ret)
1666 goto err_interruptible;
1667
1668 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1669 * fence, whereas 965+ only requires a fence if using
1670 * framebuffer compression. For simplicity, we always install
1671 * a fence as the cost is not that onerous.
1672 */
1673 ret = i915_gem_object_get_fence(obj);
1674 if (ret)
1675 goto err_unpin;
1676
1677 i915_gem_object_pin_fence(obj);
1678
1679 dev_priv->mm.interruptible = true;
1680 return 0;
1681
1682 err_unpin:
1683 i915_gem_object_unpin(obj);
1684 err_interruptible:
1685 dev_priv->mm.interruptible = true;
1686 return ret;
1687 }
1688
1689 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1690 {
1691 i915_gem_object_unpin_fence(obj);
1692 i915_gem_object_unpin(obj);
1693 }
1694
1695 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1696 int x, int y)
1697 {
1698 struct drm_device *dev = crtc->dev;
1699 struct drm_i915_private *dev_priv = dev->dev_private;
1700 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1701 struct intel_framebuffer *intel_fb;
1702 struct drm_i915_gem_object *obj;
1703 int plane = intel_crtc->plane;
1704 unsigned long Start, Offset;
1705 u32 dspcntr;
1706 u32 reg;
1707
1708 switch (plane) {
1709 case 0:
1710 case 1:
1711 break;
1712 default:
1713 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1714 return -EINVAL;
1715 }
1716
1717 intel_fb = to_intel_framebuffer(fb);
1718 obj = intel_fb->obj;
1719
1720 reg = DSPCNTR(plane);
1721 dspcntr = I915_READ(reg);
1722 /* Mask out pixel format bits in case we change it */
1723 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1724 switch (fb->bits_per_pixel) {
1725 case 8:
1726 dspcntr |= DISPPLANE_8BPP;
1727 break;
1728 case 16:
1729 if (fb->depth == 15)
1730 dspcntr |= DISPPLANE_15_16BPP;
1731 else
1732 dspcntr |= DISPPLANE_16BPP;
1733 break;
1734 case 24:
1735 case 32:
1736 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1737 break;
1738 default:
1739 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1740 return -EINVAL;
1741 }
1742 if (INTEL_INFO(dev)->gen >= 4) {
1743 if (obj->tiling_mode != I915_TILING_NONE)
1744 dspcntr |= DISPPLANE_TILED;
1745 else
1746 dspcntr &= ~DISPPLANE_TILED;
1747 }
1748
1749 I915_WRITE(reg, dspcntr);
1750
1751 Start = obj->gtt_offset;
1752 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1753
1754 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1755 Start, Offset, x, y, fb->pitches[0]);
1756 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1757 if (INTEL_INFO(dev)->gen >= 4) {
1758 I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
1759 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1760 I915_WRITE(DSPADDR(plane), Offset);
1761 } else
1762 I915_WRITE(DSPADDR(plane), Start + Offset);
1763 POSTING_READ(reg);
1764
1765 return 0;
1766 }
1767
1768 static int ironlake_update_plane(struct drm_crtc *crtc,
1769 struct drm_framebuffer *fb, int x, int y)
1770 {
1771 struct drm_device *dev = crtc->dev;
1772 struct drm_i915_private *dev_priv = dev->dev_private;
1773 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1774 struct intel_framebuffer *intel_fb;
1775 struct drm_i915_gem_object *obj;
1776 int plane = intel_crtc->plane;
1777 unsigned long Start, Offset;
1778 u32 dspcntr;
1779 u32 reg;
1780
1781 switch (plane) {
1782 case 0:
1783 case 1:
1784 case 2:
1785 break;
1786 default:
1787 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1788 return -EINVAL;
1789 }
1790
1791 intel_fb = to_intel_framebuffer(fb);
1792 obj = intel_fb->obj;
1793
1794 reg = DSPCNTR(plane);
1795 dspcntr = I915_READ(reg);
1796 /* Mask out pixel format bits in case we change it */
1797 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1798 switch (fb->bits_per_pixel) {
1799 case 8:
1800 dspcntr |= DISPPLANE_8BPP;
1801 break;
1802 case 16:
1803 if (fb->depth != 16)
1804 return -EINVAL;
1805
1806 dspcntr |= DISPPLANE_16BPP;
1807 break;
1808 case 24:
1809 case 32:
1810 if (fb->depth == 24)
1811 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1812 else if (fb->depth == 30)
1813 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1814 else
1815 return -EINVAL;
1816 break;
1817 default:
1818 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1819 return -EINVAL;
1820 }
1821
1822 if (obj->tiling_mode != I915_TILING_NONE)
1823 dspcntr |= DISPPLANE_TILED;
1824 else
1825 dspcntr &= ~DISPPLANE_TILED;
1826
1827 /* must disable */
1828 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1829
1830 I915_WRITE(reg, dspcntr);
1831
1832 Start = obj->gtt_offset;
1833 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1834
1835 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1836 Start, Offset, x, y, fb->pitches[0]);
1837 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1838 I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
1839 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1840 I915_WRITE(DSPADDR(plane), Offset);
1841 POSTING_READ(reg);
1842
1843 return 0;
1844 }
1845
1846 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1847 static int
1848 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1849 int x, int y, enum mode_set_atomic state)
1850 {
1851 struct drm_device *dev = crtc->dev;
1852 struct drm_i915_private *dev_priv = dev->dev_private;
1853
1854 if (dev_priv->display.disable_fbc)
1855 dev_priv->display.disable_fbc(dev);
1856 intel_increase_pllclock(crtc);
1857
1858 return dev_priv->display.update_plane(crtc, fb, x, y);
1859 }
1860
1861 static int
1862 intel_finish_fb(struct drm_framebuffer *old_fb)
1863 {
1864 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1865 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1866 bool was_interruptible = dev_priv->mm.interruptible;
1867 int ret;
1868
1869 wait_event(dev_priv->pending_flip_queue,
1870 atomic_read(&dev_priv->mm.wedged) ||
1871 atomic_read(&obj->pending_flip) == 0);
1872
1873 /* Big Hammer, we also need to ensure that any pending
1874 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1875 * current scanout is retired before unpinning the old
1876 * framebuffer.
1877 *
1878 * This should only fail upon a hung GPU, in which case we
1879 * can safely continue.
1880 */
1881 dev_priv->mm.interruptible = false;
1882 ret = i915_gem_object_finish_gpu(obj);
1883 dev_priv->mm.interruptible = was_interruptible;
1884
1885 return ret;
1886 }
1887
1888 static int
1889 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1890 struct drm_framebuffer *old_fb)
1891 {
1892 struct drm_device *dev = crtc->dev;
1893 struct drm_i915_private *dev_priv = dev->dev_private;
1894 struct drm_i915_master_private *master_priv;
1895 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1896 int ret;
1897
1898 /* no fb bound */
1899 if (!crtc->fb) {
1900 DRM_ERROR("No FB bound\n");
1901 return 0;
1902 }
1903
1904 switch (intel_crtc->plane) {
1905 case 0:
1906 case 1:
1907 break;
1908 case 2:
1909 if (IS_IVYBRIDGE(dev))
1910 break;
1911 /* fall through otherwise */
1912 default:
1913 DRM_ERROR("no plane for crtc\n");
1914 return -EINVAL;
1915 }
1916
1917 mutex_lock(&dev->struct_mutex);
1918 ret = intel_pin_and_fence_fb_obj(dev,
1919 to_intel_framebuffer(crtc->fb)->obj,
1920 NULL);
1921 if (ret != 0) {
1922 mutex_unlock(&dev->struct_mutex);
1923 DRM_ERROR("pin & fence failed\n");
1924 return ret;
1925 }
1926
1927 if (old_fb)
1928 intel_finish_fb(old_fb);
1929
1930 ret = dev_priv->display.update_plane(crtc, crtc->fb, x, y);
1931 if (ret) {
1932 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
1933 mutex_unlock(&dev->struct_mutex);
1934 DRM_ERROR("failed to update base address\n");
1935 return ret;
1936 }
1937
1938 if (old_fb) {
1939 intel_wait_for_vblank(dev, intel_crtc->pipe);
1940 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
1941 }
1942
1943 intel_update_fbc(dev);
1944 mutex_unlock(&dev->struct_mutex);
1945
1946 if (!dev->primary->master)
1947 return 0;
1948
1949 master_priv = dev->primary->master->driver_priv;
1950 if (!master_priv->sarea_priv)
1951 return 0;
1952
1953 if (intel_crtc->pipe) {
1954 master_priv->sarea_priv->pipeB_x = x;
1955 master_priv->sarea_priv->pipeB_y = y;
1956 } else {
1957 master_priv->sarea_priv->pipeA_x = x;
1958 master_priv->sarea_priv->pipeA_y = y;
1959 }
1960
1961 return 0;
1962 }
1963
1964 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
1965 {
1966 struct drm_device *dev = crtc->dev;
1967 struct drm_i915_private *dev_priv = dev->dev_private;
1968 u32 dpa_ctl;
1969
1970 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1971 dpa_ctl = I915_READ(DP_A);
1972 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1973
1974 if (clock < 200000) {
1975 u32 temp;
1976 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1977 /* workaround for 160Mhz:
1978 1) program 0x4600c bits 15:0 = 0x8124
1979 2) program 0x46010 bit 0 = 1
1980 3) program 0x46034 bit 24 = 1
1981 4) program 0x64000 bit 14 = 1
1982 */
1983 temp = I915_READ(0x4600c);
1984 temp &= 0xffff0000;
1985 I915_WRITE(0x4600c, temp | 0x8124);
1986
1987 temp = I915_READ(0x46010);
1988 I915_WRITE(0x46010, temp | 1);
1989
1990 temp = I915_READ(0x46034);
1991 I915_WRITE(0x46034, temp | (1 << 24));
1992 } else {
1993 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1994 }
1995 I915_WRITE(DP_A, dpa_ctl);
1996
1997 POSTING_READ(DP_A);
1998 udelay(500);
1999 }
2000
2001 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2002 {
2003 struct drm_device *dev = crtc->dev;
2004 struct drm_i915_private *dev_priv = dev->dev_private;
2005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2006 int pipe = intel_crtc->pipe;
2007 u32 reg, temp;
2008
2009 /* enable normal train */
2010 reg = FDI_TX_CTL(pipe);
2011 temp = I915_READ(reg);
2012 if (IS_IVYBRIDGE(dev)) {
2013 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2014 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2015 } else {
2016 temp &= ~FDI_LINK_TRAIN_NONE;
2017 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2018 }
2019 I915_WRITE(reg, temp);
2020
2021 reg = FDI_RX_CTL(pipe);
2022 temp = I915_READ(reg);
2023 if (HAS_PCH_CPT(dev)) {
2024 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2025 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2026 } else {
2027 temp &= ~FDI_LINK_TRAIN_NONE;
2028 temp |= FDI_LINK_TRAIN_NONE;
2029 }
2030 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2031
2032 /* wait one idle pattern time */
2033 POSTING_READ(reg);
2034 udelay(1000);
2035
2036 /* IVB wants error correction enabled */
2037 if (IS_IVYBRIDGE(dev))
2038 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2039 FDI_FE_ERRC_ENABLE);
2040 }
2041
2042 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2043 {
2044 struct drm_i915_private *dev_priv = dev->dev_private;
2045 u32 flags = I915_READ(SOUTH_CHICKEN1);
2046
2047 flags |= FDI_PHASE_SYNC_OVR(pipe);
2048 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2049 flags |= FDI_PHASE_SYNC_EN(pipe);
2050 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2051 POSTING_READ(SOUTH_CHICKEN1);
2052 }
2053
2054 /* The FDI link training functions for ILK/Ibexpeak. */
2055 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2056 {
2057 struct drm_device *dev = crtc->dev;
2058 struct drm_i915_private *dev_priv = dev->dev_private;
2059 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2060 int pipe = intel_crtc->pipe;
2061 int plane = intel_crtc->plane;
2062 u32 reg, temp, tries;
2063
2064 /* FDI needs bits from pipe & plane first */
2065 assert_pipe_enabled(dev_priv, pipe);
2066 assert_plane_enabled(dev_priv, plane);
2067
2068 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2069 for train result */
2070 reg = FDI_RX_IMR(pipe);
2071 temp = I915_READ(reg);
2072 temp &= ~FDI_RX_SYMBOL_LOCK;
2073 temp &= ~FDI_RX_BIT_LOCK;
2074 I915_WRITE(reg, temp);
2075 I915_READ(reg);
2076 udelay(150);
2077
2078 /* enable CPU FDI TX and PCH FDI RX */
2079 reg = FDI_TX_CTL(pipe);
2080 temp = I915_READ(reg);
2081 temp &= ~(7 << 19);
2082 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2083 temp &= ~FDI_LINK_TRAIN_NONE;
2084 temp |= FDI_LINK_TRAIN_PATTERN_1;
2085 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2086
2087 reg = FDI_RX_CTL(pipe);
2088 temp = I915_READ(reg);
2089 temp &= ~FDI_LINK_TRAIN_NONE;
2090 temp |= FDI_LINK_TRAIN_PATTERN_1;
2091 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2092
2093 POSTING_READ(reg);
2094 udelay(150);
2095
2096 /* Ironlake workaround, enable clock pointer after FDI enable*/
2097 if (HAS_PCH_IBX(dev)) {
2098 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2099 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2100 FDI_RX_PHASE_SYNC_POINTER_EN);
2101 }
2102
2103 reg = FDI_RX_IIR(pipe);
2104 for (tries = 0; tries < 5; tries++) {
2105 temp = I915_READ(reg);
2106 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2107
2108 if ((temp & FDI_RX_BIT_LOCK)) {
2109 DRM_DEBUG_KMS("FDI train 1 done.\n");
2110 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2111 break;
2112 }
2113 }
2114 if (tries == 5)
2115 DRM_ERROR("FDI train 1 fail!\n");
2116
2117 /* Train 2 */
2118 reg = FDI_TX_CTL(pipe);
2119 temp = I915_READ(reg);
2120 temp &= ~FDI_LINK_TRAIN_NONE;
2121 temp |= FDI_LINK_TRAIN_PATTERN_2;
2122 I915_WRITE(reg, temp);
2123
2124 reg = FDI_RX_CTL(pipe);
2125 temp = I915_READ(reg);
2126 temp &= ~FDI_LINK_TRAIN_NONE;
2127 temp |= FDI_LINK_TRAIN_PATTERN_2;
2128 I915_WRITE(reg, temp);
2129
2130 POSTING_READ(reg);
2131 udelay(150);
2132
2133 reg = FDI_RX_IIR(pipe);
2134 for (tries = 0; tries < 5; tries++) {
2135 temp = I915_READ(reg);
2136 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2137
2138 if (temp & FDI_RX_SYMBOL_LOCK) {
2139 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2140 DRM_DEBUG_KMS("FDI train 2 done.\n");
2141 break;
2142 }
2143 }
2144 if (tries == 5)
2145 DRM_ERROR("FDI train 2 fail!\n");
2146
2147 DRM_DEBUG_KMS("FDI train done\n");
2148
2149 }
2150
2151 static const int snb_b_fdi_train_param[] = {
2152 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2153 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2154 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2155 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2156 };
2157
2158 /* The FDI link training functions for SNB/Cougarpoint. */
2159 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2160 {
2161 struct drm_device *dev = crtc->dev;
2162 struct drm_i915_private *dev_priv = dev->dev_private;
2163 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2164 int pipe = intel_crtc->pipe;
2165 u32 reg, temp, i, retry;
2166
2167 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2168 for train result */
2169 reg = FDI_RX_IMR(pipe);
2170 temp = I915_READ(reg);
2171 temp &= ~FDI_RX_SYMBOL_LOCK;
2172 temp &= ~FDI_RX_BIT_LOCK;
2173 I915_WRITE(reg, temp);
2174
2175 POSTING_READ(reg);
2176 udelay(150);
2177
2178 /* enable CPU FDI TX and PCH FDI RX */
2179 reg = FDI_TX_CTL(pipe);
2180 temp = I915_READ(reg);
2181 temp &= ~(7 << 19);
2182 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2183 temp &= ~FDI_LINK_TRAIN_NONE;
2184 temp |= FDI_LINK_TRAIN_PATTERN_1;
2185 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2186 /* SNB-B */
2187 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2188 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2189
2190 reg = FDI_RX_CTL(pipe);
2191 temp = I915_READ(reg);
2192 if (HAS_PCH_CPT(dev)) {
2193 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2194 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2195 } else {
2196 temp &= ~FDI_LINK_TRAIN_NONE;
2197 temp |= FDI_LINK_TRAIN_PATTERN_1;
2198 }
2199 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2200
2201 POSTING_READ(reg);
2202 udelay(150);
2203
2204 if (HAS_PCH_CPT(dev))
2205 cpt_phase_pointer_enable(dev, pipe);
2206
2207 for (i = 0; i < 4; i++) {
2208 reg = FDI_TX_CTL(pipe);
2209 temp = I915_READ(reg);
2210 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2211 temp |= snb_b_fdi_train_param[i];
2212 I915_WRITE(reg, temp);
2213
2214 POSTING_READ(reg);
2215 udelay(500);
2216
2217 for (retry = 0; retry < 5; retry++) {
2218 reg = FDI_RX_IIR(pipe);
2219 temp = I915_READ(reg);
2220 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2221 if (temp & FDI_RX_BIT_LOCK) {
2222 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2223 DRM_DEBUG_KMS("FDI train 1 done.\n");
2224 break;
2225 }
2226 udelay(50);
2227 }
2228 if (retry < 5)
2229 break;
2230 }
2231 if (i == 4)
2232 DRM_ERROR("FDI train 1 fail!\n");
2233
2234 /* Train 2 */
2235 reg = FDI_TX_CTL(pipe);
2236 temp = I915_READ(reg);
2237 temp &= ~FDI_LINK_TRAIN_NONE;
2238 temp |= FDI_LINK_TRAIN_PATTERN_2;
2239 if (IS_GEN6(dev)) {
2240 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2241 /* SNB-B */
2242 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2243 }
2244 I915_WRITE(reg, temp);
2245
2246 reg = FDI_RX_CTL(pipe);
2247 temp = I915_READ(reg);
2248 if (HAS_PCH_CPT(dev)) {
2249 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2250 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2251 } else {
2252 temp &= ~FDI_LINK_TRAIN_NONE;
2253 temp |= FDI_LINK_TRAIN_PATTERN_2;
2254 }
2255 I915_WRITE(reg, temp);
2256
2257 POSTING_READ(reg);
2258 udelay(150);
2259
2260 for (i = 0; i < 4; i++) {
2261 reg = FDI_TX_CTL(pipe);
2262 temp = I915_READ(reg);
2263 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2264 temp |= snb_b_fdi_train_param[i];
2265 I915_WRITE(reg, temp);
2266
2267 POSTING_READ(reg);
2268 udelay(500);
2269
2270 for (retry = 0; retry < 5; retry++) {
2271 reg = FDI_RX_IIR(pipe);
2272 temp = I915_READ(reg);
2273 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2274 if (temp & FDI_RX_SYMBOL_LOCK) {
2275 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2276 DRM_DEBUG_KMS("FDI train 2 done.\n");
2277 break;
2278 }
2279 udelay(50);
2280 }
2281 if (retry < 5)
2282 break;
2283 }
2284 if (i == 4)
2285 DRM_ERROR("FDI train 2 fail!\n");
2286
2287 DRM_DEBUG_KMS("FDI train done.\n");
2288 }
2289
2290 /* Manual link training for Ivy Bridge A0 parts */
2291 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2292 {
2293 struct drm_device *dev = crtc->dev;
2294 struct drm_i915_private *dev_priv = dev->dev_private;
2295 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2296 int pipe = intel_crtc->pipe;
2297 u32 reg, temp, i;
2298
2299 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2300 for train result */
2301 reg = FDI_RX_IMR(pipe);
2302 temp = I915_READ(reg);
2303 temp &= ~FDI_RX_SYMBOL_LOCK;
2304 temp &= ~FDI_RX_BIT_LOCK;
2305 I915_WRITE(reg, temp);
2306
2307 POSTING_READ(reg);
2308 udelay(150);
2309
2310 /* enable CPU FDI TX and PCH FDI RX */
2311 reg = FDI_TX_CTL(pipe);
2312 temp = I915_READ(reg);
2313 temp &= ~(7 << 19);
2314 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2315 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2316 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2317 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2318 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2319 temp |= FDI_COMPOSITE_SYNC;
2320 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2321
2322 reg = FDI_RX_CTL(pipe);
2323 temp = I915_READ(reg);
2324 temp &= ~FDI_LINK_TRAIN_AUTO;
2325 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2326 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2327 temp |= FDI_COMPOSITE_SYNC;
2328 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2329
2330 POSTING_READ(reg);
2331 udelay(150);
2332
2333 if (HAS_PCH_CPT(dev))
2334 cpt_phase_pointer_enable(dev, pipe);
2335
2336 for (i = 0; i < 4; i++) {
2337 reg = FDI_TX_CTL(pipe);
2338 temp = I915_READ(reg);
2339 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2340 temp |= snb_b_fdi_train_param[i];
2341 I915_WRITE(reg, temp);
2342
2343 POSTING_READ(reg);
2344 udelay(500);
2345
2346 reg = FDI_RX_IIR(pipe);
2347 temp = I915_READ(reg);
2348 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2349
2350 if (temp & FDI_RX_BIT_LOCK ||
2351 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2352 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2353 DRM_DEBUG_KMS("FDI train 1 done.\n");
2354 break;
2355 }
2356 }
2357 if (i == 4)
2358 DRM_ERROR("FDI train 1 fail!\n");
2359
2360 /* Train 2 */
2361 reg = FDI_TX_CTL(pipe);
2362 temp = I915_READ(reg);
2363 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2364 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2365 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2366 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2367 I915_WRITE(reg, temp);
2368
2369 reg = FDI_RX_CTL(pipe);
2370 temp = I915_READ(reg);
2371 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2372 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2373 I915_WRITE(reg, temp);
2374
2375 POSTING_READ(reg);
2376 udelay(150);
2377
2378 for (i = 0; i < 4; i++) {
2379 reg = FDI_TX_CTL(pipe);
2380 temp = I915_READ(reg);
2381 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2382 temp |= snb_b_fdi_train_param[i];
2383 I915_WRITE(reg, temp);
2384
2385 POSTING_READ(reg);
2386 udelay(500);
2387
2388 reg = FDI_RX_IIR(pipe);
2389 temp = I915_READ(reg);
2390 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2391
2392 if (temp & FDI_RX_SYMBOL_LOCK) {
2393 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2394 DRM_DEBUG_KMS("FDI train 2 done.\n");
2395 break;
2396 }
2397 }
2398 if (i == 4)
2399 DRM_ERROR("FDI train 2 fail!\n");
2400
2401 DRM_DEBUG_KMS("FDI train done.\n");
2402 }
2403
2404 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2405 {
2406 struct drm_device *dev = crtc->dev;
2407 struct drm_i915_private *dev_priv = dev->dev_private;
2408 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2409 int pipe = intel_crtc->pipe;
2410 u32 reg, temp;
2411
2412 /* Write the TU size bits so error detection works */
2413 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2414 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2415
2416 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2417 reg = FDI_RX_CTL(pipe);
2418 temp = I915_READ(reg);
2419 temp &= ~((0x7 << 19) | (0x7 << 16));
2420 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2421 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2422 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2423
2424 POSTING_READ(reg);
2425 udelay(200);
2426
2427 /* Switch from Rawclk to PCDclk */
2428 temp = I915_READ(reg);
2429 I915_WRITE(reg, temp | FDI_PCDCLK);
2430
2431 POSTING_READ(reg);
2432 udelay(200);
2433
2434 /* Enable CPU FDI TX PLL, always on for Ironlake */
2435 reg = FDI_TX_CTL(pipe);
2436 temp = I915_READ(reg);
2437 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2438 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2439
2440 POSTING_READ(reg);
2441 udelay(100);
2442 }
2443 }
2444
2445 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2446 {
2447 struct drm_i915_private *dev_priv = dev->dev_private;
2448 u32 flags = I915_READ(SOUTH_CHICKEN1);
2449
2450 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2451 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2452 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2453 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2454 POSTING_READ(SOUTH_CHICKEN1);
2455 }
2456 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2457 {
2458 struct drm_device *dev = crtc->dev;
2459 struct drm_i915_private *dev_priv = dev->dev_private;
2460 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2461 int pipe = intel_crtc->pipe;
2462 u32 reg, temp;
2463
2464 /* disable CPU FDI tx and PCH FDI rx */
2465 reg = FDI_TX_CTL(pipe);
2466 temp = I915_READ(reg);
2467 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2468 POSTING_READ(reg);
2469
2470 reg = FDI_RX_CTL(pipe);
2471 temp = I915_READ(reg);
2472 temp &= ~(0x7 << 16);
2473 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2474 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2475
2476 POSTING_READ(reg);
2477 udelay(100);
2478
2479 /* Ironlake workaround, disable clock pointer after downing FDI */
2480 if (HAS_PCH_IBX(dev)) {
2481 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2482 I915_WRITE(FDI_RX_CHICKEN(pipe),
2483 I915_READ(FDI_RX_CHICKEN(pipe) &
2484 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2485 } else if (HAS_PCH_CPT(dev)) {
2486 cpt_phase_pointer_disable(dev, pipe);
2487 }
2488
2489 /* still set train pattern 1 */
2490 reg = FDI_TX_CTL(pipe);
2491 temp = I915_READ(reg);
2492 temp &= ~FDI_LINK_TRAIN_NONE;
2493 temp |= FDI_LINK_TRAIN_PATTERN_1;
2494 I915_WRITE(reg, temp);
2495
2496 reg = FDI_RX_CTL(pipe);
2497 temp = I915_READ(reg);
2498 if (HAS_PCH_CPT(dev)) {
2499 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2500 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2501 } else {
2502 temp &= ~FDI_LINK_TRAIN_NONE;
2503 temp |= FDI_LINK_TRAIN_PATTERN_1;
2504 }
2505 /* BPC in FDI rx is consistent with that in PIPECONF */
2506 temp &= ~(0x07 << 16);
2507 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2508 I915_WRITE(reg, temp);
2509
2510 POSTING_READ(reg);
2511 udelay(100);
2512 }
2513
2514 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2515 {
2516 struct drm_device *dev = crtc->dev;
2517
2518 if (crtc->fb == NULL)
2519 return;
2520
2521 mutex_lock(&dev->struct_mutex);
2522 intel_finish_fb(crtc->fb);
2523 mutex_unlock(&dev->struct_mutex);
2524 }
2525
2526 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2527 {
2528 struct drm_device *dev = crtc->dev;
2529 struct drm_mode_config *mode_config = &dev->mode_config;
2530 struct intel_encoder *encoder;
2531
2532 /*
2533 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2534 * must be driven by its own crtc; no sharing is possible.
2535 */
2536 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2537 if (encoder->base.crtc != crtc)
2538 continue;
2539
2540 switch (encoder->type) {
2541 case INTEL_OUTPUT_EDP:
2542 if (!intel_encoder_is_pch_edp(&encoder->base))
2543 return false;
2544 continue;
2545 }
2546 }
2547
2548 return true;
2549 }
2550
2551 /*
2552 * Enable PCH resources required for PCH ports:
2553 * - PCH PLLs
2554 * - FDI training & RX/TX
2555 * - update transcoder timings
2556 * - DP transcoding bits
2557 * - transcoder
2558 */
2559 static void ironlake_pch_enable(struct drm_crtc *crtc)
2560 {
2561 struct drm_device *dev = crtc->dev;
2562 struct drm_i915_private *dev_priv = dev->dev_private;
2563 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2564 int pipe = intel_crtc->pipe;
2565 u32 reg, temp;
2566
2567 /* For PCH output, training FDI link */
2568 dev_priv->display.fdi_link_train(crtc);
2569
2570 intel_enable_pch_pll(intel_crtc);
2571
2572 if (HAS_PCH_CPT(dev)) {
2573 u32 sel;
2574
2575 temp = I915_READ(PCH_DPLL_SEL);
2576 switch (pipe) {
2577 default:
2578 case 0:
2579 temp |= TRANSA_DPLL_ENABLE;
2580 sel = TRANSA_DPLLB_SEL;
2581 break;
2582 case 1:
2583 temp |= TRANSB_DPLL_ENABLE;
2584 sel = TRANSB_DPLLB_SEL;
2585 break;
2586 case 2:
2587 temp |= TRANSC_DPLL_ENABLE;
2588 sel = TRANSC_DPLLB_SEL;
2589 break;
2590 }
2591 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2592 temp |= sel;
2593 else
2594 temp &= ~sel;
2595 I915_WRITE(PCH_DPLL_SEL, temp);
2596 }
2597
2598 /* set transcoder timing, panel must allow it */
2599 assert_panel_unlocked(dev_priv, pipe);
2600 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2601 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2602 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
2603
2604 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2605 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2606 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
2607 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
2608
2609 intel_fdi_normal_train(crtc);
2610
2611 /* For PCH DP, enable TRANS_DP_CTL */
2612 if (HAS_PCH_CPT(dev) &&
2613 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2614 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2615 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2616 reg = TRANS_DP_CTL(pipe);
2617 temp = I915_READ(reg);
2618 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2619 TRANS_DP_SYNC_MASK |
2620 TRANS_DP_BPC_MASK);
2621 temp |= (TRANS_DP_OUTPUT_ENABLE |
2622 TRANS_DP_ENH_FRAMING);
2623 temp |= bpc << 9; /* same format but at 11:9 */
2624
2625 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2626 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2627 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2628 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2629
2630 switch (intel_trans_dp_port_sel(crtc)) {
2631 case PCH_DP_B:
2632 temp |= TRANS_DP_PORT_SEL_B;
2633 break;
2634 case PCH_DP_C:
2635 temp |= TRANS_DP_PORT_SEL_C;
2636 break;
2637 case PCH_DP_D:
2638 temp |= TRANS_DP_PORT_SEL_D;
2639 break;
2640 default:
2641 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2642 temp |= TRANS_DP_PORT_SEL_B;
2643 break;
2644 }
2645
2646 I915_WRITE(reg, temp);
2647 }
2648
2649 intel_enable_transcoder(dev_priv, pipe);
2650 }
2651
2652 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
2653 {
2654 struct intel_pch_pll *pll = intel_crtc->pch_pll;
2655
2656 if (pll == NULL)
2657 return;
2658
2659 if (pll->refcount == 0) {
2660 WARN(1, "bad PCH PLL refcount\n");
2661 return;
2662 }
2663
2664 --pll->refcount;
2665 intel_crtc->pch_pll = NULL;
2666 }
2667
2668 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
2669 {
2670 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
2671 struct intel_pch_pll *pll;
2672 int i;
2673
2674 pll = intel_crtc->pch_pll;
2675 if (pll) {
2676 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
2677 intel_crtc->base.base.id, pll->pll_reg);
2678 goto prepare;
2679 }
2680
2681 for (i = 0; i < dev_priv->num_pch_pll; i++) {
2682 pll = &dev_priv->pch_plls[i];
2683
2684 /* Only want to check enabled timings first */
2685 if (pll->refcount == 0)
2686 continue;
2687
2688 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
2689 fp == I915_READ(pll->fp0_reg)) {
2690 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
2691 intel_crtc->base.base.id,
2692 pll->pll_reg, pll->refcount, pll->active);
2693
2694 goto found;
2695 }
2696 }
2697
2698 /* Ok no matching timings, maybe there's a free one? */
2699 for (i = 0; i < dev_priv->num_pch_pll; i++) {
2700 pll = &dev_priv->pch_plls[i];
2701 if (pll->refcount == 0) {
2702 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
2703 intel_crtc->base.base.id, pll->pll_reg);
2704 goto found;
2705 }
2706 }
2707
2708 return NULL;
2709
2710 found:
2711 intel_crtc->pch_pll = pll;
2712 pll->refcount++;
2713 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
2714 prepare: /* separate function? */
2715 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
2716
2717 /* Wait for the clocks to stabilize before rewriting the regs */
2718 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
2719 POSTING_READ(pll->pll_reg);
2720 udelay(150);
2721
2722 I915_WRITE(pll->fp0_reg, fp);
2723 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
2724 pll->on = false;
2725 return pll;
2726 }
2727
2728 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
2729 {
2730 struct drm_i915_private *dev_priv = dev->dev_private;
2731 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
2732 u32 temp;
2733
2734 temp = I915_READ(dslreg);
2735 udelay(500);
2736 if (wait_for(I915_READ(dslreg) != temp, 5)) {
2737 /* Without this, mode sets may fail silently on FDI */
2738 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
2739 udelay(250);
2740 I915_WRITE(tc2reg, 0);
2741 if (wait_for(I915_READ(dslreg) != temp, 5))
2742 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
2743 }
2744 }
2745
2746 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2747 {
2748 struct drm_device *dev = crtc->dev;
2749 struct drm_i915_private *dev_priv = dev->dev_private;
2750 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2751 int pipe = intel_crtc->pipe;
2752 int plane = intel_crtc->plane;
2753 u32 temp;
2754 bool is_pch_port;
2755
2756 if (intel_crtc->active)
2757 return;
2758
2759 intel_crtc->active = true;
2760 intel_update_watermarks(dev);
2761
2762 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2763 temp = I915_READ(PCH_LVDS);
2764 if ((temp & LVDS_PORT_EN) == 0)
2765 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2766 }
2767
2768 is_pch_port = intel_crtc_driving_pch(crtc);
2769
2770 if (is_pch_port)
2771 ironlake_fdi_pll_enable(crtc);
2772 else
2773 ironlake_fdi_disable(crtc);
2774
2775 /* Enable panel fitting for LVDS */
2776 if (dev_priv->pch_pf_size &&
2777 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2778 /* Force use of hard-coded filter coefficients
2779 * as some pre-programmed values are broken,
2780 * e.g. x201.
2781 */
2782 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2783 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2784 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
2785 }
2786
2787 /*
2788 * On ILK+ LUT must be loaded before the pipe is running but with
2789 * clocks enabled
2790 */
2791 intel_crtc_load_lut(crtc);
2792
2793 intel_enable_pipe(dev_priv, pipe, is_pch_port);
2794 intel_enable_plane(dev_priv, plane, pipe);
2795
2796 if (is_pch_port)
2797 ironlake_pch_enable(crtc);
2798
2799 mutex_lock(&dev->struct_mutex);
2800 intel_update_fbc(dev);
2801 mutex_unlock(&dev->struct_mutex);
2802
2803 intel_crtc_update_cursor(crtc, true);
2804 }
2805
2806 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2807 {
2808 struct drm_device *dev = crtc->dev;
2809 struct drm_i915_private *dev_priv = dev->dev_private;
2810 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2811 int pipe = intel_crtc->pipe;
2812 int plane = intel_crtc->plane;
2813 u32 reg, temp;
2814
2815 if (!intel_crtc->active)
2816 return;
2817
2818 intel_crtc_wait_for_pending_flips(crtc);
2819 drm_vblank_off(dev, pipe);
2820 intel_crtc_update_cursor(crtc, false);
2821
2822 intel_disable_plane(dev_priv, plane, pipe);
2823
2824 if (dev_priv->cfb_plane == plane)
2825 intel_disable_fbc(dev);
2826
2827 intel_disable_pipe(dev_priv, pipe);
2828
2829 /* Disable PF */
2830 I915_WRITE(PF_CTL(pipe), 0);
2831 I915_WRITE(PF_WIN_SZ(pipe), 0);
2832
2833 ironlake_fdi_disable(crtc);
2834
2835 /* This is a horrible layering violation; we should be doing this in
2836 * the connector/encoder ->prepare instead, but we don't always have
2837 * enough information there about the config to know whether it will
2838 * actually be necessary or just cause undesired flicker.
2839 */
2840 intel_disable_pch_ports(dev_priv, pipe);
2841
2842 intel_disable_transcoder(dev_priv, pipe);
2843
2844 if (HAS_PCH_CPT(dev)) {
2845 /* disable TRANS_DP_CTL */
2846 reg = TRANS_DP_CTL(pipe);
2847 temp = I915_READ(reg);
2848 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2849 temp |= TRANS_DP_PORT_SEL_NONE;
2850 I915_WRITE(reg, temp);
2851
2852 /* disable DPLL_SEL */
2853 temp = I915_READ(PCH_DPLL_SEL);
2854 switch (pipe) {
2855 case 0:
2856 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2857 break;
2858 case 1:
2859 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2860 break;
2861 case 2:
2862 /* C shares PLL A or B */
2863 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
2864 break;
2865 default:
2866 BUG(); /* wtf */
2867 }
2868 I915_WRITE(PCH_DPLL_SEL, temp);
2869 }
2870
2871 /* disable PCH DPLL */
2872 intel_disable_pch_pll(intel_crtc);
2873
2874 /* Switch from PCDclk to Rawclk */
2875 reg = FDI_RX_CTL(pipe);
2876 temp = I915_READ(reg);
2877 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2878
2879 /* Disable CPU FDI TX PLL */
2880 reg = FDI_TX_CTL(pipe);
2881 temp = I915_READ(reg);
2882 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2883
2884 POSTING_READ(reg);
2885 udelay(100);
2886
2887 reg = FDI_RX_CTL(pipe);
2888 temp = I915_READ(reg);
2889 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2890
2891 /* Wait for the clocks to turn off. */
2892 POSTING_READ(reg);
2893 udelay(100);
2894
2895 intel_crtc->active = false;
2896 intel_update_watermarks(dev);
2897
2898 mutex_lock(&dev->struct_mutex);
2899 intel_update_fbc(dev);
2900 mutex_unlock(&dev->struct_mutex);
2901 }
2902
2903 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2904 {
2905 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2906 int pipe = intel_crtc->pipe;
2907 int plane = intel_crtc->plane;
2908
2909 /* XXX: When our outputs are all unaware of DPMS modes other than off
2910 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2911 */
2912 switch (mode) {
2913 case DRM_MODE_DPMS_ON:
2914 case DRM_MODE_DPMS_STANDBY:
2915 case DRM_MODE_DPMS_SUSPEND:
2916 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2917 ironlake_crtc_enable(crtc);
2918 break;
2919
2920 case DRM_MODE_DPMS_OFF:
2921 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2922 ironlake_crtc_disable(crtc);
2923 break;
2924 }
2925 }
2926
2927 static void ironlake_crtc_off(struct drm_crtc *crtc)
2928 {
2929 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2930 intel_put_pch_pll(intel_crtc);
2931 }
2932
2933 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2934 {
2935 if (!enable && intel_crtc->overlay) {
2936 struct drm_device *dev = intel_crtc->base.dev;
2937 struct drm_i915_private *dev_priv = dev->dev_private;
2938
2939 mutex_lock(&dev->struct_mutex);
2940 dev_priv->mm.interruptible = false;
2941 (void) intel_overlay_switch_off(intel_crtc->overlay);
2942 dev_priv->mm.interruptible = true;
2943 mutex_unlock(&dev->struct_mutex);
2944 }
2945
2946 /* Let userspace switch the overlay on again. In most cases userspace
2947 * has to recompute where to put it anyway.
2948 */
2949 }
2950
2951 static void i9xx_crtc_enable(struct drm_crtc *crtc)
2952 {
2953 struct drm_device *dev = crtc->dev;
2954 struct drm_i915_private *dev_priv = dev->dev_private;
2955 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2956 int pipe = intel_crtc->pipe;
2957 int plane = intel_crtc->plane;
2958
2959 if (intel_crtc->active)
2960 return;
2961
2962 intel_crtc->active = true;
2963 intel_update_watermarks(dev);
2964
2965 intel_enable_pll(dev_priv, pipe);
2966 intel_enable_pipe(dev_priv, pipe, false);
2967 intel_enable_plane(dev_priv, plane, pipe);
2968
2969 intel_crtc_load_lut(crtc);
2970 intel_update_fbc(dev);
2971
2972 /* Give the overlay scaler a chance to enable if it's on this pipe */
2973 intel_crtc_dpms_overlay(intel_crtc, true);
2974 intel_crtc_update_cursor(crtc, true);
2975 }
2976
2977 static void i9xx_crtc_disable(struct drm_crtc *crtc)
2978 {
2979 struct drm_device *dev = crtc->dev;
2980 struct drm_i915_private *dev_priv = dev->dev_private;
2981 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2982 int pipe = intel_crtc->pipe;
2983 int plane = intel_crtc->plane;
2984
2985 if (!intel_crtc->active)
2986 return;
2987
2988 /* Give the overlay scaler a chance to disable if it's on this pipe */
2989 intel_crtc_wait_for_pending_flips(crtc);
2990 drm_vblank_off(dev, pipe);
2991 intel_crtc_dpms_overlay(intel_crtc, false);
2992 intel_crtc_update_cursor(crtc, false);
2993
2994 if (dev_priv->cfb_plane == plane)
2995 intel_disable_fbc(dev);
2996
2997 intel_disable_plane(dev_priv, plane, pipe);
2998 intel_disable_pipe(dev_priv, pipe);
2999 intel_disable_pll(dev_priv, pipe);
3000
3001 intel_crtc->active = false;
3002 intel_update_fbc(dev);
3003 intel_update_watermarks(dev);
3004 }
3005
3006 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3007 {
3008 /* XXX: When our outputs are all unaware of DPMS modes other than off
3009 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3010 */
3011 switch (mode) {
3012 case DRM_MODE_DPMS_ON:
3013 case DRM_MODE_DPMS_STANDBY:
3014 case DRM_MODE_DPMS_SUSPEND:
3015 i9xx_crtc_enable(crtc);
3016 break;
3017 case DRM_MODE_DPMS_OFF:
3018 i9xx_crtc_disable(crtc);
3019 break;
3020 }
3021 }
3022
3023 static void i9xx_crtc_off(struct drm_crtc *crtc)
3024 {
3025 }
3026
3027 /**
3028 * Sets the power management mode of the pipe and plane.
3029 */
3030 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3031 {
3032 struct drm_device *dev = crtc->dev;
3033 struct drm_i915_private *dev_priv = dev->dev_private;
3034 struct drm_i915_master_private *master_priv;
3035 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3036 int pipe = intel_crtc->pipe;
3037 bool enabled;
3038
3039 if (intel_crtc->dpms_mode == mode)
3040 return;
3041
3042 intel_crtc->dpms_mode = mode;
3043
3044 dev_priv->display.dpms(crtc, mode);
3045
3046 if (!dev->primary->master)
3047 return;
3048
3049 master_priv = dev->primary->master->driver_priv;
3050 if (!master_priv->sarea_priv)
3051 return;
3052
3053 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3054
3055 switch (pipe) {
3056 case 0:
3057 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3058 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3059 break;
3060 case 1:
3061 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3062 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3063 break;
3064 default:
3065 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3066 break;
3067 }
3068 }
3069
3070 static void intel_crtc_disable(struct drm_crtc *crtc)
3071 {
3072 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3073 struct drm_device *dev = crtc->dev;
3074 struct drm_i915_private *dev_priv = dev->dev_private;
3075
3076 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3077 dev_priv->display.off(crtc);
3078
3079 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3080 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3081
3082 if (crtc->fb) {
3083 mutex_lock(&dev->struct_mutex);
3084 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3085 mutex_unlock(&dev->struct_mutex);
3086 }
3087 }
3088
3089 /* Prepare for a mode set.
3090 *
3091 * Note we could be a lot smarter here. We need to figure out which outputs
3092 * will be enabled, which disabled (in short, how the config will changes)
3093 * and perform the minimum necessary steps to accomplish that, e.g. updating
3094 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3095 * panel fitting is in the proper state, etc.
3096 */
3097 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3098 {
3099 i9xx_crtc_disable(crtc);
3100 }
3101
3102 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3103 {
3104 i9xx_crtc_enable(crtc);
3105 }
3106
3107 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3108 {
3109 ironlake_crtc_disable(crtc);
3110 }
3111
3112 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3113 {
3114 ironlake_crtc_enable(crtc);
3115 }
3116
3117 void intel_encoder_prepare(struct drm_encoder *encoder)
3118 {
3119 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3120 /* lvds has its own version of prepare see intel_lvds_prepare */
3121 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3122 }
3123
3124 void intel_encoder_commit(struct drm_encoder *encoder)
3125 {
3126 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3127 struct drm_device *dev = encoder->dev;
3128 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
3129
3130 /* lvds has its own version of commit see intel_lvds_commit */
3131 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3132
3133 if (HAS_PCH_CPT(dev))
3134 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3135 }
3136
3137 void intel_encoder_destroy(struct drm_encoder *encoder)
3138 {
3139 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3140
3141 drm_encoder_cleanup(encoder);
3142 kfree(intel_encoder);
3143 }
3144
3145 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3146 struct drm_display_mode *mode,
3147 struct drm_display_mode *adjusted_mode)
3148 {
3149 struct drm_device *dev = crtc->dev;
3150
3151 if (HAS_PCH_SPLIT(dev)) {
3152 /* FDI link clock is fixed at 2.7G */
3153 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3154 return false;
3155 }
3156
3157 /* All interlaced capable intel hw wants timings in frames. Note though
3158 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3159 * timings, so we need to be careful not to clobber these.*/
3160 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3161 drm_mode_set_crtcinfo(adjusted_mode, 0);
3162
3163 return true;
3164 }
3165
3166 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3167 {
3168 return 400000; /* FIXME */
3169 }
3170
3171 static int i945_get_display_clock_speed(struct drm_device *dev)
3172 {
3173 return 400000;
3174 }
3175
3176 static int i915_get_display_clock_speed(struct drm_device *dev)
3177 {
3178 return 333000;
3179 }
3180
3181 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3182 {
3183 return 200000;
3184 }
3185
3186 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3187 {
3188 u16 gcfgc = 0;
3189
3190 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3191
3192 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3193 return 133000;
3194 else {
3195 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3196 case GC_DISPLAY_CLOCK_333_MHZ:
3197 return 333000;
3198 default:
3199 case GC_DISPLAY_CLOCK_190_200_MHZ:
3200 return 190000;
3201 }
3202 }
3203 }
3204
3205 static int i865_get_display_clock_speed(struct drm_device *dev)
3206 {
3207 return 266000;
3208 }
3209
3210 static int i855_get_display_clock_speed(struct drm_device *dev)
3211 {
3212 u16 hpllcc = 0;
3213 /* Assume that the hardware is in the high speed state. This
3214 * should be the default.
3215 */
3216 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3217 case GC_CLOCK_133_200:
3218 case GC_CLOCK_100_200:
3219 return 200000;
3220 case GC_CLOCK_166_250:
3221 return 250000;
3222 case GC_CLOCK_100_133:
3223 return 133000;
3224 }
3225
3226 /* Shouldn't happen */
3227 return 0;
3228 }
3229
3230 static int i830_get_display_clock_speed(struct drm_device *dev)
3231 {
3232 return 133000;
3233 }
3234
3235 struct fdi_m_n {
3236 u32 tu;
3237 u32 gmch_m;
3238 u32 gmch_n;
3239 u32 link_m;
3240 u32 link_n;
3241 };
3242
3243 static void
3244 fdi_reduce_ratio(u32 *num, u32 *den)
3245 {
3246 while (*num > 0xffffff || *den > 0xffffff) {
3247 *num >>= 1;
3248 *den >>= 1;
3249 }
3250 }
3251
3252 static void
3253 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3254 int link_clock, struct fdi_m_n *m_n)
3255 {
3256 m_n->tu = 64; /* default size */
3257
3258 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3259 m_n->gmch_m = bits_per_pixel * pixel_clock;
3260 m_n->gmch_n = link_clock * nlanes * 8;
3261 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3262
3263 m_n->link_m = pixel_clock;
3264 m_n->link_n = link_clock;
3265 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3266 }
3267
3268 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3269 {
3270 if (i915_panel_use_ssc >= 0)
3271 return i915_panel_use_ssc != 0;
3272 return dev_priv->lvds_use_ssc
3273 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
3274 }
3275
3276 /**
3277 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3278 * @crtc: CRTC structure
3279 * @mode: requested mode
3280 *
3281 * A pipe may be connected to one or more outputs. Based on the depth of the
3282 * attached framebuffer, choose a good color depth to use on the pipe.
3283 *
3284 * If possible, match the pipe depth to the fb depth. In some cases, this
3285 * isn't ideal, because the connected output supports a lesser or restricted
3286 * set of depths. Resolve that here:
3287 * LVDS typically supports only 6bpc, so clamp down in that case
3288 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3289 * Displays may support a restricted set as well, check EDID and clamp as
3290 * appropriate.
3291 * DP may want to dither down to 6bpc to fit larger modes
3292 *
3293 * RETURNS:
3294 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3295 * true if they don't match).
3296 */
3297 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3298 unsigned int *pipe_bpp,
3299 struct drm_display_mode *mode)
3300 {
3301 struct drm_device *dev = crtc->dev;
3302 struct drm_i915_private *dev_priv = dev->dev_private;
3303 struct drm_encoder *encoder;
3304 struct drm_connector *connector;
3305 unsigned int display_bpc = UINT_MAX, bpc;
3306
3307 /* Walk the encoders & connectors on this crtc, get min bpc */
3308 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3309 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3310
3311 if (encoder->crtc != crtc)
3312 continue;
3313
3314 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3315 unsigned int lvds_bpc;
3316
3317 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3318 LVDS_A3_POWER_UP)
3319 lvds_bpc = 8;
3320 else
3321 lvds_bpc = 6;
3322
3323 if (lvds_bpc < display_bpc) {
3324 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
3325 display_bpc = lvds_bpc;
3326 }
3327 continue;
3328 }
3329
3330 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
3331 /* Use VBT settings if we have an eDP panel */
3332 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
3333
3334 if (edp_bpc < display_bpc) {
3335 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
3336 display_bpc = edp_bpc;
3337 }
3338 continue;
3339 }
3340
3341 /* Not one of the known troublemakers, check the EDID */
3342 list_for_each_entry(connector, &dev->mode_config.connector_list,
3343 head) {
3344 if (connector->encoder != encoder)
3345 continue;
3346
3347 /* Don't use an invalid EDID bpc value */
3348 if (connector->display_info.bpc &&
3349 connector->display_info.bpc < display_bpc) {
3350 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
3351 display_bpc = connector->display_info.bpc;
3352 }
3353 }
3354
3355 /*
3356 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3357 * through, clamp it down. (Note: >12bpc will be caught below.)
3358 */
3359 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3360 if (display_bpc > 8 && display_bpc < 12) {
3361 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
3362 display_bpc = 12;
3363 } else {
3364 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
3365 display_bpc = 8;
3366 }
3367 }
3368 }
3369
3370 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3371 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3372 display_bpc = 6;
3373 }
3374
3375 /*
3376 * We could just drive the pipe at the highest bpc all the time and
3377 * enable dithering as needed, but that costs bandwidth. So choose
3378 * the minimum value that expresses the full color range of the fb but
3379 * also stays within the max display bpc discovered above.
3380 */
3381
3382 switch (crtc->fb->depth) {
3383 case 8:
3384 bpc = 8; /* since we go through a colormap */
3385 break;
3386 case 15:
3387 case 16:
3388 bpc = 6; /* min is 18bpp */
3389 break;
3390 case 24:
3391 bpc = 8;
3392 break;
3393 case 30:
3394 bpc = 10;
3395 break;
3396 case 48:
3397 bpc = 12;
3398 break;
3399 default:
3400 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3401 bpc = min((unsigned int)8, display_bpc);
3402 break;
3403 }
3404
3405 display_bpc = min(display_bpc, bpc);
3406
3407 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3408 bpc, display_bpc);
3409
3410 *pipe_bpp = display_bpc * 3;
3411
3412 return display_bpc != bpc;
3413 }
3414
3415 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3416 {
3417 struct drm_device *dev = crtc->dev;
3418 struct drm_i915_private *dev_priv = dev->dev_private;
3419 int refclk;
3420
3421 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3422 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3423 refclk = dev_priv->lvds_ssc_freq * 1000;
3424 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3425 refclk / 1000);
3426 } else if (!IS_GEN2(dev)) {
3427 refclk = 96000;
3428 } else {
3429 refclk = 48000;
3430 }
3431
3432 return refclk;
3433 }
3434
3435 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3436 intel_clock_t *clock)
3437 {
3438 /* SDVO TV has fixed PLL values depend on its clock range,
3439 this mirrors vbios setting. */
3440 if (adjusted_mode->clock >= 100000
3441 && adjusted_mode->clock < 140500) {
3442 clock->p1 = 2;
3443 clock->p2 = 10;
3444 clock->n = 3;
3445 clock->m1 = 16;
3446 clock->m2 = 8;
3447 } else if (adjusted_mode->clock >= 140500
3448 && adjusted_mode->clock <= 200000) {
3449 clock->p1 = 1;
3450 clock->p2 = 10;
3451 clock->n = 6;
3452 clock->m1 = 12;
3453 clock->m2 = 8;
3454 }
3455 }
3456
3457 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3458 intel_clock_t *clock,
3459 intel_clock_t *reduced_clock)
3460 {
3461 struct drm_device *dev = crtc->dev;
3462 struct drm_i915_private *dev_priv = dev->dev_private;
3463 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3464 int pipe = intel_crtc->pipe;
3465 u32 fp, fp2 = 0;
3466
3467 if (IS_PINEVIEW(dev)) {
3468 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3469 if (reduced_clock)
3470 fp2 = (1 << reduced_clock->n) << 16 |
3471 reduced_clock->m1 << 8 | reduced_clock->m2;
3472 } else {
3473 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3474 if (reduced_clock)
3475 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3476 reduced_clock->m2;
3477 }
3478
3479 I915_WRITE(FP0(pipe), fp);
3480
3481 intel_crtc->lowfreq_avail = false;
3482 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3483 reduced_clock && i915_powersave) {
3484 I915_WRITE(FP1(pipe), fp2);
3485 intel_crtc->lowfreq_avail = true;
3486 } else {
3487 I915_WRITE(FP1(pipe), fp);
3488 }
3489 }
3490
3491 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3492 struct drm_display_mode *adjusted_mode)
3493 {
3494 struct drm_device *dev = crtc->dev;
3495 struct drm_i915_private *dev_priv = dev->dev_private;
3496 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3497 int pipe = intel_crtc->pipe;
3498 u32 temp;
3499
3500 temp = I915_READ(LVDS);
3501 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3502 if (pipe == 1) {
3503 temp |= LVDS_PIPEB_SELECT;
3504 } else {
3505 temp &= ~LVDS_PIPEB_SELECT;
3506 }
3507 /* set the corresponsding LVDS_BORDER bit */
3508 temp |= dev_priv->lvds_border_bits;
3509 /* Set the B0-B3 data pairs corresponding to whether we're going to
3510 * set the DPLLs for dual-channel mode or not.
3511 */
3512 if (clock->p2 == 7)
3513 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3514 else
3515 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3516
3517 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3518 * appropriately here, but we need to look more thoroughly into how
3519 * panels behave in the two modes.
3520 */
3521 /* set the dithering flag on LVDS as needed */
3522 if (INTEL_INFO(dev)->gen >= 4) {
3523 if (dev_priv->lvds_dither)
3524 temp |= LVDS_ENABLE_DITHER;
3525 else
3526 temp &= ~LVDS_ENABLE_DITHER;
3527 }
3528 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
3529 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
3530 temp |= LVDS_HSYNC_POLARITY;
3531 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
3532 temp |= LVDS_VSYNC_POLARITY;
3533 I915_WRITE(LVDS, temp);
3534 }
3535
3536 static void i9xx_update_pll(struct drm_crtc *crtc,
3537 struct drm_display_mode *mode,
3538 struct drm_display_mode *adjusted_mode,
3539 intel_clock_t *clock, intel_clock_t *reduced_clock,
3540 int num_connectors)
3541 {
3542 struct drm_device *dev = crtc->dev;
3543 struct drm_i915_private *dev_priv = dev->dev_private;
3544 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3545 int pipe = intel_crtc->pipe;
3546 u32 dpll;
3547 bool is_sdvo;
3548
3549 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
3550 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
3551
3552 dpll = DPLL_VGA_MODE_DIS;
3553
3554 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3555 dpll |= DPLLB_MODE_LVDS;
3556 else
3557 dpll |= DPLLB_MODE_DAC_SERIAL;
3558 if (is_sdvo) {
3559 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3560 if (pixel_multiplier > 1) {
3561 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3562 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3563 }
3564 dpll |= DPLL_DVO_HIGH_SPEED;
3565 }
3566 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
3567 dpll |= DPLL_DVO_HIGH_SPEED;
3568
3569 /* compute bitmask from p1 value */
3570 if (IS_PINEVIEW(dev))
3571 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3572 else {
3573 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3574 if (IS_G4X(dev) && reduced_clock)
3575 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3576 }
3577 switch (clock->p2) {
3578 case 5:
3579 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3580 break;
3581 case 7:
3582 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3583 break;
3584 case 10:
3585 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3586 break;
3587 case 14:
3588 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3589 break;
3590 }
3591 if (INTEL_INFO(dev)->gen >= 4)
3592 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3593
3594 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3595 dpll |= PLL_REF_INPUT_TVCLKINBC;
3596 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3597 /* XXX: just matching BIOS for now */
3598 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3599 dpll |= 3;
3600 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3601 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3602 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3603 else
3604 dpll |= PLL_REF_INPUT_DREFCLK;
3605
3606 dpll |= DPLL_VCO_ENABLE;
3607 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3608 POSTING_READ(DPLL(pipe));
3609 udelay(150);
3610
3611 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3612 * This is an exception to the general rule that mode_set doesn't turn
3613 * things on.
3614 */
3615 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3616 intel_update_lvds(crtc, clock, adjusted_mode);
3617
3618 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
3619 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3620
3621 I915_WRITE(DPLL(pipe), dpll);
3622
3623 /* Wait for the clocks to stabilize. */
3624 POSTING_READ(DPLL(pipe));
3625 udelay(150);
3626
3627 if (INTEL_INFO(dev)->gen >= 4) {
3628 u32 temp = 0;
3629 if (is_sdvo) {
3630 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
3631 if (temp > 1)
3632 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
3633 else
3634 temp = 0;
3635 }
3636 I915_WRITE(DPLL_MD(pipe), temp);
3637 } else {
3638 /* The pixel multiplier can only be updated once the
3639 * DPLL is enabled and the clocks are stable.
3640 *
3641 * So write it again.
3642 */
3643 I915_WRITE(DPLL(pipe), dpll);
3644 }
3645 }
3646
3647 static void i8xx_update_pll(struct drm_crtc *crtc,
3648 struct drm_display_mode *adjusted_mode,
3649 intel_clock_t *clock,
3650 int num_connectors)
3651 {
3652 struct drm_device *dev = crtc->dev;
3653 struct drm_i915_private *dev_priv = dev->dev_private;
3654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3655 int pipe = intel_crtc->pipe;
3656 u32 dpll;
3657
3658 dpll = DPLL_VGA_MODE_DIS;
3659
3660 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3661 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3662 } else {
3663 if (clock->p1 == 2)
3664 dpll |= PLL_P1_DIVIDE_BY_TWO;
3665 else
3666 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3667 if (clock->p2 == 4)
3668 dpll |= PLL_P2_DIVIDE_BY_4;
3669 }
3670
3671 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3672 /* XXX: just matching BIOS for now */
3673 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3674 dpll |= 3;
3675 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3676 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3677 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3678 else
3679 dpll |= PLL_REF_INPUT_DREFCLK;
3680
3681 dpll |= DPLL_VCO_ENABLE;
3682 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3683 POSTING_READ(DPLL(pipe));
3684 udelay(150);
3685
3686 I915_WRITE(DPLL(pipe), dpll);
3687
3688 /* Wait for the clocks to stabilize. */
3689 POSTING_READ(DPLL(pipe));
3690 udelay(150);
3691
3692 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3693 * This is an exception to the general rule that mode_set doesn't turn
3694 * things on.
3695 */
3696 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3697 intel_update_lvds(crtc, clock, adjusted_mode);
3698
3699 /* The pixel multiplier can only be updated once the
3700 * DPLL is enabled and the clocks are stable.
3701 *
3702 * So write it again.
3703 */
3704 I915_WRITE(DPLL(pipe), dpll);
3705 }
3706
3707 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
3708 struct drm_display_mode *mode,
3709 struct drm_display_mode *adjusted_mode,
3710 int x, int y,
3711 struct drm_framebuffer *old_fb)
3712 {
3713 struct drm_device *dev = crtc->dev;
3714 struct drm_i915_private *dev_priv = dev->dev_private;
3715 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3716 int pipe = intel_crtc->pipe;
3717 int plane = intel_crtc->plane;
3718 int refclk, num_connectors = 0;
3719 intel_clock_t clock, reduced_clock;
3720 u32 dspcntr, pipeconf, vsyncshift;
3721 bool ok, has_reduced_clock = false, is_sdvo = false;
3722 bool is_lvds = false, is_tv = false, is_dp = false;
3723 struct drm_mode_config *mode_config = &dev->mode_config;
3724 struct intel_encoder *encoder;
3725 const intel_limit_t *limit;
3726 int ret;
3727
3728 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3729 if (encoder->base.crtc != crtc)
3730 continue;
3731
3732 switch (encoder->type) {
3733 case INTEL_OUTPUT_LVDS:
3734 is_lvds = true;
3735 break;
3736 case INTEL_OUTPUT_SDVO:
3737 case INTEL_OUTPUT_HDMI:
3738 is_sdvo = true;
3739 if (encoder->needs_tv_clock)
3740 is_tv = true;
3741 break;
3742 case INTEL_OUTPUT_TVOUT:
3743 is_tv = true;
3744 break;
3745 case INTEL_OUTPUT_DISPLAYPORT:
3746 is_dp = true;
3747 break;
3748 }
3749
3750 num_connectors++;
3751 }
3752
3753 refclk = i9xx_get_refclk(crtc, num_connectors);
3754
3755 /*
3756 * Returns a set of divisors for the desired target clock with the given
3757 * refclk, or FALSE. The returned values represent the clock equation:
3758 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3759 */
3760 limit = intel_limit(crtc, refclk);
3761 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
3762 &clock);
3763 if (!ok) {
3764 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3765 return -EINVAL;
3766 }
3767
3768 /* Ensure that the cursor is valid for the new mode before changing... */
3769 intel_crtc_update_cursor(crtc, true);
3770
3771 if (is_lvds && dev_priv->lvds_downclock_avail) {
3772 /*
3773 * Ensure we match the reduced clock's P to the target clock.
3774 * If the clocks don't match, we can't switch the display clock
3775 * by using the FP0/FP1. In such case we will disable the LVDS
3776 * downclock feature.
3777 */
3778 has_reduced_clock = limit->find_pll(limit, crtc,
3779 dev_priv->lvds_downclock,
3780 refclk,
3781 &clock,
3782 &reduced_clock);
3783 }
3784
3785 if (is_sdvo && is_tv)
3786 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
3787
3788 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
3789 &reduced_clock : NULL);
3790
3791 if (IS_GEN2(dev))
3792 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
3793 else
3794 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
3795 has_reduced_clock ? &reduced_clock : NULL,
3796 num_connectors);
3797
3798 /* setup pipeconf */
3799 pipeconf = I915_READ(PIPECONF(pipe));
3800
3801 /* Set up the display plane register */
3802 dspcntr = DISPPLANE_GAMMA_ENABLE;
3803
3804 if (pipe == 0)
3805 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3806 else
3807 dspcntr |= DISPPLANE_SEL_PIPE_B;
3808
3809 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
3810 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3811 * core speed.
3812 *
3813 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3814 * pipe == 0 check?
3815 */
3816 if (mode->clock >
3817 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3818 pipeconf |= PIPECONF_DOUBLE_WIDE;
3819 else
3820 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
3821 }
3822
3823 /* default to 8bpc */
3824 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
3825 if (is_dp) {
3826 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3827 pipeconf |= PIPECONF_BPP_6 |
3828 PIPECONF_DITHER_EN |
3829 PIPECONF_DITHER_TYPE_SP;
3830 }
3831 }
3832
3833 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3834 drm_mode_debug_printmodeline(mode);
3835
3836 if (HAS_PIPE_CXSR(dev)) {
3837 if (intel_crtc->lowfreq_avail) {
3838 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3839 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3840 } else {
3841 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3842 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3843 }
3844 }
3845
3846 pipeconf &= ~PIPECONF_INTERLACE_MASK;
3847 if (!IS_GEN2(dev) &&
3848 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
3849 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
3850 /* the chip adds 2 halflines automatically */
3851 adjusted_mode->crtc_vtotal -= 1;
3852 adjusted_mode->crtc_vblank_end -= 1;
3853 vsyncshift = adjusted_mode->crtc_hsync_start
3854 - adjusted_mode->crtc_htotal/2;
3855 } else {
3856 pipeconf |= PIPECONF_PROGRESSIVE;
3857 vsyncshift = 0;
3858 }
3859
3860 if (!IS_GEN3(dev))
3861 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
3862
3863 I915_WRITE(HTOTAL(pipe),
3864 (adjusted_mode->crtc_hdisplay - 1) |
3865 ((adjusted_mode->crtc_htotal - 1) << 16));
3866 I915_WRITE(HBLANK(pipe),
3867 (adjusted_mode->crtc_hblank_start - 1) |
3868 ((adjusted_mode->crtc_hblank_end - 1) << 16));
3869 I915_WRITE(HSYNC(pipe),
3870 (adjusted_mode->crtc_hsync_start - 1) |
3871 ((adjusted_mode->crtc_hsync_end - 1) << 16));
3872
3873 I915_WRITE(VTOTAL(pipe),
3874 (adjusted_mode->crtc_vdisplay - 1) |
3875 ((adjusted_mode->crtc_vtotal - 1) << 16));
3876 I915_WRITE(VBLANK(pipe),
3877 (adjusted_mode->crtc_vblank_start - 1) |
3878 ((adjusted_mode->crtc_vblank_end - 1) << 16));
3879 I915_WRITE(VSYNC(pipe),
3880 (adjusted_mode->crtc_vsync_start - 1) |
3881 ((adjusted_mode->crtc_vsync_end - 1) << 16));
3882
3883 /* pipesrc and dspsize control the size that is scaled from,
3884 * which should always be the user's requested size.
3885 */
3886 I915_WRITE(DSPSIZE(plane),
3887 ((mode->vdisplay - 1) << 16) |
3888 (mode->hdisplay - 1));
3889 I915_WRITE(DSPPOS(plane), 0);
3890 I915_WRITE(PIPESRC(pipe),
3891 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
3892
3893 I915_WRITE(PIPECONF(pipe), pipeconf);
3894 POSTING_READ(PIPECONF(pipe));
3895 intel_enable_pipe(dev_priv, pipe, false);
3896
3897 intel_wait_for_vblank(dev, pipe);
3898
3899 I915_WRITE(DSPCNTR(plane), dspcntr);
3900 POSTING_READ(DSPCNTR(plane));
3901
3902 ret = intel_pipe_set_base(crtc, x, y, old_fb);
3903
3904 intel_update_watermarks(dev);
3905
3906 return ret;
3907 }
3908
3909 /*
3910 * Initialize reference clocks when the driver loads
3911 */
3912 void ironlake_init_pch_refclk(struct drm_device *dev)
3913 {
3914 struct drm_i915_private *dev_priv = dev->dev_private;
3915 struct drm_mode_config *mode_config = &dev->mode_config;
3916 struct intel_encoder *encoder;
3917 u32 temp;
3918 bool has_lvds = false;
3919 bool has_cpu_edp = false;
3920 bool has_pch_edp = false;
3921 bool has_panel = false;
3922 bool has_ck505 = false;
3923 bool can_ssc = false;
3924
3925 /* We need to take the global config into account */
3926 list_for_each_entry(encoder, &mode_config->encoder_list,
3927 base.head) {
3928 switch (encoder->type) {
3929 case INTEL_OUTPUT_LVDS:
3930 has_panel = true;
3931 has_lvds = true;
3932 break;
3933 case INTEL_OUTPUT_EDP:
3934 has_panel = true;
3935 if (intel_encoder_is_pch_edp(&encoder->base))
3936 has_pch_edp = true;
3937 else
3938 has_cpu_edp = true;
3939 break;
3940 }
3941 }
3942
3943 if (HAS_PCH_IBX(dev)) {
3944 has_ck505 = dev_priv->display_clock_mode;
3945 can_ssc = has_ck505;
3946 } else {
3947 has_ck505 = false;
3948 can_ssc = true;
3949 }
3950
3951 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
3952 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
3953 has_ck505);
3954
3955 /* Ironlake: try to setup display ref clock before DPLL
3956 * enabling. This is only under driver's control after
3957 * PCH B stepping, previous chipset stepping should be
3958 * ignoring this setting.
3959 */
3960 temp = I915_READ(PCH_DREF_CONTROL);
3961 /* Always enable nonspread source */
3962 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3963
3964 if (has_ck505)
3965 temp |= DREF_NONSPREAD_CK505_ENABLE;
3966 else
3967 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3968
3969 if (has_panel) {
3970 temp &= ~DREF_SSC_SOURCE_MASK;
3971 temp |= DREF_SSC_SOURCE_ENABLE;
3972
3973 /* SSC must be turned on before enabling the CPU output */
3974 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
3975 DRM_DEBUG_KMS("Using SSC on panel\n");
3976 temp |= DREF_SSC1_ENABLE;
3977 } else
3978 temp &= ~DREF_SSC1_ENABLE;
3979
3980 /* Get SSC going before enabling the outputs */
3981 I915_WRITE(PCH_DREF_CONTROL, temp);
3982 POSTING_READ(PCH_DREF_CONTROL);
3983 udelay(200);
3984
3985 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3986
3987 /* Enable CPU source on CPU attached eDP */
3988 if (has_cpu_edp) {
3989 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
3990 DRM_DEBUG_KMS("Using SSC on eDP\n");
3991 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3992 }
3993 else
3994 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3995 } else
3996 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
3997
3998 I915_WRITE(PCH_DREF_CONTROL, temp);
3999 POSTING_READ(PCH_DREF_CONTROL);
4000 udelay(200);
4001 } else {
4002 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4003
4004 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4005
4006 /* Turn off CPU output */
4007 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4008
4009 I915_WRITE(PCH_DREF_CONTROL, temp);
4010 POSTING_READ(PCH_DREF_CONTROL);
4011 udelay(200);
4012
4013 /* Turn off the SSC source */
4014 temp &= ~DREF_SSC_SOURCE_MASK;
4015 temp |= DREF_SSC_SOURCE_DISABLE;
4016
4017 /* Turn off SSC1 */
4018 temp &= ~ DREF_SSC1_ENABLE;
4019
4020 I915_WRITE(PCH_DREF_CONTROL, temp);
4021 POSTING_READ(PCH_DREF_CONTROL);
4022 udelay(200);
4023 }
4024 }
4025
4026 static int ironlake_get_refclk(struct drm_crtc *crtc)
4027 {
4028 struct drm_device *dev = crtc->dev;
4029 struct drm_i915_private *dev_priv = dev->dev_private;
4030 struct intel_encoder *encoder;
4031 struct drm_mode_config *mode_config = &dev->mode_config;
4032 struct intel_encoder *edp_encoder = NULL;
4033 int num_connectors = 0;
4034 bool is_lvds = false;
4035
4036 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4037 if (encoder->base.crtc != crtc)
4038 continue;
4039
4040 switch (encoder->type) {
4041 case INTEL_OUTPUT_LVDS:
4042 is_lvds = true;
4043 break;
4044 case INTEL_OUTPUT_EDP:
4045 edp_encoder = encoder;
4046 break;
4047 }
4048 num_connectors++;
4049 }
4050
4051 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4052 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4053 dev_priv->lvds_ssc_freq);
4054 return dev_priv->lvds_ssc_freq * 1000;
4055 }
4056
4057 return 120000;
4058 }
4059
4060 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4061 struct drm_display_mode *mode,
4062 struct drm_display_mode *adjusted_mode,
4063 int x, int y,
4064 struct drm_framebuffer *old_fb)
4065 {
4066 struct drm_device *dev = crtc->dev;
4067 struct drm_i915_private *dev_priv = dev->dev_private;
4068 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4069 int pipe = intel_crtc->pipe;
4070 int plane = intel_crtc->plane;
4071 int refclk, num_connectors = 0;
4072 intel_clock_t clock, reduced_clock;
4073 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4074 bool ok, has_reduced_clock = false, is_sdvo = false;
4075 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4076 struct drm_mode_config *mode_config = &dev->mode_config;
4077 struct intel_encoder *encoder, *edp_encoder = NULL;
4078 const intel_limit_t *limit;
4079 int ret;
4080 struct fdi_m_n m_n = {0};
4081 u32 temp;
4082 int target_clock, pixel_multiplier, lane, link_bw, factor;
4083 unsigned int pipe_bpp;
4084 bool dither;
4085 bool is_cpu_edp = false, is_pch_edp = false;
4086
4087 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4088 if (encoder->base.crtc != crtc)
4089 continue;
4090
4091 switch (encoder->type) {
4092 case INTEL_OUTPUT_LVDS:
4093 is_lvds = true;
4094 break;
4095 case INTEL_OUTPUT_SDVO:
4096 case INTEL_OUTPUT_HDMI:
4097 is_sdvo = true;
4098 if (encoder->needs_tv_clock)
4099 is_tv = true;
4100 break;
4101 case INTEL_OUTPUT_TVOUT:
4102 is_tv = true;
4103 break;
4104 case INTEL_OUTPUT_ANALOG:
4105 is_crt = true;
4106 break;
4107 case INTEL_OUTPUT_DISPLAYPORT:
4108 is_dp = true;
4109 break;
4110 case INTEL_OUTPUT_EDP:
4111 is_dp = true;
4112 if (intel_encoder_is_pch_edp(&encoder->base))
4113 is_pch_edp = true;
4114 else
4115 is_cpu_edp = true;
4116 edp_encoder = encoder;
4117 break;
4118 }
4119
4120 num_connectors++;
4121 }
4122
4123 refclk = ironlake_get_refclk(crtc);
4124
4125 /*
4126 * Returns a set of divisors for the desired target clock with the given
4127 * refclk, or FALSE. The returned values represent the clock equation:
4128 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4129 */
4130 limit = intel_limit(crtc, refclk);
4131 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4132 &clock);
4133 if (!ok) {
4134 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4135 return -EINVAL;
4136 }
4137
4138 /* Ensure that the cursor is valid for the new mode before changing... */
4139 intel_crtc_update_cursor(crtc, true);
4140
4141 if (is_lvds && dev_priv->lvds_downclock_avail) {
4142 /*
4143 * Ensure we match the reduced clock's P to the target clock.
4144 * If the clocks don't match, we can't switch the display clock
4145 * by using the FP0/FP1. In such case we will disable the LVDS
4146 * downclock feature.
4147 */
4148 has_reduced_clock = limit->find_pll(limit, crtc,
4149 dev_priv->lvds_downclock,
4150 refclk,
4151 &clock,
4152 &reduced_clock);
4153 }
4154 /* SDVO TV has fixed PLL values depend on its clock range,
4155 this mirrors vbios setting. */
4156 if (is_sdvo && is_tv) {
4157 if (adjusted_mode->clock >= 100000
4158 && adjusted_mode->clock < 140500) {
4159 clock.p1 = 2;
4160 clock.p2 = 10;
4161 clock.n = 3;
4162 clock.m1 = 16;
4163 clock.m2 = 8;
4164 } else if (adjusted_mode->clock >= 140500
4165 && adjusted_mode->clock <= 200000) {
4166 clock.p1 = 1;
4167 clock.p2 = 10;
4168 clock.n = 6;
4169 clock.m1 = 12;
4170 clock.m2 = 8;
4171 }
4172 }
4173
4174 /* FDI link */
4175 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4176 lane = 0;
4177 /* CPU eDP doesn't require FDI link, so just set DP M/N
4178 according to current link config */
4179 if (is_cpu_edp) {
4180 target_clock = mode->clock;
4181 intel_edp_link_config(edp_encoder, &lane, &link_bw);
4182 } else {
4183 /* [e]DP over FDI requires target mode clock
4184 instead of link clock */
4185 if (is_dp)
4186 target_clock = mode->clock;
4187 else
4188 target_clock = adjusted_mode->clock;
4189
4190 /* FDI is a binary signal running at ~2.7GHz, encoding
4191 * each output octet as 10 bits. The actual frequency
4192 * is stored as a divider into a 100MHz clock, and the
4193 * mode pixel clock is stored in units of 1KHz.
4194 * Hence the bw of each lane in terms of the mode signal
4195 * is:
4196 */
4197 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4198 }
4199
4200 /* determine panel color depth */
4201 temp = I915_READ(PIPECONF(pipe));
4202 temp &= ~PIPE_BPC_MASK;
4203 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
4204 switch (pipe_bpp) {
4205 case 18:
4206 temp |= PIPE_6BPC;
4207 break;
4208 case 24:
4209 temp |= PIPE_8BPC;
4210 break;
4211 case 30:
4212 temp |= PIPE_10BPC;
4213 break;
4214 case 36:
4215 temp |= PIPE_12BPC;
4216 break;
4217 default:
4218 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4219 pipe_bpp);
4220 temp |= PIPE_8BPC;
4221 pipe_bpp = 24;
4222 break;
4223 }
4224
4225 intel_crtc->bpp = pipe_bpp;
4226 I915_WRITE(PIPECONF(pipe), temp);
4227
4228 if (!lane) {
4229 /*
4230 * Account for spread spectrum to avoid
4231 * oversubscribing the link. Max center spread
4232 * is 2.5%; use 5% for safety's sake.
4233 */
4234 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
4235 lane = bps / (link_bw * 8) + 1;
4236 }
4237
4238 intel_crtc->fdi_lanes = lane;
4239
4240 if (pixel_multiplier > 1)
4241 link_bw *= pixel_multiplier;
4242 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4243 &m_n);
4244
4245 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4246 if (has_reduced_clock)
4247 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4248 reduced_clock.m2;
4249
4250 /* Enable autotuning of the PLL clock (if permissible) */
4251 factor = 21;
4252 if (is_lvds) {
4253 if ((intel_panel_use_ssc(dev_priv) &&
4254 dev_priv->lvds_ssc_freq == 100) ||
4255 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4256 factor = 25;
4257 } else if (is_sdvo && is_tv)
4258 factor = 20;
4259
4260 if (clock.m < factor * clock.n)
4261 fp |= FP_CB_TUNE;
4262
4263 dpll = 0;
4264
4265 if (is_lvds)
4266 dpll |= DPLLB_MODE_LVDS;
4267 else
4268 dpll |= DPLLB_MODE_DAC_SERIAL;
4269 if (is_sdvo) {
4270 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4271 if (pixel_multiplier > 1) {
4272 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4273 }
4274 dpll |= DPLL_DVO_HIGH_SPEED;
4275 }
4276 if (is_dp && !is_cpu_edp)
4277 dpll |= DPLL_DVO_HIGH_SPEED;
4278
4279 /* compute bitmask from p1 value */
4280 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4281 /* also FPA1 */
4282 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4283
4284 switch (clock.p2) {
4285 case 5:
4286 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4287 break;
4288 case 7:
4289 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4290 break;
4291 case 10:
4292 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4293 break;
4294 case 14:
4295 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4296 break;
4297 }
4298
4299 if (is_sdvo && is_tv)
4300 dpll |= PLL_REF_INPUT_TVCLKINBC;
4301 else if (is_tv)
4302 /* XXX: just matching BIOS for now */
4303 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4304 dpll |= 3;
4305 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4306 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4307 else
4308 dpll |= PLL_REF_INPUT_DREFCLK;
4309
4310 /* setup pipeconf */
4311 pipeconf = I915_READ(PIPECONF(pipe));
4312
4313 /* Set up the display plane register */
4314 dspcntr = DISPPLANE_GAMMA_ENABLE;
4315
4316 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
4317 drm_mode_debug_printmodeline(mode);
4318
4319 /* CPU eDP is the only output that doesn't need a PCH PLL of its own */
4320 if (!is_cpu_edp) {
4321 struct intel_pch_pll *pll;
4322
4323 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4324 if (pll == NULL) {
4325 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4326 pipe);
4327 return -EINVAL;
4328 }
4329 } else
4330 intel_put_pch_pll(intel_crtc);
4331
4332 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4333 * This is an exception to the general rule that mode_set doesn't turn
4334 * things on.
4335 */
4336 if (is_lvds) {
4337 temp = I915_READ(PCH_LVDS);
4338 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4339 if (HAS_PCH_CPT(dev)) {
4340 temp &= ~PORT_TRANS_SEL_MASK;
4341 temp |= PORT_TRANS_SEL_CPT(pipe);
4342 } else {
4343 if (pipe == 1)
4344 temp |= LVDS_PIPEB_SELECT;
4345 else
4346 temp &= ~LVDS_PIPEB_SELECT;
4347 }
4348
4349 /* set the corresponsding LVDS_BORDER bit */
4350 temp |= dev_priv->lvds_border_bits;
4351 /* Set the B0-B3 data pairs corresponding to whether we're going to
4352 * set the DPLLs for dual-channel mode or not.
4353 */
4354 if (clock.p2 == 7)
4355 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4356 else
4357 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4358
4359 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4360 * appropriately here, but we need to look more thoroughly into how
4361 * panels behave in the two modes.
4362 */
4363 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4364 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4365 temp |= LVDS_HSYNC_POLARITY;
4366 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4367 temp |= LVDS_VSYNC_POLARITY;
4368 I915_WRITE(PCH_LVDS, temp);
4369 }
4370
4371 pipeconf &= ~PIPECONF_DITHER_EN;
4372 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4373 if ((is_lvds && dev_priv->lvds_dither) || dither) {
4374 pipeconf |= PIPECONF_DITHER_EN;
4375 pipeconf |= PIPECONF_DITHER_TYPE_SP;
4376 }
4377 if (is_dp && !is_cpu_edp) {
4378 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4379 } else {
4380 /* For non-DP output, clear any trans DP clock recovery setting.*/
4381 I915_WRITE(TRANSDATA_M1(pipe), 0);
4382 I915_WRITE(TRANSDATA_N1(pipe), 0);
4383 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4384 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
4385 }
4386
4387 if (intel_crtc->pch_pll) {
4388 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4389
4390 /* Wait for the clocks to stabilize. */
4391 POSTING_READ(intel_crtc->pch_pll->pll_reg);
4392 udelay(150);
4393
4394 /* The pixel multiplier can only be updated once the
4395 * DPLL is enabled and the clocks are stable.
4396 *
4397 * So write it again.
4398 */
4399 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4400 }
4401
4402 intel_crtc->lowfreq_avail = false;
4403 if (intel_crtc->pch_pll) {
4404 if (is_lvds && has_reduced_clock && i915_powersave) {
4405 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4406 intel_crtc->lowfreq_avail = true;
4407 if (HAS_PIPE_CXSR(dev)) {
4408 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4409 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4410 }
4411 } else {
4412 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
4413 if (HAS_PIPE_CXSR(dev)) {
4414 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4415 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4416 }
4417 }
4418 }
4419
4420 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4421 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4422 pipeconf |= PIPECONF_INTERLACED_ILK;
4423 /* the chip adds 2 halflines automatically */
4424 adjusted_mode->crtc_vtotal -= 1;
4425 adjusted_mode->crtc_vblank_end -= 1;
4426 I915_WRITE(VSYNCSHIFT(pipe),
4427 adjusted_mode->crtc_hsync_start
4428 - adjusted_mode->crtc_htotal/2);
4429 } else {
4430 pipeconf |= PIPECONF_PROGRESSIVE;
4431 I915_WRITE(VSYNCSHIFT(pipe), 0);
4432 }
4433
4434 I915_WRITE(HTOTAL(pipe),
4435 (adjusted_mode->crtc_hdisplay - 1) |
4436 ((adjusted_mode->crtc_htotal - 1) << 16));
4437 I915_WRITE(HBLANK(pipe),
4438 (adjusted_mode->crtc_hblank_start - 1) |
4439 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4440 I915_WRITE(HSYNC(pipe),
4441 (adjusted_mode->crtc_hsync_start - 1) |
4442 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4443
4444 I915_WRITE(VTOTAL(pipe),
4445 (adjusted_mode->crtc_vdisplay - 1) |
4446 ((adjusted_mode->crtc_vtotal - 1) << 16));
4447 I915_WRITE(VBLANK(pipe),
4448 (adjusted_mode->crtc_vblank_start - 1) |
4449 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4450 I915_WRITE(VSYNC(pipe),
4451 (adjusted_mode->crtc_vsync_start - 1) |
4452 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4453
4454 /* pipesrc controls the size that is scaled from, which should
4455 * always be the user's requested size.
4456 */
4457 I915_WRITE(PIPESRC(pipe),
4458 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4459
4460 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4461 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4462 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4463 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4464
4465 if (is_cpu_edp)
4466 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4467
4468 I915_WRITE(PIPECONF(pipe), pipeconf);
4469 POSTING_READ(PIPECONF(pipe));
4470
4471 intel_wait_for_vblank(dev, pipe);
4472
4473 I915_WRITE(DSPCNTR(plane), dspcntr);
4474 POSTING_READ(DSPCNTR(plane));
4475
4476 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4477
4478 intel_update_watermarks(dev);
4479
4480 return ret;
4481 }
4482
4483 static int intel_crtc_mode_set(struct drm_crtc *crtc,
4484 struct drm_display_mode *mode,
4485 struct drm_display_mode *adjusted_mode,
4486 int x, int y,
4487 struct drm_framebuffer *old_fb)
4488 {
4489 struct drm_device *dev = crtc->dev;
4490 struct drm_i915_private *dev_priv = dev->dev_private;
4491 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4492 int pipe = intel_crtc->pipe;
4493 int ret;
4494
4495 drm_vblank_pre_modeset(dev, pipe);
4496
4497 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
4498 x, y, old_fb);
4499 drm_vblank_post_modeset(dev, pipe);
4500
4501 if (ret)
4502 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4503 else
4504 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
4505
4506 return ret;
4507 }
4508
4509 static bool intel_eld_uptodate(struct drm_connector *connector,
4510 int reg_eldv, uint32_t bits_eldv,
4511 int reg_elda, uint32_t bits_elda,
4512 int reg_edid)
4513 {
4514 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4515 uint8_t *eld = connector->eld;
4516 uint32_t i;
4517
4518 i = I915_READ(reg_eldv);
4519 i &= bits_eldv;
4520
4521 if (!eld[0])
4522 return !i;
4523
4524 if (!i)
4525 return false;
4526
4527 i = I915_READ(reg_elda);
4528 i &= ~bits_elda;
4529 I915_WRITE(reg_elda, i);
4530
4531 for (i = 0; i < eld[2]; i++)
4532 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
4533 return false;
4534
4535 return true;
4536 }
4537
4538 static void g4x_write_eld(struct drm_connector *connector,
4539 struct drm_crtc *crtc)
4540 {
4541 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4542 uint8_t *eld = connector->eld;
4543 uint32_t eldv;
4544 uint32_t len;
4545 uint32_t i;
4546
4547 i = I915_READ(G4X_AUD_VID_DID);
4548
4549 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
4550 eldv = G4X_ELDV_DEVCL_DEVBLC;
4551 else
4552 eldv = G4X_ELDV_DEVCTG;
4553
4554 if (intel_eld_uptodate(connector,
4555 G4X_AUD_CNTL_ST, eldv,
4556 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
4557 G4X_HDMIW_HDMIEDID))
4558 return;
4559
4560 i = I915_READ(G4X_AUD_CNTL_ST);
4561 i &= ~(eldv | G4X_ELD_ADDR);
4562 len = (i >> 9) & 0x1f; /* ELD buffer size */
4563 I915_WRITE(G4X_AUD_CNTL_ST, i);
4564
4565 if (!eld[0])
4566 return;
4567
4568 len = min_t(uint8_t, eld[2], len);
4569 DRM_DEBUG_DRIVER("ELD size %d\n", len);
4570 for (i = 0; i < len; i++)
4571 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
4572
4573 i = I915_READ(G4X_AUD_CNTL_ST);
4574 i |= eldv;
4575 I915_WRITE(G4X_AUD_CNTL_ST, i);
4576 }
4577
4578 static void ironlake_write_eld(struct drm_connector *connector,
4579 struct drm_crtc *crtc)
4580 {
4581 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4582 uint8_t *eld = connector->eld;
4583 uint32_t eldv;
4584 uint32_t i;
4585 int len;
4586 int hdmiw_hdmiedid;
4587 int aud_config;
4588 int aud_cntl_st;
4589 int aud_cntrl_st2;
4590
4591 if (HAS_PCH_IBX(connector->dev)) {
4592 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
4593 aud_config = IBX_AUD_CONFIG_A;
4594 aud_cntl_st = IBX_AUD_CNTL_ST_A;
4595 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
4596 } else {
4597 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
4598 aud_config = CPT_AUD_CONFIG_A;
4599 aud_cntl_st = CPT_AUD_CNTL_ST_A;
4600 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
4601 }
4602
4603 i = to_intel_crtc(crtc)->pipe;
4604 hdmiw_hdmiedid += i * 0x100;
4605 aud_cntl_st += i * 0x100;
4606 aud_config += i * 0x100;
4607
4608 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
4609
4610 i = I915_READ(aud_cntl_st);
4611 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
4612 if (!i) {
4613 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
4614 /* operate blindly on all ports */
4615 eldv = IBX_ELD_VALIDB;
4616 eldv |= IBX_ELD_VALIDB << 4;
4617 eldv |= IBX_ELD_VALIDB << 8;
4618 } else {
4619 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
4620 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
4621 }
4622
4623 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
4624 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
4625 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
4626 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
4627 } else
4628 I915_WRITE(aud_config, 0);
4629
4630 if (intel_eld_uptodate(connector,
4631 aud_cntrl_st2, eldv,
4632 aud_cntl_st, IBX_ELD_ADDRESS,
4633 hdmiw_hdmiedid))
4634 return;
4635
4636 i = I915_READ(aud_cntrl_st2);
4637 i &= ~eldv;
4638 I915_WRITE(aud_cntrl_st2, i);
4639
4640 if (!eld[0])
4641 return;
4642
4643 i = I915_READ(aud_cntl_st);
4644 i &= ~IBX_ELD_ADDRESS;
4645 I915_WRITE(aud_cntl_st, i);
4646
4647 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
4648 DRM_DEBUG_DRIVER("ELD size %d\n", len);
4649 for (i = 0; i < len; i++)
4650 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
4651
4652 i = I915_READ(aud_cntrl_st2);
4653 i |= eldv;
4654 I915_WRITE(aud_cntrl_st2, i);
4655 }
4656
4657 void intel_write_eld(struct drm_encoder *encoder,
4658 struct drm_display_mode *mode)
4659 {
4660 struct drm_crtc *crtc = encoder->crtc;
4661 struct drm_connector *connector;
4662 struct drm_device *dev = encoder->dev;
4663 struct drm_i915_private *dev_priv = dev->dev_private;
4664
4665 connector = drm_select_eld(encoder, mode);
4666 if (!connector)
4667 return;
4668
4669 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
4670 connector->base.id,
4671 drm_get_connector_name(connector),
4672 connector->encoder->base.id,
4673 drm_get_encoder_name(connector->encoder));
4674
4675 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
4676
4677 if (dev_priv->display.write_eld)
4678 dev_priv->display.write_eld(connector, crtc);
4679 }
4680
4681 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4682 void intel_crtc_load_lut(struct drm_crtc *crtc)
4683 {
4684 struct drm_device *dev = crtc->dev;
4685 struct drm_i915_private *dev_priv = dev->dev_private;
4686 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4687 int palreg = PALETTE(intel_crtc->pipe);
4688 int i;
4689
4690 /* The clocks have to be on to load the palette. */
4691 if (!crtc->enabled || !intel_crtc->active)
4692 return;
4693
4694 /* use legacy palette for Ironlake */
4695 if (HAS_PCH_SPLIT(dev))
4696 palreg = LGC_PALETTE(intel_crtc->pipe);
4697
4698 for (i = 0; i < 256; i++) {
4699 I915_WRITE(palreg + 4 * i,
4700 (intel_crtc->lut_r[i] << 16) |
4701 (intel_crtc->lut_g[i] << 8) |
4702 intel_crtc->lut_b[i]);
4703 }
4704 }
4705
4706 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4707 {
4708 struct drm_device *dev = crtc->dev;
4709 struct drm_i915_private *dev_priv = dev->dev_private;
4710 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4711 bool visible = base != 0;
4712 u32 cntl;
4713
4714 if (intel_crtc->cursor_visible == visible)
4715 return;
4716
4717 cntl = I915_READ(_CURACNTR);
4718 if (visible) {
4719 /* On these chipsets we can only modify the base whilst
4720 * the cursor is disabled.
4721 */
4722 I915_WRITE(_CURABASE, base);
4723
4724 cntl &= ~(CURSOR_FORMAT_MASK);
4725 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4726 cntl |= CURSOR_ENABLE |
4727 CURSOR_GAMMA_ENABLE |
4728 CURSOR_FORMAT_ARGB;
4729 } else
4730 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4731 I915_WRITE(_CURACNTR, cntl);
4732
4733 intel_crtc->cursor_visible = visible;
4734 }
4735
4736 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4737 {
4738 struct drm_device *dev = crtc->dev;
4739 struct drm_i915_private *dev_priv = dev->dev_private;
4740 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4741 int pipe = intel_crtc->pipe;
4742 bool visible = base != 0;
4743
4744 if (intel_crtc->cursor_visible != visible) {
4745 uint32_t cntl = I915_READ(CURCNTR(pipe));
4746 if (base) {
4747 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4748 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4749 cntl |= pipe << 28; /* Connect to correct pipe */
4750 } else {
4751 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4752 cntl |= CURSOR_MODE_DISABLE;
4753 }
4754 I915_WRITE(CURCNTR(pipe), cntl);
4755
4756 intel_crtc->cursor_visible = visible;
4757 }
4758 /* and commit changes on next vblank */
4759 I915_WRITE(CURBASE(pipe), base);
4760 }
4761
4762 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
4763 {
4764 struct drm_device *dev = crtc->dev;
4765 struct drm_i915_private *dev_priv = dev->dev_private;
4766 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4767 int pipe = intel_crtc->pipe;
4768 bool visible = base != 0;
4769
4770 if (intel_crtc->cursor_visible != visible) {
4771 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
4772 if (base) {
4773 cntl &= ~CURSOR_MODE;
4774 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4775 } else {
4776 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4777 cntl |= CURSOR_MODE_DISABLE;
4778 }
4779 I915_WRITE(CURCNTR_IVB(pipe), cntl);
4780
4781 intel_crtc->cursor_visible = visible;
4782 }
4783 /* and commit changes on next vblank */
4784 I915_WRITE(CURBASE_IVB(pipe), base);
4785 }
4786
4787 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4788 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
4789 bool on)
4790 {
4791 struct drm_device *dev = crtc->dev;
4792 struct drm_i915_private *dev_priv = dev->dev_private;
4793 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4794 int pipe = intel_crtc->pipe;
4795 int x = intel_crtc->cursor_x;
4796 int y = intel_crtc->cursor_y;
4797 u32 base, pos;
4798 bool visible;
4799
4800 pos = 0;
4801
4802 if (on && crtc->enabled && crtc->fb) {
4803 base = intel_crtc->cursor_addr;
4804 if (x > (int) crtc->fb->width)
4805 base = 0;
4806
4807 if (y > (int) crtc->fb->height)
4808 base = 0;
4809 } else
4810 base = 0;
4811
4812 if (x < 0) {
4813 if (x + intel_crtc->cursor_width < 0)
4814 base = 0;
4815
4816 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4817 x = -x;
4818 }
4819 pos |= x << CURSOR_X_SHIFT;
4820
4821 if (y < 0) {
4822 if (y + intel_crtc->cursor_height < 0)
4823 base = 0;
4824
4825 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4826 y = -y;
4827 }
4828 pos |= y << CURSOR_Y_SHIFT;
4829
4830 visible = base != 0;
4831 if (!visible && !intel_crtc->cursor_visible)
4832 return;
4833
4834 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
4835 I915_WRITE(CURPOS_IVB(pipe), pos);
4836 ivb_update_cursor(crtc, base);
4837 } else {
4838 I915_WRITE(CURPOS(pipe), pos);
4839 if (IS_845G(dev) || IS_I865G(dev))
4840 i845_update_cursor(crtc, base);
4841 else
4842 i9xx_update_cursor(crtc, base);
4843 }
4844 }
4845
4846 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4847 struct drm_file *file,
4848 uint32_t handle,
4849 uint32_t width, uint32_t height)
4850 {
4851 struct drm_device *dev = crtc->dev;
4852 struct drm_i915_private *dev_priv = dev->dev_private;
4853 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4854 struct drm_i915_gem_object *obj;
4855 uint32_t addr;
4856 int ret;
4857
4858 DRM_DEBUG_KMS("\n");
4859
4860 /* if we want to turn off the cursor ignore width and height */
4861 if (!handle) {
4862 DRM_DEBUG_KMS("cursor off\n");
4863 addr = 0;
4864 obj = NULL;
4865 mutex_lock(&dev->struct_mutex);
4866 goto finish;
4867 }
4868
4869 /* Currently we only support 64x64 cursors */
4870 if (width != 64 || height != 64) {
4871 DRM_ERROR("we currently only support 64x64 cursors\n");
4872 return -EINVAL;
4873 }
4874
4875 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
4876 if (&obj->base == NULL)
4877 return -ENOENT;
4878
4879 if (obj->base.size < width * height * 4) {
4880 DRM_ERROR("buffer is to small\n");
4881 ret = -ENOMEM;
4882 goto fail;
4883 }
4884
4885 /* we only need to pin inside GTT if cursor is non-phy */
4886 mutex_lock(&dev->struct_mutex);
4887 if (!dev_priv->info->cursor_needs_physical) {
4888 if (obj->tiling_mode) {
4889 DRM_ERROR("cursor cannot be tiled\n");
4890 ret = -EINVAL;
4891 goto fail_locked;
4892 }
4893
4894 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
4895 if (ret) {
4896 DRM_ERROR("failed to move cursor bo into the GTT\n");
4897 goto fail_locked;
4898 }
4899
4900 ret = i915_gem_object_put_fence(obj);
4901 if (ret) {
4902 DRM_ERROR("failed to release fence for cursor");
4903 goto fail_unpin;
4904 }
4905
4906 addr = obj->gtt_offset;
4907 } else {
4908 int align = IS_I830(dev) ? 16 * 1024 : 256;
4909 ret = i915_gem_attach_phys_object(dev, obj,
4910 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4911 align);
4912 if (ret) {
4913 DRM_ERROR("failed to attach phys object\n");
4914 goto fail_locked;
4915 }
4916 addr = obj->phys_obj->handle->busaddr;
4917 }
4918
4919 if (IS_GEN2(dev))
4920 I915_WRITE(CURSIZE, (height << 12) | width);
4921
4922 finish:
4923 if (intel_crtc->cursor_bo) {
4924 if (dev_priv->info->cursor_needs_physical) {
4925 if (intel_crtc->cursor_bo != obj)
4926 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4927 } else
4928 i915_gem_object_unpin(intel_crtc->cursor_bo);
4929 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
4930 }
4931
4932 mutex_unlock(&dev->struct_mutex);
4933
4934 intel_crtc->cursor_addr = addr;
4935 intel_crtc->cursor_bo = obj;
4936 intel_crtc->cursor_width = width;
4937 intel_crtc->cursor_height = height;
4938
4939 intel_crtc_update_cursor(crtc, true);
4940
4941 return 0;
4942 fail_unpin:
4943 i915_gem_object_unpin(obj);
4944 fail_locked:
4945 mutex_unlock(&dev->struct_mutex);
4946 fail:
4947 drm_gem_object_unreference_unlocked(&obj->base);
4948 return ret;
4949 }
4950
4951 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4952 {
4953 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4954
4955 intel_crtc->cursor_x = x;
4956 intel_crtc->cursor_y = y;
4957
4958 intel_crtc_update_cursor(crtc, true);
4959
4960 return 0;
4961 }
4962
4963 /** Sets the color ramps on behalf of RandR */
4964 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4965 u16 blue, int regno)
4966 {
4967 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4968
4969 intel_crtc->lut_r[regno] = red >> 8;
4970 intel_crtc->lut_g[regno] = green >> 8;
4971 intel_crtc->lut_b[regno] = blue >> 8;
4972 }
4973
4974 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4975 u16 *blue, int regno)
4976 {
4977 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4978
4979 *red = intel_crtc->lut_r[regno] << 8;
4980 *green = intel_crtc->lut_g[regno] << 8;
4981 *blue = intel_crtc->lut_b[regno] << 8;
4982 }
4983
4984 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4985 u16 *blue, uint32_t start, uint32_t size)
4986 {
4987 int end = (start + size > 256) ? 256 : start + size, i;
4988 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4989
4990 for (i = start; i < end; i++) {
4991 intel_crtc->lut_r[i] = red[i] >> 8;
4992 intel_crtc->lut_g[i] = green[i] >> 8;
4993 intel_crtc->lut_b[i] = blue[i] >> 8;
4994 }
4995
4996 intel_crtc_load_lut(crtc);
4997 }
4998
4999 /**
5000 * Get a pipe with a simple mode set on it for doing load-based monitor
5001 * detection.
5002 *
5003 * It will be up to the load-detect code to adjust the pipe as appropriate for
5004 * its requirements. The pipe will be connected to no other encoders.
5005 *
5006 * Currently this code will only succeed if there is a pipe with no encoders
5007 * configured for it. In the future, it could choose to temporarily disable
5008 * some outputs to free up a pipe for its use.
5009 *
5010 * \return crtc, or NULL if no pipes are available.
5011 */
5012
5013 /* VESA 640x480x72Hz mode to set on the pipe */
5014 static struct drm_display_mode load_detect_mode = {
5015 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5016 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5017 };
5018
5019 static struct drm_framebuffer *
5020 intel_framebuffer_create(struct drm_device *dev,
5021 struct drm_mode_fb_cmd2 *mode_cmd,
5022 struct drm_i915_gem_object *obj)
5023 {
5024 struct intel_framebuffer *intel_fb;
5025 int ret;
5026
5027 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5028 if (!intel_fb) {
5029 drm_gem_object_unreference_unlocked(&obj->base);
5030 return ERR_PTR(-ENOMEM);
5031 }
5032
5033 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5034 if (ret) {
5035 drm_gem_object_unreference_unlocked(&obj->base);
5036 kfree(intel_fb);
5037 return ERR_PTR(ret);
5038 }
5039
5040 return &intel_fb->base;
5041 }
5042
5043 static u32
5044 intel_framebuffer_pitch_for_width(int width, int bpp)
5045 {
5046 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5047 return ALIGN(pitch, 64);
5048 }
5049
5050 static u32
5051 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5052 {
5053 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5054 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5055 }
5056
5057 static struct drm_framebuffer *
5058 intel_framebuffer_create_for_mode(struct drm_device *dev,
5059 struct drm_display_mode *mode,
5060 int depth, int bpp)
5061 {
5062 struct drm_i915_gem_object *obj;
5063 struct drm_mode_fb_cmd2 mode_cmd;
5064
5065 obj = i915_gem_alloc_object(dev,
5066 intel_framebuffer_size_for_mode(mode, bpp));
5067 if (obj == NULL)
5068 return ERR_PTR(-ENOMEM);
5069
5070 mode_cmd.width = mode->hdisplay;
5071 mode_cmd.height = mode->vdisplay;
5072 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5073 bpp);
5074 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
5075
5076 return intel_framebuffer_create(dev, &mode_cmd, obj);
5077 }
5078
5079 static struct drm_framebuffer *
5080 mode_fits_in_fbdev(struct drm_device *dev,
5081 struct drm_display_mode *mode)
5082 {
5083 struct drm_i915_private *dev_priv = dev->dev_private;
5084 struct drm_i915_gem_object *obj;
5085 struct drm_framebuffer *fb;
5086
5087 if (dev_priv->fbdev == NULL)
5088 return NULL;
5089
5090 obj = dev_priv->fbdev->ifb.obj;
5091 if (obj == NULL)
5092 return NULL;
5093
5094 fb = &dev_priv->fbdev->ifb.base;
5095 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5096 fb->bits_per_pixel))
5097 return NULL;
5098
5099 if (obj->base.size < mode->vdisplay * fb->pitches[0])
5100 return NULL;
5101
5102 return fb;
5103 }
5104
5105 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5106 struct drm_connector *connector,
5107 struct drm_display_mode *mode,
5108 struct intel_load_detect_pipe *old)
5109 {
5110 struct intel_crtc *intel_crtc;
5111 struct drm_crtc *possible_crtc;
5112 struct drm_encoder *encoder = &intel_encoder->base;
5113 struct drm_crtc *crtc = NULL;
5114 struct drm_device *dev = encoder->dev;
5115 struct drm_framebuffer *old_fb;
5116 int i = -1;
5117
5118 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5119 connector->base.id, drm_get_connector_name(connector),
5120 encoder->base.id, drm_get_encoder_name(encoder));
5121
5122 /*
5123 * Algorithm gets a little messy:
5124 *
5125 * - if the connector already has an assigned crtc, use it (but make
5126 * sure it's on first)
5127 *
5128 * - try to find the first unused crtc that can drive this connector,
5129 * and use that if we find one
5130 */
5131
5132 /* See if we already have a CRTC for this connector */
5133 if (encoder->crtc) {
5134 crtc = encoder->crtc;
5135
5136 intel_crtc = to_intel_crtc(crtc);
5137 old->dpms_mode = intel_crtc->dpms_mode;
5138 old->load_detect_temp = false;
5139
5140 /* Make sure the crtc and connector are running */
5141 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5142 struct drm_encoder_helper_funcs *encoder_funcs;
5143 struct drm_crtc_helper_funcs *crtc_funcs;
5144
5145 crtc_funcs = crtc->helper_private;
5146 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5147
5148 encoder_funcs = encoder->helper_private;
5149 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5150 }
5151
5152 return true;
5153 }
5154
5155 /* Find an unused one (if possible) */
5156 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5157 i++;
5158 if (!(encoder->possible_crtcs & (1 << i)))
5159 continue;
5160 if (!possible_crtc->enabled) {
5161 crtc = possible_crtc;
5162 break;
5163 }
5164 }
5165
5166 /*
5167 * If we didn't find an unused CRTC, don't use any.
5168 */
5169 if (!crtc) {
5170 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5171 return false;
5172 }
5173
5174 encoder->crtc = crtc;
5175 connector->encoder = encoder;
5176
5177 intel_crtc = to_intel_crtc(crtc);
5178 old->dpms_mode = intel_crtc->dpms_mode;
5179 old->load_detect_temp = true;
5180 old->release_fb = NULL;
5181
5182 if (!mode)
5183 mode = &load_detect_mode;
5184
5185 old_fb = crtc->fb;
5186
5187 /* We need a framebuffer large enough to accommodate all accesses
5188 * that the plane may generate whilst we perform load detection.
5189 * We can not rely on the fbcon either being present (we get called
5190 * during its initialisation to detect all boot displays, or it may
5191 * not even exist) or that it is large enough to satisfy the
5192 * requested mode.
5193 */
5194 crtc->fb = mode_fits_in_fbdev(dev, mode);
5195 if (crtc->fb == NULL) {
5196 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5197 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5198 old->release_fb = crtc->fb;
5199 } else
5200 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5201 if (IS_ERR(crtc->fb)) {
5202 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5203 crtc->fb = old_fb;
5204 return false;
5205 }
5206
5207 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
5208 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
5209 if (old->release_fb)
5210 old->release_fb->funcs->destroy(old->release_fb);
5211 crtc->fb = old_fb;
5212 return false;
5213 }
5214
5215 /* let the connector get through one full cycle before testing */
5216 intel_wait_for_vblank(dev, intel_crtc->pipe);
5217
5218 return true;
5219 }
5220
5221 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
5222 struct drm_connector *connector,
5223 struct intel_load_detect_pipe *old)
5224 {
5225 struct drm_encoder *encoder = &intel_encoder->base;
5226 struct drm_device *dev = encoder->dev;
5227 struct drm_crtc *crtc = encoder->crtc;
5228 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5229 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5230
5231 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5232 connector->base.id, drm_get_connector_name(connector),
5233 encoder->base.id, drm_get_encoder_name(encoder));
5234
5235 if (old->load_detect_temp) {
5236 connector->encoder = NULL;
5237 drm_helper_disable_unused_functions(dev);
5238
5239 if (old->release_fb)
5240 old->release_fb->funcs->destroy(old->release_fb);
5241
5242 return;
5243 }
5244
5245 /* Switch crtc and encoder back off if necessary */
5246 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5247 encoder_funcs->dpms(encoder, old->dpms_mode);
5248 crtc_funcs->dpms(crtc, old->dpms_mode);
5249 }
5250 }
5251
5252 /* Returns the clock of the currently programmed mode of the given pipe. */
5253 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5254 {
5255 struct drm_i915_private *dev_priv = dev->dev_private;
5256 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5257 int pipe = intel_crtc->pipe;
5258 u32 dpll = I915_READ(DPLL(pipe));
5259 u32 fp;
5260 intel_clock_t clock;
5261
5262 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5263 fp = I915_READ(FP0(pipe));
5264 else
5265 fp = I915_READ(FP1(pipe));
5266
5267 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5268 if (IS_PINEVIEW(dev)) {
5269 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5270 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5271 } else {
5272 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5273 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5274 }
5275
5276 if (!IS_GEN2(dev)) {
5277 if (IS_PINEVIEW(dev))
5278 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5279 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
5280 else
5281 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5282 DPLL_FPA01_P1_POST_DIV_SHIFT);
5283
5284 switch (dpll & DPLL_MODE_MASK) {
5285 case DPLLB_MODE_DAC_SERIAL:
5286 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5287 5 : 10;
5288 break;
5289 case DPLLB_MODE_LVDS:
5290 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5291 7 : 14;
5292 break;
5293 default:
5294 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5295 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5296 return 0;
5297 }
5298
5299 /* XXX: Handle the 100Mhz refclk */
5300 intel_clock(dev, 96000, &clock);
5301 } else {
5302 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5303
5304 if (is_lvds) {
5305 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5306 DPLL_FPA01_P1_POST_DIV_SHIFT);
5307 clock.p2 = 14;
5308
5309 if ((dpll & PLL_REF_INPUT_MASK) ==
5310 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5311 /* XXX: might not be 66MHz */
5312 intel_clock(dev, 66000, &clock);
5313 } else
5314 intel_clock(dev, 48000, &clock);
5315 } else {
5316 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5317 clock.p1 = 2;
5318 else {
5319 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5320 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5321 }
5322 if (dpll & PLL_P2_DIVIDE_BY_4)
5323 clock.p2 = 4;
5324 else
5325 clock.p2 = 2;
5326
5327 intel_clock(dev, 48000, &clock);
5328 }
5329 }
5330
5331 /* XXX: It would be nice to validate the clocks, but we can't reuse
5332 * i830PllIsValid() because it relies on the xf86_config connector
5333 * configuration being accurate, which it isn't necessarily.
5334 */
5335
5336 return clock.dot;
5337 }
5338
5339 /** Returns the currently programmed mode of the given pipe. */
5340 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5341 struct drm_crtc *crtc)
5342 {
5343 struct drm_i915_private *dev_priv = dev->dev_private;
5344 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5345 int pipe = intel_crtc->pipe;
5346 struct drm_display_mode *mode;
5347 int htot = I915_READ(HTOTAL(pipe));
5348 int hsync = I915_READ(HSYNC(pipe));
5349 int vtot = I915_READ(VTOTAL(pipe));
5350 int vsync = I915_READ(VSYNC(pipe));
5351
5352 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5353 if (!mode)
5354 return NULL;
5355
5356 mode->clock = intel_crtc_clock_get(dev, crtc);
5357 mode->hdisplay = (htot & 0xffff) + 1;
5358 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5359 mode->hsync_start = (hsync & 0xffff) + 1;
5360 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5361 mode->vdisplay = (vtot & 0xffff) + 1;
5362 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5363 mode->vsync_start = (vsync & 0xffff) + 1;
5364 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5365
5366 drm_mode_set_name(mode);
5367
5368 return mode;
5369 }
5370
5371 #define GPU_IDLE_TIMEOUT 500 /* ms */
5372
5373 /* When this timer fires, we've been idle for awhile */
5374 static void intel_gpu_idle_timer(unsigned long arg)
5375 {
5376 struct drm_device *dev = (struct drm_device *)arg;
5377 drm_i915_private_t *dev_priv = dev->dev_private;
5378
5379 if (!list_empty(&dev_priv->mm.active_list)) {
5380 /* Still processing requests, so just re-arm the timer. */
5381 mod_timer(&dev_priv->idle_timer, jiffies +
5382 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5383 return;
5384 }
5385
5386 dev_priv->busy = false;
5387 queue_work(dev_priv->wq, &dev_priv->idle_work);
5388 }
5389
5390 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
5391
5392 static void intel_crtc_idle_timer(unsigned long arg)
5393 {
5394 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5395 struct drm_crtc *crtc = &intel_crtc->base;
5396 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
5397 struct intel_framebuffer *intel_fb;
5398
5399 intel_fb = to_intel_framebuffer(crtc->fb);
5400 if (intel_fb && intel_fb->obj->active) {
5401 /* The framebuffer is still being accessed by the GPU. */
5402 mod_timer(&intel_crtc->idle_timer, jiffies +
5403 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5404 return;
5405 }
5406
5407 intel_crtc->busy = false;
5408 queue_work(dev_priv->wq, &dev_priv->idle_work);
5409 }
5410
5411 static void intel_increase_pllclock(struct drm_crtc *crtc)
5412 {
5413 struct drm_device *dev = crtc->dev;
5414 drm_i915_private_t *dev_priv = dev->dev_private;
5415 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5416 int pipe = intel_crtc->pipe;
5417 int dpll_reg = DPLL(pipe);
5418 int dpll;
5419
5420 if (HAS_PCH_SPLIT(dev))
5421 return;
5422
5423 if (!dev_priv->lvds_downclock_avail)
5424 return;
5425
5426 dpll = I915_READ(dpll_reg);
5427 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
5428 DRM_DEBUG_DRIVER("upclocking LVDS\n");
5429
5430 assert_panel_unlocked(dev_priv, pipe);
5431
5432 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5433 I915_WRITE(dpll_reg, dpll);
5434 intel_wait_for_vblank(dev, pipe);
5435
5436 dpll = I915_READ(dpll_reg);
5437 if (dpll & DISPLAY_RATE_SELECT_FPA1)
5438 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
5439 }
5440
5441 /* Schedule downclock */
5442 mod_timer(&intel_crtc->idle_timer, jiffies +
5443 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5444 }
5445
5446 static void intel_decrease_pllclock(struct drm_crtc *crtc)
5447 {
5448 struct drm_device *dev = crtc->dev;
5449 drm_i915_private_t *dev_priv = dev->dev_private;
5450 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5451
5452 if (HAS_PCH_SPLIT(dev))
5453 return;
5454
5455 if (!dev_priv->lvds_downclock_avail)
5456 return;
5457
5458 /*
5459 * Since this is called by a timer, we should never get here in
5460 * the manual case.
5461 */
5462 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
5463 int pipe = intel_crtc->pipe;
5464 int dpll_reg = DPLL(pipe);
5465 int dpll;
5466
5467 DRM_DEBUG_DRIVER("downclocking LVDS\n");
5468
5469 assert_panel_unlocked(dev_priv, pipe);
5470
5471 dpll = I915_READ(dpll_reg);
5472 dpll |= DISPLAY_RATE_SELECT_FPA1;
5473 I915_WRITE(dpll_reg, dpll);
5474 intel_wait_for_vblank(dev, pipe);
5475 dpll = I915_READ(dpll_reg);
5476 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
5477 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
5478 }
5479
5480 }
5481
5482 /**
5483 * intel_idle_update - adjust clocks for idleness
5484 * @work: work struct
5485 *
5486 * Either the GPU or display (or both) went idle. Check the busy status
5487 * here and adjust the CRTC and GPU clocks as necessary.
5488 */
5489 static void intel_idle_update(struct work_struct *work)
5490 {
5491 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
5492 idle_work);
5493 struct drm_device *dev = dev_priv->dev;
5494 struct drm_crtc *crtc;
5495 struct intel_crtc *intel_crtc;
5496
5497 if (!i915_powersave)
5498 return;
5499
5500 mutex_lock(&dev->struct_mutex);
5501
5502 i915_update_gfx_val(dev_priv);
5503
5504 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5505 /* Skip inactive CRTCs */
5506 if (!crtc->fb)
5507 continue;
5508
5509 intel_crtc = to_intel_crtc(crtc);
5510 if (!intel_crtc->busy)
5511 intel_decrease_pllclock(crtc);
5512 }
5513
5514
5515 mutex_unlock(&dev->struct_mutex);
5516 }
5517
5518 /**
5519 * intel_mark_busy - mark the GPU and possibly the display busy
5520 * @dev: drm device
5521 * @obj: object we're operating on
5522 *
5523 * Callers can use this function to indicate that the GPU is busy processing
5524 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
5525 * buffer), we'll also mark the display as busy, so we know to increase its
5526 * clock frequency.
5527 */
5528 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
5529 {
5530 drm_i915_private_t *dev_priv = dev->dev_private;
5531 struct drm_crtc *crtc = NULL;
5532 struct intel_framebuffer *intel_fb;
5533 struct intel_crtc *intel_crtc;
5534
5535 if (!drm_core_check_feature(dev, DRIVER_MODESET))
5536 return;
5537
5538 if (!dev_priv->busy) {
5539 intel_sanitize_pm(dev);
5540 dev_priv->busy = true;
5541 } else
5542 mod_timer(&dev_priv->idle_timer, jiffies +
5543 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5544
5545 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5546 if (!crtc->fb)
5547 continue;
5548
5549 intel_crtc = to_intel_crtc(crtc);
5550 intel_fb = to_intel_framebuffer(crtc->fb);
5551 if (intel_fb->obj == obj) {
5552 if (!intel_crtc->busy) {
5553 /* Non-busy -> busy, upclock */
5554 intel_increase_pllclock(crtc);
5555 intel_crtc->busy = true;
5556 } else {
5557 /* Busy -> busy, put off timer */
5558 mod_timer(&intel_crtc->idle_timer, jiffies +
5559 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5560 }
5561 }
5562 }
5563 }
5564
5565 static void intel_crtc_destroy(struct drm_crtc *crtc)
5566 {
5567 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5568 struct drm_device *dev = crtc->dev;
5569 struct intel_unpin_work *work;
5570 unsigned long flags;
5571
5572 spin_lock_irqsave(&dev->event_lock, flags);
5573 work = intel_crtc->unpin_work;
5574 intel_crtc->unpin_work = NULL;
5575 spin_unlock_irqrestore(&dev->event_lock, flags);
5576
5577 if (work) {
5578 cancel_work_sync(&work->work);
5579 kfree(work);
5580 }
5581
5582 drm_crtc_cleanup(crtc);
5583
5584 kfree(intel_crtc);
5585 }
5586
5587 static void intel_unpin_work_fn(struct work_struct *__work)
5588 {
5589 struct intel_unpin_work *work =
5590 container_of(__work, struct intel_unpin_work, work);
5591
5592 mutex_lock(&work->dev->struct_mutex);
5593 intel_unpin_fb_obj(work->old_fb_obj);
5594 drm_gem_object_unreference(&work->pending_flip_obj->base);
5595 drm_gem_object_unreference(&work->old_fb_obj->base);
5596
5597 intel_update_fbc(work->dev);
5598 mutex_unlock(&work->dev->struct_mutex);
5599 kfree(work);
5600 }
5601
5602 static void do_intel_finish_page_flip(struct drm_device *dev,
5603 struct drm_crtc *crtc)
5604 {
5605 drm_i915_private_t *dev_priv = dev->dev_private;
5606 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5607 struct intel_unpin_work *work;
5608 struct drm_i915_gem_object *obj;
5609 struct drm_pending_vblank_event *e;
5610 struct timeval tnow, tvbl;
5611 unsigned long flags;
5612
5613 /* Ignore early vblank irqs */
5614 if (intel_crtc == NULL)
5615 return;
5616
5617 do_gettimeofday(&tnow);
5618
5619 spin_lock_irqsave(&dev->event_lock, flags);
5620 work = intel_crtc->unpin_work;
5621 if (work == NULL || !work->pending) {
5622 spin_unlock_irqrestore(&dev->event_lock, flags);
5623 return;
5624 }
5625
5626 intel_crtc->unpin_work = NULL;
5627
5628 if (work->event) {
5629 e = work->event;
5630 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
5631
5632 /* Called before vblank count and timestamps have
5633 * been updated for the vblank interval of flip
5634 * completion? Need to increment vblank count and
5635 * add one videorefresh duration to returned timestamp
5636 * to account for this. We assume this happened if we
5637 * get called over 0.9 frame durations after the last
5638 * timestamped vblank.
5639 *
5640 * This calculation can not be used with vrefresh rates
5641 * below 5Hz (10Hz to be on the safe side) without
5642 * promoting to 64 integers.
5643 */
5644 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
5645 9 * crtc->framedur_ns) {
5646 e->event.sequence++;
5647 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
5648 crtc->framedur_ns);
5649 }
5650
5651 e->event.tv_sec = tvbl.tv_sec;
5652 e->event.tv_usec = tvbl.tv_usec;
5653
5654 list_add_tail(&e->base.link,
5655 &e->base.file_priv->event_list);
5656 wake_up_interruptible(&e->base.file_priv->event_wait);
5657 }
5658
5659 drm_vblank_put(dev, intel_crtc->pipe);
5660
5661 spin_unlock_irqrestore(&dev->event_lock, flags);
5662
5663 obj = work->old_fb_obj;
5664
5665 atomic_clear_mask(1 << intel_crtc->plane,
5666 &obj->pending_flip.counter);
5667 if (atomic_read(&obj->pending_flip) == 0)
5668 wake_up(&dev_priv->pending_flip_queue);
5669
5670 schedule_work(&work->work);
5671
5672 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
5673 }
5674
5675 void intel_finish_page_flip(struct drm_device *dev, int pipe)
5676 {
5677 drm_i915_private_t *dev_priv = dev->dev_private;
5678 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5679
5680 do_intel_finish_page_flip(dev, crtc);
5681 }
5682
5683 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5684 {
5685 drm_i915_private_t *dev_priv = dev->dev_private;
5686 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5687
5688 do_intel_finish_page_flip(dev, crtc);
5689 }
5690
5691 void intel_prepare_page_flip(struct drm_device *dev, int plane)
5692 {
5693 drm_i915_private_t *dev_priv = dev->dev_private;
5694 struct intel_crtc *intel_crtc =
5695 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5696 unsigned long flags;
5697
5698 spin_lock_irqsave(&dev->event_lock, flags);
5699 if (intel_crtc->unpin_work) {
5700 if ((++intel_crtc->unpin_work->pending) > 1)
5701 DRM_ERROR("Prepared flip multiple times\n");
5702 } else {
5703 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5704 }
5705 spin_unlock_irqrestore(&dev->event_lock, flags);
5706 }
5707
5708 static int intel_gen2_queue_flip(struct drm_device *dev,
5709 struct drm_crtc *crtc,
5710 struct drm_framebuffer *fb,
5711 struct drm_i915_gem_object *obj)
5712 {
5713 struct drm_i915_private *dev_priv = dev->dev_private;
5714 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5715 unsigned long offset;
5716 u32 flip_mask;
5717 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
5718 int ret;
5719
5720 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
5721 if (ret)
5722 goto err;
5723
5724 /* Offset into the new buffer for cases of shared fbs between CRTCs */
5725 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
5726
5727 ret = intel_ring_begin(ring, 6);
5728 if (ret)
5729 goto err_unpin;
5730
5731 /* Can't queue multiple flips, so wait for the previous
5732 * one to finish before executing the next.
5733 */
5734 if (intel_crtc->plane)
5735 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5736 else
5737 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5738 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
5739 intel_ring_emit(ring, MI_NOOP);
5740 intel_ring_emit(ring, MI_DISPLAY_FLIP |
5741 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5742 intel_ring_emit(ring, fb->pitches[0]);
5743 intel_ring_emit(ring, obj->gtt_offset + offset);
5744 intel_ring_emit(ring, 0); /* aux display base address, unused */
5745 intel_ring_advance(ring);
5746 return 0;
5747
5748 err_unpin:
5749 intel_unpin_fb_obj(obj);
5750 err:
5751 return ret;
5752 }
5753
5754 static int intel_gen3_queue_flip(struct drm_device *dev,
5755 struct drm_crtc *crtc,
5756 struct drm_framebuffer *fb,
5757 struct drm_i915_gem_object *obj)
5758 {
5759 struct drm_i915_private *dev_priv = dev->dev_private;
5760 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5761 unsigned long offset;
5762 u32 flip_mask;
5763 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
5764 int ret;
5765
5766 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
5767 if (ret)
5768 goto err;
5769
5770 /* Offset into the new buffer for cases of shared fbs between CRTCs */
5771 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
5772
5773 ret = intel_ring_begin(ring, 6);
5774 if (ret)
5775 goto err_unpin;
5776
5777 if (intel_crtc->plane)
5778 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5779 else
5780 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5781 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
5782 intel_ring_emit(ring, MI_NOOP);
5783 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
5784 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5785 intel_ring_emit(ring, fb->pitches[0]);
5786 intel_ring_emit(ring, obj->gtt_offset + offset);
5787 intel_ring_emit(ring, MI_NOOP);
5788
5789 intel_ring_advance(ring);
5790 return 0;
5791
5792 err_unpin:
5793 intel_unpin_fb_obj(obj);
5794 err:
5795 return ret;
5796 }
5797
5798 static int intel_gen4_queue_flip(struct drm_device *dev,
5799 struct drm_crtc *crtc,
5800 struct drm_framebuffer *fb,
5801 struct drm_i915_gem_object *obj)
5802 {
5803 struct drm_i915_private *dev_priv = dev->dev_private;
5804 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5805 uint32_t pf, pipesrc;
5806 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
5807 int ret;
5808
5809 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
5810 if (ret)
5811 goto err;
5812
5813 ret = intel_ring_begin(ring, 4);
5814 if (ret)
5815 goto err_unpin;
5816
5817 /* i965+ uses the linear or tiled offsets from the
5818 * Display Registers (which do not change across a page-flip)
5819 * so we need only reprogram the base address.
5820 */
5821 intel_ring_emit(ring, MI_DISPLAY_FLIP |
5822 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5823 intel_ring_emit(ring, fb->pitches[0]);
5824 intel_ring_emit(ring, obj->gtt_offset | obj->tiling_mode);
5825
5826 /* XXX Enabling the panel-fitter across page-flip is so far
5827 * untested on non-native modes, so ignore it for now.
5828 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5829 */
5830 pf = 0;
5831 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
5832 intel_ring_emit(ring, pf | pipesrc);
5833 intel_ring_advance(ring);
5834 return 0;
5835
5836 err_unpin:
5837 intel_unpin_fb_obj(obj);
5838 err:
5839 return ret;
5840 }
5841
5842 static int intel_gen6_queue_flip(struct drm_device *dev,
5843 struct drm_crtc *crtc,
5844 struct drm_framebuffer *fb,
5845 struct drm_i915_gem_object *obj)
5846 {
5847 struct drm_i915_private *dev_priv = dev->dev_private;
5848 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5849 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
5850 uint32_t pf, pipesrc;
5851 int ret;
5852
5853 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
5854 if (ret)
5855 goto err;
5856
5857 ret = intel_ring_begin(ring, 4);
5858 if (ret)
5859 goto err_unpin;
5860
5861 intel_ring_emit(ring, MI_DISPLAY_FLIP |
5862 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5863 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
5864 intel_ring_emit(ring, obj->gtt_offset);
5865
5866 /* Contrary to the suggestions in the documentation,
5867 * "Enable Panel Fitter" does not seem to be required when page
5868 * flipping with a non-native mode, and worse causes a normal
5869 * modeset to fail.
5870 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
5871 */
5872 pf = 0;
5873 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
5874 intel_ring_emit(ring, pf | pipesrc);
5875 intel_ring_advance(ring);
5876 return 0;
5877
5878 err_unpin:
5879 intel_unpin_fb_obj(obj);
5880 err:
5881 return ret;
5882 }
5883
5884 /*
5885 * On gen7 we currently use the blit ring because (in early silicon at least)
5886 * the render ring doesn't give us interrpts for page flip completion, which
5887 * means clients will hang after the first flip is queued. Fortunately the
5888 * blit ring generates interrupts properly, so use it instead.
5889 */
5890 static int intel_gen7_queue_flip(struct drm_device *dev,
5891 struct drm_crtc *crtc,
5892 struct drm_framebuffer *fb,
5893 struct drm_i915_gem_object *obj)
5894 {
5895 struct drm_i915_private *dev_priv = dev->dev_private;
5896 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5897 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
5898 int ret;
5899
5900 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
5901 if (ret)
5902 goto err;
5903
5904 ret = intel_ring_begin(ring, 4);
5905 if (ret)
5906 goto err_unpin;
5907
5908 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
5909 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
5910 intel_ring_emit(ring, (obj->gtt_offset));
5911 intel_ring_emit(ring, (MI_NOOP));
5912 intel_ring_advance(ring);
5913 return 0;
5914
5915 err_unpin:
5916 intel_unpin_fb_obj(obj);
5917 err:
5918 return ret;
5919 }
5920
5921 static int intel_default_queue_flip(struct drm_device *dev,
5922 struct drm_crtc *crtc,
5923 struct drm_framebuffer *fb,
5924 struct drm_i915_gem_object *obj)
5925 {
5926 return -ENODEV;
5927 }
5928
5929 static int intel_crtc_page_flip(struct drm_crtc *crtc,
5930 struct drm_framebuffer *fb,
5931 struct drm_pending_vblank_event *event)
5932 {
5933 struct drm_device *dev = crtc->dev;
5934 struct drm_i915_private *dev_priv = dev->dev_private;
5935 struct intel_framebuffer *intel_fb;
5936 struct drm_i915_gem_object *obj;
5937 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5938 struct intel_unpin_work *work;
5939 unsigned long flags;
5940 int ret;
5941
5942 work = kzalloc(sizeof *work, GFP_KERNEL);
5943 if (work == NULL)
5944 return -ENOMEM;
5945
5946 work->event = event;
5947 work->dev = crtc->dev;
5948 intel_fb = to_intel_framebuffer(crtc->fb);
5949 work->old_fb_obj = intel_fb->obj;
5950 INIT_WORK(&work->work, intel_unpin_work_fn);
5951
5952 ret = drm_vblank_get(dev, intel_crtc->pipe);
5953 if (ret)
5954 goto free_work;
5955
5956 /* We borrow the event spin lock for protecting unpin_work */
5957 spin_lock_irqsave(&dev->event_lock, flags);
5958 if (intel_crtc->unpin_work) {
5959 spin_unlock_irqrestore(&dev->event_lock, flags);
5960 kfree(work);
5961 drm_vblank_put(dev, intel_crtc->pipe);
5962
5963 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5964 return -EBUSY;
5965 }
5966 intel_crtc->unpin_work = work;
5967 spin_unlock_irqrestore(&dev->event_lock, flags);
5968
5969 intel_fb = to_intel_framebuffer(fb);
5970 obj = intel_fb->obj;
5971
5972 mutex_lock(&dev->struct_mutex);
5973
5974 /* Reference the objects for the scheduled work. */
5975 drm_gem_object_reference(&work->old_fb_obj->base);
5976 drm_gem_object_reference(&obj->base);
5977
5978 crtc->fb = fb;
5979
5980 work->pending_flip_obj = obj;
5981
5982 work->enable_stall_check = true;
5983
5984 /* Block clients from rendering to the new back buffer until
5985 * the flip occurs and the object is no longer visible.
5986 */
5987 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
5988
5989 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
5990 if (ret)
5991 goto cleanup_pending;
5992
5993 intel_disable_fbc(dev);
5994 mutex_unlock(&dev->struct_mutex);
5995
5996 trace_i915_flip_request(intel_crtc->plane, obj);
5997
5998 return 0;
5999
6000 cleanup_pending:
6001 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6002 drm_gem_object_unreference(&work->old_fb_obj->base);
6003 drm_gem_object_unreference(&obj->base);
6004 mutex_unlock(&dev->struct_mutex);
6005
6006 spin_lock_irqsave(&dev->event_lock, flags);
6007 intel_crtc->unpin_work = NULL;
6008 spin_unlock_irqrestore(&dev->event_lock, flags);
6009
6010 drm_vblank_put(dev, intel_crtc->pipe);
6011 free_work:
6012 kfree(work);
6013
6014 return ret;
6015 }
6016
6017 static void intel_sanitize_modesetting(struct drm_device *dev,
6018 int pipe, int plane)
6019 {
6020 struct drm_i915_private *dev_priv = dev->dev_private;
6021 u32 reg, val;
6022
6023 /* Clear any frame start delays used for debugging left by the BIOS */
6024 for_each_pipe(pipe) {
6025 reg = PIPECONF(pipe);
6026 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
6027 }
6028
6029 if (HAS_PCH_SPLIT(dev))
6030 return;
6031
6032 /* Who knows what state these registers were left in by the BIOS or
6033 * grub?
6034 *
6035 * If we leave the registers in a conflicting state (e.g. with the
6036 * display plane reading from the other pipe than the one we intend
6037 * to use) then when we attempt to teardown the active mode, we will
6038 * not disable the pipes and planes in the correct order -- leaving
6039 * a plane reading from a disabled pipe and possibly leading to
6040 * undefined behaviour.
6041 */
6042
6043 reg = DSPCNTR(plane);
6044 val = I915_READ(reg);
6045
6046 if ((val & DISPLAY_PLANE_ENABLE) == 0)
6047 return;
6048 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6049 return;
6050
6051 /* This display plane is active and attached to the other CPU pipe. */
6052 pipe = !pipe;
6053
6054 /* Disable the plane and wait for it to stop reading from the pipe. */
6055 intel_disable_plane(dev_priv, plane, pipe);
6056 intel_disable_pipe(dev_priv, pipe);
6057 }
6058
6059 static void intel_crtc_reset(struct drm_crtc *crtc)
6060 {
6061 struct drm_device *dev = crtc->dev;
6062 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6063
6064 /* Reset flags back to the 'unknown' status so that they
6065 * will be correctly set on the initial modeset.
6066 */
6067 intel_crtc->dpms_mode = -1;
6068
6069 /* We need to fix up any BIOS configuration that conflicts with
6070 * our expectations.
6071 */
6072 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6073 }
6074
6075 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6076 .dpms = intel_crtc_dpms,
6077 .mode_fixup = intel_crtc_mode_fixup,
6078 .mode_set = intel_crtc_mode_set,
6079 .mode_set_base = intel_pipe_set_base,
6080 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6081 .load_lut = intel_crtc_load_lut,
6082 .disable = intel_crtc_disable,
6083 };
6084
6085 static const struct drm_crtc_funcs intel_crtc_funcs = {
6086 .reset = intel_crtc_reset,
6087 .cursor_set = intel_crtc_cursor_set,
6088 .cursor_move = intel_crtc_cursor_move,
6089 .gamma_set = intel_crtc_gamma_set,
6090 .set_config = drm_crtc_helper_set_config,
6091 .destroy = intel_crtc_destroy,
6092 .page_flip = intel_crtc_page_flip,
6093 };
6094
6095 static void intel_pch_pll_init(struct drm_device *dev)
6096 {
6097 drm_i915_private_t *dev_priv = dev->dev_private;
6098 int i;
6099
6100 if (dev_priv->num_pch_pll == 0) {
6101 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
6102 return;
6103 }
6104
6105 for (i = 0; i < dev_priv->num_pch_pll; i++) {
6106 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
6107 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
6108 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
6109 }
6110 }
6111
6112 static void intel_crtc_init(struct drm_device *dev, int pipe)
6113 {
6114 drm_i915_private_t *dev_priv = dev->dev_private;
6115 struct intel_crtc *intel_crtc;
6116 int i;
6117
6118 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6119 if (intel_crtc == NULL)
6120 return;
6121
6122 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6123
6124 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
6125 for (i = 0; i < 256; i++) {
6126 intel_crtc->lut_r[i] = i;
6127 intel_crtc->lut_g[i] = i;
6128 intel_crtc->lut_b[i] = i;
6129 }
6130
6131 /* Swap pipes & planes for FBC on pre-965 */
6132 intel_crtc->pipe = pipe;
6133 intel_crtc->plane = pipe;
6134 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
6135 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
6136 intel_crtc->plane = !pipe;
6137 }
6138
6139 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6140 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6141 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6142 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6143
6144 intel_crtc_reset(&intel_crtc->base);
6145 intel_crtc->active = true; /* force the pipe off on setup_init_config */
6146 intel_crtc->bpp = 24; /* default for pre-Ironlake */
6147
6148 if (HAS_PCH_SPLIT(dev)) {
6149 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6150 intel_helper_funcs.commit = ironlake_crtc_commit;
6151 } else {
6152 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6153 intel_helper_funcs.commit = i9xx_crtc_commit;
6154 }
6155
6156 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6157
6158 intel_crtc->busy = false;
6159
6160 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6161 (unsigned long)intel_crtc);
6162 }
6163
6164 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
6165 struct drm_file *file)
6166 {
6167 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
6168 struct drm_mode_object *drmmode_obj;
6169 struct intel_crtc *crtc;
6170
6171 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6172 return -ENODEV;
6173
6174 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6175 DRM_MODE_OBJECT_CRTC);
6176
6177 if (!drmmode_obj) {
6178 DRM_ERROR("no such CRTC id\n");
6179 return -EINVAL;
6180 }
6181
6182 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6183 pipe_from_crtc_id->pipe = crtc->pipe;
6184
6185 return 0;
6186 }
6187
6188 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
6189 {
6190 struct intel_encoder *encoder;
6191 int index_mask = 0;
6192 int entry = 0;
6193
6194 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6195 if (type_mask & encoder->clone_mask)
6196 index_mask |= (1 << entry);
6197 entry++;
6198 }
6199
6200 return index_mask;
6201 }
6202
6203 static bool has_edp_a(struct drm_device *dev)
6204 {
6205 struct drm_i915_private *dev_priv = dev->dev_private;
6206
6207 if (!IS_MOBILE(dev))
6208 return false;
6209
6210 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6211 return false;
6212
6213 if (IS_GEN5(dev) &&
6214 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6215 return false;
6216
6217 return true;
6218 }
6219
6220 static void intel_setup_outputs(struct drm_device *dev)
6221 {
6222 struct drm_i915_private *dev_priv = dev->dev_private;
6223 struct intel_encoder *encoder;
6224 bool dpd_is_edp = false;
6225 bool has_lvds;
6226
6227 has_lvds = intel_lvds_init(dev);
6228 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6229 /* disable the panel fitter on everything but LVDS */
6230 I915_WRITE(PFIT_CONTROL, 0);
6231 }
6232
6233 if (HAS_PCH_SPLIT(dev)) {
6234 dpd_is_edp = intel_dpd_is_edp(dev);
6235
6236 if (has_edp_a(dev))
6237 intel_dp_init(dev, DP_A);
6238
6239 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6240 intel_dp_init(dev, PCH_DP_D);
6241 }
6242
6243 intel_crt_init(dev);
6244
6245 if (HAS_PCH_SPLIT(dev)) {
6246 int found;
6247
6248 if (I915_READ(HDMIB) & PORT_DETECTED) {
6249 /* PCH SDVOB multiplex with HDMIB */
6250 found = intel_sdvo_init(dev, PCH_SDVOB, true);
6251 if (!found)
6252 intel_hdmi_init(dev, HDMIB);
6253 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6254 intel_dp_init(dev, PCH_DP_B);
6255 }
6256
6257 if (I915_READ(HDMIC) & PORT_DETECTED)
6258 intel_hdmi_init(dev, HDMIC);
6259
6260 if (I915_READ(HDMID) & PORT_DETECTED)
6261 intel_hdmi_init(dev, HDMID);
6262
6263 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6264 intel_dp_init(dev, PCH_DP_C);
6265
6266 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6267 intel_dp_init(dev, PCH_DP_D);
6268
6269 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
6270 bool found = false;
6271
6272 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6273 DRM_DEBUG_KMS("probing SDVOB\n");
6274 found = intel_sdvo_init(dev, SDVOB, true);
6275 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6276 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
6277 intel_hdmi_init(dev, SDVOB);
6278 }
6279
6280 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6281 DRM_DEBUG_KMS("probing DP_B\n");
6282 intel_dp_init(dev, DP_B);
6283 }
6284 }
6285
6286 /* Before G4X SDVOC doesn't have its own detect register */
6287
6288 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6289 DRM_DEBUG_KMS("probing SDVOC\n");
6290 found = intel_sdvo_init(dev, SDVOC, false);
6291 }
6292
6293 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6294
6295 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6296 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
6297 intel_hdmi_init(dev, SDVOC);
6298 }
6299 if (SUPPORTS_INTEGRATED_DP(dev)) {
6300 DRM_DEBUG_KMS("probing DP_C\n");
6301 intel_dp_init(dev, DP_C);
6302 }
6303 }
6304
6305 if (SUPPORTS_INTEGRATED_DP(dev) &&
6306 (I915_READ(DP_D) & DP_DETECTED)) {
6307 DRM_DEBUG_KMS("probing DP_D\n");
6308 intel_dp_init(dev, DP_D);
6309 }
6310 } else if (IS_GEN2(dev))
6311 intel_dvo_init(dev);
6312
6313 if (SUPPORTS_TV(dev))
6314 intel_tv_init(dev);
6315
6316 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6317 encoder->base.possible_crtcs = encoder->crtc_mask;
6318 encoder->base.possible_clones =
6319 intel_encoder_clones(dev, encoder->clone_mask);
6320 }
6321
6322 /* disable all the possible outputs/crtcs before entering KMS mode */
6323 drm_helper_disable_unused_functions(dev);
6324
6325 if (HAS_PCH_SPLIT(dev))
6326 ironlake_init_pch_refclk(dev);
6327 }
6328
6329 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6330 {
6331 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6332
6333 drm_framebuffer_cleanup(fb);
6334 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
6335
6336 kfree(intel_fb);
6337 }
6338
6339 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
6340 struct drm_file *file,
6341 unsigned int *handle)
6342 {
6343 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6344 struct drm_i915_gem_object *obj = intel_fb->obj;
6345
6346 return drm_gem_handle_create(file, &obj->base, handle);
6347 }
6348
6349 static const struct drm_framebuffer_funcs intel_fb_funcs = {
6350 .destroy = intel_user_framebuffer_destroy,
6351 .create_handle = intel_user_framebuffer_create_handle,
6352 };
6353
6354 int intel_framebuffer_init(struct drm_device *dev,
6355 struct intel_framebuffer *intel_fb,
6356 struct drm_mode_fb_cmd2 *mode_cmd,
6357 struct drm_i915_gem_object *obj)
6358 {
6359 int ret;
6360
6361 if (obj->tiling_mode == I915_TILING_Y)
6362 return -EINVAL;
6363
6364 if (mode_cmd->pitches[0] & 63)
6365 return -EINVAL;
6366
6367 switch (mode_cmd->pixel_format) {
6368 case DRM_FORMAT_RGB332:
6369 case DRM_FORMAT_RGB565:
6370 case DRM_FORMAT_XRGB8888:
6371 case DRM_FORMAT_XBGR8888:
6372 case DRM_FORMAT_ARGB8888:
6373 case DRM_FORMAT_XRGB2101010:
6374 case DRM_FORMAT_ARGB2101010:
6375 /* RGB formats are common across chipsets */
6376 break;
6377 case DRM_FORMAT_YUYV:
6378 case DRM_FORMAT_UYVY:
6379 case DRM_FORMAT_YVYU:
6380 case DRM_FORMAT_VYUY:
6381 break;
6382 default:
6383 DRM_DEBUG_KMS("unsupported pixel format %u\n",
6384 mode_cmd->pixel_format);
6385 return -EINVAL;
6386 }
6387
6388 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6389 if (ret) {
6390 DRM_ERROR("framebuffer init failed %d\n", ret);
6391 return ret;
6392 }
6393
6394 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
6395 intel_fb->obj = obj;
6396 return 0;
6397 }
6398
6399 static struct drm_framebuffer *
6400 intel_user_framebuffer_create(struct drm_device *dev,
6401 struct drm_file *filp,
6402 struct drm_mode_fb_cmd2 *mode_cmd)
6403 {
6404 struct drm_i915_gem_object *obj;
6405
6406 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
6407 mode_cmd->handles[0]));
6408 if (&obj->base == NULL)
6409 return ERR_PTR(-ENOENT);
6410
6411 return intel_framebuffer_create(dev, mode_cmd, obj);
6412 }
6413
6414 static const struct drm_mode_config_funcs intel_mode_funcs = {
6415 .fb_create = intel_user_framebuffer_create,
6416 .output_poll_changed = intel_fb_output_poll_changed,
6417 };
6418
6419 /* Set up chip specific display functions */
6420 static void intel_init_display(struct drm_device *dev)
6421 {
6422 struct drm_i915_private *dev_priv = dev->dev_private;
6423
6424 /* We always want a DPMS function */
6425 if (HAS_PCH_SPLIT(dev)) {
6426 dev_priv->display.dpms = ironlake_crtc_dpms;
6427 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
6428 dev_priv->display.off = ironlake_crtc_off;
6429 dev_priv->display.update_plane = ironlake_update_plane;
6430 } else {
6431 dev_priv->display.dpms = i9xx_crtc_dpms;
6432 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
6433 dev_priv->display.off = i9xx_crtc_off;
6434 dev_priv->display.update_plane = i9xx_update_plane;
6435 }
6436
6437 /* Returns the core display clock speed */
6438 if (IS_VALLEYVIEW(dev))
6439 dev_priv->display.get_display_clock_speed =
6440 valleyview_get_display_clock_speed;
6441 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
6442 dev_priv->display.get_display_clock_speed =
6443 i945_get_display_clock_speed;
6444 else if (IS_I915G(dev))
6445 dev_priv->display.get_display_clock_speed =
6446 i915_get_display_clock_speed;
6447 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
6448 dev_priv->display.get_display_clock_speed =
6449 i9xx_misc_get_display_clock_speed;
6450 else if (IS_I915GM(dev))
6451 dev_priv->display.get_display_clock_speed =
6452 i915gm_get_display_clock_speed;
6453 else if (IS_I865G(dev))
6454 dev_priv->display.get_display_clock_speed =
6455 i865_get_display_clock_speed;
6456 else if (IS_I85X(dev))
6457 dev_priv->display.get_display_clock_speed =
6458 i855_get_display_clock_speed;
6459 else /* 852, 830 */
6460 dev_priv->display.get_display_clock_speed =
6461 i830_get_display_clock_speed;
6462
6463 if (HAS_PCH_SPLIT(dev)) {
6464 if (IS_GEN5(dev)) {
6465 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
6466 dev_priv->display.write_eld = ironlake_write_eld;
6467 } else if (IS_GEN6(dev)) {
6468 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
6469 dev_priv->display.write_eld = ironlake_write_eld;
6470 } else if (IS_IVYBRIDGE(dev)) {
6471 /* FIXME: detect B0+ stepping and use auto training */
6472 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
6473 dev_priv->display.write_eld = ironlake_write_eld;
6474 } else
6475 dev_priv->display.update_wm = NULL;
6476 } else if (IS_VALLEYVIEW(dev)) {
6477 dev_priv->display.force_wake_get = vlv_force_wake_get;
6478 dev_priv->display.force_wake_put = vlv_force_wake_put;
6479 } else if (IS_G4X(dev)) {
6480 dev_priv->display.write_eld = g4x_write_eld;
6481 }
6482
6483 /* Default just returns -ENODEV to indicate unsupported */
6484 dev_priv->display.queue_flip = intel_default_queue_flip;
6485
6486 switch (INTEL_INFO(dev)->gen) {
6487 case 2:
6488 dev_priv->display.queue_flip = intel_gen2_queue_flip;
6489 break;
6490
6491 case 3:
6492 dev_priv->display.queue_flip = intel_gen3_queue_flip;
6493 break;
6494
6495 case 4:
6496 case 5:
6497 dev_priv->display.queue_flip = intel_gen4_queue_flip;
6498 break;
6499
6500 case 6:
6501 dev_priv->display.queue_flip = intel_gen6_queue_flip;
6502 break;
6503 case 7:
6504 dev_priv->display.queue_flip = intel_gen7_queue_flip;
6505 break;
6506 }
6507 }
6508
6509 /*
6510 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
6511 * resume, or other times. This quirk makes sure that's the case for
6512 * affected systems.
6513 */
6514 static void quirk_pipea_force(struct drm_device *dev)
6515 {
6516 struct drm_i915_private *dev_priv = dev->dev_private;
6517
6518 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
6519 DRM_INFO("applying pipe a force quirk\n");
6520 }
6521
6522 /*
6523 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
6524 */
6525 static void quirk_ssc_force_disable(struct drm_device *dev)
6526 {
6527 struct drm_i915_private *dev_priv = dev->dev_private;
6528 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
6529 DRM_INFO("applying lvds SSC disable quirk\n");
6530 }
6531
6532 /*
6533 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
6534 * brightness value
6535 */
6536 static void quirk_invert_brightness(struct drm_device *dev)
6537 {
6538 struct drm_i915_private *dev_priv = dev->dev_private;
6539 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
6540 DRM_INFO("applying inverted panel brightness quirk\n");
6541 }
6542
6543 struct intel_quirk {
6544 int device;
6545 int subsystem_vendor;
6546 int subsystem_device;
6547 void (*hook)(struct drm_device *dev);
6548 };
6549
6550 static struct intel_quirk intel_quirks[] = {
6551 /* HP Mini needs pipe A force quirk (LP: #322104) */
6552 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
6553
6554 /* Thinkpad R31 needs pipe A force quirk */
6555 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
6556 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
6557 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
6558
6559 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
6560 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
6561 /* ThinkPad X40 needs pipe A force quirk */
6562
6563 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6564 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
6565
6566 /* 855 & before need to leave pipe A & dpll A up */
6567 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6568 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6569
6570 /* Lenovo U160 cannot use SSC on LVDS */
6571 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
6572
6573 /* Sony Vaio Y cannot use SSC on LVDS */
6574 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
6575
6576 /* Acer Aspire 5734Z must invert backlight brightness */
6577 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
6578 };
6579
6580 static void intel_init_quirks(struct drm_device *dev)
6581 {
6582 struct pci_dev *d = dev->pdev;
6583 int i;
6584
6585 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
6586 struct intel_quirk *q = &intel_quirks[i];
6587
6588 if (d->device == q->device &&
6589 (d->subsystem_vendor == q->subsystem_vendor ||
6590 q->subsystem_vendor == PCI_ANY_ID) &&
6591 (d->subsystem_device == q->subsystem_device ||
6592 q->subsystem_device == PCI_ANY_ID))
6593 q->hook(dev);
6594 }
6595 }
6596
6597 /* Disable the VGA plane that we never use */
6598 static void i915_disable_vga(struct drm_device *dev)
6599 {
6600 struct drm_i915_private *dev_priv = dev->dev_private;
6601 u8 sr1;
6602 u32 vga_reg;
6603
6604 if (HAS_PCH_SPLIT(dev))
6605 vga_reg = CPU_VGACNTRL;
6606 else
6607 vga_reg = VGACNTRL;
6608
6609 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6610 outb(SR01, VGA_SR_INDEX);
6611 sr1 = inb(VGA_SR_DATA);
6612 outb(sr1 | 1<<5, VGA_SR_DATA);
6613 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6614 udelay(300);
6615
6616 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6617 POSTING_READ(vga_reg);
6618 }
6619
6620 static void ivb_pch_pwm_override(struct drm_device *dev)
6621 {
6622 struct drm_i915_private *dev_priv = dev->dev_private;
6623
6624 /*
6625 * IVB has CPU eDP backlight regs too, set things up to let the
6626 * PCH regs control the backlight
6627 */
6628 I915_WRITE(BLC_PWM_CPU_CTL2, PWM_ENABLE);
6629 I915_WRITE(BLC_PWM_CPU_CTL, 0);
6630 I915_WRITE(BLC_PWM_PCH_CTL1, PWM_ENABLE | (1<<30));
6631 }
6632
6633 void intel_modeset_init_hw(struct drm_device *dev)
6634 {
6635 struct drm_i915_private *dev_priv = dev->dev_private;
6636
6637 intel_init_clock_gating(dev);
6638
6639 if (IS_IRONLAKE_M(dev)) {
6640 ironlake_enable_drps(dev);
6641 intel_init_emon(dev);
6642 }
6643
6644 if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
6645 gen6_enable_rps(dev_priv);
6646 gen6_update_ring_freq(dev_priv);
6647 }
6648
6649 if (IS_IVYBRIDGE(dev))
6650 ivb_pch_pwm_override(dev);
6651 }
6652
6653 void intel_modeset_init(struct drm_device *dev)
6654 {
6655 struct drm_i915_private *dev_priv = dev->dev_private;
6656 int i, ret;
6657
6658 drm_mode_config_init(dev);
6659
6660 dev->mode_config.min_width = 0;
6661 dev->mode_config.min_height = 0;
6662
6663 dev->mode_config.preferred_depth = 24;
6664 dev->mode_config.prefer_shadow = 1;
6665
6666 dev->mode_config.funcs = (void *)&intel_mode_funcs;
6667
6668 intel_init_quirks(dev);
6669
6670 intel_init_pm(dev);
6671
6672 intel_init_display(dev);
6673
6674 if (IS_GEN2(dev)) {
6675 dev->mode_config.max_width = 2048;
6676 dev->mode_config.max_height = 2048;
6677 } else if (IS_GEN3(dev)) {
6678 dev->mode_config.max_width = 4096;
6679 dev->mode_config.max_height = 4096;
6680 } else {
6681 dev->mode_config.max_width = 8192;
6682 dev->mode_config.max_height = 8192;
6683 }
6684 dev->mode_config.fb_base = dev->agp->base;
6685
6686 DRM_DEBUG_KMS("%d display pipe%s available.\n",
6687 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6688
6689 for (i = 0; i < dev_priv->num_pipe; i++) {
6690 intel_crtc_init(dev, i);
6691 ret = intel_plane_init(dev, i);
6692 if (ret)
6693 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
6694 }
6695
6696 intel_pch_pll_init(dev);
6697
6698 /* Just disable it once at startup */
6699 i915_disable_vga(dev);
6700 intel_setup_outputs(dev);
6701
6702 intel_modeset_init_hw(dev);
6703
6704 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6705 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6706 (unsigned long)dev);
6707 }
6708
6709 void intel_modeset_gem_init(struct drm_device *dev)
6710 {
6711 if (IS_IRONLAKE_M(dev))
6712 ironlake_enable_rc6(dev);
6713
6714 intel_setup_overlay(dev);
6715 }
6716
6717 void intel_modeset_cleanup(struct drm_device *dev)
6718 {
6719 struct drm_i915_private *dev_priv = dev->dev_private;
6720 struct drm_crtc *crtc;
6721 struct intel_crtc *intel_crtc;
6722
6723 drm_kms_helper_poll_fini(dev);
6724 mutex_lock(&dev->struct_mutex);
6725
6726 intel_unregister_dsm_handler();
6727
6728
6729 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6730 /* Skip inactive CRTCs */
6731 if (!crtc->fb)
6732 continue;
6733
6734 intel_crtc = to_intel_crtc(crtc);
6735 intel_increase_pllclock(crtc);
6736 }
6737
6738 intel_disable_fbc(dev);
6739
6740 if (IS_IRONLAKE_M(dev))
6741 ironlake_disable_drps(dev);
6742 if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev))
6743 gen6_disable_rps(dev);
6744
6745 if (IS_IRONLAKE_M(dev))
6746 ironlake_disable_rc6(dev);
6747
6748 if (IS_VALLEYVIEW(dev))
6749 vlv_init_dpio(dev);
6750
6751 mutex_unlock(&dev->struct_mutex);
6752
6753 /* Disable the irq before mode object teardown, for the irq might
6754 * enqueue unpin/hotplug work. */
6755 drm_irq_uninstall(dev);
6756 cancel_work_sync(&dev_priv->hotplug_work);
6757 cancel_work_sync(&dev_priv->rps_work);
6758
6759 /* flush any delayed tasks or pending work */
6760 flush_scheduled_work();
6761
6762 /* Shut off idle work before the crtcs get freed. */
6763 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6764 intel_crtc = to_intel_crtc(crtc);
6765 del_timer_sync(&intel_crtc->idle_timer);
6766 }
6767 del_timer_sync(&dev_priv->idle_timer);
6768 cancel_work_sync(&dev_priv->idle_work);
6769
6770 drm_mode_config_cleanup(dev);
6771 }
6772
6773 /*
6774 * Return which encoder is currently attached for connector.
6775 */
6776 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
6777 {
6778 return &intel_attached_encoder(connector)->base;
6779 }
6780
6781 void intel_connector_attach_encoder(struct intel_connector *connector,
6782 struct intel_encoder *encoder)
6783 {
6784 connector->encoder = encoder;
6785 drm_mode_connector_attach_encoder(&connector->base,
6786 &encoder->base);
6787 }
6788
6789 /*
6790 * set vga decode state - true == enable VGA decode
6791 */
6792 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6793 {
6794 struct drm_i915_private *dev_priv = dev->dev_private;
6795 u16 gmch_ctrl;
6796
6797 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6798 if (state)
6799 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6800 else
6801 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6802 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6803 return 0;
6804 }
6805
6806 #ifdef CONFIG_DEBUG_FS
6807 #include <linux/seq_file.h>
6808
6809 struct intel_display_error_state {
6810 struct intel_cursor_error_state {
6811 u32 control;
6812 u32 position;
6813 u32 base;
6814 u32 size;
6815 } cursor[2];
6816
6817 struct intel_pipe_error_state {
6818 u32 conf;
6819 u32 source;
6820
6821 u32 htotal;
6822 u32 hblank;
6823 u32 hsync;
6824 u32 vtotal;
6825 u32 vblank;
6826 u32 vsync;
6827 } pipe[2];
6828
6829 struct intel_plane_error_state {
6830 u32 control;
6831 u32 stride;
6832 u32 size;
6833 u32 pos;
6834 u32 addr;
6835 u32 surface;
6836 u32 tile_offset;
6837 } plane[2];
6838 };
6839
6840 struct intel_display_error_state *
6841 intel_display_capture_error_state(struct drm_device *dev)
6842 {
6843 drm_i915_private_t *dev_priv = dev->dev_private;
6844 struct intel_display_error_state *error;
6845 int i;
6846
6847 error = kmalloc(sizeof(*error), GFP_ATOMIC);
6848 if (error == NULL)
6849 return NULL;
6850
6851 for (i = 0; i < 2; i++) {
6852 error->cursor[i].control = I915_READ(CURCNTR(i));
6853 error->cursor[i].position = I915_READ(CURPOS(i));
6854 error->cursor[i].base = I915_READ(CURBASE(i));
6855
6856 error->plane[i].control = I915_READ(DSPCNTR(i));
6857 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
6858 error->plane[i].size = I915_READ(DSPSIZE(i));
6859 error->plane[i].pos = I915_READ(DSPPOS(i));
6860 error->plane[i].addr = I915_READ(DSPADDR(i));
6861 if (INTEL_INFO(dev)->gen >= 4) {
6862 error->plane[i].surface = I915_READ(DSPSURF(i));
6863 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
6864 }
6865
6866 error->pipe[i].conf = I915_READ(PIPECONF(i));
6867 error->pipe[i].source = I915_READ(PIPESRC(i));
6868 error->pipe[i].htotal = I915_READ(HTOTAL(i));
6869 error->pipe[i].hblank = I915_READ(HBLANK(i));
6870 error->pipe[i].hsync = I915_READ(HSYNC(i));
6871 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
6872 error->pipe[i].vblank = I915_READ(VBLANK(i));
6873 error->pipe[i].vsync = I915_READ(VSYNC(i));
6874 }
6875
6876 return error;
6877 }
6878
6879 void
6880 intel_display_print_error_state(struct seq_file *m,
6881 struct drm_device *dev,
6882 struct intel_display_error_state *error)
6883 {
6884 int i;
6885
6886 for (i = 0; i < 2; i++) {
6887 seq_printf(m, "Pipe [%d]:\n", i);
6888 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
6889 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
6890 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
6891 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
6892 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
6893 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
6894 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
6895 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
6896
6897 seq_printf(m, "Plane [%d]:\n", i);
6898 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
6899 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
6900 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
6901 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
6902 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
6903 if (INTEL_INFO(dev)->gen >= 4) {
6904 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
6905 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
6906 }
6907
6908 seq_printf(m, "Cursor [%d]:\n", i);
6909 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
6910 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
6911 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
6912 }
6913 }
6914 #endif
Linux kernel - Deliverables
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