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afceb5836af7251c19cd1dd8ef21883232deb25a
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
47
48 /* Primary plane formats supported by all gen */
49 #define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_C8, \
51 DRM_FORMAT_RGB565, \
52 DRM_FORMAT_XRGB8888, \
53 DRM_FORMAT_ARGB8888
54
55 /* Primary plane formats for gen <= 3 */
56 static const uint32_t intel_primary_formats_gen2[] = {
57 COMMON_PRIMARY_FORMATS,
58 DRM_FORMAT_XRGB1555,
59 DRM_FORMAT_ARGB1555,
60 };
61
62 /* Primary plane formats for gen >= 4 */
63 static const uint32_t intel_primary_formats_gen4[] = {
64 COMMON_PRIMARY_FORMATS, \
65 DRM_FORMAT_XBGR8888,
66 DRM_FORMAT_ABGR8888,
67 DRM_FORMAT_XRGB2101010,
68 DRM_FORMAT_ARGB2101010,
69 DRM_FORMAT_XBGR2101010,
70 DRM_FORMAT_ABGR2101010,
71 };
72
73 /* Cursor formats */
74 static const uint32_t intel_cursor_formats[] = {
75 DRM_FORMAT_ARGB8888,
76 };
77
78 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79
80 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
81 struct intel_crtc_state *pipe_config);
82 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
83 struct intel_crtc_state *pipe_config);
84
85 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
86 int x, int y, struct drm_framebuffer *old_fb,
87 struct drm_atomic_state *state);
88 static int intel_framebuffer_init(struct drm_device *dev,
89 struct intel_framebuffer *ifb,
90 struct drm_mode_fb_cmd2 *mode_cmd,
91 struct drm_i915_gem_object *obj);
92 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
93 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
94 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
95 struct intel_link_m_n *m_n,
96 struct intel_link_m_n *m2_n2);
97 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
98 static void haswell_set_pipeconf(struct drm_crtc *crtc);
99 static void intel_set_pipe_csc(struct drm_crtc *crtc);
100 static void vlv_prepare_pll(struct intel_crtc *crtc,
101 const struct intel_crtc_state *pipe_config);
102 static void chv_prepare_pll(struct intel_crtc *crtc,
103 const struct intel_crtc_state *pipe_config);
104 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
105 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
106
107 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
108 {
109 if (!connector->mst_port)
110 return connector->encoder;
111 else
112 return &connector->mst_port->mst_encoders[pipe]->base;
113 }
114
115 typedef struct {
116 int min, max;
117 } intel_range_t;
118
119 typedef struct {
120 int dot_limit;
121 int p2_slow, p2_fast;
122 } intel_p2_t;
123
124 typedef struct intel_limit intel_limit_t;
125 struct intel_limit {
126 intel_range_t dot, vco, n, m, m1, m2, p, p1;
127 intel_p2_t p2;
128 };
129
130 int
131 intel_pch_rawclk(struct drm_device *dev)
132 {
133 struct drm_i915_private *dev_priv = dev->dev_private;
134
135 WARN_ON(!HAS_PCH_SPLIT(dev));
136
137 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
138 }
139
140 static inline u32 /* units of 100MHz */
141 intel_fdi_link_freq(struct drm_device *dev)
142 {
143 if (IS_GEN5(dev)) {
144 struct drm_i915_private *dev_priv = dev->dev_private;
145 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
146 } else
147 return 27;
148 }
149
150 static const intel_limit_t intel_limits_i8xx_dac = {
151 .dot = { .min = 25000, .max = 350000 },
152 .vco = { .min = 908000, .max = 1512000 },
153 .n = { .min = 2, .max = 16 },
154 .m = { .min = 96, .max = 140 },
155 .m1 = { .min = 18, .max = 26 },
156 .m2 = { .min = 6, .max = 16 },
157 .p = { .min = 4, .max = 128 },
158 .p1 = { .min = 2, .max = 33 },
159 .p2 = { .dot_limit = 165000,
160 .p2_slow = 4, .p2_fast = 2 },
161 };
162
163 static const intel_limit_t intel_limits_i8xx_dvo = {
164 .dot = { .min = 25000, .max = 350000 },
165 .vco = { .min = 908000, .max = 1512000 },
166 .n = { .min = 2, .max = 16 },
167 .m = { .min = 96, .max = 140 },
168 .m1 = { .min = 18, .max = 26 },
169 .m2 = { .min = 6, .max = 16 },
170 .p = { .min = 4, .max = 128 },
171 .p1 = { .min = 2, .max = 33 },
172 .p2 = { .dot_limit = 165000,
173 .p2_slow = 4, .p2_fast = 4 },
174 };
175
176 static const intel_limit_t intel_limits_i8xx_lvds = {
177 .dot = { .min = 25000, .max = 350000 },
178 .vco = { .min = 908000, .max = 1512000 },
179 .n = { .min = 2, .max = 16 },
180 .m = { .min = 96, .max = 140 },
181 .m1 = { .min = 18, .max = 26 },
182 .m2 = { .min = 6, .max = 16 },
183 .p = { .min = 4, .max = 128 },
184 .p1 = { .min = 1, .max = 6 },
185 .p2 = { .dot_limit = 165000,
186 .p2_slow = 14, .p2_fast = 7 },
187 };
188
189 static const intel_limit_t intel_limits_i9xx_sdvo = {
190 .dot = { .min = 20000, .max = 400000 },
191 .vco = { .min = 1400000, .max = 2800000 },
192 .n = { .min = 1, .max = 6 },
193 .m = { .min = 70, .max = 120 },
194 .m1 = { .min = 8, .max = 18 },
195 .m2 = { .min = 3, .max = 7 },
196 .p = { .min = 5, .max = 80 },
197 .p1 = { .min = 1, .max = 8 },
198 .p2 = { .dot_limit = 200000,
199 .p2_slow = 10, .p2_fast = 5 },
200 };
201
202 static const intel_limit_t intel_limits_i9xx_lvds = {
203 .dot = { .min = 20000, .max = 400000 },
204 .vco = { .min = 1400000, .max = 2800000 },
205 .n = { .min = 1, .max = 6 },
206 .m = { .min = 70, .max = 120 },
207 .m1 = { .min = 8, .max = 18 },
208 .m2 = { .min = 3, .max = 7 },
209 .p = { .min = 7, .max = 98 },
210 .p1 = { .min = 1, .max = 8 },
211 .p2 = { .dot_limit = 112000,
212 .p2_slow = 14, .p2_fast = 7 },
213 };
214
215
216 static const intel_limit_t intel_limits_g4x_sdvo = {
217 .dot = { .min = 25000, .max = 270000 },
218 .vco = { .min = 1750000, .max = 3500000},
219 .n = { .min = 1, .max = 4 },
220 .m = { .min = 104, .max = 138 },
221 .m1 = { .min = 17, .max = 23 },
222 .m2 = { .min = 5, .max = 11 },
223 .p = { .min = 10, .max = 30 },
224 .p1 = { .min = 1, .max = 3},
225 .p2 = { .dot_limit = 270000,
226 .p2_slow = 10,
227 .p2_fast = 10
228 },
229 };
230
231 static const intel_limit_t intel_limits_g4x_hdmi = {
232 .dot = { .min = 22000, .max = 400000 },
233 .vco = { .min = 1750000, .max = 3500000},
234 .n = { .min = 1, .max = 4 },
235 .m = { .min = 104, .max = 138 },
236 .m1 = { .min = 16, .max = 23 },
237 .m2 = { .min = 5, .max = 11 },
238 .p = { .min = 5, .max = 80 },
239 .p1 = { .min = 1, .max = 8},
240 .p2 = { .dot_limit = 165000,
241 .p2_slow = 10, .p2_fast = 5 },
242 };
243
244 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
245 .dot = { .min = 20000, .max = 115000 },
246 .vco = { .min = 1750000, .max = 3500000 },
247 .n = { .min = 1, .max = 3 },
248 .m = { .min = 104, .max = 138 },
249 .m1 = { .min = 17, .max = 23 },
250 .m2 = { .min = 5, .max = 11 },
251 .p = { .min = 28, .max = 112 },
252 .p1 = { .min = 2, .max = 8 },
253 .p2 = { .dot_limit = 0,
254 .p2_slow = 14, .p2_fast = 14
255 },
256 };
257
258 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
259 .dot = { .min = 80000, .max = 224000 },
260 .vco = { .min = 1750000, .max = 3500000 },
261 .n = { .min = 1, .max = 3 },
262 .m = { .min = 104, .max = 138 },
263 .m1 = { .min = 17, .max = 23 },
264 .m2 = { .min = 5, .max = 11 },
265 .p = { .min = 14, .max = 42 },
266 .p1 = { .min = 2, .max = 6 },
267 .p2 = { .dot_limit = 0,
268 .p2_slow = 7, .p2_fast = 7
269 },
270 };
271
272 static const intel_limit_t intel_limits_pineview_sdvo = {
273 .dot = { .min = 20000, .max = 400000},
274 .vco = { .min = 1700000, .max = 3500000 },
275 /* Pineview's Ncounter is a ring counter */
276 .n = { .min = 3, .max = 6 },
277 .m = { .min = 2, .max = 256 },
278 /* Pineview only has one combined m divider, which we treat as m2. */
279 .m1 = { .min = 0, .max = 0 },
280 .m2 = { .min = 0, .max = 254 },
281 .p = { .min = 5, .max = 80 },
282 .p1 = { .min = 1, .max = 8 },
283 .p2 = { .dot_limit = 200000,
284 .p2_slow = 10, .p2_fast = 5 },
285 };
286
287 static const intel_limit_t intel_limits_pineview_lvds = {
288 .dot = { .min = 20000, .max = 400000 },
289 .vco = { .min = 1700000, .max = 3500000 },
290 .n = { .min = 3, .max = 6 },
291 .m = { .min = 2, .max = 256 },
292 .m1 = { .min = 0, .max = 0 },
293 .m2 = { .min = 0, .max = 254 },
294 .p = { .min = 7, .max = 112 },
295 .p1 = { .min = 1, .max = 8 },
296 .p2 = { .dot_limit = 112000,
297 .p2_slow = 14, .p2_fast = 14 },
298 };
299
300 /* Ironlake / Sandybridge
301 *
302 * We calculate clock using (register_value + 2) for N/M1/M2, so here
303 * the range value for them is (actual_value - 2).
304 */
305 static const intel_limit_t intel_limits_ironlake_dac = {
306 .dot = { .min = 25000, .max = 350000 },
307 .vco = { .min = 1760000, .max = 3510000 },
308 .n = { .min = 1, .max = 5 },
309 .m = { .min = 79, .max = 127 },
310 .m1 = { .min = 12, .max = 22 },
311 .m2 = { .min = 5, .max = 9 },
312 .p = { .min = 5, .max = 80 },
313 .p1 = { .min = 1, .max = 8 },
314 .p2 = { .dot_limit = 225000,
315 .p2_slow = 10, .p2_fast = 5 },
316 };
317
318 static const intel_limit_t intel_limits_ironlake_single_lvds = {
319 .dot = { .min = 25000, .max = 350000 },
320 .vco = { .min = 1760000, .max = 3510000 },
321 .n = { .min = 1, .max = 3 },
322 .m = { .min = 79, .max = 118 },
323 .m1 = { .min = 12, .max = 22 },
324 .m2 = { .min = 5, .max = 9 },
325 .p = { .min = 28, .max = 112 },
326 .p1 = { .min = 2, .max = 8 },
327 .p2 = { .dot_limit = 225000,
328 .p2_slow = 14, .p2_fast = 14 },
329 };
330
331 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
332 .dot = { .min = 25000, .max = 350000 },
333 .vco = { .min = 1760000, .max = 3510000 },
334 .n = { .min = 1, .max = 3 },
335 .m = { .min = 79, .max = 127 },
336 .m1 = { .min = 12, .max = 22 },
337 .m2 = { .min = 5, .max = 9 },
338 .p = { .min = 14, .max = 56 },
339 .p1 = { .min = 2, .max = 8 },
340 .p2 = { .dot_limit = 225000,
341 .p2_slow = 7, .p2_fast = 7 },
342 };
343
344 /* LVDS 100mhz refclk limits. */
345 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
346 .dot = { .min = 25000, .max = 350000 },
347 .vco = { .min = 1760000, .max = 3510000 },
348 .n = { .min = 1, .max = 2 },
349 .m = { .min = 79, .max = 126 },
350 .m1 = { .min = 12, .max = 22 },
351 .m2 = { .min = 5, .max = 9 },
352 .p = { .min = 28, .max = 112 },
353 .p1 = { .min = 2, .max = 8 },
354 .p2 = { .dot_limit = 225000,
355 .p2_slow = 14, .p2_fast = 14 },
356 };
357
358 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
359 .dot = { .min = 25000, .max = 350000 },
360 .vco = { .min = 1760000, .max = 3510000 },
361 .n = { .min = 1, .max = 3 },
362 .m = { .min = 79, .max = 126 },
363 .m1 = { .min = 12, .max = 22 },
364 .m2 = { .min = 5, .max = 9 },
365 .p = { .min = 14, .max = 42 },
366 .p1 = { .min = 2, .max = 6 },
367 .p2 = { .dot_limit = 225000,
368 .p2_slow = 7, .p2_fast = 7 },
369 };
370
371 static const intel_limit_t intel_limits_vlv = {
372 /*
373 * These are the data rate limits (measured in fast clocks)
374 * since those are the strictest limits we have. The fast
375 * clock and actual rate limits are more relaxed, so checking
376 * them would make no difference.
377 */
378 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
379 .vco = { .min = 4000000, .max = 6000000 },
380 .n = { .min = 1, .max = 7 },
381 .m1 = { .min = 2, .max = 3 },
382 .m2 = { .min = 11, .max = 156 },
383 .p1 = { .min = 2, .max = 3 },
384 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
385 };
386
387 static const intel_limit_t intel_limits_chv = {
388 /*
389 * These are the data rate limits (measured in fast clocks)
390 * since those are the strictest limits we have. The fast
391 * clock and actual rate limits are more relaxed, so checking
392 * them would make no difference.
393 */
394 .dot = { .min = 25000 * 5, .max = 540000 * 5},
395 .vco = { .min = 4800000, .max = 6480000 },
396 .n = { .min = 1, .max = 1 },
397 .m1 = { .min = 2, .max = 2 },
398 .m2 = { .min = 24 << 22, .max = 175 << 22 },
399 .p1 = { .min = 2, .max = 4 },
400 .p2 = { .p2_slow = 1, .p2_fast = 14 },
401 };
402
403 static void vlv_clock(int refclk, intel_clock_t *clock)
404 {
405 clock->m = clock->m1 * clock->m2;
406 clock->p = clock->p1 * clock->p2;
407 if (WARN_ON(clock->n == 0 || clock->p == 0))
408 return;
409 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
410 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
411 }
412
413 /**
414 * Returns whether any output on the specified pipe is of the specified type
415 */
416 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
417 {
418 struct drm_device *dev = crtc->base.dev;
419 struct intel_encoder *encoder;
420
421 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
422 if (encoder->type == type)
423 return true;
424
425 return false;
426 }
427
428 /**
429 * Returns whether any output on the specified pipe will have the specified
430 * type after a staged modeset is complete, i.e., the same as
431 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
432 * encoder->crtc.
433 */
434 static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
435 {
436 struct drm_device *dev = crtc->base.dev;
437 struct intel_encoder *encoder;
438
439 for_each_intel_encoder(dev, encoder)
440 if (encoder->new_crtc == crtc && encoder->type == type)
441 return true;
442
443 return false;
444 }
445
446 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
447 int refclk)
448 {
449 struct drm_device *dev = crtc->base.dev;
450 const intel_limit_t *limit;
451
452 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
453 if (intel_is_dual_link_lvds(dev)) {
454 if (refclk == 100000)
455 limit = &intel_limits_ironlake_dual_lvds_100m;
456 else
457 limit = &intel_limits_ironlake_dual_lvds;
458 } else {
459 if (refclk == 100000)
460 limit = &intel_limits_ironlake_single_lvds_100m;
461 else
462 limit = &intel_limits_ironlake_single_lvds;
463 }
464 } else
465 limit = &intel_limits_ironlake_dac;
466
467 return limit;
468 }
469
470 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
471 {
472 struct drm_device *dev = crtc->base.dev;
473 const intel_limit_t *limit;
474
475 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
476 if (intel_is_dual_link_lvds(dev))
477 limit = &intel_limits_g4x_dual_channel_lvds;
478 else
479 limit = &intel_limits_g4x_single_channel_lvds;
480 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
481 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
482 limit = &intel_limits_g4x_hdmi;
483 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
484 limit = &intel_limits_g4x_sdvo;
485 } else /* The option is for other outputs */
486 limit = &intel_limits_i9xx_sdvo;
487
488 return limit;
489 }
490
491 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
492 {
493 struct drm_device *dev = crtc->base.dev;
494 const intel_limit_t *limit;
495
496 if (HAS_PCH_SPLIT(dev))
497 limit = intel_ironlake_limit(crtc, refclk);
498 else if (IS_G4X(dev)) {
499 limit = intel_g4x_limit(crtc);
500 } else if (IS_PINEVIEW(dev)) {
501 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
502 limit = &intel_limits_pineview_lvds;
503 else
504 limit = &intel_limits_pineview_sdvo;
505 } else if (IS_CHERRYVIEW(dev)) {
506 limit = &intel_limits_chv;
507 } else if (IS_VALLEYVIEW(dev)) {
508 limit = &intel_limits_vlv;
509 } else if (!IS_GEN2(dev)) {
510 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
511 limit = &intel_limits_i9xx_lvds;
512 else
513 limit = &intel_limits_i9xx_sdvo;
514 } else {
515 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
516 limit = &intel_limits_i8xx_lvds;
517 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
518 limit = &intel_limits_i8xx_dvo;
519 else
520 limit = &intel_limits_i8xx_dac;
521 }
522 return limit;
523 }
524
525 /* m1 is reserved as 0 in Pineview, n is a ring counter */
526 static void pineview_clock(int refclk, intel_clock_t *clock)
527 {
528 clock->m = clock->m2 + 2;
529 clock->p = clock->p1 * clock->p2;
530 if (WARN_ON(clock->n == 0 || clock->p == 0))
531 return;
532 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
533 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
534 }
535
536 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
537 {
538 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
539 }
540
541 static void i9xx_clock(int refclk, intel_clock_t *clock)
542 {
543 clock->m = i9xx_dpll_compute_m(clock);
544 clock->p = clock->p1 * clock->p2;
545 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
546 return;
547 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
548 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
549 }
550
551 static void chv_clock(int refclk, intel_clock_t *clock)
552 {
553 clock->m = clock->m1 * clock->m2;
554 clock->p = clock->p1 * clock->p2;
555 if (WARN_ON(clock->n == 0 || clock->p == 0))
556 return;
557 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
558 clock->n << 22);
559 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
560 }
561
562 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
563 /**
564 * Returns whether the given set of divisors are valid for a given refclk with
565 * the given connectors.
566 */
567
568 static bool intel_PLL_is_valid(struct drm_device *dev,
569 const intel_limit_t *limit,
570 const intel_clock_t *clock)
571 {
572 if (clock->n < limit->n.min || limit->n.max < clock->n)
573 INTELPllInvalid("n out of range\n");
574 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
575 INTELPllInvalid("p1 out of range\n");
576 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
577 INTELPllInvalid("m2 out of range\n");
578 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
579 INTELPllInvalid("m1 out of range\n");
580
581 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
582 if (clock->m1 <= clock->m2)
583 INTELPllInvalid("m1 <= m2\n");
584
585 if (!IS_VALLEYVIEW(dev)) {
586 if (clock->p < limit->p.min || limit->p.max < clock->p)
587 INTELPllInvalid("p out of range\n");
588 if (clock->m < limit->m.min || limit->m.max < clock->m)
589 INTELPllInvalid("m out of range\n");
590 }
591
592 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
593 INTELPllInvalid("vco out of range\n");
594 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
595 * connector, etc., rather than just a single range.
596 */
597 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
598 INTELPllInvalid("dot out of range\n");
599
600 return true;
601 }
602
603 static bool
604 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
605 int target, int refclk, intel_clock_t *match_clock,
606 intel_clock_t *best_clock)
607 {
608 struct drm_device *dev = crtc->base.dev;
609 intel_clock_t clock;
610 int err = target;
611
612 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
613 /*
614 * For LVDS just rely on its current settings for dual-channel.
615 * We haven't figured out how to reliably set up different
616 * single/dual channel state, if we even can.
617 */
618 if (intel_is_dual_link_lvds(dev))
619 clock.p2 = limit->p2.p2_fast;
620 else
621 clock.p2 = limit->p2.p2_slow;
622 } else {
623 if (target < limit->p2.dot_limit)
624 clock.p2 = limit->p2.p2_slow;
625 else
626 clock.p2 = limit->p2.p2_fast;
627 }
628
629 memset(best_clock, 0, sizeof(*best_clock));
630
631 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
632 clock.m1++) {
633 for (clock.m2 = limit->m2.min;
634 clock.m2 <= limit->m2.max; clock.m2++) {
635 if (clock.m2 >= clock.m1)
636 break;
637 for (clock.n = limit->n.min;
638 clock.n <= limit->n.max; clock.n++) {
639 for (clock.p1 = limit->p1.min;
640 clock.p1 <= limit->p1.max; clock.p1++) {
641 int this_err;
642
643 i9xx_clock(refclk, &clock);
644 if (!intel_PLL_is_valid(dev, limit,
645 &clock))
646 continue;
647 if (match_clock &&
648 clock.p != match_clock->p)
649 continue;
650
651 this_err = abs(clock.dot - target);
652 if (this_err < err) {
653 *best_clock = clock;
654 err = this_err;
655 }
656 }
657 }
658 }
659 }
660
661 return (err != target);
662 }
663
664 static bool
665 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
666 int target, int refclk, intel_clock_t *match_clock,
667 intel_clock_t *best_clock)
668 {
669 struct drm_device *dev = crtc->base.dev;
670 intel_clock_t clock;
671 int err = target;
672
673 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
674 /*
675 * For LVDS just rely on its current settings for dual-channel.
676 * We haven't figured out how to reliably set up different
677 * single/dual channel state, if we even can.
678 */
679 if (intel_is_dual_link_lvds(dev))
680 clock.p2 = limit->p2.p2_fast;
681 else
682 clock.p2 = limit->p2.p2_slow;
683 } else {
684 if (target < limit->p2.dot_limit)
685 clock.p2 = limit->p2.p2_slow;
686 else
687 clock.p2 = limit->p2.p2_fast;
688 }
689
690 memset(best_clock, 0, sizeof(*best_clock));
691
692 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
693 clock.m1++) {
694 for (clock.m2 = limit->m2.min;
695 clock.m2 <= limit->m2.max; clock.m2++) {
696 for (clock.n = limit->n.min;
697 clock.n <= limit->n.max; clock.n++) {
698 for (clock.p1 = limit->p1.min;
699 clock.p1 <= limit->p1.max; clock.p1++) {
700 int this_err;
701
702 pineview_clock(refclk, &clock);
703 if (!intel_PLL_is_valid(dev, limit,
704 &clock))
705 continue;
706 if (match_clock &&
707 clock.p != match_clock->p)
708 continue;
709
710 this_err = abs(clock.dot - target);
711 if (this_err < err) {
712 *best_clock = clock;
713 err = this_err;
714 }
715 }
716 }
717 }
718 }
719
720 return (err != target);
721 }
722
723 static bool
724 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
725 int target, int refclk, intel_clock_t *match_clock,
726 intel_clock_t *best_clock)
727 {
728 struct drm_device *dev = crtc->base.dev;
729 intel_clock_t clock;
730 int max_n;
731 bool found;
732 /* approximately equals target * 0.00585 */
733 int err_most = (target >> 8) + (target >> 9);
734 found = false;
735
736 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
737 if (intel_is_dual_link_lvds(dev))
738 clock.p2 = limit->p2.p2_fast;
739 else
740 clock.p2 = limit->p2.p2_slow;
741 } else {
742 if (target < limit->p2.dot_limit)
743 clock.p2 = limit->p2.p2_slow;
744 else
745 clock.p2 = limit->p2.p2_fast;
746 }
747
748 memset(best_clock, 0, sizeof(*best_clock));
749 max_n = limit->n.max;
750 /* based on hardware requirement, prefer smaller n to precision */
751 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
752 /* based on hardware requirement, prefere larger m1,m2 */
753 for (clock.m1 = limit->m1.max;
754 clock.m1 >= limit->m1.min; clock.m1--) {
755 for (clock.m2 = limit->m2.max;
756 clock.m2 >= limit->m2.min; clock.m2--) {
757 for (clock.p1 = limit->p1.max;
758 clock.p1 >= limit->p1.min; clock.p1--) {
759 int this_err;
760
761 i9xx_clock(refclk, &clock);
762 if (!intel_PLL_is_valid(dev, limit,
763 &clock))
764 continue;
765
766 this_err = abs(clock.dot - target);
767 if (this_err < err_most) {
768 *best_clock = clock;
769 err_most = this_err;
770 max_n = clock.n;
771 found = true;
772 }
773 }
774 }
775 }
776 }
777 return found;
778 }
779
780 /*
781 * Check if the calculated PLL configuration is more optimal compared to the
782 * best configuration and error found so far. Return the calculated error.
783 */
784 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
785 const intel_clock_t *calculated_clock,
786 const intel_clock_t *best_clock,
787 unsigned int best_error_ppm,
788 unsigned int *error_ppm)
789 {
790 /*
791 * For CHV ignore the error and consider only the P value.
792 * Prefer a bigger P value based on HW requirements.
793 */
794 if (IS_CHERRYVIEW(dev)) {
795 *error_ppm = 0;
796
797 return calculated_clock->p > best_clock->p;
798 }
799
800 if (WARN_ON_ONCE(!target_freq))
801 return false;
802
803 *error_ppm = div_u64(1000000ULL *
804 abs(target_freq - calculated_clock->dot),
805 target_freq);
806 /*
807 * Prefer a better P value over a better (smaller) error if the error
808 * is small. Ensure this preference for future configurations too by
809 * setting the error to 0.
810 */
811 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
812 *error_ppm = 0;
813
814 return true;
815 }
816
817 return *error_ppm + 10 < best_error_ppm;
818 }
819
820 static bool
821 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
822 int target, int refclk, intel_clock_t *match_clock,
823 intel_clock_t *best_clock)
824 {
825 struct drm_device *dev = crtc->base.dev;
826 intel_clock_t clock;
827 unsigned int bestppm = 1000000;
828 /* min update 19.2 MHz */
829 int max_n = min(limit->n.max, refclk / 19200);
830 bool found = false;
831
832 target *= 5; /* fast clock */
833
834 memset(best_clock, 0, sizeof(*best_clock));
835
836 /* based on hardware requirement, prefer smaller n to precision */
837 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
838 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
839 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
840 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
841 clock.p = clock.p1 * clock.p2;
842 /* based on hardware requirement, prefer bigger m1,m2 values */
843 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
844 unsigned int ppm;
845
846 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
847 refclk * clock.m1);
848
849 vlv_clock(refclk, &clock);
850
851 if (!intel_PLL_is_valid(dev, limit,
852 &clock))
853 continue;
854
855 if (!vlv_PLL_is_optimal(dev, target,
856 &clock,
857 best_clock,
858 bestppm, &ppm))
859 continue;
860
861 *best_clock = clock;
862 bestppm = ppm;
863 found = true;
864 }
865 }
866 }
867 }
868
869 return found;
870 }
871
872 static bool
873 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
874 int target, int refclk, intel_clock_t *match_clock,
875 intel_clock_t *best_clock)
876 {
877 struct drm_device *dev = crtc->base.dev;
878 unsigned int best_error_ppm;
879 intel_clock_t clock;
880 uint64_t m2;
881 int found = false;
882
883 memset(best_clock, 0, sizeof(*best_clock));
884 best_error_ppm = 1000000;
885
886 /*
887 * Based on hardware doc, the n always set to 1, and m1 always
888 * set to 2. If requires to support 200Mhz refclk, we need to
889 * revisit this because n may not 1 anymore.
890 */
891 clock.n = 1, clock.m1 = 2;
892 target *= 5; /* fast clock */
893
894 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
895 for (clock.p2 = limit->p2.p2_fast;
896 clock.p2 >= limit->p2.p2_slow;
897 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
898 unsigned int error_ppm;
899
900 clock.p = clock.p1 * clock.p2;
901
902 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
903 clock.n) << 22, refclk * clock.m1);
904
905 if (m2 > INT_MAX/clock.m1)
906 continue;
907
908 clock.m2 = m2;
909
910 chv_clock(refclk, &clock);
911
912 if (!intel_PLL_is_valid(dev, limit, &clock))
913 continue;
914
915 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
916 best_error_ppm, &error_ppm))
917 continue;
918
919 *best_clock = clock;
920 best_error_ppm = error_ppm;
921 found = true;
922 }
923 }
924
925 return found;
926 }
927
928 bool intel_crtc_active(struct drm_crtc *crtc)
929 {
930 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
931
932 /* Be paranoid as we can arrive here with only partial
933 * state retrieved from the hardware during setup.
934 *
935 * We can ditch the adjusted_mode.crtc_clock check as soon
936 * as Haswell has gained clock readout/fastboot support.
937 *
938 * We can ditch the crtc->primary->fb check as soon as we can
939 * properly reconstruct framebuffers.
940 *
941 * FIXME: The intel_crtc->active here should be switched to
942 * crtc->state->active once we have proper CRTC states wired up
943 * for atomic.
944 */
945 return intel_crtc->active && crtc->primary->state->fb &&
946 intel_crtc->config->base.adjusted_mode.crtc_clock;
947 }
948
949 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
950 enum pipe pipe)
951 {
952 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
953 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
954
955 return intel_crtc->config->cpu_transcoder;
956 }
957
958 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
959 {
960 struct drm_i915_private *dev_priv = dev->dev_private;
961 u32 reg = PIPEDSL(pipe);
962 u32 line1, line2;
963 u32 line_mask;
964
965 if (IS_GEN2(dev))
966 line_mask = DSL_LINEMASK_GEN2;
967 else
968 line_mask = DSL_LINEMASK_GEN3;
969
970 line1 = I915_READ(reg) & line_mask;
971 mdelay(5);
972 line2 = I915_READ(reg) & line_mask;
973
974 return line1 == line2;
975 }
976
977 /*
978 * intel_wait_for_pipe_off - wait for pipe to turn off
979 * @crtc: crtc whose pipe to wait for
980 *
981 * After disabling a pipe, we can't wait for vblank in the usual way,
982 * spinning on the vblank interrupt status bit, since we won't actually
983 * see an interrupt when the pipe is disabled.
984 *
985 * On Gen4 and above:
986 * wait for the pipe register state bit to turn off
987 *
988 * Otherwise:
989 * wait for the display line value to settle (it usually
990 * ends up stopping at the start of the next frame).
991 *
992 */
993 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
994 {
995 struct drm_device *dev = crtc->base.dev;
996 struct drm_i915_private *dev_priv = dev->dev_private;
997 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
998 enum pipe pipe = crtc->pipe;
999
1000 if (INTEL_INFO(dev)->gen >= 4) {
1001 int reg = PIPECONF(cpu_transcoder);
1002
1003 /* Wait for the Pipe State to go off */
1004 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1005 100))
1006 WARN(1, "pipe_off wait timed out\n");
1007 } else {
1008 /* Wait for the display line to settle */
1009 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1010 WARN(1, "pipe_off wait timed out\n");
1011 }
1012 }
1013
1014 /*
1015 * ibx_digital_port_connected - is the specified port connected?
1016 * @dev_priv: i915 private structure
1017 * @port: the port to test
1018 *
1019 * Returns true if @port is connected, false otherwise.
1020 */
1021 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1022 struct intel_digital_port *port)
1023 {
1024 u32 bit;
1025
1026 if (HAS_PCH_IBX(dev_priv->dev)) {
1027 switch (port->port) {
1028 case PORT_B:
1029 bit = SDE_PORTB_HOTPLUG;
1030 break;
1031 case PORT_C:
1032 bit = SDE_PORTC_HOTPLUG;
1033 break;
1034 case PORT_D:
1035 bit = SDE_PORTD_HOTPLUG;
1036 break;
1037 default:
1038 return true;
1039 }
1040 } else {
1041 switch (port->port) {
1042 case PORT_B:
1043 bit = SDE_PORTB_HOTPLUG_CPT;
1044 break;
1045 case PORT_C:
1046 bit = SDE_PORTC_HOTPLUG_CPT;
1047 break;
1048 case PORT_D:
1049 bit = SDE_PORTD_HOTPLUG_CPT;
1050 break;
1051 default:
1052 return true;
1053 }
1054 }
1055
1056 return I915_READ(SDEISR) & bit;
1057 }
1058
1059 static const char *state_string(bool enabled)
1060 {
1061 return enabled ? "on" : "off";
1062 }
1063
1064 /* Only for pre-ILK configs */
1065 void assert_pll(struct drm_i915_private *dev_priv,
1066 enum pipe pipe, bool state)
1067 {
1068 int reg;
1069 u32 val;
1070 bool cur_state;
1071
1072 reg = DPLL(pipe);
1073 val = I915_READ(reg);
1074 cur_state = !!(val & DPLL_VCO_ENABLE);
1075 I915_STATE_WARN(cur_state != state,
1076 "PLL state assertion failure (expected %s, current %s)\n",
1077 state_string(state), state_string(cur_state));
1078 }
1079
1080 /* XXX: the dsi pll is shared between MIPI DSI ports */
1081 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1082 {
1083 u32 val;
1084 bool cur_state;
1085
1086 mutex_lock(&dev_priv->dpio_lock);
1087 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1088 mutex_unlock(&dev_priv->dpio_lock);
1089
1090 cur_state = val & DSI_PLL_VCO_EN;
1091 I915_STATE_WARN(cur_state != state,
1092 "DSI PLL state assertion failure (expected %s, current %s)\n",
1093 state_string(state), state_string(cur_state));
1094 }
1095 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1096 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1097
1098 struct intel_shared_dpll *
1099 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1100 {
1101 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1102
1103 if (crtc->config->shared_dpll < 0)
1104 return NULL;
1105
1106 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1107 }
1108
1109 /* For ILK+ */
1110 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1111 struct intel_shared_dpll *pll,
1112 bool state)
1113 {
1114 bool cur_state;
1115 struct intel_dpll_hw_state hw_state;
1116
1117 if (WARN (!pll,
1118 "asserting DPLL %s with no DPLL\n", state_string(state)))
1119 return;
1120
1121 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1122 I915_STATE_WARN(cur_state != state,
1123 "%s assertion failure (expected %s, current %s)\n",
1124 pll->name, state_string(state), state_string(cur_state));
1125 }
1126
1127 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1128 enum pipe pipe, bool state)
1129 {
1130 int reg;
1131 u32 val;
1132 bool cur_state;
1133 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1134 pipe);
1135
1136 if (HAS_DDI(dev_priv->dev)) {
1137 /* DDI does not have a specific FDI_TX register */
1138 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1139 val = I915_READ(reg);
1140 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1141 } else {
1142 reg = FDI_TX_CTL(pipe);
1143 val = I915_READ(reg);
1144 cur_state = !!(val & FDI_TX_ENABLE);
1145 }
1146 I915_STATE_WARN(cur_state != state,
1147 "FDI TX state assertion failure (expected %s, current %s)\n",
1148 state_string(state), state_string(cur_state));
1149 }
1150 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1151 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1152
1153 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1154 enum pipe pipe, bool state)
1155 {
1156 int reg;
1157 u32 val;
1158 bool cur_state;
1159
1160 reg = FDI_RX_CTL(pipe);
1161 val = I915_READ(reg);
1162 cur_state = !!(val & FDI_RX_ENABLE);
1163 I915_STATE_WARN(cur_state != state,
1164 "FDI RX state assertion failure (expected %s, current %s)\n",
1165 state_string(state), state_string(cur_state));
1166 }
1167 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1168 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1169
1170 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1171 enum pipe pipe)
1172 {
1173 int reg;
1174 u32 val;
1175
1176 /* ILK FDI PLL is always enabled */
1177 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1178 return;
1179
1180 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1181 if (HAS_DDI(dev_priv->dev))
1182 return;
1183
1184 reg = FDI_TX_CTL(pipe);
1185 val = I915_READ(reg);
1186 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1187 }
1188
1189 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1190 enum pipe pipe, bool state)
1191 {
1192 int reg;
1193 u32 val;
1194 bool cur_state;
1195
1196 reg = FDI_RX_CTL(pipe);
1197 val = I915_READ(reg);
1198 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1199 I915_STATE_WARN(cur_state != state,
1200 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1201 state_string(state), state_string(cur_state));
1202 }
1203
1204 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1205 enum pipe pipe)
1206 {
1207 struct drm_device *dev = dev_priv->dev;
1208 int pp_reg;
1209 u32 val;
1210 enum pipe panel_pipe = PIPE_A;
1211 bool locked = true;
1212
1213 if (WARN_ON(HAS_DDI(dev)))
1214 return;
1215
1216 if (HAS_PCH_SPLIT(dev)) {
1217 u32 port_sel;
1218
1219 pp_reg = PCH_PP_CONTROL;
1220 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1221
1222 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1223 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1224 panel_pipe = PIPE_B;
1225 /* XXX: else fix for eDP */
1226 } else if (IS_VALLEYVIEW(dev)) {
1227 /* presumably write lock depends on pipe, not port select */
1228 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1229 panel_pipe = pipe;
1230 } else {
1231 pp_reg = PP_CONTROL;
1232 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1233 panel_pipe = PIPE_B;
1234 }
1235
1236 val = I915_READ(pp_reg);
1237 if (!(val & PANEL_POWER_ON) ||
1238 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1239 locked = false;
1240
1241 I915_STATE_WARN(panel_pipe == pipe && locked,
1242 "panel assertion failure, pipe %c regs locked\n",
1243 pipe_name(pipe));
1244 }
1245
1246 static void assert_cursor(struct drm_i915_private *dev_priv,
1247 enum pipe pipe, bool state)
1248 {
1249 struct drm_device *dev = dev_priv->dev;
1250 bool cur_state;
1251
1252 if (IS_845G(dev) || IS_I865G(dev))
1253 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1254 else
1255 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1256
1257 I915_STATE_WARN(cur_state != state,
1258 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1259 pipe_name(pipe), state_string(state), state_string(cur_state));
1260 }
1261 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1262 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1263
1264 void assert_pipe(struct drm_i915_private *dev_priv,
1265 enum pipe pipe, bool state)
1266 {
1267 int reg;
1268 u32 val;
1269 bool cur_state;
1270 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1271 pipe);
1272
1273 /* if we need the pipe quirk it must be always on */
1274 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1275 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1276 state = true;
1277
1278 if (!intel_display_power_is_enabled(dev_priv,
1279 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1280 cur_state = false;
1281 } else {
1282 reg = PIPECONF(cpu_transcoder);
1283 val = I915_READ(reg);
1284 cur_state = !!(val & PIPECONF_ENABLE);
1285 }
1286
1287 I915_STATE_WARN(cur_state != state,
1288 "pipe %c assertion failure (expected %s, current %s)\n",
1289 pipe_name(pipe), state_string(state), state_string(cur_state));
1290 }
1291
1292 static void assert_plane(struct drm_i915_private *dev_priv,
1293 enum plane plane, bool state)
1294 {
1295 int reg;
1296 u32 val;
1297 bool cur_state;
1298
1299 reg = DSPCNTR(plane);
1300 val = I915_READ(reg);
1301 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1302 I915_STATE_WARN(cur_state != state,
1303 "plane %c assertion failure (expected %s, current %s)\n",
1304 plane_name(plane), state_string(state), state_string(cur_state));
1305 }
1306
1307 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1308 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1309
1310 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1311 enum pipe pipe)
1312 {
1313 struct drm_device *dev = dev_priv->dev;
1314 int reg, i;
1315 u32 val;
1316 int cur_pipe;
1317
1318 /* Primary planes are fixed to pipes on gen4+ */
1319 if (INTEL_INFO(dev)->gen >= 4) {
1320 reg = DSPCNTR(pipe);
1321 val = I915_READ(reg);
1322 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1323 "plane %c assertion failure, should be disabled but not\n",
1324 plane_name(pipe));
1325 return;
1326 }
1327
1328 /* Need to check both planes against the pipe */
1329 for_each_pipe(dev_priv, i) {
1330 reg = DSPCNTR(i);
1331 val = I915_READ(reg);
1332 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1333 DISPPLANE_SEL_PIPE_SHIFT;
1334 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1335 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1336 plane_name(i), pipe_name(pipe));
1337 }
1338 }
1339
1340 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1341 enum pipe pipe)
1342 {
1343 struct drm_device *dev = dev_priv->dev;
1344 int reg, sprite;
1345 u32 val;
1346
1347 if (INTEL_INFO(dev)->gen >= 9) {
1348 for_each_sprite(dev_priv, pipe, sprite) {
1349 val = I915_READ(PLANE_CTL(pipe, sprite));
1350 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1351 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1352 sprite, pipe_name(pipe));
1353 }
1354 } else if (IS_VALLEYVIEW(dev)) {
1355 for_each_sprite(dev_priv, pipe, sprite) {
1356 reg = SPCNTR(pipe, sprite);
1357 val = I915_READ(reg);
1358 I915_STATE_WARN(val & SP_ENABLE,
1359 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1360 sprite_name(pipe, sprite), pipe_name(pipe));
1361 }
1362 } else if (INTEL_INFO(dev)->gen >= 7) {
1363 reg = SPRCTL(pipe);
1364 val = I915_READ(reg);
1365 I915_STATE_WARN(val & SPRITE_ENABLE,
1366 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1367 plane_name(pipe), pipe_name(pipe));
1368 } else if (INTEL_INFO(dev)->gen >= 5) {
1369 reg = DVSCNTR(pipe);
1370 val = I915_READ(reg);
1371 I915_STATE_WARN(val & DVS_ENABLE,
1372 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1373 plane_name(pipe), pipe_name(pipe));
1374 }
1375 }
1376
1377 static void assert_vblank_disabled(struct drm_crtc *crtc)
1378 {
1379 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1380 drm_crtc_vblank_put(crtc);
1381 }
1382
1383 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1384 {
1385 u32 val;
1386 bool enabled;
1387
1388 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1389
1390 val = I915_READ(PCH_DREF_CONTROL);
1391 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1392 DREF_SUPERSPREAD_SOURCE_MASK));
1393 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1394 }
1395
1396 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1397 enum pipe pipe)
1398 {
1399 int reg;
1400 u32 val;
1401 bool enabled;
1402
1403 reg = PCH_TRANSCONF(pipe);
1404 val = I915_READ(reg);
1405 enabled = !!(val & TRANS_ENABLE);
1406 I915_STATE_WARN(enabled,
1407 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1408 pipe_name(pipe));
1409 }
1410
1411 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1412 enum pipe pipe, u32 port_sel, u32 val)
1413 {
1414 if ((val & DP_PORT_EN) == 0)
1415 return false;
1416
1417 if (HAS_PCH_CPT(dev_priv->dev)) {
1418 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1419 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1420 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1421 return false;
1422 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1423 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1424 return false;
1425 } else {
1426 if ((val & DP_PIPE_MASK) != (pipe << 30))
1427 return false;
1428 }
1429 return true;
1430 }
1431
1432 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1433 enum pipe pipe, u32 val)
1434 {
1435 if ((val & SDVO_ENABLE) == 0)
1436 return false;
1437
1438 if (HAS_PCH_CPT(dev_priv->dev)) {
1439 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1440 return false;
1441 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1442 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1443 return false;
1444 } else {
1445 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1446 return false;
1447 }
1448 return true;
1449 }
1450
1451 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1452 enum pipe pipe, u32 val)
1453 {
1454 if ((val & LVDS_PORT_EN) == 0)
1455 return false;
1456
1457 if (HAS_PCH_CPT(dev_priv->dev)) {
1458 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1459 return false;
1460 } else {
1461 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1462 return false;
1463 }
1464 return true;
1465 }
1466
1467 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1468 enum pipe pipe, u32 val)
1469 {
1470 if ((val & ADPA_DAC_ENABLE) == 0)
1471 return false;
1472 if (HAS_PCH_CPT(dev_priv->dev)) {
1473 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1474 return false;
1475 } else {
1476 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1477 return false;
1478 }
1479 return true;
1480 }
1481
1482 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1483 enum pipe pipe, int reg, u32 port_sel)
1484 {
1485 u32 val = I915_READ(reg);
1486 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1487 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1488 reg, pipe_name(pipe));
1489
1490 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1491 && (val & DP_PIPEB_SELECT),
1492 "IBX PCH dp port still using transcoder B\n");
1493 }
1494
1495 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1496 enum pipe pipe, int reg)
1497 {
1498 u32 val = I915_READ(reg);
1499 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1500 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1501 reg, pipe_name(pipe));
1502
1503 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1504 && (val & SDVO_PIPE_B_SELECT),
1505 "IBX PCH hdmi port still using transcoder B\n");
1506 }
1507
1508 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1509 enum pipe pipe)
1510 {
1511 int reg;
1512 u32 val;
1513
1514 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1515 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1516 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1517
1518 reg = PCH_ADPA;
1519 val = I915_READ(reg);
1520 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1521 "PCH VGA enabled on transcoder %c, should be disabled\n",
1522 pipe_name(pipe));
1523
1524 reg = PCH_LVDS;
1525 val = I915_READ(reg);
1526 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1527 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1528 pipe_name(pipe));
1529
1530 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1531 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1532 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1533 }
1534
1535 static void intel_init_dpio(struct drm_device *dev)
1536 {
1537 struct drm_i915_private *dev_priv = dev->dev_private;
1538
1539 if (!IS_VALLEYVIEW(dev))
1540 return;
1541
1542 /*
1543 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1544 * CHV x1 PHY (DP/HDMI D)
1545 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1546 */
1547 if (IS_CHERRYVIEW(dev)) {
1548 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1549 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1550 } else {
1551 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1552 }
1553 }
1554
1555 static void vlv_enable_pll(struct intel_crtc *crtc,
1556 const struct intel_crtc_state *pipe_config)
1557 {
1558 struct drm_device *dev = crtc->base.dev;
1559 struct drm_i915_private *dev_priv = dev->dev_private;
1560 int reg = DPLL(crtc->pipe);
1561 u32 dpll = pipe_config->dpll_hw_state.dpll;
1562
1563 assert_pipe_disabled(dev_priv, crtc->pipe);
1564
1565 /* No really, not for ILK+ */
1566 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1567
1568 /* PLL is protected by panel, make sure we can write it */
1569 if (IS_MOBILE(dev_priv->dev))
1570 assert_panel_unlocked(dev_priv, crtc->pipe);
1571
1572 I915_WRITE(reg, dpll);
1573 POSTING_READ(reg);
1574 udelay(150);
1575
1576 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1577 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1578
1579 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1580 POSTING_READ(DPLL_MD(crtc->pipe));
1581
1582 /* We do this three times for luck */
1583 I915_WRITE(reg, dpll);
1584 POSTING_READ(reg);
1585 udelay(150); /* wait for warmup */
1586 I915_WRITE(reg, dpll);
1587 POSTING_READ(reg);
1588 udelay(150); /* wait for warmup */
1589 I915_WRITE(reg, dpll);
1590 POSTING_READ(reg);
1591 udelay(150); /* wait for warmup */
1592 }
1593
1594 static void chv_enable_pll(struct intel_crtc *crtc,
1595 const struct intel_crtc_state *pipe_config)
1596 {
1597 struct drm_device *dev = crtc->base.dev;
1598 struct drm_i915_private *dev_priv = dev->dev_private;
1599 int pipe = crtc->pipe;
1600 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1601 u32 tmp;
1602
1603 assert_pipe_disabled(dev_priv, crtc->pipe);
1604
1605 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1606
1607 mutex_lock(&dev_priv->dpio_lock);
1608
1609 /* Enable back the 10bit clock to display controller */
1610 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1611 tmp |= DPIO_DCLKP_EN;
1612 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1613
1614 /*
1615 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1616 */
1617 udelay(1);
1618
1619 /* Enable PLL */
1620 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1621
1622 /* Check PLL is locked */
1623 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1624 DRM_ERROR("PLL %d failed to lock\n", pipe);
1625
1626 /* not sure when this should be written */
1627 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1628 POSTING_READ(DPLL_MD(pipe));
1629
1630 mutex_unlock(&dev_priv->dpio_lock);
1631 }
1632
1633 static int intel_num_dvo_pipes(struct drm_device *dev)
1634 {
1635 struct intel_crtc *crtc;
1636 int count = 0;
1637
1638 for_each_intel_crtc(dev, crtc)
1639 count += crtc->active &&
1640 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1641
1642 return count;
1643 }
1644
1645 static void i9xx_enable_pll(struct intel_crtc *crtc)
1646 {
1647 struct drm_device *dev = crtc->base.dev;
1648 struct drm_i915_private *dev_priv = dev->dev_private;
1649 int reg = DPLL(crtc->pipe);
1650 u32 dpll = crtc->config->dpll_hw_state.dpll;
1651
1652 assert_pipe_disabled(dev_priv, crtc->pipe);
1653
1654 /* No really, not for ILK+ */
1655 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1656
1657 /* PLL is protected by panel, make sure we can write it */
1658 if (IS_MOBILE(dev) && !IS_I830(dev))
1659 assert_panel_unlocked(dev_priv, crtc->pipe);
1660
1661 /* Enable DVO 2x clock on both PLLs if necessary */
1662 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1663 /*
1664 * It appears to be important that we don't enable this
1665 * for the current pipe before otherwise configuring the
1666 * PLL. No idea how this should be handled if multiple
1667 * DVO outputs are enabled simultaneosly.
1668 */
1669 dpll |= DPLL_DVO_2X_MODE;
1670 I915_WRITE(DPLL(!crtc->pipe),
1671 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1672 }
1673
1674 /* Wait for the clocks to stabilize. */
1675 POSTING_READ(reg);
1676 udelay(150);
1677
1678 if (INTEL_INFO(dev)->gen >= 4) {
1679 I915_WRITE(DPLL_MD(crtc->pipe),
1680 crtc->config->dpll_hw_state.dpll_md);
1681 } else {
1682 /* The pixel multiplier can only be updated once the
1683 * DPLL is enabled and the clocks are stable.
1684 *
1685 * So write it again.
1686 */
1687 I915_WRITE(reg, dpll);
1688 }
1689
1690 /* We do this three times for luck */
1691 I915_WRITE(reg, dpll);
1692 POSTING_READ(reg);
1693 udelay(150); /* wait for warmup */
1694 I915_WRITE(reg, dpll);
1695 POSTING_READ(reg);
1696 udelay(150); /* wait for warmup */
1697 I915_WRITE(reg, dpll);
1698 POSTING_READ(reg);
1699 udelay(150); /* wait for warmup */
1700 }
1701
1702 /**
1703 * i9xx_disable_pll - disable a PLL
1704 * @dev_priv: i915 private structure
1705 * @pipe: pipe PLL to disable
1706 *
1707 * Disable the PLL for @pipe, making sure the pipe is off first.
1708 *
1709 * Note! This is for pre-ILK only.
1710 */
1711 static void i9xx_disable_pll(struct intel_crtc *crtc)
1712 {
1713 struct drm_device *dev = crtc->base.dev;
1714 struct drm_i915_private *dev_priv = dev->dev_private;
1715 enum pipe pipe = crtc->pipe;
1716
1717 /* Disable DVO 2x clock on both PLLs if necessary */
1718 if (IS_I830(dev) &&
1719 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1720 intel_num_dvo_pipes(dev) == 1) {
1721 I915_WRITE(DPLL(PIPE_B),
1722 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1723 I915_WRITE(DPLL(PIPE_A),
1724 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1725 }
1726
1727 /* Don't disable pipe or pipe PLLs if needed */
1728 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1729 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1730 return;
1731
1732 /* Make sure the pipe isn't still relying on us */
1733 assert_pipe_disabled(dev_priv, pipe);
1734
1735 I915_WRITE(DPLL(pipe), 0);
1736 POSTING_READ(DPLL(pipe));
1737 }
1738
1739 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1740 {
1741 u32 val = 0;
1742
1743 /* Make sure the pipe isn't still relying on us */
1744 assert_pipe_disabled(dev_priv, pipe);
1745
1746 /*
1747 * Leave integrated clock source and reference clock enabled for pipe B.
1748 * The latter is needed for VGA hotplug / manual detection.
1749 */
1750 if (pipe == PIPE_B)
1751 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1752 I915_WRITE(DPLL(pipe), val);
1753 POSTING_READ(DPLL(pipe));
1754
1755 }
1756
1757 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1758 {
1759 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1760 u32 val;
1761
1762 /* Make sure the pipe isn't still relying on us */
1763 assert_pipe_disabled(dev_priv, pipe);
1764
1765 /* Set PLL en = 0 */
1766 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1767 if (pipe != PIPE_A)
1768 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1769 I915_WRITE(DPLL(pipe), val);
1770 POSTING_READ(DPLL(pipe));
1771
1772 mutex_lock(&dev_priv->dpio_lock);
1773
1774 /* Disable 10bit clock to display controller */
1775 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1776 val &= ~DPIO_DCLKP_EN;
1777 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1778
1779 /* disable left/right clock distribution */
1780 if (pipe != PIPE_B) {
1781 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1782 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1783 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1784 } else {
1785 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1786 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1787 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1788 }
1789
1790 mutex_unlock(&dev_priv->dpio_lock);
1791 }
1792
1793 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1794 struct intel_digital_port *dport)
1795 {
1796 u32 port_mask;
1797 int dpll_reg;
1798
1799 switch (dport->port) {
1800 case PORT_B:
1801 port_mask = DPLL_PORTB_READY_MASK;
1802 dpll_reg = DPLL(0);
1803 break;
1804 case PORT_C:
1805 port_mask = DPLL_PORTC_READY_MASK;
1806 dpll_reg = DPLL(0);
1807 break;
1808 case PORT_D:
1809 port_mask = DPLL_PORTD_READY_MASK;
1810 dpll_reg = DPIO_PHY_STATUS;
1811 break;
1812 default:
1813 BUG();
1814 }
1815
1816 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1817 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1818 port_name(dport->port), I915_READ(dpll_reg));
1819 }
1820
1821 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1822 {
1823 struct drm_device *dev = crtc->base.dev;
1824 struct drm_i915_private *dev_priv = dev->dev_private;
1825 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1826
1827 if (WARN_ON(pll == NULL))
1828 return;
1829
1830 WARN_ON(!pll->config.crtc_mask);
1831 if (pll->active == 0) {
1832 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1833 WARN_ON(pll->on);
1834 assert_shared_dpll_disabled(dev_priv, pll);
1835
1836 pll->mode_set(dev_priv, pll);
1837 }
1838 }
1839
1840 /**
1841 * intel_enable_shared_dpll - enable PCH PLL
1842 * @dev_priv: i915 private structure
1843 * @pipe: pipe PLL to enable
1844 *
1845 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1846 * drives the transcoder clock.
1847 */
1848 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1849 {
1850 struct drm_device *dev = crtc->base.dev;
1851 struct drm_i915_private *dev_priv = dev->dev_private;
1852 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1853
1854 if (WARN_ON(pll == NULL))
1855 return;
1856
1857 if (WARN_ON(pll->config.crtc_mask == 0))
1858 return;
1859
1860 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1861 pll->name, pll->active, pll->on,
1862 crtc->base.base.id);
1863
1864 if (pll->active++) {
1865 WARN_ON(!pll->on);
1866 assert_shared_dpll_enabled(dev_priv, pll);
1867 return;
1868 }
1869 WARN_ON(pll->on);
1870
1871 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1872
1873 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1874 pll->enable(dev_priv, pll);
1875 pll->on = true;
1876 }
1877
1878 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1879 {
1880 struct drm_device *dev = crtc->base.dev;
1881 struct drm_i915_private *dev_priv = dev->dev_private;
1882 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1883
1884 /* PCH only available on ILK+ */
1885 BUG_ON(INTEL_INFO(dev)->gen < 5);
1886 if (WARN_ON(pll == NULL))
1887 return;
1888
1889 if (WARN_ON(pll->config.crtc_mask == 0))
1890 return;
1891
1892 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1893 pll->name, pll->active, pll->on,
1894 crtc->base.base.id);
1895
1896 if (WARN_ON(pll->active == 0)) {
1897 assert_shared_dpll_disabled(dev_priv, pll);
1898 return;
1899 }
1900
1901 assert_shared_dpll_enabled(dev_priv, pll);
1902 WARN_ON(!pll->on);
1903 if (--pll->active)
1904 return;
1905
1906 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1907 pll->disable(dev_priv, pll);
1908 pll->on = false;
1909
1910 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1911 }
1912
1913 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1914 enum pipe pipe)
1915 {
1916 struct drm_device *dev = dev_priv->dev;
1917 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1918 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1919 uint32_t reg, val, pipeconf_val;
1920
1921 /* PCH only available on ILK+ */
1922 BUG_ON(!HAS_PCH_SPLIT(dev));
1923
1924 /* Make sure PCH DPLL is enabled */
1925 assert_shared_dpll_enabled(dev_priv,
1926 intel_crtc_to_shared_dpll(intel_crtc));
1927
1928 /* FDI must be feeding us bits for PCH ports */
1929 assert_fdi_tx_enabled(dev_priv, pipe);
1930 assert_fdi_rx_enabled(dev_priv, pipe);
1931
1932 if (HAS_PCH_CPT(dev)) {
1933 /* Workaround: Set the timing override bit before enabling the
1934 * pch transcoder. */
1935 reg = TRANS_CHICKEN2(pipe);
1936 val = I915_READ(reg);
1937 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1938 I915_WRITE(reg, val);
1939 }
1940
1941 reg = PCH_TRANSCONF(pipe);
1942 val = I915_READ(reg);
1943 pipeconf_val = I915_READ(PIPECONF(pipe));
1944
1945 if (HAS_PCH_IBX(dev_priv->dev)) {
1946 /*
1947 * make the BPC in transcoder be consistent with
1948 * that in pipeconf reg.
1949 */
1950 val &= ~PIPECONF_BPC_MASK;
1951 val |= pipeconf_val & PIPECONF_BPC_MASK;
1952 }
1953
1954 val &= ~TRANS_INTERLACE_MASK;
1955 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1956 if (HAS_PCH_IBX(dev_priv->dev) &&
1957 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1958 val |= TRANS_LEGACY_INTERLACED_ILK;
1959 else
1960 val |= TRANS_INTERLACED;
1961 else
1962 val |= TRANS_PROGRESSIVE;
1963
1964 I915_WRITE(reg, val | TRANS_ENABLE);
1965 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1966 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1967 }
1968
1969 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1970 enum transcoder cpu_transcoder)
1971 {
1972 u32 val, pipeconf_val;
1973
1974 /* PCH only available on ILK+ */
1975 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1976
1977 /* FDI must be feeding us bits for PCH ports */
1978 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1979 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1980
1981 /* Workaround: set timing override bit. */
1982 val = I915_READ(_TRANSA_CHICKEN2);
1983 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1984 I915_WRITE(_TRANSA_CHICKEN2, val);
1985
1986 val = TRANS_ENABLE;
1987 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1988
1989 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1990 PIPECONF_INTERLACED_ILK)
1991 val |= TRANS_INTERLACED;
1992 else
1993 val |= TRANS_PROGRESSIVE;
1994
1995 I915_WRITE(LPT_TRANSCONF, val);
1996 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1997 DRM_ERROR("Failed to enable PCH transcoder\n");
1998 }
1999
2000 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2001 enum pipe pipe)
2002 {
2003 struct drm_device *dev = dev_priv->dev;
2004 uint32_t reg, val;
2005
2006 /* FDI relies on the transcoder */
2007 assert_fdi_tx_disabled(dev_priv, pipe);
2008 assert_fdi_rx_disabled(dev_priv, pipe);
2009
2010 /* Ports must be off as well */
2011 assert_pch_ports_disabled(dev_priv, pipe);
2012
2013 reg = PCH_TRANSCONF(pipe);
2014 val = I915_READ(reg);
2015 val &= ~TRANS_ENABLE;
2016 I915_WRITE(reg, val);
2017 /* wait for PCH transcoder off, transcoder state */
2018 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2019 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2020
2021 if (!HAS_PCH_IBX(dev)) {
2022 /* Workaround: Clear the timing override chicken bit again. */
2023 reg = TRANS_CHICKEN2(pipe);
2024 val = I915_READ(reg);
2025 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2026 I915_WRITE(reg, val);
2027 }
2028 }
2029
2030 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2031 {
2032 u32 val;
2033
2034 val = I915_READ(LPT_TRANSCONF);
2035 val &= ~TRANS_ENABLE;
2036 I915_WRITE(LPT_TRANSCONF, val);
2037 /* wait for PCH transcoder off, transcoder state */
2038 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2039 DRM_ERROR("Failed to disable PCH transcoder\n");
2040
2041 /* Workaround: clear timing override bit. */
2042 val = I915_READ(_TRANSA_CHICKEN2);
2043 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2044 I915_WRITE(_TRANSA_CHICKEN2, val);
2045 }
2046
2047 /**
2048 * intel_enable_pipe - enable a pipe, asserting requirements
2049 * @crtc: crtc responsible for the pipe
2050 *
2051 * Enable @crtc's pipe, making sure that various hardware specific requirements
2052 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2053 */
2054 static void intel_enable_pipe(struct intel_crtc *crtc)
2055 {
2056 struct drm_device *dev = crtc->base.dev;
2057 struct drm_i915_private *dev_priv = dev->dev_private;
2058 enum pipe pipe = crtc->pipe;
2059 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2060 pipe);
2061 enum pipe pch_transcoder;
2062 int reg;
2063 u32 val;
2064
2065 assert_planes_disabled(dev_priv, pipe);
2066 assert_cursor_disabled(dev_priv, pipe);
2067 assert_sprites_disabled(dev_priv, pipe);
2068
2069 if (HAS_PCH_LPT(dev_priv->dev))
2070 pch_transcoder = TRANSCODER_A;
2071 else
2072 pch_transcoder = pipe;
2073
2074 /*
2075 * A pipe without a PLL won't actually be able to drive bits from
2076 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2077 * need the check.
2078 */
2079 if (!HAS_PCH_SPLIT(dev_priv->dev))
2080 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2081 assert_dsi_pll_enabled(dev_priv);
2082 else
2083 assert_pll_enabled(dev_priv, pipe);
2084 else {
2085 if (crtc->config->has_pch_encoder) {
2086 /* if driving the PCH, we need FDI enabled */
2087 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2088 assert_fdi_tx_pll_enabled(dev_priv,
2089 (enum pipe) cpu_transcoder);
2090 }
2091 /* FIXME: assert CPU port conditions for SNB+ */
2092 }
2093
2094 reg = PIPECONF(cpu_transcoder);
2095 val = I915_READ(reg);
2096 if (val & PIPECONF_ENABLE) {
2097 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2098 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2099 return;
2100 }
2101
2102 I915_WRITE(reg, val | PIPECONF_ENABLE);
2103 POSTING_READ(reg);
2104 }
2105
2106 /**
2107 * intel_disable_pipe - disable a pipe, asserting requirements
2108 * @crtc: crtc whose pipes is to be disabled
2109 *
2110 * Disable the pipe of @crtc, making sure that various hardware
2111 * specific requirements are met, if applicable, e.g. plane
2112 * disabled, panel fitter off, etc.
2113 *
2114 * Will wait until the pipe has shut down before returning.
2115 */
2116 static void intel_disable_pipe(struct intel_crtc *crtc)
2117 {
2118 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2119 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2120 enum pipe pipe = crtc->pipe;
2121 int reg;
2122 u32 val;
2123
2124 /*
2125 * Make sure planes won't keep trying to pump pixels to us,
2126 * or we might hang the display.
2127 */
2128 assert_planes_disabled(dev_priv, pipe);
2129 assert_cursor_disabled(dev_priv, pipe);
2130 assert_sprites_disabled(dev_priv, pipe);
2131
2132 reg = PIPECONF(cpu_transcoder);
2133 val = I915_READ(reg);
2134 if ((val & PIPECONF_ENABLE) == 0)
2135 return;
2136
2137 /*
2138 * Double wide has implications for planes
2139 * so best keep it disabled when not needed.
2140 */
2141 if (crtc->config->double_wide)
2142 val &= ~PIPECONF_DOUBLE_WIDE;
2143
2144 /* Don't disable pipe or pipe PLLs if needed */
2145 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2146 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2147 val &= ~PIPECONF_ENABLE;
2148
2149 I915_WRITE(reg, val);
2150 if ((val & PIPECONF_ENABLE) == 0)
2151 intel_wait_for_pipe_off(crtc);
2152 }
2153
2154 /*
2155 * Plane regs are double buffered, going from enabled->disabled needs a
2156 * trigger in order to latch. The display address reg provides this.
2157 */
2158 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2159 enum plane plane)
2160 {
2161 struct drm_device *dev = dev_priv->dev;
2162 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2163
2164 I915_WRITE(reg, I915_READ(reg));
2165 POSTING_READ(reg);
2166 }
2167
2168 /**
2169 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2170 * @plane: plane to be enabled
2171 * @crtc: crtc for the plane
2172 *
2173 * Enable @plane on @crtc, making sure that the pipe is running first.
2174 */
2175 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2176 struct drm_crtc *crtc)
2177 {
2178 struct drm_device *dev = plane->dev;
2179 struct drm_i915_private *dev_priv = dev->dev_private;
2180 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2181
2182 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2183 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2184
2185 if (intel_crtc->primary_enabled)
2186 return;
2187
2188 intel_crtc->primary_enabled = true;
2189
2190 dev_priv->display.update_primary_plane(crtc, plane->fb,
2191 crtc->x, crtc->y);
2192
2193 /*
2194 * BDW signals flip done immediately if the plane
2195 * is disabled, even if the plane enable is already
2196 * armed to occur at the next vblank :(
2197 */
2198 if (IS_BROADWELL(dev))
2199 intel_wait_for_vblank(dev, intel_crtc->pipe);
2200 }
2201
2202 /**
2203 * intel_disable_primary_hw_plane - disable the primary hardware plane
2204 * @plane: plane to be disabled
2205 * @crtc: crtc for the plane
2206 *
2207 * Disable @plane on @crtc, making sure that the pipe is running first.
2208 */
2209 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2210 struct drm_crtc *crtc)
2211 {
2212 struct drm_device *dev = plane->dev;
2213 struct drm_i915_private *dev_priv = dev->dev_private;
2214 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2215
2216 if (WARN_ON(!intel_crtc->active))
2217 return;
2218
2219 if (!intel_crtc->primary_enabled)
2220 return;
2221
2222 intel_crtc->primary_enabled = false;
2223
2224 dev_priv->display.update_primary_plane(crtc, plane->fb,
2225 crtc->x, crtc->y);
2226 }
2227
2228 static bool need_vtd_wa(struct drm_device *dev)
2229 {
2230 #ifdef CONFIG_INTEL_IOMMU
2231 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2232 return true;
2233 #endif
2234 return false;
2235 }
2236
2237 unsigned int
2238 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2239 uint64_t fb_format_modifier)
2240 {
2241 unsigned int tile_height;
2242 uint32_t pixel_bytes;
2243
2244 switch (fb_format_modifier) {
2245 case DRM_FORMAT_MOD_NONE:
2246 tile_height = 1;
2247 break;
2248 case I915_FORMAT_MOD_X_TILED:
2249 tile_height = IS_GEN2(dev) ? 16 : 8;
2250 break;
2251 case I915_FORMAT_MOD_Y_TILED:
2252 tile_height = 32;
2253 break;
2254 case I915_FORMAT_MOD_Yf_TILED:
2255 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2256 switch (pixel_bytes) {
2257 default:
2258 case 1:
2259 tile_height = 64;
2260 break;
2261 case 2:
2262 case 4:
2263 tile_height = 32;
2264 break;
2265 case 8:
2266 tile_height = 16;
2267 break;
2268 case 16:
2269 WARN_ONCE(1,
2270 "128-bit pixels are not supported for display!");
2271 tile_height = 16;
2272 break;
2273 }
2274 break;
2275 default:
2276 MISSING_CASE(fb_format_modifier);
2277 tile_height = 1;
2278 break;
2279 }
2280
2281 return tile_height;
2282 }
2283
2284 unsigned int
2285 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2286 uint32_t pixel_format, uint64_t fb_format_modifier)
2287 {
2288 return ALIGN(height, intel_tile_height(dev, pixel_format,
2289 fb_format_modifier));
2290 }
2291
2292 static int
2293 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2294 const struct drm_plane_state *plane_state)
2295 {
2296 struct intel_rotation_info *info = &view->rotation_info;
2297 static const struct i915_ggtt_view rotated_view =
2298 { .type = I915_GGTT_VIEW_ROTATED };
2299
2300 *view = i915_ggtt_view_normal;
2301
2302 if (!plane_state)
2303 return 0;
2304
2305 if (!intel_rotation_90_or_270(plane_state->rotation))
2306 return 0;
2307
2308 *view = rotated_view;
2309
2310 info->height = fb->height;
2311 info->pixel_format = fb->pixel_format;
2312 info->pitch = fb->pitches[0];
2313 info->fb_modifier = fb->modifier[0];
2314
2315 if (!(info->fb_modifier == I915_FORMAT_MOD_Y_TILED ||
2316 info->fb_modifier == I915_FORMAT_MOD_Yf_TILED)) {
2317 DRM_DEBUG_KMS(
2318 "Y or Yf tiling is needed for 90/270 rotation!\n");
2319 return -EINVAL;
2320 }
2321
2322 return 0;
2323 }
2324
2325 int
2326 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2327 struct drm_framebuffer *fb,
2328 const struct drm_plane_state *plane_state,
2329 struct intel_engine_cs *pipelined)
2330 {
2331 struct drm_device *dev = fb->dev;
2332 struct drm_i915_private *dev_priv = dev->dev_private;
2333 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2334 struct i915_ggtt_view view;
2335 u32 alignment;
2336 int ret;
2337
2338 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2339
2340 switch (fb->modifier[0]) {
2341 case DRM_FORMAT_MOD_NONE:
2342 if (INTEL_INFO(dev)->gen >= 9)
2343 alignment = 256 * 1024;
2344 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2345 alignment = 128 * 1024;
2346 else if (INTEL_INFO(dev)->gen >= 4)
2347 alignment = 4 * 1024;
2348 else
2349 alignment = 64 * 1024;
2350 break;
2351 case I915_FORMAT_MOD_X_TILED:
2352 if (INTEL_INFO(dev)->gen >= 9)
2353 alignment = 256 * 1024;
2354 else {
2355 /* pin() will align the object as required by fence */
2356 alignment = 0;
2357 }
2358 break;
2359 case I915_FORMAT_MOD_Y_TILED:
2360 case I915_FORMAT_MOD_Yf_TILED:
2361 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2362 "Y tiling bo slipped through, driver bug!\n"))
2363 return -EINVAL;
2364 alignment = 1 * 1024 * 1024;
2365 break;
2366 default:
2367 MISSING_CASE(fb->modifier[0]);
2368 return -EINVAL;
2369 }
2370
2371 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2372 if (ret)
2373 return ret;
2374
2375 /* Note that the w/a also requires 64 PTE of padding following the
2376 * bo. We currently fill all unused PTE with the shadow page and so
2377 * we should always have valid PTE following the scanout preventing
2378 * the VT-d warning.
2379 */
2380 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2381 alignment = 256 * 1024;
2382
2383 /*
2384 * Global gtt pte registers are special registers which actually forward
2385 * writes to a chunk of system memory. Which means that there is no risk
2386 * that the register values disappear as soon as we call
2387 * intel_runtime_pm_put(), so it is correct to wrap only the
2388 * pin/unpin/fence and not more.
2389 */
2390 intel_runtime_pm_get(dev_priv);
2391
2392 dev_priv->mm.interruptible = false;
2393 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2394 &view);
2395 if (ret)
2396 goto err_interruptible;
2397
2398 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2399 * fence, whereas 965+ only requires a fence if using
2400 * framebuffer compression. For simplicity, we always install
2401 * a fence as the cost is not that onerous.
2402 */
2403 ret = i915_gem_object_get_fence(obj);
2404 if (ret)
2405 goto err_unpin;
2406
2407 i915_gem_object_pin_fence(obj);
2408
2409 dev_priv->mm.interruptible = true;
2410 intel_runtime_pm_put(dev_priv);
2411 return 0;
2412
2413 err_unpin:
2414 i915_gem_object_unpin_from_display_plane(obj, &view);
2415 err_interruptible:
2416 dev_priv->mm.interruptible = true;
2417 intel_runtime_pm_put(dev_priv);
2418 return ret;
2419 }
2420
2421 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2422 const struct drm_plane_state *plane_state)
2423 {
2424 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2425 struct i915_ggtt_view view;
2426 int ret;
2427
2428 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2429
2430 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2431 WARN_ONCE(ret, "Couldn't get view from plane state!");
2432
2433 i915_gem_object_unpin_fence(obj);
2434 i915_gem_object_unpin_from_display_plane(obj, &view);
2435 }
2436
2437 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2438 * is assumed to be a power-of-two. */
2439 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2440 unsigned int tiling_mode,
2441 unsigned int cpp,
2442 unsigned int pitch)
2443 {
2444 if (tiling_mode != I915_TILING_NONE) {
2445 unsigned int tile_rows, tiles;
2446
2447 tile_rows = *y / 8;
2448 *y %= 8;
2449
2450 tiles = *x / (512/cpp);
2451 *x %= 512/cpp;
2452
2453 return tile_rows * pitch * 8 + tiles * 4096;
2454 } else {
2455 unsigned int offset;
2456
2457 offset = *y * pitch + *x * cpp;
2458 *y = 0;
2459 *x = (offset & 4095) / cpp;
2460 return offset & -4096;
2461 }
2462 }
2463
2464 static int i9xx_format_to_fourcc(int format)
2465 {
2466 switch (format) {
2467 case DISPPLANE_8BPP:
2468 return DRM_FORMAT_C8;
2469 case DISPPLANE_BGRX555:
2470 return DRM_FORMAT_XRGB1555;
2471 case DISPPLANE_BGRX565:
2472 return DRM_FORMAT_RGB565;
2473 default:
2474 case DISPPLANE_BGRX888:
2475 return DRM_FORMAT_XRGB8888;
2476 case DISPPLANE_RGBX888:
2477 return DRM_FORMAT_XBGR8888;
2478 case DISPPLANE_BGRX101010:
2479 return DRM_FORMAT_XRGB2101010;
2480 case DISPPLANE_RGBX101010:
2481 return DRM_FORMAT_XBGR2101010;
2482 }
2483 }
2484
2485 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2486 {
2487 switch (format) {
2488 case PLANE_CTL_FORMAT_RGB_565:
2489 return DRM_FORMAT_RGB565;
2490 default:
2491 case PLANE_CTL_FORMAT_XRGB_8888:
2492 if (rgb_order) {
2493 if (alpha)
2494 return DRM_FORMAT_ABGR8888;
2495 else
2496 return DRM_FORMAT_XBGR8888;
2497 } else {
2498 if (alpha)
2499 return DRM_FORMAT_ARGB8888;
2500 else
2501 return DRM_FORMAT_XRGB8888;
2502 }
2503 case PLANE_CTL_FORMAT_XRGB_2101010:
2504 if (rgb_order)
2505 return DRM_FORMAT_XBGR2101010;
2506 else
2507 return DRM_FORMAT_XRGB2101010;
2508 }
2509 }
2510
2511 static bool
2512 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2513 struct intel_initial_plane_config *plane_config)
2514 {
2515 struct drm_device *dev = crtc->base.dev;
2516 struct drm_i915_gem_object *obj = NULL;
2517 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2518 struct drm_framebuffer *fb = &plane_config->fb->base;
2519 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2520 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2521 PAGE_SIZE);
2522
2523 size_aligned -= base_aligned;
2524
2525 if (plane_config->size == 0)
2526 return false;
2527
2528 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2529 base_aligned,
2530 base_aligned,
2531 size_aligned);
2532 if (!obj)
2533 return false;
2534
2535 obj->tiling_mode = plane_config->tiling;
2536 if (obj->tiling_mode == I915_TILING_X)
2537 obj->stride = fb->pitches[0];
2538
2539 mode_cmd.pixel_format = fb->pixel_format;
2540 mode_cmd.width = fb->width;
2541 mode_cmd.height = fb->height;
2542 mode_cmd.pitches[0] = fb->pitches[0];
2543 mode_cmd.modifier[0] = fb->modifier[0];
2544 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2545
2546 mutex_lock(&dev->struct_mutex);
2547 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2548 &mode_cmd, obj)) {
2549 DRM_DEBUG_KMS("intel fb init failed\n");
2550 goto out_unref_obj;
2551 }
2552 mutex_unlock(&dev->struct_mutex);
2553
2554 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2555 return true;
2556
2557 out_unref_obj:
2558 drm_gem_object_unreference(&obj->base);
2559 mutex_unlock(&dev->struct_mutex);
2560 return false;
2561 }
2562
2563 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2564 static void
2565 update_state_fb(struct drm_plane *plane)
2566 {
2567 if (plane->fb == plane->state->fb)
2568 return;
2569
2570 if (plane->state->fb)
2571 drm_framebuffer_unreference(plane->state->fb);
2572 plane->state->fb = plane->fb;
2573 if (plane->state->fb)
2574 drm_framebuffer_reference(plane->state->fb);
2575 }
2576
2577 static void
2578 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2579 struct intel_initial_plane_config *plane_config)
2580 {
2581 struct drm_device *dev = intel_crtc->base.dev;
2582 struct drm_i915_private *dev_priv = dev->dev_private;
2583 struct drm_crtc *c;
2584 struct intel_crtc *i;
2585 struct drm_i915_gem_object *obj;
2586 struct drm_plane *primary = intel_crtc->base.primary;
2587 struct drm_framebuffer *fb;
2588
2589 if (!plane_config->fb)
2590 return;
2591
2592 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2593 fb = &plane_config->fb->base;
2594 goto valid_fb;
2595 }
2596
2597 kfree(plane_config->fb);
2598
2599 /*
2600 * Failed to alloc the obj, check to see if we should share
2601 * an fb with another CRTC instead
2602 */
2603 for_each_crtc(dev, c) {
2604 i = to_intel_crtc(c);
2605
2606 if (c == &intel_crtc->base)
2607 continue;
2608
2609 if (!i->active)
2610 continue;
2611
2612 fb = c->primary->fb;
2613 if (!fb)
2614 continue;
2615
2616 obj = intel_fb_obj(fb);
2617 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2618 drm_framebuffer_reference(fb);
2619 goto valid_fb;
2620 }
2621 }
2622
2623 return;
2624
2625 valid_fb:
2626 obj = intel_fb_obj(fb);
2627 if (obj->tiling_mode != I915_TILING_NONE)
2628 dev_priv->preserve_bios_swizzle = true;
2629
2630 primary->fb = fb;
2631 primary->state->crtc = &intel_crtc->base;
2632 primary->crtc = &intel_crtc->base;
2633 update_state_fb(primary);
2634 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2635 }
2636
2637 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2638 struct drm_framebuffer *fb,
2639 int x, int y)
2640 {
2641 struct drm_device *dev = crtc->dev;
2642 struct drm_i915_private *dev_priv = dev->dev_private;
2643 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2644 struct drm_i915_gem_object *obj;
2645 int plane = intel_crtc->plane;
2646 unsigned long linear_offset;
2647 u32 dspcntr;
2648 u32 reg = DSPCNTR(plane);
2649 int pixel_size;
2650
2651 if (!intel_crtc->primary_enabled) {
2652 I915_WRITE(reg, 0);
2653 if (INTEL_INFO(dev)->gen >= 4)
2654 I915_WRITE(DSPSURF(plane), 0);
2655 else
2656 I915_WRITE(DSPADDR(plane), 0);
2657 POSTING_READ(reg);
2658 return;
2659 }
2660
2661 obj = intel_fb_obj(fb);
2662 if (WARN_ON(obj == NULL))
2663 return;
2664
2665 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2666
2667 dspcntr = DISPPLANE_GAMMA_ENABLE;
2668
2669 dspcntr |= DISPLAY_PLANE_ENABLE;
2670
2671 if (INTEL_INFO(dev)->gen < 4) {
2672 if (intel_crtc->pipe == PIPE_B)
2673 dspcntr |= DISPPLANE_SEL_PIPE_B;
2674
2675 /* pipesrc and dspsize control the size that is scaled from,
2676 * which should always be the user's requested size.
2677 */
2678 I915_WRITE(DSPSIZE(plane),
2679 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2680 (intel_crtc->config->pipe_src_w - 1));
2681 I915_WRITE(DSPPOS(plane), 0);
2682 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2683 I915_WRITE(PRIMSIZE(plane),
2684 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2685 (intel_crtc->config->pipe_src_w - 1));
2686 I915_WRITE(PRIMPOS(plane), 0);
2687 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2688 }
2689
2690 switch (fb->pixel_format) {
2691 case DRM_FORMAT_C8:
2692 dspcntr |= DISPPLANE_8BPP;
2693 break;
2694 case DRM_FORMAT_XRGB1555:
2695 case DRM_FORMAT_ARGB1555:
2696 dspcntr |= DISPPLANE_BGRX555;
2697 break;
2698 case DRM_FORMAT_RGB565:
2699 dspcntr |= DISPPLANE_BGRX565;
2700 break;
2701 case DRM_FORMAT_XRGB8888:
2702 case DRM_FORMAT_ARGB8888:
2703 dspcntr |= DISPPLANE_BGRX888;
2704 break;
2705 case DRM_FORMAT_XBGR8888:
2706 case DRM_FORMAT_ABGR8888:
2707 dspcntr |= DISPPLANE_RGBX888;
2708 break;
2709 case DRM_FORMAT_XRGB2101010:
2710 case DRM_FORMAT_ARGB2101010:
2711 dspcntr |= DISPPLANE_BGRX101010;
2712 break;
2713 case DRM_FORMAT_XBGR2101010:
2714 case DRM_FORMAT_ABGR2101010:
2715 dspcntr |= DISPPLANE_RGBX101010;
2716 break;
2717 default:
2718 BUG();
2719 }
2720
2721 if (INTEL_INFO(dev)->gen >= 4 &&
2722 obj->tiling_mode != I915_TILING_NONE)
2723 dspcntr |= DISPPLANE_TILED;
2724
2725 if (IS_G4X(dev))
2726 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2727
2728 linear_offset = y * fb->pitches[0] + x * pixel_size;
2729
2730 if (INTEL_INFO(dev)->gen >= 4) {
2731 intel_crtc->dspaddr_offset =
2732 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2733 pixel_size,
2734 fb->pitches[0]);
2735 linear_offset -= intel_crtc->dspaddr_offset;
2736 } else {
2737 intel_crtc->dspaddr_offset = linear_offset;
2738 }
2739
2740 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2741 dspcntr |= DISPPLANE_ROTATE_180;
2742
2743 x += (intel_crtc->config->pipe_src_w - 1);
2744 y += (intel_crtc->config->pipe_src_h - 1);
2745
2746 /* Finding the last pixel of the last line of the display
2747 data and adding to linear_offset*/
2748 linear_offset +=
2749 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2750 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2751 }
2752
2753 I915_WRITE(reg, dspcntr);
2754
2755 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2756 if (INTEL_INFO(dev)->gen >= 4) {
2757 I915_WRITE(DSPSURF(plane),
2758 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2759 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2760 I915_WRITE(DSPLINOFF(plane), linear_offset);
2761 } else
2762 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2763 POSTING_READ(reg);
2764 }
2765
2766 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2767 struct drm_framebuffer *fb,
2768 int x, int y)
2769 {
2770 struct drm_device *dev = crtc->dev;
2771 struct drm_i915_private *dev_priv = dev->dev_private;
2772 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2773 struct drm_i915_gem_object *obj;
2774 int plane = intel_crtc->plane;
2775 unsigned long linear_offset;
2776 u32 dspcntr;
2777 u32 reg = DSPCNTR(plane);
2778 int pixel_size;
2779
2780 if (!intel_crtc->primary_enabled) {
2781 I915_WRITE(reg, 0);
2782 I915_WRITE(DSPSURF(plane), 0);
2783 POSTING_READ(reg);
2784 return;
2785 }
2786
2787 obj = intel_fb_obj(fb);
2788 if (WARN_ON(obj == NULL))
2789 return;
2790
2791 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2792
2793 dspcntr = DISPPLANE_GAMMA_ENABLE;
2794
2795 dspcntr |= DISPLAY_PLANE_ENABLE;
2796
2797 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2798 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2799
2800 switch (fb->pixel_format) {
2801 case DRM_FORMAT_C8:
2802 dspcntr |= DISPPLANE_8BPP;
2803 break;
2804 case DRM_FORMAT_RGB565:
2805 dspcntr |= DISPPLANE_BGRX565;
2806 break;
2807 case DRM_FORMAT_XRGB8888:
2808 case DRM_FORMAT_ARGB8888:
2809 dspcntr |= DISPPLANE_BGRX888;
2810 break;
2811 case DRM_FORMAT_XBGR8888:
2812 case DRM_FORMAT_ABGR8888:
2813 dspcntr |= DISPPLANE_RGBX888;
2814 break;
2815 case DRM_FORMAT_XRGB2101010:
2816 case DRM_FORMAT_ARGB2101010:
2817 dspcntr |= DISPPLANE_BGRX101010;
2818 break;
2819 case DRM_FORMAT_XBGR2101010:
2820 case DRM_FORMAT_ABGR2101010:
2821 dspcntr |= DISPPLANE_RGBX101010;
2822 break;
2823 default:
2824 BUG();
2825 }
2826
2827 if (obj->tiling_mode != I915_TILING_NONE)
2828 dspcntr |= DISPPLANE_TILED;
2829
2830 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2831 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2832
2833 linear_offset = y * fb->pitches[0] + x * pixel_size;
2834 intel_crtc->dspaddr_offset =
2835 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2836 pixel_size,
2837 fb->pitches[0]);
2838 linear_offset -= intel_crtc->dspaddr_offset;
2839 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2840 dspcntr |= DISPPLANE_ROTATE_180;
2841
2842 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2843 x += (intel_crtc->config->pipe_src_w - 1);
2844 y += (intel_crtc->config->pipe_src_h - 1);
2845
2846 /* Finding the last pixel of the last line of the display
2847 data and adding to linear_offset*/
2848 linear_offset +=
2849 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2850 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2851 }
2852 }
2853
2854 I915_WRITE(reg, dspcntr);
2855
2856 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2857 I915_WRITE(DSPSURF(plane),
2858 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2859 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2860 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2861 } else {
2862 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2863 I915_WRITE(DSPLINOFF(plane), linear_offset);
2864 }
2865 POSTING_READ(reg);
2866 }
2867
2868 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2869 uint32_t pixel_format)
2870 {
2871 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2872
2873 /*
2874 * The stride is either expressed as a multiple of 64 bytes
2875 * chunks for linear buffers or in number of tiles for tiled
2876 * buffers.
2877 */
2878 switch (fb_modifier) {
2879 case DRM_FORMAT_MOD_NONE:
2880 return 64;
2881 case I915_FORMAT_MOD_X_TILED:
2882 if (INTEL_INFO(dev)->gen == 2)
2883 return 128;
2884 return 512;
2885 case I915_FORMAT_MOD_Y_TILED:
2886 /* No need to check for old gens and Y tiling since this is
2887 * about the display engine and those will be blocked before
2888 * we get here.
2889 */
2890 return 128;
2891 case I915_FORMAT_MOD_Yf_TILED:
2892 if (bits_per_pixel == 8)
2893 return 64;
2894 else
2895 return 128;
2896 default:
2897 MISSING_CASE(fb_modifier);
2898 return 64;
2899 }
2900 }
2901
2902 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2903 struct drm_i915_gem_object *obj)
2904 {
2905 enum i915_ggtt_view_type view = I915_GGTT_VIEW_NORMAL;
2906
2907 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2908 view = I915_GGTT_VIEW_ROTATED;
2909
2910 return i915_gem_obj_ggtt_offset_view(obj, view);
2911 }
2912
2913 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2914 struct drm_framebuffer *fb,
2915 int x, int y)
2916 {
2917 struct drm_device *dev = crtc->dev;
2918 struct drm_i915_private *dev_priv = dev->dev_private;
2919 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2920 struct drm_i915_gem_object *obj;
2921 int pipe = intel_crtc->pipe;
2922 u32 plane_ctl, stride_div;
2923 unsigned long surf_addr;
2924
2925 if (!intel_crtc->primary_enabled) {
2926 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2927 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2928 POSTING_READ(PLANE_CTL(pipe, 0));
2929 return;
2930 }
2931
2932 plane_ctl = PLANE_CTL_ENABLE |
2933 PLANE_CTL_PIPE_GAMMA_ENABLE |
2934 PLANE_CTL_PIPE_CSC_ENABLE;
2935
2936 switch (fb->pixel_format) {
2937 case DRM_FORMAT_RGB565:
2938 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2939 break;
2940 case DRM_FORMAT_XRGB8888:
2941 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2942 break;
2943 case DRM_FORMAT_ARGB8888:
2944 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2945 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2946 break;
2947 case DRM_FORMAT_XBGR8888:
2948 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2949 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2950 break;
2951 case DRM_FORMAT_ABGR8888:
2952 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2953 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2954 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2955 break;
2956 case DRM_FORMAT_XRGB2101010:
2957 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2958 break;
2959 case DRM_FORMAT_XBGR2101010:
2960 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2961 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2962 break;
2963 default:
2964 BUG();
2965 }
2966
2967 switch (fb->modifier[0]) {
2968 case DRM_FORMAT_MOD_NONE:
2969 break;
2970 case I915_FORMAT_MOD_X_TILED:
2971 plane_ctl |= PLANE_CTL_TILED_X;
2972 break;
2973 case I915_FORMAT_MOD_Y_TILED:
2974 plane_ctl |= PLANE_CTL_TILED_Y;
2975 break;
2976 case I915_FORMAT_MOD_Yf_TILED:
2977 plane_ctl |= PLANE_CTL_TILED_YF;
2978 break;
2979 default:
2980 MISSING_CASE(fb->modifier[0]);
2981 }
2982
2983 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2984 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180))
2985 plane_ctl |= PLANE_CTL_ROTATE_180;
2986
2987 obj = intel_fb_obj(fb);
2988 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
2989 fb->pixel_format);
2990 surf_addr = intel_plane_obj_offset(to_intel_plane(crtc->primary), obj);
2991
2992 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2993 I915_WRITE(PLANE_POS(pipe, 0), 0);
2994 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2995 I915_WRITE(PLANE_SIZE(pipe, 0),
2996 (intel_crtc->config->pipe_src_h - 1) << 16 |
2997 (intel_crtc->config->pipe_src_w - 1));
2998 I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
2999 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3000
3001 POSTING_READ(PLANE_SURF(pipe, 0));
3002 }
3003
3004 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3005 static int
3006 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3007 int x, int y, enum mode_set_atomic state)
3008 {
3009 struct drm_device *dev = crtc->dev;
3010 struct drm_i915_private *dev_priv = dev->dev_private;
3011
3012 if (dev_priv->display.disable_fbc)
3013 dev_priv->display.disable_fbc(dev);
3014
3015 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3016
3017 return 0;
3018 }
3019
3020 static void intel_complete_page_flips(struct drm_device *dev)
3021 {
3022 struct drm_crtc *crtc;
3023
3024 for_each_crtc(dev, crtc) {
3025 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3026 enum plane plane = intel_crtc->plane;
3027
3028 intel_prepare_page_flip(dev, plane);
3029 intel_finish_page_flip_plane(dev, plane);
3030 }
3031 }
3032
3033 static void intel_update_primary_planes(struct drm_device *dev)
3034 {
3035 struct drm_i915_private *dev_priv = dev->dev_private;
3036 struct drm_crtc *crtc;
3037
3038 for_each_crtc(dev, crtc) {
3039 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3040
3041 drm_modeset_lock(&crtc->mutex, NULL);
3042 /*
3043 * FIXME: Once we have proper support for primary planes (and
3044 * disabling them without disabling the entire crtc) allow again
3045 * a NULL crtc->primary->fb.
3046 */
3047 if (intel_crtc->active && crtc->primary->fb)
3048 dev_priv->display.update_primary_plane(crtc,
3049 crtc->primary->fb,
3050 crtc->x,
3051 crtc->y);
3052 drm_modeset_unlock(&crtc->mutex);
3053 }
3054 }
3055
3056 void intel_prepare_reset(struct drm_device *dev)
3057 {
3058 struct drm_i915_private *dev_priv = to_i915(dev);
3059 struct intel_crtc *crtc;
3060
3061 /* no reset support for gen2 */
3062 if (IS_GEN2(dev))
3063 return;
3064
3065 /* reset doesn't touch the display */
3066 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3067 return;
3068
3069 drm_modeset_lock_all(dev);
3070
3071 /*
3072 * Disabling the crtcs gracefully seems nicer. Also the
3073 * g33 docs say we should at least disable all the planes.
3074 */
3075 for_each_intel_crtc(dev, crtc) {
3076 if (crtc->active)
3077 dev_priv->display.crtc_disable(&crtc->base);
3078 }
3079 }
3080
3081 void intel_finish_reset(struct drm_device *dev)
3082 {
3083 struct drm_i915_private *dev_priv = to_i915(dev);
3084
3085 /*
3086 * Flips in the rings will be nuked by the reset,
3087 * so complete all pending flips so that user space
3088 * will get its events and not get stuck.
3089 */
3090 intel_complete_page_flips(dev);
3091
3092 /* no reset support for gen2 */
3093 if (IS_GEN2(dev))
3094 return;
3095
3096 /* reset doesn't touch the display */
3097 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3098 /*
3099 * Flips in the rings have been nuked by the reset,
3100 * so update the base address of all primary
3101 * planes to the the last fb to make sure we're
3102 * showing the correct fb after a reset.
3103 */
3104 intel_update_primary_planes(dev);
3105 return;
3106 }
3107
3108 /*
3109 * The display has been reset as well,
3110 * so need a full re-initialization.
3111 */
3112 intel_runtime_pm_disable_interrupts(dev_priv);
3113 intel_runtime_pm_enable_interrupts(dev_priv);
3114
3115 intel_modeset_init_hw(dev);
3116
3117 spin_lock_irq(&dev_priv->irq_lock);
3118 if (dev_priv->display.hpd_irq_setup)
3119 dev_priv->display.hpd_irq_setup(dev);
3120 spin_unlock_irq(&dev_priv->irq_lock);
3121
3122 intel_modeset_setup_hw_state(dev, true);
3123
3124 intel_hpd_init(dev_priv);
3125
3126 drm_modeset_unlock_all(dev);
3127 }
3128
3129 static int
3130 intel_finish_fb(struct drm_framebuffer *old_fb)
3131 {
3132 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3133 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3134 bool was_interruptible = dev_priv->mm.interruptible;
3135 int ret;
3136
3137 /* Big Hammer, we also need to ensure that any pending
3138 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3139 * current scanout is retired before unpinning the old
3140 * framebuffer.
3141 *
3142 * This should only fail upon a hung GPU, in which case we
3143 * can safely continue.
3144 */
3145 dev_priv->mm.interruptible = false;
3146 ret = i915_gem_object_finish_gpu(obj);
3147 dev_priv->mm.interruptible = was_interruptible;
3148
3149 return ret;
3150 }
3151
3152 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3153 {
3154 struct drm_device *dev = crtc->dev;
3155 struct drm_i915_private *dev_priv = dev->dev_private;
3156 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3157 bool pending;
3158
3159 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3160 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3161 return false;
3162
3163 spin_lock_irq(&dev->event_lock);
3164 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3165 spin_unlock_irq(&dev->event_lock);
3166
3167 return pending;
3168 }
3169
3170 static void intel_update_pipe_size(struct intel_crtc *crtc)
3171 {
3172 struct drm_device *dev = crtc->base.dev;
3173 struct drm_i915_private *dev_priv = dev->dev_private;
3174 const struct drm_display_mode *adjusted_mode;
3175
3176 if (!i915.fastboot)
3177 return;
3178
3179 /*
3180 * Update pipe size and adjust fitter if needed: the reason for this is
3181 * that in compute_mode_changes we check the native mode (not the pfit
3182 * mode) to see if we can flip rather than do a full mode set. In the
3183 * fastboot case, we'll flip, but if we don't update the pipesrc and
3184 * pfit state, we'll end up with a big fb scanned out into the wrong
3185 * sized surface.
3186 *
3187 * To fix this properly, we need to hoist the checks up into
3188 * compute_mode_changes (or above), check the actual pfit state and
3189 * whether the platform allows pfit disable with pipe active, and only
3190 * then update the pipesrc and pfit state, even on the flip path.
3191 */
3192
3193 adjusted_mode = &crtc->config->base.adjusted_mode;
3194
3195 I915_WRITE(PIPESRC(crtc->pipe),
3196 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3197 (adjusted_mode->crtc_vdisplay - 1));
3198 if (!crtc->config->pch_pfit.enabled &&
3199 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3200 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3201 I915_WRITE(PF_CTL(crtc->pipe), 0);
3202 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3203 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3204 }
3205 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3206 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3207 }
3208
3209 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3210 {
3211 struct drm_device *dev = crtc->dev;
3212 struct drm_i915_private *dev_priv = dev->dev_private;
3213 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3214 int pipe = intel_crtc->pipe;
3215 u32 reg, temp;
3216
3217 /* enable normal train */
3218 reg = FDI_TX_CTL(pipe);
3219 temp = I915_READ(reg);
3220 if (IS_IVYBRIDGE(dev)) {
3221 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3222 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3223 } else {
3224 temp &= ~FDI_LINK_TRAIN_NONE;
3225 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3226 }
3227 I915_WRITE(reg, temp);
3228
3229 reg = FDI_RX_CTL(pipe);
3230 temp = I915_READ(reg);
3231 if (HAS_PCH_CPT(dev)) {
3232 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3233 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3234 } else {
3235 temp &= ~FDI_LINK_TRAIN_NONE;
3236 temp |= FDI_LINK_TRAIN_NONE;
3237 }
3238 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3239
3240 /* wait one idle pattern time */
3241 POSTING_READ(reg);
3242 udelay(1000);
3243
3244 /* IVB wants error correction enabled */
3245 if (IS_IVYBRIDGE(dev))
3246 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3247 FDI_FE_ERRC_ENABLE);
3248 }
3249
3250 /* The FDI link training functions for ILK/Ibexpeak. */
3251 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3252 {
3253 struct drm_device *dev = crtc->dev;
3254 struct drm_i915_private *dev_priv = dev->dev_private;
3255 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3256 int pipe = intel_crtc->pipe;
3257 u32 reg, temp, tries;
3258
3259 /* FDI needs bits from pipe first */
3260 assert_pipe_enabled(dev_priv, pipe);
3261
3262 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3263 for train result */
3264 reg = FDI_RX_IMR(pipe);
3265 temp = I915_READ(reg);
3266 temp &= ~FDI_RX_SYMBOL_LOCK;
3267 temp &= ~FDI_RX_BIT_LOCK;
3268 I915_WRITE(reg, temp);
3269 I915_READ(reg);
3270 udelay(150);
3271
3272 /* enable CPU FDI TX and PCH FDI RX */
3273 reg = FDI_TX_CTL(pipe);
3274 temp = I915_READ(reg);
3275 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3276 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3277 temp &= ~FDI_LINK_TRAIN_NONE;
3278 temp |= FDI_LINK_TRAIN_PATTERN_1;
3279 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3280
3281 reg = FDI_RX_CTL(pipe);
3282 temp = I915_READ(reg);
3283 temp &= ~FDI_LINK_TRAIN_NONE;
3284 temp |= FDI_LINK_TRAIN_PATTERN_1;
3285 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3286
3287 POSTING_READ(reg);
3288 udelay(150);
3289
3290 /* Ironlake workaround, enable clock pointer after FDI enable*/
3291 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3292 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3293 FDI_RX_PHASE_SYNC_POINTER_EN);
3294
3295 reg = FDI_RX_IIR(pipe);
3296 for (tries = 0; tries < 5; tries++) {
3297 temp = I915_READ(reg);
3298 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3299
3300 if ((temp & FDI_RX_BIT_LOCK)) {
3301 DRM_DEBUG_KMS("FDI train 1 done.\n");
3302 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3303 break;
3304 }
3305 }
3306 if (tries == 5)
3307 DRM_ERROR("FDI train 1 fail!\n");
3308
3309 /* Train 2 */
3310 reg = FDI_TX_CTL(pipe);
3311 temp = I915_READ(reg);
3312 temp &= ~FDI_LINK_TRAIN_NONE;
3313 temp |= FDI_LINK_TRAIN_PATTERN_2;
3314 I915_WRITE(reg, temp);
3315
3316 reg = FDI_RX_CTL(pipe);
3317 temp = I915_READ(reg);
3318 temp &= ~FDI_LINK_TRAIN_NONE;
3319 temp |= FDI_LINK_TRAIN_PATTERN_2;
3320 I915_WRITE(reg, temp);
3321
3322 POSTING_READ(reg);
3323 udelay(150);
3324
3325 reg = FDI_RX_IIR(pipe);
3326 for (tries = 0; tries < 5; tries++) {
3327 temp = I915_READ(reg);
3328 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3329
3330 if (temp & FDI_RX_SYMBOL_LOCK) {
3331 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3332 DRM_DEBUG_KMS("FDI train 2 done.\n");
3333 break;
3334 }
3335 }
3336 if (tries == 5)
3337 DRM_ERROR("FDI train 2 fail!\n");
3338
3339 DRM_DEBUG_KMS("FDI train done\n");
3340
3341 }
3342
3343 static const int snb_b_fdi_train_param[] = {
3344 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3345 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3346 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3347 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3348 };
3349
3350 /* The FDI link training functions for SNB/Cougarpoint. */
3351 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3352 {
3353 struct drm_device *dev = crtc->dev;
3354 struct drm_i915_private *dev_priv = dev->dev_private;
3355 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3356 int pipe = intel_crtc->pipe;
3357 u32 reg, temp, i, retry;
3358
3359 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3360 for train result */
3361 reg = FDI_RX_IMR(pipe);
3362 temp = I915_READ(reg);
3363 temp &= ~FDI_RX_SYMBOL_LOCK;
3364 temp &= ~FDI_RX_BIT_LOCK;
3365 I915_WRITE(reg, temp);
3366
3367 POSTING_READ(reg);
3368 udelay(150);
3369
3370 /* enable CPU FDI TX and PCH FDI RX */
3371 reg = FDI_TX_CTL(pipe);
3372 temp = I915_READ(reg);
3373 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3374 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3375 temp &= ~FDI_LINK_TRAIN_NONE;
3376 temp |= FDI_LINK_TRAIN_PATTERN_1;
3377 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3378 /* SNB-B */
3379 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3380 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3381
3382 I915_WRITE(FDI_RX_MISC(pipe),
3383 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3384
3385 reg = FDI_RX_CTL(pipe);
3386 temp = I915_READ(reg);
3387 if (HAS_PCH_CPT(dev)) {
3388 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3389 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3390 } else {
3391 temp &= ~FDI_LINK_TRAIN_NONE;
3392 temp |= FDI_LINK_TRAIN_PATTERN_1;
3393 }
3394 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3395
3396 POSTING_READ(reg);
3397 udelay(150);
3398
3399 for (i = 0; i < 4; i++) {
3400 reg = FDI_TX_CTL(pipe);
3401 temp = I915_READ(reg);
3402 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3403 temp |= snb_b_fdi_train_param[i];
3404 I915_WRITE(reg, temp);
3405
3406 POSTING_READ(reg);
3407 udelay(500);
3408
3409 for (retry = 0; retry < 5; retry++) {
3410 reg = FDI_RX_IIR(pipe);
3411 temp = I915_READ(reg);
3412 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3413 if (temp & FDI_RX_BIT_LOCK) {
3414 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3415 DRM_DEBUG_KMS("FDI train 1 done.\n");
3416 break;
3417 }
3418 udelay(50);
3419 }
3420 if (retry < 5)
3421 break;
3422 }
3423 if (i == 4)
3424 DRM_ERROR("FDI train 1 fail!\n");
3425
3426 /* Train 2 */
3427 reg = FDI_TX_CTL(pipe);
3428 temp = I915_READ(reg);
3429 temp &= ~FDI_LINK_TRAIN_NONE;
3430 temp |= FDI_LINK_TRAIN_PATTERN_2;
3431 if (IS_GEN6(dev)) {
3432 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3433 /* SNB-B */
3434 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3435 }
3436 I915_WRITE(reg, temp);
3437
3438 reg = FDI_RX_CTL(pipe);
3439 temp = I915_READ(reg);
3440 if (HAS_PCH_CPT(dev)) {
3441 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3442 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3443 } else {
3444 temp &= ~FDI_LINK_TRAIN_NONE;
3445 temp |= FDI_LINK_TRAIN_PATTERN_2;
3446 }
3447 I915_WRITE(reg, temp);
3448
3449 POSTING_READ(reg);
3450 udelay(150);
3451
3452 for (i = 0; i < 4; i++) {
3453 reg = FDI_TX_CTL(pipe);
3454 temp = I915_READ(reg);
3455 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3456 temp |= snb_b_fdi_train_param[i];
3457 I915_WRITE(reg, temp);
3458
3459 POSTING_READ(reg);
3460 udelay(500);
3461
3462 for (retry = 0; retry < 5; retry++) {
3463 reg = FDI_RX_IIR(pipe);
3464 temp = I915_READ(reg);
3465 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3466 if (temp & FDI_RX_SYMBOL_LOCK) {
3467 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3468 DRM_DEBUG_KMS("FDI train 2 done.\n");
3469 break;
3470 }
3471 udelay(50);
3472 }
3473 if (retry < 5)
3474 break;
3475 }
3476 if (i == 4)
3477 DRM_ERROR("FDI train 2 fail!\n");
3478
3479 DRM_DEBUG_KMS("FDI train done.\n");
3480 }
3481
3482 /* Manual link training for Ivy Bridge A0 parts */
3483 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3484 {
3485 struct drm_device *dev = crtc->dev;
3486 struct drm_i915_private *dev_priv = dev->dev_private;
3487 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3488 int pipe = intel_crtc->pipe;
3489 u32 reg, temp, i, j;
3490
3491 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3492 for train result */
3493 reg = FDI_RX_IMR(pipe);
3494 temp = I915_READ(reg);
3495 temp &= ~FDI_RX_SYMBOL_LOCK;
3496 temp &= ~FDI_RX_BIT_LOCK;
3497 I915_WRITE(reg, temp);
3498
3499 POSTING_READ(reg);
3500 udelay(150);
3501
3502 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3503 I915_READ(FDI_RX_IIR(pipe)));
3504
3505 /* Try each vswing and preemphasis setting twice before moving on */
3506 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3507 /* disable first in case we need to retry */
3508 reg = FDI_TX_CTL(pipe);
3509 temp = I915_READ(reg);
3510 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3511 temp &= ~FDI_TX_ENABLE;
3512 I915_WRITE(reg, temp);
3513
3514 reg = FDI_RX_CTL(pipe);
3515 temp = I915_READ(reg);
3516 temp &= ~FDI_LINK_TRAIN_AUTO;
3517 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3518 temp &= ~FDI_RX_ENABLE;
3519 I915_WRITE(reg, temp);
3520
3521 /* enable CPU FDI TX and PCH FDI RX */
3522 reg = FDI_TX_CTL(pipe);
3523 temp = I915_READ(reg);
3524 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3525 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3526 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3527 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3528 temp |= snb_b_fdi_train_param[j/2];
3529 temp |= FDI_COMPOSITE_SYNC;
3530 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3531
3532 I915_WRITE(FDI_RX_MISC(pipe),
3533 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3534
3535 reg = FDI_RX_CTL(pipe);
3536 temp = I915_READ(reg);
3537 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3538 temp |= FDI_COMPOSITE_SYNC;
3539 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3540
3541 POSTING_READ(reg);
3542 udelay(1); /* should be 0.5us */
3543
3544 for (i = 0; i < 4; i++) {
3545 reg = FDI_RX_IIR(pipe);
3546 temp = I915_READ(reg);
3547 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3548
3549 if (temp & FDI_RX_BIT_LOCK ||
3550 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3551 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3552 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3553 i);
3554 break;
3555 }
3556 udelay(1); /* should be 0.5us */
3557 }
3558 if (i == 4) {
3559 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3560 continue;
3561 }
3562
3563 /* Train 2 */
3564 reg = FDI_TX_CTL(pipe);
3565 temp = I915_READ(reg);
3566 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3567 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3568 I915_WRITE(reg, temp);
3569
3570 reg = FDI_RX_CTL(pipe);
3571 temp = I915_READ(reg);
3572 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3573 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3574 I915_WRITE(reg, temp);
3575
3576 POSTING_READ(reg);
3577 udelay(2); /* should be 1.5us */
3578
3579 for (i = 0; i < 4; i++) {
3580 reg = FDI_RX_IIR(pipe);
3581 temp = I915_READ(reg);
3582 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3583
3584 if (temp & FDI_RX_SYMBOL_LOCK ||
3585 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3586 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3587 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3588 i);
3589 goto train_done;
3590 }
3591 udelay(2); /* should be 1.5us */
3592 }
3593 if (i == 4)
3594 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3595 }
3596
3597 train_done:
3598 DRM_DEBUG_KMS("FDI train done.\n");
3599 }
3600
3601 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3602 {
3603 struct drm_device *dev = intel_crtc->base.dev;
3604 struct drm_i915_private *dev_priv = dev->dev_private;
3605 int pipe = intel_crtc->pipe;
3606 u32 reg, temp;
3607
3608
3609 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3610 reg = FDI_RX_CTL(pipe);
3611 temp = I915_READ(reg);
3612 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3613 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3614 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3615 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3616
3617 POSTING_READ(reg);
3618 udelay(200);
3619
3620 /* Switch from Rawclk to PCDclk */
3621 temp = I915_READ(reg);
3622 I915_WRITE(reg, temp | FDI_PCDCLK);
3623
3624 POSTING_READ(reg);
3625 udelay(200);
3626
3627 /* Enable CPU FDI TX PLL, always on for Ironlake */
3628 reg = FDI_TX_CTL(pipe);
3629 temp = I915_READ(reg);
3630 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3631 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3632
3633 POSTING_READ(reg);
3634 udelay(100);
3635 }
3636 }
3637
3638 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3639 {
3640 struct drm_device *dev = intel_crtc->base.dev;
3641 struct drm_i915_private *dev_priv = dev->dev_private;
3642 int pipe = intel_crtc->pipe;
3643 u32 reg, temp;
3644
3645 /* Switch from PCDclk to Rawclk */
3646 reg = FDI_RX_CTL(pipe);
3647 temp = I915_READ(reg);
3648 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3649
3650 /* Disable CPU FDI TX PLL */
3651 reg = FDI_TX_CTL(pipe);
3652 temp = I915_READ(reg);
3653 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3654
3655 POSTING_READ(reg);
3656 udelay(100);
3657
3658 reg = FDI_RX_CTL(pipe);
3659 temp = I915_READ(reg);
3660 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3661
3662 /* Wait for the clocks to turn off. */
3663 POSTING_READ(reg);
3664 udelay(100);
3665 }
3666
3667 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3668 {
3669 struct drm_device *dev = crtc->dev;
3670 struct drm_i915_private *dev_priv = dev->dev_private;
3671 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3672 int pipe = intel_crtc->pipe;
3673 u32 reg, temp;
3674
3675 /* disable CPU FDI tx and PCH FDI rx */
3676 reg = FDI_TX_CTL(pipe);
3677 temp = I915_READ(reg);
3678 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3679 POSTING_READ(reg);
3680
3681 reg = FDI_RX_CTL(pipe);
3682 temp = I915_READ(reg);
3683 temp &= ~(0x7 << 16);
3684 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3685 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3686
3687 POSTING_READ(reg);
3688 udelay(100);
3689
3690 /* Ironlake workaround, disable clock pointer after downing FDI */
3691 if (HAS_PCH_IBX(dev))
3692 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3693
3694 /* still set train pattern 1 */
3695 reg = FDI_TX_CTL(pipe);
3696 temp = I915_READ(reg);
3697 temp &= ~FDI_LINK_TRAIN_NONE;
3698 temp |= FDI_LINK_TRAIN_PATTERN_1;
3699 I915_WRITE(reg, temp);
3700
3701 reg = FDI_RX_CTL(pipe);
3702 temp = I915_READ(reg);
3703 if (HAS_PCH_CPT(dev)) {
3704 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3705 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3706 } else {
3707 temp &= ~FDI_LINK_TRAIN_NONE;
3708 temp |= FDI_LINK_TRAIN_PATTERN_1;
3709 }
3710 /* BPC in FDI rx is consistent with that in PIPECONF */
3711 temp &= ~(0x07 << 16);
3712 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3713 I915_WRITE(reg, temp);
3714
3715 POSTING_READ(reg);
3716 udelay(100);
3717 }
3718
3719 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3720 {
3721 struct intel_crtc *crtc;
3722
3723 /* Note that we don't need to be called with mode_config.lock here
3724 * as our list of CRTC objects is static for the lifetime of the
3725 * device and so cannot disappear as we iterate. Similarly, we can
3726 * happily treat the predicates as racy, atomic checks as userspace
3727 * cannot claim and pin a new fb without at least acquring the
3728 * struct_mutex and so serialising with us.
3729 */
3730 for_each_intel_crtc(dev, crtc) {
3731 if (atomic_read(&crtc->unpin_work_count) == 0)
3732 continue;
3733
3734 if (crtc->unpin_work)
3735 intel_wait_for_vblank(dev, crtc->pipe);
3736
3737 return true;
3738 }
3739
3740 return false;
3741 }
3742
3743 static void page_flip_completed(struct intel_crtc *intel_crtc)
3744 {
3745 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3746 struct intel_unpin_work *work = intel_crtc->unpin_work;
3747
3748 /* ensure that the unpin work is consistent wrt ->pending. */
3749 smp_rmb();
3750 intel_crtc->unpin_work = NULL;
3751
3752 if (work->event)
3753 drm_send_vblank_event(intel_crtc->base.dev,
3754 intel_crtc->pipe,
3755 work->event);
3756
3757 drm_crtc_vblank_put(&intel_crtc->base);
3758
3759 wake_up_all(&dev_priv->pending_flip_queue);
3760 queue_work(dev_priv->wq, &work->work);
3761
3762 trace_i915_flip_complete(intel_crtc->plane,
3763 work->pending_flip_obj);
3764 }
3765
3766 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3767 {
3768 struct drm_device *dev = crtc->dev;
3769 struct drm_i915_private *dev_priv = dev->dev_private;
3770
3771 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3772 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3773 !intel_crtc_has_pending_flip(crtc),
3774 60*HZ) == 0)) {
3775 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3776
3777 spin_lock_irq(&dev->event_lock);
3778 if (intel_crtc->unpin_work) {
3779 WARN_ONCE(1, "Removing stuck page flip\n");
3780 page_flip_completed(intel_crtc);
3781 }
3782 spin_unlock_irq(&dev->event_lock);
3783 }
3784
3785 if (crtc->primary->fb) {
3786 mutex_lock(&dev->struct_mutex);
3787 intel_finish_fb(crtc->primary->fb);
3788 mutex_unlock(&dev->struct_mutex);
3789 }
3790 }
3791
3792 /* Program iCLKIP clock to the desired frequency */
3793 static void lpt_program_iclkip(struct drm_crtc *crtc)
3794 {
3795 struct drm_device *dev = crtc->dev;
3796 struct drm_i915_private *dev_priv = dev->dev_private;
3797 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3798 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3799 u32 temp;
3800
3801 mutex_lock(&dev_priv->dpio_lock);
3802
3803 /* It is necessary to ungate the pixclk gate prior to programming
3804 * the divisors, and gate it back when it is done.
3805 */
3806 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3807
3808 /* Disable SSCCTL */
3809 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3810 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3811 SBI_SSCCTL_DISABLE,
3812 SBI_ICLK);
3813
3814 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3815 if (clock == 20000) {
3816 auxdiv = 1;
3817 divsel = 0x41;
3818 phaseinc = 0x20;
3819 } else {
3820 /* The iCLK virtual clock root frequency is in MHz,
3821 * but the adjusted_mode->crtc_clock in in KHz. To get the
3822 * divisors, it is necessary to divide one by another, so we
3823 * convert the virtual clock precision to KHz here for higher
3824 * precision.
3825 */
3826 u32 iclk_virtual_root_freq = 172800 * 1000;
3827 u32 iclk_pi_range = 64;
3828 u32 desired_divisor, msb_divisor_value, pi_value;
3829
3830 desired_divisor = (iclk_virtual_root_freq / clock);
3831 msb_divisor_value = desired_divisor / iclk_pi_range;
3832 pi_value = desired_divisor % iclk_pi_range;
3833
3834 auxdiv = 0;
3835 divsel = msb_divisor_value - 2;
3836 phaseinc = pi_value;
3837 }
3838
3839 /* This should not happen with any sane values */
3840 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3841 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3842 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3843 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3844
3845 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3846 clock,
3847 auxdiv,
3848 divsel,
3849 phasedir,
3850 phaseinc);
3851
3852 /* Program SSCDIVINTPHASE6 */
3853 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3854 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3855 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3856 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3857 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3858 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3859 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3860 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3861
3862 /* Program SSCAUXDIV */
3863 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3864 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3865 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3866 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3867
3868 /* Enable modulator and associated divider */
3869 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3870 temp &= ~SBI_SSCCTL_DISABLE;
3871 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3872
3873 /* Wait for initialization time */
3874 udelay(24);
3875
3876 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3877
3878 mutex_unlock(&dev_priv->dpio_lock);
3879 }
3880
3881 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3882 enum pipe pch_transcoder)
3883 {
3884 struct drm_device *dev = crtc->base.dev;
3885 struct drm_i915_private *dev_priv = dev->dev_private;
3886 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3887
3888 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3889 I915_READ(HTOTAL(cpu_transcoder)));
3890 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3891 I915_READ(HBLANK(cpu_transcoder)));
3892 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3893 I915_READ(HSYNC(cpu_transcoder)));
3894
3895 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3896 I915_READ(VTOTAL(cpu_transcoder)));
3897 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3898 I915_READ(VBLANK(cpu_transcoder)));
3899 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3900 I915_READ(VSYNC(cpu_transcoder)));
3901 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3902 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3903 }
3904
3905 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
3906 {
3907 struct drm_i915_private *dev_priv = dev->dev_private;
3908 uint32_t temp;
3909
3910 temp = I915_READ(SOUTH_CHICKEN1);
3911 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
3912 return;
3913
3914 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3915 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3916
3917 temp &= ~FDI_BC_BIFURCATION_SELECT;
3918 if (enable)
3919 temp |= FDI_BC_BIFURCATION_SELECT;
3920
3921 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
3922 I915_WRITE(SOUTH_CHICKEN1, temp);
3923 POSTING_READ(SOUTH_CHICKEN1);
3924 }
3925
3926 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3927 {
3928 struct drm_device *dev = intel_crtc->base.dev;
3929
3930 switch (intel_crtc->pipe) {
3931 case PIPE_A:
3932 break;
3933 case PIPE_B:
3934 if (intel_crtc->config->fdi_lanes > 2)
3935 cpt_set_fdi_bc_bifurcation(dev, false);
3936 else
3937 cpt_set_fdi_bc_bifurcation(dev, true);
3938
3939 break;
3940 case PIPE_C:
3941 cpt_set_fdi_bc_bifurcation(dev, true);
3942
3943 break;
3944 default:
3945 BUG();
3946 }
3947 }
3948
3949 /*
3950 * Enable PCH resources required for PCH ports:
3951 * - PCH PLLs
3952 * - FDI training & RX/TX
3953 * - update transcoder timings
3954 * - DP transcoding bits
3955 * - transcoder
3956 */
3957 static void ironlake_pch_enable(struct drm_crtc *crtc)
3958 {
3959 struct drm_device *dev = crtc->dev;
3960 struct drm_i915_private *dev_priv = dev->dev_private;
3961 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3962 int pipe = intel_crtc->pipe;
3963 u32 reg, temp;
3964
3965 assert_pch_transcoder_disabled(dev_priv, pipe);
3966
3967 if (IS_IVYBRIDGE(dev))
3968 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3969
3970 /* Write the TU size bits before fdi link training, so that error
3971 * detection works. */
3972 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3973 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3974
3975 /* For PCH output, training FDI link */
3976 dev_priv->display.fdi_link_train(crtc);
3977
3978 /* We need to program the right clock selection before writing the pixel
3979 * mutliplier into the DPLL. */
3980 if (HAS_PCH_CPT(dev)) {
3981 u32 sel;
3982
3983 temp = I915_READ(PCH_DPLL_SEL);
3984 temp |= TRANS_DPLL_ENABLE(pipe);
3985 sel = TRANS_DPLLB_SEL(pipe);
3986 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
3987 temp |= sel;
3988 else
3989 temp &= ~sel;
3990 I915_WRITE(PCH_DPLL_SEL, temp);
3991 }
3992
3993 /* XXX: pch pll's can be enabled any time before we enable the PCH
3994 * transcoder, and we actually should do this to not upset any PCH
3995 * transcoder that already use the clock when we share it.
3996 *
3997 * Note that enable_shared_dpll tries to do the right thing, but
3998 * get_shared_dpll unconditionally resets the pll - we need that to have
3999 * the right LVDS enable sequence. */
4000 intel_enable_shared_dpll(intel_crtc);
4001
4002 /* set transcoder timing, panel must allow it */
4003 assert_panel_unlocked(dev_priv, pipe);
4004 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4005
4006 intel_fdi_normal_train(crtc);
4007
4008 /* For PCH DP, enable TRANS_DP_CTL */
4009 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4010 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4011 reg = TRANS_DP_CTL(pipe);
4012 temp = I915_READ(reg);
4013 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4014 TRANS_DP_SYNC_MASK |
4015 TRANS_DP_BPC_MASK);
4016 temp |= (TRANS_DP_OUTPUT_ENABLE |
4017 TRANS_DP_ENH_FRAMING);
4018 temp |= bpc << 9; /* same format but at 11:9 */
4019
4020 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4021 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4022 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4023 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4024
4025 switch (intel_trans_dp_port_sel(crtc)) {
4026 case PCH_DP_B:
4027 temp |= TRANS_DP_PORT_SEL_B;
4028 break;
4029 case PCH_DP_C:
4030 temp |= TRANS_DP_PORT_SEL_C;
4031 break;
4032 case PCH_DP_D:
4033 temp |= TRANS_DP_PORT_SEL_D;
4034 break;
4035 default:
4036 BUG();
4037 }
4038
4039 I915_WRITE(reg, temp);
4040 }
4041
4042 ironlake_enable_pch_transcoder(dev_priv, pipe);
4043 }
4044
4045 static void lpt_pch_enable(struct drm_crtc *crtc)
4046 {
4047 struct drm_device *dev = crtc->dev;
4048 struct drm_i915_private *dev_priv = dev->dev_private;
4049 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4050 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4051
4052 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4053
4054 lpt_program_iclkip(crtc);
4055
4056 /* Set transcoder timing. */
4057 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4058
4059 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4060 }
4061
4062 void intel_put_shared_dpll(struct intel_crtc *crtc)
4063 {
4064 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4065
4066 if (pll == NULL)
4067 return;
4068
4069 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
4070 WARN(1, "bad %s crtc mask\n", pll->name);
4071 return;
4072 }
4073
4074 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4075 if (pll->config.crtc_mask == 0) {
4076 WARN_ON(pll->on);
4077 WARN_ON(pll->active);
4078 }
4079
4080 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
4081 }
4082
4083 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4084 struct intel_crtc_state *crtc_state)
4085 {
4086 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4087 struct intel_shared_dpll *pll;
4088 enum intel_dpll_id i;
4089
4090 if (HAS_PCH_IBX(dev_priv->dev)) {
4091 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4092 i = (enum intel_dpll_id) crtc->pipe;
4093 pll = &dev_priv->shared_dplls[i];
4094
4095 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4096 crtc->base.base.id, pll->name);
4097
4098 WARN_ON(pll->new_config->crtc_mask);
4099
4100 goto found;
4101 }
4102
4103 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4104 pll = &dev_priv->shared_dplls[i];
4105
4106 /* Only want to check enabled timings first */
4107 if (pll->new_config->crtc_mask == 0)
4108 continue;
4109
4110 if (memcmp(&crtc_state->dpll_hw_state,
4111 &pll->new_config->hw_state,
4112 sizeof(pll->new_config->hw_state)) == 0) {
4113 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4114 crtc->base.base.id, pll->name,
4115 pll->new_config->crtc_mask,
4116 pll->active);
4117 goto found;
4118 }
4119 }
4120
4121 /* Ok no matching timings, maybe there's a free one? */
4122 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4123 pll = &dev_priv->shared_dplls[i];
4124 if (pll->new_config->crtc_mask == 0) {
4125 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4126 crtc->base.base.id, pll->name);
4127 goto found;
4128 }
4129 }
4130
4131 return NULL;
4132
4133 found:
4134 if (pll->new_config->crtc_mask == 0)
4135 pll->new_config->hw_state = crtc_state->dpll_hw_state;
4136
4137 crtc_state->shared_dpll = i;
4138 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4139 pipe_name(crtc->pipe));
4140
4141 pll->new_config->crtc_mask |= 1 << crtc->pipe;
4142
4143 return pll;
4144 }
4145
4146 /**
4147 * intel_shared_dpll_start_config - start a new PLL staged config
4148 * @dev_priv: DRM device
4149 * @clear_pipes: mask of pipes that will have their PLLs freed
4150 *
4151 * Starts a new PLL staged config, copying the current config but
4152 * releasing the references of pipes specified in clear_pipes.
4153 */
4154 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4155 unsigned clear_pipes)
4156 {
4157 struct intel_shared_dpll *pll;
4158 enum intel_dpll_id i;
4159
4160 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4161 pll = &dev_priv->shared_dplls[i];
4162
4163 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4164 GFP_KERNEL);
4165 if (!pll->new_config)
4166 goto cleanup;
4167
4168 pll->new_config->crtc_mask &= ~clear_pipes;
4169 }
4170
4171 return 0;
4172
4173 cleanup:
4174 while (--i >= 0) {
4175 pll = &dev_priv->shared_dplls[i];
4176 kfree(pll->new_config);
4177 pll->new_config = NULL;
4178 }
4179
4180 return -ENOMEM;
4181 }
4182
4183 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4184 {
4185 struct intel_shared_dpll *pll;
4186 enum intel_dpll_id i;
4187
4188 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4189 pll = &dev_priv->shared_dplls[i];
4190
4191 WARN_ON(pll->new_config == &pll->config);
4192
4193 pll->config = *pll->new_config;
4194 kfree(pll->new_config);
4195 pll->new_config = NULL;
4196 }
4197 }
4198
4199 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4200 {
4201 struct intel_shared_dpll *pll;
4202 enum intel_dpll_id i;
4203
4204 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4205 pll = &dev_priv->shared_dplls[i];
4206
4207 WARN_ON(pll->new_config == &pll->config);
4208
4209 kfree(pll->new_config);
4210 pll->new_config = NULL;
4211 }
4212 }
4213
4214 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4215 {
4216 struct drm_i915_private *dev_priv = dev->dev_private;
4217 int dslreg = PIPEDSL(pipe);
4218 u32 temp;
4219
4220 temp = I915_READ(dslreg);
4221 udelay(500);
4222 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4223 if (wait_for(I915_READ(dslreg) != temp, 5))
4224 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4225 }
4226 }
4227
4228 static void skylake_pfit_enable(struct intel_crtc *crtc)
4229 {
4230 struct drm_device *dev = crtc->base.dev;
4231 struct drm_i915_private *dev_priv = dev->dev_private;
4232 int pipe = crtc->pipe;
4233
4234 if (crtc->config->pch_pfit.enabled) {
4235 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
4236 I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4237 I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4238 }
4239 }
4240
4241 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4242 {
4243 struct drm_device *dev = crtc->base.dev;
4244 struct drm_i915_private *dev_priv = dev->dev_private;
4245 int pipe = crtc->pipe;
4246
4247 if (crtc->config->pch_pfit.enabled) {
4248 /* Force use of hard-coded filter coefficients
4249 * as some pre-programmed values are broken,
4250 * e.g. x201.
4251 */
4252 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4253 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4254 PF_PIPE_SEL_IVB(pipe));
4255 else
4256 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4257 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4258 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4259 }
4260 }
4261
4262 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4263 {
4264 struct drm_device *dev = crtc->dev;
4265 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4266 struct drm_plane *plane;
4267 struct intel_plane *intel_plane;
4268
4269 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4270 intel_plane = to_intel_plane(plane);
4271 if (intel_plane->pipe == pipe)
4272 intel_plane_restore(&intel_plane->base);
4273 }
4274 }
4275
4276 /*
4277 * Disable a plane internally without actually modifying the plane's state.
4278 * This will allow us to easily restore the plane later by just reprogramming
4279 * its state.
4280 */
4281 static void disable_plane_internal(struct drm_plane *plane)
4282 {
4283 struct intel_plane *intel_plane = to_intel_plane(plane);
4284 struct drm_plane_state *state =
4285 plane->funcs->atomic_duplicate_state(plane);
4286 struct intel_plane_state *intel_state = to_intel_plane_state(state);
4287
4288 intel_state->visible = false;
4289 intel_plane->commit_plane(plane, intel_state);
4290
4291 intel_plane_destroy_state(plane, state);
4292 }
4293
4294 static void intel_disable_sprite_planes(struct drm_crtc *crtc)
4295 {
4296 struct drm_device *dev = crtc->dev;
4297 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4298 struct drm_plane *plane;
4299 struct intel_plane *intel_plane;
4300
4301 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4302 intel_plane = to_intel_plane(plane);
4303 if (plane->fb && intel_plane->pipe == pipe)
4304 disable_plane_internal(plane);
4305 }
4306 }
4307
4308 void hsw_enable_ips(struct intel_crtc *crtc)
4309 {
4310 struct drm_device *dev = crtc->base.dev;
4311 struct drm_i915_private *dev_priv = dev->dev_private;
4312
4313 if (!crtc->config->ips_enabled)
4314 return;
4315
4316 /* We can only enable IPS after we enable a plane and wait for a vblank */
4317 intel_wait_for_vblank(dev, crtc->pipe);
4318
4319 assert_plane_enabled(dev_priv, crtc->plane);
4320 if (IS_BROADWELL(dev)) {
4321 mutex_lock(&dev_priv->rps.hw_lock);
4322 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4323 mutex_unlock(&dev_priv->rps.hw_lock);
4324 /* Quoting Art Runyan: "its not safe to expect any particular
4325 * value in IPS_CTL bit 31 after enabling IPS through the
4326 * mailbox." Moreover, the mailbox may return a bogus state,
4327 * so we need to just enable it and continue on.
4328 */
4329 } else {
4330 I915_WRITE(IPS_CTL, IPS_ENABLE);
4331 /* The bit only becomes 1 in the next vblank, so this wait here
4332 * is essentially intel_wait_for_vblank. If we don't have this
4333 * and don't wait for vblanks until the end of crtc_enable, then
4334 * the HW state readout code will complain that the expected
4335 * IPS_CTL value is not the one we read. */
4336 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4337 DRM_ERROR("Timed out waiting for IPS enable\n");
4338 }
4339 }
4340
4341 void hsw_disable_ips(struct intel_crtc *crtc)
4342 {
4343 struct drm_device *dev = crtc->base.dev;
4344 struct drm_i915_private *dev_priv = dev->dev_private;
4345
4346 if (!crtc->config->ips_enabled)
4347 return;
4348
4349 assert_plane_enabled(dev_priv, crtc->plane);
4350 if (IS_BROADWELL(dev)) {
4351 mutex_lock(&dev_priv->rps.hw_lock);
4352 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4353 mutex_unlock(&dev_priv->rps.hw_lock);
4354 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4355 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4356 DRM_ERROR("Timed out waiting for IPS disable\n");
4357 } else {
4358 I915_WRITE(IPS_CTL, 0);
4359 POSTING_READ(IPS_CTL);
4360 }
4361
4362 /* We need to wait for a vblank before we can disable the plane. */
4363 intel_wait_for_vblank(dev, crtc->pipe);
4364 }
4365
4366 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4367 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4368 {
4369 struct drm_device *dev = crtc->dev;
4370 struct drm_i915_private *dev_priv = dev->dev_private;
4371 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4372 enum pipe pipe = intel_crtc->pipe;
4373 int palreg = PALETTE(pipe);
4374 int i;
4375 bool reenable_ips = false;
4376
4377 /* The clocks have to be on to load the palette. */
4378 if (!crtc->state->enable || !intel_crtc->active)
4379 return;
4380
4381 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4382 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4383 assert_dsi_pll_enabled(dev_priv);
4384 else
4385 assert_pll_enabled(dev_priv, pipe);
4386 }
4387
4388 /* use legacy palette for Ironlake */
4389 if (!HAS_GMCH_DISPLAY(dev))
4390 palreg = LGC_PALETTE(pipe);
4391
4392 /* Workaround : Do not read or write the pipe palette/gamma data while
4393 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4394 */
4395 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4396 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4397 GAMMA_MODE_MODE_SPLIT)) {
4398 hsw_disable_ips(intel_crtc);
4399 reenable_ips = true;
4400 }
4401
4402 for (i = 0; i < 256; i++) {
4403 I915_WRITE(palreg + 4 * i,
4404 (intel_crtc->lut_r[i] << 16) |
4405 (intel_crtc->lut_g[i] << 8) |
4406 intel_crtc->lut_b[i]);
4407 }
4408
4409 if (reenable_ips)
4410 hsw_enable_ips(intel_crtc);
4411 }
4412
4413 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4414 {
4415 if (!enable && intel_crtc->overlay) {
4416 struct drm_device *dev = intel_crtc->base.dev;
4417 struct drm_i915_private *dev_priv = dev->dev_private;
4418
4419 mutex_lock(&dev->struct_mutex);
4420 dev_priv->mm.interruptible = false;
4421 (void) intel_overlay_switch_off(intel_crtc->overlay);
4422 dev_priv->mm.interruptible = true;
4423 mutex_unlock(&dev->struct_mutex);
4424 }
4425
4426 /* Let userspace switch the overlay on again. In most cases userspace
4427 * has to recompute where to put it anyway.
4428 */
4429 }
4430
4431 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4432 {
4433 struct drm_device *dev = crtc->dev;
4434 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4435 int pipe = intel_crtc->pipe;
4436
4437 intel_enable_primary_hw_plane(crtc->primary, crtc);
4438 intel_enable_sprite_planes(crtc);
4439 intel_crtc_update_cursor(crtc, true);
4440 intel_crtc_dpms_overlay(intel_crtc, true);
4441
4442 hsw_enable_ips(intel_crtc);
4443
4444 mutex_lock(&dev->struct_mutex);
4445 intel_fbc_update(dev);
4446 mutex_unlock(&dev->struct_mutex);
4447
4448 /*
4449 * FIXME: Once we grow proper nuclear flip support out of this we need
4450 * to compute the mask of flip planes precisely. For the time being
4451 * consider this a flip from a NULL plane.
4452 */
4453 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4454 }
4455
4456 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4457 {
4458 struct drm_device *dev = crtc->dev;
4459 struct drm_i915_private *dev_priv = dev->dev_private;
4460 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4461 int pipe = intel_crtc->pipe;
4462
4463 intel_crtc_wait_for_pending_flips(crtc);
4464
4465 if (dev_priv->fbc.crtc == intel_crtc)
4466 intel_fbc_disable(dev);
4467
4468 hsw_disable_ips(intel_crtc);
4469
4470 intel_crtc_dpms_overlay(intel_crtc, false);
4471 intel_crtc_update_cursor(crtc, false);
4472 intel_disable_sprite_planes(crtc);
4473 intel_disable_primary_hw_plane(crtc->primary, crtc);
4474
4475 /*
4476 * FIXME: Once we grow proper nuclear flip support out of this we need
4477 * to compute the mask of flip planes precisely. For the time being
4478 * consider this a flip to a NULL plane.
4479 */
4480 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4481 }
4482
4483 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4484 {
4485 struct drm_device *dev = crtc->dev;
4486 struct drm_i915_private *dev_priv = dev->dev_private;
4487 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4488 struct intel_encoder *encoder;
4489 int pipe = intel_crtc->pipe;
4490
4491 WARN_ON(!crtc->state->enable);
4492
4493 if (intel_crtc->active)
4494 return;
4495
4496 if (intel_crtc->config->has_pch_encoder)
4497 intel_prepare_shared_dpll(intel_crtc);
4498
4499 if (intel_crtc->config->has_dp_encoder)
4500 intel_dp_set_m_n(intel_crtc, M1_N1);
4501
4502 intel_set_pipe_timings(intel_crtc);
4503
4504 if (intel_crtc->config->has_pch_encoder) {
4505 intel_cpu_transcoder_set_m_n(intel_crtc,
4506 &intel_crtc->config->fdi_m_n, NULL);
4507 }
4508
4509 ironlake_set_pipeconf(crtc);
4510
4511 intel_crtc->active = true;
4512
4513 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4514 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4515
4516 for_each_encoder_on_crtc(dev, crtc, encoder)
4517 if (encoder->pre_enable)
4518 encoder->pre_enable(encoder);
4519
4520 if (intel_crtc->config->has_pch_encoder) {
4521 /* Note: FDI PLL enabling _must_ be done before we enable the
4522 * cpu pipes, hence this is separate from all the other fdi/pch
4523 * enabling. */
4524 ironlake_fdi_pll_enable(intel_crtc);
4525 } else {
4526 assert_fdi_tx_disabled(dev_priv, pipe);
4527 assert_fdi_rx_disabled(dev_priv, pipe);
4528 }
4529
4530 ironlake_pfit_enable(intel_crtc);
4531
4532 /*
4533 * On ILK+ LUT must be loaded before the pipe is running but with
4534 * clocks enabled
4535 */
4536 intel_crtc_load_lut(crtc);
4537
4538 intel_update_watermarks(crtc);
4539 intel_enable_pipe(intel_crtc);
4540
4541 if (intel_crtc->config->has_pch_encoder)
4542 ironlake_pch_enable(crtc);
4543
4544 assert_vblank_disabled(crtc);
4545 drm_crtc_vblank_on(crtc);
4546
4547 for_each_encoder_on_crtc(dev, crtc, encoder)
4548 encoder->enable(encoder);
4549
4550 if (HAS_PCH_CPT(dev))
4551 cpt_verify_modeset(dev, intel_crtc->pipe);
4552
4553 intel_crtc_enable_planes(crtc);
4554 }
4555
4556 /* IPS only exists on ULT machines and is tied to pipe A. */
4557 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4558 {
4559 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4560 }
4561
4562 /*
4563 * This implements the workaround described in the "notes" section of the mode
4564 * set sequence documentation. When going from no pipes or single pipe to
4565 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4566 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4567 */
4568 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4569 {
4570 struct drm_device *dev = crtc->base.dev;
4571 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4572
4573 /* We want to get the other_active_crtc only if there's only 1 other
4574 * active crtc. */
4575 for_each_intel_crtc(dev, crtc_it) {
4576 if (!crtc_it->active || crtc_it == crtc)
4577 continue;
4578
4579 if (other_active_crtc)
4580 return;
4581
4582 other_active_crtc = crtc_it;
4583 }
4584 if (!other_active_crtc)
4585 return;
4586
4587 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4588 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4589 }
4590
4591 static void haswell_crtc_enable(struct drm_crtc *crtc)
4592 {
4593 struct drm_device *dev = crtc->dev;
4594 struct drm_i915_private *dev_priv = dev->dev_private;
4595 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4596 struct intel_encoder *encoder;
4597 int pipe = intel_crtc->pipe;
4598
4599 WARN_ON(!crtc->state->enable);
4600
4601 if (intel_crtc->active)
4602 return;
4603
4604 if (intel_crtc_to_shared_dpll(intel_crtc))
4605 intel_enable_shared_dpll(intel_crtc);
4606
4607 if (intel_crtc->config->has_dp_encoder)
4608 intel_dp_set_m_n(intel_crtc, M1_N1);
4609
4610 intel_set_pipe_timings(intel_crtc);
4611
4612 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4613 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4614 intel_crtc->config->pixel_multiplier - 1);
4615 }
4616
4617 if (intel_crtc->config->has_pch_encoder) {
4618 intel_cpu_transcoder_set_m_n(intel_crtc,
4619 &intel_crtc->config->fdi_m_n, NULL);
4620 }
4621
4622 haswell_set_pipeconf(crtc);
4623
4624 intel_set_pipe_csc(crtc);
4625
4626 intel_crtc->active = true;
4627
4628 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4629 for_each_encoder_on_crtc(dev, crtc, encoder)
4630 if (encoder->pre_enable)
4631 encoder->pre_enable(encoder);
4632
4633 if (intel_crtc->config->has_pch_encoder) {
4634 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4635 true);
4636 dev_priv->display.fdi_link_train(crtc);
4637 }
4638
4639 intel_ddi_enable_pipe_clock(intel_crtc);
4640
4641 if (IS_SKYLAKE(dev))
4642 skylake_pfit_enable(intel_crtc);
4643 else
4644 ironlake_pfit_enable(intel_crtc);
4645
4646 /*
4647 * On ILK+ LUT must be loaded before the pipe is running but with
4648 * clocks enabled
4649 */
4650 intel_crtc_load_lut(crtc);
4651
4652 intel_ddi_set_pipe_settings(crtc);
4653 intel_ddi_enable_transcoder_func(crtc);
4654
4655 intel_update_watermarks(crtc);
4656 intel_enable_pipe(intel_crtc);
4657
4658 if (intel_crtc->config->has_pch_encoder)
4659 lpt_pch_enable(crtc);
4660
4661 if (intel_crtc->config->dp_encoder_is_mst)
4662 intel_ddi_set_vc_payload_alloc(crtc, true);
4663
4664 assert_vblank_disabled(crtc);
4665 drm_crtc_vblank_on(crtc);
4666
4667 for_each_encoder_on_crtc(dev, crtc, encoder) {
4668 encoder->enable(encoder);
4669 intel_opregion_notify_encoder(encoder, true);
4670 }
4671
4672 /* If we change the relative order between pipe/planes enabling, we need
4673 * to change the workaround. */
4674 haswell_mode_set_planes_workaround(intel_crtc);
4675 intel_crtc_enable_planes(crtc);
4676 }
4677
4678 static void skylake_pfit_disable(struct intel_crtc *crtc)
4679 {
4680 struct drm_device *dev = crtc->base.dev;
4681 struct drm_i915_private *dev_priv = dev->dev_private;
4682 int pipe = crtc->pipe;
4683
4684 /* To avoid upsetting the power well on haswell only disable the pfit if
4685 * it's in use. The hw state code will make sure we get this right. */
4686 if (crtc->config->pch_pfit.enabled) {
4687 I915_WRITE(PS_CTL(pipe), 0);
4688 I915_WRITE(PS_WIN_POS(pipe), 0);
4689 I915_WRITE(PS_WIN_SZ(pipe), 0);
4690 }
4691 }
4692
4693 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4694 {
4695 struct drm_device *dev = crtc->base.dev;
4696 struct drm_i915_private *dev_priv = dev->dev_private;
4697 int pipe = crtc->pipe;
4698
4699 /* To avoid upsetting the power well on haswell only disable the pfit if
4700 * it's in use. The hw state code will make sure we get this right. */
4701 if (crtc->config->pch_pfit.enabled) {
4702 I915_WRITE(PF_CTL(pipe), 0);
4703 I915_WRITE(PF_WIN_POS(pipe), 0);
4704 I915_WRITE(PF_WIN_SZ(pipe), 0);
4705 }
4706 }
4707
4708 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4709 {
4710 struct drm_device *dev = crtc->dev;
4711 struct drm_i915_private *dev_priv = dev->dev_private;
4712 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4713 struct intel_encoder *encoder;
4714 int pipe = intel_crtc->pipe;
4715 u32 reg, temp;
4716
4717 if (!intel_crtc->active)
4718 return;
4719
4720 intel_crtc_disable_planes(crtc);
4721
4722 for_each_encoder_on_crtc(dev, crtc, encoder)
4723 encoder->disable(encoder);
4724
4725 drm_crtc_vblank_off(crtc);
4726 assert_vblank_disabled(crtc);
4727
4728 if (intel_crtc->config->has_pch_encoder)
4729 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4730
4731 intel_disable_pipe(intel_crtc);
4732
4733 ironlake_pfit_disable(intel_crtc);
4734
4735 for_each_encoder_on_crtc(dev, crtc, encoder)
4736 if (encoder->post_disable)
4737 encoder->post_disable(encoder);
4738
4739 if (intel_crtc->config->has_pch_encoder) {
4740 ironlake_fdi_disable(crtc);
4741
4742 ironlake_disable_pch_transcoder(dev_priv, pipe);
4743
4744 if (HAS_PCH_CPT(dev)) {
4745 /* disable TRANS_DP_CTL */
4746 reg = TRANS_DP_CTL(pipe);
4747 temp = I915_READ(reg);
4748 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4749 TRANS_DP_PORT_SEL_MASK);
4750 temp |= TRANS_DP_PORT_SEL_NONE;
4751 I915_WRITE(reg, temp);
4752
4753 /* disable DPLL_SEL */
4754 temp = I915_READ(PCH_DPLL_SEL);
4755 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4756 I915_WRITE(PCH_DPLL_SEL, temp);
4757 }
4758
4759 /* disable PCH DPLL */
4760 intel_disable_shared_dpll(intel_crtc);
4761
4762 ironlake_fdi_pll_disable(intel_crtc);
4763 }
4764
4765 intel_crtc->active = false;
4766 intel_update_watermarks(crtc);
4767
4768 mutex_lock(&dev->struct_mutex);
4769 intel_fbc_update(dev);
4770 mutex_unlock(&dev->struct_mutex);
4771 }
4772
4773 static void haswell_crtc_disable(struct drm_crtc *crtc)
4774 {
4775 struct drm_device *dev = crtc->dev;
4776 struct drm_i915_private *dev_priv = dev->dev_private;
4777 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4778 struct intel_encoder *encoder;
4779 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4780
4781 if (!intel_crtc->active)
4782 return;
4783
4784 intel_crtc_disable_planes(crtc);
4785
4786 for_each_encoder_on_crtc(dev, crtc, encoder) {
4787 intel_opregion_notify_encoder(encoder, false);
4788 encoder->disable(encoder);
4789 }
4790
4791 drm_crtc_vblank_off(crtc);
4792 assert_vblank_disabled(crtc);
4793
4794 if (intel_crtc->config->has_pch_encoder)
4795 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4796 false);
4797 intel_disable_pipe(intel_crtc);
4798
4799 if (intel_crtc->config->dp_encoder_is_mst)
4800 intel_ddi_set_vc_payload_alloc(crtc, false);
4801
4802 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4803
4804 if (IS_SKYLAKE(dev))
4805 skylake_pfit_disable(intel_crtc);
4806 else
4807 ironlake_pfit_disable(intel_crtc);
4808
4809 intel_ddi_disable_pipe_clock(intel_crtc);
4810
4811 if (intel_crtc->config->has_pch_encoder) {
4812 lpt_disable_pch_transcoder(dev_priv);
4813 intel_ddi_fdi_disable(crtc);
4814 }
4815
4816 for_each_encoder_on_crtc(dev, crtc, encoder)
4817 if (encoder->post_disable)
4818 encoder->post_disable(encoder);
4819
4820 intel_crtc->active = false;
4821 intel_update_watermarks(crtc);
4822
4823 mutex_lock(&dev->struct_mutex);
4824 intel_fbc_update(dev);
4825 mutex_unlock(&dev->struct_mutex);
4826
4827 if (intel_crtc_to_shared_dpll(intel_crtc))
4828 intel_disable_shared_dpll(intel_crtc);
4829 }
4830
4831 static void ironlake_crtc_off(struct drm_crtc *crtc)
4832 {
4833 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4834 intel_put_shared_dpll(intel_crtc);
4835 }
4836
4837
4838 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4839 {
4840 struct drm_device *dev = crtc->base.dev;
4841 struct drm_i915_private *dev_priv = dev->dev_private;
4842 struct intel_crtc_state *pipe_config = crtc->config;
4843
4844 if (!pipe_config->gmch_pfit.control)
4845 return;
4846
4847 /*
4848 * The panel fitter should only be adjusted whilst the pipe is disabled,
4849 * according to register description and PRM.
4850 */
4851 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4852 assert_pipe_disabled(dev_priv, crtc->pipe);
4853
4854 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4855 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4856
4857 /* Border color in case we don't scale up to the full screen. Black by
4858 * default, change to something else for debugging. */
4859 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4860 }
4861
4862 static enum intel_display_power_domain port_to_power_domain(enum port port)
4863 {
4864 switch (port) {
4865 case PORT_A:
4866 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4867 case PORT_B:
4868 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4869 case PORT_C:
4870 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4871 case PORT_D:
4872 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4873 default:
4874 WARN_ON_ONCE(1);
4875 return POWER_DOMAIN_PORT_OTHER;
4876 }
4877 }
4878
4879 #define for_each_power_domain(domain, mask) \
4880 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4881 if ((1 << (domain)) & (mask))
4882
4883 enum intel_display_power_domain
4884 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4885 {
4886 struct drm_device *dev = intel_encoder->base.dev;
4887 struct intel_digital_port *intel_dig_port;
4888
4889 switch (intel_encoder->type) {
4890 case INTEL_OUTPUT_UNKNOWN:
4891 /* Only DDI platforms should ever use this output type */
4892 WARN_ON_ONCE(!HAS_DDI(dev));
4893 case INTEL_OUTPUT_DISPLAYPORT:
4894 case INTEL_OUTPUT_HDMI:
4895 case INTEL_OUTPUT_EDP:
4896 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4897 return port_to_power_domain(intel_dig_port->port);
4898 case INTEL_OUTPUT_DP_MST:
4899 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4900 return port_to_power_domain(intel_dig_port->port);
4901 case INTEL_OUTPUT_ANALOG:
4902 return POWER_DOMAIN_PORT_CRT;
4903 case INTEL_OUTPUT_DSI:
4904 return POWER_DOMAIN_PORT_DSI;
4905 default:
4906 return POWER_DOMAIN_PORT_OTHER;
4907 }
4908 }
4909
4910 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4911 {
4912 struct drm_device *dev = crtc->dev;
4913 struct intel_encoder *intel_encoder;
4914 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4915 enum pipe pipe = intel_crtc->pipe;
4916 unsigned long mask;
4917 enum transcoder transcoder;
4918
4919 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4920
4921 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4922 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4923 if (intel_crtc->config->pch_pfit.enabled ||
4924 intel_crtc->config->pch_pfit.force_thru)
4925 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4926
4927 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4928 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4929
4930 return mask;
4931 }
4932
4933 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4934 {
4935 struct drm_i915_private *dev_priv = dev->dev_private;
4936 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4937 struct intel_crtc *crtc;
4938
4939 /*
4940 * First get all needed power domains, then put all unneeded, to avoid
4941 * any unnecessary toggling of the power wells.
4942 */
4943 for_each_intel_crtc(dev, crtc) {
4944 enum intel_display_power_domain domain;
4945
4946 if (!crtc->base.state->enable)
4947 continue;
4948
4949 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4950
4951 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4952 intel_display_power_get(dev_priv, domain);
4953 }
4954
4955 if (dev_priv->display.modeset_global_resources)
4956 dev_priv->display.modeset_global_resources(dev);
4957
4958 for_each_intel_crtc(dev, crtc) {
4959 enum intel_display_power_domain domain;
4960
4961 for_each_power_domain(domain, crtc->enabled_power_domains)
4962 intel_display_power_put(dev_priv, domain);
4963
4964 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4965 }
4966
4967 intel_display_set_init_power(dev_priv, false);
4968 }
4969
4970 /* returns HPLL frequency in kHz */
4971 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4972 {
4973 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4974
4975 /* Obtain SKU information */
4976 mutex_lock(&dev_priv->dpio_lock);
4977 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4978 CCK_FUSE_HPLL_FREQ_MASK;
4979 mutex_unlock(&dev_priv->dpio_lock);
4980
4981 return vco_freq[hpll_freq] * 1000;
4982 }
4983
4984 static void vlv_update_cdclk(struct drm_device *dev)
4985 {
4986 struct drm_i915_private *dev_priv = dev->dev_private;
4987
4988 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4989 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4990 dev_priv->vlv_cdclk_freq);
4991
4992 /*
4993 * Program the gmbus_freq based on the cdclk frequency.
4994 * BSpec erroneously claims we should aim for 4MHz, but
4995 * in fact 1MHz is the correct frequency.
4996 */
4997 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
4998 }
4999
5000 /* Adjust CDclk dividers to allow high res or save power if possible */
5001 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5002 {
5003 struct drm_i915_private *dev_priv = dev->dev_private;
5004 u32 val, cmd;
5005
5006 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
5007
5008 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5009 cmd = 2;
5010 else if (cdclk == 266667)
5011 cmd = 1;
5012 else
5013 cmd = 0;
5014
5015 mutex_lock(&dev_priv->rps.hw_lock);
5016 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5017 val &= ~DSPFREQGUAR_MASK;
5018 val |= (cmd << DSPFREQGUAR_SHIFT);
5019 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5020 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5021 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5022 50)) {
5023 DRM_ERROR("timed out waiting for CDclk change\n");
5024 }
5025 mutex_unlock(&dev_priv->rps.hw_lock);
5026
5027 if (cdclk == 400000) {
5028 u32 divider;
5029
5030 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5031
5032 mutex_lock(&dev_priv->dpio_lock);
5033 /* adjust cdclk divider */
5034 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5035 val &= ~DISPLAY_FREQUENCY_VALUES;
5036 val |= divider;
5037 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5038
5039 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5040 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5041 50))
5042 DRM_ERROR("timed out waiting for CDclk change\n");
5043 mutex_unlock(&dev_priv->dpio_lock);
5044 }
5045
5046 mutex_lock(&dev_priv->dpio_lock);
5047 /* adjust self-refresh exit latency value */
5048 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5049 val &= ~0x7f;
5050
5051 /*
5052 * For high bandwidth configs, we set a higher latency in the bunit
5053 * so that the core display fetch happens in time to avoid underruns.
5054 */
5055 if (cdclk == 400000)
5056 val |= 4500 / 250; /* 4.5 usec */
5057 else
5058 val |= 3000 / 250; /* 3.0 usec */
5059 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5060 mutex_unlock(&dev_priv->dpio_lock);
5061
5062 vlv_update_cdclk(dev);
5063 }
5064
5065 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5066 {
5067 struct drm_i915_private *dev_priv = dev->dev_private;
5068 u32 val, cmd;
5069
5070 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
5071
5072 switch (cdclk) {
5073 case 333333:
5074 case 320000:
5075 case 266667:
5076 case 200000:
5077 break;
5078 default:
5079 MISSING_CASE(cdclk);
5080 return;
5081 }
5082
5083 /*
5084 * Specs are full of misinformation, but testing on actual
5085 * hardware has shown that we just need to write the desired
5086 * CCK divider into the Punit register.
5087 */
5088 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5089
5090 mutex_lock(&dev_priv->rps.hw_lock);
5091 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5092 val &= ~DSPFREQGUAR_MASK_CHV;
5093 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5094 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5095 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5096 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5097 50)) {
5098 DRM_ERROR("timed out waiting for CDclk change\n");
5099 }
5100 mutex_unlock(&dev_priv->rps.hw_lock);
5101
5102 vlv_update_cdclk(dev);
5103 }
5104
5105 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5106 int max_pixclk)
5107 {
5108 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5109 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5110
5111 /*
5112 * Really only a few cases to deal with, as only 4 CDclks are supported:
5113 * 200MHz
5114 * 267MHz
5115 * 320/333MHz (depends on HPLL freq)
5116 * 400MHz (VLV only)
5117 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5118 * of the lower bin and adjust if needed.
5119 *
5120 * We seem to get an unstable or solid color picture at 200MHz.
5121 * Not sure what's wrong. For now use 200MHz only when all pipes
5122 * are off.
5123 */
5124 if (!IS_CHERRYVIEW(dev_priv) &&
5125 max_pixclk > freq_320*limit/100)
5126 return 400000;
5127 else if (max_pixclk > 266667*limit/100)
5128 return freq_320;
5129 else if (max_pixclk > 0)
5130 return 266667;
5131 else
5132 return 200000;
5133 }
5134
5135 /* compute the max pixel clock for new configuration */
5136 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
5137 {
5138 struct drm_device *dev = dev_priv->dev;
5139 struct intel_crtc *intel_crtc;
5140 int max_pixclk = 0;
5141
5142 for_each_intel_crtc(dev, intel_crtc) {
5143 if (intel_crtc->new_enabled)
5144 max_pixclk = max(max_pixclk,
5145 intel_crtc->new_config->base.adjusted_mode.crtc_clock);
5146 }
5147
5148 return max_pixclk;
5149 }
5150
5151 static void valleyview_modeset_global_pipes(struct drm_device *dev,
5152 unsigned *prepare_pipes)
5153 {
5154 struct drm_i915_private *dev_priv = dev->dev_private;
5155 struct intel_crtc *intel_crtc;
5156 int max_pixclk = intel_mode_max_pixclk(dev_priv);
5157
5158 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
5159 dev_priv->vlv_cdclk_freq)
5160 return;
5161
5162 /* disable/enable all currently active pipes while we change cdclk */
5163 for_each_intel_crtc(dev, intel_crtc)
5164 if (intel_crtc->base.state->enable)
5165 *prepare_pipes |= (1 << intel_crtc->pipe);
5166 }
5167
5168 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5169 {
5170 unsigned int credits, default_credits;
5171
5172 if (IS_CHERRYVIEW(dev_priv))
5173 default_credits = PFI_CREDIT(12);
5174 else
5175 default_credits = PFI_CREDIT(8);
5176
5177 if (DIV_ROUND_CLOSEST(dev_priv->vlv_cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5178 /* CHV suggested value is 31 or 63 */
5179 if (IS_CHERRYVIEW(dev_priv))
5180 credits = PFI_CREDIT_31;
5181 else
5182 credits = PFI_CREDIT(15);
5183 } else {
5184 credits = default_credits;
5185 }
5186
5187 /*
5188 * WA - write default credits before re-programming
5189 * FIXME: should we also set the resend bit here?
5190 */
5191 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5192 default_credits);
5193
5194 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5195 credits | PFI_CREDIT_RESEND);
5196
5197 /*
5198 * FIXME is this guaranteed to clear
5199 * immediately or should we poll for it?
5200 */
5201 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5202 }
5203
5204 static void valleyview_modeset_global_resources(struct drm_device *dev)
5205 {
5206 struct drm_i915_private *dev_priv = dev->dev_private;
5207 int max_pixclk = intel_mode_max_pixclk(dev_priv);
5208 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5209
5210 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
5211 /*
5212 * FIXME: We can end up here with all power domains off, yet
5213 * with a CDCLK frequency other than the minimum. To account
5214 * for this take the PIPE-A power domain, which covers the HW
5215 * blocks needed for the following programming. This can be
5216 * removed once it's guaranteed that we get here either with
5217 * the minimum CDCLK set, or the required power domains
5218 * enabled.
5219 */
5220 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5221
5222 if (IS_CHERRYVIEW(dev))
5223 cherryview_set_cdclk(dev, req_cdclk);
5224 else
5225 valleyview_set_cdclk(dev, req_cdclk);
5226
5227 vlv_program_pfi_credits(dev_priv);
5228
5229 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5230 }
5231 }
5232
5233 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5234 {
5235 struct drm_device *dev = crtc->dev;
5236 struct drm_i915_private *dev_priv = to_i915(dev);
5237 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5238 struct intel_encoder *encoder;
5239 int pipe = intel_crtc->pipe;
5240 bool is_dsi;
5241
5242 WARN_ON(!crtc->state->enable);
5243
5244 if (intel_crtc->active)
5245 return;
5246
5247 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5248
5249 if (!is_dsi) {
5250 if (IS_CHERRYVIEW(dev))
5251 chv_prepare_pll(intel_crtc, intel_crtc->config);
5252 else
5253 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5254 }
5255
5256 if (intel_crtc->config->has_dp_encoder)
5257 intel_dp_set_m_n(intel_crtc, M1_N1);
5258
5259 intel_set_pipe_timings(intel_crtc);
5260
5261 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5262 struct drm_i915_private *dev_priv = dev->dev_private;
5263
5264 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5265 I915_WRITE(CHV_CANVAS(pipe), 0);
5266 }
5267
5268 i9xx_set_pipeconf(intel_crtc);
5269
5270 intel_crtc->active = true;
5271
5272 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5273
5274 for_each_encoder_on_crtc(dev, crtc, encoder)
5275 if (encoder->pre_pll_enable)
5276 encoder->pre_pll_enable(encoder);
5277
5278 if (!is_dsi) {
5279 if (IS_CHERRYVIEW(dev))
5280 chv_enable_pll(intel_crtc, intel_crtc->config);
5281 else
5282 vlv_enable_pll(intel_crtc, intel_crtc->config);
5283 }
5284
5285 for_each_encoder_on_crtc(dev, crtc, encoder)
5286 if (encoder->pre_enable)
5287 encoder->pre_enable(encoder);
5288
5289 i9xx_pfit_enable(intel_crtc);
5290
5291 intel_crtc_load_lut(crtc);
5292
5293 intel_update_watermarks(crtc);
5294 intel_enable_pipe(intel_crtc);
5295
5296 assert_vblank_disabled(crtc);
5297 drm_crtc_vblank_on(crtc);
5298
5299 for_each_encoder_on_crtc(dev, crtc, encoder)
5300 encoder->enable(encoder);
5301
5302 intel_crtc_enable_planes(crtc);
5303
5304 /* Underruns don't raise interrupts, so check manually. */
5305 i9xx_check_fifo_underruns(dev_priv);
5306 }
5307
5308 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5309 {
5310 struct drm_device *dev = crtc->base.dev;
5311 struct drm_i915_private *dev_priv = dev->dev_private;
5312
5313 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5314 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5315 }
5316
5317 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5318 {
5319 struct drm_device *dev = crtc->dev;
5320 struct drm_i915_private *dev_priv = to_i915(dev);
5321 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5322 struct intel_encoder *encoder;
5323 int pipe = intel_crtc->pipe;
5324
5325 WARN_ON(!crtc->state->enable);
5326
5327 if (intel_crtc->active)
5328 return;
5329
5330 i9xx_set_pll_dividers(intel_crtc);
5331
5332 if (intel_crtc->config->has_dp_encoder)
5333 intel_dp_set_m_n(intel_crtc, M1_N1);
5334
5335 intel_set_pipe_timings(intel_crtc);
5336
5337 i9xx_set_pipeconf(intel_crtc);
5338
5339 intel_crtc->active = true;
5340
5341 if (!IS_GEN2(dev))
5342 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5343
5344 for_each_encoder_on_crtc(dev, crtc, encoder)
5345 if (encoder->pre_enable)
5346 encoder->pre_enable(encoder);
5347
5348 i9xx_enable_pll(intel_crtc);
5349
5350 i9xx_pfit_enable(intel_crtc);
5351
5352 intel_crtc_load_lut(crtc);
5353
5354 intel_update_watermarks(crtc);
5355 intel_enable_pipe(intel_crtc);
5356
5357 assert_vblank_disabled(crtc);
5358 drm_crtc_vblank_on(crtc);
5359
5360 for_each_encoder_on_crtc(dev, crtc, encoder)
5361 encoder->enable(encoder);
5362
5363 intel_crtc_enable_planes(crtc);
5364
5365 /*
5366 * Gen2 reports pipe underruns whenever all planes are disabled.
5367 * So don't enable underrun reporting before at least some planes
5368 * are enabled.
5369 * FIXME: Need to fix the logic to work when we turn off all planes
5370 * but leave the pipe running.
5371 */
5372 if (IS_GEN2(dev))
5373 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5374
5375 /* Underruns don't raise interrupts, so check manually. */
5376 i9xx_check_fifo_underruns(dev_priv);
5377 }
5378
5379 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5380 {
5381 struct drm_device *dev = crtc->base.dev;
5382 struct drm_i915_private *dev_priv = dev->dev_private;
5383
5384 if (!crtc->config->gmch_pfit.control)
5385 return;
5386
5387 assert_pipe_disabled(dev_priv, crtc->pipe);
5388
5389 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5390 I915_READ(PFIT_CONTROL));
5391 I915_WRITE(PFIT_CONTROL, 0);
5392 }
5393
5394 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5395 {
5396 struct drm_device *dev = crtc->dev;
5397 struct drm_i915_private *dev_priv = dev->dev_private;
5398 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5399 struct intel_encoder *encoder;
5400 int pipe = intel_crtc->pipe;
5401
5402 if (!intel_crtc->active)
5403 return;
5404
5405 /*
5406 * Gen2 reports pipe underruns whenever all planes are disabled.
5407 * So diasble underrun reporting before all the planes get disabled.
5408 * FIXME: Need to fix the logic to work when we turn off all planes
5409 * but leave the pipe running.
5410 */
5411 if (IS_GEN2(dev))
5412 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5413
5414 /*
5415 * Vblank time updates from the shadow to live plane control register
5416 * are blocked if the memory self-refresh mode is active at that
5417 * moment. So to make sure the plane gets truly disabled, disable
5418 * first the self-refresh mode. The self-refresh enable bit in turn
5419 * will be checked/applied by the HW only at the next frame start
5420 * event which is after the vblank start event, so we need to have a
5421 * wait-for-vblank between disabling the plane and the pipe.
5422 */
5423 intel_set_memory_cxsr(dev_priv, false);
5424 intel_crtc_disable_planes(crtc);
5425
5426 /*
5427 * On gen2 planes are double buffered but the pipe isn't, so we must
5428 * wait for planes to fully turn off before disabling the pipe.
5429 * We also need to wait on all gmch platforms because of the
5430 * self-refresh mode constraint explained above.
5431 */
5432 intel_wait_for_vblank(dev, pipe);
5433
5434 for_each_encoder_on_crtc(dev, crtc, encoder)
5435 encoder->disable(encoder);
5436
5437 drm_crtc_vblank_off(crtc);
5438 assert_vblank_disabled(crtc);
5439
5440 intel_disable_pipe(intel_crtc);
5441
5442 i9xx_pfit_disable(intel_crtc);
5443
5444 for_each_encoder_on_crtc(dev, crtc, encoder)
5445 if (encoder->post_disable)
5446 encoder->post_disable(encoder);
5447
5448 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5449 if (IS_CHERRYVIEW(dev))
5450 chv_disable_pll(dev_priv, pipe);
5451 else if (IS_VALLEYVIEW(dev))
5452 vlv_disable_pll(dev_priv, pipe);
5453 else
5454 i9xx_disable_pll(intel_crtc);
5455 }
5456
5457 if (!IS_GEN2(dev))
5458 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5459
5460 intel_crtc->active = false;
5461 intel_update_watermarks(crtc);
5462
5463 mutex_lock(&dev->struct_mutex);
5464 intel_fbc_update(dev);
5465 mutex_unlock(&dev->struct_mutex);
5466 }
5467
5468 static void i9xx_crtc_off(struct drm_crtc *crtc)
5469 {
5470 }
5471
5472 /* Master function to enable/disable CRTC and corresponding power wells */
5473 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5474 {
5475 struct drm_device *dev = crtc->dev;
5476 struct drm_i915_private *dev_priv = dev->dev_private;
5477 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5478 enum intel_display_power_domain domain;
5479 unsigned long domains;
5480
5481 if (enable) {
5482 if (!intel_crtc->active) {
5483 domains = get_crtc_power_domains(crtc);
5484 for_each_power_domain(domain, domains)
5485 intel_display_power_get(dev_priv, domain);
5486 intel_crtc->enabled_power_domains = domains;
5487
5488 dev_priv->display.crtc_enable(crtc);
5489 }
5490 } else {
5491 if (intel_crtc->active) {
5492 dev_priv->display.crtc_disable(crtc);
5493
5494 domains = intel_crtc->enabled_power_domains;
5495 for_each_power_domain(domain, domains)
5496 intel_display_power_put(dev_priv, domain);
5497 intel_crtc->enabled_power_domains = 0;
5498 }
5499 }
5500 }
5501
5502 /**
5503 * Sets the power management mode of the pipe and plane.
5504 */
5505 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5506 {
5507 struct drm_device *dev = crtc->dev;
5508 struct intel_encoder *intel_encoder;
5509 bool enable = false;
5510
5511 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5512 enable |= intel_encoder->connectors_active;
5513
5514 intel_crtc_control(crtc, enable);
5515 }
5516
5517 static void intel_crtc_disable(struct drm_crtc *crtc)
5518 {
5519 struct drm_device *dev = crtc->dev;
5520 struct drm_connector *connector;
5521 struct drm_i915_private *dev_priv = dev->dev_private;
5522
5523 /* crtc should still be enabled when we disable it. */
5524 WARN_ON(!crtc->state->enable);
5525
5526 dev_priv->display.crtc_disable(crtc);
5527 dev_priv->display.off(crtc);
5528
5529 crtc->primary->funcs->disable_plane(crtc->primary);
5530
5531 /* Update computed state. */
5532 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5533 if (!connector->encoder || !connector->encoder->crtc)
5534 continue;
5535
5536 if (connector->encoder->crtc != crtc)
5537 continue;
5538
5539 connector->dpms = DRM_MODE_DPMS_OFF;
5540 to_intel_encoder(connector->encoder)->connectors_active = false;
5541 }
5542 }
5543
5544 void intel_encoder_destroy(struct drm_encoder *encoder)
5545 {
5546 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5547
5548 drm_encoder_cleanup(encoder);
5549 kfree(intel_encoder);
5550 }
5551
5552 /* Simple dpms helper for encoders with just one connector, no cloning and only
5553 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5554 * state of the entire output pipe. */
5555 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5556 {
5557 if (mode == DRM_MODE_DPMS_ON) {
5558 encoder->connectors_active = true;
5559
5560 intel_crtc_update_dpms(encoder->base.crtc);
5561 } else {
5562 encoder->connectors_active = false;
5563
5564 intel_crtc_update_dpms(encoder->base.crtc);
5565 }
5566 }
5567
5568 /* Cross check the actual hw state with our own modeset state tracking (and it's
5569 * internal consistency). */
5570 static void intel_connector_check_state(struct intel_connector *connector)
5571 {
5572 if (connector->get_hw_state(connector)) {
5573 struct intel_encoder *encoder = connector->encoder;
5574 struct drm_crtc *crtc;
5575 bool encoder_enabled;
5576 enum pipe pipe;
5577
5578 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5579 connector->base.base.id,
5580 connector->base.name);
5581
5582 /* there is no real hw state for MST connectors */
5583 if (connector->mst_port)
5584 return;
5585
5586 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5587 "wrong connector dpms state\n");
5588 I915_STATE_WARN(connector->base.encoder != &encoder->base,
5589 "active connector not linked to encoder\n");
5590
5591 if (encoder) {
5592 I915_STATE_WARN(!encoder->connectors_active,
5593 "encoder->connectors_active not set\n");
5594
5595 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5596 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
5597 if (I915_STATE_WARN_ON(!encoder->base.crtc))
5598 return;
5599
5600 crtc = encoder->base.crtc;
5601
5602 I915_STATE_WARN(!crtc->state->enable,
5603 "crtc not enabled\n");
5604 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5605 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
5606 "encoder active on the wrong pipe\n");
5607 }
5608 }
5609 }
5610
5611 /* Even simpler default implementation, if there's really no special case to
5612 * consider. */
5613 void intel_connector_dpms(struct drm_connector *connector, int mode)
5614 {
5615 /* All the simple cases only support two dpms states. */
5616 if (mode != DRM_MODE_DPMS_ON)
5617 mode = DRM_MODE_DPMS_OFF;
5618
5619 if (mode == connector->dpms)
5620 return;
5621
5622 connector->dpms = mode;
5623
5624 /* Only need to change hw state when actually enabled */
5625 if (connector->encoder)
5626 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5627
5628 intel_modeset_check_state(connector->dev);
5629 }
5630
5631 /* Simple connector->get_hw_state implementation for encoders that support only
5632 * one connector and no cloning and hence the encoder state determines the state
5633 * of the connector. */
5634 bool intel_connector_get_hw_state(struct intel_connector *connector)
5635 {
5636 enum pipe pipe = 0;
5637 struct intel_encoder *encoder = connector->encoder;
5638
5639 return encoder->get_hw_state(encoder, &pipe);
5640 }
5641
5642 static int pipe_required_fdi_lanes(struct drm_device *dev, enum pipe pipe)
5643 {
5644 struct intel_crtc *crtc =
5645 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5646
5647 if (crtc->base.state->enable &&
5648 crtc->config->has_pch_encoder)
5649 return crtc->config->fdi_lanes;
5650
5651 return 0;
5652 }
5653
5654 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5655 struct intel_crtc_state *pipe_config)
5656 {
5657 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5658 pipe_name(pipe), pipe_config->fdi_lanes);
5659 if (pipe_config->fdi_lanes > 4) {
5660 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5661 pipe_name(pipe), pipe_config->fdi_lanes);
5662 return false;
5663 }
5664
5665 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5666 if (pipe_config->fdi_lanes > 2) {
5667 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5668 pipe_config->fdi_lanes);
5669 return false;
5670 } else {
5671 return true;
5672 }
5673 }
5674
5675 if (INTEL_INFO(dev)->num_pipes == 2)
5676 return true;
5677
5678 /* Ivybridge 3 pipe is really complicated */
5679 switch (pipe) {
5680 case PIPE_A:
5681 return true;
5682 case PIPE_B:
5683 if (pipe_config->fdi_lanes > 2 &&
5684 pipe_required_fdi_lanes(dev, PIPE_C) > 0) {
5685 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5686 pipe_name(pipe), pipe_config->fdi_lanes);
5687 return false;
5688 }
5689 return true;
5690 case PIPE_C:
5691 if (pipe_config->fdi_lanes > 2) {
5692 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
5693 pipe_name(pipe), pipe_config->fdi_lanes);
5694 return false;
5695 }
5696 if (pipe_required_fdi_lanes(dev, PIPE_B) > 2) {
5697 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5698 return false;
5699 }
5700 return true;
5701 default:
5702 BUG();
5703 }
5704 }
5705
5706 #define RETRY 1
5707 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5708 struct intel_crtc_state *pipe_config)
5709 {
5710 struct drm_device *dev = intel_crtc->base.dev;
5711 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5712 int lane, link_bw, fdi_dotclock;
5713 bool setup_ok, needs_recompute = false;
5714
5715 retry:
5716 /* FDI is a binary signal running at ~2.7GHz, encoding
5717 * each output octet as 10 bits. The actual frequency
5718 * is stored as a divider into a 100MHz clock, and the
5719 * mode pixel clock is stored in units of 1KHz.
5720 * Hence the bw of each lane in terms of the mode signal
5721 * is:
5722 */
5723 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5724
5725 fdi_dotclock = adjusted_mode->crtc_clock;
5726
5727 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5728 pipe_config->pipe_bpp);
5729
5730 pipe_config->fdi_lanes = lane;
5731
5732 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5733 link_bw, &pipe_config->fdi_m_n);
5734
5735 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5736 intel_crtc->pipe, pipe_config);
5737 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5738 pipe_config->pipe_bpp -= 2*3;
5739 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5740 pipe_config->pipe_bpp);
5741 needs_recompute = true;
5742 pipe_config->bw_constrained = true;
5743
5744 goto retry;
5745 }
5746
5747 if (needs_recompute)
5748 return RETRY;
5749
5750 return setup_ok ? 0 : -EINVAL;
5751 }
5752
5753 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5754 struct intel_crtc_state *pipe_config)
5755 {
5756 pipe_config->ips_enabled = i915.enable_ips &&
5757 hsw_crtc_supports_ips(crtc) &&
5758 pipe_config->pipe_bpp <= 24;
5759 }
5760
5761 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5762 struct intel_crtc_state *pipe_config)
5763 {
5764 struct drm_device *dev = crtc->base.dev;
5765 struct drm_i915_private *dev_priv = dev->dev_private;
5766 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5767
5768 /* FIXME should check pixel clock limits on all platforms */
5769 if (INTEL_INFO(dev)->gen < 4) {
5770 int clock_limit =
5771 dev_priv->display.get_display_clock_speed(dev);
5772
5773 /*
5774 * Enable pixel doubling when the dot clock
5775 * is > 90% of the (display) core speed.
5776 *
5777 * GDG double wide on either pipe,
5778 * otherwise pipe A only.
5779 */
5780 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5781 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5782 clock_limit *= 2;
5783 pipe_config->double_wide = true;
5784 }
5785
5786 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5787 return -EINVAL;
5788 }
5789
5790 /*
5791 * Pipe horizontal size must be even in:
5792 * - DVO ganged mode
5793 * - LVDS dual channel mode
5794 * - Double wide pipe
5795 */
5796 if ((intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5797 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5798 pipe_config->pipe_src_w &= ~1;
5799
5800 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5801 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5802 */
5803 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5804 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5805 return -EINVAL;
5806
5807 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5808 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5809 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5810 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5811 * for lvds. */
5812 pipe_config->pipe_bpp = 8*3;
5813 }
5814
5815 if (HAS_IPS(dev))
5816 hsw_compute_ips_config(crtc, pipe_config);
5817
5818 if (pipe_config->has_pch_encoder)
5819 return ironlake_fdi_compute_config(crtc, pipe_config);
5820
5821 return 0;
5822 }
5823
5824 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5825 {
5826 struct drm_i915_private *dev_priv = dev->dev_private;
5827 u32 val;
5828 int divider;
5829
5830 if (dev_priv->hpll_freq == 0)
5831 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5832
5833 mutex_lock(&dev_priv->dpio_lock);
5834 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5835 mutex_unlock(&dev_priv->dpio_lock);
5836
5837 divider = val & DISPLAY_FREQUENCY_VALUES;
5838
5839 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5840 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5841 "cdclk change in progress\n");
5842
5843 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
5844 }
5845
5846 static int i945_get_display_clock_speed(struct drm_device *dev)
5847 {
5848 return 400000;
5849 }
5850
5851 static int i915_get_display_clock_speed(struct drm_device *dev)
5852 {
5853 return 333000;
5854 }
5855
5856 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5857 {
5858 return 200000;
5859 }
5860
5861 static int pnv_get_display_clock_speed(struct drm_device *dev)
5862 {
5863 u16 gcfgc = 0;
5864
5865 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5866
5867 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5868 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5869 return 267000;
5870 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5871 return 333000;
5872 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5873 return 444000;
5874 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5875 return 200000;
5876 default:
5877 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5878 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5879 return 133000;
5880 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5881 return 167000;
5882 }
5883 }
5884
5885 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5886 {
5887 u16 gcfgc = 0;
5888
5889 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5890
5891 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5892 return 133000;
5893 else {
5894 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5895 case GC_DISPLAY_CLOCK_333_MHZ:
5896 return 333000;
5897 default:
5898 case GC_DISPLAY_CLOCK_190_200_MHZ:
5899 return 190000;
5900 }
5901 }
5902 }
5903
5904 static int i865_get_display_clock_speed(struct drm_device *dev)
5905 {
5906 return 266000;
5907 }
5908
5909 static int i855_get_display_clock_speed(struct drm_device *dev)
5910 {
5911 u16 hpllcc = 0;
5912 /* Assume that the hardware is in the high speed state. This
5913 * should be the default.
5914 */
5915 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5916 case GC_CLOCK_133_200:
5917 case GC_CLOCK_100_200:
5918 return 200000;
5919 case GC_CLOCK_166_250:
5920 return 250000;
5921 case GC_CLOCK_100_133:
5922 return 133000;
5923 }
5924
5925 /* Shouldn't happen */
5926 return 0;
5927 }
5928
5929 static int i830_get_display_clock_speed(struct drm_device *dev)
5930 {
5931 return 133000;
5932 }
5933
5934 static void
5935 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5936 {
5937 while (*num > DATA_LINK_M_N_MASK ||
5938 *den > DATA_LINK_M_N_MASK) {
5939 *num >>= 1;
5940 *den >>= 1;
5941 }
5942 }
5943
5944 static void compute_m_n(unsigned int m, unsigned int n,
5945 uint32_t *ret_m, uint32_t *ret_n)
5946 {
5947 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5948 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5949 intel_reduce_m_n_ratio(ret_m, ret_n);
5950 }
5951
5952 void
5953 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5954 int pixel_clock, int link_clock,
5955 struct intel_link_m_n *m_n)
5956 {
5957 m_n->tu = 64;
5958
5959 compute_m_n(bits_per_pixel * pixel_clock,
5960 link_clock * nlanes * 8,
5961 &m_n->gmch_m, &m_n->gmch_n);
5962
5963 compute_m_n(pixel_clock, link_clock,
5964 &m_n->link_m, &m_n->link_n);
5965 }
5966
5967 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5968 {
5969 if (i915.panel_use_ssc >= 0)
5970 return i915.panel_use_ssc != 0;
5971 return dev_priv->vbt.lvds_use_ssc
5972 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5973 }
5974
5975 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5976 {
5977 struct drm_device *dev = crtc->base.dev;
5978 struct drm_i915_private *dev_priv = dev->dev_private;
5979 int refclk;
5980
5981 if (IS_VALLEYVIEW(dev)) {
5982 refclk = 100000;
5983 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5984 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5985 refclk = dev_priv->vbt.lvds_ssc_freq;
5986 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5987 } else if (!IS_GEN2(dev)) {
5988 refclk = 96000;
5989 } else {
5990 refclk = 48000;
5991 }
5992
5993 return refclk;
5994 }
5995
5996 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5997 {
5998 return (1 << dpll->n) << 16 | dpll->m2;
5999 }
6000
6001 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6002 {
6003 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6004 }
6005
6006 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6007 struct intel_crtc_state *crtc_state,
6008 intel_clock_t *reduced_clock)
6009 {
6010 struct drm_device *dev = crtc->base.dev;
6011 u32 fp, fp2 = 0;
6012
6013 if (IS_PINEVIEW(dev)) {
6014 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6015 if (reduced_clock)
6016 fp2 = pnv_dpll_compute_fp(reduced_clock);
6017 } else {
6018 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6019 if (reduced_clock)
6020 fp2 = i9xx_dpll_compute_fp(reduced_clock);
6021 }
6022
6023 crtc_state->dpll_hw_state.fp0 = fp;
6024
6025 crtc->lowfreq_avail = false;
6026 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6027 reduced_clock) {
6028 crtc_state->dpll_hw_state.fp1 = fp2;
6029 crtc->lowfreq_avail = true;
6030 } else {
6031 crtc_state->dpll_hw_state.fp1 = fp;
6032 }
6033 }
6034
6035 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6036 pipe)
6037 {
6038 u32 reg_val;
6039
6040 /*
6041 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6042 * and set it to a reasonable value instead.
6043 */
6044 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6045 reg_val &= 0xffffff00;
6046 reg_val |= 0x00000030;
6047 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6048
6049 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6050 reg_val &= 0x8cffffff;
6051 reg_val = 0x8c000000;
6052 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6053
6054 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6055 reg_val &= 0xffffff00;
6056 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6057
6058 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6059 reg_val &= 0x00ffffff;
6060 reg_val |= 0xb0000000;
6061 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6062 }
6063
6064 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6065 struct intel_link_m_n *m_n)
6066 {
6067 struct drm_device *dev = crtc->base.dev;
6068 struct drm_i915_private *dev_priv = dev->dev_private;
6069 int pipe = crtc->pipe;
6070
6071 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6072 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6073 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6074 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6075 }
6076
6077 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6078 struct intel_link_m_n *m_n,
6079 struct intel_link_m_n *m2_n2)
6080 {
6081 struct drm_device *dev = crtc->base.dev;
6082 struct drm_i915_private *dev_priv = dev->dev_private;
6083 int pipe = crtc->pipe;
6084 enum transcoder transcoder = crtc->config->cpu_transcoder;
6085
6086 if (INTEL_INFO(dev)->gen >= 5) {
6087 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6088 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6089 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6090 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6091 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6092 * for gen < 8) and if DRRS is supported (to make sure the
6093 * registers are not unnecessarily accessed).
6094 */
6095 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6096 crtc->config->has_drrs) {
6097 I915_WRITE(PIPE_DATA_M2(transcoder),
6098 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6099 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6100 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6101 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6102 }
6103 } else {
6104 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6105 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6106 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6107 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6108 }
6109 }
6110
6111 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6112 {
6113 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6114
6115 if (m_n == M1_N1) {
6116 dp_m_n = &crtc->config->dp_m_n;
6117 dp_m2_n2 = &crtc->config->dp_m2_n2;
6118 } else if (m_n == M2_N2) {
6119
6120 /*
6121 * M2_N2 registers are not supported. Hence m2_n2 divider value
6122 * needs to be programmed into M1_N1.
6123 */
6124 dp_m_n = &crtc->config->dp_m2_n2;
6125 } else {
6126 DRM_ERROR("Unsupported divider value\n");
6127 return;
6128 }
6129
6130 if (crtc->config->has_pch_encoder)
6131 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6132 else
6133 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6134 }
6135
6136 static void vlv_update_pll(struct intel_crtc *crtc,
6137 struct intel_crtc_state *pipe_config)
6138 {
6139 u32 dpll, dpll_md;
6140
6141 /*
6142 * Enable DPIO clock input. We should never disable the reference
6143 * clock for pipe B, since VGA hotplug / manual detection depends
6144 * on it.
6145 */
6146 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6147 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6148 /* We should never disable this, set it here for state tracking */
6149 if (crtc->pipe == PIPE_B)
6150 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6151 dpll |= DPLL_VCO_ENABLE;
6152 pipe_config->dpll_hw_state.dpll = dpll;
6153
6154 dpll_md = (pipe_config->pixel_multiplier - 1)
6155 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6156 pipe_config->dpll_hw_state.dpll_md = dpll_md;
6157 }
6158
6159 static void vlv_prepare_pll(struct intel_crtc *crtc,
6160 const struct intel_crtc_state *pipe_config)
6161 {
6162 struct drm_device *dev = crtc->base.dev;
6163 struct drm_i915_private *dev_priv = dev->dev_private;
6164 int pipe = crtc->pipe;
6165 u32 mdiv;
6166 u32 bestn, bestm1, bestm2, bestp1, bestp2;
6167 u32 coreclk, reg_val;
6168
6169 mutex_lock(&dev_priv->dpio_lock);
6170
6171 bestn = pipe_config->dpll.n;
6172 bestm1 = pipe_config->dpll.m1;
6173 bestm2 = pipe_config->dpll.m2;
6174 bestp1 = pipe_config->dpll.p1;
6175 bestp2 = pipe_config->dpll.p2;
6176
6177 /* See eDP HDMI DPIO driver vbios notes doc */
6178
6179 /* PLL B needs special handling */
6180 if (pipe == PIPE_B)
6181 vlv_pllb_recal_opamp(dev_priv, pipe);
6182
6183 /* Set up Tx target for periodic Rcomp update */
6184 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6185
6186 /* Disable target IRef on PLL */
6187 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6188 reg_val &= 0x00ffffff;
6189 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6190
6191 /* Disable fast lock */
6192 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6193
6194 /* Set idtafcrecal before PLL is enabled */
6195 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6196 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6197 mdiv |= ((bestn << DPIO_N_SHIFT));
6198 mdiv |= (1 << DPIO_K_SHIFT);
6199
6200 /*
6201 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6202 * but we don't support that).
6203 * Note: don't use the DAC post divider as it seems unstable.
6204 */
6205 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6206 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6207
6208 mdiv |= DPIO_ENABLE_CALIBRATION;
6209 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6210
6211 /* Set HBR and RBR LPF coefficients */
6212 if (pipe_config->port_clock == 162000 ||
6213 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6214 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
6215 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6216 0x009f0003);
6217 else
6218 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6219 0x00d0000f);
6220
6221 if (pipe_config->has_dp_encoder) {
6222 /* Use SSC source */
6223 if (pipe == PIPE_A)
6224 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6225 0x0df40000);
6226 else
6227 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6228 0x0df70000);
6229 } else { /* HDMI or VGA */
6230 /* Use bend source */
6231 if (pipe == PIPE_A)
6232 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6233 0x0df70000);
6234 else
6235 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6236 0x0df40000);
6237 }
6238
6239 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6240 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6241 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6242 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
6243 coreclk |= 0x01000000;
6244 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6245
6246 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6247 mutex_unlock(&dev_priv->dpio_lock);
6248 }
6249
6250 static void chv_update_pll(struct intel_crtc *crtc,
6251 struct intel_crtc_state *pipe_config)
6252 {
6253 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
6254 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6255 DPLL_VCO_ENABLE;
6256 if (crtc->pipe != PIPE_A)
6257 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6258
6259 pipe_config->dpll_hw_state.dpll_md =
6260 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6261 }
6262
6263 static void chv_prepare_pll(struct intel_crtc *crtc,
6264 const struct intel_crtc_state *pipe_config)
6265 {
6266 struct drm_device *dev = crtc->base.dev;
6267 struct drm_i915_private *dev_priv = dev->dev_private;
6268 int pipe = crtc->pipe;
6269 int dpll_reg = DPLL(crtc->pipe);
6270 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6271 u32 loopfilter, tribuf_calcntr;
6272 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6273 u32 dpio_val;
6274 int vco;
6275
6276 bestn = pipe_config->dpll.n;
6277 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6278 bestm1 = pipe_config->dpll.m1;
6279 bestm2 = pipe_config->dpll.m2 >> 22;
6280 bestp1 = pipe_config->dpll.p1;
6281 bestp2 = pipe_config->dpll.p2;
6282 vco = pipe_config->dpll.vco;
6283 dpio_val = 0;
6284 loopfilter = 0;
6285
6286 /*
6287 * Enable Refclk and SSC
6288 */
6289 I915_WRITE(dpll_reg,
6290 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6291
6292 mutex_lock(&dev_priv->dpio_lock);
6293
6294 /* p1 and p2 divider */
6295 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6296 5 << DPIO_CHV_S1_DIV_SHIFT |
6297 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6298 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6299 1 << DPIO_CHV_K_DIV_SHIFT);
6300
6301 /* Feedback post-divider - m2 */
6302 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6303
6304 /* Feedback refclk divider - n and m1 */
6305 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6306 DPIO_CHV_M1_DIV_BY_2 |
6307 1 << DPIO_CHV_N_DIV_SHIFT);
6308
6309 /* M2 fraction division */
6310 if (bestm2_frac)
6311 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6312
6313 /* M2 fraction division enable */
6314 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6315 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6316 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6317 if (bestm2_frac)
6318 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6319 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6320
6321 /* Program digital lock detect threshold */
6322 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6323 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6324 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6325 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6326 if (!bestm2_frac)
6327 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6328 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6329
6330 /* Loop filter */
6331 if (vco == 5400000) {
6332 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6333 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6334 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6335 tribuf_calcntr = 0x9;
6336 } else if (vco <= 6200000) {
6337 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6338 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6339 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6340 tribuf_calcntr = 0x9;
6341 } else if (vco <= 6480000) {
6342 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6343 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6344 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6345 tribuf_calcntr = 0x8;
6346 } else {
6347 /* Not supported. Apply the same limits as in the max case */
6348 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6349 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6350 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6351 tribuf_calcntr = 0;
6352 }
6353 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6354
6355 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6356 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6357 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6358 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6359
6360 /* AFC Recal */
6361 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6362 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6363 DPIO_AFC_RECAL);
6364
6365 mutex_unlock(&dev_priv->dpio_lock);
6366 }
6367
6368 /**
6369 * vlv_force_pll_on - forcibly enable just the PLL
6370 * @dev_priv: i915 private structure
6371 * @pipe: pipe PLL to enable
6372 * @dpll: PLL configuration
6373 *
6374 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6375 * in cases where we need the PLL enabled even when @pipe is not going to
6376 * be enabled.
6377 */
6378 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6379 const struct dpll *dpll)
6380 {
6381 struct intel_crtc *crtc =
6382 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6383 struct intel_crtc_state pipe_config = {
6384 .pixel_multiplier = 1,
6385 .dpll = *dpll,
6386 };
6387
6388 if (IS_CHERRYVIEW(dev)) {
6389 chv_update_pll(crtc, &pipe_config);
6390 chv_prepare_pll(crtc, &pipe_config);
6391 chv_enable_pll(crtc, &pipe_config);
6392 } else {
6393 vlv_update_pll(crtc, &pipe_config);
6394 vlv_prepare_pll(crtc, &pipe_config);
6395 vlv_enable_pll(crtc, &pipe_config);
6396 }
6397 }
6398
6399 /**
6400 * vlv_force_pll_off - forcibly disable just the PLL
6401 * @dev_priv: i915 private structure
6402 * @pipe: pipe PLL to disable
6403 *
6404 * Disable the PLL for @pipe. To be used in cases where we need
6405 * the PLL enabled even when @pipe is not going to be enabled.
6406 */
6407 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6408 {
6409 if (IS_CHERRYVIEW(dev))
6410 chv_disable_pll(to_i915(dev), pipe);
6411 else
6412 vlv_disable_pll(to_i915(dev), pipe);
6413 }
6414
6415 static void i9xx_update_pll(struct intel_crtc *crtc,
6416 struct intel_crtc_state *crtc_state,
6417 intel_clock_t *reduced_clock,
6418 int num_connectors)
6419 {
6420 struct drm_device *dev = crtc->base.dev;
6421 struct drm_i915_private *dev_priv = dev->dev_private;
6422 u32 dpll;
6423 bool is_sdvo;
6424 struct dpll *clock = &crtc_state->dpll;
6425
6426 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6427
6428 is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6429 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6430
6431 dpll = DPLL_VGA_MODE_DIS;
6432
6433 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6434 dpll |= DPLLB_MODE_LVDS;
6435 else
6436 dpll |= DPLLB_MODE_DAC_SERIAL;
6437
6438 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6439 dpll |= (crtc_state->pixel_multiplier - 1)
6440 << SDVO_MULTIPLIER_SHIFT_HIRES;
6441 }
6442
6443 if (is_sdvo)
6444 dpll |= DPLL_SDVO_HIGH_SPEED;
6445
6446 if (crtc_state->has_dp_encoder)
6447 dpll |= DPLL_SDVO_HIGH_SPEED;
6448
6449 /* compute bitmask from p1 value */
6450 if (IS_PINEVIEW(dev))
6451 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6452 else {
6453 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6454 if (IS_G4X(dev) && reduced_clock)
6455 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6456 }
6457 switch (clock->p2) {
6458 case 5:
6459 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6460 break;
6461 case 7:
6462 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6463 break;
6464 case 10:
6465 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6466 break;
6467 case 14:
6468 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6469 break;
6470 }
6471 if (INTEL_INFO(dev)->gen >= 4)
6472 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6473
6474 if (crtc_state->sdvo_tv_clock)
6475 dpll |= PLL_REF_INPUT_TVCLKINBC;
6476 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6477 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6478 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6479 else
6480 dpll |= PLL_REF_INPUT_DREFCLK;
6481
6482 dpll |= DPLL_VCO_ENABLE;
6483 crtc_state->dpll_hw_state.dpll = dpll;
6484
6485 if (INTEL_INFO(dev)->gen >= 4) {
6486 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6487 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6488 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6489 }
6490 }
6491
6492 static void i8xx_update_pll(struct intel_crtc *crtc,
6493 struct intel_crtc_state *crtc_state,
6494 intel_clock_t *reduced_clock,
6495 int num_connectors)
6496 {
6497 struct drm_device *dev = crtc->base.dev;
6498 struct drm_i915_private *dev_priv = dev->dev_private;
6499 u32 dpll;
6500 struct dpll *clock = &crtc_state->dpll;
6501
6502 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6503
6504 dpll = DPLL_VGA_MODE_DIS;
6505
6506 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6507 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6508 } else {
6509 if (clock->p1 == 2)
6510 dpll |= PLL_P1_DIVIDE_BY_TWO;
6511 else
6512 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6513 if (clock->p2 == 4)
6514 dpll |= PLL_P2_DIVIDE_BY_4;
6515 }
6516
6517 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6518 dpll |= DPLL_DVO_2X_MODE;
6519
6520 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6521 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6522 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6523 else
6524 dpll |= PLL_REF_INPUT_DREFCLK;
6525
6526 dpll |= DPLL_VCO_ENABLE;
6527 crtc_state->dpll_hw_state.dpll = dpll;
6528 }
6529
6530 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6531 {
6532 struct drm_device *dev = intel_crtc->base.dev;
6533 struct drm_i915_private *dev_priv = dev->dev_private;
6534 enum pipe pipe = intel_crtc->pipe;
6535 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6536 struct drm_display_mode *adjusted_mode =
6537 &intel_crtc->config->base.adjusted_mode;
6538 uint32_t crtc_vtotal, crtc_vblank_end;
6539 int vsyncshift = 0;
6540
6541 /* We need to be careful not to changed the adjusted mode, for otherwise
6542 * the hw state checker will get angry at the mismatch. */
6543 crtc_vtotal = adjusted_mode->crtc_vtotal;
6544 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6545
6546 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6547 /* the chip adds 2 halflines automatically */
6548 crtc_vtotal -= 1;
6549 crtc_vblank_end -= 1;
6550
6551 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6552 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6553 else
6554 vsyncshift = adjusted_mode->crtc_hsync_start -
6555 adjusted_mode->crtc_htotal / 2;
6556 if (vsyncshift < 0)
6557 vsyncshift += adjusted_mode->crtc_htotal;
6558 }
6559
6560 if (INTEL_INFO(dev)->gen > 3)
6561 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6562
6563 I915_WRITE(HTOTAL(cpu_transcoder),
6564 (adjusted_mode->crtc_hdisplay - 1) |
6565 ((adjusted_mode->crtc_htotal - 1) << 16));
6566 I915_WRITE(HBLANK(cpu_transcoder),
6567 (adjusted_mode->crtc_hblank_start - 1) |
6568 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6569 I915_WRITE(HSYNC(cpu_transcoder),
6570 (adjusted_mode->crtc_hsync_start - 1) |
6571 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6572
6573 I915_WRITE(VTOTAL(cpu_transcoder),
6574 (adjusted_mode->crtc_vdisplay - 1) |
6575 ((crtc_vtotal - 1) << 16));
6576 I915_WRITE(VBLANK(cpu_transcoder),
6577 (adjusted_mode->crtc_vblank_start - 1) |
6578 ((crtc_vblank_end - 1) << 16));
6579 I915_WRITE(VSYNC(cpu_transcoder),
6580 (adjusted_mode->crtc_vsync_start - 1) |
6581 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6582
6583 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6584 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6585 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6586 * bits. */
6587 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6588 (pipe == PIPE_B || pipe == PIPE_C))
6589 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6590
6591 /* pipesrc controls the size that is scaled from, which should
6592 * always be the user's requested size.
6593 */
6594 I915_WRITE(PIPESRC(pipe),
6595 ((intel_crtc->config->pipe_src_w - 1) << 16) |
6596 (intel_crtc->config->pipe_src_h - 1));
6597 }
6598
6599 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6600 struct intel_crtc_state *pipe_config)
6601 {
6602 struct drm_device *dev = crtc->base.dev;
6603 struct drm_i915_private *dev_priv = dev->dev_private;
6604 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6605 uint32_t tmp;
6606
6607 tmp = I915_READ(HTOTAL(cpu_transcoder));
6608 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6609 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6610 tmp = I915_READ(HBLANK(cpu_transcoder));
6611 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6612 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6613 tmp = I915_READ(HSYNC(cpu_transcoder));
6614 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6615 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6616
6617 tmp = I915_READ(VTOTAL(cpu_transcoder));
6618 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6619 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6620 tmp = I915_READ(VBLANK(cpu_transcoder));
6621 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6622 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6623 tmp = I915_READ(VSYNC(cpu_transcoder));
6624 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6625 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6626
6627 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6628 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6629 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6630 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6631 }
6632
6633 tmp = I915_READ(PIPESRC(crtc->pipe));
6634 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6635 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6636
6637 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6638 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
6639 }
6640
6641 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6642 struct intel_crtc_state *pipe_config)
6643 {
6644 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6645 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6646 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
6647 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
6648
6649 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
6650 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
6651 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
6652 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
6653
6654 mode->flags = pipe_config->base.adjusted_mode.flags;
6655
6656 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
6657 mode->flags |= pipe_config->base.adjusted_mode.flags;
6658 }
6659
6660 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6661 {
6662 struct drm_device *dev = intel_crtc->base.dev;
6663 struct drm_i915_private *dev_priv = dev->dev_private;
6664 uint32_t pipeconf;
6665
6666 pipeconf = 0;
6667
6668 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6669 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6670 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6671
6672 if (intel_crtc->config->double_wide)
6673 pipeconf |= PIPECONF_DOUBLE_WIDE;
6674
6675 /* only g4x and later have fancy bpc/dither controls */
6676 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6677 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6678 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
6679 pipeconf |= PIPECONF_DITHER_EN |
6680 PIPECONF_DITHER_TYPE_SP;
6681
6682 switch (intel_crtc->config->pipe_bpp) {
6683 case 18:
6684 pipeconf |= PIPECONF_6BPC;
6685 break;
6686 case 24:
6687 pipeconf |= PIPECONF_8BPC;
6688 break;
6689 case 30:
6690 pipeconf |= PIPECONF_10BPC;
6691 break;
6692 default:
6693 /* Case prevented by intel_choose_pipe_bpp_dither. */
6694 BUG();
6695 }
6696 }
6697
6698 if (HAS_PIPE_CXSR(dev)) {
6699 if (intel_crtc->lowfreq_avail) {
6700 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6701 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6702 } else {
6703 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6704 }
6705 }
6706
6707 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6708 if (INTEL_INFO(dev)->gen < 4 ||
6709 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6710 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6711 else
6712 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6713 } else
6714 pipeconf |= PIPECONF_PROGRESSIVE;
6715
6716 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
6717 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6718
6719 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6720 POSTING_READ(PIPECONF(intel_crtc->pipe));
6721 }
6722
6723 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
6724 struct intel_crtc_state *crtc_state)
6725 {
6726 struct drm_device *dev = crtc->base.dev;
6727 struct drm_i915_private *dev_priv = dev->dev_private;
6728 int refclk, num_connectors = 0;
6729 intel_clock_t clock, reduced_clock;
6730 bool ok, has_reduced_clock = false;
6731 bool is_lvds = false, is_dsi = false;
6732 struct intel_encoder *encoder;
6733 const intel_limit_t *limit;
6734
6735 for_each_intel_encoder(dev, encoder) {
6736 if (encoder->new_crtc != crtc)
6737 continue;
6738
6739 switch (encoder->type) {
6740 case INTEL_OUTPUT_LVDS:
6741 is_lvds = true;
6742 break;
6743 case INTEL_OUTPUT_DSI:
6744 is_dsi = true;
6745 break;
6746 default:
6747 break;
6748 }
6749
6750 num_connectors++;
6751 }
6752
6753 if (is_dsi)
6754 return 0;
6755
6756 if (!crtc_state->clock_set) {
6757 refclk = i9xx_get_refclk(crtc, num_connectors);
6758
6759 /*
6760 * Returns a set of divisors for the desired target clock with
6761 * the given refclk, or FALSE. The returned values represent
6762 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6763 * 2) / p1 / p2.
6764 */
6765 limit = intel_limit(crtc, refclk);
6766 ok = dev_priv->display.find_dpll(limit, crtc,
6767 crtc_state->port_clock,
6768 refclk, NULL, &clock);
6769 if (!ok) {
6770 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6771 return -EINVAL;
6772 }
6773
6774 if (is_lvds && dev_priv->lvds_downclock_avail) {
6775 /*
6776 * Ensure we match the reduced clock's P to the target
6777 * clock. If the clocks don't match, we can't switch
6778 * the display clock by using the FP0/FP1. In such case
6779 * we will disable the LVDS downclock feature.
6780 */
6781 has_reduced_clock =
6782 dev_priv->display.find_dpll(limit, crtc,
6783 dev_priv->lvds_downclock,
6784 refclk, &clock,
6785 &reduced_clock);
6786 }
6787 /* Compat-code for transition, will disappear. */
6788 crtc_state->dpll.n = clock.n;
6789 crtc_state->dpll.m1 = clock.m1;
6790 crtc_state->dpll.m2 = clock.m2;
6791 crtc_state->dpll.p1 = clock.p1;
6792 crtc_state->dpll.p2 = clock.p2;
6793 }
6794
6795 if (IS_GEN2(dev)) {
6796 i8xx_update_pll(crtc, crtc_state,
6797 has_reduced_clock ? &reduced_clock : NULL,
6798 num_connectors);
6799 } else if (IS_CHERRYVIEW(dev)) {
6800 chv_update_pll(crtc, crtc_state);
6801 } else if (IS_VALLEYVIEW(dev)) {
6802 vlv_update_pll(crtc, crtc_state);
6803 } else {
6804 i9xx_update_pll(crtc, crtc_state,
6805 has_reduced_clock ? &reduced_clock : NULL,
6806 num_connectors);
6807 }
6808
6809 return 0;
6810 }
6811
6812 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6813 struct intel_crtc_state *pipe_config)
6814 {
6815 struct drm_device *dev = crtc->base.dev;
6816 struct drm_i915_private *dev_priv = dev->dev_private;
6817 uint32_t tmp;
6818
6819 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6820 return;
6821
6822 tmp = I915_READ(PFIT_CONTROL);
6823 if (!(tmp & PFIT_ENABLE))
6824 return;
6825
6826 /* Check whether the pfit is attached to our pipe. */
6827 if (INTEL_INFO(dev)->gen < 4) {
6828 if (crtc->pipe != PIPE_B)
6829 return;
6830 } else {
6831 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6832 return;
6833 }
6834
6835 pipe_config->gmch_pfit.control = tmp;
6836 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6837 if (INTEL_INFO(dev)->gen < 5)
6838 pipe_config->gmch_pfit.lvds_border_bits =
6839 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6840 }
6841
6842 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6843 struct intel_crtc_state *pipe_config)
6844 {
6845 struct drm_device *dev = crtc->base.dev;
6846 struct drm_i915_private *dev_priv = dev->dev_private;
6847 int pipe = pipe_config->cpu_transcoder;
6848 intel_clock_t clock;
6849 u32 mdiv;
6850 int refclk = 100000;
6851
6852 /* In case of MIPI DPLL will not even be used */
6853 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6854 return;
6855
6856 mutex_lock(&dev_priv->dpio_lock);
6857 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6858 mutex_unlock(&dev_priv->dpio_lock);
6859
6860 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6861 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6862 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6863 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6864 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6865
6866 vlv_clock(refclk, &clock);
6867
6868 /* clock.dot is the fast clock */
6869 pipe_config->port_clock = clock.dot / 5;
6870 }
6871
6872 static void
6873 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
6874 struct intel_initial_plane_config *plane_config)
6875 {
6876 struct drm_device *dev = crtc->base.dev;
6877 struct drm_i915_private *dev_priv = dev->dev_private;
6878 u32 val, base, offset;
6879 int pipe = crtc->pipe, plane = crtc->plane;
6880 int fourcc, pixel_format;
6881 unsigned int aligned_height;
6882 struct drm_framebuffer *fb;
6883 struct intel_framebuffer *intel_fb;
6884
6885 val = I915_READ(DSPCNTR(plane));
6886 if (!(val & DISPLAY_PLANE_ENABLE))
6887 return;
6888
6889 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6890 if (!intel_fb) {
6891 DRM_DEBUG_KMS("failed to alloc fb\n");
6892 return;
6893 }
6894
6895 fb = &intel_fb->base;
6896
6897 if (INTEL_INFO(dev)->gen >= 4) {
6898 if (val & DISPPLANE_TILED) {
6899 plane_config->tiling = I915_TILING_X;
6900 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
6901 }
6902 }
6903
6904 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6905 fourcc = i9xx_format_to_fourcc(pixel_format);
6906 fb->pixel_format = fourcc;
6907 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
6908
6909 if (INTEL_INFO(dev)->gen >= 4) {
6910 if (plane_config->tiling)
6911 offset = I915_READ(DSPTILEOFF(plane));
6912 else
6913 offset = I915_READ(DSPLINOFF(plane));
6914 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6915 } else {
6916 base = I915_READ(DSPADDR(plane));
6917 }
6918 plane_config->base = base;
6919
6920 val = I915_READ(PIPESRC(pipe));
6921 fb->width = ((val >> 16) & 0xfff) + 1;
6922 fb->height = ((val >> 0) & 0xfff) + 1;
6923
6924 val = I915_READ(DSPSTRIDE(pipe));
6925 fb->pitches[0] = val & 0xffffffc0;
6926
6927 aligned_height = intel_fb_align_height(dev, fb->height,
6928 fb->pixel_format,
6929 fb->modifier[0]);
6930
6931 plane_config->size = fb->pitches[0] * aligned_height;
6932
6933 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6934 pipe_name(pipe), plane, fb->width, fb->height,
6935 fb->bits_per_pixel, base, fb->pitches[0],
6936 plane_config->size);
6937
6938 plane_config->fb = intel_fb;
6939 }
6940
6941 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6942 struct intel_crtc_state *pipe_config)
6943 {
6944 struct drm_device *dev = crtc->base.dev;
6945 struct drm_i915_private *dev_priv = dev->dev_private;
6946 int pipe = pipe_config->cpu_transcoder;
6947 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6948 intel_clock_t clock;
6949 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6950 int refclk = 100000;
6951
6952 mutex_lock(&dev_priv->dpio_lock);
6953 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6954 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6955 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6956 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6957 mutex_unlock(&dev_priv->dpio_lock);
6958
6959 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6960 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6961 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6962 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6963 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6964
6965 chv_clock(refclk, &clock);
6966
6967 /* clock.dot is the fast clock */
6968 pipe_config->port_clock = clock.dot / 5;
6969 }
6970
6971 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6972 struct intel_crtc_state *pipe_config)
6973 {
6974 struct drm_device *dev = crtc->base.dev;
6975 struct drm_i915_private *dev_priv = dev->dev_private;
6976 uint32_t tmp;
6977
6978 if (!intel_display_power_is_enabled(dev_priv,
6979 POWER_DOMAIN_PIPE(crtc->pipe)))
6980 return false;
6981
6982 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6983 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6984
6985 tmp = I915_READ(PIPECONF(crtc->pipe));
6986 if (!(tmp & PIPECONF_ENABLE))
6987 return false;
6988
6989 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6990 switch (tmp & PIPECONF_BPC_MASK) {
6991 case PIPECONF_6BPC:
6992 pipe_config->pipe_bpp = 18;
6993 break;
6994 case PIPECONF_8BPC:
6995 pipe_config->pipe_bpp = 24;
6996 break;
6997 case PIPECONF_10BPC:
6998 pipe_config->pipe_bpp = 30;
6999 break;
7000 default:
7001 break;
7002 }
7003 }
7004
7005 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
7006 pipe_config->limited_color_range = true;
7007
7008 if (INTEL_INFO(dev)->gen < 4)
7009 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7010
7011 intel_get_pipe_timings(crtc, pipe_config);
7012
7013 i9xx_get_pfit_config(crtc, pipe_config);
7014
7015 if (INTEL_INFO(dev)->gen >= 4) {
7016 tmp = I915_READ(DPLL_MD(crtc->pipe));
7017 pipe_config->pixel_multiplier =
7018 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7019 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7020 pipe_config->dpll_hw_state.dpll_md = tmp;
7021 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7022 tmp = I915_READ(DPLL(crtc->pipe));
7023 pipe_config->pixel_multiplier =
7024 ((tmp & SDVO_MULTIPLIER_MASK)
7025 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7026 } else {
7027 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7028 * port and will be fixed up in the encoder->get_config
7029 * function. */
7030 pipe_config->pixel_multiplier = 1;
7031 }
7032 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7033 if (!IS_VALLEYVIEW(dev)) {
7034 /*
7035 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7036 * on 830. Filter it out here so that we don't
7037 * report errors due to that.
7038 */
7039 if (IS_I830(dev))
7040 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7041
7042 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7043 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7044 } else {
7045 /* Mask out read-only status bits. */
7046 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7047 DPLL_PORTC_READY_MASK |
7048 DPLL_PORTB_READY_MASK);
7049 }
7050
7051 if (IS_CHERRYVIEW(dev))
7052 chv_crtc_clock_get(crtc, pipe_config);
7053 else if (IS_VALLEYVIEW(dev))
7054 vlv_crtc_clock_get(crtc, pipe_config);
7055 else
7056 i9xx_crtc_clock_get(crtc, pipe_config);
7057
7058 return true;
7059 }
7060
7061 static void ironlake_init_pch_refclk(struct drm_device *dev)
7062 {
7063 struct drm_i915_private *dev_priv = dev->dev_private;
7064 struct intel_encoder *encoder;
7065 u32 val, final;
7066 bool has_lvds = false;
7067 bool has_cpu_edp = false;
7068 bool has_panel = false;
7069 bool has_ck505 = false;
7070 bool can_ssc = false;
7071
7072 /* We need to take the global config into account */
7073 for_each_intel_encoder(dev, encoder) {
7074 switch (encoder->type) {
7075 case INTEL_OUTPUT_LVDS:
7076 has_panel = true;
7077 has_lvds = true;
7078 break;
7079 case INTEL_OUTPUT_EDP:
7080 has_panel = true;
7081 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7082 has_cpu_edp = true;
7083 break;
7084 default:
7085 break;
7086 }
7087 }
7088
7089 if (HAS_PCH_IBX(dev)) {
7090 has_ck505 = dev_priv->vbt.display_clock_mode;
7091 can_ssc = has_ck505;
7092 } else {
7093 has_ck505 = false;
7094 can_ssc = true;
7095 }
7096
7097 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
7098 has_panel, has_lvds, has_ck505);
7099
7100 /* Ironlake: try to setup display ref clock before DPLL
7101 * enabling. This is only under driver's control after
7102 * PCH B stepping, previous chipset stepping should be
7103 * ignoring this setting.
7104 */
7105 val = I915_READ(PCH_DREF_CONTROL);
7106
7107 /* As we must carefully and slowly disable/enable each source in turn,
7108 * compute the final state we want first and check if we need to
7109 * make any changes at all.
7110 */
7111 final = val;
7112 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7113 if (has_ck505)
7114 final |= DREF_NONSPREAD_CK505_ENABLE;
7115 else
7116 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7117
7118 final &= ~DREF_SSC_SOURCE_MASK;
7119 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7120 final &= ~DREF_SSC1_ENABLE;
7121
7122 if (has_panel) {
7123 final |= DREF_SSC_SOURCE_ENABLE;
7124
7125 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7126 final |= DREF_SSC1_ENABLE;
7127
7128 if (has_cpu_edp) {
7129 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7130 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7131 else
7132 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7133 } else
7134 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7135 } else {
7136 final |= DREF_SSC_SOURCE_DISABLE;
7137 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7138 }
7139
7140 if (final == val)
7141 return;
7142
7143 /* Always enable nonspread source */
7144 val &= ~DREF_NONSPREAD_SOURCE_MASK;
7145
7146 if (has_ck505)
7147 val |= DREF_NONSPREAD_CK505_ENABLE;
7148 else
7149 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7150
7151 if (has_panel) {
7152 val &= ~DREF_SSC_SOURCE_MASK;
7153 val |= DREF_SSC_SOURCE_ENABLE;
7154
7155 /* SSC must be turned on before enabling the CPU output */
7156 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7157 DRM_DEBUG_KMS("Using SSC on panel\n");
7158 val |= DREF_SSC1_ENABLE;
7159 } else
7160 val &= ~DREF_SSC1_ENABLE;
7161
7162 /* Get SSC going before enabling the outputs */
7163 I915_WRITE(PCH_DREF_CONTROL, val);
7164 POSTING_READ(PCH_DREF_CONTROL);
7165 udelay(200);
7166
7167 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7168
7169 /* Enable CPU source on CPU attached eDP */
7170 if (has_cpu_edp) {
7171 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7172 DRM_DEBUG_KMS("Using SSC on eDP\n");
7173 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7174 } else
7175 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7176 } else
7177 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7178
7179 I915_WRITE(PCH_DREF_CONTROL, val);
7180 POSTING_READ(PCH_DREF_CONTROL);
7181 udelay(200);
7182 } else {
7183 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7184
7185 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7186
7187 /* Turn off CPU output */
7188 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7189
7190 I915_WRITE(PCH_DREF_CONTROL, val);
7191 POSTING_READ(PCH_DREF_CONTROL);
7192 udelay(200);
7193
7194 /* Turn off the SSC source */
7195 val &= ~DREF_SSC_SOURCE_MASK;
7196 val |= DREF_SSC_SOURCE_DISABLE;
7197
7198 /* Turn off SSC1 */
7199 val &= ~DREF_SSC1_ENABLE;
7200
7201 I915_WRITE(PCH_DREF_CONTROL, val);
7202 POSTING_READ(PCH_DREF_CONTROL);
7203 udelay(200);
7204 }
7205
7206 BUG_ON(val != final);
7207 }
7208
7209 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7210 {
7211 uint32_t tmp;
7212
7213 tmp = I915_READ(SOUTH_CHICKEN2);
7214 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7215 I915_WRITE(SOUTH_CHICKEN2, tmp);
7216
7217 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7218 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7219 DRM_ERROR("FDI mPHY reset assert timeout\n");
7220
7221 tmp = I915_READ(SOUTH_CHICKEN2);
7222 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7223 I915_WRITE(SOUTH_CHICKEN2, tmp);
7224
7225 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7226 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7227 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7228 }
7229
7230 /* WaMPhyProgramming:hsw */
7231 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7232 {
7233 uint32_t tmp;
7234
7235 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7236 tmp &= ~(0xFF << 24);
7237 tmp |= (0x12 << 24);
7238 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7239
7240 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7241 tmp |= (1 << 11);
7242 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7243
7244 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7245 tmp |= (1 << 11);
7246 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7247
7248 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7249 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7250 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7251
7252 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7253 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7254 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7255
7256 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7257 tmp &= ~(7 << 13);
7258 tmp |= (5 << 13);
7259 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7260
7261 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7262 tmp &= ~(7 << 13);
7263 tmp |= (5 << 13);
7264 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7265
7266 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7267 tmp &= ~0xFF;
7268 tmp |= 0x1C;
7269 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7270
7271 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7272 tmp &= ~0xFF;
7273 tmp |= 0x1C;
7274 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7275
7276 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7277 tmp &= ~(0xFF << 16);
7278 tmp |= (0x1C << 16);
7279 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7280
7281 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7282 tmp &= ~(0xFF << 16);
7283 tmp |= (0x1C << 16);
7284 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7285
7286 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7287 tmp |= (1 << 27);
7288 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7289
7290 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7291 tmp |= (1 << 27);
7292 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7293
7294 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7295 tmp &= ~(0xF << 28);
7296 tmp |= (4 << 28);
7297 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7298
7299 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7300 tmp &= ~(0xF << 28);
7301 tmp |= (4 << 28);
7302 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7303 }
7304
7305 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7306 * Programming" based on the parameters passed:
7307 * - Sequence to enable CLKOUT_DP
7308 * - Sequence to enable CLKOUT_DP without spread
7309 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7310 */
7311 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
7312 bool with_fdi)
7313 {
7314 struct drm_i915_private *dev_priv = dev->dev_private;
7315 uint32_t reg, tmp;
7316
7317 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7318 with_spread = true;
7319 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
7320 with_fdi, "LP PCH doesn't have FDI\n"))
7321 with_fdi = false;
7322
7323 mutex_lock(&dev_priv->dpio_lock);
7324
7325 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7326 tmp &= ~SBI_SSCCTL_DISABLE;
7327 tmp |= SBI_SSCCTL_PATHALT;
7328 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7329
7330 udelay(24);
7331
7332 if (with_spread) {
7333 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7334 tmp &= ~SBI_SSCCTL_PATHALT;
7335 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7336
7337 if (with_fdi) {
7338 lpt_reset_fdi_mphy(dev_priv);
7339 lpt_program_fdi_mphy(dev_priv);
7340 }
7341 }
7342
7343 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7344 SBI_GEN0 : SBI_DBUFF0;
7345 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7346 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7347 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7348
7349 mutex_unlock(&dev_priv->dpio_lock);
7350 }
7351
7352 /* Sequence to disable CLKOUT_DP */
7353 static void lpt_disable_clkout_dp(struct drm_device *dev)
7354 {
7355 struct drm_i915_private *dev_priv = dev->dev_private;
7356 uint32_t reg, tmp;
7357
7358 mutex_lock(&dev_priv->dpio_lock);
7359
7360 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7361 SBI_GEN0 : SBI_DBUFF0;
7362 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7363 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7364 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7365
7366 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7367 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7368 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7369 tmp |= SBI_SSCCTL_PATHALT;
7370 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7371 udelay(32);
7372 }
7373 tmp |= SBI_SSCCTL_DISABLE;
7374 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7375 }
7376
7377 mutex_unlock(&dev_priv->dpio_lock);
7378 }
7379
7380 static void lpt_init_pch_refclk(struct drm_device *dev)
7381 {
7382 struct intel_encoder *encoder;
7383 bool has_vga = false;
7384
7385 for_each_intel_encoder(dev, encoder) {
7386 switch (encoder->type) {
7387 case INTEL_OUTPUT_ANALOG:
7388 has_vga = true;
7389 break;
7390 default:
7391 break;
7392 }
7393 }
7394
7395 if (has_vga)
7396 lpt_enable_clkout_dp(dev, true, true);
7397 else
7398 lpt_disable_clkout_dp(dev);
7399 }
7400
7401 /*
7402 * Initialize reference clocks when the driver loads
7403 */
7404 void intel_init_pch_refclk(struct drm_device *dev)
7405 {
7406 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7407 ironlake_init_pch_refclk(dev);
7408 else if (HAS_PCH_LPT(dev))
7409 lpt_init_pch_refclk(dev);
7410 }
7411
7412 static int ironlake_get_refclk(struct drm_crtc *crtc)
7413 {
7414 struct drm_device *dev = crtc->dev;
7415 struct drm_i915_private *dev_priv = dev->dev_private;
7416 struct intel_encoder *encoder;
7417 int num_connectors = 0;
7418 bool is_lvds = false;
7419
7420 for_each_intel_encoder(dev, encoder) {
7421 if (encoder->new_crtc != to_intel_crtc(crtc))
7422 continue;
7423
7424 switch (encoder->type) {
7425 case INTEL_OUTPUT_LVDS:
7426 is_lvds = true;
7427 break;
7428 default:
7429 break;
7430 }
7431 num_connectors++;
7432 }
7433
7434 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7435 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7436 dev_priv->vbt.lvds_ssc_freq);
7437 return dev_priv->vbt.lvds_ssc_freq;
7438 }
7439
7440 return 120000;
7441 }
7442
7443 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7444 {
7445 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7446 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7447 int pipe = intel_crtc->pipe;
7448 uint32_t val;
7449
7450 val = 0;
7451
7452 switch (intel_crtc->config->pipe_bpp) {
7453 case 18:
7454 val |= PIPECONF_6BPC;
7455 break;
7456 case 24:
7457 val |= PIPECONF_8BPC;
7458 break;
7459 case 30:
7460 val |= PIPECONF_10BPC;
7461 break;
7462 case 36:
7463 val |= PIPECONF_12BPC;
7464 break;
7465 default:
7466 /* Case prevented by intel_choose_pipe_bpp_dither. */
7467 BUG();
7468 }
7469
7470 if (intel_crtc->config->dither)
7471 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7472
7473 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7474 val |= PIPECONF_INTERLACED_ILK;
7475 else
7476 val |= PIPECONF_PROGRESSIVE;
7477
7478 if (intel_crtc->config->limited_color_range)
7479 val |= PIPECONF_COLOR_RANGE_SELECT;
7480
7481 I915_WRITE(PIPECONF(pipe), val);
7482 POSTING_READ(PIPECONF(pipe));
7483 }
7484
7485 /*
7486 * Set up the pipe CSC unit.
7487 *
7488 * Currently only full range RGB to limited range RGB conversion
7489 * is supported, but eventually this should handle various
7490 * RGB<->YCbCr scenarios as well.
7491 */
7492 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7493 {
7494 struct drm_device *dev = crtc->dev;
7495 struct drm_i915_private *dev_priv = dev->dev_private;
7496 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7497 int pipe = intel_crtc->pipe;
7498 uint16_t coeff = 0x7800; /* 1.0 */
7499
7500 /*
7501 * TODO: Check what kind of values actually come out of the pipe
7502 * with these coeff/postoff values and adjust to get the best
7503 * accuracy. Perhaps we even need to take the bpc value into
7504 * consideration.
7505 */
7506
7507 if (intel_crtc->config->limited_color_range)
7508 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7509
7510 /*
7511 * GY/GU and RY/RU should be the other way around according
7512 * to BSpec, but reality doesn't agree. Just set them up in
7513 * a way that results in the correct picture.
7514 */
7515 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7516 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7517
7518 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7519 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7520
7521 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7522 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7523
7524 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7525 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7526 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7527
7528 if (INTEL_INFO(dev)->gen > 6) {
7529 uint16_t postoff = 0;
7530
7531 if (intel_crtc->config->limited_color_range)
7532 postoff = (16 * (1 << 12) / 255) & 0x1fff;
7533
7534 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7535 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7536 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7537
7538 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7539 } else {
7540 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7541
7542 if (intel_crtc->config->limited_color_range)
7543 mode |= CSC_BLACK_SCREEN_OFFSET;
7544
7545 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7546 }
7547 }
7548
7549 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7550 {
7551 struct drm_device *dev = crtc->dev;
7552 struct drm_i915_private *dev_priv = dev->dev_private;
7553 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7554 enum pipe pipe = intel_crtc->pipe;
7555 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7556 uint32_t val;
7557
7558 val = 0;
7559
7560 if (IS_HASWELL(dev) && intel_crtc->config->dither)
7561 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7562
7563 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7564 val |= PIPECONF_INTERLACED_ILK;
7565 else
7566 val |= PIPECONF_PROGRESSIVE;
7567
7568 I915_WRITE(PIPECONF(cpu_transcoder), val);
7569 POSTING_READ(PIPECONF(cpu_transcoder));
7570
7571 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7572 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7573
7574 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7575 val = 0;
7576
7577 switch (intel_crtc->config->pipe_bpp) {
7578 case 18:
7579 val |= PIPEMISC_DITHER_6_BPC;
7580 break;
7581 case 24:
7582 val |= PIPEMISC_DITHER_8_BPC;
7583 break;
7584 case 30:
7585 val |= PIPEMISC_DITHER_10_BPC;
7586 break;
7587 case 36:
7588 val |= PIPEMISC_DITHER_12_BPC;
7589 break;
7590 default:
7591 /* Case prevented by pipe_config_set_bpp. */
7592 BUG();
7593 }
7594
7595 if (intel_crtc->config->dither)
7596 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7597
7598 I915_WRITE(PIPEMISC(pipe), val);
7599 }
7600 }
7601
7602 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7603 struct intel_crtc_state *crtc_state,
7604 intel_clock_t *clock,
7605 bool *has_reduced_clock,
7606 intel_clock_t *reduced_clock)
7607 {
7608 struct drm_device *dev = crtc->dev;
7609 struct drm_i915_private *dev_priv = dev->dev_private;
7610 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7611 int refclk;
7612 const intel_limit_t *limit;
7613 bool ret, is_lvds = false;
7614
7615 is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
7616
7617 refclk = ironlake_get_refclk(crtc);
7618
7619 /*
7620 * Returns a set of divisors for the desired target clock with the given
7621 * refclk, or FALSE. The returned values represent the clock equation:
7622 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7623 */
7624 limit = intel_limit(intel_crtc, refclk);
7625 ret = dev_priv->display.find_dpll(limit, intel_crtc,
7626 crtc_state->port_clock,
7627 refclk, NULL, clock);
7628 if (!ret)
7629 return false;
7630
7631 if (is_lvds && dev_priv->lvds_downclock_avail) {
7632 /*
7633 * Ensure we match the reduced clock's P to the target clock.
7634 * If the clocks don't match, we can't switch the display clock
7635 * by using the FP0/FP1. In such case we will disable the LVDS
7636 * downclock feature.
7637 */
7638 *has_reduced_clock =
7639 dev_priv->display.find_dpll(limit, intel_crtc,
7640 dev_priv->lvds_downclock,
7641 refclk, clock,
7642 reduced_clock);
7643 }
7644
7645 return true;
7646 }
7647
7648 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7649 {
7650 /*
7651 * Account for spread spectrum to avoid
7652 * oversubscribing the link. Max center spread
7653 * is 2.5%; use 5% for safety's sake.
7654 */
7655 u32 bps = target_clock * bpp * 21 / 20;
7656 return DIV_ROUND_UP(bps, link_bw * 8);
7657 }
7658
7659 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7660 {
7661 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7662 }
7663
7664 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7665 struct intel_crtc_state *crtc_state,
7666 u32 *fp,
7667 intel_clock_t *reduced_clock, u32 *fp2)
7668 {
7669 struct drm_crtc *crtc = &intel_crtc->base;
7670 struct drm_device *dev = crtc->dev;
7671 struct drm_i915_private *dev_priv = dev->dev_private;
7672 struct intel_encoder *intel_encoder;
7673 uint32_t dpll;
7674 int factor, num_connectors = 0;
7675 bool is_lvds = false, is_sdvo = false;
7676
7677 for_each_intel_encoder(dev, intel_encoder) {
7678 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7679 continue;
7680
7681 switch (intel_encoder->type) {
7682 case INTEL_OUTPUT_LVDS:
7683 is_lvds = true;
7684 break;
7685 case INTEL_OUTPUT_SDVO:
7686 case INTEL_OUTPUT_HDMI:
7687 is_sdvo = true;
7688 break;
7689 default:
7690 break;
7691 }
7692
7693 num_connectors++;
7694 }
7695
7696 /* Enable autotuning of the PLL clock (if permissible) */
7697 factor = 21;
7698 if (is_lvds) {
7699 if ((intel_panel_use_ssc(dev_priv) &&
7700 dev_priv->vbt.lvds_ssc_freq == 100000) ||
7701 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7702 factor = 25;
7703 } else if (crtc_state->sdvo_tv_clock)
7704 factor = 20;
7705
7706 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7707 *fp |= FP_CB_TUNE;
7708
7709 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7710 *fp2 |= FP_CB_TUNE;
7711
7712 dpll = 0;
7713
7714 if (is_lvds)
7715 dpll |= DPLLB_MODE_LVDS;
7716 else
7717 dpll |= DPLLB_MODE_DAC_SERIAL;
7718
7719 dpll |= (crtc_state->pixel_multiplier - 1)
7720 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7721
7722 if (is_sdvo)
7723 dpll |= DPLL_SDVO_HIGH_SPEED;
7724 if (crtc_state->has_dp_encoder)
7725 dpll |= DPLL_SDVO_HIGH_SPEED;
7726
7727 /* compute bitmask from p1 value */
7728 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7729 /* also FPA1 */
7730 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7731
7732 switch (crtc_state->dpll.p2) {
7733 case 5:
7734 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7735 break;
7736 case 7:
7737 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7738 break;
7739 case 10:
7740 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7741 break;
7742 case 14:
7743 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7744 break;
7745 }
7746
7747 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7748 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7749 else
7750 dpll |= PLL_REF_INPUT_DREFCLK;
7751
7752 return dpll | DPLL_VCO_ENABLE;
7753 }
7754
7755 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
7756 struct intel_crtc_state *crtc_state)
7757 {
7758 struct drm_device *dev = crtc->base.dev;
7759 intel_clock_t clock, reduced_clock;
7760 u32 dpll = 0, fp = 0, fp2 = 0;
7761 bool ok, has_reduced_clock = false;
7762 bool is_lvds = false;
7763 struct intel_shared_dpll *pll;
7764
7765 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7766
7767 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7768 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7769
7770 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
7771 &has_reduced_clock, &reduced_clock);
7772 if (!ok && !crtc_state->clock_set) {
7773 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7774 return -EINVAL;
7775 }
7776 /* Compat-code for transition, will disappear. */
7777 if (!crtc_state->clock_set) {
7778 crtc_state->dpll.n = clock.n;
7779 crtc_state->dpll.m1 = clock.m1;
7780 crtc_state->dpll.m2 = clock.m2;
7781 crtc_state->dpll.p1 = clock.p1;
7782 crtc_state->dpll.p2 = clock.p2;
7783 }
7784
7785 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7786 if (crtc_state->has_pch_encoder) {
7787 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7788 if (has_reduced_clock)
7789 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7790
7791 dpll = ironlake_compute_dpll(crtc, crtc_state,
7792 &fp, &reduced_clock,
7793 has_reduced_clock ? &fp2 : NULL);
7794
7795 crtc_state->dpll_hw_state.dpll = dpll;
7796 crtc_state->dpll_hw_state.fp0 = fp;
7797 if (has_reduced_clock)
7798 crtc_state->dpll_hw_state.fp1 = fp2;
7799 else
7800 crtc_state->dpll_hw_state.fp1 = fp;
7801
7802 pll = intel_get_shared_dpll(crtc, crtc_state);
7803 if (pll == NULL) {
7804 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7805 pipe_name(crtc->pipe));
7806 return -EINVAL;
7807 }
7808 }
7809
7810 if (is_lvds && has_reduced_clock)
7811 crtc->lowfreq_avail = true;
7812 else
7813 crtc->lowfreq_avail = false;
7814
7815 return 0;
7816 }
7817
7818 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7819 struct intel_link_m_n *m_n)
7820 {
7821 struct drm_device *dev = crtc->base.dev;
7822 struct drm_i915_private *dev_priv = dev->dev_private;
7823 enum pipe pipe = crtc->pipe;
7824
7825 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7826 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7827 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7828 & ~TU_SIZE_MASK;
7829 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7830 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7831 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7832 }
7833
7834 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7835 enum transcoder transcoder,
7836 struct intel_link_m_n *m_n,
7837 struct intel_link_m_n *m2_n2)
7838 {
7839 struct drm_device *dev = crtc->base.dev;
7840 struct drm_i915_private *dev_priv = dev->dev_private;
7841 enum pipe pipe = crtc->pipe;
7842
7843 if (INTEL_INFO(dev)->gen >= 5) {
7844 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7845 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7846 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7847 & ~TU_SIZE_MASK;
7848 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7849 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7850 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7851 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7852 * gen < 8) and if DRRS is supported (to make sure the
7853 * registers are not unnecessarily read).
7854 */
7855 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7856 crtc->config->has_drrs) {
7857 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7858 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7859 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7860 & ~TU_SIZE_MASK;
7861 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7862 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7863 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7864 }
7865 } else {
7866 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7867 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7868 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7869 & ~TU_SIZE_MASK;
7870 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7871 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7872 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7873 }
7874 }
7875
7876 void intel_dp_get_m_n(struct intel_crtc *crtc,
7877 struct intel_crtc_state *pipe_config)
7878 {
7879 if (pipe_config->has_pch_encoder)
7880 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7881 else
7882 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7883 &pipe_config->dp_m_n,
7884 &pipe_config->dp_m2_n2);
7885 }
7886
7887 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7888 struct intel_crtc_state *pipe_config)
7889 {
7890 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7891 &pipe_config->fdi_m_n, NULL);
7892 }
7893
7894 static void skylake_get_pfit_config(struct intel_crtc *crtc,
7895 struct intel_crtc_state *pipe_config)
7896 {
7897 struct drm_device *dev = crtc->base.dev;
7898 struct drm_i915_private *dev_priv = dev->dev_private;
7899 uint32_t tmp;
7900
7901 tmp = I915_READ(PS_CTL(crtc->pipe));
7902
7903 if (tmp & PS_ENABLE) {
7904 pipe_config->pch_pfit.enabled = true;
7905 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
7906 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
7907 }
7908 }
7909
7910 static void
7911 skylake_get_initial_plane_config(struct intel_crtc *crtc,
7912 struct intel_initial_plane_config *plane_config)
7913 {
7914 struct drm_device *dev = crtc->base.dev;
7915 struct drm_i915_private *dev_priv = dev->dev_private;
7916 u32 val, base, offset, stride_mult, tiling;
7917 int pipe = crtc->pipe;
7918 int fourcc, pixel_format;
7919 unsigned int aligned_height;
7920 struct drm_framebuffer *fb;
7921 struct intel_framebuffer *intel_fb;
7922
7923 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7924 if (!intel_fb) {
7925 DRM_DEBUG_KMS("failed to alloc fb\n");
7926 return;
7927 }
7928
7929 fb = &intel_fb->base;
7930
7931 val = I915_READ(PLANE_CTL(pipe, 0));
7932 if (!(val & PLANE_CTL_ENABLE))
7933 goto error;
7934
7935 pixel_format = val & PLANE_CTL_FORMAT_MASK;
7936 fourcc = skl_format_to_fourcc(pixel_format,
7937 val & PLANE_CTL_ORDER_RGBX,
7938 val & PLANE_CTL_ALPHA_MASK);
7939 fb->pixel_format = fourcc;
7940 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7941
7942 tiling = val & PLANE_CTL_TILED_MASK;
7943 switch (tiling) {
7944 case PLANE_CTL_TILED_LINEAR:
7945 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
7946 break;
7947 case PLANE_CTL_TILED_X:
7948 plane_config->tiling = I915_TILING_X;
7949 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7950 break;
7951 case PLANE_CTL_TILED_Y:
7952 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
7953 break;
7954 case PLANE_CTL_TILED_YF:
7955 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
7956 break;
7957 default:
7958 MISSING_CASE(tiling);
7959 goto error;
7960 }
7961
7962 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
7963 plane_config->base = base;
7964
7965 offset = I915_READ(PLANE_OFFSET(pipe, 0));
7966
7967 val = I915_READ(PLANE_SIZE(pipe, 0));
7968 fb->height = ((val >> 16) & 0xfff) + 1;
7969 fb->width = ((val >> 0) & 0x1fff) + 1;
7970
7971 val = I915_READ(PLANE_STRIDE(pipe, 0));
7972 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
7973 fb->pixel_format);
7974 fb->pitches[0] = (val & 0x3ff) * stride_mult;
7975
7976 aligned_height = intel_fb_align_height(dev, fb->height,
7977 fb->pixel_format,
7978 fb->modifier[0]);
7979
7980 plane_config->size = fb->pitches[0] * aligned_height;
7981
7982 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7983 pipe_name(pipe), fb->width, fb->height,
7984 fb->bits_per_pixel, base, fb->pitches[0],
7985 plane_config->size);
7986
7987 plane_config->fb = intel_fb;
7988 return;
7989
7990 error:
7991 kfree(fb);
7992 }
7993
7994 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7995 struct intel_crtc_state *pipe_config)
7996 {
7997 struct drm_device *dev = crtc->base.dev;
7998 struct drm_i915_private *dev_priv = dev->dev_private;
7999 uint32_t tmp;
8000
8001 tmp = I915_READ(PF_CTL(crtc->pipe));
8002
8003 if (tmp & PF_ENABLE) {
8004 pipe_config->pch_pfit.enabled = true;
8005 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8006 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8007
8008 /* We currently do not free assignements of panel fitters on
8009 * ivb/hsw (since we don't use the higher upscaling modes which
8010 * differentiates them) so just WARN about this case for now. */
8011 if (IS_GEN7(dev)) {
8012 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8013 PF_PIPE_SEL_IVB(crtc->pipe));
8014 }
8015 }
8016 }
8017
8018 static void
8019 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8020 struct intel_initial_plane_config *plane_config)
8021 {
8022 struct drm_device *dev = crtc->base.dev;
8023 struct drm_i915_private *dev_priv = dev->dev_private;
8024 u32 val, base, offset;
8025 int pipe = crtc->pipe;
8026 int fourcc, pixel_format;
8027 unsigned int aligned_height;
8028 struct drm_framebuffer *fb;
8029 struct intel_framebuffer *intel_fb;
8030
8031 val = I915_READ(DSPCNTR(pipe));
8032 if (!(val & DISPLAY_PLANE_ENABLE))
8033 return;
8034
8035 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8036 if (!intel_fb) {
8037 DRM_DEBUG_KMS("failed to alloc fb\n");
8038 return;
8039 }
8040
8041 fb = &intel_fb->base;
8042
8043 if (INTEL_INFO(dev)->gen >= 4) {
8044 if (val & DISPPLANE_TILED) {
8045 plane_config->tiling = I915_TILING_X;
8046 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8047 }
8048 }
8049
8050 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8051 fourcc = i9xx_format_to_fourcc(pixel_format);
8052 fb->pixel_format = fourcc;
8053 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8054
8055 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8056 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
8057 offset = I915_READ(DSPOFFSET(pipe));
8058 } else {
8059 if (plane_config->tiling)
8060 offset = I915_READ(DSPTILEOFF(pipe));
8061 else
8062 offset = I915_READ(DSPLINOFF(pipe));
8063 }
8064 plane_config->base = base;
8065
8066 val = I915_READ(PIPESRC(pipe));
8067 fb->width = ((val >> 16) & 0xfff) + 1;
8068 fb->height = ((val >> 0) & 0xfff) + 1;
8069
8070 val = I915_READ(DSPSTRIDE(pipe));
8071 fb->pitches[0] = val & 0xffffffc0;
8072
8073 aligned_height = intel_fb_align_height(dev, fb->height,
8074 fb->pixel_format,
8075 fb->modifier[0]);
8076
8077 plane_config->size = fb->pitches[0] * aligned_height;
8078
8079 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8080 pipe_name(pipe), fb->width, fb->height,
8081 fb->bits_per_pixel, base, fb->pitches[0],
8082 plane_config->size);
8083
8084 plane_config->fb = intel_fb;
8085 }
8086
8087 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8088 struct intel_crtc_state *pipe_config)
8089 {
8090 struct drm_device *dev = crtc->base.dev;
8091 struct drm_i915_private *dev_priv = dev->dev_private;
8092 uint32_t tmp;
8093
8094 if (!intel_display_power_is_enabled(dev_priv,
8095 POWER_DOMAIN_PIPE(crtc->pipe)))
8096 return false;
8097
8098 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8099 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8100
8101 tmp = I915_READ(PIPECONF(crtc->pipe));
8102 if (!(tmp & PIPECONF_ENABLE))
8103 return false;
8104
8105 switch (tmp & PIPECONF_BPC_MASK) {
8106 case PIPECONF_6BPC:
8107 pipe_config->pipe_bpp = 18;
8108 break;
8109 case PIPECONF_8BPC:
8110 pipe_config->pipe_bpp = 24;
8111 break;
8112 case PIPECONF_10BPC:
8113 pipe_config->pipe_bpp = 30;
8114 break;
8115 case PIPECONF_12BPC:
8116 pipe_config->pipe_bpp = 36;
8117 break;
8118 default:
8119 break;
8120 }
8121
8122 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8123 pipe_config->limited_color_range = true;
8124
8125 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8126 struct intel_shared_dpll *pll;
8127
8128 pipe_config->has_pch_encoder = true;
8129
8130 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8131 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8132 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8133
8134 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8135
8136 if (HAS_PCH_IBX(dev_priv->dev)) {
8137 pipe_config->shared_dpll =
8138 (enum intel_dpll_id) crtc->pipe;
8139 } else {
8140 tmp = I915_READ(PCH_DPLL_SEL);
8141 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8142 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
8143 else
8144 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
8145 }
8146
8147 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8148
8149 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8150 &pipe_config->dpll_hw_state));
8151
8152 tmp = pipe_config->dpll_hw_state.dpll;
8153 pipe_config->pixel_multiplier =
8154 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8155 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8156
8157 ironlake_pch_clock_get(crtc, pipe_config);
8158 } else {
8159 pipe_config->pixel_multiplier = 1;
8160 }
8161
8162 intel_get_pipe_timings(crtc, pipe_config);
8163
8164 ironlake_get_pfit_config(crtc, pipe_config);
8165
8166 return true;
8167 }
8168
8169 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8170 {
8171 struct drm_device *dev = dev_priv->dev;
8172 struct intel_crtc *crtc;
8173
8174 for_each_intel_crtc(dev, crtc)
8175 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8176 pipe_name(crtc->pipe));
8177
8178 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8179 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8180 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8181 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8182 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8183 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8184 "CPU PWM1 enabled\n");
8185 if (IS_HASWELL(dev))
8186 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8187 "CPU PWM2 enabled\n");
8188 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8189 "PCH PWM1 enabled\n");
8190 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8191 "Utility pin enabled\n");
8192 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8193
8194 /*
8195 * In theory we can still leave IRQs enabled, as long as only the HPD
8196 * interrupts remain enabled. We used to check for that, but since it's
8197 * gen-specific and since we only disable LCPLL after we fully disable
8198 * the interrupts, the check below should be enough.
8199 */
8200 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8201 }
8202
8203 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8204 {
8205 struct drm_device *dev = dev_priv->dev;
8206
8207 if (IS_HASWELL(dev))
8208 return I915_READ(D_COMP_HSW);
8209 else
8210 return I915_READ(D_COMP_BDW);
8211 }
8212
8213 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8214 {
8215 struct drm_device *dev = dev_priv->dev;
8216
8217 if (IS_HASWELL(dev)) {
8218 mutex_lock(&dev_priv->rps.hw_lock);
8219 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8220 val))
8221 DRM_ERROR("Failed to write to D_COMP\n");
8222 mutex_unlock(&dev_priv->rps.hw_lock);
8223 } else {
8224 I915_WRITE(D_COMP_BDW, val);
8225 POSTING_READ(D_COMP_BDW);
8226 }
8227 }
8228
8229 /*
8230 * This function implements pieces of two sequences from BSpec:
8231 * - Sequence for display software to disable LCPLL
8232 * - Sequence for display software to allow package C8+
8233 * The steps implemented here are just the steps that actually touch the LCPLL
8234 * register. Callers should take care of disabling all the display engine
8235 * functions, doing the mode unset, fixing interrupts, etc.
8236 */
8237 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8238 bool switch_to_fclk, bool allow_power_down)
8239 {
8240 uint32_t val;
8241
8242 assert_can_disable_lcpll(dev_priv);
8243
8244 val = I915_READ(LCPLL_CTL);
8245
8246 if (switch_to_fclk) {
8247 val |= LCPLL_CD_SOURCE_FCLK;
8248 I915_WRITE(LCPLL_CTL, val);
8249
8250 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
8251 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8252 DRM_ERROR("Switching to FCLK failed\n");
8253
8254 val = I915_READ(LCPLL_CTL);
8255 }
8256
8257 val |= LCPLL_PLL_DISABLE;
8258 I915_WRITE(LCPLL_CTL, val);
8259 POSTING_READ(LCPLL_CTL);
8260
8261 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
8262 DRM_ERROR("LCPLL still locked\n");
8263
8264 val = hsw_read_dcomp(dev_priv);
8265 val |= D_COMP_COMP_DISABLE;
8266 hsw_write_dcomp(dev_priv, val);
8267 ndelay(100);
8268
8269 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8270 1))
8271 DRM_ERROR("D_COMP RCOMP still in progress\n");
8272
8273 if (allow_power_down) {
8274 val = I915_READ(LCPLL_CTL);
8275 val |= LCPLL_POWER_DOWN_ALLOW;
8276 I915_WRITE(LCPLL_CTL, val);
8277 POSTING_READ(LCPLL_CTL);
8278 }
8279 }
8280
8281 /*
8282 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8283 * source.
8284 */
8285 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8286 {
8287 uint32_t val;
8288
8289 val = I915_READ(LCPLL_CTL);
8290
8291 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8292 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8293 return;
8294
8295 /*
8296 * Make sure we're not on PC8 state before disabling PC8, otherwise
8297 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8298 */
8299 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8300
8301 if (val & LCPLL_POWER_DOWN_ALLOW) {
8302 val &= ~LCPLL_POWER_DOWN_ALLOW;
8303 I915_WRITE(LCPLL_CTL, val);
8304 POSTING_READ(LCPLL_CTL);
8305 }
8306
8307 val = hsw_read_dcomp(dev_priv);
8308 val |= D_COMP_COMP_FORCE;
8309 val &= ~D_COMP_COMP_DISABLE;
8310 hsw_write_dcomp(dev_priv, val);
8311
8312 val = I915_READ(LCPLL_CTL);
8313 val &= ~LCPLL_PLL_DISABLE;
8314 I915_WRITE(LCPLL_CTL, val);
8315
8316 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
8317 DRM_ERROR("LCPLL not locked yet\n");
8318
8319 if (val & LCPLL_CD_SOURCE_FCLK) {
8320 val = I915_READ(LCPLL_CTL);
8321 val &= ~LCPLL_CD_SOURCE_FCLK;
8322 I915_WRITE(LCPLL_CTL, val);
8323
8324 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
8325 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8326 DRM_ERROR("Switching back to LCPLL failed\n");
8327 }
8328
8329 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8330 }
8331
8332 /*
8333 * Package states C8 and deeper are really deep PC states that can only be
8334 * reached when all the devices on the system allow it, so even if the graphics
8335 * device allows PC8+, it doesn't mean the system will actually get to these
8336 * states. Our driver only allows PC8+ when going into runtime PM.
8337 *
8338 * The requirements for PC8+ are that all the outputs are disabled, the power
8339 * well is disabled and most interrupts are disabled, and these are also
8340 * requirements for runtime PM. When these conditions are met, we manually do
8341 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8342 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8343 * hang the machine.
8344 *
8345 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8346 * the state of some registers, so when we come back from PC8+ we need to
8347 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8348 * need to take care of the registers kept by RC6. Notice that this happens even
8349 * if we don't put the device in PCI D3 state (which is what currently happens
8350 * because of the runtime PM support).
8351 *
8352 * For more, read "Display Sequences for Package C8" on the hardware
8353 * documentation.
8354 */
8355 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8356 {
8357 struct drm_device *dev = dev_priv->dev;
8358 uint32_t val;
8359
8360 DRM_DEBUG_KMS("Enabling package C8+\n");
8361
8362 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8363 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8364 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8365 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8366 }
8367
8368 lpt_disable_clkout_dp(dev);
8369 hsw_disable_lcpll(dev_priv, true, true);
8370 }
8371
8372 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8373 {
8374 struct drm_device *dev = dev_priv->dev;
8375 uint32_t val;
8376
8377 DRM_DEBUG_KMS("Disabling package C8+\n");
8378
8379 hsw_restore_lcpll(dev_priv);
8380 lpt_init_pch_refclk(dev);
8381
8382 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8383 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8384 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8385 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8386 }
8387
8388 intel_prepare_ddi(dev);
8389 }
8390
8391 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8392 struct intel_crtc_state *crtc_state)
8393 {
8394 if (!intel_ddi_pll_select(crtc, crtc_state))
8395 return -EINVAL;
8396
8397 crtc->lowfreq_avail = false;
8398
8399 return 0;
8400 }
8401
8402 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8403 enum port port,
8404 struct intel_crtc_state *pipe_config)
8405 {
8406 u32 temp, dpll_ctl1;
8407
8408 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8409 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
8410
8411 switch (pipe_config->ddi_pll_sel) {
8412 case SKL_DPLL0:
8413 /*
8414 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
8415 * of the shared DPLL framework and thus needs to be read out
8416 * separately
8417 */
8418 dpll_ctl1 = I915_READ(DPLL_CTRL1);
8419 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
8420 break;
8421 case SKL_DPLL1:
8422 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
8423 break;
8424 case SKL_DPLL2:
8425 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
8426 break;
8427 case SKL_DPLL3:
8428 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8429 break;
8430 }
8431 }
8432
8433 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8434 enum port port,
8435 struct intel_crtc_state *pipe_config)
8436 {
8437 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8438
8439 switch (pipe_config->ddi_pll_sel) {
8440 case PORT_CLK_SEL_WRPLL1:
8441 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8442 break;
8443 case PORT_CLK_SEL_WRPLL2:
8444 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8445 break;
8446 }
8447 }
8448
8449 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
8450 struct intel_crtc_state *pipe_config)
8451 {
8452 struct drm_device *dev = crtc->base.dev;
8453 struct drm_i915_private *dev_priv = dev->dev_private;
8454 struct intel_shared_dpll *pll;
8455 enum port port;
8456 uint32_t tmp;
8457
8458 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8459
8460 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8461
8462 if (IS_SKYLAKE(dev))
8463 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8464 else
8465 haswell_get_ddi_pll(dev_priv, port, pipe_config);
8466
8467 if (pipe_config->shared_dpll >= 0) {
8468 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8469
8470 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8471 &pipe_config->dpll_hw_state));
8472 }
8473
8474 /*
8475 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8476 * DDI E. So just check whether this pipe is wired to DDI E and whether
8477 * the PCH transcoder is on.
8478 */
8479 if (INTEL_INFO(dev)->gen < 9 &&
8480 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8481 pipe_config->has_pch_encoder = true;
8482
8483 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8484 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8485 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8486
8487 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8488 }
8489 }
8490
8491 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8492 struct intel_crtc_state *pipe_config)
8493 {
8494 struct drm_device *dev = crtc->base.dev;
8495 struct drm_i915_private *dev_priv = dev->dev_private;
8496 enum intel_display_power_domain pfit_domain;
8497 uint32_t tmp;
8498
8499 if (!intel_display_power_is_enabled(dev_priv,
8500 POWER_DOMAIN_PIPE(crtc->pipe)))
8501 return false;
8502
8503 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8504 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8505
8506 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8507 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8508 enum pipe trans_edp_pipe;
8509 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8510 default:
8511 WARN(1, "unknown pipe linked to edp transcoder\n");
8512 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8513 case TRANS_DDI_EDP_INPUT_A_ON:
8514 trans_edp_pipe = PIPE_A;
8515 break;
8516 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8517 trans_edp_pipe = PIPE_B;
8518 break;
8519 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8520 trans_edp_pipe = PIPE_C;
8521 break;
8522 }
8523
8524 if (trans_edp_pipe == crtc->pipe)
8525 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8526 }
8527
8528 if (!intel_display_power_is_enabled(dev_priv,
8529 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8530 return false;
8531
8532 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8533 if (!(tmp & PIPECONF_ENABLE))
8534 return false;
8535
8536 haswell_get_ddi_port_state(crtc, pipe_config);
8537
8538 intel_get_pipe_timings(crtc, pipe_config);
8539
8540 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8541 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8542 if (IS_SKYLAKE(dev))
8543 skylake_get_pfit_config(crtc, pipe_config);
8544 else
8545 ironlake_get_pfit_config(crtc, pipe_config);
8546 }
8547
8548 if (IS_HASWELL(dev))
8549 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8550 (I915_READ(IPS_CTL) & IPS_ENABLE);
8551
8552 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8553 pipe_config->pixel_multiplier =
8554 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8555 } else {
8556 pipe_config->pixel_multiplier = 1;
8557 }
8558
8559 return true;
8560 }
8561
8562 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8563 {
8564 struct drm_device *dev = crtc->dev;
8565 struct drm_i915_private *dev_priv = dev->dev_private;
8566 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8567 uint32_t cntl = 0, size = 0;
8568
8569 if (base) {
8570 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
8571 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
8572 unsigned int stride = roundup_pow_of_two(width) * 4;
8573
8574 switch (stride) {
8575 default:
8576 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8577 width, stride);
8578 stride = 256;
8579 /* fallthrough */
8580 case 256:
8581 case 512:
8582 case 1024:
8583 case 2048:
8584 break;
8585 }
8586
8587 cntl |= CURSOR_ENABLE |
8588 CURSOR_GAMMA_ENABLE |
8589 CURSOR_FORMAT_ARGB |
8590 CURSOR_STRIDE(stride);
8591
8592 size = (height << 12) | width;
8593 }
8594
8595 if (intel_crtc->cursor_cntl != 0 &&
8596 (intel_crtc->cursor_base != base ||
8597 intel_crtc->cursor_size != size ||
8598 intel_crtc->cursor_cntl != cntl)) {
8599 /* On these chipsets we can only modify the base/size/stride
8600 * whilst the cursor is disabled.
8601 */
8602 I915_WRITE(_CURACNTR, 0);
8603 POSTING_READ(_CURACNTR);
8604 intel_crtc->cursor_cntl = 0;
8605 }
8606
8607 if (intel_crtc->cursor_base != base) {
8608 I915_WRITE(_CURABASE, base);
8609 intel_crtc->cursor_base = base;
8610 }
8611
8612 if (intel_crtc->cursor_size != size) {
8613 I915_WRITE(CURSIZE, size);
8614 intel_crtc->cursor_size = size;
8615 }
8616
8617 if (intel_crtc->cursor_cntl != cntl) {
8618 I915_WRITE(_CURACNTR, cntl);
8619 POSTING_READ(_CURACNTR);
8620 intel_crtc->cursor_cntl = cntl;
8621 }
8622 }
8623
8624 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8625 {
8626 struct drm_device *dev = crtc->dev;
8627 struct drm_i915_private *dev_priv = dev->dev_private;
8628 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8629 int pipe = intel_crtc->pipe;
8630 uint32_t cntl;
8631
8632 cntl = 0;
8633 if (base) {
8634 cntl = MCURSOR_GAMMA_ENABLE;
8635 switch (intel_crtc->base.cursor->state->crtc_w) {
8636 case 64:
8637 cntl |= CURSOR_MODE_64_ARGB_AX;
8638 break;
8639 case 128:
8640 cntl |= CURSOR_MODE_128_ARGB_AX;
8641 break;
8642 case 256:
8643 cntl |= CURSOR_MODE_256_ARGB_AX;
8644 break;
8645 default:
8646 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
8647 return;
8648 }
8649 cntl |= pipe << 28; /* Connect to correct pipe */
8650
8651 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8652 cntl |= CURSOR_PIPE_CSC_ENABLE;
8653 }
8654
8655 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
8656 cntl |= CURSOR_ROTATE_180;
8657
8658 if (intel_crtc->cursor_cntl != cntl) {
8659 I915_WRITE(CURCNTR(pipe), cntl);
8660 POSTING_READ(CURCNTR(pipe));
8661 intel_crtc->cursor_cntl = cntl;
8662 }
8663
8664 /* and commit changes on next vblank */
8665 I915_WRITE(CURBASE(pipe), base);
8666 POSTING_READ(CURBASE(pipe));
8667
8668 intel_crtc->cursor_base = base;
8669 }
8670
8671 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8672 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8673 bool on)
8674 {
8675 struct drm_device *dev = crtc->dev;
8676 struct drm_i915_private *dev_priv = dev->dev_private;
8677 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8678 int pipe = intel_crtc->pipe;
8679 int x = crtc->cursor_x;
8680 int y = crtc->cursor_y;
8681 u32 base = 0, pos = 0;
8682
8683 if (on)
8684 base = intel_crtc->cursor_addr;
8685
8686 if (x >= intel_crtc->config->pipe_src_w)
8687 base = 0;
8688
8689 if (y >= intel_crtc->config->pipe_src_h)
8690 base = 0;
8691
8692 if (x < 0) {
8693 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
8694 base = 0;
8695
8696 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8697 x = -x;
8698 }
8699 pos |= x << CURSOR_X_SHIFT;
8700
8701 if (y < 0) {
8702 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
8703 base = 0;
8704
8705 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8706 y = -y;
8707 }
8708 pos |= y << CURSOR_Y_SHIFT;
8709
8710 if (base == 0 && intel_crtc->cursor_base == 0)
8711 return;
8712
8713 I915_WRITE(CURPOS(pipe), pos);
8714
8715 /* ILK+ do this automagically */
8716 if (HAS_GMCH_DISPLAY(dev) &&
8717 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
8718 base += (intel_crtc->base.cursor->state->crtc_h *
8719 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
8720 }
8721
8722 if (IS_845G(dev) || IS_I865G(dev))
8723 i845_update_cursor(crtc, base);
8724 else
8725 i9xx_update_cursor(crtc, base);
8726 }
8727
8728 static bool cursor_size_ok(struct drm_device *dev,
8729 uint32_t width, uint32_t height)
8730 {
8731 if (width == 0 || height == 0)
8732 return false;
8733
8734 /*
8735 * 845g/865g are special in that they are only limited by
8736 * the width of their cursors, the height is arbitrary up to
8737 * the precision of the register. Everything else requires
8738 * square cursors, limited to a few power-of-two sizes.
8739 */
8740 if (IS_845G(dev) || IS_I865G(dev)) {
8741 if ((width & 63) != 0)
8742 return false;
8743
8744 if (width > (IS_845G(dev) ? 64 : 512))
8745 return false;
8746
8747 if (height > 1023)
8748 return false;
8749 } else {
8750 switch (width | height) {
8751 case 256:
8752 case 128:
8753 if (IS_GEN2(dev))
8754 return false;
8755 case 64:
8756 break;
8757 default:
8758 return false;
8759 }
8760 }
8761
8762 return true;
8763 }
8764
8765 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8766 u16 *blue, uint32_t start, uint32_t size)
8767 {
8768 int end = (start + size > 256) ? 256 : start + size, i;
8769 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8770
8771 for (i = start; i < end; i++) {
8772 intel_crtc->lut_r[i] = red[i] >> 8;
8773 intel_crtc->lut_g[i] = green[i] >> 8;
8774 intel_crtc->lut_b[i] = blue[i] >> 8;
8775 }
8776
8777 intel_crtc_load_lut(crtc);
8778 }
8779
8780 /* VESA 640x480x72Hz mode to set on the pipe */
8781 static struct drm_display_mode load_detect_mode = {
8782 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8783 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8784 };
8785
8786 struct drm_framebuffer *
8787 __intel_framebuffer_create(struct drm_device *dev,
8788 struct drm_mode_fb_cmd2 *mode_cmd,
8789 struct drm_i915_gem_object *obj)
8790 {
8791 struct intel_framebuffer *intel_fb;
8792 int ret;
8793
8794 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8795 if (!intel_fb) {
8796 drm_gem_object_unreference(&obj->base);
8797 return ERR_PTR(-ENOMEM);
8798 }
8799
8800 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8801 if (ret)
8802 goto err;
8803
8804 return &intel_fb->base;
8805 err:
8806 drm_gem_object_unreference(&obj->base);
8807 kfree(intel_fb);
8808
8809 return ERR_PTR(ret);
8810 }
8811
8812 static struct drm_framebuffer *
8813 intel_framebuffer_create(struct drm_device *dev,
8814 struct drm_mode_fb_cmd2 *mode_cmd,
8815 struct drm_i915_gem_object *obj)
8816 {
8817 struct drm_framebuffer *fb;
8818 int ret;
8819
8820 ret = i915_mutex_lock_interruptible(dev);
8821 if (ret)
8822 return ERR_PTR(ret);
8823 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8824 mutex_unlock(&dev->struct_mutex);
8825
8826 return fb;
8827 }
8828
8829 static u32
8830 intel_framebuffer_pitch_for_width(int width, int bpp)
8831 {
8832 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8833 return ALIGN(pitch, 64);
8834 }
8835
8836 static u32
8837 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8838 {
8839 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8840 return PAGE_ALIGN(pitch * mode->vdisplay);
8841 }
8842
8843 static struct drm_framebuffer *
8844 intel_framebuffer_create_for_mode(struct drm_device *dev,
8845 struct drm_display_mode *mode,
8846 int depth, int bpp)
8847 {
8848 struct drm_i915_gem_object *obj;
8849 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8850
8851 obj = i915_gem_alloc_object(dev,
8852 intel_framebuffer_size_for_mode(mode, bpp));
8853 if (obj == NULL)
8854 return ERR_PTR(-ENOMEM);
8855
8856 mode_cmd.width = mode->hdisplay;
8857 mode_cmd.height = mode->vdisplay;
8858 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8859 bpp);
8860 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8861
8862 return intel_framebuffer_create(dev, &mode_cmd, obj);
8863 }
8864
8865 static struct drm_framebuffer *
8866 mode_fits_in_fbdev(struct drm_device *dev,
8867 struct drm_display_mode *mode)
8868 {
8869 #ifdef CONFIG_DRM_I915_FBDEV
8870 struct drm_i915_private *dev_priv = dev->dev_private;
8871 struct drm_i915_gem_object *obj;
8872 struct drm_framebuffer *fb;
8873
8874 if (!dev_priv->fbdev)
8875 return NULL;
8876
8877 if (!dev_priv->fbdev->fb)
8878 return NULL;
8879
8880 obj = dev_priv->fbdev->fb->obj;
8881 BUG_ON(!obj);
8882
8883 fb = &dev_priv->fbdev->fb->base;
8884 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8885 fb->bits_per_pixel))
8886 return NULL;
8887
8888 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8889 return NULL;
8890
8891 return fb;
8892 #else
8893 return NULL;
8894 #endif
8895 }
8896
8897 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8898 struct drm_display_mode *mode,
8899 struct intel_load_detect_pipe *old,
8900 struct drm_modeset_acquire_ctx *ctx)
8901 {
8902 struct intel_crtc *intel_crtc;
8903 struct intel_encoder *intel_encoder =
8904 intel_attached_encoder(connector);
8905 struct drm_crtc *possible_crtc;
8906 struct drm_encoder *encoder = &intel_encoder->base;
8907 struct drm_crtc *crtc = NULL;
8908 struct drm_device *dev = encoder->dev;
8909 struct drm_framebuffer *fb;
8910 struct drm_mode_config *config = &dev->mode_config;
8911 struct drm_atomic_state *state = NULL;
8912 struct drm_connector_state *connector_state;
8913 int ret, i = -1;
8914
8915 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8916 connector->base.id, connector->name,
8917 encoder->base.id, encoder->name);
8918
8919 retry:
8920 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8921 if (ret)
8922 goto fail_unlock;
8923
8924 /*
8925 * Algorithm gets a little messy:
8926 *
8927 * - if the connector already has an assigned crtc, use it (but make
8928 * sure it's on first)
8929 *
8930 * - try to find the first unused crtc that can drive this connector,
8931 * and use that if we find one
8932 */
8933
8934 /* See if we already have a CRTC for this connector */
8935 if (encoder->crtc) {
8936 crtc = encoder->crtc;
8937
8938 ret = drm_modeset_lock(&crtc->mutex, ctx);
8939 if (ret)
8940 goto fail_unlock;
8941 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8942 if (ret)
8943 goto fail_unlock;
8944
8945 old->dpms_mode = connector->dpms;
8946 old->load_detect_temp = false;
8947
8948 /* Make sure the crtc and connector are running */
8949 if (connector->dpms != DRM_MODE_DPMS_ON)
8950 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8951
8952 return true;
8953 }
8954
8955 /* Find an unused one (if possible) */
8956 for_each_crtc(dev, possible_crtc) {
8957 i++;
8958 if (!(encoder->possible_crtcs & (1 << i)))
8959 continue;
8960 if (possible_crtc->state->enable)
8961 continue;
8962 /* This can occur when applying the pipe A quirk on resume. */
8963 if (to_intel_crtc(possible_crtc)->new_enabled)
8964 continue;
8965
8966 crtc = possible_crtc;
8967 break;
8968 }
8969
8970 /*
8971 * If we didn't find an unused CRTC, don't use any.
8972 */
8973 if (!crtc) {
8974 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8975 goto fail_unlock;
8976 }
8977
8978 ret = drm_modeset_lock(&crtc->mutex, ctx);
8979 if (ret)
8980 goto fail_unlock;
8981 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8982 if (ret)
8983 goto fail_unlock;
8984 intel_encoder->new_crtc = to_intel_crtc(crtc);
8985 to_intel_connector(connector)->new_encoder = intel_encoder;
8986
8987 intel_crtc = to_intel_crtc(crtc);
8988 intel_crtc->new_enabled = true;
8989 intel_crtc->new_config = intel_crtc->config;
8990 old->dpms_mode = connector->dpms;
8991 old->load_detect_temp = true;
8992 old->release_fb = NULL;
8993
8994 state = drm_atomic_state_alloc(dev);
8995 if (!state)
8996 return false;
8997
8998 state->acquire_ctx = ctx;
8999
9000 connector_state = drm_atomic_get_connector_state(state, connector);
9001 if (IS_ERR(connector_state)) {
9002 ret = PTR_ERR(connector_state);
9003 goto fail;
9004 }
9005
9006 connector_state->crtc = crtc;
9007 connector_state->best_encoder = &intel_encoder->base;
9008
9009 if (!mode)
9010 mode = &load_detect_mode;
9011
9012 /* We need a framebuffer large enough to accommodate all accesses
9013 * that the plane may generate whilst we perform load detection.
9014 * We can not rely on the fbcon either being present (we get called
9015 * during its initialisation to detect all boot displays, or it may
9016 * not even exist) or that it is large enough to satisfy the
9017 * requested mode.
9018 */
9019 fb = mode_fits_in_fbdev(dev, mode);
9020 if (fb == NULL) {
9021 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9022 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9023 old->release_fb = fb;
9024 } else
9025 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9026 if (IS_ERR(fb)) {
9027 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9028 goto fail;
9029 }
9030
9031 if (intel_set_mode(crtc, mode, 0, 0, fb, state)) {
9032 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9033 if (old->release_fb)
9034 old->release_fb->funcs->destroy(old->release_fb);
9035 goto fail;
9036 }
9037 crtc->primary->crtc = crtc;
9038
9039 /* let the connector get through one full cycle before testing */
9040 intel_wait_for_vblank(dev, intel_crtc->pipe);
9041 return true;
9042
9043 fail:
9044 intel_crtc->new_enabled = crtc->state->enable;
9045 if (intel_crtc->new_enabled)
9046 intel_crtc->new_config = intel_crtc->config;
9047 else
9048 intel_crtc->new_config = NULL;
9049 fail_unlock:
9050 if (state) {
9051 drm_atomic_state_free(state);
9052 state = NULL;
9053 }
9054
9055 if (ret == -EDEADLK) {
9056 drm_modeset_backoff(ctx);
9057 goto retry;
9058 }
9059
9060 return false;
9061 }
9062
9063 void intel_release_load_detect_pipe(struct drm_connector *connector,
9064 struct intel_load_detect_pipe *old,
9065 struct drm_modeset_acquire_ctx *ctx)
9066 {
9067 struct drm_device *dev = connector->dev;
9068 struct intel_encoder *intel_encoder =
9069 intel_attached_encoder(connector);
9070 struct drm_encoder *encoder = &intel_encoder->base;
9071 struct drm_crtc *crtc = encoder->crtc;
9072 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9073 struct drm_atomic_state *state;
9074 struct drm_connector_state *connector_state;
9075
9076 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9077 connector->base.id, connector->name,
9078 encoder->base.id, encoder->name);
9079
9080 if (old->load_detect_temp) {
9081 state = drm_atomic_state_alloc(dev);
9082 if (!state)
9083 goto fail;
9084
9085 state->acquire_ctx = ctx;
9086
9087 connector_state = drm_atomic_get_connector_state(state, connector);
9088 if (IS_ERR(connector_state))
9089 goto fail;
9090
9091 to_intel_connector(connector)->new_encoder = NULL;
9092 intel_encoder->new_crtc = NULL;
9093 intel_crtc->new_enabled = false;
9094 intel_crtc->new_config = NULL;
9095
9096 connector_state->best_encoder = NULL;
9097 connector_state->crtc = NULL;
9098
9099 intel_set_mode(crtc, NULL, 0, 0, NULL, state);
9100
9101 drm_atomic_state_free(state);
9102
9103 if (old->release_fb) {
9104 drm_framebuffer_unregister_private(old->release_fb);
9105 drm_framebuffer_unreference(old->release_fb);
9106 }
9107
9108 return;
9109 }
9110
9111 /* Switch crtc and encoder back off if necessary */
9112 if (old->dpms_mode != DRM_MODE_DPMS_ON)
9113 connector->funcs->dpms(connector, old->dpms_mode);
9114
9115 return;
9116 fail:
9117 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
9118 drm_atomic_state_free(state);
9119 }
9120
9121 static int i9xx_pll_refclk(struct drm_device *dev,
9122 const struct intel_crtc_state *pipe_config)
9123 {
9124 struct drm_i915_private *dev_priv = dev->dev_private;
9125 u32 dpll = pipe_config->dpll_hw_state.dpll;
9126
9127 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
9128 return dev_priv->vbt.lvds_ssc_freq;
9129 else if (HAS_PCH_SPLIT(dev))
9130 return 120000;
9131 else if (!IS_GEN2(dev))
9132 return 96000;
9133 else
9134 return 48000;
9135 }
9136
9137 /* Returns the clock of the currently programmed mode of the given pipe. */
9138 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
9139 struct intel_crtc_state *pipe_config)
9140 {
9141 struct drm_device *dev = crtc->base.dev;
9142 struct drm_i915_private *dev_priv = dev->dev_private;
9143 int pipe = pipe_config->cpu_transcoder;
9144 u32 dpll = pipe_config->dpll_hw_state.dpll;
9145 u32 fp;
9146 intel_clock_t clock;
9147 int refclk = i9xx_pll_refclk(dev, pipe_config);
9148
9149 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
9150 fp = pipe_config->dpll_hw_state.fp0;
9151 else
9152 fp = pipe_config->dpll_hw_state.fp1;
9153
9154 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
9155 if (IS_PINEVIEW(dev)) {
9156 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9157 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
9158 } else {
9159 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9160 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9161 }
9162
9163 if (!IS_GEN2(dev)) {
9164 if (IS_PINEVIEW(dev))
9165 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9166 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
9167 else
9168 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
9169 DPLL_FPA01_P1_POST_DIV_SHIFT);
9170
9171 switch (dpll & DPLL_MODE_MASK) {
9172 case DPLLB_MODE_DAC_SERIAL:
9173 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9174 5 : 10;
9175 break;
9176 case DPLLB_MODE_LVDS:
9177 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9178 7 : 14;
9179 break;
9180 default:
9181 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
9182 "mode\n", (int)(dpll & DPLL_MODE_MASK));
9183 return;
9184 }
9185
9186 if (IS_PINEVIEW(dev))
9187 pineview_clock(refclk, &clock);
9188 else
9189 i9xx_clock(refclk, &clock);
9190 } else {
9191 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
9192 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
9193
9194 if (is_lvds) {
9195 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9196 DPLL_FPA01_P1_POST_DIV_SHIFT);
9197
9198 if (lvds & LVDS_CLKB_POWER_UP)
9199 clock.p2 = 7;
9200 else
9201 clock.p2 = 14;
9202 } else {
9203 if (dpll & PLL_P1_DIVIDE_BY_TWO)
9204 clock.p1 = 2;
9205 else {
9206 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9207 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9208 }
9209 if (dpll & PLL_P2_DIVIDE_BY_4)
9210 clock.p2 = 4;
9211 else
9212 clock.p2 = 2;
9213 }
9214
9215 i9xx_clock(refclk, &clock);
9216 }
9217
9218 /*
9219 * This value includes pixel_multiplier. We will use
9220 * port_clock to compute adjusted_mode.crtc_clock in the
9221 * encoder's get_config() function.
9222 */
9223 pipe_config->port_clock = clock.dot;
9224 }
9225
9226 int intel_dotclock_calculate(int link_freq,
9227 const struct intel_link_m_n *m_n)
9228 {
9229 /*
9230 * The calculation for the data clock is:
9231 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
9232 * But we want to avoid losing precison if possible, so:
9233 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
9234 *
9235 * and the link clock is simpler:
9236 * link_clock = (m * link_clock) / n
9237 */
9238
9239 if (!m_n->link_n)
9240 return 0;
9241
9242 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
9243 }
9244
9245 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
9246 struct intel_crtc_state *pipe_config)
9247 {
9248 struct drm_device *dev = crtc->base.dev;
9249
9250 /* read out port_clock from the DPLL */
9251 i9xx_crtc_clock_get(crtc, pipe_config);
9252
9253 /*
9254 * This value does not include pixel_multiplier.
9255 * We will check that port_clock and adjusted_mode.crtc_clock
9256 * agree once we know their relationship in the encoder's
9257 * get_config() function.
9258 */
9259 pipe_config->base.adjusted_mode.crtc_clock =
9260 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
9261 &pipe_config->fdi_m_n);
9262 }
9263
9264 /** Returns the currently programmed mode of the given pipe. */
9265 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9266 struct drm_crtc *crtc)
9267 {
9268 struct drm_i915_private *dev_priv = dev->dev_private;
9269 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9270 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9271 struct drm_display_mode *mode;
9272 struct intel_crtc_state pipe_config;
9273 int htot = I915_READ(HTOTAL(cpu_transcoder));
9274 int hsync = I915_READ(HSYNC(cpu_transcoder));
9275 int vtot = I915_READ(VTOTAL(cpu_transcoder));
9276 int vsync = I915_READ(VSYNC(cpu_transcoder));
9277 enum pipe pipe = intel_crtc->pipe;
9278
9279 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9280 if (!mode)
9281 return NULL;
9282
9283 /*
9284 * Construct a pipe_config sufficient for getting the clock info
9285 * back out of crtc_clock_get.
9286 *
9287 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9288 * to use a real value here instead.
9289 */
9290 pipe_config.cpu_transcoder = (enum transcoder) pipe;
9291 pipe_config.pixel_multiplier = 1;
9292 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9293 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9294 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
9295 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
9296
9297 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
9298 mode->hdisplay = (htot & 0xffff) + 1;
9299 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9300 mode->hsync_start = (hsync & 0xffff) + 1;
9301 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9302 mode->vdisplay = (vtot & 0xffff) + 1;
9303 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9304 mode->vsync_start = (vsync & 0xffff) + 1;
9305 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9306
9307 drm_mode_set_name(mode);
9308
9309 return mode;
9310 }
9311
9312 static void intel_decrease_pllclock(struct drm_crtc *crtc)
9313 {
9314 struct drm_device *dev = crtc->dev;
9315 struct drm_i915_private *dev_priv = dev->dev_private;
9316 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9317
9318 if (!HAS_GMCH_DISPLAY(dev))
9319 return;
9320
9321 if (!dev_priv->lvds_downclock_avail)
9322 return;
9323
9324 /*
9325 * Since this is called by a timer, we should never get here in
9326 * the manual case.
9327 */
9328 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
9329 int pipe = intel_crtc->pipe;
9330 int dpll_reg = DPLL(pipe);
9331 int dpll;
9332
9333 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9334
9335 assert_panel_unlocked(dev_priv, pipe);
9336
9337 dpll = I915_READ(dpll_reg);
9338 dpll |= DISPLAY_RATE_SELECT_FPA1;
9339 I915_WRITE(dpll_reg, dpll);
9340 intel_wait_for_vblank(dev, pipe);
9341 dpll = I915_READ(dpll_reg);
9342 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
9343 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9344 }
9345
9346 }
9347
9348 void intel_mark_busy(struct drm_device *dev)
9349 {
9350 struct drm_i915_private *dev_priv = dev->dev_private;
9351
9352 if (dev_priv->mm.busy)
9353 return;
9354
9355 intel_runtime_pm_get(dev_priv);
9356 i915_update_gfx_val(dev_priv);
9357 if (INTEL_INFO(dev)->gen >= 6)
9358 gen6_rps_busy(dev_priv);
9359 dev_priv->mm.busy = true;
9360 }
9361
9362 void intel_mark_idle(struct drm_device *dev)
9363 {
9364 struct drm_i915_private *dev_priv = dev->dev_private;
9365 struct drm_crtc *crtc;
9366
9367 if (!dev_priv->mm.busy)
9368 return;
9369
9370 dev_priv->mm.busy = false;
9371
9372 for_each_crtc(dev, crtc) {
9373 if (!crtc->primary->fb)
9374 continue;
9375
9376 intel_decrease_pllclock(crtc);
9377 }
9378
9379 if (INTEL_INFO(dev)->gen >= 6)
9380 gen6_rps_idle(dev->dev_private);
9381
9382 intel_runtime_pm_put(dev_priv);
9383 }
9384
9385 static void intel_crtc_set_state(struct intel_crtc *crtc,
9386 struct intel_crtc_state *crtc_state)
9387 {
9388 kfree(crtc->config);
9389 crtc->config = crtc_state;
9390 crtc->base.state = &crtc_state->base;
9391 }
9392
9393 static void intel_crtc_destroy(struct drm_crtc *crtc)
9394 {
9395 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9396 struct drm_device *dev = crtc->dev;
9397 struct intel_unpin_work *work;
9398
9399 spin_lock_irq(&dev->event_lock);
9400 work = intel_crtc->unpin_work;
9401 intel_crtc->unpin_work = NULL;
9402 spin_unlock_irq(&dev->event_lock);
9403
9404 if (work) {
9405 cancel_work_sync(&work->work);
9406 kfree(work);
9407 }
9408
9409 intel_crtc_set_state(intel_crtc, NULL);
9410 drm_crtc_cleanup(crtc);
9411
9412 kfree(intel_crtc);
9413 }
9414
9415 static void intel_unpin_work_fn(struct work_struct *__work)
9416 {
9417 struct intel_unpin_work *work =
9418 container_of(__work, struct intel_unpin_work, work);
9419 struct drm_device *dev = work->crtc->dev;
9420 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9421
9422 mutex_lock(&dev->struct_mutex);
9423 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
9424 drm_gem_object_unreference(&work->pending_flip_obj->base);
9425
9426 intel_fbc_update(dev);
9427
9428 if (work->flip_queued_req)
9429 i915_gem_request_assign(&work->flip_queued_req, NULL);
9430 mutex_unlock(&dev->struct_mutex);
9431
9432 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9433 drm_framebuffer_unreference(work->old_fb);
9434
9435 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9436 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9437
9438 kfree(work);
9439 }
9440
9441 static void do_intel_finish_page_flip(struct drm_device *dev,
9442 struct drm_crtc *crtc)
9443 {
9444 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9445 struct intel_unpin_work *work;
9446 unsigned long flags;
9447
9448 /* Ignore early vblank irqs */
9449 if (intel_crtc == NULL)
9450 return;
9451
9452 /*
9453 * This is called both by irq handlers and the reset code (to complete
9454 * lost pageflips) so needs the full irqsave spinlocks.
9455 */
9456 spin_lock_irqsave(&dev->event_lock, flags);
9457 work = intel_crtc->unpin_work;
9458
9459 /* Ensure we don't miss a work->pending update ... */
9460 smp_rmb();
9461
9462 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9463 spin_unlock_irqrestore(&dev->event_lock, flags);
9464 return;
9465 }
9466
9467 page_flip_completed(intel_crtc);
9468
9469 spin_unlock_irqrestore(&dev->event_lock, flags);
9470 }
9471
9472 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9473 {
9474 struct drm_i915_private *dev_priv = dev->dev_private;
9475 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9476
9477 do_intel_finish_page_flip(dev, crtc);
9478 }
9479
9480 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9481 {
9482 struct drm_i915_private *dev_priv = dev->dev_private;
9483 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9484
9485 do_intel_finish_page_flip(dev, crtc);
9486 }
9487
9488 /* Is 'a' after or equal to 'b'? */
9489 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9490 {
9491 return !((a - b) & 0x80000000);
9492 }
9493
9494 static bool page_flip_finished(struct intel_crtc *crtc)
9495 {
9496 struct drm_device *dev = crtc->base.dev;
9497 struct drm_i915_private *dev_priv = dev->dev_private;
9498
9499 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
9500 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
9501 return true;
9502
9503 /*
9504 * The relevant registers doen't exist on pre-ctg.
9505 * As the flip done interrupt doesn't trigger for mmio
9506 * flips on gmch platforms, a flip count check isn't
9507 * really needed there. But since ctg has the registers,
9508 * include it in the check anyway.
9509 */
9510 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9511 return true;
9512
9513 /*
9514 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9515 * used the same base address. In that case the mmio flip might
9516 * have completed, but the CS hasn't even executed the flip yet.
9517 *
9518 * A flip count check isn't enough as the CS might have updated
9519 * the base address just after start of vblank, but before we
9520 * managed to process the interrupt. This means we'd complete the
9521 * CS flip too soon.
9522 *
9523 * Combining both checks should get us a good enough result. It may
9524 * still happen that the CS flip has been executed, but has not
9525 * yet actually completed. But in case the base address is the same
9526 * anyway, we don't really care.
9527 */
9528 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9529 crtc->unpin_work->gtt_offset &&
9530 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9531 crtc->unpin_work->flip_count);
9532 }
9533
9534 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9535 {
9536 struct drm_i915_private *dev_priv = dev->dev_private;
9537 struct intel_crtc *intel_crtc =
9538 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9539 unsigned long flags;
9540
9541
9542 /*
9543 * This is called both by irq handlers and the reset code (to complete
9544 * lost pageflips) so needs the full irqsave spinlocks.
9545 *
9546 * NB: An MMIO update of the plane base pointer will also
9547 * generate a page-flip completion irq, i.e. every modeset
9548 * is also accompanied by a spurious intel_prepare_page_flip().
9549 */
9550 spin_lock_irqsave(&dev->event_lock, flags);
9551 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9552 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9553 spin_unlock_irqrestore(&dev->event_lock, flags);
9554 }
9555
9556 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9557 {
9558 /* Ensure that the work item is consistent when activating it ... */
9559 smp_wmb();
9560 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9561 /* and that it is marked active as soon as the irq could fire. */
9562 smp_wmb();
9563 }
9564
9565 static int intel_gen2_queue_flip(struct drm_device *dev,
9566 struct drm_crtc *crtc,
9567 struct drm_framebuffer *fb,
9568 struct drm_i915_gem_object *obj,
9569 struct intel_engine_cs *ring,
9570 uint32_t flags)
9571 {
9572 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9573 u32 flip_mask;
9574 int ret;
9575
9576 ret = intel_ring_begin(ring, 6);
9577 if (ret)
9578 return ret;
9579
9580 /* Can't queue multiple flips, so wait for the previous
9581 * one to finish before executing the next.
9582 */
9583 if (intel_crtc->plane)
9584 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9585 else
9586 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9587 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9588 intel_ring_emit(ring, MI_NOOP);
9589 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9590 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9591 intel_ring_emit(ring, fb->pitches[0]);
9592 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9593 intel_ring_emit(ring, 0); /* aux display base address, unused */
9594
9595 intel_mark_page_flip_active(intel_crtc);
9596 __intel_ring_advance(ring);
9597 return 0;
9598 }
9599
9600 static int intel_gen3_queue_flip(struct drm_device *dev,
9601 struct drm_crtc *crtc,
9602 struct drm_framebuffer *fb,
9603 struct drm_i915_gem_object *obj,
9604 struct intel_engine_cs *ring,
9605 uint32_t flags)
9606 {
9607 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9608 u32 flip_mask;
9609 int ret;
9610
9611 ret = intel_ring_begin(ring, 6);
9612 if (ret)
9613 return ret;
9614
9615 if (intel_crtc->plane)
9616 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9617 else
9618 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9619 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9620 intel_ring_emit(ring, MI_NOOP);
9621 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9622 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9623 intel_ring_emit(ring, fb->pitches[0]);
9624 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9625 intel_ring_emit(ring, MI_NOOP);
9626
9627 intel_mark_page_flip_active(intel_crtc);
9628 __intel_ring_advance(ring);
9629 return 0;
9630 }
9631
9632 static int intel_gen4_queue_flip(struct drm_device *dev,
9633 struct drm_crtc *crtc,
9634 struct drm_framebuffer *fb,
9635 struct drm_i915_gem_object *obj,
9636 struct intel_engine_cs *ring,
9637 uint32_t flags)
9638 {
9639 struct drm_i915_private *dev_priv = dev->dev_private;
9640 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9641 uint32_t pf, pipesrc;
9642 int ret;
9643
9644 ret = intel_ring_begin(ring, 4);
9645 if (ret)
9646 return ret;
9647
9648 /* i965+ uses the linear or tiled offsets from the
9649 * Display Registers (which do not change across a page-flip)
9650 * so we need only reprogram the base address.
9651 */
9652 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9653 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9654 intel_ring_emit(ring, fb->pitches[0]);
9655 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9656 obj->tiling_mode);
9657
9658 /* XXX Enabling the panel-fitter across page-flip is so far
9659 * untested on non-native modes, so ignore it for now.
9660 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9661 */
9662 pf = 0;
9663 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9664 intel_ring_emit(ring, pf | pipesrc);
9665
9666 intel_mark_page_flip_active(intel_crtc);
9667 __intel_ring_advance(ring);
9668 return 0;
9669 }
9670
9671 static int intel_gen6_queue_flip(struct drm_device *dev,
9672 struct drm_crtc *crtc,
9673 struct drm_framebuffer *fb,
9674 struct drm_i915_gem_object *obj,
9675 struct intel_engine_cs *ring,
9676 uint32_t flags)
9677 {
9678 struct drm_i915_private *dev_priv = dev->dev_private;
9679 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9680 uint32_t pf, pipesrc;
9681 int ret;
9682
9683 ret = intel_ring_begin(ring, 4);
9684 if (ret)
9685 return ret;
9686
9687 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9688 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9689 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9690 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9691
9692 /* Contrary to the suggestions in the documentation,
9693 * "Enable Panel Fitter" does not seem to be required when page
9694 * flipping with a non-native mode, and worse causes a normal
9695 * modeset to fail.
9696 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9697 */
9698 pf = 0;
9699 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9700 intel_ring_emit(ring, pf | pipesrc);
9701
9702 intel_mark_page_flip_active(intel_crtc);
9703 __intel_ring_advance(ring);
9704 return 0;
9705 }
9706
9707 static int intel_gen7_queue_flip(struct drm_device *dev,
9708 struct drm_crtc *crtc,
9709 struct drm_framebuffer *fb,
9710 struct drm_i915_gem_object *obj,
9711 struct intel_engine_cs *ring,
9712 uint32_t flags)
9713 {
9714 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9715 uint32_t plane_bit = 0;
9716 int len, ret;
9717
9718 switch (intel_crtc->plane) {
9719 case PLANE_A:
9720 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9721 break;
9722 case PLANE_B:
9723 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9724 break;
9725 case PLANE_C:
9726 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9727 break;
9728 default:
9729 WARN_ONCE(1, "unknown plane in flip command\n");
9730 return -ENODEV;
9731 }
9732
9733 len = 4;
9734 if (ring->id == RCS) {
9735 len += 6;
9736 /*
9737 * On Gen 8, SRM is now taking an extra dword to accommodate
9738 * 48bits addresses, and we need a NOOP for the batch size to
9739 * stay even.
9740 */
9741 if (IS_GEN8(dev))
9742 len += 2;
9743 }
9744
9745 /*
9746 * BSpec MI_DISPLAY_FLIP for IVB:
9747 * "The full packet must be contained within the same cache line."
9748 *
9749 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9750 * cacheline, if we ever start emitting more commands before
9751 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9752 * then do the cacheline alignment, and finally emit the
9753 * MI_DISPLAY_FLIP.
9754 */
9755 ret = intel_ring_cacheline_align(ring);
9756 if (ret)
9757 return ret;
9758
9759 ret = intel_ring_begin(ring, len);
9760 if (ret)
9761 return ret;
9762
9763 /* Unmask the flip-done completion message. Note that the bspec says that
9764 * we should do this for both the BCS and RCS, and that we must not unmask
9765 * more than one flip event at any time (or ensure that one flip message
9766 * can be sent by waiting for flip-done prior to queueing new flips).
9767 * Experimentation says that BCS works despite DERRMR masking all
9768 * flip-done completion events and that unmasking all planes at once
9769 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9770 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9771 */
9772 if (ring->id == RCS) {
9773 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9774 intel_ring_emit(ring, DERRMR);
9775 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9776 DERRMR_PIPEB_PRI_FLIP_DONE |
9777 DERRMR_PIPEC_PRI_FLIP_DONE));
9778 if (IS_GEN8(dev))
9779 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9780 MI_SRM_LRM_GLOBAL_GTT);
9781 else
9782 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9783 MI_SRM_LRM_GLOBAL_GTT);
9784 intel_ring_emit(ring, DERRMR);
9785 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9786 if (IS_GEN8(dev)) {
9787 intel_ring_emit(ring, 0);
9788 intel_ring_emit(ring, MI_NOOP);
9789 }
9790 }
9791
9792 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9793 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9794 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9795 intel_ring_emit(ring, (MI_NOOP));
9796
9797 intel_mark_page_flip_active(intel_crtc);
9798 __intel_ring_advance(ring);
9799 return 0;
9800 }
9801
9802 static bool use_mmio_flip(struct intel_engine_cs *ring,
9803 struct drm_i915_gem_object *obj)
9804 {
9805 /*
9806 * This is not being used for older platforms, because
9807 * non-availability of flip done interrupt forces us to use
9808 * CS flips. Older platforms derive flip done using some clever
9809 * tricks involving the flip_pending status bits and vblank irqs.
9810 * So using MMIO flips there would disrupt this mechanism.
9811 */
9812
9813 if (ring == NULL)
9814 return true;
9815
9816 if (INTEL_INFO(ring->dev)->gen < 5)
9817 return false;
9818
9819 if (i915.use_mmio_flip < 0)
9820 return false;
9821 else if (i915.use_mmio_flip > 0)
9822 return true;
9823 else if (i915.enable_execlists)
9824 return true;
9825 else
9826 return ring != i915_gem_request_get_ring(obj->last_read_req);
9827 }
9828
9829 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
9830 {
9831 struct drm_device *dev = intel_crtc->base.dev;
9832 struct drm_i915_private *dev_priv = dev->dev_private;
9833 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
9834 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9835 struct drm_i915_gem_object *obj = intel_fb->obj;
9836 const enum pipe pipe = intel_crtc->pipe;
9837 u32 ctl, stride;
9838
9839 ctl = I915_READ(PLANE_CTL(pipe, 0));
9840 ctl &= ~PLANE_CTL_TILED_MASK;
9841 if (obj->tiling_mode == I915_TILING_X)
9842 ctl |= PLANE_CTL_TILED_X;
9843
9844 /*
9845 * The stride is either expressed as a multiple of 64 bytes chunks for
9846 * linear buffers or in number of tiles for tiled buffers.
9847 */
9848 stride = fb->pitches[0] >> 6;
9849 if (obj->tiling_mode == I915_TILING_X)
9850 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
9851
9852 /*
9853 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
9854 * PLANE_SURF updates, the update is then guaranteed to be atomic.
9855 */
9856 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
9857 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
9858
9859 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
9860 POSTING_READ(PLANE_SURF(pipe, 0));
9861 }
9862
9863 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
9864 {
9865 struct drm_device *dev = intel_crtc->base.dev;
9866 struct drm_i915_private *dev_priv = dev->dev_private;
9867 struct intel_framebuffer *intel_fb =
9868 to_intel_framebuffer(intel_crtc->base.primary->fb);
9869 struct drm_i915_gem_object *obj = intel_fb->obj;
9870 u32 dspcntr;
9871 u32 reg;
9872
9873 reg = DSPCNTR(intel_crtc->plane);
9874 dspcntr = I915_READ(reg);
9875
9876 if (obj->tiling_mode != I915_TILING_NONE)
9877 dspcntr |= DISPPLANE_TILED;
9878 else
9879 dspcntr &= ~DISPPLANE_TILED;
9880
9881 I915_WRITE(reg, dspcntr);
9882
9883 I915_WRITE(DSPSURF(intel_crtc->plane),
9884 intel_crtc->unpin_work->gtt_offset);
9885 POSTING_READ(DSPSURF(intel_crtc->plane));
9886
9887 }
9888
9889 /*
9890 * XXX: This is the temporary way to update the plane registers until we get
9891 * around to using the usual plane update functions for MMIO flips
9892 */
9893 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9894 {
9895 struct drm_device *dev = intel_crtc->base.dev;
9896 bool atomic_update;
9897 u32 start_vbl_count;
9898
9899 intel_mark_page_flip_active(intel_crtc);
9900
9901 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9902
9903 if (INTEL_INFO(dev)->gen >= 9)
9904 skl_do_mmio_flip(intel_crtc);
9905 else
9906 /* use_mmio_flip() retricts MMIO flips to ilk+ */
9907 ilk_do_mmio_flip(intel_crtc);
9908
9909 if (atomic_update)
9910 intel_pipe_update_end(intel_crtc, start_vbl_count);
9911 }
9912
9913 static void intel_mmio_flip_work_func(struct work_struct *work)
9914 {
9915 struct intel_crtc *crtc =
9916 container_of(work, struct intel_crtc, mmio_flip.work);
9917 struct intel_mmio_flip *mmio_flip;
9918
9919 mmio_flip = &crtc->mmio_flip;
9920 if (mmio_flip->req)
9921 WARN_ON(__i915_wait_request(mmio_flip->req,
9922 crtc->reset_counter,
9923 false, NULL, NULL) != 0);
9924
9925 intel_do_mmio_flip(crtc);
9926 if (mmio_flip->req) {
9927 mutex_lock(&crtc->base.dev->struct_mutex);
9928 i915_gem_request_assign(&mmio_flip->req, NULL);
9929 mutex_unlock(&crtc->base.dev->struct_mutex);
9930 }
9931 }
9932
9933 static int intel_queue_mmio_flip(struct drm_device *dev,
9934 struct drm_crtc *crtc,
9935 struct drm_framebuffer *fb,
9936 struct drm_i915_gem_object *obj,
9937 struct intel_engine_cs *ring,
9938 uint32_t flags)
9939 {
9940 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9941
9942 i915_gem_request_assign(&intel_crtc->mmio_flip.req,
9943 obj->last_write_req);
9944
9945 schedule_work(&intel_crtc->mmio_flip.work);
9946
9947 return 0;
9948 }
9949
9950 static int intel_default_queue_flip(struct drm_device *dev,
9951 struct drm_crtc *crtc,
9952 struct drm_framebuffer *fb,
9953 struct drm_i915_gem_object *obj,
9954 struct intel_engine_cs *ring,
9955 uint32_t flags)
9956 {
9957 return -ENODEV;
9958 }
9959
9960 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9961 struct drm_crtc *crtc)
9962 {
9963 struct drm_i915_private *dev_priv = dev->dev_private;
9964 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9965 struct intel_unpin_work *work = intel_crtc->unpin_work;
9966 u32 addr;
9967
9968 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9969 return true;
9970
9971 if (!work->enable_stall_check)
9972 return false;
9973
9974 if (work->flip_ready_vblank == 0) {
9975 if (work->flip_queued_req &&
9976 !i915_gem_request_completed(work->flip_queued_req, true))
9977 return false;
9978
9979 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
9980 }
9981
9982 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
9983 return false;
9984
9985 /* Potential stall - if we see that the flip has happened,
9986 * assume a missed interrupt. */
9987 if (INTEL_INFO(dev)->gen >= 4)
9988 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9989 else
9990 addr = I915_READ(DSPADDR(intel_crtc->plane));
9991
9992 /* There is a potential issue here with a false positive after a flip
9993 * to the same address. We could address this by checking for a
9994 * non-incrementing frame counter.
9995 */
9996 return addr == work->gtt_offset;
9997 }
9998
9999 void intel_check_page_flip(struct drm_device *dev, int pipe)
10000 {
10001 struct drm_i915_private *dev_priv = dev->dev_private;
10002 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10003 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10004
10005 WARN_ON(!in_interrupt());
10006
10007 if (crtc == NULL)
10008 return;
10009
10010 spin_lock(&dev->event_lock);
10011 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
10012 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
10013 intel_crtc->unpin_work->flip_queued_vblank,
10014 drm_vblank_count(dev, pipe));
10015 page_flip_completed(intel_crtc);
10016 }
10017 spin_unlock(&dev->event_lock);
10018 }
10019
10020 static int intel_crtc_page_flip(struct drm_crtc *crtc,
10021 struct drm_framebuffer *fb,
10022 struct drm_pending_vblank_event *event,
10023 uint32_t page_flip_flags)
10024 {
10025 struct drm_device *dev = crtc->dev;
10026 struct drm_i915_private *dev_priv = dev->dev_private;
10027 struct drm_framebuffer *old_fb = crtc->primary->fb;
10028 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10029 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10030 struct drm_plane *primary = crtc->primary;
10031 enum pipe pipe = intel_crtc->pipe;
10032 struct intel_unpin_work *work;
10033 struct intel_engine_cs *ring;
10034 int ret;
10035
10036 /*
10037 * drm_mode_page_flip_ioctl() should already catch this, but double
10038 * check to be safe. In the future we may enable pageflipping from
10039 * a disabled primary plane.
10040 */
10041 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
10042 return -EBUSY;
10043
10044 /* Can't change pixel format via MI display flips. */
10045 if (fb->pixel_format != crtc->primary->fb->pixel_format)
10046 return -EINVAL;
10047
10048 /*
10049 * TILEOFF/LINOFF registers can't be changed via MI display flips.
10050 * Note that pitch changes could also affect these register.
10051 */
10052 if (INTEL_INFO(dev)->gen > 3 &&
10053 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10054 fb->pitches[0] != crtc->primary->fb->pitches[0]))
10055 return -EINVAL;
10056
10057 if (i915_terminally_wedged(&dev_priv->gpu_error))
10058 goto out_hang;
10059
10060 work = kzalloc(sizeof(*work), GFP_KERNEL);
10061 if (work == NULL)
10062 return -ENOMEM;
10063
10064 work->event = event;
10065 work->crtc = crtc;
10066 work->old_fb = old_fb;
10067 INIT_WORK(&work->work, intel_unpin_work_fn);
10068
10069 ret = drm_crtc_vblank_get(crtc);
10070 if (ret)
10071 goto free_work;
10072
10073 /* We borrow the event spin lock for protecting unpin_work */
10074 spin_lock_irq(&dev->event_lock);
10075 if (intel_crtc->unpin_work) {
10076 /* Before declaring the flip queue wedged, check if
10077 * the hardware completed the operation behind our backs.
10078 */
10079 if (__intel_pageflip_stall_check(dev, crtc)) {
10080 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10081 page_flip_completed(intel_crtc);
10082 } else {
10083 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
10084 spin_unlock_irq(&dev->event_lock);
10085
10086 drm_crtc_vblank_put(crtc);
10087 kfree(work);
10088 return -EBUSY;
10089 }
10090 }
10091 intel_crtc->unpin_work = work;
10092 spin_unlock_irq(&dev->event_lock);
10093
10094 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10095 flush_workqueue(dev_priv->wq);
10096
10097 /* Reference the objects for the scheduled work. */
10098 drm_framebuffer_reference(work->old_fb);
10099 drm_gem_object_reference(&obj->base);
10100
10101 crtc->primary->fb = fb;
10102 update_state_fb(crtc->primary);
10103
10104 work->pending_flip_obj = obj;
10105
10106 ret = i915_mutex_lock_interruptible(dev);
10107 if (ret)
10108 goto cleanup;
10109
10110 atomic_inc(&intel_crtc->unpin_work_count);
10111 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
10112
10113 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
10114 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
10115
10116 if (IS_VALLEYVIEW(dev)) {
10117 ring = &dev_priv->ring[BCS];
10118 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
10119 /* vlv: DISPLAY_FLIP fails to change tiling */
10120 ring = NULL;
10121 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
10122 ring = &dev_priv->ring[BCS];
10123 } else if (INTEL_INFO(dev)->gen >= 7) {
10124 ring = i915_gem_request_get_ring(obj->last_read_req);
10125 if (ring == NULL || ring->id != RCS)
10126 ring = &dev_priv->ring[BCS];
10127 } else {
10128 ring = &dev_priv->ring[RCS];
10129 }
10130
10131 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
10132 crtc->primary->state, ring);
10133 if (ret)
10134 goto cleanup_pending;
10135
10136 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
10137 + intel_crtc->dspaddr_offset;
10138
10139 if (use_mmio_flip(ring, obj)) {
10140 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
10141 page_flip_flags);
10142 if (ret)
10143 goto cleanup_unpin;
10144
10145 i915_gem_request_assign(&work->flip_queued_req,
10146 obj->last_write_req);
10147 } else {
10148 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
10149 page_flip_flags);
10150 if (ret)
10151 goto cleanup_unpin;
10152
10153 i915_gem_request_assign(&work->flip_queued_req,
10154 intel_ring_get_request(ring));
10155 }
10156
10157 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
10158 work->enable_stall_check = true;
10159
10160 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
10161 INTEL_FRONTBUFFER_PRIMARY(pipe));
10162
10163 intel_fbc_disable(dev);
10164 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10165 mutex_unlock(&dev->struct_mutex);
10166
10167 trace_i915_flip_request(intel_crtc->plane, obj);
10168
10169 return 0;
10170
10171 cleanup_unpin:
10172 intel_unpin_fb_obj(fb, crtc->primary->state);
10173 cleanup_pending:
10174 atomic_dec(&intel_crtc->unpin_work_count);
10175 mutex_unlock(&dev->struct_mutex);
10176 cleanup:
10177 crtc->primary->fb = old_fb;
10178 update_state_fb(crtc->primary);
10179
10180 drm_gem_object_unreference_unlocked(&obj->base);
10181 drm_framebuffer_unreference(work->old_fb);
10182
10183 spin_lock_irq(&dev->event_lock);
10184 intel_crtc->unpin_work = NULL;
10185 spin_unlock_irq(&dev->event_lock);
10186
10187 drm_crtc_vblank_put(crtc);
10188 free_work:
10189 kfree(work);
10190
10191 if (ret == -EIO) {
10192 out_hang:
10193 ret = intel_plane_restore(primary);
10194 if (ret == 0 && event) {
10195 spin_lock_irq(&dev->event_lock);
10196 drm_send_vblank_event(dev, pipe, event);
10197 spin_unlock_irq(&dev->event_lock);
10198 }
10199 }
10200 return ret;
10201 }
10202
10203 static struct drm_crtc_helper_funcs intel_helper_funcs = {
10204 .mode_set_base_atomic = intel_pipe_set_base_atomic,
10205 .load_lut = intel_crtc_load_lut,
10206 .atomic_begin = intel_begin_crtc_commit,
10207 .atomic_flush = intel_finish_crtc_commit,
10208 };
10209
10210 /**
10211 * intel_modeset_update_staged_output_state
10212 *
10213 * Updates the staged output configuration state, e.g. after we've read out the
10214 * current hw state.
10215 */
10216 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
10217 {
10218 struct intel_crtc *crtc;
10219 struct intel_encoder *encoder;
10220 struct intel_connector *connector;
10221
10222 for_each_intel_connector(dev, connector) {
10223 connector->new_encoder =
10224 to_intel_encoder(connector->base.encoder);
10225 }
10226
10227 for_each_intel_encoder(dev, encoder) {
10228 encoder->new_crtc =
10229 to_intel_crtc(encoder->base.crtc);
10230 }
10231
10232 for_each_intel_crtc(dev, crtc) {
10233 crtc->new_enabled = crtc->base.state->enable;
10234
10235 if (crtc->new_enabled)
10236 crtc->new_config = crtc->config;
10237 else
10238 crtc->new_config = NULL;
10239 }
10240 }
10241
10242 /* Transitional helper to copy current connector/encoder state to
10243 * connector->state. This is needed so that code that is partially
10244 * converted to atomic does the right thing.
10245 */
10246 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
10247 {
10248 struct intel_connector *connector;
10249
10250 for_each_intel_connector(dev, connector) {
10251 if (connector->base.encoder) {
10252 connector->base.state->best_encoder =
10253 connector->base.encoder;
10254 connector->base.state->crtc =
10255 connector->base.encoder->crtc;
10256 } else {
10257 connector->base.state->best_encoder = NULL;
10258 connector->base.state->crtc = NULL;
10259 }
10260 }
10261 }
10262
10263 /**
10264 * intel_modeset_commit_output_state
10265 *
10266 * This function copies the stage display pipe configuration to the real one.
10267 */
10268 static void intel_modeset_commit_output_state(struct drm_device *dev)
10269 {
10270 struct intel_crtc *crtc;
10271 struct intel_encoder *encoder;
10272 struct intel_connector *connector;
10273
10274 for_each_intel_connector(dev, connector) {
10275 connector->base.encoder = &connector->new_encoder->base;
10276 }
10277
10278 for_each_intel_encoder(dev, encoder) {
10279 encoder->base.crtc = &encoder->new_crtc->base;
10280 }
10281
10282 for_each_intel_crtc(dev, crtc) {
10283 crtc->base.state->enable = crtc->new_enabled;
10284 crtc->base.enabled = crtc->new_enabled;
10285 }
10286
10287 intel_modeset_update_connector_atomic_state(dev);
10288 }
10289
10290 static void
10291 connected_sink_compute_bpp(struct intel_connector *connector,
10292 struct intel_crtc_state *pipe_config)
10293 {
10294 int bpp = pipe_config->pipe_bpp;
10295
10296 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10297 connector->base.base.id,
10298 connector->base.name);
10299
10300 /* Don't use an invalid EDID bpc value */
10301 if (connector->base.display_info.bpc &&
10302 connector->base.display_info.bpc * 3 < bpp) {
10303 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10304 bpp, connector->base.display_info.bpc*3);
10305 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10306 }
10307
10308 /* Clamp bpp to 8 on screens without EDID 1.4 */
10309 if (connector->base.display_info.bpc == 0 && bpp > 24) {
10310 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10311 bpp);
10312 pipe_config->pipe_bpp = 24;
10313 }
10314 }
10315
10316 static int
10317 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10318 struct drm_framebuffer *fb,
10319 struct intel_crtc_state *pipe_config)
10320 {
10321 struct drm_device *dev = crtc->base.dev;
10322 struct intel_connector *connector;
10323 int bpp;
10324
10325 switch (fb->pixel_format) {
10326 case DRM_FORMAT_C8:
10327 bpp = 8*3; /* since we go through a colormap */
10328 break;
10329 case DRM_FORMAT_XRGB1555:
10330 case DRM_FORMAT_ARGB1555:
10331 /* checked in intel_framebuffer_init already */
10332 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10333 return -EINVAL;
10334 case DRM_FORMAT_RGB565:
10335 bpp = 6*3; /* min is 18bpp */
10336 break;
10337 case DRM_FORMAT_XBGR8888:
10338 case DRM_FORMAT_ABGR8888:
10339 /* checked in intel_framebuffer_init already */
10340 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10341 return -EINVAL;
10342 case DRM_FORMAT_XRGB8888:
10343 case DRM_FORMAT_ARGB8888:
10344 bpp = 8*3;
10345 break;
10346 case DRM_FORMAT_XRGB2101010:
10347 case DRM_FORMAT_ARGB2101010:
10348 case DRM_FORMAT_XBGR2101010:
10349 case DRM_FORMAT_ABGR2101010:
10350 /* checked in intel_framebuffer_init already */
10351 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10352 return -EINVAL;
10353 bpp = 10*3;
10354 break;
10355 /* TODO: gen4+ supports 16 bpc floating point, too. */
10356 default:
10357 DRM_DEBUG_KMS("unsupported depth\n");
10358 return -EINVAL;
10359 }
10360
10361 pipe_config->pipe_bpp = bpp;
10362
10363 /* Clamp display bpp to EDID value */
10364 for_each_intel_connector(dev, connector) {
10365 if (!connector->new_encoder ||
10366 connector->new_encoder->new_crtc != crtc)
10367 continue;
10368
10369 connected_sink_compute_bpp(connector, pipe_config);
10370 }
10371
10372 return bpp;
10373 }
10374
10375 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10376 {
10377 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10378 "type: 0x%x flags: 0x%x\n",
10379 mode->crtc_clock,
10380 mode->crtc_hdisplay, mode->crtc_hsync_start,
10381 mode->crtc_hsync_end, mode->crtc_htotal,
10382 mode->crtc_vdisplay, mode->crtc_vsync_start,
10383 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10384 }
10385
10386 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10387 struct intel_crtc_state *pipe_config,
10388 const char *context)
10389 {
10390 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10391 context, pipe_name(crtc->pipe));
10392
10393 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10394 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10395 pipe_config->pipe_bpp, pipe_config->dither);
10396 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10397 pipe_config->has_pch_encoder,
10398 pipe_config->fdi_lanes,
10399 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10400 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10401 pipe_config->fdi_m_n.tu);
10402 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10403 pipe_config->has_dp_encoder,
10404 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10405 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10406 pipe_config->dp_m_n.tu);
10407
10408 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10409 pipe_config->has_dp_encoder,
10410 pipe_config->dp_m2_n2.gmch_m,
10411 pipe_config->dp_m2_n2.gmch_n,
10412 pipe_config->dp_m2_n2.link_m,
10413 pipe_config->dp_m2_n2.link_n,
10414 pipe_config->dp_m2_n2.tu);
10415
10416 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10417 pipe_config->has_audio,
10418 pipe_config->has_infoframe);
10419
10420 DRM_DEBUG_KMS("requested mode:\n");
10421 drm_mode_debug_printmodeline(&pipe_config->base.mode);
10422 DRM_DEBUG_KMS("adjusted mode:\n");
10423 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10424 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10425 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10426 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10427 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10428 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10429 pipe_config->gmch_pfit.control,
10430 pipe_config->gmch_pfit.pgm_ratios,
10431 pipe_config->gmch_pfit.lvds_border_bits);
10432 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10433 pipe_config->pch_pfit.pos,
10434 pipe_config->pch_pfit.size,
10435 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10436 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10437 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10438 }
10439
10440 static bool encoders_cloneable(const struct intel_encoder *a,
10441 const struct intel_encoder *b)
10442 {
10443 /* masks could be asymmetric, so check both ways */
10444 return a == b || (a->cloneable & (1 << b->type) &&
10445 b->cloneable & (1 << a->type));
10446 }
10447
10448 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10449 struct intel_encoder *encoder)
10450 {
10451 struct drm_device *dev = crtc->base.dev;
10452 struct intel_encoder *source_encoder;
10453
10454 for_each_intel_encoder(dev, source_encoder) {
10455 if (source_encoder->new_crtc != crtc)
10456 continue;
10457
10458 if (!encoders_cloneable(encoder, source_encoder))
10459 return false;
10460 }
10461
10462 return true;
10463 }
10464
10465 static bool check_encoder_cloning(struct intel_crtc *crtc)
10466 {
10467 struct drm_device *dev = crtc->base.dev;
10468 struct intel_encoder *encoder;
10469
10470 for_each_intel_encoder(dev, encoder) {
10471 if (encoder->new_crtc != crtc)
10472 continue;
10473
10474 if (!check_single_encoder_cloning(crtc, encoder))
10475 return false;
10476 }
10477
10478 return true;
10479 }
10480
10481 static bool check_digital_port_conflicts(struct drm_device *dev)
10482 {
10483 struct intel_connector *connector;
10484 unsigned int used_ports = 0;
10485
10486 /*
10487 * Walk the connector list instead of the encoder
10488 * list to detect the problem on ddi platforms
10489 * where there's just one encoder per digital port.
10490 */
10491 for_each_intel_connector(dev, connector) {
10492 struct intel_encoder *encoder = connector->new_encoder;
10493
10494 if (!encoder)
10495 continue;
10496
10497 WARN_ON(!encoder->new_crtc);
10498
10499 switch (encoder->type) {
10500 unsigned int port_mask;
10501 case INTEL_OUTPUT_UNKNOWN:
10502 if (WARN_ON(!HAS_DDI(dev)))
10503 break;
10504 case INTEL_OUTPUT_DISPLAYPORT:
10505 case INTEL_OUTPUT_HDMI:
10506 case INTEL_OUTPUT_EDP:
10507 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10508
10509 /* the same port mustn't appear more than once */
10510 if (used_ports & port_mask)
10511 return false;
10512
10513 used_ports |= port_mask;
10514 default:
10515 break;
10516 }
10517 }
10518
10519 return true;
10520 }
10521
10522 static void
10523 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
10524 {
10525 struct drm_crtc_state tmp_state;
10526
10527 /* Clear only the intel specific part of the crtc state */
10528 tmp_state = crtc_state->base;
10529 memset(crtc_state, 0, sizeof *crtc_state);
10530 crtc_state->base = tmp_state;
10531 }
10532
10533 static struct intel_crtc_state *
10534 intel_modeset_pipe_config(struct drm_crtc *crtc,
10535 struct drm_framebuffer *fb,
10536 struct drm_display_mode *mode,
10537 struct drm_atomic_state *state)
10538 {
10539 struct drm_device *dev = crtc->dev;
10540 struct intel_encoder *encoder;
10541 struct intel_connector *connector;
10542 struct drm_connector_state *connector_state;
10543 struct intel_crtc_state *pipe_config;
10544 int plane_bpp, ret = -EINVAL;
10545 int i;
10546 bool retry = true;
10547
10548 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10549 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10550 return ERR_PTR(-EINVAL);
10551 }
10552
10553 if (!check_digital_port_conflicts(dev)) {
10554 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10555 return ERR_PTR(-EINVAL);
10556 }
10557
10558 pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
10559 if (IS_ERR(pipe_config))
10560 return pipe_config;
10561
10562 clear_intel_crtc_state(pipe_config);
10563
10564 pipe_config->base.crtc = crtc;
10565 drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
10566 drm_mode_copy(&pipe_config->base.mode, mode);
10567
10568 pipe_config->cpu_transcoder =
10569 (enum transcoder) to_intel_crtc(crtc)->pipe;
10570 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10571
10572 /*
10573 * Sanitize sync polarity flags based on requested ones. If neither
10574 * positive or negative polarity is requested, treat this as meaning
10575 * negative polarity.
10576 */
10577 if (!(pipe_config->base.adjusted_mode.flags &
10578 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10579 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10580
10581 if (!(pipe_config->base.adjusted_mode.flags &
10582 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10583 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10584
10585 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10586 * plane pixel format and any sink constraints into account. Returns the
10587 * source plane bpp so that dithering can be selected on mismatches
10588 * after encoders and crtc also have had their say. */
10589 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10590 fb, pipe_config);
10591 if (plane_bpp < 0)
10592 goto fail;
10593
10594 /*
10595 * Determine the real pipe dimensions. Note that stereo modes can
10596 * increase the actual pipe size due to the frame doubling and
10597 * insertion of additional space for blanks between the frame. This
10598 * is stored in the crtc timings. We use the requested mode to do this
10599 * computation to clearly distinguish it from the adjusted mode, which
10600 * can be changed by the connectors in the below retry loop.
10601 */
10602 drm_crtc_get_hv_timing(&pipe_config->base.mode,
10603 &pipe_config->pipe_src_w,
10604 &pipe_config->pipe_src_h);
10605
10606 encoder_retry:
10607 /* Ensure the port clock defaults are reset when retrying. */
10608 pipe_config->port_clock = 0;
10609 pipe_config->pixel_multiplier = 1;
10610
10611 /* Fill in default crtc timings, allow encoders to overwrite them. */
10612 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10613 CRTC_STEREO_DOUBLE);
10614
10615 /* Pass our mode to the connectors and the CRTC to give them a chance to
10616 * adjust it according to limitations or connector properties, and also
10617 * a chance to reject the mode entirely.
10618 */
10619 for (i = 0; i < state->num_connector; i++) {
10620 connector = to_intel_connector(state->connectors[i]);
10621 if (!connector)
10622 continue;
10623
10624 connector_state = state->connector_states[i];
10625 if (connector_state->crtc != crtc)
10626 continue;
10627
10628 encoder = to_intel_encoder(connector_state->best_encoder);
10629
10630 if (!(encoder->compute_config(encoder, pipe_config))) {
10631 DRM_DEBUG_KMS("Encoder config failure\n");
10632 goto fail;
10633 }
10634 }
10635
10636 /* Set default port clock if not overwritten by the encoder. Needs to be
10637 * done afterwards in case the encoder adjusts the mode. */
10638 if (!pipe_config->port_clock)
10639 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10640 * pipe_config->pixel_multiplier;
10641
10642 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10643 if (ret < 0) {
10644 DRM_DEBUG_KMS("CRTC fixup failed\n");
10645 goto fail;
10646 }
10647
10648 if (ret == RETRY) {
10649 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10650 ret = -EINVAL;
10651 goto fail;
10652 }
10653
10654 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10655 retry = false;
10656 goto encoder_retry;
10657 }
10658
10659 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10660 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10661 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10662
10663 return pipe_config;
10664 fail:
10665 return ERR_PTR(ret);
10666 }
10667
10668 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10669 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10670 static void
10671 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10672 unsigned *prepare_pipes, unsigned *disable_pipes)
10673 {
10674 struct intel_crtc *intel_crtc;
10675 struct drm_device *dev = crtc->dev;
10676 struct intel_encoder *encoder;
10677 struct intel_connector *connector;
10678 struct drm_crtc *tmp_crtc;
10679
10680 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10681
10682 /* Check which crtcs have changed outputs connected to them, these need
10683 * to be part of the prepare_pipes mask. We don't (yet) support global
10684 * modeset across multiple crtcs, so modeset_pipes will only have one
10685 * bit set at most. */
10686 for_each_intel_connector(dev, connector) {
10687 if (connector->base.encoder == &connector->new_encoder->base)
10688 continue;
10689
10690 if (connector->base.encoder) {
10691 tmp_crtc = connector->base.encoder->crtc;
10692
10693 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10694 }
10695
10696 if (connector->new_encoder)
10697 *prepare_pipes |=
10698 1 << connector->new_encoder->new_crtc->pipe;
10699 }
10700
10701 for_each_intel_encoder(dev, encoder) {
10702 if (encoder->base.crtc == &encoder->new_crtc->base)
10703 continue;
10704
10705 if (encoder->base.crtc) {
10706 tmp_crtc = encoder->base.crtc;
10707
10708 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10709 }
10710
10711 if (encoder->new_crtc)
10712 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10713 }
10714
10715 /* Check for pipes that will be enabled/disabled ... */
10716 for_each_intel_crtc(dev, intel_crtc) {
10717 if (intel_crtc->base.state->enable == intel_crtc->new_enabled)
10718 continue;
10719
10720 if (!intel_crtc->new_enabled)
10721 *disable_pipes |= 1 << intel_crtc->pipe;
10722 else
10723 *prepare_pipes |= 1 << intel_crtc->pipe;
10724 }
10725
10726
10727 /* set_mode is also used to update properties on life display pipes. */
10728 intel_crtc = to_intel_crtc(crtc);
10729 if (intel_crtc->new_enabled)
10730 *prepare_pipes |= 1 << intel_crtc->pipe;
10731
10732 /*
10733 * For simplicity do a full modeset on any pipe where the output routing
10734 * changed. We could be more clever, but that would require us to be
10735 * more careful with calling the relevant encoder->mode_set functions.
10736 */
10737 if (*prepare_pipes)
10738 *modeset_pipes = *prepare_pipes;
10739
10740 /* ... and mask these out. */
10741 *modeset_pipes &= ~(*disable_pipes);
10742 *prepare_pipes &= ~(*disable_pipes);
10743
10744 /*
10745 * HACK: We don't (yet) fully support global modesets. intel_set_config
10746 * obies this rule, but the modeset restore mode of
10747 * intel_modeset_setup_hw_state does not.
10748 */
10749 *modeset_pipes &= 1 << intel_crtc->pipe;
10750 *prepare_pipes &= 1 << intel_crtc->pipe;
10751
10752 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10753 *modeset_pipes, *prepare_pipes, *disable_pipes);
10754 }
10755
10756 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10757 {
10758 struct drm_encoder *encoder;
10759 struct drm_device *dev = crtc->dev;
10760
10761 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10762 if (encoder->crtc == crtc)
10763 return true;
10764
10765 return false;
10766 }
10767
10768 static void
10769 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10770 {
10771 struct drm_i915_private *dev_priv = dev->dev_private;
10772 struct intel_encoder *intel_encoder;
10773 struct intel_crtc *intel_crtc;
10774 struct drm_connector *connector;
10775
10776 intel_shared_dpll_commit(dev_priv);
10777
10778 for_each_intel_encoder(dev, intel_encoder) {
10779 if (!intel_encoder->base.crtc)
10780 continue;
10781
10782 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10783
10784 if (prepare_pipes & (1 << intel_crtc->pipe))
10785 intel_encoder->connectors_active = false;
10786 }
10787
10788 intel_modeset_commit_output_state(dev);
10789
10790 /* Double check state. */
10791 for_each_intel_crtc(dev, intel_crtc) {
10792 WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base));
10793 WARN_ON(intel_crtc->new_config &&
10794 intel_crtc->new_config != intel_crtc->config);
10795 WARN_ON(intel_crtc->base.state->enable != !!intel_crtc->new_config);
10796 }
10797
10798 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10799 if (!connector->encoder || !connector->encoder->crtc)
10800 continue;
10801
10802 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10803
10804 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10805 struct drm_property *dpms_property =
10806 dev->mode_config.dpms_property;
10807
10808 connector->dpms = DRM_MODE_DPMS_ON;
10809 drm_object_property_set_value(&connector->base,
10810 dpms_property,
10811 DRM_MODE_DPMS_ON);
10812
10813 intel_encoder = to_intel_encoder(connector->encoder);
10814 intel_encoder->connectors_active = true;
10815 }
10816 }
10817
10818 }
10819
10820 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10821 {
10822 int diff;
10823
10824 if (clock1 == clock2)
10825 return true;
10826
10827 if (!clock1 || !clock2)
10828 return false;
10829
10830 diff = abs(clock1 - clock2);
10831
10832 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10833 return true;
10834
10835 return false;
10836 }
10837
10838 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10839 list_for_each_entry((intel_crtc), \
10840 &(dev)->mode_config.crtc_list, \
10841 base.head) \
10842 if (mask & (1 <<(intel_crtc)->pipe))
10843
10844 static bool
10845 intel_pipe_config_compare(struct drm_device *dev,
10846 struct intel_crtc_state *current_config,
10847 struct intel_crtc_state *pipe_config)
10848 {
10849 #define PIPE_CONF_CHECK_X(name) \
10850 if (current_config->name != pipe_config->name) { \
10851 DRM_ERROR("mismatch in " #name " " \
10852 "(expected 0x%08x, found 0x%08x)\n", \
10853 current_config->name, \
10854 pipe_config->name); \
10855 return false; \
10856 }
10857
10858 #define PIPE_CONF_CHECK_I(name) \
10859 if (current_config->name != pipe_config->name) { \
10860 DRM_ERROR("mismatch in " #name " " \
10861 "(expected %i, found %i)\n", \
10862 current_config->name, \
10863 pipe_config->name); \
10864 return false; \
10865 }
10866
10867 /* This is required for BDW+ where there is only one set of registers for
10868 * switching between high and low RR.
10869 * This macro can be used whenever a comparison has to be made between one
10870 * hw state and multiple sw state variables.
10871 */
10872 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10873 if ((current_config->name != pipe_config->name) && \
10874 (current_config->alt_name != pipe_config->name)) { \
10875 DRM_ERROR("mismatch in " #name " " \
10876 "(expected %i or %i, found %i)\n", \
10877 current_config->name, \
10878 current_config->alt_name, \
10879 pipe_config->name); \
10880 return false; \
10881 }
10882
10883 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10884 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10885 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10886 "(expected %i, found %i)\n", \
10887 current_config->name & (mask), \
10888 pipe_config->name & (mask)); \
10889 return false; \
10890 }
10891
10892 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10893 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10894 DRM_ERROR("mismatch in " #name " " \
10895 "(expected %i, found %i)\n", \
10896 current_config->name, \
10897 pipe_config->name); \
10898 return false; \
10899 }
10900
10901 #define PIPE_CONF_QUIRK(quirk) \
10902 ((current_config->quirks | pipe_config->quirks) & (quirk))
10903
10904 PIPE_CONF_CHECK_I(cpu_transcoder);
10905
10906 PIPE_CONF_CHECK_I(has_pch_encoder);
10907 PIPE_CONF_CHECK_I(fdi_lanes);
10908 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10909 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10910 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10911 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10912 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10913
10914 PIPE_CONF_CHECK_I(has_dp_encoder);
10915
10916 if (INTEL_INFO(dev)->gen < 8) {
10917 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10918 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10919 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10920 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10921 PIPE_CONF_CHECK_I(dp_m_n.tu);
10922
10923 if (current_config->has_drrs) {
10924 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10925 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10926 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10927 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10928 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10929 }
10930 } else {
10931 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10932 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10933 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10934 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10935 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10936 }
10937
10938 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
10939 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
10940 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
10941 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
10942 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
10943 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
10944
10945 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
10946 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
10947 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
10948 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
10949 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
10950 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
10951
10952 PIPE_CONF_CHECK_I(pixel_multiplier);
10953 PIPE_CONF_CHECK_I(has_hdmi_sink);
10954 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10955 IS_VALLEYVIEW(dev))
10956 PIPE_CONF_CHECK_I(limited_color_range);
10957 PIPE_CONF_CHECK_I(has_infoframe);
10958
10959 PIPE_CONF_CHECK_I(has_audio);
10960
10961 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10962 DRM_MODE_FLAG_INTERLACE);
10963
10964 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10965 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10966 DRM_MODE_FLAG_PHSYNC);
10967 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10968 DRM_MODE_FLAG_NHSYNC);
10969 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10970 DRM_MODE_FLAG_PVSYNC);
10971 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10972 DRM_MODE_FLAG_NVSYNC);
10973 }
10974
10975 PIPE_CONF_CHECK_I(pipe_src_w);
10976 PIPE_CONF_CHECK_I(pipe_src_h);
10977
10978 /*
10979 * FIXME: BIOS likes to set up a cloned config with lvds+external
10980 * screen. Since we don't yet re-compute the pipe config when moving
10981 * just the lvds port away to another pipe the sw tracking won't match.
10982 *
10983 * Proper atomic modesets with recomputed global state will fix this.
10984 * Until then just don't check gmch state for inherited modes.
10985 */
10986 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10987 PIPE_CONF_CHECK_I(gmch_pfit.control);
10988 /* pfit ratios are autocomputed by the hw on gen4+ */
10989 if (INTEL_INFO(dev)->gen < 4)
10990 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10991 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10992 }
10993
10994 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10995 if (current_config->pch_pfit.enabled) {
10996 PIPE_CONF_CHECK_I(pch_pfit.pos);
10997 PIPE_CONF_CHECK_I(pch_pfit.size);
10998 }
10999
11000 /* BDW+ don't expose a synchronous way to read the state */
11001 if (IS_HASWELL(dev))
11002 PIPE_CONF_CHECK_I(ips_enabled);
11003
11004 PIPE_CONF_CHECK_I(double_wide);
11005
11006 PIPE_CONF_CHECK_X(ddi_pll_sel);
11007
11008 PIPE_CONF_CHECK_I(shared_dpll);
11009 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11010 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11011 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11012 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11013 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11014 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11015 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11016 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11017
11018 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
11019 PIPE_CONF_CHECK_I(pipe_bpp);
11020
11021 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11022 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11023
11024 #undef PIPE_CONF_CHECK_X
11025 #undef PIPE_CONF_CHECK_I
11026 #undef PIPE_CONF_CHECK_I_ALT
11027 #undef PIPE_CONF_CHECK_FLAGS
11028 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11029 #undef PIPE_CONF_QUIRK
11030
11031 return true;
11032 }
11033
11034 static void check_wm_state(struct drm_device *dev)
11035 {
11036 struct drm_i915_private *dev_priv = dev->dev_private;
11037 struct skl_ddb_allocation hw_ddb, *sw_ddb;
11038 struct intel_crtc *intel_crtc;
11039 int plane;
11040
11041 if (INTEL_INFO(dev)->gen < 9)
11042 return;
11043
11044 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11045 sw_ddb = &dev_priv->wm.skl_hw.ddb;
11046
11047 for_each_intel_crtc(dev, intel_crtc) {
11048 struct skl_ddb_entry *hw_entry, *sw_entry;
11049 const enum pipe pipe = intel_crtc->pipe;
11050
11051 if (!intel_crtc->active)
11052 continue;
11053
11054 /* planes */
11055 for_each_plane(dev_priv, pipe, plane) {
11056 hw_entry = &hw_ddb.plane[pipe][plane];
11057 sw_entry = &sw_ddb->plane[pipe][plane];
11058
11059 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11060 continue;
11061
11062 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
11063 "(expected (%u,%u), found (%u,%u))\n",
11064 pipe_name(pipe), plane + 1,
11065 sw_entry->start, sw_entry->end,
11066 hw_entry->start, hw_entry->end);
11067 }
11068
11069 /* cursor */
11070 hw_entry = &hw_ddb.cursor[pipe];
11071 sw_entry = &sw_ddb->cursor[pipe];
11072
11073 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11074 continue;
11075
11076 DRM_ERROR("mismatch in DDB state pipe %c cursor "
11077 "(expected (%u,%u), found (%u,%u))\n",
11078 pipe_name(pipe),
11079 sw_entry->start, sw_entry->end,
11080 hw_entry->start, hw_entry->end);
11081 }
11082 }
11083
11084 static void
11085 check_connector_state(struct drm_device *dev)
11086 {
11087 struct intel_connector *connector;
11088
11089 for_each_intel_connector(dev, connector) {
11090 /* This also checks the encoder/connector hw state with the
11091 * ->get_hw_state callbacks. */
11092 intel_connector_check_state(connector);
11093
11094 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
11095 "connector's staged encoder doesn't match current encoder\n");
11096 }
11097 }
11098
11099 static void
11100 check_encoder_state(struct drm_device *dev)
11101 {
11102 struct intel_encoder *encoder;
11103 struct intel_connector *connector;
11104
11105 for_each_intel_encoder(dev, encoder) {
11106 bool enabled = false;
11107 bool active = false;
11108 enum pipe pipe, tracked_pipe;
11109
11110 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11111 encoder->base.base.id,
11112 encoder->base.name);
11113
11114 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
11115 "encoder's stage crtc doesn't match current crtc\n");
11116 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
11117 "encoder's active_connectors set, but no crtc\n");
11118
11119 for_each_intel_connector(dev, connector) {
11120 if (connector->base.encoder != &encoder->base)
11121 continue;
11122 enabled = true;
11123 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
11124 active = true;
11125 }
11126 /*
11127 * for MST connectors if we unplug the connector is gone
11128 * away but the encoder is still connected to a crtc
11129 * until a modeset happens in response to the hotplug.
11130 */
11131 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
11132 continue;
11133
11134 I915_STATE_WARN(!!encoder->base.crtc != enabled,
11135 "encoder's enabled state mismatch "
11136 "(expected %i, found %i)\n",
11137 !!encoder->base.crtc, enabled);
11138 I915_STATE_WARN(active && !encoder->base.crtc,
11139 "active encoder with no crtc\n");
11140
11141 I915_STATE_WARN(encoder->connectors_active != active,
11142 "encoder's computed active state doesn't match tracked active state "
11143 "(expected %i, found %i)\n", active, encoder->connectors_active);
11144
11145 active = encoder->get_hw_state(encoder, &pipe);
11146 I915_STATE_WARN(active != encoder->connectors_active,
11147 "encoder's hw state doesn't match sw tracking "
11148 "(expected %i, found %i)\n",
11149 encoder->connectors_active, active);
11150
11151 if (!encoder->base.crtc)
11152 continue;
11153
11154 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
11155 I915_STATE_WARN(active && pipe != tracked_pipe,
11156 "active encoder's pipe doesn't match"
11157 "(expected %i, found %i)\n",
11158 tracked_pipe, pipe);
11159
11160 }
11161 }
11162
11163 static void
11164 check_crtc_state(struct drm_device *dev)
11165 {
11166 struct drm_i915_private *dev_priv = dev->dev_private;
11167 struct intel_crtc *crtc;
11168 struct intel_encoder *encoder;
11169 struct intel_crtc_state pipe_config;
11170
11171 for_each_intel_crtc(dev, crtc) {
11172 bool enabled = false;
11173 bool active = false;
11174
11175 memset(&pipe_config, 0, sizeof(pipe_config));
11176
11177 DRM_DEBUG_KMS("[CRTC:%d]\n",
11178 crtc->base.base.id);
11179
11180 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
11181 "active crtc, but not enabled in sw tracking\n");
11182
11183 for_each_intel_encoder(dev, encoder) {
11184 if (encoder->base.crtc != &crtc->base)
11185 continue;
11186 enabled = true;
11187 if (encoder->connectors_active)
11188 active = true;
11189 }
11190
11191 I915_STATE_WARN(active != crtc->active,
11192 "crtc's computed active state doesn't match tracked active state "
11193 "(expected %i, found %i)\n", active, crtc->active);
11194 I915_STATE_WARN(enabled != crtc->base.state->enable,
11195 "crtc's computed enabled state doesn't match tracked enabled state "
11196 "(expected %i, found %i)\n", enabled,
11197 crtc->base.state->enable);
11198
11199 active = dev_priv->display.get_pipe_config(crtc,
11200 &pipe_config);
11201
11202 /* hw state is inconsistent with the pipe quirk */
11203 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
11204 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
11205 active = crtc->active;
11206
11207 for_each_intel_encoder(dev, encoder) {
11208 enum pipe pipe;
11209 if (encoder->base.crtc != &crtc->base)
11210 continue;
11211 if (encoder->get_hw_state(encoder, &pipe))
11212 encoder->get_config(encoder, &pipe_config);
11213 }
11214
11215 I915_STATE_WARN(crtc->active != active,
11216 "crtc active state doesn't match with hw state "
11217 "(expected %i, found %i)\n", crtc->active, active);
11218
11219 if (active &&
11220 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
11221 I915_STATE_WARN(1, "pipe state doesn't match!\n");
11222 intel_dump_pipe_config(crtc, &pipe_config,
11223 "[hw state]");
11224 intel_dump_pipe_config(crtc, crtc->config,
11225 "[sw state]");
11226 }
11227 }
11228 }
11229
11230 static void
11231 check_shared_dpll_state(struct drm_device *dev)
11232 {
11233 struct drm_i915_private *dev_priv = dev->dev_private;
11234 struct intel_crtc *crtc;
11235 struct intel_dpll_hw_state dpll_hw_state;
11236 int i;
11237
11238 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11239 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11240 int enabled_crtcs = 0, active_crtcs = 0;
11241 bool active;
11242
11243 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11244
11245 DRM_DEBUG_KMS("%s\n", pll->name);
11246
11247 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
11248
11249 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
11250 "more active pll users than references: %i vs %i\n",
11251 pll->active, hweight32(pll->config.crtc_mask));
11252 I915_STATE_WARN(pll->active && !pll->on,
11253 "pll in active use but not on in sw tracking\n");
11254 I915_STATE_WARN(pll->on && !pll->active,
11255 "pll in on but not on in use in sw tracking\n");
11256 I915_STATE_WARN(pll->on != active,
11257 "pll on state mismatch (expected %i, found %i)\n",
11258 pll->on, active);
11259
11260 for_each_intel_crtc(dev, crtc) {
11261 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
11262 enabled_crtcs++;
11263 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11264 active_crtcs++;
11265 }
11266 I915_STATE_WARN(pll->active != active_crtcs,
11267 "pll active crtcs mismatch (expected %i, found %i)\n",
11268 pll->active, active_crtcs);
11269 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
11270 "pll enabled crtcs mismatch (expected %i, found %i)\n",
11271 hweight32(pll->config.crtc_mask), enabled_crtcs);
11272
11273 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
11274 sizeof(dpll_hw_state)),
11275 "pll hw state mismatch\n");
11276 }
11277 }
11278
11279 void
11280 intel_modeset_check_state(struct drm_device *dev)
11281 {
11282 check_wm_state(dev);
11283 check_connector_state(dev);
11284 check_encoder_state(dev);
11285 check_crtc_state(dev);
11286 check_shared_dpll_state(dev);
11287 }
11288
11289 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
11290 int dotclock)
11291 {
11292 /*
11293 * FDI already provided one idea for the dotclock.
11294 * Yell if the encoder disagrees.
11295 */
11296 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
11297 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11298 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
11299 }
11300
11301 static void update_scanline_offset(struct intel_crtc *crtc)
11302 {
11303 struct drm_device *dev = crtc->base.dev;
11304
11305 /*
11306 * The scanline counter increments at the leading edge of hsync.
11307 *
11308 * On most platforms it starts counting from vtotal-1 on the
11309 * first active line. That means the scanline counter value is
11310 * always one less than what we would expect. Ie. just after
11311 * start of vblank, which also occurs at start of hsync (on the
11312 * last active line), the scanline counter will read vblank_start-1.
11313 *
11314 * On gen2 the scanline counter starts counting from 1 instead
11315 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11316 * to keep the value positive), instead of adding one.
11317 *
11318 * On HSW+ the behaviour of the scanline counter depends on the output
11319 * type. For DP ports it behaves like most other platforms, but on HDMI
11320 * there's an extra 1 line difference. So we need to add two instead of
11321 * one to the value.
11322 */
11323 if (IS_GEN2(dev)) {
11324 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
11325 int vtotal;
11326
11327 vtotal = mode->crtc_vtotal;
11328 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
11329 vtotal /= 2;
11330
11331 crtc->scanline_offset = vtotal - 1;
11332 } else if (HAS_DDI(dev) &&
11333 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
11334 crtc->scanline_offset = 2;
11335 } else
11336 crtc->scanline_offset = 1;
11337 }
11338
11339 static struct intel_crtc_state *
11340 intel_modeset_compute_config(struct drm_crtc *crtc,
11341 struct drm_display_mode *mode,
11342 struct drm_framebuffer *fb,
11343 struct drm_atomic_state *state,
11344 unsigned *modeset_pipes,
11345 unsigned *prepare_pipes,
11346 unsigned *disable_pipes)
11347 {
11348 struct drm_device *dev = crtc->dev;
11349 struct intel_crtc_state *pipe_config = NULL;
11350 struct intel_crtc *intel_crtc;
11351 int ret = 0;
11352
11353 ret = drm_atomic_add_affected_connectors(state, crtc);
11354 if (ret)
11355 return ERR_PTR(ret);
11356
11357 intel_modeset_affected_pipes(crtc, modeset_pipes,
11358 prepare_pipes, disable_pipes);
11359
11360 for_each_intel_crtc_masked(dev, *disable_pipes, intel_crtc) {
11361 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
11362 if (IS_ERR(pipe_config))
11363 return pipe_config;
11364
11365 pipe_config->base.enable = false;
11366 }
11367
11368 /*
11369 * Note this needs changes when we start tracking multiple modes
11370 * and crtcs. At that point we'll need to compute the whole config
11371 * (i.e. one pipe_config for each crtc) rather than just the one
11372 * for this crtc.
11373 */
11374 for_each_intel_crtc_masked(dev, *modeset_pipes, intel_crtc) {
11375 /* FIXME: For now we still expect modeset_pipes has at most
11376 * one bit set. */
11377 if (WARN_ON(&intel_crtc->base != crtc))
11378 continue;
11379
11380 pipe_config = intel_modeset_pipe_config(crtc, fb, mode, state);
11381 if (IS_ERR(pipe_config))
11382 return pipe_config;
11383
11384 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11385 "[modeset]");
11386 }
11387
11388 return intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));;
11389 }
11390
11391 static int __intel_set_mode_setup_plls(struct drm_device *dev,
11392 unsigned modeset_pipes,
11393 unsigned disable_pipes)
11394 {
11395 struct drm_i915_private *dev_priv = to_i915(dev);
11396 unsigned clear_pipes = modeset_pipes | disable_pipes;
11397 struct intel_crtc *intel_crtc;
11398 int ret = 0;
11399
11400 if (!dev_priv->display.crtc_compute_clock)
11401 return 0;
11402
11403 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
11404 if (ret)
11405 goto done;
11406
11407 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11408 struct intel_crtc_state *state = intel_crtc->new_config;
11409 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11410 state);
11411 if (ret) {
11412 intel_shared_dpll_abort_config(dev_priv);
11413 goto done;
11414 }
11415 }
11416
11417 done:
11418 return ret;
11419 }
11420
11421 static int __intel_set_mode(struct drm_crtc *crtc,
11422 struct drm_display_mode *mode,
11423 int x, int y, struct drm_framebuffer *fb,
11424 struct intel_crtc_state *pipe_config,
11425 unsigned modeset_pipes,
11426 unsigned prepare_pipes,
11427 unsigned disable_pipes)
11428 {
11429 struct drm_device *dev = crtc->dev;
11430 struct drm_i915_private *dev_priv = dev->dev_private;
11431 struct drm_display_mode *saved_mode;
11432 struct intel_crtc_state *crtc_state_copy = NULL;
11433 struct intel_crtc *intel_crtc;
11434 int ret = 0;
11435
11436 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
11437 if (!saved_mode)
11438 return -ENOMEM;
11439
11440 crtc_state_copy = kmalloc(sizeof(*crtc_state_copy), GFP_KERNEL);
11441 if (!crtc_state_copy) {
11442 ret = -ENOMEM;
11443 goto done;
11444 }
11445
11446 *saved_mode = crtc->mode;
11447
11448 if (modeset_pipes)
11449 to_intel_crtc(crtc)->new_config = pipe_config;
11450
11451 /*
11452 * See if the config requires any additional preparation, e.g.
11453 * to adjust global state with pipes off. We need to do this
11454 * here so we can get the modeset_pipe updated config for the new
11455 * mode set on this crtc. For other crtcs we need to use the
11456 * adjusted_mode bits in the crtc directly.
11457 */
11458 if (IS_VALLEYVIEW(dev)) {
11459 valleyview_modeset_global_pipes(dev, &prepare_pipes);
11460
11461 /* may have added more to prepare_pipes than we should */
11462 prepare_pipes &= ~disable_pipes;
11463 }
11464
11465 ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
11466 if (ret)
11467 goto done;
11468
11469 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11470 intel_crtc_disable(&intel_crtc->base);
11471
11472 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11473 if (intel_crtc->base.state->enable)
11474 dev_priv->display.crtc_disable(&intel_crtc->base);
11475 }
11476
11477 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11478 * to set it here already despite that we pass it down the callchain.
11479 *
11480 * Note we'll need to fix this up when we start tracking multiple
11481 * pipes; here we assume a single modeset_pipe and only track the
11482 * single crtc and mode.
11483 */
11484 if (modeset_pipes) {
11485 crtc->mode = *mode;
11486 /* mode_set/enable/disable functions rely on a correct pipe
11487 * config. */
11488 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
11489
11490 /*
11491 * Calculate and store various constants which
11492 * are later needed by vblank and swap-completion
11493 * timestamping. They are derived from true hwmode.
11494 */
11495 drm_calc_timestamping_constants(crtc,
11496 &pipe_config->base.adjusted_mode);
11497 }
11498
11499 /* Only after disabling all output pipelines that will be changed can we
11500 * update the the output configuration. */
11501 intel_modeset_update_state(dev, prepare_pipes);
11502
11503 modeset_update_crtc_power_domains(dev);
11504
11505 /* Set up the DPLL and any encoders state that needs to adjust or depend
11506 * on the DPLL.
11507 */
11508 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11509 struct drm_plane *primary = intel_crtc->base.primary;
11510 int vdisplay, hdisplay;
11511
11512 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11513 ret = primary->funcs->update_plane(primary, &intel_crtc->base,
11514 fb, 0, 0,
11515 hdisplay, vdisplay,
11516 x << 16, y << 16,
11517 hdisplay << 16, vdisplay << 16);
11518 }
11519
11520 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11521 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11522 update_scanline_offset(intel_crtc);
11523
11524 dev_priv->display.crtc_enable(&intel_crtc->base);
11525 }
11526
11527 /* FIXME: add subpixel order */
11528 done:
11529 if (ret && crtc->state->enable)
11530 crtc->mode = *saved_mode;
11531
11532 if (ret == 0 && pipe_config) {
11533 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11534
11535 /* The pipe_config will be freed with the atomic state, so
11536 * make a copy. */
11537 memcpy(crtc_state_copy, intel_crtc->config,
11538 sizeof *crtc_state_copy);
11539 intel_crtc->config = crtc_state_copy;
11540 intel_crtc->base.state = &crtc_state_copy->base;
11541
11542 if (modeset_pipes)
11543 intel_crtc->new_config = intel_crtc->config;
11544 } else {
11545 kfree(crtc_state_copy);
11546 }
11547
11548 kfree(saved_mode);
11549 return ret;
11550 }
11551
11552 static int intel_set_mode_pipes(struct drm_crtc *crtc,
11553 struct drm_display_mode *mode,
11554 int x, int y, struct drm_framebuffer *fb,
11555 struct intel_crtc_state *pipe_config,
11556 unsigned modeset_pipes,
11557 unsigned prepare_pipes,
11558 unsigned disable_pipes)
11559 {
11560 int ret;
11561
11562 ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11563 prepare_pipes, disable_pipes);
11564
11565 if (ret == 0)
11566 intel_modeset_check_state(crtc->dev);
11567
11568 return ret;
11569 }
11570
11571 static int intel_set_mode(struct drm_crtc *crtc,
11572 struct drm_display_mode *mode,
11573 int x, int y, struct drm_framebuffer *fb,
11574 struct drm_atomic_state *state)
11575 {
11576 struct intel_crtc_state *pipe_config;
11577 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11578 int ret = 0;
11579
11580 pipe_config = intel_modeset_compute_config(crtc, mode, fb, state,
11581 &modeset_pipes,
11582 &prepare_pipes,
11583 &disable_pipes);
11584
11585 if (IS_ERR(pipe_config)) {
11586 ret = PTR_ERR(pipe_config);
11587 goto out;
11588 }
11589
11590 ret = intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11591 modeset_pipes, prepare_pipes,
11592 disable_pipes);
11593 if (ret)
11594 goto out;
11595
11596 out:
11597 return ret;
11598 }
11599
11600 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11601 {
11602 struct drm_device *dev = crtc->dev;
11603 struct drm_atomic_state *state;
11604 struct intel_encoder *encoder;
11605 struct intel_connector *connector;
11606 struct drm_connector_state *connector_state;
11607
11608 state = drm_atomic_state_alloc(dev);
11609 if (!state) {
11610 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
11611 crtc->base.id);
11612 return;
11613 }
11614
11615 state->acquire_ctx = dev->mode_config.acquire_ctx;
11616
11617 /* The force restore path in the HW readout code relies on the staged
11618 * config still keeping the user requested config while the actual
11619 * state has been overwritten by the configuration read from HW. We
11620 * need to copy the staged config to the atomic state, otherwise the
11621 * mode set will just reapply the state the HW is already in. */
11622 for_each_intel_encoder(dev, encoder) {
11623 if (&encoder->new_crtc->base != crtc)
11624 continue;
11625
11626 for_each_intel_connector(dev, connector) {
11627 if (connector->new_encoder != encoder)
11628 continue;
11629
11630 connector_state = drm_atomic_get_connector_state(state, &connector->base);
11631 if (IS_ERR(connector_state)) {
11632 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
11633 connector->base.base.id,
11634 connector->base.name,
11635 PTR_ERR(connector_state));
11636 continue;
11637 }
11638
11639 connector_state->crtc = crtc;
11640 connector_state->best_encoder = &encoder->base;
11641 }
11642 }
11643
11644 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb,
11645 state);
11646
11647 drm_atomic_state_free(state);
11648 }
11649
11650 #undef for_each_intel_crtc_masked
11651
11652 static void intel_set_config_free(struct intel_set_config *config)
11653 {
11654 if (!config)
11655 return;
11656
11657 kfree(config->save_connector_encoders);
11658 kfree(config->save_encoder_crtcs);
11659 kfree(config->save_crtc_enabled);
11660 kfree(config);
11661 }
11662
11663 static int intel_set_config_save_state(struct drm_device *dev,
11664 struct intel_set_config *config)
11665 {
11666 struct drm_crtc *crtc;
11667 struct drm_encoder *encoder;
11668 struct drm_connector *connector;
11669 int count;
11670
11671 config->save_crtc_enabled =
11672 kcalloc(dev->mode_config.num_crtc,
11673 sizeof(bool), GFP_KERNEL);
11674 if (!config->save_crtc_enabled)
11675 return -ENOMEM;
11676
11677 config->save_encoder_crtcs =
11678 kcalloc(dev->mode_config.num_encoder,
11679 sizeof(struct drm_crtc *), GFP_KERNEL);
11680 if (!config->save_encoder_crtcs)
11681 return -ENOMEM;
11682
11683 config->save_connector_encoders =
11684 kcalloc(dev->mode_config.num_connector,
11685 sizeof(struct drm_encoder *), GFP_KERNEL);
11686 if (!config->save_connector_encoders)
11687 return -ENOMEM;
11688
11689 /* Copy data. Note that driver private data is not affected.
11690 * Should anything bad happen only the expected state is
11691 * restored, not the drivers personal bookkeeping.
11692 */
11693 count = 0;
11694 for_each_crtc(dev, crtc) {
11695 config->save_crtc_enabled[count++] = crtc->state->enable;
11696 }
11697
11698 count = 0;
11699 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11700 config->save_encoder_crtcs[count++] = encoder->crtc;
11701 }
11702
11703 count = 0;
11704 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11705 config->save_connector_encoders[count++] = connector->encoder;
11706 }
11707
11708 return 0;
11709 }
11710
11711 static void intel_set_config_restore_state(struct drm_device *dev,
11712 struct intel_set_config *config)
11713 {
11714 struct intel_crtc *crtc;
11715 struct intel_encoder *encoder;
11716 struct intel_connector *connector;
11717 int count;
11718
11719 count = 0;
11720 for_each_intel_crtc(dev, crtc) {
11721 crtc->new_enabled = config->save_crtc_enabled[count++];
11722
11723 if (crtc->new_enabled)
11724 crtc->new_config = crtc->config;
11725 else
11726 crtc->new_config = NULL;
11727 }
11728
11729 count = 0;
11730 for_each_intel_encoder(dev, encoder) {
11731 encoder->new_crtc =
11732 to_intel_crtc(config->save_encoder_crtcs[count++]);
11733 }
11734
11735 count = 0;
11736 for_each_intel_connector(dev, connector) {
11737 connector->new_encoder =
11738 to_intel_encoder(config->save_connector_encoders[count++]);
11739 }
11740 }
11741
11742 static bool
11743 is_crtc_connector_off(struct drm_mode_set *set)
11744 {
11745 int i;
11746
11747 if (set->num_connectors == 0)
11748 return false;
11749
11750 if (WARN_ON(set->connectors == NULL))
11751 return false;
11752
11753 for (i = 0; i < set->num_connectors; i++)
11754 if (set->connectors[i]->encoder &&
11755 set->connectors[i]->encoder->crtc == set->crtc &&
11756 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11757 return true;
11758
11759 return false;
11760 }
11761
11762 static void
11763 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11764 struct intel_set_config *config)
11765 {
11766
11767 /* We should be able to check here if the fb has the same properties
11768 * and then just flip_or_move it */
11769 if (is_crtc_connector_off(set)) {
11770 config->mode_changed = true;
11771 } else if (set->crtc->primary->fb != set->fb) {
11772 /*
11773 * If we have no fb, we can only flip as long as the crtc is
11774 * active, otherwise we need a full mode set. The crtc may
11775 * be active if we've only disabled the primary plane, or
11776 * in fastboot situations.
11777 */
11778 if (set->crtc->primary->fb == NULL) {
11779 struct intel_crtc *intel_crtc =
11780 to_intel_crtc(set->crtc);
11781
11782 if (intel_crtc->active) {
11783 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11784 config->fb_changed = true;
11785 } else {
11786 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11787 config->mode_changed = true;
11788 }
11789 } else if (set->fb == NULL) {
11790 config->mode_changed = true;
11791 } else if (set->fb->pixel_format !=
11792 set->crtc->primary->fb->pixel_format) {
11793 config->mode_changed = true;
11794 } else {
11795 config->fb_changed = true;
11796 }
11797 }
11798
11799 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11800 config->fb_changed = true;
11801
11802 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11803 DRM_DEBUG_KMS("modes are different, full mode set\n");
11804 drm_mode_debug_printmodeline(&set->crtc->mode);
11805 drm_mode_debug_printmodeline(set->mode);
11806 config->mode_changed = true;
11807 }
11808
11809 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11810 set->crtc->base.id, config->mode_changed, config->fb_changed);
11811 }
11812
11813 static int
11814 intel_modeset_stage_output_state(struct drm_device *dev,
11815 struct drm_mode_set *set,
11816 struct intel_set_config *config,
11817 struct drm_atomic_state *state)
11818 {
11819 struct intel_connector *connector;
11820 struct drm_connector_state *connector_state;
11821 struct intel_encoder *encoder;
11822 struct intel_crtc *crtc;
11823 int ro;
11824
11825 /* The upper layers ensure that we either disable a crtc or have a list
11826 * of connectors. For paranoia, double-check this. */
11827 WARN_ON(!set->fb && (set->num_connectors != 0));
11828 WARN_ON(set->fb && (set->num_connectors == 0));
11829
11830 for_each_intel_connector(dev, connector) {
11831 /* Otherwise traverse passed in connector list and get encoders
11832 * for them. */
11833 for (ro = 0; ro < set->num_connectors; ro++) {
11834 if (set->connectors[ro] == &connector->base) {
11835 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11836 break;
11837 }
11838 }
11839
11840 /* If we disable the crtc, disable all its connectors. Also, if
11841 * the connector is on the changing crtc but not on the new
11842 * connector list, disable it. */
11843 if ((!set->fb || ro == set->num_connectors) &&
11844 connector->base.encoder &&
11845 connector->base.encoder->crtc == set->crtc) {
11846 connector->new_encoder = NULL;
11847
11848 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11849 connector->base.base.id,
11850 connector->base.name);
11851 }
11852
11853
11854 if (&connector->new_encoder->base != connector->base.encoder) {
11855 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n",
11856 connector->base.base.id,
11857 connector->base.name);
11858 config->mode_changed = true;
11859 }
11860 }
11861 /* connector->new_encoder is now updated for all connectors. */
11862
11863 /* Update crtc of enabled connectors. */
11864 for_each_intel_connector(dev, connector) {
11865 struct drm_crtc *new_crtc;
11866
11867 if (!connector->new_encoder)
11868 continue;
11869
11870 new_crtc = connector->new_encoder->base.crtc;
11871
11872 for (ro = 0; ro < set->num_connectors; ro++) {
11873 if (set->connectors[ro] == &connector->base)
11874 new_crtc = set->crtc;
11875 }
11876
11877 /* Make sure the new CRTC will work with the encoder */
11878 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11879 new_crtc)) {
11880 return -EINVAL;
11881 }
11882 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11883
11884 connector_state =
11885 drm_atomic_get_connector_state(state, &connector->base);
11886 if (IS_ERR(connector_state))
11887 return PTR_ERR(connector_state);
11888
11889 connector_state->crtc = new_crtc;
11890 connector_state->best_encoder = &connector->new_encoder->base;
11891
11892 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11893 connector->base.base.id,
11894 connector->base.name,
11895 new_crtc->base.id);
11896 }
11897
11898 /* Check for any encoders that needs to be disabled. */
11899 for_each_intel_encoder(dev, encoder) {
11900 int num_connectors = 0;
11901 for_each_intel_connector(dev, connector) {
11902 if (connector->new_encoder == encoder) {
11903 WARN_ON(!connector->new_encoder->new_crtc);
11904 num_connectors++;
11905 }
11906 }
11907
11908 if (num_connectors == 0)
11909 encoder->new_crtc = NULL;
11910 else if (num_connectors > 1)
11911 return -EINVAL;
11912
11913 /* Only now check for crtc changes so we don't miss encoders
11914 * that will be disabled. */
11915 if (&encoder->new_crtc->base != encoder->base.crtc) {
11916 DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n",
11917 encoder->base.base.id,
11918 encoder->base.name);
11919 config->mode_changed = true;
11920 }
11921 }
11922 /* Now we've also updated encoder->new_crtc for all encoders. */
11923 for_each_intel_connector(dev, connector) {
11924 connector_state =
11925 drm_atomic_get_connector_state(state, &connector->base);
11926
11927 if (connector->new_encoder) {
11928 if (connector->new_encoder != connector->encoder)
11929 connector->encoder = connector->new_encoder;
11930 } else {
11931 connector_state->crtc = NULL;
11932 }
11933 }
11934 for_each_intel_crtc(dev, crtc) {
11935 crtc->new_enabled = false;
11936
11937 for_each_intel_encoder(dev, encoder) {
11938 if (encoder->new_crtc == crtc) {
11939 crtc->new_enabled = true;
11940 break;
11941 }
11942 }
11943
11944 if (crtc->new_enabled != crtc->base.state->enable) {
11945 DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n",
11946 crtc->base.base.id,
11947 crtc->new_enabled ? "en" : "dis");
11948 config->mode_changed = true;
11949 }
11950
11951 if (crtc->new_enabled)
11952 crtc->new_config = crtc->config;
11953 else
11954 crtc->new_config = NULL;
11955 }
11956
11957 return 0;
11958 }
11959
11960 static void disable_crtc_nofb(struct intel_crtc *crtc)
11961 {
11962 struct drm_device *dev = crtc->base.dev;
11963 struct intel_encoder *encoder;
11964 struct intel_connector *connector;
11965
11966 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11967 pipe_name(crtc->pipe));
11968
11969 for_each_intel_connector(dev, connector) {
11970 if (connector->new_encoder &&
11971 connector->new_encoder->new_crtc == crtc)
11972 connector->new_encoder = NULL;
11973 }
11974
11975 for_each_intel_encoder(dev, encoder) {
11976 if (encoder->new_crtc == crtc)
11977 encoder->new_crtc = NULL;
11978 }
11979
11980 crtc->new_enabled = false;
11981 crtc->new_config = NULL;
11982 }
11983
11984 static int intel_crtc_set_config(struct drm_mode_set *set)
11985 {
11986 struct drm_device *dev;
11987 struct drm_mode_set save_set;
11988 struct drm_atomic_state *state = NULL;
11989 struct intel_set_config *config;
11990 struct intel_crtc_state *pipe_config;
11991 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11992 int ret;
11993
11994 BUG_ON(!set);
11995 BUG_ON(!set->crtc);
11996 BUG_ON(!set->crtc->helper_private);
11997
11998 /* Enforce sane interface api - has been abused by the fb helper. */
11999 BUG_ON(!set->mode && set->fb);
12000 BUG_ON(set->fb && set->num_connectors == 0);
12001
12002 if (set->fb) {
12003 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
12004 set->crtc->base.id, set->fb->base.id,
12005 (int)set->num_connectors, set->x, set->y);
12006 } else {
12007 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
12008 }
12009
12010 dev = set->crtc->dev;
12011
12012 ret = -ENOMEM;
12013 config = kzalloc(sizeof(*config), GFP_KERNEL);
12014 if (!config)
12015 goto out_config;
12016
12017 ret = intel_set_config_save_state(dev, config);
12018 if (ret)
12019 goto out_config;
12020
12021 save_set.crtc = set->crtc;
12022 save_set.mode = &set->crtc->mode;
12023 save_set.x = set->crtc->x;
12024 save_set.y = set->crtc->y;
12025 save_set.fb = set->crtc->primary->fb;
12026
12027 /* Compute whether we need a full modeset, only an fb base update or no
12028 * change at all. In the future we might also check whether only the
12029 * mode changed, e.g. for LVDS where we only change the panel fitter in
12030 * such cases. */
12031 intel_set_config_compute_mode_changes(set, config);
12032
12033 state = drm_atomic_state_alloc(dev);
12034 if (!state) {
12035 ret = -ENOMEM;
12036 goto out_config;
12037 }
12038
12039 state->acquire_ctx = dev->mode_config.acquire_ctx;
12040
12041 ret = intel_modeset_stage_output_state(dev, set, config, state);
12042 if (ret)
12043 goto fail;
12044
12045 pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
12046 set->fb, state,
12047 &modeset_pipes,
12048 &prepare_pipes,
12049 &disable_pipes);
12050 if (IS_ERR(pipe_config)) {
12051 ret = PTR_ERR(pipe_config);
12052 goto fail;
12053 } else if (pipe_config) {
12054 if (pipe_config->has_audio !=
12055 to_intel_crtc(set->crtc)->config->has_audio)
12056 config->mode_changed = true;
12057
12058 /*
12059 * Note we have an issue here with infoframes: current code
12060 * only updates them on the full mode set path per hw
12061 * requirements. So here we should be checking for any
12062 * required changes and forcing a mode set.
12063 */
12064 }
12065
12066 intel_update_pipe_size(to_intel_crtc(set->crtc));
12067
12068 if (config->mode_changed) {
12069 ret = intel_set_mode_pipes(set->crtc, set->mode,
12070 set->x, set->y, set->fb, pipe_config,
12071 modeset_pipes, prepare_pipes,
12072 disable_pipes);
12073 } else if (config->fb_changed) {
12074 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
12075 struct drm_plane *primary = set->crtc->primary;
12076 int vdisplay, hdisplay;
12077
12078 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
12079 ret = primary->funcs->update_plane(primary, set->crtc, set->fb,
12080 0, 0, hdisplay, vdisplay,
12081 set->x << 16, set->y << 16,
12082 hdisplay << 16, vdisplay << 16);
12083
12084 /*
12085 * We need to make sure the primary plane is re-enabled if it
12086 * has previously been turned off.
12087 */
12088 if (!intel_crtc->primary_enabled && ret == 0) {
12089 WARN_ON(!intel_crtc->active);
12090 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
12091 }
12092
12093 /*
12094 * In the fastboot case this may be our only check of the
12095 * state after boot. It would be better to only do it on
12096 * the first update, but we don't have a nice way of doing that
12097 * (and really, set_config isn't used much for high freq page
12098 * flipping, so increasing its cost here shouldn't be a big
12099 * deal).
12100 */
12101 if (i915.fastboot && ret == 0)
12102 intel_modeset_check_state(set->crtc->dev);
12103 }
12104
12105 if (ret) {
12106 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
12107 set->crtc->base.id, ret);
12108 fail:
12109 intel_set_config_restore_state(dev, config);
12110
12111 drm_atomic_state_clear(state);
12112
12113 /*
12114 * HACK: if the pipe was on, but we didn't have a framebuffer,
12115 * force the pipe off to avoid oopsing in the modeset code
12116 * due to fb==NULL. This should only happen during boot since
12117 * we don't yet reconstruct the FB from the hardware state.
12118 */
12119 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
12120 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
12121
12122 /* Try to restore the config */
12123 if (config->mode_changed &&
12124 intel_set_mode(save_set.crtc, save_set.mode,
12125 save_set.x, save_set.y, save_set.fb,
12126 state))
12127 DRM_ERROR("failed to restore config after modeset failure\n");
12128 }
12129
12130 out_config:
12131 if (state)
12132 drm_atomic_state_free(state);
12133
12134 intel_set_config_free(config);
12135 return ret;
12136 }
12137
12138 static const struct drm_crtc_funcs intel_crtc_funcs = {
12139 .gamma_set = intel_crtc_gamma_set,
12140 .set_config = intel_crtc_set_config,
12141 .destroy = intel_crtc_destroy,
12142 .page_flip = intel_crtc_page_flip,
12143 .atomic_duplicate_state = intel_crtc_duplicate_state,
12144 .atomic_destroy_state = intel_crtc_destroy_state,
12145 };
12146
12147 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
12148 struct intel_shared_dpll *pll,
12149 struct intel_dpll_hw_state *hw_state)
12150 {
12151 uint32_t val;
12152
12153 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
12154 return false;
12155
12156 val = I915_READ(PCH_DPLL(pll->id));
12157 hw_state->dpll = val;
12158 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
12159 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
12160
12161 return val & DPLL_VCO_ENABLE;
12162 }
12163
12164 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
12165 struct intel_shared_dpll *pll)
12166 {
12167 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
12168 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
12169 }
12170
12171 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
12172 struct intel_shared_dpll *pll)
12173 {
12174 /* PCH refclock must be enabled first */
12175 ibx_assert_pch_refclk_enabled(dev_priv);
12176
12177 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
12178
12179 /* Wait for the clocks to stabilize. */
12180 POSTING_READ(PCH_DPLL(pll->id));
12181 udelay(150);
12182
12183 /* The pixel multiplier can only be updated once the
12184 * DPLL is enabled and the clocks are stable.
12185 *
12186 * So write it again.
12187 */
12188 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
12189 POSTING_READ(PCH_DPLL(pll->id));
12190 udelay(200);
12191 }
12192
12193 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
12194 struct intel_shared_dpll *pll)
12195 {
12196 struct drm_device *dev = dev_priv->dev;
12197 struct intel_crtc *crtc;
12198
12199 /* Make sure no transcoder isn't still depending on us. */
12200 for_each_intel_crtc(dev, crtc) {
12201 if (intel_crtc_to_shared_dpll(crtc) == pll)
12202 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
12203 }
12204
12205 I915_WRITE(PCH_DPLL(pll->id), 0);
12206 POSTING_READ(PCH_DPLL(pll->id));
12207 udelay(200);
12208 }
12209
12210 static char *ibx_pch_dpll_names[] = {
12211 "PCH DPLL A",
12212 "PCH DPLL B",
12213 };
12214
12215 static void ibx_pch_dpll_init(struct drm_device *dev)
12216 {
12217 struct drm_i915_private *dev_priv = dev->dev_private;
12218 int i;
12219
12220 dev_priv->num_shared_dpll = 2;
12221
12222 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12223 dev_priv->shared_dplls[i].id = i;
12224 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
12225 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
12226 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
12227 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
12228 dev_priv->shared_dplls[i].get_hw_state =
12229 ibx_pch_dpll_get_hw_state;
12230 }
12231 }
12232
12233 static void intel_shared_dpll_init(struct drm_device *dev)
12234 {
12235 struct drm_i915_private *dev_priv = dev->dev_private;
12236
12237 if (HAS_DDI(dev))
12238 intel_ddi_pll_init(dev);
12239 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
12240 ibx_pch_dpll_init(dev);
12241 else
12242 dev_priv->num_shared_dpll = 0;
12243
12244 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
12245 }
12246
12247 /**
12248 * intel_wm_need_update - Check whether watermarks need updating
12249 * @plane: drm plane
12250 * @state: new plane state
12251 *
12252 * Check current plane state versus the new one to determine whether
12253 * watermarks need to be recalculated.
12254 *
12255 * Returns true or false.
12256 */
12257 bool intel_wm_need_update(struct drm_plane *plane,
12258 struct drm_plane_state *state)
12259 {
12260 /* Update watermarks on tiling changes. */
12261 if (!plane->state->fb || !state->fb ||
12262 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
12263 plane->state->rotation != state->rotation)
12264 return true;
12265
12266 return false;
12267 }
12268
12269 /**
12270 * intel_prepare_plane_fb - Prepare fb for usage on plane
12271 * @plane: drm plane to prepare for
12272 * @fb: framebuffer to prepare for presentation
12273 *
12274 * Prepares a framebuffer for usage on a display plane. Generally this
12275 * involves pinning the underlying object and updating the frontbuffer tracking
12276 * bits. Some older platforms need special physical address handling for
12277 * cursor planes.
12278 *
12279 * Returns 0 on success, negative error code on failure.
12280 */
12281 int
12282 intel_prepare_plane_fb(struct drm_plane *plane,
12283 struct drm_framebuffer *fb,
12284 const struct drm_plane_state *new_state)
12285 {
12286 struct drm_device *dev = plane->dev;
12287 struct intel_plane *intel_plane = to_intel_plane(plane);
12288 enum pipe pipe = intel_plane->pipe;
12289 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12290 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
12291 unsigned frontbuffer_bits = 0;
12292 int ret = 0;
12293
12294 if (!obj)
12295 return 0;
12296
12297 switch (plane->type) {
12298 case DRM_PLANE_TYPE_PRIMARY:
12299 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
12300 break;
12301 case DRM_PLANE_TYPE_CURSOR:
12302 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
12303 break;
12304 case DRM_PLANE_TYPE_OVERLAY:
12305 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
12306 break;
12307 }
12308
12309 mutex_lock(&dev->struct_mutex);
12310
12311 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
12312 INTEL_INFO(dev)->cursor_needs_physical) {
12313 int align = IS_I830(dev) ? 16 * 1024 : 256;
12314 ret = i915_gem_object_attach_phys(obj, align);
12315 if (ret)
12316 DRM_DEBUG_KMS("failed to attach phys object\n");
12317 } else {
12318 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
12319 }
12320
12321 if (ret == 0)
12322 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
12323
12324 mutex_unlock(&dev->struct_mutex);
12325
12326 return ret;
12327 }
12328
12329 /**
12330 * intel_cleanup_plane_fb - Cleans up an fb after plane use
12331 * @plane: drm plane to clean up for
12332 * @fb: old framebuffer that was on plane
12333 *
12334 * Cleans up a framebuffer that has just been removed from a plane.
12335 */
12336 void
12337 intel_cleanup_plane_fb(struct drm_plane *plane,
12338 struct drm_framebuffer *fb,
12339 const struct drm_plane_state *old_state)
12340 {
12341 struct drm_device *dev = plane->dev;
12342 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12343
12344 if (WARN_ON(!obj))
12345 return;
12346
12347 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
12348 !INTEL_INFO(dev)->cursor_needs_physical) {
12349 mutex_lock(&dev->struct_mutex);
12350 intel_unpin_fb_obj(fb, old_state);
12351 mutex_unlock(&dev->struct_mutex);
12352 }
12353 }
12354
12355 static int
12356 intel_check_primary_plane(struct drm_plane *plane,
12357 struct intel_plane_state *state)
12358 {
12359 struct drm_device *dev = plane->dev;
12360 struct drm_i915_private *dev_priv = dev->dev_private;
12361 struct drm_crtc *crtc = state->base.crtc;
12362 struct intel_crtc *intel_crtc;
12363 struct drm_framebuffer *fb = state->base.fb;
12364 struct drm_rect *dest = &state->dst;
12365 struct drm_rect *src = &state->src;
12366 const struct drm_rect *clip = &state->clip;
12367 int ret;
12368
12369 crtc = crtc ? crtc : plane->crtc;
12370 intel_crtc = to_intel_crtc(crtc);
12371
12372 ret = drm_plane_helper_check_update(plane, crtc, fb,
12373 src, dest, clip,
12374 DRM_PLANE_HELPER_NO_SCALING,
12375 DRM_PLANE_HELPER_NO_SCALING,
12376 false, true, &state->visible);
12377 if (ret)
12378 return ret;
12379
12380 if (intel_crtc->active) {
12381 intel_crtc->atomic.wait_for_flips = true;
12382
12383 /*
12384 * FBC does not work on some platforms for rotated
12385 * planes, so disable it when rotation is not 0 and
12386 * update it when rotation is set back to 0.
12387 *
12388 * FIXME: This is redundant with the fbc update done in
12389 * the primary plane enable function except that that
12390 * one is done too late. We eventually need to unify
12391 * this.
12392 */
12393 if (intel_crtc->primary_enabled &&
12394 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
12395 dev_priv->fbc.crtc == intel_crtc &&
12396 state->base.rotation != BIT(DRM_ROTATE_0)) {
12397 intel_crtc->atomic.disable_fbc = true;
12398 }
12399
12400 if (state->visible) {
12401 /*
12402 * BDW signals flip done immediately if the plane
12403 * is disabled, even if the plane enable is already
12404 * armed to occur at the next vblank :(
12405 */
12406 if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
12407 intel_crtc->atomic.wait_vblank = true;
12408 }
12409
12410 intel_crtc->atomic.fb_bits |=
12411 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
12412
12413 intel_crtc->atomic.update_fbc = true;
12414
12415 if (intel_wm_need_update(plane, &state->base))
12416 intel_crtc->atomic.update_wm = true;
12417 }
12418
12419 return 0;
12420 }
12421
12422 static void
12423 intel_commit_primary_plane(struct drm_plane *plane,
12424 struct intel_plane_state *state)
12425 {
12426 struct drm_crtc *crtc = state->base.crtc;
12427 struct drm_framebuffer *fb = state->base.fb;
12428 struct drm_device *dev = plane->dev;
12429 struct drm_i915_private *dev_priv = dev->dev_private;
12430 struct intel_crtc *intel_crtc;
12431 struct drm_rect *src = &state->src;
12432
12433 crtc = crtc ? crtc : plane->crtc;
12434 intel_crtc = to_intel_crtc(crtc);
12435
12436 plane->fb = fb;
12437 crtc->x = src->x1 >> 16;
12438 crtc->y = src->y1 >> 16;
12439
12440 if (intel_crtc->active) {
12441 if (state->visible) {
12442 /* FIXME: kill this fastboot hack */
12443 intel_update_pipe_size(intel_crtc);
12444
12445 intel_crtc->primary_enabled = true;
12446
12447 dev_priv->display.update_primary_plane(crtc, plane->fb,
12448 crtc->x, crtc->y);
12449 } else {
12450 /*
12451 * If clipping results in a non-visible primary plane,
12452 * we'll disable the primary plane. Note that this is
12453 * a bit different than what happens if userspace
12454 * explicitly disables the plane by passing fb=0
12455 * because plane->fb still gets set and pinned.
12456 */
12457 intel_disable_primary_hw_plane(plane, crtc);
12458 }
12459 }
12460 }
12461
12462 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
12463 {
12464 struct drm_device *dev = crtc->dev;
12465 struct drm_i915_private *dev_priv = dev->dev_private;
12466 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12467 struct intel_plane *intel_plane;
12468 struct drm_plane *p;
12469 unsigned fb_bits = 0;
12470
12471 /* Track fb's for any planes being disabled */
12472 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
12473 intel_plane = to_intel_plane(p);
12474
12475 if (intel_crtc->atomic.disabled_planes &
12476 (1 << drm_plane_index(p))) {
12477 switch (p->type) {
12478 case DRM_PLANE_TYPE_PRIMARY:
12479 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
12480 break;
12481 case DRM_PLANE_TYPE_CURSOR:
12482 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
12483 break;
12484 case DRM_PLANE_TYPE_OVERLAY:
12485 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
12486 break;
12487 }
12488
12489 mutex_lock(&dev->struct_mutex);
12490 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
12491 mutex_unlock(&dev->struct_mutex);
12492 }
12493 }
12494
12495 if (intel_crtc->atomic.wait_for_flips)
12496 intel_crtc_wait_for_pending_flips(crtc);
12497
12498 if (intel_crtc->atomic.disable_fbc)
12499 intel_fbc_disable(dev);
12500
12501 if (intel_crtc->atomic.pre_disable_primary)
12502 intel_pre_disable_primary(crtc);
12503
12504 if (intel_crtc->atomic.update_wm)
12505 intel_update_watermarks(crtc);
12506
12507 intel_runtime_pm_get(dev_priv);
12508
12509 /* Perform vblank evasion around commit operation */
12510 if (intel_crtc->active)
12511 intel_crtc->atomic.evade =
12512 intel_pipe_update_start(intel_crtc,
12513 &intel_crtc->atomic.start_vbl_count);
12514 }
12515
12516 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
12517 {
12518 struct drm_device *dev = crtc->dev;
12519 struct drm_i915_private *dev_priv = dev->dev_private;
12520 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12521 struct drm_plane *p;
12522
12523 if (intel_crtc->atomic.evade)
12524 intel_pipe_update_end(intel_crtc,
12525 intel_crtc->atomic.start_vbl_count);
12526
12527 intel_runtime_pm_put(dev_priv);
12528
12529 if (intel_crtc->atomic.wait_vblank)
12530 intel_wait_for_vblank(dev, intel_crtc->pipe);
12531
12532 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
12533
12534 if (intel_crtc->atomic.update_fbc) {
12535 mutex_lock(&dev->struct_mutex);
12536 intel_fbc_update(dev);
12537 mutex_unlock(&dev->struct_mutex);
12538 }
12539
12540 if (intel_crtc->atomic.post_enable_primary)
12541 intel_post_enable_primary(crtc);
12542
12543 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
12544 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
12545 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
12546 false, false);
12547
12548 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
12549 }
12550
12551 /**
12552 * intel_plane_destroy - destroy a plane
12553 * @plane: plane to destroy
12554 *
12555 * Common destruction function for all types of planes (primary, cursor,
12556 * sprite).
12557 */
12558 void intel_plane_destroy(struct drm_plane *plane)
12559 {
12560 struct intel_plane *intel_plane = to_intel_plane(plane);
12561 drm_plane_cleanup(plane);
12562 kfree(intel_plane);
12563 }
12564
12565 const struct drm_plane_funcs intel_plane_funcs = {
12566 .update_plane = drm_plane_helper_update,
12567 .disable_plane = drm_plane_helper_disable,
12568 .destroy = intel_plane_destroy,
12569 .set_property = drm_atomic_helper_plane_set_property,
12570 .atomic_get_property = intel_plane_atomic_get_property,
12571 .atomic_set_property = intel_plane_atomic_set_property,
12572 .atomic_duplicate_state = intel_plane_duplicate_state,
12573 .atomic_destroy_state = intel_plane_destroy_state,
12574
12575 };
12576
12577 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
12578 int pipe)
12579 {
12580 struct intel_plane *primary;
12581 struct intel_plane_state *state;
12582 const uint32_t *intel_primary_formats;
12583 int num_formats;
12584
12585 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
12586 if (primary == NULL)
12587 return NULL;
12588
12589 state = intel_create_plane_state(&primary->base);
12590 if (!state) {
12591 kfree(primary);
12592 return NULL;
12593 }
12594 primary->base.state = &state->base;
12595
12596 primary->can_scale = false;
12597 primary->max_downscale = 1;
12598 primary->pipe = pipe;
12599 primary->plane = pipe;
12600 primary->check_plane = intel_check_primary_plane;
12601 primary->commit_plane = intel_commit_primary_plane;
12602 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
12603 primary->plane = !pipe;
12604
12605 if (INTEL_INFO(dev)->gen <= 3) {
12606 intel_primary_formats = intel_primary_formats_gen2;
12607 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
12608 } else {
12609 intel_primary_formats = intel_primary_formats_gen4;
12610 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
12611 }
12612
12613 drm_universal_plane_init(dev, &primary->base, 0,
12614 &intel_plane_funcs,
12615 intel_primary_formats, num_formats,
12616 DRM_PLANE_TYPE_PRIMARY);
12617
12618 if (INTEL_INFO(dev)->gen >= 4) {
12619 if (!dev->mode_config.rotation_property)
12620 dev->mode_config.rotation_property =
12621 drm_mode_create_rotation_property(dev,
12622 BIT(DRM_ROTATE_0) |
12623 BIT(DRM_ROTATE_180));
12624 if (dev->mode_config.rotation_property)
12625 drm_object_attach_property(&primary->base.base,
12626 dev->mode_config.rotation_property,
12627 state->base.rotation);
12628 }
12629
12630 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
12631
12632 return &primary->base;
12633 }
12634
12635 static int
12636 intel_check_cursor_plane(struct drm_plane *plane,
12637 struct intel_plane_state *state)
12638 {
12639 struct drm_crtc *crtc = state->base.crtc;
12640 struct drm_device *dev = plane->dev;
12641 struct drm_framebuffer *fb = state->base.fb;
12642 struct drm_rect *dest = &state->dst;
12643 struct drm_rect *src = &state->src;
12644 const struct drm_rect *clip = &state->clip;
12645 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12646 struct intel_crtc *intel_crtc;
12647 unsigned stride;
12648 int ret;
12649
12650 crtc = crtc ? crtc : plane->crtc;
12651 intel_crtc = to_intel_crtc(crtc);
12652
12653 ret = drm_plane_helper_check_update(plane, crtc, fb,
12654 src, dest, clip,
12655 DRM_PLANE_HELPER_NO_SCALING,
12656 DRM_PLANE_HELPER_NO_SCALING,
12657 true, true, &state->visible);
12658 if (ret)
12659 return ret;
12660
12661
12662 /* if we want to turn off the cursor ignore width and height */
12663 if (!obj)
12664 goto finish;
12665
12666 /* Check for which cursor types we support */
12667 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
12668 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
12669 state->base.crtc_w, state->base.crtc_h);
12670 return -EINVAL;
12671 }
12672
12673 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
12674 if (obj->base.size < stride * state->base.crtc_h) {
12675 DRM_DEBUG_KMS("buffer is too small\n");
12676 return -ENOMEM;
12677 }
12678
12679 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
12680 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12681 ret = -EINVAL;
12682 }
12683
12684 finish:
12685 if (intel_crtc->active) {
12686 if (plane->state->crtc_w != state->base.crtc_w)
12687 intel_crtc->atomic.update_wm = true;
12688
12689 intel_crtc->atomic.fb_bits |=
12690 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
12691 }
12692
12693 return ret;
12694 }
12695
12696 static void
12697 intel_commit_cursor_plane(struct drm_plane *plane,
12698 struct intel_plane_state *state)
12699 {
12700 struct drm_crtc *crtc = state->base.crtc;
12701 struct drm_device *dev = plane->dev;
12702 struct intel_crtc *intel_crtc;
12703 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
12704 uint32_t addr;
12705
12706 crtc = crtc ? crtc : plane->crtc;
12707 intel_crtc = to_intel_crtc(crtc);
12708
12709 plane->fb = state->base.fb;
12710 crtc->cursor_x = state->base.crtc_x;
12711 crtc->cursor_y = state->base.crtc_y;
12712
12713 if (intel_crtc->cursor_bo == obj)
12714 goto update;
12715
12716 if (!obj)
12717 addr = 0;
12718 else if (!INTEL_INFO(dev)->cursor_needs_physical)
12719 addr = i915_gem_obj_ggtt_offset(obj);
12720 else
12721 addr = obj->phys_handle->busaddr;
12722
12723 intel_crtc->cursor_addr = addr;
12724 intel_crtc->cursor_bo = obj;
12725 update:
12726
12727 if (intel_crtc->active)
12728 intel_crtc_update_cursor(crtc, state->visible);
12729 }
12730
12731 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12732 int pipe)
12733 {
12734 struct intel_plane *cursor;
12735 struct intel_plane_state *state;
12736
12737 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12738 if (cursor == NULL)
12739 return NULL;
12740
12741 state = intel_create_plane_state(&cursor->base);
12742 if (!state) {
12743 kfree(cursor);
12744 return NULL;
12745 }
12746 cursor->base.state = &state->base;
12747
12748 cursor->can_scale = false;
12749 cursor->max_downscale = 1;
12750 cursor->pipe = pipe;
12751 cursor->plane = pipe;
12752 cursor->check_plane = intel_check_cursor_plane;
12753 cursor->commit_plane = intel_commit_cursor_plane;
12754
12755 drm_universal_plane_init(dev, &cursor->base, 0,
12756 &intel_plane_funcs,
12757 intel_cursor_formats,
12758 ARRAY_SIZE(intel_cursor_formats),
12759 DRM_PLANE_TYPE_CURSOR);
12760
12761 if (INTEL_INFO(dev)->gen >= 4) {
12762 if (!dev->mode_config.rotation_property)
12763 dev->mode_config.rotation_property =
12764 drm_mode_create_rotation_property(dev,
12765 BIT(DRM_ROTATE_0) |
12766 BIT(DRM_ROTATE_180));
12767 if (dev->mode_config.rotation_property)
12768 drm_object_attach_property(&cursor->base.base,
12769 dev->mode_config.rotation_property,
12770 state->base.rotation);
12771 }
12772
12773 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
12774
12775 return &cursor->base;
12776 }
12777
12778 static void intel_crtc_init(struct drm_device *dev, int pipe)
12779 {
12780 struct drm_i915_private *dev_priv = dev->dev_private;
12781 struct intel_crtc *intel_crtc;
12782 struct intel_crtc_state *crtc_state = NULL;
12783 struct drm_plane *primary = NULL;
12784 struct drm_plane *cursor = NULL;
12785 int i, ret;
12786
12787 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12788 if (intel_crtc == NULL)
12789 return;
12790
12791 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
12792 if (!crtc_state)
12793 goto fail;
12794 intel_crtc_set_state(intel_crtc, crtc_state);
12795 crtc_state->base.crtc = &intel_crtc->base;
12796
12797 primary = intel_primary_plane_create(dev, pipe);
12798 if (!primary)
12799 goto fail;
12800
12801 cursor = intel_cursor_plane_create(dev, pipe);
12802 if (!cursor)
12803 goto fail;
12804
12805 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12806 cursor, &intel_crtc_funcs);
12807 if (ret)
12808 goto fail;
12809
12810 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12811 for (i = 0; i < 256; i++) {
12812 intel_crtc->lut_r[i] = i;
12813 intel_crtc->lut_g[i] = i;
12814 intel_crtc->lut_b[i] = i;
12815 }
12816
12817 /*
12818 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12819 * is hooked to pipe B. Hence we want plane A feeding pipe B.
12820 */
12821 intel_crtc->pipe = pipe;
12822 intel_crtc->plane = pipe;
12823 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12824 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12825 intel_crtc->plane = !pipe;
12826 }
12827
12828 intel_crtc->cursor_base = ~0;
12829 intel_crtc->cursor_cntl = ~0;
12830 intel_crtc->cursor_size = ~0;
12831
12832 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12833 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12834 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12835 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12836
12837 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
12838
12839 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12840
12841 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12842 return;
12843
12844 fail:
12845 if (primary)
12846 drm_plane_cleanup(primary);
12847 if (cursor)
12848 drm_plane_cleanup(cursor);
12849 kfree(crtc_state);
12850 kfree(intel_crtc);
12851 }
12852
12853 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12854 {
12855 struct drm_encoder *encoder = connector->base.encoder;
12856 struct drm_device *dev = connector->base.dev;
12857
12858 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12859
12860 if (!encoder || WARN_ON(!encoder->crtc))
12861 return INVALID_PIPE;
12862
12863 return to_intel_crtc(encoder->crtc)->pipe;
12864 }
12865
12866 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12867 struct drm_file *file)
12868 {
12869 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12870 struct drm_crtc *drmmode_crtc;
12871 struct intel_crtc *crtc;
12872
12873 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12874
12875 if (!drmmode_crtc) {
12876 DRM_ERROR("no such CRTC id\n");
12877 return -ENOENT;
12878 }
12879
12880 crtc = to_intel_crtc(drmmode_crtc);
12881 pipe_from_crtc_id->pipe = crtc->pipe;
12882
12883 return 0;
12884 }
12885
12886 static int intel_encoder_clones(struct intel_encoder *encoder)
12887 {
12888 struct drm_device *dev = encoder->base.dev;
12889 struct intel_encoder *source_encoder;
12890 int index_mask = 0;
12891 int entry = 0;
12892
12893 for_each_intel_encoder(dev, source_encoder) {
12894 if (encoders_cloneable(encoder, source_encoder))
12895 index_mask |= (1 << entry);
12896
12897 entry++;
12898 }
12899
12900 return index_mask;
12901 }
12902
12903 static bool has_edp_a(struct drm_device *dev)
12904 {
12905 struct drm_i915_private *dev_priv = dev->dev_private;
12906
12907 if (!IS_MOBILE(dev))
12908 return false;
12909
12910 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12911 return false;
12912
12913 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12914 return false;
12915
12916 return true;
12917 }
12918
12919 static bool intel_crt_present(struct drm_device *dev)
12920 {
12921 struct drm_i915_private *dev_priv = dev->dev_private;
12922
12923 if (INTEL_INFO(dev)->gen >= 9)
12924 return false;
12925
12926 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12927 return false;
12928
12929 if (IS_CHERRYVIEW(dev))
12930 return false;
12931
12932 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12933 return false;
12934
12935 return true;
12936 }
12937
12938 static void intel_setup_outputs(struct drm_device *dev)
12939 {
12940 struct drm_i915_private *dev_priv = dev->dev_private;
12941 struct intel_encoder *encoder;
12942 struct drm_connector *connector;
12943 bool dpd_is_edp = false;
12944
12945 intel_lvds_init(dev);
12946
12947 if (intel_crt_present(dev))
12948 intel_crt_init(dev);
12949
12950 if (HAS_DDI(dev)) {
12951 int found;
12952
12953 /*
12954 * Haswell uses DDI functions to detect digital outputs.
12955 * On SKL pre-D0 the strap isn't connected, so we assume
12956 * it's there.
12957 */
12958 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12959 /* WaIgnoreDDIAStrap: skl */
12960 if (found ||
12961 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
12962 intel_ddi_init(dev, PORT_A);
12963
12964 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12965 * register */
12966 found = I915_READ(SFUSE_STRAP);
12967
12968 if (found & SFUSE_STRAP_DDIB_DETECTED)
12969 intel_ddi_init(dev, PORT_B);
12970 if (found & SFUSE_STRAP_DDIC_DETECTED)
12971 intel_ddi_init(dev, PORT_C);
12972 if (found & SFUSE_STRAP_DDID_DETECTED)
12973 intel_ddi_init(dev, PORT_D);
12974 } else if (HAS_PCH_SPLIT(dev)) {
12975 int found;
12976 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12977
12978 if (has_edp_a(dev))
12979 intel_dp_init(dev, DP_A, PORT_A);
12980
12981 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12982 /* PCH SDVOB multiplex with HDMIB */
12983 found = intel_sdvo_init(dev, PCH_SDVOB, true);
12984 if (!found)
12985 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12986 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12987 intel_dp_init(dev, PCH_DP_B, PORT_B);
12988 }
12989
12990 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12991 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12992
12993 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12994 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12995
12996 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12997 intel_dp_init(dev, PCH_DP_C, PORT_C);
12998
12999 if (I915_READ(PCH_DP_D) & DP_DETECTED)
13000 intel_dp_init(dev, PCH_DP_D, PORT_D);
13001 } else if (IS_VALLEYVIEW(dev)) {
13002 /*
13003 * The DP_DETECTED bit is the latched state of the DDC
13004 * SDA pin at boot. However since eDP doesn't require DDC
13005 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13006 * eDP ports may have been muxed to an alternate function.
13007 * Thus we can't rely on the DP_DETECTED bit alone to detect
13008 * eDP ports. Consult the VBT as well as DP_DETECTED to
13009 * detect eDP ports.
13010 */
13011 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
13012 !intel_dp_is_edp(dev, PORT_B))
13013 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
13014 PORT_B);
13015 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
13016 intel_dp_is_edp(dev, PORT_B))
13017 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
13018
13019 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
13020 !intel_dp_is_edp(dev, PORT_C))
13021 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
13022 PORT_C);
13023 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
13024 intel_dp_is_edp(dev, PORT_C))
13025 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
13026
13027 if (IS_CHERRYVIEW(dev)) {
13028 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
13029 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
13030 PORT_D);
13031 /* eDP not supported on port D, so don't check VBT */
13032 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
13033 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
13034 }
13035
13036 intel_dsi_init(dev);
13037 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
13038 bool found = false;
13039
13040 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13041 DRM_DEBUG_KMS("probing SDVOB\n");
13042 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
13043 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
13044 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
13045 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
13046 }
13047
13048 if (!found && SUPPORTS_INTEGRATED_DP(dev))
13049 intel_dp_init(dev, DP_B, PORT_B);
13050 }
13051
13052 /* Before G4X SDVOC doesn't have its own detect register */
13053
13054 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13055 DRM_DEBUG_KMS("probing SDVOC\n");
13056 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
13057 }
13058
13059 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
13060
13061 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
13062 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
13063 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
13064 }
13065 if (SUPPORTS_INTEGRATED_DP(dev))
13066 intel_dp_init(dev, DP_C, PORT_C);
13067 }
13068
13069 if (SUPPORTS_INTEGRATED_DP(dev) &&
13070 (I915_READ(DP_D) & DP_DETECTED))
13071 intel_dp_init(dev, DP_D, PORT_D);
13072 } else if (IS_GEN2(dev))
13073 intel_dvo_init(dev);
13074
13075 if (SUPPORTS_TV(dev))
13076 intel_tv_init(dev);
13077
13078 /*
13079 * FIXME: We don't have full atomic support yet, but we want to be
13080 * able to enable/test plane updates via the atomic interface in the
13081 * meantime. However as soon as we flip DRIVER_ATOMIC on, the DRM core
13082 * will take some atomic codepaths to lookup properties during
13083 * drmModeGetConnector() that unconditionally dereference
13084 * connector->state.
13085 *
13086 * We create a dummy connector state here for each connector to ensure
13087 * the DRM core doesn't try to dereference a NULL connector->state.
13088 * The actual connector properties will never be updated or contain
13089 * useful information, but since we're doing this specifically for
13090 * testing/debug of the plane operations (and only when a specific
13091 * kernel module option is given), that shouldn't really matter.
13092 *
13093 * We are also relying on these states to convert the legacy mode set
13094 * to use a drm_atomic_state struct. The states are kept consistent
13095 * with actual state, so that it is safe to rely on that instead of
13096 * the staged config.
13097 *
13098 * Once atomic support for crtc's + connectors lands, this loop should
13099 * be removed since we'll be setting up real connector state, which
13100 * will contain Intel-specific properties.
13101 */
13102 list_for_each_entry(connector,
13103 &dev->mode_config.connector_list,
13104 head) {
13105 if (!WARN_ON(connector->state)) {
13106 connector->state = kzalloc(sizeof(*connector->state),
13107 GFP_KERNEL);
13108 }
13109 }
13110
13111 intel_psr_init(dev);
13112
13113 for_each_intel_encoder(dev, encoder) {
13114 encoder->base.possible_crtcs = encoder->crtc_mask;
13115 encoder->base.possible_clones =
13116 intel_encoder_clones(encoder);
13117 }
13118
13119 intel_init_pch_refclk(dev);
13120
13121 drm_helper_move_panel_connectors_to_head(dev);
13122 }
13123
13124 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
13125 {
13126 struct drm_device *dev = fb->dev;
13127 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13128
13129 drm_framebuffer_cleanup(fb);
13130 mutex_lock(&dev->struct_mutex);
13131 WARN_ON(!intel_fb->obj->framebuffer_references--);
13132 drm_gem_object_unreference(&intel_fb->obj->base);
13133 mutex_unlock(&dev->struct_mutex);
13134 kfree(intel_fb);
13135 }
13136
13137 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
13138 struct drm_file *file,
13139 unsigned int *handle)
13140 {
13141 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13142 struct drm_i915_gem_object *obj = intel_fb->obj;
13143
13144 return drm_gem_handle_create(file, &obj->base, handle);
13145 }
13146
13147 static const struct drm_framebuffer_funcs intel_fb_funcs = {
13148 .destroy = intel_user_framebuffer_destroy,
13149 .create_handle = intel_user_framebuffer_create_handle,
13150 };
13151
13152 static
13153 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
13154 uint32_t pixel_format)
13155 {
13156 u32 gen = INTEL_INFO(dev)->gen;
13157
13158 if (gen >= 9) {
13159 /* "The stride in bytes must not exceed the of the size of 8K
13160 * pixels and 32K bytes."
13161 */
13162 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
13163 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
13164 return 32*1024;
13165 } else if (gen >= 4) {
13166 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13167 return 16*1024;
13168 else
13169 return 32*1024;
13170 } else if (gen >= 3) {
13171 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13172 return 8*1024;
13173 else
13174 return 16*1024;
13175 } else {
13176 /* XXX DSPC is limited to 4k tiled */
13177 return 8*1024;
13178 }
13179 }
13180
13181 static int intel_framebuffer_init(struct drm_device *dev,
13182 struct intel_framebuffer *intel_fb,
13183 struct drm_mode_fb_cmd2 *mode_cmd,
13184 struct drm_i915_gem_object *obj)
13185 {
13186 unsigned int aligned_height;
13187 int ret;
13188 u32 pitch_limit, stride_alignment;
13189
13190 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
13191
13192 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
13193 /* Enforce that fb modifier and tiling mode match, but only for
13194 * X-tiled. This is needed for FBC. */
13195 if (!!(obj->tiling_mode == I915_TILING_X) !=
13196 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
13197 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
13198 return -EINVAL;
13199 }
13200 } else {
13201 if (obj->tiling_mode == I915_TILING_X)
13202 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
13203 else if (obj->tiling_mode == I915_TILING_Y) {
13204 DRM_DEBUG("No Y tiling for legacy addfb\n");
13205 return -EINVAL;
13206 }
13207 }
13208
13209 /* Passed in modifier sanity checking. */
13210 switch (mode_cmd->modifier[0]) {
13211 case I915_FORMAT_MOD_Y_TILED:
13212 case I915_FORMAT_MOD_Yf_TILED:
13213 if (INTEL_INFO(dev)->gen < 9) {
13214 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
13215 mode_cmd->modifier[0]);
13216 return -EINVAL;
13217 }
13218 case DRM_FORMAT_MOD_NONE:
13219 case I915_FORMAT_MOD_X_TILED:
13220 break;
13221 default:
13222 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
13223 mode_cmd->modifier[0]);
13224 return -EINVAL;
13225 }
13226
13227 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
13228 mode_cmd->pixel_format);
13229 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
13230 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
13231 mode_cmd->pitches[0], stride_alignment);
13232 return -EINVAL;
13233 }
13234
13235 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
13236 mode_cmd->pixel_format);
13237 if (mode_cmd->pitches[0] > pitch_limit) {
13238 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
13239 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
13240 "tiled" : "linear",
13241 mode_cmd->pitches[0], pitch_limit);
13242 return -EINVAL;
13243 }
13244
13245 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
13246 mode_cmd->pitches[0] != obj->stride) {
13247 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
13248 mode_cmd->pitches[0], obj->stride);
13249 return -EINVAL;
13250 }
13251
13252 /* Reject formats not supported by any plane early. */
13253 switch (mode_cmd->pixel_format) {
13254 case DRM_FORMAT_C8:
13255 case DRM_FORMAT_RGB565:
13256 case DRM_FORMAT_XRGB8888:
13257 case DRM_FORMAT_ARGB8888:
13258 break;
13259 case DRM_FORMAT_XRGB1555:
13260 case DRM_FORMAT_ARGB1555:
13261 if (INTEL_INFO(dev)->gen > 3) {
13262 DRM_DEBUG("unsupported pixel format: %s\n",
13263 drm_get_format_name(mode_cmd->pixel_format));
13264 return -EINVAL;
13265 }
13266 break;
13267 case DRM_FORMAT_XBGR8888:
13268 case DRM_FORMAT_ABGR8888:
13269 case DRM_FORMAT_XRGB2101010:
13270 case DRM_FORMAT_ARGB2101010:
13271 case DRM_FORMAT_XBGR2101010:
13272 case DRM_FORMAT_ABGR2101010:
13273 if (INTEL_INFO(dev)->gen < 4) {
13274 DRM_DEBUG("unsupported pixel format: %s\n",
13275 drm_get_format_name(mode_cmd->pixel_format));
13276 return -EINVAL;
13277 }
13278 break;
13279 case DRM_FORMAT_YUYV:
13280 case DRM_FORMAT_UYVY:
13281 case DRM_FORMAT_YVYU:
13282 case DRM_FORMAT_VYUY:
13283 if (INTEL_INFO(dev)->gen < 5) {
13284 DRM_DEBUG("unsupported pixel format: %s\n",
13285 drm_get_format_name(mode_cmd->pixel_format));
13286 return -EINVAL;
13287 }
13288 break;
13289 default:
13290 DRM_DEBUG("unsupported pixel format: %s\n",
13291 drm_get_format_name(mode_cmd->pixel_format));
13292 return -EINVAL;
13293 }
13294
13295 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
13296 if (mode_cmd->offsets[0] != 0)
13297 return -EINVAL;
13298
13299 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
13300 mode_cmd->pixel_format,
13301 mode_cmd->modifier[0]);
13302 /* FIXME drm helper for size checks (especially planar formats)? */
13303 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
13304 return -EINVAL;
13305
13306 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
13307 intel_fb->obj = obj;
13308 intel_fb->obj->framebuffer_references++;
13309
13310 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
13311 if (ret) {
13312 DRM_ERROR("framebuffer init failed %d\n", ret);
13313 return ret;
13314 }
13315
13316 return 0;
13317 }
13318
13319 static struct drm_framebuffer *
13320 intel_user_framebuffer_create(struct drm_device *dev,
13321 struct drm_file *filp,
13322 struct drm_mode_fb_cmd2 *mode_cmd)
13323 {
13324 struct drm_i915_gem_object *obj;
13325
13326 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
13327 mode_cmd->handles[0]));
13328 if (&obj->base == NULL)
13329 return ERR_PTR(-ENOENT);
13330
13331 return intel_framebuffer_create(dev, mode_cmd, obj);
13332 }
13333
13334 #ifndef CONFIG_DRM_I915_FBDEV
13335 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
13336 {
13337 }
13338 #endif
13339
13340 static const struct drm_mode_config_funcs intel_mode_funcs = {
13341 .fb_create = intel_user_framebuffer_create,
13342 .output_poll_changed = intel_fbdev_output_poll_changed,
13343 .atomic_check = intel_atomic_check,
13344 .atomic_commit = intel_atomic_commit,
13345 };
13346
13347 /* Set up chip specific display functions */
13348 static void intel_init_display(struct drm_device *dev)
13349 {
13350 struct drm_i915_private *dev_priv = dev->dev_private;
13351
13352 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
13353 dev_priv->display.find_dpll = g4x_find_best_dpll;
13354 else if (IS_CHERRYVIEW(dev))
13355 dev_priv->display.find_dpll = chv_find_best_dpll;
13356 else if (IS_VALLEYVIEW(dev))
13357 dev_priv->display.find_dpll = vlv_find_best_dpll;
13358 else if (IS_PINEVIEW(dev))
13359 dev_priv->display.find_dpll = pnv_find_best_dpll;
13360 else
13361 dev_priv->display.find_dpll = i9xx_find_best_dpll;
13362
13363 if (INTEL_INFO(dev)->gen >= 9) {
13364 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
13365 dev_priv->display.get_initial_plane_config =
13366 skylake_get_initial_plane_config;
13367 dev_priv->display.crtc_compute_clock =
13368 haswell_crtc_compute_clock;
13369 dev_priv->display.crtc_enable = haswell_crtc_enable;
13370 dev_priv->display.crtc_disable = haswell_crtc_disable;
13371 dev_priv->display.off = ironlake_crtc_off;
13372 dev_priv->display.update_primary_plane =
13373 skylake_update_primary_plane;
13374 } else if (HAS_DDI(dev)) {
13375 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
13376 dev_priv->display.get_initial_plane_config =
13377 ironlake_get_initial_plane_config;
13378 dev_priv->display.crtc_compute_clock =
13379 haswell_crtc_compute_clock;
13380 dev_priv->display.crtc_enable = haswell_crtc_enable;
13381 dev_priv->display.crtc_disable = haswell_crtc_disable;
13382 dev_priv->display.off = ironlake_crtc_off;
13383 dev_priv->display.update_primary_plane =
13384 ironlake_update_primary_plane;
13385 } else if (HAS_PCH_SPLIT(dev)) {
13386 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
13387 dev_priv->display.get_initial_plane_config =
13388 ironlake_get_initial_plane_config;
13389 dev_priv->display.crtc_compute_clock =
13390 ironlake_crtc_compute_clock;
13391 dev_priv->display.crtc_enable = ironlake_crtc_enable;
13392 dev_priv->display.crtc_disable = ironlake_crtc_disable;
13393 dev_priv->display.off = ironlake_crtc_off;
13394 dev_priv->display.update_primary_plane =
13395 ironlake_update_primary_plane;
13396 } else if (IS_VALLEYVIEW(dev)) {
13397 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13398 dev_priv->display.get_initial_plane_config =
13399 i9xx_get_initial_plane_config;
13400 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
13401 dev_priv->display.crtc_enable = valleyview_crtc_enable;
13402 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13403 dev_priv->display.off = i9xx_crtc_off;
13404 dev_priv->display.update_primary_plane =
13405 i9xx_update_primary_plane;
13406 } else {
13407 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13408 dev_priv->display.get_initial_plane_config =
13409 i9xx_get_initial_plane_config;
13410 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
13411 dev_priv->display.crtc_enable = i9xx_crtc_enable;
13412 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13413 dev_priv->display.off = i9xx_crtc_off;
13414 dev_priv->display.update_primary_plane =
13415 i9xx_update_primary_plane;
13416 }
13417
13418 /* Returns the core display clock speed */
13419 if (IS_VALLEYVIEW(dev))
13420 dev_priv->display.get_display_clock_speed =
13421 valleyview_get_display_clock_speed;
13422 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
13423 dev_priv->display.get_display_clock_speed =
13424 i945_get_display_clock_speed;
13425 else if (IS_I915G(dev))
13426 dev_priv->display.get_display_clock_speed =
13427 i915_get_display_clock_speed;
13428 else if (IS_I945GM(dev) || IS_845G(dev))
13429 dev_priv->display.get_display_clock_speed =
13430 i9xx_misc_get_display_clock_speed;
13431 else if (IS_PINEVIEW(dev))
13432 dev_priv->display.get_display_clock_speed =
13433 pnv_get_display_clock_speed;
13434 else if (IS_I915GM(dev))
13435 dev_priv->display.get_display_clock_speed =
13436 i915gm_get_display_clock_speed;
13437 else if (IS_I865G(dev))
13438 dev_priv->display.get_display_clock_speed =
13439 i865_get_display_clock_speed;
13440 else if (IS_I85X(dev))
13441 dev_priv->display.get_display_clock_speed =
13442 i855_get_display_clock_speed;
13443 else /* 852, 830 */
13444 dev_priv->display.get_display_clock_speed =
13445 i830_get_display_clock_speed;
13446
13447 if (IS_GEN5(dev)) {
13448 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
13449 } else if (IS_GEN6(dev)) {
13450 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
13451 } else if (IS_IVYBRIDGE(dev)) {
13452 /* FIXME: detect B0+ stepping and use auto training */
13453 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
13454 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
13455 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
13456 } else if (IS_VALLEYVIEW(dev)) {
13457 dev_priv->display.modeset_global_resources =
13458 valleyview_modeset_global_resources;
13459 }
13460
13461 switch (INTEL_INFO(dev)->gen) {
13462 case 2:
13463 dev_priv->display.queue_flip = intel_gen2_queue_flip;
13464 break;
13465
13466 case 3:
13467 dev_priv->display.queue_flip = intel_gen3_queue_flip;
13468 break;
13469
13470 case 4:
13471 case 5:
13472 dev_priv->display.queue_flip = intel_gen4_queue_flip;
13473 break;
13474
13475 case 6:
13476 dev_priv->display.queue_flip = intel_gen6_queue_flip;
13477 break;
13478 case 7:
13479 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
13480 dev_priv->display.queue_flip = intel_gen7_queue_flip;
13481 break;
13482 case 9:
13483 /* Drop through - unsupported since execlist only. */
13484 default:
13485 /* Default just returns -ENODEV to indicate unsupported */
13486 dev_priv->display.queue_flip = intel_default_queue_flip;
13487 }
13488
13489 intel_panel_init_backlight_funcs(dev);
13490
13491 mutex_init(&dev_priv->pps_mutex);
13492 }
13493
13494 /*
13495 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
13496 * resume, or other times. This quirk makes sure that's the case for
13497 * affected systems.
13498 */
13499 static void quirk_pipea_force(struct drm_device *dev)
13500 {
13501 struct drm_i915_private *dev_priv = dev->dev_private;
13502
13503 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
13504 DRM_INFO("applying pipe a force quirk\n");
13505 }
13506
13507 static void quirk_pipeb_force(struct drm_device *dev)
13508 {
13509 struct drm_i915_private *dev_priv = dev->dev_private;
13510
13511 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
13512 DRM_INFO("applying pipe b force quirk\n");
13513 }
13514
13515 /*
13516 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
13517 */
13518 static void quirk_ssc_force_disable(struct drm_device *dev)
13519 {
13520 struct drm_i915_private *dev_priv = dev->dev_private;
13521 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
13522 DRM_INFO("applying lvds SSC disable quirk\n");
13523 }
13524
13525 /*
13526 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
13527 * brightness value
13528 */
13529 static void quirk_invert_brightness(struct drm_device *dev)
13530 {
13531 struct drm_i915_private *dev_priv = dev->dev_private;
13532 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
13533 DRM_INFO("applying inverted panel brightness quirk\n");
13534 }
13535
13536 /* Some VBT's incorrectly indicate no backlight is present */
13537 static void quirk_backlight_present(struct drm_device *dev)
13538 {
13539 struct drm_i915_private *dev_priv = dev->dev_private;
13540 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
13541 DRM_INFO("applying backlight present quirk\n");
13542 }
13543
13544 struct intel_quirk {
13545 int device;
13546 int subsystem_vendor;
13547 int subsystem_device;
13548 void (*hook)(struct drm_device *dev);
13549 };
13550
13551 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
13552 struct intel_dmi_quirk {
13553 void (*hook)(struct drm_device *dev);
13554 const struct dmi_system_id (*dmi_id_list)[];
13555 };
13556
13557 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
13558 {
13559 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
13560 return 1;
13561 }
13562
13563 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
13564 {
13565 .dmi_id_list = &(const struct dmi_system_id[]) {
13566 {
13567 .callback = intel_dmi_reverse_brightness,
13568 .ident = "NCR Corporation",
13569 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
13570 DMI_MATCH(DMI_PRODUCT_NAME, ""),
13571 },
13572 },
13573 { } /* terminating entry */
13574 },
13575 .hook = quirk_invert_brightness,
13576 },
13577 };
13578
13579 static struct intel_quirk intel_quirks[] = {
13580 /* HP Mini needs pipe A force quirk (LP: #322104) */
13581 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
13582
13583 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
13584 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
13585
13586 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
13587 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
13588
13589 /* 830 needs to leave pipe A & dpll A up */
13590 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
13591
13592 /* 830 needs to leave pipe B & dpll B up */
13593 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
13594
13595 /* Lenovo U160 cannot use SSC on LVDS */
13596 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
13597
13598 /* Sony Vaio Y cannot use SSC on LVDS */
13599 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
13600
13601 /* Acer Aspire 5734Z must invert backlight brightness */
13602 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
13603
13604 /* Acer/eMachines G725 */
13605 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
13606
13607 /* Acer/eMachines e725 */
13608 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
13609
13610 /* Acer/Packard Bell NCL20 */
13611 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
13612
13613 /* Acer Aspire 4736Z */
13614 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
13615
13616 /* Acer Aspire 5336 */
13617 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
13618
13619 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13620 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
13621
13622 /* Acer C720 Chromebook (Core i3 4005U) */
13623 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
13624
13625 /* Apple Macbook 2,1 (Core 2 T7400) */
13626 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
13627
13628 /* Toshiba CB35 Chromebook (Celeron 2955U) */
13629 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
13630
13631 /* HP Chromebook 14 (Celeron 2955U) */
13632 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
13633
13634 /* Dell Chromebook 11 */
13635 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
13636 };
13637
13638 static void intel_init_quirks(struct drm_device *dev)
13639 {
13640 struct pci_dev *d = dev->pdev;
13641 int i;
13642
13643 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
13644 struct intel_quirk *q = &intel_quirks[i];
13645
13646 if (d->device == q->device &&
13647 (d->subsystem_vendor == q->subsystem_vendor ||
13648 q->subsystem_vendor == PCI_ANY_ID) &&
13649 (d->subsystem_device == q->subsystem_device ||
13650 q->subsystem_device == PCI_ANY_ID))
13651 q->hook(dev);
13652 }
13653 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
13654 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
13655 intel_dmi_quirks[i].hook(dev);
13656 }
13657 }
13658
13659 /* Disable the VGA plane that we never use */
13660 static void i915_disable_vga(struct drm_device *dev)
13661 {
13662 struct drm_i915_private *dev_priv = dev->dev_private;
13663 u8 sr1;
13664 u32 vga_reg = i915_vgacntrl_reg(dev);
13665
13666 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
13667 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
13668 outb(SR01, VGA_SR_INDEX);
13669 sr1 = inb(VGA_SR_DATA);
13670 outb(sr1 | 1<<5, VGA_SR_DATA);
13671 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
13672 udelay(300);
13673
13674 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
13675 POSTING_READ(vga_reg);
13676 }
13677
13678 void intel_modeset_init_hw(struct drm_device *dev)
13679 {
13680 intel_prepare_ddi(dev);
13681
13682 if (IS_VALLEYVIEW(dev))
13683 vlv_update_cdclk(dev);
13684
13685 intel_init_clock_gating(dev);
13686
13687 intel_enable_gt_powersave(dev);
13688 }
13689
13690 void intel_modeset_init(struct drm_device *dev)
13691 {
13692 struct drm_i915_private *dev_priv = dev->dev_private;
13693 int sprite, ret;
13694 enum pipe pipe;
13695 struct intel_crtc *crtc;
13696
13697 drm_mode_config_init(dev);
13698
13699 dev->mode_config.min_width = 0;
13700 dev->mode_config.min_height = 0;
13701
13702 dev->mode_config.preferred_depth = 24;
13703 dev->mode_config.prefer_shadow = 1;
13704
13705 dev->mode_config.allow_fb_modifiers = true;
13706
13707 dev->mode_config.funcs = &intel_mode_funcs;
13708
13709 intel_init_quirks(dev);
13710
13711 intel_init_pm(dev);
13712
13713 if (INTEL_INFO(dev)->num_pipes == 0)
13714 return;
13715
13716 intel_init_display(dev);
13717 intel_init_audio(dev);
13718
13719 if (IS_GEN2(dev)) {
13720 dev->mode_config.max_width = 2048;
13721 dev->mode_config.max_height = 2048;
13722 } else if (IS_GEN3(dev)) {
13723 dev->mode_config.max_width = 4096;
13724 dev->mode_config.max_height = 4096;
13725 } else {
13726 dev->mode_config.max_width = 8192;
13727 dev->mode_config.max_height = 8192;
13728 }
13729
13730 if (IS_845G(dev) || IS_I865G(dev)) {
13731 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13732 dev->mode_config.cursor_height = 1023;
13733 } else if (IS_GEN2(dev)) {
13734 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13735 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13736 } else {
13737 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13738 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13739 }
13740
13741 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
13742
13743 DRM_DEBUG_KMS("%d display pipe%s available.\n",
13744 INTEL_INFO(dev)->num_pipes,
13745 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
13746
13747 for_each_pipe(dev_priv, pipe) {
13748 intel_crtc_init(dev, pipe);
13749 for_each_sprite(dev_priv, pipe, sprite) {
13750 ret = intel_plane_init(dev, pipe, sprite);
13751 if (ret)
13752 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13753 pipe_name(pipe), sprite_name(pipe, sprite), ret);
13754 }
13755 }
13756
13757 intel_init_dpio(dev);
13758
13759 intel_shared_dpll_init(dev);
13760
13761 /* Just disable it once at startup */
13762 i915_disable_vga(dev);
13763 intel_setup_outputs(dev);
13764
13765 /* Just in case the BIOS is doing something questionable. */
13766 intel_fbc_disable(dev);
13767
13768 drm_modeset_lock_all(dev);
13769 intel_modeset_setup_hw_state(dev, false);
13770 drm_modeset_unlock_all(dev);
13771
13772 for_each_intel_crtc(dev, crtc) {
13773 if (!crtc->active)
13774 continue;
13775
13776 /*
13777 * Note that reserving the BIOS fb up front prevents us
13778 * from stuffing other stolen allocations like the ring
13779 * on top. This prevents some ugliness at boot time, and
13780 * can even allow for smooth boot transitions if the BIOS
13781 * fb is large enough for the active pipe configuration.
13782 */
13783 if (dev_priv->display.get_initial_plane_config) {
13784 dev_priv->display.get_initial_plane_config(crtc,
13785 &crtc->plane_config);
13786 /*
13787 * If the fb is shared between multiple heads, we'll
13788 * just get the first one.
13789 */
13790 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
13791 }
13792 }
13793 }
13794
13795 static void intel_enable_pipe_a(struct drm_device *dev)
13796 {
13797 struct intel_connector *connector;
13798 struct drm_connector *crt = NULL;
13799 struct intel_load_detect_pipe load_detect_temp;
13800 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13801
13802 /* We can't just switch on the pipe A, we need to set things up with a
13803 * proper mode and output configuration. As a gross hack, enable pipe A
13804 * by enabling the load detect pipe once. */
13805 for_each_intel_connector(dev, connector) {
13806 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13807 crt = &connector->base;
13808 break;
13809 }
13810 }
13811
13812 if (!crt)
13813 return;
13814
13815 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13816 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
13817 }
13818
13819 static bool
13820 intel_check_plane_mapping(struct intel_crtc *crtc)
13821 {
13822 struct drm_device *dev = crtc->base.dev;
13823 struct drm_i915_private *dev_priv = dev->dev_private;
13824 u32 reg, val;
13825
13826 if (INTEL_INFO(dev)->num_pipes == 1)
13827 return true;
13828
13829 reg = DSPCNTR(!crtc->plane);
13830 val = I915_READ(reg);
13831
13832 if ((val & DISPLAY_PLANE_ENABLE) &&
13833 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13834 return false;
13835
13836 return true;
13837 }
13838
13839 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13840 {
13841 struct drm_device *dev = crtc->base.dev;
13842 struct drm_i915_private *dev_priv = dev->dev_private;
13843 u32 reg;
13844
13845 /* Clear any frame start delays used for debugging left by the BIOS */
13846 reg = PIPECONF(crtc->config->cpu_transcoder);
13847 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13848
13849 /* restore vblank interrupts to correct state */
13850 drm_crtc_vblank_reset(&crtc->base);
13851 if (crtc->active) {
13852 update_scanline_offset(crtc);
13853 drm_crtc_vblank_on(&crtc->base);
13854 }
13855
13856 /* We need to sanitize the plane -> pipe mapping first because this will
13857 * disable the crtc (and hence change the state) if it is wrong. Note
13858 * that gen4+ has a fixed plane -> pipe mapping. */
13859 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13860 struct intel_connector *connector;
13861 bool plane;
13862
13863 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13864 crtc->base.base.id);
13865
13866 /* Pipe has the wrong plane attached and the plane is active.
13867 * Temporarily change the plane mapping and disable everything
13868 * ... */
13869 plane = crtc->plane;
13870 crtc->plane = !plane;
13871 crtc->primary_enabled = true;
13872 dev_priv->display.crtc_disable(&crtc->base);
13873 crtc->plane = plane;
13874
13875 /* ... and break all links. */
13876 for_each_intel_connector(dev, connector) {
13877 if (connector->encoder->base.crtc != &crtc->base)
13878 continue;
13879
13880 connector->base.dpms = DRM_MODE_DPMS_OFF;
13881 connector->base.encoder = NULL;
13882 }
13883 /* multiple connectors may have the same encoder:
13884 * handle them and break crtc link separately */
13885 for_each_intel_connector(dev, connector)
13886 if (connector->encoder->base.crtc == &crtc->base) {
13887 connector->encoder->base.crtc = NULL;
13888 connector->encoder->connectors_active = false;
13889 }
13890
13891 WARN_ON(crtc->active);
13892 crtc->base.state->enable = false;
13893 crtc->base.enabled = false;
13894 }
13895
13896 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13897 crtc->pipe == PIPE_A && !crtc->active) {
13898 /* BIOS forgot to enable pipe A, this mostly happens after
13899 * resume. Force-enable the pipe to fix this, the update_dpms
13900 * call below we restore the pipe to the right state, but leave
13901 * the required bits on. */
13902 intel_enable_pipe_a(dev);
13903 }
13904
13905 /* Adjust the state of the output pipe according to whether we
13906 * have active connectors/encoders. */
13907 intel_crtc_update_dpms(&crtc->base);
13908
13909 if (crtc->active != crtc->base.state->enable) {
13910 struct intel_encoder *encoder;
13911
13912 /* This can happen either due to bugs in the get_hw_state
13913 * functions or because the pipe is force-enabled due to the
13914 * pipe A quirk. */
13915 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13916 crtc->base.base.id,
13917 crtc->base.state->enable ? "enabled" : "disabled",
13918 crtc->active ? "enabled" : "disabled");
13919
13920 crtc->base.state->enable = crtc->active;
13921 crtc->base.enabled = crtc->active;
13922
13923 /* Because we only establish the connector -> encoder ->
13924 * crtc links if something is active, this means the
13925 * crtc is now deactivated. Break the links. connector
13926 * -> encoder links are only establish when things are
13927 * actually up, hence no need to break them. */
13928 WARN_ON(crtc->active);
13929
13930 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13931 WARN_ON(encoder->connectors_active);
13932 encoder->base.crtc = NULL;
13933 }
13934 }
13935
13936 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13937 /*
13938 * We start out with underrun reporting disabled to avoid races.
13939 * For correct bookkeeping mark this on active crtcs.
13940 *
13941 * Also on gmch platforms we dont have any hardware bits to
13942 * disable the underrun reporting. Which means we need to start
13943 * out with underrun reporting disabled also on inactive pipes,
13944 * since otherwise we'll complain about the garbage we read when
13945 * e.g. coming up after runtime pm.
13946 *
13947 * No protection against concurrent access is required - at
13948 * worst a fifo underrun happens which also sets this to false.
13949 */
13950 crtc->cpu_fifo_underrun_disabled = true;
13951 crtc->pch_fifo_underrun_disabled = true;
13952 }
13953 }
13954
13955 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13956 {
13957 struct intel_connector *connector;
13958 struct drm_device *dev = encoder->base.dev;
13959
13960 /* We need to check both for a crtc link (meaning that the
13961 * encoder is active and trying to read from a pipe) and the
13962 * pipe itself being active. */
13963 bool has_active_crtc = encoder->base.crtc &&
13964 to_intel_crtc(encoder->base.crtc)->active;
13965
13966 if (encoder->connectors_active && !has_active_crtc) {
13967 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13968 encoder->base.base.id,
13969 encoder->base.name);
13970
13971 /* Connector is active, but has no active pipe. This is
13972 * fallout from our resume register restoring. Disable
13973 * the encoder manually again. */
13974 if (encoder->base.crtc) {
13975 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13976 encoder->base.base.id,
13977 encoder->base.name);
13978 encoder->disable(encoder);
13979 if (encoder->post_disable)
13980 encoder->post_disable(encoder);
13981 }
13982 encoder->base.crtc = NULL;
13983 encoder->connectors_active = false;
13984
13985 /* Inconsistent output/port/pipe state happens presumably due to
13986 * a bug in one of the get_hw_state functions. Or someplace else
13987 * in our code, like the register restore mess on resume. Clamp
13988 * things to off as a safer default. */
13989 for_each_intel_connector(dev, connector) {
13990 if (connector->encoder != encoder)
13991 continue;
13992 connector->base.dpms = DRM_MODE_DPMS_OFF;
13993 connector->base.encoder = NULL;
13994 }
13995 }
13996 /* Enabled encoders without active connectors will be fixed in
13997 * the crtc fixup. */
13998 }
13999
14000 void i915_redisable_vga_power_on(struct drm_device *dev)
14001 {
14002 struct drm_i915_private *dev_priv = dev->dev_private;
14003 u32 vga_reg = i915_vgacntrl_reg(dev);
14004
14005 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14006 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14007 i915_disable_vga(dev);
14008 }
14009 }
14010
14011 void i915_redisable_vga(struct drm_device *dev)
14012 {
14013 struct drm_i915_private *dev_priv = dev->dev_private;
14014
14015 /* This function can be called both from intel_modeset_setup_hw_state or
14016 * at a very early point in our resume sequence, where the power well
14017 * structures are not yet restored. Since this function is at a very
14018 * paranoid "someone might have enabled VGA while we were not looking"
14019 * level, just check if the power well is enabled instead of trying to
14020 * follow the "don't touch the power well if we don't need it" policy
14021 * the rest of the driver uses. */
14022 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
14023 return;
14024
14025 i915_redisable_vga_power_on(dev);
14026 }
14027
14028 static bool primary_get_hw_state(struct intel_crtc *crtc)
14029 {
14030 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
14031
14032 if (!crtc->active)
14033 return false;
14034
14035 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
14036 }
14037
14038 static void intel_modeset_readout_hw_state(struct drm_device *dev)
14039 {
14040 struct drm_i915_private *dev_priv = dev->dev_private;
14041 enum pipe pipe;
14042 struct intel_crtc *crtc;
14043 struct intel_encoder *encoder;
14044 struct intel_connector *connector;
14045 int i;
14046
14047 for_each_intel_crtc(dev, crtc) {
14048 memset(crtc->config, 0, sizeof(*crtc->config));
14049
14050 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
14051
14052 crtc->active = dev_priv->display.get_pipe_config(crtc,
14053 crtc->config);
14054
14055 crtc->base.state->enable = crtc->active;
14056 crtc->base.enabled = crtc->active;
14057 crtc->primary_enabled = primary_get_hw_state(crtc);
14058
14059 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
14060 crtc->base.base.id,
14061 crtc->active ? "enabled" : "disabled");
14062 }
14063
14064 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14065 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14066
14067 pll->on = pll->get_hw_state(dev_priv, pll,
14068 &pll->config.hw_state);
14069 pll->active = 0;
14070 pll->config.crtc_mask = 0;
14071 for_each_intel_crtc(dev, crtc) {
14072 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
14073 pll->active++;
14074 pll->config.crtc_mask |= 1 << crtc->pipe;
14075 }
14076 }
14077
14078 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
14079 pll->name, pll->config.crtc_mask, pll->on);
14080
14081 if (pll->config.crtc_mask)
14082 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
14083 }
14084
14085 for_each_intel_encoder(dev, encoder) {
14086 pipe = 0;
14087
14088 if (encoder->get_hw_state(encoder, &pipe)) {
14089 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14090 encoder->base.crtc = &crtc->base;
14091 encoder->get_config(encoder, crtc->config);
14092 } else {
14093 encoder->base.crtc = NULL;
14094 }
14095
14096 encoder->connectors_active = false;
14097 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
14098 encoder->base.base.id,
14099 encoder->base.name,
14100 encoder->base.crtc ? "enabled" : "disabled",
14101 pipe_name(pipe));
14102 }
14103
14104 for_each_intel_connector(dev, connector) {
14105 if (connector->get_hw_state(connector)) {
14106 connector->base.dpms = DRM_MODE_DPMS_ON;
14107 connector->encoder->connectors_active = true;
14108 connector->base.encoder = &connector->encoder->base;
14109 } else {
14110 connector->base.dpms = DRM_MODE_DPMS_OFF;
14111 connector->base.encoder = NULL;
14112 }
14113 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
14114 connector->base.base.id,
14115 connector->base.name,
14116 connector->base.encoder ? "enabled" : "disabled");
14117 }
14118 }
14119
14120 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
14121 * and i915 state tracking structures. */
14122 void intel_modeset_setup_hw_state(struct drm_device *dev,
14123 bool force_restore)
14124 {
14125 struct drm_i915_private *dev_priv = dev->dev_private;
14126 enum pipe pipe;
14127 struct intel_crtc *crtc;
14128 struct intel_encoder *encoder;
14129 int i;
14130
14131 intel_modeset_readout_hw_state(dev);
14132
14133 /*
14134 * Now that we have the config, copy it to each CRTC struct
14135 * Note that this could go away if we move to using crtc_config
14136 * checking everywhere.
14137 */
14138 for_each_intel_crtc(dev, crtc) {
14139 if (crtc->active && i915.fastboot) {
14140 intel_mode_from_pipe_config(&crtc->base.mode,
14141 crtc->config);
14142 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
14143 crtc->base.base.id);
14144 drm_mode_debug_printmodeline(&crtc->base.mode);
14145 }
14146 }
14147
14148 /* HW state is read out, now we need to sanitize this mess. */
14149 for_each_intel_encoder(dev, encoder) {
14150 intel_sanitize_encoder(encoder);
14151 }
14152
14153 for_each_pipe(dev_priv, pipe) {
14154 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14155 intel_sanitize_crtc(crtc);
14156 intel_dump_pipe_config(crtc, crtc->config,
14157 "[setup_hw_state]");
14158 }
14159
14160 intel_modeset_update_connector_atomic_state(dev);
14161
14162 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14163 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14164
14165 if (!pll->on || pll->active)
14166 continue;
14167
14168 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
14169
14170 pll->disable(dev_priv, pll);
14171 pll->on = false;
14172 }
14173
14174 if (IS_GEN9(dev))
14175 skl_wm_get_hw_state(dev);
14176 else if (HAS_PCH_SPLIT(dev))
14177 ilk_wm_get_hw_state(dev);
14178
14179 if (force_restore) {
14180 i915_redisable_vga(dev);
14181
14182 /*
14183 * We need to use raw interfaces for restoring state to avoid
14184 * checking (bogus) intermediate states.
14185 */
14186 for_each_pipe(dev_priv, pipe) {
14187 struct drm_crtc *crtc =
14188 dev_priv->pipe_to_crtc_mapping[pipe];
14189
14190 intel_crtc_restore_mode(crtc);
14191 }
14192 } else {
14193 intel_modeset_update_staged_output_state(dev);
14194 }
14195
14196 intel_modeset_check_state(dev);
14197 }
14198
14199 void intel_modeset_gem_init(struct drm_device *dev)
14200 {
14201 struct drm_i915_private *dev_priv = dev->dev_private;
14202 struct drm_crtc *c;
14203 struct drm_i915_gem_object *obj;
14204
14205 mutex_lock(&dev->struct_mutex);
14206 intel_init_gt_powersave(dev);
14207 mutex_unlock(&dev->struct_mutex);
14208
14209 /*
14210 * There may be no VBT; and if the BIOS enabled SSC we can
14211 * just keep using it to avoid unnecessary flicker. Whereas if the
14212 * BIOS isn't using it, don't assume it will work even if the VBT
14213 * indicates as much.
14214 */
14215 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
14216 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14217 DREF_SSC1_ENABLE);
14218
14219 intel_modeset_init_hw(dev);
14220
14221 intel_setup_overlay(dev);
14222
14223 /*
14224 * Make sure any fbs we allocated at startup are properly
14225 * pinned & fenced. When we do the allocation it's too early
14226 * for this.
14227 */
14228 mutex_lock(&dev->struct_mutex);
14229 for_each_crtc(dev, c) {
14230 obj = intel_fb_obj(c->primary->fb);
14231 if (obj == NULL)
14232 continue;
14233
14234 if (intel_pin_and_fence_fb_obj(c->primary,
14235 c->primary->fb,
14236 c->primary->state,
14237 NULL)) {
14238 DRM_ERROR("failed to pin boot fb on pipe %d\n",
14239 to_intel_crtc(c)->pipe);
14240 drm_framebuffer_unreference(c->primary->fb);
14241 c->primary->fb = NULL;
14242 update_state_fb(c->primary);
14243 }
14244 }
14245 mutex_unlock(&dev->struct_mutex);
14246
14247 intel_backlight_register(dev);
14248 }
14249
14250 void intel_connector_unregister(struct intel_connector *intel_connector)
14251 {
14252 struct drm_connector *connector = &intel_connector->base;
14253
14254 intel_panel_destroy_backlight(connector);
14255 drm_connector_unregister(connector);
14256 }
14257
14258 void intel_modeset_cleanup(struct drm_device *dev)
14259 {
14260 struct drm_i915_private *dev_priv = dev->dev_private;
14261 struct drm_connector *connector;
14262
14263 intel_disable_gt_powersave(dev);
14264
14265 intel_backlight_unregister(dev);
14266
14267 /*
14268 * Interrupts and polling as the first thing to avoid creating havoc.
14269 * Too much stuff here (turning of connectors, ...) would
14270 * experience fancy races otherwise.
14271 */
14272 intel_irq_uninstall(dev_priv);
14273
14274 /*
14275 * Due to the hpd irq storm handling the hotplug work can re-arm the
14276 * poll handlers. Hence disable polling after hpd handling is shut down.
14277 */
14278 drm_kms_helper_poll_fini(dev);
14279
14280 mutex_lock(&dev->struct_mutex);
14281
14282 intel_unregister_dsm_handler();
14283
14284 intel_fbc_disable(dev);
14285
14286 mutex_unlock(&dev->struct_mutex);
14287
14288 /* flush any delayed tasks or pending work */
14289 flush_scheduled_work();
14290
14291 /* destroy the backlight and sysfs files before encoders/connectors */
14292 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
14293 struct intel_connector *intel_connector;
14294
14295 intel_connector = to_intel_connector(connector);
14296 intel_connector->unregister(intel_connector);
14297 }
14298
14299 drm_mode_config_cleanup(dev);
14300
14301 intel_cleanup_overlay(dev);
14302
14303 mutex_lock(&dev->struct_mutex);
14304 intel_cleanup_gt_powersave(dev);
14305 mutex_unlock(&dev->struct_mutex);
14306 }
14307
14308 /*
14309 * Return which encoder is currently attached for connector.
14310 */
14311 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
14312 {
14313 return &intel_attached_encoder(connector)->base;
14314 }
14315
14316 void intel_connector_attach_encoder(struct intel_connector *connector,
14317 struct intel_encoder *encoder)
14318 {
14319 connector->encoder = encoder;
14320 drm_mode_connector_attach_encoder(&connector->base,
14321 &encoder->base);
14322 }
14323
14324 /*
14325 * set vga decode state - true == enable VGA decode
14326 */
14327 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
14328 {
14329 struct drm_i915_private *dev_priv = dev->dev_private;
14330 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
14331 u16 gmch_ctrl;
14332
14333 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
14334 DRM_ERROR("failed to read control word\n");
14335 return -EIO;
14336 }
14337
14338 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
14339 return 0;
14340
14341 if (state)
14342 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
14343 else
14344 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
14345
14346 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
14347 DRM_ERROR("failed to write control word\n");
14348 return -EIO;
14349 }
14350
14351 return 0;
14352 }
14353
14354 struct intel_display_error_state {
14355
14356 u32 power_well_driver;
14357
14358 int num_transcoders;
14359
14360 struct intel_cursor_error_state {
14361 u32 control;
14362 u32 position;
14363 u32 base;
14364 u32 size;
14365 } cursor[I915_MAX_PIPES];
14366
14367 struct intel_pipe_error_state {
14368 bool power_domain_on;
14369 u32 source;
14370 u32 stat;
14371 } pipe[I915_MAX_PIPES];
14372
14373 struct intel_plane_error_state {
14374 u32 control;
14375 u32 stride;
14376 u32 size;
14377 u32 pos;
14378 u32 addr;
14379 u32 surface;
14380 u32 tile_offset;
14381 } plane[I915_MAX_PIPES];
14382
14383 struct intel_transcoder_error_state {
14384 bool power_domain_on;
14385 enum transcoder cpu_transcoder;
14386
14387 u32 conf;
14388
14389 u32 htotal;
14390 u32 hblank;
14391 u32 hsync;
14392 u32 vtotal;
14393 u32 vblank;
14394 u32 vsync;
14395 } transcoder[4];
14396 };
14397
14398 struct intel_display_error_state *
14399 intel_display_capture_error_state(struct drm_device *dev)
14400 {
14401 struct drm_i915_private *dev_priv = dev->dev_private;
14402 struct intel_display_error_state *error;
14403 int transcoders[] = {
14404 TRANSCODER_A,
14405 TRANSCODER_B,
14406 TRANSCODER_C,
14407 TRANSCODER_EDP,
14408 };
14409 int i;
14410
14411 if (INTEL_INFO(dev)->num_pipes == 0)
14412 return NULL;
14413
14414 error = kzalloc(sizeof(*error), GFP_ATOMIC);
14415 if (error == NULL)
14416 return NULL;
14417
14418 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
14419 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
14420
14421 for_each_pipe(dev_priv, i) {
14422 error->pipe[i].power_domain_on =
14423 __intel_display_power_is_enabled(dev_priv,
14424 POWER_DOMAIN_PIPE(i));
14425 if (!error->pipe[i].power_domain_on)
14426 continue;
14427
14428 error->cursor[i].control = I915_READ(CURCNTR(i));
14429 error->cursor[i].position = I915_READ(CURPOS(i));
14430 error->cursor[i].base = I915_READ(CURBASE(i));
14431
14432 error->plane[i].control = I915_READ(DSPCNTR(i));
14433 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
14434 if (INTEL_INFO(dev)->gen <= 3) {
14435 error->plane[i].size = I915_READ(DSPSIZE(i));
14436 error->plane[i].pos = I915_READ(DSPPOS(i));
14437 }
14438 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14439 error->plane[i].addr = I915_READ(DSPADDR(i));
14440 if (INTEL_INFO(dev)->gen >= 4) {
14441 error->plane[i].surface = I915_READ(DSPSURF(i));
14442 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
14443 }
14444
14445 error->pipe[i].source = I915_READ(PIPESRC(i));
14446
14447 if (HAS_GMCH_DISPLAY(dev))
14448 error->pipe[i].stat = I915_READ(PIPESTAT(i));
14449 }
14450
14451 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
14452 if (HAS_DDI(dev_priv->dev))
14453 error->num_transcoders++; /* Account for eDP. */
14454
14455 for (i = 0; i < error->num_transcoders; i++) {
14456 enum transcoder cpu_transcoder = transcoders[i];
14457
14458 error->transcoder[i].power_domain_on =
14459 __intel_display_power_is_enabled(dev_priv,
14460 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
14461 if (!error->transcoder[i].power_domain_on)
14462 continue;
14463
14464 error->transcoder[i].cpu_transcoder = cpu_transcoder;
14465
14466 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
14467 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
14468 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
14469 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
14470 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
14471 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
14472 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
14473 }
14474
14475 return error;
14476 }
14477
14478 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
14479
14480 void
14481 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
14482 struct drm_device *dev,
14483 struct intel_display_error_state *error)
14484 {
14485 struct drm_i915_private *dev_priv = dev->dev_private;
14486 int i;
14487
14488 if (!error)
14489 return;
14490
14491 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
14492 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
14493 err_printf(m, "PWR_WELL_CTL2: %08x\n",
14494 error->power_well_driver);
14495 for_each_pipe(dev_priv, i) {
14496 err_printf(m, "Pipe [%d]:\n", i);
14497 err_printf(m, " Power: %s\n",
14498 error->pipe[i].power_domain_on ? "on" : "off");
14499 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
14500 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
14501
14502 err_printf(m, "Plane [%d]:\n", i);
14503 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
14504 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
14505 if (INTEL_INFO(dev)->gen <= 3) {
14506 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
14507 err_printf(m, " POS: %08x\n", error->plane[i].pos);
14508 }
14509 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14510 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
14511 if (INTEL_INFO(dev)->gen >= 4) {
14512 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
14513 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
14514 }
14515
14516 err_printf(m, "Cursor [%d]:\n", i);
14517 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
14518 err_printf(m, " POS: %08x\n", error->cursor[i].position);
14519 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
14520 }
14521
14522 for (i = 0; i < error->num_transcoders; i++) {
14523 err_printf(m, "CPU transcoder: %c\n",
14524 transcoder_name(error->transcoder[i].cpu_transcoder));
14525 err_printf(m, " Power: %s\n",
14526 error->transcoder[i].power_domain_on ? "on" : "off");
14527 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
14528 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
14529 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
14530 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
14531 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
14532 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
14533 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
14534 }
14535 }
14536
14537 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
14538 {
14539 struct intel_crtc *crtc;
14540
14541 for_each_intel_crtc(dev, crtc) {
14542 struct intel_unpin_work *work;
14543
14544 spin_lock_irq(&dev->event_lock);
14545
14546 work = crtc->unpin_work;
14547
14548 if (work && work->event &&
14549 work->event->base.file_priv == file) {
14550 kfree(work->event);
14551 work->event = NULL;
14552 }
14553
14554 spin_unlock_irq(&dev->event_lock);
14555 }
14556 }
Linux kernel - Deliverables
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