2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
);
45 static void intel_increase_pllclock(struct drm_crtc
*crtc
);
46 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
48 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
49 struct intel_crtc_config
*pipe_config
);
50 static void ironlake_crtc_clock_get(struct intel_crtc
*crtc
,
51 struct intel_crtc_config
*pipe_config
);
62 #define INTEL_P2_NUM 2
63 typedef struct intel_limit intel_limit_t
;
65 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
70 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
73 intel_pch_rawclk(struct drm_device
*dev
)
75 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
77 WARN_ON(!HAS_PCH_SPLIT(dev
));
79 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
82 static inline u32
/* units of 100MHz */
83 intel_fdi_link_freq(struct drm_device
*dev
)
86 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
87 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
92 static const intel_limit_t intel_limits_i8xx_dac
= {
93 .dot
= { .min
= 25000, .max
= 350000 },
94 .vco
= { .min
= 930000, .max
= 1400000 },
95 .n
= { .min
= 3, .max
= 16 },
96 .m
= { .min
= 96, .max
= 140 },
97 .m1
= { .min
= 18, .max
= 26 },
98 .m2
= { .min
= 6, .max
= 16 },
99 .p
= { .min
= 4, .max
= 128 },
100 .p1
= { .min
= 2, .max
= 33 },
101 .p2
= { .dot_limit
= 165000,
102 .p2_slow
= 4, .p2_fast
= 2 },
105 static const intel_limit_t intel_limits_i8xx_dvo
= {
106 .dot
= { .min
= 25000, .max
= 350000 },
107 .vco
= { .min
= 930000, .max
= 1400000 },
108 .n
= { .min
= 3, .max
= 16 },
109 .m
= { .min
= 96, .max
= 140 },
110 .m1
= { .min
= 18, .max
= 26 },
111 .m2
= { .min
= 6, .max
= 16 },
112 .p
= { .min
= 4, .max
= 128 },
113 .p1
= { .min
= 2, .max
= 33 },
114 .p2
= { .dot_limit
= 165000,
115 .p2_slow
= 4, .p2_fast
= 4 },
118 static const intel_limit_t intel_limits_i8xx_lvds
= {
119 .dot
= { .min
= 25000, .max
= 350000 },
120 .vco
= { .min
= 930000, .max
= 1400000 },
121 .n
= { .min
= 3, .max
= 16 },
122 .m
= { .min
= 96, .max
= 140 },
123 .m1
= { .min
= 18, .max
= 26 },
124 .m2
= { .min
= 6, .max
= 16 },
125 .p
= { .min
= 4, .max
= 128 },
126 .p1
= { .min
= 1, .max
= 6 },
127 .p2
= { .dot_limit
= 165000,
128 .p2_slow
= 14, .p2_fast
= 7 },
131 static const intel_limit_t intel_limits_i9xx_sdvo
= {
132 .dot
= { .min
= 20000, .max
= 400000 },
133 .vco
= { .min
= 1400000, .max
= 2800000 },
134 .n
= { .min
= 1, .max
= 6 },
135 .m
= { .min
= 70, .max
= 120 },
136 .m1
= { .min
= 8, .max
= 18 },
137 .m2
= { .min
= 3, .max
= 7 },
138 .p
= { .min
= 5, .max
= 80 },
139 .p1
= { .min
= 1, .max
= 8 },
140 .p2
= { .dot_limit
= 200000,
141 .p2_slow
= 10, .p2_fast
= 5 },
144 static const intel_limit_t intel_limits_i9xx_lvds
= {
145 .dot
= { .min
= 20000, .max
= 400000 },
146 .vco
= { .min
= 1400000, .max
= 2800000 },
147 .n
= { .min
= 1, .max
= 6 },
148 .m
= { .min
= 70, .max
= 120 },
149 .m1
= { .min
= 8, .max
= 18 },
150 .m2
= { .min
= 3, .max
= 7 },
151 .p
= { .min
= 7, .max
= 98 },
152 .p1
= { .min
= 1, .max
= 8 },
153 .p2
= { .dot_limit
= 112000,
154 .p2_slow
= 14, .p2_fast
= 7 },
158 static const intel_limit_t intel_limits_g4x_sdvo
= {
159 .dot
= { .min
= 25000, .max
= 270000 },
160 .vco
= { .min
= 1750000, .max
= 3500000},
161 .n
= { .min
= 1, .max
= 4 },
162 .m
= { .min
= 104, .max
= 138 },
163 .m1
= { .min
= 17, .max
= 23 },
164 .m2
= { .min
= 5, .max
= 11 },
165 .p
= { .min
= 10, .max
= 30 },
166 .p1
= { .min
= 1, .max
= 3},
167 .p2
= { .dot_limit
= 270000,
173 static const intel_limit_t intel_limits_g4x_hdmi
= {
174 .dot
= { .min
= 22000, .max
= 400000 },
175 .vco
= { .min
= 1750000, .max
= 3500000},
176 .n
= { .min
= 1, .max
= 4 },
177 .m
= { .min
= 104, .max
= 138 },
178 .m1
= { .min
= 16, .max
= 23 },
179 .m2
= { .min
= 5, .max
= 11 },
180 .p
= { .min
= 5, .max
= 80 },
181 .p1
= { .min
= 1, .max
= 8},
182 .p2
= { .dot_limit
= 165000,
183 .p2_slow
= 10, .p2_fast
= 5 },
186 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
187 .dot
= { .min
= 20000, .max
= 115000 },
188 .vco
= { .min
= 1750000, .max
= 3500000 },
189 .n
= { .min
= 1, .max
= 3 },
190 .m
= { .min
= 104, .max
= 138 },
191 .m1
= { .min
= 17, .max
= 23 },
192 .m2
= { .min
= 5, .max
= 11 },
193 .p
= { .min
= 28, .max
= 112 },
194 .p1
= { .min
= 2, .max
= 8 },
195 .p2
= { .dot_limit
= 0,
196 .p2_slow
= 14, .p2_fast
= 14
200 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
201 .dot
= { .min
= 80000, .max
= 224000 },
202 .vco
= { .min
= 1750000, .max
= 3500000 },
203 .n
= { .min
= 1, .max
= 3 },
204 .m
= { .min
= 104, .max
= 138 },
205 .m1
= { .min
= 17, .max
= 23 },
206 .m2
= { .min
= 5, .max
= 11 },
207 .p
= { .min
= 14, .max
= 42 },
208 .p1
= { .min
= 2, .max
= 6 },
209 .p2
= { .dot_limit
= 0,
210 .p2_slow
= 7, .p2_fast
= 7
214 static const intel_limit_t intel_limits_pineview_sdvo
= {
215 .dot
= { .min
= 20000, .max
= 400000},
216 .vco
= { .min
= 1700000, .max
= 3500000 },
217 /* Pineview's Ncounter is a ring counter */
218 .n
= { .min
= 3, .max
= 6 },
219 .m
= { .min
= 2, .max
= 256 },
220 /* Pineview only has one combined m divider, which we treat as m2. */
221 .m1
= { .min
= 0, .max
= 0 },
222 .m2
= { .min
= 0, .max
= 254 },
223 .p
= { .min
= 5, .max
= 80 },
224 .p1
= { .min
= 1, .max
= 8 },
225 .p2
= { .dot_limit
= 200000,
226 .p2_slow
= 10, .p2_fast
= 5 },
229 static const intel_limit_t intel_limits_pineview_lvds
= {
230 .dot
= { .min
= 20000, .max
= 400000 },
231 .vco
= { .min
= 1700000, .max
= 3500000 },
232 .n
= { .min
= 3, .max
= 6 },
233 .m
= { .min
= 2, .max
= 256 },
234 .m1
= { .min
= 0, .max
= 0 },
235 .m2
= { .min
= 0, .max
= 254 },
236 .p
= { .min
= 7, .max
= 112 },
237 .p1
= { .min
= 1, .max
= 8 },
238 .p2
= { .dot_limit
= 112000,
239 .p2_slow
= 14, .p2_fast
= 14 },
242 /* Ironlake / Sandybridge
244 * We calculate clock using (register_value + 2) for N/M1/M2, so here
245 * the range value for them is (actual_value - 2).
247 static const intel_limit_t intel_limits_ironlake_dac
= {
248 .dot
= { .min
= 25000, .max
= 350000 },
249 .vco
= { .min
= 1760000, .max
= 3510000 },
250 .n
= { .min
= 1, .max
= 5 },
251 .m
= { .min
= 79, .max
= 127 },
252 .m1
= { .min
= 12, .max
= 22 },
253 .m2
= { .min
= 5, .max
= 9 },
254 .p
= { .min
= 5, .max
= 80 },
255 .p1
= { .min
= 1, .max
= 8 },
256 .p2
= { .dot_limit
= 225000,
257 .p2_slow
= 10, .p2_fast
= 5 },
260 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
261 .dot
= { .min
= 25000, .max
= 350000 },
262 .vco
= { .min
= 1760000, .max
= 3510000 },
263 .n
= { .min
= 1, .max
= 3 },
264 .m
= { .min
= 79, .max
= 118 },
265 .m1
= { .min
= 12, .max
= 22 },
266 .m2
= { .min
= 5, .max
= 9 },
267 .p
= { .min
= 28, .max
= 112 },
268 .p1
= { .min
= 2, .max
= 8 },
269 .p2
= { .dot_limit
= 225000,
270 .p2_slow
= 14, .p2_fast
= 14 },
273 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
274 .dot
= { .min
= 25000, .max
= 350000 },
275 .vco
= { .min
= 1760000, .max
= 3510000 },
276 .n
= { .min
= 1, .max
= 3 },
277 .m
= { .min
= 79, .max
= 127 },
278 .m1
= { .min
= 12, .max
= 22 },
279 .m2
= { .min
= 5, .max
= 9 },
280 .p
= { .min
= 14, .max
= 56 },
281 .p1
= { .min
= 2, .max
= 8 },
282 .p2
= { .dot_limit
= 225000,
283 .p2_slow
= 7, .p2_fast
= 7 },
286 /* LVDS 100mhz refclk limits. */
287 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
288 .dot
= { .min
= 25000, .max
= 350000 },
289 .vco
= { .min
= 1760000, .max
= 3510000 },
290 .n
= { .min
= 1, .max
= 2 },
291 .m
= { .min
= 79, .max
= 126 },
292 .m1
= { .min
= 12, .max
= 22 },
293 .m2
= { .min
= 5, .max
= 9 },
294 .p
= { .min
= 28, .max
= 112 },
295 .p1
= { .min
= 2, .max
= 8 },
296 .p2
= { .dot_limit
= 225000,
297 .p2_slow
= 14, .p2_fast
= 14 },
300 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
301 .dot
= { .min
= 25000, .max
= 350000 },
302 .vco
= { .min
= 1760000, .max
= 3510000 },
303 .n
= { .min
= 1, .max
= 3 },
304 .m
= { .min
= 79, .max
= 126 },
305 .m1
= { .min
= 12, .max
= 22 },
306 .m2
= { .min
= 5, .max
= 9 },
307 .p
= { .min
= 14, .max
= 42 },
308 .p1
= { .min
= 2, .max
= 6 },
309 .p2
= { .dot_limit
= 225000,
310 .p2_slow
= 7, .p2_fast
= 7 },
313 static const intel_limit_t intel_limits_vlv_dac
= {
314 .dot
= { .min
= 25000, .max
= 270000 },
315 .vco
= { .min
= 4000000, .max
= 6000000 },
316 .n
= { .min
= 1, .max
= 7 },
317 .m
= { .min
= 22, .max
= 450 }, /* guess */
318 .m1
= { .min
= 2, .max
= 3 },
319 .m2
= { .min
= 11, .max
= 156 },
320 .p
= { .min
= 10, .max
= 30 },
321 .p1
= { .min
= 1, .max
= 3 },
322 .p2
= { .dot_limit
= 270000,
323 .p2_slow
= 2, .p2_fast
= 20 },
326 static const intel_limit_t intel_limits_vlv_hdmi
= {
327 .dot
= { .min
= 25000, .max
= 270000 },
328 .vco
= { .min
= 4000000, .max
= 6000000 },
329 .n
= { .min
= 1, .max
= 7 },
330 .m
= { .min
= 60, .max
= 300 }, /* guess */
331 .m1
= { .min
= 2, .max
= 3 },
332 .m2
= { .min
= 11, .max
= 156 },
333 .p
= { .min
= 10, .max
= 30 },
334 .p1
= { .min
= 2, .max
= 3 },
335 .p2
= { .dot_limit
= 270000,
336 .p2_slow
= 2, .p2_fast
= 20 },
339 static const intel_limit_t intel_limits_vlv_dp
= {
340 .dot
= { .min
= 25000, .max
= 270000 },
341 .vco
= { .min
= 4000000, .max
= 6000000 },
342 .n
= { .min
= 1, .max
= 7 },
343 .m
= { .min
= 22, .max
= 450 },
344 .m1
= { .min
= 2, .max
= 3 },
345 .m2
= { .min
= 11, .max
= 156 },
346 .p
= { .min
= 10, .max
= 30 },
347 .p1
= { .min
= 1, .max
= 3 },
348 .p2
= { .dot_limit
= 270000,
349 .p2_slow
= 2, .p2_fast
= 20 },
352 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
,
355 struct drm_device
*dev
= crtc
->dev
;
356 const intel_limit_t
*limit
;
358 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
359 if (intel_is_dual_link_lvds(dev
)) {
360 if (refclk
== 100000)
361 limit
= &intel_limits_ironlake_dual_lvds_100m
;
363 limit
= &intel_limits_ironlake_dual_lvds
;
365 if (refclk
== 100000)
366 limit
= &intel_limits_ironlake_single_lvds_100m
;
368 limit
= &intel_limits_ironlake_single_lvds
;
371 limit
= &intel_limits_ironlake_dac
;
376 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
378 struct drm_device
*dev
= crtc
->dev
;
379 const intel_limit_t
*limit
;
381 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
382 if (intel_is_dual_link_lvds(dev
))
383 limit
= &intel_limits_g4x_dual_channel_lvds
;
385 limit
= &intel_limits_g4x_single_channel_lvds
;
386 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
387 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
388 limit
= &intel_limits_g4x_hdmi
;
389 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
390 limit
= &intel_limits_g4x_sdvo
;
391 } else /* The option is for other outputs */
392 limit
= &intel_limits_i9xx_sdvo
;
397 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
, int refclk
)
399 struct drm_device
*dev
= crtc
->dev
;
400 const intel_limit_t
*limit
;
402 if (HAS_PCH_SPLIT(dev
))
403 limit
= intel_ironlake_limit(crtc
, refclk
);
404 else if (IS_G4X(dev
)) {
405 limit
= intel_g4x_limit(crtc
);
406 } else if (IS_PINEVIEW(dev
)) {
407 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
408 limit
= &intel_limits_pineview_lvds
;
410 limit
= &intel_limits_pineview_sdvo
;
411 } else if (IS_VALLEYVIEW(dev
)) {
412 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
))
413 limit
= &intel_limits_vlv_dac
;
414 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
415 limit
= &intel_limits_vlv_hdmi
;
417 limit
= &intel_limits_vlv_dp
;
418 } else if (!IS_GEN2(dev
)) {
419 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
420 limit
= &intel_limits_i9xx_lvds
;
422 limit
= &intel_limits_i9xx_sdvo
;
424 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
425 limit
= &intel_limits_i8xx_lvds
;
426 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
))
427 limit
= &intel_limits_i8xx_dvo
;
429 limit
= &intel_limits_i8xx_dac
;
434 /* m1 is reserved as 0 in Pineview, n is a ring counter */
435 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
437 clock
->m
= clock
->m2
+ 2;
438 clock
->p
= clock
->p1
* clock
->p2
;
439 clock
->vco
= refclk
* clock
->m
/ clock
->n
;
440 clock
->dot
= clock
->vco
/ clock
->p
;
443 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
445 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
448 static void i9xx_clock(int refclk
, intel_clock_t
*clock
)
450 clock
->m
= i9xx_dpll_compute_m(clock
);
451 clock
->p
= clock
->p1
* clock
->p2
;
452 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
453 clock
->dot
= clock
->vco
/ clock
->p
;
457 * Returns whether any output on the specified pipe is of the specified type
459 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
461 struct drm_device
*dev
= crtc
->dev
;
462 struct intel_encoder
*encoder
;
464 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
465 if (encoder
->type
== type
)
471 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
473 * Returns whether the given set of divisors are valid for a given refclk with
474 * the given connectors.
477 static bool intel_PLL_is_valid(struct drm_device
*dev
,
478 const intel_limit_t
*limit
,
479 const intel_clock_t
*clock
)
481 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
482 INTELPllInvalid("p1 out of range\n");
483 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
484 INTELPllInvalid("p out of range\n");
485 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
486 INTELPllInvalid("m2 out of range\n");
487 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
488 INTELPllInvalid("m1 out of range\n");
489 if (clock
->m1
<= clock
->m2
&& !IS_PINEVIEW(dev
))
490 INTELPllInvalid("m1 <= m2\n");
491 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
492 INTELPllInvalid("m out of range\n");
493 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
494 INTELPllInvalid("n out of range\n");
495 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
496 INTELPllInvalid("vco out of range\n");
497 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
498 * connector, etc., rather than just a single range.
500 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
501 INTELPllInvalid("dot out of range\n");
507 i9xx_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
508 int target
, int refclk
, intel_clock_t
*match_clock
,
509 intel_clock_t
*best_clock
)
511 struct drm_device
*dev
= crtc
->dev
;
515 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
517 * For LVDS just rely on its current settings for dual-channel.
518 * We haven't figured out how to reliably set up different
519 * single/dual channel state, if we even can.
521 if (intel_is_dual_link_lvds(dev
))
522 clock
.p2
= limit
->p2
.p2_fast
;
524 clock
.p2
= limit
->p2
.p2_slow
;
526 if (target
< limit
->p2
.dot_limit
)
527 clock
.p2
= limit
->p2
.p2_slow
;
529 clock
.p2
= limit
->p2
.p2_fast
;
532 memset(best_clock
, 0, sizeof(*best_clock
));
534 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
536 for (clock
.m2
= limit
->m2
.min
;
537 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
538 if (clock
.m2
>= clock
.m1
)
540 for (clock
.n
= limit
->n
.min
;
541 clock
.n
<= limit
->n
.max
; clock
.n
++) {
542 for (clock
.p1
= limit
->p1
.min
;
543 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
546 i9xx_clock(refclk
, &clock
);
547 if (!intel_PLL_is_valid(dev
, limit
,
551 clock
.p
!= match_clock
->p
)
554 this_err
= abs(clock
.dot
- target
);
555 if (this_err
< err
) {
564 return (err
!= target
);
568 pnv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
569 int target
, int refclk
, intel_clock_t
*match_clock
,
570 intel_clock_t
*best_clock
)
572 struct drm_device
*dev
= crtc
->dev
;
576 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
578 * For LVDS just rely on its current settings for dual-channel.
579 * We haven't figured out how to reliably set up different
580 * single/dual channel state, if we even can.
582 if (intel_is_dual_link_lvds(dev
))
583 clock
.p2
= limit
->p2
.p2_fast
;
585 clock
.p2
= limit
->p2
.p2_slow
;
587 if (target
< limit
->p2
.dot_limit
)
588 clock
.p2
= limit
->p2
.p2_slow
;
590 clock
.p2
= limit
->p2
.p2_fast
;
593 memset(best_clock
, 0, sizeof(*best_clock
));
595 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
597 for (clock
.m2
= limit
->m2
.min
;
598 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
599 for (clock
.n
= limit
->n
.min
;
600 clock
.n
<= limit
->n
.max
; clock
.n
++) {
601 for (clock
.p1
= limit
->p1
.min
;
602 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
605 pineview_clock(refclk
, &clock
);
606 if (!intel_PLL_is_valid(dev
, limit
,
610 clock
.p
!= match_clock
->p
)
613 this_err
= abs(clock
.dot
- target
);
614 if (this_err
< err
) {
623 return (err
!= target
);
627 g4x_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
628 int target
, int refclk
, intel_clock_t
*match_clock
,
629 intel_clock_t
*best_clock
)
631 struct drm_device
*dev
= crtc
->dev
;
635 /* approximately equals target * 0.00585 */
636 int err_most
= (target
>> 8) + (target
>> 9);
639 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
640 if (intel_is_dual_link_lvds(dev
))
641 clock
.p2
= limit
->p2
.p2_fast
;
643 clock
.p2
= limit
->p2
.p2_slow
;
645 if (target
< limit
->p2
.dot_limit
)
646 clock
.p2
= limit
->p2
.p2_slow
;
648 clock
.p2
= limit
->p2
.p2_fast
;
651 memset(best_clock
, 0, sizeof(*best_clock
));
652 max_n
= limit
->n
.max
;
653 /* based on hardware requirement, prefer smaller n to precision */
654 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
655 /* based on hardware requirement, prefere larger m1,m2 */
656 for (clock
.m1
= limit
->m1
.max
;
657 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
658 for (clock
.m2
= limit
->m2
.max
;
659 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
660 for (clock
.p1
= limit
->p1
.max
;
661 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
664 i9xx_clock(refclk
, &clock
);
665 if (!intel_PLL_is_valid(dev
, limit
,
669 this_err
= abs(clock
.dot
- target
);
670 if (this_err
< err_most
) {
684 vlv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
685 int target
, int refclk
, intel_clock_t
*match_clock
,
686 intel_clock_t
*best_clock
)
688 u32 p1
, p2
, m1
, m2
, vco
, bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
690 u32 updrate
, minupdate
, fracbits
, p
;
691 unsigned long bestppm
, ppm
, absppm
;
695 dotclk
= target
* 1000;
698 fastclk
= dotclk
/ (2*100);
702 n
= p
= p1
= p2
= m
= m1
= m2
= vco
= bestn
= 0;
703 bestm1
= bestm2
= bestp1
= bestp2
= 0;
705 /* based on hardware requirement, prefer smaller n to precision */
706 for (n
= limit
->n
.min
; n
<= ((refclk
) / minupdate
); n
++) {
707 updrate
= refclk
/ n
;
708 for (p1
= limit
->p1
.max
; p1
> limit
->p1
.min
; p1
--) {
709 for (p2
= limit
->p2
.p2_fast
+1; p2
> 0; p2
--) {
713 /* based on hardware requirement, prefer bigger m1,m2 values */
714 for (m1
= limit
->m1
.min
; m1
<= limit
->m1
.max
; m1
++) {
715 m2
= (((2*(fastclk
* p
* n
/ m1
)) +
716 refclk
) / (2*refclk
));
719 if (vco
>= limit
->vco
.min
&& vco
< limit
->vco
.max
) {
720 ppm
= 1000000 * ((vco
/ p
) - fastclk
) / fastclk
;
721 absppm
= (ppm
> 0) ? ppm
: (-ppm
);
722 if (absppm
< 100 && ((p1
* p2
) > (bestp1
* bestp2
))) {
726 if (absppm
< bestppm
- 10) {
743 best_clock
->n
= bestn
;
744 best_clock
->m1
= bestm1
;
745 best_clock
->m2
= bestm2
;
746 best_clock
->p1
= bestp1
;
747 best_clock
->p2
= bestp2
;
752 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
755 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
756 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
758 return intel_crtc
->config
.cpu_transcoder
;
761 static void ironlake_wait_for_vblank(struct drm_device
*dev
, int pipe
)
763 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
764 u32 frame
, frame_reg
= PIPEFRAME(pipe
);
766 frame
= I915_READ(frame_reg
);
768 if (wait_for(I915_READ_NOTRACE(frame_reg
) != frame
, 50))
769 DRM_DEBUG_KMS("vblank wait timed out\n");
773 * intel_wait_for_vblank - wait for vblank on a given pipe
775 * @pipe: pipe to wait for
777 * Wait for vblank to occur on a given pipe. Needed for various bits of
780 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
782 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
783 int pipestat_reg
= PIPESTAT(pipe
);
785 if (INTEL_INFO(dev
)->gen
>= 5) {
786 ironlake_wait_for_vblank(dev
, pipe
);
790 /* Clear existing vblank status. Note this will clear any other
791 * sticky status fields as well.
793 * This races with i915_driver_irq_handler() with the result
794 * that either function could miss a vblank event. Here it is not
795 * fatal, as we will either wait upon the next vblank interrupt or
796 * timeout. Generally speaking intel_wait_for_vblank() is only
797 * called during modeset at which time the GPU should be idle and
798 * should *not* be performing page flips and thus not waiting on
800 * Currently, the result of us stealing a vblank from the irq
801 * handler is that a single frame will be skipped during swapbuffers.
803 I915_WRITE(pipestat_reg
,
804 I915_READ(pipestat_reg
) | PIPE_VBLANK_INTERRUPT_STATUS
);
806 /* Wait for vblank interrupt bit to set */
807 if (wait_for(I915_READ(pipestat_reg
) &
808 PIPE_VBLANK_INTERRUPT_STATUS
,
810 DRM_DEBUG_KMS("vblank wait timed out\n");
814 * intel_wait_for_pipe_off - wait for pipe to turn off
816 * @pipe: pipe to wait for
818 * After disabling a pipe, we can't wait for vblank in the usual way,
819 * spinning on the vblank interrupt status bit, since we won't actually
820 * see an interrupt when the pipe is disabled.
823 * wait for the pipe register state bit to turn off
826 * wait for the display line value to settle (it usually
827 * ends up stopping at the start of the next frame).
830 void intel_wait_for_pipe_off(struct drm_device
*dev
, int pipe
)
832 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
833 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
836 if (INTEL_INFO(dev
)->gen
>= 4) {
837 int reg
= PIPECONF(cpu_transcoder
);
839 /* Wait for the Pipe State to go off */
840 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
842 WARN(1, "pipe_off wait timed out\n");
844 u32 last_line
, line_mask
;
845 int reg
= PIPEDSL(pipe
);
846 unsigned long timeout
= jiffies
+ msecs_to_jiffies(100);
849 line_mask
= DSL_LINEMASK_GEN2
;
851 line_mask
= DSL_LINEMASK_GEN3
;
853 /* Wait for the display line to settle */
855 last_line
= I915_READ(reg
) & line_mask
;
857 } while (((I915_READ(reg
) & line_mask
) != last_line
) &&
858 time_after(timeout
, jiffies
));
859 if (time_after(jiffies
, timeout
))
860 WARN(1, "pipe_off wait timed out\n");
865 * ibx_digital_port_connected - is the specified port connected?
866 * @dev_priv: i915 private structure
867 * @port: the port to test
869 * Returns true if @port is connected, false otherwise.
871 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
872 struct intel_digital_port
*port
)
876 if (HAS_PCH_IBX(dev_priv
->dev
)) {
879 bit
= SDE_PORTB_HOTPLUG
;
882 bit
= SDE_PORTC_HOTPLUG
;
885 bit
= SDE_PORTD_HOTPLUG
;
893 bit
= SDE_PORTB_HOTPLUG_CPT
;
896 bit
= SDE_PORTC_HOTPLUG_CPT
;
899 bit
= SDE_PORTD_HOTPLUG_CPT
;
906 return I915_READ(SDEISR
) & bit
;
909 static const char *state_string(bool enabled
)
911 return enabled
? "on" : "off";
914 /* Only for pre-ILK configs */
915 void assert_pll(struct drm_i915_private
*dev_priv
,
916 enum pipe pipe
, bool state
)
923 val
= I915_READ(reg
);
924 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
925 WARN(cur_state
!= state
,
926 "PLL state assertion failure (expected %s, current %s)\n",
927 state_string(state
), state_string(cur_state
));
930 struct intel_shared_dpll
*
931 intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
)
933 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
935 if (crtc
->config
.shared_dpll
< 0)
938 return &dev_priv
->shared_dplls
[crtc
->config
.shared_dpll
];
942 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
943 struct intel_shared_dpll
*pll
,
947 struct intel_dpll_hw_state hw_state
;
949 if (HAS_PCH_LPT(dev_priv
->dev
)) {
950 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
955 "asserting DPLL %s with no DPLL\n", state_string(state
)))
958 cur_state
= pll
->get_hw_state(dev_priv
, pll
, &hw_state
);
959 WARN(cur_state
!= state
,
960 "%s assertion failure (expected %s, current %s)\n",
961 pll
->name
, state_string(state
), state_string(cur_state
));
964 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
965 enum pipe pipe
, bool state
)
970 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
973 if (HAS_DDI(dev_priv
->dev
)) {
974 /* DDI does not have a specific FDI_TX register */
975 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
976 val
= I915_READ(reg
);
977 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
979 reg
= FDI_TX_CTL(pipe
);
980 val
= I915_READ(reg
);
981 cur_state
= !!(val
& FDI_TX_ENABLE
);
983 WARN(cur_state
!= state
,
984 "FDI TX state assertion failure (expected %s, current %s)\n",
985 state_string(state
), state_string(cur_state
));
987 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
988 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
990 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
991 enum pipe pipe
, bool state
)
997 reg
= FDI_RX_CTL(pipe
);
998 val
= I915_READ(reg
);
999 cur_state
= !!(val
& FDI_RX_ENABLE
);
1000 WARN(cur_state
!= state
,
1001 "FDI RX state assertion failure (expected %s, current %s)\n",
1002 state_string(state
), state_string(cur_state
));
1004 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1005 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1007 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1013 /* ILK FDI PLL is always enabled */
1014 if (dev_priv
->info
->gen
== 5)
1017 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1018 if (HAS_DDI(dev_priv
->dev
))
1021 reg
= FDI_TX_CTL(pipe
);
1022 val
= I915_READ(reg
);
1023 WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1026 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1027 enum pipe pipe
, bool state
)
1033 reg
= FDI_RX_CTL(pipe
);
1034 val
= I915_READ(reg
);
1035 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1036 WARN(cur_state
!= state
,
1037 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1038 state_string(state
), state_string(cur_state
));
1041 static void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1044 int pp_reg
, lvds_reg
;
1046 enum pipe panel_pipe
= PIPE_A
;
1049 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
1050 pp_reg
= PCH_PP_CONTROL
;
1051 lvds_reg
= PCH_LVDS
;
1053 pp_reg
= PP_CONTROL
;
1057 val
= I915_READ(pp_reg
);
1058 if (!(val
& PANEL_POWER_ON
) ||
1059 ((val
& PANEL_UNLOCK_REGS
) == PANEL_UNLOCK_REGS
))
1062 if (I915_READ(lvds_reg
) & LVDS_PIPEB_SELECT
)
1063 panel_pipe
= PIPE_B
;
1065 WARN(panel_pipe
== pipe
&& locked
,
1066 "panel assertion failure, pipe %c regs locked\n",
1070 void assert_pipe(struct drm_i915_private
*dev_priv
,
1071 enum pipe pipe
, bool state
)
1076 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1079 /* if we need the pipe A quirk it must be always on */
1080 if (pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
1083 if (!intel_display_power_enabled(dev_priv
->dev
,
1084 POWER_DOMAIN_TRANSCODER(cpu_transcoder
))) {
1087 reg
= PIPECONF(cpu_transcoder
);
1088 val
= I915_READ(reg
);
1089 cur_state
= !!(val
& PIPECONF_ENABLE
);
1092 WARN(cur_state
!= state
,
1093 "pipe %c assertion failure (expected %s, current %s)\n",
1094 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1097 static void assert_plane(struct drm_i915_private
*dev_priv
,
1098 enum plane plane
, bool state
)
1104 reg
= DSPCNTR(plane
);
1105 val
= I915_READ(reg
);
1106 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1107 WARN(cur_state
!= state
,
1108 "plane %c assertion failure (expected %s, current %s)\n",
1109 plane_name(plane
), state_string(state
), state_string(cur_state
));
1112 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1113 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1115 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1118 struct drm_device
*dev
= dev_priv
->dev
;
1123 /* Primary planes are fixed to pipes on gen4+ */
1124 if (INTEL_INFO(dev
)->gen
>= 4) {
1125 reg
= DSPCNTR(pipe
);
1126 val
= I915_READ(reg
);
1127 WARN((val
& DISPLAY_PLANE_ENABLE
),
1128 "plane %c assertion failure, should be disabled but not\n",
1133 /* Need to check both planes against the pipe */
1136 val
= I915_READ(reg
);
1137 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1138 DISPPLANE_SEL_PIPE_SHIFT
;
1139 WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1140 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1141 plane_name(i
), pipe_name(pipe
));
1145 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1148 struct drm_device
*dev
= dev_priv
->dev
;
1152 if (IS_VALLEYVIEW(dev
)) {
1153 for (i
= 0; i
< dev_priv
->num_plane
; i
++) {
1154 reg
= SPCNTR(pipe
, i
);
1155 val
= I915_READ(reg
);
1156 WARN((val
& SP_ENABLE
),
1157 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1158 sprite_name(pipe
, i
), pipe_name(pipe
));
1160 } else if (INTEL_INFO(dev
)->gen
>= 7) {
1162 val
= I915_READ(reg
);
1163 WARN((val
& SPRITE_ENABLE
),
1164 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1165 plane_name(pipe
), pipe_name(pipe
));
1166 } else if (INTEL_INFO(dev
)->gen
>= 5) {
1167 reg
= DVSCNTR(pipe
);
1168 val
= I915_READ(reg
);
1169 WARN((val
& DVS_ENABLE
),
1170 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1171 plane_name(pipe
), pipe_name(pipe
));
1175 static void assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1180 if (HAS_PCH_LPT(dev_priv
->dev
)) {
1181 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1185 val
= I915_READ(PCH_DREF_CONTROL
);
1186 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1187 DREF_SUPERSPREAD_SOURCE_MASK
));
1188 WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1191 static void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1198 reg
= PCH_TRANSCONF(pipe
);
1199 val
= I915_READ(reg
);
1200 enabled
= !!(val
& TRANS_ENABLE
);
1202 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1206 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1207 enum pipe pipe
, u32 port_sel
, u32 val
)
1209 if ((val
& DP_PORT_EN
) == 0)
1212 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1213 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1214 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1215 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1218 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1224 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1225 enum pipe pipe
, u32 val
)
1227 if ((val
& SDVO_ENABLE
) == 0)
1230 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1231 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1234 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1240 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1241 enum pipe pipe
, u32 val
)
1243 if ((val
& LVDS_PORT_EN
) == 0)
1246 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1247 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1250 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1256 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1257 enum pipe pipe
, u32 val
)
1259 if ((val
& ADPA_DAC_ENABLE
) == 0)
1261 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1262 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1265 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1271 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1272 enum pipe pipe
, int reg
, u32 port_sel
)
1274 u32 val
= I915_READ(reg
);
1275 WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1276 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1277 reg
, pipe_name(pipe
));
1279 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1280 && (val
& DP_PIPEB_SELECT
),
1281 "IBX PCH dp port still using transcoder B\n");
1284 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1285 enum pipe pipe
, int reg
)
1287 u32 val
= I915_READ(reg
);
1288 WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1289 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1290 reg
, pipe_name(pipe
));
1292 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_ENABLE
) == 0
1293 && (val
& SDVO_PIPE_B_SELECT
),
1294 "IBX PCH hdmi port still using transcoder B\n");
1297 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1303 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1304 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1305 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1308 val
= I915_READ(reg
);
1309 WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1310 "PCH VGA enabled on transcoder %c, should be disabled\n",
1314 val
= I915_READ(reg
);
1315 WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1316 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1319 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1320 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1321 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1324 static void vlv_enable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1329 assert_pipe_disabled(dev_priv
, pipe
);
1331 /* No really, not for ILK+ */
1332 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
));
1334 /* PLL is protected by panel, make sure we can write it */
1335 if (IS_MOBILE(dev_priv
->dev
) && !IS_I830(dev_priv
->dev
))
1336 assert_panel_unlocked(dev_priv
, pipe
);
1339 val
= I915_READ(reg
);
1340 val
|= DPLL_VCO_ENABLE
;
1342 /* We do this three times for luck */
1343 I915_WRITE(reg
, val
);
1345 udelay(150); /* wait for warmup */
1346 I915_WRITE(reg
, val
);
1348 udelay(150); /* wait for warmup */
1349 I915_WRITE(reg
, val
);
1351 udelay(150); /* wait for warmup */
1354 static void i9xx_enable_pll(struct intel_crtc
*crtc
)
1356 struct drm_device
*dev
= crtc
->base
.dev
;
1357 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1358 int reg
= DPLL(crtc
->pipe
);
1359 u32 dpll
= crtc
->config
.dpll_hw_state
.dpll
;
1361 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1363 /* No really, not for ILK+ */
1364 BUG_ON(dev_priv
->info
->gen
>= 5);
1366 /* PLL is protected by panel, make sure we can write it */
1367 if (IS_MOBILE(dev
) && !IS_I830(dev
))
1368 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1370 I915_WRITE(reg
, dpll
);
1372 /* Wait for the clocks to stabilize. */
1376 if (INTEL_INFO(dev
)->gen
>= 4) {
1377 I915_WRITE(DPLL_MD(crtc
->pipe
),
1378 crtc
->config
.dpll_hw_state
.dpll_md
);
1380 /* The pixel multiplier can only be updated once the
1381 * DPLL is enabled and the clocks are stable.
1383 * So write it again.
1385 I915_WRITE(reg
, dpll
);
1388 /* We do this three times for luck */
1389 I915_WRITE(reg
, dpll
);
1391 udelay(150); /* wait for warmup */
1392 I915_WRITE(reg
, dpll
);
1394 udelay(150); /* wait for warmup */
1395 I915_WRITE(reg
, dpll
);
1397 udelay(150); /* wait for warmup */
1401 * intel_disable_pll - disable a PLL
1402 * @dev_priv: i915 private structure
1403 * @pipe: pipe PLL to disable
1405 * Disable the PLL for @pipe, making sure the pipe is off first.
1407 * Note! This is for pre-ILK only.
1409 static void intel_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1414 /* Don't disable pipe A or pipe A PLLs if needed */
1415 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1418 /* Make sure the pipe isn't still relying on us */
1419 assert_pipe_disabled(dev_priv
, pipe
);
1422 val
= I915_READ(reg
);
1423 val
&= ~DPLL_VCO_ENABLE
;
1424 I915_WRITE(reg
, val
);
1428 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
, int port
)
1433 port_mask
= DPLL_PORTB_READY_MASK
;
1435 port_mask
= DPLL_PORTC_READY_MASK
;
1437 if (wait_for((I915_READ(DPLL(0)) & port_mask
) == 0, 1000))
1438 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1439 'B' + port
, I915_READ(DPLL(0)));
1443 * ironlake_enable_shared_dpll - enable PCH PLL
1444 * @dev_priv: i915 private structure
1445 * @pipe: pipe PLL to enable
1447 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1448 * drives the transcoder clock.
1450 static void ironlake_enable_shared_dpll(struct intel_crtc
*crtc
)
1452 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1453 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1455 /* PCH PLLs only available on ILK, SNB and IVB */
1456 BUG_ON(dev_priv
->info
->gen
< 5);
1457 if (WARN_ON(pll
== NULL
))
1460 if (WARN_ON(pll
->refcount
== 0))
1463 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1464 pll
->name
, pll
->active
, pll
->on
,
1465 crtc
->base
.base
.id
);
1467 if (pll
->active
++) {
1469 assert_shared_dpll_enabled(dev_priv
, pll
);
1474 DRM_DEBUG_KMS("enabling %s\n", pll
->name
);
1475 pll
->enable(dev_priv
, pll
);
1479 static void intel_disable_shared_dpll(struct intel_crtc
*crtc
)
1481 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1482 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1484 /* PCH only available on ILK+ */
1485 BUG_ON(dev_priv
->info
->gen
< 5);
1486 if (WARN_ON(pll
== NULL
))
1489 if (WARN_ON(pll
->refcount
== 0))
1492 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1493 pll
->name
, pll
->active
, pll
->on
,
1494 crtc
->base
.base
.id
);
1496 if (WARN_ON(pll
->active
== 0)) {
1497 assert_shared_dpll_disabled(dev_priv
, pll
);
1501 assert_shared_dpll_enabled(dev_priv
, pll
);
1506 DRM_DEBUG_KMS("disabling %s\n", pll
->name
);
1507 pll
->disable(dev_priv
, pll
);
1511 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1514 struct drm_device
*dev
= dev_priv
->dev
;
1515 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1516 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1517 uint32_t reg
, val
, pipeconf_val
;
1519 /* PCH only available on ILK+ */
1520 BUG_ON(dev_priv
->info
->gen
< 5);
1522 /* Make sure PCH DPLL is enabled */
1523 assert_shared_dpll_enabled(dev_priv
,
1524 intel_crtc_to_shared_dpll(intel_crtc
));
1526 /* FDI must be feeding us bits for PCH ports */
1527 assert_fdi_tx_enabled(dev_priv
, pipe
);
1528 assert_fdi_rx_enabled(dev_priv
, pipe
);
1530 if (HAS_PCH_CPT(dev
)) {
1531 /* Workaround: Set the timing override bit before enabling the
1532 * pch transcoder. */
1533 reg
= TRANS_CHICKEN2(pipe
);
1534 val
= I915_READ(reg
);
1535 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1536 I915_WRITE(reg
, val
);
1539 reg
= PCH_TRANSCONF(pipe
);
1540 val
= I915_READ(reg
);
1541 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1543 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1545 * make the BPC in transcoder be consistent with
1546 * that in pipeconf reg.
1548 val
&= ~PIPECONF_BPC_MASK
;
1549 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1552 val
&= ~TRANS_INTERLACE_MASK
;
1553 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1554 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1555 intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
))
1556 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1558 val
|= TRANS_INTERLACED
;
1560 val
|= TRANS_PROGRESSIVE
;
1562 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1563 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1564 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
1567 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1568 enum transcoder cpu_transcoder
)
1570 u32 val
, pipeconf_val
;
1572 /* PCH only available on ILK+ */
1573 BUG_ON(dev_priv
->info
->gen
< 5);
1575 /* FDI must be feeding us bits for PCH ports */
1576 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1577 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
1579 /* Workaround: set timing override bit. */
1580 val
= I915_READ(_TRANSA_CHICKEN2
);
1581 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1582 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1585 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1587 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1588 PIPECONF_INTERLACED_ILK
)
1589 val
|= TRANS_INTERLACED
;
1591 val
|= TRANS_PROGRESSIVE
;
1593 I915_WRITE(LPT_TRANSCONF
, val
);
1594 if (wait_for(I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
, 100))
1595 DRM_ERROR("Failed to enable PCH transcoder\n");
1598 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1601 struct drm_device
*dev
= dev_priv
->dev
;
1604 /* FDI relies on the transcoder */
1605 assert_fdi_tx_disabled(dev_priv
, pipe
);
1606 assert_fdi_rx_disabled(dev_priv
, pipe
);
1608 /* Ports must be off as well */
1609 assert_pch_ports_disabled(dev_priv
, pipe
);
1611 reg
= PCH_TRANSCONF(pipe
);
1612 val
= I915_READ(reg
);
1613 val
&= ~TRANS_ENABLE
;
1614 I915_WRITE(reg
, val
);
1615 /* wait for PCH transcoder off, transcoder state */
1616 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1617 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
1619 if (!HAS_PCH_IBX(dev
)) {
1620 /* Workaround: Clear the timing override chicken bit again. */
1621 reg
= TRANS_CHICKEN2(pipe
);
1622 val
= I915_READ(reg
);
1623 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1624 I915_WRITE(reg
, val
);
1628 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1632 val
= I915_READ(LPT_TRANSCONF
);
1633 val
&= ~TRANS_ENABLE
;
1634 I915_WRITE(LPT_TRANSCONF
, val
);
1635 /* wait for PCH transcoder off, transcoder state */
1636 if (wait_for((I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
) == 0, 50))
1637 DRM_ERROR("Failed to disable PCH transcoder\n");
1639 /* Workaround: clear timing override bit. */
1640 val
= I915_READ(_TRANSA_CHICKEN2
);
1641 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1642 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1646 * intel_enable_pipe - enable a pipe, asserting requirements
1647 * @dev_priv: i915 private structure
1648 * @pipe: pipe to enable
1649 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1651 * Enable @pipe, making sure that various hardware specific requirements
1652 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1654 * @pipe should be %PIPE_A or %PIPE_B.
1656 * Will wait until the pipe is actually running (i.e. first vblank) before
1659 static void intel_enable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
1662 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1664 enum pipe pch_transcoder
;
1668 assert_planes_disabled(dev_priv
, pipe
);
1669 assert_sprites_disabled(dev_priv
, pipe
);
1671 if (HAS_PCH_LPT(dev_priv
->dev
))
1672 pch_transcoder
= TRANSCODER_A
;
1674 pch_transcoder
= pipe
;
1677 * A pipe without a PLL won't actually be able to drive bits from
1678 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1681 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
1682 assert_pll_enabled(dev_priv
, pipe
);
1685 /* if driving the PCH, we need FDI enabled */
1686 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
1687 assert_fdi_tx_pll_enabled(dev_priv
,
1688 (enum pipe
) cpu_transcoder
);
1690 /* FIXME: assert CPU port conditions for SNB+ */
1693 reg
= PIPECONF(cpu_transcoder
);
1694 val
= I915_READ(reg
);
1695 if (val
& PIPECONF_ENABLE
)
1698 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
1699 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1703 * intel_disable_pipe - disable a pipe, asserting requirements
1704 * @dev_priv: i915 private structure
1705 * @pipe: pipe to disable
1707 * Disable @pipe, making sure that various hardware specific requirements
1708 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1710 * @pipe should be %PIPE_A or %PIPE_B.
1712 * Will wait until the pipe has shut down before returning.
1714 static void intel_disable_pipe(struct drm_i915_private
*dev_priv
,
1717 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1723 * Make sure planes won't keep trying to pump pixels to us,
1724 * or we might hang the display.
1726 assert_planes_disabled(dev_priv
, pipe
);
1727 assert_sprites_disabled(dev_priv
, pipe
);
1729 /* Don't disable pipe A or pipe A PLLs if needed */
1730 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1733 reg
= PIPECONF(cpu_transcoder
);
1734 val
= I915_READ(reg
);
1735 if ((val
& PIPECONF_ENABLE
) == 0)
1738 I915_WRITE(reg
, val
& ~PIPECONF_ENABLE
);
1739 intel_wait_for_pipe_off(dev_priv
->dev
, pipe
);
1743 * Plane regs are double buffered, going from enabled->disabled needs a
1744 * trigger in order to latch. The display address reg provides this.
1746 void intel_flush_display_plane(struct drm_i915_private
*dev_priv
,
1749 if (dev_priv
->info
->gen
>= 4)
1750 I915_WRITE(DSPSURF(plane
), I915_READ(DSPSURF(plane
)));
1752 I915_WRITE(DSPADDR(plane
), I915_READ(DSPADDR(plane
)));
1756 * intel_enable_plane - enable a display plane on a given pipe
1757 * @dev_priv: i915 private structure
1758 * @plane: plane to enable
1759 * @pipe: pipe being fed
1761 * Enable @plane on @pipe, making sure that @pipe is running first.
1763 static void intel_enable_plane(struct drm_i915_private
*dev_priv
,
1764 enum plane plane
, enum pipe pipe
)
1769 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1770 assert_pipe_enabled(dev_priv
, pipe
);
1772 reg
= DSPCNTR(plane
);
1773 val
= I915_READ(reg
);
1774 if (val
& DISPLAY_PLANE_ENABLE
)
1777 I915_WRITE(reg
, val
| DISPLAY_PLANE_ENABLE
);
1778 intel_flush_display_plane(dev_priv
, plane
);
1779 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1783 * intel_disable_plane - disable a display plane
1784 * @dev_priv: i915 private structure
1785 * @plane: plane to disable
1786 * @pipe: pipe consuming the data
1788 * Disable @plane; should be an independent operation.
1790 static void intel_disable_plane(struct drm_i915_private
*dev_priv
,
1791 enum plane plane
, enum pipe pipe
)
1796 reg
= DSPCNTR(plane
);
1797 val
= I915_READ(reg
);
1798 if ((val
& DISPLAY_PLANE_ENABLE
) == 0)
1801 I915_WRITE(reg
, val
& ~DISPLAY_PLANE_ENABLE
);
1802 intel_flush_display_plane(dev_priv
, plane
);
1803 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1806 static bool need_vtd_wa(struct drm_device
*dev
)
1808 #ifdef CONFIG_INTEL_IOMMU
1809 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
1816 intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
1817 struct drm_i915_gem_object
*obj
,
1818 struct intel_ring_buffer
*pipelined
)
1820 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1824 switch (obj
->tiling_mode
) {
1825 case I915_TILING_NONE
:
1826 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
1827 alignment
= 128 * 1024;
1828 else if (INTEL_INFO(dev
)->gen
>= 4)
1829 alignment
= 4 * 1024;
1831 alignment
= 64 * 1024;
1834 /* pin() will align the object as required by fence */
1838 /* Despite that we check this in framebuffer_init userspace can
1839 * screw us over and change the tiling after the fact. Only
1840 * pinned buffers can't change their tiling. */
1841 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1847 /* Note that the w/a also requires 64 PTE of padding following the
1848 * bo. We currently fill all unused PTE with the shadow page and so
1849 * we should always have valid PTE following the scanout preventing
1852 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
1853 alignment
= 256 * 1024;
1855 dev_priv
->mm
.interruptible
= false;
1856 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
);
1858 goto err_interruptible
;
1860 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1861 * fence, whereas 965+ only requires a fence if using
1862 * framebuffer compression. For simplicity, we always install
1863 * a fence as the cost is not that onerous.
1865 ret
= i915_gem_object_get_fence(obj
);
1869 i915_gem_object_pin_fence(obj
);
1871 dev_priv
->mm
.interruptible
= true;
1875 i915_gem_object_unpin(obj
);
1877 dev_priv
->mm
.interruptible
= true;
1881 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
)
1883 i915_gem_object_unpin_fence(obj
);
1884 i915_gem_object_unpin(obj
);
1887 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1888 * is assumed to be a power-of-two. */
1889 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
1890 unsigned int tiling_mode
,
1894 if (tiling_mode
!= I915_TILING_NONE
) {
1895 unsigned int tile_rows
, tiles
;
1900 tiles
= *x
/ (512/cpp
);
1903 return tile_rows
* pitch
* 8 + tiles
* 4096;
1905 unsigned int offset
;
1907 offset
= *y
* pitch
+ *x
* cpp
;
1909 *x
= (offset
& 4095) / cpp
;
1910 return offset
& -4096;
1914 static int i9xx_update_plane(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
1917 struct drm_device
*dev
= crtc
->dev
;
1918 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1919 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1920 struct intel_framebuffer
*intel_fb
;
1921 struct drm_i915_gem_object
*obj
;
1922 int plane
= intel_crtc
->plane
;
1923 unsigned long linear_offset
;
1932 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane
));
1936 intel_fb
= to_intel_framebuffer(fb
);
1937 obj
= intel_fb
->obj
;
1939 reg
= DSPCNTR(plane
);
1940 dspcntr
= I915_READ(reg
);
1941 /* Mask out pixel format bits in case we change it */
1942 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
1943 switch (fb
->pixel_format
) {
1945 dspcntr
|= DISPPLANE_8BPP
;
1947 case DRM_FORMAT_XRGB1555
:
1948 case DRM_FORMAT_ARGB1555
:
1949 dspcntr
|= DISPPLANE_BGRX555
;
1951 case DRM_FORMAT_RGB565
:
1952 dspcntr
|= DISPPLANE_BGRX565
;
1954 case DRM_FORMAT_XRGB8888
:
1955 case DRM_FORMAT_ARGB8888
:
1956 dspcntr
|= DISPPLANE_BGRX888
;
1958 case DRM_FORMAT_XBGR8888
:
1959 case DRM_FORMAT_ABGR8888
:
1960 dspcntr
|= DISPPLANE_RGBX888
;
1962 case DRM_FORMAT_XRGB2101010
:
1963 case DRM_FORMAT_ARGB2101010
:
1964 dspcntr
|= DISPPLANE_BGRX101010
;
1966 case DRM_FORMAT_XBGR2101010
:
1967 case DRM_FORMAT_ABGR2101010
:
1968 dspcntr
|= DISPPLANE_RGBX101010
;
1974 if (INTEL_INFO(dev
)->gen
>= 4) {
1975 if (obj
->tiling_mode
!= I915_TILING_NONE
)
1976 dspcntr
|= DISPPLANE_TILED
;
1978 dspcntr
&= ~DISPPLANE_TILED
;
1982 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
1984 I915_WRITE(reg
, dspcntr
);
1986 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
1988 if (INTEL_INFO(dev
)->gen
>= 4) {
1989 intel_crtc
->dspaddr_offset
=
1990 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
1991 fb
->bits_per_pixel
/ 8,
1993 linear_offset
-= intel_crtc
->dspaddr_offset
;
1995 intel_crtc
->dspaddr_offset
= linear_offset
;
1998 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1999 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2001 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2002 if (INTEL_INFO(dev
)->gen
>= 4) {
2003 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2004 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2005 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2006 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2008 I915_WRITE(DSPADDR(plane
), i915_gem_obj_ggtt_offset(obj
) + linear_offset
);
2014 static int ironlake_update_plane(struct drm_crtc
*crtc
,
2015 struct drm_framebuffer
*fb
, int x
, int y
)
2017 struct drm_device
*dev
= crtc
->dev
;
2018 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2019 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2020 struct intel_framebuffer
*intel_fb
;
2021 struct drm_i915_gem_object
*obj
;
2022 int plane
= intel_crtc
->plane
;
2023 unsigned long linear_offset
;
2033 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane
));
2037 intel_fb
= to_intel_framebuffer(fb
);
2038 obj
= intel_fb
->obj
;
2040 reg
= DSPCNTR(plane
);
2041 dspcntr
= I915_READ(reg
);
2042 /* Mask out pixel format bits in case we change it */
2043 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2044 switch (fb
->pixel_format
) {
2046 dspcntr
|= DISPPLANE_8BPP
;
2048 case DRM_FORMAT_RGB565
:
2049 dspcntr
|= DISPPLANE_BGRX565
;
2051 case DRM_FORMAT_XRGB8888
:
2052 case DRM_FORMAT_ARGB8888
:
2053 dspcntr
|= DISPPLANE_BGRX888
;
2055 case DRM_FORMAT_XBGR8888
:
2056 case DRM_FORMAT_ABGR8888
:
2057 dspcntr
|= DISPPLANE_RGBX888
;
2059 case DRM_FORMAT_XRGB2101010
:
2060 case DRM_FORMAT_ARGB2101010
:
2061 dspcntr
|= DISPPLANE_BGRX101010
;
2063 case DRM_FORMAT_XBGR2101010
:
2064 case DRM_FORMAT_ABGR2101010
:
2065 dspcntr
|= DISPPLANE_RGBX101010
;
2071 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2072 dspcntr
|= DISPPLANE_TILED
;
2074 dspcntr
&= ~DISPPLANE_TILED
;
2077 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2079 I915_WRITE(reg
, dspcntr
);
2081 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2082 intel_crtc
->dspaddr_offset
=
2083 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2084 fb
->bits_per_pixel
/ 8,
2086 linear_offset
-= intel_crtc
->dspaddr_offset
;
2088 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2089 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2091 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2092 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2093 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2094 if (IS_HASWELL(dev
)) {
2095 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2097 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2098 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2105 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2107 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2108 int x
, int y
, enum mode_set_atomic state
)
2110 struct drm_device
*dev
= crtc
->dev
;
2111 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2113 if (dev_priv
->display
.disable_fbc
)
2114 dev_priv
->display
.disable_fbc(dev
);
2115 intel_increase_pllclock(crtc
);
2117 return dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2120 void intel_display_handle_reset(struct drm_device
*dev
)
2122 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2123 struct drm_crtc
*crtc
;
2126 * Flips in the rings have been nuked by the reset,
2127 * so complete all pending flips so that user space
2128 * will get its events and not get stuck.
2130 * Also update the base address of all primary
2131 * planes to the the last fb to make sure we're
2132 * showing the correct fb after a reset.
2134 * Need to make two loops over the crtcs so that we
2135 * don't try to grab a crtc mutex before the
2136 * pending_flip_queue really got woken up.
2139 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2140 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2141 enum plane plane
= intel_crtc
->plane
;
2143 intel_prepare_page_flip(dev
, plane
);
2144 intel_finish_page_flip_plane(dev
, plane
);
2147 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2148 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2150 mutex_lock(&crtc
->mutex
);
2151 if (intel_crtc
->active
)
2152 dev_priv
->display
.update_plane(crtc
, crtc
->fb
,
2154 mutex_unlock(&crtc
->mutex
);
2159 intel_finish_fb(struct drm_framebuffer
*old_fb
)
2161 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(old_fb
)->obj
;
2162 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2163 bool was_interruptible
= dev_priv
->mm
.interruptible
;
2166 /* Big Hammer, we also need to ensure that any pending
2167 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2168 * current scanout is retired before unpinning the old
2171 * This should only fail upon a hung GPU, in which case we
2172 * can safely continue.
2174 dev_priv
->mm
.interruptible
= false;
2175 ret
= i915_gem_object_finish_gpu(obj
);
2176 dev_priv
->mm
.interruptible
= was_interruptible
;
2181 static void intel_crtc_update_sarea_pos(struct drm_crtc
*crtc
, int x
, int y
)
2183 struct drm_device
*dev
= crtc
->dev
;
2184 struct drm_i915_master_private
*master_priv
;
2185 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2187 if (!dev
->primary
->master
)
2190 master_priv
= dev
->primary
->master
->driver_priv
;
2191 if (!master_priv
->sarea_priv
)
2194 switch (intel_crtc
->pipe
) {
2196 master_priv
->sarea_priv
->pipeA_x
= x
;
2197 master_priv
->sarea_priv
->pipeA_y
= y
;
2200 master_priv
->sarea_priv
->pipeB_x
= x
;
2201 master_priv
->sarea_priv
->pipeB_y
= y
;
2209 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2210 struct drm_framebuffer
*fb
)
2212 struct drm_device
*dev
= crtc
->dev
;
2213 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2214 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2215 struct drm_framebuffer
*old_fb
;
2220 DRM_ERROR("No FB bound\n");
2224 if (intel_crtc
->plane
> INTEL_INFO(dev
)->num_pipes
) {
2225 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2226 plane_name(intel_crtc
->plane
),
2227 INTEL_INFO(dev
)->num_pipes
);
2231 mutex_lock(&dev
->struct_mutex
);
2232 ret
= intel_pin_and_fence_fb_obj(dev
,
2233 to_intel_framebuffer(fb
)->obj
,
2236 mutex_unlock(&dev
->struct_mutex
);
2237 DRM_ERROR("pin & fence failed\n");
2241 /* Update pipe size and adjust fitter if needed */
2242 if (i915_fastboot
) {
2243 I915_WRITE(PIPESRC(intel_crtc
->pipe
),
2244 ((crtc
->mode
.hdisplay
- 1) << 16) |
2245 (crtc
->mode
.vdisplay
- 1));
2246 if (!intel_crtc
->config
.pch_pfit
.size
&&
2247 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) ||
2248 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
2249 I915_WRITE(PF_CTL(intel_crtc
->pipe
), 0);
2250 I915_WRITE(PF_WIN_POS(intel_crtc
->pipe
), 0);
2251 I915_WRITE(PF_WIN_SZ(intel_crtc
->pipe
), 0);
2255 ret
= dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2257 intel_unpin_fb_obj(to_intel_framebuffer(fb
)->obj
);
2258 mutex_unlock(&dev
->struct_mutex
);
2259 DRM_ERROR("failed to update base address\n");
2269 if (intel_crtc
->active
&& old_fb
!= fb
)
2270 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2271 intel_unpin_fb_obj(to_intel_framebuffer(old_fb
)->obj
);
2274 intel_update_fbc(dev
);
2275 mutex_unlock(&dev
->struct_mutex
);
2277 intel_crtc_update_sarea_pos(crtc
, x
, y
);
2282 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
2284 struct drm_device
*dev
= crtc
->dev
;
2285 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2286 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2287 int pipe
= intel_crtc
->pipe
;
2290 /* enable normal train */
2291 reg
= FDI_TX_CTL(pipe
);
2292 temp
= I915_READ(reg
);
2293 if (IS_IVYBRIDGE(dev
)) {
2294 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2295 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2297 temp
&= ~FDI_LINK_TRAIN_NONE
;
2298 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2300 I915_WRITE(reg
, temp
);
2302 reg
= FDI_RX_CTL(pipe
);
2303 temp
= I915_READ(reg
);
2304 if (HAS_PCH_CPT(dev
)) {
2305 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2306 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2308 temp
&= ~FDI_LINK_TRAIN_NONE
;
2309 temp
|= FDI_LINK_TRAIN_NONE
;
2311 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2313 /* wait one idle pattern time */
2317 /* IVB wants error correction enabled */
2318 if (IS_IVYBRIDGE(dev
))
2319 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
2320 FDI_FE_ERRC_ENABLE
);
2323 static bool pipe_has_enabled_pch(struct intel_crtc
*intel_crtc
)
2325 return intel_crtc
->base
.enabled
&& intel_crtc
->config
.has_pch_encoder
;
2328 static void ivb_modeset_global_resources(struct drm_device
*dev
)
2330 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2331 struct intel_crtc
*pipe_B_crtc
=
2332 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
2333 struct intel_crtc
*pipe_C_crtc
=
2334 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]);
2338 * When everything is off disable fdi C so that we could enable fdi B
2339 * with all lanes. Note that we don't care about enabled pipes without
2340 * an enabled pch encoder.
2342 if (!pipe_has_enabled_pch(pipe_B_crtc
) &&
2343 !pipe_has_enabled_pch(pipe_C_crtc
)) {
2344 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
2345 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
2347 temp
= I915_READ(SOUTH_CHICKEN1
);
2348 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
2349 DRM_DEBUG_KMS("disabling fdi C rx\n");
2350 I915_WRITE(SOUTH_CHICKEN1
, temp
);
2354 /* The FDI link training functions for ILK/Ibexpeak. */
2355 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
2357 struct drm_device
*dev
= crtc
->dev
;
2358 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2359 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2360 int pipe
= intel_crtc
->pipe
;
2361 int plane
= intel_crtc
->plane
;
2362 u32 reg
, temp
, tries
;
2364 /* FDI needs bits from pipe & plane first */
2365 assert_pipe_enabled(dev_priv
, pipe
);
2366 assert_plane_enabled(dev_priv
, plane
);
2368 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2370 reg
= FDI_RX_IMR(pipe
);
2371 temp
= I915_READ(reg
);
2372 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2373 temp
&= ~FDI_RX_BIT_LOCK
;
2374 I915_WRITE(reg
, temp
);
2378 /* enable CPU FDI TX and PCH FDI RX */
2379 reg
= FDI_TX_CTL(pipe
);
2380 temp
= I915_READ(reg
);
2381 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2382 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2383 temp
&= ~FDI_LINK_TRAIN_NONE
;
2384 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2385 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2387 reg
= FDI_RX_CTL(pipe
);
2388 temp
= I915_READ(reg
);
2389 temp
&= ~FDI_LINK_TRAIN_NONE
;
2390 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2391 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2396 /* Ironlake workaround, enable clock pointer after FDI enable*/
2397 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2398 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
2399 FDI_RX_PHASE_SYNC_POINTER_EN
);
2401 reg
= FDI_RX_IIR(pipe
);
2402 for (tries
= 0; tries
< 5; tries
++) {
2403 temp
= I915_READ(reg
);
2404 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2406 if ((temp
& FDI_RX_BIT_LOCK
)) {
2407 DRM_DEBUG_KMS("FDI train 1 done.\n");
2408 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2413 DRM_ERROR("FDI train 1 fail!\n");
2416 reg
= FDI_TX_CTL(pipe
);
2417 temp
= I915_READ(reg
);
2418 temp
&= ~FDI_LINK_TRAIN_NONE
;
2419 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2420 I915_WRITE(reg
, temp
);
2422 reg
= FDI_RX_CTL(pipe
);
2423 temp
= I915_READ(reg
);
2424 temp
&= ~FDI_LINK_TRAIN_NONE
;
2425 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2426 I915_WRITE(reg
, temp
);
2431 reg
= FDI_RX_IIR(pipe
);
2432 for (tries
= 0; tries
< 5; tries
++) {
2433 temp
= I915_READ(reg
);
2434 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2436 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2437 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2438 DRM_DEBUG_KMS("FDI train 2 done.\n");
2443 DRM_ERROR("FDI train 2 fail!\n");
2445 DRM_DEBUG_KMS("FDI train done\n");
2449 static const int snb_b_fdi_train_param
[] = {
2450 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
2451 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
2452 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
2453 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
2456 /* The FDI link training functions for SNB/Cougarpoint. */
2457 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
2459 struct drm_device
*dev
= crtc
->dev
;
2460 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2461 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2462 int pipe
= intel_crtc
->pipe
;
2463 u32 reg
, temp
, i
, retry
;
2465 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2467 reg
= FDI_RX_IMR(pipe
);
2468 temp
= I915_READ(reg
);
2469 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2470 temp
&= ~FDI_RX_BIT_LOCK
;
2471 I915_WRITE(reg
, temp
);
2476 /* enable CPU FDI TX and PCH FDI RX */
2477 reg
= FDI_TX_CTL(pipe
);
2478 temp
= I915_READ(reg
);
2479 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2480 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2481 temp
&= ~FDI_LINK_TRAIN_NONE
;
2482 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2483 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2485 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2486 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2488 I915_WRITE(FDI_RX_MISC(pipe
),
2489 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2491 reg
= FDI_RX_CTL(pipe
);
2492 temp
= I915_READ(reg
);
2493 if (HAS_PCH_CPT(dev
)) {
2494 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2495 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2497 temp
&= ~FDI_LINK_TRAIN_NONE
;
2498 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2500 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2505 for (i
= 0; i
< 4; i
++) {
2506 reg
= FDI_TX_CTL(pipe
);
2507 temp
= I915_READ(reg
);
2508 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2509 temp
|= snb_b_fdi_train_param
[i
];
2510 I915_WRITE(reg
, temp
);
2515 for (retry
= 0; retry
< 5; retry
++) {
2516 reg
= FDI_RX_IIR(pipe
);
2517 temp
= I915_READ(reg
);
2518 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2519 if (temp
& FDI_RX_BIT_LOCK
) {
2520 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2521 DRM_DEBUG_KMS("FDI train 1 done.\n");
2530 DRM_ERROR("FDI train 1 fail!\n");
2533 reg
= FDI_TX_CTL(pipe
);
2534 temp
= I915_READ(reg
);
2535 temp
&= ~FDI_LINK_TRAIN_NONE
;
2536 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2538 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2540 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2542 I915_WRITE(reg
, temp
);
2544 reg
= FDI_RX_CTL(pipe
);
2545 temp
= I915_READ(reg
);
2546 if (HAS_PCH_CPT(dev
)) {
2547 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2548 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2550 temp
&= ~FDI_LINK_TRAIN_NONE
;
2551 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2553 I915_WRITE(reg
, temp
);
2558 for (i
= 0; i
< 4; i
++) {
2559 reg
= FDI_TX_CTL(pipe
);
2560 temp
= I915_READ(reg
);
2561 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2562 temp
|= snb_b_fdi_train_param
[i
];
2563 I915_WRITE(reg
, temp
);
2568 for (retry
= 0; retry
< 5; retry
++) {
2569 reg
= FDI_RX_IIR(pipe
);
2570 temp
= I915_READ(reg
);
2571 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2572 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2573 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2574 DRM_DEBUG_KMS("FDI train 2 done.\n");
2583 DRM_ERROR("FDI train 2 fail!\n");
2585 DRM_DEBUG_KMS("FDI train done.\n");
2588 /* Manual link training for Ivy Bridge A0 parts */
2589 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
2591 struct drm_device
*dev
= crtc
->dev
;
2592 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2593 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2594 int pipe
= intel_crtc
->pipe
;
2597 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2599 reg
= FDI_RX_IMR(pipe
);
2600 temp
= I915_READ(reg
);
2601 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2602 temp
&= ~FDI_RX_BIT_LOCK
;
2603 I915_WRITE(reg
, temp
);
2608 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2609 I915_READ(FDI_RX_IIR(pipe
)));
2611 /* enable CPU FDI TX and PCH FDI RX */
2612 reg
= FDI_TX_CTL(pipe
);
2613 temp
= I915_READ(reg
);
2614 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2615 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2616 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
2617 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
2618 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2619 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2620 temp
|= FDI_COMPOSITE_SYNC
;
2621 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2623 I915_WRITE(FDI_RX_MISC(pipe
),
2624 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2626 reg
= FDI_RX_CTL(pipe
);
2627 temp
= I915_READ(reg
);
2628 temp
&= ~FDI_LINK_TRAIN_AUTO
;
2629 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2630 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2631 temp
|= FDI_COMPOSITE_SYNC
;
2632 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2637 for (i
= 0; i
< 4; i
++) {
2638 reg
= FDI_TX_CTL(pipe
);
2639 temp
= I915_READ(reg
);
2640 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2641 temp
|= snb_b_fdi_train_param
[i
];
2642 I915_WRITE(reg
, temp
);
2647 reg
= FDI_RX_IIR(pipe
);
2648 temp
= I915_READ(reg
);
2649 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2651 if (temp
& FDI_RX_BIT_LOCK
||
2652 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
2653 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2654 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i
);
2659 DRM_ERROR("FDI train 1 fail!\n");
2662 reg
= FDI_TX_CTL(pipe
);
2663 temp
= I915_READ(reg
);
2664 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2665 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
2666 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2667 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2668 I915_WRITE(reg
, temp
);
2670 reg
= FDI_RX_CTL(pipe
);
2671 temp
= I915_READ(reg
);
2672 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2673 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2674 I915_WRITE(reg
, temp
);
2679 for (i
= 0; i
< 4; i
++) {
2680 reg
= FDI_TX_CTL(pipe
);
2681 temp
= I915_READ(reg
);
2682 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2683 temp
|= snb_b_fdi_train_param
[i
];
2684 I915_WRITE(reg
, temp
);
2689 reg
= FDI_RX_IIR(pipe
);
2690 temp
= I915_READ(reg
);
2691 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2693 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2694 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2695 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i
);
2700 DRM_ERROR("FDI train 2 fail!\n");
2702 DRM_DEBUG_KMS("FDI train done.\n");
2705 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
2707 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2708 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2709 int pipe
= intel_crtc
->pipe
;
2713 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2714 reg
= FDI_RX_CTL(pipe
);
2715 temp
= I915_READ(reg
);
2716 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
2717 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2718 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2719 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
2724 /* Switch from Rawclk to PCDclk */
2725 temp
= I915_READ(reg
);
2726 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
2731 /* Enable CPU FDI TX PLL, always on for Ironlake */
2732 reg
= FDI_TX_CTL(pipe
);
2733 temp
= I915_READ(reg
);
2734 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
2735 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
2742 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
2744 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2745 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2746 int pipe
= intel_crtc
->pipe
;
2749 /* Switch from PCDclk to Rawclk */
2750 reg
= FDI_RX_CTL(pipe
);
2751 temp
= I915_READ(reg
);
2752 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
2754 /* Disable CPU FDI TX PLL */
2755 reg
= FDI_TX_CTL(pipe
);
2756 temp
= I915_READ(reg
);
2757 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
2762 reg
= FDI_RX_CTL(pipe
);
2763 temp
= I915_READ(reg
);
2764 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
2766 /* Wait for the clocks to turn off. */
2771 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
2773 struct drm_device
*dev
= crtc
->dev
;
2774 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2775 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2776 int pipe
= intel_crtc
->pipe
;
2779 /* disable CPU FDI tx and PCH FDI rx */
2780 reg
= FDI_TX_CTL(pipe
);
2781 temp
= I915_READ(reg
);
2782 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
2785 reg
= FDI_RX_CTL(pipe
);
2786 temp
= I915_READ(reg
);
2787 temp
&= ~(0x7 << 16);
2788 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2789 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
2794 /* Ironlake workaround, disable clock pointer after downing FDI */
2795 if (HAS_PCH_IBX(dev
)) {
2796 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2799 /* still set train pattern 1 */
2800 reg
= FDI_TX_CTL(pipe
);
2801 temp
= I915_READ(reg
);
2802 temp
&= ~FDI_LINK_TRAIN_NONE
;
2803 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2804 I915_WRITE(reg
, temp
);
2806 reg
= FDI_RX_CTL(pipe
);
2807 temp
= I915_READ(reg
);
2808 if (HAS_PCH_CPT(dev
)) {
2809 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2810 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2812 temp
&= ~FDI_LINK_TRAIN_NONE
;
2813 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2815 /* BPC in FDI rx is consistent with that in PIPECONF */
2816 temp
&= ~(0x07 << 16);
2817 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2818 I915_WRITE(reg
, temp
);
2824 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
2826 struct drm_device
*dev
= crtc
->dev
;
2827 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2828 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2829 unsigned long flags
;
2832 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
2833 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
2836 spin_lock_irqsave(&dev
->event_lock
, flags
);
2837 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
2838 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2843 static void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
2845 struct drm_device
*dev
= crtc
->dev
;
2846 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2848 if (crtc
->fb
== NULL
)
2851 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
2853 wait_event(dev_priv
->pending_flip_queue
,
2854 !intel_crtc_has_pending_flip(crtc
));
2856 mutex_lock(&dev
->struct_mutex
);
2857 intel_finish_fb(crtc
->fb
);
2858 mutex_unlock(&dev
->struct_mutex
);
2861 /* Program iCLKIP clock to the desired frequency */
2862 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
2864 struct drm_device
*dev
= crtc
->dev
;
2865 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2866 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
2869 mutex_lock(&dev_priv
->dpio_lock
);
2871 /* It is necessary to ungate the pixclk gate prior to programming
2872 * the divisors, and gate it back when it is done.
2874 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
2876 /* Disable SSCCTL */
2877 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
2878 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
2882 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2883 if (crtc
->mode
.clock
== 20000) {
2888 /* The iCLK virtual clock root frequency is in MHz,
2889 * but the crtc->mode.clock in in KHz. To get the divisors,
2890 * it is necessary to divide one by another, so we
2891 * convert the virtual clock precision to KHz here for higher
2894 u32 iclk_virtual_root_freq
= 172800 * 1000;
2895 u32 iclk_pi_range
= 64;
2896 u32 desired_divisor
, msb_divisor_value
, pi_value
;
2898 desired_divisor
= (iclk_virtual_root_freq
/ crtc
->mode
.clock
);
2899 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
2900 pi_value
= desired_divisor
% iclk_pi_range
;
2903 divsel
= msb_divisor_value
- 2;
2904 phaseinc
= pi_value
;
2907 /* This should not happen with any sane values */
2908 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
2909 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
2910 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
2911 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
2913 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2920 /* Program SSCDIVINTPHASE6 */
2921 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
2922 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
2923 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
2924 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
2925 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
2926 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
2927 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
2928 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
2930 /* Program SSCAUXDIV */
2931 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
2932 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2933 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
2934 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
2936 /* Enable modulator and associated divider */
2937 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
2938 temp
&= ~SBI_SSCCTL_DISABLE
;
2939 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
2941 /* Wait for initialization time */
2944 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
2946 mutex_unlock(&dev_priv
->dpio_lock
);
2949 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
2950 enum pipe pch_transcoder
)
2952 struct drm_device
*dev
= crtc
->base
.dev
;
2953 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2954 enum transcoder cpu_transcoder
= crtc
->config
.cpu_transcoder
;
2956 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
2957 I915_READ(HTOTAL(cpu_transcoder
)));
2958 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
2959 I915_READ(HBLANK(cpu_transcoder
)));
2960 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
2961 I915_READ(HSYNC(cpu_transcoder
)));
2963 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
2964 I915_READ(VTOTAL(cpu_transcoder
)));
2965 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
2966 I915_READ(VBLANK(cpu_transcoder
)));
2967 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
2968 I915_READ(VSYNC(cpu_transcoder
)));
2969 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
2970 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
2974 * Enable PCH resources required for PCH ports:
2976 * - FDI training & RX/TX
2977 * - update transcoder timings
2978 * - DP transcoding bits
2981 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
2983 struct drm_device
*dev
= crtc
->dev
;
2984 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2985 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2986 int pipe
= intel_crtc
->pipe
;
2989 assert_pch_transcoder_disabled(dev_priv
, pipe
);
2991 /* Write the TU size bits before fdi link training, so that error
2992 * detection works. */
2993 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
2994 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
2996 /* For PCH output, training FDI link */
2997 dev_priv
->display
.fdi_link_train(crtc
);
2999 /* XXX: pch pll's can be enabled any time before we enable the PCH
3000 * transcoder, and we actually should do this to not upset any PCH
3001 * transcoder that already use the clock when we share it.
3003 * Note that enable_shared_dpll tries to do the right thing, but
3004 * get_shared_dpll unconditionally resets the pll - we need that to have
3005 * the right LVDS enable sequence. */
3006 ironlake_enable_shared_dpll(intel_crtc
);
3008 if (HAS_PCH_CPT(dev
)) {
3011 temp
= I915_READ(PCH_DPLL_SEL
);
3012 temp
|= TRANS_DPLL_ENABLE(pipe
);
3013 sel
= TRANS_DPLLB_SEL(pipe
);
3014 if (intel_crtc
->config
.shared_dpll
== DPLL_ID_PCH_PLL_B
)
3018 I915_WRITE(PCH_DPLL_SEL
, temp
);
3021 /* set transcoder timing, panel must allow it */
3022 assert_panel_unlocked(dev_priv
, pipe
);
3023 ironlake_pch_transcoder_set_timings(intel_crtc
, pipe
);
3025 intel_fdi_normal_train(crtc
);
3027 /* For PCH DP, enable TRANS_DP_CTL */
3028 if (HAS_PCH_CPT(dev
) &&
3029 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
3030 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3031 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
3032 reg
= TRANS_DP_CTL(pipe
);
3033 temp
= I915_READ(reg
);
3034 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
3035 TRANS_DP_SYNC_MASK
|
3037 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
3038 TRANS_DP_ENH_FRAMING
);
3039 temp
|= bpc
<< 9; /* same format but at 11:9 */
3041 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
3042 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
3043 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
3044 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
3046 switch (intel_trans_dp_port_sel(crtc
)) {
3048 temp
|= TRANS_DP_PORT_SEL_B
;
3051 temp
|= TRANS_DP_PORT_SEL_C
;
3054 temp
|= TRANS_DP_PORT_SEL_D
;
3060 I915_WRITE(reg
, temp
);
3063 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
3066 static void lpt_pch_enable(struct drm_crtc
*crtc
)
3068 struct drm_device
*dev
= crtc
->dev
;
3069 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3070 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3071 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
3073 assert_pch_transcoder_disabled(dev_priv
, TRANSCODER_A
);
3075 lpt_program_iclkip(crtc
);
3077 /* Set transcoder timing. */
3078 ironlake_pch_transcoder_set_timings(intel_crtc
, PIPE_A
);
3080 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
3083 static void intel_put_shared_dpll(struct intel_crtc
*crtc
)
3085 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3090 if (pll
->refcount
== 0) {
3091 WARN(1, "bad %s refcount\n", pll
->name
);
3095 if (--pll
->refcount
== 0) {
3097 WARN_ON(pll
->active
);
3100 crtc
->config
.shared_dpll
= DPLL_ID_PRIVATE
;
3103 static struct intel_shared_dpll
*intel_get_shared_dpll(struct intel_crtc
*crtc
)
3105 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
3106 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3107 enum intel_dpll_id i
;
3110 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3111 crtc
->base
.base
.id
, pll
->name
);
3112 intel_put_shared_dpll(crtc
);
3115 if (HAS_PCH_IBX(dev_priv
->dev
)) {
3116 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3117 i
= (enum intel_dpll_id
) crtc
->pipe
;
3118 pll
= &dev_priv
->shared_dplls
[i
];
3120 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3121 crtc
->base
.base
.id
, pll
->name
);
3126 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3127 pll
= &dev_priv
->shared_dplls
[i
];
3129 /* Only want to check enabled timings first */
3130 if (pll
->refcount
== 0)
3133 if (memcmp(&crtc
->config
.dpll_hw_state
, &pll
->hw_state
,
3134 sizeof(pll
->hw_state
)) == 0) {
3135 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3137 pll
->name
, pll
->refcount
, pll
->active
);
3143 /* Ok no matching timings, maybe there's a free one? */
3144 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3145 pll
= &dev_priv
->shared_dplls
[i
];
3146 if (pll
->refcount
== 0) {
3147 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3148 crtc
->base
.base
.id
, pll
->name
);
3156 crtc
->config
.shared_dpll
= i
;
3157 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll
->name
,
3158 pipe_name(crtc
->pipe
));
3160 if (pll
->active
== 0) {
3161 memcpy(&pll
->hw_state
, &crtc
->config
.dpll_hw_state
,
3162 sizeof(pll
->hw_state
));
3164 DRM_DEBUG_DRIVER("setting up %s\n", pll
->name
);
3166 assert_shared_dpll_disabled(dev_priv
, pll
);
3168 pll
->mode_set(dev_priv
, pll
);
3175 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
3177 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3178 int dslreg
= PIPEDSL(pipe
);
3181 temp
= I915_READ(dslreg
);
3183 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
3184 if (wait_for(I915_READ(dslreg
) != temp
, 5))
3185 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
3189 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
3191 struct drm_device
*dev
= crtc
->base
.dev
;
3192 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3193 int pipe
= crtc
->pipe
;
3195 if (crtc
->config
.pch_pfit
.size
) {
3196 /* Force use of hard-coded filter coefficients
3197 * as some pre-programmed values are broken,
3200 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
3201 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
3202 PF_PIPE_SEL_IVB(pipe
));
3204 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
3205 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
.pch_pfit
.pos
);
3206 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
.pch_pfit
.size
);
3210 static void intel_enable_planes(struct drm_crtc
*crtc
)
3212 struct drm_device
*dev
= crtc
->dev
;
3213 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
3214 struct intel_plane
*intel_plane
;
3216 list_for_each_entry(intel_plane
, &dev
->mode_config
.plane_list
, base
.head
)
3217 if (intel_plane
->pipe
== pipe
)
3218 intel_plane_restore(&intel_plane
->base
);
3221 static void intel_disable_planes(struct drm_crtc
*crtc
)
3223 struct drm_device
*dev
= crtc
->dev
;
3224 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
3225 struct intel_plane
*intel_plane
;
3227 list_for_each_entry(intel_plane
, &dev
->mode_config
.plane_list
, base
.head
)
3228 if (intel_plane
->pipe
== pipe
)
3229 intel_plane_disable(&intel_plane
->base
);
3232 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
3234 struct drm_device
*dev
= crtc
->dev
;
3235 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3236 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3237 struct intel_encoder
*encoder
;
3238 int pipe
= intel_crtc
->pipe
;
3239 int plane
= intel_crtc
->plane
;
3241 WARN_ON(!crtc
->enabled
);
3243 if (intel_crtc
->active
)
3246 intel_crtc
->active
= true;
3248 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
3249 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
3251 intel_update_watermarks(dev
);
3253 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3254 if (encoder
->pre_enable
)
3255 encoder
->pre_enable(encoder
);
3257 if (intel_crtc
->config
.has_pch_encoder
) {
3258 /* Note: FDI PLL enabling _must_ be done before we enable the
3259 * cpu pipes, hence this is separate from all the other fdi/pch
3261 ironlake_fdi_pll_enable(intel_crtc
);
3263 assert_fdi_tx_disabled(dev_priv
, pipe
);
3264 assert_fdi_rx_disabled(dev_priv
, pipe
);
3267 ironlake_pfit_enable(intel_crtc
);
3270 * On ILK+ LUT must be loaded before the pipe is running but with
3273 intel_crtc_load_lut(crtc
);
3275 intel_enable_pipe(dev_priv
, pipe
,
3276 intel_crtc
->config
.has_pch_encoder
);
3277 intel_enable_plane(dev_priv
, plane
, pipe
);
3278 intel_enable_planes(crtc
);
3279 intel_crtc_update_cursor(crtc
, true);
3281 if (intel_crtc
->config
.has_pch_encoder
)
3282 ironlake_pch_enable(crtc
);
3284 mutex_lock(&dev
->struct_mutex
);
3285 intel_update_fbc(dev
);
3286 mutex_unlock(&dev
->struct_mutex
);
3288 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3289 encoder
->enable(encoder
);
3291 if (HAS_PCH_CPT(dev
))
3292 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
3295 * There seems to be a race in PCH platform hw (at least on some
3296 * outputs) where an enabled pipe still completes any pageflip right
3297 * away (as if the pipe is off) instead of waiting for vblank. As soon
3298 * as the first vblank happend, everything works as expected. Hence just
3299 * wait for one vblank before returning to avoid strange things
3302 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3305 /* IPS only exists on ULT machines and is tied to pipe A. */
3306 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
3308 return HAS_IPS(crtc
->base
.dev
) && crtc
->pipe
== PIPE_A
;
3311 static void hsw_enable_ips(struct intel_crtc
*crtc
)
3313 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
3315 if (!crtc
->config
.ips_enabled
)
3318 /* We can only enable IPS after we enable a plane and wait for a vblank.
3319 * We guarantee that the plane is enabled by calling intel_enable_ips
3320 * only after intel_enable_plane. And intel_enable_plane already waits
3321 * for a vblank, so all we need to do here is to enable the IPS bit. */
3322 assert_plane_enabled(dev_priv
, crtc
->plane
);
3323 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
3326 static void hsw_disable_ips(struct intel_crtc
*crtc
)
3328 struct drm_device
*dev
= crtc
->base
.dev
;
3329 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3331 if (!crtc
->config
.ips_enabled
)
3334 assert_plane_enabled(dev_priv
, crtc
->plane
);
3335 I915_WRITE(IPS_CTL
, 0);
3337 /* We need to wait for a vblank before we can disable the plane. */
3338 intel_wait_for_vblank(dev
, crtc
->pipe
);
3341 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
3343 struct drm_device
*dev
= crtc
->dev
;
3344 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3345 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3346 struct intel_encoder
*encoder
;
3347 int pipe
= intel_crtc
->pipe
;
3348 int plane
= intel_crtc
->plane
;
3350 WARN_ON(!crtc
->enabled
);
3352 if (intel_crtc
->active
)
3355 intel_crtc
->active
= true;
3357 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
3358 if (intel_crtc
->config
.has_pch_encoder
)
3359 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
3361 intel_update_watermarks(dev
);
3363 if (intel_crtc
->config
.has_pch_encoder
)
3364 dev_priv
->display
.fdi_link_train(crtc
);
3366 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3367 if (encoder
->pre_enable
)
3368 encoder
->pre_enable(encoder
);
3370 intel_ddi_enable_pipe_clock(intel_crtc
);
3372 ironlake_pfit_enable(intel_crtc
);
3375 * On ILK+ LUT must be loaded before the pipe is running but with
3378 intel_crtc_load_lut(crtc
);
3380 intel_ddi_set_pipe_settings(crtc
);
3381 intel_ddi_enable_transcoder_func(crtc
);
3383 intel_enable_pipe(dev_priv
, pipe
,
3384 intel_crtc
->config
.has_pch_encoder
);
3385 intel_enable_plane(dev_priv
, plane
, pipe
);
3386 intel_enable_planes(crtc
);
3387 intel_crtc_update_cursor(crtc
, true);
3389 hsw_enable_ips(intel_crtc
);
3391 if (intel_crtc
->config
.has_pch_encoder
)
3392 lpt_pch_enable(crtc
);
3394 mutex_lock(&dev
->struct_mutex
);
3395 intel_update_fbc(dev
);
3396 mutex_unlock(&dev
->struct_mutex
);
3398 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3399 encoder
->enable(encoder
);
3402 * There seems to be a race in PCH platform hw (at least on some
3403 * outputs) where an enabled pipe still completes any pageflip right
3404 * away (as if the pipe is off) instead of waiting for vblank. As soon
3405 * as the first vblank happend, everything works as expected. Hence just
3406 * wait for one vblank before returning to avoid strange things
3409 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3412 static void ironlake_pfit_disable(struct intel_crtc
*crtc
)
3414 struct drm_device
*dev
= crtc
->base
.dev
;
3415 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3416 int pipe
= crtc
->pipe
;
3418 /* To avoid upsetting the power well on haswell only disable the pfit if
3419 * it's in use. The hw state code will make sure we get this right. */
3420 if (crtc
->config
.pch_pfit
.size
) {
3421 I915_WRITE(PF_CTL(pipe
), 0);
3422 I915_WRITE(PF_WIN_POS(pipe
), 0);
3423 I915_WRITE(PF_WIN_SZ(pipe
), 0);
3427 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
3429 struct drm_device
*dev
= crtc
->dev
;
3430 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3431 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3432 struct intel_encoder
*encoder
;
3433 int pipe
= intel_crtc
->pipe
;
3434 int plane
= intel_crtc
->plane
;
3438 if (!intel_crtc
->active
)
3441 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3442 encoder
->disable(encoder
);
3444 intel_crtc_wait_for_pending_flips(crtc
);
3445 drm_vblank_off(dev
, pipe
);
3447 if (dev_priv
->fbc
.plane
== plane
)
3448 intel_disable_fbc(dev
);
3450 intel_crtc_update_cursor(crtc
, false);
3451 intel_disable_planes(crtc
);
3452 intel_disable_plane(dev_priv
, plane
, pipe
);
3454 if (intel_crtc
->config
.has_pch_encoder
)
3455 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, false);
3457 intel_disable_pipe(dev_priv
, pipe
);
3459 ironlake_pfit_disable(intel_crtc
);
3461 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3462 if (encoder
->post_disable
)
3463 encoder
->post_disable(encoder
);
3465 if (intel_crtc
->config
.has_pch_encoder
) {
3466 ironlake_fdi_disable(crtc
);
3468 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
3469 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
3471 if (HAS_PCH_CPT(dev
)) {
3472 /* disable TRANS_DP_CTL */
3473 reg
= TRANS_DP_CTL(pipe
);
3474 temp
= I915_READ(reg
);
3475 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
3476 TRANS_DP_PORT_SEL_MASK
);
3477 temp
|= TRANS_DP_PORT_SEL_NONE
;
3478 I915_WRITE(reg
, temp
);
3480 /* disable DPLL_SEL */
3481 temp
= I915_READ(PCH_DPLL_SEL
);
3482 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
3483 I915_WRITE(PCH_DPLL_SEL
, temp
);
3486 /* disable PCH DPLL */
3487 intel_disable_shared_dpll(intel_crtc
);
3489 ironlake_fdi_pll_disable(intel_crtc
);
3492 intel_crtc
->active
= false;
3493 intel_update_watermarks(dev
);
3495 mutex_lock(&dev
->struct_mutex
);
3496 intel_update_fbc(dev
);
3497 mutex_unlock(&dev
->struct_mutex
);
3500 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
3502 struct drm_device
*dev
= crtc
->dev
;
3503 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3504 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3505 struct intel_encoder
*encoder
;
3506 int pipe
= intel_crtc
->pipe
;
3507 int plane
= intel_crtc
->plane
;
3508 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
3510 if (!intel_crtc
->active
)
3513 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3514 encoder
->disable(encoder
);
3516 intel_crtc_wait_for_pending_flips(crtc
);
3517 drm_vblank_off(dev
, pipe
);
3519 /* FBC must be disabled before disabling the plane on HSW. */
3520 if (dev_priv
->fbc
.plane
== plane
)
3521 intel_disable_fbc(dev
);
3523 hsw_disable_ips(intel_crtc
);
3525 intel_crtc_update_cursor(crtc
, false);
3526 intel_disable_planes(crtc
);
3527 intel_disable_plane(dev_priv
, plane
, pipe
);
3529 if (intel_crtc
->config
.has_pch_encoder
)
3530 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, false);
3531 intel_disable_pipe(dev_priv
, pipe
);
3533 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
3535 ironlake_pfit_disable(intel_crtc
);
3537 intel_ddi_disable_pipe_clock(intel_crtc
);
3539 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3540 if (encoder
->post_disable
)
3541 encoder
->post_disable(encoder
);
3543 if (intel_crtc
->config
.has_pch_encoder
) {
3544 lpt_disable_pch_transcoder(dev_priv
);
3545 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
3546 intel_ddi_fdi_disable(crtc
);
3549 intel_crtc
->active
= false;
3550 intel_update_watermarks(dev
);
3552 mutex_lock(&dev
->struct_mutex
);
3553 intel_update_fbc(dev
);
3554 mutex_unlock(&dev
->struct_mutex
);
3557 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
3559 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3560 intel_put_shared_dpll(intel_crtc
);
3563 static void haswell_crtc_off(struct drm_crtc
*crtc
)
3565 intel_ddi_put_crtc_pll(crtc
);
3568 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
3570 if (!enable
&& intel_crtc
->overlay
) {
3571 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3572 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3574 mutex_lock(&dev
->struct_mutex
);
3575 dev_priv
->mm
.interruptible
= false;
3576 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
3577 dev_priv
->mm
.interruptible
= true;
3578 mutex_unlock(&dev
->struct_mutex
);
3581 /* Let userspace switch the overlay on again. In most cases userspace
3582 * has to recompute where to put it anyway.
3587 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3588 * cursor plane briefly if not already running after enabling the display
3590 * This workaround avoids occasional blank screens when self refresh is
3594 g4x_fixup_plane(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
3596 u32 cntl
= I915_READ(CURCNTR(pipe
));
3598 if ((cntl
& CURSOR_MODE
) == 0) {
3599 u32 fw_bcl_self
= I915_READ(FW_BLC_SELF
);
3601 I915_WRITE(FW_BLC_SELF
, fw_bcl_self
& ~FW_BLC_SELF_EN
);
3602 I915_WRITE(CURCNTR(pipe
), CURSOR_MODE_64_ARGB_AX
);
3603 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
3604 I915_WRITE(CURCNTR(pipe
), cntl
);
3605 I915_WRITE(CURBASE(pipe
), I915_READ(CURBASE(pipe
)));
3606 I915_WRITE(FW_BLC_SELF
, fw_bcl_self
);
3610 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
3612 struct drm_device
*dev
= crtc
->base
.dev
;
3613 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3614 struct intel_crtc_config
*pipe_config
= &crtc
->config
;
3616 if (!crtc
->config
.gmch_pfit
.control
)
3620 * The panel fitter should only be adjusted whilst the pipe is disabled,
3621 * according to register description and PRM.
3623 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
3624 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
3626 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
3627 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
3629 /* Border color in case we don't scale up to the full screen. Black by
3630 * default, change to something else for debugging. */
3631 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
3634 static void valleyview_crtc_enable(struct drm_crtc
*crtc
)
3636 struct drm_device
*dev
= crtc
->dev
;
3637 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3638 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3639 struct intel_encoder
*encoder
;
3640 int pipe
= intel_crtc
->pipe
;
3641 int plane
= intel_crtc
->plane
;
3643 WARN_ON(!crtc
->enabled
);
3645 if (intel_crtc
->active
)
3648 intel_crtc
->active
= true;
3649 intel_update_watermarks(dev
);
3651 mutex_lock(&dev_priv
->dpio_lock
);
3653 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3654 if (encoder
->pre_pll_enable
)
3655 encoder
->pre_pll_enable(encoder
);
3657 vlv_enable_pll(dev_priv
, pipe
);
3659 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3660 if (encoder
->pre_enable
)
3661 encoder
->pre_enable(encoder
);
3663 /* VLV wants encoder enabling _before_ the pipe is up. */
3664 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3665 encoder
->enable(encoder
);
3667 i9xx_pfit_enable(intel_crtc
);
3669 intel_crtc_load_lut(crtc
);
3671 intel_enable_pipe(dev_priv
, pipe
, false);
3672 intel_enable_plane(dev_priv
, plane
, pipe
);
3673 intel_enable_planes(crtc
);
3674 intel_crtc_update_cursor(crtc
, true);
3676 intel_update_fbc(dev
);
3678 mutex_unlock(&dev_priv
->dpio_lock
);
3681 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
3683 struct drm_device
*dev
= crtc
->dev
;
3684 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3685 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3686 struct intel_encoder
*encoder
;
3687 int pipe
= intel_crtc
->pipe
;
3688 int plane
= intel_crtc
->plane
;
3690 WARN_ON(!crtc
->enabled
);
3692 if (intel_crtc
->active
)
3695 intel_crtc
->active
= true;
3696 intel_update_watermarks(dev
);
3698 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3699 if (encoder
->pre_enable
)
3700 encoder
->pre_enable(encoder
);
3702 i9xx_enable_pll(intel_crtc
);
3704 i9xx_pfit_enable(intel_crtc
);
3706 intel_crtc_load_lut(crtc
);
3708 intel_enable_pipe(dev_priv
, pipe
, false);
3709 intel_enable_plane(dev_priv
, plane
, pipe
);
3710 intel_enable_planes(crtc
);
3711 /* The fixup needs to happen before cursor is enabled */
3713 g4x_fixup_plane(dev_priv
, pipe
);
3714 intel_crtc_update_cursor(crtc
, true);
3716 /* Give the overlay scaler a chance to enable if it's on this pipe */
3717 intel_crtc_dpms_overlay(intel_crtc
, true);
3719 intel_update_fbc(dev
);
3721 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3722 encoder
->enable(encoder
);
3725 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
3727 struct drm_device
*dev
= crtc
->base
.dev
;
3728 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3730 if (!crtc
->config
.gmch_pfit
.control
)
3733 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
3735 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3736 I915_READ(PFIT_CONTROL
));
3737 I915_WRITE(PFIT_CONTROL
, 0);
3740 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
3742 struct drm_device
*dev
= crtc
->dev
;
3743 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3744 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3745 struct intel_encoder
*encoder
;
3746 int pipe
= intel_crtc
->pipe
;
3747 int plane
= intel_crtc
->plane
;
3749 if (!intel_crtc
->active
)
3752 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3753 encoder
->disable(encoder
);
3755 /* Give the overlay scaler a chance to disable if it's on this pipe */
3756 intel_crtc_wait_for_pending_flips(crtc
);
3757 drm_vblank_off(dev
, pipe
);
3759 if (dev_priv
->fbc
.plane
== plane
)
3760 intel_disable_fbc(dev
);
3762 intel_crtc_dpms_overlay(intel_crtc
, false);
3763 intel_crtc_update_cursor(crtc
, false);
3764 intel_disable_planes(crtc
);
3765 intel_disable_plane(dev_priv
, plane
, pipe
);
3767 intel_disable_pipe(dev_priv
, pipe
);
3769 i9xx_pfit_disable(intel_crtc
);
3771 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3772 if (encoder
->post_disable
)
3773 encoder
->post_disable(encoder
);
3775 intel_disable_pll(dev_priv
, pipe
);
3777 intel_crtc
->active
= false;
3778 intel_update_fbc(dev
);
3779 intel_update_watermarks(dev
);
3782 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
3786 static void intel_crtc_update_sarea(struct drm_crtc
*crtc
,
3789 struct drm_device
*dev
= crtc
->dev
;
3790 struct drm_i915_master_private
*master_priv
;
3791 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3792 int pipe
= intel_crtc
->pipe
;
3794 if (!dev
->primary
->master
)
3797 master_priv
= dev
->primary
->master
->driver_priv
;
3798 if (!master_priv
->sarea_priv
)
3803 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3804 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3807 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3808 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3811 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe
));
3817 * Sets the power management mode of the pipe and plane.
3819 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
3821 struct drm_device
*dev
= crtc
->dev
;
3822 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3823 struct intel_encoder
*intel_encoder
;
3824 bool enable
= false;
3826 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
3827 enable
|= intel_encoder
->connectors_active
;
3830 dev_priv
->display
.crtc_enable(crtc
);
3832 dev_priv
->display
.crtc_disable(crtc
);
3834 intel_crtc_update_sarea(crtc
, enable
);
3837 static void intel_crtc_disable(struct drm_crtc
*crtc
)
3839 struct drm_device
*dev
= crtc
->dev
;
3840 struct drm_connector
*connector
;
3841 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3842 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3844 /* crtc should still be enabled when we disable it. */
3845 WARN_ON(!crtc
->enabled
);
3847 dev_priv
->display
.crtc_disable(crtc
);
3848 intel_crtc
->eld_vld
= false;
3849 intel_crtc_update_sarea(crtc
, false);
3850 dev_priv
->display
.off(crtc
);
3852 assert_plane_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->plane
);
3853 assert_pipe_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->pipe
);
3856 mutex_lock(&dev
->struct_mutex
);
3857 intel_unpin_fb_obj(to_intel_framebuffer(crtc
->fb
)->obj
);
3858 mutex_unlock(&dev
->struct_mutex
);
3862 /* Update computed state. */
3863 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
3864 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
3867 if (connector
->encoder
->crtc
!= crtc
)
3870 connector
->dpms
= DRM_MODE_DPMS_OFF
;
3871 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
3875 void intel_modeset_disable(struct drm_device
*dev
)
3877 struct drm_crtc
*crtc
;
3879 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
3881 intel_crtc_disable(crtc
);
3885 void intel_encoder_destroy(struct drm_encoder
*encoder
)
3887 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
3889 drm_encoder_cleanup(encoder
);
3890 kfree(intel_encoder
);
3893 /* Simple dpms helper for encodres with just one connector, no cloning and only
3894 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3895 * state of the entire output pipe. */
3896 void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
3898 if (mode
== DRM_MODE_DPMS_ON
) {
3899 encoder
->connectors_active
= true;
3901 intel_crtc_update_dpms(encoder
->base
.crtc
);
3903 encoder
->connectors_active
= false;
3905 intel_crtc_update_dpms(encoder
->base
.crtc
);
3909 /* Cross check the actual hw state with our own modeset state tracking (and it's
3910 * internal consistency). */
3911 static void intel_connector_check_state(struct intel_connector
*connector
)
3913 if (connector
->get_hw_state(connector
)) {
3914 struct intel_encoder
*encoder
= connector
->encoder
;
3915 struct drm_crtc
*crtc
;
3916 bool encoder_enabled
;
3919 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3920 connector
->base
.base
.id
,
3921 drm_get_connector_name(&connector
->base
));
3923 WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
3924 "wrong connector dpms state\n");
3925 WARN(connector
->base
.encoder
!= &encoder
->base
,
3926 "active connector not linked to encoder\n");
3927 WARN(!encoder
->connectors_active
,
3928 "encoder->connectors_active not set\n");
3930 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
3931 WARN(!encoder_enabled
, "encoder not enabled\n");
3932 if (WARN_ON(!encoder
->base
.crtc
))
3935 crtc
= encoder
->base
.crtc
;
3937 WARN(!crtc
->enabled
, "crtc not enabled\n");
3938 WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
3939 WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
3940 "encoder active on the wrong pipe\n");
3944 /* Even simpler default implementation, if there's really no special case to
3946 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
3948 struct intel_encoder
*encoder
= intel_attached_encoder(connector
);
3950 /* All the simple cases only support two dpms states. */
3951 if (mode
!= DRM_MODE_DPMS_ON
)
3952 mode
= DRM_MODE_DPMS_OFF
;
3954 if (mode
== connector
->dpms
)
3957 connector
->dpms
= mode
;
3959 /* Only need to change hw state when actually enabled */
3960 if (encoder
->base
.crtc
)
3961 intel_encoder_dpms(encoder
, mode
);
3963 WARN_ON(encoder
->connectors_active
!= false);
3965 intel_modeset_check_state(connector
->dev
);
3968 /* Simple connector->get_hw_state implementation for encoders that support only
3969 * one connector and no cloning and hence the encoder state determines the state
3970 * of the connector. */
3971 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
3974 struct intel_encoder
*encoder
= connector
->encoder
;
3976 return encoder
->get_hw_state(encoder
, &pipe
);
3979 static bool ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
3980 struct intel_crtc_config
*pipe_config
)
3982 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3983 struct intel_crtc
*pipe_B_crtc
=
3984 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
3986 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3987 pipe_name(pipe
), pipe_config
->fdi_lanes
);
3988 if (pipe_config
->fdi_lanes
> 4) {
3989 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3990 pipe_name(pipe
), pipe_config
->fdi_lanes
);
3994 if (IS_HASWELL(dev
)) {
3995 if (pipe_config
->fdi_lanes
> 2) {
3996 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3997 pipe_config
->fdi_lanes
);
4004 if (INTEL_INFO(dev
)->num_pipes
== 2)
4007 /* Ivybridge 3 pipe is really complicated */
4012 if (dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]->enabled
&&
4013 pipe_config
->fdi_lanes
> 2) {
4014 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4015 pipe_name(pipe
), pipe_config
->fdi_lanes
);
4020 if (!pipe_has_enabled_pch(pipe_B_crtc
) ||
4021 pipe_B_crtc
->config
.fdi_lanes
<= 2) {
4022 if (pipe_config
->fdi_lanes
> 2) {
4023 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4024 pipe_name(pipe
), pipe_config
->fdi_lanes
);
4028 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4038 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
4039 struct intel_crtc_config
*pipe_config
)
4041 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4042 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
4043 int lane
, link_bw
, fdi_dotclock
;
4044 bool setup_ok
, needs_recompute
= false;
4047 /* FDI is a binary signal running at ~2.7GHz, encoding
4048 * each output octet as 10 bits. The actual frequency
4049 * is stored as a divider into a 100MHz clock, and the
4050 * mode pixel clock is stored in units of 1KHz.
4051 * Hence the bw of each lane in terms of the mode signal
4054 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
4056 fdi_dotclock
= adjusted_mode
->clock
;
4057 fdi_dotclock
/= pipe_config
->pixel_multiplier
;
4059 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
4060 pipe_config
->pipe_bpp
);
4062 pipe_config
->fdi_lanes
= lane
;
4064 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
4065 link_bw
, &pipe_config
->fdi_m_n
);
4067 setup_ok
= ironlake_check_fdi_lanes(intel_crtc
->base
.dev
,
4068 intel_crtc
->pipe
, pipe_config
);
4069 if (!setup_ok
&& pipe_config
->pipe_bpp
> 6*3) {
4070 pipe_config
->pipe_bpp
-= 2*3;
4071 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4072 pipe_config
->pipe_bpp
);
4073 needs_recompute
= true;
4074 pipe_config
->bw_constrained
= true;
4079 if (needs_recompute
)
4082 return setup_ok
? 0 : -EINVAL
;
4085 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
4086 struct intel_crtc_config
*pipe_config
)
4088 pipe_config
->ips_enabled
= i915_enable_ips
&&
4089 hsw_crtc_supports_ips(crtc
) &&
4090 pipe_config
->pipe_bpp
== 24;
4093 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
4094 struct intel_crtc_config
*pipe_config
)
4096 struct drm_device
*dev
= crtc
->base
.dev
;
4097 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
4099 if (HAS_PCH_SPLIT(dev
)) {
4100 /* FDI link clock is fixed at 2.7G */
4101 if (pipe_config
->requested_mode
.clock
* 3
4102 > IRONLAKE_FDI_FREQ
* 4)
4106 /* All interlaced capable intel hw wants timings in frames. Note though
4107 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4108 * timings, so we need to be careful not to clobber these.*/
4109 if (!pipe_config
->timings_set
)
4110 drm_mode_set_crtcinfo(adjusted_mode
, 0);
4112 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4113 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4115 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
4116 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
4119 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) && pipe_config
->pipe_bpp
> 10*3) {
4120 pipe_config
->pipe_bpp
= 10*3; /* 12bpc is gen5+ */
4121 } else if (INTEL_INFO(dev
)->gen
<= 4 && pipe_config
->pipe_bpp
> 8*3) {
4122 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4124 pipe_config
->pipe_bpp
= 8*3;
4128 hsw_compute_ips_config(crtc
, pipe_config
);
4130 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4131 * clock survives for now. */
4132 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
4133 pipe_config
->shared_dpll
= crtc
->config
.shared_dpll
;
4135 if (pipe_config
->has_pch_encoder
)
4136 return ironlake_fdi_compute_config(crtc
, pipe_config
);
4141 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
4143 return 400000; /* FIXME */
4146 static int i945_get_display_clock_speed(struct drm_device
*dev
)
4151 static int i915_get_display_clock_speed(struct drm_device
*dev
)
4156 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
4161 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
4165 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
4167 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
4170 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
4171 case GC_DISPLAY_CLOCK_333_MHZ
:
4174 case GC_DISPLAY_CLOCK_190_200_MHZ
:
4180 static int i865_get_display_clock_speed(struct drm_device
*dev
)
4185 static int i855_get_display_clock_speed(struct drm_device
*dev
)
4188 /* Assume that the hardware is in the high speed state. This
4189 * should be the default.
4191 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
4192 case GC_CLOCK_133_200
:
4193 case GC_CLOCK_100_200
:
4195 case GC_CLOCK_166_250
:
4197 case GC_CLOCK_100_133
:
4201 /* Shouldn't happen */
4205 static int i830_get_display_clock_speed(struct drm_device
*dev
)
4211 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
4213 while (*num
> DATA_LINK_M_N_MASK
||
4214 *den
> DATA_LINK_M_N_MASK
) {
4220 static void compute_m_n(unsigned int m
, unsigned int n
,
4221 uint32_t *ret_m
, uint32_t *ret_n
)
4223 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
4224 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
4225 intel_reduce_m_n_ratio(ret_m
, ret_n
);
4229 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
4230 int pixel_clock
, int link_clock
,
4231 struct intel_link_m_n
*m_n
)
4235 compute_m_n(bits_per_pixel
* pixel_clock
,
4236 link_clock
* nlanes
* 8,
4237 &m_n
->gmch_m
, &m_n
->gmch_n
);
4239 compute_m_n(pixel_clock
, link_clock
,
4240 &m_n
->link_m
, &m_n
->link_n
);
4243 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
4245 if (i915_panel_use_ssc
>= 0)
4246 return i915_panel_use_ssc
!= 0;
4247 return dev_priv
->vbt
.lvds_use_ssc
4248 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
4251 static int vlv_get_refclk(struct drm_crtc
*crtc
)
4253 struct drm_device
*dev
= crtc
->dev
;
4254 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4255 int refclk
= 27000; /* for DP & HDMI */
4257 return 100000; /* only one validated so far */
4259 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
4261 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
4262 if (intel_panel_use_ssc(dev_priv
))
4266 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
)) {
4273 static int i9xx_get_refclk(struct drm_crtc
*crtc
, int num_connectors
)
4275 struct drm_device
*dev
= crtc
->dev
;
4276 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4279 if (IS_VALLEYVIEW(dev
)) {
4280 refclk
= vlv_get_refclk(crtc
);
4281 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4282 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
4283 refclk
= dev_priv
->vbt
.lvds_ssc_freq
* 1000;
4284 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4286 } else if (!IS_GEN2(dev
)) {
4295 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
4297 return (1 << dpll
->n
) << 16 | dpll
->m2
;
4300 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
4302 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
4305 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
4306 intel_clock_t
*reduced_clock
)
4308 struct drm_device
*dev
= crtc
->base
.dev
;
4309 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4310 int pipe
= crtc
->pipe
;
4313 if (IS_PINEVIEW(dev
)) {
4314 fp
= pnv_dpll_compute_fp(&crtc
->config
.dpll
);
4316 fp2
= pnv_dpll_compute_fp(reduced_clock
);
4318 fp
= i9xx_dpll_compute_fp(&crtc
->config
.dpll
);
4320 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
4323 I915_WRITE(FP0(pipe
), fp
);
4324 crtc
->config
.dpll_hw_state
.fp0
= fp
;
4326 crtc
->lowfreq_avail
= false;
4327 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4328 reduced_clock
&& i915_powersave
) {
4329 I915_WRITE(FP1(pipe
), fp2
);
4330 crtc
->config
.dpll_hw_state
.fp1
= fp2
;
4331 crtc
->lowfreq_avail
= true;
4333 I915_WRITE(FP1(pipe
), fp
);
4334 crtc
->config
.dpll_hw_state
.fp1
= fp
;
4338 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
)
4343 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4344 * and set it to a reasonable value instead.
4346 reg_val
= vlv_dpio_read(dev_priv
, DPIO_IREF(1));
4347 reg_val
&= 0xffffff00;
4348 reg_val
|= 0x00000030;
4349 vlv_dpio_write(dev_priv
, DPIO_IREF(1), reg_val
);
4351 reg_val
= vlv_dpio_read(dev_priv
, DPIO_CALIBRATION
);
4352 reg_val
&= 0x8cffffff;
4353 reg_val
= 0x8c000000;
4354 vlv_dpio_write(dev_priv
, DPIO_CALIBRATION
, reg_val
);
4356 reg_val
= vlv_dpio_read(dev_priv
, DPIO_IREF(1));
4357 reg_val
&= 0xffffff00;
4358 vlv_dpio_write(dev_priv
, DPIO_IREF(1), reg_val
);
4360 reg_val
= vlv_dpio_read(dev_priv
, DPIO_CALIBRATION
);
4361 reg_val
&= 0x00ffffff;
4362 reg_val
|= 0xb0000000;
4363 vlv_dpio_write(dev_priv
, DPIO_CALIBRATION
, reg_val
);
4366 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
4367 struct intel_link_m_n
*m_n
)
4369 struct drm_device
*dev
= crtc
->base
.dev
;
4370 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4371 int pipe
= crtc
->pipe
;
4373 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
4374 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
4375 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
4376 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
4379 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
4380 struct intel_link_m_n
*m_n
)
4382 struct drm_device
*dev
= crtc
->base
.dev
;
4383 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4384 int pipe
= crtc
->pipe
;
4385 enum transcoder transcoder
= crtc
->config
.cpu_transcoder
;
4387 if (INTEL_INFO(dev
)->gen
>= 5) {
4388 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
4389 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
4390 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
4391 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
4393 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
4394 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
4395 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
4396 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
4400 static void intel_dp_set_m_n(struct intel_crtc
*crtc
)
4402 if (crtc
->config
.has_pch_encoder
)
4403 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
4405 intel_cpu_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
4408 static void vlv_update_pll(struct intel_crtc
*crtc
)
4410 struct drm_device
*dev
= crtc
->base
.dev
;
4411 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4412 struct intel_encoder
*encoder
;
4413 int pipe
= crtc
->pipe
;
4415 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
4417 u32 coreclk
, reg_val
, dpll_md
;
4419 mutex_lock(&dev_priv
->dpio_lock
);
4421 is_hdmi
= intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
);
4423 bestn
= crtc
->config
.dpll
.n
;
4424 bestm1
= crtc
->config
.dpll
.m1
;
4425 bestm2
= crtc
->config
.dpll
.m2
;
4426 bestp1
= crtc
->config
.dpll
.p1
;
4427 bestp2
= crtc
->config
.dpll
.p2
;
4429 /* See eDP HDMI DPIO driver vbios notes doc */
4431 /* PLL B needs special handling */
4433 vlv_pllb_recal_opamp(dev_priv
);
4435 /* Set up Tx target for periodic Rcomp update */
4436 vlv_dpio_write(dev_priv
, DPIO_IREF_BCAST
, 0x0100000f);
4438 /* Disable target IRef on PLL */
4439 reg_val
= vlv_dpio_read(dev_priv
, DPIO_IREF_CTL(pipe
));
4440 reg_val
&= 0x00ffffff;
4441 vlv_dpio_write(dev_priv
, DPIO_IREF_CTL(pipe
), reg_val
);
4443 /* Disable fast lock */
4444 vlv_dpio_write(dev_priv
, DPIO_FASTCLK_DISABLE
, 0x610);
4446 /* Set idtafcrecal before PLL is enabled */
4447 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
4448 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
4449 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
4450 mdiv
|= (1 << DPIO_K_SHIFT
);
4453 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4454 * but we don't support that).
4455 * Note: don't use the DAC post divider as it seems unstable.
4457 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
4458 vlv_dpio_write(dev_priv
, DPIO_DIV(pipe
), mdiv
);
4460 mdiv
|= DPIO_ENABLE_CALIBRATION
;
4461 vlv_dpio_write(dev_priv
, DPIO_DIV(pipe
), mdiv
);
4463 /* Set HBR and RBR LPF coefficients */
4464 if (crtc
->config
.port_clock
== 162000 ||
4465 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_ANALOG
) ||
4466 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
))
4467 vlv_dpio_write(dev_priv
, DPIO_LPF_COEFF(pipe
),
4470 vlv_dpio_write(dev_priv
, DPIO_LPF_COEFF(pipe
),
4473 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
) ||
4474 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
)) {
4475 /* Use SSC source */
4477 vlv_dpio_write(dev_priv
, DPIO_REFSFR(pipe
),
4480 vlv_dpio_write(dev_priv
, DPIO_REFSFR(pipe
),
4482 } else { /* HDMI or VGA */
4483 /* Use bend source */
4485 vlv_dpio_write(dev_priv
, DPIO_REFSFR(pipe
),
4488 vlv_dpio_write(dev_priv
, DPIO_REFSFR(pipe
),
4492 coreclk
= vlv_dpio_read(dev_priv
, DPIO_CORE_CLK(pipe
));
4493 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
4494 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
) ||
4495 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
))
4496 coreclk
|= 0x01000000;
4497 vlv_dpio_write(dev_priv
, DPIO_CORE_CLK(pipe
), coreclk
);
4499 vlv_dpio_write(dev_priv
, DPIO_PLL_CML(pipe
), 0x87871000);
4501 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
4502 if (encoder
->pre_pll_enable
)
4503 encoder
->pre_pll_enable(encoder
);
4505 /* Enable DPIO clock input */
4506 dpll
= DPLL_EXT_BUFFER_ENABLE_VLV
| DPLL_REFA_CLK_ENABLE_VLV
|
4507 DPLL_VGA_MODE_DIS
| DPLL_INTEGRATED_CLOCK_VLV
;
4509 dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
4511 dpll
|= DPLL_VCO_ENABLE
;
4512 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
4514 I915_WRITE(DPLL(pipe
), dpll
);
4515 POSTING_READ(DPLL(pipe
));
4518 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
4519 DRM_ERROR("DPLL %d failed to lock\n", pipe
);
4521 dpll_md
= (crtc
->config
.pixel_multiplier
- 1)
4522 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4523 crtc
->config
.dpll_hw_state
.dpll_md
= dpll_md
;
4525 I915_WRITE(DPLL_MD(pipe
), dpll_md
);
4526 POSTING_READ(DPLL_MD(pipe
));
4528 if (crtc
->config
.has_dp_encoder
)
4529 intel_dp_set_m_n(crtc
);
4531 mutex_unlock(&dev_priv
->dpio_lock
);
4534 static void i9xx_update_pll(struct intel_crtc
*crtc
,
4535 intel_clock_t
*reduced_clock
,
4538 struct drm_device
*dev
= crtc
->base
.dev
;
4539 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4542 struct dpll
*clock
= &crtc
->config
.dpll
;
4544 i9xx_update_pll_dividers(crtc
, reduced_clock
);
4546 is_sdvo
= intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_SDVO
) ||
4547 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
);
4549 dpll
= DPLL_VGA_MODE_DIS
;
4551 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
))
4552 dpll
|= DPLLB_MODE_LVDS
;
4554 dpll
|= DPLLB_MODE_DAC_SERIAL
;
4556 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
4557 dpll
|= (crtc
->config
.pixel_multiplier
- 1)
4558 << SDVO_MULTIPLIER_SHIFT_HIRES
;
4562 dpll
|= DPLL_SDVO_HIGH_SPEED
;
4564 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
))
4565 dpll
|= DPLL_SDVO_HIGH_SPEED
;
4567 /* compute bitmask from p1 value */
4568 if (IS_PINEVIEW(dev
))
4569 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
4571 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4572 if (IS_G4X(dev
) && reduced_clock
)
4573 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
4575 switch (clock
->p2
) {
4577 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
4580 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
4583 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
4586 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
4589 if (INTEL_INFO(dev
)->gen
>= 4)
4590 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
4592 if (crtc
->config
.sdvo_tv_clock
)
4593 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
4594 else if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4595 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4596 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4598 dpll
|= PLL_REF_INPUT_DREFCLK
;
4600 dpll
|= DPLL_VCO_ENABLE
;
4601 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
4603 if (INTEL_INFO(dev
)->gen
>= 4) {
4604 u32 dpll_md
= (crtc
->config
.pixel_multiplier
- 1)
4605 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4606 crtc
->config
.dpll_hw_state
.dpll_md
= dpll_md
;
4609 if (crtc
->config
.has_dp_encoder
)
4610 intel_dp_set_m_n(crtc
);
4613 static void i8xx_update_pll(struct intel_crtc
*crtc
,
4614 intel_clock_t
*reduced_clock
,
4617 struct drm_device
*dev
= crtc
->base
.dev
;
4618 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4620 struct dpll
*clock
= &crtc
->config
.dpll
;
4622 i9xx_update_pll_dividers(crtc
, reduced_clock
);
4624 dpll
= DPLL_VGA_MODE_DIS
;
4626 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
)) {
4627 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4630 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
4632 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4634 dpll
|= PLL_P2_DIVIDE_BY_4
;
4637 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DVO
))
4638 dpll
|= DPLL_DVO_2X_MODE
;
4640 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4641 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4642 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4644 dpll
|= PLL_REF_INPUT_DREFCLK
;
4646 dpll
|= DPLL_VCO_ENABLE
;
4647 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
4650 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
4652 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4653 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4654 enum pipe pipe
= intel_crtc
->pipe
;
4655 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
4656 struct drm_display_mode
*adjusted_mode
=
4657 &intel_crtc
->config
.adjusted_mode
;
4658 struct drm_display_mode
*mode
= &intel_crtc
->config
.requested_mode
;
4659 uint32_t vsyncshift
, crtc_vtotal
, crtc_vblank_end
;
4661 /* We need to be careful not to changed the adjusted mode, for otherwise
4662 * the hw state checker will get angry at the mismatch. */
4663 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
4664 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
4666 if (!IS_GEN2(dev
) && adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
4667 /* the chip adds 2 halflines automatically */
4669 crtc_vblank_end
-= 1;
4670 vsyncshift
= adjusted_mode
->crtc_hsync_start
4671 - adjusted_mode
->crtc_htotal
/ 2;
4676 if (INTEL_INFO(dev
)->gen
> 3)
4677 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
4679 I915_WRITE(HTOTAL(cpu_transcoder
),
4680 (adjusted_mode
->crtc_hdisplay
- 1) |
4681 ((adjusted_mode
->crtc_htotal
- 1) << 16));
4682 I915_WRITE(HBLANK(cpu_transcoder
),
4683 (adjusted_mode
->crtc_hblank_start
- 1) |
4684 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
4685 I915_WRITE(HSYNC(cpu_transcoder
),
4686 (adjusted_mode
->crtc_hsync_start
- 1) |
4687 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
4689 I915_WRITE(VTOTAL(cpu_transcoder
),
4690 (adjusted_mode
->crtc_vdisplay
- 1) |
4691 ((crtc_vtotal
- 1) << 16));
4692 I915_WRITE(VBLANK(cpu_transcoder
),
4693 (adjusted_mode
->crtc_vblank_start
- 1) |
4694 ((crtc_vblank_end
- 1) << 16));
4695 I915_WRITE(VSYNC(cpu_transcoder
),
4696 (adjusted_mode
->crtc_vsync_start
- 1) |
4697 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
4699 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4700 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4701 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4703 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
4704 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
4705 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
4707 /* pipesrc controls the size that is scaled from, which should
4708 * always be the user's requested size.
4710 I915_WRITE(PIPESRC(pipe
),
4711 ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
4714 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
4715 struct intel_crtc_config
*pipe_config
)
4717 struct drm_device
*dev
= crtc
->base
.dev
;
4718 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4719 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
4722 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
4723 pipe_config
->adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
4724 pipe_config
->adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
4725 tmp
= I915_READ(HBLANK(cpu_transcoder
));
4726 pipe_config
->adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
4727 pipe_config
->adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
4728 tmp
= I915_READ(HSYNC(cpu_transcoder
));
4729 pipe_config
->adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
4730 pipe_config
->adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
4732 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
4733 pipe_config
->adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
4734 pipe_config
->adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
4735 tmp
= I915_READ(VBLANK(cpu_transcoder
));
4736 pipe_config
->adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
4737 pipe_config
->adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
4738 tmp
= I915_READ(VSYNC(cpu_transcoder
));
4739 pipe_config
->adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
4740 pipe_config
->adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
4742 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
4743 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
4744 pipe_config
->adjusted_mode
.crtc_vtotal
+= 1;
4745 pipe_config
->adjusted_mode
.crtc_vblank_end
+= 1;
4748 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
4749 pipe_config
->requested_mode
.vdisplay
= (tmp
& 0xffff) + 1;
4750 pipe_config
->requested_mode
.hdisplay
= ((tmp
>> 16) & 0xffff) + 1;
4753 static void intel_crtc_mode_from_pipe_config(struct intel_crtc
*intel_crtc
,
4754 struct intel_crtc_config
*pipe_config
)
4756 struct drm_crtc
*crtc
= &intel_crtc
->base
;
4758 crtc
->mode
.hdisplay
= pipe_config
->adjusted_mode
.crtc_hdisplay
;
4759 crtc
->mode
.htotal
= pipe_config
->adjusted_mode
.crtc_htotal
;
4760 crtc
->mode
.hsync_start
= pipe_config
->adjusted_mode
.crtc_hsync_start
;
4761 crtc
->mode
.hsync_end
= pipe_config
->adjusted_mode
.crtc_hsync_end
;
4763 crtc
->mode
.vdisplay
= pipe_config
->adjusted_mode
.crtc_vdisplay
;
4764 crtc
->mode
.vtotal
= pipe_config
->adjusted_mode
.crtc_vtotal
;
4765 crtc
->mode
.vsync_start
= pipe_config
->adjusted_mode
.crtc_vsync_start
;
4766 crtc
->mode
.vsync_end
= pipe_config
->adjusted_mode
.crtc_vsync_end
;
4768 crtc
->mode
.flags
= pipe_config
->adjusted_mode
.flags
;
4770 crtc
->mode
.clock
= pipe_config
->adjusted_mode
.clock
;
4771 crtc
->mode
.flags
|= pipe_config
->adjusted_mode
.flags
;
4774 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
4776 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4777 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4782 if (intel_crtc
->pipe
== 0 && INTEL_INFO(dev
)->gen
< 4) {
4783 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4786 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4789 if (intel_crtc
->config
.requested_mode
.clock
>
4790 dev_priv
->display
.get_display_clock_speed(dev
) * 9 / 10)
4791 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
4794 /* only g4x and later have fancy bpc/dither controls */
4795 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
4796 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4797 if (intel_crtc
->config
.dither
&& intel_crtc
->config
.pipe_bpp
!= 30)
4798 pipeconf
|= PIPECONF_DITHER_EN
|
4799 PIPECONF_DITHER_TYPE_SP
;
4801 switch (intel_crtc
->config
.pipe_bpp
) {
4803 pipeconf
|= PIPECONF_6BPC
;
4806 pipeconf
|= PIPECONF_8BPC
;
4809 pipeconf
|= PIPECONF_10BPC
;
4812 /* Case prevented by intel_choose_pipe_bpp_dither. */
4817 if (HAS_PIPE_CXSR(dev
)) {
4818 if (intel_crtc
->lowfreq_avail
) {
4819 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4820 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
4822 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4826 if (!IS_GEN2(dev
) &&
4827 intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
4828 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
4830 pipeconf
|= PIPECONF_PROGRESSIVE
;
4832 if (IS_VALLEYVIEW(dev
) && intel_crtc
->config
.limited_color_range
)
4833 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
4835 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
4836 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
4839 static int i9xx_crtc_mode_set(struct drm_crtc
*crtc
,
4841 struct drm_framebuffer
*fb
)
4843 struct drm_device
*dev
= crtc
->dev
;
4844 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4845 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4846 struct drm_display_mode
*mode
= &intel_crtc
->config
.requested_mode
;
4847 int pipe
= intel_crtc
->pipe
;
4848 int plane
= intel_crtc
->plane
;
4849 int refclk
, num_connectors
= 0;
4850 intel_clock_t clock
, reduced_clock
;
4852 bool ok
, has_reduced_clock
= false;
4853 bool is_lvds
= false;
4854 struct intel_encoder
*encoder
;
4855 const intel_limit_t
*limit
;
4858 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4859 switch (encoder
->type
) {
4860 case INTEL_OUTPUT_LVDS
:
4868 refclk
= i9xx_get_refclk(crtc
, num_connectors
);
4871 * Returns a set of divisors for the desired target clock with the given
4872 * refclk, or FALSE. The returned values represent the clock equation:
4873 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4875 limit
= intel_limit(crtc
, refclk
);
4876 ok
= dev_priv
->display
.find_dpll(limit
, crtc
,
4877 intel_crtc
->config
.port_clock
,
4878 refclk
, NULL
, &clock
);
4879 if (!ok
&& !intel_crtc
->config
.clock_set
) {
4880 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4884 /* Ensure that the cursor is valid for the new mode before changing... */
4885 intel_crtc_update_cursor(crtc
, true);
4887 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
4889 * Ensure we match the reduced clock's P to the target clock.
4890 * If the clocks don't match, we can't switch the display clock
4891 * by using the FP0/FP1. In such case we will disable the LVDS
4892 * downclock feature.
4895 dev_priv
->display
.find_dpll(limit
, crtc
,
4896 dev_priv
->lvds_downclock
,
4900 /* Compat-code for transition, will disappear. */
4901 if (!intel_crtc
->config
.clock_set
) {
4902 intel_crtc
->config
.dpll
.n
= clock
.n
;
4903 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
4904 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
4905 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
4906 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
4910 i8xx_update_pll(intel_crtc
,
4911 has_reduced_clock
? &reduced_clock
: NULL
,
4913 else if (IS_VALLEYVIEW(dev
))
4914 vlv_update_pll(intel_crtc
);
4916 i9xx_update_pll(intel_crtc
,
4917 has_reduced_clock
? &reduced_clock
: NULL
,
4920 /* Set up the display plane register */
4921 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
4923 if (!IS_VALLEYVIEW(dev
)) {
4925 dspcntr
&= ~DISPPLANE_SEL_PIPE_MASK
;
4927 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
4930 intel_set_pipe_timings(intel_crtc
);
4932 /* pipesrc and dspsize control the size that is scaled from,
4933 * which should always be the user's requested size.
4935 I915_WRITE(DSPSIZE(plane
),
4936 ((mode
->vdisplay
- 1) << 16) |
4937 (mode
->hdisplay
- 1));
4938 I915_WRITE(DSPPOS(plane
), 0);
4940 i9xx_set_pipeconf(intel_crtc
);
4942 I915_WRITE(DSPCNTR(plane
), dspcntr
);
4943 POSTING_READ(DSPCNTR(plane
));
4945 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
4947 intel_update_watermarks(dev
);
4952 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
4953 struct intel_crtc_config
*pipe_config
)
4955 struct drm_device
*dev
= crtc
->base
.dev
;
4956 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4959 tmp
= I915_READ(PFIT_CONTROL
);
4961 if (INTEL_INFO(dev
)->gen
< 4) {
4962 if (crtc
->pipe
!= PIPE_B
)
4965 /* gen2/3 store dither state in pfit control, needs to match */
4966 pipe_config
->gmch_pfit
.control
= tmp
& PANEL_8TO6_DITHER_ENABLE
;
4968 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
4972 if (!(tmp
& PFIT_ENABLE
))
4975 pipe_config
->gmch_pfit
.control
= I915_READ(PFIT_CONTROL
);
4976 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
4977 if (INTEL_INFO(dev
)->gen
< 5)
4978 pipe_config
->gmch_pfit
.lvds_border_bits
=
4979 I915_READ(LVDS
) & LVDS_BORDER_ENABLE
;
4982 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
4983 struct intel_crtc_config
*pipe_config
)
4985 struct drm_device
*dev
= crtc
->base
.dev
;
4986 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4989 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
4990 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
4992 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
4993 if (!(tmp
& PIPECONF_ENABLE
))
4996 intel_get_pipe_timings(crtc
, pipe_config
);
4998 i9xx_get_pfit_config(crtc
, pipe_config
);
5000 if (INTEL_INFO(dev
)->gen
>= 4) {
5001 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
5002 pipe_config
->pixel_multiplier
=
5003 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
5004 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
5005 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
5006 } else if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
5007 tmp
= I915_READ(DPLL(crtc
->pipe
));
5008 pipe_config
->pixel_multiplier
=
5009 ((tmp
& SDVO_MULTIPLIER_MASK
)
5010 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
5012 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5013 * port and will be fixed up in the encoder->get_config
5015 pipe_config
->pixel_multiplier
= 1;
5017 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
5018 if (!IS_VALLEYVIEW(dev
)) {
5019 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
5020 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
5022 /* Mask out read-only status bits. */
5023 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
5024 DPLL_PORTC_READY_MASK
|
5025 DPLL_PORTB_READY_MASK
);
5031 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
5033 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5034 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
5035 struct intel_encoder
*encoder
;
5037 bool has_lvds
= false;
5038 bool has_cpu_edp
= false;
5039 bool has_panel
= false;
5040 bool has_ck505
= false;
5041 bool can_ssc
= false;
5043 /* We need to take the global config into account */
5044 list_for_each_entry(encoder
, &mode_config
->encoder_list
,
5046 switch (encoder
->type
) {
5047 case INTEL_OUTPUT_LVDS
:
5051 case INTEL_OUTPUT_EDP
:
5053 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
5059 if (HAS_PCH_IBX(dev
)) {
5060 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
5061 can_ssc
= has_ck505
;
5067 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5068 has_panel
, has_lvds
, has_ck505
);
5070 /* Ironlake: try to setup display ref clock before DPLL
5071 * enabling. This is only under driver's control after
5072 * PCH B stepping, previous chipset stepping should be
5073 * ignoring this setting.
5075 val
= I915_READ(PCH_DREF_CONTROL
);
5077 /* As we must carefully and slowly disable/enable each source in turn,
5078 * compute the final state we want first and check if we need to
5079 * make any changes at all.
5082 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
5084 final
|= DREF_NONSPREAD_CK505_ENABLE
;
5086 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
5088 final
&= ~DREF_SSC_SOURCE_MASK
;
5089 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
5090 final
&= ~DREF_SSC1_ENABLE
;
5093 final
|= DREF_SSC_SOURCE_ENABLE
;
5095 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
5096 final
|= DREF_SSC1_ENABLE
;
5099 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
5100 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
5102 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
5104 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5106 final
|= DREF_SSC_SOURCE_DISABLE
;
5107 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5113 /* Always enable nonspread source */
5114 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
5117 val
|= DREF_NONSPREAD_CK505_ENABLE
;
5119 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
5122 val
&= ~DREF_SSC_SOURCE_MASK
;
5123 val
|= DREF_SSC_SOURCE_ENABLE
;
5125 /* SSC must be turned on before enabling the CPU output */
5126 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
5127 DRM_DEBUG_KMS("Using SSC on panel\n");
5128 val
|= DREF_SSC1_ENABLE
;
5130 val
&= ~DREF_SSC1_ENABLE
;
5132 /* Get SSC going before enabling the outputs */
5133 I915_WRITE(PCH_DREF_CONTROL
, val
);
5134 POSTING_READ(PCH_DREF_CONTROL
);
5137 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
5139 /* Enable CPU source on CPU attached eDP */
5141 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
5142 DRM_DEBUG_KMS("Using SSC on eDP\n");
5143 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
5146 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
5148 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5150 I915_WRITE(PCH_DREF_CONTROL
, val
);
5151 POSTING_READ(PCH_DREF_CONTROL
);
5154 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5156 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
5158 /* Turn off CPU output */
5159 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5161 I915_WRITE(PCH_DREF_CONTROL
, val
);
5162 POSTING_READ(PCH_DREF_CONTROL
);
5165 /* Turn off the SSC source */
5166 val
&= ~DREF_SSC_SOURCE_MASK
;
5167 val
|= DREF_SSC_SOURCE_DISABLE
;
5170 val
&= ~DREF_SSC1_ENABLE
;
5172 I915_WRITE(PCH_DREF_CONTROL
, val
);
5173 POSTING_READ(PCH_DREF_CONTROL
);
5177 BUG_ON(val
!= final
);
5180 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5181 static void lpt_init_pch_refclk(struct drm_device
*dev
)
5183 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5184 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
5185 struct intel_encoder
*encoder
;
5186 bool has_vga
= false;
5187 bool is_sdv
= false;
5190 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
) {
5191 switch (encoder
->type
) {
5192 case INTEL_OUTPUT_ANALOG
:
5201 mutex_lock(&dev_priv
->dpio_lock
);
5203 /* XXX: Rip out SDV support once Haswell ships for real. */
5204 if (IS_HASWELL(dev
) && (dev
->pci_device
& 0xFF00) == 0x0C00)
5207 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
5208 tmp
&= ~SBI_SSCCTL_DISABLE
;
5209 tmp
|= SBI_SSCCTL_PATHALT
;
5210 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5214 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
5215 tmp
&= ~SBI_SSCCTL_PATHALT
;
5216 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5219 tmp
= I915_READ(SOUTH_CHICKEN2
);
5220 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
5221 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
5223 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
5224 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
5225 DRM_ERROR("FDI mPHY reset assert timeout\n");
5227 tmp
= I915_READ(SOUTH_CHICKEN2
);
5228 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
5229 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
5231 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
5232 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0,
5234 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5237 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
5238 tmp
&= ~(0xFF << 24);
5239 tmp
|= (0x12 << 24);
5240 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
5243 tmp
= intel_sbi_read(dev_priv
, 0x800C, SBI_MPHY
);
5245 intel_sbi_write(dev_priv
, 0x800C, tmp
, SBI_MPHY
);
5248 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
5250 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
5252 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
5254 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
5257 tmp
= intel_sbi_read(dev_priv
, 0x2038, SBI_MPHY
);
5258 tmp
|= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5259 intel_sbi_write(dev_priv
, 0x2038, tmp
, SBI_MPHY
);
5261 tmp
= intel_sbi_read(dev_priv
, 0x2138, SBI_MPHY
);
5262 tmp
|= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5263 intel_sbi_write(dev_priv
, 0x2138, tmp
, SBI_MPHY
);
5265 tmp
= intel_sbi_read(dev_priv
, 0x203C, SBI_MPHY
);
5267 intel_sbi_write(dev_priv
, 0x203C, tmp
, SBI_MPHY
);
5269 tmp
= intel_sbi_read(dev_priv
, 0x213C, SBI_MPHY
);
5271 intel_sbi_write(dev_priv
, 0x213C, tmp
, SBI_MPHY
);
5274 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
5275 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
5276 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
5278 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
5279 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
5280 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
5283 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
5286 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
5288 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
5291 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
5294 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
5297 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
5299 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
5302 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
5304 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
5305 tmp
&= ~(0xFF << 16);
5306 tmp
|= (0x1C << 16);
5307 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
5309 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
5310 tmp
&= ~(0xFF << 16);
5311 tmp
|= (0x1C << 16);
5312 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
5315 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
5317 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
5319 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
5321 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
5323 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
5324 tmp
&= ~(0xF << 28);
5326 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
5328 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
5329 tmp
&= ~(0xF << 28);
5331 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
5334 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5335 tmp
= intel_sbi_read(dev_priv
, SBI_DBUFF0
, SBI_ICLK
);
5336 tmp
|= SBI_DBUFF0_ENABLE
;
5337 intel_sbi_write(dev_priv
, SBI_DBUFF0
, tmp
, SBI_ICLK
);
5339 mutex_unlock(&dev_priv
->dpio_lock
);
5343 * Initialize reference clocks when the driver loads
5345 void intel_init_pch_refclk(struct drm_device
*dev
)
5347 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
5348 ironlake_init_pch_refclk(dev
);
5349 else if (HAS_PCH_LPT(dev
))
5350 lpt_init_pch_refclk(dev
);
5353 static int ironlake_get_refclk(struct drm_crtc
*crtc
)
5355 struct drm_device
*dev
= crtc
->dev
;
5356 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5357 struct intel_encoder
*encoder
;
5358 int num_connectors
= 0;
5359 bool is_lvds
= false;
5361 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5362 switch (encoder
->type
) {
5363 case INTEL_OUTPUT_LVDS
:
5370 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
5371 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5372 dev_priv
->vbt
.lvds_ssc_freq
);
5373 return dev_priv
->vbt
.lvds_ssc_freq
* 1000;
5379 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
5381 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
5382 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5383 int pipe
= intel_crtc
->pipe
;
5388 switch (intel_crtc
->config
.pipe_bpp
) {
5390 val
|= PIPECONF_6BPC
;
5393 val
|= PIPECONF_8BPC
;
5396 val
|= PIPECONF_10BPC
;
5399 val
|= PIPECONF_12BPC
;
5402 /* Case prevented by intel_choose_pipe_bpp_dither. */
5406 if (intel_crtc
->config
.dither
)
5407 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
5409 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
5410 val
|= PIPECONF_INTERLACED_ILK
;
5412 val
|= PIPECONF_PROGRESSIVE
;
5414 if (intel_crtc
->config
.limited_color_range
)
5415 val
|= PIPECONF_COLOR_RANGE_SELECT
;
5417 I915_WRITE(PIPECONF(pipe
), val
);
5418 POSTING_READ(PIPECONF(pipe
));
5422 * Set up the pipe CSC unit.
5424 * Currently only full range RGB to limited range RGB conversion
5425 * is supported, but eventually this should handle various
5426 * RGB<->YCbCr scenarios as well.
5428 static void intel_set_pipe_csc(struct drm_crtc
*crtc
)
5430 struct drm_device
*dev
= crtc
->dev
;
5431 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5432 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5433 int pipe
= intel_crtc
->pipe
;
5434 uint16_t coeff
= 0x7800; /* 1.0 */
5437 * TODO: Check what kind of values actually come out of the pipe
5438 * with these coeff/postoff values and adjust to get the best
5439 * accuracy. Perhaps we even need to take the bpc value into
5443 if (intel_crtc
->config
.limited_color_range
)
5444 coeff
= ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5447 * GY/GU and RY/RU should be the other way around according
5448 * to BSpec, but reality doesn't agree. Just set them up in
5449 * a way that results in the correct picture.
5451 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeff
<< 16);
5452 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), 0);
5454 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeff
);
5455 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), 0);
5457 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), 0);
5458 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeff
<< 16);
5460 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
5461 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
5462 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
5464 if (INTEL_INFO(dev
)->gen
> 6) {
5465 uint16_t postoff
= 0;
5467 if (intel_crtc
->config
.limited_color_range
)
5468 postoff
= (16 * (1 << 13) / 255) & 0x1fff;
5470 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
5471 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
5472 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
5474 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
5476 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
5478 if (intel_crtc
->config
.limited_color_range
)
5479 mode
|= CSC_BLACK_SCREEN_OFFSET
;
5481 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
5485 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
5487 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
5488 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5489 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
5494 if (intel_crtc
->config
.dither
)
5495 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
5497 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
5498 val
|= PIPECONF_INTERLACED_ILK
;
5500 val
|= PIPECONF_PROGRESSIVE
;
5502 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
5503 POSTING_READ(PIPECONF(cpu_transcoder
));
5505 I915_WRITE(GAMMA_MODE(intel_crtc
->pipe
), GAMMA_MODE_MODE_8BIT
);
5506 POSTING_READ(GAMMA_MODE(intel_crtc
->pipe
));
5509 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
5510 intel_clock_t
*clock
,
5511 bool *has_reduced_clock
,
5512 intel_clock_t
*reduced_clock
)
5514 struct drm_device
*dev
= crtc
->dev
;
5515 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5516 struct intel_encoder
*intel_encoder
;
5518 const intel_limit_t
*limit
;
5519 bool ret
, is_lvds
= false;
5521 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5522 switch (intel_encoder
->type
) {
5523 case INTEL_OUTPUT_LVDS
:
5529 refclk
= ironlake_get_refclk(crtc
);
5532 * Returns a set of divisors for the desired target clock with the given
5533 * refclk, or FALSE. The returned values represent the clock equation:
5534 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5536 limit
= intel_limit(crtc
, refclk
);
5537 ret
= dev_priv
->display
.find_dpll(limit
, crtc
,
5538 to_intel_crtc(crtc
)->config
.port_clock
,
5539 refclk
, NULL
, clock
);
5543 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
5545 * Ensure we match the reduced clock's P to the target clock.
5546 * If the clocks don't match, we can't switch the display clock
5547 * by using the FP0/FP1. In such case we will disable the LVDS
5548 * downclock feature.
5550 *has_reduced_clock
=
5551 dev_priv
->display
.find_dpll(limit
, crtc
,
5552 dev_priv
->lvds_downclock
,
5560 static void cpt_enable_fdi_bc_bifurcation(struct drm_device
*dev
)
5562 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5565 temp
= I915_READ(SOUTH_CHICKEN1
);
5566 if (temp
& FDI_BC_BIFURCATION_SELECT
)
5569 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
5570 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
5572 temp
|= FDI_BC_BIFURCATION_SELECT
;
5573 DRM_DEBUG_KMS("enabling fdi C rx\n");
5574 I915_WRITE(SOUTH_CHICKEN1
, temp
);
5575 POSTING_READ(SOUTH_CHICKEN1
);
5578 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
5580 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5581 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5583 switch (intel_crtc
->pipe
) {
5587 if (intel_crtc
->config
.fdi_lanes
> 2)
5588 WARN_ON(I915_READ(SOUTH_CHICKEN1
) & FDI_BC_BIFURCATION_SELECT
);
5590 cpt_enable_fdi_bc_bifurcation(dev
);
5594 cpt_enable_fdi_bc_bifurcation(dev
);
5602 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
5605 * Account for spread spectrum to avoid
5606 * oversubscribing the link. Max center spread
5607 * is 2.5%; use 5% for safety's sake.
5609 u32 bps
= target_clock
* bpp
* 21 / 20;
5610 return bps
/ (link_bw
* 8) + 1;
5613 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
5615 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
5618 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
5620 intel_clock_t
*reduced_clock
, u32
*fp2
)
5622 struct drm_crtc
*crtc
= &intel_crtc
->base
;
5623 struct drm_device
*dev
= crtc
->dev
;
5624 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5625 struct intel_encoder
*intel_encoder
;
5627 int factor
, num_connectors
= 0;
5628 bool is_lvds
= false, is_sdvo
= false;
5630 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5631 switch (intel_encoder
->type
) {
5632 case INTEL_OUTPUT_LVDS
:
5635 case INTEL_OUTPUT_SDVO
:
5636 case INTEL_OUTPUT_HDMI
:
5644 /* Enable autotuning of the PLL clock (if permissible) */
5647 if ((intel_panel_use_ssc(dev_priv
) &&
5648 dev_priv
->vbt
.lvds_ssc_freq
== 100) ||
5649 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
5651 } else if (intel_crtc
->config
.sdvo_tv_clock
)
5654 if (ironlake_needs_fb_cb_tune(&intel_crtc
->config
.dpll
, factor
))
5657 if (fp2
&& (reduced_clock
->m
< factor
* reduced_clock
->n
))
5663 dpll
|= DPLLB_MODE_LVDS
;
5665 dpll
|= DPLLB_MODE_DAC_SERIAL
;
5667 dpll
|= (intel_crtc
->config
.pixel_multiplier
- 1)
5668 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
5671 dpll
|= DPLL_SDVO_HIGH_SPEED
;
5672 if (intel_crtc
->config
.has_dp_encoder
)
5673 dpll
|= DPLL_SDVO_HIGH_SPEED
;
5675 /* compute bitmask from p1 value */
5676 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5678 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
5680 switch (intel_crtc
->config
.dpll
.p2
) {
5682 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
5685 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
5688 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
5691 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
5695 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
5696 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
5698 dpll
|= PLL_REF_INPUT_DREFCLK
;
5700 return dpll
| DPLL_VCO_ENABLE
;
5703 static int ironlake_crtc_mode_set(struct drm_crtc
*crtc
,
5705 struct drm_framebuffer
*fb
)
5707 struct drm_device
*dev
= crtc
->dev
;
5708 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5709 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5710 int pipe
= intel_crtc
->pipe
;
5711 int plane
= intel_crtc
->plane
;
5712 int num_connectors
= 0;
5713 intel_clock_t clock
, reduced_clock
;
5714 u32 dpll
= 0, fp
= 0, fp2
= 0;
5715 bool ok
, has_reduced_clock
= false;
5716 bool is_lvds
= false;
5717 struct intel_encoder
*encoder
;
5718 struct intel_shared_dpll
*pll
;
5721 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5722 switch (encoder
->type
) {
5723 case INTEL_OUTPUT_LVDS
:
5731 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
5732 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
5734 ok
= ironlake_compute_clocks(crtc
, &clock
,
5735 &has_reduced_clock
, &reduced_clock
);
5736 if (!ok
&& !intel_crtc
->config
.clock_set
) {
5737 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5740 /* Compat-code for transition, will disappear. */
5741 if (!intel_crtc
->config
.clock_set
) {
5742 intel_crtc
->config
.dpll
.n
= clock
.n
;
5743 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
5744 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
5745 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
5746 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
5749 /* Ensure that the cursor is valid for the new mode before changing... */
5750 intel_crtc_update_cursor(crtc
, true);
5752 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5753 if (intel_crtc
->config
.has_pch_encoder
) {
5754 fp
= i9xx_dpll_compute_fp(&intel_crtc
->config
.dpll
);
5755 if (has_reduced_clock
)
5756 fp2
= i9xx_dpll_compute_fp(&reduced_clock
);
5758 dpll
= ironlake_compute_dpll(intel_crtc
,
5759 &fp
, &reduced_clock
,
5760 has_reduced_clock
? &fp2
: NULL
);
5762 intel_crtc
->config
.dpll_hw_state
.dpll
= dpll
;
5763 intel_crtc
->config
.dpll_hw_state
.fp0
= fp
;
5764 if (has_reduced_clock
)
5765 intel_crtc
->config
.dpll_hw_state
.fp1
= fp2
;
5767 intel_crtc
->config
.dpll_hw_state
.fp1
= fp
;
5769 pll
= intel_get_shared_dpll(intel_crtc
);
5771 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5776 intel_put_shared_dpll(intel_crtc
);
5778 if (intel_crtc
->config
.has_dp_encoder
)
5779 intel_dp_set_m_n(intel_crtc
);
5781 if (is_lvds
&& has_reduced_clock
&& i915_powersave
)
5782 intel_crtc
->lowfreq_avail
= true;
5784 intel_crtc
->lowfreq_avail
= false;
5786 if (intel_crtc
->config
.has_pch_encoder
) {
5787 pll
= intel_crtc_to_shared_dpll(intel_crtc
);
5791 intel_set_pipe_timings(intel_crtc
);
5793 if (intel_crtc
->config
.has_pch_encoder
) {
5794 intel_cpu_transcoder_set_m_n(intel_crtc
,
5795 &intel_crtc
->config
.fdi_m_n
);
5798 if (IS_IVYBRIDGE(dev
))
5799 ivybridge_update_fdi_bc_bifurcation(intel_crtc
);
5801 ironlake_set_pipeconf(crtc
);
5803 /* Set up the display plane register */
5804 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
);
5805 POSTING_READ(DSPCNTR(plane
));
5807 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
5809 intel_update_watermarks(dev
);
5814 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
5815 struct intel_crtc_config
*pipe_config
)
5817 struct drm_device
*dev
= crtc
->base
.dev
;
5818 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5819 enum transcoder transcoder
= pipe_config
->cpu_transcoder
;
5821 pipe_config
->fdi_m_n
.link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
5822 pipe_config
->fdi_m_n
.link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
5823 pipe_config
->fdi_m_n
.gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
5825 pipe_config
->fdi_m_n
.gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
5826 pipe_config
->fdi_m_n
.tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
5827 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
5830 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
5831 struct intel_crtc_config
*pipe_config
)
5833 struct drm_device
*dev
= crtc
->base
.dev
;
5834 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5837 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
5839 if (tmp
& PF_ENABLE
) {
5840 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
5841 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
5843 /* We currently do not free assignements of panel fitters on
5844 * ivb/hsw (since we don't use the higher upscaling modes which
5845 * differentiates them) so just WARN about this case for now. */
5847 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
5848 PF_PIPE_SEL_IVB(crtc
->pipe
));
5853 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
5854 struct intel_crtc_config
*pipe_config
)
5856 struct drm_device
*dev
= crtc
->base
.dev
;
5857 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5860 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
5861 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
5863 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
5864 if (!(tmp
& PIPECONF_ENABLE
))
5867 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
5868 struct intel_shared_dpll
*pll
;
5870 pipe_config
->has_pch_encoder
= true;
5872 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
5873 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
5874 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
5876 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
5878 if (HAS_PCH_IBX(dev_priv
->dev
)) {
5879 pipe_config
->shared_dpll
=
5880 (enum intel_dpll_id
) crtc
->pipe
;
5882 tmp
= I915_READ(PCH_DPLL_SEL
);
5883 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
5884 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_B
;
5886 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_A
;
5889 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
5891 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
5892 &pipe_config
->dpll_hw_state
));
5894 tmp
= pipe_config
->dpll_hw_state
.dpll
;
5895 pipe_config
->pixel_multiplier
=
5896 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
5897 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
5899 pipe_config
->pixel_multiplier
= 1;
5902 intel_get_pipe_timings(crtc
, pipe_config
);
5904 ironlake_get_pfit_config(crtc
, pipe_config
);
5909 static void haswell_modeset_global_resources(struct drm_device
*dev
)
5911 bool enable
= false;
5912 struct intel_crtc
*crtc
;
5914 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
5915 if (!crtc
->base
.enabled
)
5918 if (crtc
->pipe
!= PIPE_A
|| crtc
->config
.pch_pfit
.size
||
5919 crtc
->config
.cpu_transcoder
!= TRANSCODER_EDP
)
5923 intel_set_power_well(dev
, enable
);
5926 static int haswell_crtc_mode_set(struct drm_crtc
*crtc
,
5928 struct drm_framebuffer
*fb
)
5930 struct drm_device
*dev
= crtc
->dev
;
5931 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5932 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5933 int plane
= intel_crtc
->plane
;
5936 if (!intel_ddi_pll_mode_set(crtc
))
5939 /* Ensure that the cursor is valid for the new mode before changing... */
5940 intel_crtc_update_cursor(crtc
, true);
5942 if (intel_crtc
->config
.has_dp_encoder
)
5943 intel_dp_set_m_n(intel_crtc
);
5945 intel_crtc
->lowfreq_avail
= false;
5947 intel_set_pipe_timings(intel_crtc
);
5949 if (intel_crtc
->config
.has_pch_encoder
) {
5950 intel_cpu_transcoder_set_m_n(intel_crtc
,
5951 &intel_crtc
->config
.fdi_m_n
);
5954 haswell_set_pipeconf(crtc
);
5956 intel_set_pipe_csc(crtc
);
5958 /* Set up the display plane register */
5959 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
| DISPPLANE_PIPE_CSC_ENABLE
);
5960 POSTING_READ(DSPCNTR(plane
));
5962 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
5964 intel_update_watermarks(dev
);
5969 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
5970 struct intel_crtc_config
*pipe_config
)
5972 struct drm_device
*dev
= crtc
->base
.dev
;
5973 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5974 enum intel_display_power_domain pfit_domain
;
5977 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
5978 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
5980 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
5981 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
5982 enum pipe trans_edp_pipe
;
5983 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
5985 WARN(1, "unknown pipe linked to edp transcoder\n");
5986 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
5987 case TRANS_DDI_EDP_INPUT_A_ON
:
5988 trans_edp_pipe
= PIPE_A
;
5990 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
5991 trans_edp_pipe
= PIPE_B
;
5993 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
5994 trans_edp_pipe
= PIPE_C
;
5998 if (trans_edp_pipe
== crtc
->pipe
)
5999 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
6002 if (!intel_display_power_enabled(dev
,
6003 POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
)))
6006 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
6007 if (!(tmp
& PIPECONF_ENABLE
))
6011 * Haswell has only FDI/PCH transcoder A. It is which is connected to
6012 * DDI E. So just check whether this pipe is wired to DDI E and whether
6013 * the PCH transcoder is on.
6015 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
6016 if ((tmp
& TRANS_DDI_PORT_MASK
) == TRANS_DDI_SELECT_PORT(PORT_E
) &&
6017 I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
6018 pipe_config
->has_pch_encoder
= true;
6020 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
6021 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
6022 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
6024 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
6027 intel_get_pipe_timings(crtc
, pipe_config
);
6029 pfit_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
6030 if (intel_display_power_enabled(dev
, pfit_domain
))
6031 ironlake_get_pfit_config(crtc
, pipe_config
);
6033 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
6034 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
6036 pipe_config
->pixel_multiplier
= 1;
6041 static int intel_crtc_mode_set(struct drm_crtc
*crtc
,
6043 struct drm_framebuffer
*fb
)
6045 struct drm_device
*dev
= crtc
->dev
;
6046 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6047 struct drm_encoder_helper_funcs
*encoder_funcs
;
6048 struct intel_encoder
*encoder
;
6049 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6050 struct drm_display_mode
*adjusted_mode
=
6051 &intel_crtc
->config
.adjusted_mode
;
6052 struct drm_display_mode
*mode
= &intel_crtc
->config
.requested_mode
;
6053 int pipe
= intel_crtc
->pipe
;
6056 drm_vblank_pre_modeset(dev
, pipe
);
6058 ret
= dev_priv
->display
.crtc_mode_set(crtc
, x
, y
, fb
);
6060 drm_vblank_post_modeset(dev
, pipe
);
6065 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
6066 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6067 encoder
->base
.base
.id
,
6068 drm_get_encoder_name(&encoder
->base
),
6069 mode
->base
.id
, mode
->name
);
6070 if (encoder
->mode_set
) {
6071 encoder
->mode_set(encoder
);
6073 encoder_funcs
= encoder
->base
.helper_private
;
6074 encoder_funcs
->mode_set(&encoder
->base
, mode
, adjusted_mode
);
6081 static bool intel_eld_uptodate(struct drm_connector
*connector
,
6082 int reg_eldv
, uint32_t bits_eldv
,
6083 int reg_elda
, uint32_t bits_elda
,
6086 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6087 uint8_t *eld
= connector
->eld
;
6090 i
= I915_READ(reg_eldv
);
6099 i
= I915_READ(reg_elda
);
6101 I915_WRITE(reg_elda
, i
);
6103 for (i
= 0; i
< eld
[2]; i
++)
6104 if (I915_READ(reg_edid
) != *((uint32_t *)eld
+ i
))
6110 static void g4x_write_eld(struct drm_connector
*connector
,
6111 struct drm_crtc
*crtc
)
6113 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6114 uint8_t *eld
= connector
->eld
;
6119 i
= I915_READ(G4X_AUD_VID_DID
);
6121 if (i
== INTEL_AUDIO_DEVBLC
|| i
== INTEL_AUDIO_DEVCL
)
6122 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
6124 eldv
= G4X_ELDV_DEVCTG
;
6126 if (intel_eld_uptodate(connector
,
6127 G4X_AUD_CNTL_ST
, eldv
,
6128 G4X_AUD_CNTL_ST
, G4X_ELD_ADDR
,
6129 G4X_HDMIW_HDMIEDID
))
6132 i
= I915_READ(G4X_AUD_CNTL_ST
);
6133 i
&= ~(eldv
| G4X_ELD_ADDR
);
6134 len
= (i
>> 9) & 0x1f; /* ELD buffer size */
6135 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
6140 len
= min_t(uint8_t, eld
[2], len
);
6141 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6142 for (i
= 0; i
< len
; i
++)
6143 I915_WRITE(G4X_HDMIW_HDMIEDID
, *((uint32_t *)eld
+ i
));
6145 i
= I915_READ(G4X_AUD_CNTL_ST
);
6147 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
6150 static void haswell_write_eld(struct drm_connector
*connector
,
6151 struct drm_crtc
*crtc
)
6153 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6154 uint8_t *eld
= connector
->eld
;
6155 struct drm_device
*dev
= crtc
->dev
;
6156 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6160 int pipe
= to_intel_crtc(crtc
)->pipe
;
6163 int hdmiw_hdmiedid
= HSW_AUD_EDID_DATA(pipe
);
6164 int aud_cntl_st
= HSW_AUD_DIP_ELD_CTRL(pipe
);
6165 int aud_config
= HSW_AUD_CFG(pipe
);
6166 int aud_cntrl_st2
= HSW_AUD_PIN_ELD_CP_VLD
;
6169 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6171 /* Audio output enable */
6172 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6173 tmp
= I915_READ(aud_cntrl_st2
);
6174 tmp
|= (AUDIO_OUTPUT_ENABLE_A
<< (pipe
* 4));
6175 I915_WRITE(aud_cntrl_st2
, tmp
);
6177 /* Wait for 1 vertical blank */
6178 intel_wait_for_vblank(dev
, pipe
);
6180 /* Set ELD valid state */
6181 tmp
= I915_READ(aud_cntrl_st2
);
6182 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp
);
6183 tmp
|= (AUDIO_ELD_VALID_A
<< (pipe
* 4));
6184 I915_WRITE(aud_cntrl_st2
, tmp
);
6185 tmp
= I915_READ(aud_cntrl_st2
);
6186 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp
);
6188 /* Enable HDMI mode */
6189 tmp
= I915_READ(aud_config
);
6190 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp
);
6191 /* clear N_programing_enable and N_value_index */
6192 tmp
&= ~(AUD_CONFIG_N_VALUE_INDEX
| AUD_CONFIG_N_PROG_ENABLE
);
6193 I915_WRITE(aud_config
, tmp
);
6195 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
6197 eldv
= AUDIO_ELD_VALID_A
<< (pipe
* 4);
6198 intel_crtc
->eld_vld
= true;
6200 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
6201 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6202 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6203 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
6205 I915_WRITE(aud_config
, 0);
6207 if (intel_eld_uptodate(connector
,
6208 aud_cntrl_st2
, eldv
,
6209 aud_cntl_st
, IBX_ELD_ADDRESS
,
6213 i
= I915_READ(aud_cntrl_st2
);
6215 I915_WRITE(aud_cntrl_st2
, i
);
6220 i
= I915_READ(aud_cntl_st
);
6221 i
&= ~IBX_ELD_ADDRESS
;
6222 I915_WRITE(aud_cntl_st
, i
);
6223 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
6224 DRM_DEBUG_DRIVER("port num:%d\n", i
);
6226 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
6227 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6228 for (i
= 0; i
< len
; i
++)
6229 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
6231 i
= I915_READ(aud_cntrl_st2
);
6233 I915_WRITE(aud_cntrl_st2
, i
);
6237 static void ironlake_write_eld(struct drm_connector
*connector
,
6238 struct drm_crtc
*crtc
)
6240 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6241 uint8_t *eld
= connector
->eld
;
6249 int pipe
= to_intel_crtc(crtc
)->pipe
;
6251 if (HAS_PCH_IBX(connector
->dev
)) {
6252 hdmiw_hdmiedid
= IBX_HDMIW_HDMIEDID(pipe
);
6253 aud_config
= IBX_AUD_CFG(pipe
);
6254 aud_cntl_st
= IBX_AUD_CNTL_ST(pipe
);
6255 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
6257 hdmiw_hdmiedid
= CPT_HDMIW_HDMIEDID(pipe
);
6258 aud_config
= CPT_AUD_CFG(pipe
);
6259 aud_cntl_st
= CPT_AUD_CNTL_ST(pipe
);
6260 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
6263 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
6265 i
= I915_READ(aud_cntl_st
);
6266 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
6268 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6269 /* operate blindly on all ports */
6270 eldv
= IBX_ELD_VALIDB
;
6271 eldv
|= IBX_ELD_VALIDB
<< 4;
6272 eldv
|= IBX_ELD_VALIDB
<< 8;
6274 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i
));
6275 eldv
= IBX_ELD_VALIDB
<< ((i
- 1) * 4);
6278 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
6279 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6280 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6281 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
6283 I915_WRITE(aud_config
, 0);
6285 if (intel_eld_uptodate(connector
,
6286 aud_cntrl_st2
, eldv
,
6287 aud_cntl_st
, IBX_ELD_ADDRESS
,
6291 i
= I915_READ(aud_cntrl_st2
);
6293 I915_WRITE(aud_cntrl_st2
, i
);
6298 i
= I915_READ(aud_cntl_st
);
6299 i
&= ~IBX_ELD_ADDRESS
;
6300 I915_WRITE(aud_cntl_st
, i
);
6302 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
6303 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6304 for (i
= 0; i
< len
; i
++)
6305 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
6307 i
= I915_READ(aud_cntrl_st2
);
6309 I915_WRITE(aud_cntrl_st2
, i
);
6312 void intel_write_eld(struct drm_encoder
*encoder
,
6313 struct drm_display_mode
*mode
)
6315 struct drm_crtc
*crtc
= encoder
->crtc
;
6316 struct drm_connector
*connector
;
6317 struct drm_device
*dev
= encoder
->dev
;
6318 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6320 connector
= drm_select_eld(encoder
, mode
);
6324 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6326 drm_get_connector_name(connector
),
6327 connector
->encoder
->base
.id
,
6328 drm_get_encoder_name(connector
->encoder
));
6330 connector
->eld
[6] = drm_av_sync_delay(connector
, mode
) / 2;
6332 if (dev_priv
->display
.write_eld
)
6333 dev_priv
->display
.write_eld(connector
, crtc
);
6336 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6337 void intel_crtc_load_lut(struct drm_crtc
*crtc
)
6339 struct drm_device
*dev
= crtc
->dev
;
6340 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6341 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6342 enum pipe pipe
= intel_crtc
->pipe
;
6343 int palreg
= PALETTE(pipe
);
6345 bool reenable_ips
= false;
6347 /* The clocks have to be on to load the palette. */
6348 if (!crtc
->enabled
|| !intel_crtc
->active
)
6351 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
6352 assert_pll_enabled(dev_priv
, pipe
);
6354 /* use legacy palette for Ironlake */
6355 if (HAS_PCH_SPLIT(dev
))
6356 palreg
= LGC_PALETTE(pipe
);
6358 /* Workaround : Do not read or write the pipe palette/gamma data while
6359 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6361 if (intel_crtc
->config
.ips_enabled
&&
6362 ((I915_READ(GAMMA_MODE(pipe
)) & GAMMA_MODE_MODE_MASK
) ==
6363 GAMMA_MODE_MODE_SPLIT
)) {
6364 hsw_disable_ips(intel_crtc
);
6365 reenable_ips
= true;
6368 for (i
= 0; i
< 256; i
++) {
6369 I915_WRITE(palreg
+ 4 * i
,
6370 (intel_crtc
->lut_r
[i
] << 16) |
6371 (intel_crtc
->lut_g
[i
] << 8) |
6372 intel_crtc
->lut_b
[i
]);
6376 hsw_enable_ips(intel_crtc
);
6379 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6381 struct drm_device
*dev
= crtc
->dev
;
6382 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6383 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6384 bool visible
= base
!= 0;
6387 if (intel_crtc
->cursor_visible
== visible
)
6390 cntl
= I915_READ(_CURACNTR
);
6392 /* On these chipsets we can only modify the base whilst
6393 * the cursor is disabled.
6395 I915_WRITE(_CURABASE
, base
);
6397 cntl
&= ~(CURSOR_FORMAT_MASK
);
6398 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6399 cntl
|= CURSOR_ENABLE
|
6400 CURSOR_GAMMA_ENABLE
|
6403 cntl
&= ~(CURSOR_ENABLE
| CURSOR_GAMMA_ENABLE
);
6404 I915_WRITE(_CURACNTR
, cntl
);
6406 intel_crtc
->cursor_visible
= visible
;
6409 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6411 struct drm_device
*dev
= crtc
->dev
;
6412 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6413 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6414 int pipe
= intel_crtc
->pipe
;
6415 bool visible
= base
!= 0;
6417 if (intel_crtc
->cursor_visible
!= visible
) {
6418 uint32_t cntl
= I915_READ(CURCNTR(pipe
));
6420 cntl
&= ~(CURSOR_MODE
| MCURSOR_PIPE_SELECT
);
6421 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
6422 cntl
|= pipe
<< 28; /* Connect to correct pipe */
6424 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
6425 cntl
|= CURSOR_MODE_DISABLE
;
6427 I915_WRITE(CURCNTR(pipe
), cntl
);
6429 intel_crtc
->cursor_visible
= visible
;
6431 /* and commit changes on next vblank */
6432 I915_WRITE(CURBASE(pipe
), base
);
6435 static void ivb_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6437 struct drm_device
*dev
= crtc
->dev
;
6438 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6439 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6440 int pipe
= intel_crtc
->pipe
;
6441 bool visible
= base
!= 0;
6443 if (intel_crtc
->cursor_visible
!= visible
) {
6444 uint32_t cntl
= I915_READ(CURCNTR_IVB(pipe
));
6446 cntl
&= ~CURSOR_MODE
;
6447 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
6449 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
6450 cntl
|= CURSOR_MODE_DISABLE
;
6452 if (IS_HASWELL(dev
))
6453 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
6454 I915_WRITE(CURCNTR_IVB(pipe
), cntl
);
6456 intel_crtc
->cursor_visible
= visible
;
6458 /* and commit changes on next vblank */
6459 I915_WRITE(CURBASE_IVB(pipe
), base
);
6462 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6463 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
6466 struct drm_device
*dev
= crtc
->dev
;
6467 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6468 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6469 int pipe
= intel_crtc
->pipe
;
6470 int x
= intel_crtc
->cursor_x
;
6471 int y
= intel_crtc
->cursor_y
;
6477 if (on
&& crtc
->enabled
&& crtc
->fb
) {
6478 base
= intel_crtc
->cursor_addr
;
6479 if (x
> (int) crtc
->fb
->width
)
6482 if (y
> (int) crtc
->fb
->height
)
6488 if (x
+ intel_crtc
->cursor_width
< 0)
6491 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
6494 pos
|= x
<< CURSOR_X_SHIFT
;
6497 if (y
+ intel_crtc
->cursor_height
< 0)
6500 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
6503 pos
|= y
<< CURSOR_Y_SHIFT
;
6505 visible
= base
!= 0;
6506 if (!visible
&& !intel_crtc
->cursor_visible
)
6509 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
6510 I915_WRITE(CURPOS_IVB(pipe
), pos
);
6511 ivb_update_cursor(crtc
, base
);
6513 I915_WRITE(CURPOS(pipe
), pos
);
6514 if (IS_845G(dev
) || IS_I865G(dev
))
6515 i845_update_cursor(crtc
, base
);
6517 i9xx_update_cursor(crtc
, base
);
6521 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
6522 struct drm_file
*file
,
6524 uint32_t width
, uint32_t height
)
6526 struct drm_device
*dev
= crtc
->dev
;
6527 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6528 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6529 struct drm_i915_gem_object
*obj
;
6533 /* if we want to turn off the cursor ignore width and height */
6535 DRM_DEBUG_KMS("cursor off\n");
6538 mutex_lock(&dev
->struct_mutex
);
6542 /* Currently we only support 64x64 cursors */
6543 if (width
!= 64 || height
!= 64) {
6544 DRM_ERROR("we currently only support 64x64 cursors\n");
6548 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
6549 if (&obj
->base
== NULL
)
6552 if (obj
->base
.size
< width
* height
* 4) {
6553 DRM_ERROR("buffer is to small\n");
6558 /* we only need to pin inside GTT if cursor is non-phy */
6559 mutex_lock(&dev
->struct_mutex
);
6560 if (!dev_priv
->info
->cursor_needs_physical
) {
6563 if (obj
->tiling_mode
) {
6564 DRM_ERROR("cursor cannot be tiled\n");
6569 /* Note that the w/a also requires 2 PTE of padding following
6570 * the bo. We currently fill all unused PTE with the shadow
6571 * page and so we should always have valid PTE following the
6572 * cursor preventing the VT-d warning.
6575 if (need_vtd_wa(dev
))
6576 alignment
= 64*1024;
6578 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, NULL
);
6580 DRM_ERROR("failed to move cursor bo into the GTT\n");
6584 ret
= i915_gem_object_put_fence(obj
);
6586 DRM_ERROR("failed to release fence for cursor");
6590 addr
= i915_gem_obj_ggtt_offset(obj
);
6592 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
6593 ret
= i915_gem_attach_phys_object(dev
, obj
,
6594 (intel_crtc
->pipe
== 0) ? I915_GEM_PHYS_CURSOR_0
: I915_GEM_PHYS_CURSOR_1
,
6597 DRM_ERROR("failed to attach phys object\n");
6600 addr
= obj
->phys_obj
->handle
->busaddr
;
6604 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
6607 if (intel_crtc
->cursor_bo
) {
6608 if (dev_priv
->info
->cursor_needs_physical
) {
6609 if (intel_crtc
->cursor_bo
!= obj
)
6610 i915_gem_detach_phys_object(dev
, intel_crtc
->cursor_bo
);
6612 i915_gem_object_unpin(intel_crtc
->cursor_bo
);
6613 drm_gem_object_unreference(&intel_crtc
->cursor_bo
->base
);
6616 mutex_unlock(&dev
->struct_mutex
);
6618 intel_crtc
->cursor_addr
= addr
;
6619 intel_crtc
->cursor_bo
= obj
;
6620 intel_crtc
->cursor_width
= width
;
6621 intel_crtc
->cursor_height
= height
;
6623 intel_crtc_update_cursor(crtc
, intel_crtc
->cursor_bo
!= NULL
);
6627 i915_gem_object_unpin(obj
);
6629 mutex_unlock(&dev
->struct_mutex
);
6631 drm_gem_object_unreference_unlocked(&obj
->base
);
6635 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
6637 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6639 intel_crtc
->cursor_x
= x
;
6640 intel_crtc
->cursor_y
= y
;
6642 intel_crtc_update_cursor(crtc
, intel_crtc
->cursor_bo
!= NULL
);
6647 /** Sets the color ramps on behalf of RandR */
6648 void intel_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
6649 u16 blue
, int regno
)
6651 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6653 intel_crtc
->lut_r
[regno
] = red
>> 8;
6654 intel_crtc
->lut_g
[regno
] = green
>> 8;
6655 intel_crtc
->lut_b
[regno
] = blue
>> 8;
6658 void intel_crtc_fb_gamma_get(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
6659 u16
*blue
, int regno
)
6661 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6663 *red
= intel_crtc
->lut_r
[regno
] << 8;
6664 *green
= intel_crtc
->lut_g
[regno
] << 8;
6665 *blue
= intel_crtc
->lut_b
[regno
] << 8;
6668 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
6669 u16
*blue
, uint32_t start
, uint32_t size
)
6671 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
6672 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6674 for (i
= start
; i
< end
; i
++) {
6675 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
6676 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
6677 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
6680 intel_crtc_load_lut(crtc
);
6683 /* VESA 640x480x72Hz mode to set on the pipe */
6684 static struct drm_display_mode load_detect_mode
= {
6685 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
6686 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
6689 static struct drm_framebuffer
*
6690 intel_framebuffer_create(struct drm_device
*dev
,
6691 struct drm_mode_fb_cmd2
*mode_cmd
,
6692 struct drm_i915_gem_object
*obj
)
6694 struct intel_framebuffer
*intel_fb
;
6697 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
6699 drm_gem_object_unreference_unlocked(&obj
->base
);
6700 return ERR_PTR(-ENOMEM
);
6703 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
6705 drm_gem_object_unreference_unlocked(&obj
->base
);
6707 return ERR_PTR(ret
);
6710 return &intel_fb
->base
;
6714 intel_framebuffer_pitch_for_width(int width
, int bpp
)
6716 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
6717 return ALIGN(pitch
, 64);
6721 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
6723 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
6724 return ALIGN(pitch
* mode
->vdisplay
, PAGE_SIZE
);
6727 static struct drm_framebuffer
*
6728 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
6729 struct drm_display_mode
*mode
,
6732 struct drm_i915_gem_object
*obj
;
6733 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
6735 obj
= i915_gem_alloc_object(dev
,
6736 intel_framebuffer_size_for_mode(mode
, bpp
));
6738 return ERR_PTR(-ENOMEM
);
6740 mode_cmd
.width
= mode
->hdisplay
;
6741 mode_cmd
.height
= mode
->vdisplay
;
6742 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
6744 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
6746 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
6749 static struct drm_framebuffer
*
6750 mode_fits_in_fbdev(struct drm_device
*dev
,
6751 struct drm_display_mode
*mode
)
6753 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6754 struct drm_i915_gem_object
*obj
;
6755 struct drm_framebuffer
*fb
;
6757 if (dev_priv
->fbdev
== NULL
)
6760 obj
= dev_priv
->fbdev
->ifb
.obj
;
6764 fb
= &dev_priv
->fbdev
->ifb
.base
;
6765 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
6766 fb
->bits_per_pixel
))
6769 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
6775 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
6776 struct drm_display_mode
*mode
,
6777 struct intel_load_detect_pipe
*old
)
6779 struct intel_crtc
*intel_crtc
;
6780 struct intel_encoder
*intel_encoder
=
6781 intel_attached_encoder(connector
);
6782 struct drm_crtc
*possible_crtc
;
6783 struct drm_encoder
*encoder
= &intel_encoder
->base
;
6784 struct drm_crtc
*crtc
= NULL
;
6785 struct drm_device
*dev
= encoder
->dev
;
6786 struct drm_framebuffer
*fb
;
6789 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6790 connector
->base
.id
, drm_get_connector_name(connector
),
6791 encoder
->base
.id
, drm_get_encoder_name(encoder
));
6794 * Algorithm gets a little messy:
6796 * - if the connector already has an assigned crtc, use it (but make
6797 * sure it's on first)
6799 * - try to find the first unused crtc that can drive this connector,
6800 * and use that if we find one
6803 /* See if we already have a CRTC for this connector */
6804 if (encoder
->crtc
) {
6805 crtc
= encoder
->crtc
;
6807 mutex_lock(&crtc
->mutex
);
6809 old
->dpms_mode
= connector
->dpms
;
6810 old
->load_detect_temp
= false;
6812 /* Make sure the crtc and connector are running */
6813 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
6814 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
6819 /* Find an unused one (if possible) */
6820 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
6822 if (!(encoder
->possible_crtcs
& (1 << i
)))
6824 if (!possible_crtc
->enabled
) {
6825 crtc
= possible_crtc
;
6831 * If we didn't find an unused CRTC, don't use any.
6834 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6838 mutex_lock(&crtc
->mutex
);
6839 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
6840 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
6842 intel_crtc
= to_intel_crtc(crtc
);
6843 old
->dpms_mode
= connector
->dpms
;
6844 old
->load_detect_temp
= true;
6845 old
->release_fb
= NULL
;
6848 mode
= &load_detect_mode
;
6850 /* We need a framebuffer large enough to accommodate all accesses
6851 * that the plane may generate whilst we perform load detection.
6852 * We can not rely on the fbcon either being present (we get called
6853 * during its initialisation to detect all boot displays, or it may
6854 * not even exist) or that it is large enough to satisfy the
6857 fb
= mode_fits_in_fbdev(dev
, mode
);
6859 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6860 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
6861 old
->release_fb
= fb
;
6863 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6865 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6866 mutex_unlock(&crtc
->mutex
);
6870 if (intel_set_mode(crtc
, mode
, 0, 0, fb
)) {
6871 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6872 if (old
->release_fb
)
6873 old
->release_fb
->funcs
->destroy(old
->release_fb
);
6874 mutex_unlock(&crtc
->mutex
);
6878 /* let the connector get through one full cycle before testing */
6879 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
6883 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
6884 struct intel_load_detect_pipe
*old
)
6886 struct intel_encoder
*intel_encoder
=
6887 intel_attached_encoder(connector
);
6888 struct drm_encoder
*encoder
= &intel_encoder
->base
;
6889 struct drm_crtc
*crtc
= encoder
->crtc
;
6891 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6892 connector
->base
.id
, drm_get_connector_name(connector
),
6893 encoder
->base
.id
, drm_get_encoder_name(encoder
));
6895 if (old
->load_detect_temp
) {
6896 to_intel_connector(connector
)->new_encoder
= NULL
;
6897 intel_encoder
->new_crtc
= NULL
;
6898 intel_set_mode(crtc
, NULL
, 0, 0, NULL
);
6900 if (old
->release_fb
) {
6901 drm_framebuffer_unregister_private(old
->release_fb
);
6902 drm_framebuffer_unreference(old
->release_fb
);
6905 mutex_unlock(&crtc
->mutex
);
6909 /* Switch crtc and encoder back off if necessary */
6910 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
6911 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
6913 mutex_unlock(&crtc
->mutex
);
6916 /* Returns the clock of the currently programmed mode of the given pipe. */
6917 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
6918 struct intel_crtc_config
*pipe_config
)
6920 struct drm_device
*dev
= crtc
->base
.dev
;
6921 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6922 int pipe
= pipe_config
->cpu_transcoder
;
6923 u32 dpll
= I915_READ(DPLL(pipe
));
6925 intel_clock_t clock
;
6927 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
6928 fp
= I915_READ(FP0(pipe
));
6930 fp
= I915_READ(FP1(pipe
));
6932 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
6933 if (IS_PINEVIEW(dev
)) {
6934 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
6935 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
6937 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
6938 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
6941 if (!IS_GEN2(dev
)) {
6942 if (IS_PINEVIEW(dev
))
6943 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
6944 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
6946 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
6947 DPLL_FPA01_P1_POST_DIV_SHIFT
);
6949 switch (dpll
& DPLL_MODE_MASK
) {
6950 case DPLLB_MODE_DAC_SERIAL
:
6951 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
6954 case DPLLB_MODE_LVDS
:
6955 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
6959 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6960 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
6961 pipe_config
->adjusted_mode
.clock
= 0;
6965 if (IS_PINEVIEW(dev
))
6966 pineview_clock(96000, &clock
);
6968 i9xx_clock(96000, &clock
);
6970 bool is_lvds
= (pipe
== 1) && (I915_READ(LVDS
) & LVDS_PORT_EN
);
6973 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
6974 DPLL_FPA01_P1_POST_DIV_SHIFT
);
6977 if ((dpll
& PLL_REF_INPUT_MASK
) ==
6978 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
6979 /* XXX: might not be 66MHz */
6980 i9xx_clock(66000, &clock
);
6982 i9xx_clock(48000, &clock
);
6984 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
6987 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
6988 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
6990 if (dpll
& PLL_P2_DIVIDE_BY_4
)
6995 i9xx_clock(48000, &clock
);
6999 pipe_config
->adjusted_mode
.clock
= clock
.dot
*
7000 pipe_config
->pixel_multiplier
;
7003 static void ironlake_crtc_clock_get(struct intel_crtc
*crtc
,
7004 struct intel_crtc_config
*pipe_config
)
7006 struct drm_device
*dev
= crtc
->base
.dev
;
7007 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7008 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
7009 int link_freq
, repeat
;
7013 repeat
= pipe_config
->pixel_multiplier
;
7016 * The calculation for the data clock is:
7017 * pixel_clock = ((m/n)*(link_clock * nr_lanes * repeat))/bpp
7018 * But we want to avoid losing precison if possible, so:
7019 * pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp))
7021 * and the link clock is simpler:
7022 * link_clock = (m * link_clock * repeat) / n
7026 * We need to get the FDI or DP link clock here to derive
7029 * For FDI, we read it from the BIOS or use a fixed 2.7GHz.
7030 * For DP, it's either 1.62GHz or 2.7GHz.
7031 * We do our calculations in 10*MHz since we don't need much precison.
7033 if (pipe_config
->has_pch_encoder
)
7034 link_freq
= intel_fdi_link_freq(dev
) * 10000;
7036 link_freq
= pipe_config
->port_clock
;
7038 link_m
= I915_READ(PIPE_LINK_M1(cpu_transcoder
));
7039 link_n
= I915_READ(PIPE_LINK_N1(cpu_transcoder
));
7041 if (!link_m
|| !link_n
)
7044 clock
= ((u64
)link_m
* (u64
)link_freq
* (u64
)repeat
);
7045 do_div(clock
, link_n
);
7047 pipe_config
->adjusted_mode
.clock
= clock
;
7050 /** Returns the currently programmed mode of the given pipe. */
7051 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
7052 struct drm_crtc
*crtc
)
7054 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7055 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7056 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
7057 struct drm_display_mode
*mode
;
7058 struct intel_crtc_config pipe_config
;
7059 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
7060 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
7061 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
7062 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
7064 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
7069 * Construct a pipe_config sufficient for getting the clock info
7070 * back out of crtc_clock_get.
7072 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7073 * to use a real value here instead.
7075 pipe_config
.cpu_transcoder
= (enum transcoder
) intel_crtc
->pipe
;
7076 pipe_config
.pixel_multiplier
= 1;
7077 i9xx_crtc_clock_get(intel_crtc
, &pipe_config
);
7079 mode
->clock
= pipe_config
.adjusted_mode
.clock
;
7080 mode
->hdisplay
= (htot
& 0xffff) + 1;
7081 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
7082 mode
->hsync_start
= (hsync
& 0xffff) + 1;
7083 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
7084 mode
->vdisplay
= (vtot
& 0xffff) + 1;
7085 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
7086 mode
->vsync_start
= (vsync
& 0xffff) + 1;
7087 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
7089 drm_mode_set_name(mode
);
7094 static void intel_increase_pllclock(struct drm_crtc
*crtc
)
7096 struct drm_device
*dev
= crtc
->dev
;
7097 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7098 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7099 int pipe
= intel_crtc
->pipe
;
7100 int dpll_reg
= DPLL(pipe
);
7103 if (HAS_PCH_SPLIT(dev
))
7106 if (!dev_priv
->lvds_downclock_avail
)
7109 dpll
= I915_READ(dpll_reg
);
7110 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
7111 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7113 assert_panel_unlocked(dev_priv
, pipe
);
7115 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
7116 I915_WRITE(dpll_reg
, dpll
);
7117 intel_wait_for_vblank(dev
, pipe
);
7119 dpll
= I915_READ(dpll_reg
);
7120 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
7121 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7125 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
7127 struct drm_device
*dev
= crtc
->dev
;
7128 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7129 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7131 if (HAS_PCH_SPLIT(dev
))
7134 if (!dev_priv
->lvds_downclock_avail
)
7138 * Since this is called by a timer, we should never get here in
7141 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
7142 int pipe
= intel_crtc
->pipe
;
7143 int dpll_reg
= DPLL(pipe
);
7146 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7148 assert_panel_unlocked(dev_priv
, pipe
);
7150 dpll
= I915_READ(dpll_reg
);
7151 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
7152 I915_WRITE(dpll_reg
, dpll
);
7153 intel_wait_for_vblank(dev
, pipe
);
7154 dpll
= I915_READ(dpll_reg
);
7155 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
7156 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7161 void intel_mark_busy(struct drm_device
*dev
)
7163 i915_update_gfx_val(dev
->dev_private
);
7166 void intel_mark_idle(struct drm_device
*dev
)
7168 struct drm_crtc
*crtc
;
7170 if (!i915_powersave
)
7173 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
7177 intel_decrease_pllclock(crtc
);
7181 void intel_mark_fb_busy(struct drm_i915_gem_object
*obj
,
7182 struct intel_ring_buffer
*ring
)
7184 struct drm_device
*dev
= obj
->base
.dev
;
7185 struct drm_crtc
*crtc
;
7187 if (!i915_powersave
)
7190 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
7194 if (to_intel_framebuffer(crtc
->fb
)->obj
!= obj
)
7197 intel_increase_pllclock(crtc
);
7198 if (ring
&& intel_fbc_enabled(dev
))
7199 ring
->fbc_dirty
= true;
7203 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
7205 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7206 struct drm_device
*dev
= crtc
->dev
;
7207 struct intel_unpin_work
*work
;
7208 unsigned long flags
;
7210 spin_lock_irqsave(&dev
->event_lock
, flags
);
7211 work
= intel_crtc
->unpin_work
;
7212 intel_crtc
->unpin_work
= NULL
;
7213 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7216 cancel_work_sync(&work
->work
);
7220 intel_crtc_cursor_set(crtc
, NULL
, 0, 0, 0);
7222 drm_crtc_cleanup(crtc
);
7227 static void intel_unpin_work_fn(struct work_struct
*__work
)
7229 struct intel_unpin_work
*work
=
7230 container_of(__work
, struct intel_unpin_work
, work
);
7231 struct drm_device
*dev
= work
->crtc
->dev
;
7233 mutex_lock(&dev
->struct_mutex
);
7234 intel_unpin_fb_obj(work
->old_fb_obj
);
7235 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
7236 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
7238 intel_update_fbc(dev
);
7239 mutex_unlock(&dev
->struct_mutex
);
7241 BUG_ON(atomic_read(&to_intel_crtc(work
->crtc
)->unpin_work_count
) == 0);
7242 atomic_dec(&to_intel_crtc(work
->crtc
)->unpin_work_count
);
7247 static void do_intel_finish_page_flip(struct drm_device
*dev
,
7248 struct drm_crtc
*crtc
)
7250 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7251 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7252 struct intel_unpin_work
*work
;
7253 unsigned long flags
;
7255 /* Ignore early vblank irqs */
7256 if (intel_crtc
== NULL
)
7259 spin_lock_irqsave(&dev
->event_lock
, flags
);
7260 work
= intel_crtc
->unpin_work
;
7262 /* Ensure we don't miss a work->pending update ... */
7265 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
7266 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7270 /* and that the unpin work is consistent wrt ->pending. */
7273 intel_crtc
->unpin_work
= NULL
;
7276 drm_send_vblank_event(dev
, intel_crtc
->pipe
, work
->event
);
7278 drm_vblank_put(dev
, intel_crtc
->pipe
);
7280 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7282 wake_up_all(&dev_priv
->pending_flip_queue
);
7284 queue_work(dev_priv
->wq
, &work
->work
);
7286 trace_i915_flip_complete(intel_crtc
->plane
, work
->pending_flip_obj
);
7289 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
7291 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7292 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
7294 do_intel_finish_page_flip(dev
, crtc
);
7297 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
7299 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7300 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
7302 do_intel_finish_page_flip(dev
, crtc
);
7305 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
7307 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7308 struct intel_crtc
*intel_crtc
=
7309 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
7310 unsigned long flags
;
7312 /* NB: An MMIO update of the plane base pointer will also
7313 * generate a page-flip completion irq, i.e. every modeset
7314 * is also accompanied by a spurious intel_prepare_page_flip().
7316 spin_lock_irqsave(&dev
->event_lock
, flags
);
7317 if (intel_crtc
->unpin_work
)
7318 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
7319 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7322 inline static void intel_mark_page_flip_active(struct intel_crtc
*intel_crtc
)
7324 /* Ensure that the work item is consistent when activating it ... */
7326 atomic_set(&intel_crtc
->unpin_work
->pending
, INTEL_FLIP_PENDING
);
7327 /* and that it is marked active as soon as the irq could fire. */
7331 static int intel_gen2_queue_flip(struct drm_device
*dev
,
7332 struct drm_crtc
*crtc
,
7333 struct drm_framebuffer
*fb
,
7334 struct drm_i915_gem_object
*obj
)
7336 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7337 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7339 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7342 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7346 ret
= intel_ring_begin(ring
, 6);
7350 /* Can't queue multiple flips, so wait for the previous
7351 * one to finish before executing the next.
7353 if (intel_crtc
->plane
)
7354 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
7356 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
7357 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
7358 intel_ring_emit(ring
, MI_NOOP
);
7359 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7360 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7361 intel_ring_emit(ring
, fb
->pitches
[0]);
7362 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
7363 intel_ring_emit(ring
, 0); /* aux display base address, unused */
7365 intel_mark_page_flip_active(intel_crtc
);
7366 intel_ring_advance(ring
);
7370 intel_unpin_fb_obj(obj
);
7375 static int intel_gen3_queue_flip(struct drm_device
*dev
,
7376 struct drm_crtc
*crtc
,
7377 struct drm_framebuffer
*fb
,
7378 struct drm_i915_gem_object
*obj
)
7380 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7381 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7383 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7386 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7390 ret
= intel_ring_begin(ring
, 6);
7394 if (intel_crtc
->plane
)
7395 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
7397 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
7398 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
7399 intel_ring_emit(ring
, MI_NOOP
);
7400 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
7401 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7402 intel_ring_emit(ring
, fb
->pitches
[0]);
7403 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
7404 intel_ring_emit(ring
, MI_NOOP
);
7406 intel_mark_page_flip_active(intel_crtc
);
7407 intel_ring_advance(ring
);
7411 intel_unpin_fb_obj(obj
);
7416 static int intel_gen4_queue_flip(struct drm_device
*dev
,
7417 struct drm_crtc
*crtc
,
7418 struct drm_framebuffer
*fb
,
7419 struct drm_i915_gem_object
*obj
)
7421 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7422 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7423 uint32_t pf
, pipesrc
;
7424 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7427 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7431 ret
= intel_ring_begin(ring
, 4);
7435 /* i965+ uses the linear or tiled offsets from the
7436 * Display Registers (which do not change across a page-flip)
7437 * so we need only reprogram the base address.
7439 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7440 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7441 intel_ring_emit(ring
, fb
->pitches
[0]);
7442 intel_ring_emit(ring
,
7443 (i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
) |
7446 /* XXX Enabling the panel-fitter across page-flip is so far
7447 * untested on non-native modes, so ignore it for now.
7448 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7451 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
7452 intel_ring_emit(ring
, pf
| pipesrc
);
7454 intel_mark_page_flip_active(intel_crtc
);
7455 intel_ring_advance(ring
);
7459 intel_unpin_fb_obj(obj
);
7464 static int intel_gen6_queue_flip(struct drm_device
*dev
,
7465 struct drm_crtc
*crtc
,
7466 struct drm_framebuffer
*fb
,
7467 struct drm_i915_gem_object
*obj
)
7469 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7470 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7471 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7472 uint32_t pf
, pipesrc
;
7475 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7479 ret
= intel_ring_begin(ring
, 4);
7483 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7484 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7485 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
7486 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
7488 /* Contrary to the suggestions in the documentation,
7489 * "Enable Panel Fitter" does not seem to be required when page
7490 * flipping with a non-native mode, and worse causes a normal
7492 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7495 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
7496 intel_ring_emit(ring
, pf
| pipesrc
);
7498 intel_mark_page_flip_active(intel_crtc
);
7499 intel_ring_advance(ring
);
7503 intel_unpin_fb_obj(obj
);
7509 * On gen7 we currently use the blit ring because (in early silicon at least)
7510 * the render ring doesn't give us interrpts for page flip completion, which
7511 * means clients will hang after the first flip is queued. Fortunately the
7512 * blit ring generates interrupts properly, so use it instead.
7514 static int intel_gen7_queue_flip(struct drm_device
*dev
,
7515 struct drm_crtc
*crtc
,
7516 struct drm_framebuffer
*fb
,
7517 struct drm_i915_gem_object
*obj
)
7519 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7520 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7521 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[BCS
];
7522 uint32_t plane_bit
= 0;
7525 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7529 switch(intel_crtc
->plane
) {
7531 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
7534 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
7537 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
7540 WARN_ONCE(1, "unknown plane in flip command\n");
7545 ret
= intel_ring_begin(ring
, 4);
7549 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
7550 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
7551 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
7552 intel_ring_emit(ring
, (MI_NOOP
));
7554 intel_mark_page_flip_active(intel_crtc
);
7555 intel_ring_advance(ring
);
7559 intel_unpin_fb_obj(obj
);
7564 static int intel_default_queue_flip(struct drm_device
*dev
,
7565 struct drm_crtc
*crtc
,
7566 struct drm_framebuffer
*fb
,
7567 struct drm_i915_gem_object
*obj
)
7572 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
7573 struct drm_framebuffer
*fb
,
7574 struct drm_pending_vblank_event
*event
)
7576 struct drm_device
*dev
= crtc
->dev
;
7577 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7578 struct drm_framebuffer
*old_fb
= crtc
->fb
;
7579 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(fb
)->obj
;
7580 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7581 struct intel_unpin_work
*work
;
7582 unsigned long flags
;
7585 /* Can't change pixel format via MI display flips. */
7586 if (fb
->pixel_format
!= crtc
->fb
->pixel_format
)
7590 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7591 * Note that pitch changes could also affect these register.
7593 if (INTEL_INFO(dev
)->gen
> 3 &&
7594 (fb
->offsets
[0] != crtc
->fb
->offsets
[0] ||
7595 fb
->pitches
[0] != crtc
->fb
->pitches
[0]))
7598 work
= kzalloc(sizeof *work
, GFP_KERNEL
);
7602 work
->event
= event
;
7604 work
->old_fb_obj
= to_intel_framebuffer(old_fb
)->obj
;
7605 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
7607 ret
= drm_vblank_get(dev
, intel_crtc
->pipe
);
7611 /* We borrow the event spin lock for protecting unpin_work */
7612 spin_lock_irqsave(&dev
->event_lock
, flags
);
7613 if (intel_crtc
->unpin_work
) {
7614 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7616 drm_vblank_put(dev
, intel_crtc
->pipe
);
7618 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7621 intel_crtc
->unpin_work
= work
;
7622 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7624 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
7625 flush_workqueue(dev_priv
->wq
);
7627 ret
= i915_mutex_lock_interruptible(dev
);
7631 /* Reference the objects for the scheduled work. */
7632 drm_gem_object_reference(&work
->old_fb_obj
->base
);
7633 drm_gem_object_reference(&obj
->base
);
7637 work
->pending_flip_obj
= obj
;
7639 work
->enable_stall_check
= true;
7641 atomic_inc(&intel_crtc
->unpin_work_count
);
7642 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
7644 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
);
7646 goto cleanup_pending
;
7648 intel_disable_fbc(dev
);
7649 intel_mark_fb_busy(obj
, NULL
);
7650 mutex_unlock(&dev
->struct_mutex
);
7652 trace_i915_flip_request(intel_crtc
->plane
, obj
);
7657 atomic_dec(&intel_crtc
->unpin_work_count
);
7659 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
7660 drm_gem_object_unreference(&obj
->base
);
7661 mutex_unlock(&dev
->struct_mutex
);
7664 spin_lock_irqsave(&dev
->event_lock
, flags
);
7665 intel_crtc
->unpin_work
= NULL
;
7666 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7668 drm_vblank_put(dev
, intel_crtc
->pipe
);
7675 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
7676 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
7677 .load_lut
= intel_crtc_load_lut
,
7680 static bool intel_encoder_crtc_ok(struct drm_encoder
*encoder
,
7681 struct drm_crtc
*crtc
)
7683 struct drm_device
*dev
;
7684 struct drm_crtc
*tmp
;
7687 WARN(!crtc
, "checking null crtc?\n");
7691 list_for_each_entry(tmp
, &dev
->mode_config
.crtc_list
, head
) {
7697 if (encoder
->possible_crtcs
& crtc_mask
)
7703 * intel_modeset_update_staged_output_state
7705 * Updates the staged output configuration state, e.g. after we've read out the
7708 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
7710 struct intel_encoder
*encoder
;
7711 struct intel_connector
*connector
;
7713 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7715 connector
->new_encoder
=
7716 to_intel_encoder(connector
->base
.encoder
);
7719 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7722 to_intel_crtc(encoder
->base
.crtc
);
7727 * intel_modeset_commit_output_state
7729 * This function copies the stage display pipe configuration to the real one.
7731 static void intel_modeset_commit_output_state(struct drm_device
*dev
)
7733 struct intel_encoder
*encoder
;
7734 struct intel_connector
*connector
;
7736 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7738 connector
->base
.encoder
= &connector
->new_encoder
->base
;
7741 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7743 encoder
->base
.crtc
= &encoder
->new_crtc
->base
;
7748 connected_sink_compute_bpp(struct intel_connector
* connector
,
7749 struct intel_crtc_config
*pipe_config
)
7751 int bpp
= pipe_config
->pipe_bpp
;
7753 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7754 connector
->base
.base
.id
,
7755 drm_get_connector_name(&connector
->base
));
7757 /* Don't use an invalid EDID bpc value */
7758 if (connector
->base
.display_info
.bpc
&&
7759 connector
->base
.display_info
.bpc
* 3 < bpp
) {
7760 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7761 bpp
, connector
->base
.display_info
.bpc
*3);
7762 pipe_config
->pipe_bpp
= connector
->base
.display_info
.bpc
*3;
7765 /* Clamp bpp to 8 on screens without EDID 1.4 */
7766 if (connector
->base
.display_info
.bpc
== 0 && bpp
> 24) {
7767 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7769 pipe_config
->pipe_bpp
= 24;
7774 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
7775 struct drm_framebuffer
*fb
,
7776 struct intel_crtc_config
*pipe_config
)
7778 struct drm_device
*dev
= crtc
->base
.dev
;
7779 struct intel_connector
*connector
;
7782 switch (fb
->pixel_format
) {
7784 bpp
= 8*3; /* since we go through a colormap */
7786 case DRM_FORMAT_XRGB1555
:
7787 case DRM_FORMAT_ARGB1555
:
7788 /* checked in intel_framebuffer_init already */
7789 if (WARN_ON(INTEL_INFO(dev
)->gen
> 3))
7791 case DRM_FORMAT_RGB565
:
7792 bpp
= 6*3; /* min is 18bpp */
7794 case DRM_FORMAT_XBGR8888
:
7795 case DRM_FORMAT_ABGR8888
:
7796 /* checked in intel_framebuffer_init already */
7797 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
7799 case DRM_FORMAT_XRGB8888
:
7800 case DRM_FORMAT_ARGB8888
:
7803 case DRM_FORMAT_XRGB2101010
:
7804 case DRM_FORMAT_ARGB2101010
:
7805 case DRM_FORMAT_XBGR2101010
:
7806 case DRM_FORMAT_ABGR2101010
:
7807 /* checked in intel_framebuffer_init already */
7808 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
7812 /* TODO: gen4+ supports 16 bpc floating point, too. */
7814 DRM_DEBUG_KMS("unsupported depth\n");
7818 pipe_config
->pipe_bpp
= bpp
;
7820 /* Clamp display bpp to EDID value */
7821 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7823 if (!connector
->new_encoder
||
7824 connector
->new_encoder
->new_crtc
!= crtc
)
7827 connected_sink_compute_bpp(connector
, pipe_config
);
7833 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
7834 struct intel_crtc_config
*pipe_config
,
7835 const char *context
)
7837 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc
->base
.base
.id
,
7838 context
, pipe_name(crtc
->pipe
));
7840 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config
->cpu_transcoder
));
7841 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7842 pipe_config
->pipe_bpp
, pipe_config
->dither
);
7843 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7844 pipe_config
->has_pch_encoder
,
7845 pipe_config
->fdi_lanes
,
7846 pipe_config
->fdi_m_n
.gmch_m
, pipe_config
->fdi_m_n
.gmch_n
,
7847 pipe_config
->fdi_m_n
.link_m
, pipe_config
->fdi_m_n
.link_n
,
7848 pipe_config
->fdi_m_n
.tu
);
7849 DRM_DEBUG_KMS("requested mode:\n");
7850 drm_mode_debug_printmodeline(&pipe_config
->requested_mode
);
7851 DRM_DEBUG_KMS("adjusted mode:\n");
7852 drm_mode_debug_printmodeline(&pipe_config
->adjusted_mode
);
7853 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7854 pipe_config
->gmch_pfit
.control
,
7855 pipe_config
->gmch_pfit
.pgm_ratios
,
7856 pipe_config
->gmch_pfit
.lvds_border_bits
);
7857 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7858 pipe_config
->pch_pfit
.pos
,
7859 pipe_config
->pch_pfit
.size
);
7860 DRM_DEBUG_KMS("ips: %i\n", pipe_config
->ips_enabled
);
7863 static bool check_encoder_cloning(struct drm_crtc
*crtc
)
7865 int num_encoders
= 0;
7866 bool uncloneable_encoders
= false;
7867 struct intel_encoder
*encoder
;
7869 list_for_each_entry(encoder
, &crtc
->dev
->mode_config
.encoder_list
,
7871 if (&encoder
->new_crtc
->base
!= crtc
)
7875 if (!encoder
->cloneable
)
7876 uncloneable_encoders
= true;
7879 return !(num_encoders
> 1 && uncloneable_encoders
);
7882 static struct intel_crtc_config
*
7883 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
7884 struct drm_framebuffer
*fb
,
7885 struct drm_display_mode
*mode
)
7887 struct drm_device
*dev
= crtc
->dev
;
7888 struct drm_encoder_helper_funcs
*encoder_funcs
;
7889 struct intel_encoder
*encoder
;
7890 struct intel_crtc_config
*pipe_config
;
7891 int plane_bpp
, ret
= -EINVAL
;
7894 if (!check_encoder_cloning(crtc
)) {
7895 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
7896 return ERR_PTR(-EINVAL
);
7899 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
7901 return ERR_PTR(-ENOMEM
);
7903 drm_mode_copy(&pipe_config
->adjusted_mode
, mode
);
7904 drm_mode_copy(&pipe_config
->requested_mode
, mode
);
7905 pipe_config
->cpu_transcoder
=
7906 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
7907 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
7909 /* Compute a starting value for pipe_config->pipe_bpp taking the source
7910 * plane pixel format and any sink constraints into account. Returns the
7911 * source plane bpp so that dithering can be selected on mismatches
7912 * after encoders and crtc also have had their say. */
7913 plane_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
7919 /* Ensure the port clock defaults are reset when retrying. */
7920 pipe_config
->port_clock
= 0;
7921 pipe_config
->pixel_multiplier
= 1;
7923 /* Pass our mode to the connectors and the CRTC to give them a chance to
7924 * adjust it according to limitations or connector properties, and also
7925 * a chance to reject the mode entirely.
7927 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7930 if (&encoder
->new_crtc
->base
!= crtc
)
7933 if (encoder
->compute_config
) {
7934 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
7935 DRM_DEBUG_KMS("Encoder config failure\n");
7942 encoder_funcs
= encoder
->base
.helper_private
;
7943 if (!(encoder_funcs
->mode_fixup(&encoder
->base
,
7944 &pipe_config
->requested_mode
,
7945 &pipe_config
->adjusted_mode
))) {
7946 DRM_DEBUG_KMS("Encoder fixup failed\n");
7951 /* Set default port clock if not overwritten by the encoder. Needs to be
7952 * done afterwards in case the encoder adjusts the mode. */
7953 if (!pipe_config
->port_clock
)
7954 pipe_config
->port_clock
= pipe_config
->adjusted_mode
.clock
;
7956 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
7958 DRM_DEBUG_KMS("CRTC fixup failed\n");
7963 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
7968 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7973 pipe_config
->dither
= pipe_config
->pipe_bpp
!= plane_bpp
;
7974 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7975 plane_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
7980 return ERR_PTR(ret
);
7983 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7984 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7986 intel_modeset_affected_pipes(struct drm_crtc
*crtc
, unsigned *modeset_pipes
,
7987 unsigned *prepare_pipes
, unsigned *disable_pipes
)
7989 struct intel_crtc
*intel_crtc
;
7990 struct drm_device
*dev
= crtc
->dev
;
7991 struct intel_encoder
*encoder
;
7992 struct intel_connector
*connector
;
7993 struct drm_crtc
*tmp_crtc
;
7995 *disable_pipes
= *modeset_pipes
= *prepare_pipes
= 0;
7997 /* Check which crtcs have changed outputs connected to them, these need
7998 * to be part of the prepare_pipes mask. We don't (yet) support global
7999 * modeset across multiple crtcs, so modeset_pipes will only have one
8000 * bit set at most. */
8001 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8003 if (connector
->base
.encoder
== &connector
->new_encoder
->base
)
8006 if (connector
->base
.encoder
) {
8007 tmp_crtc
= connector
->base
.encoder
->crtc
;
8009 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
8012 if (connector
->new_encoder
)
8014 1 << connector
->new_encoder
->new_crtc
->pipe
;
8017 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8019 if (encoder
->base
.crtc
== &encoder
->new_crtc
->base
)
8022 if (encoder
->base
.crtc
) {
8023 tmp_crtc
= encoder
->base
.crtc
;
8025 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
8028 if (encoder
->new_crtc
)
8029 *prepare_pipes
|= 1 << encoder
->new_crtc
->pipe
;
8032 /* Check for any pipes that will be fully disabled ... */
8033 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
8037 /* Don't try to disable disabled crtcs. */
8038 if (!intel_crtc
->base
.enabled
)
8041 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8043 if (encoder
->new_crtc
== intel_crtc
)
8048 *disable_pipes
|= 1 << intel_crtc
->pipe
;
8052 /* set_mode is also used to update properties on life display pipes. */
8053 intel_crtc
= to_intel_crtc(crtc
);
8055 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
8058 * For simplicity do a full modeset on any pipe where the output routing
8059 * changed. We could be more clever, but that would require us to be
8060 * more careful with calling the relevant encoder->mode_set functions.
8063 *modeset_pipes
= *prepare_pipes
;
8065 /* ... and mask these out. */
8066 *modeset_pipes
&= ~(*disable_pipes
);
8067 *prepare_pipes
&= ~(*disable_pipes
);
8070 * HACK: We don't (yet) fully support global modesets. intel_set_config
8071 * obies this rule, but the modeset restore mode of
8072 * intel_modeset_setup_hw_state does not.
8074 *modeset_pipes
&= 1 << intel_crtc
->pipe
;
8075 *prepare_pipes
&= 1 << intel_crtc
->pipe
;
8077 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8078 *modeset_pipes
, *prepare_pipes
, *disable_pipes
);
8081 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
8083 struct drm_encoder
*encoder
;
8084 struct drm_device
*dev
= crtc
->dev
;
8086 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
8087 if (encoder
->crtc
== crtc
)
8094 intel_modeset_update_state(struct drm_device
*dev
, unsigned prepare_pipes
)
8096 struct intel_encoder
*intel_encoder
;
8097 struct intel_crtc
*intel_crtc
;
8098 struct drm_connector
*connector
;
8100 list_for_each_entry(intel_encoder
, &dev
->mode_config
.encoder_list
,
8102 if (!intel_encoder
->base
.crtc
)
8105 intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
8107 if (prepare_pipes
& (1 << intel_crtc
->pipe
))
8108 intel_encoder
->connectors_active
= false;
8111 intel_modeset_commit_output_state(dev
);
8113 /* Update computed state. */
8114 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
8116 intel_crtc
->base
.enabled
= intel_crtc_in_use(&intel_crtc
->base
);
8119 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
8120 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
8123 intel_crtc
= to_intel_crtc(connector
->encoder
->crtc
);
8125 if (prepare_pipes
& (1 << intel_crtc
->pipe
)) {
8126 struct drm_property
*dpms_property
=
8127 dev
->mode_config
.dpms_property
;
8129 connector
->dpms
= DRM_MODE_DPMS_ON
;
8130 drm_object_property_set_value(&connector
->base
,
8134 intel_encoder
= to_intel_encoder(connector
->encoder
);
8135 intel_encoder
->connectors_active
= true;
8141 static bool intel_fuzzy_clock_check(struct intel_crtc_config
*cur
,
8142 struct intel_crtc_config
*new)
8144 int clock1
, clock2
, diff
;
8146 clock1
= cur
->adjusted_mode
.clock
;
8147 clock2
= new->adjusted_mode
.clock
;
8149 if (clock1
== clock2
)
8152 if (!clock1
|| !clock2
)
8155 diff
= abs(clock1
- clock2
);
8157 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
8163 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8164 list_for_each_entry((intel_crtc), \
8165 &(dev)->mode_config.crtc_list, \
8167 if (mask & (1 <<(intel_crtc)->pipe))
8170 intel_pipe_config_compare(struct drm_device
*dev
,
8171 struct intel_crtc_config
*current_config
,
8172 struct intel_crtc_config
*pipe_config
)
8174 #define PIPE_CONF_CHECK_X(name) \
8175 if (current_config->name != pipe_config->name) { \
8176 DRM_ERROR("mismatch in " #name " " \
8177 "(expected 0x%08x, found 0x%08x)\n", \
8178 current_config->name, \
8179 pipe_config->name); \
8183 #define PIPE_CONF_CHECK_I(name) \
8184 if (current_config->name != pipe_config->name) { \
8185 DRM_ERROR("mismatch in " #name " " \
8186 "(expected %i, found %i)\n", \
8187 current_config->name, \
8188 pipe_config->name); \
8192 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
8193 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8194 DRM_ERROR("mismatch in " #name "(" #mask ") " \
8195 "(expected %i, found %i)\n", \
8196 current_config->name & (mask), \
8197 pipe_config->name & (mask)); \
8201 #define PIPE_CONF_QUIRK(quirk) \
8202 ((current_config->quirks | pipe_config->quirks) & (quirk))
8204 PIPE_CONF_CHECK_I(cpu_transcoder
);
8206 PIPE_CONF_CHECK_I(has_pch_encoder
);
8207 PIPE_CONF_CHECK_I(fdi_lanes
);
8208 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_m
);
8209 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_n
);
8210 PIPE_CONF_CHECK_I(fdi_m_n
.link_m
);
8211 PIPE_CONF_CHECK_I(fdi_m_n
.link_n
);
8212 PIPE_CONF_CHECK_I(fdi_m_n
.tu
);
8214 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hdisplay
);
8215 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_htotal
);
8216 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_start
);
8217 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_end
);
8218 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_start
);
8219 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_end
);
8221 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vdisplay
);
8222 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vtotal
);
8223 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_start
);
8224 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_end
);
8225 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_start
);
8226 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_end
);
8228 PIPE_CONF_CHECK_I(pixel_multiplier
);
8230 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8231 DRM_MODE_FLAG_INTERLACE
);
8233 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
8234 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8235 DRM_MODE_FLAG_PHSYNC
);
8236 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8237 DRM_MODE_FLAG_NHSYNC
);
8238 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8239 DRM_MODE_FLAG_PVSYNC
);
8240 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8241 DRM_MODE_FLAG_NVSYNC
);
8244 PIPE_CONF_CHECK_I(requested_mode
.hdisplay
);
8245 PIPE_CONF_CHECK_I(requested_mode
.vdisplay
);
8247 PIPE_CONF_CHECK_I(gmch_pfit
.control
);
8248 /* pfit ratios are autocomputed by the hw on gen4+ */
8249 if (INTEL_INFO(dev
)->gen
< 4)
8250 PIPE_CONF_CHECK_I(gmch_pfit
.pgm_ratios
);
8251 PIPE_CONF_CHECK_I(gmch_pfit
.lvds_border_bits
);
8252 PIPE_CONF_CHECK_I(pch_pfit
.pos
);
8253 PIPE_CONF_CHECK_I(pch_pfit
.size
);
8255 PIPE_CONF_CHECK_I(ips_enabled
);
8257 PIPE_CONF_CHECK_I(shared_dpll
);
8258 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
8259 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
8260 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
8261 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
8263 #undef PIPE_CONF_CHECK_X
8264 #undef PIPE_CONF_CHECK_I
8265 #undef PIPE_CONF_CHECK_FLAGS
8266 #undef PIPE_CONF_QUIRK
8268 if (!IS_HASWELL(dev
)) {
8269 if (!intel_fuzzy_clock_check(current_config
, pipe_config
)) {
8270 DRM_ERROR("mismatch in clock (expected %d, found %d)\n",
8271 current_config
->adjusted_mode
.clock
,
8272 pipe_config
->adjusted_mode
.clock
);
8281 check_connector_state(struct drm_device
*dev
)
8283 struct intel_connector
*connector
;
8285 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8287 /* This also checks the encoder/connector hw state with the
8288 * ->get_hw_state callbacks. */
8289 intel_connector_check_state(connector
);
8291 WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
8292 "connector's staged encoder doesn't match current encoder\n");
8297 check_encoder_state(struct drm_device
*dev
)
8299 struct intel_encoder
*encoder
;
8300 struct intel_connector
*connector
;
8302 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8304 bool enabled
= false;
8305 bool active
= false;
8306 enum pipe pipe
, tracked_pipe
;
8308 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8309 encoder
->base
.base
.id
,
8310 drm_get_encoder_name(&encoder
->base
));
8312 WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
8313 "encoder's stage crtc doesn't match current crtc\n");
8314 WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
8315 "encoder's active_connectors set, but no crtc\n");
8317 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8319 if (connector
->base
.encoder
!= &encoder
->base
)
8322 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
8325 WARN(!!encoder
->base
.crtc
!= enabled
,
8326 "encoder's enabled state mismatch "
8327 "(expected %i, found %i)\n",
8328 !!encoder
->base
.crtc
, enabled
);
8329 WARN(active
&& !encoder
->base
.crtc
,
8330 "active encoder with no crtc\n");
8332 WARN(encoder
->connectors_active
!= active
,
8333 "encoder's computed active state doesn't match tracked active state "
8334 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
8336 active
= encoder
->get_hw_state(encoder
, &pipe
);
8337 WARN(active
!= encoder
->connectors_active
,
8338 "encoder's hw state doesn't match sw tracking "
8339 "(expected %i, found %i)\n",
8340 encoder
->connectors_active
, active
);
8342 if (!encoder
->base
.crtc
)
8345 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
8346 WARN(active
&& pipe
!= tracked_pipe
,
8347 "active encoder's pipe doesn't match"
8348 "(expected %i, found %i)\n",
8349 tracked_pipe
, pipe
);
8355 check_crtc_state(struct drm_device
*dev
)
8357 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8358 struct intel_crtc
*crtc
;
8359 struct intel_encoder
*encoder
;
8360 struct intel_crtc_config pipe_config
;
8362 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
8364 bool enabled
= false;
8365 bool active
= false;
8367 memset(&pipe_config
, 0, sizeof(pipe_config
));
8369 DRM_DEBUG_KMS("[CRTC:%d]\n",
8370 crtc
->base
.base
.id
);
8372 WARN(crtc
->active
&& !crtc
->base
.enabled
,
8373 "active crtc, but not enabled in sw tracking\n");
8375 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8377 if (encoder
->base
.crtc
!= &crtc
->base
)
8380 if (encoder
->connectors_active
)
8384 WARN(active
!= crtc
->active
,
8385 "crtc's computed active state doesn't match tracked active state "
8386 "(expected %i, found %i)\n", active
, crtc
->active
);
8387 WARN(enabled
!= crtc
->base
.enabled
,
8388 "crtc's computed enabled state doesn't match tracked enabled state "
8389 "(expected %i, found %i)\n", enabled
, crtc
->base
.enabled
);
8391 active
= dev_priv
->display
.get_pipe_config(crtc
,
8394 /* hw state is inconsistent with the pipe A quirk */
8395 if (crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
8396 active
= crtc
->active
;
8398 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8400 if (encoder
->base
.crtc
!= &crtc
->base
)
8402 if (encoder
->get_config
)
8403 encoder
->get_config(encoder
, &pipe_config
);
8406 if (dev_priv
->display
.get_clock
)
8407 dev_priv
->display
.get_clock(crtc
, &pipe_config
);
8409 WARN(crtc
->active
!= active
,
8410 "crtc active state doesn't match with hw state "
8411 "(expected %i, found %i)\n", crtc
->active
, active
);
8414 !intel_pipe_config_compare(dev
, &crtc
->config
, &pipe_config
)) {
8415 WARN(1, "pipe state doesn't match!\n");
8416 intel_dump_pipe_config(crtc
, &pipe_config
,
8418 intel_dump_pipe_config(crtc
, &crtc
->config
,
8425 check_shared_dpll_state(struct drm_device
*dev
)
8427 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8428 struct intel_crtc
*crtc
;
8429 struct intel_dpll_hw_state dpll_hw_state
;
8432 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
8433 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
8434 int enabled_crtcs
= 0, active_crtcs
= 0;
8437 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
8439 DRM_DEBUG_KMS("%s\n", pll
->name
);
8441 active
= pll
->get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
8443 WARN(pll
->active
> pll
->refcount
,
8444 "more active pll users than references: %i vs %i\n",
8445 pll
->active
, pll
->refcount
);
8446 WARN(pll
->active
&& !pll
->on
,
8447 "pll in active use but not on in sw tracking\n");
8448 WARN(pll
->on
!= active
,
8449 "pll on state mismatch (expected %i, found %i)\n",
8452 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
8454 if (crtc
->base
.enabled
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
8456 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
8459 WARN(pll
->active
!= active_crtcs
,
8460 "pll active crtcs mismatch (expected %i, found %i)\n",
8461 pll
->active
, active_crtcs
);
8462 WARN(pll
->refcount
!= enabled_crtcs
,
8463 "pll enabled crtcs mismatch (expected %i, found %i)\n",
8464 pll
->refcount
, enabled_crtcs
);
8466 WARN(pll
->on
&& memcmp(&pll
->hw_state
, &dpll_hw_state
,
8467 sizeof(dpll_hw_state
)),
8468 "pll hw state mismatch\n");
8473 intel_modeset_check_state(struct drm_device
*dev
)
8475 check_connector_state(dev
);
8476 check_encoder_state(dev
);
8477 check_crtc_state(dev
);
8478 check_shared_dpll_state(dev
);
8481 static int __intel_set_mode(struct drm_crtc
*crtc
,
8482 struct drm_display_mode
*mode
,
8483 int x
, int y
, struct drm_framebuffer
*fb
)
8485 struct drm_device
*dev
= crtc
->dev
;
8486 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8487 struct drm_display_mode
*saved_mode
, *saved_hwmode
;
8488 struct intel_crtc_config
*pipe_config
= NULL
;
8489 struct intel_crtc
*intel_crtc
;
8490 unsigned disable_pipes
, prepare_pipes
, modeset_pipes
;
8493 saved_mode
= kmalloc(2 * sizeof(*saved_mode
), GFP_KERNEL
);
8496 saved_hwmode
= saved_mode
+ 1;
8498 intel_modeset_affected_pipes(crtc
, &modeset_pipes
,
8499 &prepare_pipes
, &disable_pipes
);
8501 *saved_hwmode
= crtc
->hwmode
;
8502 *saved_mode
= crtc
->mode
;
8504 /* Hack: Because we don't (yet) support global modeset on multiple
8505 * crtcs, we don't keep track of the new mode for more than one crtc.
8506 * Hence simply check whether any bit is set in modeset_pipes in all the
8507 * pieces of code that are not yet converted to deal with mutliple crtcs
8508 * changing their mode at the same time. */
8509 if (modeset_pipes
) {
8510 pipe_config
= intel_modeset_pipe_config(crtc
, fb
, mode
);
8511 if (IS_ERR(pipe_config
)) {
8512 ret
= PTR_ERR(pipe_config
);
8517 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,
8521 for_each_intel_crtc_masked(dev
, disable_pipes
, intel_crtc
)
8522 intel_crtc_disable(&intel_crtc
->base
);
8524 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
8525 if (intel_crtc
->base
.enabled
)
8526 dev_priv
->display
.crtc_disable(&intel_crtc
->base
);
8529 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8530 * to set it here already despite that we pass it down the callchain.
8532 if (modeset_pipes
) {
8534 /* mode_set/enable/disable functions rely on a correct pipe
8536 to_intel_crtc(crtc
)->config
= *pipe_config
;
8539 /* Only after disabling all output pipelines that will be changed can we
8540 * update the the output configuration. */
8541 intel_modeset_update_state(dev
, prepare_pipes
);
8543 if (dev_priv
->display
.modeset_global_resources
)
8544 dev_priv
->display
.modeset_global_resources(dev
);
8546 /* Set up the DPLL and any encoders state that needs to adjust or depend
8549 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
8550 ret
= intel_crtc_mode_set(&intel_crtc
->base
,
8556 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8557 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
)
8558 dev_priv
->display
.crtc_enable(&intel_crtc
->base
);
8560 if (modeset_pipes
) {
8561 /* Store real post-adjustment hardware mode. */
8562 crtc
->hwmode
= pipe_config
->adjusted_mode
;
8564 /* Calculate and store various constants which
8565 * are later needed by vblank and swap-completion
8566 * timestamping. They are derived from true hwmode.
8568 drm_calc_timestamping_constants(crtc
);
8571 /* FIXME: add subpixel order */
8573 if (ret
&& crtc
->enabled
) {
8574 crtc
->hwmode
= *saved_hwmode
;
8575 crtc
->mode
= *saved_mode
;
8584 int intel_set_mode(struct drm_crtc
*crtc
,
8585 struct drm_display_mode
*mode
,
8586 int x
, int y
, struct drm_framebuffer
*fb
)
8590 ret
= __intel_set_mode(crtc
, mode
, x
, y
, fb
);
8593 intel_modeset_check_state(crtc
->dev
);
8598 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
8600 intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
, crtc
->fb
);
8603 #undef for_each_intel_crtc_masked
8605 static void intel_set_config_free(struct intel_set_config
*config
)
8610 kfree(config
->save_connector_encoders
);
8611 kfree(config
->save_encoder_crtcs
);
8615 static int intel_set_config_save_state(struct drm_device
*dev
,
8616 struct intel_set_config
*config
)
8618 struct drm_encoder
*encoder
;
8619 struct drm_connector
*connector
;
8622 config
->save_encoder_crtcs
=
8623 kcalloc(dev
->mode_config
.num_encoder
,
8624 sizeof(struct drm_crtc
*), GFP_KERNEL
);
8625 if (!config
->save_encoder_crtcs
)
8628 config
->save_connector_encoders
=
8629 kcalloc(dev
->mode_config
.num_connector
,
8630 sizeof(struct drm_encoder
*), GFP_KERNEL
);
8631 if (!config
->save_connector_encoders
)
8634 /* Copy data. Note that driver private data is not affected.
8635 * Should anything bad happen only the expected state is
8636 * restored, not the drivers personal bookkeeping.
8639 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
8640 config
->save_encoder_crtcs
[count
++] = encoder
->crtc
;
8644 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
8645 config
->save_connector_encoders
[count
++] = connector
->encoder
;
8651 static void intel_set_config_restore_state(struct drm_device
*dev
,
8652 struct intel_set_config
*config
)
8654 struct intel_encoder
*encoder
;
8655 struct intel_connector
*connector
;
8659 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
8661 to_intel_crtc(config
->save_encoder_crtcs
[count
++]);
8665 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
8666 connector
->new_encoder
=
8667 to_intel_encoder(config
->save_connector_encoders
[count
++]);
8672 is_crtc_connector_off(struct drm_crtc
*crtc
, struct drm_connector
*connectors
,
8677 for (i
= 0; i
< num_connectors
; i
++)
8678 if (connectors
[i
].encoder
&&
8679 connectors
[i
].encoder
->crtc
== crtc
&&
8680 connectors
[i
].dpms
!= DRM_MODE_DPMS_ON
)
8687 intel_set_config_compute_mode_changes(struct drm_mode_set
*set
,
8688 struct intel_set_config
*config
)
8691 /* We should be able to check here if the fb has the same properties
8692 * and then just flip_or_move it */
8693 if (set
->connectors
!= NULL
&&
8694 is_crtc_connector_off(set
->crtc
, *set
->connectors
,
8695 set
->num_connectors
)) {
8696 config
->mode_changed
= true;
8697 } else if (set
->crtc
->fb
!= set
->fb
) {
8698 /* If we have no fb then treat it as a full mode set */
8699 if (set
->crtc
->fb
== NULL
) {
8700 struct intel_crtc
*intel_crtc
=
8701 to_intel_crtc(set
->crtc
);
8703 if (intel_crtc
->active
&& i915_fastboot
) {
8704 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
8705 config
->fb_changed
= true;
8707 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
8708 config
->mode_changed
= true;
8710 } else if (set
->fb
== NULL
) {
8711 config
->mode_changed
= true;
8712 } else if (set
->fb
->pixel_format
!=
8713 set
->crtc
->fb
->pixel_format
) {
8714 config
->mode_changed
= true;
8716 config
->fb_changed
= true;
8720 if (set
->fb
&& (set
->x
!= set
->crtc
->x
|| set
->y
!= set
->crtc
->y
))
8721 config
->fb_changed
= true;
8723 if (set
->mode
&& !drm_mode_equal(set
->mode
, &set
->crtc
->mode
)) {
8724 DRM_DEBUG_KMS("modes are different, full mode set\n");
8725 drm_mode_debug_printmodeline(&set
->crtc
->mode
);
8726 drm_mode_debug_printmodeline(set
->mode
);
8727 config
->mode_changed
= true;
8732 intel_modeset_stage_output_state(struct drm_device
*dev
,
8733 struct drm_mode_set
*set
,
8734 struct intel_set_config
*config
)
8736 struct drm_crtc
*new_crtc
;
8737 struct intel_connector
*connector
;
8738 struct intel_encoder
*encoder
;
8741 /* The upper layers ensure that we either disable a crtc or have a list
8742 * of connectors. For paranoia, double-check this. */
8743 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
8744 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
8747 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8749 /* Otherwise traverse passed in connector list and get encoders
8751 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
8752 if (set
->connectors
[ro
] == &connector
->base
) {
8753 connector
->new_encoder
= connector
->encoder
;
8758 /* If we disable the crtc, disable all its connectors. Also, if
8759 * the connector is on the changing crtc but not on the new
8760 * connector list, disable it. */
8761 if ((!set
->fb
|| ro
== set
->num_connectors
) &&
8762 connector
->base
.encoder
&&
8763 connector
->base
.encoder
->crtc
== set
->crtc
) {
8764 connector
->new_encoder
= NULL
;
8766 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8767 connector
->base
.base
.id
,
8768 drm_get_connector_name(&connector
->base
));
8772 if (&connector
->new_encoder
->base
!= connector
->base
.encoder
) {
8773 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8774 config
->mode_changed
= true;
8777 /* connector->new_encoder is now updated for all connectors. */
8779 /* Update crtc of enabled connectors. */
8781 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8783 if (!connector
->new_encoder
)
8786 new_crtc
= connector
->new_encoder
->base
.crtc
;
8788 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
8789 if (set
->connectors
[ro
] == &connector
->base
)
8790 new_crtc
= set
->crtc
;
8793 /* Make sure the new CRTC will work with the encoder */
8794 if (!intel_encoder_crtc_ok(&connector
->new_encoder
->base
,
8798 connector
->encoder
->new_crtc
= to_intel_crtc(new_crtc
);
8800 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8801 connector
->base
.base
.id
,
8802 drm_get_connector_name(&connector
->base
),
8806 /* Check for any encoders that needs to be disabled. */
8807 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8809 list_for_each_entry(connector
,
8810 &dev
->mode_config
.connector_list
,
8812 if (connector
->new_encoder
== encoder
) {
8813 WARN_ON(!connector
->new_encoder
->new_crtc
);
8818 encoder
->new_crtc
= NULL
;
8820 /* Only now check for crtc changes so we don't miss encoders
8821 * that will be disabled. */
8822 if (&encoder
->new_crtc
->base
!= encoder
->base
.crtc
) {
8823 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8824 config
->mode_changed
= true;
8827 /* Now we've also updated encoder->new_crtc for all encoders. */
8832 static int intel_crtc_set_config(struct drm_mode_set
*set
)
8834 struct drm_device
*dev
;
8835 struct drm_mode_set save_set
;
8836 struct intel_set_config
*config
;
8841 BUG_ON(!set
->crtc
->helper_private
);
8843 /* Enforce sane interface api - has been abused by the fb helper. */
8844 BUG_ON(!set
->mode
&& set
->fb
);
8845 BUG_ON(set
->fb
&& set
->num_connectors
== 0);
8848 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8849 set
->crtc
->base
.id
, set
->fb
->base
.id
,
8850 (int)set
->num_connectors
, set
->x
, set
->y
);
8852 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
8855 dev
= set
->crtc
->dev
;
8858 config
= kzalloc(sizeof(*config
), GFP_KERNEL
);
8862 ret
= intel_set_config_save_state(dev
, config
);
8866 save_set
.crtc
= set
->crtc
;
8867 save_set
.mode
= &set
->crtc
->mode
;
8868 save_set
.x
= set
->crtc
->x
;
8869 save_set
.y
= set
->crtc
->y
;
8870 save_set
.fb
= set
->crtc
->fb
;
8872 /* Compute whether we need a full modeset, only an fb base update or no
8873 * change at all. In the future we might also check whether only the
8874 * mode changed, e.g. for LVDS where we only change the panel fitter in
8876 intel_set_config_compute_mode_changes(set
, config
);
8878 ret
= intel_modeset_stage_output_state(dev
, set
, config
);
8882 if (config
->mode_changed
) {
8883 ret
= intel_set_mode(set
->crtc
, set
->mode
,
8884 set
->x
, set
->y
, set
->fb
);
8885 } else if (config
->fb_changed
) {
8886 intel_crtc_wait_for_pending_flips(set
->crtc
);
8888 ret
= intel_pipe_set_base(set
->crtc
,
8889 set
->x
, set
->y
, set
->fb
);
8893 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
8894 set
->crtc
->base
.id
, ret
);
8896 intel_set_config_restore_state(dev
, config
);
8898 /* Try to restore the config */
8899 if (config
->mode_changed
&&
8900 intel_set_mode(save_set
.crtc
, save_set
.mode
,
8901 save_set
.x
, save_set
.y
, save_set
.fb
))
8902 DRM_ERROR("failed to restore config after modeset failure\n");
8906 intel_set_config_free(config
);
8910 static const struct drm_crtc_funcs intel_crtc_funcs
= {
8911 .cursor_set
= intel_crtc_cursor_set
,
8912 .cursor_move
= intel_crtc_cursor_move
,
8913 .gamma_set
= intel_crtc_gamma_set
,
8914 .set_config
= intel_crtc_set_config
,
8915 .destroy
= intel_crtc_destroy
,
8916 .page_flip
= intel_crtc_page_flip
,
8919 static void intel_cpu_pll_init(struct drm_device
*dev
)
8922 intel_ddi_pll_init(dev
);
8925 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private
*dev_priv
,
8926 struct intel_shared_dpll
*pll
,
8927 struct intel_dpll_hw_state
*hw_state
)
8931 val
= I915_READ(PCH_DPLL(pll
->id
));
8932 hw_state
->dpll
= val
;
8933 hw_state
->fp0
= I915_READ(PCH_FP0(pll
->id
));
8934 hw_state
->fp1
= I915_READ(PCH_FP1(pll
->id
));
8936 return val
& DPLL_VCO_ENABLE
;
8939 static void ibx_pch_dpll_mode_set(struct drm_i915_private
*dev_priv
,
8940 struct intel_shared_dpll
*pll
)
8942 I915_WRITE(PCH_FP0(pll
->id
), pll
->hw_state
.fp0
);
8943 I915_WRITE(PCH_FP1(pll
->id
), pll
->hw_state
.fp1
);
8946 static void ibx_pch_dpll_enable(struct drm_i915_private
*dev_priv
,
8947 struct intel_shared_dpll
*pll
)
8949 /* PCH refclock must be enabled first */
8950 assert_pch_refclk_enabled(dev_priv
);
8952 I915_WRITE(PCH_DPLL(pll
->id
), pll
->hw_state
.dpll
);
8954 /* Wait for the clocks to stabilize. */
8955 POSTING_READ(PCH_DPLL(pll
->id
));
8958 /* The pixel multiplier can only be updated once the
8959 * DPLL is enabled and the clocks are stable.
8961 * So write it again.
8963 I915_WRITE(PCH_DPLL(pll
->id
), pll
->hw_state
.dpll
);
8964 POSTING_READ(PCH_DPLL(pll
->id
));
8968 static void ibx_pch_dpll_disable(struct drm_i915_private
*dev_priv
,
8969 struct intel_shared_dpll
*pll
)
8971 struct drm_device
*dev
= dev_priv
->dev
;
8972 struct intel_crtc
*crtc
;
8974 /* Make sure no transcoder isn't still depending on us. */
8975 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
8976 if (intel_crtc_to_shared_dpll(crtc
) == pll
)
8977 assert_pch_transcoder_disabled(dev_priv
, crtc
->pipe
);
8980 I915_WRITE(PCH_DPLL(pll
->id
), 0);
8981 POSTING_READ(PCH_DPLL(pll
->id
));
8985 static char *ibx_pch_dpll_names
[] = {
8990 static void ibx_pch_dpll_init(struct drm_device
*dev
)
8992 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8995 dev_priv
->num_shared_dpll
= 2;
8997 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
8998 dev_priv
->shared_dplls
[i
].id
= i
;
8999 dev_priv
->shared_dplls
[i
].name
= ibx_pch_dpll_names
[i
];
9000 dev_priv
->shared_dplls
[i
].mode_set
= ibx_pch_dpll_mode_set
;
9001 dev_priv
->shared_dplls
[i
].enable
= ibx_pch_dpll_enable
;
9002 dev_priv
->shared_dplls
[i
].disable
= ibx_pch_dpll_disable
;
9003 dev_priv
->shared_dplls
[i
].get_hw_state
=
9004 ibx_pch_dpll_get_hw_state
;
9008 static void intel_shared_dpll_init(struct drm_device
*dev
)
9010 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9012 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
9013 ibx_pch_dpll_init(dev
);
9015 dev_priv
->num_shared_dpll
= 0;
9017 BUG_ON(dev_priv
->num_shared_dpll
> I915_NUM_PLLS
);
9018 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9019 dev_priv
->num_shared_dpll
);
9022 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
9024 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
9025 struct intel_crtc
*intel_crtc
;
9028 intel_crtc
= kzalloc(sizeof(struct intel_crtc
) + (INTELFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
9029 if (intel_crtc
== NULL
)
9032 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
9034 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
9035 for (i
= 0; i
< 256; i
++) {
9036 intel_crtc
->lut_r
[i
] = i
;
9037 intel_crtc
->lut_g
[i
] = i
;
9038 intel_crtc
->lut_b
[i
] = i
;
9041 /* Swap pipes & planes for FBC on pre-965 */
9042 intel_crtc
->pipe
= pipe
;
9043 intel_crtc
->plane
= pipe
;
9044 if (IS_MOBILE(dev
) && IS_GEN3(dev
)) {
9045 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
9046 intel_crtc
->plane
= !pipe
;
9049 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
9050 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
9051 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
9052 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
9054 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
9057 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
9058 struct drm_file
*file
)
9060 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
9061 struct drm_mode_object
*drmmode_obj
;
9062 struct intel_crtc
*crtc
;
9064 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
9067 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
9068 DRM_MODE_OBJECT_CRTC
);
9071 DRM_ERROR("no such CRTC id\n");
9075 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
9076 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
9081 static int intel_encoder_clones(struct intel_encoder
*encoder
)
9083 struct drm_device
*dev
= encoder
->base
.dev
;
9084 struct intel_encoder
*source_encoder
;
9088 list_for_each_entry(source_encoder
,
9089 &dev
->mode_config
.encoder_list
, base
.head
) {
9091 if (encoder
== source_encoder
)
9092 index_mask
|= (1 << entry
);
9094 /* Intel hw has only one MUX where enocoders could be cloned. */
9095 if (encoder
->cloneable
&& source_encoder
->cloneable
)
9096 index_mask
|= (1 << entry
);
9104 static bool has_edp_a(struct drm_device
*dev
)
9106 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9108 if (!IS_MOBILE(dev
))
9111 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
9115 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES
) & ILK_eDP_A_DISABLE
))
9121 static void intel_setup_outputs(struct drm_device
*dev
)
9123 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9124 struct intel_encoder
*encoder
;
9125 bool dpd_is_edp
= false;
9127 intel_lvds_init(dev
);
9130 intel_crt_init(dev
);
9135 /* Haswell uses DDI functions to detect digital outputs */
9136 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
9137 /* DDI A only supports eDP */
9139 intel_ddi_init(dev
, PORT_A
);
9141 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9143 found
= I915_READ(SFUSE_STRAP
);
9145 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
9146 intel_ddi_init(dev
, PORT_B
);
9147 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
9148 intel_ddi_init(dev
, PORT_C
);
9149 if (found
& SFUSE_STRAP_DDID_DETECTED
)
9150 intel_ddi_init(dev
, PORT_D
);
9151 } else if (HAS_PCH_SPLIT(dev
)) {
9153 dpd_is_edp
= intel_dpd_is_edp(dev
);
9156 intel_dp_init(dev
, DP_A
, PORT_A
);
9158 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
9159 /* PCH SDVOB multiplex with HDMIB */
9160 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
9162 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
9163 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
9164 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
9167 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
9168 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
9170 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
9171 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
9173 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
9174 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
9176 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
9177 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
9178 } else if (IS_VALLEYVIEW(dev
)) {
9179 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9180 if (I915_READ(VLV_DISPLAY_BASE
+ DP_C
) & DP_DETECTED
)
9181 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_C
, PORT_C
);
9183 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIB
) & SDVO_DETECTED
) {
9184 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIB
,
9186 if (I915_READ(VLV_DISPLAY_BASE
+ DP_B
) & DP_DETECTED
)
9187 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_B
, PORT_B
);
9189 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
9192 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
9193 DRM_DEBUG_KMS("probing SDVOB\n");
9194 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, true);
9195 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
9196 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9197 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
9200 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
))
9201 intel_dp_init(dev
, DP_B
, PORT_B
);
9204 /* Before G4X SDVOC doesn't have its own detect register */
9206 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
9207 DRM_DEBUG_KMS("probing SDVOC\n");
9208 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, false);
9211 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
9213 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
9214 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9215 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
9217 if (SUPPORTS_INTEGRATED_DP(dev
))
9218 intel_dp_init(dev
, DP_C
, PORT_C
);
9221 if (SUPPORTS_INTEGRATED_DP(dev
) &&
9222 (I915_READ(DP_D
) & DP_DETECTED
))
9223 intel_dp_init(dev
, DP_D
, PORT_D
);
9224 } else if (IS_GEN2(dev
))
9225 intel_dvo_init(dev
);
9227 if (SUPPORTS_TV(dev
))
9230 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
9231 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
9232 encoder
->base
.possible_clones
=
9233 intel_encoder_clones(encoder
);
9236 intel_init_pch_refclk(dev
);
9238 drm_helper_move_panel_connectors_to_head(dev
);
9241 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
9243 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
9245 drm_framebuffer_cleanup(fb
);
9246 drm_gem_object_unreference_unlocked(&intel_fb
->obj
->base
);
9251 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
9252 struct drm_file
*file
,
9253 unsigned int *handle
)
9255 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
9256 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
9258 return drm_gem_handle_create(file
, &obj
->base
, handle
);
9261 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
9262 .destroy
= intel_user_framebuffer_destroy
,
9263 .create_handle
= intel_user_framebuffer_create_handle
,
9266 int intel_framebuffer_init(struct drm_device
*dev
,
9267 struct intel_framebuffer
*intel_fb
,
9268 struct drm_mode_fb_cmd2
*mode_cmd
,
9269 struct drm_i915_gem_object
*obj
)
9274 if (obj
->tiling_mode
== I915_TILING_Y
) {
9275 DRM_DEBUG("hardware does not support tiling Y\n");
9279 if (mode_cmd
->pitches
[0] & 63) {
9280 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9281 mode_cmd
->pitches
[0]);
9285 if (INTEL_INFO(dev
)->gen
>= 5 && !IS_VALLEYVIEW(dev
)) {
9286 pitch_limit
= 32*1024;
9287 } else if (INTEL_INFO(dev
)->gen
>= 4) {
9288 if (obj
->tiling_mode
)
9289 pitch_limit
= 16*1024;
9291 pitch_limit
= 32*1024;
9292 } else if (INTEL_INFO(dev
)->gen
>= 3) {
9293 if (obj
->tiling_mode
)
9294 pitch_limit
= 8*1024;
9296 pitch_limit
= 16*1024;
9298 /* XXX DSPC is limited to 4k tiled */
9299 pitch_limit
= 8*1024;
9301 if (mode_cmd
->pitches
[0] > pitch_limit
) {
9302 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9303 obj
->tiling_mode
? "tiled" : "linear",
9304 mode_cmd
->pitches
[0], pitch_limit
);
9308 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
9309 mode_cmd
->pitches
[0] != obj
->stride
) {
9310 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9311 mode_cmd
->pitches
[0], obj
->stride
);
9315 /* Reject formats not supported by any plane early. */
9316 switch (mode_cmd
->pixel_format
) {
9318 case DRM_FORMAT_RGB565
:
9319 case DRM_FORMAT_XRGB8888
:
9320 case DRM_FORMAT_ARGB8888
:
9322 case DRM_FORMAT_XRGB1555
:
9323 case DRM_FORMAT_ARGB1555
:
9324 if (INTEL_INFO(dev
)->gen
> 3) {
9325 DRM_DEBUG("unsupported pixel format: %s\n",
9326 drm_get_format_name(mode_cmd
->pixel_format
));
9330 case DRM_FORMAT_XBGR8888
:
9331 case DRM_FORMAT_ABGR8888
:
9332 case DRM_FORMAT_XRGB2101010
:
9333 case DRM_FORMAT_ARGB2101010
:
9334 case DRM_FORMAT_XBGR2101010
:
9335 case DRM_FORMAT_ABGR2101010
:
9336 if (INTEL_INFO(dev
)->gen
< 4) {
9337 DRM_DEBUG("unsupported pixel format: %s\n",
9338 drm_get_format_name(mode_cmd
->pixel_format
));
9342 case DRM_FORMAT_YUYV
:
9343 case DRM_FORMAT_UYVY
:
9344 case DRM_FORMAT_YVYU
:
9345 case DRM_FORMAT_VYUY
:
9346 if (INTEL_INFO(dev
)->gen
< 5) {
9347 DRM_DEBUG("unsupported pixel format: %s\n",
9348 drm_get_format_name(mode_cmd
->pixel_format
));
9353 DRM_DEBUG("unsupported pixel format: %s\n",
9354 drm_get_format_name(mode_cmd
->pixel_format
));
9358 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9359 if (mode_cmd
->offsets
[0] != 0)
9362 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
9363 intel_fb
->obj
= obj
;
9365 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
9367 DRM_ERROR("framebuffer init failed %d\n", ret
);
9374 static struct drm_framebuffer
*
9375 intel_user_framebuffer_create(struct drm_device
*dev
,
9376 struct drm_file
*filp
,
9377 struct drm_mode_fb_cmd2
*mode_cmd
)
9379 struct drm_i915_gem_object
*obj
;
9381 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
9382 mode_cmd
->handles
[0]));
9383 if (&obj
->base
== NULL
)
9384 return ERR_PTR(-ENOENT
);
9386 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
9389 static const struct drm_mode_config_funcs intel_mode_funcs
= {
9390 .fb_create
= intel_user_framebuffer_create
,
9391 .output_poll_changed
= intel_fb_output_poll_changed
,
9394 /* Set up chip specific display functions */
9395 static void intel_init_display(struct drm_device
*dev
)
9397 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9399 if (HAS_PCH_SPLIT(dev
) || IS_G4X(dev
))
9400 dev_priv
->display
.find_dpll
= g4x_find_best_dpll
;
9401 else if (IS_VALLEYVIEW(dev
))
9402 dev_priv
->display
.find_dpll
= vlv_find_best_dpll
;
9403 else if (IS_PINEVIEW(dev
))
9404 dev_priv
->display
.find_dpll
= pnv_find_best_dpll
;
9406 dev_priv
->display
.find_dpll
= i9xx_find_best_dpll
;
9409 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
9410 dev_priv
->display
.crtc_mode_set
= haswell_crtc_mode_set
;
9411 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
9412 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
9413 dev_priv
->display
.off
= haswell_crtc_off
;
9414 dev_priv
->display
.update_plane
= ironlake_update_plane
;
9415 } else if (HAS_PCH_SPLIT(dev
)) {
9416 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
9417 dev_priv
->display
.get_clock
= ironlake_crtc_clock_get
;
9418 dev_priv
->display
.crtc_mode_set
= ironlake_crtc_mode_set
;
9419 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
9420 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
9421 dev_priv
->display
.off
= ironlake_crtc_off
;
9422 dev_priv
->display
.update_plane
= ironlake_update_plane
;
9423 } else if (IS_VALLEYVIEW(dev
)) {
9424 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
9425 dev_priv
->display
.get_clock
= i9xx_crtc_clock_get
;
9426 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
9427 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
9428 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
9429 dev_priv
->display
.off
= i9xx_crtc_off
;
9430 dev_priv
->display
.update_plane
= i9xx_update_plane
;
9432 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
9433 dev_priv
->display
.get_clock
= i9xx_crtc_clock_get
;
9434 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
9435 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
9436 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
9437 dev_priv
->display
.off
= i9xx_crtc_off
;
9438 dev_priv
->display
.update_plane
= i9xx_update_plane
;
9441 /* Returns the core display clock speed */
9442 if (IS_VALLEYVIEW(dev
))
9443 dev_priv
->display
.get_display_clock_speed
=
9444 valleyview_get_display_clock_speed
;
9445 else if (IS_I945G(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
9446 dev_priv
->display
.get_display_clock_speed
=
9447 i945_get_display_clock_speed
;
9448 else if (IS_I915G(dev
))
9449 dev_priv
->display
.get_display_clock_speed
=
9450 i915_get_display_clock_speed
;
9451 else if (IS_I945GM(dev
) || IS_845G(dev
) || IS_PINEVIEW_M(dev
))
9452 dev_priv
->display
.get_display_clock_speed
=
9453 i9xx_misc_get_display_clock_speed
;
9454 else if (IS_I915GM(dev
))
9455 dev_priv
->display
.get_display_clock_speed
=
9456 i915gm_get_display_clock_speed
;
9457 else if (IS_I865G(dev
))
9458 dev_priv
->display
.get_display_clock_speed
=
9459 i865_get_display_clock_speed
;
9460 else if (IS_I85X(dev
))
9461 dev_priv
->display
.get_display_clock_speed
=
9462 i855_get_display_clock_speed
;
9464 dev_priv
->display
.get_display_clock_speed
=
9465 i830_get_display_clock_speed
;
9467 if (HAS_PCH_SPLIT(dev
)) {
9469 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
9470 dev_priv
->display
.write_eld
= ironlake_write_eld
;
9471 } else if (IS_GEN6(dev
)) {
9472 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
9473 dev_priv
->display
.write_eld
= ironlake_write_eld
;
9474 } else if (IS_IVYBRIDGE(dev
)) {
9475 /* FIXME: detect B0+ stepping and use auto training */
9476 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
9477 dev_priv
->display
.write_eld
= ironlake_write_eld
;
9478 dev_priv
->display
.modeset_global_resources
=
9479 ivb_modeset_global_resources
;
9480 } else if (IS_HASWELL(dev
)) {
9481 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
9482 dev_priv
->display
.write_eld
= haswell_write_eld
;
9483 dev_priv
->display
.modeset_global_resources
=
9484 haswell_modeset_global_resources
;
9486 } else if (IS_G4X(dev
)) {
9487 dev_priv
->display
.write_eld
= g4x_write_eld
;
9490 /* Default just returns -ENODEV to indicate unsupported */
9491 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
9493 switch (INTEL_INFO(dev
)->gen
) {
9495 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
9499 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
9504 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
9508 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
9511 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
9517 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9518 * resume, or other times. This quirk makes sure that's the case for
9521 static void quirk_pipea_force(struct drm_device
*dev
)
9523 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9525 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
9526 DRM_INFO("applying pipe a force quirk\n");
9530 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9532 static void quirk_ssc_force_disable(struct drm_device
*dev
)
9534 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9535 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
9536 DRM_INFO("applying lvds SSC disable quirk\n");
9540 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9543 static void quirk_invert_brightness(struct drm_device
*dev
)
9545 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9546 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
9547 DRM_INFO("applying inverted panel brightness quirk\n");
9550 struct intel_quirk
{
9552 int subsystem_vendor
;
9553 int subsystem_device
;
9554 void (*hook
)(struct drm_device
*dev
);
9557 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9558 struct intel_dmi_quirk
{
9559 void (*hook
)(struct drm_device
*dev
);
9560 const struct dmi_system_id (*dmi_id_list
)[];
9563 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
9565 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
9569 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
9571 .dmi_id_list
= &(const struct dmi_system_id
[]) {
9573 .callback
= intel_dmi_reverse_brightness
,
9574 .ident
= "NCR Corporation",
9575 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
9576 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
9579 { } /* terminating entry */
9581 .hook
= quirk_invert_brightness
,
9585 static struct intel_quirk intel_quirks
[] = {
9586 /* HP Mini needs pipe A force quirk (LP: #322104) */
9587 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
9589 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9590 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
9592 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9593 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
9595 /* 830/845 need to leave pipe A & dpll A up */
9596 { 0x2562, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
9597 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
9599 /* Lenovo U160 cannot use SSC on LVDS */
9600 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
9602 /* Sony Vaio Y cannot use SSC on LVDS */
9603 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
9605 /* Acer Aspire 5734Z must invert backlight brightness */
9606 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
9608 /* Acer/eMachines G725 */
9609 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
9611 /* Acer/eMachines e725 */
9612 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
9614 /* Acer/Packard Bell NCL20 */
9615 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
9617 /* Acer Aspire 4736Z */
9618 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
9621 static void intel_init_quirks(struct drm_device
*dev
)
9623 struct pci_dev
*d
= dev
->pdev
;
9626 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
9627 struct intel_quirk
*q
= &intel_quirks
[i
];
9629 if (d
->device
== q
->device
&&
9630 (d
->subsystem_vendor
== q
->subsystem_vendor
||
9631 q
->subsystem_vendor
== PCI_ANY_ID
) &&
9632 (d
->subsystem_device
== q
->subsystem_device
||
9633 q
->subsystem_device
== PCI_ANY_ID
))
9636 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
9637 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
9638 intel_dmi_quirks
[i
].hook(dev
);
9642 /* Disable the VGA plane that we never use */
9643 static void i915_disable_vga(struct drm_device
*dev
)
9645 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9647 u32 vga_reg
= i915_vgacntrl_reg(dev
);
9649 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
9650 outb(SR01
, VGA_SR_INDEX
);
9651 sr1
= inb(VGA_SR_DATA
);
9652 outb(sr1
| 1<<5, VGA_SR_DATA
);
9653 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
9656 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
9657 POSTING_READ(vga_reg
);
9660 void intel_modeset_init_hw(struct drm_device
*dev
)
9662 intel_init_power_well(dev
);
9664 intel_prepare_ddi(dev
);
9666 intel_init_clock_gating(dev
);
9668 mutex_lock(&dev
->struct_mutex
);
9669 intel_enable_gt_powersave(dev
);
9670 mutex_unlock(&dev
->struct_mutex
);
9673 void intel_modeset_suspend_hw(struct drm_device
*dev
)
9675 intel_suspend_hw(dev
);
9678 void intel_modeset_init(struct drm_device
*dev
)
9680 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9683 drm_mode_config_init(dev
);
9685 dev
->mode_config
.min_width
= 0;
9686 dev
->mode_config
.min_height
= 0;
9688 dev
->mode_config
.preferred_depth
= 24;
9689 dev
->mode_config
.prefer_shadow
= 1;
9691 dev
->mode_config
.funcs
= &intel_mode_funcs
;
9693 intel_init_quirks(dev
);
9697 if (INTEL_INFO(dev
)->num_pipes
== 0)
9700 intel_init_display(dev
);
9703 dev
->mode_config
.max_width
= 2048;
9704 dev
->mode_config
.max_height
= 2048;
9705 } else if (IS_GEN3(dev
)) {
9706 dev
->mode_config
.max_width
= 4096;
9707 dev
->mode_config
.max_height
= 4096;
9709 dev
->mode_config
.max_width
= 8192;
9710 dev
->mode_config
.max_height
= 8192;
9712 dev
->mode_config
.fb_base
= dev_priv
->gtt
.mappable_base
;
9714 DRM_DEBUG_KMS("%d display pipe%s available.\n",
9715 INTEL_INFO(dev
)->num_pipes
,
9716 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
9719 intel_crtc_init(dev
, i
);
9720 for (j
= 0; j
< dev_priv
->num_plane
; j
++) {
9721 ret
= intel_plane_init(dev
, i
, j
);
9723 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9724 pipe_name(i
), sprite_name(i
, j
), ret
);
9728 intel_cpu_pll_init(dev
);
9729 intel_shared_dpll_init(dev
);
9731 /* Just disable it once at startup */
9732 i915_disable_vga(dev
);
9733 intel_setup_outputs(dev
);
9735 /* Just in case the BIOS is doing something questionable. */
9736 intel_disable_fbc(dev
);
9740 intel_connector_break_all_links(struct intel_connector
*connector
)
9742 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
9743 connector
->base
.encoder
= NULL
;
9744 connector
->encoder
->connectors_active
= false;
9745 connector
->encoder
->base
.crtc
= NULL
;
9748 static void intel_enable_pipe_a(struct drm_device
*dev
)
9750 struct intel_connector
*connector
;
9751 struct drm_connector
*crt
= NULL
;
9752 struct intel_load_detect_pipe load_detect_temp
;
9754 /* We can't just switch on the pipe A, we need to set things up with a
9755 * proper mode and output configuration. As a gross hack, enable pipe A
9756 * by enabling the load detect pipe once. */
9757 list_for_each_entry(connector
,
9758 &dev
->mode_config
.connector_list
,
9760 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
9761 crt
= &connector
->base
;
9769 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
))
9770 intel_release_load_detect_pipe(crt
, &load_detect_temp
);
9776 intel_check_plane_mapping(struct intel_crtc
*crtc
)
9778 struct drm_device
*dev
= crtc
->base
.dev
;
9779 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9782 if (INTEL_INFO(dev
)->num_pipes
== 1)
9785 reg
= DSPCNTR(!crtc
->plane
);
9786 val
= I915_READ(reg
);
9788 if ((val
& DISPLAY_PLANE_ENABLE
) &&
9789 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
9795 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
9797 struct drm_device
*dev
= crtc
->base
.dev
;
9798 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9801 /* Clear any frame start delays used for debugging left by the BIOS */
9802 reg
= PIPECONF(crtc
->config
.cpu_transcoder
);
9803 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
9805 /* We need to sanitize the plane -> pipe mapping first because this will
9806 * disable the crtc (and hence change the state) if it is wrong. Note
9807 * that gen4+ has a fixed plane -> pipe mapping. */
9808 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
9809 struct intel_connector
*connector
;
9812 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9813 crtc
->base
.base
.id
);
9815 /* Pipe has the wrong plane attached and the plane is active.
9816 * Temporarily change the plane mapping and disable everything
9818 plane
= crtc
->plane
;
9819 crtc
->plane
= !plane
;
9820 dev_priv
->display
.crtc_disable(&crtc
->base
);
9821 crtc
->plane
= plane
;
9823 /* ... and break all links. */
9824 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9826 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
9829 intel_connector_break_all_links(connector
);
9832 WARN_ON(crtc
->active
);
9833 crtc
->base
.enabled
= false;
9836 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
9837 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
9838 /* BIOS forgot to enable pipe A, this mostly happens after
9839 * resume. Force-enable the pipe to fix this, the update_dpms
9840 * call below we restore the pipe to the right state, but leave
9841 * the required bits on. */
9842 intel_enable_pipe_a(dev
);
9845 /* Adjust the state of the output pipe according to whether we
9846 * have active connectors/encoders. */
9847 intel_crtc_update_dpms(&crtc
->base
);
9849 if (crtc
->active
!= crtc
->base
.enabled
) {
9850 struct intel_encoder
*encoder
;
9852 /* This can happen either due to bugs in the get_hw_state
9853 * functions or because the pipe is force-enabled due to the
9855 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9857 crtc
->base
.enabled
? "enabled" : "disabled",
9858 crtc
->active
? "enabled" : "disabled");
9860 crtc
->base
.enabled
= crtc
->active
;
9862 /* Because we only establish the connector -> encoder ->
9863 * crtc links if something is active, this means the
9864 * crtc is now deactivated. Break the links. connector
9865 * -> encoder links are only establish when things are
9866 * actually up, hence no need to break them. */
9867 WARN_ON(crtc
->active
);
9869 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
9870 WARN_ON(encoder
->connectors_active
);
9871 encoder
->base
.crtc
= NULL
;
9876 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
9878 struct intel_connector
*connector
;
9879 struct drm_device
*dev
= encoder
->base
.dev
;
9881 /* We need to check both for a crtc link (meaning that the
9882 * encoder is active and trying to read from a pipe) and the
9883 * pipe itself being active. */
9884 bool has_active_crtc
= encoder
->base
.crtc
&&
9885 to_intel_crtc(encoder
->base
.crtc
)->active
;
9887 if (encoder
->connectors_active
&& !has_active_crtc
) {
9888 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9889 encoder
->base
.base
.id
,
9890 drm_get_encoder_name(&encoder
->base
));
9892 /* Connector is active, but has no active pipe. This is
9893 * fallout from our resume register restoring. Disable
9894 * the encoder manually again. */
9895 if (encoder
->base
.crtc
) {
9896 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9897 encoder
->base
.base
.id
,
9898 drm_get_encoder_name(&encoder
->base
));
9899 encoder
->disable(encoder
);
9902 /* Inconsistent output/port/pipe state happens presumably due to
9903 * a bug in one of the get_hw_state functions. Or someplace else
9904 * in our code, like the register restore mess on resume. Clamp
9905 * things to off as a safer default. */
9906 list_for_each_entry(connector
,
9907 &dev
->mode_config
.connector_list
,
9909 if (connector
->encoder
!= encoder
)
9912 intel_connector_break_all_links(connector
);
9915 /* Enabled encoders without active connectors will be fixed in
9916 * the crtc fixup. */
9919 void i915_redisable_vga(struct drm_device
*dev
)
9921 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9922 u32 vga_reg
= i915_vgacntrl_reg(dev
);
9924 if (I915_READ(vga_reg
) != VGA_DISP_DISABLE
) {
9925 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9926 i915_disable_vga(dev
);
9930 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
9932 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9934 struct intel_crtc
*crtc
;
9935 struct intel_encoder
*encoder
;
9936 struct intel_connector
*connector
;
9939 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
9941 memset(&crtc
->config
, 0, sizeof(crtc
->config
));
9943 crtc
->active
= dev_priv
->display
.get_pipe_config(crtc
,
9946 crtc
->base
.enabled
= crtc
->active
;
9948 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9950 crtc
->active
? "enabled" : "disabled");
9953 /* FIXME: Smash this into the new shared dpll infrastructure. */
9955 intel_ddi_setup_hw_pll_state(dev
);
9957 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
9958 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
9960 pll
->on
= pll
->get_hw_state(dev_priv
, pll
, &pll
->hw_state
);
9962 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
9964 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
9967 pll
->refcount
= pll
->active
;
9969 DRM_DEBUG_KMS("%s hw state readout: refcount %i\n",
9970 pll
->name
, pll
->refcount
);
9973 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9977 if (encoder
->get_hw_state(encoder
, &pipe
)) {
9978 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
9979 encoder
->base
.crtc
= &crtc
->base
;
9980 if (encoder
->get_config
)
9981 encoder
->get_config(encoder
, &crtc
->config
);
9983 encoder
->base
.crtc
= NULL
;
9986 encoder
->connectors_active
= false;
9987 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9988 encoder
->base
.base
.id
,
9989 drm_get_encoder_name(&encoder
->base
),
9990 encoder
->base
.crtc
? "enabled" : "disabled",
9994 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
9998 if (dev_priv
->display
.get_clock
)
9999 dev_priv
->display
.get_clock(crtc
,
10003 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10005 if (connector
->get_hw_state(connector
)) {
10006 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
10007 connector
->encoder
->connectors_active
= true;
10008 connector
->base
.encoder
= &connector
->encoder
->base
;
10010 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
10011 connector
->base
.encoder
= NULL
;
10013 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10014 connector
->base
.base
.id
,
10015 drm_get_connector_name(&connector
->base
),
10016 connector
->base
.encoder
? "enabled" : "disabled");
10020 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10021 * and i915 state tracking structures. */
10022 void intel_modeset_setup_hw_state(struct drm_device
*dev
,
10023 bool force_restore
)
10025 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10027 struct drm_plane
*plane
;
10028 struct intel_crtc
*crtc
;
10029 struct intel_encoder
*encoder
;
10031 intel_modeset_readout_hw_state(dev
);
10034 * Now that we have the config, copy it to each CRTC struct
10035 * Note that this could go away if we move to using crtc_config
10036 * checking everywhere.
10038 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
10040 if (crtc
->active
&& i915_fastboot
) {
10041 intel_crtc_mode_from_pipe_config(crtc
, &crtc
->config
);
10043 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10044 crtc
->base
.base
.id
);
10045 drm_mode_debug_printmodeline(&crtc
->base
.mode
);
10049 /* HW state is read out, now we need to sanitize this mess. */
10050 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
10052 intel_sanitize_encoder(encoder
);
10055 for_each_pipe(pipe
) {
10056 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
10057 intel_sanitize_crtc(crtc
);
10058 intel_dump_pipe_config(crtc
, &crtc
->config
, "[setup_hw_state]");
10061 if (force_restore
) {
10063 * We need to use raw interfaces for restoring state to avoid
10064 * checking (bogus) intermediate states.
10066 for_each_pipe(pipe
) {
10067 struct drm_crtc
*crtc
=
10068 dev_priv
->pipe_to_crtc_mapping
[pipe
];
10070 __intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
,
10073 list_for_each_entry(plane
, &dev
->mode_config
.plane_list
, head
)
10074 intel_plane_restore(plane
);
10076 i915_redisable_vga(dev
);
10078 intel_modeset_update_staged_output_state(dev
);
10081 intel_modeset_check_state(dev
);
10083 drm_mode_config_reset(dev
);
10086 void intel_modeset_gem_init(struct drm_device
*dev
)
10088 intel_modeset_init_hw(dev
);
10090 intel_setup_overlay(dev
);
10092 intel_modeset_setup_hw_state(dev
, false);
10095 void intel_modeset_cleanup(struct drm_device
*dev
)
10097 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10098 struct drm_crtc
*crtc
;
10099 struct intel_crtc
*intel_crtc
;
10102 * Interrupts and polling as the first thing to avoid creating havoc.
10103 * Too much stuff here (turning of rps, connectors, ...) would
10104 * experience fancy races otherwise.
10106 drm_irq_uninstall(dev
);
10107 cancel_work_sync(&dev_priv
->hotplug_work
);
10109 * Due to the hpd irq storm handling the hotplug work can re-arm the
10110 * poll handlers. Hence disable polling after hpd handling is shut down.
10112 drm_kms_helper_poll_fini(dev
);
10114 mutex_lock(&dev
->struct_mutex
);
10116 intel_unregister_dsm_handler();
10118 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
10119 /* Skip inactive CRTCs */
10123 intel_crtc
= to_intel_crtc(crtc
);
10124 intel_increase_pllclock(crtc
);
10127 intel_disable_fbc(dev
);
10129 intel_disable_gt_powersave(dev
);
10131 ironlake_teardown_rc6(dev
);
10133 mutex_unlock(&dev
->struct_mutex
);
10135 /* flush any delayed tasks or pending work */
10136 flush_scheduled_work();
10138 /* destroy backlight, if any, before the connectors */
10139 intel_panel_destroy_backlight(dev
);
10141 drm_mode_config_cleanup(dev
);
10143 intel_cleanup_overlay(dev
);
10147 * Return which encoder is currently attached for connector.
10149 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
10151 return &intel_attached_encoder(connector
)->base
;
10154 void intel_connector_attach_encoder(struct intel_connector
*connector
,
10155 struct intel_encoder
*encoder
)
10157 connector
->encoder
= encoder
;
10158 drm_mode_connector_attach_encoder(&connector
->base
,
10163 * set vga decode state - true == enable VGA decode
10165 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
10167 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10170 pci_read_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, &gmch_ctrl
);
10172 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
10174 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
10175 pci_write_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, gmch_ctrl
);
10179 struct intel_display_error_state
{
10181 u32 power_well_driver
;
10183 struct intel_cursor_error_state
{
10188 } cursor
[I915_MAX_PIPES
];
10190 struct intel_pipe_error_state
{
10191 enum transcoder cpu_transcoder
;
10201 } pipe
[I915_MAX_PIPES
];
10203 struct intel_plane_error_state
{
10211 } plane
[I915_MAX_PIPES
];
10214 struct intel_display_error_state
*
10215 intel_display_capture_error_state(struct drm_device
*dev
)
10217 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
10218 struct intel_display_error_state
*error
;
10219 enum transcoder cpu_transcoder
;
10222 error
= kmalloc(sizeof(*error
), GFP_ATOMIC
);
10226 if (HAS_POWER_WELL(dev
))
10227 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_DRIVER
);
10230 cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
, i
);
10231 error
->pipe
[i
].cpu_transcoder
= cpu_transcoder
;
10233 if (INTEL_INFO(dev
)->gen
<= 6 || IS_VALLEYVIEW(dev
)) {
10234 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
10235 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
10236 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
10238 error
->cursor
[i
].control
= I915_READ(CURCNTR_IVB(i
));
10239 error
->cursor
[i
].position
= I915_READ(CURPOS_IVB(i
));
10240 error
->cursor
[i
].base
= I915_READ(CURBASE_IVB(i
));
10243 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
10244 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
10245 if (INTEL_INFO(dev
)->gen
<= 3) {
10246 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
10247 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
10249 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
10250 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
10251 if (INTEL_INFO(dev
)->gen
>= 4) {
10252 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
10253 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
10256 error
->pipe
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
10257 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
10258 error
->pipe
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
10259 error
->pipe
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
10260 error
->pipe
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
10261 error
->pipe
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
10262 error
->pipe
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
10263 error
->pipe
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
10266 /* In the code above we read the registers without checking if the power
10267 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10268 * prevent the next I915_WRITE from detecting it and printing an error
10270 if (HAS_POWER_WELL(dev
))
10271 I915_WRITE_NOTRACE(FPGA_DBG
, FPGA_DBG_RM_NOCLAIM
);
10276 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10279 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
10280 struct drm_device
*dev
,
10281 struct intel_display_error_state
*error
)
10285 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
10286 if (HAS_POWER_WELL(dev
))
10287 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
10288 error
->power_well_driver
);
10290 err_printf(m
, "Pipe [%d]:\n", i
);
10291 err_printf(m
, " CPU transcoder: %c\n",
10292 transcoder_name(error
->pipe
[i
].cpu_transcoder
));
10293 err_printf(m
, " CONF: %08x\n", error
->pipe
[i
].conf
);
10294 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
10295 err_printf(m
, " HTOTAL: %08x\n", error
->pipe
[i
].htotal
);
10296 err_printf(m
, " HBLANK: %08x\n", error
->pipe
[i
].hblank
);
10297 err_printf(m
, " HSYNC: %08x\n", error
->pipe
[i
].hsync
);
10298 err_printf(m
, " VTOTAL: %08x\n", error
->pipe
[i
].vtotal
);
10299 err_printf(m
, " VBLANK: %08x\n", error
->pipe
[i
].vblank
);
10300 err_printf(m
, " VSYNC: %08x\n", error
->pipe
[i
].vsync
);
10302 err_printf(m
, "Plane [%d]:\n", i
);
10303 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
10304 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
10305 if (INTEL_INFO(dev
)->gen
<= 3) {
10306 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
10307 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
10309 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
10310 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
10311 if (INTEL_INFO(dev
)->gen
>= 4) {
10312 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
10313 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
10316 err_printf(m
, "Cursor [%d]:\n", i
);
10317 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
10318 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
10319 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);