2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
);
45 static void intel_increase_pllclock(struct drm_crtc
*crtc
);
46 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
57 #define INTEL_P2_NUM 2
58 typedef struct intel_limit intel_limit_t
;
60 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
65 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
68 intel_pch_rawclk(struct drm_device
*dev
)
70 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
72 WARN_ON(!HAS_PCH_SPLIT(dev
));
74 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
77 static inline u32
/* units of 100MHz */
78 intel_fdi_link_freq(struct drm_device
*dev
)
81 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
82 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
87 static const intel_limit_t intel_limits_i8xx_dvo
= {
88 .dot
= { .min
= 25000, .max
= 350000 },
89 .vco
= { .min
= 930000, .max
= 1400000 },
90 .n
= { .min
= 3, .max
= 16 },
91 .m
= { .min
= 96, .max
= 140 },
92 .m1
= { .min
= 18, .max
= 26 },
93 .m2
= { .min
= 6, .max
= 16 },
94 .p
= { .min
= 4, .max
= 128 },
95 .p1
= { .min
= 2, .max
= 33 },
96 .p2
= { .dot_limit
= 165000,
97 .p2_slow
= 4, .p2_fast
= 2 },
100 static const intel_limit_t intel_limits_i8xx_lvds
= {
101 .dot
= { .min
= 25000, .max
= 350000 },
102 .vco
= { .min
= 930000, .max
= 1400000 },
103 .n
= { .min
= 3, .max
= 16 },
104 .m
= { .min
= 96, .max
= 140 },
105 .m1
= { .min
= 18, .max
= 26 },
106 .m2
= { .min
= 6, .max
= 16 },
107 .p
= { .min
= 4, .max
= 128 },
108 .p1
= { .min
= 1, .max
= 6 },
109 .p2
= { .dot_limit
= 165000,
110 .p2_slow
= 14, .p2_fast
= 7 },
113 static const intel_limit_t intel_limits_i9xx_sdvo
= {
114 .dot
= { .min
= 20000, .max
= 400000 },
115 .vco
= { .min
= 1400000, .max
= 2800000 },
116 .n
= { .min
= 1, .max
= 6 },
117 .m
= { .min
= 70, .max
= 120 },
118 .m1
= { .min
= 8, .max
= 18 },
119 .m2
= { .min
= 3, .max
= 7 },
120 .p
= { .min
= 5, .max
= 80 },
121 .p1
= { .min
= 1, .max
= 8 },
122 .p2
= { .dot_limit
= 200000,
123 .p2_slow
= 10, .p2_fast
= 5 },
126 static const intel_limit_t intel_limits_i9xx_lvds
= {
127 .dot
= { .min
= 20000, .max
= 400000 },
128 .vco
= { .min
= 1400000, .max
= 2800000 },
129 .n
= { .min
= 1, .max
= 6 },
130 .m
= { .min
= 70, .max
= 120 },
131 .m1
= { .min
= 8, .max
= 18 },
132 .m2
= { .min
= 3, .max
= 7 },
133 .p
= { .min
= 7, .max
= 98 },
134 .p1
= { .min
= 1, .max
= 8 },
135 .p2
= { .dot_limit
= 112000,
136 .p2_slow
= 14, .p2_fast
= 7 },
140 static const intel_limit_t intel_limits_g4x_sdvo
= {
141 .dot
= { .min
= 25000, .max
= 270000 },
142 .vco
= { .min
= 1750000, .max
= 3500000},
143 .n
= { .min
= 1, .max
= 4 },
144 .m
= { .min
= 104, .max
= 138 },
145 .m1
= { .min
= 17, .max
= 23 },
146 .m2
= { .min
= 5, .max
= 11 },
147 .p
= { .min
= 10, .max
= 30 },
148 .p1
= { .min
= 1, .max
= 3},
149 .p2
= { .dot_limit
= 270000,
155 static const intel_limit_t intel_limits_g4x_hdmi
= {
156 .dot
= { .min
= 22000, .max
= 400000 },
157 .vco
= { .min
= 1750000, .max
= 3500000},
158 .n
= { .min
= 1, .max
= 4 },
159 .m
= { .min
= 104, .max
= 138 },
160 .m1
= { .min
= 16, .max
= 23 },
161 .m2
= { .min
= 5, .max
= 11 },
162 .p
= { .min
= 5, .max
= 80 },
163 .p1
= { .min
= 1, .max
= 8},
164 .p2
= { .dot_limit
= 165000,
165 .p2_slow
= 10, .p2_fast
= 5 },
168 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
169 .dot
= { .min
= 20000, .max
= 115000 },
170 .vco
= { .min
= 1750000, .max
= 3500000 },
171 .n
= { .min
= 1, .max
= 3 },
172 .m
= { .min
= 104, .max
= 138 },
173 .m1
= { .min
= 17, .max
= 23 },
174 .m2
= { .min
= 5, .max
= 11 },
175 .p
= { .min
= 28, .max
= 112 },
176 .p1
= { .min
= 2, .max
= 8 },
177 .p2
= { .dot_limit
= 0,
178 .p2_slow
= 14, .p2_fast
= 14
182 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
183 .dot
= { .min
= 80000, .max
= 224000 },
184 .vco
= { .min
= 1750000, .max
= 3500000 },
185 .n
= { .min
= 1, .max
= 3 },
186 .m
= { .min
= 104, .max
= 138 },
187 .m1
= { .min
= 17, .max
= 23 },
188 .m2
= { .min
= 5, .max
= 11 },
189 .p
= { .min
= 14, .max
= 42 },
190 .p1
= { .min
= 2, .max
= 6 },
191 .p2
= { .dot_limit
= 0,
192 .p2_slow
= 7, .p2_fast
= 7
196 static const intel_limit_t intel_limits_pineview_sdvo
= {
197 .dot
= { .min
= 20000, .max
= 400000},
198 .vco
= { .min
= 1700000, .max
= 3500000 },
199 /* Pineview's Ncounter is a ring counter */
200 .n
= { .min
= 3, .max
= 6 },
201 .m
= { .min
= 2, .max
= 256 },
202 /* Pineview only has one combined m divider, which we treat as m2. */
203 .m1
= { .min
= 0, .max
= 0 },
204 .m2
= { .min
= 0, .max
= 254 },
205 .p
= { .min
= 5, .max
= 80 },
206 .p1
= { .min
= 1, .max
= 8 },
207 .p2
= { .dot_limit
= 200000,
208 .p2_slow
= 10, .p2_fast
= 5 },
211 static const intel_limit_t intel_limits_pineview_lvds
= {
212 .dot
= { .min
= 20000, .max
= 400000 },
213 .vco
= { .min
= 1700000, .max
= 3500000 },
214 .n
= { .min
= 3, .max
= 6 },
215 .m
= { .min
= 2, .max
= 256 },
216 .m1
= { .min
= 0, .max
= 0 },
217 .m2
= { .min
= 0, .max
= 254 },
218 .p
= { .min
= 7, .max
= 112 },
219 .p1
= { .min
= 1, .max
= 8 },
220 .p2
= { .dot_limit
= 112000,
221 .p2_slow
= 14, .p2_fast
= 14 },
224 /* Ironlake / Sandybridge
226 * We calculate clock using (register_value + 2) for N/M1/M2, so here
227 * the range value for them is (actual_value - 2).
229 static const intel_limit_t intel_limits_ironlake_dac
= {
230 .dot
= { .min
= 25000, .max
= 350000 },
231 .vco
= { .min
= 1760000, .max
= 3510000 },
232 .n
= { .min
= 1, .max
= 5 },
233 .m
= { .min
= 79, .max
= 127 },
234 .m1
= { .min
= 12, .max
= 22 },
235 .m2
= { .min
= 5, .max
= 9 },
236 .p
= { .min
= 5, .max
= 80 },
237 .p1
= { .min
= 1, .max
= 8 },
238 .p2
= { .dot_limit
= 225000,
239 .p2_slow
= 10, .p2_fast
= 5 },
242 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
243 .dot
= { .min
= 25000, .max
= 350000 },
244 .vco
= { .min
= 1760000, .max
= 3510000 },
245 .n
= { .min
= 1, .max
= 3 },
246 .m
= { .min
= 79, .max
= 118 },
247 .m1
= { .min
= 12, .max
= 22 },
248 .m2
= { .min
= 5, .max
= 9 },
249 .p
= { .min
= 28, .max
= 112 },
250 .p1
= { .min
= 2, .max
= 8 },
251 .p2
= { .dot_limit
= 225000,
252 .p2_slow
= 14, .p2_fast
= 14 },
255 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
256 .dot
= { .min
= 25000, .max
= 350000 },
257 .vco
= { .min
= 1760000, .max
= 3510000 },
258 .n
= { .min
= 1, .max
= 3 },
259 .m
= { .min
= 79, .max
= 127 },
260 .m1
= { .min
= 12, .max
= 22 },
261 .m2
= { .min
= 5, .max
= 9 },
262 .p
= { .min
= 14, .max
= 56 },
263 .p1
= { .min
= 2, .max
= 8 },
264 .p2
= { .dot_limit
= 225000,
265 .p2_slow
= 7, .p2_fast
= 7 },
268 /* LVDS 100mhz refclk limits. */
269 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
270 .dot
= { .min
= 25000, .max
= 350000 },
271 .vco
= { .min
= 1760000, .max
= 3510000 },
272 .n
= { .min
= 1, .max
= 2 },
273 .m
= { .min
= 79, .max
= 126 },
274 .m1
= { .min
= 12, .max
= 22 },
275 .m2
= { .min
= 5, .max
= 9 },
276 .p
= { .min
= 28, .max
= 112 },
277 .p1
= { .min
= 2, .max
= 8 },
278 .p2
= { .dot_limit
= 225000,
279 .p2_slow
= 14, .p2_fast
= 14 },
282 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
283 .dot
= { .min
= 25000, .max
= 350000 },
284 .vco
= { .min
= 1760000, .max
= 3510000 },
285 .n
= { .min
= 1, .max
= 3 },
286 .m
= { .min
= 79, .max
= 126 },
287 .m1
= { .min
= 12, .max
= 22 },
288 .m2
= { .min
= 5, .max
= 9 },
289 .p
= { .min
= 14, .max
= 42 },
290 .p1
= { .min
= 2, .max
= 6 },
291 .p2
= { .dot_limit
= 225000,
292 .p2_slow
= 7, .p2_fast
= 7 },
295 static const intel_limit_t intel_limits_vlv_dac
= {
296 .dot
= { .min
= 25000, .max
= 270000 },
297 .vco
= { .min
= 4000000, .max
= 6000000 },
298 .n
= { .min
= 1, .max
= 7 },
299 .m
= { .min
= 22, .max
= 450 }, /* guess */
300 .m1
= { .min
= 2, .max
= 3 },
301 .m2
= { .min
= 11, .max
= 156 },
302 .p
= { .min
= 10, .max
= 30 },
303 .p1
= { .min
= 1, .max
= 3 },
304 .p2
= { .dot_limit
= 270000,
305 .p2_slow
= 2, .p2_fast
= 20 },
308 static const intel_limit_t intel_limits_vlv_hdmi
= {
309 .dot
= { .min
= 25000, .max
= 270000 },
310 .vco
= { .min
= 4000000, .max
= 6000000 },
311 .n
= { .min
= 1, .max
= 7 },
312 .m
= { .min
= 60, .max
= 300 }, /* guess */
313 .m1
= { .min
= 2, .max
= 3 },
314 .m2
= { .min
= 11, .max
= 156 },
315 .p
= { .min
= 10, .max
= 30 },
316 .p1
= { .min
= 2, .max
= 3 },
317 .p2
= { .dot_limit
= 270000,
318 .p2_slow
= 2, .p2_fast
= 20 },
321 static const intel_limit_t intel_limits_vlv_dp
= {
322 .dot
= { .min
= 25000, .max
= 270000 },
323 .vco
= { .min
= 4000000, .max
= 6000000 },
324 .n
= { .min
= 1, .max
= 7 },
325 .m
= { .min
= 22, .max
= 450 },
326 .m1
= { .min
= 2, .max
= 3 },
327 .m2
= { .min
= 11, .max
= 156 },
328 .p
= { .min
= 10, .max
= 30 },
329 .p1
= { .min
= 1, .max
= 3 },
330 .p2
= { .dot_limit
= 270000,
331 .p2_slow
= 2, .p2_fast
= 20 },
334 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
,
337 struct drm_device
*dev
= crtc
->dev
;
338 const intel_limit_t
*limit
;
340 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
341 if (intel_is_dual_link_lvds(dev
)) {
342 if (refclk
== 100000)
343 limit
= &intel_limits_ironlake_dual_lvds_100m
;
345 limit
= &intel_limits_ironlake_dual_lvds
;
347 if (refclk
== 100000)
348 limit
= &intel_limits_ironlake_single_lvds_100m
;
350 limit
= &intel_limits_ironlake_single_lvds
;
353 limit
= &intel_limits_ironlake_dac
;
358 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
360 struct drm_device
*dev
= crtc
->dev
;
361 const intel_limit_t
*limit
;
363 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
364 if (intel_is_dual_link_lvds(dev
))
365 limit
= &intel_limits_g4x_dual_channel_lvds
;
367 limit
= &intel_limits_g4x_single_channel_lvds
;
368 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
369 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
370 limit
= &intel_limits_g4x_hdmi
;
371 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
372 limit
= &intel_limits_g4x_sdvo
;
373 } else /* The option is for other outputs */
374 limit
= &intel_limits_i9xx_sdvo
;
379 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
, int refclk
)
381 struct drm_device
*dev
= crtc
->dev
;
382 const intel_limit_t
*limit
;
384 if (HAS_PCH_SPLIT(dev
))
385 limit
= intel_ironlake_limit(crtc
, refclk
);
386 else if (IS_G4X(dev
)) {
387 limit
= intel_g4x_limit(crtc
);
388 } else if (IS_PINEVIEW(dev
)) {
389 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
390 limit
= &intel_limits_pineview_lvds
;
392 limit
= &intel_limits_pineview_sdvo
;
393 } else if (IS_VALLEYVIEW(dev
)) {
394 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
))
395 limit
= &intel_limits_vlv_dac
;
396 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
397 limit
= &intel_limits_vlv_hdmi
;
399 limit
= &intel_limits_vlv_dp
;
400 } else if (!IS_GEN2(dev
)) {
401 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
402 limit
= &intel_limits_i9xx_lvds
;
404 limit
= &intel_limits_i9xx_sdvo
;
406 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
407 limit
= &intel_limits_i8xx_lvds
;
409 limit
= &intel_limits_i8xx_dvo
;
414 /* m1 is reserved as 0 in Pineview, n is a ring counter */
415 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
417 clock
->m
= clock
->m2
+ 2;
418 clock
->p
= clock
->p1
* clock
->p2
;
419 clock
->vco
= refclk
* clock
->m
/ clock
->n
;
420 clock
->dot
= clock
->vco
/ clock
->p
;
423 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
425 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
428 static void i9xx_clock(int refclk
, intel_clock_t
*clock
)
430 clock
->m
= i9xx_dpll_compute_m(clock
);
431 clock
->p
= clock
->p1
* clock
->p2
;
432 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
433 clock
->dot
= clock
->vco
/ clock
->p
;
437 * Returns whether any output on the specified pipe is of the specified type
439 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
441 struct drm_device
*dev
= crtc
->dev
;
442 struct intel_encoder
*encoder
;
444 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
445 if (encoder
->type
== type
)
451 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
453 * Returns whether the given set of divisors are valid for a given refclk with
454 * the given connectors.
457 static bool intel_PLL_is_valid(struct drm_device
*dev
,
458 const intel_limit_t
*limit
,
459 const intel_clock_t
*clock
)
461 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
462 INTELPllInvalid("p1 out of range\n");
463 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
464 INTELPllInvalid("p out of range\n");
465 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
466 INTELPllInvalid("m2 out of range\n");
467 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
468 INTELPllInvalid("m1 out of range\n");
469 if (clock
->m1
<= clock
->m2
&& !IS_PINEVIEW(dev
))
470 INTELPllInvalid("m1 <= m2\n");
471 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
472 INTELPllInvalid("m out of range\n");
473 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
474 INTELPllInvalid("n out of range\n");
475 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
476 INTELPllInvalid("vco out of range\n");
477 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
478 * connector, etc., rather than just a single range.
480 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
481 INTELPllInvalid("dot out of range\n");
487 i9xx_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
488 int target
, int refclk
, intel_clock_t
*match_clock
,
489 intel_clock_t
*best_clock
)
491 struct drm_device
*dev
= crtc
->dev
;
495 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
497 * For LVDS just rely on its current settings for dual-channel.
498 * We haven't figured out how to reliably set up different
499 * single/dual channel state, if we even can.
501 if (intel_is_dual_link_lvds(dev
))
502 clock
.p2
= limit
->p2
.p2_fast
;
504 clock
.p2
= limit
->p2
.p2_slow
;
506 if (target
< limit
->p2
.dot_limit
)
507 clock
.p2
= limit
->p2
.p2_slow
;
509 clock
.p2
= limit
->p2
.p2_fast
;
512 memset(best_clock
, 0, sizeof(*best_clock
));
514 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
516 for (clock
.m2
= limit
->m2
.min
;
517 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
518 if (clock
.m2
>= clock
.m1
)
520 for (clock
.n
= limit
->n
.min
;
521 clock
.n
<= limit
->n
.max
; clock
.n
++) {
522 for (clock
.p1
= limit
->p1
.min
;
523 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
526 i9xx_clock(refclk
, &clock
);
527 if (!intel_PLL_is_valid(dev
, limit
,
531 clock
.p
!= match_clock
->p
)
534 this_err
= abs(clock
.dot
- target
);
535 if (this_err
< err
) {
544 return (err
!= target
);
548 pnv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
549 int target
, int refclk
, intel_clock_t
*match_clock
,
550 intel_clock_t
*best_clock
)
552 struct drm_device
*dev
= crtc
->dev
;
556 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
558 * For LVDS just rely on its current settings for dual-channel.
559 * We haven't figured out how to reliably set up different
560 * single/dual channel state, if we even can.
562 if (intel_is_dual_link_lvds(dev
))
563 clock
.p2
= limit
->p2
.p2_fast
;
565 clock
.p2
= limit
->p2
.p2_slow
;
567 if (target
< limit
->p2
.dot_limit
)
568 clock
.p2
= limit
->p2
.p2_slow
;
570 clock
.p2
= limit
->p2
.p2_fast
;
573 memset(best_clock
, 0, sizeof(*best_clock
));
575 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
577 for (clock
.m2
= limit
->m2
.min
;
578 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
579 for (clock
.n
= limit
->n
.min
;
580 clock
.n
<= limit
->n
.max
; clock
.n
++) {
581 for (clock
.p1
= limit
->p1
.min
;
582 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
585 pineview_clock(refclk
, &clock
);
586 if (!intel_PLL_is_valid(dev
, limit
,
590 clock
.p
!= match_clock
->p
)
593 this_err
= abs(clock
.dot
- target
);
594 if (this_err
< err
) {
603 return (err
!= target
);
607 g4x_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
608 int target
, int refclk
, intel_clock_t
*match_clock
,
609 intel_clock_t
*best_clock
)
611 struct drm_device
*dev
= crtc
->dev
;
615 /* approximately equals target * 0.00585 */
616 int err_most
= (target
>> 8) + (target
>> 9);
619 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
620 if (intel_is_dual_link_lvds(dev
))
621 clock
.p2
= limit
->p2
.p2_fast
;
623 clock
.p2
= limit
->p2
.p2_slow
;
625 if (target
< limit
->p2
.dot_limit
)
626 clock
.p2
= limit
->p2
.p2_slow
;
628 clock
.p2
= limit
->p2
.p2_fast
;
631 memset(best_clock
, 0, sizeof(*best_clock
));
632 max_n
= limit
->n
.max
;
633 /* based on hardware requirement, prefer smaller n to precision */
634 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
635 /* based on hardware requirement, prefere larger m1,m2 */
636 for (clock
.m1
= limit
->m1
.max
;
637 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
638 for (clock
.m2
= limit
->m2
.max
;
639 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
640 for (clock
.p1
= limit
->p1
.max
;
641 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
644 i9xx_clock(refclk
, &clock
);
645 if (!intel_PLL_is_valid(dev
, limit
,
649 this_err
= abs(clock
.dot
- target
);
650 if (this_err
< err_most
) {
664 vlv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
665 int target
, int refclk
, intel_clock_t
*match_clock
,
666 intel_clock_t
*best_clock
)
668 u32 p1
, p2
, m1
, m2
, vco
, bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
670 u32 updrate
, minupdate
, fracbits
, p
;
671 unsigned long bestppm
, ppm
, absppm
;
675 dotclk
= target
* 1000;
678 fastclk
= dotclk
/ (2*100);
682 n
= p
= p1
= p2
= m
= m1
= m2
= vco
= bestn
= 0;
683 bestm1
= bestm2
= bestp1
= bestp2
= 0;
685 /* based on hardware requirement, prefer smaller n to precision */
686 for (n
= limit
->n
.min
; n
<= ((refclk
) / minupdate
); n
++) {
687 updrate
= refclk
/ n
;
688 for (p1
= limit
->p1
.max
; p1
> limit
->p1
.min
; p1
--) {
689 for (p2
= limit
->p2
.p2_fast
+1; p2
> 0; p2
--) {
693 /* based on hardware requirement, prefer bigger m1,m2 values */
694 for (m1
= limit
->m1
.min
; m1
<= limit
->m1
.max
; m1
++) {
695 m2
= (((2*(fastclk
* p
* n
/ m1
)) +
696 refclk
) / (2*refclk
));
699 if (vco
>= limit
->vco
.min
&& vco
< limit
->vco
.max
) {
700 ppm
= 1000000 * ((vco
/ p
) - fastclk
) / fastclk
;
701 absppm
= (ppm
> 0) ? ppm
: (-ppm
);
702 if (absppm
< 100 && ((p1
* p2
) > (bestp1
* bestp2
))) {
706 if (absppm
< bestppm
- 10) {
723 best_clock
->n
= bestn
;
724 best_clock
->m1
= bestm1
;
725 best_clock
->m2
= bestm2
;
726 best_clock
->p1
= bestp1
;
727 best_clock
->p2
= bestp2
;
732 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
735 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
736 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
738 return intel_crtc
->config
.cpu_transcoder
;
741 static void ironlake_wait_for_vblank(struct drm_device
*dev
, int pipe
)
743 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
744 u32 frame
, frame_reg
= PIPEFRAME(pipe
);
746 frame
= I915_READ(frame_reg
);
748 if (wait_for(I915_READ_NOTRACE(frame_reg
) != frame
, 50))
749 DRM_DEBUG_KMS("vblank wait timed out\n");
753 * intel_wait_for_vblank - wait for vblank on a given pipe
755 * @pipe: pipe to wait for
757 * Wait for vblank to occur on a given pipe. Needed for various bits of
760 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
762 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
763 int pipestat_reg
= PIPESTAT(pipe
);
765 if (INTEL_INFO(dev
)->gen
>= 5) {
766 ironlake_wait_for_vblank(dev
, pipe
);
770 /* Clear existing vblank status. Note this will clear any other
771 * sticky status fields as well.
773 * This races with i915_driver_irq_handler() with the result
774 * that either function could miss a vblank event. Here it is not
775 * fatal, as we will either wait upon the next vblank interrupt or
776 * timeout. Generally speaking intel_wait_for_vblank() is only
777 * called during modeset at which time the GPU should be idle and
778 * should *not* be performing page flips and thus not waiting on
780 * Currently, the result of us stealing a vblank from the irq
781 * handler is that a single frame will be skipped during swapbuffers.
783 I915_WRITE(pipestat_reg
,
784 I915_READ(pipestat_reg
) | PIPE_VBLANK_INTERRUPT_STATUS
);
786 /* Wait for vblank interrupt bit to set */
787 if (wait_for(I915_READ(pipestat_reg
) &
788 PIPE_VBLANK_INTERRUPT_STATUS
,
790 DRM_DEBUG_KMS("vblank wait timed out\n");
794 * intel_wait_for_pipe_off - wait for pipe to turn off
796 * @pipe: pipe to wait for
798 * After disabling a pipe, we can't wait for vblank in the usual way,
799 * spinning on the vblank interrupt status bit, since we won't actually
800 * see an interrupt when the pipe is disabled.
803 * wait for the pipe register state bit to turn off
806 * wait for the display line value to settle (it usually
807 * ends up stopping at the start of the next frame).
810 void intel_wait_for_pipe_off(struct drm_device
*dev
, int pipe
)
812 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
813 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
816 if (INTEL_INFO(dev
)->gen
>= 4) {
817 int reg
= PIPECONF(cpu_transcoder
);
819 /* Wait for the Pipe State to go off */
820 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
822 WARN(1, "pipe_off wait timed out\n");
824 u32 last_line
, line_mask
;
825 int reg
= PIPEDSL(pipe
);
826 unsigned long timeout
= jiffies
+ msecs_to_jiffies(100);
829 line_mask
= DSL_LINEMASK_GEN2
;
831 line_mask
= DSL_LINEMASK_GEN3
;
833 /* Wait for the display line to settle */
835 last_line
= I915_READ(reg
) & line_mask
;
837 } while (((I915_READ(reg
) & line_mask
) != last_line
) &&
838 time_after(timeout
, jiffies
));
839 if (time_after(jiffies
, timeout
))
840 WARN(1, "pipe_off wait timed out\n");
845 * ibx_digital_port_connected - is the specified port connected?
846 * @dev_priv: i915 private structure
847 * @port: the port to test
849 * Returns true if @port is connected, false otherwise.
851 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
852 struct intel_digital_port
*port
)
856 if (HAS_PCH_IBX(dev_priv
->dev
)) {
859 bit
= SDE_PORTB_HOTPLUG
;
862 bit
= SDE_PORTC_HOTPLUG
;
865 bit
= SDE_PORTD_HOTPLUG
;
873 bit
= SDE_PORTB_HOTPLUG_CPT
;
876 bit
= SDE_PORTC_HOTPLUG_CPT
;
879 bit
= SDE_PORTD_HOTPLUG_CPT
;
886 return I915_READ(SDEISR
) & bit
;
889 static const char *state_string(bool enabled
)
891 return enabled
? "on" : "off";
894 /* Only for pre-ILK configs */
895 static void assert_pll(struct drm_i915_private
*dev_priv
,
896 enum pipe pipe
, bool state
)
903 val
= I915_READ(reg
);
904 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
905 WARN(cur_state
!= state
,
906 "PLL state assertion failure (expected %s, current %s)\n",
907 state_string(state
), state_string(cur_state
));
909 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
910 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
912 static struct intel_shared_dpll
*
913 intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
)
915 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
917 if (crtc
->config
.shared_dpll
< 0)
920 return &dev_priv
->shared_dplls
[crtc
->config
.shared_dpll
];
924 static void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
925 struct intel_shared_dpll
*pll
,
931 if (HAS_PCH_LPT(dev_priv
->dev
)) {
932 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
937 "asserting DPLL %s with no DPLL\n", state_string(state
)))
940 val
= I915_READ(PCH_DPLL(pll
->id
));
941 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
942 WARN(cur_state
!= state
,
943 "%s assertion failure (expected %s, current %s), val=%08x\n",
944 pll
->name
, state_string(state
), state_string(cur_state
), val
);
946 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
947 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
949 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
950 enum pipe pipe
, bool state
)
955 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
958 if (HAS_DDI(dev_priv
->dev
)) {
959 /* DDI does not have a specific FDI_TX register */
960 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
961 val
= I915_READ(reg
);
962 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
964 reg
= FDI_TX_CTL(pipe
);
965 val
= I915_READ(reg
);
966 cur_state
= !!(val
& FDI_TX_ENABLE
);
968 WARN(cur_state
!= state
,
969 "FDI TX state assertion failure (expected %s, current %s)\n",
970 state_string(state
), state_string(cur_state
));
972 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
973 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
975 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
976 enum pipe pipe
, bool state
)
982 reg
= FDI_RX_CTL(pipe
);
983 val
= I915_READ(reg
);
984 cur_state
= !!(val
& FDI_RX_ENABLE
);
985 WARN(cur_state
!= state
,
986 "FDI RX state assertion failure (expected %s, current %s)\n",
987 state_string(state
), state_string(cur_state
));
989 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
990 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
992 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
998 /* ILK FDI PLL is always enabled */
999 if (dev_priv
->info
->gen
== 5)
1002 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1003 if (HAS_DDI(dev_priv
->dev
))
1006 reg
= FDI_TX_CTL(pipe
);
1007 val
= I915_READ(reg
);
1008 WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1011 static void assert_fdi_rx_pll_enabled(struct drm_i915_private
*dev_priv
,
1017 reg
= FDI_RX_CTL(pipe
);
1018 val
= I915_READ(reg
);
1019 WARN(!(val
& FDI_RX_PLL_ENABLE
), "FDI RX PLL assertion failure, should be active but is disabled\n");
1022 static void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1025 int pp_reg
, lvds_reg
;
1027 enum pipe panel_pipe
= PIPE_A
;
1030 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
1031 pp_reg
= PCH_PP_CONTROL
;
1032 lvds_reg
= PCH_LVDS
;
1034 pp_reg
= PP_CONTROL
;
1038 val
= I915_READ(pp_reg
);
1039 if (!(val
& PANEL_POWER_ON
) ||
1040 ((val
& PANEL_UNLOCK_REGS
) == PANEL_UNLOCK_REGS
))
1043 if (I915_READ(lvds_reg
) & LVDS_PIPEB_SELECT
)
1044 panel_pipe
= PIPE_B
;
1046 WARN(panel_pipe
== pipe
&& locked
,
1047 "panel assertion failure, pipe %c regs locked\n",
1051 void assert_pipe(struct drm_i915_private
*dev_priv
,
1052 enum pipe pipe
, bool state
)
1057 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1060 /* if we need the pipe A quirk it must be always on */
1061 if (pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
1064 if (!intel_display_power_enabled(dev_priv
->dev
,
1065 POWER_DOMAIN_TRANSCODER(cpu_transcoder
))) {
1068 reg
= PIPECONF(cpu_transcoder
);
1069 val
= I915_READ(reg
);
1070 cur_state
= !!(val
& PIPECONF_ENABLE
);
1073 WARN(cur_state
!= state
,
1074 "pipe %c assertion failure (expected %s, current %s)\n",
1075 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1078 static void assert_plane(struct drm_i915_private
*dev_priv
,
1079 enum plane plane
, bool state
)
1085 reg
= DSPCNTR(plane
);
1086 val
= I915_READ(reg
);
1087 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1088 WARN(cur_state
!= state
,
1089 "plane %c assertion failure (expected %s, current %s)\n",
1090 plane_name(plane
), state_string(state
), state_string(cur_state
));
1093 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1094 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1096 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1099 struct drm_device
*dev
= dev_priv
->dev
;
1104 /* Primary planes are fixed to pipes on gen4+ */
1105 if (INTEL_INFO(dev
)->gen
>= 4) {
1106 reg
= DSPCNTR(pipe
);
1107 val
= I915_READ(reg
);
1108 WARN((val
& DISPLAY_PLANE_ENABLE
),
1109 "plane %c assertion failure, should be disabled but not\n",
1114 /* Need to check both planes against the pipe */
1115 for (i
= 0; i
< INTEL_INFO(dev
)->num_pipes
; i
++) {
1117 val
= I915_READ(reg
);
1118 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1119 DISPPLANE_SEL_PIPE_SHIFT
;
1120 WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1121 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1122 plane_name(i
), pipe_name(pipe
));
1126 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1129 struct drm_device
*dev
= dev_priv
->dev
;
1133 if (IS_VALLEYVIEW(dev
)) {
1134 for (i
= 0; i
< dev_priv
->num_plane
; i
++) {
1135 reg
= SPCNTR(pipe
, i
);
1136 val
= I915_READ(reg
);
1137 WARN((val
& SP_ENABLE
),
1138 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1139 sprite_name(pipe
, i
), pipe_name(pipe
));
1141 } else if (INTEL_INFO(dev
)->gen
>= 7) {
1143 val
= I915_READ(reg
);
1144 WARN((val
& SPRITE_ENABLE
),
1145 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1146 plane_name(pipe
), pipe_name(pipe
));
1147 } else if (INTEL_INFO(dev
)->gen
>= 5) {
1148 reg
= DVSCNTR(pipe
);
1149 val
= I915_READ(reg
);
1150 WARN((val
& DVS_ENABLE
),
1151 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1152 plane_name(pipe
), pipe_name(pipe
));
1156 static void assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1161 if (HAS_PCH_LPT(dev_priv
->dev
)) {
1162 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1166 val
= I915_READ(PCH_DREF_CONTROL
);
1167 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1168 DREF_SUPERSPREAD_SOURCE_MASK
));
1169 WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1172 static void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1179 reg
= PCH_TRANSCONF(pipe
);
1180 val
= I915_READ(reg
);
1181 enabled
= !!(val
& TRANS_ENABLE
);
1183 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1187 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1188 enum pipe pipe
, u32 port_sel
, u32 val
)
1190 if ((val
& DP_PORT_EN
) == 0)
1193 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1194 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1195 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1196 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1199 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1205 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1206 enum pipe pipe
, u32 val
)
1208 if ((val
& SDVO_ENABLE
) == 0)
1211 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1212 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1215 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1221 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1222 enum pipe pipe
, u32 val
)
1224 if ((val
& LVDS_PORT_EN
) == 0)
1227 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1228 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1231 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1237 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1238 enum pipe pipe
, u32 val
)
1240 if ((val
& ADPA_DAC_ENABLE
) == 0)
1242 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1243 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1246 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1252 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1253 enum pipe pipe
, int reg
, u32 port_sel
)
1255 u32 val
= I915_READ(reg
);
1256 WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1257 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1258 reg
, pipe_name(pipe
));
1260 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1261 && (val
& DP_PIPEB_SELECT
),
1262 "IBX PCH dp port still using transcoder B\n");
1265 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1266 enum pipe pipe
, int reg
)
1268 u32 val
= I915_READ(reg
);
1269 WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1270 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1271 reg
, pipe_name(pipe
));
1273 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_ENABLE
) == 0
1274 && (val
& SDVO_PIPE_B_SELECT
),
1275 "IBX PCH hdmi port still using transcoder B\n");
1278 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1284 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1285 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1286 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1289 val
= I915_READ(reg
);
1290 WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1291 "PCH VGA enabled on transcoder %c, should be disabled\n",
1295 val
= I915_READ(reg
);
1296 WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1297 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1300 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1301 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1302 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1306 * intel_enable_pll - enable a PLL
1307 * @dev_priv: i915 private structure
1308 * @pipe: pipe PLL to enable
1310 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1311 * make sure the PLL reg is writable first though, since the panel write
1312 * protect mechanism may be enabled.
1314 * Note! This is for pre-ILK only.
1316 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1318 static void intel_enable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1323 assert_pipe_disabled(dev_priv
, pipe
);
1325 /* No really, not for ILK+ */
1326 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
) && dev_priv
->info
->gen
>= 5);
1328 /* PLL is protected by panel, make sure we can write it */
1329 if (IS_MOBILE(dev_priv
->dev
) && !IS_I830(dev_priv
->dev
))
1330 assert_panel_unlocked(dev_priv
, pipe
);
1333 val
= I915_READ(reg
);
1334 val
|= DPLL_VCO_ENABLE
;
1336 /* We do this three times for luck */
1337 I915_WRITE(reg
, val
);
1339 udelay(150); /* wait for warmup */
1340 I915_WRITE(reg
, val
);
1342 udelay(150); /* wait for warmup */
1343 I915_WRITE(reg
, val
);
1345 udelay(150); /* wait for warmup */
1349 * intel_disable_pll - disable a PLL
1350 * @dev_priv: i915 private structure
1351 * @pipe: pipe PLL to disable
1353 * Disable the PLL for @pipe, making sure the pipe is off first.
1355 * Note! This is for pre-ILK only.
1357 static void intel_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1362 /* Don't disable pipe A or pipe A PLLs if needed */
1363 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1366 /* Make sure the pipe isn't still relying on us */
1367 assert_pipe_disabled(dev_priv
, pipe
);
1370 val
= I915_READ(reg
);
1371 val
&= ~DPLL_VCO_ENABLE
;
1372 I915_WRITE(reg
, val
);
1376 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
, int port
)
1381 port_mask
= DPLL_PORTB_READY_MASK
;
1383 port_mask
= DPLL_PORTC_READY_MASK
;
1385 if (wait_for((I915_READ(DPLL(0)) & port_mask
) == 0, 1000))
1386 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1387 'B' + port
, I915_READ(DPLL(0)));
1391 * ironlake_enable_shared_dpll - enable PCH PLL
1392 * @dev_priv: i915 private structure
1393 * @pipe: pipe PLL to enable
1395 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1396 * drives the transcoder clock.
1398 static void ironlake_enable_shared_dpll(struct intel_crtc
*crtc
)
1400 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1401 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1403 /* PCH PLLs only available on ILK, SNB and IVB */
1404 BUG_ON(dev_priv
->info
->gen
< 5);
1408 if (WARN_ON(pll
->refcount
== 0))
1411 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1412 pll
->name
, pll
->active
, pll
->on
,
1413 crtc
->base
.base
.id
);
1415 if (pll
->active
++) {
1417 assert_shared_dpll_enabled(dev_priv
, pll
);
1422 DRM_DEBUG_KMS("enabling %s\n", pll
->name
);
1423 pll
->enable(dev_priv
, pll
);
1427 static void intel_disable_shared_dpll(struct intel_crtc
*crtc
)
1429 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1430 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1432 /* PCH only available on ILK+ */
1433 BUG_ON(dev_priv
->info
->gen
< 5);
1437 if (WARN_ON(pll
->refcount
== 0))
1440 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1441 pll
->name
, pll
->active
, pll
->on
,
1442 crtc
->base
.base
.id
);
1444 if (WARN_ON(pll
->active
== 0)) {
1445 assert_shared_dpll_disabled(dev_priv
, pll
);
1449 assert_shared_dpll_enabled(dev_priv
, pll
);
1454 DRM_DEBUG_KMS("disabling %s\n", pll
->name
);
1455 pll
->disable(dev_priv
, pll
);
1459 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1462 struct drm_device
*dev
= dev_priv
->dev
;
1463 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1464 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1465 uint32_t reg
, val
, pipeconf_val
;
1467 /* PCH only available on ILK+ */
1468 BUG_ON(dev_priv
->info
->gen
< 5);
1470 /* Make sure PCH DPLL is enabled */
1471 assert_shared_dpll_enabled(dev_priv
,
1472 intel_crtc_to_shared_dpll(intel_crtc
));
1474 /* FDI must be feeding us bits for PCH ports */
1475 assert_fdi_tx_enabled(dev_priv
, pipe
);
1476 assert_fdi_rx_enabled(dev_priv
, pipe
);
1478 if (HAS_PCH_CPT(dev
)) {
1479 /* Workaround: Set the timing override bit before enabling the
1480 * pch transcoder. */
1481 reg
= TRANS_CHICKEN2(pipe
);
1482 val
= I915_READ(reg
);
1483 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1484 I915_WRITE(reg
, val
);
1487 reg
= PCH_TRANSCONF(pipe
);
1488 val
= I915_READ(reg
);
1489 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1491 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1493 * make the BPC in transcoder be consistent with
1494 * that in pipeconf reg.
1496 val
&= ~PIPECONF_BPC_MASK
;
1497 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1500 val
&= ~TRANS_INTERLACE_MASK
;
1501 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1502 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1503 intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
))
1504 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1506 val
|= TRANS_INTERLACED
;
1508 val
|= TRANS_PROGRESSIVE
;
1510 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1511 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1512 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
1515 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1516 enum transcoder cpu_transcoder
)
1518 u32 val
, pipeconf_val
;
1520 /* PCH only available on ILK+ */
1521 BUG_ON(dev_priv
->info
->gen
< 5);
1523 /* FDI must be feeding us bits for PCH ports */
1524 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1525 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
1527 /* Workaround: set timing override bit. */
1528 val
= I915_READ(_TRANSA_CHICKEN2
);
1529 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1530 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1533 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1535 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1536 PIPECONF_INTERLACED_ILK
)
1537 val
|= TRANS_INTERLACED
;
1539 val
|= TRANS_PROGRESSIVE
;
1541 I915_WRITE(LPT_TRANSCONF
, val
);
1542 if (wait_for(I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
, 100))
1543 DRM_ERROR("Failed to enable PCH transcoder\n");
1546 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1549 struct drm_device
*dev
= dev_priv
->dev
;
1552 /* FDI relies on the transcoder */
1553 assert_fdi_tx_disabled(dev_priv
, pipe
);
1554 assert_fdi_rx_disabled(dev_priv
, pipe
);
1556 /* Ports must be off as well */
1557 assert_pch_ports_disabled(dev_priv
, pipe
);
1559 reg
= PCH_TRANSCONF(pipe
);
1560 val
= I915_READ(reg
);
1561 val
&= ~TRANS_ENABLE
;
1562 I915_WRITE(reg
, val
);
1563 /* wait for PCH transcoder off, transcoder state */
1564 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1565 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
1567 if (!HAS_PCH_IBX(dev
)) {
1568 /* Workaround: Clear the timing override chicken bit again. */
1569 reg
= TRANS_CHICKEN2(pipe
);
1570 val
= I915_READ(reg
);
1571 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1572 I915_WRITE(reg
, val
);
1576 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1580 val
= I915_READ(LPT_TRANSCONF
);
1581 val
&= ~TRANS_ENABLE
;
1582 I915_WRITE(LPT_TRANSCONF
, val
);
1583 /* wait for PCH transcoder off, transcoder state */
1584 if (wait_for((I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
) == 0, 50))
1585 DRM_ERROR("Failed to disable PCH transcoder\n");
1587 /* Workaround: clear timing override bit. */
1588 val
= I915_READ(_TRANSA_CHICKEN2
);
1589 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1590 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1594 * intel_enable_pipe - enable a pipe, asserting requirements
1595 * @dev_priv: i915 private structure
1596 * @pipe: pipe to enable
1597 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1599 * Enable @pipe, making sure that various hardware specific requirements
1600 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1602 * @pipe should be %PIPE_A or %PIPE_B.
1604 * Will wait until the pipe is actually running (i.e. first vblank) before
1607 static void intel_enable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
1610 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1612 enum pipe pch_transcoder
;
1616 assert_planes_disabled(dev_priv
, pipe
);
1617 assert_sprites_disabled(dev_priv
, pipe
);
1619 if (HAS_PCH_LPT(dev_priv
->dev
))
1620 pch_transcoder
= TRANSCODER_A
;
1622 pch_transcoder
= pipe
;
1625 * A pipe without a PLL won't actually be able to drive bits from
1626 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1629 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
1630 assert_pll_enabled(dev_priv
, pipe
);
1633 /* if driving the PCH, we need FDI enabled */
1634 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
1635 assert_fdi_tx_pll_enabled(dev_priv
,
1636 (enum pipe
) cpu_transcoder
);
1638 /* FIXME: assert CPU port conditions for SNB+ */
1641 reg
= PIPECONF(cpu_transcoder
);
1642 val
= I915_READ(reg
);
1643 if (val
& PIPECONF_ENABLE
)
1646 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
1647 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1651 * intel_disable_pipe - disable a pipe, asserting requirements
1652 * @dev_priv: i915 private structure
1653 * @pipe: pipe to disable
1655 * Disable @pipe, making sure that various hardware specific requirements
1656 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1658 * @pipe should be %PIPE_A or %PIPE_B.
1660 * Will wait until the pipe has shut down before returning.
1662 static void intel_disable_pipe(struct drm_i915_private
*dev_priv
,
1665 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1671 * Make sure planes won't keep trying to pump pixels to us,
1672 * or we might hang the display.
1674 assert_planes_disabled(dev_priv
, pipe
);
1675 assert_sprites_disabled(dev_priv
, pipe
);
1677 /* Don't disable pipe A or pipe A PLLs if needed */
1678 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1681 reg
= PIPECONF(cpu_transcoder
);
1682 val
= I915_READ(reg
);
1683 if ((val
& PIPECONF_ENABLE
) == 0)
1686 I915_WRITE(reg
, val
& ~PIPECONF_ENABLE
);
1687 intel_wait_for_pipe_off(dev_priv
->dev
, pipe
);
1691 * Plane regs are double buffered, going from enabled->disabled needs a
1692 * trigger in order to latch. The display address reg provides this.
1694 void intel_flush_display_plane(struct drm_i915_private
*dev_priv
,
1697 if (dev_priv
->info
->gen
>= 4)
1698 I915_WRITE(DSPSURF(plane
), I915_READ(DSPSURF(plane
)));
1700 I915_WRITE(DSPADDR(plane
), I915_READ(DSPADDR(plane
)));
1704 * intel_enable_plane - enable a display plane on a given pipe
1705 * @dev_priv: i915 private structure
1706 * @plane: plane to enable
1707 * @pipe: pipe being fed
1709 * Enable @plane on @pipe, making sure that @pipe is running first.
1711 static void intel_enable_plane(struct drm_i915_private
*dev_priv
,
1712 enum plane plane
, enum pipe pipe
)
1717 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1718 assert_pipe_enabled(dev_priv
, pipe
);
1720 reg
= DSPCNTR(plane
);
1721 val
= I915_READ(reg
);
1722 if (val
& DISPLAY_PLANE_ENABLE
)
1725 I915_WRITE(reg
, val
| DISPLAY_PLANE_ENABLE
);
1726 intel_flush_display_plane(dev_priv
, plane
);
1727 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1731 * intel_disable_plane - disable a display plane
1732 * @dev_priv: i915 private structure
1733 * @plane: plane to disable
1734 * @pipe: pipe consuming the data
1736 * Disable @plane; should be an independent operation.
1738 static void intel_disable_plane(struct drm_i915_private
*dev_priv
,
1739 enum plane plane
, enum pipe pipe
)
1744 reg
= DSPCNTR(plane
);
1745 val
= I915_READ(reg
);
1746 if ((val
& DISPLAY_PLANE_ENABLE
) == 0)
1749 I915_WRITE(reg
, val
& ~DISPLAY_PLANE_ENABLE
);
1750 intel_flush_display_plane(dev_priv
, plane
);
1751 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1754 static bool need_vtd_wa(struct drm_device
*dev
)
1756 #ifdef CONFIG_INTEL_IOMMU
1757 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
1764 intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
1765 struct drm_i915_gem_object
*obj
,
1766 struct intel_ring_buffer
*pipelined
)
1768 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1772 switch (obj
->tiling_mode
) {
1773 case I915_TILING_NONE
:
1774 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
1775 alignment
= 128 * 1024;
1776 else if (INTEL_INFO(dev
)->gen
>= 4)
1777 alignment
= 4 * 1024;
1779 alignment
= 64 * 1024;
1782 /* pin() will align the object as required by fence */
1786 /* Despite that we check this in framebuffer_init userspace can
1787 * screw us over and change the tiling after the fact. Only
1788 * pinned buffers can't change their tiling. */
1789 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1795 /* Note that the w/a also requires 64 PTE of padding following the
1796 * bo. We currently fill all unused PTE with the shadow page and so
1797 * we should always have valid PTE following the scanout preventing
1800 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
1801 alignment
= 256 * 1024;
1803 dev_priv
->mm
.interruptible
= false;
1804 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
);
1806 goto err_interruptible
;
1808 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1809 * fence, whereas 965+ only requires a fence if using
1810 * framebuffer compression. For simplicity, we always install
1811 * a fence as the cost is not that onerous.
1813 ret
= i915_gem_object_get_fence(obj
);
1817 i915_gem_object_pin_fence(obj
);
1819 dev_priv
->mm
.interruptible
= true;
1823 i915_gem_object_unpin(obj
);
1825 dev_priv
->mm
.interruptible
= true;
1829 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
)
1831 i915_gem_object_unpin_fence(obj
);
1832 i915_gem_object_unpin(obj
);
1835 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1836 * is assumed to be a power-of-two. */
1837 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
1838 unsigned int tiling_mode
,
1842 if (tiling_mode
!= I915_TILING_NONE
) {
1843 unsigned int tile_rows
, tiles
;
1848 tiles
= *x
/ (512/cpp
);
1851 return tile_rows
* pitch
* 8 + tiles
* 4096;
1853 unsigned int offset
;
1855 offset
= *y
* pitch
+ *x
* cpp
;
1857 *x
= (offset
& 4095) / cpp
;
1858 return offset
& -4096;
1862 static int i9xx_update_plane(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
1865 struct drm_device
*dev
= crtc
->dev
;
1866 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1867 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1868 struct intel_framebuffer
*intel_fb
;
1869 struct drm_i915_gem_object
*obj
;
1870 int plane
= intel_crtc
->plane
;
1871 unsigned long linear_offset
;
1880 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane
));
1884 intel_fb
= to_intel_framebuffer(fb
);
1885 obj
= intel_fb
->obj
;
1887 reg
= DSPCNTR(plane
);
1888 dspcntr
= I915_READ(reg
);
1889 /* Mask out pixel format bits in case we change it */
1890 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
1891 switch (fb
->pixel_format
) {
1893 dspcntr
|= DISPPLANE_8BPP
;
1895 case DRM_FORMAT_XRGB1555
:
1896 case DRM_FORMAT_ARGB1555
:
1897 dspcntr
|= DISPPLANE_BGRX555
;
1899 case DRM_FORMAT_RGB565
:
1900 dspcntr
|= DISPPLANE_BGRX565
;
1902 case DRM_FORMAT_XRGB8888
:
1903 case DRM_FORMAT_ARGB8888
:
1904 dspcntr
|= DISPPLANE_BGRX888
;
1906 case DRM_FORMAT_XBGR8888
:
1907 case DRM_FORMAT_ABGR8888
:
1908 dspcntr
|= DISPPLANE_RGBX888
;
1910 case DRM_FORMAT_XRGB2101010
:
1911 case DRM_FORMAT_ARGB2101010
:
1912 dspcntr
|= DISPPLANE_BGRX101010
;
1914 case DRM_FORMAT_XBGR2101010
:
1915 case DRM_FORMAT_ABGR2101010
:
1916 dspcntr
|= DISPPLANE_RGBX101010
;
1922 if (INTEL_INFO(dev
)->gen
>= 4) {
1923 if (obj
->tiling_mode
!= I915_TILING_NONE
)
1924 dspcntr
|= DISPPLANE_TILED
;
1926 dspcntr
&= ~DISPPLANE_TILED
;
1930 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
1932 I915_WRITE(reg
, dspcntr
);
1934 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
1936 if (INTEL_INFO(dev
)->gen
>= 4) {
1937 intel_crtc
->dspaddr_offset
=
1938 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
1939 fb
->bits_per_pixel
/ 8,
1941 linear_offset
-= intel_crtc
->dspaddr_offset
;
1943 intel_crtc
->dspaddr_offset
= linear_offset
;
1946 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
1947 obj
->gtt_offset
, linear_offset
, x
, y
, fb
->pitches
[0]);
1948 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
1949 if (INTEL_INFO(dev
)->gen
>= 4) {
1950 I915_MODIFY_DISPBASE(DSPSURF(plane
),
1951 obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
1952 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
1953 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
1955 I915_WRITE(DSPADDR(plane
), obj
->gtt_offset
+ linear_offset
);
1961 static int ironlake_update_plane(struct drm_crtc
*crtc
,
1962 struct drm_framebuffer
*fb
, int x
, int y
)
1964 struct drm_device
*dev
= crtc
->dev
;
1965 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1966 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1967 struct intel_framebuffer
*intel_fb
;
1968 struct drm_i915_gem_object
*obj
;
1969 int plane
= intel_crtc
->plane
;
1970 unsigned long linear_offset
;
1980 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane
));
1984 intel_fb
= to_intel_framebuffer(fb
);
1985 obj
= intel_fb
->obj
;
1987 reg
= DSPCNTR(plane
);
1988 dspcntr
= I915_READ(reg
);
1989 /* Mask out pixel format bits in case we change it */
1990 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
1991 switch (fb
->pixel_format
) {
1993 dspcntr
|= DISPPLANE_8BPP
;
1995 case DRM_FORMAT_RGB565
:
1996 dspcntr
|= DISPPLANE_BGRX565
;
1998 case DRM_FORMAT_XRGB8888
:
1999 case DRM_FORMAT_ARGB8888
:
2000 dspcntr
|= DISPPLANE_BGRX888
;
2002 case DRM_FORMAT_XBGR8888
:
2003 case DRM_FORMAT_ABGR8888
:
2004 dspcntr
|= DISPPLANE_RGBX888
;
2006 case DRM_FORMAT_XRGB2101010
:
2007 case DRM_FORMAT_ARGB2101010
:
2008 dspcntr
|= DISPPLANE_BGRX101010
;
2010 case DRM_FORMAT_XBGR2101010
:
2011 case DRM_FORMAT_ABGR2101010
:
2012 dspcntr
|= DISPPLANE_RGBX101010
;
2018 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2019 dspcntr
|= DISPPLANE_TILED
;
2021 dspcntr
&= ~DISPPLANE_TILED
;
2024 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2026 I915_WRITE(reg
, dspcntr
);
2028 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2029 intel_crtc
->dspaddr_offset
=
2030 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2031 fb
->bits_per_pixel
/ 8,
2033 linear_offset
-= intel_crtc
->dspaddr_offset
;
2035 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2036 obj
->gtt_offset
, linear_offset
, x
, y
, fb
->pitches
[0]);
2037 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2038 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2039 obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
2040 if (IS_HASWELL(dev
)) {
2041 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2043 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2044 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2051 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2053 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2054 int x
, int y
, enum mode_set_atomic state
)
2056 struct drm_device
*dev
= crtc
->dev
;
2057 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2059 if (dev_priv
->display
.disable_fbc
)
2060 dev_priv
->display
.disable_fbc(dev
);
2061 intel_increase_pllclock(crtc
);
2063 return dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2066 void intel_display_handle_reset(struct drm_device
*dev
)
2068 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2069 struct drm_crtc
*crtc
;
2072 * Flips in the rings have been nuked by the reset,
2073 * so complete all pending flips so that user space
2074 * will get its events and not get stuck.
2076 * Also update the base address of all primary
2077 * planes to the the last fb to make sure we're
2078 * showing the correct fb after a reset.
2080 * Need to make two loops over the crtcs so that we
2081 * don't try to grab a crtc mutex before the
2082 * pending_flip_queue really got woken up.
2085 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2086 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2087 enum plane plane
= intel_crtc
->plane
;
2089 intel_prepare_page_flip(dev
, plane
);
2090 intel_finish_page_flip_plane(dev
, plane
);
2093 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2094 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2096 mutex_lock(&crtc
->mutex
);
2097 if (intel_crtc
->active
)
2098 dev_priv
->display
.update_plane(crtc
, crtc
->fb
,
2100 mutex_unlock(&crtc
->mutex
);
2105 intel_finish_fb(struct drm_framebuffer
*old_fb
)
2107 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(old_fb
)->obj
;
2108 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2109 bool was_interruptible
= dev_priv
->mm
.interruptible
;
2112 /* Big Hammer, we also need to ensure that any pending
2113 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2114 * current scanout is retired before unpinning the old
2117 * This should only fail upon a hung GPU, in which case we
2118 * can safely continue.
2120 dev_priv
->mm
.interruptible
= false;
2121 ret
= i915_gem_object_finish_gpu(obj
);
2122 dev_priv
->mm
.interruptible
= was_interruptible
;
2127 static void intel_crtc_update_sarea_pos(struct drm_crtc
*crtc
, int x
, int y
)
2129 struct drm_device
*dev
= crtc
->dev
;
2130 struct drm_i915_master_private
*master_priv
;
2131 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2133 if (!dev
->primary
->master
)
2136 master_priv
= dev
->primary
->master
->driver_priv
;
2137 if (!master_priv
->sarea_priv
)
2140 switch (intel_crtc
->pipe
) {
2142 master_priv
->sarea_priv
->pipeA_x
= x
;
2143 master_priv
->sarea_priv
->pipeA_y
= y
;
2146 master_priv
->sarea_priv
->pipeB_x
= x
;
2147 master_priv
->sarea_priv
->pipeB_y
= y
;
2155 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2156 struct drm_framebuffer
*fb
)
2158 struct drm_device
*dev
= crtc
->dev
;
2159 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2160 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2161 struct drm_framebuffer
*old_fb
;
2166 DRM_ERROR("No FB bound\n");
2170 if (intel_crtc
->plane
> INTEL_INFO(dev
)->num_pipes
) {
2171 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2172 plane_name(intel_crtc
->plane
),
2173 INTEL_INFO(dev
)->num_pipes
);
2177 mutex_lock(&dev
->struct_mutex
);
2178 ret
= intel_pin_and_fence_fb_obj(dev
,
2179 to_intel_framebuffer(fb
)->obj
,
2182 mutex_unlock(&dev
->struct_mutex
);
2183 DRM_ERROR("pin & fence failed\n");
2187 ret
= dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2189 intel_unpin_fb_obj(to_intel_framebuffer(fb
)->obj
);
2190 mutex_unlock(&dev
->struct_mutex
);
2191 DRM_ERROR("failed to update base address\n");
2201 if (intel_crtc
->active
&& old_fb
!= fb
)
2202 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2203 intel_unpin_fb_obj(to_intel_framebuffer(old_fb
)->obj
);
2206 intel_update_fbc(dev
);
2207 mutex_unlock(&dev
->struct_mutex
);
2209 intel_crtc_update_sarea_pos(crtc
, x
, y
);
2214 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
2216 struct drm_device
*dev
= crtc
->dev
;
2217 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2218 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2219 int pipe
= intel_crtc
->pipe
;
2222 /* enable normal train */
2223 reg
= FDI_TX_CTL(pipe
);
2224 temp
= I915_READ(reg
);
2225 if (IS_IVYBRIDGE(dev
)) {
2226 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2227 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2229 temp
&= ~FDI_LINK_TRAIN_NONE
;
2230 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2232 I915_WRITE(reg
, temp
);
2234 reg
= FDI_RX_CTL(pipe
);
2235 temp
= I915_READ(reg
);
2236 if (HAS_PCH_CPT(dev
)) {
2237 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2238 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2240 temp
&= ~FDI_LINK_TRAIN_NONE
;
2241 temp
|= FDI_LINK_TRAIN_NONE
;
2243 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2245 /* wait one idle pattern time */
2249 /* IVB wants error correction enabled */
2250 if (IS_IVYBRIDGE(dev
))
2251 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
2252 FDI_FE_ERRC_ENABLE
);
2255 static bool pipe_has_enabled_pch(struct intel_crtc
*intel_crtc
)
2257 return intel_crtc
->base
.enabled
&& intel_crtc
->config
.has_pch_encoder
;
2260 static void ivb_modeset_global_resources(struct drm_device
*dev
)
2262 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2263 struct intel_crtc
*pipe_B_crtc
=
2264 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
2265 struct intel_crtc
*pipe_C_crtc
=
2266 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]);
2270 * When everything is off disable fdi C so that we could enable fdi B
2271 * with all lanes. Note that we don't care about enabled pipes without
2272 * an enabled pch encoder.
2274 if (!pipe_has_enabled_pch(pipe_B_crtc
) &&
2275 !pipe_has_enabled_pch(pipe_C_crtc
)) {
2276 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
2277 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
2279 temp
= I915_READ(SOUTH_CHICKEN1
);
2280 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
2281 DRM_DEBUG_KMS("disabling fdi C rx\n");
2282 I915_WRITE(SOUTH_CHICKEN1
, temp
);
2286 /* The FDI link training functions for ILK/Ibexpeak. */
2287 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
2289 struct drm_device
*dev
= crtc
->dev
;
2290 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2291 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2292 int pipe
= intel_crtc
->pipe
;
2293 int plane
= intel_crtc
->plane
;
2294 u32 reg
, temp
, tries
;
2296 /* FDI needs bits from pipe & plane first */
2297 assert_pipe_enabled(dev_priv
, pipe
);
2298 assert_plane_enabled(dev_priv
, plane
);
2300 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2302 reg
= FDI_RX_IMR(pipe
);
2303 temp
= I915_READ(reg
);
2304 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2305 temp
&= ~FDI_RX_BIT_LOCK
;
2306 I915_WRITE(reg
, temp
);
2310 /* enable CPU FDI TX and PCH FDI RX */
2311 reg
= FDI_TX_CTL(pipe
);
2312 temp
= I915_READ(reg
);
2313 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2314 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2315 temp
&= ~FDI_LINK_TRAIN_NONE
;
2316 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2317 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2319 reg
= FDI_RX_CTL(pipe
);
2320 temp
= I915_READ(reg
);
2321 temp
&= ~FDI_LINK_TRAIN_NONE
;
2322 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2323 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2328 /* Ironlake workaround, enable clock pointer after FDI enable*/
2329 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2330 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
2331 FDI_RX_PHASE_SYNC_POINTER_EN
);
2333 reg
= FDI_RX_IIR(pipe
);
2334 for (tries
= 0; tries
< 5; tries
++) {
2335 temp
= I915_READ(reg
);
2336 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2338 if ((temp
& FDI_RX_BIT_LOCK
)) {
2339 DRM_DEBUG_KMS("FDI train 1 done.\n");
2340 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2345 DRM_ERROR("FDI train 1 fail!\n");
2348 reg
= FDI_TX_CTL(pipe
);
2349 temp
= I915_READ(reg
);
2350 temp
&= ~FDI_LINK_TRAIN_NONE
;
2351 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2352 I915_WRITE(reg
, temp
);
2354 reg
= FDI_RX_CTL(pipe
);
2355 temp
= I915_READ(reg
);
2356 temp
&= ~FDI_LINK_TRAIN_NONE
;
2357 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2358 I915_WRITE(reg
, temp
);
2363 reg
= FDI_RX_IIR(pipe
);
2364 for (tries
= 0; tries
< 5; tries
++) {
2365 temp
= I915_READ(reg
);
2366 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2368 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2369 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2370 DRM_DEBUG_KMS("FDI train 2 done.\n");
2375 DRM_ERROR("FDI train 2 fail!\n");
2377 DRM_DEBUG_KMS("FDI train done\n");
2381 static const int snb_b_fdi_train_param
[] = {
2382 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
2383 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
2384 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
2385 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
2388 /* The FDI link training functions for SNB/Cougarpoint. */
2389 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
2391 struct drm_device
*dev
= crtc
->dev
;
2392 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2393 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2394 int pipe
= intel_crtc
->pipe
;
2395 u32 reg
, temp
, i
, retry
;
2397 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2399 reg
= FDI_RX_IMR(pipe
);
2400 temp
= I915_READ(reg
);
2401 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2402 temp
&= ~FDI_RX_BIT_LOCK
;
2403 I915_WRITE(reg
, temp
);
2408 /* enable CPU FDI TX and PCH FDI RX */
2409 reg
= FDI_TX_CTL(pipe
);
2410 temp
= I915_READ(reg
);
2411 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2412 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2413 temp
&= ~FDI_LINK_TRAIN_NONE
;
2414 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2415 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2417 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2418 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2420 I915_WRITE(FDI_RX_MISC(pipe
),
2421 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2423 reg
= FDI_RX_CTL(pipe
);
2424 temp
= I915_READ(reg
);
2425 if (HAS_PCH_CPT(dev
)) {
2426 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2427 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2429 temp
&= ~FDI_LINK_TRAIN_NONE
;
2430 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2432 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2437 for (i
= 0; i
< 4; i
++) {
2438 reg
= FDI_TX_CTL(pipe
);
2439 temp
= I915_READ(reg
);
2440 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2441 temp
|= snb_b_fdi_train_param
[i
];
2442 I915_WRITE(reg
, temp
);
2447 for (retry
= 0; retry
< 5; retry
++) {
2448 reg
= FDI_RX_IIR(pipe
);
2449 temp
= I915_READ(reg
);
2450 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2451 if (temp
& FDI_RX_BIT_LOCK
) {
2452 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2453 DRM_DEBUG_KMS("FDI train 1 done.\n");
2462 DRM_ERROR("FDI train 1 fail!\n");
2465 reg
= FDI_TX_CTL(pipe
);
2466 temp
= I915_READ(reg
);
2467 temp
&= ~FDI_LINK_TRAIN_NONE
;
2468 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2470 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2472 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2474 I915_WRITE(reg
, temp
);
2476 reg
= FDI_RX_CTL(pipe
);
2477 temp
= I915_READ(reg
);
2478 if (HAS_PCH_CPT(dev
)) {
2479 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2480 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2482 temp
&= ~FDI_LINK_TRAIN_NONE
;
2483 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2485 I915_WRITE(reg
, temp
);
2490 for (i
= 0; i
< 4; i
++) {
2491 reg
= FDI_TX_CTL(pipe
);
2492 temp
= I915_READ(reg
);
2493 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2494 temp
|= snb_b_fdi_train_param
[i
];
2495 I915_WRITE(reg
, temp
);
2500 for (retry
= 0; retry
< 5; retry
++) {
2501 reg
= FDI_RX_IIR(pipe
);
2502 temp
= I915_READ(reg
);
2503 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2504 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2505 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2506 DRM_DEBUG_KMS("FDI train 2 done.\n");
2515 DRM_ERROR("FDI train 2 fail!\n");
2517 DRM_DEBUG_KMS("FDI train done.\n");
2520 /* Manual link training for Ivy Bridge A0 parts */
2521 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
2523 struct drm_device
*dev
= crtc
->dev
;
2524 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2525 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2526 int pipe
= intel_crtc
->pipe
;
2529 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2531 reg
= FDI_RX_IMR(pipe
);
2532 temp
= I915_READ(reg
);
2533 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2534 temp
&= ~FDI_RX_BIT_LOCK
;
2535 I915_WRITE(reg
, temp
);
2540 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2541 I915_READ(FDI_RX_IIR(pipe
)));
2543 /* enable CPU FDI TX and PCH FDI RX */
2544 reg
= FDI_TX_CTL(pipe
);
2545 temp
= I915_READ(reg
);
2546 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2547 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2548 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
2549 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
2550 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2551 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2552 temp
|= FDI_COMPOSITE_SYNC
;
2553 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2555 I915_WRITE(FDI_RX_MISC(pipe
),
2556 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2558 reg
= FDI_RX_CTL(pipe
);
2559 temp
= I915_READ(reg
);
2560 temp
&= ~FDI_LINK_TRAIN_AUTO
;
2561 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2562 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2563 temp
|= FDI_COMPOSITE_SYNC
;
2564 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2569 for (i
= 0; i
< 4; i
++) {
2570 reg
= FDI_TX_CTL(pipe
);
2571 temp
= I915_READ(reg
);
2572 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2573 temp
|= snb_b_fdi_train_param
[i
];
2574 I915_WRITE(reg
, temp
);
2579 reg
= FDI_RX_IIR(pipe
);
2580 temp
= I915_READ(reg
);
2581 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2583 if (temp
& FDI_RX_BIT_LOCK
||
2584 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
2585 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2586 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i
);
2591 DRM_ERROR("FDI train 1 fail!\n");
2594 reg
= FDI_TX_CTL(pipe
);
2595 temp
= I915_READ(reg
);
2596 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2597 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
2598 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2599 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2600 I915_WRITE(reg
, temp
);
2602 reg
= FDI_RX_CTL(pipe
);
2603 temp
= I915_READ(reg
);
2604 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2605 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2606 I915_WRITE(reg
, temp
);
2611 for (i
= 0; i
< 4; i
++) {
2612 reg
= FDI_TX_CTL(pipe
);
2613 temp
= I915_READ(reg
);
2614 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2615 temp
|= snb_b_fdi_train_param
[i
];
2616 I915_WRITE(reg
, temp
);
2621 reg
= FDI_RX_IIR(pipe
);
2622 temp
= I915_READ(reg
);
2623 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2625 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2626 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2627 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i
);
2632 DRM_ERROR("FDI train 2 fail!\n");
2634 DRM_DEBUG_KMS("FDI train done.\n");
2637 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
2639 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2640 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2641 int pipe
= intel_crtc
->pipe
;
2645 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2646 reg
= FDI_RX_CTL(pipe
);
2647 temp
= I915_READ(reg
);
2648 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
2649 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2650 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2651 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
2656 /* Switch from Rawclk to PCDclk */
2657 temp
= I915_READ(reg
);
2658 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
2663 /* Enable CPU FDI TX PLL, always on for Ironlake */
2664 reg
= FDI_TX_CTL(pipe
);
2665 temp
= I915_READ(reg
);
2666 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
2667 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
2674 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
2676 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2677 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2678 int pipe
= intel_crtc
->pipe
;
2681 /* Switch from PCDclk to Rawclk */
2682 reg
= FDI_RX_CTL(pipe
);
2683 temp
= I915_READ(reg
);
2684 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
2686 /* Disable CPU FDI TX PLL */
2687 reg
= FDI_TX_CTL(pipe
);
2688 temp
= I915_READ(reg
);
2689 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
2694 reg
= FDI_RX_CTL(pipe
);
2695 temp
= I915_READ(reg
);
2696 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
2698 /* Wait for the clocks to turn off. */
2703 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
2705 struct drm_device
*dev
= crtc
->dev
;
2706 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2707 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2708 int pipe
= intel_crtc
->pipe
;
2711 /* disable CPU FDI tx and PCH FDI rx */
2712 reg
= FDI_TX_CTL(pipe
);
2713 temp
= I915_READ(reg
);
2714 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
2717 reg
= FDI_RX_CTL(pipe
);
2718 temp
= I915_READ(reg
);
2719 temp
&= ~(0x7 << 16);
2720 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2721 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
2726 /* Ironlake workaround, disable clock pointer after downing FDI */
2727 if (HAS_PCH_IBX(dev
)) {
2728 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2731 /* still set train pattern 1 */
2732 reg
= FDI_TX_CTL(pipe
);
2733 temp
= I915_READ(reg
);
2734 temp
&= ~FDI_LINK_TRAIN_NONE
;
2735 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2736 I915_WRITE(reg
, temp
);
2738 reg
= FDI_RX_CTL(pipe
);
2739 temp
= I915_READ(reg
);
2740 if (HAS_PCH_CPT(dev
)) {
2741 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2742 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2744 temp
&= ~FDI_LINK_TRAIN_NONE
;
2745 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2747 /* BPC in FDI rx is consistent with that in PIPECONF */
2748 temp
&= ~(0x07 << 16);
2749 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2750 I915_WRITE(reg
, temp
);
2756 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
2758 struct drm_device
*dev
= crtc
->dev
;
2759 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2760 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2761 unsigned long flags
;
2764 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
2765 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
2768 spin_lock_irqsave(&dev
->event_lock
, flags
);
2769 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
2770 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2775 static void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
2777 struct drm_device
*dev
= crtc
->dev
;
2778 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2780 if (crtc
->fb
== NULL
)
2783 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
2785 wait_event(dev_priv
->pending_flip_queue
,
2786 !intel_crtc_has_pending_flip(crtc
));
2788 mutex_lock(&dev
->struct_mutex
);
2789 intel_finish_fb(crtc
->fb
);
2790 mutex_unlock(&dev
->struct_mutex
);
2793 /* Program iCLKIP clock to the desired frequency */
2794 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
2796 struct drm_device
*dev
= crtc
->dev
;
2797 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2798 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
2801 mutex_lock(&dev_priv
->dpio_lock
);
2803 /* It is necessary to ungate the pixclk gate prior to programming
2804 * the divisors, and gate it back when it is done.
2806 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
2808 /* Disable SSCCTL */
2809 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
2810 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
2814 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2815 if (crtc
->mode
.clock
== 20000) {
2820 /* The iCLK virtual clock root frequency is in MHz,
2821 * but the crtc->mode.clock in in KHz. To get the divisors,
2822 * it is necessary to divide one by another, so we
2823 * convert the virtual clock precision to KHz here for higher
2826 u32 iclk_virtual_root_freq
= 172800 * 1000;
2827 u32 iclk_pi_range
= 64;
2828 u32 desired_divisor
, msb_divisor_value
, pi_value
;
2830 desired_divisor
= (iclk_virtual_root_freq
/ crtc
->mode
.clock
);
2831 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
2832 pi_value
= desired_divisor
% iclk_pi_range
;
2835 divsel
= msb_divisor_value
- 2;
2836 phaseinc
= pi_value
;
2839 /* This should not happen with any sane values */
2840 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
2841 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
2842 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
2843 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
2845 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2852 /* Program SSCDIVINTPHASE6 */
2853 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
2854 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
2855 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
2856 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
2857 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
2858 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
2859 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
2860 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
2862 /* Program SSCAUXDIV */
2863 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
2864 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2865 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
2866 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
2868 /* Enable modulator and associated divider */
2869 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
2870 temp
&= ~SBI_SSCCTL_DISABLE
;
2871 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
2873 /* Wait for initialization time */
2876 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
2878 mutex_unlock(&dev_priv
->dpio_lock
);
2881 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
2882 enum pipe pch_transcoder
)
2884 struct drm_device
*dev
= crtc
->base
.dev
;
2885 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2886 enum transcoder cpu_transcoder
= crtc
->config
.cpu_transcoder
;
2888 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
2889 I915_READ(HTOTAL(cpu_transcoder
)));
2890 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
2891 I915_READ(HBLANK(cpu_transcoder
)));
2892 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
2893 I915_READ(HSYNC(cpu_transcoder
)));
2895 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
2896 I915_READ(VTOTAL(cpu_transcoder
)));
2897 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
2898 I915_READ(VBLANK(cpu_transcoder
)));
2899 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
2900 I915_READ(VSYNC(cpu_transcoder
)));
2901 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
2902 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
2906 * Enable PCH resources required for PCH ports:
2908 * - FDI training & RX/TX
2909 * - update transcoder timings
2910 * - DP transcoding bits
2913 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
2915 struct drm_device
*dev
= crtc
->dev
;
2916 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2917 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2918 int pipe
= intel_crtc
->pipe
;
2921 assert_pch_transcoder_disabled(dev_priv
, pipe
);
2923 /* Write the TU size bits before fdi link training, so that error
2924 * detection works. */
2925 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
2926 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
2928 /* For PCH output, training FDI link */
2929 dev_priv
->display
.fdi_link_train(crtc
);
2931 /* XXX: pch pll's can be enabled any time before we enable the PCH
2932 * transcoder, and we actually should do this to not upset any PCH
2933 * transcoder that already use the clock when we share it.
2935 * Note that enable_shared_dpll tries to do the right thing, but
2936 * get_shared_dpll unconditionally resets the pll - we need that to have
2937 * the right LVDS enable sequence. */
2938 ironlake_enable_shared_dpll(intel_crtc
);
2940 if (HAS_PCH_CPT(dev
)) {
2943 temp
= I915_READ(PCH_DPLL_SEL
);
2944 temp
|= TRANS_DPLL_ENABLE(pipe
);
2945 sel
= TRANS_DPLLB_SEL(pipe
);
2946 if (intel_crtc
->config
.shared_dpll
== DPLL_ID_PCH_PLL_B
)
2950 I915_WRITE(PCH_DPLL_SEL
, temp
);
2953 /* set transcoder timing, panel must allow it */
2954 assert_panel_unlocked(dev_priv
, pipe
);
2955 ironlake_pch_transcoder_set_timings(intel_crtc
, pipe
);
2957 intel_fdi_normal_train(crtc
);
2959 /* For PCH DP, enable TRANS_DP_CTL */
2960 if (HAS_PCH_CPT(dev
) &&
2961 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
2962 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
2963 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
2964 reg
= TRANS_DP_CTL(pipe
);
2965 temp
= I915_READ(reg
);
2966 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
2967 TRANS_DP_SYNC_MASK
|
2969 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
2970 TRANS_DP_ENH_FRAMING
);
2971 temp
|= bpc
<< 9; /* same format but at 11:9 */
2973 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
2974 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
2975 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
2976 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
2978 switch (intel_trans_dp_port_sel(crtc
)) {
2980 temp
|= TRANS_DP_PORT_SEL_B
;
2983 temp
|= TRANS_DP_PORT_SEL_C
;
2986 temp
|= TRANS_DP_PORT_SEL_D
;
2992 I915_WRITE(reg
, temp
);
2995 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
2998 static void lpt_pch_enable(struct drm_crtc
*crtc
)
3000 struct drm_device
*dev
= crtc
->dev
;
3001 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3002 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3003 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
3005 assert_pch_transcoder_disabled(dev_priv
, TRANSCODER_A
);
3007 lpt_program_iclkip(crtc
);
3009 /* Set transcoder timing. */
3010 ironlake_pch_transcoder_set_timings(intel_crtc
, PIPE_A
);
3012 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
3015 static void intel_put_shared_dpll(struct intel_crtc
*crtc
)
3017 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3022 if (pll
->refcount
== 0) {
3023 WARN(1, "bad %s refcount\n", pll
->name
);
3027 if (--pll
->refcount
== 0) {
3029 WARN_ON(pll
->active
);
3032 crtc
->config
.shared_dpll
= DPLL_ID_PRIVATE
;
3035 static struct intel_shared_dpll
*intel_get_shared_dpll(struct intel_crtc
*crtc
, u32 dpll
, u32 fp
)
3037 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
3038 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3039 enum intel_dpll_id i
;
3042 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3043 crtc
->base
.base
.id
, pll
->name
);
3044 intel_put_shared_dpll(crtc
);
3047 if (HAS_PCH_IBX(dev_priv
->dev
)) {
3048 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3050 pll
= &dev_priv
->shared_dplls
[i
];
3052 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3053 crtc
->base
.base
.id
, pll
->name
);
3058 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3059 pll
= &dev_priv
->shared_dplls
[i
];
3061 /* Only want to check enabled timings first */
3062 if (pll
->refcount
== 0)
3065 if (dpll
== (I915_READ(PCH_DPLL(pll
->id
)) & 0x7fffffff) &&
3066 fp
== I915_READ(PCH_FP0(pll
->id
))) {
3067 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3069 pll
->name
, pll
->refcount
, pll
->active
);
3075 /* Ok no matching timings, maybe there's a free one? */
3076 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3077 pll
= &dev_priv
->shared_dplls
[i
];
3078 if (pll
->refcount
== 0) {
3079 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3080 crtc
->base
.base
.id
, pll
->name
);
3088 crtc
->config
.shared_dpll
= i
;
3089 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll
->name
,
3090 pipe_name(crtc
->pipe
));
3091 if (pll
->active
== 0) {
3092 DRM_DEBUG_DRIVER("setting up %s\n", pll
->name
);
3094 assert_shared_dpll_disabled(dev_priv
, pll
);
3096 /* Wait for the clocks to stabilize before rewriting the regs */
3097 I915_WRITE(PCH_DPLL(pll
->id
), dpll
& ~DPLL_VCO_ENABLE
);
3098 POSTING_READ(PCH_DPLL(pll
->id
));
3101 I915_WRITE(PCH_FP0(pll
->id
), fp
);
3102 I915_WRITE(PCH_DPLL(pll
->id
), dpll
& ~DPLL_VCO_ENABLE
);
3109 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
3111 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3112 int dslreg
= PIPEDSL(pipe
);
3115 temp
= I915_READ(dslreg
);
3117 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
3118 if (wait_for(I915_READ(dslreg
) != temp
, 5))
3119 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
3123 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
3125 struct drm_device
*dev
= crtc
->base
.dev
;
3126 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3127 int pipe
= crtc
->pipe
;
3129 if (crtc
->config
.pch_pfit
.size
) {
3130 /* Force use of hard-coded filter coefficients
3131 * as some pre-programmed values are broken,
3134 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
3135 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
3136 PF_PIPE_SEL_IVB(pipe
));
3138 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
3139 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
.pch_pfit
.pos
);
3140 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
.pch_pfit
.size
);
3144 static void intel_enable_planes(struct drm_crtc
*crtc
)
3146 struct drm_device
*dev
= crtc
->dev
;
3147 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
3148 struct intel_plane
*intel_plane
;
3150 list_for_each_entry(intel_plane
, &dev
->mode_config
.plane_list
, base
.head
)
3151 if (intel_plane
->pipe
== pipe
)
3152 intel_plane_restore(&intel_plane
->base
);
3155 static void intel_disable_planes(struct drm_crtc
*crtc
)
3157 struct drm_device
*dev
= crtc
->dev
;
3158 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
3159 struct intel_plane
*intel_plane
;
3161 list_for_each_entry(intel_plane
, &dev
->mode_config
.plane_list
, base
.head
)
3162 if (intel_plane
->pipe
== pipe
)
3163 intel_plane_disable(&intel_plane
->base
);
3166 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
3168 struct drm_device
*dev
= crtc
->dev
;
3169 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3170 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3171 struct intel_encoder
*encoder
;
3172 int pipe
= intel_crtc
->pipe
;
3173 int plane
= intel_crtc
->plane
;
3176 WARN_ON(!crtc
->enabled
);
3178 if (intel_crtc
->active
)
3181 intel_crtc
->active
= true;
3183 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
3184 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
3186 intel_update_watermarks(dev
);
3188 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
3189 temp
= I915_READ(PCH_LVDS
);
3190 if ((temp
& LVDS_PORT_EN
) == 0)
3191 I915_WRITE(PCH_LVDS
, temp
| LVDS_PORT_EN
);
3195 if (intel_crtc
->config
.has_pch_encoder
) {
3196 /* Note: FDI PLL enabling _must_ be done before we enable the
3197 * cpu pipes, hence this is separate from all the other fdi/pch
3199 ironlake_fdi_pll_enable(intel_crtc
);
3201 assert_fdi_tx_disabled(dev_priv
, pipe
);
3202 assert_fdi_rx_disabled(dev_priv
, pipe
);
3205 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3206 if (encoder
->pre_enable
)
3207 encoder
->pre_enable(encoder
);
3209 /* Enable panel fitting for LVDS */
3210 ironlake_pfit_enable(intel_crtc
);
3213 * On ILK+ LUT must be loaded before the pipe is running but with
3216 intel_crtc_load_lut(crtc
);
3218 intel_enable_pipe(dev_priv
, pipe
,
3219 intel_crtc
->config
.has_pch_encoder
);
3220 intel_enable_plane(dev_priv
, plane
, pipe
);
3221 intel_enable_planes(crtc
);
3222 intel_crtc_update_cursor(crtc
, true);
3224 if (intel_crtc
->config
.has_pch_encoder
)
3225 ironlake_pch_enable(crtc
);
3227 mutex_lock(&dev
->struct_mutex
);
3228 intel_update_fbc(dev
);
3229 mutex_unlock(&dev
->struct_mutex
);
3231 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3232 encoder
->enable(encoder
);
3234 if (HAS_PCH_CPT(dev
))
3235 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
3238 * There seems to be a race in PCH platform hw (at least on some
3239 * outputs) where an enabled pipe still completes any pageflip right
3240 * away (as if the pipe is off) instead of waiting for vblank. As soon
3241 * as the first vblank happend, everything works as expected. Hence just
3242 * wait for one vblank before returning to avoid strange things
3245 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3248 /* IPS only exists on ULT machines and is tied to pipe A. */
3249 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
3251 return IS_ULT(crtc
->base
.dev
) && crtc
->pipe
== PIPE_A
;
3254 static void hsw_enable_ips(struct intel_crtc
*crtc
)
3256 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
3258 if (!crtc
->config
.ips_enabled
)
3261 /* We can only enable IPS after we enable a plane and wait for a vblank.
3262 * We guarantee that the plane is enabled by calling intel_enable_ips
3263 * only after intel_enable_plane. And intel_enable_plane already waits
3264 * for a vblank, so all we need to do here is to enable the IPS bit. */
3265 assert_plane_enabled(dev_priv
, crtc
->plane
);
3266 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
3269 static void hsw_disable_ips(struct intel_crtc
*crtc
)
3271 struct drm_device
*dev
= crtc
->base
.dev
;
3272 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3274 if (!crtc
->config
.ips_enabled
)
3277 assert_plane_enabled(dev_priv
, crtc
->plane
);
3278 I915_WRITE(IPS_CTL
, 0);
3280 /* We need to wait for a vblank before we can disable the plane. */
3281 intel_wait_for_vblank(dev
, crtc
->pipe
);
3284 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
3286 struct drm_device
*dev
= crtc
->dev
;
3287 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3288 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3289 struct intel_encoder
*encoder
;
3290 int pipe
= intel_crtc
->pipe
;
3291 int plane
= intel_crtc
->plane
;
3293 WARN_ON(!crtc
->enabled
);
3295 if (intel_crtc
->active
)
3298 intel_crtc
->active
= true;
3300 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
3301 if (intel_crtc
->config
.has_pch_encoder
)
3302 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
3304 intel_update_watermarks(dev
);
3306 if (intel_crtc
->config
.has_pch_encoder
)
3307 dev_priv
->display
.fdi_link_train(crtc
);
3309 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3310 if (encoder
->pre_enable
)
3311 encoder
->pre_enable(encoder
);
3313 intel_ddi_enable_pipe_clock(intel_crtc
);
3315 /* Enable panel fitting for eDP */
3316 ironlake_pfit_enable(intel_crtc
);
3319 * On ILK+ LUT must be loaded before the pipe is running but with
3322 intel_crtc_load_lut(crtc
);
3324 intel_ddi_set_pipe_settings(crtc
);
3325 intel_ddi_enable_transcoder_func(crtc
);
3327 intel_enable_pipe(dev_priv
, pipe
,
3328 intel_crtc
->config
.has_pch_encoder
);
3329 intel_enable_plane(dev_priv
, plane
, pipe
);
3330 intel_enable_planes(crtc
);
3331 intel_crtc_update_cursor(crtc
, true);
3333 hsw_enable_ips(intel_crtc
);
3335 if (intel_crtc
->config
.has_pch_encoder
)
3336 lpt_pch_enable(crtc
);
3338 mutex_lock(&dev
->struct_mutex
);
3339 intel_update_fbc(dev
);
3340 mutex_unlock(&dev
->struct_mutex
);
3342 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3343 encoder
->enable(encoder
);
3346 * There seems to be a race in PCH platform hw (at least on some
3347 * outputs) where an enabled pipe still completes any pageflip right
3348 * away (as if the pipe is off) instead of waiting for vblank. As soon
3349 * as the first vblank happend, everything works as expected. Hence just
3350 * wait for one vblank before returning to avoid strange things
3353 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3356 static void ironlake_pfit_disable(struct intel_crtc
*crtc
)
3358 struct drm_device
*dev
= crtc
->base
.dev
;
3359 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3360 int pipe
= crtc
->pipe
;
3362 /* To avoid upsetting the power well on haswell only disable the pfit if
3363 * it's in use. The hw state code will make sure we get this right. */
3364 if (crtc
->config
.pch_pfit
.size
) {
3365 I915_WRITE(PF_CTL(pipe
), 0);
3366 I915_WRITE(PF_WIN_POS(pipe
), 0);
3367 I915_WRITE(PF_WIN_SZ(pipe
), 0);
3371 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
3373 struct drm_device
*dev
= crtc
->dev
;
3374 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3375 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3376 struct intel_encoder
*encoder
;
3377 int pipe
= intel_crtc
->pipe
;
3378 int plane
= intel_crtc
->plane
;
3382 if (!intel_crtc
->active
)
3385 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3386 encoder
->disable(encoder
);
3388 intel_crtc_wait_for_pending_flips(crtc
);
3389 drm_vblank_off(dev
, pipe
);
3391 if (dev_priv
->cfb_plane
== plane
)
3392 intel_disable_fbc(dev
);
3394 intel_crtc_update_cursor(crtc
, false);
3395 intel_disable_planes(crtc
);
3396 intel_disable_plane(dev_priv
, plane
, pipe
);
3398 if (intel_crtc
->config
.has_pch_encoder
)
3399 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, false);
3401 intel_disable_pipe(dev_priv
, pipe
);
3403 ironlake_pfit_disable(intel_crtc
);
3405 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3406 if (encoder
->post_disable
)
3407 encoder
->post_disable(encoder
);
3409 if (intel_crtc
->config
.has_pch_encoder
) {
3410 ironlake_fdi_disable(crtc
);
3412 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
3413 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
3415 if (HAS_PCH_CPT(dev
)) {
3416 /* disable TRANS_DP_CTL */
3417 reg
= TRANS_DP_CTL(pipe
);
3418 temp
= I915_READ(reg
);
3419 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
3420 TRANS_DP_PORT_SEL_MASK
);
3421 temp
|= TRANS_DP_PORT_SEL_NONE
;
3422 I915_WRITE(reg
, temp
);
3424 /* disable DPLL_SEL */
3425 temp
= I915_READ(PCH_DPLL_SEL
);
3426 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
3427 I915_WRITE(PCH_DPLL_SEL
, temp
);
3430 /* disable PCH DPLL */
3431 intel_disable_shared_dpll(intel_crtc
);
3433 ironlake_fdi_pll_disable(intel_crtc
);
3436 intel_crtc
->active
= false;
3437 intel_update_watermarks(dev
);
3439 mutex_lock(&dev
->struct_mutex
);
3440 intel_update_fbc(dev
);
3441 mutex_unlock(&dev
->struct_mutex
);
3444 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
3446 struct drm_device
*dev
= crtc
->dev
;
3447 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3448 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3449 struct intel_encoder
*encoder
;
3450 int pipe
= intel_crtc
->pipe
;
3451 int plane
= intel_crtc
->plane
;
3452 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
3454 if (!intel_crtc
->active
)
3457 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3458 encoder
->disable(encoder
);
3460 intel_crtc_wait_for_pending_flips(crtc
);
3461 drm_vblank_off(dev
, pipe
);
3463 /* FBC must be disabled before disabling the plane on HSW. */
3464 if (dev_priv
->cfb_plane
== plane
)
3465 intel_disable_fbc(dev
);
3467 hsw_disable_ips(intel_crtc
);
3469 intel_crtc_update_cursor(crtc
, false);
3470 intel_disable_planes(crtc
);
3471 intel_disable_plane(dev_priv
, plane
, pipe
);
3473 if (intel_crtc
->config
.has_pch_encoder
)
3474 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, false);
3475 intel_disable_pipe(dev_priv
, pipe
);
3477 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
3479 ironlake_pfit_disable(intel_crtc
);
3481 intel_ddi_disable_pipe_clock(intel_crtc
);
3483 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3484 if (encoder
->post_disable
)
3485 encoder
->post_disable(encoder
);
3487 if (intel_crtc
->config
.has_pch_encoder
) {
3488 lpt_disable_pch_transcoder(dev_priv
);
3489 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
3490 intel_ddi_fdi_disable(crtc
);
3493 intel_crtc
->active
= false;
3494 intel_update_watermarks(dev
);
3496 mutex_lock(&dev
->struct_mutex
);
3497 intel_update_fbc(dev
);
3498 mutex_unlock(&dev
->struct_mutex
);
3501 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
3503 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3504 intel_put_shared_dpll(intel_crtc
);
3507 static void haswell_crtc_off(struct drm_crtc
*crtc
)
3509 intel_ddi_put_crtc_pll(crtc
);
3512 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
3514 if (!enable
&& intel_crtc
->overlay
) {
3515 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3516 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3518 mutex_lock(&dev
->struct_mutex
);
3519 dev_priv
->mm
.interruptible
= false;
3520 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
3521 dev_priv
->mm
.interruptible
= true;
3522 mutex_unlock(&dev
->struct_mutex
);
3525 /* Let userspace switch the overlay on again. In most cases userspace
3526 * has to recompute where to put it anyway.
3531 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3532 * cursor plane briefly if not already running after enabling the display
3534 * This workaround avoids occasional blank screens when self refresh is
3538 g4x_fixup_plane(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
3540 u32 cntl
= I915_READ(CURCNTR(pipe
));
3542 if ((cntl
& CURSOR_MODE
) == 0) {
3543 u32 fw_bcl_self
= I915_READ(FW_BLC_SELF
);
3545 I915_WRITE(FW_BLC_SELF
, fw_bcl_self
& ~FW_BLC_SELF_EN
);
3546 I915_WRITE(CURCNTR(pipe
), CURSOR_MODE_64_ARGB_AX
);
3547 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
3548 I915_WRITE(CURCNTR(pipe
), cntl
);
3549 I915_WRITE(CURBASE(pipe
), I915_READ(CURBASE(pipe
)));
3550 I915_WRITE(FW_BLC_SELF
, fw_bcl_self
);
3554 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
3556 struct drm_device
*dev
= crtc
->base
.dev
;
3557 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3558 struct intel_crtc_config
*pipe_config
= &crtc
->config
;
3560 if (!crtc
->config
.gmch_pfit
.control
)
3564 * The panel fitter should only be adjusted whilst the pipe is disabled,
3565 * according to register description and PRM.
3567 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
3568 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
3570 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
3571 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
3573 /* Border color in case we don't scale up to the full screen. Black by
3574 * default, change to something else for debugging. */
3575 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
3578 static void valleyview_crtc_enable(struct drm_crtc
*crtc
)
3580 struct drm_device
*dev
= crtc
->dev
;
3581 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3582 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3583 struct intel_encoder
*encoder
;
3584 int pipe
= intel_crtc
->pipe
;
3585 int plane
= intel_crtc
->plane
;
3587 WARN_ON(!crtc
->enabled
);
3589 if (intel_crtc
->active
)
3592 intel_crtc
->active
= true;
3593 intel_update_watermarks(dev
);
3595 mutex_lock(&dev_priv
->dpio_lock
);
3597 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3598 if (encoder
->pre_pll_enable
)
3599 encoder
->pre_pll_enable(encoder
);
3601 intel_enable_pll(dev_priv
, pipe
);
3603 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3604 if (encoder
->pre_enable
)
3605 encoder
->pre_enable(encoder
);
3607 /* VLV wants encoder enabling _before_ the pipe is up. */
3608 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3609 encoder
->enable(encoder
);
3611 /* Enable panel fitting for eDP */
3612 i9xx_pfit_enable(intel_crtc
);
3614 intel_crtc_load_lut(crtc
);
3616 intel_enable_pipe(dev_priv
, pipe
, false);
3617 intel_enable_plane(dev_priv
, plane
, pipe
);
3618 intel_enable_planes(crtc
);
3619 intel_crtc_update_cursor(crtc
, true);
3621 intel_update_fbc(dev
);
3623 mutex_unlock(&dev_priv
->dpio_lock
);
3626 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
3628 struct drm_device
*dev
= crtc
->dev
;
3629 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3630 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3631 struct intel_encoder
*encoder
;
3632 int pipe
= intel_crtc
->pipe
;
3633 int plane
= intel_crtc
->plane
;
3635 WARN_ON(!crtc
->enabled
);
3637 if (intel_crtc
->active
)
3640 intel_crtc
->active
= true;
3641 intel_update_watermarks(dev
);
3643 intel_enable_pll(dev_priv
, pipe
);
3645 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3646 if (encoder
->pre_enable
)
3647 encoder
->pre_enable(encoder
);
3649 /* Enable panel fitting for LVDS */
3650 i9xx_pfit_enable(intel_crtc
);
3652 intel_crtc_load_lut(crtc
);
3654 intel_enable_pipe(dev_priv
, pipe
, false);
3655 intel_enable_plane(dev_priv
, plane
, pipe
);
3656 intel_enable_planes(crtc
);
3657 /* The fixup needs to happen before cursor is enabled */
3659 g4x_fixup_plane(dev_priv
, pipe
);
3660 intel_crtc_update_cursor(crtc
, true);
3662 /* Give the overlay scaler a chance to enable if it's on this pipe */
3663 intel_crtc_dpms_overlay(intel_crtc
, true);
3665 intel_update_fbc(dev
);
3667 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3668 encoder
->enable(encoder
);
3671 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
3673 struct drm_device
*dev
= crtc
->base
.dev
;
3674 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3676 if (!crtc
->config
.gmch_pfit
.control
)
3679 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
3681 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3682 I915_READ(PFIT_CONTROL
));
3683 I915_WRITE(PFIT_CONTROL
, 0);
3686 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
3688 struct drm_device
*dev
= crtc
->dev
;
3689 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3690 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3691 struct intel_encoder
*encoder
;
3692 int pipe
= intel_crtc
->pipe
;
3693 int plane
= intel_crtc
->plane
;
3695 if (!intel_crtc
->active
)
3698 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3699 encoder
->disable(encoder
);
3701 /* Give the overlay scaler a chance to disable if it's on this pipe */
3702 intel_crtc_wait_for_pending_flips(crtc
);
3703 drm_vblank_off(dev
, pipe
);
3705 if (dev_priv
->cfb_plane
== plane
)
3706 intel_disable_fbc(dev
);
3708 intel_crtc_dpms_overlay(intel_crtc
, false);
3709 intel_crtc_update_cursor(crtc
, false);
3710 intel_disable_planes(crtc
);
3711 intel_disable_plane(dev_priv
, plane
, pipe
);
3713 intel_disable_pipe(dev_priv
, pipe
);
3715 i9xx_pfit_disable(intel_crtc
);
3717 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3718 if (encoder
->post_disable
)
3719 encoder
->post_disable(encoder
);
3721 intel_disable_pll(dev_priv
, pipe
);
3723 intel_crtc
->active
= false;
3724 intel_update_fbc(dev
);
3725 intel_update_watermarks(dev
);
3728 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
3732 static void intel_crtc_update_sarea(struct drm_crtc
*crtc
,
3735 struct drm_device
*dev
= crtc
->dev
;
3736 struct drm_i915_master_private
*master_priv
;
3737 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3738 int pipe
= intel_crtc
->pipe
;
3740 if (!dev
->primary
->master
)
3743 master_priv
= dev
->primary
->master
->driver_priv
;
3744 if (!master_priv
->sarea_priv
)
3749 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3750 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3753 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3754 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3757 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe
));
3763 * Sets the power management mode of the pipe and plane.
3765 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
3767 struct drm_device
*dev
= crtc
->dev
;
3768 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3769 struct intel_encoder
*intel_encoder
;
3770 bool enable
= false;
3772 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
3773 enable
|= intel_encoder
->connectors_active
;
3776 dev_priv
->display
.crtc_enable(crtc
);
3778 dev_priv
->display
.crtc_disable(crtc
);
3780 intel_crtc_update_sarea(crtc
, enable
);
3783 static void intel_crtc_disable(struct drm_crtc
*crtc
)
3785 struct drm_device
*dev
= crtc
->dev
;
3786 struct drm_connector
*connector
;
3787 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3788 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3790 /* crtc should still be enabled when we disable it. */
3791 WARN_ON(!crtc
->enabled
);
3793 dev_priv
->display
.crtc_disable(crtc
);
3794 intel_crtc
->eld_vld
= false;
3795 intel_crtc_update_sarea(crtc
, false);
3796 dev_priv
->display
.off(crtc
);
3798 assert_plane_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->plane
);
3799 assert_pipe_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->pipe
);
3802 mutex_lock(&dev
->struct_mutex
);
3803 intel_unpin_fb_obj(to_intel_framebuffer(crtc
->fb
)->obj
);
3804 mutex_unlock(&dev
->struct_mutex
);
3808 /* Update computed state. */
3809 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
3810 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
3813 if (connector
->encoder
->crtc
!= crtc
)
3816 connector
->dpms
= DRM_MODE_DPMS_OFF
;
3817 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
3821 void intel_modeset_disable(struct drm_device
*dev
)
3823 struct drm_crtc
*crtc
;
3825 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
3827 intel_crtc_disable(crtc
);
3831 void intel_encoder_destroy(struct drm_encoder
*encoder
)
3833 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
3835 drm_encoder_cleanup(encoder
);
3836 kfree(intel_encoder
);
3839 /* Simple dpms helper for encodres with just one connector, no cloning and only
3840 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3841 * state of the entire output pipe. */
3842 void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
3844 if (mode
== DRM_MODE_DPMS_ON
) {
3845 encoder
->connectors_active
= true;
3847 intel_crtc_update_dpms(encoder
->base
.crtc
);
3849 encoder
->connectors_active
= false;
3851 intel_crtc_update_dpms(encoder
->base
.crtc
);
3855 /* Cross check the actual hw state with our own modeset state tracking (and it's
3856 * internal consistency). */
3857 static void intel_connector_check_state(struct intel_connector
*connector
)
3859 if (connector
->get_hw_state(connector
)) {
3860 struct intel_encoder
*encoder
= connector
->encoder
;
3861 struct drm_crtc
*crtc
;
3862 bool encoder_enabled
;
3865 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3866 connector
->base
.base
.id
,
3867 drm_get_connector_name(&connector
->base
));
3869 WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
3870 "wrong connector dpms state\n");
3871 WARN(connector
->base
.encoder
!= &encoder
->base
,
3872 "active connector not linked to encoder\n");
3873 WARN(!encoder
->connectors_active
,
3874 "encoder->connectors_active not set\n");
3876 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
3877 WARN(!encoder_enabled
, "encoder not enabled\n");
3878 if (WARN_ON(!encoder
->base
.crtc
))
3881 crtc
= encoder
->base
.crtc
;
3883 WARN(!crtc
->enabled
, "crtc not enabled\n");
3884 WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
3885 WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
3886 "encoder active on the wrong pipe\n");
3890 /* Even simpler default implementation, if there's really no special case to
3892 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
3894 struct intel_encoder
*encoder
= intel_attached_encoder(connector
);
3896 /* All the simple cases only support two dpms states. */
3897 if (mode
!= DRM_MODE_DPMS_ON
)
3898 mode
= DRM_MODE_DPMS_OFF
;
3900 if (mode
== connector
->dpms
)
3903 connector
->dpms
= mode
;
3905 /* Only need to change hw state when actually enabled */
3906 if (encoder
->base
.crtc
)
3907 intel_encoder_dpms(encoder
, mode
);
3909 WARN_ON(encoder
->connectors_active
!= false);
3911 intel_modeset_check_state(connector
->dev
);
3914 /* Simple connector->get_hw_state implementation for encoders that support only
3915 * one connector and no cloning and hence the encoder state determines the state
3916 * of the connector. */
3917 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
3920 struct intel_encoder
*encoder
= connector
->encoder
;
3922 return encoder
->get_hw_state(encoder
, &pipe
);
3925 static bool ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
3926 struct intel_crtc_config
*pipe_config
)
3928 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3929 struct intel_crtc
*pipe_B_crtc
=
3930 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
3932 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3933 pipe_name(pipe
), pipe_config
->fdi_lanes
);
3934 if (pipe_config
->fdi_lanes
> 4) {
3935 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3936 pipe_name(pipe
), pipe_config
->fdi_lanes
);
3940 if (IS_HASWELL(dev
)) {
3941 if (pipe_config
->fdi_lanes
> 2) {
3942 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3943 pipe_config
->fdi_lanes
);
3950 if (INTEL_INFO(dev
)->num_pipes
== 2)
3953 /* Ivybridge 3 pipe is really complicated */
3958 if (dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]->enabled
&&
3959 pipe_config
->fdi_lanes
> 2) {
3960 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3961 pipe_name(pipe
), pipe_config
->fdi_lanes
);
3966 if (!pipe_has_enabled_pch(pipe_B_crtc
) ||
3967 pipe_B_crtc
->config
.fdi_lanes
<= 2) {
3968 if (pipe_config
->fdi_lanes
> 2) {
3969 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3970 pipe_name(pipe
), pipe_config
->fdi_lanes
);
3974 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
3984 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
3985 struct intel_crtc_config
*pipe_config
)
3987 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3988 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
3989 int lane
, link_bw
, fdi_dotclock
;
3990 bool setup_ok
, needs_recompute
= false;
3993 /* FDI is a binary signal running at ~2.7GHz, encoding
3994 * each output octet as 10 bits. The actual frequency
3995 * is stored as a divider into a 100MHz clock, and the
3996 * mode pixel clock is stored in units of 1KHz.
3997 * Hence the bw of each lane in terms of the mode signal
4000 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
4002 fdi_dotclock
= adjusted_mode
->clock
;
4003 fdi_dotclock
/= pipe_config
->pixel_multiplier
;
4005 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
4006 pipe_config
->pipe_bpp
);
4008 pipe_config
->fdi_lanes
= lane
;
4010 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
4011 link_bw
, &pipe_config
->fdi_m_n
);
4013 setup_ok
= ironlake_check_fdi_lanes(intel_crtc
->base
.dev
,
4014 intel_crtc
->pipe
, pipe_config
);
4015 if (!setup_ok
&& pipe_config
->pipe_bpp
> 6*3) {
4016 pipe_config
->pipe_bpp
-= 2*3;
4017 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4018 pipe_config
->pipe_bpp
);
4019 needs_recompute
= true;
4020 pipe_config
->bw_constrained
= true;
4025 if (needs_recompute
)
4028 return setup_ok
? 0 : -EINVAL
;
4031 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
4032 struct intel_crtc_config
*pipe_config
)
4034 pipe_config
->ips_enabled
= i915_enable_ips
&&
4035 hsw_crtc_supports_ips(crtc
) &&
4036 pipe_config
->pipe_bpp
== 24;
4039 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
4040 struct intel_crtc_config
*pipe_config
)
4042 struct drm_device
*dev
= crtc
->base
.dev
;
4043 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
4045 if (HAS_PCH_SPLIT(dev
)) {
4046 /* FDI link clock is fixed at 2.7G */
4047 if (pipe_config
->requested_mode
.clock
* 3
4048 > IRONLAKE_FDI_FREQ
* 4)
4052 /* All interlaced capable intel hw wants timings in frames. Note though
4053 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4054 * timings, so we need to be careful not to clobber these.*/
4055 if (!pipe_config
->timings_set
)
4056 drm_mode_set_crtcinfo(adjusted_mode
, 0);
4058 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4059 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4061 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
4062 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
4065 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) && pipe_config
->pipe_bpp
> 10*3) {
4066 pipe_config
->pipe_bpp
= 10*3; /* 12bpc is gen5+ */
4067 } else if (INTEL_INFO(dev
)->gen
<= 4 && pipe_config
->pipe_bpp
> 8*3) {
4068 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4070 pipe_config
->pipe_bpp
= 8*3;
4073 if (IS_HASWELL(dev
))
4074 hsw_compute_ips_config(crtc
, pipe_config
);
4076 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4077 * clock survives for now. */
4078 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
4079 pipe_config
->shared_dpll
= crtc
->config
.shared_dpll
;
4081 if (pipe_config
->has_pch_encoder
)
4082 return ironlake_fdi_compute_config(crtc
, pipe_config
);
4087 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
4089 return 400000; /* FIXME */
4092 static int i945_get_display_clock_speed(struct drm_device
*dev
)
4097 static int i915_get_display_clock_speed(struct drm_device
*dev
)
4102 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
4107 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
4111 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
4113 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
4116 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
4117 case GC_DISPLAY_CLOCK_333_MHZ
:
4120 case GC_DISPLAY_CLOCK_190_200_MHZ
:
4126 static int i865_get_display_clock_speed(struct drm_device
*dev
)
4131 static int i855_get_display_clock_speed(struct drm_device
*dev
)
4134 /* Assume that the hardware is in the high speed state. This
4135 * should be the default.
4137 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
4138 case GC_CLOCK_133_200
:
4139 case GC_CLOCK_100_200
:
4141 case GC_CLOCK_166_250
:
4143 case GC_CLOCK_100_133
:
4147 /* Shouldn't happen */
4151 static int i830_get_display_clock_speed(struct drm_device
*dev
)
4157 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
4159 while (*num
> DATA_LINK_M_N_MASK
||
4160 *den
> DATA_LINK_M_N_MASK
) {
4166 static void compute_m_n(unsigned int m
, unsigned int n
,
4167 uint32_t *ret_m
, uint32_t *ret_n
)
4169 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
4170 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
4171 intel_reduce_m_n_ratio(ret_m
, ret_n
);
4175 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
4176 int pixel_clock
, int link_clock
,
4177 struct intel_link_m_n
*m_n
)
4181 compute_m_n(bits_per_pixel
* pixel_clock
,
4182 link_clock
* nlanes
* 8,
4183 &m_n
->gmch_m
, &m_n
->gmch_n
);
4185 compute_m_n(pixel_clock
, link_clock
,
4186 &m_n
->link_m
, &m_n
->link_n
);
4189 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
4191 if (i915_panel_use_ssc
>= 0)
4192 return i915_panel_use_ssc
!= 0;
4193 return dev_priv
->vbt
.lvds_use_ssc
4194 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
4197 static int vlv_get_refclk(struct drm_crtc
*crtc
)
4199 struct drm_device
*dev
= crtc
->dev
;
4200 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4201 int refclk
= 27000; /* for DP & HDMI */
4203 return 100000; /* only one validated so far */
4205 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
4207 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
4208 if (intel_panel_use_ssc(dev_priv
))
4212 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
)) {
4219 static int i9xx_get_refclk(struct drm_crtc
*crtc
, int num_connectors
)
4221 struct drm_device
*dev
= crtc
->dev
;
4222 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4225 if (IS_VALLEYVIEW(dev
)) {
4226 refclk
= vlv_get_refclk(crtc
);
4227 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4228 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
4229 refclk
= dev_priv
->vbt
.lvds_ssc_freq
* 1000;
4230 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4232 } else if (!IS_GEN2(dev
)) {
4241 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
4243 return (1 << dpll
->n
) << 16 | dpll
->m1
<< 8 | dpll
->m2
;
4246 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
4248 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
4251 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
4252 intel_clock_t
*reduced_clock
)
4254 struct drm_device
*dev
= crtc
->base
.dev
;
4255 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4256 int pipe
= crtc
->pipe
;
4259 if (IS_PINEVIEW(dev
)) {
4260 fp
= pnv_dpll_compute_fp(&crtc
->config
.dpll
);
4262 fp2
= pnv_dpll_compute_fp(reduced_clock
);
4264 fp
= i9xx_dpll_compute_fp(&crtc
->config
.dpll
);
4266 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
4269 I915_WRITE(FP0(pipe
), fp
);
4271 crtc
->lowfreq_avail
= false;
4272 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4273 reduced_clock
&& i915_powersave
) {
4274 I915_WRITE(FP1(pipe
), fp2
);
4275 crtc
->lowfreq_avail
= true;
4277 I915_WRITE(FP1(pipe
), fp
);
4281 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
)
4286 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4287 * and set it to a reasonable value instead.
4289 reg_val
= vlv_dpio_read(dev_priv
, DPIO_IREF(1));
4290 reg_val
&= 0xffffff00;
4291 reg_val
|= 0x00000030;
4292 vlv_dpio_write(dev_priv
, DPIO_IREF(1), reg_val
);
4294 reg_val
= vlv_dpio_read(dev_priv
, DPIO_CALIBRATION
);
4295 reg_val
&= 0x8cffffff;
4296 reg_val
= 0x8c000000;
4297 vlv_dpio_write(dev_priv
, DPIO_CALIBRATION
, reg_val
);
4299 reg_val
= vlv_dpio_read(dev_priv
, DPIO_IREF(1));
4300 reg_val
&= 0xffffff00;
4301 vlv_dpio_write(dev_priv
, DPIO_IREF(1), reg_val
);
4303 reg_val
= vlv_dpio_read(dev_priv
, DPIO_CALIBRATION
);
4304 reg_val
&= 0x00ffffff;
4305 reg_val
|= 0xb0000000;
4306 vlv_dpio_write(dev_priv
, DPIO_CALIBRATION
, reg_val
);
4309 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
4310 struct intel_link_m_n
*m_n
)
4312 struct drm_device
*dev
= crtc
->base
.dev
;
4313 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4314 int pipe
= crtc
->pipe
;
4316 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
4317 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
4318 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
4319 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
4322 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
4323 struct intel_link_m_n
*m_n
)
4325 struct drm_device
*dev
= crtc
->base
.dev
;
4326 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4327 int pipe
= crtc
->pipe
;
4328 enum transcoder transcoder
= crtc
->config
.cpu_transcoder
;
4330 if (INTEL_INFO(dev
)->gen
>= 5) {
4331 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
4332 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
4333 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
4334 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
4336 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
4337 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
4338 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
4339 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
4343 static void intel_dp_set_m_n(struct intel_crtc
*crtc
)
4345 if (crtc
->config
.has_pch_encoder
)
4346 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
4348 intel_cpu_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
4351 static void vlv_update_pll(struct intel_crtc
*crtc
)
4353 struct drm_device
*dev
= crtc
->base
.dev
;
4354 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4355 struct intel_encoder
*encoder
;
4356 int pipe
= crtc
->pipe
;
4358 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
4360 u32 coreclk
, reg_val
, dpll_md
;
4362 mutex_lock(&dev_priv
->dpio_lock
);
4364 is_hdmi
= intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
);
4366 bestn
= crtc
->config
.dpll
.n
;
4367 bestm1
= crtc
->config
.dpll
.m1
;
4368 bestm2
= crtc
->config
.dpll
.m2
;
4369 bestp1
= crtc
->config
.dpll
.p1
;
4370 bestp2
= crtc
->config
.dpll
.p2
;
4372 /* See eDP HDMI DPIO driver vbios notes doc */
4374 /* PLL B needs special handling */
4376 vlv_pllb_recal_opamp(dev_priv
);
4378 /* Set up Tx target for periodic Rcomp update */
4379 vlv_dpio_write(dev_priv
, DPIO_IREF_BCAST
, 0x0100000f);
4381 /* Disable target IRef on PLL */
4382 reg_val
= vlv_dpio_read(dev_priv
, DPIO_IREF_CTL(pipe
));
4383 reg_val
&= 0x00ffffff;
4384 vlv_dpio_write(dev_priv
, DPIO_IREF_CTL(pipe
), reg_val
);
4386 /* Disable fast lock */
4387 vlv_dpio_write(dev_priv
, DPIO_FASTCLK_DISABLE
, 0x610);
4389 /* Set idtafcrecal before PLL is enabled */
4390 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
4391 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
4392 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
4393 mdiv
|= (1 << DPIO_K_SHIFT
);
4396 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4397 * but we don't support that).
4398 * Note: don't use the DAC post divider as it seems unstable.
4400 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
4401 vlv_dpio_write(dev_priv
, DPIO_DIV(pipe
), mdiv
);
4403 mdiv
|= DPIO_ENABLE_CALIBRATION
;
4404 vlv_dpio_write(dev_priv
, DPIO_DIV(pipe
), mdiv
);
4406 /* Set HBR and RBR LPF coefficients */
4407 if (crtc
->config
.port_clock
== 162000 ||
4408 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
))
4409 vlv_dpio_write(dev_priv
, DPIO_LFP_COEFF(pipe
),
4412 vlv_dpio_write(dev_priv
, DPIO_LFP_COEFF(pipe
),
4415 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
) ||
4416 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
)) {
4417 /* Use SSC source */
4419 vlv_dpio_write(dev_priv
, DPIO_REFSFR(pipe
),
4422 vlv_dpio_write(dev_priv
, DPIO_REFSFR(pipe
),
4424 } else { /* HDMI or VGA */
4425 /* Use bend source */
4427 vlv_dpio_write(dev_priv
, DPIO_REFSFR(pipe
),
4430 vlv_dpio_write(dev_priv
, DPIO_REFSFR(pipe
),
4434 coreclk
= vlv_dpio_read(dev_priv
, DPIO_CORE_CLK(pipe
));
4435 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
4436 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
) ||
4437 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
))
4438 coreclk
|= 0x01000000;
4439 vlv_dpio_write(dev_priv
, DPIO_CORE_CLK(pipe
), coreclk
);
4441 vlv_dpio_write(dev_priv
, DPIO_PLL_CML(pipe
), 0x87871000);
4443 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
4444 if (encoder
->pre_pll_enable
)
4445 encoder
->pre_pll_enable(encoder
);
4447 /* Enable DPIO clock input */
4448 dpll
= DPLL_EXT_BUFFER_ENABLE_VLV
| DPLL_REFA_CLK_ENABLE_VLV
|
4449 DPLL_VGA_MODE_DIS
| DPLL_INTEGRATED_CLOCK_VLV
;
4451 dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
4453 dpll
|= DPLL_VCO_ENABLE
;
4454 I915_WRITE(DPLL(pipe
), dpll
);
4455 POSTING_READ(DPLL(pipe
));
4458 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
4459 DRM_ERROR("DPLL %d failed to lock\n", pipe
);
4461 dpll_md
= (crtc
->config
.pixel_multiplier
- 1)
4462 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4463 I915_WRITE(DPLL_MD(pipe
), dpll_md
);
4464 POSTING_READ(DPLL_MD(pipe
));
4466 if (crtc
->config
.has_dp_encoder
)
4467 intel_dp_set_m_n(crtc
);
4469 mutex_unlock(&dev_priv
->dpio_lock
);
4472 static void i9xx_update_pll(struct intel_crtc
*crtc
,
4473 intel_clock_t
*reduced_clock
,
4476 struct drm_device
*dev
= crtc
->base
.dev
;
4477 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4478 struct intel_encoder
*encoder
;
4479 int pipe
= crtc
->pipe
;
4482 struct dpll
*clock
= &crtc
->config
.dpll
;
4484 i9xx_update_pll_dividers(crtc
, reduced_clock
);
4486 is_sdvo
= intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_SDVO
) ||
4487 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
);
4489 dpll
= DPLL_VGA_MODE_DIS
;
4491 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
))
4492 dpll
|= DPLLB_MODE_LVDS
;
4494 dpll
|= DPLLB_MODE_DAC_SERIAL
;
4496 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
4497 dpll
|= (crtc
->config
.pixel_multiplier
- 1)
4498 << SDVO_MULTIPLIER_SHIFT_HIRES
;
4502 dpll
|= DPLL_DVO_HIGH_SPEED
;
4504 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
))
4505 dpll
|= DPLL_DVO_HIGH_SPEED
;
4507 /* compute bitmask from p1 value */
4508 if (IS_PINEVIEW(dev
))
4509 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
4511 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4512 if (IS_G4X(dev
) && reduced_clock
)
4513 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
4515 switch (clock
->p2
) {
4517 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
4520 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
4523 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
4526 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
4529 if (INTEL_INFO(dev
)->gen
>= 4)
4530 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
4532 if (crtc
->config
.sdvo_tv_clock
)
4533 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
4534 else if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4535 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4536 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4538 dpll
|= PLL_REF_INPUT_DREFCLK
;
4540 dpll
|= DPLL_VCO_ENABLE
;
4541 I915_WRITE(DPLL(pipe
), dpll
& ~DPLL_VCO_ENABLE
);
4542 POSTING_READ(DPLL(pipe
));
4545 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
4546 if (encoder
->pre_pll_enable
)
4547 encoder
->pre_pll_enable(encoder
);
4549 if (crtc
->config
.has_dp_encoder
)
4550 intel_dp_set_m_n(crtc
);
4552 I915_WRITE(DPLL(pipe
), dpll
);
4554 /* Wait for the clocks to stabilize. */
4555 POSTING_READ(DPLL(pipe
));
4558 if (INTEL_INFO(dev
)->gen
>= 4) {
4559 u32 dpll_md
= (crtc
->config
.pixel_multiplier
- 1)
4560 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4561 I915_WRITE(DPLL_MD(pipe
), dpll_md
);
4563 /* The pixel multiplier can only be updated once the
4564 * DPLL is enabled and the clocks are stable.
4566 * So write it again.
4568 I915_WRITE(DPLL(pipe
), dpll
);
4572 static void i8xx_update_pll(struct intel_crtc
*crtc
,
4573 intel_clock_t
*reduced_clock
,
4576 struct drm_device
*dev
= crtc
->base
.dev
;
4577 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4578 struct intel_encoder
*encoder
;
4579 int pipe
= crtc
->pipe
;
4581 struct dpll
*clock
= &crtc
->config
.dpll
;
4583 i9xx_update_pll_dividers(crtc
, reduced_clock
);
4585 dpll
= DPLL_VGA_MODE_DIS
;
4587 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
)) {
4588 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4591 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
4593 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4595 dpll
|= PLL_P2_DIVIDE_BY_4
;
4598 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4599 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4600 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4602 dpll
|= PLL_REF_INPUT_DREFCLK
;
4604 dpll
|= DPLL_VCO_ENABLE
;
4605 I915_WRITE(DPLL(pipe
), dpll
& ~DPLL_VCO_ENABLE
);
4606 POSTING_READ(DPLL(pipe
));
4609 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
4610 if (encoder
->pre_pll_enable
)
4611 encoder
->pre_pll_enable(encoder
);
4613 I915_WRITE(DPLL(pipe
), dpll
);
4615 /* Wait for the clocks to stabilize. */
4616 POSTING_READ(DPLL(pipe
));
4619 /* The pixel multiplier can only be updated once the
4620 * DPLL is enabled and the clocks are stable.
4622 * So write it again.
4624 I915_WRITE(DPLL(pipe
), dpll
);
4627 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
4629 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4630 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4631 enum pipe pipe
= intel_crtc
->pipe
;
4632 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
4633 struct drm_display_mode
*adjusted_mode
=
4634 &intel_crtc
->config
.adjusted_mode
;
4635 struct drm_display_mode
*mode
= &intel_crtc
->config
.requested_mode
;
4636 uint32_t vsyncshift
, crtc_vtotal
, crtc_vblank_end
;
4638 /* We need to be careful not to changed the adjusted mode, for otherwise
4639 * the hw state checker will get angry at the mismatch. */
4640 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
4641 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
4643 if (!IS_GEN2(dev
) && adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
4644 /* the chip adds 2 halflines automatically */
4646 crtc_vblank_end
-= 1;
4647 vsyncshift
= adjusted_mode
->crtc_hsync_start
4648 - adjusted_mode
->crtc_htotal
/ 2;
4653 if (INTEL_INFO(dev
)->gen
> 3)
4654 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
4656 I915_WRITE(HTOTAL(cpu_transcoder
),
4657 (adjusted_mode
->crtc_hdisplay
- 1) |
4658 ((adjusted_mode
->crtc_htotal
- 1) << 16));
4659 I915_WRITE(HBLANK(cpu_transcoder
),
4660 (adjusted_mode
->crtc_hblank_start
- 1) |
4661 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
4662 I915_WRITE(HSYNC(cpu_transcoder
),
4663 (adjusted_mode
->crtc_hsync_start
- 1) |
4664 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
4666 I915_WRITE(VTOTAL(cpu_transcoder
),
4667 (adjusted_mode
->crtc_vdisplay
- 1) |
4668 ((crtc_vtotal
- 1) << 16));
4669 I915_WRITE(VBLANK(cpu_transcoder
),
4670 (adjusted_mode
->crtc_vblank_start
- 1) |
4671 ((crtc_vblank_end
- 1) << 16));
4672 I915_WRITE(VSYNC(cpu_transcoder
),
4673 (adjusted_mode
->crtc_vsync_start
- 1) |
4674 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
4676 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4677 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4678 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4680 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
4681 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
4682 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
4684 /* pipesrc controls the size that is scaled from, which should
4685 * always be the user's requested size.
4687 I915_WRITE(PIPESRC(pipe
),
4688 ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
4691 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
4692 struct intel_crtc_config
*pipe_config
)
4694 struct drm_device
*dev
= crtc
->base
.dev
;
4695 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4696 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
4699 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
4700 pipe_config
->adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
4701 pipe_config
->adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
4702 tmp
= I915_READ(HBLANK(cpu_transcoder
));
4703 pipe_config
->adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
4704 pipe_config
->adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
4705 tmp
= I915_READ(HSYNC(cpu_transcoder
));
4706 pipe_config
->adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
4707 pipe_config
->adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
4709 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
4710 pipe_config
->adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
4711 pipe_config
->adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
4712 tmp
= I915_READ(VBLANK(cpu_transcoder
));
4713 pipe_config
->adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
4714 pipe_config
->adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
4715 tmp
= I915_READ(VSYNC(cpu_transcoder
));
4716 pipe_config
->adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
4717 pipe_config
->adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
4719 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
4720 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
4721 pipe_config
->adjusted_mode
.crtc_vtotal
+= 1;
4722 pipe_config
->adjusted_mode
.crtc_vblank_end
+= 1;
4725 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
4726 pipe_config
->requested_mode
.vdisplay
= (tmp
& 0xffff) + 1;
4727 pipe_config
->requested_mode
.hdisplay
= ((tmp
>> 16) & 0xffff) + 1;
4730 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
4732 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4733 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4736 pipeconf
= I915_READ(PIPECONF(intel_crtc
->pipe
));
4738 if (intel_crtc
->pipe
== 0 && INTEL_INFO(dev
)->gen
< 4) {
4739 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4742 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4745 if (intel_crtc
->config
.requested_mode
.clock
>
4746 dev_priv
->display
.get_display_clock_speed(dev
) * 9 / 10)
4747 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
4749 pipeconf
&= ~PIPECONF_DOUBLE_WIDE
;
4752 /* only g4x and later have fancy bpc/dither controls */
4753 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
4754 pipeconf
&= ~(PIPECONF_BPC_MASK
|
4755 PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_MASK
);
4757 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4758 if (intel_crtc
->config
.dither
&& intel_crtc
->config
.pipe_bpp
!= 30)
4759 pipeconf
|= PIPECONF_DITHER_EN
|
4760 PIPECONF_DITHER_TYPE_SP
;
4762 switch (intel_crtc
->config
.pipe_bpp
) {
4764 pipeconf
|= PIPECONF_6BPC
;
4767 pipeconf
|= PIPECONF_8BPC
;
4770 pipeconf
|= PIPECONF_10BPC
;
4773 /* Case prevented by intel_choose_pipe_bpp_dither. */
4778 if (HAS_PIPE_CXSR(dev
)) {
4779 if (intel_crtc
->lowfreq_avail
) {
4780 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4781 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
4783 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4784 pipeconf
&= ~PIPECONF_CXSR_DOWNCLOCK
;
4788 pipeconf
&= ~PIPECONF_INTERLACE_MASK
;
4789 if (!IS_GEN2(dev
) &&
4790 intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
4791 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
4793 pipeconf
|= PIPECONF_PROGRESSIVE
;
4795 if (IS_VALLEYVIEW(dev
)) {
4796 if (intel_crtc
->config
.limited_color_range
)
4797 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
4799 pipeconf
&= ~PIPECONF_COLOR_RANGE_SELECT
;
4802 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
4803 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
4806 static int i9xx_crtc_mode_set(struct drm_crtc
*crtc
,
4808 struct drm_framebuffer
*fb
)
4810 struct drm_device
*dev
= crtc
->dev
;
4811 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4812 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4813 struct drm_display_mode
*mode
= &intel_crtc
->config
.requested_mode
;
4814 int pipe
= intel_crtc
->pipe
;
4815 int plane
= intel_crtc
->plane
;
4816 int refclk
, num_connectors
= 0;
4817 intel_clock_t clock
, reduced_clock
;
4819 bool ok
, has_reduced_clock
= false;
4820 bool is_lvds
= false;
4821 struct intel_encoder
*encoder
;
4822 const intel_limit_t
*limit
;
4825 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4826 switch (encoder
->type
) {
4827 case INTEL_OUTPUT_LVDS
:
4835 refclk
= i9xx_get_refclk(crtc
, num_connectors
);
4838 * Returns a set of divisors for the desired target clock with the given
4839 * refclk, or FALSE. The returned values represent the clock equation:
4840 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4842 limit
= intel_limit(crtc
, refclk
);
4843 ok
= dev_priv
->display
.find_dpll(limit
, crtc
,
4844 intel_crtc
->config
.port_clock
,
4845 refclk
, NULL
, &clock
);
4846 if (!ok
&& !intel_crtc
->config
.clock_set
) {
4847 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4851 /* Ensure that the cursor is valid for the new mode before changing... */
4852 intel_crtc_update_cursor(crtc
, true);
4854 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
4856 * Ensure we match the reduced clock's P to the target clock.
4857 * If the clocks don't match, we can't switch the display clock
4858 * by using the FP0/FP1. In such case we will disable the LVDS
4859 * downclock feature.
4862 dev_priv
->display
.find_dpll(limit
, crtc
,
4863 dev_priv
->lvds_downclock
,
4867 /* Compat-code for transition, will disappear. */
4868 if (!intel_crtc
->config
.clock_set
) {
4869 intel_crtc
->config
.dpll
.n
= clock
.n
;
4870 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
4871 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
4872 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
4873 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
4877 i8xx_update_pll(intel_crtc
,
4878 has_reduced_clock
? &reduced_clock
: NULL
,
4880 else if (IS_VALLEYVIEW(dev
))
4881 vlv_update_pll(intel_crtc
);
4883 i9xx_update_pll(intel_crtc
,
4884 has_reduced_clock
? &reduced_clock
: NULL
,
4887 /* Set up the display plane register */
4888 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
4890 if (!IS_VALLEYVIEW(dev
)) {
4892 dspcntr
&= ~DISPPLANE_SEL_PIPE_MASK
;
4894 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
4897 intel_set_pipe_timings(intel_crtc
);
4899 /* pipesrc and dspsize control the size that is scaled from,
4900 * which should always be the user's requested size.
4902 I915_WRITE(DSPSIZE(plane
),
4903 ((mode
->vdisplay
- 1) << 16) |
4904 (mode
->hdisplay
- 1));
4905 I915_WRITE(DSPPOS(plane
), 0);
4907 i9xx_set_pipeconf(intel_crtc
);
4909 I915_WRITE(DSPCNTR(plane
), dspcntr
);
4910 POSTING_READ(DSPCNTR(plane
));
4912 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
4914 intel_update_watermarks(dev
);
4919 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
4920 struct intel_crtc_config
*pipe_config
)
4922 struct drm_device
*dev
= crtc
->base
.dev
;
4923 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4926 tmp
= I915_READ(PFIT_CONTROL
);
4928 if (INTEL_INFO(dev
)->gen
< 4) {
4929 if (crtc
->pipe
!= PIPE_B
)
4932 /* gen2/3 store dither state in pfit control, needs to match */
4933 pipe_config
->gmch_pfit
.control
= tmp
& PANEL_8TO6_DITHER_ENABLE
;
4935 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
4939 if (!(tmp
& PFIT_ENABLE
))
4942 pipe_config
->gmch_pfit
.control
= I915_READ(PFIT_CONTROL
);
4943 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
4944 if (INTEL_INFO(dev
)->gen
< 5)
4945 pipe_config
->gmch_pfit
.lvds_border_bits
=
4946 I915_READ(LVDS
) & LVDS_BORDER_ENABLE
;
4949 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
4950 struct intel_crtc_config
*pipe_config
)
4952 struct drm_device
*dev
= crtc
->base
.dev
;
4953 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4956 pipe_config
->cpu_transcoder
= crtc
->pipe
;
4957 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
4959 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
4960 if (!(tmp
& PIPECONF_ENABLE
))
4963 intel_get_pipe_timings(crtc
, pipe_config
);
4965 i9xx_get_pfit_config(crtc
, pipe_config
);
4967 if (INTEL_INFO(dev
)->gen
>= 4) {
4968 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
4969 pipe_config
->pixel_multiplier
=
4970 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
4971 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
4972 } else if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
4973 tmp
= I915_READ(DPLL(crtc
->pipe
));
4974 pipe_config
->pixel_multiplier
=
4975 ((tmp
& SDVO_MULTIPLIER_MASK
)
4976 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
4978 /* Note that on i915G/GM the pixel multiplier is in the sdvo
4979 * port and will be fixed up in the encoder->get_config
4981 pipe_config
->pixel_multiplier
= 1;
4987 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
4989 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4990 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
4991 struct intel_encoder
*encoder
;
4993 bool has_lvds
= false;
4994 bool has_cpu_edp
= false;
4995 bool has_panel
= false;
4996 bool has_ck505
= false;
4997 bool can_ssc
= false;
4999 /* We need to take the global config into account */
5000 list_for_each_entry(encoder
, &mode_config
->encoder_list
,
5002 switch (encoder
->type
) {
5003 case INTEL_OUTPUT_LVDS
:
5007 case INTEL_OUTPUT_EDP
:
5009 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
5015 if (HAS_PCH_IBX(dev
)) {
5016 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
5017 can_ssc
= has_ck505
;
5023 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5024 has_panel
, has_lvds
, has_ck505
);
5026 /* Ironlake: try to setup display ref clock before DPLL
5027 * enabling. This is only under driver's control after
5028 * PCH B stepping, previous chipset stepping should be
5029 * ignoring this setting.
5031 val
= I915_READ(PCH_DREF_CONTROL
);
5033 /* As we must carefully and slowly disable/enable each source in turn,
5034 * compute the final state we want first and check if we need to
5035 * make any changes at all.
5038 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
5040 final
|= DREF_NONSPREAD_CK505_ENABLE
;
5042 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
5044 final
&= ~DREF_SSC_SOURCE_MASK
;
5045 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
5046 final
&= ~DREF_SSC1_ENABLE
;
5049 final
|= DREF_SSC_SOURCE_ENABLE
;
5051 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
5052 final
|= DREF_SSC1_ENABLE
;
5055 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
5056 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
5058 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
5060 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5062 final
|= DREF_SSC_SOURCE_DISABLE
;
5063 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5069 /* Always enable nonspread source */
5070 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
5073 val
|= DREF_NONSPREAD_CK505_ENABLE
;
5075 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
5078 val
&= ~DREF_SSC_SOURCE_MASK
;
5079 val
|= DREF_SSC_SOURCE_ENABLE
;
5081 /* SSC must be turned on before enabling the CPU output */
5082 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
5083 DRM_DEBUG_KMS("Using SSC on panel\n");
5084 val
|= DREF_SSC1_ENABLE
;
5086 val
&= ~DREF_SSC1_ENABLE
;
5088 /* Get SSC going before enabling the outputs */
5089 I915_WRITE(PCH_DREF_CONTROL
, val
);
5090 POSTING_READ(PCH_DREF_CONTROL
);
5093 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
5095 /* Enable CPU source on CPU attached eDP */
5097 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
5098 DRM_DEBUG_KMS("Using SSC on eDP\n");
5099 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
5102 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
5104 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5106 I915_WRITE(PCH_DREF_CONTROL
, val
);
5107 POSTING_READ(PCH_DREF_CONTROL
);
5110 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5112 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
5114 /* Turn off CPU output */
5115 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5117 I915_WRITE(PCH_DREF_CONTROL
, val
);
5118 POSTING_READ(PCH_DREF_CONTROL
);
5121 /* Turn off the SSC source */
5122 val
&= ~DREF_SSC_SOURCE_MASK
;
5123 val
|= DREF_SSC_SOURCE_DISABLE
;
5126 val
&= ~DREF_SSC1_ENABLE
;
5128 I915_WRITE(PCH_DREF_CONTROL
, val
);
5129 POSTING_READ(PCH_DREF_CONTROL
);
5133 BUG_ON(val
!= final
);
5136 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5137 static void lpt_init_pch_refclk(struct drm_device
*dev
)
5139 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5140 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
5141 struct intel_encoder
*encoder
;
5142 bool has_vga
= false;
5143 bool is_sdv
= false;
5146 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
) {
5147 switch (encoder
->type
) {
5148 case INTEL_OUTPUT_ANALOG
:
5157 mutex_lock(&dev_priv
->dpio_lock
);
5159 /* XXX: Rip out SDV support once Haswell ships for real. */
5160 if (IS_HASWELL(dev
) && (dev
->pci_device
& 0xFF00) == 0x0C00)
5163 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
5164 tmp
&= ~SBI_SSCCTL_DISABLE
;
5165 tmp
|= SBI_SSCCTL_PATHALT
;
5166 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5170 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
5171 tmp
&= ~SBI_SSCCTL_PATHALT
;
5172 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5175 tmp
= I915_READ(SOUTH_CHICKEN2
);
5176 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
5177 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
5179 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
5180 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
5181 DRM_ERROR("FDI mPHY reset assert timeout\n");
5183 tmp
= I915_READ(SOUTH_CHICKEN2
);
5184 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
5185 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
5187 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
5188 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0,
5190 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5193 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
5194 tmp
&= ~(0xFF << 24);
5195 tmp
|= (0x12 << 24);
5196 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
5199 tmp
= intel_sbi_read(dev_priv
, 0x800C, SBI_MPHY
);
5201 intel_sbi_write(dev_priv
, 0x800C, tmp
, SBI_MPHY
);
5204 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
5206 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
5208 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
5210 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
5213 tmp
= intel_sbi_read(dev_priv
, 0x2038, SBI_MPHY
);
5214 tmp
|= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5215 intel_sbi_write(dev_priv
, 0x2038, tmp
, SBI_MPHY
);
5217 tmp
= intel_sbi_read(dev_priv
, 0x2138, SBI_MPHY
);
5218 tmp
|= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5219 intel_sbi_write(dev_priv
, 0x2138, tmp
, SBI_MPHY
);
5221 tmp
= intel_sbi_read(dev_priv
, 0x203C, SBI_MPHY
);
5223 intel_sbi_write(dev_priv
, 0x203C, tmp
, SBI_MPHY
);
5225 tmp
= intel_sbi_read(dev_priv
, 0x213C, SBI_MPHY
);
5227 intel_sbi_write(dev_priv
, 0x213C, tmp
, SBI_MPHY
);
5230 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
5231 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
5232 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
5234 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
5235 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
5236 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
5239 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
5242 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
5244 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
5247 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
5250 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
5253 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
5255 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
5258 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
5260 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
5261 tmp
&= ~(0xFF << 16);
5262 tmp
|= (0x1C << 16);
5263 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
5265 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
5266 tmp
&= ~(0xFF << 16);
5267 tmp
|= (0x1C << 16);
5268 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
5271 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
5273 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
5275 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
5277 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
5279 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
5280 tmp
&= ~(0xF << 28);
5282 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
5284 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
5285 tmp
&= ~(0xF << 28);
5287 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
5290 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5291 tmp
= intel_sbi_read(dev_priv
, SBI_DBUFF0
, SBI_ICLK
);
5292 tmp
|= SBI_DBUFF0_ENABLE
;
5293 intel_sbi_write(dev_priv
, SBI_DBUFF0
, tmp
, SBI_ICLK
);
5295 mutex_unlock(&dev_priv
->dpio_lock
);
5299 * Initialize reference clocks when the driver loads
5301 void intel_init_pch_refclk(struct drm_device
*dev
)
5303 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
5304 ironlake_init_pch_refclk(dev
);
5305 else if (HAS_PCH_LPT(dev
))
5306 lpt_init_pch_refclk(dev
);
5309 static int ironlake_get_refclk(struct drm_crtc
*crtc
)
5311 struct drm_device
*dev
= crtc
->dev
;
5312 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5313 struct intel_encoder
*encoder
;
5314 int num_connectors
= 0;
5315 bool is_lvds
= false;
5317 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5318 switch (encoder
->type
) {
5319 case INTEL_OUTPUT_LVDS
:
5326 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
5327 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5328 dev_priv
->vbt
.lvds_ssc_freq
);
5329 return dev_priv
->vbt
.lvds_ssc_freq
* 1000;
5335 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
5337 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
5338 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5339 int pipe
= intel_crtc
->pipe
;
5342 val
= I915_READ(PIPECONF(pipe
));
5344 val
&= ~PIPECONF_BPC_MASK
;
5345 switch (intel_crtc
->config
.pipe_bpp
) {
5347 val
|= PIPECONF_6BPC
;
5350 val
|= PIPECONF_8BPC
;
5353 val
|= PIPECONF_10BPC
;
5356 val
|= PIPECONF_12BPC
;
5359 /* Case prevented by intel_choose_pipe_bpp_dither. */
5363 val
&= ~(PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_MASK
);
5364 if (intel_crtc
->config
.dither
)
5365 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
5367 val
&= ~PIPECONF_INTERLACE_MASK
;
5368 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
5369 val
|= PIPECONF_INTERLACED_ILK
;
5371 val
|= PIPECONF_PROGRESSIVE
;
5373 if (intel_crtc
->config
.limited_color_range
)
5374 val
|= PIPECONF_COLOR_RANGE_SELECT
;
5376 val
&= ~PIPECONF_COLOR_RANGE_SELECT
;
5378 I915_WRITE(PIPECONF(pipe
), val
);
5379 POSTING_READ(PIPECONF(pipe
));
5383 * Set up the pipe CSC unit.
5385 * Currently only full range RGB to limited range RGB conversion
5386 * is supported, but eventually this should handle various
5387 * RGB<->YCbCr scenarios as well.
5389 static void intel_set_pipe_csc(struct drm_crtc
*crtc
)
5391 struct drm_device
*dev
= crtc
->dev
;
5392 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5393 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5394 int pipe
= intel_crtc
->pipe
;
5395 uint16_t coeff
= 0x7800; /* 1.0 */
5398 * TODO: Check what kind of values actually come out of the pipe
5399 * with these coeff/postoff values and adjust to get the best
5400 * accuracy. Perhaps we even need to take the bpc value into
5404 if (intel_crtc
->config
.limited_color_range
)
5405 coeff
= ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5408 * GY/GU and RY/RU should be the other way around according
5409 * to BSpec, but reality doesn't agree. Just set them up in
5410 * a way that results in the correct picture.
5412 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeff
<< 16);
5413 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), 0);
5415 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeff
);
5416 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), 0);
5418 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), 0);
5419 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeff
<< 16);
5421 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
5422 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
5423 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
5425 if (INTEL_INFO(dev
)->gen
> 6) {
5426 uint16_t postoff
= 0;
5428 if (intel_crtc
->config
.limited_color_range
)
5429 postoff
= (16 * (1 << 13) / 255) & 0x1fff;
5431 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
5432 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
5433 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
5435 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
5437 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
5439 if (intel_crtc
->config
.limited_color_range
)
5440 mode
|= CSC_BLACK_SCREEN_OFFSET
;
5442 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
5446 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
5448 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
5449 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5450 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
5453 val
= I915_READ(PIPECONF(cpu_transcoder
));
5455 val
&= ~(PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_MASK
);
5456 if (intel_crtc
->config
.dither
)
5457 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
5459 val
&= ~PIPECONF_INTERLACE_MASK_HSW
;
5460 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
5461 val
|= PIPECONF_INTERLACED_ILK
;
5463 val
|= PIPECONF_PROGRESSIVE
;
5465 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
5466 POSTING_READ(PIPECONF(cpu_transcoder
));
5469 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
5470 intel_clock_t
*clock
,
5471 bool *has_reduced_clock
,
5472 intel_clock_t
*reduced_clock
)
5474 struct drm_device
*dev
= crtc
->dev
;
5475 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5476 struct intel_encoder
*intel_encoder
;
5478 const intel_limit_t
*limit
;
5479 bool ret
, is_lvds
= false;
5481 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5482 switch (intel_encoder
->type
) {
5483 case INTEL_OUTPUT_LVDS
:
5489 refclk
= ironlake_get_refclk(crtc
);
5492 * Returns a set of divisors for the desired target clock with the given
5493 * refclk, or FALSE. The returned values represent the clock equation:
5494 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5496 limit
= intel_limit(crtc
, refclk
);
5497 ret
= dev_priv
->display
.find_dpll(limit
, crtc
,
5498 to_intel_crtc(crtc
)->config
.port_clock
,
5499 refclk
, NULL
, clock
);
5503 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
5505 * Ensure we match the reduced clock's P to the target clock.
5506 * If the clocks don't match, we can't switch the display clock
5507 * by using the FP0/FP1. In such case we will disable the LVDS
5508 * downclock feature.
5510 *has_reduced_clock
=
5511 dev_priv
->display
.find_dpll(limit
, crtc
,
5512 dev_priv
->lvds_downclock
,
5520 static void cpt_enable_fdi_bc_bifurcation(struct drm_device
*dev
)
5522 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5525 temp
= I915_READ(SOUTH_CHICKEN1
);
5526 if (temp
& FDI_BC_BIFURCATION_SELECT
)
5529 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
5530 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
5532 temp
|= FDI_BC_BIFURCATION_SELECT
;
5533 DRM_DEBUG_KMS("enabling fdi C rx\n");
5534 I915_WRITE(SOUTH_CHICKEN1
, temp
);
5535 POSTING_READ(SOUTH_CHICKEN1
);
5538 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
5540 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5541 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5543 switch (intel_crtc
->pipe
) {
5547 if (intel_crtc
->config
.fdi_lanes
> 2)
5548 WARN_ON(I915_READ(SOUTH_CHICKEN1
) & FDI_BC_BIFURCATION_SELECT
);
5550 cpt_enable_fdi_bc_bifurcation(dev
);
5554 cpt_enable_fdi_bc_bifurcation(dev
);
5562 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
5565 * Account for spread spectrum to avoid
5566 * oversubscribing the link. Max center spread
5567 * is 2.5%; use 5% for safety's sake.
5569 u32 bps
= target_clock
* bpp
* 21 / 20;
5570 return bps
/ (link_bw
* 8) + 1;
5573 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
5575 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
5578 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
5580 intel_clock_t
*reduced_clock
, u32
*fp2
)
5582 struct drm_crtc
*crtc
= &intel_crtc
->base
;
5583 struct drm_device
*dev
= crtc
->dev
;
5584 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5585 struct intel_encoder
*intel_encoder
;
5587 int factor
, num_connectors
= 0;
5588 bool is_lvds
= false, is_sdvo
= false;
5590 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5591 switch (intel_encoder
->type
) {
5592 case INTEL_OUTPUT_LVDS
:
5595 case INTEL_OUTPUT_SDVO
:
5596 case INTEL_OUTPUT_HDMI
:
5604 /* Enable autotuning of the PLL clock (if permissible) */
5607 if ((intel_panel_use_ssc(dev_priv
) &&
5608 dev_priv
->vbt
.lvds_ssc_freq
== 100) ||
5609 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
5611 } else if (intel_crtc
->config
.sdvo_tv_clock
)
5614 if (ironlake_needs_fb_cb_tune(&intel_crtc
->config
.dpll
, factor
))
5617 if (fp2
&& (reduced_clock
->m
< factor
* reduced_clock
->n
))
5623 dpll
|= DPLLB_MODE_LVDS
;
5625 dpll
|= DPLLB_MODE_DAC_SERIAL
;
5627 dpll
|= (intel_crtc
->config
.pixel_multiplier
- 1)
5628 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
5631 dpll
|= DPLL_DVO_HIGH_SPEED
;
5632 if (intel_crtc
->config
.has_dp_encoder
)
5633 dpll
|= DPLL_DVO_HIGH_SPEED
;
5635 /* compute bitmask from p1 value */
5636 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5638 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
5640 switch (intel_crtc
->config
.dpll
.p2
) {
5642 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
5645 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
5648 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
5651 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
5655 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
5656 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
5658 dpll
|= PLL_REF_INPUT_DREFCLK
;
5663 static int ironlake_crtc_mode_set(struct drm_crtc
*crtc
,
5665 struct drm_framebuffer
*fb
)
5667 struct drm_device
*dev
= crtc
->dev
;
5668 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5669 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5670 int pipe
= intel_crtc
->pipe
;
5671 int plane
= intel_crtc
->plane
;
5672 int num_connectors
= 0;
5673 intel_clock_t clock
, reduced_clock
;
5674 u32 dpll
= 0, fp
= 0, fp2
= 0;
5675 bool ok
, has_reduced_clock
= false;
5676 bool is_lvds
= false;
5677 struct intel_encoder
*encoder
;
5678 struct intel_shared_dpll
*pll
;
5681 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5682 switch (encoder
->type
) {
5683 case INTEL_OUTPUT_LVDS
:
5691 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
5692 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
5694 ok
= ironlake_compute_clocks(crtc
, &clock
,
5695 &has_reduced_clock
, &reduced_clock
);
5696 if (!ok
&& !intel_crtc
->config
.clock_set
) {
5697 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5700 /* Compat-code for transition, will disappear. */
5701 if (!intel_crtc
->config
.clock_set
) {
5702 intel_crtc
->config
.dpll
.n
= clock
.n
;
5703 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
5704 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
5705 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
5706 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
5709 /* Ensure that the cursor is valid for the new mode before changing... */
5710 intel_crtc_update_cursor(crtc
, true);
5712 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5713 if (intel_crtc
->config
.has_pch_encoder
) {
5714 fp
= i9xx_dpll_compute_fp(&intel_crtc
->config
.dpll
);
5715 if (has_reduced_clock
)
5716 fp2
= i9xx_dpll_compute_fp(&reduced_clock
);
5718 dpll
= ironlake_compute_dpll(intel_crtc
,
5719 &fp
, &reduced_clock
,
5720 has_reduced_clock
? &fp2
: NULL
);
5722 pll
= intel_get_shared_dpll(intel_crtc
, dpll
, fp
);
5724 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5729 intel_put_shared_dpll(intel_crtc
);
5731 if (intel_crtc
->config
.has_dp_encoder
)
5732 intel_dp_set_m_n(intel_crtc
);
5734 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5735 if (encoder
->pre_pll_enable
)
5736 encoder
->pre_pll_enable(encoder
);
5738 intel_crtc
->lowfreq_avail
= false;
5740 if (intel_crtc
->config
.has_pch_encoder
) {
5741 pll
= intel_crtc_to_shared_dpll(intel_crtc
);
5743 I915_WRITE(PCH_DPLL(pll
->id
), dpll
);
5745 /* Wait for the clocks to stabilize. */
5746 POSTING_READ(PCH_DPLL(pll
->id
));
5749 /* The pixel multiplier can only be updated once the
5750 * DPLL is enabled and the clocks are stable.
5752 * So write it again.
5754 I915_WRITE(PCH_DPLL(pll
->id
), dpll
);
5756 if (is_lvds
&& has_reduced_clock
&& i915_powersave
) {
5757 I915_WRITE(PCH_FP1(pll
->id
), fp2
);
5758 intel_crtc
->lowfreq_avail
= true;
5760 I915_WRITE(PCH_FP1(pll
->id
), fp
);
5764 intel_set_pipe_timings(intel_crtc
);
5766 if (intel_crtc
->config
.has_pch_encoder
) {
5767 intel_cpu_transcoder_set_m_n(intel_crtc
,
5768 &intel_crtc
->config
.fdi_m_n
);
5771 if (IS_IVYBRIDGE(dev
))
5772 ivybridge_update_fdi_bc_bifurcation(intel_crtc
);
5774 ironlake_set_pipeconf(crtc
);
5776 /* Set up the display plane register */
5777 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
);
5778 POSTING_READ(DSPCNTR(plane
));
5780 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
5782 intel_update_watermarks(dev
);
5787 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
5788 struct intel_crtc_config
*pipe_config
)
5790 struct drm_device
*dev
= crtc
->base
.dev
;
5791 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5792 enum transcoder transcoder
= pipe_config
->cpu_transcoder
;
5794 pipe_config
->fdi_m_n
.link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
5795 pipe_config
->fdi_m_n
.link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
5796 pipe_config
->fdi_m_n
.gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
5798 pipe_config
->fdi_m_n
.gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
5799 pipe_config
->fdi_m_n
.tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
5800 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
5803 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
5804 struct intel_crtc_config
*pipe_config
)
5806 struct drm_device
*dev
= crtc
->base
.dev
;
5807 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5810 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
5812 if (tmp
& PF_ENABLE
) {
5813 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
5814 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
5816 /* We currently do not free assignements of panel fitters on
5817 * ivb/hsw (since we don't use the higher upscaling modes which
5818 * differentiates them) so just WARN about this case for now. */
5820 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
5821 PF_PIPE_SEL_IVB(crtc
->pipe
));
5826 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
5827 struct intel_crtc_config
*pipe_config
)
5829 struct drm_device
*dev
= crtc
->base
.dev
;
5830 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5833 pipe_config
->cpu_transcoder
= crtc
->pipe
;
5834 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
5836 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
5837 if (!(tmp
& PIPECONF_ENABLE
))
5840 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
5841 pipe_config
->has_pch_encoder
= true;
5843 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
5844 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
5845 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
5847 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
5849 /* XXX: Can't properly read out the pch dpll pixel multiplier
5850 * since we don't have state tracking for pch clocks yet. */
5851 pipe_config
->pixel_multiplier
= 1;
5853 if (HAS_PCH_IBX(dev_priv
->dev
)) {
5854 pipe_config
->shared_dpll
= crtc
->pipe
;
5856 tmp
= I915_READ(PCH_DPLL_SEL
);
5857 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
5858 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_B
;
5860 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_A
;
5863 pipe_config
->pixel_multiplier
= 1;
5866 intel_get_pipe_timings(crtc
, pipe_config
);
5868 ironlake_get_pfit_config(crtc
, pipe_config
);
5873 static void haswell_modeset_global_resources(struct drm_device
*dev
)
5875 bool enable
= false;
5876 struct intel_crtc
*crtc
;
5878 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
5879 if (!crtc
->base
.enabled
)
5882 if (crtc
->pipe
!= PIPE_A
|| crtc
->config
.pch_pfit
.size
||
5883 crtc
->config
.cpu_transcoder
!= TRANSCODER_EDP
)
5887 intel_set_power_well(dev
, enable
);
5890 static int haswell_crtc_mode_set(struct drm_crtc
*crtc
,
5892 struct drm_framebuffer
*fb
)
5894 struct drm_device
*dev
= crtc
->dev
;
5895 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5896 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5897 int plane
= intel_crtc
->plane
;
5900 if (!intel_ddi_pll_mode_set(crtc
))
5903 /* Ensure that the cursor is valid for the new mode before changing... */
5904 intel_crtc_update_cursor(crtc
, true);
5906 if (intel_crtc
->config
.has_dp_encoder
)
5907 intel_dp_set_m_n(intel_crtc
);
5909 intel_crtc
->lowfreq_avail
= false;
5911 intel_set_pipe_timings(intel_crtc
);
5913 if (intel_crtc
->config
.has_pch_encoder
) {
5914 intel_cpu_transcoder_set_m_n(intel_crtc
,
5915 &intel_crtc
->config
.fdi_m_n
);
5918 haswell_set_pipeconf(crtc
);
5920 intel_set_pipe_csc(crtc
);
5922 /* Set up the display plane register */
5923 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
| DISPPLANE_PIPE_CSC_ENABLE
);
5924 POSTING_READ(DSPCNTR(plane
));
5926 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
5928 intel_update_watermarks(dev
);
5933 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
5934 struct intel_crtc_config
*pipe_config
)
5936 struct drm_device
*dev
= crtc
->base
.dev
;
5937 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5938 enum intel_display_power_domain pfit_domain
;
5941 pipe_config
->cpu_transcoder
= crtc
->pipe
;
5942 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
5944 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
5945 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
5946 enum pipe trans_edp_pipe
;
5947 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
5949 WARN(1, "unknown pipe linked to edp transcoder\n");
5950 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
5951 case TRANS_DDI_EDP_INPUT_A_ON
:
5952 trans_edp_pipe
= PIPE_A
;
5954 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
5955 trans_edp_pipe
= PIPE_B
;
5957 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
5958 trans_edp_pipe
= PIPE_C
;
5962 if (trans_edp_pipe
== crtc
->pipe
)
5963 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
5966 if (!intel_display_power_enabled(dev
,
5967 POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
)))
5970 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
5971 if (!(tmp
& PIPECONF_ENABLE
))
5975 * Haswell has only FDI/PCH transcoder A. It is which is connected to
5976 * DDI E. So just check whether this pipe is wired to DDI E and whether
5977 * the PCH transcoder is on.
5979 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
5980 if ((tmp
& TRANS_DDI_PORT_MASK
) == TRANS_DDI_SELECT_PORT(PORT_E
) &&
5981 I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
5982 pipe_config
->has_pch_encoder
= true;
5984 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
5985 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
5986 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
5988 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
5991 intel_get_pipe_timings(crtc
, pipe_config
);
5993 pfit_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
5994 if (intel_display_power_enabled(dev
, pfit_domain
))
5995 ironlake_get_pfit_config(crtc
, pipe_config
);
5997 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
5998 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
6000 pipe_config
->pixel_multiplier
= 1;
6005 static int intel_crtc_mode_set(struct drm_crtc
*crtc
,
6007 struct drm_framebuffer
*fb
)
6009 struct drm_device
*dev
= crtc
->dev
;
6010 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6011 struct drm_encoder_helper_funcs
*encoder_funcs
;
6012 struct intel_encoder
*encoder
;
6013 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6014 struct drm_display_mode
*adjusted_mode
=
6015 &intel_crtc
->config
.adjusted_mode
;
6016 struct drm_display_mode
*mode
= &intel_crtc
->config
.requested_mode
;
6017 int pipe
= intel_crtc
->pipe
;
6020 drm_vblank_pre_modeset(dev
, pipe
);
6022 ret
= dev_priv
->display
.crtc_mode_set(crtc
, x
, y
, fb
);
6024 drm_vblank_post_modeset(dev
, pipe
);
6029 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
6030 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6031 encoder
->base
.base
.id
,
6032 drm_get_encoder_name(&encoder
->base
),
6033 mode
->base
.id
, mode
->name
);
6034 if (encoder
->mode_set
) {
6035 encoder
->mode_set(encoder
);
6037 encoder_funcs
= encoder
->base
.helper_private
;
6038 encoder_funcs
->mode_set(&encoder
->base
, mode
, adjusted_mode
);
6045 static bool intel_eld_uptodate(struct drm_connector
*connector
,
6046 int reg_eldv
, uint32_t bits_eldv
,
6047 int reg_elda
, uint32_t bits_elda
,
6050 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6051 uint8_t *eld
= connector
->eld
;
6054 i
= I915_READ(reg_eldv
);
6063 i
= I915_READ(reg_elda
);
6065 I915_WRITE(reg_elda
, i
);
6067 for (i
= 0; i
< eld
[2]; i
++)
6068 if (I915_READ(reg_edid
) != *((uint32_t *)eld
+ i
))
6074 static void g4x_write_eld(struct drm_connector
*connector
,
6075 struct drm_crtc
*crtc
)
6077 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6078 uint8_t *eld
= connector
->eld
;
6083 i
= I915_READ(G4X_AUD_VID_DID
);
6085 if (i
== INTEL_AUDIO_DEVBLC
|| i
== INTEL_AUDIO_DEVCL
)
6086 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
6088 eldv
= G4X_ELDV_DEVCTG
;
6090 if (intel_eld_uptodate(connector
,
6091 G4X_AUD_CNTL_ST
, eldv
,
6092 G4X_AUD_CNTL_ST
, G4X_ELD_ADDR
,
6093 G4X_HDMIW_HDMIEDID
))
6096 i
= I915_READ(G4X_AUD_CNTL_ST
);
6097 i
&= ~(eldv
| G4X_ELD_ADDR
);
6098 len
= (i
>> 9) & 0x1f; /* ELD buffer size */
6099 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
6104 len
= min_t(uint8_t, eld
[2], len
);
6105 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6106 for (i
= 0; i
< len
; i
++)
6107 I915_WRITE(G4X_HDMIW_HDMIEDID
, *((uint32_t *)eld
+ i
));
6109 i
= I915_READ(G4X_AUD_CNTL_ST
);
6111 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
6114 static void haswell_write_eld(struct drm_connector
*connector
,
6115 struct drm_crtc
*crtc
)
6117 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6118 uint8_t *eld
= connector
->eld
;
6119 struct drm_device
*dev
= crtc
->dev
;
6120 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6124 int pipe
= to_intel_crtc(crtc
)->pipe
;
6127 int hdmiw_hdmiedid
= HSW_AUD_EDID_DATA(pipe
);
6128 int aud_cntl_st
= HSW_AUD_DIP_ELD_CTRL(pipe
);
6129 int aud_config
= HSW_AUD_CFG(pipe
);
6130 int aud_cntrl_st2
= HSW_AUD_PIN_ELD_CP_VLD
;
6133 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6135 /* Audio output enable */
6136 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6137 tmp
= I915_READ(aud_cntrl_st2
);
6138 tmp
|= (AUDIO_OUTPUT_ENABLE_A
<< (pipe
* 4));
6139 I915_WRITE(aud_cntrl_st2
, tmp
);
6141 /* Wait for 1 vertical blank */
6142 intel_wait_for_vblank(dev
, pipe
);
6144 /* Set ELD valid state */
6145 tmp
= I915_READ(aud_cntrl_st2
);
6146 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp
);
6147 tmp
|= (AUDIO_ELD_VALID_A
<< (pipe
* 4));
6148 I915_WRITE(aud_cntrl_st2
, tmp
);
6149 tmp
= I915_READ(aud_cntrl_st2
);
6150 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp
);
6152 /* Enable HDMI mode */
6153 tmp
= I915_READ(aud_config
);
6154 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp
);
6155 /* clear N_programing_enable and N_value_index */
6156 tmp
&= ~(AUD_CONFIG_N_VALUE_INDEX
| AUD_CONFIG_N_PROG_ENABLE
);
6157 I915_WRITE(aud_config
, tmp
);
6159 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
6161 eldv
= AUDIO_ELD_VALID_A
<< (pipe
* 4);
6162 intel_crtc
->eld_vld
= true;
6164 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
6165 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6166 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6167 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
6169 I915_WRITE(aud_config
, 0);
6171 if (intel_eld_uptodate(connector
,
6172 aud_cntrl_st2
, eldv
,
6173 aud_cntl_st
, IBX_ELD_ADDRESS
,
6177 i
= I915_READ(aud_cntrl_st2
);
6179 I915_WRITE(aud_cntrl_st2
, i
);
6184 i
= I915_READ(aud_cntl_st
);
6185 i
&= ~IBX_ELD_ADDRESS
;
6186 I915_WRITE(aud_cntl_st
, i
);
6187 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
6188 DRM_DEBUG_DRIVER("port num:%d\n", i
);
6190 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
6191 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6192 for (i
= 0; i
< len
; i
++)
6193 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
6195 i
= I915_READ(aud_cntrl_st2
);
6197 I915_WRITE(aud_cntrl_st2
, i
);
6201 static void ironlake_write_eld(struct drm_connector
*connector
,
6202 struct drm_crtc
*crtc
)
6204 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6205 uint8_t *eld
= connector
->eld
;
6213 int pipe
= to_intel_crtc(crtc
)->pipe
;
6215 if (HAS_PCH_IBX(connector
->dev
)) {
6216 hdmiw_hdmiedid
= IBX_HDMIW_HDMIEDID(pipe
);
6217 aud_config
= IBX_AUD_CFG(pipe
);
6218 aud_cntl_st
= IBX_AUD_CNTL_ST(pipe
);
6219 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
6221 hdmiw_hdmiedid
= CPT_HDMIW_HDMIEDID(pipe
);
6222 aud_config
= CPT_AUD_CFG(pipe
);
6223 aud_cntl_st
= CPT_AUD_CNTL_ST(pipe
);
6224 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
6227 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
6229 i
= I915_READ(aud_cntl_st
);
6230 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
6232 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6233 /* operate blindly on all ports */
6234 eldv
= IBX_ELD_VALIDB
;
6235 eldv
|= IBX_ELD_VALIDB
<< 4;
6236 eldv
|= IBX_ELD_VALIDB
<< 8;
6238 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i
));
6239 eldv
= IBX_ELD_VALIDB
<< ((i
- 1) * 4);
6242 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
6243 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6244 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6245 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
6247 I915_WRITE(aud_config
, 0);
6249 if (intel_eld_uptodate(connector
,
6250 aud_cntrl_st2
, eldv
,
6251 aud_cntl_st
, IBX_ELD_ADDRESS
,
6255 i
= I915_READ(aud_cntrl_st2
);
6257 I915_WRITE(aud_cntrl_st2
, i
);
6262 i
= I915_READ(aud_cntl_st
);
6263 i
&= ~IBX_ELD_ADDRESS
;
6264 I915_WRITE(aud_cntl_st
, i
);
6266 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
6267 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6268 for (i
= 0; i
< len
; i
++)
6269 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
6271 i
= I915_READ(aud_cntrl_st2
);
6273 I915_WRITE(aud_cntrl_st2
, i
);
6276 void intel_write_eld(struct drm_encoder
*encoder
,
6277 struct drm_display_mode
*mode
)
6279 struct drm_crtc
*crtc
= encoder
->crtc
;
6280 struct drm_connector
*connector
;
6281 struct drm_device
*dev
= encoder
->dev
;
6282 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6284 connector
= drm_select_eld(encoder
, mode
);
6288 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6290 drm_get_connector_name(connector
),
6291 connector
->encoder
->base
.id
,
6292 drm_get_encoder_name(connector
->encoder
));
6294 connector
->eld
[6] = drm_av_sync_delay(connector
, mode
) / 2;
6296 if (dev_priv
->display
.write_eld
)
6297 dev_priv
->display
.write_eld(connector
, crtc
);
6300 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6301 void intel_crtc_load_lut(struct drm_crtc
*crtc
)
6303 struct drm_device
*dev
= crtc
->dev
;
6304 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6305 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6306 enum pipe pipe
= intel_crtc
->pipe
;
6307 int palreg
= PALETTE(pipe
);
6309 bool reenable_ips
= false;
6311 /* The clocks have to be on to load the palette. */
6312 if (!crtc
->enabled
|| !intel_crtc
->active
)
6315 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
6316 assert_pll_enabled(dev_priv
, pipe
);
6318 /* use legacy palette for Ironlake */
6319 if (HAS_PCH_SPLIT(dev
))
6320 palreg
= LGC_PALETTE(pipe
);
6322 /* Workaround : Do not read or write the pipe palette/gamma data while
6323 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6325 if (intel_crtc
->config
.ips_enabled
&&
6326 ((I915_READ(GAMMA_MODE(pipe
)) & GAMMA_MODE_MODE_MASK
) ==
6327 GAMMA_MODE_MODE_SPLIT
)) {
6328 hsw_disable_ips(intel_crtc
);
6329 reenable_ips
= true;
6332 for (i
= 0; i
< 256; i
++) {
6333 I915_WRITE(palreg
+ 4 * i
,
6334 (intel_crtc
->lut_r
[i
] << 16) |
6335 (intel_crtc
->lut_g
[i
] << 8) |
6336 intel_crtc
->lut_b
[i
]);
6340 hsw_enable_ips(intel_crtc
);
6343 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6345 struct drm_device
*dev
= crtc
->dev
;
6346 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6347 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6348 bool visible
= base
!= 0;
6351 if (intel_crtc
->cursor_visible
== visible
)
6354 cntl
= I915_READ(_CURACNTR
);
6356 /* On these chipsets we can only modify the base whilst
6357 * the cursor is disabled.
6359 I915_WRITE(_CURABASE
, base
);
6361 cntl
&= ~(CURSOR_FORMAT_MASK
);
6362 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6363 cntl
|= CURSOR_ENABLE
|
6364 CURSOR_GAMMA_ENABLE
|
6367 cntl
&= ~(CURSOR_ENABLE
| CURSOR_GAMMA_ENABLE
);
6368 I915_WRITE(_CURACNTR
, cntl
);
6370 intel_crtc
->cursor_visible
= visible
;
6373 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6375 struct drm_device
*dev
= crtc
->dev
;
6376 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6377 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6378 int pipe
= intel_crtc
->pipe
;
6379 bool visible
= base
!= 0;
6381 if (intel_crtc
->cursor_visible
!= visible
) {
6382 uint32_t cntl
= I915_READ(CURCNTR(pipe
));
6384 cntl
&= ~(CURSOR_MODE
| MCURSOR_PIPE_SELECT
);
6385 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
6386 cntl
|= pipe
<< 28; /* Connect to correct pipe */
6388 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
6389 cntl
|= CURSOR_MODE_DISABLE
;
6391 I915_WRITE(CURCNTR(pipe
), cntl
);
6393 intel_crtc
->cursor_visible
= visible
;
6395 /* and commit changes on next vblank */
6396 I915_WRITE(CURBASE(pipe
), base
);
6399 static void ivb_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6401 struct drm_device
*dev
= crtc
->dev
;
6402 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6403 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6404 int pipe
= intel_crtc
->pipe
;
6405 bool visible
= base
!= 0;
6407 if (intel_crtc
->cursor_visible
!= visible
) {
6408 uint32_t cntl
= I915_READ(CURCNTR_IVB(pipe
));
6410 cntl
&= ~CURSOR_MODE
;
6411 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
6413 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
6414 cntl
|= CURSOR_MODE_DISABLE
;
6416 if (IS_HASWELL(dev
))
6417 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
6418 I915_WRITE(CURCNTR_IVB(pipe
), cntl
);
6420 intel_crtc
->cursor_visible
= visible
;
6422 /* and commit changes on next vblank */
6423 I915_WRITE(CURBASE_IVB(pipe
), base
);
6426 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6427 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
6430 struct drm_device
*dev
= crtc
->dev
;
6431 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6432 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6433 int pipe
= intel_crtc
->pipe
;
6434 int x
= intel_crtc
->cursor_x
;
6435 int y
= intel_crtc
->cursor_y
;
6441 if (on
&& crtc
->enabled
&& crtc
->fb
) {
6442 base
= intel_crtc
->cursor_addr
;
6443 if (x
> (int) crtc
->fb
->width
)
6446 if (y
> (int) crtc
->fb
->height
)
6452 if (x
+ intel_crtc
->cursor_width
< 0)
6455 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
6458 pos
|= x
<< CURSOR_X_SHIFT
;
6461 if (y
+ intel_crtc
->cursor_height
< 0)
6464 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
6467 pos
|= y
<< CURSOR_Y_SHIFT
;
6469 visible
= base
!= 0;
6470 if (!visible
&& !intel_crtc
->cursor_visible
)
6473 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
6474 I915_WRITE(CURPOS_IVB(pipe
), pos
);
6475 ivb_update_cursor(crtc
, base
);
6477 I915_WRITE(CURPOS(pipe
), pos
);
6478 if (IS_845G(dev
) || IS_I865G(dev
))
6479 i845_update_cursor(crtc
, base
);
6481 i9xx_update_cursor(crtc
, base
);
6485 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
6486 struct drm_file
*file
,
6488 uint32_t width
, uint32_t height
)
6490 struct drm_device
*dev
= crtc
->dev
;
6491 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6492 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6493 struct drm_i915_gem_object
*obj
;
6497 /* if we want to turn off the cursor ignore width and height */
6499 DRM_DEBUG_KMS("cursor off\n");
6502 mutex_lock(&dev
->struct_mutex
);
6506 /* Currently we only support 64x64 cursors */
6507 if (width
!= 64 || height
!= 64) {
6508 DRM_ERROR("we currently only support 64x64 cursors\n");
6512 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
6513 if (&obj
->base
== NULL
)
6516 if (obj
->base
.size
< width
* height
* 4) {
6517 DRM_ERROR("buffer is to small\n");
6522 /* we only need to pin inside GTT if cursor is non-phy */
6523 mutex_lock(&dev
->struct_mutex
);
6524 if (!dev_priv
->info
->cursor_needs_physical
) {
6527 if (obj
->tiling_mode
) {
6528 DRM_ERROR("cursor cannot be tiled\n");
6533 /* Note that the w/a also requires 2 PTE of padding following
6534 * the bo. We currently fill all unused PTE with the shadow
6535 * page and so we should always have valid PTE following the
6536 * cursor preventing the VT-d warning.
6539 if (need_vtd_wa(dev
))
6540 alignment
= 64*1024;
6542 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, NULL
);
6544 DRM_ERROR("failed to move cursor bo into the GTT\n");
6548 ret
= i915_gem_object_put_fence(obj
);
6550 DRM_ERROR("failed to release fence for cursor");
6554 addr
= obj
->gtt_offset
;
6556 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
6557 ret
= i915_gem_attach_phys_object(dev
, obj
,
6558 (intel_crtc
->pipe
== 0) ? I915_GEM_PHYS_CURSOR_0
: I915_GEM_PHYS_CURSOR_1
,
6561 DRM_ERROR("failed to attach phys object\n");
6564 addr
= obj
->phys_obj
->handle
->busaddr
;
6568 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
6571 if (intel_crtc
->cursor_bo
) {
6572 if (dev_priv
->info
->cursor_needs_physical
) {
6573 if (intel_crtc
->cursor_bo
!= obj
)
6574 i915_gem_detach_phys_object(dev
, intel_crtc
->cursor_bo
);
6576 i915_gem_object_unpin(intel_crtc
->cursor_bo
);
6577 drm_gem_object_unreference(&intel_crtc
->cursor_bo
->base
);
6580 mutex_unlock(&dev
->struct_mutex
);
6582 intel_crtc
->cursor_addr
= addr
;
6583 intel_crtc
->cursor_bo
= obj
;
6584 intel_crtc
->cursor_width
= width
;
6585 intel_crtc
->cursor_height
= height
;
6587 intel_crtc_update_cursor(crtc
, intel_crtc
->cursor_bo
!= NULL
);
6591 i915_gem_object_unpin(obj
);
6593 mutex_unlock(&dev
->struct_mutex
);
6595 drm_gem_object_unreference_unlocked(&obj
->base
);
6599 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
6601 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6603 intel_crtc
->cursor_x
= x
;
6604 intel_crtc
->cursor_y
= y
;
6606 intel_crtc_update_cursor(crtc
, intel_crtc
->cursor_bo
!= NULL
);
6611 /** Sets the color ramps on behalf of RandR */
6612 void intel_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
6613 u16 blue
, int regno
)
6615 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6617 intel_crtc
->lut_r
[regno
] = red
>> 8;
6618 intel_crtc
->lut_g
[regno
] = green
>> 8;
6619 intel_crtc
->lut_b
[regno
] = blue
>> 8;
6622 void intel_crtc_fb_gamma_get(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
6623 u16
*blue
, int regno
)
6625 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6627 *red
= intel_crtc
->lut_r
[regno
] << 8;
6628 *green
= intel_crtc
->lut_g
[regno
] << 8;
6629 *blue
= intel_crtc
->lut_b
[regno
] << 8;
6632 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
6633 u16
*blue
, uint32_t start
, uint32_t size
)
6635 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
6636 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6638 for (i
= start
; i
< end
; i
++) {
6639 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
6640 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
6641 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
6644 intel_crtc_load_lut(crtc
);
6647 /* VESA 640x480x72Hz mode to set on the pipe */
6648 static struct drm_display_mode load_detect_mode
= {
6649 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
6650 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
6653 static struct drm_framebuffer
*
6654 intel_framebuffer_create(struct drm_device
*dev
,
6655 struct drm_mode_fb_cmd2
*mode_cmd
,
6656 struct drm_i915_gem_object
*obj
)
6658 struct intel_framebuffer
*intel_fb
;
6661 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
6663 drm_gem_object_unreference_unlocked(&obj
->base
);
6664 return ERR_PTR(-ENOMEM
);
6667 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
6669 drm_gem_object_unreference_unlocked(&obj
->base
);
6671 return ERR_PTR(ret
);
6674 return &intel_fb
->base
;
6678 intel_framebuffer_pitch_for_width(int width
, int bpp
)
6680 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
6681 return ALIGN(pitch
, 64);
6685 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
6687 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
6688 return ALIGN(pitch
* mode
->vdisplay
, PAGE_SIZE
);
6691 static struct drm_framebuffer
*
6692 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
6693 struct drm_display_mode
*mode
,
6696 struct drm_i915_gem_object
*obj
;
6697 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
6699 obj
= i915_gem_alloc_object(dev
,
6700 intel_framebuffer_size_for_mode(mode
, bpp
));
6702 return ERR_PTR(-ENOMEM
);
6704 mode_cmd
.width
= mode
->hdisplay
;
6705 mode_cmd
.height
= mode
->vdisplay
;
6706 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
6708 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
6710 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
6713 static struct drm_framebuffer
*
6714 mode_fits_in_fbdev(struct drm_device
*dev
,
6715 struct drm_display_mode
*mode
)
6717 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6718 struct drm_i915_gem_object
*obj
;
6719 struct drm_framebuffer
*fb
;
6721 if (dev_priv
->fbdev
== NULL
)
6724 obj
= dev_priv
->fbdev
->ifb
.obj
;
6728 fb
= &dev_priv
->fbdev
->ifb
.base
;
6729 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
6730 fb
->bits_per_pixel
))
6733 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
6739 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
6740 struct drm_display_mode
*mode
,
6741 struct intel_load_detect_pipe
*old
)
6743 struct intel_crtc
*intel_crtc
;
6744 struct intel_encoder
*intel_encoder
=
6745 intel_attached_encoder(connector
);
6746 struct drm_crtc
*possible_crtc
;
6747 struct drm_encoder
*encoder
= &intel_encoder
->base
;
6748 struct drm_crtc
*crtc
= NULL
;
6749 struct drm_device
*dev
= encoder
->dev
;
6750 struct drm_framebuffer
*fb
;
6753 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6754 connector
->base
.id
, drm_get_connector_name(connector
),
6755 encoder
->base
.id
, drm_get_encoder_name(encoder
));
6758 * Algorithm gets a little messy:
6760 * - if the connector already has an assigned crtc, use it (but make
6761 * sure it's on first)
6763 * - try to find the first unused crtc that can drive this connector,
6764 * and use that if we find one
6767 /* See if we already have a CRTC for this connector */
6768 if (encoder
->crtc
) {
6769 crtc
= encoder
->crtc
;
6771 mutex_lock(&crtc
->mutex
);
6773 old
->dpms_mode
= connector
->dpms
;
6774 old
->load_detect_temp
= false;
6776 /* Make sure the crtc and connector are running */
6777 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
6778 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
6783 /* Find an unused one (if possible) */
6784 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
6786 if (!(encoder
->possible_crtcs
& (1 << i
)))
6788 if (!possible_crtc
->enabled
) {
6789 crtc
= possible_crtc
;
6795 * If we didn't find an unused CRTC, don't use any.
6798 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6802 mutex_lock(&crtc
->mutex
);
6803 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
6804 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
6806 intel_crtc
= to_intel_crtc(crtc
);
6807 old
->dpms_mode
= connector
->dpms
;
6808 old
->load_detect_temp
= true;
6809 old
->release_fb
= NULL
;
6812 mode
= &load_detect_mode
;
6814 /* We need a framebuffer large enough to accommodate all accesses
6815 * that the plane may generate whilst we perform load detection.
6816 * We can not rely on the fbcon either being present (we get called
6817 * during its initialisation to detect all boot displays, or it may
6818 * not even exist) or that it is large enough to satisfy the
6821 fb
= mode_fits_in_fbdev(dev
, mode
);
6823 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6824 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
6825 old
->release_fb
= fb
;
6827 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6829 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6830 mutex_unlock(&crtc
->mutex
);
6834 if (intel_set_mode(crtc
, mode
, 0, 0, fb
)) {
6835 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6836 if (old
->release_fb
)
6837 old
->release_fb
->funcs
->destroy(old
->release_fb
);
6838 mutex_unlock(&crtc
->mutex
);
6842 /* let the connector get through one full cycle before testing */
6843 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
6847 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
6848 struct intel_load_detect_pipe
*old
)
6850 struct intel_encoder
*intel_encoder
=
6851 intel_attached_encoder(connector
);
6852 struct drm_encoder
*encoder
= &intel_encoder
->base
;
6853 struct drm_crtc
*crtc
= encoder
->crtc
;
6855 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6856 connector
->base
.id
, drm_get_connector_name(connector
),
6857 encoder
->base
.id
, drm_get_encoder_name(encoder
));
6859 if (old
->load_detect_temp
) {
6860 to_intel_connector(connector
)->new_encoder
= NULL
;
6861 intel_encoder
->new_crtc
= NULL
;
6862 intel_set_mode(crtc
, NULL
, 0, 0, NULL
);
6864 if (old
->release_fb
) {
6865 drm_framebuffer_unregister_private(old
->release_fb
);
6866 drm_framebuffer_unreference(old
->release_fb
);
6869 mutex_unlock(&crtc
->mutex
);
6873 /* Switch crtc and encoder back off if necessary */
6874 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
6875 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
6877 mutex_unlock(&crtc
->mutex
);
6880 /* Returns the clock of the currently programmed mode of the given pipe. */
6881 static int intel_crtc_clock_get(struct drm_device
*dev
, struct drm_crtc
*crtc
)
6883 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6884 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6885 int pipe
= intel_crtc
->pipe
;
6886 u32 dpll
= I915_READ(DPLL(pipe
));
6888 intel_clock_t clock
;
6890 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
6891 fp
= I915_READ(FP0(pipe
));
6893 fp
= I915_READ(FP1(pipe
));
6895 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
6896 if (IS_PINEVIEW(dev
)) {
6897 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
6898 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
6900 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
6901 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
6904 if (!IS_GEN2(dev
)) {
6905 if (IS_PINEVIEW(dev
))
6906 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
6907 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
6909 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
6910 DPLL_FPA01_P1_POST_DIV_SHIFT
);
6912 switch (dpll
& DPLL_MODE_MASK
) {
6913 case DPLLB_MODE_DAC_SERIAL
:
6914 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
6917 case DPLLB_MODE_LVDS
:
6918 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
6922 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6923 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
6927 if (IS_PINEVIEW(dev
))
6928 pineview_clock(96000, &clock
);
6930 i9xx_clock(96000, &clock
);
6932 bool is_lvds
= (pipe
== 1) && (I915_READ(LVDS
) & LVDS_PORT_EN
);
6935 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
6936 DPLL_FPA01_P1_POST_DIV_SHIFT
);
6939 if ((dpll
& PLL_REF_INPUT_MASK
) ==
6940 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
6941 /* XXX: might not be 66MHz */
6942 i9xx_clock(66000, &clock
);
6944 i9xx_clock(48000, &clock
);
6946 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
6949 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
6950 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
6952 if (dpll
& PLL_P2_DIVIDE_BY_4
)
6957 i9xx_clock(48000, &clock
);
6961 /* XXX: It would be nice to validate the clocks, but we can't reuse
6962 * i830PllIsValid() because it relies on the xf86_config connector
6963 * configuration being accurate, which it isn't necessarily.
6969 /** Returns the currently programmed mode of the given pipe. */
6970 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
6971 struct drm_crtc
*crtc
)
6973 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6974 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6975 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
6976 struct drm_display_mode
*mode
;
6977 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
6978 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
6979 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
6980 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
6982 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
6986 mode
->clock
= intel_crtc_clock_get(dev
, crtc
);
6987 mode
->hdisplay
= (htot
& 0xffff) + 1;
6988 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
6989 mode
->hsync_start
= (hsync
& 0xffff) + 1;
6990 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
6991 mode
->vdisplay
= (vtot
& 0xffff) + 1;
6992 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
6993 mode
->vsync_start
= (vsync
& 0xffff) + 1;
6994 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
6996 drm_mode_set_name(mode
);
7001 static void intel_increase_pllclock(struct drm_crtc
*crtc
)
7003 struct drm_device
*dev
= crtc
->dev
;
7004 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7005 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7006 int pipe
= intel_crtc
->pipe
;
7007 int dpll_reg
= DPLL(pipe
);
7010 if (HAS_PCH_SPLIT(dev
))
7013 if (!dev_priv
->lvds_downclock_avail
)
7016 dpll
= I915_READ(dpll_reg
);
7017 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
7018 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7020 assert_panel_unlocked(dev_priv
, pipe
);
7022 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
7023 I915_WRITE(dpll_reg
, dpll
);
7024 intel_wait_for_vblank(dev
, pipe
);
7026 dpll
= I915_READ(dpll_reg
);
7027 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
7028 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7032 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
7034 struct drm_device
*dev
= crtc
->dev
;
7035 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7036 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7038 if (HAS_PCH_SPLIT(dev
))
7041 if (!dev_priv
->lvds_downclock_avail
)
7045 * Since this is called by a timer, we should never get here in
7048 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
7049 int pipe
= intel_crtc
->pipe
;
7050 int dpll_reg
= DPLL(pipe
);
7053 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7055 assert_panel_unlocked(dev_priv
, pipe
);
7057 dpll
= I915_READ(dpll_reg
);
7058 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
7059 I915_WRITE(dpll_reg
, dpll
);
7060 intel_wait_for_vblank(dev
, pipe
);
7061 dpll
= I915_READ(dpll_reg
);
7062 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
7063 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7068 void intel_mark_busy(struct drm_device
*dev
)
7070 i915_update_gfx_val(dev
->dev_private
);
7073 void intel_mark_idle(struct drm_device
*dev
)
7075 struct drm_crtc
*crtc
;
7077 if (!i915_powersave
)
7080 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
7084 intel_decrease_pllclock(crtc
);
7088 void intel_mark_fb_busy(struct drm_i915_gem_object
*obj
,
7089 struct intel_ring_buffer
*ring
)
7091 struct drm_device
*dev
= obj
->base
.dev
;
7092 struct drm_crtc
*crtc
;
7094 if (!i915_powersave
)
7097 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
7101 if (to_intel_framebuffer(crtc
->fb
)->obj
!= obj
)
7104 intel_increase_pllclock(crtc
);
7105 if (ring
&& intel_fbc_enabled(dev
))
7106 ring
->fbc_dirty
= true;
7110 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
7112 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7113 struct drm_device
*dev
= crtc
->dev
;
7114 struct intel_unpin_work
*work
;
7115 unsigned long flags
;
7117 spin_lock_irqsave(&dev
->event_lock
, flags
);
7118 work
= intel_crtc
->unpin_work
;
7119 intel_crtc
->unpin_work
= NULL
;
7120 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7123 cancel_work_sync(&work
->work
);
7127 intel_crtc_cursor_set(crtc
, NULL
, 0, 0, 0);
7129 drm_crtc_cleanup(crtc
);
7134 static void intel_unpin_work_fn(struct work_struct
*__work
)
7136 struct intel_unpin_work
*work
=
7137 container_of(__work
, struct intel_unpin_work
, work
);
7138 struct drm_device
*dev
= work
->crtc
->dev
;
7140 mutex_lock(&dev
->struct_mutex
);
7141 intel_unpin_fb_obj(work
->old_fb_obj
);
7142 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
7143 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
7145 intel_update_fbc(dev
);
7146 mutex_unlock(&dev
->struct_mutex
);
7148 BUG_ON(atomic_read(&to_intel_crtc(work
->crtc
)->unpin_work_count
) == 0);
7149 atomic_dec(&to_intel_crtc(work
->crtc
)->unpin_work_count
);
7154 static void do_intel_finish_page_flip(struct drm_device
*dev
,
7155 struct drm_crtc
*crtc
)
7157 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7158 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7159 struct intel_unpin_work
*work
;
7160 unsigned long flags
;
7162 /* Ignore early vblank irqs */
7163 if (intel_crtc
== NULL
)
7166 spin_lock_irqsave(&dev
->event_lock
, flags
);
7167 work
= intel_crtc
->unpin_work
;
7169 /* Ensure we don't miss a work->pending update ... */
7172 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
7173 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7177 /* and that the unpin work is consistent wrt ->pending. */
7180 intel_crtc
->unpin_work
= NULL
;
7183 drm_send_vblank_event(dev
, intel_crtc
->pipe
, work
->event
);
7185 drm_vblank_put(dev
, intel_crtc
->pipe
);
7187 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7189 wake_up_all(&dev_priv
->pending_flip_queue
);
7191 queue_work(dev_priv
->wq
, &work
->work
);
7193 trace_i915_flip_complete(intel_crtc
->plane
, work
->pending_flip_obj
);
7196 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
7198 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7199 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
7201 do_intel_finish_page_flip(dev
, crtc
);
7204 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
7206 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7207 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
7209 do_intel_finish_page_flip(dev
, crtc
);
7212 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
7214 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7215 struct intel_crtc
*intel_crtc
=
7216 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
7217 unsigned long flags
;
7219 /* NB: An MMIO update of the plane base pointer will also
7220 * generate a page-flip completion irq, i.e. every modeset
7221 * is also accompanied by a spurious intel_prepare_page_flip().
7223 spin_lock_irqsave(&dev
->event_lock
, flags
);
7224 if (intel_crtc
->unpin_work
)
7225 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
7226 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7229 inline static void intel_mark_page_flip_active(struct intel_crtc
*intel_crtc
)
7231 /* Ensure that the work item is consistent when activating it ... */
7233 atomic_set(&intel_crtc
->unpin_work
->pending
, INTEL_FLIP_PENDING
);
7234 /* and that it is marked active as soon as the irq could fire. */
7238 static int intel_gen2_queue_flip(struct drm_device
*dev
,
7239 struct drm_crtc
*crtc
,
7240 struct drm_framebuffer
*fb
,
7241 struct drm_i915_gem_object
*obj
)
7243 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7244 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7246 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7249 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7253 ret
= intel_ring_begin(ring
, 6);
7257 /* Can't queue multiple flips, so wait for the previous
7258 * one to finish before executing the next.
7260 if (intel_crtc
->plane
)
7261 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
7263 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
7264 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
7265 intel_ring_emit(ring
, MI_NOOP
);
7266 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7267 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7268 intel_ring_emit(ring
, fb
->pitches
[0]);
7269 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
7270 intel_ring_emit(ring
, 0); /* aux display base address, unused */
7272 intel_mark_page_flip_active(intel_crtc
);
7273 intel_ring_advance(ring
);
7277 intel_unpin_fb_obj(obj
);
7282 static int intel_gen3_queue_flip(struct drm_device
*dev
,
7283 struct drm_crtc
*crtc
,
7284 struct drm_framebuffer
*fb
,
7285 struct drm_i915_gem_object
*obj
)
7287 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7288 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7290 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7293 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7297 ret
= intel_ring_begin(ring
, 6);
7301 if (intel_crtc
->plane
)
7302 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
7304 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
7305 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
7306 intel_ring_emit(ring
, MI_NOOP
);
7307 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
7308 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7309 intel_ring_emit(ring
, fb
->pitches
[0]);
7310 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
7311 intel_ring_emit(ring
, MI_NOOP
);
7313 intel_mark_page_flip_active(intel_crtc
);
7314 intel_ring_advance(ring
);
7318 intel_unpin_fb_obj(obj
);
7323 static int intel_gen4_queue_flip(struct drm_device
*dev
,
7324 struct drm_crtc
*crtc
,
7325 struct drm_framebuffer
*fb
,
7326 struct drm_i915_gem_object
*obj
)
7328 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7329 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7330 uint32_t pf
, pipesrc
;
7331 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7334 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7338 ret
= intel_ring_begin(ring
, 4);
7342 /* i965+ uses the linear or tiled offsets from the
7343 * Display Registers (which do not change across a page-flip)
7344 * so we need only reprogram the base address.
7346 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7347 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7348 intel_ring_emit(ring
, fb
->pitches
[0]);
7349 intel_ring_emit(ring
,
7350 (obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
) |
7353 /* XXX Enabling the panel-fitter across page-flip is so far
7354 * untested on non-native modes, so ignore it for now.
7355 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7358 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
7359 intel_ring_emit(ring
, pf
| pipesrc
);
7361 intel_mark_page_flip_active(intel_crtc
);
7362 intel_ring_advance(ring
);
7366 intel_unpin_fb_obj(obj
);
7371 static int intel_gen6_queue_flip(struct drm_device
*dev
,
7372 struct drm_crtc
*crtc
,
7373 struct drm_framebuffer
*fb
,
7374 struct drm_i915_gem_object
*obj
)
7376 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7377 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7378 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7379 uint32_t pf
, pipesrc
;
7382 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7386 ret
= intel_ring_begin(ring
, 4);
7390 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7391 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7392 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
7393 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
7395 /* Contrary to the suggestions in the documentation,
7396 * "Enable Panel Fitter" does not seem to be required when page
7397 * flipping with a non-native mode, and worse causes a normal
7399 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7402 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
7403 intel_ring_emit(ring
, pf
| pipesrc
);
7405 intel_mark_page_flip_active(intel_crtc
);
7406 intel_ring_advance(ring
);
7410 intel_unpin_fb_obj(obj
);
7416 * On gen7 we currently use the blit ring because (in early silicon at least)
7417 * the render ring doesn't give us interrpts for page flip completion, which
7418 * means clients will hang after the first flip is queued. Fortunately the
7419 * blit ring generates interrupts properly, so use it instead.
7421 static int intel_gen7_queue_flip(struct drm_device
*dev
,
7422 struct drm_crtc
*crtc
,
7423 struct drm_framebuffer
*fb
,
7424 struct drm_i915_gem_object
*obj
)
7426 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7427 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7428 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[BCS
];
7429 uint32_t plane_bit
= 0;
7432 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7436 switch(intel_crtc
->plane
) {
7438 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
7441 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
7444 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
7447 WARN_ONCE(1, "unknown plane in flip command\n");
7452 ret
= intel_ring_begin(ring
, 4);
7456 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
7457 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
7458 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
7459 intel_ring_emit(ring
, (MI_NOOP
));
7461 intel_mark_page_flip_active(intel_crtc
);
7462 intel_ring_advance(ring
);
7466 intel_unpin_fb_obj(obj
);
7471 static int intel_default_queue_flip(struct drm_device
*dev
,
7472 struct drm_crtc
*crtc
,
7473 struct drm_framebuffer
*fb
,
7474 struct drm_i915_gem_object
*obj
)
7479 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
7480 struct drm_framebuffer
*fb
,
7481 struct drm_pending_vblank_event
*event
)
7483 struct drm_device
*dev
= crtc
->dev
;
7484 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7485 struct drm_framebuffer
*old_fb
= crtc
->fb
;
7486 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(fb
)->obj
;
7487 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7488 struct intel_unpin_work
*work
;
7489 unsigned long flags
;
7492 /* Can't change pixel format via MI display flips. */
7493 if (fb
->pixel_format
!= crtc
->fb
->pixel_format
)
7497 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7498 * Note that pitch changes could also affect these register.
7500 if (INTEL_INFO(dev
)->gen
> 3 &&
7501 (fb
->offsets
[0] != crtc
->fb
->offsets
[0] ||
7502 fb
->pitches
[0] != crtc
->fb
->pitches
[0]))
7505 work
= kzalloc(sizeof *work
, GFP_KERNEL
);
7509 work
->event
= event
;
7511 work
->old_fb_obj
= to_intel_framebuffer(old_fb
)->obj
;
7512 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
7514 ret
= drm_vblank_get(dev
, intel_crtc
->pipe
);
7518 /* We borrow the event spin lock for protecting unpin_work */
7519 spin_lock_irqsave(&dev
->event_lock
, flags
);
7520 if (intel_crtc
->unpin_work
) {
7521 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7523 drm_vblank_put(dev
, intel_crtc
->pipe
);
7525 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7528 intel_crtc
->unpin_work
= work
;
7529 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7531 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
7532 flush_workqueue(dev_priv
->wq
);
7534 ret
= i915_mutex_lock_interruptible(dev
);
7538 /* Reference the objects for the scheduled work. */
7539 drm_gem_object_reference(&work
->old_fb_obj
->base
);
7540 drm_gem_object_reference(&obj
->base
);
7544 work
->pending_flip_obj
= obj
;
7546 work
->enable_stall_check
= true;
7548 atomic_inc(&intel_crtc
->unpin_work_count
);
7549 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
7551 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
);
7553 goto cleanup_pending
;
7555 intel_disable_fbc(dev
);
7556 intel_mark_fb_busy(obj
, NULL
);
7557 mutex_unlock(&dev
->struct_mutex
);
7559 trace_i915_flip_request(intel_crtc
->plane
, obj
);
7564 atomic_dec(&intel_crtc
->unpin_work_count
);
7566 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
7567 drm_gem_object_unreference(&obj
->base
);
7568 mutex_unlock(&dev
->struct_mutex
);
7571 spin_lock_irqsave(&dev
->event_lock
, flags
);
7572 intel_crtc
->unpin_work
= NULL
;
7573 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7575 drm_vblank_put(dev
, intel_crtc
->pipe
);
7582 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
7583 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
7584 .load_lut
= intel_crtc_load_lut
,
7587 static bool intel_encoder_crtc_ok(struct drm_encoder
*encoder
,
7588 struct drm_crtc
*crtc
)
7590 struct drm_device
*dev
;
7591 struct drm_crtc
*tmp
;
7594 WARN(!crtc
, "checking null crtc?\n");
7598 list_for_each_entry(tmp
, &dev
->mode_config
.crtc_list
, head
) {
7604 if (encoder
->possible_crtcs
& crtc_mask
)
7610 * intel_modeset_update_staged_output_state
7612 * Updates the staged output configuration state, e.g. after we've read out the
7615 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
7617 struct intel_encoder
*encoder
;
7618 struct intel_connector
*connector
;
7620 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7622 connector
->new_encoder
=
7623 to_intel_encoder(connector
->base
.encoder
);
7626 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7629 to_intel_crtc(encoder
->base
.crtc
);
7634 * intel_modeset_commit_output_state
7636 * This function copies the stage display pipe configuration to the real one.
7638 static void intel_modeset_commit_output_state(struct drm_device
*dev
)
7640 struct intel_encoder
*encoder
;
7641 struct intel_connector
*connector
;
7643 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7645 connector
->base
.encoder
= &connector
->new_encoder
->base
;
7648 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7650 encoder
->base
.crtc
= &encoder
->new_crtc
->base
;
7655 connected_sink_compute_bpp(struct intel_connector
* connector
,
7656 struct intel_crtc_config
*pipe_config
)
7658 int bpp
= pipe_config
->pipe_bpp
;
7660 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7661 connector
->base
.base
.id
,
7662 drm_get_connector_name(&connector
->base
));
7664 /* Don't use an invalid EDID bpc value */
7665 if (connector
->base
.display_info
.bpc
&&
7666 connector
->base
.display_info
.bpc
* 3 < bpp
) {
7667 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7668 bpp
, connector
->base
.display_info
.bpc
*3);
7669 pipe_config
->pipe_bpp
= connector
->base
.display_info
.bpc
*3;
7672 /* Clamp bpp to 8 on screens without EDID 1.4 */
7673 if (connector
->base
.display_info
.bpc
== 0 && bpp
> 24) {
7674 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7676 pipe_config
->pipe_bpp
= 24;
7681 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
7682 struct drm_framebuffer
*fb
,
7683 struct intel_crtc_config
*pipe_config
)
7685 struct drm_device
*dev
= crtc
->base
.dev
;
7686 struct intel_connector
*connector
;
7689 switch (fb
->pixel_format
) {
7691 bpp
= 8*3; /* since we go through a colormap */
7693 case DRM_FORMAT_XRGB1555
:
7694 case DRM_FORMAT_ARGB1555
:
7695 /* checked in intel_framebuffer_init already */
7696 if (WARN_ON(INTEL_INFO(dev
)->gen
> 3))
7698 case DRM_FORMAT_RGB565
:
7699 bpp
= 6*3; /* min is 18bpp */
7701 case DRM_FORMAT_XBGR8888
:
7702 case DRM_FORMAT_ABGR8888
:
7703 /* checked in intel_framebuffer_init already */
7704 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
7706 case DRM_FORMAT_XRGB8888
:
7707 case DRM_FORMAT_ARGB8888
:
7710 case DRM_FORMAT_XRGB2101010
:
7711 case DRM_FORMAT_ARGB2101010
:
7712 case DRM_FORMAT_XBGR2101010
:
7713 case DRM_FORMAT_ABGR2101010
:
7714 /* checked in intel_framebuffer_init already */
7715 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
7719 /* TODO: gen4+ supports 16 bpc floating point, too. */
7721 DRM_DEBUG_KMS("unsupported depth\n");
7725 pipe_config
->pipe_bpp
= bpp
;
7727 /* Clamp display bpp to EDID value */
7728 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7730 if (!connector
->new_encoder
||
7731 connector
->new_encoder
->new_crtc
!= crtc
)
7734 connected_sink_compute_bpp(connector
, pipe_config
);
7740 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
7741 struct intel_crtc_config
*pipe_config
,
7742 const char *context
)
7744 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc
->base
.base
.id
,
7745 context
, pipe_name(crtc
->pipe
));
7747 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config
->cpu_transcoder
));
7748 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7749 pipe_config
->pipe_bpp
, pipe_config
->dither
);
7750 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7751 pipe_config
->has_pch_encoder
,
7752 pipe_config
->fdi_lanes
,
7753 pipe_config
->fdi_m_n
.gmch_m
, pipe_config
->fdi_m_n
.gmch_n
,
7754 pipe_config
->fdi_m_n
.link_m
, pipe_config
->fdi_m_n
.link_n
,
7755 pipe_config
->fdi_m_n
.tu
);
7756 DRM_DEBUG_KMS("requested mode:\n");
7757 drm_mode_debug_printmodeline(&pipe_config
->requested_mode
);
7758 DRM_DEBUG_KMS("adjusted mode:\n");
7759 drm_mode_debug_printmodeline(&pipe_config
->adjusted_mode
);
7760 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7761 pipe_config
->gmch_pfit
.control
,
7762 pipe_config
->gmch_pfit
.pgm_ratios
,
7763 pipe_config
->gmch_pfit
.lvds_border_bits
);
7764 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7765 pipe_config
->pch_pfit
.pos
,
7766 pipe_config
->pch_pfit
.size
);
7767 DRM_DEBUG_KMS("ips: %i\n", pipe_config
->ips_enabled
);
7770 static bool check_encoder_cloning(struct drm_crtc
*crtc
)
7772 int num_encoders
= 0;
7773 bool uncloneable_encoders
= false;
7774 struct intel_encoder
*encoder
;
7776 list_for_each_entry(encoder
, &crtc
->dev
->mode_config
.encoder_list
,
7778 if (&encoder
->new_crtc
->base
!= crtc
)
7782 if (!encoder
->cloneable
)
7783 uncloneable_encoders
= true;
7786 return !(num_encoders
> 1 && uncloneable_encoders
);
7789 static struct intel_crtc_config
*
7790 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
7791 struct drm_framebuffer
*fb
,
7792 struct drm_display_mode
*mode
)
7794 struct drm_device
*dev
= crtc
->dev
;
7795 struct drm_encoder_helper_funcs
*encoder_funcs
;
7796 struct intel_encoder
*encoder
;
7797 struct intel_crtc_config
*pipe_config
;
7798 int plane_bpp
, ret
= -EINVAL
;
7801 if (!check_encoder_cloning(crtc
)) {
7802 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
7803 return ERR_PTR(-EINVAL
);
7806 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
7808 return ERR_PTR(-ENOMEM
);
7810 drm_mode_copy(&pipe_config
->adjusted_mode
, mode
);
7811 drm_mode_copy(&pipe_config
->requested_mode
, mode
);
7812 pipe_config
->cpu_transcoder
= to_intel_crtc(crtc
)->pipe
;
7813 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
7815 /* Compute a starting value for pipe_config->pipe_bpp taking the source
7816 * plane pixel format and any sink constraints into account. Returns the
7817 * source plane bpp so that dithering can be selected on mismatches
7818 * after encoders and crtc also have had their say. */
7819 plane_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
7825 /* Ensure the port clock defaults are reset when retrying. */
7826 pipe_config
->port_clock
= 0;
7827 pipe_config
->pixel_multiplier
= 1;
7829 /* Pass our mode to the connectors and the CRTC to give them a chance to
7830 * adjust it according to limitations or connector properties, and also
7831 * a chance to reject the mode entirely.
7833 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7836 if (&encoder
->new_crtc
->base
!= crtc
)
7839 if (encoder
->compute_config
) {
7840 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
7841 DRM_DEBUG_KMS("Encoder config failure\n");
7848 encoder_funcs
= encoder
->base
.helper_private
;
7849 if (!(encoder_funcs
->mode_fixup(&encoder
->base
,
7850 &pipe_config
->requested_mode
,
7851 &pipe_config
->adjusted_mode
))) {
7852 DRM_DEBUG_KMS("Encoder fixup failed\n");
7857 /* Set default port clock if not overwritten by the encoder. Needs to be
7858 * done afterwards in case the encoder adjusts the mode. */
7859 if (!pipe_config
->port_clock
)
7860 pipe_config
->port_clock
= pipe_config
->adjusted_mode
.clock
;
7862 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
7864 DRM_DEBUG_KMS("CRTC fixup failed\n");
7869 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
7874 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7879 pipe_config
->dither
= pipe_config
->pipe_bpp
!= plane_bpp
;
7880 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7881 plane_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
7886 return ERR_PTR(ret
);
7889 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7890 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7892 intel_modeset_affected_pipes(struct drm_crtc
*crtc
, unsigned *modeset_pipes
,
7893 unsigned *prepare_pipes
, unsigned *disable_pipes
)
7895 struct intel_crtc
*intel_crtc
;
7896 struct drm_device
*dev
= crtc
->dev
;
7897 struct intel_encoder
*encoder
;
7898 struct intel_connector
*connector
;
7899 struct drm_crtc
*tmp_crtc
;
7901 *disable_pipes
= *modeset_pipes
= *prepare_pipes
= 0;
7903 /* Check which crtcs have changed outputs connected to them, these need
7904 * to be part of the prepare_pipes mask. We don't (yet) support global
7905 * modeset across multiple crtcs, so modeset_pipes will only have one
7906 * bit set at most. */
7907 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7909 if (connector
->base
.encoder
== &connector
->new_encoder
->base
)
7912 if (connector
->base
.encoder
) {
7913 tmp_crtc
= connector
->base
.encoder
->crtc
;
7915 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
7918 if (connector
->new_encoder
)
7920 1 << connector
->new_encoder
->new_crtc
->pipe
;
7923 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7925 if (encoder
->base
.crtc
== &encoder
->new_crtc
->base
)
7928 if (encoder
->base
.crtc
) {
7929 tmp_crtc
= encoder
->base
.crtc
;
7931 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
7934 if (encoder
->new_crtc
)
7935 *prepare_pipes
|= 1 << encoder
->new_crtc
->pipe
;
7938 /* Check for any pipes that will be fully disabled ... */
7939 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
7943 /* Don't try to disable disabled crtcs. */
7944 if (!intel_crtc
->base
.enabled
)
7947 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7949 if (encoder
->new_crtc
== intel_crtc
)
7954 *disable_pipes
|= 1 << intel_crtc
->pipe
;
7958 /* set_mode is also used to update properties on life display pipes. */
7959 intel_crtc
= to_intel_crtc(crtc
);
7961 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
7964 * For simplicity do a full modeset on any pipe where the output routing
7965 * changed. We could be more clever, but that would require us to be
7966 * more careful with calling the relevant encoder->mode_set functions.
7969 *modeset_pipes
= *prepare_pipes
;
7971 /* ... and mask these out. */
7972 *modeset_pipes
&= ~(*disable_pipes
);
7973 *prepare_pipes
&= ~(*disable_pipes
);
7976 * HACK: We don't (yet) fully support global modesets. intel_set_config
7977 * obies this rule, but the modeset restore mode of
7978 * intel_modeset_setup_hw_state does not.
7980 *modeset_pipes
&= 1 << intel_crtc
->pipe
;
7981 *prepare_pipes
&= 1 << intel_crtc
->pipe
;
7983 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7984 *modeset_pipes
, *prepare_pipes
, *disable_pipes
);
7987 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
7989 struct drm_encoder
*encoder
;
7990 struct drm_device
*dev
= crtc
->dev
;
7992 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
7993 if (encoder
->crtc
== crtc
)
8000 intel_modeset_update_state(struct drm_device
*dev
, unsigned prepare_pipes
)
8002 struct intel_encoder
*intel_encoder
;
8003 struct intel_crtc
*intel_crtc
;
8004 struct drm_connector
*connector
;
8006 list_for_each_entry(intel_encoder
, &dev
->mode_config
.encoder_list
,
8008 if (!intel_encoder
->base
.crtc
)
8011 intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
8013 if (prepare_pipes
& (1 << intel_crtc
->pipe
))
8014 intel_encoder
->connectors_active
= false;
8017 intel_modeset_commit_output_state(dev
);
8019 /* Update computed state. */
8020 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
8022 intel_crtc
->base
.enabled
= intel_crtc_in_use(&intel_crtc
->base
);
8025 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
8026 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
8029 intel_crtc
= to_intel_crtc(connector
->encoder
->crtc
);
8031 if (prepare_pipes
& (1 << intel_crtc
->pipe
)) {
8032 struct drm_property
*dpms_property
=
8033 dev
->mode_config
.dpms_property
;
8035 connector
->dpms
= DRM_MODE_DPMS_ON
;
8036 drm_object_property_set_value(&connector
->base
,
8040 intel_encoder
= to_intel_encoder(connector
->encoder
);
8041 intel_encoder
->connectors_active
= true;
8047 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8048 list_for_each_entry((intel_crtc), \
8049 &(dev)->mode_config.crtc_list, \
8051 if (mask & (1 <<(intel_crtc)->pipe))
8054 intel_pipe_config_compare(struct drm_device
*dev
,
8055 struct intel_crtc_config
*current_config
,
8056 struct intel_crtc_config
*pipe_config
)
8058 #define PIPE_CONF_CHECK_I(name) \
8059 if (current_config->name != pipe_config->name) { \
8060 DRM_ERROR("mismatch in " #name " " \
8061 "(expected %i, found %i)\n", \
8062 current_config->name, \
8063 pipe_config->name); \
8067 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
8068 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8069 DRM_ERROR("mismatch in " #name " " \
8070 "(expected %i, found %i)\n", \
8071 current_config->name & (mask), \
8072 pipe_config->name & (mask)); \
8076 #define PIPE_CONF_QUIRK(quirk) \
8077 ((current_config->quirks | pipe_config->quirks) & (quirk))
8079 PIPE_CONF_CHECK_I(cpu_transcoder
);
8081 PIPE_CONF_CHECK_I(has_pch_encoder
);
8082 PIPE_CONF_CHECK_I(fdi_lanes
);
8083 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_m
);
8084 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_n
);
8085 PIPE_CONF_CHECK_I(fdi_m_n
.link_m
);
8086 PIPE_CONF_CHECK_I(fdi_m_n
.link_n
);
8087 PIPE_CONF_CHECK_I(fdi_m_n
.tu
);
8089 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hdisplay
);
8090 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_htotal
);
8091 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_start
);
8092 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_end
);
8093 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_start
);
8094 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_end
);
8096 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vdisplay
);
8097 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vtotal
);
8098 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_start
);
8099 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_end
);
8100 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_start
);
8101 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_end
);
8103 if (!HAS_PCH_SPLIT(dev
))
8104 PIPE_CONF_CHECK_I(pixel_multiplier
);
8106 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8107 DRM_MODE_FLAG_INTERLACE
);
8109 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
8110 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8111 DRM_MODE_FLAG_PHSYNC
);
8112 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8113 DRM_MODE_FLAG_NHSYNC
);
8114 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8115 DRM_MODE_FLAG_PVSYNC
);
8116 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8117 DRM_MODE_FLAG_NVSYNC
);
8120 PIPE_CONF_CHECK_I(requested_mode
.hdisplay
);
8121 PIPE_CONF_CHECK_I(requested_mode
.vdisplay
);
8123 PIPE_CONF_CHECK_I(gmch_pfit
.control
);
8124 /* pfit ratios are autocomputed by the hw on gen4+ */
8125 if (INTEL_INFO(dev
)->gen
< 4)
8126 PIPE_CONF_CHECK_I(gmch_pfit
.pgm_ratios
);
8127 PIPE_CONF_CHECK_I(gmch_pfit
.lvds_border_bits
);
8128 PIPE_CONF_CHECK_I(pch_pfit
.pos
);
8129 PIPE_CONF_CHECK_I(pch_pfit
.size
);
8131 PIPE_CONF_CHECK_I(ips_enabled
);
8133 PIPE_CONF_CHECK_I(shared_dpll
);
8135 #undef PIPE_CONF_CHECK_I
8136 #undef PIPE_CONF_CHECK_FLAGS
8137 #undef PIPE_CONF_QUIRK
8143 intel_modeset_check_state(struct drm_device
*dev
)
8145 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8146 struct intel_crtc
*crtc
;
8147 struct intel_encoder
*encoder
;
8148 struct intel_connector
*connector
;
8149 struct intel_crtc_config pipe_config
;
8151 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8153 /* This also checks the encoder/connector hw state with the
8154 * ->get_hw_state callbacks. */
8155 intel_connector_check_state(connector
);
8157 WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
8158 "connector's staged encoder doesn't match current encoder\n");
8161 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8163 bool enabled
= false;
8164 bool active
= false;
8165 enum pipe pipe
, tracked_pipe
;
8167 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8168 encoder
->base
.base
.id
,
8169 drm_get_encoder_name(&encoder
->base
));
8171 WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
8172 "encoder's stage crtc doesn't match current crtc\n");
8173 WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
8174 "encoder's active_connectors set, but no crtc\n");
8176 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8178 if (connector
->base
.encoder
!= &encoder
->base
)
8181 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
8184 WARN(!!encoder
->base
.crtc
!= enabled
,
8185 "encoder's enabled state mismatch "
8186 "(expected %i, found %i)\n",
8187 !!encoder
->base
.crtc
, enabled
);
8188 WARN(active
&& !encoder
->base
.crtc
,
8189 "active encoder with no crtc\n");
8191 WARN(encoder
->connectors_active
!= active
,
8192 "encoder's computed active state doesn't match tracked active state "
8193 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
8195 active
= encoder
->get_hw_state(encoder
, &pipe
);
8196 WARN(active
!= encoder
->connectors_active
,
8197 "encoder's hw state doesn't match sw tracking "
8198 "(expected %i, found %i)\n",
8199 encoder
->connectors_active
, active
);
8201 if (!encoder
->base
.crtc
)
8204 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
8205 WARN(active
&& pipe
!= tracked_pipe
,
8206 "active encoder's pipe doesn't match"
8207 "(expected %i, found %i)\n",
8208 tracked_pipe
, pipe
);
8212 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
8214 bool enabled
= false;
8215 bool active
= false;
8217 memset(&pipe_config
, 0, sizeof(pipe_config
));
8219 DRM_DEBUG_KMS("[CRTC:%d]\n",
8220 crtc
->base
.base
.id
);
8222 WARN(crtc
->active
&& !crtc
->base
.enabled
,
8223 "active crtc, but not enabled in sw tracking\n");
8225 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8227 if (encoder
->base
.crtc
!= &crtc
->base
)
8230 if (encoder
->connectors_active
)
8234 WARN(active
!= crtc
->active
,
8235 "crtc's computed active state doesn't match tracked active state "
8236 "(expected %i, found %i)\n", active
, crtc
->active
);
8237 WARN(enabled
!= crtc
->base
.enabled
,
8238 "crtc's computed enabled state doesn't match tracked enabled state "
8239 "(expected %i, found %i)\n", enabled
, crtc
->base
.enabled
);
8241 active
= dev_priv
->display
.get_pipe_config(crtc
,
8243 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8245 if (encoder
->base
.crtc
!= &crtc
->base
)
8247 if (encoder
->get_config
)
8248 encoder
->get_config(encoder
, &pipe_config
);
8251 WARN(crtc
->active
!= active
,
8252 "crtc active state doesn't match with hw state "
8253 "(expected %i, found %i)\n", crtc
->active
, active
);
8256 !intel_pipe_config_compare(dev
, &crtc
->config
, &pipe_config
)) {
8257 WARN(1, "pipe state doesn't match!\n");
8258 intel_dump_pipe_config(crtc
, &pipe_config
,
8260 intel_dump_pipe_config(crtc
, &crtc
->config
,
8266 static int __intel_set_mode(struct drm_crtc
*crtc
,
8267 struct drm_display_mode
*mode
,
8268 int x
, int y
, struct drm_framebuffer
*fb
)
8270 struct drm_device
*dev
= crtc
->dev
;
8271 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8272 struct drm_display_mode
*saved_mode
, *saved_hwmode
;
8273 struct intel_crtc_config
*pipe_config
= NULL
;
8274 struct intel_crtc
*intel_crtc
;
8275 unsigned disable_pipes
, prepare_pipes
, modeset_pipes
;
8278 saved_mode
= kmalloc(2 * sizeof(*saved_mode
), GFP_KERNEL
);
8281 saved_hwmode
= saved_mode
+ 1;
8283 intel_modeset_affected_pipes(crtc
, &modeset_pipes
,
8284 &prepare_pipes
, &disable_pipes
);
8286 *saved_hwmode
= crtc
->hwmode
;
8287 *saved_mode
= crtc
->mode
;
8289 /* Hack: Because we don't (yet) support global modeset on multiple
8290 * crtcs, we don't keep track of the new mode for more than one crtc.
8291 * Hence simply check whether any bit is set in modeset_pipes in all the
8292 * pieces of code that are not yet converted to deal with mutliple crtcs
8293 * changing their mode at the same time. */
8294 if (modeset_pipes
) {
8295 pipe_config
= intel_modeset_pipe_config(crtc
, fb
, mode
);
8296 if (IS_ERR(pipe_config
)) {
8297 ret
= PTR_ERR(pipe_config
);
8302 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,
8306 for_each_intel_crtc_masked(dev
, disable_pipes
, intel_crtc
)
8307 intel_crtc_disable(&intel_crtc
->base
);
8309 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
8310 if (intel_crtc
->base
.enabled
)
8311 dev_priv
->display
.crtc_disable(&intel_crtc
->base
);
8314 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8315 * to set it here already despite that we pass it down the callchain.
8317 if (modeset_pipes
) {
8319 /* mode_set/enable/disable functions rely on a correct pipe
8321 to_intel_crtc(crtc
)->config
= *pipe_config
;
8324 /* Only after disabling all output pipelines that will be changed can we
8325 * update the the output configuration. */
8326 intel_modeset_update_state(dev
, prepare_pipes
);
8328 if (dev_priv
->display
.modeset_global_resources
)
8329 dev_priv
->display
.modeset_global_resources(dev
);
8331 /* Set up the DPLL and any encoders state that needs to adjust or depend
8334 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
8335 ret
= intel_crtc_mode_set(&intel_crtc
->base
,
8341 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8342 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
)
8343 dev_priv
->display
.crtc_enable(&intel_crtc
->base
);
8345 if (modeset_pipes
) {
8346 /* Store real post-adjustment hardware mode. */
8347 crtc
->hwmode
= pipe_config
->adjusted_mode
;
8349 /* Calculate and store various constants which
8350 * are later needed by vblank and swap-completion
8351 * timestamping. They are derived from true hwmode.
8353 drm_calc_timestamping_constants(crtc
);
8356 /* FIXME: add subpixel order */
8358 if (ret
&& crtc
->enabled
) {
8359 crtc
->hwmode
= *saved_hwmode
;
8360 crtc
->mode
= *saved_mode
;
8369 int intel_set_mode(struct drm_crtc
*crtc
,
8370 struct drm_display_mode
*mode
,
8371 int x
, int y
, struct drm_framebuffer
*fb
)
8375 ret
= __intel_set_mode(crtc
, mode
, x
, y
, fb
);
8378 intel_modeset_check_state(crtc
->dev
);
8383 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
8385 intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
, crtc
->fb
);
8388 #undef for_each_intel_crtc_masked
8390 static void intel_set_config_free(struct intel_set_config
*config
)
8395 kfree(config
->save_connector_encoders
);
8396 kfree(config
->save_encoder_crtcs
);
8400 static int intel_set_config_save_state(struct drm_device
*dev
,
8401 struct intel_set_config
*config
)
8403 struct drm_encoder
*encoder
;
8404 struct drm_connector
*connector
;
8407 config
->save_encoder_crtcs
=
8408 kcalloc(dev
->mode_config
.num_encoder
,
8409 sizeof(struct drm_crtc
*), GFP_KERNEL
);
8410 if (!config
->save_encoder_crtcs
)
8413 config
->save_connector_encoders
=
8414 kcalloc(dev
->mode_config
.num_connector
,
8415 sizeof(struct drm_encoder
*), GFP_KERNEL
);
8416 if (!config
->save_connector_encoders
)
8419 /* Copy data. Note that driver private data is not affected.
8420 * Should anything bad happen only the expected state is
8421 * restored, not the drivers personal bookkeeping.
8424 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
8425 config
->save_encoder_crtcs
[count
++] = encoder
->crtc
;
8429 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
8430 config
->save_connector_encoders
[count
++] = connector
->encoder
;
8436 static void intel_set_config_restore_state(struct drm_device
*dev
,
8437 struct intel_set_config
*config
)
8439 struct intel_encoder
*encoder
;
8440 struct intel_connector
*connector
;
8444 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
8446 to_intel_crtc(config
->save_encoder_crtcs
[count
++]);
8450 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
8451 connector
->new_encoder
=
8452 to_intel_encoder(config
->save_connector_encoders
[count
++]);
8457 intel_set_config_compute_mode_changes(struct drm_mode_set
*set
,
8458 struct intel_set_config
*config
)
8461 /* We should be able to check here if the fb has the same properties
8462 * and then just flip_or_move it */
8463 if (set
->crtc
->fb
!= set
->fb
) {
8464 /* If we have no fb then treat it as a full mode set */
8465 if (set
->crtc
->fb
== NULL
) {
8466 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8467 config
->mode_changed
= true;
8468 } else if (set
->fb
== NULL
) {
8469 config
->mode_changed
= true;
8470 } else if (set
->fb
->pixel_format
!=
8471 set
->crtc
->fb
->pixel_format
) {
8472 config
->mode_changed
= true;
8474 config
->fb_changed
= true;
8477 if (set
->fb
&& (set
->x
!= set
->crtc
->x
|| set
->y
!= set
->crtc
->y
))
8478 config
->fb_changed
= true;
8480 if (set
->mode
&& !drm_mode_equal(set
->mode
, &set
->crtc
->mode
)) {
8481 DRM_DEBUG_KMS("modes are different, full mode set\n");
8482 drm_mode_debug_printmodeline(&set
->crtc
->mode
);
8483 drm_mode_debug_printmodeline(set
->mode
);
8484 config
->mode_changed
= true;
8489 intel_modeset_stage_output_state(struct drm_device
*dev
,
8490 struct drm_mode_set
*set
,
8491 struct intel_set_config
*config
)
8493 struct drm_crtc
*new_crtc
;
8494 struct intel_connector
*connector
;
8495 struct intel_encoder
*encoder
;
8498 /* The upper layers ensure that we either disable a crtc or have a list
8499 * of connectors. For paranoia, double-check this. */
8500 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
8501 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
8504 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8506 /* Otherwise traverse passed in connector list and get encoders
8508 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
8509 if (set
->connectors
[ro
] == &connector
->base
) {
8510 connector
->new_encoder
= connector
->encoder
;
8515 /* If we disable the crtc, disable all its connectors. Also, if
8516 * the connector is on the changing crtc but not on the new
8517 * connector list, disable it. */
8518 if ((!set
->fb
|| ro
== set
->num_connectors
) &&
8519 connector
->base
.encoder
&&
8520 connector
->base
.encoder
->crtc
== set
->crtc
) {
8521 connector
->new_encoder
= NULL
;
8523 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8524 connector
->base
.base
.id
,
8525 drm_get_connector_name(&connector
->base
));
8529 if (&connector
->new_encoder
->base
!= connector
->base
.encoder
) {
8530 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8531 config
->mode_changed
= true;
8534 /* connector->new_encoder is now updated for all connectors. */
8536 /* Update crtc of enabled connectors. */
8538 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8540 if (!connector
->new_encoder
)
8543 new_crtc
= connector
->new_encoder
->base
.crtc
;
8545 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
8546 if (set
->connectors
[ro
] == &connector
->base
)
8547 new_crtc
= set
->crtc
;
8550 /* Make sure the new CRTC will work with the encoder */
8551 if (!intel_encoder_crtc_ok(&connector
->new_encoder
->base
,
8555 connector
->encoder
->new_crtc
= to_intel_crtc(new_crtc
);
8557 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8558 connector
->base
.base
.id
,
8559 drm_get_connector_name(&connector
->base
),
8563 /* Check for any encoders that needs to be disabled. */
8564 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8566 list_for_each_entry(connector
,
8567 &dev
->mode_config
.connector_list
,
8569 if (connector
->new_encoder
== encoder
) {
8570 WARN_ON(!connector
->new_encoder
->new_crtc
);
8575 encoder
->new_crtc
= NULL
;
8577 /* Only now check for crtc changes so we don't miss encoders
8578 * that will be disabled. */
8579 if (&encoder
->new_crtc
->base
!= encoder
->base
.crtc
) {
8580 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8581 config
->mode_changed
= true;
8584 /* Now we've also updated encoder->new_crtc for all encoders. */
8589 static int intel_crtc_set_config(struct drm_mode_set
*set
)
8591 struct drm_device
*dev
;
8592 struct drm_mode_set save_set
;
8593 struct intel_set_config
*config
;
8598 BUG_ON(!set
->crtc
->helper_private
);
8600 /* Enforce sane interface api - has been abused by the fb helper. */
8601 BUG_ON(!set
->mode
&& set
->fb
);
8602 BUG_ON(set
->fb
&& set
->num_connectors
== 0);
8605 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8606 set
->crtc
->base
.id
, set
->fb
->base
.id
,
8607 (int)set
->num_connectors
, set
->x
, set
->y
);
8609 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
8612 dev
= set
->crtc
->dev
;
8615 config
= kzalloc(sizeof(*config
), GFP_KERNEL
);
8619 ret
= intel_set_config_save_state(dev
, config
);
8623 save_set
.crtc
= set
->crtc
;
8624 save_set
.mode
= &set
->crtc
->mode
;
8625 save_set
.x
= set
->crtc
->x
;
8626 save_set
.y
= set
->crtc
->y
;
8627 save_set
.fb
= set
->crtc
->fb
;
8629 /* Compute whether we need a full modeset, only an fb base update or no
8630 * change at all. In the future we might also check whether only the
8631 * mode changed, e.g. for LVDS where we only change the panel fitter in
8633 intel_set_config_compute_mode_changes(set
, config
);
8635 ret
= intel_modeset_stage_output_state(dev
, set
, config
);
8639 if (config
->mode_changed
) {
8640 ret
= intel_set_mode(set
->crtc
, set
->mode
,
8641 set
->x
, set
->y
, set
->fb
);
8643 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8644 set
->crtc
->base
.id
, ret
);
8647 } else if (config
->fb_changed
) {
8648 intel_crtc_wait_for_pending_flips(set
->crtc
);
8650 ret
= intel_pipe_set_base(set
->crtc
,
8651 set
->x
, set
->y
, set
->fb
);
8654 intel_set_config_free(config
);
8659 intel_set_config_restore_state(dev
, config
);
8661 /* Try to restore the config */
8662 if (config
->mode_changed
&&
8663 intel_set_mode(save_set
.crtc
, save_set
.mode
,
8664 save_set
.x
, save_set
.y
, save_set
.fb
))
8665 DRM_ERROR("failed to restore config after modeset failure\n");
8668 intel_set_config_free(config
);
8672 static const struct drm_crtc_funcs intel_crtc_funcs
= {
8673 .cursor_set
= intel_crtc_cursor_set
,
8674 .cursor_move
= intel_crtc_cursor_move
,
8675 .gamma_set
= intel_crtc_gamma_set
,
8676 .set_config
= intel_crtc_set_config
,
8677 .destroy
= intel_crtc_destroy
,
8678 .page_flip
= intel_crtc_page_flip
,
8681 static void intel_cpu_pll_init(struct drm_device
*dev
)
8684 intel_ddi_pll_init(dev
);
8687 static void ibx_pch_dpll_enable(struct drm_i915_private
*dev_priv
,
8688 struct intel_shared_dpll
*pll
)
8692 /* PCH refclock must be enabled first */
8693 assert_pch_refclk_enabled(dev_priv
);
8695 reg
= PCH_DPLL(pll
->id
);
8696 val
= I915_READ(reg
);
8697 val
|= DPLL_VCO_ENABLE
;
8698 I915_WRITE(reg
, val
);
8703 static void ibx_pch_dpll_disable(struct drm_i915_private
*dev_priv
,
8704 struct intel_shared_dpll
*pll
)
8706 struct drm_device
*dev
= dev_priv
->dev
;
8707 struct intel_crtc
*crtc
;
8710 /* Make sure no transcoder isn't still depending on us. */
8711 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
8712 if (intel_crtc_to_shared_dpll(crtc
) == pll
)
8713 assert_pch_transcoder_disabled(dev_priv
, crtc
->pipe
);
8716 reg
= PCH_DPLL(pll
->id
);
8717 val
= I915_READ(reg
);
8718 val
&= ~DPLL_VCO_ENABLE
;
8719 I915_WRITE(reg
, val
);
8724 static char *ibx_pch_dpll_names
[] = {
8729 static void ibx_pch_dpll_init(struct drm_device
*dev
)
8731 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8734 dev_priv
->num_shared_dpll
= 2;
8736 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
8737 dev_priv
->shared_dplls
[i
].id
= i
;
8738 dev_priv
->shared_dplls
[i
].name
= ibx_pch_dpll_names
[i
];
8739 dev_priv
->shared_dplls
[i
].enable
= ibx_pch_dpll_enable
;
8740 dev_priv
->shared_dplls
[i
].disable
= ibx_pch_dpll_disable
;
8744 static void intel_shared_dpll_init(struct drm_device
*dev
)
8746 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8748 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
8749 ibx_pch_dpll_init(dev
);
8751 dev_priv
->num_shared_dpll
= 0;
8753 BUG_ON(dev_priv
->num_shared_dpll
> I915_NUM_PLLS
);
8754 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
8755 dev_priv
->num_shared_dpll
);
8758 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
8760 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8761 struct intel_crtc
*intel_crtc
;
8764 intel_crtc
= kzalloc(sizeof(struct intel_crtc
) + (INTELFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
8765 if (intel_crtc
== NULL
)
8768 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
8770 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
8771 for (i
= 0; i
< 256; i
++) {
8772 intel_crtc
->lut_r
[i
] = i
;
8773 intel_crtc
->lut_g
[i
] = i
;
8774 intel_crtc
->lut_b
[i
] = i
;
8777 /* Swap pipes & planes for FBC on pre-965 */
8778 intel_crtc
->pipe
= pipe
;
8779 intel_crtc
->plane
= pipe
;
8780 if (IS_MOBILE(dev
) && IS_GEN3(dev
)) {
8781 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8782 intel_crtc
->plane
= !pipe
;
8785 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
8786 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
8787 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
8788 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
8790 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
8793 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
8794 struct drm_file
*file
)
8796 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
8797 struct drm_mode_object
*drmmode_obj
;
8798 struct intel_crtc
*crtc
;
8800 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
8803 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
8804 DRM_MODE_OBJECT_CRTC
);
8807 DRM_ERROR("no such CRTC id\n");
8811 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
8812 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
8817 static int intel_encoder_clones(struct intel_encoder
*encoder
)
8819 struct drm_device
*dev
= encoder
->base
.dev
;
8820 struct intel_encoder
*source_encoder
;
8824 list_for_each_entry(source_encoder
,
8825 &dev
->mode_config
.encoder_list
, base
.head
) {
8827 if (encoder
== source_encoder
)
8828 index_mask
|= (1 << entry
);
8830 /* Intel hw has only one MUX where enocoders could be cloned. */
8831 if (encoder
->cloneable
&& source_encoder
->cloneable
)
8832 index_mask
|= (1 << entry
);
8840 static bool has_edp_a(struct drm_device
*dev
)
8842 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8844 if (!IS_MOBILE(dev
))
8847 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
8851 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES
) & ILK_eDP_A_DISABLE
))
8857 static void intel_setup_outputs(struct drm_device
*dev
)
8859 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8860 struct intel_encoder
*encoder
;
8861 bool dpd_is_edp
= false;
8864 has_lvds
= intel_lvds_init(dev
);
8865 if (!has_lvds
&& !HAS_PCH_SPLIT(dev
)) {
8866 /* disable the panel fitter on everything but LVDS */
8867 I915_WRITE(PFIT_CONTROL
, 0);
8871 intel_crt_init(dev
);
8876 /* Haswell uses DDI functions to detect digital outputs */
8877 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
8878 /* DDI A only supports eDP */
8880 intel_ddi_init(dev
, PORT_A
);
8882 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8884 found
= I915_READ(SFUSE_STRAP
);
8886 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
8887 intel_ddi_init(dev
, PORT_B
);
8888 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
8889 intel_ddi_init(dev
, PORT_C
);
8890 if (found
& SFUSE_STRAP_DDID_DETECTED
)
8891 intel_ddi_init(dev
, PORT_D
);
8892 } else if (HAS_PCH_SPLIT(dev
)) {
8894 dpd_is_edp
= intel_dpd_is_edp(dev
);
8897 intel_dp_init(dev
, DP_A
, PORT_A
);
8899 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
8900 /* PCH SDVOB multiplex with HDMIB */
8901 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
8903 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
8904 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
8905 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
8908 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
8909 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
8911 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
8912 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
8914 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
8915 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
8917 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
8918 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
8919 } else if (IS_VALLEYVIEW(dev
)) {
8920 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8921 if (I915_READ(VLV_DISPLAY_BASE
+ DP_C
) & DP_DETECTED
)
8922 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_C
, PORT_C
);
8924 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIB
) & SDVO_DETECTED
) {
8925 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIB
,
8927 if (I915_READ(VLV_DISPLAY_BASE
+ DP_B
) & DP_DETECTED
)
8928 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_B
, PORT_B
);
8930 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
8933 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
8934 DRM_DEBUG_KMS("probing SDVOB\n");
8935 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, true);
8936 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
8937 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8938 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
8941 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
))
8942 intel_dp_init(dev
, DP_B
, PORT_B
);
8945 /* Before G4X SDVOC doesn't have its own detect register */
8947 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
8948 DRM_DEBUG_KMS("probing SDVOC\n");
8949 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, false);
8952 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
8954 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
8955 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8956 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
8958 if (SUPPORTS_INTEGRATED_DP(dev
))
8959 intel_dp_init(dev
, DP_C
, PORT_C
);
8962 if (SUPPORTS_INTEGRATED_DP(dev
) &&
8963 (I915_READ(DP_D
) & DP_DETECTED
))
8964 intel_dp_init(dev
, DP_D
, PORT_D
);
8965 } else if (IS_GEN2(dev
))
8966 intel_dvo_init(dev
);
8968 if (SUPPORTS_TV(dev
))
8971 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
8972 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
8973 encoder
->base
.possible_clones
=
8974 intel_encoder_clones(encoder
);
8977 intel_init_pch_refclk(dev
);
8979 drm_helper_move_panel_connectors_to_head(dev
);
8982 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
8984 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
8986 drm_framebuffer_cleanup(fb
);
8987 drm_gem_object_unreference_unlocked(&intel_fb
->obj
->base
);
8992 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
8993 struct drm_file
*file
,
8994 unsigned int *handle
)
8996 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
8997 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
8999 return drm_gem_handle_create(file
, &obj
->base
, handle
);
9002 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
9003 .destroy
= intel_user_framebuffer_destroy
,
9004 .create_handle
= intel_user_framebuffer_create_handle
,
9007 int intel_framebuffer_init(struct drm_device
*dev
,
9008 struct intel_framebuffer
*intel_fb
,
9009 struct drm_mode_fb_cmd2
*mode_cmd
,
9010 struct drm_i915_gem_object
*obj
)
9014 if (obj
->tiling_mode
== I915_TILING_Y
) {
9015 DRM_DEBUG("hardware does not support tiling Y\n");
9019 if (mode_cmd
->pitches
[0] & 63) {
9020 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9021 mode_cmd
->pitches
[0]);
9025 /* FIXME <= Gen4 stride limits are bit unclear */
9026 if (mode_cmd
->pitches
[0] > 32768) {
9027 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
9028 mode_cmd
->pitches
[0]);
9032 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
9033 mode_cmd
->pitches
[0] != obj
->stride
) {
9034 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9035 mode_cmd
->pitches
[0], obj
->stride
);
9039 /* Reject formats not supported by any plane early. */
9040 switch (mode_cmd
->pixel_format
) {
9042 case DRM_FORMAT_RGB565
:
9043 case DRM_FORMAT_XRGB8888
:
9044 case DRM_FORMAT_ARGB8888
:
9046 case DRM_FORMAT_XRGB1555
:
9047 case DRM_FORMAT_ARGB1555
:
9048 if (INTEL_INFO(dev
)->gen
> 3) {
9049 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd
->pixel_format
);
9053 case DRM_FORMAT_XBGR8888
:
9054 case DRM_FORMAT_ABGR8888
:
9055 case DRM_FORMAT_XRGB2101010
:
9056 case DRM_FORMAT_ARGB2101010
:
9057 case DRM_FORMAT_XBGR2101010
:
9058 case DRM_FORMAT_ABGR2101010
:
9059 if (INTEL_INFO(dev
)->gen
< 4) {
9060 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd
->pixel_format
);
9064 case DRM_FORMAT_YUYV
:
9065 case DRM_FORMAT_UYVY
:
9066 case DRM_FORMAT_YVYU
:
9067 case DRM_FORMAT_VYUY
:
9068 if (INTEL_INFO(dev
)->gen
< 5) {
9069 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd
->pixel_format
);
9074 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd
->pixel_format
);
9078 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9079 if (mode_cmd
->offsets
[0] != 0)
9082 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
9083 intel_fb
->obj
= obj
;
9085 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
9087 DRM_ERROR("framebuffer init failed %d\n", ret
);
9094 static struct drm_framebuffer
*
9095 intel_user_framebuffer_create(struct drm_device
*dev
,
9096 struct drm_file
*filp
,
9097 struct drm_mode_fb_cmd2
*mode_cmd
)
9099 struct drm_i915_gem_object
*obj
;
9101 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
9102 mode_cmd
->handles
[0]));
9103 if (&obj
->base
== NULL
)
9104 return ERR_PTR(-ENOENT
);
9106 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
9109 static const struct drm_mode_config_funcs intel_mode_funcs
= {
9110 .fb_create
= intel_user_framebuffer_create
,
9111 .output_poll_changed
= intel_fb_output_poll_changed
,
9114 /* Set up chip specific display functions */
9115 static void intel_init_display(struct drm_device
*dev
)
9117 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9119 if (HAS_PCH_SPLIT(dev
) || IS_G4X(dev
))
9120 dev_priv
->display
.find_dpll
= g4x_find_best_dpll
;
9121 else if (IS_VALLEYVIEW(dev
))
9122 dev_priv
->display
.find_dpll
= vlv_find_best_dpll
;
9123 else if (IS_PINEVIEW(dev
))
9124 dev_priv
->display
.find_dpll
= pnv_find_best_dpll
;
9126 dev_priv
->display
.find_dpll
= i9xx_find_best_dpll
;
9129 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
9130 dev_priv
->display
.crtc_mode_set
= haswell_crtc_mode_set
;
9131 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
9132 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
9133 dev_priv
->display
.off
= haswell_crtc_off
;
9134 dev_priv
->display
.update_plane
= ironlake_update_plane
;
9135 } else if (HAS_PCH_SPLIT(dev
)) {
9136 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
9137 dev_priv
->display
.crtc_mode_set
= ironlake_crtc_mode_set
;
9138 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
9139 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
9140 dev_priv
->display
.off
= ironlake_crtc_off
;
9141 dev_priv
->display
.update_plane
= ironlake_update_plane
;
9142 } else if (IS_VALLEYVIEW(dev
)) {
9143 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
9144 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
9145 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
9146 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
9147 dev_priv
->display
.off
= i9xx_crtc_off
;
9148 dev_priv
->display
.update_plane
= i9xx_update_plane
;
9150 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
9151 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
9152 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
9153 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
9154 dev_priv
->display
.off
= i9xx_crtc_off
;
9155 dev_priv
->display
.update_plane
= i9xx_update_plane
;
9158 /* Returns the core display clock speed */
9159 if (IS_VALLEYVIEW(dev
))
9160 dev_priv
->display
.get_display_clock_speed
=
9161 valleyview_get_display_clock_speed
;
9162 else if (IS_I945G(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
9163 dev_priv
->display
.get_display_clock_speed
=
9164 i945_get_display_clock_speed
;
9165 else if (IS_I915G(dev
))
9166 dev_priv
->display
.get_display_clock_speed
=
9167 i915_get_display_clock_speed
;
9168 else if (IS_I945GM(dev
) || IS_845G(dev
) || IS_PINEVIEW_M(dev
))
9169 dev_priv
->display
.get_display_clock_speed
=
9170 i9xx_misc_get_display_clock_speed
;
9171 else if (IS_I915GM(dev
))
9172 dev_priv
->display
.get_display_clock_speed
=
9173 i915gm_get_display_clock_speed
;
9174 else if (IS_I865G(dev
))
9175 dev_priv
->display
.get_display_clock_speed
=
9176 i865_get_display_clock_speed
;
9177 else if (IS_I85X(dev
))
9178 dev_priv
->display
.get_display_clock_speed
=
9179 i855_get_display_clock_speed
;
9181 dev_priv
->display
.get_display_clock_speed
=
9182 i830_get_display_clock_speed
;
9184 if (HAS_PCH_SPLIT(dev
)) {
9186 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
9187 dev_priv
->display
.write_eld
= ironlake_write_eld
;
9188 } else if (IS_GEN6(dev
)) {
9189 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
9190 dev_priv
->display
.write_eld
= ironlake_write_eld
;
9191 } else if (IS_IVYBRIDGE(dev
)) {
9192 /* FIXME: detect B0+ stepping and use auto training */
9193 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
9194 dev_priv
->display
.write_eld
= ironlake_write_eld
;
9195 dev_priv
->display
.modeset_global_resources
=
9196 ivb_modeset_global_resources
;
9197 } else if (IS_HASWELL(dev
)) {
9198 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
9199 dev_priv
->display
.write_eld
= haswell_write_eld
;
9200 dev_priv
->display
.modeset_global_resources
=
9201 haswell_modeset_global_resources
;
9203 } else if (IS_G4X(dev
)) {
9204 dev_priv
->display
.write_eld
= g4x_write_eld
;
9207 /* Default just returns -ENODEV to indicate unsupported */
9208 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
9210 switch (INTEL_INFO(dev
)->gen
) {
9212 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
9216 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
9221 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
9225 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
9228 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
9234 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9235 * resume, or other times. This quirk makes sure that's the case for
9238 static void quirk_pipea_force(struct drm_device
*dev
)
9240 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9242 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
9243 DRM_INFO("applying pipe a force quirk\n");
9247 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9249 static void quirk_ssc_force_disable(struct drm_device
*dev
)
9251 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9252 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
9253 DRM_INFO("applying lvds SSC disable quirk\n");
9257 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9260 static void quirk_invert_brightness(struct drm_device
*dev
)
9262 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9263 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
9264 DRM_INFO("applying inverted panel brightness quirk\n");
9267 struct intel_quirk
{
9269 int subsystem_vendor
;
9270 int subsystem_device
;
9271 void (*hook
)(struct drm_device
*dev
);
9274 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9275 struct intel_dmi_quirk
{
9276 void (*hook
)(struct drm_device
*dev
);
9277 const struct dmi_system_id (*dmi_id_list
)[];
9280 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
9282 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
9286 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
9288 .dmi_id_list
= &(const struct dmi_system_id
[]) {
9290 .callback
= intel_dmi_reverse_brightness
,
9291 .ident
= "NCR Corporation",
9292 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
9293 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
9296 { } /* terminating entry */
9298 .hook
= quirk_invert_brightness
,
9302 static struct intel_quirk intel_quirks
[] = {
9303 /* HP Mini needs pipe A force quirk (LP: #322104) */
9304 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
9306 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9307 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
9309 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9310 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
9312 /* 830/845 need to leave pipe A & dpll A up */
9313 { 0x2562, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
9314 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
9316 /* Lenovo U160 cannot use SSC on LVDS */
9317 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
9319 /* Sony Vaio Y cannot use SSC on LVDS */
9320 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
9322 /* Acer Aspire 5734Z must invert backlight brightness */
9323 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
9325 /* Acer/eMachines G725 */
9326 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
9328 /* Acer/eMachines e725 */
9329 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
9331 /* Acer/Packard Bell NCL20 */
9332 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
9334 /* Acer Aspire 4736Z */
9335 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
9338 static void intel_init_quirks(struct drm_device
*dev
)
9340 struct pci_dev
*d
= dev
->pdev
;
9343 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
9344 struct intel_quirk
*q
= &intel_quirks
[i
];
9346 if (d
->device
== q
->device
&&
9347 (d
->subsystem_vendor
== q
->subsystem_vendor
||
9348 q
->subsystem_vendor
== PCI_ANY_ID
) &&
9349 (d
->subsystem_device
== q
->subsystem_device
||
9350 q
->subsystem_device
== PCI_ANY_ID
))
9353 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
9354 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
9355 intel_dmi_quirks
[i
].hook(dev
);
9359 /* Disable the VGA plane that we never use */
9360 static void i915_disable_vga(struct drm_device
*dev
)
9362 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9364 u32 vga_reg
= i915_vgacntrl_reg(dev
);
9366 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
9367 outb(SR01
, VGA_SR_INDEX
);
9368 sr1
= inb(VGA_SR_DATA
);
9369 outb(sr1
| 1<<5, VGA_SR_DATA
);
9370 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
9373 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
9374 POSTING_READ(vga_reg
);
9377 void intel_modeset_init_hw(struct drm_device
*dev
)
9379 intel_init_power_well(dev
);
9381 intel_prepare_ddi(dev
);
9383 intel_init_clock_gating(dev
);
9385 mutex_lock(&dev
->struct_mutex
);
9386 intel_enable_gt_powersave(dev
);
9387 mutex_unlock(&dev
->struct_mutex
);
9390 void intel_modeset_suspend_hw(struct drm_device
*dev
)
9392 intel_suspend_hw(dev
);
9395 void intel_modeset_init(struct drm_device
*dev
)
9397 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9400 drm_mode_config_init(dev
);
9402 dev
->mode_config
.min_width
= 0;
9403 dev
->mode_config
.min_height
= 0;
9405 dev
->mode_config
.preferred_depth
= 24;
9406 dev
->mode_config
.prefer_shadow
= 1;
9408 dev
->mode_config
.funcs
= &intel_mode_funcs
;
9410 intel_init_quirks(dev
);
9414 if (INTEL_INFO(dev
)->num_pipes
== 0)
9417 intel_init_display(dev
);
9420 dev
->mode_config
.max_width
= 2048;
9421 dev
->mode_config
.max_height
= 2048;
9422 } else if (IS_GEN3(dev
)) {
9423 dev
->mode_config
.max_width
= 4096;
9424 dev
->mode_config
.max_height
= 4096;
9426 dev
->mode_config
.max_width
= 8192;
9427 dev
->mode_config
.max_height
= 8192;
9429 dev
->mode_config
.fb_base
= dev_priv
->gtt
.mappable_base
;
9431 DRM_DEBUG_KMS("%d display pipe%s available.\n",
9432 INTEL_INFO(dev
)->num_pipes
,
9433 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
9435 for (i
= 0; i
< INTEL_INFO(dev
)->num_pipes
; i
++) {
9436 intel_crtc_init(dev
, i
);
9437 for (j
= 0; j
< dev_priv
->num_plane
; j
++) {
9438 ret
= intel_plane_init(dev
, i
, j
);
9440 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9441 pipe_name(i
), sprite_name(i
, j
), ret
);
9445 intel_cpu_pll_init(dev
);
9446 intel_shared_dpll_init(dev
);
9448 /* Just disable it once at startup */
9449 i915_disable_vga(dev
);
9450 intel_setup_outputs(dev
);
9452 /* Just in case the BIOS is doing something questionable. */
9453 intel_disable_fbc(dev
);
9457 intel_connector_break_all_links(struct intel_connector
*connector
)
9459 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
9460 connector
->base
.encoder
= NULL
;
9461 connector
->encoder
->connectors_active
= false;
9462 connector
->encoder
->base
.crtc
= NULL
;
9465 static void intel_enable_pipe_a(struct drm_device
*dev
)
9467 struct intel_connector
*connector
;
9468 struct drm_connector
*crt
= NULL
;
9469 struct intel_load_detect_pipe load_detect_temp
;
9471 /* We can't just switch on the pipe A, we need to set things up with a
9472 * proper mode and output configuration. As a gross hack, enable pipe A
9473 * by enabling the load detect pipe once. */
9474 list_for_each_entry(connector
,
9475 &dev
->mode_config
.connector_list
,
9477 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
9478 crt
= &connector
->base
;
9486 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
))
9487 intel_release_load_detect_pipe(crt
, &load_detect_temp
);
9493 intel_check_plane_mapping(struct intel_crtc
*crtc
)
9495 struct drm_device
*dev
= crtc
->base
.dev
;
9496 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9499 if (INTEL_INFO(dev
)->num_pipes
== 1)
9502 reg
= DSPCNTR(!crtc
->plane
);
9503 val
= I915_READ(reg
);
9505 if ((val
& DISPLAY_PLANE_ENABLE
) &&
9506 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
9512 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
9514 struct drm_device
*dev
= crtc
->base
.dev
;
9515 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9518 /* Clear any frame start delays used for debugging left by the BIOS */
9519 reg
= PIPECONF(crtc
->config
.cpu_transcoder
);
9520 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
9522 /* We need to sanitize the plane -> pipe mapping first because this will
9523 * disable the crtc (and hence change the state) if it is wrong. Note
9524 * that gen4+ has a fixed plane -> pipe mapping. */
9525 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
9526 struct intel_connector
*connector
;
9529 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9530 crtc
->base
.base
.id
);
9532 /* Pipe has the wrong plane attached and the plane is active.
9533 * Temporarily change the plane mapping and disable everything
9535 plane
= crtc
->plane
;
9536 crtc
->plane
= !plane
;
9537 dev_priv
->display
.crtc_disable(&crtc
->base
);
9538 crtc
->plane
= plane
;
9540 /* ... and break all links. */
9541 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9543 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
9546 intel_connector_break_all_links(connector
);
9549 WARN_ON(crtc
->active
);
9550 crtc
->base
.enabled
= false;
9553 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
9554 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
9555 /* BIOS forgot to enable pipe A, this mostly happens after
9556 * resume. Force-enable the pipe to fix this, the update_dpms
9557 * call below we restore the pipe to the right state, but leave
9558 * the required bits on. */
9559 intel_enable_pipe_a(dev
);
9562 /* Adjust the state of the output pipe according to whether we
9563 * have active connectors/encoders. */
9564 intel_crtc_update_dpms(&crtc
->base
);
9566 if (crtc
->active
!= crtc
->base
.enabled
) {
9567 struct intel_encoder
*encoder
;
9569 /* This can happen either due to bugs in the get_hw_state
9570 * functions or because the pipe is force-enabled due to the
9572 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9574 crtc
->base
.enabled
? "enabled" : "disabled",
9575 crtc
->active
? "enabled" : "disabled");
9577 crtc
->base
.enabled
= crtc
->active
;
9579 /* Because we only establish the connector -> encoder ->
9580 * crtc links if something is active, this means the
9581 * crtc is now deactivated. Break the links. connector
9582 * -> encoder links are only establish when things are
9583 * actually up, hence no need to break them. */
9584 WARN_ON(crtc
->active
);
9586 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
9587 WARN_ON(encoder
->connectors_active
);
9588 encoder
->base
.crtc
= NULL
;
9593 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
9595 struct intel_connector
*connector
;
9596 struct drm_device
*dev
= encoder
->base
.dev
;
9598 /* We need to check both for a crtc link (meaning that the
9599 * encoder is active and trying to read from a pipe) and the
9600 * pipe itself being active. */
9601 bool has_active_crtc
= encoder
->base
.crtc
&&
9602 to_intel_crtc(encoder
->base
.crtc
)->active
;
9604 if (encoder
->connectors_active
&& !has_active_crtc
) {
9605 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9606 encoder
->base
.base
.id
,
9607 drm_get_encoder_name(&encoder
->base
));
9609 /* Connector is active, but has no active pipe. This is
9610 * fallout from our resume register restoring. Disable
9611 * the encoder manually again. */
9612 if (encoder
->base
.crtc
) {
9613 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9614 encoder
->base
.base
.id
,
9615 drm_get_encoder_name(&encoder
->base
));
9616 encoder
->disable(encoder
);
9619 /* Inconsistent output/port/pipe state happens presumably due to
9620 * a bug in one of the get_hw_state functions. Or someplace else
9621 * in our code, like the register restore mess on resume. Clamp
9622 * things to off as a safer default. */
9623 list_for_each_entry(connector
,
9624 &dev
->mode_config
.connector_list
,
9626 if (connector
->encoder
!= encoder
)
9629 intel_connector_break_all_links(connector
);
9632 /* Enabled encoders without active connectors will be fixed in
9633 * the crtc fixup. */
9636 void i915_redisable_vga(struct drm_device
*dev
)
9638 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9639 u32 vga_reg
= i915_vgacntrl_reg(dev
);
9641 if (I915_READ(vga_reg
) != VGA_DISP_DISABLE
) {
9642 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9643 i915_disable_vga(dev
);
9647 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9648 * and i915 state tracking structures. */
9649 void intel_modeset_setup_hw_state(struct drm_device
*dev
,
9652 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9654 struct drm_plane
*plane
;
9655 struct intel_crtc
*crtc
;
9656 struct intel_encoder
*encoder
;
9657 struct intel_connector
*connector
;
9659 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
9661 memset(&crtc
->config
, 0, sizeof(crtc
->config
));
9663 crtc
->active
= dev_priv
->display
.get_pipe_config(crtc
,
9666 crtc
->base
.enabled
= crtc
->active
;
9668 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9670 crtc
->active
? "enabled" : "disabled");
9674 intel_ddi_setup_hw_pll_state(dev
);
9676 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9680 if (encoder
->get_hw_state(encoder
, &pipe
)) {
9681 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
9682 encoder
->base
.crtc
= &crtc
->base
;
9683 if (encoder
->get_config
)
9684 encoder
->get_config(encoder
, &crtc
->config
);
9686 encoder
->base
.crtc
= NULL
;
9689 encoder
->connectors_active
= false;
9690 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9691 encoder
->base
.base
.id
,
9692 drm_get_encoder_name(&encoder
->base
),
9693 encoder
->base
.crtc
? "enabled" : "disabled",
9697 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9699 if (connector
->get_hw_state(connector
)) {
9700 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
9701 connector
->encoder
->connectors_active
= true;
9702 connector
->base
.encoder
= &connector
->encoder
->base
;
9704 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
9705 connector
->base
.encoder
= NULL
;
9707 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9708 connector
->base
.base
.id
,
9709 drm_get_connector_name(&connector
->base
),
9710 connector
->base
.encoder
? "enabled" : "disabled");
9713 /* HW state is read out, now we need to sanitize this mess. */
9714 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9716 intel_sanitize_encoder(encoder
);
9719 for_each_pipe(pipe
) {
9720 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
9721 intel_sanitize_crtc(crtc
);
9722 intel_dump_pipe_config(crtc
, &crtc
->config
, "[setup_hw_state]");
9725 if (force_restore
) {
9727 * We need to use raw interfaces for restoring state to avoid
9728 * checking (bogus) intermediate states.
9730 for_each_pipe(pipe
) {
9731 struct drm_crtc
*crtc
=
9732 dev_priv
->pipe_to_crtc_mapping
[pipe
];
9734 __intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
,
9737 list_for_each_entry(plane
, &dev
->mode_config
.plane_list
, head
)
9738 intel_plane_restore(plane
);
9740 i915_redisable_vga(dev
);
9742 intel_modeset_update_staged_output_state(dev
);
9745 intel_modeset_check_state(dev
);
9747 drm_mode_config_reset(dev
);
9750 void intel_modeset_gem_init(struct drm_device
*dev
)
9752 intel_modeset_init_hw(dev
);
9754 intel_setup_overlay(dev
);
9756 intel_modeset_setup_hw_state(dev
, false);
9759 void intel_modeset_cleanup(struct drm_device
*dev
)
9761 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9762 struct drm_crtc
*crtc
;
9763 struct intel_crtc
*intel_crtc
;
9766 * Interrupts and polling as the first thing to avoid creating havoc.
9767 * Too much stuff here (turning of rps, connectors, ...) would
9768 * experience fancy races otherwise.
9770 drm_irq_uninstall(dev
);
9771 cancel_work_sync(&dev_priv
->hotplug_work
);
9773 * Due to the hpd irq storm handling the hotplug work can re-arm the
9774 * poll handlers. Hence disable polling after hpd handling is shut down.
9776 drm_kms_helper_poll_fini(dev
);
9778 mutex_lock(&dev
->struct_mutex
);
9780 intel_unregister_dsm_handler();
9782 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
9783 /* Skip inactive CRTCs */
9787 intel_crtc
= to_intel_crtc(crtc
);
9788 intel_increase_pllclock(crtc
);
9791 intel_disable_fbc(dev
);
9793 intel_disable_gt_powersave(dev
);
9795 ironlake_teardown_rc6(dev
);
9797 mutex_unlock(&dev
->struct_mutex
);
9799 /* flush any delayed tasks or pending work */
9800 flush_scheduled_work();
9802 /* destroy backlight, if any, before the connectors */
9803 intel_panel_destroy_backlight(dev
);
9805 drm_mode_config_cleanup(dev
);
9807 intel_cleanup_overlay(dev
);
9811 * Return which encoder is currently attached for connector.
9813 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
9815 return &intel_attached_encoder(connector
)->base
;
9818 void intel_connector_attach_encoder(struct intel_connector
*connector
,
9819 struct intel_encoder
*encoder
)
9821 connector
->encoder
= encoder
;
9822 drm_mode_connector_attach_encoder(&connector
->base
,
9827 * set vga decode state - true == enable VGA decode
9829 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
9831 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9834 pci_read_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, &gmch_ctrl
);
9836 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
9838 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
9839 pci_write_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, gmch_ctrl
);
9843 #ifdef CONFIG_DEBUG_FS
9844 #include <linux/seq_file.h>
9846 struct intel_display_error_state
{
9848 u32 power_well_driver
;
9850 struct intel_cursor_error_state
{
9855 } cursor
[I915_MAX_PIPES
];
9857 struct intel_pipe_error_state
{
9858 enum transcoder cpu_transcoder
;
9868 } pipe
[I915_MAX_PIPES
];
9870 struct intel_plane_error_state
{
9878 } plane
[I915_MAX_PIPES
];
9881 struct intel_display_error_state
*
9882 intel_display_capture_error_state(struct drm_device
*dev
)
9884 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
9885 struct intel_display_error_state
*error
;
9886 enum transcoder cpu_transcoder
;
9889 error
= kmalloc(sizeof(*error
), GFP_ATOMIC
);
9893 if (HAS_POWER_WELL(dev
))
9894 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_DRIVER
);
9897 cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
, i
);
9898 error
->pipe
[i
].cpu_transcoder
= cpu_transcoder
;
9900 if (INTEL_INFO(dev
)->gen
<= 6 || IS_VALLEYVIEW(dev
)) {
9901 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
9902 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
9903 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
9905 error
->cursor
[i
].control
= I915_READ(CURCNTR_IVB(i
));
9906 error
->cursor
[i
].position
= I915_READ(CURPOS_IVB(i
));
9907 error
->cursor
[i
].base
= I915_READ(CURBASE_IVB(i
));
9910 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
9911 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
9912 if (INTEL_INFO(dev
)->gen
<= 3) {
9913 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
9914 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
9916 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
9917 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
9918 if (INTEL_INFO(dev
)->gen
>= 4) {
9919 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
9920 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
9923 error
->pipe
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
9924 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
9925 error
->pipe
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
9926 error
->pipe
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
9927 error
->pipe
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
9928 error
->pipe
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
9929 error
->pipe
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
9930 error
->pipe
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
9933 /* In the code above we read the registers without checking if the power
9934 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
9935 * prevent the next I915_WRITE from detecting it and printing an error
9937 if (HAS_POWER_WELL(dev
))
9938 I915_WRITE_NOTRACE(FPGA_DBG
, FPGA_DBG_RM_NOCLAIM
);
9943 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
9946 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
9947 struct drm_device
*dev
,
9948 struct intel_display_error_state
*error
)
9952 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
9953 if (HAS_POWER_WELL(dev
))
9954 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
9955 error
->power_well_driver
);
9957 err_printf(m
, "Pipe [%d]:\n", i
);
9958 err_printf(m
, " CPU transcoder: %c\n",
9959 transcoder_name(error
->pipe
[i
].cpu_transcoder
));
9960 err_printf(m
, " CONF: %08x\n", error
->pipe
[i
].conf
);
9961 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
9962 err_printf(m
, " HTOTAL: %08x\n", error
->pipe
[i
].htotal
);
9963 err_printf(m
, " HBLANK: %08x\n", error
->pipe
[i
].hblank
);
9964 err_printf(m
, " HSYNC: %08x\n", error
->pipe
[i
].hsync
);
9965 err_printf(m
, " VTOTAL: %08x\n", error
->pipe
[i
].vtotal
);
9966 err_printf(m
, " VBLANK: %08x\n", error
->pipe
[i
].vblank
);
9967 err_printf(m
, " VSYNC: %08x\n", error
->pipe
[i
].vsync
);
9969 err_printf(m
, "Plane [%d]:\n", i
);
9970 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
9971 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
9972 if (INTEL_INFO(dev
)->gen
<= 3) {
9973 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
9974 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
9976 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
9977 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
9978 if (INTEL_INFO(dev
)->gen
>= 4) {
9979 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
9980 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
9983 err_printf(m
, "Cursor [%d]:\n", i
);
9984 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
9985 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
9986 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);