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drm/i915: enable thermal reporting for IPS
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/vgaarb.h>
33 #include "drmP.h"
34 #include "intel_drv.h"
35 #include "i915_drm.h"
36 #include "i915_drv.h"
37 #include "i915_trace.h"
38 #include "drm_dp_helper.h"
39
40 #include "drm_crtc_helper.h"
41
42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
43
44 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
45 static void intel_update_watermarks(struct drm_device *dev);
46 static void intel_increase_pllclock(struct drm_crtc *crtc);
47 static void intel_crtc_update_cursor(struct drm_crtc *crtc);
48
49 typedef struct {
50 /* given values */
51 int n;
52 int m1, m2;
53 int p1, p2;
54 /* derived values */
55 int dot;
56 int vco;
57 int m;
58 int p;
59 } intel_clock_t;
60
61 typedef struct {
62 int min, max;
63 } intel_range_t;
64
65 typedef struct {
66 int dot_limit;
67 int p2_slow, p2_fast;
68 } intel_p2_t;
69
70 #define INTEL_P2_NUM 2
71 typedef struct intel_limit intel_limit_t;
72 struct intel_limit {
73 intel_range_t dot, vco, n, m, m1, m2, p, p1;
74 intel_p2_t p2;
75 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
76 int, int, intel_clock_t *);
77 };
78
79 #define I8XX_DOT_MIN 25000
80 #define I8XX_DOT_MAX 350000
81 #define I8XX_VCO_MIN 930000
82 #define I8XX_VCO_MAX 1400000
83 #define I8XX_N_MIN 3
84 #define I8XX_N_MAX 16
85 #define I8XX_M_MIN 96
86 #define I8XX_M_MAX 140
87 #define I8XX_M1_MIN 18
88 #define I8XX_M1_MAX 26
89 #define I8XX_M2_MIN 6
90 #define I8XX_M2_MAX 16
91 #define I8XX_P_MIN 4
92 #define I8XX_P_MAX 128
93 #define I8XX_P1_MIN 2
94 #define I8XX_P1_MAX 33
95 #define I8XX_P1_LVDS_MIN 1
96 #define I8XX_P1_LVDS_MAX 6
97 #define I8XX_P2_SLOW 4
98 #define I8XX_P2_FAST 2
99 #define I8XX_P2_LVDS_SLOW 14
100 #define I8XX_P2_LVDS_FAST 7
101 #define I8XX_P2_SLOW_LIMIT 165000
102
103 #define I9XX_DOT_MIN 20000
104 #define I9XX_DOT_MAX 400000
105 #define I9XX_VCO_MIN 1400000
106 #define I9XX_VCO_MAX 2800000
107 #define PINEVIEW_VCO_MIN 1700000
108 #define PINEVIEW_VCO_MAX 3500000
109 #define I9XX_N_MIN 1
110 #define I9XX_N_MAX 6
111 /* Pineview's Ncounter is a ring counter */
112 #define PINEVIEW_N_MIN 3
113 #define PINEVIEW_N_MAX 6
114 #define I9XX_M_MIN 70
115 #define I9XX_M_MAX 120
116 #define PINEVIEW_M_MIN 2
117 #define PINEVIEW_M_MAX 256
118 #define I9XX_M1_MIN 10
119 #define I9XX_M1_MAX 22
120 #define I9XX_M2_MIN 5
121 #define I9XX_M2_MAX 9
122 /* Pineview M1 is reserved, and must be 0 */
123 #define PINEVIEW_M1_MIN 0
124 #define PINEVIEW_M1_MAX 0
125 #define PINEVIEW_M2_MIN 0
126 #define PINEVIEW_M2_MAX 254
127 #define I9XX_P_SDVO_DAC_MIN 5
128 #define I9XX_P_SDVO_DAC_MAX 80
129 #define I9XX_P_LVDS_MIN 7
130 #define I9XX_P_LVDS_MAX 98
131 #define PINEVIEW_P_LVDS_MIN 7
132 #define PINEVIEW_P_LVDS_MAX 112
133 #define I9XX_P1_MIN 1
134 #define I9XX_P1_MAX 8
135 #define I9XX_P2_SDVO_DAC_SLOW 10
136 #define I9XX_P2_SDVO_DAC_FAST 5
137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
138 #define I9XX_P2_LVDS_SLOW 14
139 #define I9XX_P2_LVDS_FAST 7
140 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
141
142 /*The parameter is for SDVO on G4x platform*/
143 #define G4X_DOT_SDVO_MIN 25000
144 #define G4X_DOT_SDVO_MAX 270000
145 #define G4X_VCO_MIN 1750000
146 #define G4X_VCO_MAX 3500000
147 #define G4X_N_SDVO_MIN 1
148 #define G4X_N_SDVO_MAX 4
149 #define G4X_M_SDVO_MIN 104
150 #define G4X_M_SDVO_MAX 138
151 #define G4X_M1_SDVO_MIN 17
152 #define G4X_M1_SDVO_MAX 23
153 #define G4X_M2_SDVO_MIN 5
154 #define G4X_M2_SDVO_MAX 11
155 #define G4X_P_SDVO_MIN 10
156 #define G4X_P_SDVO_MAX 30
157 #define G4X_P1_SDVO_MIN 1
158 #define G4X_P1_SDVO_MAX 3
159 #define G4X_P2_SDVO_SLOW 10
160 #define G4X_P2_SDVO_FAST 10
161 #define G4X_P2_SDVO_LIMIT 270000
162
163 /*The parameter is for HDMI_DAC on G4x platform*/
164 #define G4X_DOT_HDMI_DAC_MIN 22000
165 #define G4X_DOT_HDMI_DAC_MAX 400000
166 #define G4X_N_HDMI_DAC_MIN 1
167 #define G4X_N_HDMI_DAC_MAX 4
168 #define G4X_M_HDMI_DAC_MIN 104
169 #define G4X_M_HDMI_DAC_MAX 138
170 #define G4X_M1_HDMI_DAC_MIN 16
171 #define G4X_M1_HDMI_DAC_MAX 23
172 #define G4X_M2_HDMI_DAC_MIN 5
173 #define G4X_M2_HDMI_DAC_MAX 11
174 #define G4X_P_HDMI_DAC_MIN 5
175 #define G4X_P_HDMI_DAC_MAX 80
176 #define G4X_P1_HDMI_DAC_MIN 1
177 #define G4X_P1_HDMI_DAC_MAX 8
178 #define G4X_P2_HDMI_DAC_SLOW 10
179 #define G4X_P2_HDMI_DAC_FAST 5
180 #define G4X_P2_HDMI_DAC_LIMIT 165000
181
182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
200
201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
219
220 /*The parameter is for DISPLAY PORT on G4x platform*/
221 #define G4X_DOT_DISPLAY_PORT_MIN 161670
222 #define G4X_DOT_DISPLAY_PORT_MAX 227000
223 #define G4X_N_DISPLAY_PORT_MIN 1
224 #define G4X_N_DISPLAY_PORT_MAX 2
225 #define G4X_M_DISPLAY_PORT_MIN 97
226 #define G4X_M_DISPLAY_PORT_MAX 108
227 #define G4X_M1_DISPLAY_PORT_MIN 0x10
228 #define G4X_M1_DISPLAY_PORT_MAX 0x12
229 #define G4X_M2_DISPLAY_PORT_MIN 0x05
230 #define G4X_M2_DISPLAY_PORT_MAX 0x06
231 #define G4X_P_DISPLAY_PORT_MIN 10
232 #define G4X_P_DISPLAY_PORT_MAX 20
233 #define G4X_P1_DISPLAY_PORT_MIN 1
234 #define G4X_P1_DISPLAY_PORT_MAX 2
235 #define G4X_P2_DISPLAY_PORT_SLOW 10
236 #define G4X_P2_DISPLAY_PORT_FAST 10
237 #define G4X_P2_DISPLAY_PORT_LIMIT 0
238
239 /* Ironlake / Sandybridge */
240 /* as we calculate clock using (register_value + 2) for
241 N/M1/M2, so here the range value for them is (actual_value-2).
242 */
243 #define IRONLAKE_DOT_MIN 25000
244 #define IRONLAKE_DOT_MAX 350000
245 #define IRONLAKE_VCO_MIN 1760000
246 #define IRONLAKE_VCO_MAX 3510000
247 #define IRONLAKE_M1_MIN 12
248 #define IRONLAKE_M1_MAX 22
249 #define IRONLAKE_M2_MIN 5
250 #define IRONLAKE_M2_MAX 9
251 #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
252
253 /* We have parameter ranges for different type of outputs. */
254
255 /* DAC & HDMI Refclk 120Mhz */
256 #define IRONLAKE_DAC_N_MIN 1
257 #define IRONLAKE_DAC_N_MAX 5
258 #define IRONLAKE_DAC_M_MIN 79
259 #define IRONLAKE_DAC_M_MAX 127
260 #define IRONLAKE_DAC_P_MIN 5
261 #define IRONLAKE_DAC_P_MAX 80
262 #define IRONLAKE_DAC_P1_MIN 1
263 #define IRONLAKE_DAC_P1_MAX 8
264 #define IRONLAKE_DAC_P2_SLOW 10
265 #define IRONLAKE_DAC_P2_FAST 5
266
267 /* LVDS single-channel 120Mhz refclk */
268 #define IRONLAKE_LVDS_S_N_MIN 1
269 #define IRONLAKE_LVDS_S_N_MAX 3
270 #define IRONLAKE_LVDS_S_M_MIN 79
271 #define IRONLAKE_LVDS_S_M_MAX 118
272 #define IRONLAKE_LVDS_S_P_MIN 28
273 #define IRONLAKE_LVDS_S_P_MAX 112
274 #define IRONLAKE_LVDS_S_P1_MIN 2
275 #define IRONLAKE_LVDS_S_P1_MAX 8
276 #define IRONLAKE_LVDS_S_P2_SLOW 14
277 #define IRONLAKE_LVDS_S_P2_FAST 14
278
279 /* LVDS dual-channel 120Mhz refclk */
280 #define IRONLAKE_LVDS_D_N_MIN 1
281 #define IRONLAKE_LVDS_D_N_MAX 3
282 #define IRONLAKE_LVDS_D_M_MIN 79
283 #define IRONLAKE_LVDS_D_M_MAX 127
284 #define IRONLAKE_LVDS_D_P_MIN 14
285 #define IRONLAKE_LVDS_D_P_MAX 56
286 #define IRONLAKE_LVDS_D_P1_MIN 2
287 #define IRONLAKE_LVDS_D_P1_MAX 8
288 #define IRONLAKE_LVDS_D_P2_SLOW 7
289 #define IRONLAKE_LVDS_D_P2_FAST 7
290
291 /* LVDS single-channel 100Mhz refclk */
292 #define IRONLAKE_LVDS_S_SSC_N_MIN 1
293 #define IRONLAKE_LVDS_S_SSC_N_MAX 2
294 #define IRONLAKE_LVDS_S_SSC_M_MIN 79
295 #define IRONLAKE_LVDS_S_SSC_M_MAX 126
296 #define IRONLAKE_LVDS_S_SSC_P_MIN 28
297 #define IRONLAKE_LVDS_S_SSC_P_MAX 112
298 #define IRONLAKE_LVDS_S_SSC_P1_MIN 2
299 #define IRONLAKE_LVDS_S_SSC_P1_MAX 8
300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
301 #define IRONLAKE_LVDS_S_SSC_P2_FAST 14
302
303 /* LVDS dual-channel 100Mhz refclk */
304 #define IRONLAKE_LVDS_D_SSC_N_MIN 1
305 #define IRONLAKE_LVDS_D_SSC_N_MAX 3
306 #define IRONLAKE_LVDS_D_SSC_M_MIN 79
307 #define IRONLAKE_LVDS_D_SSC_M_MAX 126
308 #define IRONLAKE_LVDS_D_SSC_P_MIN 14
309 #define IRONLAKE_LVDS_D_SSC_P_MAX 42
310 #define IRONLAKE_LVDS_D_SSC_P1_MIN 2
311 #define IRONLAKE_LVDS_D_SSC_P1_MAX 6
312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
313 #define IRONLAKE_LVDS_D_SSC_P2_FAST 7
314
315 /* DisplayPort */
316 #define IRONLAKE_DP_N_MIN 1
317 #define IRONLAKE_DP_N_MAX 2
318 #define IRONLAKE_DP_M_MIN 81
319 #define IRONLAKE_DP_M_MAX 90
320 #define IRONLAKE_DP_P_MIN 10
321 #define IRONLAKE_DP_P_MAX 20
322 #define IRONLAKE_DP_P2_FAST 10
323 #define IRONLAKE_DP_P2_SLOW 10
324 #define IRONLAKE_DP_P2_LIMIT 0
325 #define IRONLAKE_DP_P1_MIN 1
326 #define IRONLAKE_DP_P1_MAX 2
327
328 /* FDI */
329 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
330
331 static bool
332 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
333 int target, int refclk, intel_clock_t *best_clock);
334 static bool
335 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
336 int target, int refclk, intel_clock_t *best_clock);
337
338 static bool
339 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
340 int target, int refclk, intel_clock_t *best_clock);
341 static bool
342 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
343 int target, int refclk, intel_clock_t *best_clock);
344
345 static inline u32 /* units of 100MHz */
346 intel_fdi_link_freq(struct drm_device *dev)
347 {
348 struct drm_i915_private *dev_priv = dev->dev_private;
349 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
350 }
351
352 static const intel_limit_t intel_limits_i8xx_dvo = {
353 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
354 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
355 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
356 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
357 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
358 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
359 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
360 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
361 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
362 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
363 .find_pll = intel_find_best_PLL,
364 };
365
366 static const intel_limit_t intel_limits_i8xx_lvds = {
367 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
368 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
369 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
370 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
371 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
372 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
373 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
374 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
375 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
376 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
377 .find_pll = intel_find_best_PLL,
378 };
379
380 static const intel_limit_t intel_limits_i9xx_sdvo = {
381 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
382 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
383 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
384 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
385 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
386 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
387 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
388 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
389 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
390 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
391 .find_pll = intel_find_best_PLL,
392 };
393
394 static const intel_limit_t intel_limits_i9xx_lvds = {
395 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
396 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
397 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
398 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
399 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
400 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
401 .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
402 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
403 /* The single-channel range is 25-112Mhz, and dual-channel
404 * is 80-224Mhz. Prefer single channel as much as possible.
405 */
406 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
407 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
408 .find_pll = intel_find_best_PLL,
409 };
410
411 /* below parameter and function is for G4X Chipset Family*/
412 static const intel_limit_t intel_limits_g4x_sdvo = {
413 .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
414 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
415 .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
416 .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
417 .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
418 .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
419 .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
420 .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
421 .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
422 .p2_slow = G4X_P2_SDVO_SLOW,
423 .p2_fast = G4X_P2_SDVO_FAST
424 },
425 .find_pll = intel_g4x_find_best_PLL,
426 };
427
428 static const intel_limit_t intel_limits_g4x_hdmi = {
429 .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
430 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
431 .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
432 .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
433 .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
434 .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
435 .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
436 .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
437 .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
438 .p2_slow = G4X_P2_HDMI_DAC_SLOW,
439 .p2_fast = G4X_P2_HDMI_DAC_FAST
440 },
441 .find_pll = intel_g4x_find_best_PLL,
442 };
443
444 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
445 .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
446 .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
447 .vco = { .min = G4X_VCO_MIN,
448 .max = G4X_VCO_MAX },
449 .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
450 .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
451 .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
452 .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
453 .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
454 .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
455 .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
456 .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
457 .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
458 .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
459 .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
460 .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
461 .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
462 .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
463 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
464 },
465 .find_pll = intel_g4x_find_best_PLL,
466 };
467
468 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
469 .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
470 .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
471 .vco = { .min = G4X_VCO_MIN,
472 .max = G4X_VCO_MAX },
473 .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
474 .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
475 .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
476 .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
477 .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
478 .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
479 .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
480 .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
481 .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
482 .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
483 .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
484 .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
485 .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
486 .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
487 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
488 },
489 .find_pll = intel_g4x_find_best_PLL,
490 };
491
492 static const intel_limit_t intel_limits_g4x_display_port = {
493 .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
494 .max = G4X_DOT_DISPLAY_PORT_MAX },
495 .vco = { .min = G4X_VCO_MIN,
496 .max = G4X_VCO_MAX},
497 .n = { .min = G4X_N_DISPLAY_PORT_MIN,
498 .max = G4X_N_DISPLAY_PORT_MAX },
499 .m = { .min = G4X_M_DISPLAY_PORT_MIN,
500 .max = G4X_M_DISPLAY_PORT_MAX },
501 .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
502 .max = G4X_M1_DISPLAY_PORT_MAX },
503 .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
504 .max = G4X_M2_DISPLAY_PORT_MAX },
505 .p = { .min = G4X_P_DISPLAY_PORT_MIN,
506 .max = G4X_P_DISPLAY_PORT_MAX },
507 .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
508 .max = G4X_P1_DISPLAY_PORT_MAX},
509 .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
510 .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
511 .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
512 .find_pll = intel_find_pll_g4x_dp,
513 };
514
515 static const intel_limit_t intel_limits_pineview_sdvo = {
516 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
517 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
518 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
519 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
520 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
521 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
522 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
523 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
524 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
525 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
526 .find_pll = intel_find_best_PLL,
527 };
528
529 static const intel_limit_t intel_limits_pineview_lvds = {
530 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
531 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
532 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
533 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
534 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
535 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
536 .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX },
537 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
538 /* Pineview only supports single-channel mode. */
539 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
540 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
541 .find_pll = intel_find_best_PLL,
542 };
543
544 static const intel_limit_t intel_limits_ironlake_dac = {
545 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
546 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
547 .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX },
548 .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX },
549 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
550 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
551 .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX },
552 .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX },
553 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
554 .p2_slow = IRONLAKE_DAC_P2_SLOW,
555 .p2_fast = IRONLAKE_DAC_P2_FAST },
556 .find_pll = intel_g4x_find_best_PLL,
557 };
558
559 static const intel_limit_t intel_limits_ironlake_single_lvds = {
560 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
561 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
562 .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX },
563 .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX },
564 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
565 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
566 .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX },
567 .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX },
568 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
569 .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
570 .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
571 .find_pll = intel_g4x_find_best_PLL,
572 };
573
574 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
575 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
576 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
577 .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX },
578 .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX },
579 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
580 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
581 .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX },
582 .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX },
583 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
584 .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
585 .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
586 .find_pll = intel_g4x_find_best_PLL,
587 };
588
589 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
590 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
591 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
592 .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
593 .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
594 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
595 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
596 .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
597 .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
598 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
599 .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
600 .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
601 .find_pll = intel_g4x_find_best_PLL,
602 };
603
604 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
605 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
606 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
607 .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
608 .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
609 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
610 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
611 .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
612 .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
613 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
614 .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
615 .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
616 .find_pll = intel_g4x_find_best_PLL,
617 };
618
619 static const intel_limit_t intel_limits_ironlake_display_port = {
620 .dot = { .min = IRONLAKE_DOT_MIN,
621 .max = IRONLAKE_DOT_MAX },
622 .vco = { .min = IRONLAKE_VCO_MIN,
623 .max = IRONLAKE_VCO_MAX},
624 .n = { .min = IRONLAKE_DP_N_MIN,
625 .max = IRONLAKE_DP_N_MAX },
626 .m = { .min = IRONLAKE_DP_M_MIN,
627 .max = IRONLAKE_DP_M_MAX },
628 .m1 = { .min = IRONLAKE_M1_MIN,
629 .max = IRONLAKE_M1_MAX },
630 .m2 = { .min = IRONLAKE_M2_MIN,
631 .max = IRONLAKE_M2_MAX },
632 .p = { .min = IRONLAKE_DP_P_MIN,
633 .max = IRONLAKE_DP_P_MAX },
634 .p1 = { .min = IRONLAKE_DP_P1_MIN,
635 .max = IRONLAKE_DP_P1_MAX},
636 .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
637 .p2_slow = IRONLAKE_DP_P2_SLOW,
638 .p2_fast = IRONLAKE_DP_P2_FAST },
639 .find_pll = intel_find_pll_ironlake_dp,
640 };
641
642 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
643 {
644 struct drm_device *dev = crtc->dev;
645 struct drm_i915_private *dev_priv = dev->dev_private;
646 const intel_limit_t *limit;
647 int refclk = 120;
648
649 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
650 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
651 refclk = 100;
652
653 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
654 LVDS_CLKB_POWER_UP) {
655 /* LVDS dual channel */
656 if (refclk == 100)
657 limit = &intel_limits_ironlake_dual_lvds_100m;
658 else
659 limit = &intel_limits_ironlake_dual_lvds;
660 } else {
661 if (refclk == 100)
662 limit = &intel_limits_ironlake_single_lvds_100m;
663 else
664 limit = &intel_limits_ironlake_single_lvds;
665 }
666 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
667 HAS_eDP)
668 limit = &intel_limits_ironlake_display_port;
669 else
670 limit = &intel_limits_ironlake_dac;
671
672 return limit;
673 }
674
675 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
676 {
677 struct drm_device *dev = crtc->dev;
678 struct drm_i915_private *dev_priv = dev->dev_private;
679 const intel_limit_t *limit;
680
681 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
682 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
683 LVDS_CLKB_POWER_UP)
684 /* LVDS with dual channel */
685 limit = &intel_limits_g4x_dual_channel_lvds;
686 else
687 /* LVDS with dual channel */
688 limit = &intel_limits_g4x_single_channel_lvds;
689 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
690 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
691 limit = &intel_limits_g4x_hdmi;
692 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
693 limit = &intel_limits_g4x_sdvo;
694 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
695 limit = &intel_limits_g4x_display_port;
696 } else /* The option is for other outputs */
697 limit = &intel_limits_i9xx_sdvo;
698
699 return limit;
700 }
701
702 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
703 {
704 struct drm_device *dev = crtc->dev;
705 const intel_limit_t *limit;
706
707 if (HAS_PCH_SPLIT(dev))
708 limit = intel_ironlake_limit(crtc);
709 else if (IS_G4X(dev)) {
710 limit = intel_g4x_limit(crtc);
711 } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
712 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
713 limit = &intel_limits_i9xx_lvds;
714 else
715 limit = &intel_limits_i9xx_sdvo;
716 } else if (IS_PINEVIEW(dev)) {
717 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
718 limit = &intel_limits_pineview_lvds;
719 else
720 limit = &intel_limits_pineview_sdvo;
721 } else {
722 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
723 limit = &intel_limits_i8xx_lvds;
724 else
725 limit = &intel_limits_i8xx_dvo;
726 }
727 return limit;
728 }
729
730 /* m1 is reserved as 0 in Pineview, n is a ring counter */
731 static void pineview_clock(int refclk, intel_clock_t *clock)
732 {
733 clock->m = clock->m2 + 2;
734 clock->p = clock->p1 * clock->p2;
735 clock->vco = refclk * clock->m / clock->n;
736 clock->dot = clock->vco / clock->p;
737 }
738
739 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
740 {
741 if (IS_PINEVIEW(dev)) {
742 pineview_clock(refclk, clock);
743 return;
744 }
745 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
746 clock->p = clock->p1 * clock->p2;
747 clock->vco = refclk * clock->m / (clock->n + 2);
748 clock->dot = clock->vco / clock->p;
749 }
750
751 /**
752 * Returns whether any output on the specified pipe is of the specified type
753 */
754 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
755 {
756 struct drm_device *dev = crtc->dev;
757 struct drm_mode_config *mode_config = &dev->mode_config;
758 struct intel_encoder *encoder;
759
760 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
761 if (encoder->base.crtc == crtc && encoder->type == type)
762 return true;
763
764 return false;
765 }
766
767 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
768 /**
769 * Returns whether the given set of divisors are valid for a given refclk with
770 * the given connectors.
771 */
772
773 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
774 {
775 const intel_limit_t *limit = intel_limit (crtc);
776 struct drm_device *dev = crtc->dev;
777
778 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
779 INTELPllInvalid ("p1 out of range\n");
780 if (clock->p < limit->p.min || limit->p.max < clock->p)
781 INTELPllInvalid ("p out of range\n");
782 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
783 INTELPllInvalid ("m2 out of range\n");
784 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
785 INTELPllInvalid ("m1 out of range\n");
786 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
787 INTELPllInvalid ("m1 <= m2\n");
788 if (clock->m < limit->m.min || limit->m.max < clock->m)
789 INTELPllInvalid ("m out of range\n");
790 if (clock->n < limit->n.min || limit->n.max < clock->n)
791 INTELPllInvalid ("n out of range\n");
792 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
793 INTELPllInvalid ("vco out of range\n");
794 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
795 * connector, etc., rather than just a single range.
796 */
797 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
798 INTELPllInvalid ("dot out of range\n");
799
800 return true;
801 }
802
803 static bool
804 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
805 int target, int refclk, intel_clock_t *best_clock)
806
807 {
808 struct drm_device *dev = crtc->dev;
809 struct drm_i915_private *dev_priv = dev->dev_private;
810 intel_clock_t clock;
811 int err = target;
812
813 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
814 (I915_READ(LVDS)) != 0) {
815 /*
816 * For LVDS, if the panel is on, just rely on its current
817 * settings for dual-channel. We haven't figured out how to
818 * reliably set up different single/dual channel state, if we
819 * even can.
820 */
821 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
822 LVDS_CLKB_POWER_UP)
823 clock.p2 = limit->p2.p2_fast;
824 else
825 clock.p2 = limit->p2.p2_slow;
826 } else {
827 if (target < limit->p2.dot_limit)
828 clock.p2 = limit->p2.p2_slow;
829 else
830 clock.p2 = limit->p2.p2_fast;
831 }
832
833 memset (best_clock, 0, sizeof (*best_clock));
834
835 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
836 clock.m1++) {
837 for (clock.m2 = limit->m2.min;
838 clock.m2 <= limit->m2.max; clock.m2++) {
839 /* m1 is always 0 in Pineview */
840 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
841 break;
842 for (clock.n = limit->n.min;
843 clock.n <= limit->n.max; clock.n++) {
844 for (clock.p1 = limit->p1.min;
845 clock.p1 <= limit->p1.max; clock.p1++) {
846 int this_err;
847
848 intel_clock(dev, refclk, &clock);
849
850 if (!intel_PLL_is_valid(crtc, &clock))
851 continue;
852
853 this_err = abs(clock.dot - target);
854 if (this_err < err) {
855 *best_clock = clock;
856 err = this_err;
857 }
858 }
859 }
860 }
861 }
862
863 return (err != target);
864 }
865
866 static bool
867 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
868 int target, int refclk, intel_clock_t *best_clock)
869 {
870 struct drm_device *dev = crtc->dev;
871 struct drm_i915_private *dev_priv = dev->dev_private;
872 intel_clock_t clock;
873 int max_n;
874 bool found;
875 /* approximately equals target * 0.00585 */
876 int err_most = (target >> 8) + (target >> 9);
877 found = false;
878
879 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
880 int lvds_reg;
881
882 if (HAS_PCH_SPLIT(dev))
883 lvds_reg = PCH_LVDS;
884 else
885 lvds_reg = LVDS;
886 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
887 LVDS_CLKB_POWER_UP)
888 clock.p2 = limit->p2.p2_fast;
889 else
890 clock.p2 = limit->p2.p2_slow;
891 } else {
892 if (target < limit->p2.dot_limit)
893 clock.p2 = limit->p2.p2_slow;
894 else
895 clock.p2 = limit->p2.p2_fast;
896 }
897
898 memset(best_clock, 0, sizeof(*best_clock));
899 max_n = limit->n.max;
900 /* based on hardware requirement, prefer smaller n to precision */
901 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
902 /* based on hardware requirement, prefere larger m1,m2 */
903 for (clock.m1 = limit->m1.max;
904 clock.m1 >= limit->m1.min; clock.m1--) {
905 for (clock.m2 = limit->m2.max;
906 clock.m2 >= limit->m2.min; clock.m2--) {
907 for (clock.p1 = limit->p1.max;
908 clock.p1 >= limit->p1.min; clock.p1--) {
909 int this_err;
910
911 intel_clock(dev, refclk, &clock);
912 if (!intel_PLL_is_valid(crtc, &clock))
913 continue;
914 this_err = abs(clock.dot - target) ;
915 if (this_err < err_most) {
916 *best_clock = clock;
917 err_most = this_err;
918 max_n = clock.n;
919 found = true;
920 }
921 }
922 }
923 }
924 }
925 return found;
926 }
927
928 static bool
929 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
930 int target, int refclk, intel_clock_t *best_clock)
931 {
932 struct drm_device *dev = crtc->dev;
933 intel_clock_t clock;
934
935 /* return directly when it is eDP */
936 if (HAS_eDP)
937 return true;
938
939 if (target < 200000) {
940 clock.n = 1;
941 clock.p1 = 2;
942 clock.p2 = 10;
943 clock.m1 = 12;
944 clock.m2 = 9;
945 } else {
946 clock.n = 2;
947 clock.p1 = 1;
948 clock.p2 = 10;
949 clock.m1 = 14;
950 clock.m2 = 8;
951 }
952 intel_clock(dev, refclk, &clock);
953 memcpy(best_clock, &clock, sizeof(intel_clock_t));
954 return true;
955 }
956
957 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
958 static bool
959 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
960 int target, int refclk, intel_clock_t *best_clock)
961 {
962 intel_clock_t clock;
963 if (target < 200000) {
964 clock.p1 = 2;
965 clock.p2 = 10;
966 clock.n = 2;
967 clock.m1 = 23;
968 clock.m2 = 8;
969 } else {
970 clock.p1 = 1;
971 clock.p2 = 10;
972 clock.n = 1;
973 clock.m1 = 14;
974 clock.m2 = 2;
975 }
976 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
977 clock.p = (clock.p1 * clock.p2);
978 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
979 clock.vco = 0;
980 memcpy(best_clock, &clock, sizeof(intel_clock_t));
981 return true;
982 }
983
984 /**
985 * intel_wait_for_vblank - wait for vblank on a given pipe
986 * @dev: drm device
987 * @pipe: pipe to wait for
988 *
989 * Wait for vblank to occur on a given pipe. Needed for various bits of
990 * mode setting code.
991 */
992 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
993 {
994 struct drm_i915_private *dev_priv = dev->dev_private;
995 int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);
996
997 /* Clear existing vblank status. Note this will clear any other
998 * sticky status fields as well.
999 *
1000 * This races with i915_driver_irq_handler() with the result
1001 * that either function could miss a vblank event. Here it is not
1002 * fatal, as we will either wait upon the next vblank interrupt or
1003 * timeout. Generally speaking intel_wait_for_vblank() is only
1004 * called during modeset at which time the GPU should be idle and
1005 * should *not* be performing page flips and thus not waiting on
1006 * vblanks...
1007 * Currently, the result of us stealing a vblank from the irq
1008 * handler is that a single frame will be skipped during swapbuffers.
1009 */
1010 I915_WRITE(pipestat_reg,
1011 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
1012
1013 /* Wait for vblank interrupt bit to set */
1014 if (wait_for(I915_READ(pipestat_reg) &
1015 PIPE_VBLANK_INTERRUPT_STATUS,
1016 50))
1017 DRM_DEBUG_KMS("vblank wait timed out\n");
1018 }
1019
1020 /**
1021 * intel_wait_for_vblank_off - wait for vblank after disabling a pipe
1022 * @dev: drm device
1023 * @pipe: pipe to wait for
1024 *
1025 * After disabling a pipe, we can't wait for vblank in the usual way,
1026 * spinning on the vblank interrupt status bit, since we won't actually
1027 * see an interrupt when the pipe is disabled.
1028 *
1029 * So this function waits for the display line value to settle (it
1030 * usually ends up stopping at the start of the next frame).
1031 */
1032 void intel_wait_for_vblank_off(struct drm_device *dev, int pipe)
1033 {
1034 struct drm_i915_private *dev_priv = dev->dev_private;
1035 int pipedsl_reg = (pipe == 0 ? PIPEADSL : PIPEBDSL);
1036 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1037 u32 last_line;
1038
1039 /* Wait for the display line to settle */
1040 do {
1041 last_line = I915_READ(pipedsl_reg) & DSL_LINEMASK;
1042 mdelay(5);
1043 } while (((I915_READ(pipedsl_reg) & DSL_LINEMASK) != last_line) &&
1044 time_after(timeout, jiffies));
1045
1046 if (time_after(jiffies, timeout))
1047 DRM_DEBUG_KMS("vblank wait timed out\n");
1048 }
1049
1050 /* Parameters have changed, update FBC info */
1051 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1052 {
1053 struct drm_device *dev = crtc->dev;
1054 struct drm_i915_private *dev_priv = dev->dev_private;
1055 struct drm_framebuffer *fb = crtc->fb;
1056 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1057 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1058 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1059 int plane, i;
1060 u32 fbc_ctl, fbc_ctl2;
1061
1062 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1063
1064 if (fb->pitch < dev_priv->cfb_pitch)
1065 dev_priv->cfb_pitch = fb->pitch;
1066
1067 /* FBC_CTL wants 64B units */
1068 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1069 dev_priv->cfb_fence = obj_priv->fence_reg;
1070 dev_priv->cfb_plane = intel_crtc->plane;
1071 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1072
1073 /* Clear old tags */
1074 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1075 I915_WRITE(FBC_TAG + (i * 4), 0);
1076
1077 /* Set it up... */
1078 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1079 if (obj_priv->tiling_mode != I915_TILING_NONE)
1080 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1081 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1082 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1083
1084 /* enable it... */
1085 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1086 if (IS_I945GM(dev))
1087 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1088 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1089 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1090 if (obj_priv->tiling_mode != I915_TILING_NONE)
1091 fbc_ctl |= dev_priv->cfb_fence;
1092 I915_WRITE(FBC_CONTROL, fbc_ctl);
1093
1094 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1095 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1096 }
1097
1098 void i8xx_disable_fbc(struct drm_device *dev)
1099 {
1100 struct drm_i915_private *dev_priv = dev->dev_private;
1101 u32 fbc_ctl;
1102
1103 if (!I915_HAS_FBC(dev))
1104 return;
1105
1106 if (!(I915_READ(FBC_CONTROL) & FBC_CTL_EN))
1107 return; /* Already off, just return */
1108
1109 /* Disable compression */
1110 fbc_ctl = I915_READ(FBC_CONTROL);
1111 fbc_ctl &= ~FBC_CTL_EN;
1112 I915_WRITE(FBC_CONTROL, fbc_ctl);
1113
1114 /* Wait for compressing bit to clear */
1115 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1116 DRM_DEBUG_KMS("FBC idle timed out\n");
1117 return;
1118 }
1119
1120 DRM_DEBUG_KMS("disabled FBC\n");
1121 }
1122
1123 static bool i8xx_fbc_enabled(struct drm_device *dev)
1124 {
1125 struct drm_i915_private *dev_priv = dev->dev_private;
1126
1127 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1128 }
1129
1130 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1131 {
1132 struct drm_device *dev = crtc->dev;
1133 struct drm_i915_private *dev_priv = dev->dev_private;
1134 struct drm_framebuffer *fb = crtc->fb;
1135 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1136 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1137 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1138 int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1139 DPFC_CTL_PLANEB);
1140 unsigned long stall_watermark = 200;
1141 u32 dpfc_ctl;
1142
1143 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1144 dev_priv->cfb_fence = obj_priv->fence_reg;
1145 dev_priv->cfb_plane = intel_crtc->plane;
1146
1147 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1148 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1149 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1150 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1151 } else {
1152 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1153 }
1154
1155 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1156 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1157 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1158 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1159 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1160
1161 /* enable it... */
1162 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1163
1164 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1165 }
1166
1167 void g4x_disable_fbc(struct drm_device *dev)
1168 {
1169 struct drm_i915_private *dev_priv = dev->dev_private;
1170 u32 dpfc_ctl;
1171
1172 /* Disable compression */
1173 dpfc_ctl = I915_READ(DPFC_CONTROL);
1174 dpfc_ctl &= ~DPFC_CTL_EN;
1175 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1176
1177 DRM_DEBUG_KMS("disabled FBC\n");
1178 }
1179
1180 static bool g4x_fbc_enabled(struct drm_device *dev)
1181 {
1182 struct drm_i915_private *dev_priv = dev->dev_private;
1183
1184 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1185 }
1186
1187 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1188 {
1189 struct drm_device *dev = crtc->dev;
1190 struct drm_i915_private *dev_priv = dev->dev_private;
1191 struct drm_framebuffer *fb = crtc->fb;
1192 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1193 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1194 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1195 int plane = (intel_crtc->plane == 0) ? DPFC_CTL_PLANEA :
1196 DPFC_CTL_PLANEB;
1197 unsigned long stall_watermark = 200;
1198 u32 dpfc_ctl;
1199
1200 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1201 dev_priv->cfb_fence = obj_priv->fence_reg;
1202 dev_priv->cfb_plane = intel_crtc->plane;
1203
1204 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1205 dpfc_ctl &= DPFC_RESERVED;
1206 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1207 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1208 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1209 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1210 } else {
1211 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1212 }
1213
1214 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1215 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1216 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1217 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1218 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1219 I915_WRITE(ILK_FBC_RT_BASE, obj_priv->gtt_offset | ILK_FBC_RT_VALID);
1220 /* enable it... */
1221 I915_WRITE(ILK_DPFC_CONTROL, I915_READ(ILK_DPFC_CONTROL) |
1222 DPFC_CTL_EN);
1223
1224 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1225 }
1226
1227 void ironlake_disable_fbc(struct drm_device *dev)
1228 {
1229 struct drm_i915_private *dev_priv = dev->dev_private;
1230 u32 dpfc_ctl;
1231
1232 /* Disable compression */
1233 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1234 dpfc_ctl &= ~DPFC_CTL_EN;
1235 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1236
1237 DRM_DEBUG_KMS("disabled FBC\n");
1238 }
1239
1240 static bool ironlake_fbc_enabled(struct drm_device *dev)
1241 {
1242 struct drm_i915_private *dev_priv = dev->dev_private;
1243
1244 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1245 }
1246
1247 bool intel_fbc_enabled(struct drm_device *dev)
1248 {
1249 struct drm_i915_private *dev_priv = dev->dev_private;
1250
1251 if (!dev_priv->display.fbc_enabled)
1252 return false;
1253
1254 return dev_priv->display.fbc_enabled(dev);
1255 }
1256
1257 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1258 {
1259 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1260
1261 if (!dev_priv->display.enable_fbc)
1262 return;
1263
1264 dev_priv->display.enable_fbc(crtc, interval);
1265 }
1266
1267 void intel_disable_fbc(struct drm_device *dev)
1268 {
1269 struct drm_i915_private *dev_priv = dev->dev_private;
1270
1271 if (!dev_priv->display.disable_fbc)
1272 return;
1273
1274 dev_priv->display.disable_fbc(dev);
1275 }
1276
1277 /**
1278 * intel_update_fbc - enable/disable FBC as needed
1279 * @crtc: CRTC to point the compressor at
1280 * @mode: mode in use
1281 *
1282 * Set up the framebuffer compression hardware at mode set time. We
1283 * enable it if possible:
1284 * - plane A only (on pre-965)
1285 * - no pixel mulitply/line duplication
1286 * - no alpha buffer discard
1287 * - no dual wide
1288 * - framebuffer <= 2048 in width, 1536 in height
1289 *
1290 * We can't assume that any compression will take place (worst case),
1291 * so the compressed buffer has to be the same size as the uncompressed
1292 * one. It also must reside (along with the line length buffer) in
1293 * stolen memory.
1294 *
1295 * We need to enable/disable FBC on a global basis.
1296 */
1297 static void intel_update_fbc(struct drm_crtc *crtc,
1298 struct drm_display_mode *mode)
1299 {
1300 struct drm_device *dev = crtc->dev;
1301 struct drm_i915_private *dev_priv = dev->dev_private;
1302 struct drm_framebuffer *fb = crtc->fb;
1303 struct intel_framebuffer *intel_fb;
1304 struct drm_i915_gem_object *obj_priv;
1305 struct drm_crtc *tmp_crtc;
1306 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1307 int plane = intel_crtc->plane;
1308 int crtcs_enabled = 0;
1309
1310 DRM_DEBUG_KMS("\n");
1311
1312 if (!i915_powersave)
1313 return;
1314
1315 if (!I915_HAS_FBC(dev))
1316 return;
1317
1318 if (!crtc->fb)
1319 return;
1320
1321 intel_fb = to_intel_framebuffer(fb);
1322 obj_priv = to_intel_bo(intel_fb->obj);
1323
1324 /*
1325 * If FBC is already on, we just have to verify that we can
1326 * keep it that way...
1327 * Need to disable if:
1328 * - more than one pipe is active
1329 * - changing FBC params (stride, fence, mode)
1330 * - new fb is too large to fit in compressed buffer
1331 * - going to an unsupported config (interlace, pixel multiply, etc.)
1332 */
1333 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1334 if (tmp_crtc->enabled)
1335 crtcs_enabled++;
1336 }
1337 DRM_DEBUG_KMS("%d pipes active\n", crtcs_enabled);
1338 if (crtcs_enabled > 1) {
1339 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1340 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1341 goto out_disable;
1342 }
1343 if (intel_fb->obj->size > dev_priv->cfb_size) {
1344 DRM_DEBUG_KMS("framebuffer too large, disabling "
1345 "compression\n");
1346 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1347 goto out_disable;
1348 }
1349 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1350 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1351 DRM_DEBUG_KMS("mode incompatible with compression, "
1352 "disabling\n");
1353 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1354 goto out_disable;
1355 }
1356 if ((mode->hdisplay > 2048) ||
1357 (mode->vdisplay > 1536)) {
1358 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1359 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1360 goto out_disable;
1361 }
1362 if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1363 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1364 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1365 goto out_disable;
1366 }
1367 if (obj_priv->tiling_mode != I915_TILING_X) {
1368 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1369 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1370 goto out_disable;
1371 }
1372
1373 /* If the kernel debugger is active, always disable compression */
1374 if (in_dbg_master())
1375 goto out_disable;
1376
1377 if (intel_fbc_enabled(dev)) {
1378 /* We can re-enable it in this case, but need to update pitch */
1379 if ((fb->pitch > dev_priv->cfb_pitch) ||
1380 (obj_priv->fence_reg != dev_priv->cfb_fence) ||
1381 (plane != dev_priv->cfb_plane))
1382 intel_disable_fbc(dev);
1383 }
1384
1385 /* Now try to turn it back on if possible */
1386 if (!intel_fbc_enabled(dev))
1387 intel_enable_fbc(crtc, 500);
1388
1389 return;
1390
1391 out_disable:
1392 /* Multiple disables should be harmless */
1393 if (intel_fbc_enabled(dev)) {
1394 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1395 intel_disable_fbc(dev);
1396 }
1397 }
1398
1399 int
1400 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1401 {
1402 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1403 u32 alignment;
1404 int ret;
1405
1406 switch (obj_priv->tiling_mode) {
1407 case I915_TILING_NONE:
1408 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1409 alignment = 128 * 1024;
1410 else if (IS_I965G(dev))
1411 alignment = 4 * 1024;
1412 else
1413 alignment = 64 * 1024;
1414 break;
1415 case I915_TILING_X:
1416 /* pin() will align the object as required by fence */
1417 alignment = 0;
1418 break;
1419 case I915_TILING_Y:
1420 /* FIXME: Is this true? */
1421 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1422 return -EINVAL;
1423 default:
1424 BUG();
1425 }
1426
1427 ret = i915_gem_object_pin(obj, alignment);
1428 if (ret != 0)
1429 return ret;
1430
1431 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1432 * fence, whereas 965+ only requires a fence if using
1433 * framebuffer compression. For simplicity, we always install
1434 * a fence as the cost is not that onerous.
1435 */
1436 if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1437 obj_priv->tiling_mode != I915_TILING_NONE) {
1438 ret = i915_gem_object_get_fence_reg(obj);
1439 if (ret != 0) {
1440 i915_gem_object_unpin(obj);
1441 return ret;
1442 }
1443 }
1444
1445 return 0;
1446 }
1447
1448 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1449 static int
1450 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1451 int x, int y)
1452 {
1453 struct drm_device *dev = crtc->dev;
1454 struct drm_i915_private *dev_priv = dev->dev_private;
1455 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1456 struct intel_framebuffer *intel_fb;
1457 struct drm_i915_gem_object *obj_priv;
1458 struct drm_gem_object *obj;
1459 int plane = intel_crtc->plane;
1460 unsigned long Start, Offset;
1461 int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1462 int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1463 int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1464 int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1465 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1466 u32 dspcntr;
1467
1468 switch (plane) {
1469 case 0:
1470 case 1:
1471 break;
1472 default:
1473 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1474 return -EINVAL;
1475 }
1476
1477 intel_fb = to_intel_framebuffer(fb);
1478 obj = intel_fb->obj;
1479 obj_priv = to_intel_bo(obj);
1480
1481 dspcntr = I915_READ(dspcntr_reg);
1482 /* Mask out pixel format bits in case we change it */
1483 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1484 switch (fb->bits_per_pixel) {
1485 case 8:
1486 dspcntr |= DISPPLANE_8BPP;
1487 break;
1488 case 16:
1489 if (fb->depth == 15)
1490 dspcntr |= DISPPLANE_15_16BPP;
1491 else
1492 dspcntr |= DISPPLANE_16BPP;
1493 break;
1494 case 24:
1495 case 32:
1496 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1497 break;
1498 default:
1499 DRM_ERROR("Unknown color depth\n");
1500 return -EINVAL;
1501 }
1502 if (IS_I965G(dev)) {
1503 if (obj_priv->tiling_mode != I915_TILING_NONE)
1504 dspcntr |= DISPPLANE_TILED;
1505 else
1506 dspcntr &= ~DISPPLANE_TILED;
1507 }
1508
1509 if (HAS_PCH_SPLIT(dev))
1510 /* must disable */
1511 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1512
1513 I915_WRITE(dspcntr_reg, dspcntr);
1514
1515 Start = obj_priv->gtt_offset;
1516 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1517
1518 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1519 Start, Offset, x, y, fb->pitch);
1520 I915_WRITE(dspstride, fb->pitch);
1521 if (IS_I965G(dev)) {
1522 I915_WRITE(dspsurf, Start);
1523 I915_WRITE(dsptileoff, (y << 16) | x);
1524 I915_WRITE(dspbase, Offset);
1525 } else {
1526 I915_WRITE(dspbase, Start + Offset);
1527 }
1528 POSTING_READ(dspbase);
1529
1530 if (IS_I965G(dev) || plane == 0)
1531 intel_update_fbc(crtc, &crtc->mode);
1532
1533 intel_wait_for_vblank(dev, intel_crtc->pipe);
1534 intel_increase_pllclock(crtc);
1535
1536 return 0;
1537 }
1538
1539 static int
1540 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1541 struct drm_framebuffer *old_fb)
1542 {
1543 struct drm_device *dev = crtc->dev;
1544 struct drm_i915_master_private *master_priv;
1545 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1546 struct intel_framebuffer *intel_fb;
1547 struct drm_i915_gem_object *obj_priv;
1548 struct drm_gem_object *obj;
1549 int pipe = intel_crtc->pipe;
1550 int plane = intel_crtc->plane;
1551 int ret;
1552
1553 /* no fb bound */
1554 if (!crtc->fb) {
1555 DRM_DEBUG_KMS("No FB bound\n");
1556 return 0;
1557 }
1558
1559 switch (plane) {
1560 case 0:
1561 case 1:
1562 break;
1563 default:
1564 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1565 return -EINVAL;
1566 }
1567
1568 intel_fb = to_intel_framebuffer(crtc->fb);
1569 obj = intel_fb->obj;
1570 obj_priv = to_intel_bo(obj);
1571
1572 mutex_lock(&dev->struct_mutex);
1573 ret = intel_pin_and_fence_fb_obj(dev, obj);
1574 if (ret != 0) {
1575 mutex_unlock(&dev->struct_mutex);
1576 return ret;
1577 }
1578
1579 ret = i915_gem_object_set_to_display_plane(obj);
1580 if (ret != 0) {
1581 i915_gem_object_unpin(obj);
1582 mutex_unlock(&dev->struct_mutex);
1583 return ret;
1584 }
1585
1586 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y);
1587 if (ret) {
1588 i915_gem_object_unpin(obj);
1589 mutex_unlock(&dev->struct_mutex);
1590 return ret;
1591 }
1592
1593 if (old_fb) {
1594 intel_fb = to_intel_framebuffer(old_fb);
1595 obj_priv = to_intel_bo(intel_fb->obj);
1596 i915_gem_object_unpin(intel_fb->obj);
1597 }
1598
1599 mutex_unlock(&dev->struct_mutex);
1600
1601 if (!dev->primary->master)
1602 return 0;
1603
1604 master_priv = dev->primary->master->driver_priv;
1605 if (!master_priv->sarea_priv)
1606 return 0;
1607
1608 if (pipe) {
1609 master_priv->sarea_priv->pipeB_x = x;
1610 master_priv->sarea_priv->pipeB_y = y;
1611 } else {
1612 master_priv->sarea_priv->pipeA_x = x;
1613 master_priv->sarea_priv->pipeA_y = y;
1614 }
1615
1616 return 0;
1617 }
1618
1619 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1620 {
1621 struct drm_device *dev = crtc->dev;
1622 struct drm_i915_private *dev_priv = dev->dev_private;
1623 u32 dpa_ctl;
1624
1625 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1626 dpa_ctl = I915_READ(DP_A);
1627 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1628
1629 if (clock < 200000) {
1630 u32 temp;
1631 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1632 /* workaround for 160Mhz:
1633 1) program 0x4600c bits 15:0 = 0x8124
1634 2) program 0x46010 bit 0 = 1
1635 3) program 0x46034 bit 24 = 1
1636 4) program 0x64000 bit 14 = 1
1637 */
1638 temp = I915_READ(0x4600c);
1639 temp &= 0xffff0000;
1640 I915_WRITE(0x4600c, temp | 0x8124);
1641
1642 temp = I915_READ(0x46010);
1643 I915_WRITE(0x46010, temp | 1);
1644
1645 temp = I915_READ(0x46034);
1646 I915_WRITE(0x46034, temp | (1 << 24));
1647 } else {
1648 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1649 }
1650 I915_WRITE(DP_A, dpa_ctl);
1651 POSTING_READ(DP_A);
1652
1653 udelay(500);
1654 }
1655
1656 /* The FDI link training functions for ILK/Ibexpeak. */
1657 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1658 {
1659 struct drm_device *dev = crtc->dev;
1660 struct drm_i915_private *dev_priv = dev->dev_private;
1661 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1662 int pipe = intel_crtc->pipe;
1663 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1664 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1665 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1666 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1667 u32 temp, tries = 0;
1668
1669 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1670 for train result */
1671 temp = I915_READ(fdi_rx_imr_reg);
1672 temp &= ~FDI_RX_SYMBOL_LOCK;
1673 temp &= ~FDI_RX_BIT_LOCK;
1674 I915_WRITE(fdi_rx_imr_reg, temp);
1675 I915_READ(fdi_rx_imr_reg);
1676 udelay(150);
1677
1678 /* enable CPU FDI TX and PCH FDI RX */
1679 temp = I915_READ(fdi_tx_reg);
1680 temp |= FDI_TX_ENABLE;
1681 temp &= ~(7 << 19);
1682 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1683 temp &= ~FDI_LINK_TRAIN_NONE;
1684 temp |= FDI_LINK_TRAIN_PATTERN_1;
1685 I915_WRITE(fdi_tx_reg, temp);
1686 I915_READ(fdi_tx_reg);
1687
1688 temp = I915_READ(fdi_rx_reg);
1689 temp &= ~FDI_LINK_TRAIN_NONE;
1690 temp |= FDI_LINK_TRAIN_PATTERN_1;
1691 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1692 I915_READ(fdi_rx_reg);
1693 udelay(150);
1694
1695 for (tries = 0; tries < 5; tries++) {
1696 temp = I915_READ(fdi_rx_iir_reg);
1697 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1698
1699 if ((temp & FDI_RX_BIT_LOCK)) {
1700 DRM_DEBUG_KMS("FDI train 1 done.\n");
1701 I915_WRITE(fdi_rx_iir_reg,
1702 temp | FDI_RX_BIT_LOCK);
1703 break;
1704 }
1705 }
1706 if (tries == 5)
1707 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1708
1709 /* Train 2 */
1710 temp = I915_READ(fdi_tx_reg);
1711 temp &= ~FDI_LINK_TRAIN_NONE;
1712 temp |= FDI_LINK_TRAIN_PATTERN_2;
1713 I915_WRITE(fdi_tx_reg, temp);
1714
1715 temp = I915_READ(fdi_rx_reg);
1716 temp &= ~FDI_LINK_TRAIN_NONE;
1717 temp |= FDI_LINK_TRAIN_PATTERN_2;
1718 I915_WRITE(fdi_rx_reg, temp);
1719 POSTING_READ(fdi_rx_reg);
1720 udelay(150);
1721
1722 tries = 0;
1723
1724 for (tries = 0; tries < 5; tries++) {
1725 temp = I915_READ(fdi_rx_iir_reg);
1726 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1727
1728 if (temp & FDI_RX_SYMBOL_LOCK) {
1729 I915_WRITE(fdi_rx_iir_reg,
1730 temp | FDI_RX_SYMBOL_LOCK);
1731 DRM_DEBUG_KMS("FDI train 2 done.\n");
1732 break;
1733 }
1734 }
1735 if (tries == 5)
1736 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1737
1738 DRM_DEBUG_KMS("FDI train done\n");
1739 }
1740
1741 static int snb_b_fdi_train_param [] = {
1742 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1743 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1744 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1745 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1746 };
1747
1748 /* The FDI link training functions for SNB/Cougarpoint. */
1749 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1750 {
1751 struct drm_device *dev = crtc->dev;
1752 struct drm_i915_private *dev_priv = dev->dev_private;
1753 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1754 int pipe = intel_crtc->pipe;
1755 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1756 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1757 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1758 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1759 u32 temp, i;
1760
1761 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1762 for train result */
1763 temp = I915_READ(fdi_rx_imr_reg);
1764 temp &= ~FDI_RX_SYMBOL_LOCK;
1765 temp &= ~FDI_RX_BIT_LOCK;
1766 I915_WRITE(fdi_rx_imr_reg, temp);
1767 I915_READ(fdi_rx_imr_reg);
1768 udelay(150);
1769
1770 /* enable CPU FDI TX and PCH FDI RX */
1771 temp = I915_READ(fdi_tx_reg);
1772 temp |= FDI_TX_ENABLE;
1773 temp &= ~(7 << 19);
1774 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1775 temp &= ~FDI_LINK_TRAIN_NONE;
1776 temp |= FDI_LINK_TRAIN_PATTERN_1;
1777 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1778 /* SNB-B */
1779 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1780 I915_WRITE(fdi_tx_reg, temp);
1781 I915_READ(fdi_tx_reg);
1782
1783 temp = I915_READ(fdi_rx_reg);
1784 if (HAS_PCH_CPT(dev)) {
1785 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1786 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1787 } else {
1788 temp &= ~FDI_LINK_TRAIN_NONE;
1789 temp |= FDI_LINK_TRAIN_PATTERN_1;
1790 }
1791 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1792 I915_READ(fdi_rx_reg);
1793 udelay(150);
1794
1795 for (i = 0; i < 4; i++ ) {
1796 temp = I915_READ(fdi_tx_reg);
1797 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1798 temp |= snb_b_fdi_train_param[i];
1799 I915_WRITE(fdi_tx_reg, temp);
1800 POSTING_READ(fdi_tx_reg);
1801 udelay(500);
1802
1803 temp = I915_READ(fdi_rx_iir_reg);
1804 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1805
1806 if (temp & FDI_RX_BIT_LOCK) {
1807 I915_WRITE(fdi_rx_iir_reg,
1808 temp | FDI_RX_BIT_LOCK);
1809 DRM_DEBUG_KMS("FDI train 1 done.\n");
1810 break;
1811 }
1812 }
1813 if (i == 4)
1814 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1815
1816 /* Train 2 */
1817 temp = I915_READ(fdi_tx_reg);
1818 temp &= ~FDI_LINK_TRAIN_NONE;
1819 temp |= FDI_LINK_TRAIN_PATTERN_2;
1820 if (IS_GEN6(dev)) {
1821 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1822 /* SNB-B */
1823 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1824 }
1825 I915_WRITE(fdi_tx_reg, temp);
1826
1827 temp = I915_READ(fdi_rx_reg);
1828 if (HAS_PCH_CPT(dev)) {
1829 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1830 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1831 } else {
1832 temp &= ~FDI_LINK_TRAIN_NONE;
1833 temp |= FDI_LINK_TRAIN_PATTERN_2;
1834 }
1835 I915_WRITE(fdi_rx_reg, temp);
1836 POSTING_READ(fdi_rx_reg);
1837 udelay(150);
1838
1839 for (i = 0; i < 4; i++ ) {
1840 temp = I915_READ(fdi_tx_reg);
1841 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1842 temp |= snb_b_fdi_train_param[i];
1843 I915_WRITE(fdi_tx_reg, temp);
1844 POSTING_READ(fdi_tx_reg);
1845 udelay(500);
1846
1847 temp = I915_READ(fdi_rx_iir_reg);
1848 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1849
1850 if (temp & FDI_RX_SYMBOL_LOCK) {
1851 I915_WRITE(fdi_rx_iir_reg,
1852 temp | FDI_RX_SYMBOL_LOCK);
1853 DRM_DEBUG_KMS("FDI train 2 done.\n");
1854 break;
1855 }
1856 }
1857 if (i == 4)
1858 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1859
1860 DRM_DEBUG_KMS("FDI train done.\n");
1861 }
1862
1863 static void ironlake_fdi_enable(struct drm_crtc *crtc)
1864 {
1865 struct drm_device *dev = crtc->dev;
1866 struct drm_i915_private *dev_priv = dev->dev_private;
1867 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1868 int pipe = intel_crtc->pipe;
1869 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1870 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1871 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1872 int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
1873 u32 temp;
1874 u32 pipe_bpc;
1875 u32 tx_size;
1876
1877 temp = I915_READ(pipeconf_reg);
1878 pipe_bpc = temp & PIPE_BPC_MASK;
1879
1880 /* Write the TU size bits so error detection works */
1881 tx_size = I915_READ(data_m1_reg) & TU_SIZE_MASK;
1882 I915_WRITE(FDI_RXA_TUSIZE1, tx_size);
1883
1884 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1885 temp = I915_READ(fdi_rx_reg);
1886 /*
1887 * make the BPC in FDI Rx be consistent with that in
1888 * pipeconf reg.
1889 */
1890 temp &= ~(0x7 << 16);
1891 temp |= (pipe_bpc << 11);
1892 temp &= ~(7 << 19);
1893 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1894 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
1895 I915_READ(fdi_rx_reg);
1896 udelay(200);
1897
1898 /* Switch from Rawclk to PCDclk */
1899 temp = I915_READ(fdi_rx_reg);
1900 I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
1901 I915_READ(fdi_rx_reg);
1902 udelay(200);
1903
1904 /* Enable CPU FDI TX PLL, always on for Ironlake */
1905 temp = I915_READ(fdi_tx_reg);
1906 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1907 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1908 I915_READ(fdi_tx_reg);
1909 udelay(100);
1910 }
1911 }
1912
1913 static void ironlake_crtc_enable(struct drm_crtc *crtc)
1914 {
1915 struct drm_device *dev = crtc->dev;
1916 struct drm_i915_private *dev_priv = dev->dev_private;
1917 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1918 int pipe = intel_crtc->pipe;
1919 int plane = intel_crtc->plane;
1920 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1921 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1922 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1923 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1924 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1925 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1926 int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1927 int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1928 int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1929 int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1930 int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1931 int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1932 int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1933 int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1934 int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1935 int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1936 int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1937 int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1938 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1939 int trans_dpll_sel = (pipe == 0) ? 0 : 1;
1940 u32 temp;
1941 u32 pipe_bpc;
1942
1943 temp = I915_READ(pipeconf_reg);
1944 pipe_bpc = temp & PIPE_BPC_MASK;
1945
1946 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1947 temp = I915_READ(PCH_LVDS);
1948 if ((temp & LVDS_PORT_EN) == 0) {
1949 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1950 POSTING_READ(PCH_LVDS);
1951 }
1952 }
1953
1954 ironlake_fdi_enable(crtc);
1955
1956 /* Enable panel fitting for LVDS */
1957 if (dev_priv->pch_pf_size &&
1958 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
1959 || HAS_eDP || intel_pch_has_edp(crtc))) {
1960 /* Force use of hard-coded filter coefficients
1961 * as some pre-programmed values are broken,
1962 * e.g. x201.
1963 */
1964 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
1965 PF_ENABLE | PF_FILTER_MED_3x3);
1966 I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
1967 dev_priv->pch_pf_pos);
1968 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
1969 dev_priv->pch_pf_size);
1970 }
1971
1972 /* Enable CPU pipe */
1973 temp = I915_READ(pipeconf_reg);
1974 if ((temp & PIPEACONF_ENABLE) == 0) {
1975 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1976 I915_READ(pipeconf_reg);
1977 udelay(100);
1978 }
1979
1980 /* configure and enable CPU plane */
1981 temp = I915_READ(dspcntr_reg);
1982 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1983 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1984 /* Flush the plane changes */
1985 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1986 }
1987
1988 /* For PCH output, training FDI link */
1989 if (IS_GEN6(dev))
1990 gen6_fdi_link_train(crtc);
1991 else
1992 ironlake_fdi_link_train(crtc);
1993
1994 /* enable PCH DPLL */
1995 temp = I915_READ(pch_dpll_reg);
1996 if ((temp & DPLL_VCO_ENABLE) == 0) {
1997 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1998 I915_READ(pch_dpll_reg);
1999 udelay(200);
2000 }
2001
2002 if (HAS_PCH_CPT(dev)) {
2003 /* Be sure PCH DPLL SEL is set */
2004 temp = I915_READ(PCH_DPLL_SEL);
2005 if (trans_dpll_sel == 0 &&
2006 (temp & TRANSA_DPLL_ENABLE) == 0)
2007 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2008 else if (trans_dpll_sel == 1 &&
2009 (temp & TRANSB_DPLL_ENABLE) == 0)
2010 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2011 I915_WRITE(PCH_DPLL_SEL, temp);
2012 I915_READ(PCH_DPLL_SEL);
2013 }
2014 /* set transcoder timing */
2015 I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
2016 I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
2017 I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
2018
2019 I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
2020 I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
2021 I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
2022
2023 /* enable normal train */
2024 temp = I915_READ(fdi_tx_reg);
2025 temp &= ~FDI_LINK_TRAIN_NONE;
2026 I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
2027 FDI_TX_ENHANCE_FRAME_ENABLE);
2028 I915_READ(fdi_tx_reg);
2029
2030 temp = I915_READ(fdi_rx_reg);
2031 if (HAS_PCH_CPT(dev)) {
2032 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2033 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2034 } else {
2035 temp &= ~FDI_LINK_TRAIN_NONE;
2036 temp |= FDI_LINK_TRAIN_NONE;
2037 }
2038 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2039 I915_READ(fdi_rx_reg);
2040
2041 /* wait one idle pattern time */
2042 udelay(100);
2043
2044 /* For PCH DP, enable TRANS_DP_CTL */
2045 if (HAS_PCH_CPT(dev) &&
2046 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2047 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2048 int reg;
2049
2050 reg = I915_READ(trans_dp_ctl);
2051 reg &= ~(TRANS_DP_PORT_SEL_MASK |
2052 TRANS_DP_SYNC_MASK);
2053 reg |= (TRANS_DP_OUTPUT_ENABLE |
2054 TRANS_DP_ENH_FRAMING);
2055
2056 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2057 reg |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2058 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2059 reg |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2060
2061 switch (intel_trans_dp_port_sel(crtc)) {
2062 case PCH_DP_B:
2063 reg |= TRANS_DP_PORT_SEL_B;
2064 break;
2065 case PCH_DP_C:
2066 reg |= TRANS_DP_PORT_SEL_C;
2067 break;
2068 case PCH_DP_D:
2069 reg |= TRANS_DP_PORT_SEL_D;
2070 break;
2071 default:
2072 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2073 reg |= TRANS_DP_PORT_SEL_B;
2074 break;
2075 }
2076
2077 I915_WRITE(trans_dp_ctl, reg);
2078 POSTING_READ(trans_dp_ctl);
2079 }
2080
2081 /* enable PCH transcoder */
2082 temp = I915_READ(transconf_reg);
2083 /*
2084 * make the BPC in transcoder be consistent with
2085 * that in pipeconf reg.
2086 */
2087 temp &= ~PIPE_BPC_MASK;
2088 temp |= pipe_bpc;
2089 I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
2090 I915_READ(transconf_reg);
2091
2092 if (wait_for(I915_READ(transconf_reg) & TRANS_STATE_ENABLE, 100))
2093 DRM_ERROR("failed to enable transcoder\n");
2094
2095 intel_crtc_load_lut(crtc);
2096
2097 intel_update_fbc(crtc, &crtc->mode);
2098 }
2099
2100 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2101 {
2102 struct drm_device *dev = crtc->dev;
2103 struct drm_i915_private *dev_priv = dev->dev_private;
2104 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2105 int pipe = intel_crtc->pipe;
2106 int plane = intel_crtc->plane;
2107 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
2108 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2109 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2110 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
2111 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
2112 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
2113 int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
2114 int trans_dpll_sel = (pipe == 0) ? 0 : 1;
2115 u32 temp;
2116 u32 pipe_bpc;
2117
2118 temp = I915_READ(pipeconf_reg);
2119 pipe_bpc = temp & PIPE_BPC_MASK;
2120
2121 drm_vblank_off(dev, pipe);
2122 /* Disable display plane */
2123 temp = I915_READ(dspcntr_reg);
2124 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2125 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2126 /* Flush the plane changes */
2127 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2128 I915_READ(dspbase_reg);
2129 }
2130
2131 if (dev_priv->cfb_plane == plane &&
2132 dev_priv->display.disable_fbc)
2133 dev_priv->display.disable_fbc(dev);
2134
2135 /* disable cpu pipe, disable after all planes disabled */
2136 temp = I915_READ(pipeconf_reg);
2137 if ((temp & PIPEACONF_ENABLE) != 0) {
2138 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2139
2140 /* wait for cpu pipe off, pipe state */
2141 if (wait_for((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) == 0, 50))
2142 DRM_ERROR("failed to turn off cpu pipe\n");
2143 } else
2144 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
2145
2146 /* Disable PF */
2147 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0);
2148 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0);
2149
2150 /* disable CPU FDI tx and PCH FDI rx */
2151 temp = I915_READ(fdi_tx_reg);
2152 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
2153 I915_READ(fdi_tx_reg);
2154
2155 temp = I915_READ(fdi_rx_reg);
2156 /* BPC in FDI rx is consistent with that in pipeconf */
2157 temp &= ~(0x07 << 16);
2158 temp |= (pipe_bpc << 11);
2159 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
2160 I915_READ(fdi_rx_reg);
2161
2162 udelay(100);
2163
2164 /* still set train pattern 1 */
2165 temp = I915_READ(fdi_tx_reg);
2166 temp &= ~FDI_LINK_TRAIN_NONE;
2167 temp |= FDI_LINK_TRAIN_PATTERN_1;
2168 I915_WRITE(fdi_tx_reg, temp);
2169 POSTING_READ(fdi_tx_reg);
2170
2171 temp = I915_READ(fdi_rx_reg);
2172 if (HAS_PCH_CPT(dev)) {
2173 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2174 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2175 } else {
2176 temp &= ~FDI_LINK_TRAIN_NONE;
2177 temp |= FDI_LINK_TRAIN_PATTERN_1;
2178 }
2179 I915_WRITE(fdi_rx_reg, temp);
2180 POSTING_READ(fdi_rx_reg);
2181
2182 udelay(100);
2183
2184 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2185 temp = I915_READ(PCH_LVDS);
2186 I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2187 I915_READ(PCH_LVDS);
2188 udelay(100);
2189 }
2190
2191 /* disable PCH transcoder */
2192 temp = I915_READ(transconf_reg);
2193 if ((temp & TRANS_ENABLE) != 0) {
2194 I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
2195
2196 /* wait for PCH transcoder off, transcoder state */
2197 if (wait_for((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0, 50))
2198 DRM_ERROR("failed to disable transcoder\n");
2199 }
2200
2201 temp = I915_READ(transconf_reg);
2202 /* BPC in transcoder is consistent with that in pipeconf */
2203 temp &= ~PIPE_BPC_MASK;
2204 temp |= pipe_bpc;
2205 I915_WRITE(transconf_reg, temp);
2206 I915_READ(transconf_reg);
2207 udelay(100);
2208
2209 if (HAS_PCH_CPT(dev)) {
2210 /* disable TRANS_DP_CTL */
2211 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2212 int reg;
2213
2214 reg = I915_READ(trans_dp_ctl);
2215 reg &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2216 I915_WRITE(trans_dp_ctl, reg);
2217 POSTING_READ(trans_dp_ctl);
2218
2219 /* disable DPLL_SEL */
2220 temp = I915_READ(PCH_DPLL_SEL);
2221 if (trans_dpll_sel == 0)
2222 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2223 else
2224 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2225 I915_WRITE(PCH_DPLL_SEL, temp);
2226 I915_READ(PCH_DPLL_SEL);
2227
2228 }
2229
2230 /* disable PCH DPLL */
2231 temp = I915_READ(pch_dpll_reg);
2232 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
2233 I915_READ(pch_dpll_reg);
2234
2235 /* Switch from PCDclk to Rawclk */
2236 temp = I915_READ(fdi_rx_reg);
2237 temp &= ~FDI_SEL_PCDCLK;
2238 I915_WRITE(fdi_rx_reg, temp);
2239 I915_READ(fdi_rx_reg);
2240
2241 /* Disable CPU FDI TX PLL */
2242 temp = I915_READ(fdi_tx_reg);
2243 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
2244 I915_READ(fdi_tx_reg);
2245 udelay(100);
2246
2247 temp = I915_READ(fdi_rx_reg);
2248 temp &= ~FDI_RX_PLL_ENABLE;
2249 I915_WRITE(fdi_rx_reg, temp);
2250 I915_READ(fdi_rx_reg);
2251
2252 /* Wait for the clocks to turn off. */
2253 udelay(100);
2254 }
2255
2256 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2257 {
2258 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2259 int pipe = intel_crtc->pipe;
2260 int plane = intel_crtc->plane;
2261
2262 /* XXX: When our outputs are all unaware of DPMS modes other than off
2263 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2264 */
2265 switch (mode) {
2266 case DRM_MODE_DPMS_ON:
2267 case DRM_MODE_DPMS_STANDBY:
2268 case DRM_MODE_DPMS_SUSPEND:
2269 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2270 ironlake_crtc_enable(crtc);
2271 break;
2272
2273 case DRM_MODE_DPMS_OFF:
2274 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2275 ironlake_crtc_disable(crtc);
2276 break;
2277 }
2278 }
2279
2280 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2281 {
2282 if (!enable && intel_crtc->overlay) {
2283 struct drm_device *dev = intel_crtc->base.dev;
2284
2285 mutex_lock(&dev->struct_mutex);
2286 (void) intel_overlay_switch_off(intel_crtc->overlay, false);
2287 mutex_unlock(&dev->struct_mutex);
2288 }
2289
2290 /* Let userspace switch the overlay on again. In most cases userspace
2291 * has to recompute where to put it anyway.
2292 */
2293 }
2294
2295 static void i9xx_crtc_enable(struct drm_crtc *crtc)
2296 {
2297 struct drm_device *dev = crtc->dev;
2298 struct drm_i915_private *dev_priv = dev->dev_private;
2299 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2300 int pipe = intel_crtc->pipe;
2301 int plane = intel_crtc->plane;
2302 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2303 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2304 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
2305 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2306 u32 temp;
2307
2308 /* Enable the DPLL */
2309 temp = I915_READ(dpll_reg);
2310 if ((temp & DPLL_VCO_ENABLE) == 0) {
2311 I915_WRITE(dpll_reg, temp);
2312 I915_READ(dpll_reg);
2313 /* Wait for the clocks to stabilize. */
2314 udelay(150);
2315 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2316 I915_READ(dpll_reg);
2317 /* Wait for the clocks to stabilize. */
2318 udelay(150);
2319 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2320 I915_READ(dpll_reg);
2321 /* Wait for the clocks to stabilize. */
2322 udelay(150);
2323 }
2324
2325 /* Enable the pipe */
2326 temp = I915_READ(pipeconf_reg);
2327 if ((temp & PIPEACONF_ENABLE) == 0)
2328 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
2329
2330 /* Enable the plane */
2331 temp = I915_READ(dspcntr_reg);
2332 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2333 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
2334 /* Flush the plane changes */
2335 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2336 }
2337
2338 intel_crtc_load_lut(crtc);
2339
2340 if ((IS_I965G(dev) || plane == 0))
2341 intel_update_fbc(crtc, &crtc->mode);
2342
2343 /* Give the overlay scaler a chance to enable if it's on this pipe */
2344 intel_crtc_dpms_overlay(intel_crtc, true);
2345 }
2346
2347 static void i9xx_crtc_disable(struct drm_crtc *crtc)
2348 {
2349 struct drm_device *dev = crtc->dev;
2350 struct drm_i915_private *dev_priv = dev->dev_private;
2351 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2352 int pipe = intel_crtc->pipe;
2353 int plane = intel_crtc->plane;
2354 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2355 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2356 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
2357 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2358 u32 temp;
2359
2360 /* Give the overlay scaler a chance to disable if it's on this pipe */
2361 intel_crtc_dpms_overlay(intel_crtc, false);
2362 drm_vblank_off(dev, pipe);
2363
2364 if (dev_priv->cfb_plane == plane &&
2365 dev_priv->display.disable_fbc)
2366 dev_priv->display.disable_fbc(dev);
2367
2368 /* Disable display plane */
2369 temp = I915_READ(dspcntr_reg);
2370 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2371 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2372 /* Flush the plane changes */
2373 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2374 I915_READ(dspbase_reg);
2375 }
2376
2377 if (!IS_I9XX(dev)) {
2378 /* Wait for vblank for the disable to take effect */
2379 intel_wait_for_vblank_off(dev, pipe);
2380 }
2381
2382 /* Don't disable pipe A or pipe A PLLs if needed */
2383 if (pipeconf_reg == PIPEACONF &&
2384 (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2385 goto skip_pipe_off;
2386
2387 /* Next, disable display pipes */
2388 temp = I915_READ(pipeconf_reg);
2389 if ((temp & PIPEACONF_ENABLE) != 0) {
2390 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2391 I915_READ(pipeconf_reg);
2392 }
2393
2394 /* Wait for vblank for the disable to take effect. */
2395 intel_wait_for_vblank_off(dev, pipe);
2396
2397 temp = I915_READ(dpll_reg);
2398 if ((temp & DPLL_VCO_ENABLE) != 0) {
2399 I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
2400 I915_READ(dpll_reg);
2401 }
2402 skip_pipe_off:
2403 /* Wait for the clocks to turn off. */
2404 udelay(150);
2405 }
2406
2407 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2408 {
2409 /* XXX: When our outputs are all unaware of DPMS modes other than off
2410 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2411 */
2412 switch (mode) {
2413 case DRM_MODE_DPMS_ON:
2414 case DRM_MODE_DPMS_STANDBY:
2415 case DRM_MODE_DPMS_SUSPEND:
2416 i9xx_crtc_enable(crtc);
2417 break;
2418 case DRM_MODE_DPMS_OFF:
2419 i9xx_crtc_disable(crtc);
2420 break;
2421 }
2422 }
2423
2424 /*
2425 * When we disable a pipe, we need to clear any pending scanline wait events
2426 * to avoid hanging the ring, which we assume we are waiting on.
2427 */
2428 static void intel_clear_scanline_wait(struct drm_device *dev)
2429 {
2430 struct drm_i915_private *dev_priv = dev->dev_private;
2431 u32 tmp;
2432
2433 if (IS_GEN2(dev))
2434 /* Can't break the hang on i8xx */
2435 return;
2436
2437 tmp = I915_READ(PRB0_CTL);
2438 if (tmp & RING_WAIT) {
2439 I915_WRITE(PRB0_CTL, tmp);
2440 POSTING_READ(PRB0_CTL);
2441 }
2442 }
2443
2444 /**
2445 * Sets the power management mode of the pipe and plane.
2446 */
2447 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2448 {
2449 struct drm_device *dev = crtc->dev;
2450 struct drm_i915_private *dev_priv = dev->dev_private;
2451 struct drm_i915_master_private *master_priv;
2452 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2453 int pipe = intel_crtc->pipe;
2454 bool enabled;
2455
2456 if (intel_crtc->dpms_mode == mode)
2457 return;
2458
2459 intel_crtc->dpms_mode = mode;
2460 intel_crtc->cursor_on = mode == DRM_MODE_DPMS_ON;
2461
2462 /* When switching on the display, ensure that SR is disabled
2463 * with multiple pipes prior to enabling to new pipe.
2464 *
2465 * When switching off the display, make sure the cursor is
2466 * properly hidden and there are no pending waits prior to
2467 * disabling the pipe.
2468 */
2469 if (mode == DRM_MODE_DPMS_ON)
2470 intel_update_watermarks(dev);
2471 else
2472 intel_crtc_update_cursor(crtc);
2473
2474 dev_priv->display.dpms(crtc, mode);
2475
2476 if (mode == DRM_MODE_DPMS_ON)
2477 intel_crtc_update_cursor(crtc);
2478 else {
2479 /* XXX Note that this is not a complete solution, but a hack
2480 * to avoid the most frequently hit hang.
2481 */
2482 intel_clear_scanline_wait(dev);
2483
2484 intel_update_watermarks(dev);
2485 }
2486
2487 if (!dev->primary->master)
2488 return;
2489
2490 master_priv = dev->primary->master->driver_priv;
2491 if (!master_priv->sarea_priv)
2492 return;
2493
2494 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2495
2496 switch (pipe) {
2497 case 0:
2498 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2499 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2500 break;
2501 case 1:
2502 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2503 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2504 break;
2505 default:
2506 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2507 break;
2508 }
2509 }
2510
2511 /* Prepare for a mode set.
2512 *
2513 * Note we could be a lot smarter here. We need to figure out which outputs
2514 * will be enabled, which disabled (in short, how the config will changes)
2515 * and perform the minimum necessary steps to accomplish that, e.g. updating
2516 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
2517 * panel fitting is in the proper state, etc.
2518 */
2519 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
2520 {
2521 struct drm_device *dev = crtc->dev;
2522 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2523
2524 intel_crtc->cursor_on = false;
2525 intel_crtc_update_cursor(crtc);
2526
2527 i9xx_crtc_disable(crtc);
2528 intel_clear_scanline_wait(dev);
2529 }
2530
2531 static void i9xx_crtc_commit(struct drm_crtc *crtc)
2532 {
2533 struct drm_device *dev = crtc->dev;
2534 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2535
2536 intel_update_watermarks(dev);
2537 i9xx_crtc_enable(crtc);
2538
2539 intel_crtc->cursor_on = true;
2540 intel_crtc_update_cursor(crtc);
2541 }
2542
2543 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
2544 {
2545 struct drm_device *dev = crtc->dev;
2546 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2547
2548 intel_crtc->cursor_on = false;
2549 intel_crtc_update_cursor(crtc);
2550
2551 ironlake_crtc_disable(crtc);
2552 intel_clear_scanline_wait(dev);
2553 }
2554
2555 static void ironlake_crtc_commit(struct drm_crtc *crtc)
2556 {
2557 struct drm_device *dev = crtc->dev;
2558 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2559
2560 intel_update_watermarks(dev);
2561 ironlake_crtc_enable(crtc);
2562
2563 intel_crtc->cursor_on = true;
2564 intel_crtc_update_cursor(crtc);
2565 }
2566
2567 void intel_encoder_prepare (struct drm_encoder *encoder)
2568 {
2569 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2570 /* lvds has its own version of prepare see intel_lvds_prepare */
2571 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2572 }
2573
2574 void intel_encoder_commit (struct drm_encoder *encoder)
2575 {
2576 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2577 /* lvds has its own version of commit see intel_lvds_commit */
2578 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2579 }
2580
2581 void intel_encoder_destroy(struct drm_encoder *encoder)
2582 {
2583 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2584
2585 if (intel_encoder->ddc_bus)
2586 intel_i2c_destroy(intel_encoder->ddc_bus);
2587
2588 if (intel_encoder->i2c_bus)
2589 intel_i2c_destroy(intel_encoder->i2c_bus);
2590
2591 drm_encoder_cleanup(encoder);
2592 kfree(intel_encoder);
2593 }
2594
2595 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2596 struct drm_display_mode *mode,
2597 struct drm_display_mode *adjusted_mode)
2598 {
2599 struct drm_device *dev = crtc->dev;
2600 if (HAS_PCH_SPLIT(dev)) {
2601 /* FDI link clock is fixed at 2.7G */
2602 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2603 return false;
2604 }
2605 return true;
2606 }
2607
2608 static int i945_get_display_clock_speed(struct drm_device *dev)
2609 {
2610 return 400000;
2611 }
2612
2613 static int i915_get_display_clock_speed(struct drm_device *dev)
2614 {
2615 return 333000;
2616 }
2617
2618 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2619 {
2620 return 200000;
2621 }
2622
2623 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2624 {
2625 u16 gcfgc = 0;
2626
2627 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2628
2629 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2630 return 133000;
2631 else {
2632 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2633 case GC_DISPLAY_CLOCK_333_MHZ:
2634 return 333000;
2635 default:
2636 case GC_DISPLAY_CLOCK_190_200_MHZ:
2637 return 190000;
2638 }
2639 }
2640 }
2641
2642 static int i865_get_display_clock_speed(struct drm_device *dev)
2643 {
2644 return 266000;
2645 }
2646
2647 static int i855_get_display_clock_speed(struct drm_device *dev)
2648 {
2649 u16 hpllcc = 0;
2650 /* Assume that the hardware is in the high speed state. This
2651 * should be the default.
2652 */
2653 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2654 case GC_CLOCK_133_200:
2655 case GC_CLOCK_100_200:
2656 return 200000;
2657 case GC_CLOCK_166_250:
2658 return 250000;
2659 case GC_CLOCK_100_133:
2660 return 133000;
2661 }
2662
2663 /* Shouldn't happen */
2664 return 0;
2665 }
2666
2667 static int i830_get_display_clock_speed(struct drm_device *dev)
2668 {
2669 return 133000;
2670 }
2671
2672 /**
2673 * Return the pipe currently connected to the panel fitter,
2674 * or -1 if the panel fitter is not present or not in use
2675 */
2676 int intel_panel_fitter_pipe (struct drm_device *dev)
2677 {
2678 struct drm_i915_private *dev_priv = dev->dev_private;
2679 u32 pfit_control;
2680
2681 /* i830 doesn't have a panel fitter */
2682 if (IS_I830(dev))
2683 return -1;
2684
2685 pfit_control = I915_READ(PFIT_CONTROL);
2686
2687 /* See if the panel fitter is in use */
2688 if ((pfit_control & PFIT_ENABLE) == 0)
2689 return -1;
2690
2691 /* 965 can place panel fitter on either pipe */
2692 if (IS_I965G(dev))
2693 return (pfit_control >> 29) & 0x3;
2694
2695 /* older chips can only use pipe 1 */
2696 return 1;
2697 }
2698
2699 struct fdi_m_n {
2700 u32 tu;
2701 u32 gmch_m;
2702 u32 gmch_n;
2703 u32 link_m;
2704 u32 link_n;
2705 };
2706
2707 static void
2708 fdi_reduce_ratio(u32 *num, u32 *den)
2709 {
2710 while (*num > 0xffffff || *den > 0xffffff) {
2711 *num >>= 1;
2712 *den >>= 1;
2713 }
2714 }
2715
2716 #define DATA_N 0x800000
2717 #define LINK_N 0x80000
2718
2719 static void
2720 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2721 int link_clock, struct fdi_m_n *m_n)
2722 {
2723 u64 temp;
2724
2725 m_n->tu = 64; /* default size */
2726
2727 temp = (u64) DATA_N * pixel_clock;
2728 temp = div_u64(temp, link_clock);
2729 m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2730 m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2731 m_n->gmch_n = DATA_N;
2732 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2733
2734 temp = (u64) LINK_N * pixel_clock;
2735 m_n->link_m = div_u64(temp, link_clock);
2736 m_n->link_n = LINK_N;
2737 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2738 }
2739
2740
2741 struct intel_watermark_params {
2742 unsigned long fifo_size;
2743 unsigned long max_wm;
2744 unsigned long default_wm;
2745 unsigned long guard_size;
2746 unsigned long cacheline_size;
2747 };
2748
2749 /* Pineview has different values for various configs */
2750 static struct intel_watermark_params pineview_display_wm = {
2751 PINEVIEW_DISPLAY_FIFO,
2752 PINEVIEW_MAX_WM,
2753 PINEVIEW_DFT_WM,
2754 PINEVIEW_GUARD_WM,
2755 PINEVIEW_FIFO_LINE_SIZE
2756 };
2757 static struct intel_watermark_params pineview_display_hplloff_wm = {
2758 PINEVIEW_DISPLAY_FIFO,
2759 PINEVIEW_MAX_WM,
2760 PINEVIEW_DFT_HPLLOFF_WM,
2761 PINEVIEW_GUARD_WM,
2762 PINEVIEW_FIFO_LINE_SIZE
2763 };
2764 static struct intel_watermark_params pineview_cursor_wm = {
2765 PINEVIEW_CURSOR_FIFO,
2766 PINEVIEW_CURSOR_MAX_WM,
2767 PINEVIEW_CURSOR_DFT_WM,
2768 PINEVIEW_CURSOR_GUARD_WM,
2769 PINEVIEW_FIFO_LINE_SIZE,
2770 };
2771 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2772 PINEVIEW_CURSOR_FIFO,
2773 PINEVIEW_CURSOR_MAX_WM,
2774 PINEVIEW_CURSOR_DFT_WM,
2775 PINEVIEW_CURSOR_GUARD_WM,
2776 PINEVIEW_FIFO_LINE_SIZE
2777 };
2778 static struct intel_watermark_params g4x_wm_info = {
2779 G4X_FIFO_SIZE,
2780 G4X_MAX_WM,
2781 G4X_MAX_WM,
2782 2,
2783 G4X_FIFO_LINE_SIZE,
2784 };
2785 static struct intel_watermark_params g4x_cursor_wm_info = {
2786 I965_CURSOR_FIFO,
2787 I965_CURSOR_MAX_WM,
2788 I965_CURSOR_DFT_WM,
2789 2,
2790 G4X_FIFO_LINE_SIZE,
2791 };
2792 static struct intel_watermark_params i965_cursor_wm_info = {
2793 I965_CURSOR_FIFO,
2794 I965_CURSOR_MAX_WM,
2795 I965_CURSOR_DFT_WM,
2796 2,
2797 I915_FIFO_LINE_SIZE,
2798 };
2799 static struct intel_watermark_params i945_wm_info = {
2800 I945_FIFO_SIZE,
2801 I915_MAX_WM,
2802 1,
2803 2,
2804 I915_FIFO_LINE_SIZE
2805 };
2806 static struct intel_watermark_params i915_wm_info = {
2807 I915_FIFO_SIZE,
2808 I915_MAX_WM,
2809 1,
2810 2,
2811 I915_FIFO_LINE_SIZE
2812 };
2813 static struct intel_watermark_params i855_wm_info = {
2814 I855GM_FIFO_SIZE,
2815 I915_MAX_WM,
2816 1,
2817 2,
2818 I830_FIFO_LINE_SIZE
2819 };
2820 static struct intel_watermark_params i830_wm_info = {
2821 I830_FIFO_SIZE,
2822 I915_MAX_WM,
2823 1,
2824 2,
2825 I830_FIFO_LINE_SIZE
2826 };
2827
2828 static struct intel_watermark_params ironlake_display_wm_info = {
2829 ILK_DISPLAY_FIFO,
2830 ILK_DISPLAY_MAXWM,
2831 ILK_DISPLAY_DFTWM,
2832 2,
2833 ILK_FIFO_LINE_SIZE
2834 };
2835
2836 static struct intel_watermark_params ironlake_cursor_wm_info = {
2837 ILK_CURSOR_FIFO,
2838 ILK_CURSOR_MAXWM,
2839 ILK_CURSOR_DFTWM,
2840 2,
2841 ILK_FIFO_LINE_SIZE
2842 };
2843
2844 static struct intel_watermark_params ironlake_display_srwm_info = {
2845 ILK_DISPLAY_SR_FIFO,
2846 ILK_DISPLAY_MAX_SRWM,
2847 ILK_DISPLAY_DFT_SRWM,
2848 2,
2849 ILK_FIFO_LINE_SIZE
2850 };
2851
2852 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2853 ILK_CURSOR_SR_FIFO,
2854 ILK_CURSOR_MAX_SRWM,
2855 ILK_CURSOR_DFT_SRWM,
2856 2,
2857 ILK_FIFO_LINE_SIZE
2858 };
2859
2860 /**
2861 * intel_calculate_wm - calculate watermark level
2862 * @clock_in_khz: pixel clock
2863 * @wm: chip FIFO params
2864 * @pixel_size: display pixel size
2865 * @latency_ns: memory latency for the platform
2866 *
2867 * Calculate the watermark level (the level at which the display plane will
2868 * start fetching from memory again). Each chip has a different display
2869 * FIFO size and allocation, so the caller needs to figure that out and pass
2870 * in the correct intel_watermark_params structure.
2871 *
2872 * As the pixel clock runs, the FIFO will be drained at a rate that depends
2873 * on the pixel size. When it reaches the watermark level, it'll start
2874 * fetching FIFO line sized based chunks from memory until the FIFO fills
2875 * past the watermark point. If the FIFO drains completely, a FIFO underrun
2876 * will occur, and a display engine hang could result.
2877 */
2878 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2879 struct intel_watermark_params *wm,
2880 int pixel_size,
2881 unsigned long latency_ns)
2882 {
2883 long entries_required, wm_size;
2884
2885 /*
2886 * Note: we need to make sure we don't overflow for various clock &
2887 * latency values.
2888 * clocks go from a few thousand to several hundred thousand.
2889 * latency is usually a few thousand
2890 */
2891 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2892 1000;
2893 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
2894
2895 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2896
2897 wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2898
2899 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2900
2901 /* Don't promote wm_size to unsigned... */
2902 if (wm_size > (long)wm->max_wm)
2903 wm_size = wm->max_wm;
2904 if (wm_size <= 0)
2905 wm_size = wm->default_wm;
2906 return wm_size;
2907 }
2908
2909 struct cxsr_latency {
2910 int is_desktop;
2911 int is_ddr3;
2912 unsigned long fsb_freq;
2913 unsigned long mem_freq;
2914 unsigned long display_sr;
2915 unsigned long display_hpll_disable;
2916 unsigned long cursor_sr;
2917 unsigned long cursor_hpll_disable;
2918 };
2919
2920 static const struct cxsr_latency cxsr_latency_table[] = {
2921 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
2922 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
2923 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
2924 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
2925 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
2926
2927 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
2928 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
2929 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
2930 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
2931 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
2932
2933 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
2934 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
2935 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
2936 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
2937 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
2938
2939 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
2940 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
2941 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
2942 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
2943 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
2944
2945 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
2946 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
2947 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
2948 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
2949 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
2950
2951 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
2952 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
2953 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
2954 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
2955 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
2956 };
2957
2958 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
2959 int is_ddr3,
2960 int fsb,
2961 int mem)
2962 {
2963 const struct cxsr_latency *latency;
2964 int i;
2965
2966 if (fsb == 0 || mem == 0)
2967 return NULL;
2968
2969 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2970 latency = &cxsr_latency_table[i];
2971 if (is_desktop == latency->is_desktop &&
2972 is_ddr3 == latency->is_ddr3 &&
2973 fsb == latency->fsb_freq && mem == latency->mem_freq)
2974 return latency;
2975 }
2976
2977 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2978
2979 return NULL;
2980 }
2981
2982 static void pineview_disable_cxsr(struct drm_device *dev)
2983 {
2984 struct drm_i915_private *dev_priv = dev->dev_private;
2985
2986 /* deactivate cxsr */
2987 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
2988 }
2989
2990 /*
2991 * Latency for FIFO fetches is dependent on several factors:
2992 * - memory configuration (speed, channels)
2993 * - chipset
2994 * - current MCH state
2995 * It can be fairly high in some situations, so here we assume a fairly
2996 * pessimal value. It's a tradeoff between extra memory fetches (if we
2997 * set this value too high, the FIFO will fetch frequently to stay full)
2998 * and power consumption (set it too low to save power and we might see
2999 * FIFO underruns and display "flicker").
3000 *
3001 * A value of 5us seems to be a good balance; safe for very low end
3002 * platforms but not overly aggressive on lower latency configs.
3003 */
3004 static const int latency_ns = 5000;
3005
3006 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3007 {
3008 struct drm_i915_private *dev_priv = dev->dev_private;
3009 uint32_t dsparb = I915_READ(DSPARB);
3010 int size;
3011
3012 size = dsparb & 0x7f;
3013 if (plane)
3014 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3015
3016 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3017 plane ? "B" : "A", size);
3018
3019 return size;
3020 }
3021
3022 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3023 {
3024 struct drm_i915_private *dev_priv = dev->dev_private;
3025 uint32_t dsparb = I915_READ(DSPARB);
3026 int size;
3027
3028 size = dsparb & 0x1ff;
3029 if (plane)
3030 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3031 size >>= 1; /* Convert to cachelines */
3032
3033 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3034 plane ? "B" : "A", size);
3035
3036 return size;
3037 }
3038
3039 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3040 {
3041 struct drm_i915_private *dev_priv = dev->dev_private;
3042 uint32_t dsparb = I915_READ(DSPARB);
3043 int size;
3044
3045 size = dsparb & 0x7f;
3046 size >>= 2; /* Convert to cachelines */
3047
3048 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3049 plane ? "B" : "A",
3050 size);
3051
3052 return size;
3053 }
3054
3055 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3056 {
3057 struct drm_i915_private *dev_priv = dev->dev_private;
3058 uint32_t dsparb = I915_READ(DSPARB);
3059 int size;
3060
3061 size = dsparb & 0x7f;
3062 size >>= 1; /* Convert to cachelines */
3063
3064 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3065 plane ? "B" : "A", size);
3066
3067 return size;
3068 }
3069
3070 static void pineview_update_wm(struct drm_device *dev, int planea_clock,
3071 int planeb_clock, int sr_hdisplay, int unused,
3072 int pixel_size)
3073 {
3074 struct drm_i915_private *dev_priv = dev->dev_private;
3075 const struct cxsr_latency *latency;
3076 u32 reg;
3077 unsigned long wm;
3078 int sr_clock;
3079
3080 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3081 dev_priv->fsb_freq, dev_priv->mem_freq);
3082 if (!latency) {
3083 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3084 pineview_disable_cxsr(dev);
3085 return;
3086 }
3087
3088 if (!planea_clock || !planeb_clock) {
3089 sr_clock = planea_clock ? planea_clock : planeb_clock;
3090
3091 /* Display SR */
3092 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
3093 pixel_size, latency->display_sr);
3094 reg = I915_READ(DSPFW1);
3095 reg &= ~DSPFW_SR_MASK;
3096 reg |= wm << DSPFW_SR_SHIFT;
3097 I915_WRITE(DSPFW1, reg);
3098 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3099
3100 /* cursor SR */
3101 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
3102 pixel_size, latency->cursor_sr);
3103 reg = I915_READ(DSPFW3);
3104 reg &= ~DSPFW_CURSOR_SR_MASK;
3105 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3106 I915_WRITE(DSPFW3, reg);
3107
3108 /* Display HPLL off SR */
3109 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
3110 pixel_size, latency->display_hpll_disable);
3111 reg = I915_READ(DSPFW3);
3112 reg &= ~DSPFW_HPLL_SR_MASK;
3113 reg |= wm & DSPFW_HPLL_SR_MASK;
3114 I915_WRITE(DSPFW3, reg);
3115
3116 /* cursor HPLL off SR */
3117 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
3118 pixel_size, latency->cursor_hpll_disable);
3119 reg = I915_READ(DSPFW3);
3120 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3121 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3122 I915_WRITE(DSPFW3, reg);
3123 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3124
3125 /* activate cxsr */
3126 I915_WRITE(DSPFW3,
3127 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3128 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3129 } else {
3130 pineview_disable_cxsr(dev);
3131 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3132 }
3133 }
3134
3135 static void g4x_update_wm(struct drm_device *dev, int planea_clock,
3136 int planeb_clock, int sr_hdisplay, int sr_htotal,
3137 int pixel_size)
3138 {
3139 struct drm_i915_private *dev_priv = dev->dev_private;
3140 int total_size, cacheline_size;
3141 int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
3142 struct intel_watermark_params planea_params, planeb_params;
3143 unsigned long line_time_us;
3144 int sr_clock, sr_entries = 0, entries_required;
3145
3146 /* Create copies of the base settings for each pipe */
3147 planea_params = planeb_params = g4x_wm_info;
3148
3149 /* Grab a couple of global values before we overwrite them */
3150 total_size = planea_params.fifo_size;
3151 cacheline_size = planea_params.cacheline_size;
3152
3153 /*
3154 * Note: we need to make sure we don't overflow for various clock &
3155 * latency values.
3156 * clocks go from a few thousand to several hundred thousand.
3157 * latency is usually a few thousand
3158 */
3159 entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3160 1000;
3161 entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3162 planea_wm = entries_required + planea_params.guard_size;
3163
3164 entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3165 1000;
3166 entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3167 planeb_wm = entries_required + planeb_params.guard_size;
3168
3169 cursora_wm = cursorb_wm = 16;
3170 cursor_sr = 32;
3171
3172 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3173
3174 /* Calc sr entries for one plane configs */
3175 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3176 /* self-refresh has much higher latency */
3177 static const int sr_latency_ns = 12000;
3178
3179 sr_clock = planea_clock ? planea_clock : planeb_clock;
3180 line_time_us = ((sr_htotal * 1000) / sr_clock);
3181
3182 /* Use ns/us then divide to preserve precision */
3183 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3184 pixel_size * sr_hdisplay;
3185 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3186
3187 entries_required = (((sr_latency_ns / line_time_us) +
3188 1000) / 1000) * pixel_size * 64;
3189 entries_required = DIV_ROUND_UP(entries_required,
3190 g4x_cursor_wm_info.cacheline_size);
3191 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3192
3193 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3194 cursor_sr = g4x_cursor_wm_info.max_wm;
3195 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3196 "cursor %d\n", sr_entries, cursor_sr);
3197
3198 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3199 } else {
3200 /* Turn off self refresh if both pipes are enabled */
3201 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3202 & ~FW_BLC_SELF_EN);
3203 }
3204
3205 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3206 planea_wm, planeb_wm, sr_entries);
3207
3208 planea_wm &= 0x3f;
3209 planeb_wm &= 0x3f;
3210
3211 I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3212 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3213 (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3214 I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3215 (cursora_wm << DSPFW_CURSORA_SHIFT));
3216 /* HPLL off in SR has some issues on G4x... disable it */
3217 I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3218 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3219 }
3220
3221 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3222 int planeb_clock, int sr_hdisplay, int sr_htotal,
3223 int pixel_size)
3224 {
3225 struct drm_i915_private *dev_priv = dev->dev_private;
3226 unsigned long line_time_us;
3227 int sr_clock, sr_entries, srwm = 1;
3228 int cursor_sr = 16;
3229
3230 /* Calc sr entries for one plane configs */
3231 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3232 /* self-refresh has much higher latency */
3233 static const int sr_latency_ns = 12000;
3234
3235 sr_clock = planea_clock ? planea_clock : planeb_clock;
3236 line_time_us = ((sr_htotal * 1000) / sr_clock);
3237
3238 /* Use ns/us then divide to preserve precision */
3239 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3240 pixel_size * sr_hdisplay;
3241 sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
3242 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3243 srwm = I965_FIFO_SIZE - sr_entries;
3244 if (srwm < 0)
3245 srwm = 1;
3246 srwm &= 0x1ff;
3247
3248 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3249 pixel_size * 64;
3250 sr_entries = DIV_ROUND_UP(sr_entries,
3251 i965_cursor_wm_info.cacheline_size);
3252 cursor_sr = i965_cursor_wm_info.fifo_size -
3253 (sr_entries + i965_cursor_wm_info.guard_size);
3254
3255 if (cursor_sr > i965_cursor_wm_info.max_wm)
3256 cursor_sr = i965_cursor_wm_info.max_wm;
3257
3258 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3259 "cursor %d\n", srwm, cursor_sr);
3260
3261 if (IS_I965GM(dev))
3262 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3263 } else {
3264 /* Turn off self refresh if both pipes are enabled */
3265 if (IS_I965GM(dev))
3266 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3267 & ~FW_BLC_SELF_EN);
3268 }
3269
3270 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3271 srwm);
3272
3273 /* 965 has limitations... */
3274 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3275 (8 << 0));
3276 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3277 /* update cursor SR watermark */
3278 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3279 }
3280
3281 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3282 int planeb_clock, int sr_hdisplay, int sr_htotal,
3283 int pixel_size)
3284 {
3285 struct drm_i915_private *dev_priv = dev->dev_private;
3286 uint32_t fwater_lo;
3287 uint32_t fwater_hi;
3288 int total_size, cacheline_size, cwm, srwm = 1;
3289 int planea_wm, planeb_wm;
3290 struct intel_watermark_params planea_params, planeb_params;
3291 unsigned long line_time_us;
3292 int sr_clock, sr_entries = 0;
3293
3294 /* Create copies of the base settings for each pipe */
3295 if (IS_I965GM(dev) || IS_I945GM(dev))
3296 planea_params = planeb_params = i945_wm_info;
3297 else if (IS_I9XX(dev))
3298 planea_params = planeb_params = i915_wm_info;
3299 else
3300 planea_params = planeb_params = i855_wm_info;
3301
3302 /* Grab a couple of global values before we overwrite them */
3303 total_size = planea_params.fifo_size;
3304 cacheline_size = planea_params.cacheline_size;
3305
3306 /* Update per-plane FIFO sizes */
3307 planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3308 planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3309
3310 planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3311 pixel_size, latency_ns);
3312 planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3313 pixel_size, latency_ns);
3314 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3315
3316 /*
3317 * Overlay gets an aggressive default since video jitter is bad.
3318 */
3319 cwm = 2;
3320
3321 /* Calc sr entries for one plane configs */
3322 if (HAS_FW_BLC(dev) && sr_hdisplay &&
3323 (!planea_clock || !planeb_clock)) {
3324 /* self-refresh has much higher latency */
3325 static const int sr_latency_ns = 6000;
3326
3327 sr_clock = planea_clock ? planea_clock : planeb_clock;
3328 line_time_us = ((sr_htotal * 1000) / sr_clock);
3329
3330 /* Use ns/us then divide to preserve precision */
3331 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3332 pixel_size * sr_hdisplay;
3333 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3334 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3335 srwm = total_size - sr_entries;
3336 if (srwm < 0)
3337 srwm = 1;
3338
3339 if (IS_I945G(dev) || IS_I945GM(dev))
3340 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3341 else if (IS_I915GM(dev)) {
3342 /* 915M has a smaller SRWM field */
3343 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3344 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3345 }
3346 } else {
3347 /* Turn off self refresh if both pipes are enabled */
3348 if (IS_I945G(dev) || IS_I945GM(dev)) {
3349 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3350 & ~FW_BLC_SELF_EN);
3351 } else if (IS_I915GM(dev)) {
3352 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3353 }
3354 }
3355
3356 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3357 planea_wm, planeb_wm, cwm, srwm);
3358
3359 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3360 fwater_hi = (cwm & 0x1f);
3361
3362 /* Set request length to 8 cachelines per fetch */
3363 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3364 fwater_hi = fwater_hi | (1 << 8);
3365
3366 I915_WRITE(FW_BLC, fwater_lo);
3367 I915_WRITE(FW_BLC2, fwater_hi);
3368 }
3369
3370 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3371 int unused2, int unused3, int pixel_size)
3372 {
3373 struct drm_i915_private *dev_priv = dev->dev_private;
3374 uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3375 int planea_wm;
3376
3377 i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3378
3379 planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3380 pixel_size, latency_ns);
3381 fwater_lo |= (3<<8) | planea_wm;
3382
3383 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3384
3385 I915_WRITE(FW_BLC, fwater_lo);
3386 }
3387
3388 #define ILK_LP0_PLANE_LATENCY 700
3389 #define ILK_LP0_CURSOR_LATENCY 1300
3390
3391 static void ironlake_update_wm(struct drm_device *dev, int planea_clock,
3392 int planeb_clock, int sr_hdisplay, int sr_htotal,
3393 int pixel_size)
3394 {
3395 struct drm_i915_private *dev_priv = dev->dev_private;
3396 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3397 int sr_wm, cursor_wm;
3398 unsigned long line_time_us;
3399 int sr_clock, entries_required;
3400 u32 reg_value;
3401 int line_count;
3402 int planea_htotal = 0, planeb_htotal = 0;
3403 struct drm_crtc *crtc;
3404
3405 /* Need htotal for all active display plane */
3406 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3407 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3408 if (intel_crtc->dpms_mode == DRM_MODE_DPMS_ON) {
3409 if (intel_crtc->plane == 0)
3410 planea_htotal = crtc->mode.htotal;
3411 else
3412 planeb_htotal = crtc->mode.htotal;
3413 }
3414 }
3415
3416 /* Calculate and update the watermark for plane A */
3417 if (planea_clock) {
3418 entries_required = ((planea_clock / 1000) * pixel_size *
3419 ILK_LP0_PLANE_LATENCY) / 1000;
3420 entries_required = DIV_ROUND_UP(entries_required,
3421 ironlake_display_wm_info.cacheline_size);
3422 planea_wm = entries_required +
3423 ironlake_display_wm_info.guard_size;
3424
3425 if (planea_wm > (int)ironlake_display_wm_info.max_wm)
3426 planea_wm = ironlake_display_wm_info.max_wm;
3427
3428 /* Use the large buffer method to calculate cursor watermark */
3429 line_time_us = (planea_htotal * 1000) / planea_clock;
3430
3431 /* Use ns/us then divide to preserve precision */
3432 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3433
3434 /* calculate the cursor watermark for cursor A */
3435 entries_required = line_count * 64 * pixel_size;
3436 entries_required = DIV_ROUND_UP(entries_required,
3437 ironlake_cursor_wm_info.cacheline_size);
3438 cursora_wm = entries_required + ironlake_cursor_wm_info.guard_size;
3439 if (cursora_wm > ironlake_cursor_wm_info.max_wm)
3440 cursora_wm = ironlake_cursor_wm_info.max_wm;
3441
3442 reg_value = I915_READ(WM0_PIPEA_ILK);
3443 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3444 reg_value |= (planea_wm << WM0_PIPE_PLANE_SHIFT) |
3445 (cursora_wm & WM0_PIPE_CURSOR_MASK);
3446 I915_WRITE(WM0_PIPEA_ILK, reg_value);
3447 DRM_DEBUG_KMS("FIFO watermarks For pipe A - plane %d, "
3448 "cursor: %d\n", planea_wm, cursora_wm);
3449 }
3450 /* Calculate and update the watermark for plane B */
3451 if (planeb_clock) {
3452 entries_required = ((planeb_clock / 1000) * pixel_size *
3453 ILK_LP0_PLANE_LATENCY) / 1000;
3454 entries_required = DIV_ROUND_UP(entries_required,
3455 ironlake_display_wm_info.cacheline_size);
3456 planeb_wm = entries_required +
3457 ironlake_display_wm_info.guard_size;
3458
3459 if (planeb_wm > (int)ironlake_display_wm_info.max_wm)
3460 planeb_wm = ironlake_display_wm_info.max_wm;
3461
3462 /* Use the large buffer method to calculate cursor watermark */
3463 line_time_us = (planeb_htotal * 1000) / planeb_clock;
3464
3465 /* Use ns/us then divide to preserve precision */
3466 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3467
3468 /* calculate the cursor watermark for cursor B */
3469 entries_required = line_count * 64 * pixel_size;
3470 entries_required = DIV_ROUND_UP(entries_required,
3471 ironlake_cursor_wm_info.cacheline_size);
3472 cursorb_wm = entries_required + ironlake_cursor_wm_info.guard_size;
3473 if (cursorb_wm > ironlake_cursor_wm_info.max_wm)
3474 cursorb_wm = ironlake_cursor_wm_info.max_wm;
3475
3476 reg_value = I915_READ(WM0_PIPEB_ILK);
3477 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3478 reg_value |= (planeb_wm << WM0_PIPE_PLANE_SHIFT) |
3479 (cursorb_wm & WM0_PIPE_CURSOR_MASK);
3480 I915_WRITE(WM0_PIPEB_ILK, reg_value);
3481 DRM_DEBUG_KMS("FIFO watermarks For pipe B - plane %d, "
3482 "cursor: %d\n", planeb_wm, cursorb_wm);
3483 }
3484
3485 /*
3486 * Calculate and update the self-refresh watermark only when one
3487 * display plane is used.
3488 */
3489 if (!planea_clock || !planeb_clock) {
3490
3491 /* Read the self-refresh latency. The unit is 0.5us */
3492 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3493
3494 sr_clock = planea_clock ? planea_clock : planeb_clock;
3495 line_time_us = ((sr_htotal * 1000) / sr_clock);
3496
3497 /* Use ns/us then divide to preserve precision */
3498 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3499 / 1000;
3500
3501 /* calculate the self-refresh watermark for display plane */
3502 entries_required = line_count * sr_hdisplay * pixel_size;
3503 entries_required = DIV_ROUND_UP(entries_required,
3504 ironlake_display_srwm_info.cacheline_size);
3505 sr_wm = entries_required +
3506 ironlake_display_srwm_info.guard_size;
3507
3508 /* calculate the self-refresh watermark for display cursor */
3509 entries_required = line_count * pixel_size * 64;
3510 entries_required = DIV_ROUND_UP(entries_required,
3511 ironlake_cursor_srwm_info.cacheline_size);
3512 cursor_wm = entries_required +
3513 ironlake_cursor_srwm_info.guard_size;
3514
3515 /* configure watermark and enable self-refresh */
3516 reg_value = I915_READ(WM1_LP_ILK);
3517 reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK |
3518 WM1_LP_CURSOR_MASK);
3519 reg_value |= (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3520 (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm;
3521
3522 I915_WRITE(WM1_LP_ILK, reg_value);
3523 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3524 "cursor %d\n", sr_wm, cursor_wm);
3525
3526 } else {
3527 /* Turn off self refresh if both pipes are enabled */
3528 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
3529 }
3530 }
3531 /**
3532 * intel_update_watermarks - update FIFO watermark values based on current modes
3533 *
3534 * Calculate watermark values for the various WM regs based on current mode
3535 * and plane configuration.
3536 *
3537 * There are several cases to deal with here:
3538 * - normal (i.e. non-self-refresh)
3539 * - self-refresh (SR) mode
3540 * - lines are large relative to FIFO size (buffer can hold up to 2)
3541 * - lines are small relative to FIFO size (buffer can hold more than 2
3542 * lines), so need to account for TLB latency
3543 *
3544 * The normal calculation is:
3545 * watermark = dotclock * bytes per pixel * latency
3546 * where latency is platform & configuration dependent (we assume pessimal
3547 * values here).
3548 *
3549 * The SR calculation is:
3550 * watermark = (trunc(latency/line time)+1) * surface width *
3551 * bytes per pixel
3552 * where
3553 * line time = htotal / dotclock
3554 * surface width = hdisplay for normal plane and 64 for cursor
3555 * and latency is assumed to be high, as above.
3556 *
3557 * The final value programmed to the register should always be rounded up,
3558 * and include an extra 2 entries to account for clock crossings.
3559 *
3560 * We don't use the sprite, so we can ignore that. And on Crestline we have
3561 * to set the non-SR watermarks to 8.
3562 */
3563 static void intel_update_watermarks(struct drm_device *dev)
3564 {
3565 struct drm_i915_private *dev_priv = dev->dev_private;
3566 struct drm_crtc *crtc;
3567 int sr_hdisplay = 0;
3568 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3569 int enabled = 0, pixel_size = 0;
3570 int sr_htotal = 0;
3571
3572 if (!dev_priv->display.update_wm)
3573 return;
3574
3575 /* Get the clock config from both planes */
3576 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3577 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3578 if (intel_crtc->dpms_mode == DRM_MODE_DPMS_ON) {
3579 enabled++;
3580 if (intel_crtc->plane == 0) {
3581 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3582 intel_crtc->pipe, crtc->mode.clock);
3583 planea_clock = crtc->mode.clock;
3584 } else {
3585 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3586 intel_crtc->pipe, crtc->mode.clock);
3587 planeb_clock = crtc->mode.clock;
3588 }
3589 sr_hdisplay = crtc->mode.hdisplay;
3590 sr_clock = crtc->mode.clock;
3591 sr_htotal = crtc->mode.htotal;
3592 if (crtc->fb)
3593 pixel_size = crtc->fb->bits_per_pixel / 8;
3594 else
3595 pixel_size = 4; /* by default */
3596 }
3597 }
3598
3599 if (enabled <= 0)
3600 return;
3601
3602 dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3603 sr_hdisplay, sr_htotal, pixel_size);
3604 }
3605
3606 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3607 struct drm_display_mode *mode,
3608 struct drm_display_mode *adjusted_mode,
3609 int x, int y,
3610 struct drm_framebuffer *old_fb)
3611 {
3612 struct drm_device *dev = crtc->dev;
3613 struct drm_i915_private *dev_priv = dev->dev_private;
3614 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3615 int pipe = intel_crtc->pipe;
3616 int plane = intel_crtc->plane;
3617 int fp_reg = (pipe == 0) ? FPA0 : FPB0;
3618 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3619 int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
3620 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
3621 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
3622 int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
3623 int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
3624 int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
3625 int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
3626 int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
3627 int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
3628 int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
3629 int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
3630 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
3631 int refclk, num_connectors = 0;
3632 intel_clock_t clock, reduced_clock;
3633 u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
3634 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3635 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3636 struct intel_encoder *has_edp_encoder = NULL;
3637 struct drm_mode_config *mode_config = &dev->mode_config;
3638 struct drm_encoder *encoder;
3639 const intel_limit_t *limit;
3640 int ret;
3641 struct fdi_m_n m_n = {0};
3642 int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
3643 int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
3644 int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
3645 int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
3646 int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
3647 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
3648 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
3649 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
3650 int trans_dpll_sel = (pipe == 0) ? 0 : 1;
3651 int lvds_reg = LVDS;
3652 u32 temp;
3653 int target_clock;
3654
3655 drm_vblank_pre_modeset(dev, pipe);
3656
3657 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
3658 struct intel_encoder *intel_encoder;
3659
3660 if (encoder->crtc != crtc)
3661 continue;
3662
3663 intel_encoder = to_intel_encoder(encoder);
3664 switch (intel_encoder->type) {
3665 case INTEL_OUTPUT_LVDS:
3666 is_lvds = true;
3667 break;
3668 case INTEL_OUTPUT_SDVO:
3669 case INTEL_OUTPUT_HDMI:
3670 is_sdvo = true;
3671 if (intel_encoder->needs_tv_clock)
3672 is_tv = true;
3673 break;
3674 case INTEL_OUTPUT_DVO:
3675 is_dvo = true;
3676 break;
3677 case INTEL_OUTPUT_TVOUT:
3678 is_tv = true;
3679 break;
3680 case INTEL_OUTPUT_ANALOG:
3681 is_crt = true;
3682 break;
3683 case INTEL_OUTPUT_DISPLAYPORT:
3684 is_dp = true;
3685 break;
3686 case INTEL_OUTPUT_EDP:
3687 has_edp_encoder = intel_encoder;
3688 break;
3689 }
3690
3691 num_connectors++;
3692 }
3693
3694 if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3695 refclk = dev_priv->lvds_ssc_freq * 1000;
3696 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3697 refclk / 1000);
3698 } else if (IS_I9XX(dev)) {
3699 refclk = 96000;
3700 if (HAS_PCH_SPLIT(dev))
3701 refclk = 120000; /* 120Mhz refclk */
3702 } else {
3703 refclk = 48000;
3704 }
3705
3706
3707 /*
3708 * Returns a set of divisors for the desired target clock with the given
3709 * refclk, or FALSE. The returned values represent the clock equation:
3710 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3711 */
3712 limit = intel_limit(crtc);
3713 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3714 if (!ok) {
3715 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3716 drm_vblank_post_modeset(dev, pipe);
3717 return -EINVAL;
3718 }
3719
3720 /* Ensure that the cursor is valid for the new mode before changing... */
3721 intel_crtc_update_cursor(crtc);
3722
3723 if (is_lvds && dev_priv->lvds_downclock_avail) {
3724 has_reduced_clock = limit->find_pll(limit, crtc,
3725 dev_priv->lvds_downclock,
3726 refclk,
3727 &reduced_clock);
3728 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3729 /*
3730 * If the different P is found, it means that we can't
3731 * switch the display clock by using the FP0/FP1.
3732 * In such case we will disable the LVDS downclock
3733 * feature.
3734 */
3735 DRM_DEBUG_KMS("Different P is found for "
3736 "LVDS clock/downclock\n");
3737 has_reduced_clock = 0;
3738 }
3739 }
3740 /* SDVO TV has fixed PLL values depend on its clock range,
3741 this mirrors vbios setting. */
3742 if (is_sdvo && is_tv) {
3743 if (adjusted_mode->clock >= 100000
3744 && adjusted_mode->clock < 140500) {
3745 clock.p1 = 2;
3746 clock.p2 = 10;
3747 clock.n = 3;
3748 clock.m1 = 16;
3749 clock.m2 = 8;
3750 } else if (adjusted_mode->clock >= 140500
3751 && adjusted_mode->clock <= 200000) {
3752 clock.p1 = 1;
3753 clock.p2 = 10;
3754 clock.n = 6;
3755 clock.m1 = 12;
3756 clock.m2 = 8;
3757 }
3758 }
3759
3760 /* FDI link */
3761 if (HAS_PCH_SPLIT(dev)) {
3762 int lane = 0, link_bw, bpp;
3763 /* eDP doesn't require FDI link, so just set DP M/N
3764 according to current link config */
3765 if (has_edp_encoder) {
3766 target_clock = mode->clock;
3767 intel_edp_link_config(has_edp_encoder,
3768 &lane, &link_bw);
3769 } else {
3770 /* DP over FDI requires target mode clock
3771 instead of link clock */
3772 if (is_dp)
3773 target_clock = mode->clock;
3774 else
3775 target_clock = adjusted_mode->clock;
3776
3777 /* FDI is a binary signal running at ~2.7GHz, encoding
3778 * each output octet as 10 bits. The actual frequency
3779 * is stored as a divider into a 100MHz clock, and the
3780 * mode pixel clock is stored in units of 1KHz.
3781 * Hence the bw of each lane in terms of the mode signal
3782 * is:
3783 */
3784 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
3785 }
3786
3787 /* determine panel color depth */
3788 temp = I915_READ(pipeconf_reg);
3789 temp &= ~PIPE_BPC_MASK;
3790 if (is_lvds) {
3791 int lvds_reg = I915_READ(PCH_LVDS);
3792 /* the BPC will be 6 if it is 18-bit LVDS panel */
3793 if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3794 temp |= PIPE_8BPC;
3795 else
3796 temp |= PIPE_6BPC;
3797 } else if (has_edp_encoder || (is_dp && intel_pch_has_edp(crtc))) {
3798 switch (dev_priv->edp_bpp/3) {
3799 case 8:
3800 temp |= PIPE_8BPC;
3801 break;
3802 case 10:
3803 temp |= PIPE_10BPC;
3804 break;
3805 case 6:
3806 temp |= PIPE_6BPC;
3807 break;
3808 case 12:
3809 temp |= PIPE_12BPC;
3810 break;
3811 }
3812 } else
3813 temp |= PIPE_8BPC;
3814 I915_WRITE(pipeconf_reg, temp);
3815 I915_READ(pipeconf_reg);
3816
3817 switch (temp & PIPE_BPC_MASK) {
3818 case PIPE_8BPC:
3819 bpp = 24;
3820 break;
3821 case PIPE_10BPC:
3822 bpp = 30;
3823 break;
3824 case PIPE_6BPC:
3825 bpp = 18;
3826 break;
3827 case PIPE_12BPC:
3828 bpp = 36;
3829 break;
3830 default:
3831 DRM_ERROR("unknown pipe bpc value\n");
3832 bpp = 24;
3833 }
3834
3835 if (!lane) {
3836 /*
3837 * Account for spread spectrum to avoid
3838 * oversubscribing the link. Max center spread
3839 * is 2.5%; use 5% for safety's sake.
3840 */
3841 u32 bps = target_clock * bpp * 21 / 20;
3842 lane = bps / (link_bw * 8) + 1;
3843 }
3844
3845 intel_crtc->fdi_lanes = lane;
3846
3847 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3848 }
3849
3850 /* Ironlake: try to setup display ref clock before DPLL
3851 * enabling. This is only under driver's control after
3852 * PCH B stepping, previous chipset stepping should be
3853 * ignoring this setting.
3854 */
3855 if (HAS_PCH_SPLIT(dev)) {
3856 temp = I915_READ(PCH_DREF_CONTROL);
3857 /* Always enable nonspread source */
3858 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3859 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3860 I915_WRITE(PCH_DREF_CONTROL, temp);
3861 POSTING_READ(PCH_DREF_CONTROL);
3862
3863 temp &= ~DREF_SSC_SOURCE_MASK;
3864 temp |= DREF_SSC_SOURCE_ENABLE;
3865 I915_WRITE(PCH_DREF_CONTROL, temp);
3866 POSTING_READ(PCH_DREF_CONTROL);
3867
3868 udelay(200);
3869
3870 if (has_edp_encoder) {
3871 if (dev_priv->lvds_use_ssc) {
3872 temp |= DREF_SSC1_ENABLE;
3873 I915_WRITE(PCH_DREF_CONTROL, temp);
3874 POSTING_READ(PCH_DREF_CONTROL);
3875
3876 udelay(200);
3877
3878 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3879 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3880 I915_WRITE(PCH_DREF_CONTROL, temp);
3881 POSTING_READ(PCH_DREF_CONTROL);
3882 } else {
3883 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3884 I915_WRITE(PCH_DREF_CONTROL, temp);
3885 POSTING_READ(PCH_DREF_CONTROL);
3886 }
3887 }
3888 }
3889
3890 if (IS_PINEVIEW(dev)) {
3891 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3892 if (has_reduced_clock)
3893 fp2 = (1 << reduced_clock.n) << 16 |
3894 reduced_clock.m1 << 8 | reduced_clock.m2;
3895 } else {
3896 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3897 if (has_reduced_clock)
3898 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3899 reduced_clock.m2;
3900 }
3901
3902 if (!HAS_PCH_SPLIT(dev))
3903 dpll = DPLL_VGA_MODE_DIS;
3904
3905 if (IS_I9XX(dev)) {
3906 if (is_lvds)
3907 dpll |= DPLLB_MODE_LVDS;
3908 else
3909 dpll |= DPLLB_MODE_DAC_SERIAL;
3910 if (is_sdvo) {
3911 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3912 if (pixel_multiplier > 1) {
3913 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3914 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3915 else if (HAS_PCH_SPLIT(dev))
3916 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3917 }
3918 dpll |= DPLL_DVO_HIGH_SPEED;
3919 }
3920 if (is_dp)
3921 dpll |= DPLL_DVO_HIGH_SPEED;
3922
3923 /* compute bitmask from p1 value */
3924 if (IS_PINEVIEW(dev))
3925 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3926 else {
3927 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3928 /* also FPA1 */
3929 if (HAS_PCH_SPLIT(dev))
3930 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3931 if (IS_G4X(dev) && has_reduced_clock)
3932 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3933 }
3934 switch (clock.p2) {
3935 case 5:
3936 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3937 break;
3938 case 7:
3939 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3940 break;
3941 case 10:
3942 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3943 break;
3944 case 14:
3945 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3946 break;
3947 }
3948 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
3949 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3950 } else {
3951 if (is_lvds) {
3952 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3953 } else {
3954 if (clock.p1 == 2)
3955 dpll |= PLL_P1_DIVIDE_BY_TWO;
3956 else
3957 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3958 if (clock.p2 == 4)
3959 dpll |= PLL_P2_DIVIDE_BY_4;
3960 }
3961 }
3962
3963 if (is_sdvo && is_tv)
3964 dpll |= PLL_REF_INPUT_TVCLKINBC;
3965 else if (is_tv)
3966 /* XXX: just matching BIOS for now */
3967 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3968 dpll |= 3;
3969 else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3970 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3971 else
3972 dpll |= PLL_REF_INPUT_DREFCLK;
3973
3974 /* setup pipeconf */
3975 pipeconf = I915_READ(pipeconf_reg);
3976
3977 /* Set up the display plane register */
3978 dspcntr = DISPPLANE_GAMMA_ENABLE;
3979
3980 /* Ironlake's plane is forced to pipe, bit 24 is to
3981 enable color space conversion */
3982 if (!HAS_PCH_SPLIT(dev)) {
3983 if (pipe == 0)
3984 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3985 else
3986 dspcntr |= DISPPLANE_SEL_PIPE_B;
3987 }
3988
3989 if (pipe == 0 && !IS_I965G(dev)) {
3990 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3991 * core speed.
3992 *
3993 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3994 * pipe == 0 check?
3995 */
3996 if (mode->clock >
3997 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3998 pipeconf |= PIPEACONF_DOUBLE_WIDE;
3999 else
4000 pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
4001 }
4002
4003 dspcntr |= DISPLAY_PLANE_ENABLE;
4004 pipeconf |= PIPEACONF_ENABLE;
4005 dpll |= DPLL_VCO_ENABLE;
4006
4007
4008 /* Disable the panel fitter if it was on our pipe */
4009 if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe)
4010 I915_WRITE(PFIT_CONTROL, 0);
4011
4012 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4013 drm_mode_debug_printmodeline(mode);
4014
4015 /* assign to Ironlake registers */
4016 if (HAS_PCH_SPLIT(dev)) {
4017 fp_reg = pch_fp_reg;
4018 dpll_reg = pch_dpll_reg;
4019 }
4020
4021 if (!has_edp_encoder) {
4022 I915_WRITE(fp_reg, fp);
4023 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
4024 I915_READ(dpll_reg);
4025 udelay(150);
4026 }
4027
4028 /* enable transcoder DPLL */
4029 if (HAS_PCH_CPT(dev)) {
4030 temp = I915_READ(PCH_DPLL_SEL);
4031 if (trans_dpll_sel == 0)
4032 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
4033 else
4034 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
4035 I915_WRITE(PCH_DPLL_SEL, temp);
4036 I915_READ(PCH_DPLL_SEL);
4037 udelay(150);
4038 }
4039
4040 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4041 * This is an exception to the general rule that mode_set doesn't turn
4042 * things on.
4043 */
4044 if (is_lvds) {
4045 u32 lvds;
4046
4047 if (HAS_PCH_SPLIT(dev))
4048 lvds_reg = PCH_LVDS;
4049
4050 lvds = I915_READ(lvds_reg);
4051 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4052 if (pipe == 1) {
4053 if (HAS_PCH_CPT(dev))
4054 lvds |= PORT_TRANS_B_SEL_CPT;
4055 else
4056 lvds |= LVDS_PIPEB_SELECT;
4057 } else {
4058 if (HAS_PCH_CPT(dev))
4059 lvds &= ~PORT_TRANS_SEL_MASK;
4060 else
4061 lvds &= ~LVDS_PIPEB_SELECT;
4062 }
4063 /* set the corresponsding LVDS_BORDER bit */
4064 lvds |= dev_priv->lvds_border_bits;
4065 /* Set the B0-B3 data pairs corresponding to whether we're going to
4066 * set the DPLLs for dual-channel mode or not.
4067 */
4068 if (clock.p2 == 7)
4069 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4070 else
4071 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4072
4073 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4074 * appropriately here, but we need to look more thoroughly into how
4075 * panels behave in the two modes.
4076 */
4077 /* set the dithering flag on non-PCH LVDS as needed */
4078 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
4079 if (dev_priv->lvds_dither)
4080 lvds |= LVDS_ENABLE_DITHER;
4081 else
4082 lvds &= ~LVDS_ENABLE_DITHER;
4083 }
4084 I915_WRITE(lvds_reg, lvds);
4085 I915_READ(lvds_reg);
4086 }
4087
4088 /* set the dithering flag and clear for anything other than a panel. */
4089 if (HAS_PCH_SPLIT(dev)) {
4090 pipeconf &= ~PIPECONF_DITHER_EN;
4091 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4092 if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
4093 pipeconf |= PIPECONF_DITHER_EN;
4094 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
4095 }
4096 }
4097
4098 if (is_dp)
4099 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4100 else if (HAS_PCH_SPLIT(dev)) {
4101 /* For non-DP output, clear any trans DP clock recovery setting.*/
4102 if (pipe == 0) {
4103 I915_WRITE(TRANSA_DATA_M1, 0);
4104 I915_WRITE(TRANSA_DATA_N1, 0);
4105 I915_WRITE(TRANSA_DP_LINK_M1, 0);
4106 I915_WRITE(TRANSA_DP_LINK_N1, 0);
4107 } else {
4108 I915_WRITE(TRANSB_DATA_M1, 0);
4109 I915_WRITE(TRANSB_DATA_N1, 0);
4110 I915_WRITE(TRANSB_DP_LINK_M1, 0);
4111 I915_WRITE(TRANSB_DP_LINK_N1, 0);
4112 }
4113 }
4114
4115 if (!has_edp_encoder) {
4116 I915_WRITE(fp_reg, fp);
4117 I915_WRITE(dpll_reg, dpll);
4118 I915_READ(dpll_reg);
4119 /* Wait for the clocks to stabilize. */
4120 udelay(150);
4121
4122 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
4123 if (is_sdvo) {
4124 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4125 if (pixel_multiplier > 1)
4126 pixel_multiplier = (pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4127 else
4128 pixel_multiplier = 0;
4129
4130 I915_WRITE(dpll_md_reg,
4131 (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
4132 pixel_multiplier);
4133 } else
4134 I915_WRITE(dpll_md_reg, 0);
4135 } else {
4136 /* write it again -- the BIOS does, after all */
4137 I915_WRITE(dpll_reg, dpll);
4138 }
4139 I915_READ(dpll_reg);
4140 /* Wait for the clocks to stabilize. */
4141 udelay(150);
4142 }
4143
4144 if (is_lvds && has_reduced_clock && i915_powersave) {
4145 I915_WRITE(fp_reg + 4, fp2);
4146 intel_crtc->lowfreq_avail = true;
4147 if (HAS_PIPE_CXSR(dev)) {
4148 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4149 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4150 }
4151 } else {
4152 I915_WRITE(fp_reg + 4, fp);
4153 intel_crtc->lowfreq_avail = false;
4154 if (HAS_PIPE_CXSR(dev)) {
4155 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4156 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4157 }
4158 }
4159
4160 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4161 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4162 /* the chip adds 2 halflines automatically */
4163 adjusted_mode->crtc_vdisplay -= 1;
4164 adjusted_mode->crtc_vtotal -= 1;
4165 adjusted_mode->crtc_vblank_start -= 1;
4166 adjusted_mode->crtc_vblank_end -= 1;
4167 adjusted_mode->crtc_vsync_end -= 1;
4168 adjusted_mode->crtc_vsync_start -= 1;
4169 } else
4170 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4171
4172 I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
4173 ((adjusted_mode->crtc_htotal - 1) << 16));
4174 I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
4175 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4176 I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
4177 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4178 I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
4179 ((adjusted_mode->crtc_vtotal - 1) << 16));
4180 I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
4181 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4182 I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
4183 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4184 /* pipesrc and dspsize control the size that is scaled from, which should
4185 * always be the user's requested size.
4186 */
4187 if (!HAS_PCH_SPLIT(dev)) {
4188 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
4189 (mode->hdisplay - 1));
4190 I915_WRITE(dsppos_reg, 0);
4191 }
4192 I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4193
4194 if (HAS_PCH_SPLIT(dev)) {
4195 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
4196 I915_WRITE(data_n1_reg, m_n.gmch_n);
4197 I915_WRITE(link_m1_reg, m_n.link_m);
4198 I915_WRITE(link_n1_reg, m_n.link_n);
4199
4200 if (has_edp_encoder) {
4201 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4202 } else {
4203 /* enable FDI RX PLL too */
4204 temp = I915_READ(fdi_rx_reg);
4205 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
4206 I915_READ(fdi_rx_reg);
4207 udelay(200);
4208
4209 /* enable FDI TX PLL too */
4210 temp = I915_READ(fdi_tx_reg);
4211 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
4212 I915_READ(fdi_tx_reg);
4213
4214 /* enable FDI RX PCDCLK */
4215 temp = I915_READ(fdi_rx_reg);
4216 I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
4217 I915_READ(fdi_rx_reg);
4218 udelay(200);
4219 }
4220 }
4221
4222 I915_WRITE(pipeconf_reg, pipeconf);
4223 I915_READ(pipeconf_reg);
4224
4225 intel_wait_for_vblank(dev, pipe);
4226
4227 if (IS_IRONLAKE(dev)) {
4228 /* enable address swizzle for tiling buffer */
4229 temp = I915_READ(DISP_ARB_CTL);
4230 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
4231 }
4232
4233 I915_WRITE(dspcntr_reg, dspcntr);
4234
4235 /* Flush the plane changes */
4236 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4237
4238 intel_update_watermarks(dev);
4239
4240 drm_vblank_post_modeset(dev, pipe);
4241
4242 return ret;
4243 }
4244
4245 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4246 void intel_crtc_load_lut(struct drm_crtc *crtc)
4247 {
4248 struct drm_device *dev = crtc->dev;
4249 struct drm_i915_private *dev_priv = dev->dev_private;
4250 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4251 int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4252 int i;
4253
4254 /* The clocks have to be on to load the palette. */
4255 if (!crtc->enabled)
4256 return;
4257
4258 /* use legacy palette for Ironlake */
4259 if (HAS_PCH_SPLIT(dev))
4260 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4261 LGC_PALETTE_B;
4262
4263 for (i = 0; i < 256; i++) {
4264 I915_WRITE(palreg + 4 * i,
4265 (intel_crtc->lut_r[i] << 16) |
4266 (intel_crtc->lut_g[i] << 8) |
4267 intel_crtc->lut_b[i]);
4268 }
4269 }
4270
4271 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4272 {
4273 struct drm_device *dev = crtc->dev;
4274 struct drm_i915_private *dev_priv = dev->dev_private;
4275 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4276 bool visible = base != 0;
4277 u32 cntl;
4278
4279 if (intel_crtc->cursor_visible == visible)
4280 return;
4281
4282 cntl = I915_READ(CURACNTR);
4283 if (visible) {
4284 /* On these chipsets we can only modify the base whilst
4285 * the cursor is disabled.
4286 */
4287 I915_WRITE(CURABASE, base);
4288
4289 cntl &= ~(CURSOR_FORMAT_MASK);
4290 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4291 cntl |= CURSOR_ENABLE |
4292 CURSOR_GAMMA_ENABLE |
4293 CURSOR_FORMAT_ARGB;
4294 } else
4295 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4296 I915_WRITE(CURACNTR, cntl);
4297
4298 intel_crtc->cursor_visible = visible;
4299 }
4300
4301 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4302 {
4303 struct drm_device *dev = crtc->dev;
4304 struct drm_i915_private *dev_priv = dev->dev_private;
4305 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4306 int pipe = intel_crtc->pipe;
4307 bool visible = base != 0;
4308
4309 if (intel_crtc->cursor_visible != visible) {
4310 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
4311 if (base) {
4312 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4313 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4314 cntl |= pipe << 28; /* Connect to correct pipe */
4315 } else {
4316 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4317 cntl |= CURSOR_MODE_DISABLE;
4318 }
4319 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4320
4321 intel_crtc->cursor_visible = visible;
4322 }
4323 /* and commit changes on next vblank */
4324 I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4325 }
4326
4327 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4328 static void intel_crtc_update_cursor(struct drm_crtc *crtc)
4329 {
4330 struct drm_device *dev = crtc->dev;
4331 struct drm_i915_private *dev_priv = dev->dev_private;
4332 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4333 int pipe = intel_crtc->pipe;
4334 int x = intel_crtc->cursor_x;
4335 int y = intel_crtc->cursor_y;
4336 u32 base, pos;
4337 bool visible;
4338
4339 pos = 0;
4340
4341 if (intel_crtc->cursor_on && crtc->fb) {
4342 base = intel_crtc->cursor_addr;
4343 if (x > (int) crtc->fb->width)
4344 base = 0;
4345
4346 if (y > (int) crtc->fb->height)
4347 base = 0;
4348 } else
4349 base = 0;
4350
4351 if (x < 0) {
4352 if (x + intel_crtc->cursor_width < 0)
4353 base = 0;
4354
4355 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4356 x = -x;
4357 }
4358 pos |= x << CURSOR_X_SHIFT;
4359
4360 if (y < 0) {
4361 if (y + intel_crtc->cursor_height < 0)
4362 base = 0;
4363
4364 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4365 y = -y;
4366 }
4367 pos |= y << CURSOR_Y_SHIFT;
4368
4369 visible = base != 0;
4370 if (!visible && !intel_crtc->cursor_visible)
4371 return;
4372
4373 I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
4374 if (IS_845G(dev) || IS_I865G(dev))
4375 i845_update_cursor(crtc, base);
4376 else
4377 i9xx_update_cursor(crtc, base);
4378
4379 if (visible)
4380 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4381 }
4382
4383 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4384 struct drm_file *file_priv,
4385 uint32_t handle,
4386 uint32_t width, uint32_t height)
4387 {
4388 struct drm_device *dev = crtc->dev;
4389 struct drm_i915_private *dev_priv = dev->dev_private;
4390 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4391 struct drm_gem_object *bo;
4392 struct drm_i915_gem_object *obj_priv;
4393 uint32_t addr;
4394 int ret;
4395
4396 DRM_DEBUG_KMS("\n");
4397
4398 /* if we want to turn off the cursor ignore width and height */
4399 if (!handle) {
4400 DRM_DEBUG_KMS("cursor off\n");
4401 addr = 0;
4402 bo = NULL;
4403 mutex_lock(&dev->struct_mutex);
4404 goto finish;
4405 }
4406
4407 /* Currently we only support 64x64 cursors */
4408 if (width != 64 || height != 64) {
4409 DRM_ERROR("we currently only support 64x64 cursors\n");
4410 return -EINVAL;
4411 }
4412
4413 bo = drm_gem_object_lookup(dev, file_priv, handle);
4414 if (!bo)
4415 return -ENOENT;
4416
4417 obj_priv = to_intel_bo(bo);
4418
4419 if (bo->size < width * height * 4) {
4420 DRM_ERROR("buffer is to small\n");
4421 ret = -ENOMEM;
4422 goto fail;
4423 }
4424
4425 /* we only need to pin inside GTT if cursor is non-phy */
4426 mutex_lock(&dev->struct_mutex);
4427 if (!dev_priv->info->cursor_needs_physical) {
4428 ret = i915_gem_object_pin(bo, PAGE_SIZE);
4429 if (ret) {
4430 DRM_ERROR("failed to pin cursor bo\n");
4431 goto fail_locked;
4432 }
4433
4434 ret = i915_gem_object_set_to_gtt_domain(bo, 0);
4435 if (ret) {
4436 DRM_ERROR("failed to move cursor bo into the GTT\n");
4437 goto fail_unpin;
4438 }
4439
4440 addr = obj_priv->gtt_offset;
4441 } else {
4442 int align = IS_I830(dev) ? 16 * 1024 : 256;
4443 ret = i915_gem_attach_phys_object(dev, bo,
4444 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4445 align);
4446 if (ret) {
4447 DRM_ERROR("failed to attach phys object\n");
4448 goto fail_locked;
4449 }
4450 addr = obj_priv->phys_obj->handle->busaddr;
4451 }
4452
4453 if (!IS_I9XX(dev))
4454 I915_WRITE(CURSIZE, (height << 12) | width);
4455
4456 finish:
4457 if (intel_crtc->cursor_bo) {
4458 if (dev_priv->info->cursor_needs_physical) {
4459 if (intel_crtc->cursor_bo != bo)
4460 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4461 } else
4462 i915_gem_object_unpin(intel_crtc->cursor_bo);
4463 drm_gem_object_unreference(intel_crtc->cursor_bo);
4464 }
4465
4466 mutex_unlock(&dev->struct_mutex);
4467
4468 intel_crtc->cursor_addr = addr;
4469 intel_crtc->cursor_bo = bo;
4470 intel_crtc->cursor_width = width;
4471 intel_crtc->cursor_height = height;
4472
4473 intel_crtc_update_cursor(crtc);
4474
4475 return 0;
4476 fail_unpin:
4477 i915_gem_object_unpin(bo);
4478 fail_locked:
4479 mutex_unlock(&dev->struct_mutex);
4480 fail:
4481 drm_gem_object_unreference_unlocked(bo);
4482 return ret;
4483 }
4484
4485 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4486 {
4487 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4488
4489 intel_crtc->cursor_x = x;
4490 intel_crtc->cursor_y = y;
4491
4492 intel_crtc_update_cursor(crtc);
4493
4494 return 0;
4495 }
4496
4497 /** Sets the color ramps on behalf of RandR */
4498 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4499 u16 blue, int regno)
4500 {
4501 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4502
4503 intel_crtc->lut_r[regno] = red >> 8;
4504 intel_crtc->lut_g[regno] = green >> 8;
4505 intel_crtc->lut_b[regno] = blue >> 8;
4506 }
4507
4508 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4509 u16 *blue, int regno)
4510 {
4511 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4512
4513 *red = intel_crtc->lut_r[regno] << 8;
4514 *green = intel_crtc->lut_g[regno] << 8;
4515 *blue = intel_crtc->lut_b[regno] << 8;
4516 }
4517
4518 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4519 u16 *blue, uint32_t start, uint32_t size)
4520 {
4521 int end = (start + size > 256) ? 256 : start + size, i;
4522 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4523
4524 for (i = start; i < end; i++) {
4525 intel_crtc->lut_r[i] = red[i] >> 8;
4526 intel_crtc->lut_g[i] = green[i] >> 8;
4527 intel_crtc->lut_b[i] = blue[i] >> 8;
4528 }
4529
4530 intel_crtc_load_lut(crtc);
4531 }
4532
4533 /**
4534 * Get a pipe with a simple mode set on it for doing load-based monitor
4535 * detection.
4536 *
4537 * It will be up to the load-detect code to adjust the pipe as appropriate for
4538 * its requirements. The pipe will be connected to no other encoders.
4539 *
4540 * Currently this code will only succeed if there is a pipe with no encoders
4541 * configured for it. In the future, it could choose to temporarily disable
4542 * some outputs to free up a pipe for its use.
4543 *
4544 * \return crtc, or NULL if no pipes are available.
4545 */
4546
4547 /* VESA 640x480x72Hz mode to set on the pipe */
4548 static struct drm_display_mode load_detect_mode = {
4549 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4550 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4551 };
4552
4553 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4554 struct drm_connector *connector,
4555 struct drm_display_mode *mode,
4556 int *dpms_mode)
4557 {
4558 struct intel_crtc *intel_crtc;
4559 struct drm_crtc *possible_crtc;
4560 struct drm_crtc *supported_crtc =NULL;
4561 struct drm_encoder *encoder = &intel_encoder->base;
4562 struct drm_crtc *crtc = NULL;
4563 struct drm_device *dev = encoder->dev;
4564 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4565 struct drm_crtc_helper_funcs *crtc_funcs;
4566 int i = -1;
4567
4568 /*
4569 * Algorithm gets a little messy:
4570 * - if the connector already has an assigned crtc, use it (but make
4571 * sure it's on first)
4572 * - try to find the first unused crtc that can drive this connector,
4573 * and use that if we find one
4574 * - if there are no unused crtcs available, try to use the first
4575 * one we found that supports the connector
4576 */
4577
4578 /* See if we already have a CRTC for this connector */
4579 if (encoder->crtc) {
4580 crtc = encoder->crtc;
4581 /* Make sure the crtc and connector are running */
4582 intel_crtc = to_intel_crtc(crtc);
4583 *dpms_mode = intel_crtc->dpms_mode;
4584 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4585 crtc_funcs = crtc->helper_private;
4586 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4587 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4588 }
4589 return crtc;
4590 }
4591
4592 /* Find an unused one (if possible) */
4593 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4594 i++;
4595 if (!(encoder->possible_crtcs & (1 << i)))
4596 continue;
4597 if (!possible_crtc->enabled) {
4598 crtc = possible_crtc;
4599 break;
4600 }
4601 if (!supported_crtc)
4602 supported_crtc = possible_crtc;
4603 }
4604
4605 /*
4606 * If we didn't find an unused CRTC, don't use any.
4607 */
4608 if (!crtc) {
4609 return NULL;
4610 }
4611
4612 encoder->crtc = crtc;
4613 connector->encoder = encoder;
4614 intel_encoder->load_detect_temp = true;
4615
4616 intel_crtc = to_intel_crtc(crtc);
4617 *dpms_mode = intel_crtc->dpms_mode;
4618
4619 if (!crtc->enabled) {
4620 if (!mode)
4621 mode = &load_detect_mode;
4622 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4623 } else {
4624 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4625 crtc_funcs = crtc->helper_private;
4626 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4627 }
4628
4629 /* Add this connector to the crtc */
4630 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4631 encoder_funcs->commit(encoder);
4632 }
4633 /* let the connector get through one full cycle before testing */
4634 intel_wait_for_vblank(dev, intel_crtc->pipe);
4635
4636 return crtc;
4637 }
4638
4639 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4640 struct drm_connector *connector, int dpms_mode)
4641 {
4642 struct drm_encoder *encoder = &intel_encoder->base;
4643 struct drm_device *dev = encoder->dev;
4644 struct drm_crtc *crtc = encoder->crtc;
4645 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4646 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4647
4648 if (intel_encoder->load_detect_temp) {
4649 encoder->crtc = NULL;
4650 connector->encoder = NULL;
4651 intel_encoder->load_detect_temp = false;
4652 crtc->enabled = drm_helper_crtc_in_use(crtc);
4653 drm_helper_disable_unused_functions(dev);
4654 }
4655
4656 /* Switch crtc and encoder back off if necessary */
4657 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4658 if (encoder->crtc == crtc)
4659 encoder_funcs->dpms(encoder, dpms_mode);
4660 crtc_funcs->dpms(crtc, dpms_mode);
4661 }
4662 }
4663
4664 /* Returns the clock of the currently programmed mode of the given pipe. */
4665 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4666 {
4667 struct drm_i915_private *dev_priv = dev->dev_private;
4668 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4669 int pipe = intel_crtc->pipe;
4670 u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4671 u32 fp;
4672 intel_clock_t clock;
4673
4674 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4675 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4676 else
4677 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4678
4679 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4680 if (IS_PINEVIEW(dev)) {
4681 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4682 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4683 } else {
4684 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4685 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4686 }
4687
4688 if (IS_I9XX(dev)) {
4689 if (IS_PINEVIEW(dev))
4690 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4691 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4692 else
4693 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4694 DPLL_FPA01_P1_POST_DIV_SHIFT);
4695
4696 switch (dpll & DPLL_MODE_MASK) {
4697 case DPLLB_MODE_DAC_SERIAL:
4698 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4699 5 : 10;
4700 break;
4701 case DPLLB_MODE_LVDS:
4702 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4703 7 : 14;
4704 break;
4705 default:
4706 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4707 "mode\n", (int)(dpll & DPLL_MODE_MASK));
4708 return 0;
4709 }
4710
4711 /* XXX: Handle the 100Mhz refclk */
4712 intel_clock(dev, 96000, &clock);
4713 } else {
4714 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4715
4716 if (is_lvds) {
4717 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4718 DPLL_FPA01_P1_POST_DIV_SHIFT);
4719 clock.p2 = 14;
4720
4721 if ((dpll & PLL_REF_INPUT_MASK) ==
4722 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4723 /* XXX: might not be 66MHz */
4724 intel_clock(dev, 66000, &clock);
4725 } else
4726 intel_clock(dev, 48000, &clock);
4727 } else {
4728 if (dpll & PLL_P1_DIVIDE_BY_TWO)
4729 clock.p1 = 2;
4730 else {
4731 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4732 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4733 }
4734 if (dpll & PLL_P2_DIVIDE_BY_4)
4735 clock.p2 = 4;
4736 else
4737 clock.p2 = 2;
4738
4739 intel_clock(dev, 48000, &clock);
4740 }
4741 }
4742
4743 /* XXX: It would be nice to validate the clocks, but we can't reuse
4744 * i830PllIsValid() because it relies on the xf86_config connector
4745 * configuration being accurate, which it isn't necessarily.
4746 */
4747
4748 return clock.dot;
4749 }
4750
4751 /** Returns the currently programmed mode of the given pipe. */
4752 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4753 struct drm_crtc *crtc)
4754 {
4755 struct drm_i915_private *dev_priv = dev->dev_private;
4756 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4757 int pipe = intel_crtc->pipe;
4758 struct drm_display_mode *mode;
4759 int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4760 int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4761 int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4762 int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4763
4764 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4765 if (!mode)
4766 return NULL;
4767
4768 mode->clock = intel_crtc_clock_get(dev, crtc);
4769 mode->hdisplay = (htot & 0xffff) + 1;
4770 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4771 mode->hsync_start = (hsync & 0xffff) + 1;
4772 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4773 mode->vdisplay = (vtot & 0xffff) + 1;
4774 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4775 mode->vsync_start = (vsync & 0xffff) + 1;
4776 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4777
4778 drm_mode_set_name(mode);
4779 drm_mode_set_crtcinfo(mode, 0);
4780
4781 return mode;
4782 }
4783
4784 #define GPU_IDLE_TIMEOUT 500 /* ms */
4785
4786 /* When this timer fires, we've been idle for awhile */
4787 static void intel_gpu_idle_timer(unsigned long arg)
4788 {
4789 struct drm_device *dev = (struct drm_device *)arg;
4790 drm_i915_private_t *dev_priv = dev->dev_private;
4791
4792 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4793
4794 dev_priv->busy = false;
4795
4796 queue_work(dev_priv->wq, &dev_priv->idle_work);
4797 }
4798
4799 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4800
4801 static void intel_crtc_idle_timer(unsigned long arg)
4802 {
4803 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4804 struct drm_crtc *crtc = &intel_crtc->base;
4805 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4806
4807 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4808
4809 intel_crtc->busy = false;
4810
4811 queue_work(dev_priv->wq, &dev_priv->idle_work);
4812 }
4813
4814 static void intel_increase_pllclock(struct drm_crtc *crtc)
4815 {
4816 struct drm_device *dev = crtc->dev;
4817 drm_i915_private_t *dev_priv = dev->dev_private;
4818 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4819 int pipe = intel_crtc->pipe;
4820 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4821 int dpll = I915_READ(dpll_reg);
4822
4823 if (HAS_PCH_SPLIT(dev))
4824 return;
4825
4826 if (!dev_priv->lvds_downclock_avail)
4827 return;
4828
4829 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4830 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4831
4832 /* Unlock panel regs */
4833 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4834 PANEL_UNLOCK_REGS);
4835
4836 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4837 I915_WRITE(dpll_reg, dpll);
4838 dpll = I915_READ(dpll_reg);
4839 intel_wait_for_vblank(dev, pipe);
4840 dpll = I915_READ(dpll_reg);
4841 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4842 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4843
4844 /* ...and lock them again */
4845 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4846 }
4847
4848 /* Schedule downclock */
4849 mod_timer(&intel_crtc->idle_timer, jiffies +
4850 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4851 }
4852
4853 static void intel_decrease_pllclock(struct drm_crtc *crtc)
4854 {
4855 struct drm_device *dev = crtc->dev;
4856 drm_i915_private_t *dev_priv = dev->dev_private;
4857 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4858 int pipe = intel_crtc->pipe;
4859 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4860 int dpll = I915_READ(dpll_reg);
4861
4862 if (HAS_PCH_SPLIT(dev))
4863 return;
4864
4865 if (!dev_priv->lvds_downclock_avail)
4866 return;
4867
4868 /*
4869 * Since this is called by a timer, we should never get here in
4870 * the manual case.
4871 */
4872 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
4873 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4874
4875 /* Unlock panel regs */
4876 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4877 PANEL_UNLOCK_REGS);
4878
4879 dpll |= DISPLAY_RATE_SELECT_FPA1;
4880 I915_WRITE(dpll_reg, dpll);
4881 dpll = I915_READ(dpll_reg);
4882 intel_wait_for_vblank(dev, pipe);
4883 dpll = I915_READ(dpll_reg);
4884 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4885 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4886
4887 /* ...and lock them again */
4888 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4889 }
4890
4891 }
4892
4893 /**
4894 * intel_idle_update - adjust clocks for idleness
4895 * @work: work struct
4896 *
4897 * Either the GPU or display (or both) went idle. Check the busy status
4898 * here and adjust the CRTC and GPU clocks as necessary.
4899 */
4900 static void intel_idle_update(struct work_struct *work)
4901 {
4902 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4903 idle_work);
4904 struct drm_device *dev = dev_priv->dev;
4905 struct drm_crtc *crtc;
4906 struct intel_crtc *intel_crtc;
4907 int enabled = 0;
4908
4909 if (!i915_powersave)
4910 return;
4911
4912 mutex_lock(&dev->struct_mutex);
4913
4914 i915_update_gfx_val(dev_priv);
4915
4916 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4917 /* Skip inactive CRTCs */
4918 if (!crtc->fb)
4919 continue;
4920
4921 enabled++;
4922 intel_crtc = to_intel_crtc(crtc);
4923 if (!intel_crtc->busy)
4924 intel_decrease_pllclock(crtc);
4925 }
4926
4927 if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
4928 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4929 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4930 }
4931
4932 mutex_unlock(&dev->struct_mutex);
4933 }
4934
4935 /**
4936 * intel_mark_busy - mark the GPU and possibly the display busy
4937 * @dev: drm device
4938 * @obj: object we're operating on
4939 *
4940 * Callers can use this function to indicate that the GPU is busy processing
4941 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
4942 * buffer), we'll also mark the display as busy, so we know to increase its
4943 * clock frequency.
4944 */
4945 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4946 {
4947 drm_i915_private_t *dev_priv = dev->dev_private;
4948 struct drm_crtc *crtc = NULL;
4949 struct intel_framebuffer *intel_fb;
4950 struct intel_crtc *intel_crtc;
4951
4952 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4953 return;
4954
4955 if (!dev_priv->busy) {
4956 if (IS_I945G(dev) || IS_I945GM(dev)) {
4957 u32 fw_blc_self;
4958
4959 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4960 fw_blc_self = I915_READ(FW_BLC_SELF);
4961 fw_blc_self &= ~FW_BLC_SELF_EN;
4962 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4963 }
4964 dev_priv->busy = true;
4965 } else
4966 mod_timer(&dev_priv->idle_timer, jiffies +
4967 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4968
4969 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4970 if (!crtc->fb)
4971 continue;
4972
4973 intel_crtc = to_intel_crtc(crtc);
4974 intel_fb = to_intel_framebuffer(crtc->fb);
4975 if (intel_fb->obj == obj) {
4976 if (!intel_crtc->busy) {
4977 if (IS_I945G(dev) || IS_I945GM(dev)) {
4978 u32 fw_blc_self;
4979
4980 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4981 fw_blc_self = I915_READ(FW_BLC_SELF);
4982 fw_blc_self &= ~FW_BLC_SELF_EN;
4983 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4984 }
4985 /* Non-busy -> busy, upclock */
4986 intel_increase_pllclock(crtc);
4987 intel_crtc->busy = true;
4988 } else {
4989 /* Busy -> busy, put off timer */
4990 mod_timer(&intel_crtc->idle_timer, jiffies +
4991 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4992 }
4993 }
4994 }
4995 }
4996
4997 static void intel_crtc_destroy(struct drm_crtc *crtc)
4998 {
4999 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5000 struct drm_device *dev = crtc->dev;
5001 struct intel_unpin_work *work;
5002 unsigned long flags;
5003
5004 spin_lock_irqsave(&dev->event_lock, flags);
5005 work = intel_crtc->unpin_work;
5006 intel_crtc->unpin_work = NULL;
5007 spin_unlock_irqrestore(&dev->event_lock, flags);
5008
5009 if (work) {
5010 cancel_work_sync(&work->work);
5011 kfree(work);
5012 }
5013
5014 drm_crtc_cleanup(crtc);
5015
5016 kfree(intel_crtc);
5017 }
5018
5019 static void intel_unpin_work_fn(struct work_struct *__work)
5020 {
5021 struct intel_unpin_work *work =
5022 container_of(__work, struct intel_unpin_work, work);
5023
5024 mutex_lock(&work->dev->struct_mutex);
5025 i915_gem_object_unpin(work->old_fb_obj);
5026 drm_gem_object_unreference(work->pending_flip_obj);
5027 drm_gem_object_unreference(work->old_fb_obj);
5028 mutex_unlock(&work->dev->struct_mutex);
5029 kfree(work);
5030 }
5031
5032 static void do_intel_finish_page_flip(struct drm_device *dev,
5033 struct drm_crtc *crtc)
5034 {
5035 drm_i915_private_t *dev_priv = dev->dev_private;
5036 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5037 struct intel_unpin_work *work;
5038 struct drm_i915_gem_object *obj_priv;
5039 struct drm_pending_vblank_event *e;
5040 struct timeval now;
5041 unsigned long flags;
5042
5043 /* Ignore early vblank irqs */
5044 if (intel_crtc == NULL)
5045 return;
5046
5047 spin_lock_irqsave(&dev->event_lock, flags);
5048 work = intel_crtc->unpin_work;
5049 if (work == NULL || !work->pending) {
5050 spin_unlock_irqrestore(&dev->event_lock, flags);
5051 return;
5052 }
5053
5054 intel_crtc->unpin_work = NULL;
5055 drm_vblank_put(dev, intel_crtc->pipe);
5056
5057 if (work->event) {
5058 e = work->event;
5059 do_gettimeofday(&now);
5060 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
5061 e->event.tv_sec = now.tv_sec;
5062 e->event.tv_usec = now.tv_usec;
5063 list_add_tail(&e->base.link,
5064 &e->base.file_priv->event_list);
5065 wake_up_interruptible(&e->base.file_priv->event_wait);
5066 }
5067
5068 spin_unlock_irqrestore(&dev->event_lock, flags);
5069
5070 obj_priv = to_intel_bo(work->pending_flip_obj);
5071
5072 /* Initial scanout buffer will have a 0 pending flip count */
5073 if ((atomic_read(&obj_priv->pending_flip) == 0) ||
5074 atomic_dec_and_test(&obj_priv->pending_flip))
5075 DRM_WAKEUP(&dev_priv->pending_flip_queue);
5076 schedule_work(&work->work);
5077
5078 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
5079 }
5080
5081 void intel_finish_page_flip(struct drm_device *dev, int pipe)
5082 {
5083 drm_i915_private_t *dev_priv = dev->dev_private;
5084 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5085
5086 do_intel_finish_page_flip(dev, crtc);
5087 }
5088
5089 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5090 {
5091 drm_i915_private_t *dev_priv = dev->dev_private;
5092 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5093
5094 do_intel_finish_page_flip(dev, crtc);
5095 }
5096
5097 void intel_prepare_page_flip(struct drm_device *dev, int plane)
5098 {
5099 drm_i915_private_t *dev_priv = dev->dev_private;
5100 struct intel_crtc *intel_crtc =
5101 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5102 unsigned long flags;
5103
5104 spin_lock_irqsave(&dev->event_lock, flags);
5105 if (intel_crtc->unpin_work) {
5106 if ((++intel_crtc->unpin_work->pending) > 1)
5107 DRM_ERROR("Prepared flip multiple times\n");
5108 } else {
5109 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5110 }
5111 spin_unlock_irqrestore(&dev->event_lock, flags);
5112 }
5113
5114 static int intel_crtc_page_flip(struct drm_crtc *crtc,
5115 struct drm_framebuffer *fb,
5116 struct drm_pending_vblank_event *event)
5117 {
5118 struct drm_device *dev = crtc->dev;
5119 struct drm_i915_private *dev_priv = dev->dev_private;
5120 struct intel_framebuffer *intel_fb;
5121 struct drm_i915_gem_object *obj_priv;
5122 struct drm_gem_object *obj;
5123 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5124 struct intel_unpin_work *work;
5125 unsigned long flags, offset;
5126 int pipe = intel_crtc->pipe;
5127 u32 pf, pipesrc;
5128 int ret;
5129
5130 work = kzalloc(sizeof *work, GFP_KERNEL);
5131 if (work == NULL)
5132 return -ENOMEM;
5133
5134 work->event = event;
5135 work->dev = crtc->dev;
5136 intel_fb = to_intel_framebuffer(crtc->fb);
5137 work->old_fb_obj = intel_fb->obj;
5138 INIT_WORK(&work->work, intel_unpin_work_fn);
5139
5140 /* We borrow the event spin lock for protecting unpin_work */
5141 spin_lock_irqsave(&dev->event_lock, flags);
5142 if (intel_crtc->unpin_work) {
5143 spin_unlock_irqrestore(&dev->event_lock, flags);
5144 kfree(work);
5145
5146 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5147 return -EBUSY;
5148 }
5149 intel_crtc->unpin_work = work;
5150 spin_unlock_irqrestore(&dev->event_lock, flags);
5151
5152 intel_fb = to_intel_framebuffer(fb);
5153 obj = intel_fb->obj;
5154
5155 mutex_lock(&dev->struct_mutex);
5156 ret = intel_pin_and_fence_fb_obj(dev, obj);
5157 if (ret)
5158 goto cleanup_work;
5159
5160 /* Reference the objects for the scheduled work. */
5161 drm_gem_object_reference(work->old_fb_obj);
5162 drm_gem_object_reference(obj);
5163
5164 crtc->fb = fb;
5165 ret = i915_gem_object_flush_write_domain(obj);
5166 if (ret)
5167 goto cleanup_objs;
5168
5169 ret = drm_vblank_get(dev, intel_crtc->pipe);
5170 if (ret)
5171 goto cleanup_objs;
5172
5173 obj_priv = to_intel_bo(obj);
5174 atomic_inc(&obj_priv->pending_flip);
5175 work->pending_flip_obj = obj;
5176
5177 if (IS_GEN3(dev) || IS_GEN2(dev)) {
5178 u32 flip_mask;
5179
5180 if (intel_crtc->plane)
5181 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5182 else
5183 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5184
5185 BEGIN_LP_RING(2);
5186 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5187 OUT_RING(0);
5188 ADVANCE_LP_RING();
5189 }
5190
5191 work->enable_stall_check = true;
5192
5193 /* Offset into the new buffer for cases of shared fbs between CRTCs */
5194 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
5195
5196 BEGIN_LP_RING(4);
5197 switch(INTEL_INFO(dev)->gen) {
5198 case 2:
5199 OUT_RING(MI_DISPLAY_FLIP |
5200 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5201 OUT_RING(fb->pitch);
5202 OUT_RING(obj_priv->gtt_offset + offset);
5203 OUT_RING(MI_NOOP);
5204 break;
5205
5206 case 3:
5207 OUT_RING(MI_DISPLAY_FLIP_I915 |
5208 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5209 OUT_RING(fb->pitch);
5210 OUT_RING(obj_priv->gtt_offset + offset);
5211 OUT_RING(MI_NOOP);
5212 break;
5213
5214 case 4:
5215 case 5:
5216 /* i965+ uses the linear or tiled offsets from the
5217 * Display Registers (which do not change across a page-flip)
5218 * so we need only reprogram the base address.
5219 */
5220 OUT_RING(MI_DISPLAY_FLIP |
5221 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5222 OUT_RING(fb->pitch);
5223 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
5224
5225 /* XXX Enabling the panel-fitter across page-flip is so far
5226 * untested on non-native modes, so ignore it for now.
5227 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5228 */
5229 pf = 0;
5230 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5231 OUT_RING(pf | pipesrc);
5232 break;
5233
5234 case 6:
5235 OUT_RING(MI_DISPLAY_FLIP |
5236 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5237 OUT_RING(fb->pitch | obj_priv->tiling_mode);
5238 OUT_RING(obj_priv->gtt_offset);
5239
5240 pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5241 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5242 OUT_RING(pf | pipesrc);
5243 break;
5244 }
5245 ADVANCE_LP_RING();
5246
5247 mutex_unlock(&dev->struct_mutex);
5248
5249 trace_i915_flip_request(intel_crtc->plane, obj);
5250
5251 return 0;
5252
5253 cleanup_objs:
5254 drm_gem_object_unreference(work->old_fb_obj);
5255 drm_gem_object_unreference(obj);
5256 cleanup_work:
5257 mutex_unlock(&dev->struct_mutex);
5258
5259 spin_lock_irqsave(&dev->event_lock, flags);
5260 intel_crtc->unpin_work = NULL;
5261 spin_unlock_irqrestore(&dev->event_lock, flags);
5262
5263 kfree(work);
5264
5265 return ret;
5266 }
5267
5268 static struct drm_crtc_helper_funcs intel_helper_funcs = {
5269 .dpms = intel_crtc_dpms,
5270 .mode_fixup = intel_crtc_mode_fixup,
5271 .mode_set = intel_crtc_mode_set,
5272 .mode_set_base = intel_pipe_set_base,
5273 .mode_set_base_atomic = intel_pipe_set_base_atomic,
5274 .load_lut = intel_crtc_load_lut,
5275 };
5276
5277 static const struct drm_crtc_funcs intel_crtc_funcs = {
5278 .cursor_set = intel_crtc_cursor_set,
5279 .cursor_move = intel_crtc_cursor_move,
5280 .gamma_set = intel_crtc_gamma_set,
5281 .set_config = drm_crtc_helper_set_config,
5282 .destroy = intel_crtc_destroy,
5283 .page_flip = intel_crtc_page_flip,
5284 };
5285
5286
5287 static void intel_crtc_init(struct drm_device *dev, int pipe)
5288 {
5289 drm_i915_private_t *dev_priv = dev->dev_private;
5290 struct intel_crtc *intel_crtc;
5291 int i;
5292
5293 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
5294 if (intel_crtc == NULL)
5295 return;
5296
5297 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
5298
5299 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
5300 intel_crtc->pipe = pipe;
5301 intel_crtc->plane = pipe;
5302 for (i = 0; i < 256; i++) {
5303 intel_crtc->lut_r[i] = i;
5304 intel_crtc->lut_g[i] = i;
5305 intel_crtc->lut_b[i] = i;
5306 }
5307
5308 /* Swap pipes & planes for FBC on pre-965 */
5309 intel_crtc->pipe = pipe;
5310 intel_crtc->plane = pipe;
5311 if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
5312 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5313 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
5314 }
5315
5316 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
5317 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
5318 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5319 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5320
5321 intel_crtc->cursor_addr = 0;
5322 intel_crtc->dpms_mode = -1;
5323
5324 if (HAS_PCH_SPLIT(dev)) {
5325 intel_helper_funcs.prepare = ironlake_crtc_prepare;
5326 intel_helper_funcs.commit = ironlake_crtc_commit;
5327 } else {
5328 intel_helper_funcs.prepare = i9xx_crtc_prepare;
5329 intel_helper_funcs.commit = i9xx_crtc_commit;
5330 }
5331
5332 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5333
5334 intel_crtc->busy = false;
5335
5336 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
5337 (unsigned long)intel_crtc);
5338 }
5339
5340 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
5341 struct drm_file *file_priv)
5342 {
5343 drm_i915_private_t *dev_priv = dev->dev_private;
5344 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5345 struct drm_mode_object *drmmode_obj;
5346 struct intel_crtc *crtc;
5347
5348 if (!dev_priv) {
5349 DRM_ERROR("called with no initialization\n");
5350 return -EINVAL;
5351 }
5352
5353 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
5354 DRM_MODE_OBJECT_CRTC);
5355
5356 if (!drmmode_obj) {
5357 DRM_ERROR("no such CRTC id\n");
5358 return -EINVAL;
5359 }
5360
5361 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
5362 pipe_from_crtc_id->pipe = crtc->pipe;
5363
5364 return 0;
5365 }
5366
5367 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
5368 {
5369 struct intel_encoder *encoder;
5370 int index_mask = 0;
5371 int entry = 0;
5372
5373 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5374 if (type_mask & encoder->clone_mask)
5375 index_mask |= (1 << entry);
5376 entry++;
5377 }
5378
5379 return index_mask;
5380 }
5381
5382 static void intel_setup_outputs(struct drm_device *dev)
5383 {
5384 struct drm_i915_private *dev_priv = dev->dev_private;
5385 struct intel_encoder *encoder;
5386 bool dpd_is_edp = false;
5387
5388 if (IS_MOBILE(dev) && !IS_I830(dev))
5389 intel_lvds_init(dev);
5390
5391 if (HAS_PCH_SPLIT(dev)) {
5392 dpd_is_edp = intel_dpd_is_edp(dev);
5393
5394 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
5395 intel_dp_init(dev, DP_A);
5396
5397 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5398 intel_dp_init(dev, PCH_DP_D);
5399 }
5400
5401 intel_crt_init(dev);
5402
5403 if (HAS_PCH_SPLIT(dev)) {
5404 int found;
5405
5406 if (I915_READ(HDMIB) & PORT_DETECTED) {
5407 /* PCH SDVOB multiplex with HDMIB */
5408 found = intel_sdvo_init(dev, PCH_SDVOB);
5409 if (!found)
5410 intel_hdmi_init(dev, HDMIB);
5411 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5412 intel_dp_init(dev, PCH_DP_B);
5413 }
5414
5415 if (I915_READ(HDMIC) & PORT_DETECTED)
5416 intel_hdmi_init(dev, HDMIC);
5417
5418 if (I915_READ(HDMID) & PORT_DETECTED)
5419 intel_hdmi_init(dev, HDMID);
5420
5421 if (I915_READ(PCH_DP_C) & DP_DETECTED)
5422 intel_dp_init(dev, PCH_DP_C);
5423
5424 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5425 intel_dp_init(dev, PCH_DP_D);
5426
5427 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
5428 bool found = false;
5429
5430 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5431 DRM_DEBUG_KMS("probing SDVOB\n");
5432 found = intel_sdvo_init(dev, SDVOB);
5433 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
5434 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5435 intel_hdmi_init(dev, SDVOB);
5436 }
5437
5438 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
5439 DRM_DEBUG_KMS("probing DP_B\n");
5440 intel_dp_init(dev, DP_B);
5441 }
5442 }
5443
5444 /* Before G4X SDVOC doesn't have its own detect register */
5445
5446 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5447 DRM_DEBUG_KMS("probing SDVOC\n");
5448 found = intel_sdvo_init(dev, SDVOC);
5449 }
5450
5451 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
5452
5453 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
5454 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5455 intel_hdmi_init(dev, SDVOC);
5456 }
5457 if (SUPPORTS_INTEGRATED_DP(dev)) {
5458 DRM_DEBUG_KMS("probing DP_C\n");
5459 intel_dp_init(dev, DP_C);
5460 }
5461 }
5462
5463 if (SUPPORTS_INTEGRATED_DP(dev) &&
5464 (I915_READ(DP_D) & DP_DETECTED)) {
5465 DRM_DEBUG_KMS("probing DP_D\n");
5466 intel_dp_init(dev, DP_D);
5467 }
5468 } else if (IS_GEN2(dev))
5469 intel_dvo_init(dev);
5470
5471 if (SUPPORTS_TV(dev))
5472 intel_tv_init(dev);
5473
5474 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5475 encoder->base.possible_crtcs = encoder->crtc_mask;
5476 encoder->base.possible_clones =
5477 intel_encoder_clones(dev, encoder->clone_mask);
5478 }
5479 }
5480
5481 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5482 {
5483 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5484
5485 drm_framebuffer_cleanup(fb);
5486 drm_gem_object_unreference_unlocked(intel_fb->obj);
5487
5488 kfree(intel_fb);
5489 }
5490
5491 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5492 struct drm_file *file_priv,
5493 unsigned int *handle)
5494 {
5495 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5496 struct drm_gem_object *object = intel_fb->obj;
5497
5498 return drm_gem_handle_create(file_priv, object, handle);
5499 }
5500
5501 static const struct drm_framebuffer_funcs intel_fb_funcs = {
5502 .destroy = intel_user_framebuffer_destroy,
5503 .create_handle = intel_user_framebuffer_create_handle,
5504 };
5505
5506 int intel_framebuffer_init(struct drm_device *dev,
5507 struct intel_framebuffer *intel_fb,
5508 struct drm_mode_fb_cmd *mode_cmd,
5509 struct drm_gem_object *obj)
5510 {
5511 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
5512 int ret;
5513
5514 if (obj_priv->tiling_mode == I915_TILING_Y)
5515 return -EINVAL;
5516
5517 if (mode_cmd->pitch & 63)
5518 return -EINVAL;
5519
5520 switch (mode_cmd->bpp) {
5521 case 8:
5522 case 16:
5523 case 24:
5524 case 32:
5525 break;
5526 default:
5527 return -EINVAL;
5528 }
5529
5530 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5531 if (ret) {
5532 DRM_ERROR("framebuffer init failed %d\n", ret);
5533 return ret;
5534 }
5535
5536 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
5537 intel_fb->obj = obj;
5538 return 0;
5539 }
5540
5541 static struct drm_framebuffer *
5542 intel_user_framebuffer_create(struct drm_device *dev,
5543 struct drm_file *filp,
5544 struct drm_mode_fb_cmd *mode_cmd)
5545 {
5546 struct drm_gem_object *obj;
5547 struct intel_framebuffer *intel_fb;
5548 int ret;
5549
5550 obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
5551 if (!obj)
5552 return ERR_PTR(-ENOENT);
5553
5554 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5555 if (!intel_fb)
5556 return ERR_PTR(-ENOMEM);
5557
5558 ret = intel_framebuffer_init(dev, intel_fb,
5559 mode_cmd, obj);
5560 if (ret) {
5561 drm_gem_object_unreference_unlocked(obj);
5562 kfree(intel_fb);
5563 return ERR_PTR(ret);
5564 }
5565
5566 return &intel_fb->base;
5567 }
5568
5569 static const struct drm_mode_config_funcs intel_mode_funcs = {
5570 .fb_create = intel_user_framebuffer_create,
5571 .output_poll_changed = intel_fb_output_poll_changed,
5572 };
5573
5574 static struct drm_gem_object *
5575 intel_alloc_context_page(struct drm_device *dev)
5576 {
5577 struct drm_gem_object *ctx;
5578 int ret;
5579
5580 ctx = i915_gem_alloc_object(dev, 4096);
5581 if (!ctx) {
5582 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5583 return NULL;
5584 }
5585
5586 mutex_lock(&dev->struct_mutex);
5587 ret = i915_gem_object_pin(ctx, 4096);
5588 if (ret) {
5589 DRM_ERROR("failed to pin power context: %d\n", ret);
5590 goto err_unref;
5591 }
5592
5593 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
5594 if (ret) {
5595 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5596 goto err_unpin;
5597 }
5598 mutex_unlock(&dev->struct_mutex);
5599
5600 return ctx;
5601
5602 err_unpin:
5603 i915_gem_object_unpin(ctx);
5604 err_unref:
5605 drm_gem_object_unreference(ctx);
5606 mutex_unlock(&dev->struct_mutex);
5607 return NULL;
5608 }
5609
5610 bool ironlake_set_drps(struct drm_device *dev, u8 val)
5611 {
5612 struct drm_i915_private *dev_priv = dev->dev_private;
5613 u16 rgvswctl;
5614
5615 rgvswctl = I915_READ16(MEMSWCTL);
5616 if (rgvswctl & MEMCTL_CMD_STS) {
5617 DRM_DEBUG("gpu busy, RCS change rejected\n");
5618 return false; /* still busy with another command */
5619 }
5620
5621 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5622 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5623 I915_WRITE16(MEMSWCTL, rgvswctl);
5624 POSTING_READ16(MEMSWCTL);
5625
5626 rgvswctl |= MEMCTL_CMD_STS;
5627 I915_WRITE16(MEMSWCTL, rgvswctl);
5628
5629 return true;
5630 }
5631
5632 void ironlake_enable_drps(struct drm_device *dev)
5633 {
5634 struct drm_i915_private *dev_priv = dev->dev_private;
5635 u32 rgvmodectl = I915_READ(MEMMODECTL);
5636 u8 fmax, fmin, fstart, vstart;
5637
5638 /* Enable temp reporting */
5639 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
5640 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
5641
5642 /* 100ms RC evaluation intervals */
5643 I915_WRITE(RCUPEI, 100000);
5644 I915_WRITE(RCDNEI, 100000);
5645
5646 /* Set max/min thresholds to 90ms and 80ms respectively */
5647 I915_WRITE(RCBMAXAVG, 90000);
5648 I915_WRITE(RCBMINAVG, 80000);
5649
5650 I915_WRITE(MEMIHYST, 1);
5651
5652 /* Set up min, max, and cur for interrupt handling */
5653 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5654 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5655 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5656 MEMMODE_FSTART_SHIFT;
5657 fstart = fmax;
5658
5659 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5660 PXVFREQ_PX_SHIFT;
5661
5662 dev_priv->fmax = fstart; /* IPS callback will increase this */
5663 dev_priv->fstart = fstart;
5664
5665 dev_priv->max_delay = fmax;
5666 dev_priv->min_delay = fmin;
5667 dev_priv->cur_delay = fstart;
5668
5669 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin,
5670 fstart);
5671
5672 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5673
5674 /*
5675 * Interrupts will be enabled in ironlake_irq_postinstall
5676 */
5677
5678 I915_WRITE(VIDSTART, vstart);
5679 POSTING_READ(VIDSTART);
5680
5681 rgvmodectl |= MEMMODE_SWMODE_EN;
5682 I915_WRITE(MEMMODECTL, rgvmodectl);
5683
5684 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
5685 DRM_ERROR("stuck trying to change perf mode\n");
5686 msleep(1);
5687
5688 ironlake_set_drps(dev, fstart);
5689
5690 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5691 I915_READ(0x112e0);
5692 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5693 dev_priv->last_count2 = I915_READ(0x112f4);
5694 getrawmonotonic(&dev_priv->last_time2);
5695 }
5696
5697 void ironlake_disable_drps(struct drm_device *dev)
5698 {
5699 struct drm_i915_private *dev_priv = dev->dev_private;
5700 u16 rgvswctl = I915_READ16(MEMSWCTL);
5701
5702 /* Ack interrupts, disable EFC interrupt */
5703 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5704 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5705 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5706 I915_WRITE(DEIIR, DE_PCU_EVENT);
5707 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5708
5709 /* Go back to the starting frequency */
5710 ironlake_set_drps(dev, dev_priv->fstart);
5711 msleep(1);
5712 rgvswctl |= MEMCTL_CMD_STS;
5713 I915_WRITE(MEMSWCTL, rgvswctl);
5714 msleep(1);
5715
5716 }
5717
5718 static unsigned long intel_pxfreq(u32 vidfreq)
5719 {
5720 unsigned long freq;
5721 int div = (vidfreq & 0x3f0000) >> 16;
5722 int post = (vidfreq & 0x3000) >> 12;
5723 int pre = (vidfreq & 0x7);
5724
5725 if (!pre)
5726 return 0;
5727
5728 freq = ((div * 133333) / ((1<<post) * pre));
5729
5730 return freq;
5731 }
5732
5733 void intel_init_emon(struct drm_device *dev)
5734 {
5735 struct drm_i915_private *dev_priv = dev->dev_private;
5736 u32 lcfuse;
5737 u8 pxw[16];
5738 int i;
5739
5740 /* Disable to program */
5741 I915_WRITE(ECR, 0);
5742 POSTING_READ(ECR);
5743
5744 /* Program energy weights for various events */
5745 I915_WRITE(SDEW, 0x15040d00);
5746 I915_WRITE(CSIEW0, 0x007f0000);
5747 I915_WRITE(CSIEW1, 0x1e220004);
5748 I915_WRITE(CSIEW2, 0x04000004);
5749
5750 for (i = 0; i < 5; i++)
5751 I915_WRITE(PEW + (i * 4), 0);
5752 for (i = 0; i < 3; i++)
5753 I915_WRITE(DEW + (i * 4), 0);
5754
5755 /* Program P-state weights to account for frequency power adjustment */
5756 for (i = 0; i < 16; i++) {
5757 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5758 unsigned long freq = intel_pxfreq(pxvidfreq);
5759 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5760 PXVFREQ_PX_SHIFT;
5761 unsigned long val;
5762
5763 val = vid * vid;
5764 val *= (freq / 1000);
5765 val *= 255;
5766 val /= (127*127*900);
5767 if (val > 0xff)
5768 DRM_ERROR("bad pxval: %ld\n", val);
5769 pxw[i] = val;
5770 }
5771 /* Render standby states get 0 weight */
5772 pxw[14] = 0;
5773 pxw[15] = 0;
5774
5775 for (i = 0; i < 4; i++) {
5776 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5777 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5778 I915_WRITE(PXW + (i * 4), val);
5779 }
5780
5781 /* Adjust magic regs to magic values (more experimental results) */
5782 I915_WRITE(OGW0, 0);
5783 I915_WRITE(OGW1, 0);
5784 I915_WRITE(EG0, 0x00007f00);
5785 I915_WRITE(EG1, 0x0000000e);
5786 I915_WRITE(EG2, 0x000e0000);
5787 I915_WRITE(EG3, 0x68000300);
5788 I915_WRITE(EG4, 0x42000000);
5789 I915_WRITE(EG5, 0x00140031);
5790 I915_WRITE(EG6, 0);
5791 I915_WRITE(EG7, 0);
5792
5793 for (i = 0; i < 8; i++)
5794 I915_WRITE(PXWL + (i * 4), 0);
5795
5796 /* Enable PMON + select events */
5797 I915_WRITE(ECR, 0x80000019);
5798
5799 lcfuse = I915_READ(LCFUSE02);
5800
5801 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
5802 }
5803
5804 void intel_init_clock_gating(struct drm_device *dev)
5805 {
5806 struct drm_i915_private *dev_priv = dev->dev_private;
5807
5808 /*
5809 * Disable clock gating reported to work incorrectly according to the
5810 * specs, but enable as much else as we can.
5811 */
5812 if (HAS_PCH_SPLIT(dev)) {
5813 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5814
5815 if (IS_IRONLAKE(dev)) {
5816 /* Required for FBC */
5817 dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5818 /* Required for CxSR */
5819 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5820
5821 I915_WRITE(PCH_3DCGDIS0,
5822 MARIUNIT_CLOCK_GATE_DISABLE |
5823 SVSMUNIT_CLOCK_GATE_DISABLE);
5824 }
5825
5826 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5827
5828 /*
5829 * According to the spec the following bits should be set in
5830 * order to enable memory self-refresh
5831 * The bit 22/21 of 0x42004
5832 * The bit 5 of 0x42020
5833 * The bit 15 of 0x45000
5834 */
5835 if (IS_IRONLAKE(dev)) {
5836 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5837 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5838 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5839 I915_WRITE(ILK_DSPCLK_GATE,
5840 (I915_READ(ILK_DSPCLK_GATE) |
5841 ILK_DPARB_CLK_GATE));
5842 I915_WRITE(DISP_ARB_CTL,
5843 (I915_READ(DISP_ARB_CTL) |
5844 DISP_FBC_WM_DIS));
5845 I915_WRITE(WM3_LP_ILK, 0);
5846 I915_WRITE(WM2_LP_ILK, 0);
5847 I915_WRITE(WM1_LP_ILK, 0);
5848 }
5849 /*
5850 * Based on the document from hardware guys the following bits
5851 * should be set unconditionally in order to enable FBC.
5852 * The bit 22 of 0x42000
5853 * The bit 22 of 0x42004
5854 * The bit 7,8,9 of 0x42020.
5855 */
5856 if (IS_IRONLAKE_M(dev)) {
5857 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5858 I915_READ(ILK_DISPLAY_CHICKEN1) |
5859 ILK_FBCQ_DIS);
5860 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5861 I915_READ(ILK_DISPLAY_CHICKEN2) |
5862 ILK_DPARB_GATE);
5863 I915_WRITE(ILK_DSPCLK_GATE,
5864 I915_READ(ILK_DSPCLK_GATE) |
5865 ILK_DPFC_DIS1 |
5866 ILK_DPFC_DIS2 |
5867 ILK_CLK_FBC);
5868 }
5869 return;
5870 } else if (IS_G4X(dev)) {
5871 uint32_t dspclk_gate;
5872 I915_WRITE(RENCLK_GATE_D1, 0);
5873 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5874 GS_UNIT_CLOCK_GATE_DISABLE |
5875 CL_UNIT_CLOCK_GATE_DISABLE);
5876 I915_WRITE(RAMCLK_GATE_D, 0);
5877 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5878 OVRUNIT_CLOCK_GATE_DISABLE |
5879 OVCUNIT_CLOCK_GATE_DISABLE;
5880 if (IS_GM45(dev))
5881 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5882 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5883 } else if (IS_I965GM(dev)) {
5884 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5885 I915_WRITE(RENCLK_GATE_D2, 0);
5886 I915_WRITE(DSPCLK_GATE_D, 0);
5887 I915_WRITE(RAMCLK_GATE_D, 0);
5888 I915_WRITE16(DEUC, 0);
5889 } else if (IS_I965G(dev)) {
5890 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5891 I965_RCC_CLOCK_GATE_DISABLE |
5892 I965_RCPB_CLOCK_GATE_DISABLE |
5893 I965_ISC_CLOCK_GATE_DISABLE |
5894 I965_FBC_CLOCK_GATE_DISABLE);
5895 I915_WRITE(RENCLK_GATE_D2, 0);
5896 } else if (IS_I9XX(dev)) {
5897 u32 dstate = I915_READ(D_STATE);
5898
5899 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5900 DSTATE_DOT_CLOCK_GATING;
5901 I915_WRITE(D_STATE, dstate);
5902 } else if (IS_I85X(dev) || IS_I865G(dev)) {
5903 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5904 } else if (IS_I830(dev)) {
5905 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5906 }
5907
5908 /*
5909 * GPU can automatically power down the render unit if given a page
5910 * to save state.
5911 */
5912 if (IS_IRONLAKE_M(dev)) {
5913 if (dev_priv->renderctx == NULL)
5914 dev_priv->renderctx = intel_alloc_context_page(dev);
5915 if (dev_priv->renderctx) {
5916 struct drm_i915_gem_object *obj_priv;
5917 obj_priv = to_intel_bo(dev_priv->renderctx);
5918 if (obj_priv) {
5919 BEGIN_LP_RING(4);
5920 OUT_RING(MI_SET_CONTEXT);
5921 OUT_RING(obj_priv->gtt_offset |
5922 MI_MM_SPACE_GTT |
5923 MI_SAVE_EXT_STATE_EN |
5924 MI_RESTORE_EXT_STATE_EN |
5925 MI_RESTORE_INHIBIT);
5926 OUT_RING(MI_NOOP);
5927 OUT_RING(MI_FLUSH);
5928 ADVANCE_LP_RING();
5929 }
5930 } else
5931 DRM_DEBUG_KMS("Failed to allocate render context."
5932 "Disable RC6\n");
5933 }
5934
5935 if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5936 struct drm_i915_gem_object *obj_priv = NULL;
5937
5938 if (dev_priv->pwrctx) {
5939 obj_priv = to_intel_bo(dev_priv->pwrctx);
5940 } else {
5941 struct drm_gem_object *pwrctx;
5942
5943 pwrctx = intel_alloc_context_page(dev);
5944 if (pwrctx) {
5945 dev_priv->pwrctx = pwrctx;
5946 obj_priv = to_intel_bo(pwrctx);
5947 }
5948 }
5949
5950 if (obj_priv) {
5951 I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
5952 I915_WRITE(MCHBAR_RENDER_STANDBY,
5953 I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5954 }
5955 }
5956 }
5957
5958 /* Set up chip specific display functions */
5959 static void intel_init_display(struct drm_device *dev)
5960 {
5961 struct drm_i915_private *dev_priv = dev->dev_private;
5962
5963 /* We always want a DPMS function */
5964 if (HAS_PCH_SPLIT(dev))
5965 dev_priv->display.dpms = ironlake_crtc_dpms;
5966 else
5967 dev_priv->display.dpms = i9xx_crtc_dpms;
5968
5969 if (I915_HAS_FBC(dev)) {
5970 if (IS_IRONLAKE_M(dev)) {
5971 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5972 dev_priv->display.enable_fbc = ironlake_enable_fbc;
5973 dev_priv->display.disable_fbc = ironlake_disable_fbc;
5974 } else if (IS_GM45(dev)) {
5975 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5976 dev_priv->display.enable_fbc = g4x_enable_fbc;
5977 dev_priv->display.disable_fbc = g4x_disable_fbc;
5978 } else if (IS_I965GM(dev)) {
5979 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5980 dev_priv->display.enable_fbc = i8xx_enable_fbc;
5981 dev_priv->display.disable_fbc = i8xx_disable_fbc;
5982 }
5983 /* 855GM needs testing */
5984 }
5985
5986 /* Returns the core display clock speed */
5987 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
5988 dev_priv->display.get_display_clock_speed =
5989 i945_get_display_clock_speed;
5990 else if (IS_I915G(dev))
5991 dev_priv->display.get_display_clock_speed =
5992 i915_get_display_clock_speed;
5993 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
5994 dev_priv->display.get_display_clock_speed =
5995 i9xx_misc_get_display_clock_speed;
5996 else if (IS_I915GM(dev))
5997 dev_priv->display.get_display_clock_speed =
5998 i915gm_get_display_clock_speed;
5999 else if (IS_I865G(dev))
6000 dev_priv->display.get_display_clock_speed =
6001 i865_get_display_clock_speed;
6002 else if (IS_I85X(dev))
6003 dev_priv->display.get_display_clock_speed =
6004 i855_get_display_clock_speed;
6005 else /* 852, 830 */
6006 dev_priv->display.get_display_clock_speed =
6007 i830_get_display_clock_speed;
6008
6009 /* For FIFO watermark updates */
6010 if (HAS_PCH_SPLIT(dev)) {
6011 if (IS_IRONLAKE(dev)) {
6012 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
6013 dev_priv->display.update_wm = ironlake_update_wm;
6014 else {
6015 DRM_DEBUG_KMS("Failed to get proper latency. "
6016 "Disable CxSR\n");
6017 dev_priv->display.update_wm = NULL;
6018 }
6019 } else
6020 dev_priv->display.update_wm = NULL;
6021 } else if (IS_PINEVIEW(dev)) {
6022 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6023 dev_priv->is_ddr3,
6024 dev_priv->fsb_freq,
6025 dev_priv->mem_freq)) {
6026 DRM_INFO("failed to find known CxSR latency "
6027 "(found ddr%s fsb freq %d, mem freq %d), "
6028 "disabling CxSR\n",
6029 (dev_priv->is_ddr3 == 1) ? "3": "2",
6030 dev_priv->fsb_freq, dev_priv->mem_freq);
6031 /* Disable CxSR and never update its watermark again */
6032 pineview_disable_cxsr(dev);
6033 dev_priv->display.update_wm = NULL;
6034 } else
6035 dev_priv->display.update_wm = pineview_update_wm;
6036 } else if (IS_G4X(dev))
6037 dev_priv->display.update_wm = g4x_update_wm;
6038 else if (IS_I965G(dev))
6039 dev_priv->display.update_wm = i965_update_wm;
6040 else if (IS_I9XX(dev)) {
6041 dev_priv->display.update_wm = i9xx_update_wm;
6042 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6043 } else if (IS_I85X(dev)) {
6044 dev_priv->display.update_wm = i9xx_update_wm;
6045 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
6046 } else {
6047 dev_priv->display.update_wm = i830_update_wm;
6048 if (IS_845G(dev))
6049 dev_priv->display.get_fifo_size = i845_get_fifo_size;
6050 else
6051 dev_priv->display.get_fifo_size = i830_get_fifo_size;
6052 }
6053 }
6054
6055 /*
6056 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
6057 * resume, or other times. This quirk makes sure that's the case for
6058 * affected systems.
6059 */
6060 static void quirk_pipea_force (struct drm_device *dev)
6061 {
6062 struct drm_i915_private *dev_priv = dev->dev_private;
6063
6064 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
6065 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
6066 }
6067
6068 struct intel_quirk {
6069 int device;
6070 int subsystem_vendor;
6071 int subsystem_device;
6072 void (*hook)(struct drm_device *dev);
6073 };
6074
6075 struct intel_quirk intel_quirks[] = {
6076 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
6077 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
6078 /* HP Mini needs pipe A force quirk (LP: #322104) */
6079 { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
6080
6081 /* Thinkpad R31 needs pipe A force quirk */
6082 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
6083 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
6084 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
6085
6086 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
6087 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
6088 /* ThinkPad X40 needs pipe A force quirk */
6089
6090 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6091 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
6092
6093 /* 855 & before need to leave pipe A & dpll A up */
6094 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6095 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6096 };
6097
6098 static void intel_init_quirks(struct drm_device *dev)
6099 {
6100 struct pci_dev *d = dev->pdev;
6101 int i;
6102
6103 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
6104 struct intel_quirk *q = &intel_quirks[i];
6105
6106 if (d->device == q->device &&
6107 (d->subsystem_vendor == q->subsystem_vendor ||
6108 q->subsystem_vendor == PCI_ANY_ID) &&
6109 (d->subsystem_device == q->subsystem_device ||
6110 q->subsystem_device == PCI_ANY_ID))
6111 q->hook(dev);
6112 }
6113 }
6114
6115 /* Disable the VGA plane that we never use */
6116 static void i915_disable_vga(struct drm_device *dev)
6117 {
6118 struct drm_i915_private *dev_priv = dev->dev_private;
6119 u8 sr1;
6120 u32 vga_reg;
6121
6122 if (HAS_PCH_SPLIT(dev))
6123 vga_reg = CPU_VGACNTRL;
6124 else
6125 vga_reg = VGACNTRL;
6126
6127 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6128 outb(1, VGA_SR_INDEX);
6129 sr1 = inb(VGA_SR_DATA);
6130 outb(sr1 | 1<<5, VGA_SR_DATA);
6131 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6132 udelay(300);
6133
6134 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6135 POSTING_READ(vga_reg);
6136 }
6137
6138 void intel_modeset_init(struct drm_device *dev)
6139 {
6140 struct drm_i915_private *dev_priv = dev->dev_private;
6141 int i;
6142
6143 drm_mode_config_init(dev);
6144
6145 dev->mode_config.min_width = 0;
6146 dev->mode_config.min_height = 0;
6147
6148 dev->mode_config.funcs = (void *)&intel_mode_funcs;
6149
6150 intel_init_quirks(dev);
6151
6152 intel_init_display(dev);
6153
6154 if (IS_I965G(dev)) {
6155 dev->mode_config.max_width = 8192;
6156 dev->mode_config.max_height = 8192;
6157 } else if (IS_I9XX(dev)) {
6158 dev->mode_config.max_width = 4096;
6159 dev->mode_config.max_height = 4096;
6160 } else {
6161 dev->mode_config.max_width = 2048;
6162 dev->mode_config.max_height = 2048;
6163 }
6164
6165 /* set memory base */
6166 if (IS_I9XX(dev))
6167 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
6168 else
6169 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
6170
6171 if (IS_MOBILE(dev) || IS_I9XX(dev))
6172 dev_priv->num_pipe = 2;
6173 else
6174 dev_priv->num_pipe = 1;
6175 DRM_DEBUG_KMS("%d display pipe%s available.\n",
6176 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6177
6178 for (i = 0; i < dev_priv->num_pipe; i++) {
6179 intel_crtc_init(dev, i);
6180 }
6181
6182 intel_setup_outputs(dev);
6183
6184 intel_init_clock_gating(dev);
6185
6186 /* Just disable it once at startup */
6187 i915_disable_vga(dev);
6188
6189 if (IS_IRONLAKE_M(dev)) {
6190 ironlake_enable_drps(dev);
6191 intel_init_emon(dev);
6192 }
6193
6194 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6195 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6196 (unsigned long)dev);
6197
6198 intel_setup_overlay(dev);
6199 }
6200
6201 void intel_modeset_cleanup(struct drm_device *dev)
6202 {
6203 struct drm_i915_private *dev_priv = dev->dev_private;
6204 struct drm_crtc *crtc;
6205 struct intel_crtc *intel_crtc;
6206
6207 mutex_lock(&dev->struct_mutex);
6208
6209 drm_kms_helper_poll_fini(dev);
6210 intel_fbdev_fini(dev);
6211
6212 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6213 /* Skip inactive CRTCs */
6214 if (!crtc->fb)
6215 continue;
6216
6217 intel_crtc = to_intel_crtc(crtc);
6218 intel_increase_pllclock(crtc);
6219 }
6220
6221 if (dev_priv->display.disable_fbc)
6222 dev_priv->display.disable_fbc(dev);
6223
6224 if (dev_priv->renderctx) {
6225 struct drm_i915_gem_object *obj_priv;
6226
6227 obj_priv = to_intel_bo(dev_priv->renderctx);
6228 I915_WRITE(CCID, obj_priv->gtt_offset &~ CCID_EN);
6229 I915_READ(CCID);
6230 i915_gem_object_unpin(dev_priv->renderctx);
6231 drm_gem_object_unreference(dev_priv->renderctx);
6232 }
6233
6234 if (dev_priv->pwrctx) {
6235 struct drm_i915_gem_object *obj_priv;
6236
6237 obj_priv = to_intel_bo(dev_priv->pwrctx);
6238 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
6239 I915_READ(PWRCTXA);
6240 i915_gem_object_unpin(dev_priv->pwrctx);
6241 drm_gem_object_unreference(dev_priv->pwrctx);
6242 }
6243
6244 if (IS_IRONLAKE_M(dev))
6245 ironlake_disable_drps(dev);
6246
6247 mutex_unlock(&dev->struct_mutex);
6248
6249 /* Disable the irq before mode object teardown, for the irq might
6250 * enqueue unpin/hotplug work. */
6251 drm_irq_uninstall(dev);
6252 cancel_work_sync(&dev_priv->hotplug_work);
6253
6254 /* Shut off idle work before the crtcs get freed. */
6255 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6256 intel_crtc = to_intel_crtc(crtc);
6257 del_timer_sync(&intel_crtc->idle_timer);
6258 }
6259 del_timer_sync(&dev_priv->idle_timer);
6260 cancel_work_sync(&dev_priv->idle_work);
6261
6262 drm_mode_config_cleanup(dev);
6263 }
6264
6265 /*
6266 * Return which encoder is currently attached for connector.
6267 */
6268 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
6269 {
6270 return &intel_attached_encoder(connector)->base;
6271 }
6272
6273 void intel_connector_attach_encoder(struct intel_connector *connector,
6274 struct intel_encoder *encoder)
6275 {
6276 connector->encoder = encoder;
6277 drm_mode_connector_attach_encoder(&connector->base,
6278 &encoder->base);
6279 }
6280
6281 /*
6282 * set vga decode state - true == enable VGA decode
6283 */
6284 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6285 {
6286 struct drm_i915_private *dev_priv = dev->dev_private;
6287 u16 gmch_ctrl;
6288
6289 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6290 if (state)
6291 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6292 else
6293 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6294 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6295 return 0;
6296 }
Linux kernel - Deliverables
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